Add qemu 2.4.0

Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5
Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>

1144 files changed, 297111 insertions, 0 deletions

diff --git a/qemu/roms/u-boot/include/.gitignore b/qemu/roms/u-boot/include/.gitignore
new file mode 100644
index 000000000..bf142fc2f
--- /dev/null
+++ b/qemu/roms/u-boot/include/.gitignore
@@ -0,0 +1,5 @@
+/autoconf.mk*
+/bmp_logo.h
+/bmp_logo_data.h
+/config.h
+/config.mk
diff --git a/qemu/roms/u-boot/include/74xx_7xx.h b/qemu/roms/u-boot/include/74xx_7xx.h
new file mode 100644
index 000000000..3deeeeaa5
--- /dev/null
+++ b/qemu/roms/u-boot/include/74xx_7xx.h
@@ -0,0 +1,110 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber, Mission Critical Linux, Inc. <huber@mclx.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * 74xx_7xx.h
+ *
+ * 74xx/7xx specific definitions
+ */
+
+#ifndef __MPC74XX_H__
+#define __MPC74XX_H__
+
+/*----------------------------------------------------------------
+ * Exception offsets (PowerPC standard)
+ */
+#define EXC_OFF_SYS_RESET        0x0100      /* default system reset offset */
+#define _START_OFFSET		EXC_OFF_SYS_RESET
+
+/*----------------------------------------------------------------
+ * l2cr values
+ */
+#define l2cr		 1017
+
+#define L2CR_L2E         0x80000000 /* bit 0 - enable */
+#define L2CR_L2PE        0x40000000 /* bit 1 - data parity */
+#define L2CR_L2SIZ_2M    0x00000000 /* bits 2-3 - 2MB, MPC7400 only! */
+#define L2CR_L2SIZ_1M    0x30000000 /* ... 1MB */
+#define L2CR_L2SIZ_HM    0x20000000 /* ... 512K */
+#define L2CR_L2SIZ_QM    0x10000000 /* ... 256k */
+#define L2CR_L2CLK_1     0x02000000 /* bits 4-6 clock ratio div 1 */
+#define L2CR_L2CLK_1_5   0x04000000 /* bits 4-6 clock ratio div 1.5 */
+#define L2CR_L2CLK_2     0x08000000 /* bits 4-6 clock ratio div 2 */
+#define L2CR_L2CLK_2_5   0x0a000000 /* bits 4-6 clock ratio div 2.5 */
+#define L2CR_L2CLK_3     0x0c000000 /* bits 4-6 clock ratio div 3 */
+#define L2CR_L2CLK_3_5   0x06000000 /* bits 4-6 clock ratio div 3.5 */
+#define L2CR_L2CLK_4     0x0e000000 /* bits 4-6 clock ratio div 4 */
+#define L2CR_L2RAM_BURST 0x01000000 /* bits 7-8 - burst SRAM */
+#define L2CR_DO          0x00400000 /* bit 9 - enable caching of instr. in L2 */
+#define L2CR_L2I         0x00200000 /* bit 10 - global invalidate bit */
+#define L2CR_L2CTL       0x00100000 /* bit 11 - l2 ram control */
+#define L2CR_L2WT        0x00080000 /* bit 12 - l2 write-through */
+#define L2CR_TS          0x00040000 /* bit 13 - test support on */
+#define L2CR_TS_OFF      -L2CR_TS   /* bit 13 - test support off */
+#define L2CR_L2OH_5      0x00000000 /* bits 14-15 - output hold time = short */
+#define L2CR_L2OH_1      0x00010000 /* bits 14-15 - output hold time = medium */
+#define L2CR_L2OH_INV    0x00020000 /* bits 14-15 - output hold time = long */
+#define L2CR_L2IP        0x00000001 /* global invalidate in progress */
+
+#ifndef __ASSEMBLY__
+/* cpu ids we detect */
+typedef enum __cpu_t {
+	CPU_740, CPU_750,
+	CPU_740P, CPU_750P,
+	CPU_745, CPU_755,
+	CPU_750CX, CPU_750FX, CPU_750GX,
+	CPU_7400,
+	CPU_7410,
+	CPU_7447A, CPU_7448,
+	CPU_7450, CPU_7455, CPU_7457,
+	CPU_UNKNOWN} cpu_t;
+
+extern cpu_t get_cpu_type(void);
+
+#define l1icache_enable	icache_enable
+
+void l2cache_enable(void);
+void l1dcache_enable(void);
+
+static __inline__ unsigned long get_msr (void)
+{
+	unsigned long msr;
+	asm volatile("mfmsr %0" : "=r" (msr) :);
+	return msr;
+}
+
+static __inline__ void set_msr (unsigned long msr)
+{
+	asm volatile("mtmsr %0" : : "r" (msr));
+}
+
+static __inline__ unsigned long get_hid0 (void)
+{
+	unsigned long hid0;
+	asm volatile("mfspr %0, 1008" : "=r" (hid0) :);
+	return hid0;
+}
+
+static __inline__ unsigned long get_hid1 (void)
+{
+	unsigned long hid1;
+	asm volatile("mfspr %0, 1009" : "=r" (hid1) :);
+	return hid1;
+}
+
+static __inline__ void set_hid0 (unsigned long hid0)
+{
+	asm volatile("mtspr 1008, %0" : : "r" (hid0));
+}
+
+static __inline__ void set_hid1 (unsigned long hid1)
+{
+	asm volatile("mtspr 1009, %0" : : "r" (hid1));
+}
+
+#endif	/* __ASSEMBLY__ */
+#endif  /* __MPC74XX_H__ */
diff --git a/qemu/roms/u-boot/include/ACEX1K.h b/qemu/roms/u-boot/include/ACEX1K.h
new file mode 100644
index 000000000..3df605a43
--- /dev/null
+++ b/qemu/roms/u-boot/include/ACEX1K.h
@@ -0,0 +1,70 @@
+/*
+ * (C) Copyright 2003
+ * Steven Scholz, imc Measurement & Control, steven.scholz@imc-berlin.de
+ *
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ACEX1K_H_
+#define _ACEX1K_H_
+
+#include <altera.h>
+
+extern int ACEX1K_load(Altera_desc *desc, const void *image, size_t size);
+extern int ACEX1K_dump(Altera_desc *desc, const void *buf, size_t bsize);
+extern int ACEX1K_info(Altera_desc *desc);
+
+extern int CYC2_load(Altera_desc *desc, const void *image, size_t size);
+extern int CYC2_dump(Altera_desc *desc, const void *buf, size_t bsize);
+extern int CYC2_info(Altera_desc *desc);
+
+/* Slave Serial Implementation function table */
+typedef struct {
+	Altera_pre_fn		pre;
+	Altera_config_fn	config;
+	Altera_clk_fn		clk;
+	Altera_status_fn	status;
+	Altera_done_fn		done;
+	Altera_data_fn		data;
+	Altera_abort_fn		abort;
+	Altera_post_fn		post;
+} Altera_ACEX1K_Passive_Serial_fns;
+
+/* Slave Serial Implementation function table */
+typedef struct {
+	Altera_pre_fn		pre;
+	Altera_config_fn	config;
+	Altera_status_fn	status;
+	Altera_done_fn		done;
+	Altera_write_fn		write;
+	Altera_abort_fn		abort;
+	Altera_post_fn		post;
+} Altera_CYC2_Passive_Serial_fns;
+
+/* Device Image Sizes
+ *********************************************************************/
+/* ACEX1K */
+/* FIXME: Which size do we mean?
+ * Datasheet says 1337000/8=167125Bytes,
+ * Filesize of an *.rbf file is 166965 Bytes
+ */
+#if 0
+#define Altera_EP1K100_SIZE	1337000/8	/* 167125 Bytes */
+#endif
+#define Altera_EP1K100_SIZE	(166965*8)
+
+#define Altera_EP2C8_SIZE	247942
+#define Altera_EP2C20_SIZE	586562
+#define Altera_EP2C35_SIZE	883905
+#define Altera_EP3C5_SIZE	368011		/* .rbf size in bytes */
+
+/* Descriptor Macros
+ *********************************************************************/
+/* ACEX1K devices */
+#define Altera_EP1K100_DESC(iface, fn_table, cookie) \
+{ Altera_ACEX1K, iface, Altera_EP1K100_SIZE, fn_table, cookie }
+
+#endif /* _ACEX1K_H_ */
diff --git a/qemu/roms/u-boot/include/MCD_dma.h b/qemu/roms/u-boot/include/MCD_dma.h
new file mode 100644
index 000000000..d7a419135
--- /dev/null
+++ b/qemu/roms/u-boot/include/MCD_dma.h
@@ -0,0 +1,370 @@
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _MCD_API_H
+#define _MCD_API_H
+
+/* Turn Execution Unit tasks ON (#define) or OFF (#undef) */
+#undef MCD_INCLUDE_EU
+
+/* Number of DMA channels */
+#define NCHANNELS	16
+
+/* Total number of variants */
+#ifdef MCD_INCLUDE_EU
+#define NUMOFVARIANTS	6
+#else
+#define NUMOFVARIANTS	4
+#endif
+
+/* Define sizes of the various tables */
+#define TASK_TABLE_SIZE		(NCHANNELS*32)
+#define VAR_TAB_SIZE		(128)
+#define CONTEXT_SAVE_SIZE	(128)
+#define FUNCDESC_TAB_SIZE	(256)
+
+#ifdef MCD_INCLUDE_EU
+#define FUNCDESC_TAB_NUM	16
+#else
+#define FUNCDESC_TAB_NUM	1
+#endif
+
+#ifndef DEFINESONLY
+
+/* Portability typedefs */
+#if 1
+#include "common.h"
+#else
+#ifndef s32
+typedef int s32;
+#endif
+#ifndef u32
+typedef unsigned int u32;
+#endif
+#ifndef s16
+typedef short s16;
+#endif
+#ifndef u16
+typedef unsigned short u16;
+#endif
+#ifndef s8
+typedef char s8;
+#endif
+#ifndef u8
+typedef unsigned char u8;
+#endif
+#endif
+
+/*
+ * These structures represent the internal registers of the
+ * multi-channel DMA
+ */
+struct dmaRegs_s {
+	u32 taskbar;		/* task table base address */
+	u32 currPtr;
+	u32 endPtr;
+	u32 varTablePtr;
+	u16 dma_rsvd0;
+	u16 ptdControl;		/* ptd control */
+	u32 intPending;		/* interrupt pending */
+	u32 intMask;		/* interrupt mask */
+	u16 taskControl[16];	/* task control */
+	u8 priority[32];	/* priority */
+	u32 initiatorMux;	/* initiator mux control */
+	u32 taskSize0;		/* task size control 0. */
+	u32 taskSize1;		/* task size control 1. */
+	u32 dma_rsvd1;		/* reserved */
+	u32 dma_rsvd2;		/* reserved */
+	u32 debugComp1;		/* debug comparator 1 */
+	u32 debugComp2;		/* debug comparator 2 */
+	u32 debugControl;	/* debug control */
+	u32 debugStatus;	/* debug status */
+	u32 ptdDebug;		/* priority task decode debug */
+	u32 dma_rsvd3[31];	/* reserved */
+};
+typedef volatile struct dmaRegs_s dmaRegs;
+
+#endif
+
+/* PTD contrl reg bits */
+#define PTD_CTL_TSK_PRI		0x8000
+#define PTD_CTL_COMM_PREFETCH	0x0001
+
+/* Task Control reg bits and field masks */
+#define TASK_CTL_EN		0x8000
+#define TASK_CTL_VALID		0x4000
+#define TASK_CTL_ALWAYS		0x2000
+#define TASK_CTL_INIT_MASK	0x1f00
+#define TASK_CTL_ASTRT		0x0080
+#define TASK_CTL_HIPRITSKEN	0x0040
+#define TASK_CTL_HLDINITNUM	0x0020
+#define TASK_CTL_ASTSKNUM_MASK	0x000f
+
+/* Priority reg bits and field masks */
+#define PRIORITY_HLD		0x80
+#define PRIORITY_PRI_MASK	0x07
+
+/* Debug Control reg bits and field masks */
+#define DBG_CTL_BLOCK_TASKS_MASK	0xffff0000
+#define DBG_CTL_AUTO_ARM		0x00008000
+#define DBG_CTL_BREAK			0x00004000
+#define DBG_CTL_COMP1_TYP_MASK		0x00003800
+#define DBG_CTL_COMP2_TYP_MASK		0x00000070
+#define DBG_CTL_EXT_BREAK		0x00000004
+#define DBG_CTL_INT_BREAK		0x00000002
+
+/*
+ * PTD Debug reg selector addresses
+ * This reg must be written with a value to show the contents of
+ * one of the desired internal register.
+ */
+#define PTD_DBG_REQ		0x00	/* shows the state of 31 initiators */
+#define PTD_DBG_TSK_VLD_INIT	0x01	/* shows which 16 tasks are valid and
+					   have initiators asserted */
+
+/* General return values */
+#define MCD_OK			0
+#define MCD_ERROR		-1
+#define MCD_TABLE_UNALIGNED	-2
+#define MCD_CHANNEL_INVALID	-3
+
+/* MCD_initDma input flags */
+#define MCD_RELOC_TASKS		0x00000001
+#define MCD_NO_RELOC_TASKS	0x00000000
+#define MCD_COMM_PREFETCH_EN	0x00000002	/* MCF547x/548x ONLY */
+
+/*
+ * MCD_dmaStatus Status Values for each channel:
+ * MCD_NO_DMA	- No DMA has been requested since reset
+ * MCD_IDLE	- DMA active, but the initiator is currently inactive
+ * MCD_RUNNING	- DMA active, and the initiator is currently active
+ * MCD_PAUSED	- DMA active but it is currently paused
+ * MCD_HALTED	- the most recent DMA has been killed with MCD_killTask()
+ * MCD_DONE	- the most recent DMA has completed
+ */
+#define MCD_NO_DMA		1
+#define MCD_IDLE		2
+#define MCD_RUNNING		3
+#define MCD_PAUSED		4
+#define MCD_HALTED		5
+#define MCD_DONE		6
+
+/* MCD_startDma parameter defines */
+
+/* Constants for the funcDesc parameter */
+/*
+ * MCD_NO_BYTE_SWAP	- to disable byte swapping
+ * MCD_BYTE_REVERSE	- to reverse the bytes of each u32 of the DMAed data
+ * MCD_U16_REVERSE	- to reverse the 16-bit halves of each 32-bit data
+ *			  value being DMAed
+ * MCD_U16_BYTE_REVERSE	- to reverse the byte halves of each 16-bit half of
+ *			  each 32-bit data value DMAed
+ * MCD_NO_BIT_REV	- do not reverse the bits of each byte DMAed
+ * MCD_BIT_REV		- reverse the bits of each byte DMAed
+ * MCD_CRC16		- to perform CRC-16 on DMAed data
+ * MCD_CRCCCITT		- to perform CRC-CCITT on DMAed data
+ * MCD_CRC32		- to perform CRC-32 on DMAed data
+ * MCD_CSUMINET		- to perform internet checksums on DMAed data
+ * MCD_NO_CSUM		- to perform no checksumming
+ */
+#define MCD_NO_BYTE_SWAP	0x00045670
+#define MCD_BYTE_REVERSE	0x00076540
+#define MCD_U16_REVERSE		0x00067450
+#define MCD_U16_BYTE_REVERSE	0x00054760
+#define MCD_NO_BIT_REV		0x00000000
+#define MCD_BIT_REV		0x00088880
+/* CRCing: */
+#define MCD_CRC16		0xc0100000
+#define MCD_CRCCCITT		0xc0200000
+#define MCD_CRC32		0xc0300000
+#define MCD_CSUMINET		0xc0400000
+#define MCD_NO_CSUM		0xa0000000
+
+#define MCD_FUNC_NOEU1		(MCD_NO_BYTE_SWAP | MCD_NO_BIT_REV | \
+				 MCD_NO_CSUM)
+#define MCD_FUNC_NOEU2		(MCD_NO_BYTE_SWAP | MCD_NO_CSUM)
+
+/* Constants for the flags parameter */
+#define MCD_TT_FLAGS_RL		0x00000001	/* Read line */
+#define MCD_TT_FLAGS_CW		0x00000002	/* Combine Writes */
+#define MCD_TT_FLAGS_SP		0x00000004	/* MCF547x/548x ONLY  */
+#define MCD_TT_FLAGS_MASK	0x000000ff
+#define MCD_TT_FLAGS_DEF	(MCD_TT_FLAGS_RL | MCD_TT_FLAGS_CW)
+
+#define MCD_SINGLE_DMA		0x00000100	/* Unchained DMA */
+#define MCD_CHAIN_DMA		/* TBD */
+#define MCD_EU_DMA		/* TBD */
+#define MCD_FECTX_DMA		0x00001000	/* FEC TX ring DMA */
+#define MCD_FECRX_DMA		0x00002000	/* FEC RX ring DMA */
+
+/* these flags are valid for MCD_startDma and the chained buffer descriptors */
+/*
+ * MCD_BUF_READY	- indicates that this buf is now under the DMA's ctrl
+ * MCD_WRAP		- to tell the FEC Dmas to wrap to the first BD
+ * MCD_INTERRUPT	- to generate an interrupt after completion of the DMA
+ * MCD_END_FRAME	- tell the DMA to end the frame when transferring
+ *			  last byte of data in buffer
+ * MCD_CRC_RESTART	- to empty out the accumulated checksum prior to
+ *			  performing the DMA
+ */
+#define MCD_BUF_READY		0x80000000
+#define MCD_WRAP		0x20000000
+#define MCD_INTERRUPT		0x10000000
+#define MCD_END_FRAME		0x08000000
+#define MCD_CRC_RESTART		0x40000000
+
+/* Defines for the FEC buffer descriptor control/status word*/
+#define MCD_FEC_BUF_READY	0x8000
+#define MCD_FEC_WRAP		0x2000
+#define MCD_FEC_INTERRUPT	0x1000
+#define MCD_FEC_END_FRAME	0x0800
+
+/* Defines for general intuitiveness */
+
+#define MCD_TRUE		1
+#define MCD_FALSE		0
+
+/* Three different cases for destination and source. */
+#define MINUS1			-1
+#define ZERO			0
+#define PLUS1			1
+
+#ifndef DEFINESONLY
+
+/* Task Table Entry struct*/
+typedef struct {
+	u32 TDTstart;		/* task descriptor table start */
+	u32 TDTend;		/* task descriptor table end */
+	u32 varTab;		/* variable table start */
+	u32 FDTandFlags;	/* function descriptor table start & flags */
+	volatile u32 descAddrAndStatus;
+	volatile u32 modifiedVarTab;
+	u32 contextSaveSpace;	/* context save space start */
+	u32 literalBases;
+} TaskTableEntry;
+
+/* Chained buffer descriptor:
+ * flags	- flags describing the DMA
+ * csumResult	- checksum performed since last checksum reset
+ * srcAddr	- the address to move data from
+ * destAddr	- the address to move data to
+ * lastDestAddr	- the last address written to
+ * dmaSize	- the no of bytes to xfer independent of the xfer sz
+ * next		- next buffer descriptor in chain
+ * info		- private info about this descriptor;  DMA does not affect it
+ */
+typedef volatile struct MCD_bufDesc_struct MCD_bufDesc;
+struct MCD_bufDesc_struct {
+	u32 flags;
+	u32 csumResult;
+	s8 *srcAddr;
+	s8 *destAddr;
+	s8 *lastDestAddr;
+	u32 dmaSize;
+	MCD_bufDesc *next;
+	u32 info;
+};
+
+/* Progress Query struct:
+ * lastSrcAddr	- the most-recent or last, post-increment source address
+ * lastDestAddr	- the most-recent or last, post-increment destination address
+ * dmaSize	- the amount of data transferred for the current buffer
+ * currBufDesc	- pointer to the current buffer descriptor being DMAed
+ */
+
+typedef volatile struct MCD_XferProg_struct {
+	s8 *lastSrcAddr;
+	s8 *lastDestAddr;
+	u32 dmaSize;
+	MCD_bufDesc *currBufDesc;
+} MCD_XferProg;
+
+/* FEC buffer descriptor */
+typedef volatile struct MCD_bufDescFec_struct {
+	u16 statCtrl;
+	u16 length;
+	u32 dataPointer;
+} MCD_bufDescFec;
+
+/*************************************************************************/
+/* API function Prototypes  - see MCD_dmaApi.c for further notes */
+
+/* MCD_startDma starts a particular kind of DMA:
+ * srcAddr	- the channel on which to run the DMA
+ * srcIncr	- the address to move data from, or buffer-descriptor address
+ * destAddr	- the amount to increment the source address per transfer
+ * destIncr	- the address to move data to
+ * dmaSize	- the amount to increment the destination address per transfer
+ * xferSize	- the number bytes in of each data movement (1, 2, or 4)
+ * initiator	- what device initiates the DMA
+ * priority	- priority of the DMA
+ * flags	- flags describing the DMA
+ * funcDesc	- description of byte swapping, bit swapping, and CRC actions
+ */
+int MCD_startDma(int channel, s8 * srcAddr, s16 srcIncr, s8 * destAddr,
+		 s16 destIncr, u32 dmaSize, u32 xferSize, u32 initiator,
+		 int priority, u32 flags, u32 funcDesc);
+
+/*
+ * MCD_initDma() initializes the DMA API by setting up a pointer to the DMA
+ * registers, relocating and creating the appropriate task structures, and
+ * setting up some global settings
+ */
+int MCD_initDma(dmaRegs * sDmaBarAddr, void *taskTableDest, u32 flags);
+
+/* MCD_dmaStatus() returns the status of the DMA on the requested channel. */
+int MCD_dmaStatus(int channel);
+
+/* MCD_XferProgrQuery() returns progress of DMA on requested channel */
+int MCD_XferProgrQuery(int channel, MCD_XferProg * progRep);
+
+/*
+ * MCD_killDma() halts the DMA on the requested channel, without any
+ * intention of resuming the DMA.
+ */
+int MCD_killDma(int channel);
+
+/*
+ * MCD_continDma() continues a DMA which as stopped due to encountering an
+ * unready buffer descriptor.
+ */
+int MCD_continDma(int channel);
+
+/*
+ * MCD_pauseDma() pauses the DMA on the given channel ( if any DMA is
+ * running on that channel).
+ */
+int MCD_pauseDma(int channel);
+
+/*
+ * MCD_resumeDma() resumes the DMA on a given channel (if any DMA is
+ * running on that channel).
+ */
+int MCD_resumeDma(int channel);
+
+/* MCD_csumQuery provides the checksum/CRC after performing a non-chained DMA */
+int MCD_csumQuery(int channel, u32 * csum);
+
+/*
+ * MCD_getCodeSize provides the packed size required by the microcoded task
+ * and structures.
+ */
+int MCD_getCodeSize(void);
+
+/*
+ * MCD_getVersion provides a pointer to a version string and returns a
+ * version number.
+ */
+int MCD_getVersion(char **longVersion);
+
+/* macro for setting a location in the variable table */
+#define MCD_SET_VAR(taskTab,idx,value) ((u32 *)(taskTab)->varTab)[idx] = value
+/* Note that MCD_SET_VAR() is invoked many times in firing up a DMA function,
+   so I'm avoiding surrounding it with "do {} while(0)" */
+
+#endif				/* DEFINESONLY */
+
+#endif				/* _MCD_API_H */
diff --git a/qemu/roms/u-boot/include/MCD_progCheck.h b/qemu/roms/u-boot/include/MCD_progCheck.h
new file mode 100644
index 000000000..faccdbba2
--- /dev/null
+++ b/qemu/roms/u-boot/include/MCD_progCheck.h
@@ -0,0 +1,11 @@
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+ /* This file is autogenerated. Do not change */
+#define CURRBD		4
+#define DCOUNT		6
+#define DESTPTR		5
+#define SRCPTR		7
diff --git a/qemu/roms/u-boot/include/MCD_tasksInit.h b/qemu/roms/u-boot/include/MCD_tasksInit.h
new file mode 100644
index 000000000..a05f30514
--- /dev/null
+++ b/qemu/roms/u-boot/include/MCD_tasksInit.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef MCD_TSK_INIT_H
+#define MCD_TSK_INIT_H 1
+
+/*
+ * Do not edit!
+ */
+
+/* Task 0 */
+void MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr,
+			   int xferSize, short xferSizeIncr, int *cSave,
+			   volatile TaskTableEntry * taskTable, int channel);
+
+/* Task 1 */
+void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr,
+			    short destIncr, int dmaSize, short xferSizeIncr,
+			    int flags, int *currBD, int *cSave,
+			    volatile TaskTableEntry * taskTable, int channel);
+
+/* Task 2 */
+void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr,
+			 int xferSize, short xferSizeIncr, int *cSave,
+			 volatile TaskTableEntry * taskTable, int channel);
+
+/* Task 3 */
+void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr,
+			  short destIncr, int dmaSize, short xferSizeIncr,
+			  int flags, int *currBD, int *cSave,
+			  volatile TaskTableEntry * taskTable, int channel);
+
+/* Task 4 */
+void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr,
+			 volatile TaskTableEntry * taskTable, int channel);
+
+/* Task 5 */
+void MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr,
+			  volatile TaskTableEntry * taskTable, int channel);
+
+#endif				/* MCD_TSK_INIT_H */
diff --git a/qemu/roms/u-boot/include/SA-1100.h b/qemu/roms/u-boot/include/SA-1100.h
new file mode 100644
index 000000000..7589df238
--- /dev/null
+++ b/qemu/roms/u-boot/include/SA-1100.h
@@ -0,0 +1,2833 @@
+/*
+ *	FILE		SA-1100.h
+ *
+ *	Version		1.2
+ *	Author		Copyright (c) Marc A. Viredaz, 1998
+ *			DEC Western Research Laboratory, Palo Alto, CA
+ *	Date		January 1998 (April 1997)
+ *	System		StrongARM SA-1100
+ *	Language	C or ARM Assembly
+ *	Purpose		Definition of constants related to the StrongARM
+ *			SA-1100 microprocessor (Advanced RISC Machine (ARM)
+ *			architecture version 4). This file is based on the
+ *			StrongARM SA-1100 data sheet version 2.2.
+ *
+ *			Language-specific definitions are selected by the
+ *			macro "LANGUAGE", which should be defined as either
+ *			"C" (default) or "Assembly".
+ */
+
+
+#ifndef LANGUAGE
+# ifdef __ASSEMBLY__
+#  define LANGUAGE Assembly
+# else
+#  define LANGUAGE C
+# endif
+#endif
+
+#ifndef io_p2v
+#define io_p2v(PhAdd)	(PhAdd)
+#endif
+
+#include <asm/arch-sa1100/bitfield.h>
+
+#define C		0
+#define Assembly	1
+
+
+#if LANGUAGE == C
+typedef unsigned short	Word16 ;
+typedef unsigned int	Word32 ;
+typedef Word32		Word ;
+typedef Word		Quad [4] ;
+typedef void		*Address ;
+typedef void		(*ExcpHndlr) (void) ;
+#endif /* LANGUAGE == C */
+
+
+/*
+ * Memory
+ */
+
+#define MemBnkSp	0x08000000	/* Memory Bank Space [byte]	   */
+
+#define StMemBnkSp	MemBnkSp	/* Static Memory Bank Space [byte] */
+#define StMemBnk0Sp	StMemBnkSp	/* Static Memory Bank 0 Space	   */
+					/* [byte]			   */
+#define StMemBnk1Sp	StMemBnkSp	/* Static Memory Bank 1 Space	   */
+					/* [byte]			   */
+#define StMemBnk2Sp	StMemBnkSp	/* Static Memory Bank 2 Space	   */
+					/* [byte]			   */
+#define StMemBnk3Sp	StMemBnkSp	/* Static Memory Bank 3 Space	   */
+					/* [byte]			   */
+
+#define DRAMBnkSp	MemBnkSp	/* DRAM Bank Space [byte]	   */
+#define DRAMBnk0Sp	DRAMBnkSp	/* DRAM Bank 0 Space [byte]	   */
+#define DRAMBnk1Sp	DRAMBnkSp	/* DRAM Bank 1 Space [byte]	   */
+#define DRAMBnk2Sp	DRAMBnkSp	/* DRAM Bank 2 Space [byte]	   */
+#define DRAMBnk3Sp	DRAMBnkSp	/* DRAM Bank 3 Space [byte]	   */
+
+#define ZeroMemSp	MemBnkSp	/* Zero Memory bank Space [byte]   */
+
+#define _StMemBnk(Nb)			/* Static Memory Bank [0..3]	   */ \
+			(0x00000000 + (Nb)*StMemBnkSp)
+#define _StMemBnk0	_StMemBnk (0)	/* Static Memory Bank 0		   */
+#define _StMemBnk1	_StMemBnk (1)	/* Static Memory Bank 1		   */
+#define _StMemBnk2	_StMemBnk (2)	/* Static Memory Bank 2		   */
+#define _StMemBnk3	_StMemBnk (3)	/* Static Memory Bank 3		   */
+
+#if LANGUAGE == C
+typedef Quad		StMemBnkType [StMemBnkSp/sizeof (Quad)] ;
+#define StMemBnk			/* Static Memory Bank [0..3]	   */ \
+			((StMemBnkType *) io_p2v (_StMemBnk (0)))
+#define StMemBnk0	(StMemBnk [0])	/* Static Memory Bank 0		   */
+#define StMemBnk1	(StMemBnk [1])	/* Static Memory Bank 1		   */
+#define StMemBnk2	(StMemBnk [2])	/* Static Memory Bank 2		   */
+#define StMemBnk3	(StMemBnk [3])	/* Static Memory Bank 3		   */
+#endif /* LANGUAGE == C */
+
+#define _DRAMBnk(Nb)			/* DRAM Bank [0..3]		   */ \
+			(0xC0000000 + (Nb)*DRAMBnkSp)
+#define _DRAMBnk0	_DRAMBnk (0)	/* DRAM Bank 0			   */
+#define _DRAMBnk1	_DRAMBnk (1)	/* DRAM Bank 1			   */
+#define _DRAMBnk2	_DRAMBnk (2)	/* DRAM Bank 2			   */
+#define _DRAMBnk3	_DRAMBnk (3)	/* DRAM Bank 3			   */
+
+#if LANGUAGE == C
+typedef Quad		DRAMBnkType [DRAMBnkSp/sizeof (Quad)] ;
+#define DRAMBnk				/* DRAM Bank [0..3]		   */ \
+			((DRAMBnkType *) io_p2v (_DRAMBnk (0)))
+#define DRAMBnk0	(DRAMBnk [0])	/* DRAM Bank 0			   */
+#define DRAMBnk1	(DRAMBnk [1])	/* DRAM Bank 1			   */
+#define DRAMBnk2	(DRAMBnk [2])	/* DRAM Bank 2			   */
+#define DRAMBnk3	(DRAMBnk [3])	/* DRAM Bank 3			   */
+#endif /* LANGUAGE == C */
+
+#define _ZeroMem	0xE0000000	/* Zero Memory bank		   */
+
+#if LANGUAGE == C
+typedef Quad		ZeroMemType [ZeroMemSp/sizeof (Quad)] ;
+#define ZeroMem				/* Zero Memory bank		   */ \
+			(*((ZeroMemType *) io_p2v (_ZeroMem)))
+#endif /* LANGUAGE == C */
+
+
+/*
+ * Personal Computer Memory Card International Association (PCMCIA) sockets
+ */
+
+#define PCMCIAPrtSp	0x04000000	/* PCMCIA Partition Space [byte]   */
+#define PCMCIASp	(4*PCMCIAPrtSp)	/* PCMCIA Space [byte]		   */
+#define PCMCIAIOSp	PCMCIAPrtSp	/* PCMCIA I/O Space [byte]	   */
+#define PCMCIAAttrSp	PCMCIAPrtSp	/* PCMCIA Attribute Space [byte]   */
+#define PCMCIAMemSp	PCMCIAPrtSp	/* PCMCIA Memory Space [byte]	   */
+
+#define PCMCIA0Sp	PCMCIASp	/* PCMCIA 0 Space [byte]	   */
+#define PCMCIA0IOSp	PCMCIAIOSp	/* PCMCIA 0 I/O Space [byte]	   */
+#define PCMCIA0AttrSp	PCMCIAAttrSp	/* PCMCIA 0 Attribute Space [byte] */
+#define PCMCIA0MemSp	PCMCIAMemSp	/* PCMCIA 0 Memory Space [byte]    */
+
+#define PCMCIA1Sp	PCMCIASp	/* PCMCIA 1 Space [byte]	   */
+#define PCMCIA1IOSp	PCMCIAIOSp	/* PCMCIA 1 I/O Space [byte]	   */
+#define PCMCIA1AttrSp	PCMCIAAttrSp	/* PCMCIA 1 Attribute Space [byte] */
+#define PCMCIA1MemSp	PCMCIAMemSp	/* PCMCIA 1 Memory Space [byte]    */
+
+#define _PCMCIA(Nb)			/* PCMCIA [0..1]		   */ \
+			(0x20000000 + (Nb)*PCMCIASp)
+#define _PCMCIAIO(Nb)	_PCMCIA (Nb)	/* PCMCIA I/O [0..1]		   */
+#define _PCMCIAAttr(Nb)			/* PCMCIA Attribute [0..1]	   */ \
+			(_PCMCIA (Nb) + 2*PCMCIAPrtSp)
+#define _PCMCIAMem(Nb)			/* PCMCIA Memory [0..1]		   */ \
+			(_PCMCIA (Nb) + 3*PCMCIAPrtSp)
+
+#define _PCMCIA0	_PCMCIA (0)	/* PCMCIA 0			   */
+#define _PCMCIA0IO	_PCMCIAIO (0)	/* PCMCIA 0 I/O			   */
+#define _PCMCIA0Attr	_PCMCIAAttr (0)	/* PCMCIA 0 Attribute		   */
+#define _PCMCIA0Mem	_PCMCIAMem (0)	/* PCMCIA 0 Memory		   */
+
+#define _PCMCIA1	_PCMCIA (1)	/* PCMCIA 1			   */
+#define _PCMCIA1IO	_PCMCIAIO (1)	/* PCMCIA 1 I/O			   */
+#define _PCMCIA1Attr	_PCMCIAAttr (1)	/* PCMCIA 1 Attribute		   */
+#define _PCMCIA1Mem	_PCMCIAMem (1)	/* PCMCIA 1 Memory		   */
+
+#if LANGUAGE == C
+
+typedef Quad		PCMCIAPrtType [PCMCIAPrtSp/sizeof (Quad)] ;
+typedef PCMCIAPrtType	PCMCIAType [PCMCIASp/PCMCIAPrtSp] ;
+
+#define PCMCIA0				/* PCMCIA 0			   */ \
+			(*((PCMCIAType *) io_p2v (_PCMCIA0)))
+#define PCMCIA0IO			/* PCMCIA 0 I/O			   */ \
+			(*((PCMCIAPrtType *) io_p2v (_PCMCIA0IO)))
+#define PCMCIA0Attr			/* PCMCIA 0 Attribute		   */ \
+			(*((PCMCIAPrtType *) io_p2v (_PCMCIA0Attr)))
+#define PCMCIA0Mem			/* PCMCIA 0 Memory		   */ \
+			(*((PCMCIAPrtType *) io_p2v (_PCMCIA0Mem)))
+
+#define PCMCIA1				/* PCMCIA 1			   */ \
+			(*((PCMCIAType *) io_p2v (_PCMCIA1)))
+#define PCMCIA1IO			/* PCMCIA 1 I/O			   */ \
+			(*((PCMCIAPrtType *) io_p2v (_PCMCIA1IO)))
+#define PCMCIA1Attr			/* PCMCIA 1 Attribute		   */ \
+			(*((PCMCIAPrtType *) io_p2v (_PCMCIA1Attr)))
+#define PCMCIA1Mem			/* PCMCIA 1 Memory		   */ \
+			(*((PCMCIAPrtType *) io_p2v (_PCMCIA1Mem)))
+
+#endif /* LANGUAGE == C */
+
+
+/*
+ * Universal Serial Bus (USB) Device Controller (UDC) control registers
+ *
+ * Registers
+ *    Ser0UDCCR		Serial port 0 Universal Serial Bus (USB) Device
+ *			Controller (UDC) Control Register (read/write).
+ *    Ser0UDCAR		Serial port 0 Universal Serial Bus (USB) Device
+ *			Controller (UDC) Address Register (read/write).
+ *    Ser0UDCOMP	Serial port 0 Universal Serial Bus (USB) Device
+ *			Controller (UDC) Output Maximum Packet size register
+ *			(read/write).
+ *    Ser0UDCIMP	Serial port 0 Universal Serial Bus (USB) Device
+ *			Controller (UDC) Input Maximum Packet size register
+ *			(read/write).
+ *    Ser0UDCCS0	Serial port 0 Universal Serial Bus (USB) Device
+ *			Controller (UDC) Control/Status register end-point 0
+ *			(read/write).
+ *    Ser0UDCCS1	Serial port 0 Universal Serial Bus (USB) Device
+ *			Controller (UDC) Control/Status register end-point 1
+ *			(output, read/write).
+ *    Ser0UDCCS2	Serial port 0 Universal Serial Bus (USB) Device
+ *			Controller (UDC) Control/Status register end-point 2
+ *			(input, read/write).
+ *    Ser0UDCD0		Serial port 0 Universal Serial Bus (USB) Device
+ *			Controller (UDC) Data register end-point 0
+ *			(read/write).
+ *    Ser0UDCWC		Serial port 0 Universal Serial Bus (USB) Device
+ *			Controller (UDC) Write Count register end-point 0
+ *			(read).
+ *    Ser0UDCDR		Serial port 0 Universal Serial Bus (USB) Device
+ *			Controller (UDC) Data Register (read/write).
+ *    Ser0UDCSR		Serial port 0 Universal Serial Bus (USB) Device
+ *			Controller (UDC) Status Register (read/write).
+ */
+
+#define _Ser0UDCCR	0x80000000	/* Ser. port 0 UDC Control Reg.    */
+#define _Ser0UDCAR	0x80000004	/* Ser. port 0 UDC Address Reg.    */
+#define _Ser0UDCOMP	0x80000008	/* Ser. port 0 UDC Output Maximum  */
+					/* Packet size reg.		   */
+#define _Ser0UDCIMP	0x8000000C	/* Ser. port 0 UDC Input Maximum   */
+					/* Packet size reg.		   */
+#define _Ser0UDCCS0	0x80000010	/* Ser. port 0 UDC Control/Status  */
+					/* reg. end-point 0		   */
+#define _Ser0UDCCS1	0x80000014	/* Ser. port 0 UDC Control/Status  */
+					/* reg. end-point 1 (output)	   */
+#define _Ser0UDCCS2	0x80000018	/* Ser. port 0 UDC Control/Status  */
+					/* reg. end-point 2 (input)	   */
+#define _Ser0UDCD0	0x8000001C	/* Ser. port 0 UDC Data reg.	   */
+					/* end-point 0			   */
+#define _Ser0UDCWC	0x80000020	/* Ser. port 0 UDC Write Count	   */
+					/* reg. end-point 0		   */
+#define _Ser0UDCDR	0x80000028	/* Ser. port 0 UDC Data Reg.	   */
+#define _Ser0UDCSR	0x80000030	/* Ser. port 0 UDC Status Reg.	   */
+
+#if LANGUAGE == C
+#define Ser0UDCCR			/* Ser. port 0 UDC Control Reg.    */ \
+			(*((volatile Word *) io_p2v (_Ser0UDCCR)))
+#define Ser0UDCAR			/* Ser. port 0 UDC Address Reg.    */ \
+			(*((volatile Word *) io_p2v (_Ser0UDCAR)))
+#define Ser0UDCOMP			/* Ser. port 0 UDC Output Maximum  */ \
+					/* Packet size reg.		   */ \
+			(*((volatile Word *) io_p2v (_Ser0UDCOMP)))
+#define Ser0UDCIMP			/* Ser. port 0 UDC Input Maximum   */ \
+					/* Packet size reg.		   */ \
+			(*((volatile Word *) io_p2v (_Ser0UDCIMP)))
+#define Ser0UDCCS0			/* Ser. port 0 UDC Control/Status  */ \
+					/* reg. end-point 0		   */ \
+			(*((volatile Word *) io_p2v (_Ser0UDCCS0)))
+#define Ser0UDCCS1			/* Ser. port 0 UDC Control/Status  */ \
+					/* reg. end-point 1 (output)	   */ \
+			(*((volatile Word *) io_p2v (_Ser0UDCCS1)))
+#define Ser0UDCCS2			/* Ser. port 0 UDC Control/Status  */ \
+					/* reg. end-point 2 (input)	   */ \
+			(*((volatile Word *) io_p2v (_Ser0UDCCS2)))
+#define Ser0UDCD0			/* Ser. port 0 UDC Data reg.	   */ \
+					/* end-point 0			   */ \
+			(*((volatile Word *) io_p2v (_Ser0UDCD0)))
+#define Ser0UDCWC			/* Ser. port 0 UDC Write Count	   */ \
+					/* reg. end-point 0		   */ \
+			(*((volatile Word *) io_p2v (_Ser0UDCWC)))
+#define Ser0UDCDR			/* Ser. port 0 UDC Data Reg.	   */ \
+			(*((volatile Word *) io_p2v (_Ser0UDCDR)))
+#define Ser0UDCSR			/* Ser. port 0 UDC Status Reg.	   */ \
+			(*((volatile Word *) io_p2v (_Ser0UDCSR)))
+#endif /* LANGUAGE == C */
+
+#define UDCCR_UDD	0x00000001	/* UDC Disable			   */
+#define UDCCR_UDA	0x00000002	/* UDC Active (read)		   */
+#define UDCCR_RESIM	0x00000004	/* Resume Interrupt Mask, per errata */
+#define UDCCR_EIM	0x00000008	/* End-point 0 Interrupt Mask	   */
+					/* (disable)			   */
+#define UDCCR_RIM	0x00000010	/* Receive Interrupt Mask	   */
+					/* (disable)			   */
+#define UDCCR_TIM	0x00000020	/* Transmit Interrupt Mask	   */
+					/* (disable)			   */
+#define UDCCR_SRM	0x00000040	/* Suspend/Resume interrupt Mask   */
+					/* (disable)			   */
+#define UDCCR_SUSIM	UDCCR_SRM	/* Per errata, SRM just masks suspend */
+#define UDCCR_REM	0x00000080	/* REset interrupt Mask (disable)  */
+
+#define UDCAR_ADD	Fld (7, 0)	/* function ADDress		   */
+
+#define UDCOMP_OUTMAXP	Fld (8, 0)	/* OUTput MAXimum Packet size - 1  */
+					/* [byte]			   */
+#define UDCOMP_OutMaxPkt(Size)		/* Output Maximum Packet size	   */ \
+					/* [1..256 byte]		   */ \
+			(((Size) - 1) << FShft (UDCOMP_OUTMAXP))
+
+#define UDCIMP_INMAXP	Fld (8, 0)	/* INput MAXimum Packet size - 1   */
+					/* [byte]			   */
+#define UDCIMP_InMaxPkt(Size)		/* Input Maximum Packet size	   */ \
+					/* [1..256 byte]		   */ \
+			(((Size) - 1) << FShft (UDCIMP_INMAXP))
+
+#define UDCCS0_OPR	0x00000001	/* Output Packet Ready (read)	   */
+#define UDCCS0_IPR	0x00000002	/* Input Packet Ready		   */
+#define UDCCS0_SST	0x00000004	/* Sent STall			   */
+#define UDCCS0_FST	0x00000008	/* Force STall			   */
+#define UDCCS0_DE	0x00000010	/* Data End			   */
+#define UDCCS0_SE	0x00000020	/* Setup End (read)		   */
+#define UDCCS0_SO	0x00000040	/* Serviced Output packet ready    */
+					/* (write)			   */
+#define UDCCS0_SSE	0x00000080	/* Serviced Setup End (write)	   */
+
+#define UDCCS1_RFS	0x00000001	/* Receive FIFO 12-bytes or more   */
+					/* Service request (read)	   */
+#define UDCCS1_RPC	0x00000002	/* Receive Packet Complete	   */
+#define UDCCS1_RPE	0x00000004	/* Receive Packet Error (read)	   */
+#define UDCCS1_SST	0x00000008	/* Sent STall			   */
+#define UDCCS1_FST	0x00000010	/* Force STall			   */
+#define UDCCS1_RNE	0x00000020	/* Receive FIFO Not Empty (read)   */
+
+#define UDCCS2_TFS	0x00000001	/* Transmit FIFO 8-bytes or less   */
+					/* Service request (read)	   */
+#define UDCCS2_TPC	0x00000002	/* Transmit Packet Complete	   */
+#define UDCCS2_TPE	0x00000004	/* Transmit Packet Error (read)    */
+#define UDCCS2_TUR	0x00000008	/* Transmit FIFO Under-Run	   */
+#define UDCCS2_SST	0x00000010	/* Sent STall			   */
+#define UDCCS2_FST	0x00000020	/* Force STall			   */
+
+#define UDCD0_DATA	Fld (8, 0)	/* receive/transmit DATA FIFOs	   */
+
+#define UDCWC_WC	Fld (4, 0)	/* Write Count			   */
+
+#define UDCDR_DATA	Fld (8, 0)	/* receive/transmit DATA FIFOs	   */
+
+#define UDCSR_EIR	0x00000001	/* End-point 0 Interrupt Request   */
+#define UDCSR_RIR	0x00000002	/* Receive Interrupt Request	   */
+#define UDCSR_TIR	0x00000004	/* Transmit Interrupt Request	   */
+#define UDCSR_SUSIR	0x00000008	/* SUSpend Interrupt Request	   */
+#define UDCSR_RESIR	0x00000010	/* RESume Interrupt Request	   */
+#define UDCSR_RSTIR	0x00000020	/* ReSeT Interrupt Request	   */
+
+
+/*
+ * Universal Asynchronous Receiver/Transmitter (UART) control registers
+ *
+ * Registers
+ *    Ser1UTCR0		Serial port 1 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Control Register 0
+ *			(read/write).
+ *    Ser1UTCR1		Serial port 1 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Control Register 1
+ *			(read/write).
+ *    Ser1UTCR2		Serial port 1 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Control Register 2
+ *			(read/write).
+ *    Ser1UTCR3		Serial port 1 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Control Register 3
+ *			(read/write).
+ *    Ser1UTDR		Serial port 1 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Data Register
+ *			(read/write).
+ *    Ser1UTSR0		Serial port 1 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Status Register 0
+ *			(read/write).
+ *    Ser1UTSR1		Serial port 1 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Status Register 1 (read).
+ *
+ *    Ser2UTCR0		Serial port 2 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Control Register 0
+ *			(read/write).
+ *    Ser2UTCR1		Serial port 2 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Control Register 1
+ *			(read/write).
+ *    Ser2UTCR2		Serial port 2 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Control Register 2
+ *			(read/write).
+ *    Ser2UTCR3		Serial port 2 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Control Register 3
+ *			(read/write).
+ *    Ser2UTCR4		Serial port 2 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Control Register 4
+ *			(read/write).
+ *    Ser2UTDR		Serial port 2 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Data Register
+ *			(read/write).
+ *    Ser2UTSR0		Serial port 2 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Status Register 0
+ *			(read/write).
+ *    Ser2UTSR1		Serial port 2 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Status Register 1 (read).
+ *
+ *    Ser3UTCR0		Serial port 3 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Control Register 0
+ *			(read/write).
+ *    Ser3UTCR1		Serial port 3 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Control Register 1
+ *			(read/write).
+ *    Ser3UTCR2		Serial port 3 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Control Register 2
+ *			(read/write).
+ *    Ser3UTCR3		Serial port 3 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Control Register 3
+ *			(read/write).
+ *    Ser3UTDR		Serial port 3 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Data Register
+ *			(read/write).
+ *    Ser3UTSR0		Serial port 3 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Status Register 0
+ *			(read/write).
+ *    Ser3UTSR1		Serial port 3 Universal Asynchronous
+ *			Receiver/Transmitter (UART) Status Register 1 (read).
+ *
+ * Clocks
+ *    fxtl, Txtl	Frequency, period of the system crystal (3.6864 MHz
+ *			or 3.5795 MHz).
+ *    fua, Tua		Frequency, period of the UART communication.
+ */
+
+#define _UTCR0(Nb)			/* UART Control Reg. 0 [1..3]	   */ \
+			(0x80010000 + ((Nb) - 1)*0x00020000)
+#define _UTCR1(Nb)			/* UART Control Reg. 1 [1..3]	   */ \
+			(0x80010004 + ((Nb) - 1)*0x00020000)
+#define _UTCR2(Nb)			/* UART Control Reg. 2 [1..3]	   */ \
+			(0x80010008 + ((Nb) - 1)*0x00020000)
+#define _UTCR3(Nb)			/* UART Control Reg. 3 [1..3]	   */ \
+			(0x8001000C + ((Nb) - 1)*0x00020000)
+#define _UTCR4(Nb)			/* UART Control Reg. 4 [2]	   */ \
+			(0x80010010 + ((Nb) - 1)*0x00020000)
+#define _UTDR(Nb)			/* UART Data Reg. [1..3]	   */ \
+			(0x80010014 + ((Nb) - 1)*0x00020000)
+#define _UTSR0(Nb)			/* UART Status Reg. 0 [1..3]	   */ \
+			(0x8001001C + ((Nb) - 1)*0x00020000)
+#define _UTSR1(Nb)			/* UART Status Reg. 1 [1..3]	   */ \
+			(0x80010020 + ((Nb) - 1)*0x00020000)
+
+#define _Ser1UTCR0	_UTCR0 (1)	/* Ser. port 1 UART Control Reg. 0 */
+#define _Ser1UTCR1	_UTCR1 (1)	/* Ser. port 1 UART Control Reg. 1 */
+#define _Ser1UTCR2	_UTCR2 (1)	/* Ser. port 1 UART Control Reg. 2 */
+#define _Ser1UTCR3	_UTCR3 (1)	/* Ser. port 1 UART Control Reg. 3 */
+#define _Ser1UTDR	_UTDR (1)	/* Ser. port 1 UART Data Reg.	   */
+#define _Ser1UTSR0	_UTSR0 (1)	/* Ser. port 1 UART Status Reg. 0  */
+#define _Ser1UTSR1	_UTSR1 (1)	/* Ser. port 1 UART Status Reg. 1  */
+
+#define _Ser2UTCR0	_UTCR0 (2)	/* Ser. port 2 UART Control Reg. 0 */
+#define _Ser2UTCR1	_UTCR1 (2)	/* Ser. port 2 UART Control Reg. 1 */
+#define _Ser2UTCR2	_UTCR2 (2)	/* Ser. port 2 UART Control Reg. 2 */
+#define _Ser2UTCR3	_UTCR3 (2)	/* Ser. port 2 UART Control Reg. 3 */
+#define _Ser2UTCR4	_UTCR4 (2)	/* Ser. port 2 UART Control Reg. 4 */
+#define _Ser2UTDR	_UTDR (2)	/* Ser. port 2 UART Data Reg.	   */
+#define _Ser2UTSR0	_UTSR0 (2)	/* Ser. port 2 UART Status Reg. 0  */
+#define _Ser2UTSR1	_UTSR1 (2)	/* Ser. port 2 UART Status Reg. 1  */
+
+#define _Ser3UTCR0	_UTCR0 (3)	/* Ser. port 3 UART Control Reg. 0 */
+#define _Ser3UTCR1	_UTCR1 (3)	/* Ser. port 3 UART Control Reg. 1 */
+#define _Ser3UTCR2	_UTCR2 (3)	/* Ser. port 3 UART Control Reg. 2 */
+#define _Ser3UTCR3	_UTCR3 (3)	/* Ser. port 3 UART Control Reg. 3 */
+#define _Ser3UTDR	_UTDR (3)	/* Ser. port 3 UART Data Reg.	   */
+#define _Ser3UTSR0	_UTSR0 (3)	/* Ser. port 3 UART Status Reg. 0  */
+#define _Ser3UTSR1	_UTSR1 (3)	/* Ser. port 3 UART Status Reg. 1  */
+
+#if LANGUAGE == C
+
+#define Ser1UTCR0			/* Ser. port 1 UART Control Reg. 0 */ \
+			(*((volatile Word *) io_p2v (_Ser1UTCR0)))
+#define Ser1UTCR1			/* Ser. port 1 UART Control Reg. 1 */ \
+			(*((volatile Word *) io_p2v (_Ser1UTCR1)))
+#define Ser1UTCR2			/* Ser. port 1 UART Control Reg. 2 */ \
+			(*((volatile Word *) io_p2v (_Ser1UTCR2)))
+#define Ser1UTCR3			/* Ser. port 1 UART Control Reg. 3 */ \
+			(*((volatile Word *) io_p2v (_Ser1UTCR3)))
+#define Ser1UTDR			/* Ser. port 1 UART Data Reg.	   */ \
+			(*((volatile Word *) io_p2v (_Ser1UTDR)))
+#define Ser1UTSR0			/* Ser. port 1 UART Status Reg. 0  */ \
+			(*((volatile Word *) io_p2v (_Ser1UTSR0)))
+#define Ser1UTSR1			/* Ser. port 1 UART Status Reg. 1  */ \
+			(*((volatile Word *) io_p2v (_Ser1UTSR1)))
+
+#define Ser2UTCR0			/* Ser. port 2 UART Control Reg. 0 */ \
+			(*((volatile Word *) io_p2v (_Ser2UTCR0)))
+#define Ser2UTCR1			/* Ser. port 2 UART Control Reg. 1 */ \
+			(*((volatile Word *) io_p2v (_Ser2UTCR1)))
+#define Ser2UTCR2			/* Ser. port 2 UART Control Reg. 2 */ \
+			(*((volatile Word *) io_p2v (_Ser2UTCR2)))
+#define Ser2UTCR3			/* Ser. port 2 UART Control Reg. 3 */ \
+			(*((volatile Word *) io_p2v (_Ser2UTCR3)))
+#define Ser2UTCR4			/* Ser. port 2 UART Control Reg. 4 */ \
+			(*((volatile Word *) io_p2v (_Ser2UTCR4)))
+#define Ser2UTDR			/* Ser. port 2 UART Data Reg.	   */ \
+			(*((volatile Word *) io_p2v (_Ser2UTDR)))
+#define Ser2UTSR0			/* Ser. port 2 UART Status Reg. 0  */ \
+			(*((volatile Word *) io_p2v (_Ser2UTSR0)))
+#define Ser2UTSR1			/* Ser. port 2 UART Status Reg. 1  */ \
+			(*((volatile Word *) io_p2v (_Ser2UTSR1)))
+
+#define Ser3UTCR0			/* Ser. port 3 UART Control Reg. 0 */ \
+			(*((volatile Word *) io_p2v (_Ser3UTCR0)))
+#define Ser3UTCR1			/* Ser. port 3 UART Control Reg. 1 */ \
+			(*((volatile Word *) io_p2v (_Ser3UTCR1)))
+#define Ser3UTCR2			/* Ser. port 3 UART Control Reg. 2 */ \
+			(*((volatile Word *) io_p2v (_Ser3UTCR2)))
+#define Ser3UTCR3			/* Ser. port 3 UART Control Reg. 3 */ \
+			(*((volatile Word *) io_p2v (_Ser3UTCR3)))
+#define Ser3UTDR			/* Ser. port 3 UART Data Reg.	   */ \
+			(*((volatile Word *) io_p2v (_Ser3UTDR)))
+#define Ser3UTSR0			/* Ser. port 3 UART Status Reg. 0  */ \
+			(*((volatile Word *) io_p2v (_Ser3UTSR0)))
+#define Ser3UTSR1			/* Ser. port 3 UART Status Reg. 1  */ \
+			(*((volatile Word *) io_p2v (_Ser3UTSR1)))
+
+#elif LANGUAGE == Assembly
+#define Ser1UTCR0	( io_p2v (_Ser1UTCR0))
+#define Ser1UTCR1	( io_p2v (_Ser1UTCR1))
+#define Ser1UTCR2	( io_p2v (_Ser1UTCR2))
+#define Ser1UTCR3	( io_p2v (_Ser1UTCR3))
+#define Ser1UTDR	( io_p2v (_Ser1UTDR))
+#define Ser1UTSR0	( io_p2v (_Ser1UTSR0))
+#define Ser1UTSR1	( io_p2v (_Ser1UTSR1))
+
+#define Ser2UTCR0	( io_p2v (_Ser2UTCR0))
+#define Ser2UTCR1	( io_p2v (_Ser2UTCR1))
+#define Ser2UTCR2	( io_p2v (_Ser2UTCR2))
+#define Ser2UTCR3	( io_p2v (_Ser2UTCR3))
+#define Ser2UTCR4	( io_p2v (_Ser2UTCR4))
+#define Ser2UTDR	( io_p2v (_Ser2UTDR))
+#define Ser2UTSR0	( io_p2v (_Ser2UTSR0))
+#define Ser2UTSR1	( io_p2v (_Ser2UTSR1))
+
+#define Ser3UTCR0	( io_p2v (_Ser3UTCR0))
+#define Ser3UTCR1	( io_p2v (_Ser3UTCR1))
+#define Ser3UTCR2	( io_p2v (_Ser3UTCR2))
+#define Ser3UTCR3	( io_p2v (_Ser3UTCR3))
+#define Ser3UTDR	( io_p2v (_Ser3UTDR))
+#define Ser3UTSR0	( io_p2v (_Ser3UTSR0))
+#define Ser3UTSR1	( io_p2v (_Ser3UTSR1))
+
+#endif /* LANGUAGE == C */
+
+#define UTCR0_PE	0x00000001	/* Parity Enable		   */
+#define UTCR0_OES	0x00000002	/* Odd/Even parity Select	   */
+#define UTCR0_OddPar	(UTCR0_OES*0)	/*  Odd Parity			   */
+#define UTCR0_EvenPar	(UTCR0_OES*1)	/*  Even Parity			   */
+#define UTCR0_SBS	0x00000004	/* Stop Bit Select		   */
+#define UTCR0_1StpBit	(UTCR0_SBS*0)	/*  1 Stop Bit per frame	   */
+#define UTCR0_2StpBit	(UTCR0_SBS*1)	/*  2 Stop Bits per frame	   */
+#define UTCR0_DSS	0x00000008	/* Data Size Select		   */
+#define UTCR0_7BitData	(UTCR0_DSS*0)	/*  7-Bit Data			   */
+#define UTCR0_8BitData	(UTCR0_DSS*1)	/*  8-Bit Data			   */
+#define UTCR0_SCE	0x00000010	/* Sample Clock Enable		   */
+					/* (ser. port 1: GPIO [18],	   */
+					/* ser. port 3: GPIO [20])	   */
+#define UTCR0_RCE	0x00000020	/* Receive Clock Edge select	   */
+#define UTCR0_RcRsEdg	(UTCR0_RCE*0)	/*  Receive clock Rising-Edge	   */
+#define UTCR0_RcFlEdg	(UTCR0_RCE*1)	/*  Receive clock Falling-Edge	   */
+#define UTCR0_TCE	0x00000040	/* Transmit Clock Edge select	   */
+#define UTCR0_TrRsEdg	(UTCR0_TCE*0)	/*  Transmit clock Rising-Edge	   */
+#define UTCR0_TrFlEdg	(UTCR0_TCE*1)	/*  Transmit clock Falling-Edge    */
+#define UTCR0_Ser2IrDA			/* Ser. port 2 IrDA settings	   */ \
+			(UTCR0_1StpBit + UTCR0_8BitData)
+
+#define UTCR1_BRD	Fld (4, 0)	/* Baud Rate Divisor/16 - 1 [11:8] */
+#define UTCR2_BRD	Fld (8, 0)	/* Baud Rate Divisor/16 - 1  [7:0] */
+					/* fua = fxtl/(16*(BRD[11:0] + 1)) */
+					/* Tua = 16*(BRD [11:0] + 1)*Txtl  */
+#define UTCR1_BdRtDiv(Div)		/*  Baud Rate Divisor [16..65536]  */ \
+			(((Div) - 16)/16 >> FSize (UTCR2_BRD) << \
+			 FShft (UTCR1_BRD))
+#define UTCR2_BdRtDiv(Div)		/*  Baud Rate Divisor [16..65536]  */ \
+			(((Div) - 16)/16 & FAlnMsk (UTCR2_BRD) << \
+			 FShft (UTCR2_BRD))
+					/*  fua = fxtl/(16*Floor (Div/16)) */
+					/*  Tua = 16*Floor (Div/16)*Txtl   */
+#define UTCR1_CeilBdRtDiv(Div)		/*  Ceil. of BdRtDiv [16..65536]   */ \
+			(((Div) - 1)/16 >> FSize (UTCR2_BRD) << \
+			 FShft (UTCR1_BRD))
+#define UTCR2_CeilBdRtDiv(Div)		/*  Ceil. of BdRtDiv [16..65536]   */ \
+			(((Div) - 1)/16 & FAlnMsk (UTCR2_BRD) << \
+			 FShft (UTCR2_BRD))
+					/*  fua = fxtl/(16*Ceil (Div/16))  */
+					/*  Tua = 16*Ceil (Div/16)*Txtl    */
+
+#define UTCR3_RXE	0x00000001	/* Receive Enable		   */
+#define UTCR3_TXE	0x00000002	/* Transmit Enable		   */
+#define UTCR3_BRK	0x00000004	/* BReaK mode			   */
+#define UTCR3_RIE	0x00000008	/* Receive FIFO 1/3-to-2/3-full or */
+					/* more Interrupt Enable	   */
+#define UTCR3_TIE	0x00000010	/* Transmit FIFO 1/2-full or less  */
+					/* Interrupt Enable		   */
+#define UTCR3_LBM	0x00000020	/* Look-Back Mode		   */
+#define UTCR3_Ser2IrDA			/* Ser. port 2 IrDA settings (RIE, */ \
+					/* TIE, LBM can be set or cleared) */ \
+			(UTCR3_RXE + UTCR3_TXE)
+
+#define UTCR4_HSE	0x00000001	/* Hewlett-Packard Serial InfraRed */
+					/* (HP-SIR) modulation Enable	   */
+#define UTCR4_NRZ	(UTCR4_HSE*0)	/*  Non-Return to Zero modulation  */
+#define UTCR4_HPSIR	(UTCR4_HSE*1)	/*  HP-SIR modulation		   */
+#define UTCR4_LPM	0x00000002	/* Low-Power Mode		   */
+#define UTCR4_Z3_16Bit	(UTCR4_LPM*0)	/*  Zero pulse = 3/16 Bit time	   */
+#define UTCR4_Z1_6us	(UTCR4_LPM*1)	/*  Zero pulse = 1.6 us		   */
+
+#define UTDR_DATA	Fld (8, 0)	/* receive/transmit DATA FIFOs	   */
+#if 0					/* Hidden receive FIFO bits	   */
+#define UTDR_PRE	0x00000100	/*  receive PaRity Error (read)    */
+#define UTDR_FRE	0x00000200	/*  receive FRaming Error (read)   */
+#define UTDR_ROR	0x00000400	/*  Receive FIFO Over-Run (read)   */
+#endif /* 0 */
+
+#define UTSR0_TFS	0x00000001	/* Transmit FIFO 1/2-full or less  */
+					/* Service request (read)	   */
+#define UTSR0_RFS	0x00000002	/* Receive FIFO 1/3-to-2/3-full or */
+					/* more Service request (read)	   */
+#define UTSR0_RID	0x00000004	/* Receiver IDle		   */
+#define UTSR0_RBB	0x00000008	/* Receive Beginning of Break	   */
+#define UTSR0_REB	0x00000010	/* Receive End of Break		   */
+#define UTSR0_EIF	0x00000020	/* Error In FIFO (read)		   */
+
+#define UTSR1_TBY	0x00000001	/* Transmitter BusY (read)	   */
+#define UTSR1_RNE	0x00000002	/* Receive FIFO Not Empty (read)   */
+#define UTSR1_TNF	0x00000004	/* Transmit FIFO Not Full (read)   */
+#define UTSR1_PRE	0x00000008	/* receive PaRity Error (read)	   */
+#define UTSR1_FRE	0x00000010	/* receive FRaming Error (read)    */
+#define UTSR1_ROR	0x00000020	/* Receive FIFO Over-Run (read)    */
+
+
+/*
+ * Synchronous Data Link Controller (SDLC) control registers
+ *
+ * Registers
+ *    Ser1SDCR0		Serial port 1 Synchronous Data Link Controller (SDLC)
+ *			Control Register 0 (read/write).
+ *    Ser1SDCR1		Serial port 1 Synchronous Data Link Controller (SDLC)
+ *			Control Register 1 (read/write).
+ *    Ser1SDCR2		Serial port 1 Synchronous Data Link Controller (SDLC)
+ *			Control Register 2 (read/write).
+ *    Ser1SDCR3		Serial port 1 Synchronous Data Link Controller (SDLC)
+ *			Control Register 3 (read/write).
+ *    Ser1SDCR4		Serial port 1 Synchronous Data Link Controller (SDLC)
+ *			Control Register 4 (read/write).
+ *    Ser1SDDR		Serial port 1 Synchronous Data Link Controller (SDLC)
+ *			Data Register (read/write).
+ *    Ser1SDSR0		Serial port 1 Synchronous Data Link Controller (SDLC)
+ *			Status Register 0 (read/write).
+ *    Ser1SDSR1		Serial port 1 Synchronous Data Link Controller (SDLC)
+ *			Status Register 1 (read/write).
+ *
+ * Clocks
+ *    fxtl, Txtl	Frequency, period of the system crystal (3.6864 MHz
+ *			or 3.5795 MHz).
+ *    fsd, Tsd		Frequency, period of the SDLC communication.
+ */
+
+#define _Ser1SDCR0	0x80020060	/* Ser. port 1 SDLC Control Reg. 0 */
+#define _Ser1SDCR1	0x80020064	/* Ser. port 1 SDLC Control Reg. 1 */
+#define _Ser1SDCR2	0x80020068	/* Ser. port 1 SDLC Control Reg. 2 */
+#define _Ser1SDCR3	0x8002006C	/* Ser. port 1 SDLC Control Reg. 3 */
+#define _Ser1SDCR4	0x80020070	/* Ser. port 1 SDLC Control Reg. 4 */
+#define _Ser1SDDR	0x80020078	/* Ser. port 1 SDLC Data Reg.	   */
+#define _Ser1SDSR0	0x80020080	/* Ser. port 1 SDLC Status Reg. 0  */
+#define _Ser1SDSR1	0x80020084	/* Ser. port 1 SDLC Status Reg. 1  */
+
+#if LANGUAGE == C
+#define Ser1SDCR0			/* Ser. port 1 SDLC Control Reg. 0 */ \
+			(*((volatile Word *) io_p2v (_Ser1SDCR0)))
+#define Ser1SDCR1			/* Ser. port 1 SDLC Control Reg. 1 */ \
+			(*((volatile Word *) io_p2v (_Ser1SDCR1)))
+#define Ser1SDCR2			/* Ser. port 1 SDLC Control Reg. 2 */ \
+			(*((volatile Word *) io_p2v (_Ser1SDCR2)))
+#define Ser1SDCR3			/* Ser. port 1 SDLC Control Reg. 3 */ \
+			(*((volatile Word *) io_p2v (_Ser1SDCR3)))
+#define Ser1SDCR4			/* Ser. port 1 SDLC Control Reg. 4 */ \
+			(*((volatile Word *) io_p2v (_Ser1SDCR4)))
+#define Ser1SDDR			/* Ser. port 1 SDLC Data Reg.	   */ \
+			(*((volatile Word *) io_p2v (_Ser1SDDR)))
+#define Ser1SDSR0			/* Ser. port 1 SDLC Status Reg. 0  */ \
+			(*((volatile Word *) io_p2v (_Ser1SDSR0)))
+#define Ser1SDSR1			/* Ser. port 1 SDLC Status Reg. 1  */ \
+			(*((volatile Word *) io_p2v (_Ser1SDSR1)))
+#endif /* LANGUAGE == C */
+
+#define SDCR0_SUS	0x00000001	/* SDLC/UART Select		   */
+#define SDCR0_SDLC	(SDCR0_SUS*0)	/*  SDLC mode (TXD1 & RXD1)	   */
+#define SDCR0_UART	(SDCR0_SUS*1)	/*  UART mode (TXD1 & RXD1)	   */
+#define SDCR0_SDF	0x00000002	/* Single/Double start Flag select */
+#define SDCR0_SglFlg	(SDCR0_SDF*0)	/*  Single start Flag		   */
+#define SDCR0_DblFlg	(SDCR0_SDF*1)	/*  Double start Flag		   */
+#define SDCR0_LBM	0x00000004	/* Look-Back Mode		   */
+#define SDCR0_BMS	0x00000008	/* Bit Modulation Select	   */
+#define SDCR0_FM0	(SDCR0_BMS*0)	/*  Freq. Modulation zero (0)	   */
+#define SDCR0_NRZ	(SDCR0_BMS*1)	/*  Non-Return to Zero modulation  */
+#define SDCR0_SCE	0x00000010	/* Sample Clock Enable (GPIO [16]) */
+#define SDCR0_SCD	0x00000020	/* Sample Clock Direction select   */
+					/* (GPIO [16])			   */
+#define SDCR0_SClkIn	(SDCR0_SCD*0)	/*  Sample Clock Input		   */
+#define SDCR0_SClkOut	(SDCR0_SCD*1)	/*  Sample Clock Output		   */
+#define SDCR0_RCE	0x00000040	/* Receive Clock Edge select	   */
+#define SDCR0_RcRsEdg	(SDCR0_RCE*0)	/*  Receive clock Rising-Edge	   */
+#define SDCR0_RcFlEdg	(SDCR0_RCE*1)	/*  Receive clock Falling-Edge	   */
+#define SDCR0_TCE	0x00000080	/* Transmit Clock Edge select	   */
+#define SDCR0_TrRsEdg	(SDCR0_TCE*0)	/*  Transmit clock Rising-Edge	   */
+#define SDCR0_TrFlEdg	(SDCR0_TCE*1)	/*  Transmit clock Falling-Edge    */
+
+#define SDCR1_AAF	0x00000001	/* Abort After Frame enable	   */
+					/* (GPIO [17])			   */
+#define SDCR1_TXE	0x00000002	/* Transmit Enable		   */
+#define SDCR1_RXE	0x00000004	/* Receive Enable		   */
+#define SDCR1_RIE	0x00000008	/* Receive FIFO 1/3-to-2/3-full or */
+					/* more Interrupt Enable	   */
+#define SDCR1_TIE	0x00000010	/* Transmit FIFO 1/2-full or less  */
+					/* Interrupt Enable		   */
+#define SDCR1_AME	0x00000020	/* Address Match Enable		   */
+#define SDCR1_TUS	0x00000040	/* Transmit FIFO Under-run Select  */
+#define SDCR1_EFrmURn	(SDCR1_TUS*0)	/*  End Frame on Under-Run	   */
+#define SDCR1_AbortURn	(SDCR1_TUS*1)	/*  Abort on Under-Run		   */
+#define SDCR1_RAE	0x00000080	/* Receive Abort interrupt Enable  */
+
+#define SDCR2_AMV	Fld (8, 0)	/* Address Match Value		   */
+
+#define SDCR3_BRD	Fld (4, 0)	/* Baud Rate Divisor/16 - 1 [11:8] */
+#define SDCR4_BRD	Fld (8, 0)	/* Baud Rate Divisor/16 - 1  [7:0] */
+					/* fsd = fxtl/(16*(BRD[11:0] + 1)) */
+					/* Tsd = 16*(BRD[11:0] + 1)*Txtl   */
+#define SDCR3_BdRtDiv(Div)		/*  Baud Rate Divisor [16..65536]  */ \
+			(((Div) - 16)/16 >> FSize (SDCR4_BRD) << \
+			 FShft (SDCR3_BRD))
+#define SDCR4_BdRtDiv(Div)		/*  Baud Rate Divisor [16..65536]  */ \
+			(((Div) - 16)/16 & FAlnMsk (SDCR4_BRD) << \
+			 FShft (SDCR4_BRD))
+					/*  fsd = fxtl/(16*Floor (Div/16)) */
+					/*  Tsd = 16*Floor (Div/16)*Txtl   */
+#define SDCR3_CeilBdRtDiv(Div)		/*  Ceil. of BdRtDiv [16..65536]   */ \
+			(((Div) - 1)/16 >> FSize (SDCR4_BRD) << \
+			 FShft (SDCR3_BRD))
+#define SDCR4_CeilBdRtDiv(Div)		/*  Ceil. of BdRtDiv [16..65536]   */ \
+			(((Div) - 1)/16 & FAlnMsk (SDCR4_BRD) << \
+			 FShft (SDCR4_BRD))
+					/*  fsd = fxtl/(16*Ceil (Div/16))  */
+					/*  Tsd = 16*Ceil (Div/16)*Txtl    */
+
+#define SDDR_DATA	Fld (8, 0)	/* receive/transmit DATA FIFOs	   */
+#if 0					/* Hidden receive FIFO bits	   */
+#define SDDR_EOF	0x00000100	/*  receive End-Of-Frame (read)    */
+#define SDDR_CRE	0x00000200	/*  receive CRC Error (read)	   */
+#define SDDR_ROR	0x00000400	/*  Receive FIFO Over-Run (read)   */
+#endif /* 0 */
+
+#define SDSR0_EIF	0x00000001	/* Error In FIFO (read)		   */
+#define SDSR0_TUR	0x00000002	/* Transmit FIFO Under-Run	   */
+#define SDSR0_RAB	0x00000004	/* Receive ABort		   */
+#define SDSR0_TFS	0x00000008	/* Transmit FIFO 1/2-full or less  */
+					/* Service request (read)	   */
+#define SDSR0_RFS	0x00000010	/* Receive FIFO 1/3-to-2/3-full or */
+					/* more Service request (read)	   */
+
+#define SDSR1_RSY	0x00000001	/* Receiver SYnchronized (read)    */
+#define SDSR1_TBY	0x00000002	/* Transmitter BusY (read)	   */
+#define SDSR1_RNE	0x00000004	/* Receive FIFO Not Empty (read)   */
+#define SDSR1_TNF	0x00000008	/* Transmit FIFO Not Full (read)   */
+#define SDSR1_RTD	0x00000010	/* Receive Transition Detected	   */
+#define SDSR1_EOF	0x00000020	/* receive End-Of-Frame (read)	   */
+#define SDSR1_CRE	0x00000040	/* receive CRC Error (read)	   */
+#define SDSR1_ROR	0x00000080	/* Receive FIFO Over-Run (read)    */
+
+
+/*
+ * High-Speed Serial to Parallel controller (HSSP) control registers
+ *
+ * Registers
+ *    Ser2HSCR0		Serial port 2 High-Speed Serial to Parallel
+ *			controller (HSSP) Control Register 0 (read/write).
+ *    Ser2HSCR1		Serial port 2 High-Speed Serial to Parallel
+ *			controller (HSSP) Control Register 1 (read/write).
+ *    Ser2HSDR		Serial port 2 High-Speed Serial to Parallel
+ *			controller (HSSP) Data Register (read/write).
+ *    Ser2HSSR0		Serial port 2 High-Speed Serial to Parallel
+ *			controller (HSSP) Status Register 0 (read/write).
+ *    Ser2HSSR1		Serial port 2 High-Speed Serial to Parallel
+ *			controller (HSSP) Status Register 1 (read).
+ *    Ser2HSCR2		Serial port 2 High-Speed Serial to Parallel
+ *			controller (HSSP) Control Register 2 (read/write).
+ *			[The HSCR2 register is only implemented in
+ *			versions 2.0 (rev. = 8) and higher of the StrongARM
+ *			SA-1100.]
+ */
+
+#define _Ser2HSCR0	0x80040060	/* Ser. port 2 HSSP Control Reg. 0 */
+#define _Ser2HSCR1	0x80040064	/* Ser. port 2 HSSP Control Reg. 1 */
+#define _Ser2HSDR	0x8004006C	/* Ser. port 2 HSSP Data Reg.	   */
+#define _Ser2HSSR0	0x80040074	/* Ser. port 2 HSSP Status Reg. 0  */
+#define _Ser2HSSR1	0x80040078	/* Ser. port 2 HSSP Status Reg. 1  */
+#define _Ser2HSCR2	0x90060028	/* Ser. port 2 HSSP Control Reg. 2 */
+
+#if LANGUAGE == C
+#define Ser2HSCR0			/* Ser. port 2 HSSP Control Reg. 0 */ \
+			(*((volatile Word *) io_p2v (_Ser2HSCR0)))
+#define Ser2HSCR1			/* Ser. port 2 HSSP Control Reg. 1 */ \
+			(*((volatile Word *) io_p2v (_Ser2HSCR1)))
+#define Ser2HSDR			/* Ser. port 2 HSSP Data Reg.	   */ \
+			(*((volatile Word *) io_p2v (_Ser2HSDR)))
+#define Ser2HSSR0			/* Ser. port 2 HSSP Status Reg. 0  */ \
+			(*((volatile Word *) io_p2v (_Ser2HSSR0)))
+#define Ser2HSSR1			/* Ser. port 2 HSSP Status Reg. 1  */ \
+			(*((volatile Word *) io_p2v (_Ser2HSSR1)))
+#define Ser2HSCR2			/* Ser. port 2 HSSP Control Reg. 2 */ \
+			(*((volatile Word *) io_p2v (_Ser2HSCR2)))
+#endif /* LANGUAGE == C */
+
+#define HSCR0_ITR	0x00000001	/* IrDA Transmission Rate	   */
+#define HSCR0_UART	(HSCR0_ITR*0)	/*  UART mode (115.2 kb/s if IrDA) */
+#define HSCR0_HSSP	(HSCR0_ITR*1)	/*  HSSP mode (4 Mb/s)		   */
+#define HSCR0_LBM	0x00000002	/* Look-Back Mode		   */
+#define HSCR0_TUS	0x00000004	/* Transmit FIFO Under-run Select  */
+#define HSCR0_EFrmURn	(HSCR0_TUS*0)	/*  End Frame on Under-Run	   */
+#define HSCR0_AbortURn	(HSCR0_TUS*1)	/*  Abort on Under-Run		   */
+#define HSCR0_TXE	0x00000008	/* Transmit Enable		   */
+#define HSCR0_RXE	0x00000010	/* Receive Enable		   */
+#define HSCR0_RIE	0x00000020	/* Receive FIFO 2/5-to-3/5-full or */
+					/* more Interrupt Enable	   */
+#define HSCR0_TIE	0x00000040	/* Transmit FIFO 1/2-full or less  */
+					/* Interrupt Enable		   */
+#define HSCR0_AME	0x00000080	/* Address Match Enable		   */
+
+#define HSCR1_AMV	Fld (8, 0)	/* Address Match Value		   */
+
+#define HSDR_DATA	Fld (8, 0)	/* receive/transmit DATA FIFOs	   */
+#if 0					/* Hidden receive FIFO bits	   */
+#define HSDR_EOF	0x00000100	/*  receive End-Of-Frame (read)    */
+#define HSDR_CRE	0x00000200	/*  receive CRC Error (read)	   */
+#define HSDR_ROR	0x00000400	/*  Receive FIFO Over-Run (read)   */
+#endif /* 0 */
+
+#define HSSR0_EIF	0x00000001	/* Error In FIFO (read)		   */
+#define HSSR0_TUR	0x00000002	/* Transmit FIFO Under-Run	   */
+#define HSSR0_RAB	0x00000004	/* Receive ABort		   */
+#define HSSR0_TFS	0x00000008	/* Transmit FIFO 1/2-full or less  */
+					/* Service request (read)	   */
+#define HSSR0_RFS	0x00000010	/* Receive FIFO 2/5-to-3/5-full or */
+					/* more Service request (read)	   */
+#define HSSR0_FRE	0x00000020	/* receive FRaming Error	   */
+
+#define HSSR1_RSY	0x00000001	/* Receiver SYnchronized (read)    */
+#define HSSR1_TBY	0x00000002	/* Transmitter BusY (read)	   */
+#define HSSR1_RNE	0x00000004	/* Receive FIFO Not Empty (read)   */
+#define HSSR1_TNF	0x00000008	/* Transmit FIFO Not Full (read)   */
+#define HSSR1_EOF	0x00000010	/* receive End-Of-Frame (read)	   */
+#define HSSR1_CRE	0x00000020	/* receive CRC Error (read)	   */
+#define HSSR1_ROR	0x00000040	/* Receive FIFO Over-Run (read)    */
+
+#define HSCR2_TXP	0x00040000	/* Transmit data Polarity (TXD_2)  */
+#define HSCR2_TrDataL	(HSCR2_TXP*0)	/*  Transmit Data active Low	   */
+					/*  (inverted)			   */
+#define HSCR2_TrDataH	(HSCR2_TXP*1)	/*  Transmit Data active High	   */
+					/*  (non-inverted)		   */
+#define HSCR2_RXP	0x00080000	/* Receive data Polarity (RXD_2)   */
+#define HSCR2_RcDataL	(HSCR2_RXP*0)	/*  Receive Data active Low	   */
+					/*  (inverted)			   */
+#define HSCR2_RcDataH	(HSCR2_RXP*1)	/*  Receive Data active High	   */
+					/*  (non-inverted)		   */
+
+
+/*
+ * Multi-media Communications Port (MCP) control registers
+ *
+ * Registers
+ *    Ser4MCCR0		Serial port 4 Multi-media Communications Port (MCP)
+ *			Control Register 0 (read/write).
+ *    Ser4MCDR0		Serial port 4 Multi-media Communications Port (MCP)
+ *			Data Register 0 (audio, read/write).
+ *    Ser4MCDR1		Serial port 4 Multi-media Communications Port (MCP)
+ *			Data Register 1 (telecom, read/write).
+ *    Ser4MCDR2		Serial port 4 Multi-media Communications Port (MCP)
+ *			Data Register 2 (CODEC registers, read/write).
+ *    Ser4MCSR		Serial port 4 Multi-media Communications Port (MCP)
+ *			Status Register (read/write).
+ *    Ser4MCCR1		Serial port 4 Multi-media Communications Port (MCP)
+ *			Control Register 1 (read/write).
+ *			[The MCCR1 register is only implemented in
+ *			versions 2.0 (rev. = 8) and higher of the StrongARM
+ *			SA-1100.]
+ *
+ * Clocks
+ *    fmc, Tmc		Frequency, period of the MCP communication (10 MHz,
+ *			12 MHz, or GPIO [21]).
+ *    faud, Taud	Frequency, period of the audio sampling.
+ *    ftcm, Ttcm	Frequency, period of the telecom sampling.
+ */
+
+#define _Ser4MCCR0	0x80060000	/* Ser. port 4 MCP Control Reg. 0  */
+#define _Ser4MCDR0	0x80060008	/* Ser. port 4 MCP Data Reg. 0	   */
+					/* (audio)			   */
+#define _Ser4MCDR1	0x8006000C	/* Ser. port 4 MCP Data Reg. 1	   */
+					/* (telecom)			   */
+#define _Ser4MCDR2	0x80060010	/* Ser. port 4 MCP Data Reg. 2	   */
+					/* (CODEC reg.)			   */
+#define _Ser4MCSR	0x80060018	/* Ser. port 4 MCP Status Reg.	   */
+#define _Ser4MCCR1	0x90060030	/* Ser. port 4 MCP Control Reg. 1  */
+
+#if LANGUAGE == C
+#define Ser4MCCR0			/* Ser. port 4 MCP Control Reg. 0  */ \
+			(*((volatile Word *) io_p2v (_Ser4MCCR0)))
+#define Ser4MCDR0			/* Ser. port 4 MCP Data Reg. 0	   */ \
+					/* (audio)			   */ \
+			(*((volatile Word *) io_p2v (_Ser4MCDR0)))
+#define Ser4MCDR1			/* Ser. port 4 MCP Data Reg. 1	   */ \
+					/* (telecom)			   */ \
+			(*((volatile Word *) io_p2v (_Ser4MCDR1)))
+#define Ser4MCDR2			/* Ser. port 4 MCP Data Reg. 2	   */ \
+					/* (CODEC reg.)			   */ \
+			(*((volatile Word *) io_p2v (_Ser4MCDR2)))
+#define Ser4MCSR			/* Ser. port 4 MCP Status Reg.	   */ \
+			(*((volatile Word *) io_p2v (_Ser4MCSR)))
+#define Ser4MCCR1			/* Ser. port 4 MCP Control Reg. 1  */ \
+			(*((volatile Word *) io_p2v (_Ser4MCCR1)))
+#endif /* LANGUAGE == C */
+
+#define MCCR0_ASD	Fld (7, 0)	/* Audio Sampling rate Divisor/32  */
+					/* [6..127]			   */
+					/* faud = fmc/(32*ASD)		   */
+					/* Taud = 32*ASD*Tmc		   */
+#define MCCR0_AudSmpDiv(Div)		/*  Audio Sampling rate Divisor    */ \
+					/*  [192..4064]			   */ \
+			((Div)/32 << FShft (MCCR0_ASD))
+					/*  faud = fmc/(32*Floor (Div/32)) */
+					/*  Taud = 32*Floor (Div/32)*Tmc   */
+#define MCCR0_CeilAudSmpDiv(Div)	/*  Ceil. of AudSmpDiv [192..4064] */ \
+			(((Div) + 31)/32 << FShft (MCCR0_ASD))
+					/*  faud = fmc/(32*Ceil (Div/32))  */
+					/*  Taud = 32*Ceil (Div/32)*Tmc    */
+#define MCCR0_TSD	Fld (7, 8)	/* Telecom Sampling rate	   */
+					/* Divisor/32 [16..127]		   */
+					/* ftcm = fmc/(32*TSD)		   */
+					/* Ttcm = 32*TSD*Tmc		   */
+#define MCCR0_TcmSmpDiv(Div)		/*  Telecom Sampling rate Divisor  */ \
+					/*  [512..4064]			   */ \
+			((Div)/32 << FShft (MCCR0_TSD))
+					/*  ftcm = fmc/(32*Floor (Div/32)) */
+					/*  Ttcm = 32*Floor (Div/32)*Tmc   */
+#define MCCR0_CeilTcmSmpDiv(Div)	/*  Ceil. of TcmSmpDiv [512..4064] */ \
+			(((Div) + 31)/32 << FShft (MCCR0_TSD))
+					/*  ftcm = fmc/(32*Ceil (Div/32))  */
+					/*  Ttcm = 32*Ceil (Div/32)*Tmc    */
+#define MCCR0_MCE	0x00010000	/* MCP Enable			   */
+#define MCCR0_ECS	0x00020000	/* External Clock Select	   */
+#define MCCR0_IntClk	(MCCR0_ECS*0)	/*  Internal Clock (10 or 12 MHz)  */
+#define MCCR0_ExtClk	(MCCR0_ECS*1)	/*  External Clock (GPIO [21])	   */
+#define MCCR0_ADM	0x00040000	/* A/D (audio/telecom) data	   */
+					/* sampling/storing Mode	   */
+#define MCCR0_VldBit	(MCCR0_ADM*0)	/*  Valid Bit storing mode	   */
+#define MCCR0_SmpCnt	(MCCR0_ADM*1)	/*  Sampling Counter storing mode  */
+#define MCCR0_TTE	0x00080000	/* Telecom Transmit FIFO 1/2-full  */
+					/* or less interrupt Enable	   */
+#define MCCR0_TRE	0x00100000	/* Telecom Receive FIFO 1/2-full   */
+					/* or more interrupt Enable	   */
+#define MCCR0_ATE	0x00200000	/* Audio Transmit FIFO 1/2-full    */
+					/* or less interrupt Enable	   */
+#define MCCR0_ARE	0x00400000	/* Audio Receive FIFO 1/2-full or  */
+					/* more interrupt Enable	   */
+#define MCCR0_LBM	0x00800000	/* Look-Back Mode		   */
+#define MCCR0_ECP	Fld (2, 24)	/* External Clock Prescaler - 1    */
+#define MCCR0_ExtClkDiv(Div)		/*  External Clock Divisor [1..4]  */ \
+			(((Div) - 1) << FShft (MCCR0_ECP))
+
+#define MCDR0_DATA	Fld (12, 4)	/* receive/transmit audio DATA	   */
+					/* FIFOs			   */
+
+#define MCDR1_DATA	Fld (14, 2)	/* receive/transmit telecom DATA   */
+					/* FIFOs			   */
+
+					/* receive/transmit CODEC reg.	   */
+					/* FIFOs:			   */
+#define MCDR2_DATA	Fld (16, 0)	/*  reg. DATA			   */
+#define MCDR2_RW	0x00010000	/*  reg. Read/Write (transmit)	   */
+#define MCDR2_Rd	(MCDR2_RW*0)	/*   reg. Read			   */
+#define MCDR2_Wr	(MCDR2_RW*1)	/*   reg. Write			   */
+#define MCDR2_ADD	Fld (4, 17)	/*  reg. ADDress		   */
+
+#define MCSR_ATS	0x00000001	/* Audio Transmit FIFO 1/2-full    */
+					/* or less Service request (read)  */
+#define MCSR_ARS	0x00000002	/* Audio Receive FIFO 1/2-full or  */
+					/* more Service request (read)	   */
+#define MCSR_TTS	0x00000004	/* Telecom Transmit FIFO 1/2-full  */
+					/* or less Service request (read)  */
+#define MCSR_TRS	0x00000008	/* Telecom Receive FIFO 1/2-full   */
+					/* or more Service request (read)  */
+#define MCSR_ATU	0x00000010	/* Audio Transmit FIFO Under-run   */
+#define MCSR_ARO	0x00000020	/* Audio Receive FIFO Over-run	   */
+#define MCSR_TTU	0x00000040	/* Telecom Transmit FIFO Under-run */
+#define MCSR_TRO	0x00000080	/* Telecom Receive FIFO Over-run   */
+#define MCSR_ANF	0x00000100	/* Audio transmit FIFO Not Full    */
+					/* (read)			   */
+#define MCSR_ANE	0x00000200	/* Audio receive FIFO Not Empty    */
+					/* (read)			   */
+#define MCSR_TNF	0x00000400	/* Telecom transmit FIFO Not Full  */
+					/* (read)			   */
+#define MCSR_TNE	0x00000800	/* Telecom receive FIFO Not Empty  */
+					/* (read)			   */
+#define MCSR_CWC	0x00001000	/* CODEC register Write Completed  */
+					/* (read)			   */
+#define MCSR_CRC	0x00002000	/* CODEC register Read Completed   */
+					/* (read)			   */
+#define MCSR_ACE	0x00004000	/* Audio CODEC Enabled (read)	   */
+#define MCSR_TCE	0x00008000	/* Telecom CODEC Enabled (read)    */
+
+#define MCCR1_CFS	0x00100000	/* Clock Freq. Select		   */
+#define MCCR1_F12MHz	(MCCR1_CFS*0)	/*  Freq. (fmc) = ~ 12 MHz	   */
+					/*  (11.981 MHz)		   */
+#define MCCR1_F10MHz	(MCCR1_CFS*1)	/*  Freq. (fmc) = ~ 10 MHz	   */
+					/*  (9.585 MHz)			   */
+
+
+/*
+ * Synchronous Serial Port (SSP) control registers
+ *
+ * Registers
+ *    Ser4SSCR0		Serial port 4 Synchronous Serial Port (SSP) Control
+ *			Register 0 (read/write).
+ *    Ser4SSCR1		Serial port 4 Synchronous Serial Port (SSP) Control
+ *			Register 1 (read/write).
+ *			[Bits SPO and SP are only implemented in versions 2.0
+ *			(rev. = 8) and higher of the StrongARM SA-1100.]
+ *    Ser4SSDR		Serial port 4 Synchronous Serial Port (SSP) Data
+ *			Register (read/write).
+ *    Ser4SSSR		Serial port 4 Synchronous Serial Port (SSP) Status
+ *			Register (read/write).
+ *
+ * Clocks
+ *    fxtl, Txtl	Frequency, period of the system crystal (3.6864 MHz
+ *			or 3.5795 MHz).
+ *    fss, Tss		Frequency, period of the SSP communication.
+ */
+
+#define _Ser4SSCR0	0x80070060	/* Ser. port 4 SSP Control Reg. 0  */
+#define _Ser4SSCR1	0x80070064	/* Ser. port 4 SSP Control Reg. 1  */
+#define _Ser4SSDR	0x8007006C	/* Ser. port 4 SSP Data Reg.	   */
+#define _Ser4SSSR	0x80070074	/* Ser. port 4 SSP Status Reg.	   */
+
+#if LANGUAGE == C
+#define Ser4SSCR0			/* Ser. port 4 SSP Control Reg. 0  */ \
+			(*((volatile Word *) io_p2v (_Ser4SSCR0)))
+#define Ser4SSCR1			/* Ser. port 4 SSP Control Reg. 1  */ \
+			(*((volatile Word *) io_p2v (_Ser4SSCR1)))
+#define Ser4SSDR			/* Ser. port 4 SSP Data Reg.	   */ \
+			(*((volatile Word *) io_p2v (_Ser4SSDR)))
+#define Ser4SSSR			/* Ser. port 4 SSP Status Reg.	   */ \
+			(*((volatile Word *) io_p2v (_Ser4SSSR)))
+#endif /* LANGUAGE == C */
+
+#define SSCR0_DSS	Fld (4, 0)	/* Data Size - 1 Select [3..15]    */
+#define SSCR0_DataSize(Size)		/*  Data Size Select [4..16]	   */ \
+			(((Size) - 1) << FShft (SSCR0_DSS))
+#define SSCR0_FRF	Fld (2, 4)	/* FRame Format			   */
+#define SSCR0_Motorola			/*  Motorola Serial Peripheral	   */ \
+					/*  Interface (SPI) format	   */ \
+			(0 << FShft (SSCR0_FRF))
+#define SSCR0_TI			/*  Texas Instruments Synchronous  */ \
+					/*  Serial format		   */ \
+			(1 << FShft (SSCR0_FRF))
+#define SSCR0_National			/*  National Microwire format	   */ \
+			(2 << FShft (SSCR0_FRF))
+#define SSCR0_SSE	0x00000080	/* SSP Enable			   */
+#define SSCR0_SCR	Fld (8, 8)	/* Serial Clock Rate divisor/2 - 1 */
+					/* fss = fxtl/(2*(SCR + 1))	   */
+					/* Tss = 2*(SCR + 1)*Txtl	   */
+#define SSCR0_SerClkDiv(Div)		/*  Serial Clock Divisor [2..512]  */ \
+			(((Div) - 2)/2 << FShft (SSCR0_SCR))
+					/*  fss = fxtl/(2*Floor (Div/2))   */
+					/*  Tss = 2*Floor (Div/2)*Txtl	   */
+#define SSCR0_CeilSerClkDiv(Div)	/*  Ceil. of SerClkDiv [2..512]    */ \
+			(((Div) - 1)/2 << FShft (SSCR0_SCR))
+					/*  fss = fxtl/(2*Ceil (Div/2))    */
+					/*  Tss = 2*Ceil (Div/2)*Txtl	   */
+
+#define SSCR1_RIE	0x00000001	/* Receive FIFO 1/2-full or more   */
+					/* Interrupt Enable		   */
+#define SSCR1_TIE	0x00000002	/* Transmit FIFO 1/2-full or less  */
+					/* Interrupt Enable		   */
+#define SSCR1_LBM	0x00000004	/* Look-Back Mode		   */
+#define SSCR1_SPO	0x00000008	/* Sample clock (SCLK) POlarity    */
+#define SSCR1_SClkIactL	(SSCR1_SPO*0)	/*  Sample Clock Inactive Low	   */
+#define SSCR1_SClkIactH	(SSCR1_SPO*1)	/*  Sample Clock Inactive High	   */
+#define SSCR1_SP	0x00000010	/* Sample clock (SCLK) Phase	   */
+#define SSCR1_SClk1P	(SSCR1_SP*0)	/*  Sample Clock active 1 Period   */
+					/*  after frame (SFRM, 1st edge)   */
+#define SSCR1_SClk1_2P	(SSCR1_SP*1)	/*  Sample Clock active 1/2 Period */
+					/*  after frame (SFRM, 1st edge)   */
+#define SSCR1_ECS	0x00000020	/* External Clock Select	   */
+#define SSCR1_IntClk	(SSCR1_ECS*0)	/*  Internal Clock		   */
+#define SSCR1_ExtClk	(SSCR1_ECS*1)	/*  External Clock (GPIO [19])	   */
+
+#define SSDR_DATA	Fld (16, 0)	/* receive/transmit DATA FIFOs	   */
+
+#define SSSR_TNF	0x00000002	/* Transmit FIFO Not Full (read)   */
+#define SSSR_RNE	0x00000004	/* Receive FIFO Not Empty (read)   */
+#define SSSR_BSY	0x00000008	/* SSP BuSY (read)		   */
+#define SSSR_TFS	0x00000010	/* Transmit FIFO 1/2-full or less  */
+					/* Service request (read)	   */
+#define SSSR_RFS	0x00000020	/* Receive FIFO 1/2-full or more   */
+					/* Service request (read)	   */
+#define SSSR_ROR	0x00000040	/* Receive FIFO Over-Run	   */
+
+
+/*
+ * Operating System (OS) timer control registers
+ *
+ * Registers
+ *    OSMR0		Operating System (OS) timer Match Register 0
+ *			(read/write).
+ *    OSMR1		Operating System (OS) timer Match Register 1
+ *			(read/write).
+ *    OSMR2		Operating System (OS) timer Match Register 2
+ *			(read/write).
+ *    OSMR3		Operating System (OS) timer Match Register 3
+ *			(read/write).
+ *    OSCR		Operating System (OS) timer Counter Register
+ *			(read/write).
+ *    OSSR		Operating System (OS) timer Status Register
+ *			(read/write).
+ *    OWER		Operating System (OS) timer Watch-dog Enable Register
+ *			(read/write).
+ *    OIER		Operating System (OS) timer Interrupt Enable Register
+ *			(read/write).
+ */
+
+#define _OSMR(Nb)			/* OS timer Match Reg. [0..3]	   */ \
+			(0x90000000 + (Nb)*4)
+#define _OSMR0		_OSMR (0)	/* OS timer Match Reg. 0	   */
+#define _OSMR1		_OSMR (1)	/* OS timer Match Reg. 1	   */
+#define _OSMR2		_OSMR (2)	/* OS timer Match Reg. 2	   */
+#define _OSMR3		_OSMR (3)	/* OS timer Match Reg. 3	   */
+#define _OSCR		0x90000010	/* OS timer Counter Reg.	   */
+#define _OSSR		0x90000014	/* OS timer Status Reg.		   */
+#define _OWER		0x90000018	/* OS timer Watch-dog Enable Reg.  */
+#define _OIER		0x9000001C	/* OS timer Interrupt Enable Reg.  */
+
+#if LANGUAGE == C
+#define OSMR				/* OS timer Match Reg. [0..3]	   */ \
+			((volatile Word *) io_p2v (_OSMR (0)))
+#define OSMR0		(OSMR [0])	/* OS timer Match Reg. 0	   */
+#define OSMR1		(OSMR [1])	/* OS timer Match Reg. 1	   */
+#define OSMR2		(OSMR [2])	/* OS timer Match Reg. 2	   */
+#define OSMR3		(OSMR [3])	/* OS timer Match Reg. 3	   */
+#define OSCR				/* OS timer Counter Reg.	   */ \
+			(*((volatile Word *) io_p2v (_OSCR)))
+#define OSSR				/* OS timer Status Reg.		   */ \
+			(*((volatile Word *) io_p2v (_OSSR)))
+#define OWER				/* OS timer Watch-dog Enable Reg.  */ \
+			(*((volatile Word *) io_p2v (_OWER)))
+#define OIER				/* OS timer Interrupt Enable Reg.  */ \
+			(*((volatile Word *) io_p2v (_OIER)))
+#endif /* LANGUAGE == C */
+
+#define OSSR_M(Nb)			/* Match detected [0..3]	   */ \
+			(0x00000001 << (Nb))
+#define OSSR_M0		OSSR_M (0)	/* Match detected 0		   */
+#define OSSR_M1		OSSR_M (1)	/* Match detected 1		   */
+#define OSSR_M2		OSSR_M (2)	/* Match detected 2		   */
+#define OSSR_M3		OSSR_M (3)	/* Match detected 3		   */
+
+#define OWER_WME	0x00000001	/* Watch-dog Match Enable	   */
+					/* (set only)			   */
+
+#define OIER_E(Nb)			/* match interrupt Enable [0..3]   */ \
+			(0x00000001 << (Nb))
+#define OIER_E0		OIER_E (0)	/* match interrupt Enable 0	   */
+#define OIER_E1		OIER_E (1)	/* match interrupt Enable 1	   */
+#define OIER_E2		OIER_E (2)	/* match interrupt Enable 2	   */
+#define OIER_E3		OIER_E (3)	/* match interrupt Enable 3	   */
+
+
+/*
+ * Real-Time Clock (RTC) control registers
+ *
+ * Registers
+ *    RTAR		Real-Time Clock (RTC) Alarm Register (read/write).
+ *    RCNR		Real-Time Clock (RTC) CouNt Register (read/write).
+ *    RTTR		Real-Time Clock (RTC) Trim Register (read/write).
+ *    RTSR		Real-Time Clock (RTC) Status Register (read/write).
+ *
+ * Clocks
+ *    frtx, Trtx	Frequency, period of the real-time clock crystal
+ *			(32.768 kHz nominal).
+ *    frtc, Trtc	Frequency, period of the real-time clock counter
+ *			(1 Hz nominal).
+ */
+
+#define _RTAR		0x90010000	/* RTC Alarm Reg.		   */
+#define _RCNR		0x90010004	/* RTC CouNt Reg.		   */
+#define _RTTR		0x90010008	/* RTC Trim Reg.		   */
+#define _RTSR		0x90010010	/* RTC Status Reg.		   */
+
+#if LANGUAGE == C
+#define RTAR				/* RTC Alarm Reg.		   */ \
+			(*((volatile Word *) io_p2v (_RTAR)))
+#define RCNR				/* RTC CouNt Reg.		   */ \
+			(*((volatile Word *) io_p2v (_RCNR)))
+#define RTTR				/* RTC Trim Reg.		   */ \
+			(*((volatile Word *) io_p2v (_RTTR)))
+#define RTSR				/* RTC Status Reg.		   */ \
+			(*((volatile Word *) io_p2v (_RTSR)))
+#endif /* LANGUAGE == C */
+
+#define RTTR_C		Fld (16, 0)	/* clock divider Count - 1	   */
+#define RTTR_D		Fld (10, 16)	/* trim Delete count		   */
+					/* frtc = (1023*(C + 1) - D)*frtx/ */
+					/*	  (1023*(C + 1)^2)	   */
+					/* Trtc = (1023*(C + 1)^2)*Trtx/   */
+					/*	  (1023*(C + 1) - D)	   */
+
+#define RTSR_AL		0x00000001	/* ALarm detected		   */
+#define RTSR_HZ		0x00000002	/* 1 Hz clock detected		   */
+#define RTSR_ALE	0x00000004	/* ALarm interrupt Enable	   */
+#define RTSR_HZE	0x00000008	/* 1 Hz clock interrupt Enable	   */
+
+
+/*
+ * Power Manager (PM) control registers
+ *
+ * Registers
+ *    PMCR		Power Manager (PM) Control Register (read/write).
+ *    PSSR		Power Manager (PM) Sleep Status Register (read/write).
+ *    PSPR		Power Manager (PM) Scratch-Pad Register (read/write).
+ *    PWER		Power Manager (PM) Wake-up Enable Register
+ *			(read/write).
+ *    PCFR		Power Manager (PM) general ConFiguration Register
+ *			(read/write).
+ *    PPCR		Power Manager (PM) Phase-Locked Loop (PLL)
+ *			Configuration Register (read/write).
+ *    PGSR		Power Manager (PM) General-Purpose Input/Output (GPIO)
+ *			Sleep state Register (read/write, see GPIO pins).
+ *    POSR		Power Manager (PM) Oscillator Status Register (read).
+ *
+ * Clocks
+ *    fxtl, Txtl	Frequency, period of the system crystal (3.6864 MHz
+ *			or 3.5795 MHz).
+ *    fcpu, Tcpu	Frequency, period of the CPU core clock (CCLK).
+ */
+
+#define _PMCR		0x90020000	/* PM Control Reg.		   */
+#define _PSSR		0x90020004	/* PM Sleep Status Reg.		   */
+#define _PSPR		0x90020008	/* PM Scratch-Pad Reg.		   */
+#define _PWER		0x9002000C	/* PM Wake-up Enable Reg.	   */
+#define _PCFR		0x90020010	/* PM general ConFiguration Reg.   */
+#define _PPCR		0x90020014	/* PM PLL Configuration Reg.	   */
+#define _PGSR		0x90020018	/* PM GPIO Sleep state Reg.	   */
+#define _POSR		0x9002001C	/* PM Oscillator Status Reg.	   */
+
+#if LANGUAGE == C
+#define PMCR				/* PM Control Reg.		   */ \
+			(*((volatile Word *) io_p2v (_PMCR)))
+#define PSSR				/* PM Sleep Status Reg.		   */ \
+			(*((volatile Word *) io_p2v (_PSSR)))
+#define PSPR				/* PM Scratch-Pad Reg.		   */ \
+			(*((volatile Word *) io_p2v (_PSPR)))
+#define PWER				/* PM Wake-up Enable Reg.	   */ \
+			(*((volatile Word *) io_p2v (_PWER)))
+#define PCFR				/* PM general ConFiguration Reg.   */ \
+			(*((volatile Word *) io_p2v (_PCFR)))
+#define PPCR				/* PM PLL Configuration Reg.	   */ \
+			(*((volatile Word *) io_p2v (_PPCR)))
+#define PGSR				/* PM GPIO Sleep state Reg.	   */ \
+			(*((volatile Word *) io_p2v (_PGSR)))
+#define POSR				/* PM Oscillator Status Reg.	   */ \
+			(*((volatile Word *) io_p2v (_POSR)))
+
+#elif LANGUAGE == Assembly
+#define PMCR		(io_p2v (_PMCR))
+#define PSSR		(io_p2v (_PSSR))
+#define PSPR		(io_p2v (_PSPR))
+#define PWER		(io_p2v (_PWER))
+#define PCFR		(io_p2v (_PCFR))
+#define PPCR		(io_p2v (_PPCR))
+#define PGSR		(io_p2v (_PGSR))
+#define POSR		(io_p2v (_POSR))
+
+#endif /* LANGUAGE == C */
+
+#define PMCR_SF		0x00000001	/* Sleep Force (set only)	   */
+
+#define PSSR_SS		0x00000001	/* Software Sleep		   */
+#define PSSR_BFS	0x00000002	/* Battery Fault Status		   */
+					/* (BATT_FAULT)			   */
+#define PSSR_VFS	0x00000004	/* Vdd Fault Status (VDD_FAULT)    */
+#define PSSR_DH		0x00000008	/* DRAM control Hold		   */
+#define PSSR_PH		0x00000010	/* Peripheral control Hold	   */
+
+#define PWER_GPIO(Nb)	GPIO_GPIO (Nb)	/* GPIO [0..27] wake-up enable	   */
+#define PWER_GPIO0	PWER_GPIO (0)	/* GPIO  [0] wake-up enable	   */
+#define PWER_GPIO1	PWER_GPIO (1)	/* GPIO  [1] wake-up enable	   */
+#define PWER_GPIO2	PWER_GPIO (2)	/* GPIO  [2] wake-up enable	   */
+#define PWER_GPIO3	PWER_GPIO (3)	/* GPIO  [3] wake-up enable	   */
+#define PWER_GPIO4	PWER_GPIO (4)	/* GPIO  [4] wake-up enable	   */
+#define PWER_GPIO5	PWER_GPIO (5)	/* GPIO  [5] wake-up enable	   */
+#define PWER_GPIO6	PWER_GPIO (6)	/* GPIO  [6] wake-up enable	   */
+#define PWER_GPIO7	PWER_GPIO (7)	/* GPIO  [7] wake-up enable	   */
+#define PWER_GPIO8	PWER_GPIO (8)	/* GPIO  [8] wake-up enable	   */
+#define PWER_GPIO9	PWER_GPIO (9)	/* GPIO  [9] wake-up enable	   */
+#define PWER_GPIO10	PWER_GPIO (10)	/* GPIO [10] wake-up enable	   */
+#define PWER_GPIO11	PWER_GPIO (11)	/* GPIO [11] wake-up enable	   */
+#define PWER_GPIO12	PWER_GPIO (12)	/* GPIO [12] wake-up enable	   */
+#define PWER_GPIO13	PWER_GPIO (13)	/* GPIO [13] wake-up enable	   */
+#define PWER_GPIO14	PWER_GPIO (14)	/* GPIO [14] wake-up enable	   */
+#define PWER_GPIO15	PWER_GPIO (15)	/* GPIO [15] wake-up enable	   */
+#define PWER_GPIO16	PWER_GPIO (16)	/* GPIO [16] wake-up enable	   */
+#define PWER_GPIO17	PWER_GPIO (17)	/* GPIO [17] wake-up enable	   */
+#define PWER_GPIO18	PWER_GPIO (18)	/* GPIO [18] wake-up enable	   */
+#define PWER_GPIO19	PWER_GPIO (19)	/* GPIO [19] wake-up enable	   */
+#define PWER_GPIO20	PWER_GPIO (20)	/* GPIO [20] wake-up enable	   */
+#define PWER_GPIO21	PWER_GPIO (21)	/* GPIO [21] wake-up enable	   */
+#define PWER_GPIO22	PWER_GPIO (22)	/* GPIO [22] wake-up enable	   */
+#define PWER_GPIO23	PWER_GPIO (23)	/* GPIO [23] wake-up enable	   */
+#define PWER_GPIO24	PWER_GPIO (24)	/* GPIO [24] wake-up enable	   */
+#define PWER_GPIO25	PWER_GPIO (25)	/* GPIO [25] wake-up enable	   */
+#define PWER_GPIO26	PWER_GPIO (26)	/* GPIO [26] wake-up enable	   */
+#define PWER_GPIO27	PWER_GPIO (27)	/* GPIO [27] wake-up enable	   */
+#define PWER_RTC	0x80000000	/* RTC alarm wake-up enable	   */
+
+#define PCFR_OPDE	0x00000001	/* Oscillator Power-Down Enable    */
+#define PCFR_ClkRun	(PCFR_OPDE*0)	/*  Clock Running in sleep mode    */
+#define PCFR_ClkStp	(PCFR_OPDE*1)	/*  Clock Stopped in sleep mode    */
+#define PCFR_FP		0x00000002	/* Float PCMCIA pins		   */
+#define PCFR_PCMCIANeg	(PCFR_FP*0)	/*  PCMCIA pins Negated (1)	   */
+#define PCFR_PCMCIAFlt	(PCFR_FP*1)	/*  PCMCIA pins Floating	   */
+#define PCFR_FS		0x00000004	/* Float Static memory pins	   */
+#define PCFR_StMemNeg	(PCFR_FS*0)	/*  Static Memory pins Negated (1) */
+#define PCFR_StMemFlt	(PCFR_FS*1)	/*  Static Memory pins Floating    */
+#define PCFR_FO		0x00000008	/* Force RTC oscillator		   */
+					/* (32.768 kHz) enable On	   */
+
+#define PPCR_CCF	Fld (5, 0)	/* CPU core Clock (CCLK) Freq.	   */
+#define PPCR_Fx16			/*  Freq. x 16 (fcpu = 16*fxtl)    */ \
+			(0x00 << FShft (PPCR_CCF))
+#define PPCR_Fx20			/*  Freq. x 20 (fcpu = 20*fxtl)    */ \
+			(0x01 << FShft (PPCR_CCF))
+#define PPCR_Fx24			/*  Freq. x 24 (fcpu = 24*fxtl)    */ \
+			(0x02 << FShft (PPCR_CCF))
+#define PPCR_Fx28			/*  Freq. x 28 (fcpu = 28*fxtl)    */ \
+			(0x03 << FShft (PPCR_CCF))
+#define PPCR_Fx32			/*  Freq. x 32 (fcpu = 32*fxtl)    */ \
+			(0x04 << FShft (PPCR_CCF))
+#define PPCR_Fx36			/*  Freq. x 36 (fcpu = 36*fxtl)    */ \
+			(0x05 << FShft (PPCR_CCF))
+#define PPCR_Fx40			/*  Freq. x 40 (fcpu = 40*fxtl)    */ \
+			(0x06 << FShft (PPCR_CCF))
+#define PPCR_Fx44			/*  Freq. x 44 (fcpu = 44*fxtl)    */ \
+			(0x07 << FShft (PPCR_CCF))
+#define PPCR_Fx48			/*  Freq. x 48 (fcpu = 48*fxtl)    */ \
+			(0x08 << FShft (PPCR_CCF))
+#define PPCR_Fx52			/*  Freq. x 52 (fcpu = 52*fxtl)    */ \
+			(0x09 << FShft (PPCR_CCF))
+#define PPCR_Fx56			/*  Freq. x 56 (fcpu = 56*fxtl)    */ \
+			(0x0A << FShft (PPCR_CCF))
+#define PPCR_Fx60			/*  Freq. x 60 (fcpu = 60*fxtl)    */ \
+			(0x0B << FShft (PPCR_CCF))
+#define PPCR_Fx64			/*  Freq. x 64 (fcpu = 64*fxtl)    */ \
+			(0x0C << FShft (PPCR_CCF))
+#define PPCR_Fx68			/*  Freq. x 68 (fcpu = 68*fxtl)    */ \
+			(0x0D << FShft (PPCR_CCF))
+#define PPCR_Fx72			/*  Freq. x 72 (fcpu = 72*fxtl)    */ \
+			(0x0E << FShft (PPCR_CCF))
+#define PPCR_Fx76			/*  Freq. x 76 (fcpu = 76*fxtl)    */ \
+			(0x0F << FShft (PPCR_CCF))
+					/*  3.6864 MHz crystal (fxtl):	   */
+#define PPCR_F59_0MHz	PPCR_Fx16	/*   Freq. (fcpu) =  59.0 MHz	   */
+#define PPCR_F73_7MHz	PPCR_Fx20	/*   Freq. (fcpu) =  73.7 MHz	   */
+#define PPCR_F88_5MHz	PPCR_Fx24	/*   Freq. (fcpu) =  88.5 MHz	   */
+#define PPCR_F103_2MHz	PPCR_Fx28	/*   Freq. (fcpu) = 103.2 MHz	   */
+#define PPCR_F118_0MHz	PPCR_Fx32	/*   Freq. (fcpu) = 118.0 MHz	   */
+#define PPCR_F132_7MHz	PPCR_Fx36	/*   Freq. (fcpu) = 132.7 MHz	   */
+#define PPCR_F147_5MHz	PPCR_Fx40	/*   Freq. (fcpu) = 147.5 MHz	   */
+#define PPCR_F162_2MHz	PPCR_Fx44	/*   Freq. (fcpu) = 162.2 MHz	   */
+#define PPCR_F176_9MHz	PPCR_Fx48	/*   Freq. (fcpu) = 176.9 MHz	   */
+#define PPCR_F191_7MHz	PPCR_Fx52	/*   Freq. (fcpu) = 191.7 MHz	   */
+#define PPCR_F206_4MHz	PPCR_Fx56	/*   Freq. (fcpu) = 206.4 MHz	   */
+#define PPCR_F221_2MHz	PPCR_Fx60	/*   Freq. (fcpu) = 221.2 MHz	   */
+#define PPCR_F239_6MHz	PPCR_Fx64	/*   Freq. (fcpu) = 239.6 MHz	   */
+#define PPCR_F250_7MHz	PPCR_Fx68	/*   Freq. (fcpu) = 250.7 MHz	   */
+#define PPCR_F265_4MHz	PPCR_Fx72	/*   Freq. (fcpu) = 265.4 MHz	   */
+#define PPCR_F280_2MHz	PPCR_Fx76	/*   Freq. (fcpu) = 280.2 MHz	   */
+					/*  3.5795 MHz crystal (fxtl):	   */
+#define PPCR_F57_3MHz	PPCR_Fx16	/*   Freq. (fcpu) =  57.3 MHz	   */
+#define PPCR_F71_6MHz	PPCR_Fx20	/*   Freq. (fcpu) =  71.6 MHz	   */
+#define PPCR_F85_9MHz	PPCR_Fx24	/*   Freq. (fcpu) =  85.9 MHz	   */
+#define PPCR_F100_2MHz	PPCR_Fx28	/*   Freq. (fcpu) = 100.2 MHz	   */
+#define PPCR_F114_5MHz	PPCR_Fx32	/*   Freq. (fcpu) = 114.5 MHz	   */
+#define PPCR_F128_9MHz	PPCR_Fx36	/*   Freq. (fcpu) = 128.9 MHz	   */
+#define PPCR_F143_2MHz	PPCR_Fx40	/*   Freq. (fcpu) = 143.2 MHz	   */
+#define PPCR_F157_5MHz	PPCR_Fx44	/*   Freq. (fcpu) = 157.5 MHz	   */
+#define PPCR_F171_8MHz	PPCR_Fx48	/*   Freq. (fcpu) = 171.8 MHz	   */
+#define PPCR_F186_1MHz	PPCR_Fx52	/*   Freq. (fcpu) = 186.1 MHz	   */
+#define PPCR_F200_5MHz	PPCR_Fx56	/*   Freq. (fcpu) = 200.5 MHz	   */
+#define PPCR_F214_8MHz	PPCR_Fx60	/*   Freq. (fcpu) = 214.8 MHz	   */
+#define PPCR_F229_1MHz	PPCR_Fx64	/*   Freq. (fcpu) = 229.1 MHz	   */
+#define PPCR_F243_4MHz	PPCR_Fx68	/*   Freq. (fcpu) = 243.4 MHz	   */
+#define PPCR_F257_7MHz	PPCR_Fx72	/*   Freq. (fcpu) = 257.7 MHz	   */
+#define PPCR_F272_0MHz	PPCR_Fx76	/*   Freq. (fcpu) = 272.0 MHz	   */
+
+#define POSR_OOK	0x00000001	/* RTC Oscillator (32.768 kHz) OK  */
+
+
+/*
+ * Reset Controller (RC) control registers
+ *
+ * Registers
+ *    RSRR		Reset Controller (RC) Software Reset Register
+ *			(read/write).
+ *    RCSR		Reset Controller (RC) Status Register (read/write).
+ */
+
+#define _RSRR		0x90030000	/* RC Software Reset Reg.	   */
+#define _RCSR		0x90030004	/* RC Status Reg.		   */
+
+#if LANGUAGE == C
+#define RSRR				/* RC Software Reset Reg.	   */ \
+			(*((volatile Word *) io_p2v (_RSRR)))
+#define RCSR				/* RC Status Reg.		   */ \
+			(*((volatile Word *) io_p2v (_RCSR)))
+#endif /* LANGUAGE == C */
+
+#define RSRR_SWR	0x00000001	/* SoftWare Reset (set only)	   */
+
+#define RCSR_HWR	0x00000001	/* HardWare Reset		   */
+#define RCSR_SWR	0x00000002	/* SoftWare Reset		   */
+#define RCSR_WDR	0x00000004	/* Watch-Dog Reset		   */
+#define RCSR_SMR	0x00000008	/* Sleep-Mode Reset		   */
+
+
+/*
+ * Test unit control registers
+ *
+ * Registers
+ *    TUCR		Test Unit Control Register (read/write).
+ */
+
+#define _TUCR		0x90030008	/* Test Unit Control Reg.	   */
+
+#if LANGUAGE == C
+#define TUCR				/* Test Unit Control Reg.	   */ \
+			(*((volatile Word *) io_p2v (_TUCR)))
+#endif /* LANGUAGE == C */
+
+#define TUCR_TIC	0x00000040	/* TIC mode			   */
+#define TUCR_TTST	0x00000080	/* Trim TeST mode		   */
+#define TUCR_RCRC	0x00000100	/* Richard's Cyclic Redundancy	   */
+					/* Check			   */
+#define TUCR_PMD	0x00000200	/* Power Management Disable	   */
+#define TUCR_MR		0x00000400	/* Memory Request mode		   */
+#define TUCR_NoMB	(TUCR_MR*0)	/*  No Memory Bus request & grant  */
+#define TUCR_MBGPIO	(TUCR_MR*1)	/*  Memory Bus request (MBREQ) &   */
+					/*  grant (MBGNT) on GPIO [22:21]  */
+#define TUCR_CTB	Fld (3, 20)	/* Clock Test Bits		   */
+#define TUCR_FDC	0x00800000	/* RTC Force Delete Count	   */
+#define TUCR_FMC	0x01000000	/* Force Michelle's Control mode   */
+#define TUCR_TMC	0x02000000	/* RTC Trimmer Multiplexer Control */
+#define TUCR_DPS	0x04000000	/* Disallow Pad Sleep		   */
+#define TUCR_TSEL	Fld (3, 29)	/* clock Test SELect on GPIO [27]  */
+#define TUCR_32_768kHz			/*  32.768 kHz osc. on GPIO [27]   */ \
+			(0 << FShft (TUCR_TSEL))
+#define TUCR_3_6864MHz			/*  3.6864 MHz osc. on GPIO [27]   */ \
+			(1 << FShft (TUCR_TSEL))
+#define TUCR_VDD			/*  VDD ring osc./16 on GPIO [27]  */ \
+			(2 << FShft (TUCR_TSEL))
+#define TUCR_96MHzPLL			/*  96 MHz PLL/4 on GPIO [27]	   */ \
+			(3 << FShft (TUCR_TSEL))
+#define TUCR_Clock			/*  internal (fcpu/2) & 32.768 kHz */ \
+					/*  Clocks on GPIO [26:27]	   */ \
+			(4 << FShft (TUCR_TSEL))
+#define TUCR_3_6864MHzA			/*  3.6864 MHz osc. on GPIO [27]   */ \
+					/*  (Alternative)		   */ \
+			(5 << FShft (TUCR_TSEL))
+#define TUCR_MainPLL			/*  Main PLL/16 on GPIO [27]	   */ \
+			(6 << FShft (TUCR_TSEL))
+#define TUCR_VDDL			/*  VDDL ring osc./4 on GPIO [27]  */ \
+			(7 << FShft (TUCR_TSEL))
+
+
+/*
+ * General-Purpose Input/Output (GPIO) control registers
+ *
+ * Registers
+ *    GPLR		General-Purpose Input/Output (GPIO) Pin Level
+ *			Register (read).
+ *    GPDR		General-Purpose Input/Output (GPIO) Pin Direction
+ *			Register (read/write).
+ *    GPSR		General-Purpose Input/Output (GPIO) Pin output Set
+ *			Register (write).
+ *    GPCR		General-Purpose Input/Output (GPIO) Pin output Clear
+ *			Register (write).
+ *    GRER		General-Purpose Input/Output (GPIO) Rising-Edge
+ *			detect Register (read/write).
+ *    GFER		General-Purpose Input/Output (GPIO) Falling-Edge
+ *			detect Register (read/write).
+ *    GEDR		General-Purpose Input/Output (GPIO) Edge Detect
+ *			status Register (read/write).
+ *    GAFR		General-Purpose Input/Output (GPIO) Alternate
+ *			Function Register (read/write).
+ *
+ * Clock
+ *    fcpu, Tcpu	Frequency, period of the CPU core clock (CCLK).
+ */
+
+#define _GPLR		0x90040000	/* GPIO Pin Level Reg.		   */
+#define _GPDR		0x90040004	/* GPIO Pin Direction Reg.	   */
+#define _GPSR		0x90040008	/* GPIO Pin output Set Reg.	   */
+#define _GPCR		0x9004000C	/* GPIO Pin output Clear Reg.	   */
+#define _GRER		0x90040010	/* GPIO Rising-Edge detect Reg.    */
+#define _GFER		0x90040014	/* GPIO Falling-Edge detect Reg.   */
+#define _GEDR		0x90040018	/* GPIO Edge Detect status Reg.    */
+#define _GAFR		0x9004001C	/* GPIO Alternate Function Reg.    */
+
+#if LANGUAGE == C
+#define GPLR				/* GPIO Pin Level Reg.		   */ \
+			(*((volatile Word *) io_p2v (_GPLR)))
+#define GPDR				/* GPIO Pin Direction Reg.	   */ \
+			(*((volatile Word *) io_p2v (_GPDR)))
+#define GPSR				/* GPIO Pin output Set Reg.	   */ \
+			(*((volatile Word *) io_p2v (_GPSR)))
+#define GPCR				/* GPIO Pin output Clear Reg.	   */ \
+			(*((volatile Word *) io_p2v (_GPCR)))
+#define GRER				/* GPIO Rising-Edge detect Reg.    */ \
+			(*((volatile Word *) io_p2v (_GRER)))
+#define GFER				/* GPIO Falling-Edge detect Reg.   */ \
+			(*((volatile Word *) io_p2v (_GFER)))
+#define GEDR				/* GPIO Edge Detect status Reg.    */ \
+			(*((volatile Word *) io_p2v (_GEDR)))
+#define GAFR				/* GPIO Alternate Function Reg.    */ \
+			(*((volatile Word *) io_p2v (_GAFR)))
+#elif LANGUAGE == Assembly
+
+#define GPLR  (io_p2v (_GPLR))
+#define GPDR  (io_p2v (_GPDR))
+#define GPSR  (io_p2v (_GPSR))
+#define GPCR  (io_p2v (_GPCR))
+#define GRER  (io_p2v (_GRER))
+#define GFER  (io_p2v (_GFER))
+#define GEDR  (io_p2v (_GEDR))
+#define GAFR  (io_p2v (_GAFR))
+
+#endif /* LANGUAGE == C */
+
+#define GPIO_MIN	(0)
+#define GPIO_MAX	(27)
+
+#define GPIO_GPIO(Nb)			/* GPIO [0..27]			   */ \
+			(0x00000001 << (Nb))
+#define GPIO_GPIO0	GPIO_GPIO (0)	/* GPIO  [0]			   */
+#define GPIO_GPIO1	GPIO_GPIO (1)	/* GPIO  [1]			   */
+#define GPIO_GPIO2	GPIO_GPIO (2)	/* GPIO  [2]			   */
+#define GPIO_GPIO3	GPIO_GPIO (3)	/* GPIO  [3]			   */
+#define GPIO_GPIO4	GPIO_GPIO (4)	/* GPIO  [4]			   */
+#define GPIO_GPIO5	GPIO_GPIO (5)	/* GPIO  [5]			   */
+#define GPIO_GPIO6	GPIO_GPIO (6)	/* GPIO  [6]			   */
+#define GPIO_GPIO7	GPIO_GPIO (7)	/* GPIO  [7]			   */
+#define GPIO_GPIO8	GPIO_GPIO (8)	/* GPIO  [8]			   */
+#define GPIO_GPIO9	GPIO_GPIO (9)	/* GPIO  [9]			   */
+#define GPIO_GPIO10	GPIO_GPIO (10)	/* GPIO [10]			   */
+#define GPIO_GPIO11	GPIO_GPIO (11)	/* GPIO [11]			   */
+#define GPIO_GPIO12	GPIO_GPIO (12)	/* GPIO [12]			   */
+#define GPIO_GPIO13	GPIO_GPIO (13)	/* GPIO [13]			   */
+#define GPIO_GPIO14	GPIO_GPIO (14)	/* GPIO [14]			   */
+#define GPIO_GPIO15	GPIO_GPIO (15)	/* GPIO [15]			   */
+#define GPIO_GPIO16	GPIO_GPIO (16)	/* GPIO [16]			   */
+#define GPIO_GPIO17	GPIO_GPIO (17)	/* GPIO [17]			   */
+#define GPIO_GPIO18	GPIO_GPIO (18)	/* GPIO [18]			   */
+#define GPIO_GPIO19	GPIO_GPIO (19)	/* GPIO [19]			   */
+#define GPIO_GPIO20	GPIO_GPIO (20)	/* GPIO [20]			   */
+#define GPIO_GPIO21	GPIO_GPIO (21)	/* GPIO [21]			   */
+#define GPIO_GPIO22	GPIO_GPIO (22)	/* GPIO [22]			   */
+#define GPIO_GPIO23	GPIO_GPIO (23)	/* GPIO [23]			   */
+#define GPIO_GPIO24	GPIO_GPIO (24)	/* GPIO [24]			   */
+#define GPIO_GPIO25	GPIO_GPIO (25)	/* GPIO [25]			   */
+#define GPIO_GPIO26	GPIO_GPIO (26)	/* GPIO [26]			   */
+#define GPIO_GPIO27	GPIO_GPIO (27)	/* GPIO [27]			   */
+
+#define GPIO_LDD(Nb)			/* LCD Data [8..15] (O)		   */ \
+			GPIO_GPIO ((Nb) - 6)
+#define GPIO_LDD8	GPIO_LDD (8)	/* LCD Data  [8] (O)		   */
+#define GPIO_LDD9	GPIO_LDD (9)	/* LCD Data  [9] (O)		   */
+#define GPIO_LDD10	GPIO_LDD (10)	/* LCD Data [10] (O)		   */
+#define GPIO_LDD11	GPIO_LDD (11)	/* LCD Data [11] (O)		   */
+#define GPIO_LDD12	GPIO_LDD (12)	/* LCD Data [12] (O)		   */
+#define GPIO_LDD13	GPIO_LDD (13)	/* LCD Data [13] (O)		   */
+#define GPIO_LDD14	GPIO_LDD (14)	/* LCD Data [14] (O)		   */
+#define GPIO_LDD15	GPIO_LDD (15)	/* LCD Data [15] (O)		   */
+					/* ser. port 4:			   */
+#define GPIO_SSP_TXD	GPIO_GPIO (10)	/*  SSP Transmit Data (O)	   */
+#define GPIO_SSP_RXD	GPIO_GPIO (11)	/*  SSP Receive Data (I)	   */
+#define GPIO_SSP_SCLK	GPIO_GPIO (12)	/*  SSP Sample CLocK (O)	   */
+#define GPIO_SSP_SFRM	GPIO_GPIO (13)	/*  SSP Sample FRaMe (O)	   */
+					/* ser. port 1:			   */
+#define GPIO_UART_TXD	GPIO_GPIO (14)	/*  UART Transmit Data (O)	   */
+#define GPIO_UART_RXD	GPIO_GPIO (15)	/*  UART Receive Data (I)	   */
+#define GPIO_SDLC_SCLK	GPIO_GPIO (16)	/*  SDLC Sample CLocK (I/O)	   */
+#define GPIO_SDLC_AAF	GPIO_GPIO (17)	/*  SDLC Abort After Frame (O)	   */
+#define GPIO_UART_SCLK1	GPIO_GPIO (18)	/*  UART Sample CLocK 1 (I)	   */
+					/* ser. port 4:			   */
+#define GPIO_SSP_CLK	GPIO_GPIO (19)	/*  SSP external CLocK (I)	   */
+					/* ser. port 3:			   */
+#define GPIO_UART_SCLK3	GPIO_GPIO (20)	/*  UART Sample CLocK 3 (I)	   */
+					/* ser. port 4:			   */
+#define GPIO_MCP_CLK	GPIO_GPIO (21)	/*  MCP CLocK (I)		   */
+					/* test controller:		   */
+#define GPIO_TIC_ACK	GPIO_GPIO (21)	/*  TIC ACKnowledge (O)		   */
+#define GPIO_MBGNT	GPIO_GPIO (21)	/*  Memory Bus GraNT (O)	   */
+#define GPIO_TREQA	GPIO_GPIO (22)	/*  TIC REQuest A (I)		   */
+#define GPIO_MBREQ	GPIO_GPIO (22)	/*  Memory Bus REQuest (I)	   */
+#define GPIO_TREQB	GPIO_GPIO (23)	/*  TIC REQuest B (I)		   */
+#define GPIO_1Hz	GPIO_GPIO (25)	/* 1 Hz clock (O)		   */
+#define GPIO_RCLK	GPIO_GPIO (26)	/* internal (R) CLocK (O, fcpu/2)  */
+#define GPIO_32_768kHz	GPIO_GPIO (27)	/* 32.768 kHz clock (O, RTC)	   */
+
+#define GPDR_In		0		/* Input			   */
+#define GPDR_Out	1		/* Output			   */
+
+
+/*
+ * Interrupt Controller (IC) control registers
+ *
+ * Registers
+ *    ICIP		Interrupt Controller (IC) Interrupt ReQuest (IRQ)
+ *			Pending register (read).
+ *    ICMR		Interrupt Controller (IC) Mask Register (read/write).
+ *    ICLR		Interrupt Controller (IC) Level Register (read/write).
+ *    ICCR		Interrupt Controller (IC) Control Register
+ *			(read/write).
+ *			[The ICCR register is only implemented in versions 2.0
+ *			(rev. = 8) and higher of the StrongARM SA-1100.]
+ *    ICFP		Interrupt Controller (IC) Fast Interrupt reQuest
+ *			(FIQ) Pending register (read).
+ *    ICPR		Interrupt Controller (IC) Pending Register (read).
+ *			[The ICPR register is active low (inverted) in
+ *			versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
+ *			StrongARM SA-1100, it is active high (non-inverted) in
+ *			versions 2.0 (rev. = 8) and higher.]
+ */
+
+#define _ICIP		0x90050000	/* IC IRQ Pending reg.		   */
+#define _ICMR		0x90050004	/* IC Mask Reg.			   */
+#define _ICLR		0x90050008	/* IC Level Reg.		   */
+#define _ICCR		0x9005000C	/* IC Control Reg.		   */
+#define _ICFP		0x90050010	/* IC FIQ Pending reg.		   */
+#define _ICPR		0x90050020	/* IC Pending Reg.		   */
+
+#if LANGUAGE == C
+#define ICIP				/* IC IRQ Pending reg.		   */ \
+			(*((volatile Word *) io_p2v (_ICIP)))
+#define ICMR				/* IC Mask Reg.			   */ \
+			(*((volatile Word *) io_p2v (_ICMR)))
+#define ICLR				/* IC Level Reg.		   */ \
+			(*((volatile Word *) io_p2v (_ICLR)))
+#define ICCR				/* IC Control Reg.		   */ \
+			(*((volatile Word *) io_p2v (_ICCR)))
+#define ICFP				/* IC FIQ Pending reg.		   */ \
+			(*((volatile Word *) io_p2v (_ICFP)))
+#define ICPR				/* IC Pending Reg.		   */ \
+			(*((volatile Word *) io_p2v (_ICPR)))
+#endif /* LANGUAGE == C */
+
+#define IC_GPIO(Nb)			/* GPIO [0..10]			   */ \
+			(0x00000001 << (Nb))
+#define IC_GPIO0	IC_GPIO (0)	/* GPIO  [0]			   */
+#define IC_GPIO1	IC_GPIO (1)	/* GPIO  [1]			   */
+#define IC_GPIO2	IC_GPIO (2)	/* GPIO  [2]			   */
+#define IC_GPIO3	IC_GPIO (3)	/* GPIO  [3]			   */
+#define IC_GPIO4	IC_GPIO (4)	/* GPIO  [4]			   */
+#define IC_GPIO5	IC_GPIO (5)	/* GPIO  [5]			   */
+#define IC_GPIO6	IC_GPIO (6)	/* GPIO  [6]			   */
+#define IC_GPIO7	IC_GPIO (7)	/* GPIO  [7]			   */
+#define IC_GPIO8	IC_GPIO (8)	/* GPIO  [8]			   */
+#define IC_GPIO9	IC_GPIO (9)	/* GPIO  [9]			   */
+#define IC_GPIO10	IC_GPIO (10)	/* GPIO [10]			   */
+#define IC_GPIO11_27	0x00000800	/* GPIO [11:27] (ORed)		   */
+#define IC_LCD		0x00001000	/* LCD controller		   */
+#define IC_Ser0UDC	0x00002000	/* Ser. port 0 UDC		   */
+#define IC_Ser1SDLC	0x00004000	/* Ser. port 1 SDLC		   */
+#define IC_Ser1UART	0x00008000	/* Ser. port 1 UART		   */
+#define IC_Ser2ICP	0x00010000	/* Ser. port 2 ICP		   */
+#define IC_Ser3UART	0x00020000	/* Ser. port 3 UART		   */
+#define IC_Ser4MCP	0x00040000	/* Ser. port 4 MCP		   */
+#define IC_Ser4SSP	0x00080000	/* Ser. port 4 SSP		   */
+#define IC_DMA(Nb)			/* DMA controller channel [0..5]   */ \
+			(0x00100000 << (Nb))
+#define IC_DMA0		IC_DMA (0)	/* DMA controller channel 0	   */
+#define IC_DMA1		IC_DMA (1)	/* DMA controller channel 1	   */
+#define IC_DMA2		IC_DMA (2)	/* DMA controller channel 2	   */
+#define IC_DMA3		IC_DMA (3)	/* DMA controller channel 3	   */
+#define IC_DMA4		IC_DMA (4)	/* DMA controller channel 4	   */
+#define IC_DMA5		IC_DMA (5)	/* DMA controller channel 5	   */
+#define IC_OST(Nb)			/* OS Timer match [0..3]	   */ \
+			(0x04000000 << (Nb))
+#define IC_OST0		IC_OST (0)	/* OS Timer match 0		   */
+#define IC_OST1		IC_OST (1)	/* OS Timer match 1		   */
+#define IC_OST2		IC_OST (2)	/* OS Timer match 2		   */
+#define IC_OST3		IC_OST (3)	/* OS Timer match 3		   */
+#define IC_RTC1Hz	0x40000000	/* RTC 1 Hz clock		   */
+#define IC_RTCAlrm	0x80000000	/* RTC Alarm			   */
+
+#define ICLR_IRQ	0		/* Interrupt ReQuest		   */
+#define ICLR_FIQ	1		/* Fast Interrupt reQuest	   */
+
+#define ICCR_DIM	0x00000001	/* Disable Idle-mode interrupt	   */
+					/* Mask				   */
+#define ICCR_IdleAllInt	(ICCR_DIM*0)	/*  Idle-mode All Interrupt enable */
+					/*  (ICMR ignored)		   */
+#define ICCR_IdleMskInt	(ICCR_DIM*1)	/*  Idle-mode non-Masked Interrupt */
+					/*  enable (ICMR used)		   */
+
+
+/*
+ * Peripheral Pin Controller (PPC) control registers
+ *
+ * Registers
+ *    PPDR		Peripheral Pin Controller (PPC) Pin Direction
+ *			Register (read/write).
+ *    PPSR		Peripheral Pin Controller (PPC) Pin State Register
+ *			(read/write).
+ *    PPAR		Peripheral Pin Controller (PPC) Pin Assignment
+ *			Register (read/write).
+ *    PSDR		Peripheral Pin Controller (PPC) Sleep-mode pin
+ *			Direction Register (read/write).
+ *    PPFR		Peripheral Pin Controller (PPC) Pin Flag Register
+ *			(read).
+ */
+
+#define _PPDR		0x90060000	/* PPC Pin Direction Reg.	   */
+#define _PPSR		0x90060004	/* PPC Pin State Reg.		   */
+#define _PPAR		0x90060008	/* PPC Pin Assignment Reg.	   */
+#define _PSDR		0x9006000C	/* PPC Sleep-mode pin Direction    */
+					/* Reg.				   */
+#define _PPFR		0x90060010	/* PPC Pin Flag Reg.		   */
+
+#if LANGUAGE == C
+#define PPDR				/* PPC Pin Direction Reg.	   */ \
+			(*((volatile Word *) io_p2v (_PPDR)))
+#define PPSR				/* PPC Pin State Reg.		   */ \
+			(*((volatile Word *) io_p2v (_PPSR)))
+#define PPAR				/* PPC Pin Assignment Reg.	   */ \
+			(*((volatile Word *) io_p2v (_PPAR)))
+#define PSDR				/* PPC Sleep-mode pin Direction    */ \
+					/* Reg.				   */ \
+			(*((volatile Word *) io_p2v (_PSDR)))
+#define PPFR				/* PPC Pin Flag Reg.		   */ \
+			(*((volatile Word *) io_p2v (_PPFR)))
+#endif /* LANGUAGE == C */
+
+#define PPC_LDD(Nb)			/* LCD Data [0..7]		   */ \
+			(0x00000001 << (Nb))
+#define PPC_LDD0	PPC_LDD (0)	/* LCD Data [0]			   */
+#define PPC_LDD1	PPC_LDD (1)	/* LCD Data [1]			   */
+#define PPC_LDD2	PPC_LDD (2)	/* LCD Data [2]			   */
+#define PPC_LDD3	PPC_LDD (3)	/* LCD Data [3]			   */
+#define PPC_LDD4	PPC_LDD (4)	/* LCD Data [4]			   */
+#define PPC_LDD5	PPC_LDD (5)	/* LCD Data [5]			   */
+#define PPC_LDD6	PPC_LDD (6)	/* LCD Data [6]			   */
+#define PPC_LDD7	PPC_LDD (7)	/* LCD Data [7]			   */
+#define PPC_L_PCLK	0x00000100	/* LCD Pixel CLocK		   */
+#define PPC_L_LCLK	0x00000200	/* LCD Line CLocK		   */
+#define PPC_L_FCLK	0x00000400	/* LCD Frame CLocK		   */
+#define PPC_L_BIAS	0x00000800	/* LCD AC BIAS			   */
+					/* ser. port 1:			   */
+#define PPC_TXD1	0x00001000	/*  SDLC/UART Transmit Data 1	   */
+#define PPC_RXD1	0x00002000	/*  SDLC/UART Receive Data 1	   */
+					/* ser. port 2:			   */
+#define PPC_TXD2	0x00004000	/*  IPC Transmit Data 2		   */
+#define PPC_RXD2	0x00008000	/*  IPC Receive Data 2		   */
+					/* ser. port 3:			   */
+#define PPC_TXD3	0x00010000	/*  UART Transmit Data 3	   */
+#define PPC_RXD3	0x00020000	/*  UART Receive Data 3		   */
+					/* ser. port 4:			   */
+#define PPC_TXD4	0x00040000	/*  MCP/SSP Transmit Data 4	   */
+#define PPC_RXD4	0x00080000	/*  MCP/SSP Receive Data 4	   */
+#define PPC_SCLK	0x00100000	/*  MCP/SSP Sample CLocK	   */
+#define PPC_SFRM	0x00200000	/*  MCP/SSP Sample FRaMe	   */
+
+#define PPDR_In		0		/* Input			   */
+#define PPDR_Out	1		/* Output			   */
+
+					/* ser. port 1:			   */
+#define PPAR_UPR	0x00001000	/*  UART Pin Reassignment	   */
+#define PPAR_UARTTR	(PPAR_UPR*0)	/*   UART on TXD_1 & RXD_1	   */
+#define PPAR_UARTGPIO	(PPAR_UPR*1)	/*   UART on GPIO [14:15]	   */
+					/* ser. port 4:			   */
+#define PPAR_SPR	0x00040000	/*  SSP Pin Reassignment	   */
+#define PPAR_SSPTRSS	(PPAR_SPR*0)	/*   SSP on TXD_C, RXD_C, SCLK_C,  */
+					/*   & SFRM_C			   */
+#define PPAR_SSPGPIO	(PPAR_SPR*1)	/*   SSP on GPIO [10:13]	   */
+
+#define PSDR_OutL	0		/* Output Low in sleep mode	   */
+#define PSDR_Flt	1		/* Floating (input) in sleep mode  */
+
+#define PPFR_LCD	0x00000001	/* LCD controller		   */
+#define PPFR_SP1TX	0x00001000	/* Ser. Port 1 SDLC/UART Transmit  */
+#define PPFR_SP1RX	0x00002000	/* Ser. Port 1 SDLC/UART Receive   */
+#define PPFR_SP2TX	0x00004000	/* Ser. Port 2 ICP Transmit	   */
+#define PPFR_SP2RX	0x00008000	/* Ser. Port 2 ICP Receive	   */
+#define PPFR_SP3TX	0x00010000	/* Ser. Port 3 UART Transmit	   */
+#define PPFR_SP3RX	0x00020000	/* Ser. Port 3 UART Receive	   */
+#define PPFR_SP4	0x00040000	/* Ser. Port 4 MCP/SSP		   */
+#define PPFR_PerEn	0		/* Peripheral Enabled		   */
+#define PPFR_PPCEn	1		/* PPC Enabled			   */
+
+
+/*
+ * Dynamic Random-Access Memory (DRAM) control registers
+ *
+ * Registers
+ *    MDCNFG		Memory system: Dynamic Random-Access Memory (DRAM)
+ *			CoNFiGuration register (read/write).
+ *    MDCAS0		Memory system: Dynamic Random-Access Memory (DRAM)
+ *			Column Address Strobe (CAS) shift register 0
+ *			(read/write).
+ *    MDCAS1		Memory system: Dynamic Random-Access Memory (DRAM)
+ *			Column Address Strobe (CAS) shift register 1
+ *			(read/write).
+ *    MDCAS2		Memory system: Dynamic Random-Access Memory (DRAM)
+ *			Column Address Strobe (CAS) shift register 2
+ *			(read/write).
+ *
+ * Clocks
+ *    fcpu, Tcpu	Frequency, period of the CPU core clock (CCLK).
+ *    fmem, Tmem	Frequency, period of the memory clock (fmem = fcpu/2).
+ *    fcas, Tcas	Frequency, period of the DRAM CAS shift registers.
+ */
+
+					/* Memory system:		   */
+#define _MDCNFG		0xA0000000	/*  DRAM CoNFiGuration reg.	   */
+#define _MDCAS(Nb)			/*  DRAM CAS shift reg. [0..3]	   */ \
+			(0xA0000004 + (Nb)*4)
+#define _MDCAS0		_MDCAS (0)	/*  DRAM CAS shift reg. 0	   */
+#define _MDCAS1		_MDCAS (1)	/*  DRAM CAS shift reg. 1	   */
+#define _MDCAS2		_MDCAS (2)	/*  DRAM CAS shift reg. 2	   */
+
+#if LANGUAGE == C
+					/* Memory system:		   */
+#define MDCNFG				/*  DRAM CoNFiGuration reg.	   */ \
+			(*((volatile Word *) io_p2v (_MDCNFG)))
+#define MDCAS				/*  DRAM CAS shift reg. [0..3]	   */ \
+			((volatile Word *) io_p2v (_MDCAS (0)))
+#define MDCAS0		(MDCAS [0])	/*  DRAM CAS shift reg. 0	   */
+#define MDCAS1		(MDCAS [1])	/*  DRAM CAS shift reg. 1	   */
+#define MDCAS2		(MDCAS [2])	/*  DRAM CAS shift reg. 2	   */
+
+#elif LANGUAGE == Assembly
+
+#define MDCNFG		(io_p2v(_MDCNFG))
+
+#endif /* LANGUAGE == C */
+
+/* SA1100 MDCNFG values */
+#define MDCNFG_DE(Nb)			/* DRAM Enable bank [0..3]	   */ \
+			(0x00000001 << (Nb))
+#define MDCNFG_DE0	MDCNFG_DE (0)	/* DRAM Enable bank 0		   */
+#define MDCNFG_DE1	MDCNFG_DE (1)	/* DRAM Enable bank 1		   */
+#define MDCNFG_DE2	MDCNFG_DE (2)	/* DRAM Enable bank 2		   */
+#define MDCNFG_DE3	MDCNFG_DE (3)	/* DRAM Enable bank 3		   */
+#define MDCNFG_DRAC	Fld (2, 4)	/* DRAM Row Address Count - 9	   */
+#define MDCNFG_RowAdd(Add)		/*  Row Address count [9..12]	   */ \
+			(((Add) - 9) << FShft (MDCNFG_DRAC))
+#define MDCNFG_CDB2	0x00000040	/* shift reg. Clock Divide By 2    */
+					/* (fcas = fcpu/2)		   */
+#define MDCNFG_TRP	Fld (4, 7)	/* Time RAS Pre-charge - 1 [Tmem]  */
+#define MDCNFG_PrChrg(Tcpu)		/*  Pre-Charge time [2..32 Tcpu]   */ \
+			(((Tcpu) - 2)/2 << FShft (MDCNFG_TRP))
+#define MDCNFG_CeilPrChrg(Tcpu)		/*  Ceil. of PrChrg [2..32 Tcpu]   */ \
+			(((Tcpu) - 1)/2 << FShft (MDCNFG_TRP))
+#define MDCNFG_TRASR	Fld (4, 11)	/* Time RAS Refresh - 1 [Tmem]	   */
+#define MDCNFG_Ref(Tcpu)		/*  Refresh time [2..32 Tcpu]	   */ \
+			(((Tcpu) - 2)/2 << FShft (MDCNFG_TRASR))
+#define MDCNFG_CeilRef(Tcpu)		/*  Ceil. of Ref [2..32 Tcpu]	   */ \
+			(((Tcpu) - 1)/2 << FShft (MDCNFG_TRASR))
+#define MDCNFG_TDL	Fld (2, 15)	/* Time Data Latch [Tcpu]	   */
+#define MDCNFG_DataLtch(Tcpu)		/*  Data Latch delay [0..3 Tcpu]   */ \
+			((Tcpu) << FShft (MDCNFG_TDL))
+#define MDCNFG_DRI	Fld (15, 17)	/* min. DRAM Refresh Interval/4    */
+					/* [Tmem]			   */
+#define MDCNFG_RefInt(Tcpu)		/*  min. Refresh Interval	   */ \
+					/*  [0..262136 Tcpu]		   */ \
+			((Tcpu)/8 << FShft (MDCNFG_DRI))
+
+/* SA1110 MDCNFG values */
+#define MDCNFG_SA1110_DE0	0x00000001	/* DRAM Enable bank 0	     */
+#define MDCNFG_SA1110_DE1	0x00000002	/* DRAM Enable bank 1	     */
+#define MDCNFG_SA1110_DTIM0	0x00000004	/* DRAM timing type 0/1      */
+#define MDCNFG_SA1110_DWID0	0x00000008	/* DRAM bus width 0/1	     */
+#define MDCNFG_SA1110_DRAC0	Fld(3, 4)	/* DRAM row addr bit count   */
+						/* bank 0/1		     */
+#define MDCNFG_SA1110_CDB20	0x00000080	/* Mem Clock divide by 2 0/1 */
+#define MDCNFG_SA1110_TRP0	Fld(3, 8)	/* RAS precharge 0/1	     */
+#define MDCNFG_SA1110_TDL0	Fld(2, 12)	/* Data input latch after CAS*/
+						/* deassertion 0/1	     */
+#define MDCNFG_SA1110_TWR0	Fld(2, 14)	/* SDRAM write recovery 0/1  */
+#define MDCNFG_SA1110_DE2	0x00010000	/* DRAM Enable bank 0	     */
+#define MDCNFG_SA1110_DE3	0x00020000	/* DRAM Enable bank 1	     */
+#define MDCNFG_SA1110_DTIM2	0x00040000	/* DRAM timing type 0/1      */
+#define MDCNFG_SA1110_DWID2	0x00080000	/* DRAM bus width 0/1	     */
+#define MDCNFG_SA1110_DRAC2	Fld(3, 20)	/* DRAM row addr bit count   */
+						/* bank 0/1		     */
+#define MDCNFG_SA1110_CDB22	0x00800000	/* Mem Clock divide by 2 0/1 */
+#define MDCNFG_SA1110_TRP2	Fld(3, 24)	/* RAS precharge 0/1	     */
+#define MDCNFG_SA1110_TDL2	Fld(2, 28)	/* Data input latch after CAS*/
+						/* deassertion 0/1	     */
+#define MDCNFG_SA1110_TWR2	Fld(2, 30)	/* SDRAM write recovery 0/1  */
+
+
+/*
+ * Static memory control registers
+ *
+ * Registers
+ *    MSC0		Memory system: Static memory Control register 0
+ *			(read/write).
+ *    MSC1		Memory system: Static memory Control register 1
+ *			(read/write).
+ *
+ * Clocks
+ *    fcpu, Tcpu	Frequency, period of the CPU core clock (CCLK).
+ *    fmem, Tmem	Frequency, period of the memory clock (fmem = fcpu/2).
+ */
+
+					/* Memory system:		   */
+#define _MSC(Nb)			/*  Static memory Control reg.	   */ \
+					/*  [0..1]			   */ \
+			(0xA0000010 + (Nb)*4)
+#define _MSC0		_MSC (0)	/*  Static memory Control reg. 0   */
+#define _MSC1		_MSC (1)	/*  Static memory Control reg. 1   */
+#define _MSC2		0xA000002C	/*  Static memory Control reg. 2, not contiguous   */
+
+#if LANGUAGE == C
+					/* Memory system:		   */
+#define MSC				/*  Static memory Control reg.	   */ \
+					/*  [0..1]			   */ \
+			((volatile Word *) io_p2v (_MSC (0)))
+#define MSC0		(MSC [0])	/*  Static memory Control reg. 0   */
+#define MSC1		(MSC [1])	/*  Static memory Control reg. 1   */
+#define MSC2		(*(volatile Word *) io_p2v (_MSC2))	/*  Static memory Control reg. 2   */
+
+#elif LANGUAGE == Assembly
+
+#define MSC0		io_p2v(0xa0000010)
+#define MSC1		io_p2v(0xa0000014)
+#define MSC2		io_p2v(0xa000002c)
+
+#endif /* LANGUAGE == C */
+
+#define MSC_Bnk(Nb)			/* static memory Bank [0..3]	   */ \
+			Fld (16, ((Nb) Modulo 2)*16)
+#define MSC0_Bnk0	MSC_Bnk (0)	/* static memory Bank 0		   */
+#define MSC0_Bnk1	MSC_Bnk (1)	/* static memory Bank 1		   */
+#define MSC1_Bnk2	MSC_Bnk (2)	/* static memory Bank 2		   */
+#define MSC1_Bnk3	MSC_Bnk (3)	/* static memory Bank 3		   */
+
+#define MSC_RT		Fld (2, 0)	/* ROM/static memory Type	   */
+#define MSC_NonBrst			/*  Non-Burst static memory	   */ \
+			(0 << FShft (MSC_RT))
+#define MSC_SRAM			/*  32-bit byte-writable SRAM	   */ \
+			(1 << FShft (MSC_RT))
+#define MSC_Brst4			/*  Burst-of-4 static memory	   */ \
+			(2 << FShft (MSC_RT))
+#define MSC_Brst8			/*  Burst-of-8 static memory	   */ \
+			(3 << FShft (MSC_RT))
+#define MSC_RBW		0x0004		/* ROM/static memory Bus Width	   */
+#define MSC_32BitStMem	(MSC_RBW*0)	/*  32-Bit Static Memory	   */
+#define MSC_16BitStMem	(MSC_RBW*1)	/*  16-Bit Static Memory	   */
+#define MSC_RDF		Fld (5, 3)	/* ROM/static memory read Delay    */
+					/* First access - 1(.5) [Tmem]	   */
+#define MSC_1stRdAcc(Tcpu)		/*  1st Read Access time (burst    */ \
+					/*  static memory) [3..65 Tcpu]    */ \
+			((((Tcpu) - 3)/2) << FShft (MSC_RDF))
+#define MSC_Ceil1stRdAcc(Tcpu)		/*  Ceil. of 1stRdAcc [3..65 Tcpu] */ \
+			((((Tcpu) - 2)/2) << FShft (MSC_RDF))
+#define MSC_RdAcc(Tcpu)			/*  Read Access time (non-burst    */ \
+					/*  static memory) [2..64 Tcpu]    */ \
+			((((Tcpu) - 2)/2) << FShft (MSC_RDF))
+#define MSC_CeilRdAcc(Tcpu)		/*  Ceil. of RdAcc [2..64 Tcpu]    */ \
+			((((Tcpu) - 1)/2) << FShft (MSC_RDF))
+#define MSC_RDN		Fld (5, 8)	/* ROM/static memory read Delay    */
+					/* Next access - 1 [Tmem]	   */
+#define MSC_NxtRdAcc(Tcpu)		/*  Next Read Access time (burst   */ \
+					/*  static memory) [2..64 Tcpu]    */ \
+			((((Tcpu) - 2)/2) << FShft (MSC_RDN))
+#define MSC_CeilNxtRdAcc(Tcpu)		/*  Ceil. of NxtRdAcc [2..64 Tcpu] */ \
+			((((Tcpu) - 1)/2) << FShft (MSC_RDN))
+#define MSC_WrAcc(Tcpu)			/*  Write Access time (non-burst   */ \
+					/*  static memory) [2..64 Tcpu]    */ \
+			((((Tcpu) - 2)/2) << FShft (MSC_RDN))
+#define MSC_CeilWrAcc(Tcpu)		/*  Ceil. of WrAcc [2..64 Tcpu]    */ \
+			((((Tcpu) - 1)/2) << FShft (MSC_RDN))
+#define MSC_RRR		Fld (3, 13)	/* ROM/static memory RecoveRy	   */
+					/* time/2 [Tmem]		   */
+#define MSC_Rec(Tcpu)			/*  Recovery time [0..28 Tcpu]	   */ \
+			(((Tcpu)/4) << FShft (MSC_RRR))
+#define MSC_CeilRec(Tcpu)		/*  Ceil. of Rec [0..28 Tcpu]	   */ \
+			((((Tcpu) + 3)/4) << FShft (MSC_RRR))
+
+
+/*
+ * Personal Computer Memory Card International Association (PCMCIA) control
+ * register
+ *
+ * Register
+ *    MECR		Memory system: Expansion memory bus (PCMCIA)
+ *			Configuration Register (read/write).
+ *
+ * Clocks
+ *    fcpu, Tcpu	Frequency, period of the CPU core clock (CCLK).
+ *    fmem, Tmem	Frequency, period of the memory clock (fmem = fcpu/2).
+ *    fbclk, Tbclk	Frequency, period of the PCMCIA clock (BCLK).
+ */
+
+					/* Memory system:		   */
+#define _MECR		0xA0000018	/*  Expansion memory bus (PCMCIA)  */
+					/*  Configuration Reg.		   */
+
+#if LANGUAGE == C
+					/* Memory system:		   */
+#define MECR				/*  Expansion memory bus (PCMCIA)  */ \
+					/*  Configuration Reg.		   */ \
+			(*((volatile Word *) io_p2v (_MECR)))
+#endif /* LANGUAGE == C */
+
+#define MECR_PCMCIA(Nb)			/* PCMCIA [0..1]		   */ \
+			Fld (15, (Nb)*16)
+#define MECR_PCMCIA0	MECR_PCMCIA (0)	/* PCMCIA 0			   */
+#define MECR_PCMCIA1	MECR_PCMCIA (1)	/* PCMCIA 1			   */
+
+#define MECR_BSIO	Fld (5, 0)	/* BCLK Select I/O - 1 [Tmem]	   */
+#define MECR_IOClk(Tcpu)		/*  I/O Clock [2..64 Tcpu]	   */ \
+			((((Tcpu) - 2)/2) << FShft (MECR_BSIO))
+#define MECR_CeilIOClk(Tcpu)		/*  Ceil. of IOClk [2..64 Tcpu]    */ \
+			((((Tcpu) - 1)/2) << FShft (MECR_BSIO))
+#define MECR_BSA	Fld (5, 5)	/* BCLK Select Attribute - 1	   */
+					/* [Tmem]			   */
+#define MECR_AttrClk(Tcpu)		/*  Attribute Clock [2..64 Tcpu]   */ \
+			((((Tcpu) - 2)/2) << FShft (MECR_BSA))
+#define MECR_CeilAttrClk(Tcpu)		/*  Ceil. of AttrClk [2..64 Tcpu]  */ \
+			((((Tcpu) - 1)/2) << FShft (MECR_BSA))
+#define MECR_BSM	Fld (5, 10)	/* BCLK Select Memory - 1 [Tmem]   */
+#define MECR_MemClk(Tcpu)		/*  Memory Clock [2..64 Tcpu]	   */ \
+			((((Tcpu) - 2)/2) << FShft (MECR_BSM))
+#define MECR_CeilMemClk(Tcpu)		/*  Ceil. of MemClk [2..64 Tcpu]   */ \
+			((((Tcpu) - 1)/2) << FShft (MECR_BSM))
+
+/*
+ * On SA1110 only
+ */
+
+#define _MDREFR		0xA000001C
+
+#if LANGUAGE == C
+					/* Memory system:		   */
+#define MDREFR \
+			(*((volatile Word *) io_p2v (_MDREFR)))
+
+#elif LANGUAGE == Assembly
+
+#define MDREFR		(io_p2v(_MDREFR))
+
+#endif /* LANGUAGE == C */
+
+#define MDREFR_TRASR		Fld (4, 0)
+#define MDREFR_DRI		Fld (12, 4)
+#define MDREFR_E0PIN		(1 << 16)
+#define MDREFR_K0RUN		(1 << 17)
+#define MDREFR_K0DB2		(1 << 18)
+#define MDREFR_E1PIN		(1 << 20)
+#define MDREFR_K1RUN		(1 << 21)
+#define MDREFR_K1DB2		(1 << 22)
+#define MDREFR_K2RUN		(1 << 25)
+#define MDREFR_K2DB2		(1 << 26)
+#define MDREFR_EAPD		(1 << 28)
+#define MDREFR_KAPD		(1 << 29)
+#define MDREFR_SLFRSH		(1 << 31)
+
+
+/*
+ * Direct Memory Access (DMA) control registers
+ *
+ * Registers
+ *    DDAR0		Direct Memory Access (DMA) Device Address Register
+ *			channel 0 (read/write).
+ *    DCSR0		Direct Memory Access (DMA) Control and Status
+ *			Register channel 0 (read/write).
+ *    DBSA0		Direct Memory Access (DMA) Buffer Start address
+ *			register A channel 0 (read/write).
+ *    DBTA0		Direct Memory Access (DMA) Buffer Transfer count
+ *			register A channel 0 (read/write).
+ *    DBSB0		Direct Memory Access (DMA) Buffer Start address
+ *			register B channel 0 (read/write).
+ *    DBTB0		Direct Memory Access (DMA) Buffer Transfer count
+ *			register B channel 0 (read/write).
+ *
+ *    DDAR1		Direct Memory Access (DMA) Device Address Register
+ *			channel 1 (read/write).
+ *    DCSR1		Direct Memory Access (DMA) Control and Status
+ *			Register channel 1 (read/write).
+ *    DBSA1		Direct Memory Access (DMA) Buffer Start address
+ *			register A channel 1 (read/write).
+ *    DBTA1		Direct Memory Access (DMA) Buffer Transfer count
+ *			register A channel 1 (read/write).
+ *    DBSB1		Direct Memory Access (DMA) Buffer Start address
+ *			register B channel 1 (read/write).
+ *    DBTB1		Direct Memory Access (DMA) Buffer Transfer count
+ *			register B channel 1 (read/write).
+ *
+ *    DDAR2		Direct Memory Access (DMA) Device Address Register
+ *			channel 2 (read/write).
+ *    DCSR2		Direct Memory Access (DMA) Control and Status
+ *			Register channel 2 (read/write).
+ *    DBSA2		Direct Memory Access (DMA) Buffer Start address
+ *			register A channel 2 (read/write).
+ *    DBTA2		Direct Memory Access (DMA) Buffer Transfer count
+ *			register A channel 2 (read/write).
+ *    DBSB2		Direct Memory Access (DMA) Buffer Start address
+ *			register B channel 2 (read/write).
+ *    DBTB2		Direct Memory Access (DMA) Buffer Transfer count
+ *			register B channel 2 (read/write).
+ *
+ *    DDAR3		Direct Memory Access (DMA) Device Address Register
+ *			channel 3 (read/write).
+ *    DCSR3		Direct Memory Access (DMA) Control and Status
+ *			Register channel 3 (read/write).
+ *    DBSA3		Direct Memory Access (DMA) Buffer Start address
+ *			register A channel 3 (read/write).
+ *    DBTA3		Direct Memory Access (DMA) Buffer Transfer count
+ *			register A channel 3 (read/write).
+ *    DBSB3		Direct Memory Access (DMA) Buffer Start address
+ *			register B channel 3 (read/write).
+ *    DBTB3		Direct Memory Access (DMA) Buffer Transfer count
+ *			register B channel 3 (read/write).
+ *
+ *    DDAR4		Direct Memory Access (DMA) Device Address Register
+ *			channel 4 (read/write).
+ *    DCSR4		Direct Memory Access (DMA) Control and Status
+ *			Register channel 4 (read/write).
+ *    DBSA4		Direct Memory Access (DMA) Buffer Start address
+ *			register A channel 4 (read/write).
+ *    DBTA4		Direct Memory Access (DMA) Buffer Transfer count
+ *			register A channel 4 (read/write).
+ *    DBSB4		Direct Memory Access (DMA) Buffer Start address
+ *			register B channel 4 (read/write).
+ *    DBTB4		Direct Memory Access (DMA) Buffer Transfer count
+ *			register B channel 4 (read/write).
+ *
+ *    DDAR5		Direct Memory Access (DMA) Device Address Register
+ *			channel 5 (read/write).
+ *    DCSR5		Direct Memory Access (DMA) Control and Status
+ *			Register channel 5 (read/write).
+ *    DBSA5		Direct Memory Access (DMA) Buffer Start address
+ *			register A channel 5 (read/write).
+ *    DBTA5		Direct Memory Access (DMA) Buffer Transfer count
+ *			register A channel 5 (read/write).
+ *    DBSB5		Direct Memory Access (DMA) Buffer Start address
+ *			register B channel 5 (read/write).
+ *    DBTB5		Direct Memory Access (DMA) Buffer Transfer count
+ *			register B channel 5 (read/write).
+ */
+
+#define DMASp		0x00000020	/* DMA control reg. Space [byte]   */
+
+#define _DDAR(Nb)			/* DMA Device Address Reg.	   */ \
+					/* channel [0..5]		   */ \
+			(0xB0000000 + (Nb)*DMASp)
+#define _SetDCSR(Nb)			/* Set DMA Control & Status Reg.   */ \
+					/* channel [0..5] (write)	   */ \
+			(0xB0000004 + (Nb)*DMASp)
+#define _ClrDCSR(Nb)			/* Clear DMA Control & Status Reg. */ \
+					/* channel [0..5] (write)	   */ \
+			(0xB0000008 + (Nb)*DMASp)
+#define _RdDCSR(Nb)			/* Read DMA Control & Status Reg.  */ \
+					/* channel [0..5] (read)	   */ \
+			(0xB000000C + (Nb)*DMASp)
+#define _DBSA(Nb)			/* DMA Buffer Start address reg. A */ \
+					/* channel [0..5]		   */ \
+			(0xB0000010 + (Nb)*DMASp)
+#define _DBTA(Nb)			/* DMA Buffer Transfer count	   */ \
+					/* reg. A channel [0..5]	   */ \
+			(0xB0000014 + (Nb)*DMASp)
+#define _DBSB(Nb)			/* DMA Buffer Start address reg. B */ \
+					/* channel [0..5]		   */ \
+			(0xB0000018 + (Nb)*DMASp)
+#define _DBTB(Nb)			/* DMA Buffer Transfer count	   */ \
+					/* reg. B channel [0..5]	   */ \
+			(0xB000001C + (Nb)*DMASp)
+
+#define _DDAR0		_DDAR (0)	/* DMA Device Address Reg.	   */
+					/* channel 0			   */
+#define _SetDCSR0	_SetDCSR (0)	/* Set DMA Control & Status Reg.   */
+					/* channel 0 (write)		   */
+#define _ClrDCSR0	_ClrDCSR (0)	/* Clear DMA Control & Status Reg. */
+					/* channel 0 (write)		   */
+#define _RdDCSR0	_RdDCSR (0)	/* Read DMA Control & Status Reg.  */
+					/* channel 0 (read)		   */
+#define _DBSA0		_DBSA (0)	/* DMA Buffer Start address reg. A */
+					/* channel 0			   */
+#define _DBTA0		_DBTA (0)	/* DMA Buffer Transfer count	   */
+					/* reg. A channel 0		   */
+#define _DBSB0		_DBSB (0)	/* DMA Buffer Start address reg. B */
+					/* channel 0			   */
+#define _DBTB0		_DBTB (0)	/* DMA Buffer Transfer count	   */
+					/* reg. B channel 0		   */
+
+#define _DDAR1		_DDAR (1)	/* DMA Device Address Reg.	   */
+					/* channel 1			   */
+#define _SetDCSR1	_SetDCSR (1)	/* Set DMA Control & Status Reg.   */
+					/* channel 1 (write)		   */
+#define _ClrDCSR1	_ClrDCSR (1)	/* Clear DMA Control & Status Reg. */
+					/* channel 1 (write)		   */
+#define _RdDCSR1	_RdDCSR (1)	/* Read DMA Control & Status Reg.  */
+					/* channel 1 (read)		   */
+#define _DBSA1		_DBSA (1)	/* DMA Buffer Start address reg. A */
+					/* channel 1			   */
+#define _DBTA1		_DBTA (1)	/* DMA Buffer Transfer count	   */
+					/* reg. A channel 1		   */
+#define _DBSB1		_DBSB (1)	/* DMA Buffer Start address reg. B */
+					/* channel 1			   */
+#define _DBTB1		_DBTB (1)	/* DMA Buffer Transfer count	   */
+					/* reg. B channel 1		   */
+
+#define _DDAR2		_DDAR (2)	/* DMA Device Address Reg.	   */
+					/* channel 2			   */
+#define _SetDCSR2	_SetDCSR (2)	/* Set DMA Control & Status Reg.   */
+					/* channel 2 (write)		   */
+#define _ClrDCSR2	_ClrDCSR (2)	/* Clear DMA Control & Status Reg. */
+					/* channel 2 (write)		   */
+#define _RdDCSR2	_RdDCSR (2)	/* Read DMA Control & Status Reg.  */
+					/* channel 2 (read)		   */
+#define _DBSA2		_DBSA (2)	/* DMA Buffer Start address reg. A */
+					/* channel 2			   */
+#define _DBTA2		_DBTA (2)	/* DMA Buffer Transfer count	   */
+					/* reg. A channel 2		   */
+#define _DBSB2		_DBSB (2)	/* DMA Buffer Start address reg. B */
+					/* channel 2			   */
+#define _DBTB2		_DBTB (2)	/* DMA Buffer Transfer count	   */
+					/* reg. B channel 2		   */
+
+#define _DDAR3		_DDAR (3)	/* DMA Device Address Reg.	   */
+					/* channel 3			   */
+#define _SetDCSR3	_SetDCSR (3)	/* Set DMA Control & Status Reg.   */
+					/* channel 3 (write)		   */
+#define _ClrDCSR3	_ClrDCSR (3)	/* Clear DMA Control & Status Reg. */
+					/* channel 3 (write)		   */
+#define _RdDCSR3	_RdDCSR (3)	/* Read DMA Control & Status Reg.  */
+					/* channel 3 (read)		   */
+#define _DBSA3		_DBSA (3)	/* DMA Buffer Start address reg. A */
+					/* channel 3			   */
+#define _DBTA3		_DBTA (3)	/* DMA Buffer Transfer count	   */
+					/* reg. A channel 3		   */
+#define _DBSB3		_DBSB (3)	/* DMA Buffer Start address reg. B */
+					/* channel 3			   */
+#define _DBTB3		_DBTB (3)	/* DMA Buffer Transfer count	   */
+					/* reg. B channel 3		   */
+
+#define _DDAR4		_DDAR (4)	/* DMA Device Address Reg.	   */
+					/* channel 4			   */
+#define _SetDCSR4	_SetDCSR (4)	/* Set DMA Control & Status Reg.   */
+					/* channel 4 (write)		   */
+#define _ClrDCSR4	_ClrDCSR (4)	/* Clear DMA Control & Status Reg. */
+					/* channel 4 (write)		   */
+#define _RdDCSR4	_RdDCSR (4)	/* Read DMA Control & Status Reg.  */
+					/* channel 4 (read)		   */
+#define _DBSA4		_DBSA (4)	/* DMA Buffer Start address reg. A */
+					/* channel 4			   */
+#define _DBTA4		_DBTA (4)	/* DMA Buffer Transfer count	   */
+					/* reg. A channel 4		   */
+#define _DBSB4		_DBSB (4)	/* DMA Buffer Start address reg. B */
+					/* channel 4			   */
+#define _DBTB4		_DBTB (4)	/* DMA Buffer Transfer count	   */
+					/* reg. B channel 4		   */
+
+#define _DDAR5		_DDAR (5)	/* DMA Device Address Reg.	   */
+					/* channel 5			   */
+#define _SetDCSR5	_SetDCSR (5)	/* Set DMA Control & Status Reg.   */
+					/* channel 5 (write)		   */
+#define _ClrDCSR5	_ClrDCSR (5)	/* Clear DMA Control & Status Reg. */
+					/* channel 5 (write)		   */
+#define _RdDCSR5	_RdDCSR (5)	/* Read DMA Control & Status Reg.  */
+					/* channel 5 (read)		   */
+#define _DBSA5		_DBSA (5)	/* DMA Buffer Start address reg. A */
+					/* channel 5			   */
+#define _DBTA5		_DBTA (5)	/* DMA Buffer Transfer count	   */
+					/* reg. A channel 5		   */
+#define _DBSB5		_DBSB (5)	/* DMA Buffer Start address reg. B */
+					/* channel 5			   */
+#define _DBTB5		_DBTB (5)	/* DMA Buffer Transfer count	   */
+					/* reg. B channel 5		   */
+
+#if LANGUAGE == C
+
+#define DDAR0				/* DMA Device Address Reg.	   */ \
+					/* channel 0			   */ \
+			(*((volatile Word *) io_p2v (_DDAR0)))
+#define SetDCSR0			/* Set DMA Control & Status Reg.   */ \
+					/* channel 0 (write)		   */ \
+			(*((volatile Word *) io_p2v (_SetDCSR0)))
+#define ClrDCSR0			/* Clear DMA Control & Status Reg. */ \
+					/* channel 0 (write)		   */ \
+			(*((volatile Word *) io_p2v (_ClrDCSR0)))
+#define RdDCSR0				/* Read DMA Control & Status Reg.  */ \
+					/* channel 0 (read)		   */ \
+			(*((volatile Word *) io_p2v (_RdDCSR0)))
+#define DBSA0				/* DMA Buffer Start address reg. A */ \
+					/* channel 0			   */ \
+			(*((volatile Address *) io_p2v (_DBSA0)))
+#define DBTA0				/* DMA Buffer Transfer count	   */ \
+					/* reg. A channel 0		   */ \
+			(*((volatile Word *) io_p2v (_DBTA0)))
+#define DBSB0				/* DMA Buffer Start address reg. B */ \
+					/* channel 0			   */ \
+			(*((volatile Address *) io_p2v (_DBSB0)))
+#define DBTB0				/* DMA Buffer Transfer count	   */ \
+					/* reg. B channel 0		   */ \
+			(*((volatile Word *) io_p2v (_DBTB0)))
+
+#define DDAR1				/* DMA Device Address Reg.	   */ \
+					/* channel 1			   */ \
+			(*((volatile Word *) io_p2v (_DDAR1)))
+#define SetDCSR1			/* Set DMA Control & Status Reg.   */ \
+					/* channel 1 (write)		   */ \
+			(*((volatile Word *) io_p2v (_SetDCSR1)))
+#define ClrDCSR1			/* Clear DMA Control & Status Reg. */ \
+					/* channel 1 (write)		   */ \
+			(*((volatile Word *) io_p2v (_ClrDCSR1)))
+#define RdDCSR1				/* Read DMA Control & Status Reg.  */ \
+					/* channel 1 (read)		   */ \
+			(*((volatile Word *) io_p2v (_RdDCSR1)))
+#define DBSA1				/* DMA Buffer Start address reg. A */ \
+					/* channel 1			   */ \
+			(*((volatile Address *) io_p2v (_DBSA1)))
+#define DBTA1				/* DMA Buffer Transfer count	   */ \
+					/* reg. A channel 1		   */ \
+			(*((volatile Word *) io_p2v (_DBTA1)))
+#define DBSB1				/* DMA Buffer Start address reg. B */ \
+					/* channel 1			   */ \
+			(*((volatile Address *) io_p2v (_DBSB1)))
+#define DBTB1				/* DMA Buffer Transfer count	   */ \
+					/* reg. B channel 1		   */ \
+			(*((volatile Word *) io_p2v (_DBTB1)))
+
+#define DDAR2				/* DMA Device Address Reg.	   */ \
+					/* channel 2			   */ \
+			(*((volatile Word *) io_p2v (_DDAR2)))
+#define SetDCSR2			/* Set DMA Control & Status Reg.   */ \
+					/* channel 2 (write)		   */ \
+			(*((volatile Word *) io_p2v (_SetDCSR2)))
+#define ClrDCSR2			/* Clear DMA Control & Status Reg. */ \
+					/* channel 2 (write)		   */ \
+			(*((volatile Word *) io_p2v (_ClrDCSR2)))
+#define RdDCSR2				/* Read DMA Control & Status Reg.  */ \
+					/* channel 2 (read)		   */ \
+			(*((volatile Word *) io_p2v (_RdDCSR2)))
+#define DBSA2				/* DMA Buffer Start address reg. A */ \
+					/* channel 2			   */ \
+			(*((volatile Address *) io_p2v (_DBSA2)))
+#define DBTA2				/* DMA Buffer Transfer count	   */ \
+					/* reg. A channel 2		   */ \
+			(*((volatile Word *) io_p2v (_DBTA2)))
+#define DBSB2				/* DMA Buffer Start address reg. B */ \
+					/* channel 2			   */ \
+			(*((volatile Address *) io_p2v (_DBSB2)))
+#define DBTB2				/* DMA Buffer Transfer count	   */ \
+					/* reg. B channel 2		   */ \
+			(*((volatile Word *) io_p2v (_DBTB2)))
+
+#define DDAR3				/* DMA Device Address Reg.	   */ \
+					/* channel 3			   */ \
+			(*((volatile Word *) io_p2v (_DDAR3)))
+#define SetDCSR3			/* Set DMA Control & Status Reg.   */ \
+					/* channel 3 (write)		   */ \
+			(*((volatile Word *) io_p2v (_SetDCSR3)))
+#define ClrDCSR3			/* Clear DMA Control & Status Reg. */ \
+					/* channel 3 (write)		   */ \
+			(*((volatile Word *) io_p2v (_ClrDCSR3)))
+#define RdDCSR3				/* Read DMA Control & Status Reg.  */ \
+					/* channel 3 (read)		   */ \
+			(*((volatile Word *) io_p2v (_RdDCSR3)))
+#define DBSA3				/* DMA Buffer Start address reg. A */ \
+					/* channel 3			   */ \
+			(*((volatile Address *) io_p2v (_DBSA3)))
+#define DBTA3				/* DMA Buffer Transfer count	   */ \
+					/* reg. A channel 3		   */ \
+			(*((volatile Word *) io_p2v (_DBTA3)))
+#define DBSB3				/* DMA Buffer Start address reg. B */ \
+					/* channel 3			   */ \
+			(*((volatile Address *) io_p2v (_DBSB3)))
+#define DBTB3				/* DMA Buffer Transfer count	   */ \
+					/* reg. B channel 3		   */ \
+			(*((volatile Word *) io_p2v (_DBTB3)))
+
+#define DDAR4				/* DMA Device Address Reg.	   */ \
+					/* channel 4			   */ \
+			(*((volatile Word *) io_p2v (_DDAR4)))
+#define SetDCSR4			/* Set DMA Control & Status Reg.   */ \
+					/* channel 4 (write)		   */ \
+			(*((volatile Word *) io_p2v (_SetDCSR4)))
+#define ClrDCSR4			/* Clear DMA Control & Status Reg. */ \
+					/* channel 4 (write)		   */ \
+			(*((volatile Word *) io_p2v (_ClrDCSR4)))
+#define RdDCSR4				/* Read DMA Control & Status Reg.  */ \
+					/* channel 4 (read)		   */ \
+			(*((volatile Word *) io_p2v (_RdDCSR4)))
+#define DBSA4				/* DMA Buffer Start address reg. A */ \
+					/* channel 4			   */ \
+			(*((volatile Address *) io_p2v (_DBSA4)))
+#define DBTA4				/* DMA Buffer Transfer count	   */ \
+					/* reg. A channel 4		   */ \
+			(*((volatile Word *) io_p2v (_DBTA4)))
+#define DBSB4				/* DMA Buffer Start address reg. B */ \
+					/* channel 4			   */ \
+			(*((volatile Address *) io_p2v (_DBSB4)))
+#define DBTB4				/* DMA Buffer Transfer count	   */ \
+					/* reg. B channel 4		   */ \
+			(*((volatile Word *) io_p2v (_DBTB4)))
+
+#define DDAR5				/* DMA Device Address Reg.	   */ \
+					/* channel 5			   */ \
+			(*((volatile Word *) io_p2v (_DDAR5)))
+#define SetDCSR5			/* Set DMA Control & Status Reg.   */ \
+					/* channel 5 (write)		   */ \
+			(*((volatile Word *) io_p2v (_SetDCSR5)))
+#define ClrDCSR5			/* Clear DMA Control & Status Reg. */ \
+					/* channel 5 (write)		   */ \
+			(*((volatile Word *) io_p2v (_ClrDCSR5)))
+#define RdDCSR5				/* Read DMA Control & Status Reg.  */ \
+					/* channel 5 (read)		   */ \
+			(*((volatile Word *) io_p2v (_RdDCSR5)))
+#define DBSA5				/* DMA Buffer Start address reg. A */ \
+					/* channel 5			   */ \
+			(*((volatile Address *) io_p2v (_DBSA5)))
+#define DBTA5				/* DMA Buffer Transfer count	   */ \
+					/* reg. A channel 5		   */ \
+			(*((volatile Word *) io_p2v (_DBTA5)))
+#define DBSB5				/* DMA Buffer Start address reg. B */ \
+					/* channel 5			   */ \
+			(*((volatile Address *) io_p2v (_DBSB5)))
+#define DBTB5				/* DMA Buffer Transfer count	   */ \
+					/* reg. B channel 5		   */ \
+			(*((volatile Word *) io_p2v (_DBTB5)))
+
+#endif /* LANGUAGE == C */
+
+#define DDAR_RW		0x00000001	/* device data Read/Write	   */
+#define DDAR_DevWr	(DDAR_RW*0)	/*  Device data Write		   */
+					/*  (memory -> device)		   */
+#define DDAR_DevRd	(DDAR_RW*1)	/*  Device data Read		   */
+					/*  (device -> memory)		   */
+#define DDAR_E		0x00000002	/* big/little Endian device	   */
+#define DDAR_LtlEnd	(DDAR_E*0)	/*  Little Endian device	   */
+#define DDAR_BigEnd	(DDAR_E*1)	/*  Big Endian device		   */
+#define DDAR_BS		0x00000004	/* device Burst Size		   */
+#define DDAR_Brst4	(DDAR_BS*0)	/*  Burst-of-4 device		   */
+#define DDAR_Brst8	(DDAR_BS*1)	/*  Burst-of-8 device		   */
+#define DDAR_DW		0x00000008	/* device Data Width		   */
+#define DDAR_8BitDev	(DDAR_DW*0)	/*  8-Bit Device		   */
+#define DDAR_16BitDev	(DDAR_DW*1)	/*  16-Bit Device		   */
+#define DDAR_DS		Fld (4, 4)	/* Device Select		   */
+#define DDAR_Ser0UDCTr			/*  Ser. port 0 UDC Transmit	   */ \
+			(0x0 << FShft (DDAR_DS))
+#define DDAR_Ser0UDCRc			/*  Ser. port 0 UDC Receive	   */ \
+			(0x1 << FShft (DDAR_DS))
+#define DDAR_Ser1SDLCTr			/*  Ser. port 1 SDLC Transmit	   */ \
+			(0x2 << FShft (DDAR_DS))
+#define DDAR_Ser1SDLCRc			/*  Ser. port 1 SDLC Receive	   */ \
+			(0x3 << FShft (DDAR_DS))
+#define DDAR_Ser1UARTTr			/*  Ser. port 1 UART Transmit	   */ \
+			(0x4 << FShft (DDAR_DS))
+#define DDAR_Ser1UARTRc			/*  Ser. port 1 UART Receive	   */ \
+			(0x5 << FShft (DDAR_DS))
+#define DDAR_Ser2ICPTr			/*  Ser. port 2 ICP Transmit	   */ \
+			(0x6 << FShft (DDAR_DS))
+#define DDAR_Ser2ICPRc			/*  Ser. port 2 ICP Receive	   */ \
+			(0x7 << FShft (DDAR_DS))
+#define DDAR_Ser3UARTTr			/*  Ser. port 3 UART Transmit	   */ \
+			(0x8 << FShft (DDAR_DS))
+#define DDAR_Ser3UARTRc			/*  Ser. port 3 UART Receive	   */ \
+			(0x9 << FShft (DDAR_DS))
+#define DDAR_Ser4MCP0Tr			/*  Ser. port 4 MCP 0 Transmit	   */ \
+					/*  (audio)			   */ \
+			(0xA << FShft (DDAR_DS))
+#define DDAR_Ser4MCP0Rc			/*  Ser. port 4 MCP 0 Receive	   */ \
+					/*  (audio)			   */ \
+			(0xB << FShft (DDAR_DS))
+#define DDAR_Ser4MCP1Tr			/*  Ser. port 4 MCP 1 Transmit	   */ \
+					/*  (telecom)			   */ \
+			(0xC << FShft (DDAR_DS))
+#define DDAR_Ser4MCP1Rc			/*  Ser. port 4 MCP 1 Receive	   */ \
+					/*  (telecom)			   */ \
+			(0xD << FShft (DDAR_DS))
+#define DDAR_Ser4SSPTr			/*  Ser. port 4 SSP Transmit	   */ \
+			(0xE << FShft (DDAR_DS))
+#define DDAR_Ser4SSPRc			/*  Ser. port 4 SSP Receive	   */ \
+			(0xF << FShft (DDAR_DS))
+#define DDAR_DA		Fld (24, 8)	/* Device Address		   */
+#define DDAR_DevAdd(Add)		/*  Device Address		   */ \
+			(((Add) & 0xF0000000) | \
+			 (((Add) & 0X003FFFFC) << (FShft (DDAR_DA) - 2)))
+#define DDAR_Ser0UDCWr			/* Ser. port 0 UDC Write	   */ \
+			(DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \
+			 DDAR_Ser0UDCTr + DDAR_DevAdd (_Ser0UDCDR))
+#define DDAR_Ser0UDCRd			/* Ser. port 0 UDC Read		   */ \
+			(DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \
+			 DDAR_Ser0UDCRc + DDAR_DevAdd (_Ser0UDCDR))
+#define DDAR_Ser1UARTWr			/* Ser. port 1 UART Write	   */ \
+			(DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
+			 DDAR_Ser1UARTTr + DDAR_DevAdd (_Ser1UTDR))
+#define DDAR_Ser1UARTRd			/* Ser. port 1 UART Read	   */ \
+			(DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
+			 DDAR_Ser1UARTRc + DDAR_DevAdd (_Ser1UTDR))
+#define DDAR_Ser1SDLCWr			/* Ser. port 1 SDLC Write	   */ \
+			(DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
+			 DDAR_Ser1SDLCTr + DDAR_DevAdd (_Ser1SDDR))
+#define DDAR_Ser1SDLCRd			/* Ser. port 1 SDLC Read	   */ \
+			(DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
+			 DDAR_Ser1SDLCRc + DDAR_DevAdd (_Ser1SDDR))
+#define DDAR_Ser2UARTWr			/* Ser. port 2 UART Write	   */ \
+			(DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
+			 DDAR_Ser2ICPTr + DDAR_DevAdd (_Ser2UTDR))
+#define DDAR_Ser2UARTRd			/* Ser. port 2 UART Read	   */ \
+			(DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
+			 DDAR_Ser2ICPRc + DDAR_DevAdd (_Ser2UTDR))
+#define DDAR_Ser2HSSPWr			/* Ser. port 2 HSSP Write	   */ \
+			(DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \
+			 DDAR_Ser2ICPTr + DDAR_DevAdd (_Ser2HSDR))
+#define DDAR_Ser2HSSPRd			/* Ser. port 2 HSSP Read	   */ \
+			(DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \
+			 DDAR_Ser2ICPRc + DDAR_DevAdd (_Ser2HSDR))
+#define DDAR_Ser3UARTWr			/* Ser. port 3 UART Write	   */ \
+			(DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
+			 DDAR_Ser3UARTTr + DDAR_DevAdd (_Ser3UTDR))
+#define DDAR_Ser3UARTRd			/* Ser. port 3 UART Read	   */ \
+			(DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
+			 DDAR_Ser3UARTRc + DDAR_DevAdd (_Ser3UTDR))
+#define DDAR_Ser4MCP0Wr			/* Ser. port 4 MCP 0 Write (audio) */ \
+			(DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
+			 DDAR_Ser4MCP0Tr + DDAR_DevAdd (_Ser4MCDR0))
+#define DDAR_Ser4MCP0Rd			/* Ser. port 4 MCP 0 Read (audio)  */ \
+			(DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
+			 DDAR_Ser4MCP0Rc + DDAR_DevAdd (_Ser4MCDR0))
+#define DDAR_Ser4MCP1Wr			/* Ser. port 4 MCP 1 Write	   */ \
+					/* (telecom)			   */ \
+			(DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
+			 DDAR_Ser4MCP1Tr + DDAR_DevAdd (_Ser4MCDR1))
+#define DDAR_Ser4MCP1Rd			/* Ser. port 4 MCP 1 Read	   */ \
+					/* (telecom)			   */ \
+			(DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
+			 DDAR_Ser4MCP1Rc + DDAR_DevAdd (_Ser4MCDR1))
+#define DDAR_Ser4SSPWr			/* Ser. port 4 SSP Write (16 bits) */ \
+			(DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
+			 DDAR_Ser4SSPTr + DDAR_DevAdd (_Ser4SSDR))
+#define DDAR_Ser4SSPRd			/* Ser. port 4 SSP Read (16 bits)  */ \
+			(DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
+			 DDAR_Ser4SSPRc + DDAR_DevAdd (_Ser4SSDR))
+
+#define DCSR_RUN	0x00000001	/* DMA RUNing			   */
+#define DCSR_IE		0x00000002	/* DMA Interrupt Enable		   */
+#define DCSR_ERROR	0x00000004	/* DMA ERROR			   */
+#define DCSR_DONEA	0x00000008	/* DONE DMA transfer buffer A	   */
+#define DCSR_STRTA	0x00000010	/* STaRTed DMA transfer buffer A   */
+#define DCSR_DONEB	0x00000020	/* DONE DMA transfer buffer B	   */
+#define DCSR_STRTB	0x00000040	/* STaRTed DMA transfer buffer B   */
+#define DCSR_BIU	0x00000080	/* DMA Buffer In Use		   */
+#define DCSR_BufA	(DCSR_BIU*0)	/*  DMA Buffer A in use		   */
+#define DCSR_BufB	(DCSR_BIU*1)	/*  DMA Buffer B in use		   */
+
+#define DBT_TC		Fld (13, 0)	/* Transfer Count		   */
+#define DBTA_TCA	DBT_TC		/* Transfer Count buffer A	   */
+#define DBTB_TCB	DBT_TC		/* Transfer Count buffer B	   */
+
+
+/*
+ * Liquid Crystal Display (LCD) control registers
+ *
+ * Registers
+ *    LCCR0		Liquid Crystal Display (LCD) Control Register 0
+ *			(read/write).
+ *			[Bits LDM, BAM, and ERM are only implemented in
+ *			versions 2.0 (rev. = 8) and higher of the StrongARM
+ *			SA-1100.]
+ *    LCSR		Liquid Crystal Display (LCD) Status Register
+ *			(read/write).
+ *			[Bit LDD can be only read in versions 1.0 (rev. = 1)
+ *			and 1.1 (rev. = 2) of the StrongARM SA-1100, it can be
+ *			read and written (cleared) in versions 2.0 (rev. = 8)
+ *			and higher.]
+ *    DBAR1		Liquid Crystal Display (LCD) Direct Memory Access
+ *			(DMA) Base Address Register channel 1 (read/write).
+ *    DCAR1		Liquid Crystal Display (LCD) Direct Memory Access
+ *			(DMA) Current Address Register channel 1 (read).
+ *    DBAR2		Liquid Crystal Display (LCD) Direct Memory Access
+ *			(DMA) Base Address Register channel 2 (read/write).
+ *    DCAR2		Liquid Crystal Display (LCD) Direct Memory Access
+ *			(DMA) Current Address Register channel 2 (read).
+ *    LCCR1		Liquid Crystal Display (LCD) Control Register 1
+ *			(read/write).
+ *			[The LCCR1 register can be only written in
+ *			versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
+ *			StrongARM SA-1100, it can be written and read in
+ *			versions 2.0 (rev. = 8) and higher.]
+ *    LCCR2		Liquid Crystal Display (LCD) Control Register 2
+ *			(read/write).
+ *			[The LCCR1 register can be only written in
+ *			versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
+ *			StrongARM SA-1100, it can be written and read in
+ *			versions 2.0 (rev. = 8) and higher.]
+ *    LCCR3		Liquid Crystal Display (LCD) Control Register 3
+ *			(read/write).
+ *			[The LCCR1 register can be only written in
+ *			versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
+ *			StrongARM SA-1100, it can be written and read in
+ *			versions 2.0 (rev. = 8) and higher. Bit PCP is only
+ *			implemented in versions 2.0 (rev. = 8) and higher of
+ *			the StrongARM SA-1100.]
+ *
+ * Clocks
+ *    fcpu, Tcpu	Frequency, period of the CPU core clock (CCLK).
+ *    fmem, Tmem	Frequency, period of the memory clock (fmem = fcpu/2).
+ *    fpix, Tpix	Frequency, period of the pixel clock.
+ *    fln, Tln		Frequency, period of the line clock.
+ *    fac, Tac		Frequency, period of the AC bias clock.
+ */
+
+#define LCD_PEntrySp	2		/* LCD Palette Entry Space [byte]  */
+#define LCD_4BitPSp			/* LCD 4-Bit pixel Palette Space   */ \
+					/* [byte]			   */ \
+			(16*LCD_PEntrySp)
+#define LCD_8BitPSp			/* LCD 8-Bit pixel Palette Space   */ \
+					/* [byte]			   */ \
+			(256*LCD_PEntrySp)
+#define LCD_12_16BitPSp			/* LCD 12/16-Bit pixel		   */ \
+					/* dummy-Palette Space [byte]	   */ \
+			(16*LCD_PEntrySp)
+
+#define LCD_PGrey	Fld (4, 0)	/* LCD Palette entry Grey value    */
+#define LCD_PBlue	Fld (4, 0)	/* LCD Palette entry Blue value    */
+#define LCD_PGreen	Fld (4, 4)	/* LCD Palette entry Green value   */
+#define LCD_PRed	Fld (4, 8)	/* LCD Palette entry Red value	   */
+#define LCD_PBS		Fld (2, 12)	/* LCD Pixel Bit Size		   */
+#define LCD_4Bit			/*  LCD 4-Bit pixel mode	   */ \
+			(0 << FShft (LCD_PBS))
+#define LCD_8Bit			/*  LCD 8-Bit pixel mode	   */ \
+			(1 << FShft (LCD_PBS))
+#define LCD_12_16Bit			/*  LCD 12/16-Bit pixel mode	   */ \
+			(2 << FShft (LCD_PBS))
+
+#define LCD_Int0_0	0x0		/* LCD Intensity =   0.0% =  0	   */
+#define LCD_Int11_1	0x1		/* LCD Intensity =  11.1% =  1/9   */
+#define LCD_Int20_0	0x2		/* LCD Intensity =  20.0% =  1/5   */
+#define LCD_Int26_7	0x3		/* LCD Intensity =  26.7% =  4/15  */
+#define LCD_Int33_3	0x4		/* LCD Intensity =  33.3% =  3/9   */
+#define LCD_Int40_0	0x5		/* LCD Intensity =  40.0% =  2/5   */
+#define LCD_Int44_4	0x6		/* LCD Intensity =  44.4% =  4/9   */
+#define LCD_Int50_0	0x7		/* LCD Intensity =  50.0% =  1/2   */
+#define LCD_Int55_6	0x8		/* LCD Intensity =  55.6% =  5/9   */
+#define LCD_Int60_0	0x9		/* LCD Intensity =  60.0% =  3/5   */
+#define LCD_Int66_7	0xA		/* LCD Intensity =  66.7% =  6/9   */
+#define LCD_Int73_3	0xB		/* LCD Intensity =  73.3% = 11/15  */
+#define LCD_Int80_0	0xC		/* LCD Intensity =  80.0% =  4/5   */
+#define LCD_Int88_9	0xD		/* LCD Intensity =  88.9% =  8/9   */
+#define LCD_Int100_0	0xE		/* LCD Intensity = 100.0% =  1	   */
+#define LCD_Int100_0A	0xF		/* LCD Intensity = 100.0% =  1	   */
+					/* (Alternative)		   */
+
+#define _LCCR0		0xB0100000	/* LCD Control Reg. 0		   */
+#define _LCSR		0xB0100004	/* LCD Status Reg.		   */
+#define _DBAR1		0xB0100010	/* LCD DMA Base Address Reg.	   */
+					/* channel 1			   */
+#define _DCAR1		0xB0100014	/* LCD DMA Current Address Reg.    */
+					/* channel 1			   */
+#define _DBAR2		0xB0100018	/* LCD DMA Base Address Reg.	   */
+					/* channel 2			   */
+#define _DCAR2		0xB010001C	/* LCD DMA Current Address Reg.    */
+					/* channel 2			   */
+#define _LCCR1		0xB0100020	/* LCD Control Reg. 1		   */
+#define _LCCR2		0xB0100024	/* LCD Control Reg. 2		   */
+#define _LCCR3		0xB0100028	/* LCD Control Reg. 3		   */
+
+#if LANGUAGE == C
+#define LCCR0				/* LCD Control Reg. 0		   */ \
+			(*((volatile Word *) io_p2v (_LCCR0)))
+#define LCSR				/* LCD Status Reg.		   */ \
+			(*((volatile Word *) io_p2v (_LCSR)))
+#define DBAR1				/* LCD DMA Base Address Reg.	   */ \
+					/* channel 1			   */ \
+			(*((volatile Address *) io_p2v (_DBAR1)))
+#define DCAR1				/* LCD DMA Current Address Reg.    */ \
+					/* channel 1			   */ \
+			(*((volatile Address *) io_p2v (_DCAR1)))
+#define DBAR2				/* LCD DMA Base Address Reg.	   */ \
+					/* channel 2			   */ \
+			(*((volatile Address *) io_p2v (_DBAR2)))
+#define DCAR2				/* LCD DMA Current Address Reg.    */ \
+					/* channel 2			   */ \
+			(*((volatile Address *) io_p2v (_DCAR2)))
+#define LCCR1				/* LCD Control Reg. 1		   */ \
+			(*((volatile Word *) io_p2v (_LCCR1)))
+#define LCCR2				/* LCD Control Reg. 2		   */ \
+			(*((volatile Word *) io_p2v (_LCCR2)))
+#define LCCR3				/* LCD Control Reg. 3		   */ \
+			(*((volatile Word *) io_p2v (_LCCR3)))
+#endif /* LANGUAGE == C */
+
+#define LCCR0_LEN	0x00000001	/* LCD ENable			   */
+#define LCCR0_CMS	0x00000002	/* Color/Monochrome display Select */
+#define LCCR0_Color	(LCCR0_CMS*0)	/*  Color display		   */
+#define LCCR0_Mono	(LCCR0_CMS*1)	/*  Monochrome display		   */
+#define LCCR0_SDS	0x00000004	/* Single/Dual panel display	   */
+					/* Select			   */
+#define LCCR0_Sngl	(LCCR0_SDS*0)	/*  Single panel display	   */
+#define LCCR0_Dual	(LCCR0_SDS*1)	/*  Dual panel display		   */
+#define LCCR0_LDM	0x00000008	/* LCD Disable done (LDD)	   */
+					/* interrupt Mask (disable)	   */
+#define LCCR0_BAM	0x00000010	/* Base Address update (BAU)	   */
+					/* interrupt Mask (disable)	   */
+#define LCCR0_ERM	0x00000020	/* LCD ERror (BER, IOL, IUL, IOU,  */
+					/* IUU, OOL, OUL, OOU, and OUU)    */
+					/* interrupt Mask (disable)	   */
+#define LCCR0_PAS	0x00000080	/* Passive/Active display Select   */
+#define LCCR0_Pas	(LCCR0_PAS*0)	/*  Passive display (STN)	   */
+#define LCCR0_Act	(LCCR0_PAS*1)	/*  Active display (TFT)	   */
+#define LCCR0_BLE	0x00000100	/* Big/Little Endian select	   */
+#define LCCR0_LtlEnd	(LCCR0_BLE*0)	/*  Little Endian frame buffer	   */
+#define LCCR0_BigEnd	(LCCR0_BLE*1)	/*  Big Endian frame buffer	   */
+#define LCCR0_DPD	0x00000200	/* Double Pixel Data (monochrome   */
+					/* display mode)		   */
+#define LCCR0_4PixMono	(LCCR0_DPD*0)	/*  4-Pixel/clock Monochrome	   */
+					/*  display			   */
+#define LCCR0_8PixMono	(LCCR0_DPD*1)	/*  8-Pixel/clock Monochrome	   */
+					/*  display			   */
+#define LCCR0_PDD	Fld (8, 12)	/* Palette DMA request Delay	   */
+					/* [Tmem]			   */
+#define LCCR0_DMADel(Tcpu)		/*  palette DMA request Delay	   */ \
+					/*  [0..510 Tcpu]		   */ \
+			((Tcpu)/2 << FShft (LCCR0_PDD))
+
+#define LCSR_LDD	0x00000001	/* LCD Disable Done		   */
+#define LCSR_BAU	0x00000002	/* Base Address Update (read)	   */
+#define LCSR_BER	0x00000004	/* Bus ERror			   */
+#define LCSR_ABC	0x00000008	/* AC Bias clock Count		   */
+#define LCSR_IOL	0x00000010	/* Input FIFO Over-run Lower	   */
+					/* panel			   */
+#define LCSR_IUL	0x00000020	/* Input FIFO Under-run Lower	   */
+					/* panel			   */
+#define LCSR_IOU	0x00000040	/* Input FIFO Over-run Upper	   */
+					/* panel			   */
+#define LCSR_IUU	0x00000080	/* Input FIFO Under-run Upper	   */
+					/* panel			   */
+#define LCSR_OOL	0x00000100	/* Output FIFO Over-run Lower	   */
+					/* panel			   */
+#define LCSR_OUL	0x00000200	/* Output FIFO Under-run Lower	   */
+					/* panel			   */
+#define LCSR_OOU	0x00000400	/* Output FIFO Over-run Upper	   */
+					/* panel			   */
+#define LCSR_OUU	0x00000800	/* Output FIFO Under-run Upper	   */
+					/* panel			   */
+
+#define LCCR1_PPL	Fld (6, 4)	/* Pixels Per Line/16 - 1	   */
+#define LCCR1_DisWdth(Pixel)		/*  Display Width [16..1024 pix.]  */ \
+			(((Pixel) - 16)/16 << FShft (LCCR1_PPL))
+#define LCCR1_HSW	Fld (6, 10)	/* Horizontal Synchronization	   */
+					/* pulse Width - 2 [Tpix] (L_LCLK) */
+#define LCCR1_HorSnchWdth(Tpix)		/*  Horizontal Synchronization	   */ \
+					/*  pulse Width [2..65 Tpix]	   */ \
+			(((Tpix) - 2) << FShft (LCCR1_HSW))
+#define LCCR1_ELW	Fld (8, 16)	/* End-of-Line pixel clock Wait    */
+					/* count - 1 [Tpix]		   */
+#define LCCR1_EndLnDel(Tpix)		/*  End-of-Line Delay		   */ \
+					/*  [1..256 Tpix]		   */ \
+			(((Tpix) - 1) << FShft (LCCR1_ELW))
+#define LCCR1_BLW	Fld (8, 24)	/* Beginning-of-Line pixel clock   */
+					/* Wait count - 1 [Tpix]	   */
+#define LCCR1_BegLnDel(Tpix)		/*  Beginning-of-Line Delay	   */ \
+					/*  [1..256 Tpix]		   */ \
+			(((Tpix) - 1) << FShft (LCCR1_BLW))
+
+#define LCCR2_LPP	Fld (10, 0)	/* Line Per Panel - 1		   */
+#define LCCR2_DisHght(Line)		/*  Display Height [1..1024 lines] */ \
+			(((Line) - 1) << FShft (LCCR2_LPP))
+#define LCCR2_VSW	Fld (6, 10)	/* Vertical Synchronization pulse  */
+					/* Width - 1 [Tln] (L_FCLK)	   */
+#define LCCR2_VrtSnchWdth(Tln)		/*  Vertical Synchronization pulse */ \
+					/*  Width [1..64 Tln]		   */ \
+			(((Tln) - 1) << FShft (LCCR2_VSW))
+#define LCCR2_EFW	Fld (8, 16)	/* End-of-Frame line clock Wait    */
+					/* count [Tln]			   */
+#define LCCR2_EndFrmDel(Tln)		/*  End-of-Frame Delay		   */ \
+					/*  [0..255 Tln]		   */ \
+			((Tln) << FShft (LCCR2_EFW))
+#define LCCR2_BFW	Fld (8, 24)	/* Beginning-of-Frame line clock   */
+					/* Wait count [Tln]		   */
+#define LCCR2_BegFrmDel(Tln)		/*  Beginning-of-Frame Delay	   */ \
+					/*  [0..255 Tln]		   */ \
+			((Tln) << FShft (LCCR2_BFW))
+
+#define LCCR3_PCD	Fld (8, 0)	/* Pixel Clock Divisor/2 - 2	   */
+					/* [1..255] (L_PCLK)		   */
+					/* fpix = fcpu/(2*(PCD + 2))	   */
+					/* Tpix = 2*(PCD + 2)*Tcpu	   */
+#define LCCR3_PixClkDiv(Div)		/*  Pixel Clock Divisor [6..514]   */ \
+			(((Div) - 4)/2 << FShft (LCCR3_PCD))
+					/*  fpix = fcpu/(2*Floor (Div/2))  */
+					/*  Tpix = 2*Floor (Div/2)*Tcpu    */
+#define LCCR3_CeilPixClkDiv(Div)	/*  Ceil. of PixClkDiv [6..514]    */ \
+			(((Div) - 3)/2 << FShft (LCCR3_PCD))
+					/*  fpix = fcpu/(2*Ceil (Div/2))   */
+					/*  Tpix = 2*Ceil (Div/2)*Tcpu	   */
+#define LCCR3_ACB	Fld (8, 8)	/* AC Bias clock half period - 1   */
+					/* [Tln] (L_BIAS)		   */
+#define LCCR3_ACBsDiv(Div)		/*  AC Bias clock Divisor [2..512] */ \
+			(((Div) - 2)/2 << FShft (LCCR3_ACB))
+					/*  fac = fln/(2*Floor (Div/2))    */
+					/*  Tac = 2*Floor (Div/2)*Tln	   */
+#define LCCR3_CeilACBsDiv(Div)		/*  Ceil. of ACBsDiv [2..512]	   */ \
+			(((Div) - 1)/2 << FShft (LCCR3_ACB))
+					/*  fac = fln/(2*Ceil (Div/2))	   */
+					/*  Tac = 2*Ceil (Div/2)*Tln	   */
+#define LCCR3_API	Fld (4, 16)	/* AC bias Pin transitions per	   */
+					/* Interrupt			   */
+#define LCCR3_ACBsCntOff		/*  AC Bias clock transition Count */ \
+					/*  Off				   */ \
+			(0 << FShft (LCCR3_API))
+#define LCCR3_ACBsCnt(Trans)		/*  AC Bias clock transition Count */ \
+					/*  [1..15]			   */ \
+			((Trans) << FShft (LCCR3_API))
+#define LCCR3_VSP	0x00100000	/* Vertical Synchronization pulse  */
+					/* Polarity (L_FCLK)		   */
+#define LCCR3_VrtSnchH	(LCCR3_VSP*0)	/*  Vertical Synchronization pulse */
+					/*  active High			   */
+#define LCCR3_VrtSnchL	(LCCR3_VSP*1)	/*  Vertical Synchronization pulse */
+					/*  active Low			   */
+#define LCCR3_HSP	0x00200000	/* Horizontal Synchronization	   */
+					/* pulse Polarity (L_LCLK)	   */
+#define LCCR3_HorSnchH	(LCCR3_HSP*0)	/*  Horizontal Synchronization	   */
+					/*  pulse active High		   */
+#define LCCR3_HorSnchL	(LCCR3_HSP*1)	/*  Horizontal Synchronization	   */
+					/*  pulse active Low		   */
+#define LCCR3_PCP	0x00400000	/* Pixel Clock Polarity (L_PCLK)   */
+#define LCCR3_PixRsEdg	(LCCR3_PCP*0)	/*  Pixel clock Rising-Edge	   */
+#define LCCR3_PixFlEdg	(LCCR3_PCP*1)	/*  Pixel clock Falling-Edge	   */
+#define LCCR3_OEP	0x00800000	/* Output Enable Polarity (L_BIAS, */
+					/* active display mode)		   */
+#define LCCR3_OutEnH	(LCCR3_OEP*0)	/*  Output Enable active High	   */
+#define LCCR3_OutEnL	(LCCR3_OEP*1)	/*  Output Enable active Low	   */
+
+
+#undef C
+#undef Assembly
diff --git a/qemu/roms/u-boot/include/_exports.h b/qemu/roms/u-boot/include/_exports.h
new file mode 100644
index 000000000..349a3c552
--- /dev/null
+++ b/qemu/roms/u-boot/include/_exports.h
@@ -0,0 +1,32 @@
+/*
+ * You do not need to use #ifdef around functions that may not exist
+ * in the final configuration (such as i2c).
+ */
+EXPORT_FUNC(get_version)
+EXPORT_FUNC(getc)
+EXPORT_FUNC(tstc)
+EXPORT_FUNC(putc)
+EXPORT_FUNC(puts)
+EXPORT_FUNC(printf)
+EXPORT_FUNC(install_hdlr)
+EXPORT_FUNC(free_hdlr)
+EXPORT_FUNC(malloc)
+EXPORT_FUNC(free)
+EXPORT_FUNC(udelay)
+EXPORT_FUNC(get_timer)
+EXPORT_FUNC(vprintf)
+EXPORT_FUNC(do_reset)
+EXPORT_FUNC(getenv)
+EXPORT_FUNC(setenv)
+EXPORT_FUNC(simple_strtoul)
+EXPORT_FUNC(strict_strtoul)
+EXPORT_FUNC(simple_strtol)
+EXPORT_FUNC(strcmp)
+EXPORT_FUNC(i2c_write)
+EXPORT_FUNC(i2c_read)
+EXPORT_FUNC(spi_init)
+EXPORT_FUNC(spi_setup_slave)
+EXPORT_FUNC(spi_free_slave)
+EXPORT_FUNC(spi_claim_bus)
+EXPORT_FUNC(spi_release_bus)
+EXPORT_FUNC(spi_xfer)
diff --git a/qemu/roms/u-boot/include/addr_map.h b/qemu/roms/u-boot/include/addr_map.h
new file mode 100644
index 000000000..dda4d6e71
--- /dev/null
+++ b/qemu/roms/u-boot/include/addr_map.h
@@ -0,0 +1,29 @@
+#ifndef __ADDR_MAP_H
+#define __ADDR_MAP_H
+
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/types.h>
+
+extern phys_addr_t addrmap_virt_to_phys(void *vaddr);
+extern void *addrmap_phys_to_virt(phys_addr_t paddr);
+extern void addrmap_set_entry(unsigned long vaddr, phys_addr_t paddr,
+				phys_size_t size, int idx);
+
+#endif
diff --git a/qemu/roms/u-boot/include/aes.h b/qemu/roms/u-boot/include/aes.h
new file mode 100644
index 000000000..6315c02aa
--- /dev/null
+++ b/qemu/roms/u-boot/include/aes.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2010 - 2011 NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _AES_REF_H_
+#define _AES_REF_H_
+
+#ifdef USE_HOSTCC
+/* Define compat stuff for use in fw_* tools. */
+typedef unsigned char u8;
+typedef unsigned int u32;
+#define debug(...) do {} while (0)
+#endif
+
+/*
+ * AES encryption library, with small code size, supporting only 128-bit AES
+ *
+ * AES is a stream cipher which works a block at a time, with each block
+ * in this case being AES_KEY_LENGTH bytes.
+ */
+
+enum {
+	AES_STATECOLS	= 4,	/* columns in the state & expanded key */
+	AES_KEYCOLS	= 4,	/* columns in a key */
+	AES_ROUNDS	= 10,	/* rounds in encryption */
+
+	AES_KEY_LENGTH	= 128 / 8,
+	AES_EXPAND_KEY_LENGTH	= 4 * AES_STATECOLS * (AES_ROUNDS + 1),
+};
+
+/**
+ * aes_expand_key() - Expand the AES key
+ *
+ * Expand a key into a key schedule, which is then used for the other
+ * operations.
+ *
+ * @key		Key, of length AES_KEY_LENGTH bytes
+ * @expkey	Buffer to place expanded key, AES_EXPAND_KEY_LENGTH
+ */
+void aes_expand_key(u8 *key, u8 *expkey);
+
+/**
+ * aes_encrypt() - Encrypt single block of data with AES 128
+ *
+ * @in		Input data
+ * @expkey	Expanded key to use for encryption (from aes_expand_key())
+ * @out		Output data
+ */
+void aes_encrypt(u8 *in, u8 *expkey, u8 *out);
+
+/**
+ * aes_decrypt() - Decrypt single block of data with AES 128
+ *
+ * @in		Input data
+ * @expkey	Expanded key to use for decryption (from aes_expand_key())
+ * @out		Output data
+ */
+void aes_decrypt(u8 *in, u8 *expkey, u8 *out);
+
+/**
+ * Apply chain data to the destination using EOR
+ *
+ * Each array is of length AES_KEY_LENGTH.
+ *
+ * @cbc_chain_data	Chain data
+ * @src			Source data
+ * @dst			Destination data, which is modified here
+ */
+void aes_apply_cbc_chain_data(u8 *cbc_chain_data, u8 *src, u8 *dst);
+
+/**
+ * aes_cbc_encrypt_blocks() - Encrypt multiple blocks of data with AES CBC.
+ *
+ * @key_exp		Expanded key to use
+ * @src			Source data to encrypt
+ * @dst			Destination buffer
+ * @num_aes_blocks	Number of AES blocks to encrypt
+ */
+void aes_cbc_encrypt_blocks(u8 *key_exp, u8 *src, u8 *dst, u32 num_aes_blocks);
+
+/**
+ * Decrypt multiple blocks of data with AES CBC.
+ *
+ * @key_exp		Expanded key to use
+ * @src			Source data to decrypt
+ * @dst			Destination buffer
+ * @num_aes_blocks	Number of AES blocks to decrypt
+ */
+void aes_cbc_decrypt_blocks(u8 *key_exp, u8 *src, u8 *dst, u32 num_aes_blocks);
+
+#endif /* _AES_REF_H_ */
diff --git a/qemu/roms/u-boot/include/ahci.h b/qemu/roms/u-boot/include/ahci.h
new file mode 100644
index 000000000..90e850929
--- /dev/null
+++ b/qemu/roms/u-boot/include/ahci.h
@@ -0,0 +1,161 @@
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006.
+ * Author: Jason Jin<Jason.jin@freescale.com>
+ *         Zhang Wei<wei.zhang@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _AHCI_H_
+#define _AHCI_H_
+
+#include <pci.h>
+
+#define AHCI_PCI_BAR		0x24
+#define AHCI_MAX_SG		56 /* hardware max is 64K */
+#define AHCI_CMD_SLOT_SZ	32
+#define AHCI_MAX_CMD_SLOT	32
+#define AHCI_RX_FIS_SZ		256
+#define AHCI_CMD_TBL_HDR	0x80
+#define AHCI_CMD_TBL_CDB	0x40
+#define AHCI_CMD_TBL_SZ		AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16)
+#define AHCI_PORT_PRIV_DMA_SZ	(AHCI_CMD_SLOT_SZ * AHCI_MAX_CMD_SLOT + \
+				AHCI_CMD_TBL_SZ	+ AHCI_RX_FIS_SZ)
+#define AHCI_CMD_ATAPI		(1 << 5)
+#define AHCI_CMD_WRITE		(1 << 6)
+#define AHCI_CMD_PREFETCH	(1 << 7)
+#define AHCI_CMD_RESET		(1 << 8)
+#define AHCI_CMD_CLR_BUSY	(1 << 10)
+
+#define RX_FIS_D2H_REG		0x40	/* offset of D2H Register FIS data */
+
+/* Global controller registers */
+#define HOST_CAP		0x00 /* host capabilities */
+#define HOST_CTL		0x04 /* global host control */
+#define HOST_IRQ_STAT		0x08 /* interrupt status */
+#define HOST_PORTS_IMPL		0x0c /* bitmap of implemented ports */
+#define HOST_VERSION		0x10 /* AHCI spec. version compliancy */
+#define HOST_CAP2		0x24 /* host capabilities, extended */
+
+/* HOST_CTL bits */
+#define HOST_RESET		(1 << 0)  /* reset controller; self-clear */
+#define HOST_IRQ_EN		(1 << 1)  /* global IRQ enable */
+#define HOST_AHCI_EN		(1 << 31) /* AHCI enabled */
+
+/* Registers for each SATA port */
+#define PORT_LST_ADDR		0x00 /* command list DMA addr */
+#define PORT_LST_ADDR_HI	0x04 /* command list DMA addr hi */
+#define PORT_FIS_ADDR		0x08 /* FIS rx buf addr */
+#define PORT_FIS_ADDR_HI	0x0c /* FIS rx buf addr hi */
+#define PORT_IRQ_STAT		0x10 /* interrupt status */
+#define PORT_IRQ_MASK		0x14 /* interrupt enable/disable mask */
+#define PORT_CMD		0x18 /* port command */
+#define PORT_TFDATA		0x20 /* taskfile data */
+#define PORT_SIG		0x24 /* device TF signature */
+#define PORT_CMD_ISSUE		0x38 /* command issue */
+#define PORT_SCR		0x28 /* SATA phy register block */
+#define PORT_SCR_STAT		0x28 /* SATA phy register: SStatus */
+#define PORT_SCR_CTL		0x2c /* SATA phy register: SControl */
+#define PORT_SCR_ERR		0x30 /* SATA phy register: SError */
+#define PORT_SCR_ACT		0x34 /* SATA phy register: SActive */
+
+/* PORT_IRQ_{STAT,MASK} bits */
+#define PORT_IRQ_COLD_PRES	(1 << 31) /* cold presence detect */
+#define PORT_IRQ_TF_ERR		(1 << 30) /* task file error */
+#define PORT_IRQ_HBUS_ERR	(1 << 29) /* host bus fatal error */
+#define PORT_IRQ_HBUS_DATA_ERR	(1 << 28) /* host bus data error */
+#define PORT_IRQ_IF_ERR		(1 << 27) /* interface fatal error */
+#define PORT_IRQ_IF_NONFATAL	(1 << 26) /* interface non-fatal error */
+#define PORT_IRQ_OVERFLOW	(1 << 24) /* xfer exhausted available S/G */
+#define PORT_IRQ_BAD_PMP	(1 << 23) /* incorrect port multiplier */
+
+#define PORT_IRQ_PHYRDY		(1 << 22) /* PhyRdy changed */
+#define PORT_IRQ_DEV_ILCK	(1 << 7) /* device interlock */
+#define PORT_IRQ_CONNECT	(1 << 6) /* port connect change status */
+#define PORT_IRQ_SG_DONE	(1 << 5) /* descriptor processed */
+#define PORT_IRQ_UNK_FIS	(1 << 4) /* unknown FIS rx'd */
+#define PORT_IRQ_SDB_FIS	(1 << 3) /* Set Device Bits FIS rx'd */
+#define PORT_IRQ_DMAS_FIS	(1 << 2) /* DMA Setup FIS rx'd */
+#define PORT_IRQ_PIOS_FIS	(1 << 1) /* PIO Setup FIS rx'd */
+#define PORT_IRQ_D2H_REG_FIS	(1 << 0) /* D2H Register FIS rx'd */
+
+#define PORT_IRQ_FATAL		PORT_IRQ_TF_ERR | PORT_IRQ_HBUS_ERR	\
+				| PORT_IRQ_HBUS_DATA_ERR | PORT_IRQ_IF_ERR
+
+#define DEF_PORT_IRQ		PORT_IRQ_FATAL | PORT_IRQ_PHYRDY	\
+				| PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE	\
+				| PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS	\
+				| PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS	\
+				| PORT_IRQ_D2H_REG_FIS
+
+/* PORT_SCR_STAT bits */
+#define PORT_SCR_STAT_DET_MASK	0x3
+#define PORT_SCR_STAT_DET_COMINIT 0x1
+#define PORT_SCR_STAT_DET_PHYRDY 0x3
+
+/* PORT_CMD bits */
+#define PORT_CMD_ATAPI		(1 << 24) /* Device is ATAPI */
+#define PORT_CMD_LIST_ON	(1 << 15) /* cmd list DMA engine running */
+#define PORT_CMD_FIS_ON		(1 << 14) /* FIS DMA engine running */
+#define PORT_CMD_FIS_RX		(1 << 4) /* Enable FIS receive DMA engine */
+#define PORT_CMD_CLO		(1 << 3) /* Command list override */
+#define PORT_CMD_POWER_ON	(1 << 2) /* Power up device */
+#define PORT_CMD_SPIN_UP	(1 << 1) /* Spin up device */
+#define PORT_CMD_START		(1 << 0) /* Enable port DMA engine */
+
+#define PORT_CMD_ICC_ACTIVE	(0x1 << 28) /* Put i/f in active state */
+#define PORT_CMD_ICC_PARTIAL	(0x2 << 28) /* Put i/f in partial state */
+#define PORT_CMD_ICC_SLUMBER	(0x6 << 28) /* Put i/f in slumber state */
+
+#define AHCI_MAX_PORTS		32
+
+#define ATA_FLAG_SATA		(1 << 3)
+#define ATA_FLAG_NO_LEGACY	(1 << 4) /* no legacy mode check */
+#define ATA_FLAG_MMIO		(1 << 6) /* use MMIO, not PIO */
+#define ATA_FLAG_SATA_RESET	(1 << 7) /* (obsolete) use COMRESET */
+#define ATA_FLAG_PIO_DMA	(1 << 8) /* PIO cmds via DMA */
+#define ATA_FLAG_NO_ATAPI	(1 << 11) /* No ATAPI support */
+
+struct ahci_cmd_hdr {
+	u32	opts;
+	u32	status;
+	u32	tbl_addr;
+	u32	tbl_addr_hi;
+	u32	reserved[4];
+};
+
+struct ahci_sg {
+	u32	addr;
+	u32	addr_hi;
+	u32	reserved;
+	u32	flags_size;
+};
+
+struct ahci_ioports {
+	u32	cmd_addr;
+	u32	scr_addr;
+	u32	port_mmio;
+	struct ahci_cmd_hdr	*cmd_slot;
+	struct ahci_sg		*cmd_tbl_sg;
+	u32	cmd_tbl;
+	u32	rx_fis;
+};
+
+struct ahci_probe_ent {
+	pci_dev_t	dev;
+	struct ahci_ioports	port[AHCI_MAX_PORTS];
+	u32	n_ports;
+	u32	hard_port_no;
+	u32	host_flags;
+	u32	host_set_flags;
+	u32	mmio_base;
+	u32     pio_mask;
+	u32	udma_mask;
+	u32	flags;
+	u32	cap;	/* cache of HOST_CAP register */
+	u32	port_map; /* cache of HOST_PORTS_IMPL reg */
+	u32	link_port_map; /*linkup port map*/
+};
+
+int ahci_init(u32 base);
+
+#endif
diff --git a/qemu/roms/u-boot/include/ali512x.h b/qemu/roms/u-boot/include/ali512x.h
new file mode 100644
index 000000000..47c75bdd0
--- /dev/null
+++ b/qemu/roms/u-boot/include/ali512x.h
@@ -0,0 +1,38 @@
+/*
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_IC_ALI512X_H_
+#define __ASM_IC_ALI512X_H_
+
+# define ALI_INDEX    0x3f0
+# define ALI_DATA     0x3f1
+
+# define ALI_ENABLED  1
+# define ALI_DISABLED 0
+
+# define ALI_UART1    0
+# define ALI_UART2    1
+
+/* setup functions */
+void ali512x_init(void);
+void ali512x_set_fdc(int enabled, u16 io, u8 irq, u8 dma_channel);
+void ali512x_set_pp(int enabled, u16 io, u8 irq, u8 dma_channel);
+void ali512x_set_uart(int enabled, int index, u16 io, u8 irq);
+void ali512x_set_rtc(int enabled, u16 io, u8 irq);
+void ali512x_set_kbc(int enabled, u8 kbc_irq, u8 mouse_irq);
+void ali512x_set_cio(int enabled);
+
+
+/* common I/O functions */
+void ali512x_cio_function(int pin, int special, int inv, int input);
+void ali512x_cio_out(int pin, int value);
+int ali512x_cio_in(int pin);
+
+/* misc features */
+void ali512x_set_uart2_irda(int enabled);
+
+#endif
diff --git a/qemu/roms/u-boot/include/altera.h b/qemu/roms/u-boot/include/altera.h
new file mode 100644
index 000000000..0327a1b82
--- /dev/null
+++ b/qemu/roms/u-boot/include/altera.h
@@ -0,0 +1,72 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <fpga.h>
+
+#ifndef _ALTERA_H_
+#define _ALTERA_H_
+
+typedef enum {				/* typedef Altera_iface */
+	min_altera_iface_type,		/* insert all new types after this */
+	passive_serial,			/* serial data and external clock */
+	passive_parallel_synchronous,	/* parallel data */
+	passive_parallel_asynchronous,	/* parallel data */
+	passive_serial_asynchronous,	/* serial data w/ internal clock (not used)	*/
+	altera_jtag_mode,		/* jtag/tap serial (not used ) */
+	fast_passive_parallel,		/* fast passive parallel (FPP) */
+	fast_passive_parallel_security,	/* fast passive parallel with security (FPPS) */
+	max_altera_iface_type		/* insert all new types before this */
+} Altera_iface;				/* end, typedef Altera_iface */
+
+typedef enum {			/* typedef Altera_Family */
+	min_altera_type,	/* insert all new types after this */
+	Altera_ACEX1K,		/* ACEX1K Family */
+	Altera_CYC2,		/* CYCLONII Family */
+	Altera_StratixII,	/* StratixII Familiy */
+/* Add new models here */
+	max_altera_type		/* insert all new types before this */
+} Altera_Family;		/* end, typedef Altera_Family */
+
+typedef struct {		/* typedef Altera_desc */
+	Altera_Family	family;	/* part type */
+	Altera_iface	iface;	/* interface type */
+	size_t		size;	/* bytes of data part can accept */
+	void *		iface_fns;/* interface function table */
+	void *		base;	/* base interface address */
+	int		cookie;	/* implementation specific cookie */
+} Altera_desc;			/* end, typedef Altera_desc */
+
+/* Generic Altera Functions
+ *********************************************************************/
+extern int altera_load(Altera_desc *desc, const void *image, size_t size);
+extern int altera_dump(Altera_desc *desc, const void *buf, size_t bsize);
+extern int altera_info(Altera_desc *desc);
+
+/* Board specific implementation specific function types
+ *********************************************************************/
+typedef int (*Altera_pre_fn)( int cookie );
+typedef int (*Altera_config_fn)( int assert_config, int flush, int cookie );
+typedef int (*Altera_status_fn)( int cookie );
+typedef int (*Altera_done_fn)( int cookie );
+typedef int (*Altera_clk_fn)( int assert_clk, int flush, int cookie );
+typedef int (*Altera_data_fn)( int assert_data, int flush, int cookie );
+typedef int(*Altera_write_fn)(const void *buf, size_t len, int flush, int cookie);
+typedef int (*Altera_abort_fn)( int cookie );
+typedef int (*Altera_post_fn)( int cookie );
+
+typedef struct {
+	Altera_pre_fn pre;
+	Altera_config_fn config;
+	Altera_status_fn status;
+	Altera_done_fn done;
+	Altera_clk_fn clk;
+	Altera_data_fn data;
+	Altera_abort_fn abort;
+	Altera_post_fn post;
+} altera_board_specific_func;
+
+#endif /* _ALTERA_H_ */
diff --git a/qemu/roms/u-boot/include/ambapp.h b/qemu/roms/u-boot/include/ambapp.h
new file mode 100644
index 000000000..405637d8c
--- /dev/null
+++ b/qemu/roms/u-boot/include/ambapp.h
@@ -0,0 +1,377 @@
+/* Interface for accessing Gaisler AMBA Plug&Play Bus.
+ * The AHB bus can be interfaced with a simpler bus -
+ * the APB bus, also freely available in GRLIB at
+ * www.gaisler.com.
+ *
+ * (C) Copyright 2007
+ * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __AMBAPP_H__
+#define __AMBAPP_H__
+
+/* Default location of Plug&Play info
+ * normally 0xfffff000 for AHB masters
+ * and 0xfffff800 for AHB slaves.
+ * Normally no need to change this.
+ */
+#define LEON3_IO_AREA 0xfff00000
+#define LEON3_CONF_AREA  0xff000
+#define LEON3_AHB_SLAVE_CONF_AREA (1 << 11)
+
+/* Max devices this software will support */
+#define LEON3_AHB_MASTERS 16
+#define LEON3_AHB_SLAVES 16
+/*#define LEON3_APB_MASTERS 1*/ /* Number of APB buses that has Plug&Play */
+#define LEON3_APB_SLAVES 16	/* Total number of APB slaves per APB bus */
+
+/* Vendor codes */
+#define VENDOR_GAISLER       1
+#define VENDOR_PENDER        2
+#define VENDOR_ESA           4
+#define VENDOR_ASTRIUM       6
+#define VENDOR_OPENCHIP      7
+#define VENDOR_OPENCORES     8
+#define VENDOR_CONTRIB       9
+#define VENDOR_EONIC         11
+#define VENDOR_RADIONOR      15
+#define VENDOR_GLEICHMANN    16
+#define VENDOR_MENTA         17
+#define VENDOR_SUN           19
+#define VENDOR_EMBEDDIT      234
+#define VENDOR_CAL           202
+
+/* Gaisler Research device id's */
+#define GAISLER_LEON3    0x003
+#define GAISLER_LEON3DSU 0x004
+#define GAISLER_ETHAHB   0x005
+#define GAISLER_APBMST   0x006
+#define GAISLER_AHBUART  0x007
+#define GAISLER_SRCTRL   0x008
+#define GAISLER_SDCTRL   0x009
+#define GAISLER_APBUART  0x00C
+#define GAISLER_IRQMP    0x00D
+#define GAISLER_AHBRAM   0x00E
+#define GAISLER_GPTIMER  0x011
+#define GAISLER_PCITRG   0x012
+#define GAISLER_PCISBRG  0x013
+#define GAISLER_PCIFBRG  0x014
+#define GAISLER_PCITRACE 0x015
+#define GAISLER_PCIDMA   0x016
+#define GAISLER_AHBTRACE 0x017
+#define GAISLER_ETHDSU   0x018
+#define GAISLER_PIOPORT  0x01A
+#define GAISLER_AHBJTAG  0x01c
+#define GAISLER_SPW      0x01f
+#define GAISLER_ATACTRL  0x024
+#define GAISLER_VGA      0x061
+#define GAISLER_KBD      0X060
+#define GAISLER_ETHMAC   0x01D
+#define GAISLER_DDRSPA   0x025
+#define GAISLER_EHCI     0x026
+#define GAISLER_UHCI     0x027
+#define GAISLER_SPW2     0x029
+#define GAISLER_DDR2SPA  0x02E
+#define GAISLER_AHBSTAT  0x052
+#define GAISLER_FTMCTRL  0x054
+
+#define GAISLER_L2TIME   0xffd	/* internal device: leon2 timer */
+#define GAISLER_L2C      0xffe	/* internal device: leon2compat */
+#define GAISLER_PLUGPLAY 0xfff	/* internal device: plug & play configarea */
+
+/* European Space Agency device id's */
+#define ESA_LEON2        0x2
+#define ESA_MCTRL        0xF
+
+/* Opencores device id's */
+#define OPENCORES_PCIBR  0x4
+#define OPENCORES_ETHMAC 0x5
+
+/* Vendor codes */
+
+/*
+ *
+ * Macros for manipulating Configuration registers
+ *
+ */
+
+#define amba_vendor(x) (((x) >> 24) & 0xff)
+
+#define amba_device(x) (((x) >> 12) & 0xfff)
+
+#define amba_membar_start(mbar) \
+ (((mbar) & 0xfff00000) & (((mbar) & 0xfff0) << 16))
+
+#define amba_iobar_start(base, iobar) \
+ ((base) | ((((iobar) & 0xfff00000)>>12) & (((iobar) & 0xfff0)<<4)) )
+
+#define amba_irq(conf) ((conf) & 0xf)
+
+#define amba_ver(conf) (((conf)>>5) & 0x1f)
+
+#define amba_membar_type(mbar) ((mbar) & 0xf)
+
+#define amba_membar_mask(mbar) (((mbar)>>4) & 0xfff)
+
+#define AMBA_TYPE_APBIO 0x1
+#define AMBA_TYPE_MEM   0x2
+#define AMBA_TYPE_AHBIO 0x3
+
+#define AMBA_TYPE_AHBIO_ADDR(addr) (LEON3_IO_AREA | ((addr) >> 12))
+
+#ifndef __ASSEMBLER__
+
+#ifdef CONFIG_CMD_AMBAPP
+
+/* AMBA Plug&Play relocation & initialization */
+int ambapp_init_reloc(void);
+
+/* AMBA Plug&Play Name of Vendors and devices */
+
+/* Return name of device */
+char *ambapp_device_id2str(int vendor, int id);
+
+/* Return name of vendor */
+char *ambapp_vendor_id2str(int vendor);
+#endif
+
+/*
+ *  Types and structure used for AMBA Plug & Play bus scanning
+ */
+
+/* AMBA Plug&Play AHB information layout */
+typedef struct {
+	unsigned int conf;
+	unsigned int userdef[3];
+	unsigned int bars[4];
+} ahbctrl_pp_dev;
+
+/* Prototypes for scanning AMBA Plug&Play bus for AMBA
+ *  i)   AHB Masters
+ *  ii)  AHB Slaves
+ *  iii) APB Slaves (APB MST is a AHB Slave)
+ */
+
+typedef struct {
+	unsigned char irq;
+	unsigned char ver;
+	unsigned int address;
+} ambapp_apbdev;
+
+typedef struct {
+	unsigned char irq;
+	unsigned char ver;
+	unsigned int userdef[3];
+	unsigned int address[4];
+} ambapp_ahbdev;
+
+/* AMBA Plug&Play AHB Masters & Slaves information locations
+ * Max devices is 64 supported by HW, however often only 8
+ * are used.
+ */
+typedef struct {
+	ahbctrl_pp_dev masters[64];
+	ahbctrl_pp_dev slaves[64];
+} ahbctrl_info;
+
+/* AMBA Plug&Play AHB information layout */
+typedef struct {
+	unsigned int conf;
+	unsigned int bar;
+} apbctrl_pp_dev;
+
+/* All functions return the number of found devices
+ * 0 = no devices found
+ */
+
+/****************************** APB SLAVES ******************************/
+int ambapp_apb_count(unsigned int vendor, unsigned int driver);
+
+int ambapp_apb_first(unsigned int vendor,
+		     unsigned int driver, ambapp_apbdev * dev);
+
+int ambapp_apb_next(unsigned int vendor,
+		    unsigned int driver, ambapp_apbdev * dev, int index);
+
+int ambapp_apbs_first(unsigned int vendor,
+		      unsigned int driver, ambapp_apbdev * dev, int max_cnt);
+
+/****************************** AHB MASTERS ******************************/
+int ambapp_ahbmst_count(unsigned int vendor, unsigned int driver);
+
+int ambapp_ahbmst_first(unsigned int vendor,
+			unsigned int driver, ambapp_ahbdev * dev);
+
+int ambapp_ahbmst_next(unsigned int vendor,
+		       unsigned int driver, ambapp_ahbdev * dev, int index);
+
+int ambapp_ahbmsts_first(unsigned int vendor,
+			 unsigned int driver, ambapp_ahbdev * dev, int max_cnt);
+
+/****************************** AHB SLAVES ******************************/
+int ambapp_ahbslv_count(unsigned int vendor, unsigned int driver);
+
+int ambapp_ahbslv_first(unsigned int vendor,
+			unsigned int driver, ambapp_ahbdev * dev);
+
+int ambapp_ahbslv_next(unsigned int vendor,
+		       unsigned int driver, ambapp_ahbdev * dev, int index);
+
+int ambapp_ahbslvs_first(unsigned int vendor,
+			 unsigned int driver, ambapp_ahbdev * dev, int max_cnt);
+
+/*************************** AHB/APB only regs functions *************************
+ * During start up, no memory is available we can use the simplified functions
+ * to get to the memory controller.
+ *
+ * Functions uses no stack/memory, only registers.
+ */
+unsigned int ambapp_apb_next_nomem(register unsigned int vendor,	/* Plug&Play Vendor ID */
+				   register unsigned int driver,	/* Plug&Play Device ID */
+				   register int index);
+
+ahbctrl_pp_dev *ambapp_ahb_next_nomem(register unsigned int vendor,	/* Plug&Play Vendor ID */
+				      register unsigned int driver,	/* Plug&Play Device ID */
+				      register unsigned int opts,	/* scan for AHB 1=slave, 0=masters */
+				      register int index);
+
+unsigned int ambapp_ahb_get_info(ahbctrl_pp_dev * ahb, int info);
+
+/*************************** AMBA Plug&Play device register MAPS *****************/
+
+/*
+ *  The following defines the bits in the LEON UART Status Registers.
+ */
+
+#define LEON_REG_UART_STATUS_DR   0x00000001	/* Data Ready */
+#define LEON_REG_UART_STATUS_TSE  0x00000002	/* TX Send Register Empty */
+#define LEON_REG_UART_STATUS_THE  0x00000004	/* TX Hold Register Empty */
+#define LEON_REG_UART_STATUS_BR   0x00000008	/* Break Error */
+#define LEON_REG_UART_STATUS_OE   0x00000010	/* RX Overrun Error */
+#define LEON_REG_UART_STATUS_PE   0x00000020	/* RX Parity Error */
+#define LEON_REG_UART_STATUS_FE   0x00000040	/* RX Framing Error */
+#define LEON_REG_UART_STATUS_ERR  0x00000078	/* Error Mask */
+
+/*
+ *  The following defines the bits in the LEON UART Ctrl Registers.
+ */
+
+#define LEON_REG_UART_CTRL_RE     0x00000001	/* Receiver enable */
+#define LEON_REG_UART_CTRL_TE     0x00000002	/* Transmitter enable */
+#define LEON_REG_UART_CTRL_RI     0x00000004	/* Receiver interrupt enable */
+#define LEON_REG_UART_CTRL_TI     0x00000008	/* Transmitter interrupt enable */
+#define LEON_REG_UART_CTRL_PS     0x00000010	/* Parity select */
+#define LEON_REG_UART_CTRL_PE     0x00000020	/* Parity enable */
+#define LEON_REG_UART_CTRL_FL     0x00000040	/* Flow control enable */
+#define LEON_REG_UART_CTRL_LB     0x00000080	/* Loop Back enable */
+#define LEON_REG_UART_CTRL_DBG    (1<<11)	/* Debug Bit used by GRMON */
+
+#define LEON3_GPTIMER_EN 1
+#define LEON3_GPTIMER_RL 2
+#define LEON3_GPTIMER_LD 4
+#define LEON3_GPTIMER_IRQEN 8
+
+/*
+ *  The following defines the bits in the LEON PS/2 Status Registers.
+ */
+
+#define LEON_REG_PS2_STATUS_DR   0x00000001	/* Data Ready */
+#define LEON_REG_PS2_STATUS_PE   0x00000002	/* Parity error */
+#define LEON_REG_PS2_STATUS_FE   0x00000004	/* Framing error */
+#define LEON_REG_PS2_STATUS_KI   0x00000008	/* Keyboard inhibit */
+
+/*
+ *  The following defines the bits in the LEON PS/2 Ctrl Registers.
+ */
+
+#define LEON_REG_PS2_CTRL_RE     0x00000001	/* Receiver enable */
+#define LEON_REG_PS2_CTRL_TE     0x00000002	/* Transmitter enable */
+#define LEON_REG_PS2_CTRL_RI     0x00000004	/* Keyboard receive interrupt  */
+#define LEON_REG_PS2_CTRL_TI     0x00000008	/* Keyboard transmit interrupt */
+
+typedef struct {
+	volatile unsigned int ilevel;
+	volatile unsigned int ipend;
+	volatile unsigned int iforce;
+	volatile unsigned int iclear;
+	volatile unsigned int mstatus;
+	volatile unsigned int notused[11];
+	volatile unsigned int cpu_mask[16];
+	volatile unsigned int cpu_force[16];
+} ambapp_dev_irqmp;
+
+typedef struct {
+	volatile unsigned int data;
+	volatile unsigned int status;
+	volatile unsigned int ctrl;
+	volatile unsigned int scaler;
+} ambapp_dev_apbuart;
+
+typedef struct {
+	volatile unsigned int val;
+	volatile unsigned int rld;
+	volatile unsigned int ctrl;
+	volatile unsigned int unused;
+} ambapp_dev_gptimer_element;
+
+#define LEON3_GPTIMER_CTRL_EN	0x1	/* Timer enable */
+#define LEON3_GPTIMER_CTRL_RS	0x2	/* Timer reStart  */
+#define LEON3_GPTIMER_CTRL_LD	0x4	/* Timer reLoad */
+#define LEON3_GPTIMER_CTRL_IE	0x8	/* interrupt enable */
+#define LEON3_GPTIMER_CTRL_IP	0x10	/* interrupt flag/pending */
+#define LEON3_GPTIMER_CTRL_CH	0x20	/* Chain with previous timer */
+
+typedef struct {
+	volatile unsigned int scalar;
+	volatile unsigned int scalar_reload;
+	volatile unsigned int config;
+	volatile unsigned int unused;
+	volatile ambapp_dev_gptimer_element e[8];
+} ambapp_dev_gptimer;
+
+typedef struct {
+	volatile unsigned int iodata;
+	volatile unsigned int ioout;
+	volatile unsigned int iodir;
+	volatile unsigned int irqmask;
+	volatile unsigned int irqpol;
+	volatile unsigned int irqedge;
+} ambapp_dev_ioport;
+
+typedef struct {
+	volatile unsigned int write;
+	volatile unsigned int dummy;
+	volatile unsigned int txcolor;
+	volatile unsigned int bgcolor;
+} ambapp_dev_textvga;
+
+typedef struct {
+	volatile unsigned int data;
+	volatile unsigned int status;
+	volatile unsigned int ctrl;
+} ambapp_dev_apbps2;
+
+typedef struct {
+	unsigned int mcfg1, mcfg2, mcfg3;
+} ambapp_dev_mctrl;
+
+typedef struct {
+	unsigned int sdcfg;
+} ambapp_dev_sdctrl;
+
+typedef struct {
+	unsigned int cfg1;
+	unsigned int cfg2;
+	unsigned int cfg3;
+} ambapp_dev_ddr2spa;
+
+typedef struct {
+	unsigned int ctrl;
+	unsigned int cfg;
+} ambapp_dev_ddrspa;
+
+#endif
+
+#endif
diff --git a/qemu/roms/u-boot/include/andestech/andes_pcu.h b/qemu/roms/u-boot/include/andestech/andes_pcu.h
new file mode 100644
index 000000000..1e6c9bae5
--- /dev/null
+++ b/qemu/roms/u-boot/include/andestech/andes_pcu.h
@@ -0,0 +1,355 @@
+/*
+ * (C) Copyright 2011 Andes Technology Corp
+ * Macpaul Lin <macpaul@andestech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Andes Power Control Unit
+ */
+#ifndef __ANDES_PCU_H
+#define __ANDES_PCU_H
+
+#ifndef __ASSEMBLY__
+
+struct pcs {
+	unsigned int	cr;		/* PCSx Configuration (clock scaling) */
+	unsigned int	parm;		/* PCSx Parameter*/
+	unsigned int	stat1;		/* PCSx Status 1 */
+	unsigned int	stat2;		/* PCSx Stusts 2 */
+	unsigned int	pdd;		/* PCSx PDD */
+};
+
+struct andes_pcu {
+	unsigned int	rev;		/* 0x00 - PCU Revision */
+	unsigned int	spinfo;		/* 0x04 - Scratch Pad Info */
+	unsigned int	rsvd1[2];	/* 0x08-0x0C: Reserved */
+	unsigned int	soc_id;		/* 0x10 - SoC ID */
+	unsigned int	soc_ahb;	/* 0x14 - SoC AHB configuration */
+	unsigned int	soc_apb;	/* 0x18 - SoC APB configuration */
+	unsigned int	rsvd2;		/* 0x1C */
+	unsigned int	dcsrcr0;	/* 0x20 - Driving Capability
+						and Slew Rate Control 0 */
+	unsigned int	dcsrcr1;	/* 0x24 - Driving Capability
+						and Slew Rate Control 1 */
+	unsigned int	dcsrcr2;	/* 0x28 - Driving Capability
+						and Slew Rate Control 2 */
+	unsigned int	rsvd3;		/* 0x2C */
+	unsigned int	mfpsr0;		/* 0x30 - Multi-Func Port Setting 0 */
+	unsigned int	mfpsr1;		/* 0x34 - Multi-Func Port Setting 1 */
+	unsigned int	dmaes;		/* 0x38 - DMA Engine Selection */
+	unsigned int	rsvd4;		/* 0x3C */
+	unsigned int	oscc;		/* 0x40 - OSC Control */
+	unsigned int	pwmcd;		/* 0x44 - PWM Clock divider */
+	unsigned int	socmisc;	/* 0x48 - SoC Misc. */
+	unsigned int	rsvd5[13];	/* 0x4C-0x7C: Reserved */
+	unsigned int	bsmcr;		/* 0x80 - BSM Controrl */
+	unsigned int	bsmst;		/* 0x84 - BSM Status */
+	unsigned int	wes;		/* 0x88 - Wakeup Event Sensitivity*/
+	unsigned int	west;		/* 0x8C - Wakeup Event Status */
+	unsigned int	rsttiming;	/* 0x90 - Reset Timing  */
+	unsigned int	intr_st;	/* 0x94 - PCU Interrupt Status */
+	unsigned int	rsvd6[2];	/* 0x98-0x9C: Reserved */
+	struct pcs	pcs1;		/* 0xA0-0xB0: PCS1 (clock scaling) */
+	unsigned int	pcsrsvd1[3];	/* 0xB4-0xBC: Reserved */
+	struct pcs	pcs2;		/* 0xC0-0xD0: PCS2 (AHB clock gating) */
+	unsigned int	pcsrsvd2[3];	/* 0xD4-0xDC: Reserved */
+	struct pcs	pcs3;		/* 0xE0-0xF0: PCS3 (APB clock gating) */
+	unsigned int	pcsrsvd3[3];	/* 0xF4-0xFC: Reserved */
+	struct pcs	pcs4;		/* 0x100-0x110: PCS4 main PLL scaling */
+	unsigned int	pcsrsvd4[3];	/* 0x114-0x11C: Reserved */
+	struct pcs	pcs5;		/* 0x120-0x130: PCS5 PCI PLL scaling */
+	unsigned int	pcsrsvd5[3];	/* 0x134-0x13C: Reserved */
+	struct pcs	pcs6;		/* 0x140-0x150: PCS6 AC97 PLL scaling */
+	unsigned int	pcsrsvd6[3];	/* 0x154-0x15C: Reserved */
+	struct pcs	pcs7;		/* 0x160-0x170: PCS7 GMAC PLL scaling */
+	unsigned int	pcsrsvd7[3];	/* 0x174-0x17C: Reserved */
+	struct pcs	pcs8;		/* 0x180-0x190: PCS8 voltage scaling */
+	unsigned int	pcsrsvd8[3];	/* 0x194-0x19C: Reserved */
+	struct pcs	pcs9;		/* 0x1A0-0x1B0: PCS9 power control */
+	unsigned int	pcsrsvd9[93];	/* 0x1B4-0x3FC: Reserved */
+	unsigned int	pmspdm[40];	/* 0x400-0x4fC: Power Manager
+							Scratch Pad Memory 0 */
+};
+#endif /* __ASSEMBLY__ */
+
+/*
+ * PCU Revision Register (ro)
+ */
+#define ANDES_PCU_REV_NUMBER_PCS(x)	(((x) >> 0) & 0xff)
+#define ANDES_PCU_REV_VER(x)		(((x) >> 16) & 0xffff)
+
+/*
+ * Scratch Pad Info Register (ro)
+ */
+#define ANDES_PCU_SPINFO_SIZE(x)	(((x) >> 0) & 0xff)
+#define ANDES_PCU_SPINFO_OFFSET(x)	(((x) >> 8) & 0xf)
+
+/*
+ * SoC ID Register (ro)
+ */
+#define ANDES_PCU_SOC_ID_VER_MINOR(x)	(((x) >> 0) & 0xf)
+#define ANDES_PCU_SOC_ID_VER_MAJOR(x)	(((x) >> 4) & 0xfff)
+#define ANDES_PCU_SOC_ID_DEVICEID(x)	(((x) >> 16) & 0xffff)
+
+/*
+ * SoC AHB Configuration Register (ro)
+ */
+#define ANDES_PCU_SOC_AHB_AHBC(x)		((x) << 0)
+#define ANDES_PCU_SOC_AHB_APBREG(x)		((x) << 1)
+#define ANDES_PCU_SOC_AHB_APB(x)		((x) << 2)
+#define ANDES_PCU_SOC_AHB_DLM1(x)		((x) << 3)
+#define ANDES_PCU_SOC_AHB_SPIROM(x)		((x) << 4)
+#define ANDES_PCU_SOC_AHB_DDR2C(x)		((x) << 5)
+#define ANDES_PCU_SOC_AHB_DDR2MEM(x)		((x) << 6)
+#define ANDES_PCU_SOC_AHB_DMAC(x)		((x) << 7)
+#define ANDES_PCU_SOC_AHB_DLM2(x)		((x) << 8)
+#define ANDES_PCU_SOC_AHB_GPU(x)		((x) << 9)
+#define ANDES_PCU_SOC_AHB_GMAC(x)		((x) << 12)
+#define ANDES_PCU_SOC_AHB_IDE(x)		((x) << 13)
+#define ANDES_PCU_SOC_AHB_USBOTG(x)		((x) << 14)
+#define ANDES_PCU_SOC_AHB_INTC(x)		((x) << 15)
+#define ANDES_PCU_SOC_AHB_LPCIO(x)		((x) << 16)
+#define ANDES_PCU_SOC_AHB_LPCREG(x)		((x) << 17)
+#define ANDES_PCU_SOC_AHB_PCIIO(x)		((x) << 18)
+#define ANDES_PCU_SOC_AHB_PCIMEM(x)		((x) << 19)
+#define ANDES_PCU_SOC_AHB_L2CC(x)		((x) << 20)
+#define ANDES_PCU_SOC_AHB_AHB2AHBREG(x)		((x) << 27)
+#define ANDES_PCU_SOC_AHB_AHB2AHBMEM0(x)	((x) << 28)
+#define ANDES_PCU_SOC_AHB_AHB2AHBMEM1(x)	((x) << 29)
+#define ANDES_PCU_SOC_AHB_AHB2AHBMEM2(x)	((x) << 30)
+#define ANDES_PCU_SOC_AHB_AHB2AHBMEM3(x)	((x) << 31)
+
+/*
+ * SoC APB Configuration Register (ro)
+ */
+#define ANDES_PCU_SOC_APB_CFC(x)	((x) << 1)
+#define ANDES_PCU_SOC_APB_SSP(x)	((x) << 2)
+#define ANDES_PCU_SOC_APB_UART1(x)	((x) << 3)
+#define ANDES_PCU_SOC_APB_SDC(x)	((x) << 5)
+#define ANDES_PCU_SOC_APB_AC97I2S(x)	((x) << 6)
+#define ANDES_PCU_SOC_APB_UART2(x)	((x) << 8)
+#define ANDES_PCU_SOC_APB_PCU(x)	((x) << 16)
+#define ANDES_PCU_SOC_APB_TMR(x)	((x) << 17)
+#define ANDES_PCU_SOC_APB_WDT(x)	((x) << 18)
+#define ANDES_PCU_SOC_APB_RTC(x)	((x) << 19)
+#define ANDES_PCU_SOC_APB_GPIO(x)	((x) << 20)
+#define ANDES_PCU_SOC_APB_I2C(x)	((x) << 22)
+#define ANDES_PCU_SOC_APB_PWM(x)	((x) << 23)
+
+/*
+ * Driving Capability and Slew Rate Control Register 0 (rw)
+ */
+#define ANDES_PCU_DCSRCR0_TRIAHB(x)	(((x) & 0x1f) << 0)
+#define ANDES_PCU_DCSRCR0_LPC(x)	(((x) & 0xf) << 8)
+#define ANDES_PCU_DCSRCR0_ULPI(x)	(((x) & 0xf) << 12)
+#define ANDES_PCU_DCSRCR0_GMAC(x)	(((x) & 0xf) << 16)
+#define ANDES_PCU_DCSRCR0_GPU(x)	(((x) & 0xf) << 20)
+
+/*
+ * Driving Capability and Slew Rate Control Register 1 (rw)
+ */
+#define ANDES_PCU_DCSRCR1_I2C(x)	(((x) & 0xf) << 0)
+
+/*
+ * Driving Capability and Slew Rate Control Register 2 (rw)
+ */
+#define ANDES_PCU_DCSRCR2_UART1(x)	(((x) & 0xf) << 0)
+#define ANDES_PCU_DCSRCR2_UART2(x)	(((x) & 0xf) << 4)
+#define ANDES_PCU_DCSRCR2_AC97(x)	(((x) & 0xf) << 8)
+#define ANDES_PCU_DCSRCR2_SPI(x)	(((x) & 0xf) << 12)
+#define ANDES_PCU_DCSRCR2_SD(x)		(((x) & 0xf) << 16)
+#define ANDES_PCU_DCSRCR2_CFC(x)	(((x) & 0xf) << 20)
+#define ANDES_PCU_DCSRCR2_GPIO(x)	(((x) & 0xf) << 24)
+#define ANDES_PCU_DCSRCR2_PCU(x)	(((x) & 0xf) << 28)
+
+/*
+ * Multi-function Port Setting Register 0 (rw)
+ */
+#define ANDES_PCU_MFPSR0_PCIMODE(x)		((x) << 0)
+#define ANDES_PCU_MFPSR0_IDEMODE(x)		((x) << 1)
+#define ANDES_PCU_MFPSR0_MINI_TC01(x)		((x) << 2)
+#define ANDES_PCU_MFPSR0_AHB_DEBUG(x)		((x) << 3)
+#define ANDES_PCU_MFPSR0_AHB_TARGET(x)		((x) << 4)
+#define ANDES_PCU_MFPSR0_DEFAULT_IVB(x)		(((x) & 0x7) << 28)
+#define ANDES_PCU_MFPSR0_DEFAULT_ENDIAN(x)	((x) << 31)
+
+/*
+ * Multi-function Port Setting Register 1 (rw)
+ */
+#define ANDES_PCU_MFPSR1_SUSPEND(x)		((x) << 0)
+#define ANDES_PCU_MFPSR1_PWM0(x)		((x) << 1)
+#define ANDES_PCU_MFPSR1_PWM1(x)		((x) << 2)
+#define ANDES_PCU_MFPSR1_AC97CLKOUT(x)		((x) << 3)
+#define ANDES_PCU_MFPSR1_PWREN(x)		((x) << 4)
+#define ANDES_PCU_MFPSR1_PME(x)			((x) << 5)
+#define ANDES_PCU_MFPSR1_I2C(x)			((x) << 6)
+#define ANDES_PCU_MFPSR1_UART1(x)		((x) << 7)
+#define ANDES_PCU_MFPSR1_UART2(x)		((x) << 8)
+#define ANDES_PCU_MFPSR1_SPI(x)			((x) << 9)
+#define ANDES_PCU_MFPSR1_SD(x)			((x) << 10)
+#define ANDES_PCU_MFPSR1_GPUPLLSRC(x)		((x) << 27)
+#define ANDES_PCU_MFPSR1_DVOMODE(x)		((x) << 28)
+#define ANDES_PCU_MFPSR1_HSMP_FAST_REQ(x)	((x) << 29)
+#define ANDES_PCU_MFPSR1_AHB_FAST_REQ(x)	((x) << 30)
+#define ANDES_PCU_MFPSR1_PMUR_EXT_INT(x)	((x) << 31)
+
+/*
+ * DMA Engine Selection Register (rw)
+ */
+#define ANDES_PCU_DMAES_AC97RX(x)		((x) << 2)
+#define ANDES_PCU_DMAES_AC97TX(x)		((x) << 3)
+#define ANDES_PCU_DMAES_UART1RX(x)		((x) << 4)
+#define ANDES_PCU_DMAES_UART1TX(x)		((x) << 5)
+#define ANDES_PCU_DMAES_UART2RX(x)		((x) << 6)
+#define ANDES_PCU_DMAES_UART2TX(x)		((x) << 7)
+#define ANDES_PCU_DMAES_SDDMA(x)		((x) << 8)
+#define ANDES_PCU_DMAES_CFCDMA(x)		((x) << 9)
+
+/*
+ * OSC Control Register (rw)
+ */
+#define ANDES_PCU_OSCC_OSCH_OFF(x)	((x) << 0)
+#define ANDES_PCU_OSCC_OSCH_STABLE(x)	((x) << 1)
+#define ANDES_PCU_OSCC_OSCH_TRI(x)	((x) << 2)
+#define ANDES_PCU_OSCC_OSCH_RANGE(x)	(((x) & 0x3) << 4)
+#define ANDES_PCU_OSCC_OSCH2_RANGE(x)	(((x) & 0x3) << 6)
+#define ANDES_PCU_OSCC_OSCH3_RANGE(x)	(((x) & 0x3) << 8)
+
+/*
+ * PWM Clock Divider Register (rw)
+ */
+#define ANDES_PCU_PWMCD_PWMDIV(x)	(((x) & 0xf) << 0)
+
+/*
+ * SoC Misc. Register (rw)
+ */
+#define ANDES_PCU_SOCMISC_RSCPUA(x)		((x) << 0)
+#define ANDES_PCU_SOCMISC_RSCPUB(x)		((x) << 1)
+#define ANDES_PCU_SOCMISC_RSPCI(x)		((x) << 2)
+#define ANDES_PCU_SOCMISC_USBWAKE(x)		((x) << 3)
+#define ANDES_PCU_SOCMISC_EXLM_WAITA(x)		(((x) & 0x3) << 4)
+#define ANDES_PCU_SOCMISC_EXLM_WAITB(x)		(((x) & 0x3) << 6)
+#define ANDES_PCU_SOCMISC_DDRPLL_BYPASS(x)	(((x) << 8)
+#define ANDES_PCU_SOCMISC_300MHZSEL(x)		(((x) << 9)
+#define ANDES_PCU_SOCMISC_DDRDLL_SRST(x)	(((x) << 10)
+#define ANDES_PCU_SOCMISC_DDRDDQ_TEST(x)	(((x) << 11)
+#define ANDES_PCU_SOCMISC_DDRDLL_TEST(x)	(((x) << 12)
+#define ANDES_PCU_SOCMISC_GPUPLL_BYPASS(x)	(((x) << 13)
+#define ANDES_PCU_SOCMISC_ENCPUA(x)		(((x) << 14)
+#define ANDES_PCU_SOCMISC_ENCPUB(x)		(((x) << 15)
+#define ANDES_PCU_SOCMISC_PWON_PWBTN(x)		(((x) << 16)
+#define ANDES_PCU_SOCMISC_PWON_GPIO1(x)		(((x) << 17)
+#define ANDES_PCU_SOCMISC_PWON_GPIO2(x)		(((x) << 18)
+#define ANDES_PCU_SOCMISC_PWON_GPIO3(x)		(((x) << 19)
+#define ANDES_PCU_SOCMISC_PWON_GPIO4(x)		(((x) << 20)
+#define ANDES_PCU_SOCMISC_PWON_GPIO5(x)		(((x) << 21)
+#define ANDES_PCU_SOCMISC_PWON_WOL(x)		(((x) << 22)
+#define ANDES_PCU_SOCMISC_PWON_RTC(x)		(((x) << 23)
+#define ANDES_PCU_SOCMISC_PWON_RTCALM(x)	(((x) << 24)
+#define ANDES_PCU_SOCMISC_PWON_XDBGIN(x)	(((x) << 25)
+#define ANDES_PCU_SOCMISC_PWON_PME(x)		(((x) << 26)
+#define ANDES_PCU_SOCMISC_PWON_PWFAIL(x)	(((x) << 27)
+#define ANDES_PCU_SOCMISC_CPUA_SRSTED(x)	(((x) << 28)
+#define ANDES_PCU_SOCMISC_CPUB_SRSTED(x)	(((x) << 29)
+#define ANDES_PCU_SOCMISC_WD_RESET(x)		(((x) << 30)
+#define ANDES_PCU_SOCMISC_HW_RESET(x)		(((x) << 31)
+
+/*
+ * BSM Control Register (rw)
+ */
+#define ANDES_PCU_BSMCR_LINK0(x)	(((x) & 0xf) << 0)
+#define ANDES_PCU_BSMCR_LINK1(x)	(((x) & 0xf) << 4)
+#define ANDES_PCU_BSMCR_SYNCSRC(x)	(((x) & 0xf) << 24)
+#define ANDES_PCU_BSMCR_CMD(x)		(((x) & 0x7) << 28)
+#define ANDES_PCU_BSMCR_IE(x)		((x) << 31)
+
+/*
+ * BSM Status Register
+ */
+#define ANDES_PCU_BSMSR_CI0(x)		(((x) & 0xf) << 0)
+#define ANDES_PCU_BSMSR_CI1(x)		(((x) & 0xf) << 4)
+#define ANDES_PCU_BSMSR_SYNCSRC(x)	(((x) & 0xf) << 24)
+#define ANDES_PCU_BSMSR_BSMST(x)	(((x) & 0xf) << 28)
+
+/*
+ * Wakeup Event Sensitivity Register (rw)
+ */
+#define ANDES_PCU_WESR_POLOR(x)		(((x) & 0xff) << 0)
+
+/*
+ * Wakeup Event Status Register (ro)
+ */
+#define ANDES_PCU_WEST_SIG(x)		(((x) & 0xff) << 0)
+
+/*
+ * Reset Timing Register
+ */
+#define ANDES_PCU_RSTTIMING_RG0(x)	(((x) & 0xff) << 0)
+#define ANDES_PCU_RSTTIMING_RG1(x)	(((x) & 0xff) << 8)
+#define ANDES_PCU_RSTTIMING_RG2(x)	(((x) & 0xff) << 16)
+#define ANDES_PCU_RSTTIMING_RG3(x)	(((x) & 0xff) << 24)
+
+/*
+ * PCU Interrupt Status Register
+ */
+#define ANDES_PCU_INTR_ST_BSM(x)	((x) << 0)
+#define ANDES_PCU_INTR_ST_PCS1(x)	((x) << 1)
+#define ANDES_PCU_INTR_ST_PCS2(x)	((x) << 2)
+#define ANDES_PCU_INTR_ST_PCS3(x)	((x) << 3)
+#define ANDES_PCU_INTR_ST_PCS4(x)	((x) << 4)
+#define ANDES_PCU_INTR_ST_PCS5(x)	((x) << 5)
+#define ANDES_PCU_INTR_ST_PCS6(x)	((x) << 6)
+#define ANDES_PCU_INTR_ST_PCS7(x)	((x) << 7)
+#define ANDES_PCU_INTR_ST_PCS8(x)	((x) << 8)
+#define ANDES_PCU_INTR_ST_PCS9(x)	((x) << 9)
+
+/*
+ * PCSx Configuration Register
+ */
+#define ANDES_PCU_PCSX_CR_WAKEUP_EN(x)	(((x) & 0xff) << 0)
+#define ANDES_PCU_PCSX_CR_LW(x)		(((x) & 0xf) << 16)
+#define ANDES_PCU_PCSX_CR_LS(x)		(((x) & 0xf) << 20)
+#define ANDES_PCU_PCSX_CR_TYPE(x)	(((x) >> 28) & 0x7)	/* (ro) */
+
+/*
+ * PCSx Parameter Register (rw)
+ */
+#define ANDES_PCU_PCSX_PARM_NEXT(x)	(((x) & 0xffffff) << 0)
+#define ANDES_PCU_PCSX_PARM_SYNCSRC(x)	(((x) & 0xf) << 24)
+#define ANDES_PCU_PCSX_PARM_PCSCMD(x)	(((x) & 0x7) << 28)
+#define ANDES_PCU_PCSX_PARM_IE(x)	(((x) << 31)
+
+/*
+ * PCSx Status Register 1
+ */
+#define ANDES_PCU_PCSX_STAT1_ERRNO(x)	(((x) & 0xf) << 0)
+#define ANDES_PCU_PCSX_STAT1_ST(x)	(((x) & 0x7) << 28)
+
+/*
+ * PCSx Status Register 2
+ */
+#define ANDES_PCU_PCSX_STAT2_CRNTPARM(x)	(((x) & 0xffffff) << 0)
+#define ANDES_PCU_PCSX_STAT2_SYNCSRC(x)		(((x) & 0xf) << 24)
+
+/*
+ * PCSx PDD Register
+ * This is reserved for PCS(1-7)
+ */
+#define ANDES_PCU_PCS8_PDD_1BYTE(x)		(((x) & 0xff) << 0)
+#define ANDES_PCU_PCS8_PDD_2BYTE(x)		(((x) & 0xff) << 8)
+#define ANDES_PCU_PCS8_PDD_3BYTE(x)		(((x) & 0xff) << 16)
+#define ANDES_PCU_PCS8_PDD_4BYTE(x)		(((x) & 0xff) << 24)
+
+#define ANDES_PCU_PCS9_PDD_TIME1(x)		(((x) & 0x3f) << 0)
+#define ANDES_PCU_PCS9_PDD_TIME2(x)		(((x) & 0x3f) << 6)
+#define ANDES_PCU_PCS9_PDD_TIME3(x)		(((x) & 0x3f) << 12)
+#define ANDES_PCU_PCS9_PDD_TIME4(x)		(((x) & 0x3f) << 18)
+#define ANDES_PCU_PCS9_PDD_TICKTYPE(x)		((x) << 24)
+#define ANDES_PCU_PCS9_PDD_GPU_SRST(x)		((x) << 27)
+#define ANDES_PCU_PCS9_PDD_PWOFFTIME(x)		(((x) & 0x3) << 28)
+#define ANDES_PCU_PCS9_PDD_SUS2DRAM(x)		((x) << 30)
+#define ANDES_PCU_PCS9_PDD_CLRPWOFF_FLAG(x)	((x) << 31)
+
+#endif	/* __ANDES_PCU_H */
diff --git a/qemu/roms/u-boot/include/ansi.h b/qemu/roms/u-boot/include/ansi.h
new file mode 100644
index 000000000..5f646344c
--- /dev/null
+++ b/qemu/roms/u-boot/include/ansi.h
@@ -0,0 +1,26 @@
+/*
+ * (C) Copyright 2012
+ * Pali Rohár <pali.rohar@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * ANSI terminal
+ */
+
+#define ANSI_CURSOR_UP			"\e[%dA"
+#define ANSI_CURSOR_DOWN		"\e[%dB"
+#define ANSI_CURSOR_FORWARD		"\e[%dC"
+#define ANSI_CURSOR_BACK		"\e[%dD"
+#define ANSI_CURSOR_NEXTLINE		"\e[%dE"
+#define ANSI_CURSOR_PREVIOUSLINE	"\e[%dF"
+#define ANSI_CURSOR_COLUMN		"\e[%dG"
+#define ANSI_CURSOR_POSITION		"\e[%d;%dH"
+#define ANSI_CURSOR_SHOW		"\e[?25h"
+#define ANSI_CURSOR_HIDE		"\e[?25l"
+#define ANSI_CLEAR_CONSOLE		"\e[2J"
+#define ANSI_CLEAR_LINE_TO_END		"\e[0K"
+#define ANSI_CLEAR_LINE			"\e[2K"
+#define ANSI_COLOR_RESET		"\e[0m"
+#define ANSI_COLOR_REVERSE		"\e[7m"
diff --git a/qemu/roms/u-boot/include/api_public.h b/qemu/roms/u-boot/include/api_public.h
new file mode 100644
index 000000000..f5c89f3f1
--- /dev/null
+++ b/qemu/roms/u-boot/include/api_public.h
@@ -0,0 +1,128 @@
+/*
+ * (C) Copyright 2007-2008 Semihalf
+ *
+ * Written by: Rafal Jaworowski <raj@semihalf.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+	BSD-2-Clause
+ */
+
+#ifndef _API_PUBLIC_H_
+#define _API_PUBLIC_H_
+
+#define API_EINVAL		1	/* invalid argument(s)	*/
+#define API_ENODEV		2	/* no device		*/
+#define API_ENOMEM		3	/* no memory		*/
+#define API_EBUSY		4	/* busy, occupied etc.	*/
+#define API_EIO			5	/* I/O error		*/
+#define API_ESYSC		6	/* syscall error	*/
+
+typedef	int (*scp_t)(int, int *, ...);
+
+#define API_SIG_VERSION	1
+#define API_SIG_MAGIC	"UBootAPI"
+#define API_SIG_MAGLEN	8
+
+struct api_signature {
+	char		magic[API_SIG_MAGLEN];	/* magic string */
+	uint16_t	version;		/* API version */
+	uint32_t	checksum;		/* checksum of this sig struct */
+	scp_t		syscall;		/* entry point to the API */
+};
+
+enum {
+	API_RSVD = 0,
+	API_GETC,
+	API_PUTC,
+	API_TSTC,
+	API_PUTS,
+	API_RESET,
+	API_GET_SYS_INFO,
+	API_UDELAY,
+	API_GET_TIMER,
+	API_DEV_ENUM,
+	API_DEV_OPEN,
+	API_DEV_CLOSE,
+	API_DEV_READ,
+	API_DEV_WRITE,
+	API_ENV_ENUM,
+	API_ENV_GET,
+	API_ENV_SET,
+	API_DISPLAY_GET_INFO,
+	API_DISPLAY_DRAW_BITMAP,
+	API_DISPLAY_CLEAR,
+	API_MAXCALL
+};
+
+#define MR_ATTR_FLASH	0x0001
+#define MR_ATTR_DRAM	0x0002
+#define MR_ATTR_SRAM	0x0003
+
+struct mem_region {
+	unsigned long	start;
+	unsigned long	size;
+	int		flags;
+};
+
+struct sys_info {
+	unsigned long		clk_bus;
+	unsigned long		clk_cpu;
+	unsigned long		bar;
+	struct mem_region	*mr;
+	int			mr_no;	/* number of memory regions */
+};
+
+#undef CONFIG_SYS_64BIT_LBA
+#ifdef CONFIG_SYS_64BIT_LBA
+typedef	u_int64_t lbasize_t;
+#else
+typedef unsigned long lbasize_t;
+#endif
+typedef unsigned long lbastart_t;
+
+#define DEV_TYP_NONE	0x0000
+#define DEV_TYP_NET	0x0001
+
+#define DEV_TYP_STOR	0x0002
+#define DT_STOR_IDE	0x0010
+#define DT_STOR_SCSI	0x0020
+#define DT_STOR_USB	0x0040
+#define DT_STOR_MMC	0x0080
+#define DT_STOR_SATA	0x0100
+
+#define DEV_STA_CLOSED	0x0000		/* invalid, closed */
+#define DEV_STA_OPEN	0x0001		/* open i.e. active */
+
+struct device_info {
+	int	type;
+	void	*cookie;
+
+	union {
+		struct {
+			lbasize_t	block_count;	/* no of blocks */
+			unsigned long	block_size;	/* size of one block */
+		} storage;
+
+		struct {
+			unsigned char	hwaddr[6];
+		} net;
+	} info;
+#define di_stor info.storage
+#define di_net info.net
+
+	int	state;
+};
+
+#define DISPLAY_TYPE_LCD	0x0001
+#define DISPLAY_TYPE_VIDEO	0x0002
+
+struct display_info {
+	int type;
+	/* screen size in pixels */
+	int pixel_width;
+	int pixel_height;
+	/* screen size in rows and columns of text */
+	int screen_rows;
+	int screen_cols;
+};
+
+#endif /* _API_PUBLIC_H_ */
diff --git a/qemu/roms/u-boot/include/armcoremodule.h b/qemu/roms/u-boot/include/armcoremodule.h
new file mode 100644
index 000000000..cc6f2b4d3
--- /dev/null
+++ b/qemu/roms/u-boot/include/armcoremodule.h
@@ -0,0 +1,76 @@
+/*
+ * (C) Copyright 2005
+ * ARM Ltd.
+ * Peter Pearse, <Peter.Pearse@arm.com>
+ * Configuration for ARM Core Modules.
+ * No standalonw port yet available
+ * - this file is included by both integratorap.h & integratorcp.h
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ARMCOREMODULE_H
+#define __ARMCOREMODULE_H
+
+#define CM_BASE			0x10000000
+
+/* CM registers common to all CMs */
+/* Note that observed values after reboot into the ARM Boot Monitor
+   have been used as defaults, rather than the POR values */
+#define OS_CTRL			0x0000000C
+#define CMMASK_REMAP		0x00000005	/* set remap & led           */
+#define CMMASK_RESET		0x00000008
+#define OS_LOCK			0x00000014
+#define CMVAL_LOCK1		0x0000A000	/* locking value             */
+#define CMVAL_LOCK2		0x0000005F	/* locking value             */
+#define CMVAL_UNLOCK		0x00000000	/* any value != CM_LOCKVAL   */
+#define OS_SDRAM		0x00000020
+#define OS_INIT			0x00000024
+#define CMMASK_MAP_SIMPLE	0xFFFDFFFF	/* simple mapping */
+#define CMMASK_TCRAM_DISABLE	0xFFFEFFFF	/* TCRAM disabled */
+#define CMMASK_LOWVEC		0x00000000	/* vectors @ 0x00000000 */
+#define CMMASK_LE		0xFFFFFFF7	/* little endian */
+#define CMMASK_CMxx6_COMMON	0x00000013      /* Common value for CMxx6 */
+						/* - observed reset value of */
+						/*   CM926EJ-S */
+						/*   CM1136-EJ-S */
+
+#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E)
+#define CMMASK_INIT_102	0x00000300		/* see CM102xx ref manual */
+						/* - PLL test clock bypassed */
+						/* - bus clock ratio 2 */
+						/* - little endian */
+						/* - vectors at zero */
+#endif /* CM1022xx */
+
+/* Determine CM characteristics */
+
+#undef	CONFIG_CM_MULTIPLE_SSRAM
+#undef	CONFIG_CM_SPD_DETECT
+#undef	CONFIG_CM_REMAP
+#undef	CONFIG_CM_INIT
+#undef	CONFIG_CM_TCRAM
+
+#if defined (CONFIG_CM946E_S) || defined (CONFIG_CM966E_S)
+#define	CONFIG_CM_MULTIPLE_SSRAM	/* CM has multiple SSRAM mapping */
+#endif
+
+/* Excalibur core module has reduced functionality */
+#ifndef	CONFIG_CM922T_XA10
+#define CONFIG_CM_SPD_DETECT			/* CM supports SPD query      */
+#define OS_SPD			0x00000100	/* Address of SPD data        */
+#define CONFIG_CM_REMAP				/* CM supports remapping      */
+#define CONFIG_CM_INIT				/* CM has initialization reg  */
+#endif	/* NOT EXCALIBUR */
+
+#if defined(CONFIG_CM926EJ_S)   || defined (CONFIG_CM946E_S)	|| \
+    defined(CONFIG_CM966E_S)    || defined (CONFIG_CM1026EJ_S)	|| \
+    defined(CONFIG_CM1136JF_S)
+#define CONFIG_CM_TCRAM				/* CM has TCRAM  */
+#endif
+
+#ifdef CONFIG_CM_SPD_DETECT
+#define OS_SPD		0x00000100	/* The SDRAM SPD data is copied here */
+#endif
+
+#endif /* __ARMCOREMODULE_H */
diff --git a/qemu/roms/u-boot/include/asm-generic/errno.h b/qemu/roms/u-boot/include/asm-generic/errno.h
new file mode 100644
index 000000000..523defbab
--- /dev/null
+++ b/qemu/roms/u-boot/include/asm-generic/errno.h
@@ -0,0 +1,139 @@
+/*
+ * U-boot - errno.h Error number defines
+ *
+ * Copyright (c) 2005-2007 Analog Devices Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _GENERIC_ERRNO_H
+#define _GENERIC_ERRNO_H
+
+#define	EPERM		1	/* Operation not permitted */
+#define	ENOENT		2	/* No such file or directory */
+#define	ESRCH		3	/* No such process */
+#define	EINTR		4	/* Interrupted system call */
+#define	EIO		5	/* I/O error */
+#define	ENXIO		6	/* No such device or address */
+#define	E2BIG		7	/* Argument list too long */
+#define	ENOEXEC		8	/* Exec format error */
+#define	EBADF		9	/* Bad file number */
+#define	ECHILD		10	/* No child processes */
+#define	EAGAIN		11	/* Try again */
+#define	ENOMEM		12	/* Out of memory */
+#define	EACCES		13	/* Permission denied */
+#define	EFAULT		14	/* Bad address */
+#define	ENOTBLK		15	/* Block device required */
+#define	EBUSY		16	/* Device or resource busy */
+#define	EEXIST		17	/* File exists */
+#define	EXDEV		18	/* Cross-device link */
+#define	ENODEV		19	/* No such device */
+#define	ENOTDIR		20	/* Not a directory */
+#define	EISDIR		21	/* Is a directory */
+#define	EINVAL		22	/* Invalid argument */
+#define	ENFILE		23	/* File table overflow */
+#define	EMFILE		24	/* Too many open files */
+#define	ENOTTY		25	/* Not a typewriter */
+#define	ETXTBSY		26	/* Text file busy */
+#define	EFBIG		27	/* File too large */
+#define	ENOSPC		28	/* No space left on device */
+#define	ESPIPE		29	/* Illegal seek */
+#define	EROFS		30	/* Read-only file system */
+#define	EMLINK		31	/* Too many links */
+#define	EPIPE		32	/* Broken pipe */
+#define	EDOM		33	/* Math argument out of domain of func */
+#define	ERANGE		34	/* Math result not representable */
+#define	EDEADLK		35	/* Resource deadlock would occur */
+#define	ENAMETOOLONG	36	/* File name too long */
+#define	ENOLCK		37	/* No record locks available */
+#define	ENOSYS		38	/* Function not implemented */
+#define	ENOTEMPTY	39	/* Directory not empty */
+#define	ELOOP		40	/* Too many symbolic links encountered */
+#define	EWOULDBLOCK	EAGAIN	/* Operation would block */
+#define	ENOMSG		42	/* No message of desired type */
+#define	EIDRM		43	/* Identifier removed */
+#define	ECHRNG		44	/* Channel number out of range */
+#define	EL2NSYNC	45	/* Level 2 not synchronized */
+#define	EL3HLT		46	/* Level 3 halted */
+#define	EL3RST		47	/* Level 3 reset */
+#define	ELNRNG		48	/* Link number out of range */
+#define	EUNATCH		49	/* Protocol driver not attached */
+#define	ENOCSI		50	/* No CSI structure available */
+#define	EL2HLT		51	/* Level 2 halted */
+#define	EBADE		52	/* Invalid exchange */
+#define	EBADR		53	/* Invalid request descriptor */
+#define	EXFULL		54	/* Exchange full */
+#define	ENOANO		55	/* No anode */
+#define	EBADRQC		56	/* Invalid request code */
+#define	EBADSLT		57	/* Invalid slot */
+
+#define	EDEADLOCK	EDEADLK
+
+#define	EBFONT		59	/* Bad font file format */
+#define	ENOSTR		60	/* Device not a stream */
+#define	ENODATA		61	/* No data available */
+#define	ETIME		62	/* Timer expired */
+#define	ENOSR		63	/* Out of streams resources */
+#define	ENONET		64	/* Machine is not on the network */
+#define	ENOPKG		65	/* Package not installed */
+#define	EREMOTE		66	/* Object is remote */
+#define	ENOLINK		67	/* Link has been severed */
+#define	EADV		68	/* Advertise error */
+#define	ESRMNT		69	/* Srmount error */
+#define	ECOMM		70	/* Communication error on send */
+#define	EPROTO		71	/* Protocol error */
+#define	EMULTIHOP	72	/* Multihop attempted */
+#define	EDOTDOT		73	/* RFS specific error */
+#define	EBADMSG		74	/* Not a data message */
+#define	EOVERFLOW	75	/* Value too large for defined data type */
+#define	ENOTUNIQ	76	/* Name not unique on network */
+#define	EBADFD		77	/* File descriptor in bad state */
+#define	EREMCHG		78	/* Remote address changed */
+#define	ELIBACC		79	/* Can not access a needed shared library */
+#define	ELIBBAD		80	/* Accessing a corrupted shared library */
+#define	ELIBSCN		81	/* .lib section in a.out corrupted */
+#define	ELIBMAX		82	/* Attempting to link in too many shared libraries */
+#define	ELIBEXEC	83	/* Cannot exec a shared library directly */
+#define	EILSEQ		84	/* Illegal byte sequence */
+#define	ERESTART	85	/* Interrupted system call should be restarted */
+#define	ESTRPIPE	86	/* Streams pipe error */
+#define	EUSERS		87	/* Too many users */
+#define	ENOTSOCK	88	/* Socket operation on non-socket */
+#define	EDESTADDRREQ	89	/* Destination address required */
+#define	EMSGSIZE	90	/* Message too long */
+#define	EPROTOTYPE	91	/* Protocol wrong type for socket */
+#define	ENOPROTOOPT	92	/* Protocol not available */
+#define	EPROTONOSUPPORT	93	/* Protocol not supported */
+#define	ESOCKTNOSUPPORT	94	/* Socket type not supported */
+#define	EOPNOTSUPP	95	/* Operation not supported on transport endpoint */
+#define	EPFNOSUPPORT	96	/* Protocol family not supported */
+#define	EAFNOSUPPORT	97	/* Address family not supported by protocol */
+#define	EADDRINUSE	98	/* Address already in use */
+#define	EADDRNOTAVAIL	99	/* Cannot assign requested address */
+#define	ENETDOWN	100	/* Network is down */
+#define	ENETUNREACH	101	/* Network is unreachable */
+#define	ENETRESET	102	/* Network dropped connection because of reset */
+#define	ECONNABORTED	103	/* Software caused connection abort */
+#define	ECONNRESET	104	/* Connection reset by peer */
+#define	ENOBUFS		105	/* No buffer space available */
+#define	EISCONN		106	/* Transport endpoint is already connected */
+#define	ENOTCONN	107	/* Transport endpoint is not connected */
+#define	ESHUTDOWN	108	/* Cannot send after transport endpoint shutdown */
+#define	ETOOMANYREFS	109	/* Too many references: cannot splice */
+#define	ETIMEDOUT	110	/* Connection timed out */
+#define	ECONNREFUSED	111	/* Connection refused */
+#define	EHOSTDOWN	112	/* Host is down */
+#define	EHOSTUNREACH	113	/* No route to host */
+#define	EALREADY	114	/* Operation already in progress */
+#define	EINPROGRESS	115	/* Operation now in progress */
+#define	ESTALE		116	/* Stale NFS file handle */
+#define	EUCLEAN		117	/* Structure needs cleaning */
+#define	ENOTNAM		118	/* Not a XENIX named type file */
+#define	ENAVAIL		119	/* No XENIX semaphores available */
+#define	EISNAM		120	/* Is a named type file */
+#define	EREMOTEIO	121	/* Remote I/O error */
+#define	EDQUOT		122	/* Quota exceeded */
+#define	ENOMEDIUM	123	/* No medium found */
+#define	EMEDIUMTYPE	124	/* Wrong medium type */
+
+#endif
diff --git a/qemu/roms/u-boot/include/asm-generic/global_data.h b/qemu/roms/u-boot/include/asm-generic/global_data.h
new file mode 100644
index 000000000..e98b661e3
--- /dev/null
+++ b/qemu/roms/u-boot/include/asm-generic/global_data.h
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ * (C) Copyright 2002-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_GENERIC_GBL_DATA_H
+#define __ASM_GENERIC_GBL_DATA_H
+/*
+ * The following data structure is placed in some memory which is
+ * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
+ * some locked parts of the data cache) to allow for a minimum set of
+ * global variables during system initialization (until we have set
+ * up the memory controller so that we can use RAM).
+ *
+ * Keep it *SMALL* and remember to set GENERATED_GBL_DATA_SIZE > sizeof(gd_t)
+ *
+ * Each architecture has its own private fields. For now all are private
+ */
+
+#ifndef __ASSEMBLY__
+#include <linux/list.h>
+
+typedef struct global_data {
+	bd_t *bd;
+	unsigned long flags;
+	unsigned int baudrate;
+	unsigned long cpu_clk;	/* CPU clock in Hz!		*/
+	unsigned long bus_clk;
+	/* We cannot bracket this with CONFIG_PCI due to mpc5xxx */
+	unsigned long pci_clk;
+	unsigned long mem_clk;
+#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO)
+	unsigned long fb_base;	/* Base address of framebuffer mem */
+#endif
+#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
+	unsigned long post_log_word;  /* Record POST activities */
+	unsigned long post_log_res; /* success of POST test */
+	unsigned long post_init_f_time;  /* When post_init_f started */
+#endif
+#ifdef CONFIG_BOARD_TYPES
+	unsigned long board_type;
+#endif
+	unsigned long have_console;	/* serial_init() was called */
+#ifdef CONFIG_PRE_CONSOLE_BUFFER
+	unsigned long precon_buf_idx;	/* Pre-Console buffer index */
+#endif
+#ifdef CONFIG_MODEM_SUPPORT
+	unsigned long do_mdm_init;
+	unsigned long be_quiet;
+#endif
+	unsigned long env_addr;	/* Address  of Environment struct */
+	unsigned long env_valid;	/* Checksum of Environment valid? */
+
+	unsigned long ram_top;	/* Top address of RAM used by U-Boot */
+
+	unsigned long relocaddr;	/* Start address of U-Boot in RAM */
+	phys_size_t ram_size;	/* RAM size */
+	unsigned long mon_len;	/* monitor len */
+	unsigned long irq_sp;		/* irq stack pointer */
+	unsigned long start_addr_sp;	/* start_addr_stackpointer */
+	unsigned long reloc_off;
+	struct global_data *new_gd;	/* relocated global data */
+
+#ifdef CONFIG_DM
+	struct device	*dm_root;	/* Root instance for Driver Model */
+	struct list_head uclass_root;	/* Head of core tree */
+#endif
+
+	const void *fdt_blob;	/* Our device tree, NULL if none */
+	void *new_fdt;		/* Relocated FDT */
+	unsigned long fdt_size;	/* Space reserved for relocated FDT */
+	void **jt;		/* jump table */
+	char env_buf[32];	/* buffer for getenv() before reloc. */
+#ifdef CONFIG_TRACE
+	void		*trace_buff;	/* The trace buffer */
+#endif
+#if defined(CONFIG_SYS_I2C)
+	int		cur_i2c_bus;	/* current used i2c bus */
+#endif
+#ifdef CONFIG_SYS_I2C_MXC
+	void *srdata[10];
+#endif
+	unsigned long timebase_h;
+	unsigned long timebase_l;
+	struct arch_global_data arch;	/* architecture-specific data */
+} gd_t;
+#endif
+
+/*
+ * Global Data Flags
+ */
+#define GD_FLG_RELOC		0x00001	/* Code was relocated to RAM	   */
+#define GD_FLG_DEVINIT		0x00002	/* Devices have been initialized   */
+#define GD_FLG_SILENT		0x00004	/* Silent mode			   */
+#define GD_FLG_POSTFAIL		0x00008	/* Critical POST test failed	   */
+#define GD_FLG_POSTSTOP		0x00010	/* POST seqeunce aborted	   */
+#define GD_FLG_LOGINIT		0x00020	/* Log Buffer has been initialized */
+#define GD_FLG_DISABLE_CONSOLE	0x00040	/* Disable console (in & out)	   */
+#define GD_FLG_ENV_READY	0x00080	/* Env. imported into hash table   */
+
+#endif /* __ASM_GENERIC_GBL_DATA_H */
diff --git a/qemu/roms/u-boot/include/asm-generic/gpio.h b/qemu/roms/u-boot/include/asm-generic/gpio.h
new file mode 100644
index 000000000..e325df40d
--- /dev/null
+++ b/qemu/roms/u-boot/include/asm-generic/gpio.h
@@ -0,0 +1,185 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * Copyright (c) 2011, NVIDIA Corp. All rights reserved.
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_GENERIC_GPIO_H_
+#define _ASM_GENERIC_GPIO_H_
+
+/*
+ * Generic GPIO API for U-Boot
+ *
+ * GPIOs are numbered from 0 to GPIO_COUNT-1 which value is defined
+ * by the SOC/architecture.
+ *
+ * Each GPIO can be an input or output. If an input then its value can
+ * be read as 0 or 1. If an output then its value can be set to 0 or 1.
+ * If you try to write an input then the value is undefined. If you try
+ * to read an output, barring something very unusual,  you will get
+ * back the value of the output that you previously set.
+ *
+ * In some cases the operation may fail, for example if the GPIO number
+ * is out of range, or the GPIO is not available because its pin is
+ * being used by another function. In that case, functions may return
+ * an error value of -1.
+ */
+
+/**
+ * Request a gpio. This should be called before any of the other functions
+ * are used on this gpio.
+ *
+ * @param gp	GPIO number
+ * @param label	User label for this GPIO
+ * @return 0 if ok, -1 on error
+ */
+int gpio_request(unsigned gpio, const char *label);
+
+/**
+ * Stop using the GPIO.  This function should not alter pin configuration.
+ *
+ * @param gpio	GPIO number
+ * @return 0 if ok, -1 on error
+ */
+int gpio_free(unsigned gpio);
+
+/**
+ * Make a GPIO an input.
+ *
+ * @param gpio	GPIO number
+ * @return 0 if ok, -1 on error
+ */
+int gpio_direction_input(unsigned gpio);
+
+/**
+ * Make a GPIO an output, and set its value.
+ *
+ * @param gpio	GPIO number
+ * @param value	GPIO value (0 for low or 1 for high)
+ * @return 0 if ok, -1 on error
+ */
+int gpio_direction_output(unsigned gpio, int value);
+
+/**
+ * Get a GPIO's value. This will work whether the GPIO is an input
+ * or an output.
+ *
+ * @param gpio	GPIO number
+ * @return 0 if low, 1 if high, -1 on error
+ */
+int gpio_get_value(unsigned gpio);
+
+/**
+ * Set an output GPIO's value. The GPIO must already be an output or
+ * this function may have no effect.
+ *
+ * @param gpio	GPIO number
+ * @param value	GPIO value (0 for low or 1 for high)
+ * @return 0 if ok, -1 on error
+ */
+int gpio_set_value(unsigned gpio, int value);
+
+/* State of a GPIO, as reported by get_state() */
+enum {
+	GPIOF_INPUT = 0,
+	GPIOF_OUTPUT,
+	GPIOF_UNKNOWN,
+};
+
+struct device;
+
+/**
+ * struct struct dm_gpio_ops - Driver model GPIO operations
+ *
+ * Refer to functions above for description. These function largely copy
+ * the old API.
+ *
+ * This is trying to be close to Linux GPIO API. Once the U-Boot uses the
+ * new DM GPIO API, this should be really easy to flip over to the Linux
+ * GPIO API-alike interface.
+ *
+ * Akso it would be useful to standardise additional functions like
+ * pullup, slew rate and drive strength.
+ *
+ * gpio_request)( and gpio_free() are optional - if NULL then they will
+ * not be called.
+ *
+ * Note that @offset is the offset from the base GPIO of the device. So
+ * offset 0 is the device's first GPIO and offset o-1 is the last GPIO,
+ * where o is the number of GPIO lines controlled by the device. A device
+ * is typically used to control a single bank of GPIOs. Within complex
+ * SoCs there may be many banks and therefore many devices all referring
+ * to the different IO addresses within the SoC.
+ *
+ * The uclass combines all GPIO devices togther to provide a consistent
+ * numbering from 0 to n-1, where n is the number of GPIOs in total across
+ * all devices. Be careful not to confuse offset with gpio in the parameters.
+ */
+struct dm_gpio_ops {
+	int (*request)(struct device *dev, unsigned offset, const char *label);
+	int (*free)(struct device *dev, unsigned offset);
+	int (*direction_input)(struct device *dev, unsigned offset);
+	int (*direction_output)(struct device *dev, unsigned offset,
+				int value);
+	int (*get_value)(struct device *dev, unsigned offset);
+	int (*set_value)(struct device *dev, unsigned offset, int value);
+	int (*get_function)(struct device *dev, unsigned offset);
+	int (*get_state)(struct device *dev, unsigned offset, char *state,
+			 int maxlen);
+};
+
+/**
+ * struct gpio_dev_priv - information about a device used by the uclass
+ *
+ * The uclass combines all active GPIO devices into a unified numbering
+ * scheme. To do this it maintains some private information aobut each
+ * device.
+ *
+ * To implement driver model support in your GPIO driver, add a probe
+ * handler, and set @gpio_count and @bank_name correctly in that handler.
+ * This tells the uclass the name of the GPIO bank and the number of GPIOs
+ * it contains.
+ *
+ * @bank_name: Name of the GPIO device (e.g 'a' means GPIOs will be called
+ * 'A0', 'A1', etc.
+ * @gpio_count: Number of GPIOs in this device
+ * @gpio_base: Base GPIO number for this device. For the first active device
+ * this will be 0; the numbering for others will follow sequentially so that
+ * @gpio_base for device 1 will equal the number of GPIOs in device 0.
+ */
+struct gpio_dev_priv {
+	const char *bank_name;
+	unsigned gpio_count;
+	unsigned gpio_base;
+};
+
+/* Access the GPIO operations for a device */
+#define gpio_get_ops(dev)	((struct dm_gpio_ops *)(dev)->driver->ops)
+
+/**
+ * gpio_get_bank_info - Return information about a GPIO bank/device
+ *
+ * This looks up a device and returns both its GPIO base name and the number
+ * of GPIOs it controls.
+ *
+ * @dev: Device to look up
+ * @offset_count: Returns number of GPIOs within this bank
+ * @return bank name of this device
+ */
+const char *gpio_get_bank_info(struct device *dev, int *offset_count);
+
+/**
+ * gpio_lookup_name - Look up a GPIO name and return its details
+ *
+ * This is used to convert a named GPIO into a device, offset and GPIO
+ * number.
+ *
+ * @name: GPIO name to look up
+ * @devp: Returns pointer to device which contains this GPIO
+ * @offsetp: Returns the offset number within this device
+ * @gpiop: Returns the absolute GPIO number, numbered from 0
+ */
+int gpio_lookup_name(const char *name, struct device **devp,
+		     unsigned int *offsetp, unsigned int *gpiop);
+
+#endif	/* _ASM_GENERIC_GPIO_H_ */
diff --git a/qemu/roms/u-boot/include/asm-generic/ioctl.h b/qemu/roms/u-boot/include/asm-generic/ioctl.h
new file mode 100644
index 000000000..15828b2d6
--- /dev/null
+++ b/qemu/roms/u-boot/include/asm-generic/ioctl.h
@@ -0,0 +1,105 @@
+#ifndef _ASM_GENERIC_IOCTL_H
+#define _ASM_GENERIC_IOCTL_H
+
+/* ioctl command encoding: 32 bits total, command in lower 16 bits,
+ * size of the parameter structure in the lower 14 bits of the
+ * upper 16 bits.
+ * Encoding the size of the parameter structure in the ioctl request
+ * is useful for catching programs compiled with old versions
+ * and to avoid overwriting user space outside the user buffer area.
+ * The highest 2 bits are reserved for indicating the ``access mode''.
+ * NOTE: This limits the max parameter size to 16kB -1 !
+ */
+
+/*
+ * The following is for compatibility across the various Linux
+ * platforms.  The generic ioctl numbering scheme doesn't really enforce
+ * a type field.  De facto, however, the top 8 bits of the lower 16
+ * bits are indeed used as a type field, so we might just as well make
+ * this explicit here.  Please be sure to use the decoding macros
+ * below from now on.
+ */
+#define _IOC_NRBITS	8
+#define _IOC_TYPEBITS	8
+
+/*
+ * Let any architecture override either of the following before
+ * including this file.
+ */
+
+#ifndef _IOC_SIZEBITS
+# define _IOC_SIZEBITS	14
+#endif
+
+#ifndef _IOC_DIRBITS
+# define _IOC_DIRBITS	2
+#endif
+
+#define _IOC_NRMASK	((1 << _IOC_NRBITS)-1)
+#define _IOC_TYPEMASK	((1 << _IOC_TYPEBITS)-1)
+#define _IOC_SIZEMASK	((1 << _IOC_SIZEBITS)-1)
+#define _IOC_DIRMASK	((1 << _IOC_DIRBITS)-1)
+
+#define _IOC_NRSHIFT	0
+#define _IOC_TYPESHIFT	(_IOC_NRSHIFT+_IOC_NRBITS)
+#define _IOC_SIZESHIFT	(_IOC_TYPESHIFT+_IOC_TYPEBITS)
+#define _IOC_DIRSHIFT	(_IOC_SIZESHIFT+_IOC_SIZEBITS)
+
+/*
+ * Direction bits, which any architecture can choose to override
+ * before including this file.
+ */
+
+#ifndef _IOC_NONE
+# define _IOC_NONE	0U
+#endif
+
+#ifndef _IOC_WRITE
+# define _IOC_WRITE	1U
+#endif
+
+#ifndef _IOC_READ
+# define _IOC_READ	2U
+#endif
+
+#define _IOC(dir,type,nr,size) \
+	(((dir)  << _IOC_DIRSHIFT) | \
+	 ((type) << _IOC_TYPESHIFT) | \
+	 ((nr)   << _IOC_NRSHIFT) | \
+	 ((size) << _IOC_SIZESHIFT))
+
+#ifdef __KERNEL__
+/* provoke compile error for invalid uses of size argument */
+extern unsigned int __invalid_size_argument_for_IOC;
+#define _IOC_TYPECHECK(t) \
+	((sizeof(t) == sizeof(t[1]) && \
+	  sizeof(t) < (1 << _IOC_SIZEBITS)) ? \
+	  sizeof(t) : __invalid_size_argument_for_IOC)
+#else
+#define _IOC_TYPECHECK(t) (sizeof(t))
+#endif
+
+/* used to create numbers */
+#define _IO(type,nr)		_IOC(_IOC_NONE,(type),(nr),0)
+#define _IOR(type,nr,size)	_IOC(_IOC_READ,(type),(nr),(_IOC_TYPECHECK(size)))
+#define _IOW(type,nr,size)	_IOC(_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size)))
+#define _IOWR(type,nr,size)	_IOC(_IOC_READ|_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size)))
+#define _IOR_BAD(type,nr,size)	_IOC(_IOC_READ,(type),(nr),sizeof(size))
+#define _IOW_BAD(type,nr,size)	_IOC(_IOC_WRITE,(type),(nr),sizeof(size))
+#define _IOWR_BAD(type,nr,size)	_IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size))
+
+/* used to decode ioctl numbers.. */
+#define _IOC_DIR(nr)		(((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK)
+#define _IOC_TYPE(nr)		(((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK)
+#define _IOC_NR(nr)		(((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK)
+#define _IOC_SIZE(nr)		(((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK)
+
+/* ...and for the drivers/sound files... */
+
+#define IOC_IN		(_IOC_WRITE << _IOC_DIRSHIFT)
+#define IOC_OUT		(_IOC_READ << _IOC_DIRSHIFT)
+#define IOC_INOUT	((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT)
+#define IOCSIZE_MASK	(_IOC_SIZEMASK << _IOC_SIZESHIFT)
+#define IOCSIZE_SHIFT	(_IOC_SIZESHIFT)
+
+#endif /* _ASM_GENERIC_IOCTL_H */
diff --git a/qemu/roms/u-boot/include/asm-generic/sections.h b/qemu/roms/u-boot/include/asm-generic/sections.h
new file mode 100644
index 000000000..458952fb5
--- /dev/null
+++ b/qemu/roms/u-boot/include/asm-generic/sections.h
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* Taken from Linux kernel, commit f56c3196 */
+
+#ifndef _ASM_GENERIC_SECTIONS_H_
+#define _ASM_GENERIC_SECTIONS_H_
+
+/* References to section boundaries */
+
+extern char _text[], _stext[], _etext[];
+extern char _data[], _sdata[], _edata[];
+extern char __bss_start[], __bss_stop[];
+extern char __init_begin[], __init_end[];
+extern char _sinittext[], _einittext[];
+extern char _end[], _init[];
+extern char __per_cpu_load[], __per_cpu_start[], __per_cpu_end[];
+extern char __kprobes_text_start[], __kprobes_text_end[];
+extern char __entry_text_start[], __entry_text_end[];
+extern char __initdata_begin[], __initdata_end[];
+extern char __start_rodata[], __end_rodata[];
+
+/* Start and end of .ctors section - used for constructor calls. */
+extern char __ctors_start[], __ctors_end[];
+
+/* function descriptor handling (if any).  Override
+ * in asm/sections.h */
+#ifndef dereference_function_descriptor
+#define dereference_function_descriptor(p) (p)
+#endif
+
+/* random extra sections (if any).  Override
+ * in asm/sections.h */
+#ifndef arch_is_kernel_text
+static inline int arch_is_kernel_text(unsigned long addr)
+{
+	return 0;
+}
+#endif
+
+#ifndef arch_is_kernel_data
+static inline int arch_is_kernel_data(unsigned long addr)
+{
+	return 0;
+}
+#endif
+
+/* U-Boot-specific things begin here */
+
+/* Start of U-Boot text region */
+extern char __text_start[];
+
+/* This marks the end of the text region which must be relocated */
+extern char __image_copy_end[];
+
+/*
+ * This is the U-Boot entry point - prior to relocation it should be same
+ * as __text_start
+ */
+extern void _start(void);
+
+/*
+ * ARM defines its symbols as char[]. Other arches define them as ulongs.
+ */
+#ifdef CONFIG_ARM
+
+extern char __bss_start[];
+extern char __bss_end[];
+extern char __image_copy_start[];
+extern char __image_copy_end[];
+extern char __rel_dyn_start[];
+extern char __rel_dyn_end[];
+
+#else /* don't use offsets: */
+
+/* Exports from the Linker Script */
+extern ulong __data_end;
+extern ulong __rel_dyn_start;
+extern ulong __rel_dyn_end;
+extern ulong __bss_end;
+
+extern ulong _TEXT_BASE;	/* code start */
+
+#endif
+
+#endif /* _ASM_GENERIC_SECTIONS_H_ */
diff --git a/qemu/roms/u-boot/include/asm-generic/signal.h b/qemu/roms/u-boot/include/asm-generic/signal.h
new file mode 100644
index 000000000..af939478c
--- /dev/null
+++ b/qemu/roms/u-boot/include/asm-generic/signal.h
@@ -0,0 +1,101 @@
+#ifndef __ASM_GENERIC_SIGNAL_H
+#define __ASM_GENERIC_SIGNAL_H
+
+#include <linux/types.h>
+
+#define _NSIG		64
+#define _NSIG_BPW	BITS_PER_LONG
+#define _NSIG_WORDS	(_NSIG / _NSIG_BPW)
+
+#define SIGHUP		 1
+#define SIGINT		 2
+#define SIGQUIT		 3
+#define SIGILL		 4
+#define SIGTRAP		 5
+#define SIGABRT		 6
+#define SIGIOT		 6
+#define SIGBUS		 7
+#define SIGFPE		 8
+#define SIGKILL		 9
+#define SIGUSR1		10
+#define SIGSEGV		11
+#define SIGUSR2		12
+#define SIGPIPE		13
+#define SIGALRM		14
+#define SIGTERM		15
+#define SIGSTKFLT	16
+#define SIGCHLD		17
+#define SIGCONT		18
+#define SIGSTOP		19
+#define SIGTSTP		20
+#define SIGTTIN		21
+#define SIGTTOU		22
+#define SIGURG		23
+#define SIGXCPU		24
+#define SIGXFSZ		25
+#define SIGVTALRM	26
+#define SIGPROF		27
+#define SIGWINCH	28
+#define SIGIO		29
+#define SIGPOLL		SIGIO
+/*
+#define SIGLOST		29
+*/
+#define SIGPWR		30
+#define SIGSYS		31
+#define	SIGUNUSED	31
+
+/* These should not be considered constants from userland.  */
+#define SIGRTMIN	32
+#ifndef SIGRTMAX
+#define SIGRTMAX	_NSIG
+#endif
+
+/*
+ * SA_FLAGS values:
+ *
+ * SA_ONSTACK indicates that a registered stack_t will be used.
+ * SA_RESTART flag to get restarting signals (which were the default long ago)
+ * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
+ * SA_RESETHAND clears the handler when the signal is delivered.
+ * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
+ * SA_NODEFER prevents the current signal from being masked in the handler.
+ *
+ * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
+ * Unix names RESETHAND and NODEFER respectively.
+ */
+#define SA_NOCLDSTOP	0x00000001
+#define SA_NOCLDWAIT	0x00000002
+#define SA_SIGINFO	0x00000004
+#define SA_ONSTACK	0x08000000
+#define SA_RESTART	0x10000000
+#define SA_NODEFER	0x40000000
+#define SA_RESETHAND	0x80000000
+
+#define SA_NOMASK	SA_NODEFER
+#define SA_ONESHOT	SA_RESETHAND
+
+/*
+ * New architectures should not define the obsolete
+ *	SA_RESTORER	0x04000000
+ */
+
+/*
+ * sigaltstack controls
+ */
+#define SS_ONSTACK	1
+#define SS_DISABLE	2
+
+#define MINSIGSTKSZ	2048
+#define SIGSTKSZ	8192
+
+#ifndef __ASSEMBLY__
+typedef struct {
+	unsigned long sig[_NSIG_WORDS];
+} sigset_t;
+
+/* not actually used, but required for linux/syscalls.h */
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASM_GENERIC_SIGNAL_H */
diff --git a/qemu/roms/u-boot/include/asm-generic/u-boot.h b/qemu/roms/u-boot/include/asm-generic/u-boot.h
new file mode 100644
index 000000000..62cb1eabc
--- /dev/null
+++ b/qemu/roms/u-boot/include/asm-generic/u-boot.h
@@ -0,0 +1,135 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * (C) Copyright 2000 - 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
+ */
+
+#ifndef __ASM_GENERIC_U_BOOT_H__
+#define __ASM_GENERIC_U_BOOT_H__
+
+/*
+ * Board information passed to Linux kernel from U-Boot
+ *
+ * include/asm-ppc/u-boot.h
+ */
+
+#ifndef __ASSEMBLY__
+
+typedef struct bd_info {
+	unsigned long	bi_memstart;	/* start of DRAM memory */
+	phys_size_t	bi_memsize;	/* size	 of DRAM memory in bytes */
+	unsigned long	bi_flashstart;	/* start of FLASH memory */
+	unsigned long	bi_flashsize;	/* size	 of FLASH memory */
+	unsigned long	bi_flashoffset; /* reserved area for startup monitor */
+	unsigned long	bi_sramstart;	/* start of SRAM memory */
+	unsigned long	bi_sramsize;	/* size	 of SRAM memory */
+#ifdef CONFIG_ARM
+	unsigned long	bi_arm_freq; /* arm frequency */
+	unsigned long	bi_dsp_freq; /* dsp core frequency */
+	unsigned long	bi_ddr_freq; /* ddr frequency */
+#endif
+#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_MPC8260) \
+	|| defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
+	unsigned long	bi_immr_base;	/* base of IMMR register */
+#endif
+#if defined(CONFIG_MPC5xxx)
+	unsigned long	bi_mbar_base;	/* base of internal registers */
+#endif
+#if defined(CONFIG_MPC83xx)
+	unsigned long	bi_immrbar;
+#endif
+	unsigned long	bi_bootflags;	/* boot / reboot flag (Unused) */
+	unsigned long	bi_ip_addr;	/* IP Address */
+	unsigned char	bi_enetaddr[6];	/* OLD: see README.enetaddr */
+	unsigned short	bi_ethspeed;	/* Ethernet speed in Mbps */
+	unsigned long	bi_intfreq;	/* Internal Freq, in MHz */
+	unsigned long	bi_busfreq;	/* Bus Freq, in MHz */
+#if defined(CONFIG_CPM2)
+	unsigned long	bi_cpmfreq;	/* CPM_CLK Freq, in MHz */
+	unsigned long	bi_brgfreq;	/* BRG_CLK Freq, in MHz */
+	unsigned long	bi_sccfreq;	/* SCC_CLK Freq, in MHz */
+	unsigned long	bi_vco;		/* VCO Out from PLL, in MHz */
+#endif
+#if defined(CONFIG_MPC512X)
+	unsigned long	bi_ipsfreq;	/* IPS Bus Freq, in MHz */
+#endif /* CONFIG_MPC512X */
+#if defined(CONFIG_MPC5xxx)
+	unsigned long	bi_ipbfreq;	/* IPB Bus Freq, in MHz */
+	unsigned long	bi_pcifreq;	/* PCI Bus Freq, in MHz */
+#endif
+#if defined(CONFIG_405)   || \
+		defined(CONFIG_405GP) || \
+		defined(CONFIG_405EP) || \
+		defined(CONFIG_405EZ) || \
+		defined(CONFIG_405EX) || \
+		defined(CONFIG_440)
+	unsigned char	bi_s_version[4];	/* Version of this structure */
+	unsigned char	bi_r_version[32];	/* Version of the ROM (AMCC) */
+	unsigned int	bi_procfreq;	/* CPU (Internal) Freq, in Hz */
+	unsigned int	bi_plb_busfreq;	/* PLB Bus speed, in Hz */
+	unsigned int	bi_pci_busfreq;	/* PCI Bus speed, in Hz */
+	unsigned char	bi_pci_enetaddr[6];	/* PCI Ethernet MAC address */
+#endif
+#if defined(CONFIG_HYMOD)
+	hymod_conf_t	bi_hymod_conf;	/* hymod configuration information */
+#endif
+
+#ifdef CONFIG_HAS_ETH1
+	unsigned char   bi_enet1addr[6];	/* OLD: see README.enetaddr */
+#endif
+#ifdef CONFIG_HAS_ETH2
+	unsigned char	bi_enet2addr[6];	/* OLD: see README.enetaddr */
+#endif
+#ifdef CONFIG_HAS_ETH3
+	unsigned char   bi_enet3addr[6];	/* OLD: see README.enetaddr */
+#endif
+#ifdef CONFIG_HAS_ETH4
+	unsigned char   bi_enet4addr[6];	/* OLD: see README.enetaddr */
+#endif
+#ifdef CONFIG_HAS_ETH5
+	unsigned char   bi_enet5addr[6];	/* OLD: see README.enetaddr */
+#endif
+
+#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
+		defined(CONFIG_405EZ) || defined(CONFIG_440GX) || \
+		defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+		defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+		defined(CONFIG_460EX) || defined(CONFIG_460GT)
+	unsigned int	bi_opbfreq;		/* OPB clock in Hz */
+	int		bi_iic_fast[2];		/* Use fast i2c mode */
+#endif
+#if defined(CONFIG_4xx)
+#if defined(CONFIG_440GX) || \
+		defined(CONFIG_460EX) || defined(CONFIG_460GT)
+	int		bi_phynum[4];           /* Determines phy mapping */
+	int		bi_phymode[4];          /* Determines phy mode */
+#elif defined(CONFIG_405EP) || defined(CONFIG_405EX) || defined(CONFIG_440)
+	int		bi_phynum[2];           /* Determines phy mapping */
+	int		bi_phymode[2];          /* Determines phy mode */
+#else
+	int		bi_phynum[1];           /* Determines phy mapping */
+	int		bi_phymode[1];          /* Determines phy mode */
+#endif
+#endif /* defined(CONFIG_4xx) */
+	ulong	        bi_arch_number;	/* unique id for this board */
+	ulong	        bi_boot_params;	/* where this board expects params */
+#ifdef CONFIG_NR_DRAM_BANKS
+	struct {			/* RAM configuration */
+		ulong start;
+		ulong size;
+	} bi_dram[CONFIG_NR_DRAM_BANKS];
+#endif /* CONFIG_NR_DRAM_BANKS */
+} bd_t;
+
+#endif /* __ASSEMBLY__ */
+
+#endif	/* __ASM_GENERIC_U_BOOT_H__ */
diff --git a/qemu/roms/u-boot/include/asm-generic/unaligned.h b/qemu/roms/u-boot/include/asm-generic/unaligned.h
new file mode 100644
index 000000000..fd0255099
--- /dev/null
+++ b/qemu/roms/u-boot/include/asm-generic/unaligned.h
@@ -0,0 +1,23 @@
+#ifndef _GENERIC_UNALIGNED_H
+#define _GENERIC_UNALIGNED_H
+
+#include <asm/byteorder.h>
+
+#include <linux/unaligned/le_byteshift.h>
+#include <linux/unaligned/be_byteshift.h>
+#include <linux/unaligned/generic.h>
+
+/*
+ * Select endianness
+ */
+#if defined(__LITTLE_ENDIAN)
+#define get_unaligned	__get_unaligned_le
+#define put_unaligned	__put_unaligned_le
+#elif defined(__BIG_ENDIAN)
+#define get_unaligned	__get_unaligned_be
+#define put_unaligned	__put_unaligned_be
+#else
+#error invalid endian
+#endif
+
+#endif
diff --git a/qemu/roms/u-boot/include/asm-offsets.h b/qemu/roms/u-boot/include/asm-offsets.h
new file mode 100644
index 000000000..ad3bf1f0b
--- /dev/null
+++ b/qemu/roms/u-boot/include/asm-offsets.h
@@ -0,0 +1,6 @@
+#ifndef	DO_DEPS_ONLY
+
+#include <generated/generic-asm-offsets.h>
+/* #include <generated/asm-offsets.h> */
+
+#endif
diff --git a/qemu/roms/u-boot/include/ata.h b/qemu/roms/u-boot/include/ata.h
new file mode 100644
index 000000000..9d6f59c97
--- /dev/null
+++ b/qemu/roms/u-boot/include/ata.h
@@ -0,0 +1,251 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Most of the following information was derived from the document
+ * "Information Technology - AT Attachment-3 Interface (ATA-3)"
+ * which can be found at:
+ * http://www.dt.wdc.com/ata/ata-3/ata3r5v.zip
+ * ftp://poctok.iae.nsk.su/pub/asm/Documents/IDE/ATA3R5V.ZIP
+ * ftp://ftp.fee.vutbr.cz/pub/doc/io/ata/ata-3/ata3r5v.zip
+ */
+
+#ifndef	_ATA_H
+#define _ATA_H
+
+#include <libata.h>
+
+/* Register addressing depends on the hardware design; for instance,
+ * 8-bit (register) and 16-bit (data) accesses might use different
+ * address spaces. This is implemented by the following definitions.
+ */
+#ifndef CONFIG_SYS_ATA_STRIDE
+#define CONFIG_SYS_ATA_STRIDE	1
+#endif
+
+#define ATA_IO_DATA(x)	(CONFIG_SYS_ATA_DATA_OFFSET+((x) * CONFIG_SYS_ATA_STRIDE))
+#define ATA_IO_REG(x)	(CONFIG_SYS_ATA_REG_OFFSET +((x) * CONFIG_SYS_ATA_STRIDE))
+#define ATA_IO_ALT(x)	(CONFIG_SYS_ATA_ALT_OFFSET +((x) * CONFIG_SYS_ATA_STRIDE))
+
+/*
+ * I/O Register Descriptions
+ */
+#define ATA_DATA_REG	ATA_IO_DATA(0)
+#define ATA_ERROR_REG	ATA_IO_REG(1)
+#define ATA_SECT_CNT	ATA_IO_REG(2)
+#define ATA_SECT_NUM	ATA_IO_REG(3)
+#define ATA_CYL_LOW	ATA_IO_REG(4)
+#define ATA_CYL_HIGH	ATA_IO_REG(5)
+#define ATA_DEV_HD	ATA_IO_REG(6)
+#define ATA_COMMAND	ATA_IO_REG(7)
+#define ATA_DATA_EVEN	ATA_IO_REG(8)
+#define ATA_DATA_ODD	ATA_IO_REG(9)
+#define ATA_STATUS	ATA_COMMAND
+#define ATA_DEV_CTL	ATA_IO_ALT(6)
+#define ATA_LBA_LOW	ATA_SECT_NUM
+#define ATA_LBA_MID	ATA_CYL_LOW
+#define ATA_LBA_HIGH	ATA_CYL_HIGH
+#define ATA_LBA_SEL	ATA_DEV_CTL
+
+/*
+ * Status register bits
+ */
+#define ATA_STAT_BUSY	0x80	/* Device Busy			*/
+#define ATA_STAT_READY	0x40	/* Device Ready			*/
+#define ATA_STAT_FAULT	0x20	/* Device Fault			*/
+#define ATA_STAT_SEEK	0x10	/* Device Seek Complete		*/
+#define ATA_STAT_DRQ	0x08	/* Data Request (ready)		*/
+#define ATA_STAT_CORR	0x04	/* Corrected Data Error		*/
+#define ATA_STAT_INDEX	0x02	/* Vendor specific		*/
+#define ATA_STAT_ERR	0x01	/* Error			*/
+
+/*
+ * Device / Head Register Bits
+ */
+#ifndef ATA_DEVICE
+#define ATA_DEVICE(x)	((x & 1)<<4)
+#endif /* ATA_DEVICE */
+#define ATA_LBA		0xE0
+
+/*
+ * ATA Commands (only mandatory commands listed here)
+ */
+#define ATA_CMD_READ	0x20	/* Read Sectors (with retries)	*/
+#define ATA_CMD_READN	0x21	/* Read Sectors ( no  retries)	*/
+#define ATA_CMD_WRITE	0x30	/* Write Sectores (with retries)*/
+#define ATA_CMD_WRITEN	0x31	/* Write Sectors  ( no  retries)*/
+#define ATA_CMD_VRFY	0x40	/* Read Verify  (with retries)	*/
+#define ATA_CMD_VRFYN	0x41	/* Read verify  ( no  retries)	*/
+#define ATA_CMD_SEEK	0x70	/* Seek				*/
+#define ATA_CMD_DIAG	0x90	/* Execute Device Diagnostic	*/
+#define ATA_CMD_INIT	0x91	/* Initialize Device Parameters	*/
+#define ATA_CMD_RD_MULT	0xC4	/* Read Multiple		*/
+#define ATA_CMD_WR_MULT	0xC5	/* Write Multiple		*/
+#define ATA_CMD_SETMULT	0xC6	/* Set Multiple Mode		*/
+#define ATA_CMD_RD_DMA	0xC8	/* Read DMA (with retries)	*/
+#define ATA_CMD_RD_DMAN	0xC9	/* Read DMS ( no  retries)	*/
+#define ATA_CMD_WR_DMA	0xCA	/* Write DMA (with retries)	*/
+#define ATA_CMD_WR_DMAN	0xCB	/* Write DMA ( no  retires)	*/
+#define ATA_CMD_IDENT	0xEC	/* Identify Device		*/
+#define ATA_CMD_SETF	0xEF	/* Set Features			*/
+#define ATA_CMD_CHK_PWR	0xE5	/* Check Power Mode		*/
+
+#define ATA_CMD_READ_EXT 0x24	/* Read Sectors (with retries)	with 48bit addressing */
+#define ATA_CMD_WRITE_EXT	0x34	/* Write Sectores (with retries) with 48bit addressing */
+#define ATA_CMD_VRFY_EXT	0x42	/* Read Verify	(with retries)	with 48bit addressing */
+
+#define ATA_CMD_FLUSH 0xE7 /* Flush drive cache */
+#define ATA_CMD_FLUSH_EXT 0xEA /* Flush drive cache, with 48bit addressing */
+
+/*
+ * ATAPI Commands
+ */
+#define ATAPI_CMD_IDENT 0xA1 /* Identify AT Atachment Packed Interface Device */
+#define ATAPI_CMD_PACKET 0xA0 /* Packed Command */
+
+
+#define ATAPI_CMD_INQUIRY 0x12
+#define ATAPI_CMD_REQ_SENSE 0x03
+#define ATAPI_CMD_READ_CAP 0x25
+#define ATAPI_CMD_START_STOP 0x1B
+#define ATAPI_CMD_READ_12 0xA8
+
+
+#define ATA_GET_ERR()	inb(ATA_STATUS)
+#define ATA_GET_STAT()	inb(ATA_STATUS)
+#define ATA_OK_STAT(stat,good,bad)	(((stat)&((good)|(bad)))==(good))
+#define ATA_BAD_R_STAT	(ATA_STAT_BUSY	| ATA_STAT_ERR)
+#define ATA_BAD_W_STAT	(ATA_BAD_R_STAT	| ATA_STAT_FAULT)
+#define ATA_BAD_STAT	(ATA_BAD_R_STAT	| ATA_STAT_DRQ)
+#define ATA_DRIVE_READY	(ATA_READY_STAT	| ATA_STAT_SEEK)
+#define ATA_DATA_READY	(ATA_STAT_DRQ)
+
+#define ATA_BLOCKSIZE	512	/* bytes */
+#define ATA_BLOCKSHIFT	9	/* 2 ^ ATA_BLOCKSIZESHIFT = 512 */
+#define ATA_SECTORWORDS	(512 / sizeof(unsigned long))
+
+#ifndef ATA_RESET_TIME
+#define ATA_RESET_TIME	60	/* spec allows up to 31 seconds */
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * structure returned by ATA_CMD_IDENT, as per ANSI ATA2 rev.2f spec
+ */
+typedef struct hd_driveid {
+	unsigned short	config;		/* lots of obsolete bit flags */
+	unsigned short	cyls;		/* "physical" cyls */
+	unsigned short	reserved2;	/* reserved (word 2) */
+	unsigned short	heads;		/* "physical" heads */
+	unsigned short	track_bytes;	/* unformatted bytes per track */
+	unsigned short	sector_bytes;	/* unformatted bytes per sector */
+	unsigned short	sectors;	/* "physical" sectors per track */
+	unsigned short	vendor0;	/* vendor unique */
+	unsigned short	vendor1;	/* vendor unique */
+	unsigned short	vendor2;	/* vendor unique */
+	unsigned char	serial_no[20];	/* 0 = not_specified */
+	unsigned short	buf_type;
+	unsigned short	buf_size;	/* 512 byte increments; 0 = not_specified */
+	unsigned short	ecc_bytes;	/* for r/w long cmds; 0 = not_specified */
+	unsigned char	fw_rev[8];	/* 0 = not_specified */
+	unsigned char	model[40];	/* 0 = not_specified */
+	unsigned char	max_multsect;	/* 0=not_implemented */
+	unsigned char	vendor3;	/* vendor unique */
+	unsigned short	dword_io;	/* 0=not_implemented; 1=implemented */
+	unsigned char	vendor4;	/* vendor unique */
+	unsigned char	capability;	/* bits 0:DMA 1:LBA 2:IORDYsw 3:IORDYsup*/
+	unsigned short	reserved50;	/* reserved (word 50) */
+	unsigned char	vendor5;	/* vendor unique */
+	unsigned char	tPIO;		/* 0=slow, 1=medium, 2=fast */
+	unsigned char	vendor6;	/* vendor unique */
+	unsigned char	tDMA;		/* 0=slow, 1=medium, 2=fast */
+	unsigned short	field_valid;	/* bits 0:cur_ok 1:eide_ok */
+	unsigned short	cur_cyls;	/* logical cylinders */
+	unsigned short	cur_heads;	/* logical heads */
+	unsigned short	cur_sectors;	/* logical sectors per track */
+	unsigned short	cur_capacity0;	/* logical total sectors on drive */
+	unsigned short	cur_capacity1;	/*  (2 words, misaligned int)     */
+	unsigned char	multsect;	/* current multiple sector count */
+	unsigned char	multsect_valid;	/* when (bit0==1) multsect is ok */
+	unsigned int	lba_capacity;	/* total number of sectors */
+	unsigned short	dma_1word;	/* single-word dma info */
+	unsigned short	dma_mword;	/* multiple-word dma info */
+	unsigned short  eide_pio_modes; /* bits 0:mode3 1:mode4 */
+	unsigned short  eide_dma_min;	/* min mword dma cycle time (ns) */
+	unsigned short  eide_dma_time;	/* recommended mword dma cycle time (ns) */
+	unsigned short  eide_pio;       /* min cycle time (ns), no IORDY  */
+	unsigned short  eide_pio_iordy; /* min cycle time (ns), with IORDY */
+	unsigned short	words69_70[2];	/* reserved words 69-70 */
+	unsigned short	words71_74[4];	/* reserved words 71-74 */
+	unsigned short  queue_depth;	/*  */
+	unsigned short  words76_79[4];	/* reserved words 76-79 */
+	unsigned short  major_rev_num;	/*  */
+	unsigned short  minor_rev_num;	/*  */
+	unsigned short  command_set_1;	/* bits 0:Smart 1:Security 2:Removable 3:PM */
+	unsigned short	command_set_2;	/* bits 14:Smart Enabled 13:0 zero 10:lba48 support*/
+	unsigned short  cfsse;		/* command set-feature supported extensions */
+	unsigned short  cfs_enable_1;	/* command set-feature enabled */
+	unsigned short  cfs_enable_2;	/* command set-feature enabled */
+	unsigned short  csf_default;	/* command set-feature default */
+	unsigned short  dma_ultra;	/*  */
+	unsigned short	word89;		/* reserved (word 89) */
+	unsigned short	word90;		/* reserved (word 90) */
+	unsigned short	CurAPMvalues;	/* current APM values */
+	unsigned short	word92;		/* reserved (word 92) */
+	unsigned short	hw_config;	/* hardware config */
+	unsigned short	words94_99[6];/* reserved words 94-99 */
+	/*unsigned long long  lba48_capacity; /--* 4 16bit values containing lba 48 total number of sectors */
+	unsigned short	lba48_capacity[4]; /* 4 16bit values containing lba 48 total number of sectors */
+	unsigned short	words104_125[22];/* reserved words 104-125 */
+	unsigned short	last_lun;	/* reserved (word 126) */
+	unsigned short	word127;	/* reserved (word 127) */
+	unsigned short	dlf;		/* device lock function
+					 * 15:9	reserved
+					 * 8	security level 1:max 0:high
+					 * 7:6	reserved
+					 * 5	enhanced erase
+					 * 4	expire
+					 * 3	frozen
+					 * 2	locked
+					 * 1	en/disabled
+					 * 0	capability
+					 */
+	unsigned short  csfo;		/* current set features options
+					 * 15:4	reserved
+					 * 3	auto reassign
+					 * 2	reverting
+					 * 1	read-look-ahead
+					 * 0	write cache
+					 */
+	unsigned short	words130_155[26];/* reserved vendor words 130-155 */
+	unsigned short	word156;
+	unsigned short	words157_159[3];/* reserved vendor words 157-159 */
+	unsigned short	words160_162[3];/* reserved words 160-162 */
+	unsigned short	cf_advanced_caps;
+	unsigned short	words164_255[92];/* reserved words 164-255 */
+} hd_driveid_t;
+
+
+/*
+ * PIO Mode Configuration
+ *
+ * See ATA-3 (AT Attachment-3 Interface) documentation, Figure 14 / Table 21
+ */
+
+typedef struct {
+	unsigned int	t_setup;	/* Setup  Time in [ns] or clocks	*/
+	unsigned int	t_length;	/* Length Time in [ns] or clocks	*/
+	unsigned int	t_hold;		/* Hold   Time in [ns] or clocks	*/
+}
+pio_config_t;
+
+#define	IDE_MAX_PIO_MODE	4	/* max suppurted PIO mode		*/
+
+/* ------------------------------------------------------------------------- */
+
+#endif /* _ATA_H */
diff --git a/qemu/roms/u-boot/include/atmel_hlcdc.h b/qemu/roms/u-boot/include/atmel_hlcdc.h
new file mode 100644
index 000000000..a9ba3ef2d
--- /dev/null
+++ b/qemu/roms/u-boot/include/atmel_hlcdc.h
@@ -0,0 +1,226 @@
+/*
+ *  Header file for AT91/AT32 MULTI LAYER LCD Controller
+ *
+ *  Data structure and register user interface
+ *
+ *  Copyright (C) 2012 Atmel Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __ATMEL_HLCDC_H__
+#define __ATMEL_HLCDC_H__
+
+/* Atmel multi layer lcdc hardware registers */
+struct atmel_hlcd_regs {
+	u32	lcdc_lcdcfg0;
+	u32	lcdc_lcdcfg1;
+	u32	lcdc_lcdcfg2;
+	u32	lcdc_lcdcfg3;
+	u32	lcdc_lcdcfg4;
+	u32	lcdc_lcdcfg5;
+	u32	lcdc_lcdcfg6;
+	u32	res1;
+	u32	lcdc_lcden;
+	u32	lcdc_lcddis;
+	u32	lcdc_lcdsr;
+	u32	res2;
+	u32	lcdc_lcdidr;
+	u32	res3[3];
+	u32	lcdc_basecher;
+	u32	res4[3];
+	u32	lcdc_baseidr;
+	u32	res5[3];
+	u32	lcdc_baseaddr;
+	u32	lcdc_basectrl;
+	u32	lcdc_basenext;
+	u32	lcdc_basecfg0;
+	u32	lcdc_basecfg1;
+	u32	lcdc_basecfg2;
+	u32	lcdc_basecfg3;
+	u32	lcdc_basecfg4;
+};
+
+#define LCDC_LCDCFG0_CLKPOL	(0x1 << 0)
+#define LCDC_LCDCFG0_CLKSEL	(0x1 << 2)
+#define LCDC_LCDCFG0_CLKPWMSEL	(0x1 << 3)
+#define LCDC_LCDCFG0_CGDISBASE	(0x1 << 8)
+#define LCDC_LCDCFG0_CGDISOVR1	(0x1 << 9)
+#define LCDC_LCDCFG0_CGDISHEO	(0x1 << 11)
+#define LCDC_LCDCFG0_CGDISHCR	(0x1 << 12)
+#define LCDC_LCDCFG0_CLKDIV_Pos	16
+#define LCDC_LCDCFG0_CLKDIV_Msk	(0xff << LCDC_LCDCFG0_CLKDIV_Pos)
+#define LCDC_LCDCFG0_CLKDIV(value) \
+	((LCDC_LCDCFG0_CLKDIV_Msk & ((value) << LCDC_LCDCFG0_CLKDIV_Pos)))
+
+#define LCDC_LCDCFG1_HSPW_Pos	0
+#define LCDC_LCDCFG1_HSPW_Msk	(0x3f << LCDC_LCDCFG1_HSPW_Pos)
+#define LCDC_LCDCFG1_HSPW(value) \
+	((LCDC_LCDCFG1_HSPW_Msk & ((value) << LCDC_LCDCFG1_HSPW_Pos)))
+#define LCDC_LCDCFG1_VSPW_Pos	16
+#define LCDC_LCDCFG1_VSPW_Msk	(0x3f << LCDC_LCDCFG1_VSPW_Pos)
+#define LCDC_LCDCFG1_VSPW(value) \
+	((LCDC_LCDCFG1_VSPW_Msk & ((value) << LCDC_LCDCFG1_VSPW_Pos)))
+
+#define LCDC_LCDCFG2_VFPW_Pos	0
+#define LCDC_LCDCFG2_VFPW_Msk	(0x3f << LCDC_LCDCFG2_VFPW_Pos)
+#define LCDC_LCDCFG2_VFPW(value) \
+	((LCDC_LCDCFG2_VFPW_Msk & ((value) << LCDC_LCDCFG2_VFPW_Pos)))
+#define LCDC_LCDCFG2_VBPW_Pos	16
+#define LCDC_LCDCFG2_VBPW_Msk	(0x3f << LCDC_LCDCFG2_VBPW_Pos)
+#define LCDC_LCDCFG2_VBPW(value) \
+	((LCDC_LCDCFG2_VBPW_Msk & ((value) << LCDC_LCDCFG2_VBPW_Pos)))
+
+#define LCDC_LCDCFG3_HFPW_Pos	0
+#define LCDC_LCDCFG3_HFPW_Msk	(0xff << LCDC_LCDCFG3_HFPW_Pos)
+#define LCDC_LCDCFG3_HFPW(value) \
+	((LCDC_LCDCFG3_HFPW_Msk & ((value) << LCDC_LCDCFG3_HFPW_Pos)))
+#define LCDC_LCDCFG3_HBPW_Pos	16
+#define LCDC_LCDCFG3_HBPW_Msk	(0xff << LCDC_LCDCFG3_HBPW_Pos)
+#define LCDC_LCDCFG3_HBPW(value) \
+	((LCDC_LCDCFG3_HBPW_Msk & ((value) << LCDC_LCDCFG3_HBPW_Pos)))
+
+#define LCDC_LCDCFG4_PPL_Pos	0
+#define LCDC_LCDCFG4_PPL_Msk	(0x7ff << LCDC_LCDCFG4_PPL_Pos)
+#define LCDC_LCDCFG4_PPL(value) \
+	((LCDC_LCDCFG4_PPL_Msk & ((value) << LCDC_LCDCFG4_PPL_Pos)))
+#define LCDC_LCDCFG4_RPF_Pos	16
+#define LCDC_LCDCFG4_RPF_Msk	(0x7ff << LCDC_LCDCFG4_RPF_Pos)
+#define LCDC_LCDCFG4_RPF(value) \
+	((LCDC_LCDCFG4_RPF_Msk & ((value) << LCDC_LCDCFG4_RPF_Pos)))
+
+#define LCDC_LCDCFG5_HSPOL	(0x1 << 0)
+#define LCDC_LCDCFG5_VSPOL	(0x1 << 1)
+#define LCDC_LCDCFG5_VSPDLYS	(0x1 << 2)
+#define LCDC_LCDCFG5_VSPDLYE	(0x1 << 3)
+#define LCDC_LCDCFG5_DISPPOL	(0x1 << 4)
+#define LCDC_LCDCFG5_SERIAL	(0x1 << 5)
+#define LCDC_LCDCFG5_DITHER	(0x1 << 6)
+#define LCDC_LCDCFG5_DISPDLY	(0x1 << 7)
+#define LCDC_LCDCFG5_MODE_Pos	8
+#define LCDC_LCDCFG5_MODE_Msk	(0x3 << LCDC_LCDCFG5_MODE_Pos)
+#define LCDC_LCDCFG5_MODE_OUTPUT_12BPP	(0x0 << 8)
+#define LCDC_LCDCFG5_MODE_OUTPUT_16BPP	(0x1 << 8)
+#define LCDC_LCDCFG5_MODE_OUTPUT_18BPP	(0x2 << 8)
+#define LCDC_LCDCFG5_MODE_OUTPUT_24BPP	(0x3 << 8)
+#define LCDC_LCDCFG5_VSPSU		(0x1 << 12)
+#define LCDC_LCDCFG5_VSPHO		(0x1 << 13)
+#define LCDC_LCDCFG5_GUARDTIME_Pos	16
+#define LCDC_LCDCFG5_GUARDTIME_Msk	(0x1f << LCDC_LCDCFG5_GUARDTIME_Pos)
+#define LCDC_LCDCFG5_GUARDTIME(value) \
+	((LCDC_LCDCFG5_GUARDTIME_Msk & ((value) << LCDC_LCDCFG5_GUARDTIME_Pos)))
+
+#define LCDC_LCDCFG6_PWMPS_Pos		0
+#define LCDC_LCDCFG6_PWMPS_Msk		(0x7 << LCDC_LCDCFG6_PWMPS_Pos)
+#define LCDC_LCDCFG6_PWMPS(value) \
+	((LCDC_LCDCFG6_PWMPS_Msk & ((value) << LCDC_LCDCFG6_PWMPS_Pos)))
+#define LCDC_LCDCFG6_PWMPOL		(0x1 << 4)
+#define LCDC_LCDCFG6_PWMCVAL_Pos	8
+#define LCDC_LCDCFG6_PWMCVAL_Msk	(0xff << LCDC_LCDCFG6_PWMCVAL_Pos)
+#define LCDC_LCDCFG6_PWMCVAL(value) \
+	((LCDC_LCDCFG6_PWMCVAL_Msk & ((value) << LCDC_LCDCFG6_PWMCVAL_Pos)))
+
+#define LCDC_LCDEN_CLKEN	(0x1 << 0)
+#define LCDC_LCDEN_SYNCEN	(0x1 << 1)
+#define LCDC_LCDEN_DISPEN	(0x1 << 2)
+#define LCDC_LCDEN_PWMEN	(0x1 << 3)
+
+#define LCDC_LCDDIS_CLKDIS	(0x1 << 0)
+#define LCDC_LCDDIS_SYNCDIS	(0x1 << 1)
+#define LCDC_LCDDIS_DISPDIS	(0x1 << 2)
+#define LCDC_LCDDIS_PWMDIS	(0x1 << 3)
+#define LCDC_LCDDIS_CLKRST	(0x1 << 8)
+#define LCDC_LCDDIS_SYNCRST	(0x1 << 9)
+#define LCDC_LCDDIS_DISPRST	(0x1 << 10)
+#define LCDC_LCDDIS_PWMRST	(0x1 << 11)
+
+#define LCDC_LCDSR_CLKSTS	(0x1 << 0)
+#define LCDC_LCDSR_LCDSTS	(0x1 << 1)
+#define LCDC_LCDSR_DISPSTS	(0x1 << 2)
+#define LCDC_LCDSR_PWMSTS	(0x1 << 3)
+#define LCDC_LCDSR_SIPSTS	(0x1 << 4)
+
+#define LCDC_LCDIDR_SOFID	(0x1 << 0)
+#define LCDC_LCDIDR_DISID	(0x1 << 1)
+#define LCDC_LCDIDR_DISPID	(0x1 << 2)
+#define LCDC_LCDIDR_FIFOERRID	(0x1 << 4)
+#define LCDC_LCDIDR_BASEID	(0x1 << 8)
+#define LCDC_LCDIDR_OVR1ID	(0x1 << 9)
+#define LCDC_LCDIDR_HEOID	(0x1 << 11)
+#define LCDC_LCDIDR_HCRID	(0x1 << 12)
+
+#define LCDC_BASECHER_CHEN	(0x1 << 0)
+#define LCDC_BASECHER_UPDATEEN	(0x1 << 1)
+#define LCDC_BASECHER_A2QEN	(0x1 << 2)
+
+#define LCDC_BASEIDR_DMA	(0x1 << 2)
+#define LCDC_BASEIDR_DSCR	(0x1 << 3)
+#define LCDC_BASEIDR_ADD	(0x1 << 4)
+#define LCDC_BASEIDR_DONE	(0x1 << 5)
+#define LCDC_BASEIDR_OVR	(0x1 << 6)
+
+#define LCDC_BASECTRL_DFETCH	(0x1 << 0)
+#define LCDC_BASECTRL_LFETCH	(0x1 << 1)
+#define LCDC_BASECTRL_DMAIEN	(0x1 << 2)
+#define LCDC_BASECTRL_DSCRIEN	(0x1 << 3)
+#define LCDC_BASECTRL_ADDIEN	(0x1 << 4)
+#define LCDC_BASECTRL_DONEIEN	(0x1 << 5)
+
+#define LCDC_BASECFG0_BLEN_Pos		4
+#define LCDC_BASECFG0_BLEN_AHB_SINGLE	(0x0 << 4)
+#define LCDC_BASECFG0_BLEN_AHB_INCR4	(0x1 << 4)
+#define LCDC_BASECFG0_BLEN_AHB_INCR8	(0x2 << 4)
+#define LCDC_BASECFG0_BLEN_AHB_INCR16	(0x3 << 4)
+#define LCDC_BASECFG0_DLBO		(0x1 << 8)
+
+#define LCDC_BASECFG1_RGBMODE_12BPP_RGB_444		(0x0 << 4)
+#define LCDC_BASECFG1_RGBMODE_16BPP_ARGB_4444		(0x1 << 4)
+#define LCDC_BASECFG1_RGBMODE_16BPP_RGBA_4444		(0x2 << 4)
+#define LCDC_BASECFG1_RGBMODE_16BPP_RGB_565		(0x3 << 4)
+#define LCDC_BASECFG1_RGBMODE_16BPP_TRGB_1555		(0x4 << 4)
+#define LCDC_BASECFG1_RGBMODE_18BPP_RGB_666		(0x5 << 4)
+#define LCDC_BASECFG1_RGBMODE_18BPP_RGB_666_PACKED	(0x6 << 4)
+#define LCDC_BASECFG1_RGBMODE_19BPP_TRGB_1666		(0x7 << 4)
+#define LCDC_BASECFG1_RGBMODE_19BPP_TRGB_PACKED		(0x8 << 4)
+#define LCDC_BASECFG1_RGBMODE_24BPP_RGB_888		(0x9 << 4)
+#define LCDC_BASECFG1_RGBMODE_24BPP_RGB_888_PACKED	(0xA << 4)
+#define LCDC_BASECFG1_RGBMODE_25BPP_TRGB_1888		(0xB << 4)
+#define LCDC_BASECFG1_RGBMODE_32BPP_ARGB_8888		(0xC << 4)
+#define LCDC_BASECFG1_RGBMODE_32BPP_RGBA_8888		(0xD << 4)
+
+#define LCDC_BASECFG2_XSTRIDE_Pos 0
+#define LCDC_BASECFG2_XSTRIDE_Msk (0xffffffff << LCDC_BASECFG2_XSTRIDE_Pos)
+#define LCDC_BASECFG2_XSTRIDE(value) \
+	((LCDC_BASECFG2_XSTRIDE_Msk & ((value) << LCDC_BASECFG2_XSTRIDE_Pos)))
+
+#define LCDC_BASECFG3_BDEF_Pos	0
+#define LCDC_BASECFG3_BDEF_Msk	(0xff << LCDC_BASECFG3_BDEF_Pos)
+#define LCDC_BASECFG3_BDEF(value) \
+	((LCDC_BASECFG3_BDEF_Msk & ((value) << LCDC_BASECFG3_BDEF_Pos)))
+#define LCDC_BASECFG3_GDEF_Pos	8
+#define LCDC_BASECFG3_GDEF_Msk	(0xff << LCDC_BASECFG3_GDEF_Pos)
+#define LCDC_BASECFG3_GDEF(value) \
+	((LCDC_BASECFG3_GDEF_Msk & ((value) << LCDC_BASECFG3_GDEF_Pos)))
+#define LCDC_BASECFG3_RDEF_Pos	16
+#define LCDC_BASECFG3_RDEF_Msk	(0xff << LCDC_BASECFG3_RDEF_Pos)
+#define LCDC_BASECFG3_RDEF(value) \
+	((LCDC_BASECFG3_RDEF_Msk & ((value) << LCDC_BASECFG3_RDEF_Pos)))
+
+#define LCDC_BASECLUT_BCLUT_Pos 0
+#define LCDC_BASECLUT_BCLUT_Msk (0xff << LCDC_BASECLUT_BCLUT_Pos)
+#define LCDC_BASECLUT_GCLUT_Pos 8
+#define LCDC_BASECLUT_GCLUT_Msk (0xff << LCDC_BASECLUT_GCLUT_Pos)
+#define LCDC_BASECLUT_RCLUT_Pos 16
+#define LCDC_BASECLUT_RCLUT_Msk (0xff << LCDC_BASECLUT_RCLUT_Pos)
+
+#define LCDC_BASECFG4_DMA	(0x1 << 8)
+#define LCDC_BASECFG4_REP	(0x1 << 9)
+
+struct lcd_dma_desc {
+	u32	address;
+	u32	control;
+	u32	next;
+};
+
+#define ATMEL_LCDC_LUT(n)	(0x0400 + ((n)*4))
+
+#endif /* __ATMEL_HLCDC_H__ */
diff --git a/qemu/roms/u-boot/include/atmel_lcdc.h b/qemu/roms/u-boot/include/atmel_lcdc.h
new file mode 100644
index 000000000..ba62180f5
--- /dev/null
+++ b/qemu/roms/u-boot/include/atmel_lcdc.h
@@ -0,0 +1,165 @@
+/*
+ *  Header file for AT91/AT32 LCD Controller
+ *
+ *  Data structure and register user interface
+ *
+ *  Copyright (C) 2007 Atmel Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __ATMEL_LCDC_H__
+#define __ATMEL_LCDC_H__
+
+#define ATMEL_LCDC_DMABADDR1	0x00
+#define ATMEL_LCDC_DMABADDR2	0x04
+#define ATMEL_LCDC_DMAFRMPT1	0x08
+#define ATMEL_LCDC_DMAFRMPT2	0x0c
+#define ATMEL_LCDC_DMAFRMADD1	0x10
+#define ATMEL_LCDC_DMAFRMADD2	0x14
+
+#define ATMEL_LCDC_DMAFRMCFG	0x18
+#define	ATMEL_LCDC_FRSIZE	(0x7fffff <<  0)
+#define	ATMEL_LCDC_BLENGTH_OFFSET	24
+#define	ATMEL_LCDC_BLENGTH	(0x7f     << ATMEL_LCDC_BLENGTH_OFFSET)
+
+#define ATMEL_LCDC_DMACON	0x1c
+#define	ATMEL_LCDC_DMAEN	(0x1 << 0)
+#define	ATMEL_LCDC_DMARST	(0x1 << 1)
+#define	ATMEL_LCDC_DMABUSY	(0x1 << 2)
+#define		ATMEL_LCDC_DMAUPDT	(0x1 << 3)
+#define		ATMEL_LCDC_DMA2DEN	(0x1 << 4)
+
+#define ATMEL_LCDC_DMA2DCFG	0x20
+#define		ATMEL_LCDC_ADDRINC_OFFSET	0
+#define		ATMEL_LCDC_ADDRINC		(0xffff)
+#define		ATMEL_LCDC_PIXELOFF_OFFSET	24
+#define		ATMEL_LCDC_PIXELOFF		(0x1f << 24)
+
+#define ATMEL_LCDC_LCDCON1	0x0800
+#define	ATMEL_LCDC_BYPASS	(1     <<  0)
+#define	ATMEL_LCDC_CLKVAL_OFFSET	12
+#define	ATMEL_LCDC_CLKVAL	(0x1ff << ATMEL_LCDC_CLKVAL_OFFSET)
+#define	ATMEL_LCDC_LINCNT	(0x7ff << 21)
+
+#define ATMEL_LCDC_LCDCON2	0x0804
+#define	ATMEL_LCDC_DISTYPE	(3 << 0)
+#define		ATMEL_LCDC_DISTYPE_STNMONO	(0 << 0)
+#define		ATMEL_LCDC_DISTYPE_STNCOLOR	(1 << 0)
+#define		ATMEL_LCDC_DISTYPE_TFT		(2 << 0)
+#define	ATMEL_LCDC_SCANMOD	(1 << 2)
+#define		ATMEL_LCDC_SCANMOD_SINGLE	(0 << 2)
+#define		ATMEL_LCDC_SCANMOD_DUAL		(1 << 2)
+#define	ATMEL_LCDC_IFWIDTH	(3 << 3)
+#define		ATMEL_LCDC_IFWIDTH_4		(0 << 3)
+#define		ATMEL_LCDC_IFWIDTH_8		(1 << 3)
+#define		ATMEL_LCDC_IFWIDTH_16		(2 << 3)
+#define	ATMEL_LCDC_PIXELSIZE	(7 << 5)
+#define		ATMEL_LCDC_PIXELSIZE_1		(0 << 5)
+#define		ATMEL_LCDC_PIXELSIZE_2		(1 << 5)
+#define		ATMEL_LCDC_PIXELSIZE_4		(2 << 5)
+#define		ATMEL_LCDC_PIXELSIZE_8		(3 << 5)
+#define		ATMEL_LCDC_PIXELSIZE_16		(4 << 5)
+#define		ATMEL_LCDC_PIXELSIZE_24		(5 << 5)
+#define		ATMEL_LCDC_PIXELSIZE_32		(6 << 5)
+#define	ATMEL_LCDC_INVVD	(1 << 8)
+#define		ATMEL_LCDC_INVVD_NORMAL		(0 << 8)
+#define		ATMEL_LCDC_INVVD_INVERTED	(1 << 8)
+#define	ATMEL_LCDC_INVFRAME	(1 << 9 )
+#define		ATMEL_LCDC_INVFRAME_NORMAL	(0 << 9)
+#define		ATMEL_LCDC_INVFRAME_INVERTED	(1 << 9)
+#define	ATMEL_LCDC_INVLINE	(1 << 10)
+#define		ATMEL_LCDC_INVLINE_NORMAL	(0 << 10)
+#define		ATMEL_LCDC_INVLINE_INVERTED	(1 << 10)
+#define	ATMEL_LCDC_INVCLK	(1 << 11)
+#define		ATMEL_LCDC_INVCLK_NORMAL	(0 << 11)
+#define		ATMEL_LCDC_INVCLK_INVERTED	(1 << 11)
+#define	ATMEL_LCDC_INVDVAL	(1 << 12)
+#define		ATMEL_LCDC_INVDVAL_NORMAL	(0 << 12)
+#define		ATMEL_LCDC_INVDVAL_INVERTED	(1 << 12)
+#define	ATMEL_LCDC_CLKMOD	(1 << 15)
+#define		ATMEL_LCDC_CLKMOD_ACTIVEDISPLAY	(0 << 15)
+#define		ATMEL_LCDC_CLKMOD_ALWAYSACTIVE	(1 << 15)
+#define	ATMEL_LCDC_MEMOR	(1 << 31)
+#define		ATMEL_LCDC_MEMOR_BIG		(0 << 31)
+#define		ATMEL_LCDC_MEMOR_LITTLE		(1 << 31)
+
+#define ATMEL_LCDC_TIM1		0x0808
+#define	ATMEL_LCDC_VFP		(0xffU <<  0)
+#define	ATMEL_LCDC_VBP_OFFSET		8
+#define	ATMEL_LCDC_VBP		(0xffU <<  ATMEL_LCDC_VBP_OFFSET)
+#define	ATMEL_LCDC_VPW_OFFSET		16
+#define	ATMEL_LCDC_VPW		(0x3fU << ATMEL_LCDC_VPW_OFFSET)
+#define	ATMEL_LCDC_VHDLY_OFFSET		24
+#define	ATMEL_LCDC_VHDLY	(0xfU  << ATMEL_LCDC_VHDLY_OFFSET)
+
+#define ATMEL_LCDC_TIM2		0x080c
+#define	ATMEL_LCDC_HBP		(0xffU  <<  0)
+#define	ATMEL_LCDC_HPW_OFFSET		8
+#define	ATMEL_LCDC_HPW		(0x3fU  <<  ATMEL_LCDC_HPW_OFFSET)
+#define	ATMEL_LCDC_HFP_OFFSET		21
+#define	ATMEL_LCDC_HFP		(0x7ffU << ATMEL_LCDC_HFP_OFFSET)
+
+#define ATMEL_LCDC_LCDFRMCFG	0x0810
+#define	ATMEL_LCDC_LINEVAL	(0x7ff <<  0)
+#define	ATMEL_LCDC_HOZVAL_OFFSET	21
+#define	ATMEL_LCDC_HOZVAL	(0x7ff << ATMEL_LCDC_HOZVAL_OFFSET)
+
+#define ATMEL_LCDC_FIFO		0x0814
+#define	ATMEL_LCDC_FIFOTH	(0xffff)
+
+#define ATMEL_LCDC_MVAL		0x0818
+
+#define ATMEL_LCDC_DP1_2	0x081c
+#define ATMEL_LCDC_DP4_7	0x0820
+#define ATMEL_LCDC_DP3_5	0x0824
+#define ATMEL_LCDC_DP2_3	0x0828
+#define ATMEL_LCDC_DP5_7	0x082c
+#define ATMEL_LCDC_DP3_4	0x0830
+#define ATMEL_LCDC_DP4_5	0x0834
+#define ATMEL_LCDC_DP6_7	0x0838
+#define	ATMEL_LCDC_DP1_2_VAL	(0xff)
+#define	ATMEL_LCDC_DP4_7_VAL	(0xfffffff)
+#define	ATMEL_LCDC_DP3_5_VAL	(0xfffff)
+#define	ATMEL_LCDC_DP2_3_VAL	(0xfff)
+#define	ATMEL_LCDC_DP5_7_VAL	(0xfffffff)
+#define	ATMEL_LCDC_DP3_4_VAL	(0xffff)
+#define	ATMEL_LCDC_DP4_5_VAL	(0xfffff)
+#define	ATMEL_LCDC_DP6_7_VAL	(0xfffffff)
+
+#define ATMEL_LCDC_PWRCON	0x083c
+#define	ATMEL_LCDC_PWR		(1    <<  0)
+#define	ATMEL_LCDC_GUARDT_OFFSET	1
+#define	ATMEL_LCDC_GUARDT	(0x7f <<  ATMEL_LCDC_GUARDT_OFFSET)
+#define	ATMEL_LCDC_BUSY		(1    << 31)
+
+#define ATMEL_LCDC_CONTRAST_CTR	0x0840
+#define	ATMEL_LCDC_PS		(3 << 0)
+#define		ATMEL_LCDC_PS_DIV1		(0 << 0)
+#define		ATMEL_LCDC_PS_DIV2		(1 << 0)
+#define		ATMEL_LCDC_PS_DIV4		(2 << 0)
+#define		ATMEL_LCDC_PS_DIV8		(3 << 0)
+#define	ATMEL_LCDC_POL		(1 << 2)
+#define		ATMEL_LCDC_POL_NEGATIVE		(0 << 2)
+#define		ATMEL_LCDC_POL_POSITIVE		(1 << 2)
+#define	ATMEL_LCDC_ENA		(1 << 3)
+#define		ATMEL_LCDC_ENA_PWMDISABLE	(0 << 3)
+#define		ATMEL_LCDC_ENA_PWMENABLE	(1 << 3)
+
+#define ATMEL_LCDC_CONTRAST_VAL	0x0844
+#define	ATMEL_LCDC_CVAL	(0xff)
+
+#define ATMEL_LCDC_IER		0x0848
+#define ATMEL_LCDC_IDR		0x084c
+#define ATMEL_LCDC_IMR		0x0850
+#define ATMEL_LCDC_ISR		0x0854
+#define ATMEL_LCDC_ICR		0x0858
+#define	ATMEL_LCDC_LNI		(1 << 0)
+#define	ATMEL_LCDC_LSTLNI	(1 << 1)
+#define	ATMEL_LCDC_EOFI		(1 << 2)
+#define	ATMEL_LCDC_UFLWI	(1 << 4)
+#define	ATMEL_LCDC_OWRI		(1 << 5)
+#define	ATMEL_LCDC_MERI		(1 << 6)
+
+#define ATMEL_LCDC_LUT(n)	(0x0c00 + ((n)*4))
+
+#endif /* __ATMEL_LCDC_H__ */
diff --git a/qemu/roms/u-boot/include/atmel_mci.h b/qemu/roms/u-boot/include/atmel_mci.h
new file mode 100644
index 000000000..090574d8c
--- /dev/null
+++ b/qemu/roms/u-boot/include/atmel_mci.h
@@ -0,0 +1,202 @@
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __ATMEL_MCI_H__
+#define __ATMEL_MCI_H__
+
+int atmel_mci_init(void *regs);
+
+#ifndef __ASSEMBLY__
+
+/*
+ * Structure for struct SoC access.
+ * Names starting with '_' are fillers.
+ */
+typedef struct atmel_mci {
+	/*	reg	Offset */
+	u32	cr;	/* 0x00 */
+	u32	mr;	/* 0x04 */
+	u32	dtor;	/* 0x08 */
+	u32	sdcr;	/* 0x0c */
+	u32	argr;	/* 0x10 */
+	u32	cmdr;	/* 0x14 */
+	u32	blkr;	/* 0x18 */
+	u32	_1c;	/* 0x1c */
+	u32	rspr;	/* 0x20 */
+	u32	rspr1;	/* 0x24 */
+	u32	rspr2;	/* 0x28 */
+	u32	rspr3;	/* 0x2c */
+	u32	rdr;	/* 0x30 */
+	u32	tdr;	/* 0x34 */
+	u32	_38;	/* 0x38 */
+	u32	_3c;	/* 0x3c */
+	u32	sr;	/* 0x40 */
+	u32	ier;	/* 0x44 */
+	u32	idr;	/* 0x48 */
+	u32	imr;	/* 0x4c */
+	u32	reserved[43];
+	u32	version;
+} atmel_mci_t;
+
+#endif /* __ASSEMBLY__ */
+
+/* Bitfields in CR */
+#define MMCI_MCIEN_OFFSET			0
+#define MMCI_MCIEN_SIZE				1
+#define MMCI_MCIDIS_OFFSET			1
+#define MMCI_MCIDIS_SIZE			1
+#define MMCI_PWSEN_OFFSET			2
+#define MMCI_PWSEN_SIZE				1
+#define MMCI_PWSDIS_OFFSET			3
+#define MMCI_PWSDIS_SIZE			1
+#define MMCI_SWRST_OFFSET			7
+#define MMCI_SWRST_SIZE				1
+
+/* Bitfields in MR */
+#define MMCI_CLKDIV_OFFSET			0
+#define MMCI_CLKDIV_SIZE			8
+#define MMCI_PWSDIV_OFFSET			8
+#define MMCI_PWSDIV_SIZE			3
+#define MMCI_RDPROOF_OFFSET			11
+#define MMCI_RDPROOF_SIZE			1
+#define MMCI_WRPROOF_OFFSET			12
+#define MMCI_WRPROOF_SIZE			1
+#define MMCI_PDCPADV_OFFSET			14
+#define MMCI_PDCPADV_SIZE			1
+#define MMCI_PDCMODE_OFFSET			15
+#define MMCI_PDCMODE_SIZE			1
+#define MMCI_BLKLEN_OFFSET			16
+#define MMCI_BLKLEN_SIZE			16
+
+/* Bitfields in DTOR */
+#define MMCI_DTOCYC_OFFSET			0
+#define MMCI_DTOCYC_SIZE			4
+#define MMCI_DTOMUL_OFFSET			4
+#define MMCI_DTOMUL_SIZE			3
+
+/* Bitfields in SDCR */
+#define MMCI_SCDSEL_OFFSET			0
+#define MMCI_SCDSEL_SIZE			4
+#define MMCI_SCDBUS_OFFSET			7
+#define MMCI_SCDBUS_SIZE			1
+
+/* Bitfields in ARGR */
+#define MMCI_ARG_OFFSET				0
+#define MMCI_ARG_SIZE				32
+
+/* Bitfields in CMDR */
+#define MMCI_CMDNB_OFFSET			0
+#define MMCI_CMDNB_SIZE				6
+#define MMCI_RSPTYP_OFFSET			6
+#define MMCI_RSPTYP_SIZE			2
+#define MMCI_SPCMD_OFFSET			8
+#define MMCI_SPCMD_SIZE				3
+#define MMCI_OPDCMD_OFFSET			11
+#define MMCI_OPDCMD_SIZE			1
+#define MMCI_MAXLAT_OFFSET			12
+#define MMCI_MAXLAT_SIZE			1
+#define MMCI_TRCMD_OFFSET			16
+#define MMCI_TRCMD_SIZE				2
+#define MMCI_TRDIR_OFFSET			18
+#define MMCI_TRDIR_SIZE				1
+#define MMCI_TRTYP_OFFSET			19
+#define MMCI_TRTYP_SIZE				2
+
+/* Bitfields in BLKR */
+/* MMCI_BLKLEN_OFFSET/SIZE already defined in MR */
+#define MMCI_BCNT_OFFSET			0
+#define MMCI_BCNT_SIZE			16
+
+/* Bitfields in RSPRx */
+#define MMCI_RSP_OFFSET				0
+#define MMCI_RSP_SIZE				32
+
+/* Bitfields in SR/IER/IDR/IMR */
+#define MMCI_CMDRDY_OFFSET			0
+#define MMCI_CMDRDY_SIZE			1
+#define MMCI_RXRDY_OFFSET			1
+#define MMCI_RXRDY_SIZE				1
+#define MMCI_TXRDY_OFFSET			2
+#define MMCI_TXRDY_SIZE				1
+#define MMCI_BLKE_OFFSET			3
+#define MMCI_BLKE_SIZE				1
+#define MMCI_DTIP_OFFSET			4
+#define MMCI_DTIP_SIZE				1
+#define MMCI_NOTBUSY_OFFSET			5
+#define MMCI_NOTBUSY_SIZE			1
+#define MMCI_ENDRX_OFFSET			6
+#define MMCI_ENDRX_SIZE				1
+#define MMCI_ENDTX_OFFSET			7
+#define MMCI_ENDTX_SIZE				1
+#define MMCI_RXBUFF_OFFSET			14
+#define MMCI_RXBUFF_SIZE			1
+#define MMCI_TXBUFE_OFFSET			15
+#define MMCI_TXBUFE_SIZE			1
+#define MMCI_RINDE_OFFSET			16
+#define MMCI_RINDE_SIZE				1
+#define MMCI_RDIRE_OFFSET			17
+#define MMCI_RDIRE_SIZE				1
+#define MMCI_RCRCE_OFFSET			18
+#define MMCI_RCRCE_SIZE				1
+#define MMCI_RENDE_OFFSET			19
+#define MMCI_RENDE_SIZE				1
+#define MMCI_RTOE_OFFSET			20
+#define MMCI_RTOE_SIZE				1
+#define MMCI_DCRCE_OFFSET			21
+#define MMCI_DCRCE_SIZE				1
+#define MMCI_DTOE_OFFSET			22
+#define MMCI_DTOE_SIZE				1
+#define MMCI_OVRE_OFFSET			30
+#define MMCI_OVRE_SIZE				1
+#define MMCI_UNRE_OFFSET			31
+#define MMCI_UNRE_SIZE				1
+
+/* Constants for DTOMUL */
+#define MMCI_DTOMUL_1_CYCLE			0
+#define MMCI_DTOMUL_16_CYCLES			1
+#define MMCI_DTOMUL_128_CYCLES			2
+#define MMCI_DTOMUL_256_CYCLES			3
+#define MMCI_DTOMUL_1024_CYCLES			4
+#define MMCI_DTOMUL_4096_CYCLES			5
+#define MMCI_DTOMUL_65536_CYCLES		6
+#define MMCI_DTOMUL_1048576_CYCLES		7
+
+/* Constants for RSPTYP */
+#define MMCI_RSPTYP_NO_RESP			0
+#define MMCI_RSPTYP_48_BIT_RESP			1
+#define MMCI_RSPTYP_136_BIT_RESP		2
+
+/* Constants for SPCMD */
+#define MMCI_SPCMD_NO_SPEC_CMD			0
+#define MMCI_SPCMD_INIT_CMD			1
+#define MMCI_SPCMD_SYNC_CMD			2
+#define MMCI_SPCMD_INT_CMD			4
+#define MMCI_SPCMD_INT_RESP			5
+
+/* Constants for TRCMD */
+#define MMCI_TRCMD_NO_TRANS			0
+#define MMCI_TRCMD_START_TRANS			1
+#define MMCI_TRCMD_STOP_TRANS			2
+
+/* Constants for TRTYP */
+#define MMCI_TRTYP_BLOCK			0
+#define MMCI_TRTYP_MULTI_BLOCK			1
+#define MMCI_TRTYP_STREAM			2
+
+/* Bit manipulation macros */
+#define MMCI_BIT(name)					\
+	(1 << MMCI_##name##_OFFSET)
+#define MMCI_BF(name,value)				\
+	(((value) & ((1 << MMCI_##name##_SIZE) - 1))	\
+	 << MMCI_##name##_OFFSET)
+#define MMCI_BFEXT(name,value)				\
+	(((value) >> MMCI_##name##_OFFSET)\
+	 & ((1 << MMCI_##name##_SIZE) - 1))
+#define MMCI_BFINS(name,value,old)			\
+	(((old) & ~(((1 << MMCI_##name##_SIZE) - 1)	\
+		    << MMCI_##name##_OFFSET))		\
+	 | MMCI_BF(name,value))
+
+#endif /* __ATMEL_MCI_H__ */
diff --git a/qemu/roms/u-boot/include/bcd.h b/qemu/roms/u-boot/include/bcd.h
new file mode 100644
index 000000000..af4aa9c7b
--- /dev/null
+++ b/qemu/roms/u-boot/include/bcd.h
@@ -0,0 +1,25 @@
+/* Permission is hereby granted to copy, modify and redistribute this code
+ * in terms of the GNU Library General Public License, Version 2 or later,
+ * at your option.
+ */
+
+/* inline functions to translate to/from binary and binary-coded decimal
+ * (frequently found in RTC chips).
+ */
+
+#ifndef _BCD_H
+#define _BCD_H
+
+#include <linux/types.h>
+
+static inline unsigned int bcd2bin(u8 val)
+{
+	return ((val) & 0x0f) + ((val) >> 4) * 10;
+}
+
+static inline u8 bin2bcd (unsigned int val)
+{
+	return (((val / 10) << 4) | (val % 10));
+}
+
+#endif /* _BCD_H */
diff --git a/qemu/roms/u-boot/include/bedbug/bedbug.h b/qemu/roms/u-boot/include/bedbug/bedbug.h
new file mode 100644
index 000000000..0c5d687f8
--- /dev/null
+++ b/qemu/roms/u-boot/include/bedbug/bedbug.h
@@ -0,0 +1,40 @@
+/* $Id$ */
+
+#ifndef _BEDBUG_H
+#define _BEDBUG_H
+
+#ifndef NULL
+#define NULL	0
+#endif
+
+#define _USE_PROTOTYPES
+
+#ifndef isblank
+#define isblank(c) isspace((int)(c))
+#endif
+
+#ifndef __P
+#if defined(_USE_PROTOTYPES) && (defined(__STDC__) || defined(__cplusplus))
+#define __P(protos)	protos		/* full-blown ANSI C */
+#else
+#define __P(protos)	()		/* traditional C preprocessor */
+#endif
+#endif
+
+#endif /* _BEDBUG_H */
+
+
+/*
+ * Copyright (c) 2001 William L. Pitts
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are freely
+ * permitted provided that the above copyright notice and this
+ * paragraph and the following disclaimer are duplicated in all
+ * such forms.
+ *
+ * This software is provided "AS IS" and without any express or
+ * implied warranties, including, without limitation, the implied
+ * warranties of merchantability and fitness for a particular
+ * purpose.
+ */
diff --git a/qemu/roms/u-boot/include/bedbug/ppc.h b/qemu/roms/u-boot/include/bedbug/ppc.h
new file mode 100644
index 000000000..76d86fdbf
--- /dev/null
+++ b/qemu/roms/u-boot/include/bedbug/ppc.h
@@ -0,0 +1,408 @@
+/* $Id$ */
+
+#ifndef _PPC_H
+#define _PPC_H
+
+/*======================================================================
+ *
+ *  OPERANDS
+ *
+ *======================================================================*/
+
+enum OP_FIELD {
+  O_AA = 1, O_BD, O_BI, O_BO, O_crbD, O_crbA, O_crbB, O_CRM, O_d, O_frC, O_frD,
+  O_frS, O_IMM, O_LI, O_LK, O_MB, O_ME, O_NB, O_OE, O_rA, O_rB, O_Rc, O_rD,
+  O_rS, O_SH, O_SIMM, O_SR, O_TO, O_UIMM, O_crfD, O_crfS, O_L, O_spr, O_tbr,
+  O_cr2 };
+
+struct operand {
+  enum OP_FIELD	field;		/* The operand identifier from the
+				   enum above */
+
+  char *	name;		/* Symbolic name of this operand */
+
+  unsigned int	bits;		/* The number of bits used by this
+				   operand */
+
+  unsigned int	shift;		/* How far to the right the operand
+				   should be shifted so that it is
+				   aligned at the beginning of the
+				   word */
+
+  unsigned int	hint;		/* A bitwise-inclusive-OR of the
+				   values shown below.  These are used
+				   tell the disassembler how to print
+				   this operand */
+};
+
+/* Values for operand hint */
+#define OH_SILENT	0x01	/* dont print this operand */
+#define OH_ADDR		0x02	/* this operand is an address */
+#define OH_REG		0x04	/* this operand is a register */
+#define OH_SPR		0x08	/* this operand is an SPR */
+#define OH_TBR		0x10	/* this operand is a TBR */
+#define OH_OFFSET	0x20	/* this operand is an offset */
+#define OH_LITERAL      0x40    /* a literal string */
+
+
+/*======================================================================
+ *
+ *  OPCODES
+ *
+ *======================================================================*/
+
+/* From the MPCxxx instruction set documentation, all instructions are
+ * 32 bits long and word aligned.  Bits 0-5 always specify the primary
+ * opcode.  Many instructions also have an extended opcode.
+ */
+
+#define GET_OPCD(i) (((unsigned long)(i) >> 26) & 0x3f)
+#define MAKE_OPCODE(i) ((((unsigned long)(i)) & 0x3f) << 26)
+
+/* The MPC860 User's Manual, Appendix D.4 contains the definitions of the
+ * instruction forms
+ */
+
+
+/*-------------------------------------------------
+ *              I-Form Instructions:
+ * bX
+ *-------------------------------------------------
+ * OPCD |           LI                       |AA|LK
+ *-------------------------------------------------*/
+
+#define I_OPCODE(i,aa,lk) (MAKE_OPCODE(i) | (((aa) & 0x1) << 1) | ((lk) & 0x1))
+#define I_MASK I_OPCODE(0x3f,0x1,0x1)
+
+
+/*-------------------------------------------------
+ *              B-Form Instructions:
+ * bcX
+ *-------------------------------------------------
+ * OPCD |    BO   |  BI  |   BD              |AA|LK
+ *-------------------------------------------------*/
+
+#define B_OPCODE(i,aa,lk) (MAKE_OPCODE(i) | (((aa) & 0x1) << 1) | ((lk) & 0x1))
+#define B_MASK B_OPCODE(0x3f,0x1,0x1)
+
+
+/*-------------------------------------------------
+ *             SC-Form Instructions:
+ * sc
+ *-------------------------------------------------
+ * OPCD | 00000 | 00000 | 00000000000000       |1|0
+ *-------------------------------------------------*/
+
+#define SC_OPCODE(i) (MAKE_OPCODE(i) | 0x2)
+#define SC_MASK SC_OPCODE(0x3f)
+
+
+/*-------------------------------------------------
+ *             D-Form Instructions:
+ * addi addic addic. addis andi. andis. cmpi cmpli
+ * lbz lbzu lha lhau lhz lhzu lmw lwz lwzu mulli
+ * ori oris stb stbu sth sthu stmw stw stwu subfic
+ * twi xori xoris
+ *-------------------------------------------------
+ * OPCD |   D    |   A   |            d
+ * OPCD |   D    |   A   |           SIMM
+ * OPCD |   S    |   A   |            d
+ * OPCD |   S    |   A   |           UIMM
+ * OPCD |crfD|0|L|   A   |           SIMM
+ * OPCD |crfD|0|L|   A   |           UIMM
+ * OPCD |   TO   |   A   |           SIMM
+ *-------------------------------------------------*/
+
+#define D_OPCODE(i) MAKE_OPCODE(i)
+#define D_MASK MAKE_OPCODE(0x3f)
+
+
+/*-------------------------------------------------
+ *            DS-Form Instructions:
+ * (none supported by MPC860)
+ *-------------------------------------------------
+ * OPCD |   D    |   A   |          ds          |XO
+ * OPCD |   S    |   A   |          ds          |XO
+ *-------------------------------------------------*/
+
+#define DS_OPCODE(i,xo) (MAKE_OPCODE(i) | ((xo) & 0x3))
+#define DS_MASK DS_OPCODE(0x3f,0x1)
+
+
+/*---------------------------------------------------
+ *            X-Form Instructions:
+ * andX andcX cmp cmpl cntlzwX dcbf dcbi dcbst dcbt
+ * dcbtst dcbz eciwx ecowx eieio eqvX extsbX extshX
+ * icbi lbzux lbxz lhaux lhax lhbrx lhzux lhxz lswi
+ * lswx lwarx lwbrx lwzux lwxz mcrfs mcrxr mfcr
+ * mfmsr mfsr mfsrin mtmsr mtsr mtsrin nandX norX
+ * orX orcX slwX srawX srawiX srwX stbux stbx
+ * sthbrx sthuxsthx stswi stswx stwbrx stwcx. stwux
+ * stwx sync tlbie tlbld tlbli tlbsync tw xorX
+ *---------------------------------------------------
+ * OPCD |   D    |    A   |    B   |      XO      |0
+ * OPCD |   D    |    A   |   NB   |      XO      |0
+ * OPCD |   D    |  00000 |    B   |      XO      |0
+ * OPCD |   D    |  00000 |  00000 |      XO      |0
+ * OPCD |   D    |0|  SR  |  00000 |      XO      |0
+ * OPCD |   S    |    A   |    B   |      XO      |Rc
+ * OPCD |   S    |    A   |    B   |      XO      |1
+ * OPCD |   S    |    A   |    B   |      XO      |0
+ * OPCD |   S    |    A   |   NB   |      XO      |0
+ * OPCD |   S    |    A   |  00000 |      XO      |Rc
+ * OPCD |   S    |  00000 |    B   |      XO      |0
+ * OPCD |   S    |  00000 |  00000 |      XO      |0
+ * OPCD |   S    |0|  SR  |  00000 |      XO      |0
+ * OPCD |   S    |    A   |   SH   |      XO      |Rc
+ * OPCD |crfD|0|L|    A   |   SH   |      XO      |0
+ * OPCD |crfD |00|    A   |    B   |      XO      |0
+ * OPCD |crfD |00|crfS |00|  00000 |      XO      |0
+ * OPCD |crfD |00|  00000 |  00000 |      XO      |0
+ * OPCD |crfD |00|  00000 | IMM  |0|      XO      |Rc
+ * OPCD |   TO   |    A   |    B   |      XO      |0
+ * OPCD |   D    |  00000 |    B   |      XO      |Rc
+ * OPCD |   D    |  00000 |  00000 |      XO      |Rc
+ * OPCD |  crbD  |  00000 |  00000 |      XO      |Rc
+ * OPCD |  00000 |    A   |    B   |      XO      |0
+ * OPCD |  00000 |  00000 |    B   |      XO      |0
+ * OPCD |  00000 |  00000 |  00000 |      XO      |0
+ *---------------------------------------------------*/
+
+#define X_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \
+			   ((rc) & 0x1))
+#define X_MASK X_OPCODE(0x3f,0x3ff,0x1)
+
+
+/*---------------------------------------------------
+ *            XL-Form Instructions:
+ * bcctrX bclrX crand crandc creqv crnand crnor cror
+ * croc crxorisync mcrf rfi
+ *---------------------------------------------------
+ * OPCD |   BO   |  BI    |  00000 |      XO      |LK
+ * OPCD |  crbD  | crbA   |  crbB  |      XO      |0
+ * OPCD |crfD |00|crfS |00|  00000 |      XO      |0
+ * OPCD |  00000 |  00000 |  00000 |      XO      |0
+ *---------------------------------------------------*/
+
+#define XL_OPCODE(i,xo,lk) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \
+			    ((lk) & 0x1))
+#define XL_MASK XL_OPCODE(0x3f,0x3ff,0x1)
+
+
+/*---------------------------------------------------
+ *            XFX-Form Instructions:
+ * mfspr mftb mtcrf mtspr
+ *---------------------------------------------------
+ * OPCD |   D    |      spr        |      XO       |0
+ * OPCD |   D    |0|    CRM      |0|      XO       |0
+ * OPCD |   S    |      spr        |      XO       |0
+ * OPCD |   D    |      tbr        |      XO       |0
+ *---------------------------------------------------*/
+
+#define XFX_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \
+			     ((rc) & 0x1))
+#define XFX_MASK XFX_OPCODE(0x3f,0x3ff,0x1)
+
+
+/*---------------------------------------------------
+ *            XFL-Form Instructions:
+ * (none supported by MPC860)
+ *---------------------------------------------------
+ * OPCD |0|      FM     |0|   B    |      XO       |0
+ *---------------------------------------------------*/
+
+#define XFL_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \
+			     ((rc) & 0x1))
+#define XFL_MASK XFL_OPCODE(0x3f,0x3ff,0x1)
+
+
+/*---------------------------------------------------
+ *            XS-Form Instructions:
+ * (none supported by MPC860)
+ *---------------------------------------------------
+ * OPCD |    S   |   A    |   sh   |      XO   |sh|LK
+ *---------------------------------------------------*/
+
+#define XS_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x1ff) << 2) | \
+			     ((rc) & 0x1))
+#define XS_MASK XS_OPCODE(0x3f,0x1ff,0x1)
+
+
+/*---------------------------------------------------
+ *            XO-Form Instructions:
+ * addX addcXaddeX addmeX addzeX divwX divwuX mulhwX
+ * mulhwuX mullwX negX subfX subfcX subfeX subfmeX
+ * subfzeX
+ *---------------------------------------------------
+ * OPCD |    D   |   A    |    B   |OE|     XO    |Rc
+ * OPCD |    D   |   A    |    B   |0 |     XO    |Rc
+ * OPCD |    D   |   A    |  00000 |OE|     XO    |Rc
+ *---------------------------------------------------*/
+
+#define XO_OPCODE(i,xo,oe,rc) (MAKE_OPCODE(i) | (((oe) & 0x1) << 10) | \
+			       (((xo) & 0x1ff) << 1) | ((rc) & 0x1))
+#define XO_MASK XO_OPCODE(0x3f,0x1ff,0x1,0x1)
+
+
+/*---------------------------------------------------
+ *            A-Form Instructions:
+ * (none supported by MPC860)
+ *---------------------------------------------------
+ * OPCD |    D   |   A    |    B   |00000|  XO    |Rc
+ * OPCD |    D   |   A    |    B   |  C  |  XO    |Rc
+ * OPCD |    D   |   A    |  00000 |  C  |  XO    |Rc
+ * OPCD |    D   |  00000 |    B   |00000|  XO    |Rc
+ *---------------------------------------------------*/
+
+#define A_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x1f) << 1) | \
+			   ((rc) & 0x1))
+#define A_MASK A_OPCODE(0x3f,0x1f,0x1)
+
+
+/*---------------------------------------------------
+ *            M-Form Instructions:
+ * rlwimiX rlwinmX rlwnmX
+ *---------------------------------------------------
+ * OPCD |    S   |   A    |    SH   |  MB |  ME   |Rc
+ * OPCD |    S   |   A    |     B   |  MB |  ME   |Rc
+ *---------------------------------------------------*/
+
+#define M_OPCODE(i,rc) (MAKE_OPCODE(i) | ((rc) & 0x1))
+#define M_MASK M_OPCODE(0x3f,0x1)
+
+
+/*---------------------------------------------------
+ *            MD-Form Instructions:
+ * (none supported by MPC860)
+ *---------------------------------------------------
+ * OPCD |    S   |   A    |    sh   |  mb | XO |sh|Rc
+ * OPCD |    S   |   A    |    sh   |  me | XO |sh|Rc
+ *---------------------------------------------------*/
+
+#define MD_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x7) << 2) | \
+			   ((rc) & 0x1))
+#define MD_MASK MD_OPCODE(0x3f,0x7,0x1)
+
+
+/*---------------------------------------------------
+ *            MDS-Form Instructions:
+ * (none supported by MPC860)
+ *---------------------------------------------------
+ * OPCD |    S   |   A    |    B    |  mb | XO    |Rc
+ * OPCD |    S   |   A    |    B    |  me | XO    |Rc
+ *---------------------------------------------------*/
+
+#define MDS_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0xf) << 1) | \
+			   ((rc) & 0x1))
+#define MDS_MASK MDS_OPCODE(0x3f,0xf,0x1)
+
+#define INSTRUCTION( memaddr ) ntohl(*(unsigned long *)(memaddr))
+
+#define MAX_OPERANDS  8
+
+struct ppc_ctx;
+
+struct opcode {
+  unsigned long	opcode;		/* The complete opcode as produced by
+				   one of the XXX_OPCODE macros above */
+
+  unsigned long	mask;		/* The mask to use on an instruction
+				   before comparing with the opcode
+				   field to see if it matches */
+
+  enum OP_FIELD	fields[MAX_OPERANDS];
+				/* An array defining the operands for
+				   this opcode.  The values of the
+				   array are the operand identifiers */
+
+  int (*hfunc)(struct ppc_ctx *);
+				/* Address of a function to handle the given
+				   mnemonic */
+
+  char *	name;		/* The symbolic name of this opcode */
+
+  unsigned int	hint;		/* A bitwise-inclusive-OR of the
+				   values shown below.  These are used
+				   tell the disassembler how to print
+				   some operands for this opcode */
+};
+
+/* values for opcode hints */
+#define H_RELATIVE	0x1	/* The address operand is relative */
+#define H_IMM_HIGH	0x2	/* [U|S]IMM field shifted high */
+#define H_RA0_IS_0	0x4	/* If rA = 0 then treat as literal 0 */
+
+struct ppc_ctx {
+  struct opcode *	op;
+  unsigned long		instr;
+  unsigned int		flags;
+  int			datalen;
+  char			data[ 256 ];
+  char			radix_fmt[ 8 ];
+  unsigned char *	virtual;
+};
+
+
+/*======================================================================
+ *
+ *  FUNCTIONS
+ *
+ *======================================================================*/
+
+/* Values for flags as passed to various ppc routines */
+#define F_RADOCTAL	0x1	/* output radix = unsigned octal */
+#define F_RADUDECIMAL	0x2	/* output radix = unsigned decimal */
+#define F_RADSDECIMAL	0x4	/* output radix = signed decimal */
+#define F_RADHEX	0x8	/* output radix = unsigned hex */
+#define F_SIMPLE	0x10	/* use simplified mnemonics */
+#define F_SYMBOL	0x20	/* use symbol lookups for addresses */
+#define F_INSTR		0x40	/* output the raw instruction */
+#define F_LOCALMEM	0x80	/* retrieve opcodes from local memory
+				   rather than from the HMI */
+#define F_LINENO	0x100	/* show line number info if available */
+#define F_VALIDONLY	0x200	/* cache: valid entries only */
+
+/* Values for assembler error codes */
+#define E_ASM_BAD_OPCODE	1
+#define E_ASM_NUM_OPERANDS	2
+#define E_ASM_BAD_REGISTER	3
+#define E_ASM_BAD_SPR		4
+#define E_ASM_BAD_TBR		5
+
+extern int disppc __P((unsigned char *,unsigned char *,int,
+		       int (*)(const char *), unsigned long));
+extern int print_source_line __P((char *,char *,int,
+				  int (*pfunc)(const char *)));
+extern int find_next_address __P((unsigned char *,int,struct pt_regs *));
+extern int handle_bc __P((struct ppc_ctx *));
+extern unsigned long asmppc __P((unsigned long,char*,int*));
+extern char *asm_error_str __P((int));
+
+/*======================================================================
+ *
+ *  GLOBAL VARIABLES
+ *
+ *======================================================================*/
+
+extern struct operand operands[];
+extern const unsigned int n_operands;
+extern struct opcode opcodes[];
+extern const unsigned int n_opcodes;
+
+#endif /* _PPC_H */
+
+
+/*
+ * Copyright (c) 2000 William L. Pitts and W. Gerald Hicks
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are freely
+ * permitted provided that the above copyright notice and this
+ * paragraph and the following disclaimer are duplicated in all
+ * such forms.
+ *
+ * This software is provided "AS IS" and without any express or
+ * implied warranties, including, without limitation, the implied
+ * warranties of merchantability and fitness for a particular
+ * purpose.
+ */
diff --git a/qemu/roms/u-boot/include/bedbug/regs.h b/qemu/roms/u-boot/include/bedbug/regs.h
new file mode 100644
index 000000000..eb746912b
--- /dev/null
+++ b/qemu/roms/u-boot/include/bedbug/regs.h
@@ -0,0 +1,402 @@
+/* $Id$ */
+
+#ifndef _REGS_H
+#define _REGS_H
+
+/* Special Purpose Registers */
+
+#define SPR_CR		-1
+#define SPR_MSR		-2
+
+#define SPR_XER		1
+#define SPR_LR		8
+#define SPR_CTR		9
+#define SPR_DSISR	18
+#define SPR_DAR		19
+#define SPR_DEC		22
+#define SPR_SRR0	26
+#define SPR_SRR1	27
+#define SPR_EIE		80
+#define SPR_EID		81
+#define SPR_CMPA	144
+#define SPR_CMPB	145
+#define SPR_CMPC	146
+#define SPR_CMPD	147
+#define SPR_ICR		148
+#define SPR_DER		149
+#define SPR_COUNTA	150
+#define SPR_COUNTB	151
+#define SPR_CMPE	152
+#define SPR_CMPF	153
+#define SPR_CMPG	154
+#define SPR_CMPH	155
+#define SPR_LCTRL1	156
+#define SPR_LCTRL2	157
+#define SPR_ICTRL	158
+#define SPR_BAR		159
+#define SPR_USPRG0      256
+#define SPR_SPRG4_RO    260
+#define SPR_SPRG5_RO    261
+#define SPR_SPRG6_RO    262
+#define SPR_SPRG7_RO    263
+#define SPR_SPRG0	272
+#define SPR_SPRG1	273
+#define SPR_SPRG2	274
+#define SPR_SPRG3	275
+#define SPR_SPRG4       276
+#define SPR_SPRG5       277
+#define SPR_SPRG6       278
+#define SPR_SPRG7       279
+#define SPR_EAR         282	/* MPC603e core */
+#define SPR_TBL         284
+#define SPR_TBU         285
+#define SPR_PVR		287
+#define SPR_IC_CST	560
+#define SPR_IC_ADR	561
+#define SPR_IC_DAT	562
+#define SPR_DC_CST	568
+#define SPR_DC_ADR	569
+#define SPR_DC_DAT	570
+#define SPR_DPDR	630
+#define SPR_IMMR	638
+#define SPR_MI_CTR	784
+#define SPR_MI_AP	786
+#define SPR_MI_EPN	787
+#define SPR_MI_TWC	789
+#define SPR_MI_RPN	790
+#define SPR_MD_CTR	792
+#define SPR_M_CASID	793
+#define SPR_MD_AP	794
+#define SPR_MD_EPN	795
+#define SPR_M_TWB	796
+#define SPR_MD_TWC	797
+#define SPR_MD_RPN	798
+#define SPR_M_TW	799
+#define SPR_MI_DBCAM	816
+#define SPR_MI_DBRAM0	817
+#define SPR_MI_DBRAM1	818
+#define SPR_MD_DBCAM	824
+#define SPR_MD_DBRAM0	825
+#define SPR_MD_DBRAM1	826
+#define SPR_ZPR         944
+#define SPR_PID         945
+#define SPR_CCR0        947
+#define SPR_IAC3        948
+#define SPR_IAC4        949
+#define SPR_DVC1        950
+#define SPR_DVC2        951
+#define SPR_SGR         953
+#define SPR_DCWR        954
+#define SPR_SLER        955
+#define SPR_SU0R        956
+#define SPR_DBCR1       957
+#define SPR_ICDBDR      979
+#define SPR_ESR         980
+#define SPR_DEAR        981
+#define SPR_EVPR        982
+#define SPR_TSR         984
+#define SPR_TCR         986
+#define SPR_PIT         987
+#define SPR_SRR2        990
+#define SPR_SRR3        991
+#define SPR_DBSR        1008
+#define SPR_DBCR0       1010
+#define SPR_IABR        1010	/* MPC603e core */
+#define SPR_IAC1        1012
+#define SPR_IAC2        1013
+#define SPR_DAC1        1014
+#define SPR_DAC2        1015
+#define SPR_DCCR        1018
+#define SPR_ICCR        1019
+
+/* Bits for the DBCR0 register */
+#define DBCR0_EDM	0x80000000
+#define DBCR0_IDM	0x40000000
+#define DBCR0_RST	0x30000000
+#define DBCR0_IC	0x08000000
+#define DBCR0_BT	0x04000000
+#define DBCR0_EDE	0x02000000
+#define DBCR0_TDE	0x01000000
+#define DBCR0_IA1	0x00800000
+#define DBCR0_IA2	0x00400000
+#define DBCR0_IA12	0x00200000
+#define DBCR0_IA12X	0x00100000
+#define DBCR0_IA3	0x00080000
+#define DBCR0_IA4	0x00040000
+#define DBCR0_IA34	0x00020000
+#define DBCR0_IA34X	0x00010000
+#define DBCR0_IA12T	0x00008000
+#define DBCR0_IA34T	0x00004000
+#define DBCR0_FT	0x00000001
+
+/* Bits for the DBCR1 register */
+#define DBCR1_D1R	0x80000000
+#define DBCR1_D2R	0x40000000
+#define DBCR1_D1W	0x20000000
+#define DBCR1_D2W	0x10000000
+#define DBCR1_D1S	0x0C000000
+#define DBCR1_D2S	0x03000000
+#define DBCR1_DA12	0x00800000
+#define DBCR1_DA12X	0x00400000
+#define DBCR1_DV1M	0x000C0000
+#define DBCR1_DV2M	0x00030000
+#define DBCR1_DV1BE	0x0000F000
+#define DBCR1_DV2BE	0x00000F00
+
+/*
+ * DBSR bits which have conflicting definitions on true Book E versus PPC40x
+ */
+#ifdef CONFIG_BOOKE
+#define DBSR_IA1	0x00800000	/* Instr Address Compare 1 Event */
+#define DBSR_IA2	0x00400000	/* Instr Address Compare 2 Event */
+#define DBSR_IA3	0x00200000	/* Instr Address Compare 3 Event */
+#define DBSR_IA4	0x00100000	/* Instr Address Compare 4 Event */
+#endif
+#ifndef CONFIG_440
+#define DBSR_IA1	0x04000000	/* Instr Address Compare 1 Event */
+#define DBSR_IA2	0x02000000	/* Instr Address Compare 2 Event */
+#define DBSR_IA3	0x00080000	/* Instr Address Compare 3 Event */
+#define DBSR_IA4	0x00040000	/* Instr Address Compare 4 Event */
+#endif
+
+struct spr_info {
+  int  spr_val;
+  char spr_name[ 10 ];
+};
+
+extern struct spr_info spr_map[];
+extern const unsigned int n_sprs;
+
+
+#define SET_REGISTER( str, val ) \
+({ unsigned long __value = (val); \
+  asm volatile( str : : "r" (__value)); \
+  __value; })
+
+#define	GET_REGISTER( str ) \
+({ unsigned long __value; \
+  asm volatile( str : "=r" (__value) : ); \
+  __value; })
+
+#define	 GET_CR()	     GET_REGISTER( "mfcr %0" )
+#define	 SET_CR(val)	     SET_REGISTER( "mtcr %0", val )
+#define	 GET_MSR()	     GET_REGISTER( "mfmsr %0" )
+#define	 SET_MSR(val)	     SET_REGISTER( "mtmsr %0", val )
+#define	 GET_XER()	     GET_REGISTER( "mfspr %0,1" )
+#define	 SET_XER(val)	     SET_REGISTER( "mtspr 1,%0", val )
+#define	 GET_LR()	     GET_REGISTER( "mfspr %0,8" )
+#define	 SET_LR(val)	     SET_REGISTER( "mtspr 8,%0", val )
+#define	 GET_CTR()	     GET_REGISTER( "mfspr %0,9" )
+#define	 SET_CTR(val)	     SET_REGISTER( "mtspr 9,%0", val )
+#define	 GET_DSISR()	     GET_REGISTER( "mfspr %0,18" )
+#define	 SET_DSISR(val)	     SET_REGISTER( "mtspr 18,%0", val )
+#define	 GET_DAR()	     GET_REGISTER( "mfspr %0,19" )
+#define	 SET_DAR(val)	     SET_REGISTER( "mtspr 19,%0", val )
+#define	 GET_DEC()	     GET_REGISTER( "mfspr %0,22" )
+#define	 SET_DEC(val)	     SET_REGISTER( "mtspr 22,%0", val )
+#define	 GET_SRR0()	     GET_REGISTER( "mfspr %0,26" )
+#define	 SET_SRR0(val)       SET_REGISTER( "mtspr 26,%0", val )
+#define	 GET_SRR1()	     GET_REGISTER( "mfspr %0,27" )
+#define	 SET_SRR1(val)	     SET_REGISTER( "mtspr 27,%0", val )
+#define	 GET_EIE()	     GET_REGISTER( "mfspr %0,80" )
+#define	 SET_EIE(val)	     SET_REGISTER( "mtspr 80,%0", val )
+#define	 GET_EID()	     GET_REGISTER( "mfspr %0,81" )
+#define	 SET_EID(val)	     SET_REGISTER( "mtspr 81,%0", val )
+#define	 GET_CMPA()	     GET_REGISTER( "mfspr %0,144" )
+#define	 SET_CMPA(val)	     SET_REGISTER( "mtspr 144,%0", val )
+#define	 GET_CMPB()	     GET_REGISTER( "mfspr %0,145" )
+#define	 SET_CMPB(val)	     SET_REGISTER( "mtspr 145,%0", val )
+#define	 GET_CMPC()	     GET_REGISTER( "mfspr %0,146" )
+#define	 SET_CMPC(val)	     SET_REGISTER( "mtspr 146,%0", val )
+#define	 GET_CMPD()	     GET_REGISTER( "mfspr %0,147" )
+#define	 SET_CMPD(val)	     SET_REGISTER( "mtspr 147,%0", val )
+#define	 GET_ICR()	     GET_REGISTER( "mfspr %0,148" )
+#define	 SET_ICR(val)	     SET_REGISTER( "mtspr 148,%0", val )
+#define	 GET_DER()	     GET_REGISTER( "mfspr %0,149" )
+#define	 SET_DER(val)	     SET_REGISTER( "mtspr 149,%0", val )
+#define	 GET_COUNTA()	     GET_REGISTER( "mfspr %0,150" )
+#define	 SET_COUNTA(val)     SET_REGISTER( "mtspr 150,%0", val )
+#define	 GET_COUNTB()	     GET_REGISTER( "mfspr %0,151" )
+#define	 SET_COUNTB(val)     SET_REGISTER( "mtspr 151,%0", val )
+#define	 GET_CMPE()	     GET_REGISTER( "mfspr %0,152" )
+#define	 SET_CMPE(val)	     SET_REGISTER( "mtspr 152,%0", val )
+#define	 GET_CMPF()	     GET_REGISTER( "mfspr %0,153" )
+#define	 SET_CMPF(val)	     SET_REGISTER( "mtspr 153,%0", val )
+#define	 GET_CMPG()	     GET_REGISTER( "mfspr %0,154" )
+#define	 SET_CMPG(val)	     SET_REGISTER( "mtspr 154,%0", val )
+#define	 GET_CMPH()	     GET_REGISTER( "mfspr %0,155" )
+#define	 SET_CMPH(val)	     SET_REGISTER( "mtspr 155,%0", val )
+#define  GET_LCTRL1()	     GET_REGISTER( "mfspr %0,156" )
+#define	 SET_LCTRL1(val)     SET_REGISTER( "mtspr 156,%0", val )
+#define  GET_LCTRL2()	     GET_REGISTER( "mfspr %0,157" )
+#define	 SET_LCTRL2(val)     SET_REGISTER( "mtspr 157,%0", val )
+#define  GET_ICTRL()	     GET_REGISTER( "mfspr %0,158" )
+#define	 SET_ICTRL(val)	     SET_REGISTER( "mtspr 158,%0", val )
+#define  GET_BAR()	     GET_REGISTER( "mfspr %0,159" )
+#define	 SET_BAR(val)	     SET_REGISTER( "mtspr 159,%0", val )
+#define  GET_USPRG0()	     GET_REGISTER( "mfspr %0,256" )
+#define	 SET_USPRG0(val)     SET_REGISTER( "mtspr 256,%0", val )
+#define  GET_SPRG4_RO()	     GET_REGISTER( "mfspr %0,260" )
+#define	 SET_SPRG4_RO(val)   SET_REGISTER( "mtspr 260,%0", val )
+#define  GET_SPRG5_RO()	     GET_REGISTER( "mfspr %0,261" )
+#define	 SET_SPRG5_RO(val)   SET_REGISTER( "mtspr 261,%0", val )
+#define  GET_SPRG6_RO()	     GET_REGISTER( "mfspr %0,262" )
+#define	 SET_SPRG6_RO(val)   SET_REGISTER( "mtspr 262,%0", val )
+#define  GET_SPRG7_RO()	     GET_REGISTER( "mfspr %0,263" )
+#define	 SET_SPRG7_RO(val)   SET_REGISTER( "mtspr 263,%0", val )
+#define  GET_SPRG0()	     GET_REGISTER( "mfspr %0,272" )
+#define	 SET_SPRG0(val)	     SET_REGISTER( "mtspr 272,%0", val )
+#define  GET_SPRG1()	     GET_REGISTER( "mfspr %0,273" )
+#define	 SET_SPRG1(val)	     SET_REGISTER( "mtspr 273,%0", val )
+#define  GET_SPRG2()	     GET_REGISTER( "mfspr %0,274" )
+#define	 SET_SPRG2(val)	     SET_REGISTER( "mtspr 274,%0", val )
+#define  GET_SPRG3()	     GET_REGISTER( "mfspr %0,275" )
+#define	 SET_SPRG3(val)	     SET_REGISTER( "mtspr 275,%0", val )
+#define  GET_SPRG4()	     GET_REGISTER( "mfspr %0,276" )
+#define	 SET_SPRG4(val)      SET_REGISTER( "mtspr 276,%0", val )
+#define  GET_SPRG5()	     GET_REGISTER( "mfspr %0,277" )
+#define	 SET_SPRG5(val)	     SET_REGISTER( "mtspr 277,%0", val )
+#define  GET_SPRG6()	     GET_REGISTER( "mfspr %0,278" )
+#define	 SET_SPRG6(val)	     SET_REGISTER( "mtspr 278,%0", val )
+#define  GET_SPRG7()	     GET_REGISTER( "mfspr %0,279" )
+#define	 SET_SPRG7(val)	     SET_REGISTER( "mtspr 279,%0", val )
+#define  GET_EAR()	     GET_REGISTER( "mfspr %0,282" )
+#define	 SET_EAR(val)	     SET_REGISTER( "mtspr 282,%0", val )
+#define  GET_TBL()	     GET_REGISTER( "mfspr %0,284" )
+#define	 SET_TBL(val)	     SET_REGISTER( "mtspr 284,%0", val )
+#define  GET_TBU()	     GET_REGISTER( "mfspr %0,285" )
+#define	 SET_TBU(val)	     SET_REGISTER( "mtspr 285,%0", val )
+#define  GET_PVR()	     GET_REGISTER( "mfspr %0,287" )
+#define	 SET_PVR(val)	     SET_REGISTER( "mtspr 287,%0", val )
+#define  GET_IC_CST()	     GET_REGISTER( "mfspr %0,560" )
+#define	 SET_IC_CST(val)     SET_REGISTER( "mtspr 560,%0", val )
+#define  GET_IC_ADR()	     GET_REGISTER( "mfspr %0,561" )
+#define	 SET_IC_ADR(val)     SET_REGISTER( "mtspr 561,%0", val )
+#define  GET_IC_DAT()	     GET_REGISTER( "mfspr %0,562" )
+#define	 SET_IC_DAT(val)     SET_REGISTER( "mtspr 562,%0", val )
+#define  GET_DC_CST()	     GET_REGISTER( "mfspr %0,568" )
+#define	 SET_DC_CST(val)     SET_REGISTER( "mtspr 568,%0", val )
+#define  GET_DC_ADR()	     GET_REGISTER( "mfspr %0,569" )
+#define	 SET_DC_ADR(val)     SET_REGISTER( "mtspr 569,%0", val )
+#define  GET_DC_DAT()	     GET_REGISTER( "mfspr %0,570" )
+#define	 SET_DC_DAT(val)     SET_REGISTER( "mtspr 570,%0", val )
+#define  GET_DPDR()	     GET_REGISTER( "mfspr %0,630" )
+#define	 SET_DPDR(val)	     SET_REGISTER( "mtspr 630,%0", val )
+#define  GET_IMMR()	     GET_REGISTER( "mfspr %0,638" )
+#define	 SET_IMMR(val)	     SET_REGISTER( "mtspr 638,%0", val )
+#define  GET_MI_CTR()	     GET_REGISTER( "mfspr %0,784" )
+#define	 SET_MI_CTR(val)     SET_REGISTER( "mtspr 784,%0", val )
+#define  GET_MI_AP()	     GET_REGISTER( "mfspr %0,786" )
+#define	 SET_MI_AP(val)	     SET_REGISTER( "mtspr 786,%0", val )
+#define  GET_MI_EPN()	     GET_REGISTER( "mfspr %0,787" )
+#define	 SET_MI_EPN(val)     SET_REGISTER( "mtspr 787,%0", val )
+#define  GET_MI_TWC()	     GET_REGISTER( "mfspr %0,789" )
+#define	 SET_MI_TWC(val)     SET_REGISTER( "mtspr 789,%0", val )
+#define  GET_MI_RPN()	     GET_REGISTER( "mfspr %0,790" )
+#define	 SET_MI_RPN(val)     SET_REGISTER( "mtspr 790,%0", val )
+#define  GET_MD_CTR()	     GET_REGISTER( "mfspr %0,792" )
+#define	 SET_MD_CTR(val)     SET_REGISTER( "mtspr 792,%0", val )
+#define  GET_M_CASID()	     GET_REGISTER( "mfspr %0,793" )
+#define	 SET_M_CASID(val)    SET_REGISTER( "mtspr 793,%0", val )
+#define  GET_MD_AP()	     GET_REGISTER( "mfspr %0,794" )
+#define	 SET_MD_AP(val)	     SET_REGISTER( "mtspr ,794%0", val )
+#define  GET_MD_EPN()	     GET_REGISTER( "mfspr %0,795" )
+#define	 SET_MD_EPN(val)     SET_REGISTER( "mtspr 795,%0", val )
+#define  GET_M_TWB()	     GET_REGISTER( "mfspr %0,796" )
+#define	 SET_M_TWB(val)	     SET_REGISTER( "mtspr 796,%0", val )
+#define  GET_MD_TWC()	     GET_REGISTER( "mfspr %0,797" )
+#define	 SET_MD_TWC(val)     SET_REGISTER( "mtspr 797,%0", val )
+#define  GET_MD_RPN()	     GET_REGISTER( "mfspr %0,798" )
+#define	 SET_MD_RPN(val)     SET_REGISTER( "mtspr 798,%0", val )
+#define  GET_M_TW()	     GET_REGISTER( "mfspr %0,799" )
+#define	 SET_M_TW(val)	     SET_REGISTER( "mtspr 799,%0", val )
+#define  GET_MI_DBCAM()      GET_REGISTER( "mfspr %0,816" )
+#define	 SET_MI_DBCAM(val)   SET_REGISTER( "mtspr 816,%0", val )
+#define  GET_MI_DBRAM0()     GET_REGISTER( "mfspr %0,817" )
+#define	 SET_MI_DBRAM0(val)  SET_REGISTER( "mtspr 817,%0", val )
+#define  GET_MI_DBRAM1()     GET_REGISTER( "mfspr %0,818" )
+#define	 SET_MI_DBRAM1(val)  SET_REGISTER( "mtspr 818,%0", val )
+#define  GET_MD_DBCAM()      GET_REGISTER( "mfspr %0,824" )
+#define	 SET_MD_DBCA(val)    SET_REGISTER( "mtspr 824,%0", val )
+#define  GET_MD_DBRAM0()     GET_REGISTER( "mfspr %0,825" )
+#define	 SET_MD_DBRAM0(val)  SET_REGISTER( "mtspr 825,%0", val )
+#define  GET_MD_DBRAM1()     GET_REGISTER( "mfspr %0,826" )
+#define	 SET_MD_DBRAM1(val)  SET_REGISTER( "mtspr 826,%0", val )
+#define  GET_ZPR()           GET_REGISTER( "mfspr %0,944" )
+#define	 SET_ZPR(val)        SET_REGISTER( "mtspr 944,%0", val )
+#define  GET_PID()	     GET_REGISTER( "mfspr %0,945" )
+#define	 SET_PID(val)	     SET_REGISTER( "mtspr 945,%0", val )
+#define  GET_CCR0()	     GET_REGISTER( "mfspr %0,947" )
+#define	 SET_CCR0(val)	     SET_REGISTER( "mtspr 947,%0", val )
+#define	 GET_IAC3()	     GET_REGISTER( "mfspr %0,948" )
+#define	 SET_IAC3(val)	     SET_REGISTER( "mtspr 948,%0", val )
+#define	 GET_IAC4()	     GET_REGISTER( "mfspr %0,949" )
+#define	 SET_IAC4(val)	     SET_REGISTER( "mtspr 949,%0", val )
+#define	 GET_DVC1()	     GET_REGISTER( "mfspr %0,950" )
+#define	 SET_DVC1(val)	     SET_REGISTER( "mtspr 950,%0", val )
+#define	 GET_DVC2()	     GET_REGISTER( "mfspr %0,951" )
+#define	 SET_DVC2(val)	     SET_REGISTER( "mtspr 951,%0", val )
+#define	 GET_SGR()	     GET_REGISTER( "mfspr %0,953" )
+#define	 SET_SGR(val)	     SET_REGISTER( "mtspr 953,%0", val )
+#define	 GET_DCWR()	     GET_REGISTER( "mfspr %0,954" )
+#define	 SET_DCWR(val)	     SET_REGISTER( "mtspr 954,%0", val )
+#define	 GET_SLER()	     GET_REGISTER( "mfspr %0,955" )
+#define	 SET_SLER(val)	     SET_REGISTER( "mtspr 955,%0", val )
+#define	 GET_SU0R()	     GET_REGISTER( "mfspr %0,956" )
+#define	 SET_SU0R(val)	     SET_REGISTER( "mtspr 956,%0", val )
+#define	 GET_DBCR1()	     GET_REGISTER( "mfspr %0,957" )
+#define	 SET_DBCR1(val)	     SET_REGISTER( "mtspr 957,%0", val )
+#define	 GET_ICDBDR()	     GET_REGISTER( "mfspr %0,979" )
+#define	 SET_ICDBDR(val)     SET_REGISTER( "mtspr 979,%0", val )
+#define	 GET_ESR()	     GET_REGISTER( "mfspr %0,980" )
+#define	 SET_ESR(val)	     SET_REGISTER( "mtspr 980,%0", val )
+#define	 GET_DEAR()	     GET_REGISTER( "mfspr %0,981" )
+#define	 SET_DEAR(val)	     SET_REGISTER( "mtspr 981,%0", val )
+#define	 GET_EVPR()	     GET_REGISTER( "mfspr %0,982" )
+#define	 SET_EVPR(val)	     SET_REGISTER( "mtspr 982,%0", val )
+#define	 GET_TSR()	     GET_REGISTER( "mfspr %0,984" )
+#define	 SET_TSR(val)	     SET_REGISTER( "mtspr 984,%0", val )
+#define	 GET_TCR()	     GET_REGISTER( "mfspr %0,986" )
+#define	 SET_TCR(val)	     SET_REGISTER( "mtspr 986,%0", val )
+#define	 GET_PIT()	     GET_REGISTER( "mfspr %0,987" )
+#define	 SET_PIT(val)	     SET_REGISTER( "mtspr 987,%0", val )
+#define	 GET_SRR2()	     GET_REGISTER( "mfspr %0,990" )
+#define	 SET_SRR2(val)	     SET_REGISTER( "mtspr 990,%0", val )
+#define	 GET_SRR3()	     GET_REGISTER( "mfspr %0,991" )
+#define	 SET_SRR3(val)	     SET_REGISTER( "mtspr 991,%0", val )
+#define	 GET_DBSR()	     GET_REGISTER( "mfspr %0,1008" )
+#define	 SET_DBSR(val)	     SET_REGISTER( "mtspr 1008,%0", val )
+#define	 GET_DBCR0()	     GET_REGISTER( "mfspr %0,1010" )
+#define	 SET_DBCR0(val)	     SET_REGISTER( "mtspr 1010,%0", val )
+#define	 GET_IABR()	     GET_REGISTER( "mfspr %0,1010" )
+#define	 SET_IABR(val)	     SET_REGISTER( "mtspr 1010,%0", val )
+#define	 GET_IAC1()	     GET_REGISTER( "mfspr %0,1012" )
+#define	 SET_IAC1(val)	     SET_REGISTER( "mtspr 1012,%0", val )
+#define	 GET_IAC2()	     GET_REGISTER( "mfspr %0,1013" )
+#define	 SET_IAC2(val)	     SET_REGISTER( "mtspr 1013,%0", val )
+#define	 GET_DAC1()	     GET_REGISTER( "mfspr %0,1014" )
+#define	 SET_DAC1(val)	     SET_REGISTER( "mtspr 1014,%0", val )
+#define	 GET_DAC2()	     GET_REGISTER( "mfspr %0,1015" )
+#define	 SET_DAC2(val)	     SET_REGISTER( "mtspr 1015,%0", val )
+#define	 GET_DCCR()	     GET_REGISTER( "mfspr %0,1018" )
+#define	 SET_DCCR(val)	     SET_REGISTER( "mtspr 1018,%0", val )
+#define	 GET_ICCR()	     GET_REGISTER( "mfspr %0,1019" )
+#define	 SET_ICCR(val)	     SET_REGISTER( "mtspr 1019,%0", val )
+
+#endif /* _REGS_H */
+
+
+/*
+ * Copyright (c) 2000 William L. Pitts and W. Gerald Hicks
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are freely
+ * permitted provided that the above copyright notice and this
+ * paragraph and the following disclaimer are duplicated in all
+ * such forms.
+ *
+ * This software is provided "AS IS" and without any express or
+ * implied warranties, including, without limitation, the implied
+ * warranties of merchantability and fitness for a particular
+ * purpose.
+ */
diff --git a/qemu/roms/u-boot/include/bedbug/tables.h b/qemu/roms/u-boot/include/bedbug/tables.h
new file mode 100644
index 000000000..e675de320
--- /dev/null
+++ b/qemu/roms/u-boot/include/bedbug/tables.h
@@ -0,0 +1,601 @@
+/* $Id$ */
+
+#ifndef TABLES_H
+#define TABLES_H
+
+/* This is only included by common/bedbug.c, and depends on the following
+ * files to already be included
+ *   common.h
+ *   bedbug/bedbug.h
+ *   bedbug/ppc.h
+ *   bedbug/regs.h
+ */
+
+struct operand operands[] = {
+  /*Field    Name     Bits  Shift  Hint			   Position	*/
+  /*-----    ------   ----- -----  ----			   ------------ */
+  { O_AA,    "O_AA",	1,     1,  OH_SILENT },		/*   30		*/
+  { O_BD,    "O_BD",   14,     2,  OH_ADDR },		/* 16-29	*/
+  { O_BI,    "O_BI",	5,    16,  0 },			/* 11-15	*/
+  { O_BO,    "O_BO",	5,    21,  0 },			/*  6-10	*/
+  { O_crbD,  "O_crbD",	5,    21,  0 },			/*  6-10	*/
+  { O_crbA,  "O_crbA",	5,    16,  0 },			/* 11-15	*/
+  { O_crbB,  "O_crbB",	5,    11,  0 },			/* 16-20	*/
+  { O_CRM,   "O_CRM",	8,    12,  0 },			/* 12-19	*/
+  { O_d,     "O_d",    15,     0,  OH_OFFSET },		/* 16-31	*/
+  { O_frC,   "O_frC",	5,     6,  0 },			/* 21-25	*/
+  { O_frD,   "O_frD",	5,    21,  0 },			/*  6-10	*/
+  { O_frS,   "O_frS",	5,    21,  0 },			/*  6-10	*/
+  { O_IMM,   "O_IMM",	4,    12,  0 },			/* 16-19	*/
+  { O_LI,    "O_LI",   24,     2,  OH_ADDR },		/*  6-29	*/
+  { O_LK,    "O_LK",	1,     0,  OH_SILENT },		/*   31		*/
+  { O_MB,    "O_MB",	5,     6,  0 },			/* 21-25	*/
+  { O_ME,    "O_ME",	5,     1,  0 },			/* 26-30	*/
+  { O_NB,    "O_NB",	5,    11,  0 },			/* 16-20	*/
+  { O_OE,    "O_OE",	1,    10,  OH_SILENT },		/*   21		*/
+  { O_rA,    "O_rA",	5,    16,  OH_REG },		/* 11-15	*/
+  { O_rB,    "O_rB",	5,    11,  OH_REG },		/* 16-20	*/
+  { O_Rc,    "O_Rc",	1,     0,  OH_SILENT },		/*   31		*/
+  { O_rD,    "O_rD",	5,    21,  OH_REG },		/*  6-10	*/
+  { O_rS,    "O_rS",	5,    21,  OH_REG },		/*  6-10	*/
+  { O_SH,    "O_SH",	5,    11,  0 },			/* 16-20	*/
+  { O_SIMM,  "O_SIMM", 16,     0,  0 },			/* 16-31	*/
+  { O_SR,    "O_SR",	4,    16,  0 },			/* 12-15	*/
+  { O_TO,    "O_TO",	5,    21,  0 },			/*  6-10	*/
+  { O_UIMM,  "O_UIMM", 16,     0,  0 },			/* 16-31	*/
+  { O_crfD,  "O_crfD",	3,    23,  0 },			/*  6- 8	*/
+  { O_crfS,  "O_crfS",	3,    18,  0 },			/* 11-13	*/
+  { O_L,     "O_L",	1,    21,  0 },			/*   10		*/
+  { O_spr,   "O_spr",  10,    11,  OH_SPR },		/* 11-20	*/
+  { O_tbr,   "O_tbr",  10,    11,  OH_TBR },		/* 11-20	*/
+  { O_cr2,   "O_cr2",	0,     0,  OH_LITERAL },	/* "cr2"	*/
+};
+
+const unsigned int n_operands = sizeof(operands) / sizeof(operands[0]);
+
+/* A note about the fields array in the opcodes structure:
+   The operands are listed in the order they appear in the output.
+
+   This table is arranged in numeric order of the opcode.  Note that some
+   opcodes have defined bits in odd places so not all forms of a command
+   will be in the same place.  This is done so that a binary search can be
+   done to find the opcodes.  Note that table D.2 in the MPC860 User's
+   Manual "Instructions Sorted by Opcode" does not account for these
+   bit locations */
+
+struct opcode opcodes[] = {
+  { D_OPCODE(3),	   D_MASK,   {O_TO, O_rA, O_SIMM, 0},
+    0,		     "twi",	     0 },
+  { D_OPCODE(7),	   D_MASK,   {O_rD, O_rA, O_SIMM, 0},
+    0,		     "mulli",	     0 },
+  { D_OPCODE(8),	   D_MASK,   {O_rD, O_rA, O_SIMM, 0},
+    0,		     "subfic",	     0 },
+  { D_OPCODE(10),	   D_MASK,   {O_crfD, O_L, O_rA, O_UIMM, 0},
+    0,		     "cmpli",	     0 },
+  { D_OPCODE(11),	   D_MASK,   {O_crfD, O_L, O_rA, O_SIMM, 0},
+    0,		     "cmpi",	     0 },
+  { D_OPCODE(12),	   D_MASK,   {O_rD, O_rA, O_SIMM, 0},
+    0,		     "addic",	     0 },
+  { D_OPCODE(13),	   D_MASK,   {O_rD, O_rA, O_SIMM, 0},
+    0,		     "addic.",	     0 },
+  { D_OPCODE(14),	   D_MASK,   {O_rD, O_rA, O_SIMM, 0},
+    0,		     "addi",	     H_RA0_IS_0 },
+  { D_OPCODE(15),	   D_MASK,   {O_rD, O_rA, O_SIMM, 0},
+    0,		     "addis",	     H_RA0_IS_0|H_IMM_HIGH },
+  { B_OPCODE(16,0,0),	   B_MASK,   {O_BO, O_BI, O_BD, O_AA, O_LK, 0},
+    handle_bc,	     "bc",	     H_RELATIVE },
+  { B_OPCODE(16,0,1),	   B_MASK,   {O_BO, O_BI, O_BD, O_AA, O_LK, 0},
+    0,		     "bcl",	     H_RELATIVE },
+  { B_OPCODE(16,1,0),	   B_MASK,   {O_BO, O_BI, O_BD, O_AA, O_LK, 0},
+    0,		     "bca",	     0 },
+  { B_OPCODE(16,1,1),	   B_MASK,   {O_BO, O_BI, O_BD, O_AA, O_LK, 0},
+    0,		     "bcla",	     0 },
+  { SC_OPCODE(17),	   SC_MASK,  {0},
+    0,		     "sc",	     0 },
+  { I_OPCODE(18,0,0),	   I_MASK,   {O_LI, O_AA, O_LK, 0},
+    0,		     "b",	     H_RELATIVE },
+  { I_OPCODE(18,0,1),	   I_MASK,   {O_LI, O_AA, O_LK, 0},
+    0,		     "bl",	     H_RELATIVE },
+  { I_OPCODE(18,1,0),	   I_MASK,   {O_LI, O_AA, O_LK, 0},
+    0,		     "ba",	     0 },
+  { I_OPCODE(18,1,1),	   I_MASK,   {O_LI, O_AA, O_LK, 0},
+    0,		     "bla",	     0 },
+  { XL_OPCODE(19,0,0),	   XL_MASK,  {O_crfD, O_crfS},
+    0,		     "mcrf",	     0 },
+  { XL_OPCODE(19,16,0),    XL_MASK,  {O_BO, O_BI, O_LK, 0},
+    0,		     "bclr",	     0 },
+  { XL_OPCODE(19,16,1),    XL_MASK,  {O_BO, O_BI, O_LK, 0},
+    0,		     "bclrl",	     0 },
+  { XL_OPCODE(19,33,0),    XL_MASK,  {O_crbD, O_crbA, O_crbB, 0},
+    0,		     "crnor",	     0 },
+  { XL_OPCODE(19,50,0),    XL_MASK,  {0},
+    0,		     "rfi",	     0 },
+  { XL_OPCODE(19,129,0),   XL_MASK,  {O_crbD, O_crbA, O_crbB, 0},
+    0,		     "crandc",	     0 },
+  { XL_OPCODE(19,150,0),   XL_MASK,  {0},
+    0,		     "isync",	     0 },
+  { XL_OPCODE(19,193,0),   XL_MASK,  {O_crbD, O_crbA, O_crbB, 0},
+    0,		     "crxor",	     0 },
+  { XL_OPCODE(19,225,0),   XL_MASK,  {O_crbD, O_crbA, O_crbB, 0},
+    0,		     "crnand",	     0 },
+  { XL_OPCODE(19,257,0),   XL_MASK,  {O_crbD, O_crbA, O_crbB, 0},
+    0,		     "crand",	     0 },
+  { XL_OPCODE(19,289,0),   XL_MASK,  {O_crbD, O_crbA, O_crbB, 0},
+    0,		     "creqv",	     0 },
+  { XL_OPCODE(19,417,0),   XL_MASK,  {O_crbD, O_crbA, O_crbB, 0},
+    0,		     "crorc",	     0 },
+  { XL_OPCODE(19,449,0),   XL_MASK,  {O_crbD, O_crbA, O_crbB, 0},
+    0,		     "cror",	     0 },
+  { XL_OPCODE(19,528,0),   XL_MASK,  {O_BO, O_BI, O_LK, 0},
+    0,		     "bcctr",	     0 },
+  { XL_OPCODE(19,528,1),   XL_MASK,  {O_BO, O_BI, O_LK, 0},
+    0,		     "bcctrl",	     0 },
+  { M_OPCODE(20,0),	   M_MASK,   {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0},
+    0,		     "rlwimi",	     0 },
+  { M_OPCODE(20,1),	   M_MASK,   {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0},
+    0,		     "rlwimi.",      0 },
+  { M_OPCODE(21,0),	   M_MASK,   {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0},
+    0,		     "rlwinm",	     0 },
+  { M_OPCODE(21,1),	   M_MASK,   {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0},
+    0,		     "rlwinm.",      0 },
+  { M_OPCODE(23,0),	   M_MASK,   {O_rA, O_rS, O_rB, O_MB, O_ME, O_Rc, 0},
+    0,		     "rlwnm",	     0 },
+  { M_OPCODE(23,1),	   M_MASK,   {O_rA, O_rS, O_rB, O_MB, O_ME, O_Rc, 0},
+    0,		     "rlwnm.",	     0 },
+  { D_OPCODE(24),	   D_MASK,   {O_rA, O_rS, O_UIMM, 0},
+    0,		     "ori",	     0 },
+  { D_OPCODE(25),	   D_MASK,   {O_rA, O_rS, O_UIMM, 0},
+    0,		     "oris",	     H_IMM_HIGH },
+  { D_OPCODE(26),	   D_MASK,   {O_rA, O_rS, O_UIMM, 0},
+    0,		     "xori",	     0 },
+  { D_OPCODE(27),	   D_MASK,   {O_rA, O_rS, O_UIMM, 0},
+    0,		     "xoris",	     H_IMM_HIGH },
+  { D_OPCODE(28),	   D_MASK,   {O_rA, O_rS, O_UIMM, 0},
+    0,		     "andi.",	     0 },
+  { D_OPCODE(29),	   D_MASK,   {O_rA, O_rS, O_UIMM, 0},
+    0,		     "andis.",	     H_IMM_HIGH },
+  { X_OPCODE(31,0,0),	   X_MASK,   {O_crfD, O_L, O_rA, O_rB, 0},
+    0,		     "cmp",	     0 },
+  { X_OPCODE(31,4,0),	   X_MASK,   {O_TO, O_rA, O_rB, 0},
+    0,		     "tw",	     0 },
+  { XO_OPCODE(31,8,0,0),   XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "subfc",	     0 },
+  { XO_OPCODE(31,8,0,1),   XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "subfc.",	     0 },
+  { XO_OPCODE(31,10,0,0),  XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "addc",	     0 },
+  { XO_OPCODE(31,10,0,1),  XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "addc.",	     0 },
+  { XO_OPCODE(31,11,0,0),  XO_MASK,  {O_rD, O_rA, O_rB, O_Rc, 0},
+    0,		     "mulhwu",	     0 },
+  { XO_OPCODE(31,11,0,1),  XO_MASK,  {O_rD, O_rA, O_rB, O_Rc, 0},
+    0,		     "mulhwu.",      0 },
+  { X_OPCODE(31,19,0),	   X_MASK,   {O_rD, 0},
+    0,		     "mfcr",	     0 },
+  { X_OPCODE(31,20,0),	   X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,		     "lwarx",	     H_RA0_IS_0 },
+  { X_OPCODE(31,23,0),	   X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,		     "lwzx",	     H_RA0_IS_0 },
+  { X_OPCODE(31,24,0),	   X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "slw",	     0 },
+  { X_OPCODE(31,24,1),	   X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "slw.",	     0 },
+  { X_OPCODE(31,26,0),	   X_MASK,   {O_rA, O_rS, O_Rc, 0 },
+    0,		     "cntlzw",	     0 },
+  { X_OPCODE(31,26,1),	   X_MASK,   {O_rA, O_rS, O_Rc, 0},
+    0,		     "cntlzw.",      0 },
+  { X_OPCODE(31,28,0),	   X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "and",	     0 },
+  { X_OPCODE(31,28,1),	   X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "and.",	     0 },
+  { X_OPCODE(31,32,0),	   X_MASK,   {O_crfD, O_L, O_rA, O_rB, 0},
+    0,		     "cmpl",	     0 },
+  { XO_OPCODE(31,40,0,0),  XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "subf",	     0 },
+  { XO_OPCODE(31,40,0,1),  XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "subf.",	     0 },
+  { X_OPCODE(31,54,0),	   X_MASK,   {O_rA, O_rB, 0},
+    0,		     "dcbst",	     H_RA0_IS_0 },
+  { X_OPCODE(31,55,0),	   X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,		     "lwzux",	     0 },
+  { X_OPCODE(31,60,0),	   X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "andc",	     0 },
+  { X_OPCODE(31,60,1),	   X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "andc.",	     0 },
+  { XO_OPCODE(31,75,0,0),  XO_MASK,  {O_rD, O_rA, O_rB, O_Rc, 0},
+    0,		     "mulhw",	     0 },
+  { XO_OPCODE(31,75,0,1),  XO_MASK,  {O_rD, O_rA, O_rB, O_Rc, 0},
+    0,		     "mulhw.",	     0 },
+  { X_OPCODE(31,83,0),	   X_MASK,   {O_rD, 0},
+    0,		     "mfmsr",	     0 },
+  { X_OPCODE(31,86,0),	   X_MASK,   {O_rA, O_rB, 0},
+    0,		     "dcbf",	     H_RA0_IS_0 },
+  { X_OPCODE(31,87,0),	   X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,		     "lbzx",	     H_RA0_IS_0 },
+  { XO_OPCODE(31,104,0,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "neg",	     0 },
+  { XO_OPCODE(31,104,0,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "neg.",	     0 },
+  { X_OPCODE(31,119,0),    X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,		     "lbzux",	     0 },
+  { X_OPCODE(31,124,0),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "nor",	     0 },
+  { X_OPCODE(31,124,1),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "nor.",	     0 },
+  { XO_OPCODE(31,136,0,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "subfe",	     0 },
+  { XO_OPCODE(31,136,0,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "subfe.",	     0 },
+  { XO_OPCODE(31,138,0,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "adde",	     0 },
+  { XO_OPCODE(31,138,0,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "adde.",	     0 },
+  { XFX_OPCODE(31,144,0),  XFX_MASK, {O_CRM, O_rS, 0},
+    0,		     "mtcrf",	     0 },
+  { X_OPCODE(31,146,0),    X_MASK,   {O_rS, 0},
+    0,		     "mtmsr",	     0 },
+  { X_OPCODE(31,150,1),    X_MASK,   {O_rS, O_rA, O_rB, 0},
+    0,		     "stwcx.",	     0 },
+  { X_OPCODE(31,151,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
+    0,		     "stwx",	     0 },
+  { X_OPCODE(31,183,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
+    0,		     "stwux",	     0 },
+  { XO_OPCODE(31,200,0,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "subfze",	     0 },
+  { XO_OPCODE(31,200,0,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "subfze.",      0 },
+  { XO_OPCODE(31,202,0,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "addze",	     0 },
+  { XO_OPCODE(31,202,0,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "addze.",	     0 },
+  { X_OPCODE(31,210,0),    X_MASK,   {O_SR, O_rS, 0},
+    0,		     "mtsr",	     0 },
+  { X_OPCODE(31,215,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
+    0,		     "stbx",	     H_RA0_IS_0 },
+  { XO_OPCODE(31,232,0,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "subfme",	     0 },
+  { XO_OPCODE(31,232,0,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "subfme.",      0 },
+  { XO_OPCODE(31,234,0,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "addme",	     0 },
+  { XO_OPCODE(31,234,0,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "addme.",	     0 },
+  { XO_OPCODE(31,235,0,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "mullw",	     0 },
+  { XO_OPCODE(31,235,0,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "mullw.",	     0 },
+  { X_OPCODE(31,242,0),    X_MASK,   {O_rS, O_rB, 0},
+    0,		     "mtsrin",	     0 },
+  { X_OPCODE(31,246,0),    X_MASK,   {O_rA, O_rB, 0},
+    0,		     "dcbtst",	     H_RA0_IS_0 },
+  { X_OPCODE(31,247,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
+    0,		     "stbux",	     0 },
+  { XO_OPCODE(31,266,0,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "add",	     0 },
+  { XO_OPCODE(31,266,0,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "add.",	     0 },
+  { X_OPCODE(31,278,0),    X_MASK,   {O_rA, O_rB, 0},
+    0,		     "dcbt",	     H_RA0_IS_0 },
+  { X_OPCODE(31,279,0),    X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,		     "lhzx",	     H_RA0_IS_0 },
+  { X_OPCODE(31,284,0),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "eqv",	     0 },
+  { X_OPCODE(31,284,1),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "eqv.",	     0 },
+  { X_OPCODE(31,306,0),    X_MASK,   {O_rB, 0},
+    0,		     "tlbie",	     0 },
+  { X_OPCODE(31,310,0),    X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,		     "eciwx",	     H_RA0_IS_0 },
+  { X_OPCODE(31,311,0),    X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,		     "lhzux",	     0 },
+  { X_OPCODE(31,316,0),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "xor",	     0 },
+  { X_OPCODE(31,316,1),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "xor.",	     0 },
+  { XFX_OPCODE(31,339,0),  XFX_MASK, {O_rD, O_spr, 0},
+    0,		     "mfspr",	     0 },
+  { X_OPCODE(31,343,0),    X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,		     "lhax",	     H_RA0_IS_0 },
+  { X_OPCODE(31,370,0),    X_MASK,   {0},
+    0,		     "tlbia",	     0 },
+  { XFX_OPCODE(31,371,0),  XFX_MASK, {O_rD, O_tbr, 0},
+    0,		     "mftb",	     0 },
+  { X_OPCODE(31,375,0),    X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,		     "lhaux",	     0 },
+  { X_OPCODE(31,407,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
+    0,		     "sthx",	     H_RA0_IS_0 },
+  { X_OPCODE(31,412,0),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "orc",	     0 },
+  { X_OPCODE(31,412,1),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "orc.",	     0 },
+  { X_OPCODE(31,438,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
+    0,		     "ecowx",	     H_RA0_IS_0 },
+  { X_OPCODE(31,439,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
+    0,		     "sthux",	     0 },
+  { X_OPCODE(31,444,0),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "or",	     0 },
+  { X_OPCODE(31,444,1),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "or.",	     0 },
+  { XO_OPCODE(31,459,0,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "divwu",	     0 },
+  { XO_OPCODE(31,459,0,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "divwu.",	     0 },
+  { XFX_OPCODE(31,467,0),  XFX_MASK, {O_spr, O_rS, 0},
+    0,		     "mtspr",	     0 },
+  { X_OPCODE(31,470,0),    X_MASK,   {O_rA, O_rB, 0},
+    0,		     "dcbi",	     H_RA0_IS_0 },
+  { X_OPCODE(31,476,0),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "nand",	     0 },
+  { X_OPCODE(31,476,1),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc,0},
+    0,		     "nand.",	     0 },
+  { XO_OPCODE(31,491,0,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "divw",	     0 },
+  { XO_OPCODE(31,491,0,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "divw.",	     0 },
+  { X_OPCODE(31,512,0),    X_MASK,   {O_crfD, 0},
+    0,		     "mcrxr",	     0 },
+  { XO_OPCODE(31,8,1,0),   XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "subfco",	     0 },
+  { XO_OPCODE(31,8,1,1),   XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "subfco.",      0 },
+  { XO_OPCODE(31,10,1,0),  XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "addco",	     0 },
+  { XO_OPCODE(31,10,1,1),  XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "addco.",	     0 },
+  { X_OPCODE(31,533,0),    X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,		     "lswx",	     H_RA0_IS_0 },
+  { X_OPCODE(31,534,0),    X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,		     "lwbrx",	     H_RA0_IS_0 },
+  { X_OPCODE(31,536,0),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "srw",	     0 },
+  { X_OPCODE(31,536,1),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "srw.",	     0 },
+  { XO_OPCODE(31,40,1,0),  XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "subfo",	     0 },
+  { XO_OPCODE(31,40,1,1),  XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "subfo.",	     0 },
+  { X_OPCODE(31,566,0),    X_MASK,   {0},
+    0,		     "tlbsync",      0 },
+  { X_OPCODE(31,595,0),    X_MASK,   {O_rD, O_SR, 0},
+    0,		     "mfsr",	     0 },
+  { X_OPCODE(31,597,0),    X_MASK,   {O_rD, O_rA, O_NB, 0},
+    0,		     "lswi",	     H_RA0_IS_0 },
+  { X_OPCODE(31,598,0),    X_MASK,   {0},
+    0,		     "sync",	     0 },
+  { XO_OPCODE(31,104,1,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "nego",	     0 },
+  { XO_OPCODE(31,104,1,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "nego.",	     0 },
+  { XO_OPCODE(31,136,1,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "subfeo",	     0 },
+  { XO_OPCODE(31,136,1,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "subfeo.",      0 },
+  { XO_OPCODE(31,138,1,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "addeo",	     0 },
+  { XO_OPCODE(31,138,1,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "addeo.",	     0 },
+  { X_OPCODE(31,659,0),    X_MASK,   {O_rD, O_rB, 0},
+    0,		     "mfsrin",	     0 },
+  { X_OPCODE(31,661,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
+    0,		     "stswx",	     H_RA0_IS_0 },
+  { X_OPCODE(31,662,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
+    0,		     "stwbrx",	     H_RA0_IS_0 },
+  { XO_OPCODE(31,200,1,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "subfzeo",      0 },
+  { XO_OPCODE(31,200,1,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "subfzeo.",     0 },
+  { XO_OPCODE(31,202,1,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "addzeo",	     0 },
+  { XO_OPCODE(31,202,1,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "addzeo.",      0 },
+  { X_OPCODE(31,725,0),    X_MASK,   {O_rS, O_rA, O_NB, 0},
+    0,		     "stswi",	     H_RA0_IS_0 },
+  { XO_OPCODE(31,232,1,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "subfmeo",      0 },
+  { XO_OPCODE(31,232,1,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "subfmeo.",     0 },
+  { XO_OPCODE(31,234,1,0), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "addmeo",	     0 },
+  { XO_OPCODE(31,234,1,1), XO_MASK,  {O_rD, O_rA, O_OE, O_Rc, 0},
+    0,		     "addmeo.",      0 },
+  { XO_OPCODE(31,235,1,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "mullwo",	     0 },
+  { XO_OPCODE(31,235,1,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "mullwo.",      0 },
+  { XO_OPCODE(31,266,1,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "addo",	     0 },
+  { XO_OPCODE(31,266,1,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "addo.",	     0 },
+  { X_OPCODE(31,790,0),    X_MASK,   {O_rD, O_rA, O_rB, 0},
+    0,		     "lhbrx",	     H_RA0_IS_0 },
+  { X_OPCODE(31,792,0),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "sraw",	     0 },
+  { X_OPCODE(31,792,1),    X_MASK,   {O_rA, O_rS, O_rB, O_Rc, 0},
+    0,		     "sraw.",	     0 },
+  { X_OPCODE(31,824,0),    X_MASK,   {O_rA, O_rS, O_SH, O_Rc, 0},
+    0,		     "srawi",	     0 },
+  { X_OPCODE(31,824,1),    X_MASK,   {O_rA, O_rS, O_SH, O_Rc, 0},
+    0,		     "srawi.",	     0 },
+  { X_OPCODE(31,854,0),    X_MASK,   {0},
+    0,		     "eieio",	     0 },
+  { X_OPCODE(31,918,0),    X_MASK,   {O_rS, O_rA, O_rB, 0},
+    0,		     "sthbrx",	     H_RA0_IS_0 },
+  { X_OPCODE(31,922,0),    X_MASK,   {O_rA, O_rS, O_Rc, 0},
+    0,		     "extsh",	     0 },
+  { X_OPCODE(31,922,1),    X_MASK,   {O_rA, O_rS, O_Rc, 0},
+    0,		     "extsh.",	     0 },
+  { X_OPCODE(31,954,0),    X_MASK,   {O_rA, O_rS, O_Rc, 0},
+    0,		     "extsb",	     0 },
+  { X_OPCODE(31,954,1),    X_MASK,   {O_rA, O_rS, O_Rc, 0},
+    0,		     "extsb.",	     0 },
+  { XO_OPCODE(31,459,1,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "divwuo",	     0 },
+  { XO_OPCODE(31,459,1,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "divwuo.",      0 },
+  { X_OPCODE(31,978,0),    X_MASK,   {O_rB, 0},
+    0,		     "tlbld",	     0 },
+  { X_OPCODE(31,982,0),    X_MASK,   {O_rA, O_rB, 0},
+    0,		     "icbi",	     H_RA0_IS_0 },
+  { XO_OPCODE(31,491,1,0), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "divwo",	     0 },
+  { XO_OPCODE(31,491,1,1), XO_MASK,  {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
+    0,		     "divwo.",	     0 },
+  { X_OPCODE(31,1010,0),   X_MASK,   {O_rB, 0},
+    0,		     "tlbli",	     0 },
+  { X_OPCODE(31,1014,0),   X_MASK,   {O_rA, O_rB, 0},
+    0,		     "dcbz",	     H_RA0_IS_0 },
+  { D_OPCODE(32),	   D_MASK,   {O_rD, O_d, O_rA, 0},
+    0,		     "lwz",	     H_RA0_IS_0 },
+  { D_OPCODE(33),	   D_MASK,   {O_rD, O_d, O_rA, 0},
+    0,		     "lwzu",	     0 },
+  { D_OPCODE(34),	   D_MASK,   {O_rD, O_d, O_rA, 0},
+    0,		     "lbz",	     H_RA0_IS_0 },
+  { D_OPCODE(35),	   D_MASK,   {O_rD, O_d, O_rA, 0},
+    0,		     "lbzu",	     0 },
+  { D_OPCODE(36),	   D_MASK,   {O_rS, O_d, O_rA, 0},
+    0,		     "stw",	     H_RA0_IS_0 },
+  { D_OPCODE(37),	   D_MASK,   {O_rS, O_d, O_rA, 0},
+    0,		     "stwu",	     0 },
+  { D_OPCODE(38),	   D_MASK,   {O_rS, O_d, O_rA, 0},
+    0,		     "stb",	     H_RA0_IS_0 },
+  { D_OPCODE(39),	   D_MASK,   {O_rS, O_d, O_rA, 0},
+    0,		     "stbu",	     0 },
+  { D_OPCODE(40),	   D_MASK,   {O_rD, O_d, O_rA, 0},
+    0,		     "lhz",	     H_RA0_IS_0 },
+  { D_OPCODE(41),	   D_MASK,   {O_rD, O_d, O_rA, 0},
+    0,		     "lhzu",	     0 },
+  { D_OPCODE(42),	   D_MASK,   {O_rD, O_d, O_rA, 0},
+    0,		     "lha",	     H_RA0_IS_0 },
+  { D_OPCODE(43),	   D_MASK,   {O_rD, O_d, O_rA, 0},
+    0,		     "lhau",	     0 },
+  { D_OPCODE(44),	   D_MASK,   {O_rS, O_d, O_rA, 0},
+    0,		     "sth",	     H_RA0_IS_0 },
+  { D_OPCODE(45),	   D_MASK,   {O_rS, O_d, O_rA, 0},
+    0,		     "sthu",	     0 },
+  { D_OPCODE(46),	   D_MASK,   {O_rD, O_d, O_rA, 0},
+    0,		     "lmw",	     H_RA0_IS_0 },
+  { D_OPCODE(47),	   D_MASK,   {O_rS, O_d, O_rA, 0},
+    0,		     "stmw",	     H_RA0_IS_0 },
+};
+
+const unsigned int n_opcodes = sizeof(opcodes) / sizeof(opcodes[0]);
+
+struct spr_info spr_map[] = {
+  { SPR_XER,	"XER" },
+  { SPR_LR,	"LR" },
+  { SPR_CTR,	"CTR" },
+  { SPR_DSISR,	"DSISR" },
+  { SPR_DAR,	"DAR" },
+  { SPR_DEC,	"DEC" },
+  { SPR_SRR0,	"SRR0" },
+  { SPR_SRR1,	"SRR1" },
+  { SPR_EIE,	"EIE" },
+  { SPR_EID,	"EID" },
+  { SPR_CMPA,	"CMPA" },
+  { SPR_CMPB,	"CMPB" },
+  { SPR_CMPC,	"CMPC" },
+  { SPR_CMPD,	"CMPD" },
+  { SPR_ICR,	"ICR" },
+  { SPR_DER,	"DER" },
+  { SPR_COUNTA,	"COUNTA" },
+  { SPR_COUNTB,	"COUNTB" },
+  { SPR_CMPE,	"CMPE" },
+  { SPR_CMPF,	"CMPF" },
+  { SPR_CMPG,	"CMPG" },
+  { SPR_CMPH,	"CMPH" },
+  { SPR_LCTRL1,	"LCTRL1" },
+  { SPR_LCTRL2,	"LCTRL2" },
+  { SPR_ICTRL,	"ICTRL" },
+  { SPR_BAR,	"BAR" },
+  { SPR_USPRG0,	"USPRG0" },
+  { SPR_SPRG4_RO,	"SPRG4_RO" },
+  { SPR_SPRG5_RO,	"SPRG5_RO" },
+  { SPR_SPRG6_RO,	"SPRG6_RO" },
+  { SPR_SPRG7_RO,	"SPRG7_RO" },
+  { SPR_SPRG0,	"SPRG0" },
+  { SPR_SPRG1,	"SPRG1" },
+  { SPR_SPRG2,	"SPRG2" },
+  { SPR_SPRG3,	"SPRG3" },
+  { SPR_SPRG4,	"SPRG4" },
+  { SPR_SPRG5,	"SPRG5" },
+  { SPR_SPRG6,	"SPRG6" },
+  { SPR_SPRG7,	"SPRG7" },
+  { SPR_EAR,	"EAR" },
+  { SPR_TBL,	"TBL" },
+  { SPR_TBU,	"TBU" },
+  { SPR_IC_CST,	"IC_CST" },
+  { SPR_IC_ADR,	"IC_ADR" },
+  { SPR_IC_DAT,	"IC_DAT" },
+  { SPR_DC_CST,	"DC_CST" },
+  { SPR_DC_ADR,	"DC_ADR" },
+  { SPR_DC_DAT,	"DC_DAT" },
+  { SPR_DPDR,	"DPDR" },
+  { SPR_IMMR,	"IMMR" },
+  { SPR_MI_CTR,	"MI_CTR" },
+  { SPR_MI_AP,	"MI_AP" },
+  { SPR_MI_EPN,	"MI_EPN" },
+  { SPR_MI_TWC,	"MI_TWC" },
+  { SPR_MI_RPN,	"MI_RPN" },
+  { SPR_MD_CTR,	"MD_CTR" },
+  { SPR_M_CASID,	"M_CASID" },
+  { SPR_MD_AP,	"MD_AP" },
+  { SPR_MD_EPN,	"MD_EPN" },
+  { SPR_M_TWB,	"M_TWB" },
+  { SPR_MD_TWC,	"MD_TWC" },
+  { SPR_MD_RPN,	"MD_RPN" },
+  { SPR_M_TW,	"M_TW" },
+  { SPR_MI_DBCAM,	"MI_DBCAM" },
+  { SPR_MI_DBRAM0,	"MI_DBRAM0" },
+  { SPR_MI_DBRAM1,	"MI_DBRAM1" },
+  { SPR_MD_DBCAM,	"MD_DBCAM" },
+  { SPR_MD_DBRAM0,	"MD_DBRAM0" },
+  { SPR_MD_DBRAM1,	"MD_DBRAM1" },
+  { SPR_ZPR,	"ZPR" },
+  { SPR_PID,	"PID" },
+  { SPR_CCR0,	"CCR0" },
+  { SPR_IAC3,	"IAC3" },
+  { SPR_IAC4,	"IAC4" },
+  { SPR_DVC1,	"DVC1" },
+  { SPR_DVC2,	"DVC2" },
+  { SPR_SGR,	"SGR" },
+  { SPR_DCWR,	"DCWR" },
+  { SPR_SLER,	"SLER" },
+  { SPR_SU0R,	"SU0R" },
+  { SPR_DBCR1,	"DBCR1" },
+  { SPR_ICDBDR,	"ICDBDR" },
+  { SPR_ESR,	"ESR" },
+  { SPR_DEAR,	"DEAR" },
+  { SPR_EVPR,	"EVPR" },
+  { SPR_TSR,	"TSR" },
+  { SPR_TCR,	"TCR" },
+  { SPR_PIT,	"PIT" },
+  { SPR_SRR2,	"SRR2" },
+  { SPR_SRR3,	"SRR3" },
+  { SPR_DBSR,	"DBSR" },
+  { SPR_DBCR0,	"DBCR0" },
+  { SPR_IAC1,	"IAC1" },
+  { SPR_IAC2,	"IAC2" },
+  { SPR_DAC1,	"DAC1" },
+  { SPR_DAC2,	"DAC2" },
+  { SPR_DCCR,	"DCCR" },
+  { SPR_ICCR,	"ICCR" },
+};
+
+const unsigned int n_sprs = sizeof(spr_map) / sizeof(spr_map[0]);
+
+#endif
+
+/*
+ * Copyright (c) 2000 William L. Pitts and W. Gerald Hicks
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are freely
+ * permitted provided that the above copyright notice and this
+ * paragraph and the following disclaimer are duplicated in all
+ * such forms.
+ *
+ * This software is provided "AS IS" and without any express or
+ * implied warranties, including, without limitation, the implied
+ * warranties of merchantability and fitness for a particular
+ * purpose.
+ */
diff --git a/qemu/roms/u-boot/include/bedbug/type.h b/qemu/roms/u-boot/include/bedbug/type.h
new file mode 100644
index 000000000..b7b447b1f
--- /dev/null
+++ b/qemu/roms/u-boot/include/bedbug/type.h
@@ -0,0 +1,26 @@
+#ifndef _TYPE_BEDBUG_H
+#define _TYPE_BEDBUG_H
+
+/* Supporting routines */
+int bedbug_puts (const char *);
+void bedbug_init (void);
+void bedbug860_init (void);
+void do_bedbug_breakpoint (struct pt_regs *);
+void bedbug_main_loop (unsigned long, struct pt_regs *);
+
+
+typedef struct {
+	int hw_debug_enabled;
+	int stopped;
+	int current_bp;
+	struct pt_regs *regs;
+
+	void (*do_break) (cmd_tbl_t *, int, int, char * const []);
+	void (*break_isr) (struct pt_regs *);
+	int (*find_empty) (void);
+	int (*set) (int, unsigned long);
+	int (*clear) (int);
+} CPU_DEBUG_CTX;
+
+
+#endif /* _TYPE_BEDBUG_H  */
diff --git a/qemu/roms/u-boot/include/bitfield.h b/qemu/roms/u-boot/include/bitfield.h
new file mode 100644
index 000000000..ec4815c8e
--- /dev/null
+++ b/qemu/roms/u-boot/include/bitfield.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:      GPL-2.0+
+ */
+
+/*
+ * Bitfield operations
+ *
+ * These are generic bitfield operations which allow manipulation of variable
+ * width bitfields within a word. One use of this would be to use data tables
+ * to determine how to reprogram fields within R/W hardware registers.
+ *
+ * Example:
+ *
+ *            old_reg_val
+ * +--------+----+---+--+-----+----------+
+ * |        |    |   |  | old |          |
+ * +--------+----+---+--+-----+----------+
+ *
+ *            new_reg_val
+ * +--------+----+---+--+-----+----------+
+ * |        |    |   |  | new |          |
+ * +--------+----+---+--+-----+----------+
+ *
+ * mask = bitfield_mask(10, 5);
+ * old = bitfield_extract(old_reg_val, 10, 5);
+ * new_reg_val = bitfield_replace(old_reg_val, 10, 5, new);
+ *
+ * The numbers 10 and 5 could for example come from data
+ * tables which describe all bitfields in all registers.
+ */
+
+#include <linux/types.h>
+
+/* Produces a mask of set bits covering a range of a uint value */
+static inline uint bitfield_mask(uint shift, uint width)
+{
+	return ((1 << width) - 1) << shift;
+}
+
+/* Extract the value of a bitfield found within a given register value */
+static inline uint bitfield_extract(uint reg_val, uint shift, uint width)
+{
+	return (reg_val & bitfield_mask(shift, width)) >> shift;
+}
+
+/*
+ * Replace the value of a bitfield found within a given register value
+ * Returns the newly modified uint value with the replaced field.
+ */
+static inline uint bitfield_replace(uint reg_val, uint shift, uint width,
+				    uint bitfield_val)
+{
+	uint mask = bitfield_mask(shift, width);
+
+	return (reg_val & ~mask) | (bitfield_val << shift);
+}
diff --git a/qemu/roms/u-boot/include/bmp_layout.h b/qemu/roms/u-boot/include/bmp_layout.h
new file mode 100644
index 000000000..22b1fbc94
--- /dev/null
+++ b/qemu/roms/u-boot/include/bmp_layout.h
@@ -0,0 +1,61 @@
+/* (C) Copyright 2002
+ * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/************************************************************************/
+/* ** Layout of a bmp file						*/
+/************************************************************************/
+
+#ifndef _BMP_H_
+#define _BMP_H_
+
+typedef struct bmp_color_table_entry {
+	__u8	blue;
+	__u8	green;
+	__u8	red;
+	__u8	reserved;
+} __attribute__ ((packed)) bmp_color_table_entry_t;
+
+/* When accessing these fields, remember that they are stored in little
+   endian format, so use linux macros, e.g. le32_to_cpu(width)          */
+
+typedef struct bmp_header {
+	/* Header */
+	char signature[2];
+	__u32	file_size;
+	__u32	reserved;
+	__u32	data_offset;
+	/* InfoHeader */
+	__u32	size;
+	__u32	width;
+	__u32	height;
+	__u16	planes;
+	__u16	bit_count;
+	__u32	compression;
+	__u32	image_size;
+	__u32	x_pixels_per_m;
+	__u32	y_pixels_per_m;
+	__u32	colors_used;
+	__u32	colors_important;
+	/* ColorTable */
+
+} __attribute__ ((packed)) bmp_header_t;
+
+typedef struct bmp_image {
+	bmp_header_t header;
+	/* We use a zero sized array just as a placeholder for variable
+	   sized array */
+	bmp_color_table_entry_t color_table[0];
+} bmp_image_t;
+
+/* Data in the bmp_image is aligned to this length */
+#define BMP_DATA_ALIGN	4
+
+/* Constants for the compression field */
+#define BMP_BI_RGB	0
+#define BMP_BI_RLE8	1
+#define BMP_BI_RLE4	2
+
+#endif							/* _BMP_H_ */
diff --git a/qemu/roms/u-boot/include/bootcount.h b/qemu/roms/u-boot/include/bootcount.h
new file mode 100644
index 000000000..06fb4d357
--- /dev/null
+++ b/qemu/roms/u-boot/include/bootcount.h
@@ -0,0 +1,40 @@
+/*
+ * (C) Copyright 2012
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/byteorder.h>
+
+#if !defined(CONFIG_SYS_BOOTCOUNT_LE) && !defined(CONFIG_SYS_BOOTCOUNT_BE)
+# if __BYTE_ORDER == __LITTLE_ENDIAN
+#  define CONFIG_SYS_BOOTCOUNT_LE
+# else
+#  define CONFIG_SYS_BOOTCOUNT_BE
+# endif
+#endif
+
+#ifdef CONFIG_SYS_BOOTCOUNT_LE
+static inline void raw_bootcount_store(volatile u32 *addr, u32 data)
+{
+	out_le32(addr, data);
+}
+
+static inline u32 raw_bootcount_load(volatile u32 *addr)
+{
+	return in_le32(addr);
+}
+#else
+static inline void raw_bootcount_store(volatile u32 *addr, u32 data)
+{
+	out_be32(addr, data);
+}
+
+static inline u32 raw_bootcount_load(volatile u32 *addr)
+{
+	return in_be32(addr);
+}
+#endif
diff --git a/qemu/roms/u-boot/include/bootstage.h b/qemu/roms/u-boot/include/bootstage.h
new file mode 100644
index 000000000..87bf906b2
--- /dev/null
+++ b/qemu/roms/u-boot/include/bootstage.h
@@ -0,0 +1,391 @@
+/*
+ * This file implements recording of each stage of the boot process. It is
+ * intended to implement timing of each stage, reporting this information
+ * to the user and passing it to the OS for logging / further analysis.
+ *
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _BOOTSTAGE_H
+#define _BOOTSTAGE_H
+
+/* The number of boot stage records available for the user */
+#ifndef CONFIG_BOOTSTAGE_USER_COUNT
+#define CONFIG_BOOTSTAGE_USER_COUNT	20
+#endif
+
+/* Flags for each bootstage record */
+enum bootstage_flags {
+	BOOTSTAGEF_ERROR	= 1 << 0,	/* Error record */
+	BOOTSTAGEF_ALLOC	= 1 << 1,	/* Allocate an id */
+};
+
+/* bootstate sub-IDs used for kernel and ramdisk ranges */
+enum {
+	BOOTSTAGE_SUB_FORMAT,
+	BOOTSTAGE_SUB_FORMAT_OK,
+	BOOTSTAGE_SUB_NO_UNIT_NAME,
+	BOOTSTAGE_SUB_UNIT_NAME,
+	BOOTSTAGE_SUB_SUBNODE,
+
+	BOOTSTAGE_SUB_CHECK,
+	BOOTSTAGE_SUB_HASH = 5,
+	BOOTSTAGE_SUB_CHECK_ARCH = 5,
+	BOOTSTAGE_SUB_CHECK_ALL,
+	BOOTSTAGE_SUB_GET_DATA,
+	BOOTSTAGE_SUB_CHECK_ALL_OK = 7,
+	BOOTSTAGE_SUB_GET_DATA_OK,
+	BOOTSTAGE_SUB_LOAD,
+};
+
+/*
+ * A list of boot stages that we know about. Each of these indicates the
+ * state that we are at, and the action that we are about to perform. For
+ * errors, we issue an error for an item when it fails. Therefore the
+ * normal sequence is:
+ *
+ * progress action1
+ * progress action2
+ * progress action3
+ *
+ * and an error condition where action 3 failed would be:
+ *
+ * progress action1
+ * progress action2
+ * progress action3
+ * error on action3
+ */
+enum bootstage_id {
+	BOOTSTAGE_ID_START = 0,
+	BOOTSTAGE_ID_CHECK_MAGIC,	/* Checking image magic */
+	BOOTSTAGE_ID_CHECK_HEADER,	/* Checking image header */
+	BOOTSTAGE_ID_CHECK_CHECKSUM,	/* Checking image checksum */
+	BOOTSTAGE_ID_CHECK_ARCH,	/* Checking architecture */
+
+	BOOTSTAGE_ID_CHECK_IMAGETYPE = 5,/* Checking image type */
+	BOOTSTAGE_ID_DECOMP_IMAGE,	/* Decompressing image */
+	BOOTSTAGE_ID_KERNEL_LOADED,	/* Kernel has been loaded */
+	BOOTSTAGE_ID_DECOMP_UNIMPL = 7,	/* Odd decompression algorithm */
+	BOOTSTAGE_ID_CHECK_BOOT_OS,	/* Calling OS-specific boot function */
+	BOOTSTAGE_ID_BOOT_OS_RETURNED,	/* Tried to boot OS, but it returned */
+	BOOTSTAGE_ID_CHECK_RAMDISK = 9,	/* Checking ram disk */
+
+	BOOTSTAGE_ID_RD_MAGIC,		/* Checking ram disk magic */
+	BOOTSTAGE_ID_RD_HDR_CHECKSUM,	/* Checking ram disk heder checksum */
+	BOOTSTAGE_ID_RD_CHECKSUM,	/* Checking ram disk checksum */
+	BOOTSTAGE_ID_COPY_RAMDISK = 12,	/* Copying ram disk into place */
+	BOOTSTAGE_ID_RAMDISK,		/* Checking for valid ramdisk */
+	BOOTSTAGE_ID_NO_RAMDISK,	/* No ram disk found (not an error) */
+
+	BOOTSTAGE_ID_RUN_OS	= 15,	/* Exiting U-Boot, entering OS */
+
+	BOOTSTAGE_ID_NEED_RESET = 30,
+	BOOTSTAGE_ID_POST_FAIL,		/* Post failure */
+	BOOTSTAGE_ID_POST_FAIL_R,	/* Post failure reported after reloc */
+
+	/*
+	 * This set is reported ony by x86, and the meaning is different. In
+	 * this case we are reporting completion of a particular stage.
+	 * This should probably change in he x86 code (which doesn't report
+	 * errors in any case), but discussion this can perhaps wait until we
+	 * have a generic board implementation.
+	 */
+	BOOTSTAGE_ID_BOARD_INIT_R,	/* We have relocated */
+	BOOTSTAGE_ID_BOARD_GLOBAL_DATA,	/* Global data is set up */
+
+	BOOTSTAGE_ID_BOARD_INIT_SEQ,	/* We completed the init sequence */
+	BOOTSTAGE_ID_BOARD_FLASH,	/* We have configured flash banks */
+	BOOTSTAGE_ID_BOARD_FLASH_37,	/* In case you didn't hear... */
+	BOOTSTAGE_ID_BOARD_ENV,		/* Environment is relocated & ready */
+	BOOTSTAGE_ID_BOARD_PCI,		/* PCI is up */
+
+	BOOTSTAGE_ID_BOARD_INTERRUPTS,	/* Exceptions / interrupts ready */
+	BOOTSTAGE_ID_BOARD_DONE,	/* Board init done, off to main loop */
+	/* ^^^ here ends the x86 sequence */
+
+	/* Boot stages related to loading a kernel from an IDE device */
+	BOOTSTAGE_ID_IDE_START = 41,
+	BOOTSTAGE_ID_IDE_ADDR,
+	BOOTSTAGE_ID_IDE_BOOT_DEVICE,
+	BOOTSTAGE_ID_IDE_TYPE,
+
+	BOOTSTAGE_ID_IDE_PART,
+	BOOTSTAGE_ID_IDE_PART_INFO,
+	BOOTSTAGE_ID_IDE_PART_TYPE,
+	BOOTSTAGE_ID_IDE_PART_READ,
+	BOOTSTAGE_ID_IDE_FORMAT,
+
+	BOOTSTAGE_ID_IDE_CHECKSUM,	/* 50 */
+	BOOTSTAGE_ID_IDE_READ,
+
+	/* Boot stages related to loading a kernel from an NAND device */
+	BOOTSTAGE_ID_NAND_PART,
+	BOOTSTAGE_ID_NAND_SUFFIX,
+	BOOTSTAGE_ID_NAND_BOOT_DEVICE,
+	BOOTSTAGE_ID_NAND_HDR_READ = 55,
+	BOOTSTAGE_ID_NAND_AVAILABLE = 55,
+	BOOTSTAGE_ID_NAND_TYPE = 57,
+	BOOTSTAGE_ID_NAND_READ,
+
+	/* Boot stages related to loading a kernel from an network device */
+	BOOTSTAGE_ID_NET_CHECKSUM = 60,
+	BOOTSTAGE_ID_NET_ETH_START = 64,
+	BOOTSTAGE_ID_NET_ETH_INIT,
+
+	BOOTSTAGE_ID_NET_START = 80,
+	BOOTSTAGE_ID_NET_NETLOOP_OK,
+	BOOTSTAGE_ID_NET_LOADED,
+	BOOTSTAGE_ID_NET_DONE_ERR,
+	BOOTSTAGE_ID_NET_DONE,
+
+	BOOTSTAGE_ID_FIT_FDT_START = 90,
+	/*
+	 * Boot stages related to loading a FIT image. Some of these are a
+	 * bit wonky.
+	 */
+	BOOTSTAGE_ID_FIT_KERNEL_START = 100,
+
+	BOOTSTAGE_ID_FIT_CONFIG = 110,
+	BOOTSTAGE_ID_FIT_TYPE,
+	BOOTSTAGE_ID_FIT_KERNEL_INFO,
+
+	BOOTSTAGE_ID_FIT_COMPRESSION,
+	BOOTSTAGE_ID_FIT_OS,
+	BOOTSTAGE_ID_FIT_LOADADDR,
+	BOOTSTAGE_ID_OVERWRITTEN,
+
+	/* Next 10 IDs used by BOOTSTAGE_SUB_... */
+	BOOTSTAGE_ID_FIT_RD_START = 120,	/* Ramdisk stages */
+
+	BOOTSTAGE_ID_IDE_FIT_READ = 140,
+	BOOTSTAGE_ID_IDE_FIT_READ_OK,
+
+	BOOTSTAGE_ID_NAND_FIT_READ = 150,
+	BOOTSTAGE_ID_NAND_FIT_READ_OK,
+
+	/*
+	 * These boot stages are new, higher level, and not directly related
+	 * to the old boot progress numbers. They are useful for recording
+	 * rough boot timing information.
+	 */
+	BOOTSTAGE_ID_AWAKE,
+	BOOTSTAGE_ID_START_SPL,
+	BOOTSTAGE_ID_START_UBOOT_F,
+	BOOTSTAGE_ID_START_UBOOT_R,
+	BOOTSTAGE_ID_USB_START,
+	BOOTSTAGE_ID_ETH_START,
+	BOOTSTAGE_ID_BOOTP_START,
+	BOOTSTAGE_ID_BOOTP_STOP,
+	BOOTSTAGE_ID_BOOTM_START,
+	BOOTSTAGE_ID_BOOTM_HANDOFF,
+	BOOTSTAGE_ID_MAIN_LOOP,
+	BOOTSTAGE_KERNELREAD_START,
+	BOOTSTAGE_KERNELREAD_STOP,
+	BOOTSTAGE_ID_BOARD_INIT,
+	BOOTSTAGE_ID_BOARD_INIT_DONE,
+
+	BOOTSTAGE_ID_CPU_AWAKE,
+	BOOTSTAGE_ID_MAIN_CPU_AWAKE,
+	BOOTSTAGE_ID_MAIN_CPU_READY,
+
+	BOOTSTAGE_ID_ACCUM_LCD,
+
+	/* a few spare for the user, from here */
+	BOOTSTAGE_ID_USER,
+	BOOTSTAGE_ID_COUNT = BOOTSTAGE_ID_USER + CONFIG_BOOTSTAGE_USER_COUNT,
+	BOOTSTAGE_ID_ALLOC,
+};
+
+/*
+ * Return the time since boot in microseconds, This is needed for bootstage
+ * and should be defined in CPU- or board-specific code. If undefined then
+ * millisecond resolution will be used (the standard get_timer()).
+ */
+ulong timer_get_boot_us(void);
+
+#if !defined(CONFIG_SPL_BUILD) && !defined(USE_HOSTCC)
+/*
+ * Board code can implement show_boot_progress() if needed.
+ *
+ * @param val	Progress state (enum bootstage_id), or -id if an error
+ *		has occurred.
+ */
+void show_boot_progress(int val);
+#else
+#define show_boot_progress(val) do {} while (0)
+#endif
+
+#if defined(CONFIG_BOOTSTAGE) && !defined(CONFIG_SPL_BUILD) && \
+	!defined(USE_HOSTCC)
+/* This is the full bootstage implementation */
+
+/**
+ * Relocate existing bootstage records
+ *
+ * Call this after relocation has happened and after malloc has been initted.
+ * We need to copy any pointers in bootstage records that were added pre-
+ * relocation, since memory can be overritten later.
+ * @return Always returns 0, to indicate success
+ */
+int bootstage_relocate(void);
+
+/**
+ * Add a new bootstage record
+ *
+ * @param id	Bootstage ID to use (ignored if flags & BOOTSTAGEF_ALLOC)
+ * @param name	Name of record, or NULL for none
+ * @param flags	Flags (BOOTSTAGEF_...)
+ * @param mark	Time to record in this record, in microseconds
+ */
+ulong bootstage_add_record(enum bootstage_id id, const char *name,
+			   int flags, ulong mark);
+
+/*
+ * Mark a time stamp for the current boot stage.
+ */
+ulong bootstage_mark(enum bootstage_id id);
+
+ulong bootstage_error(enum bootstage_id id);
+
+ulong bootstage_mark_name(enum bootstage_id id, const char *name);
+
+/**
+ * Mark a time stamp in the given function and line number
+ *
+ * See BOOTSTAGE_MARKER() for a convenient macro.
+ *
+ * @param file		Filename to record (NULL if none)
+ * @param func		Function name to record
+ * @param linenum	Line number to record
+ * @return recorded time stamp
+ */
+ulong bootstage_mark_code(const char *file, const char *func,
+			  int linenum);
+
+/**
+ * Mark the start of a bootstage activity. The end will be marked later with
+ * bootstage_accum() and at that point we accumulate the time taken. Calling
+ * this function turns the given id into a accumulator rather than and
+ * absolute mark in time. Accumulators record the total amount of time spent
+ * in an activty during boot.
+ *
+ * @param id	Bootstage id to record this timestamp against
+ * @param name	Textual name to display for this id in the report (maybe NULL)
+ * @return start timestamp in microseconds
+ */
+uint32_t bootstage_start(enum bootstage_id id, const char *name);
+
+/**
+ * Mark the end of a bootstage activity
+ *
+ * After previously marking the start of an activity with bootstage_start(),
+ * call this function to mark the end. You can call these functions in pairs
+ * as many times as you like.
+ *
+ * @param id	Bootstage id to record this timestamp against
+ * @return time spent in this iteration of the activity (i.e. the time now
+ *		less the start time recorded in the last bootstage_start() call
+ *		with this id.
+ */
+uint32_t bootstage_accum(enum bootstage_id id);
+
+/* Print a report about boot time */
+void bootstage_report(void);
+
+/**
+ * Add bootstage information to the device tree
+ *
+ * @return 0 if ok, -ve on error
+ */
+int bootstage_fdt_add_report(void);
+
+/*
+ * Stash bootstage data into memory
+ *
+ * @param base	Base address of memory buffer
+ * @param size	Size of memory buffer
+ * @return 0 if stashed ok, -1 if out of space
+ */
+int bootstage_stash(void *base, int size);
+
+/**
+ * Read bootstage data from memory
+ *
+ * Bootstage data is read from memory and placed in the bootstage table
+ * in the user records.
+ *
+ * @param base	Base address of memory buffer
+ * @param size	Size of memory buffer (-1 if unknown)
+ * @return 0 if unstashed ok, -1 if bootstage info not found, or out of space
+ */
+int bootstage_unstash(void *base, int size);
+
+#else
+static inline ulong bootstage_add_record(enum bootstage_id id,
+		const char *name, int flags, ulong mark)
+{
+	return 0;
+}
+
+/*
+ * This is a dummy implementation which just calls show_boot_progress(),
+ * and won't even do that unless CONFIG_SHOW_BOOT_PROGRESS is defined
+ */
+
+static inline int bootstage_relocate(void)
+{
+	return 0;
+}
+
+static inline ulong bootstage_mark(enum bootstage_id id)
+{
+	show_boot_progress(id);
+	return 0;
+}
+
+static inline ulong bootstage_error(enum bootstage_id id)
+{
+	show_boot_progress(-id);
+	return 0;
+}
+
+static inline ulong bootstage_mark_name(enum bootstage_id id, const char *name)
+{
+	show_boot_progress(id);
+	return 0;
+}
+
+static inline ulong bootstage_mark_code(const char *file, const char *func,
+					int linenum)
+{
+	return 0;
+}
+
+static inline uint32_t bootstage_start(enum bootstage_id id, const char *name)
+{
+	return 0;
+}
+
+static inline uint32_t bootstage_accum(enum bootstage_id id)
+{
+	return 0;
+}
+
+static inline int bootstage_stash(void *base, int size)
+{
+	return 0;	/* Pretend to succeed */
+}
+
+static inline int bootstage_unstash(void *base, int size)
+{
+	return 0;	/* Pretend to succeed */
+}
+#endif /* CONFIG_BOOTSTAGE */
+
+/* Helper macro for adding a bootstage to a line of code */
+#define BOOTSTAGE_MARKER()	\
+		bootstage_mark_code(__FILE__, __func__, __LINE__)
+
+#endif
diff --git a/qemu/roms/u-boot/include/bouncebuf.h b/qemu/roms/u-boot/include/bouncebuf.h
new file mode 100644
index 000000000..5ffa99bc1
--- /dev/null
+++ b/qemu/roms/u-boot/include/bouncebuf.h
@@ -0,0 +1,72 @@
+/*
+ * Generic bounce buffer implementation
+ *
+ * Copyright (C) 2012 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __INCLUDE_BOUNCEBUF_H__
+#define __INCLUDE_BOUNCEBUF_H__
+
+#include <linux/types.h>
+
+/*
+ * GEN_BB_READ -- Data are read from the buffer eg. by DMA hardware.
+ * The source buffer is copied into the bounce buffer (if unaligned, otherwise
+ * the source buffer is used directly) upon start() call, then the operation
+ * requiring the aligned transfer happens, then the bounce buffer is lost upon
+ * stop() call.
+ */
+#define GEN_BB_READ	(1 << 0)
+/*
+ * GEN_BB_WRITE -- Data are written into the buffer eg. by DMA hardware.
+ * The source buffer starts in an undefined state upon start() call, then the
+ * operation requiring the aligned transfer happens, then the bounce buffer is
+ * copied into the destination buffer (if unaligned, otherwise destination
+ * buffer is used directly) upon stop() call.
+ */
+#define GEN_BB_WRITE	(1 << 1)
+/*
+ * GEN_BB_RW -- Data are read and written into the buffer eg. by DMA hardware.
+ * The source buffer is copied into the bounce buffer (if unaligned, otherwise
+ * the source buffer is used directly) upon start() call, then the  operation
+ * requiring the aligned transfer happens, then the bounce buffer is  copied
+ * into the destination buffer (if unaligned, otherwise destination buffer is
+ * used directly) upon stop() call.
+ */
+#define GEN_BB_RW	(GEN_BB_READ | GEN_BB_WRITE)
+
+struct bounce_buffer {
+	/* Copy of data parameter passed to start() */
+	void *user_buffer;
+	/*
+	 * DMA-aligned buffer. This field is always set to the value that
+	 * should be used for DMA; either equal to .user_buffer, or to a
+	 * freshly allocated aligned buffer.
+	 */
+	void *bounce_buffer;
+	/* Copy of len parameter passed to start() */
+	size_t len;
+	/* DMA-aligned buffer length */
+	size_t len_aligned;
+	/* Copy of flags parameter passed to start() */
+	unsigned int flags;
+};
+
+/**
+ * bounce_buffer_start() -- Start the bounce buffer session
+ * state:	stores state passed between bounce_buffer_{start,stop}
+ * data:	pointer to buffer to be aligned
+ * len:		length of the buffer
+ * flags:	flags describing the transaction, see above.
+ */
+int bounce_buffer_start(struct bounce_buffer *state, void *data,
+			size_t len, unsigned int flags);
+/**
+ * bounce_buffer_stop() -- Finish the bounce buffer session
+ * state:	stores state passed between bounce_buffer_{start,stop}
+ */
+int bounce_buffer_stop(struct bounce_buffer *state);
+
+#endif
diff --git a/qemu/roms/u-boot/include/bus_vcxk.h b/qemu/roms/u-boot/include/bus_vcxk.h
new file mode 100644
index 000000000..131f33835
--- /dev/null
+++ b/qemu/roms/u-boot/include/bus_vcxk.h
@@ -0,0 +1,20 @@
+/*
+ * (C) Copyright 2005-2009
+ * Jens Scharsig @ BuS Elektronik GmbH & Co. KG, <esw@bus-elektronik.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __BUS_VCXK_H_
+#define __BUS_VCXK_H_
+
+extern int vcxk_init(unsigned long width, unsigned long height);
+extern void vcxk_setpixel(int x, int y, unsigned long color);
+extern int vcxk_acknowledge_wait(void);
+extern int vcxk_request(void);
+extern void vcxk_loadimage(ulong source);
+extern int vcxk_display_bitmap(ulong addr, int x, int y);
+extern void vcxk_setbrightness(unsigned int side, short brightness);
+extern int video_display_bitmap(ulong addr, int x, int y);
+
+#endif
diff --git a/qemu/roms/u-boot/include/bzlib.h b/qemu/roms/u-boot/include/bzlib.h
new file mode 100644
index 000000000..2d864d56b
--- /dev/null
+++ b/qemu/roms/u-boot/include/bzlib.h
@@ -0,0 +1,329 @@
+/*
+ * This file is a modified version of bzlib.h from the bzip2-1.0.2
+ * distribution which can be found at http://sources.redhat.com/bzip2/
+ */
+
+/*-------------------------------------------------------------*/
+/*--- Public header file for the library.                   ---*/
+/*---                                               bzlib.h ---*/
+/*-------------------------------------------------------------*/
+
+/*--
+  This file is a part of bzip2 and/or libbzip2, a program and
+  library for lossless, block-sorting data compression.
+
+  Copyright (C) 1996-2002 Julian R Seward.  All rights reserved.
+
+  Redistribution and use in source and binary forms, with or without
+  modification, are permitted provided that the following conditions
+  are met:
+
+  1. Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+
+  2. The origin of this software must not be misrepresented; you must
+     not claim that you wrote the original software.  If you use this
+     software in a product, an acknowledgment in the product
+     documentation would be appreciated but is not required.
+
+  3. Altered source versions must be plainly marked as such, and must
+     not be misrepresented as being the original software.
+
+  4. The name of the author may not be used to endorse or promote
+     products derived from this software without specific prior written
+     permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+  OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+  WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+  DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+  GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+  WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+  SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+  Julian Seward, Cambridge, UK.
+  jseward@acm.org
+  bzip2/libbzip2 version 1.0 of 21 March 2000
+
+  This program is based on (at least) the work of:
+     Mike Burrows
+     David Wheeler
+     Peter Fenwick
+     Alistair Moffat
+     Radford Neal
+     Ian H. Witten
+     Robert Sedgewick
+     Jon L. Bentley
+
+  For more information on these sources, see the manual.
+--*/
+
+
+#ifndef _BZLIB_H
+#define _BZLIB_H
+
+/* Configure for U-Boot environment */
+#define BZ_NO_STDIO
+#define BZ_NO_COMPRESS
+/* End of configuration for U-Boot environment */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define BZ_RUN               0
+#define BZ_FLUSH             1
+#define BZ_FINISH            2
+
+#define BZ_OK                0
+#define BZ_RUN_OK            1
+#define BZ_FLUSH_OK          2
+#define BZ_FINISH_OK         3
+#define BZ_STREAM_END        4
+#define BZ_SEQUENCE_ERROR    (-1)
+#define BZ_PARAM_ERROR       (-2)
+#define BZ_MEM_ERROR         (-3)
+#define BZ_DATA_ERROR        (-4)
+#define BZ_DATA_ERROR_MAGIC  (-5)
+#define BZ_IO_ERROR          (-6)
+#define BZ_UNEXPECTED_EOF    (-7)
+#define BZ_OUTBUFF_FULL      (-8)
+#define BZ_CONFIG_ERROR      (-9)
+
+typedef
+   struct {
+      char *next_in;
+      unsigned int avail_in;
+      unsigned int total_in_lo32;
+      unsigned int total_in_hi32;
+
+      char *next_out;
+      unsigned int avail_out;
+      unsigned int total_out_lo32;
+      unsigned int total_out_hi32;
+
+      void *state;
+
+      void *(*bzalloc)(void *,int,int);
+      void (*bzfree)(void *,void *);
+      void *opaque;
+   }
+   bz_stream;
+
+
+#ifndef BZ_IMPORT
+#define BZ_EXPORT
+#endif
+
+#ifdef _WIN32
+#   include <windows.h>
+#   ifdef small
+      /* windows.h define small to char */
+#      undef small
+#   endif
+#   ifdef BZ_EXPORT
+#   define BZ_API(func) WINAPI func
+#   define BZ_EXTERN extern
+#   else
+   /* import windows dll dynamically */
+#   define BZ_API(func) (WINAPI * func)
+#   define BZ_EXTERN
+#   endif
+#else
+#   define BZ_API(func) func
+#   define BZ_EXTERN extern
+#endif
+
+
+/*-- Core (low-level) library functions --*/
+
+BZ_EXTERN int BZ_API(BZ2_bzCompressInit) (
+      bz_stream* strm,
+      int        blockSize100k,
+      int        verbosity,
+      int        workFactor
+   );
+
+BZ_EXTERN int BZ_API(BZ2_bzCompress) (
+      bz_stream* strm,
+      int action
+   );
+
+BZ_EXTERN int BZ_API(BZ2_bzCompressEnd) (
+      bz_stream* strm
+   );
+
+BZ_EXTERN int BZ_API(BZ2_bzDecompressInit) (
+      bz_stream *strm,
+      int       verbosity,
+      int       small
+   );
+
+BZ_EXTERN int BZ_API(BZ2_bzDecompress) (
+      bz_stream* strm
+   );
+
+BZ_EXTERN int BZ_API(BZ2_bzDecompressEnd) (
+      bz_stream *strm
+   );
+
+
+/*-- High(er) level library functions --*/
+
+#ifndef BZ_NO_STDIO
+#define BZ_MAX_UNUSED 5000
+
+/* Need a definitition for FILE */
+#include <stdio.h>
+
+typedef void BZFILE;
+
+BZ_EXTERN BZFILE* BZ_API(BZ2_bzReadOpen) (
+      int*  bzerror,
+      FILE* f,
+      int   verbosity,
+      int   small,
+      void* unused,
+      int   nUnused
+   );
+
+BZ_EXTERN void BZ_API(BZ2_bzReadClose) (
+      int*    bzerror,
+      BZFILE* b
+   );
+
+BZ_EXTERN void BZ_API(BZ2_bzReadGetUnused) (
+      int*    bzerror,
+      BZFILE* b,
+      void**  unused,
+      int*    nUnused
+   );
+
+BZ_EXTERN int BZ_API(BZ2_bzRead) (
+      int*    bzerror,
+      BZFILE* b,
+      void*   buf,
+      int     len
+   );
+
+BZ_EXTERN BZFILE* BZ_API(BZ2_bzWriteOpen) (
+      int*  bzerror,
+      FILE* f,
+      int   blockSize100k,
+      int   verbosity,
+      int   workFactor
+   );
+
+BZ_EXTERN void BZ_API(BZ2_bzWrite) (
+      int*    bzerror,
+      BZFILE* b,
+      void*   buf,
+      int     len
+   );
+
+BZ_EXTERN void BZ_API(BZ2_bzWriteClose) (
+      int*          bzerror,
+      BZFILE*       b,
+      int           abandon,
+      unsigned int* nbytes_in,
+      unsigned int* nbytes_out
+   );
+
+BZ_EXTERN void BZ_API(BZ2_bzWriteClose64) (
+      int*          bzerror,
+      BZFILE*       b,
+      int           abandon,
+      unsigned int* nbytes_in_lo32,
+      unsigned int* nbytes_in_hi32,
+      unsigned int* nbytes_out_lo32,
+      unsigned int* nbytes_out_hi32
+   );
+#endif
+
+
+/*-- Utility functions --*/
+
+BZ_EXTERN int BZ_API(BZ2_bzBuffToBuffCompress) (
+      char*         dest,
+      unsigned int* destLen,
+      char*         source,
+      unsigned int  sourceLen,
+      int           blockSize100k,
+      int           verbosity,
+      int           workFactor
+   );
+
+BZ_EXTERN int BZ_API(BZ2_bzBuffToBuffDecompress) (
+      char*         dest,
+      unsigned int* destLen,
+      char*         source,
+      unsigned int  sourceLen,
+      int           small,
+      int           verbosity
+   );
+
+
+/*--
+   Code contributed by Yoshioka Tsuneo
+   (QWF00133@niftyserve.or.jp/tsuneo-y@is.aist-nara.ac.jp),
+   to support better zlib compatibility.
+   This code is not _officially_ part of libbzip2 (yet);
+   I haven't tested it, documented it, or considered the
+   threading-safeness of it.
+   If this code breaks, please contact both Yoshioka and me.
+--*/
+
+BZ_EXTERN const char * BZ_API(BZ2_bzlibVersion) (
+      void
+   );
+
+#ifndef BZ_NO_STDIO
+BZ_EXTERN BZFILE * BZ_API(BZ2_bzopen) (
+      const char *path,
+      const char *mode
+   );
+
+BZ_EXTERN BZFILE * BZ_API(BZ2_bzdopen) (
+      int        fd,
+      const char *mode
+   );
+
+BZ_EXTERN int BZ_API(BZ2_bzread) (
+      BZFILE* b,
+      void* buf,
+      int len
+   );
+
+BZ_EXTERN int BZ_API(BZ2_bzwrite) (
+      BZFILE* b,
+      void*   buf,
+      int     len
+   );
+
+BZ_EXTERN int BZ_API(BZ2_bzflush) (
+      BZFILE* b
+   );
+
+BZ_EXTERN void BZ_API(BZ2_bzclose) (
+      BZFILE* b
+   );
+
+BZ_EXTERN const char * BZ_API(BZ2_bzerror) (
+      BZFILE *b,
+      int    *errnum
+   );
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/*-------------------------------------------------------------*/
+/*--- end                                           bzlib.h ---*/
+/*-------------------------------------------------------------*/
diff --git a/qemu/roms/u-boot/include/cbfs.h b/qemu/roms/u-boot/include/cbfs.h
new file mode 100644
index 000000000..f50280107
--- /dev/null
+++ b/qemu/roms/u-boot/include/cbfs.h
@@ -0,0 +1,168 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CBFS_H
+#define __CBFS_H
+
+#include <compiler.h>
+#include <linux/compiler.h>
+
+enum cbfs_result {
+	CBFS_SUCCESS = 0,
+	CBFS_NOT_INITIALIZED,
+	CBFS_BAD_HEADER,
+	CBFS_BAD_FILE,
+	CBFS_FILE_NOT_FOUND
+};
+
+enum cbfs_filetype {
+	CBFS_TYPE_STAGE = 0x10,
+	CBFS_TYPE_PAYLOAD = 0x20,
+	CBFS_TYPE_OPTIONROM = 0x30,
+	CBFS_TYPE_BOOTSPLASH = 0x40,
+	CBFS_TYPE_RAW = 0x50,
+	CBFS_TYPE_VSA = 0x51,
+	CBFS_TYPE_MBI = 0x52,
+	CBFS_TYPE_MICROCODE = 0x53,
+	CBFS_COMPONENT_CMOS_DEFAULT = 0xaa,
+	CBFS_COMPONENT_CMOS_LAYOUT = 0x01aa
+};
+
+struct cbfs_header {
+	u32 magic;
+	u32 version;
+	u32 rom_size;
+	u32 boot_block_size;
+	u32 align;
+	u32 offset;
+	u32 pad[2];
+} __packed;
+
+struct cbfs_fileheader {
+	u8 magic[8];
+	u32 len;
+	u32 type;
+	u32 checksum;
+	u32 offset;
+} __packed;
+
+struct cbfs_cachenode {
+	struct cbfs_cachenode *next;
+	u32 type;
+	void *data;
+	u32 data_length;
+	char *name;
+	u32 name_length;
+	u32 checksum;
+} __packed;
+
+extern enum cbfs_result file_cbfs_result;
+
+/**
+ * file_cbfs_error() - Return a string describing the most recent error
+ * condition.
+ *
+ * @return A pointer to the constant string.
+ */
+const char *file_cbfs_error(void);
+
+/**
+ * file_cbfs_init() - Initialize the CBFS driver and load metadata into RAM.
+ *
+ * @end_of_rom: Points to the end of the ROM the CBFS should be read
+ *                      from.
+ */
+void file_cbfs_init(uintptr_t end_of_rom);
+
+/**
+ * file_cbfs_get_header() - Get the header structure for the current CBFS.
+ *
+ * @return A pointer to the constant structure, or NULL if there is none.
+ */
+const struct cbfs_header *file_cbfs_get_header(void);
+
+/**
+ * file_cbfs_get_first() - Get a handle for the first file in CBFS.
+ *
+ * @return A handle for the first file in CBFS, NULL on error.
+ */
+const struct cbfs_cachenode *file_cbfs_get_first(void);
+
+/**
+ * file_cbfs_get_next() - Get a handle to the file after this one in CBFS.
+ *
+ * @file:		A pointer to the handle to advance.
+ */
+void file_cbfs_get_next(const struct cbfs_cachenode **file);
+
+/**
+ * file_cbfs_find() - Find a file with a particular name in CBFS.
+ *
+ * @name:		The name to search for.
+ *
+ * @return A handle to the file, or NULL on error.
+ */
+const struct cbfs_cachenode *file_cbfs_find(const char *name);
+
+
+/***************************************************************************/
+/* All of the functions below can be used without first initializing CBFS. */
+/***************************************************************************/
+
+/**
+ * file_cbfs_find_uncached() - Find a file with a particular name in CBFS
+ * without using the heap.
+ *
+ * @end_of_rom:		Points to the end of the ROM the CBFS should be read
+ *                      from.
+ * @name:		The name to search for.
+ *
+ * @return A handle to the file, or NULL on error.
+ */
+const struct cbfs_cachenode *file_cbfs_find_uncached(uintptr_t end_of_rom,
+						     const char *name);
+
+/**
+ * file_cbfs_name() - Get the name of a file in CBFS.
+ *
+ * @file:		The handle to the file.
+ *
+ * @return The name of the file, NULL on error.
+ */
+const char *file_cbfs_name(const struct cbfs_cachenode *file);
+
+/**
+ * file_cbfs_size() - Get the size of a file in CBFS.
+ *
+ * @file:		The handle to the file.
+ *
+ * @return The size of the file, zero on error.
+ */
+u32 file_cbfs_size(const struct cbfs_cachenode *file);
+
+/**
+ * file_cbfs_type() - Get the type of a file in CBFS.
+ *
+ * @file:		The handle to the file.
+ *
+ * @return The type of the file, zero on error.
+ */
+u32 file_cbfs_type(const struct cbfs_cachenode *file);
+
+/**
+ * file_cbfs_read() - Read a file from CBFS into RAM
+ *
+ * @file:		A handle to the file to read.
+ * @buffer:		Where to read it into memory.
+ * @maxsize:		Maximum number of bytes to read
+ *
+ * @return If positive or zero, the number of characters read. If negative, an
+ *	   error occurred.
+ */
+long file_cbfs_read(const struct cbfs_cachenode *file, void *buffer,
+		    unsigned long maxsize);
+
+#endif /* __CBFS_H */
diff --git a/qemu/roms/u-boot/include/circbuf.h b/qemu/roms/u-boot/include/circbuf.h
new file mode 100644
index 000000000..34d0f85f2
--- /dev/null
+++ b/qemu/roms/u-boot/include/circbuf.h
@@ -0,0 +1,27 @@
+/*
+ * (C) Copyright 2003
+ * Gerry Hamel, geh@ti.com, Texas Instruments
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CIRCBUF_H__
+#define __CIRCBUF_H__
+
+typedef struct circbuf {
+	unsigned int size;	/* current number of bytes held */
+	unsigned int totalsize; /* number of bytes allocated */
+
+	char *top;		/* pointer to current buffer start */
+	char *tail;		/* pointer to space for next element */
+
+	char *data;		/* all data */
+	char *end;		/* end of data buffer */
+} circbuf_t;
+
+int buf_init (circbuf_t * buf, unsigned int size);
+int buf_free (circbuf_t * buf);
+int buf_pop (circbuf_t * buf, char *dest, unsigned int len);
+int buf_push (circbuf_t * buf, const char *src, unsigned int len);
+
+#endif
diff --git a/qemu/roms/u-boot/include/clk.h b/qemu/roms/u-boot/include/clk.h
new file mode 100644
index 000000000..df4570c6f
--- /dev/null
+++ b/qemu/roms/u-boot/include/clk.h
@@ -0,0 +1,6 @@
+#ifndef _CLK_H_
+#define _CLK_H_
+
+int soc_clk_dump(void);
+
+#endif /* _CLK_H_ */
diff --git a/qemu/roms/u-boot/include/cmd_spl.h b/qemu/roms/u-boot/include/cmd_spl.h
new file mode 100644
index 000000000..c7615debf
--- /dev/null
+++ b/qemu/roms/u-boot/include/cmd_spl.h
@@ -0,0 +1,15 @@
+/* Copyright (C) 2011
+ * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _NAND_SPL_H_
+#define	_NAND_SPL_H_
+
+#define SPL_EXPORT	(0x00000001)
+
+#define SPL_EXPORT_FDT		(0x00000001)
+#define SPL_EXPORT_ATAGS	(0x00000002)
+#define SPL_EXPORT_LAST		SPL_EXPORT_ATAGS
+
+#endif /* _NAND_SPL_H_ */
diff --git a/qemu/roms/u-boot/include/command.h b/qemu/roms/u-boot/include/command.h
new file mode 100644
index 000000000..d3f700fc3
--- /dev/null
+++ b/qemu/roms/u-boot/include/command.h
@@ -0,0 +1,184 @@
+/*
+ * (C) Copyright 2000-2009
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ *  Definitions for Command Processor
+ */
+#ifndef __COMMAND_H
+#define __COMMAND_H
+
+#include <config.h>
+#include <linker_lists.h>
+
+#ifndef NULL
+#define NULL	0
+#endif
+
+/* Default to a width of 8 characters for help message command width */
+#ifndef CONFIG_SYS_HELP_CMD_WIDTH
+#define CONFIG_SYS_HELP_CMD_WIDTH	8
+#endif
+
+#ifndef	__ASSEMBLY__
+/*
+ * Monitor Command Table
+ */
+
+struct cmd_tbl_s {
+	char		*name;		/* Command Name			*/
+	int		maxargs;	/* maximum number of arguments	*/
+	int		repeatable;	/* autorepeat allowed?		*/
+					/* Implementation function	*/
+	int		(*cmd)(struct cmd_tbl_s *, int, int, char * const []);
+	char		*usage;		/* Usage message	(short)	*/
+#ifdef	CONFIG_SYS_LONGHELP
+	char		*help;		/* Help  message	(long)	*/
+#endif
+#ifdef CONFIG_AUTO_COMPLETE
+	/* do auto completion on the arguments */
+	int		(*complete)(int argc, char * const argv[], char last_char, int maxv, char *cmdv[]);
+#endif
+};
+
+typedef struct cmd_tbl_s	cmd_tbl_t;
+
+
+#if defined(CONFIG_CMD_RUN)
+extern int do_run(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+#endif
+
+/* common/command.c */
+int _do_help (cmd_tbl_t *cmd_start, int cmd_items, cmd_tbl_t * cmdtp, int
+	      flag, int argc, char * const argv[]);
+cmd_tbl_t *find_cmd(const char *cmd);
+cmd_tbl_t *find_cmd_tbl (const char *cmd, cmd_tbl_t *table, int table_len);
+
+extern int cmd_usage(const cmd_tbl_t *cmdtp);
+
+#ifdef CONFIG_AUTO_COMPLETE
+extern int var_complete(int argc, char * const argv[], char last_char, int maxv, char *cmdv[]);
+extern int cmd_auto_complete(const char *const prompt, char *buf, int *np, int *colp);
+#endif
+
+/**
+ * cmd_process_error() - report and process a possible error
+ *
+ * @cmdtp: Command which caused the error
+ * @err: Error code (0 if none, -ve for error, like -EIO)
+ * @return 0 if there is not error, 1 (CMD_RET_FAILURE) if an error is found
+ */
+int cmd_process_error(cmd_tbl_t *cmdtp, int err);
+
+/*
+ * Monitor Command
+ *
+ * All commands use a common argument format:
+ *
+ * void function (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+ */
+
+#if defined(CONFIG_CMD_MEMORY)		\
+	|| defined(CONFIG_CMD_I2C)	\
+	|| defined(CONFIG_CMD_ITEST)	\
+	|| defined(CONFIG_CMD_PCI)	\
+	|| defined(CONFIG_CMD_PORTIO)
+#define CMD_DATA_SIZE
+extern int cmd_get_data_size(char* arg, int default_size);
+#endif
+
+#ifdef CONFIG_CMD_BOOTD
+extern int do_bootd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+#endif
+#ifdef CONFIG_CMD_BOOTM
+extern int do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+extern int bootm_maybe_autostart(cmd_tbl_t *cmdtp, const char *cmd);
+#else
+static inline int bootm_maybe_autostart(cmd_tbl_t *cmdtp, const char *cmd)
+{
+	return 0;
+}
+#endif
+
+extern int do_bootz(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+
+extern int common_diskboot(cmd_tbl_t *cmdtp, const char *intf, int argc,
+			   char *const argv[]);
+
+extern int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+
+/*
+ * Error codes that commands return to cmd_process(). We use the standard 0
+ * and 1 for success and failure, but add one more case - failure with a
+ * request to call cmd_usage(). But the cmd_process() function handles
+ * CMD_RET_USAGE itself and after calling cmd_usage() it will return 1.
+ * This is just a convenience for commands to avoid them having to call
+ * cmd_usage() all over the place.
+ */
+enum command_ret_t {
+	CMD_RET_SUCCESS,	/* 0 = Success */
+	CMD_RET_FAILURE,	/* 1 = Failure */
+	CMD_RET_USAGE = -1,	/* Failure, please report 'usage' error */
+};
+
+/**
+ * Process a command with arguments. We look up the command and execute it
+ * if valid. Otherwise we print a usage message.
+ *
+ * @param flag		Some flags normally 0 (see CMD_FLAG_.. above)
+ * @param argc		Number of arguments (arg 0 must be the command text)
+ * @param argv		Arguments
+ * @param repeatable	This function sets this to 0 if the command is not
+ *			repeatable. If the command is repeatable, the value
+ *			is left unchanged.
+ * @param ticks		If ticks is not null, this function set it to the
+ *			number of ticks the command took to complete.
+ * @return 0 if the command succeeded, 1 if it failed
+ */
+int cmd_process(int flag, int argc, char * const argv[],
+			       int *repeatable, unsigned long *ticks);
+
+#endif	/* __ASSEMBLY__ */
+
+/*
+ * Command Flags:
+ */
+#define CMD_FLAG_REPEAT		0x0001	/* repeat last command		*/
+#define CMD_FLAG_BOOTD		0x0002	/* command is from bootd	*/
+
+#ifdef CONFIG_AUTO_COMPLETE
+# define _CMD_COMPLETE(x) x,
+#else
+# define _CMD_COMPLETE(x)
+#endif
+#ifdef CONFIG_SYS_LONGHELP
+# define _CMD_HELP(x) x,
+#else
+# define _CMD_HELP(x)
+#endif
+
+#define U_BOOT_CMD_MKENT_COMPLETE(_name, _maxargs, _rep, _cmd,		\
+				_usage, _help, _comp)			\
+		{ #_name, _maxargs, _rep, _cmd, _usage,			\
+			_CMD_HELP(_help) _CMD_COMPLETE(_comp) }
+
+#define U_BOOT_CMD_MKENT(_name, _maxargs, _rep, _cmd, _usage, _help)	\
+	U_BOOT_CMD_MKENT_COMPLETE(_name, _maxargs, _rep, _cmd,		\
+					_usage, _help, NULL)
+
+#define U_BOOT_CMD_COMPLETE(_name, _maxargs, _rep, _cmd, _usage, _help, _comp) \
+	ll_entry_declare(cmd_tbl_t, _name, cmd) =			\
+		U_BOOT_CMD_MKENT_COMPLETE(_name, _maxargs, _rep, _cmd,	\
+						_usage, _help, _comp);
+
+#define U_BOOT_CMD(_name, _maxargs, _rep, _cmd, _usage, _help)		\
+	U_BOOT_CMD_COMPLETE(_name, _maxargs, _rep, _cmd, _usage, _help, NULL)
+
+#if defined(CONFIG_NEEDS_MANUAL_RELOC)
+void fixup_cmdtable(cmd_tbl_t *cmdtp, int size);
+#endif
+
+#endif	/* __COMMAND_H */
diff --git a/qemu/roms/u-boot/include/common.h b/qemu/roms/u-boot/include/common.h
new file mode 100644
index 000000000..13e5dc74e
--- /dev/null
+++ b/qemu/roms/u-boot/include/common.h
@@ -0,0 +1,1077 @@
+/*
+ * (C) Copyright 2000-2009
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __COMMON_H_
+#define __COMMON_H_	1
+
+#ifndef __ASSEMBLY__		/* put C only stuff in this section */
+
+typedef unsigned char		uchar;
+typedef volatile unsigned long	vu_long;
+typedef volatile unsigned short vu_short;
+typedef volatile unsigned char	vu_char;
+
+#include <config.h>
+#include <asm-offsets.h>
+#include <linux/bitops.h>
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/stringify.h>
+#include <asm/ptrace.h>
+#include <stdarg.h>
+#if defined(CONFIG_PCI) && defined(CONFIG_4xx)
+#include <pci.h>
+#endif
+#if defined(CONFIG_8xx)
+#include <asm/8xx_immap.h>
+#if defined(CONFIG_MPC852)	|| defined(CONFIG_MPC852T)	|| \
+    defined(CONFIG_MPC859)	|| defined(CONFIG_MPC859T)	|| \
+    defined(CONFIG_MPC859DSL)	|| \
+    defined(CONFIG_MPC866)	|| defined(CONFIG_MPC866T)	|| \
+    defined(CONFIG_MPC866P)
+# define CONFIG_MPC866_FAMILY 1
+#elif defined(CONFIG_MPC870) \
+   || defined(CONFIG_MPC875) \
+   || defined(CONFIG_MPC880) \
+   || defined(CONFIG_MPC885)
+# define CONFIG_MPC885_FAMILY   1
+#endif
+#if   defined(CONFIG_MPC860)	   \
+   || defined(CONFIG_MPC860T)	   \
+   || defined(CONFIG_MPC866_FAMILY) \
+   || defined(CONFIG_MPC885_FAMILY)
+# define CONFIG_MPC86x 1
+#endif
+#elif defined(CONFIG_5xx)
+#include <asm/5xx_immap.h>
+#elif defined(CONFIG_MPC5xxx)
+#include <mpc5xxx.h>
+#elif defined(CONFIG_MPC512X)
+#include <asm/immap_512x.h>
+#elif defined(CONFIG_MPC8260)
+#if   defined(CONFIG_MPC8247) \
+   || defined(CONFIG_MPC8248) \
+   || defined(CONFIG_MPC8271) \
+   || defined(CONFIG_MPC8272)
+#define CONFIG_MPC8272_FAMILY	1
+#endif
+#include <asm/immap_8260.h>
+#endif
+#ifdef CONFIG_MPC86xx
+#include <mpc86xx.h>
+#include <asm/immap_86xx.h>
+#endif
+#ifdef CONFIG_MPC85xx
+#include <mpc85xx.h>
+#include <asm/immap_85xx.h>
+#endif
+#ifdef CONFIG_MPC83xx
+#include <mpc83xx.h>
+#include <asm/immap_83xx.h>
+#endif
+#ifdef	CONFIG_4xx
+#include <asm/ppc4xx.h>
+#endif
+#ifdef CONFIG_HYMOD
+#include <board/hymod/hymod.h>
+#endif
+#ifdef CONFIG_ARM
+#define asmlinkage	/* nothing */
+#endif
+#ifdef CONFIG_BLACKFIN
+#include <asm/blackfin.h>
+#endif
+#ifdef CONFIG_SOC_DA8XX
+#include <asm/arch/hardware.h>
+#endif
+
+#include <part.h>
+#include <flash.h>
+#include <image.h>
+
+#ifdef __LP64__
+#define CONFIG_SYS_SUPPORT_64BIT_DATA
+#endif
+
+#ifdef DEBUG
+#define _DEBUG	1
+#else
+#define _DEBUG	0
+#endif
+
+/*
+ * Output a debug text when condition "cond" is met. The "cond" should be
+ * computed by a preprocessor in the best case, allowing for the best
+ * optimization.
+ */
+#define debug_cond(cond, fmt, args...)		\
+	do {					\
+		if (cond)			\
+			printf(fmt, ##args);	\
+	} while (0)
+
+#define debug(fmt, args...)			\
+	debug_cond(_DEBUG, fmt, ##args)
+
+/*
+ * An assertion is run-time check done in debug mode only. If DEBUG is not
+ * defined then it is skipped. If DEBUG is defined and the assertion fails,
+ * then it calls panic*( which may or may not reset/halt U-Boot (see
+ * CONFIG_PANIC_HANG), It is hoped that all failing assertions are found
+ * before release, and after release it is hoped that they don't matter. But
+ * in any case these failing assertions cannot be fixed with a reset (which
+ * may just do the same assertion again).
+ */
+void __assert_fail(const char *assertion, const char *file, unsigned line,
+		   const char *function);
+#define assert(x) \
+	({ if (!(x) && _DEBUG) \
+		__assert_fail(#x, __FILE__, __LINE__, __func__); })
+
+#define error(fmt, args...) do {					\
+		printf("ERROR: " fmt "\nat %s:%d/%s()\n",		\
+			##args, __FILE__, __LINE__, __func__);		\
+} while (0)
+
+#ifndef BUG
+#define BUG() do { \
+	printf("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __FUNCTION__); \
+	panic("BUG!"); \
+} while (0)
+#define BUG_ON(condition) do { if (unlikely((condition)!=0)) BUG(); } while(0)
+#endif /* BUG */
+
+/* Force a compilation error if condition is true */
+#define BUILD_BUG_ON(condition) ((void)sizeof(char[1 - 2*!!(condition)]))
+
+typedef void (interrupt_handler_t)(void *);
+
+#include <asm/u-boot.h> /* boot information for Linux kernel */
+#include <asm/global_data.h>	/* global data used for startup functions */
+
+/*
+ * enable common handling for all TQM8xxL/M boards:
+ * - CONFIG_TQM8xxM will be defined for all TQM8xxM boards
+ * - CONFIG_TQM8xxL will be defined for all TQM8xxL _and_ TQM8xxM boards
+ *                  and for the TQM885D board
+ */
+#if defined(CONFIG_TQM823M) || defined(CONFIG_TQM850M) || \
+    defined(CONFIG_TQM855M) || defined(CONFIG_TQM860M) || \
+    defined(CONFIG_TQM862M) || defined(CONFIG_TQM866M)
+# ifndef CONFIG_TQM8xxM
+#  define CONFIG_TQM8xxM
+# endif
+#endif
+#if defined(CONFIG_TQM823L) || defined(CONFIG_TQM850L) || \
+    defined(CONFIG_TQM855L) || defined(CONFIG_TQM860L) || \
+    defined(CONFIG_TQM862L) || defined(CONFIG_TQM8xxM) || \
+    defined(CONFIG_TQM885D)
+# ifndef CONFIG_TQM8xxL
+#  define CONFIG_TQM8xxL
+# endif
+#endif
+
+/*
+ * General Purpose Utilities
+ */
+#define min(X, Y)				\
+	({ typeof(X) __x = (X);			\
+		typeof(Y) __y = (Y);		\
+		(__x < __y) ? __x : __y; })
+
+#define max(X, Y)				\
+	({ typeof(X) __x = (X);			\
+		typeof(Y) __y = (Y);		\
+		(__x > __y) ? __x : __y; })
+
+#define MIN(x, y)  min(x, y)
+#define MAX(x, y)  max(x, y)
+
+#define min3(X, Y, Z)				\
+	({ typeof(X) __x = (X);			\
+		typeof(Y) __y = (Y);		\
+		typeof(Z) __z = (Z);		\
+		__x < __y ? (__x < __z ? __x : __z) :	\
+		(__y < __z ? __y : __z); })
+
+#define max3(X, Y, Z)				\
+	({ typeof(X) __x = (X);			\
+		typeof(Y) __y = (Y);		\
+		typeof(Z) __z = (Z);		\
+		__x > __y ? (__x > __z ? __x : __z) :	\
+		(__y > __z ? __y : __z); })
+
+#define MIN3(x, y, z)  min3(x, y, z)
+#define MAX3(x, y, z)  max3(x, y, z)
+
+/*
+ * Return the absolute value of a number.
+ *
+ * This handles unsigned and signed longs, ints, shorts and chars.  For all
+ * input types abs() returns a signed long.
+ *
+ * For 64-bit types, use abs64()
+ */
+#define abs(x) ({						\
+		long ret;					\
+		if (sizeof(x) == sizeof(long)) {		\
+			long __x = (x);				\
+			ret = (__x < 0) ? -__x : __x;		\
+		} else {					\
+			int __x = (x);				\
+			ret = (__x < 0) ? -__x : __x;		\
+		}						\
+		ret;						\
+	})
+
+#define abs64(x) ({				\
+		s64 __x = (x);			\
+		(__x < 0) ? -__x : __x;		\
+	})
+
+#if defined(CONFIG_ENV_IS_EMBEDDED)
+#define TOTAL_MALLOC_LEN	CONFIG_SYS_MALLOC_LEN
+#elif ( ((CONFIG_ENV_ADDR+CONFIG_ENV_SIZE) < CONFIG_SYS_MONITOR_BASE) || \
+	(CONFIG_ENV_ADDR >= (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)) ) || \
+      defined(CONFIG_ENV_IS_IN_NVRAM)
+#define	TOTAL_MALLOC_LEN	(CONFIG_SYS_MALLOC_LEN + CONFIG_ENV_SIZE)
+#else
+#define	TOTAL_MALLOC_LEN	CONFIG_SYS_MALLOC_LEN
+#endif
+
+/**
+ * container_of - cast a member of a structure out to the containing structure
+ * @ptr:	the pointer to the member.
+ * @type:	the type of the container struct this is embedded in.
+ * @member:	the name of the member within the struct.
+ *
+ */
+#define container_of(ptr, type, member) ({			\
+	const typeof( ((type *)0)->member ) *__mptr = (ptr);	\
+	(type *)( (char *)__mptr - offsetof(type,member) );})
+
+/*
+ * Function Prototypes
+ */
+
+void	hang		(void) __attribute__ ((noreturn));
+
+int	timer_init(void);
+int	cpu_init(void);
+
+/* */
+phys_size_t initdram (int);
+int	display_options (void);
+void	print_size(unsigned long long, const char *);
+int print_buffer(ulong addr, const void *data, uint width, uint count,
+		 uint linelen);
+
+/* common/main.c */
+void	main_loop	(void);
+int run_command(const char *cmd, int flag);
+
+/**
+ * Run a list of commands separated by ; or even \0
+ *
+ * Note that if 'len' is not -1, then the command does not need to be nul
+ * terminated, Memory will be allocated for the command in that case.
+ *
+ * @param cmd	List of commands to run, each separated bu semicolon
+ * @param len	Length of commands excluding terminator if known (-1 if not)
+ * @param flag	Execution flags (CMD_FLAG_...)
+ * @return 0 on success, or != 0 on error.
+ */
+int run_command_list(const char *cmd, int len, int flag);
+int	readline	(const char *const prompt);
+int	readline_into_buffer(const char *const prompt, char *buffer,
+			int timeout);
+int	parse_line (char *, char *[]);
+void	init_cmd_timeout(void);
+void	reset_cmd_timeout(void);
+extern char console_buffer[];
+
+/* arch/$(ARCH)/lib/board.c */
+void	board_init_f(ulong);
+void	board_init_r  (gd_t *, ulong) __attribute__ ((noreturn));
+int	checkboard    (void);
+int	checkflash    (void);
+int	checkdram     (void);
+int	last_stage_init(void);
+extern ulong monitor_flash_len;
+int mac_read_from_eeprom(void);
+extern u8 __dtb_dt_begin[];	/* embedded device tree blob */
+int set_cpu_clk_info(void);
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void);
+#else
+static inline int print_cpuinfo(void)
+{
+	return 0;
+}
+#endif
+int update_flash_size(int flash_size);
+int arch_early_init_r(void);
+
+/**
+ * Show the DRAM size in a board-specific way
+ *
+ * This is used by boards to display DRAM information in their own way.
+ *
+ * @param size	Size of DRAM (which should be displayed along with other info)
+ */
+void board_show_dram(ulong size);
+
+/**
+ * arch_fixup_memory_node() - Write arch-specific memory information to fdt
+ *
+ * Defined in arch/$(ARCH)/lib/bootm.c
+ *
+ * @blob:	FDT blob to write to
+ * @return 0 if ok, or -ve FDT_ERR_... on failure
+ */
+int arch_fixup_memory_node(void *blob);
+
+/* common/flash.c */
+void flash_perror (int);
+
+/* common/cmd_source.c */
+int	source (ulong addr, const char *fit_uname);
+
+extern ulong load_addr;		/* Default Load Address */
+extern ulong save_addr;		/* Default Save Address */
+extern ulong save_size;		/* Default Save Size */
+
+/* common/cmd_doc.c */
+void	doc_probe(unsigned long physadr);
+
+/* common/cmd_net.c */
+int do_tftpb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+
+/* common/cmd_fat.c */
+int do_fat_fsload(cmd_tbl_t *, int, int, char * const []);
+
+/* common/cmd_ext2.c */
+int do_ext2load(cmd_tbl_t *, int, int, char * const []);
+
+/* common/cmd_nvedit.c */
+int	env_init     (void);
+void	env_relocate (void);
+int	envmatch     (uchar *, int);
+
+/* Avoid unfortunate conflict with libc's getenv() */
+#ifdef CONFIG_SANDBOX
+#define getenv uboot_getenv
+#endif
+char	*getenv	     (const char *);
+int	getenv_f     (const char *name, char *buf, unsigned len);
+ulong getenv_ulong(const char *name, int base, ulong default_val);
+
+/**
+ * getenv_hex() - Return an environment variable as a hex value
+ *
+ * Decode an environment as a hex number (it may or may not have a 0x
+ * prefix). If the environment variable cannot be found, or does not start
+ * with hex digits, the default value is returned.
+ *
+ * @varname:		Variable to decode
+ * @default_val:	Value to return on error
+ */
+ulong getenv_hex(const char *varname, ulong default_val);
+
+/*
+ * Read an environment variable as a boolean
+ * Return -1 if variable does not exist (default to true)
+ */
+int getenv_yesno(const char *var);
+int	saveenv	     (void);
+int	setenv	     (const char *, const char *);
+int setenv_ulong(const char *varname, ulong value);
+int setenv_hex(const char *varname, ulong value);
+/**
+ * setenv_addr - Set an environment variable to an address in hex
+ *
+ * @varname:	Environment variable to set
+ * @addr:	Value to set it to
+ * @return 0 if ok, 1 on error
+ */
+static inline int setenv_addr(const char *varname, const void *addr)
+{
+	return setenv_hex(varname, (ulong)addr);
+}
+
+#ifdef CONFIG_ARM
+# include <asm/mach-types.h>
+# include <asm/setup.h>
+# include <asm/u-boot-arm.h>	/* ARM version to be fixed! */
+#endif /* CONFIG_ARM */
+#ifdef CONFIG_X86		/* x86 version to be fixed! */
+# include <asm/u-boot-x86.h>
+#endif /* CONFIG_X86 */
+#ifdef CONFIG_SANDBOX
+# include <asm/u-boot-sandbox.h>	/* TODO(sjg) what needs to be fixed? */
+#endif
+#ifdef CONFIG_NDS32
+# include <asm/mach-types.h>
+# include <asm/setup.h>
+# include <asm/u-boot-nds32.h>
+#endif /* CONFIG_NDS32 */
+#ifdef CONFIG_MIPS
+# include <asm/u-boot-mips.h>
+#endif /* CONFIG_MIPS */
+#ifdef CONFIG_ARC
+# include <asm/u-boot-arc.h>
+#endif /* CONFIG_ARC */
+
+#ifdef CONFIG_AUTO_COMPLETE
+int env_complete(char *var, int maxv, char *cmdv[], int maxsz, char *buf);
+#endif
+int get_env_id (void);
+
+void	pci_init      (void);
+void	pci_init_board(void);
+void	pciinfo	      (int, int);
+
+#if defined(CONFIG_PCI) && defined(CONFIG_4xx)
+    int	   pci_pre_init	       (struct pci_controller *);
+    int	   is_pci_host	       (struct pci_controller *);
+#endif
+
+#if defined(CONFIG_PCI) && (defined(CONFIG_440) || defined(CONFIG_405EX))
+#   if defined(CONFIG_SYS_PCI_TARGET_INIT)
+	void	pci_target_init	     (struct pci_controller *);
+#   endif
+#   if defined(CONFIG_SYS_PCI_MASTER_INIT)
+	void	pci_master_init	     (struct pci_controller *);
+#   endif
+#if defined(CONFIG_440SPE) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+    defined(CONFIG_405EX)
+   void pcie_setup_hoses(int busno);
+#endif
+#endif
+
+int	misc_init_f   (void);
+int	misc_init_r   (void);
+
+/* common/exports.c */
+void	jumptable_init(void);
+
+/* common/kallsysm.c */
+const char *symbol_lookup(unsigned long addr, unsigned long *caddr);
+
+/* api/api.c */
+void	api_init (void);
+
+/* common/memsize.c */
+long	get_ram_size  (long *, long);
+phys_size_t get_effective_memsize(void);
+
+/* $(BOARD)/$(BOARD).c */
+void	reset_phy     (void);
+void	fdc_hw_init   (void);
+
+/* $(BOARD)/eeprom.c */
+void eeprom_init  (void);
+#ifndef CONFIG_SPI
+int  eeprom_probe (unsigned dev_addr, unsigned offset);
+#endif
+int  eeprom_read  (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt);
+int  eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt);
+#ifdef CONFIG_LWMON
+extern uchar pic_read  (uchar reg);
+extern void  pic_write (uchar reg, uchar val);
+#endif
+
+/*
+ * Set this up regardless of board
+ * type, to prevent errors.
+ */
+#if defined(CONFIG_SPI) || !defined(CONFIG_SYS_I2C_EEPROM_ADDR)
+# define CONFIG_SYS_DEF_EEPROM_ADDR 0
+#else
+#if !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
+# define CONFIG_SYS_DEF_EEPROM_ADDR CONFIG_SYS_I2C_EEPROM_ADDR
+#endif
+#endif /* CONFIG_SPI || !defined(CONFIG_SYS_I2C_EEPROM_ADDR) */
+
+#if defined(CONFIG_SPI)
+extern void spi_init_f (void);
+extern void spi_init_r (void);
+extern ssize_t spi_read	 (uchar *, int, uchar *, int);
+extern ssize_t spi_write (uchar *, int, uchar *, int);
+#endif
+
+void rpxlite_init (void);
+
+#ifdef CONFIG_HERMES
+/* $(BOARD)/hermes.c */
+void hermes_start_lxt980 (int speed);
+#endif
+
+#ifdef CONFIG_EVB64260
+void  evb64260_init(void);
+void  debug_led(int, int);
+void  display_mem_map(void);
+void  perform_soft_reset(void);
+#endif
+
+/* $(BOARD)/$(BOARD).c */
+int board_early_init_f (void);
+int board_late_init (void);
+int board_postclk_init (void); /* after clocks/timebase, before env/serial */
+int board_early_init_r (void);
+void board_poweroff (void);
+
+#if defined(CONFIG_SYS_DRAM_TEST)
+int testdram(void);
+#endif /* CONFIG_SYS_DRAM_TEST */
+
+/* $(CPU)/start.S */
+#if defined(CONFIG_5xx) || \
+    defined(CONFIG_8xx)
+uint	get_immr      (uint);
+#endif
+uint	get_pir	      (void);
+#if defined(CONFIG_MPC5xxx)
+uint	get_svr       (void);
+#endif
+uint	get_pvr	      (void);
+uint	get_svr	      (void);
+uint	rd_ic_cst     (void);
+void	wr_ic_cst     (uint);
+void	wr_ic_adr     (uint);
+uint	rd_dc_cst     (void);
+void	wr_dc_cst     (uint);
+void	wr_dc_adr     (uint);
+int	icache_status (void);
+void	icache_enable (void);
+void	icache_disable(void);
+int	dcache_status (void);
+void	dcache_enable (void);
+void	dcache_disable(void);
+void	mmu_disable(void);
+#if defined(CONFIG_ARM)
+void	relocate_code(ulong);
+#else
+void	relocate_code(ulong, gd_t *, ulong) __attribute__ ((noreturn));
+#endif
+ulong	get_endaddr   (void);
+void	trap_init     (ulong);
+#if defined (CONFIG_4xx)	|| \
+    defined (CONFIG_MPC5xxx)	|| \
+    defined (CONFIG_74xx_7xx)	|| \
+    defined (CONFIG_74x)	|| \
+    defined (CONFIG_75x)	|| \
+    defined (CONFIG_74xx)	|| \
+    defined (CONFIG_MPC85xx)	|| \
+    defined (CONFIG_MPC86xx)	|| \
+    defined (CONFIG_MPC83xx)
+unsigned char	in8(unsigned int);
+void		out8(unsigned int, unsigned char);
+unsigned short	in16(unsigned int);
+unsigned short	in16r(unsigned int);
+void		out16(unsigned int, unsigned short value);
+void		out16r(unsigned int, unsigned short value);
+unsigned long	in32(unsigned int);
+unsigned long	in32r(unsigned int);
+void		out32(unsigned int, unsigned long value);
+void		out32r(unsigned int, unsigned long value);
+void		ppcDcbf(unsigned long value);
+void		ppcDcbi(unsigned long value);
+void		ppcSync(void);
+void		ppcDcbz(unsigned long value);
+#endif
+#if defined (CONFIG_MICROBLAZE)
+unsigned short	in16(unsigned int);
+void		out16(unsigned int, unsigned short value);
+#endif
+
+#if defined (CONFIG_MPC83xx)
+void		ppcDWload(unsigned int *addr, unsigned int *ret);
+void		ppcDWstore(unsigned int *addr, unsigned int *value);
+void disable_addr_trans(void);
+void enable_addr_trans(void);
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+void ddr_enable_ecc(unsigned int dram_size);
+#endif
+#endif
+
+/*
+ * Return the current value of a monotonically increasing microsecond timer.
+ * Granularity may be larger than 1us if hardware does not support this.
+ */
+ulong timer_get_us(void);
+
+/* $(CPU)/cpu.c */
+static inline int cpumask_next(int cpu, unsigned int mask)
+{
+	for (cpu++; !((1 << cpu) & mask); cpu++)
+		;
+
+	return cpu;
+}
+
+#define for_each_cpu(iter, cpu, num_cpus, mask) \
+	for (iter = 0, cpu = cpumask_next(-1, mask); \
+		iter < num_cpus; \
+		iter++, cpu = cpumask_next(cpu, mask)) \
+
+int	cpu_numcores  (void);
+u32	cpu_mask      (void);
+int	is_core_valid (unsigned int);
+int	probecpu      (void);
+int	checkcpu      (void);
+int	checkicache   (void);
+int	checkdcache   (void);
+void	upmconfig     (unsigned int, unsigned int *, unsigned int);
+ulong	get_tbclk     (void);
+void	reset_cpu     (ulong addr);
+#if defined (CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP)
+void ft_cpu_setup(void *blob, bd_t *bd);
+#ifdef CONFIG_PCI
+void ft_pci_setup(void *blob, bd_t *bd);
+#endif
+#endif
+
+void smp_set_core_boot_addr(unsigned long addr, int corenr);
+void smp_kick_all_cpus(void);
+
+/* $(CPU)/serial.c */
+int	serial_init   (void);
+void	serial_setbrg (void);
+void	serial_putc   (const char);
+void	serial_putc_raw(const char);
+void	serial_puts   (const char *);
+int	serial_getc   (void);
+int	serial_tstc   (void);
+
+void	_serial_setbrg (const int);
+void	_serial_putc   (const char, const int);
+void	_serial_putc_raw(const char, const int);
+void	_serial_puts   (const char *, const int);
+int	_serial_getc   (const int);
+int	_serial_tstc   (const int);
+
+/* $(CPU)/speed.c */
+int	get_clocks (void);
+int	get_clocks_866 (void);
+int	sdram_adjust_866 (void);
+int	adjust_sdram_tbs_8xx (void);
+#if defined(CONFIG_MPC8260)
+int	prt_8260_clks (void);
+#elif defined(CONFIG_MPC5xxx)
+int	prt_mpc5xxx_clks (void);
+#endif
+#ifdef CONFIG_4xx
+ulong	get_OPB_freq (void);
+ulong	get_PCI_freq (void);
+#endif
+#if defined(CONFIG_S3C24X0) || \
+    defined(CONFIG_LH7A40X) || \
+    defined(CONFIG_EP93XX)
+ulong	get_FCLK (void);
+ulong	get_HCLK (void);
+ulong	get_PCLK (void);
+ulong	get_UCLK (void);
+#endif
+#if defined(CONFIG_LH7A40X)
+ulong	get_PLLCLK (void);
+#endif
+#if defined(CONFIG_IMX)
+ulong get_systemPLLCLK(void);
+ulong get_FCLK(void);
+ulong get_HCLK(void);
+ulong get_BCLK(void);
+ulong get_PERCLK1(void);
+ulong get_PERCLK2(void);
+ulong get_PERCLK3(void);
+#endif
+ulong	get_bus_freq  (ulong);
+int get_serial_clock(void);
+
+#if defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx)
+ulong get_ddr_freq(ulong);
+#endif
+#if defined(CONFIG_MPC85xx)
+typedef MPC85xx_SYS_INFO sys_info_t;
+void	get_sys_info  ( sys_info_t * );
+#  if defined(CONFIG_OF_LIBFDT)
+	void ft_fixup_cpu(void *, u64);
+	void ft_fixup_num_cores(void *);
+#  endif
+#endif
+#if defined(CONFIG_MPC86xx)
+typedef MPC86xx_SYS_INFO sys_info_t;
+void   get_sys_info  ( sys_info_t * );
+static inline ulong get_ddr_freq(ulong dummy)
+{
+	return get_bus_freq(dummy);
+}
+#endif
+
+#if defined(CONFIG_4xx)
+#  if defined(CONFIG_440)
+#	if defined(CONFIG_440SPE)
+	 unsigned long determine_sysper(void);
+	 unsigned long determine_pci_clock_per(void);
+#	endif
+#  endif
+typedef PPC4xx_SYS_INFO sys_info_t;
+int	ppc440spe_revB(void);
+void	get_sys_info  ( sys_info_t * );
+#endif
+
+/* $(CPU)/cpu_init.c */
+#if defined(CONFIG_8xx) || defined(CONFIG_MPC8260)
+void	cpu_init_f    (volatile immap_t *immr);
+#endif
+#if defined(CONFIG_4xx) || defined(CONFIG_MCF52x2) || defined(CONFIG_MPC86xx)
+void	cpu_init_f    (void);
+#endif
+#ifdef CONFIG_MPC85xx
+ulong cpu_init_f(void);
+#endif
+
+int	cpu_init_r    (void);
+#if defined(CONFIG_MPC8260)
+int	prt_8260_rsr  (void);
+#elif defined(CONFIG_MPC83xx)
+int	prt_83xx_rsr  (void);
+#endif
+
+/* $(CPU)/interrupts.c */
+int	interrupt_init	   (void);
+void	timer_interrupt	   (struct pt_regs *);
+void	external_interrupt (struct pt_regs *);
+void	irq_install_handler(int, interrupt_handler_t *, void *);
+void	irq_free_handler   (int);
+void	reset_timer	   (void);
+ulong	get_timer	   (ulong base);
+
+/* Return value of monotonic microsecond timer */
+unsigned long timer_get_us(void);
+
+void	enable_interrupts  (void);
+int	disable_interrupts (void);
+
+/* $(CPU)/.../commproc.c */
+int	dpram_init (void);
+uint	dpram_base(void);
+uint	dpram_base_align(uint align);
+uint	dpram_alloc(uint size);
+uint	dpram_alloc_align(uint size,uint align);
+void	bootcount_store (ulong);
+ulong	bootcount_load (void);
+#define BOOTCOUNT_MAGIC		0xB001C041
+
+/* $(CPU)/.../<eth> */
+void mii_init (void);
+
+/* $(CPU)/.../lcd.c */
+ulong	lcd_setmem (ulong);
+
+/* $(CPU)/.../video.c */
+ulong	video_setmem (ulong);
+
+/* arch/$(ARCH)/lib/cache.c */
+void	enable_caches(void);
+void	flush_cache   (unsigned long, unsigned long);
+void	flush_dcache_all(void);
+void	flush_dcache_range(unsigned long start, unsigned long stop);
+void	invalidate_dcache_range(unsigned long start, unsigned long stop);
+void	invalidate_dcache_all(void);
+void	invalidate_icache_all(void);
+
+/* arch/$(ARCH)/lib/ticks.S */
+unsigned long long get_ticks(void);
+void	wait_ticks    (unsigned long);
+
+/* arch/$(ARCH)/lib/time.c */
+void	__udelay      (unsigned long);
+ulong	usec2ticks    (unsigned long usec);
+ulong	ticks2usec    (unsigned long ticks);
+int	init_timebase (void);
+
+/* lib/gunzip.c */
+int gunzip(void *, int, unsigned char *, unsigned long *);
+int zunzip(void *dst, int dstlen, unsigned char *src, unsigned long *lenp,
+						int stoponerr, int offset);
+
+/* lib/qsort.c */
+void qsort(void *base, size_t nmemb, size_t size,
+	   int(*compar)(const void *, const void *));
+int strcmp_compar(const void *, const void *);
+
+/* lib/time.c */
+void	udelay        (unsigned long);
+void mdelay(unsigned long);
+
+/* lib/uuid.c */
+#include <uuid.h>
+
+/* lib/vsprintf.c */
+#include <vsprintf.h>
+
+/* lib/strmhz.c */
+char *	strmhz(char *buf, unsigned long hz);
+
+/* lib/crc32.c */
+#include <u-boot/crc.h>
+
+/* lib/rand.c */
+#define RAND_MAX -1U
+void srand(unsigned int seed);
+unsigned int rand(void);
+unsigned int rand_r(unsigned int *seedp);
+
+/* common/console.c */
+int	console_init_f(void);	/* Before relocation; uses the serial  stuff	*/
+int	console_init_r(void);	/* After  relocation; uses the console stuff	*/
+int	console_assign(int file, const char *devname);	/* Assign the console	*/
+int	ctrlc (void);
+int	had_ctrlc (void);	/* have we had a Control-C since last clear? */
+void	clear_ctrlc (void);	/* clear the Control-C condition */
+int	disable_ctrlc (int);	/* 1 to disable, 0 to enable Control-C detect */
+
+/*
+ * STDIO based functions (can always be used)
+ */
+/* serial stuff */
+int	serial_printf (const char *fmt, ...)
+		__attribute__ ((format (__printf__, 1, 2)));
+/* stdin */
+int	getc(void);
+int	tstc(void);
+
+/* stdout */
+void	putc(const char c);
+void	puts(const char *s);
+int	printf(const char *fmt, ...)
+		__attribute__ ((format (__printf__, 1, 2)));
+int	vprintf(const char *fmt, va_list args);
+
+/* stderr */
+#define eputc(c)		fputc(stderr, c)
+#define eputs(s)		fputs(stderr, s)
+#define eprintf(fmt,args...)	fprintf(stderr,fmt ,##args)
+
+/*
+ * FILE based functions (can only be used AFTER relocation!)
+ */
+#define stdin		0
+#define stdout		1
+#define stderr		2
+#define MAX_FILES	3
+
+int	fprintf(int file, const char *fmt, ...)
+		__attribute__ ((format (__printf__, 2, 3)));
+void	fputs(int file, const char *s);
+void	fputc(int file, const char c);
+int	ftstc(int file);
+int	fgetc(int file);
+
+/* lib/gzip.c */
+int gzip(void *dst, unsigned long *lenp,
+		unsigned char *src, unsigned long srclen);
+int zzip(void *dst, unsigned long *lenp, unsigned char *src,
+		unsigned long srclen, int stoponerr,
+		int (*func)(unsigned long, unsigned long));
+
+/* lib/net_utils.c */
+#include <net.h>
+static inline IPaddr_t getenv_IPaddr(char *var)
+{
+	return string_to_ip(getenv(var));
+}
+
+/*
+ * CONSOLE multiplexing.
+ */
+#ifdef CONFIG_CONSOLE_MUX
+#include <iomux.h>
+#endif
+
+int	pcmcia_init (void);
+
+#ifdef CONFIG_STATUS_LED
+# include <status_led.h>
+#endif
+
+#include <bootstage.h>
+
+#ifdef CONFIG_SHOW_ACTIVITY
+void show_activity(int arg);
+#endif
+
+/* Multicore arch functions */
+#ifdef CONFIG_MP
+int cpu_status(int nr);
+int cpu_reset(int nr);
+int cpu_disable(int nr);
+int cpu_release(int nr, int argc, char * const argv[]);
+#endif
+
+/* Define a null map_sysmem() if the architecture doesn't use it */
+# ifndef CONFIG_ARCH_MAP_SYSMEM
+static inline void *map_sysmem(phys_addr_t paddr, unsigned long len)
+{
+	return (void *)(uintptr_t)paddr;
+}
+
+static inline void unmap_sysmem(const void *vaddr)
+{
+}
+
+static inline phys_addr_t map_to_sysmem(const void *ptr)
+{
+	return (phys_addr_t)(uintptr_t)ptr;
+}
+# endif
+
+#endif /* __ASSEMBLY__ */
+
+#ifdef CONFIG_PPC
+/*
+ * Has to be included outside of the #ifndef __ASSEMBLY__ section.
+ * Otherwise might lead to compilation errors in assembler files.
+ */
+#include <asm/cache.h>
+#endif
+
+/* Put only stuff here that the assembler can digest */
+
+#ifdef CONFIG_POST
+#define CONFIG_HAS_POST
+#ifndef CONFIG_POST_ALT_LIST
+#define CONFIG_POST_STD_LIST
+#endif
+#endif
+
+#ifdef CONFIG_INIT_CRITICAL
+#error CONFIG_INIT_CRITICAL is deprecated!
+#error Read section CONFIG_SKIP_LOWLEVEL_INIT in README.
+#endif
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+#define ROUND(a,b)		(((a) + (b) - 1) & ~((b) - 1))
+#define DIV_ROUND(n,d)		(((n) + ((d)/2)) / (d))
+#define DIV_ROUND_UP(n,d)	(((n) + (d) - 1) / (d))
+#define roundup(x, y)		((((x) + ((y) - 1)) / (y)) * (y))
+
+/*
+ * Divide positive or negative dividend by positive divisor and round
+ * to closest integer. Result is undefined for negative divisors and
+ * for negative dividends if the divisor variable type is unsigned.
+ */
+#define DIV_ROUND_CLOSEST(x, divisor)(			\
+{							\
+	typeof(x) __x = x;				\
+	typeof(divisor) __d = divisor;			\
+	(((typeof(x))-1) > 0 ||				\
+	 ((typeof(divisor))-1) > 0 || (__x) > 0) ?	\
+		(((__x) + ((__d) / 2)) / (__d)) :	\
+		(((__x) - ((__d) / 2)) / (__d));	\
+}							\
+)
+
+#define ALIGN(x,a)		__ALIGN_MASK((x),(typeof(x))(a)-1)
+#define __ALIGN_MASK(x,mask)	(((x)+(mask))&~(mask))
+
+/*
+ * ARCH_DMA_MINALIGN is defined in asm/cache.h for each architecture.  It
+ * is used to align DMA buffers.
+ */
+#ifndef __ASSEMBLY__
+#include <asm/cache.h>
+#endif
+
+/*
+ * The ALLOC_CACHE_ALIGN_BUFFER macro is used to allocate a buffer on the
+ * stack that meets the minimum architecture alignment requirements for DMA.
+ * Such a buffer is useful for DMA operations where flushing and invalidating
+ * the cache before and after a read and/or write operation is required for
+ * correct operations.
+ *
+ * When called the macro creates an array on the stack that is sized such
+ * that:
+ *
+ * 1) The beginning of the array can be advanced enough to be aligned.
+ *
+ * 2) The size of the aligned portion of the array is a multiple of the minimum
+ *    architecture alignment required for DMA.
+ *
+ * 3) The aligned portion contains enough space for the original number of
+ *    elements requested.
+ *
+ * The macro then creates a pointer to the aligned portion of this array and
+ * assigns to the pointer the address of the first element in the aligned
+ * portion of the array.
+ *
+ * Calling the macro as:
+ *
+ *     ALLOC_CACHE_ALIGN_BUFFER(uint32_t, buffer, 1024);
+ *
+ * Will result in something similar to saying:
+ *
+ *     uint32_t    buffer[1024];
+ *
+ * The following differences exist:
+ *
+ * 1) The resulting buffer is guaranteed to be aligned to the value of
+ *    ARCH_DMA_MINALIGN.
+ *
+ * 2) The buffer variable created by the macro is a pointer to the specified
+ *    type, and NOT an array of the specified type.  This can be very important
+ *    if you want the address of the buffer, which you probably do, to pass it
+ *    to the DMA hardware.  The value of &buffer is different in the two cases.
+ *    In the macro case it will be the address of the pointer, not the address
+ *    of the space reserved for the buffer.  However, in the second case it
+ *    would be the address of the buffer.  So if you are replacing hard coded
+ *    stack buffers with this macro you need to make sure you remove the & from
+ *    the locations where you are taking the address of the buffer.
+ *
+ * Note that the size parameter is the number of array elements to allocate,
+ * not the number of bytes.
+ *
+ * This macro can not be used outside of function scope, or for the creation
+ * of a function scoped static buffer.  It can not be used to create a cache
+ * line aligned global buffer.
+ */
+#define PAD_COUNT(s, pad) (((s) - 1) / (pad) + 1)
+#define PAD_SIZE(s, pad) (PAD_COUNT(s, pad) * pad)
+#define ALLOC_ALIGN_BUFFER_PAD(type, name, size, align, pad)		\
+	char __##name[ROUND(PAD_SIZE((size) * sizeof(type), pad), align)  \
+		      + (align - 1)];					\
+									\
+	type *name = (type *) ALIGN((uintptr_t)__##name, align)
+#define ALLOC_ALIGN_BUFFER(type, name, size, align)		\
+	ALLOC_ALIGN_BUFFER_PAD(type, name, size, align, 1)
+#define ALLOC_CACHE_ALIGN_BUFFER_PAD(type, name, size, pad)		\
+	ALLOC_ALIGN_BUFFER_PAD(type, name, size, ARCH_DMA_MINALIGN, pad)
+#define ALLOC_CACHE_ALIGN_BUFFER(type, name, size)			\
+	ALLOC_ALIGN_BUFFER(type, name, size, ARCH_DMA_MINALIGN)
+
+/*
+ * DEFINE_CACHE_ALIGN_BUFFER() is similar to ALLOC_CACHE_ALIGN_BUFFER, but it's
+ * purpose is to allow allocating aligned buffers outside of function scope.
+ * Usage of this macro shall be avoided or used with extreme care!
+ */
+#define DEFINE_ALIGN_BUFFER(type, name, size, align)			\
+	static char __##name[roundup(size * sizeof(type), align)]	\
+			__aligned(align);				\
+									\
+	static type *name = (type *)__##name
+#define DEFINE_CACHE_ALIGN_BUFFER(type, name, size)			\
+	DEFINE_ALIGN_BUFFER(type, name, size, ARCH_DMA_MINALIGN)
+
+/* Pull in stuff for the build system */
+#ifdef DO_DEPS_ONLY
+# include <environment.h>
+#endif
+
+#endif	/* __COMMON_H_ */
diff --git a/qemu/roms/u-boot/include/common_timing_params.h b/qemu/roms/u-boot/include/common_timing_params.h
new file mode 100644
index 000000000..821de21de
--- /dev/null
+++ b/qemu/roms/u-boot/include/common_timing_params.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2008-2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#ifndef COMMON_TIMING_PARAMS_H
+#define COMMON_TIMING_PARAMS_H
+
+typedef struct {
+	/* parameters to constrict */
+
+	unsigned int tckmin_x_ps;
+	unsigned int tckmax_ps;
+	unsigned int trcd_ps;
+	unsigned int trp_ps;
+	unsigned int tras_ps;
+#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
+	unsigned int taamin_ps;
+#endif
+
+#ifdef CONFIG_SYS_FSL_DDR4
+	unsigned int trfc1_ps;
+	unsigned int trfc2_ps;
+	unsigned int trfc4_ps;
+	unsigned int trrds_ps;
+	unsigned int trrdl_ps;
+	unsigned int tccdl_ps;
+#else
+	unsigned int twtr_ps;	/* maximum = 63750 ps */
+	unsigned int trfc_ps;	/* maximum = 255 ns + 256 ns + .75 ns
+					   = 511750 ps */
+
+	unsigned int trrd_ps;	/* maximum = 63750 ps */
+	unsigned int trtp_ps;	/* byte 38, spd->trtp */
+#endif
+	unsigned int twr_ps;	/* maximum = 63750 ps */
+	unsigned int trc_ps;	/* maximum = 254 ns + .75 ns = 254750 ps */
+
+	unsigned int refresh_rate_ps;
+	unsigned int extended_op_srt;
+
+#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
+	unsigned int tis_ps;	/* byte 32, spd->ca_setup */
+	unsigned int tih_ps;	/* byte 33, spd->ca_hold */
+	unsigned int tds_ps;	/* byte 34, spd->data_setup */
+	unsigned int tdh_ps;	/* byte 35, spd->data_hold */
+	unsigned int tdqsq_max_ps;	/* byte 44, spd->tdqsq */
+	unsigned int tqhs_ps;	/* byte 45, spd->tqhs */
+#endif
+
+	unsigned int ndimms_present;
+	unsigned int lowest_common_spd_caslat;
+	unsigned int highest_common_derated_caslat;
+	unsigned int additive_latency;
+	unsigned int all_dimms_burst_lengths_bitmask;
+	unsigned int all_dimms_registered;
+	unsigned int all_dimms_unbuffered;
+	unsigned int all_dimms_ecc_capable;
+
+	unsigned long long total_mem;
+	unsigned long long base_address;
+
+	/* DDR3 RDIMM */
+	unsigned char rcw[16];	/* Register Control Word 0-15 */
+} common_timing_params_t;
+
+#endif
diff --git a/qemu/roms/u-boot/include/commproc.h b/qemu/roms/u-boot/include/commproc.h
new file mode 100644
index 000000000..29a3e61e8
--- /dev/null
+++ b/qemu/roms/u-boot/include/commproc.h
@@ -0,0 +1,1459 @@
+/*
+ * MPC8xx Communication Processor Module.
+ * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
+ *
+ * (C) Copyright 2000-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * This file contains structures and information for the communication
+ * processor channels.  Some CPM control and status is available
+ * throught the MPC8xx internal memory map.  See immap.h for details.
+ * This file only contains what I need for the moment, not the total
+ * CPM capabilities.  I (or someone else) will add definitions as they
+ * are needed.  -- Dan
+ *
+ */
+#ifndef __CPM_8XX__
+#define __CPM_8XX__
+
+#include <asm/8xx_immap.h>
+
+/* CPM Command register.
+*/
+#define CPM_CR_RST		((ushort)0x8000)
+#define CPM_CR_OPCODE		((ushort)0x0f00)
+#define CPM_CR_CHAN		((ushort)0x00f0)
+#define CPM_CR_FLG		((ushort)0x0001)
+
+/* Some commands (there are more...later)
+*/
+#define CPM_CR_INIT_TRX		((ushort)0x0000)
+#define CPM_CR_INIT_RX		((ushort)0x0001)
+#define CPM_CR_INIT_TX		((ushort)0x0002)
+#define CPM_CR_HUNT_MODE	((ushort)0x0003)
+#define CPM_CR_STOP_TX		((ushort)0x0004)
+#define CPM_CR_RESTART_TX	((ushort)0x0006)
+#define CPM_CR_SET_GADDR	((ushort)0x0008)
+
+/* Channel numbers.
+*/
+#define CPM_CR_CH_SCC1		((ushort)0x0000)
+#define CPM_CR_CH_I2C		((ushort)0x0001)    /* I2C and IDMA1 */
+#define CPM_CR_CH_SCC2		((ushort)0x0004)
+#define CPM_CR_CH_SPI		((ushort)0x0005)    /* SPI/IDMA2/Timers */
+#define CPM_CR_CH_SCC3		((ushort)0x0008)
+#define CPM_CR_CH_SMC1		((ushort)0x0009)    /* SMC1 / DSP1 */
+#define CPM_CR_CH_SCC4		((ushort)0x000c)
+#define CPM_CR_CH_SMC2		((ushort)0x000d)    /* SMC2 / DSP2 */
+
+#define mk_cr_cmd(CH, CMD)	((CMD << 8) | (CH << 4))
+
+/*
+ * DPRAM defines and allocation functions
+ */
+
+/* The dual ported RAM is multi-functional.  Some areas can be (and are
+ * being) used for microcode.  There is an area that can only be used
+ * as data ram for buffer descriptors, which is all we use right now.
+ * Currently the first 512 and last 256 bytes are used for microcode.
+ */
+#ifdef  CONFIG_SYS_ALLOC_DPRAM
+
+#define CPM_DATAONLY_BASE	((uint)0x0800)
+#define CPM_DATAONLY_SIZE	((uint)0x0700)
+#define CPM_DP_NOSPACE		((uint)0x7fffffff)
+
+#else
+
+#define CPM_SERIAL_BASE		0x0800
+#define CPM_I2C_BASE		0x0820
+#define CPM_SPI_BASE		0x0840
+#define CPM_FEC_BASE		0x0860
+#define CPM_SERIAL2_BASE	0x08E0
+#define CPM_SCC_BASE		0x0900
+#define CPM_POST_BASE		0x0980
+#define CPM_WLKBD_BASE		0x0a00
+
+#endif
+
+#ifndef CONFIG_SYS_CPM_POST_WORD_ADDR
+#define CPM_POST_WORD_ADDR	0x07FC
+#else
+#define CPM_POST_WORD_ADDR	CONFIG_SYS_CPM_POST_WORD_ADDR
+#endif
+
+#ifndef CONFIG_SYS_CPM_BOOTCOUNT_ADDR
+#define CPM_BOOTCOUNT_ADDR	(CPM_POST_WORD_ADDR - 2*sizeof(ulong))
+#else
+#define CPM_BOOTCOUNT_ADDR	CONFIG_SYS_CPM_BOOTCOUNT_ADDR
+#endif
+
+#define BD_IIC_START	((uint) 0x0400) /* <- please use CPM_I2C_BASE !! */
+
+/* Export the base address of the communication processor registers
+ * and dual port ram.
+ */
+extern	cpm8xx_t	*cpmp;		/* Pointer to comm processor */
+
+/* Buffer descriptors used by many of the CPM protocols.
+*/
+typedef struct cpm_buf_desc {
+	ushort	cbd_sc;		/* Status and Control */
+	ushort	cbd_datlen;	/* Data length in buffer */
+	uint	cbd_bufaddr;	/* Buffer address in host memory */
+} cbd_t;
+
+#define BD_SC_EMPTY	((ushort)0x8000)	/* Receive is empty */
+#define BD_SC_READY	((ushort)0x8000)	/* Transmit is ready */
+#define BD_SC_WRAP	((ushort)0x2000)	/* Last buffer descriptor */
+#define BD_SC_INTRPT	((ushort)0x1000)	/* Interrupt on change */
+#define BD_SC_LAST	((ushort)0x0800)	/* Last buffer in frame */
+#define BD_SC_TC	((ushort)0x0400)	/* Transmit CRC */
+#define BD_SC_CM	((ushort)0x0200)	/* Continous mode */
+#define BD_SC_ID	((ushort)0x0100)	/* Rec'd too many idles */
+#define BD_SC_P		((ushort)0x0100)	/* xmt preamble */
+#define BD_SC_BR	((ushort)0x0020)	/* Break received */
+#define BD_SC_FR	((ushort)0x0010)	/* Framing error */
+#define BD_SC_PR	((ushort)0x0008)	/* Parity error */
+#define BD_SC_OV	((ushort)0x0002)	/* Overrun */
+#define BD_SC_CD	((ushort)0x0001)	/* Carrier Detect lost */
+
+/* Parameter RAM offsets.
+*/
+#define PROFF_SCC1	((uint)0x0000)
+#define PROFF_IIC	((uint)0x0080)
+#define PROFF_REVNUM	((uint)0x00b0)
+#define PROFF_SCC2	((uint)0x0100)
+#define PROFF_SPI	((uint)0x0180)
+#define PROFF_SCC3	((uint)0x0200)
+#define PROFF_SMC1	((uint)0x0280)
+#define PROFF_SCC4	((uint)0x0300)
+#define PROFF_SMC2	((uint)0x0380)
+
+/* Define enough so I can at least use the serial port as a UART.
+ */
+typedef struct smc_uart {
+	ushort	smc_rbase;	/* Rx Buffer descriptor base address */
+	ushort	smc_tbase;	/* Tx Buffer descriptor base address */
+	u_char	smc_rfcr;	/* Rx function code */
+	u_char	smc_tfcr;	/* Tx function code */
+	ushort	smc_mrblr;	/* Max receive buffer length */
+	uint	smc_rstate;	/* Internal */
+	uint	smc_idp;	/* Internal */
+	ushort	smc_rbptr;	/* Internal */
+	ushort	smc_ibc;	/* Internal */
+	uint	smc_rxtmp;	/* Internal */
+	uint	smc_tstate;	/* Internal */
+	uint	smc_tdp;	/* Internal */
+	ushort	smc_tbptr;	/* Internal */
+	ushort	smc_tbc;	/* Internal */
+	uint	smc_txtmp;	/* Internal */
+	ushort	smc_maxidl;	/* Maximum idle characters */
+	ushort	smc_tmpidl;	/* Temporary idle counter */
+	ushort	smc_brklen;	/* Last received break length */
+	ushort	smc_brkec;	/* rcv'd break condition counter */
+	ushort	smc_brkcr;	/* xmt break count register */
+	ushort	smc_rmask;	/* Temporary bit mask */
+	u_char	res1[8];
+	ushort	smc_rpbase;	/* Relocation pointer */
+} smc_uart_t;
+
+/* Function code bits.
+*/
+#define SMC_EB	((u_char)0x10)	/* Set big endian byte order */
+
+/* SMC uart mode register.
+*/
+#define	SMCMR_REN	((ushort)0x0001)
+#define SMCMR_TEN	((ushort)0x0002)
+#define SMCMR_DM	((ushort)0x000c)
+#define SMCMR_SM_GCI	((ushort)0x0000)
+#define SMCMR_SM_UART	((ushort)0x0020)
+#define SMCMR_SM_TRANS	((ushort)0x0030)
+#define SMCMR_SM_MASK	((ushort)0x0030)
+#define SMCMR_PM_EVEN	((ushort)0x0100)	/* Even parity, else odd */
+#define SMCMR_REVD	SMCMR_PM_EVEN
+#define SMCMR_PEN	((ushort)0x0200)	/* Parity enable */
+#define SMCMR_BS	SMCMR_PEN
+#define SMCMR_SL	((ushort)0x0400)	/* Two stops, else one */
+#define SMCR_CLEN_MASK	((ushort)0x7800)	/* Character length */
+#define smcr_mk_clen(C)	(((C) << 11) & SMCR_CLEN_MASK)
+
+/* SMC2 as Centronics parallel printer.  It is half duplex, in that
+ * it can only receive or transmit.  The parameter ram values for
+ * each direction are either unique or properly overlap, so we can
+ * include them in one structure.
+ */
+typedef struct smc_centronics {
+	ushort	scent_rbase;
+	ushort	scent_tbase;
+	u_char	scent_cfcr;
+	u_char	scent_smask;
+	ushort	scent_mrblr;
+	uint	scent_rstate;
+	uint	scent_r_ptr;
+	ushort	scent_rbptr;
+	ushort	scent_r_cnt;
+	uint	scent_rtemp;
+	uint	scent_tstate;
+	uint	scent_t_ptr;
+	ushort	scent_tbptr;
+	ushort	scent_t_cnt;
+	uint	scent_ttemp;
+	ushort	scent_max_sl;
+	ushort	scent_sl_cnt;
+	ushort	scent_character1;
+	ushort	scent_character2;
+	ushort	scent_character3;
+	ushort	scent_character4;
+	ushort	scent_character5;
+	ushort	scent_character6;
+	ushort	scent_character7;
+	ushort	scent_character8;
+	ushort	scent_rccm;
+	ushort	scent_rccr;
+} smc_cent_t;
+
+/* Centronics Status Mask Register.
+*/
+#define SMC_CENT_F	((u_char)0x08)
+#define SMC_CENT_PE	((u_char)0x04)
+#define SMC_CENT_S	((u_char)0x02)
+
+/* SMC Event and Mask register.
+*/
+#define	SMCM_BRKE	((unsigned char)0x40)	/* When in UART Mode */
+#define	SMCM_BRK	((unsigned char)0x10)	/* When in UART Mode */
+#define	SMCM_TXE	((unsigned char)0x10)	/* When in Transparent Mode */
+#define	SMCM_BSY	((unsigned char)0x04)
+#define	SMCM_TX		((unsigned char)0x02)
+#define	SMCM_RX		((unsigned char)0x01)
+
+/* Baud rate generators.
+*/
+#define CPM_BRG_RST		((uint)0x00020000)
+#define CPM_BRG_EN		((uint)0x00010000)
+#define CPM_BRG_EXTC_INT	((uint)0x00000000)
+#define CPM_BRG_EXTC_CLK2	((uint)0x00004000)
+#define CPM_BRG_EXTC_CLK6	((uint)0x00008000)
+#define CPM_BRG_ATB		((uint)0x00002000)
+#define CPM_BRG_CD_MASK		((uint)0x00001ffe)
+#define CPM_BRG_DIV16		((uint)0x00000001)
+
+/* SI Clock Route Register
+*/
+#define SICR_RCLK_SCC1_BRG1	((uint)0x00000000)
+#define SICR_TCLK_SCC1_BRG1	((uint)0x00000000)
+#define SICR_RCLK_SCC2_BRG2	((uint)0x00000800)
+#define SICR_TCLK_SCC2_BRG2	((uint)0x00000100)
+#define SICR_RCLK_SCC3_BRG3	((uint)0x00100000)
+#define SICR_TCLK_SCC3_BRG3	((uint)0x00020000)
+#define SICR_RCLK_SCC4_BRG4	((uint)0x18000000)
+#define SICR_TCLK_SCC4_BRG4	((uint)0x03000000)
+
+/* SCCs.
+*/
+#define SCC_GSMRH_IRP		((uint)0x00040000)
+#define SCC_GSMRH_GDE		((uint)0x00010000)
+#define SCC_GSMRH_TCRC_CCITT	((uint)0x00008000)
+#define SCC_GSMRH_TCRC_BISYNC	((uint)0x00004000)
+#define SCC_GSMRH_TCRC_HDLC	((uint)0x00000000)
+#define SCC_GSMRH_REVD		((uint)0x00002000)
+#define SCC_GSMRH_TRX		((uint)0x00001000)
+#define SCC_GSMRH_TTX		((uint)0x00000800)
+#define SCC_GSMRH_CDP		((uint)0x00000400)
+#define SCC_GSMRH_CTSP		((uint)0x00000200)
+#define SCC_GSMRH_CDS		((uint)0x00000100)
+#define SCC_GSMRH_CTSS		((uint)0x00000080)
+#define SCC_GSMRH_TFL		((uint)0x00000040)
+#define SCC_GSMRH_RFW		((uint)0x00000020)
+#define SCC_GSMRH_TXSY		((uint)0x00000010)
+#define SCC_GSMRH_SYNL16	((uint)0x0000000c)
+#define SCC_GSMRH_SYNL8		((uint)0x00000008)
+#define SCC_GSMRH_SYNL4		((uint)0x00000004)
+#define SCC_GSMRH_RTSM		((uint)0x00000002)
+#define SCC_GSMRH_RSYN		((uint)0x00000001)
+
+#define SCC_GSMRL_SIR		((uint)0x80000000)	/* SCC2 only */
+#define SCC_GSMRL_EDGE_NONE	((uint)0x60000000)
+#define SCC_GSMRL_EDGE_NEG	((uint)0x40000000)
+#define SCC_GSMRL_EDGE_POS	((uint)0x20000000)
+#define SCC_GSMRL_EDGE_BOTH	((uint)0x00000000)
+#define SCC_GSMRL_TCI		((uint)0x10000000)
+#define SCC_GSMRL_TSNC_3	((uint)0x0c000000)
+#define SCC_GSMRL_TSNC_4	((uint)0x08000000)
+#define SCC_GSMRL_TSNC_14	((uint)0x04000000)
+#define SCC_GSMRL_TSNC_INF	((uint)0x00000000)
+#define SCC_GSMRL_RINV		((uint)0x02000000)
+#define SCC_GSMRL_TINV		((uint)0x01000000)
+#define SCC_GSMRL_TPL_128	((uint)0x00c00000)
+#define SCC_GSMRL_TPL_64	((uint)0x00a00000)
+#define SCC_GSMRL_TPL_48	((uint)0x00800000)
+#define SCC_GSMRL_TPL_32	((uint)0x00600000)
+#define SCC_GSMRL_TPL_16	((uint)0x00400000)
+#define SCC_GSMRL_TPL_8		((uint)0x00200000)
+#define SCC_GSMRL_TPL_NONE	((uint)0x00000000)
+#define SCC_GSMRL_TPP_ALL1	((uint)0x00180000)
+#define SCC_GSMRL_TPP_01	((uint)0x00100000)
+#define SCC_GSMRL_TPP_10	((uint)0x00080000)
+#define SCC_GSMRL_TPP_ZEROS	((uint)0x00000000)
+#define SCC_GSMRL_TEND		((uint)0x00040000)
+#define SCC_GSMRL_TDCR_32	((uint)0x00030000)
+#define SCC_GSMRL_TDCR_16	((uint)0x00020000)
+#define SCC_GSMRL_TDCR_8	((uint)0x00010000)
+#define SCC_GSMRL_TDCR_1	((uint)0x00000000)
+#define SCC_GSMRL_RDCR_32	((uint)0x0000c000)
+#define SCC_GSMRL_RDCR_16	((uint)0x00008000)
+#define SCC_GSMRL_RDCR_8	((uint)0x00004000)
+#define SCC_GSMRL_RDCR_1	((uint)0x00000000)
+#define SCC_GSMRL_RENC_DFMAN	((uint)0x00003000)
+#define SCC_GSMRL_RENC_MANCH	((uint)0x00002000)
+#define SCC_GSMRL_RENC_FM0	((uint)0x00001000)
+#define SCC_GSMRL_RENC_NRZI	((uint)0x00000800)
+#define SCC_GSMRL_RENC_NRZ	((uint)0x00000000)
+#define SCC_GSMRL_TENC_DFMAN	((uint)0x00000600)
+#define SCC_GSMRL_TENC_MANCH	((uint)0x00000400)
+#define SCC_GSMRL_TENC_FM0	((uint)0x00000200)
+#define SCC_GSMRL_TENC_NRZI	((uint)0x00000100)
+#define SCC_GSMRL_TENC_NRZ	((uint)0x00000000)
+#define SCC_GSMRL_DIAG_LE	((uint)0x000000c0)	/* Loop and echo */
+#define SCC_GSMRL_DIAG_ECHO	((uint)0x00000080)
+#define SCC_GSMRL_DIAG_LOOP	((uint)0x00000040)
+#define SCC_GSMRL_DIAG_NORM	((uint)0x00000000)
+#define SCC_GSMRL_ENR		((uint)0x00000020)
+#define SCC_GSMRL_ENT		((uint)0x00000010)
+#define SCC_GSMRL_MODE_ENET	((uint)0x0000000c)
+#define SCC_GSMRL_MODE_DDCMP	((uint)0x00000009)
+#define SCC_GSMRL_MODE_BISYNC	((uint)0x00000008)
+#define SCC_GSMRL_MODE_V14	((uint)0x00000007)
+#define SCC_GSMRL_MODE_AHDLC	((uint)0x00000006)
+#define SCC_GSMRL_MODE_PROFIBUS	((uint)0x00000005)
+#define SCC_GSMRL_MODE_UART	((uint)0x00000004)
+#define SCC_GSMRL_MODE_SS7	((uint)0x00000003)
+#define SCC_GSMRL_MODE_ATALK	((uint)0x00000002)
+#define SCC_GSMRL_MODE_HDLC	((uint)0x00000000)
+
+#define SCC_TODR_TOD		((ushort)0x8000)
+
+/* SCC Event and Mask register.
+*/
+#define	SCCM_TXE	((unsigned char)0x10)
+#define	SCCM_BSY	((unsigned char)0x04)
+#define	SCCM_TX		((unsigned char)0x02)
+#define	SCCM_RX		((unsigned char)0x01)
+
+typedef struct scc_param {
+	ushort	scc_rbase;	/* Rx Buffer descriptor base address */
+	ushort	scc_tbase;	/* Tx Buffer descriptor base address */
+	u_char	scc_rfcr;	/* Rx function code */
+	u_char	scc_tfcr;	/* Tx function code */
+	ushort	scc_mrblr;	/* Max receive buffer length */
+	uint	scc_rstate;	/* Internal */
+	uint	scc_idp;	/* Internal */
+	ushort	scc_rbptr;	/* Internal */
+	ushort	scc_ibc;	/* Internal */
+	uint	scc_rxtmp;	/* Internal */
+	uint	scc_tstate;	/* Internal */
+	uint	scc_tdp;	/* Internal */
+	ushort	scc_tbptr;	/* Internal */
+	ushort	scc_tbc;	/* Internal */
+	uint	scc_txtmp;	/* Internal */
+	uint	scc_rcrc;	/* Internal */
+	uint	scc_tcrc;	/* Internal */
+} sccp_t;
+
+/* Function code bits.
+*/
+#define SCC_EB	((u_char)0x10)	/* Set big endian byte order */
+
+/* CPM Ethernet through SCCx.
+ */
+typedef struct scc_enet {
+	sccp_t	sen_genscc;
+	uint	sen_cpres;	/* Preset CRC */
+	uint	sen_cmask;	/* Constant mask for CRC */
+	uint	sen_crcec;	/* CRC Error counter */
+	uint	sen_alec;	/* alignment error counter */
+	uint	sen_disfc;	/* discard frame counter */
+	ushort	sen_pads;	/* Tx short frame pad character */
+	ushort	sen_retlim;	/* Retry limit threshold */
+	ushort	sen_retcnt;	/* Retry limit counter */
+	ushort	sen_maxflr;	/* maximum frame length register */
+	ushort	sen_minflr;	/* minimum frame length register */
+	ushort	sen_maxd1;	/* maximum DMA1 length */
+	ushort	sen_maxd2;	/* maximum DMA2 length */
+	ushort	sen_maxd;	/* Rx max DMA */
+	ushort	sen_dmacnt;	/* Rx DMA counter */
+	ushort	sen_maxb;	/* Max BD byte count */
+	ushort	sen_gaddr1;	/* Group address filter */
+	ushort	sen_gaddr2;
+	ushort	sen_gaddr3;
+	ushort	sen_gaddr4;
+	uint	sen_tbuf0data0;	/* Save area 0 - current frame */
+	uint	sen_tbuf0data1;	/* Save area 1 - current frame */
+	uint	sen_tbuf0rba;	/* Internal */
+	uint	sen_tbuf0crc;	/* Internal */
+	ushort	sen_tbuf0bcnt;	/* Internal */
+	ushort	sen_paddrh;	/* physical address (MSB) */
+	ushort	sen_paddrm;
+	ushort	sen_paddrl;	/* physical address (LSB) */
+	ushort	sen_pper;	/* persistence */
+	ushort	sen_rfbdptr;	/* Rx first BD pointer */
+	ushort	sen_tfbdptr;	/* Tx first BD pointer */
+	ushort	sen_tlbdptr;	/* Tx last BD pointer */
+	uint	sen_tbuf1data0;	/* Save area 0 - current frame */
+	uint	sen_tbuf1data1;	/* Save area 1 - current frame */
+	uint	sen_tbuf1rba;	/* Internal */
+	uint	sen_tbuf1crc;	/* Internal */
+	ushort	sen_tbuf1bcnt;	/* Internal */
+	ushort	sen_txlen;	/* Tx Frame length counter */
+	ushort	sen_iaddr1;	/* Individual address filter */
+	ushort	sen_iaddr2;
+	ushort	sen_iaddr3;
+	ushort	sen_iaddr4;
+	ushort	sen_boffcnt;	/* Backoff counter */
+
+	/* NOTE: Some versions of the manual have the following items
+	 * incorrectly documented.  Below is the proper order.
+	 */
+	ushort	sen_taddrh;	/* temp address (MSB) */
+	ushort	sen_taddrm;
+	ushort	sen_taddrl;	/* temp address (LSB) */
+} scc_enet_t;
+
+/**********************************************************************
+ *
+ * Board specific configuration settings.
+ *
+ * Please note that we use the presence of a #define SCC_ENET and/or
+ * #define FEC_ENET to enable the SCC resp. FEC ethernet drivers.
+ **********************************************************************/
+
+/***  BSEIP  **********************************************************/
+
+#ifdef CONFIG_BSEIP
+/* This ENET stuff is for the MPC823 with ethernet on SCC2.
+ * This is unique to the BSE ip-Engine board.
+ */
+#define	PROFF_ENET	PROFF_SCC2
+#define	CPM_CR_ENET	CPM_CR_CH_SCC2
+#define	SCC_ENET	1
+#define PA_ENET_RXD	((ushort)0x0004)
+#define PA_ENET_TXD	((ushort)0x0008)
+#define PA_ENET_TCLK	((ushort)0x0100)
+#define PA_ENET_RCLK	((ushort)0x0200)
+#define PB_ENET_TENA	((uint)0x00002000)
+#define PC_ENET_CLSN	((ushort)0x0040)
+#define PC_ENET_RENA	((ushort)0x0080)
+
+/* BSE uses port B and C bits for PHY control also.
+*/
+#define PB_BSE_POWERUP	((uint)0x00000004)
+#define PB_BSE_FDXDIS	((uint)0x00008000)
+#define PC_BSE_LOOPBACK	((ushort)0x0800)
+
+#define SICR_ENET_MASK	((uint)0x0000ff00)
+#define SICR_ENET_CLKRT	((uint)0x00002c00)
+#endif	/* CONFIG_BSEIP */
+
+/***  BSEIP  **********************************************************/
+
+#ifdef CONFIG_FLAGADM
+/* Enet configuration for the FLAGADM */
+/* Enet on SCC2 */
+
+#define	PROFF_ENET	PROFF_SCC2
+#define	CPM_CR_ENET	CPM_CR_CH_SCC2
+#define	SCC_ENET	1
+#define PA_ENET_RXD	((ushort)0x0004)
+#define PA_ENET_TXD	((ushort)0x0008)
+#define PA_ENET_TCLK	((ushort)0x0100)
+#define PA_ENET_RCLK	((ushort)0x0400)
+#define PB_ENET_TENA	((uint)0x00002000)
+#define PC_ENET_CLSN	((ushort)0x0040)
+#define PC_ENET_RENA	((ushort)0x0080)
+
+#define SICR_ENET_MASK	((uint)0x0000ff00)
+#define SICR_ENET_CLKRT	((uint)0x00003400)
+#endif	/* CONFIG_FLAGADM */
+
+/***  ELPT860 *********************************************************/
+
+#ifdef CONFIG_ELPT860
+/* Bits in parallel I/O port registers that have to be set/cleared
+ * to configure the pins for SCC1 use.
+ */
+#  define PROFF_ENET        PROFF_SCC1
+#  define CPM_CR_ENET       CPM_CR_CH_SCC1
+#  define SCC_ENET          0
+
+#  define PA_ENET_RXD       ((ushort)0x0001)	/* PA 15 */
+#  define PA_ENET_TXD       ((ushort)0x0002)	/* PA 14 */
+#  define PA_ENET_RCLK      ((ushort)0x0100)	/* PA  7 */
+#  define PA_ENET_TCLK      ((ushort)0x0200)	/* PA  6 */
+
+#  define PC_ENET_TENA      ((ushort)0x0001)	/* PC 15 */
+#  define PC_ENET_CLSN      ((ushort)0x0010)	/* PC 11 */
+#  define PC_ENET_RENA      ((ushort)0x0020)	/* PC 10 */
+
+/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK1) to
+ * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
+ */
+#  define SICR_ENET_MASK    ((uint)0x000000FF)
+#  define SICR_ENET_CLKRT   ((uint)0x00000025)
+#endif	/* CONFIG_ELPT860 */
+
+/***  ESTEEM 192E  **************************************************/
+#ifdef CONFIG_ESTEEM192E
+/* ESTEEM192E
+ * This ENET stuff is for the MPC850 with ethernet on SCC2. This
+ * is very similar to the RPX-Lite configuration.
+ * Note TENA , LOOPBACK , FDPLEX_DIS on Port B.
+ */
+
+#define	PROFF_ENET	PROFF_SCC2
+#define	CPM_CR_ENET	CPM_CR_CH_SCC2
+#define	SCC_ENET	1
+
+#define PA_ENET_RXD	((ushort)0x0004)
+#define PA_ENET_TXD	((ushort)0x0008)
+#define PA_ENET_TCLK	((ushort)0x0200)
+#define PA_ENET_RCLK	((ushort)0x0800)
+#define PB_ENET_TENA	((uint)0x00002000)
+#define PC_ENET_CLSN	((ushort)0x0040)
+#define PC_ENET_RENA	((ushort)0x0080)
+
+#define SICR_ENET_MASK	((uint)0x0000ff00)
+#define SICR_ENET_CLKRT	((uint)0x00003d00)
+
+#define PB_ENET_LOOPBACK ((uint)0x00004000)
+#define PB_ENET_FDPLEX_DIS ((uint)0x00008000)
+
+#endif
+
+/***  FADS860T********************************************************/
+
+#if defined(CONFIG_FADS) && defined(CONFIG_MPC86x)
+/*
+ * This ENET stuff is for the MPC86xFADS/MPC8xxADS with ethernet on SCC1.
+ */
+#ifdef CONFIG_SCC1_ENET
+
+#define	SCC_ENET	0
+
+#define	PROFF_ENET	PROFF_SCC1
+#define	CPM_CR_ENET	CPM_CR_CH_SCC1
+
+#define PA_ENET_RXD	((ushort)0x0001)
+#define PA_ENET_TXD	((ushort)0x0002)
+#define PA_ENET_TCLK	((ushort)0x0100)
+#define PA_ENET_RCLK	((ushort)0x0200)
+
+#define PB_ENET_TENA	((uint)0x00001000)
+
+#define PC_ENET_CLSN	((ushort)0x0010)
+#define PC_ENET_RENA	((ushort)0x0020)
+
+#define SICR_ENET_MASK	((uint)0x000000ff)
+#define SICR_ENET_CLKRT	((uint)0x0000002c)
+
+#endif	/* CONFIG_SCC1_ETHERNET */
+
+/*
+ * This ENET stuff is for the MPC860TFADS/MPC86xADS/MPC885ADS
+ * with ethernet on FEC.
+ */
+
+#ifdef CONFIG_FEC_ENET
+#define	FEC_ENET	/* Use FEC for Ethernet */
+#endif	/* CONFIG_FEC_ENET */
+
+#endif	/* CONFIG_FADS && CONFIG_MPC86x */
+
+/***  FPS850L, FPS860L  ************************************************/
+
+#if defined(CONFIG_FPS850L) || defined(CONFIG_FPS860L)
+/* Bits in parallel I/O port registers that have to be set/cleared
+ * to configure the pins for SCC2 use.
+ */
+#define	PROFF_ENET	PROFF_SCC2
+#define	CPM_CR_ENET	CPM_CR_CH_SCC2
+#define	SCC_ENET	1
+#define PA_ENET_RXD	((ushort)0x0004)	/* PA 13 */
+#define PA_ENET_TXD	((ushort)0x0008)	/* PA 12 */
+#define PA_ENET_RCLK	((ushort)0x0100)	/* PA  7 */
+#define PA_ENET_TCLK	((ushort)0x0400)	/* PA  5 */
+
+#define PC_ENET_TENA	((ushort)0x0002)	/* PC 14 */
+#define PC_ENET_CLSN	((ushort)0x0040)	/* PC  9 */
+#define PC_ENET_RENA	((ushort)0x0080)	/* PC  8 */
+
+/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
+ * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
+ */
+#define SICR_ENET_MASK	((uint)0x0000ff00)
+#define SICR_ENET_CLKRT	((uint)0x00002600)
+#endif	/* CONFIG_FPS850L, CONFIG_FPS860L */
+
+/*** GEN860T **********************************************************/
+#if defined(CONFIG_GEN860T)
+#undef	SCC_ENET
+#define	FEC_ENET
+
+#define PD_MII_TXD1	((ushort)0x1000)	/* PD  3	*/
+#define PD_MII_TXD2	((ushort)0x0800)	/* PD  4	*/
+#define PD_MII_TXD3	((ushort)0x0400)	/* PD  5	*/
+#define PD_MII_RX_DV	((ushort)0x0200)	/* PD  6	*/
+#define PD_MII_RX_ERR	((ushort)0x0100)	/* PD  7	*/
+#define PD_MII_RX_CLK	((ushort)0x0080)	/* PD  8	*/
+#define PD_MII_TXD0	((ushort)0x0040)	/* PD  9	*/
+#define PD_MII_RXD0	((ushort)0x0020)	/* PD 10	*/
+#define PD_MII_TX_ERR	((ushort)0x0010)	/* PD 11	*/
+#define PD_MII_MDC	((ushort)0x0008)	/* PD 12	*/
+#define PD_MII_RXD1	((ushort)0x0004)	/* PD 13	*/
+#define PD_MII_RXD2	((ushort)0x0002)	/* PD 14	*/
+#define PD_MII_RXD3	((ushort)0x0001)	/* PD 15	*/
+#define PD_MII_MASK	((ushort)0x1FFF)	/* PD 3-15	*/
+#endif	/* CONFIG_GEN860T */
+
+/*** HERMES-PRO ******************************************************/
+
+/* The HERMES-PRO uses the FEC on a MPC860T for Ethernet */
+
+#ifdef CONFIG_HERMES
+
+#define	FEC_ENET	/* use FEC for EThernet */
+#undef	SCC_ENET
+
+
+#define PD_MII_TXD1	((ushort)0x1000)	/* PD  3 */
+#define PD_MII_TXD2	((ushort)0x0800)	/* PD  4 */
+#define PD_MII_TXD3	((ushort)0x0400)	/* PD  5 */
+#define PD_MII_RX_DV	((ushort)0x0200)	/* PD  6 */
+#define PD_MII_RX_ERR	((ushort)0x0100)	/* PD  7 */
+#define PD_MII_RX_CLK	((ushort)0x0080)	/* PD  8 */
+#define PD_MII_TXD0	((ushort)0x0040)	/* PD  9 */
+#define PD_MII_RXD0	((ushort)0x0020)	/* PD 10 */
+#define PD_MII_TX_ERR	((ushort)0x0010)	/* PD 11 */
+#define PD_MII_MDC	((ushort)0x0008)	/* PD 12 */
+#define PD_MII_RXD1	((ushort)0x0004)	/* PD 13 */
+#define PD_MII_RXD2	((ushort)0x0002)	/* PD 14 */
+#define PD_MII_RXD3	((ushort)0x0001)	/* PD 15 */
+
+#define PD_MII_MASK	((ushort)0x1FFF)	/* PD 3...15 */
+
+#endif	/* CONFIG_HERMES */
+
+/*** ICU862  **********************************************************/
+
+#if defined(CONFIG_ICU862)
+
+#ifdef CONFIG_FEC_ENET
+#define FEC_ENET	/* use FEC for EThernet */
+#endif  /* CONFIG_FEC_ETHERNET */
+
+#endif /* CONFIG_ICU862 */
+
+/***  IP860  **********************************************************/
+
+#if defined(CONFIG_IP860)
+/* Bits in parallel I/O port registers that have to be set/cleared
+ * to configure the pins for SCC1 use.
+ */
+#define	PROFF_ENET	PROFF_SCC1
+#define	CPM_CR_ENET	CPM_CR_CH_SCC1
+#define	SCC_ENET	0
+#define PA_ENET_RXD	((ushort)0x0001)	/* PA 15 */
+#define PA_ENET_TXD	((ushort)0x0002)	/* PA 14 */
+#define PA_ENET_RCLK	((ushort)0x0200)	/* PA  6 */
+#define PA_ENET_TCLK	((ushort)0x0100)	/* PA  7 */
+
+#define PC_ENET_TENA	((ushort)0x0001)	/* PC 15 */
+#define PC_ENET_CLSN	((ushort)0x0010)	/* PC 11 */
+#define PC_ENET_RENA	((ushort)0x0020)	/* PC 10 */
+
+#define PB_ENET_RESET	(uint)0x00000008	/* PB 28 */
+#define PB_ENET_JABD	(uint)0x00000004	/* PB 29 */
+
+/* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to
+ * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
+ */
+#define SICR_ENET_MASK	((uint)0x000000ff)
+#define SICR_ENET_CLKRT	((uint)0x0000002C)
+#endif	/* CONFIG_IP860 */
+
+/*** IVMS8  **********************************************************/
+
+/* The IVMS8 uses the FEC on a MPC860T for Ethernet */
+
+#if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24)
+
+#define	FEC_ENET	/* use FEC for EThernet */
+#undef	SCC_ENET
+
+#define	PB_ENET_POWER	((uint)0x00010000)	/* PB 15 */
+
+#define PC_ENET_RESET	((ushort)0x0010)	/* PC 11 */
+
+#define PD_MII_TXD1	((ushort)0x1000)	/* PD  3 */
+#define PD_MII_TXD2	((ushort)0x0800)	/* PD  4 */
+#define PD_MII_TXD3	((ushort)0x0400)	/* PD  5 */
+#define PD_MII_RX_DV	((ushort)0x0200)	/* PD  6 */
+#define PD_MII_RX_ERR	((ushort)0x0100)	/* PD  7 */
+#define PD_MII_RX_CLK	((ushort)0x0080)	/* PD  8 */
+#define PD_MII_TXD0	((ushort)0x0040)	/* PD  9 */
+#define PD_MII_RXD0	((ushort)0x0020)	/* PD 10 */
+#define PD_MII_TX_ERR	((ushort)0x0010)	/* PD 11 */
+#define PD_MII_MDC	((ushort)0x0008)	/* PD 12 */
+#define PD_MII_RXD1	((ushort)0x0004)	/* PD 13 */
+#define PD_MII_RXD2	((ushort)0x0002)	/* PD 14 */
+#define PD_MII_RXD3	((ushort)0x0001)	/* PD 15 */
+
+#define PD_MII_MASK	((ushort)0x1FFF)	/* PD 3...15 */
+
+#endif	/* CONFIG_IVMS8, CONFIG_IVML24 */
+
+/***  KUP4K, KUP4X ****************************************************/
+/* The KUP4 boards uses the FEC on a MPC8xx for Ethernet */
+
+#if defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X)
+
+#define	FEC_ENET	/* use FEC for EThernet */
+#undef	SCC_ENET
+
+#define	PB_ENET_POWER	((uint)0x00010000)	/* PB 15 */
+
+#define PC_ENET_RESET	((ushort)0x0010)	/* PC 11 */
+
+#define PD_MII_TXD1	((ushort)0x1000)	/* PD  3 */
+#define PD_MII_TXD2	((ushort)0x0800)	/* PD  4 */
+#define PD_MII_TXD3	((ushort)0x0400)	/* PD  5 */
+#define PD_MII_RX_DV	((ushort)0x0200)	/* PD  6 */
+#define PD_MII_RX_ERR	((ushort)0x0100)	/* PD  7 */
+#define PD_MII_RX_CLK	((ushort)0x0080)	/* PD  8 */
+#define PD_MII_TXD0	((ushort)0x0040)	/* PD  9 */
+#define PD_MII_RXD0	((ushort)0x0020)	/* PD 10 */
+#define PD_MII_TX_ERR	((ushort)0x0010)	/* PD 11 */
+#define PD_MII_MDC	((ushort)0x0008)	/* PD 12 */
+#define PD_MII_RXD1	((ushort)0x0004)	/* PD 13 */
+#define PD_MII_RXD2	((ushort)0x0002)	/* PD 14 */
+#define PD_MII_RXD3	((ushort)0x0001)	/* PD 15 */
+
+#define PD_MII_MASK	((ushort)0x1FFF)	/* PD 3...15 */
+
+#endif	/* CONFIG_KUP4K */
+
+/***  LWMON  **********************************************************/
+
+#if defined(CONFIG_LWMON)
+/* Bits in parallel I/O port registers that have to be set/cleared
+ * to configure the pins for SCC2 use.
+ */
+#define	PROFF_ENET	PROFF_SCC2
+#define	CPM_CR_ENET	CPM_CR_CH_SCC2
+#define	SCC_ENET	1
+#define PA_ENET_RXD	((ushort)0x0004)	/* PA 13 */
+#define PA_ENET_TXD	((ushort)0x0008)	/* PA 12 */
+#define PA_ENET_RCLK	((ushort)0x0800)	/* PA  4 */
+#define PA_ENET_TCLK	((ushort)0x0400)	/* PA  5 */
+
+#define PB_ENET_TENA	((uint)0x00002000)	/* PB 18 */
+
+#define PC_ENET_CLSN	((ushort)0x0040)	/* PC  9 */
+#define PC_ENET_RENA	((ushort)0x0080)	/* PC  8 */
+
+/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK4) to
+ * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
+ */
+#define SICR_ENET_MASK	((uint)0x0000ff00)
+#define SICR_ENET_CLKRT	((uint)0x00003E00)
+#endif	/* CONFIG_LWMON */
+
+/***  KM8XX  *********************************************************/
+
+/* The KM8XX Service Module uses SCC3 for Ethernet */
+
+#ifdef CONFIG_KM8XX
+#define PROFF_ENET	PROFF_SCC3		/* Ethernet on SCC3 */
+#define CPM_CR_ENET	CPM_CR_CH_SCC3
+#define SCC_ENET	2
+#define PA_ENET_RXD	((ushort)0x0010)	/* PA 11 */
+#define PA_ENET_TXD	((ushort)0x0020)	/* PA 10 */
+#define PA_ENET_RCLK	((ushort)0x1000)	/* PA  3 CLK 5 */
+#define PA_ENET_TCLK	((ushort)0x2000)	/* PA  2 CLK 6 */
+
+#define PC_ENET_TENA	((ushort)0x0004)	/* PC 13 */
+
+#define PC_ENET_RENA	((ushort)0x0200)	/* PC  6 */
+#define PC_ENET_CLSN	((ushort)0x0100)	/* PC  7 */
+
+/* Control bits in the SICR to route TCLK (CLK6) and RCLK (CLK5) to
+ * SCC3.  Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero.
+ */
+#define SICR_ENET_MASK	((uint)0x00FF0000)
+#define SICR_ENET_CLKRT	((uint)0x00250000)
+#endif	/* CONFIG_KM8XX */
+
+
+/***  MHPC  ********************************************************/
+
+#if defined(CONFIG_MHPC)
+/* This ENET stuff is for the MHPC with ethernet on SCC2.
+ * Note TENA is on Port B.
+ */
+#define	PROFF_ENET	PROFF_SCC2
+#define	CPM_CR_ENET	CPM_CR_CH_SCC2
+#define	SCC_ENET	1
+#define PA_ENET_RXD	((ushort)0x0004)	/* PA 13 */
+#define PA_ENET_TXD	((ushort)0x0008)	/* PA 12 */
+#define PA_ENET_RCLK	((ushort)0x0200)	/* PA 6 */
+#define PA_ENET_TCLK	((ushort)0x0400)	/* PA 5 */
+#define PB_ENET_TENA	((uint)0x00002000)	/* PB 18 */
+#define PC_ENET_CLSN	((ushort)0x0040)	/* PC 9 */
+#define PC_ENET_RENA	((ushort)0x0080)	/* PC 8 */
+
+#define SICR_ENET_MASK	((uint)0x0000ff00)
+#define SICR_ENET_CLKRT	((uint)0x00002e00)	/* RCLK-CLK2, TCLK-CLK3 */
+#endif	/* CONFIG_MHPC */
+
+/***  NETVIA  *******************************************************/
+
+/* SinoVee Microsystems SC8xx series FEL8xx-AT,SC823,SC850,SC855T,SC860T */
+#if ( defined CONFIG_SVM_SC8xx )
+# ifndef CONFIG_FEC_ENET
+
+#define PROFF_ENET      PROFF_SCC2
+#define CPM_CR_ENET     CPM_CR_CH_SCC2
+#define SCC_ENET        1
+
+	/* Bits in parallel I/O port registers that have to be set/cleared
+	 *  *  *  * to configure the pins for SCC2 use.
+	 *   *   *   */
+#define PA_ENET_RXD     ((ushort)0x0004)        /* PA 13 */
+#define PA_ENET_TXD     ((ushort)0x0008)        /* PA 12 */
+#define PA_ENET_RCLK    ((ushort)0x0400)        /* PA  5 */
+#define PA_ENET_TCLK    ((ushort)0x0800)        /* PA  4 */
+
+#define PB_ENET_TENA    ((uint)0x00002000)      /* PB 18 */
+
+#define PC_ENET_CLSN    ((ushort)0x0040)        /* PC  9 */
+#define PC_ENET_RENA    ((ushort)0x0080)        /* PC  8 */
+/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
+ *  *  *  * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
+ *   *   *   */
+#define SICR_ENET_MASK  ((uint)0x0000ff00)
+#define SICR_ENET_CLKRT ((uint)0x00003700)
+
+# else                          /* Use FEC for Fast Ethernet */
+
+#undef  SCC_ENET
+#define FEC_ENET
+
+#define PD_MII_TXD1     ((ushort)0x1000)        /* PD  3 */
+#define PD_MII_TXD2     ((ushort)0x0800)        /* PD  4 */
+#define PD_MII_TXD3     ((ushort)0x0400)        /* PD  5 */
+#define PD_MII_RX_DV    ((ushort)0x0200)        /* PD  6 */
+#define PD_MII_RX_ERR   ((ushort)0x0100)        /* PD  7 */
+#define PD_MII_RX_CLK   ((ushort)0x0080)        /* PD  8 */
+#define PD_MII_TXD0     ((ushort)0x0040)        /* PD  9 */
+#define PD_MII_RXD0     ((ushort)0x0020)        /* PD 10 */
+#define PD_MII_TX_ERR   ((ushort)0x0010)        /* PD 11 */
+#define PD_MII_MDC      ((ushort)0x0008)        /* PD 12 */
+#define PD_MII_RXD1     ((ushort)0x0004)        /* PD 13 */
+#define PD_MII_RXD2     ((ushort)0x0002)        /* PD 14 */
+#define PD_MII_RXD3     ((ushort)0x0001)        /* PD 15 */
+
+#define PD_MII_MASK     ((ushort)0x1FFF)        /* PD 3...15 */
+
+# endif /* CONFIG_FEC_ENET */
+#endif  /* CONFIG_SVM_SC8xx */
+
+
+#if defined(CONFIG_NETVIA)
+/* Bits in parallel I/O port registers that have to be set/cleared
+ * to configure the pins for SCC2 use.
+ */
+#define	PROFF_ENET	PROFF_SCC2
+#define	CPM_CR_ENET	CPM_CR_CH_SCC2
+#define	SCC_ENET	1
+#define PA_ENET_RXD	((ushort)0x0004)	/* PA 13 */
+#define PA_ENET_TXD	((ushort)0x0008)	/* PA 12 */
+#define PA_ENET_RCLK	((ushort)0x0200)	/* PA  6 */
+#define PA_ENET_TCLK	((ushort)0x0800)	/* PA  4 */
+
+#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
+# define PB_ENET_PDN	((ushort)0x4000)	/* PB 17 */
+#elif CONFIG_NETVIA_VERSION >= 2
+# define PC_ENET_PDN	((ushort)0x0008)	/* PC 12 */
+#endif
+
+#define PB_ENET_TENA	((ushort)0x2000)	/* PB 18 */
+
+#define PC_ENET_CLSN	((ushort)0x0040)	/* PC  9 */
+#define PC_ENET_RENA	((ushort)0x0080)	/* PC  8 */
+
+/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
+ * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
+ */
+#define SICR_ENET_MASK	((uint)0x0000ff00)
+#define SICR_ENET_CLKRT	((uint)0x00002f00)
+
+#endif	/* CONFIG_NETVIA */
+
+/***  QS850/QS823  ***************************************************/
+
+#if defined(CONFIG_QS850) || defined(CONFIG_QS823)
+#undef FEC_ENET /* Don't use FEC for EThernet */
+
+#define PROFF_ENET		PROFF_SCC2
+#define CPM_CR_ENET		CPM_CR_CH_SCC2
+#define SCC_ENET		1
+
+#define PA_ENET_RXD		((ushort)0x0004)  /* RXD on PA13 (Pin D9) */
+#define PA_ENET_TXD		((ushort)0x0008)  /* TXD on PA12 (Pin D7) */
+#define PC_ENET_RENA		((ushort)0x0080)  /* RENA on PC8 (Pin D12) */
+#define PC_ENET_CLSN		((ushort)0x0040)  /* CLSN on PC9 (Pin C12) */
+#define PA_ENET_TCLK		((ushort)0x0200)  /* TCLK on PA6 (Pin D8) */
+#define PA_ENET_RCLK		((ushort)0x0800)  /* RCLK on PA4 (Pin D10) */
+#define PB_ENET_TENA		((uint)0x00002000)  /* TENA on PB18 (Pin D11) */
+#define PC_ENET_LBK		((ushort)0x0010)  /* Loopback control on PC11 (Pin B14) */
+#define PC_ENET_LI		((ushort)0x0020)  /* Link Integrity control PC10 (A15) */
+#define PC_ENET_SQE		((ushort)0x0100)  /* SQE Disable control PC7 (B15) */
+
+/* SCC2 TXCLK from CLK2
+ * SCC2 RXCLK from CLK4
+ * SCC2 Connected to NMSI */
+#define SICR_ENET_MASK		((uint)0x00007F00)
+#define SICR_ENET_CLKRT		((uint)0x00003D00)
+
+#endif /* CONFIG_QS850/QS823 */
+
+/***  QS860T  ***************************************************/
+
+#ifdef CONFIG_QS860T
+#ifdef CONFIG_FEC_ENET
+#define FEC_ENET /* use FEC for EThernet */
+#endif /* CONFIG_FEC_ETHERNET */
+
+/* This ENET stuff is for GTH 10 Mbit ( SCC ) */
+#define PROFF_ENET		PROFF_SCC1
+#define CPM_CR_ENET		CPM_CR_CH_SCC1
+#define SCC_ENET		0
+
+#define PA_ENET_RXD		((ushort)0x0001) /* PA15 */
+#define PA_ENET_TXD		((ushort)0x0002) /* PA14 */
+#define PA_ENET_TCLK		((ushort)0x0800) /* PA4 */
+#define PA_ENET_RCLK		((ushort)0x0200) /* PA6 */
+#define PB_ENET_TENA		((uint)0x00001000) /* PB19 */
+#define PC_ENET_CLSN		((ushort)0x0010) /* PC11 */
+#define PC_ENET_RENA		((ushort)0x0020) /* PC10 */
+
+#define SICR_ENET_MASK		((uint)0x000000ff)
+/* RCLK PA4 -->CLK4, TCLK PA6 -->CLK2 */
+#define SICR_ENET_CLKRT		((uint)0x0000003D)
+
+#endif /* CONFIG_QS860T */
+
+/***  RPXLITE  ********************************************************/
+
+#ifdef CONFIG_RPXLITE
+/* This ENET stuff is for the MPC850 with ethernet on SCC2.  Some of
+ * this may be unique to the RPX-Lite configuration.
+ * Note TENA is on Port B.
+ */
+#define	PROFF_ENET	PROFF_SCC2
+#define	CPM_CR_ENET	CPM_CR_CH_SCC2
+#define	SCC_ENET	1
+#define PA_ENET_RXD	((ushort)0x0004)
+#define PA_ENET_TXD	((ushort)0x0008)
+#define PA_ENET_TCLK	((ushort)0x0200)
+#define PA_ENET_RCLK	((ushort)0x0800)
+#if defined(CONFIG_RMU)
+#define PC_ENET_TENA	((uint)0x00000002)	/* PC14 */
+#else
+#define PB_ENET_TENA	((uint)0x00002000)
+#endif
+#define PC_ENET_CLSN	((ushort)0x0040)
+#define PC_ENET_RENA	((ushort)0x0080)
+
+#define SICR_ENET_MASK	((uint)0x0000ff00)
+#define SICR_ENET_CLKRT	((uint)0x00003d00)
+#endif	/* CONFIG_RPXLITE */
+
+/***  SM850  *********************************************************/
+
+/* The SM850 Service Module uses SCC2 for IrDA and SCC3 for Ethernet */
+
+#ifdef CONFIG_SM850
+#define PROFF_ENET	PROFF_SCC3		/* Ethernet on SCC3 */
+#define CPM_CR_ENET	CPM_CR_CH_SCC3
+#define SCC_ENET	2
+#define PB_ENET_RXD	((uint)0x00000004)	/* PB 29 */
+#define PB_ENET_TXD	((uint)0x00000002)	/* PB 30 */
+#define PA_ENET_RCLK	((ushort)0x0100)	/* PA  7 */
+#define PA_ENET_TCLK	((ushort)0x0400)	/* PA  5 */
+
+#define PC_ENET_LBK	((ushort)0x0008)	/* PC 12 */
+#define PC_ENET_TENA	((ushort)0x0004)	/* PC 13 */
+
+#define PC_ENET_RENA	((ushort)0x0800)	/* PC  4 */
+#define PC_ENET_CLSN	((ushort)0x0400)	/* PC  5 */
+
+/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
+ * SCC3.  Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero.
+ */
+#define SICR_ENET_MASK	((uint)0x00FF0000)
+#define SICR_ENET_CLKRT	((uint)0x00260000)
+#endif	/* CONFIG_SM850 */
+
+/***  SPD823TS  ******************************************************/
+
+#ifdef CONFIG_SPD823TS
+/* Bits in parallel I/O port registers that have to be set/cleared
+ * to configure the pins for SCC2 use.
+ */
+#define	PROFF_ENET	PROFF_SCC2		/* Ethernet on SCC2 */
+#define CPM_CR_ENET     CPM_CR_CH_SCC2
+#define	SCC_ENET	1
+#define PA_ENET_MDC	((ushort)0x0001)	/* PA 15 !!! */
+#define PA_ENET_MDIO	((ushort)0x0002)	/* PA 14 !!! */
+#define PA_ENET_RXD	((ushort)0x0004)	/* PA 13 */
+#define PA_ENET_TXD	((ushort)0x0008)	/* PA 12 */
+#define PA_ENET_RCLK	((ushort)0x0200)	/* PA  6 */
+#define PA_ENET_TCLK	((ushort)0x0400)	/* PA  5 */
+
+#define PB_ENET_TENA	((uint)0x00002000)	/* PB 18 */
+
+#define PC_ENET_CLSN	((ushort)0x0040)	/* PC  9 */
+#define PC_ENET_RENA	((ushort)0x0080)	/* PC  8 */
+#define	PC_ENET_RESET	((ushort)0x0100)	/* PC  7 !!! */
+
+/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to
+ * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
+ */
+#define SICR_ENET_MASK	((uint)0x0000ff00)
+#define SICR_ENET_CLKRT	((uint)0x00002E00)
+#endif	/* CONFIG_SPD823TS */
+
+/***  SXNI855T  ******************************************************/
+
+#if defined(CONFIG_SXNI855T)
+
+#ifdef CONFIG_FEC_ENET
+#define	FEC_ENET	/* use FEC for Ethernet */
+#endif	/* CONFIG_FEC_ETHERNET */
+
+#endif	/* CONFIG_SXNI855T */
+
+/***  MVS1, TQM823L/M, TQM850L/M, TQM885D, R360MPI  **********/
+
+#if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \
+    defined(CONFIG_R360MPI) || defined(CONFIG_RBC823)  || \
+    defined(CONFIG_RRVISION)|| defined(CONFIG_TQM823L) || \
+    defined(CONFIG_TQM823M) || defined(CONFIG_TQM850L) || \
+    defined(CONFIG_TQM850M) || defined(CONFIG_TQM885D) || \
+    defined(CONFIG_RRVISION)|| defined(CONFIG_VIRTLAB2)
+
+/* Bits in parallel I/O port registers that have to be set/cleared
+ * to configure the pins for SCC2 use.
+ */
+#define	PROFF_ENET	PROFF_SCC2
+#define	CPM_CR_ENET	CPM_CR_CH_SCC2
+#if (!defined(CONFIG_TK885D))	/* TK885D does not use SCC Ethernet */
+#define	SCC_ENET	1
+#endif
+#define PA_ENET_RXD	((ushort)0x0004)	/* PA 13 */
+#define PA_ENET_TXD	((ushort)0x0008)	/* PA 12 */
+#define PA_ENET_RCLK	((ushort)0x0100)	/* PA  7 */
+#define PA_ENET_TCLK	((ushort)0x0400)	/* PA  5 */
+
+#define PB_ENET_TENA	((uint)0x00002000)	/* PB 18 */
+
+#define PC_ENET_CLSN	((ushort)0x0040)	/* PC  9 */
+#define PC_ENET_RENA	((ushort)0x0080)	/* PC  8 */
+#if defined(CONFIG_R360MPI)
+#define PC_ENET_LBK	((ushort)0x0008)	/* PC 12 */
+#endif   /* CONFIG_R360MPI */
+
+/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
+ * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
+ */
+#define SICR_ENET_MASK	((uint)0x0000ff00)
+#define SICR_ENET_CLKRT	((uint)0x00002600)
+
+# ifdef CONFIG_FEC_ENET		/* Use FEC for Fast Ethernet */
+#define FEC_ENET
+# endif	/* CONFIG_FEC_ENET */
+
+#endif	/* CONFIG_MVS v1, CONFIG_TQM823L/M, CONFIG_TQM850L/M, etc. */
+
+/***  TQM855L/M, TQM860L/M, TQM862L/M, TQM866L/M  *********************/
+
+#if defined(CONFIG_TQM855L) || defined(CONFIG_TQM855M) || \
+    defined(CONFIG_TQM860L) || defined(CONFIG_TQM860M) || \
+    defined(CONFIG_TQM862L) || defined(CONFIG_TQM862M) || \
+    defined(CONFIG_TQM866L) || defined(CONFIG_TQM866M)
+
+# ifdef CONFIG_SCC1_ENET	/* use SCC for 10Mbps Ethernet	*/
+
+/* Bits in parallel I/O port registers that have to be set/cleared
+ * to configure the pins for SCC1 use.
+ */
+#define	PROFF_ENET	PROFF_SCC1
+#define	CPM_CR_ENET	CPM_CR_CH_SCC1
+#define	SCC_ENET	0
+#define PA_ENET_RXD	((ushort)0x0001)	/* PA 15 */
+#define PA_ENET_TXD	((ushort)0x0002)	/* PA 14 */
+#define PA_ENET_RCLK	((ushort)0x0100)	/* PA  7 */
+#define PA_ENET_TCLK	((ushort)0x0400)	/* PA  5 */
+
+#define PC_ENET_TENA	((ushort)0x0001)	/* PC 15 */
+#define PC_ENET_CLSN	((ushort)0x0010)	/* PC 11 */
+#define PC_ENET_RENA	((ushort)0x0020)	/* PC 10 */
+
+/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
+ * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
+ */
+#define SICR_ENET_MASK	((uint)0x000000ff)
+#define SICR_ENET_CLKRT	((uint)0x00000026)
+
+# endif	/* CONFIG_SCC1_ENET */
+
+# ifdef CONFIG_FEC_ENET		/* Use FEC for Fast Ethernet */
+
+#define FEC_ENET
+
+#define PD_MII_TXD1	((ushort)0x1000)	/* PD  3 */
+#define PD_MII_TXD2	((ushort)0x0800)	/* PD  4 */
+#define PD_MII_TXD3	((ushort)0x0400)	/* PD  5 */
+#define PD_MII_RX_DV	((ushort)0x0200)	/* PD  6 */
+#define PD_MII_RX_ERR	((ushort)0x0100)	/* PD  7 */
+#define PD_MII_RX_CLK	((ushort)0x0080)	/* PD  8 */
+#define PD_MII_TXD0	((ushort)0x0040)	/* PD  9 */
+#define PD_MII_RXD0	((ushort)0x0020)	/* PD 10 */
+#define PD_MII_TX_ERR	((ushort)0x0010)	/* PD 11 */
+#define PD_MII_MDC	((ushort)0x0008)	/* PD 12 */
+#define PD_MII_RXD1	((ushort)0x0004)	/* PD 13 */
+#define PD_MII_RXD2	((ushort)0x0002)	/* PD 14 */
+#define PD_MII_RXD3	((ushort)0x0001)	/* PD 15 */
+
+#define PD_MII_MASK	((ushort)0x1FFF)	/* PD 3...15 */
+
+# endif	/* CONFIG_FEC_ENET */
+#endif	/* CONFIG_TQM855L/M, TQM860L/M, TQM862L/M */
+
+/***  V37  **********************************************************/
+
+#ifdef CONFIG_V37
+/* This ENET stuff is for the MPC823 with ethernet on SCC2.  Some of
+ * this may be unique to the Marel V37 configuration.
+ * Note TENA is on Port B.
+ */
+#define	PROFF_ENET	PROFF_SCC2
+#define	CPM_CR_ENET	CPM_CR_CH_SCC2
+#define	SCC_ENET	1
+#define PA_ENET_RXD	((ushort)0x0004)
+#define PA_ENET_TXD	((ushort)0x0008)
+#define PA_ENET_TCLK	((ushort)0x0400)
+#define PA_ENET_RCLK	((ushort)0x0200)
+#define PB_ENET_TENA	((uint)0x00002000)
+#define PC_ENET_CLSN	((ushort)0x0040)
+#define PC_ENET_RENA	((ushort)0x0080)
+
+#define SICR_ENET_MASK	((uint)0x0000ff00)
+#define SICR_ENET_CLKRT	((uint)0x00002e00)
+#endif	/* CONFIG_V37 */
+
+
+/*********************************************************************/
+
+/* SCC Event register as used by Ethernet.
+*/
+#define SCCE_ENET_GRA	((ushort)0x0080)	/* Graceful stop complete */
+#define SCCE_ENET_TXE	((ushort)0x0010)	/* Transmit Error */
+#define SCCE_ENET_RXF	((ushort)0x0008)	/* Full frame received */
+#define SCCE_ENET_BSY	((ushort)0x0004)	/* All incoming buffers full */
+#define SCCE_ENET_TXB	((ushort)0x0002)	/* A buffer was transmitted */
+#define SCCE_ENET_RXB	((ushort)0x0001)	/* A buffer was received */
+
+/* SCC Mode Register (PSMR) as used by Ethernet.
+*/
+#define SCC_PSMR_HBC	((ushort)0x8000)	/* Enable heartbeat */
+#define SCC_PSMR_FC	((ushort)0x4000)	/* Force collision */
+#define SCC_PSMR_RSH	((ushort)0x2000)	/* Receive short frames */
+#define SCC_PSMR_IAM	((ushort)0x1000)	/* Check individual hash */
+#define SCC_PSMR_ENCRC	((ushort)0x0800)	/* Ethernet CRC mode */
+#define SCC_PSMR_PRO	((ushort)0x0200)	/* Promiscuous mode */
+#define SCC_PSMR_BRO	((ushort)0x0100)	/* Catch broadcast pkts */
+#define SCC_PSMR_SBT	((ushort)0x0080)	/* Special backoff timer */
+#define SCC_PSMR_LPB	((ushort)0x0040)	/* Set Loopback mode */
+#define SCC_PSMR_SIP	((ushort)0x0020)	/* Sample Input Pins */
+#define SCC_PSMR_LCW	((ushort)0x0010)	/* Late collision window */
+#define SCC_PSMR_NIB22	((ushort)0x000a)	/* Start frame search */
+#define SCC_PSMR_FDE	((ushort)0x0001)	/* Full duplex enable */
+
+/* Buffer descriptor control/status used by Ethernet receive.
+*/
+#define BD_ENET_RX_EMPTY	((ushort)0x8000)
+#define BD_ENET_RX_WRAP		((ushort)0x2000)
+#define BD_ENET_RX_INTR		((ushort)0x1000)
+#define BD_ENET_RX_LAST		((ushort)0x0800)
+#define BD_ENET_RX_FIRST	((ushort)0x0400)
+#define BD_ENET_RX_MISS		((ushort)0x0100)
+#define BD_ENET_RX_LG		((ushort)0x0020)
+#define BD_ENET_RX_NO		((ushort)0x0010)
+#define BD_ENET_RX_SH		((ushort)0x0008)
+#define BD_ENET_RX_CR		((ushort)0x0004)
+#define BD_ENET_RX_OV		((ushort)0x0002)
+#define BD_ENET_RX_CL		((ushort)0x0001)
+#define BD_ENET_RX_STATS	((ushort)0x013f)	/* All status bits */
+
+/* Buffer descriptor control/status used by Ethernet transmit.
+*/
+#define BD_ENET_TX_READY	((ushort)0x8000)
+#define BD_ENET_TX_PAD		((ushort)0x4000)
+#define BD_ENET_TX_WRAP		((ushort)0x2000)
+#define BD_ENET_TX_INTR		((ushort)0x1000)
+#define BD_ENET_TX_LAST		((ushort)0x0800)
+#define BD_ENET_TX_TC		((ushort)0x0400)
+#define BD_ENET_TX_DEF		((ushort)0x0200)
+#define BD_ENET_TX_HB		((ushort)0x0100)
+#define BD_ENET_TX_LC		((ushort)0x0080)
+#define BD_ENET_TX_RL		((ushort)0x0040)
+#define BD_ENET_TX_RCMASK	((ushort)0x003c)
+#define BD_ENET_TX_UN		((ushort)0x0002)
+#define BD_ENET_TX_CSL		((ushort)0x0001)
+#define BD_ENET_TX_STATS	((ushort)0x03ff)	/* All status bits */
+
+/* SCC as UART
+*/
+typedef struct scc_uart {
+	sccp_t	scc_genscc;
+	uint	scc_res1;	/* Reserved */
+	uint	scc_res2;	/* Reserved */
+	ushort	scc_maxidl;	/* Maximum idle chars */
+	ushort	scc_idlc;	/* temp idle counter */
+	ushort	scc_brkcr;	/* Break count register */
+	ushort	scc_parec;	/* receive parity error counter */
+	ushort	scc_frmec;	/* receive framing error counter */
+	ushort	scc_nosec;	/* receive noise counter */
+	ushort	scc_brkec;	/* receive break condition counter */
+	ushort	scc_brkln;	/* last received break length */
+	ushort	scc_uaddr1;	/* UART address character 1 */
+	ushort	scc_uaddr2;	/* UART address character 2 */
+	ushort	scc_rtemp;	/* Temp storage */
+	ushort	scc_toseq;	/* Transmit out of sequence char */
+	ushort	scc_char1;	/* control character 1 */
+	ushort	scc_char2;	/* control character 2 */
+	ushort	scc_char3;	/* control character 3 */
+	ushort	scc_char4;	/* control character 4 */
+	ushort	scc_char5;	/* control character 5 */
+	ushort	scc_char6;	/* control character 6 */
+	ushort	scc_char7;	/* control character 7 */
+	ushort	scc_char8;	/* control character 8 */
+	ushort	scc_rccm;	/* receive control character mask */
+	ushort	scc_rccr;	/* receive control character register */
+	ushort	scc_rlbc;	/* receive last break character */
+} scc_uart_t;
+
+/* SCC Event and Mask registers when it is used as a UART.
+*/
+#define UART_SCCM_GLR		((ushort)0x1000)
+#define UART_SCCM_GLT		((ushort)0x0800)
+#define UART_SCCM_AB		((ushort)0x0200)
+#define UART_SCCM_IDL		((ushort)0x0100)
+#define UART_SCCM_GRA		((ushort)0x0080)
+#define UART_SCCM_BRKE		((ushort)0x0040)
+#define UART_SCCM_BRKS		((ushort)0x0020)
+#define UART_SCCM_CCR		((ushort)0x0008)
+#define UART_SCCM_BSY		((ushort)0x0004)
+#define UART_SCCM_TX		((ushort)0x0002)
+#define UART_SCCM_RX		((ushort)0x0001)
+
+/* The SCC PSMR when used as a UART.
+*/
+#define SCU_PSMR_FLC		((ushort)0x8000)
+#define SCU_PSMR_SL		((ushort)0x4000)
+#define SCU_PSMR_CL		((ushort)0x3000)
+#define SCU_PSMR_UM		((ushort)0x0c00)
+#define SCU_PSMR_FRZ		((ushort)0x0200)
+#define SCU_PSMR_RZS		((ushort)0x0100)
+#define SCU_PSMR_SYN		((ushort)0x0080)
+#define SCU_PSMR_DRT		((ushort)0x0040)
+#define SCU_PSMR_PEN		((ushort)0x0010)
+#define SCU_PSMR_RPM		((ushort)0x000c)
+#define SCU_PSMR_REVP		((ushort)0x0008)
+#define SCU_PSMR_TPM		((ushort)0x0003)
+#define SCU_PSMR_TEVP		((ushort)0x0003)
+
+/* CPM Transparent mode SCC.
+ */
+typedef struct scc_trans {
+	sccp_t	st_genscc;
+	uint	st_cpres;	/* Preset CRC */
+	uint	st_cmask;	/* Constant mask for CRC */
+} scc_trans_t;
+
+#define BD_SCC_TX_LAST		((ushort)0x0800)
+
+/* IIC parameter RAM.
+*/
+typedef struct iic {
+	ushort	iic_rbase;	/* Rx Buffer descriptor base address */
+	ushort	iic_tbase;	/* Tx Buffer descriptor base address */
+	u_char	iic_rfcr;	/* Rx function code */
+	u_char	iic_tfcr;	/* Tx function code */
+	ushort	iic_mrblr;	/* Max receive buffer length */
+	uint	iic_rstate;	/* Internal */
+	uint	iic_rdp;	/* Internal */
+	ushort	iic_rbptr;	/* Internal */
+	ushort	iic_rbc;	/* Internal */
+	uint	iic_rxtmp;	/* Internal */
+	uint	iic_tstate;	/* Internal */
+	uint	iic_tdp;	/* Internal */
+	ushort	iic_tbptr;	/* Internal */
+	ushort	iic_tbc;	/* Internal */
+	uint	iic_txtmp;	/* Internal */
+	uint	iic_res;	/* reserved */
+	ushort	iic_rpbase;	/* Relocation pointer */
+	ushort	iic_res2;	/* reserved */
+} iic_t;
+
+/* SPI parameter RAM.
+*/
+typedef struct spi {
+	ushort	spi_rbase;	/* Rx Buffer descriptor base address */
+	ushort	spi_tbase;	/* Tx Buffer descriptor base address */
+	u_char	spi_rfcr;	/* Rx function code */
+	u_char	spi_tfcr;	/* Tx function code */
+	ushort	spi_mrblr;	/* Max receive buffer length */
+	uint	spi_rstate;	/* Internal */
+	uint	spi_rdp;	/* Internal */
+	ushort	spi_rbptr;	/* Internal */
+	ushort	spi_rbc;	/* Internal */
+	uint	spi_rxtmp;	/* Internal */
+	uint	spi_tstate;	/* Internal */
+	uint	spi_tdp;	/* Internal */
+	ushort	spi_tbptr;	/* Internal */
+	ushort	spi_tbc;	/* Internal */
+	uint	spi_txtmp;	/* Internal */
+	uint	spi_res;
+	ushort	spi_rpbase;	/* Relocation pointer */
+	ushort	spi_res2;
+} spi_t;
+
+/* SPI Mode register.
+*/
+#define SPMODE_LOOP	((ushort)0x4000)	/* Loopback */
+#define SPMODE_CI	((ushort)0x2000)	/* Clock Invert */
+#define SPMODE_CP	((ushort)0x1000)	/* Clock Phase */
+#define SPMODE_DIV16	((ushort)0x0800)	/* BRG/16 mode */
+#define SPMODE_REV	((ushort)0x0400)	/* Reversed Data */
+#define SPMODE_MSTR	((ushort)0x0200)	/* SPI Master */
+#define SPMODE_EN	((ushort)0x0100)	/* Enable */
+#define SPMODE_LENMSK	((ushort)0x00f0)	/* character length */
+#define SPMODE_PMMSK	((ushort)0x000f)	/* prescale modulus */
+
+#define SPMODE_LEN(x)	((((x)-1)&0xF)<<4)
+#define SPMODE_PM(x)	((x) &0xF)
+
+/* HDLC parameter RAM.
+*/
+
+typedef struct hdlc_pram_s {
+	/*
+	 * SCC parameter RAM
+	 */
+	ushort	rbase;		/* Rx Buffer descriptor base address */
+	ushort	tbase;		/* Tx Buffer descriptor base address */
+	uchar	rfcr;		/* Rx function code */
+	uchar	tfcr;		/* Tx function code */
+	ushort	mrblr;		/* Rx buffer length */
+	ulong	rstate;		/* Rx internal state */
+	ulong	rptr;		/* Rx internal data pointer */
+	ushort	rbptr;		/* rb BD Pointer */
+	ushort	rcount;		/* Rx internal byte count */
+	ulong	rtemp;		/* Rx temp */
+	ulong	tstate;		/* Tx internal state */
+	ulong	tptr;		/* Tx internal data pointer */
+	ushort	tbptr;		/* Tx BD pointer */
+	ushort	tcount;		/* Tx byte count */
+	ulong	ttemp;		/* Tx temp */
+	ulong	rcrc;		/* temp receive CRC */
+	ulong	tcrc;		/* temp transmit CRC */
+	/*
+	 * HDLC specific parameter RAM
+	 */
+	uchar	res[4];		/* reserved */
+	ulong	c_mask;		/* CRC constant */
+	ulong	c_pres;		/* CRC preset */
+	ushort	disfc;		/* discarded frame counter */
+	ushort	crcec;		/* CRC error counter */
+	ushort	abtsc;		/* abort sequence counter */
+	ushort	nmarc;		/* nonmatching address rx cnt */
+	ushort	retrc;		/* frame retransmission cnt */
+	ushort	mflr;		/* maximum frame length reg */
+	ushort	max_cnt;	/* maximum length counter */
+	ushort	rfthr;		/* received frames threshold */
+	ushort	rfcnt;		/* received frames count */
+	ushort	hmask;		/* user defined frm addr mask */
+	ushort	haddr1;		/* user defined frm address 1 */
+	ushort	haddr2;		/* user defined frm address 2 */
+	ushort	haddr3;		/* user defined frm address 3 */
+	ushort	haddr4;		/* user defined frm address 4 */
+	ushort	tmp;		/* temp */
+	ushort	tmp_mb;		/* temp */
+} hdlc_pram_t;
+
+/* CPM interrupts.  There are nearly 32 interrupts generated by CPM
+ * channels or devices.  All of these are presented to the PPC core
+ * as a single interrupt.  The CPM interrupt handler dispatches its
+ * own handlers, in a similar fashion to the PPC core handler.  We
+ * use the table as defined in the manuals (i.e. no special high
+ * priority and SCC1 == SCCa, etc...).
+ */
+#define CPMVEC_NR		32
+#define CPMVEC_OFFSET           0x00010000
+#define CPMVEC_PIO_PC15		((ushort)0x1f | CPMVEC_OFFSET)
+#define CPMVEC_SCC1		((ushort)0x1e | CPMVEC_OFFSET)
+#define CPMVEC_SCC2		((ushort)0x1d | CPMVEC_OFFSET)
+#define CPMVEC_SCC3		((ushort)0x1c | CPMVEC_OFFSET)
+#define CPMVEC_SCC4		((ushort)0x1b | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC14		((ushort)0x1a | CPMVEC_OFFSET)
+#define CPMVEC_TIMER1		((ushort)0x19 | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC13		((ushort)0x18 | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC12		((ushort)0x17 | CPMVEC_OFFSET)
+#define CPMVEC_SDMA_CB_ERR	((ushort)0x16 | CPMVEC_OFFSET)
+#define CPMVEC_IDMA1		((ushort)0x15 | CPMVEC_OFFSET)
+#define CPMVEC_IDMA2		((ushort)0x14 | CPMVEC_OFFSET)
+#define CPMVEC_TIMER2		((ushort)0x12 | CPMVEC_OFFSET)
+#define CPMVEC_RISCTIMER	((ushort)0x11 | CPMVEC_OFFSET)
+#define CPMVEC_I2C		((ushort)0x10 | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC11		((ushort)0x0f | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC10		((ushort)0x0e | CPMVEC_OFFSET)
+#define CPMVEC_TIMER3		((ushort)0x0c | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC9		((ushort)0x0b | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC8		((ushort)0x0a | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC7		((ushort)0x09 | CPMVEC_OFFSET)
+#define CPMVEC_TIMER4		((ushort)0x07 | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC6		((ushort)0x06 | CPMVEC_OFFSET)
+#define CPMVEC_SPI		((ushort)0x05 | CPMVEC_OFFSET)
+#define CPMVEC_SMC1		((ushort)0x04 | CPMVEC_OFFSET)
+#define CPMVEC_SMC2		((ushort)0x03 | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC5		((ushort)0x02 | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC4		((ushort)0x01 | CPMVEC_OFFSET)
+#define CPMVEC_ERROR		((ushort)0x00 | CPMVEC_OFFSET)
+
+extern void irq_install_handler(int vec, void (*handler)(void *), void *dev_id);
+
+/* CPM interrupt configuration vector.
+*/
+#define	CICR_SCD_SCC4		((uint)0x00c00000)	/* SCC4 @ SCCd */
+#define	CICR_SCC_SCC3		((uint)0x00200000)	/* SCC3 @ SCCc */
+#define	CICR_SCB_SCC2		((uint)0x00040000)	/* SCC2 @ SCCb */
+#define	CICR_SCA_SCC1		((uint)0x00000000)	/* SCC1 @ SCCa */
+#define CICR_IRL_MASK		((uint)0x0000e000)	/* Core interrrupt */
+#define CICR_HP_MASK		((uint)0x00001f00)	/* Hi-pri int. */
+#define CICR_IEN		((uint)0x00000080)	/* Int. enable */
+#define CICR_SPS		((uint)0x00000001)	/* SCC Spread */
+#endif /* __CPM_8XX__ */
diff --git a/qemu/roms/u-boot/include/compiler.h b/qemu/roms/u-boot/include/compiler.h
new file mode 100644
index 000000000..0734ed494
--- /dev/null
+++ b/qemu/roms/u-boot/include/compiler.h
@@ -0,0 +1,137 @@
+/*
+ * Keep all the ugly #ifdef for system stuff here
+ */
+
+#ifndef __COMPILER_H__
+#define __COMPILER_H__
+
+#include <stddef.h>
+
+#ifdef USE_HOSTCC
+
+#if defined(__BEOS__)	 || \
+    defined(__NetBSD__)  || \
+    defined(__FreeBSD__) || \
+    defined(__sun__)	 || \
+    defined(__APPLE__)
+# include <inttypes.h>
+#elif defined(__linux__) || defined(__WIN32__) || defined(__MINGW32__)
+# include <stdint.h>
+#endif
+
+#include <errno.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+
+#if !defined(__WIN32__) && !defined(__MINGW32__)
+# include <sys/mman.h>
+#endif
+
+/* Not all systems (like Windows) has this define, and yes
+ * we do replace/emulate mmap() on those systems ...
+ */
+#ifndef MAP_FAILED
+# define MAP_FAILED ((void *)-1)
+#endif
+
+#include <fcntl.h>
+#ifndef O_BINARY		/* should be define'd on __WIN32__ */
+#define O_BINARY	0
+#endif
+
+#ifdef __linux__
+# include <endian.h>
+# include <byteswap.h>
+#elif defined(__MACH__) || defined(__FreeBSD__)
+# include <machine/endian.h>
+typedef unsigned long ulong;
+#endif
+
+typedef uint8_t __u8;
+typedef uint16_t __u16;
+typedef uint32_t __u32;
+typedef unsigned int uint;
+
+#define uswap_16(x) \
+	((((x) & 0xff00) >> 8) | \
+	 (((x) & 0x00ff) << 8))
+#define uswap_32(x) \
+	((((x) & 0xff000000) >> 24) | \
+	 (((x) & 0x00ff0000) >>  8) | \
+	 (((x) & 0x0000ff00) <<  8) | \
+	 (((x) & 0x000000ff) << 24))
+#define _uswap_64(x, sfx) \
+	((((x) & 0xff00000000000000##sfx) >> 56) | \
+	 (((x) & 0x00ff000000000000##sfx) >> 40) | \
+	 (((x) & 0x0000ff0000000000##sfx) >> 24) | \
+	 (((x) & 0x000000ff00000000##sfx) >>  8) | \
+	 (((x) & 0x00000000ff000000##sfx) <<  8) | \
+	 (((x) & 0x0000000000ff0000##sfx) << 24) | \
+	 (((x) & 0x000000000000ff00##sfx) << 40) | \
+	 (((x) & 0x00000000000000ff##sfx) << 56))
+#if defined(__GNUC__)
+# define uswap_64(x) _uswap_64(x, ull)
+#else
+# define uswap_64(x) _uswap_64(x, )
+#endif
+
+#if __BYTE_ORDER == __LITTLE_ENDIAN
+# define cpu_to_le16(x)		(x)
+# define cpu_to_le32(x)		(x)
+# define cpu_to_le64(x)		(x)
+# define le16_to_cpu(x)		(x)
+# define le32_to_cpu(x)		(x)
+# define le64_to_cpu(x)		(x)
+# define cpu_to_be16(x)		uswap_16(x)
+# define cpu_to_be32(x)		uswap_32(x)
+# define cpu_to_be64(x)		uswap_64(x)
+# define be16_to_cpu(x)		uswap_16(x)
+# define be32_to_cpu(x)		uswap_32(x)
+# define be64_to_cpu(x)		uswap_64(x)
+#else
+# define cpu_to_le16(x)		uswap_16(x)
+# define cpu_to_le32(x)		uswap_32(x)
+# define cpu_to_le64(x)		uswap_64(x)
+# define le16_to_cpu(x)		uswap_16(x)
+# define le32_to_cpu(x)		uswap_32(x)
+# define le64_to_cpu(x)		uswap_64(x)
+# define cpu_to_be16(x)		(x)
+# define cpu_to_be32(x)		(x)
+# define cpu_to_be64(x)		(x)
+# define be16_to_cpu(x)		(x)
+# define be32_to_cpu(x)		(x)
+# define be64_to_cpu(x)		(x)
+#endif
+
+#else /* !USE_HOSTCC */
+
+#include <linux/string.h>
+#include <linux/types.h>
+#include <asm/byteorder.h>
+
+#if __SIZEOF_LONG__ == 8
+# define __WORDSIZE	64
+#elif __SIZEOF_LONG__ == 4
+# define __WORDSIZE	32
+#else
+/*
+ * Assume 32-bit for now - only newer toolchains support this feature and
+ * this is only required for sandbox support at present.
+ */
+#define __WORDSIZE	32
+#endif
+
+/* Type for `void *' pointers. */
+typedef unsigned long int uintptr_t;
+
+#endif /* USE_HOSTCC */
+
+/* compiler options */
+#define uninitialized_var(x)		x = x
+
+#define likely(x)	__builtin_expect(!!(x), 1)
+#define unlikely(x)	__builtin_expect(!!(x), 0)
+
+#endif
diff --git a/qemu/roms/u-boot/include/config_cmd_all.h b/qemu/roms/u-boot/include/config_cmd_all.h
new file mode 100644
index 000000000..2c2a05bce
--- /dev/null
+++ b/qemu/roms/u-boot/include/config_cmd_all.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License Version 2. This file is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef _CONFIG_CMD_ALL_H
+#define _CONFIG_CMD_ALL_H
+
+/*
+ * Alphabetical list of all possible commands.
+ */
+
+#define CONFIG_CMD_AMBAPP	/* AMBA Plug & Play Bus print utility */
+#define CONFIG_CMD_ASKENV	/* ask for env variable		*/
+#define CONFIG_CMD_BDI		/* bdinfo			*/
+#define CONFIG_CMD_BEDBUG	/* Include BedBug Debugger	*/
+#define CONFIG_CMD_BMP		/* BMP support			*/
+#define CONFIG_CMD_BOOTD	/* bootd			*/
+#define CONFIG_CMD_BOOTZ	/* boot zImage			*/
+#define CONFIG_CMD_BSP		/* Board Specific functions	*/
+#define CONFIG_CMD_CACHE	/* icache, dcache		*/
+#define CONFIG_CMD_CDP		/* Cisco Discovery Protocol	*/
+#define CONFIG_CMD_CLK		/* Clock support		*/
+#define CONFIG_CMD_CONSOLE	/* coninfo			*/
+#define CONFIG_CMD_DATE		/* support for RTC, date/time...*/
+#define CONFIG_CMD_DHCP		/* DHCP Support			*/
+#define CONFIG_CMD_DIAG		/* Diagnostics			*/
+#define CONFIG_CMD_DISPLAY	/* Display support		*/
+#define CONFIG_CMD_DOC		/* Disk-On-Chip Support		*/
+#define CONFIG_CMD_DTT		/* Digital Therm and Thermostat */
+#define CONFIG_CMD_ECHO		/* echo arguments		*/
+#define CONFIG_CMD_EDITENV	/* editenv			*/
+#define CONFIG_CMD_EEPROM	/* EEPROM read/write support	*/
+#define CONFIG_CMD_ELF		/* ELF (VxWorks) load/boot cmd	*/
+#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
+#define CONFIG_CMD_FAT		/* FAT support			*/
+#define CONFIG_CMD_FDC		/* Floppy Disk Support		*/
+#define CONFIG_CMD_FLASH	/* flinfo, erase, protect	*/
+#define CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
+#define CONFIG_CMD_FUSE		/* Device fuse support		*/
+#define CONFIG_CMD_GETTIME	/* Get time since boot         */
+#define CONFIG_CMD_HASH		/* calculate hash / digest	*/
+#define CONFIG_CMD_HWFLOW	/* RTS/CTS hw flow control	*/
+#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
+#define CONFIG_CMD_IDE		/* IDE harddisk support		*/
+#define CONFIG_CMD_IMI		/* iminfo			*/
+#define CONFIG_CMD_IMLS		/* List all found images	*/
+#define CONFIG_CMD_IMMAP	/* IMMR dump support		*/
+#define CONFIG_CMD_IO		/* Access to X86 IO space	*/
+#define CONFIG_CMD_IRQ		/* irqinfo			*/
+#define CONFIG_CMD_ITEST	/* Integer (and string) test	*/
+#define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
+#define CONFIG_CMD_KGDB		/* kgdb				*/
+#define CONFIG_CMD_LICENSE	/* console license display	*/
+#define CONFIG_CMD_LOADB	/* loadb			*/
+#define CONFIG_CMD_LOADS	/* loads			*/
+#define CONFIG_CMD_MEMINFO	/* meminfo			*/
+#define CONFIG_CMD_MEMORY	/* md mm nm mw cp cmp crc base loop */
+#define CONFIG_CMD_MEMTEST	/* mtest			*/
+#define CONFIG_CMD_MFSL		/* FSL support for Microblaze	*/
+#define CONFIG_CMD_MII		/* MII support			*/
+#define CONFIG_CMD_MISC		/* Misc functions like sleep etc*/
+#define CONFIG_CMD_MMC		/* MMC support			*/
+#define CONFIG_CMD_MTDPARTS	/* mtd parts support		*/
+#define CONFIG_CMD_NAND		/* NAND support			*/
+#define CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot	*/
+#define CONFIG_CMD_NFS		/* NFS support			*/
+#define CONFIG_CMD_ONENAND	/* OneNAND support		*/
+#define CONFIG_CMD_PCI		/* pciinfo			*/
+#define CONFIG_CMD_PCMCIA	/* PCMCIA support		*/
+#define CONFIG_CMD_PING		/* ping support			*/
+#define CONFIG_CMD_PORTIO	/* Port I/O			*/
+#define CONFIG_CMD_REGINFO	/* Register dump		*/
+#define CONFIG_CMD_REISER	/* Reiserfs support		*/
+#define CONFIG_CMD_RARP		/* rarpboot support		*/
+#define CONFIG_CMD_READ		/* Read data from partition	*/
+#define CONFIG_CMD_RUN		/* run command in env variable	*/
+#define CONFIG_CMD_SANDBOX	/* sb command to access sandbox features */
+#define CONFIG_CMD_SAVEENV	/* saveenv			*/
+#define CONFIG_CMD_SAVES	/* save S record dump		*/
+#define CONFIG_CMD_SCSI		/* SCSI Support			*/
+#define CONFIG_CMD_SDRAM	/* SDRAM DIMM SPD info printout */
+#define CONFIG_CMD_SETEXPR	/* setexpr support		*/
+#define CONFIG_CMD_SETGETDCR	/* DCR support on 4xx		*/
+#define CONFIG_CMD_SNTP		/* SNTP support			*/
+#define CONFIG_CMD_SOURCE	/* "source" command support	*/
+#define CONFIG_CMD_SPI		/* SPI utility			*/
+#define CONFIG_CMD_TERMINAL	/* built-in Serial Terminal	*/
+#define CONFIG_CMD_UBI		/* UBI Support			*/
+#define CONFIG_CMD_UBIFS	/* UBIFS Support		*/
+#define CONFIG_CMD_UNIVERSE	/* Tundra Universe Support	*/
+#define CONFIG_CMD_UNZIP	/* unzip from memory to memory	*/
+#define CONFIG_CMD_USB		/* USB Support			*/
+#define CONFIG_CMD_XIMG		/* Load part of Multi Image	*/
+#define CONFIG_CMD_ZFS		/* ZFS Support			*/
+
+#endif	/* _CONFIG_CMD_ALL_H */
diff --git a/qemu/roms/u-boot/include/config_cmd_default.h b/qemu/roms/u-boot/include/config_cmd_default.h
new file mode 100644
index 000000000..73c9544ea
--- /dev/null
+++ b/qemu/roms/u-boot/include/config_cmd_default.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License Version 2. This file is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef _CONFIG_CMD_DEFAULT_H
+#define _CONFIG_CMD_DEFAULT_H
+
+/*
+ * Alphabetical list of all commands that are configured by default.
+ * This is essentially all commands minus those that are considered
+ * "non-standard" for some reason (memory hogs, requires special
+ * hardware, not fully tested, etc.).
+ */
+
+#define CONFIG_CMD_BDI		/* bdinfo			*/
+#define CONFIG_CMD_BOOTD	/* bootd			*/
+#define CONFIG_CMD_CONSOLE	/* coninfo			*/
+#define CONFIG_CMD_ECHO		/* echo arguments		*/
+#define CONFIG_CMD_EDITENV	/* editenv			*/
+#define CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
+#define CONFIG_CMD_IMI		/* iminfo			*/
+#define CONFIG_CMD_ITEST	/* Integer (and string) test	*/
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_CMD_FLASH	/* flinfo, erase, protect	*/
+#define CONFIG_CMD_IMLS		/* List all found images	*/
+#endif
+#define CONFIG_CMD_LOADB	/* loadb			*/
+#define CONFIG_CMD_LOADS	/* loads			*/
+#define CONFIG_CMD_MEMORY	/* md mm nm mw cp cmp crc base loop */
+#define CONFIG_CMD_MISC		/* Misc functions like sleep etc*/
+#define CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot	*/
+#define CONFIG_CMD_NFS		/* NFS support			*/
+#define CONFIG_CMD_RUN		/* run command in env variable	*/
+#define CONFIG_CMD_SAVEENV	/* saveenv			*/
+#define CONFIG_CMD_SETGETDCR	/* DCR support on 4xx		*/
+#define CONFIG_CMD_SOURCE	/* "source" command support	*/
+#define CONFIG_CMD_XIMG		/* Load part of Multi Image	*/
+
+#endif	/* _CONFIG_CMD_DEFAULT_H */
diff --git a/qemu/roms/u-boot/include/config_cmd_defaults.h b/qemu/roms/u-boot/include/config_cmd_defaults.h
new file mode 100644
index 000000000..a55b268b9
--- /dev/null
+++ b/qemu/roms/u-boot/include/config_cmd_defaults.h
@@ -0,0 +1,18 @@
+/*
+ * config_cmd_defaults.h - sane defaults for everyone
+ *
+ * Copyright (c) 2010-2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef _CONFIG_CMD_DEFAULTS_H_
+#define _CONFIG_CMD_DEFAULTS_H_
+
+#define CONFIG_CMD_BOOTM 1
+#define CONFIG_CMD_CRC32 1
+#define CONFIG_CMD_EXPORTENV 1
+#define CONFIG_CMD_GO 1
+#define CONFIG_CMD_IMPORTENV 1
+
+#endif
diff --git a/qemu/roms/u-boot/include/config_defaults.h b/qemu/roms/u-boot/include/config_defaults.h
new file mode 100644
index 000000000..ad08c1d33
--- /dev/null
+++ b/qemu/roms/u-boot/include/config_defaults.h
@@ -0,0 +1,23 @@
+/*
+ * config_defaults.h - sane defaults for everyone
+ *
+ * Copyright (c) 2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef _CONFIG_DEFAULTS_H_
+#define _CONFIG_DEFAULTS_H_
+
+/* Support bootm-ing different OSes */
+#define CONFIG_BOOTM_LINUX 1
+#define CONFIG_BOOTM_NETBSD 1
+#define CONFIG_BOOTM_PLAN9 1
+#define CONFIG_BOOTM_RTEMS 1
+#define CONFIG_BOOTM_VXWORKS 1
+
+#define CONFIG_GZIP 1
+#define CONFIG_ZLIB 1
+#define CONFIG_PARTITIONS 1
+
+#endif
diff --git a/qemu/roms/u-boot/include/config_distro_defaults.h b/qemu/roms/u-boot/include/config_distro_defaults.h
new file mode 100644
index 000000000..5d18a4b90
--- /dev/null
+++ b/qemu/roms/u-boot/include/config_distro_defaults.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright 2013-2014 Red Hat, Inc.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _CONFIG_CMD_DISTRO_DEFAULTS_H
+#define _CONFIG_CMD_DISTRO_DEFAULTS_H
+
+/*
+ * List of all commands and options that when defined enables support for
+ * features required by distros to support boards in a standardised and
+ * consitant manner.
+ */
+
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_PXE
+#define CONFIG_BOOTP_SUBNETMASK
+
+#if defined(__arm__)
+#define CONFIG_BOOTP_PXE_CLIENTARCH     0x100
+#if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__)
+#define CONFIG_BOOTP_VCI_STRING         "U-boot.armv7"
+#else
+#define CONFIG_BOOTP_VCI_STRING         "U-boot.arm"
+#endif
+#endif
+
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_PXE
+
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_BOOTDELAY     2
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_MENU
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+#define CONFIG_SUPPORT_RAW_INITRD
+#define CONFIG_SYS_HUSH_PARSER
+
+#endif	/* _CONFIG_CMD_DISTRO_DEFAULTS_H */
diff --git a/qemu/roms/u-boot/include/config_fallbacks.h b/qemu/roms/u-boot/include/config_fallbacks.h
new file mode 100644
index 000000000..b304a4103
--- /dev/null
+++ b/qemu/roms/u-boot/include/config_fallbacks.h
@@ -0,0 +1,86 @@
+/*
+ * Copyright 2012 Texas Instruments
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License Version 2. This file is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __CONFIG_FALLBACKS_H
+#define __CONFIG_FALLBACKS_H
+
+#ifdef CONFIG_SPL
+#ifdef CONFIG_SPL_PAD_TO
+#ifdef CONFIG_SPL_MAX_SIZE
+#if CONFIG_SPL_PAD_TO && CONFIG_SPL_PAD_TO < CONFIG_SPL_MAX_SIZE
+#error CONFIG_SPL_PAD_TO < CONFIG_SPL_MAX_SIZE
+#endif
+#endif
+#else
+#ifdef CONFIG_SPL_MAX_SIZE
+#define CONFIG_SPL_PAD_TO	CONFIG_SPL_MAX_SIZE
+#else
+#define CONFIG_SPL_PAD_TO	0
+#endif
+#endif
+#endif
+
+#ifndef CONFIG_SYS_BAUDRATE_TABLE
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#endif
+
+#if defined(CONFIG_CMD_FAT) && !defined(CONFIG_FS_FAT)
+#define CONFIG_FS_FAT
+#endif
+
+#if (defined(CONFIG_CMD_EXT4) || defined(CONFIG_CMD_EXT2)) && \
+						!defined(CONFIG_FS_EXT4)
+#define CONFIG_FS_EXT4
+#endif
+
+#if defined(CONFIG_CMD_EXT4_WRITE) && !defined(CONFIG_EXT4_WRITE)
+#define CONFIG_EXT4_WRITE
+#endif
+
+/* Rather than repeat this expression each time, add a define for it */
+#if defined(CONFIG_CMD_IDE) || \
+	defined(CONFIG_CMD_SATA) || \
+	defined(CONFIG_CMD_SCSI) || \
+	defined(CONFIG_CMD_USB) || \
+	defined(CONFIG_CMD_PART) || \
+	defined(CONFIG_CMD_GPT) || \
+	defined(CONFIG_MMC) || \
+	defined(CONFIG_SYSTEMACE) || \
+	defined(CONFIG_SANDBOX)
+#define HAVE_BLOCK_DEVICE
+#endif
+
+#if (defined(CONFIG_PARTITION_UUIDS) || \
+	defined(CONFIG_EFI_PARTITION) || \
+	defined(CONFIG_RANDOM_UUID) || \
+	defined(CONFIG_CMD_UUID) || \
+	defined(CONFIG_BOOTP_PXE)) && \
+	!defined(CONFIG_LIB_UUID)
+#define CONFIG_LIB_UUID
+#endif
+
+#if (defined(CONFIG_RANDOM_UUID) || \
+	defined(CONFIG_CMD_UUID)) && \
+	(!defined(CONFIG_LIB_RAND) && \
+	!defined(CONFIG_LIB_HW_RAND))
+#define CONFIG_LIB_RAND
+#endif
+
+#if defined(CONFIG_API) && defined(CONFIG_LCD)
+#define CONFIG_CMD_BMP
+#endif
+
+#ifndef CONFIG_SYS_PROMPT
+#define CONFIG_SYS_PROMPT	"=> "
+#endif
+
+#ifndef CONFIG_SYS_HZ
+#define CONFIG_SYS_HZ		1000
+#endif
+
+#endif	/* __CONFIG_FALLBACKS_H */
diff --git a/qemu/roms/u-boot/include/config_phylib_all_drivers.h b/qemu/roms/u-boot/include/config_phylib_all_drivers.h
new file mode 100644
index 000000000..12828c67e
--- /dev/null
+++ b/qemu/roms/u-boot/include/config_phylib_all_drivers.h
@@ -0,0 +1,34 @@
+/*
+ * Enable all PHYs
+ *
+ * This software may be used and distributed according to the
+ * terms of the GNU Public License, Version 2, incorporated
+ * herein by reference.
+ *
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * author Andy Fleming
+ *
+ */
+#ifndef _CONFIG_PHYLIB_ALL_H
+#define _CONFIG_PHYLIB_ALL_H
+
+#ifdef CONFIG_PHYLIB
+
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_MARVELL
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_BROADCOM
+#define CONFIG_PHY_DAVICOM
+#define CONFIG_PHY_REALTEK
+#define CONFIG_PHY_NATSEMI
+#define CONFIG_PHY_LXT
+#define CONFIG_PHY_ATHEROS
+#define CONFIG_PHY_SMSC
+
+#ifdef CONFIG_PHYLIB_10G
+#define CONFIG_PHY_TERANETICS
+#endif /* CONFIG_PHYLIB_10G */
+
+#endif /* CONFIG_PHYLIB */
+
+#endif /*_CONFIG_PHYLIB_ALL_H */
diff --git a/qemu/roms/u-boot/include/config_uncmd_spl.h b/qemu/roms/u-boot/include/config_uncmd_spl.h
new file mode 100644
index 000000000..9cb7a9a1f
--- /dev/null
+++ b/qemu/roms/u-boot/include/config_uncmd_spl.h
@@ -0,0 +1,24 @@
+/*
+ * (C) Copyright 2012
+ * Ilya Yanok, ilya.yanok@gmail.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_UNCMD_SPL_H__
+#define __CONFIG_UNCMD_SPL_H__
+
+#ifdef CONFIG_SPL_BUILD
+/* SPL needs only BOOTP + TFTP so undefine other stuff to save space */
+#undef CONFIG_CMD_CDP
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_DNS
+#undef CONFIG_CMD_LINK_LOCAL
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_PING
+#undef CONFIG_CMD_RARP
+#undef CONFIG_CMD_SNTP
+#undef CONFIG_CMD_TFTPPUT
+#undef CONFIG_CMD_TFTPSRV
+#endif /* CONFIG_SPL_BUILD */
+#endif /* __CONFIG_UNCMD_SPL_H__ */
diff --git a/qemu/roms/u-boot/include/configs/A3000.h b/qemu/roms/u-boot/include/configs/A3000.h
new file mode 100644
index 000000000..35e3e6fa8
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/A3000.h
@@ -0,0 +1,293 @@
+/*
+ * (C) Copyright 2001, 2002, 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Configuration settings for the A-3000 board (Artis Microsystems Inc.).
+ * http://artismicro.com
+ */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC8245		1
+#define CONFIG_A3000		1
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
+
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		9600
+
+#define CONFIG_BOOTDELAY	5
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#undef CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"A3000> "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+
+/* Print Buffer Size
+ */
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	8		/* Max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_LOAD_ADDR	0x00400000	/* Default load address		*/
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_HARD_I2C		1		/* To enable I2C support */
+#undef	CONFIG_SYS_I2C_SOFT			/* I2C bit-banged */
+#define CONFIG_SYS_I2C_SPEED		400000		/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#undef	CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
+
+
+/* #define CONFIG_TULIP */
+/* #define CONFIG_EEPRO100 */
+#define CONFIG_NATSEMI
+
+#define PCI_ENET0_IOADDR		0x80000000
+#define PCI_ENET0_MEMADDR		0x80000000
+#define PCI_ENET1_IOADDR		0x81000000
+#define PCI_ENET1_MEMADDR		0x81000000
+#define PCI_ENET2_IOADDR		0x82000000
+#define PCI_ENET2_MEMADDR		0x82000000
+#define PCI_ENET3_IOADDR		0x83000000
+#define PCI_ENET3_MEMADDR		0x83000000
+
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE			0x00000000
+
+#define CONFIG_SYS_FLASH_BASE0_PRELIM		0xFF000000	/* FLASH bank on RCS#0 */
+#define CONFIG_SYS_FLASH_BASE1_PRELIM		0xFF000000	/* FLASH bank on RCS#1 */
+#define CONFIG_SYS_FLASH_BASE			CONFIG_SYS_FLASH_BASE0_PRELIM
+#define CONFIG_SYS_FLASH_BANKS			{ CONFIG_SYS_FLASH_BASE0_PRELIM }
+
+/* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the
+ * reset vector is actually located at FFB00100, but the 8245
+ * takes care of us.
+ */
+#define CONFIG_SYS_RESET_ADDRESS   0xFFF00100
+
+#define CONFIG_SYS_EUMB_ADDR	    0xFC000000
+
+#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN	    (128 << 10) /* Reserve 128 kB for malloc()	*/
+
+#define CONFIG_SYS_MEMTEST_START   0x00004000	/* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END	    0x02000000	/* 0 ... 32 MB in DRAM		*/
+
+	/* Maximum amount of RAM.
+	 */
+#define CONFIG_SYS_MAX_RAM_SIZE    0x04000000	/* 0 .. 128 MB of (S)DRAM */
+
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+#undef CONFIG_SYS_RAMBOOT
+#else
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_EUMB_ADDR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_EUMB_ADDR + 0x4600)
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area
+ */
+
+/* #define CONFIG_SYS_MONITOR_BASE	   CONFIG_SYS_TEXT_BASE */
+#define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE      0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ * For the detail description refer to the MPC8240 user's manual.
+ */
+
+#define CONFIG_SYS_CLK_FREQ  33333333	/* external frequency to pll */
+
+	/* Bit-field values for MCCR1.
+	 */
+#define CONFIG_SYS_ROMNAL	    7
+#define CONFIG_SYS_ROMFAL	    11
+#define CONFIG_SYS_DBUS_SIZE	    0x3
+
+	/* Bit-field values for MCCR2.
+	 */
+#define CONFIG_SYS_TSWAIT	    0x5		    /* Transaction Start Wait States timer */
+#define CONFIG_SYS_REFINT	    0x400	    /* Refresh interval	FIXME: was 0t430		*/
+
+	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
+	 */
+#define CONFIG_SYS_BSTOPRE	    121
+
+	/* Bit-field values for MCCR3.
+	 */
+#define CONFIG_SYS_REFREC	    8	    /* Refresh to activate interval */
+
+	/* Bit-field values for MCCR4.
+	 */
+#define CONFIG_SYS_PRETOACT	    3	    /* Precharge to activate interval FIXME: was 2	*/
+#define CONFIG_SYS_ACTTOPRE	    5	    /* Activate to Precharge interval FIXME: was 5	*/
+#define CONFIG_SYS_ACTORW	    3		/* FIXME was 2 */
+#define CONFIG_SYS_SDMODE_CAS_LAT  3	    /* SDMODE CAS latancy */
+#define CONFIG_SYS_SDMODE_WRAP	    0	    /* SDMODE wrap type	*/
+#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
+#define CONFIG_SYS_EXTROM	    1
+#define CONFIG_SYS_REGDIMM	    0
+
+#define CONFIG_SYS_PGMAX	    0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/
+
+#define CONFIG_SYS_SDRAM_DSCD	0x20	/* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */
+
+/* Memory bank settings.
+ * Only bits 20-29 are actually used from these vales to set the
+ * start/end addresses. The upper two bits will always be 0, and the lower
+ * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
+ * address. Refer to the MPC8240 book.
+ */
+
+#define CONFIG_SYS_BANK0_START	    0x00000000
+#define CONFIG_SYS_BANK0_END	    (CONFIG_SYS_MAX_RAM_SIZE - 1)
+#define CONFIG_SYS_BANK0_ENABLE    1
+#define CONFIG_SYS_BANK1_START	    0x3ff00000
+#define CONFIG_SYS_BANK1_END	    0x3fffffff
+#define CONFIG_SYS_BANK1_ENABLE    0
+#define CONFIG_SYS_BANK2_START	    0x3ff00000
+#define CONFIG_SYS_BANK2_END	    0x3fffffff
+#define CONFIG_SYS_BANK2_ENABLE    0
+#define CONFIG_SYS_BANK3_START	    0x3ff00000
+#define CONFIG_SYS_BANK3_END	    0x3fffffff
+#define CONFIG_SYS_BANK3_ENABLE    0
+#define CONFIG_SYS_BANK4_START	    0x3ff00000
+#define CONFIG_SYS_BANK4_END	    0x3fffffff
+#define CONFIG_SYS_BANK4_ENABLE    0
+#define CONFIG_SYS_BANK5_START	    0x3ff00000
+#define CONFIG_SYS_BANK5_END	    0x3fffffff
+#define CONFIG_SYS_BANK5_ENABLE    0
+#define CONFIG_SYS_BANK6_START	    0x3ff00000
+#define CONFIG_SYS_BANK6_END	    0x3fffffff
+#define CONFIG_SYS_BANK6_ENABLE    0
+#define CONFIG_SYS_BANK7_START	    0x3ff00000
+#define CONFIG_SYS_BANK7_END	    0x3fffffff
+#define CONFIG_SYS_BANK7_ENABLE    0
+
+#define CONFIG_SYS_ODCR	    0xff
+
+#define CONFIG_SYS_IBAT0L  (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U  (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_DBAT0L  CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U  CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L  CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U  CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L  CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U  CONFIG_SYS_IBAT3U
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* Max number of flash banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* Max number of sectors per flash	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
+
+
+	/* Warining: environment is not EMBEDDED in the U-Boot code.
+	 * It's stored in flash separately.
+	 */
+#define CONFIG_ENV_IS_IN_FLASH	    1
+#define CONFIG_ENV_ADDR		0xFFFE0000
+#define CONFIG_ENV_SIZE		0x00020000 /* Size of the Environment		*/
+#define CONFIG_ENV_SECT_SIZE	0x00020000 /* Size of the Environment Sector	*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	32
+#if defined(CONFIG_CMD_KGDB)
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/APC405.h b/qemu/roms/u-boot/include/configs/APC405.h
new file mode 100644
index 000000000..2678f50bb
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/APC405.h
@@ -0,0 +1,424 @@
+/*
+ * (C) Copyright 2005-2008
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ *
+ * (C) Copyright 2001-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_APCG405		1	/* ...on a APC405 board		*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFF80000
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_BOARD_EARLY_INIT_R 1
+#define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
+
+#define CONFIG_SYS_CLK_FREQ     33333400 /* external frequency to pll   */
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_BOOTDELAY	1	/* autoboot after 3 seconds	*/
+#define CONFIG_BOOTCOUNT_LIMIT	1
+
+#undef	CONFIG_BOOTARGS
+
+#define CONFIG_SYS_USB_LOAD_COMMAND	"fatload usb 0 200000 pImage;"		\
+				"fatload usb 0 300000 pImage.initrd"
+#define CONFIG_SYS_USB_SELF_COMMAND	"usb start;run usb_load;usb stop;"	\
+				"run ramargs addip addcon usbargs;"	\
+				"bootm 200000 300000"
+#define CONFIG_SYS_USB_ARGS		"setenv bootargs $(bootargs) usbboot=1"
+#define CONFIG_SYS_BOOTLIMIT		"3"
+#define CONFIG_SYS_ALT_BOOTCOMMAND	"run usb_self;reset"
+
+#define CONFIG_EXTRA_ENV_SETTINGS                                       \
+	"hostname=abg405\0"                                             \
+	"bd_type=abg405\0"                                              \
+	"serial#=AA0000\0"                                              \
+	"kernel_addr=fe000000\0"                                        \
+	"ramdisk_addr=fe100000\0"                                       \
+	"ramargs=setenv bootargs root=/dev/ram rw\0"                    \
+	"nfsargs=setenv bootargs root=/dev/nfs rw "                     \
+	"nfsroot=$(serverip):$(rootpath)\0"				\
+	"addip=setenv bootargs $(bootargs) "                            \
+		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
+		":$(hostname)::off panic=1\0"				\
+	"addcon=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)"  \
+		" $(optargs)\0"                                         \
+	"flash_self=run ramargs addip addcon;"                          \
+		"bootm $(kernel_addr) $(ramdisk_addr)\0"                \
+	"net_nfs=tftp 200000 $(img);run nfsargs addip addcon;"          \
+		"bootm\0"                                               \
+	"rootpath=/tftpboot/abg405/target_root\0"                       \
+	"img=/tftpboot/abg405/pImage\0"                                 \
+	"load=tftp 100000 /tftpboot/abg405/u-boot.bin\0"		\
+	"update=protect off fff80000 ffffffff;era fff80000 ffffffff;"   \
+		"cp.b 100000 fff80000 80000\0"                          \
+	"ipaddr=10.0.111.111\0"                                         \
+	"netmask=255.255.0.0\0"                                         \
+	"serverip=10.0.0.190\0"						\
+	"splashimage=ffe80000\0"                                        \
+	"usb_load="CONFIG_SYS_USB_LOAD_COMMAND"\0"				\
+	"usb_self="CONFIG_SYS_USB_SELF_COMMAND"\0"				\
+	"usbargs="CONFIG_SYS_USB_ARGS"\0"					\
+	"bootlimit="CONFIG_SYS_BOOTLIMIT"\0"					\
+	"altbootcmd="CONFIG_SYS_ALT_BOOTCOMMAND"\0"				\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self;reset"
+
+#define CONFIG_ETHADDR		00:02:27:8e:00:00
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#undef  CONFIG_HAS_ETH1
+
+#define CONFIG_PPC4xx_EMAC
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP	1
+#define CONFIG_RESET_PHY_R	1	/* use reset_phy() */
+
+#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SOURCE
+#define CONFIG_CMD_USB
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_SUPPORT_VFAT
+
+#define CONFIG_AUTO_UPDATE	1	/* autoupdate via CF or USB */
+
+#undef  CONFIG_WATCHDOG			/* watchdog disabled */
+
+#define CONFIG_RTC_MC146818		/* DS1685 is MC146818 compatible*/
+#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
+
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0 */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device */
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+
+#define CONFIG_SYS_EXT_SERIAL_CLOCK    14745600 /* use external serial clock   */
+
+/* The following table includes the supported baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE      \
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+/* Only interrupt boot if space is pressed */
+/* If a long serial cable is connected but */
+/* other end is dead, garbage will be read */
+#define CONFIG_AUTOBOOT_KEYED	1
+#define CONFIG_AUTOBOOT_PROMPT	\
+	"Press SPACE to abort autoboot in %d seconds\n", bootdelay
+#undef CONFIG_AUTOBOOT_DELAY_STR
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
+#define CONFIG_VERSION_VARIABLE	1	/* include version env variable */
+
+#define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+
+/*
+ * PCI stuff
+ */
+#define PCI_HOST_ADAPTER	0	/* configure as pci adapter     */
+#define PCI_HOST_FORCE		1	/* configure as pci host        */
+#define PCI_HOST_AUTO		2	/* detected via arbiter enable  */
+
+#define CONFIG_PCI			/* include pci support          */
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_HOST PCI_HOST_FORCE	/* select pci host function     */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
+					/* resource configuration       */
+
+#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup  */
+#define CONFIG_PCI_SKIP_HOST_BRIDGE 1
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
+#define CONFIG_SYS_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
+#define CONFIG_SYS_PCI_PTM1LA  0x00000000      /* point to sdram               */
+#define CONFIG_SYS_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CONFIG_SYS_PCI_PTM2LA  0xffc00000      /* point to flash               */
+#define CONFIG_SYS_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
+#define CONFIG_SYS_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+
+/*
+ * IDE/ATA stuff
+ */
+#undef  CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
+#undef  CONFIG_IDE_LED			/* no led for ide supported */
+#define CONFIG_IDE_RESET	1	/* reset for ide supported */
+
+#define CONFIG_SYS_IDE_MAXBUS		1		/* max. 1 IDE busses */
+#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS) /* max. 1 drives per IDE bus */
+
+#define CONFIG_SYS_ATA_BASE_ADDR	0xF0100000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O */
+#define CONFIG_SYS_ATA_REG_OFFSET	0x0000	/* Offset for normal register access */
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers */
+
+/*
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_MONITOR_BASE	0xFFF80000
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN		(2*1024*1024)	/* Reserve 2MB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Init. Memory map for Linux */
+
+/*
+ * FLASH organization
+ */
+#define CONFIG_SYS_FLASH_BASE		0xFE000000
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2
+#define CONFIG_SYS_FLASH_QUIET_TEST	1
+#define CONFIG_SYS_FLASH_INCREMENT	0x01000000
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* use hardware protection */
+#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { \
+				{0xfe000000, 0x500000}, \
+				{0xffe80000, 0x180000} \
+				}
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster) */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ \
+				CONFIG_SYS_FLASH_BASE, \
+				CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_INCREMENT \
+				}
+#define CONFIG_SYS_FLASH_EMPTY_INFO	/* print 'E' for empty sector on flinfo */
+
+/*
+ * Environment Variable setup
+ */
+#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CONFIG_ENV_OFFSET		0x000	/* environment starts at the */
+					/* beginning of the EEPROM */
+#define CONFIG_ENV_SIZE		0x800	/* 2048 bytes may be used for env vars*/
+#define CONFIG_ENV_OVERWRITE	1	/* allow overwriting vendor vars */
+
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xF0000500	/* NVRAM base address */
+#define CONFIG_SYS_NVRAM_SIZE		242		/* NVRAM size */
+
+/*
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		100000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08 */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address */
+/* mask of address bits that overflow into the "EEPROM chip address" */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has */
+					/* 16 byte page write mode using*/
+					/* last	4 bits of the address */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10 /* and takes up to 10 msec */
+
+/*
+ * External Bus Controller (EBC) Setup
+ */
+#define FLASH0_BA       (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_INCREMENT) /* FLASH 0 BA */
+#define FLASH1_BA       CONFIG_SYS_FLASH_BASE      /* FLASH 1 Base Address          */
+#define CAN_BA          0xF0000000          /* CAN Base Address              */
+#define DUART0_BA       0xF0000400          /* DUART Base Address            */
+#define DUART1_BA       0xF0000408          /* DUART Base Address            */
+#define RTC_BA          0xF0000500          /* RTC Base Address              */
+#define PS2_BA          0xF0000600          /* PS/2 Base Address             */
+#define CF_BA           0xF0100000          /* CompactFlash Base Address     */
+#define FPGA_BA         0xF0100100          /* FPGA internal Base Address    */
+#define FUJI_BA         0xF0100200          /* Fuji internal Base Address    */
+#define PCMCIA1_BA      0x20000000          /* PCMCIA Slot 1 Base Address    */
+#define PCMCIA2_BA      0x28000000          /* PCMCIA Slot 2 Base Address    */
+#define VGA_BA          0xF1000000          /* Epson VGA Base Address        */
+
+#define CONFIG_SYS_FPGA_BASE_ADDR      FPGA_BA     /* FPGA internal Base Address    */
+
+/* Memory Bank 0 (Flash Bank 0) initialization                               */
+#define CONFIG_SYS_EBC_PB0AP   0x92015480
+#define CONFIG_SYS_EBC_PB0CR   FLASH0_BA | 0x9A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit*/
+#define CONFIG_SYS_EBC_PB0AP_HWREV8 CONFIG_SYS_EBC_PB0AP
+#define CONFIG_SYS_EBC_PB0CR_HWREV8 FLASH1_BA | 0xBA000 /* BS=32MB */
+
+/* Memory Bank 1 (Flash Bank 1) initialization                               */
+#define CONFIG_SYS_EBC_PB1AP   0x92015480
+#define CONFIG_SYS_EBC_PB1CR   FLASH1_BA | 0x9A000 /* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/
+
+/* Memory Bank 2 (CAN0, 1, RTC, Duart) initialization                           */
+#define CONFIG_SYS_EBC_PB2AP   0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB2CR   CAN_BA | 0x18000    /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
+
+/* Memory Bank 3 (CompactFlash IDE, FPGA internal) initialization               */
+#define CONFIG_SYS_EBC_PB3AP   0x010059C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB3CR   CF_BA | 0x1A000     /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 4 (PCMCIA Slot 1) initialization                                 */
+#define CONFIG_SYS_EBC_PB4AP   0x050007C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB4CR   PCMCIA1_BA | 0xFA000 /*BAS=0x200,BS=128MB,BU=R/W,BW=16bit*/
+
+/* Memory Bank 5 (Epson VGA) initialization                                     */
+#define CONFIG_SYS_EBC_PB5AP   0x03805380   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */
+#define CONFIG_SYS_EBC_PB5CR   VGA_BA | 0x5A000    /* BAS=0xF10,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 6 (PCMCIA Slot 2) initialization                                 */
+#define CONFIG_SYS_EBC_PB6AP   0x050007C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB6CR   PCMCIA2_BA | 0xFA000 /*BAS=0x280,BS=128MB,BU=R/W,BW=16bit*/
+
+/*
+ * FPGA stuff
+ */
+
+/* FPGA internal regs */
+#define CONFIG_SYS_FPGA_CTRL           0x008
+#define CONFIG_SYS_FPGA_CTRL2          0x00a
+
+/* FPGA Control Reg */
+#define CONFIG_SYS_FPGA_CTRL_CF_RESET  0x0001
+#define CONFIG_SYS_FPGA_CTRL_WDI       0x0002
+#define CONFIG_SYS_FPGA_CTRL_PS2_RESET 0x0020
+
+#define CONFIG_SYS_FPGA_SPARTAN2       1           /* using Xilinx Spartan 2 now    */
+#define CONFIG_SYS_FPGA_MAX_SIZE       80*1024     /* 80kByte is enough for XC2S50  */
+
+/* FPGA program pin configuration */
+#define CONFIG_SYS_FPGA_PRG            0x04000000  /* FPGA program pin (ppc output) */
+#define CONFIG_SYS_FPGA_CLK            0x02000000  /* FPGA clk pin (ppc output)     */
+#define CONFIG_SYS_FPGA_DATA           0x01000000  /* FPGA data pin (ppc output)    */
+#define CONFIG_SYS_FPGA_INIT           0x00010000  /* FPGA init pin (ppc input)     */
+#define CONFIG_SYS_FPGA_DONE           0x00008000  /* FPGA done pin (ppc input)     */
+
+/*
+ * LCD Setup
+ */
+#define CONFIG_SYS_LCD_BIG_MEM		(VGA_BA + 0x200000) /* S1D13806 Mem Base */
+#define CONFIG_SYS_LCD_BIG_REG		VGA_BA /* S1D13806 Reg Base */
+
+#define CONFIG_LCD_BIG		2 /* Epson S1D13806 used */
+
+/* Image information... */
+#define CONFIG_LCD_USED		CONFIG_LCD_BIG
+
+#define CONFIG_SYS_LCD_MEM		CONFIG_SYS_LCD_BIG_MEM
+#define CONFIG_SYS_LCD_REG		CONFIG_SYS_LCD_BIG_REG
+
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (1 << 20)
+
+/*
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CONFIG_SYS_TEMP_STACK_OCM	1
+
+/* On Chip Memory location */
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+/* reserve some memory for BOOT limit info */
+#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 16)
+
+#ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */
+#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 8)
+#endif
+
+/*
+ * PCI OHCI controller
+ */
+#define CONFIG_USB_OHCI_NEW	1
+#define CONFIG_PCI_OHCI		1
+#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"ohci_pci"
+#define CONFIG_USB_STORAGE	1
+#define CONFIG_SYS_USB_OHCI_BOARD_INIT 1
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/AR405.h b/qemu/roms/u-boot/include/configs/AR405.h
new file mode 100644
index 000000000..45dd46a41
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/AR405.h
@@ -0,0 +1,253 @@
+/*
+ * (C) Copyright 2001-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405GP		1	/* This is a PPC405GP CPU	*/
+#define CONFIG_AR405		1	/* ...on a AR405 board		*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFA0000
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+
+#define CONFIG_SYS_CLK_FREQ	33000000 /* external frequency to pll	*/
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+#if 1
+#define CONFIG_BOOTCOMMAND	"bootm fff00000" /* autoboot command	*/
+#else
+#define CONFIG_BOOTCOMMAND	"bootp" /* autoboot command		*/
+#endif
+
+#if 0
+#define CONFIG_BOOTARGS		"root=/dev/nfs "			\
+    "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0 "	\
+    "nfsroot=192.168.2.190:/home/stefan/cpci405/target_ftest4"
+#else
+#define CONFIG_BOOTARGS		"root=/dev/hda1 "			\
+    "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0"
+
+#endif
+
+#define CONFIG_PREBOOT                  /* enable preboot variable      */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_PPC4xx_EMAC
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_MII
+#undef CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_BSP
+
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
+#define CONFIG_LOOPW            1       /* enable loopw command         */
+#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+
+#define CONFIG_SYS_EXT_SERIAL_CLOCK	14745600 /* use external serial clock	*/
+
+/* The following table includes the supported baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0		/* configure ar pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_HOST PCI_HOST_FORCE	/* select pci host function	*/
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+					/* resource configuration	*/
+
+#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
+
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
+
+#define CONFIG_PCI_BOOTDELAY	0	/* enable pci bootdelay variable*/
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0403	/* PCI Device ID: ARISTO405	*/
+#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CONFIG_SYS_PCI_PTM1MS	0x80000001	/* 2GB, enable hard-wired to 1	*/
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CONFIG_SYS_PCI_PTM2LA	0xfff00000	/* point to flash		*/
+#define CONFIG_SYS_PCI_PTM2MS	0xfff00001	/* 1MB, enable			*/
+#define CONFIG_SYS_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(~(CONFIG_SYS_TEXT_BASE) + 1)
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SECT_SIZE	0x10000 /* see README - env sector total size	*/
+#define CONFIG_ENV_SIZE		0x04000	        /* Size of Environment	        */
+
+#define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash Bank 0) initialization					*/
+#define CONFIG_SYS_EBC_PB0AP		0x92015480
+#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (CAN0, 1, 2, 3) initialization					*/
+#define CONFIG_SYS_EBC_PB1AP		0x01000380  /* enable Ready, BEM=0		*/
+#define CONFIG_SYS_EBC_PB1CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 2 (Expension Bus) initialization					*/
+#define CONFIG_SYS_EBC_PB2AP		0x01000280  /* disable Ready, BEM=0		*/
+#define CONFIG_SYS_EBC_PB2CR		0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 3 (16552) initialization						*/
+#define CONFIG_SYS_EBC_PB3AP		0x01000380  /* enable Ready, BEM=0		*/
+#define CONFIG_SYS_EBC_PB3CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 4 (FPGA regs) initialization					*/
+#define CONFIG_SYS_EBC_PB4AP		0x01005380  /* enable Ready, BEM=0		*/
+#define CONFIG_SYS_EBC_PB4CR		0xF031C000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=32bit */
+
+/* Memory Bank 5 (Flash Bank 1/DUMMY) initialization				*/
+#define CONFIG_SYS_EBC_PB5AP		0x92015480
+#define CONFIG_SYS_EBC_PB5CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+#define CONFIG_SYS_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
+
+#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000	/* Size of used area in RAM	       */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/ASH405.h b/qemu/roms/u-boot/include/configs/ASH405.h
new file mode 100644
index 000000000..2ff9b598c
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/ASH405.h
@@ -0,0 +1,351 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_ASH405		1	/* ...on a ASH405 board		*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
+
+#define CONFIG_SYS_CLK_FREQ	33333300 /* external frequency to pll	*/
+
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+#undef	CONFIG_BOOTARGS
+#undef  CONFIG_BOOTCOMMAND
+
+#define CONFIG_PREBOOT                  /* enable preboot variable      */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#undef  CONFIG_HAS_ETH1
+
+#define CONFIG_PPC4xx_EMAC
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
+
+#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_EEPROM
+
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_RTC_MC146818		/* DS1685 is MC146818 compatible*/
+#define CONFIG_SYS_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address		*/
+
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+
+#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CONFIG_SYS_BASE_BAUD	    691200
+
+/* The following table includes the supported baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+#define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+
+/*-----------------------------------------------------------------------
+ * NAND-FLASH stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1         /* Max number of NAND devices */
+#define NAND_BIG_DELAY_US	25
+
+#define CONFIG_SYS_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
+#define CONFIG_SYS_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
+#define CONFIG_SYS_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
+#define CONFIG_SYS_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
+
+#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I	1	/* ".i" read skips bad blocks   */
+#define CONFIG_SYS_NAND_QUIET		1
+#define CONFIG_SYS_NAND_MAX_OOBFREE	2
+#define CONFIG_SYS_NAND_MAX_ECCPOS	56
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_HOST PCI_HOST_HOST	/* select pci host function	*/
+#undef	CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+					/* resource configuration	*/
+
+#undef	CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
+#define CONFIG_SYS_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
+#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CONFIG_SYS_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CONFIG_SYS_PCI_PTM2LA	0xffc00000	/* point to flash		*/
+#define CONFIG_SYS_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
+#define CONFIG_SYS_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFFC0000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
+
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#if 0 /* test-only */
+#define CONFIG_SYS_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
+#define CONFIG_SYS_JFFS2_NUM_BANKS	1	    /* ! second bank contains U-Boot */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Environment Variable setup
+ */
+#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CONFIG_ENV_OFFSET		0x100	/* environment starts at the beginning of the EEPROM */
+#define CONFIG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
+				   /* total size of a CAT24WC16 is 2048 bytes */
+
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
+#define CONFIG_SYS_NVRAM_SIZE		242			/* NVRAM size		*/
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last 4 bits of the address	*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
+#define CONFIG_SYS_EBC_PB0AP		0x92015480
+/*#define CONFIG_SYS_EBC_PB0AP		  0x08055880  /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
+#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization			*/
+#define CONFIG_SYS_EBC_PB1AP		0x92015480
+#define CONFIG_SYS_EBC_PB1CR		0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization		*/
+#define CONFIG_SYS_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization	*/
+#define CONFIG_SYS_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+
+#define CAN_BA		0xF0000000	    /* CAN Base Address			*/
+#define DUART0_BA	0xF0000400	    /* DUART Base Address		*/
+#define DUART1_BA	0xF0000408	    /* DUART Base Address		*/
+#define DUART2_BA	0xF0000410	    /* DUART Base Address		*/
+#define DUART3_BA	0xF0000418	    /* DUART Base Address		*/
+#define RTC_BA		0xF0000500	    /* RTC Base Address			*/
+#define CONFIG_SYS_NAND_BASE	0xF4000000
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ */
+#define CONFIG_SYS_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
+#define CONFIG_SYS_FPGA_MAX_SIZE	128*1024    /* 128kByte is enough for XC2S50E*/
+
+/* FPGA program pin configuration */
+#define CONFIG_SYS_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
+#define CONFIG_SYS_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
+#define CONFIG_SYS_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
+#define CONFIG_SYS_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
+#define CONFIG_SYS_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CONFIG_SYS_TEMP_STACK_OCM	  1
+
+/* On Chip Memory location */
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
+
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO setup (PPC405EP specific)
+ *
+ * GPIO0[0]	- External Bus Controller BLAST output
+ * GPIO0[1-9]	- Instruction trace outputs -> GPIO
+ * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
+ * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
+ * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
+ * GPIO0[24-27] - UART0 control signal inputs/outputs
+ * GPIO0[28-29] - UART1 data signal input/output
+ * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
+ */
+#define CONFIG_SYS_GPIO0_OSRL		0x40000550
+#define CONFIG_SYS_GPIO0_OSRH		0x00000110
+#define CONFIG_SYS_GPIO0_ISR1L		0x00000000
+#define CONFIG_SYS_GPIO0_ISR1H		0x15555445
+#define CONFIG_SYS_GPIO0_TSRL		0x00000000
+#define CONFIG_SYS_GPIO0_TSRH		0x00000000
+#define CONFIG_SYS_GPIO0_TCR		0xF7FE0014
+
+#define CONFIG_SYS_DUART_RST		(0x80000000 >> 14)
+
+/*
+ * Default speed selection (cpu_plb_opb_ebc) in mhz.
+ * This value will be set if iic boot eprom is disabled.
+ */
+#if 0
+#define PLLMR0_DEFAULT	 PLLMR0_266_133_66_33
+#define PLLMR1_DEFAULT	 PLLMR1_266_133_66_33
+#endif
+#if 1
+#define PLLMR0_DEFAULT	 PLLMR0_200_100_50_33
+#define PLLMR1_DEFAULT	 PLLMR1_200_100_50_33
+#endif
+#if 0
+#define PLLMR0_DEFAULT	 PLLMR0_133_66_66_33
+#define PLLMR1_DEFAULT	 PLLMR1_133_66_66_33
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/Adder.h b/qemu/roms/u-boot/include/configs/Adder.h
new file mode 100644
index 000000000..140f4439c
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/Adder.h
@@ -0,0 +1,193 @@
+/*
+ * Copyright (C) 2004-2005 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * Support for Analogue&Micro Adder boards family.
+ * Tested on AdderII and Adder87x.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#if !defined(CONFIG_MPC875) && !defined(CONFIG_MPC852T)
+#define CONFIG_MPC875
+#endif
+
+#define CONFIG_ADDER				/* Analogue&Micro Adder board	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xFE000000
+
+#define	CONFIG_8xx_CONS_SMC1	1		/* Console is on SMC1		*/
+#define CONFIG_BAUDRATE		38400
+
+#define CONFIG_ETHER_ON_FEC1
+#define CONFIG_ETHER_ON_FEC2
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+
+#if defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2)
+#define CONFIG_SYS_DISCOVER_PHY
+#define CONFIG_MII_INIT		1
+#define FEC_ENET
+#endif /* CONFIG_ETHER_ON_FEC || CONFIG_ETHER_ON_FEC2 */
+
+#define CONFIG_8xx_OSCLK		10000000 /* 10 MHz oscillator on EXTCLK */
+#define CONFIG_8xx_CPUCLK_DEFAULT	50000000
+#define CONFIG_SYS_8xx_CPUCLK_MIN		40000000
+#ifdef CONFIG_MPC852T
+#define CONFIG_SYS_8xx_CPUCLK_MAX		50000000
+#else
+#define CONFIG_SYS_8xx_CPUCLK_MAX		133000000
+#endif /* CONFIG_MPC852T */
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+
+
+#define CONFIG_BOOTDELAY	5		/* Autoboot after 5 seconds	*/
+#define CONFIG_BOOTCOMMAND	"bootm fe040000"	/* Autoboot command	*/
+#define CONFIG_BOOTARGS		"root=/dev/mtdblock1 rw mtdparts=1M(ROM)ro,-(root)"
+
+#define CONFIG_BZIP2		/* Include support for bzip2 compressed images  */
+#undef	CONFIG_WATCHDOG		/* Disable platform specific watchdog		*/
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_LONGHELP				/* #undef to save memory	*/
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)  /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* Max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x400000	/* Default load address		*/
+
+/*-----------------------------------------------------------------------
+ * RAM configuration (note that CONFIG_SYS_SDRAM_BASE must be zero)
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_MAX_SIZE	0x01000000	/* Up to 16 Mbyte		*/
+
+#define CONFIG_SYS_MAMR		0x00002114
+
+/*
+ * 4096	Up to 4096 SDRAM rows
+ * 1000	factor s -> ms
+ * 32	PTP (pre-divider from MPTPR)
+ * 4	Number of refresh cycles per period
+ * 64	Refresh cycle in ms per number of rows
+ */
+#define CONFIG_SYS_PTA_PER_CLK		((4096 * 32 * 1000) / (4 * 64))
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END		0x00500000	/* 1 ... 5 MB in SDRAM		*/
+
+#define CONFIG_SYS_RESET_ADDRESS	0x09900000
+
+/*-----------------------------------------------------------------------
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 KB for Monitor   */
+#ifdef CONFIG_BZIP2
+#define CONFIG_SYS_MALLOC_LEN		(2500 << 10)	/* Reserve ~2.5 MB for malloc() */
+#else
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 KB for malloc()  */
+#endif /* CONFIG_BZIP2 */
+
+/*-----------------------------------------------------------------------
+ * Flash organisation
+ */
+#define CONFIG_SYS_FLASH_BASE		0xFE000000
+#define CONFIG_SYS_FLASH_CFI				/* The flash is CFI compatible  */
+#define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver        */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* Max number of flash banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	128		/* Max num of sects on one chip */
+
+/* Environment is in flash */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	0x10000		/* We use one complete sector	*/
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_SYS_OR0_PRELIM		0xFF000774
+#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_MS_GPCM | BR_V)
+
+#define	CONFIG_SYS_DIRECT_FLASH_TFTP
+
+/*-----------------------------------------------------------------------
+ * Internal Memory Map Register
+ */
+#define CONFIG_SYS_IMMR		0xFF000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2F00		/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Configuration registers
+ */
+#ifdef CONFIG_WATCHDOG
+#define CONFIG_SYS_SYPCR		(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME  | \
+				 SYPCR_SWF  | SYPCR_SWE | SYPCR_SWRI | \
+				 SYPCR_SWP)
+#else
+#define CONFIG_SYS_SYPCR		(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME  | \
+				 SYPCR_SWF  | SYPCR_SWP)
+#endif /* CONFIG_WATCHDOG */
+
+#define CONFIG_SYS_SIUMCR		(SIUMCR_MLRC01 | SIUMCR_DBGC11)
+
+/* TBSCR - Time Base Status and Control Register */
+#define CONFIG_SYS_TBSCR		(TBSCR_TBF | TBSCR_TBE)
+
+/* PISCR - Periodic Interrupt Status and Control */
+#define CONFIG_SYS_PISCR		(PISCR_PS | PISCR_PITF)
+
+/* PLPRCR - PLL, Low-Power, and Reset Control Register */
+/* #define CONFIG_SYS_PLPRCR		PLPRCR_TEXPS */
+
+/* SCCR - System Clock and reset Control Register */
+#define SCCR_MASK		SCCR_EBDF11
+#define CONFIG_SYS_SCCR		SCCR_RTSEL
+
+#define CONFIG_SYS_DER			0
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx chips			*/
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/B4860QDS.h b/qemu/roms/u-boot/include/configs/B4860QDS.h
new file mode 100644
index 000000000..47aca9c00
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/B4860QDS.h
@@ -0,0 +1,910 @@
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
+/*
+ * B4860 QDS board configuration file
+ */
+#define CONFIG_B4860QDS
+#define CONFIG_PHYS_64BIT
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_SYS_FSL_PBL_PBI	$(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW	$(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
+#ifndef CONFIG_NAND
+#define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
+#else
+#define CONFIG_SPL
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_FSL_LAW                 /* Use common FSL init code */
+#define CONFIG_SYS_TEXT_BASE		0x00201000
+#define CONFIG_SPL_TEXT_BASE		0xFFFD8000
+#define CONFIG_SPL_PAD_TO		0x40000
+#define CONFIG_SPL_MAX_SIZE		0x28000
+#define RESET_VECTOR_OFFSET		0x27FFC
+#define BOOT_PAGE_OFFSET		0x27000
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(256 << 10)
+#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#define CONFIG_SPL_NAND_BOOT
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_SKIP_RELOCATE
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#define CONFIG_SYS_NO_FLASH
+#endif
+#endif
+#endif
+
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+/* Set 1M boot space */
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
+		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CONFIG_SYS_NO_FLASH
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE
+#define CONFIG_E500			/* BOOKE e500 family */
+#define CONFIG_E500MC			/* BOOKE e500mc family */
+#define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
+#define CONFIG_MP			/* support multiple processors */
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xeff40000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+#define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC		CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_FSL_IFC			/* Enable IFC Support */
+#define CONFIG_PCI			/* Enable PCI/PCIE */
+#define CONFIG_PCIE1			/* PCIE controler 1 */
+#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
+
+#ifndef CONFIG_PPC_B4420
+#define CONFIG_SYS_SRIO
+#define CONFIG_SRIO1			/* SRIO port 1 */
+#define CONFIG_SRIO2			/* SRIO port 2 */
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
+#endif
+
+#define CONFIG_FSL_LAW			/* Use common FSL init code */
+
+/* I2C bus multiplexer */
+#define I2C_MUX_PCA_ADDR                0x77
+
+/* VSC Crossbar switches */
+#define CONFIG_VSC_CROSSBAR
+#define I2C_CH_DEFAULT                  0x8
+#define I2C_CH_VSC3316                  0xc
+#define I2C_CH_VSC3308                  0xd
+
+#define VSC3316_TX_ADDRESS              0x70
+#define VSC3316_RX_ADDRESS              0x71
+#define VSC3308_TX_ADDRESS              0x02
+#define VSC3308_RX_ADDRESS              0x03
+
+/* IDT clock synthesizers */
+#define CONFIG_IDT8T49N222A
+#define I2C_CH_IDT                     0x9
+
+#define IDT_SERDES1_ADDRESS            0x6E
+#define IDT_SERDES2_ADDRESS            0x6C
+
+/* Voltage monitor on channel 2*/
+#define I2C_MUX_CH_VOL_MONITOR		0xa
+#define I2C_VOL_MONITOR_ADDR		0x40
+#define I2C_VOL_MONITOR_BUS_V_OFFSET	0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF	0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT	3
+
+#define CONFIG_ZM7300
+#define I2C_MUX_CH_DPM			0xa
+#define I2C_DPM_ADDR			0x28
+
+#define CONFIG_ENV_OVERWRITE
+
+#ifdef CONFIG_SYS_NO_FLASH
+#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+#else
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#endif
+
+#if defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS              0
+#define CONFIG_ENV_SPI_CS               0
+#define CONFIG_ENV_SPI_MAX_HZ           10000000
+#define CONFIG_ENV_SPI_MODE             0
+#define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
+#define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
+#define CONFIG_ENV_SECT_SIZE            0x10000
+#elif defined(CONFIG_SDCARD)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV          0
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_OFFSET		(512 * 1097)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_OFFSET		(10 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+#define CONFIG_ENV_IS_IN_REMOTE
+#define CONFIG_ENV_ADDR		0xffe20000
+#define CONFIG_ENV_SIZE		0x2000
+#elif defined(CONFIG_ENV_IS_NOWHERE)
+#define CONFIG_ENV_SIZE		0x2000
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+#endif
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk() /* sysclk for MPC85xx */
+#define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk()
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BTB			/* toggle branch predition */
+#define CONFIG_DDR_ECC
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#endif
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP		64	/* number of TLB1 entries */
+#endif
+
+#if 0
+#define CONFIG_POST CONFIG_SYS_POST_MEMORY	/* test POST memory test */
+#endif
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_PANIC_HANG	/* do not reset board on panic */
+
+/*
+ *  Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
+#define CONFIG_SYS_L3_SIZE		256 << 10
+#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
+#ifdef CONFIG_NAND
+#define CONFIG_ENV_ADDR			(CONFIG_SPL_GD_ADDR + 4 * 1024)
+#endif
+#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SPL_GD_ADDR + 12 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(30 << 10)
+#define CONFIG_SPL_RELOC_STACK		(CONFIG_SPL_GD_ADDR + 64 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE	(22 << 10)
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_DCSRBAR		0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
+#endif
+
+/* EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM	0
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(4 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_DDR_RAW_TIMING
+#define CONFIG_SYS_FSL_DDR3
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_FSL_DDR_INTERACTIVE
+#endif
+
+#define CONFIG_SYS_SPD_BUS_NUM	0
+#define SPD_EEPROM_ADDRESS1	0x51
+#define SPD_EEPROM_ADDRESS2	0x53
+
+#define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
+#define CONFIG_SYS_SDRAM_SIZE	2048	/* for fixed parameter use */
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE	0xe0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+#else
+#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+#endif
+
+#define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+				+ 0x8000000) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR1_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128 * 1024 * 1024)
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(4)
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x01) | \
+				FTIM0_NOR_TEADC(0x04) | \
+				FTIM0_NOR_TEAHC(0x20))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
+				FTIM1_NOR_TRAD_NOR(0x1A) |\
+				FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x01) | \
+				FTIM2_NOR_TCH(0x0E) | \
+				FTIM2_NOR_TWPH(0x0E) | \
+				FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3	0x0
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS \
+					+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
+
+#define CONFIG_FSL_QIXIS	/* use common QIXIS code */
+#define CONFIG_FSL_QIXIS_V2
+#define QIXIS_BASE		0xffdf0000
+#ifdef CONFIG_PHYS_64BIT
+#define QIXIS_BASE_PHYS		(0xf00000000ull | QIXIS_BASE)
+#else
+#define QIXIS_BASE_PHYS		QIXIS_BASE
+#endif
+#define QIXIS_LBMAP_SWITCH		0x01
+#define QIXIS_LBMAP_MASK		0x0f
+#define QIXIS_LBMAP_SHIFT		0
+#define QIXIS_LBMAP_DFLTBANK		0x00
+#define QIXIS_LBMAP_ALTBANK		0x02
+#define QIXIS_RST_CTL_RESET		0x31
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+
+#define CONFIG_SYS_CSPR3_EXT	(0xf)
+#define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 \
+				| CSPR_MSEL_GPCM \
+				| CSPR_V)
+#define CONFIG_SYS_AMASK3	IFC_AMASK(4 * 1024)
+#define CONFIG_SYS_CSOR3	0x0
+/* QIXIS Timing parameters for IFC CS3 */
+#define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
+					FTIM0_GPCM_TEADC(0x0e) | \
+					FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \
+					FTIM1_GPCM_TRAD(0x1f))
+#define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
+					FTIM2_GPCM_TCH(0x0) | \
+					FTIM2_GPCM_TWP(0x1f))
+#define CONFIG_SYS_CS3_FTIM3		0x0
+
+/* NAND Flash on IFC */
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_MAX_ECCPOS	256
+#define CONFIG_SYS_NAND_MAX_OOBFREE	2
+#define CONFIG_SYS_NAND_BASE		0xff800000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
+#else
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#endif
+
+#define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
+
+#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
+				| CSOR_NAND_RAL_3	/* RAL = 2Byes */ \
+				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
+				| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
+				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+					FTIM0_NAND_TWP(0x18)   | \
+					FTIM0_NAND_TWCHT(0x07) | \
+					FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+					FTIM1_NAND_TWBE(0x39)  | \
+					FTIM1_NAND_TRR(0x0e)   | \
+					FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
+					FTIM2_NAND_TREH(0x0a) | \
+					FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3		0x0
+
+#define CONFIG_SYS_NAND_DDR_LAW		11
+
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
+#endif
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe0ec000
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#else
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS	0xfe0ec000 /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
+#endif
+#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
+#define CONFIG_SERIAL_MULTI		/* Enable both serial ports */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	/* determine from environment */
+#endif
+
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL		/* Use FSL common I2C driver */
+#define CONFIG_SYS_FSL_I2C_SPEED	400000	/* I2C speed in Hz */
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000	/* I2C speed in Hz */
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x119000
+
+/*
+ * RTC configuration
+ */
+#define RTC
+#define CONFIG_RTC_DS3231               1
+#define CONFIG_SYS_I2C_RTC_ADDR         0x68
+
+/*
+ * RapidIO
+ */
+#ifdef CONFIG_SYS_SRIO
+#ifdef CONFIG_SRIO1
+#define CONFIG_SYS_SRIO1_MEM_VIRT	0xa0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
+#else
+#define CONFIG_SYS_SRIO1_MEM_PHYS	0xa0000000
+#endif
+#define CONFIG_SYS_SRIO1_MEM_SIZE	0x10000000	/* 256M */
+#endif
+
+#ifdef CONFIG_SRIO2
+#define CONFIG_SYS_SRIO2_MEM_VIRT	0xb0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
+#else
+#define CONFIG_SYS_SRIO2_MEM_PHYS	0xb0000000
+#endif
+#define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000	/* 256M */
+#endif
+#endif
+
+/*
+ * for slave u-boot IMAGE instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000	/* 512K */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
+/*
+ * for slave UCODE and ENV instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000	/* 256K */
+
+/* slave core release by master*/
+#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
+#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
+
+/*
+ * SRIO_PCIE_BOOT - SLAVE
+ */
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
+		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
+#endif
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#define CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED         10000000
+#define CONFIG_SF_DEFAULT_MODE          0
+
+/*
+ * MAPLE
+ */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_MAPLE_MEM_PHYS      0xFA0000000ull
+#else
+#define CONFIG_SYS_MAPLE_MEM_PHYS      0xA0000000
+#endif
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#else
+#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0x80000000
+#endif
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
+#else
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xf8000000
+#endif
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+
+/* Qman/Bman */
+#ifndef CONFIG_NOBQFMAN
+#define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS	25
+#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
+#else
+#define CONFIG_SYS_BMAN_MEM_PHYS	CONFIG_SYS_BMAN_MEM_BASE
+#endif
+#define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
+#define CONFIG_SYS_QMAN_NUM_PORTALS	25
+#define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
+#else
+#define CONFIG_SYS_QMAN_MEM_PHYS	CONFIG_SYS_QMAN_MEM_BASE
+#endif
+#define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
+
+#define CONFIG_SYS_DPAA_FMAN
+
+#define CONFIG_SYS_DPAA_RMAN
+
+/* Default address of microcode for the Linux Fman driver */
+#if defined(CONFIG_SPIFLASH)
+/*
+ * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
+ * env, so we got 0x110000.
+ */
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_FMAN_FW_ADDR	0x110000
+#elif defined(CONFIG_SDCARD)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 545KB (1089 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+#define CONFIG_SYS_FMAN_FW_ADDR	(512 * 1130)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_FMAN_FW_ADDR	(13 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+/*
+ * Slave has no ucode locally, it can fetch this from remote. When implementing
+ * in two corenet boards, slave's ucode could be stored in master's memory
+ * space, the address can be mapped from slave TLB->slave LAW->
+ * slave SRIO or PCIE outbound window->master inbound window->
+ * master LAW->the ucode address in master's memory space.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
+#define CONFIG_SYS_FMAN_FW_ADDR	0xFFE00000
+#else
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_FMAN_FW_ADDR		0xEFF00000
+#endif
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+#endif /* CONFIG_NOBQFMAN */
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_TERANETICS
+#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
+#define SGMII_CARD_PORT2_PHY_ADDR 0x10
+#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
+#define SGMII_CARD_PORT4_PHY_ADDR 0x11
+#endif
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+#define CONFIG_E1000
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif	/* CONFIG_PCI */
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR	0x10
+#define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR	0x11
+
+/*B4860 QDS AMC2PEX-2S default PHY_ADDR */
+#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7	 /*SLOT 1*/
+#define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6	 /*SLOT 2*/
+
+
+#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
+#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
+#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
+#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
+
+#define CONFIG_MII		/* MII PHY management */
+#define CONFIG_ETHPRIME		"FM1@DTSEC1"
+#define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ERRATA
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SETEXPR
+
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
+/*
+* USB
+*/
+#define CONFIG_HAS_FSL_DR_USB
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+#define CONFIG_USB_EHCI
+
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_CMD_EXT2
+#endif
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	"u-boot.bin"	/* U-Boot image on TFTP server*/
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+#define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
+
+#define CONFIG_BAUDRATE	115200
+
+#define __USB_PHY_TYPE	ulpi
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hwconfig=fsl_ddr:ctlr_intlv=null,"		\
+	"bank_intlv=cs0_cs1;"					\
+	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
+	"netdev=eth0\0"						\
+	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
+	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"			\
+	"tftpflash=tftpboot $loadaddr $uboot && "		\
+	"protect off $ubootaddr +$filesize && "			\
+	"erase $ubootaddr +$filesize && "			\
+	"cp.b $loadaddr $ubootaddr $filesize && "		\
+	"protect on $ubootaddr +$filesize && "			\
+	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
+	"consoledev=ttyS0\0"					\
+	"ramdiskaddr=2000000\0"					\
+	"ramdiskfile=b4860qds/ramdisk.uboot\0"			\
+	"fdtaddr=c00000\0"					\
+	"fdtfile=b4860qds/b4860qds.dtb\0"				\
+	"bdev=sda3\0"						\
+	"c=ffe\0"
+
+/* For emulation this causes u-boot to jump to the start of the proof point
+   app code automatically */
+#define CONFIG_PROOF_POINTS			\
+ "setenv bootargs root=/dev/$bdev rw "		\
+ "console=$consoledev,$baudrate $othbootargs;"	\
+ "cpu 1 release 0x29000000 - - -;"		\
+ "cpu 2 release 0x29000000 - - -;"		\
+ "cpu 3 release 0x29000000 - - -;"		\
+ "cpu 4 release 0x29000000 - - -;"		\
+ "cpu 5 release 0x29000000 - - -;"		\
+ "cpu 6 release 0x29000000 - - -;"		\
+ "cpu 7 release 0x29000000 - - -;"		\
+ "go 0x29000000"
+
+#define CONFIG_HVBOOT	\
+ "setenv bootargs config-addr=0x60000000; "	\
+ "bootm 0x01000000 - 0x00f00000"
+
+#define CONFIG_ALU				\
+ "setenv bootargs root=/dev/$bdev rw "		\
+ "console=$consoledev,$baudrate $othbootargs;"	\
+ "cpu 1 release 0x01000000 - - -;"		\
+ "cpu 2 release 0x01000000 - - -;"		\
+ "cpu 3 release 0x01000000 - - -;"		\
+ "cpu 4 release 0x01000000 - - -;"		\
+ "cpu 5 release 0x01000000 - - -;"		\
+ "cpu 6 release 0x01000000 - - -;"		\
+ "cpu 7 release 0x01000000 - - -;"		\
+ "go 0x01000000"
+
+#define CONFIG_LINUX				\
+ "setenv bootargs root=/dev/ram rw "		\
+ "console=$consoledev,$baudrate $othbootargs;"	\
+ "setenv ramdiskaddr 0x02000000;"		\
+ "setenv fdtaddr 0x00c00000;"			\
+ "setenv loadaddr 0x1000000;"			\
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_HDBOOT					\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND			\
+	"setenv bootargs root=/dev/nfs rw "	\
+	"nfsroot=$serverip:$rootpath "		\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"		\
+	"tftp $fdtaddr $fdtfile;"		\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND				\
+	"setenv bootargs root=/dev/ram rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $ramdiskaddr $ramdiskfile;"		\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_LINUX
+
+#include <asm/fsl_secure_boot.h>
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/BC3450.h b/qemu/roms/u-boot/include/configs/BC3450.h
new file mode 100644
index 000000000..802e9cce1
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/BC3450.h
@@ -0,0 +1,541 @@
+/*
+ * -- Version 1.1 --
+ *
+ * (C) Copyright 2003-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004-2005
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * (C) Copyright 2005
+ * Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de.
+ *
+ * History:
+ *	1.1 - add define CONFIG_ZERO_BOOTDELAY_CHECK
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_MPC5200		1	/* This is a MPC5200 CPU	    */
+#define CONFIG_TQM5200		1	/* ... on a TQM5200 module	    */
+
+#define CONFIG_BC3450		1	/* ... on a BC3450 mainboard	    */
+#define CONFIG_BC3450_PS2	1	/*  + a PS/2 converter onboard	    */
+#define CONFIG_BC3450_IDE	1	/*  + IDE drives (Compact Flash)    */
+#define CONFIG_BC3450_USB	1	/*  + USB support		    */
+# define CONFIG_FAT		1	/*    + FAT support		    */
+# define CONFIG_EXT2		1	/*    + EXT2 support		    */
+#undef CONFIG_BC3450_BUZZER		/*  + Buzzer onboard		    */
+#undef CONFIG_BC3450_CAN		/*  + CAN transceiver		    */
+#undef CONFIG_BC3450_DS1340		/*  + a RTC DS1340 onboard	    */
+#undef CONFIG_BC3450_DS3231		/*  + a RTC DS3231 onboard	tbd */
+#undef CONFIG_BC3450_AC97		/*  + AC97 on PSC2,		tbd */
+#define CONFIG_BC3450_FP	1	/*  + enable FP O/P		    */
+#undef CONFIG_BC3450_CRT		/*  + enable CRT O/P (Debug only!)  */
+
+/*
+ * Valid values for CONFIG_SYS_TEXT_BASE are:
+ * 0xFC000000	boot low (standard configuration with room for
+ *		max 64 MByte Flash ROM)
+ * 0x00100000	boot from RAM (for testing only)
+ */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xFC000000
+#endif
+
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz	    */
+
+#define CONFIG_HIGH_BATS	1	/* High BATs supported		    */
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1		*/
+#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps		*/
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*
+ * AT-PS/2 Multiplexer
+ */
+#ifdef CONFIG_BC3450_PS2
+# define CONFIG_PS2KBD			/* AT-PS/2 Keyboard		*/
+# define CONFIG_PS2MULT			/* .. on PS/2 Multiplexer	*/
+# define CONFIG_PS2SERIAL	6		/* .. on PSC6		*/
+# define CONFIG_PS2MULT_DELAY	(CONFIG_SYS_HZ/2)	/* Initial delay	*/
+# define CONFIG_BOARD_EARLY_INIT_R
+#endif /* CONFIG_BC3450_PS2 */
+
+/*
+ * PCI Mapping:
+ * 0x40000000 - 0x4fffffff - PCI Memory
+ * 0x50000000 - 0x50ffffff - PCI IO Space
+ */
+# define CONFIG_PCI		1
+# define CONFIG_PCI_PNP		1
+/* #define CONFIG_PCI_SCAN_SHOW 1 */
+#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1
+
+#define CONFIG_PCI_MEM_BUS	0x40000000
+#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE	0x10000000
+
+#define CONFIG_PCI_IO_BUS	0x50000000
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0x01000000
+
+/*#define CONFIG_EEPRO100	XXX - FIXME: conflicts when CONFIG_MII is enabled */
+#define CONFIG_SYS_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100	*/
+#define CONFIG_NS8382X		1
+
+/*
+ * Video console
+ */
+# define CONFIG_VIDEO
+# define CONFIG_VIDEO_SM501
+# define CONFIG_VIDEO_SM501_32BPP
+# define CONFIG_CFB_CONSOLE
+# define CONFIG_VIDEO_LOGO
+# define CONFIG_VGA_AS_SINGLE_DEVICE
+# define CONFIG_CONSOLE_EXTRA_INFO	/* display Board/Device-Infos */
+# define CONFIG_VIDEO_SW_CURSOR
+# define CONFIG_SPLASH_SCREEN
+# define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+/*
+ * Partitions
+ */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+/*
+ * USB
+ */
+#ifdef CONFIG_BC3450_USB
+# define CONFIG_USB_OHCI
+# define CONFIG_USB_STORAGE
+#endif /* CONFIG_BC3450_USB */
+
+/*
+ * POST support
+ */
+#define CONFIG_POST		(CONFIG_SYS_POST_MEMORY   | \
+				 CONFIG_SYS_POST_CPU	   | \
+				 CONFIG_SYS_POST_I2C)
+
+#ifdef CONFIG_POST
+/* preserve space for the post_word at end of on-chip SRAM */
+# define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
+#endif /* CONFIG_POST */
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_BSP
+
+#ifdef CONFIG_VIDEO
+    #define CONFIG_CMD_BMP
+#endif
+
+#ifdef CONFIG_BC3450_IDE
+    #define CONFIG_CMD_IDE
+#endif
+
+#if defined(CONFIG_BC3450_IDE) || defined(CONFIG_BC3450_USB)
+    #ifdef CONFIG_FAT
+	#define CONFIG_CMD_FAT
+    #endif
+
+    #ifdef CONFIG_EXT2
+	#define CONFIG_CMD_EXT2
+    #endif
+#endif
+
+#ifdef CONFIG_BC3450_USB
+    #define CONFIG_CMD_USB
+#endif
+
+#ifdef CONFIG_PCI
+    #define CONFIG_CMD_PCI
+#endif
+
+#ifdef CONFIG_POST
+    #define CONFIG_CMD_DIAG
+#endif
+
+
+#define CONFIG_TIMESTAMP		/* display image timestamps */
+
+#if (CONFIG_SYS_TEXT_BASE == 0xFC000000)		/* Boot low */
+#   define CONFIG_SYS_LOWBOOT		1
+#endif
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+#define CONFIG_PREBOOT	"echo;" \
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+	"echo;"
+
+#undef	CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"ipaddr=192.168.1.10\0"						\
+	"serverip=192.168.1.3\0"					\
+	"netmask=255.255.255.0\0"					\
+	"hostname=bc3450\0"						\
+	"rootpath=/opt/eldk/ppc_6xx\0"					\
+	"kernel_addr=fc0a0000\0"					\
+	"ramdisk_addr=fc1c0000\0"					\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=$(serverip):$(rootpath)\0"			\
+	"ideargs=setenv bootargs root=/dev/hda2 ro\0"			\
+	"addip=setenv bootargs $(bootargs) "				\
+		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
+		":$(hostname):$(netdev):off panic=1\0"			\
+	"addcons=setenv bootargs $(bootargs) "				\
+		"console=ttyS0,$(baudrate) console=tty0\0"		\
+	"flash_self=run ramargs addip addcons;"				\
+		"bootm $(kernel_addr) $(ramdisk_addr)\0"		\
+	"flash_nfs=run nfsargs addip addcons; bootm $(kernel_addr)\0"	\
+	"net_nfs=tftp 200000 $(bootfile); "				\
+		"run nfsargs addip addcons; bootm\0"			\
+	"ide_nfs=run nfsargs addip addcons; "				\
+		"disk 200000 0:1; bootm\0"				\
+	"ide_ide=run ideargs addip addcons; "				\
+		"disk 200000 0:1; bootm\0"				\
+	"usb_self=run usbload; run ramargs addip addcons; "		\
+		"bootm 200000 400000\0"					\
+	"usbload=usb reset; usb scan; usbboot 200000 0:1; "		\
+		"usbboot 400000 0:2\0"					\
+	"bootfile=uImage\0"						\
+	"load=tftp 200000 $(u-boot)\0"					\
+	"u-boot=u-boot.bin\0"						\
+	"update=protect off FC000000 FC05FFFF;"				\
+		"erase FC000000 FC05FFFF;"				\
+		"cp.b 200000 FC000000 $(filesize);"			\
+		"protect on FC000000 FC05FFFF\0"			\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
+
+/*
+ * PCI Bus clocking configuration
+ *
+ * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
+ * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
+ *  of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
+ */
+#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
+# define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2	/* define for 66MHz speed */
+#endif
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #2 */
+
+/*
+ * I2C clock frequency
+ *
+ * Please notice, that the resulting clock frequency could differ from the
+ * configured value. This is because the I2C clock is derived from system
+ * clock over a frequency divider with only a few divider values. U-boot
+ * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
+ * approximation allways lies below the configured value, never above.
+ */
+#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+
+/*
+ * EEPROM configuration for I²C EEPROM M24C32
+ * M24C64 should work also. For other EEPROMs config should be verified.
+ *
+ * The TQM5200 module may hold an EEPROM at address 0x50.
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x (TQM) */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* =32 Bytes per write */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	70
+
+/*
+ * RTC configuration
+ */
+#if defined (CONFIG_BC3450_DS1340) && !defined (CONFIG_BC3450_DS3231)
+# define CONFIG_RTC_M41T11	1
+# define CONFIG_SYS_I2C_RTC_ADDR	0x68
+#else
+# define CONFIG_RTC_MPC5200	1	/* use MPC5200 internal RTC */
+# define CONFIG_BOARD_EARLY_INIT_R
+#endif
+
+/*
+ * Flash configuration
+ */
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_TEXT_BASE /* 0xFC000000 */
+
+/* use CFI flash driver if no module variant is spezified */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_BOOTCS_START }
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_SIZE		0x04000000 /* 64 MByte */
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sects on one chip */
+#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE	/* not supported yet for AMD */
+
+#if !defined(CONFIG_SYS_LOWBOOT)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000)
+#else	/* CONFIG_SYS_LOWBOOT */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00060000)
+#endif	/* CONFIG_SYS_LOWBOOT */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks
+					   (= chip selects) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
+
+/* Dynamic MTD partition support */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
+#define MTDIDS_DEFAULT		"nor0=TQM5200-0"
+#define MTDPARTS_DEFAULT	"mtdparts=TQM5200-0:640k(firmware),"	\
+						"1408k(kernel),"	\
+						"2m(initrd),"		\
+						"4m(small-fs),"		\
+						"16m(big-fs),"		\
+						"8m(misc)"
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_SIZE		0x10000
+#define CONFIG_ENV_SECT_SIZE	0x20000
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+/*
+ * Memory map
+ */
+#define CONFIG_SYS_MBAR		0xF0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
+
+/* Use ON-Chip SRAM until RAM will be available */
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+#ifdef CONFIG_POST
+/* preserve space for the post_word at end of on-chip SRAM */
+# define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_POST_SIZE
+#else
+# define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
+#endif /*CONFIG_POST*/
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN		(384 << 10) /* Reserve 384 kB for Monitor   */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10) /* Reserve 128 kB for malloc()  */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)   /* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ *
+ * Define CONFIG_MPC5xxx_MII10 to force FEC at 10MBIT
+ */
+#define CONFIG_MPC5xxx_FEC	1
+#define CONFIG_MPC5xxx_FEC_MII100
+#undef CONFIG_MPC5xxx_MII10
+#define CONFIG_PHY_ADDR		0x00
+
+/*
+ * GPIO configuration on BC3450
+ *
+ *  PSC1:   UART1 (Service-UART)	 [0x xxxxxxx4]
+ *  PSC2:   UART2			 [0x xxxxxx4x]
+ *    or:   AC/97 if CONFIG_BC3450_AC97	 [0x xxxxxx2x]
+ *  PSC3:   USB2			 [0x xxxxx1xx]
+ *  USB:    UART4(ext.)/UART5(int.)	 [0x xxxx2xxx]
+ *	      (this has to match
+ *	      CONFIG_USB_CONFIG which is
+ *	      used by usb_ohci.c to set
+ *	      the USB ports)
+ *  Eth:    10/100Mbit Ethernet		 [0x xxx0xxxx]
+ *	      (this is reset to '5'
+ *	      in FEC driver: fec.c)
+ *  PSC6:   UART6 (int. to PS/2 contr.)	 [0x xx5xxxxx]
+ *  ATA/CS: ???				 [0x x1xxxxxx]
+ *	    FIXME! UM Fig 2-10 suggests	 [0x x0xxxxxx]
+ *  CS1:    Use Pin gpio_wkup_6 as second
+ *	    SDRAM chip select (mem_cs1)
+ *  Timer:  CAN2 / SPI
+ *  I2C:    CAN1 / I²C2		  [0x bxxxxxxx]
+ */
+#ifdef CONFIG_BC3450_AC97
+# define CONFIG_SYS_GPS_PORT_CONFIG	0xb1502124
+#else /* PSC2=UART2 */
+# define CONFIG_SYS_GPS_PORT_CONFIG	0xb1502144
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP				/* undef to save memory	    */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size  */
+#else
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size  */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size  */
+#define CONFIG_SYS_MAXARGS		16		/* max no of command args   */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Arg. Buffer Size    */
+
+#define CONFIG_SYS_ALT_MEMTEST				/* Enable an alternative,   */
+						/*  more extensive mem test */
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on	    */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	    */
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	    */
+
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs		    */
+#if defined(CONFIG_CMD_KGDB)
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value    */
+#endif
+
+/*
+ * Enable loopw command.
+ */
+#define CONFIG_LOOPW
+
+/*
+ * Various low-level settings
+ */
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
+
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
+# define CONFIG_SYS_BOOTCS_CFG		0x0008DF30	/* for pci_clk	= 66 MHz */
+#else
+# define CONFIG_SYS_BOOTCS_CFG		0x0004DF30	/* for pci_clk = 33 MHz	 */
+#endif
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
+
+/* automatic configuration of chip selects */
+#ifdef CONFIG_TQM5200
+# define CONFIG_LAST_STAGE_INIT
+#endif /* CONFIG_TQM5200 */
+
+/*
+ * SRAM - Do not map below 2 GB in address space, because this area is used
+ * for SDRAM autosizing.
+ */
+#ifdef CONFIG_TQM5200
+# define CONFIG_SYS_CS2_START		0xE5000000
+# define CONFIG_SYS_CS2_SIZE		0x100000	/* 1 MByte */
+# define CONFIG_SYS_CS2_CFG		0x0004D930
+#endif /* CONFIG_TQM5200 */
+
+/*
+ * Grafic controller - Do not map below 2 GB in address space, because this
+ * area is used for SDRAM autosizing.
+ */
+#ifdef CONFIG_TQM5200
+# define SM501_FB_BASE		0xE0000000
+# define CONFIG_SYS_CS1_START		(SM501_FB_BASE)
+# define CONFIG_SYS_CS1_SIZE		0x4000000	/* 64 MByte */
+# define CONFIG_SYS_CS1_CFG		0x8F48FF70
+# define SM501_MMIO_BASE	CONFIG_SYS_CS1_START + 0x03E00000
+#endif /* CONFIG_TQM5200 */
+
+#define CONFIG_SYS_CS_BURST		0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE	0x33333311	/* 1 dead cycle for	*/
+						/*  flash and SM501	*/
+
+#define CONFIG_SYS_RESET_ADDRESS	0xff000000
+
+/*
+ * USB stuff
+ */
+#define CONFIG_USB_CLOCK	0x0001BBBB
+#define CONFIG_USB_CONFIG	0x00002000	/* we're using Port 2	*/
+
+/*
+ * IDE/ATA stuff Supports IDE harddisk
+ */
+#undef	CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card Adapter */
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	  not supported */
+#undef	CONFIG_IDE_LED			/* LED for ide	  not supported */
+
+#define CONFIG_IDE_RESET		/* reset for ide      supported */
+#define CONFIG_IDE_PREINIT
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	2	/* max. 2 drives per IDE bus	*/
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
+
+/* Offset for data I/O */
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
+
+/* Offset for normal register accesses */
+#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers */
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)
+
+/* Interval between registers */
+#define CONFIG_SYS_ATA_STRIDE		4
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/BSC9131RDB.h b/qemu/roms/u-boot/include/configs/BSC9131RDB.h
new file mode 100644
index 000000000..5a316c83a
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/BSC9131RDB.h
@@ -0,0 +1,444 @@
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * BSC9131 RDB board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifdef CONFIG_BSC9131RDB
+#define CONFIG_BSC9131
+#define CONFIG_NAND_FSL_IFC
+#endif
+
+#ifdef CONFIG_SPIFLASH
+#define CONFIG_RAMBOOT_SPIFLASH
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_SYS_TEXT_BASE		0x11000000
+#define CONFIG_RESET_VECTOR_ADDRESS	0x110bfffc
+#endif
+
+#ifdef CONFIG_NAND
+#define CONFIG_SPL
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BOOT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+
+#define CONFIG_SYS_TEXT_BASE		0x00201000
+#define CONFIG_SPL_TEXT_BASE		0xFFFFE000
+#define CONFIG_SPL_MAX_SIZE		8192
+#define CONFIG_SPL_RELOC_TEXT_BASE	0x00100000
+#define CONFIG_SPL_RELOC_STACK		0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	((768 << 10) - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_DST	(0x00200000 - CONFIG_SPL_MAX_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0
+#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE			/* BOOKE */
+#define CONFIG_E500			/* BOOKE e500 family */
+#define CONFIG_FSL_IFC			/* Enable IFC Support */
+
+#define CONFIG_FSL_LAW			/* Use common FSL init code */
+#define CONFIG_TSEC_ENET
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_DDR_CLK_FREQ	66666666 /* DDRCLK on 9131 RDB */
+#if defined(CONFIG_SYS_CLK_100)
+#define CONFIG_SYS_CLK_FREQ    100000000 /* SYSCLK for 9131 RDB */
+#else
+#define CONFIG_SYS_CLK_FREQ	66666666 /* SYSCLK for 9131 RDB */
+#endif
+
+#define CONFIG_HWCONFIG
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* enable branch predition */
+
+#define CONFIG_SYS_MEMTEST_START	0x01000000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x01ffffff
+
+/* DDR Setup */
+#define CONFIG_SYS_FSL_DDR3
+#undef CONFIG_SYS_DDR_RAW_TIMING
+#undef CONFIG_DDR_SPD
+#define CONFIG_SYS_SPD_BUS_NUM		0
+#define SPD_EEPROM_ADDRESS		0x52 /* I2C access */
+
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_sdram_size(void);
+#endif
+#define CONFIG_SYS_SDRAM_SIZE		get_sdram_size() /* DDR size */
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	1
+
+#define CONFIG_SYS_DDR_CS0_BNDS		0x0000003f
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80014302
+#define CONFIG_SYS_DDR_CS0_CONFIG_2	0x00000000
+
+#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
+#define CONFIG_SYS_DDR_INIT_ADDR	0x00000000
+#define CONFIG_SYS_DDR_INIT_EXT_ADDR	0x00000000
+#define CONFIG_SYS_DDR_MODE_CONTROL	0x00000000
+
+#define CONFIG_SYS_DDR_ZQ_CONTROL	0x89080600
+#define CONFIG_SYS_DDR_SR_CNTR		0x00000000
+#define CONFIG_SYS_DDR_RCW_1		0x00000000
+#define CONFIG_SYS_DDR_RCW_2		0x00000000
+#define CONFIG_SYS_DDR_CONTROL		0xC70C0000	/* Type = DDR3	*/
+#define CONFIG_SYS_DDR_CONTROL_2	0x24401000
+#define CONFIG_SYS_DDR_TIMING_4		0x00000001
+#define CONFIG_SYS_DDR_TIMING_5		0x02401400
+
+#define CONFIG_SYS_DDR_TIMING_3_800		0x00030000
+#define CONFIG_SYS_DDR_TIMING_0_800		0x00110104
+#define CONFIG_SYS_DDR_TIMING_1_800		0x6f6b8644
+#define CONFIG_SYS_DDR_TIMING_2_800		0x0fa888cf
+#define CONFIG_SYS_DDR_CLK_CTRL_800		0x03000000
+#define CONFIG_SYS_DDR_MODE_1_800		0x00441420
+#define CONFIG_SYS_DDR_MODE_2_800		0x8000c000
+#define CONFIG_SYS_DDR_INTERVAL_800		0x0c300100
+#define CONFIG_SYS_DDR_WRLVL_CONTROL_800	0x8675f608
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+/* relocated CCSRBAR */
+#define CONFIG_SYS_CCSRBAR	CONFIG_SYS_CCSRBAR_DEFAULT
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR_DEFAULT
+
+#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses */
+							/* CONFIG_SYS_IMMR */
+/* DSP CCSRBAR */
+#define CONFIG_SYS_FSL_DSP_CCSRBAR	CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
+#define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS	CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000	0x3FFF_FFFF	DDR			1G cacheable
+ * 0x8800_0000	0x8810_0000	IFC internal SRAM		1M
+ * 0xB000_0000	0xB0FF_FFFF	DSP core M2 memory	16M
+ * 0xC100_0000	0xC13F_FFFF	MAPLE-2F		4M
+ * 0xC1F0_0000	0xC1F3_FFFF	PA L2 SRAM Region 0	256K
+ * 0xC1F8_0000	0xC1F9_FFFF	PA L2 SRAM Region 1	128K
+ * 0xFED0_0000	0xFED0_3FFF	SEC Secured RAM		16K
+ * 0xFF60_0000	0xFF6F_FFFF	DSP CCSR		1M
+ * 0xFF70_0000	0xFF7F_FFFF	PA CCSR			1M
+ * 0xFF80_0000	0xFFFF_FFFF	Boot Page & NAND flash buffer	8M
+ *
+ */
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_NO_FLASH
+
+/* NAND Flash on IFC */
+#define CONFIG_SYS_NAND_BASE		0xff800000
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8	/* Port Size = 8 bit*/ \
+				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+
+#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
+				| CSOR_NAND_RAL_2	/* RAL = 2Byes */ \
+				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
+				| CSOR_NAND_SPRZ_64	/* Spare size = 64 */ \
+				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
+
+/* NAND Flash Timing Params */
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x03)  \
+					| FTIM0_NAND_TWP(0x05)   \
+					| FTIM0_NAND_TWCHT(0x02) \
+					| FTIM0_NAND_TWH(0x04))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x1C) \
+					| FTIM1_NAND_TWBE(0x1E) \
+					| FTIM1_NAND_TRR(0x07)  \
+					| FTIM1_NAND_TRP(0x05))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x08)  \
+					| FTIM2_NAND_TREH(0x04) \
+					| FTIM2_NAND_TWHRE(0x11))
+#define CONFIG_SYS_NAND_FTIM3		FTIM3_NAND_TWW(0x04)
+
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+
+#define CONFIG_SYS_NAND_DDR_LAW		11
+
+/* Set up IFC registers for boot location NAND */
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+
+#define CONFIG_BOARD_EARLY_INIT_F	/* Call board_pre_init */
+
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* stack in RAM */
+#define CONFIG_SYS_INIT_RAM_END		0x00004000/* End of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END \
+						- GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc*/
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX	1
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
+
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	/* determine from environment */
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#endif
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
+
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+
+/* I2C EEPROM */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+#define CONFIG_CMD_I2C
+
+
+#define CONFIG_FSL_ESPI
+/* eSPI - Enhanced SPI */
+#ifdef CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED		10000000
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
+#endif
+
+#if defined(CONFIG_TSEC_ENET)
+
+#define CONFIG_MII			/* MII PHY management */
+#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"eTSEC2"
+
+#define TSEC1_PHY_ADDR		0
+#define TSEC2_PHY_ADDR		3
+
+#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+
+#define TSEC1_PHYIDX		0
+
+#define TSEC2_PHYIDX		0
+
+#define CONFIG_ETHPRIME		"eTSEC1"
+
+#define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
+
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#if defined(CONFIG_RAMBOOT_SPIFLASH)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS	0
+#define CONFIG_ENV_SPI_CS	0
+#define CONFIG_ENV_SPI_MAX_HZ	10000000
+#define CONFIG_ENV_SPI_MODE	0
+#define CONFIG_ENV_OFFSET	0x100000	/* 1MB */
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#define CONFIG_ENV_SIZE		0x2000
+#elif defined(CONFIG_NAND)
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET	((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_RANGE	(3 * CONFIG_ENV_SIZE)
+#elif defined(CONFIG_SYS_RAMBOOT)
+#define CONFIG_ENV_IS_NOWHERE	/* Store ENV in memory only */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
+#define CONFIG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE		/* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ERRATA
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SETEXPR
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+						/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20) /* Increase max gunzip size */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+#define CONFIG_USB_EHCI
+
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_USB_STORAGE
+#define CONFIG_HAS_FSL_DR_USB
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#endif
+
+#define CONFIG_HOSTNAME		BSC9131rdb
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	"u-boot.bin" /* U-Boot image on TFTP server */
+
+#define CONFIG_BAUDRATE		115200
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"netdev=eth0\0"						\
+	"uboot=" CONFIG_UBOOTPATH "\0"				\
+	"loadaddr=1000000\0"			\
+	"bootfile=uImage\0"	\
+	"consoledev=ttyS0\0"				\
+	"ramdiskaddr=2000000\0"			\
+	"ramdiskfile=rootfs.ext2.gz.uboot\0"		\
+	"fdtaddr=c00000\0"				\
+	"fdtfile=bsc9131rdb.dtb\0"		\
+	"bdev=sda1\0"	\
+	"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"	\
+	"bootm_size=0x37000000\0"	\
+	"othbootargs=ramdisk_size=600000 " \
+	"default_hugepagesz=256m hugepagesz=256m hugepages=1\0" \
+	"usbext2boot=setenv bootargs root=/dev/ram rw "	\
+	"console=$consoledev,$baudrate $othbootargs; "	\
+	"usb start;"			\
+	"ext2load usb 0:4 $loadaddr $bootfile;"		\
+	"ext2load usb 0:4 $fdtaddr $fdtfile;"	\
+	"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"	\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr\0"	\
+
+#define CONFIG_RAMBOOTCOMMAND		\
+	"setenv bootargs root=/dev/ram rw "	\
+	"console=$consoledev,$baudrate $othbootargs; "	\
+	"tftp $ramdiskaddr $ramdiskfile;"	\
+	"tftp $loadaddr $bootfile;"		\
+	"tftp $fdtaddr $fdtfile;"		\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/BSC9132QDS.h b/qemu/roms/u-boot/include/configs/BSC9132QDS.h
new file mode 100644
index 000000000..e76a04b26
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/BSC9132QDS.h
@@ -0,0 +1,708 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * BSC9132 QDS board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifdef CONFIG_BSC9132QDS
+#define CONFIG_BSC9132
+#endif
+
+#define CONFIG_MISC_INIT_R
+
+#ifdef CONFIG_SDCARD
+#define CONFIG_RAMBOOT_SDCARD
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_SYS_TEXT_BASE		0x11000000
+#define CONFIG_RESET_VECTOR_ADDRESS	0x110bfffc
+#endif
+#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769	1
+#ifdef CONFIG_SPIFLASH
+#define CONFIG_RAMBOOT_SPIFLASH
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_SYS_TEXT_BASE		0x11000000
+#define CONFIG_RESET_VECTOR_ADDRESS	0x110bfffc
+#endif
+#ifdef CONFIG_NAND_SECBOOT
+#define CONFIG_RAMBOOT_NAND
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_SYS_TEXT_BASE		0x11000000
+#define CONFIG_RESET_VECTOR_ADDRESS	0x110bfffc
+#endif
+
+#ifdef CONFIG_NAND
+#define CONFIG_SPL
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BOOT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+
+#define CONFIG_SYS_TEXT_BASE		0x00201000
+#define CONFIG_SPL_TEXT_BASE		0xFFFFE000
+#define CONFIG_SPL_MAX_SIZE		8192
+#define CONFIG_SPL_RELOC_TEXT_BASE	0x00100000
+#define CONFIG_SPL_RELOC_STACK		0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	((768 << 10) - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_DST	(0x00200000 - CONFIG_SPL_MAX_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0
+#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#endif
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE		0x8ff40000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0x8ffffffc
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE			/* BOOKE */
+#define CONFIG_E500			/* BOOKE e500 family */
+#define CONFIG_FSL_IFC			/* Enable IFC Support */
+#define CONFIG_SYS_HAS_SERDES		/* common SERDES init code */
+
+#define CONFIG_PCI			/* Enable PCI/PCIE */
+#if defined(CONFIG_PCI)
+#define CONFIG_PCIE1			/* PCIE controler 1 (slot 1) */
+#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_FSL_PCIE_RESET		/* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
+
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+
+#define CONFIG_E1000			/*  E1000 pci Ethernet card*/
+
+/*
+ * PCI Windows
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+/* controller 1, Slot 1, tgtid 1, Base address a000 */
+#define CONFIG_SYS_PCIE1_NAME		"PCIe Slot"
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0x90000000
+#define CONFIG_SYS_PCIE1_MEM_BUS	0x90000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0x90000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xC0010000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xC0010000
+
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif
+
+#define CONFIG_FSL_LAW			/* Use common FSL init code */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_TSEC_ENET /* ethernet */
+
+#if defined(CONFIG_SYS_CLK_100_DDR_100)
+#define CONFIG_SYS_CLK_FREQ	100000000
+#define CONFIG_DDR_CLK_FREQ	100000000
+#elif defined(CONFIG_SYS_CLK_100_DDR_133)
+#define CONFIG_SYS_CLK_FREQ	100000000
+#define CONFIG_DDR_CLK_FREQ	133000000
+#endif
+
+#define CONFIG_MP
+
+#define CONFIG_HWCONFIG
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* enable branch predition */
+
+#define CONFIG_SYS_MEMTEST_START	0x01000000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x01ffffff
+
+/* DDR Setup */
+#define CONFIG_SYS_FSL_DDR3
+#define CONFIG_SYS_SPD_BUS_NUM		0
+#define SPD_EEPROM_ADDRESS1		0x54 /* I2C access */
+#define SPD_EEPROM_ADDRESS2		0x56 /* I2C access */
+#define CONFIG_FSL_DDR_INTERACTIVE
+
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+
+#define CONFIG_SYS_SDRAM_SIZE		(1024)
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+
+/* DDR3 Controller Settings */
+#define CONFIG_CHIP_SELECTS_PER_CTRL	1
+#define CONFIG_SYS_DDR_CS0_BNDS		0x0000003F
+#define CONFIG_SYS_DDR_CS0_CONFIG_1333	0x80004302
+#define CONFIG_SYS_DDR_CS0_CONFIG_800	0x80014302
+#define CONFIG_SYS_DDR_CS0_CONFIG_2	0x00000000
+#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
+#define CONFIG_SYS_DDR_INIT_ADDR	0x00000000
+#define CONFIG_SYS_DDR_INIT_EXT_ADDR	0x00000000
+#define CONFIG_SYS_DDR_MODE_CONTROL	0x00000000
+#define CONFIG_SYS_DDR1_CS0_BNDS       0x0040007F
+
+#define CONFIG_SYS_DDR_ZQ_CONTROL	0x89080600
+#define CONFIG_SYS_DDR_SR_CNTR		0x00000000
+#define CONFIG_SYS_DDR_RCW_1		0x00000000
+#define CONFIG_SYS_DDR_RCW_2		0x00000000
+#define CONFIG_SYS_DDR_CONTROL_800		0x470C0000
+#define CONFIG_SYS_DDR_CONTROL_2_800	0x04401050
+#define CONFIG_SYS_DDR_TIMING_4_800		0x00220001
+#define CONFIG_SYS_DDR_TIMING_5_800		0x03402400
+
+#define CONFIG_SYS_DDR_CONTROL_1333		0x470C0008
+#define CONFIG_SYS_DDR_CONTROL_2_1333	0x24401010
+#define CONFIG_SYS_DDR_TIMING_4_1333		0x00000001
+#define CONFIG_SYS_DDR_TIMING_5_1333		0x03401400
+
+#define CONFIG_SYS_DDR_TIMING_3_800		0x00020000
+#define CONFIG_SYS_DDR_TIMING_0_800		0x00330004
+#define CONFIG_SYS_DDR_TIMING_1_800		0x6f6B4846
+#define CONFIG_SYS_DDR_TIMING_2_800		0x0FA8C8CF
+#define CONFIG_SYS_DDR_CLK_CTRL_800		0x03000000
+#define CONFIG_SYS_DDR_MODE_1_800		0x40461520
+#define CONFIG_SYS_DDR_MODE_2_800		0x8000c000
+#define CONFIG_SYS_DDR_INTERVAL_800		0x0C300000
+#define CONFIG_SYS_DDR_WRLVL_CONTROL_800	0x8655A608
+
+#define CONFIG_SYS_DDR_TIMING_3_1333		0x01061000
+#define CONFIG_SYS_DDR_TIMING_0_1333		0x00440104
+#define CONFIG_SYS_DDR_TIMING_1_1333		0x98913A45
+#define CONFIG_SYS_DDR_TIMING_2_1333		0x0FB8B114
+#define CONFIG_SYS_DDR_CLK_CTRL_1333		0x02800000
+#define CONFIG_SYS_DDR_MODE_1_1333		0x00061A50
+#define CONFIG_SYS_DDR_MODE_2_1333		0x00100000
+#define CONFIG_SYS_DDR_INTERVAL_1333		0x144E0513
+#define CONFIG_SYS_DDR_WRLVL_CONTROL_1333	0x8655F607
+
+/*FIXME: the following params are constant w.r.t diff freq
+combinations. this should be removed later
+*/
+#if CONFIG_DDR_CLK_FREQ == 100000000
+#define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800
+#define CONFIG_SYS_DDR_CONTROL		CONFIG_SYS_DDR_CONTROL_800
+#define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800
+#define CONFIG_SYS_DDR_TIMING_4	CONFIG_SYS_DDR_TIMING_4_800
+#define CONFIG_SYS_DDR_TIMING_5	CONFIG_SYS_DDR_TIMING_5_800
+#elif CONFIG_DDR_CLK_FREQ == 133000000
+#define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_1333
+#define CONFIG_SYS_DDR_CONTROL		CONFIG_SYS_DDR_CONTROL_1333
+#define CONFIG_SYS_DDR_CONTROL_2	CONFIG_SYS_DDR_CONTROL_2_1333
+#define CONFIG_SYS_DDR_TIMING_4	CONFIG_SYS_DDR_TIMING_4_1333
+#define CONFIG_SYS_DDR_TIMING_5	CONFIG_SYS_DDR_TIMING_5_1333
+#else
+#define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800
+#define CONFIG_SYS_DDR_CONTROL		CONFIG_SYS_DDR_CONTROL_800
+#define CONFIG_SYS_DDR_CONTROL_2	CONFIG_SYS_DDR_CONTROL_2_800
+#define CONFIG_SYS_DDR_TIMING_4	CONFIG_SYS_DDR_TIMING_4_800
+#define CONFIG_SYS_DDR_TIMING_5	CONFIG_SYS_DDR_TIMING_5_800
+#endif
+
+
+/* relocated CCSRBAR */
+#define CONFIG_SYS_CCSRBAR	CONFIG_SYS_CCSRBAR_DEFAULT
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR_DEFAULT
+
+#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR
+
+/* DSP CCSRBAR */
+#define CONFIG_SYS_FSL_DSP_CCSRBAR	CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
+#define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS	CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
+
+/*
+ * IFC Definitions
+ */
+/* NOR Flash on IFC */
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_NO_FLASH
+#endif
+#define CONFIG_SYS_FLASH_BASE		0x88000000
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* Max number of sector: 32M */
+
+#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_SYS_NOR_CSPR	0x88000101
+#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
+#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(5)
+/* NOR Flash Timing Params */
+
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x01) \
+				| FTIM0_NOR_TEADC(0x03) \
+				| FTIM0_NOR_TAVDS(0x00) \
+				| FTIM0_NOR_TEAHC(0x0f))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x1d) \
+				| FTIM1_NOR_TRAD_NOR(0x09) \
+				| FTIM1_NOR_TSEQRAD_NOR(0x09))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x1) \
+				| FTIM2_NOR_TCH(0x4) \
+				| FTIM2_NOR_TWPH(0x7) \
+				| FTIM2_NOR_TWP(0x1e))
+#define CONFIG_SYS_NOR_FTIM3	0x0
+
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS}
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+/* CFI for NOR Flash */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/* NAND Flash on IFC */
+#define CONFIG_SYS_NAND_BASE		0xff800000
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+
+#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
+				| CSOR_NAND_RAL_2	/* RAL = 2Byes */ \
+				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
+				| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
+				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
+
+/* NAND Flash Timing Params */
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x03) \
+					| FTIM0_NAND_TWP(0x05) \
+					| FTIM0_NAND_TWCHT(0x02) \
+					| FTIM0_NAND_TWH(0x04))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x1c) \
+					| FTIM1_NAND_TWBE(0x1e) \
+					| FTIM1_NAND_TRR(0x07) \
+					| FTIM1_NAND_TRP(0x05))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x08) \
+					| FTIM2_NAND_TREH(0x04) \
+					| FTIM2_NAND_TWHRE(0x11))
+#define CONFIG_SYS_NAND_FTIM3		FTIM3_NAND_TWW(0x04)
+
+#define CONFIG_SYS_NAND_DDR_LAW		11
+
+/* NAND */
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_FSL_QIXIS
+#endif
+#ifdef CONFIG_FSL_QIXIS
+#define CONFIG_SYS_FPGA_BASE	0xffb00000
+#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
+#define QIXIS_BASE	CONFIG_SYS_FPGA_BASE
+#define QIXIS_LBMAP_SWITCH	9
+#define QIXIS_LBMAP_MASK	0x07
+#define QIXIS_LBMAP_SHIFT	0
+#define QIXIS_LBMAP_DFLTBANK		0x00
+#define QIXIS_LBMAP_ALTBANK		0x04
+#define QIXIS_RST_CTL_RESET		0x83
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+
+#define CONFIG_SYS_FPGA_BASE_PHYS	CONFIG_SYS_FPGA_BASE
+
+#define CONFIG_SYS_CSPR2		(CSPR_PHYS_ADDR(CONFIG_SYS_FPGA_BASE) \
+					| CSPR_PORT_SIZE_8 \
+					| CSPR_MSEL_GPCM \
+					| CSPR_V)
+#define CONFIG_SYS_AMASK2		IFC_AMASK(64*1024)
+#define CONFIG_SYS_CSOR2		0x0
+/* CPLD Timing parameters for IFC CS3 */
+#define CONFIG_SYS_CS2_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
+					FTIM0_GPCM_TEADC(0x0e) | \
+					FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS2_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \
+					FTIM1_GPCM_TRAD(0x1f))
+#define CONFIG_SYS_CS2_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
+					FTIM2_GPCM_TCH(0x0) | \
+					FTIM2_GPCM_TWP(0x1f))
+#define CONFIG_SYS_CS2_FTIM3		0x0
+#endif
+
+/* Set up IFC registers for boot location NOR/NAND */
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_F	/* Call board_pre_init */
+#define CONFIG_BOARD_EARLY_INIT_R
+
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* stack in RAM */
+#define CONFIG_SYS_INIT_RAM_END		0x00004000 /* End of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END \
+						- GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc*/
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX	1
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
+
+#define CONFIG_SERIAL_MULTI	1 /* Enable both serial ports */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	/* determine from environment */
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR + 0x4600)
+#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR + 0x4700)
+#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR + 0x4800)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER    /* hush parser */
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#endif
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
+
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400800 /* I2C speed and slave address*/
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_SPEED	400800 /* I2C speed and slave address*/
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+
+/* I2C EEPROM */
+#define CONFIG_ID_EEPROM
+#ifdef CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#endif
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_BUS_NUM	0
+
+/* enable read and write access to EEPROM */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+/* I2C FPGA */
+#define CONFIG_I2C_FPGA
+#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
+
+#define CONFIG_RTC_DS3231
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68
+
+/*
+ * SPI interface will not be available in case of NAND boot SPI CS0 will be
+ * used for SLIC
+ */
+/* eSPI - Enhanced SPI */
+#define CONFIG_FSL_ESPI  /* SPI */
+#ifdef CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED		10000000
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
+#endif
+
+#if defined(CONFIG_TSEC_ENET)
+
+#define CONFIG_MII			/* MII PHY management */
+#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"eTSEC2"
+
+#define TSEC1_PHY_ADDR		0
+#define TSEC2_PHY_ADDR		1
+
+#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+
+#define CONFIG_ETHPRIME		"eTSEC1"
+
+#define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
+
+/* TBI PHY configuration for SGMII mode */
+#define CONFIG_TSEC_TBICR_SETTINGS ( \
+		TBICR_PHY_RESET \
+		| TBICR_ANEG_ENABLE \
+		| TBICR_FULL_DUPLEX \
+		| TBICR_SPEED1_SET \
+		)
+
+#endif	/* CONFIG_TSEC_ENET */
+
+#define CONFIG_MMC
+#ifdef CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FSL_ESDHC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#endif
+
+#define CONFIG_USB_EHCI  /* USB */
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_USB_STORAGE
+#define CONFIG_HAS_FSL_DR_USB
+#endif
+
+/*
+ * Environment
+ */
+#if defined(CONFIG_RAMBOOT_SDCARD)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_FSL_FIXED_MMC_LOCATION
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_ENV_SIZE			0x2000
+#elif defined(CONFIG_RAMBOOT_SPIFLASH)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS	0
+#define CONFIG_ENV_SPI_CS	0
+#define CONFIG_ENV_SPI_MAX_HZ	10000000
+#define CONFIG_ENV_SPI_MODE	0
+#define CONFIG_ENV_OFFSET	0x100000	/* 1MB */
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#define CONFIG_ENV_SIZE		0x2000
+#elif defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET	((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_RANGE	(3 * CONFIG_ENV_SIZE)
+#elif defined(CONFIG_SYS_RAMBOOT)
+#define CONFIG_ENV_IS_NOWHERE		/* Store ENV in memory only */
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_MONITOR_BASE - 0x1000)
+#define CONFIG_ENV_SIZE			0x2000
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000
+#endif
+
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ERRATA
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
+
+#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+						/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20) /* Increase max gunzip size */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#endif
+
+#define CONFIG_HOSTNAME		BSC9132qds
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	"u-boot.bin"
+
+#define CONFIG_BAUDRATE		115200
+
+#ifdef CONFIG_SDCARD
+#define CONFIG_DEF_HWCONFIG	"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
+#else
+#define CONFIG_DEF_HWCONFIG	"hwconfig=sim;usb1:dr_mode=host,phy_type=ulpi\0"
+#endif
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"netdev=eth0\0"						\
+	"uboot=" CONFIG_UBOOTPATH "\0"				\
+	"loadaddr=1000000\0"			\
+	"bootfile=uImage\0"	\
+	"consoledev=ttyS0\0"				\
+	"ramdiskaddr=2000000\0"			\
+	"ramdiskfile=rootfs.ext2.gz.uboot\0"		\
+	"fdtaddr=c00000\0"				\
+	"fdtfile=bsc9132qds.dtb\0"		\
+	"bdev=sda1\0"	\
+	CONFIG_DEF_HWCONFIG\
+	"othbootargs=mem=880M ramdisk_size=600000 " \
+		"default_hugepagesz=256m hugepagesz=256m hugepages=1 " \
+		"isolcpus=0\0" \
+	"usbext2boot=setenv bootargs root=/dev/ram rw "	\
+		"console=$consoledev,$baudrate $othbootargs; "	\
+		"usb start;"			\
+		"ext2load usb 0:4 $loadaddr $bootfile;"		\
+		"ext2load usb 0:4 $fdtaddr $fdtfile;"	\
+		"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"	\
+		"bootm $loadaddr $ramdiskaddr $fdtaddr\0"	\
+	"debug_halt_off=mw ff7e0e30 0xf0000000;"
+
+#define CONFIG_NFSBOOTCOMMAND	\
+	"setenv bootargs root=/dev/nfs rw "	\
+	"nfsroot=$serverip:$rootpath "	\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs;" \
+	"tftp $loadaddr $bootfile;"	\
+	"tftp $fdtaddr $fdtfile;"	\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_HDBOOT	\
+	"setenv bootargs root=/dev/$bdev rw rootdelay=30 "	\
+	"console=$consoledev,$baudrate $othbootargs;" \
+	"usb start;"	\
+	"ext2load usb 0:1 $loadaddr /boot/$bootfile;"	\
+	"ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"	\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND		\
+	"setenv bootargs root=/dev/ram rw "	\
+	"console=$consoledev,$baudrate $othbootargs; "	\
+	"tftp $ramdiskaddr $ramdiskfile;"	\
+	"tftp $loadaddr $bootfile;"		\
+	"tftp $fdtaddr $fdtfile;"		\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
+
+#include <asm/fsl_secure_boot.h>
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/C29XPCIE.h b/qemu/roms/u-boot/include/configs/C29XPCIE.h
new file mode 100644
index 000000000..9e12fac5b
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/C29XPCIE.h
@@ -0,0 +1,577 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * C29XPCIE board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_PHYS_64BIT
+
+#ifdef CONFIG_C29XPCIE
+#define CONFIG_PPC_C29X
+#endif
+
+#ifdef CONFIG_SPIFLASH
+#define CONFIG_RAMBOOT_SPIFLASH
+#define CONFIG_SYS_TEXT_BASE		0x11000000
+#define CONFIG_RESET_VECTOR_ADDRESS	0x110bfffc
+#endif
+
+#ifdef CONFIG_NAND
+#define CONFIG_SPL
+#define CONFIG_TPL
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SPL_NAND_BOOT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_NAND_INIT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SPL_MAX_SIZE		(128 << 10)
+#define CONFIG_SPL_TEXT_BASE		0xf8f81000
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(832 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	(0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_START	(0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	((128 + 128) << 10)
+#elif defined(CONFIG_SPL_BUILD)
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TEXT_BASE		0xff800000
+#define CONFIG_SPL_MAX_SIZE		8192
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(128 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	0xf8f80000
+#define CONFIG_SYS_NAND_U_BOOT_START	0xf8f80000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(128 << 10)
+#endif
+#define CONFIG_SPL_PAD_TO		0x20000
+#define CONFIG_TPL_PAD_TO		0x20000
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SYS_TEXT_BASE		0x11001000
+#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#endif
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE		0xeff40000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE			/* BOOKE */
+#define CONFIG_E500			/* BOOKE e500 family */
+#define CONFIG_FSL_IFC			/* Enable IFC Support */
+#define CONFIG_SYS_HAS_SERDES		/* common SERDES init code */
+
+#define CONFIG_PCI			/* Enable PCI/PCIE */
+#ifdef CONFIG_PCI
+#define CONFIG_PCIE1			/* PCIE controler 1 (slot 1) */
+#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_FSL_PCIE_RESET		/* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
+
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+
+#define CONFIG_E1000
+
+/*
+ * PCI Windows
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+/* controller 1, Slot 1, tgtid 1, Base address a000 */
+#define CONFIG_SYS_PCIE1_NAME		"Slot 1"
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc00000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xfffc00000ull
+
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif
+
+#define CONFIG_FSL_LAW			/* Use common FSL init code */
+#define CONFIG_TSEC_ENET
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_DDR_CLK_FREQ	100000000
+#define CONFIG_SYS_CLK_FREQ	66666666
+
+#define CONFIG_HWCONFIG
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* toggle branch predition */
+
+#define CONFIG_ADDR_STREAMING		/* toggle addr streaming */
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#define CONFIG_ADDR_MAP			1
+#define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+#define CONFIG_PANIC_HANG
+
+/* DDR Setup */
+#define CONFIG_SYS_FSL_DDR3
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_SPD_BUS_NUM		0
+#define SPD_EEPROM_ADDRESS		0x50
+#define CONFIG_SYS_DDR_RAW_TIMING
+
+/* DDR ECC Setup*/
+#define CONFIG_DDR_ECC
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+
+#define CONFIG_SYS_SDRAM_SIZE		512
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	1
+
+#define CONFIG_SYS_CCSRBAR		0xffe00000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+
+/* Platform SRAM setting  */
+#define CONFIG_SYS_PLATFORM_SRAM_BASE	0xffb00000
+#define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \
+			(0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE)
+#define CONFIG_SYS_PLATFORM_SRAM_SIZE	(512 << 10)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_NO_FLASH
+#endif
+
+/*
+ * IFC Definitions
+ */
+/* NOR Flash on IFC */
+#define CONFIG_SYS_FLASH_BASE		0xec000000
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* 64M */
+
+#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE_PHYS }
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* in ms */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* in ms */
+
+/* 16Bit NOR Flash - S29GL512S10TFI01 */
+#define CONFIG_SYS_NOR_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(64*1024*1024)
+#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(4)
+
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
+				FTIM0_NOR_TEADC(0x5) | \
+				FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
+				FTIM1_NOR_TRAD_NOR(0x1A) |\
+				FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
+				FTIM2_NOR_TCH(0x4) | \
+				FTIM2_NOR_TWPH(0x0E) | \
+				FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3	0x0
+
+/* CFI for NOR Flash */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/* NAND Flash on IFC */
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_BASE		0xff800000
+#define CONFIG_SYS_NAND_BASE_PHYS	0xfff800000ull
+
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(1024 * 1024)
+
+/* 8Bit NAND Flash - K9F1G08U0B */
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 \
+				| CSPR_MSEL_NAND \
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+#define CONFIG_SYS_NAND_OOBSIZE	0x00000280	/* 640b */
+#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */ \
+				| CSOR_NAND_RAL_3	/* RAL = 3 Bytes */ \
+				| CSOR_NAND_PGS_8K	/* Page Size = 8K */ \
+				| CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\
+				| CSOR_NAND_PB(128))	/*128 Pages Per Block*/
+#define CONFIG_SYS_NAND_FTIM0	(FTIM0_NAND_TCCST(0x01) | \
+				FTIM0_NAND_TWP(0x0c)   | \
+				FTIM0_NAND_TWCHT(0x08) | \
+				FTIM0_NAND_TWH(0x06))
+#define CONFIG_SYS_NAND_FTIM1	(FTIM1_NAND_TADLE(0x28) | \
+				FTIM1_NAND_TWBE(0x1d)  | \
+				FTIM1_NAND_TRR(0x08)   | \
+				FTIM1_NAND_TRP(0x0c))
+#define CONFIG_SYS_NAND_FTIM2	(FTIM2_NAND_TRAD(0x0c) | \
+				FTIM2_NAND_TREH(0x0a) | \
+				FTIM2_NAND_TWHRE(0x18))
+#define CONFIG_SYS_NAND_FTIM3	(FTIM3_NAND_TWW(0x04))
+
+#define CONFIG_SYS_NAND_DDR_LAW		11
+
+/* Set up IFC registers for boot location NOR/NAND */
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CSOR0_EXT		CONFIG_SYS_NAND_OOBSIZE
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CSOR1_EXT		CONFIG_SYS_NAND_OOBSIZE
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
+#endif
+
+/* CPLD on IFC, selected by CS2 */
+#define CONFIG_SYS_CPLD_BASE		0xffdf0000
+#define CONFIG_SYS_CPLD_BASE_PHYS	(0xf00000000ull \
+					| CONFIG_SYS_CPLD_BASE)
+
+#define CONFIG_SYS_CSPR2	(CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 \
+				| CSPR_MSEL_GPCM \
+				| CSPR_V)
+#define CONFIG_SYS_AMASK2	IFC_AMASK(64*1024)
+#define CONFIG_SYS_CSOR2	0x0
+/* CPLD Timing parameters for IFC CS2 */
+#define CONFIG_SYS_CS2_FTIM0	(FTIM0_GPCM_TACSE(0x0e) | \
+				FTIM0_GPCM_TEADC(0x0e) | \
+				FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS2_FTIM1	(FTIM1_GPCM_TACO(0x0e) | \
+				FTIM1_GPCM_TRAD(0x1f))
+#define CONFIG_SYS_CS2_FTIM2	(FTIM2_GPCM_TCS(0x0e) | \
+				FTIM2_GPCM_TCH(0x0) | \
+				FTIM2_GPCM_TWP(0x1f))
+#define CONFIG_SYS_CS2_FTIM3	0x0
+
+#if defined(CONFIG_RAMBOOT_SPIFLASH)
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_R
+
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000
+#define CONFIG_SYS_INIT_RAM_END		0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END \
+						- GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(2 * 1024 * 1024)
+
+/*
+ * Config the L2 Cache as L2 SRAM
+ */
+#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE		(256 << 10)
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE	0xf8f81000
+#define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE	(32 << 10)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(96 << 10)
+#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
+#elif defined(CONFIG_NAND)
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE		(256 << 10)
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE	0xf8f81000
+#define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(48 << 10)
+#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
+#else
+#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE		(256 << 10)
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE	(CONFIG_SYS_INIT_L2_END - 0x3000)
+#define CONFIG_SPL_RELOC_STACK		((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
+#endif
+#endif
+#endif
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
+
+#define CONFIG_SERIAL_MULTI		/* Enable both serial ports */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
+
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+
+/* I2C EEPROM */
+/* enable read and write access to EEPROM */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+#define CONFIG_CMD_I2C
+
+/* eSPI - Enhanced SPI */
+#define CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_SPI_FLASH_EON
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED		10000000
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
+
+#ifdef CONFIG_TSEC_ENET
+#define CONFIG_NET_MULTI
+#define CONFIG_MII			/* MII PHY management */
+#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
+#define CONFIG_TSEC1		1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define CONFIG_TSEC2		1
+#define CONFIG_TSEC2_NAME	"eTSEC2"
+
+/* Default mode is RGMII mode */
+#define TSEC1_PHY_ADDR		0
+#define TSEC2_PHY_ADDR		2
+
+#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+
+#define CONFIG_ETHPRIME		"eTSEC1"
+
+#define CONFIG_PHY_GIGE
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#if defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_RAMBOOT_SPIFLASH)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS	0
+#define CONFIG_ENV_SPI_CS	0
+#define CONFIG_ENV_SPI_MAX_HZ	10000000
+#define CONFIG_ENV_SPI_MODE	0
+#define CONFIG_ENV_OFFSET	0x100000	/* 1MB */
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#define CONFIG_ENV_SIZE		0x2000
+#endif
+#elif defined(CONFIG_NAND)
+#define CONFIG_ENV_IS_IN_NAND
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
+#else
+#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_RANGE	CONFIG_ENV_SIZE
+#endif
+#define CONFIG_ENV_OFFSET	CONFIG_SYS_NAND_BLOCK_SIZE
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000
+#endif
+
+#define CONFIG_LOADS_ECHO
+#define CONFIG_SYS_LOADS_BAUD_CHANGE
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ERRATA
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+						/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20) /* Increase max gunzip size */
+
+/*
+ * Environment Configuration
+ */
+
+#ifdef CONFIG_TSEC_ENET
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#endif
+
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	u-boot.bin/* U-Boot image on TFTP server */
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+#define CONFIG_BOOTDELAY	-1	/* -1 disables auto-boot */
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_DEF_HWCONFIG	fsl_ddr:ecc=on
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hwconfig=" __stringify(CONFIG_DEF_HWCONFIG)  "\0"	\
+	"netdev=eth0\0"						\
+	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
+	"loadaddr=1000000\0"				\
+	"consoledev=ttyS0\0"				\
+	"ramdiskaddr=2000000\0"				\
+	"ramdiskfile=rootfs.ext2.gz.uboot\0"		\
+	"fdtaddr=c00000\0"				\
+	"fdtfile=name/of/device-tree.dtb\0"			\
+	"othbootargs=ramdisk_size=600000\0"		\
+
+#define CONFIG_RAMBOOTCOMMAND			\
+	"setenv bootargs root=/dev/ram rw "	\
+	"console=$consoledev,$baudrate $othbootargs; "	\
+	"tftp $ramdiskaddr $ramdiskfile;"	\
+	"tftp $loadaddr $bootfile;"		\
+	"tftp $fdtaddr $fdtfile;"		\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/CATcenter.h b/qemu/roms/u-boot/include/configs/CATcenter.h
new file mode 100644
index 000000000..27539d27d
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/CATcenter.h
@@ -0,0 +1,750 @@
+/*
+ * ueberarbeitet durch Christoph Seyfert
+ *
+ * (C) Copyright 2004-2005 DENX Software Engineering,
+ *     Wolfgang Grandegger <wg@denx.de>
+ * (C) Copyright 2003
+ *     DAVE Srl
+ *
+ * http://www.dave-tech.it
+ * http://www.wawnet.biz
+ * mailto:info@wawnet.biz
+ *
+ * Credits: Stefan Roese, Wolfgang Denk
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_PPCHAMELEON_MODULE_BA	0	/* Basic    Model */
+#define CONFIG_PPCHAMELEON_MODULE_ME	1	/* Medium   Model */
+#define CONFIG_PPCHAMELEON_MODULE_HI	2	/* High-End Model */
+#ifndef CONFIG_PPCHAMELEON_MODULE_MODEL
+#define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA
+#endif
+
+/* Only one of the following two symbols must be defined (default is 25 MHz)
+ * CONFIG_PPCHAMELEON_CLK_25
+ * CONFIG_PPCHAMELEON_CLK_33
+ */
+#if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33))
+#define CONFIG_PPCHAMELEON_CLK_25
+#endif
+
+#if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33))
+#error "* Two external frequencies (SysClk) are defined! *"
+#endif
+
+#undef CONFIG_PPCHAMELEON_SMI712
+
+/*
+ * Debug stuff
+ */
+#undef	__DEBUG_START_FROM_SRAM__
+#define __DISABLE_MACHINE_EXCEPTION__
+
+#ifdef __DEBUG_START_FROM_SRAM__
+#define CONFIG_SYS_DUMMY_FLASH_SIZE		1024*1024*4
+#endif
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_PPCHAMELEONEVB	1	/* ...on a PPChameleonEVB board */
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFB0000	/* Reserve 320 kB for Monitor */
+#define CONFIG_SYS_LDSCRIPT	"board/dave/PPChameleonEVB/u-boot.lds"
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
+
+#ifdef CONFIG_PPCHAMELEON_CLK_25
+# define CONFIG_SYS_CLK_FREQ	25000000 /* external frequency to pll   */
+#elif (defined (CONFIG_PPCHAMELEON_CLK_33))
+#define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll	*/
+#else
+# error "* External frequency (SysClk) not defined! *"
+#endif
+
+#define CONFIG_CONS_INDEX	2	/* Use UART1			*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_VERSION_VARIABLE	1	/* add version variable		*/
+#define CONFIG_IDENT_STRING	"1"
+
+#undef	CONFIG_BOOTARGS
+
+/* Ethernet stuff */
+#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
+#define CONFIG_ETHADDR	00:50:C2:1E:AF:FE
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR 00:50:C2:1E:AF:FD
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+
+#define CONFIG_PPC4xx_EMAC
+#undef CONFIG_EXT_PHY
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#ifndef	 CONFIG_EXT_PHY
+#define CONFIG_PHY_ADDR		1	/* EMAC0 PHY address		*/
+#define CONFIG_PHY1_ADDR	16	/* EMAC1 PHY address		*/
+#else
+#define CONFIG_PHY_ADDR		2	/* PHY address			*/
+#endif
+#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ
+
+#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_RTC_MC146818		/* DS1685 is MC146818 compatible*/
+#define CONFIG_SYS_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address		*/
+
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+
+#define	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK		/* no external serial clock used */
+#define CONFIG_SYS_BASE_BAUD		691200
+
+/* The following table includes the supported baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+/*-----------------------------------------------------------------------
+ * NAND-FLASH stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_NAND0_BASE 0xFF400000
+#define CONFIG_SYS_NAND1_BASE 0xFF000000
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND0_BASE }
+#define NAND_BIG_DELAY_US	25
+
+/* For CATcenter there is only NAND on the module */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
+#define NAND_NO_RB
+
+#define CONFIG_SYS_NAND0_CE  (0x80000000 >> 1)	 /* our CE is GPIO1 */
+#define CONFIG_SYS_NAND0_CLE (0x80000000 >> 2)	 /* our CLE is GPIO2 */
+#define CONFIG_SYS_NAND0_ALE (0x80000000 >> 3)	 /* our ALE is GPIO3 */
+#define CONFIG_SYS_NAND0_RDY (0x80000000 >> 4)	 /* our RDY is GPIO4 */
+
+#define CONFIG_SYS_NAND1_CE  (0x80000000 >> 14)  /* our CE is GPIO14 */
+#define CONFIG_SYS_NAND1_CLE (0x80000000 >> 15)  /* our CLE is GPIO15 */
+#define CONFIG_SYS_NAND1_ALE (0x80000000 >> 16)  /* our ALE is GPIO16 */
+#define CONFIG_SYS_NAND1_RDY (0x80000000 >> 31)  /* our RDY is GPIO31 */
+
+
+#define MACRO_NAND_DISABLE_CE(nandptr) do \
+{ \
+	switch((unsigned long)nandptr) \
+	{ \
+	    case CONFIG_SYS_NAND0_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CE); \
+		break; \
+	    case CONFIG_SYS_NAND1_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CE); \
+		break; \
+	} \
+} while(0)
+
+#define MACRO_NAND_ENABLE_CE(nandptr) do \
+{ \
+	switch((unsigned long)nandptr) \
+	{ \
+	    case CONFIG_SYS_NAND0_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CE); \
+		break; \
+	    case CONFIG_SYS_NAND1_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CE); \
+		break; \
+	} \
+} while(0)
+
+#define MACRO_NAND_CTL_CLRALE(nandptr) do \
+{ \
+	switch((unsigned long)nandptr) \
+	{ \
+	    case CONFIG_SYS_NAND0_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_ALE); \
+		break; \
+	    case CONFIG_SYS_NAND1_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_ALE); \
+		break; \
+	} \
+} while(0)
+
+#define MACRO_NAND_CTL_SETALE(nandptr) do \
+{ \
+	switch((unsigned long)nandptr) \
+	{ \
+	    case CONFIG_SYS_NAND0_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_ALE); \
+		break; \
+	    case CONFIG_SYS_NAND1_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_ALE); \
+		break; \
+	} \
+} while(0)
+
+#define MACRO_NAND_CTL_CLRCLE(nandptr) do \
+{ \
+	switch((unsigned long)nandptr) \
+	{ \
+	    case CONFIG_SYS_NAND0_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CLE); \
+		break; \
+	    case CONFIG_SYS_NAND1_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CLE); \
+		break; \
+	} \
+} while(0)
+
+#define MACRO_NAND_CTL_SETCLE(nandptr) do { \
+	switch((unsigned long)nandptr) { \
+	case CONFIG_SYS_NAND0_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CLE); \
+		break; \
+	case CONFIG_SYS_NAND1_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CLE); \
+		break; \
+	} \
+} while(0)
+
+#ifdef NAND_NO_RB
+/* constant delay (see also tR in the datasheet) */
+#define NAND_WAIT_READY(nand) do { \
+	udelay(12); \
+} while (0)
+#else
+/* use the R/B pin */
+/* TBD */
+#endif
+
+#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
+#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
+#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
+#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#if 0	/* No PCI on CATcenter */
+#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_HOST PCI_HOST_FORCE	 /* select pci host function	 */
+#undef	CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+					/* resource configuration	*/
+
+#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014	/* PCI Vendor ID: IBM	*/
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000	/* PCI Device ID: ---	*/
+#define CONFIG_SYS_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
+
+#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CONFIG_SYS_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CONFIG_SYS_PCI_PTM2LA	0xffc00000	/* point to flash		*/
+#define CONFIG_SYS_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
+#define CONFIG_SYS_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+#endif	/* No PCI */
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFFC0000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
+
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+/*-----------------------------------------------------------------------
+ * Environment Variable setup
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars */
+#define CONFIG_ENV_ADDR		0xFFFF8000	/* environment starts at the first small sector */
+#define CONFIG_ENV_SECT_SIZE	0x2000	/* 8196 bytes may be used for env vars*/
+#define CONFIG_ENV_ADDR_REDUND	0xFFFFA000
+#define CONFIG_ENV_SIZE_REDUND	0x2000
+
+#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
+#define CONFIG_SYS_NVRAM_SIZE		242			/* NVRAM size		*/
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+/*#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last 4 bits of the address	*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
+#define CONFIG_SYS_EBC_PB0AP		0x92015480
+#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (External SRAM) initialization					*/
+/* Since this must replace NOR Flash, we use the same settings for CS0		*/
+#define CONFIG_SYS_EBC_PB1AP		0x92015480
+#define CONFIG_SYS_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 2 (Flash Bank 1, NAND-FLASH) initialization			*/
+#define CONFIG_SYS_EBC_PB2AP		0x92015480
+#define CONFIG_SYS_EBC_PB2CR		0xFF458000  /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 3 (Flash Bank 2, NAND-FLASH) initialization			*/
+#define CONFIG_SYS_EBC_PB3AP		0x92015480
+#define CONFIG_SYS_EBC_PB3CR		0xFF058000  /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit	*/
+
+#ifdef CONFIG_PPCHAMELEON_SMI712
+/*
+ * Video console (graphic: SMI LynxEM)
+ */
+#define CONFIG_VIDEO
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_SMI_LYNXEM
+#define CONFIG_VIDEO_LOGO
+/*#define CONFIG_VIDEO_BMP_LOGO*/
+#define CONFIG_CONSOLE_EXTRA_INFO
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+/* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */
+#define CONFIG_SYS_ISA_IO 0xE8000000
+/* see also drivers/video/videomodes.c */
+#define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x303
+#endif
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ */
+/* FPGA internal regs */
+#define CONFIG_SYS_FPGA_MODE		0x00
+#define CONFIG_SYS_FPGA_STATUS		0x02
+#define CONFIG_SYS_FPGA_TS		0x04
+#define CONFIG_SYS_FPGA_TS_LOW		0x06
+#define CONFIG_SYS_FPGA_TS_CAP0	0x10
+#define CONFIG_SYS_FPGA_TS_CAP0_LOW	0x12
+#define CONFIG_SYS_FPGA_TS_CAP1	0x14
+#define CONFIG_SYS_FPGA_TS_CAP1_LOW	0x16
+#define CONFIG_SYS_FPGA_TS_CAP2	0x18
+#define CONFIG_SYS_FPGA_TS_CAP2_LOW	0x1a
+#define CONFIG_SYS_FPGA_TS_CAP3	0x1c
+#define CONFIG_SYS_FPGA_TS_CAP3_LOW	0x1e
+
+/* FPGA Mode Reg */
+#define CONFIG_SYS_FPGA_MODE_CF_RESET	0x0001
+#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
+#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR  0x1000
+#define CONFIG_SYS_FPGA_MODE_TS_CLEAR	0x2000
+
+/* FPGA Status Reg */
+#define CONFIG_SYS_FPGA_STATUS_DIP0	0x0001
+#define CONFIG_SYS_FPGA_STATUS_DIP1	0x0002
+#define CONFIG_SYS_FPGA_STATUS_DIP2	0x0004
+#define CONFIG_SYS_FPGA_STATUS_FLASH	0x0008
+#define CONFIG_SYS_FPGA_STATUS_TS_IRQ	0x1000
+
+#define CONFIG_SYS_FPGA_SPARTAN2	1		/* using Xilinx Spartan 2 now	*/
+#define CONFIG_SYS_FPGA_MAX_SIZE	128*1024	/* 128kByte is enough for XC2S50E*/
+
+/* FPGA program pin configuration */
+#define CONFIG_SYS_FPGA_PRG		0x04000000	/* FPGA program pin (ppc output) */
+#define CONFIG_SYS_FPGA_CLK		0x02000000	/* FPGA clk pin (ppc output)	*/
+#define CONFIG_SYS_FPGA_DATA		0x01000000	/* FPGA data pin (ppc output)	*/
+#define CONFIG_SYS_FPGA_INIT		0x00010000	/* FPGA init pin (ppc input)	*/
+#define CONFIG_SYS_FPGA_DONE		0x00008000	/* FPGA done pin (ppc input)	*/
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CONFIG_SYS_TEMP_STACK_OCM	1
+
+/* On Chip Memory location */
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
+
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO setup (PPC405EP specific)
+ *
+ * GPIO0[0]	- External Bus Controller BLAST output
+ * GPIO0[1-9]	- Instruction trace outputs -> GPIO
+ * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
+ * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
+ * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
+ * GPIO0[24-27] - UART0 control signal inputs/outputs
+ * GPIO0[28-29] - UART1 data signal input/output
+ * GPIO0[30]	- EMAC0 input
+ * GPIO0[31]	- EMAC1 reject packet as output
+ */
+#define CONFIG_SYS_GPIO0_OSRL		0x40000550
+#define CONFIG_SYS_GPIO0_OSRH		0x00000110
+#define CONFIG_SYS_GPIO0_ISR1L		0x00000000
+/*#define CONFIG_SYS_GPIO0_ISR1H	0x15555445*/
+#define CONFIG_SYS_GPIO0_ISR1H		0x15555444
+#define CONFIG_SYS_GPIO0_TSRL		0x00000000
+#define CONFIG_SYS_GPIO0_TSRH		0x00000000
+#define CONFIG_SYS_GPIO0_TCR		0xF7FF8014
+
+#define CONFIG_NO_SERIAL_EEPROM
+
+/*--------------------------------------------------------------------*/
+
+#ifdef CONFIG_NO_SERIAL_EEPROM
+
+/*
+!-----------------------------------------------------------------------
+! Defines for entry options.
+! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
+!	are plugged in the board will be utilized as non-ECC DIMMs.
+!-----------------------------------------------------------------------
+*/
+#undef		AUTO_MEMORY_CONFIG
+#define		DIMM_READ_ADDR 0xAB
+#define		DIMM_WRITE_ADDR 0xAA
+
+/* Defines for CPC0_PLLMR1 Register fields */
+#define PLL_ACTIVE		0x80000000
+#define CPC0_PLLMR1_SSCS	0x80000000
+#define PLL_RESET		0x40000000
+#define CPC0_PLLMR1_PLLR	0x40000000
+    /* Feedback multiplier */
+#define PLL_FBKDIV		0x00F00000
+#define CPC0_PLLMR1_FBDV	0x00F00000
+#define PLL_FBKDIV_16		0x00000000
+#define PLL_FBKDIV_1		0x00100000
+#define PLL_FBKDIV_2		0x00200000
+#define PLL_FBKDIV_3		0x00300000
+#define PLL_FBKDIV_4		0x00400000
+#define PLL_FBKDIV_5		0x00500000
+#define PLL_FBKDIV_6		0x00600000
+#define PLL_FBKDIV_7		0x00700000
+#define PLL_FBKDIV_8		0x00800000
+#define PLL_FBKDIV_9		0x00900000
+#define PLL_FBKDIV_10		0x00A00000
+#define PLL_FBKDIV_11		0x00B00000
+#define PLL_FBKDIV_12		0x00C00000
+#define PLL_FBKDIV_13		0x00D00000
+#define PLL_FBKDIV_14		0x00E00000
+#define PLL_FBKDIV_15		0x00F00000
+    /* Forward A divisor */
+#define PLL_FWDDIVA		0x00070000
+#define CPC0_PLLMR1_FWDVA	0x00070000
+#define PLL_FWDDIVA_8		0x00000000
+#define PLL_FWDDIVA_7		0x00010000
+#define PLL_FWDDIVA_6		0x00020000
+#define PLL_FWDDIVA_5		0x00030000
+#define PLL_FWDDIVA_4		0x00040000
+#define PLL_FWDDIVA_3		0x00050000
+#define PLL_FWDDIVA_2		0x00060000
+#define PLL_FWDDIVA_1		0x00070000
+    /* Forward B divisor */
+#define PLL_FWDDIVB		0x00007000
+#define CPC0_PLLMR1_FWDVB	0x00007000
+#define PLL_FWDDIVB_8		0x00000000
+#define PLL_FWDDIVB_7		0x00001000
+#define PLL_FWDDIVB_6		0x00002000
+#define PLL_FWDDIVB_5		0x00003000
+#define PLL_FWDDIVB_4		0x00004000
+#define PLL_FWDDIVB_3		0x00005000
+#define PLL_FWDDIVB_2		0x00006000
+#define PLL_FWDDIVB_1		0x00007000
+    /* PLL tune bits */
+#define PLL_TUNE_MASK		0x000003FF
+#define PLL_TUNE_2_M_3		0x00000133	/*  2 <= M <= 3			*/
+#define PLL_TUNE_4_M_6		0x00000134	/*  3 <	 M <= 6			*/
+#define PLL_TUNE_7_M_10		0x00000138	/*  6 <	 M <= 10		*/
+#define PLL_TUNE_11_M_14	0x0000013C	/* 10 <	 M <= 14		*/
+#define PLL_TUNE_15_M_40	0x0000023E	/* 14 <	 M <= 40		*/
+#define PLL_TUNE_VCO_LOW	0x00000000	/* 500MHz <= VCO <=  800MHz	*/
+#define PLL_TUNE_VCO_HI		0x00000080	/* 800MHz <  VCO <= 1000MHz	*/
+
+/* Defines for CPC0_PLLMR0 Register fields */
+    /* CPU divisor */
+#define PLL_CPUDIV		0x00300000
+#define CPC0_PLLMR0_CCDV	0x00300000
+#define PLL_CPUDIV_1		0x00000000
+#define PLL_CPUDIV_2		0x00100000
+#define PLL_CPUDIV_3		0x00200000
+#define PLL_CPUDIV_4		0x00300000
+    /* PLB divisor */
+#define PLL_PLBDIV		0x00030000
+#define CPC0_PLLMR0_CBDV	0x00030000
+#define PLL_PLBDIV_1		0x00000000
+#define PLL_PLBDIV_2		0x00010000
+#define PLL_PLBDIV_3		0x00020000
+#define PLL_PLBDIV_4		0x00030000
+    /* OPB divisor */
+#define PLL_OPBDIV		0x00003000
+#define CPC0_PLLMR0_OPDV	0x00003000
+#define PLL_OPBDIV_1		0x00000000
+#define PLL_OPBDIV_2		0x00001000
+#define PLL_OPBDIV_3		0x00002000
+#define PLL_OPBDIV_4		0x00003000
+    /* EBC divisor */
+#define PLL_EXTBUSDIV		0x00000300
+#define CPC0_PLLMR0_EPDV	0x00000300
+#define PLL_EXTBUSDIV_2		0x00000000
+#define PLL_EXTBUSDIV_3		0x00000100
+#define PLL_EXTBUSDIV_4		0x00000200
+#define PLL_EXTBUSDIV_5		0x00000300
+    /* MAL divisor */
+#define PLL_MALDIV		0x00000030
+#define CPC0_PLLMR0_MPDV	0x00000030
+#define PLL_MALDIV_1		0x00000000
+#define PLL_MALDIV_2		0x00000010
+#define PLL_MALDIV_3		0x00000020
+#define PLL_MALDIV_4		0x00000030
+    /* PCI divisor */
+#define PLL_PCIDIV		0x00000003
+#define CPC0_PLLMR0_PPFD	0x00000003
+#define PLL_PCIDIV_1		0x00000000
+#define PLL_PCIDIV_2		0x00000001
+#define PLL_PCIDIV_3		0x00000002
+#define PLL_PCIDIV_4		0x00000003
+
+#ifdef CONFIG_PPCHAMELEON_CLK_25
+/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 25.0 MHz input clock to the 405EP) */
+#define PPCHAMELEON_PLLMR0_133_133_33_66_33	 (PLL_CPUDIV_1 | PLL_PLBDIV_1 |	 \
+			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |	\
+			      PLL_MALDIV_1 | PLL_PCIDIV_4)
+#define PPCHAMELEON_PLLMR1_133_133_33_66_33	 (PLL_FBKDIV_8	|  \
+			      PLL_FWDDIVA_6 | PLL_FWDDIVB_4 |  \
+			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+
+#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |  \
+			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |	\
+			      PLL_MALDIV_1 | PLL_PCIDIV_4)
+#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_8  |  \
+			      PLL_FWDDIVA_4 | PLL_FWDDIVB_4 |  \
+			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+
+#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |	\
+			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |	\
+			      PLL_MALDIV_1 | PLL_PCIDIV_4)
+#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8  |  \
+			      PLL_FWDDIVA_3 | PLL_FWDDIVB_4 |  \
+			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+
+#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 |	\
+			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |	\
+			      PLL_MALDIV_1 | PLL_PCIDIV_2)
+#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10	|  \
+			      PLL_FWDDIVA_3 | PLL_FWDDIVB_4 |  \
+			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
+
+#elif (defined (CONFIG_PPCHAMELEON_CLK_33))
+
+/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */
+#define PPCHAMELEON_PLLMR0_133_133_33_66_33	 (PLL_CPUDIV_1 | PLL_PLBDIV_1 |	 \
+				  PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |	\
+				  PLL_MALDIV_1 | PLL_PCIDIV_4)
+#define PPCHAMELEON_PLLMR1_133_133_33_66_33	 (PLL_FBKDIV_4	|  \
+				  PLL_FWDDIVA_6 | PLL_FWDDIVB_6 |  \
+				  PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+
+#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |  \
+				  PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |	\
+				  PLL_MALDIV_1 | PLL_PCIDIV_4)
+#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_6  |  \
+				  PLL_FWDDIVA_4 | PLL_FWDDIVB_4 |  \
+				  PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+
+#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |	\
+				  PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |	\
+				  PLL_MALDIV_1 | PLL_PCIDIV_4)
+#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8  |  \
+				  PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
+				  PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+
+#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 |	\
+				  PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |	\
+				  PLL_MALDIV_1 | PLL_PCIDIV_2)
+#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10	|  \
+				  PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
+				  PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
+
+#else
+#error "* External frequency (SysClk) not defined! *"
+#endif
+
+#if   (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
+/* Model HI */
+#define PLLMR0_DEFAULT	PPCHAMELEON_PLLMR0_333_111_37_55_55
+#define PLLMR1_DEFAULT	PPCHAMELEON_PLLMR1_333_111_37_55_55
+#define CONFIG_SYS_OPB_FREQ	55555555
+/* Model ME */
+#elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
+#define PLLMR0_DEFAULT	PPCHAMELEON_PLLMR0_266_133_33_66_33
+#define PLLMR1_DEFAULT	PPCHAMELEON_PLLMR1_266_133_33_66_33
+#define CONFIG_SYS_OPB_FREQ	66666666
+#else
+/* Model BA (default) */
+#define PLLMR0_DEFAULT	PPCHAMELEON_PLLMR0_133_133_33_66_33
+#define PLLMR1_DEFAULT	PPCHAMELEON_PLLMR1_133_133_33_66_33
+#define CONFIG_SYS_OPB_FREQ	66666666
+#endif
+
+#endif /* CONFIG_NO_SERIAL_EEPROM */
+
+#define CONFIG_JFFS2_NAND 1			/* jffs2 on nand support */
+#define NAND_CACHE_PAGES 16			/* size of nand cache in 512 bytes pages */
+
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition */
+#undef CONFIG_CMD_MTDPARTS
+#define CONFIG_JFFS2_DEV		"nand"
+#define CONFIG_JFFS2_PART_SIZE		0x00200000
+#define CONFIG_JFFS2_PART_OFFSET	0x00000000
+
+/* mtdparts command line support
+ *
+ * Note: fake mtd_id used, no linux mtd map file
+ */
+/*
+#define CONFIG_CMD_MTDPARTS
+#define MTDIDS_DEFAULT		"nand0=catcenter"
+#define MTDPARTS_DEFAULT	"mtdparts=catcenter:2m(nand)"
+*/
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/CMS700.h b/qemu/roms/u-boot/include/configs/CMS700.h
new file mode 100644
index 000000000..5b872f61a
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/CMS700.h
@@ -0,0 +1,308 @@
+/*
+ * (C) Copyright 2005
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * CMS700.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_VOM405		1	/* ...on a VOM405 board		*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFC8000
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
+
+#define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/
+
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+#undef	CONFIG_BOOTARGS
+#undef  CONFIG_BOOTCOMMAND
+
+#define CONFIG_PREBOOT                  /* enable preboot variable      */
+
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_PPC4xx_EMAC
+#undef  CONFIG_HAS_ETH1
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_EEPROM
+
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+#undef  CONFIG_PRAM			/* no "protected RAM"           */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+
+#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CONFIG_CONS_INDEX	2	/* Use UART1			*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CONFIG_SYS_BASE_BAUD	    691200
+
+/* The following table includes the supported baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+#define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+
+/*-----------------------------------------------------------------------
+ * RTC stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_RTC_DS1337
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68
+
+/*-----------------------------------------------------------------------
+ * NAND-FLASH stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1         /* Max number of NAND devices */
+#define NAND_BIG_DELAY_US	25
+
+#define CONFIG_SYS_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
+#define CONFIG_SYS_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
+#define CONFIG_SYS_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
+#define CONFIG_SYS_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
+
+#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1       /* ".i" read skips bad blocks   */
+#define CONFIG_SYS_NAND_QUIET          1
+
+#define CONFIG_SYS_NAND_MAX_OOBFREE	2
+#define CONFIG_SYS_NAND_MAX_ECCPOS	48
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
+
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(~(CONFIG_SYS_TEXT_BASE) + 1)
+#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)
+
+#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
+# define CONFIG_SYS_RAMBOOT		1
+#else
+# undef CONFIG_SYS_RAMBOOT
+#endif
+
+/*-----------------------------------------------------------------------
+ * Environment Variable setup
+ */
+#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CONFIG_ENV_OFFSET		0x100	/* environment starts at the beginning of the EEPROM */
+#define CONFIG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
+				   /* total size of a CAT24WC16 is 2048 bytes */
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		100000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last 4 bits of the address	*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+
+#define CONFIG_SYS_EEPROM_WREN         1
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+#define CONFIG_SYS_PLD_BASE            0xf0000000
+#define CONFIG_SYS_NAND_BASE	        0xF4000000  /* NAND FLASH Base Address		*/
+
+/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
+#define CONFIG_SYS_EBC_PB0AP		0x92015480
+#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization			*/
+#define CONFIG_SYS_EBC_PB1AP		0x92015480
+#define CONFIG_SYS_EBC_PB1CR		0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization		*/
+#define CONFIG_SYS_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ */
+#define CONFIG_SYS_XSVF_DEFAULT_ADDR	0xfffc0000
+
+/* FPGA program pin configuration */
+#define CONFIG_SYS_FPGA_PRG		0x04000000  /* JTAG TMS pin (ppc output)     */
+#define CONFIG_SYS_FPGA_CLK		0x02000000  /* JTAG TCK pin (ppc output)     */
+#define CONFIG_SYS_FPGA_DATA		0x01000000  /* JTAG TDO->TDI data pin (ppc output) */
+#define CONFIG_SYS_FPGA_INIT		0x00010000  /* unused (ppc input)	     */
+#define CONFIG_SYS_FPGA_DONE		0x00008000  /* JTAG TDI->TDO pin (ppc input) */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CONFIG_SYS_TEMP_STACK_OCM	  1
+
+/* On Chip Memory location */
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
+
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO setup (PPC405EP specific)
+ *
+ * GPIO0[0]	- External Bus Controller BLAST output
+ * GPIO0[1-9]	- Instruction trace outputs -> GPIO
+ * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
+ * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
+ * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
+ * GPIO0[24-27] - UART0 control signal inputs/outputs
+ * GPIO0[28-29] - UART1 data signal input/output
+ * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
+ */
+/* GPIO Input:		OSR=00, ISR=00, TSR=00, TCR=0 */
+/* GPIO Output:		OSR=00, ISR=00, TSR=00, TCR=1 */
+/* Alt. Funtion Input:	OSR=00, ISR=01, TSR=00, TCR=0 */
+/* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
+#define CONFIG_SYS_GPIO0_OSRL		0x40000500  /*	0 ... 15 */
+#define CONFIG_SYS_GPIO0_OSRH		0x00000110  /* 16 ... 31 */
+#define CONFIG_SYS_GPIO0_ISR1L		0x00000000  /*	0 ... 15 */
+#define CONFIG_SYS_GPIO0_ISR1H		0x14000045  /* 16 ... 31 */
+#define CONFIG_SYS_GPIO0_TSRL		0x00000000  /*	0 ... 15 */
+#define CONFIG_SYS_GPIO0_TSRH		0x00000000  /* 16 ... 31 */
+#define CONFIG_SYS_GPIO0_TCR		0xF7FE0014  /*	0 ... 31 */
+
+#define CONFIG_SYS_EEPROM_WP		(0x80000000 >> 8)    /* GPIO8 */
+#define CONFIG_SYS_PLD_RESET		(0x80000000 >> 12)   /* GPIO12 */
+
+/*
+ * Default speed selection (cpu_plb_opb_ebc) in mhz.
+ * This value will be set if iic boot eprom is disabled.
+ */
+#define PLLMR0_DEFAULT	 PLLMR0_133_66_66_33
+#define PLLMR1_DEFAULT	 PLLMR1_133_66_66_33
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/CPC45.h b/qemu/roms/u-boot/include/configs/CPC45.h
new file mode 100644
index 000000000..a75c52f2c
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/CPC45.h
@@ -0,0 +1,489 @@
+/*
+ * (C) Copyright 2001-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ *
+ * Configuration settings for the CPC45 board.
+ *
+ */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC8245		1
+#define CONFIG_CPC45		1
+
+#define CONFIG_SYS_TEXT_BASE	0xFFF00000
+
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		9600
+
+#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
+
+#define CONFIG_BOOTDELAY	5
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+
+#if 1
+#define CONFIG_SYS_HUSH_PARSER		1	/* use "hush" command parser	*/
+#endif
+
+/* Print Buffer Size
+ */
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_LOAD_ADDR	0x00100000	/* Default load address		*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+
+#if defined(CONFIG_BOOT_ROM)
+#define CONFIG_SYS_FLASH_BASE		0xFF000000
+#else
+#define CONFIG_SYS_FLASH_BASE		0xFF800000
+#endif
+
+#define CONFIG_SYS_RESET_ADDRESS	0xFFF00100
+
+#define CONFIG_SYS_EUMB_ADDR		0xFCE00000
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x00004000	/* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END		0x02000000	/* 0 ... 32 MB in DRAM		*/
+
+/* Maximum amount of RAM.
+ */
+#define CONFIG_SYS_MAX_RAM_SIZE	0x10000000
+
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+#undef CONFIG_SYS_RAMBOOT
+#else
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area
+ */
+
+#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_EUMB_ADDR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_EUMB_ADDR + 0x4600)
+#define DUART_DCR		(CONFIG_SYS_EUMB_ADDR + 0x4511)
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+
+#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+
+/*
+ * RTC configuration
+ */
+#define CONFIG_RTC_PCF8563
+#define CONFIG_SYS_I2C_RTC_ADDR	0x51
+
+/*
+ * EEPROM configuration
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x58
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ * For the detail description refer to the MPC8240 user's manual.
+ */
+
+#define CONFIG_SYS_CLK_FREQ	33000000
+
+
+/* Bit-field values for MCCR1.
+ */
+#define CONFIG_SYS_ROMNAL		0
+#define CONFIG_SYS_ROMFAL		8
+
+#define CONFIG_SYS_BANK0_ROW		0	/* SDRAM bank 7-0 row address */
+#define CONFIG_SYS_BANK1_ROW		0
+#define CONFIG_SYS_BANK2_ROW		0
+#define CONFIG_SYS_BANK3_ROW		0
+#define CONFIG_SYS_BANK4_ROW		0
+#define CONFIG_SYS_BANK5_ROW		0
+#define CONFIG_SYS_BANK6_ROW		0
+#define CONFIG_SYS_BANK7_ROW		0
+
+/* Bit-field values for MCCR2.
+ */
+
+#define CONFIG_SYS_REFINT		0x2ec
+
+/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
+ */
+#define CONFIG_SYS_BSTOPRE		160
+
+/* Bit-field values for MCCR3.
+ */
+#define CONFIG_SYS_REFREC		2	/* Refresh to activate interval		*/
+#define CONFIG_SYS_RDLAT		0	/* Data latancy from read command	*/
+
+/* Bit-field values for MCCR4.
+ */
+#define CONFIG_SYS_PRETOACT		2	/* Precharge to activate interval	*/
+#define CONFIG_SYS_ACTTOPRE		5	/* Activate to Precharge interval	*/
+#define CONFIG_SYS_SDMODE_CAS_LAT	2	/* SDMODE CAS latancy			*/
+#define CONFIG_SYS_SDMODE_WRAP		0	/* SDMODE wrap type			*/
+#define CONFIG_SYS_SDMODE_BURSTLEN	2	/* SDMODE Burst length			*/
+#define CONFIG_SYS_ACTORW		2
+#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
+#define CONFIG_SYS_EXTROM		0
+#define CONFIG_SYS_REGDIMM		0
+
+/* Memory bank settings.
+ * Only bits 20-29 are actually used from these vales to set the
+ * start/end addresses. The upper two bits will always be 0, and the lower
+ * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
+ * address. Refer to the MPC8240 book.
+ */
+
+#define CONFIG_SYS_BANK0_START		0x00000000
+#define CONFIG_SYS_BANK0_END		(CONFIG_SYS_MAX_RAM_SIZE - 1)
+#define CONFIG_SYS_BANK0_ENABLE	1
+#define CONFIG_SYS_BANK1_START		0x3ff00000
+#define CONFIG_SYS_BANK1_END		0x3fffffff
+#define CONFIG_SYS_BANK1_ENABLE	0
+#define CONFIG_SYS_BANK2_START		0x3ff00000
+#define CONFIG_SYS_BANK2_END		0x3fffffff
+#define CONFIG_SYS_BANK2_ENABLE	0
+#define CONFIG_SYS_BANK3_START		0x3ff00000
+#define CONFIG_SYS_BANK3_END		0x3fffffff
+#define CONFIG_SYS_BANK3_ENABLE	0
+#define CONFIG_SYS_BANK4_START		0x3ff00000
+#define CONFIG_SYS_BANK4_END		0x3fffffff
+#define CONFIG_SYS_BANK4_ENABLE	0
+#define CONFIG_SYS_BANK5_START		0x3ff00000
+#define CONFIG_SYS_BANK5_END		0x3fffffff
+#define CONFIG_SYS_BANK5_ENABLE	0
+#define CONFIG_SYS_BANK6_START		0x3ff00000
+#define CONFIG_SYS_BANK6_END		0x3fffffff
+#define CONFIG_SYS_BANK6_ENABLE	0
+#define CONFIG_SYS_BANK7_START		0x3ff00000
+#define CONFIG_SYS_BANK7_END		0x3fffffff
+#define CONFIG_SYS_BANK7_ENABLE	0
+
+#define CONFIG_SYS_ODCR		0xff
+#define CONFIG_SYS_PGMAX		0x32	/* how long the 8240 retains the	*/
+					/* currently accessed page in memory	*/
+					/* see 8240 book for details		*/
+
+#define CONFIG_SYS_IBAT0L  (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U  (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT3L  (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U  (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_DBAT0L  CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U  CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L  CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U  CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L  CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U  CONFIG_SYS_IBAT3U
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* Max number of flash banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	39	/* Max number of sectors in one bank	*/
+#define INTEL_ID_28F160F3T	0x88F388F3	/*  16M = 1M x 16 top boot sector	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+	/* Warining: environment is not EMBEDDED in the ppcboot code.
+	 * It's stored in flash separately.
+	 */
+#define CONFIG_ENV_IS_IN_FLASH	    1
+
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x7F8000)
+#define CONFIG_ENV_SIZE		0x4000	/* Size of the Environment		*/
+#define CONFIG_ENV_OFFSET		0	/* starting right at the beginning	*/
+#define CONFIG_ENV_SECT_SIZE	0x8000 /* Size of the Environment Sector	*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	32
+#if defined(CONFIG_CMD_KGDB)
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*----------------------------------------------------------------------*/
+/* CPC45 Memory Map							*/
+/*----------------------------------------------------------------------*/
+#define SRAM_BASE	0x80000000	/* SRAM base address		*/
+#define SRAM_END	0x801FFFFF
+#define ST16552_A_BASE	0x80200000	/* ST16552 channel A		*/
+#define ST16552_B_BASE	0x80400000	/* ST16552 channel A		*/
+#define BCSR_BASE	0x80600000	/* board control / status registers */
+#define DISPLAY_BASE	0x80600040	/* DISPLAY base			*/
+#define PCMCIA_MEM_BASE 0x83000000	/* PCMCIA memory window base	*/
+#define PCMCIA_IO_BASE	0xFE000000	/* PCMCIA IO window base	*/
+
+#define	CONFIG_SYS_SRAM_BASE	SRAM_BASE
+#define	CONFIG_SYS_SRAM_SIZE	(SRAM_END - SRAM_BASE + 1)
+
+/*---------------------------------------------------------------------*/
+/* CPC45 Control/Status Registers				       */
+/*---------------------------------------------------------------------*/
+#define IRQ_ENA_1		*((volatile uchar*)(BCSR_BASE + 0x00))
+#define IRQ_STAT_1		*((volatile uchar*)(BCSR_BASE + 0x01))
+#define IRQ_ENA_2		*((volatile uchar*)(BCSR_BASE + 0x02))
+#define IRQ_STAT_2		*((volatile uchar*)(BCSR_BASE + 0x03))
+#define BOARD_CTRL		*((volatile uchar*)(BCSR_BASE + 0x04))
+#define BOARD_STAT		*((volatile uchar*)(BCSR_BASE + 0x05))
+#define WDG_START		*((volatile uchar*)(BCSR_BASE + 0x06))
+#define WDG_PRESTOP		*((volatile uchar*)(BCSR_BASE + 0x06))
+#define WDG_STOP		*((volatile uchar*)(BCSR_BASE + 0x06))
+#define BOARD_REV		*((volatile uchar*)(BCSR_BASE + 0x07))
+
+/* IRQ_ENA_1 bit definitions */
+#define I_ENA_1_IERA	0x80		/* INTA enable			*/
+#define I_ENA_1_IERB	0x40		/* INTB enable			*/
+#define I_ENA_1_IERC	0x20		/* INTC enable			*/
+#define I_ENA_1_IERD	0x10		/* INTD enable			*/
+
+/* IRQ_STAT_1 bit definitions */
+#define I_STAT_1_INTA	0x80		/* INTA status			*/
+#define I_STAT_1_INTB	0x40		/* INTB status			*/
+#define I_STAT_1_INTC	0x20		/* INTC status			*/
+#define I_STAT_1_INTD	0x10		/* INTD status			*/
+
+/* IRQ_ENA_2 bit definitions */
+#define I_ENA_2_IEAB	0x80		/* ABORT IRQ enable		*/
+#define I_ENA_2_IEK1	0x40		/* KEY1 IRQ enable		*/
+#define I_ENA_2_IEK2	0x20		/* KEY2 IRQ enable		*/
+#define I_ENA_2_IERT	0x10		/* RTC IRQ enable		*/
+#define I_ENA_2_IESM	0x08		/* LM81 IRQ enable		*/
+#define I_ENA_2_IEDG	0x04		/* DEGENERATING IRQ enable	*/
+#define I_ENA_2_IES2	0x02		/* ST16552/B IRQ enable		*/
+#define I_ENA_2_IES1	0x01		/* ST16552/A IRQ enable		*/
+
+/* IRQ_STAT_2 bit definitions */
+#define I_STAT_2_ABO	0x80		/* ABORT IRQ status		*/
+#define I_STAT_2_KY1	0x40		/* KEY1 IRQ status		*/
+#define I_STAT_2_KY2	0x20		/* KEY2 IRQ status		*/
+#define I_STAT_2_RTC	0x10		/* RTC IRQ status		*/
+#define I_STAT_2_SMN	0x08		/* LM81 IRQ status		*/
+#define I_STAT_2_DEG	0x04		/* DEGENERATING IRQ status	*/
+#define I_STAT_2_SIO2	0x02		/* ST16552/B IRQ status		*/
+#define I_STAT_2_SIO1	0x01		/* ST16552/A IRQ status		*/
+
+/* BOARD_CTRL bit definitions */
+#define USER_LEDS		2			/* 2 user LEDs	*/
+
+#if (USER_LEDS == 4)
+#define B_CTRL_WRSE		0x80
+#define B_CTRL_KRSE		0x40
+#define B_CTRL_FWRE		0x20		/* Flash write enable		*/
+#define B_CTRL_FWPT		0x10		/* Flash write protect		*/
+#define B_CTRL_LED3		0x08		/* LED 3 control		*/
+#define B_CTRL_LED2		0x04		/* LED 2 control		*/
+#define B_CTRL_LED1		0x02		/* LED 1 control		*/
+#define B_CTRL_LED0		0x01		/* LED 0 control		*/
+#else
+#define B_CTRL_WRSE		0x80
+#define B_CTRL_KRSE		0x40
+#define B_CTRL_FWRE_1		0x20		/* Flash write enable		*/
+#define B_CTRL_FWPT_1		0x10		/* Flash write protect		*/
+#define B_CTRL_LED1		0x08		/* LED 1 control		*/
+#define B_CTRL_LED0		0x04		/* LED 0 control		*/
+#define B_CTRL_FWRE_0		0x02		/* Flash write enable		*/
+#define B_CTRL_FWPT_0		0x01		/* Flash write protect		*/
+#endif
+
+/* BOARD_STAT bit definitions */
+#define B_STAT_WDGE		0x80
+#define B_STAT_WDGS		0x40
+#define B_STAT_WRST		0x20
+#define B_STAT_KRST		0x10
+#define B_STAT_CSW3		0x08		/* sitch bit 3 status		*/
+#define B_STAT_CSW2		0x04		/* sitch bit 2 status		*/
+#define B_STAT_CSW1		0x02		/* sitch bit 1 status		*/
+#define B_STAT_CSW0		0x01		/* sitch bit 0 status		*/
+
+/*---------------------------------------------------------------------*/
+/* Display addresses						       */
+/*---------------------------------------------------------------------*/
+#define DISP_UDC_RAM	(DISPLAY_BASE + 0x08)	/* UDC RAM	       */
+#define DISP_CHR_RAM	(DISPLAY_BASE + 0x18)	/* character Ram       */
+#define DISP_FLASH	(DISPLAY_BASE + 0x20)	/* Flash Ram	       */
+
+#define DISP_UDC_ADR	*((volatile uchar*)(DISPLAY_BASE + 0x00))	/* UDC Address Reg.    */
+#define DISP_CWORD	*((volatile uchar*)(DISPLAY_BASE + 0x10))	/* Control Word Reg.   */
+
+#define DISP_DIG0	*((volatile uchar*)(DISP_CHR_RAM + 0x00))	/* Digit 0 address     */
+#define DISP_DIG1	*((volatile uchar*)(DISP_CHR_RAM + 0x01))	/* Digit 0 address     */
+#define DISP_DIG2	*((volatile uchar*)(DISP_CHR_RAM + 0x02))	/* Digit 0 address     */
+#define DISP_DIG3	*((volatile uchar*)(DISP_CHR_RAM + 0x03))	/* Digit 0 address     */
+#define DISP_DIG4	*((volatile uchar*)(DISP_CHR_RAM + 0x04))	/* Digit 0 address     */
+#define DISP_DIG5	*((volatile uchar*)(DISP_CHR_RAM + 0x05))	/* Digit 0 address     */
+#define DISP_DIG6	*((volatile uchar*)(DISP_CHR_RAM + 0x06))	/* Digit 0 address     */
+#define DISP_DIG7	*((volatile uchar*)(DISP_CHR_RAM + 0x07))	/* Digit 0 address     */
+
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_PCI			/* include pci support			*/
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_SYS_EARLY_PCI_INIT
+#undef	CONFIG_PCI_PNP
+#undef	CONFIG_PCI_SCAN_SHOW
+
+
+#define CONFIG_EEPRO100
+#define CONFIG_SYS_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100	*/
+
+#define PCI_ENET0_IOADDR	0x82000000
+#define PCI_ENET0_MEMADDR	0x82000000
+#define PCI_PLX9030_IOADDR	0x82100000
+#define PCI_PLX9030_MEMADDR	0x82100000
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_I82365
+
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	PCMCIA_MEM_BASE
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	0x1000
+
+#define CONFIG_PCMCIA_SLOT_A
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_IDE_PREINIT	1	/* Use preinit IDE hook */
+#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for IDE not supported	*/
+#define	CONFIG_IDE_LED			/* LED   for IDE is  supported	*/
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
+
+#define CONFIG_SYS_ATA_DATA_OFFSET	CONFIG_SYS_PCMCIA_MEM_SIZE
+
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x400)
+
+#define CONFIG_DOS_PARTITION
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/CPCI2DP.h b/qemu/roms/u-boot/include/configs/CPCI2DP.h
new file mode 100644
index 000000000..05106cde9
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/CPCI2DP.h
@@ -0,0 +1,253 @@
+/*
+ * (C) Copyright 2005
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+
+#define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/
+
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+#undef	CONFIG_BOOTARGS
+#undef	CONFIG_BOOTCOMMAND
+
+#define CONFIG_PREBOOT                  /* enable preboot variable      */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_EEPROM
+
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+
+#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CONFIG_CONS_INDEX	2	/* Use UART1			*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CONFIG_SYS_BASE_BAUD	    691200
+
+/* The following table includes the supported baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CONFIG_LOOPW            1       /* enable loopw command         */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+#define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
+#define PCI_HOST_FORCE  1               /* configure as pci host        */
+#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_HOST	PCI_HOST_AUTO   /* select pci host function     */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
+					/* resource configuration       */
+
+#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
+
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
+
+#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x040b  /* PCI Device ID: CPCI-2DP      */
+#define CONFIG_SYS_PCI_CLASSCODE       0x0280	/* PCI Class Code: Network/Other*/
+
+#define CONFIG_SYS_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram               */
+#define CONFIG_SYS_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CONFIG_SYS_PCI_PTM2LA	0xef000000	/* point to internal regs + PB0/1 */
+#define CONFIG_SYS_PCI_PTM2MS  0xff000001      /* 16MB, enable                  */
+#define CONFIG_SYS_PCI_PTM2PCI 0x00000000      /* Host: use this pci address   */
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFFC0000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+
+#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CONFIG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
+#define CONFIG_ENV_SIZE		0x400	/* 1024 bytes may be used for env vars */
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last 4 bits of the address	*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+
+#define CONFIG_SYS_EEPROM_WREN         1
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+#define FLASH_BASE0_PRELIM	0xFFE00000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0               /* FLASH bank #1	*/
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash Bank 0) initialization					*/
+#define CONFIG_SYS_EBC_PB0AP		0x92015480
+#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 2 (PB0) initialization					*/
+#define CONFIG_SYS_EBC_PB2AP		0x03004580  /* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */
+#define CONFIG_SYS_EBC_PB2CR		0xEF018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 3 (PB1) initialization				*/
+#define CONFIG_SYS_EBC_PB3AP		0x03004580  /* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */
+#define CONFIG_SYS_EBC_PB3CR		0xEF118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+#define CONFIG_SYS_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
+
+#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000	/* Size of used area in RAM	       */
+#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * GPIO definitions
+ */
+#define CONFIG_SYS_EEPROM_WP		(0x80000000 >> 13)   /* GPIO13 */
+#define CONFIG_SYS_SELF_RST		(0x80000000 >> 14)   /* GPIO14 */
+#define CONFIG_SYS_PB_LED		(0x80000000 >> 16)   /* GPIO16 */
+#define CONFIG_SYS_INTA_FAKE		(0x80000000 >> 23)   /* GPIO23 */
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/CPCI405.h b/qemu/roms/u-boot/include/configs/CPCI405.h
new file mode 100644
index 000000000..34252d4d3
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/CPCI405.h
@@ -0,0 +1,320 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_CPCI405		1	/* ...on a CPCI405 board	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R	 1	/* call misc_init_r()		*/
+
+#define CONFIG_SYS_CLK_FREQ	33000000 /* external frequency to pll	*/
+
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+#undef	CONFIG_BOOTARGS
+#undef	CONFIG_BOOTCOMMAND
+
+#define CONFIG_PREBOOT                  /* enable preboot variable      */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_PPC4xx_EMAC
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
+
+#undef  CONFIG_HAS_ETH1
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_EEPROM
+
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_SUPPORT_VFAT
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+
+#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CONFIG_SYS_BASE_BAUD	    691200
+
+/* The following table includes the supported baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CONFIG_LOOPW            1       /* enable loopw command         */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
+#define PCI_HOST_FORCE  1               /* configure as pci host        */
+#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_HOST	PCI_HOST_AUTO   /* select pci host function     */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
+					/* resource configuration       */
+
+#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
+
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
+
+#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A    */
+#define CONFIG_SYS_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
+#define CONFIG_SYS_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram               */
+#define CONFIG_SYS_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CONFIG_SYS_PCI_PTM2LA  0xffc00000      /* point to flash               */
+#define CONFIG_SYS_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
+#define CONFIG_SYS_PCI_PTM2PCI (bd->bi_memsize) /* host use this pci address */
+
+#define CONFIG_PCI_4xx_PTM_OVERWRITE	1 /* overwrite PTMx settings by env */
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff
+ *-----------------------------------------------------------------------
+ */
+#undef	CONFIG_IDE_8xx_DIRECT		    /* no pcmcia interface required */
+#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
+#undef	CONFIG_IDE_RESET		/* no reset for ide supported	*/
+
+#define CONFIG_SYS_IDE_MAXBUS		1		/* max. 1 IDE busses	*/
+#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+
+#define CONFIG_SYS_ATA_BASE_ADDR	0xF0100000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(~(CONFIG_SYS_TEXT_BASE) + 1)
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
+#define CONFIG_SYS_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
+#define CONFIG_SYS_VXWORKS_MAC_PTR     (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
+
+#if 1 /* Use NVRAM for environment variables */
+/*-----------------------------------------------------------------------
+ * NVRAM organization
+ */
+#define CONFIG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
+#define CONFIG_ENV_SIZE		0x1000		/* Size of Environment vars	*/
+#define CONFIG_ENV_ADDR		\
+	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE)	/* Env	*/
+
+#else /* Use EEPROM for environment variables */
+
+#define CONFIG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
+#define CONFIG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
+#define CONFIG_ENV_SIZE            0x400   /* 1024 bytes may be used for env vars */
+				   /* total size of a CAT24WC08 is 1024 bytes */
+#endif
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC08) for environment
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last 4 bits of the address	*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0xFF800000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0xFFC00000	/* FLASH bank #1	*/
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash Bank 0) initialization					*/
+#define CONFIG_SYS_EBC_PB0AP		0x92015480
+#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (Flash Bank 1) initialization					*/
+#define CONFIG_SYS_EBC_PB1AP		0x92015480
+#define CONFIG_SYS_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 2 (CAN0, 1, 2, Codeswitch) initialization			*/
+#define CONFIG_SYS_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 3 (CompactFlash IDE) initialization				*/
+#define CONFIG_SYS_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 4 (NVRAM) initialization						*/
+#define CONFIG_SYS_EBC_PB4AP		0x01005280  /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1	*/
+#define CONFIG_SYS_EBC_PB4CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 5 (Quart) initialization						*/
+#define CONFIG_SYS_EBC_PB5AP		0x04005B80  /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
+#define CONFIG_SYS_EBC_PB5CR		0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit	*/
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ */
+
+/* FPGA program pin configuration */
+#define CONFIG_SYS_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
+#define CONFIG_SYS_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
+#define CONFIG_SYS_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
+#define CONFIG_SYS_FPGA_INIT		0x00400000  /* FPGA init pin (ppc input)     */
+#define CONFIG_SYS_FPGA_DONE		0x00800000  /* FPGA done pin (ppc input)     */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+#if 1 /* test-only */
+#define CONFIG_SYS_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
+
+#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
+#else
+#define CONFIG_SYS_INIT_RAM_ADDR	0x00df0000 /* inside of SDRAM			*/
+#endif
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000	/* Size of used area in RAM	       */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/CPCI4052.h b/qemu/roms/u-boot/include/configs/CPCI4052.h
new file mode 100644
index 000000000..bf8543980
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/CPCI4052.h
@@ -0,0 +1,381 @@
+/*
+ * (C) Copyright 2001-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_CPCI405		1	/* ...on a CPCI405 board	*/
+#define CONFIG_CPCI405_VER2	1	/* ...version 2			*/
+#undef  CONFIG_CPCI405_6U               /* enable this for 6U boards    */
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R	 1	/* call misc_init_r()		*/
+
+#define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/
+
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+#undef	CONFIG_BOOTARGS
+#undef	CONFIG_BOOTCOMMAND
+
+#define CONFIG_PREBOOT                  /* enable preboot variable      */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_PPC4xx_EMAC
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
+
+#undef  CONFIG_HAS_ETH1
+
+#define CONFIG_RTC_M48T35A	1		/* ST Electronics M48 timekeeper */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_EEPROM
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_SUPPORT_VFAT
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+
+#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CONFIG_SYS_BASE_BAUD	    691200
+
+/* The following table includes the supported baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CONFIG_CMDLINE_EDITING		/* add command line history	*/
+
+#define CONFIG_LOOPW            1       /* enable loopw command         */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+#define CONFIG_AUTOBOOT_KEYED	1
+#define CONFIG_AUTOBOOT_PROMPT	\
+	"Press SPACE to abort autoboot in %d seconds\n", bootdelay
+#undef CONFIG_AUTOBOOT_DELAY_STR
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
+#define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
+#define PCI_HOST_FORCE  1               /* configure as pci host        */
+#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_HOST	PCI_HOST_AUTO   /* select pci host function     */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
+					/* resource configuration       */
+
+#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
+
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
+
+#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A    */
+#define CONFIG_SYS_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
+#define CONFIG_SYS_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram               */
+#define CONFIG_SYS_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CONFIG_SYS_PCI_PTM2LA  0xffc00000      /* point to flash               */
+#define CONFIG_SYS_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
+#define CONFIG_SYS_PCI_PTM2PCI (bd->bi_memsize) /* host use this pci address */
+
+#define CONFIG_PCI_4xx_PTM_OVERWRITE	1 /* overwrite PTMx settings by env */
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff
+ *-----------------------------------------------------------------------
+ */
+#undef	CONFIG_IDE_8xx_DIRECT		    /* no pcmcia interface required */
+#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
+#define CONFIG_IDE_RESET	1	/* reset for ide supported	*/
+
+#define CONFIG_SYS_IDE_MAXBUS		1		/* max. 1 IDE busses	*/
+#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+
+#define CONFIG_SYS_ATA_BASE_ADDR	0xF0100000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFFC0000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+
+#define CONFIG_PRAM		0	/* use pram variable to overwrite */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#if 0 /* Use NVRAM for environment variables */
+/*-----------------------------------------------------------------------
+ * NVRAM organization
+ */
+#define CONFIG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
+#define CONFIG_ENV_SIZE		0x0ff8		/* Size of Environment vars	*/
+#define CONFIG_ENV_ADDR		\
+	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-(CONFIG_ENV_SIZE+8))	/* Env	*/
+
+#else /* Use EEPROM for environment variables */
+
+#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CONFIG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
+#define CONFIG_ENV_SIZE		0x800	/* 2048 bytes may be used for env vars*/
+				   /* total size of a CAT24WC16 is 2048 bytes */
+#endif
+
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
+#define CONFIG_SYS_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
+#define CONFIG_SYS_VXWORKS_MAC_PTR     (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last 4 bits of the address	*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0xFF800000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0xFFC00000	/* FLASH bank #1	*/
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash Bank 0) initialization					*/
+#define CONFIG_SYS_EBC_PB0AP		0x92015480
+#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (Flash Bank 1) initialization					*/
+#define CONFIG_SYS_EBC_PB1AP		0x92015480
+#define CONFIG_SYS_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 2 (CAN0, 1) initialization					*/
+#define CONFIG_SYS_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_LED_ADDR		0xF0000380
+
+/* Memory Bank 3 (CompactFlash IDE) initialization				*/
+#define CONFIG_SYS_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 4 (NVRAM/RTC) initialization					*/
+/*#define CONFIG_SYS_EBC_PB4AP		  0x01805280  / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1	   */
+#define CONFIG_SYS_EBC_PB4AP		0x01805680  /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1	*/
+#define CONFIG_SYS_EBC_PB4CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 5 (optional Quart) initialization				*/
+#define CONFIG_SYS_EBC_PB5AP		0x04005B80  /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
+#define CONFIG_SYS_EBC_PB5CR		0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 6 (FPGA internal) initialization					*/
+#define CONFIG_SYS_EBC_PB6AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB6CR		0xF041A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_FPGA_BASE_ADDR	0xF0400000
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ */
+/* FPGA internal regs */
+#define CONFIG_SYS_FPGA_MODE		0x00
+#define CONFIG_SYS_FPGA_STATUS		0x02
+#define CONFIG_SYS_FPGA_TS		0x04
+#define CONFIG_SYS_FPGA_TS_LOW		0x06
+#define CONFIG_SYS_FPGA_TS_CAP0	0x10
+#define CONFIG_SYS_FPGA_TS_CAP0_LOW	0x12
+#define CONFIG_SYS_FPGA_TS_CAP1	0x14
+#define CONFIG_SYS_FPGA_TS_CAP1_LOW	0x16
+#define CONFIG_SYS_FPGA_TS_CAP2	0x18
+#define CONFIG_SYS_FPGA_TS_CAP2_LOW	0x1a
+#define CONFIG_SYS_FPGA_TS_CAP3	0x1c
+#define CONFIG_SYS_FPGA_TS_CAP3_LOW	0x1e
+
+/* FPGA Mode Reg */
+#define CONFIG_SYS_FPGA_MODE_CF_RESET	    0x0001
+#define CONFIG_SYS_FPGA_MODE_DUART_RESET   0x0002
+#define CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT 0x0004     /* only set on CPCI-405 Ver 3 */
+#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
+#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR  0x1000
+#define CONFIG_SYS_FPGA_MODE_TS_CLEAR	    0x2000
+
+/* FPGA Status Reg */
+#define CONFIG_SYS_FPGA_STATUS_DIP0	0x0001
+#define CONFIG_SYS_FPGA_STATUS_DIP1	0x0002
+#define CONFIG_SYS_FPGA_STATUS_DIP2	0x0004
+#define CONFIG_SYS_FPGA_STATUS_FLASH	0x0008
+#define CONFIG_SYS_FPGA_STATUS_TS_IRQ	0x1000
+
+#define CONFIG_SYS_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
+#define CONFIG_SYS_FPGA_MAX_SIZE	32*1024	    /* 32kByte is enough for XC2S15  */
+
+/* FPGA program pin configuration */
+#define CONFIG_SYS_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
+#define CONFIG_SYS_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
+#define CONFIG_SYS_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
+#define CONFIG_SYS_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
+#define CONFIG_SYS_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+#define CONFIG_SYS_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
+
+#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000	/* Size of used area in RAM	       */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/CPCI405AB.h b/qemu/roms/u-boot/include/configs/CPCI405AB.h
new file mode 100644
index 000000000..7d58e9d13
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/CPCI405AB.h
@@ -0,0 +1,373 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_CPCI405		1	/* ...on a CPCI405 board	*/
+#define CONFIG_CPCI405_VER2	1	/* ...version 2			*/
+#define CONFIG_CPCI405AB	1	/* ...and special AB version	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R	 1	/* call misc_init_r()		*/
+
+#define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/
+
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+#undef	CONFIG_BOOTARGS
+#undef	CONFIG_BOOTCOMMAND
+
+#define CONFIG_PREBOOT                  /* enable preboot variable      */
+
+#undef	CONFIG_LOADS_ECHO		/* echo on for serial download	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_PPC4xx_EMAC
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
+
+#undef  CONFIG_HAS_ETH1
+
+#define CONFIG_RTC_M48T35A	1		/* ST Electronics M48 timekeeper */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_EEPROM
+
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_SUPPORT_VFAT
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+
+#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CONFIG_SYS_BASE_BAUD	    691200
+
+/* The following table includes the supported baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CONFIG_CMDLINE_EDITING		/* add command line history	*/
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+#define CONFIG_AUTOBOOT_KEYED	1
+#define CONFIG_AUTOBOOT_PROMPT	\
+	"Press SPACE to abort autoboot in %d seconds\n", bootdelay
+#undef CONFIG_AUTOBOOT_DELAY_STR
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
+#define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_HOST PCI_HOST_AUTO	/* select pci host function	*/
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+					/* resource configuration	*/
+
+#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
+
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
+
+#define CONFIG_PCI_BOOTDELAY	0	/* enable pci bootdelay variable*/
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A	*/
+#define CONFIG_SYS_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
+#define CONFIG_SYS_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram               */
+#define CONFIG_SYS_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CONFIG_SYS_PCI_PTM2LA	0xffc00000	/* point to flash		*/
+#define CONFIG_SYS_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
+#define CONFIG_SYS_PCI_PTM2PCI (bd->bi_memsize) /* host use this pci address */
+
+#define CONFIG_PCI_4xx_PTM_OVERWRITE	1 /* overwrite PTMx settings by env */
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff
+ *-----------------------------------------------------------------------
+ */
+#undef	CONFIG_IDE_8xx_DIRECT		    /* no pcmcia interface required */
+#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
+#define CONFIG_IDE_RESET	1	/* reset for ide supported	*/
+
+#define CONFIG_SYS_IDE_MAXBUS		1		/* max. 1 IDE busses	*/
+#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+
+#define CONFIG_SYS_ATA_BASE_ADDR	0xF0100000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFFC0000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
+
+#define CONFIG_PRAM		0	/* use pram variable to overwrite */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC32) for environment
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		100000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC32		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x01
+#define CONFIG_SYS_I2C_MULTI_EEPROMS   1       /* more than one eeprom used!   */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5	/* The Catalyst CAT24WC32 has	*/
+					/* 32 byte page write mode using*/
+					/* last 5 bits of the address	*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+
+/* Use EEPROM for environment variables */
+
+#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CONFIG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
+#define CONFIG_ENV_SIZE		0x800	/* 2048 bytes may be used for env vars*/
+				   /* total size of a CAT24WC32 is 4096 bytes */
+
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
+#define CONFIG_SYS_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
+#define CONFIG_SYS_VXWORKS_MAC_PTR     (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0xFF800000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0xFFC00000	/* FLASH bank #1	*/
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash Bank 0) initialization					*/
+#define CONFIG_SYS_EBC_PB0AP		0x92015480
+#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (Flash Bank 1) initialization					*/
+#define CONFIG_SYS_EBC_PB1AP		0x92015480
+#define CONFIG_SYS_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 2 (CAN0, 1) initialization					*/
+#define CONFIG_SYS_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_LED_ADDR		0xF0000380
+
+/* Memory Bank 3 (CompactFlash IDE) initialization				*/
+#define CONFIG_SYS_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 4 (NVRAM/RTC) initialization					*/
+/*#define CONFIG_SYS_EBC_PB4AP		  0x01805280  / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1	   */
+#define CONFIG_SYS_EBC_PB4AP		0x01805680  /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1	*/
+#define CONFIG_SYS_EBC_PB4CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 5 (optional Quart) initialization				*/
+#define CONFIG_SYS_EBC_PB5AP		0x04005B80  /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
+#define CONFIG_SYS_EBC_PB5CR		0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 6 (FPGA internal) initialization					*/
+#define CONFIG_SYS_EBC_PB6AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB6CR		0xF041A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_FPGA_BASE_ADDR	0xF0400000
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ */
+/* FPGA internal regs */
+#define CONFIG_SYS_FPGA_MODE		0x00
+#define CONFIG_SYS_FPGA_STATUS		0x02
+#define CONFIG_SYS_FPGA_TS		0x04
+#define CONFIG_SYS_FPGA_TS_LOW		0x06
+#define CONFIG_SYS_FPGA_TS_CAP0	0x10
+#define CONFIG_SYS_FPGA_TS_CAP0_LOW	0x12
+#define CONFIG_SYS_FPGA_TS_CAP1	0x14
+#define CONFIG_SYS_FPGA_TS_CAP1_LOW	0x16
+#define CONFIG_SYS_FPGA_TS_CAP2	0x18
+#define CONFIG_SYS_FPGA_TS_CAP2_LOW	0x1a
+#define CONFIG_SYS_FPGA_TS_CAP3	0x1c
+#define CONFIG_SYS_FPGA_TS_CAP3_LOW	0x1e
+
+/* FPGA Mode Reg */
+#define CONFIG_SYS_FPGA_MODE_CF_RESET	    0x0001
+#define CONFIG_SYS_FPGA_MODE_DUART_RESET   0x0002
+#define CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT 0x0004     /* only set on CPCI-405 Ver 3 */
+#define CONFIG_SYS_FPGA_MODE_1WIRE_DIR     0x0100     /* dir=1 -> output */
+#define CONFIG_SYS_FPGA_MODE_SIM_OK_DIR    0x0200
+#define CONFIG_SYS_FPGA_MODE_TESTRIG_FAIL_DIR 0x0400
+#define CONFIG_SYS_FPGA_MODE_1WIRE         0x1000
+#define CONFIG_SYS_FPGA_MODE_SIM_OK        0x2000     /* wired-or net from all devices */
+#define CONFIG_SYS_FPGA_MODE_TESTRIG_FAIL  0x4000
+
+/* FPGA Status Reg */
+#define CONFIG_SYS_FPGA_STATUS_DIP0    0x0001
+#define CONFIG_SYS_FPGA_STATUS_DIP1    0x0002
+#define CONFIG_SYS_FPGA_STATUS_DIP2    0x0004
+#define CONFIG_SYS_FPGA_STATUS_FLASH   0x0008
+#define CONFIG_SYS_FPGA_STATUS_1WIRE   0x1000
+#define CONFIG_SYS_FPGA_STATUS_SIM_OK  0x2000
+
+#define CONFIG_SYS_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
+#define CONFIG_SYS_FPGA_MAX_SIZE	128*1024    /* 128kByte is enough for XC2S30 */
+
+/* FPGA program pin configuration */
+#define CONFIG_SYS_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
+#define CONFIG_SYS_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
+#define CONFIG_SYS_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
+#define CONFIG_SYS_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
+#define CONFIG_SYS_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+#define CONFIG_SYS_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
+
+#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000	/* Size of used area in RAM	       */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/CPCI405DT.h b/qemu/roms/u-boot/include/configs/CPCI405DT.h
new file mode 100644
index 000000000..c2598a302
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/CPCI405DT.h
@@ -0,0 +1,376 @@
+/*
+ * (C) Copyright 2001-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_CPCI405		1	/* ...on a CPCI405 board	*/
+#define CONFIG_CPCI405_VER2	1	/* ...version 2			*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R	 1	/* call misc_init_r()		*/
+
+#define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/
+
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+#undef	CONFIG_BOOTARGS
+#undef	CONFIG_BOOTCOMMAND
+
+#define CONFIG_PREBOOT                  /* enable preboot variable      */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_PPC4xx_EMAC
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
+
+#undef  CONFIG_HAS_ETH1
+
+#define CONFIG_RTC_M48T35A	1		/* ST Electronics M48 timekeeper */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_EEPROM
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_SUPPORT_VFAT
+
+#undef  CONFIG_AUTO_UPDATE              /* autoupdate via compactflash  */
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+
+#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CONFIG_SYS_BASE_BAUD	    691200
+
+/* The following table includes the supported baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CONFIG_LOOPW            1       /* enable loopw command         */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+/* Only interrupt boot if special string is typed */
+#define CONFIG_AUTOBOOT_KEYED	1
+#define CONFIG_AUTOBOOT_PROMPT 	\
+	"Autobooting in %d seconds\n", bootdelay
+#undef  CONFIG_AUTOBOOT_DELAY_STR
+#undef  CONFIG_AUTOBOOT_STOP_STR        /* defined via environment var  */
+#define CONFIG_AUTOBOOT_STOP_STR2 "esdesd" /* esd special for esd access*/
+
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+#define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
+#define PCI_HOST_FORCE  1               /* configure as pci host        */
+#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_HOST	PCI_HOST_AUTO   /* select pci host function     */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
+					/* resource configuration       */
+
+#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
+
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
+
+#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A    */
+#define CONFIG_SYS_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
+#define CONFIG_SYS_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram               */
+#define CONFIG_SYS_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CONFIG_SYS_PCI_PTM2LA  0xffc00000      /* point to flash               */
+#define CONFIG_SYS_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
+#define CONFIG_SYS_PCI_PTM2PCI (bd->bi_memsize) /* host use this pci address */
+
+#define CONFIG_PCI_4xx_PTM_OVERWRITE	1 /* overwrite PTMx settings by env */
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff
+ *-----------------------------------------------------------------------
+ */
+#undef	CONFIG_IDE_8xx_DIRECT		    /* no pcmcia interface required */
+#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
+#define CONFIG_IDE_RESET	1	/* reset for ide supported	*/
+
+#define CONFIG_SYS_IDE_MAXBUS		1		/* max. 1 IDE busses	*/
+#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+
+#define CONFIG_SYS_ATA_BASE_ADDR	0xF0100000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFFC0000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#if 0 /* Use NVRAM for environment variables */
+/*-----------------------------------------------------------------------
+ * NVRAM organization
+ */
+#define CONFIG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
+#define CONFIG_ENV_SIZE		0x0ff8		/* Size of Environment vars	*/
+#define CONFIG_ENV_ADDR		\
+	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-(CONFIG_ENV_SIZE+8))	/* Env	*/
+
+#else /* Use EEPROM for environment variables */
+
+#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CONFIG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
+#define CONFIG_ENV_SIZE		0x800	/* 2048 bytes may be used for env vars*/
+				   /* total size of a CAT24WC16 is 2048 bytes */
+#endif
+
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
+#define CONFIG_SYS_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
+#define CONFIG_SYS_VXWORKS_MAC_PTR     (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last 4 bits of the address	*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0xFF800000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0xFFC00000	/* FLASH bank #1	*/
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash Bank 0) initialization					*/
+#define CONFIG_SYS_EBC_PB0AP		0x92015480
+#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (Flash Bank 1) initialization					*/
+#define CONFIG_SYS_EBC_PB1AP		0x92015480
+#define CONFIG_SYS_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 2 (CAN0, 1) initialization					*/
+#define CONFIG_SYS_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+#define CONFIG_SYS_LED_ADDR		0xF0000380
+
+/* Memory Bank 3 (CompactFlash IDE) initialization				*/
+#define CONFIG_SYS_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 4 (NVRAM/RTC) initialization					*/
+/*#define CONFIG_SYS_EBC_PB4AP		  0x01805280  / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1	   */
+#define CONFIG_SYS_EBC_PB4AP		0x01805680  /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1	*/
+#define CONFIG_SYS_EBC_PB4CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 5 (optional Quart) initialization				*/
+#define CONFIG_SYS_EBC_PB5AP		0x04005B80  /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
+#define CONFIG_SYS_EBC_PB5CR		0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 6 (FPGA internal) initialization					*/
+#define CONFIG_SYS_EBC_PB6AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB6CR		0xF041A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_FPGA_BASE_ADDR	0xF0400000
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ */
+/* FPGA internal regs */
+#define CONFIG_SYS_FPGA_MODE		0x00
+#define CONFIG_SYS_FPGA_STATUS		0x02
+#define CONFIG_SYS_FPGA_TS		0x04
+#define CONFIG_SYS_FPGA_TS_LOW		0x06
+#define CONFIG_SYS_FPGA_TS_CAP0	0x10
+#define CONFIG_SYS_FPGA_TS_CAP0_LOW	0x12
+#define CONFIG_SYS_FPGA_TS_CAP1	0x14
+#define CONFIG_SYS_FPGA_TS_CAP1_LOW	0x16
+#define CONFIG_SYS_FPGA_TS_CAP2	0x18
+#define CONFIG_SYS_FPGA_TS_CAP2_LOW	0x1a
+#define CONFIG_SYS_FPGA_TS_CAP3	0x1c
+#define CONFIG_SYS_FPGA_TS_CAP3_LOW	0x1e
+
+/* FPGA Mode Reg */
+#define CONFIG_SYS_FPGA_MODE_CF_RESET	    0x0001
+#define CONFIG_SYS_FPGA_MODE_DUART_RESET   0x0002
+#define CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT 0x0004     /* only set on CPCI-405 Ver 3 */
+#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
+#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR  0x1000
+#define CONFIG_SYS_FPGA_MODE_TS_CLEAR	    0x2000
+
+/* FPGA Status Reg */
+#define CONFIG_SYS_FPGA_STATUS_DIP0	0x0001
+#define CONFIG_SYS_FPGA_STATUS_DIP1	0x0002
+#define CONFIG_SYS_FPGA_STATUS_DIP2	0x0004
+#define CONFIG_SYS_FPGA_STATUS_FLASH	0x0008
+#define CONFIG_SYS_FPGA_STATUS_TS_IRQ	0x1000
+
+#define CONFIG_SYS_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
+#define CONFIG_SYS_FPGA_MAX_SIZE	32*1024	    /* 32kByte is enough for XC2S15  */
+
+/* FPGA program pin configuration */
+#define CONFIG_SYS_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
+#define CONFIG_SYS_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
+#define CONFIG_SYS_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
+#define CONFIG_SYS_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
+#define CONFIG_SYS_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+#define CONFIG_SYS_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
+
+#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000	/* Size of used area in RAM	       */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/CPCI750.h b/qemu/roms/u-boot/include/configs/CPCI750.h
new file mode 100644
index 000000000..304a12bea
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/CPCI750.h
@@ -0,0 +1,609 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+/*************************************************************************
+ * (c) 2004 esd gmbh Hannover
+ *
+ *
+ * from db64360.h file
+ * by Reinhard Arlt reinhard.arlt@esd-electronics.com
+ *
+  ************************************************************************/
+
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* This define must be before the core.h include */
+#define CONFIG_CPCI750		1	/* this is an CPCI750 board	*/
+
+#ifndef __ASSEMBLY__
+#include <../board/Marvell/include/core.h>
+#endif
+/*-----------------------------------------------------*/
+
+#include "../board/esd/cpci750/local.h"
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_750FX			/* we have a 750FX (override local.h) */
+
+#define CONFIG_CPCI750		1	/* this is an CPCI750 board	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xfff00000
+
+#define CONFIG_BAUDRATE		9600	/* console baudrate = 9600	*/
+
+#define CONFIG_MV64360_ECC		/* enable ECC support */
+
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
+/* which initialization functions to call for this board */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_BOARD_PRE_INIT
+#define CONFIG_BOARD_EARLY_INIT_F 1
+
+#define CONFIG_SYS_BOARD_NAME		"CPCI750"
+#define CONFIG_IDENT_STRING	"Marvell 64360 + IBM750FX"
+
+/*#define CONFIG_SYS_HUSH_PARSER*/
+#define CONFIG_SYS_HUSH_PARSER
+
+
+#define CONFIG_CMDLINE_EDITING		/* add command line history	*/
+#define CONFIG_AUTO_COMPLETE		/* add autocompletion support	*/
+
+/* Define which ETH port will be used for connecting the network */
+#define CONFIG_SYS_ETH_PORT		ETH_0
+
+/*
+ * The following defines let you select what serial you want to use
+ * for your console driver.
+ *
+ * what to do:
+ * to use the DUART, undef CONFIG_MPSC.	 If you have hacked a serial
+ * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1
+ * to 0 below.
+ *
+ * to use the MPSC, #define CONFIG_MPSC.  If you have wired up another
+ * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
+ */
+#define CONFIG_MPSC
+#define CONFIG_MPSC_PORT	0
+
+/* to change the default ethernet port, use this define (options: 0, 1, 2) */
+#define MV_ETH_DEVS		1
+#define CONFIG_ETHER_PORT	0
+
+#undef CONFIG_ETHER_PORT_MII	/* use RMII */
+
+#define CONFIG_BOOTDELAY	5	/* autoboot disabled		*/
+
+#define CONFIG_RTC_M48T35A	1	/* ST Electronics M48 timekeeper */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+
+#undef	CONFIG_BOOTARGS
+
+/* -----------------------------------------------------------------------------
+ * New bootcommands for Marvell CPCI750 c 2002 Ingo Assmus
+ */
+
+#define CONFIG_IPADDR		"192.168.0.185"
+
+#define CONFIG_SERIAL		"AA000001"
+#define CONFIG_SERVERIP		"10.0.0.79"
+#define CONFIG_ROOTPATH		"/export/nfs_cpci750/%s"
+
+#define CONFIG_TESTDRAMDATA	y
+#define CONFIG_TESTDRAMADDRESS	n
+#define CONFIG_TESETDRAMWALK	n
+
+/* ----------------------------------------------------------------------------- */
+
+
+#define CONFIG_LOADS_ECHO	0	/* echo off for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE		/* allow baudrate changes	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+#undef	CONFIG_ALTIVEC			/* undef to disable		*/
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+
+
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_USE_CPCIDVI
+
+#ifdef	CONFIG_USE_CPCIDVI
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_CT69000
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_I8042_KBD
+#define CONFIG_SYS_ISA_IO 0
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_SPEED	80000		/* I2C speed default */
+
+#define CONFIG_PRAM 0
+
+#define CONFIG_SYS_GT_DUAL_CPU			/* also for JTAG even with one cpu */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+/*#define CONFIG_SYS_MEMTEST_START	0x00400000*/	/* memtest works on	*/
+/*#define CONFIG_SYS_MEMTEST_END		0x00C00000*/	/* 4 ... 12 MB in DRAM	*/
+/*#define CONFIG_SYS_MEMTEST_END		0x07c00000*/	/* 4 ... 124 MB in DRAM */
+
+/*
+#define CONFIG_SYS_DRAM_TEST
+ * DRAM tests
+ *   CONFIG_SYS_DRAM_TEST - enables the following tests.
+ *
+ *   CONFIG_SYS_DRAM_TEST_DATA - Enables test for shorted or open data lines
+ *			  Environment variable 'test_dram_data' must be
+ *			  set to 'y'.
+ *   CONFIG_SYS_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
+ *			  addressable. Environment variable
+ *			  'test_dram_address' must be set to 'y'.
+ *   CONFIG_SYS_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
+ *			  This test takes about 6 minutes to test 64 MB.
+ *			  Environment variable 'test_dram_walk' must be
+ *			  set to 'y'.
+ */
+#define CONFIG_SYS_DRAM_TEST
+#if defined(CONFIG_SYS_DRAM_TEST)
+#define CONFIG_SYS_MEMTEST_START		0x00400000	/* memtest works on	*/
+/*#define CONFIG_SYS_MEMTEST_END		0x00C00000*/	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_END		0x07c00000	/* 4 ... 124 MB in DRAM */
+#define CONFIG_SYS_DRAM_TEST_DATA
+#define CONFIG_SYS_DRAM_TEST_ADDRESS
+#define CONFIG_SYS_DRAM_TEST_WALK
+#endif /* CONFIG_SYS_DRAM_TEST */
+
+#define CONFIG_DISPLAY_MEMMAP		/* at the end of the bootprocess show the memory map */
+#undef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT	/* show SPD content during boot */
+
+#define CONFIG_SYS_LOAD_ADDR		0x00300000	/* default load address */
+
+#define CONFIG_SYS_BUS_CLK		133000000	/* 133 MHz (CPU = 5*Bus = 666MHz)		*/
+
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#define CONFIG_SYS_TCLK		133000000
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area
+ */
+
+ /*
+ * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS
+ * To an unused memory region. The stack will remain in cache until RAM
+ * is initialized
+*/
+#undef	  CONFIG_SYS_INIT_RAM_LOCK
+/* #define CONFIG_SYS_INIT_RAM_ADDR	0x40000000*/ /* unused memory region */
+/* #define CONFIG_SYS_INIT_RAM_ADDR	0xfba00000*/ /* unused memory region */
+#define CONFIG_SYS_INIT_RAM_ADDR	0xf1080000 /* unused memory region */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+#define RELOCATE_INTERNAL_RAM_ADDR
+#ifdef RELOCATE_INTERNAL_RAM_ADDR
+/*#define CONFIG_SYS_INTERNAL_RAM_ADDR 0xfba00000*/
+#define CONFIG_SYS_INTERNAL_RAM_ADDR	0xf1080000
+#endif
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+/* Dummies for BAT 4-7 */
+#define CONFIG_SYS_SDRAM1_BASE		0x10000000	/* each 256 MByte */
+#define CONFIG_SYS_SDRAM2_BASE		0x20000000
+#define CONFIG_SYS_SDRAM3_BASE		0x30000000
+#define CONFIG_SYS_SDRAM4_BASE		0x40000000
+#define CONFIG_SYS_RESET_ADDRESS	0xfff00100
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MONITOR_BASE	0xfff00000
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 256 kB for malloc */
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI		1	   /* Flash is CFI conformant		*/
+#define CONFIG_SYS_FLASH_PROTECTION	1	   /* use hardware protection		*/
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	   /* use buffered writes (20x faster)	*/
+#define CONFIG_SYS_FLASH_BASE		0xfc000000 /* start of flash banks		*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	4	   /* max number of memory banks	*/
+#define CONFIG_SYS_FLASH_INCREMENT	0x01000000 /* size of  flash bank		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	128	   /* max number of sectors on one chip */
+#define CONFIG_SYS_FLASH_BANKS_LIST  { CONFIG_SYS_FLASH_BASE,				   \
+				CONFIG_SYS_FLASH_BASE + 1*CONFIG_SYS_FLASH_INCREMENT,	   \
+				CONFIG_SYS_FLASH_BASE + 2*CONFIG_SYS_FLASH_INCREMENT,	   \
+				CONFIG_SYS_FLASH_BASE + 3*CONFIG_SYS_FLASH_INCREMENT }
+#define CONFIG_SYS_FLASH_EMPTY_INFO	1	   /* show if bank is empty		*/
+
+/* areas to map different things with the GT in physical space */
+#define CONFIG_SYS_DRAM_BANKS		4
+
+/* What to put in the bats. */
+#define CONFIG_SYS_MISC_REGION_BASE	0xf0000000
+
+/* Peripheral Device section */
+
+/*******************************************************/
+/* We have on the cpci750 Board :		       */
+/* GT-Chipset Register Area			       */
+/* GT-Chipset internal SRAM 256k		       */
+/* SRAM on external device module		       */
+/* Real time clock on external device module	       */
+/* dobble UART on external device module	       */
+/* Data flash on external device module		       */
+/* Boot flash on external device module		       */
+/*******************************************************/
+#define CONFIG_SYS_DFL_GT_REGS		0x14000000				/* boot time GT_REGS */
+#define	 CONFIG_SYS_CPCI750_RESET_ADDR 0x14000000				/* After power on Reset the CPCI750 is here */
+
+#undef	MARVEL_STANDARD_CFG
+#ifndef		MARVEL_STANDARD_CFG
+/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+#define CONFIG_SYS_GT_REGS		0xf1000000				/* GT Registers will be mapped here */
+/*#define CONFIG_SYS_DEV_BASE		0xfc000000*/				/* GT Devices CS start here */
+#define CONFIG_SYS_INT_SRAM_BASE	0xf1080000				/* GT offers 256k internal fast SRAM */
+
+#define CONFIG_SYS_BOOT_SPACE		0xff000000				/* BOOT_CS0 flash 0    */
+#define CONFIG_SYS_DEV0_SPACE		0xfc000000				/* DEV_CS0 flash 1     */
+#define CONFIG_SYS_DEV1_SPACE		0xfd000000				/* DEV_CS1 flash 2     */
+#define CONFIG_SYS_DEV2_SPACE		0xfe000000				/* DEV_CS2 flash 3     */
+#define CONFIG_SYS_DEV3_SPACE		0xf0000000				/* DEV_CS3 nvram/can   */
+
+#define CONFIG_SYS_BOOT_SIZE		_16M					/* cpci750 flash 0     */
+#define CONFIG_SYS_DEV0_SIZE		_16M					/* cpci750 flash 1     */
+#define CONFIG_SYS_DEV1_SIZE		_16M					/* cpci750 flash 2     */
+#define CONFIG_SYS_DEV2_SIZE		_16M					/* cpci750 flash 3     */
+#define CONFIG_SYS_DEV3_SIZE		_16M					/* cpci750 nvram/can   */
+
+/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+#endif
+
+/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */
+#define CONFIG_SYS_DEV0_PAR		0x8FDFFFFF				/* 16 bit flash */
+#define CONFIG_SYS_DEV1_PAR		0x8FDFFFFF				/* 16 bit flash */
+#define CONFIG_SYS_DEV2_PAR		0x8FDFFFFF				/* 16 bit flash */
+#define CONFIG_SYS_DEV3_PAR		0x8FCFFFFF				/* nvram/can	*/
+#define CONFIG_SYS_BOOT_PAR		0x8FDFFFFF				/* 16 bit flash */
+
+	/*   c	  4    a      8	    2	  4    1      c		*/
+	/* 33 22|2222|22 22|111 1|11 11|1 1  |	  |		*/
+	/* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210	*/
+	/* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100	*/
+	/*  3| 0|.... ..| 2| 4 |  0 |  4 |  8  |  3  | 4	*/
+
+
+/* MPP Control MV64360 Appendix P P. 632*/
+#define CONFIG_SYS_MPP_CONTROL_0	0x00002222	/*				     */
+#define CONFIG_SYS_MPP_CONTROL_1	0x11110000	/*				     */
+#define CONFIG_SYS_MPP_CONTROL_2	0x11111111	/*				     */
+#define CONFIG_SYS_MPP_CONTROL_3	0x00001111	/*				     */
+/* #define CONFIG_SYS_SERIAL_PORT_MUX	0x00000102*/	/*				     */
+
+
+#define CONFIG_SYS_GPP_LEVEL_CONTROL	0xffffffff	/* 1111 1111 1111 1111 1111 1111 1111 1111*/
+
+/* setup new config_value for MV64360 DDR-RAM To_do !! */
+/*# define CONFIG_SYS_SDRAM_CONFIG	0xd8e18200*/	/* 0x448 */
+/*# define CONFIG_SYS_SDRAM_CONFIG	0xd8e14400*/	/* 0x1400 */
+				/* GB has high prio.
+				   idma has low prio
+				   MPSC has low prio
+				   pci has low prio 1 and 2
+				   cpu has high prio
+				   Data DQS pins == eight (DQS[7:0] foe x8 and x16 devices
+				   ECC disable
+				   non registered DRAM */
+				/* 31:26   25:22  21:20 19 18 17 16 */
+				/* 100001 0000	 010   0   0   0  0 */
+				/* refresh_count=0x400
+				   phisical interleaving disable
+				   virtual interleaving enable */
+				/* 15 14 13:0 */
+				/* 0  1	 0x400 */
+# define CONFIG_SYS_SDRAM_CONFIG	0x58200400	/* 0x1400  copied from Dink32 bzw. VxWorks*/
+
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+
+#define PCI_HOST_ADAPTER 0		/* configure ar pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST PCI_HOST_FORCE	/* select pci host function	*/
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+#define CONFIG_PCI_SCAN_SHOW		/* show devices on bus		*/
+
+/* PCI MEMORY MAP section */
+#define CONFIG_SYS_PCI0_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI0_MEM_SIZE	_128M
+#define CONFIG_SYS_PCI1_MEM_BASE	0x88000000
+#define CONFIG_SYS_PCI1_MEM_SIZE	_128M
+
+#define CONFIG_SYS_PCI0_0_MEM_SPACE	(CONFIG_SYS_PCI0_MEM_BASE)
+#define CONFIG_SYS_PCI1_0_MEM_SPACE	(CONFIG_SYS_PCI1_MEM_BASE)
+
+/* PCI I/O MAP section */
+#define CONFIG_SYS_PCI0_IO_BASE	0xfa000000
+#define CONFIG_SYS_PCI0_IO_SIZE	_16M
+#define CONFIG_SYS_PCI1_IO_BASE	0xfb000000
+#define CONFIG_SYS_PCI1_IO_SIZE	_16M
+
+#define CONFIG_SYS_PCI0_IO_SPACE	(CONFIG_SYS_PCI0_IO_BASE)
+#define CONFIG_SYS_PCI0_IO_SPACE_PCI	0x00000000
+#define CONFIG_SYS_PCI1_IO_SPACE	(CONFIG_SYS_PCI1_IO_BASE)
+#define CONFIG_SYS_PCI1_IO_SPACE_PCI	0x00000000
+
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS (CONFIG_SYS_PCI0_IO_BASE)
+
+#if defined (CONFIG_750CX)
+#define CONFIG_SYS_PCI_IDSEL 0x0
+#else
+#define CONFIG_SYS_PCI_IDSEL 0x30
+#endif
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff
+ *-----------------------------------------------------------------------
+ */
+#undef	CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
+#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
+#define CONFIG_IDE_RESET		/* no reset for ide supported	*/
+#define CONFIG_IDE_PREINIT		/* check for units		*/
+
+#define CONFIG_SYS_IDE_MAXBUS		2		/* max. 1 IDE busses	*/
+#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*2) /* max. 1 drives per IDE bus */
+
+#define CONFIG_SYS_ATA_BASE_ADDR	0
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0
+#define CONFIG_SYS_ATA_IDE1_OFFSET	0
+
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
+#ifndef __ASSEMBLY__
+int ata_device(int dev);
+#endif
+#define ATA_DEVICE(dev)                 ata_device(dev)
+#define CONFIG_ATAPI                    1
+
+/*----------------------------------------------------------------------
+ * Initial BAT mappings
+ */
+
+/* NOTES:
+ * 1) GUARDED and WRITE_THRU not allowed in IBATS
+ * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
+ */
+
+/* SDRAM */
+#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
+
+/* init ram */
+#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
+
+/* PCI0, PCI1 in one BAT */
+#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
+#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
+#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* GT regs, bootrom, all the devices, PCI I/O */
+#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
+#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
+#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
+
+/*
+ * 750FX IBAT and DBAT pairs (To_do: define regins for I(D)BAT4 - I(D)BAT7)
+ * IBAT4 and DBAT4
+ * FIXME: ingo disable BATs for Linux Kernel
+ */
+/* #undef SETUP_HIGH_BATS_FX750	*/	/* don't initialize BATS 4-7 */
+#define SETUP_HIGH_BATS_FX750		/* initialize BATS 4-7 */
+
+#ifdef SETUP_HIGH_BATS_FX750
+#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
+
+/* IBAT5 and DBAT5 */
+#define CONFIG_SYS_IBAT5L (CONFIG_SYS_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT5U (CONFIG_SYS_SDRAM2_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT5L (CONFIG_SYS_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
+
+/* IBAT6 and DBAT6 */
+#define CONFIG_SYS_IBAT6L (CONFIG_SYS_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT6U (CONFIG_SYS_SDRAM3_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT6L (CONFIG_SYS_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
+
+/* IBAT7 and DBAT7 */
+#define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
+
+#else		/* set em out of range for Linux !!!!!!!!!!! */
+#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT4L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
+
+/* IBAT5 and DBAT5 */
+#define CONFIG_SYS_IBAT5L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT5U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT5L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT4U
+
+/* IBAT6 and DBAT6 */
+#define CONFIG_SYS_IBAT6L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT6U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT6L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT4U
+
+/* IBAT7 and DBAT7 */
+#define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT4U
+
+#endif
+/* FIXME: ingo end: disable BATs for Linux Kernel */
+
+/* I2C addresses for the two DIMM SPD chips */
+#define DIMM0_I2C_ADDR	0x51
+#define DIMM1_I2C_ADDR	0x52
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8<<20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_BOOT_FLASH_WIDTH	2	/* 16 bit */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
+#define CONFIG_SYS_FLASH_LOCK_TOUT	500	/* Timeout for Flash Lock (in ms) */
+
+#if 0
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SIZE		0x1000	/* Total Size of Environment Sector */
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#define CONFIG_ENV_ADDR		0xFFF78000 /* Marvell 8-Bit Bootflash last sector */
+/* #define CONFIG_ENV_ADDR	   (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) */
+#endif
+
+#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x050
+#define CONFIG_ENV_OFFSET		0x200	/* environment starts at the beginning of the EEPROM */
+#define CONFIG_ENV_SIZE		0x600	/* 2048 bytes may be used for env vars*/
+
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xf0000000		/* NVRAM base address	*/
+#define CONFIG_SYS_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
+#define CONFIG_SYS_VXWORKS_MAC_PTR	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-0x40)
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For all MPC74xx CPUs		 */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * L2CR setup -- make sure this is right for your board!
+ * look in include/mpc74xx.h for the defines used here
+ */
+
+/*#define CONFIG_SYS_L2*/
+#undef CONFIG_SYS_L2
+
+/*    #ifdef CONFIG_750CX*/
+#if defined (CONFIG_750CX) || defined (CONFIG_750FX)
+#define L2_INIT 0
+#else
+#define L2_INIT		(L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
+			L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
+#endif
+
+#define L2_ENABLE	(L2_INIT | L2CR_L2E)
+
+#define CONFIG_SYS_BOARD_ASM_INIT	1
+
+#define CPCI750_SLAVE_TEST	(((in8(0xf0300000) & 0x80) == 0) ? 0 : 1)
+#define CPCI750_ECC_TEST	(((in8(0xf0300000) & 0x02) == 0) ? 1 : 0)
+#define CONFIG_SYS_PLD_VER	0xf0e00000
+
+#define CONFIG_OF_LIBFDT 1
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/CPCIISER4.h b/qemu/roms/u-boot/include/configs/CPCIISER4.h
new file mode 100644
index 000000000..25365f747
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/CPCIISER4.h
@@ -0,0 +1,237 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_CPCIISER4	1	/* ...on a CPCIISER4 board	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+
+#define CONFIG_SYS_CLK_FREQ	25000000 /* external frequency to pll	*/
+
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND	"bootm fff00000"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_PPC4xx_EMAC
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EEPROM
+
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+
+#define CONFIG_SYS_EXT_SERIAL_CLOCK	1843200	 /* use external serial clock	*/
+
+/* The following table includes the supported baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0		/* configure ar pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_HOST PCI_HOST_AUTO	/* select pci host function	*/
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+					/* resource configuration	*/
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0404	/* PCI Device ID: CPCI-ISER4	*/
+#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CONFIG_SYS_PCI_PTM1MS	0xff000001	/* 16MB, enable hard-wired to 1 */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CONFIG_SYS_PCI_PTM2LA	0xffe00000	/* point to flash		*/
+#define CONFIG_SYS_PCI_PTM2MS	0xffe00001	/* 2MB, enable			*/
+#define CONFIG_SYS_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFFC0000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC08) for environment
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last 4 bits of the address	*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+
+#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CONFIG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
+#define CONFIG_ENV_SIZE		0x300	/* 768 bytes may be used for env vars */
+				   /* total size of a CAT24WC08 is 1024 bytes */
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0xFFF00000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0		/* FLASH bank #1	*/
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash Bank 0) initialization					*/
+#define CONFIG_SYS_EBC_PB0AP		0x92015480
+#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (Uart 8bit) initialization					*/
+#define CONFIG_SYS_EBC_PB1AP		0x01000480  /* TWT=2,TH=2,no Ready,BEM=0,SOR=1	*/
+#define CONFIG_SYS_EBC_PB1CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 2 (Uart 32bit) initialization					*/
+#define CONFIG_SYS_EBC_PB2AP		0x000004c0  /* no Ready, BEM=1			*/
+#define CONFIG_SYS_EBC_PB2CR		0xF011C000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=32bit */
+
+/* Memory Bank 3 (FPGA Reset) initialization					*/
+#define CONFIG_SYS_EBC_PB3AP		0x010004C0  /* no Ready, BEM=1			*/
+#define CONFIG_SYS_EBC_PB3CR		0xF021A000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=16bit */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000	/* Size of used area in RAM	       */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/CPU86.h b/qemu/roms/u-boot/include/configs/CPU86.h
new file mode 100644
index 000000000..7be83b078
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/CPU86.h
@@ -0,0 +1,629 @@
+/*
+ * (C) Copyright 2001-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_CPU86		1	/* ...on a CPU86 board	*/
+#define CONFIG_CPM2		1	/* Has a CPM2 */
+
+#ifdef CONFIG_BOOT_ROM
+#define CONFIG_SYS_TEXT_BASE	0xFF800000
+#else
+#define	CONFIG_SYS_TEXT_BASE	0xFF000000
+#endif
+
+/*
+ * select serial console configuration
+ *
+ * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ *
+ * if CONFIG_CONS_NONE is defined, then the serial console routines must
+ * defined elsewhere (for example, on the cogent platform, there are serial
+ * ports on the motherboard which are used for the serial console - see
+ * cogent/cma101/serial.[ch]).
+ */
+#undef  CONFIG_CONS_ON_SMC		/* define if console on SMC */
+#define CONFIG_CONS_ON_SCC		/* define if console on SCC */
+#undef  CONFIG_CONS_NONE		/* define if console on something else*/
+#define CONFIG_CONS_INDEX	1	/* which serial channel for console */
+
+#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
+#define CONFIG_BAUDRATE		230400
+#else
+#define CONFIG_BAUDRATE		9600
+#endif
+
+/*
+ * select ethernet configuration
+ *
+ * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
+ * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
+ * for FCC)
+ *
+ * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
+ */
+#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC       */
+#define	CONFIG_ETHER_ON_FCC		/* define if ether on FCC       */
+#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
+#define	CONFIG_ETHER_INDEX	1	/* which SCC/FCC channel for ethernet */
+
+#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
+
+/*
+ * - Rx-CLK is CLK11
+ * - Tx-CLK is CLK12
+ * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
+ * - Enable Full Duplex in FSMR
+ */
+# define CONFIG_SYS_CMXFCR_MASK1	(CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE1	(CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
+# define CONFIG_SYS_CPMFCR_RAMTYPE	0
+# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+
+#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
+
+/*
+ * - Rx-CLK is CLK13
+ * - Tx-CLK is CLK14
+ * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
+ * - Enable Full Duplex in FSMR
+ */
+# define CONFIG_SYS_CMXFCR_MASK2	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
+# define CONFIG_SYS_CPMFCR_RAMTYPE	0
+# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+
+#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
+
+/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
+#define CONFIG_8260_CLKIN	64000000	/* in Hz */
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_PREBOOT								\
+	"echo; "								\
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS; "	\
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND							\
+	"bootp; "								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
+	"bootm"
+
+/*-----------------------------------------------------------------------
+ * I2C/EEPROM/RTC configuration
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT			/* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED	50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
+
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
+#define I2C_ACTIVE	(iop->pdir |=  0x00010000)
+#define I2C_TRISTATE	(iop->pdir &= ~0x00010000)
+#define I2C_READ	((iop->pdat & 0x00010000) != 0)
+#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00010000; \
+			else    iop->pdat &= ~0x00010000
+#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00020000; \
+			else    iop->pdat &= ~0x00020000
+#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
+
+#define CONFIG_RTC_PCF8563
+#define CONFIG_SYS_I2C_RTC_ADDR	0x51
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configuration options
+ */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address	*/
+
+#define	CONFIG_SYS_RESET_ADDRESS 0xFFF00100	/* "bad" address		*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * Flash configuration
+ */
+
+#define CONFIG_SYS_BOOTROM_BASE	0xFF800000
+#define CONFIG_SYS_BOOTROM_SIZE	0x00080000
+#define CONFIG_SYS_FLASH_BASE		0xFF000000
+#define CONFIG_SYS_FLASH_SIZE		0x00800000
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max num of memory banks      */
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+
+/*-----------------------------------------------------------------------
+ * Other areas to be mapped
+ */
+
+/* CS3: Dual ported SRAM */
+#define CONFIG_SYS_DPSRAM_BASE		0x40000000
+#define CONFIG_SYS_DPSRAM_SIZE		0x00020000
+
+/* CS4: DiskOnChip */
+#define CONFIG_SYS_DOC_BASE		0xF4000000
+#define CONFIG_SYS_DOC_SIZE		0x00100000
+
+/* CS5: FDC37C78 controller */
+#define CONFIG_SYS_FDC37C78_BASE	0xF1000000
+#define CONFIG_SYS_FDC37C78_SIZE	0x00100000
+
+/* CS6: Board configuration registers */
+#define CONFIG_SYS_BCRS_BASE		0xF2000000
+#define CONFIG_SYS_BCRS_SIZE		0x00010000
+
+/* CS7: VME Extended Access Range */
+#define CONFIG_SYS_VMEEAR_BASE		0x80000000
+#define CONFIG_SYS_VMEEAR_SIZE		0x01000000
+
+/* CS8: VME Standard Access Range */
+#define CONFIG_SYS_VMESAR_BASE		0xFE000000
+#define CONFIG_SYS_VMESAR_SIZE		0x01000000
+
+/* CS9: VME Short I/O Access Range */
+#define CONFIG_SYS_VMESIOAR_BASE	0xFD000000
+#define CONFIG_SYS_VMESIOAR_SIZE	0x01000000
+
+/*-----------------------------------------------------------------------
+ * Hard Reset Configuration Words
+ *
+ * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
+ * defines for the various registers affected by the HRCW e.g. changing
+ * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
+ */
+#if defined(CONFIG_BOOT_ROM)
+#define CONFIG_SYS_HRCW_MASTER		(HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
+				 HRCW_BPS01 | HRCW_CS10PC01)
+#else
+#define CONFIG_SYS_HRCW_MASTER		(HRCW_CIP | HRCW_ISB100 | HRCW_BMS | HRCW_CS10PC01)
+#endif
+
+/* no slaves so just fill with zeros */
+#define CONFIG_SYS_HRCW_SLAVE1		0
+#define CONFIG_SYS_HRCW_SLAVE2		0
+#define CONFIG_SYS_HRCW_SLAVE3		0
+#define CONFIG_SYS_HRCW_SLAVE4		0
+#define CONFIG_SYS_HRCW_SLAVE5		0
+#define CONFIG_SYS_HRCW_SLAVE6		0
+#define CONFIG_SYS_HRCW_SLAVE7		0
+
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xF0000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000  /* Size of used area in DPRAM    */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ *
+ * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE.
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_MAX_SIZE	0x08000000	/* max. 128 MB		*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+# define CONFIG_SYS_RAMBOOT
+#endif
+
+#if 0
+/* environment is in Flash */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#ifdef CONFIG_BOOT_ROM
+# define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE+0x70000)
+# define CONFIG_ENV_SIZE		0x10000
+# define CONFIG_ENV_SECT_SIZE	0x10000
+#endif
+#else
+/* environment is in EEPROM */
+#define CONFIG_ENV_IS_IN_EEPROM	1
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x58	/* EEPROM X24C16		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+/* mask of address bits that overflow into the "EEPROM chip address"    */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+#define CONFIG_ENV_OFFSET		512
+#define CONFIG_ENV_SIZE		(2048 - 512)
+#endif
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
+#if defined(CONFIG_CMD_KGDB)
+# define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * HIDx - Hardware Implementation-dependent Registers                    2-11
+ *-----------------------------------------------------------------------
+ * HID0 also contains cache control - initially enable both caches and
+ * invalidate contents, then the final state leaves only the instruction
+ * cache enabled. Note that Power-On and Hard reset invalidate the caches,
+ * but Soft reset does not.
+ *
+ * HID1 has only read-only information - nothing to set.
+ */
+#define CONFIG_SYS_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|\
+			 HID0_DCI|HID0_IFEM|HID0_ABE)
+#define CONFIG_SYS_HID0_FINAL  (HID0_IFEM|HID0_ABE)
+#define CONFIG_SYS_HID2        0
+
+/*-----------------------------------------------------------------------
+ * RMR - Reset Mode Register                                     5-5
+ *-----------------------------------------------------------------------
+ * turn on Checkstop Reset Enable
+ */
+#define CONFIG_SYS_RMR         RMR_CSRE
+
+/*-----------------------------------------------------------------------
+ * BCR - Bus Configuration                                       4-25
+ *-----------------------------------------------------------------------
+ */
+#define BCR_APD01	0x10000000
+#define CONFIG_SYS_BCR		(BCR_APD01|BCR_ETM|BCR_LETM)	/* 8260 mode */
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration                             4-31
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_SIUMCR      (SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\
+			 SIUMCR_CS10PC01|SIUMCR_BCTLC10)
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control                             4-35
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
+#else
+#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+			 SYPCR_SWRI|SYPCR_SWP)
+#endif /* CONFIG_WATCHDOG */
+
+/*-----------------------------------------------------------------------
+ * TMCNTSC - Time Counter Status and Control                     4-40
+ *-----------------------------------------------------------------------
+ * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
+ * and enable Time Counter
+ */
+#define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control                 4-42
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
+ * Periodic timer
+ */
+#define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control                                   9-8
+ *-----------------------------------------------------------------------
+ * Ensure DFBRG is Divide by 16
+ */
+#define CONFIG_SYS_SCCR        SCCR_DFBRG01
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration                         13-7
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RCCR        0
+
+#define CONFIG_SYS_MIN_AM_MASK	0xC0000000
+/*-----------------------------------------------------------------------
+ * MPTPR - Memory Refresh Timer Prescaler Register              10-18
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_MPTPR       0x1F00
+
+/*-----------------------------------------------------------------------
+ * PSRT - Refresh Timer Register                                10-16
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_PSRT        0x0f
+
+/*-----------------------------------------------------------------------
+ * PSRT - SDRAM Mode Register                                   10-10
+ *-----------------------------------------------------------------------
+ */
+
+	/* SDRAM initialization values for 8-column chips
+	 */
+#define CONFIG_SYS_OR2_8COL	(CONFIG_SYS_MIN_AM_MASK		|\
+			 ORxS_BPD_4			|\
+			 ORxS_ROWST_PBI0_A9		|\
+			 ORxS_NUMR_12)
+
+#define CONFIG_SYS_PSDMR_8COL	(PSDMR_SDAM_A13_IS_A5		|\
+			 PSDMR_BSMA_A14_A16		|\
+			 PSDMR_SDA10_PBI0_A10		|\
+			 PSDMR_RFRC_7_CLK		|\
+			 PSDMR_PRETOACT_2W		|\
+			 PSDMR_ACTTORW_1W		|\
+			 PSDMR_LDOTOPRE_1C		|\
+			 PSDMR_WRC_1C			|\
+			 PSDMR_CL_2)
+
+	/* SDRAM initialization values for 9-column chips
+	 */
+#define CONFIG_SYS_OR2_9COL	(CONFIG_SYS_MIN_AM_MASK		|\
+			 ORxS_BPD_4			|\
+			 ORxS_ROWST_PBI0_A7		|\
+			 ORxS_NUMR_13)
+
+#define CONFIG_SYS_PSDMR_9COL	(PSDMR_SDAM_A14_IS_A5		|\
+			 PSDMR_BSMA_A13_A15		|\
+			 PSDMR_SDA10_PBI0_A9		|\
+			 PSDMR_RFRC_7_CLK		|\
+			 PSDMR_PRETOACT_2W		|\
+			 PSDMR_ACTTORW_1W		|\
+			 PSDMR_LDOTOPRE_1C		|\
+			 PSDMR_WRC_1C			|\
+			 PSDMR_CL_2)
+
+/*
+ * Init Memory Controller:
+ *
+ * Bank Bus     Machine PortSz  Device
+ * ---- ---     ------- ------  ------
+ *  0   60x     GPCM    8  bit  Boot ROM
+ *  1   60x     GPCM    64 bit  FLASH
+ *  2   60x     SDRAM   64 bit  SDRAM
+ *
+ */
+
+#define CONFIG_SYS_MRS_OFFS	0x00000000
+
+#ifdef CONFIG_BOOT_ROM
+/* Bank 0 - Boot ROM
+ */
+#define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
+			 BRx_PS_8                       |\
+			 BRx_MS_GPCM_P                  |\
+			 BRx_V)
+
+#define CONFIG_SYS_OR0_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE)   |\
+			 ORxG_CSNT                      |\
+			 ORxG_ACS_DIV1                  |\
+			 ORxG_SCY_3_CLK                 |\
+			 ORxU_EHTR_8IDLE)
+
+/* Bank 1 - FLASH
+ */
+#define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)  |\
+			 BRx_PS_64                      |\
+			 BRx_MS_GPCM_P                  |\
+			 BRx_V)
+
+#define CONFIG_SYS_OR1_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)     |\
+			 ORxG_CSNT                      |\
+			 ORxG_ACS_DIV1                  |\
+			 ORxG_SCY_3_CLK                 |\
+			 ORxU_EHTR_8IDLE)
+
+#else /* CONFIG_BOOT_ROM */
+/* Bank 0 - FLASH
+ */
+#define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)  |\
+			 BRx_PS_64                      |\
+			 BRx_MS_GPCM_P                  |\
+			 BRx_V)
+
+#define CONFIG_SYS_OR0_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)     |\
+			 ORxG_CSNT                      |\
+			 ORxG_ACS_DIV1                  |\
+			 ORxG_SCY_3_CLK                 |\
+			 ORxU_EHTR_8IDLE)
+
+/* Bank 1 - Boot ROM
+ */
+#define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
+			 BRx_PS_8                       |\
+			 BRx_MS_GPCM_P                  |\
+			 BRx_V)
+
+#define CONFIG_SYS_OR1_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE)   |\
+			 ORxG_CSNT                      |\
+			 ORxG_ACS_DIV1                  |\
+			 ORxG_SCY_3_CLK                 |\
+			 ORxU_EHTR_8IDLE)
+
+#endif /* CONFIG_BOOT_ROM */
+
+
+/* Bank 2 - 60x bus SDRAM
+ */
+#ifndef CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_BR2_PRELIM  ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)  |\
+			 BRx_PS_64                      |\
+			 BRx_MS_SDRAM_P                 |\
+			 BRx_V)
+
+#define CONFIG_SYS_OR2_PRELIM	 CONFIG_SYS_OR2_9COL
+
+#define CONFIG_SYS_PSDMR	 CONFIG_SYS_PSDMR_9COL
+#endif /* CONFIG_SYS_RAMBOOT */
+
+/* Bank 3 - Dual Ported SRAM
+ */
+#define CONFIG_SYS_BR3_PRELIM  ((CONFIG_SYS_DPSRAM_BASE & BRx_BA_MSK) |\
+			 BRx_PS_16                      |\
+			 BRx_MS_GPCM_P                  |\
+			 BRx_V)
+
+#define CONFIG_SYS_OR3_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_DPSRAM_SIZE)    |\
+			 ORxG_CSNT                      |\
+			 ORxG_ACS_DIV1                  |\
+			 ORxG_SCY_5_CLK                 |\
+			 ORxG_SETA)
+
+/* Bank 4 - DiskOnChip
+ */
+#define CONFIG_SYS_BR4_PRELIM  ((CONFIG_SYS_DOC_BASE & BRx_BA_MSK)    |\
+			 BRx_PS_8                       |\
+			 BRx_MS_GPCM_P                  |\
+			 BRx_V)
+
+#define CONFIG_SYS_OR4_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE)       |\
+			 ORxG_ACS_DIV2                  |\
+			 ORxG_SCY_5_CLK                 |\
+			 ORxU_EHTR_8IDLE)
+
+/* Bank 5 - FDC37C78 controller
+ */
+#define CONFIG_SYS_BR5_PRELIM  ((CONFIG_SYS_FDC37C78_BASE & BRx_BA_MSK) |\
+			 BRx_PS_8                         |\
+			 BRx_MS_GPCM_P                    |\
+			 BRx_V)
+
+#define CONFIG_SYS_OR5_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_FDC37C78_SIZE)    |\
+			 ORxG_ACS_DIV2                    |\
+			 ORxG_SCY_8_CLK                   |\
+			 ORxU_EHTR_8IDLE)
+
+/* Bank 6 - Board control registers
+ */
+#define CONFIG_SYS_BR6_PRELIM  ((CONFIG_SYS_BCRS_BASE & BRx_BA_MSK)   |\
+			 BRx_PS_8                       |\
+			 BRx_MS_GPCM_P                  |\
+			 BRx_V)
+
+#define CONFIG_SYS_OR6_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_BCRS_SIZE)      |\
+			 ORxG_CSNT                      |\
+			 ORxG_SCY_5_CLK)
+
+/* Bank 7 - VME Extended Access Range
+ */
+#define CONFIG_SYS_BR7_PRELIM  ((CONFIG_SYS_VMEEAR_BASE & BRx_BA_MSK) |\
+			 BRx_PS_32                      |\
+			 BRx_MS_GPCM_P                  |\
+			 BRx_V)
+
+#define CONFIG_SYS_OR7_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_VMEEAR_SIZE)    |\
+			 ORxG_CSNT                      |\
+			 ORxG_ACS_DIV1                  |\
+			 ORxG_SCY_5_CLK                 |\
+			 ORxG_SETA)
+
+/* Bank 8 - VME Standard Access Range
+ */
+#define CONFIG_SYS_BR8_PRELIM  ((CONFIG_SYS_VMESAR_BASE & BRx_BA_MSK) |\
+			 BRx_PS_16                      |\
+			 BRx_MS_GPCM_P                  |\
+			 BRx_V)
+
+#define CONFIG_SYS_OR8_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_VMESAR_SIZE)    |\
+			 ORxG_CSNT                      |\
+			 ORxG_ACS_DIV1                  |\
+			 ORxG_SCY_5_CLK                 |\
+			 ORxG_SETA)
+
+/* Bank 9 - VME Short I/O Access Range
+ */
+#define CONFIG_SYS_BR9_PRELIM  ((CONFIG_SYS_VMESIOAR_BASE & BRx_BA_MSK) |\
+			 BRx_PS_16                        |\
+			 BRx_MS_GPCM_P                    |\
+			 BRx_V)
+
+#define CONFIG_SYS_OR9_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_VMESIOAR_SIZE)    |\
+			 ORxG_CSNT                        |\
+			 ORxG_ACS_DIV1                    |\
+			 ORxG_SCY_5_CLK                   |\
+			 ORxG_SETA)
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/CPU87.h b/qemu/roms/u-boot/include/configs/CPU87.h
new file mode 100644
index 000000000..d3a59e8ba
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/CPU87.h
@@ -0,0 +1,676 @@
+/*
+ * (C) Copyright 2001-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_CPU87		1	/* ...on a CPU87 board	*/
+#define CONFIG_PCI
+#define CONFIG_CPM2		1	/* Has a CPM2 */
+
+#ifdef CONFIG_BOOT_ROM
+#define CONFIG_SYS_TEXT_BASE	0xFF800000
+#else
+#define	CONFIG_SYS_TEXT_BASE	0xFF000000
+#endif
+
+/*
+ * select serial console configuration
+ *
+ * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ *
+ * if CONFIG_CONS_NONE is defined, then the serial console routines must
+ * defined elsewhere (for example, on the cogent platform, there are serial
+ * ports on the motherboard which are used for the serial console - see
+ * cogent/cma101/serial.[ch]).
+ */
+#undef	CONFIG_CONS_ON_SMC		/* define if console on SMC */
+#define CONFIG_CONS_ON_SCC		/* define if console on SCC */
+#undef	CONFIG_CONS_NONE		/* define if console on something else*/
+#define CONFIG_CONS_INDEX	1	/* which serial channel for console */
+
+#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
+#define CONFIG_BAUDRATE		230400
+#else
+#define CONFIG_BAUDRATE		9600
+#endif
+
+/*
+ * select ethernet configuration
+ *
+ * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
+ * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
+ * for FCC)
+ *
+ * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
+ */
+#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC	*/
+#define CONFIG_ETHER_ON_FCC		/* define if ether on FCC	*/
+#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
+#define CONFIG_ETHER_INDEX	1	/* which SCC/FCC channel for ethernet */
+
+#define	CONFIG_HAS_ETH1		1
+#define	CONFIG_HAS_ETH2		1
+
+#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
+
+/*
+ * - Rx-CLK is CLK11
+ * - Tx-CLK is CLK12
+ * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
+ * - Enable Full Duplex in FSMR
+ */
+# define CONFIG_SYS_CMXFCR_MASK1	(CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE1	(CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
+# define CONFIG_SYS_CPMFCR_RAMTYPE	0
+# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+
+#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
+
+/*
+ * - Rx-CLK is CLK13
+ * - Tx-CLK is CLK14
+ * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
+ * - Enable Full Duplex in FSMR
+ */
+# define CONFIG_SYS_CMXFCR_MASK2	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
+# define CONFIG_SYS_CPMFCR_RAMTYPE	0
+# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+
+#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
+
+/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
+#define CONFIG_8260_CLKIN	100000000	/* in Hz */
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_PREBOOT								\
+	"echo; "								\
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS; "	\
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND							\
+	"bootp; "								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
+	"bootm"
+
+/*-----------------------------------------------------------------------
+ * I2C/EEPROM/RTC configuration
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED	50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
+
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
+#define I2C_ACTIVE	(iop->pdir |=  0x00010000)
+#define I2C_TRISTATE	(iop->pdir &= ~0x00010000)
+#define I2C_READ	((iop->pdat & 0x00010000) != 0)
+#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00010000; \
+			else	iop->pdat &= ~0x00010000
+#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00020000; \
+			else	iop->pdat &= ~0x00020000
+#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
+
+#define CONFIG_RTC_PCF8563
+#define CONFIG_SYS_I2C_RTC_ADDR	0x51
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/*-----------------------------------------------------------------------
+ * Disk-On-Chip configuration
+ */
+
+#define CONFIG_SYS_MAX_DOC_DEVICE	1	/* Max number of DOC devices	*/
+
+#define CONFIG_SYS_DOC_SUPPORT_2000
+#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configuration options
+ */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+    #define CONFIG_CMD_PCI
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END 0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+
+#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100	/* "bad" address		*/
+
+#define CONFIG_LOOPW
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * Flash configuration
+ */
+
+#define CONFIG_SYS_BOOTROM_BASE	0xFF800000
+#define CONFIG_SYS_BOOTROM_SIZE	0x00080000
+#define CONFIG_SYS_FLASH_BASE		0xFF000000
+#define CONFIG_SYS_FLASH_SIZE		0x00800000
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max num of memory banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	135	/* max num of sects on one chip */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
+
+/*-----------------------------------------------------------------------
+ * Other areas to be mapped
+ */
+
+/* CS3: Dual ported SRAM */
+#define CONFIG_SYS_DPSRAM_BASE		0x40000000
+#define CONFIG_SYS_DPSRAM_SIZE		0x00100000
+
+/* CS4: DiskOnChip */
+#define CONFIG_SYS_DOC_BASE		0xF4000000
+#define CONFIG_SYS_DOC_SIZE		0x00100000
+
+/* CS5: FDC37C78 controller */
+#define CONFIG_SYS_FDC37C78_BASE	0xF1000000
+#define CONFIG_SYS_FDC37C78_SIZE	0x00100000
+
+/* CS6: Board configuration registers */
+#define CONFIG_SYS_BCRS_BASE		0xF2000000
+#define CONFIG_SYS_BCRS_SIZE		0x00010000
+
+/* CS7: VME Extended Access Range */
+#define CONFIG_SYS_VMEEAR_BASE		0x60000000
+#define CONFIG_SYS_VMEEAR_SIZE		0x01000000
+
+/* CS8: VME Standard Access Range */
+#define CONFIG_SYS_VMESAR_BASE		0xFE000000
+#define CONFIG_SYS_VMESAR_SIZE		0x01000000
+
+/* CS9: VME Short I/O Access Range */
+#define CONFIG_SYS_VMESIOAR_BASE	0xFD000000
+#define CONFIG_SYS_VMESIOAR_SIZE	0x01000000
+
+/*-----------------------------------------------------------------------
+ * Hard Reset Configuration Words
+ *
+ * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
+ * defines for the various registers affected by the HRCW e.g. changing
+ * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
+ */
+#if defined(CONFIG_BOOT_ROM)
+#define CONFIG_SYS_HRCW_MASTER		(HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
+				 HRCW_BPS01 | HRCW_CS10PC01)
+#else
+#define CONFIG_SYS_HRCW_MASTER		(HRCW_CIP | HRCW_ISB100 | HRCW_BMS | HRCW_CS10PC01)
+#endif
+
+/* no slaves so just fill with zeros */
+#define CONFIG_SYS_HRCW_SLAVE1		0
+#define CONFIG_SYS_HRCW_SLAVE2		0
+#define CONFIG_SYS_HRCW_SLAVE3		0
+#define CONFIG_SYS_HRCW_SLAVE4		0
+#define CONFIG_SYS_HRCW_SLAVE5		0
+#define CONFIG_SYS_HRCW_SLAVE6		0
+#define CONFIG_SYS_HRCW_SLAVE7		0
+
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xF0000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ *
+ * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE.
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_MAX_SIZE	0x08000000	/* max. 128 MB		*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+# define CONFIG_SYS_RAMBOOT
+#endif
+
+#ifdef	CONFIG_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_EEPRO100
+#define CONFIG_SYS_RX_ETH_BUFFER	8		/* use 8 rx buffer on eepro100	*/
+#endif
+
+#if 0
+/* environment is in Flash */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#ifdef CONFIG_BOOT_ROM
+# define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE+0x70000)
+# define CONFIG_ENV_SIZE		0x10000
+# define CONFIG_ENV_SECT_SIZE	0x10000
+#endif
+#else
+/* environment is in EEPROM */
+#define CONFIG_ENV_IS_IN_EEPROM	1
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x58	/* EEPROM X24C16		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+#define CONFIG_ENV_OFFSET		512
+#define CONFIG_ENV_SIZE		(2048 - 512)
+#endif
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPU		*/
+#if defined(CONFIG_CMD_KGDB)
+# define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * HIDx - Hardware Implementation-dependent Registers			 2-11
+ *-----------------------------------------------------------------------
+ * HID0 also contains cache control - initially enable both caches and
+ * invalidate contents, then the final state leaves only the instruction
+ * cache enabled. Note that Power-On and Hard reset invalidate the caches,
+ * but Soft reset does not.
+ *
+ * HID1 has only read-only information - nothing to set.
+ */
+#define CONFIG_SYS_HID0_INIT	(HID0_ICE|HID0_DCE|HID0_ICFI|\
+			 HID0_DCI|HID0_IFEM|HID0_ABE)
+#define CONFIG_SYS_HID0_FINAL	(HID0_IFEM|HID0_ABE)
+#define CONFIG_SYS_HID2	0
+
+/*-----------------------------------------------------------------------
+ * RMR - Reset Mode Register					 5-5
+ *-----------------------------------------------------------------------
+ * turn on Checkstop Reset Enable
+ */
+#define CONFIG_SYS_RMR		RMR_CSRE
+
+/*-----------------------------------------------------------------------
+ * BCR - Bus Configuration					 4-25
+ *-----------------------------------------------------------------------
+ */
+#define BCR_APD01	0x10000000
+#define CONFIG_SYS_BCR		(BCR_APD01|BCR_ETM|BCR_LETM)	/* 8260 mode */
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				 4-31
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\
+			 SIUMCR_CS10PC01|SIUMCR_BCTLC10)
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				 4-35
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
+#else
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+			 SYPCR_SWRI|SYPCR_SWP)
+#endif /* CONFIG_WATCHDOG */
+
+/*-----------------------------------------------------------------------
+ * TMCNTSC - Time Counter Status and Control			 4-40
+ *-----------------------------------------------------------------------
+ * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
+ * and enable Time Counter
+ */
+#define CONFIG_SYS_TMCNTSC	(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		 4-42
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
+ * Periodic timer
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS|PISCR_PTF|PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control					 9-8
+ *-----------------------------------------------------------------------
+ * Ensure DFBRG is Divide by 16
+ */
+#define CONFIG_SYS_SCCR	SCCR_DFBRG01
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration				13-7
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RCCR	0
+
+#define CONFIG_SYS_MIN_AM_MASK 0xC0000000
+
+/*
+ * we use the same values for 32 MB, 128 MB and 256 MB SDRAM
+ * refresh rate = 7.68 uS (100 MHz Bus Clock)
+ */
+
+/*-----------------------------------------------------------------------
+ * MPTPR - Memory Refresh Timer Prescaler Register		10-18
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_MPTPR	0x2000
+
+/*-----------------------------------------------------------------------
+ * PSRT - Refresh Timer Register				10-16
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_PSRT	0x16
+
+/*-----------------------------------------------------------------------
+ * PSRT - SDRAM Mode Register					10-10
+ *-----------------------------------------------------------------------
+ */
+
+	/* SDRAM initialization values for 8-column chips
+	 */
+#define CONFIG_SYS_OR2_8COL	(CONFIG_SYS_MIN_AM_MASK		|\
+			 ORxS_BPD_4			|\
+			 ORxS_ROWST_PBI0_A9		|\
+			 ORxS_NUMR_12)
+
+#define CONFIG_SYS_PSDMR_8COL	(PSDMR_SDAM_A13_IS_A5		|\
+			 PSDMR_BSMA_A14_A16		|\
+			 PSDMR_SDA10_PBI0_A10		|\
+			 PSDMR_RFRC_7_CLK		|\
+			 PSDMR_PRETOACT_2W		|\
+			 PSDMR_ACTTORW_2W		|\
+			 PSDMR_LDOTOPRE_1C		|\
+			 PSDMR_WRC_1C			|\
+			 PSDMR_CL_2)
+
+	/* SDRAM initialization values for 9-column chips
+	 */
+#define CONFIG_SYS_OR2_9COL	(CONFIG_SYS_MIN_AM_MASK		|\
+			 ORxS_BPD_4			|\
+			 ORxS_ROWST_PBI0_A7		|\
+			 ORxS_NUMR_13)
+
+#define CONFIG_SYS_PSDMR_9COL	(PSDMR_SDAM_A14_IS_A5		|\
+			 PSDMR_BSMA_A13_A15		|\
+			 PSDMR_SDA10_PBI0_A9		|\
+			 PSDMR_RFRC_7_CLK		|\
+			 PSDMR_PRETOACT_2W		|\
+			 PSDMR_ACTTORW_2W		|\
+			 PSDMR_LDOTOPRE_1C		|\
+			 PSDMR_WRC_1C			|\
+			 PSDMR_CL_2)
+
+	/* SDRAM initialization values for 10-column chips
+	 */
+#define CONFIG_SYS_OR2_10COL	(CONFIG_SYS_MIN_AM_MASK		|\
+			 ORxS_BPD_4			|\
+			 ORxS_ROWST_PBI1_A4		|\
+			 ORxS_NUMR_13)
+
+#define CONFIG_SYS_PSDMR_10COL	(PSDMR_PBI			|\
+			 PSDMR_SDAM_A17_IS_A5		|\
+			 PSDMR_BSMA_A13_A15		|\
+			 PSDMR_SDA10_PBI1_A6		|\
+			 PSDMR_RFRC_7_CLK		|\
+			 PSDMR_PRETOACT_2W		|\
+			 PSDMR_ACTTORW_2W		|\
+			 PSDMR_LDOTOPRE_1C		|\
+			 PSDMR_WRC_1C			|\
+			 PSDMR_CL_2)
+
+/*
+ * Init Memory Controller:
+ *
+ * Bank Bus	Machine PortSz	Device
+ * ---- ---	------- ------	------
+ *  0	60x	GPCM	8  bit	Boot ROM
+ *  1	60x	GPCM	64 bit	FLASH
+ *  2	60x	SDRAM	64 bit	SDRAM
+ *
+ */
+
+#define CONFIG_SYS_MRS_OFFS	0x00000000
+
+#ifdef CONFIG_BOOT_ROM
+/* Bank 0 - Boot ROM
+ */
+#define CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
+			 BRx_PS_8			|\
+			 BRx_MS_GPCM_P			|\
+			 BRx_V)
+
+#define CONFIG_SYS_OR0_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE)	|\
+			 ORxG_CSNT			|\
+			 ORxG_ACS_DIV1			|\
+			 ORxG_SCY_5_CLK			|\
+			 ORxU_EHTR_8IDLE)
+
+/* Bank 1 - FLASH
+ */
+#define CONFIG_SYS_BR1_PRELIM	((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)	|\
+			 BRx_PS_64			|\
+			 BRx_MS_GPCM_P			|\
+			 BRx_V)
+
+#define CONFIG_SYS_OR1_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)	|\
+			 ORxG_CSNT			|\
+			 ORxG_ACS_DIV1			|\
+			 ORxG_SCY_5_CLK			|\
+			 ORxU_EHTR_8IDLE)
+
+#else /* CONFIG_BOOT_ROM */
+/* Bank 0 - FLASH
+ */
+#define CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)	|\
+			 BRx_PS_64			|\
+			 BRx_MS_GPCM_P			|\
+			 BRx_V)
+
+#define CONFIG_SYS_OR0_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)	|\
+			 ORxG_CSNT			|\
+			 ORxG_ACS_DIV1			|\
+			 ORxG_SCY_5_CLK			|\
+			 ORxU_EHTR_8IDLE)
+
+/* Bank 1 - Boot ROM
+ */
+#define CONFIG_SYS_BR1_PRELIM	((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
+			 BRx_PS_8			|\
+			 BRx_MS_GPCM_P			|\
+			 BRx_V)
+
+#define CONFIG_SYS_OR1_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE)	|\
+			 ORxG_CSNT			|\
+			 ORxG_ACS_DIV1			|\
+			 ORxG_SCY_5_CLK			|\
+			 ORxU_EHTR_8IDLE)
+
+#endif /* CONFIG_BOOT_ROM */
+
+
+/* Bank 2 - 60x bus SDRAM
+ */
+#ifndef CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_BR2_PRELIM	((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)	|\
+			 BRx_PS_64			|\
+			 BRx_MS_SDRAM_P			|\
+			 BRx_V)
+
+#define CONFIG_SYS_OR2_PRELIM	 CONFIG_SYS_OR2_8COL
+
+#define CONFIG_SYS_PSDMR	 CONFIG_SYS_PSDMR_8COL
+#endif /* CONFIG_SYS_RAMBOOT */
+
+/* Bank 3 - Dual Ported SRAM
+ */
+#define CONFIG_SYS_BR3_PRELIM	((CONFIG_SYS_DPSRAM_BASE & BRx_BA_MSK) |\
+			 BRx_PS_16			|\
+			 BRx_MS_GPCM_P			|\
+			 BRx_V)
+
+#define CONFIG_SYS_OR3_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_DPSRAM_SIZE)	|\
+			 ORxG_CSNT			|\
+			 ORxG_ACS_DIV1			|\
+			 ORxG_SCY_7_CLK			|\
+			 ORxG_SETA)
+
+/* Bank 4 - DiskOnChip
+ */
+#define CONFIG_SYS_BR4_PRELIM	((CONFIG_SYS_DOC_BASE & BRx_BA_MSK)	|\
+			 BRx_PS_8			|\
+			 BRx_MS_GPCM_P			|\
+			 BRx_V)
+
+#define CONFIG_SYS_OR4_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE)	|\
+			 ORxG_CSNT			|\
+			 ORxG_ACS_DIV2			|\
+			 ORxG_SCY_9_CLK			|\
+			 ORxU_EHTR_8IDLE)
+
+/* Bank 5 - FDC37C78 controller
+ */
+#define CONFIG_SYS_BR5_PRELIM	((CONFIG_SYS_FDC37C78_BASE & BRx_BA_MSK) |\
+			 BRx_PS_8			  |\
+			 BRx_MS_GPCM_P			  |\
+			 BRx_V)
+
+#define CONFIG_SYS_OR5_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_FDC37C78_SIZE)	  |\
+			 ORxG_ACS_DIV2			  |\
+			 ORxG_SCY_10_CLK		  |\
+			 ORxU_EHTR_8IDLE)
+
+/* Bank 6 - Board control registers
+ */
+#define CONFIG_SYS_BR6_PRELIM	((CONFIG_SYS_BCRS_BASE & BRx_BA_MSK)	|\
+			 BRx_PS_8			|\
+			 BRx_MS_GPCM_P			|\
+			 BRx_V)
+
+#define CONFIG_SYS_OR6_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_BCRS_SIZE)	|\
+			 ORxG_CSNT			|\
+			 ORxG_SCY_7_CLK)
+
+/* Bank 7 - VME Extended Access Range
+ */
+#define CONFIG_SYS_BR7_PRELIM	((CONFIG_SYS_VMEEAR_BASE & BRx_BA_MSK) |\
+			 BRx_PS_32			|\
+			 BRx_MS_GPCM_P			|\
+			 BRx_V)
+
+#define CONFIG_SYS_OR7_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_VMEEAR_SIZE)	|\
+			 ORxG_CSNT			|\
+			 ORxG_ACS_DIV1			|\
+			 ORxG_SCY_7_CLK			|\
+			 ORxG_SETA)
+
+/* Bank 8 - VME Standard Access Range
+ */
+#define CONFIG_SYS_BR8_PRELIM	((CONFIG_SYS_VMESAR_BASE & BRx_BA_MSK) |\
+			 BRx_PS_16			|\
+			 BRx_MS_GPCM_P			|\
+			 BRx_V)
+
+#define CONFIG_SYS_OR8_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_VMESAR_SIZE)	|\
+			 ORxG_CSNT			|\
+			 ORxG_ACS_DIV1			|\
+			 ORxG_SCY_7_CLK			|\
+			 ORxG_SETA)
+
+/* Bank 9 - VME Short I/O Access Range
+ */
+#define CONFIG_SYS_BR9_PRELIM	((CONFIG_SYS_VMESIOAR_BASE & BRx_BA_MSK) |\
+			 BRx_PS_16			  |\
+			 BRx_MS_GPCM_P			  |\
+			 BRx_V)
+
+#define CONFIG_SYS_OR9_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_VMESIOAR_SIZE)	  |\
+			 ORxG_CSNT			  |\
+			 ORxG_ACS_DIV1			  |\
+			 ORxG_SCY_7_CLK			  |\
+			 ORxG_SETA)
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/CRAYL1.h b/qemu/roms/u-boot/include/configs/CRAYL1.h
new file mode 100644
index 000000000..788fa0f91
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/CRAYL1.h
@@ -0,0 +1,228 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * David Updegraff, Cray, Inc.  dave@cray.com: our 405 is walnut-lite..
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_CRAYL1
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405GP		1	/* This is a PPC405 CPU	*/
+
+/*
+ * Note: I make an "image" from U-Boot itself, which prefixes 0x40
+ * bytes of header info, hence start address is thus shifted.
+ */
+#define	CONFIG_SYS_TEXT_BASE	0xFFFD0040
+
+#define CONFIG_SYS_CLK_FREQ 25000000
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_PPC4xx_EMAC
+#define CONFIG_MII		    1	/* MII PHY management */
+#define	CONFIG_PHY_ADDR		1	/* PHY address; handling of ENET */
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* early setup for 405gp */
+#define CONFIG_MISC_INIT_R	1	/* so that a misc_init_r() is called */
+
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+
+/* set PRAM to keep U-Boot out, mem= to keep linux out, and initrd_hi to
+ * keep possible initrd ramdisk decompression out.  This is in k (1024 bytes)
+ #define CONFIG_PRAM			16
+ */
+#define	CONFIG_LOADADDR		0x100000	/* where TFTP images go */
+#undef CONFIG_BOOTARGS
+
+/* Bootcmd is overridden by the bootscript in board/cray/L1
+ */
+#define	CONFIG_SYS_AUTOLOAD		"no"
+#define CONFIG_BOOTCOMMAND	"dhcp"
+
+/*
+ * ..during experiments..
+ #define CONFIG_SERVERIP         10.0.0.1
+ #define CONFIG_ETHADDR          00:40:a6:80:14:5
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SDRAM_BANK0		1
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		    400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		    0x7F
+#define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_IDENT_STRING     "Cray L1"
+#define CONFIG_ENV_OVERWRITE     1
+#define CONFIG_SYS_HUSH_PARSER			1
+#define CONFIG_SOURCE			1
+
+
+/*
+ * Command line configuration.
+ */
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_CONSOLE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_SETGETDCR
+#define CONFIG_CMD_SOURCE
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_VENDOREX
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * how many time to fail & restart a net-TFTP before giving up & resetting
+ * the board hoping that a reset of net interface might help..
+ */
+#define CONFIG_NET_RESET 5
+
+/*
+ * bauds.  Just to make it compile; in our case, I read the base_baud
+ * from the DCR anyway, so its kinda-tied to the above ref. clock which in turn
+ * drives the system clock.
+ */
+#define CONFIG_SYS_BASE_BAUD       403225
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_CBSIZE	256				/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE			/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16				/* max number of command args	*/
+
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* where to load what we get from TFTP */
+#define CONFIG_SYS_EXTBDINFO		1		/* To use extended board_into (bd_t) */
+#define CONFIG_SYS_DRAM_TEST		1
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFC00000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+
+
+#define CONFIG_SYS_MONITOR_LEN		(192 * 1024)	/* Reserve 192 kB for Monitor	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	 1		/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	 64		/* max number of sectors on one chip	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT 120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500	/* Timeout for Flash Write (in ms)	*/
+
+/* BEG ENVIRONNEMENT FLASH: needs to be a whole FlashSector  */
+#define CONFIG_ENV_OFFSET		0x3c8000
+#define CONFIG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars */
+#define	CONFIG_ENV_SIZE		0x1000	 /* Total Size of Environment area	*/
+#define CONFIG_ENV_SECT_SIZE	0x10000	 /* see README - env sector total size	*/
+
+/* Memory tests: U-BOOT relocates itself to the top of Ram, so its at
+ * 32meg-(128k+some_malloc_space+copy-of-ENV sector)..
+ */
+#define CONFIG_SYS_SDRAM_SIZE		32		/* megs of ram */
+#define CONFIG_SYS_MEMTEST_START	0x2000  /* memtest works from the end of */
+									/* the exception vector table */
+									/* to the end of the DRAM  */
+									/* less monitor and malloc area */
+#define CONFIG_SYS_STACK_USAGE		0x10000 /* Reserve 64k for the stack usage */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* 128k for malloc space */
+#define CONFIG_SYS_MEM_END_USAGE	( CONFIG_SYS_MONITOR_LEN \
+				+ CONFIG_SYS_MALLOC_LEN \
+				+ CONFIG_ENV_SECT_SIZE \
+				+ CONFIG_SYS_STACK_USAGE )
+
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 - CONFIG_SYS_MEM_END_USAGE)
+/* END ENVIRONNEMENT FLASH */
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	CONFIG_SYS_FLASH_BASE	/* FLASH bank #0	*/
+
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in OnChipMem )
+ */
+#if 1
+/* On Chip Memory location */
+#define CONFIG_SYS_TEMP_STACK_OCM	1
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF0000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
+#else
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF0000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR	/* inside of On Chip SRAM    */
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE	/* Size of On Chip SRAM	     */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+#endif
+
+/*-----------------------------------------------------------------------
+ * Definitions for Serial Presence Detect EEPROM address
+ */
+#define EEPROM_WRITE_ADDRESS 0xA0
+#define EEPROM_READ_ADDRESS  0xA1
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/CU824.h b/qemu/roms/u-boot/include/configs/CU824.h
new file mode 100644
index 000000000..dc98a560c
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/CU824.h
@@ -0,0 +1,286 @@
+/*
+ * (C) Copyright 2001-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ *
+ * Configuration settings for the CU824 board.
+ *
+ */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC8240		1
+#define CONFIG_CU824		1
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
+
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		9600
+
+#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
+
+#define CONFIG_BOOTCOMMAND	"bootm FE020000"	/* autoboot command	*/
+#define CONFIG_BOOTDELAY	5
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+
+#if 1
+#define	CONFIG_SYS_HUSH_PARSER		1	/* use "hush" command parser	*/
+#endif
+
+/* Print Buffer Size
+ */
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_LOAD_ADDR	0x00100000	/* Default load address		*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE	    0x00000000
+#define CONFIG_SYS_FLASH_BASE	    0xFF000000
+
+#define CONFIG_SYS_RESET_ADDRESS   0xFFF00100
+
+#define CONFIG_SYS_EUMB_ADDR	    0xFCE00000
+
+#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN	    (128 << 10) /* Reserve 128 kB for malloc()	*/
+
+#define CONFIG_SYS_MEMTEST_START   0x00004000	/* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END	    0x02000000	/* 0 ... 32 MB in DRAM		*/
+
+	/* Maximum amount of RAM.
+	 */
+#define CONFIG_SYS_MAX_RAM_SIZE    0x10000000
+
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+#undef CONFIG_SYS_RAMBOOT
+#else
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area
+ */
+
+#define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE      0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+
+#define CONFIG_SYS_NS16550_REG_SIZE	4
+
+#define CONFIG_SYS_NS16550_CLK		(14745600 / 2)
+
+#define CONFIG_SYS_NS16550_COM1	0xFE800080
+#define CONFIG_SYS_NS16550_COM2	0xFE8000C0
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ * For the detail description refer to the MPC8240 user's manual.
+ */
+
+#define CONFIG_SYS_CLK_FREQ  33000000
+
+	/* Bit-field values for MCCR1.
+	 */
+#define CONFIG_SYS_ROMNAL	    0
+#define CONFIG_SYS_ROMFAL	    7
+
+	/* Bit-field values for MCCR2.
+	 */
+#define CONFIG_SYS_REFINT	    430	    /* Refresh interval			*/
+
+	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
+	 */
+#define CONFIG_SYS_BSTOPRE	    192
+
+	/* Bit-field values for MCCR3.
+	 */
+#define CONFIG_SYS_REFREC	    2	    /* Refresh to activate interval	*/
+#define CONFIG_SYS_RDLAT	    3	    /* Data latancy from read command	*/
+
+	/* Bit-field values for MCCR4.
+	 */
+#define CONFIG_SYS_PRETOACT	    2	    /* Precharge to activate interval	*/
+#define CONFIG_SYS_ACTTOPRE	    5	    /* Activate to Precharge interval	*/
+#define CONFIG_SYS_SDMODE_CAS_LAT  2	    /* SDMODE CAS latancy		*/
+#define CONFIG_SYS_SDMODE_WRAP	    0	    /* SDMODE wrap type			*/
+#define CONFIG_SYS_SDMODE_BURSTLEN 2	    /* SDMODE Burst length		*/
+#define CONFIG_SYS_ACTORW	    2
+#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
+
+/* Memory bank settings.
+ * Only bits 20-29 are actually used from these vales to set the
+ * start/end addresses. The upper two bits will always be 0, and the lower
+ * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
+ * address. Refer to the MPC8240 book.
+ */
+
+#define CONFIG_SYS_BANK0_START	    0x00000000
+#define CONFIG_SYS_BANK0_END	    (CONFIG_SYS_MAX_RAM_SIZE - 1)
+#define CONFIG_SYS_BANK0_ENABLE    1
+#define CONFIG_SYS_BANK1_START	    0x3ff00000
+#define CONFIG_SYS_BANK1_END	    0x3fffffff
+#define CONFIG_SYS_BANK1_ENABLE    0
+#define CONFIG_SYS_BANK2_START	    0x3ff00000
+#define CONFIG_SYS_BANK2_END	    0x3fffffff
+#define CONFIG_SYS_BANK2_ENABLE    0
+#define CONFIG_SYS_BANK3_START	    0x3ff00000
+#define CONFIG_SYS_BANK3_END	    0x3fffffff
+#define CONFIG_SYS_BANK3_ENABLE    0
+#define CONFIG_SYS_BANK4_START	    0x3ff00000
+#define CONFIG_SYS_BANK4_END	    0x3fffffff
+#define CONFIG_SYS_BANK4_ENABLE    0
+#define CONFIG_SYS_BANK5_START	    0x3ff00000
+#define CONFIG_SYS_BANK5_END	    0x3fffffff
+#define CONFIG_SYS_BANK5_ENABLE    0
+#define CONFIG_SYS_BANK6_START	    0x3ff00000
+#define CONFIG_SYS_BANK6_END	    0x3fffffff
+#define CONFIG_SYS_BANK6_ENABLE    0
+#define CONFIG_SYS_BANK7_START	    0x3ff00000
+#define CONFIG_SYS_BANK7_END	    0x3fffffff
+#define CONFIG_SYS_BANK7_ENABLE    0
+
+#define CONFIG_SYS_ODCR	    0xff
+
+#define CONFIG_SYS_IBAT0L  (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U  (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT3L  (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U  (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_DBAT0L  CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U  CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L  CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U  CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L  CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U  CONFIG_SYS_IBAT3U
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* Max number of flash banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	39	/* Max number of sectors in one bank	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+	/* Warining: environment is not EMBEDDED in the U-Boot code.
+	 * It's stored in flash separately.
+	 */
+#define CONFIG_ENV_IS_IN_FLASH	    1
+#if 0
+#define CONFIG_ENV_ADDR		0xFF008000
+#define CONFIG_ENV_SIZE		0x8000	/* Size of the Environment Sector	*/
+#else
+#define CONFIG_ENV_ADDR		0xFFFC0000
+#define CONFIG_ENV_SIZE		0x4000	/* Size of the Environment		*/
+#define CONFIG_ENV_OFFSET		0	/* starting right at the beginning	*/
+#define CONFIG_ENV_SECT_SIZE	0x40000 /* Size of the Environment Sector	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	32
+#if defined(CONFIG_CMD_KGDB)
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_PCI			/* include pci support			*/
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#undef CONFIG_PCI_PNP
+
+
+#define CONFIG_TULIP
+#define CONFIG_TULIP_USE_IO
+
+#define CONFIG_SYS_ETH_DEV_FN	     0x7800
+#define CONFIG_SYS_ETH_IOBASE	     0x00104000
+
+#define CONFIG_EEPRO100
+#define CONFIG_SYS_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
+#define PCI_ENET0_IOADDR	0x00104000
+#define PCI_ENET0_MEMADDR	0x80000000
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/DB64360.h b/qemu/roms/u-boot/include/configs/DB64360.h
new file mode 100644
index 000000000..b77c8b289
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/DB64360.h
@@ -0,0 +1,579 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+/*************************************************************************
+ * (c) 2002 Datentechnik AG - Project: Dino
+ *
+ *
+ * $Id: DB64360.h,v 1.3 2003/04/26 04:58:13 brad Exp $
+ *
+  ************************************************************************/
+
+/*************************************************************************
+ *
+ * History:
+ *
+ *	$Log: DB64360.h,v $
+ *	Revision 1.3  2003/04/26 04:58:13  brad
+ *	Cosmetic changes and compiler warning cleanups
+ *
+ *	Revision 1.2  2003/04/23 15:48:15  ingo
+ *	mem. map output added
+ *
+ *	Revision 1.1  2003/04/17 09:31:42  ias
+ *	keymile changes 17_04_2003
+ *
+ *	Revision 1.10  2003/03/06 12:25:04  ias
+ *	750 FX CPU HID settings updated
+ *
+ *	Revision 1.9  2003/03/03 16:14:36  ias
+ *	cleanup compiler warnings of printf fuctions
+ *
+ *	Revision 1.8  2003/03/03 15:11:44  ias
+ *	Marvell MPSC-UART is working
+ *
+ *	Revision 1.7  2003/02/26 12:15:45  ssu
+ *	adapted default parameters to new board flash address
+ *
+ *	Revision 1.6  2003/02/25 14:55:42  ssu
+ *	changed default environment parameters
+ *
+ *	Revision 1.5  2003/02/21 17:14:23  ias
+ *	added extended SPD handling
+ *
+ *	Revision 1.4  2003/01/14 09:16:08  ias
+ *	PPCBoot for Marvel Beta 0.9
+ *
+ *	Revision 1.3  2002/12/03 13:56:26  ias
+ *	Environment in flash support added
+ *
+ *	Revision 1.2  2002/11/29 16:53:29  ias
+ *	Flash support for STM added
+ *
+ *	Revision 1.1  2002/11/29 13:36:31  ias
+ *	Revision 0.1 of PPCBOOT (1.1.5) for Marvell DB64360 IBM750FX Board
+ *	- working DDRRAM (only 32MByte of 128MB Modul)
+ *	- working I2C Driver for SPD EEPROM read
+ *	- working DUART 16650 for Serial Console
+ *	- working "console"
+ *
+ *
+ *
+ ************************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* This define must be before the core.h include */
+#define CONFIG_DB64360		1	/* this is an DB64360 board	*/
+
+#ifndef __ASSEMBLY__
+#include "../board/Marvell/include/core.h"
+#endif
+
+/*-----------------------------------------------------*/
+/*    #include "../board/db64360/local.h"	      */
+#ifndef __LOCAL_H
+#define __LOCAL_H
+
+/* first ethernet */
+#define CONFIG_ETHADDR		64:36:00:00:00:01
+											     /* next two ethernet hwaddrs */
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR		64:36:00:00:00:02
+/* in the atlantis 64360 we have only 2 ETH port on the board,
+if we use PCI it has its own MAC addr */
+
+#define CONFIG_ENV_OVERWRITE
+#endif	/* __CONFIG_H */
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_74xx			/* we have a 750FX (override local.h) */
+
+#define CONFIG_DB64360		1	/* this is an DB64360 board	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xfff00000
+
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115000	*/
+/*ronen - we don't use the global CONFIG_ECC, since in the global ecc we initialize the
+	DRAM for ECC in the phase we are relocating to it, which isn't so sufficient.
+	so we will define our ECC CONFIG and initilize the DRAM for ECC in the DRAM initialization phase,
+	see sdram_init.c   */
+#undef CONFIG_ECC	 /* enable ECC support */
+#define CONFIG_MV64360_ECC
+
+/* which initialization functions to call for this board */
+#define CONFIG_MISC_INIT_R     /* initialize the icache L1 */
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_SYS_BOARD_NAME		"DB64360"
+#define CONFIG_IDENT_STRING	"Marvell DB64360 (1.1)"
+
+/*#define CONFIG_SYS_HUSH_PARSER */
+#undef CONFIG_SYS_HUSH_PARSER
+
+
+/*
+ * The following defines let you select what serial you want to use
+ * for your console driver.
+ *
+ * what to do:
+ * to use the DUART, undef CONFIG_MPSC.	 If you have hacked a serial
+ * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1
+ * to 0 below.
+ *
+ * to use the MPSC, #define CONFIG_MPSC.  If you have wired up another
+ * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
+ */
+
+#define CONFIG_MPSC_PORT	0
+
+/* to change the default ethernet port, use this define (options: 0, 1, 2) */
+#define MV_ETH_DEVS 2
+
+/* #undef CONFIG_ETHER_PORT_MII	 */
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	3	/* autoboot after 5 seconds	*/
+#endif
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+
+#undef	CONFIG_BOOTARGS
+/*#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" */
+
+/* ronen - autoboot using tftp */
+#if (CONFIG_BOOTDELAY >= 0)
+#define CONFIG_BOOTCOMMAND	"tftpboot 0x400000 uImage;\
+ setenv bootargs ${bootargs} ${bootargs_root} nfsroot=${serverip}:${rootpath} \
+ ip=${ipaddr}:${serverip}${bootargs_end};  bootm 0x400000; "
+
+#define CONFIG_BOOTARGS "console=ttyS0,115200"
+
+#endif
+
+/* ronen - the u-boot.bin should be ~0x30000 bytes */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+     "burn_uboot_sep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF4ffff; \
+cp.b 100000 FFF00000 0x40000;protect on 1:0-4;\0" \
+      "burn_uboot_dep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF7ffff; \
+cp.b 100000 FFF00000 0x40000;protect on 1:0-7;\0" \
+      "bootargs_root=root=/dev/nfs rw\0" \
+      "bootargs_end=:::DB64360:eth0:none \0"\
+      "ethprime=mv_enet0\0"\
+      "standalone=fsload 0x400000 uImage;setenv bootargs ${bootargs} root=/dev/mtdblock/0 rw \
+ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
+
+/* --------------------------------------------------------------------------------------------------------------- */
+/* New bootcommands for Marvell DB64360 c 2002 Ingo Assmus */
+
+#define CONFIG_IPADDR		10.2.40.90
+
+#define CONFIG_SERIAL		"No. 1"
+#define CONFIG_SERVERIP		10.2.1.126
+#define CONFIG_ROOTPATH		"/mnt/yellow_dog_mini"
+
+
+#define CONFIG_TESTDRAMDATA	y
+#define CONFIG_TESTDRAMADDRESS	n
+#define CONFIG_TESETDRAMWALK	n
+
+/* --------------------------------------------------------------------------------------------------------------- */
+
+#define CONFIG_LOADS_ECHO	0	/* echo off for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE		/* allow baudrate changes	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+#undef	CONFIG_ALTIVEC			/* undef to disable		*/
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_CMD_MTDPARTS
+#define CONFIG_JFFS2_DEV		"nor1"
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET	0x00000000
+
+/* mtdparts command line support */
+
+/* Use first bank for JFFS2, second bank contains U-Boot.
+ *
+ * Note: fake mtd_id's used, no linux mtd map file.
+ */
+/*
+#define CONFIG_CMD_MTDPARTS
+#define MTDIDS_DEFAULT		"nor1=db64360-1"
+#define MTDPARTS_DEFAULT	"mtdparts=db64360-1:-(jffs2)"
+*/
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_SPEED	40000		/* I2C speed default */
+
+/* #define CONFIG_SYS_GT_DUAL_CPU	 also for JTAG even with one cpu */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+/*#define CONFIG_SYS_MEMTEST_START	0x00400000	 memtest works on	*/
+/*#define CONFIG_SYS_MEMTEST_END		0x00C00000	 4 ... 12 MB in DRAM	*/
+/*#define CONFIG_SYS_MEMTEST_END		0x07c00000	 4 ... 124 MB in DRAM	*/
+
+/*
+#define CONFIG_SYS_DRAM_TEST
+ * DRAM tests
+ *   CONFIG_SYS_DRAM_TEST - enables the following tests.
+ *
+ *   CONFIG_SYS_DRAM_TEST_DATA - Enables test for shorted or open data lines
+ *			  Environment variable 'test_dram_data' must be
+ *			  set to 'y'.
+ *   CONFIG_SYS_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
+ *			  addressable. Environment variable
+ *			  'test_dram_address' must be set to 'y'.
+ *   CONFIG_SYS_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
+ *			  This test takes about 6 minutes to test 64 MB.
+ *			  Environment variable 'test_dram_walk' must be
+ *			  set to 'y'.
+ */
+#define CONFIG_SYS_DRAM_TEST
+#if defined(CONFIG_SYS_DRAM_TEST)
+#define CONFIG_SYS_MEMTEST_START		0x00400000	/* memtest works on	*/
+/* #define CONFIG_SYS_MEMTEST_END		0x00C00000	 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_END		0x07c00000	/* 4 ... 124 MB in DRAM */
+#define CONFIG_SYS_DRAM_TEST_DATA
+#define CONFIG_SYS_DRAM_TEST_ADDRESS
+#define CONFIG_SYS_DRAM_TEST_WALK
+#endif /* CONFIG_SYS_DRAM_TEST */
+
+#undef CONFIG_DISPLAY_MEMMAP		/* at the end of the bootprocess show the memory map */
+#undef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT	/* show SPD content during boot */
+
+#define CONFIG_SYS_LOAD_ADDR		0x00400000	/* default load address */
+
+/*ronen - this the Sys clock (cpu bus,internal dram and SDRAM) */
+#define CONFIG_SYS_BUS_CLK		133000000	/* 133 MHz (CPU = 5*Bus = 666MHz)		*/
+
+#define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP 7 /* define the SDRAM cycle count */
+#define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP 50 /* for 400MHZ -> 5.0 ns, for 133MHZ -> 7.50 ns */
+
+/*ronen - this is the Tclk (MV64360 core) */
+#define CONFIG_SYS_TCLK		133000000
+
+
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#define CONFIG_SYS_750FX_HID0		0x8000c084
+#define CONFIG_SYS_750FX_HID1		0x54800000
+#define CONFIG_SYS_750FX_HID2		0x00000000
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area
+ */
+
+/*
+ * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS
+ * To an unused memory region. The stack will remain in cache until RAM
+ * is initialized
+*/
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000 /* unused memory region */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+#define RELOCATE_INTERNAL_RAM_ADDR
+#ifdef RELOCATE_INTERNAL_RAM_ADDR
+	#define CONFIG_SYS_INTERNAL_RAM_ADDR	0xf8000000
+#endif
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+/* Dummies for BAT 4-7 */
+#define CONFIG_SYS_SDRAM1_BASE		0x10000000	/* each 256 MByte */
+#define CONFIG_SYS_SDRAM2_BASE		0x20000000
+#define CONFIG_SYS_SDRAM3_BASE		0x30000000
+#define CONFIG_SYS_SDRAM4_BASE		0x40000000
+#define CONFIG_SYS_FLASH_BASE			0xfff00000
+
+#define CONFIG_SYS_DFL_BOOTCS_BASE	0xff800000
+#define CONFIG_VERY_BIG_RAM		/* we will use up to 256M memory for cause we are short of BATS*/
+
+#define BRIDGE_REG_BASE_BOOTM 0xfbe00000 /* this paramaters are used when booting the linux kernel */
+#define UART_BASE_BOOTM	      0xfbb00000 /* in order to be sync with the kernel parameters. */
+#define PCI0_IO_BASE_BOOTM    0xfd000000
+
+#define CONFIG_SYS_RESET_ADDRESS		0xfff00100
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc */
+
+/* areas to map different things with the GT in physical space */
+#define CONFIG_SYS_DRAM_BANKS		4
+
+/* What to put in the bats. */
+#define CONFIG_SYS_MISC_REGION_BASE	0xf0000000
+
+/* Peripheral Device section */
+
+/*******************************************************/
+/* We have on the db64360 Board :		   */
+/* GT-Chipset Register Area				*/
+/* GT-Chipset internal SRAM 256k		    */
+/* SRAM on external device module		   */
+/* Real time clock on external device module	  */
+/* dobble UART on external device module	 */
+/* Data flash on external device module		    */
+/* Boot flash on external device module		    */
+/*******************************************************/
+#define CONFIG_SYS_DFL_GT_REGS		0x14000000				/* boot time GT_REGS */
+#define	 CONFIG_SYS_DB64360_RESET_ADDR 0x14000000				/* After power on Reset the DB64360 is here */
+
+/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+#define CONFIG_SYS_GT_REGS		0xf1000000				/* GT Registers will be mapped here */
+#define CONFIG_SYS_DEV_BASE		0xfc000000				/* GT Devices CS start here */
+
+#define CONFIG_SYS_DEV0_SPACE		CONFIG_SYS_DEV_BASE				/* DEV_CS0 device modul sram */
+#define CONFIG_SYS_DEV1_SPACE		(CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE)	/* DEV_CS1 device modul real time clock (rtc) */
+#define CONFIG_SYS_DEV2_SPACE		(CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE)	/* DEV_CS2 device modul doubel uart (duart) */
+#define CONFIG_SYS_DEV3_SPACE		(CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE)	/* DEV_CS3 device modul large flash */
+
+#define CONFIG_SYS_DEV0_SIZE		 _8M					/* db64360 sram	 @ 0xfc00.0000 */
+#define CONFIG_SYS_DEV1_SIZE		 _8M					/* db64360 rtc	 @ 0xfc80.0000 */
+#define CONFIG_SYS_DEV2_SIZE		_16M					/* db64360 duart @ 0xfd00.0000 */
+#define CONFIG_SYS_DEV3_SIZE		_16M					/* db64360 flash @ 0xfe00.0000 */
+/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+
+/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */
+#define CONFIG_SYS_DEV0_PAR		0x8FEFFFFF				/* 32Bit  sram */
+#define CONFIG_SYS_DEV1_PAR		0x8FCFFFFF				/* 8Bit	 rtc */
+#define CONFIG_SYS_DEV2_PAR		0x8FCFFFFF				/* 8Bit duart */
+#define CONFIG_SYS_8BIT_BOOT_PAR	0x8FCFFFFF				/* 8Bit flash */
+#define CONFIG_SYS_32BIT_BOOT_PAR	0x8FEFFFFF				/* 32Bit flash */
+
+	/*   c	  4    a      8	    2	  4    1      c		*/
+	/* 33 22|2222|22 22|111 1|11 11|1 1  |	  |		*/
+	/* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210	*/
+	/* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100	*/
+	/*  3| 0|.... ..| 2| 4 |  0 |  4 |  8  |  3  | 4	*/
+
+
+/* ronen - update MPP Control MV64360*/
+#define CONFIG_SYS_MPP_CONTROL_0	0x02222222
+#define CONFIG_SYS_MPP_CONTROL_1	0x11333011
+#define CONFIG_SYS_MPP_CONTROL_2	0x40431111
+#define CONFIG_SYS_MPP_CONTROL_3	0x00000044
+
+/*# define CONFIG_SYS_SERIAL_PORT_MUX	0x00000102	 0=hiZ	1=MPSC0 2=ETH 0 and 2 RMII */
+
+
+# define CONFIG_SYS_GPP_LEVEL_CONTROL	0x2c600000	/* 1111 1001 0000 1111 1100 0000 0000 0000*/
+							/* gpp[31]		gpp[30]		gpp[29]		gpp[28] */
+				/* gpp[27]			gpp[24]*/
+							/* gpp[19:14] */
+
+/* setup new config_value for MV64360 DDR-RAM !! */
+# define CONFIG_SYS_SDRAM_CONFIG	0x58200400	/* 0x1400  copied from Dink32 bzw. VxWorks*/
+
+#define CONFIG_SYS_DUART_IO		CONFIG_SYS_DEV2_SPACE
+#define CONFIG_SYS_DUART_CHAN		1		/* channel to use for console */
+#define CONFIG_SYS_INIT_CHAN1
+#define CONFIG_SYS_INIT_CHAN2
+
+#define SRAM_BASE		CONFIG_SYS_DEV0_SPACE
+#define SRAM_SIZE		0x00100000		/* 1 MB of sram */
+
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+
+#define PCI_HOST_ADAPTER 0		/* configure ar pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST PCI_HOST_FORCE	/* select pci host function	*/
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+#define CONFIG_EEPRO100			/* ronen - Support for Intel 82557/82559/82559ER chips */
+
+/* PCI MEMORY MAP section */
+#define CONFIG_SYS_PCI0_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI0_MEM_SIZE	_128M
+#define CONFIG_SYS_PCI1_MEM_BASE	0x88000000
+#define CONFIG_SYS_PCI1_MEM_SIZE	_128M
+
+#define CONFIG_SYS_PCI0_0_MEM_SPACE	(CONFIG_SYS_PCI0_MEM_BASE)
+#define CONFIG_SYS_PCI1_0_MEM_SPACE	(CONFIG_SYS_PCI1_MEM_BASE)
+
+/* PCI I/O MAP section */
+#define CONFIG_SYS_PCI0_IO_BASE	0xfa000000
+#define CONFIG_SYS_PCI0_IO_SIZE	_16M
+#define CONFIG_SYS_PCI1_IO_BASE	0xfb000000
+#define CONFIG_SYS_PCI1_IO_SIZE	_16M
+
+#define CONFIG_SYS_PCI0_IO_SPACE	(CONFIG_SYS_PCI0_IO_BASE)
+#define CONFIG_SYS_PCI0_IO_SPACE_PCI	(CONFIG_SYS_PCI0_IO_BASE) /* ronen we want phy=bus 0x00000000 */
+#define CONFIG_SYS_PCI1_IO_SPACE	(CONFIG_SYS_PCI1_IO_BASE)
+#define CONFIG_SYS_PCI1_IO_SPACE_PCI	(CONFIG_SYS_PCI1_IO_BASE) /* ronen we want phy=bus 0x00000000 */
+
+#if defined (CONFIG_750CX)
+#define CONFIG_SYS_PCI_IDSEL 0x0
+#else
+#define CONFIG_SYS_PCI_IDSEL 0x30
+#endif
+/*----------------------------------------------------------------------
+ * Initial BAT mappings
+ */
+
+/* NOTES:
+ * 1) GUARDED and WRITE_THRU not allowed in IBATS
+ * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
+ */
+
+/* SDRAM */
+#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
+
+/* init ram */
+#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
+
+/* PCI0, PCI1 in one BAT */
+#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
+#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
+#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* GT regs, bootrom, all the devices, PCI I/O */
+#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
+#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
+#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
+
+/* I2C addresses for the two DIMM SPD chips */
+#define DIMM0_I2C_ADDR	0x56
+#define DIMM1_I2C_ADDR	0x54
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8<<20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	67	/* max number of sectors on one chip */
+
+#define CONFIG_SYS_EXTRA_FLASH_DEVICE	DEVICE3 /* extra flash at device 3 */
+#define CONFIG_SYS_EXTRA_FLASH_WIDTH	4	/* 32 bit */
+#define CONFIG_SYS_BOOT_FLASH_WIDTH	1	/* 8 bit */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
+#define CONFIG_SYS_FLASH_LOCK_TOUT	500	/* Timeout for Flash Lock (in ms) */
+#define CONFIG_SYS_FLASH_CFI		1
+
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_SIZE		0x1000	/* Total Size of Environment Sector */
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#define CONFIG_ENV_ADDR	      0xFFF78000 /* Marvell 8-Bit Bootflash last sector */
+/* #define CONFIG_ENV_ADDR	   (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For all MPC74xx CPUs		 */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * L2CR setup -- make sure this is right for your board!
+ * look in include/mpc74xx.h for the defines used here
+ */
+
+#define CONFIG_SYS_L2
+
+
+#if defined (CONFIG_750CX) || defined (CONFIG_750FX)
+#define L2_INIT 0
+#else
+
+#define L2_INIT		0
+/*
+#define L2_INIT		(L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
+			L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
+*/
+#endif
+
+#define L2_ENABLE	(L2_INIT | L2CR_L2E)
+
+#define CONFIG_SYS_BOARD_ASM_INIT	1
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/DB64460.h b/qemu/roms/u-boot/include/configs/DB64460.h
new file mode 100644
index 000000000..abc443499
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/DB64460.h
@@ -0,0 +1,517 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* This define must be before the core.h include */
+#define CONFIG_DB64460		1	/* this is an DB64460 board	*/
+
+#ifndef __ASSEMBLY__
+#include "../board/Marvell/include/core.h"
+#endif
+
+/*-----------------------------------------------------*/
+/*    #include "../board/db64460/local.h"	      */
+#ifndef __LOCAL_H
+#define __LOCAL_H
+
+#define CONFIG_ETHADDR		64:46:00:00:00:01
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR		64:46:00:00:00:02
+#define CONFIG_HAS_ETH2
+#define CONFIG_ETH2ADDR		64:46:00:00:00:03
+
+#define CONFIG_ENV_OVERWRITE
+#endif	/* __CONFIG_H */
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_74xx			/* we have a 750FX (override local.h) */
+
+#define CONFIG_DB64460		1	/* this is an DB64460 board	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xfff00000
+
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115000	*/
+/*ronen - we don't use the global CONFIG_ECC, since in the global ecc we initialize the
+	DRAM for ECC in the phase we are relocating to it, which isn't so sufficient.
+	so we will define our ECC CONFIG and initilize the DRAM for ECC in the DRAM initialization phase,
+	see sdram_init.c   */
+#undef CONFIG_ECC	 /* enable ECC support */
+#define CONFIG_MV64460_ECC
+
+/* which initialization functions to call for this board */
+#define CONFIG_MISC_INIT_R     /* initialize the icache L1 */
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_SYS_BOARD_NAME		"DB64460"
+#define CONFIG_IDENT_STRING	"Marvell DB64460 (1.0)"
+
+/*#define CONFIG_SYS_HUSH_PARSER */
+#undef CONFIG_SYS_HUSH_PARSER
+
+
+/*
+ * The following defines let you select what serial you want to use
+ * for your console driver.
+ *
+ * what to do:
+ * to use the DUART, undef CONFIG_MPSC.	 If you have hacked a serial
+ * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1
+ * to 0 below.
+ *
+ * to use the MPSC, #define CONFIG_MPSC.  If you have wired up another
+ * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
+ */
+
+#define CONFIG_MPSC_PORT	0
+
+/* to change the default ethernet port, use this define (options: 0, 1, 2) */
+#define MV_ETH_DEVS 3
+
+/* #undef CONFIG_ETHER_PORT_MII	 */
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	3	/* autoboot after 5 seconds	*/
+#endif
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+
+#undef	CONFIG_BOOTARGS
+/*#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" */
+
+/* ronen - autoboot using tftp */
+#if (CONFIG_BOOTDELAY >= 0)
+#define CONFIG_BOOTCOMMAND	"tftpboot 0x400000 uImage;\
+ setenv bootargs ${bootargs} ${bootargs_root} nfsroot=${serverip}:${rootpath} \
+ ip=${ipaddr}:${serverip}${bootargs_end};  bootm 0x400000; "
+
+#define CONFIG_BOOTARGS "console=ttyS0,115200"
+
+#endif
+
+/* ronen - the u-boot.bin should be ~0x30000 bytes */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+     "burn_uboot_sep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF4ffff; \
+cp.b 100000 FFF00000 0x40000;protect on 1:0-4;\0" \
+      "burn_uboot_dep= tftp 100000 u-boot.bin;protect off all;era FFF00000 FFF7ffff; \
+cp.b 100000 FFF00000 0x40000;protect on 1:0-7;\0" \
+      "bootargs_root=root=/dev/nfs rw\0" \
+      "bootargs_end=:::DB64460:eth0:none \0"\
+      "ethprime=mv_enet0\0"\
+      "standalone=fsload 0x400000 uImage;setenv bootargs ${bootargs} root=/dev/mtdblock/0 rw \
+ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
+
+/* --------------------------------------------------------------------------------------------------------------- */
+/* New bootcommands for Marvell DB64460 c 2002 Ingo Assmus */
+
+#define CONFIG_IPADDR		10.2.40.90
+
+#define CONFIG_SERIAL		"No. 1"
+#define CONFIG_SERVERIP		10.2.1.126
+#define CONFIG_ROOTPATH		"/mnt/yellow_dog_mini"
+
+
+#define CONFIG_TESTDRAMDATA	y
+#define CONFIG_TESTDRAMADDRESS	n
+#define CONFIG_TESETDRAMWALK	n
+
+/* --------------------------------------------------------------------------------------------------------------- */
+
+#define CONFIG_LOADS_ECHO	0	/* echo off for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE		/* allow baudrate changes	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+#undef	CONFIG_ALTIVEC			/* undef to disable		*/
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_CMD_MTDPARTS
+#define CONFIG_JFFS2_DEV		"nor1"
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET	0x00000000
+
+/* mtdparts command line support */
+
+/* Use first bank for JFFS2, second bank contains U-Boot.
+ *
+ * Note: fake mtd_id's used, no linux mtd map file.
+ */
+/*
+#define CONFIG_CMD_MTDPARTS
+#define MTDIDS_DEFAULT		"nor1=db64460-1"
+#define MTDPARTS_DEFAULT	"mtdparts=db64460-1:-(jffs2)"
+*/
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_SPEED	40000		/* I2C speed default */
+
+/* #define CONFIG_SYS_GT_DUAL_CPU	 also for JTAG even with one cpu */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+/*#define CONFIG_SYS_MEMTEST_START	0x00400000	 memtest works on	*/
+/*#define CONFIG_SYS_MEMTEST_END		0x00C00000	 4 ... 12 MB in DRAM	*/
+/*#define CONFIG_SYS_MEMTEST_END		0x07c00000	 4 ... 124 MB in DRAM	*/
+
+/*
+#define CONFIG_SYS_DRAM_TEST
+ * DRAM tests
+ *   CONFIG_SYS_DRAM_TEST - enables the following tests.
+ *
+ *   CONFIG_SYS_DRAM_TEST_DATA - Enables test for shorted or open data lines
+ *			  Environment variable 'test_dram_data' must be
+ *			  set to 'y'.
+ *   CONFIG_SYS_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
+ *			  addressable. Environment variable
+ *			  'test_dram_address' must be set to 'y'.
+ *   CONFIG_SYS_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
+ *			  This test takes about 6 minutes to test 64 MB.
+ *			  Environment variable 'test_dram_walk' must be
+ *			  set to 'y'.
+ */
+#define CONFIG_SYS_DRAM_TEST
+#if defined(CONFIG_SYS_DRAM_TEST)
+#define CONFIG_SYS_MEMTEST_START		0x00400000	/* memtest works on	*/
+/* #define CONFIG_SYS_MEMTEST_END		0x00C00000	 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_END		0x07c00000	/* 4 ... 124 MB in DRAM */
+#define CONFIG_SYS_DRAM_TEST_DATA
+#define CONFIG_SYS_DRAM_TEST_ADDRESS
+#define CONFIG_SYS_DRAM_TEST_WALK
+#endif /* CONFIG_SYS_DRAM_TEST */
+
+#undef CONFIG_DISPLAY_MEMMAP		/* at the end of the bootprocess show the memory map */
+#undef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT	/* show SPD content during boot */
+
+#define CONFIG_SYS_LOAD_ADDR		0x00400000	/* default load address */
+
+/*ronen - this the Sys clock (cpu bus,internal dram and SDRAM) */
+#define CONFIG_SYS_BUS_CLK		133000000	/* 133 MHz (CPU = 5*Bus = 666MHz)		*/
+
+#define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP 7 /* define the SDRAM cycle count */
+#define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP 50 /* for 200MHZ -> 5.0 ns, 166MHZ -> 6.0, 133MHZ -> 7.50 ns */
+
+/*ronen - this is the Tclk (MV64460 core) */
+#define CONFIG_SYS_TCLK		133000000
+
+
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#define CONFIG_SYS_750FX_HID0		0x8000c084
+#define CONFIG_SYS_750FX_HID1		0x54800000
+#define CONFIG_SYS_750FX_HID2		0x00000000
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area
+ */
+
+/*
+ * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS
+ * To an unused memory region. The stack will remain in cache until RAM
+ * is initialized
+*/
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000 /* unused memory region */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+#define RELOCATE_INTERNAL_RAM_ADDR
+#ifdef RELOCATE_INTERNAL_RAM_ADDR
+	#define CONFIG_SYS_INTERNAL_RAM_ADDR	0xf8000000
+#endif
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+/* Dummies for BAT 4-7 */
+#define CONFIG_SYS_SDRAM1_BASE		0x10000000	/* each 256 MByte */
+#define CONFIG_SYS_SDRAM2_BASE		0x20000000
+#define CONFIG_SYS_SDRAM3_BASE		0x30000000
+#define CONFIG_SYS_SDRAM4_BASE		0x40000000
+#define CONFIG_SYS_FLASH_BASE			0xfff00000
+
+#define CONFIG_SYS_DFL_BOOTCS_BASE	0xff800000
+#define CONFIG_VERY_BIG_RAM		/* we will use up to 256M memory for cause we are short of BATS*/
+
+#define BRIDGE_REG_BASE_BOOTM 0xfbe00000 /* this paramaters are used when booting the linux kernel */
+#define UART_BASE_BOOTM	      0xfbb00000 /* in order to be sync with the kernel parameters. */
+#define PCI0_IO_BASE_BOOTM    0xfd000000
+
+#define CONFIG_SYS_RESET_ADDRESS		0xfff00100
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc */
+
+/* areas to map different things with the GT in physical space */
+#define CONFIG_SYS_DRAM_BANKS		4
+
+/* What to put in the bats. */
+#define CONFIG_SYS_MISC_REGION_BASE	0xf0000000
+
+/* Peripheral Device section */
+
+/*******************************************************/
+/* We have on the db64460 Board :		   */
+/* GT-Chipset Register Area				*/
+/* GT-Chipset internal SRAM 256k		    */
+/* SRAM on external device module		   */
+/* Real time clock on external device module	  */
+/* dobble UART on external device module	 */
+/* Data flash on external device module		    */
+/* Boot flash on external device module		    */
+/*******************************************************/
+#define CONFIG_SYS_DFL_GT_REGS		0x14000000				/* boot time GT_REGS */
+#define	 CONFIG_SYS_DB64460_RESET_ADDR 0x14000000				/* After power on Reset the DB64460 is here */
+
+/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+#define CONFIG_SYS_GT_REGS		0xf1000000				/* GT Registers will be mapped here */
+#define CONFIG_SYS_DEV_BASE		0xfc000000				/* GT Devices CS start here */
+
+#define CONFIG_SYS_DEV0_SPACE		CONFIG_SYS_DEV_BASE				/* DEV_CS0 device modul sram */
+#define CONFIG_SYS_DEV1_SPACE		(CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE)	/* DEV_CS1 device modul real time clock (rtc) */
+#define CONFIG_SYS_DEV2_SPACE		(CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE)	/* DEV_CS2 device modul doubel uart (duart) */
+#define CONFIG_SYS_DEV3_SPACE		(CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE)	/* DEV_CS3 device modul large flash */
+
+#define CONFIG_SYS_DEV0_SIZE		 _8M					/* db64460 sram	 @ 0xfc00.0000 */
+#define CONFIG_SYS_DEV1_SIZE		 _8M					/* db64460 rtc	 @ 0xfc80.0000 */
+#define CONFIG_SYS_DEV2_SIZE		_16M					/* db64460 duart @ 0xfd00.0000 */
+#define CONFIG_SYS_DEV3_SIZE		_16M					/* db64460 flash @ 0xfe00.0000 */
+/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
+
+/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */
+#define CONFIG_SYS_DEV0_PAR		0x8FEFFFFF				/* 32Bit  sram */
+#define CONFIG_SYS_DEV1_PAR		0x8FCFFFFF				/* 8Bit	 rtc */
+#define CONFIG_SYS_DEV2_PAR		0x8FCFFFFF				/* 8Bit duart */
+#define CONFIG_SYS_8BIT_BOOT_PAR	0x8FCFFFFF				/* 8Bit flash */
+#define CONFIG_SYS_32BIT_BOOT_PAR	0x8FEFFFFF				/* 32Bit flash */
+
+	/*   c	  4    a      8	    2	  4    1      c		*/
+	/* 33 22|2222|22 22|111 1|11 11|1 1  |	  |		*/
+	/* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210	*/
+	/* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100	*/
+	/*  3| 0|.... ..| 2| 4 |  0 |  4 |  8  |  3  | 4	*/
+
+
+/* ronen - update MPP Control MV64460*/
+#define CONFIG_SYS_MPP_CONTROL_0	0x02222222
+#define CONFIG_SYS_MPP_CONTROL_1	0x11333011
+#define CONFIG_SYS_MPP_CONTROL_2	0x40431111
+#define CONFIG_SYS_MPP_CONTROL_3	0x00000044
+
+/*# define CONFIG_SYS_SERIAL_PORT_MUX	0x00000102	 0=hiZ	1=MPSC0 2=ETH 0 and 2 RMII */
+
+
+# define CONFIG_SYS_GPP_LEVEL_CONTROL	0x2c600000	/* 1111 1001 0000 1111 1100 0000 0000 0000*/
+							/* gpp[31]		gpp[30]		gpp[29]		gpp[28] */
+				/* gpp[27]			gpp[24]*/
+							/* gpp[19:14] */
+
+/* setup new config_value for MV64460 DDR-RAM !! */
+# define CONFIG_SYS_SDRAM_CONFIG	0x58200400	/* 0x1400  copied from Dink32 bzw. VxWorks*/
+
+#define CONFIG_SYS_DUART_IO		CONFIG_SYS_DEV2_SPACE
+#define CONFIG_SYS_DUART_CHAN		1		/* channel to use for console */
+#define CONFIG_SYS_INIT_CHAN1
+#define CONFIG_SYS_INIT_CHAN2
+
+#define SRAM_BASE		CONFIG_SYS_DEV0_SPACE
+#define SRAM_SIZE		0x00100000		/* 1 MB of sram */
+
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+
+#define PCI_HOST_ADAPTER 0		/* configure ar pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST PCI_HOST_FORCE	/* select pci host function	*/
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+#define CONFIG_EEPRO100			/* ronen - Support for Intel 82557/82559/82559ER chips */
+
+/* PCI MEMORY MAP section */
+#define CONFIG_SYS_PCI0_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI0_MEM_SIZE	_128M
+#define CONFIG_SYS_PCI1_MEM_BASE	0x88000000
+#define CONFIG_SYS_PCI1_MEM_SIZE	_128M
+
+#define CONFIG_SYS_PCI0_0_MEM_SPACE	(CONFIG_SYS_PCI0_MEM_BASE)
+#define CONFIG_SYS_PCI1_0_MEM_SPACE	(CONFIG_SYS_PCI1_MEM_BASE)
+
+/* PCI I/O MAP section */
+#define CONFIG_SYS_PCI0_IO_BASE	0xfa000000
+#define CONFIG_SYS_PCI0_IO_SIZE	_16M
+#define CONFIG_SYS_PCI1_IO_BASE	0xfb000000
+#define CONFIG_SYS_PCI1_IO_SIZE	_16M
+
+#define CONFIG_SYS_PCI0_IO_SPACE	(CONFIG_SYS_PCI0_IO_BASE)
+#define CONFIG_SYS_PCI0_IO_SPACE_PCI	(CONFIG_SYS_PCI0_IO_BASE) /* ronen we want phy=bus 0x00000000 */
+#define CONFIG_SYS_PCI1_IO_SPACE	(CONFIG_SYS_PCI1_IO_BASE)
+#define CONFIG_SYS_PCI1_IO_SPACE_PCI	(CONFIG_SYS_PCI1_IO_BASE) /* ronen we want phy=bus 0x00000000 */
+
+#if defined (CONFIG_750CX)
+#define CONFIG_SYS_PCI_IDSEL 0x0
+#else
+#define CONFIG_SYS_PCI_IDSEL 0x30
+#endif
+/*----------------------------------------------------------------------
+ * Initial BAT mappings
+ */
+
+/* NOTES:
+ * 1) GUARDED and WRITE_THRU not allowed in IBATS
+ * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
+ */
+
+/* SDRAM */
+#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
+
+/* init ram */
+#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
+
+/* PCI0, PCI1 in one BAT */
+#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
+#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
+#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* GT regs, bootrom, all the devices, PCI I/O */
+#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
+#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
+#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
+
+/* I2C addresses for the two DIMM SPD chips */
+#define DIMM0_I2C_ADDR	0x56
+#define DIMM1_I2C_ADDR	0x54
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8<<20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	67	/* max number of sectors on one chip */
+
+#define CONFIG_SYS_EXTRA_FLASH_DEVICE	DEVICE3 /* extra flash at device 3 */
+#define CONFIG_SYS_EXTRA_FLASH_WIDTH	4	/* 32 bit */
+#define CONFIG_SYS_BOOT_FLASH_WIDTH	1	/* 8 bit */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
+#define CONFIG_SYS_FLASH_LOCK_TOUT	500	/* Timeout for Flash Lock (in ms) */
+#define CONFIG_SYS_FLASH_CFI		1
+
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_SIZE		0x1000	/* Total Size of Environment Sector */
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#define CONFIG_ENV_ADDR	      0xFFF78000 /* Marvell 8-Bit Bootflash last sector */
+/* #define CONFIG_ENV_ADDR	   (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For all MPC74xx CPUs		 */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * L2CR setup -- make sure this is right for your board!
+ * look in include/mpc74xx.h for the defines used here
+ */
+
+#define CONFIG_SYS_L2
+
+
+#if defined (CONFIG_750CX) || defined (CONFIG_750FX)
+#define L2_INIT 0
+#else
+
+#define L2_INIT		0
+/*
+#define L2_INIT		(L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
+			L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
+*/
+#endif
+
+#define L2_ENABLE	(L2_INIT | L2CR_L2E)
+
+#define CONFIG_SYS_BOARD_ASM_INIT	1
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/DP405.h b/qemu/roms/u-boot/include/configs/DP405.h
new file mode 100644
index 000000000..68e4a7f40
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/DP405.h
@@ -0,0 +1,246 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_DP405		1	/* ...on a DP405 board		*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFD0000
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
+
+#define CONFIG_SYS_CLK_FREQ	33333300 /* external frequency to pll	*/
+
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+#undef	CONFIG_BOOTARGS
+#undef  CONFIG_BOOTCOMMAND
+
+#define CONFIG_PREBOOT                  /* enable preboot variable      */
+
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
+
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+#define CONFIG_PRAM		2	/* reserve 2 kB "protected RAM" */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+
+#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CONFIG_SYS_BASE_BAUD	    691200
+
+/* The following table includes the supported baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
+
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(~(CONFIG_SYS_TEXT_BASE) + 1)
+#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)
+
+#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
+# define CONFIG_SYS_RAMBOOT		1
+#else
+# undef CONFIG_SYS_RAMBOOT
+#endif
+
+/*-----------------------------------------------------------------------
+ * Environment Variable setup
+ */
+#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CONFIG_ENV_OFFSET		0x100	/* environment starts at the beginning of the EEPROM */
+#define CONFIG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
+				   /* total size of a CAT24WC16 is 2048 bytes */
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last 4 bits of the address	*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+#define CAN_BA		0xF0000000	    /* CAN Base Address			*/
+
+/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
+#define CONFIG_SYS_EBC_PB0AP		0x92015480
+#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization		*/
+#define CONFIG_SYS_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ */
+/* FPGA program pin configuration */
+#define CONFIG_SYS_FPGA_PRG		0x04000000  /* JTAG TMS pin (ppc output)     */
+#define CONFIG_SYS_FPGA_CLK		0x02000000  /* JTAG TCK pin (ppc output)     */
+#define CONFIG_SYS_FPGA_DATA		0x01000000  /* JTAG TDO->TDI data pin (ppc output) */
+#define CONFIG_SYS_FPGA_INIT		0x00010000  /* unused (ppc input)	     */
+#define CONFIG_SYS_FPGA_DONE		0x00008000  /* JTAG TDI->TDO pin (ppc input) */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CONFIG_SYS_TEMP_STACK_OCM	  1
+
+/* On Chip Memory location */
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
+
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO setup (PPC405EP specific)
+ *
+ * GPIO0[0]	- External Bus Controller BLAST output
+ * GPIO0[1-9]	- Instruction trace outputs -> GPIO
+ * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
+ * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
+ * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
+ * GPIO0[24-27] - UART0 control signal inputs/outputs
+ * GPIO0[28-29] - UART1 data signal input/output
+ * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
+ */
+/* GPIO Input:		OSR=00, ISR=00, TSR=00, TCR=0 */
+/* GPIO Output:		OSR=00, ISR=00, TSR=00, TCR=1 */
+/* Alt. Funtion Input:	OSR=00, ISR=01, TSR=00, TCR=0 */
+/* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
+#define CONFIG_SYS_GPIO0_OSRL		0x40000540  /*	0 ... 15 */
+#define CONFIG_SYS_GPIO0_OSRH		0x00000110  /* 16 ... 31 */
+#define CONFIG_SYS_GPIO0_ISR1L		0x00000000  /*	0 ... 15 */
+#define CONFIG_SYS_GPIO0_ISR1H		0x14000045  /* 16 ... 31 */
+#define CONFIG_SYS_GPIO0_TSRL		0x00000000  /*	0 ... 15 */
+#define CONFIG_SYS_GPIO0_TSRH		0x00000000  /* 16 ... 31 */
+#define CONFIG_SYS_GPIO0_TCR		0xB7FE0014  /*	0 ... 31 */
+
+/*
+ * Default speed selection (cpu_plb_opb_ebc) in mhz.
+ * This value will be set if iic boot eprom is disabled.
+ */
+#define PLLMR0_DEFAULT	 PLLMR0_133_66_66_33
+#define PLLMR1_DEFAULT	 PLLMR1_133_66_66_33
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/DU405.h b/qemu/roms/u-boot/include/configs/DU405.h
new file mode 100644
index 000000000..9be2310db
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/DU405.h
@@ -0,0 +1,273 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_DU405		1	/* ...on a DU405 board		*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFD0000
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
+
+#define CONFIG_SYS_CLK_FREQ	25000000 /* external frequency to pll	*/
+
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND	"bootm fff00000"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_PPC4xx_EMAC
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
+#undef  CONFIG_HAS_ETH1
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_EDITENV
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_CONSOLE
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_RTC_MC146818		/* BQ3285 is MC146818 compatible*/
+#define CONFIG_SYS_RTC_REG_BASE_ADDR	 0xF0000080 /* RTC Base Address		*/
+
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+
+#define CONFIG_SYS_EXT_SERIAL_CLOCK	11059200  /* use external serial clock	*/
+
+/* The following table includes the supported baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+#define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff
+ *-----------------------------------------------------------------------
+ */
+#undef	CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
+#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
+#undef	CONFIG_IDE_RESET		/* no reset for ide supported	*/
+
+#define CONFIG_SYS_IDE_MAXBUS		1		/* max. 1 IDE busses	*/
+#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+
+#define CONFIG_SYS_ATA_BASE_ADDR	0xF0100000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFFD0000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(192 * 1024)	/* Reserve 192 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC08) for environment
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last 4 bits of the address	*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+
+#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CONFIG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
+#define CONFIG_ENV_SIZE		0x400	/* 1024 bytes may be used for env vars */
+				   /* total size of a CAT24WC08 is 1024 bytes */
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0xFF800000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0xFFC00000	/* FLASH bank #1	*/
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+#define FLASH0_BA	0xFFC00000	    /* FLASH 0 Base Address		*/
+#define FLASH1_BA	0xFF800000	    /* FLASH 1 Base Address		*/
+#define CAN_BA		0xF0000000	    /* CAN Base Address			*/
+#define DUART_BA	0xF0300000	    /* DUART Base Address		*/
+#define CF_BA		0xF0100000	    /* CompactFlash Base Address	*/
+#define SRAM_BA		0xF0200000	    /* SRAM Base Address		*/
+#define DURAG_IO_BA	0xF0400000	    /* DURAG Bus IO Base Address	*/
+#define DURAG_MEM_BA	0xF0500000	    /* DURAG Bus Mem Base Address	*/
+
+#define FPGA_MODE_REG	(DUART_BA+0x80)	    /* FPGA Mode Register		*/
+
+/* Memory Bank 0 (Flash Bank 0) initialization					*/
+#define CONFIG_SYS_EBC_PB0AP	0x92015480
+#define CONFIG_SYS_EBC_PB0CR	FLASH0_BA | 0x5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (Flash Bank 1) initialization					*/
+#define CONFIG_SYS_EBC_PB1AP	0x92015480
+#define CONFIG_SYS_EBC_PB1CR	FLASH1_BA | 0x5A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 2 (CAN0) initialization						*/
+#define CONFIG_SYS_EBC_PB2AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB2CR	CAN_BA | 0x18000    /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 3 (DUART) initialization						*/
+#define CONFIG_SYS_EBC_PB3AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB3CR	DUART_BA | 0x18000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 4 (CompactFlash IDE) initialization				*/
+#define CONFIG_SYS_EBC_PB4AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB4CR	CF_BA | 0x1A000	    /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 5 (SRAM) initialization						*/
+#define CONFIG_SYS_EBC_PB5AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB5CR	SRAM_BA | 0x1A000   /* BAS=0xF02,BS=1MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 6 (DURAG Bus IO Space) initialization				*/
+#define CONFIG_SYS_EBC_PB6AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB6CR	DURAG_IO_BA | 0x18000 /* BAS=0xF04,BS=1MB,BU=R/W,BW=8bit*/
+
+/* Memory Bank 7 (DURAG Bus Mem Space) initialization				*/
+#define CONFIG_SYS_EBC_PB7AP	0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB7CR	DURAG_MEM_BA | 0x18000 /* BAS=0xF05,BS=1MB,BU=R/W,BW=8bit */
+
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CONFIG_SYS_TEMP_STACK_OCM	  1
+
+/* On Chip Memory location */
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/DU440.h b/qemu/roms/u-boot/include/configs/DU440.h
new file mode 100644
index 000000000..be5494b2e
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/DU440.h
@@ -0,0 +1,415 @@
+/*
+ * (C) Copyright 2008
+ * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
+ *
+ * based on the Sequoia board configuration by
+ * Stefan Roese, Jacqueline Pira-Ferriol and Alain Saurel
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ **********************************************************************
+ * DU440.h - configuration for esd's DU440 board (Power PC440EPx)
+ **********************************************************************
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_DU440		1		/* Board is esd DU440	*/
+#define CONFIG_440EPX		1		/* Specific PPC440EPx	*/
+#define CONFIG_SYS_CLK_FREQ	33333400	/* external freq to pll	*/
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xFFFA0000
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_early_init_f */
+#define CONFIG_MISC_INIT_R	1		/* Call misc_init_r	*/
+#define CONFIG_LAST_STAGE_INIT  1               /* last_stage_init      */
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_MONITOR_LEN		(384 * 1024)	/* Reserve 384 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN		(8 << 20)	/* Reserve 8 MB for malloc()  */
+
+#define CONFIG_SYS_BOOT_BASE_ADDR	0xf0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
+#define CONFIG_SYS_FLASH_BASE		0xfc000000	/* start of FLASH	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND0_ADDR		0xd0000000      /* NAND Flash		*/
+#define CONFIG_SYS_NAND1_ADDR		0xd0100000      /* NAND Flash		*/
+#define CONFIG_SYS_OCM_BASE		0xe0010000      /* ocm			*/
+#define CONFIG_SYS_PCI_BASE		0xe0000000      /* Internal PCI regs	*/
+#define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped pci memory	*/
+#define CONFIG_SYS_PCI_MEMBASE1	CONFIG_SYS_PCI_MEMBASE  + 0x10000000
+#define CONFIG_SYS_PCI_MEMBASE2	CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
+#define CONFIG_SYS_PCI_MEMBASE3	CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
+#define CONFIG_SYS_PCI_IOBASE		0xe8000000
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID	PCI_VENDOR_ID_ESDGMBH
+#define CONFIG_SYS_PCI_SUBSYS_ID	0x0444		/* device ID for DU440 */
+
+#define CONFIG_SYS_USB2D0_BASE		0xe0000100
+#define CONFIG_SYS_USB_DEVICE		0xe0000000
+#define CONFIG_SYS_USB_HOST		0xe0000400
+
+/*
+ * Initial RAM & stack pointer
+ */
+/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache	*/
+#define CONFIG_SYS_INIT_RAM_OCM	1		/* OCM as init ram	*/
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_BASE	/* OCM			*/
+
+#define CONFIG_SYS_INIT_RAM_SIZE	(4 << 10)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+#undef CONFIG_SYS_EXT_SERIAL_CLOCK
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_SYS_BAUDRATE_TABLE						\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*
+ * Video Port
+ */
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_SMI_LYNXEM
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_VIDEO_BMP_GZIP              /* gzip compressed bmp images */
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (4 << 20)  /* for decompressed img */
+#define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x31a       /* 1280x1024,16bpp */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_ISA_IO CONFIG_SYS_PCI_IOBASE
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_EEPROM    1	/* use FLASH for environment vars */
+
+/*
+ * FLASH related
+ */
+#define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible */
+#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver       */
+
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks	      */
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip  */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)    */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)    */
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)   */
+/* CFI_FLASH_PROTECTION make flash_protect hang sometimes -> disabled */
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* use hardware flash protection      */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash      */
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* size of one complete sector        */
+#define CONFIG_ENV_ADDR		((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
+#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector   */
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_EEPROM
+#define CONFIG_ENV_OFFSET		0	/* environment starts at */
+					/* the beginning of the EEPROM */
+#define CONFIG_ENV_SIZE		0x1000 /* 4096 bytes may be used for env vars */
+#endif
+
+/*
+ * DDR SDRAM
+ */
+#define CONFIG_SYS_MBYTES_SDRAM        (1024)	/* 512 MiB      TODO: remove    */
+#define CONFIG_DDR_DATA_EYE		/* use DDR2 optimization        */
+#define CONFIG_SYS_MEM_TOP_HIDE        (4 << 10) /* don't use last 4kbytes     */
+					/* 440EPx errata CHIP 11        */
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for setup     */
+#define CONFIG_DDR_ECC			/* Use ECC when available       */
+#define SPD_EEPROM_ADDRESS	{0x50}
+#define CONFIG_PROG_SDRAM_TLB
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		100000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
+#define CONFIG_SYS_I2C_PPC4XX_CH1
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_1		100000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_1		0x7F
+
+#define CONFIG_SYS_SPD_BUS_NUM         0
+#define IIC1_MCP3021_ADDR	0x4d
+#define IIC1_USB2507_ADDR	0x2c
+#define CONFIG_SYS_I2C_NOPROBES		{ {1, IIC1_USB2507_ADDR} }
+
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x54
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
+
+#define CONFIG_SYS_EEPROM_WREN         1
+#define CONFIG_SYS_I2C_BOOT_EEPROM_ADDR 0x52
+
+/*
+ * standard dtt sensor configuration - bottom bit will determine local or
+ * remote sensor of the TMP401
+ */
+#define CONFIG_DTT_SENSORS		{ 0, 1 }
+
+/*
+ * The PMC440 uses a TI TMP401 temperature sensor. This part
+ * is basically compatible to the ADM1021 that is supported
+ * by U-Boot.
+ *
+ * - i2c addr 0x4c
+ * - conversion rate 0x02 = 0.25 conversions/second
+ * - ALERT ouput disabled
+ * - local temp sensor enabled, min set to 0 deg, max set to 70 deg
+ * - remote temp sensor enabled, min set to 0 deg, max set to 70 deg
+ */
+#define CONFIG_DTT_ADM1021
+#define CONFIG_SYS_DTT_ADM1021		{ { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} }
+
+/*
+ * RTC stuff
+ */
+#define CONFIG_RTC_DS1338
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"ethrotate=no\0"						\
+	"hostname=du440\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+	"flash_self=run ramargs addip addtty optargs;"			\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${img};run nfsargs addip addtty optargs;"	\
+		"bootm\0"						\
+	"rootpath=/tftpboot/du440/target_root_du440\0"			\
+	"img=/tftpboot/du440/uImage\0"					\
+	"kernel_addr=FFC00000\0"					\
+	"ramdisk_addr=FFE00000\0"					\
+	"initrd_high=30000000\0"					\
+	"load=tftp 100000 /tftpboot/du440/u-boot.bin\0"			\
+	"update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;"	\
+		"cp.b 100000 FFFA0000 60000\0"				\
+	""
+
+#define CONFIG_PREBOOT                  /* enable preboot variable      */
+
+#define CONFIG_BOOTDELAY	3	/* autoboot after 5 seconds	*/
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#ifndef __ASSEMBLY__
+int du440_phy_addr(int devnum);
+#endif
+
+#define CONFIG_PPC4xx_EMAC
+#define	CONFIG_IBM_EMAC4_V4	1
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		du440_phy_addr(0) /* PHY address	*/
+
+#define CONFIG_PHY_RESET        1	/* reset phy upon startup	*/
+#undef CONFIG_PHY_GIGE			/* no GbE detection		*/
+
+#define CONFIG_HAS_ETH0
+#define CONFIG_SYS_RX_ETH_BUFFER	128
+
+#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
+#define CONFIG_PHY1_ADDR	du440_phy_addr(1)
+
+/*
+ * USB
+ */
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_USB_STORAGE
+#define CONFIG_SYS_OHCI_BE_CONTROLLER
+
+#define CONFIG_SYS_USB_OHCI_CPU_INIT	1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE	CONFIG_SYS_USB_HOST
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"du440"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
+
+/* Comment this out to enable USB 1.1 device */
+#define USB_2_0_DEVICE
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BMP
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SOURCE
+#define CONFIG_CMD_USB
+
+#define CONFIG_SUPPORT_VFAT
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	        1024	/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	        256	/* Console I/O Buffer Size	*/
+#endif
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	        16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	        CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x00400000 /* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END		0x3f000000 /* 4 ... < 1GB DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000  /* default load address	*/
+#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_LOOPW            1       /* enable loopw command         */
+#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+#define CONFIG_AUTOBOOT_KEYED	1
+#define CONFIG_AUTOBOOT_PROMPT	\
+	"Press SPACE to abort autoboot in %d seconds\n", bootdelay
+#define CONFIG_AUTOBOOT_DELAY_STR "d"
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
+/*
+ * PCI stuff
+ */
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_PNP			/* do (not) pci plug-and-play   */
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup  */
+#define CONFIG_SYS_PCI_TARGBASE       0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
+
+/* Board-specific PCI */
+#define CONFIG_SYS_PCI_TARGET_INIT
+#define CONFIG_SYS_PCI_MASTER_INIT
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)     /* Initial Memory map for Linux */
+
+/*
+ * External Bus Controller (EBC) Setup
+ */
+#define CONFIG_SYS_FLASH		CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_SYS_CPLD_BASE		0xC0000000
+#define CONFIG_SYS_CPLD_RANGE	        0x00000010
+#define CONFIG_SYS_DUMEM_BASE		0xC0100000
+#define CONFIG_SYS_DUMEM_RANGE		0x00100000
+#define CONFIG_SYS_DUIO_BASE		0xC0200000
+#define CONFIG_SYS_DUIO_RANGE	        0x00010000
+
+#define CONFIG_SYS_NAND0_CS		2		/* NAND chip connected to CSx */
+#define CONFIG_SYS_NAND1_CS		3		/* NAND chip connected to CSx */
+/* Memory Bank 0 (NOR-FLASH) initialization */
+#define CONFIG_SYS_EBC_PB0AP		0x04017200
+#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_FLASH_BASE | 0xda000)
+
+/* Memory Bank 1 (CPLD, 16 bytes needed, but 1MB is minimum) */
+#define CONFIG_SYS_EBC_PB1AP		0x018003c0
+#define CONFIG_SYS_EBC_PB1CR		(CONFIG_SYS_CPLD_BASE | 0x18000)
+
+/* Memory Bank 2 (NAND-FLASH) initialization */
+#define CONFIG_SYS_EBC_PB2AP		0x018003c0
+#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_NAND0_ADDR | 0x1c000)
+
+/* Memory Bank 3 (NAND-FLASH) initialization */
+#define CONFIG_SYS_EBC_PB3AP		0x018003c0
+#define CONFIG_SYS_EBC_PB3CR		(CONFIG_SYS_NAND1_ADDR | 0x1c000)
+
+/* Memory Bank 4 (DUMEM, 1MB) initialization */
+#define CONFIG_SYS_EBC_PB4AP		0x018053c0
+#define CONFIG_SYS_EBC_PB4CR		(CONFIG_SYS_DUMEM_BASE | 0x18000)
+
+/* Memory Bank 5 (DUIO, 64KB needed, but 1MB is minimum) */
+#define CONFIG_SYS_EBC_PB5AP		0x018053c0
+#define CONFIG_SYS_EBC_PB5CR		(CONFIG_SYS_DUIO_BASE | 0x18000)
+
+/*
+ * NAND FLASH
+ */
+#define CONFIG_SYS_MAX_NAND_DEVICE	2
+#define CONFIG_SYS_NAND_SELECT_DEVICE  1	/* nand driver supports mutipl. chips */
+#define CONFIG_SYS_NAND_BASE_LIST	{CONFIG_SYS_NAND0_ADDR + CONFIG_SYS_NAND0_CS, \
+				 CONFIG_SYS_NAND1_ADDR + CONFIG_SYS_NAND1_CS}
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+#define CONFIG_SOURCE		1
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/ELPPC.h b/qemu/roms/u-boot/include/configs/ELPPC.h
new file mode 100644
index 000000000..0ffbd41b4
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/ELPPC.h
@@ -0,0 +1,337 @@
+/*
+ * (C) Copyright 2002 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define GTREGREAD(x) 0xffffffff         /* needed for debug */
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
+
+/* these hardware addresses are pretty bogus, please change them to
+   suit your needs */
+
+/* first ethernet */
+#define CONFIG_ETHADDR          00:00:5b:ee:de:ad
+
+#define CONFIG_IPADDR           192.168.0.105
+#define CONFIG_SERVERIP         192.168.0.100
+
+#define CONFIG_ELPPC            1       /* this is an BAB740/BAB750 board */
+
+#define CONFIG_BAUDRATE         9600    /* console baudrate */
+
+#undef  CONFIG_WATCHDOG
+
+#define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#undef  CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND                                  \
+    "bootp 1000000; "                                       \
+    "setenv bootargs root=ramfs console=ttyS00,9600 "       \
+    "ip=${ipaddr}:${serverip}:${rootpath}:${gatewayip}:"    \
+    "${netmask}:${hostname}:eth0:none; "                    \
+    "bootm"
+
+#define CONFIG_LOADS_ECHO       0       /* echo off for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE           /* allow baudrate changes */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_JFFS2
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP                    /* undef to save memory */
+
+/*
+ * choose between COM1 and COM2 as serial console
+ */
+#define CONFIG_CONS_INDEX       1
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE              1024        /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE              256         /* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS             16          /* max number of command args    */
+#define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE  /* Boot Argument Buffer Size    */
+
+#define CONFIG_SYS_MEMTEST_START       0x00000000  /* memtest works on    */
+#define CONFIG_SYS_MEMTEST_END         0x04000000  /* 0 ... 64 MB in DRAM    */
+
+#define CONFIG_SYS_LOAD_ADDR           0x1000000   /* default load address    */
+
+#define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+#define CONFIG_SYS_BOARD_ASM_INIT
+#define CONFIG_MISC_INIT_R
+
+/*
+ * Address mapping scheme for the MPC107 mem controller is mapping B (CHRP)
+ */
+#undef  CONFIG_SYS_ADDRESS_MAP_A
+
+#define CONFIG_SYS_PCI_MEMORY_BUS      0x00000000
+#define CONFIG_SYS_PCI_MEMORY_PHYS     0x00000000
+#define CONFIG_SYS_PCI_MEMORY_SIZE     0x40000000
+
+#define CONFIG_SYS_PCI_MEM_BUS         0x80000000
+#define CONFIG_SYS_PCI_MEM_PHYS        0x80000000
+#define CONFIG_SYS_PCI_MEM_SIZE        0x7d000000
+
+#define CONFIG_SYS_ISA_MEM_BUS         0x00000000
+#define CONFIG_SYS_ISA_MEM_PHYS        0xfd000000
+#define CONFIG_SYS_ISA_MEM_SIZE        0x01000000
+
+#define CONFIG_SYS_PCI_IO_BUS          0x00800000
+#define CONFIG_SYS_PCI_IO_PHYS         0xfe800000
+#define CONFIG_SYS_PCI_IO_SIZE         0x00400000
+
+#define CONFIG_SYS_ISA_IO_BUS          0x00000000
+#define CONFIG_SYS_ISA_IO_PHYS         0xfe000000
+#define CONFIG_SYS_ISA_IO_SIZE         0x00800000
+
+/* driver defines FDC,IDE,... */
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_ISA_IO_PHYS
+#define CONFIG_SYS_ISA_IO              CONFIG_SYS_ISA_IO_PHYS
+#define CONFIG_SYS_60X_PCI_IO_OFFSET   CONFIG_SYS_ISA_IO_PHYS
+
+/*
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE          0x00000000
+
+#define CONFIG_SYS_USR_LED_BASE        0x78000000
+#define CONFIG_SYS_NVRAM_BASE          0xff000000
+#define CONFIG_SYS_UART_BASE           0xff400000
+#define CONFIG_SYS_FLASH_BASE          0xfff00000
+
+#define MPC107_EUMB_ADDR        0xfce00000
+#define MPC107_EUMB_PI          0xfce41090
+#define MPC107_EUMB_GCR         0xfce41020
+#define MPC107_EUMB_IACKR       0xfce600a0
+#define MPC107_I2C_ADDR         0xfce03000
+
+/*
+ * Definitions for initial stack pointer and data area
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR       0x00fd0000  /* above the memtest region */
+#define CONFIG_SYS_INIT_RAM_SIZE        0x4000
+#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * Flash mapping/organization on the MPC10x.
+ */
+#define FLASH_BASE0_PRELIM      0xff800000
+#define FLASH_BASE1_PRELIM      0xffc00000
+
+#define CONFIG_SYS_MAX_FLASH_BANKS     2           /* max number of memory banks    */
+#define CONFIG_SYS_MAX_FLASH_SECT      67          /* max number of sectors on one chip */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT    120000      /* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT    500         /* Timeout for Flash Write (in ms) */
+
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_CMD_MTDPARTS
+#define CONFIG_JFFS2_DEV		"nor0"
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET	0x00000000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_CMD_MTDPARTS
+#define MTDIDS_DEFAULT		"nor0=elppc-0,nor1=elppc-1"
+#define MTDPARTS_DEFAULT	"mtdparts=elppc-0:-(jffs2),elppc-1:-(user)"
+*/
+
+#define CONFIG_SYS_MONITOR_BASE        CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN         0x40000     /* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN          0x20000     /* Reserve 128 kB for malloc() */
+#undef  CONFIG_SYS_MEMTEST
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_IS_IN_NVRAM     1           /* use NVRAM for environment vars */
+#define CONFIG_SYS_NVRAM_SIZE          0x800       /* NVRAM size (2kB) */
+#define CONFIG_ENV_SIZE            0x400       /* Size of Environment vars (1kB) */
+#define CONFIG_ENV_ADDR            0x0
+#define CONFIG_ENV_MAP_ADRS        0xff000000
+#define CONFIG_SYS_NV_SROM_COPY_ADDR   (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
+#define CONFIG_SYS_NVRAM_ACCESS_ROUTINE            /* only byte accsess alowed */
+#define CONFIG_SYS_SROM_SIZE           0x100       /* shadow of revision info is in nvram */
+
+/*
+ * Serial devices
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE    1
+#define CONFIG_SYS_NS16550_CLK         24000000
+#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_UART_BASE + 0)
+#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_UART_BASE + 8)
+
+/*
+ * PCI stuff
+ */
+#define CONFIG_PCI                                /* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_PNP                            /* pci plug-and-play */
+#define CONFIG_PCI_HOST         PCI_HOST_AUTO
+#undef  CONFIG_PCI_SCAN_SHOW
+
+/*
+ * Optional Video console (graphic: SMI LynxEM)
+ */
+#define CONFIG_VIDEO
+#define CONFIG_CFB_CONSOLE
+#define VIDEO_KBD_INIT_FCT    (simple_strtol (getenv("console"), NULL, 10))
+#define VIDEO_TSTC_FCT        serial_tstc
+#define VIDEO_GETC_FCT        serial_getc
+
+#define CONFIG_VIDEO_SMI_LYNXEM
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_CONSOLE_EXTRA_INFO
+
+/*
+ * Initial BATs
+ */
+#if 1
+
+#define CONFIG_SYS_IBAT0L 0
+#define CONFIG_SYS_IBAT0U 0
+#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT1U
+
+#define CONFIG_SYS_IBAT1L 0
+#define CONFIG_SYS_IBAT1U 0
+#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
+
+#define CONFIG_SYS_IBAT2L 0
+#define CONFIG_SYS_IBAT2U 0
+#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
+
+#define CONFIG_SYS_IBAT3L 0
+#define CONFIG_SYS_IBAT3U 0
+#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
+
+#else
+
+/* SDRAM */
+#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_RW)
+#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT1U
+
+/* address range for flashes */
+#define CONFIG_SYS_IBAT1L (CONFIG_SYS_FLASH_BASE | BATL_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT1U (CONFIG_SYS_FLASH_BASE | BATU_BL_16M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
+
+/* ISA IO space */
+#define CONFIG_SYS_IBAT2L (CONFIG_SYS_ISA_IO | BATL_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U (CONFIG_SYS_ISA_IO | BATU_BL_16M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
+
+/* ISA memory space */
+#define CONFIG_SYS_IBAT3L (CONFIG_SYS_ISA_MEM | BATL_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U (CONFIG_SYS_ISA_MEM | BATU_BL_16M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
+
+#endif
+
+/*
+ * Speed settings are board specific
+ */
+#define CONFIG_SYS_BUS_CLK	100000000
+#define CONFIG_SYS_CPU_CLK	400000000
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ           (8 << 20)           /* Initial Memory map for Linux */
+
+/*
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE        32    /* For all MPC74xx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT        5    /* log base 2 of the above value */
+#endif
+
+/*
+ * L2CR setup -- make sure this is right for your board!
+ * look in include/74xx_7xx.h for the defines used here
+ */
+
+#define CONFIG_SYS_L2
+
+#if 1
+#define L2_INIT     0       /* cpu 750 CXe*/
+#else
+#define L2_INIT     (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
+		     L2CR_L2OH_5   | L2CR_L2CTL | L2CR_L2WT)
+#endif
+#define L2_ENABLE   (L2_INIT | L2CR_L2E)
+
+#define CONFIG_EEPRO100
+#define CONFIG_SYS_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
+#define CONFIG_EEPRO100_SROM_WRITE
+
+#endif    /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/ELPT860.h b/qemu/roms/u-boot/include/configs/ELPT860.h
new file mode 100644
index 000000000..a9d62c880
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/ELPT860.h
@@ -0,0 +1,374 @@
+/*
+**=====================================================================
+**
+** Copyright (C) 2000, 2001, 2002, 2003
+** The LEOX team <team@leox.org>, http://www.leox.org
+**
+** LEOX.org is about the development of free hardware and software resources
+**   for system on chip.
+**
+** Description: U-Boot port on the LEOX's ELPT860 CPU board
+** ~~~~~~~~~~~
+**
+**=====================================================================
+**
+ * SPDX-License-Identifier:	GPL-2.0+
+**
+**=====================================================================
+*/
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC860		1	/* It's a MPC860, in fact a 860T CPU */
+#define CONFIG_MPC860T		1
+#define CONFIG_ELPT860		1	/* ...on a LEOX's ELPT860 CPU board */
+
+#define CONFIG_SYS_TEXT_BASE	0x02000000
+
+#define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		    */
+#undef	  CONFIG_8xx_CONS_SMC2
+#undef	  CONFIG_8xx_CONS_NONE
+
+#define CONFIG_CLOCKS_IN_MHZ	1  /* Clock passed to Linux (<2.4.5) in MHz */
+#define CONFIG_8xx_GCLK_FREQ	50000000       /* MPC860T runs at 50MHz */
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
+#define CONFIG_RESET_PHY_R	1	/* Call reset_phy()		*/
+
+/* BOOT arguments */
+#define CONFIG_PREBOOT							   \
+     "echo;"								   \
+     "echo Type \"run nfsboot\" to mount root filesystem over NFS;"	   \
+     "echo"
+
+#undef	  CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+    "ramargs=setenv bootargs root=/dev/ram rw\0"			\
+    "rootargs=setenv rootpath /tftp/${ipaddr}\0"			\
+    "nfsargs=setenv bootargs root=/dev/nfs rw "				\
+	"nfsroot=${serverip}:${rootpath}\0"				\
+    "addip=setenv bootargs ${bootargs} "				\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"		\
+	":${hostname}:eth0:off panic=1\0"				\
+    "ramboot=tftp 400000 /home/paugaml/pMulti;"				\
+	"run ramargs;bootm\0"						\
+    "nfsboot=tftp 400000 /home/paugaml/uImage;"				\
+	"run rootargs;run nfsargs;run addip;bootm\0"			\
+    ""
+#define CONFIG_BOOTCOMMAND	"run ramboot"
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+#undef	  CONFIG_WATCHDOG		/* watchdog disabled		*/
+#undef	  CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+#undef	  CONFIG_RTC_MPC8xx		/* internal RTC MPC8xx unused	*/
+#define CONFIG_RTC_DS164x	1	/* RTC is a Dallas DS1646	*/
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	  CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT     "LEOX_elpt860: " /* Monitor Command Prompt	*/
+
+#if defined(CONFIG_CMD_KGDB)
+#  define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#  define CONFIG_SYS_CBSIZE	 256		/* Console I/O Buffer Size	*/
+#endif
+
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	  16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	  CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x00400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x00C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address */
+
+/*
+ * Environment Variables and Storages
+ */
+#define CONFIG_ENV_OVERWRITE	1  /* Allow Overwrite of serial# & ethaddr */
+
+#undef	  CONFIG_ENV_IS_IN_NVRAM	       /* Environment is in NVRAM	*/
+#undef	  CONFIG_ENV_IS_IN_EEPROM	       /* Environment is in I2C EEPROM	*/
+#define CONFIG_ENV_IS_IN_FLASH	1      /* Environment is in FLASH	*/
+
+#define CONFIG_BAUDRATE		9600   /* console baudrate = 9600 bps	*/
+
+#define CONFIG_ETHADDR		00:01:77:00:60:40
+#define CONFIG_IPADDR		192.168.0.30
+#define CONFIG_NETMASK		255.255.255.0
+
+#define CONFIG_SERVERIP		192.168.0.1
+#define CONFIG_GATEWAYIP	192.168.0.1
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xFF000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x02000000
+#define CONFIG_SYS_NVRAM_BASE		0x03000000
+
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+#  if defined(DEBUG)
+#    define CONFIG_SYS_MONITOR_LEN	(320 << 10)  /* Reserve 320 kB for Monitor  */
+#  else
+#    define CONFIG_SYS_MONITOR_LEN	(256 << 10)  /* Reserve 256 kB for Monitor  */
+#  endif
+#else
+#  if defined(DEBUG)
+#    define CONFIG_SYS_MONITOR_LEN	(256 << 10)  /* Reserve 256 kB for Monitor  */
+#  else
+#    define CONFIG_SYS_MONITOR_LEN	(192 << 10)  /* Reserve 192 kB for Monitor  */
+#  endif
+#endif
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)  /* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)    /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks	     */
+#define CONFIG_SYS_MAX_FLASH_SECT	8	/* max number of sectors on one chip */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)   */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)   */
+
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+#  define CONFIG_ENV_OFFSET	0x10000 /* Offset   of Environment Sector    */
+#  define CONFIG_ENV_SIZE		0x10000 /* Total Size of Environment Sector  */
+#endif
+
+/*-----------------------------------------------------------------------
+ * NVRAM organization
+ */
+#define CONFIG_SYS_NVRAM_BASE_ADDR	CONFIG_SYS_NVRAM_BASE /* Base address of NVRAM area */
+#define CONFIG_SYS_NVRAM_SIZE		((128*1024)-8) /* clock regs resident in the */
+					       /*   8 top NVRAM locations    */
+
+#if defined(CONFIG_ENV_IS_IN_NVRAM)
+#  define CONFIG_ENV_ADDR		CONFIG_SYS_NVRAM_BASE /* Base address of NVRAM area */
+#  define CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector  */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs		     */
+
+#if defined(CONFIG_CMD_KGDB)
+#  define CONFIG_SYS_CACHELINE_SHIFT	 4	/* log base 2 of the above value     */
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#  define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT	 | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI | SYPCR_SWP)
+#else
+#  define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT	 | SYPCR_BME | SYPCR_SWF | \
+						   SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ * Once-per-Second Interrupt, Alarm Interrupt, RTC freezing enabled, RTC
+ *  enabled
+ */
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit - leave PLL multiplication factor unchanged !
+ */
+#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	 SCCR_EBDF11
+#define CONFIG_SYS_SCCR	(SCCR_TBS     | \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * Chip Selects + SDRAM timings + Memory Periodic Timer Prescaler
+ *-----------------------------------------------------------------------
+ *
+ */
+#ifdef DEBUG
+#  define CONFIG_SYS_DER		0xFFE7400F	/* Debug Enable Register */
+#else
+#  define CONFIG_SYS_DER		0
+#endif
+
+/*
+ * Init Memory Controller:
+ * ~~~~~~~~~~~~~~~~~~~~~~
+ *
+ * BR0 and OR0 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	CONFIG_SYS_FLASH_BASE	/* FLASH bank #0	  */
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CONFIG_SYS_PRELIM_OR_AM	0xFF000000	/* 16 MB between each CSx */
+
+/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 0, SCY = 8, EHTR = 0	  */
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV2 | OR_BI | OR_SCY_8_CLK)
+
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
+
+/*
+ * BR1 and OR1 (SDRAM)
+ *
+ */
+#define SDRAM_BASE1_PRELIM	CONFIG_SYS_SDRAM_BASE	/* SDRAM bank #0	*/
+#define SDRAM_MAX_SIZE		0x02000000	/* 32 MB MAX for CS1	*/
+
+/* SDRAM timing:							*/
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000000
+
+#define CONFIG_SYS_OR1_PRELIM	((2 * CONFIG_SYS_PRELIM_OR_AM) | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR1_PRELIM	((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+/*
+ * BR2 and OR2 (NVRAM)
+ *
+ */
+#define NVRAM_BASE1_PRELIM	CONFIG_SYS_NVRAM_BASE	/* NVRAM bank #0	*/
+#define NVRAM_MAX_SIZE		0x00020000	/* 128 KB MAX for CS2	*/
+
+#define CONFIG_SYS_OR2_PRELIM		0xFFF80160
+#define CONFIG_SYS_BR2_PRELIM	((NVRAM_BASE1_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CONFIG_SYS_MAMR_PTA		97     /* start with divider for 100 MHz */
+
+/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16	  /* setting for 2 banks */
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32	  /* setting for 1 bank	 */
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit	 */
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8	  /* setting for 2 banks */
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16	  /* setting for 1 bank	 */
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    | \
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    | \
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/ESTEEM192E.h b/qemu/roms/u-boot/include/configs/ESTEEM192E.h
new file mode 100644
index 000000000..347f8b64a
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/ESTEEM192E.h
@@ -0,0 +1,292 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC850		1	/* This is a MPC850 CPU		*/
+#define CONFIG_ESTEEM192E	1	/* ...on a EST ESTEEM192E	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0x40000000
+
+#define CONFIG_FLASH_16BIT	1	/* Rom 16 bit data bus		*/
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef  CONFIG_8xx_CONS_NONE
+
+#define MPC8XX_FACT	10		/* Multiply by 10		*/
+#define MPC8XX_XIN	4915200	/* 4.915200 MHz in	- ??? - XXX	*/
+#define CONFIG_SYS_PLPRCR_MF	((MPC8XX_FACT-1) << 20)
+#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) /* 49,152,000 Hz	*/
+
+#define CONFIG_8xx_GCLK_FREQ	MPC8XX_HZ	/* Force it - dont measure it */
+
+#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+
+#define CONFIG_BAUDRATE		9600
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+#define CONFIG_BOOTCOMMAND	"bootm 40030000" /* autoboot command	*/
+
+#define CONFIG_BOOTARGS		"root=/dev/ram rw ramdisk=8192 "			\
+				"ip=100.100.100.21:100.100.100.14:100.100.100.1:255.0.0.0 "
+/*
+ * Miscellaneous configurable options
+ */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT	"BOOT: "	/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_CBSIZE	256			/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	8			/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xFF000000
+
+  /*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#ifdef	DEBUG
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#else
+#define	CONFIG_SYS_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
+#endif
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	71	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CONFIG_ENV_IS_IN_FLASH	1
+#define	CONFIG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
+#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+
+/*-----------------------------------------------------------------------
+ * SUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) /* DBGC00 */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
+
+/* (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) */
+
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit - leave PLL multiplication factor unchanged !
+ */
+#define CONFIG_SYS_PLPRCR	(CONFIG_SYS_PLPRCR_MF | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CONFIG_SYS_SCCR	(SCCR_TBS     | \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
+
+#define CONFIG_SYS_PCMCIA_INTERRUPT	SIU_LEVEL6
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+/*#define	CONFIG_SYS_DER	0x2002000F*/
+#define CONFIG_SYS_DER	0
+/*#define CONFIG_SYS_DER	0x02002000 */
+
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
+#define CONFIG_SYS_OR_TIMING_FLASH	0x00000160
+				/*(OR_CSNT_SAM  | OR_ACS_DIV2 | OR_BI | \
+				 OR_SCY_5_CLK | OR_EHTR) */
+
+#define CONFIG_SYS_OR0_REMAP	0x80000160     /*(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)*/
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	( FLASH_BASE0_PRELIM | 0x00000801 )
+
+#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+#define CONFIG_SYS_BR1_PRELIM	( FLASH_BASE1_PRELIM | 0x00000801 )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_BASE3_PRELIM	0x04000000	/* SDRAM bank #1	*/
+#define	SDRAM_MAX_SIZE		0x02000000	/* max 32 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
+
+#define CONFIG_SYS_OR2_PRELIM	0xFC000E00
+#define CONFIG_SYS_BR2_PRELIM	(SDRAM_BASE2_PRELIM | 0x00000081)
+
+#define	CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+#define CONFIG_SYS_BR3_PRELIM	(SDRAM_BASE3_PRELIM | 0x00000081)
+
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CONFIG_SYS_MAMR_PTA	97		/* start with divider for 100 MHz	*/
+
+/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CONFIG_SYS_MAMR_8COL	0x18803112
+#define CONFIG_SYS_MAMR_9COL	0x18803112	/* same as 8 column because its just easier to port with*/
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/FLAGADM.h b/qemu/roms/u-boot/include/configs/FLAGADM.h
new file mode 100644
index 000000000..d93223fa4
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/FLAGADM.h
@@ -0,0 +1,296 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC823		1	/* This is a MPC823 CPU		*/
+#define CONFIG_FLAGADM		1	/* ...on a FLAGA DM	*/
+#define CONFIG_8xx_GCLK_FREQ 48000000	/*48MHz*/
+
+#define	CONFIG_SYS_TEXT_BASE	0x40000000
+
+#undef	CONFIG_8xx_CONS_SMC1		/* Console is on SMC1		*/
+#define CONFIG_8xx_CONS_SMC2	1
+#undef	CONFIG_8xx_CONS_NONE
+
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+#define CONFIG_BOOTDELAY	3	/* autoboot after 5 seconds	*/
+
+#undef	CONFIG_CLOCKS_IN_MHZ
+
+#if 0
+#define CONFIG_BOOTARGS		"root=/dev/nfs rw ip=bootp"
+#define CONFIG_BOOTCOMMAND							\
+   "setenv bootargs root=/dev/ram ip=off panic=1;"     \
+   "bootm 40040000 400e0000"
+#else
+#define CONFIG_BOOTARGS		"root=/dev/nfs rw ip=bootp panic=1"
+#define CONFIG_BOOTCOMMAND	"bootp 0x400000; bootm 0x400000"
+#endif /* 0|1*/
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+/*#define	CONFIG_WATCHDOG*/	/* watchdog enabled		*/
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
+
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_NET
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"EEG> "		/* Monitor Command Prompt	*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0100000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x40040000	/* default load address */
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xFF000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#define CONFIG_SYS_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	71	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	8000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CONFIG_ENV_IS_IN_FLASH	1
+/* This is a litlebit wasteful, but one sector is 128kb and we have to
+ * assigne a whole sector for the environment, so that we can safely
+ * erase and write it without disturbing the boot sector
+ */
+#define CONFIG_ENV_OFFSET		0x20000 /*   Offset   of Environment Sector	*/
+#define CONFIG_ENV_SIZE		0x20000 /* Total Size of Environment Sector	*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+#define CONFIG_SYS_DELAYED_ICACHE	1	/* enable ICache not before
+						 * running in RAM.
+						 */
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#ifdef CONFIG_WATCHDOG
+#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP)
+#else
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CONFIG_SYS_PRE_SIUMCR (SIUMCR_DBGC11 | SIUMCR_MPRE | \
+							SIUMCR_MLRC01 | SIUMCR_GB5E)
+#define CONFIG_SYS_SIUMCR (CONFIG_SYS_PRE_SIUMCR | SIUMCR_DLK)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit miltiplier of 0x00b i.e. operation clock is
+ * 4MHz * (0x00b+1) = 4MHz * 12 =  48MHz
+ */
+#define CONFIG_SYS_PLPRCR	(0x00b00000 | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CONFIG_SYS_SCCR	( SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+#define CONFIG_SYS_DER 0
+
+/*
+ * In the Flaga DM we have:
+ * Flash on BR0/OR0/CS0a at 0x40000000
+ * Display on BR1/OR1/CS1 at 0x20000000
+ * SDRAM on BR2/OR2/CS2 at 0x00000000
+ * Free BR3/OR3/CS3
+ * DSP1 on BR4/OR4/CS4 at 0x80000000
+ * DSP2 on BR5/OR5/CS5 at 0xa0000000
+ *
+ * For now we just configure the Flash and the SDRAM and leave the others
+ * untouched.
+*/
+
+#define CONFIG_SYS_FLASH_PROTECTION 0
+
+#define FLASH_BASE0		0x40000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CONFIG_SYS_OR_AM		0xff000000	/* OR addr mask */
+#define CONFIG_SYS_OR_ATM		0x00006000
+
+/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1	*/
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | \
+				 OR_SCY_3_CLK | OR_TRLX | OR_EHTR )
+
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_OR_AM | CONFIG_SYS_OR_ATM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0 & BR_BA_MSK) | BR_PS_16 | BR_V )
+
+/*
+ * BR2 and OR2 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2			0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CONFIG_SYS_OR_TIMING_SDRAM	( 0x00000800 )
+
+#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM)
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2 & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#define CONFIG_SYS_BR2			CONFIG_SYS_BR2_PRELIM
+#define CONFIG_SYS_OR2			CONFIG_SYS_OR2_PRELIM
+
+/*
+ * MAMR settings for SDRAM
+ */
+#define CONFIG_SYS_MAMR_48_SDR (CONFIG_SYS_MAMR_PTA |	 MAMR_WLFA_1X | MAMR_RLFA_1X  \
+					| MAMR_G0CLA_A11)
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CONFIG_SYS_MAMR_PTA	0x0F000000
+
+/*
+   * BR4 and OR4 (DSP1)
+   *
+   * We do not wan't preliminary setup of the DSP, anyway we need the
+   * UPMB setup correctly before we can access the DSP.
+   *
+*/
+#define DSP_BASE 0x80000000
+
+#define CONFIG_SYS_OR4 ( OR_AM_MSK | OR_CSNT_SAM | OR_BI | OR_G5LS)
+#define CONFIG_SYS_BR4 ( (DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_UPMB | BR_V )
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/FPS850L.h b/qemu/roms/u-boot/include/configs/FPS850L.h
new file mode 100644
index 000000000..4ea24a631
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/FPS850L.h
@@ -0,0 +1,413 @@
+/*
+ * (C) Copyright 2000-2008
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC850		1	/* This is a MPC850 CPU		*/
+#define CONFIG_FPS850L		1	/* ...on a FingerPrint Sensor	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0x40000000
+
+#define	CONFIG_8xx_CONS_SMC2	1	/* Console is on SMC2		*/
+#define CONFIG_SYS_SMC_RXBUFLEN	128
+#define CONFIG_SYS_MAXIDLE	10
+#define CONFIG_BAUDRATE		115200
+
+#define	CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_8xx\0"					\
+	"hostname=FPS850L\0"						\
+	"bootfile=FPS850L/uImage\0"					\
+	"fdt_addr=40040000\0"						\
+	"kernel_addr=40060000\0"					\
+	"ramdisk_addr=40200000\0"					\
+	"u-boot=FPS850L/u-image.bin\0"					\
+	"load=tftp 200000 ${u-boot}\0"					\
+	"update=prot off 40000000 +${filesize};"			\
+		"era 40000000 +${filesize};"				\
+		"cp.b 200000 40000000 ${filesize};"			\
+		"sete filesize;save\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_NISDOMAIN
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_NTPSERVER
+#define CONFIG_BOOTP_TIMEOFFSET
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
+
+#define CONFIG_NETCONSOLE
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+
+/* use CFI flash driver */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	71	/* max number of sectors on one chip */
+
+#define	CONFIG_ENV_IS_IN_FLASH	1
+#define	CONFIG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
+#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+
+#define CONFIG_MISC_INIT_R		/* Make sure to remap flashes correctly */
+
+/*-----------------------------------------------------------------------
+ * Dynamic MTD partition support
+ */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
+#define MTDIDS_DEFAULT		"nor0=TQM8xxL-0"
+
+#define MTDPARTS_DEFAULT	"mtdparts=TQM8xxL-0:256k(u-boot),"	\
+						"128k(dtb),"		\
+						"1664k(kernel),"	\
+						"2m(rootfs),"		\
+						"4m(data)"
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit - leave PLL multiplication factor unchanged !
+ */
+#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CONFIG_SYS_SCCR	(SCCR_TBS     | \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
+
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
+#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
+
+#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#define	CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ *	gclk	  CPU clock (not bus clock!)
+ *	Trefresh  Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096  Rows from SDRAM example configuration
+ * 1000  factor s -> ms
+ *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
+ *    4  Number of refresh cycles per period
+ *   64  Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ * 50 MHz => 50.000.000 / Divider =  98
+ * 66 Mhz => 66.000.000 / Divider = 129
+ * 80 Mhz => 80.000.000 / Divider = 156
+ */
+
+#define CONFIG_SYS_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CONFIG_SYS_MAMR_PTA	98
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ */
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_HWCONFIG		1
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/FPS860L.h b/qemu/roms/u-boot/include/configs/FPS860L.h
new file mode 100644
index 000000000..c3688616a
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/FPS860L.h
@@ -0,0 +1,415 @@
+/*
+ * (C) Copyright 2000-2008
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC860		1	/* This is a MPC860 CPU		*/
+#define CONFIG_FPS860L		1	/* ...on a FingerPrint Sensor	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0x40000000
+
+#define	CONFIG_8xx_CONS_SMC2	1	/* Console is on SMC2		*/
+#define CONFIG_SYS_SMC_RXBUFLEN	128
+#define CONFIG_SYS_MAXIDLE	10
+#define CONFIG_BAUDRATE		115200
+
+#define	CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_8xx\0"					\
+	"hostname=FPS860L\0"						\
+	"bootfile=FPS860L/uImage\0"					\
+	"fdt_addr=40040000\0"						\
+	"kernel_addr=40060000\0"					\
+	"ramdisk_addr=40200000\0"					\
+	"u-boot=FPS860L/u-image.bin\0"					\
+	"load=tftp 200000 ${u-boot}\0"					\
+	"update=prot off 40000000 +${filesize};"			\
+		"era 40000000 +${filesize};"				\
+		"cp.b 200000 40000000 ${filesize};"			\
+		"sete filesize;save\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_NISDOMAIN
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_NTPSERVER
+#define CONFIG_BOOTP_TIMEOFFSET
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
+
+#define CONFIG_NETCONSOLE
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+
+/* use CFI flash driver */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	71	/* max number of sectors on one chip */
+
+#define	CONFIG_ENV_IS_IN_FLASH	1
+#define	CONFIG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
+#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+
+#define CONFIG_MISC_INIT_R		/* Make sure to remap flashes correctly */
+
+/*-----------------------------------------------------------------------
+ * Dynamic MTD partition support
+ */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
+#define MTDIDS_DEFAULT		"nor0=TQM8xxL-0"
+
+#define MTDPARTS_DEFAULT	"mtdparts=TQM8xxL-0:256k(u-boot),"	\
+						"128k(dtb),"		\
+						"1664k(kernel),"	\
+						"2m(rootfs),"		\
+						"4m(data)"
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit - leave PLL multiplication factor unchanged !
+ */
+#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CONFIG_SYS_SCCR	(SCCR_TBS     | \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
+
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
+#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
+
+#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#define	CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ *	gclk	  CPU clock (not bus clock!)
+ *	Trefresh  Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096  Rows from SDRAM example configuration
+ * 1000  factor s -> ms
+ *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
+ *    4  Number of refresh cycles per period
+ *   64  Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ * 50 MHz => 50.000.000 / Divider =  98
+ * 66 Mhz => 66.000.000 / Divider = 129
+ * 80 Mhz => 80.000.000 / Divider = 156
+ */
+
+#define CONFIG_SYS_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CONFIG_SYS_MAMR_PTA	98
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ */
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+#define CONFIG_SCC1_ENET
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_HWCONFIG		1
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/G2000.h b/qemu/roms/u-boot/include/configs/G2000.h
new file mode 100644
index 000000000..0c66092e0
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/G2000.h
@@ -0,0 +1,383 @@
+/*
+ * (C) Copyright 2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_G2000		1	/* ...on a PLU405 board		*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
+
+#define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
+
+#if 0 /* test-only */
+#define CONFIG_BAUDRATE		115200
+#else
+#define CONFIG_BAUDRATE		9600
+#endif
+
+#define CONFIG_PREBOOT
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off\0"				\
+	"addmisc=setenv bootargs ${bootargs} "				\
+		"console=ttyS0,${baudrate} "				\
+		"panic=1\0"						\
+	"flash_nfs=run nfsargs addip addmisc;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip addmisc;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};"				\
+		"run nfsargs addip addmisc;bootm\0"			\
+	"rootpath=/opt/eldk/ppc_4xx\0"					\
+	"bootfile=/tftpboot/g2000/pImage\0"				\
+	"kernel_addr=ff800000\0"				        \
+	"ramdisk_addr=ff900000\0"				        \
+	"pciconfighost=yes\0"				                \
+	""
+#define CONFIG_BOOTCOMMAND	"run net_nfs"
+
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+
+#define CONFIG_PPC4xx_EMAC
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_PHY1_ADDR	1	/* PHY address			*/
+
+#if 0 /* test-only */
+#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
+#endif
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_EEPROM
+
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#if 0 /* test-only */
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+
+#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CONFIG_SYS_BASE_BAUD	    691200
+
+/* The following table includes the supported baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+#define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+
+/*----------------------------------------------------------------------------*/
+/* adding Ethernet setting:  FTS OUI 00:11:0B */
+/*----------------------------------------------------------------------------*/
+#define CONFIG_ETHADDR          00:11:0B:00:00:01
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR         00:11:0B:00:00:02
+#define CONFIG_IPADDR		10.48.8.178
+#define CONFIG_IP1ADDR		10.48.8.188
+#define CONFIG_NETMASK		255.255.255.128
+#define CONFIG_SERVERIP		10.48.8.138
+
+/*-----------------------------------------------------------------------
+ * RTC stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_RTC_DS1337
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68
+
+#if 0 /* test-only */
+/*-----------------------------------------------------------------------
+ * NAND-FLASH stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
+
+#define CONFIG_SYS_NAND_CE  (0x80000000 >> 1)	/* our CE is GPIO1 */
+#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2)	/* our CLE is GPIO2 */
+#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3)	/* our ALE is GPIO3 */
+#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4)	/* our RDY is GPIO4 */
+
+#endif
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
+#define PCI_HOST_FORCE  1               /* configure as pci host        */
+#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_HOST	PCI_HOST_HOST   /* select pci host function     */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
+					/* resource configuration       */
+
+#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
+
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
+#define CONFIG_SYS_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
+#define CONFIG_SYS_PCI_PTM1LA  0x00000000      /* point to sdram               */
+#define CONFIG_SYS_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CONFIG_SYS_PCI_PTM2LA  0xffc00000      /* point to flash               */
+#define CONFIG_SYS_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
+#define CONFIG_SYS_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#if 0 /* APC405 */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#undef CONFIG_SYS_FLASH_PROTECTION		/* don't use hardware protection	*/
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+#define CONFIG_SYS_FLASH_BASE		0xFE000000 /* test-only...*/
+#define CONFIG_SYS_FLASH_INCREMENT	0x01000000 /* test-only */
+#else /* G2000 */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#undef CONFIG_SYS_FLASH_PROTECTION		/* don't use hardware protection	*/
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+#define CONFIG_SYS_FLASH_BASE		0xFF800000 /* test-only...*/
+#define CONFIG_SYS_FLASH_INCREMENT	0x01000000 /* test-only */
+#endif
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
+
+#define CONFIG_SYS_JFFS2_FIRST_BANK    0           /* use for JFFS2 */
+#define CONFIG_SYS_JFFS2_NUM_BANKS     1           /* ! second bank contains u-boot    */
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_MONITOR_BASE	0xFFFC0000
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
+
+/*-----------------------------------------------------------------------
+ * Environment Variable setup
+ */
+#if 1 /* test-only */
+#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CONFIG_ENV_OFFSET		0x100	/* environment starts at the beginning of the EEPROM */
+#define CONFIG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
+				   /* total size of a CAT24WC16 is 2048 bytes */
+
+#else	/* DEFAULT: environment in flash, using redundand flash sectors */
+
+#define CONFIG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars */
+#define CONFIG_ENV_ADDR		0xFFFA0000 /* environment starts before u-boot */
+#define CONFIG_ENV_SECT_SIZE	0x20000	/* 128k bytes may be used for env vars*/
+
+#endif
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT24WC08		*/
+/* CAT24WC08/16... */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last 4 bits of the address	*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Intel Strata Flash) initialization                            */
+#define CONFIG_SYS_EBC_PB0AP   0x92015480
+#define CONFIG_SYS_EBC_PB0CR   0xFF87A000          /* BAS=0xFF8,BS=08MB,BU=R/W,BW=16bit*/
+
+/* Memory Bank 1 ( Power TAU) initialization               */
+/* #define CONFIG_SYS_EBC_PB1AP           0x04041000 */
+/* #define CONFIG_SYS_EBC_PB1CR           0xF0018000   */  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
+#define CONFIG_SYS_EBC_PB1AP           0x00000000
+#define CONFIG_SYS_EBC_PB1CR           0x00000000
+
+/* Memory Bank 2 (Intel Flash) initialization                 */
+#define CONFIG_SYS_EBC_PB2AP           0x00000000
+#define CONFIG_SYS_EBC_PB2CR           0x00000000
+
+/* Memory Bank 3 (NAND) initialization                        */
+#define CONFIG_SYS_EBC_PB3AP           0x92015480
+#define CONFIG_SYS_EBC_PB3CR           0xF40B8000  /*addr 0xF40, BS=32M,BU=R/W, BW=8bit */
+
+/* Memory Bank 4 (FPGA regs) initialization                                     */
+#define CONFIG_SYS_EBC_PB4AP           0x00000000
+#define CONFIG_SYS_EBC_PB4CR           0x00000000  /* leave it blank  */
+
+#define CONFIG_SYS_NAND_BASE   0xF4000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CONFIG_SYS_TEMP_STACK_OCM	  1
+
+/* On Chip Memory location */
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
+
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO setup (PPC405EP specific)
+ *
+ * GPIO0[0]     - External Bus Controller BLAST output
+ * GPIO0[1-9]   - Instruction trace outputs
+ * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
+ * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
+ * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
+ * GPIO0[24-27] - UART0 control signal inputs/outputs
+ * GPIO0[28-29] - UART1 data signal input/output
+ * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
+ *
+ * following GPIO setting changed for G20000, 080304
+ */
+#define CONFIG_SYS_GPIO0_OSRL          0x40005555
+#define CONFIG_SYS_GPIO0_OSRH          0x40000110
+#define CONFIG_SYS_GPIO0_ISR1L         0x00000000
+#define CONFIG_SYS_GPIO0_ISR1H         0x15555445
+#define CONFIG_SYS_GPIO0_TSRL          0x00000000
+#define CONFIG_SYS_GPIO0_TSRH          0x00000000
+#define CONFIG_SYS_GPIO0_TCR           0xF7FF8014
+
+/*
+ * Default speed selection (cpu_plb_opb_ebc) in mhz.
+ * This value will be set if iic boot eprom is disabled.
+ */
+#if 1
+#define PLLMR0_DEFAULT	 PLLMR0_266_66_33_33
+#define PLLMR1_DEFAULT	 PLLMR1_266_66_33_33
+#endif
+#if 0
+#define PLLMR0_DEFAULT	 PLLMR0_266_133_66_33
+#define PLLMR1_DEFAULT	 PLLMR1_266_133_66_33
+#endif
+#if 0
+#define PLLMR0_DEFAULT	 PLLMR0_200_100_50_33
+#define PLLMR1_DEFAULT	 PLLMR1_200_100_50_33
+#endif
+#if 0
+#define PLLMR0_DEFAULT	 PLLMR0_133_66_66_33
+#define PLLMR1_DEFAULT	 PLLMR1_133_66_66_33
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/GEN860T.h b/qemu/roms/u-boot/include/configs/GEN860T.h
new file mode 100644
index 000000000..2822a08c0
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/GEN860T.h
@@ -0,0 +1,711 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Keith Outwater, keith_outwater@mvis.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config_GEN860T.h - board specific configuration options
+ */
+
+#ifndef __CONFIG_GEN860T_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_MPC860
+#define CONFIG_GEN860T
+
+#define	CONFIG_SYS_TEXT_BASE		0x40000000
+
+/*
+ * Identify the board
+ */
+#if !defined(CONFIG_SC)
+#define CONFIG_IDENT_STRING		" B2"
+#else
+#define CONFIG_IDENT_STRING		" SC"
+#endif
+
+/*
+ * Don't depend on the RTC clock to determine clock frequency -
+ * the 860's internal rtc uses a 32.768 KHz clock which is
+ * generated by the DS1337 - and the DS1337 clock can be turned off.
+ */
+#if !defined(CONFIG_SC)
+#define	CONFIG_8xx_GCLK_FREQ		66600000
+#else
+#define	CONFIG_8xx_GCLK_FREQ		48000000
+#endif
+
+/*
+ * The RS-232 console port is on SMC1
+ */
+#define	CONFIG_8xx_CONS_SMC1
+#define CONFIG_BAUDRATE			38400
+
+/*
+ * Print console information
+ */
+#undef	 CONFIG_SYS_CONSOLE_INFO_QUIET
+
+/*
+ * Set the autoboot delay in seconds.  A delay of -1 disables autoboot
+ */
+#define CONFIG_BOOTDELAY				5
+
+/*
+ * Pass the clock frequency to the Linux kernel in units of MHz
+ */
+#define	CONFIG_CLOCKS_IN_MHZ
+
+#define CONFIG_PREBOOT		\
+	"echo;echo"
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND	\
+	"bootp;" \
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
+	"bootm"
+
+/*
+ * Turn off echo for serial download by default.  Allow baud rate to be changed
+ * for downloads
+ */
+#undef	CONFIG_LOADS_ECHO
+#define	CONFIG_SYS_LOADS_BAUD_CHANGE
+
+/*
+ * Turn off the watchdog timer
+ */
+#undef	CONFIG_WATCHDOG
+
+/*
+ * Do not reboot if a panic occurs
+ */
+#define CONFIG_PANIC_HANG
+
+/*
+ * Enable the status LED
+ */
+#define	CONFIG_STATUS_LED
+
+/*
+ * Reset address. We pick an address such that when an instruction
+ * is executed at that address, a machine check exception occurs
+ */
+#define CONFIG_SYS_RESET_ADDRESS				((ulong) -1)
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * The GEN860T network interface uses the on-chip 10/100 FEC with
+ * an Intel LXT971A PHY connected to the 860T's MII. The PHY's
+ * MII address is hardwired on the board to zero.
+ */
+#define CONFIG_FEC_ENET
+#define CONFIG_SYS_DISCOVER_PHY
+#define CONFIG_MII
+#define CONFIG_MII_INIT			1
+#define CONFIG_PHY_ADDR			0
+
+/*
+ * Set default IP stuff just to get bootstrap entries into the
+ * environment so that we can source the full default environment.
+ */
+#define CONFIG_ETHADDR					9a:52:63:15:85:25
+#define CONFIG_SERVERIP					10.0.4.201
+#define CONFIG_IPADDR					10.0.4.111
+
+/*
+ * This board has a 32 kibibyte EEPROM (Atmel AT24C256) connected to
+ * the MPC860T I2C interface.
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR				0x50
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS		6		/* 64 byte pages		*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	12		/* 10 mS w/ 20% margin	*/
+#define	CONFIG_SYS_I2C_EEPROM_ADDR_LEN			2		/* need 16 bit address	*/
+#define CONFIG_ENV_EEPROM_SIZE				(32 * 1024)
+
+/*
+ * Enable I2C and select the hardware/software driver
+ */
+#define CONFIG_HARD_I2C		1		/* CPM based I2C */
+#undef	CONFIG_SYS_I2C_SOFT			/* Bit-banged I2C */
+
+#ifdef CONFIG_HARD_I2C
+#define	CONFIG_SYS_I2C_SPEED		100000	/* clock speed in Hz */
+#define CONFIG_SYS_I2C_SLAVE		0xFE	/* I2C slave address */
+#endif
+
+#ifdef CONFIG_SYS_I2C_SOFT
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT_SPEED	50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
+#define PB_SCL		0x00000020		/* PB 26 */
+#define PB_SDA		0x00000010		/* PB 27 */
+#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
+#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
+#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
+#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+#define I2C_SDA(bit)	if (bit) \
+				immr->im_cpm.cp_pbdat |=  PB_SDA; \
+			else \
+				immr->im_cpm.cp_pbdat &= ~PB_SDA
+#define I2C_SCL(bit)	if (bit) \
+				immr->im_cpm.cp_pbdat |=  PB_SCL; \
+			else \
+				immr->im_cpm.cp_pbdat &= ~PB_SCL
+#define I2C_DELAY	udelay(5) /* 1/4 I2C clock duration */
+#endif
+
+/*
+ * Allow environment overwrites by anyone
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#if !defined(CONFIG_SC)
+/*
+ * The MPC860's internal RTC is horribly broken in rev D masks. Three
+ * internal MPC860T circuit nodes were inadvertently left floating; this
+ * causes KAPWR current in power down mode to be three orders of magnitude
+ * higher than specified in the datasheet (from 10 uA to 10 mA).  No
+ * reasonable battery can keep that kind RTC running during powerdown for any
+ * length of time, so we use an external RTC on the I2C bus instead.
+ */
+#define CONFIG_RTC_DS1337
+#define CONFIG_SYS_I2C_RTC_ADDR				0x68
+
+#else
+/*
+ * No external RTC on SC variant, so we're stuck with the internal one.
+ */
+#define	CONFIG_RTC_MPC8xx
+#endif
+
+/*
+ * Power On Self Test support
+ */
+#define CONFIG_POST			  ( CONFIG_SYS_POST_CACHE		| \
+								CONFIG_SYS_POST_MEMORY		| \
+								CONFIG_SYS_POST_CPU		| \
+								CONFIG_SYS_POST_UART		| \
+								CONFIG_SYS_POST_SPR )
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_FPGA
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_BEDBUG
+
+#ifdef CONFIG_POST
+#define CONFIG_CMD_DIAG
+#endif
+
+/*
+ * There is no IDE/PCMCIA hardware support on the board.
+ */
+#undef  CONFIG_IDE_PCMCIA
+#undef  CONFIG_IDE_LED
+#undef  CONFIG_IDE_RESET
+
+/*
+ * Enable the call to misc_init_r() for miscellaneous platform
+ * dependent initialization.
+ */
+#define CONFIG_MISC_INIT_R
+
+/*
+ * Enable call to last_stage_init() so we can twiddle some LEDS :)
+ */
+#define CONFIG_LAST_STAGE_INIT
+
+/*
+ * Virtex2 FPGA configuration support
+ */
+#define CONFIG_FPGA_COUNT		1
+#define CONFIG_FPGA
+#define CONFIG_FPGA_XILINX
+#define CONFIG_FPGA_VIRTEX2
+#define CONFIG_SYS_FPGA_PROG_FEEDBACK
+
+/*
+ * Verbose help from command monitor.
+ */
+#define	CONFIG_SYS_LONGHELP
+#if !defined(CONFIG_SC)
+#define	CONFIG_SYS_PROMPT			"B2> "
+#else
+#define	CONFIG_SYS_PROMPT			"SC> "
+#endif
+
+
+/*
+ * Use the "hush" command parser
+ */
+#define	CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Set buffer size for console I/O
+ */
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE			1024
+#else
+#define	CONFIG_SYS_CBSIZE			256
+#endif
+
+/*
+ * Print buffer size
+ */
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/*
+ * Maximum number of arguments that a command can accept
+ */
+#define	CONFIG_SYS_MAXARGS			16
+
+/*
+ * Boot argument buffer size
+ */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+/*
+ * Default memory test range
+ */
+#define CONFIG_SYS_MEMTEST_START	0x0100000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START  + (128 * 1024))
+
+/*
+ * Select the more full-featured memory test
+ */
+#define	CONFIG_SYS_ALT_MEMTEST
+
+/*
+ * Default load address
+ */
+#define	CONFIG_SYS_LOAD_ADDR		0x01000000
+
+/*
+ * Device memory map (after SDRAM remap to 0x0):
+ *
+ * CS		Device				Base Addr	Size
+ * ----------------------------------------------------
+ * CS0*		Flash				0x40000000	64 M
+ * CS1*		SDRAM				0x00000000	16 M
+ * CS2*		Disk-On-Chip		0x50000000	32 K
+ * CS3*		FPGA				0x60000000	64 M
+ * CS4*		SelectMap			0x70000000	32 K
+ * CS5*		Mil-Std 1553 I/F	0x80000000	32 K
+ * CS6*		Unused
+ * CS7*		Unused
+ * IMMR		860T Registers		0xfff00000
+ */
+
+/*
+ * Base addresses and block sizes
+ */
+#define CONFIG_SYS_IMMR			0xFF000000
+
+#define SDRAM_BASE			0x00000000
+#define SDRAM_SIZE			(64 * 1024 * 1024)
+
+#define FLASH_BASE			0x40000000
+#define FLASH_SIZE			(16 * 1024 * 1024)
+
+#define DOC_BASE			0x50000000
+#define DOC_SIZE			(32 * 1024)
+
+#define FPGA_BASE			0x60000000
+#define FPGA_SIZE			(64 * 1024 * 1024)
+
+#define SELECTMAP_BASE		0x70000000
+#define SELECTMAP_SIZE		(32 * 1024)
+
+#define M1553_BASE			0x80000000
+#define M1553_SIZE			(64 * 1024)
+
+/*
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR		CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_SIZE		0x2F00	/* Size of used area in DPRAM		*/
+#define	CONFIG_SYS_INIT_DATA_SIZE		64	/* # bytes reserved for initial data*/
+#define CONFIG_SYS_GBL_DATA_OFFSET		(CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET		CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define	CONFIG_SYS_SDRAM_BASE			SDRAM_BASE
+
+/*
+ * FLASH organization
+ */
+#define CONFIG_SYS_FLASH_BASE			FLASH_BASE
+#define CONFIG_SYS_FLASH_SIZE			FLASH_SIZE
+#define CONFIG_SYS_FLASH_SECT_SIZE		(128 * 1024)
+#define CONFIG_SYS_MAX_FLASH_BANKS		1
+#define CONFIG_SYS_MAX_FLASH_SECT		128
+
+/*
+ * The timeout values are for an entire chip and are in milliseconds.
+ * Yes I know that the write timeout is huge.  Accroding to the
+ * datasheet a single byte takes 630 uS (round to 1 ms) max at worst
+ * case VCC and temp after 100K programming cycles.  It works out
+ * to 280 minutes (might as well be forever).
+ */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(CONFIG_SYS_MAX_FLASH_SECT * 5000)
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(CONFIG_SYS_MAX_FLASH_SECT * 128 * 1024 * 1)
+
+/*
+ * Allow direct writes to FLASH from tftp transfers (** dangerous **)
+ */
+#define	CONFIG_SYS_DIRECT_FLASH_TFTP
+
+/*
+ * Reserve memory for U-Boot.
+ */
+#define CONFIG_SYS_MAX_UBOOT_SECTS		4
+#define	CONFIG_SYS_MONITOR_LEN			(CONFIG_SYS_MAX_UBOOT_SECTS * CONFIG_SYS_FLASH_SECT_SIZE)
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+
+/*
+ * Select environment placement.  NOTE that u-boot.lds must
+ * be edited if this is changed!
+ */
+#undef	CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_IS_IN_EEPROM
+
+#if defined(CONFIG_ENV_IS_IN_EEPROM)
+#define CONFIG_ENV_SIZE			(2 * 1024)
+#define CONFIG_ENV_OFFSET			(CONFIG_ENV_EEPROM_SIZE - (8 * 1024))
+#else
+#define CONFIG_ENV_SIZE			0x1000
+#define CONFIG_ENV_SECT_SIZE		CONFIG_SYS_FLASH_SECT_SIZE
+
+/*
+ * This ultimately gets passed right into the linker script, so we have to
+ * use a number :(
+ */
+#define CONFIG_ENV_OFFSET			0x060000
+#endif
+
+/*
+ * Reserve memory for malloc()
+ */
+#define	CONFIG_SYS_MALLOC_LEN		(128 * 1024)
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
+
+/*
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE		16	/* For all MPC8xx CPUs				*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT		4	/* log base 2 of above value		*/
+#endif
+
+/*------------------------------------------------------------------------
+ * SYPCR - System Protection Control							UM 11-9
+ * -----------------------------------------------------------------------
+ * SYPCR can only be written once after reset!
+ *
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR	( SYPCR_SWTC	| \
+					  SYPCR_BMT	| \
+					  SYPCR_BME	| \
+					  SYPCR_SWF	| \
+					  SYPCR_SWE	| \
+					  SYPCR_SWRI	| \
+					  SYPCR_SWP		  \
+					)
+#else
+#define CONFIG_SYS_SYPCR	( SYPCR_SWTC	| \
+					  SYPCR_BMT	| \
+					  SYPCR_BME	| \
+					  SYPCR_SWF	| \
+					  SYPCR_SWP		  \
+					)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration							UM 11-6
+ *-----------------------------------------------------------------------
+ * Set debug pin mux, enable SPKROUT and GPLB5*.
+ */
+#define CONFIG_SYS_SIUMCR	( SIUMCR_DBGC11 | \
+					  SIUMCR_DBPC11 | \
+					  SIUMCR_MLRC11	| \
+					  SIUMCR_GB5E	  \
+					)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control							UM 11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freeze enabled
+ */
+#define CONFIG_SYS_TBSCR	( TBSCR_REFA | \
+					  TBSCR_REFB | \
+					  TBSCR_TBF	   \
+					)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register			UM 11-27
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RTCSC	( RTCSC_SEC	| \
+					  RTCSC_ALR | \
+					  RTCSC_RTF | \
+					  RTCSC_RTE	  \
+					)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control				UM 11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CONFIG_SYS_PISCR	( PISCR_PS		| \
+					  PISCR_PITF	  \
+					)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register			UM 15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit. Set MF for 1:2:1 mode.
+ */
+#define CONFIG_SYS_PLPRCR	( ((0x1 << PLPRCR_MF_SHIFT) & PLPRCR_MF_MSK)	| \
+					  PLPRCR_SPLSS	| \
+					  PLPRCR_TEXPS	| \
+					  PLPRCR_TMIST	  \
+					)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register				UM 15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK   SCCR_EBDF11
+
+#if !defined(CONFIG_SC)
+#define CONFIG_SYS_SCCR	( SCCR_TBS			|	/* timebase = GCLK/2	*/ \
+					  SCCR_COM00		|	/* full strength CLKOUT	*/ \
+					  SCCR_DFSYNC00	|	/* SYNCLK / 1 (normal)	*/ \
+					  SCCR_DFBRG00		|	/* BRGCLK / 1 (normal)	*/ \
+					  SCCR_DFNL000		| \
+					  SCCR_DFNH000		  \
+					)
+#else
+#define CONFIG_SYS_SCCR	( SCCR_TBS			|	/* timebase = GCLK/2	*/ \
+					  SCCR_COM00		|	/* full strength CLKOUT	*/ \
+					  SCCR_DFSYNC00	|	/* SYNCLK / 1 (normal)	*/ \
+					  SCCR_DFBRG00		|	/* BRGCLK / 1 (normal)	*/ \
+					  SCCR_DFNL000		| \
+					  SCCR_DFNH000		| \
+					  SCCR_RTDIV		| \
+					  SCCR_RTSEL		  \
+					)
+#endif
+
+/*-----------------------------------------------------------------------
+ * DER - Debug Enable Register									UM 37-46
+ *-----------------------------------------------------------------------
+ * Mask all events that can cause entry into debug mode
+ */
+#define CONFIG_SYS_DER				0
+
+/*
+ * Initialize Memory Controller:
+ *
+ * BR0 and OR0 (FLASH memory)
+ */
+#define FLASH_BASE0_PRELIM	FLASH_BASE
+
+/*
+ * Flash address mask
+ */
+#define CONFIG_SYS_PRELIM_OR_AM	0xfe000000
+
+/*
+ * FLASH timing:
+ * 33 Mhz bus with ACS = 11, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1
+ */
+#define CONFIG_SYS_OR_TIMING_FLASH	( OR_CSNT_SAM	| \
+							  OR_ACS_DIV2	| \
+							  OR_BI			| \
+							  OR_SCY_2_CLK	| \
+							  OR_TRLX		| \
+							  OR_EHTR		  \
+							)
+
+#define CONFIG_SYS_OR0_PRELIM	( CONFIG_SYS_PRELIM_OR_AM		| \
+						  CONFIG_SYS_OR_TIMING_FLASH	  \
+						)
+
+#define CONFIG_SYS_BR0_PRELIM	( (FLASH_BASE0_PRELIM & BR_BA_MSK)	| \
+						  BR_MS_GPCM						| \
+						  BR_PS_8							| \
+						  BR_V								  \
+						)
+
+/*
+ * SDRAM configuration
+ */
+#define CONFIG_SYS_OR1_AM	0xfc000000
+#define CONFIG_SYS_OR1		( (CONFIG_SYS_OR1_AM & OR_AM_MSK)	| \
+					  OR_CSNT_SAM				  \
+					)
+
+#define CONFIG_SYS_BR1		( (SDRAM_BASE & BR_BA_MSK)	| \
+					  BR_MS_UPMA				| \
+					  BR_PS_32					| \
+					  BR_V						  \
+					)
+
+/*
+ * Refresh rate 7.8 us (= 64 ms / 8K = 31.2 uS quad bursts) for one bank
+ * of 256 MBit SDRAM
+ */
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16
+
+/*
+ * Periodic timer for refresh @ 33 MHz system clock
+ */
+#define CONFIG_SYS_MAMR_PTA	64
+
+/*
+ * MAMR settings for SDRAM
+ */
+#define CONFIG_SYS_MAMR_8COL	( (CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)	| \
+						  MAMR_PTAE				| \
+						  MAMR_AMA_TYPE_1			| \
+						  MAMR_DSA_1_CYCL			| \
+						  MAMR_G0CLA_A10			| \
+						  MAMR_RLFA_1X				| \
+						  MAMR_WLFA_1X				| \
+						  MAMR_TLFA_4X				  \
+						)
+
+/*
+ * CS2* configuration for Disk On Chip:
+ * 33 MHz bus with TRLX=1, ACS=11, CSNT=1, EBDF=1, SCY=2, EHTR=1,
+ * no burst.
+ */
+#define CONFIG_SYS_OR2_PRELIM	( (0xffff0000 & OR_AM_MSK)	| \
+						  OR_CSNT_SAM				| \
+						  OR_ACS_DIV2				| \
+						  OR_BI						| \
+						  OR_SCY_2_CLK				| \
+						  OR_TRLX					| \
+						  OR_EHTR					  \
+						)
+
+#define CONFIG_SYS_BR2_PRELIM	( (DOC_BASE & BR_BA_MSK)	| \
+						  BR_PS_8					| \
+						  BR_MS_GPCM				| \
+						  BR_V						  \
+						)
+
+/*
+ * CS3* configuration for FPGA:
+ * 33 MHz bus with SCY=15, no burst.
+ * The FPGA uses TA and TEA to terminate bus cycles, but we
+ * clear SETA and set the cycle length to a large number so that
+ * the cycle will still complete even if there is a configuration
+ * error that prevents TA from asserting on FPGA accesss.
+ */
+#define CONFIG_SYS_OR3_PRELIM	( (0xfc000000 & OR_AM_MSK)  | \
+						  OR_SCY_15_CLK				| \
+						  OR_BI					  \
+						)
+
+#define CONFIG_SYS_BR3_PRELIM	( (FPGA_BASE & BR_BA_MSK)	| \
+						  BR_PS_32					| \
+						  BR_MS_GPCM				| \
+						  BR_V						  \
+						)
+/*
+ * CS4* configuration for FPGA SelectMap configuration interface.
+ * 33 MHz bus, UPMB, no burst. Do not assert GPLB5 on falling edge
+ * of GCLK1_50
+ */
+#define CONFIG_SYS_OR4_PRELIM	( (0xffff0000 & OR_AM_MSK)	| \
+						  OR_G5LS						| \
+						  OR_BI							  \
+						)
+
+#define CONFIG_SYS_BR4_PRELIM	( (SELECTMAP_BASE & BR_BA_MSK)	| \
+						  BR_PS_8						| \
+						  BR_MS_UPMB					| \
+						  BR_V							  \
+						)
+
+/*
+ * CS5* configuration for Mil-Std 1553 databus interface.
+ * 33 MHz bus, GPCM, no burst.
+ * The 1553 interface  uses TA and TEA to terminate bus cycles,
+ * but we clear SETA and set the cycle length to a large number so that
+ * the cycle will still complete even if there is a configuration
+ * error that prevents TA from asserting on FPGA accesss.
+ */
+#define CONFIG_SYS_OR5_PRELIM	( (0xffff0000 & OR_AM_MSK)  | \
+						  OR_SCY_15_CLK				| \
+						  OR_EHTR					| \
+						  OR_TRLX					| \
+						  OR_CSNT_SAM				| \
+						  OR_BI						  \
+						)
+
+#define CONFIG_SYS_BR5_PRELIM	( (M1553_BASE & BR_BA_MSK)	| \
+						  BR_PS_16					| \
+						  BR_MS_GPCM				| \
+						  BR_V						  \
+						)
+
+/*
+ * FEC interrupt assignment
+ */
+#define FEC_INTERRUPT   SIU_LEVEL1
+
+/*
+ * Sanity checks
+ */
+#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
+#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
+#endif
+
+#endif	/* __CONFIG_GEN860T_H */
diff --git a/qemu/roms/u-boot/include/configs/HH405.h b/qemu/roms/u-boot/include/configs/HH405.h
new file mode 100644
index 000000000..033dcbfe2
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/HH405.h
@@ -0,0 +1,479 @@
+/*
+ * (C) Copyright 2001-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2006
+ * Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_HH405		1	/* ...on a HH405 board	        */
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFF80000
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
+
+#define CONFIG_SYS_CLK_FREQ     33333400 /* external frequency to pll   */
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+#undef	CONFIG_BOOTARGS
+#undef	CONFIG_BOOTCOMMAND
+
+#define CONFIG_PREBOOT	        "autoupd"
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"pciconfighost=1\0"						\
+	""
+
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_PPC4xx_EMAC
+#undef  CONFIG_HAS_ETH1
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
+
+#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
+
+/*
+ * Video console
+ */
+#define CONFIG_VIDEO			/* for sm501 video support	*/
+
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO_SM501
+#if 0
+#define CONFIG_VIDEO_SM501_32BPP
+#else
+#define CONFIG_VIDEO_SM501_16BPP
+#endif
+#define CONFIG_VIDEO_SM501_FBMEM_OFFSET 0x10000
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_CONSOLE_EXTRA_INFO
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_VIDEO_BMP_GZIP		/* gzip compressed bmp images	*/
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(2 << 20)	/* for decompressed img */
+
+#endif /* CONFIG_VIDEO */
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_EEPROM
+
+#ifdef CONFIG_VIDEO
+#define CONFIG_CMD_BMP
+#endif
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_SUPPORT_VFAT
+
+#define CONFIG_AUTO_UPDATE      1       /* autoupdate via compactflash  */
+#undef CONFIG_AUTO_UPDATE_SHOW          /* use board show routine       */
+
+#undef  CONFIG_BZIP2	 /* include support for bzip2 compressed images */
+#undef  CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+
+#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_DEVICE_NULLDEV      1       /* include nulldev device       */
+
+#undef  CONFIG_SYS_CONSOLE_INFO_QUIET          /* print console @ startup	*/
+
+#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CONFIG_CONS_INDEX	2	/* Use UART1			*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+
+#undef  CONFIG_SYS_EXT_SERIAL_CLOCK           /* no external serial clock used */
+#define CONFIG_SYS_BASE_BAUD       691200
+
+/* The following table includes the supported baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE      \
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+#define CONFIG_VERSION_VARIABLE	1       /* include version env variable */
+
+#define CONFIG_SYS_RX_ETH_BUFFER	16      /* use 16 rx buffer on 405 emac */
+
+/*-----------------------------------------------------------------------
+ * RTC stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_RTC_DS1338
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68
+
+/*-----------------------------------------------------------------------
+ * NAND-FLASH stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1         /* Max number of NAND devices */
+#define NAND_BIG_DELAY_US	25
+
+#define CONFIG_SYS_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
+#define CONFIG_SYS_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
+#define CONFIG_SYS_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
+#define CONFIG_SYS_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
+
+#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1       /* ".i" read skips bad blocks   */
+#define CONFIG_SYS_NAND_QUIET          1
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
+#define PCI_HOST_FORCE  1               /* configure as pci host        */
+#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_HOST	PCI_HOST_HOST   /* select pci host function     */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
+					/* resource configuration       */
+
+#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
+
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
+#define CONFIG_SYS_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
+#define CONFIG_SYS_PCI_PTM1LA  0x00000000      /* point to sdram               */
+#define CONFIG_SYS_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CONFIG_SYS_PCI_PTM2LA  0xffc00000      /* point to flash               */
+#define CONFIG_SYS_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
+#define CONFIG_SYS_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff
+ *-----------------------------------------------------------------------
+ */
+#undef  CONFIG_IDE_8xx_DIRECT               /* no pcmcia interface required */
+#undef  CONFIG_IDE_LED                  /* no led for ide supported     */
+#define CONFIG_IDE_RESET	1	/* reset for ide supported	*/
+
+#define	CONFIG_SYS_IDE_MAXBUS	        1		/* max. 1 IDE busses	*/
+#define	CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+
+#define	CONFIG_SYS_ATA_BASE_ADDR	0xF0100000
+#define	CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
+#define	CONFIG_SYS_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
+
+#define CONFIG_SYS_FLASH_WORD_SIZE     unsigned short  /* flash word size (width)      */
+#define CONFIG_SYS_FLASH_ADDR0         0x5555  /* 1st address for flash config cycles  */
+#define CONFIG_SYS_FLASH_ADDR1         0x2AAA  /* 2nd address for flash config cycles  */
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CONFIG_SYS_FLASH_READ0         0x0000  /* 0 is standard                        */
+#define CONFIG_SYS_FLASH_READ1         0x0001  /* 1 is standard                        */
+#define CONFIG_SYS_FLASH_READ2         0x0002  /* 2 is standard                        */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
+
+#if 0 /* test-only */
+#define CONFIG_SYS_JFFS2_FIRST_BANK    0           /* use for JFFS2 */
+#define CONFIG_SYS_JFFS2_NUM_BANKS     1           /* ! second bank contains U-Boot */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFF80000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(4 << 20)	/* Reserve 4 MB for malloc()	*/
+
+#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
+# define CONFIG_SYS_RAMBOOT		1
+#else
+# undef CONFIG_SYS_RAMBOOT
+#endif
+
+/*-----------------------------------------------------------------------
+ * Environment Variable setup
+ */
+#define CONFIG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
+#define CONFIG_ENV_OFFSET          0x100   /* environment starts at the beginning of the EEPROM */
+#define CONFIG_ENV_SIZE            0x700   /* 2048 bytes may be used for env vars*/
+				   /* total size of a CAT24WC16 is 2048 bytes */
+
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xF4080000		/* NVRAM base address	*/
+#define CONFIG_SYS_NVRAM_SIZE		0x8000		        /* NVRAM size		*/
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#if 0 /* test-only */
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
+#else
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		100000
+#endif
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT24WC08		*/
+#define CONFIG_SYS_EEPROM_WREN         1
+
+#if 1 /* test-only */
+/* CAT24WC08/16... */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"    */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last	4 bits of the address	*/
+#else
+/* CAT24WC32/64... */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"    */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x01
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5	/* The Catalyst CAT24WC32 has	*/
+					/* 32 byte page write mode using*/
+					/* last	5 bits of the address	*/
+#endif
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+#define CAN_BA          0xF0000000          /* CAN Base Address                 */
+#define LCD_BA          0xF1000000          /* Epson LCD Base Address           */
+#define CONFIG_SYS_NAND_BASE   0xF4000000          /* NAND FLASH Base Address          */
+#define CONFIG_SYS_NVRAM_BASE  0xF4080000          /* NVRAM Base Address               */
+
+/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization                       */
+#define CONFIG_SYS_EBC_PB0AP           0x92015480
+#define CONFIG_SYS_EBC_PB0CR           0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (Flash Bank 1, NAND-FLASH & NVRAM) initialization              */
+#define CONFIG_SYS_EBC_PB1AP           0x92015480
+#define CONFIG_SYS_EBC_PB1CR           0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit  */
+
+/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization              */
+#define CONFIG_SYS_EBC_PB2AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB2CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
+
+/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization     */
+#define CONFIG_SYS_EBC_PB3AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB3CR           0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 4 (Epson LCD) initialization                                     */
+#define CONFIG_SYS_EBC_PB4AP   0x03805380   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */
+#define CONFIG_SYS_EBC_PB4CR   LCD_BA | 0x7A000    /* BAS=0xF10,BS=8MB,BU=R/W,BW=16bit */
+
+/*-----------------------------------------------------------------------
+ * LCD Setup
+ */
+
+#define CONFIG_SYS_LCD_BIG_MEM         0xF1200000  /* Epson S1D13806 Mem Base Address  */
+#define CONFIG_SYS_LCD_BIG_REG         0xF1000000  /* Epson S1D13806 Reg Base Address  */
+#define CONFIG_SYS_LCD_SMALL_MEM       0xF1400000  /* Epson S1D13704 Mem Base Address  */
+#define CONFIG_SYS_LCD_SMALL_REG       0xF140FFE0  /* Epson S1D13704 Reg Base Address  */
+
+/*-----------------------------------------------------------------------
+ * Universal Interrupt Controller (UIC) Setup
+ */
+
+/*
+ * define UIC_EXT0 ... UIC_EXT6 if external interrupt is active high
+ */
+#define CONFIG_SYS_UIC0_POLARITY       (0xFFFFFF80 | UIC_MASK(VECNUM_EIRQ6))
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ */
+
+#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0100100       /* FPGA internal Base Address       */
+
+#define LCD_CLK_OFF             0x0000      /* Off                           */
+#define LCD_CLK_02083           0x1000      /* 2.083 MHz                     */
+#define LCD_CLK_03135           0x2000      /* 3.135 MHz                     */
+#define LCD_CLK_04165           0x3000      /* 4.165 MHz                     */
+#define LCD_CLK_06250           0x4000      /* 6.250 MHz                     */
+#define LCD_CLK_08330           0x5000      /* 8.330 MHz                     */
+#define LCD_CLK_12500           0x6000      /* 12.50 MHz                     */
+#define LCD_CLK_25000           0x7000      /* 25.00 MHz                     */
+
+#define CONFIG_SYS_FPGA_SPARTAN2       1           /* using Xilinx Spartan 2 now    */
+#define CONFIG_SYS_FPGA_MAX_SIZE       128*1024    /* 128kByte is enough for XC2S50E*/
+
+/* FPGA program pin configuration */
+#define CONFIG_SYS_FPGA_PRG            0x04000000  /* FPGA program pin (ppc output) */
+#define CONFIG_SYS_FPGA_CLK            0x02000000  /* FPGA clk pin (ppc output)     */
+#define CONFIG_SYS_FPGA_DATA           0x01000000  /* FPGA data pin (ppc output)    */
+#define CONFIG_SYS_FPGA_INIT           0x00010000  /* FPGA init pin (ppc input)     */
+#define CONFIG_SYS_FPGA_DONE           0x00008000  /* FPGA done pin (ppc input)     */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CONFIG_SYS_TEMP_STACK_OCM        1
+
+/* On Chip Memory location */
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
+
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO setup (PPC405EP specific)
+ *
+ * GPIO0[0]     - External Bus Controller BLAST output
+ * GPIO0[1-9]   - Instruction trace outputs -> GPIO
+ * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
+ * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
+ * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
+ * GPIO0[24-27] - UART0 control signal inputs/outputs
+ * GPIO0[28-29] - UART1 data signal input/output
+ * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
+ */
+#define CONFIG_SYS_GPIO0_OSRL		0x40000550
+#define CONFIG_SYS_GPIO0_OSRH		0x00000110
+#define CONFIG_SYS_GPIO0_ISR1L		0x00000000
+#define CONFIG_SYS_GPIO0_ISR1H		0x15555440
+#define CONFIG_SYS_GPIO0_TSRL		0x00000000
+#define CONFIG_SYS_GPIO0_TSRH		0x00000000
+#define CONFIG_SYS_GPIO0_TCR		0xF7FE0017
+
+#define CONFIG_SYS_LCD_ENDIAN		(0x80000000 >> 7)
+#define CONFIG_SYS_EEPROM_WP		(0x80000000 >> 8)   /* GPIO8 */
+#define CONFIG_SYS_TOUCH_RST		(0x80000000 >> 9)   /* GPIO9 */
+#define CONFIG_SYS_LCD0_RST		(0x80000000 >> 30)
+#define CONFIG_SYS_LCD1_RST		(0x80000000 >> 31)
+
+/*
+ * Default speed selection (cpu_plb_opb_ebc) in mhz.
+ * This value will be set if iic boot eprom is disabled.
+ */
+#if 0
+#define PLLMR0_DEFAULT   PLLMR0_266_133_66_33
+#define PLLMR1_DEFAULT   PLLMR1_266_133_66_33
+#endif
+#if 0
+#define PLLMR0_DEFAULT   PLLMR0_200_100_50_33
+#define PLLMR1_DEFAULT   PLLMR1_200_100_50_33
+#endif
+#if 1
+#define PLLMR0_DEFAULT   PLLMR0_133_66_66_33
+#define PLLMR1_DEFAULT   PLLMR1_133_66_66_33
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/HIDDEN_DRAGON.h b/qemu/roms/u-boot/include/configs/HIDDEN_DRAGON.h
new file mode 100644
index 000000000..e0a233b28
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/HIDDEN_DRAGON.h
@@ -0,0 +1,371 @@
+/*
+ * (C) Copyright 2004
+ * Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com
+ *
+ * (C) Copyright 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC8245		1
+#define CONFIG_HIDDEN_DRAGON	1
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
+
+#if 0
+#define USE_DINK32		1
+#else
+#undef USE_DINK32
+#endif
+
+#define CONFIG_CONS_INDEX	3		/* set to '3' for on-chip DUART */
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_DRAM_SPEED	100		/* MHz				*/
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		1		/* undef to save memory		*/
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size	*/
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address		*/
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_PCI				/* include pci support		*/
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#undef CONFIG_PCI_PNP
+
+
+#define CONFIG_SYS_RX_ETH_BUFFER	8		/* use 8 rx buffer on eepro100	*/
+
+#define PCI_ENET0_IOADDR	0x80000000
+#define PCI_ENET0_MEMADDR	0x80000000
+#define PCI_ENET1_IOADDR	0x81000000
+#define PCI_ENET1_MEMADDR	0x81000000
+
+#define CONFIG_RTL8139
+
+/* Make sure the ethaddr can be overwritten
+   TODO: Remove this on final product
+*/
+#define CONFIG_ENV_OVERWRITE
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_MAX_RAM_SIZE	0x02000000
+
+#define CONFIG_SYS_RESET_ADDRESS	0xFFF00100
+
+#if defined (USE_DINK32)
+#define CONFIG_SYS_MONITOR_LEN		0x00030000
+#define CONFIG_SYS_MONITOR_BASE	0x00090000
+#define CONFIG_SYS_RAMBOOT		1
+#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x10000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+#else
+#undef	CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_MONITOR_LEN		0x00030000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+
+
+#define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE      0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+#endif
+
+#define CONFIG_SYS_FLASH_BASE		0xFFE00000
+#define CONFIG_SYS_FLASH_SIZE		(2 * 1024 * 1024)	/* Unity has onboard 1MByte flash */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_OFFSET		0x00004000	/* Offset of Environment Sector */
+#define CONFIG_ENV_SIZE		0x00002000	/* Total Size of Environment Sector */
+
+#define CONFIG_SYS_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END		0x02000000	/* 0 ... 32 MB in DRAM		*/
+
+#define CONFIG_SYS_EUMB_ADDR		0xFC000000
+
+#define CONFIG_SYS_ISA_MEM		0xFD000000
+#define CONFIG_SYS_ISA_IO		0xFE000000
+
+#define CONFIG_SYS_FLASH_RANGE_BASE	0xFFE00000	/* flash memory address range	*/
+#define CONFIG_SYS_FLASH_RANGE_SIZE	0x00200000
+#define FLASH_BASE0_PRELIM	0xFFE00000	/* processor board flash	*/
+
+/*
+ * select i2c support configuration
+ *
+ * Supported configurations are {none, software, hardware} drivers.
+ * If the software driver is chosen, there are some additional
+ * configuration items that the driver uses to drive the port pins.
+ */
+#define CONFIG_HARD_I2C		1		/* To enable I2C support	*/
+#undef	CONFIG_SYS_I2C_SOFT			/* I2C bit-banged */
+#define CONFIG_SYS_I2C_SPEED		400000		/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+
+#ifdef CONFIG_SYS_I2C_SOFT
+#error "Soft I2C is not configured properly.  Please review!"
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT_SPEED	50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
+#define I2C_PORT		3		/* Port A=0, B=1, C=2, D=3 */
+#define I2C_ACTIVE		(iop->pdir |=  0x00010000)
+#define I2C_TRISTATE		(iop->pdir &= ~0x00010000)
+#define I2C_READ		((iop->pdat & 0x00010000) != 0)
+#define I2C_SDA(bit)		if(bit) iop->pdat |=  0x00010000; \
+				else	iop->pdat &= ~0x00010000
+#define I2C_SCL(bit)		if(bit) iop->pdat |=  0x00020000; \
+				else	iop->pdat &= ~0x00020000
+#define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
+#endif /* CONFIG_SYS_I2C_SOFT */
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57		/* EEPROM IS24C02		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1		/* Bytes of address		*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+
+#define CONFIG_SYS_FLASH_BANKS		{ FLASH_BASE0_PRELIM }
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+
+
+/* #define CONFIG_WINBOND_83C553	1	/ *has a winbond bridge			*/
+#define CONFIG_SYS_USE_WINBOND_IDE	0	/*use winbond 83c553 internal IDE ctrlr */
+#define CONFIG_SYS_WINBOND_ISA_CFG_ADDR    0x80005800	/*pci-isa bridge config addr	*/
+#define CONFIG_SYS_WINBOND_IDE_CFG_ADDR    0x80005900	/*ide config addr		*/
+
+#define CONFIG_SYS_IDE_MAXBUS		2   /* max. 2 IDE busses	*/
+#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
+
+/* TODO: Change this to VIA686A */
+
+/*
+ * NS87308 Configuration
+ */
+#define CONFIG_NS87308			/* Nat Semi super-io controller on ISA bus */
+
+#define CONFIG_SYS_NS87308_BADDR_10	1
+
+#define CONFIG_SYS_NS87308_DEVS	( CONFIG_SYS_NS87308_UART1   | \
+				  CONFIG_SYS_NS87308_UART2   | \
+				  CONFIG_SYS_NS87308_POWRMAN | \
+				  CONFIG_SYS_NS87308_RTC_APC )
+
+#undef	CONFIG_SYS_NS87308_PS2MOD
+
+#define CONFIG_SYS_NS87308_CS0_BASE	0x0076
+#define CONFIG_SYS_NS87308_CS0_CONF	0x30
+#define CONFIG_SYS_NS87308_CS1_BASE	0x0075
+#define CONFIG_SYS_NS87308_CS1_CONF	0x30
+#define CONFIG_SYS_NS87308_CS2_BASE	0x0074
+#define CONFIG_SYS_NS87308_CS2_CONF	0x30
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+
+#if (CONFIG_CONS_INDEX > 2)
+#define CONFIG_SYS_NS16550_CLK		CONFIG_DRAM_SPEED*1000000
+#else
+#define CONFIG_SYS_NS16550_CLK		1843200
+#endif
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART1_BASE)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART2_BASE)
+#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_EUMB_ADDR + 0x4500)
+#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_EUMB_ADDR + 0x4600)
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+#define CONFIG_SYS_CLK_FREQ  33333333	/* external frequency to pll */
+
+#define CONFIG_SYS_ROMNAL		7	/*rom/flash next access time		*/
+#define CONFIG_SYS_ROMFAL		11	/*rom/flash access time			*/
+
+#define CONFIG_SYS_REFINT	430	/* no of clock cycles between CBR refresh cycles */
+
+/* the following are for SDRAM only*/
+#define CONFIG_SYS_BSTOPRE	121	/* Burst To Precharge, sets open page interval */
+#define CONFIG_SYS_REFREC		8	/* Refresh to activate interval		*/
+#define CONFIG_SYS_RDLAT		4	/* data latency from read command	*/
+#define CONFIG_SYS_PRETOACT		3	/* Precharge to activate interval	*/
+#define CONFIG_SYS_ACTTOPRE		5	/* Activate to Precharge interval	*/
+#define CONFIG_SYS_ACTORW		3	/* Activate to R/W			*/
+#define CONFIG_SYS_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
+#define CONFIG_SYS_SDMODE_WRAP		0	/* SDMODE wrap type			*/
+#if 0
+#define CONFIG_SYS_SDMODE_BURSTLEN	2	/* OBSOLETE!  SDMODE Burst length 2=4, 3=8		*/
+#endif
+
+#define CONFIG_SYS_REGISTERD_TYPE_BUFFER   1
+#define CONFIG_SYS_EXTROM 1
+#define CONFIG_SYS_REGDIMM 0
+
+
+/* memory bank settings*/
+/*
+ * only bits 20-29 are actually used from these vales to set the
+ * start/end address the upper two bits will be 0, and the lower 20
+ * bits will be set to 0x00000 for a start address, or 0xfffff for an
+ * end address
+ */
+#define CONFIG_SYS_BANK0_START		0x00000000
+#define CONFIG_SYS_BANK0_END		(CONFIG_SYS_MAX_RAM_SIZE - 1)
+#define CONFIG_SYS_BANK0_ENABLE	1
+#define CONFIG_SYS_BANK1_START		0x3ff00000
+#define CONFIG_SYS_BANK1_END		0x3fffffff
+#define CONFIG_SYS_BANK1_ENABLE	0
+#define CONFIG_SYS_BANK2_START		0x3ff00000
+#define CONFIG_SYS_BANK2_END		0x3fffffff
+#define CONFIG_SYS_BANK2_ENABLE	0
+#define CONFIG_SYS_BANK3_START		0x3ff00000
+#define CONFIG_SYS_BANK3_END		0x3fffffff
+#define CONFIG_SYS_BANK3_ENABLE	0
+#define CONFIG_SYS_BANK4_START		0x00000000
+#define CONFIG_SYS_BANK4_END		0x00000000
+#define CONFIG_SYS_BANK4_ENABLE	0
+#define CONFIG_SYS_BANK5_START		0x00000000
+#define CONFIG_SYS_BANK5_END		0x00000000
+#define CONFIG_SYS_BANK5_ENABLE	0
+#define CONFIG_SYS_BANK6_START		0x00000000
+#define CONFIG_SYS_BANK6_END		0x00000000
+#define CONFIG_SYS_BANK6_ENABLE	0
+#define CONFIG_SYS_BANK7_START		0x00000000
+#define CONFIG_SYS_BANK7_END		0x00000000
+#define CONFIG_SYS_BANK7_ENABLE	0
+/*
+ * Memory bank enable bitmask, specifying which of the banks defined above
+ are actually present. MSB is for bank #7, LSB is for bank #0.
+ */
+#define CONFIG_SYS_BANK_ENABLE		0x01
+
+#define CONFIG_SYS_ODCR		0xff	/* configures line driver impedances,	*/
+					/* see 8240 book for bit definitions	*/
+#define CONFIG_SYS_PGMAX		0x32	/* how long the 8240 retains the	*/
+					/* currently accessed page in memory	*/
+					/* see 8240 book for details		*/
+
+/* SDRAM 0 - 256MB */
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* stack in DCACHE @ 1GB (no backing mem) */
+#if defined(USE_DINK32)
+#define CONFIG_SYS_IBAT1L	(0x40000000 | BATL_PP_00 )
+#define CONFIG_SYS_IBAT1U	(0x40000000 | BATU_BL_128K )
+#else
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#endif
+
+/* PCI memory */
+#define CONFIG_SYS_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* Flash, config addrs, etc */
+#define CONFIG_SYS_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	36	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8240 CPU			*/
+#if defined(CONFIG_CMD_KGDB)
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/* values according to the manual */
+#define CONFIG_DRAM_50MHZ	1
+#define CONFIG_SDRAM_50MHZ
+
+#undef	NR_8259_INTS
+#define NR_8259_INTS		1
+
+#define CONFIG_DISK_SPINUP_TIME 1000000
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/HUB405.h b/qemu/roms/u-boot/include/configs/HUB405.h
new file mode 100644
index 000000000..1783b9ff1
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/HUB405.h
@@ -0,0 +1,351 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_HUB405		1	/* ...on a HUB405 board		*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
+
+#define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+#undef	CONFIG_BOOTARGS
+#undef  CONFIG_BOOTCOMMAND
+
+#define CONFIG_PREBOOT                  /* enable preboot variable      */
+
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_PPC4xx_EMAC
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+
+#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_EEPROM
+
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+
+#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CONFIG_SYS_BASE_BAUD	    691200
+
+/* The following table includes the supported baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+#define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+
+/* Ethernet stuff */
+#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
+#define CONFIG_ETHADDR	00:50:C2:1E:AF:FE
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR 00:50:C2:1E:AF:FD
+
+/*-----------------------------------------------------------------------
+ * NAND-FLASH stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1         /* Max number of NAND devices */
+#define NAND_BIG_DELAY_US	25
+
+#define CONFIG_SYS_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
+#define CONFIG_SYS_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
+#define CONFIG_SYS_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
+#define CONFIG_SYS_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
+
+#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1       /* ".i" read skips bad blocks   */
+#define CONFIG_SYS_NAND_QUIET          1
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#undef	CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST PCI_HOST_HOST	/* select pci host function	*/
+#undef	CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+					/* resource configuration	*/
+
+#undef	CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
+#define CONFIG_SYS_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
+#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CONFIG_SYS_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CONFIG_SYS_PCI_PTM2LA	0xffc00000	/* point to flash		*/
+#define CONFIG_SYS_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
+#define CONFIG_SYS_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFFC0000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
+
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#if 0 /* test-only */
+#define CONFIG_SYS_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
+#define CONFIG_SYS_JFFS2_NUM_BANKS	1	    /* ! second bank contains U-Boot */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Environment Variable setup
+ */
+#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CONFIG_ENV_OFFSET		0x100	/* environment starts at the beginning of the EEPROM */
+#define CONFIG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
+				   /* total size of a CAT24WC16 is 2048 bytes */
+
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
+#define CONFIG_SYS_NVRAM_SIZE		242			/* NVRAM size		*/
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last 4 bits of the address	*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
+#define CONFIG_SYS_EBC_PB0AP		0x92015480
+/*#define CONFIG_SYS_EBC_PB0AP		  0x08055880  /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
+#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization			*/
+#define CONFIG_SYS_EBC_PB1AP		0x92015480
+#define CONFIG_SYS_EBC_PB1CR		0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 2 (8 Bit Peripheral: UART) initialization			*/
+#if 0
+#define CONFIG_SYS_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+#else
+#define CONFIG_SYS_EBC_PB2AP		0x92015480
+#define CONFIG_SYS_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+#endif
+
+#define DUART0_BA	0xF0000000	    /* DUART Base Address		*/
+#define DUART1_BA	0xF0000008	    /* DUART Base Address		*/
+#define DUART2_BA	0xF0000010	    /* DUART Base Address		*/
+#define DUART3_BA	0xF0000018	    /* DUART Base Address		*/
+#define CONFIG_SYS_NAND_BASE	0xF4000000
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ */
+#define CONFIG_SYS_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
+#define CONFIG_SYS_FPGA_MAX_SIZE	128*1024    /* 128kByte is enough for XC2S50E*/
+
+/* FPGA program pin configuration */
+#define CONFIG_SYS_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
+#define CONFIG_SYS_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
+#define CONFIG_SYS_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
+#define CONFIG_SYS_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
+#define CONFIG_SYS_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CONFIG_SYS_TEMP_STACK_OCM	  1
+
+/* On Chip Memory location */
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
+
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO setup (PPC405EP specific)
+ *
+ * GPIO0[0]	- External Bus Controller BLAST output
+ * GPIO0[1-9]	- Instruction trace outputs -> GPIO
+ * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
+ * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
+ * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
+ * GPIO0[24-27] - UART0 control signal inputs/outputs
+ * GPIO0[28-29] - UART1 data signal input/output
+ * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
+ */
+#define CONFIG_SYS_GPIO0_OSRL		0x40000550
+#define CONFIG_SYS_GPIO0_OSRH		0x00000110
+#define CONFIG_SYS_GPIO0_ISR1L		0x00000000
+#define CONFIG_SYS_GPIO0_ISR1H		0x15555445
+#define CONFIG_SYS_GPIO0_TSRL		0x00000000
+#define CONFIG_SYS_GPIO0_TSRH		0x00000000
+#define CONFIG_SYS_GPIO0_TCR		0xF7FE0014
+
+#define CONFIG_SYS_DUART_RST           (0x80000000 >> 14)
+#define CONFIG_SYS_UART2_RS232         (0x80000000 >> 5)
+#define CONFIG_SYS_UART3_RS232         (0x80000000 >> 6)
+#define CONFIG_SYS_UART4_RS232         (0x80000000 >> 7)
+#define CONFIG_SYS_UART5_RS232         (0x80000000 >> 8)
+
+/*
+ * Default speed selection (cpu_plb_opb_ebc) in mhz.
+ * This value will be set if iic boot eprom is disabled.
+ */
+#if 0
+#define PLLMR0_DEFAULT	 PLLMR0_266_133_66_33
+#define PLLMR1_DEFAULT	 PLLMR1_266_133_66_33
+#endif
+#if 0
+#define PLLMR0_DEFAULT	 PLLMR0_200_100_50_33
+#define PLLMR1_DEFAULT	 PLLMR1_200_100_50_33
+#endif
+#if 1
+#define PLLMR0_DEFAULT	 PLLMR0_133_66_66_33
+#define PLLMR1_DEFAULT	 PLLMR1_133_66_66_33
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/HWW1U1A.h b/qemu/roms/u-boot/include/configs/HWW1U1A.h
new file mode 100644
index 000000000..6a3a11cb7
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/HWW1U1A.h
@@ -0,0 +1,460 @@
+/*
+ * Copyright 2009-2010 eXMeritus, A Boeing Company
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * HardwareWall HWW-1U-1A airborne unit configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High-level system configuration options */
+#define CONFIG_BOOKE		/* Power/PowerPC Book-E			*/
+#define CONFIG_E500		/* e500 (Power ISA v2.03 with SPE)	*/
+#define CONFIG_FSL_ELBC		/* FreeScale Enhanced LocalBus Cntlr	*/
+#define CONFIG_FSL_LAW		/* FreeScale Local Access Window	*/
+#define CONFIG_P2020		/* FreeScale P2020			*/
+#define CONFIG_HWW1U1A		/* eXMeritus HardwareWall HWW-1U-1A	*/
+#define CONFIG_MP		/* Multiprocessing support		*/
+#define CONFIG_HWCONFIG		/* Use hwconfig from environment	*/
+
+#define CONFIG_L2_CACHE			/* L2 cache enabled		*/
+#define CONFIG_BTB			/* Branch predition enabled	*/
+
+#define CONFIG_PANIC_HANG		/* No board reset on panic	*/
+#define CONFIG_BOARD_EARLY_INIT_R	/* Call board_early_init_r()	*/
+#define CONFIG_CMD_REGINFO		/* Dump various CPU regs	*/
+
+/*
+ * Allow the use of 36-bit physical addresses.  Device-trees with 64-bit
+ * addresses have known compatibility issues with some existing kernels.
+ */
+#define CONFIG_ENABLE_36BIT_PHYS
+#define CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP 16 /* Number of entries in TLB1 */
+
+/* Reserve plenty of RAM for malloc (we have 2GB+) */
+#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
+
+/* How much L2 cache do we map so we can use it as RAM */
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
+
+/* This is our temporary global data area just above the stack */
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+/* The stack grows down from the global data area */
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+/* Enable IRQs and watchdog with a 1000Hz system decrementer */
+#define CONFIG_CMD_IRQ
+
+/* -------------------------------------------------------------------- */
+
+/*
+ * Clock crystal configuration:
+ *  (1) SYS: 66.666MHz +/- 50ppm (drives CPU/PCI/DDR)
+ *  (2) CCB: Multiplier from SYS_CLK
+ *  (3) RTC: 25.000MHz +/- 50ppm (sampled against CCB clock)
+ */
+#define CONFIG_SYS_CLK_FREQ 66666000/*Hz*/
+#define CONFIG_DDR_CLK_FREQ 66666000/*Hz*/
+
+
+/* -------------------------------------------------------------------- */
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000  0x7fff_ffff    2G  DDR2 ECC SDRAM
+ * 0x8000_0000  0x9fff_ffff  512M  PCI-E Bus 1
+ * 0xa000_0000  0xbfff_ffff  512M  PCI-E Bus 2 (unused)
+ * 0xc000_0000  0xdfff_ffff  512M  PCI-E Bus 3
+ * 0xe000_0000  0xe7ff_ffff  128M  Spansion FLASH
+ * 0xe800_0000  0xefff_ffff  128M  Spansion FLASH
+ * 0xffd0_0000  0xffd0_3fff   16K  L1 boot stack (TLB0)
+ * 0xffe0_0000  0xffef_ffff    1M  CCSR
+ * 0xffe0_5000  0xffe0_5fff    4K    Enhanced LocalBus Controller
+ */
+
+/* Virtual Memory Map */
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0xc0000000
+#define CONFIG_SYS_FLASH_BASE		0xe0000000
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xffc00000
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xffc10000
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc20000
+#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000
+#define CONFIG_SYS_CCSRBAR		0xffe00000 /* CCSRBAR @ runtime */
+
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000 /* 64k */
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000 /* 64k */
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000 /* 64k */
+
+/* Physical Memory Map */
+#define CONFIG_SYS_PCIE3_MEM_PHYS     0xc00000000ull
+#define CONFIG_SYS_PCIE2_MEM_PHYS     0xc20000000ull
+#define CONFIG_SYS_PCIE1_MEM_PHYS     0xc40000000ull
+#define CONFIG_SYS_FLASH_BASE_PHYS    0xfe0000000ull
+#define CONFIG_SYS_PCIE3_IO_PHYS      0xfffc00000ull
+#define CONFIG_SYS_PCIE2_IO_PHYS      0xfffc10000ull
+#define CONFIG_SYS_PCIE1_IO_PHYS      0xfffc20000ull
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfffd00000ull
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf		/* for ASM code */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW  0xffd00000	/* for ASM code */
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH       0xf		/* for ASM code */
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW        0xffe00000	/* for ASM code */
+
+
+/* -------------------------------------------------------------------- */
+
+/* U-Boot image (MONITOR_BASE == TEXT_BASE) */
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc /* Top address in flash */
+#define CONFIG_SYS_TEXT_BASE		0xeff80000 /* Start of U-Boot image */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		0x80000 /* 512kB (4 flash sectors) */
+
+/*
+ * U-Boot Environment Image:  The two sectors immediately below U-Boot
+ * form the U-Boot environment (regular and redundant).
+ */
+#define CONFIG_ENV_IS_IN_FLASH	/* The environment image is stored in FLASH */
+#define CONFIG_ENV_OVERWRITE	/* Allow "protected" variables to be erased */
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128kB (1 flash sector) */
+#define CONFIG_ENV_ADDR        (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR         - CONFIG_ENV_SECT_SIZE)
+
+/* Only use 8kB of each environment sector for data */
+#define CONFIG_ENV_SIZE		0x2000 /* 8kB */
+#define CONFIG_ENV_SIZE_REDUND	0x2000 /* 8kB */
+
+
+/* -------------------------------------------------------------------- */
+
+/* Serial Console Configuration */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+
+/* Echo back characters received during a serial download */
+#define CONFIG_LOADS_ECHO
+
+/* Allow a serial-download to temporarily change baud */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE
+
+
+/* -------------------------------------------------------------------- */
+
+/* PCI and PCI-Express Support */
+#define CONFIG_PCI		/* Enable PCI/PCIE			*/
+#define CONFIG_PCI_PNP		/* Scan PCI busses			*/
+#define CONFIG_CMD_PCI		/* Enable the "pci" command		*/
+#define CONFIG_FSL_PCI_INIT	/* Common FreeScale PCI initialization	*/
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_FSL_PCIE_RESET	/* We have PCI-E reset errata		*/
+#define CONFIG_SYS_PCI_64BIT	/* PCI resources are 64-bit		*/
+#define CONFIG_PCI_SCAN_SHOW	/* Display PCI scan during boot		*/
+
+/* Enable 2 of the 3 PCI-E controllers */
+#define CONFIG_PCIE3
+#undef  CONFIG_PCIE2
+#define CONFIG_PCIE1
+
+/* Display human-readable names when initializing */
+#define CONFIG_SYS_PCIE3_NAME "Intel 82571EB"
+#define CONFIG_SYS_PCIE2_NAME "Unused"
+#define CONFIG_SYS_PCIE1_NAME "Silicon Image SIL3531"
+
+/*
+ * PCI bus addresses
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+#define CONFIG_SYS_PCIE3_IO_BUS  0x00000000
+#define CONFIG_SYS_PCIE2_IO_BUS  0x00000000
+#define CONFIG_SYS_PCIE1_IO_BUS  0x00000000
+#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
+
+
+/* -------------------------------------------------------------------- */
+
+/* Generic FreeScale hardware I2C support */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x29} }
+#define CONFIG_CMD_I2C
+
+/* DDR2 SO-RDIMM SPD EEPROM is at I2C0-0x51 */
+#define CONFIG_SYS_SPD_BUS_NUM 0
+#define SPD_EEPROM_ADDRESS 0x51
+
+/* DS1339 RTC is at I2C0-0x68 (I know it says "DS1337", it's a DS1339) */
+#define CONFIG_CMD_DATE
+#define CONFIG_RTC_DS1337
+#define CONFIG_SYS_RTC_BUS_NUM 0
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68
+/* Turn off RTC square-wave output to save battery */
+#define CONFIG_SYS_RTC_DS1337_NOOSC
+
+/*
+ * AT24C128N EEPROM at I2C0-0x53.
+ *
+ * That Atmel EEPROM has 128kbit of memory (16kByte) divided into 256 pages
+ * of 64 bytes per page.  The chip uses 2-byte addresses and has a max write
+ * cycle time of 20ms according to the datasheet.
+ *
+ * NOTE: Our environment is stored on regular direct-attached FLASH, this
+ * chip is only used as a write-protected backup for certain key settings
+ * such as the serial# and macaddr values.  (EG: "env import")
+ */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 1 << 6 == 64 byte pages */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 21
+
+/*
+ * PCA9554 is at I2C1-0x3f (I know it says "PCA953X", it's a PCA9554).  You
+ * must first select the I2C1 bus with "i2c dev 1" or the "pca953x" command
+ * will not be able to access the chip.
+ */
+#define CONFIG_PCA953X
+#define CONFIG_CMD_PCA953X
+#define CONFIG_CMD_PCA953X_INFO
+#define CONFIG_SYS_I2C_PCA953X_ADDR 0x3f
+
+
+/* -------------------------------------------------------------------- */
+
+/* FreeScale DDR2/3 SDRAM Controller */
+#define CONFIG_SYS_FSL_DDR2		/* Our SDRAM slot is DDR2		*/
+#define CONFIG_DDR_ECC		/* Enable ECC by default		*/
+#define CONFIG_DDR_SPD		/* Detect DDR config from SPD EEPROM	*/
+#define CONFIG_SPD_EEPROM	/* ...why 2 config variables for this?	*/
+#define CONFIG_VERY_BIG_RAM	/* Allow 2GB+ of RAM			*/
+#define CONFIG_CMD_SDRAM
+
+/* Standard P2020 DDR controller parameters */
+#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL 2
+
+/* Make sure to tell the DDR controller to preinitialze all of RAM */
+#define CONFIG_MEM_INIT_VALUE 0xDEADBEEF
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+
+
+/* -------------------------------------------------------------------- */
+
+/* FLASH Memory Configuration (2x 128MB SPANSION FLASH) */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
+
+/* Flash banks (2x 128MB) */
+#define FLASH0_PHYS (CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000ull)
+#define FLASH1_PHYS (CONFIG_SYS_FLASH_BASE_PHYS + 0x0000000ull)
+#define CONFIG_SYS_MAX_FLASH_BANKS 2
+#define CONFIG_SYS_MAX_FLASH_SECT 1024
+#define CONFIG_SYS_FLASH_BANKS_LIST { FLASH0_PHYS, FLASH1_PHYS }
+
+/*
+ * Flash access modes and timings (values are the defaults after a RESET).
+ *
+ * NOTE: These could probably be optimized but are more than sufficient for
+ * this particular system for the moment.
+ */
+#define FLASH_BRx (BR_PS_16 | BR_MS_GPCM | BR_V)
+#define FLASH_ORx (OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS \
+		| OR_GPCM_SCY_15 | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
+
+/* Configure both flash banks */
+#define CONFIG_SYS_BR0_PRELIM (FLASH_BRx | BR_PHYS_ADDR(FLASH0_PHYS))
+#define CONFIG_SYS_BR1_PRELIM (FLASH_BRx | BR_PHYS_ADDR(FLASH1_PHYS))
+#define CONFIG_SYS_OR0_PRELIM (FLASH_ORx | OR_AM_128MB)
+#define CONFIG_SYS_OR1_PRELIM (FLASH_ORx | OR_AM_128MB)
+
+/* Flash timeouts (in ms) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000UL /* Erase (60s)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT   500UL /* Write (0.5s)	*/
+
+/* Quiet flash testing */
+#define CONFIG_SYS_FLASH_QUIET_TEST
+
+/* Make program/erase count down from 45/5 (9....8....7....) */
+#define CONFIG_FLASH_SHOW_PROGRESS 45
+
+
+/* -------------------------------------------------------------------- */
+
+/* Ethernet Device Support */
+#define CONFIG_MII			/* Enable MII PHY code		*/
+#define CONFIG_MII_DEFAULT_TSEC		/* ??? Copied from P2020DS	*/
+#define CONFIG_PHY_GIGE			/* Support Gigabit PHYs		*/
+#define CONFIG_ETHPRIME "e1000#0"	/* Default to external ports	*/
+
+/* Turn on various helpful networking commands */
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+
+/* On-chip FreeScale P2020 "tsec" Ethernet (oneway fibers and peer) */
+#define CONFIG_TSEC_ENET
+#define CONFIG_TSEC1
+#define CONFIG_TSEC2
+#define CONFIG_TSEC3
+#define CONFIG_TSEC1_NAME "owt0"
+#define CONFIG_TSEC2_NAME "owt1"
+#define CONFIG_TSEC3_NAME "peer"
+#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC1_PHYIDX 0
+#define TSEC2_PHYIDX 0
+#define TSEC3_PHYIDX 0
+#define TSEC1_PHY_ADDR      2
+#define TSEC2_PHY_ADDR      3
+#define TSEC3_PHY_ADDR      4
+#define TSEC3_PHY_ADDR_CPUA 4
+#define TSEC3_PHY_ADDR_CPUB 5
+
+/* PCI-E dual-port E1000 (external ethernet ports) */
+#define CONFIG_E1000
+#define CONFIG_E1000_SPI
+#define CONFIG_E1000_SPI_GENERIC
+#define CONFIG_CMD_E1000
+
+/* We need the SPI infrastructure to poke the E1000's EEPROM */
+#define CONFIG_SPI
+#define CONFIG_SPI_X
+#define CONFIG_CMD_SPI
+#define MAX_SPI_BYTES 32
+
+
+/* -------------------------------------------------------------------- */
+
+/* USB Thumbdrive Device Support */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_USB_STORAGE
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_CMD_USB
+
+/* Partition and Filesystem support */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+#define CONFIG_ISO_PARTITION
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+
+
+/* -------------------------------------------------------------------- */
+
+/* Command line configuration. */
+#define CONFIG_CMDLINE_EDITING		/* Enable command editing	*/
+#define CONFIG_COMMAND_HISTORY		/* Enable command history	*/
+#define CONFIG_AUTO_COMPLETE		/* Enable command completion	*/
+#define CONFIG_SYS_LONGHELP		/* Enable detailed command help	*/
+#define CONFIG_SYS_MAXARGS 128		/* Up to 128 command-line args	*/
+#define CONFIG_SYS_PBSIZE 8192		/* Allow up to 8k printed lines	*/
+#define CONFIG_SYS_CBSIZE 4096		/* Allow up to 4k command lines	*/
+#define CONFIG_SYS_BARGSIZE 4096	/* Allow up to 4k boot args	*/
+#define CONFIG_SYS_HUSH_PARSER		/* Enable a fancier shell	*/
+
+/* A little extra magic here for the prompt */
+#define CONFIG_SYS_PROMPT hww1u1a_get_ps1()
+#ifndef __ASSEMBLY__
+const char *hww1u1a_get_ps1(void);
+#endif
+
+/* Include a bunch of default commands we probably want */
+#include <config_cmd_default.h>
+
+/* Other helpful shell-like commands */
+#define CONFIG_MD5
+#define CONFIG_SHA1
+#define CONFIG_CMD_MD5SUM
+#define CONFIG_CMD_SHA1SUM
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_SETEXPR
+
+
+/* -------------------------------------------------------------------- */
+
+/* Image manipulation and booting */
+
+/* We use the OpenFirmware-esque "Flattened Device Tree" */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_CMD_ELF
+#define CONFIG_SYS_BOOTMAPSZ (64 << 20)	/* Maximum kernel memory map	*/
+#define CONFIG_SYS_BOOTM_LEN (64 << 20)	/* Maximum kernel size of 64MB	*/
+
+/* This is the default address for commands with an optional address arg */
+#define CONFIG_LOADADDR		  100000
+#define CONFIG_SYS_LOAD_ADDR	0x100000
+
+/* Test memory starting from the default load address to just below 2GB */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_LOAD_ADDR
+#define CONFIG_SYS_MEMTEST_END		0x7f000000
+
+#define CONFIG_BOOTDELAY 20
+#define CONFIG_BOOTCOMMAND "echo Not yet flashed"
+#define CONFIG_BOOTARGS ""
+#define CONFIG_BOOTARGS_DYNAMIC "console=ttyS0,${baudrate}n1"
+
+/* Extra environment parameters */
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"ethprime=e1000#0\0"						\
+	"ethrotate=no\0"						\
+	"setbootargs=setenv bootargs "					\
+			"\"${bootargs} "CONFIG_BOOTARGS_DYNAMIC"\"\0"	\
+	"perf_mode=performance\0"					\
+	"hwconfig="	"fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1;"	\
+			"usb1:dr_mode=host,phy_type=ulpi\0"		\
+	"flkernel=0xe8000000\0"						\
+	"flinitramfs=0xe8800000\0"					\
+	"fldevicetree=0xeff20000\0"					\
+	"flbootm=bootm ${flkernel} ${flinitramfs} ${fldevicetree}\0"	\
+	"flboot=run preboot; run flbootm\0"				\
+	"restore_eeprom=i2c dev 0 && "					\
+			"eeprom read $loadaddr 0x0000 0x2000 && "	\
+			"env import -c $loadaddr 0x2000\0"
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/ICU862.h b/qemu/roms/u-boot/include/configs/ICU862.h
new file mode 100644
index 000000000..16af4bbca
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/ICU862.h
@@ -0,0 +1,443 @@
+/*
+ * (C) Copyright 2001-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <mpc8xx_irq.h>
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MPC860		1
+#define CONFIG_MPC860T		1
+#define CONFIG_ICU862		1
+#define CONFIG_MPC862		1
+
+#define	CONFIG_SYS_TEXT_BASE	0x40F00000
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+
+#ifdef CONFIG_100MHz
+#define MPC8XX_FACT		24		/* Multiply by 24	*/
+#define MPC8XX_XIN		4165000		/* 4.165 MHz in		*/
+#define CONFIG_8xx_GCLK_FREQ	(MPC8XX_FACT * MPC8XX_XIN)
+				    /* define if cant' use get_gclk_freq */
+#else
+#if 1				/* for 50MHz version of processor	*/
+#define MPC8XX_FACT		12		/* Multiply by 12	*/
+#define MPC8XX_XIN		4000000		/* 4 MHz in		*/
+#define CONFIG_8xx_GCLK_FREQ	48000000 /* define if cant use get_gclk_freq */
+#else				/* for 80MHz version of processor	*/
+#define MPC8XX_FACT		20		/* Multiply by 20	*/
+#define MPC8XX_XIN		4000000		/* 4 MHz in		*/
+#define CONFIG_8xx_GCLK_FREQ    80000000 /* define if cant use get_gclk_freq */
+#endif
+#endif
+
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND							\
+	"bootp;"								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"	\
+	"bootm"
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+#undef	CONFIG_SCC1_ENET		/* disable SCC1 ethernet */
+#define	CONFIG_FEC_ENET		1	/* use FEC ethernet  */
+#define	CONFIG_MII		1
+#if 1
+#define CONFIG_SYS_DISCOVER_PHY	1
+#else
+#undef	CONFIG_SYS_DISCOVER_PHY
+#endif
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+/* enable I2C and select the hardware/software driver */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED	50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PB_SCL		0x00000020	/* PB 26 */
+#define PB_SDA		0x00000010	/* PB 27 */
+
+#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
+#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
+#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
+#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
+#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
+#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
+
+#define CONFIG_SYS_EEPROM_X40430		/* Use a Xicor X40430 EEPROM	*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS  4	/* 16 bytes page write mode	*/
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address */
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0100000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0400000	/* 1 ... 4 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x00100000
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xF0000000
+#define CONFIG_SYS_IMMR_SIZE		((uint)(64 * 1024))
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#define CONFIG_SYS_FLASH_SIZE		((uint)(16 * 1024 * 1024))	/* max 16Mbyte */
+
+#define CONFIG_SYS_RESET_ADDRESS	0xFFF00100
+
+#if 0
+#if defined(DEBUG)
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#else
+#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#endif
+#else
+#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#endif
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Timeout for Flash Write (in ms)	*/
+
+
+#define	CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_OFFSET		0x00F40000
+
+#define CONFIG_ENV_SECT_SIZE	0x40000	/* Total Size of Environment sector	*/
+#define	CONFIG_ENV_SIZE		0x4000	/* Used Size of Environment Sector	*/
+#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control					11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration					11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control					11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register	15-30
+ *-----------------------------------------------------------------------
+ * set the PLL, the low-power modes and the reset control (15-29)
+ */
+#define CONFIG_SYS_PLPRCR	(((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) |	\
+				PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#ifdef CONFIG_100MHz	/* for 100 MHz, external bus is half CPU clock */
+#define SCCR_MASK	0
+#define CONFIG_SYS_SCCR	(SCCR_TBS	| SCCR_COM00	| SCCR_DFSYNC00	| \
+			 SCCR_DFBRG00	| SCCR_DFNL000	| SCCR_DFNH000	| \
+			 SCCR_DFLCD000	|SCCR_DFALCD00	| SCCR_EBDF01)
+#else			/* up to 50 MHz we use a 1:1 clock */
+#define SCCR_MASK	SCCR_EBDF11
+#define CONFIG_SYS_SCCR	(SCCR_TBS	| SCCR_COM00	| SCCR_DFSYNC00	| \
+			 SCCR_DFBRG00	| SCCR_DFNL000	| SCCR_DFNH000	| \
+			 SCCR_DFLCD000	|SCCR_DFALCD00	)
+#endif	/* CONFIG_100MHz */
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration Register		19-4
+ *-----------------------------------------------------------------------
+ */
+/* +0x09C4 => DRQP = 10 (IDMA requests have lowest priority) */
+#define CONFIG_SYS_RCCR 0x0020
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * PCMCIA Power Switch
+ *
+ * The ICU862 uses a TPS2205 PC-Card Power-Interface Switch to
+ * control the voltages on the PCMCIA slot which is connected to Port B
+ *-----------------------------------------------------------------------
+ */
+			/* Output pins */
+#define TPS2205_VCC5	0x00008000	/* PB.16:  5V Voltage Control	*/
+#define TPS2205_VCC3	0x00004000	/* PB.17:  3V Voltage Control	*/
+#define TPS2205_VPP_PGM	0x00002000	/* PB.18: PGM Voltage Control	*/
+#define TPS2205_VPP_VCC	0x00001000	/* PB.19: VPP Voltage Control	*/
+#define TPS2205_SHDN	0x00000200	/* PB.22: Shutdown		*/
+#define TPS2205_OUTPUTS ( TPS2205_VCC5    | TPS2205_VCC3    | \
+			  TPS2205_VPP_PGM | TPS2205_VPP_VCC | \
+			  TPS2205_SHDN)
+
+			/* Input pins */
+#define TPS2205_OC	0x00000100	/* PB.23: Over-Current		*/
+#define TPS2205_INPUTS	( TPS2205_OC )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_IDE_PREINIT	1	/* Use preinit IDE hook */
+#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
+
+
+ /*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_DER		0
+
+/* Because of the way the 860 starts up and assigns CS0 the
+* entire address space, we have to set the memory controller
+* differently.  Normally, you write the option register
+* first, and then enable the chip select by writing the
+* base register.  For CS0, you must write the base register
+* first, followed by the option register.
+*/
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0 and OR0 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x0		/* FLASH bank #1	*/
+
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0	*/
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
+
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+
+#define CONFIG_SYS_OR0_PRELIM	0xFF000954		/* Real values for the board */
+#define CONFIG_SYS_BR0_PRELIM	0x40000001		/* Real values for the board */
+
+/*
+ * BR1 and OR1 (SDRAM)
+ */
+#define SDRAM_BASE1_PRELIM	0x00000000	/* SDRAM bank		*/
+#define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000800	/* BIH is not set	*/
+
+#define CONFIG_SYS_OR1_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM)
+#define CONFIG_SYS_BR1_PRELIM	((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V)
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CONFIG_SYS_MAMR_PTA		97	/* start with divider for 100 MHz	*/
+
+/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+#define CONFIG_SYS_MAMR		0x13a01114
+
+#ifdef CONFIG_MPC860T
+
+/* Interrupt level assignments.
+*/
+#define FEC_INTERRUPT	SIU_LEVEL1	/* FEC interrupt */
+
+#endif /* CONFIG_MPC860T */
+
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/IDS8247.h b/qemu/roms/u-boot/include/configs/IDS8247.h
new file mode 100644
index 000000000..8ccb0ff9d
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/IDS8247.h
@@ -0,0 +1,462 @@
+/*
+ * (C) Copyright 2005
+ * Heiko Schocher, DENX Software Engineering, <hs@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC8272_FAMILY	1
+#define CONFIG_IDS8247		1
+#define CPU_ID_STR		"MPC8247"
+#define CONFIG_CPM2		1	/* Has a CPM2 */
+
+#define	CONFIG_SYS_TEXT_BASE	0xfff00000
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define	CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw "			\
+	"console=ttyS0,115200\0"					\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_82xx\0"					\
+	"bootfile=/tftpboot/IDS8247/uImage\0"				\
+	"kernel_addr=ff800000\0"					\
+	"ramdisk_addr=ffa00000\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_MISC_INIT_R	1
+
+/* enable I2C and select the hardware/software driver */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED	400000
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0x7F
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+
+#define I2C_PORT	0		/* Port A=0, B=1, C=2, D=3 */
+#define I2C_ACTIVE	(iop->pdir |=  0x00000080)
+#define I2C_TRISTATE	(iop->pdir &= ~0x00000080)
+#define I2C_READ	((iop->pdat & 0x00000080) != 0)
+#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00000080; \
+			else    iop->pdat &= ~0x00000080
+#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00000100; \
+			else    iop->pdat &= ~0x00000100
+#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
+
+#if 0
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+
+#define CONFIG_I2C_X
+#endif
+
+/*
+ * select serial console configuration
+ * use the extern UART for the console
+ */
+#define	CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		115200
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+
+#define CONFIG_SYS_NS16550_REG_SIZE    1
+
+#define CONFIG_SYS_NS16550_CLK         14745600
+
+#define	CONFIG_SYS_UART_BASE	0xE0000000
+#define CONFIG_SYS_UART_SIZE	0x10000
+
+#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_UART_BASE + 0x8000)
+
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+#define OF_TBCLK	(bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH	"/soc@f0000000/serial8250@e0008000"
+
+
+/*
+ * select ethernet configuration
+ *
+ * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
+ * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
+ * for FCC)
+ *
+ * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
+ */
+#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC       */
+#define	CONFIG_ETHER_ON_FCC		/* define if ether on FCC       */
+#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
+#define	CONFIG_ETHER_INDEX	1	/* which SCC/FCC channel for ethernet */
+#define CONFIG_ETHER_ON_FCC1
+#define FCC_ENET
+
+/*
+ * - Rx-CLK is CLK10
+ * - Tx-CLK is CLK9
+ * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
+ * - Enable Full Duplex in FSMR
+ */
+# define CONFIG_SYS_CMXFCR_MASK1	(CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE1	(CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK9)
+# define CONFIG_SYS_CPMFCR_RAMTYPE	0
+# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+
+
+/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
+#define CONFIG_8260_CLKIN	66666666	/* in Hz */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+#define CONFIG_RTC_PCF8563
+#define CONFIG_SYS_I2C_RTC_ADDR		0x51
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_SNTP
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address	*/
+
+#define	CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC	/* "bad" address		*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
+
+#define CONFIG_SYS_FLASH_CFI				/* The flash is CFI compatible  */
+#define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver        */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ 0xFF800000 }
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks	      */
+/* What should the base address of the main FLASH be and how big is
+ * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/ids8247/config.mk
+ * The main FLASH is whichever is connected to *CS0.
+ */
+#define CONFIG_SYS_FLASH0_BASE 0xFFF00000
+#define CONFIG_SYS_FLASH0_SIZE 8
+
+/* Flash bank size (for preliminary settings)
+ */
+#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+
+/* Environment in flash */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE+0x60000)
+#define CONFIG_ENV_SIZE		0x20000
+#define CONFIG_ENV_SECT_SIZE	0x20000
+
+/*-----------------------------------------------------------------------
+ * NAND-FLASH stuff
+ *-----------------------------------------------------------------------
+ */
+#if defined(CONFIG_CMD_NAND)
+
+#define CONFIG_SYS_NAND0_BASE 0xE1000000
+#define CONFIG_SYS_MAX_NAND_DEVICE     1       /* Max number of NAND devices           */
+
+#endif /* CONFIG_CMD_NAND */
+
+/*-----------------------------------------------------------------------
+ * Hard Reset Configuration Words
+ *
+ * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
+ * defines for the various registers affected by the HRCW e.g. changing
+ * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
+ */
+#define CONFIG_SYS_HRCW_MASTER	(HRCW_BPS01 | HRCW_BMS | HRCW_ISB100 | HRCW_APPC10 | HRCW_MODCK_H1000)
+
+/* no slaves so just fill with zeros */
+#define CONFIG_SYS_HRCW_SLAVE1		0
+#define CONFIG_SYS_HRCW_SLAVE2		0
+#define CONFIG_SYS_HRCW_SLAVE3		0
+#define CONFIG_SYS_HRCW_SLAVE4		0
+#define CONFIG_SYS_HRCW_SLAVE5		0
+#define CONFIG_SYS_HRCW_SLAVE6		0
+#define CONFIG_SYS_HRCW_SLAVE7		0
+
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xF0000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000  /* Size of used area in DPRAM    */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ *
+ * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_FLASH0_BASE
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
+#if defined(CONFIG_CMD_KGDB)
+# define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * HIDx - Hardware Implementation-dependent Registers                    2-11
+ *-----------------------------------------------------------------------
+ * HID0 also contains cache control - initially enable both caches and
+ * invalidate contents, then the final state leaves only the instruction
+ * cache enabled. Note that Power-On and Hard reset invalidate the caches,
+ * but Soft reset does not.
+ *
+ * HID1 has only read-only information - nothing to set.
+ */
+
+#define CONFIG_SYS_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI)
+#define CONFIG_SYS_HID0_FINAL  0
+#define CONFIG_SYS_HID2        0
+
+/*-----------------------------------------------------------------------
+ * RMR - Reset Mode Register                                     5-5
+ *-----------------------------------------------------------------------
+ * turn on Checkstop Reset Enable
+ */
+#define CONFIG_SYS_RMR         0
+
+/*-----------------------------------------------------------------------
+ * BCR - Bus Configuration                                       4-25
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_BCR		0
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration                             4-31
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_SIUMCR      (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_BCTLC01)
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control                             4-35
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
+#else
+#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+			 SYPCR_SWRI|SYPCR_SWP)
+#endif /* CONFIG_WATCHDOG */
+
+/*-----------------------------------------------------------------------
+ * TMCNTSC - Time Counter Status and Control                     4-40
+ *-----------------------------------------------------------------------
+ * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
+ * and enable Time Counter
+ */
+#define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control                 4-42
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
+ * Periodic timer
+ */
+#define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control                                   9-8
+ *-----------------------------------------------------------------------
+ * Ensure DFBRG is Divide by 16
+ */
+#define CONFIG_SYS_SCCR        (0x00000028 | SCCR_DFBRG01)
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration                         13-7
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RCCR        0
+
+/*
+ * Init Memory Controller:
+ *
+ * Bank Bus     Machine PortSz  Device
+ * ---- ---     ------- ------  ------
+ *  0   60x     GPCM    16 bit  FLASH
+ *  1   60x     GPCM     8 bit  NAND
+ *  2   60x     SDRAM   32 bit  SDRAM
+ *  3   60x     GPCM     8 bit  UART
+ *
+ */
+
+#define SDRAM_MAX_SIZE	0x08000000	/* max. 128 MB		*/
+
+/* Minimum mask to separate preliminary
+ * address ranges for CS[0:2]
+ */
+#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT	(32<<20)	/* less than 32 MB */
+
+#define CONFIG_SYS_MPTPR       0x6600
+
+/*-----------------------------------------------------------------------------
+ * Address for Mode Register Set (MRS) command
+ *-----------------------------------------------------------------------------
+ */
+#define CONFIG_SYS_MRS_OFFS	0x00000110
+
+
+/* Bank 0 - FLASH
+ */
+#define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)  |\
+			 BRx_PS_8                       |\
+			 BRx_MS_GPCM_P                  |\
+			 BRx_V)
+
+#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE)      |\
+			 ORxG_SCY_6_CLK                 )
+
+#if defined(CONFIG_CMD_NAND)
+/* Bank 1 - NAND Flash
+*/
+#define	CONFIG_SYS_NAND_BASE		CONFIG_SYS_NAND0_BASE
+#define	CONFIG_SYS_NAND_SIZE		0x8000
+
+#define CONFIG_SYS_OR_TIMING_NAND	0x000036
+
+#define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_NAND_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V  )
+#define CONFIG_SYS_OR1_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_NAND_SIZE) | CONFIG_SYS_OR_TIMING_NAND )
+#endif
+
+/* Bank 2 - 60x bus SDRAM
+ */
+#define CONFIG_SYS_PSRT        0x20
+#define CONFIG_SYS_LSRT        0x20
+
+#define CONFIG_SYS_BR2_PRELIM  ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)  |\
+			 BRx_PS_32                      |\
+			 BRx_MS_SDRAM_P                 |\
+			 BRx_V)
+
+#define CONFIG_SYS_OR2_PRELIM	CONFIG_SYS_OR2
+
+
+/* SDRAM initialization values
+*/
+#define CONFIG_SYS_OR2    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+			 ORxS_BPD_4                     |\
+			 ORxS_ROWST_PBI0_A9		|\
+			 ORxS_NUMR_12)
+
+#define CONFIG_SYS_PSDMR  (PSDMR_SDAM_A14_IS_A5 |\
+			 PSDMR_BSMA_A15_A17           |\
+			 PSDMR_SDA10_PBI0_A10		|\
+			 PSDMR_RFRC_5_CLK               |\
+			 PSDMR_PRETOACT_2W              |\
+			 PSDMR_ACTTORW_2W               |\
+			 PSDMR_BL                       |\
+			 PSDMR_LDOTOPRE_2C              |\
+			 PSDMR_WRC_3C                   |\
+			 PSDMR_CL_3)
+
+/* Bank 3 - UART
+*/
+
+#define CONFIG_SYS_BR3_PRELIM  ((CONFIG_SYS_UART_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V  )
+#define CONFIG_SYS_OR3_PRELIM  (((-CONFIG_SYS_UART_SIZE) & ORxG_AM_MSK) | ORxG_CSNT | ORxG_SCY_1_CLK | ORxG_TRLX )
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/IP860.h b/qemu/roms/u-boot/include/configs/IP860.h
new file mode 100644
index 000000000..97eda5844
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/IP860.h
@@ -0,0 +1,438 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC860		1	/* This is a MPC860 CPU		*/
+#define CONFIG_IP860		1	/* ...on a IP860 board		*/
+
+#define	CONFIG_SYS_TEXT_BASE	0x10000000
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
+#define CONFIG_RESET_PHY_R	1	/* Call reset_phy()		*/
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" \
+"\0load=tftp \"/tftpboot/u-boot.bin\"\0update=protect off 1:0;era 1:0;cp.b 100000 10000000 ${filesize}\0"
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND							\
+	"bootp; "								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
+	"bootm"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+
+/* enable I2C and select the hardware/software driver */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED	50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PB_SCL		0x00000020	/* PB 26 */
+#define PB_SDA		0x00000010	/* PB 27 */
+
+#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
+#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
+#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
+#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
+#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
+#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
+
+# define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM X24C16		*/
+# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"    */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* takes up to 10 msec */
+
+#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x00F00000	/* 1 ... 15MB in DRAM	*/
+
+#define	CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address	*/
+
+#define	CONFIG_SYS_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xF1000000	/* Non-standard value!!	*/
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x10000000
+#ifdef	DEBUG
+#define	CONFIG_SYS_MONITOR_LEN		(512 << 10)	/* Reserve 512 kB for Monitor	*/
+#else
+#if 0 /* need more space for I2C tests */
+#define	CONFIG_SYS_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
+#else
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)
+#endif
+#endif
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	124	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#undef	CONFIG_ENV_IS_IN_FLASH
+#undef	CONFIG_ENV_IS_IN_NVRAM
+#undef  CONFIG_ENV_IS_IN_NVRAM
+#undef	DEBUG_I2C
+#define	CONFIG_ENV_IS_IN_EEPROM
+
+#ifdef	CONFIG_ENV_IS_IN_NVRAM
+#define CONFIG_ENV_ADDR		0x20000000	/* use SRAM	*/
+#define CONFIG_ENV_SIZE		(16<<10)	/* use 16 kB	*/
+#endif	/* CONFIG_ENV_IS_IN_NVRAM */
+
+#ifdef	CONFIG_ENV_IS_IN_EEPROM
+#define CONFIG_ENV_OFFSET		 512	/* Leave 512 bytes free for other data	*/
+#define CONFIG_ENV_SIZE		1536	/* Use remaining space			*/
+#endif	/* CONFIG_ENV_IS_IN_EEPROM */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+#define CONFIG_SYS_DELAYED_ICACHE	1	/* enable ICache not before
+						 * running in RAM.
+						 */
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ * +0x0004
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * +0x0000 => 0x80600800
+ */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_EARB   | SIUMCR_EARP0 | \
+			 SIUMCR_DBGC11 | SIUMCR_MLRC10)
+
+/*-----------------------------------------------------------------------
+ * Clock Setting - get clock frequency from Board Revision Register
+ *-----------------------------------------------------------------------
+ */
+#ifndef __ASSEMBLY__
+extern  unsigned long           ip860_get_clk_freq (void);
+#endif
+#define	CONFIG_8xx_GCLK_FREQ	ip860_get_clk_freq()
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ * +0x0200 => 0x00C2
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ * +0x0240 => 0x0082
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit, set PLL multiplication factor !
+ */
+/* +0x0286 => was: 0x0000D000 */
+#define CONFIG_SYS_PLPRCR							\
+		(	PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST |	\
+			/*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |		\
+			PLPRCR_CSR   | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/	\
+		)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CONFIG_SYS_SCCR	(SCCR_COM00	|   SCCR_TBS	  |	\
+			 SCCR_RTDIV	|   SCCR_RTSEL	  |	\
+			 /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/	\
+			 SCCR_EBDF00	|   SCCR_DFSYNC00 |	\
+			 SCCR_DFBRG00	|   SCCR_DFNL000  |	\
+			 SCCR_DFNH000)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+/* +0x0220 => 0x00C3 */
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration Register		19-4
+ *-----------------------------------------------------------------------
+ */
+/* +0x09C4 => TIMEP=1 */
+#define CONFIG_SYS_RCCR 0x0100
+
+/*-----------------------------------------------------------------------
+ * RMDS - RISC Microcode Development Support Control Register
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RMDS 0
+
+/*-----------------------------------------------------------------------
+ * DER - Debug Event Register
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_DER	0
+
+/*
+ * Init Memory Controller:
+ */
+
+/*
+ * MAMR settings for SDRAM	- 16-14
+ * => 0xC3804114
+ */
+
+/* periodic timer for refresh */
+#define CONFIG_SYS_MAMR_PTA	0xC3
+
+#define CONFIG_SYS_MAMR	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/*
+ * BR1 and OR1 (FLASH)
+ */
+#define FLASH_BASE		0x10000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+/* allow for max 8 MB of Flash */
+#define CONFIG_SYS_REMAP_OR_AM		0xFF800000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xFF800000	/* OR addr mask */
+
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_6_CLK)
+
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+/* 16 bit, bank valid */
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE & BR_BA_MSK) | BR_PS_32 | BR_V )
+
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+#define CONFIG_SYS_BR1_PRELIM	CONFIG_SYS_BR0_PRELIM
+
+/*
+ * BR2/OR2 - SDRAM
+ */
+#define SDRAM_BASE		0x00000000	/* SDRAM bank */
+#define SDRAM_PRELIM_OR_AM	0xF8000000	/* map max. 128 MB */
+#define SDRAM_TIMING		0x00000A00	/* SDRAM-Timing */
+
+#define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB SDRAM */
+
+#define CONFIG_SYS_OR2		(SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
+#define CONFIG_SYS_BR2		((SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+/*
+ * BR3/OR3 - SRAM (16 bit)
+ */
+#define	SRAM_BASE	0x20000000
+#define CONFIG_SYS_OR3		0xFFF00130		/* BI/SCY = 5/TRLX (internal) */
+#define CONFIG_SYS_BR3		((SRAM_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
+#define SRAM_SIZE	(1 + (~(CONFIG_SYS_OR3 & BR_BA_MSK)))
+#define CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR3			/* Make sure to map early */
+#define CONFIG_SYS_BR3_PRELIM	CONFIG_SYS_BR3			/* in case it's used for ENV */
+#define	CONFIG_SYS_SRAM_BASE	SRAM_BASE
+#define	CONFIG_SYS_SRAM_SIZE	SRAM_SIZE
+
+/*
+ * BR4/OR4 - Board Control & Status (8 bit)
+ */
+#define	BCSR_BASE	0xFC000000
+#define CONFIG_SYS_OR4		0xFFFF0120		/* BI (internal) */
+#define CONFIG_SYS_BR4		((BCSR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
+
+/*
+ * BR5/OR5 - IP Slot A/B (16 bit)
+ */
+#define	IP_SLOT_BASE	0x40000000
+#define CONFIG_SYS_OR5		0xFE00010C		/* SETA/TRLX/BI/ SCY=0 (external) */
+#define CONFIG_SYS_BR5		((IP_SLOT_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
+
+/*
+ * BR6/OR6 - VME STD  (16 bit)
+ */
+#define	VME_STD_BASE	0xFE000000
+#define CONFIG_SYS_OR6		0xFF00010C		/* SETA/TRLX/BI/SCY=0  (external) */
+#define CONFIG_SYS_BR6		((VME_STD_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
+
+/*
+ * BR7/OR7 - SHORT I/O + RTC + IACK  (16 bit)
+ */
+#define VME_SHORT_BASE	0xFF000000
+#define CONFIG_SYS_OR7		0xFF00010C		/* SETA/TRLX/BI/ SCY=0 (external) */
+#define CONFIG_SYS_BR7		((VME_SHORT_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
+
+/*-----------------------------------------------------------------------
+ * Board Control and Status Region:
+ *-----------------------------------------------------------------------
+ */
+#ifndef __ASSEMBLY__
+typedef	struct ip860_bcsr_s {
+	unsigned char	shmem_addr;	/* +00 shared memory address register	*/
+	unsigned char	reserved0;
+	unsigned char	mbox_addr;	/* +02 mailbox address register		*/
+	unsigned char	reserved1;
+	unsigned char	vme_int_mask;	/* +04 VME Bus interrupt mask register	*/
+	unsigned char	reserved2;
+	unsigned char	vme_int_pend;	/* +06 VME interrupt pending register	*/
+	unsigned char	reserved3;
+	unsigned char	bd_int_mask;	/* +08 board interrupt mask register	*/
+	unsigned char	reserved4;
+	unsigned char	bd_int_pend;	/* +0A board interrupt pending register	*/
+	unsigned char	reserved5;
+	unsigned char	bd_ctrl;	/* +0C board control register		*/
+	unsigned char	reserved6;
+	unsigned char	bd_status;	/* +0E board status  register		*/
+	unsigned char	reserved7;
+	unsigned char	vme_irq;	/* +10 VME interrupt request register	*/
+	unsigned char	reserved8;
+	unsigned char	vme_ivec;	/* +12 VME interrupt vector register	*/
+	unsigned char	reserved9;
+	unsigned char	cli_mbox;	/* +14 clear mailbox irq		*/
+	unsigned char	reservedA;
+	unsigned char	rtc;		/* +16 RTC control register		*/
+	unsigned char	reservedB;
+	unsigned char	mbox_data;	/* +18 mailbox read/write register	*/
+	unsigned char	reservedC;
+	unsigned char	wd_trigger;	/* +1A Watchdog trigger register	*/
+	unsigned char	reservedD;
+	unsigned char	rmw_req;	/* +1C RMW request register		*/
+	unsigned char	reservedE;
+	unsigned char	bd_rev;		/* +1E Board Revision register		*/
+} ip860_bcsr_t;
+#endif	/* __ASSEMBLY__ */
+
+/*-----------------------------------------------------------------------
+ * Board Control Register: bd_ctrl (Offset 0x0C)
+ *-----------------------------------------------------------------------
+ */
+#define BD_CTRL_IPLSE	0x80	/* IP Slot Long Select Enable		*/
+#define BD_CTRL_WDOGE	0x40	/* Watchdog Enable			*/
+#define BD_CTRL_FLWE	0x20	/* Flash Write Enable			*/
+#define BD_CTRL_RWDN	0x10	/* VMEBus Requester Release When Done Enable */
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/IPHASE4539.h b/qemu/roms/u-boot/include/configs/IPHASE4539.h
new file mode 100644
index 000000000..e402075d3
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/IPHASE4539.h
@@ -0,0 +1,328 @@
+/*
+ * (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de>
+ *
+ * This file is based on similar values for other boards found in
+ * other U-Boot config files, mainly tqm8260.h and mpc8260ads.h.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Config header file for a Interphase 4539 PMC, 64 MB SDRAM, 4MB Flash.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_IPHASE4539	1	/* ...on a Interphase 4539 PMC */
+
+#define	CONFIG_SYS_TEXT_BASE	0xffb00000
+
+#define CONFIG_CPM2		1	/* Has a CPM2 */
+
+/*-----------------------------------------------------------------------
+ * select serial console configuration
+ *
+ * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ *
+ * if CONFIG_CONS_NONE is defined, then the serial console routines must
+ * defined elsewhere (for example, on the cogent platform, there are serial
+ * ports on the motherboard which are used for the serial console - see
+ * cogent/cma101/serial.[ch]).
+ */
+#define	CONFIG_CONS_ON_SMC		/* define if console on SMC */
+#undef	CONFIG_CONS_ON_SCC		/* define if console on SCC */
+#undef	CONFIG_CONS_NONE		/* define if console on something else */
+#define CONFIG_CONS_INDEX	1	/* which serial channel for console */
+
+/*-----------------------------------------------------------------------
+ * select ethernet configuration
+ *
+ * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
+ * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
+ * for FCC)
+ *
+ * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
+ */
+#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC   */
+#define CONFIG_ETHER_ON_FCC		/* define if ether on FCC   */
+#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
+#define CONFIG_ETHER_INDEX	3	/* which channel for ether  */
+
+#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
+
+/*-----------------------------------------------------------------------
+ * - Rx-CLK is CLK14
+ * - Tx-CLK is CLK16
+ * - Select bus for bd/buffers (see 28-13)
+ * - Half duplex
+ */
+# define CONFIG_SYS_CMXFCR_MASK3	(CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE3	(CMXFCR_RF3CS_CLK14 | CMXFCR_TF3CS_CLK16)
+# define CONFIG_SYS_CPMFCR_RAMTYPE	0
+# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+
+#endif	/* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
+
+/* other options */
+
+#define CONFIG_8260_CLKIN	66666666	/* in Hz */
+#define CONFIG_BAUDRATE		19200
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * select i2c support configuration
+ *
+ * Supported configurations are {none, software, hardware} drivers.
+ * If the software driver is chosen, there are some additional
+ * configuration items that the driver uses to drive the port pins.
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED	400000
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0x7F
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
+#define I2C_ACTIVE	(iop->pdir |=  0x00010000)
+#define I2C_TRISTATE	(iop->pdir &= ~0x00010000)
+#define I2C_READ	((iop->pdat & 0x00010000) != 0)
+#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00010000; \
+			else    iop->pdat &= ~0x00010000
+#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00020000; \
+			else    iop->pdat &= ~0x00020000
+#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+#define CONFIG_BOOTCOMMAND	"bootm 100000"	/* autoboot command */
+#define CONFIG_BOOTARGS		"root=/dev/ram rw"
+
+#if defined(CONFIG_CMD_KGDB)
+#undef	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
+#define CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
+#undef	CONFIG_KGDB_NONE		/* define if kgdb on something else */
+#define CONFIG_KGDB_INDEX	2	/* which serial channel for kgdb */
+#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port at */
+#endif
+
+#undef	CONFIG_WATCHDOG			/* disable platform specific watchdog */
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)  /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x00F00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CONFIG_CLOCKS_IN_MHZ	1	/* clocks passed to Linux in MHz */
+					/* for versions < 2.4.5-pre5	 */
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define CONFIG_SYS_RESET_ADDRESS	0x04400000
+
+#define CONFIG_MISC_INIT_R	1	/* We need misc_init_r()	*/
+
+/*-----------------------------------------------------------------------
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration (Setup by the
+ * startup code). Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0.
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFF800000
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)     /* Reserve 256 kB for Monitor  */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	64	/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_SIZE	(CONFIG_SYS_MAX_FLASH_SECT * 0x10000)	/* 4 MB */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	2400000	/* Flash Erase Timeout (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
+
+/* Environment in FLASH, there is little space left in Serial EEPROM */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_SECT_SIZE	0x10000 /* We use one complete sector	*/
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x10000) /* 2. sector */
+
+
+/*-----------------------------------------------------------------------
+ * Hard Reset Configuration Words
+ *
+ * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
+ * defines for the various registers affected by the HRCW e.g. changing
+ * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
+ */
+#define CONFIG_SYS_HRCW_MASTER ( ( HRCW_BPS01 | HRCW_EBM )		|\
+			  ( HRCW_L2CPC10 | HRCW_ISB110 )	|\
+			  ( HRCW_MMR11 | HRCW_APPC10 )		|\
+			  ( HRCW_CS10PC01 | HRCW_MODCK_H0101 )	 \
+			) /* 0x14863245 */
+
+/* no slaves */
+#define CONFIG_SYS_HRCW_SLAVE1 0
+#define CONFIG_SYS_HRCW_SLAVE2 0
+#define CONFIG_SYS_HRCW_SLAVE3 0
+#define CONFIG_SYS_HRCW_SLAVE4 0
+#define CONFIG_SYS_HRCW_SLAVE5 0
+#define CONFIG_SYS_HRCW_SLAVE6 0
+#define CONFIG_SYS_HRCW_SLAVE7 0
+
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xFF000000 /* We keep original value */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	32     /* For MPC8260 CPU		*/
+#if defined(CONFIG_CMD_KGDB)
+# define CONFIG_SYS_CACHELINE_SHIFT	5      /* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * HIDx - Hardware Implementation-dependent Registers		2-11
+ *-----------------------------------------------------------------------
+ * HID0 also contains cache control.
+ *
+ * HID1 has only read-only information - nothing to set.
+ */
+#define CONFIG_SYS_HID0_INIT	(HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
+			 HID0_IFEM|HID0_ABE)
+#define CONFIG_SYS_HID0_FINAL	(HID0_IFEM|HID0_ABE)
+#define CONFIG_SYS_HID2	0
+
+/*-----------------------------------------------------------------------
+ * RMR - Reset Mode Register					 5-5
+ *-----------------------------------------------------------------------
+ * turn on Checkstop Reset Enable
+ */
+#define CONFIG_SYS_RMR		RMR_CSRE
+
+/*-----------------------------------------------------------------------
+ * BCR - Bus Configuration					 4-25
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_BCR		0xA01C0000
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				 4-31
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_SIUMCR	0X4205C000
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				 4-35
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
+ */
+#if defined (CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
+#else
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+			 SYPCR_SWRI|SYPCR_SWP)
+#endif /* CONFIG_WATCHDOG */
+
+/*-----------------------------------------------------------------------
+ * TMCNTSC - Time Counter Status and Control			 4-40
+ * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
+ * and enable Time Counter
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_TMCNTSC	(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		 4-42
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
+ * Periodic timer
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS|PISCR_PTF|PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control					 9-8
+ *-----------------------------------------------------------------------
+ * Ensure DFBRG is Divide by 16
+ */
+#define CONFIG_SYS_SCCR	0
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration				13-7
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RCCR	0
+
+/*-----------------------------------------------------------------------
+ * Init Memory Controller:
+ *
+ * Bank Bus	Machine PortSz	Device
+ * ---- ---	------- ------	------
+ *  0	60x	GPCM	64 bit	FLASH
+ *  1	60x	SDRAM	64 bit	SDRAM
+ */
+
+#define CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) | 0x0801)
+#define CONFIG_SYS_OR0_PRELIM	0xFF800882
+#define CONFIG_SYS_BR1_PRELIM	((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) | 0x0041)
+#define CONFIG_SYS_OR1_PRELIM	0xF8002CD0
+
+#define CONFIG_SYS_PSDMR	0x404A241A
+#define CONFIG_SYS_MPTPR	0x00007400
+#define CONFIG_SYS_PSRT	0x00000007
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/ISPAN.h b/qemu/roms/u-boot/include/configs/ISPAN.h
new file mode 100644
index 000000000..a2fdfd327
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/ISPAN.h
@@ -0,0 +1,330 @@
+/*
+ * Copyright (C) 2004 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * Support for Interphase iSPAN Communications Controllers
+ * (453x and others). Tested on 4532.
+ *
+ * Derived from iSPAN 4539 port (iphase4539) by
+ * Wolfgang Grandegger <wg@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_ISPAN			/* ...on one of Interphase iSPAN boards */
+#define CONFIG_CPM2		1	/* Has a CPM2 */
+
+#define	CONFIG_SYS_TEXT_BASE	0xFE7A0000
+
+/*-----------------------------------------------------------------------
+ * Select serial console configuration
+ *
+ * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ *
+ * If CONFIG_CONS_NONE is defined, then the serial console routines must be
+ * defined elsewhere (for example, on the cogent platform, there are serial
+ * ports on the motherboard which are used for the serial console - see
+ * cogent/cma101/serial.[ch]).
+ */
+#define	CONFIG_CONS_ON_SMC		/* Define if console on SMC		*/
+#undef	CONFIG_CONS_ON_SCC		/* Define if console on SCC		*/
+#undef	CONFIG_CONS_NONE		/* Define if console on something else	*/
+#define CONFIG_CONS_INDEX	1	/* Which serial channel for console	*/
+
+/*-----------------------------------------------------------------------
+ * Select Ethernet configuration
+ *
+ * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
+ * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
+ * for FCC).
+ *
+ * If CONFIG_ETHER_NONE is defined, then either the Ethernet routines must
+ * be defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
+ */
+#undef	CONFIG_ETHER_ON_SCC		/* Define if Ethernet on SCC		*/
+#define CONFIG_ETHER_ON_FCC		/* Define if Ethernet on FCC		*/
+#undef	CONFIG_ETHER_NONE		/* Define if Ethernet on something else */
+#define CONFIG_ETHER_INDEX	3	/* Which channel for Ethernrt		*/
+
+#ifdef CONFIG_ETHER_ON_FCC
+
+#if CONFIG_ETHER_INDEX == 3
+
+#define CONFIG_SYS_PHY_ADDR		0
+#define CONFIG_SYS_CMXFCR_VALUE3	(CMXFCR_RF3CS_CLK14 | CMXFCR_TF3CS_CLK16)
+#define CONFIG_SYS_CMXFCR_MASK3		(CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
+
+#endif /* CONFIG_ETHER_INDEX == 3 */
+
+#define CONFIG_SYS_CPMFCR_RAMTYPE	0
+#define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
+
+#define CONFIG_MII				/* MII PHY management		*/
+#define CONFIG_BITBANGMII			/* Bit-bang MII PHY management	*/
+/*
+ * GPIO pins used for bit-banged MII communications
+ */
+#define MDIO_PORT		3		/* Port D */
+#define MDIO_DECLARE		volatile ioport_t *iop = ioport_addr ( \
+					(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
+#define MDC_DECLARE		MDIO_DECLARE
+
+
+#define CONFIG_SYS_MDIO_PIN		0x00040000	/* PD13 */
+#define CONFIG_SYS_MDC_PIN		0x00080000	/* PD12 */
+
+#define MDIO_ACTIVE		(iop->pdir |=  CONFIG_SYS_MDIO_PIN)
+#define MDIO_TRISTATE		(iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
+#define MDIO_READ		((iop->pdat &  CONFIG_SYS_MDIO_PIN) != 0)
+
+#define MDIO(bit)		if(bit) iop->pdat |=  CONFIG_SYS_MDIO_PIN; \
+				else	iop->pdat &= ~CONFIG_SYS_MDIO_PIN
+
+#define MDC(bit)		if(bit) iop->pdat |=  CONFIG_SYS_MDC_PIN; \
+				else	iop->pdat &= ~CONFIG_SYS_MDC_PIN
+
+#define MIIDELAY		udelay(1)
+
+#endif /* CONFIG_ETHER_ON_FCC */
+
+#define CONFIG_8260_CLKIN	65536000	/* in Hz */
+#define CONFIG_BAUDRATE		38400
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+
+
+#define CONFIG_BOOTDELAY	5		/* autoboot after 5 seconds	*/
+#define CONFIG_BOOTCOMMAND	"bootm fe010000"	/* autoboot command	*/
+#define CONFIG_BOOTARGS		"root=/dev/ram rw"
+
+#define CONFIG_BZIP2		/* Include support for bzip2 compressed images  */
+#undef	CONFIG_WATCHDOG		/* Disable platform specific watchdog		*/
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_LONGHELP				/* #undef to save memory	*/
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)  /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* Max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END		0x03B00000	/* 1 ... 59 MB in SDRAM		*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* Default load address		*/
+
+#define CONFIG_SYS_RESET_ADDRESS	0x09900000
+
+#define CONFIG_MISC_INIT_R			/* We need misc_init_r()	*/
+
+/*-----------------------------------------------------------------------
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor   */
+#ifdef CONFIG_BZIP2
+#define CONFIG_SYS_MALLOC_LEN		(4096 << 10)	/* Reserve 4 MB for malloc()    */
+#else
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 KB for malloc()  */
+#endif /* CONFIG_BZIP2 */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_FLASH_BASE		0xFE000000
+#define CONFIG_SYS_FLASH_CFI				/* The flash is CFI compatible  */
+#define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver        */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* Max num of memory banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	142		/* Max num of sects on one chip */
+
+/* Environment is in flash, there is little space left in Serial EEPROM */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	0x10000		/* We use one complete sector	*/
+#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+/*-----------------------------------------------------------------------
+ * Hard Reset Configuration Words
+ *
+ * If you change bits in the HRCW, you must also change the CONFIG_SYS_*
+ * defines for the various registers affected by the HRCW e.g. changing
+ * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
+ */
+/* 0x1686B245 */
+#define CONFIG_SYS_HRCW_MASTER (HRCW_EBM      | HRCW_BPS01       | HRCW_CIP    |\
+			 HRCW_L2CPC10  | HRCW_ISB110                    |\
+			 HRCW_BMS      | HRCW_MMR11       | HRCW_APPC10 |\
+			 HRCW_CS10PC01 | HRCW_MODCK_H0101                \
+			)
+/* No slaves */
+#define CONFIG_SYS_HRCW_SLAVE1 0
+#define CONFIG_SYS_HRCW_SLAVE2 0
+#define CONFIG_SYS_HRCW_SLAVE3 0
+#define CONFIG_SYS_HRCW_SLAVE4 0
+#define CONFIG_SYS_HRCW_SLAVE5 0
+#define CONFIG_SYS_HRCW_SLAVE6 0
+#define CONFIG_SYS_HRCW_SLAVE7 0
+
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xF0F00000
+#ifdef CONFIG_SYS_REV_B
+#define CONFIG_SYS_DEFAULT_IMMR	0xFF000000
+#endif /* CONFIG_SYS_REV_B */
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPU			*/
+
+/*-----------------------------------------------------------------------
+ * HIDx - Hardware Implementation-dependent Registers		2-11
+ *-----------------------------------------------------------------------
+ * HID0 also contains cache control.
+ *
+ * HID1 has only read-only information - nothing to set.
+ */
+#define CONFIG_SYS_HID0_INIT		(HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
+				HID0_IFEM|HID0_ABE)
+#define CONFIG_SYS_HID0_FINAL		(HID0_ICE|HID0_IFEM|HID0_ABE)
+#define CONFIG_SYS_HID2		0
+
+/*-----------------------------------------------------------------------
+ * RMR - Reset Mode Register					 5-5
+ *-----------------------------------------------------------------------
+ * turn on Checkstop Reset Enable
+ */
+#define CONFIG_SYS_RMR			RMR_CSRE
+
+/*-----------------------------------------------------------------------
+ * BCR - Bus Configuration					 4-25
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_BCR			0xA01C0000
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				 4-31
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_SIUMCR		0x42250000/* 0x4205C000 */
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				 4-35
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
+ */
+#if defined (CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR		(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+				SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
+#else
+#define CONFIG_SYS_SYPCR		(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+				SYPCR_SWRI|SYPCR_SWP)
+#endif /* CONFIG_WATCHDOG */
+
+/*-----------------------------------------------------------------------
+ * TMCNTSC - Time Counter Status and Control			 4-40
+ * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
+ * and enable Time Counter
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_TMCNTSC		(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		 4-42
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
+ * Periodic timer
+ */
+#define CONFIG_SYS_PISCR		(PISCR_PS|PISCR_PTF|PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control					 9-8
+ *-----------------------------------------------------------------------
+ * Ensure DFBRG is Divide by 16
+ */
+#define CONFIG_SYS_SCCR		SCCR_DFBRG01
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration				13-7
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RCCR		0
+
+/*-----------------------------------------------------------------------
+ * Init Memory Controller:
+ *
+ * Bank Bus	Machine PortSize                        Device
+ * ---- ---	------- -----------------------------   ------
+ *  0	60x	GPCM	 8 bit (Rev.B)/16 bit (Rev.D)   Flash
+ *  1	60x	SDRAM	64 bit                          SDRAM
+ *  2	Local	SDRAM	32 bit	                        SDRAM
+ */
+#define CONFIG_SYS_USE_FIRMWARE	/* If defined - do not initialise memory
+				   controller, rely on initialisation
+				   performed by the Interphase boot firmware.
+				 */
+
+#define CONFIG_SYS_OR0_PRELIM		0xFE000882
+#ifdef CONFIG_SYS_REV_B
+#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | BRx_PS_8  | BRx_V)
+#else  /* Rev. D */
+#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | BRx_PS_16 | BRx_V)
+#endif /* CONFIG_SYS_REV_B */
+
+#define CONFIG_SYS_MPTPR		0x7F00
+
+/* Please note that 60x SDRAM MUST start at 0 */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_60x_BR		0x00000041
+#define CONFIG_SYS_60x_OR		0xF0002CD0
+#define CONFIG_SYS_PSDMR		0x0049929A
+#define CONFIG_SYS_PSRT		0x07
+
+#define CONFIG_SYS_LSDRAM_BASE		0xF7000000
+#define CONFIG_SYS_LOC_BR		0x00001861
+#define CONFIG_SYS_LOC_OR		0xFF803280
+#define CONFIG_SYS_LSDMR		0x8285A552
+#define CONFIG_SYS_LSRT		0x07
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/IVML24.h b/qemu/roms/u-boot/include/configs/IVML24.h
new file mode 100644
index 000000000..8aa4ac215
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/IVML24.h
@@ -0,0 +1,458 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC860		1	/* This is a MPC860 CPU		*/
+#define CONFIG_IVML24		1	/* ...on a IVML24 board		*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xFF000000
+
+#if defined (CONFIG_IVML24_16M)
+# define CONFIG_IDENT_STRING     " IVML24"
+#elif defined (CONFIG_IVML24_32M)
+# define CONFIG_IDENT_STRING     " IVML24_128"
+#elif defined (CONFIG_IVML24_64M)
+# define CONFIG_IDENT_STRING     " IVML24_256"
+#endif
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		115200
+
+#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+#define CONFIG_8xx_GCLK_FREQ    50331648
+
+#define CONFIG_RESET_PHY_R	1	/* Call reset_phy()		*/
+
+#define	CONFIG_SHOW_BOOT_PROGRESS 1	/* Show boot progress on LEDs	*/
+
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+#define CONFIG_BOOTCOMMAND	"bootp" /* autoboot command		*/
+
+#define CONFIG_BOOTARGS		"root=/dev/nfs rw "			\
+				"nfsroot=10.0.0.2:/opt/eldk/ppc_8xx "	\
+				"nfsaddrs=10.0.0.99:10.0.0.2"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_IDE
+
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x00F00000	/* 1 ... 15MB in DRAM	*/
+
+#define	CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address	*/
+
+#define	CONFIG_SYS_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/
+
+#define CONFIG_SYS_PB_12V_ENABLE	0x00002000		/* PB 18	*/
+#define CONFIG_SYS_PB_ILOCK_SWITCH	0x00004000		/* PB 17	*/
+#define CONFIG_SYS_PB_SDRAM_CLKE	0x00008000		/* PB 16	*/
+#define CONFIG_SYS_PB_ETH_POWERDOWN	0x00010000		/* PB 15	*/
+#define CONFIG_SYS_PB_IDE_MOTOR	0x00020000		/* PB 14	*/
+
+#define CONFIG_SYS_PC_ETH_RESET	((ushort)0x0010)	/* PC 11	*/
+#define CONFIG_SYS_PC_IDE_RESET	((ushort)0x0020)	/* PC 10	*/
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xFFF00000 /* was: 0xFF000000 */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+
+#if defined (CONFIG_IVML24_16M)
+# define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#elif defined (CONFIG_IVML24_32M)
+# define	CONFIG_SYS_INIT_RAM_SIZE	0x3000	/* Size of used area in DPRAM	*/
+#elif defined (CONFIG_IVML24_64M)
+# define	CONFIG_SYS_INIT_RAM_SIZE	0x3000	/* Size of used area in DPRAM	*/
+#endif
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFF000000
+#ifdef	DEBUG
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#else
+#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#endif
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CONFIG_ENV_IS_IN_FLASH	1
+#define	CONFIG_ENV_OFFSET		0x7A000	/*   Offset   of Environment Sector	*/
+#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+
+# if defined (CONFIG_IVML24_16M)
+#  define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+# elif defined (CONFIG_IVML24_32M)
+#  define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWP)
+# elif defined (CONFIG_IVML24_64M)
+#  define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWP)
+# endif
+
+#else
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+/* EARB, DBGC and DBPC are initialised by the HCW */
+/* => 0x000000C0 */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_BSC | SIUMCR_GB5E)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit, set PLL multiplication factor !
+ */
+/* 0x00B0C0C0 */
+#define CONFIG_SYS_PLPRCR							\
+		(	(11 << PLPRCR_MF_SHIFT) |			\
+			PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/	\
+			/*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |		\
+			PLPRCR_CSR   | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/	\
+		)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+/* 0x01800014 */
+#define CONFIG_SYS_SCCR	(SCCR_COM01	| /*SCCR_TBS|*/		\
+			 SCCR_RTDIV	|   SCCR_RTSEL	  |	\
+			 /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/	\
+			 SCCR_EBDF00	|   SCCR_DFSYNC00 |	\
+			 SCCR_DFBRG00	|   SCCR_DFNL000  |	\
+			 SCCR_DFNH000	|   SCCR_DFLCD101 |	\
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+/* 0x00C3 */
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration Register		19-4
+ *-----------------------------------------------------------------------
+ */
+/* TIMEP=2 */
+#define CONFIG_SYS_RCCR 0x0200
+
+/*-----------------------------------------------------------------------
+ * RMDS - RISC Microcode Development Support Control Register
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RMDS 0
+
+/*-----------------------------------------------------------------------
+ *
+ * Interrupt Levels
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_CPM_INTERRUPT	13	/* SIU_LEVEL6	*/
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_IDE_PREINIT	1	/* Use preinit IDE hook */
+#define CONFIG_IDE_INIT_POSTRESET	1	/* Use postreset IDE hook */
+#define CONFIG_IDE_8xx_DIRECT	1	/* PCMCIA interface required	*/
+#define CONFIG_IDE_RESET	1	/* reset for ide supported	*/
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* The IVML24 has only 1 IDE bus*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/*    ... and only 1 IDE device	*/
+
+#define CONFIG_SYS_ATA_BASE_ADDR	0xFE100000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+#undef	CONFIG_SYS_ATA_IDE1_OFFSET		/* only one IDE bus available	*/
+
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_REG_OFFSET	0x0080	/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100	/* Offset for alternate registers	*/
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0 and OR0 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0xFF000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+/* EPROMs are 512kb */
+#define CONFIG_SYS_REMAP_OR_AM		0xFFF80000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xFFF80000	/* OR addr mask */
+
+/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_SCY_5_CLK | OR_EHTR)
+
+#define CONFIG_SYS_OR0_REMAP	( CONFIG_SYS_REMAP_OR_AM | OR_ACS_DIV4 | OR_BI | \
+				CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | OR_ACS_DIV4 | OR_BI | \
+				CONFIG_SYS_OR_TIMING_FLASH)
+/* 16 bit, bank valid */
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+
+/*
+ * BR1/OR1 - ELIC SACCO bank  @ 0xFE000000
+ *
+ * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1
+ */
+#define ELIC_SACCO_BASE		0xFE000000
+#define ELIC_SACCO_OR_AM	0xFFFF8000
+#define ELIC_SACCO_TIMING	(OR_SCY_2_CLK | OR_TRLX | OR_EHTR)
+
+#define CONFIG_SYS_OR1	(ELIC_SACCO_OR_AM | OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
+			ELIC_SACCO_TIMING)
+#define CONFIG_SYS_BR1	((ELIC_SACCO_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
+
+/*
+ * BR2/OR2 - ELIC EPIC bank   @ 0xFE008000
+ *
+ * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1
+ */
+#define ELIC_EPIC_BASE		0xFE008000
+#define ELIC_EPIC_OR_AM		0xFFFF8000
+#define ELIC_EPIC_TIMING	(OR_SCY_2_CLK | OR_TRLX | OR_EHTR)
+
+#define CONFIG_SYS_OR2 (ELIC_EPIC_OR_AM | OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
+			ELIC_EPIC_TIMING)
+#define CONFIG_SYS_BR2	((ELIC_EPIC_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
+
+/*
+ * BR3/OR3: SDRAM
+ *
+ * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
+ */
+#define SDRAM_BASE3_PRELIM	0x00000000	/* SDRAM bank */
+#define SDRAM_PRELIM_OR_AM	0xF8000000	/* map max. 128 MB */
+#define SDRAM_TIMING		OR_SCY_0_CLK	/* SDRAM-Timing */
+
+#define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB SDRAM */
+
+#define CONFIG_SYS_OR3_PRELIM	(SDRAM_PRELIM_OR_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING )
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V )
+
+/*
+ * BR4/OR4 - HDLC Address
+ *
+ *  AM=0xFFFF8 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=0 BIH=1 SCY=1 SETA=0 TRLX=0 EHTR=0
+ */
+#define HDLC_ADDR_BASE		0xFE108000	/* HDLC Address area */
+#define HDLC_ADDR_OR_AM		0xFFFF8000
+#define HDLC_ADDR_TIMING	OR_SCY_1_CLK
+
+#define CONFIG_SYS_OR4	(HDLC_ADDR_OR_AM | OR_BI | HDLC_ADDR_TIMING)
+#define CONFIG_SYS_BR4	((HDLC_ADDR_BASE & BR_BA_MSK) | BR_PS_8 | BR_WP | BR_V )
+
+/*
+ * BR5/OR5: SHARC ADSP-2165L
+ *
+ * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0
+ */
+#define SHARC_BASE		0xFE400000
+#define SHARC_OR_AM		0xFFC00000
+#define SHARC_TIMING		OR_SCY_0_CLK
+
+#define CONFIG_SYS_OR5	(SHARC_OR_AM | OR_ACS_DIV2 | OR_BI | SHARC_TIMING )
+#define CONFIG_SYS_BR5	((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V )
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CONFIG_SYS_MBMR_PTB	204
+
+/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+
+#if defined (CONFIG_IVML24_16M)
+# define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+#elif defined (CONFIG_IVML24_32M)
+# define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+#elif defined (CONFIG_IVML24_64M)
+# define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV8		/* setting for 1 bank	*/
+#endif
+
+
+/*
+ * MBMR settings for SDRAM
+ */
+
+#if defined (CONFIG_IVML24_16M)
+ /* 8 column SDRAM */
+# define CONFIG_SYS_MBMR_8COL	((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT)  | \
+			 MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 |	\
+			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)
+#elif defined (CONFIG_IVML24_32M)
+/* 128 MBit SDRAM */
+# define CONFIG_SYS_MBMR_8COL	((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT)  | \
+			 MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 |	\
+			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)
+#elif defined (CONFIG_IVML24_64M)
+/* 128 MBit SDRAM */
+# define CONFIG_SYS_MBMR_8COL	((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT)  | \
+			 MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 |	\
+			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)
+#endif
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/IVMS8.h b/qemu/roms/u-boot/include/configs/IVMS8.h
new file mode 100644
index 000000000..0b54af595
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/IVMS8.h
@@ -0,0 +1,441 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC860		1	/* This is a MPC860 CPU		*/
+#define CONFIG_IVMS8		1	/* ...on a IVMS8 board		*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xFF000000
+
+#if defined (CONFIG_IVMS8_16M)
+# define CONFIG_IDENT_STRING     " IVMS8"
+#elif defined (CONFIG_IVMS8_32M)
+# define CONFIG_IDENT_STRING     " IVMS8_128"
+#elif defined (CONFIG_IVMS8_64M)
+# define CONFIG_IDENT_STRING     " IVMS8_256"
+#endif
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_RESET_PHY_R	1	/* Call reset_phy()		*/
+
+#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+#define CONFIG_8xx_GCLK_FREQ    50331648
+
+#define	CONFIG_SHOW_BOOT_PROGRESS 1	/* Show boot progress on LEDs	*/
+
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+#define CONFIG_BOOTCOMMAND	"bootp" /* autoboot command		*/
+
+#define CONFIG_BOOTARGS		"root=/dev/nfs rw "			\
+				"nfsroot=10.0.0.2:/opt/eldk/ppc_8xx "	\
+				"nfsaddrs=10.0.0.99:10.0.0.2"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_IDE
+
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x00F00000	/* 1 ... 15MB in DRAM	*/
+
+#define	CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address	*/
+
+#define	CONFIG_SYS_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/
+
+#define CONFIG_SYS_PB_SDRAM_CLKE	0x00008000		/* PB 16	*/
+#define CONFIG_SYS_PB_ETH_POWERDOWN	0x00010000		/* PB 15	*/
+#define CONFIG_SYS_PB_IDE_MOTOR	0x00020000		/* PB 14	*/
+
+#define CONFIG_SYS_PC_ETH_RESET	((ushort)0x0010)	/* PC 11	*/
+#define CONFIG_SYS_PC_IDE_RESET	((ushort)0x0020)	/* PC 10	*/
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xFFF00000 /* was: 0xFF000000 */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#if defined (CONFIG_IVMS8_16M)
+# define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#elif defined (CONFIG_IVMS8_32M)
+# define	CONFIG_SYS_INIT_RAM_SIZE	0x3000	/* Size of used area in DPRAM	*/
+#elif defined (CONFIG_IVMS8_64M)
+# define	CONFIG_SYS_INIT_RAM_SIZE	0x3000	/* Size of used area in DPRAM	*/
+#endif
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFF000000
+#ifdef	DEBUG
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#else
+#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#endif
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CONFIG_ENV_IS_IN_FLASH	1
+#define	CONFIG_ENV_OFFSET		0x7A000	/*   Offset   of Environment Sector	*/
+#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+# if defined (CONFIG_IVMS8_16M)
+#   define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#  elif defined (CONFIG_IVMS8_32M)
+#   define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWP)
+#  elif defined (CONFIG_IVMS8_64M)
+#   define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWP)
+#  endif
+#else
+# define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+/* EARB, DBGC and DBPC are initialised by the HCW */
+/* => 0x000000C0 */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_BSC | SIUMCR_GB5E)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit, set PLL multiplication factor !
+ */
+/* 0x00B0C0C0 */
+#define CONFIG_SYS_PLPRCR							\
+		(	(11 << PLPRCR_MF_SHIFT) |			\
+			PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/	\
+			/*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |		\
+			PLPRCR_CSR   | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/	\
+		)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+/* 0x01800014 */
+#define CONFIG_SYS_SCCR	(SCCR_COM01	| /*SCCR_TBS|*/		\
+			 SCCR_RTDIV	|   SCCR_RTSEL	  |	\
+			 /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/	\
+			 SCCR_EBDF00	|   SCCR_DFSYNC00 |	\
+			 SCCR_DFBRG00	|   SCCR_DFNL000  |	\
+			 SCCR_DFNH000	|   SCCR_DFLCD101 |	\
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+/* 0x00C3 */
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration Register		19-4
+ *-----------------------------------------------------------------------
+ */
+/* TIMEP=2 */
+#define CONFIG_SYS_RCCR 0x0200
+
+/*-----------------------------------------------------------------------
+ * RMDS - RISC Microcode Development Support Control Register
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RMDS 0
+
+/*-----------------------------------------------------------------------
+ *
+ * Interrupt Levels
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_CPM_INTERRUPT	13	/* SIU_LEVEL6	*/
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_IDE_PREINIT	1	/* Use preinit IDE hook */
+#define CONFIG_IDE_INIT_POSTRESET	1	/* Use postreset IDE hook */
+#define CONFIG_IDE_8xx_DIRECT	1	/* PCMCIA interface required	*/
+#define CONFIG_IDE_RESET	1	/* reset for ide supported	*/
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* The IVMS8 has only 1 IDE bus	*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/*    ... and only 1 IDE device	*/
+
+#define CONFIG_SYS_ATA_BASE_ADDR	0xFE100000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+#undef	CONFIG_SYS_ATA_IDE1_OFFSET		/* only one IDE bus available	*/
+
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_REG_OFFSET	0x0080	/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100	/* Offset for alternate registers	*/
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0 and OR0 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0xFF000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+/* EPROMs are 512kb */
+#define CONFIG_SYS_REMAP_OR_AM		0xFFF80000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xFFF80000	/* OR addr mask */
+
+/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
+#define CONFIG_SYS_OR_TIMING_FLASH	(/* OR_CSNT_SAM | */ OR_ACS_DIV4 | OR_BI | \
+				 OR_SCY_5_CLK | OR_EHTR)
+
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+/* 16 bit, bank valid */
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+
+/*
+ * BR1/OR1 - ELIC SACCO bank  @ 0xFE000000
+ *
+ * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1
+ */
+#define ELIC_SACCO_BASE		0xFE000000
+#define ELIC_SACCO_OR_AM	0xFFFF8000
+#define ELIC_SACCO_TIMING	0x00000F26
+
+#define CONFIG_SYS_OR1	(ELIC_SACCO_OR_AM | ELIC_SACCO_TIMING)
+#define CONFIG_SYS_BR1	((ELIC_SACCO_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
+
+/*
+ * BR2/OR2 - ELIC EPIC bank   @ 0xFE008000
+ *
+ * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1
+ */
+#define ELIC_EPIC_BASE		0xFE008000
+#define ELIC_EPIC_OR_AM		0xFFFF8000
+#define ELIC_EPIC_TIMING	0x00000F26
+
+#define CONFIG_SYS_OR2 (ELIC_EPIC_OR_AM | ELIC_EPIC_TIMING)
+#define CONFIG_SYS_BR2	((ELIC_EPIC_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
+
+/*
+ * BR3/OR3: SDRAM
+ *
+ * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
+ */
+#define SDRAM_BASE3_PRELIM	0x00000000	/* SDRAM bank */
+#define SDRAM_PRELIM_OR_AM	0xF8000000	/* map max. 128 MB */
+#define SDRAM_TIMING		0x00000A00	/* SDRAM-Timing */
+
+#define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB SDRAM */
+
+#define CONFIG_SYS_OR3_PRELIM	(SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V )
+
+/*
+ * BR4/OR4: not used
+ */
+
+/*
+ * BR5/OR5: SHARC ADSP-2165L
+ *
+ * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0
+ */
+#define SHARC_BASE		0xFE400000
+#define SHARC_OR_AM		0xFFC00000
+#define SHARC_TIMING		0x00000700
+
+#define CONFIG_SYS_OR5	(SHARC_OR_AM | SHARC_TIMING )
+#define CONFIG_SYS_BR5	((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V )
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CONFIG_SYS_MBMR_PTB	204
+
+/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#if defined (CONFIG_IVMS8_16M)
+ #define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+#elif defined (CONFIG_IVMS8_32M)
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+#elif defined (CONFIG_IVMS8_64M)
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV8		/* setting for 1 bank	*/
+#endif
+
+
+/*
+ * MBMR settings for SDRAM
+ */
+
+#if defined (CONFIG_IVMS8_16M)
+ /* 8 column SDRAM */
+# define CONFIG_SYS_MBMR_8COL	((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT)  | \
+			 MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 |	\
+			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)
+#elif defined (CONFIG_IVMS8_32M)
+/* 128 MBit SDRAM */
+#define CONFIG_SYS_MBMR_8COL	((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT)  | \
+			 MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 |	\
+			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)
+#elif defined (CONFIG_IVMS8_64M)
+/* 128 MBit SDRAM */
+#define CONFIG_SYS_MBMR_8COL	((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT)  | \
+			 MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 |	\
+			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)
+
+#endif
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/IceCube.h b/qemu/roms/u-boot/include/configs/IceCube.h
new file mode 100644
index 000000000..1861aa86d
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/IceCube.h
@@ -0,0 +1,403 @@
+/*
+ * (C) Copyright 2003-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5200		1	/* This is a MPC5200 CPU */
+#define CONFIG_ICECUBE		1	/* ... on IceCube board */
+
+/*
+ * Valid values for CONFIG_SYS_TEXT_BASE are:
+ * 0xFFF00000	boot high (standard configuration)
+ * 0xFF000000	boot low for 16 MiB boards
+ * 0xFF800000	boot low for  8 MiB boards
+ * 0x00100000	boot from RAM (for testing only)
+ */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
+#endif
+
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
+
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
+#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+
+/*
+ * PCI Mapping:
+ * 0x40000000 - 0x4fffffff - PCI Memory
+ * 0x50000000 - 0x50ffffff - PCI IO Space
+ */
+#define CONFIG_PCI
+
+#if defined(CONFIG_PCI)
+#define CONFIG_PCI_PNP		1
+#define CONFIG_PCI_SCAN_SHOW	1
+#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1
+
+#define CONFIG_PCI_MEM_BUS	0x40000000
+#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE	0x10000000
+
+#define CONFIG_PCI_IO_BUS	0x50000000
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0x01000000
+#endif
+
+#define CONFIG_SYS_XLB_PIPELINING	1
+
+#define CONFIG_MII		1
+#define CONFIG_EEPRO100		1
+#define CONFIG_SYS_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
+#define CONFIG_NS8382X		1
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+/* USB */
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_USB_STORAGE
+#define CONFIG_SYS_OHCI_BE_CONTROLLER
+#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
+#define CONFIG_SYS_USB_OHCI_CPU_INIT	1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE	MPC5XXX_USB
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"mpc5200"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
+
+#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_USB
+
+#if defined(CONFIG_PCI)
+#define CONFIG_CMD_PCI
+#endif
+
+
+#if (CONFIG_SYS_TEXT_BASE == 0xFF000000)		/* Boot low with 16 MB Flash */
+#   define CONFIG_SYS_LOWBOOT	        1
+#   define CONFIG_SYS_LOWBOOT16	1
+#endif
+#if (CONFIG_SYS_TEXT_BASE == 0xFF800000)		/* Boot low with  8 MB Flash */
+#if defined(CONFIG_LITE5200B)
+#   error CONFIG_SYS_LOWBOOT08 is incompatible with the Lite5200B
+#else
+#   define CONFIG_SYS_LOWBOOT	        1
+#   define CONFIG_SYS_LOWBOOT08	1
+#endif
+#endif
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_82xx\0"					\
+	"bootfile=/tftpboot/MPC5200/uImage\0"				\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#if defined(CONFIG_LITE5200B)
+#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK	/* define for 133MHz speed */
+#else
+#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
+#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+#define OF_CPU			"PowerPC,5200@0"
+#define OF_SOC			"soc5200@f0000000"
+#define OF_TBCLK		(bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH		"/soc5200@f0000000/serial@2000"
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #1 or #2 */
+
+#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	70
+
+/*
+ * Flash configuration
+ */
+#if defined(CONFIG_LITE5200B)
+#define CONFIG_SYS_FLASH_BASE		0xFE000000
+#define CONFIG_SYS_FLASH_SIZE		0x01000000
+#if !defined(CONFIG_SYS_LOWBOOT)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x01760000 + 0x00800000)
+#else	/* CONFIG_SYS_LOWBOOT */
+#if defined(CONFIG_SYS_LOWBOOT08)
+# error CONFIG_SYS_LOWBOOT08 is incompatible with the Lite5200B
+#endif
+#if defined(CONFIG_SYS_LOWBOOT16)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x01060000)
+#endif
+#endif /* CONFIG_SYS_LOWBOOT */
+#else /* !CONFIG_LITE5200B (IceCube)*/
+#define CONFIG_SYS_FLASH_BASE		0xFF000000
+#define CONFIG_SYS_FLASH_SIZE		0x01000000
+#if !defined(CONFIG_SYS_LOWBOOT)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00740000 + 0x00800000)
+#else	/* CONFIG_SYS_LOWBOOT */
+#if defined(CONFIG_SYS_LOWBOOT08)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00040000 + 0x00800000)
+#endif
+#if defined(CONFIG_SYS_LOWBOOT16)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00040000)
+#endif
+#endif	/* CONFIG_SYS_LOWBOOT */
+#endif /* CONFIG_LITE5200B */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max num of memory banks      */
+
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+
+#undef CONFIG_FLASH_16BIT	/* Flash is 8-bit */
+
+#if defined(CONFIG_LITE5200B)
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_CS1_START,CONFIG_SYS_CS0_START}
+#endif
+
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_SIZE		0x10000
+#if defined(CONFIG_LITE5200B)
+#define CONFIG_ENV_SECT_SIZE	0x20000
+#else
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#endif
+#define CONFIG_ENV_OVERWRITE	1
+
+/*
+ * Memory map
+ */
+#define CONFIG_SYS_MBAR		0xF0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
+
+/* Use SRAM until RAM will be available */
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */
+
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC	1
+#define CONFIG_MPC5xxx_FEC_MII100
+/*
+ * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
+ */
+/* #define CONFIG_MPC5xxx_FEC_MII10 */
+#define CONFIG_PHY_ADDR		0x00
+
+/*
+ * GPIO configuration
+ */
+#ifdef CONFIG_MPC5200_DDR
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x90000004
+#else
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x10000004
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_SYS_HUSH_PARSER		1	/* use "hush" command parser	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
+
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*
+ * Various low-level settings
+ */
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
+
+#if defined(CONFIG_LITE5200B)
+#define CONFIG_SYS_CS1_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS1_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_CS1_CFG		0x00047800
+#define CONFIG_SYS_CS0_START		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE)
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_CS0_START
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_CFG		0x00047800
+#else /* IceCube aka Lite5200 */
+#ifdef CONFIG_MPC5200_DDR
+
+#define CONFIG_SYS_BOOTCS_START	(CONFIG_SYS_CS1_START + CONFIG_SYS_CS1_SIZE)
+#define CONFIG_SYS_BOOTCS_SIZE		0x00800000
+#define CONFIG_SYS_BOOTCS_CFG		0x00047801
+#define CONFIG_SYS_CS1_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS1_SIZE		0x00800000
+#define CONFIG_SYS_CS1_CFG		0x00047800
+
+#else /* !CONFIG_MPC5200_DDR */
+
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_CFG		0x00047801
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
+
+#endif /* CONFIG_MPC5200_DDR */
+#endif /*CONFIG_LITE5200B */
+
+#define CONFIG_SYS_CS_BURST		0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE	0x33333333
+
+#define CONFIG_SYS_RESET_ADDRESS	0xff000000
+
+/*-----------------------------------------------------------------------
+ * USB stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_USB_CLOCK	0x0001BBBB
+#define CONFIG_USB_CONFIG	0x00001000
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+
+#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+
+#define	CONFIG_IDE_RESET		/* reset for ide supported	*/
+#define CONFIG_IDE_PREINIT
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	2	/* max. 1 drive per IDE bus	*/
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
+
+/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
+
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)
+
+/* Interval between registers                                                */
+#define CONFIG_SYS_ATA_STRIDE          4
+
+#define CONFIG_ATAPI            1
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/JSE.h b/qemu/roms/u-boot/include/configs/JSE.h
new file mode 100644
index 000000000..5cc25576a
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/JSE.h
@@ -0,0 +1,276 @@
+/*
+ * (C) Copyright 2003 Picture Elements, Inc.
+ * Stephen Williams <steve@icarus.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options for the JSE board
+ * (Theoretically easy to change, but the board is fixed.)
+ */
+
+#define CONFIG_JSE 1
+  /* JSE has a PPC405GPr */
+#define CONFIG_405GP 1
+  /* ... with a 33MHz OSC. connected to the SysCLK input */
+#define CONFIG_SYS_CLK_FREQ	33333333
+  /* ... with on-chip memory here (4KBytes) */
+#define CONFIG_SYS_OCM_DATA_ADDR 0xF4000000
+#define CONFIG_SYS_OCM_DATA_SIZE 0x00001000
+  /* Do not set up locked dcache as init ram. */
+#undef CONFIG_SYS_INIT_DCACHE_CS
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFF80000
+
+  /* Map the SystemACE chip (CS#1) here. (Must be a multiple of 1Meg) */
+#define CONFIG_SYSTEMACE 1
+#define CONFIG_SYS_SYSTEMACE_BASE 0xf0000000
+#define CONFIG_SYS_SYSTEMACE_WIDTH 8
+#define CONFIG_DOS_PARTITION 1
+
+  /* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */
+#define CONFIG_SYS_TEMP_STACK_OCM 1
+  /* ... place INIT RAM in the OCM address */
+# define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR
+  /* ... give it the whole init ram */
+# define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE
+  /* ... Shave a bit off the end for global data */
+# define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+  /* ... and place the stack pointer at the top of what's left. */
+# define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+  /* Enable board_pre_init function */
+#define CONFIG_BOARD_PRE_INIT	1
+#define CONFIG_BOARD_EARLY_INIT_F 1
+  /* Disable post-clk setup init function */
+#undef CONFIG_BOARD_POSTCLK_INIT
+  /* Disable call to post_init_f: late init function. */
+#undef CONFIG_POST
+  /* Enable DRAM test. */
+#define CONFIG_SYS_DRAM_TEST 1
+  /* Enable misc_init_r function. */
+#define CONFIG_MISC_INIT_R 1
+
+  /* JSE has EEPROM chips that are good for environment. */
+#undef	CONFIG_ENV_IS_IN_NVRAM
+#undef	CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_IS_IN_EEPROM 1
+#undef	CONFIG_ENV_IS_NOWHERE
+
+  /* This is the 7bit address of the device, not including P. */
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
+  /* After the device address, need one more address byte. */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+  /* The EEPROM is 512 bytes. */
+#define CONFIG_SYS_EEPROM_SIZE 512
+  /* The EEPROM can do 16byte ( 1 << 4 ) page writes. */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
+  /* Put the environment in the second half. */
+#define CONFIG_ENV_OFFSET	0x00
+#define CONFIG_ENV_SIZE	512
+
+  /* The JSE connects UART1 to the console tap connector. */
+#define CONFIG_CONS_INDEX	2
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+
+  /* Set console baudrate to 9600 */
+#define CONFIG_BAUDRATE		9600
+
+/*
+ * Configuration related to auto-boot.
+ *
+ * CONFIG_BOOTDELAY sets the delay (in seconds) that U-Boot will wait
+ * before resorting to autoboot. This value can be overridden by the
+ * bootdelay environment variable.
+ *
+ * CONFIG_AUTOBOOT_PROMPT is the string that U-Boot emits to warn the
+ * user that an autoboot will happen.
+ *
+ * CONFIG_BOOTCOMMAND is the sequence of commands that U-Boot will
+ * execute to boot the JSE. This loads the uimage and initrd.img files
+ * from CompactFlash into memory, then boots them from memory.
+ *
+ * CONFIG_BOOTARGS is the arguments passed to the Linux kernel to get
+ * it going on the JSE.
+ */
+#define CONFIG_BOOTDELAY	5
+#define CONFIG_BOOTARGS		"root=/dev/ram0 init=/linuxrc rw"
+#define CONFIG_BOOTCOMMAND	"fatload ace 0 2000000 uimage; fatload ace 0 2100000 initrd.img; bootm 2000000 2100000"
+
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_PPC4xx_EMAC
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		1	/* PHY address			*/
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+
+
+  /* watchdog disabled */
+#undef CONFIG_WATCHDOG
+  /* SPD EEPROM (sdram speed config) disabled */
+#undef CONFIG_SPD_EEPROM
+#undef SPD_EEPROM_ADDRESS
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+
+#define CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+/*
+ * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
+ * The Linux BASE_BAUD define should match this configuration.
+ *    baseBaud = cpuClock/(uartDivisor*16)
+ * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * set Linux BASE_BAUD to 403200.
+ */
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* external serial clock */
+#undef	CONFIG_SYS_405_UART_ERRATA_59	       /* 405GP/CR Rev. D silicon */
+#define CONFIG_SYS_BASE_BAUD	    691200
+
+/* The following table includes the supported baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
+
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0		/* configure ar pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_HOST PCI_HOST_FORCE	/* select pci host function	*/
+#undef	CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+					/* resource configuration	*/
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000	/* PCI Vendor ID: to-do!!!	*/
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000	/* PCI Device ID: to-do!!!	*/
+#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CONFIG_SYS_PCI_PTM1MS	0x80000001	/* 2GB, enable hard-wired to 1	*/
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CONFIG_SYS_PCI_PTM2LA	0x00000000	/* disabled			*/
+#define CONFIG_SYS_PCI_PTM2MS	0x00000000	/* disabled			*/
+#define CONFIG_SYS_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+
+/*-----------------------------------------------------------------------
+ * External peripheral base address
+ *-----------------------------------------------------------------------
+ */
+#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
+#undef	CONFIG_IDE_RESET		/* no reset for ide supported	*/
+
+#define CONFIG_SYS_KEY_REG_BASE_ADDR	0xF0100000
+#define CONFIG_SYS_IR_REG_BASE_ADDR	0xF0200000
+#define CONFIG_SYS_FPGA_REG_BASE_ADDR	0xF0300000
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFF80000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	CONFIG_SYS_FLASH_BASE	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0		/* FLASH bank #1	*/
+
+
+/* Configuration Port location */
+#define CONFIG_PORT_ADDR	0xF0000500
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/KAREF.h b/qemu/roms/u-boot/include/configs/KAREF.h
new file mode 100644
index 000000000..546b72531
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/KAREF.h
@@ -0,0 +1,284 @@
+/*
+ * (C) Copyright 2004 Sandburst Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/************************************************************************
+ * KAMINOREFDES.h - configuration for the Sandburst Kamino Reference
+ *		    design.
+ ***********************************************************************/
+
+/*
+ * $Id: KAREF.h,v 1.6 2005/06/03 15:05:25 tsawyer Exp $
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_KAREF	     1		/* Board is Kamino Ref Variant */
+#define CONFIG_440GX		  1	     /* Specifc GX support	*/
+#define CONFIG_440		  1	     /* ... PPC440 family	*/
+#define CONFIG_BOARD_EARLY_INIT_F 1	     /* Call board_pre_init	*/
+#define CONFIG_MISC_INIT_F	  1	     /* Call board misc_init_f	*/
+#define CONFIG_MISC_INIT_R	  1	     /* Call board misc_init_r	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFF80000
+
+#undef	CONFIG_SYS_DRAM_TEST			     /* Disable-takes long time!*/
+#define CONFIG_SYS_CLK_FREQ	  66666666   /* external freq to pll	*/
+
+#define CONFIG_VERY_BIG_RAM 1
+#define CONFIG_VERSION_VARIABLE
+
+#define CONFIG_IDENT_STRING " Sandburst Kamino Reference Design"
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_SDRAM_BASE	       0x00000000    /* _must_ be 0		*/
+#define CONFIG_SYS_FLASH_BASE	       0xfff80000    /* start of FLASH		*/
+#define CONFIG_SYS_MONITOR_BASE       0xfff80000    /* start of monitor	*/
+#define CONFIG_SYS_PCI_MEMBASE	       0x80000000    /* mapped pci memory	*/
+#define CONFIG_SYS_ISRAM_BASE	       0xc0000000    /* internal SRAM		*/
+#define CONFIG_SYS_PCI_BASE	       0xd0000000    /* internal PCI regs	*/
+
+#define CONFIG_SYS_NVRAM_BASE_ADDR   (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
+#define CONFIG_SYS_KAREF_FPGA_BASE   (CONFIG_SYS_PERIPHERAL_BASE + 0x08200000)
+#define CONFIG_SYS_OFEM_FPGA_BASE    (CONFIG_SYS_PERIPHERAL_BASE + 0x08400000)
+#define CONFIG_SYS_BME32_BASE	      (CONFIG_SYS_PERIPHERAL_BASE + 0x08500000)
+#define CONFIG_SYS_GPIO_BASE	      (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)
+
+/* Here for completeness */
+#define CONFIG_SYS_OFEMAC_BASE	      (CONFIG_SYS_PERIPHERAL_BASE + 0x08600000)
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in internal SRAM)
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_TEMP_STACK_OCM    1
+#define CONFIG_SYS_OCM_DATA_ADDR     CONFIG_SYS_ISRAM_BASE
+#define CONFIG_SYS_INIT_RAM_ADDR     CONFIG_SYS_ISRAM_BASE /* Initial RAM address	*/
+#define CONFIG_SYS_INIT_RAM_SIZE      0x2000	     /* Size of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET    (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
+
+#define CONFIG_SYS_MONITOR_LEN	      (256 * 1024)   /* Rsrv 256kB for Mon	*/
+#define CONFIG_SYS_MALLOC_LEN	      (128 * 1024)   /* Rsrv 128kB for malloc	*/
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+#define CONFIG_BAUDRATE	      9600
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * NVRAM/RTC
+ *
+ * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
+ * The DS1743 code assumes this condition (i.e. -- it assumes the base
+ * address for the RTC registers is:
+ *
+ *	CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE
+ *
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_NVRAM_SIZE	      (0x2000 - 8)   /* NVRAM size(8k)- RTC regs*/
+#define CONFIG_RTC_DS174x     1		     /* DS1743 RTC		*/
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_MAX_FLASH_BANKS   1		     /* number of banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT    8		     /* sectors per device	*/
+
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT  120000	     /* Flash Erase TO (in ms)	 */
+#define CONFIG_SYS_FLASH_WRITE_TOUT  500	     /* Flash Write TO(in ms)	 */
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CONFIG_SPD_EEPROM     1		     /* Use SPD EEPROM for setup*/
+#define SPD_EEPROM_ADDRESS    {0x53}	     /* SPD i2c spd addresses	*/
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
+#define CONFIG_SYS_I2C_PPC4XX_CH1
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_1 400000 /* I2C speed 400kHz */
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_1 0x7F
+#define CONFIG_SYS_I2C_NOPROBES { { 0, 0x69} } /* Don't probe these addrs */
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+#define CONFIG_ENV_IS_IN_NVRAM   1		     /* Environment uses NVRAM	*/
+#undef	CONFIG_ENV_IS_IN_FLASH		     /* ... not in flash	*/
+#undef	CONFIG_ENV_IS_IN_EEPROM		     /* ... not in EEPROM	*/
+#define CONFIG_ENV_OVERWRITE  1		     /* allow env overwrite	*/
+
+#define CONFIG_ENV_SIZE	      0x1000	     /* Size of Env vars	*/
+#define CONFIG_ENV_ADDR	      (CONFIG_SYS_NVRAM_BASE_ADDR)
+
+#define CONFIG_BOOTDELAY      5		    /* 5 second autoboot */
+
+#define CONFIG_LOADS_ECHO     1		     /* echo on for serial dnld */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE 1		     /* allow baudrate change	*/
+
+/*-----------------------------------------------------------------------
+ * Networking
+ *----------------------------------------------------------------------*/
+#define CONFIG_PPC4xx_EMAC
+#define CONFIG_MII	      1		     /* MII PHY management	*/
+#define CONFIG_PHY_ADDR	      0xff	     /* no phy on EMAC0		*/
+#define CONFIG_PHY1_ADDR      0xff	     /* no phy on EMAC1		*/
+#define CONFIG_PHY2_ADDR      0x08	     /* PHY addr, MGMT, EMAC2	*/
+#define CONFIG_PHY3_ADDR      0x18	     /* PHY addr, LCL, EMAC3	*/
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+#define CONFIG_HAS_ETH3
+#define CONFIG_PHY_RESET      1              /* reset phy upon startup  */
+#define CONFIG_CIS8201_PHY    1		     /* RGMII mode for Cicada	*/
+#define CONFIG_CIS8201_SHORT_ETCH 1	     /* Use short etch mode	*/
+#define CONFIG_PHY_GIGE	      1		     /* GbE speed/duplex detect */
+#define CONFIG_PHY_RESET_DELAY 1000
+#define CONFIG_NETMASK	      255.255.0.0
+#define CONFIG_ETHADDR	      00:00:00:00:00:00 /* No EMAC 0 support	*/
+#define CONFIG_ETH1ADDR	      00:00:00:00:00:00 /* No EMAC 1 support	*/
+#define CONFIG_SYS_RX_ETH_BUFFER     32	     /* #eth rx buff & descrs	*/
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FAT
+
+
+/* Include NetConsole support */
+#define CONFIG_NETCONSOLE
+
+/* Include auto complete with tabs */
+#define CONFIG_AUTO_COMPLETE 1
+#define CONFIG_SYS_ALT_MEMTEST	     1	     /* use real memory test	 */
+
+#define CONFIG_SYS_LONGHELP			     /* undef to save memory	*/
+#define CONFIG_SYS_PROMPT	      "KaRefDes=> "  /* Monitor Command Prompt	*/
+
+#define CONFIG_SYS_HUSH_PARSER	       1	     /* HUSH for ext'd cli	*/
+
+
+/*-----------------------------------------------------------------------
+ * Console Buffer
+ *----------------------------------------------------------------------*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	      1024	     /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	      256	     /* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+					     /* Print Buffer Size	*/
+#define CONFIG_SYS_MAXARGS	      16	     /* max number of cmd args	*/
+#define CONFIG_SYS_BARGSIZE	      CONFIG_SYS_CBSIZE     /* Boot Arg Buffer Size	*/
+
+/*-----------------------------------------------------------------------
+ * Memory Test
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_MEMTEST_START     0x0400000	     /* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END	      0x0C00000	     /* 4 ... 12 MB in DRAM	*/
+
+/*-----------------------------------------------------------------------
+ * Compact Flash (in true IDE mode)
+ *----------------------------------------------------------------------*/
+#undef	CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
+#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
+
+#define CONFIG_IDE_RESET		/* reset for ide supported	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE busses	*/
+#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+
+#define CONFIG_SYS_ATA_BASE_ADDR	0xF0000000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	 /* Offset for data I/O */
+#define CONFIG_SYS_ATA_REG_OFFSET	0x0000	 /* Offset for normal register accesses*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x100000 /* Offset for alternate registers */
+
+#define CONFIG_SYS_ATA_STRIDE		2	 /* Directly connected CF, needs a stride
+					    to get to the correct offset */
+#define CONFIG_DOS_PARTITION  1		     /* Include dos partition	*/
+
+/*-----------------------------------------------------------------------
+ * PCI
+ *----------------------------------------------------------------------*/
+/* General PCI */
+#define CONFIG_PCI			     /* include pci support	*/
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_PNP			     /* do pci plug-and-play	*/
+#define CONFIG_PCI_SCAN_SHOW		     /* show pci devices	*/
+#define CONFIG_SYS_PCI_TARGBASE      (CONFIG_SYS_PCI_MEMBASE)
+
+/* Board-specific PCI */
+#define CONFIG_SYS_PCI_TARGET_INIT		     /* let board init pci target*/
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x17BA	     /* Sandburst */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	     /* Whatever */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE  230400	     /* kgdb serial port baud	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ *----------------------------------------------------------------------*/
+#undef CONFIG_WATCHDOG			     /* watchdog disabled	*/
+#define CONFIG_SYS_LOAD_ADDR	      0x8000000	     /* default load address	*/
+#define CONFIG_SYS_EXTBDINFO	      1		     /* use extended board_info */
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/KUP4K.h b/qemu/roms/u-boot/include/configs/KUP4K.h
new file mode 100644
index 000000000..7cf09d01f
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/KUP4K.h
@@ -0,0 +1,488 @@
+/*
+  * (C) Copyright 2000-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ * Derived from ../tqm8xx/tqm8xx.c
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC855		1	/* This is a MPC855 CPU		*/
+#define CONFIG_KUP4K		1	/* ...on a KUP4K module */
+
+#define	CONFIG_SYS_TEXT_BASE	0x40000000
+
+#define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		115200	/* console baudrate		*/
+#define CONFIG_BOOTDELAY	1	/* autoboot after 1 second	*/
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#undef	CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS						\
+"slot_a_boot=setenv bootargs root=/dev/sda2 ip=off;"				\
+ "run addhw; mw.b 400000 00 80; diskboot 400000 0:1; bootm 400000\0"		\
+"slot_b_boot=setenv bootargs root=/dev/sda2 ip=off;"				\
+ "run addhw; mw.b 400000 00 80; diskboot 400000 2:1; bootm 400000\0"		\
+"nfs_boot=mw.b 400000 00 80; dhcp; run nfsargs addip addhw; bootm 400000\0"	\
+"fat_boot=mw.b 400000 00 80; fatload ide 2:1 400000 st.bin; run addhw;		\
+ bootm 400000 \0"								\
+"panic_boot=echo No Bootdevice !!! reset\0"					\
+"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${rootpath}\0"		\
+"ramargs=setenv bootargs root=/dev/ram rw\0"					\
+"addip=setenv bootargs ${bootargs} ip=${ipaddr}::${gatewayip}"			\
+ ":${netmask}:${hostname}:${netdev}:off\0"					\
+"addhw=setenv bootargs ${bootargs} ${mtdparts} console=${console} ${debug}	\
+ hw=${hw} key1=${key1} panic=1 mem=${mem}\0"					\
+"console=ttyCPM0,115200\0"							\
+"netdev=eth0\0"									\
+"contrast=20\0"									\
+"silent=1\0"									\
+"mtdparts=" MTDPARTS_DEFAULT "\0"						\
+"load=tftp 200000 bootloader-4k.bitmap;tftp 100000 bootloader-4k.bin\0"		\
+"update=protect off 1:0-9;era 1:0-9;cp.b 100000 40000000 ${filesize};"		\
+ "cp.b 200000 40050000 14000\0"
+
+#define CONFIG_BOOTCOMMAND  \
+    "run fat_boot;run slot_b_boot;run slot_a_boot;run nfs_boot;run panic_boot"
+
+#define CONFIG_PREBOOT	"setenv preboot; saveenv"
+
+#define CONFIG_MISC_INIT_R	1
+#define CONFIG_MISC_INIT_F	1
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE	/* don't allow baudrate change	*/
+
+#define	CONFIG_WATCHDOG	1		/* watchdog enabled		*/
+
+#define CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+/*
+ * enable I2C and select the hardware/software driver
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED	93000	/* 93 kHz is supposed to work */
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
+
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PB_SCL		0x00000020	/* PB 26 */
+#define PB_SDA		0x00000010	/* PB 27 */
+
+#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
+#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
+#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
+#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
+#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
+#define I2C_DELAY	udelay(2)	/* 1/4 I2C clock duration */
+
+/*-----------------------------------------------------------------------
+ * I2C Configuration
+ */
+
+#define CONFIG_SYS_I2C_PICIO_ADDR	0x21	/* PCF8574 IO Expander */
+#define CONFIG_SYS_I2C_RTC_ADDR		0x51	/* PCF8563 RTC */
+
+/* List of I2C addresses to be verified by POST */
+
+#define CONFIG_SYS_POST_I2C_ADDRS	{CONFIG_SYS_I2C_PICIO_ADDR,	\
+					 CONFIG_SYS_I2C_RTC_ADDR,	\
+					}
+
+#define CONFIG_RTC_PCF8563		/* use Philips PCF8563 RTC	*/
+
+#define CONFIG_SYS_DISCOVER_PHY
+#define CONFIG_MII
+
+/* Define to allow the user to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_SNTP
+
+#ifdef CONFIG_POST
+    #define CONFIG_CMD_DIAG
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	512		/* Console I/O Buffer Size	*/
+#endif
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x000400000	/* memtest works on     */
+#define CONFIG_SYS_MEMTEST_END		0x005C00000	/* 4 ... 92 MB in DRAM  */
+#define CONFIG_SYS_ALT_MEMTEST 1
+#define CONFIG_SYS_MEMTEST_SCRATCH	0x90000200	/* using latch as scratch register */
+
+#define CONFIG_SYS_LOAD_ADDR		0x400000	/* default load address */
+
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 115200 }
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET 1
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	19	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_OFFSET		0x40000 /*   Offset   of Environment Sector	*/
+#define CONFIG_ENV_SIZE		0x1000	/* Total Size of Environment Sector	*/
+#define CONFIG_ENV_SECT_SIZE	0x10000
+
+/*-----------------------------------------------------------------------
+ * Dynamic MTD partition support
+ */
+#define MTDPARTS_DEFAULT	"mtdparts=40000000.flash:256k(u-boot),"	\
+						"64k(env),"		\
+						"128k(splash),"		\
+						"512k(etc),"		\
+						"64k(hw-info)"
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CONFIG_SYS_HWINFO_OFFSET	0x000F0000	/* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE		0x00000100	/* size   of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC	0x4B26500D		/* 'K&P<CR>' */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ *
+ * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
+ */
+#define CONFIG_SYS_PLPRCR ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF00
+#define CONFIG_SYS_SCCR	(SCCR_TBS | SCCR_EBDF01 |  \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+
+/* KUP4K use both slots, SLOT_A as "primary". */
+#define CONFIG_PCMCIA_SLOT_A 1
+
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
+
+#define PCMCIA_SOCKETS_NO 2
+#define PCMCIA_MEM_WIN_NO 8
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_IDE_PREINIT	1	/* Use preinit IDE hook */
+#define CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card Adapter */
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
+#define CONFIG_IDE_LED		1	/* LED	 for ide supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CONFIG_SYS_IDE_MAXBUS		2
+#define CONFIG_SYS_IDE_MAXDEVICE	4
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_IDE1_OFFSET	(4 * CONFIG_SYS_PCMCIA_MEM_SIZE)
+
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_DER 0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV2  | OR_CSNT_SAM | \
+				 OR_SCY_5_CLK | OR_EHTR | OR_BI)
+
+#define CONFIG_SYS_OR0_REMAP \
+	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM \
+	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM \
+	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ *	gclk	  CPU clock (not bus clock!)
+ *	Trefresh  Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096	 Rows from SDRAM example configuration
+ * 1000	 factor s -> ms
+ *   32	 PTP (pre-divider from MPTPR) from SDRAM example configuration
+ *    4	 Number of refresh cycles per period
+ *   64	 Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ * 50 MHz => 50.000.000 / Divider =  98
+ * 66 Mhz => 66.000.000 / Divider = 129
+ * 80 Mhz => 80.000.000 / Divider = 156
+ */
+#if   defined(CONFIG_80MHz)
+#define CONFIG_SYS_MAMR_PTA		156
+#elif defined(CONFIG_66MHz)
+#define CONFIG_SYS_MAMR_PTA		129
+#else		/*   50 MHz */
+#define CONFIG_SYS_MAMR_PTA		 98
+#endif	/*CONFIG_??MHz */
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ */
+#define CONFIG_SYS_MPTPR 0x400
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CONFIG_SYS_MAMR_8COL 0x68802114
+/* 9 column SDRAM */
+#define CONFIG_SYS_MAMR_9COL 0x68904114
+
+/*
+ * Chip Selects
+ */
+#define CONFIG_SYS_OR0
+#define CONFIG_SYS_BR0
+
+#define CONFIG_SYS_OR1_8COL 0xFF000A00
+#define CONFIG_SYS_BR1_8COL 0x00000081
+#define CONFIG_SYS_OR2_8COL 0xFE000A00
+#define CONFIG_SYS_BR2_8COL 0x01000081
+#define CONFIG_SYS_OR3_8COL 0xFC000A00
+#define CONFIG_SYS_BR3_8COL 0x02000081
+
+#define CONFIG_SYS_OR1_9COL 0xFE000A00
+#define CONFIG_SYS_BR1_9COL 0x00000081
+#define CONFIG_SYS_OR2_9COL 0xFE000A00
+#define CONFIG_SYS_BR2_9COL 0x02000081
+#define CONFIG_SYS_OR3_9COL 0xFE000A00
+#define CONFIG_SYS_BR3_9COL 0x04000081
+
+#define CONFIG_SYS_OR4 0xFFFF8926
+#define CONFIG_SYS_BR4 0x90000401
+
+#define CONFIG_SYS_OR5 0xFFC007F0  /* EPSON: 4 MB  17 WS or externel TA */
+#define CONFIG_SYS_BR5 0x80080801  /* Start at 0x80080000 */
+
+#define LATCH_ADDR 0x90000200
+
+#define CONFIG_AUTOBOOT_KEYED		/* use key strings to stop autoboot */
+#define CONFIG_AUTOBOOT_STOP_STR	"."
+#define CONFIG_SILENT_CONSOLE		1
+#define CONFIG_SYS_DEVICE_NULLDEV	1       /* enble null device		*/
+#define CONFIG_VERSION_VARIABLE		1
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/KUP4X.h b/qemu/roms/u-boot/include/configs/KUP4X.h
new file mode 100644
index 000000000..47d16233a
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/KUP4X.h
@@ -0,0 +1,440 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ * Derived from ../tqm8xx/tqm8xx.c
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC859T		1	/* This is a MPC859T CPU	*/
+#define CONFIG_KUP4X		1	/* ...on a KUP4X module		*/
+
+#define	CONFIG_SYS_TEXT_BASE	0x40000000
+
+#define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		115200	/* console baudrate		*/
+
+#define CONFIG_BOOTDELAY	1	/* autoboot after 1 second	*/
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_SYS_8XX_FACT		8	/* Multiply by 8	*/
+#define CONFIG_SYS_8XX_XIN		16000000	/* 16 MHz in	*/
+
+
+#define MPC8XX_HZ ((CONFIG_SYS_8XX_XIN) * (CONFIG_SYS_8XX_FACT))
+
+/* should ALWAYS define this, measure_gclk in speed.c is unreliable */
+/* in general, we always know this for FADS+new ADS anyway */
+#define CONFIG_8xx_GCLK_FREQ	 MPC8XX_HZ
+
+
+#undef	CONFIG_BOOTARGS
+
+
+#define CONFIG_EXTRA_ENV_SETTINGS						\
+"slot_a_boot=setenv bootargs root=/dev/hda2 ip=off;"				\
+  "run addhw;diskboot 200000 0:1;bootm 200000\0"				\
+"usb_boot=setenv bootargs root=/dev/sda2 ip=off;				\
+ run addhw; sleep 2; usb reset; usb scan; usbboot 200000 0:1;			\
+ usb stop; bootm 200000\0"							\
+"nfs_boot=dhcp;run nfsargs addip addhw;bootm 200000\0"				\
+"panic_boot=echo No Bootdevice !!! reset\0"					\
+"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0"	\
+"ramargs=setenv bootargs root=/dev/ram rw\0"					\
+"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}"	\
+ ":${netmask}:${hostname}:${netdev}:off\0"					\
+"addhw=setenv bootargs ${bootargs} hw=${hw} key1=${key1} panic=1\0"		\
+"netdev=eth0\0"									\
+"silent=1\0"									\
+"load=tftp 200000 bootloader-4x.bitmap;tftp 100000 bootloader-4x.bin\0"		\
+"update=protect off 1:0-5;era 1:0-5;cp.b 100000 40000000 ${filesize};"		\
+ "cp.b 200000 40040000 14000\0"
+
+#define CONFIG_BOOTCOMMAND  \
+    "run usb_boot;run slot_a_boot;run nfs_boot;run panic_boot"
+
+
+#define CONFIG_MISC_INIT_R	1
+#define CONFIG_MISC_INIT_F	1
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE	/* don't allow baudrate change	*/
+
+#define	CONFIG_WATCHDOG		1	/* watchdog enabled		*/
+
+#define CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+/*
+ * enable I2C and select the hardware/software driver
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
+
+#ifdef CONFIG_SYS_I2C_SOFT
+#define CONFIG_SYS_I2C_SOFT_SPEED	93000	/* 93 kHz is supposed to work */
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
+
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PB_SCL		0x00000020	/* PB 26 */
+#define PB_SDA		0x00000010	/* PB 27 */
+
+#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
+#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
+#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
+#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
+#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
+#define I2C_DELAY	udelay(2)	/* 1/4 I2C clock duration */
+#endif	/* CONFIG_SYS_I2C_SOFT */
+
+
+/*-----------------------------------------------------------------------
+ * I2C Configuration
+ */
+
+#define CONFIG_SYS_I2C_PICIO_ADDR	0x21	/* PCF8574 IO Expander	*/
+#define CONFIG_SYS_I2C_RTC_ADDR	0x51	/* PCF8563 RTC			*/
+
+
+/* List of I2C addresses to be verified by POST */
+
+#define CONFIG_SYS_POST_I2C_ADDRS	{CONFIG_SYS_I2C_PICIO_ADDR,	\
+					 CONFIG_SYS_I2C_RTC_ADDR,	\
+					}
+
+
+#define CONFIG_RTC_PCF8563		/* use Philips PCF8563 RTC	*/
+
+#define CONFIG_SYS_DISCOVER_PHY
+#define CONFIG_MII
+
+#undef CONFIG_KUP4K_LOGO
+
+/* Define to allow the user to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+
+/* POST support */
+#define CONFIG_POST		(CONFIG_SYS_POST_CPU	   | \
+				 CONFIG_SYS_POST_RTC	   | \
+				 CONFIG_SYS_POST_I2C)
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_USB
+
+#ifdef CONFIG_POST
+    #define CONFIG_CMD_DIAG
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x000400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x003C00000	/* 4 ... 60 MB in DRAM	*/
+#define CONFIG_SYS_LOAD_ADDR		0x200000	/* default load address */
+
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 115200 }
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET 1
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	19	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_OFFSET		0x40000 /*   Offset   of Environment Sector	*/
+#define CONFIG_ENV_SIZE		0x1000	/* Total Size of Environment Sector	*/
+#define CONFIG_ENV_SECT_SIZE	0x10000
+
+/* Address and size of Redundant Environment Sector	*/
+#if 0
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+#endif
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#if 1
+#define CONFIG_SYS_HWINFO_OFFSET	0x000F0000	/* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE		0x00000100	/* size   of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC	0x4B26500D	/* 'K&P<CR>' */
+#endif
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if 0 && defined(CONFIG_WATCHDOG)       /* KUP uses external TPS3705 WD */
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
+
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register	15-30
+ *-----------------------------------------------------------------------
+ * set the PLL, the low-power modes and the reset control (15-29)
+ */
+#define CONFIG_SYS_PLPRCR	((CONFIG_SYS_8XX_FACT << PLPRCR_MFI_SHIFT) |	\
+				PLPRCR_SPLSS | PLPRCR_TEXPS)
+
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF00
+#define CONFIG_SYS_SCCR	(SCCR_TBS | SCCR_EBDF01 |  \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+
+/* KUP4K use both slots, SLOT_A as "primary". */
+#define CONFIG_PCMCIA_SLOT_A 1
+
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
+
+#define PCMCIA_SOCKETS_NO 1
+#define PCMCIA_MEM_WIN_NO 8
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_IDE_PREINIT	1	/* Use preinit IDE hook */
+#define CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card Adapter */
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
+#define CONFIG_IDE_LED			1   /* LED   for ide supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CONFIG_SYS_IDE_MAXBUS		1
+#define CONFIG_SYS_IDE_MAXDEVICE	2
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_IDE1_OFFSET	(4 * CONFIG_SYS_PCMCIA_MEM_SIZE)
+
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
+
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_DER 0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+				 OR_SCY_2_CLK | OR_EHTR | OR_BI)
+
+#define CONFIG_SYS_OR0_REMAP \
+		(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM \
+		(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM \
+		((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
+
+
+#define CONFIG_SYS_MPTPR 0x400
+
+/*
+ * MAMR settings for SDRAM
+ */
+#define CONFIG_SYS_MAMR 0x80802114
+
+
+/*
+ * Chip Selects
+ */
+
+#define CONFIG_SYS_OR4 0xFFFF8926
+#define CONFIG_SYS_BR4 0x90000401
+
+#define LATCH_ADDR 0x90000200
+
+#define CONFIG_AUTOBOOT_KEYED		/* use key strings to stop autoboot	*/
+
+#define CONFIG_AUTOBOOT_STOP_STR	"."	/* easy to stop for now		*/
+#define CONFIG_SILENT_CONSOLE	1
+
+#define CONFIG_USB_STORAGE	1
+#define CONFIG_USB_SL811HS	1
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/M5208EVBE.h b/qemu/roms/u-boot/include/configs/M5208EVBE.h
new file mode 100644
index 000000000..66303773c
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/M5208EVBE.h
@@ -0,0 +1,215 @@
+/*
+ * Configuation settings for the Freescale MCF5208EVBe.
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _M5208EVBE_H
+#define _M5208EVBE_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MCF520x		/* define processor family */
+#define CONFIG_M5208		/* define processor type */
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT		(0)
+#define CONFIG_BAUDRATE			115200
+
+#undef CONFIG_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT		5000
+
+/* Command line configuration */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#undef CONFIG_CMD_I2C
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_MII		1
+#	define CONFIG_MII_INIT		1
+#	define CONFIG_SYS_DISCOVER_PHY
+#	define CONFIG_SYS_RX_ETH_BUFFER	8
+#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#	define CONFIG_HAS_ETH1
+
+#	define CONFIG_SYS_FEC0_PINMUX	0
+#	define CONFIG_SYS_FEC0_MIIBASE	CONFIG_SYS_FEC0_IOBASE
+#	define MCFFEC_TOUT_LOOP		50000
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+#	ifndef CONFIG_SYS_DISCOVER_PHY
+#		define FECDUPLEX	FULL
+#		define FECSPEED		_100BASET
+#	else
+#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#		endif
+#	endif			/* CONFIG_SYS_DISCOVER_PHY */
+#endif
+
+/* Timer */
+#define CONFIG_MCFTMR
+#undef CONFIG_MCFPIT
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	80000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x58000
+#define CONFIG_SYS_IMMR			CONFIG_SYS_MBAR
+
+#define CONFIG_BOOTDELAY		1	/* autoboot after 5 seconds */
+#define CONFIG_UDP_CHECKSUM
+
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_ETHADDR	00:e0:0c:bc:e5:60
+#	define CONFIG_IPADDR	192.162.1.2
+#	define CONFIG_NETMASK	255.255.255.0
+#	define CONFIG_SERVERIP	192.162.1.1
+#	define CONFIG_GATEWAYIP	192.162.1.1
+#	define CONFIG_OVERWRITE_ETHADDR_ONCE
+#endif				/* CONFIG_MCFFEC */
+
+#define CONFIG_HOSTNAME		M5208EVBe
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"netdev=eth0\0"				\
+	"loadaddr=40010000\0"			\
+	"u-boot=u-boot.bin\0"			\
+	"load=tftp ${loadaddr) ${u-boot}\0"	\
+	"upd=run load; run prog\0"		\
+	"prog=prot off 0 3ffff;"		\
+	"era 0 3ffff;"				\
+	"cp.b ${loadaddr} 0 ${filesize};"	\
+	"save\0"				\
+	""
+
+#define CONFIG_PRAM		512	/* 512 KB */
+#define CONFIG_SYS_PROMPT	"-> "
+#define CONFIG_SYS_LONGHELP	/* undef to save memory */
+
+#ifdef CONFIG_CMD_KGDB
+#	define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
+#else
+#	define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
+#endif
+
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of cmd args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Arg Buf Sz */
+#define CONFIG_SYS_LOAD_ADDR	0x40010000
+
+#define CONFIG_SYS_CLK		166666666	/* CPU Core Clock */
+#define CONFIG_SYS_PLL_ODR	0x36
+#define CONFIG_SYS_PLL_FDR	0x7D
+
+#define CONFIG_SYS_MBAR		0xFC000000
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/* Definitions for initial stack pointer and data area (in DPRAM) */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
+#define CONFIG_SYS_INIT_RAM_SIZE		0x4000	/* Size of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_CTRL	0x221
+#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CONFIG_SYS_SDRAM_SIZE		32	/* SDRAM size in MB */
+#define CONFIG_SYS_SDRAM_CFG1		0x43711630
+#define CONFIG_SYS_SDRAM_CFG2		0x56670000
+#define CONFIG_SYS_SDRAM_CTRL		0xE1002000
+#define CONFIG_SYS_SDRAM_EMOD		0x80010000
+#define CONFIG_SYS_SDRAM_MODE		0x00CD0000
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
+#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
+
+#define CONFIG_SYS_MONITOR_BASE		(CONFIG_SYS_FLASH_BASE + 0x400)
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)
+
+/* FLASH organization */
+#define CONFIG_SYS_FLASH_CFI
+#ifdef CONFIG_SYS_FLASH_CFI
+#	define CONFIG_FLASH_CFI_DRIVER		1
+#	define CONFIG_SYS_FLASH_SIZE		0x800000	/* Max size that the board might have */
+#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#	define CONFIG_SYS_MAX_FLASH_SECT	254	/* max number of sectors on one chip */
+#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
+#endif
+
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
+
+/*
+ * Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#define CONFIG_ENV_OFFSET		0x2000
+#define CONFIG_ENV_SIZE			0x1000
+#define CONFIG_ENV_SECT_SIZE		0x2000
+#define CONFIG_ENV_IS_IN_FLASH		1
+
+/* Cache Configuration */
+#define CONFIG_SYS_CACHELINE_SIZE	16
+
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
+					 CF_CACR_DISD | CF_CACR_INVI | \
+					 CF_CACR_CEIB | CF_CACR_DCM | \
+					 CF_CACR_EUSP)
+
+/* Chipselect bank definitions */
+/*
+ * CS0 - NOR Flash
+ * CS1 - Available
+ * CS2 - Available
+ * CS3 - Available
+ * CS4 - Available
+ * CS5 - Available
+ */
+#define CONFIG_SYS_CS0_BASE		0
+#define CONFIG_SYS_CS0_MASK		0x007F0001
+#define CONFIG_SYS_CS0_CTRL		0x00001FA0
+
+#endif				/* _M5208EVBE_H */
diff --git a/qemu/roms/u-boot/include/configs/M52277EVB.h b/qemu/roms/u-boot/include/configs/M52277EVB.h
new file mode 100644
index 000000000..cde730595
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/M52277EVB.h
@@ -0,0 +1,322 @@
+/*
+ * Configuation settings for the Freescale MCF52277 EVB board.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _M52277EVB_H
+#define _M52277EVB_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MCF5227x		/* define processor family */
+#define CONFIG_M52277		/* define processor type */
+#define CONFIG_M52277EVB	/* M52277EVB board */
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT		(0)
+#define CONFIG_BAUDRATE			115200
+
+#undef CONFIG_WATCHDOG
+
+#define CONFIG_TIMESTAMP	/* Print image info with timestamp */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/* Command line configuration */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#define CONFIG_CMD_REGINFO
+#undef CONFIG_CMD_USB
+#undef CONFIG_CMD_BMP
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+
+#define CONFIG_HOSTNAME			M52277EVB
+#define CONFIG_SYS_UBOOT_END		0x3FFFF
+#define	CONFIG_SYS_LOAD_ADDR2		0x40010007
+#ifdef CONFIG_SYS_STMICRO_BOOT
+/* ST Micro serial flash */
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
+	"loadaddr=0x40010000\0"			\
+	"uboot=u-boot.bin\0"			\
+	"load=loadb ${loadaddr} ${baudrate};"	\
+	"loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0"	\
+	"upd=run load; run prog\0"		\
+	"prog=sf probe 0:2 10000 1;"		\
+	"sf erase 0 30000;"			\
+	"sf write ${loadaddr} 0 30000;"		\
+	"save\0"				\
+	""
+#endif
+#ifdef CONFIG_SYS_SPANSION_BOOT
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
+	"loadaddr=0x40010000\0"			\
+	"uboot=u-boot.bin\0"			\
+	"load=loadb ${loadaddr} ${baudrate}\0"	\
+	"upd=run load; run prog\0"		\
+	"prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE)	\
+	" " __stringify(CONFIG_SYS_UBOOT_END) ";"		\
+	"era " __stringify(CONFIG_SYS_FLASH_BASE) " "		\
+	__stringify(CONFIG_SYS_UBOOT_END) ";"			\
+	"cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE)	\
+	" ${filesize}; save\0"			\
+	"updsbf=run loadsbf; run progsbf\0"	\
+	"loadsbf=loadb ${loadaddr} ${baudrate};"	\
+	"loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0"	\
+	"progsbf=sf probe 0:2 10000 1;"		\
+	"sf erase 0 30000;"			\
+	"sf write ${loadaddr} 0 30000;"		\
+	""
+#endif
+
+#define CONFIG_BOOTDELAY		3	/* autoboot after 3 seconds */
+/* LCD */
+#ifdef CONFIG_CMD_BMP
+#define CONFIG_LCD
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_LCD_LOGO
+#define CONFIG_SHARP_LQ035Q7DH06
+#endif
+
+/* USB */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_STORAGE
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION
+#define CONFIG_ISO_PARTITION
+#define CONFIG_SYS_USB_EHCI_REGS_BASE	0xFC0B0000
+#define CONFIG_SYS_USB_EHCI_CPU_INIT
+#endif
+
+/* Realtime clock */
+#define CONFIG_MCFRTC
+#undef RTC_DEBUG
+#define CONFIG_SYS_RTC_OSCILLATOR	(32 * CONFIG_SYS_HZ)
+
+/* Timer */
+#define CONFIG_MCFTMR
+#undef CONFIG_MCFPIT
+
+/* I2c */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	80000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x58000
+#define CONFIG_SYS_IMMR			CONFIG_SYS_MBAR
+
+/* DSPI and Serial Flash */
+#define CONFIG_CF_SPI
+#define CONFIG_CF_DSPI
+#define CONFIG_HARD_SPI
+#define CONFIG_SYS_SBFHDR_SIZE		0x7
+#ifdef CONFIG_CMD_SPI
+#	define CONFIG_SYS_DSPI_CS2
+#	define CONFIG_SPI_FLASH
+#	define CONFIG_SPI_FLASH_STMICRO
+
+#	define CONFIG_SYS_DSPI_CTAR0	(DSPI_CTAR_TRSZ(7) | \
+					 DSPI_CTAR_PCSSCK_1CLK | \
+					 DSPI_CTAR_PASC(0) | \
+					 DSPI_CTAR_PDT(0) | \
+					 DSPI_CTAR_CSSCK(0) | \
+					 DSPI_CTAR_ASC(0) | \
+					 DSPI_CTAR_DT(1))
+#endif
+
+/* Input, PCI, Flexbus, and VCO */
+#define CONFIG_EXTRA_CLOCK
+
+#define CONFIG_SYS_INPUT_CLKSRC	16000000
+
+#define CONFIG_PRAM		2048	/* 2048 KB */
+
+#define CONFIG_SYS_PROMPT	"-> "
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
+
+#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_SDRAM_BASE + 0x10000)
+
+#define CONFIG_SYS_MBAR		0xFC000000
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
+#define CONFIG_SYS_INIT_RAM_SIZE		0x8000	/* Size of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_CTRL	0x221
+#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
+#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 32)
+#define CONFIG_SYS_SBFHDR_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - 32)
+
+/*
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CONFIG_SYS_SDRAM_SIZE		64	/* SDRAM size in MB */
+#define CONFIG_SYS_SDRAM_CFG1		0x43711630
+#define CONFIG_SYS_SDRAM_CFG2		0x56670000
+#define CONFIG_SYS_SDRAM_CTRL		0xE1092000
+#define CONFIG_SYS_SDRAM_EMOD		0x81810000
+#define CONFIG_SYS_SDRAM_MODE		0x00CD0000
+#define CONFIG_SYS_SDRAM_DRV_STRENGTH	0x00
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
+#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
+
+#ifdef CONFIG_CF_SBF
+#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_TEXT_BASE + 0x400)
+#else
+#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
+#endif
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
+
+/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)
+
+/*
+ * Configuration for environment
+ * Environment is not embedded in u-boot. First time runing may have env
+ * crc error warning if there is no correct environment on the flash.
+ */
+#ifdef CONFIG_CF_SBF
+#	define CONFIG_ENV_IS_IN_SPI_FLASH
+#	define CONFIG_ENV_SPI_CS	2
+#else
+#	define CONFIG_ENV_IS_IN_FLASH	1
+#endif
+#define CONFIG_ENV_OVERWRITE		1
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#ifdef CONFIG_SYS_STMICRO_BOOT
+#	define CONFIG_SYS_FLASH_BASE	CONFIG_SYS_CS0_BASE
+#	define CONFIG_SYS_FLASH0_BASE	CONFIG_SYS_CS0_BASE
+#	define CONFIG_ENV_OFFSET	0x30000
+#	define CONFIG_ENV_SIZE		0x1000
+#	define CONFIG_ENV_SECT_SIZE	0x10000
+#endif
+#ifdef CONFIG_SYS_SPANSION_BOOT
+#	define CONFIG_SYS_FLASH_BASE	CONFIG_SYS_CS0_BASE
+#	define CONFIG_SYS_FLASH0_BASE	CONFIG_SYS_CS0_BASE
+#	define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x40000)
+#	define CONFIG_ENV_SIZE		0x1000
+#	define CONFIG_ENV_SECT_SIZE	0x8000
+#endif
+
+#define CONFIG_SYS_FLASH_CFI
+#ifdef CONFIG_SYS_FLASH_CFI
+#	define CONFIG_FLASH_CFI_DRIVER	1
+#	define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+#	define CONFIG_FLASH_SPANSION_S29WS_N	1
+#	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
+#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
+#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
+#	define CONFIG_SYS_FLASH_CHECKSUM
+#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_CS0_BASE }
+#endif
+
+/*
+ * This is setting for JFFS2 support in u-boot.
+ * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
+ */
+#ifdef CONFIG_CMD_JFFS2
+#	define CONFIG_JFFS2_DEV		"nor0"
+#	define CONFIG_JFFS2_PART_SIZE	(0x01000000 - 0x40000)
+#	define CONFIG_JFFS2_PART_OFFSET	(CONFIG_SYS_FLASH0_BASE + 0x40000)
+#endif
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16
+
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
+					 CF_CACR_DISD | CF_CACR_INVI | \
+					 CF_CACR_CEIB | CF_CACR_DCM | \
+					 CF_CACR_EUSP)
+
+/*-----------------------------------------------------------------------
+ * Memory bank definitions
+ */
+/*
+ * CS0 - NOR Flash
+ * CS1 - Available
+ * CS2 - Available
+ * CS3 - Available
+ * CS4 - Available
+ * CS5 - Available
+ */
+
+#ifdef CONFIG_CF_SBF
+#define CONFIG_SYS_CS0_BASE		0x04000000
+#define CONFIG_SYS_CS0_MASK		0x00FF0001
+#define CONFIG_SYS_CS0_CTRL		0x00001FA0
+#else
+#define CONFIG_SYS_CS0_BASE		0x00000000
+#define CONFIG_SYS_CS0_MASK		0x00FF0001
+#define CONFIG_SYS_CS0_CTRL		0x00001FA0
+#endif
+
+#endif				/* _M52277EVB_H */
diff --git a/qemu/roms/u-boot/include/configs/M5235EVB.h b/qemu/roms/u-boot/include/configs/M5235EVB.h
new file mode 100644
index 000000000..0f6e2f72c
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/M5235EVB.h
@@ -0,0 +1,254 @@
+/*
+ * Configuation settings for the Freescale MCF5329 FireEngine board.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _M5235EVB_H
+#define _M5235EVB_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MCF523x		/* define processor family */
+#define CONFIG_M5235		/* define processor type */
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT		(0)
+#define CONFIG_BAUDRATE		115200
+
+#undef CONFIG_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT	5000	/* timeout in milliseconds, max timeout is 6.71sec */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/* Command line configuration */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_MII		1
+#	define CONFIG_MII_INIT		1
+#	define CONFIG_SYS_DISCOVER_PHY
+#	define CONFIG_SYS_RX_ETH_BUFFER	8
+#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+
+#	define CONFIG_SYS_FEC0_PINMUX		0
+#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
+#	define MCFFEC_TOUT_LOOP		50000
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+#	ifndef CONFIG_SYS_DISCOVER_PHY
+#		define FECDUPLEX	FULL
+#		define FECSPEED		_100BASET
+#	else
+#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#		endif
+#	endif			/* CONFIG_SYS_DISCOVER_PHY */
+#endif
+
+/* Timer */
+#define CONFIG_MCFTMR
+#undef CONFIG_MCFPIT
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_i2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	80000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x00000300
+#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
+#define CONFIG_SYS_I2C_PINMUX_REG	(gpio->par_qspi)
+#define CONFIG_SYS_I2C_PINMUX_CLR	~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
+#define CONFIG_SYS_I2C_PINMUX_SET	(GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#define CONFIG_BOOTDELAY	1	/* autoboot after 5 seconds */
+#define CONFIG_BOOTFILE		"u-boot.bin"
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_ETHADDR	00:e0:0c:bc:e5:60
+#	define CONFIG_IPADDR	192.162.1.2
+#	define CONFIG_NETMASK	255.255.255.0
+#	define CONFIG_SERVERIP	192.162.1.1
+#	define CONFIG_GATEWAYIP	192.162.1.1
+#	define CONFIG_OVERWRITE_ETHADDR_ONCE
+#endif				/* FEC_ENET */
+
+#define CONFIG_HOSTNAME		M5235EVB
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"netdev=eth0\0"				\
+	"loadaddr=10000\0"			\
+	"u-boot=u-boot.bin\0"			\
+	"load=tftp ${loadaddr) ${u-boot}\0"	\
+	"upd=run load; run prog\0"		\
+	"prog=prot off ffe00000 ffe3ffff;"	\
+	"era ffe00000 ffe3ffff;"		\
+	"cp.b ${loadaddr} ffe00000 ${filesize};"\
+	"save\0"				\
+	""
+
+#define CONFIG_PRAM		512	/* 512 KB */
+#define CONFIG_SYS_PROMPT		"-> "
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+
+#if defined(CONFIG_KGDB)
+#	define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
+#else
+#	define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+#endif
+
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE+0x20000)
+
+#define CONFIG_SYS_CLK			75000000
+#define CONFIG_SYS_CPU_CLK		CONFIG_SYS_CLK * 2
+
+#define CONFIG_SYS_MBAR		0x40000000
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x10000	/* Size of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_CTRL	0x21
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_SIZE		16	/* SDRAM size in MB */
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
+#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
+
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_FLASH_CFI
+#ifdef CONFIG_SYS_FLASH_CFI
+#	define CONFIG_FLASH_CFI_DRIVER	1
+#	define CONFIG_SYS_FLASH_SIZE		0x800000	/* Max size that the board might have */
+#ifdef NORFLASH_PS32BIT
+#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_32BIT
+#else
+#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#endif
+#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
+#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
+#endif
+
+#define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CS0_BASE)
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#ifdef NORFLASH_PS32BIT
+#	define CONFIG_ENV_OFFSET		(0x8000)
+#	define CONFIG_ENV_SIZE		0x4000
+#	define CONFIG_ENV_SECT_SIZE	0x4000
+#else
+#	define CONFIG_ENV_OFFSET		(0x4000)
+#	define CONFIG_ENV_SIZE		0x2000
+#	define CONFIG_ENV_SECT_SIZE	0x2000
+#endif
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16
+
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_DISD | \
+					 CF_CACR_CEIB | CF_CACR_DCM | \
+					 CF_CACR_EUSP)
+
+/*-----------------------------------------------------------------------
+ * Chipselect bank definitions
+ */
+/*
+ * CS0 - NOR Flash 1, 2, 4, or 8MB
+ * CS1 - Available
+ * CS2 - Available
+ * CS3 - Available
+ * CS4 - Available
+ * CS5 - Available
+ * CS6 - Available
+ * CS7 - Available
+ */
+#ifdef NORFLASH_PS32BIT
+#	define CONFIG_SYS_CS0_BASE	0xFFC00000
+#	define CONFIG_SYS_CS0_MASK	0x003f0001
+#	define CONFIG_SYS_CS0_CTRL	0x00001D00
+#else
+#	define CONFIG_SYS_CS0_BASE	0xFFE00000
+#	define CONFIG_SYS_CS0_MASK	0x001f0001
+#	define CONFIG_SYS_CS0_CTRL	0x00001D80
+#endif
+
+#endif				/* _M5329EVB_H */
diff --git a/qemu/roms/u-boot/include/configs/M5249EVB.h b/qemu/roms/u-boot/include/configs/M5249EVB.h
new file mode 100644
index 000000000..ae4fe45fc
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/M5249EVB.h
@@ -0,0 +1,188 @@
+/*
+ * Configuation settings for the esd TASREG board.
+ *
+ * (C) Copyright 2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _M5249EVB_H
+#define _M5249EVB_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MCF52x2			/* define processor family */
+#define CONFIG_M5249			/* define processor type */
+
+#define CONFIG_MCFTMR
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT		(0)
+#define CONFIG_BAUDRATE		115200
+
+#undef  CONFIG_WATCHDOG
+
+#undef CONFIG_MONITOR_IS_IN_RAM		/* no pre-loader required!!! ;-) */
+
+/*
+ * BOOTP options
+ */
+#undef CONFIG_BOOTP_BOOTFILESIZE
+#undef CONFIG_BOOTP_BOOTPATH
+#undef CONFIG_BOOTP_GATEWAY
+#undef CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_CACHE
+#undef CONFIG_CMD_NET
+
+#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup	*/
+#define CONFIG_AUTO_COMPLETE	1	/* add autocompletion support	*/
+#define CONFIG_LOOPW		1	/* enable loopw command	*/
+#define CONFIG_MX_CYCLIC	1	/* enable mdc/mwc commands	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x200000	/* default load address */
+
+#define CONFIG_SYS_MEMTEST_START	0x400
+#define CONFIG_SYS_MEMTEST_END		0x380000
+
+/*
+ * Clock configuration: enable only one of the following options
+ */
+
+#undef  CONFIG_SYS_PLL_BYPASS				/* bypass PLL for test purpose */
+#define CONFIG_SYS_FAST_CLK		1		/* MCF5249 can run at 140MHz   */
+#define	CONFIG_SYS_CLK			132025600	/* MCF5249 can run at 140MHz   */
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+#define CONFIG_SYS_MBAR		0x10000000	/* Register Base Addrs */
+#define	CONFIG_SYS_MBAR2		0x80000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in internal SRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_OFFSET		0x4000	/* Address of Environment Sector*/
+#define CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
+#define CONFIG_ENV_SECT_SIZE	0x2000 /* see README - env sector total size	*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_SIZE		16		/* SDRAM size in MB */
+#define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CS0_BASE)
+
+#if 0 /* test-only */
+#define CONFIG_PRAM		512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
+#endif
+
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
+
+#define CONFIG_SYS_MONITOR_LEN		0x20000
+#define CONFIG_SYS_MALLOC_LEN		(1 * 1024*1024)	/* Reserve 1 MB for malloc()	*/
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_FLASH_CFI
+#ifdef CONFIG_SYS_FLASH_CFI
+
+#	define CONFIG_FLASH_CFI_DRIVER	1
+#	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
+#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
+#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
+#	define CONFIG_SYS_FLASH_CHECKSUM
+#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#endif
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16
+
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_DCM)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_FLASH_BASE | \
+					 CF_ADDRMASK(2) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ACR1		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CEIB | \
+					 CF_CACR_DBWE)
+
+/*-----------------------------------------------------------------------
+ * Memory bank definitions
+ */
+
+/* CS0 - AMD Flash, address 0xffc00000 */
+#define	CONFIG_SYS_CS0_BASE		0xffe00000
+#define	CONFIG_SYS_CS0_CTRL		0x00001980	/* WS=0110, AA=1, PS=10         */
+/** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/
+#define	CONFIG_SYS_CS0_MASK		0x003f0021	/* 4MB, AA=0, WP=0, C/I=1, V=1  */
+
+/* CS1 - FPGA, address 0xe0000000 */
+#define	CONFIG_SYS_CS1_BASE		0xe0000000
+#define	CONFIG_SYS_CS1_CTRL		0x00000d80	/* WS=0011, AA=1, PS=10         */
+#define	CONFIG_SYS_CS1_MASK		0x00010001	/* 128kB, AA=0, WP=0, C/I=0, V=1*/
+
+/*-----------------------------------------------------------------------
+ * Port configuration
+ */
+#define	CONFIG_SYS_GPIO_FUNC		0x00000008	/* Set gpio pins: none          */
+#define	CONFIG_SYS_GPIO1_FUNC		0x00df00f0	/* 36-39(SWITCH),48-52(FPGAs),54*/
+#define	CONFIG_SYS_GPIO_EN		0x00000008	/* Set gpio output enable       */
+#define	CONFIG_SYS_GPIO1_EN		0x00c70000	/* Set gpio output enable       */
+#define	CONFIG_SYS_GPIO_OUT		0x00000008	/* Set outputs to default state */
+#define	CONFIG_SYS_GPIO1_OUT		0x00c70000	/* Set outputs to default state */
+#define CONFIG_SYS_GPIO1_LED		0x00400000	/* user led                     */
+
+#endif	/* M5249 */
diff --git a/qemu/roms/u-boot/include/configs/M5253DEMO.h b/qemu/roms/u-boot/include/configs/M5253DEMO.h
new file mode 100644
index 000000000..3a1cbcae9
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/M5253DEMO.h
@@ -0,0 +1,244 @@
+/* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Hayden Fraser (Hayden.Fraser@freescale.com)
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _M5253DEMO_H
+#define _M5253DEMO_H
+
+#define CONFIG_MCF52x2		/* define processor family */
+#define CONFIG_M5253		/* define processor type */
+#define CONFIG_M5253DEMO	/* define board type */
+
+#define CONFIG_MCFTMR
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT		(0)
+#define CONFIG_BAUDRATE		115200
+
+#undef CONFIG_WATCHDOG		/* disable watchdog */
+
+#define CONFIG_BOOTDELAY	5
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#ifdef CONFIG_MONITOR_IS_IN_RAM
+#	define CONFIG_ENV_OFFSET		0x4000
+#	define CONFIG_ENV_SECT_SIZE	0x1000
+#	define CONFIG_ENV_IS_IN_FLASH	1
+#else
+#	define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x4000)
+#	define CONFIG_ENV_SECT_SIZE	0x1000
+#	define CONFIG_ENV_IS_IN_FLASH	1
+#endif
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_PING
+
+#ifdef CONFIG_CMD_IDE
+/* ATA */
+#	define CONFIG_DOS_PARTITION
+#	define CONFIG_MAC_PARTITION
+#	define CONFIG_IDE_RESET		1
+#	define CONFIG_IDE_PREINIT	1
+#	define CONFIG_ATAPI
+#	undef CONFIG_LBA48
+
+#	define CONFIG_SYS_IDE_MAXBUS		1
+#	define CONFIG_SYS_IDE_MAXDEVICE	2
+
+#	define CONFIG_SYS_ATA_BASE_ADDR	(CONFIG_SYS_MBAR2 + 0x800)
+#	define CONFIG_SYS_ATA_IDE0_OFFSET	0
+
+#	define CONFIG_SYS_ATA_DATA_OFFSET	0xA0	/* Offset for data I/O */
+#	define CONFIG_SYS_ATA_REG_OFFSET	0xA0	/* Offset for normal register accesses */
+#	define CONFIG_SYS_ATA_ALT_OFFSET	0xC0	/* Offset for alternate registers */
+#	define CONFIG_SYS_ATA_STRIDE		4	/* Interval between registers */
+#endif
+
+#define CONFIG_DRIVER_DM9000
+#ifdef CONFIG_DRIVER_DM9000
+#	define CONFIG_DM9000_BASE	(CONFIG_SYS_CS1_BASE | 0x300)
+#	define DM9000_IO		CONFIG_DM9000_BASE
+#	define DM9000_DATA		(CONFIG_DM9000_BASE + 4)
+#	undef CONFIG_DM9000_DEBUG
+#	define CONFIG_DM9000_BYTE_SWAPPED
+
+#	define CONFIG_OVERWRITE_ETHADDR_ONCE
+
+#	define CONFIG_EXTRA_ENV_SETTINGS		\
+		"netdev=eth0\0"				\
+		"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
+		"loadaddr=10000\0"			\
+		"u-boot=u-boot.bin\0"			\
+		"load=tftp ${loadaddr) ${u-boot}\0"	\
+		"upd=run load; run prog\0"		\
+		"prog=prot off 0xff800000 0xff82ffff;"	\
+		"era 0xff800000 0xff82ffff;"		\
+		"cp.b ${loadaddr} 0xff800000 ${filesize};"	\
+		"save\0"				\
+		""
+#endif
+
+#define CONFIG_HOSTNAME		M5253DEMO
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	80000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x00000280
+#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
+#define CONFIG_SYS_I2C_PINMUX_REG	(*(u32 *) (CONFIG_SYS_MBAR+0x19C))
+#define CONFIG_SYS_I2C_PINMUX_CLR	(0xFFFFE7FF)
+#define CONFIG_SYS_I2C_PINMUX_SET	(0)
+
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+
+#if defined(CONFIG_CMD_KGDB)
+#	define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
+#else
+#	define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_LOAD_ADDR		0x00100000
+
+#define CONFIG_SYS_MEMTEST_START	0x400
+#define CONFIG_SYS_MEMTEST_END		0x380000
+
+#undef CONFIG_SYS_PLL_BYPASS		/* bypass PLL for test purpose */
+#define CONFIG_SYS_FAST_CLK
+#ifdef CONFIG_SYS_FAST_CLK
+#	define CONFIG_SYS_PLLCR	0x1243E054
+#	define CONFIG_SYS_CLK		140000000
+#else
+#	define CONFIG_SYS_PLLCR	0x135a4140
+#	define CONFIG_SYS_CLK		70000000
+#endif
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+#define CONFIG_SYS_MBAR		0x10000000	/* Register Base Addrs */
+#define CONFIG_SYS_MBAR2		0x80000000	/* Module Base Addrs 2 */
+
+/*
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x10000	/* Size of used area in internal SRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_SIZE		16	/* SDRAM size in MB */
+
+#ifdef CONFIG_MONITOR_IS_IN_RAM
+#	define CONFIG_SYS_MONITOR_BASE	0x20000
+#else
+#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN		0x40000
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
+#define CONFIG_SYS_BOOTPARAMS_LEN	(64*1024)
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)
+
+/* FLASH organization */
+#define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CS0_BASE)
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	2048	/* max number of sectors on one chip */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	1000
+
+#define FLASH_SST6401B		0x200
+#define SST_ID_xF6401B		0x236D236D
+
+#undef CONFIG_SYS_FLASH_CFI
+#ifdef CONFIG_SYS_FLASH_CFI
+/*
+ * Unable to use CFI driver, due to incompatible sector erase command by SST.
+ * Amd/Atmel use 0x30 for sector erase, SST use 0x50.
+ * 0x30 is block erase in SST
+ */
+#	define CONFIG_FLASH_CFI_DRIVER	1
+#	define CONFIG_SYS_FLASH_SIZE		0x800000
+#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#	define CONFIG_FLASH_CFI_LEGACY
+#else
+#	define CONFIG_SYS_SST_SECT		2048
+#	define CONFIG_SYS_SST_SECTSZ		0x1000
+#	define CONFIG_SYS_FLASH_WRITE_TOUT	500
+#endif
+
+/* Cache Configuration */
+#define CONFIG_SYS_CACHELINE_SIZE	16
+
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_DCM)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_FLASH_BASE | \
+					 CF_ADDRMASK(8) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ACR1		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CEIB | \
+					 CF_CACR_DBWE)
+
+/* Port configuration */
+#define CONFIG_SYS_FECI2C		0xF0
+
+#define CONFIG_SYS_CS0_BASE		0xFF800000
+#define CONFIG_SYS_CS0_MASK		0x007F0021
+#define CONFIG_SYS_CS0_CTRL		0x00001D80
+
+#define CONFIG_SYS_CS1_BASE		0xE0000000
+#define CONFIG_SYS_CS1_MASK		0x00000001
+#define CONFIG_SYS_CS1_CTRL		0x00003DD8
+
+/*-----------------------------------------------------------------------
+ * Port configuration
+ */
+#define CONFIG_SYS_GPIO_FUNC		0x00000008	/* Set gpio pins: none */
+#define CONFIG_SYS_GPIO1_FUNC		0x00df00f0	/* 36-39(SWITCH),48-52(FPGAs),54 */
+#define CONFIG_SYS_GPIO_EN		0x00000008	/* Set gpio output enable */
+#define CONFIG_SYS_GPIO1_EN		0x00c70000	/* Set gpio output enable */
+#define CONFIG_SYS_GPIO_OUT		0x00000008	/* Set outputs to default state */
+#define CONFIG_SYS_GPIO1_OUT		0x00c70000	/* Set outputs to default state */
+#define CONFIG_SYS_GPIO1_LED		0x00400000	/* user led */
+
+#endif				/* _M5253DEMO_H */
diff --git a/qemu/roms/u-boot/include/configs/M5253EVBE.h b/qemu/roms/u-boot/include/configs/M5253EVBE.h
new file mode 100644
index 000000000..fabfdb93d
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/M5253EVBE.h
@@ -0,0 +1,194 @@
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Hayden Fraser (Hayden.Fraser@freescale.com)
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _M5253EVBE_H
+#define _M5253EVBE_H
+
+#define CONFIG_MCF52x2		/* define processor family */
+#define CONFIG_M5253		/* define processor type */
+#define CONFIG_M5253EVBE	/* define board type */
+
+#define CONFIG_MCFTMR
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT		(0)
+#define CONFIG_BAUDRATE		115200
+
+#undef CONFIG_WATCHDOG		/* disable watchdog */
+
+#define CONFIG_BOOTDELAY	5
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#ifndef CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_ENV_OFFSET		0x4000
+#define CONFIG_ENV_SECT_SIZE	0x2000
+#define CONFIG_ENV_IS_IN_FLASH	1
+#else
+#define CONFIG_ENV_ADDR		0xffe04000
+#define CONFIG_ENV_SECT_SIZE	0x2000
+#define CONFIG_ENV_IS_IN_FLASH	1
+#endif
+
+/*
+ * BOOTP options
+ */
+#undef CONFIG_BOOTP_BOOTFILESIZE
+#undef CONFIG_BOOTP_BOOTPATH
+#undef CONFIG_BOOTP_GATEWAY
+#undef CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_CACHE
+#undef CONFIG_CMD_NET
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+
+/* ATA */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION
+#define CONFIG_IDE_RESET	1
+#define CONFIG_IDE_PREINIT	1
+#define CONFIG_ATAPI
+#undef CONFIG_LBA48
+
+#define CONFIG_SYS_IDE_MAXBUS		1
+#define CONFIG_SYS_IDE_MAXDEVICE	2
+
+#define CONFIG_SYS_ATA_BASE_ADDR	(CONFIG_SYS_MBAR2 + 0x800)
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0
+
+#define CONFIG_SYS_ATA_DATA_OFFSET	0xA0	/* Offset for data I/O */
+#define CONFIG_SYS_ATA_REG_OFFSET	0xA0	/* Offset for normal register accesses */
+#define CONFIG_SYS_ATA_ALT_OFFSET	0xC0	/* Offset for alternate registers */
+#define CONFIG_SYS_ATA_STRIDE		4	/* Interval between registers */
+
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_LOAD_ADDR		0x00100000
+
+#define CONFIG_SYS_MEMTEST_START	0x400
+#define CONFIG_SYS_MEMTEST_END		0x380000
+
+#undef CONFIG_SYS_PLL_BYPASS		/* bypass PLL for test purpose */
+#define CONFIG_SYS_FAST_CLK
+#ifdef CONFIG_SYS_FAST_CLK
+#	define CONFIG_SYS_PLLCR	0x1243E054
+#	define CONFIG_SYS_CLK		140000000
+#else
+#	define CONFIG_SYS_PLLCR	0x135a4140
+#	define CONFIG_SYS_CLK		70000000
+#endif
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+#define CONFIG_SYS_MBAR		0x10000000	/* Register Base Addrs */
+#define CONFIG_SYS_MBAR2		0x80000000	/* Module Base Addrs 2 */
+
+/*
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x10000	/* Size of used area in internal SRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_SIZE		8	/* SDRAM size in MB */
+
+#ifdef CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_SYS_MONITOR_BASE	0x20000
+#else
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN		0x40000
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
+#define CONFIG_SYS_BOOTPARAMS_LEN	(64*1024)
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)
+
+/* FLASH organization */
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	35	/* max number of sectors on one chip */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	1000
+
+#define CONFIG_SYS_FLASH_CFI		1
+#define CONFIG_FLASH_CFI_DRIVER	1
+#define CONFIG_SYS_FLASH_SIZE		0x200000
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+
+/* Cache Configuration */
+#define CONFIG_SYS_CACHELINE_SIZE	16
+
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_DCM)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_FLASH_BASE | \
+					 CF_ADDRMASK(2) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ACR1		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CEIB | \
+					 CF_CACR_DBWE)
+
+/* Port configuration */
+#define CONFIG_SYS_FECI2C		0xF0
+
+#define CONFIG_SYS_CS0_BASE		0xFFE00000
+#define CONFIG_SYS_CS0_MASK		0x001F0021
+#define CONFIG_SYS_CS0_CTRL		0x00001D80
+
+/*-----------------------------------------------------------------------
+ * Port configuration
+ */
+#define CONFIG_SYS_GPIO_FUNC		0x00000008	/* Set gpio pins: none */
+#define CONFIG_SYS_GPIO1_FUNC		0x00df00f0	/* 36-39(SWITCH),48-52(FPGAs),54 */
+#define CONFIG_SYS_GPIO_EN		0x00000008	/* Set gpio output enable */
+#define CONFIG_SYS_GPIO1_EN		0x00c70000	/* Set gpio output enable */
+#define CONFIG_SYS_GPIO_OUT		0x00000008	/* Set outputs to default state */
+#define CONFIG_SYS_GPIO1_OUT		0x00c70000	/* Set outputs to default state */
+#define CONFIG_SYS_GPIO1_LED		0x00400000	/* user led */
+
+#endif				/* _M5253EVB_H */
diff --git a/qemu/roms/u-boot/include/configs/M5272C3.h b/qemu/roms/u-boot/include/configs/M5272C3.h
new file mode 100644
index 000000000..4c8412655
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/M5272C3.h
@@ -0,0 +1,238 @@
+/*
+ * Configuation settings for the Motorola MC5272C3 board.
+ *
+ * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _M5272C3_H
+#define _M5272C3_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MCF52x2		/* define processor family */
+#define CONFIG_M5272		/* define processor type */
+
+#define CONFIG_MCFTMR
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT		(0)
+#define CONFIG_BAUDRATE		115200
+
+#undef CONFIG_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT 10000	/* timeout in milliseconds */
+
+#undef CONFIG_MONITOR_IS_IN_RAM	/* define if monitor is started from a pre-loader */
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#ifndef CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_ENV_OFFSET		0x4000
+#define CONFIG_ENV_SECT_SIZE	0x2000
+#define CONFIG_ENV_IS_IN_FLASH	1
+#else
+#define CONFIG_ENV_ADDR		0xffe04000
+#define CONFIG_ENV_SECT_SIZE	0x2000
+#define CONFIG_ENV_IS_IN_FLASH	1
+#endif
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_MEMORY
+
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_LOADB
+
+#define CONFIG_BOOTDELAY	5
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_MII		1
+#	define CONFIG_MII_INIT		1
+#	define CONFIG_SYS_DISCOVER_PHY
+#	define CONFIG_SYS_RX_ETH_BUFFER	8
+#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+
+#	define CONFIG_SYS_FEC0_PINMUX		0
+#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
+#	define MCFFEC_TOUT_LOOP		50000
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+#	ifndef CONFIG_SYS_DISCOVER_PHY
+#		define FECDUPLEX	FULL
+#		define FECSPEED		_100BASET
+#	else
+#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#		endif
+#	endif			/* CONFIG_SYS_DISCOVER_PHY */
+#endif
+
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_ETHADDR	00:e0:0c:bc:e5:60
+#	define CONFIG_IPADDR	192.162.1.2
+#	define CONFIG_NETMASK	255.255.255.0
+#	define CONFIG_SERVERIP	192.162.1.1
+#	define CONFIG_GATEWAYIP	192.162.1.1
+#	define CONFIG_OVERWRITE_ETHADDR_ONCE
+#endif				/* CONFIG_MCFFEC */
+
+#define CONFIG_HOSTNAME		M5272C3
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"netdev=eth0\0"				\
+	"loadaddr=10000\0"			\
+	"u-boot=u-boot.bin\0"			\
+	"load=tftp ${loadaddr) ${u-boot}\0"	\
+	"upd=run load; run prog\0"		\
+	"prog=prot off ffe00000 ffe3ffff;"	\
+	"era ffe00000 ffe3ffff;"		\
+	"cp.b ${loadaddr} ffe00000 ${filesize};"\
+	"save\0"				\
+	""
+
+#define CONFIG_SYS_PROMPT		"-> "
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size      */
+#else
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size      */
+#endif
+
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args   */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
+#define CONFIG_SYS_LOAD_ADDR		0x20000
+#define CONFIG_SYS_MEMTEST_START	0x400
+#define CONFIG_SYS_MEMTEST_END		0x380000
+#define CONFIG_SYS_CLK			66000000
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+#define CONFIG_SYS_MBAR		0x10000000	/* Register Base Addrs */
+#define CONFIG_SYS_SCR			0x0003
+#define CONFIG_SYS_SPR			0xffff
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in internal SRAM    */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_SIZE		4	/* SDRAM size in MB */
+#define CONFIG_SYS_FLASH_BASE		0xffe00000
+
+#ifdef	CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_SYS_MONITOR_BASE	0x20000
+#else
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN		0x20000
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+
+/*
+ * FLASH organization
+ */
+#define CONFIG_SYS_FLASH_CFI
+#ifdef CONFIG_SYS_FLASH_CFI
+#	define CONFIG_FLASH_CFI_DRIVER	1
+#	define CONFIG_SYS_FLASH_SIZE		0x800000	/* Max size that the board might have */
+#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
+#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16
+
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
+					 CF_CACR_DISD | CF_CACR_INVI | \
+					 CF_CACR_CEIB | CF_CACR_DCM | \
+					 CF_CACR_EUSP)
+
+/*-----------------------------------------------------------------------
+ * Memory bank definitions
+ */
+#define CONFIG_SYS_BR0_PRELIM		0xFFE00201
+#define CONFIG_SYS_OR0_PRELIM		0xFFE00014
+#define CONFIG_SYS_BR1_PRELIM		0
+#define CONFIG_SYS_OR1_PRELIM		0
+#define CONFIG_SYS_BR2_PRELIM		0x30000001
+#define CONFIG_SYS_OR2_PRELIM		0xFFF80000
+#define CONFIG_SYS_BR3_PRELIM		0
+#define CONFIG_SYS_OR3_PRELIM		0
+#define CONFIG_SYS_BR4_PRELIM		0
+#define CONFIG_SYS_OR4_PRELIM		0
+#define CONFIG_SYS_BR5_PRELIM		0
+#define CONFIG_SYS_OR5_PRELIM		0
+#define CONFIG_SYS_BR6_PRELIM		0
+#define CONFIG_SYS_OR6_PRELIM		0
+#define CONFIG_SYS_BR7_PRELIM		0x00000701
+#define CONFIG_SYS_OR7_PRELIM		0xFFC0007C
+
+/*-----------------------------------------------------------------------
+ * Port configuration
+ */
+#define CONFIG_SYS_PACNT		0x00000000
+#define CONFIG_SYS_PADDR		0x0000
+#define CONFIG_SYS_PADAT		0x0000
+#define CONFIG_SYS_PBCNT		0x55554155	/* Ethernet/UART configuration */
+#define CONFIG_SYS_PBDDR		0x0000
+#define CONFIG_SYS_PBDAT		0x0000
+#define CONFIG_SYS_PDCNT		0x00000000
+#endif				/* _M5272C3_H */
diff --git a/qemu/roms/u-boot/include/configs/M5275EVB.h b/qemu/roms/u-boot/include/configs/M5275EVB.h
new file mode 100644
index 000000000..4dddab7c1
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/M5275EVB.h
@@ -0,0 +1,232 @@
+/*
+ * Configuation settings for the Motorola MC5275EVB board.
+ *
+ * By Arthur Shipkowski <art@videon-central.com>
+ * Copyright (C) 2005 Videon Central, Inc.
+ *
+ * Based off of M5272C3 board code by Josef Baumgartner
+ * <josef.baumgartner@telex.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _M5275EVB_H
+#define _M5275EVB_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MCF52x2			/* define processor family */
+#define CONFIG_M5275			/* define processor type */
+#define CONFIG_M5275EVB			/* define board type */
+
+#define CONFIG_MCFTMR
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT		(0)
+#define CONFIG_BAUDRATE		115200
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#ifndef CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_ENV_OFFSET		0x4000
+#define CONFIG_ENV_SECT_SIZE	0x2000
+#define CONFIG_ENV_IS_IN_FLASH	1
+#else
+#define CONFIG_ENV_ADDR		0xffe04000
+#define CONFIG_ENV_SECT_SIZE	0x2000
+#define CONFIG_ENV_IS_IN_FLASH	1
+#endif
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/* Available command configuration */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_DHCP
+
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_LOADB
+
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+#define CONFIG_MII		1
+#define CONFIG_MII_INIT		1
+#define CONFIG_SYS_DISCOVER_PHY
+#define CONFIG_SYS_RX_ETH_BUFFER	8
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#define CONFIG_SYS_FEC0_PINMUX		0
+#define CONFIG_SYS_FEC0_MIIBASE	CONFIG_SYS_FEC0_IOBASE
+#define CONFIG_SYS_FEC1_PINMUX		0
+#define CONFIG_SYS_FEC1_MIIBASE	CONFIG_SYS_FEC1_IOBASE
+#define MCFFEC_TOUT_LOOP	50000
+#define CONFIG_HAS_ETH1
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+#ifndef CONFIG_SYS_DISCOVER_PHY
+#define FECDUPLEX		FULL
+#define FECSPEED		_100BASET
+#else
+#ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#endif
+#endif
+#endif
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	80000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x00000300
+#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
+#define CONFIG_SYS_I2C_PINMUX_REG	(gpio_reg->par_feci2c)
+#define CONFIG_SYS_I2C_PINMUX_CLR	(0xFFF0)
+#define CONFIG_SYS_I2C_PINMUX_SET	(0x000F)
+
+#define CONFIG_SYS_PROMPT		"-> "
+#define CONFIG_SYS_LONGHELP		/* undef to save memory	*/
+
+#if (CONFIG_CMD_KGDB)
+#	define CONFIG_SYS_CBSIZE	1024
+#else
+#	define CONFIG_SYS_CBSIZE	256
+#endif
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_LOAD_ADDR		0x800000
+
+#define CONFIG_BOOTDELAY	5
+#define CONFIG_BOOTCOMMAND	"bootm ffe40000"
+#define CONFIG_SYS_MEMTEST_START	0x400
+#define CONFIG_SYS_MEMTEST_END		0x380000
+
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_NET_RETRY_COUNT	5
+#	define CONFIG_OVERWRITE_ETHADDR_ONCE
+#endif				/* FEC_ENET */
+
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"netdev=eth0\0"				\
+	"loadaddr=10000\0"			\
+	"uboot=u-boot.bin\0"			\
+	"load=tftp ${loadaddr} ${uboot}\0"	\
+	"upd=run load; run prog\0"		\
+	"prog=prot off ffe00000 ffe3ffff;"	\
+	"era ffe00000 ffe3ffff;"		\
+	"cp.b ${loadaddr} ffe00000 ${filesize};"\
+	"save\0"				\
+	""
+
+#define CONFIG_SYS_CLK			150000000
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+#define CONFIG_SYS_MBAR		0x40000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x10000	/* Size of used area in internal SRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_SIZE		16	/* SDRAM size in MB */
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
+
+#ifdef CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_SYS_MONITOR_BASE	0x20000
+#else
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN		0x20000
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	11	/* max number of sectors on one chip */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	1000
+
+#define CONFIG_SYS_FLASH_CFI		1
+#define CONFIG_FLASH_CFI_DRIVER	1
+#define CONFIG_SYS_FLASH_SIZE		0x200000
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16
+
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
+					 CF_CACR_DISD | CF_CACR_INVI | \
+					 CF_CACR_CEIB | CF_CACR_DCM | \
+					 CF_CACR_EUSP)
+
+/*-----------------------------------------------------------------------
+ * Memory bank definitions
+ */
+#define CONFIG_SYS_CS0_BASE		0xffe00000
+#define CONFIG_SYS_CS0_CTRL		0x00001980
+#define CONFIG_SYS_CS0_MASK		0x001F0001
+
+#define CONFIG_SYS_CS1_BASE		0x30000000
+#define CONFIG_SYS_CS1_CTRL		0x00001900
+#define CONFIG_SYS_CS1_MASK		0x00070001
+
+/*-----------------------------------------------------------------------
+ * Port configuration
+ */
+#define CONFIG_SYS_FECI2C		0x0FA0
+
+#endif	/* _M5275EVB_H */
diff --git a/qemu/roms/u-boot/include/configs/M5282EVB.h b/qemu/roms/u-boot/include/configs/M5282EVB.h
new file mode 100644
index 000000000..fd970d078
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/M5282EVB.h
@@ -0,0 +1,236 @@
+/*
+ * Configuation settings for the Motorola MC5282EVB board.
+ *
+ * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _CONFIG_M5282EVB_H
+#define _CONFIG_M5282EVB_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define	CONFIG_MCF52x2		/* define processor family */
+#define CONFIG_M5282		/* define processor type */
+
+#define CONFIG_MCFTMR
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT		(0)
+#define CONFIG_BAUDRATE		115200
+
+#undef	CONFIG_MONITOR_IS_IN_RAM	/* define if monitor is started from a pre-loader */
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#define CONFIG_ENV_ADDR		0xffe04000
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_IS_IN_FLASH	1
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MII
+
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_LOADB
+
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_MII		1
+#	define CONFIG_MII_INIT		1
+#	define CONFIG_SYS_DISCOVER_PHY
+#	define CONFIG_SYS_RX_ETH_BUFFER	8
+#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+
+#	define CONFIG_SYS_FEC0_PINMUX		0
+#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
+#	define MCFFEC_TOUT_LOOP		50000
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+#	ifndef CONFIG_SYS_DISCOVER_PHY
+#		define FECDUPLEX	FULL
+#		define FECSPEED		_100BASET
+#	else
+#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#		endif
+#	endif			/* CONFIG_SYS_DISCOVER_PHY */
+#endif
+
+#define CONFIG_BOOTDELAY	5
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_ETHADDR	00:e0:0c:bc:e5:60
+#	define CONFIG_IPADDR	192.162.1.2
+#	define CONFIG_NETMASK	255.255.255.0
+#	define CONFIG_SERVERIP	192.162.1.1
+#	define CONFIG_GATEWAYIP	192.162.1.1
+#	define CONFIG_OVERWRITE_ETHADDR_ONCE
+#endif				/* CONFIG_MCFFEC */
+
+#define CONFIG_HOSTNAME		M5282EVB
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"netdev=eth0\0"				\
+	"loadaddr=10000\0"			\
+	"u-boot=u-boot.bin\0"			\
+	"load=tftp ${loadaddr) ${u-boot}\0"	\
+	"upd=run load; run prog\0"		\
+	"prog=prot off ffe00000 ffe3ffff;"	\
+	"era ffe00000 ffe3ffff;"		\
+	"cp.b ${loadaddr} ffe00000 ${filesize};"\
+	"save\0"				\
+	""
+
+#define CONFIG_SYS_PROMPT		"-> "
+#define	CONFIG_SYS_LONGHELP		/* undef to save memory         */
+
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size      */
+#else
+#define	CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size      */
+#endif
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16	/* max number of command args   */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
+
+#define CONFIG_SYS_LOAD_ADDR		0x20000
+
+#define CONFIG_SYS_MEMTEST_START	0x400
+#define CONFIG_SYS_MEMTEST_END		0x380000
+
+#define	CONFIG_SYS_CLK			64000000
+
+/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
+
+#define CONFIG_SYS_MFD			0x02	/* PLL Multiplication Factor Devider */
+#define CONFIG_SYS_RFD			0x00	/* PLL Reduce Frecuency Devider */
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+#define	CONFIG_SYS_MBAR		0x40000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x10000	/* Size of used area in internal SRAM    */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define	CONFIG_SYS_SDRAM_SIZE		16	/* SDRAM size in MB */
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
+#define	CONFIG_SYS_INT_FLASH_BASE	0xf0000000
+#define CONFIG_SYS_INT_FLASH_ENABLE	0x21
+
+/* If M5282 port is fully implemented the monitor base will be behind
+ * the vector table. */
+#if (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE)
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
+#else
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_TEXT_BASE + 0x418)	/* 24 Byte for CFM-Config */
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN		0x20000
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_FLASH_CFI
+#ifdef CONFIG_SYS_FLASH_CFI
+
+#	define CONFIG_FLASH_CFI_DRIVER	1
+#	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
+#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
+#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
+#	define CONFIG_SYS_FLASH_CHECKSUM
+#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#endif
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16
+
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV + CF_CACR_DCM)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_DISD | \
+					 CF_CACR_CEIB | CF_CACR_DBWE | \
+					 CF_CACR_EUSP)
+
+/*-----------------------------------------------------------------------
+ * Memory bank definitions
+ */
+#define CONFIG_SYS_CS0_BASE		0xFFE00000
+#define CONFIG_SYS_CS0_CTRL		0x00001980
+#define CONFIG_SYS_CS0_MASK		0x001F0001
+
+/*-----------------------------------------------------------------------
+ * Port configuration
+ */
+#define CONFIG_SYS_PACNT		0x0000000	/* Port A D[31:24] */
+#define CONFIG_SYS_PADDR		0x0000000
+#define CONFIG_SYS_PADAT		0x0000000
+
+#define CONFIG_SYS_PBCNT		0x0000000	/* Port B D[23:16] */
+#define CONFIG_SYS_PBDDR		0x0000000
+#define CONFIG_SYS_PBDAT		0x0000000
+
+#define CONFIG_SYS_PCCNT		0x0000000	/* Port C D[15:08] */
+#define CONFIG_SYS_PCDDR		0x0000000
+#define CONFIG_SYS_PCDAT		0x0000000
+
+#define CONFIG_SYS_PDCNT		0x0000000	/* Port D D[07:00] */
+#define CONFIG_SYS_PCDDR		0x0000000
+#define CONFIG_SYS_PCDAT		0x0000000
+
+#define CONFIG_SYS_PEHLPAR		0xC0
+#define CONFIG_SYS_PUAPAR		0x0F	/* UA0..UA3 = Uart 0 +1 */
+#define CONFIG_SYS_DDRUA		0x05
+#define CONFIG_SYS_PJPAR		0xFF
+
+#endif				/* _CONFIG_M5282EVB_H */
diff --git a/qemu/roms/u-boot/include/configs/M53017EVB.h b/qemu/roms/u-boot/include/configs/M53017EVB.h
new file mode 100644
index 000000000..a100d9f31
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/M53017EVB.h
@@ -0,0 +1,245 @@
+/*
+ * Configuation settings for the Freescale MCF53017EVB.
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _M53017EVB_H
+#define _M53017EVB_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MCF5301x		/* define processor family */
+#define CONFIG_M53015		/* define processor type */
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT		(0)
+#define CONFIG_BAUDRATE			115200
+
+#undef CONFIG_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT		5000
+
+/* Command line configuration */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#undef CONFIG_CMD_I2C
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+
+#define CONFIG_SYS_UNIFY_CACHE
+
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_MII		1
+#	define CONFIG_MII_INIT		1
+#	define CONFIG_SYS_DISCOVER_PHY
+#	define CONFIG_SYS_RX_ETH_BUFFER	8
+#	define CONFIG_SYS_TX_ETH_BUFFER	8
+#	define CONFIG_SYS_FEC_BUF_USE_SRAM
+#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#	define CONFIG_HAS_ETH1
+
+#	define CONFIG_SYS_FEC0_PINMUX	0
+#	define CONFIG_SYS_FEC0_MIIBASE	CONFIG_SYS_FEC0_IOBASE
+#	define CONFIG_SYS_FEC1_PINMUX	0
+#	define CONFIG_SYS_FEC1_MIIBASE	CONFIG_SYS_FEC1_IOBASE
+#	define MCFFEC_TOUT_LOOP		50000
+
+#	define CONFIG_BOOTARGS		"root=/dev/mtdblock3 rw rootfstype=jffs2"
+
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+#	ifndef CONFIG_SYS_DISCOVER_PHY
+#		define FECDUPLEX	FULL
+#		define FECSPEED		_100BASET
+#	else
+#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#		endif
+#	endif			/* CONFIG_SYS_DISCOVER_PHY */
+#endif
+
+#define CONFIG_MCFRTC
+#undef RTC_DEBUG
+#define CONFIG_SYS_RTC_CNT		(0x8000)
+#define CONFIG_SYS_RTC_SETUP		(RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN)
+
+/* Timer */
+#define CONFIG_MCFTMR
+#undef CONFIG_MCFPIT
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	80000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x58000
+#define CONFIG_SYS_IMMR			CONFIG_SYS_MBAR
+
+#define CONFIG_BOOTDELAY		1	/* autoboot after 5 seconds */
+#define CONFIG_UDP_CHECKSUM
+
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_ETHADDR	00:e0:0c:bc:e5:60
+#	define CONFIG_ETH1ADDR	00:e0:0c:bc:e5:61
+#	define CONFIG_IPADDR	192.162.1.2
+#	define CONFIG_NETMASK	255.255.255.0
+#	define CONFIG_SERVERIP	192.162.1.1
+#	define CONFIG_GATEWAYIP	192.162.1.1
+#	define CONFIG_OVERWRITE_ETHADDR_ONCE
+#endif				/* FEC_ENET */
+
+#define CONFIG_HOSTNAME		M53017
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"netdev=eth0\0"				\
+	"loadaddr=40010000\0"			\
+	"u-boot=u-boot.bin\0"			\
+	"load=tftp ${loadaddr) ${u-boot}\0"	\
+	"upd=run load; run prog\0"		\
+	"prog=prot off 0 3ffff;"		\
+	"era 0 3ffff;"				\
+	"cp.b ${loadaddr} 0 ${filesize};"	\
+	"save\0"				\
+	""
+
+#define CONFIG_PRAM		512	/* 512 KB */
+#define CONFIG_SYS_PROMPT	"-> "
+#define CONFIG_SYS_LONGHELP	/* undef to save memory */
+
+#ifdef CONFIG_CMD_KGDB
+#	define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
+#else
+#	define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
+#endif
+
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of cmd args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Arg Buf Sz */
+#define CONFIG_SYS_LOAD_ADDR	0x40010000
+
+#define CONFIG_SYS_CLK		80000000
+#define CONFIG_SYS_CPU_CLK	CONFIG_SYS_CLK * 3
+
+#define CONFIG_SYS_MBAR		0xFC000000
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
+#define CONFIG_SYS_INIT_RAM_SIZE		0x20000	/* Size of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_CTRL	0x221
+#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CONFIG_SYS_SDRAM_SIZE		64	/* SDRAM size in MB */
+#define CONFIG_SYS_SDRAM_CFG1		0x43711630
+#define CONFIG_SYS_SDRAM_CFG2		0x56670000
+#define CONFIG_SYS_SDRAM_CTRL		0xE1092000
+#define CONFIG_SYS_SDRAM_EMOD		0x80010000
+#define CONFIG_SYS_SDRAM_MODE		0x00CD0000
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
+#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
+
+#define CONFIG_SYS_MONITOR_BASE		(CONFIG_SYS_FLASH_BASE + 0x400)
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_FLASH_CFI
+#ifdef CONFIG_SYS_FLASH_CFI
+#	define CONFIG_FLASH_CFI_DRIVER		1
+#	define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+#	define CONFIG_FLASH_SPANSION_S29WS_N	1
+#	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
+#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
+#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
+#endif
+
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#define CONFIG_ENV_OFFSET		0x8000
+#define CONFIG_ENV_SIZE			0x1000
+#define CONFIG_ENV_SECT_SIZE		0x8000
+#define CONFIG_ENV_IS_IN_FLASH		1
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16
+
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINVA)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_EC | CF_CACR_CINVA | \
+					 CF_CACR_DCM_P)
+
+/*-----------------------------------------------------------------------
+ * Chipselect bank definitions
+ */
+/*
+ * CS0 - NOR Flash
+ * CS1 - Ext SRAM
+ * CS2 - Available
+ * CS3 - Available
+ * CS4 - Available
+ * CS5 - Available
+ */
+#define CONFIG_SYS_CS0_BASE		0
+#define CONFIG_SYS_CS0_MASK		0x00FF0001
+#define CONFIG_SYS_CS0_CTRL		0x00001FA0
+
+#define CONFIG_SYS_CS1_BASE		0xC0000000
+#define CONFIG_SYS_CS1_MASK		0x00070001
+#define CONFIG_SYS_CS1_CTRL		0x00001FA0
+
+#endif				/* _M53017EVB_H */
diff --git a/qemu/roms/u-boot/include/configs/M5329EVB.h b/qemu/roms/u-boot/include/configs/M5329EVB.h
new file mode 100644
index 000000000..78ea38437
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/M5329EVB.h
@@ -0,0 +1,255 @@
+/*
+ * Configuation settings for the Freescale MCF5329 FireEngine board.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _M5329EVB_H
+#define _M5329EVB_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MCF532x		/* define processor family */
+#define CONFIG_M5329		/* define processor type */
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT		(0)
+#define CONFIG_BAUDRATE		115200
+
+#undef CONFIG_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT	5000	/* timeout in milliseconds, max timeout is 6.71sec */
+
+/* Command line configuration */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+
+#ifdef CONFIG_NANDFLASH_SIZE
+#      define CONFIG_CMD_NAND
+#endif
+
+#define CONFIG_SYS_UNIFY_CACHE
+
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_MII		1
+#	define CONFIG_MII_INIT		1
+#	define CONFIG_SYS_DISCOVER_PHY
+#	define CONFIG_SYS_RX_ETH_BUFFER	8
+#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+
+#	define CONFIG_SYS_FEC0_PINMUX		0
+#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
+#	define MCFFEC_TOUT_LOOP		50000
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+#	ifndef CONFIG_SYS_DISCOVER_PHY
+#		define FECDUPLEX	FULL
+#		define FECSPEED		_100BASET
+#	else
+#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#		endif
+#	endif			/* CONFIG_SYS_DISCOVER_PHY */
+#endif
+
+#define CONFIG_MCFRTC
+#undef RTC_DEBUG
+
+/* Timer */
+#define CONFIG_MCFTMR
+#undef CONFIG_MCFPIT
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	80000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x58000
+#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
+
+#define CONFIG_BOOTDELAY	1	/* autoboot after 5 seconds */
+#define CONFIG_UDP_CHECKSUM
+
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_ETHADDR	00:e0:0c:bc:e5:60
+#	define CONFIG_IPADDR	192.162.1.2
+#	define CONFIG_NETMASK	255.255.255.0
+#	define CONFIG_SERVERIP	192.162.1.1
+#	define CONFIG_GATEWAYIP	192.162.1.1
+#	define CONFIG_OVERWRITE_ETHADDR_ONCE
+#endif				/* FEC_ENET */
+
+#define CONFIG_HOSTNAME		M5329EVB
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"			\
+	"loadaddr=40010000\0"	\
+	"u-boot=u-boot.bin\0"	\
+	"load=tftp ${loadaddr) ${u-boot}\0"	\
+	"upd=run load; run prog\0"	\
+	"prog=prot off 0 3ffff;"	\
+	"era 0 3ffff;"	\
+	"cp.b ${loadaddr} 0 ${filesize};"	\
+	"save\0"	\
+	""
+
+#define CONFIG_PRAM		512	/* 512 KB */
+#define CONFIG_SYS_PROMPT		"-> "
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+
+#ifdef CONFIG_CMD_KGDB
+#	define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
+#else
+#	define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
+#endif
+
+#define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
+#define CONFIG_SYS_LOAD_ADDR		0x40010000
+
+#define CONFIG_SYS_CLK			80000000
+#define CONFIG_SYS_CPU_CLK		CONFIG_SYS_CLK * 3
+
+#define CONFIG_SYS_MBAR		0xFC000000
+
+#define CONFIG_SYS_LATCH_ADDR		(CONFIG_SYS_CS1_BASE + 0x80000)
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x8000	/* Size of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_CTRL	0x221
+#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CONFIG_SYS_SDRAM_SIZE		32	/* SDRAM size in MB */
+#define CONFIG_SYS_SDRAM_CFG1		0x53722730
+#define CONFIG_SYS_SDRAM_CFG2		0x56670000
+#define CONFIG_SYS_SDRAM_CTRL		0xE1092000
+#define CONFIG_SYS_SDRAM_EMOD		0x40010000
+#define CONFIG_SYS_SDRAM_MODE		0x018D0000
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
+#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
+
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_FLASH_CFI
+#ifdef CONFIG_SYS_FLASH_CFI
+#	define CONFIG_FLASH_CFI_DRIVER	1
+#	define CONFIG_SYS_FLASH_SIZE		0x800000	/* Max size that the board might have */
+#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
+#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
+#endif
+
+#ifdef CONFIG_NANDFLASH_SIZE
+#	define CONFIG_SYS_MAX_NAND_DEVICE	1
+#	define CONFIG_SYS_NAND_BASE		CONFIG_SYS_CS2_BASE
+#	define CONFIG_SYS_NAND_SIZE		1
+#	define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#	define NAND_ALLOW_ERASE_ALL	1
+#	define CONFIG_JFFS2_NAND	1
+#	define CONFIG_JFFS2_DEV		"nand0"
+#	define CONFIG_JFFS2_PART_SIZE	(CONFIG_SYS_CS2_MASK & ~1)
+#	define CONFIG_JFFS2_PART_OFFSET	0x00000000
+#endif
+
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#define CONFIG_ENV_OFFSET		0x4000
+#define CONFIG_ENV_SECT_SIZE	0x2000
+#define CONFIG_ENV_IS_IN_FLASH	1
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16
+
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINVA)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_EC | CF_CACR_CINVA | \
+					 CF_CACR_DCM_P)
+
+/*-----------------------------------------------------------------------
+ * Chipselect bank definitions
+ */
+/*
+ * CS0 - NOR Flash 1, 2, 4, or 8MB
+ * CS1 - CompactFlash and registers
+ * CS2 - NAND Flash 16, 32, or 64MB
+ * CS3 - Available
+ * CS4 - Available
+ * CS5 - Available
+ */
+#define CONFIG_SYS_CS0_BASE		0
+#define CONFIG_SYS_CS0_MASK		0x007f0001
+#define CONFIG_SYS_CS0_CTRL		0x00001fa0
+
+#define CONFIG_SYS_CS1_BASE		0x10000000
+#define CONFIG_SYS_CS1_MASK		0x001f0001
+#define CONFIG_SYS_CS1_CTRL		0x002A3780
+
+#ifdef CONFIG_NANDFLASH_SIZE
+#define CONFIG_SYS_CS2_BASE		0x20000000
+#define CONFIG_SYS_CS2_MASK		((CONFIG_NANDFLASH_SIZE << 20) | 1)
+#define CONFIG_SYS_CS2_CTRL		0x00001f60
+#endif
+
+#endif				/* _M5329EVB_H */
diff --git a/qemu/roms/u-boot/include/configs/M5373EVB.h b/qemu/roms/u-boot/include/configs/M5373EVB.h
new file mode 100644
index 000000000..849c26562
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/M5373EVB.h
@@ -0,0 +1,255 @@
+/*
+ * Configuation settings for the Freescale MCF5373 FireEngine board.
+ *
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _M5373EVB_H
+#define _M5373EVB_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MCF532x		/* define processor family */
+#define CONFIG_M5373		/* define processor type */
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT		(0)
+#define CONFIG_BAUDRATE		115200
+
+#undef CONFIG_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT	3360	/* timeout in ms, max is 3.36 sec */
+
+/* Command line configuration */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+
+#ifdef CONFIG_NANDFLASH_SIZE
+#      define CONFIG_CMD_NAND
+#endif
+
+#define CONFIG_SYS_UNIFY_CACHE
+
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_MII		1
+#	define CONFIG_MII_INIT		1
+#	define CONFIG_SYS_DISCOVER_PHY
+#	define CONFIG_SYS_RX_ETH_BUFFER	8
+#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+
+#	define CONFIG_SYS_FEC0_PINMUX		0
+#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
+#	define MCFFEC_TOUT_LOOP		50000
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+#	ifndef CONFIG_SYS_DISCOVER_PHY
+#		define FECDUPLEX	FULL
+#		define FECSPEED		_100BASET
+#	else
+#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#		endif
+#	endif			/* CONFIG_SYS_DISCOVER_PHY */
+#endif
+
+#define CONFIG_MCFRTC
+#undef RTC_DEBUG
+
+/* Timer */
+#define CONFIG_MCFTMR
+#undef CONFIG_MCFPIT
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	80000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x58000
+#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
+
+#define CONFIG_BOOTDELAY	1	/* autoboot after 5 seconds */
+#define CONFIG_UDP_CHECKSUM
+
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_ETHADDR	00:e0:0c:bc:e5:60
+#	define CONFIG_IPADDR	192.162.1.2
+#	define CONFIG_NETMASK	255.255.255.0
+#	define CONFIG_SERVERIP	192.162.1.1
+#	define CONFIG_GATEWAYIP	192.162.1.1
+#	define CONFIG_OVERWRITE_ETHADDR_ONCE
+#endif				/* FEC_ENET */
+
+#define CONFIG_HOSTNAME		M5373EVB
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"			\
+	"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0"	\
+	"u-boot=u-boot.bin\0"	\
+	"load=tftp ${loadaddr) ${u-boot}\0"	\
+	"upd=run load; run prog\0"	\
+	"prog=prot off 0 3ffff;"	\
+	"era 0 3ffff;"	\
+	"cp.b ${loadaddr} 0 ${filesize};"	\
+	"save\0"	\
+	""
+
+#define CONFIG_PRAM		512	/* 512 KB */
+#define CONFIG_SYS_PROMPT		"-> "
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+
+#ifdef CONFIG_CMD_KGDB
+#	define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
+#else
+#	define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
+#endif
+
+#define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
+#define CONFIG_SYS_LOAD_ADDR		0x40010000
+
+#define CONFIG_SYS_CLK			80000000
+#define CONFIG_SYS_CPU_CLK		CONFIG_SYS_CLK * 3
+
+#define CONFIG_SYS_MBAR		0xFC000000
+
+#define CONFIG_SYS_LATCH_ADDR		(CONFIG_SYS_CS1_BASE + 0x80000)
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x8000	/* Size of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_CTRL	0x221
+#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CONFIG_SYS_SDRAM_SIZE		32	/* SDRAM size in MB */
+#define CONFIG_SYS_SDRAM_CFG1		0x53722730
+#define CONFIG_SYS_SDRAM_CFG2		0x56670000
+#define CONFIG_SYS_SDRAM_CTRL		0xE1092000
+#define CONFIG_SYS_SDRAM_EMOD		0x40010000
+#define CONFIG_SYS_SDRAM_MODE		0x018D0000
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
+#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
+
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_FLASH_CFI
+#ifdef CONFIG_SYS_FLASH_CFI
+#	define CONFIG_FLASH_CFI_DRIVER	1
+#	define CONFIG_SYS_FLASH_SIZE		0x800000	/* Max size that the board might have */
+#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
+#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
+#endif
+
+#ifdef CONFIG_NANDFLASH_SIZE
+#	define CONFIG_SYS_MAX_NAND_DEVICE	1
+#	define CONFIG_SYS_NAND_BASE		CONFIG_SYS_CS2_BASE
+#	define CONFIG_SYS_NAND_SIZE		1
+#	define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#	define NAND_ALLOW_ERASE_ALL	1
+#	define CONFIG_JFFS2_NAND	1
+#	define CONFIG_JFFS2_DEV		"nand0"
+#	define CONFIG_JFFS2_PART_SIZE	(CONFIG_SYS_CS2_MASK & ~1)
+#	define CONFIG_JFFS2_PART_OFFSET	0x00000000
+#endif
+
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#define CONFIG_ENV_OFFSET		0x4000
+#define CONFIG_ENV_SECT_SIZE	0x2000
+#define CONFIG_ENV_IS_IN_FLASH	1
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16
+
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINVA)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_EC | CF_CACR_CINVA | \
+					 CF_CACR_DCM_P)
+
+/*-----------------------------------------------------------------------
+ * Chipselect bank definitions
+ */
+/*
+ * CS0 - NOR Flash 1, 2, 4, or 8MB
+ * CS1 - CompactFlash and registers
+ * CS2 - NAND Flash 16, 32, or 64MB
+ * CS3 - Available
+ * CS4 - Available
+ * CS5 - Available
+ */
+#define CONFIG_SYS_CS0_BASE		0
+#define CONFIG_SYS_CS0_MASK		0x007f0001
+#define CONFIG_SYS_CS0_CTRL		0x00001fa0
+
+#define CONFIG_SYS_CS1_BASE		0x10000000
+#define CONFIG_SYS_CS1_MASK		0x001f0001
+#define CONFIG_SYS_CS1_CTRL		0x002A3780
+
+#ifdef CONFIG_NANDFLASH_SIZE
+#define CONFIG_SYS_CS2_BASE		0x20000000
+#define CONFIG_SYS_CS2_MASK		((CONFIG_NANDFLASH_SIZE << 20) | 1)
+#define CONFIG_SYS_CS2_CTRL		0x00001f60
+#endif
+
+#endif				/* _M5373EVB_H */
diff --git a/qemu/roms/u-boot/include/configs/M54418TWR.h b/qemu/roms/u-boot/include/configs/M54418TWR.h
new file mode 100644
index 000000000..3d7dc1fb2
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/M54418TWR.h
@@ -0,0 +1,427 @@
+/*
+ * Configuation settings for the Freescale MCF54418 TWR board.
+ *
+ * Copyright 2010-2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _M54418TWR_H
+#define _M54418TWR_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MCF5441x	/* define processor family */
+#define CONFIG_M54418		/* define processor type */
+#define CONFIG_M54418TWR	/* M54418TWR board */
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT		(0)
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
+
+#undef CONFIG_WATCHDOG
+
+#define CONFIG_TIMESTAMP	/* Print image info with timestamp */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/* Command line configuration */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_CACHE
+#undef CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_I2C
+#undef CONFIG_CMD_JFFS2
+#undef CONFIG_CMD_UBI
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_MII
+#undef CONFIG_CMD_NAND
+#undef CONFIG_CMD_NAND_YAFFS
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#undef CONFIG_CMD_IMLS
+
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+
+/*
+ * NAND FLASH
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_JFFS2_NAND
+#define CONFIG_NAND_FSL_NFC
+#define CONFIG_SYS_NAND_BASE		0xFC0FC000
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define NAND_MAX_CHIPS			CONFIG_SYS_MAX_NAND_DEVICE
+#define CONFIG_SYS_NAND_SELECT_DEVICE
+#endif
+
+/* Network configuration */
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+#define CONFIG_NET_MULTI		1
+#define CONFIG_MII			1
+#define CONFIG_MII_INIT		1
+#define CONFIG_SYS_DISCOVER_PHY
+#define CONFIG_SYS_RX_ETH_BUFFER	2
+#define CONFIG_SYS_FAULT_ECCONFIG_SYS_NO_FLASHHO_LINK_DOWN
+#define CONFIG_SYS_TX_ETH_BUFFER	2
+#define CONFIG_HAS_ETH1
+
+#define CONFIG_SYS_FEC0_PINMUX		0
+#define CONFIG_SYS_FEC0_MIIBASE	CONFIG_SYS_FEC0_IOBASE
+#define CONFIG_SYS_FEC1_PINMUX		0
+#define CONFIG_SYS_FEC1_MIIBASE	CONFIG_SYS_FEC0_MIIBASE
+#define MCFFEC_TOUT_LOOP		50000
+#define CONFIG_SYS_FEC0_PHYADDR	0
+#define CONFIG_SYS_FEC1_PHYADDR	1
+
+#define CONFIG_BOOTDELAY		2	/* autoboot after 5 seconds */
+
+#ifdef	CONFIG_SYS_NAND_BOOT
+#define CONFIG_BOOTARGS	"root=/dev/mtdblock2 rw rootfstype=jffs2 " \
+				"mtdparts=NAND:1M(u-boot)ro,7M(kernel)ro," \
+				"-(jffs2) console=ttyS0,115200"
+#else
+#define CONFIG_BOOTARGS	"root=/dev/nfs rw nfsroot="	\
+				__stringify(CONFIG_SERVERIP) ":/tftpboot/" \
+				__stringify(CONFIG_IPADDR) "  ip="	\
+				__stringify(CONFIG_IPADDR) ":"	\
+				__stringify(CONFIG_SERVERIP)":"	\
+				__stringify(CONFIG_GATEWAYIP)": "	\
+				__stringify(CONFIG_NETMASK)		\
+				"::eth0:off:rw console=ttyS0,115200"
+#endif
+
+#define CONFIG_ETHADDR		00:e0:0c:bc:e5:60
+#define CONFIG_ETH1ADDR	00:e0:0c:bc:e5:61
+#define CONFIG_ETHPRIME	"FEC0"
+#define CONFIG_IPADDR		192.168.1.2
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_SERVERIP	192.168.1.1
+#define CONFIG_GATEWAYIP	192.168.1.1
+
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
+#define CONFIG_SYS_FEC_BUF_USE_SRAM
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+#ifndef CONFIG_SYS_DISCOVER_PHY
+#define FECDUPLEX	FULL
+#define FECSPEED	_100BASET
+#define LINKSTATUS	1
+#else
+#define LINKSTATUS	0
+#ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#endif
+#endif			/* CONFIG_SYS_DISCOVER_PHY */
+#endif
+
+#define CONFIG_HOSTNAME		M54418TWR
+
+#if defined(CONFIG_CF_SBF)
+/* ST Micro serial flash */
+#define	CONFIG_SYS_LOAD_ADDR2		0x40010007
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"netdev=eth0\0"				\
+	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
+	"loadaddr=0x40010000\0"			\
+	"sbfhdr=sbfhdr.bin\0"			\
+	"uboot=u-boot.bin\0"			\
+	"load=tftp ${loadaddr} ${sbfhdr};"	\
+	"tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0"	\
+	"upd=run load; run prog\0"		\
+	"prog=sf probe 0:1 1000000 3;"		\
+	"sf erase 0 40000;"			\
+	"sf write ${loadaddr} 0 40000;"		\
+	"save\0"				\
+	""
+#elif defined(CONFIG_SYS_NAND_BOOT)
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"netdev=eth0\0"				\
+	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
+	"loadaddr=0x40010000\0"			\
+	"u-boot=u-boot.bin\0"			\
+	"load=tftp ${loadaddr} ${u-boot};\0"	\
+	"upd=run load; run prog\0"		\
+	"prog=nand device 0;"			\
+	"nand erase 0 40000;"			\
+	"nb_update ${loadaddr} ${filesize};"	\
+	"save\0"				\
+	""
+#else
+#define CONFIG_SYS_UBOOT_END	0x3FFFF
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"netdev=eth0\0"				\
+	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
+	"loadaddr=40010000\0"			\
+	"u-boot=u-boot.bin\0"			\
+	"load=tftp ${loadaddr) ${u-boot}\0"	\
+	"upd=run load; run prog\0"		\
+	"prog=prot off mram" " ;"	\
+	"cp.b ${loadaddr} 0 ${filesize};"	\
+	"save\0"				\
+	""
+#endif
+
+/* Realtime clock */
+#undef CONFIG_MCFRTC
+#define CONFIG_RTC_MCFRRTC
+#define CONFIG_SYS_MCFRRTC_BASE		0xFC0A8000
+
+/* Timer */
+#define CONFIG_MCFTMR
+#undef CONFIG_MCFPIT
+
+/* I2c */
+#undef CONFIG_SYS_FSL_I2C
+#undef CONFIG_HARD_I2C		/* I2C with hardware support */
+#undef	CONFIG_SYS_I2C_SOFT	/* I2C bit-banged */
+/* I2C speed and slave address  */
+#define CONFIG_SYS_I2C_SPEED		80000
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_OFFSET		0x58000
+#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
+
+/* DSPI and Serial Flash */
+#define CONFIG_CF_SPI
+#define CONFIG_CF_DSPI
+#define CONFIG_SERIAL_FLASH
+#define CONFIG_HARD_SPI
+#define CONFIG_SYS_SBFHDR_SIZE		0x7
+#ifdef CONFIG_CMD_SPI
+#	define CONFIG_SPI_FLASH
+#	define CONFIG_SPI_FLASH_ATMEL
+
+#	define CONFIG_SYS_DSPI_CTAR0	(DSPI_CTAR_TRSZ(7) | \
+					 DSPI_CTAR_PCSSCK_1CLK | \
+					 DSPI_CTAR_PASC(0) | \
+					 DSPI_CTAR_PDT(0) | \
+					 DSPI_CTAR_CSSCK(0) | \
+					 DSPI_CTAR_ASC(0) | \
+					 DSPI_CTAR_DT(1))
+#	define CONFIG_SYS_DSPI_CTAR1	(CONFIG_SYS_DSPI_CTAR0)
+#	define CONFIG_SYS_DSPI_CTAR2	(CONFIG_SYS_DSPI_CTAR0)
+#endif
+
+/* Input, PCI, Flexbus, and VCO */
+#define CONFIG_EXTRA_CLOCK
+
+#define CONFIG_PRAM			2048	/* 2048 KB */
+
+/* HUSH */
+#define CONFIG_SYS_HUSH_PARSER		1
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+
+#define CONFIG_SYS_PROMPT		"-> "
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+#endif
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+/* Boot Argument Buffer Size    */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x10000)
+
+#define CONFIG_SYS_MBAR		0xFC000000
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
+/* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x10000
+#define CONFIG_SYS_INIT_RAM_CTRL	0x221
+#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE) - 32)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+#define CONFIG_SYS_SBFHDR_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - 32)
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CONFIG_SYS_SDRAM_SIZE		128	/* SDRAM size in MB */
+
+#define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE + 0x400)
+#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
+#define CONFIG_SYS_DRAM_TEST
+
+#if defined(CONFIG_CF_SBF) || defined(CONFIG_SYS_NAND_BOOT)
+#define CONFIG_SERIAL_BOOT
+#endif
+
+#if defined(CONFIG_SERIAL_BOOT)
+#define CONFIG_SYS_MONITOR_BASE	(TEXT_BASE + 0x400)
+#else
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
+#endif
+
+#define CONFIG_SYS_BOOTPARAMS_LEN	(64 * 1024)
+/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)
+/* Reserve 256 kB for malloc() */
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \
+				(CONFIG_SYS_SDRAM_SIZE << 20))
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#if !defined(CONFIG_SERIAL_BOOT)  /*MRAM boot*/
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_IS_IN_MRAM	1
+#define CONFIG_ENV_ADDR		(0x40000 - 0x1000) /*MRAM size 40000*/
+#define CONFIG_ENV_SIZE		0x1000
+#endif
+
+#if defined(CONFIG_CF_SBF)
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_IS_IN_SPI_FLASH	1
+#define CONFIG_ENV_SPI_CS		1
+#define CONFIG_ENV_OFFSET		0x40000
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE		0x10000
+#endif
+#if defined(CONFIG_SYS_NAND_BOOT)
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_OFFSET	0x80000
+#define CONFIG_ENV_SIZE	0x20000
+#define CONFIG_ENV_SECT_SIZE	0x20000
+#endif
+#undef CONFIG_ENV_OVERWRITE
+
+/* FLASH organization */
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
+
+#undef CONFIG_SYS_FLASH_CFI
+#ifdef CONFIG_SYS_FLASH_CFI
+
+#define CONFIG_FLASH_CFI_DRIVER	1
+/* Max size that the board might have */
+#define CONFIG_SYS_FLASH_SIZE		0x1000000
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_SECT	270
+/* "Real" (hardware) sectors protection */
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_CS0_BASE }
+#else
+/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_SECT	270
+/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	0
+#endif
+
+/*
+ * This is setting for JFFS2 support in u-boot.
+ * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
+ */
+#ifdef CONFIG_CMD_JFFS2
+#define CONFIG_JFFS2_DEV		"nand0"
+#define CONFIG_JFFS2_PART_OFFSET	(0x800000)
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define MTDIDS_DEFAULT		"nand0=m54418twr.nand"
+
+#define MTDPARTS_DEFAULT	"mtdparts=m54418twr.nand:1m(data),"	\
+						"7m(kernel),"		\
+						"-(rootfs)"
+
+#endif
+
+#ifdef CONFIG_CMD_UBI
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE	/* needed for mtdparts command */
+#define CONFIG_MTD_PARTITIONS	/* mtdparts and UBI support */
+#define CONFIG_RBTREE
+#define MTDIDS_DEFAULT		"nand0=NAND"
+#define MTDPARTS_DEFAULT	"mtdparts=NAND:1m(u-boot),"	\
+					"-(ubi)"
+#endif
+/* Cache Configuration */
+#define CONFIG_SYS_CACHELINE_SIZE	16
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_BCINVA + CF_CACR_ICINVA)
+#define CONFIG_SYS_DCACHE_INV		(CF_CACR_DCINVA)
+#define CONFIG_SYS_CACHE_ACR2		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_BEC | CF_CACR_IEC | \
+					 CF_CACR_ICINVA | CF_CACR_EUSP)
+#define CONFIG_SYS_CACHE_DCACR		((CONFIG_SYS_CACHE_ICACR | \
+					 CF_CACR_DEC | CF_CACR_DDCM_P | \
+					 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
+
+#define CACR_STATUS	(CONFIG_SYS_INIT_RAM_ADDR + \
+			CONFIG_SYS_INIT_RAM_SIZE - 12)
+
+/*-----------------------------------------------------------------------
+ * Memory bank definitions
+ */
+/*
+ * CS0 - NOR Flash 16MB
+ * CS1 - Available
+ * CS2 - Available
+ * CS3 - Available
+ * CS4 - Available
+ * CS5 - Available
+ */
+
+ /* Flash */
+#define CONFIG_SYS_CS0_BASE		0x00000000
+#define CONFIG_SYS_CS0_MASK		0x000F0101
+#define CONFIG_SYS_CS0_CTRL		0x00001D60
+
+#endif				/* _M54418TWR_H */
diff --git a/qemu/roms/u-boot/include/configs/M54451EVB.h b/qemu/roms/u-boot/include/configs/M54451EVB.h
new file mode 100644
index 000000000..0f4b726f3
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/M54451EVB.h
@@ -0,0 +1,327 @@
+/*
+ * Configuation settings for the Freescale MCF54451 EVB board.
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _M54451EVB_H
+#define _M54451EVB_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MCF5445x		/* define processor family */
+#define CONFIG_M54451		/* define processor type */
+#define CONFIG_M54451EVB	/* M54451EVB board */
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT		(0)
+#define CONFIG_BAUDRATE		115200
+
+#undef CONFIG_WATCHDOG
+
+#define CONFIG_TIMESTAMP	/* Print image info with timestamp */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/* Command line configuration */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#undef CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+
+/* Network configuration */
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_MII		1
+#	define CONFIG_MII_INIT		1
+#	define CONFIG_SYS_DISCOVER_PHY
+#	define CONFIG_SYS_RX_ETH_BUFFER	8
+#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+
+#	define CONFIG_SYS_FEC0_PINMUX	0
+#	define CONFIG_SYS_FEC0_MIIBASE	CONFIG_SYS_FEC0_IOBASE
+#	define MCFFEC_TOUT_LOOP 50000
+
+#	define CONFIG_BOOTDELAY	1	/* autoboot after 5 seconds */
+#	define CONFIG_BOOTARGS		"root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:2M(kernel)ro,-(jffs2)"
+#	define CONFIG_ETHADDR		00:e0:0c:bc:e5:60
+#	define CONFIG_ETHPRIME		"FEC0"
+#	define CONFIG_IPADDR		192.162.1.2
+#	define CONFIG_NETMASK		255.255.255.0
+#	define CONFIG_SERVERIP		192.162.1.1
+#	define CONFIG_GATEWAYIP		192.162.1.1
+#	define CONFIG_OVERWRITE_ETHADDR_ONCE
+
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+#	ifndef CONFIG_SYS_DISCOVER_PHY
+#		define FECDUPLEX	FULL
+#		define FECSPEED		_100BASET
+#	else
+#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#		endif
+#	endif			/* CONFIG_SYS_DISCOVER_PHY */
+#endif
+
+#define CONFIG_HOSTNAME		M54451EVB
+#ifdef CONFIG_SYS_STMICRO_BOOT
+/* ST Micro serial flash */
+#define	CONFIG_SYS_LOAD_ADDR2		0x40010007
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"netdev=eth0\0"				\
+	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
+	"loadaddr=0x40010000\0"			\
+	"sbfhdr=sbfhdr.bin\0"			\
+	"uboot=u-boot.bin\0"			\
+	"load=tftp ${loadaddr} ${sbfhdr};"	\
+	"tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0"	\
+	"upd=run load; run prog\0"		\
+	"prog=sf probe 0:1 1000000 3;"		\
+	"sf erase 0 30000;"			\
+	"sf write ${loadaddr} 0 30000;"		\
+	"save\0"				\
+	""
+#else
+#define CONFIG_SYS_UBOOT_END	0x3FFFF
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"netdev=eth0\0"				\
+	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
+	"loadaddr=40010000\0"			\
+	"u-boot=u-boot.bin\0"			\
+	"load=tftp ${loadaddr) ${u-boot}\0"	\
+	"upd=run load; run prog\0"		\
+	"prog=prot off 0 " __stringify(CONFIG_SYS_UBOOT_END)	\
+	"; era 0 " __stringify(CONFIG_SYS_UBOOT_END) " ;"	\
+	"cp.b ${loadaddr} 0 ${filesize};"	\
+	"save\0"				\
+	""
+#endif
+
+/* Realtime clock */
+#define CONFIG_MCFRTC
+#undef RTC_DEBUG
+#define CONFIG_SYS_RTC_OSCILLATOR	(32 * CONFIG_SYS_HZ)
+
+/* Timer */
+#define CONFIG_MCFTMR
+#undef CONFIG_MCFPIT
+
+/* I2c */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	80000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x58000
+#define CONFIG_SYS_IMMR			CONFIG_SYS_MBAR
+
+/* DSPI and Serial Flash */
+#define CONFIG_CF_SPI
+#define CONFIG_CF_DSPI
+#define CONFIG_SERIAL_FLASH
+#define CONFIG_HARD_SPI
+#define CONFIG_SYS_SBFHDR_SIZE		0x7
+#ifdef CONFIG_CMD_SPI
+#	define CONFIG_SPI_FLASH
+#	define CONFIG_SPI_FLASH_STMICRO
+
+#	define CONFIG_SYS_DSPI_CTAR0	(DSPI_CTAR_TRSZ(7) | \
+					 DSPI_CTAR_PCSSCK_1CLK | \
+					 DSPI_CTAR_PASC(0) | \
+					 DSPI_CTAR_PDT(0) | \
+					 DSPI_CTAR_CSSCK(0) | \
+					 DSPI_CTAR_ASC(0) | \
+					 DSPI_CTAR_DT(1))
+#	define CONFIG_SYS_DSPI_CTAR1	(CONFIG_SYS_DSPI_CTAR0)
+#	define CONFIG_SYS_DSPI_CTAR2	(CONFIG_SYS_DSPI_CTAR0)
+#endif
+
+/* Input, PCI, Flexbus, and VCO */
+#define CONFIG_EXTRA_CLOCK
+
+#define CONFIG_PRAM			2048	/* 2048 KB */
+
+#define CONFIG_SYS_PROMPT		"-> "
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE			1024	/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE			256	/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
+
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x10000)
+
+#define CONFIG_SYS_MBAR			0xFC000000
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x8000	/* Size of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_CTRL	0x221
+#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+#define CONFIG_SYS_SBFHDR_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - 32)
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CONFIG_SYS_SDRAM_SIZE		128	/* SDRAM size in MB */
+#define CONFIG_SYS_SDRAM_CFG1		0x33633F30
+#define CONFIG_SYS_SDRAM_CFG2		0x57670000
+#define CONFIG_SYS_SDRAM_CTRL		0xE20D2C00
+#define CONFIG_SYS_SDRAM_EMOD		0x80810000
+#define CONFIG_SYS_SDRAM_MODE		0x008D0000
+#define CONFIG_SYS_SDRAM_DRV_STRENGTH	0x44
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
+#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
+
+#ifdef CONFIG_CF_SBF
+#	define CONFIG_SERIAL_BOOT
+#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_TEXT_BASE + 0x400)
+#else
+#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
+#endif
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+
+/* Reserve 256 kB for malloc() */
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+
+/* Configuration for environment
+ * Environment is not embedded in u-boot. First time runing may have env
+ * crc error warning if there is no correct environment on the flash.
+ */
+#if defined(CONFIG_SYS_STMICRO_BOOT)
+#	define CONFIG_ENV_IS_IN_SPI_FLASH	1
+#	define CONFIG_ENV_SPI_CS		1
+#	define CONFIG_ENV_OFFSET		0x20000
+#	define CONFIG_ENV_SIZE		0x2000
+#	define CONFIG_ENV_SECT_SIZE	0x10000
+#else
+#	define CONFIG_ENV_IS_IN_FLASH	1
+#	define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x40000)
+#	define CONFIG_ENV_SIZE		0x2000
+#	define CONFIG_ENV_SECT_SIZE	0x20000
+#endif
+#undef CONFIG_ENV_OVERWRITE
+
+/* FLASH organization */
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
+
+#define CONFIG_SYS_FLASH_CFI
+#ifdef CONFIG_SYS_FLASH_CFI
+
+#	define CONFIG_FLASH_CFI_DRIVER	1
+#	define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+#	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
+#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
+#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
+#	define CONFIG_SYS_FLASH_CHECKSUM
+#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_CS0_BASE }
+
+#endif
+
+/*
+ * This is setting for JFFS2 support in u-boot.
+ * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
+ */
+#ifdef CONFIG_CMD_JFFS2
+#	define CONFIG_JFFS2_DEV		"nor0"
+#	define CONFIG_JFFS2_PART_SIZE	0x01000000
+#	define CONFIG_JFFS2_PART_OFFSET	(CONFIG_SYS_FLASH0_BASE + 0x500000)
+#endif
+
+/* Cache Configuration */
+#define CONFIG_SYS_CACHELINE_SIZE		16
+
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_BCINVA + CF_CACR_ICINVA)
+#define CONFIG_SYS_DCACHE_INV		(CF_CACR_DCINVA)
+#define CONFIG_SYS_CACHE_ACR2		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_BEC | CF_CACR_IEC | \
+					 CF_CACR_ICINVA | CF_CACR_EUSP)
+#define CONFIG_SYS_CACHE_DCACR		((CONFIG_SYS_CACHE_ICACR | \
+					 CF_CACR_DEC | CF_CACR_DDCM_P | \
+					 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
+
+/*-----------------------------------------------------------------------
+ * Memory bank definitions
+ */
+/*
+ * CS0 - NOR Flash 16MB
+ * CS1 - Available
+ * CS2 - Available
+ * CS3 - Available
+ * CS4 - Available
+ * CS5 - Available
+ */
+
+ /* Flash */
+#define CONFIG_SYS_CS0_BASE		0x00000000
+#define CONFIG_SYS_CS0_MASK		0x00FF0001
+#define CONFIG_SYS_CS0_CTRL		0x00004D80
+
+#define CONFIG_SYS_SPANSION_BASE	CONFIG_SYS_CS0_BASE
+
+#endif				/* _M54451EVB_H */
diff --git a/qemu/roms/u-boot/include/configs/M54455EVB.h b/qemu/roms/u-boot/include/configs/M54455EVB.h
new file mode 100644
index 000000000..7a55d3c61
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/M54455EVB.h
@@ -0,0 +1,455 @@
+/*
+ * Configuation settings for the Freescale MCF54455 EVB board.
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _M54455EVB_H
+#define _M54455EVB_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MCF5445x		/* define processor family */
+#define CONFIG_M54455		/* define processor type */
+#define CONFIG_M54455EVB	/* M54455EVB board */
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT		(0)
+#define CONFIG_BAUDRATE		115200
+
+#undef CONFIG_WATCHDOG
+
+#define CONFIG_TIMESTAMP	/* Print image info with timestamp */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/* Command line configuration */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#undef CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+
+/* Network configuration */
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_MII		1
+#	define CONFIG_MII_INIT		1
+#	define CONFIG_SYS_DISCOVER_PHY
+#	define CONFIG_SYS_RX_ETH_BUFFER	8
+#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+
+#	define CONFIG_SYS_FEC0_PINMUX	0
+#	define CONFIG_SYS_FEC1_PINMUX	0
+#	define CONFIG_SYS_FEC0_MIIBASE	CONFIG_SYS_FEC0_IOBASE
+#	define CONFIG_SYS_FEC1_MIIBASE	CONFIG_SYS_FEC0_IOBASE
+#	define MCFFEC_TOUT_LOOP 50000
+#	define CONFIG_HAS_ETH1
+
+#	define CONFIG_BOOTDELAY	1	/* autoboot after 5 seconds */
+#	define CONFIG_BOOTARGS		"root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)"
+#	define CONFIG_ETHADDR		00:e0:0c:bc:e5:60
+#	define CONFIG_ETH1ADDR		00:e0:0c:bc:e5:61
+#	define CONFIG_ETHPRIME		"FEC0"
+#	define CONFIG_IPADDR		192.162.1.2
+#	define CONFIG_NETMASK		255.255.255.0
+#	define CONFIG_SERVERIP		192.162.1.1
+#	define CONFIG_GATEWAYIP		192.162.1.1
+#	define CONFIG_OVERWRITE_ETHADDR_ONCE
+
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+#	ifndef CONFIG_SYS_DISCOVER_PHY
+#		define FECDUPLEX	FULL
+#		define FECSPEED		_100BASET
+#	else
+#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#		endif
+#	endif			/* CONFIG_SYS_DISCOVER_PHY */
+#endif
+
+#define CONFIG_HOSTNAME		M54455EVB
+#ifdef CONFIG_SYS_STMICRO_BOOT
+/* ST Micro serial flash */
+#define	CONFIG_SYS_LOAD_ADDR2		0x40010013
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"netdev=eth0\0"				\
+	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
+	"loadaddr=0x40010000\0"			\
+	"sbfhdr=sbfhdr.bin\0"			\
+	"uboot=u-boot.bin\0"			\
+	"load=tftp ${loadaddr} ${sbfhdr};"	\
+	"tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0"	\
+	"upd=run load; run prog\0"		\
+	"prog=sf probe 0:1 1000000 3;"		\
+	"sf erase 0 30000;"			\
+	"sf write ${loadaddr} 0 0x30000;"	\
+	"save\0"				\
+	""
+#else
+/* Atmel and Intel */
+#ifdef CONFIG_SYS_ATMEL_BOOT
+#	define CONFIG_SYS_UBOOT_END	0x0403FFFF
+#elif defined(CONFIG_SYS_INTEL_BOOT)
+#	define CONFIG_SYS_UBOOT_END	0x3FFFF
+#endif
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"netdev=eth0\0"				\
+	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
+	"loadaddr=0x40010000\0"			\
+	"uboot=u-boot.bin\0"			\
+	"load=tftp ${loadaddr} ${uboot}\0"	\
+	"upd=run load; run prog\0"		\
+	"prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE)	\
+	" " __stringify(CONFIG_SYS_UBOOT_END) ";"		\
+	"era " __stringify(CONFIG_SYS_FLASH_BASE) " "		\
+	__stringify(CONFIG_SYS_UBOOT_END) ";"			\
+	"cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE)	\
+	" ${filesize}; save\0"			\
+	""
+#endif
+
+/* ATA configuration */
+#define CONFIG_ISO_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_IDE_RESET	1
+#define CONFIG_IDE_PREINIT	1
+#define CONFIG_ATAPI
+#undef CONFIG_LBA48
+
+#define CONFIG_SYS_IDE_MAXBUS		1
+#define CONFIG_SYS_IDE_MAXDEVICE	2
+
+#define CONFIG_SYS_ATA_BASE_ADDR	0x90000000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0
+
+#define CONFIG_SYS_ATA_DATA_OFFSET	0xA0	/* Offset for data I/O                            */
+#define CONFIG_SYS_ATA_REG_OFFSET	0xA0	/* Offset for normal register accesses */
+#define CONFIG_SYS_ATA_ALT_OFFSET	0xC0	/* Offset for alternate registers           */
+#define CONFIG_SYS_ATA_STRIDE		4	/* Interval between registers                 */
+
+/* Realtime clock */
+#define CONFIG_MCFRTC
+#undef RTC_DEBUG
+#define CONFIG_SYS_RTC_OSCILLATOR	(32 * CONFIG_SYS_HZ)
+
+/* Timer */
+#define CONFIG_MCFTMR
+#undef CONFIG_MCFPIT
+
+/* I2c */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	80000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x58000
+#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
+
+/* DSPI and Serial Flash */
+#define CONFIG_CF_SPI
+#define CONFIG_CF_DSPI
+#define CONFIG_HARD_SPI
+#define CONFIG_SYS_SBFHDR_SIZE		0x13
+#ifdef CONFIG_CMD_SPI
+#	define CONFIG_SPI_FLASH
+#	define CONFIG_SPI_FLASH_STMICRO
+
+#	define CONFIG_SYS_DSPI_CTAR0		(DSPI_CTAR_TRSZ(7) | \
+					 DSPI_CTAR_PCSSCK_1CLK | \
+					 DSPI_CTAR_PASC(0) | \
+					 DSPI_CTAR_PDT(0) | \
+					 DSPI_CTAR_CSSCK(0) | \
+					 DSPI_CTAR_ASC(0) | \
+					 DSPI_CTAR_DT(1))
+#endif
+
+/* PCI */
+#ifdef CONFIG_CMD_PCI
+#define CONFIG_PCI		1
+#define CONFIG_PCI_PNP		1
+#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1
+
+#define CONFIG_SYS_PCI_CACHE_LINE_SIZE	4
+
+#define CONFIG_SYS_PCI_MEM_BUS		0xA0000000
+#define CONFIG_SYS_PCI_MEM_PHYS	CONFIG_SYS_PCI_MEM_BUS
+#define CONFIG_SYS_PCI_MEM_SIZE	0x10000000
+
+#define CONFIG_SYS_PCI_IO_BUS		0xB1000000
+#define CONFIG_SYS_PCI_IO_PHYS		CONFIG_SYS_PCI_IO_BUS
+#define CONFIG_SYS_PCI_IO_SIZE		0x01000000
+
+#define CONFIG_SYS_PCI_CFG_BUS		0xB0000000
+#define CONFIG_SYS_PCI_CFG_PHYS	CONFIG_SYS_PCI_CFG_BUS
+#define CONFIG_SYS_PCI_CFG_SIZE	0x01000000
+#endif
+
+/* FPGA - Spartan 2 */
+/* experiment
+#define CONFIG_FPGA
+#define CONFIG_FPGA_COUNT	1
+#define CONFIG_SYS_FPGA_PROG_FEEDBACK
+#define CONFIG_SYS_FPGA_CHECK_CTRLC
+*/
+
+/* Input, PCI, Flexbus, and VCO */
+#define CONFIG_EXTRA_CLOCK
+
+#define CONFIG_PRAM		2048	/* 2048 KB */
+
+#define CONFIG_SYS_PROMPT		"-> "
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE			1024	/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE			256	/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
+
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x10000)
+
+#define CONFIG_SYS_MBAR		0xFC000000
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
+#define CONFIG_SYS_INIT_RAM_SIZE		0x8000	/* Size of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_CTRL	0x221
+#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+#define CONFIG_SYS_SBFHDR_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - 32)
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CONFIG_SYS_SDRAM_BASE1		0x48000000
+#define CONFIG_SYS_SDRAM_SIZE		256	/* SDRAM size in MB */
+#define CONFIG_SYS_SDRAM_CFG1		0x65311610
+#define CONFIG_SYS_SDRAM_CFG2		0x59670000
+#define CONFIG_SYS_SDRAM_CTRL		0xEA0B2000
+#define CONFIG_SYS_SDRAM_EMOD		0x40010000
+#define CONFIG_SYS_SDRAM_MODE		0x00010033
+#define CONFIG_SYS_SDRAM_DRV_STRENGTH	0xAA
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
+#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
+
+#ifdef CONFIG_CF_SBF
+#	define CONFIG_SERIAL_BOOT
+#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_TEXT_BASE + 0x400)
+#else
+#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
+#endif
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+
+/* Reserve 256 kB for malloc() */
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+
+/*
+ * Configuration for environment
+ * Environment is not embedded in u-boot. First time runing may have env
+ * crc error warning if there is no correct environment on the flash.
+ */
+#ifdef CONFIG_CF_SBF
+#	define CONFIG_ENV_IS_IN_SPI_FLASH
+#	define CONFIG_ENV_SPI_CS		1
+#else
+#	define CONFIG_ENV_IS_IN_FLASH	1
+#endif
+#undef CONFIG_ENV_OVERWRITE
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#ifdef CONFIG_SYS_STMICRO_BOOT
+#	define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
+#	define CONFIG_SYS_FLASH0_BASE		CONFIG_SYS_CS1_BASE
+#	define CONFIG_ENV_OFFSET		0x30000
+#	define CONFIG_ENV_SIZE		0x2000
+#	define CONFIG_ENV_SECT_SIZE	0x10000
+#endif
+#ifdef CONFIG_SYS_ATMEL_BOOT
+#	define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
+#	define CONFIG_SYS_FLASH0_BASE		CONFIG_SYS_CS0_BASE
+#	define CONFIG_SYS_FLASH1_BASE		CONFIG_SYS_CS1_BASE
+#	define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x40000)
+#	define CONFIG_ENV_SIZE		0x2000
+#	define CONFIG_ENV_SECT_SIZE	0x10000
+#endif
+#ifdef CONFIG_SYS_INTEL_BOOT
+#	define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
+#	define CONFIG_SYS_FLASH0_BASE		CONFIG_SYS_CS0_BASE
+#	define CONFIG_SYS_FLASH1_BASE		CONFIG_SYS_CS1_BASE
+#	define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x40000)
+#	define CONFIG_ENV_SIZE		0x2000
+#	define CONFIG_ENV_SECT_SIZE	0x20000
+#endif
+
+#define CONFIG_SYS_FLASH_CFI
+#ifdef CONFIG_SYS_FLASH_CFI
+
+#	define CONFIG_FLASH_CFI_DRIVER	1
+#	define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+#	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
+#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
+#	define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
+#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
+#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
+#	define CONFIG_SYS_FLASH_CHECKSUM
+#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
+#	define CONFIG_FLASH_CFI_LEGACY
+
+#ifdef CONFIG_FLASH_CFI_LEGACY
+#	define CONFIG_SYS_ATMEL_REGION		4
+#	define CONFIG_SYS_ATMEL_TOTALSECT	11
+#	define CONFIG_SYS_ATMEL_SECT		{1, 2, 1, 7}
+#	define CONFIG_SYS_ATMEL_SECTSZ		{0x4000, 0x2000, 0x8000, 0x10000}
+#endif
+#endif
+
+/*
+ * This is setting for JFFS2 support in u-boot.
+ * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
+ */
+#ifdef CONFIG_CMD_JFFS2
+#ifdef CF_STMICRO_BOOT
+#	define CONFIG_JFFS2_DEV		"nor1"
+#	define CONFIG_JFFS2_PART_SIZE	0x01000000
+#	define CONFIG_JFFS2_PART_OFFSET	(CONFIG_SYS_FLASH2_BASE + 0x500000)
+#endif
+#ifdef CONFIG_SYS_ATMEL_BOOT
+#	define CONFIG_JFFS2_DEV		"nor1"
+#	define CONFIG_JFFS2_PART_SIZE	0x01000000
+#	define CONFIG_JFFS2_PART_OFFSET	(CONFIG_SYS_FLASH1_BASE + 0x500000)
+#endif
+#ifdef CONFIG_SYS_INTEL_BOOT
+#	define CONFIG_JFFS2_DEV		"nor0"
+#	define CONFIG_JFFS2_PART_SIZE	(0x01000000 - 0x500000)
+#	define CONFIG_JFFS2_PART_OFFSET	(CONFIG_SYS_FLASH0_BASE + 0x500000)
+#endif
+#endif
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE		16
+
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_BCINVA + CF_CACR_ICINVA)
+#define CONFIG_SYS_DCACHE_INV		(CF_CACR_DCINVA)
+#define CONFIG_SYS_CACHE_ACR2		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_BEC | CF_CACR_IEC | \
+					 CF_CACR_ICINVA | CF_CACR_EUSP)
+#define CONFIG_SYS_CACHE_DCACR		((CONFIG_SYS_CACHE_ICACR | \
+					 CF_CACR_DEC | CF_CACR_DDCM_P | \
+					 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
+
+/*-----------------------------------------------------------------------
+ * Memory bank definitions
+ */
+/*
+ * CS0 - NOR Flash 1, 2, 4, or 8MB
+ * CS1 - CompactFlash and registers
+ * CS2 - CPLD
+ * CS3 - FPGA
+ * CS4 - Available
+ * CS5 - Available
+ */
+
+#if defined(CONFIG_SYS_ATMEL_BOOT) || defined(CONFIG_SYS_STMICRO_BOOT)
+ /* Atmel Flash */
+#define CONFIG_SYS_CS0_BASE		0x04000000
+#define CONFIG_SYS_CS0_MASK		0x00070001
+#define CONFIG_SYS_CS0_CTRL		0x00001140
+/* Intel Flash */
+#define CONFIG_SYS_CS1_BASE		0x00000000
+#define CONFIG_SYS_CS1_MASK		0x01FF0001
+#define CONFIG_SYS_CS1_CTRL		0x00000D60
+
+#define CONFIG_SYS_ATMEL_BASE		CONFIG_SYS_CS0_BASE
+#else
+/* Intel Flash */
+#define CONFIG_SYS_CS0_BASE		0x00000000
+#define CONFIG_SYS_CS0_MASK		0x01FF0001
+#define CONFIG_SYS_CS0_CTRL		0x00000D60
+ /* Atmel Flash */
+#define CONFIG_SYS_CS1_BASE		0x04000000
+#define CONFIG_SYS_CS1_MASK		0x00070001
+#define CONFIG_SYS_CS1_CTRL		0x00001140
+
+#define CONFIG_SYS_ATMEL_BASE		CONFIG_SYS_CS1_BASE
+#endif
+
+/* CPLD */
+#define CONFIG_SYS_CS2_BASE		0x08000000
+#define CONFIG_SYS_CS2_MASK		0x00070001
+#define CONFIG_SYS_CS2_CTRL		0x003f1140
+
+/* FPGA */
+#define CONFIG_SYS_CS3_BASE		0x09000000
+#define CONFIG_SYS_CS3_MASK		0x00070001
+#define CONFIG_SYS_CS3_CTRL		0x00000020
+
+#endif				/* _M54455EVB_H */
diff --git a/qemu/roms/u-boot/include/configs/M5475EVB.h b/qemu/roms/u-boot/include/configs/M5475EVB.h
new file mode 100644
index 000000000..e88a6bd8d
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/M5475EVB.h
@@ -0,0 +1,308 @@
+/*
+ * Configuation settings for the Freescale MCF5475 board.
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _M5475EVB_H
+#define _M5475EVB_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MCF547x_8x	/* define processor family */
+#define CONFIG_M547x		/* define processor type */
+#define CONFIG_M5475		/* define processor type */
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT		(0)
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_HW_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT	5000	/* timeout in milliseconds, max timeout is 6.71sec */
+
+/* Command line configuration */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#undef CONFIG_CMD_DATE
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_USB
+
+#define CONFIG_SLTTMR
+
+#define CONFIG_FSLDMAFEC
+#ifdef CONFIG_FSLDMAFEC
+#	define CONFIG_MII		1
+#	define CONFIG_MII_INIT		1
+#	define CONFIG_HAS_ETH1
+
+#	define CONFIG_SYS_DMA_USE_INTSRAM	1
+#	define CONFIG_SYS_DISCOVER_PHY
+#	define CONFIG_SYS_RX_ETH_BUFFER	32
+#	define CONFIG_SYS_TX_ETH_BUFFER	48
+#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+
+#	define CONFIG_SYS_FEC0_PINMUX		0
+#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
+#	define CONFIG_SYS_FEC1_PINMUX		0
+#	define CONFIG_SYS_FEC1_MIIBASE		CONFIG_SYS_FEC0_IOBASE
+
+#	define MCFFEC_TOUT_LOOP		50000
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+#	ifndef CONFIG_SYS_DISCOVER_PHY
+#		define FECDUPLEX	FULL
+#		define FECSPEED		_100BASET
+#	else
+#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#		endif
+#	endif			/* CONFIG_SYS_DISCOVER_PHY */
+
+#	define CONFIG_ETHADDR	00:e0:0c:bc:e5:60
+#	define CONFIG_ETH1ADDR	00:e0:0c:bc:e5:61
+#	define CONFIG_IPADDR	192.162.1.2
+#	define CONFIG_NETMASK	255.255.255.0
+#	define CONFIG_SERVERIP	192.162.1.1
+#	define CONFIG_GATEWAYIP	192.162.1.1
+#	define CONFIG_OVERWRITE_ETHADDR_ONCE
+
+#endif
+
+#ifdef CONFIG_CMD_USB
+#	define CONFIG_USB_OHCI_NEW
+#	define CONFIG_USB_STORAGE
+
+#	ifndef CONFIG_CMD_PCI
+#		define CONFIG_CMD_PCI
+#	endif
+#	define CONFIG_PCI_OHCI
+#	define CONFIG_DOS_PARTITION
+
+#	undef CONFIG_SYS_USB_OHCI_BOARD_INIT
+#	undef CONFIG_SYS_USB_OHCI_CPU_INIT
+#	define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
+#	define CONFIG_SYS_USB_OHCI_SLOT_NAME		"isp1561"
+#	define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
+#endif
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	80000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x00008F00
+#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
+
+/* PCI */
+#ifdef CONFIG_CMD_PCI
+#define CONFIG_PCI		1
+#define CONFIG_PCI_PNP		1
+#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1
+
+#define CONFIG_SYS_PCI_CACHE_LINE_SIZE	8
+
+#define CONFIG_SYS_PCI_MEM_BUS		0x80000000
+#define CONFIG_SYS_PCI_MEM_PHYS	CONFIG_SYS_PCI_MEM_BUS
+#define CONFIG_SYS_PCI_MEM_SIZE	0x10000000
+
+#define CONFIG_SYS_PCI_IO_BUS		0x71000000
+#define CONFIG_SYS_PCI_IO_PHYS		CONFIG_SYS_PCI_IO_BUS
+#define CONFIG_SYS_PCI_IO_SIZE		0x01000000
+
+#define CONFIG_SYS_PCI_CFG_BUS		0x70000000
+#define CONFIG_SYS_PCI_CFG_PHYS	CONFIG_SYS_PCI_CFG_BUS
+#define CONFIG_SYS_PCI_CFG_SIZE	0x01000000
+#endif
+
+#define CONFIG_BOOTDELAY	1	/* autoboot after 5 seconds */
+#define CONFIG_UDP_CHECKSUM
+
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_ETHADDR	00:e0:0c:bc:e5:60
+#	define CONFIG_IPADDR	192.162.1.2
+#	define CONFIG_NETMASK	255.255.255.0
+#	define CONFIG_SERVERIP	192.162.1.1
+#	define CONFIG_GATEWAYIP	192.162.1.1
+#	define CONFIG_OVERWRITE_ETHADDR_ONCE
+#endif				/* FEC_ENET */
+
+#define CONFIG_HOSTNAME		M547xEVB
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"netdev=eth0\0"				\
+	"loadaddr=10000\0"			\
+	"u-boot=u-boot.bin\0"			\
+	"load=tftp ${loadaddr) ${u-boot}\0"	\
+	"upd=run load; run prog\0"		\
+	"prog=prot off bank 1;"			\
+	"era ff800000 ff83ffff;"		\
+	"cp.b ${loadaddr} ff800000 ${filesize};"\
+	"save\0"				\
+	""
+
+#define CONFIG_PRAM		512	/* 512 KB */
+#define CONFIG_SYS_PROMPT		"-> "
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+
+#ifdef CONFIG_CMD_KGDB
+#	define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
+#else
+#	define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
+#endif
+
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
+#define CONFIG_SYS_LOAD_ADDR		0x00010000
+
+#define CONFIG_SYS_CLK			CONFIG_SYS_BUSCLK
+#define CONFIG_SYS_CPU_CLK		CONFIG_SYS_CLK * 2
+
+#define CONFIG_SYS_MBAR		0xF0000000
+#define CONFIG_SYS_INTSRAM		(CONFIG_SYS_MBAR + 0x10000)
+#define CONFIG_SYS_INTSRAMSZ		0x8000
+
+/*#define CONFIG_SYS_LATCH_ADDR		(CONFIG_SYS_CS1_BASE + 0x80000)*/
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0xF2000000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_CTRL	0x21
+#define CONFIG_SYS_INIT_RAM1_ADDR	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
+#define CONFIG_SYS_INIT_RAM1_END	0x1000	/* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM1_CTRL	0x21
+#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_CFG1		0x73711630
+#define CONFIG_SYS_SDRAM_CFG2		0x46770000
+#define CONFIG_SYS_SDRAM_CTRL		0xE10B0000
+#define CONFIG_SYS_SDRAM_EMOD		0x40010000
+#define CONFIG_SYS_SDRAM_MODE		0x018D0000
+#define CONFIG_SYS_SDRAM_DRVSTRENGTH	0x000002AA
+#ifdef CONFIG_SYS_DRAMSZ1
+#	define CONFIG_SYS_SDRAM_SIZE	(CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1)
+#else
+#	define CONFIG_SYS_SDRAM_SIZE	CONFIG_SYS_DRAMSZ
+#endif
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
+#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
+
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
+
+/* Reserve 256 kB for malloc() */
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_FLASH_CFI
+#ifdef CONFIG_SYS_FLASH_CFI
+#	define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CS0_BASE)
+#	define CONFIG_FLASH_CFI_DRIVER	1
+#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
+#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
+#	define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#ifdef CONFIG_SYS_NOR1SZ
+#	define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
+#	define CONFIG_SYS_FLASH_SIZE		((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20)
+#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
+#else
+#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#	define CONFIG_SYS_FLASH_SIZE		(CONFIG_SYS_BOOTSZ << 20)
+#endif
+#endif
+
+/* Configuration for environment
+ * Environment is not embedded in u-boot but at offset 0x40000 on the flash.
+ * First time runing may have env crc error warning if there is
+ * no correct environment on the flash.
+ */
+#define CONFIG_ENV_OFFSET		0x40000
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#define CONFIG_ENV_IS_IN_FLASH	1
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16
+
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_BCINVA + CF_CACR_ICINVA + \
+					 CF_CACR_IDCM)
+#define CONFIG_SYS_DCACHE_INV		(CF_CACR_DCINVA)
+#define CONFIG_SYS_CACHE_ACR2		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_BEC | CF_CACR_BCINVA | \
+					 CF_CACR_IEC | CF_CACR_ICINVA)
+#define CONFIG_SYS_CACHE_DCACR		((CONFIG_SYS_CACHE_ICACR | \
+					 CF_CACR_DEC | CF_CACR_DDCM_P | \
+					 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
+
+/*-----------------------------------------------------------------------
+ * Chipselect bank definitions
+ */
+/*
+ * CS0 - NOR Flash 1, 2, 4, or 8MB
+ * CS1 - NOR Flash
+ * CS2 - Available
+ * CS3 - Available
+ * CS4 - Available
+ * CS5 - Available
+ */
+#define CONFIG_SYS_CS0_BASE		0xFF800000
+#define CONFIG_SYS_CS0_MASK		(((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001)
+#define CONFIG_SYS_CS0_CTRL		0x00101980
+
+#ifdef CONFIG_SYS_NOR1SZ
+#define CONFIG_SYS_CS1_BASE		0xE0000000
+#define CONFIG_SYS_CS1_MASK		(((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001)
+#define CONFIG_SYS_CS1_CTRL		0x00101D80
+#endif
+
+#endif				/* _M5475EVB_H */
diff --git a/qemu/roms/u-boot/include/configs/M5485EVB.h b/qemu/roms/u-boot/include/configs/M5485EVB.h
new file mode 100644
index 000000000..e4128062a
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/M5485EVB.h
@@ -0,0 +1,293 @@
+/*
+ * Configuation settings for the Freescale MCF5485 FireEngine board.
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _M5485EVB_H
+#define _M5485EVB_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MCF547x_8x	/* define processor family */
+#define CONFIG_M548x		/* define processor type */
+#define CONFIG_M5485		/* define processor type */
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT		(0)
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_HW_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT	5000	/* timeout in milliseconds, max timeout is 6.71sec */
+
+/* Command line configuration */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#undef CONFIG_CMD_DATE
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_USB
+
+#define CONFIG_SLTTMR
+
+#define CONFIG_FSLDMAFEC
+#ifdef CONFIG_FSLDMAFEC
+#	define CONFIG_MII		1
+#	define CONFIG_MII_INIT		1
+#	define CONFIG_HAS_ETH1
+
+#	define CONFIG_SYS_DMA_USE_INTSRAM	1
+#	define CONFIG_SYS_DISCOVER_PHY
+#	define CONFIG_SYS_RX_ETH_BUFFER	32
+#	define CONFIG_SYS_TX_ETH_BUFFER	48
+#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+
+#	define CONFIG_SYS_FEC0_PINMUX		0
+#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
+#	define CONFIG_SYS_FEC1_PINMUX		0
+#	define CONFIG_SYS_FEC1_MIIBASE		CONFIG_SYS_FEC0_IOBASE
+
+#	define MCFFEC_TOUT_LOOP		50000
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+#	ifndef CONFIG_SYS_DISCOVER_PHY
+#		define FECDUPLEX	FULL
+#		define FECSPEED		_100BASET
+#	else
+#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#		endif
+#	endif			/* CONFIG_SYS_DISCOVER_PHY */
+
+#	define CONFIG_ETHADDR	00:e0:0c:bc:e5:60
+#	define CONFIG_ETH1ADDR	00:e0:0c:bc:e5:61
+#	define CONFIG_IPADDR	192.162.1.2
+#	define CONFIG_NETMASK	255.255.255.0
+#	define CONFIG_SERVERIP	192.162.1.1
+#	define CONFIG_GATEWAYIP	192.162.1.1
+#	define CONFIG_OVERWRITE_ETHADDR_ONCE
+
+#endif
+
+#ifdef CONFIG_CMD_USB
+#	define CONFIG_USB_STORAGE
+#	define CONFIG_DOS_PARTITION
+#	define CONFIG_USB_OHCI_NEW
+#	ifndef CONFIG_CMD_PCI
+#		define CONFIG_CMD_PCI
+#	endif
+/*#	define CONFIG_PCI_OHCI*/
+#	define CONFIG_SYS_USB_OHCI_REGS_BASE		0x80041000
+#	define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
+#	define CONFIG_SYS_USB_OHCI_SLOT_NAME		"isp1561"
+#	define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
+#endif
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	80000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x00008F00
+#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
+
+/* PCI */
+#ifdef CONFIG_CMD_PCI
+#define CONFIG_PCI		1
+#define CONFIG_PCI_PNP		1
+#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1
+
+#define CONFIG_SYS_PCI_MEM_BUS		0x80000000
+#define CONFIG_SYS_PCI_MEM_PHYS	CONFIG_SYS_PCI_MEM_BUS
+#define CONFIG_SYS_PCI_MEM_SIZE	0x10000000
+
+#define CONFIG_SYS_PCI_IO_BUS		0x71000000
+#define CONFIG_SYS_PCI_IO_PHYS		CONFIG_SYS_PCI_IO_BUS
+#define CONFIG_SYS_PCI_IO_SIZE		0x01000000
+
+#define CONFIG_SYS_PCI_CFG_BUS		0x70000000
+#define CONFIG_SYS_PCI_CFG_PHYS	CONFIG_SYS_PCI_CFG_BUS
+#define CONFIG_SYS_PCI_CFG_SIZE	0x01000000
+#endif
+
+#define CONFIG_BOOTDELAY	1	/* autoboot after 5 seconds */
+#define CONFIG_UDP_CHECKSUM
+
+#define CONFIG_HOSTNAME		M548xEVB
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"netdev=eth0\0"				\
+	"loadaddr=10000\0"			\
+	"u-boot=u-boot.bin\0"			\
+	"load=tftp ${loadaddr) ${u-boot}\0"	\
+	"upd=run load; run prog\0"		\
+	"prog=prot off bank 1;"			\
+	"era ff800000 ff83ffff;"		\
+	"cp.b ${loadaddr} ff800000 ${filesize};"\
+	"save\0"				\
+	""
+
+#define CONFIG_PRAM		512	/* 512 KB */
+#define CONFIG_SYS_PROMPT		"-> "
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+
+#ifdef CONFIG_CMD_KGDB
+#	define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
+#else
+#	define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
+#endif
+
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
+#define CONFIG_SYS_LOAD_ADDR		0x00010000
+
+#define CONFIG_SYS_CLK			CONFIG_SYS_BUSCLK
+#define CONFIG_SYS_CPU_CLK		CONFIG_SYS_CLK * 2
+
+#define CONFIG_SYS_MBAR		0xF0000000
+#define CONFIG_SYS_INTSRAM		(CONFIG_SYS_MBAR + 0x10000)
+#define CONFIG_SYS_INTSRAMSZ		0x8000
+
+/*#define CONFIG_SYS_LATCH_ADDR		(CONFIG_SYS_CS1_BASE + 0x80000)*/
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0xF2000000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_CTRL	0x21
+#define CONFIG_SYS_INIT_RAM1_ADDR	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
+#define CONFIG_SYS_INIT_RAM1_END	0x1000	/* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM1_CTRL	0x21
+#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_CFG1		0x73711630
+#define CONFIG_SYS_SDRAM_CFG2		0x46770000
+#define CONFIG_SYS_SDRAM_CTRL		0xE10B0000
+#define CONFIG_SYS_SDRAM_EMOD		0x40010000
+#define CONFIG_SYS_SDRAM_MODE		0x018D0000
+#define CONFIG_SYS_SDRAM_DRVSTRENGTH	0x000002AA
+#ifdef CONFIG_SYS_DRAMSZ1
+#	define CONFIG_SYS_SDRAM_SIZE	(CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1)
+#else
+#	define CONFIG_SYS_SDRAM_SIZE	CONFIG_SYS_DRAMSZ
+#endif
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
+#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
+
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
+
+/* Reserve 256 kB for malloc() */
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_FLASH_CFI
+#ifdef CONFIG_SYS_FLASH_CFI
+#	define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CS0_BASE)
+#	define CONFIG_FLASH_CFI_DRIVER	1
+#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
+#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
+#	define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#ifdef CONFIG_SYS_NOR1SZ
+#	define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
+#	define CONFIG_SYS_FLASH_SIZE		((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20)
+#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
+#else
+#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#	define CONFIG_SYS_FLASH_SIZE		(CONFIG_SYS_BOOTSZ << 20)
+#endif
+#endif
+
+/* Configuration for environment
+ * Environment is not embedded in u-boot. First time runing may have env
+ * crc error warning if there is no correct environment on the flash.
+ */
+#define CONFIG_ENV_OFFSET		0x40000
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#define CONFIG_ENV_IS_IN_FLASH	1
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16
+
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_BCINVA + CF_CACR_ICINVA + \
+					 CF_CACR_IDCM)
+#define CONFIG_SYS_DCACHE_INV		(CF_CACR_DCINVA)
+#define CONFIG_SYS_CACHE_ACR2		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_BEC | CF_CACR_BCINVA | \
+					 CF_CACR_IEC | CF_CACR_ICINVA)
+#define CONFIG_SYS_CACHE_DCACR		((CONFIG_SYS_CACHE_ICACR | \
+					 CF_CACR_DEC | CF_CACR_DDCM_P | \
+					 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
+
+/*-----------------------------------------------------------------------
+ * Chipselect bank definitions
+ */
+/*
+ * CS0 - NOR Flash 1, 2, 4, or 8MB
+ * CS1 - NOR Flash
+ * CS2 - Available
+ * CS3 - Available
+ * CS4 - Available
+ * CS5 - Available
+ */
+#define CONFIG_SYS_CS0_BASE		0xFF800000
+#define CONFIG_SYS_CS0_MASK		(((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001)
+#define CONFIG_SYS_CS0_CTRL		0x00101980
+
+#ifdef CONFIG_SYS_NOR1SZ
+#define CONFIG_SYS_CS1_BASE		0xE0000000
+#define CONFIG_SYS_CS1_MASK		(((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001)
+#define CONFIG_SYS_CS1_CTRL		0x00101D80
+#endif
+
+#endif				/* _M5485EVB_H */
diff --git a/qemu/roms/u-boot/include/configs/MERGERBOX.h b/qemu/roms/u-boot/include/configs/MERGERBOX.h
new file mode 100644
index 000000000..19ea3167a
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/MERGERBOX.h
@@ -0,0 +1,599 @@
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ *
+ * Copyright (C) 2011 Matrix Vision GmbH
+ * Andre Schwarz <andre.schwarz@matrix-vision.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <version.h>
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300	1
+#define CONFIG_MPC837x	1
+#define CONFIG_MPC8377	1
+
+#define CONFIG_SYS_TEXT_BASE	0xFC000000
+
+#define CONFIG_PCI	1
+#define CONFIG_PCI_INDIRECT_BRIDGE 1
+
+#define	CONFIG_MASK_AER_AO
+#define CONFIG_DISPLAY_AER_FULL
+
+#define CONFIG_MISC_INIT_R
+
+/*
+ * On-board devices
+ */
+#define CONFIG_TSEC_ENET
+
+/*
+ * System Clock Setup
+ */
+#define CONFIG_83XX_CLKIN	66666667 /* in Hz */
+#define CONFIG_PCIE
+#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES
+#define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN
+
+/*
+ * Hardware Reset Configuration Word stored in EEPROM.
+ */
+#define CONFIG_SYS_HRCW_LOW	0
+#define CONFIG_SYS_HRCW_HIGH	0
+
+/* Arbiter Configuration Register */
+#define CONFIG_SYS_ACR_PIPE_DEP	3
+#define CONFIG_SYS_ACR_RPTCNT	3
+
+/* System Priority Control Regsiter */
+#define CONFIG_SYS_SPCR_TSECEP	3
+
+/* System Clock Configuration Register */
+#define CONFIG_SYS_SCCR_TSEC1CM		3
+#define CONFIG_SYS_SCCR_TSEC2CM		0
+#define CONFIG_SYS_SCCR_SDHCCM		3
+#define CONFIG_SYS_SCCR_ENCCM		3 /* also clock for I2C-1 */
+#define CONFIG_SYS_SCCR_USBDRCM		CONFIG_SYS_SCCR_ENCCM /* must match */
+#define CONFIG_SYS_SCCR_PCIEXP1CM	3
+#define CONFIG_SYS_SCCR_PCIEXP2CM	3
+#define CONFIG_SYS_SCCR_PCICM		1
+#define CONFIG_SYS_SCCR_SATACM		0xFF
+
+/*
+ * System IO Config
+ */
+#define CONFIG_SYS_SICRH	0x087c0000
+#define CONFIG_SYS_SICRL	0x40000000
+
+/*
+ * Output Buffer Impedance
+ */
+#define CONFIG_SYS_OBIR		0x30000000
+
+/*
+ * IMMR new address
+ */
+#define CONFIG_SYS_IMMR		0xE0000000
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_DDR_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_83XX_DDR_USES_CS0
+
+#define CONFIG_SYS_DDRCDR_VALUE		(DDRCDR_EN | DDRCDR_PZ_HIZ |\
+					 DDRCDR_NZ_HIZ | DDRCDR_ODT |\
+					 DDRCDR_Q_DRN)
+
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+
+#define CONFIG_SYS_DDR_MODE_WEAK
+#define CONFIG_SYS_DDR_WRITE_DATA_DELAY	2
+#define CONFIG_SYS_DDR_CPO	0x1f
+
+/* SPD table located at offset 0x20 in extended adressing ROM
+ * used for HRCW fetch after power-on reset
+ */
+#define	CONFIG_SPD_EEPROM
+#define	SPD_EEPROM_ADDRESS	0x50
+#define	SPD_EEPROM_OFFSET	0x20
+#define	SPD_EEPROM_ADDR_LEN	2
+
+/*
+ * The reserved memory
+ */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(512*1024)
+#define CONFIG_SYS_MALLOC_LEN		(512*1024)
+
+/*
+ * Initial RAM Base Address Setup
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* End of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE -\
+					 GENERATED_GBL_DATA_SIZE)
+
+/*
+ * Local Bus Configuration & Clock Setup
+ */
+#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_8
+#define CONFIG_SYS_LBC_LBCR	0x00000000
+#define CONFIG_FSL_ELBC		1
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_FLASH_SIZE		64
+
+#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_64MB)
+
+#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE | BR_PS_16 |\
+				 BR_MS_GPCM | BR_V)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_FLASH_BASE | OR_UPM_XAM |\
+				 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 |\
+				 OR_GPCM_XACS | OR_GPCM_SCY_15 |\
+				 OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET |\
+				 OR_GPCM_EAD)
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	512
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500 /* Flash Write Timeout (ms) */
+
+/*
+ * NAND Flash on the Local Bus
+ */
+#define CONFIG_MTD_NAND_VERIFY_WRITE	1
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_NAND_FSL_ELBC		1
+
+#define CONFIG_SYS_NAND_BASE	0xE0600000
+#define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_NAND_BASE | BR_DECC_CHK_GEN |\
+				 BR_PS_8 | BR_MS_FCM | BR_V)
+#define CONFIG_SYS_OR1_PRELIM	(OR_AM_32KB | OR_FCM_BCTLD | OR_FCM_CST |\
+				 OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_RST |\
+				 OR_FCM_TRLX | OR_FCM_EHTR)
+
+#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_NAND_BASE
+#define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
+
+#define CONFIG_CONSOLE		ttyS0
+#define CONFIG_BAUDRATE		115200
+
+/* SERDES */
+#define CONFIG_FSL_SERDES
+#define CONFIG_FSL_SERDES1	0xe3000
+#define CONFIG_FSL_SERDES2	0xe3100
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+/* Pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCI_MEM_BASE		0x80000000
+#define CONFIG_SYS_PCI_MEM_PHYS		CONFIG_SYS_PCI_MEM_BASE
+#define CONFIG_SYS_PCI_MEM_SIZE		(256 << 20)
+#define CONFIG_SYS_PCI_MMIO_BASE	0x90000000
+#define CONFIG_SYS_PCI_MMIO_PHYS	CONFIG_SYS_PCI_MMIO_BASE
+#define CONFIG_SYS_PCI_MMIO_SIZE	(256 << 20)
+#define CONFIG_SYS_PCI_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI_IO_PHYS		0xE0300000
+#define CONFIG_SYS_PCI_IO_SIZE		(1 << 20)
+
+#ifdef CONFIG_PCIE
+#define CONFIG_SYS_PCIE1_BASE		0xA0000000
+#define CONFIG_SYS_PCIE1_CFG_BASE	0xA0000000
+#define CONFIG_SYS_PCIE1_CFG_SIZE	(128 << 20)
+#define CONFIG_SYS_PCIE1_MEM_BASE	0xA8000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xA8000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	(256 << 20)
+#define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xB8000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	(8 << 20)
+
+#define CONFIG_SYS_PCIE2_BASE		0xC0000000
+#define CONFIG_SYS_PCIE2_CFG_BASE	0xC0000000
+#define CONFIG_SYS_PCIE2_CFG_SIZE	(128 << 20)
+#define CONFIG_SYS_PCIE2_MEM_BASE	0xC8000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xC8000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE	(256 << 20)
+#define CONFIG_SYS_PCIE2_IO_BASE	0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xD8000000
+#define CONFIG_SYS_PCIE2_IO_SIZE	(8 << 20)
+#endif
+
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
+
+/*
+ * TSEC
+ */
+#define CONFIG_GMII			/* MII PHY management */
+#define CONFIG_SYS_VSC8601_SKEWFIX
+#define	CONFIG_SYS_VSC8601_SKEW_TX	3
+#define	CONFIG_SYS_VSC8601_SKEW_RX	3
+
+#define CONFIG_TSEC1
+#define CONFIG_HAS_ETH0
+#define CONFIG_TSEC1_NAME		"TSEC0"
+#define CONFIG_SYS_TSEC1_OFFSET		0x24000
+#define TSEC1_PHY_ADDR			0x10
+#define TSEC1_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC1_PHYIDX			0
+
+#define CONFIG_ETHPRIME			"TSEC0"
+#define CONFIG_HAS_ETH0
+
+/*
+ * SATA
+ */
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1_OFFSET	0x18000
+#define CONFIG_SYS_SATA1	(CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
+#define CONFIG_SYS_SATA1_FLAGS	FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2_OFFSET	0x19000
+#define CONFIG_SYS_SATA2	(CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
+#define CONFIG_SYS_SATA2_FLAGS	FLAGS_DMA
+
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_VENDOREX
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_NTPSERVER
+#define CONFIG_BOOTP_RANDOM_DELAY
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_LIB_RAND
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_SATA
+
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
+
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+
+#define CONFIG_FLASH_CFI_MTD
+#define MTDIDS_DEFAULT "nor0=NOR,nand0=NAND"
+#define MTDPARTS_DEFAULT "mtdparts=NOR:1M(u-boot),2M(FPGA);NAND:-(root)"
+
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	1
+
+#define CONFIG_CMDLINE_EDITING	1
+#define CONFIG_AUTO_COMPLETE
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_LOAD_ADDR	0x2000000
+#define CONFIG_LOADADDR		0x4000000
+#define CONFIG_SYS_CBSIZE	256
+
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+#define CONFIG_LOADS_ECHO		1
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1
+
+#define CONFIG_SYS_MEMTEST_START	(60<<20)
+#define CONFIG_SYS_MEMTEST_END		(70<<20)
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */
+
+/*
+ * Core HID Setup
+ */
+#define CONFIG_SYS_HID0_INIT	0x000000000
+#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
+				 HID0_ENABLE_INSTRUCTION_CACHE)
+#define CONFIG_SYS_HID2		HID2_HBE
+
+/*
+ * MMU Setup
+ */
+#define CONFIG_HIGH_BATS	1
+
+/* DDR: cache cacheable */
+#define CONFIG_SYS_SDRAM	CONFIG_SYS_SDRAM_BASE
+
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM | BATL_PP_RW |\
+				 BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM | BATU_BL_256M | BATU_VS |\
+				 BATU_VP)
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+
+/* unused */
+#define CONFIG_SYS_IBAT1L	(0)
+#define CONFIG_SYS_IBAT1U	(0)
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+
+/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_IMMR | BATL_PP_RW |\
+				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS |\
+				 BATU_VP)
+#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+
+/* unused */
+#define CONFIG_SYS_IBAT3L	(0)
+#define CONFIG_SYS_IBAT3U	(0)
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
+
+/* FLASH: icache cacheable, but dcache-inhibit and guarded */
+#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_FLASH_BASE | BATL_PP_RW |\
+				 BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_FLASH_BASE | BATU_BL_64M |\
+				 BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT4L	(CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
+				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
+
+/* Stack in dcache: cacheable, no memory coherence */
+#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
+#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K |\
+				 BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
+#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
+
+/* PCI MEM space: cacheable */
+#define CONFIG_SYS_IBAT6L	(CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_RW |\
+				 BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U	(CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M |\
+				 BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
+
+/* PCI MMIO space: cache-inhibit and guarded */
+#define CONFIG_SYS_IBAT7L	(CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_RW | \
+				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT7U	(CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M |\
+				 BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
+
+/*
+ * I2C EEPROM settings
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_EEPROM_SIZE			0x4000
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_ADDR		0xFFD00000
+#define CONFIG_ENV_SECT_SIZE	0x20000
+#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
+
+/*
+ * Video
+ */
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_SM501_PCI
+#define VIDEO_FB_LITTLE_ENDIAN
+#define CONFIG_CMD_BMP
+#define CONFIG_VIDEO_SM501
+#define CONFIG_VIDEO_SM501_32BPP
+#define CONFIG_VIDEO_SM501_FBMEM_OFFSET	0x10000
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(2 << 20)
+
+/*
+ * SPI
+ */
+#define CONFIG_MPC8XXX_SPI
+
+/*
+ * USB
+ */
+#define CONFIG_SYS_USB_HOST
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_HAS_FSL_DR_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_KEYBOARD
+/*
+ *
+ */
+#define CONFIG_BOOTDELAY	5
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_STOP_STR	"s"
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define CONFIG_RESET_TO_RETRY	1000
+
+#define MV_CI		"MergerBox"
+#define MV_VCI		"MergerBox"
+#define MV_FPGA_DATA	0xfc100000
+#define MV_FPGA_SIZE	0x00200000
+
+#define CONFIG_SHOW_BOOT_PROGRESS 1
+
+#define MV_KERNEL_ADDR_RAM	0x02800000
+#define MV_DTB_ADDR_RAM		0x00600000
+#define MV_INITRD_ADDR_RAM	0x01000000
+#define MV_FITADDR		0xfc300000
+#define	MV_SPLAH_ADDR		0xffe00000
+
+#define CONFIG_BOOTCOMMAND	"run i2c_init;if test ${boot_sqfs} -eq 1;"\
+				"then; run fitboot;else;run ubiboot;fi;"
+#define CONFIG_BOOTARGS		"console=ttyS0,115200n8"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"console_nr=0\0"\
+	"stdin=serial\0"\
+	"stdout=serial\0"\
+	"stderr=serial\0"\
+	"boot_sqfs=1\0"\
+	"usb_dr_mode=host\0"\
+	"bootfile=MergerBox.fit\0"\
+	"baudrate=" __stringify(CONFIG_BAUDRATE) "\0"\
+	"fpga=0\0"\
+	"fpgadata=" __stringify(MV_FPGA_DATA) "\0"\
+	"fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0"\
+	"mv_kernel_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0"\
+	"mv_initrd_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0"\
+	"mv_dtb_ram=" __stringify(MV_DTB_ADDR_RAM) "\0"\
+	"uboota=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"\
+	"fitaddr=" __stringify(MV_FITADDR) "\0"\
+	"mv_version=" U_BOOT_VERSION "\0"\
+	"mtdids=" MTDIDS_DEFAULT "\0"\
+	"mtdparts=" MTDPARTS_DEFAULT "\0"\
+	"dhcp_client_id=" MV_CI "\0"\
+	"dhcp_vendor-class-identifier=" MV_VCI "\0"\
+	"upd_uboot=dhcp;tftp bdi2000/u-boot-mergerbox-xp.bin;"\
+		"protect off all;erase $uboota +0xC0000;"\
+		"cp.b $loadaddr $uboota $filesize\0"\
+	"upd_fpga=dhcp;tftp MergerBox.rbf;erase $fpgadata +$fpgadatasize;"\
+		"cp.b $loadaddr $fpgadata $filesize\0"\
+	"upd_fit=dhcp;tftp MergerBox.fit;erase $fitaddr +0x1000000;"\
+		"cp.b $loadaddr $fitaddr $filesize\0"\
+	"addsqshrfs=set bootargs $bootargs root=/dev/ram ro "\
+		"rootfstype=squashfs\0"\
+	"addubirfs=set bootargs $bootargs ubi.mtd=9 root=ubi0:rootfs rw "\
+		"rootfstype=ubifs\0"\
+	"addusbrfs=set bootargs $bootargs root=/dev/sda1 rw "\
+		"rootfstype=ext3 usb-storage.delay_use=1 rootdelay=3\0"\
+	"netusbboot=bootp;run fpganetload fitnetload addusbrfs doboot\0"\
+	"netubiboot= bootp;run fpganetload fitnetload addubirfs doboot\0"\
+	"ubiboot=run fitprep addubirfs;set mv_initrd_ram -;run doboot\0"\
+	"doboot=bootm $mv_kernel_ram $mv_initrd_ram $mv_dtb_ram\0"\
+	"fitprep=imxtract $fitaddr kernel $mv_kernel_ram;"\
+		"imxtract $fitaddr ramdisk $mv_initrd_ram;"\
+		"imxtract $fitaddr fdt $mv_dtb_ram\0"\
+	"fdtprep=fdt addr $mv_dtb_ram;fdt boardsetup\0"\
+	"fitboot=run fitprep fdtprep addsqshrfs doboot\0"\
+	"i2c_init=run i2c_speed init_sdi_tx i2c_init_pll\0"\
+	"i2c_init_pll=i2c mw 65 9 2;i2c mw 65 9 0;i2c mw 65 5 2b;"\
+		"i2c mw 65 7 f;i2c mw 65 8 f;i2c mw 65 11 40;i2c mw 65 12 40;"\
+		"i2c mw 65 13 40; i2c mw 65 14 40; i2c mw 65 a 0\0"\
+	"i2c_speed=i2c dev 0;i2c speed 300000;i2c dev 1;i2c speed 120000\0"\
+	"init_sdi_tx=i2c mw 21 6 0;i2c mw 21 2 0;i2c mw 21 3 0;sleep 1;"\
+		"i2c mw 21 2 ff;i2c mw 21 3 3c\0"\
+	"splashimage=" __stringify(MV_SPLAH_ADDR) "\0"\
+	""
+
+/*
+ * FPGA
+ */
+#define CONFIG_FPGA_COUNT	1
+#define CONFIG_FPGA
+#define CONFIG_FPGA_ALTERA
+#define CONFIG_FPGA_CYCLON2
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/METROBOX.h b/qemu/roms/u-boot/include/configs/METROBOX.h
new file mode 100644
index 000000000..69ab5bb51
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/METROBOX.h
@@ -0,0 +1,349 @@
+/*
+ * (C) Copyright 2004 Sandburst Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/************************************************************************
+ * METROBOX.h - configuration Sandburst MetroBox
+ ***********************************************************************/
+
+/*
+ * $Id: METROBOX.h,v 1.21 2005/06/03 15:05:25 tsawyer Exp $
+ *
+ *
+ * $Log: METROBOX.h,v $
+ * Revision 1.21  2005/06/03 15:05:25  tsawyer
+ * MB rev 2.0.3 KA rev 0.0.7.  Add CONFIG_VERSION_VARIABLE, Add fakeled to MB
+ *
+ * Revision 1.20  2005/04/11 20:51:11  tsawyer
+ * fix ethernet
+ *
+ * Revision 1.19  2005/04/06 15:13:36  tsawyer
+ * Update appropriate files to coincide with u-boot 1.1.3
+ *
+ * Revision 1.18  2005/03/10 14:16:02  tsawyer
+ * add def'n for cis8201 short etch option.
+ *
+ * Revision 1.17  2005/03/09 19:49:51  tsawyer
+ * Remove KGDB to allow use of 2nd serial port
+ *
+ * Revision 1.16  2004/12/02 19:00:23  tsawyer
+ * Add misc_init_f to turn on i2c-1 and all four fans before sdram init
+ *
+ * Revision 1.15  2004/09/15 18:04:12  tsawyer
+ * add multiple serial port support
+ *
+ * Revision 1.14  2004/09/03 15:27:51  tsawyer
+ * All metrobox boards are at 66.66 sys clock
+ *
+ * Revision 1.13  2004/08/05 20:27:46  tsawyer
+ * Remove system ace definitions, add net console support
+ *
+ * Revision 1.12  2004/07/29 20:00:13  tsawyer
+ * Add i2c bus 1
+ *
+ * Revision 1.11  2004/07/21 13:44:18  tsawyer
+ * SystemACE is out, CF direct to local bus is in
+ *
+ * Revision 1.10  2004/06/29 19:08:55  tsawyer
+ * Add CONFIG_MISC_INIT_R
+ *
+ * Revision 1.9	 2004/06/28 21:30:53  tsawyer
+ * Fix default BOOTARGS
+ *
+ * Revision 1.8	 2004/06/17 15:51:08  tsawyer
+ * auto complete
+ *
+ * Revision 1.7	 2004/06/17 15:08:49  tsawyer
+ * Add autocomplete
+ *
+ * Revision 1.6	 2004/06/15 12:33:57  tsawyer
+ * debugging checkpoint
+ *
+ * Revision 1.5	 2004/06/12 19:48:28  tsawyer
+ * Debugging checkpoint
+ *
+ * Revision 1.4	 2004/06/02 13:03:06  tsawyer
+ * Fix eth addrs
+ *
+ * Revision 1.3	 2004/05/18 19:56:10  tsawyer
+ * Change default bootcommand to pImage.metrobox
+ *
+ * Revision 1.2	 2004/05/18 14:13:44  tsawyer
+ * Add bringup values for bootargs and bootcommand.
+ * Remove definition of ipaddress and serverip addresses.
+ *
+ * Revision 1.1	 2004/04/16 15:08:54  tsawyer
+ * Initial Revision
+ *
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_METROBOX		  1	     /* Board is Metrobox	*/
+#define CONFIG_440GX		  1	     /* Specifc GX support	*/
+#define CONFIG_440		  1	     /* ... PPC440 family	*/
+#define CONFIG_BOARD_EARLY_INIT_F 1	     /* Call board_pre_init	*/
+#define CONFIG_MISC_INIT_F	  1	     /* Call board misc_init_f	*/
+#define CONFIG_MISC_INIT_R	  1	     /* Call board misc_init_r	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFF80000
+
+#undef	CONFIG_SYS_DRAM_TEST			     /* Disable-takes long time!*/
+#define CONFIG_SYS_CLK_FREQ	  66666666   /* external freq to pll	*/
+
+#define CONFIG_VERY_BIG_RAM 1
+#define CONFIG_VERSION_VARIABLE
+
+#define CONFIG_IDENT_STRING " Sandburst Metrobox"
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_SDRAM_BASE	       0x00000000    /* _must_ be 0		*/
+#define CONFIG_SYS_FLASH_BASE	       0xfff80000    /* start of FLASH		*/
+#define CONFIG_SYS_MONITOR_BASE       0xfff80000    /* start of monitor	*/
+#define CONFIG_SYS_PCI_MEMBASE	       0x80000000    /* mapped pci memory	*/
+#define CONFIG_SYS_ISRAM_BASE	       0xc0000000    /* internal SRAM		*/
+#define CONFIG_SYS_PCI_BASE	       0xd0000000    /* internal PCI regs	*/
+
+#define CONFIG_SYS_NVRAM_BASE_ADDR   (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
+#define CONFIG_SYS_FPGA_BASE	      (CONFIG_SYS_PERIPHERAL_BASE + 0x08200000)
+#define CONFIG_SYS_BME32_BASE	      (CONFIG_SYS_PERIPHERAL_BASE + 0x08500000)
+#define CONFIG_SYS_GPIO_BASE	      (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in internal SRAM)
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_TEMP_STACK_OCM    1
+#define CONFIG_SYS_OCM_DATA_ADDR     CONFIG_SYS_ISRAM_BASE
+#define CONFIG_SYS_INIT_RAM_ADDR     CONFIG_SYS_ISRAM_BASE /* Initial RAM address	*/
+#define CONFIG_SYS_INIT_RAM_SIZE      0x2000	     /* Size of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET    (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
+
+#define CONFIG_SYS_MONITOR_LEN	      (256 * 1024)   /* Rsrv 256kB for Mon	*/
+#define CONFIG_SYS_MALLOC_LEN	      (128 * 1024)   /* Rsrv 128kB for malloc	*/
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+#define CONFIG_BAUDRATE	      9600
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * NVRAM/RTC
+ *
+ * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
+ * The DS1743 code assumes this condition (i.e. -- it assumes the base
+ * address for the RTC registers is:
+ *
+ *	CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE
+ *
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_NVRAM_SIZE	      (0x2000 - 8)   /* NVRAM size(8k)- RTC regs*/
+#define CONFIG_RTC_DS174x     1		     /* DS1743 RTC		*/
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_MAX_FLASH_BANKS   1		     /* number of banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT    8		     /* sectors per device	*/
+
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT  120000	     /* Flash Erase TO (in ms)	 */
+#define CONFIG_SYS_FLASH_WRITE_TOUT  500	     /* Flash Write TO(in ms)	 */
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CONFIG_SPD_EEPROM     1		     /* Use SPD EEPROM for setup*/
+#define SPD_EEPROM_ADDRESS    {0x53}	     /* SPD i2c spd addresses	*/
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
+#define CONFIG_SYS_I2C_PPC4XX_CH1
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_1 400000 /* I2C speed 400kHz */
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_1 0x7F
+#define CONFIG_SYS_I2C_NOPROBES { { 0, 0x69} } /* Don't probe these addrs */
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+#define CONFIG_ENV_IS_IN_NVRAM   1		     /* Environment uses NVRAM	*/
+#undef	CONFIG_ENV_IS_IN_FLASH		     /* ... not in flash	*/
+#undef	CONFIG_ENV_IS_IN_EEPROM		     /* ... not in EEPROM	*/
+#define CONFIG_ENV_OVERWRITE  1		     /* allow env overwrite	*/
+
+#define CONFIG_ENV_SIZE	      0x1000	     /* Size of Env vars	*/
+#define CONFIG_ENV_ADDR	      (CONFIG_SYS_NVRAM_BASE_ADDR)
+
+#define CONFIG_BOOTARGS	      "console=ttyS0,9600 root=/dev/nfs rw nfsroot=$serverip:/home/metrobox0 nfsaddrs=$ipaddr:::::eth0:none "
+#define CONFIG_BOOTCOMMAND    "tftp 8000000 pImage.metrobox;bootm 8000000"
+#define CONFIG_BOOTDELAY      5		    /* disable autoboot */
+
+#define CONFIG_LOADS_ECHO     1		     /* echo on for serial dnld */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE 1		     /* allow baudrate change	*/
+
+/*-----------------------------------------------------------------------
+ * Networking
+ *----------------------------------------------------------------------*/
+#define CONFIG_PPC4xx_EMAC
+#define CONFIG_MII	      1		     /* MII PHY management	*/
+#define CONFIG_PHY_ADDR	      0xff	     /* no phy on EMAC0		*/
+#define CONFIG_PHY1_ADDR      0xff	     /* no phy on EMAC1		*/
+#define CONFIG_PHY2_ADDR      0x08	     /* PHY addr, MGMT, EMAC2	*/
+#define CONFIG_PHY3_ADDR      0x18	     /* PHY addr, LCL, EMAC3	*/
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+#define CONFIG_HAS_ETH3
+#define CONFIG_PHY_RESET      1              /* reset phy upon startup  */
+#define CONFIG_CIS8201_PHY    1		     /* RGMII mode for Cicada	*/
+#define CONFIG_CIS8201_SHORT_ETCH 1	     /* Use short etch mode	*/
+#define CONFIG_PHY_GIGE	      1		     /* GbE speed/duplex detect */
+#define CONFIG_PHY_RESET_DELAY 1000
+#define CONFIG_NETMASK	      255.255.0.0
+#define CONFIG_ETHADDR	      00:00:00:00:00:00 /* No EMAC 0 support	*/
+#define CONFIG_ETH1ADDR	      00:00:00:00:00:00 /* No EMAC 1 support	*/
+#define CONFIG_SYS_RX_ETH_BUFFER     32	     /* #eth rx buff & descrs	*/
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FAT
+
+
+/* Include NetConsole support */
+#define CONFIG_NETCONSOLE
+
+/* Include auto complete with tabs */
+#define CONFIG_AUTO_COMPLETE 1
+#define CONFIG_AUTO_COMPLETE 1
+#define CONFIG_SYS_ALT_MEMTEST	     1	     /* use real memory test	 */
+
+#define CONFIG_SYS_LONGHELP			     /* undef to save memory	*/
+#define CONFIG_SYS_PROMPT	      "MetroBox=> "  /* Monitor Command Prompt	*/
+
+#define CONFIG_SYS_HUSH_PARSER	       1	     /* HUSH for ext'd cli	*/
+
+
+/*-----------------------------------------------------------------------
+ * Console Buffer
+ *----------------------------------------------------------------------*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	      1024	     /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	      256	     /* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+					     /* Print Buffer Size	*/
+#define CONFIG_SYS_MAXARGS	      16	     /* max number of cmd args	*/
+#define CONFIG_SYS_BARGSIZE	      CONFIG_SYS_CBSIZE     /* Boot Arg Buffer Size	*/
+
+/*-----------------------------------------------------------------------
+ * Memory Test
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_MEMTEST_START     0x0400000	     /* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END	      0x0C00000	     /* 4 ... 12 MB in DRAM	*/
+
+/*-----------------------------------------------------------------------
+ * Compact Flash (in true IDE mode)
+ *----------------------------------------------------------------------*/
+#undef	CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
+#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
+
+#define CONFIG_IDE_RESET		/* reset for ide supported	*/
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE busses	*/
+#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+
+#define CONFIG_SYS_ATA_BASE_ADDR	0xF0000000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	 /* Offset for data I/O */
+#define CONFIG_SYS_ATA_REG_OFFSET	0x0000	 /* Offset for normal register accesses*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x100000 /* Offset for alternate registers */
+
+#define CONFIG_SYS_ATA_STRIDE		2	 /* Directly connected CF, needs a stride
+					    to get to the correct offset */
+#define CONFIG_DOS_PARTITION  1		     /* Include dos partition	*/
+
+/*-----------------------------------------------------------------------
+ * PCI
+ *----------------------------------------------------------------------*/
+/* General PCI */
+#define CONFIG_PCI			     /* include pci support	*/
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_PNP			     /* do pci plug-and-play	*/
+#define CONFIG_PCI_SCAN_SHOW		     /* show pci devices	*/
+#define CONFIG_SYS_PCI_TARGBASE      (CONFIG_SYS_PCI_MEMBASE)
+
+/* Board-specific PCI */
+#define CONFIG_SYS_PCI_TARGET_INIT		     /* let board init pci target*/
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x17BA	     /* Sandburst */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	     /* Whatever */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE  230400	     /* kgdb serial port baud	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ *----------------------------------------------------------------------*/
+#undef CONFIG_WATCHDOG			     /* watchdog disabled	*/
+#define CONFIG_SYS_LOAD_ADDR	      0x8000000	     /* default load address	*/
+#define CONFIG_SYS_EXTBDINFO	      1		     /* use extended board_info */
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/MHPC.h b/qemu/roms/u-boot/include/configs/MHPC.h
new file mode 100644
index 000000000..6314b5380
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/MHPC.h
@@ -0,0 +1,369 @@
+/*
+ * (C) Copyright 2001
+ * Frank Gottschling, ELTEC Elektronik AG, fgottschling@eltec.de
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Configuation settings for the miniHiPerCam.
+ *
+ * -----------------------------------------------------------------
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MPC823		1	/* This is a MPC823 CPU		*/
+#define CONFIG_MHPC		1	/* on a miniHiPerCam		*/
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* do special hardware init.	*/
+#define CONFIG_MISC_INIT_R	1
+
+#define	CONFIG_SYS_TEXT_BASE	0xfe000000
+
+#define CONFIG_8xx_GCLK_FREQ	MPC8XX_SPEED
+#undef	CONFIG_8xx_CONS_SMC1
+#define CONFIG_8xx_CONS_SMC2	1	/* Console is on SMC2		*/
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+
+#define CONFIG_ENV_OVERWRITE	1
+#define CONFIG_ETHADDR		00:00:5b:ee:de:ad
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND	\
+	"bootp;"								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"	\
+	"bootm"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+#define CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+#undef	CONFIG_UCODE_PATCH
+
+/* enable I2C and select the hardware/software driver */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED	50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PB_SCL		0x00000020	/* PB 26 */
+#define PB_SDA		0x00000010	/* PB 27 */
+
+#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
+#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
+#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
+#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
+			else	immr->im_cpm.cp_pbdat &= ~PB_SDA
+#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
+			else	immr->im_cpm.cp_pbdat &= ~PB_SCL
+#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* EEPROM X24C04		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1	/* bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
+
+#define LCD_VIDEO_ADDR		(SDRAM_MAX_SIZE-SDRAM_RES_SIZE)
+#define LCD_VIDEO_SIZE		SDRAM_RES_SIZE	/* 2MB */
+#define LCD_VIDEO_COLS		640
+#define LCD_VIDEO_ROWS		480
+#define LCD_VIDEO_FG		255
+#define LCD_VIDEO_BG		0
+
+#undef	CONFIG_VIDEO				/* test only ! s.a devices.c and 8xx */
+#define CONFIG_CFB_CONSOLE			/* framebuffer console with std input */
+#define CONFIG_VIDEO_LOGO
+
+#define VIDEO_KBD_INIT_FCT	0		/* no KBD dev on MHPC - use serial */
+#define VIDEO_TSTC_FCT		serial_tstc
+#define VIDEO_GETC_FCT		serial_getc
+
+#define CONFIG_BR0_WORKAROUND	1
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_REGINFO
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x300000	/* default load address */
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Physical memory map
+ */
+#define CONFIG_SYS_IMMR		0xFFF00000 /* Internal Memory Mapped Register*/
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xfe000000
+
+#define CONFIG_SYS_MONITOR_LEN		0x40000		/* Reserve 256 kB for Monitor	*/
+#undef	CONFIG_SYS_MONITOR_BASE		    /* to run U-Boot from RAM */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_CMD_MTDPARTS
+#define CONFIG_JFFS2_DEV		"nor0"
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET	0x00000000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_CMD_MTDPARTS
+#define MTDIDS_DEFAULT		"nor0=mhpc-0"
+#define MTDPARTS_DEFAULT	"mtdparts=mhpc-0:-(jffs2)"
+*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map- for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_OFFSET		CONFIG_SYS_MONITOR_LEN /* Offset of Environment */
+#define CONFIG_ENV_SIZE		0x20000 /* Total Size of Environment	*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_SEME)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF | PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		12-18
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit - leave PLL multiplication factor unchanged !
+ */
+#define MPC8XX_SPEED	50000000L
+#define MPC8XX_XIN	5000000L      /* ref clk */
+#define MPC8XX_FACT	(MPC8XX_SPEED/MPC8XX_XIN)
+#define CONFIG_SYS_PLPRCR	(((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
+			PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+
+#define SCCR_MASK	(SCCR_RTDIV | SCCR_RTSEL)     /* SCCR_EBDF11 */
+#define CONFIG_SYS_SCCR	(SCCR_TBS | SCCR_DFLCD001)
+
+
+/*-----------------------------------------------------------------------
+ * MAMR settings for SDRAM	- 16-14
+ * => 0xC080200F
+ *-----------------------------------------------------------------------
+ * periodic timer for refresh
+ */
+#define CONFIG_SYS_MAMR_PTA	0xC0
+#define CONFIG_SYS_MAMR	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | MAMR_G0CLA_A11 | MAMR_TLFA_MSK)
+
+/*
+ * BR0 and OR0 (FLASH) used to re-map FLASH
+ */
+
+/* allow for max 8 MB of Flash */
+#define FLASH_BASE		0xFE000000	/* FLASH bank #0*/
+#define FLASH_BASE0_PRELIM	0xFE000000	/* FLASH bank #0*/
+#define CONFIG_SYS_REMAP_OR_AM		0xFF800000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xFF800000	/* OR addr mask */
+
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK) /* (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_6_CLK)*/
+
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V )
+
+/*
+ * BR1 and OR1 (SDRAM)
+ */
+#define SDRAM_BASE1_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_MAX_SIZE		0x01000000	/* max 16 MB		*/
+#define SDRAM_RES_SIZE		0x00200000	/* 2 MB for framebuffer */
+
+/* SDRAM timing: drive GPL5 high on first cycle */
+#define CONFIG_SYS_OR_TIMING_SDRAM	(OR_G5LS)
+
+#define CONFIG_SYS_OR1_PRELIM	((~(SDRAM_MAX_SIZE)+1)| CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR1_PRELIM	((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+/*
+ * BR2/OR2 - DIMM
+ */
+#define CONFIG_SYS_OR2		(OR_ACS_DIV4)
+#define CONFIG_SYS_BR2		(BR_MS_UPMA)
+
+/*
+ * BR3/OR3 - DIMM
+ */
+#define CONFIG_SYS_OR3		(OR_ACS_DIV4)
+#define CONFIG_SYS_BR3		(BR_MS_UPMA)
+
+/*
+ * BR4/OR4
+ */
+#define CONFIG_SYS_OR4		0
+#define CONFIG_SYS_BR4		0
+
+/*
+ * BR5/OR5
+ */
+#define CONFIG_SYS_OR5		0
+#define CONFIG_SYS_BR5		0
+
+/*
+ * BR6/OR6
+ */
+#define CONFIG_SYS_OR6		0
+#define CONFIG_SYS_BR6		0
+
+/*
+ * BR7/OR7
+ */
+#define CONFIG_SYS_OR7		0
+#define CONFIG_SYS_BR7		0
+
+
+/*-----------------------------------------------------------------------
+ * Debug Entry Mode
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_DER 0
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/MIP405.h b/qemu/roms/u-boot/include/configs/MIP405.h
new file mode 100644
index 000000000..68824fd2d
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/MIP405.h
@@ -0,0 +1,423 @@
+/*
+ * (C) Copyright 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/***********************************************************
+ * High Level Configuration Options
+ * (easy to change)
+ ***********************************************************/
+#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_MIP405		1	/* ...on a MIP405 board		*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFF80000
+
+/***********************************************************
+ * Note that it may also be a MIP405T board which is a subset of the
+ * MIP405
+ ***********************************************************/
+/***********************************************************
+ * WARNING:
+ * CONFIG_BOOT_PCI is only used for first boot-up and should
+ * NOT be enabled for production bootloader
+ ***********************************************************/
+/*#define        CONFIG_BOOT_PCI         1*/
+/***********************************************************
+ * Clock
+ ***********************************************************/
+#define CONFIG_SYS_CLK_FREQ	33000000 /* external frequency to pll   */
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_BSP
+
+#if !defined(CONFIG_MIP405T)
+    #define CONFIG_CMD_USB
+#endif
+
+
+#define	 CONFIG_SYS_HUSH_PARSER
+/**************************************************************
+ * I2C Stuff:
+ * the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address
+ * 0x53.
+ * The Atmel EEPROM uses 16Bit addressing.
+ ***************************************************************/
+
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		50000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x53	/* EEPROM 24C128/256		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"    */
+#undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6	/* The Atmel 24C128/256 has	*/
+					/* 64 byte page write mode using*/
+					/* last	6 bits of the address	*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+
+
+#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CONFIG_ENV_OFFSET		0x00000	/* environment starts at the beginning of the EEPROM */
+#define CONFIG_ENV_SIZE		0x00800	/* 2k bytes may be used for env vars */
+
+/***************************************************************
+ * Definitions for Serial Presence Detect EEPROM address
+ * (to get SDRAM settings)
+ ***************************************************************/
+/*#define SDRAM_EEPROM_WRITE_ADDRESS	0xA0
+#define SDRAM_EEPROM_READ_ADDRESS	0xA1
+*/
+/**************************************************************
+ * Environment definitions
+ **************************************************************/
+#define CONFIG_BAUDRATE		9600	/* STD Baudrate */
+#define CONFIG_BOOTDELAY	5
+/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
+/* #define CONFIG_BOOT_RETRY_TIME	-10	/XXX* feature is available but not enabled */
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check console even if bootdelay = 0 */
+
+#define CONFIG_BOOTCOMMAND	"diskboot 400000 0:1; bootm" /* autoboot command		*/
+#define CONFIG_BOOTARGS		"console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
+
+#define CONFIG_IPADDR		10.0.0.100
+#define CONFIG_SERVERIP		10.0.0.1
+#define CONFIG_PREBOOT
+/***************************************************************
+ * defines if the console is stored in the environment
+ ***************************************************************/
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	/* stdin, stdout and stderr are in evironment */
+/***************************************************************
+ * defines if an overwrite_console function exists
+ *************************************************************/
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+/***************************************************************
+ * defines if the overwrite_console should be stored in the
+ * environment
+ **************************************************************/
+#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+
+/**************************************************************
+ * loads config
+ *************************************************************/
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MISC_INIT_R
+/***********************************************************
+ * Miscellaneous configurable options
+ **********************************************************/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0100000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 1 ... 12 MB in DRAM	*/
+
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CONFIG_SYS_BASE_BAUD       916667
+
+/* The following table includes the supported baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CONFIG_SYS_LOAD_ADDR	0x400000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
+#define PCI_HOST_FORCE  1               /* configure as pci host        */
+#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_HOST PCI_HOST_FORCE	/* configure as pci-host	*/
+#define CONFIG_PCI_PNP			/* pci plug-and-play		*/
+					/* resource configuration	*/
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000	/* PCI Vendor ID: to-do!!!	*/
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000	/* PCI Device ID: to-do!!!	*/
+#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CONFIG_SYS_PCI_PTM1MS	0x80000001	/* 2GB, enable hard-wired to 1	*/
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CONFIG_SYS_PCI_PTM2LA	0x00000000	/* disabled			*/
+#define CONFIG_SYS_PCI_PTM2MS	0x00000000	/* disabled			*/
+#define CONFIG_SYS_PCI_PTM2PCI 0x00000000      /* Host: use this pci address   */
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFF80000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserve 1024 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_UPDATE_FLASH_SIZE
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+
+#define CONFIG_FLASH_SHOW_PROGRESS	45
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	256
+
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_CMD_MTDPARTS
+#define CONFIG_JFFS2_DEV		"nor0"
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET	0x00000000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_CMD_MTDPARTS
+#define MTDIDS_DEFAULT		"nor0=mip405-0"
+#define MTDPARTS_DEFAULT	"mtdparts=mip405-0:-(jffs2)"
+*/
+
+/*-----------------------------------------------------------------------
+ * Logbuffer Configuration
+ */
+#undef CONFIG_LOGBUFFER		/* supported but not enabled */
+/*-----------------------------------------------------------------------
+ * Bootcountlimit Configuration
+ */
+#undef CONFIG_BOOTCOUNT_LIMIT	/* supported but not enabled */
+
+/*-----------------------------------------------------------------------
+ * POST Configuration
+ */
+#if 0 /* enable this if POST is desired (is supported but not enabled) */
+#define CONFIG_POST		(CONFIG_SYS_POST_MEMORY	| \
+				 CONFIG_SYS_POST_CPU		| \
+				 CONFIG_SYS_POST_RTC		| \
+				 CONFIG_SYS_POST_I2C)
+
+#endif
+/*
+ * Init Memory Controller:
+ */
+#define FLASH_MAX_SIZE		0x00800000		/* 8MByte max */
+#define FLASH_BASE_PRELIM	0xFF800000  /* open the flash CS */
+/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
+#define FLASH_SIZE_PRELIM	 3  /* maximal flash FLASH size bank #0	*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1
+#define CONFIG_BOARD_EARLY_INIT_R
+
+/* Peripheral Bus Mapping */
+#define PER_PLD_ADDR		0xF4000000 /* smallest window is 1MByte 0x10 0000*/
+#define PER_UART0_ADDR		0xF4100000 /* smallest window is 1MByte 0x10 0000*/
+#define PER_UART1_ADDR		0xF4200000 /* smallest window is 1MByte 0x10 0000*/
+
+#define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
+#define CONFIG_PORT_ADDR	PER_PLD_ADDR + 5
+
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in On Chip SRAM)
+ */
+#define CONFIG_SYS_TEMP_STACK_OCM      1
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF0000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR	/* inside of On Chip SRAM    */
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE	/* Size of On Chip SRAM	       */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+/* reserve some memory for POST and BOOT limit info */
+#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 32)
+
+#ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */
+#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 12)
+#endif
+
+/***********************************************************************
+ * External peripheral base address
+ ***********************************************************************/
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000
+
+/***********************************************************************
+ * Last Stage Init
+ ***********************************************************************/
+#define CONFIG_LAST_STAGE_INIT
+/************************************************************
+ * Ethernet Stuff
+ ***********************************************************/
+#define CONFIG_PPC4xx_EMAC
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		1	/* PHY address			*/
+#define CONFIG_PHY_RESET_DELAY	300	/* Intel LXT971A needs this */
+#define CONFIG_PHY_CMD_DELAY	40	/* Intel LXT971A needs this */
+/************************************************************
+ * RTC
+ ***********************************************************/
+#define CONFIG_RTC_MC146818
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/************************************************************
+ * IDE/ATA stuff
+ ************************************************************/
+#if defined(CONFIG_MIP405T)
+#define CONFIG_SYS_IDE_MAXBUS		1   /* MIP405T has only one IDE bus	*/
+#else
+#define CONFIG_SYS_IDE_MAXBUS		2   /* max. 2 IDE busses	*/
+#endif
+
+#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
+
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x01F0		/* ide0 offste */
+#define CONFIG_SYS_ATA_IDE1_OFFSET	0x0170		/* ide1 offset */
+#define CONFIG_SYS_ATA_DATA_OFFSET	0		/* data reg offset	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	0		/* reg offset */
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x200		/* alternate register offset */
+
+#undef	CONFIG_IDE_8xx_DIRECT      /* no pcmcia interface required */
+#undef	CONFIG_IDE_LED	       /* no led for ide supported     */
+#define CONFIG_IDE_RESET       /* reset for ide supported...	*/
+#define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
+#define CONFIG_SUPPORT_VFAT
+/************************************************************
+ * ATAPI support (experimental)
+ ************************************************************/
+#define CONFIG_ATAPI			/* enable ATAPI Support */
+
+/************************************************************
+ * DISK Partition support
+ ************************************************************/
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION
+#define CONFIG_ISO_PARTITION /* Experimental */
+
+/************************************************************
+ * Keyboard support
+ ************************************************************/
+#undef CONFIG_ISA_KEYBOARD
+
+/************************************************************
+ * Video support
+ ************************************************************/
+#define CONFIG_VIDEO			/*To enable video controller support */
+#define CONFIG_VIDEO_CT69000
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_CONSOLE_EXTRA_INFO
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_VIDEO_SW_CURSOR
+#undef CONFIG_VIDEO_ONBOARD
+/************************************************************
+ * USB support EXPERIMENTAL
+ ************************************************************/
+#if !defined(CONFIG_MIP405T)
+#define CONFIG_USB_UHCI
+#define CONFIG_USB_KEYBOARD
+#define CONFIG_USB_STORAGE
+
+/* Enable needed helper functions */
+#define CONFIG_SYS_STDIO_DEREGISTER		/* needs stdio_deregister */
+#endif
+/************************************************************
+ * Debug support
+ ************************************************************/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/************************************************************
+ * support BZIP2 compression
+ ************************************************************/
+#define CONFIG_BZIP2		1
+
+/************************************************************
+ * Ident
+ ************************************************************/
+
+#define VERSION_TAG "released"
+#if !defined(CONFIG_MIP405T)
+#define CONFIG_ISO_STRING "MEV-10072-001"
+#else
+#define CONFIG_ISO_STRING "MEV-10082-001"
+#endif
+
+#if !defined(CONFIG_BOOT_PCI)
+#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
+#else
+#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, PCI_BOOT Version"
+#endif
+
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/MPC8260ADS.h b/qemu/roms/u-boot/include/configs/MPC8260ADS.h
new file mode 100644
index 000000000..39f7564b7
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/MPC8260ADS.h
@@ -0,0 +1,549 @@
+/*
+ * (C) Copyright 2001
+ * Stuart Hughes <stuarth@lineo.com>
+ * This file is based on similar values for other boards found in other
+ * U-Boot config files, and some that I found in the mpc8260ads manual.
+ *
+ * Note: my board is a PILOT rev.
+ * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address.
+ *
+ * (C) Copyright 2003-2004 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ * Added support for SDRAM DIMMs SPD EEPROM, MII, JFFS2.
+ * Ported to PQ2FADS-ZU and PQ2FADS-VR boards.
+ * Ported to MPC8272ADS board.
+ *
+ * Copyright (c) 2005 MontaVista Software, Inc.
+ * Vitaly Bordug <vbordug@ru.mvista.com>
+ * Added support for PCI bridge on MPC8272ADS
+ *
+ * Copyright (C) Freescale Semiconductor, Inc. 2006-2009.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC8260ADS	1	/* Motorola PQ2 ADS family board */
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xFFF00000	/* Standard: boot high */
+#endif
+
+#define CONFIG_CPM2		1	/* Has a CPM2 */
+
+/*
+ * Figure out if we are booting low via flash HRCW or high via the BCSR.
+ */
+#if (CONFIG_SYS_TEXT_BASE != 0xFFF00000)		/* Boot low (flash HRCW) */
+#   define CONFIG_SYS_LOWBOOT		1
+#endif
+
+/* ADS flavours */
+#define CONFIG_SYS_8260ADS		1	/* MPC8260ADS */
+#define CONFIG_SYS_8266ADS		2	/* MPC8266ADS */
+#define CONFIG_SYS_PQ2FADS		3	/* PQ2FADS-ZU or PQ2FADS-VR */
+#define CONFIG_SYS_8272ADS		4	/* MPC8272ADS */
+
+#ifndef CONFIG_ADSTYPE
+#define CONFIG_ADSTYPE		CONFIG_SYS_8260ADS
+#endif /* CONFIG_ADSTYPE */
+
+#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
+#define CONFIG_MPC8272		1
+#elif CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
+/*
+ * Actually MPC8275, but the code is littered with ifdefs that
+ * apply to both, or which use this ifdef to assume board-specific
+ * details. :-(
+ */
+#define CONFIG_MPC8272		1
+#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
+#define CONFIG_RESET_PHY_R	1	/* Call reset_phy()		*/
+
+/* allow serial and ethaddr to be overwritten */
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * select serial console configuration
+ *
+ * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ *
+ * if CONFIG_CONS_NONE is defined, then the serial console routines must
+ * defined elsewhere (for example, on the cogent platform, there are serial
+ * ports on the motherboard which are used for the serial console - see
+ * cogent/cma101/serial.[ch]).
+ */
+#undef	CONFIG_CONS_ON_SMC		/* define if console on SMC */
+#define CONFIG_CONS_ON_SCC		/* define if console on SCC */
+#undef	CONFIG_CONS_NONE		/* define if console on something else */
+#define CONFIG_CONS_INDEX	1	/* which serial channel for console */
+
+/*
+ * select ethernet configuration
+ *
+ * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
+ * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
+ * for FCC)
+ *
+ * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
+ */
+#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC   */
+#define CONFIG_ETHER_ON_FCC		/* define if ether on FCC   */
+#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
+
+#ifdef CONFIG_ETHER_ON_FCC
+
+#define CONFIG_ETHER_INDEX	2	/* which SCC/FCC channel for ethernet */
+
+#if   CONFIG_ETHER_INDEX == 1
+
+# define CONFIG_SYS_PHY_ADDR		0
+# define CONFIG_SYS_CMXFCR_VALUE1	(CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10)
+# define CONFIG_SYS_CMXFCR_MASK1	(CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
+
+#elif CONFIG_ETHER_INDEX == 2
+
+#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS	/* RxCLK is CLK15, TxCLK is CLK16 */
+# define CONFIG_SYS_PHY_ADDR		3
+# define CONFIG_SYS_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK16)
+#else					/* RxCLK is CLK13, TxCLK is CLK14 */
+# define CONFIG_SYS_PHY_ADDR		0
+# define CONFIG_SYS_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
+#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
+
+# define CONFIG_SYS_CMXFCR_MASK2	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+
+#endif	/* CONFIG_ETHER_INDEX */
+
+#define CONFIG_SYS_CPMFCR_RAMTYPE	0		/* BDs and buffers on 60x bus */
+#define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)  /* Full duplex */
+
+#define CONFIG_MII			/* MII PHY management		*/
+#define CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
+/*
+ * GPIO pins used for bit-banged MII communications
+ */
+#define MDIO_PORT	2		/* Port C */
+#define MDIO_DECLARE	volatile ioport_t *iop = ioport_addr ( \
+				(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
+#define MDC_DECLARE	MDIO_DECLARE
+
+#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
+#define CONFIG_SYS_MDIO_PIN	0x00002000	/* PC18 */
+#define CONFIG_SYS_MDC_PIN	0x00001000	/* PC19 */
+#else
+#define CONFIG_SYS_MDIO_PIN	0x00400000	/* PC9	*/
+#define CONFIG_SYS_MDC_PIN	0x00200000	/* PC10 */
+#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
+
+#define MDIO_ACTIVE	(iop->pdir |=  CONFIG_SYS_MDIO_PIN)
+#define MDIO_TRISTATE	(iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
+#define MDIO_READ	((iop->pdat &  CONFIG_SYS_MDIO_PIN) != 0)
+
+#define MDIO(bit)	if(bit) iop->pdat |=  CONFIG_SYS_MDIO_PIN; \
+			else	iop->pdat &= ~CONFIG_SYS_MDIO_PIN
+
+#define MDC(bit)	if(bit) iop->pdat |=  CONFIG_SYS_MDC_PIN; \
+			else	iop->pdat &= ~CONFIG_SYS_MDC_PIN
+
+#define MIIDELAY	udelay(1)
+
+#endif /* CONFIG_ETHER_ON_FCC */
+
+#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
+#undef CONFIG_SPD_EEPROM	/* On new boards, SDRAM is soldered */
+#else
+#define CONFIG_HARD_I2C		1	/* To enable I2C support	*/
+#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+
+#if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_SPD_ADDR)
+#define CONFIG_SPD_ADDR		0x50
+#endif
+#endif /* CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS */
+
+/*PCI*/
+#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
+#define CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_BOOTDELAY 0
+#define CONFIG_PCI_SCAN_SHOW
+#endif
+
+#ifndef CONFIG_SDRAM_PBI
+#define CONFIG_SDRAM_PBI	0 /* By default, use bank-based interleaving */
+#endif
+
+#ifndef CONFIG_8260_CLKIN
+#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
+#define CONFIG_8260_CLKIN	100000000	/* in Hz */
+#else
+#define CONFIG_8260_CLKIN	66000000	/* in Hz */
+#endif
+#endif
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#if defined(CONFIG_OF_LIBFDT)
+#define OF_TBCLK		(bd->bi_busfreq / 4)
+#endif
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_CDP
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_PORTIO
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_SDRAM
+
+#undef CONFIG_CMD_XIMG
+
+#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
+    #undef CONFIG_CMD_SDRAM
+    #undef CONFIG_CMD_I2C
+
+#elif CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
+    #undef CONFIG_CMD_SDRAM
+    #undef CONFIG_CMD_I2C
+
+#else
+    #undef CONFIG_CMD_PCI
+
+#endif /* CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS */
+
+
+#define CONFIG_BOOTDELAY	5		/* autoboot after 5 seconds */
+#define CONFIG_BOOTCOMMAND	"bootm fff80000"	/* autoboot command */
+#define CONFIG_BOOTARGS		"root=/dev/mtdblock2"
+
+#if defined(CONFIG_CMD_KGDB)
+#undef	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
+#define CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
+#undef	CONFIG_KGDB_NONE		/* define if kgdb on something else */
+#define CONFIG_KGDB_INDEX	2	/* which serial channel for kgdb */
+#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port at */
+#endif
+
+#define CONFIG_BZIP2	/* include support for bzip2 compressed images */
+#undef	CONFIG_WATCHDOG /* disable platform specific watchdog */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size  */
+#else
+#define CONFIG_SYS_CBSIZE	256			/* Console I/O Buffer Size  */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16			/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x400000	/* default load address */
+
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#define CONFIG_SYS_FLASH_BASE		0xff800000
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	32	/* max num of sects on one chip */
+#define CONFIG_SYS_FLASH_SIZE		8
+#define CONFIG_SYS_FLASH_ERASE_TOUT	8000	/* Timeout for Flash Erase (in ms)    */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	5	/* Timeout for Flash Write (in ms)    */
+#define CONFIG_SYS_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
+#define CONFIG_SYS_FLASH_PROTECTION		/* "Real" (hardware) sectors protection */
+
+/*
+ * JFFS2 partitions
+ *
+ * Note: fake mtd_id used, no linux mtd map file
+ */
+#define MTDIDS_DEFAULT		"nor0=mpc8260ads-0"
+#define MTDPARTS_DEFAULT	"mtdparts=mpc8260ads-0:-@1m(jffs2)"
+#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
+
+/* this is stuff came out of the Motorola docs */
+#ifndef CONFIG_SYS_LOWBOOT
+#define CONFIG_SYS_DEFAULT_IMMR	0x0F010000
+#endif
+
+#define CONFIG_SYS_IMMR		0xF0000000
+#define CONFIG_SYS_BCSR		0xF4500000
+#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
+#define CONFIG_SYS_PCI_INT		0xF8200000
+#endif
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_LSDRAM_BASE		0xFD000000
+
+#define RS232EN_1		0x02000002
+#define RS232EN_2		0x01000001
+#define FETHIEN1		0x08000008
+#define FETH1_RST		0x04000004
+#define FETHIEN2		0x10000000
+#define FETH2_RST		0x08000000
+#define BCSR_PCI_MODE		0x01000000
+
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#ifdef CONFIG_SYS_LOWBOOT
+/* PQ2FADS flash HRCW = 0x0EB4B645 */
+#define CONFIG_SYS_HRCW_MASTER (   ( HRCW_BPS11 | HRCW_CIP )			    |\
+			    ( HRCW_L2CPC10 | HRCW_DPPC11 | HRCW_ISB100 )    |\
+			    ( HRCW_BMS | HRCW_MMR11 | HRCW_LBPC01 | HRCW_APPC10 ) |\
+			    ( HRCW_CS10PC01 | HRCW_MODCK_H0101 )	     \
+			)
+#else
+/* PQ2FADS BCSR HRCW = 0x0CB23645 */
+#define CONFIG_SYS_HRCW_MASTER (   ( HRCW_BPS11 | HRCW_CIP )			    |\
+			    ( HRCW_L2CPC10 | HRCW_DPPC10 | HRCW_ISB010 )    |\
+			    ( HRCW_BMS | HRCW_APPC10 )			    |\
+			    ( HRCW_MODCK_H0101 )			     \
+			)
+#endif
+/* no slaves */
+#define CONFIG_SYS_HRCW_SLAVE1 0
+#define CONFIG_SYS_HRCW_SLAVE2 0
+#define CONFIG_SYS_HRCW_SLAVE3 0
+#define CONFIG_SYS_HRCW_SLAVE4 0
+#define CONFIG_SYS_HRCW_SLAVE5 0
+#define CONFIG_SYS_HRCW_SLAVE6 0
+#define CONFIG_SYS_HRCW_SLAVE7 0
+
+#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+#ifdef CONFIG_BZIP2
+#define CONFIG_SYS_MALLOC_LEN		(4096 << 10)	/* Reserve 4 MB for malloc()	*/
+#else
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 KB for malloc()	*/
+#endif /* CONFIG_BZIP2 */
+
+#ifndef CONFIG_SYS_RAMBOOT
+#  define CONFIG_ENV_IS_IN_FLASH	1
+#  define CONFIG_ENV_SECT_SIZE	0x40000
+#  define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_ENV_SECT_SIZE)
+#else
+#  define CONFIG_ENV_IS_IN_NVRAM	1
+#  define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
+#  define CONFIG_ENV_SIZE		0x200
+#endif /* CONFIG_SYS_RAMBOOT */
+
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPU */
+#if defined(CONFIG_CMD_KGDB)
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+#define CONFIG_SYS_HID0_INIT		0
+#define CONFIG_SYS_HID0_FINAL		(HID0_ICE | HID0_IFEM | HID0_ABE )
+
+#define CONFIG_SYS_HID2		0
+
+#define CONFIG_SYS_SYPCR		0xFFFFFFC3
+#define CONFIG_SYS_BCR			0x100C0000
+#define CONFIG_SYS_SIUMCR		0x0A200000
+#define CONFIG_SYS_SCCR		SCCR_DFBRG01
+#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | 0x00001801)
+#define CONFIG_SYS_OR0_PRELIM		0xFF800876
+#define CONFIG_SYS_BR1_PRELIM		(CONFIG_SYS_BCSR | 0x00001801)
+#define CONFIG_SYS_OR1_PRELIM		0xFFFF8010
+
+/*We need to configure chip select to use CPLD PCI IC on MPC8272ADS*/
+
+#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
+#define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_PCI_INT | 0x1801)	/* PCI interrupt controller */
+#define CONFIG_SYS_OR3_PRELIM	0xFFFF8010
+#elif CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
+#define CONFIG_SYS_BR8_PRELIM	(CONFIG_SYS_PCI_INT | 0x1801)	/* PCI interrupt controller */
+#define CONFIG_SYS_OR8_PRELIM	0xFFFF8010
+#endif
+
+#define CONFIG_SYS_RMR			RMR_CSRE
+#define CONFIG_SYS_TMCNTSC		(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+#define CONFIG_SYS_PISCR		(PISCR_PS|PISCR_PTF|PISCR_PTE)
+#define CONFIG_SYS_RCCR		0
+
+#if (CONFIG_ADSTYPE == CONFIG_SYS_8266ADS) || (CONFIG_ADSTYPE == CONFIG_SYS_8272ADS)
+#undef CONFIG_SYS_LSDRAM_BASE		/* No local bus SDRAM on these boards */
+#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8266ADS */
+
+#if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
+#define CONFIG_SYS_OR2			0xFE002EC0
+#define CONFIG_SYS_PSDMR		0x824B36A3
+#define CONFIG_SYS_PSRT		0x13
+#define CONFIG_SYS_LSDMR		0x828737A3
+#define CONFIG_SYS_LSRT		0x13
+#define CONFIG_SYS_MPTPR		0x2800
+#elif CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
+#define CONFIG_SYS_OR2			0xFC002CC0
+#define CONFIG_SYS_PSDMR		0x834E24A3
+#define CONFIG_SYS_PSRT		0x13
+#define CONFIG_SYS_MPTPR		0x2800
+#else
+#define CONFIG_SYS_OR2			0xFF000CA0
+#define CONFIG_SYS_PSDMR		0x016EB452
+#define CONFIG_SYS_PSRT		0x21
+#define CONFIG_SYS_LSDMR		0x0086A522
+#define CONFIG_SYS_LSRT		0x21
+#define CONFIG_SYS_MPTPR		0x1900
+#endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */
+
+#define CONFIG_SYS_RESET_ADDRESS	0x04400000
+
+#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
+
+/* PCI Memory map (if different from default map */
+#define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE		/* Local base */
+#define CONFIG_SYS_PCI_SLV_MEM_BUS		0x00000000		/* PCI base */
+#define CONFIG_SYS_PICMR0_MASK_ATTRIB	(PICMR_MASK_512MB | PICMR_ENABLE | \
+				 PICMR_PREFETCH_EN)
+
+/*
+ * These are the windows that allow the CPU to access PCI address space.
+ * All three PCI master windows, which allow the CPU to access PCI
+ * prefetch, non prefetch, and IO space (see below), must all fit within
+ * these windows.
+ */
+
+/*
+ * Master window that allows the CPU to access PCI Memory (prefetch).
+ * This window will be setup with the second set of Outbound ATU registers
+ * in the bridge.
+ */
+
+#define CONFIG_SYS_PCI_MSTR_MEM_LOCAL	0x80000000          /* Local base */
+#define CONFIG_SYS_PCI_MSTR_MEM_BUS	0x80000000          /* PCI base   */
+#define	CONFIG_SYS_CPU_PCI_MEM_START	PCI_MSTR_MEM_LOCAL
+#define CONFIG_SYS_PCI_MSTR_MEM_SIZE	0x20000000          /* 512MB */
+#define CONFIG_SYS_POCMR0_MASK_ATTRIB	(POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
+
+/*
+ * Master window that allows the CPU to access PCI Memory (non-prefetch).
+ * This window will be setup with the second set of Outbound ATU registers
+ * in the bridge.
+ */
+
+#define CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL    0xA0000000          /* Local base */
+#define CONFIG_SYS_PCI_MSTR_MEMIO_BUS      0xA0000000          /* PCI base   */
+#define CONFIG_SYS_CPU_PCI_MEMIO_START     PCI_MSTR_MEMIO_LOCAL
+#define CONFIG_SYS_PCI_MSTR_MEMIO_SIZE     0x20000000          /* 512MB */
+#define CONFIG_SYS_POCMR1_MASK_ATTRIB      (POCMR_MASK_512MB | POCMR_ENABLE)
+
+/*
+ * Master window that allows the CPU to access PCI IO space.
+ * This window will be setup with the first set of Outbound ATU registers
+ * in the bridge.
+ */
+
+#define CONFIG_SYS_PCI_MSTR_IO_LOCAL       0xF6000000          /* Local base */
+#define CONFIG_SYS_PCI_MSTR_IO_BUS         0x00000000          /* PCI base   */
+#define CONFIG_SYS_CPU_PCI_IO_START        PCI_MSTR_IO_LOCAL
+#define CONFIG_SYS_PCI_MSTR_IO_SIZE        0x02000000          /* 64MB */
+#define CONFIG_SYS_POCMR2_MASK_ATTRIB      (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO)
+
+
+/* PCIBR0 - for PCI IO*/
+#define CONFIG_SYS_PCI_MSTR0_LOCAL		CONFIG_SYS_PCI_MSTR_IO_LOCAL		/* Local base */
+#define CONFIG_SYS_PCIMSK0_MASK		~(CONFIG_SYS_PCI_MSTR_IO_SIZE - 1U)	/* Size of window */
+/* PCIBR1 - prefetch and non-prefetch regions joined together */
+#define CONFIG_SYS_PCI_MSTR1_LOCAL		CONFIG_SYS_PCI_MSTR_MEM_LOCAL
+#define CONFIG_SYS_PCIMSK1_MASK		~(CONFIG_SYS_PCI_MSTR_MEM_SIZE + CONFIG_SYS_PCI_MSTR_MEMIO_SIZE - 1U)
+
+#endif /* CONFIG_ADSTYPE == CONFIG_8272ADS*/
+
+#define CONFIG_HAS_ETH0
+
+#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
+#define CONFIG_HAS_ETH1
+#endif
+
+#define CONFIG_NETDEV eth0
+#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"netdev=" __stringify(CONFIG_NETDEV) "\0"			\
+	"tftpflash=tftpboot $loadaddr $uboot; "				\
+		"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
+			" +$filesize; "	\
+		"erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+		"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
+			" $filesize; "	\
+		"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
+			" +$filesize; "	\
+		"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
+			" $filesize\0"	\
+	"fdtaddr=400000\0"						\
+	"console=ttyCPM0\0"						\
+	"setbootargs=setenv bootargs "					\
+		"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
+	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath "	 \
+		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+		"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv rootdev /dev/nfs;"					\
+	"run setipargs;"						\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+	"setenv rootdev /dev/ram;"					\
+	"run setbootargs;"						\
+	"tftp $ramdiskaddr $ramdiskfile;"				\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/MPC8266ADS.h b/qemu/roms/u-boot/include/configs/MPC8266ADS.h
new file mode 100644
index 000000000..8d9c8fb45
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/MPC8266ADS.h
@@ -0,0 +1,563 @@
+/*
+ * (C) Copyright 2001
+ * Stuart Hughes <stuarth@lineo.com>
+ * This file is based on similar values for other boards found in other
+ * U-Boot config files, and some that I found in the mpc8260ads manual.
+ *
+ * Note: my board is a PILOT rev.
+ * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Config header file for a MPC8266ADS Pilot 16M Ram Simm, 8Mbytes Flash Simm
+ */
+
+/* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
+   !!								      !!
+   !!  This configuration requires JP3 to be in position 1-2 to work  !!
+   !!  To make it work for the default, the CONFIG_SYS_TEXT_BASE define in	      !!
+   !!  board/mpc8266ads/config.mk must be changed from 0xfe000000 to  !!
+   !!  0xfff00000						      !!
+   !!  The CONFIG_SYS_HRCW_MASTER define below must also be changed to match !!
+   !!								      !!
+   !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC8266ADS	1	/* ...on motorola ADS board	*/
+#define CONFIG_CPM2		1	/* Has a CPM2 */
+
+#define	CONFIG_SYS_TEXT_BASE	0xfe000000
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
+#define CONFIG_RESET_PHY_R	1	/* Call reset_phy()		*/
+
+/* allow serial and ethaddr to be overwritten */
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * select serial console configuration
+ *
+ * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ *
+ * if CONFIG_CONS_NONE is defined, then the serial console routines must
+ * defined elsewhere (for example, on the cogent platform, there are serial
+ * ports on the motherboard which are used for the serial console - see
+ * cogent/cma101/serial.[ch]).
+ */
+#undef	CONFIG_CONS_ON_SMC		/* define if console on SMC */
+#define CONFIG_CONS_ON_SCC		/* define if console on SCC */
+#undef	CONFIG_CONS_NONE		/* define if console on something else */
+#define CONFIG_CONS_INDEX	1	/* which serial channel for console */
+
+/*
+ * select ethernet configuration
+ *
+ * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
+ * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
+ * for FCC)
+ *
+ * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
+ */
+#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC   */
+#define CONFIG_ETHER_ON_FCC		/* define if ether on FCC   */
+#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
+#define CONFIG_ETHER_INDEX	2	/* which channel for ether  */
+#define CONFIG_MII			/* MII PHY management		*/
+#define CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
+/*
+ * Port pins used for bit-banged MII communictions (if applicable).
+ */
+#define MDIO_PORT	2	/* Port C */
+#define MDIO_DECLARE	volatile ioport_t *iop = ioport_addr ( \
+				(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
+#define MDC_DECLARE	MDIO_DECLARE
+
+#define MDIO_ACTIVE	(iop->pdir |=  0x00400000)
+#define MDIO_TRISTATE	(iop->pdir &= ~0x00400000)
+#define MDIO_READ	((iop->pdat &  0x00400000) != 0)
+
+#define MDIO(bit)	if(bit) iop->pdat |=  0x00400000; \
+			else	iop->pdat &= ~0x00400000
+
+#define MDC(bit)	if(bit) iop->pdat |=  0x00200000; \
+			else	iop->pdat &= ~0x00200000
+
+#define MIIDELAY	udelay(1)
+
+#if (CONFIG_ETHER_INDEX == 2)
+
+/*
+ * - Rx-CLK is CLK13
+ * - Tx-CLK is CLK14
+ * - Select bus for bd/buffers (see 28-13)
+ * - Half duplex
+ */
+# define CONFIG_SYS_CMXFCR_MASK2	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
+# define CONFIG_SYS_CPMFCR_RAMTYPE	0
+# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
+
+#endif	/* CONFIG_ETHER_INDEX */
+
+/* other options */
+#define CONFIG_HARD_I2C		1	/* To enable I2C support	*/
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+
+/* PCI */
+#define CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_BOOTDELAY 0
+#undef CONFIG_PCI_SCAN_SHOW
+
+/*-----------------------------------------------------------------------
+ * Definitions for Serial Presence Detect EEPROM address
+ * (to get SDRAM settings)
+ */
+#define SPD_EEPROM_ADDRESS	0x50
+
+#define CONFIG_8260_CLKIN	66000000	/* in Hz */
+#define CONFIG_BAUDRATE		115200
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+/* Commands we want, that are not part of default set */
+#define CONFIG_CMD_ASKENV	/* ask for env variable		*/
+#define CONFIG_CMD_CACHE	/* icache, dcache		*/
+#define CONFIG_CMD_DHCP		/* DHCP Support			*/
+#define CONFIG_CMD_DIAG		/* Diagnostics			*/
+#define CONFIG_CMD_IMMAP	/* IMMR dump support		*/
+#define CONFIG_CMD_IRQ		/* irqinfo			*/
+#define CONFIG_CMD_MII		/* MII support			*/
+#define CONFIG_CMD_PCI		/* pciinfo			*/
+#define CONFIG_CMD_PING		/* ping support			*/
+#define CONFIG_CMD_PORTIO	/* Port I/O			*/
+#define CONFIG_CMD_REGINFO	/* Register dump		*/
+#define CONFIG_CMD_SAVES	/* save S record dump		*/
+#define CONFIG_CMD_SDRAM	/* SDRAM DIMM SPD info printout */
+
+/* Commands from default set we don't need */
+#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
+#undef CONFIG_CMD_SETGETDCR	/* DCR support on 4xx		*/
+
+/* Define a command string that is automatically executed when no character
+ * is read on the console interface withing "Boot Delay" after reset.
+ */
+#undef	CONFIG_BOOT_ROOT_INITRD		/* Use ram disk for the root file system */
+#define CONFIG_BOOT_ROOT_NFS		/* Use a NFS mounted root file system */
+
+#ifdef CONFIG_BOOT_ROOT_INITRD
+#define CONFIG_BOOTCOMMAND \
+	"version;" \
+	"echo;" \
+	"bootp;" \
+	"setenv bootargs root=/dev/ram0 rw " \
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
+	"bootm"
+#endif /* CONFIG_BOOT_ROOT_INITRD */
+
+#ifdef CONFIG_BOOT_ROOT_NFS
+#define CONFIG_BOOTCOMMAND \
+	"version;" \
+	"echo;" \
+	"bootp;" \
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
+	"bootm"
+#endif /* CONFIG_BOOT_ROOT_NFS */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_DNS
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+
+#if defined(CONFIG_CMD_KGDB)
+#undef	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
+#define CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
+#undef	CONFIG_KGDB_NONE		/* define if kgdb on something else */
+#define CONFIG_KGDB_INDEX	2	/* which serial channel for kgdb */
+#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port at */
+#endif
+
+#undef	CONFIG_WATCHDOG			/* disable platform specific watchdog */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size  */
+#else
+#define CONFIG_SYS_CBSIZE	256			/* Console I/O Buffer Size  */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16			/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#undef CONFIG_CLOCKS_IN_MHZ		/* clocks passsed to Linux in MHz */
+					/* for versions < 2.4.5-pre5	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
+
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#define CONFIG_SYS_FLASH_BASE		0xFE000000
+#define FLASH_BASE		0xFE000000
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	32	/* max num of sects on one chip */
+#define CONFIG_SYS_FLASH_SIZE		8
+#define CONFIG_SYS_FLASH_ERASE_TOUT	8000	/* Timeout for Flash Erase (in ms)    */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	5	/* Timeout for Flash Write (in ms)    */
+
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+
+/* this is stuff came out of the Motorola docs */
+/* Only change this if you also change the Hardware configuration Word */
+#define CONFIG_SYS_DEFAULT_IMMR	0x0F010000
+
+/* Set IMMR to 0xF0000000 or above to boot Linux  */
+#define CONFIG_SYS_IMMR		0xF0000000
+#define CONFIG_SYS_BCSR		0xF8000000
+#define CONFIG_SYS_PCI_INT		0xF8200000	/* PCI interrupt controller */
+
+/* Define CONFIG_VERY_BIG_RAM to allow use of SDRAMs larger than 256MBytes
+ */
+/*#define CONFIG_VERY_BIG_RAM	1*/
+
+/* What should be the base address of SDRAM DIMM and how big is
+ * it (in Mbytes)?  This will normally auto-configure via the SPD.
+*/
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_SIZE 16
+
+#define SDRAM_SPD_ADDR 0x50
+
+/*-----------------------------------------------------------------------
+ * BR2,BR3 - Base Register
+ *     Ref: Section 10.3.1 on page 10-14
+ * OR2,OR3 - Option Register
+ *     Ref: Section 10.3.2 on page 10-16
+ *-----------------------------------------------------------------------
+ */
+
+/* Bank 2,3 - SDRAM DIMM
+ */
+
+/* The BR2 is configured as follows:
+ *
+ *     - Base address of 0x00000000
+ *     - 64 bit port size (60x bus only)
+ *     - Data errors checking is disabled
+ *     - Read and write access
+ *     - SDRAM 60x bus
+ *     - Access are handled by the memory controller according to MSEL
+ *     - Not used for atomic operations
+ *     - No data pipelining is done
+ *     - Valid
+ */
+#define CONFIG_SYS_BR2_PRELIM	((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
+			 BRx_PS_64			|\
+			 BRx_MS_SDRAM_P			|\
+			 BRx_V)
+
+#define CONFIG_SYS_BR3_PRELIM	((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
+			 BRx_PS_64			|\
+			 BRx_MS_SDRAM_P			|\
+			 BRx_V)
+
+/* With a 64 MB DIMM, the OR2 is configured as follows:
+ *
+ *     - 64 MB
+ *     - 4 internal banks per device
+ *     - Row start address bit is A8 with PSDMR[PBI] = 0
+ *     - 12 row address lines
+ *     - Back-to-back page mode
+ *     - Internal bank interleaving within save device enabled
+ */
+#if (CONFIG_SYS_SDRAM_SIZE == 64)
+#define CONFIG_SYS_OR2_PRELIM	(MEG_TO_AM(CONFIG_SYS_SDRAM_SIZE)	|\
+			 ORxS_BPD_4			|\
+			 ORxS_ROWST_PBI0_A8		|\
+			 ORxS_NUMR_12)
+#elif (CONFIG_SYS_SDRAM_SIZE == 16)
+#define CONFIG_SYS_OR2_PRELIM	(0xFF000C80)
+#else
+#error "INVALID SDRAM CONFIGURATION"
+#endif
+
+/*-----------------------------------------------------------------------
+ * PSDMR - 60x Bus SDRAM Mode Register
+ *     Ref: Section 10.3.3 on page 10-21
+ *-----------------------------------------------------------------------
+ */
+
+#if (CONFIG_SYS_SDRAM_SIZE == 64)
+/* With a 64 MB DIMM, the PSDMR is configured as follows:
+ *
+ *     - Bank Based Interleaving,
+ *     - Refresh Enable,
+ *     - Address Multiplexing where A5 is output on A14 pin
+ *	 (A6 on A15, and so on),
+ *     - use address pins A14-A16 as bank select,
+ *     - A9 is output on SDA10 during an ACTIVATE command,
+ *     - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
+ *     - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
+ *	 is 3 clocks,
+ *     - earliest timing for READ/WRITE command after ACTIVATE command is
+ *	 2 clocks,
+ *     - earliest timing for PRECHARGE after last data was read is 1 clock,
+ *     - earliest timing for PRECHARGE after last data was written is 1 clock,
+ *     - CAS Latency is 2.
+ */
+#define CONFIG_SYS_PSDMR	(PSDMR_RFEN	      |\
+			 PSDMR_SDAM_A14_IS_A5 |\
+			 PSDMR_BSMA_A14_A16   |\
+			 PSDMR_SDA10_PBI0_A9  |\
+			 PSDMR_RFRC_7_CLK     |\
+			 PSDMR_PRETOACT_3W    |\
+			 PSDMR_ACTTORW_2W     |\
+			 PSDMR_LDOTOPRE_1C    |\
+			 PSDMR_WRC_1C	      |\
+			 PSDMR_CL_2)
+#elif (CONFIG_SYS_SDRAM_SIZE == 16)
+/* With a 16 MB DIMM, the PSDMR is configured as follows:
+ *
+ *   configuration parameters found in Motorola documentation
+ */
+#define CONFIG_SYS_PSDMR	(0x016EB452)
+#else
+#error "INVALID SDRAM CONFIGURATION"
+#endif
+
+#define RS232EN_1		0x02000002
+#define RS232EN_2		0x01000001
+#define FETHIEN			0x08000008
+#define FETH_RST		0x04000004
+
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/* Use this HRCW for booting from address 0xfe00000 (JP3 in setting 1-2)  */
+/* 0x0EB2B645 */
+#define CONFIG_SYS_HRCW_MASTER (( HRCW_BPS11 | HRCW_CIP )				|\
+			 ( HRCW_L2CPC10 | HRCW_DPPC11 | HRCW_ISB010 )		|\
+			 ( HRCW_BMS | HRCW_MMR11 | HRCW_LBPC01 | HRCW_APPC10 )	|\
+			 ( HRCW_CS10PC01 | HRCW_MODCK_H0101 )			\
+			)
+
+/* Use this HRCW for booting from address 0xfff0000 (JP3 in setting 2-3)  */
+/* #define CONFIG_SYS_HRCW_MASTER 0x0cb23645 */
+
+/* This value should actually be situated in the first 256 bytes of the FLASH
+	which on the standard MPC8266ADS board is at address 0xFF800000
+	The linker script places it at 0xFFF00000 instead.
+
+	It still works, however, as long as the ADS board jumper JP3 is set to
+	position 2-3 so the board is using the BCSR as Hardware Configuration Word
+
+	If you want to use the one defined here instead, ust copy the first 256 bytes from
+	0xfff00000 to 0xff800000  (for 8MB flash)
+
+	- Rune
+
+*/
+
+/* no slaves */
+#define CONFIG_SYS_HRCW_SLAVE1 0
+#define CONFIG_SYS_HRCW_SLAVE2 0
+#define CONFIG_SYS_HRCW_SLAVE3 0
+#define CONFIG_SYS_HRCW_SLAVE4 0
+#define CONFIG_SYS_HRCW_SLAVE5 0
+#define CONFIG_SYS_HRCW_SLAVE6 0
+#define CONFIG_SYS_HRCW_SLAVE7 0
+
+#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+#ifndef CONFIG_SYS_RAMBOOT
+#  define CONFIG_ENV_IS_IN_FLASH	1
+#    define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE + 0x40000)
+#    define CONFIG_ENV_SECT_SIZE	0x40000
+#else
+#  define CONFIG_ENV_IS_IN_NVRAM	1
+#  define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
+#  define CONFIG_ENV_SIZE		0x200
+#endif /* CONFIG_SYS_RAMBOOT */
+
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPU */
+#if defined(CONFIG_CMD_KGDB)
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * HIDx - Hardware Implementation-dependent Registers			 2-11
+ *-----------------------------------------------------------------------
+ * HID0 also contains cache control - initially enable both caches and
+ * invalidate contents, then the final state leaves only the instruction
+ * cache enabled. Note that Power-On and Hard reset invalidate the caches,
+ * but Soft reset does not.
+ *
+ * HID1 has only read-only information - nothing to set.
+ */
+/*#define CONFIG_SYS_HID0_INIT		0 */
+#define CONFIG_SYS_HID0_INIT	(HID0_ICE  |\
+			 HID0_DCE  |\
+			 HID0_ICFI |\
+			 HID0_DCI  |\
+			 HID0_IFEM |\
+			 HID0_ABE)
+
+#define CONFIG_SYS_HID0_FINAL		(HID0_ICE | HID0_IFEM | HID0_ABE )
+
+#define CONFIG_SYS_HID2		0
+
+#define CONFIG_SYS_SYPCR		0xFFFFFFC3
+#define CONFIG_SYS_BCR			0x004C0000
+#define CONFIG_SYS_SIUMCR		0x4E64C000
+#define CONFIG_SYS_SCCR		0x00000000
+
+/*	local bus memory map
+ *
+ *	0x00000000-0x03FFFFFF	 64MB	SDRAM
+ *	0x80000000-0x9FFFFFFF	512MB	outbound prefetchable PCI memory window
+ *	0xA0000000-0xBFFFFFFF	512MB	outbound non-prefetchable PCI memory window
+ *	0xF0000000-0xF001FFFF	128KB	MPC8266 internal memory
+ *	0xF4000000-0xF7FFFFFF	 64MB	outbound PCI I/O window
+ *	0xF8000000-0xF8007FFF	 32KB	BCSR
+ *	0xF8100000-0xF8107FFF	 32KB	ATM UNI
+ *	0xF8200000-0xF8207FFF	 32KB	PCI interrupt controller
+ *	0xF8300000-0xF8307FFF	 32KB	EEPROM
+ *	0xFE000000-0xFFFFFFFF	 32MB	flash
+ */
+#define CONFIG_SYS_BR0_PRELIM	0xFE001801		/* flash */
+#define CONFIG_SYS_OR0_PRELIM	0xFE000836
+#define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_BCSR | 0x1801)	/* BCSR */
+#define CONFIG_SYS_OR1_PRELIM	0xFFFF8010
+#define CONFIG_SYS_BR4_PRELIM	0xF8300801		/* EEPROM */
+#define CONFIG_SYS_OR4_PRELIM	0xFFFF8846
+#define CONFIG_SYS_BR5_PRELIM	0xF8100801		/* PM5350 ATM UNI */
+#define CONFIG_SYS_OR5_PRELIM	0xFFFF8E36
+#define CONFIG_SYS_BR8_PRELIM	(CONFIG_SYS_PCI_INT | 0x1801)	/* PCI interrupt controller */
+#define CONFIG_SYS_OR8_PRELIM	0xFFFF8010
+
+#define CONFIG_SYS_RMR			0x0001
+#define CONFIG_SYS_TMCNTSC		(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+#define CONFIG_SYS_PISCR		(PISCR_PS|PISCR_PTF|PISCR_PTE)
+#define CONFIG_SYS_RCCR		0
+#define CONFIG_SYS_MPTPR		0x00001900
+#define CONFIG_SYS_PSRT		0x00000021
+
+/* This address must not exist */
+#define CONFIG_SYS_RESET_ADDRESS	0xFCFFFF00
+
+/* PCI Memory map (if different from default map */
+#define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE		/* Local base */
+#define CONFIG_SYS_PCI_SLV_MEM_BUS		0x00000000		/* PCI base */
+#define CONFIG_SYS_PICMR0_MASK_ATTRIB	(PICMR_MASK_512MB | PICMR_ENABLE | \
+				 PICMR_PREFETCH_EN)
+
+/*
+ * These are the windows that allow the CPU to access PCI address space.
+ * All three PCI master windows, which allow the CPU to access PCI
+ * prefetch, non prefetch, and IO space (see below), must all fit within
+ * these windows.
+ */
+
+/* PCIBR0 */
+#define CONFIG_SYS_PCI_MSTR0_LOCAL		0x80000000		/* Local base */
+#define CONFIG_SYS_PCIMSK0_MASK		PCIMSK_1GB		/* Size of window */
+/* PCIBR1 */
+#define CONFIG_SYS_PCI_MSTR1_LOCAL		0xF4000000		/* Local base */
+#define CONFIG_SYS_PCIMSK1_MASK		PCIMSK_64MB		/* Size of window */
+
+/*
+ * Master window that allows the CPU to access PCI Memory (prefetch).
+ * This window will be setup with the first set of Outbound ATU registers
+ * in the bridge.
+ */
+
+#define CONFIG_SYS_PCI_MSTR_MEM_LOCAL	0x80000000			/* Local base */
+#define CONFIG_SYS_PCI_MSTR_MEM_BUS	0x80000000			/* PCI base   */
+#define CONFIG_SYS_CPU_PCI_MEM_START	PCI_MSTR_MEM_LOCAL
+#define CONFIG_SYS_PCI_MSTR_MEM_SIZE	0x20000000			/* 512MB */
+#define CONFIG_SYS_POCMR0_MASK_ATTRIB	(POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
+
+/*
+ * Master window that allows the CPU to access PCI Memory (non-prefetch).
+ * This window will be setup with the second set of Outbound ATU registers
+ * in the bridge.
+ */
+
+#define CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL    0xA0000000			/* Local base */
+#define CONFIG_SYS_PCI_MSTR_MEMIO_BUS	    0xA0000000			/* PCI base   */
+#define CONFIG_SYS_CPU_PCI_MEMIO_START	    PCI_MSTR_MEMIO_LOCAL
+#define CONFIG_SYS_PCI_MSTR_MEMIO_SIZE	    0x20000000			/* 512MB */
+#define CONFIG_SYS_POCMR1_MASK_ATTRIB	    (POCMR_MASK_512MB | POCMR_ENABLE)
+
+/*
+ * Master window that allows the CPU to access PCI IO space.
+ * This window will be setup with the third set of Outbound ATU registers
+ * in the bridge.
+ */
+
+#define CONFIG_SYS_PCI_MSTR_IO_LOCAL	    0xF4000000			/* Local base */
+#define CONFIG_SYS_PCI_MSTR_IO_BUS	    0xF4000000			/* PCI base   */
+#define CONFIG_SYS_CPU_PCI_IO_START	    PCI_MSTR_IO_LOCAL
+#define CONFIG_SYS_PCI_MSTR_IO_SIZE	    0x04000000			/* 64MB */
+#define CONFIG_SYS_POCMR2_MASK_ATTRIB	    (POCMR_MASK_64MB | POCMR_ENABLE | POCMR_PCI_IO)
+
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_CMD_MTDPARTS
+#define CONFIG_JFFS2_DEV		"nor0"
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET	0x00000000
+
+/* mtdparts command line support */
+/*
+#define CONFIG_CMD_MTDPARTS
+#define MTDIDS_DEFAULT		""
+#define MTDPARTS_DEFAULT	""
+*/
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/MPC8308RDB.h b/qemu/roms/u-boot/include/configs/MPC8308RDB.h
new file mode 100644
index 000000000..bf974fd46
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/MPC8308RDB.h
@@ -0,0 +1,582 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
+ *
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1 /* E300 family */
+#define CONFIG_MPC830x		1 /* MPC830x family */
+#define CONFIG_MPC8308		1 /* MPC8308 CPU specific */
+#define CONFIG_MPC8308RDB	1 /* MPC8308RDB board specific */
+
+#define	CONFIG_SYS_TEXT_BASE	0xFE000000
+
+#define CONFIG_MISC_INIT_R
+
+/* new uImage format support */
+#define CONFIG_FIT			1
+#define CONFIG_FIT_VERBOSE		1
+
+#define CONFIG_MMC     1
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC83xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ESDHC_USE_PIO
+
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * On-board devices
+ *
+ * TSEC1 is SoC TSEC
+ * TSEC2 is VSC switch
+ */
+#define CONFIG_TSEC1
+#define CONFIG_VSC7385_ENET
+
+/*
+ * System Clock Setup
+ */
+#define CONFIG_83XX_CLKIN	33333333 /* in Hz */
+#define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN
+
+/*
+ * Hardware Reset Configuration Word
+ * if CLKIN is 66.66MHz, then
+ * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
+ * We choose the A type silicon as default, so the core is 400Mhz.
+ */
+#define CONFIG_SYS_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_2X1 |\
+	HRCWL_SVCOD_DIV_2 |\
+	HRCWL_CSB_TO_CLKIN_4X1 |\
+	HRCWL_CORE_TO_CSB_3X1)
+/*
+ * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
+ * in 8308's HRCWH according to the manual, but original Freescale's
+ * code has them and I've expirienced some problems using the board
+ * with BDI3000 attached when I've tried to set these bits to zero
+ * (UART doesn't work after the 'reset run' command).
+ */
+#define CONFIG_SYS_HRCW_HIGH (\
+	HRCWH_PCI_HOST |\
+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0X00000100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_RL_EXT_LEGACY |\
+	HRCWH_TSEC1M_IN_RGMII |\
+	HRCWH_TSEC2M_IN_RGMII |\
+	HRCWH_BIG_ENDIAN)
+
+/*
+ * System IO Config
+ */
+#define CONFIG_SYS_SICRH (\
+	SICRH_ESDHC_A_SD |\
+	SICRH_ESDHC_B_SD |\
+	SICRH_ESDHC_C_SD |\
+	SICRH_GPIO_A_TSEC2 |\
+	SICRH_GPIO_B_TSEC2_GTX_CLK125 |\
+	SICRH_IEEE1588_A_GPIO |\
+	SICRH_USB |\
+	SICRH_GTM_GPIO |\
+	SICRH_IEEE1588_B_GPIO |\
+	SICRH_ETSEC2_CRS |\
+	SICRH_GPIOSEL_1 |\
+	SICRH_TMROBI_V3P3 |\
+	SICRH_TSOBI1_V2P5 |\
+	SICRH_TSOBI2_V2P5)	/* 0x01b7d103 */
+#define CONFIG_SYS_SICRL (\
+	SICRL_SPI_PF0 |\
+	SICRL_UART_PF0 |\
+	SICRL_IRQ_PF0 |\
+	SICRL_I2C2_PF0 |\
+	SICRL_ETSEC1_GTX_CLK125)	/* 0x00000040 */
+
+/*
+ * IMMR new address
+ */
+#define CONFIG_SYS_IMMR		0xE0000000
+
+/*
+ * SERDES
+ */
+#define CONFIG_FSL_SERDES
+#define CONFIG_FSL_SERDES1	0xe3000
+
+/*
+ * Arbiter Setup
+ */
+#define CONFIG_SYS_ACR_PIPE_DEP	3 /* Arbiter pipeline depth is 4 */
+#define CONFIG_SYS_ACR_RPTCNT	3 /* Arbiter repeat count is 4 */
+#define CONFIG_SYS_SPCR_TSECEP	3 /* eTSEC emergency priority is highest */
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+#define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN \
+				| DDRCDR_PZ_LOZ \
+				| DDRCDR_NZ_LOZ \
+				| DDRCDR_ODT \
+				| DDRCDR_Q_DRN)
+				/* 0x7b880001 */
+/*
+ * Manually set up DDR parameters
+ * consist of two chips HY5PS12621BFP-C4 from HYNIX
+ */
+
+#define CONFIG_SYS_DDR_SIZE		128 /* MB */
+
+#define CONFIG_SYS_DDR_CS0_BNDS	0x00000007
+#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
+				| CSCONFIG_ODT_RD_NEVER \
+				| CSCONFIG_ODT_WR_ONLY_CURRENT \
+				| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
+				/* 0x80010102 */
+#define CONFIG_SYS_DDR_TIMING_3	0x00000000
+#define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
+				| (0 << TIMING_CFG0_WRT_SHIFT) \
+				| (0 << TIMING_CFG0_RRT_SHIFT) \
+				| (0 << TIMING_CFG0_WWT_SHIFT) \
+				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
+				| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
+				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
+				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
+				/* 0x00220802 */
+#define CONFIG_SYS_DDR_TIMING_1	((2 << TIMING_CFG1_PRETOACT_SHIFT) \
+				| (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
+				| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
+				| (5 << TIMING_CFG1_CASLAT_SHIFT) \
+				| (6 << TIMING_CFG1_REFREC_SHIFT) \
+				| (2 << TIMING_CFG1_WRREC_SHIFT) \
+				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
+				| (2 << TIMING_CFG1_WRTORD_SHIFT))
+				/* 0x27256222 */
+#define CONFIG_SYS_DDR_TIMING_2	((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
+				| (4 << TIMING_CFG2_CPO_SHIFT) \
+				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
+				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
+				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
+				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
+				| (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
+				/* 0x121048c5 */
+#define CONFIG_SYS_DDR_INTERVAL	((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
+				| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
+				/* 0x03600100 */
+#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
+				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
+				| SDRAM_CFG_DBW_32)
+				/* 0x43080000 */
+
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000 /* 1 posted refresh */
+#define CONFIG_SYS_DDR_MODE		((0x0448 << SDRAM_MODE_ESD_SHIFT) \
+				| (0x0232 << SDRAM_MODE_SD_SHIFT))
+				/* ODT 150ohm CL=3, AL=1 on SDRAM */
+#define CONFIG_SYS_DDR_MODE2		0x00000000
+
+/*
+ * Memory test
+ */
+#define CONFIG_SYS_MEMTEST_START	0x00001000 /* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x07f00000
+
+/*
+ * The reserved memory
+ */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE /* start of monitor */
+
+#define CONFIG_SYS_MONITOR_LEN	(384 * 1024) /* Reserve 384 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN	(512 * 1024) /* Reserved for malloc */
+
+/*
+ * Initial RAM Base Address Setup
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * Local Bus Configuration & Clock Setup
+ */
+#define CONFIG_SYS_LCRR_DBYP		LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_2
+#define CONFIG_SYS_LBC_LBCR		0x00040000
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
+#define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+
+#define CONFIG_SYS_FLASH_BASE		0xFE000000 /* FLASH base address */
+#define CONFIG_SYS_FLASH_SIZE		8 /* FLASH size is 8M */
+#define CONFIG_SYS_FLASH_PROTECTION	1 /* Use h/w Flash protection. */
+
+/* Window base at flash base */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_8MB)
+
+#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE \
+				| BR_PS_16	/* 16 bit port */ \
+				| BR_MS_GPCM	/* MSEL = GPCM */ \
+				| BR_V)		/* valid */
+#define CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+				| OR_UPM_XAM \
+				| OR_GPCM_CSNT \
+				| OR_GPCM_ACS_DIV2 \
+				| OR_GPCM_XACS \
+				| OR_GPCM_SCY_15 \
+				| OR_GPCM_TRLX_SET \
+				| OR_GPCM_EHTR_SET)
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
+/* 127 64KB sectors and 8 8KB top sectors per device */
+#define CONFIG_SYS_MAX_FLASH_SECT	135
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500 /* Flash Write Timeout (ms) */
+
+/*
+ * NAND Flash on the Local Bus
+ */
+#define CONFIG_SYS_NAND_BASE	0xE0600000		/* 0xE0600000 */
+#define CONFIG_SYS_NAND_WINDOW_SIZE	(32 * 1024)	/* 0x00008000 */
+#define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_NAND_BASE \
+				| BR_DECC_CHK_GEN	/* Use HW ECC */ \
+				| BR_PS_8		/* 8 bit Port */ \
+				| BR_MS_FCM		/* MSEL = FCM */ \
+				| BR_V)			/* valid */
+#define CONFIG_SYS_OR1_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
+				| OR_FCM_CSCT \
+				| OR_FCM_CST \
+				| OR_FCM_CHT \
+				| OR_FCM_SCY_1 \
+				| OR_FCM_TRLX \
+				| OR_FCM_EHTR)
+				/* 0xFFFF8396 */
+
+#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_NAND_BASE
+#define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)
+
+#ifdef CONFIG_VSC7385_ENET
+#define CONFIG_TSEC2
+					/* VSC7385 Base address on CS2 */
+#define CONFIG_SYS_VSC7385_BASE		0xF0000000
+#define CONFIG_SYS_VSC7385_SIZE		(128 * 1024) /* 0x00020000 */
+#define CONFIG_SYS_BR2_PRELIM		(CONFIG_SYS_VSC7385_BASE \
+					| BR_PS_8	/* 8-bit port */ \
+					| BR_MS_GPCM	/* MSEL = GPCM */ \
+					| BR_V)		/* valid */
+					/* 0xF0000801 */
+#define CONFIG_SYS_OR2_PRELIM		(P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
+					| OR_GPCM_CSNT \
+					| OR_GPCM_XACS \
+					| OR_GPCM_SCY_15 \
+					| OR_GPCM_SETA \
+					| OR_GPCM_TRLX_SET \
+					| OR_GPCM_EHTR_SET)
+					/* 0xFFFE09FF */
+/* Access window base at VSC7385 base */
+#define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_VSC7385_BASE
+/* Access window size 128K */
+#define CONFIG_SYS_LBLAWAR2_PRELIM	(LBLAWAR_EN | LBLAWAR_128KB)
+/* The flash address and size of the VSC7385 firmware image */
+#define CONFIG_VSC7385_IMAGE		0xFE7FE000
+#define CONFIG_VSC7385_IMAGE_SIZE	8192
+#endif
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+/* Pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x51} }
+
+/*
+ * SPI on header J8
+ *
+ * WARNING: enabling this will break TSEC2 (connected to the Vitesse switch)
+ * due to a pinmux conflict between GPIO9 (SPI chip select )and the TSEC2 pins.
+ */
+#ifdef CONFIG_MPC8XXX_SPI
+#define CONFIG_CMD_SPI
+#define CONFIG_USE_SPIFLASH
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_CMD_SF
+#endif
+
+/*
+ * Board info - revision and where boot from
+ */
+#define CONFIG_SYS_I2C_PCF8574A_ADDR	0x39
+
+/*
+ * Config on-board RTC
+ */
+#define CONFIG_RTC_DS1337	/* ds1339 on board, use ds1337 rtc via i2c */
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68 /* at address 0x68 */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCIE1_BASE		0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_BASE	0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000
+#define CONFIG_SYS_PCIE1_CFG_BASE	0xB0000000
+#define CONFIG_SYS_PCIE1_CFG_SIZE	0x01000000
+#define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xB1000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000
+
+/* enable PCIE clock */
+#define CONFIG_SYS_SCCR_PCIEXP1CM	1
+
+#define CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_PCIE
+
+#define CONFIG_PCI_PNP		/* do pci plug-and-play */
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
+#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
+
+/*
+ * TSEC
+ */
+#define CONFIG_TSEC_ENET	/* TSEC ethernet support */
+#define CONFIG_SYS_TSEC1_OFFSET	0x24000
+#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
+#define CONFIG_SYS_TSEC2_OFFSET	0x25000
+#define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
+
+/*
+ * TSEC ethernet configuration
+ */
+#define CONFIG_MII		1 /* MII PHY management */
+#define CONFIG_TSEC1_NAME	"eTSEC0"
+#define CONFIG_TSEC2_NAME	"eTSEC1"
+#define TSEC1_PHY_ADDR		2
+#define TSEC2_PHY_ADDR		1
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
+
+/* Options are: eTSEC[0-1] */
+#define CONFIG_ETHPRIME		"eTSEC0"
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + \
+				 CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SECT_SIZE	0x10000 /* 64K(one sector) for env */
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
+
+#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */
+
+/*
+ * Core HID Setup
+ */
+#define CONFIG_SYS_HID0_INIT	0x000000000
+#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
+				 HID0_ENABLE_INSTRUCTION_CACHE | \
+				 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
+#define CONFIG_SYS_HID2		HID2_HBE
+
+/*
+ * MMU Setup
+ */
+
+/* DDR: cache cacheable */
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
+					BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
+					BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+
+/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR | BATL_PP_RW | \
+			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
+					BATU_VP)
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+
+/* FLASH: icache cacheable, but dcache-inhibit and guarded */
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
+					BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
+					BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
+					BATL_CACHEINHIBIT | \
+					BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+
+/* Stack in dcache: cacheable, no memory coherence */
+#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
+#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
+					BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
+
+/*
+ * Environment Configuration
+ */
+
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#endif
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY	5	/* -1 disables auto-boot */
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"consoledev=ttyS0\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs}"				\
+		" console=${consoledev},${baudrate}\0"			\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
+	"addmisc=setenv bootargs ${bootargs}\0"				\
+	"kernel_addr=FE080000\0"					\
+	"fdt_addr=FE280000\0"						\
+	"ramdisk_addr=FE290000\0"					\
+	"u-boot=mpc8308rdb/u-boot.bin\0"				\
+	"kernel_addr_r=1000000\0"					\
+	"fdt_addr_r=C00000\0"						\
+	"hostname=mpc8308rdb\0"						\
+	"bootfile=mpc8308rdb/uImage\0"					\
+	"fdtfile=mpc8308rdb/mpc8308rdb.dtb\0"				\
+	"rootpath=/opt/eldk-4.2/ppc_6xx\0"				\
+	"flash_self=run ramargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
+	"flash_nfs=run nfsargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
+		"tftp ${fdt_addr_r} ${fdtfile};"			\
+		"run nfsargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
+	"bootcmd=run flash_self\0"					\
+	"load=tftp ${loadaddr} ${u-boot}\0"				\
+	"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)	\
+		" +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
+		" +${filesize};cp.b ${fileaddr} "			\
+		__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"	\
+	"upd=run load update\0"						\
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/MPC8313ERDB.h b/qemu/roms/u-boot/include/configs/MPC8313ERDB.h
new file mode 100644
index 000000000..69b2cb197
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/MPC8313ERDB.h
@@ -0,0 +1,720 @@
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/*
+ * mpc8313epb board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1
+#define CONFIG_MPC831x		1
+#define CONFIG_MPC8313		1
+#define CONFIG_MPC8313ERDB	1
+
+#ifdef CONFIG_NAND
+#define CONFIG_SPL
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
+
+#define CONFIG_SYS_TEXT_BASE	0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */
+#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
+#define CONFIG_SPL_MAX_SIZE	(4 * 1024)
+#define CONFIG_SPL_PAD_TO	0x4000
+
+#define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
+#define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
+#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
+#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
+#endif
+
+#endif /* CONFIG_NAND */
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xFE000000
+#endif
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+
+#define CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_FSL_ELBC 1
+
+#define CONFIG_MISC_INIT_R
+
+/*
+ * On-board devices
+ *
+ * TSEC1 is VSC switch
+ * TSEC2 is SoC TSEC
+ */
+#define CONFIG_VSC7385_ENET
+#define CONFIG_TSEC2
+
+#ifdef CONFIG_SYS_66MHZ
+#define CONFIG_83XX_CLKIN	66666667	/* in Hz */
+#elif defined(CONFIG_SYS_33MHZ)
+#define CONFIG_83XX_CLKIN	33333333	/* in Hz */
+#else
+#error Unknown oscillator frequency.
+#endif
+
+#define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN
+
+#define CONFIG_BOARD_EARLY_INIT_F		/* call board_early_init_f */
+#define CONFIG_BOARD_EARLY_INIT_R		/* call board_early_init_r */
+
+#define CONFIG_SYS_IMMR		0xE0000000
+
+#if defined(CONFIG_NAND) && !defined(CONFIG_SPL_BUILD)
+#define CONFIG_DEFAULT_IMMR	CONFIG_SYS_IMMR
+#endif
+
+#define CONFIG_SYS_MEMTEST_START	0x00001000
+#define CONFIG_SYS_MEMTEST_END		0x07f00000
+
+/* Early revs of this board will lock up hard when attempting
+ * to access the PMC registers, unless a JTAG debugger is
+ * connected, or some resistor modifications are made.
+ */
+#define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
+
+#define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
+#define CONFIG_SYS_ACR_RPTCNT		3	/* Arbiter repeat count (0-7) */
+
+/*
+ * Device configurations
+ */
+
+/* Vitesse 7385 */
+
+#ifdef CONFIG_VSC7385_ENET
+
+#define CONFIG_TSEC1
+
+/* The flash address and size of the VSC7385 firmware image */
+#define CONFIG_VSC7385_IMAGE		0xFE7FE000
+#define CONFIG_VSC7385_IMAGE_SIZE	8192
+
+#endif
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
+
+/*
+ * Manually set up DDR parameters, as this board does not
+ * seem to have the SPD connected to I2C.
+ */
+#define CONFIG_SYS_DDR_SIZE	128		/* MB */
+#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
+				| CSCONFIG_ODT_RD_NEVER \
+				| CSCONFIG_ODT_WR_ONLY_CURRENT \
+				| CSCONFIG_ROW_BIT_13 \
+				| CSCONFIG_COL_BIT_10)
+				/* 0x80010102 */
+
+#define CONFIG_SYS_DDR_TIMING_3	0x00000000
+#define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
+				| (0 << TIMING_CFG0_WRT_SHIFT) \
+				| (0 << TIMING_CFG0_RRT_SHIFT) \
+				| (0 << TIMING_CFG0_WWT_SHIFT) \
+				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
+				| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
+				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
+				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
+				/* 0x00220802 */
+#define CONFIG_SYS_DDR_TIMING_1	((3 << TIMING_CFG1_PRETOACT_SHIFT) \
+				| (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \
+				| (3 << TIMING_CFG1_ACTTORW_SHIFT) \
+				| (5 << TIMING_CFG1_CASLAT_SHIFT) \
+				| (10 << TIMING_CFG1_REFREC_SHIFT) \
+				| (3 << TIMING_CFG1_WRREC_SHIFT) \
+				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
+				| (2 << TIMING_CFG1_WRTORD_SHIFT))
+				/* 0x3835a322 */
+#define CONFIG_SYS_DDR_TIMING_2	((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
+				| (5 << TIMING_CFG2_CPO_SHIFT) \
+				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
+				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
+				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
+				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
+				| (6 << TIMING_CFG2_FOUR_ACT_SHIFT))
+				/* 0x129048c6 */ /* P9-45,may need tuning */
+#define CONFIG_SYS_DDR_INTERVAL	((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \
+				| (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
+				/* 0x05100500 */
+#if defined(CONFIG_DDR_2T_TIMING)
+#define CONFIG_SYS_SDRAM_CFG	(SDRAM_CFG_SREN \
+				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
+				| SDRAM_CFG_DBW_32 \
+				| SDRAM_CFG_2T_EN)
+				/* 0x43088000 */
+#else
+#define CONFIG_SYS_SDRAM_CFG	(SDRAM_CFG_SREN \
+				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
+				| SDRAM_CFG_DBW_32)
+				/* 0x43080000 */
+#endif
+#define CONFIG_SYS_SDRAM_CFG2		0x00401000
+/* set burst length to 8 for 32-bit data path */
+#define CONFIG_SYS_DDR_MODE	((0x4448 << SDRAM_MODE_ESD_SHIFT) \
+				| (0x0632 << SDRAM_MODE_SD_SHIFT))
+				/* 0x44480632 */
+#define CONFIG_SYS_DDR_MODE_2	0x8000C000
+
+#define CONFIG_SYS_DDR_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+				/*0x02000000*/
+#define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN \
+				| DDRCDR_PZ_NOMZ \
+				| DDRCDR_NZ_NOMZ \
+				| DDRCDR_M_ODR)
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
+#define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
+#define CONFIG_SYS_FLASH_BASE		0xFE000000	/* start of FLASH   */
+#define CONFIG_SYS_FLASH_SIZE		8	/* flash size in MB */
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* Use h/w Flash protection. */
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* display empty sectors */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	/* buffer up multiple bytes */
+
+#define CONFIG_SYS_NOR_BR_PRELIM	(CONFIG_SYS_FLASH_BASE \
+					| BR_PS_16	/* 16 bit port */ \
+					| BR_MS_GPCM	/* MSEL = GPCM */ \
+					| BR_V)		/* valid */
+#define CONFIG_SYS_NOR_OR_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+				| OR_GPCM_XACS \
+				| OR_GPCM_SCY_9 \
+				| OR_GPCM_EHTR \
+				| OR_GPCM_EAD)
+				/* 0xFF006FF7	TODO SLOW 16 MB flash size */
+					/* window base at flash base */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
+					/* 16 MB window size */
+#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_16MB)
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	135	/* sectors per device */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
+	!defined(CONFIG_SPL_BUILD)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000	/* Initial RAM addr */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in RAM*/
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
+#define CONFIG_SYS_MONITOR_LEN	(384 * 1024)	/* Reserve 384 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN	(512 * 1024)	/* Reserved for malloc */
+
+/*
+ * Local Bus LCRR and LBCR regs
+ */
+#define CONFIG_SYS_LCRR_EADC	LCRR_EADC_1
+#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_4
+#define CONFIG_SYS_LBC_LBCR	(0x00040000 /* TODO */ \
+				| (0xFF << LBCR_BMT_SHIFT) \
+				| 0xF)	/* 0x0004ff0f */
+
+				/* LB refresh timer prescal, 266MHz/32 */
+#define CONFIG_SYS_LBC_MRTPR	0x20000000  /*TODO */
+
+/* drivers/mtd/nand/nand.c */
+#if defined(CONFIG_NAND) && defined(CONFIG_SPL_BUILD)
+#define CONFIG_SYS_NAND_BASE		0xFFF00000
+#else
+#define CONFIG_SYS_NAND_BASE		0xE2800000
+#endif
+
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITION
+#define CONFIG_CMD_MTDPARTS
+#define MTDIDS_DEFAULT			"nand0=e2800000.flash"
+#define MTDPARTS_DEFAULT		\
+	"mtdparts=e2800000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)"
+
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND 1
+#define CONFIG_NAND_FSL_ELBC 1
+#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
+#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024)
+
+
+#define CONFIG_SYS_NAND_BR_PRELIM	(CONFIG_SYS_NAND_BASE \
+				| BR_DECC_CHK_GEN	/* Use HW ECC */ \
+				| BR_PS_8		/* 8 bit port */ \
+				| BR_MS_FCM		/* MSEL = FCM */ \
+				| BR_V)			/* valid */
+#define CONFIG_SYS_NAND_OR_PRELIM	\
+				(P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
+				| OR_FCM_CSCT \
+				| OR_FCM_CST \
+				| OR_FCM_CHT \
+				| OR_FCM_SCY_1 \
+				| OR_FCM_TRLX \
+				| OR_FCM_EHTR)
+				/* 0xFFFF8396 */
+
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
+#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
+#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM
+#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM
+#else
+#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
+#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
+#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
+#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
+#endif
+
+#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_NAND_BASE
+#define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)
+
+#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
+#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
+
+/* local bus write LED / read status buffer (BCSR) mapping */
+#define CONFIG_SYS_BCSR_ADDR		0xFA000000
+#define CONFIG_SYS_BCSR_SIZE		(32 * 1024)	/* 0x00008000 */
+					/* map at 0xFA000000 on LCS3 */
+#define CONFIG_SYS_BR3_PRELIM		(CONFIG_SYS_BCSR_ADDR \
+					| BR_PS_8	/* 8 bit port */ \
+					| BR_MS_GPCM	/* MSEL = GPCM */ \
+					| BR_V)		/* valid */
+					/* 0xFA000801 */
+#define CONFIG_SYS_OR3_PRELIM		(P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \
+					| OR_GPCM_CSNT \
+					| OR_GPCM_ACS_DIV2 \
+					| OR_GPCM_XACS \
+					| OR_GPCM_SCY_15 \
+					| OR_GPCM_TRLX_SET \
+					| OR_GPCM_EHTR_SET \
+					| OR_GPCM_EAD)
+					/* 0xFFFF8FF7 */
+#define CONFIG_SYS_LBLAWBAR3_PRELIM	CONFIG_SYS_BCSR_ADDR
+#define CONFIG_SYS_LBLAWAR3_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)
+
+/* Vitesse 7385 */
+
+#ifdef CONFIG_VSC7385_ENET
+
+					/* VSC7385 Base address on LCS2 */
+#define CONFIG_SYS_VSC7385_BASE		0xF0000000
+#define CONFIG_SYS_VSC7385_SIZE		(128 * 1024)	/* 0x00020000 */
+
+#define CONFIG_SYS_BR2_PRELIM		(CONFIG_SYS_VSC7385_BASE \
+					| BR_PS_8	/* 8 bit port */ \
+					| BR_MS_GPCM	/* MSEL = GPCM */ \
+					| BR_V)		/* valid */
+#define CONFIG_SYS_OR2_PRELIM		(P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
+					| OR_GPCM_CSNT \
+					| OR_GPCM_XACS \
+					| OR_GPCM_SCY_15 \
+					| OR_GPCM_SETA \
+					| OR_GPCM_TRLX_SET \
+					| OR_GPCM_EHTR_SET \
+					| OR_GPCM_EAD)
+					/* 0xFFFE09FF */
+
+					/* Access window base at VSC7385 base */
+#define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_VSC7385_BASE
+#define CONFIG_SYS_LBLAWAR2_PRELIM	(LBLAWAR_EN | LBLAWAR_128KB)
+
+#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+#define CONFIG_MPC83XX_GPIO 1
+#define CONFIG_CMD_GPIO 1
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
+#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE	0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS	0xE2000000
+#define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */
+
+#define CONFIG_PCI_PNP		/* do pci plug-and-play */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057	/* Motorola */
+
+/*
+ * TSEC
+ */
+#define CONFIG_TSEC_ENET		/* TSEC ethernet support */
+
+#define CONFIG_GMII			/* MII PHY management */
+
+#ifdef CONFIG_TSEC1
+#define CONFIG_HAS_ETH0
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_SYS_TSEC1_OFFSET	0x24000
+#define TSEC1_PHY_ADDR		0x1c
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC1_PHYIDX		0
+#endif
+
+#ifdef CONFIG_TSEC2
+#define CONFIG_HAS_ETH1
+#define CONFIG_TSEC2_NAME	"TSEC1"
+#define CONFIG_SYS_TSEC2_OFFSET	0x25000
+#define TSEC2_PHY_ADDR		4
+#define TSEC2_FLAGS		TSEC_GIGABIT
+#define TSEC2_PHYIDX		0
+#endif
+
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME			"TSEC1"
+
+/*
+ * Configure on-board RTC
+ */
+#define CONFIG_RTC_DS1337
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68
+
+/*
+ * Environment
+ */
+#if defined(CONFIG_NAND)
+	#define CONFIG_ENV_IS_IN_NAND	1
+	#define CONFIG_ENV_OFFSET		(512 * 1024)
+	#define CONFIG_ENV_SECT_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
+	#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
+	#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+	#define CONFIG_ENV_RANGE		(CONFIG_ENV_SECT_SIZE * 4)
+	#define CONFIG_ENV_OFFSET_REDUND	\
+					(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
+#elif !defined(CONFIG_SYS_RAMBOOT)
+	#define CONFIG_ENV_IS_IN_FLASH	1
+	#define CONFIG_ENV_ADDR		\
+			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+	#define CONFIG_ENV_SECT_SIZE	0x10000	/* 64K(one sector) for env */
+	#define CONFIG_ENV_SIZE		0x2000
+
+/* Address and size of Redundant Environment Sector */
+#else
+	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
+	#define CONFIG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_PCI
+
+#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND)
+    #undef CONFIG_CMD_SAVEENV
+    #undef CONFIG_CMD_LOADS
+#endif
+
+#define CONFIG_CMDLINE_EDITING 1
+#define CONFIG_AUTO_COMPLETE	/* add autocompletion support   */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+
+						/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE	\
+			(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+				/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+				/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)
+
+#define CONFIG_SYS_RCWH_PCIHOST 0x80000000	/* PCIHOST  */
+
+#ifdef CONFIG_SYS_66MHZ
+
+/* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */
+/* 0x62040000 */
+#define CONFIG_SYS_HRCW_LOW (\
+	0x20000000 /* reserved, must be set */ |\
+	HRCWL_DDRCM |\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_2X1 |\
+	HRCWL_CSB_TO_CLKIN_2X1 |\
+	HRCWL_CORE_TO_CSB_2X1)
+
+#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
+
+#elif defined(CONFIG_SYS_33MHZ)
+
+/* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */
+/* 0x65040000 */
+#define CONFIG_SYS_HRCW_LOW (\
+	0x20000000 /* reserved, must be set */ |\
+	HRCWL_DDRCM |\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_2X1 |\
+	HRCWL_CSB_TO_CLKIN_5X1 |\
+	HRCWL_CORE_TO_CSB_2X1)
+
+#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5)
+
+#endif
+
+#define CONFIG_SYS_HRCW_HIGH_BASE (\
+	HRCWH_PCI_HOST |\
+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_TSEC1M_IN_RGMII |\
+	HRCWH_TSEC2M_IN_RGMII |\
+	HRCWH_BIG_ENDIAN)
+
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
+		       HRCWH_FROM_0XFFF00100 |\
+		       HRCWH_ROM_LOC_NAND_SP_8BIT |\
+		       HRCWH_RL_EXT_NAND)
+#else
+#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
+		       HRCWH_FROM_0X00000100 |\
+		       HRCWH_ROM_LOC_LOCAL_16BIT |\
+		       HRCWH_RL_EXT_LEGACY)
+#endif
+
+/* System IO Config */
+#define CONFIG_SYS_SICRH	(SICRH_TSOBI1 | SICRH_TSOBI2)	/* RGMII */
+			/* Enable Internal USB Phy and GPIO on LCD Connector */
+#define CONFIG_SYS_SICRL	(SICRL_USBDR_10 | SICRL_LBC)
+
+#define CONFIG_SYS_HID0_INIT	0x000000000
+#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
+				 HID0_ENABLE_INSTRUCTION_CACHE | \
+				 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
+
+#define CONFIG_SYS_HID2 HID2_HBE
+
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
+/* DDR @ 0x00000000 */
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+
+/* PCI @ 0x80000000 */
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_PCI1_MEM_BASE \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_MMIO_BASE \
+				| BATL_PP_RW \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PCI1_MMIO_BASE \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+
+/* PCI2 not supported on 8313 */
+#define CONFIG_SYS_IBAT3L	(0)
+#define CONFIG_SYS_IBAT3U	(0)
+#define CONFIG_SYS_IBAT4L	(0)
+#define CONFIG_SYS_IBAT4U	(0)
+
+/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
+#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_IMMR \
+				| BATL_PP_RW \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_IMMR \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+
+/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
+#define CONFIG_SYS_IBAT6L	(0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT6U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT7L	(0)
+#define CONFIG_SYS_IBAT7U	(0)
+
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
+#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
+#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
+#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
+#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_NETDEV		"eth1"
+
+#define CONFIG_HOSTNAME		mpc8313erdb
+#define CONFIG_ROOTPATH		"/nfs/root/path"
+#define CONFIG_BOOTFILE		"uImage"
+				/* U-Boot image on TFTP server */
+#define CONFIG_UBOOTPATH	"u-boot.bin"
+#define CONFIG_FDTFILE		"mpc8313erdb.dtb"
+
+				/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		800000
+#define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"netdev=" CONFIG_NETDEV "\0"					\
+	"ethprime=TSEC1\0"						\
+	"uboot=" CONFIG_UBOOTPATH "\0"					\
+	"tftpflash=tftpboot $loadaddr $uboot; "				\
+		"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
+			" +$filesize; "	\
+		"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
+			" +$filesize; "	\
+		"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
+			" $filesize; "	\
+		"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
+			" +$filesize; "	\
+		"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
+			" $filesize\0"	\
+	"fdtaddr=780000\0"						\
+	"fdtfile=" CONFIG_FDTFILE "\0"					\
+	"console=ttyS0\0"						\
+	"setbootargs=setenv bootargs "					\
+		"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
+	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath "	 \
+		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
+							"$netdev:off " \
+		"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv rootdev /dev/nfs;"					\
+	"run setbootargs;"						\
+	"run setipargs;"						\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+	"setenv rootdev /dev/ram;"					\
+	"run setbootargs;"						\
+	"tftp $ramdiskaddr $ramdiskfile;"				\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/MPC8315ERDB.h b/qemu/roms/u-boot/include/configs/MPC8315ERDB.h
new file mode 100644
index 000000000..3dd52ce30
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/MPC8315ERDB.h
@@ -0,0 +1,687 @@
+/*
+ * Copyright (C) 2007-2010 Freescale Semiconductor, Inc.
+ *
+ * Dave Liu <daveliu@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
+#define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
+#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
+
+#ifdef CONFIG_NAND_U_BOOT
+#define CONFIG_SYS_TEXT_BASE	0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */
+#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
+#endif /* CONFIG_NAND_SPL */
+#endif /* CONFIG_NAND_U_BOOT */
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xFE000000
+#endif
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1 /* E300 family */
+#define CONFIG_MPC831x		1 /* MPC831x CPU family */
+#define CONFIG_MPC8315		1 /* MPC8315 CPU specific */
+#define CONFIG_MPC8315ERDB	1 /* MPC8315ERDB board specific */
+
+/*
+ * System Clock Setup
+ */
+#define CONFIG_83XX_CLKIN	66666667 /* in Hz */
+#define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN
+
+/*
+ * Hardware Reset Configuration Word
+ * if CLKIN is 66.66MHz, then
+ * CSB = 133MHz, CORE = 400MHz, DDRC = 266MHz, LBC = 133MHz
+ */
+#define CONFIG_SYS_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_2X1 |\
+	HRCWL_SVCOD_DIV_2 |\
+	HRCWL_CSB_TO_CLKIN_2X1 |\
+	HRCWL_CORE_TO_CSB_3X1)
+#define CONFIG_SYS_HRCW_HIGH_BASE (\
+	HRCWH_PCI_HOST |\
+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_TSEC1M_IN_RGMII |\
+	HRCWH_TSEC2M_IN_RGMII |\
+	HRCWH_BIG_ENDIAN |\
+	HRCWH_LALE_NORMAL)
+
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
+		       HRCWH_FROM_0XFFF00100 |\
+		       HRCWH_ROM_LOC_NAND_SP_8BIT |\
+		       HRCWH_RL_EXT_NAND)
+#else
+#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
+		       HRCWH_FROM_0X00000100 |\
+		       HRCWH_ROM_LOC_LOCAL_16BIT |\
+		       HRCWH_RL_EXT_LEGACY)
+#endif
+
+/*
+ * System IO Config
+ */
+#define CONFIG_SYS_SICRH		0x00000000
+#define CONFIG_SYS_SICRL		0x00000000 /* 3.3V, no delay */
+
+#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
+#define CONFIG_HWCONFIG
+
+/*
+ * IMMR new address
+ */
+#define CONFIG_SYS_IMMR		0xE0000000
+
+#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+#define CONFIG_DEFAULT_IMMR	CONFIG_SYS_IMMR
+#endif
+
+/*
+ * Arbiter Setup
+ */
+#define CONFIG_SYS_ACR_PIPE_DEP	3 /* Arbiter pipeline depth is 4 */
+#define CONFIG_SYS_ACR_RPTCNT	3 /* Arbiter repeat count is 4 */
+#define CONFIG_SYS_SPCR_TSECEP	3 /* eTSEC emergency priority is highest */
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+#define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN \
+				| DDRCDR_PZ_LOZ \
+				| DDRCDR_NZ_LOZ \
+				| DDRCDR_ODT \
+				| DDRCDR_Q_DRN)
+				/* 0x7b880001 */
+/*
+ * Manually set up DDR parameters
+ * consist of two chips HY5PS12621BFP-C4 from HYNIX
+ */
+#define CONFIG_SYS_DDR_SIZE		128 /* MB */
+#define CONFIG_SYS_DDR_CS0_BNDS	0x00000007
+#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
+				| CSCONFIG_ODT_RD_NEVER \
+				| CSCONFIG_ODT_WR_ONLY_CURRENT \
+				| CSCONFIG_ROW_BIT_13 \
+				| CSCONFIG_COL_BIT_10)
+				/* 0x80010102 */
+#define CONFIG_SYS_DDR_TIMING_3	0x00000000
+#define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
+				| (0 << TIMING_CFG0_WRT_SHIFT) \
+				| (0 << TIMING_CFG0_RRT_SHIFT) \
+				| (0 << TIMING_CFG0_WWT_SHIFT) \
+				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
+				| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
+				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
+				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
+				/* 0x00220802 */
+#define CONFIG_SYS_DDR_TIMING_1	((2 << TIMING_CFG1_PRETOACT_SHIFT) \
+				| (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
+				| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
+				| (5 << TIMING_CFG1_CASLAT_SHIFT) \
+				| (6 << TIMING_CFG1_REFREC_SHIFT) \
+				| (2 << TIMING_CFG1_WRREC_SHIFT) \
+				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
+				| (2 << TIMING_CFG1_WRTORD_SHIFT))
+				/* 0x27256222 */
+#define CONFIG_SYS_DDR_TIMING_2	((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
+				| (4 << TIMING_CFG2_CPO_SHIFT) \
+				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
+				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
+				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
+				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
+				| (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
+				/* 0x121048c5 */
+#define CONFIG_SYS_DDR_INTERVAL	((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
+				| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
+				/* 0x03600100 */
+#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
+				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
+				| SDRAM_CFG_DBW_32)
+				/* 0x43080000 */
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000 /* 1 posted refresh */
+#define CONFIG_SYS_DDR_MODE		((0x0448 << SDRAM_MODE_ESD_SHIFT) \
+				| (0x0232 << SDRAM_MODE_SD_SHIFT))
+				/* ODT 150ohm CL=3, AL=1 on SDRAM */
+#define CONFIG_SYS_DDR_MODE2	0x00000000
+
+/*
+ * Memory test
+ */
+#undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
+#define CONFIG_SYS_MEMTEST_START	0x00040000 /* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00140000
+
+/*
+ * The reserved memory
+ */
+#define CONFIG_SYS_MONITOR_LEN	(384 * 1024) /* Reserve 384 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN	(512 * 1024) /* Reserved for malloc */
+
+/*
+ * Initial RAM Base Address Setup
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * Local Bus Configuration & Clock Setup
+ */
+#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_2
+#define CONFIG_SYS_LBC_LBCR		0x00040000
+#define CONFIG_FSL_ELBC		1
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
+#define CONFIG_FLASH_CFI_DRIVER	/* use the CFI driver */
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+
+#define CONFIG_SYS_FLASH_BASE		0xFE000000 /* FLASH base address */
+#define CONFIG_SYS_FLASH_SIZE		8	/* FLASH size is 8M */
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* Use h/w Flash protection. */
+
+					/* Window base at flash base */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_8MB)
+
+#define CONFIG_SYS_NOR_BR_PRELIM	(CONFIG_SYS_FLASH_BASE \
+					| BR_PS_16	/* 16 bit port */ \
+					| BR_MS_GPCM	/* MSEL = GPCM */ \
+					| BR_V)		/* valid */
+#define CONFIG_SYS_NOR_OR_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+					| OR_UPM_XAM \
+					| OR_GPCM_CSNT \
+					| OR_GPCM_ACS_DIV2 \
+					| OR_GPCM_XACS \
+					| OR_GPCM_SCY_15 \
+					| OR_GPCM_TRLX_SET \
+					| OR_GPCM_EHTR_SET \
+					| OR_GPCM_EAD)
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
+/* 127 64KB sectors and 8 8KB top sectors per device */
+#define CONFIG_SYS_MAX_FLASH_SECT	135
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500 /* Flash Write Timeout (ms) */
+
+/*
+ * NAND Flash on the Local Bus
+ */
+
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_SYS_NAND_BASE		0xFFF00000
+#else
+#define CONFIG_SYS_NAND_BASE		0xE0600000
+#endif
+
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITION
+#define CONFIG_CMD_MTDPARTS
+#define MTDIDS_DEFAULT			"nand0=e0600000.flash"
+#define MTDPARTS_DEFAULT		\
+	"mtdparts=e0600000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)"
+
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE	1
+#define CONFIG_CMD_NAND			1
+#define CONFIG_NAND_FSL_ELBC		1
+#define CONFIG_SYS_NAND_BLOCK_SIZE	16384
+#define CONFIG_SYS_NAND_WINDOW_SIZE    (32 * 1024)     /* 0x00008000 */
+
+#define CONFIG_SYS_NAND_U_BOOT_SIZE  (512 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST   0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
+#define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
+#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
+
+#define CONFIG_SYS_NAND_BR_PRELIM	(CONFIG_SYS_NAND_BASE \
+				| BR_DECC_CHK_GEN	/* Use HW ECC */ \
+				| BR_PS_8		/* 8 bit port */ \
+				| BR_MS_FCM		/* MSEL = FCM */ \
+				| BR_V)			/* valid */
+#define CONFIG_SYS_NAND_OR_PRELIM	\
+				(P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
+				| OR_FCM_CSCT \
+				| OR_FCM_CST \
+				| OR_FCM_CHT \
+				| OR_FCM_SCY_1 \
+				| OR_FCM_TRLX \
+				| OR_FCM_EHTR)
+				/* 0xFFFF8396 */
+
+#ifdef CONFIG_NAND_U_BOOT
+#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
+#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
+#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM
+#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM
+#else
+#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
+#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
+#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
+#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
+#endif
+
+#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_NAND_BASE
+#define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)
+
+#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
+#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
+
+#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \
+	!defined(CONFIG_NAND_SPL)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef CONFIG_SYS_RAMBOOT
+#endif
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		(CONFIG_83XX_CLKIN * 2)
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+/* Pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x51} }
+
+/*
+ * Board info - revision and where boot from
+ */
+#define CONFIG_SYS_I2C_PCF8574A_ADDR	0x39
+
+/*
+ * Config on-board RTC
+ */
+#define CONFIG_RTC_DS1337	/* ds1339 on board, use ds1337 rtc via i2c */
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68 /* at address 0x68 */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCI_MEM_BASE		0x80000000
+#define CONFIG_SYS_PCI_MEM_PHYS		CONFIG_SYS_PCI_MEM_BASE
+#define CONFIG_SYS_PCI_MEM_SIZE		0x10000000 /* 256M */
+#define CONFIG_SYS_PCI_MMIO_BASE	0x90000000
+#define CONFIG_SYS_PCI_MMIO_PHYS	CONFIG_SYS_PCI_MMIO_BASE
+#define CONFIG_SYS_PCI_MMIO_SIZE	0x10000000 /* 256M */
+#define CONFIG_SYS_PCI_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI_IO_PHYS		0xE0300000
+#define CONFIG_SYS_PCI_IO_SIZE		0x100000 /* 1M */
+
+#define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_PCI_SLV_MEM_BUS	0x00000000
+#define CONFIG_SYS_PCI_SLV_MEM_SIZE	0x80000000
+
+#define CONFIG_SYS_PCIE1_BASE		0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_BASE	0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000
+#define CONFIG_SYS_PCIE1_CFG_BASE	0xB0000000
+#define CONFIG_SYS_PCIE1_CFG_SIZE	0x01000000
+#define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xB1000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000
+
+#define CONFIG_SYS_PCIE2_BASE		0xC0000000
+#define CONFIG_SYS_PCIE2_MEM_BASE	0xC0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xC0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000
+#define CONFIG_SYS_PCIE2_CFG_BASE	0xD0000000
+#define CONFIG_SYS_PCIE2_CFG_SIZE	0x01000000
+#define CONFIG_SYS_PCIE2_IO_BASE	0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xD1000000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000
+
+#define CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_PCIE
+
+#define CONFIG_PCI_PNP		/* do pci plug-and-play */
+
+#define CONFIG_EEPRO100
+#undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
+
+#define CONFIG_HAS_FSL_DR_USB
+#define CONFIG_SYS_SCCR_USBDRCM		3
+
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_USB_PHY_TYPE	"utmi"
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+
+/*
+ * TSEC
+ */
+#define CONFIG_TSEC_ENET	/* TSEC ethernet support */
+#define CONFIG_SYS_TSEC1_OFFSET	0x24000
+#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
+#define CONFIG_SYS_TSEC2_OFFSET	0x25000
+#define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
+
+/*
+ * TSEC ethernet configuration
+ */
+#define CONFIG_MII		1 /* MII PHY management */
+#define CONFIG_TSEC1		1
+#define CONFIG_TSEC1_NAME	"eTSEC0"
+#define CONFIG_TSEC2		1
+#define CONFIG_TSEC2_NAME	"eTSEC1"
+#define TSEC1_PHY_ADDR		0
+#define TSEC2_PHY_ADDR		1
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
+
+/* Options are: eTSEC[0-1] */
+#define CONFIG_ETHPRIME		"eTSEC1"
+
+/*
+ * SATA
+ */
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1_OFFSET	0x18000
+#define CONFIG_SYS_SATA1	(CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
+#define CONFIG_SYS_SATA1_FLAGS	FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2_OFFSET	0x19000
+#define CONFIG_SYS_SATA2	(CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
+#define CONFIG_SYS_SATA2_FLAGS	FLAGS_DMA
+
+#ifdef CONFIG_FSL_SATA
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+/*
+ * Environment
+ */
+#if defined(CONFIG_NAND_U_BOOT)
+	#define CONFIG_ENV_IS_IN_NAND	1
+	#define CONFIG_ENV_OFFSET		(512 * 1024)
+	#define CONFIG_ENV_SECT_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
+	#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
+	#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+	#define CONFIG_ENV_RANGE	(CONFIG_ENV_SECT_SIZE * 4)
+	#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
+						 CONFIG_ENV_RANGE)
+#elif !defined(CONFIG_SYS_RAMBOOT)
+	#define CONFIG_ENV_IS_IN_FLASH	1
+	#define CONFIG_ENV_ADDR		\
+			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+	#define CONFIG_ENV_SECT_SIZE	0x10000 /* 64K(one sector) for env */
+	#define CONFIG_ENV_SIZE		0x2000
+#else
+	#define CONFIG_SYS_NO_FLASH	1	/* Flash is not usable now */
+	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
+	#define CONFIG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_PCI
+
+#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
+    #undef CONFIG_CMD_SAVEENV
+    #undef CONFIG_CMD_LOADS
+#endif
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history */
+#define CONFIG_AUTO_COMPLETE		/* add autocompletion support */
+
+#undef CONFIG_WATCHDOG		/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
+
+#if defined(CONFIG_CMD_KGDB)
+	#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */
+#else
+	#define CONFIG_SYS_CBSIZE	256 /* Console I/O Buffer Size */
+#endif
+
+				/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+				/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */
+
+/*
+ * Core HID Setup
+ */
+#define CONFIG_SYS_HID0_INIT	0x000000000
+#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
+				 HID0_ENABLE_INSTRUCTION_CACHE | \
+				 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
+#define CONFIG_SYS_HID2		HID2_HBE
+
+/*
+ * MMU Setup
+ */
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
+/* DDR: cache cacheable */
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE \
+				| BATL_PP_RW \
+				| BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE \
+				| BATU_BL_128M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+
+/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR \
+				| BATL_PP_RW \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR \
+				| BATU_BL_8M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+
+/* FLASH: icache cacheable, but dcache-inhibit and guarded */
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_FLASH_BASE \
+				| BATL_PP_RW \
+				| BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_FLASH_BASE \
+				| BATU_BL_32M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_FLASH_BASE \
+				| BATL_PP_RW \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+
+/* Stack in dcache: cacheable, no memory coherence */
+#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
+#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_INIT_RAM_ADDR \
+				| BATU_BL_128K \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
+
+/* PCI MEM space: cacheable */
+#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCI_MEM_PHYS \
+				| BATL_PP_RW \
+				| BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_PCI_MEM_PHYS \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
+#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
+
+/* PCI MMIO space: cache-inhibit and guarded */
+#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_PCI_MMIO_PHYS \
+				| BATL_PP_RW \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_PCI_MMIO_PHYS \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
+#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
+
+#define CONFIG_SYS_IBAT6L	0
+#define CONFIG_SYS_IBAT6U	0
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
+
+#define CONFIG_SYS_IBAT7L	0
+#define CONFIG_SYS_IBAT7U	0
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#endif
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_LOADADDR 800000	/* default location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY 6	/* -1 disables auto-boot */
+#undef CONFIG_BOOTARGS		/* the boot command will set bootargs */
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"consoledev=ttyS0\0"						\
+	"ramdiskaddr=1000000\0"						\
+	"ramdiskfile=ramfs.83xx\0"					\
+	"fdtaddr=780000\0"						\
+	"fdtfile=mpc8315erdb.dtb\0"					\
+	"usb_phy_type=utmi\0"						\
+	""
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv bootargs root=/dev/nfs rw "				\
+		"nfsroot=$serverip:$rootpath "				\
+		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"	\
+							"$netdev:off "	\
+		"console=$consoledev,$baudrate $othbootargs;"		\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+	"setenv bootargs root=/dev/ram rw "				\
+		"console=$consoledev,$baudrate $othbootargs;"		\
+	"tftp $ramdiskaddr $ramdiskfile;"				\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+
+#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/MPC8323ERDB.h b/qemu/roms/u-boot/include/configs/MPC8323ERDB.h
new file mode 100644
index 000000000..65a63e2b7
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/MPC8323ERDB.h
@@ -0,0 +1,555 @@
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1	/* E300 family */
+#define CONFIG_QE		1	/* Has QE */
+#define CONFIG_MPC832x		1	/* MPC832x CPU specific */
+
+#define	CONFIG_SYS_TEXT_BASE	0xFE000000
+
+#define CONFIG_PCI		1
+
+/*
+ * System Clock Setup
+ */
+#define CONFIG_83XX_CLKIN	66666667	/* in Hz */
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN
+#endif
+
+/*
+ * Hardware Reset Configuration Word
+ */
+#define CONFIG_SYS_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_2X1 |\
+	HRCWL_VCO_1X2 |\
+	HRCWL_CSB_TO_CLKIN_2X1 |\
+	HRCWL_CORE_TO_CSB_2_5X1 |\
+	HRCWL_CE_PLL_VCO_DIV_2 |\
+	HRCWL_CE_PLL_DIV_1X1 |\
+	HRCWL_CE_TO_PLL_1X3)
+
+#define CONFIG_SYS_HRCW_HIGH (\
+	HRCWH_PCI_HOST |\
+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0X00000100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_BIG_ENDIAN |\
+	HRCWH_LALE_NORMAL)
+
+/*
+ * System IO Config
+ */
+#define CONFIG_SYS_SICRL		0x00000000
+
+/*
+ * IMMR new address
+ */
+#define CONFIG_SYS_IMMR		0xE0000000
+
+/*
+ * System performance
+ */
+#define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
+#define CONFIG_SYS_ACR_RPTCNT	3	/* Arbiter repeat count (0-7) */
+/* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */
+#define CONFIG_SYS_SPCR_OPT	1
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_DDR_BASE	0x00000000	/* DDR is system memory */
+#define CONFIG_SYS_SDRAM_BASE	CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
+
+#undef CONFIG_SPD_EEPROM
+#if defined(CONFIG_SPD_EEPROM)
+/* Determine DDR configuration from I2C interface
+ */
+#define SPD_EEPROM_ADDRESS	0x51	/* DDR SODIMM */
+#else
+/* Manually set up DDR parameters
+ */
+#define CONFIG_SYS_DDR_SIZE	64	/* MB */
+#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
+				| CSCONFIG_ROW_BIT_13 \
+				| CSCONFIG_COL_BIT_9)
+				/* 0x80010101 */
+#define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
+				| (0 << TIMING_CFG0_WRT_SHIFT) \
+				| (0 << TIMING_CFG0_RRT_SHIFT) \
+				| (0 << TIMING_CFG0_WWT_SHIFT) \
+				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
+				| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
+				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
+				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
+				/* 0x00220802 */
+#define CONFIG_SYS_DDR_TIMING_1	((2 << TIMING_CFG1_PRETOACT_SHIFT) \
+				| (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
+				| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
+				| (5 << TIMING_CFG1_CASLAT_SHIFT) \
+				| (3 << TIMING_CFG1_REFREC_SHIFT) \
+				| (2 << TIMING_CFG1_WRREC_SHIFT) \
+				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
+				| (2 << TIMING_CFG1_WRTORD_SHIFT))
+				/* 0x26253222 */
+#define CONFIG_SYS_DDR_TIMING_2	((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
+				| (31 << TIMING_CFG2_CPO_SHIFT) \
+				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
+				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
+				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
+				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
+				| (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
+				/* 0x1f9048c7 */
+#define CONFIG_SYS_DDR_TIMING_3	0x00000000
+#define CONFIG_SYS_DDR_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+				/* 0x02000000 */
+#define CONFIG_SYS_DDR_MODE	((0x4448 << SDRAM_MODE_ESD_SHIFT) \
+				| (0x0232 << SDRAM_MODE_SD_SHIFT))
+				/* 0x44480232 */
+#define CONFIG_SYS_DDR_MODE2	0x8000c000
+#define CONFIG_SYS_DDR_INTERVAL	((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
+				| (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
+				/* 0x03200064 */
+#define CONFIG_SYS_DDR_CS0_BNDS	0x00000003
+#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
+				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
+				| SDRAM_CFG_32_BE)
+				/* 0x43080000 */
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
+#endif
+
+/*
+ * Memory test
+ */
+#undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
+#define CONFIG_SYS_MEMTEST_START	0x00030000	/* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x03f00000
+
+/*
+ * The reserved memory
+ */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef  CONFIG_SYS_RAMBOOT
+#endif
+
+/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
+#define CONFIG_SYS_MONITOR_LEN	(384 * 1024)	/* Reserve 384 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN	(256 * 1024)	/* Reserved for malloc */
+
+/*
+ * Initial RAM Base Address Setup
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * Local Bus Configuration & Clock Setup
+ */
+#define CONFIG_SYS_LCRR_DBYP		LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_2
+#define CONFIG_SYS_LBC_LBCR		0x00000000
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
+#define CONFIG_FLASH_CFI_DRIVER	/* use the CFI driver */
+#define CONFIG_SYS_FLASH_BASE	0xFE000000	/* FLASH base address */
+#define CONFIG_SYS_FLASH_SIZE		16	/* FLASH size is 16M */
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* Use h/w Flash protection. */
+
+					/* Window base at flash base */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_32MB)
+
+#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE \
+				| BR_PS_16	/* 16 bit port */ \
+				| BR_MS_GPCM	/* MSEL = GPCM */ \
+				| BR_V)		/* valid */
+#define CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+				| OR_GPCM_XAM \
+				| OR_GPCM_CSNT \
+				| OR_GPCM_ACS_DIV2 \
+				| OR_GPCM_XACS \
+				| OR_GPCM_SCY_15 \
+				| OR_GPCM_TRLX_SET \
+				| OR_GPCM_EHTR_SET \
+				| OR_GPCM_EAD)
+				/* 0xFE006FF7 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* sectors per device */
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history */
+#define CONFIG_AUTO_COMPLETE		/* add autocompletion support   */
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x51} }
+
+/*
+ * Config on-board EEPROM
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
+#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE		0xd0000000
+#define CONFIG_SYS_PCI1_IO_PHYS		CONFIG_SYS_PCI1_IO_BASE
+#define CONFIG_SYS_PCI1_IO_SIZE		0x04000000	/* 64M */
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_PCI_SKIP_HOST_BRIDGE
+#define CONFIG_PCI_PNP		/* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID	0x1957	/* Freescale */
+
+#endif	/* CONFIG_PCI */
+
+/*
+ * QE UEC ethernet configuration
+ */
+#define CONFIG_UEC_ETH
+#define CONFIG_ETHPRIME		"UEC0"
+
+#define CONFIG_UEC_ETH1		/* ETH3 */
+
+#ifdef CONFIG_UEC_ETH1
+#define CONFIG_SYS_UEC1_UCC_NUM	2	/* UCC3 */
+#define CONFIG_SYS_UEC1_RX_CLK		QE_CLK9
+#define CONFIG_SYS_UEC1_TX_CLK		QE_CLK10
+#define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
+#define CONFIG_SYS_UEC1_PHY_ADDR	4
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE	PHY_INTERFACE_MODE_MII
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED	100
+#endif
+
+#define CONFIG_UEC_ETH2		/* ETH4 */
+
+#ifdef CONFIG_UEC_ETH2
+#define CONFIG_SYS_UEC2_UCC_NUM	1	/* UCC2 */
+#define CONFIG_SYS_UEC2_RX_CLK		QE_CLK16
+#define CONFIG_SYS_UEC2_TX_CLK		QE_CLK3
+#define CONFIG_SYS_UEC2_ETH_TYPE	FAST_ETH
+#define CONFIG_SYS_UEC2_PHY_ADDR	0
+#define CONFIG_SYS_UEC2_INTERFACE_TYPE	PHY_INTERFACE_MODE_MII
+#define CONFIG_SYS_UEC2_INTERFACE_SPEED	100
+#endif
+
+/*
+ * Environment
+ */
+#ifndef CONFIG_SYS_RAMBOOT
+	#define CONFIG_ENV_IS_IN_FLASH	1
+	#define CONFIG_ENV_ADDR		\
+			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+	#define CONFIG_ENV_SECT_SIZE	0x20000
+	#define CONFIG_ENV_SIZE		0x2000
+#else
+	#define CONFIG_SYS_NO_FLASH	1	/* Flash is not usable now */
+	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
+	#define CONFIG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ASKENV
+
+#if defined(CONFIG_PCI)
+	#define CONFIG_CMD_PCI
+#endif
+#if defined(CONFIG_SYS_RAMBOOT)
+	#undef CONFIG_CMD_SAVEENV
+	#undef CONFIG_CMD_LOADS
+#endif
+
+#undef CONFIG_WATCHDOG		/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+#if (CONFIG_CMD_KGDB)
+	#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
+#else
+	#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
+#endif
+
+				/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+				/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+					/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(256 << 20)
+
+/*
+ * Core HID Setup
+ */
+#define CONFIG_SYS_HID0_INIT	0x000000000
+#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
+				 HID0_ENABLE_INSTRUCTION_CACHE)
+#define CONFIG_SYS_HID2		HID2_HBE
+
+/*
+ * MMU Setup
+ */
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
+/* DDR: cache cacheable */
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE \
+				| BATL_PP_RW \
+				| BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+
+/* IMMRBAR & PCI IO: cache-inhibit and guarded */
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR \
+				| BATL_PP_RW \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR \
+				| BATU_BL_4M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+
+/* FLASH: icache cacheable, but dcache-inhibit and guarded */
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_FLASH_BASE \
+				| BATL_PP_RW \
+				| BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_FLASH_BASE \
+				| BATU_BL_32M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_FLASH_BASE \
+				| BATL_PP_RW \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+
+#define CONFIG_SYS_IBAT3L	(0)
+#define CONFIG_SYS_IBAT3U	(0)
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
+
+/* Stack in dcache: cacheable, no memory coherence */
+#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
+#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_INIT_RAM_ADDR \
+				| BATU_BL_128K \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
+#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
+
+#ifdef CONFIG_PCI
+/* PCI MEM space: cacheable */
+#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_PCI1_MEM_PHYS \
+				| BATL_PP_RW \
+				| BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_PCI1_MEM_PHYS \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
+#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
+/* PCI MMIO space: cache-inhibit and guarded */
+#define CONFIG_SYS_IBAT6L	(CONFIG_SYS_PCI1_MMIO_PHYS \
+				| BATL_PP_RW \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT6U	(CONFIG_SYS_PCI1_MMIO_PHYS \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
+#else
+#define CONFIG_SYS_IBAT5L	(0)
+#define CONFIG_SYS_IBAT5U	(0)
+#define CONFIG_SYS_IBAT6L	(0)
+#define CONFIG_SYS_IBAT6U	(0)
+#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
+#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
+#endif
+
+/* Nothing in BAT7 */
+#define CONFIG_SYS_IBAT7L	(0)
+#define CONFIG_SYS_IBAT7U	(0)
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
+
+#if (CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_HAS_ETH0		/* add support for "ethaddr" */
+#define CONFIG_HAS_ETH1		/* add support for "eth1addr" */
+
+/* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM
+ * (see CONFIG_SYS_I2C_EEPROM) */
+					/* MAC address offset in I2C EEPROM */
+#define CONFIG_SYS_I2C_MAC_OFFSET	0x7f00
+
+#define CONFIG_NETDEV		"eth1"
+
+#define CONFIG_HOSTNAME		mpc8323erdb
+#define CONFIG_ROOTPATH		"/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+				/* U-Boot image on TFTP server */
+#define CONFIG_UBOOTPATH	"u-boot.bin"
+#define CONFIG_FDTFILE		"mpc832x_rdb.dtb"
+#define CONFIG_RAMDISKFILE	"rootfs.ext2.gz.uboot"
+
+				/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		800000
+#define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"netdev=" CONFIG_NETDEV "\0"					\
+	"uboot=" CONFIG_UBOOTPATH "\0"					\
+	"tftpflash=tftp $loadaddr $uboot;"				\
+		"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
+			" +$filesize; "	\
+		"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
+			" +$filesize; "	\
+		"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
+			" $filesize; "	\
+		"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
+			" +$filesize; "	\
+		"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
+			" $filesize\0"	\
+	"fdtaddr=780000\0"						\
+	"fdtfile=" CONFIG_FDTFILE "\0"					\
+	"ramdiskaddr=1000000\0"						\
+	"ramdiskfile=" CONFIG_RAMDISKFILE "\0"				\
+	"console=ttyS0\0"						\
+	"setbootargs=setenv bootargs "					\
+		"root=$rootdev rw console=$console,$baudrate $othbootargs\0"\
+	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath "	\
+		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
+								"$netdev:off "\
+		"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv rootdev /dev/nfs;"					\
+	"run setbootargs;"						\
+	"run setipargs;"						\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+	"setenv rootdev /dev/ram;"					\
+	"run setbootargs;"						\
+	"tftp $ramdiskaddr $ramdiskfile;"				\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/MPC832XEMDS.h b/qemu/roms/u-boot/include/configs/MPC832XEMDS.h
new file mode 100644
index 000000000..1735b3c52
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/MPC832XEMDS.h
@@ -0,0 +1,624 @@
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1	/* E300 family */
+#define CONFIG_QE		1	/* Has QE */
+#define CONFIG_MPC832x		1	/* MPC832x CPU specific */
+#define CONFIG_MPC832XEMDS	1	/* MPC832XEMDS board specific */
+
+#define	CONFIG_SYS_TEXT_BASE	0xFE000000
+
+/*
+ * System Clock Setup
+ */
+#ifdef CONFIG_PCISLAVE
+#define CONFIG_83XX_PCICLK	66000000	/* in HZ */
+#else
+#define CONFIG_83XX_CLKIN	66000000	/* in Hz */
+#endif
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_CLK_FREQ	66000000
+#endif
+
+/*
+ * Hardware Reset Configuration Word
+ */
+#define CONFIG_SYS_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_2X1 |\
+	HRCWL_VCO_1X2 |\
+	HRCWL_CSB_TO_CLKIN_2X1 |\
+	HRCWL_CORE_TO_CSB_2X1 |\
+	HRCWL_CE_PLL_VCO_DIV_2 |\
+	HRCWL_CE_PLL_DIV_1X1 |\
+	HRCWL_CE_TO_PLL_1X3)
+
+#ifdef CONFIG_PCISLAVE
+#define CONFIG_SYS_HRCW_HIGH (\
+	HRCWH_PCI_AGENT |\
+	HRCWH_PCI1_ARBITER_DISABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0XFFF00100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_BIG_ENDIAN |\
+	HRCWH_LALE_NORMAL)
+#else
+#define CONFIG_SYS_HRCW_HIGH (\
+	HRCWH_PCI_HOST |\
+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0X00000100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_BIG_ENDIAN |\
+	HRCWH_LALE_NORMAL)
+#endif
+
+/*
+ * System IO Config
+ */
+#define CONFIG_SYS_SICRL		0x00000000
+
+#define CONFIG_BOARD_EARLY_INIT_F	/* call board_pre_init */
+#define CONFIG_BOARD_EARLY_INIT_R
+
+/*
+ * IMMR new address
+ */
+#define CONFIG_SYS_IMMR		0xE0000000
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_DDR_BASE	0x00000000	/* DDR is system memory */
+#define CONFIG_SYS_SDRAM_BASE	CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDRCDR	0x73000002	/* DDR II voltage is 1.8V */
+
+#undef CONFIG_SPD_EEPROM
+#if defined(CONFIG_SPD_EEPROM)
+/* Determine DDR configuration from I2C interface
+ */
+#define SPD_EEPROM_ADDRESS	0x51	/* DDR SODIMM */
+#else
+/* Manually set up DDR parameters
+ */
+#define CONFIG_SYS_DDR_SIZE		128	/* MB */
+#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
+					| CSCONFIG_AP \
+					| CSCONFIG_ODT_WR_CFG \
+					| CSCONFIG_ROW_BIT_13 \
+					| CSCONFIG_COL_BIT_10)
+					/* 0x80840102 */
+#define CONFIG_SYS_DDR_TIMING_0		((0 << TIMING_CFG0_RWT_SHIFT) \
+					| (0 << TIMING_CFG0_WRT_SHIFT) \
+					| (0 << TIMING_CFG0_RRT_SHIFT) \
+					| (0 << TIMING_CFG0_WWT_SHIFT) \
+					| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
+					| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
+					| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
+					| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
+					/* 0x00220802 */
+#define CONFIG_SYS_DDR_TIMING_1		((3 << TIMING_CFG1_PRETOACT_SHIFT) \
+					| (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
+					| (3 << TIMING_CFG1_ACTTORW_SHIFT) \
+					| (5 << TIMING_CFG1_CASLAT_SHIFT) \
+					| (13 << TIMING_CFG1_REFREC_SHIFT) \
+					| (3 << TIMING_CFG1_WRREC_SHIFT) \
+					| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
+					| (2 << TIMING_CFG1_WRTORD_SHIFT))
+					/* 0x3935D322 */
+#define CONFIG_SYS_DDR_TIMING_2		((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
+				| (31 << TIMING_CFG2_CPO_SHIFT) \
+				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
+				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
+				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
+				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
+				| (10 << TIMING_CFG2_FOUR_ACT_SHIFT))
+				/* 0x0F9048CA */
+#define CONFIG_SYS_DDR_TIMING_3		0x00000000
+#define CONFIG_SYS_DDR_CLK_CNTL		DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+					/* 0x02000000 */
+#define CONFIG_SYS_DDR_MODE		((0x4440 << SDRAM_MODE_ESD_SHIFT) \
+					| (0x0232 << SDRAM_MODE_SD_SHIFT))
+					/* 0x44400232 */
+#define CONFIG_SYS_DDR_MODE2		0x8000c000
+#define CONFIG_SYS_DDR_INTERVAL		((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
+					| (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
+					/* 0x03200064 */
+#define CONFIG_SYS_DDR_CS0_BNDS		0x00000007
+#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
+					| SDRAM_CFG_SDRAM_TYPE_DDR2 \
+					| SDRAM_CFG_32_BE)
+					/* 0x43080000 */
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
+#endif
+
+/*
+ * Memory test
+ */
+#undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
+#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00100000
+
+/*
+ * The reserved memory
+ */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef  CONFIG_SYS_RAMBOOT
+#endif
+
+/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
+#define CONFIG_SYS_MONITOR_LEN	(384 * 1024)	/* Reserve 384 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN	(256 * 1024)	/* Reserved for malloc */
+
+/*
+ * Initial RAM Base Address Setup
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000	/* Initial RAM addr */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * Local Bus Configuration & Clock Setup
+ */
+#define CONFIG_SYS_LCRR_DBYP		LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_2
+#define CONFIG_SYS_LBC_LBCR		0x00000000
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
+#define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
+#define CONFIG_SYS_FLASH_BASE	0xFE000000	/* FLASH base address */
+#define CONFIG_SYS_FLASH_SIZE	16	/* FLASH size is 16M */
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* Use h/w Flash protection. */
+
+					/* Window base at flash base */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_32MB)
+
+#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE \
+				| BR_PS_16	/* 16 bit port */ \
+				| BR_MS_GPCM	/* MSEL = GPCM */ \
+				| BR_V)		/* valid */
+#define CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+				| OR_GPCM_XAM \
+				| OR_GPCM_CSNT \
+				| OR_GPCM_ACS_DIV2 \
+				| OR_GPCM_XACS \
+				| OR_GPCM_SCY_15 \
+				| OR_GPCM_TRLX_SET \
+				| OR_GPCM_EHTR_SET \
+				| OR_GPCM_EAD)
+				/* 0xfe006ff7 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* sectors per device */
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+
+/*
+ * BCSR on the Local Bus
+ */
+#define CONFIG_SYS_BCSR			0xF8000000
+					/* Access window base at BCSR base */
+#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_BCSR
+#define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)
+
+#define CONFIG_SYS_BR1_PRELIM		(CONFIG_SYS_BCSR \
+					| BR_PS_8 \
+					| BR_MS_GPCM \
+					| BR_V)
+#define CONFIG_SYS_OR1_PRELIM		(OR_AM_32KB \
+					| OR_GPCM_XAM \
+					| OR_GPCM_CSNT \
+					| OR_GPCM_XACS \
+					| OR_GPCM_SCY_15 \
+					| OR_GPCM_TRLX_SET \
+					| OR_GPCM_EHTR_SET \
+					| OR_GPCM_EAD)
+					/* 0xFFFFE9F7 */
+
+/*
+ * Windows to access PIB via local bus
+ */
+					/* PIB window base 0xF8008000 */
+#define CONFIG_SYS_PIB_BASE		0xF8008000
+#define CONFIG_SYS_PIB_WINDOW_SIZE	(32 * 1024)
+#define CONFIG_SYS_LBLAWBAR3_PRELIM	CONFIG_SYS_PIB_BASE
+#define CONFIG_SYS_LBLAWAR3_PRELIM	(LBLAWAR_EN | LBLAWAR_64KB)
+
+/*
+ * CS2 on Local Bus, to PIB
+ */
+#define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_PIB_BASE \
+				| BR_PS_8 \
+				| BR_MS_GPCM \
+				| BR_V)
+				/* 0xF8008801 */
+#define CONFIG_SYS_OR2_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
+				| OR_GPCM_XAM \
+				| OR_GPCM_CSNT \
+				| OR_GPCM_XACS \
+				| OR_GPCM_SCY_15 \
+				| OR_GPCM_TRLX_SET \
+				| OR_GPCM_EHTR_SET \
+				| OR_GPCM_EAD)
+				/* 0xffffe9f7 */
+
+/*
+ * CS3 on Local Bus, to PIB
+ */
+#define CONFIG_SYS_BR3_PRELIM	((CONFIG_SYS_PIB_BASE + \
+					CONFIG_SYS_PIB_WINDOW_SIZE) \
+				| BR_PS_8 \
+				| BR_MS_GPCM \
+				| BR_V)
+				/* 0xF8010801 */
+#define CONFIG_SYS_OR3_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
+				| OR_GPCM_XAM \
+				| OR_GPCM_CSNT \
+				| OR_GPCM_XACS \
+				| OR_GPCM_SCY_15 \
+				| OR_GPCM_TRLX_SET \
+				| OR_GPCM_EHTR_SET \
+				| OR_GPCM_EAD)
+				/* 0xffffe9f7 */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_AUTO_COMPLETE		/* add autocompletion support   */
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x51} }
+
+/*
+ * Config on-board RTC
+ */
+#define CONFIG_RTC_DS1374		/* use ds1374 rtc via i2c */
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68	/* at address 0x68 */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
+#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS		0xE0300000
+#define CONFIG_SYS_PCI1_IO_SIZE		0x100000	/* 1M */
+
+#define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_PCI_SLV_MEM_BUS	0x00000000
+#define CONFIG_SYS_PCI_SLV_MEM_SIZE	0x80000000
+
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+
+#define CONFIG_PCI_PNP		/* do pci plug-and-play */
+#define CONFIG_83XX_PCI_STREAMING
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID	0x1957	/* Freescale */
+
+#endif	/* CONFIG_PCI */
+
+/*
+ * QE UEC ethernet configuration
+ */
+#define CONFIG_UEC_ETH
+#define CONFIG_ETHPRIME		"UEC0"
+
+#define CONFIG_UEC_ETH1		/* ETH3 */
+
+#ifdef CONFIG_UEC_ETH1
+#define CONFIG_SYS_UEC1_UCC_NUM	2	/* UCC3 */
+#define CONFIG_SYS_UEC1_RX_CLK		QE_CLK9
+#define CONFIG_SYS_UEC1_TX_CLK		QE_CLK10
+#define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
+#define CONFIG_SYS_UEC1_PHY_ADDR	3
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE	PHY_INTERFACE_MODE_MII
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED	100
+#endif
+
+#define CONFIG_UEC_ETH2		/* ETH4 */
+
+#ifdef CONFIG_UEC_ETH2
+#define CONFIG_SYS_UEC2_UCC_NUM	3	/* UCC4 */
+#define CONFIG_SYS_UEC2_RX_CLK		QE_CLK7
+#define CONFIG_SYS_UEC2_TX_CLK		QE_CLK8
+#define CONFIG_SYS_UEC2_ETH_TYPE	FAST_ETH
+#define CONFIG_SYS_UEC2_PHY_ADDR	4
+#define CONFIG_SYS_UEC2_INTERFACE_TYPE	PHY_INTERFACE_MODE_MII
+#define CONFIG_SYS_UEC2_INTERFACE_SPEED	100
+#endif
+
+/*
+ * Environment
+ */
+#ifndef CONFIG_SYS_RAMBOOT
+	#define CONFIG_ENV_IS_IN_FLASH	1
+	#define CONFIG_ENV_ADDR		\
+			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+	#define CONFIG_ENV_SECT_SIZE	0x20000
+	#define CONFIG_ENV_SIZE		0x2000
+#else
+	#define CONFIG_SYS_NO_FLASH	1	/* Flash is not usable now */
+	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
+	#define CONFIG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_ASKENV
+
+#if defined(CONFIG_PCI)
+    #define CONFIG_CMD_PCI
+#endif
+
+#if defined(CONFIG_SYS_RAMBOOT)
+    #undef CONFIG_CMD_SAVEENV
+    #undef CONFIG_CMD_LOADS
+#endif
+
+
+#undef CONFIG_WATCHDOG		/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP	/* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+#if defined(CONFIG_CMD_KGDB)
+	#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
+#else
+	#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
+#endif
+
+				/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+				/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+					/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(256 << 20)
+
+/*
+ * Core HID Setup
+ */
+#define CONFIG_SYS_HID0_INIT	0x000000000
+#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
+				 HID0_ENABLE_INSTRUCTION_CACHE)
+#define CONFIG_SYS_HID2		HID2_HBE
+
+/*
+ * MMU Setup
+ */
+
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
+/* DDR: cache cacheable */
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE \
+				| BATL_PP_RW \
+				| BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+
+/* IMMRBAR & PCI IO: cache-inhibit and guarded */
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR \
+				| BATL_PP_RW \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR \
+				| BATU_BL_4M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+
+/* BCSR: cache-inhibit and guarded */
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_BCSR \
+				| BATL_PP_RW \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_BCSR \
+				| BATU_BL_128K \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+
+/* FLASH: icache cacheable, but dcache-inhibit and guarded */
+#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_FLASH_BASE \
+				| BATL_PP_RW \
+				| BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_FLASH_BASE \
+				| BATU_BL_32M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT3L	(CONFIG_SYS_FLASH_BASE \
+				| BATL_PP_RW \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
+
+#define CONFIG_SYS_IBAT4L	(0)
+#define CONFIG_SYS_IBAT4U	(0)
+#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
+#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
+
+/* Stack in dcache: cacheable, no memory coherence */
+#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
+#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_INIT_RAM_ADDR \
+				| BATU_BL_128K \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
+#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
+
+#ifdef CONFIG_PCI
+/* PCI MEM space: cacheable */
+#define CONFIG_SYS_IBAT6L	(CONFIG_SYS_PCI1_MEM_PHYS \
+				| BATL_PP_RW \
+				| BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U	(CONFIG_SYS_PCI1_MEM_PHYS \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
+/* PCI MMIO space: cache-inhibit and guarded */
+#define CONFIG_SYS_IBAT7L	(CONFIG_SYS_PCI1_MMIO_PHYS \
+				| BATL_PP_RW \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT7U	(CONFIG_SYS_PCI1_MMIO_PHYS \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
+#else
+#define CONFIG_SYS_IBAT6L	(0)
+#define CONFIG_SYS_IBAT6U	(0)
+#define CONFIG_SYS_IBAT7L	(0)
+#define CONFIG_SYS_IBAT7U	(0)
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
+#endif
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */ #define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_UEC_ETH)
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#endif
+
+#define CONFIG_BAUDRATE	115200
+
+#define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY 6	/* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"consoledev=ttyS0\0"						\
+	"ramdiskaddr=1000000\0"						\
+	"ramdiskfile=ramfs.83xx\0"					\
+	"fdtaddr=780000\0"						\
+	"fdtfile=mpc832x_mds.dtb\0"					\
+	""
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv bootargs root=/dev/nfs rw "				\
+		"nfsroot=$serverip:$rootpath "				\
+		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"	\
+							"$netdev:off "	\
+		"console=$consoledev,$baudrate $othbootargs;"		\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+	"setenv bootargs root=/dev/ram rw "				\
+		"console=$consoledev,$baudrate $othbootargs;"		\
+	"tftp $ramdiskaddr $ramdiskfile;"				\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+
+#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/MPC8349EMDS.h b/qemu/roms/u-boot/include/configs/MPC8349EMDS.h
new file mode 100644
index 000000000..6b7d64894
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/MPC8349EMDS.h
@@ -0,0 +1,810 @@
+/*
+ * (C) Copyright 2006-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * mpc8349emds board configuration file
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1	/* E300 Family */
+#define CONFIG_MPC834x		1	/* MPC834x family */
+#define CONFIG_MPC8349		1	/* MPC8349 specific */
+#define CONFIG_MPC8349EMDS	1	/* MPC8349EMDS board specific */
+
+#define	CONFIG_SYS_TEXT_BASE	0xFE000000
+
+#define CONFIG_PCI_66M
+#ifdef CONFIG_PCI_66M
+#define CONFIG_83XX_CLKIN	66000000	/* in Hz */
+#else
+#define CONFIG_83XX_CLKIN	33000000	/* in Hz */
+#endif
+
+#ifdef CONFIG_PCISLAVE
+#define CONFIG_PCI
+#define CONFIG_83XX_PCICLK	66666666	/* in Hz */
+#endif /* CONFIG_PCISLAVE */
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#ifdef CONFIG_PCI_66M
+#define CONFIG_SYS_CLK_FREQ	66000000
+#define HRCWL_CSB_TO_CLKIN	HRCWL_CSB_TO_CLKIN_4X1
+#else
+#define CONFIG_SYS_CLK_FREQ	33000000
+#define HRCWL_CSB_TO_CLKIN	HRCWL_CSB_TO_CLKIN_8X1
+#endif
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_F		/* call board_pre_init */
+
+#define CONFIG_SYS_IMMR		0xE0000000
+
+#undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
+#define CONFIG_SYS_MEMTEST_START	0x00000000      /* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00100000
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_DDR_ECC			/* support DDR ECC function */
+#define CONFIG_DDR_ECC_CMD		/* use DDR ECC user commands */
+#define CONFIG_SPD_EEPROM		/* use SPD EEPROM for DDR setup*/
+
+/*
+ * define CONFIG_SYS_FSL_DDR2 to use unified DDR driver
+ * undefine it to use old spd_sdram.c
+ */
+#define CONFIG_SYS_FSL_DDR2
+#ifdef CONFIG_SYS_FSL_DDR2
+#define CONFIG_SYS_FSL_DDRC_GEN2
+#define CONFIG_SYS_SPD_BUS_NUM	0
+#define SPD_EEPROM_ADDRESS1	0x52
+#define SPD_EEPROM_ADDRESS2	0x51
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	2
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+#endif
+
+/*
+ * 32-bit data path mode.
+ *
+ * Please note that using this mode for devices with the real density of 64-bit
+ * effectively reduces the amount of available memory due to the effect of
+ * wrapping around while translating address to row/columns, for example in the
+ * 256MB module the upper 128MB get aliased with contents of the lower
+ * 128MB); normally this define should be used for devices with real 32-bit
+ * data path.
+ */
+#undef CONFIG_DDR_32BIT
+
+#define CONFIG_SYS_DDR_BASE	0x00000000	/* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE	CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN \
+					| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+#undef  CONFIG_DDR_2T_TIMING
+
+/*
+ * DDRCDR - DDR Control Driver Register
+ */
+#define CONFIG_SYS_DDRCDR_VALUE	0x80080001
+
+#if defined(CONFIG_SPD_EEPROM)
+/*
+ * Determine DDR configuration from I2C interface.
+ */
+#define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
+#else
+/*
+ * Manually set up DDR parameters
+ */
+#define CONFIG_SYS_DDR_SIZE		256		/* MB */
+#if defined(CONFIG_DDR_II)
+#define CONFIG_SYS_DDRCDR		0x80080001
+#define CONFIG_SYS_DDR_CS2_BNDS		0x0000000f
+#define CONFIG_SYS_DDR_CS2_CONFIG	0x80330102
+#define CONFIG_SYS_DDR_TIMING_0		0x00220802
+#define CONFIG_SYS_DDR_TIMING_1		0x38357322
+#define CONFIG_SYS_DDR_TIMING_2		0x2f9048c8
+#define CONFIG_SYS_DDR_TIMING_3		0x00000000
+#define CONFIG_SYS_DDR_CLK_CNTL		0x02000000
+#define CONFIG_SYS_DDR_MODE		0x47d00432
+#define CONFIG_SYS_DDR_MODE2		0x8000c000
+#define CONFIG_SYS_DDR_INTERVAL		0x03cf0080
+#define CONFIG_SYS_DDR_SDRAM_CFG	0x43000000
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
+#else
+#define CONFIG_SYS_DDR_CS2_CONFIG	(CSCONFIG_EN \
+				| CSCONFIG_ROW_BIT_13 \
+				| CSCONFIG_COL_BIT_10)
+#define CONFIG_SYS_DDR_TIMING_1	0x36332321
+#define CONFIG_SYS_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
+#define CONFIG_SYS_DDR_CONTROL	0xc2000000	/* unbuffered,no DYN_PWR */
+#define CONFIG_SYS_DDR_INTERVAL	0x04060100	/* autocharge,no open page */
+
+#if defined(CONFIG_DDR_32BIT)
+/* set burst length to 8 for 32-bit data path */
+				/* DLL,normal,seq,4/2.5, 8 burst len */
+#define CONFIG_SYS_DDR_MODE	0x00000023
+#else
+/* the default burst length is 4 - for 64-bit data path */
+				/* DLL,normal,seq,4/2.5, 4 burst len */
+#define CONFIG_SYS_DDR_MODE	0x00000022
+#endif
+#endif
+#endif
+
+/*
+ * SDRAM on the Local Bus
+ */
+#define CONFIG_SYS_LBC_SDRAM_BASE	0xF0000000	/* Localbus SDRAM */
+#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
+#define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
+#define CONFIG_SYS_FLASH_BASE		0xFE000000	/* start of FLASH   */
+#define CONFIG_SYS_FLASH_SIZE		32	/* max flash size in MB */
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* Use h/w Flash protection. */
+/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
+
+#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE \
+				| BR_PS_16	/* 16 bit port  */ \
+				| BR_MS_GPCM	/* MSEL = GPCM */ \
+				| BR_V)		/* valid */
+#define CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+				| OR_UPM_XAM \
+				| OR_GPCM_CSNT \
+				| OR_GPCM_ACS_DIV2 \
+				| OR_GPCM_XACS \
+				| OR_GPCM_SCY_15 \
+				| OR_GPCM_TRLX_SET \
+				| OR_GPCM_EHTR_SET \
+				| OR_GPCM_EAD)
+
+					/* window base at flash base */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_32MB)
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max sectors per device */
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef  CONFIG_SYS_RAMBOOT
+#endif
+
+/*
+ * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
+ */
+#define CONFIG_SYS_BCSR			0xE2400000
+					/* Access window base at BCSR base */
+#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_BCSR
+#define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)
+#define CONFIG_SYS_BR1_PRELIM		(CONFIG_SYS_BCSR \
+					| BR_PS_8 \
+					| BR_MS_GPCM \
+					| BR_V)
+					/* 0x00000801 */
+#define CONFIG_SYS_OR1_PRELIM		(OR_AM_32KB \
+					| OR_GPCM_XAM \
+					| OR_GPCM_CSNT \
+					| OR_GPCM_SCY_15 \
+					| OR_GPCM_TRLX_CLEAR \
+					| OR_GPCM_EHTR_CLEAR)
+					/* 0xFFFFE8F0 */
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000	/* Initial RAM addr */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in RAM*/
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN	(384 * 1024)	/* Reserve 384 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN	(256 * 1024)	/* Reserved for malloc */
+
+/*
+ * Local Bus LCRR and LBCR regs
+ *    LCRR:  DLL bypass, Clock divider is 4
+ * External Local Bus rate is
+ *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
+ */
+#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_4
+#define CONFIG_SYS_LBC_LBCR	0x00000000
+
+/*
+ * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
+ * if board has SRDAM on local bus, you can define CONFIG_SYS_LB_SDRAM
+ */
+#undef CONFIG_SYS_LB_SDRAM
+
+#ifdef CONFIG_SYS_LB_SDRAM
+/* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
+/*
+ * Base Register 2 and Option Register 2 configure SDRAM.
+ * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
+ *
+ * For BR2, need:
+ *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
+ *    port-size = 32-bits = BR2[19:20] = 11
+ *    no parity checking = BR2[21:22] = 00
+ *    SDRAM for MSEL = BR2[24:26] = 011
+ *    Valid = BR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
+ */
+
+#define CONFIG_SYS_BR2_PRELIM		(CONFIG_SYS_LBC_SDRAM_BASE \
+					| BR_PS_32	/* 32-bit port */ \
+					| BR_MS_SDRAM	/* MSEL = SDRAM */ \
+					| BR_V)		/* Valid */
+					/* 0xF0001861 */
+#define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_LBC_SDRAM_BASE
+#define CONFIG_SYS_LBLAWAR2_PRELIM	(LBLAWAR_EN | LBLAWAR_64MB)
+
+/*
+ * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
+ *
+ * For OR2, need:
+ *    64MB mask for AM, OR2[0:7] = 1111 1100
+ *                 XAM, OR2[17:18] = 11
+ *    9 columns OR2[19-21] = 010
+ *    13 rows   OR2[23-25] = 100
+ *    EAD set for extra time OR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
+ */
+
+#define CONFIG_SYS_OR2_PRELIM	(OR_AM_64MB \
+			| OR_SDRAM_XAM \
+			| ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
+			| ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
+			| OR_SDRAM_EAD)
+			/* 0xFC006901 */
+
+				/* LB sdram refresh timer, about 6us */
+#define CONFIG_SYS_LBC_LSRT	0x32000000
+				/* LB refresh timer prescal, 266MHz/32 */
+#define CONFIG_SYS_LBC_MRTPR	0x20000000
+
+#define CONFIG_SYS_LBC_LSDMR_COMMON    (LSDMR_RFEN	\
+				| LSDMR_BSMA1516	\
+				| LSDMR_RFCR8		\
+				| LSDMR_PRETOACT6	\
+				| LSDMR_ACTTORW3	\
+				| LSDMR_BL8		\
+				| LSDMR_WRC3		\
+				| LSDMR_CL3)
+
+/*
+ * SDRAM Controller configuration sequence.
+ */
+#define CONFIG_SYS_LBC_LSDMR_1	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
+#define CONFIG_SYS_LBC_LSDMR_2	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_3	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_4	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
+#define CONFIG_SYS_LBC_LSDMR_5	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
+#endif
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX     1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE    1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_IMMR+0x4500)
+#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_IMMR+0x4600)
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_AUTO_COMPLETE		/* add autocompletion support   */
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
+
+/* SPI */
+#define CONFIG_MPC8XXX_SPI
+#undef CONFIG_SOFT_SPI			/* SPI bit-banged */
+
+/* GPIOs.  Used as SPI chip selects */
+#define CONFIG_SYS_GPIO1_PRELIM
+#define CONFIG_SYS_GPIO1_DIR		0xC0000000  /* SPI CS on 0, LED on 1 */
+#define CONFIG_SYS_GPIO1_DAT		0xC0000000  /* Both are active LOW */
+
+/* TSEC */
+#define CONFIG_SYS_TSEC1_OFFSET 0x24000
+#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
+#define CONFIG_SYS_TSEC2_OFFSET 0x25000
+#define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
+
+/* USB */
+#define CONFIG_SYS_USE_MPC834XSYS_USB_PHY	1 /* Use SYS board PHY */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
+#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS		0xE2000000
+#define CONFIG_SYS_PCI1_IO_SIZE		0x00100000	/* 1M */
+
+#define CONFIG_SYS_PCI2_MEM_BASE	0xA0000000
+#define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BASE
+#define CONFIG_SYS_PCI2_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI2_MMIO_BASE	0xB0000000
+#define CONFIG_SYS_PCI2_MMIO_PHYS	CONFIG_SYS_PCI2_MMIO_BASE
+#define CONFIG_SYS_PCI2_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI2_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI2_IO_PHYS		0xE2100000
+#define CONFIG_SYS_PCI2_IO_SIZE		0x00100000	/* 1M */
+
+#if defined(CONFIG_PCI)
+
+#define PCI_ONE_PCI1
+#if defined(PCI_64BIT)
+#undef PCI_ALL_PCI1
+#undef PCI_TWO_PCI1
+#undef PCI_ONE_PCI1
+#endif
+
+#define CONFIG_PCI_PNP		/* do pci plug-and-play */
+#define CONFIG_83XX_PCI_STREAMING
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+	#define PCI_ENET0_IOADDR	0xFIXME
+	#define PCI_ENET0_MEMADDR	0xFIXME
+	#define PCI_IDSEL_NUMBER	0x0c	/* slot0->3(IDSEL)=12->15 */
+#endif
+
+#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957  /* Freescale */
+
+#endif	/* CONFIG_PCI */
+
+/*
+ * TSEC configuration
+ */
+#define CONFIG_TSEC_ENET	/* TSEC ethernet support */
+
+#if defined(CONFIG_TSEC_ENET)
+
+#define CONFIG_GMII		1	/* MII PHY management */
+#define CONFIG_TSEC1		1
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_TSEC2		1
+#define CONFIG_TSEC2_NAME	"TSEC1"
+#define TSEC1_PHY_ADDR		0
+#define TSEC2_PHY_ADDR		1
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME		"TSEC0"
+
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * Configure on-board RTC
+ */
+#define CONFIG_RTC_DS1374		/* use ds1374 rtc via i2c */
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68	/* at address 0x68 */
+
+/*
+ * Environment
+ */
+#ifndef CONFIG_SYS_RAMBOOT
+	#define CONFIG_ENV_IS_IN_FLASH	1
+	#define CONFIG_ENV_ADDR		\
+			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+	#define CONFIG_ENV_SECT_SIZE	0x20000	/* 128K(one sector) for env */
+	#define CONFIG_ENV_SIZE		0x2000
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+#else
+	#define CONFIG_SYS_NO_FLASH	1	/* Flash is not usable now */
+	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
+	#define CONFIG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_MII
+
+#if defined(CONFIG_PCI)
+    #define CONFIG_CMD_PCI
+#endif
+
+#if defined(CONFIG_SYS_RAMBOOT)
+    #undef CONFIG_CMD_SAVEENV
+    #undef CONFIG_CMD_LOADS
+#endif
+
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+#if defined(CONFIG_CMD_KGDB)
+	#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
+#else
+	#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
+#endif
+
+				/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+				/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+				/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)
+
+#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
+
+#if 1 /*528/264*/
+#define CONFIG_SYS_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_1X1 |\
+	HRCWL_CSB_TO_CLKIN |\
+	HRCWL_VCO_1X2 |\
+	HRCWL_CORE_TO_CSB_2X1)
+#elif 0 /*396/132*/
+#define CONFIG_SYS_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_1X1 |\
+	HRCWL_CSB_TO_CLKIN |\
+	HRCWL_VCO_1X4 |\
+	HRCWL_CORE_TO_CSB_3X1)
+#elif 0 /*264/132*/
+#define CONFIG_SYS_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_1X1 |\
+	HRCWL_CSB_TO_CLKIN |\
+	HRCWL_VCO_1X4 |\
+	HRCWL_CORE_TO_CSB_2X1)
+#elif 0 /*132/132*/
+#define CONFIG_SYS_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_1X1 |\
+	HRCWL_CSB_TO_CLKIN |\
+	HRCWL_VCO_1X4 |\
+	HRCWL_CORE_TO_CSB_1X1)
+#elif 0 /*264/264 */
+#define CONFIG_SYS_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_1X1 |\
+	HRCWL_CSB_TO_CLKIN |\
+	HRCWL_VCO_1X4 |\
+	HRCWL_CORE_TO_CSB_1X1)
+#endif
+
+#ifdef CONFIG_PCISLAVE
+#define CONFIG_SYS_HRCW_HIGH (\
+	HRCWH_PCI_AGENT |\
+	HRCWH_64_BIT_PCI |\
+	HRCWH_PCI1_ARBITER_DISABLE |\
+	HRCWH_PCI2_ARBITER_DISABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0X00000100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_TSEC1M_IN_GMII |\
+	HRCWH_TSEC2M_IN_GMII)
+#else
+#if defined(PCI_64BIT)
+#define CONFIG_SYS_HRCW_HIGH (\
+	HRCWH_PCI_HOST |\
+	HRCWH_64_BIT_PCI |\
+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_PCI2_ARBITER_DISABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0X00000100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_TSEC1M_IN_GMII |\
+	HRCWH_TSEC2M_IN_GMII)
+#else
+#define CONFIG_SYS_HRCW_HIGH (\
+	HRCWH_PCI_HOST |\
+	HRCWH_32_BIT_PCI |\
+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_PCI2_ARBITER_ENABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0X00000100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_TSEC1M_IN_GMII |\
+	HRCWH_TSEC2M_IN_GMII)
+#endif /* PCI_64BIT */
+#endif /* CONFIG_PCISLAVE */
+
+/*
+ * System performance
+ */
+#define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
+#define CONFIG_SYS_ACR_RPTCNT	3	/* Arbiter repeat count (0-7) */
+#define CONFIG_SYS_SPCR_TSEC1EP	3	/* TSEC1 emergency priority (0-3) */
+#define CONFIG_SYS_SPCR_TSEC2EP	3	/* TSEC2 emergency priority (0-3) */
+#define CONFIG_SYS_SCCR_TSEC1CM	1	/* TSEC1 clock mode (0-3) */
+#define CONFIG_SYS_SCCR_TSEC2CM	1	/* TSEC2 & I2C0 clock mode (0-3) */
+
+/* System IO Config */
+#define CONFIG_SYS_SICRH 0
+#define CONFIG_SYS_SICRL SICRL_LDP_A
+
+#define CONFIG_SYS_HID0_INIT	0x000000000
+#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK \
+				| HID0_ENABLE_INSTRUCTION_CACHE)
+
+/* #define CONFIG_SYS_HID0_FINAL	(\
+	HID0_ENABLE_INSTRUCTION_CACHE |\
+	HID0_ENABLE_M_BIT |\
+	HID0_ENABLE_ADDRESS_BROADCAST) */
+
+
+#define CONFIG_SYS_HID2 HID2_HBE
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
+/* DDR @ 0x00000000 */
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE \
+				| BATL_PP_RW \
+				| BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+
+/* PCI @ 0x80000000 */
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_BASE \
+				| BATL_PP_RW \
+				| BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_PCI1_MEM_BASE \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_MMIO_BASE \
+				| BATL_PP_RW \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PCI1_MMIO_BASE \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+#else
+#define CONFIG_SYS_IBAT1L	(0)
+#define CONFIG_SYS_IBAT1U	(0)
+#define CONFIG_SYS_IBAT2L	(0)
+#define CONFIG_SYS_IBAT2U	(0)
+#endif
+
+#ifdef CONFIG_MPC83XX_PCI2
+#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_PCI2_MEM_BASE \
+				| BATL_PP_RW \
+				| BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_PCI2_MEM_BASE \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCI2_MMIO_BASE \
+				| BATL_PP_RW \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_PCI2_MMIO_BASE \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+#else
+#define CONFIG_SYS_IBAT3L	(0)
+#define CONFIG_SYS_IBAT3U	(0)
+#define CONFIG_SYS_IBAT4L	(0)
+#define CONFIG_SYS_IBAT4U	(0)
+#endif
+
+/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
+#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_IMMR \
+				| BATL_PP_RW \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_IMMR \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+
+/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
+#define CONFIG_SYS_IBAT6L	(0xF0000000 \
+				| BATL_PP_RW \
+				| BATL_MEMCOHERENCE \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT6U	(0xF0000000 \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+
+#define CONFIG_SYS_IBAT7L	(0)
+#define CONFIG_SYS_IBAT7U	(0)
+
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
+#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
+#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
+#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
+#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH0
+#endif
+
+#define CONFIG_HOSTNAME		mpc8349emds
+#define CONFIG_ROOTPATH		"/nfsroot/rootfs"
+#define CONFIG_BOOTFILE		"uImage"
+
+#define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE	 115200
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+	"echo"
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"hostname=mpc8349emds\0"					\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"	\
+		"bootm\0"						\
+	"load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0"		\
+	"update=protect off fe000000 fe03ffff; "			\
+		"era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\
+	"upd=run load update\0"						\
+	"fdtaddr=780000\0"						\
+	"fdtfile=mpc834x_mds.dtb\0"					\
+	""
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv bootargs root=/dev/nfs rw "				\
+		"nfsroot=$serverip:$rootpath "				\
+		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"	\
+							"$netdev:off "	\
+		"console=$consoledev,$baudrate $othbootargs;"		\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+	"setenv bootargs root=/dev/ram rw "				\
+		"console=$consoledev,$baudrate $othbootargs;"		\
+	"tftp $ramdiskaddr $ramdiskfile;"				\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/MPC8349ITX.h b/qemu/roms/u-boot/include/configs/MPC8349ITX.h
new file mode 100644
index 000000000..398918a94
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/MPC8349ITX.h
@@ -0,0 +1,806 @@
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ MPC8349E-mITX and MPC8349E-mITX-GP board configuration file
+
+ Memory map:
+
+ 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB)
+ 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB)
+ 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB)
+ 0xE000_0000-0xEFFF_FFFF IMMR (1 MB)
+ 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB)
+ 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB)
+ 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only)
+ 0xF001_0000-0xF001_FFFF Local bus expansion slot
+ 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only)
+ 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory
+ 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only)
+
+ I2C address list:
+						Align.	Board
+ Bus	Addr	Part No.	Description	Length	Location
+ ----------------------------------------------------------------
+ I2C0	0x50	M24256-BWMN6P	Board EEPROM	2	U64
+
+ I2C1	0x20	PCF8574		I2C Expander	0	U8
+ I2C1	0x21	PCF8574		I2C Expander	0	U10
+ I2C1	0x38	PCF8574A	I2C Expander	0	U8
+ I2C1	0x39	PCF8574A	I2C Expander	0	U10
+ I2C1	0x51	(DDR)		DDR EEPROM	1	U1
+ I2C1	0x68	DS1339		RTC		1	U68
+
+ Note that a given board has *either* a pair of 8574s or a pair of 8574As.
+*/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#if (CONFIG_SYS_TEXT_BASE == 0xFE000000)
+#define CONFIG_SYS_LOWBOOT
+#endif
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_MPC834x		/* MPC834x family (8343, 8347, 8349) */
+#define CONFIG_MPC8349		/* MPC8349 specific */
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xFEF00000
+#endif
+
+#define CONFIG_SYS_IMMR	0xE0000000	/* The IMMR is relocated to here */
+
+#define CONFIG_MISC_INIT_F
+#define CONFIG_MISC_INIT_R
+
+/*
+ * On-board devices
+ */
+
+#ifdef CONFIG_MPC8349ITX
+/* The CF card interface on the back of the board */
+#define CONFIG_COMPACT_FLASH
+#define CONFIG_VSC7385_ENET	/* VSC7385 ethernet support */
+#define CONFIG_SATA_SIL3114	/* SIL3114 SATA controller */
+#define CONFIG_SYS_USB_HOST	/* use the EHCI USB controller */
+#endif
+
+#define CONFIG_PCI
+#define CONFIG_RTC_DS1337
+#define CONFIG_SYS_I2C
+#define CONFIG_TSEC_ENET		/* TSEC Ethernet support */
+
+/*
+ * Device configurations
+ */
+
+/* I2C */
+#ifdef CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+
+#define CONFIG_SYS_SPD_BUS_NUM		1	/* The I2C bus for SPD */
+#define CONFIG_SYS_RTC_BUS_NUM		1	/* The I2C bus for RTC */
+
+#define CONFIG_SYS_I2C_8574_ADDR1	0x20	/* I2C1, PCF8574 */
+#define CONFIG_SYS_I2C_8574_ADDR2	0x21	/* I2C1, PCF8574 */
+#define CONFIG_SYS_I2C_8574A_ADDR1	0x38	/* I2C1, PCF8574A */
+#define CONFIG_SYS_I2C_8574A_ADDR2	0x39	/* I2C1, PCF8574A */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* I2C0, Board EEPROM */
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68	/* I2C1, DS1339 RTC*/
+#define SPD_EEPROM_ADDRESS		0x51	/* I2C1, DDR */
+
+/* Don't probe these addresses: */
+#define CONFIG_SYS_I2C_NOPROBES	{ {1, CONFIG_SYS_I2C_8574_ADDR1}, \
+				 {1, CONFIG_SYS_I2C_8574_ADDR2}, \
+				 {1, CONFIG_SYS_I2C_8574A_ADDR1}, \
+				 {1, CONFIG_SYS_I2C_8574A_ADDR2} }
+/* Bit definitions for the 8574[A] I2C expander */
+				/* Board revision, 00=0.0, 01=0.1, 10=1.0 */
+#define I2C_8574_REVISION	0x03
+#define I2C_8574_CF		0x08	/* 1=Compact flash absent, 0=present */
+#define I2C_8574_MPCICLKRN	0x10	/* MiniPCI Clk Run */
+#define I2C_8574_PCI66		0x20	/* 0=33MHz PCI, 1=66MHz PCI */
+#define I2C_8574_FLASHSIDE	0x40	/* 0=Reset vector from U4, 1=from U7*/
+
+#endif
+
+/* Compact Flash */
+#ifdef CONFIG_COMPACT_FLASH
+
+#define CONFIG_SYS_IDE_MAXBUS		1
+#define CONFIG_SYS_IDE_MAXDEVICE	1
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_CF_BASE
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000
+#define CONFIG_SYS_ATA_REG_OFFSET	0
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0200
+#define CONFIG_SYS_ATA_STRIDE		2
+
+/* If a CF card is not inserted, time out quickly */
+#define ATA_RESET_TIME	1
+
+#endif
+
+/*
+ * SATA
+ */
+#ifdef CONFIG_SATA_SIL3114
+
+#define CONFIG_SYS_SATA_MAX_DEVICE      4
+#define CONFIG_LIBATA
+#define CONFIG_LBA48
+
+#endif
+
+#ifdef CONFIG_SYS_USB_HOST
+/*
+ * Support USB
+ */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+
+/* Current USB implementation supports the only USB controller,
+ * so we have to choose between the MPH or the DR ones */
+#if 1
+#define CONFIG_HAS_FSL_MPH_USB
+#else
+#define CONFIG_HAS_FSL_DR_USB
+#endif
+
+#endif
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_83XX_DDR_USES_CS0
+#define CONFIG_SYS_MEMTEST_START	0x1000	/* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x2000
+
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN \
+					| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
+
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_MAX_MEM_MAPPED   ((phys_size_t)256 << 20)
+
+#ifdef CONFIG_SYS_I2C
+#define CONFIG_SPD_EEPROM		/* use SPD EEPROM for DDR setup*/
+#endif
+
+/* No SPD? Then manually set up DDR parameters */
+#ifndef CONFIG_SPD_EEPROM
+    #define CONFIG_SYS_DDR_SIZE		256	/* Mb */
+    #define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
+					| CSCONFIG_ROW_BIT_13 \
+					| CSCONFIG_COL_BIT_10)
+
+    #define CONFIG_SYS_DDR_TIMING_1	0x26242321
+    #define CONFIG_SYS_DDR_TIMING_2	0x00000800  /* P9-45, may need tuning */
+#endif
+
+/*
+ *Flash on the Local Bus
+ */
+
+#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
+#define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
+#define CONFIG_SYS_FLASH_BASE		0xFE000000	/* start of FLASH   */
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+/* 127 64KB sectors + 8 8KB sectors per device */
+#define CONFIG_SYS_MAX_FLASH_SECT	135
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+
+/* The ITX has two flash chips, but the ITX-GP has only one.  To support both
+boards, we say we have two, but don't display a message if we find only one. */
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
+#define CONFIG_SYS_FLASH_BANKS_LIST	\
+		{CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
+#define CONFIG_SYS_FLASH_SIZE		16	/* FLASH size in MB */
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* Use h/w Flash protection. */
+
+/* Vitesse 7385 */
+
+#ifdef CONFIG_VSC7385_ENET
+
+#define CONFIG_TSEC2
+
+/* The flash address and size of the VSC7385 firmware image */
+#define CONFIG_VSC7385_IMAGE		0xFEFFE000
+#define CONFIG_VSC7385_IMAGE_SIZE	8192
+
+#endif
+
+/*
+ * BRx, ORx, LBLAWBARx, and LBLAWARx
+ */
+
+/* Flash */
+
+#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE \
+				| BR_PS_16 \
+				| BR_MS_GPCM \
+				| BR_V)
+#define CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+				| OR_UPM_XAM \
+				| OR_GPCM_CSNT \
+				| OR_GPCM_ACS_DIV2 \
+				| OR_GPCM_XACS \
+				| OR_GPCM_SCY_15 \
+				| OR_GPCM_TRLX_SET \
+				| OR_GPCM_EHTR_SET \
+				| OR_GPCM_EAD)
+#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_16MB)
+
+/* Vitesse 7385 */
+
+#define CONFIG_SYS_VSC7385_BASE	0xF8000000
+
+#ifdef CONFIG_VSC7385_ENET
+
+#define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_VSC7385_BASE \
+				| BR_PS_8 \
+				| BR_MS_GPCM \
+				| BR_V)
+#define CONFIG_SYS_OR1_PRELIM	(OR_AM_128KB \
+				| OR_GPCM_CSNT \
+				| OR_GPCM_XACS \
+				| OR_GPCM_SCY_15 \
+				| OR_GPCM_SETA \
+				| OR_GPCM_TRLX_SET \
+				| OR_GPCM_EHTR_SET \
+				| OR_GPCM_EAD)
+
+#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_VSC7385_BASE
+#define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_128KB)
+
+#endif
+
+/* LED */
+
+#define CONFIG_SYS_LED_BASE	0xF9000000
+#define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_LED_BASE \
+				| BR_PS_8 \
+				| BR_MS_GPCM \
+				| BR_V)
+#define CONFIG_SYS_OR2_PRELIM	(OR_AM_2MB \
+				| OR_GPCM_CSNT \
+				| OR_GPCM_ACS_DIV2 \
+				| OR_GPCM_XACS \
+				| OR_GPCM_SCY_9 \
+				| OR_GPCM_TRLX_SET \
+				| OR_GPCM_EHTR_SET \
+				| OR_GPCM_EAD)
+
+/* Compact Flash */
+
+#ifdef CONFIG_COMPACT_FLASH
+
+#define CONFIG_SYS_CF_BASE	0xF0000000
+
+#define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_CF_BASE \
+				| BR_PS_16 \
+				| BR_MS_UPMA \
+				| BR_V)
+#define CONFIG_SYS_OR3_PRELIM	(OR_UPM_AM | OR_UPM_BI)
+
+#define CONFIG_SYS_LBLAWBAR3_PRELIM	CONFIG_SYS_CF_BASE
+#define CONFIG_SYS_LBLAWAR3_PRELIM	(LBLAWAR_EN | LBLAWAR_64KB)
+
+#endif
+
+/*
+ * U-Boot memory configuration
+ */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef	CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000	/* Initial RAM addr */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in RAM*/
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
+#define CONFIG_SYS_MONITOR_LEN	(384 * 1024) /* Reserve 384 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN	(256 * 1024) /* Reserved for malloc */
+
+/*
+ * Local Bus LCRR and LBCR regs
+ *    LCRR:  DLL bypass, Clock divider is 4
+ * External Local Bus rate is
+ *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
+ */
+#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_4
+#define CONFIG_SYS_LBC_LBCR	0x00000000
+
+				/* LB sdram refresh timer, about 6us */
+#define CONFIG_SYS_LBC_LSRT	0x32000000
+				/* LB refresh timer prescal, 266MHz/32*/
+#define CONFIG_SYS_LBC_MRTPR	0x20000000
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_CONSOLE		ttyS0
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+/*
+ * PCI
+ */
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+
+#define CONFIG_MPC83XX_PCI2
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE	\
+			(CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
+#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS		0xE2000000
+#define CONFIG_SYS_PCI1_IO_SIZE		0x01000000	/* 16M */
+
+#ifdef CONFIG_MPC83XX_PCI2
+#define CONFIG_SYS_PCI2_MEM_BASE	\
+			(CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE)
+#define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BASE
+#define CONFIG_SYS_PCI2_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI2_MMIO_BASE	\
+			(CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE)
+#define CONFIG_SYS_PCI2_MMIO_PHYS	CONFIG_SYS_PCI2_MMIO_BASE
+#define CONFIG_SYS_PCI2_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI2_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI2_IO_PHYS		\
+			(CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE)
+#define CONFIG_SYS_PCI2_IO_SIZE		0x01000000	/* 16M */
+#endif
+
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+
+#ifndef CONFIG_PCI_PNP
+    #define PCI_ENET0_IOADDR	0x00000000
+    #define PCI_ENET0_MEMADDR	CONFIG_SYS_PCI2_MEM_BASE
+    #define PCI_IDSEL_NUMBER	0x0f	/* IDSEL = AD15 */
+#endif
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+
+#endif
+
+#define CONFIG_PCI_66M
+#ifdef CONFIG_PCI_66M
+#define CONFIG_83XX_CLKIN	66666666	/* in Hz */
+#else
+#define CONFIG_83XX_CLKIN	33333333	/* in Hz */
+#endif
+
+/* TSEC */
+
+#ifdef CONFIG_TSEC_ENET
+
+#define CONFIG_MII
+#define CONFIG_PHY_GIGE		/* In case CONFIG_CMD_MII is specified */
+
+#define CONFIG_TSEC1
+
+#ifdef CONFIG_TSEC1
+#define CONFIG_HAS_ETH0
+#define CONFIG_TSEC1_NAME  "TSEC0"
+#define CONFIG_SYS_TSEC1_OFFSET	0x24000
+#define TSEC1_PHY_ADDR		0x1c	/* VSC8201 uses address 0x1c */
+#define TSEC1_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#endif
+
+#ifdef CONFIG_TSEC2
+#define CONFIG_HAS_ETH1
+#define CONFIG_TSEC2_NAME  "TSEC1"
+#define CONFIG_SYS_TSEC2_OFFSET	0x25000
+
+#define TSEC2_PHY_ADDR		4
+#define TSEC2_PHYIDX		0
+#define TSEC2_FLAGS		TSEC_GIGABIT
+#endif
+
+#define CONFIG_ETHPRIME		"Freescale TSEC"
+
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#ifndef CONFIG_SYS_RAMBOOT
+  #define CONFIG_ENV_IS_IN_FLASH
+  #define CONFIG_ENV_ADDR	\
+			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+  #define CONFIG_ENV_SECT_SIZE	0x10000 /* 64K (one sector) for environment */
+  #define CONFIG_ENV_SIZE	0x2000
+#else
+  #define CONFIG_SYS_NO_FLASH	/* Flash is not usable now */
+  #undef  CONFIG_FLASH_CFI_DRIVER
+  #define CONFIG_ENV_IS_NOWHERE	/* Store ENV in memory only */
+  #define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - 0x1000)
+  #define CONFIG_ENV_SIZE	0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_SDRAM
+
+#if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) \
+				|| defined(CONFIG_USB_STORAGE)
+	#define CONFIG_DOS_PARTITION
+	#define CONFIG_CMD_FAT
+	#define CONFIG_SUPPORT_VFAT
+#endif
+
+#ifdef CONFIG_COMPACT_FLASH
+	#define CONFIG_CMD_IDE
+#endif
+
+#ifdef CONFIG_SATA_SIL3114
+	#define CONFIG_CMD_SATA
+#endif
+
+#if defined(CONFIG_SATA_SIL3114) || defined(CONFIG_USB_STORAGE)
+	#define CONFIG_CMD_EXT2
+#endif
+
+#ifdef CONFIG_PCI
+	#define CONFIG_CMD_PCI
+#endif
+
+#ifdef CONFIG_SYS_I2C
+	#define CONFIG_CMD_I2C
+#endif
+
+/* Watchdog */
+#undef CONFIG_WATCHDOG		/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_CMDLINE_EDITING		/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE		/* add autocompletion support */
+#define CONFIG_SYS_HUSH_PARSER		/* Use the HUSH parser */
+
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */
+
+#ifdef CONFIG_MPC8349ITX
+#define CONFIG_SYS_PROMPT "MPC8349E-mITX> "	/* Monitor Command Prompt */
+#else
+#define CONFIG_SYS_PROMPT "MPC8349E-mITX-GP> "	/* Monitor Command Prompt */
+#endif
+
+#if defined(CONFIG_CMD_KGDB)
+	#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
+#else
+	#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
+#endif
+
+				/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+				/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+				/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)
+
+#define CONFIG_SYS_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_1X1 |\
+	HRCWL_CSB_TO_CLKIN_4X1 |\
+	HRCWL_VCO_1X2 |\
+	HRCWL_CORE_TO_CSB_2X1)
+
+#ifdef CONFIG_SYS_LOWBOOT
+#define CONFIG_SYS_HRCW_HIGH (\
+	HRCWH_PCI_HOST |\
+	HRCWH_32_BIT_PCI |\
+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_PCI2_ARBITER_ENABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0X00000100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_TSEC1M_IN_GMII |\
+	HRCWH_TSEC2M_IN_GMII)
+#else
+#define CONFIG_SYS_HRCW_HIGH (\
+	HRCWH_PCI_HOST |\
+	HRCWH_32_BIT_PCI |\
+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_PCI2_ARBITER_ENABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0XFFF00100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_TSEC1M_IN_GMII |\
+	HRCWH_TSEC2M_IN_GMII)
+#endif
+
+/*
+ * System performance
+ */
+#define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
+#define CONFIG_SYS_ACR_RPTCNT	3	/* Arbiter repeat count (0-7) */
+#define CONFIG_SYS_SPCR_TSEC1EP	3	/* TSEC1 emergency priority (0-3) */
+#define CONFIG_SYS_SPCR_TSEC2EP	3	/* TSEC2 emergency priority (0-3) */
+#define CONFIG_SYS_SCCR_TSEC1CM	1	/* TSEC1 clock mode (0-3) */
+#define CONFIG_SYS_SCCR_TSEC2CM	1	/* TSEC2 & I2C0 clock mode (0-3) */
+#define CONFIG_SYS_SCCR_USBMPHCM 3	/* USB MPH controller's clock */
+#define CONFIG_SYS_SCCR_USBDRCM	0	/* USB DR controller's clock */
+
+/*
+ * System IO Config
+ */
+/* Needed for gigabit to work on TSEC 1 */
+#define CONFIG_SYS_SICRH SICRH_TSOBI1
+				/* USB DR as device + USB MPH as host */
+#define CONFIG_SYS_SICRL	(SICRL_LDP_A | SICRL_USB1)
+
+#define CONFIG_SYS_HID0_INIT	0x00000000
+#define CONFIG_SYS_HID0_FINAL	HID0_ENABLE_INSTRUCTION_CACHE
+
+#define CONFIG_SYS_HID2	HID2_HBE
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
+/* DDR  */
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE \
+				| BATL_PP_RW \
+				| BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+
+/* PCI  */
+#ifdef CONFIG_PCI
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_BASE \
+				| BATL_PP_RW \
+				| BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_PCI1_MEM_BASE \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_MMIO_BASE \
+				| BATL_PP_RW \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PCI1_MMIO_BASE \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+#else
+#define CONFIG_SYS_IBAT1L	0
+#define CONFIG_SYS_IBAT1U	0
+#define CONFIG_SYS_IBAT2L	0
+#define CONFIG_SYS_IBAT2U	0
+#endif
+
+#ifdef CONFIG_MPC83XX_PCI2
+#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_PCI2_MEM_BASE \
+				| BATL_PP_RW \
+				| BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_PCI2_MEM_BASE \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCI2_MMIO_BASE \
+				| BATL_PP_RW \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_PCI2_MMIO_BASE \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+#else
+#define CONFIG_SYS_IBAT3L	0
+#define CONFIG_SYS_IBAT3U	0
+#define CONFIG_SYS_IBAT4L	0
+#define CONFIG_SYS_IBAT4U	0
+#endif
+
+/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
+#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_IMMR \
+				| BATL_PP_RW \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_IMMR \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+
+/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
+#define CONFIG_SYS_IBAT6L	(0xF0000000 \
+				| BATL_PP_RW \
+				| BATL_MEMCOHERENCE \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT6U	(0xF0000000 \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+
+#define CONFIG_SYS_IBAT7L	0
+#define CONFIG_SYS_IBAT7U	0
+
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
+#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
+#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
+#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
+#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
+#endif
+
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_NETDEV		"eth0"
+
+#ifdef CONFIG_MPC8349ITX
+#define CONFIG_HOSTNAME		"mpc8349emitx"
+#else
+#define CONFIG_HOSTNAME		"mpc8349emitxgp"
+#endif
+
+/* Default path and filenames */
+#define CONFIG_ROOTPATH		"/nfsroot/rootfs"
+#define CONFIG_BOOTFILE		"uImage"
+				/* U-Boot image on TFTP server */
+#define CONFIG_UBOOTPATH	"u-boot.bin"
+
+#ifdef CONFIG_MPC8349ITX
+#define CONFIG_FDTFILE		"mpc8349emitx.dtb"
+#else
+#define CONFIG_FDTFILE		"mpc8349emitxgp.dtb"
+#endif
+
+#define CONFIG_BOOTDELAY	6
+
+#define CONFIG_BOOTARGS \
+	"root=/dev/nfs rw" \
+	" nfsroot=" __stringify(CONFIG_SERVERIP) ":" CONFIG_ROOTPATH	\
+	" ip=" __stringify(CONFIG_IPADDR) ":"		\
+		__stringify(CONFIG_SERVERIP) ":"	\
+		__stringify(CONFIG_GATEWAYIP) ":"	\
+		__stringify(CONFIG_NETMASK) ":"		\
+		CONFIG_HOSTNAME ":" CONFIG_NETDEV ":off"		\
+	" console=" __stringify(CONFIG_CONSOLE) "," __stringify(CONFIG_BAUDRATE)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"console=" __stringify(CONFIG_CONSOLE) "\0"			\
+	"netdev=" CONFIG_NETDEV "\0"					\
+	"uboot=" CONFIG_UBOOTPATH "\0"					\
+	"tftpflash=tftpboot $loadaddr $uboot; "				\
+		"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
+			" +$filesize; "	\
+		"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
+			" +$filesize; "	\
+		"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
+			" $filesize; "	\
+		"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
+			" +$filesize; "	\
+		"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
+			" $filesize\0"	\
+	"fdtaddr=780000\0"						\
+	"fdtfile=" CONFIG_FDTFILE "\0"
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath"	\
+	" ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
+	" console=$console,$baudrate $othbootargs; "			\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+	"setenv bootargs root=/dev/ram rw"				\
+	" console=$console,$baudrate $othbootargs; "			\
+	"tftp $ramdiskaddr $ramdiskfile;"				\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/MPC8360EMDS.h b/qemu/roms/u-boot/include/configs/MPC8360EMDS.h
new file mode 100644
index 000000000..aefde74fc
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/MPC8360EMDS.h
@@ -0,0 +1,735 @@
+/*
+ * Copyright (C) 2006,2011 Freescale Semiconductor, Inc.
+ *
+ * Dave Liu <daveliu@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1 /* E300 family */
+#define CONFIG_QE		1 /* Has QE */
+#define CONFIG_MPC8360		1 /* MPC8360 CPU specific */
+#define CONFIG_MPC8360EMDS	1 /* MPC8360EMDS board specific */
+
+#define	CONFIG_SYS_TEXT_BASE	0xFE000000
+
+#undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */
+#undef CONFIG_PQ_MDS_PIB_ATM /* QOC3 ATM card */
+
+/*
+ * System Clock Setup
+ */
+#ifdef CONFIG_CLKIN_33MHZ
+#ifdef CONFIG_PCISLAVE
+#define CONFIG_83XX_PCICLK	33330000 /* in HZ */
+#else
+#define CONFIG_83XX_CLKIN	33330000 /* in Hz */
+#endif
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_CLK_FREQ	33330000
+#endif
+
+#elif defined(CONFIG_CLKIN_66MHZ)
+#ifdef CONFIG_PCISLAVE
+#define CONFIG_83XX_PCICLK	66000000 /* in HZ */
+#else
+#define CONFIG_83XX_CLKIN	66000000 /* in Hz */
+#endif
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_CLK_FREQ	66000000
+#endif
+#else
+#error Unknown oscillator frequency.
+#endif
+
+/*
+ * Hardware Reset Configuration Word
+ */
+#ifdef CONFIG_CLKIN_33MHZ
+#define CONFIG_SYS_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_1X1 |\
+	HRCWL_CSB_TO_CLKIN_8X1 |\
+	HRCWL_VCO_1X2 |\
+	HRCWL_CE_PLL_VCO_DIV_4 |\
+	HRCWL_CE_PLL_DIV_1X1 |\
+	HRCWL_CE_TO_PLL_1X15 |\
+	HRCWL_CORE_TO_CSB_2X1)
+#elif defined(CONFIG_CLKIN_66MHZ)
+#define CONFIG_SYS_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_1X1 |\
+	HRCWL_CSB_TO_CLKIN_4X1 |\
+	HRCWL_VCO_1X2 |\
+	HRCWL_CE_PLL_VCO_DIV_4 |\
+	HRCWL_CE_PLL_DIV_1X1 |\
+	HRCWL_CE_TO_PLL_1X6 |\
+	HRCWL_CORE_TO_CSB_2X1)
+#endif
+
+#ifdef CONFIG_PCISLAVE
+#define CONFIG_SYS_HRCW_HIGH (\
+	HRCWH_PCI_AGENT |\
+	HRCWH_PCI1_ARBITER_DISABLE |\
+	HRCWH_PCICKDRV_DISABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0XFFF00100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT)
+#else
+#define CONFIG_SYS_HRCW_HIGH (\
+	HRCWH_PCI_HOST |\
+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_PCICKDRV_ENABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0X00000100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT)
+#endif
+
+/*
+ * System IO Config
+ */
+#define CONFIG_SYS_SICRH		0x00000000
+#define CONFIG_SYS_SICRL		0x40000000
+
+#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
+#define CONFIG_BOARD_EARLY_INIT_R
+
+/*
+ * IMMR new address
+ */
+#define CONFIG_SYS_IMMR		0xE0000000
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_DDR_BASE	0x00000000 /* DDR is system memory */
+#define CONFIG_SYS_SDRAM_BASE	CONFIG_SYS_DDR_BASE
+				/* + 256M */
+#define CONFIG_SYS_SDRAM_BASE2	(CONFIG_SYS_SDRAM_BASE + 0x10000000)
+#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN \
+					| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+
+#define CONFIG_SYS_83XX_DDR_USES_CS0
+
+#define CONFIG_DDR_ECC		/* support DDR ECC function */
+#define CONFIG_DDR_ECC_CMD	/* Use DDR ECC user commands */
+
+/*
+ * DDRCDR - DDR Control Driver Register
+ */
+#define CONFIG_SYS_DDRCDR_VALUE	0x80080001
+
+#define CONFIG_SPD_EEPROM	/* Use SPD EEPROM for DDR setup */
+#if defined(CONFIG_SPD_EEPROM)
+/*
+ * Determine DDR configuration from I2C interface.
+ */
+#define SPD_EEPROM_ADDRESS	0x52 /* DDR SODIMM */
+#else
+/*
+ * Manually set up DDR parameters
+ */
+#define CONFIG_SYS_DDR_SIZE		256 /* MB */
+#if defined(CONFIG_DDR_II)
+#define CONFIG_SYS_DDRCDR		0x80080001
+#define CONFIG_SYS_DDR_CS0_BNDS		0x0000000f
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80330102
+#define CONFIG_SYS_DDR_TIMING_0		0x00220802
+#define CONFIG_SYS_DDR_TIMING_1		0x38357322
+#define CONFIG_SYS_DDR_TIMING_2		0x2f9048c8
+#define CONFIG_SYS_DDR_TIMING_3		0x00000000
+#define CONFIG_SYS_DDR_CLK_CNTL		0x02000000
+#define CONFIG_SYS_DDR_MODE		0x47d00432
+#define CONFIG_SYS_DDR_MODE2		0x8000c000
+#define CONFIG_SYS_DDR_INTERVAL		0x03cf0080
+#define CONFIG_SYS_DDR_SDRAM_CFG	0x43000000
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
+#else
+#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
+					| CSCONFIG_ROW_BIT_13 \
+					| CSCONFIG_COL_BIT_9)
+#define CONFIG_SYS_DDR_CS1_CONFIG	CONFIG_SYS_DDR_CS0_CONFIG
+#define CONFIG_SYS_DDR_TIMING_1	0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */
+#define CONFIG_SYS_DDR_TIMING_2	0x00000800 /* may need tuning */
+#define CONFIG_SYS_DDR_CONTROL	0x42008000 /* Self refresh,2T timing */
+#define CONFIG_SYS_DDR_MODE	0x20000162 /* DLL,normal,seq,4/2.5 */
+#define CONFIG_SYS_DDR_INTERVAL	0x045b0100 /* page mode */
+#endif
+#endif
+
+/*
+ * Memory test
+ */
+#undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
+#define CONFIG_SYS_MEMTEST_START	0x00000000 /* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00100000
+
+/*
+ * The reserved memory
+ */
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE /* start of monitor */
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef	CONFIG_SYS_RAMBOOT
+#endif
+
+/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
+#define CONFIG_SYS_MONITOR_LEN	(384 * 1024) /* Reserve 384 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN	(256 * 1024) /* Reserved for malloc */
+
+/*
+ * Initial RAM Base Address Setup
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * Local Bus Configuration & Clock Setup
+ */
+#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_4
+#define CONFIG_SYS_LBC_LBCR	0x00000000
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
+#define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
+#define CONFIG_SYS_FLASH_BASE		0xFE000000 /* FLASH base address */
+#define CONFIG_SYS_FLASH_SIZE		32 /* max FLASH size is 32M */
+#define CONFIG_SYS_FLASH_PROTECTION	1 /* Use h/w Flash protection. */
+#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
+
+					/* Window base at flash base */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_32MB)
+
+#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE \
+				| BR_PS_16	/* 16 bit port */ \
+				| BR_MS_GPCM	/* MSEL = GPCM */ \
+				| BR_V)		/* valid */
+#define CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+				| OR_GPCM_XAM \
+				| OR_GPCM_CSNT \
+				| OR_GPCM_ACS_DIV2 \
+				| OR_GPCM_XACS \
+				| OR_GPCM_SCY_15 \
+				| OR_GPCM_TRLX_SET \
+				| OR_GPCM_EHTR_SET \
+				| OR_GPCM_EAD)
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	256 /* max sectors per device */
+
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+
+/*
+ * BCSR on the Local Bus
+ */
+#define CONFIG_SYS_BCSR			0xF8000000
+					/* Access window base at BCSR base */
+#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_BCSR
+#define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_64KB)
+
+#define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_BCSR \
+				| BR_PS_8 \
+				| BR_MS_GPCM \
+				| BR_V)
+#define CONFIG_SYS_OR1_PRELIM	(OR_AM_32KB \
+				| OR_GPCM_XAM \
+				| OR_GPCM_CSNT \
+				| OR_GPCM_XACS \
+				| OR_GPCM_SCY_15 \
+				| OR_GPCM_TRLX_SET \
+				| OR_GPCM_EHTR_SET \
+				| OR_GPCM_EAD)
+				/* 0xFFFFE9F7 */
+
+/*
+ * SDRAM on the Local Bus
+ */
+#define CONFIG_SYS_LBC_SDRAM_BASE	0xF0000000	/* SDRAM base address */
+#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
+
+#define CONFIG_SYS_LB_SDRAM		/* if board has SRDAM on local bus */
+
+#ifdef CONFIG_SYS_LB_SDRAM
+#define CONFIG_SYS_LBLAWBAR2		0
+#define CONFIG_SYS_LBLAWAR2		(LBLAWAR_EN | LBLAWAR_64MB)
+
+/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
+/*
+ * Base Register 2 and Option Register 2 configure SDRAM.
+ *
+ * For BR2, need:
+ *    Base address = BR[0:16] = dynamic
+ *    port size = 32-bits = BR2[19:20] = 11
+ *    no parity checking = BR2[21:22] = 00
+ *    SDRAM for MSEL = BR2[24:26] = 011
+ *    Valid = BR[31] = 1
+ *
+ * 0	4    8	  12   16   20	 24   28
+ * xxxx xxxx xxxx xxxx x001 1000 0110 0001 = 00001861
+ */
+
+/* Port size=32bit, MSEL=DRAM */
+#define CONFIG_SYS_BR2	(BR_PS_32 | BR_MS_SDRAM | BR_V) /* 0xF0001861 */
+
+/*
+ * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
+ *
+ * For OR2, need:
+ *    64MB mask for AM, OR2[0:7] = 1111 1100
+ *		   XAM, OR2[17:18] = 11
+ *    9 columns OR2[19-21] = 010
+ *    13 rows	OR2[23-25] = 100
+ *    EAD set for extra time OR[31] = 1
+ *
+ * 0	4    8	  12   16   20	 24   28
+ * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
+ */
+
+#define CONFIG_SYS_OR2	(MEG_TO_AM(CONFIG_SYS_LBC_SDRAM_SIZE) \
+			| OR_SDRAM_XAM \
+			| ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
+			| ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
+			| OR_SDRAM_EAD)
+			/* 0xFC006901 */
+
+				/* LB sdram refresh timer, about 6us */
+#define CONFIG_SYS_LBC_LSRT	0x32000000
+				/* LB refresh timer prescal, 266MHz/32 */
+#define CONFIG_SYS_LBC_MRTPR	0x20000000
+
+#define CONFIG_SYS_LBC_LSDMR_COMMON	0x0063b723
+
+/*
+ * SDRAM Controller configuration sequence.
+ */
+#define CONFIG_SYS_LBC_LSDMR_1	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
+#define CONFIG_SYS_LBC_LSDMR_2	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_3	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_4	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
+#define CONFIG_SYS_LBC_LSDMR_5	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
+
+#endif
+
+/*
+ * Windows to access Platform I/O Boards (PIB) via local bus
+ */
+#define CONFIG_SYS_PIB_BASE		0xF8008000
+#define CONFIG_SYS_PIB_WINDOW_SIZE	(32 * 1024)
+
+/* [RFC] This LBLAW only covers the 2nd window (CS5) */
+#define CONFIG_SYS_LBLAWBAR3_PRELIM	\
+			CONFIG_SYS_PIB_BASE + CONFIG_SYS_PIB_WINDOW_SIZE
+#define CONFIG_SYS_LBLAWAR3_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)
+
+/*
+ * CS4 on Local Bus, to PIB
+ */
+				/* CS4 base address at 0xf8008000 */
+#define CONFIG_SYS_BR4_PRELIM	(CONFIG_SYS_PIB_BASE \
+				| BR_PS_8 \
+				| BR_MS_GPCM \
+				| BR_V)
+				/* 0xF8008801 */
+#define CONFIG_SYS_OR4_PRELIM	(OR_AM_32KB \
+				| OR_GPCM_XAM \
+				| OR_GPCM_CSNT \
+				| OR_GPCM_XACS \
+				| OR_GPCM_SCY_15 \
+				| OR_GPCM_TRLX_SET \
+				| OR_GPCM_EHTR_SET \
+				| OR_GPCM_EAD)
+				/* 0xffffe9f7 */
+
+/*
+ * CS5 on Local Bus, to PIB
+ */
+				/* CS5 base address at 0xf8010000 */
+#define CONFIG_SYS_BR5_PRELIM	((CONFIG_SYS_PIB_BASE + \
+						CONFIG_SYS_PIB_WINDOW_SIZE) \
+				| BR_PS_8 \
+				| BR_MS_GPCM \
+				| BR_V)
+				/* 0xF8010801 */
+#define CONFIG_SYS_OR5_PRELIM	(CONFIG_SYS_PIB_BASE \
+				| OR_GPCM_XAM \
+				| OR_GPCM_CSNT \
+				| OR_GPCM_XACS \
+				| OR_GPCM_SCY_15 \
+				| OR_GPCM_TRLX_SET \
+				| OR_GPCM_EHTR_SET \
+				| OR_GPCM_EAD)
+				/* 0xffffe9f7 */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_AUTO_COMPLETE		/* add autocompletion support   */
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x52} }
+
+/*
+ * Config on-board RTC
+ */
+#define CONFIG_RTC_DS1374		/* use ds1374 rtc via i2c */
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68	/* at address 0x68 */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000 /* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
+#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000 /* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS		0xE0300000
+#define CONFIG_SYS_PCI1_IO_SIZE		0x100000 /* 1M */
+
+#define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_PCI_SLV_MEM_BUS	0x00000000
+#define CONFIG_SYS_PCI_SLV_MEM_SIZE	0x80000000
+
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+
+#define CONFIG_PCI_PNP		/* do pci plug-and-play */
+#define CONFIG_83XX_PCI_STREAMING
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
+
+#endif	/* CONFIG_PCI */
+
+
+#define CONFIG_HWCONFIG		1
+
+/*
+ * QE UEC ethernet configuration
+ */
+#define CONFIG_UEC_ETH
+#define CONFIG_ETHPRIME		"UEC0"
+#define CONFIG_PHY_MODE_NEED_CHANGE
+
+#define CONFIG_UEC_ETH1		/* GETH1 */
+
+#ifdef CONFIG_UEC_ETH1
+#define CONFIG_SYS_UEC1_UCC_NUM	0	/* UCC1 */
+#define CONFIG_SYS_UEC1_RX_CLK		QE_CLK_NONE
+#define CONFIG_SYS_UEC1_TX_CLK		QE_CLK9
+#define CONFIG_SYS_UEC1_ETH_TYPE	GIGA_ETH
+#define CONFIG_SYS_UEC1_PHY_ADDR	0
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
+#endif
+
+#define CONFIG_UEC_ETH2		/* GETH2 */
+
+#ifdef CONFIG_UEC_ETH2
+#define CONFIG_SYS_UEC2_UCC_NUM	1	/* UCC2 */
+#define CONFIG_SYS_UEC2_RX_CLK		QE_CLK_NONE
+#define CONFIG_SYS_UEC2_TX_CLK		QE_CLK4
+#define CONFIG_SYS_UEC2_ETH_TYPE	GIGA_ETH
+#define CONFIG_SYS_UEC2_PHY_ADDR	1
+#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
+#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
+#endif
+
+/*
+ * Environment
+ */
+
+#ifndef CONFIG_SYS_RAMBOOT
+	#define CONFIG_ENV_IS_IN_FLASH	1
+	#define CONFIG_ENV_ADDR		\
+			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+	#define CONFIG_ENV_SECT_SIZE	0x20000
+	#define CONFIG_ENV_SIZE		0x2000
+#else
+	#define CONFIG_SYS_NO_FLASH	1	/* Flash is not usable now */
+	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
+	#define CONFIG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_SDRAM
+
+#if defined(CONFIG_PCI)
+    #define CONFIG_CMD_PCI
+#endif
+
+#if defined(CONFIG_SYS_RAMBOOT)
+    #undef CONFIG_CMD_SAVEENV
+    #undef CONFIG_CMD_LOADS
+#endif
+
+
+#undef CONFIG_WATCHDOG		/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
+
+#if defined(CONFIG_CMD_KGDB)
+	#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */
+#else
+	#define CONFIG_SYS_CBSIZE	256 /* Console I/O Buffer Size */
+#endif
+
+				/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+				/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */
+
+/*
+ * Core HID Setup
+ */
+#define CONFIG_SYS_HID0_INIT	0x000000000
+#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
+				 HID0_ENABLE_INSTRUCTION_CACHE)
+#define CONFIG_SYS_HID2		HID2_HBE
+
+/*
+ * MMU Setup
+ */
+
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+#define CONFIG_BAT_RW
+
+/* DDR/LBC SDRAM: cacheable */
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE \
+				| BATL_PP_RW \
+				| BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+
+/* IMMRBAR & PCI IO: cache-inhibit and guarded */
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR \
+				| BATL_PP_RW \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR \
+				| BATU_BL_4M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+
+/* BCSR: cache-inhibit and guarded */
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_BCSR \
+				| BATL_PP_RW \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_BCSR \
+				| BATU_BL_128K \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+
+/* FLASH: icache cacheable, but dcache-inhibit and guarded */
+#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_FLASH_BASE \
+				| BATL_PP_RW \
+				| BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_FLASH_BASE \
+				| BATU_BL_32M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT3L	(CONFIG_SYS_FLASH_BASE \
+				| BATL_PP_RW \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
+
+/* DDR/LBC SDRAM next 256M: cacheable */
+#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_SDRAM_BASE2 \
+				| BATL_PP_RW \
+				| BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_SDRAM_BASE2 \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
+#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
+
+/* Stack in dcache: cacheable, no memory coherence */
+#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
+#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_INIT_RAM_ADDR \
+				| BATU_BL_128K \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
+#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
+
+#ifdef CONFIG_PCI
+/* PCI MEM space: cacheable */
+#define CONFIG_SYS_IBAT6L	(CONFIG_SYS_PCI1_MEM_PHYS \
+				| BATL_PP_RW \
+				| BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U	(CONFIG_SYS_PCI1_MEM_PHYS \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
+/* PCI MMIO space: cache-inhibit and guarded */
+#define CONFIG_SYS_IBAT7L	(CONFIG_SYS_PCI1_MMIO_PHYS \
+				| BATL_PP_RW \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT7U	(CONFIG_SYS_PCI1_MMIO_PHYS \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
+#else
+#define CONFIG_SYS_IBAT6L	(0)
+#define CONFIG_SYS_IBAT6U	(0)
+#define CONFIG_SYS_IBAT7L	(0)
+#define CONFIG_SYS_IBAT7U	(0)
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
+#endif
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_UEC_ETH)
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#endif
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_LOADADDR 800000	/* default location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY 6	/* -1 disables auto-boot */
+#undef	CONFIG_BOOTARGS		/* the boot command will set bootargs */
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"consoledev=ttyS0\0"						\
+	"ramdiskaddr=1000000\0"						\
+	"ramdiskfile=ramfs.83xx\0"					\
+	"fdtaddr=780000\0"						\
+	"fdtfile=mpc836x_mds.dtb\0"					\
+	""
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv bootargs root=/dev/nfs rw "				\
+		"nfsroot=$serverip:$rootpath "				\
+		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"	\
+							"$netdev:off "	\
+		"console=$consoledev,$baudrate $othbootargs;"		\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+	"setenv bootargs root=/dev/ram rw "				\
+		"console=$consoledev,$baudrate $othbootargs;"		\
+	"tftp $ramdiskaddr $ramdiskfile;"				\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+
+#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/MPC8360ERDK.h b/qemu/roms/u-boot/include/configs/MPC8360ERDK.h
new file mode 100644
index 000000000..1b8bad179
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/MPC8360ERDK.h
@@ -0,0 +1,620 @@
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ *                    Dave Liu <daveliu@freescale.com>
+ *
+ * Copyright (C) 2007 Logic Product Development, Inc.
+ *                    Peter Barada <peterb@logicpd.com>
+ *
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ *                    Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1 /* E300 family */
+#define CONFIG_QE		1 /* Has QE */
+#define CONFIG_MPC8360		1 /* MPC8360 CPU specific */
+#define CONFIG_MPC8360ERDK	1 /* MPC8360ERDK board specific */
+
+#define	CONFIG_SYS_TEXT_BASE	0xFF800000
+
+/*
+ * System Clock Setup
+ */
+#ifdef CONFIG_CLKIN_33MHZ
+#define CONFIG_83XX_CLKIN		33333333
+#define CONFIG_SYS_CLK_FREQ		33333333
+#define CONFIG_PCI_33M				1
+#define HRCWL_CSB_TO_CLKIN_MPC8360ERDK	HRCWL_CSB_TO_CLKIN_10X1
+#else
+#define CONFIG_83XX_CLKIN		66000000
+#define CONFIG_SYS_CLK_FREQ		66000000
+#define CONFIG_PCI_66M				1
+#define HRCWL_CSB_TO_CLKIN_MPC8360ERDK	HRCWL_CSB_TO_CLKIN_5X1
+#endif /* CONFIG_CLKIN_33MHZ */
+
+/*
+ * Hardware Reset Configuration Word
+ */
+#define CONFIG_SYS_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_1X1 |\
+	HRCWL_CSB_TO_CLKIN_MPC8360ERDK |\
+	HRCWL_CORE_TO_CSB_2X1 |\
+	HRCWL_CE_TO_PLL_1X15)
+
+#define CONFIG_SYS_HRCW_HIGH (\
+	HRCWH_PCI_HOST |\
+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_PCICKDRV_ENABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0X00000100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_SECONDARY_DDR_DISABLE |\
+	HRCWH_BIG_ENDIAN |\
+	HRCWH_LALE_EARLY)
+
+/*
+ * System IO Config
+ */
+#define CONFIG_SYS_SICRH		0x00000000
+#define CONFIG_SYS_SICRL		0x40000000
+
+#define CONFIG_BOARD_EARLY_INIT_R
+
+/*
+ * IMMR new address
+ */
+#define CONFIG_SYS_IMMR		0xE0000000
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN \
+					| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+
+#define CONFIG_SYS_83XX_DDR_USES_CS0
+
+#define CONFIG_DDR_ECC		/* support DDR ECC function */
+#define CONFIG_DDR_ECC_CMD	/* Use DDR ECC user commands */
+
+/*
+ * DDRCDR - DDR Control Driver Register
+ */
+#define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_DHC_EN \
+				| DDRCDR_ODT \
+				| DDRCDR_Q_DRN)
+				/* 0x80080001 */
+
+#undef CONFIG_SPD_EEPROM	/* Do not use SPD EEPROM for DDR setup */
+
+/*
+ * Manually set up DDR parameters
+ */
+#define CONFIG_DDR_II
+#define CONFIG_SYS_DDR_SIZE		256 /* MB */
+#define CONFIG_SYS_DDR_CS0_BNDS		0x0000000f
+#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
+					| CSCONFIG_ROW_BIT_13 \
+					| CSCONFIG_COL_BIT_10 \
+					| CSCONFIG_ODT_WR_ONLY_CURRENT)
+#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SDRAM_TYPE_DDR2 \
+					| SDRAM_CFG_ECC_EN)
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00001000
+#define CONFIG_SYS_DDR_CLK_CNTL		(DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+#define CONFIG_SYS_DDR_INTERVAL		((256 << SDRAM_INTERVAL_BSTOPRE_SHIFT) \
+					| (1115 << SDRAM_INTERVAL_REFINT_SHIFT))
+#define CONFIG_SYS_DDR_MODE		0x47800432
+#define CONFIG_SYS_DDR_MODE2		0x8000c000
+
+#define CONFIG_SYS_DDR_TIMING_0	((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
+				 (9 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
+				 (3 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
+				 (3 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
+				 (0 << TIMING_CFG0_WWT_SHIFT) | \
+				 (0 << TIMING_CFG0_RRT_SHIFT) | \
+				 (0 << TIMING_CFG0_WRT_SHIFT) | \
+				 (0 << TIMING_CFG0_RWT_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_1	((TIMING_CFG1_CASLAT_30) | \
+				 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
+				 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
+				 (3 << TIMING_CFG1_WRREC_SHIFT) | \
+				 (10 << TIMING_CFG1_REFREC_SHIFT) | \
+				 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
+				 (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
+				 (3 << TIMING_CFG1_PRETOACT_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_2	((9 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
+				 (4 << TIMING_CFG2_CKE_PLS_SHIFT) | \
+				 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
+				 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
+				 (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
+				 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
+				 (0 << TIMING_CFG2_CPO_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_3	0x00000000
+
+/*
+ * Memory test
+ */
+#undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
+#define CONFIG_SYS_MEMTEST_START	0x00000000 /* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00100000
+
+/*
+ * The reserved memory
+ */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_FLASH_BASE		0xFF800000 /* FLASH base address */
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef	CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN	(384 * 1024) /* Reserve 384 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN	(256 * 1024) /* Reserved for malloc */
+
+/*
+ * Initial RAM Base Address Setup
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * Local Bus Configuration & Clock Setup
+ */
+#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_4
+#define CONFIG_SYS_LBC_LBCR	0x00000000
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
+#define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
+#define CONFIG_SYS_FLASH_SIZE		8 /* max FLASH size is 32M */
+#define CONFIG_SYS_FLASH_PROTECTION	1 /* Use intel Flash protection. */
+
+					/* Window base at flash base */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_32MB)
+
+#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE \
+				| BR_PS_16	/* 16 bit port */ \
+				| BR_MS_GPCM	/* MSEL = GPCM */ \
+				| BR_V)		/* valid */
+#define CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+				| OR_UPM_XAM \
+				| OR_GPCM_CSNT \
+				| OR_GPCM_ACS_DIV2 \
+				| OR_GPCM_XACS \
+				| OR_GPCM_SCY_15 \
+				| OR_GPCM_TRLX_SET \
+				| OR_GPCM_EHTR_SET \
+				| OR_GPCM_EAD)
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	256 /* max sectors per device */
+
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+
+/*
+ * NAND flash on the local bus
+ */
+#define CONFIG_SYS_NAND_BASE		0x60000000
+#define CONFIG_CMD_NAND		1
+#define CONFIG_NAND_FSL_UPM	1
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+
+#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_NAND_BASE
+/*
+ * [RFC] Comment said 4KB window; code said 256MB window; OR1 says 64MB
+ * ... What's correct?
+ */
+#define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_256MB)
+
+/* Port size 8 bit, UPMA */
+#define CONFIG_SYS_BR1_PRELIM		(CONFIG_SYS_NAND_BASE \
+					| BR_PS_8 \
+					| BR_MS_UPMA \
+					| BR_V)
+					/* 0x60000881 */
+#define CONFIG_SYS_OR1_PRELIM		(OR_AM_64MB | OR_UPM_EAD)
+					/* 0xFC000001 */
+
+/*
+ * Fujitsu MB86277 (MINT) graphics controller
+ */
+#define CONFIG_SYS_VIDEO_BASE		0x70000000
+
+#define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_VIDEO_BASE
+#define CONFIG_SYS_LBLAWAR2_PRELIM	(LBLAWAR_EN | LBLAWAR_64MB)
+
+/* Port size 32 bit, UPMB */
+#define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_VIDEO_BASE \
+				| BR_PS_32 \
+				| BR_MS_UPMB \
+				| BR_V)
+				/* 0x000018a1 */
+#define CONFIG_SYS_OR2_PRELIM	(OR_AM_64MB | OR_UPM_EAD)
+				/* 0xFC000001 */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history */
+#define CONFIG_AUTO_COMPLETE		/* add autocompletion support */
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+/* Pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x52} }
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_PCI
+
+#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000 /* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
+#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000 /* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE		0xE0300000
+#define CONFIG_SYS_PCI1_IO_PHYS		0xE0300000
+#define CONFIG_SYS_PCI1_IO_SIZE		0x100000 /* 1M */
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+
+#define CONFIG_PCI_PNP		/* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
+
+#endif	/* CONFIG_PCI */
+
+/*
+ * QE UEC ethernet configuration
+ */
+#define CONFIG_UEC_ETH
+#define CONFIG_ETHPRIME		"UEC0"
+
+#define CONFIG_UEC_ETH1		/* GETH1 */
+
+#ifdef CONFIG_UEC_ETH1
+#define CONFIG_SYS_UEC1_UCC_NUM	0	/* UCC1 */
+#define CONFIG_SYS_UEC1_RX_CLK		QE_CLK_NONE
+#define CONFIG_SYS_UEC1_TX_CLK		QE_CLK9
+#define CONFIG_SYS_UEC1_ETH_TYPE	GIGA_ETH
+#define CONFIG_SYS_UEC1_PHY_ADDR	2
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE	PHY_INTERFACE_MODE_RGMII_RXID
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED	1000
+#endif
+
+#define CONFIG_UEC_ETH2		/* GETH2 */
+
+#ifdef CONFIG_UEC_ETH2
+#define CONFIG_SYS_UEC2_UCC_NUM	1	/* UCC2 */
+#define CONFIG_SYS_UEC2_RX_CLK		QE_CLK_NONE
+#define CONFIG_SYS_UEC2_TX_CLK		QE_CLK4
+#define CONFIG_SYS_UEC2_ETH_TYPE	GIGA_ETH
+#define CONFIG_SYS_UEC2_PHY_ADDR	4
+#define CONFIG_SYS_UEC2_INTERFACE_TYPE	PHY_INTERFACE_MODE_RGMII_RXID
+#define CONFIG_SYS_UEC2_INTERFACE_SPEED	1000
+#endif
+
+/*
+ * Environment
+ */
+
+#ifndef CONFIG_SYS_RAMBOOT
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env */
+#define CONFIG_ENV_SIZE		0x20000
+#else /* CONFIG_SYS_RAMBOOT */
+#define CONFIG_SYS_NO_FLASH	1	/* Flash is not usable now */
+#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
+#define CONFIG_ENV_SIZE		0x2000
+#endif /* CONFIG_SYS_RAMBOOT */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+
+#if defined(CONFIG_PCI)
+#define CONFIG_CMD_PCI
+#endif
+
+#if defined(CONFIG_SYS_RAMBOOT)
+#undef CONFIG_CMD_SAVEENV
+#undef CONFIG_CMD_LOADS
+#endif
+
+#undef CONFIG_WATCHDOG		/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
+
+#if defined(CONFIG_CMD_KGDB)
+	#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */
+#else
+	#define CONFIG_SYS_CBSIZE	256 /* Console I/O Buffer Size */
+#endif
+
+				/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+				/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */
+
+/*
+ * Core HID Setup
+ */
+#define CONFIG_SYS_HID0_INIT	0x000000000
+#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
+				 HID0_ENABLE_INSTRUCTION_CACHE)
+#define CONFIG_SYS_HID2		HID2_HBE
+
+/*
+ * MMU Setup
+ */
+
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
+/* DDR: cache cacheable */
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE \
+				| BATL_PP_RW \
+				| BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+
+/* IMMRBAR & PCI IO: cache-inhibit and guarded */
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR \
+				| BATL_PP_RW \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR \
+				| BATU_BL_4M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+
+/* NAND: cache-inhibit and guarded */
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_NAND_BASE \
+				| BATL_PP_RW \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_NAND_BASE \
+				| BATU_BL_64M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+
+/* FLASH: icache cacheable, but dcache-inhibit and guarded */
+#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_FLASH_BASE \
+				| BATL_PP_RW \
+				| BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_FLASH_BASE \
+				| BATU_BL_32M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT3L	(CONFIG_SYS_FLASH_BASE \
+				| BATL_PP_RW \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
+
+/* Stack in dcache: cacheable, no memory coherence */
+#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_INIT_RAM_ADDR \
+				| BATL_PP_RW)
+#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_INIT_RAM_ADDR \
+				| BATU_BL_128K \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
+#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
+
+#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_VIDEO_BASE \
+				| BATL_PP_RW \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_VIDEO_BASE \
+				| BATU_BL_64M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
+#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
+
+#ifdef CONFIG_PCI
+/* PCI MEM space: cacheable */
+#define CONFIG_SYS_IBAT6L	(CONFIG_SYS_PCI1_MEM_PHYS \
+				| BATL_PP_RW \
+				| BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U	(CONFIG_SYS_PCI1_MEM_PHYS \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
+/* PCI MMIO space: cache-inhibit and guarded */
+#define CONFIG_SYS_IBAT7L	(CONFIG_SYS_PCI1_MMIO_PHYS \
+				| BATL_PP_RW \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT7U	(CONFIG_SYS_PCI1_MMIO_PHYS \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
+#else /* CONFIG_PCI */
+#define CONFIG_SYS_IBAT6L	(0)
+#define CONFIG_SYS_IBAT6U	(0)
+#define CONFIG_SYS_IBAT7L	(0)
+#define CONFIG_SYS_IBAT7U	(0)
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
+#endif /* CONFIG_PCI */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_UEC_ETH)
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+#define CONFIG_HAS_ETH3
+#endif
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_LOADADDR	a00000
+#define CONFIG_HOSTNAME	mpc8360erdk
+#define CONFIG_BOOTFILE	"uImage"
+
+#define CONFIG_ROOTPATH		"/nfsroot/"
+
+#define	CONFIG_BOOTDELAY 2	/* -1 disables auto-boot */
+#undef	CONFIG_BOOTARGS		/* the boot command will set bootargs */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"netdev=eth0\0"							\
+	"consoledev=ttyS0\0"						\
+	"loadaddr=a00000\0"						\
+	"fdtaddr=900000\0"						\
+	"fdtfile=mpc836x_rdk.dtb\0"					\
+	"fsfile=fs\0"							\
+	"ubootfile=u-boot.bin\0"					\
+	"mtdparts=mtdparts=60000000.nand-flash:4096k(kernel),128k(dtb),"\
+							"-(rootfs)\0"	\
+	"setbootargs=setenv bootargs console=$consoledev,$baudrate "	\
+		"$mtdparts panic=1\0"					\
+	"adddhcpargs=setenv bootargs $bootargs ip=on\0"			\
+	"addnfsargs=setenv bootargs $bootargs ip=$ipaddr:$serverip:"	\
+		"$gatewayip:$netmask:$hostname:$netdev:off "		\
+		"root=/dev/nfs rw nfsroot=$serverip:$rootpath\0"	\
+	"addnandargs=setenv bootargs $bootargs root=/dev/mtdblock3 "	\
+		"rootfstype=jffs2 rw\0"					\
+	"tftp_get_uboot=tftp 100000 $ubootfile\0"			\
+	"tftp_get_kernel=tftp $loadaddr $bootfile\0"			\
+	"tftp_get_dtb=tftp $fdtaddr $fdtfile\0"				\
+	"tftp_get_fs=tftp c00000 $fsfile\0"				\
+	"nand_erase_kernel=nand erase 0 400000\0"			\
+	"nand_erase_dtb=nand erase 400000 20000\0"			\
+	"nand_erase_fs=nand erase 420000 3be0000\0"			\
+	"nand_write_kernel=nand write.jffs2 $loadaddr 0 400000\0"	\
+	"nand_write_dtb=nand write.jffs2 $fdtaddr 400000 20000\0"	\
+	"nand_write_fs=nand write.jffs2 c00000 420000 $filesize\0"	\
+	"nand_read_kernel=nand read.jffs2 $loadaddr 0 400000\0"		\
+	"nand_read_dtb=nand read.jffs2 $fdtaddr 400000 20000\0"		\
+	"nor_reflash=protect off ff800000 ff87ffff ; "			\
+		"erase ff800000 ff87ffff ; "				\
+		"cp.b 100000 ff800000 $filesize\0"			\
+	"nand_reflash_kernel=run tftp_get_kernel nand_erase_kernel "	\
+		"nand_write_kernel\0"					\
+	"nand_reflash_dtb=run tftp_get_dtb nand_erase_dtb nand_write_dtb\0"\
+	"nand_reflash_fs=run tftp_get_fs nand_erase_fs nand_write_fs\0"	\
+	"nand_reflash=run nand_reflash_kernel nand_reflash_dtb "	\
+		"nand_reflash_fs\0"					\
+	"boot_m=bootm $loadaddr - $fdtaddr\0"				\
+	"dhcpboot=dhcp ; run setbootargs adddhcpargs tftp_get_dtb boot_m\0"\
+	"nfsboot=run setbootargs addnfsargs tftp_get_kernel tftp_get_dtb "\
+		"boot_m\0"						\
+	"nandboot=run setbootargs addnandargs nand_read_kernel nand_read_dtb "\
+		"boot_m\0"						\
+	""
+
+#define CONFIG_BOOTCOMMAND "run dhcpboot"
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/MPC837XEMDS.h b/qemu/roms/u-boot/include/configs/MPC837XEMDS.h
new file mode 100644
index 000000000..695e47bf0
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/MPC837XEMDS.h
@@ -0,0 +1,714 @@
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ * Dave Liu <daveliu@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1 /* E300 family */
+#define CONFIG_MPC837x		1 /* MPC837x CPU specific */
+#define CONFIG_MPC837XEMDS	1 /* MPC837XEMDS board specific */
+
+#define	CONFIG_SYS_TEXT_BASE	0xFE000000
+
+/*
+ * System Clock Setup
+ */
+#ifdef CONFIG_PCISLAVE
+#define CONFIG_83XX_PCICLK	66000000 /* in HZ */
+#else
+#define CONFIG_83XX_CLKIN	66000000 /* in Hz */
+#endif
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_CLK_FREQ	66000000
+#endif
+
+/*
+ * Hardware Reset Configuration Word
+ * if CLKIN is 66MHz, then
+ * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz
+ */
+#define CONFIG_SYS_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_1X1 |\
+	HRCWL_SVCOD_DIV_2 |\
+	HRCWL_CSB_TO_CLKIN_6X1 |\
+	HRCWL_CORE_TO_CSB_1_5X1)
+
+#ifdef CONFIG_PCISLAVE
+#define CONFIG_SYS_HRCW_HIGH (\
+	HRCWH_PCI_AGENT |\
+	HRCWH_PCI1_ARBITER_DISABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0XFFF00100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_RL_EXT_LEGACY |\
+	HRCWH_TSEC1M_IN_RGMII |\
+	HRCWH_TSEC2M_IN_RGMII |\
+	HRCWH_BIG_ENDIAN |\
+	HRCWH_LDP_CLEAR)
+#else
+#define CONFIG_SYS_HRCW_HIGH (\
+	HRCWH_PCI_HOST |\
+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0X00000100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_RL_EXT_LEGACY |\
+	HRCWH_TSEC1M_IN_RGMII |\
+	HRCWH_TSEC2M_IN_RGMII |\
+	HRCWH_BIG_ENDIAN |\
+	HRCWH_LDP_CLEAR)
+#endif
+
+/* Arbiter Configuration Register */
+#define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth is 4 */
+#define CONFIG_SYS_ACR_RPTCNT	3	/* Arbiter repeat count is 4 */
+
+/* System Priority Control Register */
+#define CONFIG_SYS_SPCR_TSECEP	3 /* eTSEC1/2 emergency has highest priority */
+
+/*
+ * IP blocks clock configuration
+ */
+#define CONFIG_SYS_SCCR_TSEC1CM	1	/* CSB:eTSEC1 = 1:1 */
+#define CONFIG_SYS_SCCR_TSEC2CM	1	/* CSB:eTSEC2 = 1:1 */
+#define CONFIG_SYS_SCCR_SATACM	SCCR_SATACM_2	/* CSB:SATA[0:3] = 2:1 */
+
+/*
+ * System IO Config
+ */
+#define CONFIG_SYS_SICRH		0x00000000
+#define CONFIG_SYS_SICRL		0x00000000
+
+/*
+ * Output Buffer Impedance
+ */
+#define CONFIG_SYS_OBIR		0x31100000
+
+#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_HWCONFIG
+
+/*
+ * IMMR new address
+ */
+#define CONFIG_SYS_IMMR		0xE0000000
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+#define CONFIG_SYS_83XX_DDR_USES_CS0
+#define CONFIG_SYS_DDRCDR_VALUE		(DDRCDR_DHC_EN \
+					| DDRCDR_ODT \
+					| DDRCDR_Q_DRN)
+					/* 0x80080001 */ /* ODT 150ohm on SoC */
+
+#undef CONFIG_DDR_ECC		/* support DDR ECC function */
+#undef CONFIG_DDR_ECC_CMD	/* Use DDR ECC user commands */
+
+#define CONFIG_SPD_EEPROM	/* Use SPD EEPROM for DDR setup */
+#define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
+
+#if defined(CONFIG_SPD_EEPROM)
+#define SPD_EEPROM_ADDRESS	0x51 /* I2C address of DDR SODIMM SPD */
+#else
+/*
+ * Manually set up DDR parameters
+ * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM
+ * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5
+ */
+#define CONFIG_SYS_DDR_SIZE		512 /* MB */
+#define CONFIG_SYS_DDR_CS0_BNDS	0x0000001f
+#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
+			| CSCONFIG_ODT_RD_NEVER  /* ODT_RD to none */ \
+			| CSCONFIG_ODT_WR_ONLY_CURRENT  /* ODT_WR to CSn */ \
+			| CSCONFIG_ROW_BIT_14 \
+			| CSCONFIG_COL_BIT_10)
+			/* 0x80010202 */
+#define CONFIG_SYS_DDR_TIMING_3	0x00000000
+#define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
+				| (0 << TIMING_CFG0_WRT_SHIFT) \
+				| (0 << TIMING_CFG0_RRT_SHIFT) \
+				| (0 << TIMING_CFG0_WWT_SHIFT) \
+				| (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
+				| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
+				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
+				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
+				/* 0x00620802 */
+#define CONFIG_SYS_DDR_TIMING_1	((3 << TIMING_CFG1_PRETOACT_SHIFT) \
+				| (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
+				| (3 << TIMING_CFG1_ACTTORW_SHIFT) \
+				| (5 << TIMING_CFG1_CASLAT_SHIFT) \
+				| (13 << TIMING_CFG1_REFREC_SHIFT) \
+				| (3 << TIMING_CFG1_WRREC_SHIFT) \
+				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
+				| (2 << TIMING_CFG1_WRTORD_SHIFT))
+				/* 0x3935d322 */
+#define CONFIG_SYS_DDR_TIMING_2	((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
+				| (6 << TIMING_CFG2_CPO_SHIFT) \
+				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
+				| (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
+				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
+				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
+				| (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
+				/* 0x131088c8 */
+#define CONFIG_SYS_DDR_INTERVAL	((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \
+				| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
+				/* 0x03E00100 */
+#define CONFIG_SYS_DDR_SDRAM_CFG	0x43000000
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00001000 /* 1 posted refresh */
+#define CONFIG_SYS_DDR_MODE	((0x0448 << SDRAM_MODE_ESD_SHIFT) \
+				| (0x1432 << SDRAM_MODE_SD_SHIFT))
+				/* ODT 150ohm CL=3, AL=1 on SDRAM */
+#define CONFIG_SYS_DDR_MODE2	0x00000000
+#endif
+
+/*
+ * Memory test
+ */
+#undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
+#define CONFIG_SYS_MEMTEST_START	0x00040000 /* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00140000
+
+/*
+ * The reserved memory
+ */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE /* start of monitor */
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef CONFIG_SYS_RAMBOOT
+#endif
+
+/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
+#define CONFIG_SYS_MONITOR_LEN	(384 * 1024) /* Reserve 384 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN	(512 * 1024) /* Reserved for malloc */
+
+/*
+ * Initial RAM Base Address Setup
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * Local Bus Configuration & Clock Setup
+ */
+#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_8
+#define CONFIG_SYS_LBC_LBCR		0x00000000
+#define CONFIG_FSL_ELBC		1
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_CFI	/* use the Common Flash Interface */
+#define CONFIG_FLASH_CFI_DRIVER	/* use the CFI driver */
+#define CONFIG_SYS_FLASH_BASE	0xFE000000 /* FLASH base address */
+#define CONFIG_SYS_FLASH_SIZE	32 /* max FLASH size is 32M */
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* Use h/w Flash protection. */
+
+					/* Window base at flash base */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_32MB)
+
+#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE \
+				| BR_PS_16	/* 16 bit port */ \
+				| BR_MS_GPCM	/* MSEL = GPCM */ \
+				| BR_V)		/* valid */
+#define CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+				| OR_UPM_XAM \
+				| OR_GPCM_CSNT \
+				| OR_GPCM_ACS_DIV2 \
+				| OR_GPCM_XACS \
+				| OR_GPCM_SCY_15 \
+				| OR_GPCM_TRLX_SET \
+				| OR_GPCM_EHTR_SET \
+				| OR_GPCM_EAD)
+				/* 0xFE000FF7 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	256 /* max sectors per device */
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500 /* Flash Write Timeout (ms) */
+
+/*
+ * BCSR on the Local Bus
+ */
+#define CONFIG_SYS_BCSR		0xF8000000
+					/* Access window base at BCSR base */
+#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_BCSR
+#define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)
+
+#define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_BCSR \
+				| BR_PS_8 \
+				| BR_MS_GPCM \
+				| BR_V)
+				/* 0xF8000801 */
+#define CONFIG_SYS_OR1_PRELIM	(OR_AM_32KB \
+				| OR_GPCM_XAM \
+				| OR_GPCM_CSNT \
+				| OR_GPCM_XACS \
+				| OR_GPCM_SCY_15 \
+				| OR_GPCM_TRLX_SET \
+				| OR_GPCM_EHTR_SET \
+				| OR_GPCM_EAD)
+				/* 0xFFFFE9F7 */
+
+/*
+ * NAND Flash on the Local Bus
+ */
+#define CONFIG_CMD_NAND		1
+#define CONFIG_MTD_NAND_VERIFY_WRITE	1
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_NAND_FSL_ELBC	1
+
+#define CONFIG_SYS_NAND_BASE	0xE0600000
+#define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_NAND_BASE \
+				| BR_DECC_CHK_GEN	/* Use HW ECC */ \
+				| BR_PS_8		/* 8 bit port */ \
+				| BR_MS_FCM		/* MSEL = FCM */ \
+				| BR_V)			/* valid */
+#define CONFIG_SYS_OR3_PRELIM	(OR_AM_32KB \
+				| OR_FCM_BCTLD \
+				| OR_FCM_CST \
+				| OR_FCM_CHT \
+				| OR_FCM_SCY_1 \
+				| OR_FCM_RST \
+				| OR_FCM_TRLX \
+				| OR_FCM_EHTR)
+				/* 0xFFFF919E */
+
+#define CONFIG_SYS_LBLAWBAR3_PRELIM	CONFIG_SYS_NAND_BASE
+#define CONFIG_SYS_LBLAWAR3_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+/* Pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x51} }
+
+/*
+ * Config on-board RTC
+ */
+#define CONFIG_RTC_DS1374	/* use ds1374 rtc via i2c */
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68 /* at address 0x68 */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCI_MEM_BASE		0x80000000
+#define CONFIG_SYS_PCI_MEM_PHYS		CONFIG_SYS_PCI_MEM_BASE
+#define CONFIG_SYS_PCI_MEM_SIZE		0x10000000 /* 256M */
+#define CONFIG_SYS_PCI_MMIO_BASE	0x90000000
+#define CONFIG_SYS_PCI_MMIO_PHYS	CONFIG_SYS_PCI_MMIO_BASE
+#define CONFIG_SYS_PCI_MMIO_SIZE	0x10000000 /* 256M */
+#define CONFIG_SYS_PCI_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI_IO_PHYS		0xE0300000
+#define CONFIG_SYS_PCI_IO_SIZE		0x100000 /* 1M */
+
+#define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_PCI_SLV_MEM_BUS	0x00000000
+#define CONFIG_SYS_PCI_SLV_MEM_SIZE	0x80000000
+
+#define CONFIG_SYS_PCIE1_BASE		0xA0000000
+#define CONFIG_SYS_PCIE1_CFG_BASE	0xA0000000
+#define CONFIG_SYS_PCIE1_CFG_SIZE	0x08000000
+#define CONFIG_SYS_PCIE1_MEM_BASE	0xA8000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xA8000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000
+#define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xB8000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000
+
+#define CONFIG_SYS_PCIE2_BASE		0xC0000000
+#define CONFIG_SYS_PCIE2_CFG_BASE	0xC0000000
+#define CONFIG_SYS_PCIE2_CFG_SIZE	0x08000000
+#define CONFIG_SYS_PCIE2_MEM_BASE	0xC8000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xC8000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000
+#define CONFIG_SYS_PCIE2_IO_BASE	0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xD8000000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#ifndef __ASSEMBLY__
+extern int board_pci_host_broken(void);
+#endif
+#define CONFIG_PCIE
+#define CONFIG_PQ_MDS_PIB	1 /* PQ MDS Platform IO Board */
+
+#define CONFIG_HAS_FSL_DR_USB	1 /* fixup device tree for the DR USB */
+
+#define CONFIG_PCI_PNP		/* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
+#endif /* CONFIG_PCI */
+
+/*
+ * TSEC
+ */
+#define CONFIG_TSEC_ENET	/* TSEC ethernet support */
+#define CONFIG_SYS_TSEC1_OFFSET	0x24000
+#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
+#define CONFIG_SYS_TSEC2_OFFSET	0x25000
+#define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
+
+/*
+ * TSEC ethernet configuration
+ */
+#define CONFIG_MII		1 /* MII PHY management */
+#define CONFIG_TSEC1		1
+#define CONFIG_TSEC1_NAME	"eTSEC0"
+#define CONFIG_TSEC2		1
+#define CONFIG_TSEC2_NAME	"eTSEC1"
+#define TSEC1_PHY_ADDR		2
+#define TSEC2_PHY_ADDR		3
+#define TSEC1_PHY_ADDR_SGMII	8
+#define TSEC2_PHY_ADDR_SGMII	4
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME		"eTSEC1"
+
+/* SERDES */
+#define CONFIG_FSL_SERDES
+#define CONFIG_FSL_SERDES1	0xe3000
+#define CONFIG_FSL_SERDES2	0xe3100
+
+/*
+ * SATA
+ */
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1_OFFSET	0x18000
+#define CONFIG_SYS_SATA1	(CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
+#define CONFIG_SYS_SATA1_FLAGS	FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2_OFFSET	0x19000
+#define CONFIG_SYS_SATA2	(CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
+#define CONFIG_SYS_SATA2_FLAGS	FLAGS_DMA
+
+#ifdef CONFIG_FSL_SATA
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+/*
+ * Environment
+ */
+#ifndef CONFIG_SYS_RAMBOOT
+	#define CONFIG_ENV_IS_IN_FLASH	1
+	#define CONFIG_ENV_ADDR		\
+			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+	#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env */
+	#define CONFIG_ENV_SIZE		0x2000
+#else
+	#define CONFIG_SYS_NO_FLASH	1	/* Flash is not usable now */
+	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
+	#define CONFIG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_DATE
+
+#if defined(CONFIG_PCI)
+    #define CONFIG_CMD_PCI
+#endif
+
+#if defined(CONFIG_SYS_RAMBOOT)
+    #undef CONFIG_CMD_SAVEENV
+    #undef CONFIG_CMD_LOADS
+#endif
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history */
+#define CONFIG_AUTO_COMPLETE		/* add autocompletion support   */
+
+#undef CONFIG_WATCHDOG		/* watchdog disabled */
+
+#define CONFIG_MMC     1
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_ESDHC_PIN_MUX
+#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC83xx_ESDHC_ADDR
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
+
+#if defined(CONFIG_CMD_KGDB)
+	#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */
+#else
+	#define CONFIG_SYS_CBSIZE	256 /* Console I/O Buffer Size */
+#endif
+
+				/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+				/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */
+
+/*
+ * Core HID Setup
+ */
+#define CONFIG_SYS_HID0_INIT	0x000000000
+#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
+				 HID0_ENABLE_INSTRUCTION_CACHE)
+#define CONFIG_SYS_HID2		HID2_HBE
+
+/*
+ * MMU Setup
+ */
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
+/* DDR: cache cacheable */
+#define CONFIG_SYS_SDRAM_LOWER		CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_SDRAM_UPPER		(CONFIG_SYS_SDRAM_BASE + 0x10000000)
+
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_LOWER \
+				| BATL_PP_RW \
+				| BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_LOWER \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_SDRAM_UPPER \
+				| BATL_PP_RW \
+				| BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_SDRAM_UPPER \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+
+/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_IMMR \
+				| BATL_PP_RW \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_IMMR \
+				| BATU_BL_8M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+
+/* BCSR: cache-inhibit and guarded */
+#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_BCSR \
+				| BATL_PP_RW \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_BCSR \
+				| BATU_BL_128K \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
+
+/* FLASH: icache cacheable, but dcache-inhibit and guarded */
+#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_FLASH_BASE \
+				| BATL_PP_RW \
+				| BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_FLASH_BASE \
+				| BATU_BL_32M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT4L	(CONFIG_SYS_FLASH_BASE \
+				| BATL_PP_RW \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
+
+/* Stack in dcache: cacheable, no memory coherence */
+#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
+#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_INIT_RAM_ADDR \
+				| BATU_BL_128K \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
+#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
+
+#ifdef CONFIG_PCI
+/* PCI MEM space: cacheable */
+#define CONFIG_SYS_IBAT6L	(CONFIG_SYS_PCI_MEM_PHYS \
+				| BATL_PP_RW \
+				| BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U	(CONFIG_SYS_PCI_MEM_PHYS \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
+/* PCI MMIO space: cache-inhibit and guarded */
+#define CONFIG_SYS_IBAT7L	(CONFIG_SYS_PCI_MMIO_PHYS \
+				| BATL_PP_RW \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT7U	(CONFIG_SYS_PCI_MMIO_PHYS \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
+#else
+#define CONFIG_SYS_IBAT6L	(0)
+#define CONFIG_SYS_IBAT6U	(0)
+#define CONFIG_SYS_IBAT7L	(0)
+#define CONFIG_SYS_IBAT7U	(0)
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
+#endif
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#endif
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_LOADADDR 800000	/* default location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY 6	/* -1 disables auto-boot */
+#undef CONFIG_BOOTARGS		/* the boot command will set bootargs */
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"consoledev=ttyS0\0"						\
+	"ramdiskaddr=1000000\0"						\
+	"ramdiskfile=ramfs.83xx\0"					\
+	"fdtaddr=780000\0"						\
+	"fdtfile=mpc8379_mds.dtb\0"					\
+	""
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv bootargs root=/dev/nfs rw "				\
+		"nfsroot=$serverip:$rootpath "				\
+		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"	\
+							"$netdev:off "	\
+		"console=$consoledev,$baudrate $othbootargs;"		\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+	"setenv bootargs root=/dev/ram rw "				\
+		"console=$consoledev,$baudrate $othbootargs;"		\
+	"tftp $ramdiskaddr $ramdiskfile;"				\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+
+#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/MPC837XERDB.h b/qemu/roms/u-boot/include/configs/MPC837XERDB.h
new file mode 100644
index 000000000..1d1f4c0e2
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/MPC837XERDB.h
@@ -0,0 +1,746 @@
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ * Kevin Lam <kevin.lam@freescale.com>
+ * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1 /* E300 family */
+#define CONFIG_MPC837x		1 /* MPC837x CPU specific */
+#define CONFIG_MPC837XERDB	1
+
+#define	CONFIG_SYS_TEXT_BASE	0xFE000000
+
+#define CONFIG_PCI	1
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MISC_INIT_R
+#define CONFIG_HWCONFIG
+
+/*
+ * On-board devices
+ */
+#define CONFIG_TSEC_ENET		/* TSEC Ethernet support */
+#define CONFIG_VSC7385_ENET
+
+/*
+ * System Clock Setup
+ */
+#ifdef CONFIG_PCISLAVE
+#define CONFIG_83XX_PCICLK	66666667 /* in HZ */
+#else
+#define CONFIG_83XX_CLKIN	66666667 /* in Hz */
+#define CONFIG_PCIE
+#endif
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN
+#endif
+
+/*
+ * Hardware Reset Configuration Word
+ */
+#define CONFIG_SYS_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_1X1 |\
+	HRCWL_SVCOD_DIV_2 |\
+	HRCWL_CSB_TO_CLKIN_5X1 |\
+	HRCWL_CORE_TO_CSB_2X1)
+
+#ifdef CONFIG_PCISLAVE
+#define CONFIG_SYS_HRCW_HIGH (\
+	HRCWH_PCI_AGENT |\
+	HRCWH_PCI1_ARBITER_DISABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0XFFF00100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_RL_EXT_LEGACY |\
+	HRCWH_TSEC1M_IN_RGMII |\
+	HRCWH_TSEC2M_IN_RGMII |\
+	HRCWH_BIG_ENDIAN |\
+	HRCWH_LDP_CLEAR)
+#else
+#define CONFIG_SYS_HRCW_HIGH (\
+	HRCWH_PCI_HOST |\
+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0X00000100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_RL_EXT_LEGACY |\
+	HRCWH_TSEC1M_IN_RGMII |\
+	HRCWH_TSEC2M_IN_RGMII |\
+	HRCWH_BIG_ENDIAN |\
+	HRCWH_LDP_CLEAR)
+#endif
+
+/* System performance - define the value i.e. CONFIG_SYS_XXX
+*/
+
+/* Arbiter Configuration Register */
+#define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
+#define CONFIG_SYS_ACR_RPTCNT	3	/* Arbiter repeat count (0-7) */
+
+/* System Priority Control Regsiter */
+#define CONFIG_SYS_SPCR_TSECEP	3	/* eTSEC1&2 emergency priority (0-3) */
+
+/* System Clock Configuration Register */
+#define CONFIG_SYS_SCCR_TSEC1CM	1		/* eTSEC1 clock mode (0-3) */
+#define CONFIG_SYS_SCCR_TSEC2CM	1		/* eTSEC2 clock mode (0-3) */
+#define CONFIG_SYS_SCCR_SATACM	SCCR_SATACM_2	/* SATA1-4 clock mode (0-3) */
+
+/*
+ * System IO Config
+ */
+#define CONFIG_SYS_SICRH		0x08200000
+#define CONFIG_SYS_SICRL		0x00000000
+
+/*
+ * Output Buffer Impedance
+ */
+#define CONFIG_SYS_OBIR		0x30100000
+
+/*
+ * IMMR new address
+ */
+#define CONFIG_SYS_IMMR		0xE0000000
+
+/*
+ * Device configurations
+ */
+
+/* Vitesse 7385 */
+
+#ifdef CONFIG_VSC7385_ENET
+
+#define CONFIG_TSEC2
+
+/* The flash address and size of the VSC7385 firmware image */
+#define CONFIG_VSC7385_IMAGE		0xFE7FE000
+#define CONFIG_VSC7385_IMAGE_SIZE	8192
+
+#endif
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	0x03000000
+#define CONFIG_SYS_83XX_DDR_USES_CS0
+
+#define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
+
+#undef CONFIG_DDR_ECC		/* support DDR ECC function */
+#undef CONFIG_DDR_ECC_CMD	/* Use DDR ECC user commands */
+
+#undef CONFIG_NEVER_ASSERT_ODT_TO_CPU	/* Never assert ODT to internal IOs */
+
+/*
+ * Manually set up DDR parameters
+ */
+#define CONFIG_SYS_DDR_SIZE		256		/* MB */
+#define CONFIG_SYS_DDR_CS0_BNDS		0x0000000f
+#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
+					| CSCONFIG_ODT_WR_ONLY_CURRENT \
+					| CSCONFIG_ROW_BIT_13 \
+					| CSCONFIG_COL_BIT_10)
+
+#define CONFIG_SYS_DDR_TIMING_3	0x00000000
+#define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
+				| (0 << TIMING_CFG0_WRT_SHIFT) \
+				| (0 << TIMING_CFG0_RRT_SHIFT) \
+				| (0 << TIMING_CFG0_WWT_SHIFT) \
+				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
+				| (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
+				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
+				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
+				/* 0x00260802 */ /* DDR400 */
+#define CONFIG_SYS_DDR_TIMING_1	((3 << TIMING_CFG1_PRETOACT_SHIFT) \
+				| (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
+				| (3 << TIMING_CFG1_ACTTORW_SHIFT) \
+				| (7 << TIMING_CFG1_CASLAT_SHIFT) \
+				| (13 << TIMING_CFG1_REFREC_SHIFT) \
+				| (3 << TIMING_CFG1_WRREC_SHIFT) \
+				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
+				| (2 << TIMING_CFG1_WRTORD_SHIFT))
+				/* 0x3937d322 */
+#define CONFIG_SYS_DDR_TIMING_2	((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
+				| (5 << TIMING_CFG2_CPO_SHIFT) \
+				| (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
+				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
+				| (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
+				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
+				| (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
+				/* 0x02984cc8 */
+
+#define CONFIG_SYS_DDR_INTERVAL	((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
+				| (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
+				/* 0x06090100 */
+
+#if defined(CONFIG_DDR_2T_TIMING)
+#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
+					| SDRAM_CFG_SDRAM_TYPE_DDR2 \
+					| SDRAM_CFG_32_BE \
+					| SDRAM_CFG_2T_EN)
+					/* 0x43088000 */
+#else
+#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
+					| SDRAM_CFG_SDRAM_TYPE_DDR2)
+					/* 0x43000000 */
+#endif
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00001000 /* 1 posted refresh */
+#define CONFIG_SYS_DDR_MODE		((0x0406 << SDRAM_MODE_ESD_SHIFT) \
+					| (0x0442 << SDRAM_MODE_SD_SHIFT))
+					/* 0x04400442 */ /* DDR400 */
+#define CONFIG_SYS_DDR_MODE2		0x00000000
+
+/*
+ * Memory test
+ */
+#undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
+#define CONFIG_SYS_MEMTEST_START	0x00040000 /* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x0ef70010
+
+/*
+ * The reserved memory
+ */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE /* start of monitor */
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef	CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN	(384 * 1024) /* Reserve 384 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN	(512 * 1024) /* Reserved for malloc */
+
+/*
+ * Initial RAM Base Address Setup
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * Local Bus Configuration & Clock Setup
+ */
+#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_8
+#define CONFIG_SYS_LBC_LBCR		0x00000000
+#define CONFIG_FSL_ELBC		1
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
+#define CONFIG_FLASH_CFI_DRIVER	/* use the CFI driver */
+#define CONFIG_SYS_FLASH_BASE		0xFE000000 /* FLASH base address */
+#define CONFIG_SYS_FLASH_SIZE		8 /* max FLASH size is 32M */
+
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* Use h/w Flash protection. */
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* display empty sectors */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	/* buffer up multiple bytes */
+
+					/* Window base at flash base */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_LBLAWAR0_PRELIM	0x80000016	/* 8 MB window size */
+
+#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE \
+				| BR_PS_16	/* 16 bit port */ \
+				| BR_MS_GPCM	/* MSEL = GPCM */ \
+				| BR_V)		/* valid */
+#define CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+				| OR_GPCM_XACS \
+				| OR_GPCM_SCY_9 \
+				| OR_GPCM_EHTR_SET \
+				| OR_GPCM_EAD)
+				/* 0xFF800191 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	256 /* max sectors per device */
+
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+/*
+ * NAND Flash on the Local Bus
+ */
+#define CONFIG_SYS_NAND_BASE	0xE0600000
+#define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_NAND_BASE \
+				| BR_DECC_CHK_GEN	/* Use HW ECC */ \
+				| BR_PS_8		/* 8 bit port */ \
+				| BR_MS_FCM		/* MSEL = FCM */ \
+				| BR_V)			/* valid */
+#define CONFIG_SYS_OR1_PRELIM	(OR_AM_32KB \
+				| OR_FCM_CSCT \
+				| OR_FCM_CST \
+				| OR_FCM_CHT \
+				| OR_FCM_SCY_1 \
+				| OR_FCM_TRLX \
+				| OR_FCM_EHTR)
+#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_NAND_BASE
+#define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)
+
+/* Vitesse 7385 */
+
+#define CONFIG_SYS_VSC7385_BASE	0xF0000000
+
+#ifdef CONFIG_VSC7385_ENET
+
+#define CONFIG_SYS_BR2_PRELIM		(CONFIG_SYS_VSC7385_BASE \
+					| BR_PS_8 \
+					| BR_MS_GPCM \
+					| BR_V)
+					/* 0xF0000801 */
+#define CONFIG_SYS_OR2_PRELIM		(OR_AM_128KB \
+					| OR_GPCM_CSNT \
+					| OR_GPCM_XACS \
+					| OR_GPCM_SCY_15 \
+					| OR_GPCM_SETA \
+					| OR_GPCM_TRLX_SET \
+					| OR_GPCM_EHTR_SET \
+					| OR_GPCM_EAD)
+					/* 0xfffe09ff */
+
+					/* Access Base */
+#define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_VSC7385_BASE
+#define CONFIG_SYS_LBLAWAR2_PRELIM	(LBLAWAR_EN | LBLAWAR_128KB)
+
+#endif
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
+
+/* SERDES */
+#define CONFIG_FSL_SERDES
+#define CONFIG_FSL_SERDES1	0xe3000
+#define CONFIG_FSL_SERDES2	0xe3100
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+/* Pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x51} }
+
+/*
+ * Config on-board RTC
+ */
+#define CONFIG_RTC_DS1374	/* use ds1374 rtc via i2c */
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68 /* at address 0x68 */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCI_MEM_BASE		0x80000000
+#define CONFIG_SYS_PCI_MEM_PHYS		CONFIG_SYS_PCI_MEM_BASE
+#define CONFIG_SYS_PCI_MEM_SIZE		0x10000000 /* 256M */
+#define CONFIG_SYS_PCI_MMIO_BASE	0x90000000
+#define CONFIG_SYS_PCI_MMIO_PHYS	CONFIG_SYS_PCI_MMIO_BASE
+#define CONFIG_SYS_PCI_MMIO_SIZE	0x10000000 /* 256M */
+#define CONFIG_SYS_PCI_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI_IO_PHYS		0xE0300000
+#define CONFIG_SYS_PCI_IO_SIZE		0x100000 /* 1M */
+
+#define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_PCI_SLV_MEM_BUS	0x00000000
+#define CONFIG_SYS_PCI_SLV_MEM_SIZE	0x80000000
+
+#define CONFIG_SYS_PCIE1_BASE		0xA0000000
+#define CONFIG_SYS_PCIE1_CFG_BASE	0xA0000000
+#define CONFIG_SYS_PCIE1_CFG_SIZE	0x08000000
+#define CONFIG_SYS_PCIE1_MEM_BASE	0xA8000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xA8000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000
+#define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xB8000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000
+
+#define CONFIG_SYS_PCIE2_BASE		0xC0000000
+#define CONFIG_SYS_PCIE2_CFG_BASE	0xC0000000
+#define CONFIG_SYS_PCIE2_CFG_SIZE	0x08000000
+#define CONFIG_SYS_PCIE2_MEM_BASE	0xC8000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xC8000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000
+#define CONFIG_SYS_PCIE2_IO_BASE	0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xD8000000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_PCI_PNP		/* do pci plug-and-play */
+
+#undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
+#endif	/* CONFIG_PCI */
+
+/*
+ * TSEC
+ */
+#ifdef CONFIG_TSEC_ENET
+
+#define CONFIG_GMII			/* MII PHY management */
+
+#define CONFIG_TSEC1
+
+#ifdef CONFIG_TSEC1
+#define CONFIG_HAS_ETH0
+#define CONFIG_TSEC1_NAME		"TSEC0"
+#define CONFIG_SYS_TSEC1_OFFSET		0x24000
+#define TSEC1_PHY_ADDR			2
+#define TSEC1_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC1_PHYIDX			0
+#endif
+
+#ifdef CONFIG_TSEC2
+#define CONFIG_HAS_ETH1
+#define CONFIG_TSEC2_NAME		"TSEC1"
+#define CONFIG_SYS_TSEC2_OFFSET		0x25000
+#define TSEC2_PHY_ADDR			0x1c
+#define TSEC2_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_PHYIDX			0
+#endif
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME			"TSEC0"
+
+#endif
+
+/*
+ * SATA
+ */
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1_OFFSET	0x18000
+#define CONFIG_SYS_SATA1	(CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
+#define CONFIG_SYS_SATA1_FLAGS	FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2_OFFSET	0x19000
+#define CONFIG_SYS_SATA2	(CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
+#define CONFIG_SYS_SATA2_FLAGS	FLAGS_DMA
+
+#ifdef CONFIG_FSL_SATA
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+/*
+ * Environment
+ */
+#ifndef CONFIG_SYS_RAMBOOT
+	#define CONFIG_ENV_IS_IN_FLASH	1
+	#define CONFIG_ENV_ADDR		\
+			(CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN)
+	#define CONFIG_ENV_SECT_SIZE	0x10000	/* 64K (one sector) for env */
+	#define CONFIG_ENV_SIZE		0x4000
+#else
+	#define CONFIG_SYS_NO_FLASH	1	/* Flash is not usable now */
+	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-0x1000)
+	#define CONFIG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_DATE
+
+#if defined(CONFIG_PCI)
+#define CONFIG_CMD_PCI
+#endif
+
+#if defined(CONFIG_SYS_RAMBOOT)
+#undef CONFIG_CMD_SAVEENV
+#undef CONFIG_CMD_LOADS
+#endif
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history */
+#define CONFIG_AUTO_COMPLETE		/* add autocompletion support */
+
+#undef CONFIG_WATCHDOG		/* watchdog disabled */
+
+#define CONFIG_MMC     1
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_ESDHC_PIN_MUX
+#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC83xx_ESDHC_ADDR
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP	/* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000 /* default load address */
+
+#if defined(CONFIG_CMD_KGDB)
+	#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */
+#else
+	#define CONFIG_SYS_CBSIZE	256 /* Console I/O Buffer Size */
+#endif
+
+				/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+				/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */
+
+/*
+ * Core HID Setup
+ */
+#define CONFIG_SYS_HID0_INIT	0x000000000
+#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK \
+				| HID0_ENABLE_INSTRUCTION_CACHE)
+#define CONFIG_SYS_HID2		HID2_HBE
+
+/*
+ * MMU Setup
+ */
+
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
+/* DDR: cache cacheable */
+#define CONFIG_SYS_SDRAM_LOWER		CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_SDRAM_UPPER		(CONFIG_SYS_SDRAM_BASE + 0x10000000)
+
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_LOWER \
+				| BATL_PP_RW \
+				| BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_LOWER \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_SDRAM_UPPER \
+				| BATL_PP_RW \
+				| BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_SDRAM_UPPER \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+
+/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_IMMR \
+				| BATL_PP_RW \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_IMMR \
+				| BATU_BL_8M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+
+/* L2 Switch: cache-inhibit and guarded */
+#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_VSC7385_BASE \
+				| BATL_PP_RW \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_VSC7385_BASE \
+				| BATU_BL_128K \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
+
+/* FLASH: icache cacheable, but dcache-inhibit and guarded */
+#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_FLASH_BASE \
+				| BATL_PP_RW \
+				| BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_FLASH_BASE \
+				| BATU_BL_32M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT4L	(CONFIG_SYS_FLASH_BASE \
+				| BATL_PP_RW \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
+
+/* Stack in dcache: cacheable, no memory coherence */
+#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
+#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_INIT_RAM_ADDR \
+				| BATU_BL_128K \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
+#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
+
+#ifdef CONFIG_PCI
+/* PCI MEM space: cacheable */
+#define CONFIG_SYS_IBAT6L	(CONFIG_SYS_PCI_MEM_PHYS \
+				| BATL_PP_RW \
+				| BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U	(CONFIG_SYS_PCI_MEM_PHYS \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
+/* PCI MMIO space: cache-inhibit and guarded */
+#define CONFIG_SYS_IBAT7L	(CONFIG_SYS_PCI_MMIO_PHYS \
+				| BATL_PP_RW \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT7U	(CONFIG_SYS_PCI_MMIO_PHYS \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
+#else
+#define CONFIG_SYS_IBAT6L	(0)
+#define CONFIG_SYS_IBAT6U	(0)
+#define CONFIG_SYS_IBAT7L	(0)
+#define CONFIG_SYS_IBAT7U	(0)
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
+#endif
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_HAS_FSL_DR_USB
+
+#define CONFIG_NETDEV		"eth1"
+
+#define CONFIG_HOSTNAME		mpc837x_rdb
+#define CONFIG_ROOTPATH		"/nfsroot"
+#define CONFIG_RAMDISKFILE	"rootfs.ext2.gz.uboot"
+#define CONFIG_BOOTFILE		"uImage"
+				/* U-Boot image on TFTP server */
+#define CONFIG_UBOOTPATH	"u-boot.bin"
+#define CONFIG_FDTFILE		"mpc8379_rdb.dtb"
+
+				/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		800000
+#define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"netdev=" CONFIG_NETDEV "\0"				\
+	"uboot=" CONFIG_UBOOTPATH "\0"					\
+	"tftpflash=tftp $loadaddr $uboot;"				\
+		"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
+			" +$filesize; "	\
+		"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
+			" +$filesize; "	\
+		"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
+			" $filesize; "	\
+		"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
+			" +$filesize; "	\
+		"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
+			" $filesize\0"	\
+	"fdtaddr=780000\0"						\
+	"fdtfile=" CONFIG_FDTFILE "\0"					\
+	"ramdiskaddr=1000000\0"						\
+	"ramdiskfile=" CONFIG_RAMDISKFILE "\0"				\
+	"console=ttyS0\0"						\
+	"setbootargs=setenv bootargs "					\
+		"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
+	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath "	\
+		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"	\
+							"$netdev:off "	\
+		"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv rootdev /dev/nfs;"					\
+	"run setbootargs;"						\
+	"run setipargs;"						\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+	"setenv rootdev /dev/ram;"					\
+	"run setbootargs;"						\
+	"tftp $ramdiskaddr $ramdiskfile;"				\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/MPC8536DS.h b/qemu/roms/u-boot/include/configs/MPC8536DS.h
new file mode 100644
index 000000000..72f5fde16
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/MPC8536DS.h
@@ -0,0 +1,825 @@
+/*
+ * Copyright 2007-2009,2010-2012 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * mpc8536ds board configuration file
+ *
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+#include "../board/freescale/common/ics307_clk.h"
+
+#ifdef CONFIG_36BIT
+#define CONFIG_PHYS_64BIT	1
+#endif
+
+#ifdef CONFIG_NAND
+#define CONFIG_NAND_U_BOOT		1
+#define CONFIG_RAMBOOT_NAND		1
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
+#else
+#define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds
+#define CONFIG_SYS_TEXT_BASE	0xf8f82000
+#endif /* CONFIG_NAND_SPL */
+#endif
+
+#ifdef CONFIG_SDCARD
+#define CONFIG_RAMBOOT_SDCARD		1
+#define CONFIG_SYS_TEXT_BASE	0xf8f40000
+#define CONFIG_RESET_VECTOR_ADDRESS	0xf8fffffc
+#endif
+
+#ifdef CONFIG_SPIFLASH
+#define CONFIG_RAMBOOT_SPIFLASH		1
+#define CONFIG_SYS_TEXT_BASE	0xf8f40000
+#define CONFIG_RESET_VECTOR_ADDRESS	0xf8fffffc
+#endif
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xeff40000
+#endif
+
+#ifndef	CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE		1	/* BOOKE */
+#define CONFIG_E500		1	/* BOOKE e500 family */
+#define CONFIG_MPC8536		1
+#define CONFIG_MPC8536DS	1
+
+#define CONFIG_FSL_ELBC		1	/* Has Enhanced localbus controller */
+#define CONFIG_SPI_FLASH	1	/* Has SPI Flash */
+#define CONFIG_PCI		1	/* Enable PCI/PCIE */
+#define CONFIG_PCI1		1	/* Enable PCI controller 1 */
+#define CONFIG_PCIE1		1	/* PCIE controler 1 (slot 1) */
+#define CONFIG_PCIE2		1	/* PCIE controler 2 (slot 2) */
+#define CONFIG_PCIE3		1	/* PCIE controler 3 (ULI bridge) */
+#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
+#define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
+
+#define CONFIG_FSL_LAW		1	/* Use common FSL init code */
+#define CONFIG_E1000		1	/* Defind e1000 pci Ethernet card*/
+
+#define CONFIG_TSEC_ENET		/* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk() /* sysclk for MPC85xx */
+#define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk()
+#define CONFIG_ICS307_REFCLK_HZ	33333000  /* ICS307 clock chip ref freq */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* toggle branch predition */
+
+#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
+
+#define CONFIG_ENABLE_36BIT_PHYS	1
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP			1
+#define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
+#endif
+
+#define CONFIG_SYS_MEMTEST_START 0x00010000	/* skip exception vectors */
+#define CONFIG_SYS_MEMTEST_END   0x1f000000	/* skip u-boot at top of RAM */
+#define CONFIG_PANIC_HANG	/* do not reset board on panic */
+
+/*
+ * Config the L2 Cache as L2 SRAM
+ */
+#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	0xff8f80000ull
+#else
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#endif
+#define CONFIG_SYS_L2_SIZE		(512 << 10)
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+
+#define CONFIG_SYS_CCSRBAR		0xffe00000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+
+#if defined(CONFIG_NAND_SPL)
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#endif
+
+/* DDR Setup */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_FSL_DDR2
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
+#define CONFIG_DDR_SPD
+
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	2
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
+#define CONFIG_SYS_SPD_BUS_NUM		1
+
+/* These are used when DDR doesn't use SPD. */
+#define CONFIG_SYS_SDRAM_SIZE		256	/* DDR is 256MB */
+#define CONFIG_SYS_DDR_CS0_BNDS	0x0000001F
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80010102 /* Enable, no interleaving */
+#define CONFIG_SYS_DDR_TIMING_3	0x00000000
+#define CONFIG_SYS_DDR_TIMING_0	0x00260802
+#define CONFIG_SYS_DDR_TIMING_1	0x3935d322
+#define CONFIG_SYS_DDR_TIMING_2	0x14904cc8
+#define CONFIG_SYS_DDR_MODE_1		0x00480432
+#define CONFIG_SYS_DDR_MODE_2		0x00000000
+#define CONFIG_SYS_DDR_INTERVAL	0x06180100
+#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
+#define CONFIG_SYS_DDR_CLK_CTRL	0x03800000
+#define CONFIG_SYS_DDR_OCD_CTRL	0x00000000
+#define CONFIG_SYS_DDR_OCD_STATUS	0x00000000
+#define CONFIG_SYS_DDR_CONTROL	0xC3008000	/* Type = DDR2 */
+#define CONFIG_SYS_DDR_CONTROL2	0x04400010
+
+#define CONFIG_SYS_DDR_ERR_INT_EN	0x0000000d
+#define CONFIG_SYS_DDR_ERR_DIS		0x00000000
+#define CONFIG_SYS_DDR_SBE		0x00010000
+
+/* Make sure required options are set */
+#ifndef CONFIG_SPD_EEPROM
+#error ("CONFIG_SPD_EEPROM is required")
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+
+/*
+ * Memory map -- xxx -this is wrong, needs updating
+ *
+ * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
+ * 0x8000_0000	0xbfff_ffff	PCI Express Mem		1G non-cacheable
+ * 0xc000_0000	0xdfff_ffff	PCI			512M non-cacheable
+ * 0xe100_0000	0xe3ff_ffff	PCI IO range		4M non-cacheable
+ *
+ * Localbus cacheable (TBD)
+ * 0xXXXX_XXXX	0xXXXX_XXXX	SRAM			YZ M Cacheable
+ *
+ * Localbus non-cacheable
+ * 0xe000_0000	0xe7ff_ffff	Promjet/free		128M non-cacheable
+ * 0xe800_0000	0xefff_ffff	FLASH			128M non-cacheable
+ * 0xffa0_0000	0xffaf_ffff	NAND			1M non-cacheable
+ * 0xffdf_0000	0xffdf_7fff	PIXIS			32K non-cacheable TLB0
+ * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K Cacheable TLB0
+ * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
+ */
+
+/*
+ * Local Bus Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE		0xe0000000	/* start of FLASH 128M */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_FLASH_BASE_PHYS	0xfe0000000ull
+#else
+#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+#endif
+
+#define CONFIG_FLASH_BR_PRELIM \
+	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
+#define CONFIG_FLASH_OR_PRELIM	0xf8000ff7
+
+#define CONFIG_SYS_BR1_PRELIM \
+		(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
+		 | BR_PS_16 | BR_V)
+#define CONFIG_SYS_OR1_PRELIM	0xf8000ff7
+
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \
+				      CONFIG_SYS_FLASH_BASE_PHYS }
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_RAMBOOT_SDCARD) || \
+    defined(CONFIG_RAMBOOT_SPIFLASH)
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#else
+#undef CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
+
+#define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
+
+#define CONFIG_HWCONFIG			/* enable hwconfig */
+#define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
+#define PIXIS_BASE	0xffdf0000	/* PIXIS registers */
+#ifdef CONFIG_PHYS_64BIT
+#define PIXIS_BASE_PHYS	0xfffdf0000ull
+#else
+#define PIXIS_BASE_PHYS	PIXIS_BASE
+#endif
+
+#define CONFIG_SYS_BR3_PRELIM	(BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR3_PRELIM	0xffffeff7	/* 32KB but only 4k mapped */
+
+#define PIXIS_ID		0x0	/* Board ID at offset 0 */
+#define PIXIS_VER		0x1	/* Board version at offset 1 */
+#define PIXIS_PVER		0x2	/* PIXIS FPGA version at offset 2 */
+#define PIXIS_CSR   		0x3	/* PIXIS General control/status register */
+#define PIXIS_RST		0x4	/* PIXIS Reset Control register */
+#define PIXIS_PWR		0x5	/* PIXIS Power status register */
+#define PIXIS_AUX		0x6	/* Auxiliary 1 register */
+#define PIXIS_SPD		0x7	/* Register for SYSCLK speed */
+#define PIXIS_AUX2		0x8	/* Auxiliary 2 register */
+#define PIXIS_VCTL		0x10	/* VELA Control Register */
+#define PIXIS_VSTAT		0x11	/* VELA Status Register */
+#define PIXIS_VCFGEN0		0x12	/* VELA Config Enable 0 */
+#define PIXIS_VCFGEN1		0x13	/* VELA Config Enable 1 */
+#define PIXIS_VCORE0	 	0x14	/* VELA VCORE0 Register */
+#define PIXIS_VBOOT		0x16	/* VELA VBOOT Register */
+#define PIXIS_VBOOT_LBMAP	0xe0	/* VBOOT - CFG_LBMAP */
+#define PIXIS_VBOOT_LBMAP_NOR0	0x00	/* cfg_lbmap - boot from NOR 0 */
+#define PIXIS_VBOOT_LBMAP_NOR1	0x01	/* cfg_lbmap - boot from NOR 1 */
+#define PIXIS_VBOOT_LBMAP_NOR2	0x02	/* cfg_lbmap - boot from NOR 2 */
+#define PIXIS_VBOOT_LBMAP_NOR3	0x03	/* cfg_lbmap - boot from NOR 3 */
+#define PIXIS_VBOOT_LBMAP_PJET	0x04	/* cfg_lbmap - boot from projet */
+#define PIXIS_VBOOT_LBMAP_NAND	0x05	/* cfg_lbmap - boot from NAND */
+#define PIXIS_VSPEED0		0x17	/* VELA VSpeed 0 */
+#define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
+#define PIXIS_VSPEED2		0x19	/* VELA VSpeed 2 */
+#define PIXIS_VSYSCLK0		0x1A	/* VELA SYSCLK0 Register */
+#define PIXIS_VSYSCLK1		0x1B	/* VELA SYSCLK1 Register */
+#define PIXIS_VSYSCLK2		0x1C	/* VELA SYSCLK2 Register */
+#define PIXIS_VDDRCLK0		0x1D	/* VELA DDRCLK0 Register */
+#define PIXIS_VDDRCLK1		0x1E	/* VELA DDRCLK1 Register */
+#define PIXIS_VDDRCLK2		0x1F	/* VELA DDRCLK2 Register */
+#define PIXIS_VWATCH		0x24    /* Watchdog Register */
+#define PIXIS_LED		0x25    /* LED Register */
+
+#define PIXIS_SPD_SYSCLK	0x7	/* SYSCLK option */
+
+/* old pixis referenced names */
+#define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
+#define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
+#define CONFIG_SYS_PIXIS_VBOOT_MASK	0x4e
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000	/* Size of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+		(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN	(256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN	(1024 * 1024)	/* Reserved for malloc */
+
+#ifndef CONFIG_NAND_SPL
+#define CONFIG_SYS_NAND_BASE		0xffa00000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_NAND_BASE_PHYS	0xfffa00000ull
+#else
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#endif
+#else
+#define CONFIG_SYS_NAND_BASE		0xfff00000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_NAND_BASE_PHYS	0xffff00000ull
+#else
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#endif
+#endif
+#define CONFIG_SYS_NAND_BASE_LIST     { CONFIG_SYS_NAND_BASE,\
+				CONFIG_SYS_NAND_BASE + 0x40000, \
+				CONFIG_SYS_NAND_BASE + 0x80000, \
+				CONFIG_SYS_NAND_BASE + 0xC0000}
+#define CONFIG_SYS_MAX_NAND_DEVICE	4
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND		1
+#define CONFIG_NAND_FSL_ELBC	1
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+
+/* NAND boot: 4K NAND loader config */
+#define CONFIG_SYS_NAND_SPL_SIZE	0x1000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	((768 << 10) - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_DST	(CONFIG_SYS_INIT_L2_ADDR)
+#define CONFIG_SYS_NAND_U_BOOT_START \
+		(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(0)
+#define CONFIG_SYS_NAND_U_BOOT_RELOC	(CONFIG_SYS_INIT_L2_END - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
+
+/* NAND flash config */
+#define CONFIG_SYS_NAND_BR_PRELIM \
+		(BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+		| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
+		| BR_PS_8		/* Port Size = 8 bit */ \
+		| BR_MS_FCM		/* MSEL = FCM */ \
+		| BR_V)			/* valid */
+#define CONFIG_SYS_NAND_OR_PRELIM	(0xFFFC0000	/* length 256K */ \
+		| OR_FCM_PGS		/* Large Page*/ \
+		| OR_FCM_CSCT \
+		| OR_FCM_CST \
+		| OR_FCM_CHT \
+		| OR_FCM_SCY_1 \
+		| OR_FCM_TRLX \
+		| OR_FCM_EHTR)
+
+#ifdef CONFIG_RAMBOOT_NAND
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#define CONFIG_SYS_BR2_PRELIM  CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
+#define CONFIG_SYS_OR2_PRELIM  CONFIG_FLASH_OR_PRELIM	/* NOR Options */
+#else
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_FLASH_OR_PRELIM	/* NOR Options */
+#define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
+#define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#endif
+
+#define CONFIG_SYS_BR4_PRELIM \
+		(BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
+		| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
+		| BR_PS_8		/* Port Size = 8 bit */ \
+		| BR_MS_FCM		/* MSEL = FCM */ \
+		| BR_V)			/* valid */
+#define CONFIG_SYS_OR4_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#define CONFIG_SYS_BR5_PRELIM \
+		(BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \
+		| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
+		| BR_PS_8		/* Port Size = 8 bit */ \
+		| BR_MS_FCM		/* MSEL = FCM */ \
+		| BR_V)			/* valid */
+#define CONFIG_SYS_OR5_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+
+#define CONFIG_SYS_BR6_PRELIM \
+		(BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \
+		| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
+		| BR_PS_8		/* Port Size = 8 bit */ \
+		| BR_MS_FCM		/* MSEL = FCM */ \
+		| BR_V)			/* valid */
+#define CONFIG_SYS_OR6_PRELIM	CONFIG_SYS_NAND_OR_PRELIM	/* NAND Options */
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR + 0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT		1
+#define CONFIG_OF_BOARD_SETUP		1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x29} }
+
+/*
+ * I2C2 EEPROM
+ */
+#define CONFIG_ID_EEPROM
+#ifdef CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#endif
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_EEPROM_BUS_NUM	1
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#define CONFIG_HARD_SPI
+#define CONFIG_FSL_ESPI
+
+#if defined(CONFIG_SPI_FLASH)
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED	10000000
+#define CONFIG_SF_DEFAULT_MODE	0
+#endif
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+#define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCI1_MEM_BUS		0xf0000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	0xc00000000ull
+#else
+#define CONFIG_SYS_PCI1_MEM_BUS		0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
+#endif
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_IO_VIRT		0xffc00000
+#define CONFIG_SYS_PCI1_IO_BUS		0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCI1_IO_PHYS		0xfffc00000ull
+#else
+#define CONFIG_SYS_PCI1_IO_PHYS		0xffc00000
+#endif
+#define CONFIG_SYS_PCI1_IO_SIZE		0x00010000	/* 64k */
+
+/* controller 1, Slot 1, tgtid 1, Base address a000 */
+#define CONFIG_SYS_PCIE1_NAME		"Slot 1"
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0x90000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xf8000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc10000000ull
+#else
+#define CONFIG_SYS_PCIE1_MEM_BUS	0x90000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0x90000000
+#endif
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x08000000	/* 128M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc10000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xfffc10000ull
+#else
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xffc10000
+#endif
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 2, Slot 2, tgtid 2, Base address 9000 */
+#define CONFIG_SYS_PCIE2_NAME		"Slot 2"
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0x98000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xf8000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc18000000ull
+#else
+#define CONFIG_SYS_PCIE2_MEM_BUS	0x98000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0x98000000
+#endif
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x08000000	/* 128M */
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xffc20000
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xfffc20000ull
+#else
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xffc20000
+#endif
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 3, direct to uli, tgtid 3, Base address 8000 */
+#define CONFIG_SYS_PCIE3_NAME		"Slot 3"
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0xa0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc20000000ull
+#else
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xa0000000
+#endif
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xffc30000
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xfffc30000ull
+#else
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xffc30000
+#endif
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+
+/*PCIE video card used*/
+#define VIDEO_IO_OFFSET		CONFIG_SYS_PCIE3_IO_VIRT
+
+/*PCI video card used*/
+/*#define VIDEO_IO_OFFSET	CONFIG_SYS_PCI1_IO_VIRT*/
+
+/* video */
+#define CONFIG_VIDEO
+
+#if defined(CONFIG_VIDEO)
+#define CONFIG_BIOSEMU
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_ATI_RADEON_FB
+#define CONFIG_VIDEO_LOGO
+/*#define CONFIG_CONSOLE_CURSOR*/
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT
+#endif
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+#undef CONFIG_RTL8139
+
+#ifndef CONFIG_PCI_PNP
+	#define PCI_ENET0_IOADDR	CONFIG_SYS_PCI1_IO_BUS
+	#define PCI_ENET0_MEMADDR	CONFIG_SYS_PCI1_IO_BUS
+	#define PCI_IDSEL_NUMBER	0x11	/* IDSEL = AD11 */
+#endif
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+
+#endif	/* CONFIG_PCI */
+
+/* SATA */
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
+
+#ifdef CONFIG_FSL_SATA
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+#if defined(CONFIG_TSEC_ENET)
+
+#define CONFIG_MII		1	/* MII PHY management */
+#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define CONFIG_TSEC3	1
+#define CONFIG_TSEC3_NAME	"eTSEC3"
+
+#define CONFIG_FSL_SGMII_RISER	1
+#define SGMII_RISER_PHY_OFFSET	0x1c
+
+#define TSEC1_PHY_ADDR		1	/* TSEC1 -> PHY1 */
+#define TSEC3_PHY_ADDR		0	/* TSEC3 -> PHY0 */
+
+#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+
+#define TSEC1_PHYIDX		0
+#define TSEC3_PHYIDX		0
+
+#define CONFIG_ETHPRIME		"eTSEC1"
+
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+
+#if defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_RAMBOOT_NAND)
+#define CONFIG_ENV_IS_IN_NAND	1
+#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_RANGE	(3 * CONFIG_ENV_SIZE)
+#elif defined(CONFIG_RAMBOOT_SPIFLASH)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS	0
+#define CONFIG_ENV_SPI_CS	0
+#define CONFIG_ENV_SPI_MAX_HZ	10000000
+#define CONFIG_ENV_SPI_MODE	0
+#define CONFIG_ENV_SIZE		0x2000	/* 8KB */
+#define CONFIG_ENV_OFFSET	0xF0000
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#elif defined(CONFIG_RAMBOOT_SDCARD)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_FSL_FIXED_MMC_LOCATION
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_SYS_MMC_ENV_DEV  0
+#else
+	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
+	#define CONFIG_ENV_SIZE		0x2000
+#endif
+#else
+	#define CONFIG_ENV_IS_IN_FLASH	1
+	#define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+	#define CONFIG_ENV_SIZE		0x2000
+	#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
+
+#if defined(CONFIG_PCI)
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+#define CONFIG_MMC     1
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#endif
+
+/*
+ * USB
+ */
+#define CONFIG_HAS_FSL_MPH_USB
+#ifdef CONFIG_HAS_FSL_MPH_USB
+#define CONFIG_USB_EHCI
+
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_USB_STORAGE
+#endif
+#endif
+
+#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE \
+		+ sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+/* The mac addresses for all ethernet interface */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_ETHADDR	00:E0:0C:02:00:FD
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR	00:E0:0C:02:01:FD
+#define CONFIG_HAS_ETH2
+#define CONFIG_ETH2ADDR	00:E0:0C:02:02:FD
+#define CONFIG_HAS_ETH3
+#define CONFIG_ETH3ADDR	00:E0:0C:02:03:FD
+#endif
+
+#define CONFIG_IPADDR		192.168.1.254
+
+#define CONFIG_HOSTNAME		unknown
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	u-boot.bin /* U-Boot image on TFTP server */
+
+#define CONFIG_SERVERIP		192.168.1.1
+#define CONFIG_GATEWAYIP	192.168.1.1
+#define CONFIG_NETMASK		255.255.255.0
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE	115200
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+"netdev=eth0\0"						\
+"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
+"tftpflash=tftpboot $loadaddr $uboot; "			\
+	"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
+		" +$filesize; "	\
+	"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
+		" +$filesize; "	\
+	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
+		" $filesize; "	\
+	"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
+		" +$filesize; "	\
+	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
+		" $filesize\0"	\
+"consoledev=ttyS0\0"				\
+"ramdiskaddr=2000000\0"			\
+"ramdiskfile=8536ds/ramdisk.uboot\0"		\
+"fdtaddr=c00000\0"				\
+"fdtfile=8536ds/mpc8536ds.dtb\0"		\
+"bdev=sda3\0"					\
+"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
+
+#define CONFIG_HDBOOT				\
+ "setenv bootargs root=/dev/$bdev rw "		\
+ "console=$consoledev,$baudrate $othbootargs;"	\
+ "tftp $loadaddr $bootfile;"			\
+ "tftp $fdtaddr $fdtfile;"			\
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND		\
+ "setenv bootargs root=/dev/nfs rw "	\
+ "nfsroot=$serverip:$rootpath "		\
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;"	\
+ "tftp $loadaddr $bootfile;"		\
+ "tftp $fdtaddr $fdtfile;"		\
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND		\
+ "setenv bootargs root=/dev/ram rw "	\
+ "console=$consoledev,$baudrate $othbootargs;"	\
+ "tftp $ramdiskaddr $ramdiskfile;"	\
+ "tftp $loadaddr $bootfile;"		\
+ "tftp $fdtaddr $fdtfile;"		\
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_HDBOOT
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/MPC8540ADS.h b/qemu/roms/u-boot/include/configs/MPC8540ADS.h
new file mode 100644
index 000000000..37c2b9415
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/MPC8540ADS.h
@@ -0,0 +1,460 @@
+/*
+ * Copyright 2004, 2011 Freescale Semiconductor.
+ * (C) Copyright 2002,2003 Motorola,Inc.
+ * Xianghua Xiao <X.Xiao@motorola.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * mpc8540ads board configuration file
+ *
+ * Please refer to doc/README.mpc85xx for more info.
+ *
+ * Make sure you change the MAC address and other network params first,
+ * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE		1	/* BOOKE */
+#define CONFIG_E500		1	/* BOOKE e500 family */
+#define CONFIG_MPC8540		1	/* MPC8540 specific */
+#define CONFIG_MPC8540ADS	1	/* MPC8540ADS board specific */
+
+/*
+ * default CCARBAR is at 0xff700000
+ * assume U-Boot is less than 0.5MB
+ */
+#define	CONFIG_SYS_TEXT_BASE	0xfff80000
+
+#ifndef CONFIG_HAS_FEC
+#define CONFIG_HAS_FEC		1	/* 8540 has FEC */
+#endif
+
+#define CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
+#define CONFIG_TSEC_ENET		/* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_FSL_LAW		1	/* Use common FSL init code */
+
+/*
+ * sysclk for MPC85xx
+ *
+ * Two valid values are:
+ *    33000000
+ *    66000000
+ *
+ * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
+ * is likely the desired value here, so that is now the default.
+ * The board, however, can run at 66MHz.  In any event, this value
+ * must match the settings of some switches.  Details can be found
+ * in the README.mpc85xxads.
+ *
+ * XXX -- Can't we run at 66 MHz, anyway?  PCI should drop to
+ * 33MHz to accommodate, based on a PCI pin.
+ * Note that PCI-X won't work at 33MHz.
+ */
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_CLK_FREQ	33000000
+#endif
+
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* toggle branch predition */
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+
+#define CONFIG_SYS_CCSRBAR		0xe0000000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+
+/* DDR Setup */
+#define CONFIG_SYS_FSL_DDR1
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_SPD
+#undef CONFIG_FSL_DDR_INTERACTIVE
+
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
+
+/* These are used when DDR doesn't use SPD. */
+#define CONFIG_SYS_SDRAM_SIZE	128		/* DDR is 128MB */
+#define CONFIG_SYS_DDR_CS0_BNDS	0x00000007	/* 0-128MB */
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80000002
+#define CONFIG_SYS_DDR_TIMING_1	0x37344321
+#define CONFIG_SYS_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
+#define CONFIG_SYS_DDR_CONTROL		0xc2000000	/* unbuffered,no DYN_PWR */
+#define CONFIG_SYS_DDR_MODE		0x00000062	/* DLL,normal,seq,4/2.5 */
+#define CONFIG_SYS_DDR_INTERVAL	0x05200100	/* autocharge,no open page */
+
+/*
+ * SDRAM on the Local Bus
+ */
+#define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
+#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
+
+#define CONFIG_SYS_FLASH_BASE		0xff000000	/* start of FLASH 16M */
+#define CONFIG_SYS_BR0_PRELIM		0xff001801	/* port size 32bit */
+
+#define CONFIG_SYS_OR0_PRELIM		0xff006ff7	/* 16MB Flash */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	64		/* sectors per device */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef  CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+
+/*
+ * Local Bus Definitions
+ */
+
+/*
+ * Base Register 2 and Option Register 2 configure SDRAM.
+ * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
+ *
+ * For BR2, need:
+ *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
+ *    port-size = 32-bits = BR2[19:20] = 11
+ *    no parity checking = BR2[21:22] = 00
+ *    SDRAM for MSEL = BR2[24:26] = 011
+ *    Valid = BR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
+ *
+ * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
+ * FIXME: the top 17 bits of BR2.
+ */
+
+#define CONFIG_SYS_BR2_PRELIM		0xf0001861
+
+/*
+ * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
+ *
+ * For OR2, need:
+ *    64MB mask for AM, OR2[0:7] = 1111 1100
+ *		   XAM, OR2[17:18] = 11
+ *    9 columns OR2[19-21] = 010
+ *    13 rows   OR2[23-25] = 100
+ *    EAD set for extra time OR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
+ */
+
+#define CONFIG_SYS_OR2_PRELIM		0xfc006901
+
+#define CONFIG_SYS_LBC_LCRR		0x00030004    /* LB clock ratio reg */
+#define CONFIG_SYS_LBC_LBCR		0x00000000    /* LB config reg */
+#define CONFIG_SYS_LBC_LSRT		0x20000000    /* LB sdram refresh timer */
+#define CONFIG_SYS_LBC_MRTPR		0x20000000    /* LB refresh timer prescal*/
+
+#define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_BSMA1516	\
+				| LSDMR_RFCR5		\
+				| LSDMR_PRETOACT3	\
+				| LSDMR_ACTTORW3	\
+				| LSDMR_BL8		\
+				| LSDMR_WRC2		\
+				| LSDMR_CL3		\
+				| LSDMR_RFEN		\
+				)
+
+/*
+ * SDRAM Controller configuration sequence.
+ */
+#define CONFIG_SYS_LBC_LSDMR_1	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
+#define CONFIG_SYS_LBC_LSDMR_2	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_3	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_4	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
+#define CONFIG_SYS_LBC_LSDMR_5	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
+
+
+/*
+ * 32KB, 8-bit wide for ADS config reg
+ */
+#define CONFIG_SYS_BR4_PRELIM          0xf8000801
+#define CONFIG_SYS_OR4_PRELIM		0xffffe1f1
+#define CONFIG_SYS_BCSR		(CONFIG_SYS_BR4_PRELIM & 0xffff8000)
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)    /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)    /* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX     1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE    1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef  CONFIG_SYS_HUSH_PARSER
+#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT		1
+#define CONFIG_OF_BOARD_SETUP		1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
+
+/* RapidIO MMU */
+#define CONFIG_SYS_RIO_MEM_VIRT	0xc0000000	/* base address */
+#define CONFIG_SYS_RIO_MEM_BUS	0xc0000000	/* base address */
+#define CONFIG_SYS_RIO_MEM_PHYS	0xc0000000
+#define CONFIG_SYS_RIO_MEM_SIZE	0x20000000	/* 128M */
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+#define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCI1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCI1_IO_VIRT	0xe2000000
+#define CONFIG_SYS_PCI1_IO_BUS	0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
+#define CONFIG_SYS_PCI1_IO_SIZE	0x100000	/* 1M */
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+    #define PCI_ENET0_IOADDR	0xe0000000
+    #define PCI_ENET0_MEMADDR	0xe0000000
+    #define PCI_IDSEL_NUMBER	0x0c	/* slot0->3(IDSEL)=12->15 */
+#endif
+
+#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
+
+#endif	/* CONFIG_PCI */
+
+
+#if defined(CONFIG_TSEC_ENET)
+
+#define CONFIG_MII		1	/* MII PHY management */
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"TSEC1"
+#define TSEC1_PHY_ADDR		0
+#define TSEC2_PHY_ADDR		1
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
+
+
+#if CONFIG_HAS_FEC
+#define CONFIG_MPC85XX_FEC	1
+#define CONFIG_MPC85XX_FEC_NAME		"FEC"
+#define FEC_PHY_ADDR		3
+#define FEC_PHYIDX		0
+#define FEC_FLAGS		0
+#endif
+
+/* Options are: TSEC[0-1], FEC */
+#define CONFIG_ETHPRIME		"TSEC0"
+
+#endif	/* CONFIG_TSEC_ENET */
+
+
+/*
+ * Environment
+ */
+#ifndef CONFIG_SYS_RAMBOOT
+  #define CONFIG_ENV_IS_IN_FLASH	1
+  #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
+  #define CONFIG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
+  #define CONFIG_ENV_SIZE		0x2000
+#else
+  #define CONFIG_SYS_NO_FLASH		1	/* Flash is not usable now */
+  #define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
+  #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
+  #define CONFIG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_SETEXPR
+
+#if defined(CONFIG_PCI)
+    #define CONFIG_CMD_PCI
+#endif
+
+#if defined(CONFIG_SYS_RAMBOOT)
+    #undef CONFIG_CMD_SAVEENV
+    #undef CONFIG_CMD_LOADS
+#endif
+
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+#if defined(CONFIG_CMD_KGDB)
+    #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+    #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+
+/*
+ * Environment Configuration
+ */
+
+/* The mac addresses for all ethernet interface */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_ETHADDR   00:E0:0C:00:00:FD
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
+#define CONFIG_HAS_ETH2
+#define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
+#endif
+
+#define CONFIG_IPADDR    192.168.1.253
+
+#define CONFIG_HOSTNAME		unknown
+#define CONFIG_ROOTPATH		"/nfsroot"
+#define CONFIG_BOOTFILE		"your.uImage"
+
+#define CONFIG_SERVERIP  192.168.1.1
+#define CONFIG_GATEWAYIP 192.168.1.1
+#define CONFIG_NETMASK   255.255.255.0
+
+#define CONFIG_LOADADDR  200000	/* default location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE	115200
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				        \
+   "netdev=eth0\0"                                                      \
+   "consoledev=ttyS0\0"                                                 \
+   "ramdiskaddr=1000000\0"						\
+   "ramdiskfile=your.ramdisk.u-boot\0"					\
+   "fdtaddr=400000\0"							\
+   "fdtfile=your.fdt.dtb\0"
+
+#define CONFIG_NFSBOOTCOMMAND	                                        \
+   "setenv bootargs root=/dev/nfs rw "                                  \
+      "nfsroot=$serverip:$rootpath "                                    \
+      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+      "console=$consoledev,$baudrate $othbootargs;"                     \
+   "tftp $loadaddr $bootfile;"                                          \
+   "tftp $fdtaddr $fdtfile;"						\
+   "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+   "setenv bootargs root=/dev/ram rw "                                  \
+      "console=$consoledev,$baudrate $othbootargs;"                     \
+   "tftp $ramdiskaddr $ramdiskfile;"                                    \
+   "tftp $loadaddr $bootfile;"                                          \
+   "tftp $fdtaddr $fdtfile;"						\
+   "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/MPC8541CDS.h b/qemu/roms/u-boot/include/configs/MPC8541CDS.h
new file mode 100644
index 000000000..5d229a0d2
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/MPC8541CDS.h
@@ -0,0 +1,471 @@
+/*
+ * Copyright 2004, 2011 Freescale Semiconductor.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * mpc8541cds board configuration file
+ *
+ * Please refer to doc/README.mpc85xxcds for more info.
+ *
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE		1	/* BOOKE */
+#define CONFIG_E500		1	/* BOOKE e500 family */
+#define CONFIG_CPM2		1	/* has CPM2 */
+#define CONFIG_MPC8541		1	/* MPC8541 specific */
+#define CONFIG_MPC8541CDS	1	/* MPC8541CDS board specific */
+
+#define	CONFIG_SYS_TEXT_BASE	0xfff80000
+
+#define CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
+#define CONFIG_TSEC_ENET		/* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_FSL_LAW		1	/* Use common FSL init code */
+
+#define CONFIG_FSL_VIA
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_clock_freq(void);
+#endif
+#define CONFIG_SYS_CLK_FREQ	get_clock_freq() /* sysclk for MPC85xx */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			    /* toggle L2 cache	*/
+#define CONFIG_BTB			    /* toggle branch predition */
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+
+#define CONFIG_SYS_CCSRBAR		0xe0000000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+
+/* DDR Setup */
+#define CONFIG_SYS_FSL_DDR1
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_SPD
+#undef CONFIG_FSL_DDR_INTERACTIVE
+
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
+
+/*
+ * Make sure required options are set
+ */
+#ifndef CONFIG_SPD_EEPROM
+#error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+/*
+ * Local Bus Definitions
+ */
+
+/*
+ * FLASH on the Local Bus
+ * Two banks, 8M each, using the CFI driver.
+ * Boot from BR0/OR0 bank at 0xff00_0000
+ * Alternate BR1/OR1 bank at 0xff80_0000
+ *
+ * BR0, BR1:
+ *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
+ *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
+ *    Port Size = 16 bits = BRx[19:20] = 10
+ *    Use GPCM = BRx[24:26] = 000
+ *    Valid = BRx[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001    BR0
+ * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001    BR1
+ *
+ * OR0, OR1:
+ *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
+ *    Reserved ORx[17:18] = 11, confusion here?
+ *    CSNT = ORx[20] = 1
+ *    ACS = half cycle delay = ORx[21:22] = 11
+ *    SCY = 6 = ORx[24:27] = 0110
+ *    TRLX = use relaxed timing = ORx[29] = 1
+ *    EAD = use external address latch delay = OR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    ORx
+ */
+
+#define CONFIG_SYS_FLASH_BASE		0xff000000	/* start of FLASH 8M */
+
+#define CONFIG_SYS_BR0_PRELIM		0xff801001
+#define CONFIG_SYS_BR1_PRELIM		0xff001001
+
+#define	CONFIG_SYS_OR0_PRELIM		0xff806e65
+#define	CONFIG_SYS_OR1_PRELIM		0xff806e65
+
+#define CONFIG_SYS_FLASH_BANKS_LIST	{0xff800000, CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	128		/* sectors per device */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+
+/*
+ * SDRAM on the Local Bus
+ */
+#define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
+#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
+
+/*
+ * Base Register 2 and Option Register 2 configure SDRAM.
+ * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
+ *
+ * For BR2, need:
+ *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
+ *    port-size = 32-bits = BR2[19:20] = 11
+ *    no parity checking = BR2[21:22] = 00
+ *    SDRAM for MSEL = BR2[24:26] = 011
+ *    Valid = BR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
+ *
+ * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
+ * FIXME: the top 17 bits of BR2.
+ */
+
+#define CONFIG_SYS_BR2_PRELIM          0xf0001861
+
+/*
+ * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
+ *
+ * For OR2, need:
+ *    64MB mask for AM, OR2[0:7] = 1111 1100
+ *		   XAM, OR2[17:18] = 11
+ *    9 columns OR2[19-21] = 010
+ *    13 rows   OR2[23-25] = 100
+ *    EAD set for extra time OR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
+ */
+
+#define CONFIG_SYS_OR2_PRELIM		0xfc006901
+
+#define CONFIG_SYS_LBC_LCRR		0x00030004    /* LB clock ratio reg */
+#define CONFIG_SYS_LBC_LBCR		0x00000000    /* LB config reg */
+#define CONFIG_SYS_LBC_LSRT		0x20000000  /* LB sdram refresh timer */
+#define CONFIG_SYS_LBC_MRTPR		0x00000000  /* LB refresh timer prescal*/
+
+/*
+ * Common settings for all Local Bus SDRAM commands.
+ * At run time, either BSMA1516 (for CPU 1.1)
+ *                  or BSMA1617 (for CPU 1.0) (old)
+ * is OR'ed in too.
+ */
+#define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_RFCR16		\
+				| LSDMR_PRETOACT7	\
+				| LSDMR_ACTTORW7	\
+				| LSDMR_BL8		\
+				| LSDMR_WRC4		\
+				| LSDMR_CL3		\
+				| LSDMR_RFEN		\
+				)
+
+/*
+ * The CADMUS registers are connected to CS3 on CDS.
+ * The new memory map places CADMUS at 0xf8000000.
+ *
+ * For BR3, need:
+ *    Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
+ *    port-size = 8-bits  = BR[19:20] = 01
+ *    no parity checking  = BR[21:22] = 00
+ *    GPMC for MSEL       = BR[24:26] = 000
+ *    Valid               = BR[31]    = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
+ *
+ * For OR3, need:
+ *    1 MB mask for AM,   OR[0:16]  = 1111 1111 1111 0000 0
+ *    disable buffer ctrl OR[19]    = 0
+ *    CSNT                OR[20]    = 1
+ *    ACS                 OR[21:22] = 11
+ *    XACS                OR[23]    = 1
+ *    SCY 15 wait states  OR[24:27] = 1111	max is suboptimal but safe
+ *    SETA                OR[28]    = 0
+ *    TRLX                OR[29]    = 1
+ *    EHTR                OR[30]    = 1
+ *    EAD extra time      OR[31]    = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
+ */
+
+#define CONFIG_FSL_CADMUS
+
+#define CADMUS_BASE_ADDR 0xf8000000
+#define CONFIG_SYS_BR3_PRELIM   0xf8000801
+#define CONFIG_SYS_OR3_PRELIM   0xfff00ff7
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000	    /* Size of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX     2
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE    1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef  CONFIG_SYS_HUSH_PARSER
+#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT		1
+#define CONFIG_OF_BOARD_SETUP		1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_CCID
+#define CONFIG_SYS_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+#define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCI1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCI1_IO_VIRT	0xe2000000
+#define CONFIG_SYS_PCI1_IO_BUS	0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
+#define CONFIG_SYS_PCI1_IO_SIZE	0x100000	/* 1M */
+
+#define CONFIG_SYS_PCI2_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCI2_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCI2_MEM_PHYS	0xa0000000
+#define CONFIG_SYS_PCI2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCI2_IO_VIRT	0xe2100000
+#define CONFIG_SYS_PCI2_IO_BUS	0x00000000
+#define CONFIG_SYS_PCI2_IO_PHYS	0xe2100000
+#define CONFIG_SYS_PCI2_IO_SIZE	0x100000	/* 1M */
+
+#ifdef CONFIG_LEGACY
+#define BRIDGE_ID 17
+#define VIA_ID 2
+#else
+#define BRIDGE_ID 28
+#define VIA_ID 4
+#endif
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_MPC85XX_PCI2
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
+
+#endif	/* CONFIG_PCI */
+
+
+#if defined(CONFIG_TSEC_ENET)
+
+#define CONFIG_MII		1	/* MII PHY management */
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"TSEC1"
+#define TSEC1_PHY_ADDR		0
+#define TSEC2_PHY_ADDR		1
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME		"TSEC0"
+
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
+#define CONFIG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
+#define CONFIG_ENV_SIZE		0x2000
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
+
+#if defined(CONFIG_PCI)
+    #define CONFIG_CMD_PCI
+#endif
+
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+/* The mac addresses for all ethernet interface */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_ETHADDR   00:E0:0C:00:00:FD
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
+#define CONFIG_HAS_ETH2
+#define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
+#endif
+
+#define CONFIG_IPADDR    192.168.1.253
+
+#define CONFIG_HOSTNAME  unknown
+#define CONFIG_ROOTPATH  "/nfsroot"
+#define CONFIG_BOOTFILE  "your.uImage"
+
+#define CONFIG_SERVERIP  192.168.1.1
+#define CONFIG_GATEWAYIP 192.168.1.1
+#define CONFIG_NETMASK   255.255.255.0
+
+#define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
+
+#define CONFIG_BOOTDELAY 10       /* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS           /* the boot command will set bootargs*/
+
+#define CONFIG_BAUDRATE	115200
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				        \
+   "netdev=eth0\0"                                                      \
+   "consoledev=ttyS1\0"                                                 \
+   "ramdiskaddr=600000\0"                                               \
+   "ramdiskfile=your.ramdisk.u-boot\0"					\
+   "fdtaddr=400000\0"							\
+   "fdtfile=your.fdt.dtb\0"
+
+#define CONFIG_NFSBOOTCOMMAND	                                        \
+   "setenv bootargs root=/dev/nfs rw "                                  \
+      "nfsroot=$serverip:$rootpath "                                    \
+      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+      "console=$consoledev,$baudrate $othbootargs;"                     \
+   "tftp $loadaddr $bootfile;"                                          \
+   "tftp $fdtaddr $fdtfile;"						\
+   "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+   "setenv bootargs root=/dev/ram rw "                                  \
+      "console=$consoledev,$baudrate $othbootargs;"                     \
+   "tftp $ramdiskaddr $ramdiskfile;"                                    \
+   "tftp $loadaddr $bootfile;"                                          \
+   "bootm $loadaddr $ramdiskaddr"
+
+#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/MPC8544DS.h b/qemu/roms/u-boot/include/configs/MPC8544DS.h
new file mode 100644
index 000000000..dade6d3b8
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/MPC8544DS.h
@@ -0,0 +1,520 @@
+/*
+ * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * mpc8544ds board configuration file
+ *
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE		1	/* BOOKE */
+#define CONFIG_E500		1	/* BOOKE e500 family */
+#define CONFIG_MPC8544		1
+#define CONFIG_MPC8544DS	1
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xfff80000
+#endif
+
+#define CONFIG_PCI		1	/* Enable PCI/PCIE */
+#define CONFIG_PCI1		1	/* PCI controller 1 */
+#define CONFIG_PCIE1		1	/* PCIE controler 1 (slot 1) */
+#define CONFIG_PCIE2		1	/* PCIE controler 2 (slot 2) */
+#define CONFIG_PCIE3		1	/* PCIE controler 3 (ULI bridge) */
+#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
+#define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
+
+#define CONFIG_FSL_LAW		1	/* Use common FSL init code */
+#define CONFIG_E1000		1	/* Defind e1000 pci Ethernet card*/
+
+#define CONFIG_TSEC_ENET		/* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_board_sys_clk(unsigned long dummy);
+#endif
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0) /* sysclk for MPC85xx */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* toggle branch predition */
+
+/*
+ * Only possible on E500 Version 2 or newer cores.
+ */
+#define CONFIG_ENABLE_36BIT_PHYS	1
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+#define CONFIG_PANIC_HANG	/* do not reset board on panic */
+
+#define CONFIG_SYS_CCSRBAR		0xe0000000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+
+/* DDR Setup */
+#define CONFIG_SYS_FSL_DDR2
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
+#define CONFIG_DDR_SPD
+
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
+
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	2
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
+
+/* Make sure required options are set */
+#ifndef CONFIG_SPD_EEPROM
+#error ("CONFIG_SPD_EEPROM is required")
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
+ *
+ * 0x8000_0000	0xbfff_ffff	PCI Express Mem		1G non-cacheable
+ *
+ * 0xc000_0000	0xdfff_ffff	PCI			512M non-cacheable
+ *
+ * 0xe000_0000	0xe00f_ffff	CCSR			1M non-cacheable
+ * 0xe100_0000	0xe3ff_ffff	PCI IO range		4M non-cacheable
+ *
+ * Localbus cacheable
+ *
+ * 0xf000_0000	0xf3ff_ffff	SDRAM			64M Cacheable
+ * 0xf401_0000	0xf401_3fff	L1 for stack		4K Cacheable TLB0
+ *
+ * Localbus non-cacheable
+ *
+ * 0xf800_0000	0xf80f_ffff	NVRAM/CADMUS (*)	1M non-cacheable
+ * 0xff00_0000	0xff7f_ffff	FLASH (2nd bank)	8M non-cacheable
+ * 0xff80_0000	0xffff_ffff	FLASH (boot bank)	8M non-cacheable
+ *
+ */
+
+/*
+ * Local Bus Definitions
+ */
+#define CONFIG_SYS_BOOT_BLOCK		0xfc000000	/* boot TLB */
+
+#define CONFIG_SYS_FLASH_BASE		0xff800000	/* start of FLASH 8M */
+
+#define CONFIG_SYS_BR0_PRELIM		0xff801001
+#define CONFIG_SYS_BR1_PRELIM		0xfe801001
+
+#define CONFIG_SYS_OR0_PRELIM		0xff806e65
+#define CONFIG_SYS_OR1_PRELIM		0xff806e65
+
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE}
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	128		/* sectors per device */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
+#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+#define CONFIG_SYS_LBC_NONCACHE_BASE	0xf8000000
+
+#define CONFIG_SYS_BR2_PRELIM		0xf8201001	/* port size 16bit */
+#define CONFIG_SYS_OR2_PRELIM		0xfff06ff7	/* 1MB Compact Flash area*/
+
+#define CONFIG_SYS_BR3_PRELIM		0xf8100801	/* port size 8bit */
+#define CONFIG_SYS_OR3_PRELIM		0xfff06ff7	/* 1MB PIXIS area*/
+
+#define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
+#define PIXIS_BASE	0xf8100000	/* PIXIS registers */
+#define PIXIS_ID		0x0	/* Board ID at offset 0 */
+#define PIXIS_VER		0x1	/* Board version at offset 1 */
+#define PIXIS_PVER		0x2	/* PIXIS FPGA version at offset 2 */
+#define PIXIS_RST		0x4	/* PIXIS Reset Control register */
+#define PIXIS_AUX		0x6	/* PIXIS Auxiliary register; Scratch
+					 * register */
+#define PIXIS_SPD		0x7	/* Register for SYSCLK speed */
+#define PIXIS_VCTL		0x10	/* VELA Control Register */
+#define PIXIS_VCFGEN0		0x12	/* VELA Config Enable 0 */
+#define PIXIS_VCFGEN1		0x13	/* VELA Config Enable 1 */
+#define PIXIS_VBOOT		0x16	/* VELA VBOOT Register */
+#define PIXIS_VBOOT_FMAP	0x80	/* VBOOT - CFG_FLASHMAP */
+#define PIXIS_VBOOT_FBANK	0x40	/* VBOOT - CFG_FLASHBANK */
+#define PIXIS_VSPEED0		0x17	/* VELA VSpeed 0 */
+#define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
+#define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
+#define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
+#define PIXIS_VSPEED2		0x1d	/* VELA VSpeed 2 */
+#define CONFIG_SYS_PIXIS_VBOOT_MASK	0x40    /* Reset altbank mask*/
+#define PIXIS_VSPEED2_TSEC1SER	0x2
+#define PIXIS_VSPEED2_TSEC3SER	0x1
+#define PIXIS_VCFGEN1_TSEC1SER	0x20
+#define PIXIS_VCFGEN1_TSEC3SER	0x40
+#define PIXIS_VSPEED2_MASK	(PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER)
+#define PIXIS_VCFGEN1_MASK	(PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER)
+
+
+#define CONFIG_SYS_INIT_RAM_LOCK      1
+#define CONFIG_SYS_INIT_RAM_ADDR      0xf4010000      /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_SIZE       0x00004000      /* Size of used area in RAM */
+
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT		1
+#define CONFIG_OF_BOARD_SETUP		1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+#define CONFIG_SYS_PCIE_VIRT		0x80000000	/* 1G PCIE TLB */
+#define CONFIG_SYS_PCIE_PHYS		0x80000000	/* 1G PCIE TLB */
+#define CONFIG_SYS_PCI_VIRT		0xc0000000	/* 512M PCI TLB */
+#define CONFIG_SYS_PCI_PHYS		0xc0000000	/* 512M PCI TLB */
+
+#define CONFIG_SYS_PCI1_MEM_VIRT	0xc0000000
+#define CONFIG_SYS_PCI1_MEM_BUS	0xc0000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	0xc0000000
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCI1_IO_VIRT	0xe1000000
+#define CONFIG_SYS_PCI1_IO_BUS	0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS	0xe1000000
+#define CONFIG_SYS_PCI1_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 2, Slot 1, tgtid 1, Base address 9000 */
+#define CONFIG_SYS_PCIE2_NAME		"Slot 1"
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCIE2_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0x80000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xe1010000
+#define CONFIG_SYS_PCIE2_IO_BUS	0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xe1010000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 1, Slot 2,tgtid 2, Base address a000 */
+#define CONFIG_SYS_PCIE1_NAME		"Slot 2"
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xe1020000
+#define CONFIG_SYS_PCIE1_IO_BUS	0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xe1020000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 3, direct to uli, tgtid 3, Base address b000 */
+#define CONFIG_SYS_PCIE3_NAME		"ULI"
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0xb0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xb0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xb0000000
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x00100000	/* 1M */
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xb0100000	/* reuse mem LAW */
+#define CONFIG_SYS_PCIE3_IO_BUS	0x00000000
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xb0100000	/* reuse mem LAW */
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00100000	/* 1M */
+#define CONFIG_SYS_PCIE3_MEM_VIRT2	0xb0200000
+#define CONFIG_SYS_PCIE3_MEM_BUS2	0xb0200000
+#define CONFIG_SYS_PCIE3_MEM_PHYS2	0xb0200000
+#define CONFIG_SYS_PCIE3_MEM_SIZE2	0x00200000	/* 1M */
+
+#if defined(CONFIG_PCI)
+
+/*PCIE video card used*/
+#define VIDEO_IO_OFFSET		CONFIG_SYS_PCIE2_IO_VIRT
+
+/*PCI video card used*/
+/*#define VIDEO_IO_OFFSET	CONFIG_SYS_PCI1_IO_VIRT*/
+
+/* video */
+#define CONFIG_VIDEO
+
+#if defined(CONFIG_VIDEO)
+#define CONFIG_BIOSEMU
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_ATI_RADEON_FB
+#define CONFIG_VIDEO_LOGO
+/*#define CONFIG_CONSOLE_CURSOR*/
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
+#endif
+
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+#define CONFIG_RTL8139
+
+#ifndef CONFIG_PCI_PNP
+	#define PCI_ENET0_IOADDR	CONFIG_SYS_PCI1_IO_BUS
+	#define PCI_ENET0_MEMADDR	CONFIG_SYS_PCI1_IO_BUS
+	#define PCI_IDSEL_NUMBER	0x11	/* IDSEL = AD11 */
+#endif
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SCSI_AHCI
+
+#ifdef CONFIG_SCSI_AHCI
+#define CONFIG_LIBATA
+#define CONFIG_SATA_ULI5288
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	4
+#define CONFIG_SYS_SCSI_MAX_LUN	1
+#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
+#define CONFIG_SYS_SCSI_MAXDEVICE	CONFIG_SYS_SCSI_MAX_DEVICE
+#endif /* SCSCI */
+
+#endif	/* CONFIG_PCI */
+
+
+#if defined(CONFIG_TSEC_ENET)
+
+#define CONFIG_MII		1	/* MII PHY management */
+#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define CONFIG_TSEC3	1
+#define CONFIG_TSEC3_NAME	"eTSEC3"
+
+#define CONFIG_PIXIS_SGMII_CMD
+#define CONFIG_FSL_SGMII_RISER	1
+#define SGMII_RISER_PHY_OFFSET	0x1c
+
+#define TSEC1_PHY_ADDR		0
+#define TSEC3_PHY_ADDR		1
+
+#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+
+#define TSEC1_PHYIDX		0
+#define TSEC3_PHYIDX		0
+
+#define CONFIG_ETHPRIME		"eTSEC1"
+
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
+#define CONFIG_ENV_ADDR		0xfff80000
+#else
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x70000)
+#endif
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x10000 /* 64K (one sector) */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
+
+#if defined(CONFIG_PCI)
+    #define CONFIG_CMD_PCI
+    #define CONFIG_CMD_NET
+    #define CONFIG_CMD_SCSI
+    #define CONFIG_CMD_EXT2
+#endif
+
+/*
+ * USB
+ */
+#define CONFIG_USB_EHCI
+
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_USB_EHCI_PCI
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_STORAGE
+#define CONFIG_PCI_EHCI_DEVICE			0
+#endif
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+/* The mac addresses for all ethernet interface */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_ETHADDR	00:E0:0C:02:00:FD
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR	00:E0:0C:02:01:FD
+#endif
+
+#define CONFIG_IPADDR	192.168.1.251
+
+#define CONFIG_HOSTNAME	8544ds_unknown
+#define CONFIG_ROOTPATH	"/nfs/mpc85xx"
+#define CONFIG_BOOTFILE	"8544ds/uImage.uboot"
+#define CONFIG_UBOOTPATH	8544ds/u-boot.bin	/* TFTP server */
+
+#define CONFIG_SERVERIP	192.168.1.1
+#define CONFIG_GATEWAYIP 192.168.1.1
+#define CONFIG_NETMASK	255.255.0.0
+
+#define CONFIG_LOADADDR	1000000	/*default location for tftp and bootm*/
+
+#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
+#undef	CONFIG_BOOTARGS		/* the boot command will set bootargs*/
+
+#define CONFIG_BAUDRATE	115200
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+"netdev=eth0\0"						\
+"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
+"tftpflash=tftpboot $loadaddr $uboot; "			\
+	"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
+		" +$filesize; "	\
+	"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
+		" +$filesize; "	\
+	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
+		" $filesize; "	\
+	"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
+		" +$filesize; "	\
+	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
+		" $filesize\0"	\
+"consoledev=ttyS0\0"				\
+"ramdiskaddr=2000000\0"			\
+"ramdiskfile=8544ds/ramdisk.uboot\0"		\
+"fdtaddr=c00000\0"				\
+"fdtfile=8544ds/mpc8544ds.dtb\0"		\
+"bdev=sda3\0"
+
+#define CONFIG_NFSBOOTCOMMAND		\
+ "setenv bootargs root=/dev/nfs rw "	\
+ "nfsroot=$serverip:$rootpath "		\
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;"	\
+ "tftp $loadaddr $bootfile;"		\
+ "tftp $fdtaddr $fdtfile;"		\
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND		\
+ "setenv bootargs root=/dev/ram rw "	\
+ "console=$consoledev,$baudrate $othbootargs;"	\
+ "tftp $ramdiskaddr $ramdiskfile;"	\
+ "tftp $loadaddr $bootfile;"		\
+ "tftp $fdtaddr $fdtfile;"		\
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		\
+ "setenv bootargs root=/dev/$bdev rw "	\
+ "console=$consoledev,$baudrate $othbootargs;"	\
+ "tftp $loadaddr $bootfile;"		\
+ "tftp $fdtaddr $fdtfile;"		\
+ "bootm $loadaddr - $fdtaddr"
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/MPC8548CDS.h b/qemu/roms/u-boot/include/configs/MPC8548CDS.h
new file mode 100644
index 000000000..190c66830
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/MPC8548CDS.h
@@ -0,0 +1,614 @@
+/*
+ * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * mpc8548cds board configuration file
+ *
+ * Please refer to doc/README.mpc85xxcds for more info.
+ *
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifdef CONFIG_36BIT
+#define CONFIG_PHYS_64BIT
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE		1	/* BOOKE */
+#define CONFIG_E500		1	/* BOOKE e500 family */
+#define CONFIG_MPC8548		1	/* MPC8548 specific */
+#define CONFIG_MPC8548CDS	1	/* MPC8548CDS board specific */
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xfff80000
+#endif
+
+#define CONFIG_SYS_SRIO
+#define CONFIG_SRIO1			/* SRIO port 1 */
+
+#define CONFIG_PCI		/* enable any pci type devices */
+#define CONFIG_PCI1		/* PCI controller 1 */
+#define CONFIG_PCIE1		/* PCIE controler 1 (slot 1) */
+#undef CONFIG_PCI2
+#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
+#define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
+
+#define CONFIG_TSEC_ENET		/* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */
+#define CONFIG_FSL_LAW		1	/* Use common FSL init code */
+
+#define CONFIG_FSL_VIA
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_clock_freq(void);
+#endif
+#define CONFIG_SYS_CLK_FREQ	get_clock_freq() /* sysclk for MPC85xx */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* toggle branch predition */
+
+/*
+ * Only possible on E500 Version 2 or newer cores.
+ */
+#define CONFIG_ENABLE_36BIT_PHYS	1
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
+#endif
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+
+#define CONFIG_SYS_CCSRBAR		0xe0000000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+
+/* DDR Setup */
+#define CONFIG_SYS_FSL_DDR2
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_SPD
+
+#define CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
+
+/* Make sure required options are set */
+#ifndef CONFIG_SPD_EEPROM
+#error ("CONFIG_SPD_EEPROM is required")
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ
+/*
+ * Physical Address Map
+ *
+ * 32bit:
+ * 0x0000_0000	0x7fff_ffff	DDR			2G	cacheable
+ * 0x8000_0000	0x9fff_ffff	PCI1 MEM		512M	cacheable
+ * 0xa000_0000	0xbfff_ffff	PCIe MEM		512M	cacheable
+ * 0xc000_0000	0xdfff_ffff	RapidIO			512M	cacheable
+ * 0xe000_0000	0xe00f_ffff	CCSR			1M	non-cacheable
+ * 0xe200_0000	0xe20f_ffff	PCI1 IO			1M	non-cacheable
+ * 0xe300_0000	0xe30f_ffff	PCIe IO			1M	non-cacheable
+ * 0xf000_0000	0xf3ff_ffff	SDRAM			64M	cacheable
+ * 0xf800_0000	0xf80f_ffff	NVRAM/CADMUS		1M	non-cacheable
+ * 0xff00_0000	0xff7f_ffff	FLASH (2nd bank)	8M	non-cacheable
+ * 0xff80_0000	0xffff_ffff	FLASH (boot bank)	8M	non-cacheable
+ *
+ * 36bit:
+ * 0x00000_0000	0x07fff_ffff	DDR			2G	cacheable
+ * 0xc0000_0000	0xc1fff_ffff	PCI1 MEM		512M	cacheable
+ * 0xc2000_0000	0xc3fff_ffff	PCIe MEM		512M	cacheable
+ * 0xc4000_0000	0xc5fff_ffff	RapidIO			512M	cacheable
+ * 0xfe000_0000	0xfe00f_ffff	CCSR			1M	non-cacheable
+ * 0xfe200_0000	0xfe20f_ffff	PCI1 IO			1M	non-cacheable
+ * 0xfe300_0000	0xfe30f_ffff	PCIe IO			1M	non-cacheable
+ * 0xff000_0000	0xff3ff_ffff	SDRAM			64M	cacheable
+ * 0xff800_0000	0xff80f_ffff	NVRAM/CADMUS		1M	non-cacheable
+ * 0xfff00_0000	0xfff7f_ffff	FLASH (2nd bank)	8M	non-cacheable
+ * 0xfff80_0000	0xfffff_ffff	FLASH (boot bank)	8M	non-cacheable
+ *
+ */
+
+
+/*
+ * Local Bus Definitions
+ */
+
+/*
+ * FLASH on the Local Bus
+ * Two banks, 8M each, using the CFI driver.
+ * Boot from BR0/OR0 bank at 0xff00_0000
+ * Alternate BR1/OR1 bank at 0xff80_0000
+ *
+ * BR0, BR1:
+ *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
+ *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
+ *    Port Size = 16 bits = BRx[19:20] = 10
+ *    Use GPCM = BRx[24:26] = 000
+ *    Valid = BRx[31] = 1
+ *
+ * 0	4    8	  12   16   20	 24   28
+ * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001	 BR0
+ * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001	 BR1
+ *
+ * OR0, OR1:
+ *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
+ *    Reserved ORx[17:18] = 11, confusion here?
+ *    CSNT = ORx[20] = 1
+ *    ACS = half cycle delay = ORx[21:22] = 11
+ *    SCY = 6 = ORx[24:27] = 0110
+ *    TRLX = use relaxed timing = ORx[29] = 1
+ *    EAD = use external address latch delay = OR[31] = 1
+ *
+ * 0	4    8	  12   16   20	 24   28
+ * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65	 ORx
+ */
+
+#define CONFIG_SYS_FLASH_BASE		0xff000000	/* start of FLASH 16M */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_FLASH_BASE_PHYS	0xfff000000ull
+#else
+#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+#endif
+
+#define CONFIG_SYS_BR0_PRELIM \
+	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V)
+#define CONFIG_SYS_BR1_PRELIM \
+	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
+
+#define	CONFIG_SYS_OR0_PRELIM		0xff806e65
+#define	CONFIG_SYS_OR1_PRELIM		0xff806e65
+
+#define CONFIG_SYS_FLASH_BANKS_LIST \
+	{CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS}
+#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	128		/* sectors per device */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+#define CONFIG_HWCONFIG			/* enable hwconfig */
+
+/*
+ * SDRAM on the Local Bus
+ */
+#define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS	0xff0000000ull
+#else
+#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS	CONFIG_SYS_LBC_SDRAM_BASE
+#endif
+#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
+
+/*
+ * Base Register 2 and Option Register 2 configure SDRAM.
+ * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
+ *
+ * For BR2, need:
+ *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
+ *    port-size = 32-bits = BR2[19:20] = 11
+ *    no parity checking = BR2[21:22] = 00
+ *    SDRAM for MSEL = BR2[24:26] = 011
+ *    Valid = BR[31] = 1
+ *
+ * 0	4    8	  12   16   20	 24   28
+ * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
+ *
+ * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
+ * FIXME: the top 17 bits of BR2.
+ */
+
+#define CONFIG_SYS_BR2_PRELIM \
+	(BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \
+	| BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V)
+
+/*
+ * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
+ *
+ * For OR2, need:
+ *    64MB mask for AM, OR2[0:7] = 1111 1100
+ *		   XAM, OR2[17:18] = 11
+ *    9 columns OR2[19-21] = 010
+ *    13 rows	OR2[23-25] = 100
+ *    EAD set for extra time OR[31] = 1
+ *
+ * 0	4    8	  12   16   20	 24   28
+ * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
+ */
+
+#define CONFIG_SYS_OR2_PRELIM		0xfc006901
+
+#define CONFIG_SYS_LBC_LCRR		0x00030004	/* LB clock ratio reg */
+#define CONFIG_SYS_LBC_LBCR		0x00000000	/* LB config reg */
+#define CONFIG_SYS_LBC_LSRT		0x20000000	/* LB sdram refresh timer */
+#define CONFIG_SYS_LBC_MRTPR		0x00000000	/* LB refresh timer prescal*/
+
+/*
+ * Common settings for all Local Bus SDRAM commands.
+ * At run time, either BSMA1516 (for CPU 1.1)
+ *		    or BSMA1617 (for CPU 1.0) (old)
+ * is OR'ed in too.
+ */
+#define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_RFCR16		\
+				| LSDMR_PRETOACT7	\
+				| LSDMR_ACTTORW7	\
+				| LSDMR_BL8		\
+				| LSDMR_WRC4		\
+				| LSDMR_CL3		\
+				| LSDMR_RFEN		\
+				)
+
+/*
+ * The CADMUS registers are connected to CS3 on CDS.
+ * The new memory map places CADMUS at 0xf8000000.
+ *
+ * For BR3, need:
+ *    Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
+ *    port-size = 8-bits  = BR[19:20] = 01
+ *    no parity checking  = BR[21:22] = 00
+ *    GPMC for MSEL	  = BR[24:26] = 000
+ *    Valid		  = BR[31]    = 1
+ *
+ * 0	4    8	  12   16   20	 24   28
+ * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
+ *
+ * For OR3, need:
+ *    1 MB mask for AM,	  OR[0:16]  = 1111 1111 1111 0000 0
+ *    disable buffer ctrl OR[19]    = 0
+ *    CSNT		  OR[20]    = 1
+ *    ACS		  OR[21:22] = 11
+ *    XACS		  OR[23]    = 1
+ *    SCY 15 wait states  OR[24:27] = 1111	max is suboptimal but safe
+ *    SETA		  OR[28]    = 0
+ *    TRLX		  OR[29]    = 1
+ *    EHTR		  OR[30]    = 1
+ *    EAD extra time	  OR[31]    = 1
+ *
+ * 0	4    8	  12   16   20	 24   28
+ * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
+ */
+
+#define CONFIG_FSL_CADMUS
+
+#define CADMUS_BASE_ADDR 0xf8000000
+#ifdef CONFIG_PHYS_64BIT
+#define CADMUS_BASE_ADDR_PHYS	0xff8000000ull
+#else
+#define CADMUS_BASE_ADDR_PHYS	CADMUS_BASE_ADDR
+#endif
+#define CONFIG_SYS_BR3_PRELIM \
+	(BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR3_PRELIM	 0xfff00ff7
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN	(1024 * 1024)	/* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX	2
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT		1
+#define CONFIG_OF_BOARD_SETUP		1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_CCID
+#define CONFIG_SYS_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+#define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCI1_MEM_BUS		0xe0000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	0xc00000000ull
+#else
+#define CONFIG_SYS_PCI1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
+#endif
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCI1_IO_VIRT	0xe2000000
+#define CONFIG_SYS_PCI1_IO_BUS	0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull
+#else
+#define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
+#endif
+#define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */
+
+#ifdef CONFIG_PCIE1
+#define CONFIG_SYS_PCIE1_NAME		"Slot"
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0xa0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc20000000ull
+#else
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xa0000000
+#endif
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xe3000000
+#define CONFIG_SYS_PCIE1_IO_BUS	0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_IO_PHYS        0xfe3000000ull
+#else
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xe3000000
+#endif
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00100000	/*   1M */
+#endif
+
+/*
+ * RapidIO MMU
+ */
+#define CONFIG_SYS_SRIO1_MEM_VIRT	0xc0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_SRIO1_MEM_PHYS	0xc40000000ull
+#else
+#define CONFIG_SYS_SRIO1_MEM_PHYS	0xc0000000
+#endif
+#define CONFIG_SYS_SRIO1_MEM_SIZE	0x20000000	/* 512M */
+
+#ifdef CONFIG_LEGACY
+#define BRIDGE_ID 17
+#define VIA_ID 2
+#else
+#define BRIDGE_ID 28
+#define VIA_ID 4
+#endif
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+#define CONFIG_E1000			/* Define e1000 pci Ethernet card */
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+
+#endif	/* CONFIG_PCI */
+
+
+#if defined(CONFIG_TSEC_ENET)
+
+#define CONFIG_MII		1	/* MII PHY management */
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"eTSEC0"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"eTSEC1"
+#define CONFIG_TSEC3	1
+#define CONFIG_TSEC3_NAME	"eTSEC2"
+#define CONFIG_TSEC4
+#define CONFIG_TSEC4_NAME	"eTSEC3"
+#undef CONFIG_MPC85XX_FEC
+
+#define CONFIG_PHY_MARVELL
+
+#define TSEC1_PHY_ADDR		0
+#define TSEC2_PHY_ADDR		1
+#define TSEC3_PHY_ADDR		2
+#define TSEC4_PHY_ADDR		3
+
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC3_PHYIDX		0
+#define TSEC4_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
+#define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC4_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+
+/* Options are: eTSEC[0-3] */
+#define CONFIG_ETHPRIME		"eTSEC0"
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
+#define CONFIG_ENV_ADDR	0xfff80000
+#else
+#define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#endif
+#define CONFIG_ENV_SECT_SIZE	0x20000	/* 128K for env */
+#define CONFIG_ENV_SIZE		0x2000
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
+
+#if defined(CONFIG_PCI)
+    #define CONFIG_CMD_PCI
+#endif
+
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+/* The mac addresses for all ethernet interface */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_ETHADDR	 00:E0:0C:00:00:FD
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR	 00:E0:0C:00:01:FD
+#define CONFIG_HAS_ETH2
+#define CONFIG_ETH2ADDR	 00:E0:0C:00:02:FD
+#define CONFIG_HAS_ETH3
+#define CONFIG_ETH3ADDR	 00:E0:0C:00:03:FD
+#endif
+
+#define CONFIG_IPADDR	 192.168.1.253
+
+#define CONFIG_HOSTNAME	 unknown
+#define CONFIG_ROOTPATH	 "/nfsroot"
+#define CONFIG_BOOTFILE "8548cds/uImage.uboot"
+#define CONFIG_UBOOTPATH	8548cds/u-boot.bin	/* TFTP server */
+
+#define CONFIG_SERVERIP	 192.168.1.1
+#define CONFIG_GATEWAYIP 192.168.1.1
+#define CONFIG_NETMASK	 255.255.255.0
+
+#define CONFIG_LOADADDR	1000000	/*default location for tftp and bootm*/
+
+#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
+#undef	CONFIG_BOOTARGS		/* the boot command will set bootargs*/
+
+#define CONFIG_BAUDRATE	115200
+
+#define	CONFIG_EXTRA_ENV_SETTINGS		\
+	"hwconfig=fsl_ddr:ecc=off\0"		\
+	"netdev=eth0\0"				\
+	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"	\
+	"tftpflash=tftpboot $loadaddr $uboot; "	\
+		"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
+			" +$filesize; "	\
+		"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
+			" +$filesize; "	\
+		"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
+			" $filesize; "	\
+		"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
+			" +$filesize; "	\
+		"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
+			" $filesize\0"	\
+	"consoledev=ttyS1\0"			\
+	"ramdiskaddr=2000000\0"			\
+	"ramdiskfile=ramdisk.uboot\0"		\
+	"fdtaddr=c00000\0"			\
+	"fdtfile=mpc8548cds.dtb\0"
+
+#define CONFIG_NFSBOOTCOMMAND						\
+   "setenv bootargs root=/dev/nfs rw "					\
+      "nfsroot=$serverip:$rootpath "					\
+      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+      "console=$consoledev,$baudrate $othbootargs;"			\
+   "tftp $loadaddr $bootfile;"						\
+   "tftp $fdtaddr $fdtfile;"						\
+   "bootm $loadaddr - $fdtaddr"
+
+
+#define CONFIG_RAMBOOTCOMMAND \
+   "setenv bootargs root=/dev/ram rw "					\
+      "console=$consoledev,$baudrate $othbootargs;"			\
+   "tftp $ramdiskaddr $ramdiskfile;"					\
+   "tftp $loadaddr $bootfile;"						\
+   "tftp $fdtaddr $fdtfile;"						\
+   "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND	CONFIG_NFSBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/MPC8555CDS.h b/qemu/roms/u-boot/include/configs/MPC8555CDS.h
new file mode 100644
index 000000000..5263ffcc8
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/MPC8555CDS.h
@@ -0,0 +1,469 @@
+/*
+ * Copyright 2004, 2011 Freescale Semiconductor.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * mpc8555cds board configuration file
+ *
+ * Please refer to doc/README.mpc85xxcds for more info.
+ *
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE		1	/* BOOKE */
+#define CONFIG_E500		1	/* BOOKE e500 family */
+#define CONFIG_CPM2		1	/* has CPM2 */
+#define CONFIG_MPC8555		1	/* MPC8555 specific */
+#define CONFIG_MPC8555CDS	1	/* MPC8555CDS board specific */
+
+#define	CONFIG_SYS_TEXT_BASE	0xfff80000
+
+#define CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
+#define CONFIG_TSEC_ENET		/* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_FSL_LAW		1	/* Use common FSL init code */
+
+#define CONFIG_FSL_VIA
+
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_clock_freq(void);
+#endif
+#define CONFIG_SYS_CLK_FREQ	get_clock_freq() /* sysclk for MPC85xx */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			    /* toggle L2 cache	*/
+#define CONFIG_BTB			    /* toggle branch predition */
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+
+#define CONFIG_SYS_CCSRBAR		0xe0000000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+
+/* DDR Setup */
+#define CONFIG_SYS_FSL_DDR1
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_SPD
+#undef CONFIG_FSL_DDR_INTERACTIVE
+
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
+
+/* Make sure required options are set */
+#ifndef CONFIG_SPD_EEPROM
+#error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+/*
+ * Local Bus Definitions
+ */
+
+/*
+ * FLASH on the Local Bus
+ * Two banks, 8M each, using the CFI driver.
+ * Boot from BR0/OR0 bank at 0xff00_0000
+ * Alternate BR1/OR1 bank at 0xff80_0000
+ *
+ * BR0, BR1:
+ *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
+ *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
+ *    Port Size = 16 bits = BRx[19:20] = 10
+ *    Use GPCM = BRx[24:26] = 000
+ *    Valid = BRx[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001    BR0
+ * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001    BR1
+ *
+ * OR0, OR1:
+ *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
+ *    Reserved ORx[17:18] = 11, confusion here?
+ *    CSNT = ORx[20] = 1
+ *    ACS = half cycle delay = ORx[21:22] = 11
+ *    SCY = 6 = ORx[24:27] = 0110
+ *    TRLX = use relaxed timing = ORx[29] = 1
+ *    EAD = use external address latch delay = OR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    ORx
+ */
+
+#define CONFIG_SYS_FLASH_BASE		0xff000000	/* start of FLASH 8M */
+
+#define CONFIG_SYS_BR0_PRELIM		0xff801001
+#define CONFIG_SYS_BR1_PRELIM		0xff001001
+
+#define	CONFIG_SYS_OR0_PRELIM		0xff806e65
+#define	CONFIG_SYS_OR1_PRELIM		0xff806e65
+
+#define CONFIG_SYS_FLASH_BANKS_LIST	{0xff800000, CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	128		/* sectors per device */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+
+/*
+ * SDRAM on the Local Bus
+ */
+#define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
+#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
+
+/*
+ * Base Register 2 and Option Register 2 configure SDRAM.
+ * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
+ *
+ * For BR2, need:
+ *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
+ *    port-size = 32-bits = BR2[19:20] = 11
+ *    no parity checking = BR2[21:22] = 00
+ *    SDRAM for MSEL = BR2[24:26] = 011
+ *    Valid = BR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
+ *
+ * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
+ * FIXME: the top 17 bits of BR2.
+ */
+
+#define CONFIG_SYS_BR2_PRELIM          0xf0001861
+
+/*
+ * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
+ *
+ * For OR2, need:
+ *    64MB mask for AM, OR2[0:7] = 1111 1100
+ *		   XAM, OR2[17:18] = 11
+ *    9 columns OR2[19-21] = 010
+ *    13 rows   OR2[23-25] = 100
+ *    EAD set for extra time OR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
+ */
+
+#define CONFIG_SYS_OR2_PRELIM		0xfc006901
+
+#define CONFIG_SYS_LBC_LCRR		0x00030004    /* LB clock ratio reg */
+#define CONFIG_SYS_LBC_LBCR		0x00000000    /* LB config reg */
+#define CONFIG_SYS_LBC_LSRT		0x20000000  /* LB sdram refresh timer */
+#define CONFIG_SYS_LBC_MRTPR		0x00000000  /* LB refresh timer prescal*/
+
+/*
+ * Common settings for all Local Bus SDRAM commands.
+ * At run time, either BSMA1516 (for CPU 1.1)
+ *                  or BSMA1617 (for CPU 1.0) (old)
+ * is OR'ed in too.
+ */
+#define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_RFCR16		\
+				| LSDMR_PRETOACT7	\
+				| LSDMR_ACTTORW7	\
+				| LSDMR_BL8		\
+				| LSDMR_WRC4		\
+				| LSDMR_CL3		\
+				| LSDMR_RFEN		\
+				)
+
+/*
+ * The CADMUS registers are connected to CS3 on CDS.
+ * The new memory map places CADMUS at 0xf8000000.
+ *
+ * For BR3, need:
+ *    Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
+ *    port-size = 8-bits  = BR[19:20] = 01
+ *    no parity checking  = BR[21:22] = 00
+ *    GPMC for MSEL       = BR[24:26] = 000
+ *    Valid               = BR[31]    = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
+ *
+ * For OR3, need:
+ *    1 MB mask for AM,   OR[0:16]  = 1111 1111 1111 0000 0
+ *    disable buffer ctrl OR[19]    = 0
+ *    CSNT                OR[20]    = 1
+ *    ACS                 OR[21:22] = 11
+ *    XACS                OR[23]    = 1
+ *    SCY 15 wait states  OR[24:27] = 1111	max is suboptimal but safe
+ *    SETA                OR[28]    = 0
+ *    TRLX                OR[29]    = 1
+ *    EHTR                OR[30]    = 1
+ *    EAD extra time      OR[31]    = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
+ */
+
+#define CONFIG_FSL_CADMUS
+
+#define CADMUS_BASE_ADDR 0xf8000000
+#define CONFIG_SYS_BR3_PRELIM   0xf8000801
+#define CONFIG_SYS_OR3_PRELIM   0xfff00ff7
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000	    /* Size of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX     2
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE    1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef  CONFIG_SYS_HUSH_PARSER
+#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT		1
+#define CONFIG_OF_BOARD_SETUP		1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_CCID
+#define CONFIG_SYS_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCI1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCI1_IO_VIRT	0xe2000000
+#define CONFIG_SYS_PCI1_IO_BUS	0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
+#define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */
+
+#define CONFIG_SYS_PCI2_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCI2_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCI2_MEM_PHYS	0xa0000000
+#define CONFIG_SYS_PCI2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCI2_IO_VIRT	0xe2100000
+#define CONFIG_SYS_PCI2_IO_BUS	0x00000000
+#define CONFIG_SYS_PCI2_IO_PHYS	0xe2100000
+#define CONFIG_SYS_PCI2_IO_SIZE	0x00100000	/* 1M */
+
+#ifdef CONFIG_LEGACY
+#define BRIDGE_ID 17
+#define VIA_ID 2
+#else
+#define BRIDGE_ID 28
+#define VIA_ID 4
+#endif
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+#define CONFIG_MPC85XX_PCI2
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
+
+#endif	/* CONFIG_PCI */
+
+
+#if defined(CONFIG_TSEC_ENET)
+
+#define CONFIG_MII		1	/* MII PHY management */
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"TSEC1"
+#define TSEC1_PHY_ADDR		0
+#define TSEC2_PHY_ADDR		1
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME		"TSEC0"
+
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
+#define CONFIG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
+#define CONFIG_ENV_SIZE		0x2000
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
+
+#if defined(CONFIG_PCI)
+    #define CONFIG_CMD_PCI
+#endif
+
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+/* The mac addresses for all ethernet interface */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_ETHADDR   00:E0:0C:00:00:FD
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
+#define CONFIG_HAS_ETH2
+#define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
+#endif
+
+#define CONFIG_IPADDR    192.168.1.253
+
+#define CONFIG_HOSTNAME  unknown
+#define CONFIG_ROOTPATH  "/nfsroot"
+#define CONFIG_BOOTFILE  "your.uImage"
+
+#define CONFIG_SERVERIP  192.168.1.1
+#define CONFIG_GATEWAYIP 192.168.1.1
+#define CONFIG_NETMASK   255.255.255.0
+
+#define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
+
+#define CONFIG_BOOTDELAY 10       /* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS           /* the boot command will set bootargs*/
+
+#define CONFIG_BAUDRATE	115200
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				        \
+   "netdev=eth0\0"                                                      \
+   "consoledev=ttyS1\0"                                                 \
+   "ramdiskaddr=600000\0"                                               \
+   "ramdiskfile=your.ramdisk.u-boot\0"					\
+   "fdtaddr=400000\0"							\
+   "fdtfile=your.fdt.dtb\0"
+
+#define CONFIG_NFSBOOTCOMMAND	                                        \
+   "setenv bootargs root=/dev/nfs rw "                                  \
+      "nfsroot=$serverip:$rootpath "                                    \
+      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+      "console=$consoledev,$baudrate $othbootargs;"                     \
+   "tftp $loadaddr $bootfile;"                                          \
+   "tftp $fdtaddr $fdtfile;"						\
+   "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+   "setenv bootargs root=/dev/ram rw "                                  \
+      "console=$consoledev,$baudrate $othbootargs;"                     \
+   "tftp $ramdiskaddr $ramdiskfile;"                                    \
+   "tftp $loadaddr $bootfile;"                                          \
+   "bootm $loadaddr $ramdiskaddr"
+
+#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/MPC8560ADS.h b/qemu/roms/u-boot/include/configs/MPC8560ADS.h
new file mode 100644
index 000000000..ac78d481d
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/MPC8560ADS.h
@@ -0,0 +1,503 @@
+/*
+ * Copyright 2004, 2011 Freescale Semiconductor.
+ * (C) Copyright 2002,2003 Motorola,Inc.
+ * Xianghua Xiao <X.Xiao@motorola.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * mpc8560ads board configuration file
+ *
+ * Please refer to doc/README.mpc85xx for more info.
+ *
+ * Make sure you change the MAC address and other network params first,
+ * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE		1	/* BOOKE */
+#define CONFIG_E500		1	/* BOOKE e500 family */
+#define CONFIG_CPM2		1	/* has CPM2 */
+#define CONFIG_MPC8560ADS	1	/* MPC8560ADS board specific */
+#define CONFIG_MPC8560		1
+
+/*
+ * default CCARBAR is at 0xff700000
+ * assume U-Boot is less than 0.5MB
+ */
+#define	CONFIG_SYS_TEXT_BASE	0xfff80000
+
+#define CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
+#define CONFIG_TSEC_ENET		/* tsec ethernet support */
+#undef CONFIG_ETHER_ON_FCC             /* cpm FCC ethernet support */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_FSL_LAW		1	/* Use common FSL init code */
+#define CONFIG_RESET_PHY_R	1	/* Call reset_phy() */
+
+/*
+ * sysclk for MPC85xx
+ *
+ * Two valid values are:
+ *    33000000
+ *    66000000
+ *
+ * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
+ * is likely the desired value here, so that is now the default.
+ * The board, however, can run at 66MHz.  In any event, this value
+ * must match the settings of some switches.  Details can be found
+ * in the README.mpc85xxads.
+ */
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_CLK_FREQ	33000000
+#endif
+
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* toggle branch predition */
+
+#define CONFIG_SYS_INIT_DBCR DBCR_IDM		/* Enable Debug Exceptions */
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+
+#define CONFIG_SYS_CCSRBAR		0xe0000000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+
+/* DDR Setup */
+#define CONFIG_SYS_FSL_DDR1
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_SPD
+#undef CONFIG_FSL_DDR_INTERACTIVE
+
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
+
+/* These are used when DDR doesn't use SPD.  */
+#define CONFIG_SYS_SDRAM_SIZE	128		/* DDR is 128MB */
+#define CONFIG_SYS_DDR_CS0_BNDS	0x00000007	/* 0-128MB */
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80000002
+#define CONFIG_SYS_DDR_TIMING_1	0x37344321
+#define CONFIG_SYS_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
+#define CONFIG_SYS_DDR_CONTROL		0xc2000000	/* unbuffered,no DYN_PWR */
+#define CONFIG_SYS_DDR_MODE		0x00000062	/* DLL,normal,seq,4/2.5 */
+#define CONFIG_SYS_DDR_INTERVAL	0x05200100	/* autocharge,no open page */
+
+/*
+ * SDRAM on the Local Bus
+ */
+#define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
+#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
+
+#define CONFIG_SYS_FLASH_BASE		0xff000000	/* start of FLASH 16M */
+#define CONFIG_SYS_BR0_PRELIM		0xff001801	/* port size 32bit */
+
+#define CONFIG_SYS_OR0_PRELIM		0xff006ff7	/* 16MB Flash */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	64		/* sectors per device */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef  CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+
+/*
+ * Local Bus Definitions
+ */
+
+/*
+ * Base Register 2 and Option Register 2 configure SDRAM.
+ * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
+ *
+ * For BR2, need:
+ *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
+ *    port-size = 32-bits = BR2[19:20] = 11
+ *    no parity checking = BR2[21:22] = 00
+ *    SDRAM for MSEL = BR2[24:26] = 011
+ *    Valid = BR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
+ *
+ * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
+ * FIXME: the top 17 bits of BR2.
+ */
+
+#define CONFIG_SYS_BR2_PRELIM		0xf0001861
+
+/*
+ * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
+ *
+ * For OR2, need:
+ *    64MB mask for AM, OR2[0:7] = 1111 1100
+ *		   XAM, OR2[17:18] = 11
+ *    9 columns OR2[19-21] = 010
+ *    13 rows   OR2[23-25] = 100
+ *    EAD set for extra time OR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
+ */
+
+#define CONFIG_SYS_OR2_PRELIM		0xfc006901
+
+#define CONFIG_SYS_LBC_LCRR		0x00030004    /* LB clock ratio reg */
+#define CONFIG_SYS_LBC_LBCR		0x00000000    /* LB config reg */
+#define CONFIG_SYS_LBC_LSRT		0x20000000    /* LB sdram refresh timer */
+#define CONFIG_SYS_LBC_MRTPR		0x20000000    /* LB refresh timer prescal*/
+
+#define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_BSMA1516	\
+				| LSDMR_RFCR5		\
+				| LSDMR_PRETOACT3	\
+				| LSDMR_ACTTORW3	\
+				| LSDMR_BL8		\
+				| LSDMR_WRC2		\
+				| LSDMR_CL3		\
+				| LSDMR_RFEN		\
+				)
+
+/*
+ * SDRAM Controller configuration sequence.
+ */
+#define CONFIG_SYS_LBC_LSDMR_1	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
+#define CONFIG_SYS_LBC_LSDMR_2	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_3	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_4	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
+#define CONFIG_SYS_LBC_LSDMR_5	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
+
+
+/*
+ * 32KB, 8-bit wide for ADS config reg
+ */
+#define CONFIG_SYS_BR4_PRELIM          0xf8000801
+#define CONFIG_SYS_OR4_PRELIM		0xffffe1f1
+#define CONFIG_SYS_BCSR		(CONFIG_SYS_BR4_PRELIM & 0xffff8000)
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)    /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)    /* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_ON_SCC	/* define if console on SCC */
+#undef  CONFIG_CONS_NONE	/* define if console on something else */
+#define CONFIG_CONS_INDEX       1  /* which serial channel for console */
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef  CONFIG_SYS_HUSH_PARSER
+#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT		1
+#define CONFIG_OF_BOARD_SETUP		1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
+
+/* RapidIO MMU */
+#define CONFIG_SYS_RIO_MEM_VIRT	0xc0000000	/* base address */
+#define CONFIG_SYS_RIO_MEM_BUS	0xc0000000	/* base address */
+#define CONFIG_SYS_RIO_MEM_PHYS	0xc0000000
+#define CONFIG_SYS_RIO_MEM_SIZE	0x20000000	/* 128M */
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+#define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCI1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCI1_IO_VIRT	0xe2000000
+#define CONFIG_SYS_PCI1_IO_BUS	0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
+#define CONFIG_SYS_PCI1_IO_SIZE	0x100000	/* 1M */
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+    #define PCI_ENET0_IOADDR	0xe0000000
+    #define PCI_ENET0_MEMADDR	0xe0000000
+    #define PCI_IDSEL_NUMBER	0x0c	/* slot0->3(IDSEL)=12->15 */
+#endif
+
+#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
+
+#endif	/* CONFIG_PCI */
+
+
+#ifdef CONFIG_TSEC_ENET
+
+#ifndef CONFIG_MII
+#define CONFIG_MII		1	/* MII PHY management */
+#endif
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"TSEC1"
+#define TSEC1_PHY_ADDR		0
+#define TSEC2_PHY_ADDR		1
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME		"TSEC0"
+
+#endif /* CONFIG_TSEC_ENET */
+
+#ifdef CONFIG_ETHER_ON_FCC		/* CPM FCC Ethernet */
+
+#undef  CONFIG_ETHER_NONE		/* define if ether on something else */
+#define CONFIG_ETHER_INDEX      2       /* which channel for ether */
+
+#if (CONFIG_ETHER_INDEX == 2)
+  /*
+   * - Rx-CLK is CLK13
+   * - Tx-CLK is CLK14
+   * - Select bus for bd/buffers
+   * - Full duplex
+   */
+  #define CONFIG_SYS_CMXFCR_MASK2      (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+  #define CONFIG_SYS_CMXFCR_VALUE2     (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
+  #define CONFIG_SYS_CPMFCR_RAMTYPE    0
+  #define CONFIG_SYS_FCC_PSMR          (FCC_PSMR_FDE)
+  #define FETH2_RST		0x01
+#elif (CONFIG_ETHER_INDEX == 3)
+  /* need more definitions here for FE3 */
+  #define FETH3_RST		0x80
+#endif					/* CONFIG_ETHER_INDEX */
+
+#ifndef CONFIG_MII
+#define CONFIG_MII		1	/* MII PHY management */
+#endif
+
+#define CONFIG_BITBANGMII		/* bit-bang MII PHY management */
+
+/*
+ * GPIO pins used for bit-banged MII communications
+ */
+#define MDIO_PORT	2		/* Port C */
+#define MDIO_DECLARE	volatile ioport_t *iop = ioport_addr ( \
+				(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
+#define MDC_DECLARE	MDIO_DECLARE
+
+#define MDIO_ACTIVE	(iop->pdir |=  0x00400000)
+#define MDIO_TRISTATE	(iop->pdir &= ~0x00400000)
+#define MDIO_READ	((iop->pdat &  0x00400000) != 0)
+
+#define MDIO(bit)	if(bit) iop->pdat |=  0x00400000; \
+			else	iop->pdat &= ~0x00400000
+
+#define MDC(bit)	if(bit) iop->pdat |=  0x00200000; \
+			else	iop->pdat &= ~0x00200000
+
+#define MIIDELAY	udelay(1)
+
+#endif
+
+
+/*
+ * Environment
+ */
+#ifndef CONFIG_SYS_RAMBOOT
+  #define CONFIG_ENV_IS_IN_FLASH	1
+  #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
+  #define CONFIG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
+  #define CONFIG_ENV_SIZE		0x2000
+#else
+  #define CONFIG_SYS_NO_FLASH		1	/* Flash is not usable now */
+  #define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
+  #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
+  #define CONFIG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
+
+#if defined(CONFIG_PCI)
+    #define CONFIG_CMD_PCI
+#endif
+
+#if defined(CONFIG_ETHER_ON_FCC)
+    #define CONFIG_CMD_MII
+#endif
+
+#if defined(CONFIG_SYS_RAMBOOT)
+    #undef CONFIG_CMD_SAVEENV
+    #undef CONFIG_CMD_LOADS
+#endif
+
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR	0x1000000	/* default load address */
+
+#if defined(CONFIG_CMD_KGDB)
+    #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+    #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+
+/*
+ * Environment Configuration
+ */
+
+/* The mac addresses for all ethernet interface */
+#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
+#define CONFIG_HAS_ETH0
+#define CONFIG_ETHADDR   00:E0:0C:00:00:FD
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
+#define CONFIG_HAS_ETH2
+#define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
+#define CONFIG_HAS_ETH3
+#define CONFIG_ETH3ADDR  00:E0:0C:00:03:FD
+#endif
+
+#define CONFIG_IPADDR    192.168.1.253
+
+#define CONFIG_HOSTNAME		unknown
+#define CONFIG_ROOTPATH		"/nfsroot"
+#define CONFIG_BOOTFILE		"your.uImage"
+
+#define CONFIG_SERVERIP  192.168.1.1
+#define CONFIG_GATEWAYIP 192.168.1.1
+#define CONFIG_NETMASK   255.255.255.0
+
+#define CONFIG_LOADADDR  200000	/* default location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE	115200
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				        \
+	"netdev=eth0\0"							\
+	"consoledev=ttyCPM\0"						\
+	"ramdiskaddr=1000000\0"						\
+	"ramdiskfile=your.ramdisk.u-boot\0"				\
+	"fdtaddr=400000\0"						\
+	"fdtfile=mpc8560ads.dtb\0"
+
+#define CONFIG_NFSBOOTCOMMAND	                                        \
+	"setenv bootargs root=/dev/nfs rw "				\
+		"nfsroot=$serverip:$rootpath "				\
+		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+		"console=$consoledev,$baudrate $othbootargs;"		\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+	"setenv bootargs root=/dev/ram rw "				\
+		"console=$consoledev,$baudrate $othbootargs;"		\
+	"tftp $ramdiskaddr $ramdiskfile;"				\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/MPC8568MDS.h b/qemu/roms/u-boot/include/configs/MPC8568MDS.h
new file mode 100644
index 000000000..02a5acf38
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/MPC8568MDS.h
@@ -0,0 +1,497 @@
+/*
+ * Copyright 2004-2007, 2010-2011 Freescale Semiconductor.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * mpc8568mds board configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE		1	/* BOOKE */
+#define CONFIG_E500		1	/* BOOKE e500 family */
+#define CONFIG_MPC8568		1	/* MPC8568 specific */
+#define CONFIG_MPC8568MDS	1	/* MPC8568MDS board specific */
+
+#define	CONFIG_SYS_TEXT_BASE	0xfff80000
+
+#define CONFIG_SYS_SRIO
+#define CONFIG_SRIO1			/* SRIO port 1 */
+
+#define CONFIG_PCI		1	/* Enable PCI/PCIE */
+#define CONFIG_PCI1		1	/* PCI controller */
+#define CONFIG_PCIE1		1	/* PCIE controller */
+#define CONFIG_FSL_PCI_INIT	1	/* use common fsl pci init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
+#define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
+#define CONFIG_TSEC_ENET		/* tsec ethernet support */
+#define CONFIG_QE			/* Enable QE */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_FSL_LAW		1	/* Use common FSL init code */
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_clock_freq(void);
+#endif						  /*Replace a call to get_clock_freq (after it is implemented)*/
+#define CONFIG_SYS_CLK_FREQ	66000000 /*TODO: restore if wanting to read from BCSR: get_clock_freq()*/ /* sysclk for MPC85xx */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE				/* toggle L2 cache	*/
+#define CONFIG_BTB				/* toggle branch predition */
+
+/*
+ * Only possible on E500 Version 2 or newer cores.
+ */
+#define CONFIG_ENABLE_36BIT_PHYS	1
+
+
+#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+
+#define CONFIG_SYS_CCSRBAR		0xe0000000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+
+/* DDR Setup */
+#define CONFIG_SYS_FSL_DDR2
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_SPD
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
+
+/* Make sure required options are set */
+#ifndef CONFIG_SPD_EEPROM
+#error ("CONFIG_SPD_EEPROM is required")
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+/*
+ * Local Bus Definitions
+ */
+
+/*
+ * FLASH on the Local Bus
+ * Two banks, 8M each, using the CFI driver.
+ * Boot from BR0/OR0 bank at 0xff00_0000
+ * Alternate BR1/OR1 bank at 0xff80_0000
+ *
+ * BR0, BR1:
+ *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
+ *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
+ *    Port Size = 16 bits = BRx[19:20] = 10
+ *    Use GPCM = BRx[24:26] = 000
+ *    Valid = BRx[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001    BR0
+ * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001    BR1
+ *
+ * OR0, OR1:
+ *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
+ *    Reserved ORx[17:18] = 11, confusion here?
+ *    CSNT = ORx[20] = 1
+ *    ACS = half cycle delay = ORx[21:22] = 11
+ *    SCY = 6 = ORx[24:27] = 0110
+ *    TRLX = use relaxed timing = ORx[29] = 1
+ *    EAD = use external address latch delay = OR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    ORx
+ */
+#define CONFIG_SYS_BCSR_BASE		0xf8000000
+
+#define CONFIG_SYS_FLASH_BASE		0xfe000000	/* start of FLASH 32M */
+
+/*Chip select 0 - Flash*/
+#define CONFIG_SYS_BR0_PRELIM		0xfe001001
+#define	CONFIG_SYS_OR0_PRELIM		0xfe006ff7
+
+/*Chip slelect 1 - BCSR*/
+#define CONFIG_SYS_BR1_PRELIM		0xf8000801
+#define	CONFIG_SYS_OR1_PRELIM		0xffffe9f7
+
+/*#define CONFIG_SYS_FLASH_BANKS_LIST	{0xff800000, CONFIG_SYS_FLASH_BASE} */
+#define CONFIG_SYS_MAX_FLASH_BANKS		1		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT		512		/* sectors per device */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+
+/*
+ * SDRAM on the LocalBus
+ */
+#define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM	 */
+#define CONFIG_SYS_LBC_SDRAM_SIZE	64			/* LBC SDRAM is 64MB */
+
+
+/*Chip select 2 - SDRAM*/
+#define CONFIG_SYS_BR2_PRELIM      0xf0001861
+#define CONFIG_SYS_OR2_PRELIM		0xfc006901
+
+#define CONFIG_SYS_LBC_LCRR		0x00030004	/* LB clock ratio reg */
+#define CONFIG_SYS_LBC_LBCR		0x00000000	/* LB config reg */
+#define CONFIG_SYS_LBC_LSRT		0x20000000	/* LB sdram refresh timer */
+#define CONFIG_SYS_LBC_MRTPR		0x00000000	/* LB refresh timer prescal*/
+
+/*
+ * Common settings for all Local Bus SDRAM commands.
+ * At run time, either BSMA1516 (for CPU 1.1)
+ *                  or BSMA1617 (for CPU 1.0) (old)
+ * is OR'ed in too.
+ */
+#define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_RFCR16		\
+				| LSDMR_PRETOACT7	\
+				| LSDMR_ACTTORW7	\
+				| LSDMR_BL8		\
+				| LSDMR_WRC4		\
+				| LSDMR_CL3		\
+				| LSDMR_RFEN		\
+				)
+
+/*
+ * The bcsr registers are connected to CS3 on MDS.
+ * The new memory map places bcsr at 0xf8000000.
+ *
+ * For BR3, need:
+ *    Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
+ *    port-size = 8-bits  = BR[19:20] = 01
+ *    no parity checking  = BR[21:22] = 00
+ *    GPMC for MSEL       = BR[24:26] = 000
+ *    Valid               = BR[31]    = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
+ *
+ * For OR3, need:
+ *    1 MB mask for AM,   OR[0:16]  = 1111 1111 1111 0000 0
+ *    disable buffer ctrl OR[19]    = 0
+ *    CSNT                OR[20]    = 1
+ *    ACS                 OR[21:22] = 11
+ *    XACS                OR[23]    = 1
+ *    SCY 15 wait states  OR[24:27] = 1111	max is suboptimal but safe
+ *    SETA                OR[28]    = 0
+ *    TRLX                OR[29]    = 1
+ *    EHTR                OR[30]    = 1
+ *    EAD extra time      OR[31]    = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
+ */
+#define CONFIG_SYS_BCSR (0xf8000000)
+
+/*Chip slelect 4 - PIB*/
+#define CONFIG_SYS_BR4_PRELIM   0xf8008801
+#define CONFIG_SYS_OR4_PRELIM   0xffffe9f7
+
+/*Chip select 5 - PIB*/
+#define CONFIG_SYS_BR5_PRELIM	 0xf8010801
+#define CONFIG_SYS_OR5_PRELIM	 0xffff69f7
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000	    /* Size of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE    1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
+
+/* Use the HUSH parser*/
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef  CONFIG_SYS_HUSH_PARSER
+#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT		1
+#define CONFIG_OF_BOARD_SETUP		1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x52
+
+/*
+ * General PCI
+ * Memory Addresses are mapped 1-1. I/O is mapped from 0
+ */
+#define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCI1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCI1_IO_VIRT	0xe2000000
+#define CONFIG_SYS_PCI1_IO_BUS	0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
+#define CONFIG_SYS_PCI1_IO_SIZE	0x00800000	/* 8M */
+
+#define CONFIG_SYS_PCIE1_NAME		"Slot"
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xe2800000
+#define CONFIG_SYS_PCIE1_IO_BUS	0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xe2800000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000	/* 8M */
+
+#define CONFIG_SYS_SRIO1_MEM_VIRT	0xC0000000
+#define CONFIG_SYS_SRIO1_MEM_BUS	0xC0000000
+#define CONFIG_SYS_SRIO1_MEM_PHYS	CONFIG_SYS_SRIO1_MEM_BUS
+#define CONFIG_SYS_SRIO1_MEM_SIZE	0x20000000	/* 512M */
+
+#ifdef CONFIG_QE
+/*
+ * QE UEC ethernet configuration
+ */
+#define CONFIG_UEC_ETH
+#ifndef CONFIG_TSEC_ENET
+#define CONFIG_ETHPRIME         "UEC0"
+#endif
+#define CONFIG_PHY_MODE_NEED_CHANGE
+#define CONFIG_eTSEC_MDIO_BUS
+
+#ifdef CONFIG_eTSEC_MDIO_BUS
+#define CONFIG_MIIM_ADDRESS	0xE0024520
+#endif
+
+#define CONFIG_UEC_ETH1         /* GETH1 */
+
+#ifdef CONFIG_UEC_ETH1
+#define CONFIG_SYS_UEC1_UCC_NUM        0       /* UCC1 */
+#define CONFIG_SYS_UEC1_RX_CLK         QE_CLK_NONE
+#define CONFIG_SYS_UEC1_TX_CLK         QE_CLK16
+#define CONFIG_SYS_UEC1_ETH_TYPE       GIGA_ETH
+#define CONFIG_SYS_UEC1_PHY_ADDR       7
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
+#endif
+
+#define CONFIG_UEC_ETH2         /* GETH2 */
+
+#ifdef CONFIG_UEC_ETH2
+#define CONFIG_SYS_UEC2_UCC_NUM        1       /* UCC2 */
+#define CONFIG_SYS_UEC2_RX_CLK         QE_CLK_NONE
+#define CONFIG_SYS_UEC2_TX_CLK         QE_CLK16
+#define CONFIG_SYS_UEC2_ETH_TYPE       GIGA_ETH
+#define CONFIG_SYS_UEC2_PHY_ADDR       1
+#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
+#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
+#endif
+#endif /* CONFIG_QE */
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
+
+#endif	/* CONFIG_PCI */
+
+#if defined(CONFIG_TSEC_ENET)
+
+#define CONFIG_MII		1	/* MII PHY management */
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"eTSEC0"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"eTSEC1"
+
+#define TSEC1_PHY_ADDR		2
+#define TSEC2_PHY_ADDR		3
+
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
+
+/* Options are: eTSEC[0-1] */
+#define CONFIG_ETHPRIME		"eTSEC0"
+
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
+#define CONFIG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
+#define CONFIG_ENV_SIZE		0x2000
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
+
+#if defined(CONFIG_PCI)
+    #define CONFIG_CMD_PCI
+#endif
+
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	256			/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+/* The mac addresses for all ethernet interface */
+#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH)
+#define CONFIG_HAS_ETH0
+#define CONFIG_ETHADDR   00:E0:0C:00:00:FD
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
+#define CONFIG_HAS_ETH2
+#define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
+#define CONFIG_HAS_ETH3
+#define CONFIG_ETH3ADDR  00:E0:0C:00:03:FD
+#endif
+
+#define CONFIG_IPADDR    192.168.1.253
+
+#define CONFIG_HOSTNAME  unknown
+#define CONFIG_ROOTPATH  "/nfsroot"
+#define CONFIG_BOOTFILE  "your.uImage"
+
+#define CONFIG_SERVERIP  192.168.1.1
+#define CONFIG_GATEWAYIP 192.168.1.1
+#define CONFIG_NETMASK   255.255.255.0
+
+#define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
+
+#define CONFIG_BOOTDELAY 10       /* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS           /* the boot command will set bootargs*/
+
+#define CONFIG_BAUDRATE	115200
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				        \
+   "netdev=eth0\0"                                                      \
+   "consoledev=ttyS0\0"                                                 \
+   "ramdiskaddr=600000\0"                                               \
+   "ramdiskfile=your.ramdisk.u-boot\0"					\
+   "fdtaddr=400000\0"							\
+   "fdtfile=your.fdt.dtb\0"						\
+   "nfsargs=setenv bootargs root=/dev/nfs rw "				\
+      "nfsroot=$serverip:$rootpath "					\
+      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+      "console=$consoledev,$baudrate $othbootargs\0"			\
+   "ramargs=setenv bootargs root=/dev/ram rw "				\
+      "console=$consoledev,$baudrate $othbootargs\0"			\
+
+
+#define CONFIG_NFSBOOTCOMMAND	                                        \
+   "run nfsargs;"							\
+   "tftp $loadaddr $bootfile;"                                          \
+   "tftp $fdtaddr $fdtfile;"						\
+   "bootm $loadaddr - $fdtaddr"
+
+
+#define CONFIG_RAMBOOTCOMMAND \
+   "run ramargs;"							\
+   "tftp $ramdiskaddr $ramdiskfile;"                                    \
+   "tftp $loadaddr $bootfile;"                                          \
+   "bootm $loadaddr $ramdiskaddr"
+
+#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/MPC8569MDS.h b/qemu/roms/u-boot/include/configs/MPC8569MDS.h
new file mode 100644
index 000000000..5165a456a
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/MPC8569MDS.h
@@ -0,0 +1,616 @@
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * mpc8569mds board configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE		1	/* BOOKE */
+#define CONFIG_E500		1	/* BOOKE e500 family */
+#define CONFIG_MPC8569		1	/* MPC8569 specific */
+#define CONFIG_MPC8569MDS	1	/* MPC8569MDS board specific */
+
+#define CONFIG_FSL_ELBC		1	/* Has Enhance localbus controller */
+
+#define CONFIG_SYS_SRIO
+#define CONFIG_SRIO1			/* SRIO port 1 */
+
+#define CONFIG_PCI		1	/* Disable PCI/PCIE */
+#define CONFIG_PCIE1		1	/* PCIE controller */
+#define CONFIG_FSL_PCI_INIT	1	/* use common fsl pci init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
+#define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
+#define CONFIG_QE			/* Enable QE */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_FSL_LAW		1	/* Use common FSL init code */
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_clock_freq(void);
+#endif
+/* Replace a call to get_clock_freq (after it is implemented)*/
+#define CONFIG_SYS_CLK_FREQ	66666666
+#define CONFIG_DDR_CLK_FREQ	CONFIG_SYS_CLK_FREQ
+
+#ifdef CONFIG_ATM
+#define CONFIG_PQ_MDS_PIB
+#define CONFIG_PQ_MDS_PIB_ATM
+#endif
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE				/* toggle L2 cache	*/
+#define CONFIG_BTB				/* toggle branch predition */
+
+#ifdef CONFIG_NAND
+#define CONFIG_NAND_U_BOOT		1
+#define CONFIG_RAMBOOT_NAND		1
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
+#else
+#define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds
+#define CONFIG_SYS_TEXT_BASE	0xf8f82000
+#endif
+#endif
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xfff80000
+#endif
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+
+/*
+ * Only possible on E500 Version 2 or newer cores.
+ */
+#define CONFIG_ENABLE_36BIT_PHYS	1
+
+#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
+#define CONFIG_BOARD_EARLY_INIT_R	1
+#define CONFIG_HWCONFIG
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+
+/*
+ * Config the L2 Cache as L2 SRAM
+ */
+#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE		(512 << 10)
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+
+#define CONFIG_SYS_CCSRBAR		0xe0000000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+
+#if defined(CONFIG_NAND_SPL)
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#endif
+
+/* DDR Setup */
+#define CONFIG_SYS_FSL_DDR3
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_SPD
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+					/* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS    0x51    /* CTLR 0 DIMM 0 */
+
+/* These are used when DDR doesn't use SPD.  */
+#define CONFIG_SYS_SDRAM_SIZE           1024		/* DDR is 1024MB */
+#define CONFIG_SYS_DDR_CS0_BNDS         0x0000003F
+#define CONFIG_SYS_DDR_CS0_CONFIG       0x80014202
+#define CONFIG_SYS_DDR_TIMING_3         0x00020000
+#define CONFIG_SYS_DDR_TIMING_0         0x00330004
+#define CONFIG_SYS_DDR_TIMING_1         0x6F6B4644
+#define CONFIG_SYS_DDR_TIMING_2         0x002888D0
+#define CONFIG_SYS_DDR_SDRAM_CFG	0x47000000
+#define CONFIG_SYS_DDR_SDRAM_CFG_2	0x04401040
+#define CONFIG_SYS_DDR_SDRAM_MODE	0x40401521
+#define CONFIG_SYS_DDR_SDRAM_MODE_2	0x8000C000
+#define CONFIG_SYS_DDR_SDRAM_INTERVAL	0x03E00000
+#define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	0x01000000
+#define CONFIG_SYS_DDR_TIMING_4         0x00220001
+#define CONFIG_SYS_DDR_TIMING_5         0x03402400
+#define CONFIG_SYS_DDR_ZQ_CNTL		0x89080600
+#define CONFIG_SYS_DDR_WRLVL_CNTL	0x0655A604
+#define CONFIG_SYS_DDR_CDR_1		0x80040000
+#define CONFIG_SYS_DDR_CDR_2		0x00000000
+#define CONFIG_SYS_DDR_OCD_CTRL         0x00000000
+#define CONFIG_SYS_DDR_OCD_STATUS       0x00000000
+#define CONFIG_SYS_DDR_CONTROL          0xc7000000      /* Type = DDR3 */
+#define CONFIG_SYS_DDR_CONTROL2         0x24400000
+
+#define CONFIG_SYS_DDR_ERR_INT_EN       0x0000000d
+#define CONFIG_SYS_DDR_ERR_DIS          0x00000000
+#define CONFIG_SYS_DDR_SBE              0x00010000
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+/*
+ * Local Bus Definitions
+ */
+
+#define CONFIG_SYS_FLASH_BASE		0xfe000000	/* start of FLASH 32M */
+#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_SYS_BCSR_BASE		0xf8000000
+#define CONFIG_SYS_BCSR_BASE_PHYS	CONFIG_SYS_BCSR_BASE
+
+/*Chip select 0 - Flash*/
+#define CONFIG_FLASH_BR_PRELIM		0xfe000801
+#define	CONFIG_FLASH_OR_PRELIM		0xfe000ff7
+
+/*Chip select 1 - BCSR*/
+#define CONFIG_SYS_BR1_PRELIM		0xf8000801
+#define	CONFIG_SYS_OR1_PRELIM		0xffffe9f7
+
+/*Chip select 4 - PIB*/
+#define CONFIG_SYS_BR4_PRELIM		0xf8008801
+#define CONFIG_SYS_OR4_PRELIM		0xffffe9f7
+
+/*Chip select 5 - PIB*/
+#define CONFIG_SYS_BR5_PRELIM		0xf8010801
+#define CONFIG_SYS_OR5_PRELIM		0xffffe9f7
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* sectors per device */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#if defined(CONFIG_RAMBOOT_NAND)
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#else
+#undef CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+/* Chip select 3 - NAND */
+#ifndef CONFIG_NAND_SPL
+#define CONFIG_SYS_NAND_BASE		0xFC000000
+#else
+#define CONFIG_SYS_NAND_BASE		0xFFF00000
+#endif
+
+/* NAND boot: 4K NAND loader config */
+#define CONFIG_SYS_NAND_SPL_SIZE	0x1000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	((512 << 10) - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_DST	(CONFIG_SYS_INIT_L2_ADDR)
+#define CONFIG_SYS_NAND_U_BOOT_START \
+	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(0)
+#define CONFIG_SYS_NAND_U_BOOT_RELOC	(CONFIG_SYS_INIT_L2_END - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP	((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
+
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE, }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE	1
+#define CONFIG_CMD_NAND			1
+#define CONFIG_NAND_FSL_ELBC		1
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+#define CONFIG_SYS_NAND_BR_PRELIM	(CONFIG_SYS_NAND_BASE_PHYS \
+				| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
+				| BR_PS_8	     /* Port Size = 8 bit */ \
+				| BR_MS_FCM	     /* MSEL = FCM */ \
+				| BR_V)		     /* valid */
+#define CONFIG_SYS_NAND_OR_PRELIM	(0xFFFC0000	     /* length 256K */ \
+				| OR_FCM_CSCT \
+				| OR_FCM_CST \
+				| OR_FCM_CHT \
+				| OR_FCM_SCY_1 \
+				| OR_FCM_TRLX \
+				| OR_FCM_EHTR)
+
+#ifdef CONFIG_RAMBOOT_NAND
+#define CONFIG_SYS_BR0_PRELIM	CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
+#define CONFIG_SYS_OR0_PRELIM	CONFIG_SYS_NAND_OR_PRELIM/* NAND Options */
+#define CONFIG_SYS_BR3_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
+#define CONFIG_SYS_OR3_PRELIM	CONFIG_FLASH_OR_PRELIM	/* NOR Options */
+#else
+#define CONFIG_SYS_BR0_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM	CONFIG_FLASH_OR_PRELIM	/* NOR Options */
+#define CONFIG_SYS_BR3_PRELIM	CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
+#define CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#endif
+
+#define CONFIG_SYS_LBC_LCRR	0x00000004	/* LB clock ratio reg */
+#define CONFIG_SYS_LBC_LBCR	0x00040000	/* LB config reg */
+#define CONFIG_SYS_LBC_LSRT	0x20000000	/* LB sdram refresh timer */
+#define CONFIG_SYS_LBC_MRTPR	0x00000000	/* LB refresh timer prescal*/
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000  /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000	    /* Size of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)	/* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN	(512 * 1024)	/* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE    1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
+
+/* Use the HUSH parser*/
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef  CONFIG_SYS_HUSH_PARSER
+#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT		1
+#define CONFIG_OF_BOARD_SETUP		1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
+
+/*
+ * I2C2 EEPROM
+ */
+#define CONFIG_ID_EEPROM
+#ifdef CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#endif
+#define CONFIG_SYS_I2C_EEPROM_ADDR      0x52
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_EEPROM_BUS_NUM       1
+
+#define PLPPAR1_I2C_BIT_MASK		0x0000000F
+#define PLPPAR1_I2C2_VAL		0x00000000
+#define PLPPAR1_ESDHC_VAL		0x0000000A
+#define PLPDIR1_I2C_BIT_MASK		0x0000000F
+#define PLPDIR1_I2C2_VAL		0x0000000F
+#define PLPDIR1_ESDHC_VAL		0x00000006
+#define PLPPAR1_UART0_BIT_MASK		0x00000fc0
+#define PLPPAR1_ESDHC_4BITS_VAL		0x00000a80
+#define PLPDIR1_UART0_BIT_MASK		0x00000fc0
+#define PLPDIR1_ESDHC_4BITS_VAL		0x00000a80
+
+/*
+ * General PCI
+ * Memory Addresses are mapped 1-1. I/O is mapped from 0
+ */
+#define CONFIG_SYS_PCIE1_NAME		"Slot"
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xe2800000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xe2800000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000	/* 8M */
+
+#define CONFIG_SYS_SRIO1_MEM_VIRT	0xC0000000
+#define CONFIG_SYS_SRIO1_MEM_BUS	0xC0000000
+#define CONFIG_SYS_SRIO1_MEM_PHYS	CONFIG_SYS_SRIO1_MEM_BUS
+#define CONFIG_SYS_SRIO1_MEM_SIZE	0x20000000	/* 512M */
+
+#ifdef CONFIG_QE
+/*
+ * QE UEC ethernet configuration
+ */
+#define CONFIG_SYS_UCC_RGMII_MODE	/* Set UCC work at RGMII by default */
+#undef CONFIG_SYS_UCC_RMII_MODE		/* Set UCC work at RMII mode */
+
+#define CONFIG_MIIM_ADDRESS	(CONFIG_SYS_CCSRBAR + 0x82120)
+#define CONFIG_UEC_ETH
+#define CONFIG_ETHPRIME         "UEC0"
+#define CONFIG_PHY_MODE_NEED_CHANGE
+
+#define CONFIG_UEC_ETH1         /* GETH1 */
+#define CONFIG_HAS_ETH0
+
+#ifdef CONFIG_UEC_ETH1
+#define CONFIG_SYS_UEC1_UCC_NUM        0       /* UCC1 */
+#define CONFIG_SYS_UEC1_RX_CLK         QE_CLK_NONE
+#if defined(CONFIG_SYS_UCC_RGMII_MODE)
+#define CONFIG_SYS_UEC1_TX_CLK         QE_CLK12
+#define CONFIG_SYS_UEC1_ETH_TYPE       GIGA_ETH
+#define CONFIG_SYS_UEC1_PHY_ADDR       7
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
+#elif defined(CONFIG_SYS_UCC_RMII_MODE)
+#define CONFIG_SYS_UEC1_TX_CLK         QE_CLK16	/* CLK16 for RMII */
+#define CONFIG_SYS_UEC1_ETH_TYPE       FAST_ETH
+#define CONFIG_SYS_UEC1_PHY_ADDR       8	/* 0x8 for RMII */
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
+#endif /* CONFIG_SYS_UCC_RGMII_MODE */
+#endif /* CONFIG_UEC_ETH1 */
+
+#define CONFIG_UEC_ETH2         /* GETH2 */
+#define CONFIG_HAS_ETH1
+
+#ifdef CONFIG_UEC_ETH2
+#define CONFIG_SYS_UEC2_UCC_NUM        1       /* UCC2 */
+#define CONFIG_SYS_UEC2_RX_CLK         QE_CLK_NONE
+#if defined(CONFIG_SYS_UCC_RGMII_MODE)
+#define CONFIG_SYS_UEC2_TX_CLK         QE_CLK17
+#define CONFIG_SYS_UEC2_ETH_TYPE       GIGA_ETH
+#define CONFIG_SYS_UEC2_PHY_ADDR       1
+#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
+#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
+#elif defined(CONFIG_SYS_UCC_RMII_MODE)
+#define CONFIG_SYS_UEC2_TX_CLK         QE_CLK16	/* CLK 16 for RMII */
+#define CONFIG_SYS_UEC2_ETH_TYPE       FAST_ETH
+#define CONFIG_SYS_UEC2_PHY_ADDR       0x9	/* 0x9 for RMII */
+#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
+#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
+#endif /* CONFIG_SYS_UCC_RGMII_MODE */
+#endif /* CONFIG_UEC_ETH2 */
+
+#define CONFIG_UEC_ETH3         /* GETH3 */
+#define CONFIG_HAS_ETH2
+
+#ifdef CONFIG_UEC_ETH3
+#define CONFIG_SYS_UEC3_UCC_NUM        2       /* UCC3 */
+#define CONFIG_SYS_UEC3_RX_CLK         QE_CLK_NONE
+#if defined(CONFIG_SYS_UCC_RGMII_MODE)
+#define CONFIG_SYS_UEC3_TX_CLK         QE_CLK12
+#define CONFIG_SYS_UEC3_ETH_TYPE       GIGA_ETH
+#define CONFIG_SYS_UEC3_PHY_ADDR       2
+#define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
+#define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000
+#elif defined(CONFIG_SYS_UCC_RMII_MODE)
+#define CONFIG_SYS_UEC3_TX_CLK		QE_CLK16 /* CLK_16 for RMII */
+#define CONFIG_SYS_UEC3_ETH_TYPE	FAST_ETH
+#define CONFIG_SYS_UEC3_PHY_ADDR	0xA     /* 0xA for RMII */
+#define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
+#define CONFIG_SYS_UEC3_INTERFACE_SPEED 100
+#endif /* CONFIG_SYS_UCC_RGMII_MODE */
+#endif /* CONFIG_UEC_ETH3 */
+
+#define CONFIG_UEC_ETH4         /* GETH4 */
+#define CONFIG_HAS_ETH3
+
+#ifdef CONFIG_UEC_ETH4
+#define CONFIG_SYS_UEC4_UCC_NUM        3       /* UCC4 */
+#define CONFIG_SYS_UEC4_RX_CLK         QE_CLK_NONE
+#if defined(CONFIG_SYS_UCC_RGMII_MODE)
+#define CONFIG_SYS_UEC4_TX_CLK         QE_CLK17
+#define CONFIG_SYS_UEC4_ETH_TYPE       GIGA_ETH
+#define CONFIG_SYS_UEC4_PHY_ADDR       3
+#define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
+#define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000
+#elif defined(CONFIG_SYS_UCC_RMII_MODE)
+#define CONFIG_SYS_UEC4_TX_CLK		QE_CLK16 /* CLK16 for RMII */
+#define CONFIG_SYS_UEC4_ETH_TYPE	FAST_ETH
+#define CONFIG_SYS_UEC4_PHY_ADDR	0xB     /* 0xB for RMII */
+#define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
+#define CONFIG_SYS_UEC4_INTERFACE_SPEED 100
+#endif /* CONFIG_SYS_UCC_RGMII_MODE */
+#endif /* CONFIG_UEC_ETH4 */
+
+#undef CONFIG_UEC_ETH6         /* GETH6 */
+#define CONFIG_HAS_ETH5
+
+#ifdef CONFIG_UEC_ETH6
+#define CONFIG_SYS_UEC6_UCC_NUM        5       /* UCC6 */
+#define CONFIG_SYS_UEC6_RX_CLK         QE_CLK_NONE
+#define CONFIG_SYS_UEC6_TX_CLK         QE_CLK_NONE
+#define CONFIG_SYS_UEC6_ETH_TYPE       GIGA_ETH
+#define CONFIG_SYS_UEC6_PHY_ADDR       4
+#define CONFIG_SYS_UEC6_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
+#define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000
+#endif /* CONFIG_UEC_ETH6 */
+
+#undef CONFIG_UEC_ETH8         /* GETH8 */
+#define CONFIG_HAS_ETH7
+
+#ifdef CONFIG_UEC_ETH8
+#define CONFIG_SYS_UEC8_UCC_NUM        7       /* UCC8 */
+#define CONFIG_SYS_UEC8_RX_CLK         QE_CLK_NONE
+#define CONFIG_SYS_UEC8_TX_CLK         QE_CLK_NONE
+#define CONFIG_SYS_UEC8_ETH_TYPE       GIGA_ETH
+#define CONFIG_SYS_UEC8_PHY_ADDR       6
+#define CONFIG_SYS_UEC8_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
+#define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000
+#endif /* CONFIG_UEC_ETH8 */
+
+#endif /* CONFIG_QE */
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+#define CONFIG_E1000			/* Define e1000 pci Ethernet card */
+
+#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+
+#endif	/* CONFIG_PCI */
+
+/*
+ * Environment
+ */
+#if defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_RAMBOOT_NAND)
+#define CONFIG_ENV_IS_IN_NAND	1
+#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET	((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
+#endif
+#else
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SECT_SIZE	0x20000	/* 128K(one sector) for env */
+#define CONFIG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/* QE microcode/firmware address */
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_QE_FW_ADDR	0xfff00000
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
+
+#if defined(CONFIG_PCI)
+    #define CONFIG_CMD_PCI
+#endif
+
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+#define CONFIG_MMC     1
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_ESDHC_PIN_MUX
+#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	2048		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	512		/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+						/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	32		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+						/* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20) /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_HOSTNAME mpc8569mds
+#define CONFIG_ROOTPATH  "/nfsroot"
+#define CONFIG_BOOTFILE  "your.uImage"
+
+#define CONFIG_SERVERIP  192.168.1.1
+#define CONFIG_GATEWAYIP 192.168.1.1
+#define CONFIG_NETMASK   255.255.255.0
+
+#define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
+
+#define CONFIG_BOOTDELAY 10       /* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS           /* the boot command will set bootargs*/
+
+#define CONFIG_BAUDRATE	115200
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"consoledev=ttyS0\0"						\
+	"ramdiskaddr=600000\0"						\
+	"ramdiskfile=your.ramdisk.u-boot\0"				\
+	"fdtaddr=400000\0"						\
+	"fdtfile=your.fdt.dtb\0"					\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+	"nfsroot=$serverip:$rootpath "					\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw "			\
+	"console=$consoledev,$baudrate $othbootargs\0"			\
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"run nfsargs;"							\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+	"run ramargs;"							\
+	"tftp $ramdiskaddr $ramdiskfile;"				\
+	"tftp $loadaddr $bootfile;"					\
+	"bootm $loadaddr $ramdiskaddr"
+
+#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/MPC8572DS.h b/qemu/roms/u-boot/include/configs/MPC8572DS.h
new file mode 100644
index 000000000..48ae9d4ca
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/MPC8572DS.h
@@ -0,0 +1,772 @@
+/*
+ * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * mpc8572ds board configuration file
+ *
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
+#include "../board/freescale/common/ics307_clk.h"
+
+#ifdef CONFIG_36BIT
+#define CONFIG_PHYS_64BIT
+#endif
+
+#ifdef CONFIG_NAND
+#define CONFIG_NAND_U_BOOT
+#define CONFIG_RAMBOOT_NAND
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
+#else
+#define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds
+#define CONFIG_SYS_TEXT_BASE	0xf8f82000
+#endif /* CONFIG_NAND_SPL */
+#endif
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xeff40000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE		1	/* BOOKE */
+#define CONFIG_E500		1	/* BOOKE e500 family */
+#define CONFIG_MPC8572		1
+#define CONFIG_MPC8572DS	1
+#define CONFIG_MP		1	/* support multiple processors */
+
+#define CONFIG_FSL_ELBC		1	/* Has Enhanced localbus controller */
+#define CONFIG_PCI		1	/* Enable PCI/PCIE */
+#define CONFIG_PCIE1		1	/* PCIE controler 1 (slot 1) */
+#define CONFIG_PCIE2		1	/* PCIE controler 2 (slot 2) */
+#define CONFIG_PCIE3		1	/* PCIE controler 3 (ULI bridge) */
+#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
+#define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
+
+#define CONFIG_FSL_LAW		1	/* Use common FSL init code */
+
+#define CONFIG_TSEC_ENET		/* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk() /* sysclk for MPC85xx */
+#define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk() /* ddrclk for MPC85xx */
+#define CONFIG_ICS307_REFCLK_HZ	33333000  /* ICS307 clock chip ref freq */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* toggle branch predition */
+
+#define CONFIG_ENABLE_36BIT_PHYS	1
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP			1
+#define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
+#endif
+
+#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x7fffffff
+#define CONFIG_PANIC_HANG	/* do not reset board on panic */
+
+/*
+ * Config the L2 Cache as L2 SRAM
+ */
+#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS		0xff8f80000ull
+#else
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS		CONFIG_SYS_INIT_L2_ADDR
+#endif
+#define CONFIG_SYS_L2_SIZE		(512 << 10)
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+
+#define CONFIG_SYS_CCSRBAR		0xffe00000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+
+#if defined(CONFIG_NAND_SPL)
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#endif
+
+/* DDR Setup */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_FSL_DDR2
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
+#define CONFIG_DDR_SPD
+
+#define CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_NUM_DDR_CONTROLLERS	2
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	2
+
+/* I2C addresses of SPD EEPROMs */
+#define CONFIG_SYS_SPD_BUS_NUM		1	/* SPD EEPROMS locate on I2C bus 1 */
+#define SPD_EEPROM_ADDRESS1	0x51	/* CTLR 0 DIMM 0 */
+#define SPD_EEPROM_ADDRESS2	0x52	/* CTLR 1 DIMM 0 */
+
+/* These are used when DDR doesn't use SPD.  */
+#define CONFIG_SYS_SDRAM_SIZE		512		/* DDR is 512MB */
+#define CONFIG_SYS_DDR_CS0_BNDS		0x0000001F
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80010202	/* Enable, no interleaving */
+#define CONFIG_SYS_DDR_TIMING_3		0x00020000
+#define CONFIG_SYS_DDR_TIMING_0		0x00260802
+#define CONFIG_SYS_DDR_TIMING_1		0x626b2634
+#define CONFIG_SYS_DDR_TIMING_2		0x062874cf
+#define CONFIG_SYS_DDR_MODE_1		0x00440462
+#define CONFIG_SYS_DDR_MODE_2		0x00000000
+#define CONFIG_SYS_DDR_INTERVAL		0x0c300100
+#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
+#define CONFIG_SYS_DDR_CLK_CTRL		0x00800000
+#define CONFIG_SYS_DDR_OCD_CTRL		0x00000000
+#define CONFIG_SYS_DDR_OCD_STATUS	0x00000000
+#define CONFIG_SYS_DDR_CONTROL		0xc3000008	/* Type = DDR2 */
+#define CONFIG_SYS_DDR_CONTROL2		0x24400000
+
+#define CONFIG_SYS_DDR_ERR_INT_EN	0x0000000d
+#define CONFIG_SYS_DDR_ERR_DIS		0x00000000
+#define CONFIG_SYS_DDR_SBE		0x00010000
+
+/*
+ * Make sure required options are set
+ */
+#ifndef CONFIG_SPD_EEPROM
+#error ("CONFIG_SPD_EEPROM is required")
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
+ * 0x8000_0000	0xbfff_ffff	PCI Express Mem		1G non-cacheable
+ * 0xc000_0000	0xdfff_ffff	PCI			512M non-cacheable
+ * 0xe100_0000	0xe3ff_ffff	PCI IO range		4M non-cacheable
+ *
+ * Localbus cacheable (TBD)
+ * 0xXXXX_XXXX	0xXXXX_XXXX	SRAM			YZ M Cacheable
+ *
+ * Localbus non-cacheable
+ * 0xe000_0000	0xe80f_ffff	Promjet/free		128M non-cacheable
+ * 0xe800_0000	0xefff_ffff	FLASH			128M non-cacheable
+ * 0xffa0_0000	0xffaf_ffff	NAND			1M non-cacheable
+ * 0xffdf_0000	0xffdf_7fff	PIXIS			32K non-cacheable TLB0
+ * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K Cacheable TLB0
+ * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
+ */
+
+/*
+ * Local Bus Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE		0xe0000000	/* start of FLASH 128M */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_FLASH_BASE_PHYS	0xfe0000000ull
+#else
+#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+#endif
+
+
+#define CONFIG_FLASH_BR_PRELIM \
+	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
+#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
+
+#define CONFIG_SYS_BR1_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
+#define CONFIG_SYS_OR1_PRELIM	0xf8000ff7
+
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
+
+#if defined(CONFIG_RAMBOOT_NAND)
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#else
+#undef CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
+
+#define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
+
+#define CONFIG_HWCONFIG			/* enable hwconfig */
+#define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
+#define PIXIS_BASE	0xffdf0000	/* PIXIS registers */
+#ifdef CONFIG_PHYS_64BIT
+#define PIXIS_BASE_PHYS	0xfffdf0000ull
+#else
+#define PIXIS_BASE_PHYS	PIXIS_BASE
+#endif
+
+#define CONFIG_SYS_BR3_PRELIM	(BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR3_PRELIM		0xffffeff7	/* 32KB but only 4k mapped */
+
+#define PIXIS_ID		0x0	/* Board ID at offset 0 */
+#define PIXIS_VER		0x1	/* Board version at offset 1 */
+#define PIXIS_PVER		0x2	/* PIXIS FPGA version at offset 2 */
+#define PIXIS_CSR   		0x3	/* PIXIS General control/status register */
+#define PIXIS_RST		0x4	/* PIXIS Reset Control register */
+#define PIXIS_PWR		0x5	/* PIXIS Power status register */
+#define PIXIS_AUX		0x6	/* Auxiliary 1 register */
+#define PIXIS_SPD		0x7	/* Register for SYSCLK speed */
+#define PIXIS_AUX2		0x8	/* Auxiliary 2 register */
+#define PIXIS_VCTL		0x10	/* VELA Control Register */
+#define PIXIS_VSTAT		0x11	/* VELA Status Register */
+#define PIXIS_VCFGEN0		0x12	/* VELA Config Enable 0 */
+#define PIXIS_VCFGEN1		0x13	/* VELA Config Enable 1 */
+#define PIXIS_VCORE0	 	0x14	/* VELA VCORE0 Register */
+#define PIXIS_VBOOT		0x16	/* VELA VBOOT Register */
+#define PIXIS_VBOOT_LBMAP	0xc0	/* VBOOT - CFG_LBMAP */
+#define PIXIS_VBOOT_LBMAP_NOR0	0x00	/* cfg_lbmap - boot from NOR 0 */
+#define PIXIS_VBOOT_LBMAP_PJET	0x01	/* cfg_lbmap - boot from projet */
+#define PIXIS_VBOOT_LBMAP_NAND	0x02	/* cfg_lbmap - boot from NAND */
+#define PIXIS_VBOOT_LBMAP_NOR1	0x03	/* cfg_lbmap - boot from NOR 1 */
+#define PIXIS_VSPEED0		0x17	/* VELA VSpeed 0 */
+#define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
+#define PIXIS_VSPEED2		0x19	/* VELA VSpeed 2 */
+#define PIXIS_VSYSCLK0		0x1C	/* VELA SYSCLK0 Register */
+#define PIXIS_VSYSCLK1		0x1D	/* VELA SYSCLK1 Register */
+#define PIXIS_VSYSCLK2		0x1E	/* VELA SYSCLK2 Register */
+#define PIXIS_VDDRCLK0		0x1F	/* VELA DDRCLK0 Register */
+#define PIXIS_VDDRCLK1		0x20	/* VELA DDRCLK1 Register */
+#define PIXIS_VDDRCLK2		0x21	/* VELA DDRCLK2 Register */
+#define PIXIS_VWATCH		0x24    /* Watchdog Register */
+#define PIXIS_LED		0x25    /* LED Register */
+
+#define PIXIS_SPD_SYSCLK_MASK		0x7		/* SYSCLK option */
+
+/* old pixis referenced names */
+#define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
+#define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
+#define CONFIG_SYS_PIXIS_VBOOT_MASK	0xc0
+#define PIXIS_VSPEED2_TSEC1SER	0x8
+#define PIXIS_VSPEED2_TSEC2SER	0x4
+#define PIXIS_VSPEED2_TSEC3SER	0x2
+#define PIXIS_VSPEED2_TSEC4SER	0x1
+#define PIXIS_VCFGEN1_TSEC1SER	0x20
+#define PIXIS_VCFGEN1_TSEC2SER	0x20
+#define PIXIS_VCFGEN1_TSEC3SER	0x20
+#define PIXIS_VCFGEN1_TSEC4SER	0x20
+#define PIXIS_VSPEED2_MASK	(PIXIS_VSPEED2_TSEC1SER \
+					| PIXIS_VSPEED2_TSEC2SER \
+					| PIXIS_VSPEED2_TSEC3SER \
+					| PIXIS_VSPEED2_TSEC4SER)
+#define PIXIS_VCFGEN1_MASK	(PIXIS_VCFGEN1_TSEC1SER \
+					| PIXIS_VCFGEN1_TSEC2SER \
+					| PIXIS_VCFGEN1_TSEC3SER \
+					| PIXIS_VCFGEN1_TSEC4SER)
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000	/* Size of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
+
+#ifndef CONFIG_NAND_SPL
+#define CONFIG_SYS_NAND_BASE		0xffa00000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_NAND_BASE_PHYS	0xfffa00000ull
+#else
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#endif
+#else
+#define CONFIG_SYS_NAND_BASE		0xfff00000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_NAND_BASE_PHYS	0xffff00000ull
+#else
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#endif
+#endif
+
+#define CONFIG_SYS_NAND_BASE_LIST     { CONFIG_SYS_NAND_BASE,\
+				CONFIG_SYS_NAND_BASE + 0x40000, \
+				CONFIG_SYS_NAND_BASE + 0x80000,\
+				CONFIG_SYS_NAND_BASE + 0xC0000}
+#define CONFIG_SYS_MAX_NAND_DEVICE    4
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND		1
+#define CONFIG_NAND_FSL_ELBC	1
+#define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
+#define CONFIG_SYS_NAND_MAX_OOBFREE	5
+#define CONFIG_SYS_NAND_MAX_ECCPOS	56
+
+/* NAND boot: 4K NAND loader config */
+#define CONFIG_SYS_NAND_SPL_SIZE	0x1000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	((512 << 10) - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_DST	(CONFIG_SYS_INIT_L2_ADDR)
+#define CONFIG_SYS_NAND_U_BOOT_START \
+		(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(0)
+#define CONFIG_SYS_NAND_U_BOOT_RELOC	(CONFIG_SYS_INIT_L2_END - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP	((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
+
+
+/* NAND flash config */
+#define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+			       | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+			       | BR_PS_8	       /* Port Size = 8 bit */ \
+			       | BR_MS_FCM	       /* MSEL = FCM */ \
+			       | BR_V)		       /* valid */
+#define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000	      /* length 256K */ \
+			       | OR_FCM_PGS	       /* Large Page*/ \
+			       | OR_FCM_CSCT \
+			       | OR_FCM_CST \
+			       | OR_FCM_CHT \
+			       | OR_FCM_SCY_1 \
+			       | OR_FCM_TRLX \
+			       | OR_FCM_EHTR)
+
+#ifdef CONFIG_RAMBOOT_NAND
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#define CONFIG_SYS_BR2_PRELIM  CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
+#define CONFIG_SYS_OR2_PRELIM  CONFIG_FLASH_OR_PRELIM	/* NOR Options */
+#else
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_FLASH_OR_PRELIM	/* NOR Options */
+#define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
+#define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#endif
+#define CONFIG_SYS_BR4_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
+			       | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+			       | BR_PS_8	       /* Port Size = 8 bit */ \
+			       | BR_MS_FCM	       /* MSEL = FCM */ \
+			       | BR_V)		       /* valid */
+#define CONFIG_SYS_OR4_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#define CONFIG_SYS_BR5_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\
+			       | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+			       | BR_PS_8	       /* Port Size = 8 bit */ \
+			       | BR_MS_FCM	       /* MSEL = FCM */ \
+			       | BR_V)		       /* valid */
+#define CONFIG_SYS_OR5_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+
+#define CONFIG_SYS_BR6_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)\
+			       | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+			       | BR_PS_8	       /* Port Size = 8 bit */ \
+			       | BR_MS_FCM	       /* MSEL = FCM */ \
+			       | BR_V)		       /* valid */
+#define CONFIG_SYS_OR6_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT		1
+#define CONFIG_OF_BOARD_SETUP		1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+/* new uImage format support */
+#define CONFIG_FIT		1
+#define CONFIG_FIT_VERBOSE	1 /* enable fit_format_{error,warning}() */
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x29} }
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+
+/*
+ * I2C2 EEPROM
+ */
+#define CONFIG_ID_EEPROM
+#ifdef CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#endif
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_BUS_NUM	1
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 3, direct to uli, tgtid 3, Base address 8000 */
+#define CONFIG_SYS_PCIE3_NAME		"ULI"
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0x80000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc00000000ull
+#else
+#define CONFIG_SYS_PCIE3_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0x80000000
+#endif
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xffc00000
+#define CONFIG_SYS_PCIE3_IO_BUS	0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xfffc00000ull
+#else
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xffc00000
+#endif
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 2, Slot 2, tgtid 2, Base address 9000 */
+#define CONFIG_SYS_PCIE2_NAME		"Slot 1"
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
+#else
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
+#endif
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xffc10000
+#define CONFIG_SYS_PCIE2_IO_BUS	0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xfffc10000ull
+#else
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
+#endif
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 1, Slot 1, tgtid 1, Base address a000 */
+#define CONFIG_SYS_PCIE1_NAME		"Slot 2"
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0xc0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc40000000ull
+#else
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc0000000
+#endif
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc20000
+#define CONFIG_SYS_PCIE1_IO_BUS	0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xfffc20000ull
+#else
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xffc20000
+#endif
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+
+#if defined(CONFIG_PCI)
+
+/*PCIE video card used*/
+#define VIDEO_IO_OFFSET		CONFIG_SYS_PCIE1_IO_VIRT
+
+/* video */
+#define CONFIG_VIDEO
+
+#if defined(CONFIG_VIDEO)
+#define CONFIG_BIOSEMU
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_ATI_RADEON_FB
+#define CONFIG_VIDEO_LOGO
+/*#define CONFIG_CONSOLE_CURSOR*/
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
+#endif
+
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+#undef CONFIG_RTL8139
+#define CONFIG_E1000			/* Define e1000 pci Ethernet card */
+
+#ifndef CONFIG_PCI_PNP
+	#define PCI_ENET0_IOADDR	CONFIG_SYS_PCIE3_IO_BUS
+	#define PCI_ENET0_MEMADDR	CONFIG_SYS_PCIE3_IO_BUS
+	#define PCI_IDSEL_NUMBER	0x11	/* IDSEL = AD11 */
+#endif
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SCSI_AHCI
+
+#ifdef CONFIG_SCSI_AHCI
+#define CONFIG_LIBATA
+#define CONFIG_SATA_ULI5288
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	4
+#define CONFIG_SYS_SCSI_MAX_LUN	1
+#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
+#define CONFIG_SYS_SCSI_MAXDEVICE	CONFIG_SYS_SCSI_MAX_DEVICE
+#endif /* SCSI */
+
+#endif	/* CONFIG_PCI */
+
+
+#if defined(CONFIG_TSEC_ENET)
+
+#define CONFIG_MII		1	/* MII PHY management */
+#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"eTSEC2"
+#define CONFIG_TSEC3	1
+#define CONFIG_TSEC3_NAME	"eTSEC3"
+#define CONFIG_TSEC4	1
+#define CONFIG_TSEC4_NAME	"eTSEC4"
+
+#define CONFIG_PIXIS_SGMII_CMD
+#define CONFIG_FSL_SGMII_RISER	1
+#define SGMII_RISER_PHY_OFFSET	0x1c
+
+#ifdef CONFIG_FSL_SGMII_RISER
+#define CONFIG_SYS_TBIPA_VALUE		0x10 /* avoid conflict with eTSEC4 paddr */
+#endif
+
+#define TSEC1_PHY_ADDR		0
+#define TSEC2_PHY_ADDR		1
+#define TSEC3_PHY_ADDR		2
+#define TSEC4_PHY_ADDR		3
+
+#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC4_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC3_PHYIDX		0
+#define TSEC4_PHYIDX		0
+
+#define CONFIG_ETHPRIME		"eTSEC1"
+
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+
+#if defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_RAMBOOT_NAND)
+#define CONFIG_ENV_IS_IN_NAND	1
+#define CONFIG_ENV_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET	((512 * 1024)\
+				+ CONFIG_SYS_NAND_BLOCK_SIZE)
+#endif
+
+#else
+	#define CONFIG_ENV_IS_IN_FLASH	1
+	#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
+	#define CONFIG_ENV_ADDR	0xfff80000
+	#else
+	#define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+	#endif
+	#define CONFIG_ENV_SIZE	0x2000
+	#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ERRATA
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
+
+#if defined(CONFIG_PCI)
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_SCSI
+#define CONFIG_CMD_EXT2
+#endif
+
+/*
+ * USB
+ */
+#define CONFIG_USB_EHCI
+
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_USB_EHCI_PCI
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_STORAGE
+#define CONFIG_PCI_EHCI_DEVICE			0
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	2
+#endif
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+/* The mac addresses for all ethernet interface */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_ETHADDR	00:E0:0C:02:00:FD
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR	00:E0:0C:02:01:FD
+#define CONFIG_HAS_ETH2
+#define CONFIG_ETH2ADDR	00:E0:0C:02:02:FD
+#define CONFIG_HAS_ETH3
+#define CONFIG_ETH3ADDR	00:E0:0C:02:03:FD
+#endif
+
+#define CONFIG_IPADDR		192.168.1.254
+
+#define CONFIG_HOSTNAME		unknown
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */
+
+#define CONFIG_SERVERIP		192.168.1.1
+#define CONFIG_GATEWAYIP	192.168.1.1
+#define CONFIG_NETMASK		255.255.255.0
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE	115200
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+"hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0"		\
+"netdev=eth0\0"						\
+"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"				\
+"tftpflash=tftpboot $loadaddr $uboot; "			\
+	"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
+		" +$filesize; "	\
+	"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
+		" +$filesize; "	\
+	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
+		" $filesize; "	\
+	"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
+		" +$filesize; "	\
+	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
+		" $filesize\0"	\
+"consoledev=ttyS0\0"				\
+"ramdiskaddr=2000000\0"			\
+"ramdiskfile=8572ds/ramdisk.uboot\0"		\
+"fdtaddr=c00000\0"				\
+"fdtfile=8572ds/mpc8572ds.dtb\0"		\
+"bdev=sda3\0"
+
+#define CONFIG_HDBOOT				\
+ "setenv bootargs root=/dev/$bdev rw "		\
+ "console=$consoledev,$baudrate $othbootargs;"	\
+ "tftp $loadaddr $bootfile;"			\
+ "tftp $fdtaddr $fdtfile;"			\
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND		\
+ "setenv bootargs root=/dev/nfs rw "	\
+ "nfsroot=$serverip:$rootpath "		\
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;"	\
+ "tftp $loadaddr $bootfile;"		\
+ "tftp $fdtaddr $fdtfile;"		\
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND		\
+ "setenv bootargs root=/dev/ram rw "	\
+ "console=$consoledev,$baudrate $othbootargs;"	\
+ "tftp $ramdiskaddr $ramdiskfile;"	\
+ "tftp $loadaddr $bootfile;"		\
+ "tftp $fdtaddr $fdtfile;"		\
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_HDBOOT
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/MPC8610HPCD.h b/qemu/roms/u-boot/include/configs/MPC8610HPCD.h
new file mode 100644
index 000000000..e6d570a6a
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/MPC8610HPCD.h
@@ -0,0 +1,674 @@
+/*
+ * Copyright 2007-2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+/*
+ * MPC8610HPCD board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_MPC8610		1	/* MPC8610 specific */
+#define CONFIG_MPC8610HPCD	1	/* MPC8610HPCD board specific */
+#define CONFIG_LINUX_RESET_VEC	0x100	/* Reset vector used by Linux */
+
+#define	CONFIG_SYS_TEXT_BASE	0xfff00000
+
+
+/* video */
+#define CONFIG_FSL_DIU_FB
+
+#ifdef CONFIG_FSL_DIU_FB
+#define CONFIG_SYS_DIU_ADDR	(CONFIG_SYS_CCSRBAR + 0x2c000)
+#define CONFIG_VIDEO
+#define CONFIG_CMD_BMP
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#endif
+
+#ifdef RUN_DIAG
+#define CONFIG_SYS_DIAG_ADDR		0xff800000
+#endif
+
+/*
+ * virtual address to be used for temporary mappings.  There
+ * should be 128k free at this VA.
+ */
+#define CONFIG_SYS_SCRATCH_VA	0xc0000000
+
+#define CONFIG_PCI		1	/* Enable PCI/PCIE*/
+#define CONFIG_PCI1		1	/* PCI controler 1 */
+#define CONFIG_PCIE1		1	/* PCIe 1 connected to ULI bridge */
+#define CONFIG_PCIE2		1	/* PCIe 2 connected to slot */
+#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
+#define CONFIG_FSL_LAW		1	/* Use common FSL init code */
+
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */
+
+#define CONFIG_BAT_RW		1	/* Use common BAT rw code */
+#define CONFIG_HIGH_BATS	1	/* High BATs supported & enabled */
+#define CONFIG_ALTIVEC		1
+
+/*
+ * L2CR setup -- make sure this is right for your board!
+ */
+#define CONFIG_SYS_L2
+#define L2_INIT		0
+#define L2_ENABLE	(L2CR_L2E |0x00100000 )
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0)
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
+#define CONFIG_MISC_INIT_R		1
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
+#define CONFIG_SYS_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
+
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0x0
+#define CONFIG_SYS_CCSRBAR_PHYS		CONFIG_SYS_CCSRBAR_PHYS_LOW
+
+/* DDR Setup */
+#define CONFIG_SYS_FSL_DDR2
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SPD_EEPROM		/* Use SPD for DDR */
+#define CONFIG_DDR_SPD
+
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_MAX_DDR_BAT_SIZE	0x80000000	/* BAT mapping size */
+#define CONFIG_VERY_BIG_RAM
+
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
+
+/* These are used when DDR doesn't use SPD.  */
+#define CONFIG_SYS_SDRAM_SIZE	256		/* DDR is 256MB */
+
+#if 0 /* TODO */
+#define CONFIG_SYS_DDR_CS0_BNDS	0x0000000F
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80010202	/* Enable, no interleaving */
+#define CONFIG_SYS_DDR_TIMING_3	0x00000000
+#define CONFIG_SYS_DDR_TIMING_0	0x00260802
+#define CONFIG_SYS_DDR_TIMING_1	0x3935d322
+#define CONFIG_SYS_DDR_TIMING_2	0x14904cc8
+#define CONFIG_SYS_DDR_MODE_1		0x00480432
+#define CONFIG_SYS_DDR_MODE_2		0x00000000
+#define CONFIG_SYS_DDR_INTERVAL	0x06180100
+#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
+#define CONFIG_SYS_DDR_CLK_CTRL	0x03800000
+#define CONFIG_SYS_DDR_OCD_CTRL	0x00000000
+#define CONFIG_SYS_DDR_OCD_STATUS	0x00000000
+#define CONFIG_SYS_DDR_CONTROL		0xe3008000	/* Type = DDR2 */
+#define CONFIG_SYS_DDR_CONTROL2	0x04400010
+
+#define CONFIG_SYS_DDR_ERR_INT_EN	0x00000000
+#define CONFIG_SYS_DDR_ERR_DIS		0x00000000
+#define CONFIG_SYS_DDR_SBE		0x000f0000
+
+#endif
+
+
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+
+
+#define CONFIG_SYS_FLASH_BASE		0xf0000000 /* start of FLASH 128M */
+#define CONFIG_SYS_FLASH_BASE2		0xf8000000
+
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
+
+#define CONFIG_SYS_BR0_PRELIM		0xf8001001 /* port size 16bit */
+#define CONFIG_SYS_OR0_PRELIM		0xf8006e65 /* 128MB NOR Flash*/
+
+#define CONFIG_SYS_BR1_PRELIM		0xf0001001 /* port size 16bit */
+#define CONFIG_SYS_OR1_PRELIM		0xf8006e65 /* 128MB Promjet */
+#if 0 /* TODO */
+#define CONFIG_SYS_BR2_PRELIM		0xf0000000
+#define CONFIG_SYS_OR2_PRELIM		0xf0000000 /* 256MB NAND Flash - bank 1 */
+#endif
+#define CONFIG_SYS_BR3_PRELIM		0xe8000801 /* port size 8bit */
+#define CONFIG_SYS_OR3_PRELIM		0xfff06ff7 /* 1MB PIXIS area*/
+
+
+#define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
+#define PIXIS_BASE	0xe8000000	/* PIXIS registers */
+#define PIXIS_ID		0x0	/* Board ID at offset 0 */
+#define PIXIS_VER		0x1	/* Board version at offset 1 */
+#define PIXIS_PVER		0x2	/* PIXIS FPGA version at offset 2 */
+#define PIXIS_RST		0x4	/* PIXIS Reset Control register */
+#define PIXIS_AUX		0x6	/* PIXIS Auxiliary register; Scratch */
+#define PIXIS_SPD		0x7	/* Register for SYSCLK speed */
+#define PIXIS_BRDCFG0		0x8	/* PIXIS Board Configuration Register0*/
+#define PIXIS_VCTL		0x10	/* VELA Control Register */
+#define PIXIS_VCFGEN0		0x12	/* VELA Config Enable 0 */
+#define PIXIS_VCFGEN1		0x13	/* VELA Config Enable 1 */
+#define PIXIS_VBOOT		0x16	/* VELA VBOOT Register */
+#define PIXIS_VSPEED0		0x17	/* VELA VSpeed 0 */
+#define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
+#define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
+#define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
+#define CONFIG_SYS_PIXIS_VBOOT_MASK	0xC0    /* Reset altbank mask */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
+
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000	/* early monitor loc */
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef	CONFIG_SYS_RAMBOOT
+#endif
+
+#if defined(CONFIG_SYS_RAMBOOT)
+#undef CONFIG_SPD_EEPROM
+#define CONFIG_SYS_SDRAM_SIZE	256
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#ifndef CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
+#else
+#define CONFIG_SYS_INIT_RAM_ADDR	0xe4000000	/* Initial RAM address */
+#endif
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 KB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(6 * 1024 * 1024)	/* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Pass open firmware flat tree to kernel
+ */
+#define CONFIG_OF_LIBFDT		1
+#define CONFIG_OF_BOARD_SETUP		1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE	8192
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCI1_MEM_BUS		0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BUS
+#define CONFIG_SYS_PCI1_MEM_VIRT	CONFIG_SYS_PCI1_MEM_BUS
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_IO_BUS	0x0000000
+#define CONFIG_SYS_PCI1_IO_PHYS	0xe1000000
+#define CONFIG_SYS_PCI1_IO_VIRT	0xe1000000
+#define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */
+
+/* controller 1, Base address 0xa000 */
+#define CONFIG_SYS_PCIE1_NAME		"ULI"
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BUS
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xe3000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00100000	/* 1M */
+
+/* controller 2, Base Address 0x9000 */
+#define CONFIG_SYS_PCIE2_NAME		"Slot 1"
+#define CONFIG_SYS_PCIE2_MEM_BUS	0x90000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	CONFIG_SYS_PCIE2_MEM_BUS
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000	/* reuse mem LAW */
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xe2000000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00100000	/* 1M */
+
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+
+#define CONFIG_CMD_NET
+#define CONFIG_PCI_PNP		/* do pci plug-and-play */
+#define CONFIG_CMD_REGINFO
+
+#define CONFIG_ULI526X
+#ifdef CONFIG_ULI526X
+#define CONFIG_ETHADDR   00:E0:0C:00:00:01
+#endif
+
+/************************************************************
+ * USB support
+ ************************************************************/
+#define CONFIG_PCI_OHCI		1
+#define CONFIG_USB_OHCI_NEW		1
+#define CONFIG_USB_KEYBOARD	1
+#define CONFIG_SYS_STDIO_DEREGISTER
+#define CONFIG_SYS_USB_EVENT_POLL	1
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"ohci_pci"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
+#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS	1
+
+#if !defined(CONFIG_PCI_PNP)
+#define PCI_ENET0_IOADDR	0xe0000000
+#define PCI_ENET0_MEMADDR	0xe0000000
+#define PCI_IDSEL_NUMBER	0x0c	/* slot0->3(IDSEL)=12->15 */
+#endif
+
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SCSI_AHCI
+
+#ifdef CONFIG_SCSI_AHCI
+#define CONFIG_LIBATA
+#define CONFIG_SATA_ULI5288
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	4
+#define CONFIG_SYS_SCSI_MAX_LUN	1
+#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
+#define CONFIG_SYS_SCSI_MAXDEVICE	CONFIG_SYS_SCSI_MAX_DEVICE
+#endif
+
+#endif	/* CONFIG_PCI */
+
+/*
+ * BAT0		2G	Cacheable, non-guarded
+ * 0x0000_0000	2G	DDR
+ */
+#define CONFIG_SYS_DBAT0L	(BATL_PP_RW)
+#define CONFIG_SYS_IBAT0L	(BATL_PP_RW)
+
+/*
+ * BAT1		1G	Cache-inhibited, guarded
+ * 0x8000_0000	256M	PCI-1 Memory
+ * 0xa000_0000	256M	PCI-Express 1 Memory
+ * 0x9000_0000	256M	PCI-Express 2 Memory
+ */
+
+#define CONFIG_SYS_DBAT1L	(CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
+			| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT1U	(CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT1U	CONFIG_SYS_DBAT1U
+
+/*
+ * BAT2		16M	Cache-inhibited, guarded
+ * 0xe100_0000	1M	PCI-1 I/O
+ */
+
+#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
+			| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U	(CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U	CONFIG_SYS_DBAT2U
+
+/*
+ * BAT3		4M	Cache-inhibited, guarded
+ * 0xe000_0000	4M	CCSR
+ */
+
+#define CONFIG_SYS_DBAT3L	(CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \
+			| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT3U	(CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U	CONFIG_SYS_DBAT3U
+
+#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
+#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
+				       | BATL_PP_RW | BATL_CACHEINHIBIT \
+				       | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
+				       | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
+				       | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
+#endif
+
+/*
+ * BAT4		32M	Cache-inhibited, guarded
+ * 0xe200_0000	1M	PCI-Express 2 I/O
+ * 0xe300_0000	1M	PCI-Express 1 I/O
+ */
+
+#define CONFIG_SYS_DBAT4L	(CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
+			| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT4U	(CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT4U	CONFIG_SYS_DBAT4U
+
+
+/*
+ * BAT5		128K	Cacheable, non-guarded
+ * 0xe400_0000	128K	Init RAM for stack in the CPU DCache (no backing memory)
+ */
+#define CONFIG_SYS_DBAT5L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_DBAT5U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT5L	CONFIG_SYS_DBAT5L
+#define CONFIG_SYS_IBAT5U	CONFIG_SYS_DBAT5U
+
+/*
+ * BAT6		256M	Cache-inhibited, guarded
+ * 0xf000_0000	256M	FLASH
+ */
+#define CONFIG_SYS_DBAT6L	(CONFIG_SYS_FLASH_BASE	 | BATL_PP_RW | BATL_CACHEINHIBIT \
+			| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6U	(CONFIG_SYS_FLASH_BASE	 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6L	(CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U	CONFIG_SYS_DBAT6U
+
+/* Map the last 1M of flash where we're running from reset */
+#define CONFIG_SYS_DBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
+				 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6U_EARLY	(CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
+				 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U_EARLY	CONFIG_SYS_DBAT6U_EARLY
+
+/*
+ * BAT7		4M	Cache-inhibited, guarded
+ * 0xe800_0000	4M	PIXIS
+ */
+#define CONFIG_SYS_DBAT7L	(PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \
+			| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT7U	(PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT7L	(PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT7U	CONFIG_SYS_DBAT7U
+
+
+/*
+ * Environment
+ */
+#ifndef CONFIG_SYS_RAMBOOT
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SECT_SIZE	0x20000	/* 126k (one sector) for env */
+#define CONFIG_ENV_SIZE		0x2000
+#else
+#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
+#define CONFIG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+
+#if defined(CONFIG_SYS_RAMBOOT)
+#undef CONFIG_CMD_SAVEENV
+#endif
+
+#if defined(CONFIG_PCI)
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_SCSI
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_USB
+#endif
+
+
+#define CONFIG_WATCHDOG			/* watchdog enabled */
+#define CONFIG_SYS_WATCHDOG_FREQ	5000	/* Feed interval, 5s */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_CMDLINE_EDITING          /* Command-line editing */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_IPADDR		192.168.1.100
+
+#define CONFIG_HOSTNAME		unknown
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	8610hpcd/u-boot.bin
+
+#define CONFIG_SERVERIP		192.168.1.1
+#define CONFIG_GATEWAYIP	192.168.1.1
+#define CONFIG_NETMASK		255.255.255.0
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
+#undef	CONFIG_BOOTARGS		/* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE	115200
+
+#if defined(CONFIG_PCI1)
+#define PCI_ENV \
+ "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
+	"echo e;md ${a}e00 9\0" \
+ "pci1regs=setenv a e0008; run pcireg\0" \
+ "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
+	"pci d.w $b.0 56 1\0" \
+ "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \
+	"pci w.w $b.0 56 ffff\0"	\
+ "pci1err=setenv a e0008; run pcierr\0"	\
+ "pci1errc=setenv a e0008; run pcierrc\0"
+#else
+#define	PCI_ENV ""
+#endif
+
+#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2)
+#define PCIE_ENV \
+ "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
+	"echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
+ "pcie1regs=setenv a e000a; run pciereg\0"	\
+ "pcie2regs=setenv a e0009; run pciereg\0"	\
+ "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\
+	"pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;"	\
+	"pci d $b.0 130 1\0" \
+ "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\
+	"pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \
+	"pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0"		\
+ "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0"	\
+ "pcie1err=setenv a e000a; run pcieerr\0"	\
+ "pcie2err=setenv a e0009; run pcieerr\0"	\
+ "pcie1errc=setenv a e000a; run pcieerrc\0"	\
+ "pcie2errc=setenv a e0009; run pcieerrc\0"
+#else
+#define	PCIE_ENV ""
+#endif
+
+#define DMA_ENV \
+ "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\
+	"mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \
+ "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\
+	"mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \
+ "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\
+	"mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \
+ "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\
+	"mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0"
+
+#ifdef ENV_DEBUG
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+"netdev=eth0\0"							\
+"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
+"tftpflash=tftpboot $loadaddr $uboot; "				\
+	"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
+		" +$filesize; "	\
+	"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
+		" +$filesize; "	\
+	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
+		" $filesize; "	\
+	"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
+		" +$filesize; "	\
+	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
+		" $filesize\0"	\
+"consoledev=ttyS0\0"						\
+"ramdiskaddr=2000000\0"					\
+"ramdiskfile=8610hpcd/ramdisk.uboot\0"				\
+"fdtaddr=c00000\0"						\
+"fdtfile=8610hpcd/mpc8610_hpcd.dtb\0"				\
+"bdev=sda3\0"					\
+"en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
+"dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
+"maxcpus=1"	\
+"eoi=mw e00400b0 0\0"						\
+"iack=md e00400a0 1\0"						\
+"ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \
+	"md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \
+	"md ${a}f00 5\0" \
+"ddr1regs=setenv a e0002; run ddrreg\0" \
+"gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \
+	"md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \
+	"md ${a}e60 1; md ${a}ef0 1d\0" \
+"guregs=setenv a e00e0; run gureg\0" \
+"mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \
+"mcmregs=setenv a e0001; run mcmreg\0" \
+"diuregs=md e002c000 1d\0" \
+"dium=mw e002c01c\0" \
+"diuerr=md e002c014 1\0" \
+"pmregs=md e00e1000 2b\0" \
+"lawregs=md e0000c08 4b\0" \
+"lbcregs=md e0005000 36\0" \
+"dma0regs=md e0021100 12\0" \
+"dma1regs=md e0021180 12\0" \
+"dma2regs=md e0021200 12\0" \
+"dma3regs=md e0021280 12\0" \
+ PCI_ENV \
+ PCIE_ENV \
+ DMA_ENV
+#else
+#define CONFIG_EXTRA_ENV_SETTINGS				\
+	"netdev=eth0\0"						\
+	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
+	"consoledev=ttyS0\0"					\
+	"ramdiskaddr=2000000\0"					\
+	"ramdiskfile=8610hpcd/ramdisk.uboot\0"			\
+	"fdtaddr=c00000\0"					\
+	"fdtfile=8610hpcd/mpc8610_hpcd.dtb\0"			\
+	"bdev=sda3\0"
+#endif
+
+#define CONFIG_NFSBOOTCOMMAND					\
+ "setenv bootargs root=/dev/nfs rw "				\
+	"nfsroot=$serverip:$rootpath "				\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs;"		\
+ "tftp $loadaddr $bootfile;"					\
+ "tftp $fdtaddr $fdtfile;"					\
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw "				\
+	"console=$consoledev,$baudrate $othbootargs;"		\
+ "tftp $ramdiskaddr $ramdiskfile;"				\
+ "tftp $loadaddr $bootfile;"					\
+ "tftp $fdtaddr $fdtfile;"					\
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		\
+ "setenv bootargs root=/dev/$bdev rw "	\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+ "tftp $loadaddr $bootfile;"		\
+ "tftp $fdtaddr $fdtfile;"		\
+ "bootm $loadaddr - $fdtaddr"
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/MPC8641HPCN.h b/qemu/roms/u-boot/include/configs/MPC8641HPCN.h
new file mode 100644
index 000000000..a0d7d5262
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/MPC8641HPCN.h
@@ -0,0 +1,756 @@
+/*
+ * Copyright 2006, 2010-2011 Freescale Semiconductor.
+ *
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * MPC8641HPCN board configuration file
+ *
+ * Make sure you change the MAC address and other network params first,
+ * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* High Level Configuration Options */
+#define CONFIG_MPC8641		1	/* MPC8641 specific */
+#define CONFIG_MPC8641HPCN	1	/* MPC8641HPCN board specific */
+#define CONFIG_MP		1	/* support multiple processors */
+#define CONFIG_LINUX_RESET_VEC	0x100	/* Reset vector used by Linux */
+/*#define CONFIG_PHYS_64BIT	1*/	/* Place devices in 36-bit space */
+#define CONFIG_ADDR_MAP		1	/* Use addr map */
+
+/*
+ * default CCSRBAR is at 0xff700000
+ * assume U-Boot is less than 0.5MB
+ */
+#define	CONFIG_SYS_TEXT_BASE	0xeff00000
+
+#ifdef RUN_DIAG
+#define CONFIG_SYS_DIAG_ADDR	     CONFIG_SYS_FLASH_BASE
+#endif
+
+/*
+ * virtual address to be used for temporary mappings.  There
+ * should be 128k free at this VA.
+ */
+#define CONFIG_SYS_SCRATCH_VA	0xe0000000
+
+#define CONFIG_SYS_SRIO
+#define CONFIG_SRIO1			/* SRIO port 1 */
+
+#define CONFIG_PCI		1	/* Enable PCI/PCIE */
+#define CONFIG_PCIE1		1	/* PCIE controler 1 (ULI bridge) */
+#define CONFIG_PCIE2		1	/* PCIE controler 2 (slot) */
+#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
+#define CONFIG_FSL_LAW		1	/* Use common FSL law init code */
+
+#define CONFIG_TSEC_ENET		/* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAT_RW		1	/* Use common BAT rw code */
+#define CONFIG_HIGH_BATS	1	/* High BATs supported and enabled */
+#define CONFIG_SYS_NUM_ADDR_MAP 8	/* Number of addr map slots = 8 dbats */
+
+#define CONFIG_ALTIVEC		1
+
+/*
+ * L2CR setup -- make sure this is right for your board!
+ */
+#define CONFIG_SYS_L2
+#define L2_INIT		0
+#define L2_ENABLE	(L2CR_L2E)
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#ifndef __ASSEMBLY__
+extern unsigned long get_board_sys_clk(unsigned long dummy);
+#endif
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0)
+#endif
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+
+/*
+ * With the exception of PCI Memory and Rapid IO, most devices will simply
+ * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA
+ * when 36-bit is enabled.  When 36-bit is not enabled, these bits are 0.
+ */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f
+#else
+#define CONFIG_SYS_PHYS_ADDR_HIGH 0x00000000
+#endif
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
+#define CONFIG_SYS_CCSRBAR		0xffe00000	/* relocated CCSRBAR */
+#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
+
+/* Physical addresses */
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	CONFIG_SYS_PHYS_ADDR_HIGH
+#define CONFIG_SYS_CCSRBAR_PHYS \
+	PAIRED_PHYS_TO_PHYS(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
+			    CONFIG_SYS_CCSRBAR_PHYS_HIGH)
+
+#define CONFIG_HWCONFIG	/* use hwconfig to control memory interleaving */
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_FSL_DDR2
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
+#define CONFIG_DDR_SPD
+
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_MAX_DDR_BAT_SIZE	0x80000000	/* BAT mapping size */
+#define CONFIG_VERY_BIG_RAM
+
+#define CONFIG_NUM_DDR_CONTROLLERS	2
+#define CONFIG_DIMM_SLOTS_PER_CTLR	2
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+/*
+ * I2C addresses of SPD EEPROMs
+ */
+#define SPD_EEPROM_ADDRESS1	0x51	/* CTLR 0 DIMM 0 */
+#define SPD_EEPROM_ADDRESS2	0x52	/* CTLR 0 DIMM 1 */
+#define SPD_EEPROM_ADDRESS3	0x53	/* CTLR 1 DIMM 0 */
+#define SPD_EEPROM_ADDRESS4	0x54	/* CTLR 1 DIMM 1 */
+
+
+/*
+ * These are used when DDR doesn't use SPD.
+ */
+#define CONFIG_SYS_SDRAM_SIZE		256		/* DDR is 256MB */
+#define CONFIG_SYS_DDR_CS0_BNDS	0x0000000F
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80010102      /* Enable, no interleaving */
+#define CONFIG_SYS_DDR_TIMING_3	0x00000000
+#define CONFIG_SYS_DDR_TIMING_0	0x00260802
+#define CONFIG_SYS_DDR_TIMING_1	0x39357322
+#define CONFIG_SYS_DDR_TIMING_2	0x14904cc8
+#define CONFIG_SYS_DDR_MODE_1		0x00480432
+#define CONFIG_SYS_DDR_MODE_2		0x00000000
+#define CONFIG_SYS_DDR_INTERVAL	0x06090100
+#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
+#define CONFIG_SYS_DDR_CLK_CTRL	0x03800000
+#define CONFIG_SYS_DDR_OCD_CTRL	0x00000000
+#define CONFIG_SYS_DDR_OCD_STATUS	0x00000000
+#define CONFIG_SYS_DDR_CONTROL		0xe3008000	/* Type = DDR2 */
+#define CONFIG_SYS_DDR_CONTROL2	0x04400000
+
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+
+#define CONFIG_SYS_FLASH_BASE		0xef800000     /* start of FLASH 8M */
+#define CONFIG_SYS_FLASH_BASE_PHYS_LOW	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_FLASH_BASE_PHYS \
+	PAIRED_PHYS_TO_PHYS(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
+			    CONFIG_SYS_PHYS_ADDR_HIGH)
+
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
+
+#define CONFIG_SYS_BR0_PRELIM	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
+				 | 0x00001001)	/* port size 16bit */
+#define CONFIG_SYS_OR0_PRELIM	0xff806ff7	/* 8MB Boot Flash area*/
+
+#define CONFIG_SYS_BR2_PRELIM	(BR_PHYS_ADDR(CF_BASE_PHYS)		\
+				 | 0x00001001)	/* port size 16bit */
+#define CONFIG_SYS_OR2_PRELIM	0xffffeff7	/* 32k Compact Flash */
+
+#define CONFIG_SYS_BR3_PRELIM	(BR_PHYS_ADDR(PIXIS_BASE_PHYS)	\
+				 | 0x00000801) /* port size 8bit */
+#define CONFIG_SYS_OR3_PRELIM	0xffffeff7	/* 32k PIXIS area*/
+
+/*
+ * The LBC_BASE is the base of the region that contains the PIXIS and the CF.
+ * The PIXIS and CF by themselves aren't large enough to take up the 128k
+ * required for the smallest BAT mapping, so there's a 64k hole.
+ */
+#define CONFIG_SYS_LBC_BASE		0xffde0000
+#define CONFIG_SYS_LBC_BASE_PHYS_LOW	CONFIG_SYS_LBC_BASE
+
+#define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
+#define PIXIS_BASE		(CONFIG_SYS_LBC_BASE + 0x00010000)
+#define PIXIS_BASE_PHYS_LOW	(CONFIG_SYS_LBC_BASE_PHYS_LOW + 0x00010000)
+#define PIXIS_BASE_PHYS		PAIRED_PHYS_TO_PHYS(PIXIS_BASE_PHYS_LOW, \
+						    CONFIG_SYS_PHYS_ADDR_HIGH)
+#define PIXIS_SIZE		0x00008000	/* 32k */
+#define PIXIS_ID		0x0	/* Board ID at offset 0 */
+#define PIXIS_VER		0x1	/* Board version at offset 1 */
+#define PIXIS_PVER		0x2	/* PIXIS FPGA version at offset 2 */
+#define PIXIS_RST		0x4	/* PIXIS Reset Control register */
+#define PIXIS_AUX		0x6	/* PIXIS Auxiliary register; Scratch register */
+#define PIXIS_SPD		0x7	/* Register for SYSCLK speed */
+#define PIXIS_VCTL		0x10	/* VELA Control Register */
+#define PIXIS_VCFGEN0		0x12	/* VELA Config Enable 0 */
+#define PIXIS_VCFGEN1		0x13	/* VELA Config Enable 1 */
+#define PIXIS_VBOOT		0x16	/* VELA VBOOT Register */
+#define PIXIS_VBOOT_FMAP	0x80	/* VBOOT - CFG_FLASHMAP */
+#define PIXIS_VBOOT_FBANK	0x40	/* VBOOT - CFG_FLASHBANK */
+#define PIXIS_VSPEED0		0x17	/* VELA VSpeed 0 */
+#define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
+#define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
+#define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
+#define CONFIG_SYS_PIXIS_VBOOT_MASK	0x40	/* Reset altbank mask*/
+
+/* Compact flash shares a BAT with PIXIS; make sure they're contiguous */
+#define CF_BASE			(PIXIS_BASE + PIXIS_SIZE)
+#define CF_BASE_PHYS		(PIXIS_BASE_PHYS + PIXIS_SIZE)
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	128		/* sectors per device */
+
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000	/* early monitor loc */
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef	CONFIG_SYS_RAMBOOT
+#endif
+
+#if defined(CONFIG_SYS_RAMBOOT)
+#undef CONFIG_SPD_EEPROM
+#define CONFIG_SYS_SDRAM_SIZE	256
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#ifndef CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0x0fd00000	/* Initial RAM address */
+#else
+#define CONFIG_SYS_INIT_RAM_ADDR	0xf8400000	/* Initial RAM address */
+#endif
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	 /* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX     1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Pass open firmware flat tree to kernel
+ */
+#define CONFIG_OF_LIBFDT		1
+#define CONFIG_OF_BOARD_SETUP		1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3100
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
+
+/*
+ * RapidIO MMU
+ */
+#define CONFIG_SYS_SRIO1_MEM_BASE	0x80000000	/* base address */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_SRIO1_MEM_PHYS_LOW	0x00000000
+#define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH  0x0000000c
+#else
+#define CONFIG_SYS_SRIO1_MEM_PHYS_LOW	CONFIG_SYS_SRIO1_MEM_BASE
+#define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH  0x00000000
+#endif
+#define CONFIG_SYS_SRIO1_MEM_PHYS \
+	PAIRED_PHYS_TO_PHYS(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
+			    CONFIG_SYS_SRIO1_MEM_PHYS_HIGH)
+#define CONFIG_SYS_SRIO1_MEM_SIZE	0x20000000	/* 128M */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+
+#define CONFIG_SYS_PCIE1_NAME		"ULI"
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS_LOW	0x00000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH	0x0000000c
+#else
+#define CONFIG_SYS_PCIE1_MEM_BUS	CONFIG_SYS_PCIE1_MEM_VIRT
+#define CONFIG_SYS_PCIE1_MEM_PHYS_LOW	CONFIG_SYS_PCIE1_MEM_VIRT
+#define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH	0x00000000
+#endif
+#define CONFIG_SYS_PCIE1_MEM_PHYS \
+	PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
+			    CONFIG_SYS_PCIE1_MEM_PHYS_HIGH)
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc00000
+#define CONFIG_SYS_PCIE1_IO_PHYS_LOW	CONFIG_SYS_PCIE1_IO_VIRT
+#define CONFIG_SYS_PCIE1_IO_PHYS \
+	PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
+			    CONFIG_SYS_PHYS_ADDR_HIGH)
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64K */
+
+#ifdef CONFIG_PHYS_64BIT
+/*
+ * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT.
+ * This will increase the amount of PCI address space available for
+ * for mapping RAM.
+ */
+#define CONFIG_SYS_PCIE2_MEM_BUS	CONFIG_SYS_PCIE1_MEM_BUS
+#else
+#define CONFIG_SYS_PCIE2_MEM_BUS	(CONFIG_SYS_PCIE1_MEM_BUS \
+					 + CONFIG_SYS_PCIE1_MEM_SIZE)
+#endif
+#define CONFIG_SYS_PCIE2_MEM_VIRT 	(CONFIG_SYS_PCIE1_MEM_VIRT \
+					 + CONFIG_SYS_PCIE1_MEM_SIZE)
+#define CONFIG_SYS_PCIE2_MEM_PHYS_LOW	(CONFIG_SYS_PCIE1_MEM_PHYS_LOW \
+					 + CONFIG_SYS_PCIE1_MEM_SIZE)
+#define CONFIG_SYS_PCIE2_MEM_PHYS_HIGH	CONFIG_SYS_PCIE1_MEM_PHYS_HIGH
+#define CONFIG_SYS_PCIE2_MEM_PHYS	(CONFIG_SYS_PCIE1_MEM_PHYS \
+					 + CONFIG_SYS_PCIE1_MEM_SIZE)
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE2_IO_VIRT 	(CONFIG_SYS_PCIE1_IO_VIRT \
+					 + CONFIG_SYS_PCIE1_IO_SIZE)
+#define CONFIG_SYS_PCIE2_IO_PHYS_LOW	(CONFIG_SYS_PCIE1_IO_PHYS_LOW \
+					 + CONFIG_SYS_PCIE1_IO_SIZE)
+#define CONFIG_SYS_PCIE2_IO_PHYS	(CONFIG_SYS_PCIE1_IO_PHYS \
+					 + CONFIG_SYS_PCIE1_IO_SIZE)
+#define CONFIG_SYS_PCIE2_IO_SIZE	CONFIG_SYS_PCIE1_IO_SIZE
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+
+#undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
+
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+
+#define CONFIG_RTL8139
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+/************************************************************
+ * USB support
+ ************************************************************/
+#define CONFIG_PCI_OHCI			1
+#define CONFIG_USB_OHCI_NEW		1
+#define CONFIG_USB_KEYBOARD		1
+#define CONFIG_SYS_STDIO_DEREGISTER
+#define CONFIG_SYS_USB_EVENT_POLL		1
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"ohci_pci"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
+#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS	1
+
+/*PCIE video card used*/
+#define VIDEO_IO_OFFSET		CONFIG_SYS_PCIE2_IO_VIRT
+
+/*PCI video card used*/
+/*#define VIDEO_IO_OFFSET	CONFIG_SYS_PCIE1_IO_VIRT*/
+
+/* video */
+#define CONFIG_VIDEO
+
+#if defined(CONFIG_VIDEO)
+#define CONFIG_BIOSEMU
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_ATI_RADEON_FB
+#define CONFIG_VIDEO_LOGO
+/*#define CONFIG_CONSOLE_CURSOR*/
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT
+#endif
+
+#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SCSI_AHCI
+
+#ifdef CONFIG_SCSI_AHCI
+#define CONFIG_LIBATA
+#define CONFIG_SATA_ULI5288
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	4
+#define CONFIG_SYS_SCSI_MAX_LUN	1
+#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
+#define CONFIG_SYS_SCSI_MAXDEVICE	CONFIG_SYS_SCSI_MAX_DEVICE
+#endif
+
+#endif	/* CONFIG_PCI */
+
+#if defined(CONFIG_TSEC_ENET)
+
+#define CONFIG_MII		1	/* MII PHY management */
+
+#define CONFIG_TSEC1		1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define CONFIG_TSEC2		1
+#define CONFIG_TSEC2_NAME	"eTSEC2"
+#define CONFIG_TSEC3		1
+#define CONFIG_TSEC3_NAME	"eTSEC3"
+#define CONFIG_TSEC4		1
+#define CONFIG_TSEC4_NAME	"eTSEC4"
+
+#define TSEC1_PHY_ADDR		0
+#define TSEC2_PHY_ADDR		1
+#define TSEC3_PHY_ADDR		2
+#define TSEC4_PHY_ADDR		3
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC3_PHYIDX		0
+#define TSEC4_PHYIDX		0
+#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC4_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+
+#define CONFIG_ETHPRIME		"eTSEC1"
+
+#endif	/* CONFIG_TSEC_ENET */
+
+
+#ifdef CONFIG_PHYS_64BIT
+#define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8)
+#define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2)
+
+/* Put physical address into the BAT format */
+#define BAT_PHYS_ADDR(low, high) \
+	(low | PHYS_HIGH_TO_BXPN(high) | PHYS_HIGH_TO_BX(high))
+/* Convert high/low pairs to actual 64-bit value */
+#define PAIRED_PHYS_TO_PHYS(low, high) (low | ((u64)high << 32))
+#else
+/* 32-bit systems just ignore the "high" bits */
+#define BAT_PHYS_ADDR(low, high)        (low)
+#define PAIRED_PHYS_TO_PHYS(low, high)  (low)
+#endif
+
+/*
+ * BAT0		DDR
+ */
+#define CONFIG_SYS_DBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE)
+
+/*
+ * BAT1		LBC (PIXIS/CF)
+ */
+#define CONFIG_SYS_DBAT1L	(BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
+					       CONFIG_SYS_PHYS_ADDR_HIGH) \
+				 | BATL_PP_RW | BATL_CACHEINHIBIT | \
+				 BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT1U	(CONFIG_SYS_LBC_BASE | BATU_BL_128K \
+				 | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L	(BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
+					       CONFIG_SYS_PHYS_ADDR_HIGH) \
+				 | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U	CONFIG_SYS_DBAT1U
+
+/* if CONFIG_PCI:
+ * BAT2		PCIE1 and PCIE1 MEM
+ * if CONFIG_RIO
+ * BAT2		Rapidio Memory
+ */
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_SYS_DBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
+					       CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
+				 | BATL_PP_RW | BATL_CACHEINHIBIT \
+				 | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U	(CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \
+				 | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
+					       CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
+				 | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U	CONFIG_SYS_DBAT2U
+#else /* CONFIG_RIO */
+#define CONFIG_SYS_DBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
+					       CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
+				 | BATL_PP_RW | BATL_CACHEINHIBIT | \
+				 BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U	(CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \
+				 | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L	(BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
+					       CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
+				 | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U	CONFIG_SYS_DBAT2U
+#endif
+
+/*
+ * BAT3		CCSR Space
+ */
+#define CONFIG_SYS_DBAT3L	(BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
+					       CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
+				 | BATL_PP_RW | BATL_CACHEINHIBIT \
+				 | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT3U	(CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \
+				 | BATU_VP)
+#define CONFIG_SYS_IBAT3L	(BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
+					       CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
+				 | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U	CONFIG_SYS_DBAT3U
+
+#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
+#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
+				       | BATL_PP_RW | BATL_CACHEINHIBIT \
+				       | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
+				       | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
+				       | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
+#endif
+
+/*
+ * BAT4		PCIE1_IO and PCIE2_IO
+ */
+#define CONFIG_SYS_DBAT4L	(BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
+					       CONFIG_SYS_PHYS_ADDR_HIGH) \
+				 | BATL_PP_RW | BATL_CACHEINHIBIT \
+				 | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT4U	(CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \
+				 | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT4L	(BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
+					       CONFIG_SYS_PHYS_ADDR_HIGH) \
+				 | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT4U	CONFIG_SYS_DBAT4U
+
+/*
+ * BAT5		Init RAM for stack in the CPU DCache (no backing memory)
+ */
+#define CONFIG_SYS_DBAT5L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_DBAT5U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT5L	CONFIG_SYS_DBAT5L
+#define CONFIG_SYS_IBAT5U	CONFIG_SYS_DBAT5U
+
+/*
+ * BAT6		FLASH
+ */
+#define CONFIG_SYS_DBAT6L	(BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
+					       CONFIG_SYS_PHYS_ADDR_HIGH) \
+				 | BATL_PP_RW | BATL_CACHEINHIBIT \
+				 | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6U	(CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \
+				 | BATU_VP)
+#define CONFIG_SYS_IBAT6L	(BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
+					       CONFIG_SYS_PHYS_ADDR_HIGH) \
+				 | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U	CONFIG_SYS_DBAT6U
+
+/* Map the last 1M of flash where we're running from reset */
+#define CONFIG_SYS_DBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
+				 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6U_EARLY	(CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
+				 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U_EARLY	CONFIG_SYS_DBAT6U_EARLY
+
+/*
+ * BAT7		FREE - used later for tmp mappings
+ */
+#define CONFIG_SYS_DBAT7L 0x00000000
+#define CONFIG_SYS_DBAT7U 0x00000000
+#define CONFIG_SYS_IBAT7L 0x00000000
+#define CONFIG_SYS_IBAT7U 0x00000000
+
+/*
+ * Environment
+ */
+#ifndef CONFIG_SYS_RAMBOOT
+    #define CONFIG_ENV_IS_IN_FLASH	1
+    #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x60000)
+    #define CONFIG_ENV_SECT_SIZE		0x10000	/* 64K(one sector) for env */
+#else
+    #define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
+    #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
+#endif
+#define CONFIG_ENV_SIZE		0x2000
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_REGINFO
+
+#if defined(CONFIG_SYS_RAMBOOT)
+    #undef CONFIG_CMD_SAVEENV
+#endif
+
+#if defined(CONFIG_PCI)
+    #define CONFIG_CMD_PCI
+    #define CONFIG_CMD_SCSI
+    #define CONFIG_CMD_EXT2
+    #define CONFIG_CMD_USB
+#endif
+
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_CMDLINE_EDITING		/* Command-line editing */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+#if defined(CONFIG_CMD_KGDB)
+    #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+    #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+
+#if defined(CONFIG_CMD_KGDB)
+    #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+/* The mac addresses for all ethernet interface */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_ETHADDR	 00:E0:0C:00:00:01
+#define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
+#define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
+#define CONFIG_ETH3ADDR  00:E0:0C:00:03:FD
+#endif
+
+#define CONFIG_HAS_ETH0		1
+#define CONFIG_HAS_ETH1		1
+#define CONFIG_HAS_ETH2		1
+#define CONFIG_HAS_ETH3		1
+
+#define CONFIG_IPADDR		192.168.1.100
+
+#define CONFIG_HOSTNAME		unknown
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */
+
+#define CONFIG_SERVERIP		192.168.1.1
+#define CONFIG_GATEWAYIP	192.168.1.1
+#define CONFIG_NETMASK		255.255.255.0
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
+#undef	CONFIG_BOOTARGS		/* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE	115200
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
+	"tftpflash=tftpboot $loadaddr $uboot; "				\
+		"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
+			" +$filesize; "	\
+		"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
+			" +$filesize; "	\
+		"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
+			" $filesize; "	\
+		"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
+			" +$filesize; "	\
+		"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
+			" $filesize\0"	\
+	"consoledev=ttyS0\0"						\
+	"ramdiskaddr=2000000\0"						\
+	"ramdiskfile=your.ramdisk.u-boot\0"				\
+	"fdtaddr=c00000\0"						\
+	"fdtfile=mpc8641_hpcn.dtb\0"					\
+	"en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0"			\
+	"dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \
+	"maxcpus=2"
+
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv bootargs root=/dev/nfs rw "				\
+	      "nfsroot=$serverip:$rootpath "				\
+	      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	      "console=$consoledev,$baudrate $othbootargs;"		\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+	"setenv bootargs root=/dev/ram rw "				\
+	      "console=$consoledev,$baudrate $othbootargs;"		\
+	"tftp $ramdiskaddr $ramdiskfile;"				\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/MPC86xADS.h b/qemu/roms/u-boot/include/configs/MPC86xADS.h
new file mode 100644
index 000000000..beada7ee2
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/MPC86xADS.h
@@ -0,0 +1,51 @@
+/*
+  * A collection of structures, addresses, and values associated with
+  * the Motorola MPC8xxADS board.  Copied from the FADS config.
+  *
+  * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
+  *
+  * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com
+  *
+  * Values common to all FADS family boards are in board/fads/fads.h
+  */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+/* board type */
+#define CONFIG_MPC86xADS        1       /* new ADS */
+#define CONFIG_FADS		1       /* We are FADS compatible (more or less) */
+
+/* CPU type - pick one of these */
+#define CONFIG_MPC866T		1
+#undef CONFIG_MPC866P
+#undef CONFIG_MPC859T
+#undef CONFIG_MPC859DSL
+#undef CONFIG_MPC852T
+
+#define	CONFIG_SYS_TEXT_BASE	0xFE000000
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		38400
+
+#define CONFIG_8xx_OSCLK		10000000 /* 10MHz oscillator on EXTCLK  */
+#define CONFIG_8xx_CPUCLK_DEFAULT	50000000
+#define CONFIG_SYS_8xx_CPUCLK_MIN		40000000
+#define CONFIG_SYS_8xx_CPUCLK_MAX		80000000
+
+#define CONFIG_DRAM_50MHZ       1
+#define CONFIG_SDRAM_50MHZ      1
+
+#include "../../board/fads/fads.h"
+
+#define CONFIG_SYS_OR5_PRELIM		0xFFFF8110	/* 64Kbyte address space */
+#define CONFIG_SYS_BR5_PRELIM		(CONFIG_SYS_PHYDEV_ADDR | BR_PS_8 | BR_V)
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/MPC885ADS.h b/qemu/roms/u-boot/include/configs/MPC885ADS.h
new file mode 100644
index 000000000..eeb2355b9
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/MPC885ADS.h
@@ -0,0 +1,39 @@
+/*
+ * A collection of structures, addresses, and values associated with
+ * the Motorola MPC885ADS board. Values common to all FADS family boards
+ * are in board/fads/fads.h
+ *
+ * Copyright (C) 2003-2004 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MPC885ADS	1	/* MPC885ADS board */
+#define CONFIG_FADS		1	/* We are FADS compatible (more or less) */
+
+#define CONFIG_MPC885		1	/* MPC885 CPU (Duet family) */
+
+#define	CONFIG_SYS_TEXT_BASE	0xFE000000
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1 */
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		38400
+
+#define CONFIG_8xx_OSCLK		10000000 /* 10 MHz oscillator on EXTCLK  */
+#define CONFIG_8xx_CPUCLK_DEFAULT	50000000
+#define CONFIG_SYS_8xx_CPUCLK_MIN		40000000
+#define CONFIG_SYS_8xx_CPUCLK_MAX		133000000
+
+#define CONFIG_SDRAM_50MHZ      1
+
+#include "../../board/fads/fads.h"
+
+#define CONFIG_SYS_OR5_PRELIM		0xFFFF8110	/* 64Kbyte address space */
+#define CONFIG_SYS_BR5_PRELIM		(CONFIG_SYS_PHYDEV_ADDR | BR_PS_8 | BR_V)
+
+#define CONFIG_HAS_ETH1
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/MUSENKI.h b/qemu/roms/u-boot/include/configs/MUSENKI.h
new file mode 100644
index 000000000..c5c929002
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/MUSENKI.h
@@ -0,0 +1,275 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ *
+ * Configuration settings for the MUSENKI board.
+ *
+ */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC8245		1
+#define CONFIG_MUSENKI		1
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
+
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		9600
+
+#define CONFIG_BOOTDELAY	5
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#undef CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+
+/* Print Buffer Size
+ */
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	8		/* Max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_LOAD_ADDR	0x00100000	/* Default load address		*/
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_PCI			/* include pci support          */
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#undef CONFIG_PCI_PNP
+
+
+#define CONFIG_TULIP
+
+#define PCI_ENET0_IOADDR		0x80000000
+#define PCI_ENET0_MEMADDR		0x80000000
+#define PCI_ENET1_IOADDR		0x81000000
+#define PCI_ENET1_MEMADDR		0x81000000
+
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE	    0x00000000
+
+#define CONFIG_SYS_FLASH_BASE0_PRELIM      0xFF800000      /* FLASH bank on RCS#0 */
+#define CONFIG_SYS_FLASH_BASE1_PRELIM      0xFF000000      /* FLASH bank on RCS#1 */
+#define CONFIG_SYS_FLASH_BASE  CONFIG_SYS_FLASH_BASE0_PRELIM
+
+/* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the
+ * reset vector is actually located at FFB00100, but the 8245
+ * takes care of us.
+ */
+#define CONFIG_SYS_RESET_ADDRESS   0xFFF00100
+
+#define CONFIG_SYS_EUMB_ADDR	    0xFC000000
+
+#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN	    (128 << 10) /* Reserve 128 kB for malloc()	*/
+
+#define CONFIG_SYS_MEMTEST_START   0x00004000	/* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END	    0x02000000	/* 0 ... 32 MB in DRAM		*/
+
+	/* Maximum amount of RAM.
+	 */
+#define CONFIG_SYS_MAX_RAM_SIZE    0x08000000	/* 0 .. 128 MB of (S)DRAM */
+
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+#undef CONFIG_SYS_RAMBOOT
+#else
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_EUMB_ADDR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_EUMB_ADDR + 0x4600)
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area
+ */
+
+/* #define CONFIG_SYS_MONITOR_BASE        CONFIG_SYS_TEXT_BASE */
+#define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE      0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ * For the detail description refer to the MPC8240 user's manual.
+ */
+
+#define CONFIG_SYS_CLK_FREQ  33333333	/* external frequency to pll */
+
+	/* Bit-field values for MCCR1.
+	 */
+#define CONFIG_SYS_ROMNAL	    7
+#define CONFIG_SYS_ROMFAL	    11
+#define CONFIG_SYS_DBUS_SIZE       0x3
+
+	/* Bit-field values for MCCR2.
+	 */
+#define CONFIG_SYS_TSWAIT	    0x5		    /* Transaction Start Wait States timer */
+#define CONFIG_SYS_REFINT	    0x400	    /* Refresh interval	FIXME: was 0t430		*/
+
+	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
+	 */
+#define CONFIG_SYS_BSTOPRE	    121
+
+	/* Bit-field values for MCCR3.
+	 */
+#define CONFIG_SYS_REFREC	    8	    /* Refresh to activate interval */
+
+	/* Bit-field values for MCCR4.
+	 */
+#define CONFIG_SYS_PRETOACT	    3	    /* Precharge to activate interval FIXME: was 2	*/
+#define CONFIG_SYS_ACTTOPRE	    5	    /* Activate to Precharge interval FIXME: was 5	*/
+#define CONFIG_SYS_ACTORW	    3		/* FIXME was 2 */
+#define CONFIG_SYS_SDMODE_CAS_LAT  3	    /* SDMODE CAS latancy */
+#define CONFIG_SYS_SDMODE_WRAP	    0	    /* SDMODE wrap type	*/
+#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
+#define CONFIG_SYS_EXTROM	    1
+#define CONFIG_SYS_REGDIMM	    0
+
+#define CONFIG_SYS_PGMAX           0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/
+
+#define CONFIG_SYS_SDRAM_DSCD	0x20	/* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */
+
+/* Memory bank settings.
+ * Only bits 20-29 are actually used from these vales to set the
+ * start/end addresses. The upper two bits will always be 0, and the lower
+ * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
+ * address. Refer to the MPC8240 book.
+ */
+
+#define CONFIG_SYS_BANK0_START	    0x00000000
+#define CONFIG_SYS_BANK0_END	    (CONFIG_SYS_MAX_RAM_SIZE - 1)
+#define CONFIG_SYS_BANK0_ENABLE    1
+#define CONFIG_SYS_BANK1_START	    0x3ff00000
+#define CONFIG_SYS_BANK1_END	    0x3fffffff
+#define CONFIG_SYS_BANK1_ENABLE    0
+#define CONFIG_SYS_BANK2_START	    0x3ff00000
+#define CONFIG_SYS_BANK2_END	    0x3fffffff
+#define CONFIG_SYS_BANK2_ENABLE    0
+#define CONFIG_SYS_BANK3_START	    0x3ff00000
+#define CONFIG_SYS_BANK3_END	    0x3fffffff
+#define CONFIG_SYS_BANK3_ENABLE    0
+#define CONFIG_SYS_BANK4_START	    0x3ff00000
+#define CONFIG_SYS_BANK4_END	    0x3fffffff
+#define CONFIG_SYS_BANK4_ENABLE    0
+#define CONFIG_SYS_BANK5_START	    0x3ff00000
+#define CONFIG_SYS_BANK5_END	    0x3fffffff
+#define CONFIG_SYS_BANK5_ENABLE    0
+#define CONFIG_SYS_BANK6_START	    0x3ff00000
+#define CONFIG_SYS_BANK6_END	    0x3fffffff
+#define CONFIG_SYS_BANK6_ENABLE    0
+#define CONFIG_SYS_BANK7_START	    0x3ff00000
+#define CONFIG_SYS_BANK7_END	    0x3fffffff
+#define CONFIG_SYS_BANK7_ENABLE    0
+
+#define CONFIG_SYS_ODCR	    0xff
+
+#define CONFIG_SYS_IBAT0L  (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U  (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_DBAT0L  CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U  CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L  CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U  CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L  CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U  CONFIG_SYS_IBAT3U
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* Max number of flash banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	64	/* Max number of sectors per flash	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
+
+
+	/* Warining: environment is not EMBEDDED in the U-Boot code.
+	 * It's stored in flash separately.
+	 */
+#define CONFIG_ENV_IS_IN_FLASH	    1
+#define CONFIG_ENV_ADDR		0xFFFF0000
+#define CONFIG_ENV_SIZE		0x00010000 /* Size of the Environment		*/
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* Size of the Environment Sector	*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	32
+#if defined(CONFIG_CMD_KGDB)
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/MVBC_P.h b/qemu/roms/u-boot/include/configs/MVBC_P.h
new file mode 100644
index 000000000..036396c78
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/MVBC_P.h
@@ -0,0 +1,299 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004-2008
+ * Matrix-Vision GmbH, andre.schwarz@matrix-vision.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <version.h>
+
+#define CONFIG_MPC5200 	1
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xFF800000
+#endif
+
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000
+
+#define CONFIG_MISC_INIT_R	1
+
+#define CONFIG_SYS_CACHELINE_SIZE	32
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CACHELINE_SHIFT	5
+#endif
+
+#define CONFIG_PSC_CONSOLE	1
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200, 230400}
+
+#define CONFIG_PCI		1
+#define CONFIG_PCI_PNP		1
+#undef	CONFIG_PCI_SCAN_SHOW
+#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1
+
+#define CONFIG_PCI_MEM_BUS	0x40000000
+#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE	0x10000000
+
+#define CONFIG_PCI_IO_BUS	0x50000000
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0x01000000
+
+#define CONFIG_SYS_XLB_PIPELINING	1
+#define CONFIG_HIGH_BATS	1
+
+#define MV_CI			mvBlueCOUGAR-P
+#define MV_VCI			mvBlueCOUGAR-P
+#define MV_FPGA_DATA		0xff860000
+#define MV_FPGA_SIZE		0
+#define MV_KERNEL_ADDR		0xffd00000
+#define MV_INITRD_ADDR		0xff900000
+#define MV_INITRD_LENGTH	0x00400000
+#define MV_SCRATCH_ADDR		0x00000000
+#define MV_SCRATCH_LENGTH	MV_INITRD_LENGTH
+#define MV_SCRIPT_ADDR		0xff840000
+#define MV_SCRIPT_ADDR2		0xff850000
+#define MV_DTB_ADDR		0xfffc0000
+
+#define CONFIG_SHOW_BOOT_PROGRESS 1
+
+#define MV_KERNEL_ADDR_RAM	0x00100000
+#define MV_DTB_ADDR_RAM		0x00600000
+#define MV_INITRD_ADDR_RAM	0x01000000
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+#define OF_CPU			"PowerPC,5200@0"
+#define OF_SOC			"soc5200@f0000000"
+#define OF_TBCLK		(bd->bi_busfreq / 4)
+#define MV_DTB_NAME		mvbc-p.dtb
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+/*
+ * Supported commands
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_FPGA
+#define CONFIG_CMD_I2C
+
+#undef CONFIG_WATCHDOG
+
+#define CONFIG_BOOTP_VENDOREX
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_NTPSERVER
+#define CONFIG_BOOTP_RANDOM_DELAY
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_LIB_RAND
+
+/*
+ * Autoboot
+ */
+#define CONFIG_BOOTDELAY		2
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_STOP_STR 	"s"
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define CONFIG_RESET_TO_RETRY		1000
+
+#define CONFIG_BOOTCOMMAND	"if imi ${script_addr}; \
+					then source ${script_addr};	\
+					else source ${script_addr2};	\
+				fi;"
+
+#define CONFIG_BOOTARGS		"root=/dev/ram ro rootfstype=squashfs"
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_EXTRA_ENV_SETTINGS				\
+	"console_nr=0\0"					\
+	"console=yes\0"						\
+	"stdin=serial\0"					\
+	"stdout=serial\0"					\
+	"stderr=serial\0"					\
+	"fpga=0\0"						\
+	"fpgadata=" __stringify(MV_FPGA_DATA) "\0"			\
+	"fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0"		\
+	"script_addr=" __stringify(MV_SCRIPT_ADDR) "\0"		\
+	"script_addr2=" __stringify(MV_SCRIPT_ADDR2) "\0"		\
+	"mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0"		\
+	"mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0"	\
+	"mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0"		\
+	"mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0"	\
+	"mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0"	\
+	"mv_dtb_addr=" __stringify(MV_DTB_ADDR) "\0"			\
+	"mv_dtb_addr_ram=" __stringify(MV_DTB_ADDR_RAM) "\0"		\
+	"dtb_name=" __stringify(MV_DTB_NAME) "\0"			\
+	"mv_scratch_addr=" __stringify(MV_SCRATCH_ADDR) "\0"		\
+	"mv_scratch_length=" __stringify(MV_SCRATCH_LENGTH) "\0"	\
+	"mv_version=" U_BOOT_VERSION "\0"			\
+	"dhcp_client_id=" __stringify(MV_CI) "\0"			\
+	"dhcp_vendor-class-identifier=" __stringify(MV_VCI) "\0"	\
+	"netretry=no\0"						\
+	"use_static_ipaddr=no\0"				\
+	"static_ipaddr=192.168.90.10\0"				\
+	"static_netmask=255.255.255.0\0"			\
+	"static_gateway=0.0.0.0\0"				\
+	"initrd_name=uInitrd.mvbc-p-rfs\0"			\
+	"zcip=no\0"						\
+	"netboot=yes\0"						\
+	"mvtest=Ff\0"						\
+	"tried_bootfromflash=no\0"				\
+	"tried_bootfromnet=no\0"				\
+	"use_dhcp=yes\0"					\
+	"gev_start=yes\0"					\
+	"mvbcdma_debug=0\0"					\
+	"mvbcia_debug=0\0"					\
+	"propdev_debug=0\0"					\
+	"gevss_debug=0\0"					\
+	"watchdog=1\0"						\
+	"sensor_cnt=1\0"					\
+	""
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK
+#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
+
+/*
+ * Flash configuration
+ */
+#undef 	CONFIG_FLASH_16BIT
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	50000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	1000
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	256
+
+#define CONFIG_SYS_LOWBOOT
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_FLASH_SIZE		0x00800000
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+#undef	CONFIG_SYS_FLASH_PROTECTION
+
+#define CONFIG_ENV_ADDR		0xFFFE0000
+#define CONFIG_ENV_SIZE		0x10000
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+
+/*
+ * Memory map
+ */
+#define CONFIG_SYS_MBAR		0xF0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
+
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT		1
+#endif
+
+/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
+#define CONFIG_SYS_MONITOR_LEN		(512 << 10)
+#define CONFIG_SYS_MALLOC_LEN		(512 << 10)
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1
+#define CONFIG_SYS_I2C_MODULE	1
+#define CONFIG_SYS_I2C_SPEED	86000
+#define CONFIG_SYS_I2C_SLAVE	0x7F
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_NET_RETRY_COUNT 5
+
+#define CONFIG_E1000
+#define CONFIG_E1000_FALLBACK_MAC	{ 0xb6, 0xb4, 0x45, 0xeb, 0xfb, 0xc0 }
+#undef CONFIG_MPC5xxx_FEC
+#undef CONFIG_PHY_ADDR
+#define CONFIG_NETDEV		eth0
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_CMDLINE_EDITING
+#undef 	CONFIG_SYS_LONGHELP
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE		1024
+#else
+#define CONFIG_SYS_CBSIZE		256
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START	0x00800000
+#define CONFIG_SYS_MEMTEST_END		0x02f00000
+
+/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x02000000
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR 	0x00200000
+
+/*
+ * Various low-level settings
+ */
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x20000004
+
+#define CONFIG_SYS_HID0_INIT		(HID0_ICE | HID0_ICFI)
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
+
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_CFG		0x00047800
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
+
+#define CONFIG_SYS_CS_BURST		0x000000f0
+#define CONFIG_SYS_CS_DEADCYCLE	0x33333303
+
+#define CONFIG_SYS_RESET_ADDRESS	0x00000100
+
+#undef FPGA_DEBUG
+#undef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#define CONFIG_FPGA
+#define CONFIG_FPGA_ALTERA	1
+#define CONFIG_FPGA_CYCLON2	1
+#define CONFIG_FPGA_COUNT	1
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/MVBLM7.h b/qemu/roms/u-boot/include/configs/MVBLM7.h
new file mode 100644
index 000000000..27c2fa011
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/MVBLM7.h
@@ -0,0 +1,490 @@
+/*
+ * Copyright (C) Matrix Vision GmbH 2008
+ *
+ * Matrix Vision mvBlueLYNX-M7 configuration file
+ * based on Freescale's MPC8349ITX.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <version.h>
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300	1
+#define CONFIG_MPC834x	1
+#define CONFIG_MPC8343	1
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
+
+#define CONFIG_SYS_IMMR		0xE0000000
+
+#define CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_PCI_SKIP_HOST_BRIDGE
+#define CONFIG_TSEC_ENET
+#define CONFIG_MPC8XXX_SPI
+#define CONFIG_HARD_SPI
+#define MVBLM7_MMC_CS   0x04000000
+#define CONFIG_MISC_INIT_R
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	100000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	100000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+
+/*
+ * DDR Setup
+ */
+#undef	CONFIG_SPD_EEPROM
+
+#define CONFIG_SYS_DDR_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_83XX_DDR_USES_CS0	1
+#define CONFIG_SYS_MEMTEST_START	(60<<20)
+#define CONFIG_SYS_MEMTEST_END		(70<<20)
+#define CONFIG_VERY_BIG_RAM
+
+#define CONFIG_SYS_DDRCDR		(DDRCDR_PZ_HIZ \
+					| DDRCDR_NZ_HIZ \
+					| DDRCDR_Q_DRN)
+					/* 0x22000001 */
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+
+#define CONFIG_SYS_DDR_SIZE		512
+
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80014202
+
+#define CONFIG_SYS_DDR_CS0_BNDS		0x0000003f
+
+#define CONFIG_SYS_DDR_TIMING_0		0x00260802
+#define CONFIG_SYS_DDR_TIMING_1		0x3837c322
+#define CONFIG_SYS_DDR_TIMING_2		0x0f9848c6
+#define CONFIG_SYS_DDR_TIMING_3		0x00000000
+
+#define CONFIG_SYS_DDR_SDRAM_CFG	0x43080008
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
+#define CONFIG_SYS_DDR_INTERVAL		0x02000100
+
+#define CONFIG_SYS_DDR_MODE		0x04040242
+#define CONFIG_SYS_DDR_MODE2		0x00800000
+
+/* Flash */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+
+#define CONFIG_SYS_FLASH_BASE		0xFF800000
+#define CONFIG_SYS_FLASH_SIZE		8
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	256
+
+#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE \
+				| BR_PS_16 \
+				| BR_MS_GPCM \
+				| BR_V)
+#define CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+				| OR_UPM_XAM \
+				| OR_GPCM_CSNT \
+				| OR_GPCM_ACS_DIV2 \
+				| OR_GPCM_XACS \
+				| OR_GPCM_SCY_15 \
+				| OR_GPCM_TRLX_SET \
+				| OR_GPCM_EHTR_SET \
+				| OR_GPCM_EAD)
+#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_8MB)
+
+/*
+ * U-Boot memory configuration
+ */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#undef	CONFIG_SYS_RAMBOOT
+
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM*/
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(512 * 1024)
+
+/*
+ * Local Bus LCRR and LBCR regs
+ *  LCRR:  DLL bypass, Clock divider is 4
+ * External Local Bus rate is
+ *  CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
+ */
+#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_4
+#define CONFIG_SYS_LBC_LBCR	0x00000000
+
+/* LB sdram refresh timer, about 6us */
+#define CONFIG_SYS_LBC_LSRT	0x32000000
+/* LB refresh timer prescal, 266MHz/32*/
+#define CONFIG_SYS_LBC_MRTPR	0x20000000
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_CONSOLE		ttyS0
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT		1
+#define CONFIG_OF_BOARD_SETUP		1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+#define MV_DTB_NAME	"mvblm7.dtb"
+
+/*
+ * PCI
+ */
+#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000
+#define CONFIG_SYS_PCI1_MMIO_BASE	\
+			(CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
+#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000
+#define CONFIG_SYS_PCI1_IO_BASE	0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS	0xE2000000
+#define CONFIG_SYS_PCI1_IO_SIZE	0x01000000
+
+#define CONFIG_NET_RETRY_COUNT	3
+
+#define CONFIG_PCI_66M
+#define CONFIG_83XX_CLKIN	66666667
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+
+/* TSEC */
+#define CONFIG_GMII
+#define CONFIG_SYS_VSC8601_SKEWFIX
+#define	CONFIG_SYS_VSC8601_SKEW_TX	3
+#define	CONFIG_SYS_VSC8601_SKEW_RX	3
+
+#define CONFIG_TSEC1
+#define CONFIG_TSEC2
+
+#define CONFIG_HAS_ETH0
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_FEC1_PHY_NORXERR
+#define CONFIG_SYS_TSEC1_OFFSET	0x24000
+#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
+#define TSEC1_PHY_ADDR		0x10
+#define TSEC1_PHYIDX		0
+#define TSEC1_FLAGS		(TSEC_GIGABIT|TSEC_REDUCED)
+
+#define CONFIG_HAS_ETH1
+#define CONFIG_TSEC2_NAME	"TSEC1"
+#define CONFIG_FEC2_PHY_NORXERR
+#define CONFIG_SYS_TSEC2_OFFSET	0x25000
+#define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
+#define TSEC2_PHY_ADDR		0x11
+#define TSEC2_PHYIDX		0
+#define TSEC2_FLAGS		(TSEC_GIGABIT|TSEC_REDUCED)
+
+#define CONFIG_ETHPRIME		"TSEC0"
+
+#define CONFIG_BOOTP_VENDOREX
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_NTPSERVER
+#define CONFIG_BOOTP_RANDOM_DELAY
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_LIB_RAND
+
+/* USB */
+#define CONFIG_SYS_USB_HOST
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_HAS_FSL_DR_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+
+/*
+ * Environment
+ */
+#undef  CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_ADDR		0xFF800000
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x2000
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+
+#define CONFIG_LOADS_ECHO
+#define CONFIG_SYS_LOADS_BAUD_CHANGE
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_FPGA
+#define CONFIG_CMD_USB
+#define CONFIG_DOS_PARTITION
+
+#undef CONFIG_WATCHDOG
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE	/* add autocompletion support   */
+#define CONFIG_SYS_HUSH_PARSER
+
+/* default load address */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR	0x200000
+
+#define CONFIG_SYS_PROMPT	"mvBL-M7> "
+#define CONFIG_SYS_CBSIZE	256
+
+#define CONFIG_SYS_PBSIZE	\
+			(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	16
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+				/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)
+
+#define CONFIG_SYS_HRCW_LOW	0x0
+#define CONFIG_SYS_HRCW_HIGH	0x0
+
+/*
+ * System performance
+ */
+#define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
+#define CONFIG_SYS_ACR_RPTCNT	3	/* Arbiter repeat count (0-7) */
+#define CONFIG_SYS_SPCR_TSEC1EP	3	/* TSEC1 emergency priority (0-3) */
+#define CONFIG_SYS_SPCR_TSEC2EP	3	/* TSEC2 emergency priority (0-3) */
+
+/* clocking */
+#define CONFIG_SYS_SCCR_ENCCM		0
+#define CONFIG_SYS_SCCR_USBMPHCM	0
+#define	CONFIG_SYS_SCCR_USBDRCM	2
+#define CONFIG_SYS_SCCR_TSEC1CM	1
+#define CONFIG_SYS_SCCR_TSEC2CM	1
+
+#define CONFIG_SYS_SICRH	0x1fef0003
+#define CONFIG_SYS_SICRL	(SICRL_LDP_A | SICRL_USB1 | SICRL_USB0)
+
+#define CONFIG_SYS_HID0_INIT	0x000000000
+#define CONFIG_SYS_HID0_FINAL	(CONFIG_SYS_HID0_INIT | \
+				 HID0_ENABLE_INSTRUCTION_CACHE)
+
+#define CONFIG_SYS_HID2	HID2_HBE
+#define CONFIG_HIGH_BATS	1
+
+/* DDR  */
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE \
+				| BATL_PP_RW \
+				| BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+
+/* PCI  */
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_BASE \
+				| BATL_PP_RW \
+				| BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_PCI1_MEM_BASE \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_MMIO_BASE \
+				| BATL_PP_RW \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PCI1_MMIO_BASE \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+
+/* no PCI2 */
+#define CONFIG_SYS_IBAT3L	0
+#define CONFIG_SYS_IBAT3U	0
+#define CONFIG_SYS_IBAT4L	0
+#define CONFIG_SYS_IBAT4U	0
+
+/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
+#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_IMMR \
+				| BATL_PP_RW \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_IMMR \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+
+/* stack in DCACHE 0xFDF00000 & FLASH @ 0xFF800000 */
+#define CONFIG_SYS_IBAT6L	(0xF0000000 \
+				| BATL_PP_RW \
+				| BATL_MEMCOHERENCE \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT6U	(0xF0000000 \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_IBAT7L	0
+#define CONFIG_SYS_IBAT7U	0
+
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
+#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
+#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
+#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
+#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_NETDEV		eth0
+
+/* Default path and filenames */
+#define CONFIG_BOOTDELAY		5
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_STOP_STR	"s"
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define CONFIG_RESET_TO_RETRY		1000
+
+#define MV_CI			"mvBL-M7"
+#define MV_VCI			"mvBL-M7"
+#define MV_FPGA_DATA		0xfff40000
+#define MV_FPGA_SIZE		0
+#define MV_KERNEL_ADDR		0xff810000
+#define MV_INITRD_ADDR		0xffb00000
+#define MV_SCRIPT_ADDR		0xff804000
+#define MV_SCRIPT_ADDR2		0xff806000
+#define MV_DTB_ADDR		0xff808000
+#define MV_INITRD_LENGTH	0x00400000
+
+#define CONFIG_SHOW_BOOT_PROGRESS 1
+
+#define MV_KERNEL_ADDR_RAM	0x00100000
+#define MV_DTB_ADDR_RAM		0x00600000
+#define MV_INITRD_ADDR_RAM	0x01000000
+
+#define CONFIG_BOOTCOMMAND	"if imi ${script_addr}; "		\
+					"then source ${script_addr}; "	\
+					"else source ${script_addr2}; "	\
+				"fi;"
+#define CONFIG_BOOTARGS		"root=/dev/ram ro rootfstype=squashfs"
+
+#define CONFIG_EXTRA_ENV_SETTINGS				\
+	"console_nr=0\0"					\
+	"baudrate=" __stringify(CONFIG_BAUDRATE) "\0"		\
+	"stdin=serial\0"					\
+	"stdout=serial\0"					\
+	"stderr=serial\0"					\
+	"fpga=0\0"						\
+	"fpgadata=" __stringify(MV_FPGA_DATA) "\0"			\
+	"fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0"		\
+	"script_addr=" __stringify(MV_SCRIPT_ADDR) "\0"		\
+	"script_addr2=" __stringify(MV_SCRIPT_ADDR2) "\0"		\
+	"mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0"		\
+	"mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0"	\
+	"mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0"		\
+	"mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0"	\
+	"mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0"	\
+	"mv_dtb_addr=" __stringify(MV_DTB_ADDR) "\0"			\
+	"mv_dtb_addr_ram=" __stringify(MV_DTB_ADDR_RAM) "\0"		\
+	"dtb_name=" __stringify(MV_DTB_NAME) "\0"			\
+	"mv_version=" U_BOOT_VERSION "\0"			\
+	"dhcp_client_id=" MV_CI "\0"				\
+	"dhcp_vendor-class-identifier=" MV_VCI "\0"		\
+	"netretry=no\0"						\
+	"use_static_ipaddr=no\0"				\
+	"static_ipaddr=192.168.90.10\0"				\
+	"static_netmask=255.255.255.0\0"			\
+	"static_gateway=0.0.0.0\0"				\
+	"initrd_name=uInitrd.mvBL-M7-rfs\0"			\
+	"zcip=no\0"						\
+	"netboot=yes\0"						\
+	"mvtest=Ff\0"						\
+	"tried_bootfromflash=no\0"				\
+	"tried_bootfromnet=no\0"				\
+	"bootfile=mvblm72625.boot\0"				\
+	"use_dhcp=yes\0"					\
+	"gev_start=yes\0"					\
+	"mvbcdma_debug=0\0"					\
+	"mvbcia_debug=0\0"					\
+	"propdev_debug=0\0"					\
+	"gevss_debug=0\0"					\
+	"watchdog=0\0"						\
+	"usb_dr_mode=host\0"					\
+	"sensor_cnt=2\0"					\
+	""
+
+#define CONFIG_FPGA_COUNT	1
+#define CONFIG_FPGA
+#define CONFIG_FPGA_ALTERA
+#define CONFIG_FPGA_CYCLON2
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/MVBLUE.h b/qemu/roms/u-boot/include/configs/MVBLUE.h
new file mode 100644
index 000000000..aa2d9c02d
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/MVBLUE.h
@@ -0,0 +1,325 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define MV_VERSION	"v0.2.0"
+
+/* LED0 = Power , LED1 = Error , LED2-5 = error code, LED6-7=00 -->PPCBoot error */
+#define ERR_NONE		0
+#define ERR_ENV			1
+#define ERR_BOOTM_BADMAGIC	2
+#define ERR_BOOTM_BADCRC	3
+#define ERR_BOOTM_GUNZIP	4
+#define ERR_BOOTP_TIMEOUT	5
+#define ERR_DHCP		6
+#define ERR_TFTP		7
+#define ERR_NOLAN		8
+#define ERR_LANDRV		9
+
+#define CONFIG_BOARD_TYPES	1
+#define MVBLUE_BOARD_BOX	1
+#define MVBLUE_BOARD_LYNX	2
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
+#define CONFIG_SYS_LDSCRIPT	"board/mvblue/u-boot.lds"
+
+#if 0
+#define ERR_LED(code)	do { if (code) \
+		*(volatile char *)(0xff000003) = ( 3 | (code<<4) ) & 0xf3; \
+	else \
+		*(volatile char *)(0xff000003) = ( 1 ); \
+} while(0)
+#else
+#define ERR_LED(code)
+#endif
+
+#define CONFIG_MPC8245		1
+#define CONFIG_MVBLUE		1
+
+#define CONFIG_CLOCKS_IN_MHZ	1
+
+#define CONFIG_BOARD_TYPES	1
+
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOT_RETRY_TIME	-1
+
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT		\
+	"autoboot in %d seconds (stop with 's')...\n", bootdelay
+#define CONFIG_AUTOBOOT_STOP_STR	"s"
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define CONFIG_RESET_TO_RETRY		60
+
+
+/*
+ * Command line configuration.
+ */
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_RUN
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_NISDOMAIN
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_NTPSERVER
+#define CONFIG_BOOTP_TIMEOFFSET
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	16		/* Max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_LOAD_ADDR	0x00100000	/* Default load address			*/
+
+#define CONFIG_BOOTCOMMAND	"run nfsboot"
+#define CONFIG_BOOTARGS			"root=/dev/mtdblock5 ro rootfstype=jffs2"
+
+#define CONFIG_NFSBOOTCOMMAND	"bootp; run nfsargs addcons;bootm"
+
+#define CONFIG_EXTRA_ENV_SETTINGS			\
+	"console_nr=0\0"				\
+    "dhcp_client_id=mvBOX-XP\0"				\
+    "dhcp_vendor-class-identifier=mvBOX\0"		\
+    "adminboot=setenv bootargs root=/dev/mtdblock5 rw rootfstype=jffs2;run addcons;bootm ffc00000\0"	\
+    "flashboot=setenv bootargs root=/dev/mtdblock5 ro rootfstype=jffs2;run addcons;bootm ffc00000\0"	\
+    "safeboot=setenv bootargs root=/dev/mtdblock2 rw rootfstype=cramfs;run addcons;bootm ffc00000\0"	\
+    "hdboot=setenv bootargs root=/dev/hda1;run addcons;bootm ffc00000\0"	\
+	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
+			"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0"	\
+	"addcons=setenv bootargs ${bootargs} console=ttyS${console_nr},${baudrate}N8\0" \
+    "mv_version=" MV_VERSION "\0"	\
+	"bootretry=30\0"
+
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+
+#define CONFIG_NET_RETRY_COUNT		5
+
+#define CONFIG_TULIP
+#define CONFIG_TULIP_FIX_DAVICOM	1
+#define CONFIG_ETHADDR			b6:b4:45:eb:fb:c0
+
+#define CONFIG_HW_WATCHDOG
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE	    0x00000000
+
+#define CONFIG_SYS_FLASH_BASE      0xFFF00000
+#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_RESET_ADDRESS   0xFFF00100
+#define CONFIG_SYS_EUMB_ADDR	    0xFC000000
+
+#define CONFIG_SYS_MONITOR_LEN     0x00100000
+#define CONFIG_SYS_MALLOC_LEN      (512 << 10) /* Reserve some kB for malloc()  */
+
+#define CONFIG_SYS_MEMTEST_START   0x00100000	/* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END	    0x00800000	/* 1M ... 8M in DRAM		*/
+
+/* Maximum amount of RAM.  */
+#define CONFIG_SYS_MAX_RAM_SIZE    0x10000000	/* 0 .. 256MB of (S)DRAM */
+
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+#undef CONFIG_SYS_RAMBOOT
+#else
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_ISA_IO      0xFE000000
+
+/*
+ * serial configuration
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+
+#define CONFIG_SYS_NS16550_REG_SIZE    1
+
+#define CONFIG_SYS_NS16550_CLK     get_bus_freq(0)
+
+#define CONFIG_SYS_NS16550_COM1    (CONFIG_SYS_EUMB_ADDR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2    (CONFIG_SYS_EUMB_ADDR + 0x4600)
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE      0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ * For the detail description refer to the MPC8240 user's manual.
+ */
+
+#define CONFIG_SYS_CLK_FREQ  33000000
+
+/* Bit-field values for MCCR1.  */
+#define CONFIG_SYS_ROMNAL      7
+#define CONFIG_SYS_ROMFAL      11
+
+/* Bit-field values for MCCR2.  */
+#define CONFIG_SYS_TSWAIT      0x5
+#define CONFIG_SYS_REFINT      430
+
+/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.  */
+#define CONFIG_SYS_BSTOPRE     121
+
+/* Bit-field values for MCCR3.  */
+#define CONFIG_SYS_REFREC      8
+
+/* Bit-field values for MCCR4.  */
+#define CONFIG_SYS_PRETOACT    3
+#define CONFIG_SYS_ACTTOPRE    5
+#define CONFIG_SYS_ACTORW      3
+#define CONFIG_SYS_SDMODE_CAS_LAT  3
+#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
+#define CONFIG_SYS_EXTROM      1
+#define CONFIG_SYS_REGDIMM     0
+#define CONFIG_SYS_DBUS_SIZE2  1
+#define CONFIG_SYS_SDMODE_WRAP 0
+
+#define CONFIG_SYS_PGMAX       0x32
+#define CONFIG_SYS_SDRAM_DSCD  0x20
+
+/* Memory bank settings.
+ * Only bits 20-29 are actually used from these vales to set the
+ * start/end addresses. The upper two bits will always be 0, and the lower
+ * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
+ * address. Refer to the MPC8240 book.
+ */
+
+#define CONFIG_SYS_BANK0_START	    0x00000000
+#define CONFIG_SYS_BANK0_END	    (CONFIG_SYS_MAX_RAM_SIZE - 1)
+#define CONFIG_SYS_BANK0_ENABLE    1
+#define CONFIG_SYS_BANK1_START     0x3ff00000
+#define CONFIG_SYS_BANK1_END       0x3fffffff
+#define CONFIG_SYS_BANK1_ENABLE    0
+#define CONFIG_SYS_BANK2_START     0x3ff00000
+#define CONFIG_SYS_BANK2_END       0x3fffffff
+#define CONFIG_SYS_BANK2_ENABLE    0
+#define CONFIG_SYS_BANK3_START     0x3ff00000
+#define CONFIG_SYS_BANK3_END       0x3fffffff
+#define CONFIG_SYS_BANK3_ENABLE    0
+#define CONFIG_SYS_BANK4_START     0x3ff00000
+#define CONFIG_SYS_BANK4_END       0x3fffffff
+#define CONFIG_SYS_BANK4_ENABLE    0
+#define CONFIG_SYS_BANK5_START     0x3ff00000
+#define CONFIG_SYS_BANK5_END       0x3fffffff
+#define CONFIG_SYS_BANK5_ENABLE    0
+#define CONFIG_SYS_BANK6_START     0x3ff00000
+#define CONFIG_SYS_BANK6_END       0x3fffffff
+#define CONFIG_SYS_BANK6_ENABLE    0
+#define CONFIG_SYS_BANK7_START     0x3ff00000
+#define CONFIG_SYS_BANK7_END       0x3fffffff
+#define CONFIG_SYS_BANK7_ENABLE    0
+
+#define CONFIG_SYS_ODCR	    0xff
+
+#define CONFIG_SYS_IBAT0L  (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U  (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_DBAT0L  CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U  CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L  CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U  CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L  CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U  CONFIG_SYS_IBAT3U
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#undef  CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS		1	/* Max number of flash banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT		63	/* Max number of sectors per flash	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	12000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	1000
+
+
+#define CONFIG_ENV_IS_IN_FLASH
+
+#define CONFIG_ENV_OFFSET		0x00010000
+#define CONFIG_ENV_SIZE		0x00010000
+#define CONFIG_ENV_SECT_SIZE	0x00010000
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	32
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/MVSMR.h b/qemu/roms/u-boot/include/configs/MVSMR.h
new file mode 100644
index 000000000..ad15506fa
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/MVSMR.h
@@ -0,0 +1,269 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004-2010
+ * Matrix-Vision GmbH, andre.schwarz@matrix-vision.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <version.h>
+
+#define CONFIG_MPC5200 	1
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xFF800000
+#endif
+#define CONFIG_SYS_LDSCRIPT	"board/matrix_vision/mvsmr/u-boot.lds"
+
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000
+
+#define CONFIG_MISC_INIT_R	1
+
+#define CONFIG_SYS_CACHELINE_SIZE	32
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CACHELINE_SHIFT	5
+#endif
+
+#define CONFIG_PSC_CONSOLE	1
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200,\
+						230400}
+
+#define CONFIG_PCI		1
+#define CONFIG_PCI_PNP		1
+#undef	CONFIG_PCI_SCAN_SHOW
+#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1
+
+#define CONFIG_PCI_MEM_BUS	0x40000000
+#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE	0x10000000
+
+#define CONFIG_PCI_IO_BUS	0x50000000
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0x01000000
+
+#define CONFIG_SYS_XLB_PIPELINING	1
+#define CONFIG_HIGH_BATS	1
+
+#define MV_CI			mvSMR
+#define MV_VCI			mvSMR
+#define MV_FPGA_DATA		0xff840000
+#define MV_FPGA_SIZE		0x1ff88
+#define MV_KERNEL_ADDR		0xfff00000
+#define MV_SCRIPT_ADDR		0xff806000
+#define MV_INITRD_ADDR		0xff880000
+#define MV_INITRD_LENGTH	0x00240000
+#define MV_SCRATCH_ADDR		0xffcc0000
+#define MV_SCRATCH_LENGTH	MV_INITRD_LENGTH
+
+#define CONFIG_SHOW_BOOT_PROGRESS 1
+
+#define MV_KERNEL_ADDR_RAM	0x00100000
+#define MV_INITRD_ADDR_RAM	0x00400000
+
+/*
+ * Supported commands
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_FPGA
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SDRAM
+
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_NTPSERVER
+#define CONFIG_BOOTP_RANDOM_DELAY
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_VENDOREX
+#define CONFIG_LIB_RAND
+
+/*
+ * Autoboot
+ */
+#define CONFIG_BOOTDELAY		1
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_STOP_STR 	"abcdefg"
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#define CONFIG_BOOTCOMMAND      "source ${script_addr}"
+#define CONFIG_BOOTARGS		"root=/dev/ram ro rootfstype=squashfs" \
+					" allocate=6M"
+
+#define CONFIG_EXTRA_ENV_SETTINGS				\
+	"console_nr=0\0"					\
+	"console=no\0"						\
+	"stdin=serial\0"					\
+	"stdout=serial\0"					\
+	"stderr=serial\0"					\
+	"fpga=0\0"						\
+	"fpgadata=" __stringify(MV_FPGA_DATA) "\0"			\
+	"fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0"		\
+	"mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0"		\
+	"mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0"	\
+	"script_addr=" __stringify(MV_SCRIPT_ADDR) "\0"		\
+	"mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0"		\
+	"mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0"	\
+	"mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0"	\
+	"mv_scratch_addr=" __stringify(MV_SCRATCH_ADDR) "\0"		\
+	"mv_scratch_length=" __stringify(MV_SCRATCH_LENGTH) "\0"	\
+	"mv_version=" U_BOOT_VERSION "\0"			\
+	"dhcp_client_id=" __stringify(MV_CI) "\0"			\
+	"dhcp_vendor-class-identifier=" __stringify(MV_VCI) "\0"	\
+	"netretry=no\0"						\
+	"use_static_ipaddr=no\0"				\
+	"static_ipaddr=192.168.0.101\0"				\
+	"static_netmask=255.255.255.0\0"			\
+	"static_gateway=0.0.0.0\0"				\
+	"initrd_name=uInitrd.mvsmr-rfs\0"			\
+	"zcip=yes\0"						\
+	"netboot=no\0"						\
+	""
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK
+
+/*
+ * Flash configuration
+ */
+#undef 	CONFIG_FLASH_16BIT
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	50000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	1000
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	256
+
+#define CONFIG_SYS_LOWBOOT
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_FLASH_SIZE		0x00800000
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+#undef	CONFIG_SYS_FLASH_PROTECTION
+#define	CONFIG_OVERWRITE_ETHADDR_ONCE
+
+#define CONFIG_ENV_OFFSET	0x8000
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x2000
+
+/* used by linker script to wrap code around */
+#define CONFIG_SCRIPT_OFFSET	0x6000
+#define CONFIG_SCRIPT_SECT_SIZE	0x2000
+
+/*
+ * Memory map
+ */
+#define CONFIG_SYS_MBAR		0xF0000000
+#define CONFIG_SYS_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
+
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+						GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT		1
+#endif
+
+/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
+#define CONFIG_SYS_MONITOR_LEN		(512 << 10)
+#define CONFIG_SYS_MALLOC_LEN		(512 << 10)
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1
+#define CONFIG_SYS_I2C_MODULE	1
+#define CONFIG_SYS_I2C_SPEED	86000
+#define CONFIG_SYS_I2C_SLAVE	0x7F
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_NET_RETRY_COUNT 5
+
+#define CONFIG_MPC5xxx_FEC
+#define CONFIG_MPC5xxx_FEC_MII100
+#define CONFIG_PHY_ADDR		0x00
+#define CONFIG_NETDEV		eth0
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_CMDLINE_EDITING
+#undef 	CONFIG_SYS_LONGHELP
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE		1024
+#else
+#define CONFIG_SYS_CBSIZE		256
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START	0x00800000
+#define CONFIG_SYS_MEMTEST_END		0x02f00000
+
+/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x02000000
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR 		0x00200000
+
+/*
+ * Various low-level settings
+ */
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x00050044
+
+#define CONFIG_SYS_HID0_INIT		(HID0_ICE | HID0_ICFI)
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
+
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_CFG		0x00047800
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
+
+#define CONFIG_SYS_CS_BURST		0x000000f0
+#define CONFIG_SYS_CS_DEADCYCLE		0x33333303
+
+#define CONFIG_SYS_RESET_ADDRESS	0x00000100
+
+#undef FPGA_DEBUG
+#undef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#define CONFIG_FPGA
+#define CONFIG_FPGA_XILINX	1
+#define CONFIG_FPGA_SPARTAN2	1
+#define CONFIG_FPGA_COUNT	1
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/MigoR.h b/qemu/roms/u-boot/include/configs/MigoR.h
new file mode 100644
index 000000000..88df94f11
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/MigoR.h
@@ -0,0 +1,127 @@
+/*
+ * Configuation settings for the Renesas Solutions Migo-R board
+ *
+ * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MIGO_R_H
+#define __MIGO_R_H
+
+#undef DEBUG
+#define CONFIG_CPU_SH7722	1
+#define CONFIG_MIGO_R		1
+
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SAVEENV
+
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTARGS		"console=ttySC0,115200 root=1f01"
+
+#define CONFIG_VERSION_VARIABLE
+#undef  CONFIG_SHOW_BOOT_PROGRESS
+
+/* SMC9111 */
+#define CONFIG_SMC91111
+#define CONFIG_SMC91111_BASE    (0xB0000000)
+
+/* MEMORY */
+#define MIGO_R_SDRAM_BASE	(0x8C000000)
+#define MIGO_R_FLASH_BASE_1	(0xA0000000)
+#define MIGO_R_FLASH_BANK_SIZE	(64 * 1024 * 1024)
+
+#define CONFIG_SYS_TEXT_BASE	0x8FFC0000
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_SYS_CBSIZE		256		/* Buffer size for input from the Console */
+#define CONFIG_SYS_PBSIZE		256		/* Buffer size for Console output */
+#define CONFIG_SYS_MAXARGS		16		/* max args accepted for monitor commands */
+#define CONFIG_SYS_BARGSIZE	512		/* Buffer size for Boot Arguments passed to kernel */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }	/* List of legal baudrate settings for this board */
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE	1
+#define CONFIG_CONS_SCIF0	1
+#undef  CONFIG_SYS_CONSOLE_INFO_QUIET	/* Suppress display of console
+								   information at boot */
+#undef  CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#undef  CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+
+#define CONFIG_SYS_MEMTEST_START	(MIGO_R_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
+
+/* Enable alternate, more extensive, memory test */
+#undef  CONFIG_SYS_ALT_MEMTEST
+/* Scratch address used by the alternate memory test */
+#undef  CONFIG_SYS_MEMTEST_SCRATCH
+
+/* Enable temporary baudrate change while serial download */
+#undef  CONFIG_SYS_LOADS_BAUD_CHANGE
+
+#define CONFIG_SYS_SDRAM_BASE	(MIGO_R_SDRAM_BASE)
+/* maybe more, but if so u-boot doesn't know about it... */
+#define CONFIG_SYS_SDRAM_SIZE	(64 * 1024 * 1024)
+/* default load address for scripts ?!? */
+#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
+
+/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
+#define CONFIG_SYS_MONITOR_BASE	(MIGO_R_FLASH_BASE_1)
+/* Monitor size */
+#define CONFIG_SYS_MONITOR_LEN	(128 * 1024)
+/* Size of DRAM reserved for malloc() use */
+#define CONFIG_SYS_MALLOC_LEN	(256 * 1024)
+#define CONFIG_SYS_BOOTMAPSZ	(8 * 1024 * 1024)
+
+/* FLASH */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#undef  CONFIG_SYS_FLASH_QUIET_TEST
+/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+/* Physical start address of Flash memory */
+#define CONFIG_SYS_FLASH_BASE	(MIGO_R_FLASH_BASE_1)
+/* Max number of sectors on each Flash chip */
+#define CONFIG_SYS_MAX_FLASH_SECT	512
+
+/* if you use all NOR Flash , you change dip-switch. Please see MIGO_R01 Manual. */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE + (0 * MIGO_R_FLASH_BANK_SIZE) }
+
+/* Timeout for Flash erase operations (in ms) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(3 * 1000)
+/* Timeout for Flash write operations (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(3 * 1000)
+/* Timeout for Flash set sector lock bit operations (in ms) */
+#define CONFIG_SYS_FLASH_LOCK_TOUT	(3 * 1000)
+/* Timeout for Flash clear lock bit operations (in ms) */
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	(3 * 1000)
+
+/* Use hardware flash sectors protection instead of U-Boot software protection */
+#undef  CONFIG_SYS_FLASH_PROTECTION
+#undef  CONFIG_SYS_DIRECT_FLASH_TFTP
+
+/* ENV setting */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE	1
+#define CONFIG_ENV_SECT_SIZE	(128 * 1024)
+#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
+/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
+#define CONFIG_ENV_OFFSET		(CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
+
+/* Board Clock */
+#define CONFIG_SYS_CLK_FREQ	33333333
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_TMU_CLK_DIV		(4)	/* 4 (default), 16, 64, 256 or 1024 */
+
+#endif	/* __MIGO_R_H */
diff --git a/qemu/roms/u-boot/include/configs/NETPHONE.h b/qemu/roms/u-boot/include/configs/NETPHONE.h
new file mode 100644
index 000000000..08cfc9e4b
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/NETPHONE.h
@@ -0,0 +1,701 @@
+/*
+ * (C) Copyright 2000-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
+ * U-Boot port on NetTA4 board
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#if !defined(CONFIG_NETPHONE_VERSION) || CONFIG_NETPHONE_VERSION > 2
+#error Unsupported CONFIG_NETPHONE version
+#endif
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC870		1	/* This is a MPC885 CPU		*/
+#define CONFIG_NETPHONE		1	/* ...on a NetPhone board	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0x40000000
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+
+/* #define CONFIG_XIN		 10000000 */
+#define CONFIG_XIN		 50000000
+/* #define MPC8XX_HZ		120000000 */
+#define MPC8XX_HZ		 66666666
+
+#define CONFIG_8xx_GCLK_FREQ	MPC8XX_HZ
+
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#undef	CONFIG_CLOCKS_IN_MHZ	/* clocks NOT passsed to Linux in MHz */
+
+#define CONFIG_PREBOOT	"echo;"
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND							\
+	"tftpboot; "								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"	\
+	"bootm"
+
+#define CONFIG_SOURCE
+#define CONFIG_LOADS_ECHO	0	/* echo off for serial download	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+#define CONFIG_BOARD_SPECIFIC_LED	/* version has board specific leds */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_NISDOMAIN
+
+#undef CONFIG_MAC_PARTITION
+#undef CONFIG_DOS_PARTITION
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+#define	FEC_ENET		1	/* eth.c needs it that way... */
+#undef CONFIG_SYS_DISCOVER_PHY
+#define CONFIG_MII		1
+#define CONFIG_MII_INIT		1
+#define CONFIG_RMII		1	/* use RMII interface */
+
+#define CONFIG_ETHER_ON_FEC1	1
+#define CONFIG_FEC1_PHY		8	/* phy address of FEC */
+#define CONFIG_FEC1_PHY_NORXERR 1
+
+#define CONFIG_ETHER_ON_FEC2	1
+#define CONFIG_FEC2_PHY		4
+#define CONFIG_FEC2_PHY_NORXERR 1
+
+#define CONFIG_ENV_OVERWRITE	1	/* allow modification of vendor params */
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_CDP
+
+
+#define CONFIG_BOARD_EARLY_INIT_F	1
+#define CONFIG_MISC_INIT_R
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+
+#define CONFIG_SYS_HUSH_PARSER	1
+
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0300000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0700000	/* 3 ... 7 MB in DRAM	*/
+
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xFF000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x3000	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#if defined(DEBUG)
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#else
+#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#endif
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#if CONFIG_NETPHONE_VERSION == 2
+#define CONFIG_SYS_FLASH_BASE4		0x40080000
+#endif
+
+#define CONFIG_SYS_RESET_ADDRESS   0x80000000
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#if CONFIG_NETPHONE_VERSION == 1
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#elif CONFIG_NETPHONE_VERSION == 2
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#endif
+#define CONFIG_SYS_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_SECT_SIZE	0x10000
+
+#define	CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x60000)
+#define	CONFIG_ENV_SIZE		0x4000
+
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_SYS_FLASH_BASE + 0x70000)
+#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef	CONFIG_CAN_DRIVER
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
+#else	/* we must activate GPL5 in the SIUMCR for CAN */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ *
+ */
+
+#if CONFIG_XIN == 10000000
+
+#if MPC8XX_HZ == 120000000
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
+			 PLPRCR_TEXPS)
+#elif MPC8XX_HZ == 100000000
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
+			 PLPRCR_TEXPS)
+#elif MPC8XX_HZ == 50000000
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
+			 PLPRCR_TEXPS)
+#elif MPC8XX_HZ == 25000000
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
+			 PLPRCR_TEXPS)
+#elif MPC8XX_HZ == 40000000
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
+			 PLPRCR_TEXPS)
+#elif MPC8XX_HZ == 75000000
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
+			 PLPRCR_TEXPS)
+#else
+#error unsupported CPU freq for XIN = 10MHz
+#endif
+
+#elif CONFIG_XIN == 50000000
+
+#if MPC8XX_HZ == 120000000
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
+			 PLPRCR_TEXPS)
+#elif MPC8XX_HZ == 100000000
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
+			 PLPRCR_TEXPS)
+#elif MPC8XX_HZ ==  66666666
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
+			 PLPRCR_TEXPS)
+#else
+#error unsupported CPU freq for XIN = 50MHz
+#endif
+
+#else
+
+#error unsupported XIN freq
+#endif
+
+
+/*
+ *-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ *
+ * Note: When TBS == 0 the timebase is independent of current cpu clock.
+ */
+
+#define SCCR_MASK	SCCR_EBDF11
+#if MPC8XX_HZ > 66666666
+#define CONFIG_SYS_SCCR	(/* SCCR_TBS	| */ SCCR_CRQEN | \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00 | SCCR_EBDF01)
+#else
+#define CONFIG_SYS_SCCR	(/* SCCR_TBS	| */ SCCR_CRQEN | \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+#endif
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+/*#define	CONFIG_SYS_DER	0x2002000F*/
+#define CONFIG_SYS_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_BI | OR_SCY_5_CLK | OR_TRLX)
+
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
+
+#if CONFIG_NETPHONE_VERSION == 2
+
+#define FLASH_BASE4_PRELIM	0x40080000	/* FLASH bank #1	*/
+
+#define CONFIG_SYS_OR4_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR4_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR4_PRELIM	((FLASH_BASE4_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
+
+#endif
+
+/*
+ * BR3 and OR3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE3_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define	SDRAM_MAX_SIZE		(256 << 20)	/* max 256MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CONFIG_SYS_OR_TIMING_SDRAM	(OR_CSNT_SAM | OR_G5LS)
+
+#define CONFIG_SYS_OR3_PRELIM	((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM)
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V)
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ *	gclk	  CPU clock (not bus clock!)
+ *	Trefresh  Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096  Rows from SDRAM example configuration
+ * 1000  factor s -> ms
+ *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
+ *    4  Number of refresh cycles per period
+ *   64  Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ * 50 MHz => 50.000.000 / Divider =  98
+ * 66 Mhz => 66.000.000 / Divider = 129
+ * 80 Mhz => 80.000.000 / Divider = 156
+ */
+
+#define CONFIG_SYS_MAMR_PTA		 234
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ */
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+/* 9 column SDRAM */
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+#define CONFIG_LAST_STAGE_INIT		/* needed to reset the damn phys */
+
+/****************************************************************/
+
+#define DSP_SIZE	0x00010000	/* 64K */
+#define NAND_SIZE	0x00010000	/* 64K */
+
+#define DSP_BASE	0xF1000000
+#define NAND_BASE	0xF1010000
+
+/*****************************************************************************/
+
+#define CONFIG_SYS_DIRECT_FLASH_TFTP
+
+/*****************************************************************************/
+
+#if CONFIG_NETPHONE_VERSION == 1
+#define STATUS_LED_BIT		0x00000008		/* bit 28 */
+#elif CONFIG_NETPHONE_VERSION == 2
+#define STATUS_LED_BIT		0x00000080		/* bit 24 */
+#endif
+
+#define STATUS_LED_PERIOD	(CONFIG_SYS_HZ / 2)
+#define STATUS_LED_STATE	STATUS_LED_BLINKING
+
+#define STATUS_LED_ACTIVE	0		/* LED on for bit == 0	*/
+#define STATUS_LED_BOOT		0		/* LED 0 used for boot status */
+
+#ifndef __ASSEMBLY__
+
+/* LEDs */
+
+/* led_id_t is unsigned int mask */
+typedef unsigned int led_id_t;
+
+#define __led_toggle(_msk) \
+	do { \
+		((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat ^= (_msk); \
+	} while(0)
+
+#define __led_set(_msk, _st) \
+	do { \
+		if ((_st)) \
+			((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat |= (_msk); \
+		else \
+			((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat &= ~(_msk); \
+	} while(0)
+
+#define __led_init(msk, st) __led_set(msk, st)
+
+#endif
+
+/***********************************************************************************************************
+
+ ----------------------------------------------------------------------------------------------
+
+   (V1) version 1 of the board
+   (V2) version 2 of the board
+
+ ----------------------------------------------------------------------------------------------
+
+   Pin definitions:
+
+ +------+----------------+--------+------------------------------------------------------------
+ |  #   | Name           | Type   | Comment
+ +------+----------------+--------+------------------------------------------------------------
+ | PA3  | SPIEN_MAX      | Output | MAX serial to uart chip select
+ | PA7  | DSP_INT        | Output | DSP interrupt
+ | PA10 | DSP_RESET      | Output | DSP reset
+ | PA14 | USBOE          | Output | USB (1)
+ | PA15 | USBRXD         | Output | USB (1)
+ | PB19 | BT_RTS         | Output | Bluetooth (0)
+ | PB23 | BT_CTS         | Output | Bluetooth (0)
+ | PB26 | SPIEN_SEP      | Output | Serial EEPROM chip select
+ | PB27 | SPICS_DISP     | Output | Display chip select
+ | PB28 | SPI_RXD_3V     | Input  | SPI Data Rx
+ | PB29 | SPI_TXD        | Output | SPI Data Tx
+ | PB30 | SPI_CLK        | Output | SPI Clock
+ | PC10 | DISPA0         | Output | Display A0
+ | PC11 | BACKLIGHT      | Output | Display backlit
+ | PC12 | SPI2RXD        | Input  | (V1) 2nd SPI RXD
+ |      | IO_RESET       | Output | (V2) General I/O reset
+ | PC13 | SPI2TXD        | Output | (V1) 2nd SPI TXD (V1)
+ |      | HOOK           | Input  | (V2) Hook input interrupt
+ | PC15 | SPI2CLK        | Output | (V1) 2nd SPI CLK
+ |      | F_RY_BY        | Input  | (V2) NAND F_RY_BY
+ | PE17 | F_ALE          | Output | NAND F_ALE
+ | PE18 | F_CLE          | Output | NAND F_CLE
+ | PE20 | F_CE           | Output | NAND F_CE
+ | PE24 | SPICS_SCOUT    | Output | (V1) Codec chip select
+ |      | LED            | Output | (V2) LED
+ | PE27 | SPICS_ER       | Output | External serial register CS
+ | PE28 | LEDIO1         | Output | (V1) LED
+ |      | BKBR1          | Input  | (V2) Keyboard input scan
+ | PE29 | LEDIO2         | Output | (V1) LED hook for A (TA2)
+ |      | BKBR2          | Input  | (V2) Keyboard input scan
+ | PE30 | LEDIO3         | Output | (V1) LED hook for A (TA2)
+ |      | BKBR3          | Input  | (V2) Keyboard input scan
+ | PE31 | F_RY_BY        | Input  | (V1) NAND F_RY_BY
+ |      | BKBR4          | Input  | (V2) Keyboard input scan
+ +------+----------------+--------+---------------------------------------------------
+
+ ----------------------------------------------------------------------------------------------
+
+   Serial register input:
+
+ +------+----------------+------------------------------------------------------------
+ |  #   | Name           | Comment
+ +------+----------------+------------------------------------------------------------
+ |    0 | BKBR1          | (V1) Keyboard input scan
+ |    1 | BKBR3          | (V1) Keyboard input scan
+ |    2 | BKBR4          | (V1) Keyboard input scan
+ |    3 | BKBR2          | (V1) Keyboard input scan
+ |    4 | HOOK           | (V1) Hook switch
+ |    5 | BT_LINK        | (V1) Bluetooth link status
+ |    6 | HOST_WAKE      | (V1) Bluetooth host wake up
+ |    7 | OK_ETH         | (V1) Cisco inline power OK status
+ +------+----------------+------------------------------------------------------------
+
+ ----------------------------------------------------------------------------------------------
+
+   Serial register output:
+
+ +------+----------------+------------------------------------------------------------
+ |  #   | Name           | Comment
+ +------+----------------+------------------------------------------------------------
+ |    0 | KEY1           | Keyboard output scan
+ |    1 | KEY2           | Keyboard output scan
+ |    2 | KEY3           | Keyboard output scan
+ |    3 | KEY4           | Keyboard output scan
+ |    4 | KEY5           | Keyboard output scan
+ |    5 | KEY6           | Keyboard output scan
+ |    6 | KEY7           | Keyboard output scan
+ |    7 | BT_WAKE        | Bluetooth wake up
+ +------+----------------+------------------------------------------------------------
+
+ ----------------------------------------------------------------------------------------------
+
+ Chip selects:
+
+ +------+----------------+------------------------------------------------------------
+ |  #   | Name           | Comment
+ +------+----------------+------------------------------------------------------------
+ | CS0  | CS0            | Boot flash
+ | CS1  | CS_FLASH       | NAND flash
+ | CS2  | CS_DSP         | DSP
+ | CS3  | DCS_DRAM       | DRAM
+ | CS4  | CS_FLASH2      | (V2) 2nd flash
+ +------+----------------+------------------------------------------------------------
+
+ ----------------------------------------------------------------------------------------------
+
+ Interrupts:
+
+ +------+----------------+------------------------------------------------------------
+ |  #   | Name           | Comment
+ +------+----------------+------------------------------------------------------------
+ | IRQ1 | IRQ_DSP        | DSP interrupt
+ | IRQ3 | S_INTER        | DUSLIC ???
+ | IRQ4 | F_RY_BY        | NAND
+ | IRQ7 | IRQ_MAX        | MAX 3100 interrupt
+ +------+----------------+------------------------------------------------------------
+
+ ----------------------------------------------------------------------------------------------
+
+ Interrupts on PCMCIA pins:
+
+ +------+----------------+------------------------------------------------------------
+ |  #   | Name           | Comment
+ +------+----------------+------------------------------------------------------------
+ | IP_A0| PHY1_LINK      | Link status changed for #1 Ethernet interface
+ | IP_A1| PHY2_LINK      | Link status changed for #2 Ethernet interface
+ | IP_A2| RMII1_MDINT    | PHY interrupt for #1
+ | IP_A3| RMII2_MDINT    | PHY interrupt for #2
+ | IP_A5| HOST_WAKE      | (V2) Bluetooth host wake
+ | IP_A6| OK_ETH         | (V2) Cisco inline power OK
+ +------+----------------+------------------------------------------------------------
+
+*************************************************************************************************/
+
+#define CONFIG_SED156X			1	/* use SED156X */
+#define CONFIG_SED156X_PG12864Q		1	/* type of display used */
+
+/* serial interfacing macros */
+
+#define SED156X_SPI_RXD_PORT	(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
+#define SED156X_SPI_RXD_MASK	0x00000008
+
+#define SED156X_SPI_TXD_PORT	(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
+#define SED156X_SPI_TXD_MASK	0x00000004
+
+#define SED156X_SPI_CLK_PORT	(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
+#define SED156X_SPI_CLK_MASK	0x00000002
+
+#define SED156X_CS_PORT		(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
+#define SED156X_CS_MASK		0x00000010
+
+#define SED156X_A0_PORT		(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat)
+#define SED156X_A0_MASK		0x0020
+
+/*************************************************************************************************/
+
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV		1
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE	1
+#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE	1
+
+/*************************************************************************************************/
+
+/* use board specific hardware */
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+#define CONFIG_HW_WATCHDOG
+#define CONFIG_SHOW_ACTIVITY
+
+/*************************************************************************************************/
+
+/* phone console configuration */
+
+#define PHONE_CONSOLE_POLL_HZ		(CONFIG_SYS_HZ/200)	/* poll every 5ms */
+
+/*************************************************************************************************/
+
+#define CONFIG_CDP_DEVICE_ID		20
+#define CONFIG_CDP_DEVICE_ID_PREFIX	"NP"	/* netphone */
+#define CONFIG_CDP_PORT_ID		"eth%d"
+#define CONFIG_CDP_CAPABILITIES		0x00000010
+#define CONFIG_CDP_VERSION		"u-boot" " " U_BOOT_DATE " " U_BOOT_TIME
+#define CONFIG_CDP_PLATFORM		"Intracom NetPhone"
+#define CONFIG_CDP_TRIGGER		0x20020001
+#define CONFIG_CDP_POWER_CONSUMPTION	4300	/* 90 mA @ 48V */
+#define CONFIG_CDP_APPLIANCE_VLAN_TYPE	0x01	/* ipphone */
+
+/*************************************************************************************************/
+
+#define CONFIG_AUTO_COMPLETE	1
+
+/*************************************************************************************************/
+
+#define CONFIG_CRC32_VERIFY	1
+
+/*************************************************************************************************/
+
+#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE	1
+
+/*************************************************************************************************/
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/NETTA.h b/qemu/roms/u-boot/include/configs/NETTA.h
new file mode 100644
index 000000000..800a92267
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/NETTA.h
@@ -0,0 +1,666 @@
+/*
+ * (C) Copyright 2000-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
+ * U-Boot port on NetTA4 board
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC885		1	/* This is a MPC885 CPU		*/
+#define CONFIG_NETTA		1	/* ...on a NetTA board		*/
+
+#define	CONFIG_SYS_TEXT_BASE	0x40000000
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+
+/* #define CONFIG_XIN		 10000000 */
+#define CONFIG_XIN		 50000000
+#define MPC8XX_HZ		120000000
+/* #define MPC8XX_HZ		100000000 */
+/* #define MPC8XX_HZ		 50000000 */
+/* #define MPC8XX_HZ		 80000000 */
+
+#define CONFIG_8xx_GCLK_FREQ	MPC8XX_HZ
+
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#undef	CONFIG_CLOCKS_IN_MHZ	/* clocks NOT passsed to Linux in MHz */
+
+#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND							\
+	"tftpboot; "								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"	\
+	"bootm"
+
+#define CONFIG_LOADS_ECHO	0	/* echo off for serial download	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+#define CONFIG_HW_WATCHDOG
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_NISDOMAIN
+
+
+#undef CONFIG_MAC_PARTITION
+#undef CONFIG_DOS_PARTITION
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+#define	FEC_ENET		1	/* eth.c needs it that way... */
+#undef  CONFIG_SYS_DISCOVER_PHY		/* do not discover phys */
+#define CONFIG_MII		1
+#define CONFIG_MII_INIT		1
+#define CONFIG_RMII		1	/* use RMII interface */
+
+#if defined(CONFIG_NETTA_ISDN)
+#define CONFIG_ETHER_ON_FEC1	1
+#define CONFIG_FEC1_PHY		1	/* phy address of FEC1 */
+#define CONFIG_FEC1_PHY_NORXERR 1
+#undef  CONFIG_ETHER_ON_FEC2
+#else
+#define CONFIG_ETHER_ON_FEC1	1
+#define CONFIG_FEC1_PHY		8	/* phy address of FEC1 */
+#define CONFIG_FEC1_PHY_NORXERR 1
+#define CONFIG_ETHER_ON_FEC2	1
+#define CONFIG_FEC2_PHY		1	/* phy address of FEC2 */
+#define CONFIG_FEC2_PHY_NORXERR 1
+#endif
+
+#define CONFIG_ENV_OVERWRITE	1	/* allow modification of vendor params */
+
+/* POST support */
+#define CONFIG_POST		(CONFIG_SYS_POST_MEMORY   | \
+				 CONFIG_SYS_POST_CODEC	   | \
+				 CONFIG_SYS_POST_DSP	   )
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CDP
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCMCIA
+#define CONFIG_CMD_PING
+
+
+#define CONFIG_BOARD_EARLY_INIT_F	1
+#define CONFIG_MISC_INIT_R
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+
+#define CONFIG_SYS_HUSH_PARSER	1
+
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0300000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0700000	/* 3 ... 7 MB in DRAM	*/
+
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xFF000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x3000	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#if defined(DEBUG)
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#else
+#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#endif
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_SECT_SIZE	0x10000
+
+#define	CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x60000)
+#define	CONFIG_ENV_SIZE		0x4000
+
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_SYS_FLASH_BASE + 0x70000)
+#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef	CONFIG_CAN_DRIVER
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
+#else	/* we must activate GPL5 in the SIUMCR for CAN */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ *
+ */
+
+#if CONFIG_XIN == 10000000
+
+#if MPC8XX_HZ == 120000000
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
+			 PLPRCR_TEXPS)
+#elif MPC8XX_HZ == 100000000
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
+			 PLPRCR_TEXPS)
+#elif MPC8XX_HZ == 50000000
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
+			 PLPRCR_TEXPS)
+#elif MPC8XX_HZ == 25000000
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
+			 PLPRCR_TEXPS)
+#elif MPC8XX_HZ == 40000000
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
+			 PLPRCR_TEXPS)
+#elif MPC8XX_HZ == 75000000
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
+			 PLPRCR_TEXPS)
+#else
+#error unsupported CPU freq for XIN = 10MHz
+#endif
+
+#elif CONFIG_XIN == 50000000
+
+#if MPC8XX_HZ == 120000000
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
+			 PLPRCR_TEXPS)
+#elif MPC8XX_HZ == 100000000
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
+			 PLPRCR_TEXPS)
+#elif MPC8XX_HZ ==  80000000
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (0 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
+			 PLPRCR_TEXPS)
+#elif MPC8XX_HZ ==  50000000
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (1 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
+			 PLPRCR_TEXPS)
+#else
+#error unsupported CPU freq for XIN = 50MHz
+#endif
+
+#else
+
+#error unsupported XIN freq
+#endif
+
+
+/*
+ *-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ *
+ * Note: When TBS == 0 the timebase is independent of current cpu clock.
+ */
+
+#define SCCR_MASK	SCCR_EBDF11
+#if MPC8XX_HZ > 66666666
+#define CONFIG_SYS_SCCR	(/* SCCR_TBS	| */ SCCR_CRQEN | \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL111 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00 | SCCR_EBDF01)
+#else
+#define CONFIG_SYS_SCCR	(/* SCCR_TBS	| */ SCCR_CRQEN | \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL111 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+#endif
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+/*#define	CONFIG_SYS_DER	0x2002000F*/
+#define CONFIG_SYS_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_BI | OR_SCY_5_CLK | OR_TRLX)
+
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
+
+/*
+ * BR3 and OR3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE3_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define	SDRAM_MAX_SIZE		(256 << 20)	/* max 256MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CONFIG_SYS_OR_TIMING_SDRAM	(OR_CSNT_SAM | OR_G5LS)
+
+#define CONFIG_SYS_OR3_PRELIM	((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM)
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V)
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ *	gclk	  CPU clock (not bus clock!)
+ *	Trefresh  Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096  Rows from SDRAM example configuration
+ * 1000  factor s -> ms
+ *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
+ *    4  Number of refresh cycles per period
+ *   64  Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ * 50 MHz => 50.000.000 / Divider =  98
+ * 66 Mhz => 66.000.000 / Divider = 129
+ * 80 Mhz => 80.000.000 / Divider = 156
+ */
+
+#if   MPC8XX_HZ == 120000000
+#define CONFIG_SYS_MAMR_PTA		 234
+#elif MPC8XX_HZ == 100000000
+#define CONFIG_SYS_MAMR_PTA		 195
+#elif MPC8XX_HZ ==  80000000
+#define CONFIG_SYS_MAMR_PTA		 156
+#elif MPC8XX_HZ ==  50000000
+#define CONFIG_SYS_MAMR_PTA		  98
+#else
+#error Unknown frequency
+#endif
+
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ */
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+/* 9 column SDRAM */
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+#define CONFIG_LAST_STAGE_INIT		/* needed to reset the damn phys */
+
+/***********************************************************************************************************
+
+   Pin definitions:
+
+ +------+----------------+--------+------------------------------------------------------------
+ |  #   | Name           | Type   | Comment
+ +------+----------------+--------+------------------------------------------------------------
+ | PA3  | OK_ETH_3V      | Input  | CISCO Ethernet power OK
+ |      |                |        | (NetRoute: FEC1, TA: FEC2) (0=power OK)
+ | PA6  | P_VCCD1        | Output | TPS2211A PCMCIA
+ | PA7  | DCL1_3V        | Periph | IDL1 PCM clock
+ | PA8  | DSP_DR1        | Periph | IDL1 PCM Data Rx
+ | PA9  | L1TXDA         | Periph | IDL1 PCM Data Tx
+ | PA10 | P_VCCD0        | Output | TPS2211A PCMCIA
+ | PA12 | P_SHDN         | Output | TPS2211A PCMCIA
+ | PA13 | ETH_LOOP       | Output | CISCO Loopback remote power
+ |      |                |        | (NetRoute: FEC1, TA: FEC2) (1=NORMAL)
+ | PA14 | P_VPPD0        | Output | TPS2211A PCMCIA
+ | PA15 | P_VPPD1        | Output | TPS2211A PCMCIA
+ | PB14 | SPIEN_FXO      | Output | SPI CS for FXO daughter-board
+ | PB15 | SPIEN_S1       | Output | SPI CS for S-interface 1 (NetRoute only)
+ | PB16 | DREQ1          | Output | D channel request for S-interface chip 1.
+ | PB17 | L1ST3          | Periph | IDL1 timeslot enable signal for PPC
+ | PB18 | L1ST2          | Periph | IDL1 timeslot enable signal for PPC
+ | PB19 | SPIEN_S2       | Output | SPI CS for S-interface 2 (NetRoute only)
+ | PB20 | SPIEN_SEEPROM  | Output | SPI CS for serial eeprom
+ | PB21 | LEDIO          | Output | Led mode indication for PHY
+ | PB22 | UART_CTS       | Input  | UART CTS
+ | PB23 | UART_RTS       | Output | UART RTS
+ | PB24 | UART_RX        | Periph | UART Data Rx
+ | PB25 | UART_TX        | Periph | UART Data Tx
+ | PB26 | RMII-MDC       | Periph | Free for future use (MII mgt clock)
+ | PB27 | RMII-MDIO      | Periph | Free for future use (MII mgt data)
+ | PB28 | SPI_RXD_3V     | Input  | SPI Data Rx
+ | PB29 | SPI_TXD        | Output | SPI Data Tx
+ | PB30 | SPI_CLK        | Output | SPI Clock
+ | PB31 | RMII1-REFCLK   | Periph | RMII reference clock for FEC1
+ | PC4  | PHY1_LINK      | Input  | PHY link state FEC1 (interrupt)
+ | PC5  | PHY2_LINK      | Input  | PHY link state FEC2 (interrupt)
+ | PC6  | RMII1-MDINT    | Input  | PHY prog interrupt FEC1 (interrupt)
+ | PC7  | RMII2-MDINT    | Input  | PHY prog interrupt FEC1 (interrupt)
+ | PC8  | P_OC           | Input  | TPS2211A PCMCIA overcurrent (interrupt) (1=OK)
+ | PC9  | COM_HOOK1      | Input  | Codec interrupt chip #1 (interrupt)
+ | PC10 | COM_HOOK2      | Input  | Codec interrupt chip #2 (interrupt)
+ | PC11 | COM_HOOK4      | Input  | Codec interrupt chip #4 (interrupt)
+ | PC12 | COM_HOOK3      | Input  | Codec interrupt chip #3 (interrupt)
+ | PC13 | F_RY_BY        | Input  | NAND ready signal (interrupt)
+ | PC14 | FAN_OK         | Input  | Fan status signal (interrupt) (1=OK)
+ | PC15 | PC15_DIRECT0   | Periph | PCMCIA DMA request.
+ | PD3  | F_ALE          | Output | NAND
+ | PD4  | F_CLE          | Output | NAND
+ | PD5  | F_CE           | Output | NAND
+ | PD6  | DSP_INT        | Output | DSP debug interrupt
+ | PD7  | DSP_RESET      | Output | DSP reset
+ | PD8  | RMII_MDC       | Periph | MII mgt clock
+ | PD9  | SPIEN_C1       | Output | SPI CS for codec #1
+ | PD10 | SPIEN_C2       | Output | SPI CS for codec #2
+ | PD11 | SPIEN_C3       | Output | SPI CS for codec #3
+ | PD12 | FSC2           | Periph | IDL2 frame sync
+ | PD13 | DGRANT2        | Input  | D channel grant from S #2
+ | PD14 | SPIEN_C4       | Output | SPI CS for codec #4
+ | PD15 | TP700          | Output | Testpoint for software debugging
+ | PE14 | RMII2-TXD0     | Periph | FEC2 transmit data
+ | PE15 | RMII2-TXD1     | Periph | FEC2 transmit data
+ | PE16 | RMII2-REFCLK   | Periph | TA: RMII ref clock for
+ |      | DCL2           | Periph | NetRoute: PCM clock #2
+ | PE17 | TP703          | Output | Testpoint for software debugging
+ | PE18 | DGRANT1        | Input  |  D channel grant from S #1
+ | PE19 | RMII2-TXEN     | Periph | TA: FEC2 tx enable
+ |      | PCM2OUT        | Periph | NetRoute: Tx data for IDL2
+ | PE20 | FSC1           | Periph | IDL1 frame sync
+ | PE21 | RMII2-RXD0     | Periph | FEC2 receive data
+ | PE22 | RMII2-RXD1     | Periph | FEC2 receive data
+ | PE23 | L1ST1          | Periph | IDL1 timeslot enable signal for PPC
+ | PE24 | U-N1           | Output | Select user/network for S #1 (0=user)
+ | PE25 | U-N2           | Output | Select user/network for S #2 (0=user)
+ | PE26 | RMII2-RXDV     | Periph | FEC2 valid
+ | PE27 | DREQ2          | Output | D channel request for S #2.
+ | PE28 | FPGA_DONE      | Input  | FPGA done signal
+ | PE29 | FPGA_INIT      | Output | FPGA init signal
+ | PE30 | UDOUT2_3V      | Input  | IDL2 PCM input
+ | PE31 |                |        | Free
+ +------+----------------+--------+---------------------------------------------------
+
+ Chip selects:
+
+ +------+----------------+------------------------------------------------------------
+ |  #   | Name           | Comment
+ +------+----------------+------------------------------------------------------------
+ | CS0  | CS0            | Boot flash
+ | CS1  | CS_FLASH       | NAND flash
+ | CS2  | CS_DSP         | DSP
+ | CS3  | DCS_DRAM       | DRAM
+ | CS4  | CS_ER1         | External output register
+ +------+----------------+------------------------------------------------------------
+
+ Interrupts:
+
+ +------+----------------+------------------------------------------------------------
+ |  #   | Name           | Comment
+ +------+----------------+------------------------------------------------------------
+ | IRQ1 | UINTER_3V      | S interrupt chips interrupt (common)
+ | IRQ3 | IRQ_DSP        | DSP interrupt
+ | IRQ4 | IRQ_DSP1       | Extra DSP interrupt
+ +------+----------------+------------------------------------------------------------
+
+*************************************************************************************************/
+
+#define DSP_SIZE	0x00010000	/* 64K */
+#define NAND_SIZE	0x00010000	/* 64K */
+#define ER_SIZE		0x00010000	/* 64K */
+#define DUMMY_SIZE	0x00010000	/* 64K */
+
+#define DSP_BASE	0xF1000000
+#define NAND_BASE	0xF1010000
+#define ER_BASE		0xF1020000
+#define DUMMY_BASE	0xF1FF0000
+
+/*****************************************************************************/
+
+#define CONFIG_SYS_DIRECT_FLASH_TFTP
+#define CONFIG_SYS_DIRECT_NAND_TFTP
+
+/*****************************************************************************/
+
+#if 1
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_IDE_PREINIT	1	/* Use preinit IDE hook */
+#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#endif
+
+/*************************************************************************************************/
+
+#define CONFIG_CDP_DEVICE_ID		20
+#define CONFIG_CDP_DEVICE_ID_PREFIX	"NT"	/* netta */
+#define CONFIG_CDP_PORT_ID		"eth%d"
+#define CONFIG_CDP_CAPABILITIES		0x00000010
+#define CONFIG_CDP_VERSION		"u-boot 1.0" " " U_BOOT_DATE " " U_BOOT_TIME
+#define CONFIG_CDP_PLATFORM		"Intracom NetTA"
+#define CONFIG_CDP_TRIGGER		0x20020001
+#define CONFIG_CDP_POWER_CONSUMPTION	4300	/* 90 mA @ 48V */
+#define CONFIG_CDP_APPLIANCE_VLAN_TYPE	0x01	/* ipphone? */
+
+/*************************************************************************************************/
+
+#define CONFIG_AUTO_COMPLETE	1
+
+/*************************************************************************************************/
+
+#define CONFIG_CRC32_VERIFY	1
+
+/*************************************************************************************************/
+
+#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE	1
+
+/*************************************************************************************************/
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/NETTA2.h b/qemu/roms/u-boot/include/configs/NETTA2.h
new file mode 100644
index 000000000..55ae4b533
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/NETTA2.h
@@ -0,0 +1,654 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
+ * U-Boot port on NetTA4 board
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#if !defined(CONFIG_NETTA2_VERSION) || CONFIG_NETTA2_VERSION > 2
+#error Unsupported CONFIG_NETTA2 version
+#endif
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC870		1	/* This is a MPC885 CPU		*/
+#define CONFIG_NETTA2		1	/* ...on a NetTA2 board		*/
+
+#define	CONFIG_SYS_TEXT_BASE	0x40000000
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+
+/* #define CONFIG_XIN		 10000000 */
+#define CONFIG_XIN		 50000000
+/* #define MPC8XX_HZ		120000000 */
+#define MPC8XX_HZ		 66666666
+
+#define CONFIG_8xx_GCLK_FREQ	MPC8XX_HZ
+
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#undef	CONFIG_CLOCKS_IN_MHZ	/* clocks NOT passsed to Linux in MHz */
+
+#define CONFIG_PREBOOT	"echo;"
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND							\
+	"tftpboot; "								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
+	"bootm"
+
+#define CONFIG_SOURCE
+#define CONFIG_LOADS_ECHO	0	/* echo off for serial download	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+#define CONFIG_BOARD_SPECIFIC_LED	/* version has board specific leds */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_NISDOMAIN
+
+
+#undef CONFIG_MAC_PARTITION
+#undef CONFIG_DOS_PARTITION
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+#define	FEC_ENET		1	/* eth.c needs it that way... */
+#undef CONFIG_SYS_DISCOVER_PHY
+#define CONFIG_MII		1
+#define CONFIG_MII_INIT		1
+#define CONFIG_RMII		1	/* use RMII interface */
+
+#define CONFIG_ETHER_ON_FEC1	1
+#define CONFIG_FEC1_PHY		8	/* phy address of FEC */
+#define CONFIG_FEC1_PHY_NORXERR 1
+
+#define CONFIG_ETHER_ON_FEC2	1
+#define CONFIG_FEC2_PHY		4
+#define CONFIG_FEC2_PHY_NORXERR 1
+
+#define CONFIG_ENV_OVERWRITE	1	/* allow modification of vendor params */
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_CDP
+
+
+#define CONFIG_BOARD_EARLY_INIT_F	1
+#define CONFIG_MISC_INIT_R
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+
+#define CONFIG_SYS_HUSH_PARSER	1
+
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0300000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0700000	/* 3 ... 7 MB in DRAM	*/
+
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xFF000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x3000	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#if defined(DEBUG)
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#else
+#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#endif
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#if CONFIG_NETTA2_VERSION == 2
+#define CONFIG_SYS_FLASH_BASE4		0x40080000
+#endif
+
+#define CONFIG_SYS_RESET_ADDRESS   0x80000000
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#if CONFIG_NETTA2_VERSION == 1
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#elif CONFIG_NETTA2_VERSION == 2
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#endif
+#define CONFIG_SYS_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_SECT_SIZE	0x10000
+
+#define	CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x60000)
+#define CONFIG_ENV_OFFSET		0
+#define	CONFIG_ENV_SIZE		0x4000
+
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_SYS_FLASH_BASE + 0x70000)
+#define CONFIG_ENV_OFFSET_REDUND	0
+#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef	CONFIG_CAN_DRIVER
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
+#else	/* we must activate GPL5 in the SIUMCR for CAN */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ *
+ */
+
+#if CONFIG_XIN == 10000000
+
+#if MPC8XX_HZ == 120000000
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
+			 PLPRCR_TEXPS)
+#elif MPC8XX_HZ == 100000000
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
+			 PLPRCR_TEXPS)
+#elif MPC8XX_HZ == 50000000
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
+			 PLPRCR_TEXPS)
+#elif MPC8XX_HZ == 25000000
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
+			 PLPRCR_TEXPS)
+#elif MPC8XX_HZ == 40000000
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
+			 PLPRCR_TEXPS)
+#elif MPC8XX_HZ == 75000000
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
+			 PLPRCR_TEXPS)
+#else
+#error unsupported CPU freq for XIN = 10MHz
+#endif
+
+#elif CONFIG_XIN == 50000000
+
+#if MPC8XX_HZ == 120000000
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
+			 PLPRCR_TEXPS)
+#elif MPC8XX_HZ == 100000000
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
+			 PLPRCR_TEXPS)
+#elif MPC8XX_HZ ==  66666666
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
+			 PLPRCR_TEXPS)
+#else
+#error unsupported CPU freq for XIN = 50MHz
+#endif
+
+#else
+
+#error unsupported XIN freq
+#endif
+
+
+/*
+ *-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ *
+ * Note: When TBS == 0 the timebase is independent of current cpu clock.
+ */
+
+#define SCCR_MASK	SCCR_EBDF11
+#if MPC8XX_HZ > 66666666
+#define CONFIG_SYS_SCCR	(/* SCCR_TBS     | */ SCCR_CRQEN | \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00 | SCCR_EBDF01)
+#else
+#define CONFIG_SYS_SCCR	(/* SCCR_TBS     | */ SCCR_CRQEN | \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+#endif
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+/*#define	CONFIG_SYS_DER	0x2002000F*/
+#define CONFIG_SYS_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_BI | OR_SCY_5_CLK | OR_TRLX)
+
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
+
+#if CONFIG_NETTA2_VERSION == 2
+
+#define FLASH_BASE4_PRELIM	0x40080000	/* FLASH bank #1	*/
+
+#define CONFIG_SYS_OR4_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR4_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR4_PRELIM	((FLASH_BASE4_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
+
+#endif
+
+/*
+ * BR3 and OR3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE3_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define	SDRAM_MAX_SIZE		(256 << 20)	/* max 256MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CONFIG_SYS_OR_TIMING_SDRAM	(OR_CSNT_SAM | OR_G5LS)
+
+#define CONFIG_SYS_OR3_PRELIM	((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM)
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V)
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ *	gclk	  CPU clock (not bus clock!)
+ *	Trefresh  Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096  Rows from SDRAM example configuration
+ * 1000  factor s -> ms
+ *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
+ *    4  Number of refresh cycles per period
+ *   64  Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ * 50 MHz => 50.000.000 / Divider =  98
+ * 66 Mhz => 66.000.000 / Divider = 129
+ * 80 Mhz => 80.000.000 / Divider = 156
+ */
+
+#define CONFIG_SYS_MAMR_PTA		 234
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ */
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+/* 9 column SDRAM */
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+#define CONFIG_LAST_STAGE_INIT		/* needed to reset the damn phys */
+
+/****************************************************************/
+
+#define DSP_SIZE	0x00010000	/* 64K */
+#define NAND_SIZE	0x00010000	/* 64K */
+
+#define DSP_BASE	0xF1000000
+#define NAND_BASE	0xF1010000
+
+/*****************************************************************************/
+
+#define CONFIG_SYS_DIRECT_FLASH_TFTP
+
+/*****************************************************************************/
+
+#if CONFIG_NETTA2_VERSION == 1
+#define STATUS_LED_BIT		0x00000008		/* bit 28 */
+#elif CONFIG_NETTA2_VERSION == 2
+#define STATUS_LED_BIT		0x00000080		/* bit 24 */
+#endif
+
+#define STATUS_LED_PERIOD	(CONFIG_SYS_HZ / 2)
+#define STATUS_LED_STATE	STATUS_LED_BLINKING
+
+#define STATUS_LED_ACTIVE	0		/* LED on for bit == 0	*/
+#define STATUS_LED_BOOT		0		/* LED 0 used for boot status */
+
+#ifndef __ASSEMBLY__
+
+/* LEDs */
+
+/* led_id_t is unsigned int mask */
+typedef unsigned int led_id_t;
+
+#define __led_toggle(_msk) \
+	do { \
+		((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat ^= (_msk); \
+	} while(0)
+
+#define __led_set(_msk, _st) \
+	do { \
+		if ((_st)) \
+			((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat |= (_msk); \
+		else \
+			((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat &= ~(_msk); \
+	} while(0)
+
+#define __led_init(msk, st) __led_set(msk, st)
+
+#endif
+
+/***********************************************************************************************************
+
+ ----------------------------------------------------------------------------------------------
+
+   (V1) version 1 of the board
+   (V2) version 2 of the board
+
+ ----------------------------------------------------------------------------------------------
+
+   Pin definitions:
+
+ +------+----------------+--------+------------------------------------------------------------
+ |  #   | Name           | Type   | Comment
+ +------+----------------+--------+------------------------------------------------------------
+ | PA3  | SPIEN_MAX      | Output | MAX serial to uart chip select
+ | PA7  | DSP_INT        | Output | DSP interrupt
+ | PA10 | DSP_RESET      | Output | DSP reset
+ | PA14 | USBOE          | Output | USB (1)
+ | PA15 | USBRXD         | Output | USB (1)
+ | PB19 | BT_RTS         | Output | Bluetooth (0)
+ | PB23 | BT_CTS         | Output | Bluetooth (0)
+ | PB26 | SPIEN_SEP      | Output | Serial EEPROM chip select
+ | PB27 | SPICS_DISP     | Output | Display chip select
+ | PB28 | SPI_RXD_3V     | Input  | SPI Data Rx
+ | PB29 | SPI_TXD        | Output | SPI Data Tx
+ | PB30 | SPI_CLK        | Output | SPI Clock
+ | PC10 | DISPA0         | Output | Display A0
+ | PC11 | BACKLIGHT      | Output | Display backlit
+ | PC12 | SPI2RXD        | Input  | (V1) 2nd SPI RXD
+ |      | IO_RESET       | Output | (V2) General I/O reset
+ | PC13 | SPI2TXD        | Output | (V1) 2nd SPI TXD (V1)
+ |      | HOOK           | Input  | (V2) Hook input interrupt
+ | PC15 | SPI2CLK        | Output | (V1) 2nd SPI CLK
+ |      | F_RY_BY        | Input  | (V2) NAND F_RY_BY
+ | PE17 | F_ALE          | Output | NAND F_ALE
+ | PE18 | F_CLE          | Output | NAND F_CLE
+ | PE20 | F_CE           | Output | NAND F_CE
+ | PE24 | SPICS_SCOUT    | Output | (V1) Codec chip select
+ |      | LED            | Output | (V2) LED
+ | PE27 | SPICS_ER       | Output | External serial register CS
+ | PE28 | LEDIO1         | Output | (V1) LED
+ |      | BKBR1          | Input  | (V2) Keyboard input scan
+ | PE29 | LEDIO2         | Output | (V1) LED hook for A (TA2)
+ |      | BKBR2          | Input  | (V2) Keyboard input scan
+ | PE30 | LEDIO3         | Output | (V1) LED hook for A (TA2)
+ |      | BKBR3          | Input  | (V2) Keyboard input scan
+ | PE31 | F_RY_BY        | Input  | (V1) NAND F_RY_BY
+ |      | BKBR4          | Input  | (V2) Keyboard input scan
+ +------+----------------+--------+---------------------------------------------------
+
+ ----------------------------------------------------------------------------------------------
+
+   Serial register input:
+
+ +------+----------------+------------------------------------------------------------
+ |  #   | Name           | Comment
+ +------+----------------+------------------------------------------------------------
+ |    4 | HOOK           | Hook switch
+ |    5 | BT_LINK        | Bluetooth link status
+ |    6 | HOST_WAKE      | Bluetooth host wake up
+ |    7 | OK_ETH         | Cisco inline power OK status
+ +------+----------------+------------------------------------------------------------
+
+ ----------------------------------------------------------------------------------------------
+
+ Chip selects:
+
+ +------+----------------+------------------------------------------------------------
+ |  #   | Name           | Comment
+ +------+----------------+------------------------------------------------------------
+ | CS0  | CS0            | Boot flash
+ | CS1  | CS_FLASH       | NAND flash
+ | CS2  | CS_DSP         | DSP
+ | CS3  | DCS_DRAM       | DRAM
+ | CS4  | CS_FLASH2      | (V2) 2nd flash
+ +------+----------------+------------------------------------------------------------
+
+ ----------------------------------------------------------------------------------------------
+
+ Interrupts:
+
+ +------+----------------+------------------------------------------------------------
+ |  #   | Name           | Comment
+ +------+----------------+------------------------------------------------------------
+ | IRQ1 | IRQ_DSP        | DSP interrupt
+ | IRQ3 | S_INTER        | DUSLIC ???
+ | IRQ4 | F_RY_BY        | NAND
+ | IRQ7 | IRQ_MAX        | MAX 3100 interrupt
+ +------+----------------+------------------------------------------------------------
+
+ ----------------------------------------------------------------------------------------------
+
+ Interrupts on PCMCIA pins:
+
+ +------+----------------+------------------------------------------------------------
+ |  #   | Name           | Comment
+ +------+----------------+------------------------------------------------------------
+ | IP_A0| PHY1_LINK      | Link status changed for #1 Ethernet interface
+ | IP_A1| PHY2_LINK      | Link status changed for #2 Ethernet interface
+ | IP_A2| RMII1_MDINT    | PHY interrupt for #1
+ | IP_A3| RMII2_MDINT    | PHY interrupt for #2
+ | IP_A5| HOST_WAKE      | (V2) Bluetooth host wake
+ | IP_A6| OK_ETH         | (V2) Cisco inline power OK
+ +------+----------------+------------------------------------------------------------
+
+**************************************************************************************************/
+
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV		1
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE	1
+#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE	1
+
+/*************************************************************************************************/
+
+/* use board specific hardware */
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+#define CONFIG_HW_WATCHDOG
+
+/*************************************************************************************************/
+
+#define CONFIG_CDP_DEVICE_ID		20
+#define CONFIG_CDP_DEVICE_ID_PREFIX	"NT"	/* netta2 */
+#define CONFIG_CDP_PORT_ID		"eth%d"
+#define CONFIG_CDP_CAPABILITIES		0x00000010
+#define CONFIG_CDP_VERSION		"u-boot" " " U_BOOT_DATE " " U_BOOT_TIME
+#define CONFIG_CDP_PLATFORM		"Intracom NetTA2"
+#define CONFIG_CDP_TRIGGER		0x20020001
+#define CONFIG_CDP_POWER_CONSUMPTION	4300	/* 90 mA @ 48V */
+#define CONFIG_CDP_APPLIANCE_VLAN_TYPE	0x01	/* ipphone ? */
+
+/*************************************************************************************************/
+
+#define CONFIG_AUTO_COMPLETE	1
+
+/*************************************************************************************************/
+
+#define CONFIG_CRC32_VERIFY	1
+
+/*************************************************************************************************/
+
+#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE	1
+
+/*************************************************************************************************/
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/NETVIA.h b/qemu/roms/u-boot/include/configs/NETVIA.h
new file mode 100644
index 000000000..4a0fa9e11
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/NETVIA.h
@@ -0,0 +1,435 @@
+/*
+ * (C) Copyright 2000-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
+ * U-Boot port on NetVia board
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC850		1	/* This is a MPC850 CPU		*/
+#define CONFIG_NETVIA		1	/* ...on a NetVia board		*/
+
+#define	CONFIG_SYS_TEXT_BASE	0x40000000
+
+#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#else
+#define CONFIG_8xx_CONS_NONE
+#define CONFIG_MAX3100_SERIAL
+#endif
+
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+
+#define CONFIG_XIN		10000000
+#define CONFIG_8xx_GCLK_FREQ	80000000
+
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#undef	CONFIG_CLOCKS_IN_MHZ	/* clocks NOT passsed to Linux in MHz */
+
+#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND							\
+	"tftpboot; "								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
+	"bootm"
+
+#define CONFIG_LOADS_ECHO	0	/* echo off for serial download	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+
+#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
+#define CONFIG_BOARD_SPECIFIC_LED	/* version has board specific leds */
+#endif
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_NISDOMAIN
+
+
+#undef CONFIG_MAC_PARTITION
+#undef CONFIG_DOS_PARTITION
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+
+#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
+/* #define CONFIG_CMD_NAND */ /* disabled */
+#endif
+
+
+#define CONFIG_BOARD_EARLY_INIT_F 1
+#define CONFIG_MISC_INIT_R
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0300000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0700000	/* 3 ... 7 MB in DRAM	*/
+
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xFF000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x3000	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#if defined(DEBUG)
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#else
+#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#endif
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_SECT_SIZE	0x10000
+
+#define	CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x60000)
+#define	CONFIG_ENV_SIZE		0x4000
+
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_SYS_FLASH_BASE + 0x70000)
+#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef	CONFIG_CAN_DRIVER
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
+#else	/* we must activate GPL5 in the SIUMCR for CAN */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ *
+ *
+ *-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+
+#define SCCR_MASK	SCCR_EBDF11
+
+#if CONFIG_8xx_GCLK_FREQ == 50000000
+
+#define CONFIG_SYS_PLPRCR	( ((5 - 1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+#define CONFIG_SYS_SCCR	(SCCR_TBS     | \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+#elif CONFIG_8xx_GCLK_FREQ == 80000000
+
+#define CONFIG_SYS_PLPRCR	( ((8 - 1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+#define CONFIG_SYS_SCCR	(SCCR_TBS     | \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00 | SCCR_EBDF01)
+
+#endif
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+/*#define	CONFIG_SYS_DER	0x2002000F*/
+#define CONFIG_SYS_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_BI | OR_SCY_5_CLK | OR_TRLX)
+
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
+
+/*
+ * BR3 and OR3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE3_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CONFIG_SYS_OR_TIMING_SDRAM	(OR_CSNT_SAM | OR_G5LS)
+
+#define CONFIG_SYS_OR3_PRELIM	((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM)
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V)
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CONFIG_SYS_MAMR_PTA	208
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 9 column SDRAM */
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+/* Ethernet at SCC2 */
+#define CONFIG_SCC2_ENET
+
+/****************************************************************/
+
+#define DSP_SIZE	0x00010000	/* 64K */
+#define FPGA_SIZE	0x00010000	/* 64K */
+
+#define DSP0_BASE	0xF1000000
+#define DSP1_BASE	(DSP0_BASE + DSP_SIZE)
+#define FPGA_BASE	(DSP1_BASE + DSP_SIZE)
+
+#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
+
+#define ER_SIZE		0x00010000	/* 64K */
+#define ER_BASE		(FPGA_BASE + FPGA_SIZE)
+
+#define NAND_SIZE	0x00010000	/* 64K */
+#define NAND_BASE	(ER_BASE + ER_SIZE)
+
+#endif
+
+/****************************************************************/
+
+#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
+
+#define STATUS_LED_BIT		0x00000001		/* bit 31 */
+#define STATUS_LED_PERIOD	(CONFIG_SYS_HZ / 2)
+#define STATUS_LED_STATE	STATUS_LED_BLINKING
+
+#define STATUS_LED_BIT1		0x00000002		/* bit 30 */
+#define STATUS_LED_PERIOD1	(CONFIG_SYS_HZ / 2)
+#define STATUS_LED_STATE1	STATUS_LED_OFF
+
+#define STATUS_LED_ACTIVE	0		/* LED on for bit == 0	*/
+#define STATUS_LED_BOOT		0		/* LED 0 used for boot status */
+
+#endif
+
+
+/*****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
+
+/* LEDs */
+
+/* last value written to the external register; we cannot read back */
+extern unsigned int last_er_val;
+
+/* led_id_t is unsigned long mask */
+typedef unsigned int led_id_t;
+
+static inline void __led_init(led_id_t mask, int state)
+{
+	unsigned int new_er_val;
+
+	if (state)
+		new_er_val = last_er_val & ~mask;
+	else
+		new_er_val = last_er_val |  mask;
+
+	*(volatile unsigned int *)ER_BASE = new_er_val;
+	last_er_val = new_er_val;
+}
+
+static inline void __led_toggle(led_id_t mask)
+{
+	unsigned int new_er_val;
+
+	new_er_val = last_er_val ^ mask;
+	*(volatile unsigned int *)ER_BASE = new_er_val;
+	last_er_val = new_er_val;
+}
+
+static inline void __led_set(led_id_t mask, int state)
+{
+	unsigned int new_er_val;
+
+	if (state)
+		new_er_val = last_er_val & ~mask;
+	else
+		new_er_val = last_er_val |  mask;
+
+	*(volatile unsigned int *)ER_BASE = new_er_val;
+	last_er_val = new_er_val;
+}
+
+/* MAX3100 console */
+#define MAX3100_SPI_RXD_PORT	(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
+#define MAX3100_SPI_RXD_BIT	0x00000008
+
+#define MAX3100_SPI_TXD_PORT	(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
+#define MAX3100_SPI_TXD_BIT	0x00000004
+
+#define MAX3100_SPI_CLK_PORT	(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
+#define MAX3100_SPI_CLK_BIT	0x00000002
+
+#define MAX3100_CS_PORT		(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat)
+#define MAX3100_CS_BIT		0x0010
+
+#endif
+
+#endif
+
+/*************************************************************************************************/
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/NSCU.h b/qemu/roms/u-boot/include/configs/NSCU.h
new file mode 100644
index 000000000..a9c649abe
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/NSCU.h
@@ -0,0 +1,463 @@
+/*
+ * (C) Copyright 2000-2008
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC855		1	/* This is a MPC855 CPU		*/
+#define CONFIG_TQM855M		1	/* ...on a TQM8xxM module	*/
+#define CONFIG_NSCU		1
+
+#define	CONFIG_SYS_TEXT_BASE	0x40000000
+
+#define	CONFIG_8xx_CONS_SCC1	1	/* Console is on SMC1		*/
+#define CONFIG_SYS_SMC_RXBUFLEN	128
+#define CONFIG_SYS_MAXIDLE	10
+
+#define	CONFIG_66MHz		1	/* running at 66 MHz, 1:1 clock	*/
+
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_8xx\0"					\
+	"hostname=NSCU\0"						\
+	"bootfile=${hostname}/uImage\0"					\
+	"kernel_addr=40080000\0"					\
+	"ramdisk_addr=40180000\0"					\
+	"u-boot=${hostname}/u-image.bin\0"				\
+	"load=tftp 200000 ${u-boot}\0"					\
+	"update=prot off 40000000 +${filesize};"			\
+		"era 40000000 +${filesize};"				\
+		"cp.b 200000 40000000 ${filesize};"			\
+		"sete filesize;save\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_MISC_INIT_R	  1
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+#define	CONFIG_ISP1362_USB		/* ISP1362 USB OTG controller	*/
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
+
+#define CONFIG_NETCONSOLE
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history
+*/
+#define	CONFIG_SYS_HUSH_PARSER		1	/* use "hush" command parser	*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#else
+#define	CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
+#endif
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+
+/* use CFI flash driver */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	71	/* max number of sectors on one chip */
+
+#define	CONFIG_ENV_IS_IN_FLASH	1
+#define	CONFIG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
+#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef	CONFIG_CAN_DRIVER
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#else	/* we must activate GPL5 in the SIUMCR for CAN */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ */
+#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CONFIG_SYS_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+/* NSCU use both slots, SLOT_A as "primary". */
+#define	CONFIG_PCMCIA_SLOT_A 1
+
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
+#define PCMCIA_MEM_WIN_NO	8 /* override default 4 in pcmcia.h */
+#define	PCMCIA_SOCKETS_NO	2 /* we have two sockets */
+#undef	NSCU_OE_INV		/* PCMCIA_GCRX_CXOE was inverted on early boards */
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_IDE_PREINIT	1	/* Use preinit IDE hook */
+#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CONFIG_SYS_IDE_MAXBUS		2	/* max. 2 IDE buses		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	4	/* max. 2 drives per IDE bus	*/
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE1_OFFSET	(4 * CONFIG_SYS_PCMCIA_MEM_SIZE) /* starts @ 4th window */
+
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
+
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
+#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
+
+#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#ifndef	CONFIG_CAN_DRIVER
+#define	CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
+#define	CONFIG_SYS_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CONFIG_SYS_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CONFIG_SYS_OR3_CAN		(CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CONFIG_SYS_BR3_CAN		((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
+					BR_PS_8 | BR_MS_UPMB | BR_V )
+#endif	/* CONFIG_CAN_DRIVER */
+
+#ifdef	CONFIG_ISP1362_USB
+#define	CONFIG_SYS_ISP1362_BASE	0xD0000000	/* ISP1362 mapped at 0xD0000000 */
+#define CONFIG_SYS_ISP1362_OR_AM	0xFFFF8000	/* 32 kB address mask		*/
+#define CONFIG_SYS_OR5_ISP1362		(CONFIG_SYS_ISP1362_OR_AM | OR_CSNT_SAM | \
+				 OR_ACS_DIV2       | OR_BI       | OR_SCY_5_CLK)
+#define CONFIG_SYS_BR5_ISP1362		((CONFIG_SYS_ISP1362_BASE & BR_BA_MSK) | \
+				 BR_PS_16          | BR_MS_GPCM | BR_V )
+#endif	/* CONFIG_ISP1362_USB */
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ *	gclk	  CPU clock (not bus clock!)
+ *	Trefresh  Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096  Rows from SDRAM example configuration
+ * 1000  factor s -> ms
+ *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
+ *    4  Number of refresh cycles per period
+ *   64  Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ * 50 MHz => 50.000.000 / Divider =  98
+ * 66 Mhz => 66.000.000 / Divider = 129
+ * 80 Mhz => 80.000.000 / Divider = 156
+ */
+
+#define CONFIG_SYS_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CONFIG_SYS_MAMR_PTA	98
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ */
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+#undef CONFIG_SCC1_ENET
+#define CONFIG_FEC_ENET
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_HWCONFIG		1
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/OCRTC.h b/qemu/roms/u-boot/include/configs/OCRTC.h
new file mode 100644
index 000000000..4680afee0
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/OCRTC.h
@@ -0,0 +1,285 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_OCRTC		1	/* ...on a OCRTC board		*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFD0000
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+
+#define CONFIG_SYS_CLK_FREQ	33000000 /* external frequency to pll	*/
+
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND "go fff00100"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_PPC4xx_EMAC
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_EEPROM
+
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CONFIG_SYS_BASE_BAUD	    691200
+
+/* The following table includes the supported baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_HOST PCI_HOST_AUTO	/* select pci host function	*/
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+					/* resource configuration	*/
+
+#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
+
+#define CONFIG_PCI_BOOTDELAY	1	/* enable pci bootdelay variable*/
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0410	/* PCI Device ID: OCRTC		*/
+#define CONFIG_SYS_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
+#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CONFIG_SYS_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CONFIG_SYS_PCI_PTM2LA	0xffc00000	/* point to flash		*/
+#define CONFIG_SYS_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
+#define CONFIG_SYS_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFFD0000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(192 * 1024)	/* Reserve 192 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#if 0 /* Use NVRAM for environment variables */
+/*-----------------------------------------------------------------------
+ * NVRAM organization
+ */
+#define CONFIG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
+#define CONFIG_SYS_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
+#define CONFIG_ENV_SIZE		0x1000		/* Size of Environment vars	*/
+#define CONFIG_ENV_ADDR		\
+	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE)	/* Env	*/
+#define CONFIG_SYS_NVRAM_VXWORKS_OFFS	0x6900		/* Offset for VxWorks eth-addr	*/
+
+#else /* Use EEPROM for environment variables */
+
+#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CONFIG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
+#define CONFIG_ENV_SIZE		0x300	/* 768 bytes may be used for env vars */
+				   /* total size of a CAT24WC08 is 1024 bytes */
+#endif
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC08) for environment
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last 4 bits of the address	*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0xFF800000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0xFFC00000	/* FLASH bank #1	*/
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash Bank 0) initialization					*/
+#define CONFIG_SYS_EBC_PB0AP		0x92015480
+#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (Flash Bank 1) initialization					*/
+#define CONFIG_SYS_EBC_PB1AP		0x92015480
+#define CONFIG_SYS_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 2 (PLD - FPGA-boot) initialization				*/
+#define CONFIG_SYS_EBC_PB2AP		0x02015480  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
+#define CONFIG_SYS_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 3 (PLD - OSL) initialization					*/
+#define CONFIG_SYS_EBC_PB3AP		0x02015480  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
+#define CONFIG_SYS_EBC_PB3CR		0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 4 (Spartan2 1) initialization					*/
+#define CONFIG_SYS_EBC_PB4AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
+#define CONFIG_SYS_EBC_PB4CR		0xF209C000  /* BAS=0xF20,BS=16MB,BU=R/W,BW=32bit*/
+
+/* Memory Bank 5 (Spartan2 2) initialization					*/
+#define CONFIG_SYS_EBC_PB5AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
+#define CONFIG_SYS_EBC_PB5CR		0xF309C000  /* BAS=0xF30,BS=16MB,BU=R/W,BW=32bit*/
+
+/* Memory Bank 6 (Virtex 1) initialization					*/
+#define CONFIG_SYS_EBC_PB6AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
+#define CONFIG_SYS_EBC_PB6CR		0xF409A000  /* BAS=0xF40,BS=16MB,BU=R/W,BW=16bit*/
+
+/* Memory Bank 7 (Virtex 2) initialization					*/
+#define CONFIG_SYS_EBC_PB7AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
+#define CONFIG_SYS_EBC_PB7CR		0xF509A000  /* BAS=0xF50,BS=16MB,BU=R/W,BW=16bit*/
+
+
+#define CONFIG_SYS_VXWORKS_MAC_PTR	0x00000000	/* Pass Ethernet MAC to VxWorks */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CONFIG_SYS_TEMP_STACK_OCM	  1
+
+/* On Chip Memory location */
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/P1010RDB.h b/qemu/roms/u-boot/include/configs/P1010RDB.h
new file mode 100644
index 000000000..d612a8b9c
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/P1010RDB.h
@@ -0,0 +1,963 @@
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * P010 RDB board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifdef CONFIG_36BIT
+#define CONFIG_PHYS_64BIT
+#endif
+
+#define CONFIG_P1010
+#define CONFIG_E500			/* BOOKE e500 family */
+#include <asm/config_mpc85xx.h>
+#define CONFIG_NAND_FSL_IFC
+
+#ifdef CONFIG_SDCARD
+#define CONFIG_SPL
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_MMC_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_FSL_LAW                 /* Use common FSL init code */
+#define CONFIG_SYS_TEXT_BASE		0x11001000
+#define CONFIG_SPL_TEXT_BASE		0xD0001000
+#define CONFIG_SPL_PAD_TO		0x18000
+#define CONFIG_SPL_MAX_SIZE		(96 * 1024)
+#define CONFIG_SYS_MMC_U_BOOT_SIZE	(512 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_DST	(0x11000000)
+#define CONFIG_SYS_MMC_U_BOOT_START	(0x11000000)
+#define CONFIG_SYS_MMC_U_BOOT_OFFS	(96 << 10)
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#define CONFIG_SPL_MMC_BOOT
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_COMMON_INIT_DDR
+#endif
+#endif
+
+#ifdef CONFIG_SPIFLASH
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_RAMBOOT_SPIFLASH
+#define CONFIG_SYS_TEXT_BASE		0x11000000
+#define CONFIG_RESET_VECTOR_ADDRESS	0x1107fffc
+#else
+#define CONFIG_SPL
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_FSL_LAW         /* Use common FSL init code */
+#define CONFIG_SYS_TEXT_BASE			0x11001000
+#define CONFIG_SPL_TEXT_BASE			0xD0001000
+#define CONFIG_SPL_PAD_TO			0x18000
+#define CONFIG_SPL_MAX_SIZE			(96 * 1024)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE	(512 << 10)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST		(0x11000000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_START	(0x11000000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS	(96 << 10)
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#define CONFIG_SPL_SPI_BOOT
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_COMMON_INIT_DDR
+#endif
+#endif
+#endif
+
+#ifdef CONFIG_NAND
+#define CONFIG_SPL
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BOOT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+
+#define CONFIG_SYS_TEXT_BASE		0x00201000
+#define CONFIG_SPL_TEXT_BASE		0xFFFFE000
+#define CONFIG_SPL_MAX_SIZE		8192
+#define CONFIG_SPL_RELOC_TEXT_BASE	0x00100000
+#define CONFIG_SPL_RELOC_STACK		0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	((768 << 10) - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_DST	(0x00200000 - CONFIG_SPL_MAX_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0
+#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#else
+#define CONFIG_TPL
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SPL_NAND_BOOT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_NAND_INIT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SPL_MAX_SIZE		(128 << 10)
+#define CONFIG_SPL_TEXT_BASE		0xD0001000
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(576 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	(0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_START	(0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	((128 + 128) << 10)
+#elif defined(CONFIG_SPL_BUILD)
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TEXT_BASE		0xff800000
+#define CONFIG_SPL_MAX_SIZE		8192
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(128 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	0xD0000000
+#define CONFIG_SYS_NAND_U_BOOT_START	0xD0000000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(128 << 10)
+#endif
+#define CONFIG_SPL_PAD_TO	0x20000
+#define CONFIG_TPL_PAD_TO	0x20000
+#define CONFIG_SPL_TARGET	"u-boot-with-spl.bin"
+#define CONFIG_SYS_TEXT_BASE	0x11001000
+#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#endif
+#endif
+
+#ifdef CONFIG_NAND_SECBOOT	/* NAND Boot */
+#define CONFIG_RAMBOOT_NAND
+#define CONFIG_SYS_TEXT_BASE		0x11000000
+#define CONFIG_RESET_VECTOR_ADDRESS	0x110bfffc
+#endif
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE		0xeff40000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE			/* BOOKE */
+#define CONFIG_E500			/* BOOKE e500 family */
+#define CONFIG_FSL_IFC			/* Enable IFC Support */
+#define CONFIG_SYS_HAS_SERDES		/* common SERDES init code */
+
+#define CONFIG_PCI			/* Enable PCI/PCIE */
+#if defined(CONFIG_PCI)
+#define CONFIG_PCIE1			/* PCIE controler 1 (slot 1) */
+#define CONFIG_PCIE2			/* PCIE controler 2 (slot 2) */
+#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_FSL_PCIE_RESET		/* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
+
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+
+#define CONFIG_E1000			/*  E1000 pci Ethernet card*/
+
+/*
+ * PCI Windows
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+/* controller 1, Slot 1, tgtid 1, Base address a000 */
+#define CONFIG_SYS_PCIE1_NAME		"mini PCIe Slot"
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#else
+#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0x80000000
+#endif
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc00000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xfffc00000ull
+#else
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xffc00000
+#endif
+
+/* controller 2, Slot 2, tgtid 2, Base address 9000 */
+#if defined(CONFIG_P1010RDB_PA)
+#define CONFIG_SYS_PCIE2_NAME		"PCIe Slot"
+#elif defined(CONFIG_P1010RDB_PB)
+#define CONFIG_SYS_PCIE2_NAME		"mini PCIe Slot"
+#endif
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xc0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
+#else
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
+#endif
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xffc10000
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xfffc10000ull
+#else
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
+#endif
+
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif
+
+#define CONFIG_FSL_LAW			/* Use common FSL init code */
+#define CONFIG_TSEC_ENET
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_DDR_CLK_FREQ	66666666 /* DDRCLK on P1010 RDB */
+#define CONFIG_SYS_CLK_FREQ	66666666 /* SYSCLK for P1010 RDB */
+
+#define CONFIG_MISC_INIT_R
+#define CONFIG_HWCONFIG
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* toggle branch predition */
+
+#define CONFIG_ADDR_STREAMING		/* toggle addr streaming */
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP			1
+#define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
+#endif
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x1fffffff
+#define CONFIG_PANIC_HANG		/* do not reset board on panic */
+
+/* DDR Setup */
+#define CONFIG_SYS_FSL_DDR3
+#define CONFIG_SYS_DDR_RAW_TIMING
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_SPD_BUS_NUM		1
+#define SPD_EEPROM_ADDRESS		0x52
+
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_sdram_size(void);
+#endif
+#define CONFIG_SYS_SDRAM_SIZE		get_sdram_size() /* DDR size */
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	1
+
+/* DDR3 Controller Settings */
+#define CONFIG_SYS_DDR_CS0_BNDS		0x0000003f
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80014302
+#define CONFIG_SYS_DDR_CS0_CONFIG_2	0x00000000
+#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
+#define CONFIG_SYS_DDR_INIT_ADDR	0x00000000
+#define CONFIG_SYS_DDR_INIT_EXT_ADDR	0x00000000
+#define CONFIG_SYS_DDR_MODE_CONTROL	0x00000000
+#define CONFIG_SYS_DDR_ZQ_CONTROL	0x89080600
+#define CONFIG_SYS_DDR_SR_CNTR		0x00000000
+#define CONFIG_SYS_DDR_RCW_1		0x00000000
+#define CONFIG_SYS_DDR_RCW_2		0x00000000
+#define CONFIG_SYS_DDR_CONTROL		0xc70c0008      /* Type = DDR3  */
+#define CONFIG_SYS_DDR_CONTROL_2	0x24401000
+#define CONFIG_SYS_DDR_TIMING_4		0x00000001
+#define CONFIG_SYS_DDR_TIMING_5		0x03402400
+
+#define CONFIG_SYS_DDR_TIMING_3_800	0x00030000
+#define CONFIG_SYS_DDR_TIMING_0_800	0x00110104
+#define CONFIG_SYS_DDR_TIMING_1_800	0x6f6b8644
+#define CONFIG_SYS_DDR_TIMING_2_800	0x0FA888CF
+#define CONFIG_SYS_DDR_CLK_CTRL_800	0x03000000
+#define CONFIG_SYS_DDR_MODE_1_800	0x00441420
+#define CONFIG_SYS_DDR_MODE_2_800	0x00000000
+#define CONFIG_SYS_DDR_INTERVAL_800	0x0C300100
+#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
+
+/* settings for DDR3 at 667MT/s */
+#define CONFIG_SYS_DDR_TIMING_3_667		0x00010000
+#define CONFIG_SYS_DDR_TIMING_0_667		0x00110004
+#define CONFIG_SYS_DDR_TIMING_1_667		0x5d59e544
+#define CONFIG_SYS_DDR_TIMING_2_667		0x0FA890CD
+#define CONFIG_SYS_DDR_CLK_CTRL_667		0x03000000
+#define CONFIG_SYS_DDR_MODE_1_667		0x00441210
+#define CONFIG_SYS_DDR_MODE_2_667		0x00000000
+#define CONFIG_SYS_DDR_INTERVAL_667		0x0a280000
+#define CONFIG_SYS_DDR_WRLVL_CONTROL_667	0x8675F608
+
+#define CONFIG_SYS_CCSRBAR			0xffe00000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW		CONFIG_SYS_CCSRBAR
+
+/* Don't relocate CCSRBAR while in NAND_SPL */
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#endif
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000	0x3fff_ffff	DDR			1G cacheable
+ * 0x8000_0000  0xbfff_ffff	PCI Express Mem		1.5G non-cacheable
+ * 0xffc0_0000  0xffc3_ffff	PCI IO range		256k non-cacheable
+ *
+ * Localbus non-cacheable
+ * 0xff80_0000	0xff8f_ffff	NAND Flash		1M non-cacheable
+ * 0xffb0_0000	0xffbf_ffff	Board CPLD		1M non-cacheable
+ * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K Cacheable TLB0
+ * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
+ */
+
+/*
+ * IFC Definitions
+ */
+/* NOR Flash on IFC */
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_NO_FLASH
+#endif
+
+#define CONFIG_SYS_FLASH_BASE		0xee000000
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* 32M */
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+#else
+#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+#endif
+
+#define CONFIG_SYS_NOR_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(32*1024*1024)
+#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(7)
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR_FTIM0	FTIM0_NOR_TACSE(0x4) | \
+				FTIM0_NOR_TEADC(0x5) | \
+				FTIM0_NOR_TEAHC(0x5)
+#define CONFIG_SYS_NOR_FTIM1	FTIM1_NOR_TACO(0x1e) | \
+				FTIM1_NOR_TRAD_NOR(0x0f)
+#define CONFIG_SYS_NOR_FTIM2	FTIM2_NOR_TCS(0x4) | \
+				FTIM2_NOR_TCH(0x4) | \
+				FTIM2_NOR_TWP(0x1c)
+#define CONFIG_SYS_NOR_FTIM3	0x0
+
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS}
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+/* CFI for NOR Flash */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/* NAND Flash on IFC */
+#define CONFIG_SYS_NAND_BASE		0xff800000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_NAND_BASE_PHYS	0xfff800000ull
+#else
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#endif
+
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITION
+#define CONFIG_CMD_MTDPARTS
+#define MTDIDS_DEFAULT			"nand0=ff800000.flash"
+#define MTDPARTS_DEFAULT		\
+	"mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
+
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8	\
+				| CSPR_MSEL_NAND	\
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+
+#if defined(CONFIG_P1010RDB_PA)
+#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */ \
+				| CSOR_NAND_RAL_2	/* RAL = 2 Bytes */ \
+				| CSOR_NAND_PGS_512	/* Page Size = 512b */ \
+				| CSOR_NAND_SPRZ_16	/* Spare size = 16 */ \
+				| CSOR_NAND_PB(32))	/* 32 Pages Per Block */
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(16 * 1024)
+
+#elif defined(CONFIG_P1010RDB_PB)
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_SYS_NAND_CSOR   (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
+				| CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
+				| CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
+				| CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
+				| CSOR_NAND_PB(128))  /*Pages Per Block = 128 */
+#define CONFIG_SYS_NAND_BLOCK_SIZE     (512 * 1024)
+#endif
+
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+
+#if defined(CONFIG_P1010RDB_PA)
+/* NAND Flash Timing Params */
+#define CONFIG_SYS_NAND_FTIM0		FTIM0_NAND_TCCST(0x01) | \
+					FTIM0_NAND_TWP(0x0C)   | \
+					FTIM0_NAND_TWCHT(0x04) | \
+					FTIM0_NAND_TWH(0x05)
+#define CONFIG_SYS_NAND_FTIM1		FTIM1_NAND_TADLE(0x1d) | \
+					FTIM1_NAND_TWBE(0x1d)  | \
+					FTIM1_NAND_TRR(0x07)   | \
+					FTIM1_NAND_TRP(0x0c)
+#define CONFIG_SYS_NAND_FTIM2		FTIM2_NAND_TRAD(0x0c) | \
+					FTIM2_NAND_TREH(0x05) | \
+					FTIM2_NAND_TWHRE(0x0f)
+#define CONFIG_SYS_NAND_FTIM3		FTIM3_NAND_TWW(0x04)
+
+#elif defined(CONFIG_P1010RDB_PB)
+/* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0  (FTIM0_NAND_TCCST(0x07)| \
+					FTIM0_NAND_TWP(0x18)   | \
+					FTIM0_NAND_TWCHT(0x07) | \
+					FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1  (FTIM1_NAND_TADLE(0x32)| \
+					FTIM1_NAND_TWBE(0x39)  | \
+					FTIM1_NAND_TRR(0x0e)   | \
+					FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2  (FTIM2_NAND_TRAD(0x0f) | \
+					FTIM2_NAND_TREH(0x0a)  | \
+					FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3	0x0
+#endif
+
+#define CONFIG_SYS_NAND_DDR_LAW		11
+
+/* Set up IFC registers for boot location NOR/NAND */
+#if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
+#endif
+
+/* CPLD on IFC */
+#define CONFIG_SYS_CPLD_BASE		0xffb00000
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_CPLD_BASE_PHYS	0xfffb00000ull
+#else
+#define CONFIG_SYS_CPLD_BASE_PHYS	CONFIG_SYS_CPLD_BASE
+#endif
+
+#define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 \
+				| CSPR_MSEL_GPCM \
+				| CSPR_V)
+#define CONFIG_SYS_AMASK3		IFC_AMASK(64*1024)
+#define CONFIG_SYS_CSOR3		0x0
+/* CPLD Timing parameters for IFC CS3 */
+#define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
+					FTIM0_GPCM_TEADC(0x0e) | \
+					FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \
+					FTIM1_GPCM_TRAD(0x1f))
+#define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
+					FTIM2_GPCM_TCH(0x0) | \
+					FTIM2_GPCM_TWP(0x1f))
+#define CONFIG_SYS_CS3_FTIM3		0x0
+
+#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
+	defined(CONFIG_RAMBOOT_NAND)
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#else
+#undef CONFIG_SYS_RAMBOOT
+#endif
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
+#if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT)
+#define CONFIG_A003399_NOR_WORKAROUND
+#endif
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_F	/* Call board_pre_init */
+#define CONFIG_BOARD_EARLY_INIT_R
+
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000 /* stack in RAM */
+#define CONFIG_SYS_INIT_RAM_END		0x00004000 /* End of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END \
+						- GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc*/
+
+/*
+ * Config the L2 Cache as L2 SRAM
+ */
+#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_INIT_L2_ADDR		0xD0000000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE		(256 << 10)
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE	0xD0001000
+#define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE	(16 << 10)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(128 << 10)
+#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 96 * 1024)
+#elif defined(CONFIG_NAND)
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SYS_INIT_L2_ADDR		0xD0000000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE		(256 << 10)
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE	0xD0001000
+#define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(48 << 10)
+#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
+#else
+#define CONFIG_SYS_INIT_L2_ADDR		0xD0000000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE		(256 << 10)
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE	(CONFIG_SYS_INIT_L2_END - 0x3000)
+#define CONFIG_SPL_RELOC_STACK		((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
+#endif
+#endif
+#endif
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX	1
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
+
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	/* determine from environment */
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+#define I2C_PCA9557_ADDR1		0x18
+#define I2C_PCA9557_ADDR2		0x19
+#define I2C_PCA9557_BUS_NUM		0
+
+/* I2C EEPROM */
+#if defined(CONFIG_P1010RDB_PB)
+#define CONFIG_ID_EEPROM
+#ifdef CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#endif
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+#define CONFIG_SYS_EEPROM_BUS_NUM	0
+#define MAX_NUM_PORTS			9 /* for 128Bytes EEPROM */
+#endif
+/* enable read and write access to EEPROM */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+/* RTC */
+#define CONFIG_RTC_PT7C4338
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68
+
+#define CONFIG_CMD_I2C
+
+/*
+ * SPI interface will not be available in case of NAND boot SPI CS0 will be
+ * used for SLIC
+ */
+#if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT)
+/* eSPI - Enhanced SPI */
+#define CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED		10000000
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
+#endif
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_MII			/* MII PHY management */
+#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"eTSEC2"
+#define CONFIG_TSEC3	1
+#define CONFIG_TSEC3_NAME	"eTSEC3"
+
+#define TSEC1_PHY_ADDR		1
+#define TSEC2_PHY_ADDR		0
+#define TSEC3_PHY_ADDR		2
+
+#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC3_PHYIDX		0
+
+#define CONFIG_ETHPRIME		"eTSEC1"
+
+#define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
+
+/* TBI PHY configuration for SGMII mode */
+#define CONFIG_TSEC_TBICR_SETTINGS ( \
+		TBICR_PHY_RESET \
+		| TBICR_ANEG_ENABLE \
+		| TBICR_FULL_DUPLEX \
+		| TBICR_SPEED1_SET \
+		)
+
+#endif	/* CONFIG_TSEC_ENET */
+
+
+/* SATA */
+#define CONFIG_FSL_SATA
+#define CONFIG_FSL_SATA_V2
+#define CONFIG_LIBATA
+
+#ifdef CONFIG_FSL_SATA
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
+
+#define CONFIG_CMD_SATA
+#define CONFIG_LBA48
+#endif /* #ifdef CONFIG_FSL_SATA  */
+
+#define CONFIG_MMC
+#ifdef CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FSL_ESDHC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#endif
+
+#define CONFIG_HAS_FSL_DR_USB
+
+#if defined(CONFIG_HAS_FSL_DR_USB)
+#define CONFIG_USB_EHCI
+
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_USB_STORAGE
+#endif
+#endif
+
+/*
+ * Environment
+ */
+#if defined(CONFIG_SDCARD)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_FSL_FIXED_MMC_LOCATION
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_ENV_SIZE			0x2000
+#elif defined(CONFIG_SPIFLASH)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS	0
+#define CONFIG_ENV_SPI_CS	0
+#define CONFIG_ENV_SPI_MAX_HZ	10000000
+#define CONFIG_ENV_SPI_MODE	0
+#define CONFIG_ENV_OFFSET	0x100000	/* 1MB */
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#define CONFIG_ENV_SIZE		0x2000
+#elif defined(CONFIG_NAND)
+#define CONFIG_ENV_IS_IN_NAND
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
+#else
+#if defined(CONFIG_P1010RDB_PA)
+#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_RANGE	(3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */
+#elif defined(CONFIG_P1010RDB_PB)
+#define CONFIG_ENV_SIZE		(16 * 1024)
+#define CONFIG_ENV_RANGE	(32 * CONFIG_ENV_SIZE) /* new block size 512K */
+#endif
+#endif
+#define CONFIG_ENV_OFFSET	(1024 * 1024)
+#elif defined(CONFIG_SYS_RAMBOOT)
+#define CONFIG_ENV_IS_NOWHERE		/* Store ENV in memory only */
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_MONITOR_BASE - 0x1000)
+#define CONFIG_ENV_SIZE			0x2000
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+#endif
+
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ERRATA
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
+		 || defined(CONFIG_FSL_SATA)
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+						/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02		/* Software reboot */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20) /* Increase max gunzip size */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+#endif
+
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	u-boot.bin/* U-Boot image on TFTP server */
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+#define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE		115200
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hwconfig=" __stringify(CONFIG_DEF_HWCONFIG)  "\0"	\
+	"netdev=eth0\0"						\
+	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
+	"loadaddr=1000000\0"			\
+	"consoledev=ttyS0\0"				\
+	"ramdiskaddr=2000000\0"			\
+	"ramdiskfile=rootfs.ext2.gz.uboot\0"		\
+	"fdtaddr=c00000\0"				\
+	"fdtfile=p1010rdb.dtb\0"		\
+	"bdev=sda1\0"	\
+	"hwconfig=usb1:dr_mode=host,phy_type=utmi\0"	\
+	"othbootargs=ramdisk_size=600000\0" \
+	"usbfatboot=setenv bootargs root=/dev/ram rw "	\
+	"console=$consoledev,$baudrate $othbootargs; "	\
+	"usb start;"			\
+	"fatload usb 0:2 $loadaddr $bootfile;"		\
+	"fatload usb 0:2 $fdtaddr $fdtfile;"	\
+	"fatload usb 0:2 $ramdiskaddr $ramdiskfile;"	\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr\0"		\
+	"usbext2boot=setenv bootargs root=/dev/ram rw "	\
+	"console=$consoledev,$baudrate $othbootargs; "	\
+	"usb start;"			\
+	"ext2load usb 0:4 $loadaddr $bootfile;"		\
+	"ext2load usb 0:4 $fdtaddr $fdtfile;"	\
+	"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"	\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr\0"	\
+	CONFIG_BOOTMODE
+
+#if defined(CONFIG_P1010RDB_PA)
+#define CONFIG_BOOTMODE \
+	"boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
+	"mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
+	"boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
+	"mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
+	"boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
+	"mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
+
+#elif defined(CONFIG_P1010RDB_PB)
+#define CONFIG_BOOTMODE \
+	"boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
+	"i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
+	"boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
+	"i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
+	"boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
+	"i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
+	"boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
+	"i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
+	"boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
+	"i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
+#endif
+
+#define CONFIG_RAMBOOTCOMMAND		\
+	"setenv bootargs root=/dev/ram rw "	\
+	"console=$consoledev,$baudrate $othbootargs; "	\
+	"tftp $ramdiskaddr $ramdiskfile;"	\
+	"tftp $loadaddr $bootfile;"		\
+	"tftp $fdtaddr $fdtfile;"		\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
+
+#include <asm/fsl_secure_boot.h>
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/P1022DS.h b/qemu/roms/u-boot/include/configs/P1022DS.h
new file mode 100644
index 000000000..959cdf69b
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/P1022DS.h
@@ -0,0 +1,786 @@
+/*
+ * Copyright 2010-2012 Freescale Semiconductor, Inc.
+ * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
+ *          Timur Tabi <timur@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "../board/freescale/common/ics307_clk.h"
+
+#ifdef CONFIG_36BIT
+#define CONFIG_PHYS_64BIT
+#endif
+
+#ifdef CONFIG_SDCARD
+#define CONFIG_SPL
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_MMC_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_FSL_LAW			/* Use common FSL init code */
+#define CONFIG_SYS_TEXT_BASE		0x11001000
+#define CONFIG_SPL_TEXT_BASE		0xf8f81000
+#define CONFIG_SPL_PAD_TO		0x20000
+#define CONFIG_SPL_MAX_SIZE		(128 * 1024)
+#define CONFIG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_DST	(0x11000000)
+#define CONFIG_SYS_MMC_U_BOOT_START	(0x11000000)
+#define CONFIG_SYS_MMC_U_BOOT_OFFS	(128 << 10)
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_LDSCRIPT		"arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#define CONFIG_SPL_MMC_BOOT
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_COMMON_INIT_DDR
+#endif
+#endif
+
+#ifdef CONFIG_SPIFLASH
+#define CONFIG_SPL
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_FSL_LAW		/* Use common FSL init code */
+#define CONFIG_SYS_TEXT_BASE		0x11001000
+#define CONFIG_SPL_TEXT_BASE		0xf8f81000
+#define CONFIG_SPL_PAD_TO		0x20000
+#define CONFIG_SPL_MAX_SIZE		(128 * 1024)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE	(768 << 10)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST		(0x11000000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_START	(0x11000000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS	(128 << 10)
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#define CONFIG_SPL_SPI_BOOT
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_COMMON_INIT_DDR
+#endif
+#endif
+
+#define CONFIG_NAND_FSL_ELBC
+#define CONFIG_SYS_NAND_MAX_ECCPOS	56
+#define CONFIG_SYS_NAND_MAX_OOBFREE	5
+
+#ifdef CONFIG_NAND
+#define CONFIG_SPL
+#define CONFIG_TPL
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SPL_NAND_BOOT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_NAND_INIT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SPL_MAX_SIZE		(128 << 10)
+#define CONFIG_SPL_TEXT_BASE		0xf8f81000
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(832 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	(0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_START	(0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	((128 + 128) << 10)
+#elif defined(CONFIG_SPL_BUILD)
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TEXT_BASE		0xff800000
+#define CONFIG_SPL_MAX_SIZE		4096
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(128 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	0xf8f80000
+#define CONFIG_SYS_NAND_U_BOOT_START	0xf8f80000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(128 << 10)
+#endif
+#define CONFIG_SPL_PAD_TO		0x20000
+#define CONFIG_TPL_PAD_TO		0x20000
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SYS_TEXT_BASE		0x11001000
+#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE			/* BOOKE */
+#define CONFIG_E500			/* BOOKE e500 family */
+#define CONFIG_P1022
+#define CONFIG_P1022DS
+#define CONFIG_MP			/* support multiple processors */
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xeff40000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+#define CONFIG_FSL_ELBC			/* Has Enhanced localbus controller */
+#define CONFIG_PCI			/* Enable PCI/PCIE */
+#define CONFIG_PCIE1			/* PCIE controler 1 (slot 1) */
+#define CONFIG_PCIE2			/* PCIE controler 2 (slot 2) */
+#define CONFIG_PCIE3			/* PCIE controler 3 (ULI bridge) */
+#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
+#define CONFIG_FSL_PCIE_RESET		/* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
+#endif
+
+#define CONFIG_FSL_LAW			/* Use common FSL init code */
+
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk()
+#define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk()
+#define CONFIG_ICS307_REFCLK_HZ	33333000  /* ICS307 clock chip ref freq */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE
+#define CONFIG_BTB
+
+#define CONFIG_SYS_MEMTEST_START	0x00000000
+#define CONFIG_SYS_MEMTEST_END		0x7fffffff
+
+#define CONFIG_SYS_CCSRBAR		0xffe00000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+
+/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
+       SPL code*/
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#endif
+
+
+/* DDR Setup */
+#define CONFIG_DDR_SPD
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_FSL_DDR3
+
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#endif
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+/* I2C addresses of SPD EEPROMs */
+#define CONFIG_SYS_SPD_BUS_NUM		1
+#define SPD_EEPROM_ADDRESS		0x51	/* CTLR 0 DIMM 0 */
+
+/* These are used when DDR doesn't use SPD.  */
+#define CONFIG_SYS_SDRAM_SIZE		2048
+#define CONFIG_SYS_SDRAM_SIZE_LAW	LAW_SIZE_2G
+#define CONFIG_SYS_DDR_CS0_BNDS		0x0000003F
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80014202
+#define CONFIG_SYS_DDR_CS1_BNDS		0x0040007F
+#define CONFIG_SYS_DDR_CS1_CONFIG	0x80014202
+#define CONFIG_SYS_DDR_TIMING_3		0x00010000
+#define CONFIG_SYS_DDR_TIMING_0		0x40110104
+#define CONFIG_SYS_DDR_TIMING_1		0x5c5bd746
+#define CONFIG_SYS_DDR_TIMING_2		0x0fa8d4ca
+#define CONFIG_SYS_DDR_MODE_1		0x00441221
+#define CONFIG_SYS_DDR_MODE_2		0x00000000
+#define CONFIG_SYS_DDR_INTERVAL		0x0a280100
+#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
+#define CONFIG_SYS_DDR_CLK_CTRL		0x02800000
+#define CONFIG_SYS_DDR_CONTROL		0xc7000008
+#define CONFIG_SYS_DDR_CONTROL_2	0x24401041
+#define	CONFIG_SYS_DDR_TIMING_4		0x00220001
+#define	CONFIG_SYS_DDR_TIMING_5		0x02401400
+#define	CONFIG_SYS_DDR_ZQ_CONTROL	0x89080600
+#define CONFIG_SYS_DDR_WRLVL_CONTROL	0x8675f608
+
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
+ * 0x8000_0000	0xdfff_ffff	PCI Express Mem		1.5G non-cacheable
+ * 0xffc0_0000	0xffc2_ffff	PCI IO range		192K non-cacheable
+ *
+ * Localbus cacheable (TBD)
+ * 0xXXXX_XXXX	0xXXXX_XXXX	SRAM			YZ M Cacheable
+ *
+ * Localbus non-cacheable
+ * 0xe000_0000	0xe80f_ffff	Promjet/free		128M non-cacheable
+ * 0xe800_0000	0xefff_ffff	FLASH			128M non-cacheable
+ * 0xff80_0000	0xff80_7fff	NAND			32K non-cacheable
+ * 0xffdf_0000	0xffdf_7fff	PIXIS			32K non-cacheable TLB0
+ * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K Cacheable TLB0
+ * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
+ */
+
+/*
+ * Local Bus Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE		0xe8000000 /* start of FLASH 128M */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_FLASH_BASE_PHYS	0xfe8000000ull
+#else
+#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+#endif
+
+#define CONFIG_FLASH_BR_PRELIM  \
+	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
+#define CONFIG_FLASH_OR_PRELIM	(OR_AM_128MB | 0xff7)
+
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_BR1_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_FLASH_OR_PRELIM	/* NOR Options */
+#else
+#define CONFIG_SYS_BR0_PRELIM	CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM	CONFIG_FLASH_OR_PRELIM  /* NOR Options */
+#endif
+
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS}
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	1024
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+#endif
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+/* Nand Flash */
+#if defined(CONFIG_NAND_FSL_ELBC)
+#define CONFIG_SYS_NAND_BASE		0xff800000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_NAND_BASE_PHYS	0xfff800000ull
+#else
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#endif
+
+#define CONFIG_SYS_NAND_BASE_LIST	{CONFIG_SYS_NAND_BASE}
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND			1
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(256 * 1024)
+#define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
+
+/* NAND flash config */
+#define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+			       | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+			       | BR_PS_8	       /* Port Size = 8 bit */ \
+			       | BR_MS_FCM	       /* MSEL = FCM */ \
+			       | BR_V)		       /* valid */
+#define CONFIG_SYS_NAND_OR_PRELIM  (OR_AM_32KB	       /* length 256K */ \
+			       | OR_FCM_PGS	       /* Large Page*/ \
+			       | OR_FCM_CSCT \
+			       | OR_FCM_CST \
+			       | OR_FCM_CHT \
+			       | OR_FCM_SCY_1 \
+			       | OR_FCM_TRLX \
+			       | OR_FCM_EHTR)
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_BR0_PRELIM	CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
+#define CONFIG_SYS_OR0_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#else
+#define CONFIG_SYS_BR1_PRELIM	CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#endif
+
+#endif /* CONFIG_NAND_FSL_ELBC */
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_MISC_INIT_R
+#define CONFIG_HWCONFIG
+
+#define CONFIG_FSL_NGPIXIS
+#define PIXIS_BASE		0xffdf0000	/* PIXIS registers */
+#ifdef CONFIG_PHYS_64BIT
+#define PIXIS_BASE_PHYS		0xfffdf0000ull
+#else
+#define PIXIS_BASE_PHYS		PIXIS_BASE
+#endif
+
+#define CONFIG_SYS_BR2_PRELIM	(BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR2_PRELIM	(OR_AM_32KB | 0x6ff7)
+
+#define PIXIS_LBMAP_SWITCH	7
+#define PIXIS_LBMAP_MASK	0xF0
+#define PIXIS_LBMAP_ALTBANK	0x20
+#define PIXIS_SPD		0x07
+#define PIXIS_SPD_SYSCLK_MASK	0x07
+#define PIXIS_ELBC_SPI_MASK	0xc0
+#define PIXIS_SPI		0x80
+
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000 /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000 /* Size of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
+
+/*
+ * Config the L2 Cache as L2 SRAM
+*/
+#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_INIT_L2_ADDR	0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE		(256 << 10)
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE	0xf8f81000
+#define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE	(32 << 10)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(108 << 10)
+#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
+#elif defined(CONFIG_NAND)
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE		(256 << 10)
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE	0xf8f81000
+#define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(48 << 10)
+#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
+#else
+#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE		(256 << 10)
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE	(CONFIG_SYS_INIT_L2_END - 0x2000)
+#define CONFIG_SPL_RELOC_STACK		((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
+#endif
+#endif
+#endif
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+/* Video */
+
+#ifdef CONFIG_FSL_DIU_FB
+#define CONFIG_SYS_DIU_ADDR	(CONFIG_SYS_CCSRBAR + 0x10000)
+#define CONFIG_VIDEO
+#define CONFIG_CMD_BMP
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+/*
+ * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
+ * disable empty flash sector detection, which is I/O-intensive.
+ */
+#undef CONFIG_SYS_FLASH_EMPTY_INFO
+#endif
+
+#ifndef CONFIG_FSL_DIU_FB
+#endif
+
+#ifdef CONFIG_ATI
+#define VIDEO_IO_OFFSET		CONFIG_SYS_PCIE1_IO_VIRT
+#define CONFIG_VIDEO
+#define CONFIG_BIOSEMU
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_ATI_RADEON_FB
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#endif
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+#define CONFIG_SYS_I2C_NOPROBES		{{0, 0x29}}
+
+/*
+ * I2C2 EEPROM
+ */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_EEPROM_BUS_NUM	1
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+
+#define CONFIG_HARD_SPI
+#define CONFIG_FSL_ESPI
+
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED		10000000
+#define CONFIG_SF_DEFAULT_MODE		0
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 1, Slot 2, tgtid 1, Base address a000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0xc0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc40000000ull
+#else
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc0000000
+#endif
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc20000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xfffc20000ull
+#else
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xffc20000
+#endif
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 2, direct to uli, tgtid 2, Base address 9000 */
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
+#else
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
+#endif
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xffc10000
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xfffc10000ull
+#else
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
+#endif
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 3, Slot 1, tgtid 3, Base address b000 */
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0x80000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc00000000ull
+#else
+#define CONFIG_SYS_PCIE3_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0x80000000
+#endif
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xffc00000
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xfffc00000ull
+#else
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xffc00000
+#endif
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_E1000			/* Define e1000 pci Ethernet card */
+#endif
+
+/* SATA */
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+#define CONFIG_FSL_SATA_V2
+
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
+
+#ifdef CONFIG_FSL_SATA
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+#define CONFIG_MMC
+#ifdef CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#endif
+
+#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+#define CONFIG_TSEC_ENET
+#ifdef CONFIG_TSEC_ENET
+
+#define CONFIG_TSECV2
+
+#define CONFIG_MII			/* MII PHY management */
+#define CONFIG_TSEC1		1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define CONFIG_TSEC2		1
+#define CONFIG_TSEC2_NAME	"eTSEC2"
+
+#define TSEC1_PHY_ADDR		1
+#define TSEC2_PHY_ADDR		2
+
+#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+
+#define CONFIG_ETHPRIME		"eTSEC1"
+
+#define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
+#endif
+
+/*
+ * Environment
+ */
+#ifdef CONFIG_SPIFLASH
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS	0
+#define CONFIG_ENV_SPI_CS	0
+#define CONFIG_ENV_SPI_MAX_HZ	10000000
+#define CONFIG_ENV_SPI_MODE	0
+#define CONFIG_ENV_SIZE		0x2000	/* 8KB */
+#define CONFIG_ENV_OFFSET	0x100000	/* 1MB */
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#elif defined(CONFIG_SDCARD)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_FSL_FIXED_MMC_LOCATION
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_SYS_MMC_ENV_DEV	0
+#elif defined(CONFIG_NAND)
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
+#else
+#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
+#endif
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET	(1024 * 1024)
+#define CONFIG_ENV_RANGE	(3 * CONFIG_ENV_SIZE)
+#elif defined(CONFIG_SYS_RAMBOOT)
+#define CONFIG_ENV_IS_NOWHERE	/* Store ENV in memory only */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
+#define CONFIG_ENV_SIZE		0x2000
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+#endif
+
+#define CONFIG_LOADS_ECHO
+#define CONFIG_SYS_LOADS_BAUD_CHANGE
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ERRATA
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
+
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
+/*
+ * USB
+ */
+#define CONFIG_HAS_FSL_DR_USB
+#ifdef CONFIG_HAS_FSL_DR_USB
+#define CONFIG_USB_EHCI
+
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_FAT
+#endif
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	16
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+#define CONFIG_HOSTNAME		p1022ds
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */
+
+#define CONFIG_LOADADDR		1000000
+
+#define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
+
+#define CONFIG_BAUDRATE	115200
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"netdev=eth0\0"						\
+	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
+	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
+	"tftpflash=tftpboot $loadaddr $uboot && "		\
+		"protect off $ubootaddr +$filesize && "		\
+		"erase $ubootaddr +$filesize && "		\
+		"cp.b $loadaddr $ubootaddr $filesize && "	\
+		"protect on $ubootaddr +$filesize && "		\
+		"cmp.b $loadaddr $ubootaddr $filesize\0"	\
+	"consoledev=ttyS0\0"					\
+	"ramdiskaddr=2000000\0"					\
+	"ramdiskfile=rootfs.ext2.gz.uboot\0"			\
+	"fdtaddr=c00000\0"	  			      	\
+	"fdtfile=p1022ds.dtb\0"	  				\
+	"bdev=sda3\0"		  			      	\
+	"hwconfig=esdhc;audclk:12\0"
+
+#define CONFIG_HDBOOT					\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs $videobootargs;"	\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv bootargs root=/dev/nfs rw "				\
+	"nfsroot=$serverip:$rootpath "					\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs $videobootargs;"	\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+	"setenv bootargs root=/dev/ram rw "				\
+	"console=$consoledev,$baudrate $othbootargs $videobootargs;"	\
+	"tftp $ramdiskaddr $ramdiskfile;"				\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_RAMBOOTCOMMAND
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/P1023RDB.h b/qemu/roms/u-boot/include/configs/P1023RDB.h
new file mode 100644
index 000000000..ba3da06df
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/P1023RDB.h
@@ -0,0 +1,379 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Authors:  Roy Zang <tie-fei.zang@freescale.com>
+ *	     Chunhe Lan <Chunhe.Lan@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xeff40000
+#endif
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE		/* BOOKE */
+#define CONFIG_E500		/* BOOKE e500 family */
+#define CONFIG_P1023
+#define CONFIG_MP		/* support multiple processors */
+
+#define CONFIG_FSL_ELBC		/* Has Enhanced localbus controller */
+#define CONFIG_PCI		/* Enable PCI/PCIE */
+#define CONFIG_PCI_INDIRECT_BRIDGE     /* indirect PCI bridge support */
+#define CONFIG_PCIE1		/* PCIE controler 1 (slot 1) */
+#define CONFIG_PCIE2		/* PCIE controler 2 (slot 2) */
+#define CONFIG_PCIE3		/* PCIE controler 3 (slot 3) */
+#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
+#define CONFIG_FSL_PCIE_RESET	/* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
+#define CONFIG_FSL_LAW		/* Use common FSL init code */
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_clock_freq(void);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ	66666666
+#define CONFIG_DDR_CLK_FREQ	CONFIG_SYS_CLK_FREQ
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* toggle branch predition */
+#define CONFIG_HWCONFIG
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#define CONFIG_SYS_MEMTEST_START	0x01000000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x02000000
+
+#define CONFIG_PANIC_HANG	/* do not reset board on panic */
+
+/* Implement conversion of addresses in the LBC */
+#define CONFIG_SYS_LBC_LBCR		0x00000000
+#define CONFIG_SYS_LBC_LCRR		LCRR_CLKDIV_8
+
+/* DDR Setup */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	1
+
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_FSL_DDR3
+#define CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SYS_SDRAM_SIZE		512u	/* DDR is 512M */
+#define CONFIG_SYS_SPD_BUS_NUM          0
+#define SPD_EEPROM_ADDRESS              0x50
+#define CONFIG_SYS_DDR_RAW_TIMING
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000	0x1fff_ffff	DDR			512M cacheable
+ * 0x8000_0000	0xbfff_ffff	PCI Express Mem		1G non-cacheable
+ * 0xc000_0000	0xdfff_ffff	PCI			512M non-cacheable
+ * 0xe100_0000	0xe3ff_ffff	PCI IO range		4M non-cacheable
+ * 0xff00_0000	0xff3f_ffff	DPAA_QBMAN		4M cacheable
+ * 0xff60_0000	0xff7f_ffff	CCSR			2M non-cacheable
+ * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K cacheable TLB0
+ *
+ * Localbus non-cacheable
+ *
+ * 0xec00_0000	0xefff_ffff	NOR flash		64M non-cacheable
+ * 0xffa0_0000	0xffaf_ffff	NAND			1M non-cacheable
+ */
+
+/*
+ * Local Bus Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE		0xec000000 /* start of FLASH 64M */
+#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_FLASH_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
+				| BR_PS_16 | BR_V)
+#define CONFIG_FLASH_OR_PRELIM	0xfc000ff7
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_BOARD_EARLY_INIT_F	/* call board_early_init_f function */
+#define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
+
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000/* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN	(768 * 1024)	  /* Reserve 512 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN	(6 * 1024 * 1024) /* Reserved for malloc */
+
+#define CONFIG_SYS_NAND_BASE		0xffa00000
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+#define CONFIG_NAND_FSL_ELBC
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+
+/* NAND flash config */
+#define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
+				| BR_PS_8		/* Port Size = 8bit */ \
+				| BR_MS_FCM		/* MSEL = FCM */ \
+				| BR_V)			/* valid */
+#define CONFIG_SYS_NAND_OR_PRELIM  (OR_AM_256KB		/* length 256K */ \
+				| OR_FCM_PGS \
+				| OR_FCM_CSCT \
+				| OR_FCM_CST \
+				| OR_FCM_CHT \
+				| OR_FCM_SCY_1 \
+				| OR_FCM_TRLX \
+				| OR_FCM_EHTR)
+
+#define CONFIG_SYS_BR0_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM	CONFIG_FLASH_OR_PRELIM	/* NOR Options */
+#define CONFIG_SYS_BR1_PRELIM	CONFIG_SYS_NAND_BR_PRELIM
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX		1
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR + 0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+
+/*
+ * I2C2 EEPROM
+ */
+#define CONFIG_ID_EEPROM
+#ifdef CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#endif
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_BUS_NUM		0
+
+#define CONFIG_CMD_I2C
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 3, Slot 1, tgtid 3, Base address b000 */
+#define CONFIG_SYS_PCIE3_NAME		"Slot 3"
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCIE3_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0x80000000
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xffc00000
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xffc00000
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 2, direct to uli, tgtid 2, Base address 9000 */
+#define CONFIG_SYS_PCIE2_NAME		"Slot 2"
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xffc10000
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 1, Slot 2, tgtid 1, Base address a000 */
+#define CONFIG_SYS_PCIE1_NAME		"Slot 1"
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc20000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xffc20000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+
+#if defined(CONFIG_PCI)
+#define CONFIG_E1000		/* Defind e1000 pci Ethernet card */
+#define CONFIG_PCI_PNP		/* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
+#endif	/* CONFIG_PCI */
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
+
+#if defined(CONFIG_PCI)
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
+/*
+ * USB
+ */
+#define CONFIG_HAS_FSL_DR_USB
+#ifdef CONFIG_HAS_FSL_DR_USB
+#define CONFIG_USB_EHCI
+
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_CMDLINE_EDITING		/* Command-line editing */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)   /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)   /* Increase max gunzip size */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	(u-boot.bin) /* U-Boot image on TFTP server */
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+#define CONFIG_BOOTDELAY -1	/* -1 disables auto-boot */
+
+#define CONFIG_BAUDRATE	115200
+
+/* Qman/Bman */
+#define CONFIG_SYS_DPAA_QBMAN		/* support Q/Bman */
+#define CONFIG_SYS_QMAN_MEM_BASE	0xff000000
+#define CONFIG_SYS_QMAN_MEM_PHYS	CONFIG_SYS_QMAN_MEM_BASE
+#define CONFIG_SYS_QMAN_MEM_SIZE	0x00200000
+#define CONFIG_SYS_BMAN_MEM_BASE	0xff200000
+#define CONFIG_SYS_BMAN_MEM_PHYS	CONFIG_SYS_BMAN_MEM_BASE
+#define CONFIG_SYS_BMAN_MEM_SIZE	0x00200000
+
+/* For FM */
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHY_ATHEROS
+#endif
+
+/* Default address of microcode for the Linux Fman driver */
+/* QE microcode/firmware address */
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_FMAN_FW_ADDR	0xEFF00000
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR	0x1
+#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR	0x2
+
+#define CONFIG_SYS_TBIPA_VALUE	8
+#define CONFIG_MII		/* MII PHY management */
+#define CONFIG_ETHPRIME		"FM1@DTSEC1"
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/P1023RDS.h b/qemu/roms/u-boot/include/configs/P1023RDS.h
new file mode 100644
index 000000000..8601eec85
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/P1023RDS.h
@@ -0,0 +1,523 @@
+/*
+ * Copyright 2010-2012 Freescale Semiconductor, Inc.
+ *
+ * Authors:  Roy Zang <tie-fei.zang@freescale.com>
+ *	     Chunhe Lan <b25806@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * p1023rds board configuration file
+ *
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifdef CONFIG_NAND
+#define CONFIG_NAND_U_BOOT
+#define CONFIG_RAMBOOT_NAND
+#endif
+
+#ifdef CONFIG_NAND_U_BOOT
+#define CONFIG_SYS_TEXT_BASE_SPL	0xfff00000
+#define CONFIG_SYS_TEXT_BASE		0x11001000
+
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
+#else
+#define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif /* CONFIG_NAND_SPL */
+#endif
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xeff40000
+#endif
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE		/* BOOKE */
+#define CONFIG_E500		/* BOOKE e500 family */
+#define CONFIG_P1023
+#define CONFIG_P1023RDS
+#define CONFIG_MP		/* support multiple processors */
+
+#define CONFIG_FSL_ELBC		/* Has Enhanced localbus controller */
+#define CONFIG_PCI		/* Enable PCI/PCIE */
+#define CONFIG_PCIE1		/* PCIE controler 1 (slot 1) */
+#define CONFIG_PCIE2		/* PCIE controler 2 (slot 2) */
+#define CONFIG_PCIE3		/* PCIE controler 3 (slot 3) */
+#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_FSL_PCIE_RESET	/* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
+#define CONFIG_FSL_LAW		/* Use common FSL init code */
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_clock_freq(void);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ	66666666
+#define CONFIG_DDR_CLK_FREQ	CONFIG_SYS_CLK_FREQ
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* toggle branch predition */
+#define CONFIG_HWCONFIG
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x1fffffff	/* fix me, only 1G */
+#define CONFIG_PANIC_HANG	/* do not reset board on panic */
+
+#define CONFIG_SYS_LBC_LBCR	0x00000000	/* Implement conversion of
+						addresses in the LBC */
+
+/* DDR Setup */
+#define CONFIG_VERY_BIG_RAM
+
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	2
+
+/* These are used when DDR doesn't use SPD.  */
+#define CONFIG_SYS_SDRAM_SIZE		2048u	/* DDR is 2GB */
+
+/* Default settings for "stable" mode */
+#define CONFIG_SYS_DDR_CS0_BNDS		0x0000003F
+#define CONFIG_SYS_DDR_CS1_BNDS		0x0040007F
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80014302
+#define CONFIG_SYS_DDR_CS1_CONFIG	0x80014302
+#define CONFIG_SYS_DDR_TIMING_3		0x00020000
+#define CONFIG_SYS_DDR_TIMING_0		0x40110104
+#define CONFIG_SYS_DDR_TIMING_1		0x5C59E544
+#define CONFIG_SYS_DDR_TIMING_2		0x0fA888CA
+#define CONFIG_SYS_DDR_MODE_1		0x00441210
+#define CONFIG_SYS_DDR_MODE_2		0x00000000
+#define CONFIG_SYS_DDR_MODE_CTRL	0x00000000
+#define CONFIG_SYS_DDR_INTERVAL		0x0A280100
+#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
+#define CONFIG_SYS_DDR_CLK_CTRL		0x01800000
+#define CONFIG_SYS_DDR_TIMING_4		0x00000001
+#define CONFIG_SYS_DDR_TIMING_5		0x01401400
+#define CONFIG_SYS_DDR_ZQ_CNTL		0x89080600
+#define CONFIG_SYS_DDR_WRLVL_CNTL	0x8675F605
+#define CONFIG_SYS_DDR_CONTROL	0xC70C0008 /* Type = DDR3: No Interleaving */
+#define CONFIG_SYS_DDR_CONTROL2		0x24401010
+#define CONFIG_SYS_DDR_CDR1		0x00000000
+#define CONFIG_SYS_DDR_CDR2		0x00000000
+
+#define CONFIG_SYS_DDR_ERR_INT_EN	0x00000000
+#define CONFIG_SYS_DDR_ERR_DIS		0x00000000
+#define CONFIG_SYS_DDR_SBE		0x00000000
+
+/* Settings that differ for "performance" mode */
+#define CONFIG_SYS_DDR_CS0_BNDS_PERF	0x0000007F /* Interleaving Enabled */
+#define CONFIG_SYS_DDR_CS1_BNDS_PERF	0x00000000 /* Interleaving Enabled */
+#define CONFIG_SYS_DDR_CS1_CONFIG_PERF	0x80014302
+#define CONFIG_SYS_DDR_TIMING_1_PERF	0x5C58E544
+#define CONFIG_SYS_DDR_TIMING_2_PERF	0x0FA888CA
+/* Type = DDR3: cs0-cs1 interleaving */
+#define CONFIG_SYS_DDR_CONTROL_PERF	0xC70C4008
+#define CONFIG_SYS_DDR_CDR_1		0x00000000
+#define CONFIG_SYS_DDR_CDR_2		0x00000000
+
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
+ * 0x8000_0000	0xbfff_ffff	PCI Express Mem		1G non-cacheable
+ * 0xc000_0000	0xdfff_ffff	PCI			512M non-cacheable
+ * 0xe100_0000	0xe3ff_ffff	PCI IO range		4M non-cacheable
+ *
+ * Localbus non-cacheable
+ * 0xe000_0000	0xe003_ffff	BCSR			256K BCSR
+ * 0xee00_0000	0xefff_ffff	NOR flash		32M NOR flash
+ * 0xff00_0000	0xff3f_ffff	DPAA_QBMAN		4M
+ * 0xff60_0000	0xff7f_ffff	CCSR			2M non-cacheable
+ * 0xffa0_0000	0xffaf_ffff	NAND			1M non-cacheable
+ * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K Cacheable TLB0
+ */
+
+/*
+ * Local Bus Definitions
+ */
+#define CONFIG_SYS_BCSR_BASE		0xe0000000 /* start of on board FPGA */
+#define CONFIG_SYS_BCSR_BASE_PHYS	CONFIG_SYS_BCSR_BASE
+
+#ifndef CONFIG_NAND
+#define CONFIG_SYS_FLASH_BASE		0xee000000 /* start of FLASH 32M */
+
+#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_FLASH_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
+		| BR_PS_16 | BR_V)
+#define CONFIG_FLASH_OR_PRELIM	0xfe000ff7
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+#else
+#define CONFIG_SYS_NO_FLASH
+#endif
+
+#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_F	/* call board_early_init_f function */
+#define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
+
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_END	0x00004000	/* End of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+	(CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN	(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN	(6 * 1024 * 1024) /* Reserved for malloc */
+
+#ifndef CONFIG_NAND_SPL
+#define CONFIG_SYS_NAND_BASE		0xffa00000
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#else
+#define CONFIG_SYS_NAND_BASE		0xfff00000
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#endif
+
+#define CONFIG_SYS_NAND_BASE_LIST	{CONFIG_SYS_NAND_BASE}
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+#define CONFIG_NAND_FSL_ELBC
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(16 * 1024)
+
+/* NAND boot: 4K NAND loader config */
+#define CONFIG_SYS_NAND_SPL_SIZE	0x1000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	((768 << 10) + CONFIG_SYS_NAND_SPL_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_DST	(0x11000000 - CONFIG_SYS_NAND_SPL_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_START	0x11000000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(0)
+#define CONFIG_SYS_NAND_U_BOOT_RELOC	0x00010000
+#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP	(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
+
+/* NAND flash config */
+#define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
+				| BR_PS_8		/* Port Size = 8bit */ \
+				| BR_MS_FCM		/* MSEL = FCM */ \
+				| BR_V)			/* valid */
+#define CONFIG_SYS_NAND_OR_PRELIM  (0xFFF80000		/* length 32K */ \
+				| OR_FCM_CSCT \
+				| OR_FCM_CST \
+				| OR_FCM_CHT \
+				| OR_FCM_SCY_1 \
+				| OR_FCM_TRLX \
+				| OR_FCM_EHTR)
+
+#ifdef CONFIG_RAMBOOT_NAND
+/* NAND Base Address */
+#define CONFIG_SYS_BR0_PRELIM	CONFIG_SYS_NAND_BR_PRELIM
+#define CONFIG_SYS_OR0_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+/* chip select 1 - BCSR */
+#define CONFIG_SYS_BR1_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_BCSR_BASE_PHYS) \
+				| BR_MS_GPCM | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR1_PRELIM  (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_XACS \
+				| OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR \
+				| OR_GPCM_EAD)
+#else
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_FLASH_OR_PRELIM	/* NOR Options */
+/* chip select 1 - BCSR */
+#define CONFIG_SYS_BR1_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_BCSR_BASE_PHYS) \
+				| BR_MS_GPCM | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR1_PRELIM  (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_XACS \
+				| OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR \
+				| OR_GPCM_EAD)
+#endif
+
+/* Serial Port
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX		1
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR + 0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x51
+
+/*
+ * I2C2 EEPROM
+ */
+#define CONFIG_ID_EEPROM
+#ifdef CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#endif
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x51
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_EEPROM_BUS_NUM	0
+
+#define CONFIG_CMD_I2C
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_ATMEL
+
+#define CONFIG_HARD_SPI
+#define CONFIG_FSL_ESPI
+
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED		10000000
+#define CONFIG_SF_DEFAULT_MODE		0
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 3, Slot 1, tgtid 3, Base address b000 */
+#define CONFIG_SYS_PCIE3_NAME		"Slot 3"
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCIE3_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0x80000000
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xffc00000
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xffc00000
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 2, direct to uli, tgtid 2, Base address 9000 */
+#define CONFIG_SYS_PCIE2_NAME		"Slot 2"
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xffc10000
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 1, Slot 2, tgtid 1, Base address a000 */
+#define CONFIG_SYS_PCIE1_NAME		"Slot 1"
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc20000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xffc20000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+
+#if defined(CONFIG_PCI)
+#define CONFIG_E1000		/* Defind e1000 pci Ethernet card */
+#define CONFIG_PCI_PNP		/* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
+#endif	/* CONFIG_PCI */
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_RAMBOOT_NAND)
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET	((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
+#else
+#define CONFIG_ENV_IS_NOWHERE	/* Store ENV in memory only */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x4000)
+#define CONFIG_ENV_SIZE		0x2000
+#endif
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+#endif
+
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
+
+#if defined(CONFIG_PCI)
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
+/*
+ * USB
+ */
+#define CONFIG_HAS_FSL_DR_USB
+#ifdef CONFIG_HAS_FSL_DR_USB
+#define CONFIG_USB_EHCI
+
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_CMDLINE_EDITING		/* Command-line editing */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(16 << 20) /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(16 << 20) /* Increase max gunzip size */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	(u-boot.bin) /* U-Boot image on TFTP server */
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
+
+#define CONFIG_BAUDRATE	115200
+
+/* Qman/Bman */
+#define CONFIG_SYS_DPAA_QBMAN		/* support Q/Bman */
+#define CONFIG_SYS_QMAN_MEM_BASE	0xff000000
+#define CONFIG_SYS_QMAN_MEM_PHYS	CONFIG_SYS_QMAN_MEM_BASE
+#define CONFIG_SYS_QMAN_MEM_SIZE	0x00200000
+#define CONFIG_SYS_BMAN_MEM_BASE	0xff200000
+#define CONFIG_SYS_BMAN_MEM_PHYS	CONFIG_SYS_BMAN_MEM_BASE
+#define CONFIG_SYS_BMAN_MEM_SIZE	0x00200000
+
+/* For FM */
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHY_MARVELL
+#endif
+
+#ifndef CONFIG_NAND
+/* Default address of microcode for the Linux Fman driver */
+/* QE microcode/firmware address */
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_FMAN_FW_ADDR	0xEFF00000
+#else
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_FMAN_FW_ADDR	0x1f00000
+#endif
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR	0x2
+#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR	0x7
+
+#define CONFIG_SYS_TBIPA_VALUE	8
+#define CONFIG_MII		/* MII PHY management */
+#define CONFIG_ETHPRIME		"FM1@DTSEC1"
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/P1_P2_RDB.h b/qemu/roms/u-boot/include/configs/P1_P2_RDB.h
new file mode 100644
index 000000000..0f0406725
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/P1_P2_RDB.h
@@ -0,0 +1,711 @@
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * P1 P2 RDB board configuration file
+ * This file is intended to address a set of Low End and Ultra Low End
+ * Freescale SOCs of QorIQ series(RDB platforms).
+ * Currently only P2020RDB
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifdef CONFIG_36BIT
+#define CONFIG_PHYS_64BIT
+#endif
+
+#ifdef CONFIG_P1011RDB
+#define CONFIG_P1011
+#endif
+#ifdef CONFIG_P1020RDB
+#define CONFIG_P1020
+#endif
+#ifdef CONFIG_P2010RDB
+#define CONFIG_P2010
+#endif
+#ifdef CONFIG_P2020RDB
+#define CONFIG_P2020
+#endif
+
+#ifdef CONFIG_NAND
+#define CONFIG_NAND_U_BOOT		1
+#define CONFIG_RAMBOOT_NAND		1
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
+#else
+#define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds
+#define CONFIG_SYS_TEXT_BASE		0xf8f82000
+#endif /* CONFIG_NAND_SPL */
+#endif
+
+#ifdef CONFIG_SDCARD
+#define CONFIG_RAMBOOT_SDCARD		1
+#define CONFIG_SYS_TEXT_BASE		0x11000000
+#define CONFIG_RESET_VECTOR_ADDRESS	0x110bfffc
+#endif
+
+#ifdef CONFIG_SPIFLASH
+#define CONFIG_RAMBOOT_SPIFLASH		1
+#define CONFIG_SYS_TEXT_BASE		0x11000000
+#define CONFIG_RESET_VECTOR_ADDRESS	0x110bfffc
+#endif
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE		0xeff40000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE		1	/* BOOKE */
+#define CONFIG_E500		1	/* BOOKE e500 family */
+#define CONFIG_FSL_ELBC		1	/* Enable eLBC Support */
+
+#define CONFIG_PCI		1	/* Enable PCI/PCIE */
+#if defined(CONFIG_PCI)
+#define CONFIG_PCIE1		1	/* PCIE controler 1 (slot 1) */
+#define CONFIG_PCIE2		1	/* PCIE controler 2 (slot 2) */
+#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
+#define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
+#endif /* #if defined(CONFIG_PCI) */
+#define CONFIG_FSL_LAW		1	/* Use common FSL init code */
+#define CONFIG_TSEC_ENET		/* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_PCI)
+#define CONFIG_E1000		1	/*  E1000 pci Ethernet card*/
+#endif
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_board_sys_clk(unsigned long dummy);
+#endif
+#define CONFIG_DDR_CLK_FREQ	66666666 /* DDRCLK on P1_P2 RDB */
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0) /*sysclk for P1_P2 RDB */
+
+#if defined(CONFIG_P2020) || defined(CONFIG_P1020)
+#define CONFIG_MP
+#endif
+
+#define CONFIG_HWCONFIG
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* toggle branch predition */
+
+#define CONFIG_ADDR_STREAMING		/* toggle addr streaming */
+
+#define CONFIG_ENABLE_36BIT_PHYS	1
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP			1
+#define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
+#endif
+
+#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x1fffffff
+#define CONFIG_PANIC_HANG	/* do not reset board on panic */
+
+ /*
+  * Config the L2 Cache as L2 SRAM
+  */
+#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	0xff8f80000ull
+#else
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#endif
+#define CONFIG_SYS_L2_SIZE		(512 << 10)
+#define CONFIG_SYS_INIT_L2_END		(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+
+#define CONFIG_SYS_CCSRBAR		0xffe00000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+
+#if defined(CONFIG_NAND_SPL)
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#endif
+
+/* DDR Setup */
+#define CONFIG_SYS_FSL_DDR2
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#undef CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
+
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+
+#define CONFIG_SYS_SDRAM_SIZE	1024 	/* DDR size on P1_P2 RDBs */
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	1
+
+#define CONFIG_SYS_DDR_ERR_INT_EN	0x0000000d
+#define CONFIG_SYS_DDR_ERR_DIS		0x00000000
+#define CONFIG_SYS_DDR_SBE		0x00FF0000
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000	0x3fff_ffff	DDR			1G cacheablen
+ * 0x8000_0000  0xbfff_ffff	PCI Express Mem		1G non-cacheable
+ * 0xffc0_0000  0xffc3_ffff	PCI IO range		256k non-cacheable
+ *
+ * Localbus cacheable (TBD)
+ * 0xXXXX_XXXX	0xXXXX_XXXX	SRAM			YZ M Cacheable
+ *
+ * Localbus non-cacheable
+ * 0xef00_0000	0xefff_ffff	FLASH			16M non-cacheable
+ * 0xffa0_0000	0xffaf_ffff	NAND			1M non-cacheable
+ * 0xffb0_0000	0xffbf_ffff	VSC7385 switch		1M non-cacheable
+ * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K Cacheable TLB0
+ * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
+ */
+
+/*
+ * Local Bus Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE		0xef000000	/* start of FLASH 16M */
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_FLASH_BASE_PHYS	0xfef000000ull
+#else
+#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+#endif
+
+#define CONFIG_FLASH_BR_PRELIM	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+					BR_PS_16 | BR_V)
+#define CONFIG_FLASH_OR_PRELIM		0xff000ff7
+
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS}
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* sectors per device */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_RAMBOOT_SDCARD) || \
+    defined(CONFIG_RAMBOOT_SPIFLASH)
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#else
+#undef CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
+
+#define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_HWCONFIG
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR      0xffd00000	/* stack in RAM */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#else
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS	CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
+#endif
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000	/* Size of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE \
+						- GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc*/
+
+#ifndef CONFIG_NAND_SPL
+#define CONFIG_SYS_NAND_BASE		0xffa00000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_NAND_BASE_PHYS	0xfffa00000ull
+#else
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#endif
+#else
+#define CONFIG_SYS_NAND_BASE		0xfff00000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_NAND_BASE_PHYS	0xffff00000ull
+#else
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#endif
+#endif
+
+#define CONFIG_CMD_NAND
+#define CONFIG_SYS_NAND_BASE_LIST	{CONFIG_SYS_NAND_BASE}
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_NAND_FSL_ELBC		1
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(16 * 1024)
+
+/* NAND boot: 4K NAND loader config */
+#define CONFIG_SYS_NAND_SPL_SIZE	0x1000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	((768 << 10) - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_DST	(CONFIG_SYS_INIT_L2_ADDR)
+#define CONFIG_SYS_NAND_U_BOOT_START	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(0)
+#define CONFIG_SYS_NAND_U_BOOT_RELOC	(CONFIG_SYS_INIT_L2_END - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP		((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
+
+/* NAND flash config */
+#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
+				| BR_PS_8	/* Port Size = 8 bit */ \
+				| BR_MS_FCM		/* MSEL = FCM */ \
+				| BR_V)			/* valid */
+
+#define CONFIG_SYS_NAND_OR_PRELIM	(0xFFF80000	/* length 32K */ \
+				| OR_FCM_CSCT \
+				| OR_FCM_CST \
+				| OR_FCM_CHT \
+				| OR_FCM_SCY_1 \
+				| OR_FCM_TRLX \
+				| OR_FCM_EHTR)
+
+#ifdef CONFIG_RAMBOOT_NAND
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#define CONFIG_SYS_BR1_PRELIM  CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
+#define CONFIG_SYS_OR1_PRELIM  CONFIG_FLASH_OR_PRELIM  /* NOR Options */
+#else
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_FLASH_OR_PRELIM  /* NOR Options */
+#define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
+#define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#endif
+
+#define CONFIG_SYS_VSC7385_BASE	0xffb00000
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_VSC7385_BASE_PHYS	0xfffb00000ull
+#else
+#define CONFIG_SYS_VSC7385_BASE_PHYS	CONFIG_SYS_VSC7385_BASE
+#endif
+
+#define CONFIG_SYS_BR2_PRELIM	(BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE) \
+							| BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR2_PRELIM	(OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
+				OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \
+				OR_GPCM_EHTR | OR_GPCM_EAD)
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
+
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	/* determine from environment */
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT		1
+#define CONFIG_OF_BOARD_SETUP		1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+/* new uImage format support */
+#define CONFIG_FIT		1
+#define CONFIG_FIT_VERBOSE	1 /* enable fit_format_{error,warning}() */
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x29} }
+
+/*
+ * I2C2 EEPROM
+ */
+#define CONFIG_ID_EEPROM
+#ifdef CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#endif
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x52
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_BUS_NUM	1
+
+#define CONFIG_SYS_I2C_PCA9557_ADDR	0x18
+
+#define CONFIG_RTC_DS1337
+#define CONFIG_SYS_RTC_DS1337_NOOSC
+#define CONFIG_SYS_I2C_RTC_ADDR                0x68
+
+/* eSPI - Enhanced SPI */
+#define CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED		10000000
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+#if defined(CONFIG_PCI)
+/* controller 2, Slot 2, tgtid 2, Base address 9000 */
+#define CONFIG_SYS_PCIE2_NAME		"Slot 1"
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xc0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
+#else
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
+#endif
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xffc10000
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xfffc10000ull
+#else
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
+#endif
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 1, Slot 1, tgtid 1, Base address a000 */
+#define CONFIG_SYS_PCIE1_NAME		"Slot 2"
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#else
+#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0x80000000
+#endif
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc00000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xfffc00000ull
+#else
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xffc00000
+#endif
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+#undef CONFIG_RTL8139
+
+#ifdef CONFIG_RTL8139
+/* This macro is used by RTL8139 but not defined in PPC architecture */
+#define KSEG1ADDR(x)		(x)
+#define _IO_BASE	0x00000000
+#endif
+
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+
+#endif	/* CONFIG_PCI */
+
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_MII		1	/* MII PHY management */
+#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"eTSEC2"
+#define CONFIG_TSEC3	1
+#define CONFIG_TSEC3_NAME	"eTSEC3"
+
+#define TSEC1_PHY_ADDR		2
+#define TSEC2_PHY_ADDR		0
+#define TSEC3_PHY_ADDR		1
+
+#define CONFIG_VSC7385_ENET
+
+#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC3_PHYIDX		0
+
+/* Vitesse 7385 */
+
+#ifdef CONFIG_VSC7385_ENET
+/* The size of the VSC7385 firmware image */
+#define CONFIG_VSC7385_IMAGE_SIZE	8192
+#endif
+
+#define CONFIG_ETHPRIME		"eTSEC1"
+
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#if defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_RAMBOOT_NAND)
+	#define CONFIG_ENV_IS_IN_NAND	1
+	#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
+	#define CONFIG_ENV_OFFSET	((768*1024)+CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_RAMBOOT_SDCARD)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_FSL_FIXED_MMC_LOCATION
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#elif defined(CONFIG_RAMBOOT_SPIFLASH)
+	#define CONFIG_ENV_IS_IN_SPI_FLASH
+	#define CONFIG_ENV_SPI_BUS	0
+	#define CONFIG_ENV_SPI_CS	0
+	#define CONFIG_ENV_SPI_MAX_HZ	10000000
+	#define CONFIG_ENV_SPI_MODE	0
+	#define CONFIG_ENV_OFFSET	0x100000	/* 1MB */
+	#define CONFIG_ENV_SECT_SIZE	0x10000
+	#define CONFIG_ENV_SIZE		0x2000
+#endif
+#else
+	#define CONFIG_ENV_IS_IN_FLASH	1
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+	#define CONFIG_ENV_SIZE		0x2000
+	#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
+
+#if defined(CONFIG_PCI)
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#endif
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+#define CONFIG_MMC	1
+
+#ifdef CONFIG_MMC
+#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
+#define CONFIG_CMD_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FSL_ESDHC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#ifdef CONFIG_P2020
+#define CONFIG_SYS_FSL_ESDHC_USE_PIO /* P2020 eSDHC DMA is not functional*/
+#endif
+#endif
+
+#define CONFIG_HAS_FSL_DR_USB
+
+#if defined(CONFIG_HAS_FSL_DR_USB)
+#define CONFIG_USB_EHCI
+
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_USB_STORAGE
+#endif
+#endif
+
+#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+						/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+#endif
+
+#define CONFIG_HOSTNAME		P2020RDB
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	u-boot.bin/* U-Boot image on TFTP server */
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE	115200
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"netdev=eth0\0"						\
+	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
+	"loadaddr=1000000\0"					\
+	"tftpflash=tftpboot $loadaddr $uboot; "			\
+		"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
+			" +$filesize; "	\
+		"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
+			" +$filesize; "	\
+		"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
+			" $filesize; "	\
+		"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
+			" +$filesize; "	\
+		"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
+			" $filesize\0"	\
+	"consoledev=ttyS0\0"				\
+	"ramdiskaddr=2000000\0"			\
+	"ramdiskfile=rootfs.ext2.gz.uboot\0"		\
+	"fdtaddr=c00000\0"				\
+	"fdtfile=p2020rdb.dtb\0"		\
+	"bdev=sda1\0"	\
+	"jffs2nor=mtdblock3\0"	\
+	"norbootaddr=ef080000\0"	\
+	"norfdtaddr=ef040000\0"	\
+	"jffs2nand=mtdblock9\0"	\
+	"nandbootaddr=100000\0"	\
+	"nandfdtaddr=80000\0"		\
+	"nandimgsize=400000\0"		\
+	"nandfdtsize=80000\0"		\
+	"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"	\
+	"vscfw_addr=ef000000\0"	\
+	"othbootargs=ramdisk_size=600000\0" \
+	"usbfatboot=setenv bootargs root=/dev/ram rw "	\
+	"console=$consoledev,$baudrate $othbootargs; "	\
+	"usb start;"			\
+	"fatload usb 0:2 $loadaddr $bootfile;"		\
+	"fatload usb 0:2 $fdtaddr $fdtfile;"	\
+	"fatload usb 0:2 $ramdiskaddr $ramdiskfile;"	\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr\0"		\
+	"usbext2boot=setenv bootargs root=/dev/ram rw "	\
+	"console=$consoledev,$baudrate $othbootargs; "	\
+	"usb start;"			\
+	"ext2load usb 0:4 $loadaddr $bootfile;"		\
+	"ext2load usb 0:4 $fdtaddr $fdtfile;"	\
+	"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"	\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr\0"		\
+	"norboot=setenv bootargs root=/dev/$jffs2nor rw "	\
+	"console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;"	\
+	"bootm $norbootaddr - $norfdtaddr\0"		\
+	"nandboot=setenv bootargs root=/dev/$jffs2nand rw rootfstype=jffs2 " \
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"nand read 2000000 $nandbootaddr $nandimgsize;"	\
+	"nand read 3000000 $nandfdtaddr $nandfdtsize;"	\
+	"bootm 2000000 - 3000000;\0"
+
+#define CONFIG_NFSBOOTCOMMAND		\
+	"setenv bootargs root=/dev/nfs rw "	\
+	"nfsroot=$serverip:$rootpath "		\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"		\
+	"tftp $fdtaddr $fdtfile;"		\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_HDBOOT			\
+	"setenv bootargs root=/dev/$bdev rw rootdelay=30 "	\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"usb start;"			\
+	"ext2load usb 0:1 $loadaddr /boot/$bootfile;"		\
+	"ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"	\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND		\
+	"setenv bootargs root=/dev/ram rw "	\
+	"console=$consoledev,$baudrate $othbootargs; "	\
+	"tftp $ramdiskaddr $ramdiskfile;"	\
+	"tftp $loadaddr $bootfile;"		\
+	"tftp $fdtaddr $fdtfile;"		\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_HDBOOT
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/P2020COME.h b/qemu/roms/u-boot/include/configs/P2020COME.h
new file mode 100644
index 000000000..d414b84dd
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/P2020COME.h
@@ -0,0 +1,547 @@
+/*
+ * Copyright 2009-2010,2012 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* The P2020COME board is only booted via the Freescale On-Chip ROM */
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+
+#define CONFIG_SYS_TEXT_BASE		0xf8f80000
+#define CONFIG_RESET_VECTOR_ADDRESS	0xf8fffffc
+
+#ifdef CONFIG_SDCARD
+#define CONFIG_RAMBOOT_SDCARD		1
+#endif
+
+#ifdef CONFIG_SPIFLASH
+#define CONFIG_RAMBOOT_SPIFLASH		1
+#endif
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE		1	/* BOOKE */
+#define CONFIG_E500		1	/* BOOKE e500 family */
+#define CONFIG_P2020		1
+#define CONFIG_P2020COME	1
+#define CONFIG_FSL_ELBC		1	/* Enable eLBC Support */
+#define CONFIG_MP
+
+#define CONFIG_PCI		1	/* Enable PCI/PCIE */
+#if defined(CONFIG_PCI)
+#define CONFIG_PCIE1		1	/* PCIE controller 1 (slot 1) */
+#define CONFIG_PCIE2		1	/* PCIE controller 2 (slot 2) */
+#define CONFIG_PCIE3		1	/* PCIE controller 3 (slot 3) */
+
+#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
+#define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
+#endif /* #if defined(CONFIG_PCI) */
+#define CONFIG_FSL_LAW		1	/* Use common FSL init code */
+#define CONFIG_TSEC_ENET		/* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_PCI)
+#define CONFIG_E1000		1	/* E1000 pci Ethernet card */
+#endif
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_board_ddr_clk(unsigned long dummy);
+extern unsigned long get_board_sys_clk(unsigned long dummy);
+#endif
+
+/*
+ * For P2020COME DDRCLK and SYSCLK are from the same oscillator
+ * For DA phase the SYSCLK is 66MHz
+ * For EA phase the SYSCLK is 100MHz
+ */
+#define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk(0)
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0)
+
+#define CONFIG_HWCONFIG
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* toggle branch prediction */
+
+#define CONFIG_ADDR_STREAMING		/* toggle addr streaming */
+
+#define CONFIG_ENABLE_36BIT_PHYS	1
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP			1
+#define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
+#endif
+
+#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x1fffffff
+#define CONFIG_PANIC_HANG	/* do not reset board on panic */
+
+ /*
+  * Config the L2 Cache as L2 SRAM
+  */
+#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	0xff8f80000ull
+#else
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#endif
+#define CONFIG_SYS_L2_SIZE		(512 << 10)
+#define CONFIG_SYS_INIT_L2_END		(CONFIG_SYS_INIT_L2_ADDR \
+					+ CONFIG_SYS_L2_SIZE)
+
+#define CONFIG_SYS_CCSRBAR		0xffe00000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+
+/* DDR Setup */
+#define CONFIG_SYS_FSL_DDR3
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
+#define CONFIG_DDR_SPD
+
+#define CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+
+#define CONFIG_SYS_SDRAM_SIZE		2048ULL	/* DDR size on P2020COME */
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	2
+
+#define CONFIG_SYS_DDR_ERR_INT_EN	0x0000000d
+#define CONFIG_SYS_DDR_ERR_DIS		0x00000000
+#define CONFIG_SYS_DDR_SBE		0x00ff0000
+
+#define CONFIG_SYS_SPD_BUS_NUM		1
+#define SPD_EEPROM_ADDRESS		0x53
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000	0x7fff_ffff	DDR3			2G Cacheable
+ * 0x8000_0000	0x9fff_ffff	PCI Express 3 Mem	1G non-cacheable
+ * 0xa000_0000	0xbfff_ffff	PCI Express 2 Mem	1G non-cacheable
+ * 0xc000_0000	0xdfff_ffff	PCI Express 1 Mem	1G non-cacheable
+ * 0xffc1_0000	0xffc1_ffff	PCI Express 3 IO	64K non-cacheable
+ * 0xffc2_0000	0xffc2_ffff	PCI Express 2 IO	64K non-cacheable
+ * 0xffc3_0000	0xffc3_ffff	PCI Express 1 IO	64K non-cacheable
+ *
+ * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K Cacheable TLB0
+ * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
+ */
+
+/*
+ * Local Bus Definitions
+ */
+
+/* There is no NOR Flash on P2020COME */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
+#define CONFIG_HWCONFIG
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* stack in RAM */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	CONFIG_SYS_INIT_RAM_ADDR
+/* the assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#else
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS	CONFIG_SYS_INIT_RAM_ADDR
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
+#endif
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE \
+						- GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	/* determine from environment */
+
+#define CONFIG_SYS_BAUDRATE_TABLE   \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT		1
+#define CONFIG_OF_BOARD_SETUP		1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+/* new uImage format support */
+#define CONFIG_FIT			1
+#define CONFIG_FIT_VERBOSE		1
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x29} }
+
+/*
+ * I2C2 EEPROM
+ */
+#define CONFIG_ID_EEPROM
+#ifdef CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#endif
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR2	0x18
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_EEPROM_BUS_NUM	0
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10 /* and takes up to 10 msec */
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#define CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED		10000000
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+#if defined(CONFIG_PCI)
+
+/* controller 3, Slot 3, tgtid 3, Base address 8000 */
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCIE3_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0x80000000
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000  /* 512M */
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xffc10000
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xffc10000
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000  /* 64k */
+
+/* controller 2, Slot 2, tgtid 2, Base address 9000 */
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000  /* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xffc20000
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xffc20000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000  /* 64k */
+
+/* controller 1, Slot 1, tgtid 1, Base address a000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000  /* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc30000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xffc30000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000  /* 64k */
+
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+#undef CONFIG_RTL8139
+
+#ifdef CONFIG_RTL8139
+/* This macro is used by RTL8139 but not defined in PPC architecture */
+#define KSEG1ADDR(x)		(x)
+#define _IO_BASE		0x00000000
+#endif
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+
+#endif	/* CONFIG_PCI */
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_MII		1	/* MII PHY management */
+#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
+#define CONFIG_TSEC1		1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define CONFIG_TSEC2		1
+#define CONFIG_TSEC2_NAME	"eTSEC2"
+#define CONFIG_TSEC3		1
+#define CONFIG_TSEC3_NAME	"eTSEC3"
+
+#define TSEC1_PHY_ADDR		0
+#define TSEC2_PHY_ADDR		2
+#define TSEC3_PHY_ADDR		1
+
+#undef CONFIG_VSC7385_ENET
+
+#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC3_PHYIDX		0
+
+#define CONFIG_ETHPRIME		"eTSEC1"
+
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#if defined(CONFIG_RAMBOOT_SDCARD)
+	#define CONFIG_ENV_IS_IN_MMC	1
+	#define CONFIG_FSL_FIXED_MMC_LOCATION
+	#define CONFIG_ENV_SIZE		0x2000
+	#define CONFIG_SYS_MMC_ENV_DEV	0
+#elif defined(CONFIG_RAMBOOT_SPIFLASH)
+	#define CONFIG_ENV_IS_IN_SPI_FLASH
+	#define CONFIG_ENV_SPI_BUS	0
+	#define CONFIG_ENV_SPI_CS	0
+	#define CONFIG_ENV_SPI_MAX_HZ	10000000
+	#define CONFIG_ENV_SPI_MODE	0
+	#define CONFIG_ENV_OFFSET	0x100000	/* 1MB */
+	#define CONFIG_ENV_SECT_SIZE	0x10000
+	#define CONFIG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO		1
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
+
+#if defined(CONFIG_PCI)
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#endif
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+#define CONFIG_MMC	1
+
+#ifdef CONFIG_MMC
+#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
+#define CONFIG_CMD_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FSL_ESDHC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
+#endif /* CONFIG_MMC */
+
+#define CONFIG_HAS_FSL_DR_USB
+#ifdef CONFIG_HAS_FSL_DR_USB
+#define CONFIG_USB_EHCI
+
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_USB_STORAGE
+#endif
+#endif
+
+#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* Misc Extra Settings */
+#define CONFIG_CMD_DHCP			1
+
+#define CONFIG_CMD_DATE			1
+#define CONFIG_RTC_M41T62		1
+#define CONFIG_SYS_RTC_BUS_NUM		1
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE	1		/* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+						/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+/* The mac addresses for all ethernet interface */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+#define CONFIG_HAS_ETH3
+#endif
+
+#define CONFIG_HOSTNAME		unknown
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	u-boot.bin
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+#define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS			/* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"hwconfig=fsl_ddr:ecc=on\0"					\
+	"bootcmd=run sdboot\0"						\
+	"sdboot=setenv bootargs root=/dev/mmcblk0p2 rw "		\
+		"rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\
+		"$othbootargs; mmcinfo; "				\
+		"ext2load mmc 0:2 $loadaddr /boot/$bootfile; "		\
+		"ext2load mmc 0:2 $fdtaddr /boot/$fdtfile; "		\
+		"bootm $loadaddr - $fdtaddr\0"				\
+	"sdfatboot=setenv bootargs root=/dev/ram rw "			\
+		"rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\
+		"$othbootargs; mmcinfo; "				\
+		"fatload mmc 0:1 $loadaddr $bootfile; "			\
+		"fatload mmc 0:1 $fdtaddr $fdtfile; "			\
+		"fatload mmc 0:1 $ramdiskaddr $ramdiskfile; "		\
+		"bootm $loadaddr $ramdiskaddr $fdtaddr\0"		\
+	"usbboot=setenv bootargs root=/dev/sda1 rw "			\
+		"rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\
+		"$othbootargs; "					\
+		"usb start; "						\
+		"ext2load usb 0:1 $loadaddr /boot/$bootfile; "		\
+		"ext2load usb 0:1 $fdtaddr /boot/$fdtfile; "		\
+		"bootm $loadaddr - $fdtaddr\0"				\
+	"usbfatboot=setenv bootargs root=/dev/ram rw "			\
+		"console=$consoledev,$baudrate $othbootargs; "		\
+		"usb start; "						\
+		"fatload usb 0:2 $loadaddr $bootfile; "			\
+		"fatload usb 0:2 $fdtaddr $fdtfile; "			\
+		"fatload usb 0:2 $ramdiskaddr $ramdiskfile; "		\
+		"bootm $loadaddr $ramdiskaddr $fdtaddr\0"		\
+	"usbext2boot=setenv bootargs root=/dev/ram rw "			\
+		"console=$consoledev,$baudrate $othbootargs; "		\
+		"usb start; "						\
+		"ext2load usb 0:4 $loadaddr $bootfile; "		\
+		"ext2load usb 0:4 $fdtaddr $fdtfile; "			\
+		"ext2load usb 0:4 $ramdiskaddr $ramdiskfile; "		\
+		"bootm $loadaddr $ramdiskaddr $fdtaddr\0"		\
+	"upgradespi=sf probe 0; "					\
+		"setenv startaddr 0; "					\
+		"setenv erasesize a0000; "				\
+		"tftp 1000000 $tftppath/$uboot_spi; "			\
+		"sf erase $startaddr $erasesize; "			\
+		"sf write 1000000 $startaddr $filesize; "		\
+		"sf erase 100000 120000\0"				\
+	"clearspienv=sf probe 0;sf erase 100000 20000\0"		\
+	"othbootargs=ramdisk_size=700000 cache-sram-size=0x10000\0"	\
+	"netdev=eth0\0"							\
+	"rootdelaysecond=15\0"						\
+	"uboot_nor=u-boot-nor.bin\0"					\
+	"uboot_spi=u-boot-p2020.spi\0"					\
+	"uboot_sd=u-boot-p2020.bin\0"					\
+	"consoledev=ttyS0\0"						\
+	"ramdiskaddr=2000000\0"						\
+	"ramdiskfile=rootfs-dev.ext2.img\0"				\
+	"fdtaddr=c00000\0"						\
+	"fdtfile=uImage-2.6.32-p2020.dtb\0"				\
+	"tftppath=p2020\0"
+
+#define CONFIG_HDBOOT							\
+	"setenv bootargs root=/dev/$bdev rw rootdelay=30 "		\
+	"console=$consoledev,$baudrate $othbootargs;"			\
+	"usb start;"							\
+	"ext2load usb 0:1 $loadaddr /boot/$bootfile;"			\
+	"ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"			\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv bootargs root=/dev/nfs rw "				\
+	"nfsroot=$serverip:$rootpath "					\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
+	"console=$consoledev,$baudrate $othbootargs;"			\
+	"tftp $loadaddr $tftppath/$bootfile;"				\
+	"tftp $fdtaddr $tftppath/$fdtfile;"				\
+	"bootm $loadaddr - $fdtaddr"
+
+
+#define CONFIG_RAMBOOTCOMMAND						\
+	"setenv bootargs root=/dev/ram rw "				\
+	"console=$consoledev,$baudrate $othbootargs;"			\
+	"tftp $ramdiskaddr $tftppath/$ramdiskfile;"			\
+	"tftp $loadaddr $tftppath/$bootfile;"				\
+	"tftp $fdtaddr $tftppath/$fdtfile;"				\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_HDBOOT
+
+#endif  /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/P2020DS.h b/qemu/roms/u-boot/include/configs/P2020DS.h
new file mode 100644
index 000000000..820b6332a
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/P2020DS.h
@@ -0,0 +1,751 @@
+/*
+ * Copyright 2007-2012 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * p2020ds board configuration file
+ *
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "../board/freescale/common/ics307_clk.h"
+
+#ifdef CONFIG_36BIT
+#define CONFIG_PHYS_64BIT
+#endif
+
+#ifdef CONFIG_SDCARD
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_SYS_TEXT_BASE		0xf8f40000
+#define CONFIG_RESET_VECTOR_ADDRESS	0xf8fffffc
+#endif
+
+#ifdef CONFIG_SPIFLASH
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_SYS_TEXT_BASE		0xf8f40000
+#define CONFIG_RESET_VECTOR_ADDRESS	0xf8fffffc
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE		1	/* BOOKE */
+#define CONFIG_E500		1	/* BOOKE e500 family */
+#define CONFIG_P2020		1
+#define CONFIG_P2020DS		1
+#define CONFIG_MP		1	/* support multiple processors */
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xeff40000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+#define CONFIG_SYS_SRIO
+#define CONFIG_SRIO1			/* SRIO port 1 */
+#define CONFIG_SRIO2			/* SRIO port 2 */
+
+#define CONFIG_FSL_ELBC		1	/* Has Enhanced localbus controller */
+#define CONFIG_PCI		1	/* Enable PCI/PCIE */
+#define CONFIG_PCIE1		1	/* PCIE controler 1 (slot 1) */
+#define CONFIG_PCIE2		1	/* PCIE controler 2 (slot 2) */
+#define CONFIG_PCIE3		1	/* PCIE controler 3 (ULI bridge) */
+#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
+#define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
+
+#define CONFIG_FSL_LAW		1	/* Use common FSL init code */
+#define CONFIG_E1000		1	/* Defind e1000 pci Ethernet card*/
+
+#define CONFIG_TSEC_ENET		/* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk() /* sysclk for MPC85xx */
+#define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk() /* ddrclk for MPC85xx */
+#define CONFIG_ICS307_REFCLK_HZ	33333000  /* ICS307 clock chip ref freq */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* toggle branch predition */
+
+#define CONFIG_BOARD_EARLY_INIT_F	/* Call board_pre_init */
+
+#define CONFIG_ENABLE_36BIT_PHYS	1
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP			1
+#define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
+#endif
+
+#define CONFIG_POST CONFIG_SYS_POST_MEMORY	/* test POST memory test */
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+#define CONFIG_PANIC_HANG	/* do not reset board on panic */
+
+/*
+ * Config the L2 Cache
+ */
+#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	0xff8f80000ull
+#else
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#endif
+#define CONFIG_SYS_L2_SIZE		(512 << 10)
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+
+#define CONFIG_SYS_CCSRBAR		0xffe00000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+
+/* DDR Setup */
+#define CONFIG_VERY_BIG_RAM
+#ifdef CONFIG_DDR2
+#define CONFIG_SYS_FSL_DDR2
+#else
+#define CONFIG_SYS_FSL_DDR3		1
+#endif
+
+/* ECC will be enabled based on perf_mode environment variable */
+/* #define	CONFIG_DDR_ECC */
+
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	2
+
+/* I2C addresses of SPD EEPROMs */
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_SPD_BUS_NUM		0	/* SPD EEPROM located on I2C bus 0 */
+#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
+
+/* These are used when DDR doesn't use SPD.  */
+#define CONFIG_SYS_SDRAM_SIZE		1024		/* DDR is 1GB */
+
+/* Default settings for "stable" mode */
+#define CONFIG_SYS_DDR_CS0_BNDS		0x0000003F
+#define CONFIG_SYS_DDR_CS1_BNDS		0x00000000
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80014202
+#define CONFIG_SYS_DDR_CS1_CONFIG	0x00000000
+#define CONFIG_SYS_DDR_TIMING_3		0x00020000
+#define CONFIG_SYS_DDR_TIMING_0		0x00330804
+#define CONFIG_SYS_DDR_TIMING_1		0x6f6b4846
+#define CONFIG_SYS_DDR_TIMING_2		0x0fa890d4
+#define CONFIG_SYS_DDR_MODE_1		0x00421422
+#define CONFIG_SYS_DDR_MODE_2		0x00000000
+#define CONFIG_SYS_DDR_MODE_CTRL	0x00000000
+#define CONFIG_SYS_DDR_INTERVAL		0x61800100
+#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
+#define CONFIG_SYS_DDR_CLK_CTRL		0x02000000
+#define CONFIG_SYS_DDR_TIMING_4		0x00220001
+#define CONFIG_SYS_DDR_TIMING_5		0x03402400
+#define CONFIG_SYS_DDR_ZQ_CNTL		0x89080600
+#define CONFIG_SYS_DDR_WRLVL_CNTL	0x8655A608
+#define CONFIG_SYS_DDR_CONTROL		0xE7000000 /* Type = DDR3: ECC enabled, No Interleaving */
+#define CONFIG_SYS_DDR_CONTROL2		0x24400011
+#define CONFIG_SYS_DDR_CDR1		0x00040000
+#define CONFIG_SYS_DDR_CDR2		0x00000000
+
+#define CONFIG_SYS_DDR_ERR_INT_EN	0x0000000d
+#define CONFIG_SYS_DDR_ERR_DIS		0x00000000
+#define CONFIG_SYS_DDR_SBE		0x00010000
+
+/* Settings that differ for "performance" mode */
+#define CONFIG_SYS_DDR_CS0_BNDS_PERF		0x0000007F /* Interleaving Enabled */
+#define CONFIG_SYS_DDR_CS1_BNDS_PERF		0x00000000 /* Interleaving Enabled */
+#define CONFIG_SYS_DDR_CS1_CONFIG_PERF	0x80014202
+#define CONFIG_SYS_DDR_TIMING_1_PERF		0x5d5b4543
+#define CONFIG_SYS_DDR_TIMING_2_PERF		0x0fa890ce
+#define CONFIG_SYS_DDR_CONTROL_PERF		0xC7004000 /* Type = DDR3: ECC disabled, cs0-cs1 interleaving */
+
+/*
+ * The following set of values were tested for DDR2
+ * with a DDR3 to DDR2 interposer
+ *
+#define CONFIG_SYS_DDR_TIMING_3		0x00000000
+#define CONFIG_SYS_DDR_TIMING_0		0x00260802
+#define CONFIG_SYS_DDR_TIMING_1		0x3935d322
+#define CONFIG_SYS_DDR_TIMING_2		0x14904cc8
+#define CONFIG_SYS_DDR_MODE_1		0x00480432
+#define CONFIG_SYS_DDR_MODE_2		0x00000000
+#define CONFIG_SYS_DDR_INTERVAL		0x06180100
+#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
+#define CONFIG_SYS_DDR_CLK_CTRL		0x03800000
+#define CONFIG_SYS_DDR_OCD_CTRL		0x00000000
+#define CONFIG_SYS_DDR_OCD_STATUS	0x00000000
+#define CONFIG_SYS_DDR_CONTROL		0xC3008000
+#define CONFIG_SYS_DDR_CONTROL2		0x04400010
+ *
+ */
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
+ * 0x8000_0000	0xbfff_ffff	PCI Express Mem		1G non-cacheable
+ * 0xc000_0000	0xdfff_ffff	PCI			512M non-cacheable
+ * 0xe100_0000	0xe3ff_ffff	PCI IO range		4M non-cacheable
+ *
+ * Localbus cacheable (TBD)
+ * 0xXXXX_XXXX	0xXXXX_XXXX	SRAM			YZ M Cacheable
+ *
+ * Localbus non-cacheable
+ * 0xe000_0000	0xe80f_ffff	Promjet/free		128M non-cacheable
+ * 0xe800_0000	0xefff_ffff	FLASH			128M non-cacheable
+ * 0xffa0_0000	0xffaf_ffff	NAND			1M non-cacheable
+ * 0xffdf_0000	0xffdf_7fff	PIXIS			32K non-cacheable TLB0
+ * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K Cacheable TLB0
+ * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
+ */
+
+/*
+ * Local Bus Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE		0xe0000000	/* start of FLASH 128M */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_FLASH_BASE_PHYS	0xfe0000000ull
+#else
+#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+#endif
+
+#define CONFIG_FLASH_BR_PRELIM  \
+	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
+#define CONFIG_FLASH_OR_PRELIM	0xf8000ff7
+
+#define CONFIG_SYS_BR1_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
+#define CONFIG_SYS_OR1_PRELIM	0xf8000ff7
+
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
+
+#define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
+
+#define CONFIG_HWCONFIG			/* enable hwconfig */
+#define CONFIG_FSL_NGPIXIS		/* use common ngPIXIS code */
+
+#ifdef CONFIG_FSL_NGPIXIS
+#define PIXIS_BASE	0xffdf0000	/* PIXIS registers */
+#ifdef CONFIG_PHYS_64BIT
+#define PIXIS_BASE_PHYS	0xfffdf0000ull
+#else
+#define PIXIS_BASE_PHYS	PIXIS_BASE
+#endif
+
+#define CONFIG_SYS_BR3_PRELIM	(BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR3_PRELIM		0xffffeff7	/* 32KB but only 4k mapped */
+
+#define PIXIS_LBMAP_SWITCH	7
+#define PIXIS_LBMAP_MASK	0xf0
+#define PIXIS_LBMAP_SHIFT	4
+#define PIXIS_LBMAP_ALTBANK	0x20
+#endif
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#else
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS	CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
+#endif
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000	/* Size of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
+
+#define CONFIG_SYS_NAND_BASE		0xffa00000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_NAND_BASE_PHYS	0xfffa00000ull
+#else
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#endif
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE,\
+				CONFIG_SYS_NAND_BASE + 0x40000, \
+				CONFIG_SYS_NAND_BASE + 0x80000,\
+				CONFIG_SYS_NAND_BASE + 0xC0000}
+#define CONFIG_SYS_MAX_NAND_DEVICE	4
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND			1
+#define CONFIG_NAND_FSL_ELBC		1
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+
+/* NAND flash config */
+#define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
+				| BR_PS_8		/* Port Size = 8bit */ \
+				| BR_MS_FCM		/* MSEL = FCM */ \
+				| BR_V)			/* valid */
+#define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000		/* length 256K */ \
+				| OR_FCM_PGS		/* Large Page*/ \
+				| OR_FCM_CSCT \
+				| OR_FCM_CST \
+				| OR_FCM_CHT \
+				| OR_FCM_SCY_1 \
+				| OR_FCM_TRLX \
+				| OR_FCM_EHTR)
+
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_FLASH_OR_PRELIM  /* NOR Options */
+#define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_NAND_BR_PRELIM  /* NAND Base Address */
+#define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_NAND_OR_PRELIM  /* NAND Options */
+
+#define CONFIG_SYS_BR4_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
+				| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
+				| BR_PS_8		/* Port Size = 8bit */ \
+				| BR_MS_FCM		/* MSEL = FCM */ \
+				| BR_V)			/* valid */
+#define CONFIG_SYS_OR4_PRELIM  CONFIG_SYS_NAND_OR_PRELIM	/* NAND Options */
+#define CONFIG_SYS_BR5_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \
+				| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
+				| BR_PS_8		/* Port Size = 8bit */ \
+				| BR_MS_FCM		/* MSEL = FCM */ \
+				| BR_V)			/* valid */
+#define CONFIG_SYS_OR5_PRELIM  CONFIG_SYS_NAND_OR_PRELIM	/* NAND Options */
+
+#define CONFIG_SYS_BR6_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \
+				| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
+				| BR_PS_8		/* Port Size = 8bit */ \
+				| BR_MS_FCM		/* MSEL = FCM */ \
+				| BR_V)			/* valid */
+#define CONFIG_SYS_OR6_PRELIM  CONFIG_SYS_NAND_OR_PRELIM	/* NAND Options */
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT		1
+#define CONFIG_OF_BOARD_SETUP		1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x29} }
+
+/*
+ * I2C2 EEPROM
+ */
+#define CONFIG_ID_EEPROM
+#ifdef CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#endif
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_BUS_NUM	0
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#define CONFIG_FSL_ESPI
+
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED		10000000
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 3, Slot 1, tgtid 3, Base address b000 */
+#define CONFIG_SYS_PCIE3_NAME		"Slot 1"
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0x80000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc00000000ull
+#else
+#define CONFIG_SYS_PCIE3_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0x80000000
+#endif
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xffc00000
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xfffc00000ull
+#else
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xffc00000
+#endif
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 2, direct to uli, tgtid 2, Base address 9000 */
+#define CONFIG_SYS_PCIE2_NAME		"ULI"
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
+#else
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
+#endif
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xffc10000
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xfffc10000ull
+#else
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
+#endif
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 1, Slot 2, tgtid 1, Base address a000 */
+#define CONFIG_SYS_PCIE1_NAME		"Slot 2"
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0xc0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc40000000ull
+#else
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc0000000
+#endif
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc20000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xfffc20000ull
+#else
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xffc20000
+#endif
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+
+#if defined(CONFIG_PCI)
+
+/*PCIE video card used*/
+#define VIDEO_IO_OFFSET		CONFIG_SYS_PCIE1_IO_VIRT
+
+/* video */
+#undef CONFIG_VIDEO
+
+#if defined(CONFIG_VIDEO)
+#define CONFIG_BIOSEMU
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_ATI_RADEON_FB
+#define CONFIG_VIDEO_LOGO
+/*#define CONFIG_CONSOLE_CURSOR*/
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
+#endif
+
+/* SRIO1 uses the same window as PCIE2 mem window */
+#define CONFIG_SYS_SRIO1_MEM_VIRT	0xa0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
+#else
+#define CONFIG_SYS_SRIO1_MEM_PHYS	0xa0000000
+#endif
+#define CONFIG_SYS_SRIO1_MEM_SIZE	0x20000000	/* 512M */
+
+/* SRIO2 uses the same window as PCIE1 mem window */
+#define CONFIG_SYS_SRIO2_MEM_VIRT	0xc0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_SRIO2_MEM_PHYS	0xc40000000ull
+#else
+#define CONFIG_SYS_SRIO2_MEM_PHYS	0xc0000000
+#endif
+#define CONFIG_SYS_SRIO2_MEM_SIZE	0x20000000	/* 512M */
+
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SCSI_AHCI
+
+#ifdef CONFIG_SCSI_AHCI
+#define CONFIG_LIBATA
+#define CONFIG_SATA_ULI5288
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	4
+#define CONFIG_SYS_SCSI_MAX_LUN	1
+#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
+#define CONFIG_SYS_SCSI_MAXDEVICE	CONFIG_SYS_SCSI_MAX_DEVICE
+#endif /* SCSI */
+
+#endif	/* CONFIG_PCI */
+
+
+#if defined(CONFIG_TSEC_ENET)
+
+#define CONFIG_MII		1	/* MII PHY management */
+#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"eTSEC2"
+#define CONFIG_TSEC3	1
+#define CONFIG_TSEC3_NAME	"eTSEC3"
+
+#define CONFIG_FSL_SGMII_RISER	1
+#define SGMII_RISER_PHY_OFFSET	0x1b
+
+#ifdef CONFIG_FSL_SGMII_RISER
+#define CONFIG_SYS_TBIPA_VALUE		0x10 /* avoid conflict with eTSEC4 paddr */
+#endif
+
+#define TSEC1_PHY_ADDR		0
+#define TSEC2_PHY_ADDR		1
+#define TSEC3_PHY_ADDR		2
+
+#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC3_PHYIDX		0
+
+#define CONFIG_ETHPRIME		"eTSEC1"
+
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#if defined(CONFIG_SDCARD)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_FSL_FIXED_MMC_LOCATION
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#elif defined(CONFIG_SPIFLASH)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS		0
+#define CONFIG_ENV_SPI_CS		0
+#define CONFIG_ENV_SPI_MAX_HZ		10000000
+#define CONFIG_ENV_SPI_MODE		0
+#define CONFIG_ENV_SIZE			0x2000		/* 8KB */
+#define CONFIG_ENV_OFFSET		0x100000	/* 1MB */
+#define CONFIG_ENV_SECT_SIZE		0x10000
+#else
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
+
+#if defined(CONFIG_PCI)
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_SCSI
+#define CONFIG_CMD_EXT2
+#endif
+
+/*
+ * USB
+ */
+#define CONFIG_HAS_FSL_DR_USB
+#ifdef CONFIG_HAS_FSL_DR_USB
+#define CONFIG_USB_EHCI
+
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#endif
+#endif
+
+/*
+ * SDHC/MMC
+ */
+#define CONFIG_MMC
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#endif
+
+#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+/* The mac addresses for all ethernet interface */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+#endif
+
+#define CONFIG_IPADDR		192.168.1.254
+
+#define CONFIG_HOSTNAME		unknown
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */
+
+#define CONFIG_SERVERIP		192.168.1.1
+#define CONFIG_GATEWAYIP	192.168.1.1
+#define CONFIG_NETMASK		255.255.255.0
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
+
+#define CONFIG_BAUDRATE	115200
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+"perf_mode=performance\0"			\
+	"hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1;"	\
+	"usb1:dr_mode=host,phy_type=ulpi\0"			\
+"netdev=eth0\0"						\
+"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
+"tftpflash=tftpboot $loadaddr $uboot; "			\
+	"protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+	"erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
+	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
+	"protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
+	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
+"satabootcmd=setenv bootargs root=/dev/$bdev rw "	\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr - $fdtaddr"			\
+"consoledev=ttyS0\0"				\
+"ramdiskaddr=2000000\0"			\
+"ramdiskfile=p2020ds/ramdisk.uboot\0"		\
+"fdtaddr=c00000\0"				\
+"othbootargs=cache-sram-size=0x10000\0"	\
+"fdtfile=p2020ds/p2020ds.dtb\0"		\
+"bdev=sda3\0"					\
+"partition=scsi 0:0\0"
+
+#define CONFIG_HDBOOT				\
+ "setenv bootargs root=/dev/$bdev rw "		\
+ "console=$consoledev,$baudrate $othbootargs;"	\
+ "ext2load $partition $loadaddr $bootfile;"	\
+ "ext2load $partition $fdtaddr $fdtfile;"	\
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND		\
+ "setenv bootargs root=/dev/nfs rw "	\
+ "nfsroot=$serverip:$rootpath "		\
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;"	\
+ "tftp $loadaddr $bootfile;"		\
+ "tftp $fdtaddr $fdtfile;"		\
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND		\
+ "setenv bootargs root=/dev/ram rw "	\
+ "console=$consoledev,$baudrate $othbootargs;"	\
+ "tftp $ramdiskaddr $ramdiskfile;"	\
+ "tftp $loadaddr $bootfile;"		\
+ "tftp $fdtaddr $fdtfile;"		\
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_HDBOOT
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/P2041RDB.h b/qemu/roms/u-boot/include/configs/P2041RDB.h
new file mode 100644
index 000000000..54e649391
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/P2041RDB.h
@@ -0,0 +1,747 @@
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * P2041 RDB board configuration file
+ * Also supports P2040 RDB
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_P2041RDB
+#define CONFIG_PHYS_64BIT
+#define CONFIG_PPC_P2041
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg
+#endif
+
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+/* Set 1M boot space */
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
+		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CONFIG_SYS_NO_FLASH
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE
+#define CONFIG_E500			/* BOOKE e500 family */
+#define CONFIG_E500MC			/* BOOKE e500mc family */
+#define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
+#define CONFIG_MP			/* support multiple processors */
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xeff40000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+#define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC		CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_FSL_ELBC			/* Has Enhanced localbus controller */
+#define CONFIG_PCI			/* Enable PCI/PCIE */
+#define CONFIG_PCIE1			/* PCIE controler 1 */
+#define CONFIG_PCIE2			/* PCIE controler 2 */
+#define CONFIG_PCIE3			/* PCIE controler 3 */
+#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
+
+#define CONFIG_SYS_SRIO
+#define CONFIG_SRIO1			/* SRIO port 1 */
+#define CONFIG_SRIO2			/* SRIO port 2 */
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
+#define CONFIG_SYS_DPAA_RMAN		/* RMan */
+
+#define CONFIG_FSL_LAW			/* Use common FSL init code */
+
+#define CONFIG_ENV_OVERWRITE
+
+#ifdef CONFIG_SYS_NO_FLASH
+#if !defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+#else
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#endif
+
+#if defined(CONFIG_SPIFLASH)
+	#define CONFIG_SYS_EXTRA_ENV_RELOC
+	#define CONFIG_ENV_IS_IN_SPI_FLASH
+	#define CONFIG_ENV_SPI_BUS              0
+	#define CONFIG_ENV_SPI_CS               0
+	#define CONFIG_ENV_SPI_MAX_HZ           10000000
+	#define CONFIG_ENV_SPI_MODE             0
+	#define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
+	#define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
+	#define CONFIG_ENV_SECT_SIZE            0x10000
+#elif defined(CONFIG_SDCARD)
+	#define CONFIG_SYS_EXTRA_ENV_RELOC
+	#define CONFIG_ENV_IS_IN_MMC
+	#define CONFIG_FSL_FIXED_MMC_LOCATION
+	#define CONFIG_SYS_MMC_ENV_DEV          0
+	#define CONFIG_ENV_SIZE			0x2000
+	#define CONFIG_ENV_OFFSET		(512 * 1658)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE			CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET		(7 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+#define CONFIG_ENV_IS_IN_REMOTE
+#define CONFIG_ENV_ADDR		0xffe20000
+#define CONFIG_ENV_SIZE		0x2000
+#elif defined(CONFIG_ENV_IS_NOWHERE)
+#define CONFIG_ENV_SIZE		0x2000
+#else
+	#define CONFIG_ENV_IS_IN_FLASH
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE \
+			- CONFIG_ENV_SECT_SIZE)
+	#define CONFIG_ENV_SIZE		0x2000
+	#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+#endif
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(unsigned long dummy);
+#endif
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0)
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BACKSIDE_L2_CACHE
+#define CONFIG_SYS_INIT_L2CSR0		L2CSR0_L2E
+#define CONFIG_BTB			/* toggle branch predition */
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP		64	/* number of TLB1 entries */
+#endif
+
+#define CONFIG_POST CONFIG_SYS_POST_MEMORY	/* test POST memory test */
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_PANIC_HANG	/* do not reset board on panic */
+
+/*
+ *  Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR		CONFIG_RAMBOOT_TEXT_BASE
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_L3_ADDR_PHYS	(0xf00000000ull | \
+		CONFIG_RAMBOOT_TEXT_BASE)
+#else
+#define CONFIG_SYS_INIT_L3_ADDR_PHYS	CONFIG_SYS_INIT_L3_ADDR
+#endif
+#define CONFIG_SYS_L3_SIZE		(1024 << 10)
+#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_DCSRBAR		0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
+#endif
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM	0
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(4 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_FSL_DDR3
+
+#define CONFIG_SYS_SPD_BUS_NUM	0
+#define SPD_EEPROM_ADDRESS	0x52
+#define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
+
+/*
+ * Local Bus Definitions
+ */
+
+/* Set the local bus clock 1/8 of platform clock */
+#define CONFIG_SYS_LBC_LCRR		LCRR_CLKDIV_8
+
+/*
+ * This board doesn't have a promjet connector.
+ * However, it uses commone corenet board LAW and TLB.
+ * It is necessary to use the same start address with proper offset.
+ */
+#define CONFIG_SYS_FLASH_BASE		0xe0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_FLASH_BASE_PHYS	0xfe0000000ull
+#else
+#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+#endif
+
+#define CONFIG_SYS_FLASH_BR_PRELIM \
+		(BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
+		BR_PS_16 | BR_V)
+#define CONFIG_SYS_FLASH_OR_PRELIM \
+		((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
+		 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
+
+#define CONFIG_FSL_CPLD
+#define CPLD_BASE		0xffdf0000	/* CPLD registers */
+#ifdef CONFIG_PHYS_64BIT
+#define CPLD_BASE_PHYS		0xfffdf0000ull
+#else
+#define CPLD_BASE_PHYS		CPLD_BASE
+#endif
+
+#define CONFIG_SYS_BR3_PRELIM	(BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR3_PRELIM	0xffffeff7	/* 32KB but only 4k mapped */
+
+#define PIXIS_LBMAP_SWITCH	7
+#define PIXIS_LBMAP_MASK	0xf0
+#define PIXIS_LBMAP_SHIFT	4
+#define PIXIS_LBMAP_ALTBANK	0x40
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Write Timeout (ms) */
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_NAND_FSL_ELBC
+/* Nand Flash */
+#ifdef CONFIG_NAND_FSL_ELBC
+#define CONFIG_SYS_NAND_BASE		0xffa00000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_NAND_BASE_PHYS	0xfffa00000ull
+#else
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#endif
+
+#define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+#define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
+
+/* NAND flash config */
+#define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+			       | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+			       | BR_PS_8	       /* Port Size = 8 bit */ \
+			       | BR_MS_FCM	       /* MSEL = FCM */ \
+			       | BR_V)		       /* valid */
+#define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000	      /* length 256K */ \
+			       | OR_FCM_PGS	       /* Large Page*/ \
+			       | OR_FCM_CSCT \
+			       | OR_FCM_CST \
+			       | OR_FCM_CHT \
+			       | OR_FCM_SCY_1 \
+			       | OR_FCM_TRLX \
+			       | OR_FCM_EHTR)
+
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
+#define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
+#else
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
+#define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
+#define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#endif
+#else
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
+#endif /* CONFIG_NAND_FSL_ELBC */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#else
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS	CONFIG_SYS_INIT_RAM_ADDR
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
+#endif
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x118100
+
+/*
+ * RapidIO
+ */
+#define CONFIG_SYS_SRIO1_MEM_VIRT	0xa0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
+#else
+#define CONFIG_SYS_SRIO1_MEM_PHYS	0xa0000000
+#endif
+#define CONFIG_SYS_SRIO1_MEM_SIZE	0x10000000	/* 256M */
+
+#define CONFIG_SYS_SRIO2_MEM_VIRT	0xb0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
+#else
+#define CONFIG_SYS_SRIO2_MEM_PHYS	0xb0000000
+#endif
+#define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000	/* 256M */
+
+/*
+ * for slave u-boot IMAGE instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000	/* 512K */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
+/*
+ * for slave UCODE and ENV instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000	/* 256K */
+
+/* slave core release by master*/
+#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
+#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
+
+/*
+ * SRIO_PCIE_BOOT - SLAVE
+ */
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
+		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
+#endif
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#define CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED         10000000
+#define CONFIG_SF_DEFAULT_MODE          0
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#else
+#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0x80000000
+#endif
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
+#else
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xf8000000
+#endif
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 2, Slot 2, tgtid 2, Base address 201000 */
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
+#else
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
+#endif
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
+#else
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xf8010000
+#endif
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 3, Slot 1, tgtid 1, Base address 202000 */
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0xc0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc40000000ull
+#else
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xc0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc0000000
+#endif
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
+#else
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xf8020000
+#endif
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
+
+/* Qman/Bman */
+#define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS	10
+#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
+#else
+#define CONFIG_SYS_BMAN_MEM_PHYS	CONFIG_SYS_BMAN_MEM_BASE
+#endif
+#define CONFIG_SYS_BMAN_MEM_SIZE	0x00200000
+#define CONFIG_SYS_QMAN_NUM_PORTALS	10
+#define CONFIG_SYS_QMAN_MEM_BASE	0xf4200000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_QMAN_MEM_PHYS	0xff4200000ull
+#else
+#define CONFIG_SYS_QMAN_MEM_PHYS	CONFIG_SYS_QMAN_MEM_BASE
+#endif
+#define CONFIG_SYS_QMAN_MEM_SIZE	0x00200000
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+/* Default address of microcode for the Linux Fman driver */
+#if defined(CONFIG_SPIFLASH)
+/*
+ * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
+ * env, so we got 0x110000.
+ */
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_FMAN_FW_ADDR	0x110000
+#elif defined(CONFIG_SDCARD)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 825KB (1650 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+#define CONFIG_SYS_FMAN_FW_ADDR	(512 * 1680)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_FMAN_FW_ADDR	(8 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+/*
+ * Slave has no ucode locally, it can fetch this from remote. When implementing
+ * in two corenet boards, slave's ucode could be stored in master's memory
+ * space, the address can be mapped from slave TLB->slave LAW->
+ * slave SRIO or PCIE outbound window->master inbound window->
+ * master LAW->the ucode address in master's memory space.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
+#define CONFIG_SYS_FMAN_FW_ADDR	0xFFE00000
+#else
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_FMAN_FW_ADDR	0xEFF00000
+#endif
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_TERANETICS
+#endif
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+#define CONFIG_E1000
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif	/* CONFIG_PCI */
+
+/* SATA */
+#define CONFIG_FSL_SATA_V2
+
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_FSL_SATA
+#define CONFIG_LIBATA
+
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
+
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR	0x2
+#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR	0x3
+#define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR	0x4
+#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR	0x1
+#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR	0x0
+
+#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR	0x1c
+#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR	0x1d
+#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR	0x1e
+#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR	0x1f
+
+#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR	0
+
+#define CONFIG_SYS_TBIPA_VALUE	8
+#define CONFIG_MII		/* MII PHY management */
+#define CONFIG_ETHPRIME		"FM1@DTSEC1"
+#define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ERRATA
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
+/*
+* USB
+*/
+#define CONFIG_HAS_FSL_DR_USB
+#define CONFIG_HAS_FSL_MPH_USB
+
+#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#endif
+
+#define CONFIG_CMD_EXT2
+
+#define CONFIG_MMC
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
+				sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory for Linux */
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	u-boot.bin
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+#define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
+
+#define CONFIG_BAUDRATE	115200
+
+#define __USB_PHY_TYPE	utmi
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hwconfig=fsl_ddr:ctlr_intlv=cacheline,"		\
+	"bank_intlv=cs0_cs1\0"					\
+	"netdev=eth0\0"						\
+	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
+	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"		\
+	"tftpflash=tftpboot $loadaddr $uboot && "		\
+	"protect off $ubootaddr +$filesize && "			\
+	"erase $ubootaddr +$filesize && "			\
+	"cp.b $loadaddr $ubootaddr $filesize && "		\
+	"protect on $ubootaddr +$filesize && "			\
+	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
+	"consoledev=ttyS0\0"					\
+	"usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0"		\
+	"usb_dr_mode=host\0"					\
+	"ramdiskaddr=2000000\0"					\
+	"ramdiskfile=p2041rdb/ramdisk.uboot\0"			\
+	"fdtaddr=c00000\0"					\
+	"fdtfile=p2041rdb/p2041rdb.dtb\0"			\
+	"bdev=sda3\0"						\
+	"c=ffe\0"
+
+#define CONFIG_HDBOOT					\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND			\
+	"setenv bootargs root=/dev/nfs rw "	\
+	"nfsroot=$serverip:$rootpath "		\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"		\
+	"tftp $fdtaddr $fdtfile;"		\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND				\
+	"setenv bootargs root=/dev/ram rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $ramdiskaddr $ramdiskfile;"		\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_HDBOOT
+
+#include <asm/fsl_secure_boot.h>
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/P3041DS.h b/qemu/roms/u-boot/include/configs/P3041DS.h
new file mode 100644
index 000000000..e05dd75ce
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/P3041DS.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * P3041 DS board configuration file
+ *
+ */
+#define CONFIG_P3041DS
+#define CONFIG_PHYS_64BIT
+#define CONFIG_PPC_P3041
+
+#define CONFIG_FSL_NGPIXIS		/* use common ngPIXIS code */
+
+#define CONFIG_MMC
+#define CONFIG_NAND_FSL_ELBC
+#define CONFIG_FSL_SATA_V2
+#define CONFIG_PCIE3
+#define CONFIG_PCIE4
+#define CONFIG_SYS_DPAA_RMAN
+
+#define CONFIG_SYS_SRIO
+#define CONFIG_SRIO1			/* SRIO port 1 */
+#define CONFIG_SRIO2			/* SRIO port 2 */
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
+#define CONFIG_ICS307_REFCLK_HZ		25000000  /* ICS307 ref clk freq */
+
+#include "corenet_ds.h"
diff --git a/qemu/roms/u-boot/include/configs/P3G4.h b/qemu/roms/u-boot/include/configs/P3G4.h
new file mode 100644
index 000000000..ac75d3ebf
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/P3G4.h
@@ -0,0 +1,407 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifndef __ASSEMBLY__
+#include <galileo/core.h>
+#endif
+
+#include "../board/evb64260/local.h"
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_P3G4		1	/* this is a P3G4  board	*/
+#define CONFIG_SYS_GT_6426x        GT_64260 /* with a 64260 system controller */
+
+#define	CONFIG_SYS_TEXT_BASE	0xfff00000
+
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115200	*/
+
+#undef	CONFIG_ECC			/* enable ECC support */
+/* #define CONFIG_EVB64260_750CX  1 */      /* Support the EVB-64260-750CX Board */
+
+/* which initialization functions to call for this board */
+#define CONFIG_MISC_INIT_R	1
+#define CONFIG_BOARD_EARLY_INIT_F 1
+
+#define CONFIG_SYS_BOARD_NAME		"P3G4"
+
+#undef CONFIG_SYS_HUSH_PARSER
+
+/*
+ * The following defines let you select what serial you want to use
+ * for your console driver.
+ *
+ * to use the MPSC, #define CONFIG_MPSC.  If you have wired up another
+ * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
+ */
+#define	CONFIG_MPSC
+#define CONFIG_MPSC_PORT	0
+
+
+/* define this if you want to enable GT MAC filtering */
+#define CONFIG_GT_USE_MAC_HASH_TABLE
+
+#undef CONFIG_ETHER_PORT_MII	/* use RMII */
+
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"hostname=p3g4\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
+		"bootm\0"						\
+	"rootpath=/opt/eldk/ppc_74xx\0"					\
+	"bootfile=/tftpboot/p3g4/uImage\0"				\
+	"kernel_addr=ff000000\0"					\
+	"ramdisk_addr=ff010000\0"					\
+	"load=tftp 100000 /tftpboot/p3g4/u-boot.bin\0"			\
+	"update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;"	\
+		"cp.b 100000 fff00000 ${filesize};"			\
+		"setenv filesize;saveenv\0"				\
+	"upd=run load update\0"						\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_LOADS_ECHO	0	/* echo off for serial download	*/
+#define	CONFIG_SYS_LOADS_BAUD_CHANGE		/* allow baudrate changes	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+#undef	CONFIG_ALTIVEC                  /* undef to disable             */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_UNIVERSE
+#define CONFIG_CMD_BSP
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x00400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x00C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CONFIG_SYS_LOAD_ADDR		0x00300000	/* default load address	*/
+#define CONFIG_SYS_BUS_CLK		133000000	/* 133 MHz		*/
+
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_LOCK
+
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xff000000
+#define CONFIG_SYS_RESET_ADDRESS	0xfff00100
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc */
+
+/* areas to map different things with the GT in physical space */
+#define CONFIG_SYS_DRAM_BANKS		1
+#define CONFIG_SYS_DFL_GT_REGS		0x14000000	/* boot time GT_REGS */
+
+/* What to put in the bats. */
+#define CONFIG_SYS_MISC_REGION_BASE	0xf0000000
+
+/* Peripheral Device section */
+#define CONFIG_SYS_GT_REGS		0xf8000000
+#define CONFIG_SYS_DEV_BASE		0xff000000
+
+#define CONFIG_SYS_DEV0_SPACE		CONFIG_SYS_DEV_BASE
+#define CONFIG_SYS_DEV1_SPACE		(CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE)
+#define CONFIG_SYS_DEV2_SPACE		(CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE)
+#define CONFIG_SYS_DEV3_SPACE		(CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE)
+
+#define CONFIG_SYS_DEV0_SIZE		 _8M /* Flash bank */
+#define CONFIG_SYS_DEV1_SIZE		 0   /* unused */
+#define CONFIG_SYS_DEV2_SIZE		 0   /* unused */
+#define CONFIG_SYS_DEV3_SIZE		 0   /* unused */
+
+#define CONFIG_SYS_16BIT_BOOT_PAR	0xc01b5e7c
+#define CONFIG_SYS_DEV0_PAR		CONFIG_SYS_16BIT_BOOT_PAR
+
+#if 0 /* Wrong?? NTL */
+#define CONFIG_SYS_MPP_CONTROL_0	0x53541717	/* InitAct EOT[4] DBurst TCEn[1] */
+						/* DMAAck[1:0] GNT0[1:0] */
+#else
+#define CONFIG_SYS_MPP_CONTROL_0	0x53547777	/* InitAct EOT[4] DBurst TCEn[1] */
+						/* REQ0[1:0] GNT0[1:0] */
+#endif
+#define CONFIG_SYS_MPP_CONTROL_1	0x44009911	/* TCEn[4] TCTcnt[4] GPP[13:12] */
+						/* DMAReq[4] DMAAck[4] WDNMI WDE */
+#if 0 /* Wrong?? NTL */
+#define CONFIG_SYS_MPP_CONTROL_2	0x40091818	/* TCTcnt[0] GPP[22:21] BClkIn */
+						/* DMAAck[1:0] GNT1[1:0] */
+#else
+#define CONFIG_SYS_MPP_CONTROL_2	0x40098888	/* TCTcnt[0] */
+						/* GPP[22] (RS232IntB or PCI1Int) */
+						/* GPP[21] (RS323IntA) */
+						/* BClkIn */
+						/* REQ1[1:0] GNT1[1:0] */
+#endif
+
+#if 0 /* Wrong?? NTL */
+# define CONFIG_SYS_MPP_CONTROL_3	0x00090066	/* GPP[31:29] BClkOut0 */
+						/* GPP[27:26] Int[1:0] */
+#else
+# define CONFIG_SYS_MPP_CONTROL_3	0x22090066      /* MREQ MGNT */
+						/* GPP[29]    (PCI1Int) */
+						/* BClkOut0 */
+						/* GPP[27]    (PCI0Int) */
+						/* GPP[26]    (RtcInt or PCI1Int) */
+						/* CPUInt[25:24] */
+#endif
+
+#define CONFIG_SYS_SERIAL_PORT_MUX	0x00001102	/* 11=MPSC1/MPSC0 02=ETH 0 and 2 RMII */
+
+#if 0 /* Wrong?? - NTL */
+# define CONFIG_SYS_GPP_LEVEL_CONTROL	0x000002c6
+#else
+# define CONFIG_SYS_GPP_LEVEL_CONTROL	0x2c600000	/* 0010 1100 0110 0000 */
+						/* gpp[29] */
+						/* gpp[27:26] */
+						/* gpp[22:21] */
+
+# define CONFIG_SYS_SDRAM_CONFIG	0xd8e18200	/* 0x448 */
+				/* idmas use buffer 1,1
+				   comm use buffer 0
+				   pci use buffer 1,1
+				   cpu use buffer 0
+				   normal load (see also ifdef HVL)
+				   standard SDRAM (see also ifdef REG)
+				   non staggered refresh */
+				/* 31:26  25 23  20 19 18 16 */
+				/* 110110 00 111 0  0  00 1 */
+				/* refresh_count=0x200
+				   phisical interleaving disable
+				   virtual interleaving enable */
+				/* 15 14 13:0 */
+				/* 1  0  0x200 */
+#endif
+
+#if 0
+#define CONFIG_SYS_DUART_IO		CONFIG_SYS_DEV2_SPACE
+#define CONFIG_SYS_DUART_CHAN		1		/* channel to use for console */
+#endif
+#undef CONFIG_SYS_INIT_CHAN1
+#undef CONFIG_SYS_INIT_CHAN2
+#if 0
+#define SRAM_BASE		CONFIG_SYS_DEV0_SPACE
+#define SRAM_SIZE		0x00100000		/* 1 MB of sram */
+#endif
+
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+
+#define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
+#define PCI_HOST_FORCE  1               /* configure as pci host        */
+#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+
+#define CONFIG_PCI                      /* include pci support          */
+#define CONFIG_PCI_HOST PCI_HOST_FORCE  /* select pci host function     */
+#define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
+
+/* PCI MEMORY MAP section */
+#define CONFIG_SYS_PCI0_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI0_MEM_SIZE	_128M
+#define CONFIG_SYS_PCI0_0_MEM_SPACE	(CONFIG_SYS_PCI0_MEM_BASE)
+
+#define CONFIG_SYS_PCI1_MEM_BASE	0x88000000
+#define CONFIG_SYS_PCI1_MEM_SIZE	_128M
+#define CONFIG_SYS_PCI1_0_MEM_SPACE	(CONFIG_SYS_PCI1_MEM_BASE)
+
+/* PCI I/O MAP section */
+#define CONFIG_SYS_PCI0_IO_BASE	0xfa000000
+#define CONFIG_SYS_PCI0_IO_SIZE	_16M
+#define CONFIG_SYS_PCI0_IO_SPACE	(CONFIG_SYS_PCI0_IO_BASE)
+#define CONFIG_SYS_PCI0_IO_SPACE_PCI	0x00000000
+
+#define CONFIG_SYS_PCI1_IO_BASE	0xfb000000
+#define CONFIG_SYS_PCI1_IO_SIZE	_16M
+#define CONFIG_SYS_PCI1_IO_SPACE	(CONFIG_SYS_PCI1_IO_BASE)
+#define CONFIG_SYS_PCI1_IO_SPACE_PCI	0x00000000
+
+/*----------------------------------------------------------------------
+ * Initial BAT mappings
+ */
+
+/* NOTES:
+ * 1) GUARDED and WRITE_THRU not allowed in IBATS
+ * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
+ */
+
+/* SDRAM */
+#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
+
+/* init ram */
+#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
+
+/* PCI0, PCI1 in one BAT */
+#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
+#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
+#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* GT regs, bootrom, all the devices, PCI I/O */
+#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
+#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
+#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
+
+/* I2C speed and slave address (for compatability) defaults */
+#define CONFIG_SYS_I2C_SPEED	400000
+#define CONFIG_SYS_I2C_SLAVE	0x7F
+
+/* I2C addresses for the two DIMM SPD chips */
+#ifndef CONFIG_EVB64260_750CX
+#define DIMM0_I2C_ADDR	0x56
+#define DIMM1_I2C_ADDR	0x54
+#else /* CONFIG_EVB64260_750CX - only has 1 DIMM */
+#define DIMM0_I2C_ADDR  0x54
+#define DIMM1_I2C_ADDR	0x54
+#endif
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CONFIG_SYS_BOOTMAPSZ		(8<<20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	67	/* max number of sectors on one chip */
+
+#define CONFIG_SYS_EXTRA_FLASH_DEVICE	BOOT_DEVICE
+#define CONFIG_SYS_EXTRA_FLASH_WIDTH	2	/* 16 bit */
+#define CONFIG_SYS_BOOT_FLASH_WIDTH	2	/* 16 bit */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
+#define CONFIG_SYS_FLASH_CFI		1
+
+#define	CONFIG_ENV_IS_IN_FLASH	1
+#define	CONFIG_ENV_SIZE		0x1000	/* Total Size of Environment Sector */
+#define CONFIG_ENV_SECT_SIZE	0x20000
+#define CONFIG_ENV_ADDR		0xFFFE0000
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For all MPC74xx CPUs		 */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * L2CR setup -- make sure this is right for your board!
+ * look in include/74xx_7xx.h for the defines used here
+ */
+
+#define CONFIG_SYS_L2
+
+#define L2_INIT		(L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
+			 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
+
+#define L2_ENABLE	(L2_INIT | L2CR_L2E)
+
+#define CONFIG_SYS_BOARD_ASM_INIT      1
+
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/P4080DS.h b/qemu/roms/u-boot/include/configs/P4080DS.h
new file mode 100644
index 000000000..2f8900834
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/P4080DS.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * P4080 DS board configuration file
+ * Also supports P4040 DS
+ */
+#define CONFIG_P4080DS
+#define CONFIG_PHYS_64BIT
+#define CONFIG_PPC_P4080
+
+#define CONFIG_FSL_NGPIXIS		/* use common ngPIXIS code */
+
+#define CONFIG_MMC
+#define CONFIG_PCIE3
+
+#define CONFIG_CMD_SATA
+#define CONFIG_SATA_SIL
+#define CONFIG_SYS_SATA_MAX_DEVICE  2
+#define CONFIG_LIBATA
+#define CONFIG_LBA48
+
+#define CONFIG_SYS_SRIO
+#define CONFIG_SRIO1			/* SRIO port 1 */
+#define CONFIG_SRIO2			/* SRIO port 2 */
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
+#define CONFIG_ICS307_REFCLK_HZ		33333000  /* ICS307 ref clk freq */
+
+#include "corenet_ds.h"
diff --git a/qemu/roms/u-boot/include/configs/P5020DS.h b/qemu/roms/u-boot/include/configs/P5020DS.h
new file mode 100644
index 000000000..588df809d
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/P5020DS.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * P5020 DS board configuration file
+ * Also supports P5010 DS
+ */
+#define CONFIG_P5020DS
+#define CONFIG_PHYS_64BIT
+#define CONFIG_PPC_P5020
+
+#define CONFIG_FSL_NGPIXIS		/* use common ngPIXIS code */
+
+#define CONFIG_MMC
+#define CONFIG_NAND_FSL_ELBC
+#define CONFIG_FSL_SATA_V2
+#define CONFIG_PCIE3
+#define CONFIG_PCIE4
+#define CONFIG_SYS_FSL_RAID_ENGINE
+#define CONFIG_SYS_DPAA_RMAN
+
+#define CONFIG_SYS_SRIO
+#define CONFIG_SRIO1			/* SRIO port 1 */
+#define CONFIG_SRIO2			/* SRIO port 2 */
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
+#define CONFIG_ICS307_REFCLK_HZ		25000000  /* ICS307 ref clk freq */
+
+#include "corenet_ds.h"
diff --git a/qemu/roms/u-boot/include/configs/P5040DS.h b/qemu/roms/u-boot/include/configs/P5040DS.h
new file mode 100644
index 000000000..371485fec
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/P5040DS.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * P5040 DS board configuration file
+ *
+ */
+#define CONFIG_P5040DS
+#define CONFIG_PHYS_64BIT
+#define CONFIG_PPC_P5040
+
+#define CONFIG_FSL_NGPIXIS		/* use common ngPIXIS code */
+
+#define CONFIG_MMC
+#define CONFIG_NAND_FSL_ELBC
+#define CONFIG_PCIE3
+#define CONFIG_SYS_FSL_RAID_ENGINE
+
+#define CONFIG_ICS307_REFCLK_HZ		25000000  /* ICS307 ref clk freq */
+
+#include "corenet_ds.h"
diff --git a/qemu/roms/u-boot/include/configs/PATI.h b/qemu/roms/u-boot/include/configs/PATI.h
new file mode 100644
index 000000000..d823b0f3c
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/PATI.h
@@ -0,0 +1,281 @@
+/*
+ * (C) Copyright 2003
+ * Denis Peter d.peter@mpl.ch
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * File:		PATI.h
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+
+#define CONFIG_MPC555		1		/* This is an MPC555 CPU		*/
+#define CONFIG_PATI		1		/* ...On a PATI board	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
+
+/* Serial Console Configuration */
+#define	CONFIG_5xx_CONS_SCI1
+#undef	CONFIG_5xx_CONS_SCI2
+
+#define CONFIG_BAUDRATE		9600
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_CONSOLE
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MISC
+
+
+#if 0
+#define CONFIG_BOOTDELAY	-1		/* autoboot disabled			*/
+#else
+#define CONFIG_BOOTDELAY	5		/* autoboot after 5 seconds		*/
+#endif
+#define CONFIG_BOOTCOMMAND	""	/* autoboot command			*/
+
+#define CONFIG_BOOTARGS		""		/* */
+
+#define CONFIG_WATCHDOG				/* turn on platform specific watchdog	*/
+
+/*#define CONFIG_STATUS_LED	1		*/ /* Enable status led */
+
+#define CONFIG_LOADS_ECHO	1		/* Echo on for serial download */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	/* stdin, stdout and stderr are in evironment */
+#define CONFIG_PREBOOT
+
+#define	CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT		"pati=> "		/* Monitor Command Prompt	*/
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size	*/
+#else
+#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#endif
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16	       /* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x00010000	/* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END		0x00A00000	/* 10 MB in SRAM			*/
+
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address		*/
+
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 1250000 }
+
+
+/***********************************************************************
+ * Last Stage Init
+ ***********************************************************************/
+#define CONFIG_LAST_STAGE_INIT
+
+/*
+ * Low Level Configuration Settings
+ */
+
+/*
+ * Internal Memory Mapped (This is not the IMMR content)
+ */
+#define CONFIG_SYS_IMMR		0x01C00000		/* Physical start adress of internal memory map */
+
+/*
+ * Definitions for initial stack pointer and data area
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_IMMR + 0x003f9800)	/* Physical start adress of internal MPC555 writable RAM */
+#define	CONFIG_SYS_INIT_RAM_SIZE	(CONFIG_SYS_IMMR + 0x003fffff)	/* Physical end adress of internal MPC555 used RAM area	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_RAM_ADDR) - GENERATED_GBL_DATA_SIZE) /* Offset from the beginning of ram */
+#define	CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_IMMR + 0x03fa000)	/* Physical start adress of inital stack */
+/*
+ * Start addresses for the final memory configuration
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000	/* Monitor won't change memory map			*/
+#define CONFIG_SYS_FLASH_BASE		0xffC00000	/* External flash */
+#define PCI_BASE		0x03000000	/* PCI Base (CS2) */
+#define PCI_CONFIG_BASE		0x04000000	/* PCI & PLD  (CS3) */
+#define PLD_CONFIG_BASE		0x04001000	/* PLD  (CS3) */
+
+#define	CONFIG_SYS_MONITOR_BASE	0xFFF00000
+/* CONFIG_SYS_FLASH_BASE	*/ /* CONFIG_SYS_TEXT_BASE is defined in the board config.mk file.	*/
+						/* This adress is given to the linker with -Ttext to	*/
+						/* locate the text section at this adress.		*/
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 192 kB for Monitor				*/
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()				*/
+
+#define CONFIG_SYS_RESET_ADDRESS	(PLD_CONFIG_BASE + 0x10)	 /* Adress which causes reset */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux		*/
+
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ *-----------------------------------------------------------------------
+ *
+ */
+
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+
+#define CONFIG_FLASH_SHOW_PROGRESS	45
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	128
+
+#define	CONFIG_ENV_IS_IN_EEPROM
+#ifdef	CONFIG_ENV_IS_IN_EEPROM
+#define CONFIG_ENV_OFFSET		0
+#define CONFIG_ENV_SIZE		2048
+#endif
+
+#undef  CONFIG_ENV_IS_IN_FLASH
+#ifdef	CONFIG_ENV_IS_IN_FLASH
+#define	CONFIG_ENV_SIZE		0x00002000		/* Set whole sector as env		*/
+#define CONFIG_ENV_OFFSET		((0 - CONFIG_SYS_FLASH_BASE) - CONFIG_ENV_SIZE)		/* Environment starts at this adress	*/
+#endif
+
+
+#define CONFIG_SPI		1
+#define CONFIG_SYS_SPI_CS_USED	0x09 /* CS0 and CS3 are used */
+#define CONFIG_SYS_SPI_CS_BASE	0x08 /* CS3 is active low */
+#define CONFIG_SYS_SPI_CS_ACT	0x00 /* CS3 is active low */
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * SW Watchdog freeze
+ */
+#undef CONFIG_WATCHDOG
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWP)
+#endif	/* CONFIG_WATCHDOG */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF00
+#define CONFIG_SYS_SCCR	(SCCR_TBS     | SCCR_RTDIV    | SCCR_RTSEL    | \
+			 SCCR_COM01   | SCCR_DFNL000 | SCCR_DFNH000)
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration
+ *-----------------------------------------------------------------------
+ * Data show cycle
+ */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_EARB | SIUMCR_GPC01 | SIUMCR_MLRC11) /* Disable data show cycle	*/
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register
+ *-----------------------------------------------------------------------
+ * Set all bits to 40 Mhz
+ *
+ */
+#define CONFIG_SYS_OSC_CLK	((uint)4000000)		/* Oscillator clock is 4MHz	*/
+
+
+#define CONFIG_SYS_PLPRCR	(PLPRCR_MF_9 | PLPRCR_DIVF_0)
+
+/*-----------------------------------------------------------------------
+ * UMCR - UIMB Module Configuration Register
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_UMCR	(UMCR_FSPEED)		/* IMB clock same as U-bus	*/
+
+/*-----------------------------------------------------------------------
+ * ICTRL - I-Bus Support Control Register
+ */
+#define CONFIG_SYS_ICTRL	(ICTRL_ISCT_SER_7)	/* Take out of serialized mode	*/
+
+/*-----------------------------------------------------------------------
+ * USIU - Memory Controller Register
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | BR_V | BR_BI | BR_PS_16 | BR_SETA)
+#define CONFIG_SYS_OR0_PRELIM		(0xffc00000) /* SCY is not used if external TA is set */
+/* SDRAM */
+#define CONFIG_SYS_BR1_PRELIM		(CONFIG_SYS_SDRAM_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA)
+#define CONFIG_SYS_OR1_PRELIM		(OR_ADDR_MK_FF) /* SCY is not used if external TA is set */
+/* PCI */
+#define CONFIG_SYS_BR2_PRELIM		(PCI_BASE | BR_V | BR_PS_32 | BR_SETA)
+#define CONFIG_SYS_OR2_PRELIM		(OR_ADDR_MK_FF)
+/* config registers: */
+#define CONFIG_SYS_BR3_PRELIM		(PCI_CONFIG_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA)
+#define CONFIG_SYS_OR3_PRELIM		(0xffff0000)
+
+#define FLASH_BASE0_PRELIM	CONFIG_SYS_FLASH_BASE	/* We don't realign the flash	*/
+
+/*-----------------------------------------------------------------------
+ * DER - Timer Decrementer
+ *-----------------------------------------------------------------------
+ * Initialise to zero
+ */
+#define CONFIG_SYS_DER			0x00000000
+
+#define VERSION_TAG "released"
+#define CONFIG_ISO_STRING "MEV-10084-001"
+
+#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/PCI405.h b/qemu/roms/u-boot/include/configs/PCI405.h
new file mode 100644
index 000000000..0989407fc
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/PCI405.h
@@ -0,0 +1,294 @@
+/*
+ * (C) Copyright 2007
+ * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
+ *
+ * (C) Copyright 2001-2004
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_PCI405		1	/* ...on a PCI405 board		*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFD0000
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r() on init	*/
+
+#define CONFIG_SYS_CLK_FREQ	25000000 /* external frequency to pll	*/
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_BOOTDELAY	0	/* autoboot after 0 seconds	*/
+
+#undef	CONFIG_BOOTARGS
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"mem_linux=14336k\0"					        \
+	"optargs=panic=0\0"					        \
+	"ramargs=setenv bootargs mem=$mem_linux root=/dev/ram rw\0"	\
+	"addcons=setenv bootargs $bootargs console=ttyS0,$baudrate $optargs\0" \
+	""
+#define	CONFIG_BOOTCOMMAND      "run ramargs;run addcons;loadpci"
+
+#define CONFIG_PREBOOT                  /* enable preboot variable      */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_ITEST
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_EEPROM
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+#define CONFIG_PRAM		2048	/* reserve 2 MB "protected RAM" */
+
+/*
+ * Miscellaneous configurable options
+ */
+
+#define CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CONFIG_SYS_BASE_BAUD	    691200
+
+/* The following table includes the supported baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#undef CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_HOST PCI_HOST_ADAPTER /* select pci host function	*/
+#undef	CONFIG_PCI_PNP			/* no pci plug-and-play		*/
+					/* resource configuration	*/
+
+#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0407	/* PCI Device ID: PCI-405	*/
+#define CONFIG_SYS_PCI_CLASSCODE	0x0280	/* PCI Class Code: Network/Other*/
+#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CONFIG_SYS_PCI_PTM1MS	0xff000001	/* 16MB, enable hard-wired to 1 */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+
+#define CONFIG_SYS_PCI_PTM2LA	0xef600000	/* point to internal regs	*/
+#define CONFIG_SYS_PCI_PTM2MS	0xffe00001	/* 2MB, enable			*/
+#define CONFIG_SYS_PCI_PTM2PCI 0x00000000	/* Host: use this pci address	*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFFD0000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(192 * 1024)	/* Reserve 196 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CONFIG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
+#define CONFIG_ENV_SIZE		0x400	/* 1024 bytes may be used for env vars*/
+				   /* total size of a CAT24WC08 is 1024 bytes */
+
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
+#define CONFIG_SYS_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last 4 bits of the address	*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0xFFE00000	/* FLASH bank #0	*/
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash Bank 0) initialization					*/
+#define CONFIG_SYS_EBC_PB0AP		0x92015480
+#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (NVRAM/RTC) initialization					*/
+#define CONFIG_SYS_EBC_PB1AP		0x01005280  /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1	*/
+#define CONFIG_SYS_EBC_PB1CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 2 (CAN0, 1) initialization					*/
+#define CONFIG_SYS_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+/*#define CONFIG_SYS_EBC_PB2AP		  0x038056C0  / * BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 3 (FPGA internal) initialization					*/
+#define CONFIG_SYS_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB3CR		0xF041C000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=32bit */
+#define CONFIG_SYS_FPGA_BASE_ADDR	0xF0400000
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ */
+/* FPGA internal regs */
+#define CONFIG_SYS_FPGA_MODE		0x00
+#define CONFIG_SYS_FPGA_STATUS		0x02
+#define CONFIG_SYS_FPGA_TS		0x04
+#define CONFIG_SYS_FPGA_TS_LOW		0x06
+#define CONFIG_SYS_FPGA_TS_CAP0	0x10
+#define CONFIG_SYS_FPGA_TS_CAP0_LOW	0x12
+#define CONFIG_SYS_FPGA_TS_CAP1	0x14
+#define CONFIG_SYS_FPGA_TS_CAP1_LOW	0x16
+#define CONFIG_SYS_FPGA_TS_CAP2	0x18
+#define CONFIG_SYS_FPGA_TS_CAP2_LOW	0x1a
+#define CONFIG_SYS_FPGA_TS_CAP3	0x1c
+#define CONFIG_SYS_FPGA_TS_CAP3_LOW	0x1e
+
+/* FPGA Mode Reg */
+#define CONFIG_SYS_FPGA_MODE_CF_RESET	0x0001
+#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
+#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR  0x1000
+#define CONFIG_SYS_FPGA_MODE_TS_CLEAR	0x2000
+
+/* FPGA Status Reg */
+#define CONFIG_SYS_FPGA_STATUS_DIP0	0x0001
+#define CONFIG_SYS_FPGA_STATUS_DIP1	0x0002
+#define CONFIG_SYS_FPGA_STATUS_DIP2	0x0004
+#define CONFIG_SYS_FPGA_STATUS_FLASH	0x0008
+#define CONFIG_SYS_FPGA_STATUS_TS_IRQ	0x1000
+
+#define CONFIG_SYS_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
+#define CONFIG_SYS_FPGA_MAX_SIZE	32*1024	    /* 32kByte is enough for XC2S15  */
+
+/* FPGA program pin configuration */
+#define CONFIG_SYS_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
+#define CONFIG_SYS_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
+#define CONFIG_SYS_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
+#define CONFIG_SYS_FPGA_INIT		0x00400000  /* FPGA init pin (ppc input)     */
+#define CONFIG_SYS_FPGA_DONE		0x00800000  /* FPGA done pin (ppc input)     */
+/* new INIT and DONE pins since board revision 1.2 (for PPC405GPr support)   */
+#define CONFIG_SYS_FPGA_INIT_V12	0x00008000  /* FPGA init pin (ppc input)     */
+#define CONFIG_SYS_FPGA_DONE_V12	0x00010000  /* FPGA done pin (ppc input)     */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CONFIG_SYS_TEMP_STACK_OCM	  1
+/* On Chip Memory location */
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
+
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/PCI5441.h b/qemu/roms/u-boot/include/configs/PCI5441.h
new file mode 100644
index 000000000..7ae25d7b6
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/PCI5441.h
@@ -0,0 +1,150 @@
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*------------------------------------------------------------------------
+ * BOARD/CPU
+ *----------------------------------------------------------------------*/
+#define	CONFIG_PCI5441		1		/* PCI-5441 board	*/
+#define CONFIG_SYS_CLK_FREQ	50000000	/* 50 MHz core clk	*/
+
+#define CONFIG_SYS_RESET_ADDR		0x00000000	/* Hard-reset address	*/
+#define CONFIG_SYS_EXCEPTION_ADDR	0x01000020	/* Exception entry point*/
+#define CONFIG_SYS_NIOS_SYSID_BASE	0x00920828	/* System id address	*/
+#define	CONFIG_BOARD_EARLY_INIT_F 1	/* enable early board-spec. init*/
+
+/*------------------------------------------------------------------------
+ * CACHE -- the following will support II/s and II/f. The II/s does not
+ * have dcache, so the cache instructions will behave as NOPs.
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_ICACHE_SIZE		4096		/* 4 KByte total	*/
+#define CONFIG_SYS_ICACHELINE_SIZE	32		/* 32 bytes/line	*/
+#define CONFIG_SYS_DCACHE_SIZE		2048		/* 2 KByte (II/f)	*/
+#define CONFIG_SYS_DCACHELINE_SIZE	4		/* 4 bytes/line (II/f)	*/
+
+/*------------------------------------------------------------------------
+ * MEMORY BASE ADDRESSES
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_FLASH_BASE		0x00000000	/* FLASH base addr	*/
+#define CONFIG_SYS_FLASH_SIZE		0x00800000	/* 8 MByte		*/
+#define CONFIG_SYS_SDRAM_BASE		0x01000000	/* SDRAM base addr	*/
+#define CONFIG_SYS_SDRAM_SIZE		0x01000000	/* 16 MByte		*/
+
+/*------------------------------------------------------------------------
+ * MEMORY ORGANIZATION
+ *	-Monitor at top.
+ *	-The heap is placed below the monitor.
+ *	-Global data is placed below the heap.
+ *	-The stack is placed below global data (&grows down).
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_MONITOR_LEN		(128 * 1024)	/* Reserve 128k		*/
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_MALLOC_BASE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP		CONFIG_SYS_GBL_DATA_OFFSET
+
+/*------------------------------------------------------------------------
+ * FLASH (AM29LV065D)
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_MAX_FLASH_SECT	128		/* Max # sects per bank */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* Max # of flash banks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	8000		/* Erase timeout (msec) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	100		/* Write timeout (msec) */
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned char	/* flash word size	*/
+
+/*------------------------------------------------------------------------
+ * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
+ * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
+ * reset address, no? This will keep the environment in user region
+ * of flash. NOTE: the monitor length must be multiple of sector size
+ * (which is common practice).
+ *----------------------------------------------------------------------*/
+#define	CONFIG_ENV_IS_IN_FLASH	1		/* Environment in flash */
+#define CONFIG_ENV_SIZE		(64 * 1024)	/* 64 KByte (1 sector)	*/
+#define CONFIG_ENV_OVERWRITE			/* Serial change Ok	*/
+#define CONFIG_ENV_ADDR	(CONFIG_SYS_RESET_ADDR + CONFIG_SYS_MONITOR_LEN)
+
+/*------------------------------------------------------------------------
+ * CONSOLE
+ *----------------------------------------------------------------------*/
+#define CONFIG_ALTERA_UART		1	/* Use altera uart */
+#if defined(CONFIG_ALTERA_JTAG_UART)
+#define CONFIG_SYS_NIOS_CONSOLE	0x00920820	/* JTAG UART base addr	*/
+#else
+#define CONFIG_SYS_NIOS_CONSOLE	0x009208a0	/* UART base addr	*/
+#endif
+
+#define CONFIG_SYS_NIOS_FIXEDBAUD	1		/* Baudrate is fixed	*/
+#define CONFIG_BAUDRATE		115200		/* Initial baudrate	*/
+#define CONFIG_SYS_BAUDRATE_TABLE	{115200}	/* It's fixed ;-)	*/
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1		/* Suppress console info*/
+
+/*------------------------------------------------------------------------
+ * DEBUG
+ *----------------------------------------------------------------------*/
+#undef CONFIG_ROM_STUBS				/* Stubs not in ROM	*/
+
+/*------------------------------------------------------------------------
+ * TIMEBASE --
+ *
+ * The high res timer defaults to 1 msec. Since it includes the period
+ * registers, the interrupt frequency can be reduced using TMRCNT.
+ * If the default period is acceptable, TMRCNT can be left undefined.
+ * TMRMS represents the desired mecs per tick (msecs per interrupt).
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_LOW_RES_TIMER
+#define CONFIG_SYS_NIOS_TMRBASE	0x00920860	/* Tick timer base addr	*/
+#define CONFIG_SYS_NIOS_TMRIRQ		3	/* Timer IRQ num */
+#define CONFIG_SYS_NIOS_TMRMS		10	/* Desired period (msec)*/
+#define CONFIG_SYS_NIOS_TMRCNT \
+		(CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_SAVES
+
+
+/*------------------------------------------------------------------------
+ * MISC
+ *----------------------------------------------------------------------*/
+#define	CONFIG_SYS_LONGHELP				/* Provide extended help*/
+#define	CONFIG_SYS_CBSIZE		256		/* Console I/O buf size	*/
+#define	CONFIG_SYS_MAXARGS		16		/* Max command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot arg buf size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buf size	*/
+#define	CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE	/* Default load address	*/
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE	/* Start addr for test	*/
+#define CONFIG_SYS_MEMTEST_END		CONFIG_SYS_INIT_SP - 0x00020000
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/PIP405.h b/qemu/roms/u-boot/include/configs/PIP405.h
new file mode 100644
index 000000000..a6f505aaa
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/PIP405.h
@@ -0,0 +1,370 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/***********************************************************
+ * High Level Configuration Options
+ * (easy to change)
+ ***********************************************************/
+#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_PIP405		1	/* ...on a PIP405 board		*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFF80000
+
+/***********************************************************
+ * Clock
+ ***********************************************************/
+#define CONFIG_SYS_CLK_FREQ	33000000 /* external frequency to pll	*/
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_FDC
+#define CONFIG_CMD_SCSI
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_BSP
+
+#define	 CONFIG_SYS_HUSH_PARSER
+/**************************************************************
+ * I2C Stuff:
+ * the PIP405 is equiped with an Atmel 24C128/256 EEPROM at address
+ * 0x53.
+ * Caution: on the same bus is the SPD (Serial Presens Detect
+ * EEPROM of the SDRAM
+ * The Atmel EEPROM uses 16Bit addressing.
+ ***************************************************************/
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		50000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x53
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+#define CONFIG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
+#define CONFIG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
+#define CONFIG_ENV_SIZE            0x800   /* 2 kBytes may be used for env vars */
+
+#undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6	/* The Atmel 24C128/256 has	*/
+					/* 64 byte page write mode using*/
+					/* last	6 bits of the address	*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+
+
+/***************************************************************
+ * Definitions for Serial Presence Detect EEPROM address
+ * (to get SDRAM settings)
+ ***************************************************************/
+#define SPD_EEPROM_ADDRESS      0x50
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R
+
+/**************************************************************
+ * Environment definitions
+ **************************************************************/
+#define CONFIG_BAUDRATE		9600	/* STD Baudrate */
+
+
+#define CONFIG_BOOTDELAY	5
+/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
+/* #define CONFIG_BOOT_RETRY_TIME	-10	/XXX* feature is available but not enabled */
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check console even if bootdelay = 0 */
+
+
+#define CONFIG_BOOTCOMMAND	"diskboot 400000 0:1; bootm" /* autoboot command		*/
+#define CONFIG_BOOTARGS		"console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
+
+#define CONFIG_IPADDR		10.0.0.100
+#define CONFIG_SERVERIP		10.0.0.1
+#define CONFIG_PREBOOT
+/***************************************************************
+ * defines if the console is stored in the environment
+ ***************************************************************/
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	/* stdin, stdout and stderr are in evironment */
+/***************************************************************
+ * defines if an overwrite_console function exists
+ *************************************************************/
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+/***************************************************************
+ * defines if the overwrite_console should be stored in the
+ * environment
+ **************************************************************/
+#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+
+/**************************************************************
+ * loads config
+ *************************************************************/
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_MISC_INIT_R
+/***********************************************************
+ * Miscellaneous configurable options
+ **********************************************************/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0100000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 1 ... 12 MB in DRAM	*/
+
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CONFIG_SYS_BASE_BAUD       691200
+
+/* The following table includes the supported baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CONFIG_SYS_LOAD_ADDR		0x400000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
+#define PCI_HOST_FORCE  1               /* configure as pci host        */
+#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_HOST PCI_HOST_FORCE	/* configure as pci-host	*/
+#define CONFIG_PCI_PNP			/* pci plug-and-play		*/
+					/* resource configuration	*/
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000	/* PCI Vendor ID: to-do!!!	*/
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000	/* PCI Device ID: to-do!!!	*/
+#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CONFIG_SYS_PCI_PTM1MS	0x80000001	/* 2GB, enable hard-wired to 1	*/
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CONFIG_SYS_PCI_PTM2LA	0x00000000	/* disabled			*/
+#define CONFIG_SYS_PCI_PTM2MS	0x00000000	/* disabled			*/
+#define CONFIG_SYS_PCI_PTM2PCI 0x00000000      /* Host: use this pci address   */
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFF80000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserve 1024 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_UPDATE_FLASH_SIZE
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+
+#define CONFIG_FLASH_SHOW_PROGRESS	45
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	256
+
+/*
+ * Init Memory Controller:
+ */
+#define FLASH_MAX_SIZE		0x00800000		/* 8MByte max */
+#define FLASH_BASE_PRELIM	0xFF800000  /* open the flash CS */
+/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
+#define FLASH_SIZE_PRELIM	 3  /* maximal flash FLASH size bank #0	*/
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* Configuration Port location */
+#define CONFIG_PORT_ADDR	0xF4000000
+#define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
+
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in On Chip SRAM)
+ */
+#define CONFIG_SYS_TEMP_STACK_OCM	1
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF0000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR	/* inside of On Chip SRAM    */
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE	/* Size of On Chip SRAM	       */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/***********************************************************************
+ * External peripheral base address
+ ***********************************************************************/
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000
+
+/***********************************************************************
+ * Last Stage Init
+ ***********************************************************************/
+#define CONFIG_LAST_STAGE_INIT
+/************************************************************
+ * Ethernet Stuff
+ ***********************************************************/
+#define CONFIG_PPC4xx_EMAC
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		1	/* PHY address			*/
+/************************************************************
+ * RTC
+ ***********************************************************/
+#define CONFIG_RTC_MC146818
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/************************************************************
+ * IDE/ATA stuff
+ ************************************************************/
+#define CONFIG_SYS_IDE_MAXBUS		2   /* max. 2 IDE busses	*/
+#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
+
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x01F0	/* ide0 offste */
+#define CONFIG_SYS_ATA_IDE1_OFFSET	0x0170	/* ide1 offset */
+#define CONFIG_SYS_ATA_DATA_OFFSET	0	/* data reg offset	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	0	/* reg offset */
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x200	/* alternate register offset */
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
+#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
+#define CONFIG_IDE_RESET		/* reset for ide supported...	*/
+#define CONFIG_IDE_RESET_ROUTINE	/* with a special reset function */
+#define CONFIG_SUPPORT_VFAT
+
+/************************************************************
+ * ATAPI support (experimental)
+ ************************************************************/
+#define CONFIG_ATAPI			/* enable ATAPI Support */
+
+/************************************************************
+ * SCSI support (experimental) only SYM53C8xx supported
+ ************************************************************/
+#define CONFIG_SCSI_SYM53C8XX
+#define CONFIG_SYS_SCSI_MAX_LUN	8	/* number of supported LUNs */
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	7	/* maximum SCSI ID (0..6) */
+#define CONFIG_SYS_SCSI_MAX_DEVICE	CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN /* maximum Target devices */
+#define CONFIG_SYS_SCSI_SPIN_UP_TIME	2
+
+/************************************************************
+ * Disk-On-Chip configuration
+ ************************************************************/
+#define CONFIG_SYS_MAX_DOC_DEVICE	1	/* Max number of DOC devices		*/
+#define CONFIG_SYS_DOC_SHORT_TIMEOUT
+#define CONFIG_SYS_DOC_SUPPORT_2000
+#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
+
+/************************************************************
+ * DISK Partition support
+ ************************************************************/
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION
+#define CONFIG_ISO_PARTITION /* Experimental */
+
+/************************************************************
+ * Keyboard support
+ ************************************************************/
+#define CONFIG_ISA_KEYBOARD
+
+/************************************************************
+ * Video support
+ ************************************************************/
+#define CONFIG_VIDEO			/*To enable video controller support */
+#define CONFIG_VIDEO_CT69000
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_CONSOLE_EXTRA_INFO
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VIDEO_ONBOARD		/* Video controller is on-board */
+
+/************************************************************
+ * USB support
+ ************************************************************/
+#define CONFIG_USB_UHCI
+#define CONFIG_USB_KEYBOARD
+#define CONFIG_USB_STORAGE
+
+/* Enable needed helper functions */
+#define CONFIG_SYS_STDIO_DEREGISTER		/* needs stdio_deregister */
+
+/************************************************************
+ * Debug support
+ ************************************************************/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/************************************************************
+ * support BZIP2 compression
+ ************************************************************/
+#define CONFIG_BZIP2		1
+
+/************************************************************
+ * Ident
+ ************************************************************/
+#define VERSION_TAG "released"
+#define CONFIG_ISO_STRING "MEV-10066-001"
+#define CONFIG_IDENT_STRING "\n(c) 2002 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
+
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/PK1C20.h b/qemu/roms/u-boot/include/configs/PK1C20.h
new file mode 100644
index 000000000..e7d08647f
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/PK1C20.h
@@ -0,0 +1,225 @@
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*------------------------------------------------------------------------
+ * BOARD/CPU
+ *----------------------------------------------------------------------*/
+#define CONFIG_PK1C20		1		/* PK1C20 board		*/
+#define CONFIG_SYS_CLK_FREQ	50000000	/* 50 MHz core clk	*/
+
+#define CONFIG_SYS_RESET_ADDR		0x00000000	/* Hard-reset address	*/
+#define CONFIG_SYS_EXCEPTION_ADDR	0x01000020	/* Exception entry point*/
+#define CONFIG_SYS_NIOS_SYSID_BASE	0x021208b8	/* System id address	*/
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* enable early board-spec. init*/
+
+/*------------------------------------------------------------------------
+ * CACHE -- the following will support II/s and II/f. The II/s does not
+ * have dcache, so the cache instructions will behave as NOPs.
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_ICACHE_SIZE		4096		/* 4 KByte total	*/
+#define CONFIG_SYS_ICACHELINE_SIZE	32		/* 32 bytes/line	*/
+#define CONFIG_SYS_DCACHE_SIZE		2048		/* 2 KByte (II/f)	*/
+#define CONFIG_SYS_DCACHELINE_SIZE	4		/* 4 bytes/line (II/f)	*/
+
+/*------------------------------------------------------------------------
+ * MEMORY BASE ADDRESSES
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_FLASH_BASE		0x00000000	/* FLASH base addr	*/
+#define CONFIG_SYS_FLASH_SIZE		0x00800000	/* 8 MByte		*/
+#define CONFIG_SYS_SDRAM_BASE		0x01000000	/* SDRAM base addr	*/
+#define CONFIG_SYS_SDRAM_SIZE		0x01000000	/* 16 MByte		*/
+#define CONFIG_SYS_SRAM_BASE		0x02000000	/* SRAM base addr	*/
+#define CONFIG_SYS_SRAM_SIZE		0x00100000	/* 1 MB (only 1M mapped)*/
+
+/*------------------------------------------------------------------------
+ * MEMORY ORGANIZATION
+ *	-Monitor at top.
+ *	-The heap is placed below the monitor.
+ *	-Global data is placed below the heap.
+ *	-The stack is placed below global data (&grows down).
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 128k		*/
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_MALLOC_BASE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP		CONFIG_SYS_GBL_DATA_OFFSET
+
+/*------------------------------------------------------------------------
+ * FLASH (AM29LV065D)
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_MAX_FLASH_SECT	128		/* Max # sects per bank */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* Max # of flash banks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	8000		/* Erase timeout (msec) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	100		/* Write timeout (msec) */
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned char	/* flash word size	*/
+
+/*------------------------------------------------------------------------
+ * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
+ * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
+ * reset address, no? This will keep the environment in user region
+ * of flash. NOTE: the monitor length must be multiple of sector size
+ * (which is common practice).
+ *----------------------------------------------------------------------*/
+#define CONFIG_ENV_IS_IN_FLASH	1		/* Environment in flash */
+#define CONFIG_ENV_SIZE		(64 * 1024)	/* 64 KByte (1 sector)	*/
+#define CONFIG_ENV_OVERWRITE			/* Serial change Ok	*/
+#define CONFIG_ENV_ADDR	(CONFIG_SYS_RESET_ADDR + CONFIG_SYS_MONITOR_LEN)
+
+/*------------------------------------------------------------------------
+ * CONSOLE
+ *----------------------------------------------------------------------*/
+#define CONFIG_ALTERA_UART		1	/* Use altera uart */
+#if defined(CONFIG_ALTERA_JTAG_UART)
+#define CONFIG_SYS_NIOS_CONSOLE	0x021208b0	/* JTAG UART base addr	*/
+#else
+#define CONFIG_SYS_NIOS_CONSOLE	0x02120840	/* UART base addr	*/
+#endif
+
+#define CONFIG_SYS_NIOS_FIXEDBAUD	1		/* Baudrate is fixed	*/
+#define CONFIG_BAUDRATE		115200		/* Initial baudrate	*/
+#define CONFIG_SYS_BAUDRATE_TABLE	{115200}	/* It's fixed ;-)	*/
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1		/* Suppress console info*/
+
+/*------------------------------------------------------------------------
+ * EPCS Device -- wne CONFIG_SYS_NIOS_EPCSBASE is defined code/commands for
+ * epcs device access is enabled. The base address is the epcs
+ * _register_ base address, NOT THE ADDRESS OF THE MEMORY BLOCK.
+ * The register base is currently at offset 0x600 from the memory base.
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_NIOS_EPCSBASE	0x02100200	/* EPCS register base	*/
+
+/*------------------------------------------------------------------------
+ * DEBUG
+ *----------------------------------------------------------------------*/
+#undef CONFIG_ROM_STUBS				/* Stubs not in ROM	*/
+
+/*------------------------------------------------------------------------
+ * TIMEBASE --
+ *
+ * The high res timer defaults to 1 msec. Since it includes the period
+ * registers, the interrupt frequency can be reduced using TMRCNT.
+ * If the default period is acceptable, TMRCNT can be left undefined.
+ * TMRMS represents the desired mecs per tick (msecs per interrupt).
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_LOW_RES_TIMER
+#define CONFIG_SYS_NIOS_TMRBASE	0x02120820	/* Tick timer base addr */
+#define CONFIG_SYS_NIOS_TMRIRQ		3	/* Timer IRQ num */
+#define CONFIG_SYS_NIOS_TMRMS		10	/* Desired period */
+#define CONFIG_SYS_NIOS_TMRCNT \
+		(CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
+
+/*------------------------------------------------------------------------
+ * STATUS LED -- Provides a simple blinking led. For Nios2 each board
+ * must implement its own led routines -- leds are, after all,
+ * board-specific, no?
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_LEDPIO_ADDR		0x02120870	/* LED PIO base addr	*/
+#define CONFIG_STATUS_LED			/* Enable status driver */
+#define CONFIG_BOARD_SPECIFIC_LED
+
+#define STATUS_LED_BIT		1		/* Bit-0 on PIO		*/
+#define STATUS_LED_STATE	1		/* Blinking		*/
+#define STATUS_LED_PERIOD	(500/CONFIG_SYS_NIOS_TMRMS) /* Every 500 msec	*/
+
+/*------------------------------------------------------------------------
+ * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ...
+ * and really doesn't need any additional clutter. So I choose the lazy
+ * way out to avoid changes there -- define the base address to ensure
+ * cache bypass so there's no need to monkey with inx/outx macros.
+ *----------------------------------------------------------------------*/
+#define CONFIG_SMC91111_BASE	0x82110300	/* Base addr (bypass)	*/
+#define CONFIG_SMC91111			/* Using SMC91c111	*/
+#undef	CONFIG_SMC91111_EXT_PHY			/* Internal PHY		*/
+#define CONFIG_SMC_USE_32_BIT			/* 32-bit interface	*/
+
+#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_IPADDR		192.168.2.21
+#define CONFIG_SERVERIP		192.168.2.16
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_SAVES
+
+
+/*------------------------------------------------------------------------
+ * COMPACT FLASH
+ *----------------------------------------------------------------------*/
+#if defined(CONFIG_CMD_IDE)
+#define CONFIG_IDE_PREINIT			/* Implement id_preinit	*/
+#define CONFIG_SYS_IDE_MAXBUS		1		/* 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1		/* 1 drive per IDE bus	*/
+
+#define CONFIG_SYS_ATA_BASE_ADDR	0x00900800	/* ATA base addr	*/
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000		/* IDE0 offset		*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0040		/* Data IO offset	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	0x0040		/* Register offset	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100		/* Alternate reg offset	*/
+#define CONFIG_SYS_ATA_STRIDE          4		/* Width betwix addrs	*/
+#define CONFIG_DOS_PARTITION
+
+/* Board-specific cf regs */
+#define CONFIG_SYS_CF_PRESENT		0x00900880	/* CF Present PIO base	*/
+#define CONFIG_SYS_CF_POWER		0x00900890	/* CF Power FET PIO base*/
+#define CONFIG_SYS_CF_ATASEL		0x009008a0	/* CF ATASEL PIO base	*/
+
+#endif
+
+/*------------------------------------------------------------------------
+ * JFFS2
+ *----------------------------------------------------------------------*/
+#if defined(CONFIG_CMD_JFFS2)
+#define CONFIG_SYS_JFFS_CUSTOM_PART			/* board defined part	*/
+#endif
+
+/*------------------------------------------------------------------------
+ * MISC
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_LONGHELP				/* Provide extended help*/
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O buf size */
+#define CONFIG_SYS_MAXARGS		16		/* Max command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot arg buf size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buf size */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE	/* Default load address */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE	/* Start addr for test	*/
+#define CONFIG_SYS_MEMTEST_END		CONFIG_SYS_INIT_SP - 0x00020000
+
+#define CONFIG_SYS_HUSH_PARSER
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/PLU405.h b/qemu/roms/u-boot/include/configs/PLU405.h
new file mode 100644
index 000000000..870516115
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/PLU405.h
@@ -0,0 +1,414 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_PLU405		1	/* ...on a PLU405 board		*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFF80000
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
+
+#define CONFIG_SYS_CLK_FREQ     33333400 /* external frequency to pll   */
+
+#define CONFIG_BAUDRATE		9600
+
+#undef	CONFIG_BOOTARGS
+#undef	CONFIG_BOOTCOMMAND
+
+#define CONFIG_PREBOOT                  /* enable preboot variable      */
+
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#undef  CONFIG_HAS_ETH1
+
+#define CONFIG_PPC4xx_EMAC
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R      1       /* use reset_phy()              */
+
+#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_USB
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_SUPPORT_VFAT
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_RTC_MC146818		/* DS1685 is MC146818 compatible*/
+#define CONFIG_SYS_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address		*/
+
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+
+#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CONFIG_SYS_BASE_BAUD	    691200
+
+/* The following table includes the supported baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+/* Only interrupt boot if space is pressed */
+/* If a long serial cable is connected but */
+/* other end is dead, garbage will be read */
+#define CONFIG_AUTOBOOT_KEYED	1
+#define CONFIG_AUTOBOOT_PROMPT	\
+	"Press SPACE to abort autoboot in %d seconds\n", bootdelay
+#undef CONFIG_AUTOBOOT_DELAY_STR
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+#define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+
+/*
+ * NAND-FLASH stuff
+ */
+#define CONFIG_SYS_NAND_BASE_LIST	{CONFIG_SYS_NAND_BASE}
+#define CONFIG_SYS_MAX_NAND_DEVICE	1         /* Max number of NAND devices */
+#define NAND_BIG_DELAY_US	25
+
+#define CONFIG_SYS_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
+#define CONFIG_SYS_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
+#define CONFIG_SYS_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
+#define CONFIG_SYS_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
+
+#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1       /* ".i" read skips bad blocks   */
+#define CONFIG_SYS_NAND_QUIET          1
+
+/*
+ * PCI stuff
+ */
+#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
+#define PCI_HOST_FORCE  1               /* configure as pci host        */
+#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_HOST	PCI_HOST_FORCE  /* select pci host function     */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
+					/* resource configuration       */
+
+#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
+
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
+#define CONFIG_SYS_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
+#define CONFIG_SYS_PCI_PTM1LA  0x00000000      /* point to sdram               */
+#define CONFIG_SYS_PCI_PTM1MS  0xf8000001      /* 128MB, enable hard-wired to 1 */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CONFIG_SYS_PCI_PTM2LA  0xffc00000      /* point to flash               */
+#define CONFIG_SYS_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
+#define CONFIG_SYS_PCI_PTM2PCI 0x08000000      /* Host: use this pci address   */
+
+/*
+ * IDE/ATA stuff
+ */
+#undef	CONFIG_IDE_8xx_DIRECT		    /* no pcmcia interface required */
+#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
+#define CONFIG_IDE_RESET	1	/* reset for ide supported	*/
+
+#define CONFIG_SYS_IDE_MAXBUS		1		/* max. 1 IDE busses	*/
+/* max. 1 drives per IDE bus */
+#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*1)
+
+#define CONFIG_SYS_ATA_BASE_ADDR	0xF0100000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O */
+#define CONFIG_SYS_ATA_REG_OFFSET	0x0000	/* Offset for normal register access */
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+
+/*
+ * FLASH organization
+ */
+#define FLASH_BASE0_PRELIM	0xFFC00000 /* FLASH bank #0 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms) */
+
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width) */
+#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st addr for flash config cycles */
+#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd addr for flash config cycles */
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard */
+#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard */
+#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector */
+
+/*
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(~(CONFIG_SYS_TEXT_BASE) + 1)
+#define CONFIG_SYS_MALLOC_LEN		(1024 << 10)
+
+/*
+ * Environment Variable setup
+ */
+#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CONFIG_ENV_OFFSET		0x100	/* reseve 0x100 bytes for strapping */
+#define CONFIG_ENV_SIZE		0x700
+
+/*
+ * I2C EEPROM (24WC16) for environment
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM 24WC16 */
+#define CONFIG_SYS_EEPROM_WREN         1
+
+/* 24WC16 */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"    */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The 24WC16 has   */
+					/* 16 byte page write mode using */
+					/* last 4 bits of the address   */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+
+/*
+ * External Bus Controller (EBC) Setup
+ */
+#define CAN0_BA		0xF0000000	    /* CAN0 Base Address	*/
+#define CAN1_BA		0xF0000100	    /* CAN1 Base Address	*/
+#define DUART0_BA	0xF0000400	    /* DUART Base Address       */
+#define DUART1_BA	0xF0000408	    /* DUART Base Address       */
+#define RTC_BA		0xF0000500	    /* RTC Base Address         */
+#define VGA_BA		0xF1000000	    /* Epson VGA Base Address   */
+#define CONFIG_SYS_NAND_BASE	0xF4000000	    /* NAND FLASH Base Address  */
+
+/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
+/* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
+#define CONFIG_SYS_EBC_PB0AP		0x92015480
+/* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000
+
+/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
+#define CONFIG_SYS_EBC_PB1AP		0x92015480
+/* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
+#define CONFIG_SYS_EBC_PB1CR		0xF4018000
+
+/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
+/* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB2AP		0x010053C0
+/* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
+#define CONFIG_SYS_EBC_PB2CR		0xF0018000
+
+/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */
+/* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB3AP		0x010053C0
+/* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB3CR		0xF011A000
+
+/*
+ * FPGA stuff
+ */
+#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0100100	    /* FPGA internal Base Address */
+
+/* FPGA internal regs */
+#define CONFIG_SYS_FPGA_CTRL		0x000
+
+/* FPGA Control Reg */
+#define CONFIG_SYS_FPGA_CTRL_CF_RESET	0x0001
+#define CONFIG_SYS_FPGA_CTRL_WDI	0x0002
+#define CONFIG_SYS_FPGA_CTRL_PS2_RESET 0x0020
+
+#define CONFIG_SYS_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now */
+#define CONFIG_SYS_FPGA_MAX_SIZE	128*1024    /* 128kByte is enough for XC2S50E*/
+
+/* FPGA program pin configuration */
+#define CONFIG_SYS_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
+#define CONFIG_SYS_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output) */
+#define CONFIG_SYS_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output) */
+#define CONFIG_SYS_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input) */
+#define CONFIG_SYS_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input) */
+
+/*
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CONFIG_SYS_TEMP_STACK_OCM	  1
+
+/* On Chip Memory location */
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM  */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * Definitions for GPIO setup (PPC405EP specific)
+ *
+ * GPIO0[0]	- External Bus Controller BLAST output
+ * GPIO0[1-9]	- Instruction trace outputs -> GPIO
+ * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
+ * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
+ * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
+ * GPIO0[24-27] - UART0 control signal inputs/outputs
+ * GPIO0[28-29] - UART1 data signal input/output
+ * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
+ */
+#define CONFIG_SYS_GPIO0_OSRL		0x00000550
+#define CONFIG_SYS_GPIO0_OSRH		0x00000110
+#define CONFIG_SYS_GPIO0_ISR1L		0x00000000
+#define CONFIG_SYS_GPIO0_ISR1H		0x15555445
+#define CONFIG_SYS_GPIO0_TSRL		0x00000000
+#define CONFIG_SYS_GPIO0_TSRH		0x00000000
+#define CONFIG_SYS_GPIO0_TCR		0x77FE0014
+
+#define CONFIG_SYS_DUART_RST		(0x80000000 >> 14)
+#define CONFIG_SYS_EEPROM_WP		(0x80000000 >> 0)
+
+/*
+ * Default speed selection (cpu_plb_opb_ebc) in MHz.
+ * This value will be set if iic boot eprom is disabled.
+ */
+#if 1
+#define PLLMR0_DEFAULT	 PLLMR0_266_133_66_33
+#define PLLMR1_DEFAULT	 PLLMR1_266_133_66_33
+#endif
+#if 0
+#define PLLMR0_DEFAULT	 PLLMR0_200_100_50_33
+#define PLLMR1_DEFAULT	 PLLMR1_200_100_50_33
+#endif
+#if 0
+#define PLLMR0_DEFAULT	 PLLMR0_133_66_66_33
+#define PLLMR1_DEFAULT	 PLLMR1_133_66_66_33
+#endif
+
+/*
+ * PCI OHCI controller
+ */
+#define CONFIG_USB_OHCI_NEW	1
+#define CONFIG_PCI_OHCI		1
+#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"ohci_pci"
+#define CONFIG_USB_STORAGE	1
+
+/*
+ * UBI
+ */
+#define CONFIG_CMD_UBI
+#define CONFIG_RBTREE
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_LZO
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/PM520.h b/qemu/roms/u-boot/include/configs/PM520.h
new file mode 100644
index 000000000..de4621642
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/PM520.h
@@ -0,0 +1,342 @@
+/*
+ * (C) Copyright 2003-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5200
+#define CONFIG_PM520		1	/* PM520 board */
+
+#define	CONFIG_SYS_TEXT_BASE	0xfff00000
+
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33MHz */
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
+#define CONFIG_BAUDRATE		9600	/* ... at 9600 bps */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+
+/*
+ * PCI Mapping:
+ * 0x40000000 - 0x4fffffff - PCI Memory
+ * 0x50000000 - 0x50ffffff - PCI IO Space
+ */
+#define CONFIG_PCI		1
+#define CONFIG_PCI_PNP		1
+#define CONFIG_PCI_SCAN_SHOW	1
+#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1
+
+#define CONFIG_PCI_MEM_BUS	0x40000000
+#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE	0x10000000
+
+#define CONFIG_PCI_IO_BUS	0x50000000
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0x01000000
+
+#define CONFIG_MII		1
+#define CONFIG_EEPRO100		1
+#define CONFIG_SYS_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
+#undef  CONFIG_NS8382X
+
+
+/* Partitions */
+#define CONFIG_DOS_PARTITION
+
+/* USB */
+#if 1
+#define CONFIG_USB_OHCI
+#define CONFIG_USB_STORAGE
+#endif
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_USB
+
+#define CONFIG_CMD_PCI
+
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"hostname=pm520\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk30/ppc_82xx\0"					\
+	"bootfile=/tftpboot/PM520/uImage\0"				\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #1 or #2 */
+
+#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x58
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
+
+/*
+ * RTC configuration
+ */
+#define CONFIG_RTC_PCF8563
+#define CONFIG_SYS_I2C_RTC_ADDR		0x51
+
+#define CONFIG_SYS_DOC_BASE		0xE0000000
+#define CONFIG_SYS_DOC_SIZE		0x00100000
+
+#if defined(CONFIG_BOOT_ROM)
+/*
+ * Flash configuration (8,16 or 32 MB)
+ * TEXT base always at 0xFFF00000
+ * ENV_ADDR always at  0xFFF40000
+ * FLASH_BASE at 0xFA000000 for 64 MB
+ *               0xFC000000 for 32 MB
+ *               0xFD000000 for 16 MB
+ *               0xFD800000 for  8 MB
+ */
+#define CONFIG_SYS_FLASH_BASE		0xFA000000
+#define CONFIG_SYS_FLASH_SIZE		0x04000000
+#define CONFIG_SYS_BOOTROM_BASE	0xFFF00000
+#define CONFIG_SYS_BOOTROM_SIZE	0x00080000
+#define CONFIG_ENV_ADDR		(0xFDF00000 + 0x40000)
+#else
+/*
+ * Flash configuration (8,16 or 32 MB)
+ * TEXT base always at 0xFFF00000
+ * ENV_ADDR always at  0xFFF40000
+ * FLASH_BASE at 0xFC000000 for 64 MB
+ *               0xFE000000 for 32 MB
+ *               0xFF000000 for 16 MB
+ *               0xFF800000 for  8 MB
+ */
+#define CONFIG_SYS_FLASH_BASE		0xFC000000
+#define CONFIG_SYS_FLASH_SIZE		0x04000000
+#define CONFIG_ENV_ADDR		(0xFFF00000 + 0x40000)
+#endif
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
+
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max num of sects on one chip */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
+#define CONFIG_SYS_FLASH_PROTECTION		/* "Real" (hardware) sectors protection */
+
+#define PHYS_FLASH_SECT_SIZE	0x00040000 /* 256 KB sectors (x2) */
+
+#undef CONFIG_FLASH_16BIT	/* Flash is 32-bit */
+
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_SIZE		0x10000
+#define CONFIG_ENV_SECT_SIZE	0x40000
+#define CONFIG_ENV_OVERWRITE	1
+
+/*
+ * Memory map
+ */
+#define CONFIG_SYS_MBAR		0xf0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
+
+/* Use SRAM until RAM will be available */
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */
+
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC	1
+#define CONFIG_MPC5xxx_FEC_MII100
+/*
+ * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
+ */
+/* #define CONFIG_MPC5xxx_FEC_MII10 */
+#define CONFIG_PHY_ADDR		0x00
+
+/*
+ * GPIO configuration
+ */
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x10000004
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
+
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*
+ * Various low-level settings
+ */
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
+
+#if defined(CONFIG_BOOT_ROM)
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_BOOTROM_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_BOOTROM_SIZE
+#define CONFIG_SYS_BOOTCS_CFG		0x00047800
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_BOOTROM_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_BOOTROM_SIZE
+#define CONFIG_SYS_CS1_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS1_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_CS1_CFG		0x0004FF00
+#else
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_CFG		0x0004FF00
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_CS1_START		CONFIG_SYS_DOC_BASE
+#define CONFIG_SYS_CS1_SIZE		CONFIG_SYS_DOC_SIZE
+#define CONFIG_SYS_CS1_CFG		0x00047800
+#endif
+
+#define CONFIG_SYS_CS_BURST		0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE	0x33333333
+
+#define CONFIG_SYS_RESET_ADDRESS	0xff000000
+
+/*-----------------------------------------------------------------------
+ * USB stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_USB_CLOCK	0x0001BBBB
+#define CONFIG_USB_CONFIG	0x00005000
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+
+#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+
+#undef	CONFIG_IDE_RESET		/* reset for ide supported	*/
+#define CONFIG_IDE_PREINIT
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	2	/* max. 2 drive per IDE bus	*/
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
+
+/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
+
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)
+
+/* Interval between registers                                                */
+#define CONFIG_SYS_ATA_STRIDE          4
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/PM826.h b/qemu/roms/u-boot/include/configs/PM826.h
new file mode 100644
index 000000000..6416ad522
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/PM826.h
@@ -0,0 +1,534 @@
+/*
+ * (C) Copyright 2001-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#undef CONFIG_SYS_RAMBOOT
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_PM826		1	/* ...on a PM8260 module	*/
+#define CONFIG_CPM2		1	/* Has a CPM2 */
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xFF000000	/* Standard: boot 64-bit flash */
+#endif
+
+#undef CONFIG_DB_CR826_J30x_ON		/* J30x jumpers on D.B. carrier	*/
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND							\
+	"bootp; "								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
+	"bootm"
+
+/* enable I2C and select the hardware/software driver */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED	50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
+#define I2C_ACTIVE	(iop->pdir |=  0x00010000)
+#define I2C_TRISTATE	(iop->pdir &= ~0x00010000)
+#define I2C_READ	((iop->pdat & 0x00010000) != 0)
+#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00010000; \
+			else    iop->pdat &= ~0x00010000
+#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00020000; \
+			else    iop->pdat &= ~0x00020000
+#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
+
+
+#define CONFIG_RTC_PCF8563
+#define CONFIG_SYS_I2C_RTC_ADDR	0x51
+
+/*
+ * select serial console configuration
+ *
+ * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ *
+ * if CONFIG_CONS_NONE is defined, then the serial console routines must
+ * defined elsewhere (for example, on the cogent platform, there are serial
+ * ports on the motherboard which are used for the serial console - see
+ * cogent/cma101/serial.[ch]).
+ */
+#define CONFIG_CONS_ON_SMC		/* define if console on SMC */
+#undef  CONFIG_CONS_ON_SCC		/* define if console on SCC */
+#undef  CONFIG_CONS_NONE		/* define if console on something else*/
+#define CONFIG_CONS_INDEX	2	/* which serial channel for console */
+
+/*
+ * select ethernet configuration
+ *
+ * if CONFIG_ETHER_ON_SCC is selected, then
+ *   - CONFIG_ETHER_INDEX must be set to the channel number (1-4)
+ *
+ * if CONFIG_ETHER_ON_FCC is selected, then
+ *   - one or more CONFIG_ETHER_ON_FCCx (x=1,2,3) must also be selected
+ *
+ * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
+ */
+#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
+
+#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC       */
+#define	CONFIG_ETHER_INDEX    1		/* which SCC channel for ethernet */
+
+#define	CONFIG_ETHER_ON_FCC		/* define if ether on FCC       */
+/*
+ * - Rx-CLK is CLK11
+ * - Tx-CLK is CLK10
+ */
+#define	CONFIG_ETHER_ON_FCC1
+# define CONFIG_SYS_CMXFCR_MASK1	(CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
+#ifndef CONFIG_DB_CR826_J30x_ON
+# define CONFIG_SYS_CMXFCR_VALUE1	(CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK10)
+#else
+# define CONFIG_SYS_CMXFCR_VALUE1	(CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
+#endif
+/*
+ * - Rx-CLK is CLK15
+ * - Tx-CLK is CLK14
+ */
+#define	CONFIG_ETHER_ON_FCC2
+# define CONFIG_SYS_CMXFCR_MASK2	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
+/*
+ * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
+ * - Enable Full Duplex in FSMR
+ */
+# define CONFIG_SYS_CPMFCR_RAMTYPE	0
+# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+
+/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
+#define CONFIG_8260_CLKIN	64000000	/* in Hz */
+
+#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
+#define CONFIG_BAUDRATE		230400
+#else
+#define CONFIG_BAUDRATE		9600
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_CMD_PCI
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address	*/
+
+#define	CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC	/* "bad" address		*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * Flash and Boot ROM mapping
+ */
+#ifdef CONFIG_FLASH_32MB
+#define	CONFIG_SYS_FLASH0_BASE		0x40000000
+#define	CONFIG_SYS_FLASH0_SIZE		0x02000000
+#else
+#define	CONFIG_SYS_FLASH0_BASE		0xFF000000
+#define	CONFIG_SYS_FLASH0_SIZE		0x00800000
+#endif
+#define	CONFIG_SYS_BOOTROM_BASE	0xFF800000
+#define	CONFIG_SYS_BOOTROM_SIZE	0x00080000
+#define CONFIG_SYS_DOC_BASE		0xFF800000
+#define CONFIG_SYS_DOC_SIZE		0x00100000
+
+/* Flash bank size (for preliminary settings)
+ */
+#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
+#ifdef CONFIG_FLASH_32MB
+#define CONFIG_SYS_MAX_FLASH_SECT	135	/* max num of sects on one chip */
+#else
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
+#endif
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+
+#if 0
+/* Start port with environment in flash; switch to EEPROM later */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE+0x40000)
+#define CONFIG_ENV_SIZE		0x40000
+#define CONFIG_ENV_SECT_SIZE	0x40000
+#else
+/* Final version: environment in EEPROM */
+#define CONFIG_ENV_IS_IN_EEPROM	1
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x58
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+#define CONFIG_ENV_OFFSET		512
+#define CONFIG_ENV_SIZE		(2048 - 512)
+#endif
+
+/*-----------------------------------------------------------------------
+ * Hard Reset Configuration Words
+ *
+ * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
+ * defines for the various registers affected by the HRCW e.g. changing
+ * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
+ */
+#if defined(CONFIG_BOOT_ROM)
+#define CONFIG_SYS_HRCW_MASTER		(HRCW_BPS01 | HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
+#else
+#define CONFIG_SYS_HRCW_MASTER		(HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
+#endif
+
+/* no slaves so just fill with zeros */
+#define CONFIG_SYS_HRCW_SLAVE1		0
+#define CONFIG_SYS_HRCW_SLAVE2		0
+#define CONFIG_SYS_HRCW_SLAVE3		0
+#define CONFIG_SYS_HRCW_SLAVE4		0
+#define CONFIG_SYS_HRCW_SLAVE5		0
+#define CONFIG_SYS_HRCW_SLAVE6		0
+#define CONFIG_SYS_HRCW_SLAVE7		0
+
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xF0000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000  /* Size of used area in DPRAM    */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ *
+ * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE, local SDRAM
+ * is mapped at SDRAM_BASE2_PRELIM.
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_FLASH0_BASE
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+# define CONFIG_SYS_RAMBOOT
+#endif
+
+#ifdef	CONFIG_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_EEPRO100
+#define CONFIG_SYS_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
+#if defined(CONFIG_CMD_KGDB)
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * HIDx - Hardware Implementation-dependent Registers                    2-11
+ *-----------------------------------------------------------------------
+ * HID0 also contains cache control - initially enable both caches and
+ * invalidate contents, then the final state leaves only the instruction
+ * cache enabled. Note that Power-On and Hard reset invalidate the caches,
+ * but Soft reset does not.
+ *
+ * HID1 has only read-only information - nothing to set.
+ */
+#define CONFIG_SYS_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
+				HID0_IFEM|HID0_ABE)
+#define CONFIG_SYS_HID0_FINAL  (HID0_ICE|HID0_IFEM|HID0_ABE)
+#define CONFIG_SYS_HID2        0
+
+/*-----------------------------------------------------------------------
+ * RMR - Reset Mode Register                                     5-5
+ *-----------------------------------------------------------------------
+ * turn on Checkstop Reset Enable
+ */
+#define CONFIG_SYS_RMR         RMR_CSRE
+
+/*-----------------------------------------------------------------------
+ * BCR - Bus Configuration                                       4-25
+ *-----------------------------------------------------------------------
+ */
+
+#define BCR_APD01       0x10000000
+#define CONFIG_SYS_BCR         (BCR_APD01|BCR_ETM|BCR_LETM)    /* 8260 mode */
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration                             4-31
+ *-----------------------------------------------------------------------
+ */
+#if 0
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_CS10PC01)
+#else
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DPPC10|SIUMCR_APPC10)
+#endif
+
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control                             4-35
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
+#else
+#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+			 SYPCR_SWRI|SYPCR_SWP)
+#endif /* CONFIG_WATCHDOG */
+
+/*-----------------------------------------------------------------------
+ * TMCNTSC - Time Counter Status and Control                     4-40
+ *-----------------------------------------------------------------------
+ * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
+ * and enable Time Counter
+ */
+#define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control                 4-42
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
+ * Periodic timer
+ */
+#define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control                                   9-8
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_SCCR        (SCCR_DFBRG00)
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration                         13-7
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RCCR        0
+
+/*
+ * Init Memory Controller:
+ *
+ * Bank Bus     Machine PortSz  Device
+ * ---- ---     ------- ------  ------
+ *  0   60x     GPCM    64 bit  FLASH
+ *  1   60x     SDRAM   64 bit  SDRAM
+ *
+ */
+
+	/* Initialize SDRAM on local bus
+	 */
+#define CONFIG_SYS_INIT_LOCAL_SDRAM
+
+
+/* Minimum mask to separate preliminary
+ * address ranges for CS[0:2]
+ */
+#define CONFIG_SYS_MIN_AM_MASK	0xC0000000
+
+/*
+ * we use the same values for 32 MB and 128 MB SDRAM
+ * refresh rate = 7.73 uS (64 MHz Bus Clock)
+ */
+#define CONFIG_SYS_MPTPR       0x2000
+#define CONFIG_SYS_PSRT        0x0E
+
+#define CONFIG_SYS_MRS_OFFS	0x00000000
+
+
+#if defined(CONFIG_BOOT_ROM)
+/*
+ * Bank 0 - Boot ROM (8 bit wide)
+ */
+#define CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
+			 BRx_PS_8			|\
+			 BRx_MS_GPCM_P			|\
+			 BRx_V)
+
+#define CONFIG_SYS_OR0_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE)	|\
+			 ORxG_CSNT			|\
+			 ORxG_ACS_DIV1			|\
+			 ORxG_SCY_3_CLK			|\
+			 ORxG_EHTR			|\
+			 ORxG_TRLX)
+
+/*
+ * Bank 1 - Flash (64 bit wide)
+ */
+#define CONFIG_SYS_BR1_PRELIM	((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)	|\
+			 BRx_PS_64			|\
+			 BRx_MS_GPCM_P			|\
+			 BRx_V)
+
+#define CONFIG_SYS_OR1_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)	|\
+			 ORxG_CSNT			|\
+			 ORxG_ACS_DIV1			|\
+			 ORxG_SCY_3_CLK			|\
+			 ORxG_EHTR			|\
+			 ORxG_TRLX)
+
+#else	/* ! CONFIG_BOOT_ROM */
+
+/*
+ * Bank 0 - Flash (64 bit wide)
+ */
+#define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)  |\
+			 BRx_PS_64                      |\
+			 BRx_MS_GPCM_P                  |\
+			 BRx_V)
+
+#define CONFIG_SYS_OR0_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)	|\
+			 ORxG_CSNT                      |\
+			 ORxG_ACS_DIV1                  |\
+			 ORxG_SCY_3_CLK                 |\
+			 ORxG_EHTR                      |\
+			 ORxG_TRLX)
+
+/*
+ * Bank 1 - Disk-On-Chip
+ */
+#define CONFIG_SYS_BR1_PRELIM	((CONFIG_SYS_DOC_BASE & BRx_BA_MSK)	|\
+			 BRx_PS_8			|\
+			 BRx_MS_GPCM_P			|\
+			 BRx_V)
+
+#define CONFIG_SYS_OR1_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE)	|\
+			 ORxG_CSNT			|\
+			 ORxG_ACS_DIV1			|\
+			 ORxG_SCY_3_CLK			|\
+			 ORxG_EHTR			|\
+			 ORxG_TRLX)
+
+#endif /* CONFIG_BOOT_ROM */
+
+/* Bank 2 - SDRAM
+ */
+
+#ifndef CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_BR2_PRELIM  ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)  |\
+			 BRx_PS_64                      |\
+			 BRx_MS_SDRAM_P                 |\
+			 BRx_V)
+
+	/* SDRAM initialization values for 8-column chips
+	 */
+#define CONFIG_SYS_OR2_8COL    (CONFIG_SYS_MIN_AM_MASK	        |\
+			 ORxS_BPD_4                     |\
+			 ORxS_ROWST_PBI0_A9             |\
+			 ORxS_NUMR_12)
+
+#define CONFIG_SYS_PSDMR_8COL  (PSDMR_SDAM_A13_IS_A5           |\
+			 PSDMR_BSMA_A14_A16             |\
+			 PSDMR_SDA10_PBI0_A10           |\
+			 PSDMR_RFRC_7_CLK               |\
+			 PSDMR_PRETOACT_2W              |\
+			 PSDMR_ACTTORW_1W               |\
+			 PSDMR_LDOTOPRE_1C              |\
+			 PSDMR_WRC_1C                   |\
+			 PSDMR_CL_2)
+
+	/* SDRAM initialization values for 9-column chips
+	 */
+#define CONFIG_SYS_OR2_9COL    (CONFIG_SYS_MIN_AM_MASK                |\
+			 ORxS_BPD_4                     |\
+			 ORxS_ROWST_PBI0_A7             |\
+			 ORxS_NUMR_13)
+
+#define CONFIG_SYS_PSDMR_9COL  (PSDMR_SDAM_A14_IS_A5           |\
+			 PSDMR_BSMA_A13_A15             |\
+			 PSDMR_SDA10_PBI0_A9            |\
+			 PSDMR_RFRC_7_CLK               |\
+			 PSDMR_PRETOACT_2W              |\
+			 PSDMR_ACTTORW_1W               |\
+			 PSDMR_LDOTOPRE_1C              |\
+			 PSDMR_WRC_1C                   |\
+			 PSDMR_CL_2)
+
+#define CONFIG_SYS_OR2_PRELIM   CONFIG_SYS_OR2_9COL
+#define CONFIG_SYS_PSDMR        CONFIG_SYS_PSDMR_9COL
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/PM828.h b/qemu/roms/u-boot/include/configs/PM828.h
new file mode 100644
index 000000000..e17fbfbbf
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/PM828.h
@@ -0,0 +1,528 @@
+/*
+ * (C) Copyright 2001-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#undef CONFIG_SYS_RAMBOOT
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_PM828		1	/* ...on a PM828 module */
+#define CONFIG_CPM2		1	/* Has a CPM2 */
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0x40000000	/* Standard: boot 64-bit flash */
+#endif
+
+#undef CONFIG_DB_CR826_J30x_ON		/* J30x jumpers on D.B. carrier */
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND							\
+	"bootp;"								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"	\
+	"bootm"
+
+/* enable I2C and select the hardware/software driver */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED	50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
+#define I2C_ACTIVE	(iop->pdir |=  0x00010000)
+#define I2C_TRISTATE	(iop->pdir &= ~0x00010000)
+#define I2C_READ	((iop->pdat & 0x00010000) != 0)
+#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00010000; \
+			else	iop->pdat &= ~0x00010000
+#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00020000; \
+			else	iop->pdat &= ~0x00020000
+#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
+
+
+#define CONFIG_RTC_PCF8563
+#define CONFIG_SYS_I2C_RTC_ADDR	0x51
+
+/*
+ * select serial console configuration
+ *
+ * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ *
+ * if CONFIG_CONS_NONE is defined, then the serial console routines must
+ * defined elsewhere (for example, on the cogent platform, there are serial
+ * ports on the motherboard which are used for the serial console - see
+ * cogent/cma101/serial.[ch]).
+ */
+#define CONFIG_CONS_ON_SMC		/* define if console on SMC */
+#undef	CONFIG_CONS_ON_SCC		/* define if console on SCC */
+#undef	CONFIG_CONS_NONE		/* define if console on something else*/
+#define CONFIG_CONS_INDEX	2	/* which serial channel for console */
+
+/*
+ * select ethernet configuration
+ *
+ * if CONFIG_ETHER_ON_SCC is selected, then
+ *   - CONFIG_ETHER_INDEX must be set to the channel number (1-4)
+ *
+ * if CONFIG_ETHER_ON_FCC is selected, then
+ *   - one or more CONFIG_ETHER_ON_FCCx (x=1,2,3) must also be selected
+ *
+ * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
+ */
+#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
+
+#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC	*/
+#define CONFIG_ETHER_INDEX    1		/* which SCC channel for ethernet */
+
+#define CONFIG_ETHER_ON_FCC		/* define if ether on FCC	*/
+/*
+ * - Rx-CLK is CLK11
+ * - Tx-CLK is CLK10
+ */
+#define CONFIG_ETHER_ON_FCC1
+# define CONFIG_SYS_CMXFCR_MASK1	(CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
+#ifndef CONFIG_DB_CR826_J30x_ON
+# define CONFIG_SYS_CMXFCR_VALUE1	(CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK10)
+#else
+# define CONFIG_SYS_CMXFCR_VALUE1	(CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
+#endif
+/*
+ * - Rx-CLK is CLK15
+ * - Tx-CLK is CLK14
+ */
+#define CONFIG_ETHER_ON_FCC2
+# define CONFIG_SYS_CMXFCR_MASK2	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
+/*
+ * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
+ * - Enable Full Duplex in FSMR
+ */
+# define CONFIG_SYS_CPMFCR_RAMTYPE	0
+# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+
+/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
+#define CONFIG_8260_CLKIN	100000000	/* in Hz */
+
+#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
+#define CONFIG_BAUDRATE		230400
+#else
+#define CONFIG_BAUDRATE		9600
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_CMD_PCI
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END 0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+
+#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC	/* "bad" address		*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	     (8 << 20)	     /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * Flash and Boot ROM mapping
+ */
+
+#define CONFIG_SYS_BOOTROM_BASE	0xFF800000
+#define CONFIG_SYS_BOOTROM_SIZE	0x00080000
+#define CONFIG_SYS_FLASH0_BASE		0x40000000
+#define CONFIG_SYS_FLASH0_SIZE		0x02000000
+#define CONFIG_SYS_DOC_BASE		0xFF800000
+#define CONFIG_SYS_DOC_SIZE		0x00100000
+
+
+/* Flash bank size (for preliminary settings)
+ */
+#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	135	/* max num of sects on one chip */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
+
+#if 0
+/* Start port with environment in flash; switch to EEPROM later */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE+0x40000)
+#define CONFIG_ENV_SIZE		0x40000
+#define CONFIG_ENV_SECT_SIZE	0x40000
+#else
+/* Final version: environment in EEPROM */
+#define CONFIG_ENV_IS_IN_EEPROM	1
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x58
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+#define CONFIG_ENV_OFFSET		512
+#define CONFIG_ENV_SIZE		(2048 - 512)
+#endif
+
+/*-----------------------------------------------------------------------
+ * Hard Reset Configuration Words
+ *
+ * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
+ * defines for the various registers affected by the HRCW e.g. changing
+ * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
+ */
+#if defined(CONFIG_BOOT_ROM)
+#define CONFIG_SYS_HRCW_MASTER		(HRCW_BPS01 | HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
+#else
+#define CONFIG_SYS_HRCW_MASTER		(HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
+#endif
+
+/* no slaves so just fill with zeros */
+#define CONFIG_SYS_HRCW_SLAVE1		0
+#define CONFIG_SYS_HRCW_SLAVE2		0
+#define CONFIG_SYS_HRCW_SLAVE3		0
+#define CONFIG_SYS_HRCW_SLAVE4		0
+#define CONFIG_SYS_HRCW_SLAVE5		0
+#define CONFIG_SYS_HRCW_SLAVE6		0
+#define CONFIG_SYS_HRCW_SLAVE7		0
+
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xF0000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ *
+ * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE, local SDRAM
+ * is mapped at SDRAM_BASE2_PRELIM.
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_FLASH0_BASE
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+# define CONFIG_SYS_RAMBOOT
+#endif
+
+#ifdef	CONFIG_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_EEPRO100
+#define CONFIG_SYS_RX_ETH_BUFFER	8		/* use 8 rx buffer on eepro100	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPU		*/
+#if defined(CONFIG_CMD_KGDB)
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * HIDx - Hardware Implementation-dependent Registers			 2-11
+ *-----------------------------------------------------------------------
+ * HID0 also contains cache control - initially enable both caches and
+ * invalidate contents, then the final state leaves only the instruction
+ * cache enabled. Note that Power-On and Hard reset invalidate the caches,
+ * but Soft reset does not.
+ *
+ * HID1 has only read-only information - nothing to set.
+ */
+#define CONFIG_SYS_HID0_INIT	(HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
+				HID0_IFEM|HID0_ABE)
+#define CONFIG_SYS_HID0_FINAL	(HID0_ICE|HID0_IFEM|HID0_ABE)
+#define CONFIG_SYS_HID2	0
+
+/*-----------------------------------------------------------------------
+ * RMR - Reset Mode Register					 5-5
+ *-----------------------------------------------------------------------
+ * turn on Checkstop Reset Enable
+ */
+#define CONFIG_SYS_RMR		RMR_CSRE
+
+/*-----------------------------------------------------------------------
+ * BCR - Bus Configuration					 4-25
+ *-----------------------------------------------------------------------
+ */
+
+#define BCR_APD01	0x10000000
+#define CONFIG_SYS_BCR		(BCR_APD01|BCR_ETM|BCR_LETM)	/* 8260 mode */
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				 4-31
+ *-----------------------------------------------------------------------
+ */
+#if 0
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_CS10PC01)
+#else
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DPPC10|SIUMCR_APPC10)
+#endif
+
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				 4-35
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
+#else
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+			 SYPCR_SWRI|SYPCR_SWP)
+#endif /* CONFIG_WATCHDOG */
+
+/*-----------------------------------------------------------------------
+ * TMCNTSC - Time Counter Status and Control			 4-40
+ *-----------------------------------------------------------------------
+ * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
+ * and enable Time Counter
+ */
+#define CONFIG_SYS_TMCNTSC	(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		 4-42
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
+ * Periodic timer
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS|PISCR_PTF|PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control					 9-8
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_SCCR	(SCCR_DFBRG00)
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration				13-7
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RCCR	0
+
+/*
+ * Init Memory Controller:
+ *
+ * Bank Bus	Machine PortSz	Device
+ * ---- ---	------- ------	------
+ *  0	60x	GPCM	64 bit	FLASH
+ *  1	60x	SDRAM	64 bit	SDRAM
+ *
+ */
+
+	/* Initialize SDRAM on local bus
+	 */
+#define CONFIG_SYS_INIT_LOCAL_SDRAM
+
+
+/* Minimum mask to separate preliminary
+ * address ranges for CS[0:2]
+ */
+#define CONFIG_SYS_MIN_AM_MASK 0xC0000000
+
+/*
+ * we use the same values for 32 MB and 128 MB SDRAM
+ * refresh rate = 7.68 uS (100 MHz Bus Clock)
+ */
+#define CONFIG_SYS_MPTPR	0x2000
+#define CONFIG_SYS_PSRT	0x16
+
+#define CONFIG_SYS_MRS_OFFS	0x00000000
+
+
+#if defined(CONFIG_BOOT_ROM)
+/*
+ * Bank 0 - Boot ROM (8 bit wide)
+ */
+#define CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
+			 BRx_PS_8			|\
+			 BRx_MS_GPCM_P			|\
+			 BRx_V)
+
+#define CONFIG_SYS_OR0_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE)	|\
+			 ORxG_CSNT			|\
+			 ORxG_ACS_DIV1			|\
+			 ORxG_SCY_5_CLK			|\
+			 ORxG_EHTR			|\
+			 ORxG_TRLX)
+
+/*
+ * Bank 1 - Flash (64 bit wide)
+ */
+#define CONFIG_SYS_BR1_PRELIM	((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)	|\
+			 BRx_PS_64			|\
+			 BRx_MS_GPCM_P			|\
+			 BRx_V)
+
+#define CONFIG_SYS_OR1_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)	|\
+			 ORxG_CSNT			|\
+			 ORxG_ACS_DIV1			|\
+			 ORxG_SCY_5_CLK			|\
+			 ORxG_EHTR			|\
+			 ORxG_TRLX)
+
+#else	/* ! CONFIG_BOOT_ROM */
+
+/*
+ * Bank 0 - Flash (64 bit wide)
+ */
+#define CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)	|\
+			 BRx_PS_64			|\
+			 BRx_MS_GPCM_P			|\
+			 BRx_V)
+
+#define CONFIG_SYS_OR0_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)	|\
+			 ORxG_CSNT			|\
+			 ORxG_ACS_DIV1			|\
+			 ORxG_SCY_5_CLK			|\
+			 ORxG_EHTR			|\
+			 ORxG_TRLX)
+
+/*
+ * Bank 1 - Disk-On-Chip
+ */
+#define CONFIG_SYS_BR1_PRELIM	((CONFIG_SYS_DOC_BASE & BRx_BA_MSK)	|\
+			 BRx_PS_8			|\
+			 BRx_MS_GPCM_P			|\
+			 BRx_V)
+
+#define CONFIG_SYS_OR1_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE)	|\
+			 ORxG_CSNT			|\
+			 ORxG_ACS_DIV1			|\
+			 ORxG_SCY_5_CLK			|\
+			 ORxG_EHTR			|\
+			 ORxG_TRLX)
+
+#endif /* CONFIG_BOOT_ROM */
+
+/* Bank 2 - SDRAM
+ */
+
+#ifndef CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_BR2_PRELIM	((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)	|\
+			 BRx_PS_64			|\
+			 BRx_MS_SDRAM_P			|\
+			 BRx_V)
+
+	/* SDRAM initialization values for 8-column chips
+	 */
+#define CONFIG_SYS_OR2_8COL	(CONFIG_SYS_MIN_AM_MASK		|\
+			 ORxS_BPD_4			|\
+			 ORxS_ROWST_PBI0_A9		|\
+			 ORxS_NUMR_12)
+
+#define CONFIG_SYS_PSDMR_8COL	(PSDMR_SDAM_A13_IS_A5		|\
+			 PSDMR_BSMA_A14_A16		|\
+			 PSDMR_SDA10_PBI0_A10		|\
+			 PSDMR_RFRC_7_CLK		|\
+			 PSDMR_PRETOACT_2W		|\
+			 PSDMR_ACTTORW_2W		|\
+			 PSDMR_LDOTOPRE_1C		|\
+			 PSDMR_WRC_1C			|\
+			 PSDMR_CL_2)
+
+	/* SDRAM initialization values for 9-column chips
+	 */
+#define CONFIG_SYS_OR2_9COL	(CONFIG_SYS_MIN_AM_MASK		|\
+			 ORxS_BPD_4			|\
+			 ORxS_ROWST_PBI0_A7		|\
+			 ORxS_NUMR_13)
+
+#define CONFIG_SYS_PSDMR_9COL	(PSDMR_SDAM_A14_IS_A5		|\
+			 PSDMR_BSMA_A13_A15		|\
+			 PSDMR_SDA10_PBI0_A9		|\
+			 PSDMR_RFRC_7_CLK		|\
+			 PSDMR_PRETOACT_2W		|\
+			 PSDMR_ACTTORW_2W		|\
+			 PSDMR_LDOTOPRE_1C		|\
+			 PSDMR_WRC_1C			|\
+			 PSDMR_CL_2)
+
+#define CONFIG_SYS_OR2_PRELIM	 CONFIG_SYS_OR2_9COL
+#define CONFIG_SYS_PSDMR	 CONFIG_SYS_PSDMR_9COL
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/PMC405.h b/qemu/roms/u-boot/include/configs/PMC405.h
new file mode 100644
index 000000000..c68d9a6ec
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/PMC405.h
@@ -0,0 +1,318 @@
+/*
+ * (C) Copyright 2001-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+
+#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_PMC405		1	/* ...on a PMC405 board		*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFF80000
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
+
+#define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/
+
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+/* Only interrupt boot if space is pressed. */
+#define CONFIG_AUTOBOOT_KEYED 1
+#define CONFIG_AUTOBOOT_PROMPT	\
+	"Press SPACE to abort autoboot in %d seconds\n", bootdelay
+#undef CONFIG_AUTOBOOT_DELAY_STR
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
+#undef CONFIG_BOOTARGS
+#undef CONFIG_BOOTCOMMAND
+
+#define CONFIG_PREBOOT			/* enable preboot variable	*/
+
+#define CFG_BOOTM_LEN		0x1000000 /* support booting of huge images */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE 1	/* allow baudrate change	*/
+
+#undef  CONFIG_HAS_ETH1
+
+#define CONFIG_PPC4xx_EMAC
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP	1	/* disable sleep mode in LXT971	*/
+#define CONFIG_RESET_PHY_R	1	/* use reset_phy()		*/
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_UNIVERSE
+#define CONFIG_CMD_EEPROM
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_RTC_MC146818		/* DS1685 is MC146818 compatible */
+#define CONFIG_SYS_RTC_REG_BASE_ADDR	0xF0000500 /* RTC Base Address */
+
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+
+#undef CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	512		/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Argument Buffer Sz */
+
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device */
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console info */
+
+#define CONFIG_AUTO_COMPLETE		1       /* add autocompletion support */
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+
+#undef CONFIG_SYS_EXT_SERIAL_CLOCK		/* no external serial clock */
+#define CONFIG_SYS_BASE_BAUD	806400
+
+/* The following table includes the supported baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1	/* To use extended board_into (bd_t) */
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history */
+#define CONFIG_LOOPW		1	/* enable loopw command */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+#define CONFIG_SYS_RX_ETH_BUFFER	16
+
+/*
+ * PCI stuff
+ */
+#define PCI_HOST_ADAPTER	0	/* configure as pci adapter	*/
+#define PCI_HOST_FORCE		1	/* configure as pci host	*/
+#define PCI_HOST_AUTO		2	/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_HOST	PCI_HOST_AUTO   /* select pci host function	*/
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+					/* resource configuration	*/
+
+#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
+
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1	/* don't skip host bridge config */
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH 0x0408 /* PCI Device ID */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID_MONARCH 0x0409 /* PCI Device ID */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID pmc405_pci_subsys_deviceid()
+
+#define CONFIG_SYS_PCI_CLASSCODE       0x0b20 /* Processor/PPC */
+
+#define CONFIG_SYS_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram	*/
+#define CONFIG_SYS_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address */
+#define CONFIG_SYS_PCI_PTM2LA  0xef000000	/* point to internal regs */
+#define CONFIG_SYS_PCI_PTM2MS  0xff000001	/* 16MB, enable */
+#define CONFIG_SYS_PCI_PTM2PCI 0x00000000	/* Host: use this pci address */
+
+#define CONFIG_PCI_4xx_PTM_OVERWRITE	1 /* overwrite PTMx settings by env */
+
+/*
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(~(CONFIG_SYS_TEXT_BASE) + 1)
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024) /* 128 kB for malloc() */
+
+#define CONFIG_PRAM			0 /* use pram variable to overwrite */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20) /* Initial Memory map for Linux */
+
+/*
+ * FLASH organization
+ */
+#define CONFIG_SYS_FLASH_BASE		0xFE000000
+#define CONFIG_SYS_FLASH_INCREMENT	0x01000000
+
+#define CONFIG_SYS_FLASH_CFI		1 /* Flash is CFI conformant */
+#define CONFIG_FLASH_CFI_DRIVER		1 /* Use the common driver */
+#define CONFIG_SYS_FLASH_PROTECTION	1 /* don't use hardware protection */
+#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST {{0xfff80000, 0x80000}}
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (faster) */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2 /* max num of flash banks */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE, \
+			CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_INCREMENT}
+#define CONFIG_SYS_MAX_FLASH_SECT	128 /* max num of sects on one chip */
+#define CONFIG_SYS_FLASH_EMPTY_INFO	/* print 'E' for empty sector on fli */
+
+/*
+ * Environment Variable setup
+ */
+#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+
+/* environment starts at the beginning of the EEPROM */
+#define CONFIG_ENV_OFFSET	0x000
+#define CONFIG_ENV_SIZE		0x800 /* 2048 bytes may be used for env vars */
+
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xF0000500	/* NVRAM base address */
+#define CONFIG_SYS_NVRAM_SIZE		242		/* NVRAM size */
+
+/*
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		100000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT24W16 */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address */
+/* mask of address bits that overflow into the "EEPROM chip address" */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24W16 has */
+					/* 16 byte page write mode using*/
+					/* last	4 bits of the address */
+
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
+
+/*
+ * External Bus Controller (EBC) Setup
+ */
+#define FLASH0_BA	0xFF000000	/* FLASH 0 Base Address	*/
+#define FLASH1_BA	0xFE000000	/* FLASH 1 Base Address	*/
+#define CAN_BA		0xF0000000	/* CAN Base Addres	*/
+#define RTC_BA		0xF0000500	/* RTC Base Address	*/
+#define NVRAM_BA	0xF0200000	/* NVRAM Base Address	*/
+
+/* Memory Bank 0 (Flash Bank 0) initialization */
+#define CONFIG_SYS_EBC_PB0AP	0x92015480
+/* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB0CR	(FLASH0_BA | 0x9A000)
+
+/* Memory Bank 1 (Flash Bank 1) initialization */
+#define CONFIG_SYS_EBC_PB1AP	0x92015480
+/* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/
+#define CONFIG_SYS_EBC_PB1CR	(FLASH1_BA | 0x9A000)
+
+/* Memory Bank 2 (CAN0, 1, RTC) initialization */
+/* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0      */
+#define CONFIG_SYS_EBC_PB2AP	0x03000440
+/* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
+#define CONFIG_SYS_EBC_PB2CR	(CAN_BA | 0x18000)
+
+/* Memory Bank 3 -> unused */
+
+/* Memory Bank 4 (NVRAM) initialization */
+/* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */
+#define CONFIG_SYS_EBC_PB4AP	0x03000440
+/* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
+#define CONFIG_SYS_EBC_PB4CR	(NVRAM_BA | 0x18000)
+
+/*
+ * FPGA stuff
+ */
+/* FPGA program pin configuration */
+#define CONFIG_SYS_FPGA_PRG		0x04000000 /* JTAG TMS pin (output) */
+#define CONFIG_SYS_FPGA_CLK		0x02000000 /* JTAG TCK pin (output) */
+#define CONFIG_SYS_FPGA_DATA		0x01000000 /* JTAG TDO pin (output) */
+#define CONFIG_SYS_FPGA_INIT		0x00010000 /* unused (ppc input) */
+#define CONFIG_SYS_FPGA_DONE		0x00008000 /* JTAG TDI pin (input) */
+
+/* pass Ethernet MAC to VxWorks */
+#define CONFIG_SYS_VXWORKS_MAC_PTR	0x00000000
+
+/*
+ * GPIOs
+ */
+#define CONFIG_SYS_VPEN			(0x80000000 >>  3) /* GPIO3 */
+#define CONFIG_SYS_NONMONARCH		(0x80000000 >> 14) /* GPIO14 */
+#define CONFIG_SYS_XEREADY		(0x80000000 >> 15) /* GPIO15 */
+#define CONFIG_SYS_INTA_FAKE		(0x80000000 >> 19) /* GPIO19 */
+#define CONFIG_SYS_SELF_RST		(0x80000000 >> 21) /* GPIO21 */
+#define CONFIG_SYS_REV1_2		(0x80000000 >> 23) /* GPIO23 */
+
+/*
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+
+/* use on chip memory (OCM) for temperary stack until sdram is tested */
+#define CONFIG_SYS_TEMP_STACK_OCM	1
+
+/* On Chip Memory location */
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+
+/* inside of SDRAM */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR
+
+/* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE		CONFIG_SYS_OCM_DATA_SIZE
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/PMC405DE.h b/qemu/roms/u-boot/include/configs/PMC405DE.h
new file mode 100644
index 000000000..94b95475a
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/PMC405DE.h
@@ -0,0 +1,364 @@
+/*
+ * (C) Copyright 2009
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd.eu
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_PMC405DE		1	/* ...on a PMC405DE board	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/
+
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+#undef  CONFIG_BOOTARGS
+#undef  CONFIG_BOOTCOMMAND
+
+#define CONFIG_PREBOOT			/* enable preboot variable	*/
+
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change*/
+
+#define CONFIG_HAS_ETH1
+
+#define CONFIG_PPC4xx_EMAC
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		1	/* PHY address			*/
+#define CONFIG_PHY1_ADDR	2	/* 2nd PHY address		*/
+
+#define CONFIG_SYS_RX_ETH_BUFFER	16 /* use 16 rx buffer on 405 emac */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_CHIP_CONFIG
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+
+#undef  CONFIG_WATCHDOG			/* watchdog disabled */
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0 */
+#define CONFIG_PRAM		0
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP
+
+#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
+
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console info */
+
+#define CONFIG_SYS_MEMTEST_START	0x0100000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x3000000 /* 1 ... 48 MB in DRAM */
+
+#define CONFIG_CONS_INDEX	2	/* Use UART1			*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+
+#undef  CONFIG_SYS_EXT_SERIAL_CLOCK
+#define CONFIG_SYS_BASE_BAUD		691200
+
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1	/* To use extended board_into (bd_t) */
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history     */
+#define CONFIG_LOOPW		1	/* enable loopw command         */
+#define CONFIG_MX_CYCLIC	1	/* enable mdc/mwc commands      */
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+#define CONFIG_AUTOBOOT_KEYED	1
+#define CONFIG_AUTOBOOT_PROMPT	\
+	"Press SPACE to abort autoboot in %d seconds\n", bootdelay
+#undef CONFIG_AUTOBOOT_DELAY_STR
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
+/*
+ * PCI stuff
+ */
+#define PCI_HOST_ADAPTER	0	/* configure as pci adapter	*/
+#define PCI_HOST_FORCE		1	/* configure as pci host	*/
+#define PCI_HOST_AUTO		2	/* detected via arbiter enable	*/
+
+#define CONFIG_PCI		/* include pci support			*/
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_HOST	PCI_HOST_AUTO  /* select pci host function	*/
+#define CONFIG_PCI_PNP		/* do (not) pci plug-and-play		*/
+
+#define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup		*/
+
+/*
+ * PCI identification
+ */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID		PCI_VENDOR_ID_ESDGMBH
+#define CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH 0x040e /* Dev ID: Non-Monarch */
+#define CONFIG_SYS_PCI_SUBSYS_ID_MONARCH 0x040f	/* Dev ID: Monarch */
+#define CONFIG_SYS_PCI_CLASSCODE_NONMONARCH	PCI_CLASS_PROCESSOR_POWERPC
+#define CONFIG_SYS_PCI_CLASSCODE_MONARCH	PCI_CLASS_BRIDGE_HOST
+
+#define CONFIG_SYS_PCI_CLASSCODE CONFIG_SYS_PCI_CLASSCODE_MONARCH
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID CONFIG_SYS_PCI_SUBSYS_ID_MONARCH
+
+#define CONFIG_SYS_PCI_PTM1LA  0x00000000      /* point to sdram */
+#define CONFIG_SYS_PCI_PTM1MS  0xfc000001      /* 64MB, enable=1 */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address */
+#define CONFIG_SYS_PCI_PTM2LA  0xef000000      /* point to CPLD, GPIO */
+#define CONFIG_SYS_PCI_PTM2MS  0xff000001      /* 16MB, enable=1 */
+#define CONFIG_SYS_PCI_PTM2PCI 0x04000000      /* Host: use this pci address */
+
+#define CONFIG_PCI_4xx_PTM_OVERWRITE	1 /* overwrite PTMx settings by env */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)
+/*
+ * FLASH organization
+ */
+#define CONFIG_SYS_FLASH_CFI		1	/* CFI compatible */
+#define CONFIG_FLASH_CFI_DRIVER		1	/* Use common CFI driver */
+
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max. no. memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max sectors per chip */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* erase timeout (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* write timeout (in ms) */
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* buffered writes (faster) */
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* hardware flash protection */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO	1 /* 'E' for empty sector (flinfo) */
+#define CONFIG_SYS_FLASH_QUIET_TEST	1 /* don't warn upon unknown flash */
+
+
+/*
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xfe000000
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(~(CONFIG_SYS_TEXT_BASE) + 1)
+#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)
+
+/*
+ * Environment in EEPROM setup
+ */
+#define CONFIG_ENV_IS_IN_EEPROM		1
+#define CONFIG_ENV_OFFSET		0x100
+#define CONFIG_ENV_SIZE			0x700
+
+/*
+ * I2C EEPROM (24W16) for environment
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM 24W16	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address */
+/* mask of address bits that overflow into the "EEPROM chip address" */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has */
+					/* 16 byte page write mode using*/
+					/* last 4 bits of the address */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10 /* and takes up to 10 msec */
+#define CONFIG_SYS_EEPROM_WREN		1
+
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR	0x50
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET	0x40
+#define CONFIG_4xx_CONFIG_BLOCKSIZE		0x20
+
+/*
+ * RTC
+ */
+#define CONFIG_RTC_RX8025
+
+/*
+ * External Bus Controller (EBC) Setup
+ * (max. 55MHZ EBC clock)
+ */
+/* Memory Bank 0 (NOR flash) BAS=0xFE0,BS=32MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB0AP		0x03017200
+#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_FLASH_BASE | 0xba000)
+
+/* Memory Bank 1 (CPLD) BAS=0xEF0,BS=16MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_CPLD_BASE		0xef000000
+#define CONFIG_SYS_EBC_PB1AP		0x00800000
+#define CONFIG_SYS_EBC_PB1CR		(CONFIG_SYS_CPLD_BASE | 0x18000)
+
+/*
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CONFIG_SYS_TEMP_STACK_OCM	  1
+
+/* On Chip Memory location */
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+/* inside SDRAM */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR
+/* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE		CONFIG_SYS_OCM_DATA_SIZE
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * GPIO Configuration
+ */
+#define CONFIG_SYS_4xx_GPIO_TABLE {                  /* GPIO    Alt1       */ \
+{                                                                             \
+/* GPIO Core 0 */                                                             \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO0   PerBLast   */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO1   TS1E       */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO2   TS2E       */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO3   TS1O       */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO4   TS2O       */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1 },      /* GPIO5   TS3        */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1 },      /* GPIO6   TS4        */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1 },      /* GPIO7   TS5        */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO8   TS6        */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1 },      /* GPIO9   TrcClk     */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10  PerCS1     */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO11  PerCS2     */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO12  PerCS3     */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO13  PerCS4     */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO14  PerAddr03  */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO15  PerAddr04  */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16  PerAddr05  */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17  IRQ0       */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18  IRQ1       */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19  IRQ2       */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO20  IRQ3       */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO21  IRQ4       */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO22  IRQ5       */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO23  IRQ6       */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24  UART0_DCD  */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO25  UART0_DSR  */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO26  UART0_RI   */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO27  UART0_DTR  */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28  UART1_Rx   */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29  UART1_Tx   */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO30  RejectPkt0 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO31  RejectPkt1 */ \
+}                                                                             \
+}
+
+#define CONFIG_SYS_GPIO_HWREV_MASK	(0xf0000000 >> 1)	/* GPIO1..4 */
+#define CONFIG_SYS_GPIO_HWREV_SHIFT	27
+#define CONFIG_SYS_GPIO_LEDRUN_N	(0x80000000 >> 5)	/* GPIO5 */
+#define CONFIG_SYS_GPIO_LEDA_N		(0x80000000 >> 6)	/* GPIO6 */
+#define CONFIG_SYS_GPIO_LEDB_N		(0x80000000 >> 7)	/* GPIO7 */
+#define CONFIG_SYS_GPIO_SELFRST_N	(0x80000000 >> 8)	/* GPIO8 */
+#define CONFIG_SYS_GPIO_EEPROM_WP	(0x80000000 >> 9)	/* GPIO9 */
+#define CONFIG_SYS_GPIO_MONARCH_N	(0x80000000 >> 11)	/* GPIO11 */
+#define CONFIG_SYS_GPIO_EREADY		(0x80000000 >> 12)	/* GPIO12 */
+#define CONFIG_SYS_GPIO_M66EN		(0x80000000 >> 13)	/* GPIO13 */
+
+/*
+ * Default speed selection (cpu_plb_opb_ebc) in mhz.
+ * This value will be set if iic boot eprom is disabled.
+ */
+#undef CONFIG_SYS_FCPU333MHZ
+#define CONFIG_SYS_FCPU266MHZ
+#undef CONFIG_SYS_FCPU133MHZ
+
+#if defined(CONFIG_SYS_FCPU333MHZ)
+/*
+ * CPU: 333MHz
+ * PLB/SDRAM/MAL: 111MHz
+ * OPB: 55MHz
+ * EBC: 55MHz
+ * PCI: 55MHz (111MHz on M66EN=1)
+ */
+#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_3 |		\
+			PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |	\
+			PLL_MALDIV_1 | PLL_PCIDIV_2)
+#define PLLMR1_DEFAULT (PLL_FBKDIV_10  |			\
+			PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |		\
+			PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
+#endif
+
+#if defined(CONFIG_SYS_FCPU266MHZ)
+/*
+ * CPU: 266MHz
+ * PLB/SDRAM/MAL: 133MHz
+ * OPB: 66MHz
+ * EBC: 44MHz
+ * PCI: 44MHz (66MHz on M66EN=1)
+ */
+#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_2 |		\
+			PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |	\
+			PLL_MALDIV_1 | PLL_PCIDIV_3)
+#define PLLMR1_DEFAULT (PLL_FBKDIV_8  |  \
+			PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |		\
+			PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+#endif
+
+#if defined(CONFIG_SYS_FCPU133MHZ)
+/*
+ * CPU: 133MHz
+ * PLB/SDRAM/MAL: 133MHz
+ * OPB: 66MHz
+ * EBC: 44MHz
+ * PCI: 44MHz (66MHz on M66EN=1)
+ */
+#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_1 |		\
+			PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |	\
+			PLL_MALDIV_1 | PLL_PCIDIV_3)
+#define PLLMR1_DEFAULT (PLL_FBKDIV_4  |  \
+			PLL_FWDDIVA_6 | PLL_FWDDIVB_6 |		\
+			PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/PMC440.h b/qemu/roms/u-boot/include/configs/PMC440.h
new file mode 100644
index 000000000..c5e2f164c
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/PMC440.h
@@ -0,0 +1,427 @@
+/*
+ * (C) Copyright 2007-2008
+ * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
+ * Based on the sequoia configuration file.
+ *
+ * (C) Copyright 2006-2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2006
+ * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
+ * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/************************************************************************
+ * PMC440.h - configuration for esd PMC440 boards
+ ***********************************************************************/
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_440EPX		1	/* Specific PPC440EPx   */
+#define CONFIG_440		1	/* ... PPC440 family    */
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xFFF90000
+#endif
+
+#define CONFIG_SYS_CLK_FREQ	33333400
+
+#if 0 /* temporary disabled because OS/9 does not like dcache on startup */
+#define CONFIG_4xx_DCACHE		/* enable dcache        */
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f */
+#define CONFIG_MISC_INIT_F	1
+#define CONFIG_MISC_INIT_R	1	/* Call misc_init_r     */
+#define CONFIG_BOARD_TYPES	1	/* support board types  */
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_MONITOR_LEN		(~(CONFIG_SYS_TEXT_BASE) + 1)
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserve 256 kB for malloc()  */
+
+#define CONFIG_PRAM		0	/* use pram variable to overwrite */
+
+#define CONFIG_SYS_BOOT_BASE_ADDR	0xf0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000	/* _must_ be 0          */
+#define CONFIG_SYS_FLASH_BASE		0xfc000000	/* start of FLASH       */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_ADDR		0xd0000000	/* NAND Flash           */
+#define CONFIG_SYS_OCM_BASE		0xe0010000	/* ocm                  */
+#define CONFIG_SYS_OCM_DATA_ADDR	CONFIG_SYS_OCM_BASE
+#define CONFIG_SYS_PCI_BASE		0xe0000000	/* Internal PCI regs    */
+#define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped pci memory    */
+#define CONFIG_SYS_PCI_MEMBASE1	CONFIG_SYS_PCI_MEMBASE  + 0x10000000
+#define CONFIG_SYS_PCI_MEMBASE2	CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
+#define CONFIG_SYS_PCI_MEMBASE3	CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
+#define CONFIG_SYS_PCI_MEMSIZE		0x80000000	/* 2GB! */
+
+#define CONFIG_SYS_USB2D0_BASE		0xe0000100
+#define CONFIG_SYS_USB_DEVICE		0xe0000000
+#define CONFIG_SYS_USB_HOST		0xe0000400
+#define CONFIG_SYS_FPGA_BASE0		0xef000000	/* 32 bit */
+#define CONFIG_SYS_FPGA_BASE1		0xef100000	/* 16 bit */
+#define CONFIG_SYS_RESET_BASE		0xef200000
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer
+ *----------------------------------------------------------------------*/
+/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache	*/
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_BASE	/* OCM                  */
+#define CONFIG_SYS_INIT_RAM_SIZE	(4 << 10)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+#undef CONFIG_SYS_EXT_SERIAL_CLOCK
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_SYS_BAUDRATE_TABLE						\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+#define CONFIG_ENV_IS_IN_EEPROM	1	/* use FLASH for environment vars */
+
+/*-----------------------------------------------------------------------
+ * RTC
+ *----------------------------------------------------------------------*/
+#define CONFIG_RTC_RX8025
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_FLASH_CFI		/* The flash is CFI compatible  */
+#define CONFIG_FLASH_CFI_DRIVER	/* Use common CFI driver        */
+
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks           */
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip    */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)      */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)      */
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)     */
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* use hardware flash protection        */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO	/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash        */
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector          */
+#define CONFIG_ENV_ADDR		((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector     */
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_EEPROM
+#define CONFIG_ENV_OFFSET		0	/* environment starts at the beginning of the EEPROM */
+#define CONFIG_ENV_SIZE		0x1000	/* 4096 bytes may be used for env vars */
+#endif
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CONFIG_DDR_DATA_EYE	/* use DDR2 optimization        */
+#define CONFIG_SYS_MEM_TOP_HIDE	(4 << 10) /* don't use last 4kbytes */
+						  /* 440EPx errata CHIP 11 */
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
+#define CONFIG_SYS_I2C_PPC4XX_CH1
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_1		400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_1		0x7F
+
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x54
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x01
+
+#define CONFIG_SYS_EEPROM_WREN			1
+#define CONFIG_SYS_I2C_BOOT_EEPROM_ADDR	0x52
+
+/*
+ * standard dtt sensor configuration - bottom bit will determine local or
+ * remote sensor of the TMP401
+ */
+#define CONFIG_DTT_SENSORS		{ 0, 1 }
+
+/*
+ * The PMC440 uses a TI TMP401 temperature sensor. This part
+ * is basically compatible to the ADM1021 that is supported
+ * by U-Boot.
+ *
+ * - i2c addr 0x4c
+ * - conversion rate 0x02 = 0.25 conversions/second
+ * - ALERT ouput disabled
+ * - local temp sensor enabled, min set to 0 deg, max set to 70 deg
+ * - remote temp sensor enabled, min set to 0 deg, max set to 70 deg
+ */
+#define CONFIG_DTT_ADM1021
+#define CONFIG_SYS_DTT_ADM1021		{ { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} }
+
+#define CONFIG_PREBOOT		"echo Add \\\"run fpga\\\" and "	\
+				"\\\"painit\\\" to preboot command"
+
+#undef	CONFIG_BOOTARGS
+
+/* Setup some board specific values for the default environment variables */
+#define CONFIG_HOSTNAME		pmc440
+#define CONFIG_SYS_BOOTFILE	"bootfile=/tftpboot/pmc440/uImage\0"
+#define CONFIG_SYS_ROOTPATH	"rootpath=/opt/eldk/ppc_4xxFP\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_SYS_BOOTFILE						\
+	CONFIG_SYS_ROOTPATH						\
+	"fdt_file=/tftpboot/pmc440/pmc440.dtb\0"			\
+	"netdev=eth0\0"							\
+	"ethrotate=no\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+	"nfsroot=${serverip}:${rootpath}\0"				\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
+	"addmisc=setenv bootargs ${bootargs} mem=${mem}\0"		\
+	"nandargs=setenv bootargs root=/dev/mtdblock6 rootfstype=jffs2 rw\0" \
+	"nand_boot_fdt=run nandargs addip addtty addmisc;"		\
+		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
+	"net_nfs_fdt=tftp ${kernel_addr_r} ${bootfile};"		\
+		"tftp  ${fdt_addr_r} ${fdt_file};"			\
+		"run nfsargs addip addtty addmisc;"			\
+		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
+	"kernel_addr=ffc00000\0"					\
+	"kernel_addr_r=200000\0"					\
+	"fpga_addr=fff00000\0"						\
+	"fdt_addr=fff80000\0"						\
+	"fdt_addr_r=800000\0"						\
+	"fpga=fpga loadb 0 ${fpga_addr}\0"				\
+	"load=tftp 200000 /tftpboot/pmc440/u-boot.bin\0"		\
+	"update=protect off fff90000 ffffffff;era fff90000 ffffffff;"	\
+		"cp.b 200000 fff90000 70000\0"				\
+	""
+
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds     */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download  */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change        */
+
+#define CONFIG_PPC4xx_EMAC
+#define CONFIG_IBM_EMAC4_V4	1
+#define CONFIG_MII		1	/* MII PHY management           */
+#define CONFIG_PHY_ADDR		0	/* PHY address, See schematics  */
+
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+
+#define CONFIG_HAS_ETH0
+#define CONFIG_SYS_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"   */
+#define CONFIG_PHY1_ADDR	1
+#define CONFIG_RESET_PHY_R	1
+
+/* USB */
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_USB_STORAGE
+#define CONFIG_SYS_OHCI_BE_CONTROLLER
+
+#define CONFIG_SYS_USB_OHCI_BOARD_INIT 1
+#define CONFIG_SYS_USB_OHCI_CPU_INIT	1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE	CONFIG_SYS_USB_HOST
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"ppc440"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
+
+/* Comment this out to enable USB 1.1 device */
+#define USB_2_0_DEVICE
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_REGINFO
+
+/* POST support */
+#define CONFIG_POST		(CONFIG_SYS_POST_MEMORY |	\
+				 CONFIG_SYS_POST_CPU    |	\
+				 CONFIG_SYS_POST_UART   |	\
+				 CONFIG_SYS_POST_I2C    |	\
+				 CONFIG_SYS_POST_CACHE  |	\
+				 CONFIG_SYS_POST_FPU    |	\
+				 CONFIG_SYS_POST_ETHER  |	\
+				 CONFIG_SYS_POST_SPR)
+
+#define CONFIG_LOGBUFFER
+#define CONFIG_SYS_POST_CACHE_ADDR	0x7fff0000	/* free virtual address     */
+
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	/* Otherwise it catches logbuffer as output */
+
+#define CONFIG_SUPPORT_VFAT
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory         */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size      */
+#else
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size      */
+#endif
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args   */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on          */
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM       */
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address      */
+#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history     */
+#define CONFIG_LOOPW		1	/* enable loopw command         */
+#define CONFIG_MX_CYCLIC	1	/* enable mdc/mwc commands      */
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+#define CONFIG_AUTOBOOT_KEYED	1
+#define CONFIG_AUTOBOOT_PROMPT	\
+	"Press SPACE to abort autoboot in %d seconds\n", bootdelay
+#undef CONFIG_AUTOBOOT_DELAY_STR
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *----------------------------------------------------------------------*/
+/* General PCI */
+#define CONFIG_PCI		/* include pci support          */
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_PNP		/* do (not) pci plug-and-play   */
+#define CONFIG_SYS_PCI_CACHE_LINE_SIZE	0	/* to avoid problems with PNP   */
+#define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup  */
+#define CONFIG_SYS_PCI_TARGBASE	0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
+
+/* Board-specific PCI */
+#define CONFIG_SYS_PCI_TARGET_INIT
+#define CONFIG_SYS_PCI_MASTER_INIT
+#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
+
+#define CONFIG_PCI_BOOTDELAY 0
+
+/* PCI identification */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh      */
+#define CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH 0x0441	/* PCI Device ID: Non-Monarch */
+#define CONFIG_SYS_PCI_SUBSYS_ID_MONARCH 0x0440	/* PCI Device ID: Monarch */
+/* for weak __pci_target_init() */
+#define CONFIG_SYS_PCI_SUBSYS_ID	CONFIG_SYS_PCI_SUBSYS_ID_MONARCH
+#define CONFIG_SYS_PCI_CLASSCODE_NONMONARCH	PCI_CLASS_PROCESSOR_POWERPC
+#define CONFIG_SYS_PCI_CLASSCODE_MONARCH	PCI_CLASS_BRIDGE_HOST
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ *----------------------------------------------------------------------*/
+#define CONFIG_FPGA
+#define CONFIG_FPGA_XILINX
+#define CONFIG_FPGA_SPARTAN2
+#define CONFIG_FPGA_SPARTAN3
+
+#define CONFIG_FPGA_COUNT	2
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ *----------------------------------------------------------------------*/
+
+/*
+ * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
+ */
+#define CONFIG_SYS_NAND_CS		2	/* NAND chip connected to CSx   */
+
+/* Memory Bank 0 (NOR-FLASH) initialization */
+#define CONFIG_SYS_EBC_PB0AP		0x03017200
+#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_FLASH_BASE | 0xda000)
+
+/* Memory Bank 2 (NAND-FLASH) initialization */
+#define CONFIG_SYS_EBC_PB2AP		0x018003c0
+#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_NAND_ADDR | 0x1c000)
+
+/* Memory Bank 1 (RESET) initialization */
+#define CONFIG_SYS_EBC_PB1AP		0x7f817200 /* 0x03017200 */
+#define CONFIG_SYS_EBC_PB1CR		(CONFIG_SYS_RESET_BASE | 0x1c000)
+
+/* Memory Bank 4 (FPGA / 32Bit) initialization */
+#define CONFIG_SYS_EBC_PB4AP		0x03840f40	/* BME=0,TWT=7,CSN=1,TH=7,RE=1,SOR=0,BEM=1 */
+#define CONFIG_SYS_EBC_PB4CR		(CONFIG_SYS_FPGA_BASE0 | 0x1c000)	/* BS=1M,BU=R/W,BW=32bit */
+
+/* Memory Bank 5 (FPGA / 16Bit) initialization */
+#define CONFIG_SYS_EBC_PB5AP		0x03840f40	/* BME=0,TWT=3,CSN=1,TH=0,RE=1,SOR=0,BEM=1 */
+#define CONFIG_SYS_EBC_PB5CR		(CONFIG_SYS_FPGA_BASE1 | 0x1a000)	/* BS=1M,BU=R/W,BW=16bit */
+
+/*-----------------------------------------------------------------------
+ * NAND FLASH
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		(CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
+#define CONFIG_SYS_NAND_SELECT_DEVICE	1 /* nand driver supports mutipl. chips */
+#define CONFIG_SYS_NAND_QUIET_TEST	1
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+#define CONFIG_API		1
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/PPChameleonEVB.h b/qemu/roms/u-boot/include/configs/PPChameleonEVB.h
new file mode 100644
index 000000000..e277d0d93
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/PPChameleonEVB.h
@@ -0,0 +1,777 @@
+/*
+ * (C) Copyright 2003-2005
+ * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+ *
+ * (C) Copyright 2003
+ * DAVE Srl
+ *
+ * http://www.dave-tech.it
+ * http://www.wawnet.biz
+ * mailto:info@wawnet.biz
+ *
+ * Credits: Stefan Roese, Wolfgang Denk
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_PPCHAMELEON_MODULE_BA	0	/* Basic    Model */
+#define CONFIG_PPCHAMELEON_MODULE_ME	1	/* Medium   Model */
+#define CONFIG_PPCHAMELEON_MODULE_HI	2	/* High-End Model */
+#ifndef CONFIG_PPCHAMELEON_MODULE_MODEL
+#define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA
+#endif
+
+
+/* Only one of the following two symbols must be defined (default is 25 MHz)
+ * CONFIG_PPCHAMELEON_CLK_25
+ * CONFIG_PPCHAMELEON_CLK_33
+ */
+#if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33))
+#define CONFIG_PPCHAMELEON_CLK_25
+#endif
+
+#if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33))
+#error "* Two external frequencies (SysClk) are defined! *"
+#endif
+
+#undef	CONFIG_PPCHAMELEON_SMI712
+
+/*
+ * Debug stuff
+ */
+#undef	__DEBUG_START_FROM_SRAM__
+#define __DISABLE_MACHINE_EXCEPTION__
+
+#ifdef __DEBUG_START_FROM_SRAM__
+#define CONFIG_SYS_DUMMY_FLASH_SIZE		1024*1024*4
+#endif
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_PPCHAMELEONEVB	1	/* ...on a PPChameleonEVB board */
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFB0000	/* Reserve 320 kB for Monitor */
+#define CONFIG_SYS_LDSCRIPT	"board/dave/PPChameleonEVB/u-boot.lds"
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
+
+
+#ifdef CONFIG_PPCHAMELEON_CLK_25
+# define CONFIG_SYS_CLK_FREQ	25000000 /* external frequency to pll	*/
+#elif (defined (CONFIG_PPCHAMELEON_CLK_33))
+# define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll	*/
+#else
+# error "* External frequency (SysClk) not defined! *"
+#endif
+
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#undef	CONFIG_BOOTARGS
+
+/* Ethernet stuff */
+#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
+#define CONFIG_ETHADDR	00:50:c2:1e:af:fe
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR 00:50:c2:1e:af:fd
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#undef CONFIG_EXT_PHY
+
+#define CONFIG_PPC4xx_EMAC
+#define CONFIG_MII		1	/* MII PHY management		*/
+#ifndef	 CONFIG_EXT_PHY
+#define CONFIG_PHY_ADDR		1	/* EMAC0 PHY address		*/
+#define CONFIG_PHY1_ADDR	2	/* EMAC1 PHY address		*/
+#else
+#define CONFIG_PHY_ADDR		2	/* PHY address			*/
+#endif
+#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_SNTP
+
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_RTC_M41T11	1	/* uses a M41T00 RTC		*/
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR	1900
+
+/*
+ * SDRAM configuration (please see cpu/ppc/sdram.[ch])
+ */
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+/* SDRAM timings used in datasheet */
+#define CONFIG_SYS_SDRAM_CL            2
+#define CONFIG_SYS_SDRAM_tRP           20
+#define CONFIG_SYS_SDRAM_tRC           65
+#define CONFIG_SYS_SDRAM_tRCD          20
+#undef  CONFIG_SYS_SDRAM_tRFC
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+
+#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK		/* no external serial clock used */
+#define CONFIG_SYS_BASE_BAUD		691200
+
+/* The following table includes the supported baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+/*-----------------------------------------------------------------------
+ * NAND-FLASH stuff
+ *-----------------------------------------------------------------------
+ */
+
+/*
+ * nand device 1 on dave (PPChameleonEVB) needs more time,
+ * so we just introduce additional wait in nand_wait(),
+ * effectively for both devices.
+ */
+#define PPCHAMELON_NAND_TIMER_HACK
+
+#define CONFIG_SYS_NAND0_BASE 0xFF400000
+#define CONFIG_SYS_NAND1_BASE 0xFF000000
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND0_BASE, CONFIG_SYS_NAND1_BASE }
+#define NAND_BIG_DELAY_US	25
+#define CONFIG_SYS_MAX_NAND_DEVICE	2	/* Max number of NAND devices */
+
+#define CONFIG_SYS_NAND0_CE  (0x80000000 >> 1)	 /* our CE is GPIO1 */
+#define CONFIG_SYS_NAND0_RDY (0x80000000 >> 4)	 /* our RDY is GPIO4 */
+#define CONFIG_SYS_NAND0_CLE (0x80000000 >> 2)	 /* our CLE is GPIO2 */
+#define CONFIG_SYS_NAND0_ALE (0x80000000 >> 3)	 /* our ALE is GPIO3 */
+
+#define CONFIG_SYS_NAND1_CE  (0x80000000 >> 14)  /* our CE is GPIO14 */
+#define CONFIG_SYS_NAND1_RDY (0x80000000 >> 31)  /* our RDY is GPIO31 */
+#define CONFIG_SYS_NAND1_CLE (0x80000000 >> 15)  /* our CLE is GPIO15 */
+#define CONFIG_SYS_NAND1_ALE (0x80000000 >> 16)  /* our ALE is GPIO16 */
+
+#define MACRO_NAND_DISABLE_CE(nandptr) do \
+{ \
+	switch((unsigned long)nandptr) \
+	{ \
+	    case CONFIG_SYS_NAND0_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CE); \
+		break; \
+	    case CONFIG_SYS_NAND1_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CE); \
+		break; \
+	} \
+} while(0)
+
+#define MACRO_NAND_ENABLE_CE(nandptr) do \
+{ \
+	switch((unsigned long)nandptr) \
+	{ \
+	    case CONFIG_SYS_NAND0_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CE); \
+		break; \
+	    case CONFIG_SYS_NAND1_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CE); \
+		break; \
+	} \
+} while(0)
+
+#define MACRO_NAND_CTL_CLRALE(nandptr) do \
+{ \
+	switch((unsigned long)nandptr) \
+	{ \
+	    case CONFIG_SYS_NAND0_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_ALE); \
+		break; \
+	    case CONFIG_SYS_NAND1_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_ALE); \
+		break; \
+	} \
+} while(0)
+
+#define MACRO_NAND_CTL_SETALE(nandptr) do \
+{ \
+	switch((unsigned long)nandptr) \
+	{ \
+	    case CONFIG_SYS_NAND0_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_ALE); \
+		break; \
+	    case CONFIG_SYS_NAND1_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_ALE); \
+		break; \
+	} \
+} while(0)
+
+#define MACRO_NAND_CTL_CLRCLE(nandptr) do \
+{ \
+	switch((unsigned long)nandptr) \
+	{ \
+	    case CONFIG_SYS_NAND0_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CLE); \
+		break; \
+	    case CONFIG_SYS_NAND1_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CLE); \
+		break; \
+	} \
+} while(0)
+
+#define MACRO_NAND_CTL_SETCLE(nandptr) do { \
+	switch((unsigned long)nandptr) { \
+	case CONFIG_SYS_NAND0_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CLE); \
+		break; \
+	case CONFIG_SYS_NAND1_BASE: \
+		out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CLE); \
+		break; \
+	} \
+} while(0)
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_HOST PCI_HOST_FORCE	 /* select pci host function	 */
+#undef	CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+					/* resource configuration	*/
+
+#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014	/* PCI Vendor ID: IBM	*/
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000	/* PCI Device ID: ---	*/
+#define CONFIG_SYS_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
+
+#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CONFIG_SYS_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CONFIG_SYS_PCI_PTM2LA	0xffc00000	/* point to flash		*/
+#define CONFIG_SYS_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
+#define CONFIG_SYS_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+
+/* Reserve 256 kB for Monitor	*/
+/*
+#define CONFIG_SYS_FLASH_BASE		0xFFFC0000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
+*/
+
+/* Reserve 320 kB for Monitor	*/
+#define CONFIG_SYS_FLASH_BASE		0xFFFB0000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(320 * 1024)
+
+#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
+
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+/*-----------------------------------------------------------------------
+ * Environment Variable setup
+ */
+#ifdef ENVIRONMENT_IN_EEPROM
+
+#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CONFIG_ENV_OFFSET		0x100	/* environment starts at the beginning of the EEPROM */
+#define CONFIG_ENV_SIZE		0x700	/* 2048-256 bytes may be used for env vars (total size of a CAT24WC16 is 2048 bytes)*/
+
+#else	/* DEFAULT: environment in flash, using redundand flash sectors */
+
+#define CONFIG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars */
+#define CONFIG_ENV_ADDR		0xFFFF8000	/* environment starts at the first small sector */
+#define CONFIG_ENV_SECT_SIZE	0x2000	/* 8196 bytes may be used for env vars*/
+#define CONFIG_ENV_ADDR_REDUND	0xFFFFA000
+#define CONFIG_ENV_SIZE_REDUND	0x2000
+
+#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+
+#endif	/* ENVIRONMENT_IN_EEPROM */
+
+
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
+#define CONFIG_SYS_NVRAM_SIZE		242			/* NVRAM size		*/
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+/*#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last 4 bits of the address	*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
+#define CONFIG_SYS_EBC_PB0AP		0x92015480
+#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (External SRAM) initialization					*/
+/* Since this must replace NOR Flash, we use the same settings for CS0		*/
+#define CONFIG_SYS_EBC_PB1AP		0x92015480
+#define CONFIG_SYS_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 2 (Flash Bank 1, NAND-FLASH) initialization			*/
+#define CONFIG_SYS_EBC_PB2AP		0x92015480
+#define CONFIG_SYS_EBC_PB2CR		0xFF458000  /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 3 (Flash Bank 2, NAND-FLASH) initialization			*/
+#define CONFIG_SYS_EBC_PB3AP		0x92015480
+#define CONFIG_SYS_EBC_PB3CR		0xFF058000  /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit	*/
+
+#ifdef CONFIG_PPCHAMELEON_SMI712
+/*
+ * Video console (graphic: SMI LynxEM)
+ */
+#define CONFIG_VIDEO
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_SMI_LYNXEM
+#define CONFIG_VIDEO_LOGO
+/*#define CONFIG_VIDEO_BMP_LOGO*/
+#define CONFIG_CONSOLE_EXTRA_INFO
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+/* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */
+#define CONFIG_SYS_ISA_IO 0xE8000000
+/* see also drivers/video/videomodes.c */
+#define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x303
+#endif
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ */
+/* FPGA internal regs */
+#define CONFIG_SYS_FPGA_MODE		0x00
+#define CONFIG_SYS_FPGA_STATUS		0x02
+#define CONFIG_SYS_FPGA_TS		0x04
+#define CONFIG_SYS_FPGA_TS_LOW		0x06
+#define CONFIG_SYS_FPGA_TS_CAP0	0x10
+#define CONFIG_SYS_FPGA_TS_CAP0_LOW	0x12
+#define CONFIG_SYS_FPGA_TS_CAP1	0x14
+#define CONFIG_SYS_FPGA_TS_CAP1_LOW	0x16
+#define CONFIG_SYS_FPGA_TS_CAP2	0x18
+#define CONFIG_SYS_FPGA_TS_CAP2_LOW	0x1a
+#define CONFIG_SYS_FPGA_TS_CAP3	0x1c
+#define CONFIG_SYS_FPGA_TS_CAP3_LOW	0x1e
+
+/* FPGA Mode Reg */
+#define CONFIG_SYS_FPGA_MODE_CF_RESET	0x0001
+#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
+#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR  0x1000
+#define CONFIG_SYS_FPGA_MODE_TS_CLEAR	0x2000
+
+/* FPGA Status Reg */
+#define CONFIG_SYS_FPGA_STATUS_DIP0	0x0001
+#define CONFIG_SYS_FPGA_STATUS_DIP1	0x0002
+#define CONFIG_SYS_FPGA_STATUS_DIP2	0x0004
+#define CONFIG_SYS_FPGA_STATUS_FLASH	0x0008
+#define CONFIG_SYS_FPGA_STATUS_TS_IRQ	0x1000
+
+#define CONFIG_SYS_FPGA_SPARTAN2	1		/* using Xilinx Spartan 2 now	 */
+#define CONFIG_SYS_FPGA_MAX_SIZE	128*1024	/* 128kByte is enough for XC2S50E*/
+
+/* FPGA program pin configuration */
+#define CONFIG_SYS_FPGA_PRG		0x04000000	/* FPGA program pin (ppc output) */
+#define CONFIG_SYS_FPGA_CLK		0x02000000	/* FPGA clk pin (ppc output)	 */
+#define CONFIG_SYS_FPGA_DATA		0x01000000	/* FPGA data pin (ppc output)	 */
+#define CONFIG_SYS_FPGA_INIT		0x00010000	/* FPGA init pin (ppc input)	 */
+#define CONFIG_SYS_FPGA_DONE		0x00008000	/* FPGA done pin (ppc input)	 */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CONFIG_SYS_TEMP_STACK_OCM	1
+
+/* On Chip Memory location */
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
+
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO setup (PPC405EP specific)
+ *
+ * GPIO0[0]	- External Bus Controller BLAST output
+ * GPIO0[1-9]	- Instruction trace outputs -> GPIO
+ * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
+ * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
+ * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
+ * GPIO0[24-27] - UART0 control signal inputs/outputs
+ * GPIO0[28-29] - UART1 data signal input/output
+ * GPIO0[30]	- EMAC0 input
+ * GPIO0[31]	- EMAC1 reject packet as output
+ */
+#define CONFIG_SYS_GPIO0_OSRL		0x40000550
+#define CONFIG_SYS_GPIO0_OSRH		0x00000110
+#define CONFIG_SYS_GPIO0_ISR1L		0x00000000
+/*#define CONFIG_SYS_GPIO0_ISR1H	0x15555445*/
+#define CONFIG_SYS_GPIO0_ISR1H		0x15555444
+#define CONFIG_SYS_GPIO0_TSRL		0x00000000
+#define CONFIG_SYS_GPIO0_TSRH		0x00000000
+#define CONFIG_SYS_GPIO0_TCR		0xF7FF8014
+
+#define CONFIG_NO_SERIAL_EEPROM
+
+/*--------------------------------------------------------------------*/
+
+#ifdef CONFIG_NO_SERIAL_EEPROM
+
+/*
+!-----------------------------------------------------------------------
+! Defines for entry options.
+! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
+!	are plugged in the board will be utilized as non-ECC DIMMs.
+!-----------------------------------------------------------------------
+*/
+#undef		AUTO_MEMORY_CONFIG
+#define		DIMM_READ_ADDR 0xAB
+#define		DIMM_WRITE_ADDR 0xAA
+
+/* Defines for CPC0_PLLMR1 Register fields */
+#define PLL_ACTIVE		0x80000000
+#define CPC0_PLLMR1_SSCS	0x80000000
+#define PLL_RESET		0x40000000
+#define CPC0_PLLMR1_PLLR	0x40000000
+    /* Feedback multiplier */
+#define PLL_FBKDIV		0x00F00000
+#define CPC0_PLLMR1_FBDV	0x00F00000
+#define PLL_FBKDIV_16		0x00000000
+#define PLL_FBKDIV_1		0x00100000
+#define PLL_FBKDIV_2		0x00200000
+#define PLL_FBKDIV_3		0x00300000
+#define PLL_FBKDIV_4		0x00400000
+#define PLL_FBKDIV_5		0x00500000
+#define PLL_FBKDIV_6		0x00600000
+#define PLL_FBKDIV_7		0x00700000
+#define PLL_FBKDIV_8		0x00800000
+#define PLL_FBKDIV_9		0x00900000
+#define PLL_FBKDIV_10		0x00A00000
+#define PLL_FBKDIV_11		0x00B00000
+#define PLL_FBKDIV_12		0x00C00000
+#define PLL_FBKDIV_13		0x00D00000
+#define PLL_FBKDIV_14		0x00E00000
+#define PLL_FBKDIV_15		0x00F00000
+    /* Forward A divisor */
+#define PLL_FWDDIVA		0x00070000
+#define CPC0_PLLMR1_FWDVA	0x00070000
+#define PLL_FWDDIVA_8		0x00000000
+#define PLL_FWDDIVA_7		0x00010000
+#define PLL_FWDDIVA_6		0x00020000
+#define PLL_FWDDIVA_5		0x00030000
+#define PLL_FWDDIVA_4		0x00040000
+#define PLL_FWDDIVA_3		0x00050000
+#define PLL_FWDDIVA_2		0x00060000
+#define PLL_FWDDIVA_1		0x00070000
+    /* Forward B divisor */
+#define PLL_FWDDIVB		0x00007000
+#define CPC0_PLLMR1_FWDVB	0x00007000
+#define PLL_FWDDIVB_8		0x00000000
+#define PLL_FWDDIVB_7		0x00001000
+#define PLL_FWDDIVB_6		0x00002000
+#define PLL_FWDDIVB_5		0x00003000
+#define PLL_FWDDIVB_4		0x00004000
+#define PLL_FWDDIVB_3		0x00005000
+#define PLL_FWDDIVB_2		0x00006000
+#define PLL_FWDDIVB_1		0x00007000
+    /* PLL tune bits */
+#define PLL_TUNE_MASK		0x000003FF
+#define PLL_TUNE_2_M_3		0x00000133	/*  2 <= M <= 3			*/
+#define PLL_TUNE_4_M_6		0x00000134	/*  3 <	 M <= 6			*/
+#define PLL_TUNE_7_M_10		0x00000138	/*  6 <	 M <= 10		*/
+#define PLL_TUNE_11_M_14	0x0000013C	/* 10 <	 M <= 14		*/
+#define PLL_TUNE_15_M_40	0x0000023E	/* 14 <	 M <= 40		*/
+#define PLL_TUNE_VCO_LOW	0x00000000	/* 500MHz <= VCO <=  800MHz	*/
+#define PLL_TUNE_VCO_HI		0x00000080	/* 800MHz <  VCO <= 1000MHz	*/
+
+/* Defines for CPC0_PLLMR0 Register fields */
+    /* CPU divisor */
+#define PLL_CPUDIV		0x00300000
+#define CPC0_PLLMR0_CCDV	0x00300000
+#define PLL_CPUDIV_1		0x00000000
+#define PLL_CPUDIV_2		0x00100000
+#define PLL_CPUDIV_3		0x00200000
+#define PLL_CPUDIV_4		0x00300000
+    /* PLB divisor */
+#define PLL_PLBDIV		0x00030000
+#define CPC0_PLLMR0_CBDV	0x00030000
+#define PLL_PLBDIV_1		0x00000000
+#define PLL_PLBDIV_2		0x00010000
+#define PLL_PLBDIV_3		0x00020000
+#define PLL_PLBDIV_4		0x00030000
+    /* OPB divisor */
+#define PLL_OPBDIV		0x00003000
+#define CPC0_PLLMR0_OPDV	0x00003000
+#define PLL_OPBDIV_1		0x00000000
+#define PLL_OPBDIV_2		0x00001000
+#define PLL_OPBDIV_3		0x00002000
+#define PLL_OPBDIV_4		0x00003000
+    /* EBC divisor */
+#define PLL_EXTBUSDIV		0x00000300
+#define CPC0_PLLMR0_EPDV	0x00000300
+#define PLL_EXTBUSDIV_2		0x00000000
+#define PLL_EXTBUSDIV_3		0x00000100
+#define PLL_EXTBUSDIV_4		0x00000200
+#define PLL_EXTBUSDIV_5		0x00000300
+    /* MAL divisor */
+#define PLL_MALDIV		0x00000030
+#define CPC0_PLLMR0_MPDV	0x00000030
+#define PLL_MALDIV_1		0x00000000
+#define PLL_MALDIV_2		0x00000010
+#define PLL_MALDIV_3		0x00000020
+#define PLL_MALDIV_4		0x00000030
+    /* PCI divisor */
+#define PLL_PCIDIV		0x00000003
+#define CPC0_PLLMR0_PPFD	0x00000003
+#define PLL_PCIDIV_1		0x00000000
+#define PLL_PCIDIV_2		0x00000001
+#define PLL_PCIDIV_3		0x00000002
+#define PLL_PCIDIV_4		0x00000003
+
+#ifdef CONFIG_PPCHAMELEON_CLK_25
+/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 25.0 MHz input clock to the 405EP) */
+#define PPCHAMELEON_PLLMR0_133_133_33_66_33	 (PLL_CPUDIV_1 | PLL_PLBDIV_1 |	 \
+			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |	\
+			      PLL_MALDIV_1 | PLL_PCIDIV_4)
+#define PPCHAMELEON_PLLMR1_133_133_33_66_33	 (PLL_FBKDIV_8	|  \
+			      PLL_FWDDIVA_6 | PLL_FWDDIVB_4 |  \
+			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+
+#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |  \
+			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |	\
+			      PLL_MALDIV_1 | PLL_PCIDIV_4)
+#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_8  |  \
+			      PLL_FWDDIVA_4 | PLL_FWDDIVB_4 |  \
+			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+
+#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |	\
+			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |	\
+			      PLL_MALDIV_1 | PLL_PCIDIV_4)
+#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8  |  \
+			      PLL_FWDDIVA_3 | PLL_FWDDIVB_4 |  \
+			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+
+#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 |	\
+			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |	\
+			      PLL_MALDIV_1 | PLL_PCIDIV_2)
+#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10	|  \
+			      PLL_FWDDIVA_3 | PLL_FWDDIVB_4 |  \
+			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
+
+#elif (defined (CONFIG_PPCHAMELEON_CLK_33))
+
+/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */
+#define PPCHAMELEON_PLLMR0_133_133_33_66_33	 (PLL_CPUDIV_1 | PLL_PLBDIV_1 |	 \
+				  PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |	\
+				  PLL_MALDIV_1 | PLL_PCIDIV_4)
+#define PPCHAMELEON_PLLMR1_133_133_33_66_33	 (PLL_FBKDIV_4	|  \
+				  PLL_FWDDIVA_6 | PLL_FWDDIVB_6 |  \
+				  PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+
+#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |  \
+				  PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |	\
+				  PLL_MALDIV_1 | PLL_PCIDIV_4)
+#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_6  |  \
+				  PLL_FWDDIVA_4 | PLL_FWDDIVB_4 |  \
+				  PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+
+#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |	\
+				  PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |	\
+				  PLL_MALDIV_1 | PLL_PCIDIV_4)
+#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8  |  \
+				  PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
+				  PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+
+#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 |	\
+				  PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |	\
+				  PLL_MALDIV_1 | PLL_PCIDIV_2)
+#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10	|  \
+				  PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
+				  PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
+
+#else
+#error "* External frequency (SysClk) not defined! *"
+#endif
+
+#if   (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
+/* Model HI */
+#define PLLMR0_DEFAULT	PPCHAMELEON_PLLMR0_333_111_37_55_55
+#define PLLMR1_DEFAULT	PPCHAMELEON_PLLMR1_333_111_37_55_55
+#define CONFIG_SYS_OPB_FREQ	55555555
+/* Model ME */
+#elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
+#define PLLMR0_DEFAULT	PPCHAMELEON_PLLMR0_266_133_33_66_33
+#define PLLMR1_DEFAULT	PPCHAMELEON_PLLMR1_266_133_33_66_33
+#define CONFIG_SYS_OPB_FREQ	66666666
+#else
+/* Model BA (default) */
+#define PLLMR0_DEFAULT	PPCHAMELEON_PLLMR0_133_133_33_66_33
+#define PLLMR1_DEFAULT	PPCHAMELEON_PLLMR1_133_133_33_66_33
+#define CONFIG_SYS_OPB_FREQ	66666666
+#endif
+
+#endif /* CONFIG_NO_SERIAL_EEPROM */
+
+#define CONFIG_JFFS2_NAND 1			/* jffs2 on nand support */
+#define NAND_CACHE_PAGES 16			/* size of nand cache in 512 bytes pages */
+
+/*
+ * JFFS2 partitions
+ */
+
+/* No command line, one static partition */
+#undef CONFIG_CMD_MTDPARTS
+#define CONFIG_JFFS2_DEV		"nand0"
+#define CONFIG_JFFS2_PART_SIZE		0x00400000
+#define CONFIG_JFFS2_PART_OFFSET	0x00000000
+
+/* mtdparts command line support */
+/*
+#define CONFIG_CMD_MTDPARTS
+#define MTDIDS_DEFAULT		"nor0=PPChameleon-0,nand0=ppchameleonevb-nand"
+*/
+
+/* 256 kB U-boot image */
+/*
+#define MTDPARTS_DEFAULT	"mtdparts=PPChameleon-0:1m(kernel1),1m(kernel2)," \
+					"1792k(user),256k(u-boot);" \
+				"ppchameleonevb-nand:-(nand)"
+*/
+
+/* 320 kB U-boot image */
+/*
+#define MTDPARTS_DEFAULT	"mtdparts=PPChameleon-0:1m(kernel1),1m(kernel2)," \
+					"1728k(user),320k(u-boot);" \
+				"ppchameleonevb-nand:-(nand)"
+*/
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/QS823.h b/qemu/roms/u-boot/include/configs/QS823.h
new file mode 100644
index 000000000..673346042
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/QS823.h
@@ -0,0 +1,551 @@
+/*
+ * (C) Copyright 2003
+ * MuLogic B.V.
+ *
+ * (C) Copyright 2002
+ * Simple Network Magic Corporation
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* various debug settings */
+#undef CONFIG_SYS_DEVICE_NULLDEV		/* null device */
+#undef CONFIG_SILENT_CONSOLE		/* silent console */
+#undef CONFIG_SYS_CONSOLE_INFO_QUIET		/* silent console ? */
+#undef DEBUG_FLASH			/* debug flash code */
+#undef FLASH_DEBUG			/* debug fash code */
+#undef DEBUG_ENV			/* debug environment code */
+
+#define CONFIG_SYS_DIRECT_FLASH_TFTP	1	/* allow direct tftp to flash */
+#define CONFIG_ENV_OVERWRITE	1	/* allow overwrite MAC address */
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MPC823		1	/* This is a MPC823 CPU */
+#define CONFIG_QS823		1	/* ...on a QS823 module */
+#define CONFIG_SCC2_ENET	1	/* SCC2 10BaseT ethernet */
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
+
+/* Select the target clock speed */
+#undef CONFIG_CLOCK_16MHZ		/* cpu=16,777,216 Hz, mem=16Mhz */
+#undef CONFIG_CLOCK_33MHZ		/* cpu=33,554,432 Hz, mem=33Mhz */
+#undef CONFIG_CLOCK_50MHZ		/* cpu=49,971,200 Hz, mem=33Mhz */
+#define CONFIG_CLOCK_66MHZ	1	/* cpu=67,108,864 Hz, mem=66Mhz */
+#undef CONFIG_CLOCK_80MHZ		/* cpu=79,986,688 Hz, mem=33Mhz */
+
+#ifdef CONFIG_CLOCK_16MHZ
+#define CONFIG_CLOCK_MULT	512
+#endif
+
+#ifdef CONFIG_CLOCK_33MHZ
+#define CONFIG_CLOCK_MULT	1024
+#endif
+
+#ifdef CONFIG_CLOCK_50MHZ
+#define CONFIG_CLOCK_MULT	1525
+#endif
+
+#ifdef CONFIG_CLOCK_66MHZ
+#define CONFIG_CLOCK_MULT	2048
+#endif
+
+#ifdef CONFIG_CLOCK_80MHZ
+#define CONFIG_CLOCK_MULT	2441
+#endif
+
+/* choose flash size, 4Mb or 8Mb */
+#define CONFIG_FLASH_4MB	1	/* board has 4Mb flash */
+#undef CONFIG_FLASH_8MB			/* board has 8Mb flash */
+
+#define CONFIG_CLOCK_BASE	32768	/* Base clock input freq */
+
+#undef CONFIG_8xx_CONS_SMC1
+#define CONFIG_8xx_CONS_SMC2	1	/* Console is on SMC2 */
+#undef CONFIG_8xx_CONS_NONE
+
+#define CONFIG_BAUDRATE		38400	/* console baudrate = 38.4kbps */
+
+#undef CONFIG_CLOCKS_IN_MHZ		/* clocks passsed to Linux in MHz */
+
+/* Define default IP addresses */
+#define CONFIG_IPADDR		192.168.1.99	/* own ip address */
+#define CONFIG_SERVERIP		192.168.1.19	/* used for tftp (not nfs?) */
+
+/* message to say directly after booting */
+#define CONFIG_PREBOOT		"echo '';" \
+	"echo 'type:';" \
+	"echo 'run boot_nfs       to boot to NFS';" \
+	"echo 'run boot_flash     to boot to flash';" \
+	"echo '';" \
+	"echo 'run flash_rootfs   to install a new rootfs';" \
+	"echo 'run flash_env      to clear the env sector';" \
+	"echo 'run flash_rw       to clear the rw fs';" \
+	"echo 'run flash_uboot    to install a new u-boot';" \
+	"echo 'run flash_kernel   to install a new kernel';"
+
+/* wait 5 seconds before executing CONFIG_BOOTCOMMAND */
+#define CONFIG_BOOTDELAY	5
+#define CONFIG_BOOTCOMMAND	"run boot_nfs"
+
+#undef CONFIG_BOOTARGS		/* made by set_nfs of set_flash */
+
+/* Our flash filesystem looks like this
+ *
+ * 4Mb board:
+ * ffc0 0000 - ffeb ffff	root filesystem (jffs2) (~3Mb)
+ * ffec 0000 - ffed ffff	read-write filesystem (ext2)
+ * ffee 0000 - ffef ffff	environment
+ * fff0 0000 - fff1 ffff	u-boot
+ * fff2 0000 - ffff ffff	linux kernel
+ *
+ * 8Mb board:
+ * ff80 0000 - ffeb ffff	root filesystem (jffs2) (~7Mb)
+ * ffec 0000 - ffed ffff	read-write filesystem (ext2)
+ * ffee 0000 - ffef ffff	environment
+ * fff0 0000 - fff1 ffff	u-boot
+ * fff2 0000 - ffff ffff	linux kernel
+ *
+ */
+
+/* environment for 4Mb board */
+#ifdef CONFIG_FLASH_4MB
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"serial#=QS823\0" \
+	"hostname=qs823\0" \
+	"netdev=eth0\0" \
+	"ethaddr=00:01:02:B4:36:56\0" \
+	"rootpath=/exports/rootfs\0" \
+	"mtdparts=mtdparts=phys:2816k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \
+	/* fill in variables */ \
+	"set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \
+	"set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \
+	"set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \
+	/* commands */ \
+	"boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \
+	"boot_flash=run set_ip; run set_flash; bootm fff20000\0" \
+	/* reinstall flash parts */ \
+	"flash_rootfs=protect off ffc00000 ffebffff; era ffc00000 ffebffff; tftp ffc00000 /tftpboot/rootfs.jffs2\0" \
+	"flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \
+	"flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \
+	"flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.4mb.bin\0" \
+	"flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0"
+#endif /* CONFIG_FLASH_4MB */
+
+/* environment for 8Mb board */
+#ifdef CONFIG_FLASH_8MB
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"serial#=QS823\0" \
+	"hostname=qs823\0" \
+	"netdev=eth0\0" \
+	"ethaddr=00:01:02:B4:36:56\0" \
+	"rootpath=/exports/rootfs\0" \
+	"mtdparts=mtdparts=phys:6912k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \
+	/* fill in variables */ \
+	"set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \
+	"set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \
+	"set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \
+	/* commands */ \
+	"boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \
+	"boot_flash=run set_ip; run set_flash; bootm fff20000\0" \
+	/* reinstall flash parts */ \
+	"flash_rootfs=protect off ff800000 ffebffff; era ff800000 ffebffff; tftp ff800000 /tftpboot/rootfs.jffs2\0" \
+	"flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \
+	"flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \
+	"flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.8mb.bin\0" \
+	"flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0"
+#endif /* CONFIG_FLASH_8MB */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#undef CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change */
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+#undef CONFIG_STATUS_LED		/* Status LED disabled */
+#undef CONFIG_CAN_DRIVER		/* CAN Driver support disabled */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+#undef CONFIG_MAC_PARTITION
+#undef CONFIG_DOS_PARTITION
+
+#define CONFIG_RTC_MPC8xx	/* use internal RTC of MPC8xx */
+
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_CONSOLE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_RUN
+
+
+/*-----------------------------------------------------------------------
+ * Environment variable storage is in FLASH, one sector before U-boot
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_SECT_SIZE	0x20000		/* 128Kb, one whole sector */
+#define CONFIG_ENV_SIZE		0x2000		/* 8kb */
+#define CONFIG_ENV_ADDR		0xffee0000	/* address of env sector */
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP				/* undef to save memory */
+
+#define CONFIG_SYS_HUSH_PARSER		1		/* use "hush" command parser */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works */
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM */
+
+#define CONFIG_SYS_LOAD_ADDR		0x400000	/* default load address */
+
+/*-----------------------------------------------------------------------
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xFF000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2F00		/* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFF800000	/* Allow an 8Mbyte window */
+
+#define FLASH_BASE0_4M_PRELIM	0xFFC00000	/* Base for 4M Flash */
+#define FLASH_BASE0_8M_PRELIM	0xFF800000	/* Base for 8M Flash */
+
+#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor */
+#define CONFIG_SYS_MONITOR_BASE	0xFFF00000	/* U-boot location */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * TODO flash parameters
+ * FLASH organization for Intel Strataflash
+ */
+#undef  CONFIG_SYS_FLASH_16BIT				/* 32-bit wide flash memory */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	71		/* max number of sectors on one chip */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000		/* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Timeout for Flash Write (in ms) */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16		/* For all MPC8xx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	4		/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control 11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+
+#ifdef CONFIG_WATCHDOG
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP)
+#else
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWRI | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration 11-6
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DLK | SIUMCR_DPC | SIUMCR_MPRE | SIUMCR_MLRC01 | SIUMCR_GB5E)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control 11-26
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register 11-27
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control 11-31
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
+ *-----------------------------------------------------------------------
+ */
+
+/* MF (Multiplication Factor of SPLL) */
+/* Sets the QS823 to specified clock from 32KHz clock at EXTAL. */
+#define vPLPRCR_MF	((CONFIG_CLOCK_MULT+1) << 20)
+#define CONFIG_SYS_PLPRCR	(vPLPRCR_MF | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | PLPRCR_LOLRE)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ */
+#if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ)
+#define CONFIG_SYS_SCCR		(SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG00)
+#define CONFIG_SYS_BRGCLK_PRESCALE	1
+#endif
+
+#if defined(CONFIG_CLOCK_66MHZ)
+#define CONFIG_SYS_SCCR		(SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG01)
+#define CONFIG_SYS_BRGCLK_PRESCALE	4
+#endif
+
+#if defined(CONFIG_CLOCK_80MHZ)
+#define CONFIG_SYS_SCCR		(SCCR_TBS | SCCR_EBDF01 | SCCR_DFBRG01)
+#define CONFIG_SYS_BRGCLK_PRESCALE	4
+#endif
+
+#define SCCR_MASK		CONFIG_SYS_SCCR
+
+/*-----------------------------------------------------------------------
+ * Debug Enable Register
+ * 0x73E67C0F - All interrupts handled by BDM
+ * 0x00824001 - Only interrupts needed by MWDebug.exe handled by BDM
+ *-----------------------------------------------------------------------
+#define CONFIG_SYS_DER			0x73E67C0F
+#define CONFIG_SYS_DER			0x0082400F
+
+ #-------------------------------------------------------------------------
+ # Program the Debug Enable Register (DER). This register provides the user
+ # with the reason for entering into the debug mode. We want all conditions
+ # to end up as an exception. We don't want to enter into debug mode for
+ # any condition. See the back of of the Development Support section of the
+ # MPC860 User Manual for a description of this register.
+ #-------------------------------------------------------------------------
+*/
+#define CONFIG_SYS_DER			0
+
+/*-----------------------------------------------------------------------
+ * Memory Controller Initialization Constants
+ *-----------------------------------------------------------------------
+ */
+
+/*
+ * BR0 and OR0 (AMD dual FLASH devices)
+ * Base address = 0xFFF0_0000 - 0xFFF7_FFFF (After relocation)
+ */
+#define CONFIG_SYS_PRELIM_OR_AM
+#define CONFIG_SYS_OR_TIMING_FLASH
+
+/*
+ *-----------------------------------------------------------------------
+ * Base Register 0 (BR0): Bank 0 is assigned to the 8Mbyte (2M X 32)
+ *                        flash that resides on the QS823.
+ *-----------------------------------------------------------------------
+ */
+
+/* BA (Base Address) = 0xFF80+0b for a total of 17 bits. 17 bit base addr */
+/*                     represents a minumum 32K block size. */
+#define vBR0_BA			((0xFF80 << 16) + (0 << 15))
+#define CONFIG_SYS_BR0_PRELIM		(vBR0_BA | BR_V)
+
+/* AM (Address Mask) = 0xFF80+0b = We've masked the upper 9 bits        */
+/*                                 which defines a 8 Mbyte memory block. */
+#define vOR0_AM			((0xFF80 << 16) + (0 << 15))
+
+#if defined(CONFIG_CLOCK_50MHZ) || defined(CONFIG_CLOCK_80MHZ)
+/*  0101 = Add a 5 clock cycle wait state */
+#define CONFIG_SYS_OR0_PRELIM		(vOR0_AM | OR_CSNT_SAM | 0R_ACS_DIV4 | OR_BI | OR_SCY_5_CLK)
+#endif
+
+#if defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_66MHZ)
+/*  0011 = Add a 3 clock cycle wait state */
+/*  29.8ns clock * (3 + 2) = 149ns cycle time */
+#define CONFIG_SYS_OR0_PRELIM		(vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK)
+#endif
+
+#if defined(CONFIG_CLOCK_16MHZ)
+/*  0010 = Add a 2 clock cycle wait state */
+#define CONFIG_SYS_OR0_PRELIM		(vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_2_CLK)
+#endif
+
+/*
+ * BR1 and OR1 (SDRAM)
+ * Base Address = 0x00000000 - 0x00FF_FFFF (16M After relocation)
+ * Base Address = 0x00000000 - 0x01FF_FFFF (32M After relocation)
+ * Base Address = 0x00000000 - 0x03FF_FFFF (64M After relocation)
+ * Base Address = 0x00000000 - 0x07FF_FFFF (128M After relocation)
+ */
+
+#define SDRAM_BASE		0x00000000	/* SDRAM bank */
+#define SDRAM_PRELIM_OR_AM	0xF8000000	/* map max. 128 MB */
+
+/* AM (Address Mask) = 0xF800+0b = We've masked the upper 5 bits which
+ *                                 represents a 128 Mbyte block the DRAM in
+ *                                 this address base.
+ */
+#define vOR1_AM			((0xF800 << 16) + (0 << 15))
+#define vBR1_BA			((0x0000 << 16) + (0 << 15))
+#define CONFIG_SYS_OR1			(vOR1_AM | OR_CSNT_SAM | OR_BI)
+#define CONFIG_SYS_BR1			(vBR1_BA | BR_MS_UPMA | BR_V)
+
+/* Machine A Mode Register */
+
+/* PTA Periodic Timer A */
+
+#if defined(CONFIG_CLOCK_80MHZ)
+#define vMAMR_PTA		(19 << 24)
+#endif
+
+#if defined(CONFIG_CLOCK_66MHZ)
+#define vMAMR_PTA		(16 << 24)
+#endif
+
+#if defined(CONFIG_CLOCK_50MHZ)
+#define vMAMR_PTA		(195 << 24)
+#endif
+
+#if defined(CONFIG_CLOCK_33MHZ)
+#define vMAMR_PTA		(131 << 24)
+#endif
+
+#if defined(CONFIG_CLOCK_16MHZ)
+#define vMAMR_PTA		(65 << 24)
+#endif
+
+/* For boards with 16M of SDRAM */
+#define SDRAM_16M_MAX_SIZE	0x01000000	/* max 16MB SDRAM */
+#define CONFIG_SYS_16M_MAMR		(vMAMR_PTA | MAMR_AMA_TYPE_0 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A11 |\
+MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
+
+/* For boards with 32M of SDRAM */
+#define SDRAM_32M_MAX_SIZE	0x02000000	/* max 32MB SDRAM */
+#define CONFIG_SYS_32M_MAMR		(vMAMR_PTA | MAMR_AMA_TYPE_1 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A10 |\
+MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
+
+
+/* Memory Periodic Timer Prescaler Register */
+
+#if defined(CONFIG_CLOCK_66MHZ) || defined(CONFIG_CLOCK_80MHZ)
+/* Divide by 32 */
+#define CONFIG_SYS_MPTPR		0x02
+#endif
+
+#if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ)
+/* Divide by 16 */
+#define CONFIG_SYS_MPTPR		0x04
+#endif
+
+/*
+ * BR2 and OR2 (Unused)
+ * Base address = 0xF020_0000 - 0xF020_0FFF
+ *
+ */
+#define CONFIG_SYS_OR2_PRELIM		0xFFF00000
+#define CONFIG_SYS_BR2_PRELIM		0xF0200000
+
+/*
+ * BR3 and OR3 (External Bus CS3)
+ * Base address = 0xF030_0000 - 0xF030_0FFF
+ *
+ */
+#define CONFIG_SYS_OR3_PRELIM		0xFFF00000
+#define CONFIG_SYS_BR3_PRELIM		0xF0300000
+
+/*
+ * BR4 and OR4 (External Bus CS3)
+ * Base address = 0xF040_0000 - 0xF040_0FFF
+ *
+ */
+#define CONFIG_SYS_OR4_PRELIM		0xFFF00000
+#define CONFIG_SYS_BR4_PRELIM		0xF0400000
+
+
+/*
+ * BR4 and OR4 (External Bus CS3)
+ * Base address = 0xF050_0000 - 0xF050_0FFF
+ *
+ */
+#define CONFIG_SYS_OR5_PRELIM		0xFFF00000
+#define CONFIG_SYS_BR5_PRELIM		0xF0500000
+
+/*
+ * BR6 and OR6 (Unused)
+ * Base address = 0xF060_0000 - 0xF060_0FFF
+ *
+ */
+#define CONFIG_SYS_OR6_PRELIM		0xFFF00000
+#define CONFIG_SYS_BR6_PRELIM		0xF0600000
+
+/*
+ * BR7 and OR7 (Unused)
+ * Base address = 0xF070_0000 - 0xF070_0FFF
+ *
+ */
+#define CONFIG_SYS_OR7_PRELIM		0xFFF00000
+#define CONFIG_SYS_BR7_PRELIM		0xF0700000
+
+/*
+ * Sanity checks
+ */
+#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
+#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/QS850.h b/qemu/roms/u-boot/include/configs/QS850.h
new file mode 100644
index 000000000..f11421387
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/QS850.h
@@ -0,0 +1,551 @@
+/*
+ * (C) Copyright 2003
+ * MuLogic B.V.
+ *
+ * (C) Copyright 2002
+ * Simple Network Magic Corporation
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* various debug settings */
+#undef CONFIG_SYS_DEVICE_NULLDEV		/* null device */
+#undef CONFIG_SILENT_CONSOLE		/* silent console */
+#undef CONFIG_SYS_CONSOLE_INFO_QUIET		/* silent console ? */
+#undef DEBUG_FLASH			/* debug flash code */
+#undef FLASH_DEBUG			/* debug fash code */
+#undef DEBUG_ENV			/* debug environment code */
+
+#define CONFIG_SYS_DIRECT_FLASH_TFTP	1	/* allow direct tftp to flash */
+#define CONFIG_ENV_OVERWRITE	1	/* allow overwrite MAC address */
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MPC850		1	/* This is a MPC850 CPU */
+#define CONFIG_QS850		1	/* ...on a QS850 module */
+#define CONFIG_SCC2_ENET	1	/* SCC2 10BaseT ethernet */
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
+
+/* Select the target clock speed */
+#undef CONFIG_CLOCK_16MHZ		/* cpu=16,777,216 Hz, mem=16Mhz */
+#undef CONFIG_CLOCK_33MHZ		/* cpu=33,554,432 Hz, mem=33Mhz */
+#undef CONFIG_CLOCK_50MHZ		/* cpu=49,971,200 Hz, mem=33Mhz */
+#define CONFIG_CLOCK_66MHZ	1	/* cpu=67,108,864 Hz, mem=66Mhz */
+#undef CONFIG_CLOCK_80MHZ		/* cpu=79,986,688 Hz, mem=33Mhz */
+
+#ifdef CONFIG_CLOCK_16MHZ
+#define CONFIG_CLOCK_MULT	512
+#endif
+
+#ifdef CONFIG_CLOCK_33MHZ
+#define CONFIG_CLOCK_MULT	1024
+#endif
+
+#ifdef CONFIG_CLOCK_50MHZ
+#define CONFIG_CLOCK_MULT	1525
+#endif
+
+#ifdef CONFIG_CLOCK_66MHZ
+#define CONFIG_CLOCK_MULT	2048
+#endif
+
+#ifdef CONFIG_CLOCK_80MHZ
+#define CONFIG_CLOCK_MULT	2441
+#endif
+
+/* choose flash size, 4Mb or 8Mb */
+#define CONFIG_FLASH_4MB	1	/* board has 4Mb flash */
+#undef CONFIG_FLASH_8MB			/* board has 8Mb flash */
+
+#define CONFIG_CLOCK_BASE	32768	/* Base clock input freq */
+
+#define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1 */
+#undef CONFIG_8xx_CONS_SMC2
+#undef CONFIG_8xx_CONS_NONE
+
+#define CONFIG_BAUDRATE		38400	/* console baudrate = 38.4kbps */
+
+#undef CONFIG_CLOCKS_IN_MHZ		/* clocks passsed to Linux in MHz */
+
+/* Define default IP addresses */
+#define CONFIG_IPADDR		192.168.1.99	/* own ip address */
+#define CONFIG_SERVERIP		192.168.1.19	/* used for tftp (not nfs?) */
+
+/* message to say directly after booting */
+#define CONFIG_PREBOOT		"echo '';" \
+	"echo 'type:';" \
+	"echo 'run boot_nfs       to boot to NFS';" \
+	"echo 'run boot_flash     to boot to flash';" \
+	"echo '';" \
+	"echo 'run flash_rootfs   to install a new rootfs';" \
+	"echo 'run flash_env      to clear the env sector';" \
+	"echo 'run flash_rw       to clear the rw fs';" \
+	"echo 'run flash_uboot    to install a new u-boot';" \
+	"echo 'run flash_kernel   to install a new kernel';"
+
+/* wait 5 seconds before executing CONFIG_BOOTCOMMAND */
+#define CONFIG_BOOTDELAY	5
+#define CONFIG_BOOTCOMMAND	"run boot_nfs"
+
+#undef CONFIG_BOOTARGS		/* made by set_nfs of set_flash */
+
+/* Our flash filesystem looks like this
+ *
+ * 4Mb board:
+ * ffc0 0000 - ffeb ffff	root filesystem (jffs2) (~3Mb)
+ * ffec 0000 - ffed ffff	read-write filesystem (ext2)
+ * ffee 0000 - ffef ffff	environment
+ * fff0 0000 - fff1 ffff	u-boot
+ * fff2 0000 - ffff ffff	linux kernel
+ *
+ * 8Mb board:
+ * ff80 0000 - ffeb ffff	root filesystem (jffs2) (~7Mb)
+ * ffec 0000 - ffed ffff	read-write filesystem (ext2)
+ * ffee 0000 - ffef ffff	environment
+ * fff0 0000 - fff1 ffff	u-boot
+ * fff2 0000 - ffff ffff	linux kernel
+ *
+ */
+
+/* environment for 4Mb board */
+#ifdef CONFIG_FLASH_4MB
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"serial#=QS850\0" \
+	"hostname=qs850\0" \
+	"netdev=eth0\0" \
+	"ethaddr=00:01:02:B4:36:56\0" \
+	"rootpath=/exports/rootfs\0" \
+	"mtdparts=mtdparts=phys:2816k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \
+	/* fill in variables */ \
+	"set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \
+	"set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \
+	"set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \
+	/* commands */ \
+	"boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \
+	"boot_flash=run set_ip; run set_flash; bootm fff20000\0" \
+	/* reinstall flash parts */ \
+	"flash_rootfs=protect off ffc00000 ffebffff; era ffc00000 ffebffff; tftp ffc00000 /tftpboot/rootfs.jffs2\0" \
+	"flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \
+	"flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \
+	"flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.4mb.bin\0" \
+	"flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0"
+#endif /* CONFIG_FLASH_4MB */
+
+/* environment for 8Mb board */
+#ifdef CONFIG_FLASH_8MB
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"serial#=QS850\0" \
+	"hostname=qs850\0" \
+	"netdev=eth0\0" \
+	"ethaddr=00:01:02:B4:36:56\0" \
+	"rootpath=/exports/rootfs\0" \
+	"mtdparts=mtdparts=phys:6912k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \
+	/* fill in variables */ \
+	"set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \
+	"set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \
+	"set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \
+	/* commands */ \
+	"boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \
+	"boot_flash=run set_ip; run set_flash; bootm fff20000\0" \
+	/* reinstall flash parts */ \
+	"flash_rootfs=protect off ff800000 ffebffff; era ff800000 ffebffff; tftp ff800000 /tftpboot/rootfs.jffs2\0" \
+	"flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \
+	"flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \
+	"flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.8mb.bin\0" \
+	"flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0"
+#endif /* CONFIG_FLASH_8MB */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#undef CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change */
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+#undef CONFIG_STATUS_LED		/* Status LED disabled */
+#undef CONFIG_CAN_DRIVER		/* CAN Driver support disabled */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+#undef CONFIG_MAC_PARTITION
+#undef CONFIG_DOS_PARTITION
+
+#define CONFIG_RTC_MPC8xx	/* use internal RTC of MPC8xx */
+
+
+/*
+ * Command line configuration.
+ */
+
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_CONSOLE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_RUN
+
+
+/*-----------------------------------------------------------------------
+ * Environment variable storage is in FLASH, one sector before U-boot
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_SECT_SIZE	0x20000		/* 128Kb, one whole sector */
+#define CONFIG_ENV_SIZE		0x2000		/* 8kb */
+#define CONFIG_ENV_ADDR		0xffee0000	/* address of env sector */
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP				/* undef to save memory */
+
+#define CONFIG_SYS_HUSH_PARSER		1		/* use "hush" command parser */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works */
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM */
+
+#define CONFIG_SYS_LOAD_ADDR		0x400000	/* default load address */
+
+/*-----------------------------------------------------------------------
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xFF000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2F00		/* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFF800000	/* Allow an 8Mbyte window */
+
+#define FLASH_BASE0_4M_PRELIM	0xFFC00000	/* Base for 4M Flash */
+#define FLASH_BASE0_8M_PRELIM	0xFF800000	/* Base for 8M Flash */
+
+#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor */
+#define CONFIG_SYS_MONITOR_BASE	0xFFF00000	/* U-boot location */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * TODO flash parameters
+ * FLASH organization for Intel Strataflash
+ */
+#undef  CONFIG_SYS_FLASH_16BIT				/* 32-bit wide flash memory */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	71		/* max number of sectors on one chip */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000		/* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Timeout for Flash Write (in ms) */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16		/* For all MPC8xx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	4		/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control 11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+
+#ifdef CONFIG_WATCHDOG
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP)
+#else
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWRI | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration 11-6
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DLK | SIUMCR_DPC | SIUMCR_MPRE | SIUMCR_MLRC01 | SIUMCR_GB5E)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control 11-26
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register 11-27
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control 11-31
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
+ *-----------------------------------------------------------------------
+ */
+
+/* MF (Multiplication Factor of SPLL) */
+/* Sets the QS850 to specified clock from 32KHz clock at EXTAL. */
+#define vPLPRCR_MF	((CONFIG_CLOCK_MULT+1) << 20)
+#define CONFIG_SYS_PLPRCR	(vPLPRCR_MF | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | PLPRCR_LOLRE)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ */
+#if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ)
+#define CONFIG_SYS_SCCR		(SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG00)
+#define CONFIG_SYS_BRGCLK_PRESCALE	1
+#endif
+
+#if defined(CONFIG_CLOCK_66MHZ)
+#define CONFIG_SYS_SCCR		(SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG01)
+#define CONFIG_SYS_BRGCLK_PRESCALE	4
+#endif
+
+#if defined(CONFIG_CLOCK_80MHZ)
+#define CONFIG_SYS_SCCR		(SCCR_TBS | SCCR_EBDF01 | SCCR_DFBRG01)
+#define CONFIG_SYS_BRGCLK_PRESCALE	4
+#endif
+
+#define SCCR_MASK		CONFIG_SYS_SCCR
+
+/*-----------------------------------------------------------------------
+ * Debug Enable Register
+ * 0x73E67C0F - All interrupts handled by BDM
+ * 0x00824001 - Only interrupts needed by MWDebug.exe handled by BDM
+ *-----------------------------------------------------------------------
+#define CONFIG_SYS_DER			0x73E67C0F
+#define CONFIG_SYS_DER			0x0082400F
+
+ #-------------------------------------------------------------------------
+ # Program the Debug Enable Register (DER). This register provides the user
+ # with the reason for entering into the debug mode. We want all conditions
+ # to end up as an exception. We don't want to enter into debug mode for
+ # any condition. See the back of of the Development Support section of the
+ # MPC860 User Manual for a description of this register.
+ #-------------------------------------------------------------------------
+*/
+#define CONFIG_SYS_DER			0
+
+/*-----------------------------------------------------------------------
+ * Memory Controller Initialization Constants
+ *-----------------------------------------------------------------------
+ */
+
+/*
+ * BR0 and OR0 (AMD dual FLASH devices)
+ * Base address = 0xFFF0_0000 - 0xFFF7_FFFF (After relocation)
+ */
+#define CONFIG_SYS_PRELIM_OR_AM
+#define CONFIG_SYS_OR_TIMING_FLASH
+
+/*
+ *-----------------------------------------------------------------------
+ * Base Register 0 (BR0): Bank 0 is assigned to the 8Mbyte (2M X 32)
+ *                        flash that resides on the QS850.
+ *-----------------------------------------------------------------------
+ */
+
+/* BA (Base Address) = 0xFF80+0b for a total of 17 bits. 17 bit base addr */
+/*                     represents a minumum 32K block size. */
+#define vBR0_BA			((0xFF80 << 16) + (0 << 15))
+#define CONFIG_SYS_BR0_PRELIM		(vBR0_BA | BR_V)
+
+/* AM (Address Mask) = 0xFF80+0b = We've masked the upper 9 bits        */
+/*                                 which defines a 8 Mbyte memory block. */
+#define vOR0_AM			((0xFF80 << 16) + (0 << 15))
+
+#if defined(CONFIG_CLOCK_50MHZ) || defined(CONFIG_CLOCK_80MHZ)
+/*  0101 = Add a 5 clock cycle wait state */
+#define CONFIG_SYS_OR0_PRELIM		(vOR0_AM | OR_CSNT_SAM | 0R_ACS_DIV4 | OR_BI | OR_SCY_5_CLK)
+#endif
+
+#if defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_66MHZ)
+/*  0011 = Add a 3 clock cycle wait state */
+/*  29.8ns clock * (3 + 2) = 149ns cycle time */
+#define CONFIG_SYS_OR0_PRELIM		(vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK)
+#endif
+
+#if defined(CONFIG_CLOCK_16MHZ)
+/*  0010 = Add a 2 clock cycle wait state */
+#define CONFIG_SYS_OR0_PRELIM		(vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_2_CLK)
+#endif
+
+/*
+ * BR1 and OR1 (SDRAM)
+ * Base Address = 0x00000000 - 0x00FF_FFFF (16M After relocation)
+ * Base Address = 0x00000000 - 0x01FF_FFFF (32M After relocation)
+ * Base Address = 0x00000000 - 0x03FF_FFFF (64M After relocation)
+ * Base Address = 0x00000000 - 0x07FF_FFFF (128M After relocation)
+ */
+
+#define SDRAM_BASE		0x00000000	/* SDRAM bank */
+#define SDRAM_PRELIM_OR_AM	0xF8000000	/* map max. 128 MB */
+
+/* AM (Address Mask) = 0xF800+0b = We've masked the upper 5 bits which
+ *                                 represents a 128 Mbyte block the DRAM in
+ *                                 this address base.
+ */
+#define vOR1_AM			((0xF800 << 16) + (0 << 15))
+#define vBR1_BA			((0x0000 << 16) + (0 << 15))
+#define CONFIG_SYS_OR1			(vOR1_AM | OR_CSNT_SAM | OR_BI)
+#define CONFIG_SYS_BR1			(vBR1_BA | BR_MS_UPMA | BR_V)
+
+/* Machine A Mode Register */
+
+/* PTA Periodic Timer A */
+
+#if defined(CONFIG_CLOCK_80MHZ)
+#define vMAMR_PTA		(19 << 24)
+#endif
+
+#if defined(CONFIG_CLOCK_66MHZ)
+#define vMAMR_PTA		(16 << 24)
+#endif
+
+#if defined(CONFIG_CLOCK_50MHZ)
+#define vMAMR_PTA		(195 << 24)
+#endif
+
+#if defined(CONFIG_CLOCK_33MHZ)
+#define vMAMR_PTA		(131 << 24)
+#endif
+
+#if defined(CONFIG_CLOCK_16MHZ)
+#define vMAMR_PTA		(65 << 24)
+#endif
+
+/* For boards with 16M of SDRAM */
+#define SDRAM_16M_MAX_SIZE	0x01000000	/* max 16MB SDRAM */
+#define CONFIG_SYS_16M_MAMR		(vMAMR_PTA | MAMR_AMA_TYPE_0 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A11 |\
+MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
+
+/* For boards with 32M of SDRAM */
+#define SDRAM_32M_MAX_SIZE	0x02000000	/* max 32MB SDRAM */
+#define CONFIG_SYS_32M_MAMR		(vMAMR_PTA | MAMR_AMA_TYPE_1 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A10 |\
+MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
+
+
+/* Memory Periodic Timer Prescaler Register */
+
+#if defined(CONFIG_CLOCK_66MHZ) || defined(CONFIG_CLOCK_80MHZ)
+/* Divide by 32 */
+#define CONFIG_SYS_MPTPR		0x02
+#endif
+
+#if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ)
+/* Divide by 16 */
+#define CONFIG_SYS_MPTPR		0x04
+#endif
+
+/*
+ * BR2 and OR2 (Unused)
+ * Base address = 0xF020_0000 - 0xF020_0FFF
+ *
+ */
+#define CONFIG_SYS_OR2_PRELIM		0xFFF00000
+#define CONFIG_SYS_BR2_PRELIM		0xF0200000
+
+/*
+ * BR3 and OR3 (External Bus CS3)
+ * Base address = 0xF030_0000 - 0xF030_0FFF
+ *
+ */
+#define CONFIG_SYS_OR3_PRELIM		0xFFF00000
+#define CONFIG_SYS_BR3_PRELIM		0xF0300000
+
+/*
+ * BR4 and OR4 (External Bus CS3)
+ * Base address = 0xF040_0000 - 0xF040_0FFF
+ *
+ */
+#define CONFIG_SYS_OR4_PRELIM		0xFFF00000
+#define CONFIG_SYS_BR4_PRELIM		0xF0400000
+
+
+/*
+ * BR4 and OR4 (External Bus CS3)
+ * Base address = 0xF050_0000 - 0xF050_0FFF
+ *
+ */
+#define CONFIG_SYS_OR5_PRELIM		0xFFF00000
+#define CONFIG_SYS_BR5_PRELIM		0xF0500000
+
+/*
+ * BR6 and OR6 (Unused)
+ * Base address = 0xF060_0000 - 0xF060_0FFF
+ *
+ */
+#define CONFIG_SYS_OR6_PRELIM		0xFFF00000
+#define CONFIG_SYS_BR6_PRELIM		0xF0600000
+
+/*
+ * BR7 and OR7 (Unused)
+ * Base address = 0xF070_0000 - 0xF070_0FFF
+ *
+ */
+#define CONFIG_SYS_OR7_PRELIM		0xFFF00000
+#define CONFIG_SYS_BR7_PRELIM		0xF0700000
+
+/*
+ * Sanity checks
+ */
+#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
+#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/QS860T.h b/qemu/roms/u-boot/include/configs/QS860T.h
new file mode 100644
index 000000000..9958c09d7
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/QS860T.h
@@ -0,0 +1,390 @@
+/*
+ * (C) Copyright 2003
+ * MuLogic B.V.
+ *
+ * (C) Copyright 2002
+ * Simple Network Magic Corporation
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* various debug settings */
+#undef CONFIG_SYS_DEVICE_NULLDEV		/* null device */
+#undef CONFIG_SILENT_CONSOLE		/* silent console */
+#undef CONFIG_SYS_CONSOLE_INFO_QUIET		/* silent console ? */
+#undef DEBUG_FLASH			/* debug flash code */
+#undef FLASH_DEBUG			/* debug fash code */
+#undef DEBUG_ENV			/* debug environment code */
+
+#define CONFIG_SYS_DIRECT_FLASH_TFTP	1	/* allow direct tftp to flash */
+#define CONFIG_ENV_OVERWRITE	1	/* allow overwrite MAC address */
+
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC860		1	/* This is a MPC860 CPU */
+#define CONFIG_QS860T		1	/* ...on a QS860T module */
+
+/* Start address of 512K Socketed Flash */
+#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
+
+#define CONFIG_FEC_ENET		1	/* FEC 10/100BaseT ethernet */
+#define CONFIG_MII
+#define FEC_INTERRUPT		SIU_LEVEL1
+#undef CONFIG_SCC1_ENET			/* SCC1 10BaseT ethernet */
+#define CONFIG_SYS_DISCOVER_PHY
+
+#undef CONFIG_8xx_CONS_SMC1
+#define CONFIG_8xx_CONS_SMC2	1	/* Console is on SMC */
+#undef CONFIG_8xx_CONS_NONE
+
+#define CONFIG_BAUDRATE		38400	/* console baudrate = 38.4kbps */
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+
+/* Pass clocks to Linux 2.4.18 in Hz */
+#undef CONFIG_CLOCKS_IN_MHZ		/* clocks passsed to Linux in MHz */
+
+#define CONFIG_PREBOOT		"echo;" \
+	"echo 'Type \\\"run flash_nfs\\\" to mount root filesystem over NFS';" \
+	"echo"
+
+#undef CONFIG_BOOTARGS
+/* TODO compare against CADM860 */
+#define CONFIG_BOOTCOMMAND	"bootp; " \
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
+	"bootm"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#undef CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change */
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+#undef CONFIG_STATUS_LED		/* Status LED disabled */
+
+#undef CONFIG_CAN_DRIVER		/* CAN Driver support disabled */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_RTC_MPC8xx	/* use internal RTC of MPC8xx */
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DATE
+
+
+/* TODO */
+#if 0
+/* Look at these */
+CONFIG_IPADDR
+CONFIG_SERVERIP
+CONFIG_I2C
+CONFIG_SPI
+#endif
+
+/*
+ * Environment variable storage is in NVRAM
+ */
+#define CONFIG_ENV_IS_IN_NVRAM	1
+#define CONFIG_ENV_SIZE		0x00001000	/* We use only the last 4K for PPCBoot */
+#define CONFIG_ENV_ADDR		0xD100E000
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP				/* undef to save memory */
+
+#define CONFIG_SYS_HUSH_PARSER		1		/* use "hush" command parser */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+
+/* TODO - size? */
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works */
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM */
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
+
+/*-----------------------------------------------------------------------
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xF0000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2F00		/* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFF00000
+
+#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/* TODO flash parameters */
+/*-----------------------------------------------------------------------
+ * FLASH organization for Intel Strataflash
+ */
+#define CONFIG_SYS_FLASH_16BIT		1		/* 16-bit wide flash memory */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	64		/* max number of sectors on one chip */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000		/* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Timeout for Flash Write (in ms) */
+
+#undef	CONFIG_ENV_IS_IN_FLASH
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16		/* For all MPC8xx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	4		/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control 11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR	(0xFFFFFF88 | SYPCR_SWE | SYPCR_SWRI)
+#else
+#define CONFIG_SYS_SYPCR	0xFFFFFF88
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration 11-6
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_SIUMCR	0x00620000
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control 11-26
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_TBSCR	0x00C3
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register 11-27
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control 11-31
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_PISCR	0x0082
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_PLPRCR	0x0090D000
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CONFIG_SYS_SCCR	0x02000000
+
+
+/*-----------------------------------------------------------------------
+ * Debug Enable Register
+ * 0x73E67C0F - All interrupts handled by BDM
+ * 0x00824001 - Only interrupts needed by MWDebug.exe handled by BDM
+ *-----------------------------------------------------------------------
+#define CONFIG_SYS_DER			0x73E67C0F
+*/
+#define CONFIG_SYS_DER			0x0082400F
+
+
+/*-----------------------------------------------------------------------
+ * Memory Controller Initialization Constants
+ *-----------------------------------------------------------------------
+ */
+
+/*
+ * BR0 and OR0 (AMD 512K Socketed FLASH)
+ * Base address = 0xFFF0_0000 - 0xFFF7_FFFF (After relocation)
+ */
+#define CONFIG_SYS_PRELIM_OR_AM
+#define CONFIG_SYS_OR_TIMING_FLASH
+
+#define FLASH_BASE0_PRELIM	0xFFF00001
+#define CONFIG_SYS_OR0_PRELIM		0xFFF80D42
+#define CONFIG_SYS_BR0_PRELIM		0xFFF00401
+
+
+/*
+ * BR1 and OR1 (Intel 8M StrataFLASH)
+ * Base address = 0xD000_0000 - 0xD07F_FFFF
+ */
+
+#define FLASH_BASE1_PRELIM	0xD0000000
+#define CONFIG_SYS_OR1_PRELIM		0xFF800D42
+#define CONFIG_SYS_BR1_PRELIM		0xD0000801
+/* #define CONFIG_SYS_OR1		0xFF800D42 */
+/* #define CONFIG_SYS_BR1		0xD0000801 */
+
+
+/*
+ * BR2 and OR2 (SDRAM)
+ * Base Address = 0x00000000 - 0x00FF_FFFF (16M After relocation)
+ * Base Address = 0x00000000 - 0x03FF_FFFF (64M After relocation)
+ * Base Address = 0x00000000 - 0x07FF_FFFF (128M After relocation)
+ *
+ */
+#define SDRAM_BASE		0x00000000	/* SDRAM bank */
+#define SDRAM_PRELIM_OR_AM	0xF8000000	/* map max. 128 MB */
+
+/* SDRAM timing */
+#define SDRAM_TIMING		0x00000A00
+
+/* For boards with 16M of SDRAM */
+#define SDRAM_16M_MAX_SIZE	0x01000000	/* max 16MB SDRAM */
+#define CONFIG_SYS_16M_MBMR		0x18802114	/* Mem Periodic Timer Prescaler */
+
+/* For boards with 64M of SDRAM */
+#define SDRAM_64M_MAX_SIZE	0x04000000	/* max 64MB SDRAM */
+/* TODO - determine real value */
+#define CONFIG_SYS_64M_MBMR		0x18802114	/* Mem Period Timer Prescaler */
+
+#define CONFIG_SYS_OR2			(SDRAM_PRELIM_OR_AM | SDRAM_TIMING)
+#define CONFIG_SYS_BR2			(SDRAM_BASE | 0x000000C1)
+
+
+/*
+ * BR3 and OR3 (NVRAM, Sipex, NAND Flash)
+ * Base address = 0xD100_0000 - 0xD100_FFFF (64K NVRAM)
+ * Base address = 0xD108_0000 - 0xD108_0000 (Sipex chip ctl register)
+ * Base address = 0xD110_0000 - 0xD110_0000 (NAND ctl register)
+ * Base address = 0xD138_0000 - 0xD138_0000 (LED ctl register)
+ *
+ */
+
+#define CONFIG_SYS_OR3_PRELIM		0xFFC00DF6
+#define CONFIG_SYS_BR3_PRELIM		0xD1000401
+/* #define CONFIG_SYS_OR3		0xFFC00DF6 */
+/* #define CONFIG_SYS_BR3		0xD1000401 */
+
+
+/*
+ * BR4 and OR4 (Unused)
+ * Base address = 0xE000_0000 - 0xE3FF_FFFF
+ *
+ */
+
+#define CONFIG_SYS_OR4_PRELIM		0xFF000000
+#define CONFIG_SYS_BR4_PRELIM		0xE0000000
+/* #define CONFIG_SYS_OR4		0xFF000000 */
+/* #define CONFIG_SYS_BR4		0xE0000000 */
+
+
+/*
+ * BR5 and OR5 (Expansion bus)
+ * Base address = 0xE400_0000 - 0xE7FF_FFFF
+ *
+ */
+
+#define CONFIG_SYS_OR5_PRELIM		0xFF000000
+#define CONFIG_SYS_BR5_PRELIM		0xE4000000
+/* #define CONFIG_SYS_OR5		0xFF000000 */
+/* #define CONFIG_SYS_BR5		0xE4000000 */
+
+
+/*
+ * BR6 and OR6 (Expansion bus)
+ * Base address = 0xE800_0000 - 0xEBFF_FFFF
+ *
+ */
+
+#define CONFIG_SYS_OR6_PRELIM		0xFF000000
+#define CONFIG_SYS_BR6_PRELIM		0xE8000000
+/* #define CONFIG_SYS_OR6		0xFF000000 */
+/* #define CONFIG_SYS_BR6		0xE8000000 */
+
+
+/*
+ * BR7 and OR7 (Expansion bus)
+ * Base address = 0xEC00_0000 - 0xEFFF_FFFF
+ *
+ */
+
+#define CONFIG_SYS_OR7_PRELIM		0xFF000000
+#define CONFIG_SYS_BR7_PRELIM		0xE8000000
+/* #define CONFIG_SYS_OR7		0xFF000000 */
+/* #define CONFIG_SYS_BR7		0xE8000000 */
+
+/*
+ * Sanity checks
+ */
+#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
+#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/R360MPI.h b/qemu/roms/u-boot/include/configs/R360MPI.h
new file mode 100644
index 000000000..009d1cf97
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/R360MPI.h
@@ -0,0 +1,464 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC823		1	/* This is a MPC823 CPU		*/
+#define CONFIG_R360MPI		1
+
+#define	CONFIG_SYS_TEXT_BASE	0x40000000
+
+#define CONFIG_LCD
+#define CONFIG_MPC8XX_LCD
+#undef  CONFIG_EDT32F10
+#define CONFIG_SHARP_LQ057Q3DC02
+
+#define	CONFIG_SPLASH_SCREEN
+
+#define MPC8XX_FACT             1		/* Multiply by 1	*/
+#define MPC8XX_XIN              50000000	/* 50 MHz in		*/
+#define CONFIG_8xx_GCLK_FREQ    50000000 /* define if can't use get_gclk_freq */
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		115200	/* console baudrate in bps	*/
+#if 0
+#define CONFIG_BOOTDELAY	0	/* immediate boot		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+
+#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND							\
+	"bootp; "								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
+	"bootm"
+
+#undef	CONFIG_SCC1_ENET
+#define	CONFIG_SCC2_ENET
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#define	CONFIG_MISC_INIT_R		/* have misc_init_r() function	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_CAN_DRIVER		/* CAN Driver support enabled	*/
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+#define CONFIG_HARD_I2C		1	/* To I2C with hardware support */
+#undef CONFIG_SYS_I2C_SOFT		/* To I2C with software support */
+#define CONFIG_SYS_I2C_SPEED		4700	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+
+#if defined(CONFIG_SYS_I2C_SOFT)
+#define CONFIG_SYS_SYS_I2C_SOFT_SPEED	4700 /* I2C speed and slave address */
+#define CONFIG_SYS_SYS_I2C_SOFT_SLAVE	0x7F
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PB_SCL			0x00000020	/* PB 26 */
+#define PB_SDA			0x00000010	/* PB 27 */
+
+#define I2C_INIT		(immr->im_cpm.cp_pbdir |=  PB_SCL)
+#define I2C_ACTIVE		(immr->im_cpm.cp_pbdir |=  PB_SDA)
+#define I2C_TRISTATE		(immr->im_cpm.cp_pbdir &= ~PB_SDA)
+#define I2C_READ		((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+#define I2C_SDA(bit)		if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
+				else    immr->im_cpm.cp_pbdat &= ~PB_SDA
+#define I2C_SCL(bit)		if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
+				else    immr->im_cpm.cp_pbdat &= ~PB_SCL
+#define I2C_DELAY		udelay(50)
+#endif /* #define(CONFIG_SYS_I2C_SOFT) */
+
+#define CONFIG_SYS_I2C_LCD_ADDR	0x8	/* LCD Control */
+#define CONFIG_SYS_I2C_KEY_ADDR	0x9	/* Keyboard coprocessor */
+#define CONFIG_SYS_I2C_TEM_ADDR	0x49	/* Temperature Sensors */
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BMP
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCMCIA
+#define CONFIG_CMD_SNTP
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* we need the null device	*/
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1	/* must set console from env	*/
+
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
+
+/*
+ * JFFS2 partitions
+ */
+/* No command line, one static partition
+ * use all the space starting at offset 3MB*/
+#undef CONFIG_CMD_MTDPARTS
+#define CONFIG_JFFS2_DEV		"nor0"
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET	0x00300000
+
+/* mtdparts command line support */
+/*
+#define CONFIG_CMD_MTDPARTS
+#define MTDIDS_DEFAULT		"nor0=r360-0"
+#define MTDPARTS_DEFAULT	"mtdparts=r360-0:-@3m(user)"
+*/
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xFF000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#if defined(DEBUG)
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#else
+#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#endif
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CONFIG_ENV_IS_IN_FLASH	1
+#define	CONFIG_ENV_OFFSET		0x40000	/* Offset of Environment		*/
+#define	CONFIG_ENV_SECT_SIZE	0x20000	/* Total Size of Environment sector	*/
+#define	CONFIG_ENV_SIZE		0x4000	/* Used Size of Environment sector	*/
+#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ *
+ * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
+ */
+#ifdef	CONFIG_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
+#define CONFIG_SYS_PLPRCR							\
+		( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
+#else			/* up to 50 MHz we use a 1:1 clock */
+#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+#endif	/* CONFIG_80MHz */
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CONFIG_SYS_SCCR	(SCCR_TBS     | \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#if 1
+#define CONFIG_IDE_PREINIT	1	/* Use preinit IDE hook */
+#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
+#endif
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xFF000000	/* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV1 | OR_SCY_7_CLK | OR_BI)
+
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+
+
+/*
+ * BR2 and OR2 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+#define CONFIG_SYS_PRELIM_OR2_AM	0xF8000000	/* OR addr mask */
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CONFIG_SYS_OR_TIMING_SDRAM	(OR_ACS_DIV1  | OR_CSNT_SAM | \
+				 OR_SCY_0_CLK | OR_G5LS)
+
+#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR2_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+/*
+ * BR3 and OR3 (CAN Controller)
+ */
+#ifdef CONFIG_CAN_DRIVER
+#define CONFIG_SYS_CAN_BASE		0xC0000000	/* CAN base address   */
+#define CONFIG_SYS_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask */
+#define CONFIG_SYS_OR3_CAN		(CONFIG_SYS_CAN_OR_AM | OR_G5LA |OR_BI)
+#define CONFIG_SYS_BR3_CAN		((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
+				 BR_PS_8 | BR_MS_UPMB | BR_V)
+#endif	/* CONFIG_CAN_DRIVER */
+
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ *	gclk	  CPU clock (not bus clock!)
+ *	Trefresh  Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096  Rows from SDRAM example configuration
+ * 1000  factor s -> ms
+ *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
+ *    4  Number of refresh cycles per period
+ *   64  Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ * 50 MHz => 50.000.000 / Divider =  98
+ * 66 Mhz => 66.000.000 / Divider = 129
+ * 80 Mhz => 80.000.000 / Divider = 156
+ */
+#if   defined(CONFIG_80MHz)
+#define CONFIG_SYS_MAMR_PTA		156
+#elif defined(CONFIG_66MHz)
+#define CONFIG_SYS_MAMR_PTA		129
+#else		/*   50 MHz */
+#define CONFIG_SYS_MAMR_PTA		 98
+#endif	/*CONFIG_??MHz */
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ */
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/RBC823.h b/qemu/roms/u-boot/include/configs/RBC823.h
new file mode 100644
index 000000000..e7e061cb3
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/RBC823.h
@@ -0,0 +1,407 @@
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Modified by Udi Finkelstein udif@udif.com
+ * For the RBC823 board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC823		1	/* This is a MPC823 CPU		*/
+#define CONFIG_RBC823		1	/* ...on a RBC823 module	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
+
+#if 0
+#define DEBUG			1
+#define CONFIG_LAST_STAGE_INIT
+#endif
+#define CONFIG_KEYBOARD		1	/* This board has a custom keybpard */
+#define CONFIG_LCD		1	/* use LCD controller ...	*/
+#define CONFIG_MPC8XX_LCD
+#define CONFIG_HITACHI_SP19X001_Z1A	/* The LCD type we use */
+
+#define	CONFIG_8xx_CONS_SMC2	1	/* Console is on SMC2		*/
+#undef	CONFIG_8xx_CONS_SMC1
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+#if 1
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+#define CONFIG_8xx_GCLK_FREQ    48000000L
+
+#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND							\
+	"bootp; "								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
+	"bootm"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+#undef CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#undef	CONFIG_RTC_MPC8xx		/* don't use internal RTC of MPC8xx (no battery)	*/
+
+#define CONFIG_HARD_I2C
+#define CONFIG_SYS_I2C_SPEED 40000
+#define CONFIG_SYS_I2C_SLAVE 0xfe
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_WRITE_BITS		4
+#define CONFIG_SYS_EEPROM_WRITE_DELAY_MS	10
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_BMP
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_CDP
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_KGDB
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_PORTIO
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_SDRAM
+
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CONFIG_SYS_LOAD_ADDR		0x0100000	/* default load address	*/
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xFF000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFF00000
+#if defined(DEBUG)
+#define	CONFIG_SYS_MONITOR_LEN		(384 << 10)	/* Reserve 256 kB for Monitor	*/
+#else
+#define	CONFIG_SYS_MONITOR_LEN		(384 << 10)	/* Reserve 192 kB for Monitor	*/
+#endif
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CONFIG_ENV_IS_IN_FLASH	1
+#define	CONFIG_ENV_OFFSET		0x10000	/*   Offset   of Environment Sector	*/
+#define	CONFIG_ENV_SIZE		0x10000	/* Total Size of Environment Sector	*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+/*
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+*/
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWRI | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC00 | SIUMCR_FRC)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ *
+ */
+
+/*
+ * for 48 MHz, we use a 4 MHz clock * 12
+ */
+#define CONFIG_SYS_PLPRCR							\
+		( (12-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_LOLRE )
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CONFIG_SYS_SCCR	(SCCR_RTDIV   | SCCR_RTSEL    | SCCR_CRQEN    | \
+			 SCCR_PRQEN   | SCCR_EBDF00   | \
+			 SCCR_COM01   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD001 | \
+			 SCCR_DFALCD00)
+
+#ifdef NOT_USED
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define	CONFIG_IDE_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_PCMCIA		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
+
+#endif
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+/*#define	CONFIG_SYS_DER	0x2002000F*/
+#define CONFIG_SYS_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0xFFF00000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x04000000	/* D.O.C Millenium	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CONFIG_SYS_PRELIM_OR_AM	0xFFF80000	/* OR addr mask */
+
+/* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 7, EHTR = 1	*/
+#define CONFIG_SYS_OR_TIMING_FLASH  (OR_ACS_DIV1 | OR_BI | OR_SCY_7_CLK | OR_EHTR)
+
+#define CONFIG_SYS_OR_TIMING_MSYS   (OR_ACS_DIV1 | OR_BI)
+
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V)
+
+#define CONFIG_SYS_OR1_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_MSYS)
+#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMB | \
+			  BR_PS_8 | BR_V)
+
+/*
+ * BR4 and OR4 (SDRAM)
+ *
+ */
+#define SDRAM_BASE4_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+/*
+ * SDRAM timing:
+ */
+#define CONFIG_SYS_OR_TIMING_SDRAM	(OR_CSNT_SAM)
+
+#define CONFIG_SYS_OR4_PRELIM	(~(SDRAM_MAX_SIZE-1) | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR4_PRELIM	((SDRAM_BASE4_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CONFIG_SYS_MAMR_PTA	187		/* start with divider for 48 MHz	*/
+
+/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_CMD_MTDPARTS
+#define CONFIG_JFFS2_DEV		"nor0"
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET	0x00000000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_CMD_MTDPARTS
+#define MTDIDS_DEFAULT		""
+#define MTDPARTS_DEFAULT	""
+*/
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/RPXlite_DW.h b/qemu/roms/u-boot/include/configs/RPXlite_DW.h
new file mode 100644
index 000000000..50c82c68e
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/RPXlite_DW.h
@@ -0,0 +1,462 @@
+/*
+ * (C) Copyright 2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+/* Yoo. Jonghoon, IPone, yooth@ipone.co.kr
+ * U-BOOT port on RPXlite board
+ */
+
+/*
+ * Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn
+ * U-BOOT port on RPXlite DW version board--RPXlite_DW
+ * June 8 ,2004
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+/* #define DEBUG	1 */
+/* #define DEPLOYMENT	1 */
+
+#undef	CONFIG_MPC860
+#define CONFIG_MPC823		1	/* This is a MPC823e CPU. */
+#define CONFIG_RPXLITE		1	/* RPXlite DW version board */
+
+#define	CONFIG_SYS_TEXT_BASE	0xff000000
+
+#ifdef	CONFIG_LCD			/* with LCD controller ?	*/
+#define CONFIG_MPC8XX_LCD
+#define CONFIG_SPLASH_SCREEN		/* ... with splashscreen support*/
+#endif
+
+#define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		9600	/* console default baudrate = 9600bps	*/
+
+#ifdef DEBUG
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	6	/* autoboot after 6 seconds	*/
+
+#ifdef DEPLOYMENT
+#define CONFIG_BOOT_RETRY_TIME		-1
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT		\
+	"autoboot in %d seconds (stop with 'st')...\n", bootdelay
+#define CONFIG_AUTOBOOT_STOP_STR	"st"
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define CONFIG_RESET_TO_RETRY		1
+#define CONFIG_BOOT_RETRY_MIN		1
+#endif	/* DEPLOYMENT */
+#endif	/* DEBUG */
+
+/* pre-boot commands */
+#define CONFIG_PREBOOT		"setenv stdout serial;setenv stdin serial"
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs console=tty0 console=ttyS0,9600 "	\
+		"root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0"	\
+	"ramargs=setenv bootargs console=tty0 root=/dev/ram rw\0"	\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"gatewayip=172.16.115.254\0"					\
+	"netmask=255.255.255.0\0"					\
+	"kernel_addr=ff040000\0"					\
+	"ramdisk_addr=ff200000\0"					\
+	"ku=era ${kernel_addr} ff1fffff;cp.b 100000 ${kernel_addr} "	\
+		"${filesize};md ${kernel_addr};"			\
+		"echo kernel updating finished\0"			\
+	"uu=protect off 1:0-4;era 1:0-4;cp.b 100000 ff000000 "		\
+		"${filesize};md ff000000;"				\
+		"echo u-boot updating finished\0"			\
+	"eu=protect off 1:6;era 1:6;reset\0"				\
+	"lcd=setenv stdout lcd;setenv stdin lcd\0"			\
+	"ser=setenv stdout serial;setenv stdin serial\0"		\
+	"verify=no"
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+#undef	CONFIG_STATUS_LED		/* disturbs display. Status LED disabled. */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+#if 1	       /* Enable this stuff could make image enlarge about 25KB. Mask it if you
+		  don't want the advanced function */
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_DHCP
+
+#ifdef	CONFIG_SPLASH_SCREEN
+#define CONFIG_CMD_BMP
+#endif
+
+
+/* test-only */
+#define CONFIG_SYS_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
+#define CONFIG_SYS_JFFS2_NUM_BANKS	1	    /* ! second bank contains U-Boot */
+
+#define CONFIG_NETCONSOLE
+
+#endif	/* 1 */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"u-boot>"	/* Monitor Command Prompt   */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0040000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x00C0000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xFA200000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2F00		/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFF000000
+
+#if defined(DEBUG) || defined(CONFIG_CMD_IDE)
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#else
+#define CONFIG_SYS_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor */
+#endif
+
+#define CONFIG_SYS_MONITOR_BASE	0xFF000000
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	71	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#ifdef	CONFIG_ENV_IS_IN_NVRAM
+#define CONFIG_ENV_ADDR		0xFA000100
+#define CONFIG_ENV_SIZE		0x1000
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OFFSET		0x30000 /* Offset of Environment Sector		*/
+#define CONFIG_ENV_SIZE		0x8000	/* Total Size of Environment Sector	*/
+#endif	/* CONFIG_ENV_IS_IN_NVRAM */
+
+#define CONFIG_SYS_RESET_ADDRESS	((ulong)((((immap_t *)CONFIG_SYS_IMMR)->im_clkrst.res)))
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control	32-bit			12-35
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif	/* We can get SYPCR: 0xFFFF0689. */
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration	32-bit			 12-30
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_MLRC10)	       /* SIUMCR:0x00000800 */
+
+/*---------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control	 16-bit			 12-16
+ *---------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
+/* TBSCR: 0x00C3 [SAM] */
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register 16-bit	 12-18
+ *-----------------------------------------------------------------------
+ * [RTC enabled but not stopped on FRZ]
+ */
+#define CONFIG_SYS_RTCSC    (RTCSC_SEC | RTCSC_ALR | RTCSC_RTE) /* RTCSC:0x00C1	*/
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control 16-bit		 12-23
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ * [Periodic timer enabled,Periodic timer interrupt disable. ]
+ */
+#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE)  /* PISCR:0x0083		*/
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register	32-bit	 5-7
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ */
+/* up to 64 MHz we use a 1:2 clock */
+#if defined(RPXlite_64MHz)
+#define CONFIG_SYS_PLPRCR	( (7 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )   /*PLPRCR: 0x00700000. */
+#else
+#define CONFIG_SYS_PLPRCR	( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
+#endif
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		5-3
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF00
+/* Up to 48MHz system clock, we use 1:1 SYSTEM/BUS ratio */
+#if defined(RPXlite_64MHz)
+#define CONFIG_SYS_SCCR	( SCCR_TBS | SCCR_EBDF01 )  /* %%%SCCR:0x02020000 */
+#else
+#define CONFIG_SYS_SCCR	( SCCR_TBS | SCCR_EBDF00 )  /* %%%SCCR:0x02000000 */
+#endif
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_IDE_PREINIT	1	/* Use preinit IDE hook */
+#define CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card Adapter */
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
+#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
+
+#define		CONFIG_SYS_DER		0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0 and OR0 (FLASH)
+ */
+#define FLASH_BASE_PRELIM	0xFC000000	/* FLASH base	*/
+#define CONFIG_SYS_PRELIM_OR_AM	0xFC000000	/* OR addr mask */
+
+/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 8, ETHR = 0, BIH = 1 */
+#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_8_CLK | OR_BI)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
+
+/*
+ * BR1 and OR1 (SDRAM)
+ *
+ */
+#define SDRAM_BASE_PRELIM	0x00000000	/* SDRAM base	*/
+#define SDRAM_MAX_SIZE		0x08000000	/* max 128 MB in system */
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000E00
+#define CONFIG_SYS_OR_AM_SDRAM		(-(SDRAM_MAX_SIZE & OR_AM_MSK))
+#define CONFIG_SYS_OR1_PRELIM	( CONFIG_SYS_OR_AM_SDRAM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR1_PRELIM	((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+/* RPXlite mem setting */
+#define CONFIG_SYS_BR3_PRELIM	0xFA400001		/* BCSR */
+#define CONFIG_SYS_OR3_PRELIM	0xFF7F8900
+#define CONFIG_SYS_BR4_PRELIM	0xFA000401		/* NVRAM&SRAM */
+#define CONFIG_SYS_OR4_PRELIM	0xFFFE0040
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+/* periodic timer for refresh */
+#if defined(RPXlite_64MHz)
+#define CONFIG_SYS_MAMR_PTA	32
+#else
+#define CONFIG_SYS_MAMR_PTA	20
+#endif
+
+/*
+ * Refresh clock Prescalar
+ */
+#define CONFIG_SYS_MPTPR	MPTPR_PTP_DIV2
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 9 column SDRAM */
+#define CONFIG_SYS_MAMR_9COL  ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE | \
+			MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10)
+/* CONFIG_SYS_MAMR_9COL:0x20904000 @ 64MHz */
+
+/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
+/* Configuration variable added by yooth. */
+/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */
+/*
+ * BCSRx
+ *
+ * Board Status and Control Registers
+ *
+ */
+#define BCSR0 0xFA400000
+#define BCSR1 0xFA400001
+#define BCSR2 0xFA400002
+#define BCSR3 0xFA400003
+
+#define BCSR0_ENMONXCVR 0x01	/* Monitor XVCR Control */
+#define BCSR0_ENNVRAM	0x02	/* CS4# Control */
+#define BCSR0_LED5	0x04	/* LED5 control 0='on' 1='off' */
+#define BCSR0_LED4	0x08	/* LED4 control 0='on' 1='off' */
+#define BCSR0_FULLDPLX	0x10	/* Ethernet XCVR Control */
+#define BCSR0_COLTEST	0x20
+#define BCSR0_ETHLPBK	0x40
+#define BCSR0_ETHEN	0x80
+
+#define BCSR1_PCVCTL7	0x01	/* PC Slot B Control */
+#define BCSR1_PCVCTL6	0x02
+#define BCSR1_PCVCTL5	0x04
+#define BCSR1_PCVCTL4	0x08
+#define BCSR1_IPB5SEL	0x10
+
+#define BCSR1_SMC1CTS	0x40	/* Added by SAM. */
+#define BCSR1_SMC1TRS	0x80	/* Added by SAM. */
+
+#define BCSR2_ENRTCIRQ	0x01	/* Added by SAM. */
+#define BCSR2_ENBRG1	0x04	/* Added by SAM. */
+
+#define BCSR2_ENPA5HDR	0x08	/* USB Control */
+#define BCSR2_ENUSBCLK	0x10
+#define BCSR2_USBPWREN	0x20
+#define BCSR2_USBSPD	0x40
+#define BCSR2_USBSUSP	0x80
+
+#define BCSR3_BWKAPWR	0x01   /* Changed by SAM. Backup battery situation */
+#define BCSR3_IRQRTC	0x02   /* Changed by SAM. NVRAM Battery */
+#define BCSR3_RDY_BSY	0x04   /* Changed by SAM. Flash Operation */
+#define BCSR3_MPLX_LIN	0x08   /* Changed by SAM. Linear or Multiplexed address Mode */
+
+#define BCSR3_D27	0x10	  /* Dip Switch settings */
+#define BCSR3_D26	0x20
+#define BCSR3_D25	0x40
+#define BCSR3_D24	0x80
+
+/*
+ * Environment setting
+ */
+#define CONFIG_ETHADDR	00:10:EC:00:37:5B
+#define CONFIG_IPADDR	172.16.115.7
+#define CONFIG_SERVERIP 172.16.115.6
+#define CONFIG_ROOTPATH "/workspace/myfilesystem/target/"
+#define CONFIG_BOOTFILE "uImage.rpxusb"
+#define CONFIG_HOSTNAME LITE_H1_DW
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/RRvision.h b/qemu/roms/u-boot/include/configs/RRvision.h
new file mode 100644
index 000000000..97f779871
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/RRvision.h
@@ -0,0 +1,450 @@
+/*
+ * (C) Copyright 2000, 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC823		1	/* This is a MPC823 CPU		*/
+#define CONFIG_RRVISION		1	/* ...on a RRvision board	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0x40000000
+
+#define CONFIG_8xx_GCLK_FREQ 64000000
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	3	/* autoboot after 5 seconds	*/
+#endif
+
+#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+
+#define CONFIG_PREBOOT	"setenv stdout serial"
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_ETHADDR                00:50:C2:00:E0:70
+#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
+#define CONFIG_IPADDR                 10.0.0.5
+#define CONFIG_SERVERIP               10.0.0.2
+#define CONFIG_NETMASK                255.0.0.0
+#define CONFIG_ROOTPATH               "/opt/eldk/ppc_8xx"
+#define CONFIG_BOOTCOMMAND            "run flash_self"
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}"	\
+		":${gatewayip}:${netmask}:${hostname}:${netdev}:off\0"	\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+	"load=tftp 100000 /tftpboot/u-boot.bin\0"			\
+	"update=protect off 1:0-8;era 1:0-8;"				\
+		"cp.b 100000 40000000 ${filesize};"			\
+		"setenv filesize;saveenv\0"				\
+	"kernel_addr=40040000\0"					\
+	"ramdisk_addr=40100000\0"					\
+	"kernel_img=/tftpboot/uImage\0"					\
+	"kernel_load=tftp 200000 ${kernel_img}\0"			\
+	"net_nfs=run kernel_load nfsargs addip addtty;bootm\0"		\
+	"flash_nfs=run nfsargs addip addtty;bootm ${kernel_addr}\0"	\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"
+
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#undef	CONFIG_STATUS_LED		/* disturbs display		*/
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+
+#ifdef CONFIG_LCD
+#define CONFIG_MPC8XX_LCD
+#else
+#define CONFIG_VIDEO		1	/* To enable the video initialization */
+
+/* Video related */
+#define CONFIG_VIDEO_LOGO			1	/* Show the logo */
+#define CONFIG_VIDEO_ENCODER_AD7179		1	/* Enable this encoder */
+#define CONFIG_VIDEO_ENCODER_AD7179_ADDR	0x2A	/* ALSB to ground */
+#endif
+
+/* enable I2C and select the hardware/software driver */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED	50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PB_SCL		0x00000020	/* PB 26 */
+#define PB_SDA		0x00000010	/* PB 27 */
+
+#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
+#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
+#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
+#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
+#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
+#define I2C_DELAY	udelay(1)	/* 1/4 I2C clock duration */
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_DATE
+
+#undef CONFIG_CMD_PCMCIA
+#undef CONFIG_CMD_IDE
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	71	/* max number of sectors on one chip	*/
+
+/* timeout values are in ticks = ms */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(120*CONFIG_SYS_HZ)	/* Timeout for Flash Erase	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(1 * CONFIG_SYS_HZ)	/* Timeout for Flash Write	*/
+
+#define	CONFIG_ENV_IS_IN_FLASH	1
+#define	CONFIG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
+#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef	CONFIG_CAN_DRIVER
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#else	/* we must activate GPL5 in the SIUMCR for CAN */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF | PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ */
+
+/* for 64 MHz, we use a 16 MHz clock * 4 */
+#define CONFIG_SYS_PLPRCR ( (4-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CONFIG_SYS_SCCR	(/* SCCR_TBS  | */ SCCR_RTSEL | SCCR_RTDIV    | \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_IDE_PREINIT	1	/* Use preinit IDE hook */
+#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+/*#define	CONFIG_SYS_DER	0x2002000F*/
+#define CONFIG_SYS_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
+
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
+#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
+
+#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#ifndef	CONFIG_CAN_DRIVER
+#define	CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
+#define	CONFIG_SYS_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CONFIG_SYS_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CONFIG_SYS_OR3_CAN		(CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CONFIG_SYS_BR3_CAN		((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
+					BR_PS_8 | BR_MS_UPMB | BR_V )
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ *	gclk	  CPU clock (not bus clock!)
+ *	Trefresh  Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096  Rows from SDRAM example configuration
+ * 1000  factor s -> ms
+ *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
+ *    4  Number of refresh cycles per period
+ *   64  Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ * 50 MHz => 50.000.000 / Divider =  98
+ * 66 Mhz => 66.000.000 / Divider = 129
+ * 80 Mhz => 80.000.000 / Divider = 156
+ */
+#define CONFIG_SYS_MAMR_PTA		129
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ */
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/Rattler.h b/qemu/roms/u-boot/include/configs/Rattler.h
new file mode 100644
index 000000000..a1e2ae975
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/Rattler.h
@@ -0,0 +1,279 @@
+/*
+ * Copyright (C) 2004 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * U-Boot configuration for Analogue&Micro Rattler boards.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifdef CONFIG_MPC8248
+#define CPU_ID_STR		"MPC8248"
+#else
+#define CPU_ID_STR		"MPC8250"
+#endif /* CONFIG_MPC8248 */
+
+#define	CONFIG_SYS_TEXT_BASE	0xFE000000
+
+#define CONFIG_CPM2		1	/* Has a CPM2 */
+
+#define CONFIG_RATTLER			/* Analogue&Micro Rattler board */
+
+/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * Select serial console configuration
+ *
+ * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ */
+#define	CONFIG_CONS_ON_SMC		/* Console is on SMC         */
+#undef  CONFIG_CONS_ON_SCC		/* It's not on SCC           */
+#undef	CONFIG_CONS_NONE		/* It's not on external UART */
+#define CONFIG_CONS_INDEX	1	/* SMC1 is used for console  */
+
+/*
+ * Select ethernet configuration
+ *
+ * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
+ * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
+ * SCC, 1-3 for FCC)
+ *
+ * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
+ * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
+ * must be unset.
+ */
+#undef	CONFIG_ETHER_ON_SCC		/* Ethernet is not on SCC */
+#define CONFIG_ETHER_ON_FCC		/* Ethernet is on FCC     */
+#undef	CONFIG_ETHER_NONE		/* No external Ethernet   */
+
+#ifdef CONFIG_ETHER_ON_FCC
+
+#define CONFIG_ETHER_INDEX	1	/* FCC1 is used for Ethernet */
+
+#if   (CONFIG_ETHER_INDEX == 1)
+
+/* - Rx clock is CLK11
+ * - Tx clock is CLK10
+ * - BDs/buffers on 60x bus
+ * - Full duplex
+ */
+#define CONFIG_SYS_CMXFCR_MASK1		(CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
+#define CONFIG_SYS_CMXFCR_VALUE1	(CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10)
+#define CONFIG_SYS_CPMFCR_RAMTYPE	0
+#define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
+
+#elif (CONFIG_ETHER_INDEX == 2)
+
+/* - Rx clock is CLK15
+ * - Tx clock is CLK14
+ * - BDs/buffers on 60x bus
+ * - Full duplex
+ */
+#define CONFIG_SYS_CMXFCR_MASK2		(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+#define CONFIG_SYS_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK14)
+#define CONFIG_SYS_CPMFCR_RAMTYPE	0
+#define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
+
+#endif /* CONFIG_ETHER_INDEX */
+
+#define CONFIG_MII			/* MII PHY management        */
+#define CONFIG_BITBANGMII		/* Bit-banged MDIO interface */
+/*
+ * GPIO pins used for bit-banged MII communications
+ */
+#define MDIO_PORT		2	/* Port C */
+#define MDIO_DECLARE		volatile ioport_t *iop = ioport_addr ( \
+					(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
+#define MDC_DECLARE		MDIO_DECLARE
+
+#define MDIO_ACTIVE		(iop->pdir |=  0x00400000)
+#define MDIO_TRISTATE		(iop->pdir &= ~0x00400000)
+#define MDIO_READ		((iop->pdat &  0x00400000) != 0)
+
+#define MDIO(bit)		if(bit) iop->pdat |=  0x00400000; \
+				else	iop->pdat &= ~0x00400000
+
+#define MDC(bit)		if(bit) iop->pdat |=  0x00800000; \
+				else	iop->pdat &= ~0x00800000
+
+#define MIIDELAY		udelay(1)
+
+#endif /* CONFIG_ETHER_ON_FCC */
+
+#ifndef CONFIG_8260_CLKIN
+#define CONFIG_8260_CLKIN	100000000	/* in Hz */
+#endif
+
+#define CONFIG_BAUDRATE		38400
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+#define CONFIG_BOOTCOMMAND	"bootm FE040000"	/* autoboot command */
+#define CONFIG_BOOTARGS		"root=/dev/mtdblock2 rw mtdparts=phys:1M(ROM)ro,-(root)"
+
+#if defined(CONFIG_CMD_KGDB)
+#undef	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
+#define CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
+#undef	CONFIG_KGDB_NONE		/* define if kgdb on something else */
+#define CONFIG_KGDB_INDEX	2	/* which serial channel for kgdb */
+#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port at */
+#endif
+
+#define CONFIG_BZIP2	/* include support for bzip2 compressed images */
+#undef	CONFIG_WATCHDOG			/* disable platform specific watchdog */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size  */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size  */
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
+
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#define CONFIG_SYS_FLASH_BASE		0xFE000000
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max num of sects on one chip */
+
+#define	CONFIG_SYS_DIRECT_FLASH_TFTP
+
+#if defined(CONFIG_CMD_JFFS2)
+#define CONFIG_SYS_JFFS2_NUM_BANKS	CONFIG_SYS_MAX_FLASH_BANKS
+#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
+
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition */
+#undef CONFIG_CMD_MTDPARTS
+#define CONFIG_JFFS2_DEV		"nor0"
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET	0x00100000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_CMD_MTDPARTS
+#define MTDIDS_DEFAULT		"nor0=rattler-0"
+#define MTDPARTS_DEFAULT	"mtdparts=rattler-0:-@1m(jffs2)"
+*/
+#endif /* CONFIG_CMD_JFFS2 */
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+
+#define CONFIG_ENV_IS_IN_FLASH
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#endif /* CONFIG_ENV_IS_IN_FLASH */
+
+#define CONFIG_SYS_DEFAULT_IMMR	0xFF010000
+
+#define CONFIG_SYS_IMMR		0xF0000000
+
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_SIZE		32
+#define CONFIG_SYS_SDRAM_BR		(CONFIG_SYS_SDRAM_BASE | 0x00000041)
+#define CONFIG_SYS_SDRAM_OR		0xFE002EC0
+
+#define CONFIG_SYS_BCSR		0xFC000000
+
+/* Hard reset configuration word */
+#define CONFIG_SYS_HRCW_MASTER		0x0A06875A /* Not used - provided by FPGA */
+/* No slaves */
+#define CONFIG_SYS_HRCW_SLAVE1		0
+#define CONFIG_SYS_HRCW_SLAVE2		0
+#define CONFIG_SYS_HRCW_SLAVE3		0
+#define CONFIG_SYS_HRCW_SLAVE4		0
+#define CONFIG_SYS_HRCW_SLAVE5		0
+#define CONFIG_SYS_HRCW_SLAVE6		0
+#define CONFIG_SYS_HRCW_SLAVE7		0
+
+#define CONFIG_SYS_MALLOC_LEN		(4096 << 10)	/* Reserve 4 MB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPUs */
+#if defined(CONFIG_CMD_KGDB)
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+#define CONFIG_SYS_HID0_INIT		0
+#define CONFIG_SYS_HID0_FINAL		(HID0_ICE | HID0_IFEM | HID0_ABE)
+
+#define CONFIG_SYS_HID2		0
+
+#define CONFIG_SYS_SIUMCR		0x0E04C000
+#define CONFIG_SYS_SYPCR		0xFFFFFFC3
+#define CONFIG_SYS_BCR			0x00000000
+#define CONFIG_SYS_SCCR		SCCR_DFBRG01
+
+#define CONFIG_SYS_RMR			RMR_CSRE
+#define CONFIG_SYS_TMCNTSC		(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+#define CONFIG_SYS_PISCR		(PISCR_PS|PISCR_PTF|PISCR_PTE)
+#define CONFIG_SYS_RCCR		0
+
+#define CONFIG_SYS_PSDMR		0x8249A452
+#define CONFIG_SYS_PSRT		0x1F
+#define CONFIG_SYS_MPTPR		0x2000
+
+#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | 0x00001001)
+#define CONFIG_SYS_OR0_PRELIM		0xFF001ED6
+#define CONFIG_SYS_BR7_PRELIM		(CONFIG_SYS_BCSR | 0x00000801)
+#define CONFIG_SYS_OR7_PRELIM		0xFFFF87F6
+
+#define CONFIG_SYS_RESET_ADDRESS	0xC0000000
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/SIMPC8313.h b/qemu/roms/u-boot/include/configs/SIMPC8313.h
new file mode 100644
index 000000000..46157ccc4
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/SIMPC8313.h
@@ -0,0 +1,580 @@
+/*
+ * Copyright (C) Sheldon Instruments, Inc. 2008
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/*
+ * simpc8313 board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_NAND_U_BOOT
+
+#define CONFIG_E300			1
+#define CONFIG_MPC831x			1
+#define CONFIG_MPC8313			1
+
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(512 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_START	0x00100100
+#define CONFIG_SYS_NAND_U_BOOT_RELOC	0x00010000
+#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
+
+#define CONFIG_SYS_TEXT_BASE	0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */
+#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
+
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
+#else
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+
+#define CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_FSL_ELBC			1
+
+#define CONFIG_MISC_INIT_R
+
+/*
+ * On-board devices
+ *
+ * TSEC1 is Marvell PHY 88E1118
+ */
+
+#define CONFIG_SYS_33MHZ
+
+#define CONFIG_83XX_CLKIN		33333333	/* in Hz */
+
+#define CONFIG_SYS_CLK_FREQ		CONFIG_83XX_CLKIN
+
+#define CONFIG_SYS_IMMR			0xE0000000
+
+#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+#define CONFIG_DEFAULT_IMMR		CONFIG_SYS_IMMR
+#endif
+
+#define CONFIG_SYS_MEMTEST_START	0x00001000
+#define CONFIG_SYS_MEMTEST_END		0x07f00000
+
+#define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
+#define CONFIG_SYS_ACR_RPTCNT	3	/* Arbiter repeat count (0-7) */
+
+/*
+ * Device configurations
+ */
+#define CONFIG_TSEC1
+
+/*
+ * DDR Setup
+ */
+					/* DDR is system memory*/
+#define CONFIG_SYS_DDR_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
+
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_MAX_MEM_MAPPED		(512 << 20)
+
+#define CONFIG_SYS_DDRCDR		(DDRCDR_EN \
+					| DDRCDR_PZ_NOMZ \
+					| DDRCDR_NZ_NOMZ \
+					| DDRCDR_M_ODR)
+					/* 0x73000002 TODO ODR & DRN ? */
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_NO_FLASH
+
+#if !defined(CONFIG_NAND_SPL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM*/
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
+#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)	/* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN	(512 * 1024)	/* Reserved for malloc */
+
+/*
+ * Local Bus LCRR and LBCR regs
+ */
+#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
+#define CONFIG_SYS_LCRR_EADC	LCRR_EADC_1
+#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_2
+#define CONFIG_SYS_LBC_LBCR	(0x00040000 /* TODO */ \
+				| (0xFF << LBCR_BMT_SHIFT) \
+				| 0xF)	/* 0x0004ff0f */
+
+				/* LB refresh timer prescal, 266MHz/32 */
+#define CONFIG_SYS_LBC_MRTPR	0x20000000
+
+/* drivers/mtd/nand/nand.c */
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_SYS_NAND_BASE		0xFFF00000
+#else
+#define CONFIG_SYS_NAND_BASE		0xE2800000
+#endif
+#define CONFIG_SYS_FPGA_BASE		0xFF000000
+
+#define CONFIG_CMD_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_NAND_FSL_ELBC		1
+
+#define CONFIG_SYS_NAND_BR_PRELIM	(CONFIG_SYS_NAND_BASE \
+				| BR_DECC_CHK_GEN	/* Use HW ECC */ \
+				| BR_PS_8		/* 8 bit Port */ \
+				| BR_MS_FCM		/* MSEL = FCM */ \
+				| BR_V)			/* valid */
+
+#ifdef CONFIG_NAND_SP
+#define CONFIG_SYS_NAND_OR_PRELIM	(OR_AM_32KB \
+					| OR_FCM_CSCT \
+					| OR_FCM_CST \
+					| OR_FCM_CHT \
+					| OR_FCM_SCY_1 \
+					| OR_FCM_TRLX \
+					| OR_FCM_EHTR)
+#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)
+#define CONFIG_SYS_NAND_PAGE_SIZE	512	/* NAND chip page size */
+					/* NAND chip block size */
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(16 << 10)
+#define NAND_CACHE_PAGES		32
+#elif defined(CONFIG_NAND_LP)
+#define CONFIG_SYS_NAND_OR_PRELIM	(OR_AM_256KB \
+					| OR_FCM_PGS \
+					| OR_FCM_CSCT \
+					| OR_FCM_CST \
+					| OR_FCM_CHT \
+					| OR_FCM_SCY_1 \
+					| OR_FCM_TRLX \
+					| OR_FCM_EHTR)
+#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_256KB)
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048	/* NAND chip page size */
+					/* NAND chip block size */
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 << 10)
+#define NAND_CACHE_PAGES		64
+#else
+#error Page size of NAND not defined.
+#endif /* CONFIG_NAND_SP */
+
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	CONFIG_SYS_NAND_BLOCK_SIZE
+
+#define CONFIG_SYS_BR0_PRELIM		CONFIG_SYS_NAND_BR_PRELIM
+#define CONFIG_SYS_OR0_PRELIM		CONFIG_SYS_NAND_OR_PRELIM
+
+#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_NAND_BASE
+
+#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM	CONFIG_SYS_LBLAWBAR0_PRELIM
+#define CONFIG_SYS_NAND_LBLAWAR_PRELIM	CONFIG_SYS_LBLAWAR0_PRELIM
+
+#define CONFIG_SYS_BR1_PRELIM		(CONFIG_SYS_FPGA_BASE \
+					| BR_PS_16 \
+					| BR_MS_UPMA \
+					| BR_V)
+#define CONFIG_SYS_OR1_PRELIM		(OR_AM_2MB \
+					| OR_UPM_BCTLD)
+
+#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_FPGA_BASE
+#define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_2MB)
+
+/*
+ * JFFS2 configuration
+ */
+#define CONFIG_JFFS2_NAND
+#define CONFIG_JFFS2_DEV	"nand0"
+
+/* mtdparts command line support */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
+#define MTDIDS_DEFAULT		"nand0=nand0"
+#define MTDPARTS_DEFAULT	"mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)"
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT		1
+#define CONFIG_OF_BOARD_SETUP		1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1		(CONFIG_SYS_IMMR+0x4500)
+#define CONFIG_SYS_NS16550_COM2		(CONFIG_SYS_IMMR+0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
+#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS		0xE2000000
+#define CONFIG_SYS_PCI1_IO_SIZE		0x00100000	/* 1M */
+
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID	0x1057	/* Motorola */
+
+/*
+ * TSEC
+ */
+#define CONFIG_TSEC_ENET		/* TSEC ethernet support */
+
+#define CONFIG_GMII			/* MII PHY management */
+
+#ifdef CONFIG_TSEC1
+#define CONFIG_HAS_ETH0
+#define CONFIG_TSEC1_NAME		"TSEC0"
+#define CONFIG_SYS_TSEC1_OFFSET		0x24000
+#define TSEC1_PHY_ADDR			0x0
+#define TSEC1_FLAGS			TSEC_GIGABIT
+#define TSEC1_PHYIDX			0
+#endif
+
+#ifdef CONFIG_TSEC2
+#define CONFIG_HAS_ETH1
+#define CONFIG_TSEC2_NAME		"TSEC1"
+#define CONFIG_SYS_TSEC2_OFFSET		0x25000
+#define TSEC2_PHY_ADDR			4
+#define TSEC2_FLAGS			TSEC_GIGABIT
+#define TSEC2_PHYIDX			0
+#endif
+
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME			"TSEC1"
+
+/*
+ * Configure on-board RTC
+ */
+#define CONFIG_RTC_DS1337
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68
+
+/*
+ * Environment
+ */
+#if defined(CONFIG_NAND_U_BOOT)
+	#define CONFIG_ENV_IS_IN_NAND	1
+	#define CONFIG_ENV_OFFSET	(768 * 1024)
+	#define CONFIG_ENV_SECT_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
+	#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
+	#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+	#define CONFIG_ENV_RANGE	(CONFIG_ENV_SECT_SIZE * 4)
+	#define CONFIG_ENV_OFFSET_REDUND	\
+					(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
+#elif !defined(CONFIG_SYS_RAMBOOT)
+	#define CONFIG_ENV_IS_IN_FLASH	1
+	#define CONFIG_ENV_ADDR		\
+			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+	#define CONFIG_ENV_SECT_SIZE	0x10000	/* 64K(one sector) for env */
+	#define CONFIG_ENV_SIZE		0x2000
+
+/* Address and size of Redundant Environment Sector */
+#else
+	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
+	#define CONFIG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO		1 /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1 /* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_FLASH
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_JFFS2
+
+#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
+	#undef CONFIG_CMD_SAVEENV
+	#undef CONFIG_CMD_LOADS
+#endif
+
+#define CONFIG_CMDLINE_EDITING	1
+#define CONFIG_AUTO_COMPLETE	/* add autocompletion support   */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE		\
+				+ sizeof(CONFIG_SYS_PROMPT)	\
+				+ 16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+				/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+				/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)
+
+#define CONFIG_SYS_RCWH_PCIHOST	0x80000000	/* PCIHOST */
+
+#define CONFIG_SYS_HRCW_LOW	(HRCWL_LCL_BUS_TO_SCB_CLK_1X1	\
+				| 0x20000000 /* reserved */	\
+				| HRCWL_DDR_TO_SCB_CLK_2X1	\
+				| HRCWL_CSB_TO_CLKIN_4X1	\
+				| HRCWL_CORE_TO_CSB_2_5X1)
+
+#define CONFIG_SYS_NS16550_CLK	(CONFIG_83XX_CLKIN * 4)
+
+#define CONFIG_SYS_HRCW_HIGH_BASE	(HRCWH_PCI_HOST	\
+				| HRCWH_PCI1_ARBITER_ENABLE	\
+				| HRCWH_CORE_ENABLE		\
+				| HRCWH_BOOTSEQ_DISABLE		\
+				| HRCWH_SW_WATCHDOG_DISABLE	\
+				| HRCWH_TSEC1M_IN_RGMII		\
+				| HRCWH_TSEC2M_IN_RGMII		\
+				| HRCWH_BIG_ENDIAN		\
+				| HRCWH_LALE_NORMAL)
+
+#ifdef CONFIG_NAND_LP
+#define CONFIG_SYS_HRCW_HIGH	(CONFIG_SYS_HRCW_HIGH_BASE	\
+				| HRCWH_FROM_0XFFF00100		\
+				| HRCWH_ROM_LOC_NAND_LP_8BIT	\
+				| HRCWH_RL_EXT_NAND)
+#else
+#define CONFIG_SYS_HRCW_HIGH	(CONFIG_SYS_HRCW_HIGH_BASE	\
+				| HRCWH_FROM_0XFFF00100		\
+				| HRCWH_ROM_LOC_NAND_SP_8BIT	\
+				| HRCWH_RL_EXT_NAND)
+#endif
+
+/* System IO Config */
+#define CONFIG_SYS_SICRH	(SICRH_ETSEC2_B	\
+				| SICRH_ETSEC2_C	\
+				| SICRH_ETSEC2_D	\
+				| SICRH_ETSEC2_E	\
+				| SICRH_ETSEC2_F	\
+				| SICRH_ETSEC2_G	\
+				| SICRH_TSOBI1		\
+				| SICRH_TSOBI2)
+#define CONFIG_SYS_SICRL	(SICRL_LBC		\
+				| SICRL_USBDR_10	\
+				| SICRL_ETSEC2_A)
+
+#define CONFIG_SYS_HID0_INIT	0x000000000
+#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK \
+				| HID0_ENABLE_INSTRUCTION_CACHE \
+				| HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
+
+#define CONFIG_SYS_HID2		HID2_HBE
+
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
+/* DDR @ 0x00000000 */
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_IBAT1L	((CONFIG_SYS_SDRAM_BASE + 0x10000000) \
+				| BATL_PP_RW)
+#define CONFIG_SYS_IBAT1U	((CONFIG_SYS_SDRAM_BASE + 0x10000000) \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+
+/* PCI @ 0x80000000 */
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PCI1_MEM_BASE \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_PCI1_MMIO_BASE \
+				| BATL_PP_RW \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_PCI1_MMIO_BASE \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+
+/* PCI2 not supported on 8313 */
+#define CONFIG_SYS_IBAT4L	(0)
+#define CONFIG_SYS_IBAT4U	(0)
+
+/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
+#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_IMMR \
+				| BATL_PP_RW \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_IMMR \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+
+/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
+#define CONFIG_SYS_IBAT6L	(0xF0000000 \
+				| BATL_PP_RW \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT6U	(0xF0000000 \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+
+#define CONFIG_SYS_IBAT7L	(0)
+#define CONFIG_SYS_IBAT7U	(0)
+
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
+#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
+#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
+#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
+#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_NETDEV		"eth1"
+
+#define CONFIG_HOSTNAME		simpc8313
+#define CONFIG_ROOTPATH		"/tftpboot/"
+#define CONFIG_BOOTFILE		"/tftpboot/uImage"
+				/* U-Boot image on TFTP server */
+#define CONFIG_UBOOTPATH	"u-boot-nand.bin"
+#define CONFIG_FDTFILE		"simpc8313.dtb"
+
+				/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		500000
+#define CONFIG_BOOTDELAY	5	/* 5 second delay */
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_BOOTCOMMAND	"nand read $loadaddr kernel 600000;" \
+					"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"netdev=" CONFIG_NETDEV "\0"					\
+	"ethprime=TSEC1\0"						\
+	"uboot=" CONFIG_UBOOTPATH "\0"					\
+	"tftpflash=tftpboot $loadaddr $uboot; "				\
+		"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
+			" +$filesize; "	\
+		"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
+			" +$filesize; "	\
+		"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
+			" $filesize; "	\
+		"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
+			" +$filesize; "	\
+		"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
+			" $filesize\0"	\
+	"fdtaddr=ae0000\0"						\
+	"fdtfile=" CONFIG_FDTFILE "\0"					\
+	"console=ttyS0\0"						\
+	"setbootargs=setenv bootargs "					\
+		"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
+	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath "	\
+		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"	\
+							"$netdev:off "	\
+		"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
+	"load_uboot=tftp 100000 u-boot-nand.bin\0"			\
+	"burn_uboot=nand erase u-boot 80000; "				\
+		"nand write 100000 u-boot $filesize\0"			\
+	"update_uboot=run load_uboot;run burn_uboot\0"			\
+	"mtdids=nand0=nand0\0"						\
+	"mtdparts=mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)\0"	\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
+	"bootargs=root=/dev/mtdblock2 rootfstype=jffs2 rw "		\
+		"console=ttyS0,115200\0"				\
+	""
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv rootdev /dev/nfs;"					\
+	"run setbootargs;"						\
+	"run setipargs;"						\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+	"setenv rootdev /dev/ram;"					\
+	"run setbootargs;"						\
+	"tftp $ramdiskaddr $ramdiskfile;"				\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/SM850.h b/qemu/roms/u-boot/include/configs/SM850.h
new file mode 100644
index 000000000..a7e44647a
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/SM850.h
@@ -0,0 +1,351 @@
+/*
+ * (C) Copyright 2000-2008
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#undef TQM8xxL_80MHz	/*	1	/ * define for 80 MHz CPU only	*/
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC850		1	/* This is a MPC850 CPU		*/
+#define CONFIG_SM850		1	/*...on a MPC850 Service Module	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0x40000000
+
+#define	CONFIG_8xx_CONS_SMC2	1	/* Console is on SMC2		*/
+#define CONFIG_SYS_SMC_RXBUFLEN	128
+#define CONFIG_SYS_MAXIDLE	10
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND							\
+	"bootp; "								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
+	"bootm"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#undef	CONFIG_STATUS_LED		/* Status LED not enabled	*/
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+#define CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DATE
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#if defined(CONFIG_CMD_KGDB) && defined(KGDB_DEBUG)
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#if defined(DEBUG)
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#else
+#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#endif
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+/* use CFI flash driver */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	71	/* max number of sectors on one chip */
+
+#define	CONFIG_ENV_IS_IN_FLASH	1
+#define	CONFIG_ENV_OFFSET	0x8000	/*   Offset   of Environment Sector	*/
+#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+#define CONFIG_MISC_INIT_R		/* Make sure to remap flashes correctly */
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef CONFIG_CAN_DRIVER
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#else	/* we must activate GPL5 in the SIUMCR for CAN */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ *
+ * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
+ */
+#ifdef TQM8xxL_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
+#define CONFIG_SYS_PLPRCR							\
+		( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
+#else
+#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+#endif	/* TQM8xxL_80MHz */
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#ifdef TQM8xxL_80MHz	/* for 80 MHz, we use a 16 MHz clock * 5 */
+#define CONFIG_SYS_SCCR	(/* SCCR_TBS  | */ \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+#else			/* up to 50 MHz we use a 1:1 clock */
+#define CONFIG_SYS_SCCR	(SCCR_TBS     | \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+#endif	/* TQM8xxL_80MHz */
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV2 | OR_BI | \
+				 OR_SCY_5_CLK | OR_EHTR)
+
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
+#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
+
+#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#ifndef	CONFIG_CAN_DRIVER
+#define	CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
+#define CONFIG_SYS_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CONFIG_SYS_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CONFIG_SYS_OR3_CAN		(CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CONFIG_SYS_BR3_CAN		((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
+					BR_PS_8 | BR_MS_UPMB | BR_V )
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CONFIG_SYS_MAMR_PTA	97		/* start with divider for 100 MHz	*/
+
+/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_HWCONFIG		1
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/SPD823TS.h b/qemu/roms/u-boot/include/configs/SPD823TS.h
new file mode 100644
index 000000000..a8b4fbb7f
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/SPD823TS.h
@@ -0,0 +1,402 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC823		1	/* This is a MPC823 CPU		*/
+#define CONFIG_SPD823TS		1	/* ...on a SPD823TS board	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xFF000000
+
+#define CONFIG_RESET_PHY_R	1	/* Call reset_phy()		*/
+
+#define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		115200
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+
+#define CONFIG_BOOTCOMMAND	"bootp" /* autoboot command		*/
+
+#define CONFIG_BOOTARGS		"root=/dev/nfs rw "			\
+				"nfsroot=10.0.0.2:/opt/eldk/ppc_8xx "	\
+				"nfsaddrs=10.0.0.99:10.0.0.2"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_IDE
+
+#undef CONFIG_CMD_SAVEENV
+#undef CONFIG_CMD_FLASH
+
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*----------------------------------------------------------------------*/
+#define CONFIG_ETHADDR		00:D0:93:00:01:CB
+#define CONFIG_IPADDR		10.0.0.98
+#define CONFIG_SERVERIP		10.0.0.1
+#undef	CONFIG_BOOTCOMMAND
+#define CONFIG_BOOTCOMMAND	"tftp 200000 uImage;bootm 200000"
+/*----------------------------------------------------------------------*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x00F00000	/* 1 ... 15MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address */
+
+#define CONFIG_SYS_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/
+
+#define CONFIG_SYS_PC_IDE_RESET	((ushort)0x0008)	/* PC 12	*/
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xFFF00000 /* was: 0xFF000000 */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFF000000
+#ifdef	DEBUG
+#define CONFIG_SYS_MONITOR_LEN		(512 << 10)	/* Reserve 512 kB for Monitor	*/
+#else
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#endif
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	0	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	0	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	0	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	0	/* Timeout for Flash Write (in ms)	*/
+
+#define	CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
+#define CONFIG_ENV_SIZE		0x0800	/* Total Size of Environment Sector	*/
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+/* 0x00000040 */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00 | SIUMCR_GB5E)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit, set PLL multiplication factor !
+ */
+/* 0x00b0c0c0 */
+#define CONFIG_SYS_PLPRCR							\
+		(	(11 << PLPRCR_MF_SHIFT) |			\
+			PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/ \
+			/*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |		\
+			PLPRCR_CSR   | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/	\
+		)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+/* 0x01800014 */
+#define CONFIG_SYS_SCCR	(SCCR_COM00	| /*SCCR_TBS|*/		\
+			 SCCR_RTDIV	|   SCCR_RTSEL	  |	\
+			 /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/	\
+			 SCCR_EBDF00	|   SCCR_DFSYNC00 |	\
+			 SCCR_DFBRG00	|   SCCR_DFNL000  |	\
+			 SCCR_DFNH000	|   SCCR_DFLCD101 |	\
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register
+ *-----------------------------------------------------------------------
+ */
+/* 0x00C3 */
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration Register
+ *-----------------------------------------------------------------------
+ */
+/* TIMEP=2 */
+#define CONFIG_SYS_RCCR 0x0200
+
+/*-----------------------------------------------------------------------
+ * RMDS - RISC Microcode Development Support Control Register
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RMDS 0
+
+/*-----------------------------------------------------------------------
+ * SDSR - SDMA Status Register
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_SDSR ((u_char)0x83)
+
+/*-----------------------------------------------------------------------
+ * SDMR - SDMA Mask Register
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_SDMR ((u_char)0x00)
+
+/*-----------------------------------------------------------------------
+ *
+ * Interrupt Levels
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_CPM_INTERRUPT	13	/* SIU_LEVEL6	*/
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_IDE_PREINIT	1	/* Use preinit IDE hook */
+#define CONFIG_IDE_INIT_POSTRESET	1	/* Use postreset IDE hook */
+#define CONFIG_IDE_8xx_DIRECT	1	/* PCMCIA interface required	*/
+#define CONFIG_IDE_LED		1	/* LED   for ide supported	*/
+#define CONFIG_IDE_RESET	1	/* reset for ide supported	*/
+
+#define CONFIG_SYS_IDE_MAXBUS		2	/* max. 2 IDE busses		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
+
+#define CONFIG_SYS_ATA_BASE_ADDR	0xFE100000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE1_OFFSET	0x0C00
+
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_REG_OFFSET	0x0080	/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100	/* Offset for alternate registers	*/
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_DER 0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0xFF000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0xFF080000	/* FLASH bank #1	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+/* EPROMs are 512kb */
+#define CONFIG_SYS_REMAP_OR_AM		0xFFF80000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xFFF80000	/* OR addr mask */
+
+/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
+#define CONFIG_SYS_OR_TIMING_FLASH	(/* OR_CSNT_SAM | */ OR_ACS_DIV4 | OR_BI | \
+				 OR_SCY_5_CLK | OR_EHTR)
+
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+/* 16 bit, bank valid */
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+
+#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+/* 16 bit, bank valid */
+#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+
+/*
+ * BR2-5 and OR2-5 (SRAM/SDRAM/PER8/SHARC)
+ *
+ */
+#define SRAM_BASE	0xFE200000	/* SRAM bank */
+#define SRAM_OR_AM	0xFFE00000	/* SRAM is 2 MB */
+
+#define SDRAM_BASE3_PRELIM	0x00000000	/* SDRAM bank */
+#define SDRAM_PRELIM_OR_AM	0xF8000000	/* map max. 128 MB */
+#define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB SDRAM */
+
+#define PER8_BASE	0xFE000000	/* PER8 bank */
+#define PER8_OR_AM	0xFFF00000	/* PER8 is 1 MB */
+
+#define SHARC_BASE	0xFE400000	/* SHARC bank */
+#define SHARC_OR_AM	0xFFC00000	/* SHARC is 4 MB */
+
+/* SRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+
+#define CONFIG_SYS_OR_TIMING_SRAM	0x00000D42	/* SRAM-Timing */
+#define CONFIG_SYS_OR2 (SRAM_OR_AM | CONFIG_SYS_OR_TIMING_SRAM )
+#define CONFIG_SYS_BR2 ((SRAM_BASE & BR_BA_MSK) | BR_PS_16 | BR_V )
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00	/* SDRAM-Timing */
+#define CONFIG_SYS_OR3_PRELIM	(SDRAM_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V )
+
+#define CONFIG_SYS_OR_TIMING_PER8	0x00000F32	/* PER8-Timing */
+#define CONFIG_SYS_OR4 (PER8_OR_AM | CONFIG_SYS_OR_TIMING_PER8 )
+#define CONFIG_SYS_BR4 ((PER8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
+
+#define CONFIG_SYS_OR_TIMING_SHARC	0x00000700	/* SHARC-Timing */
+#define CONFIG_SYS_OR5 (SHARC_OR_AM | CONFIG_SYS_OR_TIMING_SHARC )
+#define CONFIG_SYS_BR5 ((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V )
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CONFIG_SYS_MBMR_PTB	204
+
+/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MBMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CONFIG_SYS_MBMR_8COL	((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT)  | \
+			 MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 |	\
+			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/SXNI855T.h b/qemu/roms/u-boot/include/configs/SXNI855T.h
new file mode 100644
index 000000000..38940194f
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/SXNI855T.h
@@ -0,0 +1,378 @@
+/*
+ * U-Boot configuration for SIXNET SXNI855T CPU board.
+ * This board is based (loosely) on the Motorola FADS board, so this
+ * file is based (loosely) on config_FADS860T.h, see it for additional
+ * credits.
+ *
+ * Copyright (c) 2000-2002 Dave Ellis, SIXNET, dge@sixnetio.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Memory map:
+ *
+ *   ff100000 -> ff13ffff : FPGA        CS1
+ *   ff030000 -> ff03ffff : EXPANSION   CS7
+ *   ff020000 -> ff02ffff : DATA FLASH  CS4
+ *   ff018000 -> ff01ffff : UART B      CS6/UPMB
+ *   ff010000 -> ff017fff : UART A      CS5/UPMB
+ *   ff000000 -> ff00ffff : IMAP                   internal to the MPC855T
+ *   f8000000 -> fbffffff : FLASH       CS0        up to 64MB
+ *   f4000000 -> f7ffffff : NVSRAM      CS2        up to 64MB
+ *   00000000 -> 0fffffff : SDRAM       CS3/UPMA   up to 256MB
+ */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#include <mpc8xx_irq.h>
+
+#define CONFIG_SXNI855T		1	/* SIXNET IPm 855T CPU module */
+
+/* The 855T is just a stripped 860T and needs code for 860, so for now
+ * at least define 860, 860T and 855T
+ */
+#define CONFIG_MPC860		1
+#define CONFIG_MPC860T		1
+#define CONFIG_MPC855T		1
+
+#define	CONFIG_SYS_TEXT_BASE	0xF8000000
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_SCC1
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+
+#define MPC8XX_FACT		10	/* 50 MHz is 5 MHz in times 10	*/
+
+#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#define CONFIG_HAS_ETH1
+
+/*-----------------------------------------------------------------------
+ * Definitions for status LED
+ */
+#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+
+# define STATUS_LED_PAR		im_ioport.iop_papar
+# define STATUS_LED_DIR		im_ioport.iop_padir
+# define STATUS_LED_ODR		im_ioport.iop_paodr
+# define STATUS_LED_DAT		im_ioport.iop_padat
+
+# define STATUS_LED_BIT		0x8000		/* LED 0 is on PA.0 */
+# define STATUS_LED_PERIOD	((CONFIG_SYS_HZ / 2) / 5)	/* blink at 5 Hz */
+# define STATUS_LED_STATE	STATUS_LED_BLINKING
+
+# define STATUS_LED_ACTIVE	0		/* LED on for bit == 0	*/
+
+# define STATUS_LED_BOOT	0		/* LED 0 used for boot status */
+
+#ifdef DEV	/* development (debug) settings */
+#define CONFIG_BOOT_LED_STATE	STATUS_LED_OFF
+#else		/* production settings */
+#define CONFIG_BOOT_LED_STATE	STATUS_LED_ON
+#endif
+
+#define CONFIG_SHOW_BOOT_PROGRESS 1
+
+#define CONFIG_BOOTCOMMAND	"bootm f8040000 f8100000" /* autoboot command */
+#define CONFIG_BOOTARGS		"root=/dev/ram ip=off"
+
+#define CONFIG_MISC_INIT_R		/* have misc_init_r() function */
+#define CONFIG_BOARD_POSTCLK_INIT	/* have board_postclk_init() function */
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_RTC_DS1306		/* Dallas 1306 real time clock	*/
+
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED	50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PB_SCL		0x00000020	/* PB 26 */
+#define PB_SDA		0x00000010	/* PB 27 */
+
+#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
+#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
+#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
+#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
+#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
+#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
+
+# define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* Atmel 24C64			*/
+# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2	/* two byte address		*/
+
+#define	CONFIG_FEC_ENET		1	/* use FEC ethernet  */
+#define	CONFIG_MII		1
+
+#define CONFIG_SYS_DISCOVER_PHY
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_DATE
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_LONGHELP			/* undef to save a little memory */
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0100000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0400000	/* 1 ... 4 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x00100000
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xFF000000
+#define CONFIG_SYS_IMMR_SIZE		((uint)(64 * 1024))
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define	CONFIG_SYS_SRAM_BASE		0xF4000000
+#define	CONFIG_SYS_SRAM_SIZE		0x04000000	/* autosize up to 64Mbyte */
+
+#define CONFIG_SYS_FLASH_BASE		0xF8000000
+#define CONFIG_SYS_FLASH_SIZE		((uint)(8 * 1024 * 1024))	/* max 8Mbyte */
+
+#define CONFIG_SYS_DFLASH_BASE		0xff020000 /* DiskOnChip or NAND FLASH */
+#define CONFIG_SYS_DFLASH_SIZE		0x00010000
+
+#define CONFIG_SYS_FPGA_BASE		0xFF100000	/* Xilinx FPGA */
+#define CONFIG_SYS_FPGA_PROG		0xFF130000	/* Programming address */
+#define CONFIG_SYS_FPGA_SIZE		0x00040000	/* 256KiB usable */
+
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+/* Intel 28F640 has 135, 127 64K sectors in 8MB, + 8 more for 8K boot blocks.
+ * AMD 29LV641 has 128 64K sectors in 8MB
+ */
+#define CONFIG_SYS_MAX_FLASH_SECT	135	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control					11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration					11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control					11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register	15-30
+ *-----------------------------------------------------------------------
+ * set the PLL, the low-power modes and the reset control (15-29)
+ */
+#define CONFIG_SYS_PLPRCR	(((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) |	\
+				PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CONFIG_SYS_SCCR	(SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)
+
+ /*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_DER		0
+
+/* Because of the way the 860 starts up and assigns CS0 the
+ * entire address space, we have to set the memory controller
+ * differently.  Normally, you write the option register
+ * first, and then enable the chip select by writing the
+ * base register.  For CS0, you must write the base register
+ * first, followed by the option register.
+ */
+
+/*
+ * Init Memory Controller:
+ *
+ **********************************************************
+ * BR0 and OR0 (FLASH)
+ */
+
+#define CONFIG_SYS_PRELIM_OR0_AM	0xFC000000	/* OR addr mask */
+
+/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0	*/
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
+
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR0_AM | CONFIG_SYS_OR_TIMING_FLASH)
+
+#define CONFIG_FLASH_16BIT
+#define CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V )
+#define CONFIG_SYS_FLASH_PROTECTION	/* need to lock/unlock sectors in hardware */
+
+/**********************************************************
+ * BR1 and OR1 (FPGA)
+ * These preliminary values are also the final values.
+ */
+#define CONFIG_SYS_OR_TIMING_FPGA \
+	(OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_4_CLK | OR_EHTR | OR_TRLX)
+#define CONFIG_SYS_BR1_PRELIM	((CONFIG_SYS_FPGA_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
+#define CONFIG_SYS_OR1_PRELIM	(((-CONFIG_SYS_FPGA_SIZE) & OR_AM_MSK) | CONFIG_SYS_OR_TIMING_FPGA)
+
+/**********************************************************
+ * BR4 and OR4 (data flash)
+ * These preliminary values are also the final values.
+ */
+#define CONFIG_SYS_OR_TIMING_DFLASH \
+	(OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_2_CLK | OR_EHTR | OR_TRLX)
+#define CONFIG_SYS_BR4_PRELIM	((CONFIG_SYS_DFLASH_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
+#define CONFIG_SYS_OR4_PRELIM	(((-CONFIG_SYS_DFLASH_SIZE) & OR_AM_MSK) | CONFIG_SYS_OR_TIMING_DFLASH)
+
+/**********************************************************
+ * BR5/6 and OR5/6 (Dual UART)
+ */
+#define CONFIG_SYS_DUART_SIZE	0x8000	/* 32K window, only uses 8 bytes */
+#define CONFIG_SYS_DUARTA_BASE	0xff010000
+#define CONFIG_SYS_DUARTB_BASE	0xff018000
+
+#define DUART_MBMR	0
+#define DUART_OR_VALUE (ORMASK(CONFIG_SYS_DUART_SIZE) | OR_G5LS| OR_BI)
+#define DUART_BR_VALUE (BR_MS_UPMB | BR_PS_8 | BR_V)
+#define DUART_BR5_VALUE ((CONFIG_SYS_DUARTA_BASE & BR_BA_MSK ) | DUART_BR_VALUE)
+#define DUART_BR6_VALUE ((CONFIG_SYS_DUARTB_BASE & BR_BA_MSK ) | DUART_BR_VALUE)
+
+#define CONFIG_RESET_ON_PANIC		/* reset if system panic() */
+
+#define CONFIG_ENV_IS_IN_FLASH
+#ifdef CONFIG_ENV_IS_IN_FLASH
+  /* environment is in FLASH */
+  #define CONFIG_ENV_ADDR		0xF8040000	/* AM29LV641 or AM29LV800BT */
+  #define CONFIG_ENV_ADDR_REDUND	0xF8050000	/* AM29LV641 or AM29LV800BT */
+  #define CONFIG_ENV_SECT_SIZE	0x00010000
+  #define CONFIG_ENV_SIZE		0x00002000
+#else
+  /* environment is in EEPROM */
+  #define CONFIG_ENV_IS_IN_EEPROM		1
+  #define CONFIG_ENV_OFFSET		0	/* at beginning of EEPROM */
+  #define CONFIG_ENV_SIZE		     1024	/* Use only a part of it*/
+#endif
+
+#if 1
+#define CONFIG_AUTOBOOT_KEYED		/* use key strings to stop autoboot */
+#define CONFIG_AUTOBOOT_PROMPT		"autoboot in %d seconds\n", bootdelay
+#define CONFIG_AUTOBOOT_DELAY_STR	"delayabit"
+#define CONFIG_AUTOBOOT_STOP_STR	" " /* easy to stop for now */
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/Sandpoint8240.h b/qemu/roms/u-boot/include/configs/Sandpoint8240.h
new file mode 100644
index 000000000..2c0cb89af
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/Sandpoint8240.h
@@ -0,0 +1,398 @@
+/*
+ * (C) Copyright 2001-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC8240		1
+#define CONFIG_SANDPOINT	1
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
+#define CONFIG_SYS_LDSCRIPT	"board/sandpoint/u-boot.lds"
+
+#if 0
+#define USE_DINK32		1
+#else
+#undef USE_DINK32
+#endif
+
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		9600
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run net_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"net_self=tftp ${kernel_addr} ${bootfile};"			\
+		"tftp ${ramdisk_addr} ${ramdisk};"			\
+		"run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp ${kernel_addr} ${bootfile};"			\
+		"run nfsargs addip;bootm\0"				\
+	"rootpath=/opt/eldk/ppc_82xx\0"					\
+	"bootfile=/tftpboot/SP8240/uImage\0"				\
+	"ramdisk=/tftpboot/SP8240/uRamdisk\0"				\
+	"kernel_addr=200000\0"						\
+	"ramdisk_addr=400000\0"						\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_SNTP
+
+
+#define CONFIG_DRAM_SPEED	100		/* MHz				*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		1		/* undef to save memory		*/
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size	*/
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address		*/
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_PCI				/* include pci support		*/
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#undef CONFIG_PCI_PNP
+
+
+#define CONFIG_EEPRO100
+#define CONFIG_SYS_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
+
+#define PCI_ENET0_IOADDR	0x80000000
+#define PCI_ENET0_MEMADDR	0x80000000
+#define	PCI_ENET1_IOADDR	0x81000000
+#define	PCI_ENET1_MEMADDR	0x81000000
+
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_MAX_RAM_SIZE	0x10000000
+
+#define CONFIG_SYS_RESET_ADDRESS	0xFFF00100
+
+#if defined (USE_DINK32)
+#define CONFIG_SYS_MONITOR_LEN		0x00030000
+#define CONFIG_SYS_MONITOR_BASE	0x00090000
+#define CONFIG_SYS_RAMBOOT		1
+#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x10000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+#else
+#undef	CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_MONITOR_LEN		0x00030000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+
+
+#define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE      0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+#endif
+
+#define CONFIG_SYS_FLASH_BASE		0xFFF00000
+#if 0
+#define CONFIG_SYS_FLASH_SIZE		(512 * 1024)	/* sandpoint has tiny eeprom	*/
+#else
+#define CONFIG_SYS_FLASH_SIZE		(1024 * 1024)	/* Unity has onboard 1MByte flash */
+#endif
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_OFFSET		0x00004000	/* Offset of Environment Sector */
+#define CONFIG_ENV_SIZE		0x00002000	/* Total Size of Environment Sector */
+
+#define CONFIG_SYS_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END		0x04000000	/* 0 ... 32 MB in DRAM		*/
+
+#define CONFIG_SYS_EUMB_ADDR		0xFC000000
+
+#define CONFIG_SYS_ISA_MEM		0xFD000000
+#define CONFIG_SYS_ISA_IO		0xFE000000
+
+#define CONFIG_SYS_FLASH_RANGE_BASE	0xFF000000	/* flash memory address range	*/
+#define CONFIG_SYS_FLASH_RANGE_SIZE	0x01000000
+#define FLASH_BASE0_PRELIM	0xFFF00000	/* sandpoint flash		*/
+#define FLASH_BASE1_PRELIM	0xFF000000	/* PMC onboard flash		*/
+
+/*
+ * select i2c support configuration
+ *
+ * Supported configurations are {none, software, hardware} drivers.
+ * If the software driver is chosen, there are some additional
+ * configuration items that the driver uses to drive the port pins.
+ */
+#define CONFIG_HARD_I2C		1		/* To enable I2C support */
+#undef  CONFIG_SYS_I2C_SOFT
+#define CONFIG_SYS_I2C_SLAVE	0x7F
+#define CONFIG_SYS_I2C_SPEED	400000
+
+#ifdef CONFIG_SYS_I2C_SOFT
+#error "Soft I2C is not configured properly.  Please review!"
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT_SPEED	50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
+#define I2C_PORT		3               /* Port A=0, B=1, C=2, D=3 */
+#define I2C_ACTIVE		(iop->pdir |=  0x00010000)
+#define I2C_TRISTATE		(iop->pdir &= ~0x00010000)
+#define I2C_READ		((iop->pdat & 0x00010000) != 0)
+#define I2C_SDA(bit)		if(bit) iop->pdat |=  0x00010000; \
+				else    iop->pdat &= ~0x00010000
+#define I2C_SCL(bit)		if(bit) iop->pdat |=  0x00020000; \
+				else    iop->pdat &= ~0x00020000
+#define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
+#endif /* CONFIG_SYS_I2C_SOFT */
+
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57		/* EEPROM IS24C02		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1		/* Bytes of address		*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3	/* write page size		*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* takes up to 10 msec		*/
+
+
+#define CONFIG_SYS_FLASH_BANKS		{ FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM }
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+
+
+/* #define CONFIG_WINBOND_83C553	1	/ *has a winbond bridge			*/
+#define CONFIG_SYS_USE_WINBOND_IDE	0	/*use winbond 83c553 internal IDE ctrlr */
+#define CONFIG_SYS_WINBOND_ISA_CFG_ADDR    0x80005800	/*pci-isa bridge config addr	*/
+#define CONFIG_SYS_WINBOND_IDE_CFG_ADDR    0x80005900	/*ide config addr		*/
+
+#define CONFIG_SYS_IDE_MAXBUS		2   /* max. 2 IDE busses	*/
+#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
+
+/*
+ * NS87308 Configuration
+ */
+#define CONFIG_NS87308			/* Nat Semi super-io controller on ISA bus */
+
+#define CONFIG_SYS_NS87308_BADDR_10	1
+
+#define CONFIG_SYS_NS87308_DEVS	( CONFIG_SYS_NS87308_UART1   | \
+				  CONFIG_SYS_NS87308_UART2   | \
+				  CONFIG_SYS_NS87308_POWRMAN | \
+				  CONFIG_SYS_NS87308_RTC_APC )
+
+#undef  CONFIG_SYS_NS87308_PS2MOD
+
+#define CONFIG_SYS_NS87308_CS0_BASE	0x0076
+#define CONFIG_SYS_NS87308_CS0_CONF	0x30
+#define CONFIG_SYS_NS87308_CS1_BASE	0x0075
+#define CONFIG_SYS_NS87308_CS1_CONF	0x30
+#define CONFIG_SYS_NS87308_CS2_BASE	0x0074
+#define CONFIG_SYS_NS87308_CS2_CONF	0x30
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+
+#define CONFIG_SYS_NS16550_CLK		1843200
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART1_BASE)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART2_BASE)
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+#define CONFIG_SYS_CLK_FREQ  33000000	/* external frequency to pll */
+#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER  1
+
+#define CONFIG_SYS_ROMNAL		7	/*rom/flash next access time		*/
+#define CONFIG_SYS_ROMFAL		11	/*rom/flash access time			*/
+
+#define CONFIG_SYS_REFINT	430	/* no of clock cycles between CBR refresh cycles */
+
+/* the following are for SDRAM only*/
+#define CONFIG_SYS_BSTOPRE	121	/* Burst To Precharge, sets open page interval */
+#define CONFIG_SYS_REFREC		8	/* Refresh to activate interval		*/
+#define CONFIG_SYS_RDLAT		4	/* data latency from read command	*/
+#define CONFIG_SYS_PRETOACT		3	/* Precharge to activate interval	*/
+#define CONFIG_SYS_ACTTOPRE		5	/* Activate to Precharge interval	*/
+#define CONFIG_SYS_ACTORW		3	/* Activate to R/W			*/
+#define CONFIG_SYS_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
+#define CONFIG_SYS_SDMODE_WRAP		0	/* SDMODE wrap type			*/
+#define CONFIG_SYS_SDMODE_BURSTLEN	2	/* SDMODE Burst length 2=4, 3=8		*/
+
+#define CONFIG_SYS_REGISTERD_TYPE_BUFFER   1
+
+/* memory bank settings*/
+/*
+ * only bits 20-29 are actually used from these vales to set the
+ * start/end address the upper two bits will be 0, and the lower 20
+ * bits will be set to 0x00000 for a start address, or 0xfffff for an
+ * end address
+ */
+#define CONFIG_SYS_BANK0_START		0x00000000
+#define CONFIG_SYS_BANK0_END		(CONFIG_SYS_MAX_RAM_SIZE - 1)
+#define CONFIG_SYS_BANK0_ENABLE	1
+#define CONFIG_SYS_BANK1_START		0x3ff00000
+#define CONFIG_SYS_BANK1_END		0x3fffffff
+#define CONFIG_SYS_BANK1_ENABLE	0
+#define CONFIG_SYS_BANK2_START		0x3ff00000
+#define CONFIG_SYS_BANK2_END		0x3fffffff
+#define CONFIG_SYS_BANK2_ENABLE	0
+#define CONFIG_SYS_BANK3_START		0x3ff00000
+#define CONFIG_SYS_BANK3_END		0x3fffffff
+#define CONFIG_SYS_BANK3_ENABLE	0
+#define CONFIG_SYS_BANK4_START		0x00000000
+#define CONFIG_SYS_BANK4_END		0x00000000
+#define CONFIG_SYS_BANK4_ENABLE	0
+#define CONFIG_SYS_BANK5_START		0x00000000
+#define CONFIG_SYS_BANK5_END		0x00000000
+#define CONFIG_SYS_BANK5_ENABLE	0
+#define CONFIG_SYS_BANK6_START		0x00000000
+#define CONFIG_SYS_BANK6_END		0x00000000
+#define CONFIG_SYS_BANK6_ENABLE	0
+#define CONFIG_SYS_BANK7_START		0x00000000
+#define CONFIG_SYS_BANK7_END		0x00000000
+#define CONFIG_SYS_BANK7_ENABLE	0
+/*
+ * Memory bank enable bitmask, specifying which of the banks defined above
+ are actually present. MSB is for bank #7, LSB is for bank #0.
+ */
+#define CONFIG_SYS_BANK_ENABLE		0x01
+
+#define CONFIG_SYS_ODCR		0xff	/* configures line driver impedances,	*/
+					/* see 8240 book for bit definitions	*/
+#define CONFIG_SYS_PGMAX		0x32	/* how long the 8240 retains the	*/
+					/* currently accessed page in memory	*/
+					/* see 8240 book for details		*/
+
+/* SDRAM 0 - 256MB */
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* stack in DCACHE @ 1GB (no backing mem) */
+#if defined(USE_DINK32)
+#define CONFIG_SYS_IBAT1L	(0x40000000 | BATL_PP_00 )
+#define CONFIG_SYS_IBAT1U	(0x40000000 | BATU_BL_128K )
+#else
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#endif
+
+/* PCI memory */
+#define CONFIG_SYS_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* Flash, config addrs, etc */
+#define CONFIG_SYS_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	20	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8240 CPU			*/
+#if defined(CONFIG_CMD_KGDB)
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/* values according to the manual */
+
+#define CONFIG_DRAM_50MHZ	1
+#define CONFIG_SDRAM_50MHZ
+
+#undef	NR_8259_INTS
+#define NR_8259_INTS		1
+
+
+#define CONFIG_DISK_SPINUP_TIME 1000000
+
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/Sandpoint8245.h b/qemu/roms/u-boot/include/configs/Sandpoint8245.h
new file mode 100644
index 000000000..2664d5b16
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/Sandpoint8245.h
@@ -0,0 +1,376 @@
+/*
+ * (C) Copyright 2001-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC8245		1
+#define CONFIG_SANDPOINT	1
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
+#define CONFIG_SYS_LDSCRIPT	"board/sandpoint/u-boot.lds"
+
+#if 0
+#define USE_DINK32		1
+#else
+#undef USE_DINK32
+#endif
+
+#define CONFIG_CONS_INDEX     3               /* set to '3' for on-chip DUART */
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_DRAM_SPEED	100		/* MHz				*/
+
+#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_SNTP
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		1		/* undef to save memory		*/
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size	*/
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address		*/
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_PCI				/* include pci support		*/
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#undef CONFIG_PCI_PNP
+
+
+#define CONFIG_EEPRO100
+#define CONFIG_SYS_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
+#define CONFIG_NATSEMI
+#define CONFIG_NS8382X
+
+#define PCI_ENET0_IOADDR	0x80000000
+#define PCI_ENET0_MEMADDR	0x80000000
+#define	PCI_ENET1_IOADDR	0x81000000
+#define	PCI_ENET1_MEMADDR	0x81000000
+
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_MAX_RAM_SIZE	0x10000000
+
+#define CONFIG_SYS_RESET_ADDRESS	0xFFF00100
+
+#if defined (USE_DINK32)
+#define CONFIG_SYS_MONITOR_LEN		0x00030000
+#define CONFIG_SYS_MONITOR_BASE	0x00090000
+#define CONFIG_SYS_RAMBOOT		1
+#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x10000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+#else
+#undef	CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_MONITOR_LEN		0x00030000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+
+
+#define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE      0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+#endif
+
+#define CONFIG_SYS_FLASH_BASE		0xFFF00000
+#if 0
+#define CONFIG_SYS_FLASH_SIZE		(512 * 1024)	/* sandpoint has tiny eeprom	*/
+#else
+#define CONFIG_SYS_FLASH_SIZE		(1024 * 1024)	/* Unity has onboard 1MByte flash */
+#endif
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_OFFSET		0x00004000	/* Offset of Environment Sector */
+#define CONFIG_ENV_SIZE		0x00002000	/* Total Size of Environment Sector */
+
+#define CONFIG_SYS_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END		0x04000000	/* 0 ... 32 MB in DRAM		*/
+
+#define CONFIG_SYS_EUMB_ADDR		0xFC000000
+
+#define CONFIG_SYS_ISA_MEM		0xFD000000
+#define CONFIG_SYS_ISA_IO		0xFE000000
+
+#define CONFIG_SYS_FLASH_RANGE_BASE	0xFF000000	/* flash memory address range	*/
+#define CONFIG_SYS_FLASH_RANGE_SIZE	0x01000000
+#define FLASH_BASE0_PRELIM	0xFFF00000	/* sandpoint flash		*/
+#define FLASH_BASE1_PRELIM	0xFF000000	/* PMC onboard flash		*/
+
+/*
+ * select i2c support configuration
+ *
+ * Supported configurations are {none, software, hardware} drivers.
+ * If the software driver is chosen, there are some additional
+ * configuration items that the driver uses to drive the port pins.
+ */
+#define CONFIG_HARD_I2C		1		/* To enable I2C support */
+#undef  CONFIG_SYS_I2C_SOFT
+#define CONFIG_SYS_I2C_SPEED	400000
+#define CONFIG_SYS_I2C_SLAVE	0x7F
+
+#ifdef CONFIG_SYS_I2C_SOFT
+#error "Soft I2C is not configured properly.  Please review!"
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT_SPEED	50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
+#define I2C_PORT		3               /* Port A=0, B=1, C=2, D=3 */
+#define I2C_ACTIVE		(iop->pdir |=  0x00010000)
+#define I2C_TRISTATE		(iop->pdir &= ~0x00010000)
+#define I2C_READ		((iop->pdat & 0x00010000) != 0)
+#define I2C_SDA(bit)		if(bit) iop->pdat |=  0x00010000; \
+				else    iop->pdat &= ~0x00010000
+#define I2C_SCL(bit)		if(bit) iop->pdat |=  0x00020000; \
+				else    iop->pdat &= ~0x00020000
+#define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
+#endif /* CONFIG_SYS_I2C_SOFT */
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57		/* EEPROM IS24C02		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1		/* Bytes of address		*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+
+#define CONFIG_SYS_FLASH_BANKS		{ FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM }
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+
+
+/* #define CONFIG_WINBOND_83C553	1	/ *has a winbond bridge			*/
+#define CONFIG_SYS_USE_WINBOND_IDE	0	/*use winbond 83c553 internal IDE ctrlr */
+#define CONFIG_SYS_WINBOND_ISA_CFG_ADDR    0x80005800	/*pci-isa bridge config addr	*/
+#define CONFIG_SYS_WINBOND_IDE_CFG_ADDR    0x80005900	/*ide config addr		*/
+
+#define CONFIG_SYS_IDE_MAXBUS		2   /* max. 2 IDE busses	*/
+#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
+
+/*
+ * NS87308 Configuration
+ */
+#define CONFIG_NS87308			/* Nat Semi super-io controller on ISA bus */
+
+#define CONFIG_SYS_NS87308_BADDR_10	1
+
+#define CONFIG_SYS_NS87308_DEVS	( CONFIG_SYS_NS87308_UART1   | \
+				  CONFIG_SYS_NS87308_UART2   | \
+				  CONFIG_SYS_NS87308_POWRMAN | \
+				  CONFIG_SYS_NS87308_RTC_APC )
+
+#undef  CONFIG_SYS_NS87308_PS2MOD
+
+#define CONFIG_SYS_NS87308_CS0_BASE	0x0076
+#define CONFIG_SYS_NS87308_CS0_CONF	0x30
+#define CONFIG_SYS_NS87308_CS1_BASE	0x0075
+#define CONFIG_SYS_NS87308_CS1_CONF	0x30
+#define CONFIG_SYS_NS87308_CS2_BASE	0x0074
+#define CONFIG_SYS_NS87308_CS2_CONF	0x30
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+
+#if (CONFIG_CONS_INDEX > 2)
+#define CONFIG_SYS_NS16550_CLK         CONFIG_DRAM_SPEED*1000000
+#else
+#define CONFIG_SYS_NS16550_CLK         1843200
+#endif
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART1_BASE)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART2_BASE)
+#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_EUMB_ADDR + 0x4500)
+#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_EUMB_ADDR + 0x4600)
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+#define CONFIG_SYS_CLK_FREQ  33333333	/* external frequency to pll */
+
+#define CONFIG_SYS_ROMNAL		7	/*rom/flash next access time		*/
+#define CONFIG_SYS_ROMFAL		11	/*rom/flash access time			*/
+
+#define CONFIG_SYS_REFINT	430	/* no of clock cycles between CBR refresh cycles */
+
+/* the following are for SDRAM only*/
+#define CONFIG_SYS_BSTOPRE	121	/* Burst To Precharge, sets open page interval */
+#define CONFIG_SYS_REFREC		8	/* Refresh to activate interval		*/
+#define CONFIG_SYS_RDLAT		4	/* data latency from read command	*/
+#define CONFIG_SYS_PRETOACT		3	/* Precharge to activate interval	*/
+#define CONFIG_SYS_ACTTOPRE		5	/* Activate to Precharge interval	*/
+#define CONFIG_SYS_ACTORW		3	/* Activate to R/W			*/
+#define CONFIG_SYS_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
+#define CONFIG_SYS_SDMODE_WRAP		0	/* SDMODE wrap type			*/
+#if 0
+#define CONFIG_SYS_SDMODE_BURSTLEN	2	/* OBSOLETE!  SDMODE Burst length 2=4, 3=8		*/
+#endif
+
+#define CONFIG_SYS_REGISTERD_TYPE_BUFFER   1
+#define CONFIG_SYS_EXTROM 1
+#define CONFIG_SYS_REGDIMM 0
+
+
+/* memory bank settings*/
+/*
+ * only bits 20-29 are actually used from these vales to set the
+ * start/end address the upper two bits will be 0, and the lower 20
+ * bits will be set to 0x00000 for a start address, or 0xfffff for an
+ * end address
+ */
+#define CONFIG_SYS_BANK0_START		0x00000000
+#define CONFIG_SYS_BANK0_END		(CONFIG_SYS_MAX_RAM_SIZE - 1)
+#define CONFIG_SYS_BANK0_ENABLE	1
+#define CONFIG_SYS_BANK1_START		0x3ff00000
+#define CONFIG_SYS_BANK1_END		0x3fffffff
+#define CONFIG_SYS_BANK1_ENABLE	0
+#define CONFIG_SYS_BANK2_START		0x3ff00000
+#define CONFIG_SYS_BANK2_END		0x3fffffff
+#define CONFIG_SYS_BANK2_ENABLE	0
+#define CONFIG_SYS_BANK3_START		0x3ff00000
+#define CONFIG_SYS_BANK3_END		0x3fffffff
+#define CONFIG_SYS_BANK3_ENABLE	0
+#define CONFIG_SYS_BANK4_START		0x00000000
+#define CONFIG_SYS_BANK4_END		0x00000000
+#define CONFIG_SYS_BANK4_ENABLE	0
+#define CONFIG_SYS_BANK5_START		0x00000000
+#define CONFIG_SYS_BANK5_END		0x00000000
+#define CONFIG_SYS_BANK5_ENABLE	0
+#define CONFIG_SYS_BANK6_START		0x00000000
+#define CONFIG_SYS_BANK6_END		0x00000000
+#define CONFIG_SYS_BANK6_ENABLE	0
+#define CONFIG_SYS_BANK7_START		0x00000000
+#define CONFIG_SYS_BANK7_END		0x00000000
+#define CONFIG_SYS_BANK7_ENABLE	0
+/*
+ * Memory bank enable bitmask, specifying which of the banks defined above
+ are actually present. MSB is for bank #7, LSB is for bank #0.
+ */
+#define CONFIG_SYS_BANK_ENABLE		0x01
+
+#define CONFIG_SYS_ODCR		0xff	/* configures line driver impedances,	*/
+					/* see 8240 book for bit definitions	*/
+#define CONFIG_SYS_PGMAX		0x32	/* how long the 8240 retains the	*/
+					/* currently accessed page in memory	*/
+					/* see 8240 book for details		*/
+
+/* SDRAM 0 - 256MB */
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* stack in DCACHE @ 1GB (no backing mem) */
+#if defined(USE_DINK32)
+#define CONFIG_SYS_IBAT1L	(0x40000000 | BATL_PP_00 )
+#define CONFIG_SYS_IBAT1U	(0x40000000 | BATU_BL_128K )
+#else
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#endif
+
+/* PCI memory */
+#define CONFIG_SYS_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* Flash, config addrs, etc */
+#define CONFIG_SYS_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	20	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8240 CPU			*/
+#if defined(CONFIG_CMD_KGDB)
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/* values according to the manual */
+
+#define CONFIG_DRAM_50MHZ	1
+#define CONFIG_SDRAM_50MHZ
+
+#undef	NR_8259_INTS
+#define NR_8259_INTS		1
+
+
+#define CONFIG_DISK_SPINUP_TIME 1000000
+
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/T1040QDS.h b/qemu/roms/u-boot/include/configs/T1040QDS.h
new file mode 100644
index 000000000..522653bdc
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/T1040QDS.h
@@ -0,0 +1,811 @@
+/*
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * T1040 QDS board configuration file
+ */
+#define CONFIG_T1040QDS
+#define CONFIG_PHYS_64BIT
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE
+#define CONFIG_E500			/* BOOKE e500 family */
+#define CONFIG_E500MC			/* BOOKE e500mc family */
+#define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
+#define CONFIG_MP			/* support multiple processors */
+
+/* support deep sleep */
+#define CONFIG_DEEP_SLEEP
+#define CONFIG_SILENT_CONSOLE
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xeff40000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+#define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC		CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_FSL_IFC			/* Enable IFC Support */
+#define CONFIG_PCI			/* Enable PCI/PCIE */
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_PCIE1			/* PCIE controler 1 */
+#define CONFIG_PCIE2			/* PCIE controler 2 */
+#define CONFIG_PCIE3			/* PCIE controler 3 */
+#define CONFIG_PCIE4			/* PCIE controler 4 */
+
+#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
+
+#define CONFIG_FSL_LAW			/* Use common FSL init code */
+
+#define CONFIG_ENV_OVERWRITE
+
+#ifdef CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_IS_NOWHERE
+#else
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#endif
+
+#ifndef CONFIG_SYS_NO_FLASH
+#if defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS              0
+#define CONFIG_ENV_SPI_CS               0
+#define CONFIG_ENV_SPI_MAX_HZ           10000000
+#define CONFIG_ENV_SPI_MODE             0
+#define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
+#define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
+#define CONFIG_ENV_SECT_SIZE            0x10000
+#elif defined(CONFIG_SDCARD)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV          0
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_OFFSET		(512 * 1658)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE			CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET		(7 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+#endif
+#else /* CONFIG_SYS_NO_FLASH */
+#define CONFIG_ENV_SIZE                0x2000
+#define CONFIG_ENV_SECT_SIZE   0x20000 /* 128K (one sector) */
+#endif
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk() /* sysclk for MPC85xx */
+#define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk()
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BACKSIDE_L2_CACHE
+#define CONFIG_SYS_INIT_L2CSR0		L2CSR0_L2E
+#define CONFIG_BTB			/* toggle branch predition */
+#define CONFIG_DDR_ECC
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#endif
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP		64	/* number of TLB1 entries */
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_PANIC_HANG	/* do not reset board on panic */
+
+/*
+ *  Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
+
+#define CONFIG_SYS_DCSRBAR		0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM	0
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+#define CONFIG_DDR_SPD
+#ifndef CONFIG_SYS_FSL_DDR4
+#define CONFIG_SYS_FSL_DDR3
+#define CONFIG_FSL_DDR_INTERACTIVE
+#endif
+
+#define CONFIG_SYS_SPD_BUS_NUM	0
+#define SPD_EEPROM_ADDRESS	0x51
+
+#define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE	0xe0000000
+#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+
+#define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+				+ 0x8000000) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR1_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
+				FTIM0_NOR_TEADC(0x5) | \
+				FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
+				FTIM1_NOR_TRAD_NOR(0x1A) |\
+				FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
+				FTIM2_NOR_TCH(0x4) | \
+				FTIM2_NOR_TWPH(0x0E) | \
+				FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3	0x0
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS \
+					+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
+#define CONFIG_FSL_QIXIS	/* use common QIXIS code */
+#define QIXIS_BASE		0xffdf0000
+#define QIXIS_BASE_PHYS		(0xf00000000ull | QIXIS_BASE)
+#define QIXIS_LBMAP_SWITCH		0x06
+#define QIXIS_LBMAP_MASK		0x0f
+#define QIXIS_LBMAP_SHIFT		0
+#define QIXIS_LBMAP_DFLTBANK		0x00
+#define QIXIS_LBMAP_ALTBANK		0x04
+#define QIXIS_RST_CTL_RESET		0x31
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+#define	QIXIS_RST_FORCE_MEM		0x01
+
+#define CONFIG_SYS_CSPR3_EXT	(0xf)
+#define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 \
+				| CSPR_MSEL_GPCM \
+				| CSPR_V)
+#define CONFIG_SYS_AMASK3	IFC_AMASK(4*1024)
+#define CONFIG_SYS_CSOR3	0x0
+/* QIXIS Timing parameters for IFC CS3 */
+#define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
+					FTIM0_GPCM_TEADC(0x0e) | \
+					FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
+					FTIM1_GPCM_TRAD(0x3f))
+#define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
+					FTIM2_GPCM_TCH(0x8) | \
+					FTIM2_GPCM_TWP(0x1f))
+#define CONFIG_SYS_CS3_FTIM3		0x0
+
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_BASE		0xff800000
+#define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
+
+#define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+
+#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
+				| CSOR_NAND_RAL_3	/* RAL = 3Byes */ \
+				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
+				| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
+				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+					FTIM0_NAND_TWP(0x18)   | \
+					FTIM0_NAND_TWCHT(0x07) | \
+					FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+					FTIM1_NAND_TWBE(0x39)  | \
+					FTIM1_NAND_TRR(0x0e)   | \
+					FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
+					FTIM2_NAND_TREH(0x0a) | \
+					FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3		0x0
+
+#define CONFIG_SYS_NAND_DDR_LAW		11
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
+#endif
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe0ec000
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
+#define CONFIG_SERIAL_MULTI		/* Enable both serial ports */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	/* determine from environment */
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* Video */
+#define CONFIG_FSL_DIU_FB
+#ifdef CONFIG_FSL_DIU_FB
+#define CONFIG_SYS_DIU_ADDR	(CONFIG_SYS_CCSRBAR + 0x180000)
+#define CONFIG_VIDEO
+#define CONFIG_CMD_BMP
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+/*
+ * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
+ * disable empty flash sector detection, which is I/O-intensive.
+ */
+#undef CONFIG_SYS_FLASH_EMPTY_INFO
+#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL		/* Use FSL common I2C driver */
+#define CONFIG_SYS_FSL_I2C_SPEED	50000	/* I2C speed in Hz */
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_SPEED	50000	/* I2C speed in Hz */
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x119000
+
+#define I2C_MUX_PCA_ADDR		0x77
+#define I2C_MUX_PCA_ADDR_PRI		0x77 /* Primary Mux*/
+
+
+/* I2C bus multiplexer */
+#define I2C_MUX_CH_DEFAULT      0x8
+#define I2C_MUX_CH_DIU		0xC
+
+/* LDI/DVI Encoder for display */
+#define CONFIG_SYS_I2C_LDI_ADDR         0x38
+#define CONFIG_SYS_I2C_DVI_ADDR         0x75
+
+/*
+ * RTC configuration
+ */
+#define RTC
+#define CONFIG_RTC_DS3231               1
+#define CONFIG_SYS_I2C_RTC_ADDR         0x68
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#define CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_SPI_FLASH_EON
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED         10000000
+#define CONFIG_SF_DEFAULT_MODE          0
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+#ifdef CONFIG_PCI
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#ifdef CONFIG_PCIE1
+#define	CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#define	CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define	CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+#endif
+
+/* controller 2, Slot 2, tgtid 2, Base address 201000 */
+#ifdef CONFIG_PCIE2
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0x90000000
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc10000000ull
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+#endif
+
+/* controller 3, Slot 1, tgtid 1, Base address 202000 */
+#ifdef CONFIG_PCIE3
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc20000000ull
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
+#endif
+
+/* controller 4, Base address 203000 */
+#ifdef CONFIG_PCIE4
+#define CONFIG_SYS_PCIE4_MEM_VIRT	0xb0000000
+#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_PHYS	0xc30000000ull
+#define CONFIG_SYS_PCIE4_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE4_IO_VIRT	0xf8030000
+#define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
+#define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
+#endif
+
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+#define CONFIG_E1000
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif	/* CONFIG_PCI */
+
+/* SATA */
+#define CONFIG_FSL_SATA_V2
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
+
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+/*
+* USB
+*/
+#define CONFIG_HAS_FSL_DR_USB
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+#define CONFIG_USB_EHCI
+
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_CMD_EXT2
+#endif
+#endif
+
+#define CONFIG_MMC
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* Qman/Bman */
+#ifndef CONFIG_NOBQFMAN
+#define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS	25
+#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
+#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
+#define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
+#define CONFIG_SYS_QMAN_NUM_PORTALS	25
+#define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
+#define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
+#define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+
+#define CONFIG_QE
+#define CONFIG_U_QE
+/* Default address of microcode for the Linux Fman driver */
+#if defined(CONFIG_SPIFLASH)
+/*
+ * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
+ * env, so we got 0x110000.
+ */
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_FMAN_FW_ADDR	0x110000
+#elif defined(CONFIG_SDCARD)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 825KB (1650 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+#define CONFIG_SYS_FMAN_FW_ADDR	(512 * 1680)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_FMAN_FW_ADDR	(8 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#else
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_FMAN_FW_ADDR		0xEFF00000
+#define CONFIG_SYS_QE_FW_ADDR		0xEFF10000
+#endif
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+#endif /* CONFIG_NOBQFMAN */
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_REALTEK
+#define CONFIG_PHY_TERANETICS
+#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
+#define SGMII_CARD_PORT2_PHY_ADDR 0x10
+#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
+#define SGMII_CARD_PORT4_PHY_ADDR 0x11
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR	0x01
+#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR	0x02
+
+#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
+#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
+#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
+#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
+
+#define CONFIG_MII		/* MII PHY management */
+#define CONFIG_ETHPRIME		"FM1@DTSEC1"
+#define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
+#endif
+
+/*
+ * Dynamic MTD Partition support with mtdparts
+ */
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_FLASH_CFI_MTD
+#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
+			"spi0=spife110000.0"
+#define MTDPARTS_DEFAULT	"mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
+				"128k(dtb),96m(fs),-(user);"\
+				"fff800000.flash:2m(uboot),9m(kernel),"\
+				"128k(dtb),96m(fs),-(user);spife110000.0:" \
+				"2m(uboot),9m(kernel),128k(dtb),-(user)"
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ERRATA
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SETEXPR
+
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	"u-boot.bin"	/* U-Boot image on TFTP server*/
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+#define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
+
+#define CONFIG_BAUDRATE	115200
+
+#define __USB_PHY_TYPE	utmi
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hwconfig=fsl_ddr:ctlr_intlv=cacheline,"		\
+	"bank_intlv=cs0_cs1;"					\
+	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
+	"netdev=eth0\0"						\
+	"video-mode=fslfb:1024x768-32@60,monitor=dvi\0"		\
+	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
+	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
+	"tftpflash=tftpboot $loadaddr $uboot && "		\
+	"protect off $ubootaddr +$filesize && "			\
+	"erase $ubootaddr +$filesize && "			\
+	"cp.b $loadaddr $ubootaddr $filesize && "		\
+	"protect on $ubootaddr +$filesize && "			\
+	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
+	"consoledev=ttyS0\0"					\
+	"ramdiskaddr=2000000\0"					\
+	"ramdiskfile=t1040qds/ramdisk.uboot\0"			\
+	"fdtaddr=c00000\0"					\
+	"fdtfile=t1040qds/t1040qds.dtb\0"			\
+	"bdev=sda3\0"						\
+	"c=ffe\0"
+
+#define CONFIG_LINUX                       \
+	"setenv bootargs root=/dev/ram rw "            \
+	"console=$consoledev,$baudrate $othbootargs;"  \
+	"setenv ramdiskaddr 0x02000000;"               \
+	"setenv fdtaddr 0x00c00000;"		       \
+	"setenv loadaddr 0x1000000;"		       \
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_HDBOOT					\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND			\
+	"setenv bootargs root=/dev/nfs rw "	\
+	"nfsroot=$serverip:$rootpath "		\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"		\
+	"tftp $fdtaddr $fdtfile;"		\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND				\
+	"setenv bootargs root=/dev/ram rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $ramdiskaddr $ramdiskfile;"		\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_LINUX
+
+#ifdef CONFIG_SECURE_BOOT
+#include <asm/fsl_secure_boot.h>
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/T104xRDB.h b/qemu/roms/u-boot/include/configs/T104xRDB.h
new file mode 100644
index 000000000..81b4f31bc
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/T104xRDB.h
@@ -0,0 +1,823 @@
+/*
++ * Copyright 2014 Freescale Semiconductor, Inc.
++ *
++ * SPDX-License-Identifier:     GPL-2.0+
++ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * T104x RDB board configuration file
+ */
+#define CONFIG_T104xRDB
+#define CONFIG_PHYS_64BIT
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg
+#ifdef CONFIG_T1040RDB
+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1040_rcw.cfg
+#endif
+#ifdef CONFIG_T1042RDB_PI
+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_rcw.cfg
+#endif
+
+#define CONFIG_SPL
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_FSL_LAW                 /* Use common FSL init code */
+#define CONFIG_SYS_TEXT_BASE		0x00201000
+#define CONFIG_SPL_TEXT_BASE		0xFFFD8000
+#define CONFIG_SPL_PAD_TO		0x40000
+#define CONFIG_SPL_MAX_SIZE		0x28000
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_SKIP_RELOCATE
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#define CONFIG_SYS_NO_FLASH
+#endif
+#define RESET_VECTOR_OFFSET		0x27FFC
+#define BOOT_PAGE_OFFSET		0x27000
+
+#ifdef CONFIG_NAND
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(256 << 10)
+#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#define CONFIG_SPL_NAND_BOOT
+#endif
+
+#ifdef CONFIG_SPIFLASH
+#define	CONFIG_RESET_VECTOR_ADDRESS		0x200FFC
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_MINIMAL
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE	(768 << 10)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST		(0x00200000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_START	(0x00200000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS	(256 << 10)
+#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#ifndef CONFIG_SPL_BUILD
+#define	CONFIG_SYS_MPC85XX_NO_RESETVEC
+#endif
+#define CONFIG_SPL_SPI_BOOT
+#endif
+
+#ifdef CONFIG_SDCARD
+#define	CONFIG_RESET_VECTOR_ADDRESS		0x200FFC
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_MMC_MINIMAL
+#define CONFIG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_DST	(0x00200000)
+#define CONFIG_SYS_MMC_U_BOOT_START	(0x00200000)
+#define CONFIG_SYS_MMC_U_BOOT_OFFS	(260 << 10)
+#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#ifndef CONFIG_SPL_BUILD
+#define	CONFIG_SYS_MPC85XX_NO_RESETVEC
+#endif
+#define CONFIG_SPL_MMC_BOOT
+#endif
+
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE
+#define CONFIG_E500			/* BOOKE e500 family */
+#define CONFIG_E500MC			/* BOOKE e500mc family */
+#define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
+#define CONFIG_MP			/* support multiple processors */
+
+/* support deep sleep */
+#define CONFIG_DEEP_SLEEP
+#define CONFIG_SILENT_CONSOLE
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xeff40000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+#define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC		CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_FSL_IFC			/* Enable IFC Support */
+#define CONFIG_PCI			/* Enable PCI/PCIE */
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_PCIE1			/* PCIE controler 1 */
+#define CONFIG_PCIE2			/* PCIE controler 2 */
+#define CONFIG_PCIE3			/* PCIE controler 3 */
+#define CONFIG_PCIE4			/* PCIE controler 4 */
+
+#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
+
+#define CONFIG_FSL_LAW			/* Use common FSL init code */
+
+#define CONFIG_ENV_OVERWRITE
+
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#endif
+
+#if defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
+#define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
+#define CONFIG_ENV_SECT_SIZE            0x10000
+#elif defined(CONFIG_SDCARD)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV          0
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_OFFSET		(512 * 0x800)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_OFFSET		(3 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+#endif
+
+#define CONFIG_SYS_CLK_FREQ	100000000
+#define CONFIG_DDR_CLK_FREQ	66666666
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BACKSIDE_L2_CACHE
+#define CONFIG_SYS_INIT_L2CSR0		L2CSR0_L2E
+#define CONFIG_BTB			/* toggle branch predition */
+#define CONFIG_DDR_ECC
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#endif
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP		64	/* number of TLB1 entries */
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_PANIC_HANG	/* do not reset board on panic */
+
+/*
+ *  Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
+#define CONFIG_SYS_L3_SIZE		256 << 10
+#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_ENV_ADDR			(CONFIG_SPL_GD_ADDR + 4 * 1024)
+#endif
+#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SPL_GD_ADDR + 12 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(30 << 10)
+#define CONFIG_SPL_RELOC_STACK		(CONFIG_SPL_GD_ADDR + 64 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE	(22 << 10)
+
+#define CONFIG_SYS_DCSRBAR		0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_DDR_RAW_TIMING
+#define CONFIG_SYS_FSL_DDR3
+
+#define CONFIG_SYS_SPD_BUS_NUM	0
+#define SPD_EEPROM_ADDRESS	0x51
+
+#define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE	0xe8000000
+#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+
+#define CONFIG_SYS_NOR_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NOR_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
+				FTIM0_NOR_TEADC(0x5) | \
+				FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
+				FTIM1_NOR_TRAD_NOR(0x1A) |\
+				FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
+				FTIM2_NOR_TCH(0x4) | \
+				FTIM2_NOR_TWPH(0x0E) | \
+				FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3	0x0
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS}
+
+/* CPLD on IFC */
+#define CPLD_LBMAP_MASK			0x3F
+#define CPLD_BANK_SEL_MASK		0x07
+#define CPLD_BANK_OVERRIDE		0x40
+#define CPLD_LBMAP_ALTBANK		0x44 /* BANK OR | BANK 4 */
+#define CPLD_LBMAP_DFLTBANK		0x40 /* BANK OR | BANK0 */
+#define CPLD_LBMAP_RESET		0xFF
+#define CPLD_LBMAP_SHIFT		0x03
+
+#define CONFIG_SYS_CPLD_BASE	0xffdf0000
+#define CONFIG_SYS_CPLD_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_CPLD_BASE)
+#define CONFIG_SYS_CSPR2_EXT	(0xf)
+#define CONFIG_SYS_CSPR2	(CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 \
+				| CSPR_MSEL_GPCM \
+				| CSPR_V)
+#define CONFIG_SYS_AMASK2	IFC_AMASK(64*1024)
+#define CONFIG_SYS_CSOR2	0x0
+/* CPLD Timing parameters for IFC CS2 */
+#define CONFIG_SYS_CS2_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
+					FTIM0_GPCM_TEADC(0x0e) | \
+					FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS2_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \
+					FTIM1_GPCM_TRAD(0x1f))
+#define CONFIG_SYS_CS2_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
+					FTIM2_GPCM_TCH(0x0) | \
+					FTIM2_GPCM_TWP(0x1f))
+#define CONFIG_SYS_CS2_FTIM3		0x0
+
+/* NAND Flash on IFC */
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_BASE		0xff800000
+#define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
+
+#define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+
+#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
+				| CSOR_NAND_RAL_3	/* RAL = 3Byes */ \
+				| CSOR_NAND_PGS_4K	/* Page Size = 4K */ \
+				| CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
+				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+					FTIM0_NAND_TWP(0x18)   | \
+					FTIM0_NAND_TWCHT(0x07) | \
+					FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+					FTIM1_NAND_TWBE(0x39)  | \
+					FTIM1_NAND_TRR(0x0e)   | \
+					FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
+					FTIM2_NAND_TREH(0x0a) | \
+					FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3		0x0
+
+#define CONFIG_SYS_NAND_DDR_LAW		11
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(512 * 1024)
+
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe0ec000
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
+#define CONFIG_SERIAL_MULTI		/* Enable both serial ports */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	/* determine from environment */
+#endif
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL		/* Use FSL common I2C driver */
+#define CONFIG_SYS_FSL_I2C_SPEED	400000	/* I2C speed in Hz */
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000	/* I2C speed in Hz */
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x119000
+
+/* I2C bus multiplexer */
+#define I2C_MUX_PCA_ADDR                0x70
+#ifdef CONFIG_T1040RDB
+#define I2C_MUX_CH_DEFAULT      0x8
+#endif
+
+#ifdef CONFIG_T1042RDB_PI
+/*
+ * RTC configuration
+ */
+#define RTC
+#define CONFIG_RTC_DS1337               1
+#define CONFIG_SYS_I2C_RTC_ADDR         0x68
+
+/*DVI encoder*/
+#define CONFIG_HDMI_ENCODER_I2C_ADDR  0x75
+#endif
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#define CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED         10000000
+#define CONFIG_SF_DEFAULT_MODE          0
+#define CONFIG_ENV_SPI_BUS              0
+#define CONFIG_ENV_SPI_CS               0
+#define CONFIG_ENV_SPI_MAX_HZ           10000000
+#define CONFIG_ENV_SPI_MODE             0
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+#ifdef CONFIG_PCI
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#ifdef CONFIG_PCIE1
+#define	CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#define	CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define	CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+#endif
+
+/* controller 2, Slot 2, tgtid 2, Base address 201000 */
+#ifdef CONFIG_PCIE2
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0x90000000
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc10000000ull
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+#endif
+
+/* controller 3, Slot 1, tgtid 1, Base address 202000 */
+#ifdef CONFIG_PCIE3
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc20000000ull
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
+#endif
+
+/* controller 4, Base address 203000 */
+#ifdef CONFIG_PCIE4
+#define CONFIG_SYS_PCIE4_MEM_VIRT	0xb0000000
+#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_PHYS	0xc30000000ull
+#define CONFIG_SYS_PCIE4_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE4_IO_VIRT	0xf8030000
+#define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
+#define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
+#endif
+
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+#define CONFIG_E1000
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif	/* CONFIG_PCI */
+
+/* SATA */
+#define CONFIG_FSL_SATA_V2
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+
+#define CONFIG_SYS_SATA_MAX_DEVICE	1
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
+
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+/*
+* USB
+*/
+#define CONFIG_HAS_FSL_DR_USB
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+#define CONFIG_USB_EHCI
+
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_CMD_EXT2
+#endif
+#endif
+
+#define CONFIG_MMC
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* Qman/Bman */
+#ifndef CONFIG_NOBQFMAN
+#define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS	25
+#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
+#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
+#define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
+#define CONFIG_SYS_QMAN_NUM_PORTALS	25
+#define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
+#define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
+#define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+
+#ifdef CONFIG_T1040RDB
+#define CONFIG_QE
+#define CONFIG_U_QE
+#endif
+
+/* Default address of microcode for the Linux Fman driver */
+#if defined(CONFIG_SPIFLASH)
+/*
+ * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
+ * env, so we got 0x110000.
+ */
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_FMAN_FW_ADDR	0x110000
+#elif defined(CONFIG_SDCARD)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 1MB (2048 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+#define CONFIG_SYS_FMAN_FW_ADDR	(512 * 0x820)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_FMAN_FW_ADDR	(5 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#else
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_FMAN_FW_ADDR		0xEFF00000
+#endif
+
+#ifdef CONFIG_T1040RDB
+#if defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_QE_FW_ADDR		0x130000
+#elif defined(CONFIG_SDCARD)
+#define CONFIG_SYS_QE_FW_ADDR		(512 * 0x920)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_QE_FW_ADDR		(7 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#else
+#define CONFIG_SYS_QE_FW_ADDR		0xEFF10000
+#endif
+#endif
+
+
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+#endif /* CONFIG_NOBQFMAN */
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_REALTEK
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+#ifdef CONFIG_T1040RDB
+#define CONFIG_SYS_SGMII1_PHY_ADDR		0x03
+#endif
+#define CONFIG_SYS_RGMII1_PHY_ADDR		0x01
+#define CONFIG_SYS_RGMII2_PHY_ADDR		0x02
+
+#define CONFIG_MII		/* MII PHY management */
+#define CONFIG_ETHPRIME		"FM1@DTSEC4"
+#define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#ifdef CONFIG_T1042RDB_PI
+#define CONFIG_CMD_DATE
+#endif
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ERRATA
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SETEXPR
+
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Dynamic MTD Partition support with mtdparts
+ */
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_FLASH_CFI_MTD
+#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
+			"spi0=spife110000.0"
+#define MTDPARTS_DEFAULT	"mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
+				"128k(dtb),96m(fs),-(user);"\
+				"fff800000.flash:2m(uboot),9m(kernel),"\
+				"128k(dtb),96m(fs),-(user);spife110000.0:" \
+				"2m(uboot),9m(kernel),128k(dtb),-(user)"
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	"u-boot.bin"	/* U-Boot image on TFTP server*/
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+#define CONFIG_BOOTDELAY	10	/*-1 disables auto-boot*/
+
+#define CONFIG_BAUDRATE	115200
+
+#define __USB_PHY_TYPE	utmi
+
+#ifdef CONFIG_T1040RDB
+#define FDTFILE		"t1040rdb/t1040rdb.dtb"
+#define RAMDISKFILE	"t1040rdb/ramdisk.uboot"
+#elif CONFIG_T1042RDB_PI
+#define FDTFILE		"t1040rdb_pi/t1040rdb_pi.dtb"
+#define RAMDISKFILE	"t1040rdb_pi/ramdisk.uboot"
+#endif
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hwconfig=fsl_ddr:bank_intlv=cs0_cs1;"			\
+	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
+	"usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
+	"netdev=eth0\0"						\
+	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
+	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
+	"tftpflash=tftpboot $loadaddr $uboot && "		\
+	"protect off $ubootaddr +$filesize && "			\
+	"erase $ubootaddr +$filesize && "			\
+	"cp.b $loadaddr $ubootaddr $filesize && "		\
+	"protect on $ubootaddr +$filesize && "			\
+	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
+	"consoledev=ttyS0\0"					\
+	"ramdiskaddr=2000000\0"					\
+	"ramdiskfile=" __stringify(RAMDISKFILE) "\0"		\
+	"fdtaddr=c00000\0"					\
+	"fdtfile=" __stringify(FDTFILE) "\0"			\
+	"bdev=sda3\0"						\
+	"c=ffe\0"
+
+#define CONFIG_LINUX                       \
+	"setenv bootargs root=/dev/ram rw "            \
+	"console=$consoledev,$baudrate $othbootargs;"  \
+	"setenv ramdiskaddr 0x02000000;"               \
+	"setenv fdtaddr 0x00c00000;"		       \
+	"setenv loadaddr 0x1000000;"		       \
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_HDBOOT					\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND			\
+	"setenv bootargs root=/dev/nfs rw "	\
+	"nfsroot=$serverip:$rootpath "		\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"		\
+	"tftp $fdtaddr $fdtfile;"		\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND				\
+	"setenv bootargs root=/dev/ram rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $ramdiskaddr $ramdiskfile;"		\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_LINUX
+
+#ifdef CONFIG_SECURE_BOOT
+#include <asm/fsl_secure_boot.h>
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/T208xQDS.h b/qemu/roms/u-boot/include/configs/T208xQDS.h
new file mode 100644
index 000000000..8bf08430b
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/T208xQDS.h
@@ -0,0 +1,914 @@
+/*
+ * Copyright 2011-2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/*
+ * T2080/T2081 QDS board configuration file
+ */
+
+#ifndef __T208xQDS_H
+#define __T208xQDS_H
+
+#define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
+#define CONFIG_MMC
+#define CONFIG_SPI_FLASH
+#define CONFIG_USB_EHCI
+#if defined(CONFIG_PPC_T2080)
+#define CONFIG_T2080QDS
+#define CONFIG_FSL_SATA_V2
+#define CONFIG_SYS_SRIO		/* Enable Serial RapidIO Support */
+#define CONFIG_SRIO1		/* SRIO port 1 */
+#define CONFIG_SRIO2		/* SRIO port 2 */
+#elif defined(CONFIG_PPC_T2081)
+#define CONFIG_T2081QDS
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_PHYS_64BIT
+#define CONFIG_BOOKE
+#define CONFIG_E500		/* BOOKE e500 family */
+#define CONFIG_E500MC		/* BOOKE e500mc family */
+#define CONFIG_SYS_BOOK3E_HV	/* Category E.HV supported */
+#define CONFIG_MP		/* support multiple processors */
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP 1
+#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
+#endif
+
+#define CONFIG_SYS_FSL_CPC	/* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC	CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_FSL_IFC		/* Enable IFC Support */
+#define CONFIG_FSL_LAW		/* Use common FSL init code */
+#define CONFIG_ENV_OVERWRITE
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg
+#if defined(CONFIG_PPC_T2080)
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_rcw.cfg
+#elif defined(CONFIG_PPC_T2081)
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_rcw.cfg
+#endif
+
+#define CONFIG_SPL
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_FSL_LAW			/* Use common FSL init code */
+#define CONFIG_SYS_TEXT_BASE		0x00201000
+#define CONFIG_SPL_TEXT_BASE		0xFFFD8000
+#define CONFIG_SPL_PAD_TO		0x40000
+#define CONFIG_SPL_MAX_SIZE		0x28000
+#define RESET_VECTOR_OFFSET		0x27FFC
+#define BOOT_PAGE_OFFSET		0x27000
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_SKIP_RELOCATE
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#define CONFIG_SYS_NO_FLASH
+#endif
+
+#ifdef CONFIG_NAND
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(256 << 10)
+#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#define CONFIG_SPL_NAND_BOOT
+#endif
+
+#ifdef CONFIG_SPIFLASH
+#define	CONFIG_RESET_VECTOR_ADDRESS		0x200FFC
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_MINIMAL
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE	(768 << 10)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST		(0x00200000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_START	(0x00200000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS	(256 << 10)
+#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#ifndef CONFIG_SPL_BUILD
+#define	CONFIG_SYS_MPC85XX_NO_RESETVEC
+#endif
+#define CONFIG_SPL_SPI_BOOT
+#endif
+
+#ifdef CONFIG_SDCARD
+#define	CONFIG_RESET_VECTOR_ADDRESS		0x200FFC
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_MMC_MINIMAL
+#define CONFIG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_DST	(0x00200000)
+#define CONFIG_SYS_MMC_U_BOOT_START	(0x00200000)
+#define CONFIG_SYS_MMC_U_BOOT_OFFS	(260 << 10)
+#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#ifndef CONFIG_SPL_BUILD
+#define	CONFIG_SYS_MPC85XX_NO_RESETVEC
+#endif
+#define CONFIG_SPL_MMC_BOOT
+#endif
+
+#endif /* CONFIG_RAMBOOT_PBL */
+
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+/* Set 1M boot space */
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
+		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CONFIG_SYS_NO_FLASH
+#endif
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xeff40000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BTB		/* toggle branch predition */
+#define CONFIG_DDR_ECC
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#endif
+
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#endif
+
+#if defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS	0
+#define CONFIG_ENV_SPI_CS	0
+#define CONFIG_ENV_SPI_MAX_HZ	10000000
+#define CONFIG_ENV_SPI_MODE	0
+#define CONFIG_ENV_SIZE		0x2000	   /* 8KB */
+#define CONFIG_ENV_OFFSET	0x100000   /* 1MB */
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#elif defined(CONFIG_SDCARD)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV	0
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_OFFSET	(512 * 0x800)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_OFFSET	(10 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+#define CONFIG_ENV_IS_IN_REMOTE
+#define CONFIG_ENV_ADDR		0xffe20000
+#define CONFIG_ENV_SIZE		0x2000
+#elif defined(CONFIG_ENV_IS_NOWHERE)
+#define CONFIG_ENV_SIZE		0x2000
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+#endif
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk()
+#define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk()
+
+/*
+ * Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
+#define CONFIG_SYS_L3_SIZE		(512 << 10)
+#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_ENV_ADDR			(CONFIG_SPL_GD_ADDR + 4 * 1024)
+#endif
+#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SPL_GD_ADDR + 12 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(50 << 10)
+#define CONFIG_SPL_RELOC_STACK		(CONFIG_SPL_GD_ADDR + 64 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE	(22 << 10)
+
+#define CONFIG_SYS_DCSRBAR	0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS	0xf00000000ull
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM	0
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(4 * CONFIG_DIMM_SLOTS_PER_CTLR)
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_FSL_DDR3
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SYS_SPD_BUS_NUM	0
+#define CONFIG_SYS_SDRAM_SIZE	2048	/* for fixed parameter use */
+#define SPD_EEPROM_ADDRESS1	0x51
+#define SPD_EEPROM_ADDRESS2	0x52
+#define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
+#define CTRL_INTLV_PREFERED	cacheline
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE		0xe0000000
+#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+				+ 0x8000000) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR1_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
+
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
+				FTIM0_NOR_TEADC(0x5) | \
+				FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
+				FTIM1_NOR_TRAD_NOR(0x1A) |\
+				FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
+				FTIM2_NOR_TCH(0x4) | \
+				FTIM2_NOR_TWPH(0x0E) | \
+				FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3	0x0
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS \
+					+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
+
+#define CONFIG_FSL_QIXIS	/* use common QIXIS code */
+#define QIXIS_BASE			0xffdf0000
+#define QIXIS_LBMAP_SWITCH		6
+#define QIXIS_LBMAP_MASK		0x0f
+#define QIXIS_LBMAP_SHIFT		0
+#define QIXIS_LBMAP_DFLTBANK		0x00
+#define QIXIS_LBMAP_ALTBANK		0x04
+#define QIXIS_RST_CTL_RESET		0x83
+#define QIXIS_RST_FORCE_MEM		0x1
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+#define QIXIS_BASE_PHYS		(0xf00000000ull | QIXIS_BASE)
+
+#define CONFIG_SYS_CSPR3_EXT	(0xf)
+#define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 \
+				| CSPR_MSEL_GPCM \
+				| CSPR_V)
+#define CONFIG_SYS_AMASK3	IFC_AMASK(4*1024)
+#define CONFIG_SYS_CSOR3	0x0
+/* QIXIS Timing parameters for IFC CS3 */
+#define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
+					FTIM0_GPCM_TEADC(0x0e) | \
+					FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
+					FTIM1_GPCM_TRAD(0x3f))
+#define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
+					FTIM2_GPCM_TCH(0x8) | \
+					FTIM2_GPCM_TWP(0x1f))
+#define CONFIG_SYS_CS3_FTIM3		0x0
+
+/* NAND Flash on IFC */
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_BASE		0xff800000
+#define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
+
+#define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+				| CSPR_MSEL_NAND	 /* MSEL = NAND */ \
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+
+#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */	    \
+				| CSOR_NAND_RAL_3	/* RAL = 2Byes */   \
+				| CSOR_NAND_PGS_2K	/* Page Size = 2K */\
+				| CSOR_NAND_SPRZ_64	/* Spare size = 64 */\
+				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+					FTIM0_NAND_TWP(0x18)    | \
+					FTIM0_NAND_TWCHT(0x07)  | \
+					FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+					FTIM1_NAND_TWBE(0x39)   | \
+					FTIM1_NAND_TRR(0x0e)    | \
+					FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f)  | \
+					FTIM2_NAND_TREH(0x0a)   | \
+					FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3		0x0
+
+#define CONFIG_SYS_NAND_DDR_LAW		11
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
+#endif
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000 /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe0ec000
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+			((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+			CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+						GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SLAVE   0x7F
+#define CONFIG_SYS_FSL_I2C2_SLAVE  0x7F
+#define CONFIG_SYS_FSL_I2C3_SLAVE  0x7F
+#define CONFIG_SYS_FSL_I2C4_SLAVE  0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET  0x118000
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
+#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
+#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
+#define CONFIG_SYS_FSL_I2C_SPEED   100000
+#define CONFIG_SYS_FSL_I2C2_SPEED  100000
+#define CONFIG_SYS_FSL_I2C3_SPEED  100000
+#define CONFIG_SYS_FSL_I2C4_SPEED  100000
+#define I2C_MUX_PCA_ADDR_PRI	0x77 /* I2C bus multiplexer,primary */
+#define I2C_MUX_PCA_ADDR_SEC1	0x75 /* I2C bus multiplexer,secondary 1 */
+#define I2C_MUX_PCA_ADDR_SEC2	0x76 /* I2C bus multiplexer,secondary 2 */
+#define I2C_MUX_CH_DEFAULT	0x8
+
+
+/*
+ * RapidIO
+ */
+#define CONFIG_SYS_SRIO1_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
+#define CONFIG_SYS_SRIO1_MEM_SIZE	0x10000000 /* 256M */
+#define CONFIG_SYS_SRIO2_MEM_VIRT	0xb0000000
+#define CONFIG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
+#define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000 /* 256M */
+/*
+ * for slave u-boot IMAGE instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x80000 /* 512K */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
+/*
+ * for slave UCODE and ENV instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000	/* 256K */
+
+/* slave core release by master*/
+#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
+#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
+
+/*
+ * SRIO_PCIE_BOOT - SLAVE
+ */
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
+		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
+#endif
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#ifdef CONFIG_SPI_FLASH
+#define CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH_STMICRO
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_SPI_FLASH_EON
+#endif
+
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH_BAR
+#define CONFIG_SF_DEFAULT_SPEED	 10000000
+#define CONFIG_SF_DEFAULT_MODE	  0
+#endif
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+#define CONFIG_PCI		/* Enable PCI/PCIE */
+#define CONFIG_PCIE1		/* PCIE controler 1 */
+#define CONFIG_PCIE2		/* PCIE controler 2 */
+#define CONFIG_PCIE3		/* PCIE controler 3 */
+#define CONFIG_PCIE4		/* PCIE controler 4 */
+#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000      /* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 2, Slot 2, tgtid 2, Base address 201000 */
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000 /* 256M */
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 3, Slot 1, tgtid 1, Base address 202000 */
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0xb0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc30000000ull
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 4, Base address 203000 */
+#define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
+#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_PHYS	0xc40000000ull
+#define CONFIG_SYS_PCIE4_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
+#define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_FSL_PCIE_RESET	   /* need PCIe reset errata */
+#define CONFIG_NET_MULTI
+#define CONFIG_E1000
+#define CONFIG_PCI_PNP		/* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* Qman/Bman */
+#ifndef CONFIG_NOBQFMAN
+#define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS	18
+#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
+#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
+#define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
+#define CONFIG_SYS_QMAN_NUM_PORTALS	18
+#define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
+#define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
+#define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+#define CONFIG_SYS_PMAN
+#define CONFIG_SYS_DPAA_DCE
+#define CONFIG_SYS_DPAA_RMAN		/* RMan */
+#define CONFIG_SYS_INTERLAKEN
+
+/* Default address of microcode for the Linux Fman driver */
+#if defined(CONFIG_SPIFLASH)
+/*
+ * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
+ * env, so we got 0x110000.
+ */
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_FMAN_FW_ADDR	0x110000
+#elif defined(CONFIG_SDCARD)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 1MB (2048 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+#define CONFIG_SYS_FMAN_FW_ADDR	(512 * 0x820)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_FMAN_FW_ADDR	(11 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+/*
+ * Slave has no ucode locally, it can fetch this from remote. When implementing
+ * in two corenet boards, slave's ucode could be stored in master's memory
+ * space, the address can be mapped from slave TLB->slave LAW->
+ * slave SRIO or PCIE outbound window->master inbound window->
+ * master LAW->the ucode address in master's memory space.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
+#define CONFIG_SYS_FMAN_FW_ADDR	0xFFE00000
+#else
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_FMAN_FW_ADDR	0xEFF00000
+#endif
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+#endif /* CONFIG_NOBQFMAN */
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_REALTEK
+#define CONFIG_PHY_TERANETICS
+#define RGMII_PHY1_ADDR	0x1
+#define RGMII_PHY2_ADDR	0x2
+#define FM1_10GEC1_PHY_ADDR	  0x3
+#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
+#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
+#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
+#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_MII		/* MII PHY management */
+#define CONFIG_ETHPRIME		"FM1@DTSEC3"
+#define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
+#endif
+
+/*
+ * SATA
+ */
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+/*
+ * USB
+ */
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_CMD_EXT2
+#define CONFIG_HAS_FSL_DR_USB
+#endif
+
+/*
+ * SDHC
+ */
+#ifdef CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+
+/*
+ * Dynamic MTD Partition support with mtdparts
+ */
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_FLASH_CFI_MTD
+#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
+			"spi0=spife110000.0"
+#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
+			"128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \
+			"5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \
+			"1m(uboot),5m(kernel),128k(dtb),-(user)"
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_LOADS_ECHO	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ERRATA
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_BDI
+
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_CMDLINE_EDITING		/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE		/* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT	"=> "	  /* Monitor Command Prompt */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE	1024	  /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	256	  /* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH	 "/opt/nfsroot"
+#define CONFIG_BOOTFILE	 "uImage"
+#define CONFIG_UBOOTPATH "u-boot.bin"	/* U-Boot image on TFTP server */
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
+#define __USB_PHY_TYPE		utmi
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hwconfig=fsl_ddr:"					\
+	"ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","	\
+	"bank_intlv=auto;"					\
+	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
+	"netdev=eth0\0"						\
+	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
+	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
+	"tftpflash=tftpboot $loadaddr $uboot && "		\
+	"protect off $ubootaddr +$filesize && "			\
+	"erase $ubootaddr +$filesize && "			\
+	"cp.b $loadaddr $ubootaddr $filesize && "		\
+	"protect on $ubootaddr +$filesize && "			\
+	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
+	"consoledev=ttyS0\0"					\
+	"ramdiskaddr=2000000\0"					\
+	"ramdiskfile=t2080qds/ramdisk.uboot\0"			\
+	"fdtaddr=c00000\0"					\
+	"fdtfile=t2080qds/t2080qds.dtb\0"			\
+	"bdev=sda3\0"						\
+	"c=ffe\0"
+
+/*
+ * For emulation this causes u-boot to jump to the start of the
+ * proof point app code automatically
+ */
+#define CONFIG_PROOF_POINTS				\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"cpu 1 release 0x29000000 - - -;"		\
+	"cpu 2 release 0x29000000 - - -;"		\
+	"cpu 3 release 0x29000000 - - -;"		\
+	"cpu 4 release 0x29000000 - - -;"		\
+	"cpu 5 release 0x29000000 - - -;"		\
+	"cpu 6 release 0x29000000 - - -;"		\
+	"cpu 7 release 0x29000000 - - -;"		\
+	"go 0x29000000"
+
+#define CONFIG_HVBOOT				\
+	"setenv bootargs config-addr=0x60000000; "	\
+	"bootm 0x01000000 - 0x00f00000"
+
+#define CONFIG_ALU				\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"cpu 1 release 0x01000000 - - -;"		\
+	"cpu 2 release 0x01000000 - - -;"		\
+	"cpu 3 release 0x01000000 - - -;"		\
+	"cpu 4 release 0x01000000 - - -;"		\
+	"cpu 5 release 0x01000000 - - -;"		\
+	"cpu 6 release 0x01000000 - - -;"		\
+	"cpu 7 release 0x01000000 - - -;"		\
+	"go 0x01000000"
+
+#define CONFIG_LINUX				\
+	"setenv bootargs root=/dev/ram rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"setenv ramdiskaddr 0x02000000;"		\
+	"setenv fdtaddr 0x00c00000;"			\
+	"setenv loadaddr 0x1000000;"			\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_HDBOOT					\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND			\
+	"setenv bootargs root=/dev/nfs rw "	\
+	"nfsroot=$serverip:$rootpath "		\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"		\
+	"tftp $fdtaddr $fdtfile;"		\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND				\
+	"setenv bootargs root=/dev/ram rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $ramdiskaddr $ramdiskfile;"		\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_LINUX
+
+#ifdef CONFIG_SECURE_BOOT
+#include <asm/fsl_secure_boot.h>
+#undef CONFIG_CMD_USB
+#endif
+
+#endif	/* __T208xQDS_H */
diff --git a/qemu/roms/u-boot/include/configs/T208xRDB.h b/qemu/roms/u-boot/include/configs/T208xRDB.h
new file mode 100644
index 000000000..5b261788c
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/T208xRDB.h
@@ -0,0 +1,874 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/*
+ * T2080 RDB/PCIe board configuration file
+ */
+
+#ifndef __T2080RDB_H
+#define __T2080RDB_H
+
+#define CONFIG_T2080RDB
+#define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
+#define CONFIG_MMC
+#define CONFIG_SPI_FLASH
+#define CONFIG_USB_EHCI
+#define CONFIG_FSL_SATA_V2
+
+/* High Level Configuration Options */
+#define CONFIG_PHYS_64BIT
+#define CONFIG_BOOKE
+#define CONFIG_E500		/* BOOKE e500 family */
+#define CONFIG_E500MC		/* BOOKE e500mc family */
+#define CONFIG_SYS_BOOK3E_HV	/* Category E.HV supported */
+#define CONFIG_MP		/* support multiple processors */
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP 1
+#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
+#endif
+
+#define CONFIG_SYS_FSL_CPC	/* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC	CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_FSL_IFC		/* Enable IFC Support */
+#define CONFIG_FSL_LAW		/* Use common FSL init code */
+#define CONFIG_ENV_OVERWRITE
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_rcw.cfg
+
+#define CONFIG_SPL
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_FSL_LAW			/* Use common FSL init code */
+#define CONFIG_SYS_TEXT_BASE		0x00201000
+#define CONFIG_SPL_TEXT_BASE		0xFFFD8000
+#define CONFIG_SPL_PAD_TO		0x40000
+#define CONFIG_SPL_MAX_SIZE		0x28000
+#define RESET_VECTOR_OFFSET		0x27FFC
+#define BOOT_PAGE_OFFSET		0x27000
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_SKIP_RELOCATE
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#define CONFIG_SYS_NO_FLASH
+#endif
+
+#ifdef CONFIG_NAND
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(256 << 10)
+#define CONFIG_SYS_LDSCRIPT  "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#define CONFIG_SPL_NAND_BOOT
+#endif
+
+#ifdef CONFIG_SPIFLASH
+#define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_MINIMAL
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE       (768 << 10)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST                (0x00200000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_START      (0x00200000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS       (256 << 10)
+#define CONFIG_SYS_LDSCRIPT    "arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#endif
+#define CONFIG_SPL_SPI_BOOT
+#endif
+
+#ifdef CONFIG_SDCARD
+#define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_MMC_MINIMAL
+#define CONFIG_SYS_MMC_U_BOOT_SIZE     (768 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_DST      (0x00200000)
+#define CONFIG_SYS_MMC_U_BOOT_START    (0x00200000)
+#define CONFIG_SYS_MMC_U_BOOT_OFFS     (260 << 10)
+#define CONFIG_SYS_LDSCRIPT    "arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#endif
+#define CONFIG_SPL_MMC_BOOT
+#endif
+
+#endif /* CONFIG_RAMBOOT_PBL */
+
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+/* Set 1M boot space */
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
+		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CONFIG_SYS_NO_FLASH
+#endif
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xeff40000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BTB		/* toggle branch predition */
+#define CONFIG_DDR_ECC
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#endif
+
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#endif
+
+#if defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS	0
+#define CONFIG_ENV_SPI_CS	0
+#define CONFIG_ENV_SPI_MAX_HZ	10000000
+#define CONFIG_ENV_SPI_MODE	0
+#define CONFIG_ENV_SIZE		0x2000	   /* 8KB */
+#define CONFIG_ENV_OFFSET	0x100000   /* 1MB */
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#elif defined(CONFIG_SDCARD)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV	0
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_OFFSET	(512 * 0x800)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_OFFSET	(2 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+#define CONFIG_ENV_IS_IN_REMOTE
+#define CONFIG_ENV_ADDR		0xffe20000
+#define CONFIG_ENV_SIZE		0x2000
+#elif defined(CONFIG_ENV_IS_NOWHERE)
+#define CONFIG_ENV_SIZE		0x2000
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+#endif
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ	66660000
+#define CONFIG_DDR_CLK_FREQ	133330000
+
+/*
+ * Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
+#define CONFIG_SYS_L3_SIZE		(512 << 10)
+#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_ENV_ADDR			(CONFIG_SPL_GD_ADDR + 4 * 1024)
+#endif
+#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SPL_GD_ADDR + 12 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(50 << 10)
+#define CONFIG_SPL_RELOC_STACK		(CONFIG_SPL_GD_ADDR + 64 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE	(22 << 10)
+
+#define CONFIG_SYS_DCSRBAR	0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS	0xf00000000ull
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM	0
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(4 * CONFIG_DIMM_SLOTS_PER_CTLR)
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_FSL_DDR3
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SYS_SPD_BUS_NUM	0
+#define CONFIG_SYS_SDRAM_SIZE	2048	/* for fixed parameter use */
+#define SPD_EEPROM_ADDRESS1	0x51
+#define SPD_EEPROM_ADDRESS2	0x52
+#define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
+#define CTRL_INTLV_PREFERED	cacheline
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE		0xe8000000
+#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
+
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
+
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
+				FTIM0_NOR_TEADC(0x5) | \
+				FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
+				FTIM1_NOR_TRAD_NOR(0x1A) |\
+				FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
+				FTIM2_NOR_TCH(0x4) | \
+				FTIM2_NOR_TWPH(0x0E) | \
+				FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3	0x0
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS }
+
+/* CPLD on IFC */
+#define CONFIG_SYS_CPLD_BASE	0xffdf0000
+#define CONFIG_SYS_CPLD_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_CPLD_BASE)
+#define CONFIG_SYS_CSPR2_EXT	(0xf)
+#define CONFIG_SYS_CSPR2	(CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
+				| CSPR_PORT_SIZE_8 \
+				| CSPR_MSEL_GPCM \
+				| CSPR_V)
+#define CONFIG_SYS_AMASK2	IFC_AMASK(64*1024)
+#define CONFIG_SYS_CSOR2	0x0
+
+/* CPLD Timing parameters for IFC CS2 */
+#define CONFIG_SYS_CS2_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
+					FTIM0_GPCM_TEADC(0x0e) | \
+					FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS2_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \
+					FTIM1_GPCM_TRAD(0x1f))
+#define CONFIG_SYS_CS2_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
+					FTIM2_GPCM_TCH(0x0) | \
+					FTIM2_GPCM_TWP(0x1f))
+#define CONFIG_SYS_CS2_FTIM3		0x0
+
+/* NAND Flash on IFC */
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_BASE		0xff800000
+#define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
+
+#define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+				| CSPR_MSEL_NAND	 /* MSEL = NAND */ \
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+
+#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */	    \
+				| CSOR_NAND_RAL_3	/* RAL = 2Byes */   \
+				| CSOR_NAND_PGS_2K	/* Page Size = 2K */\
+				| CSOR_NAND_SPRZ_64	/* Spare size = 64 */\
+				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+					FTIM0_NAND_TWP(0x18)    | \
+					FTIM0_NAND_TWCHT(0x07)  | \
+					FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+					FTIM1_NAND_TWBE(0x39)   | \
+					FTIM1_NAND_TRR(0x0e)    | \
+					FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f)  | \
+					FTIM2_NAND_TREH(0x0a)   | \
+					FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3		0x0
+
+#define CONFIG_SYS_NAND_DDR_LAW		11
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(512 * 1024)
+
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
+#endif
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE  CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE  CONFIG_SYS_TEXT_BASE /* start of monitor */
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000 /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe0ec000
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+			((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+			CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+						GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SLAVE   0x7F
+#define CONFIG_SYS_FSL_I2C2_SLAVE  0x7F
+#define CONFIG_SYS_FSL_I2C3_SLAVE  0x7F
+#define CONFIG_SYS_FSL_I2C4_SLAVE  0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET  0x118000
+#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
+#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
+#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
+#define CONFIG_SYS_FSL_I2C_SPEED   100000
+#define CONFIG_SYS_FSL_I2C2_SPEED  100000
+#define CONFIG_SYS_FSL_I2C3_SPEED  100000
+#define CONFIG_SYS_FSL_I2C4_SPEED  100000
+#define I2C_MUX_PCA_ADDR_PRI	0x77 /* I2C bus multiplexer,primary */
+#define I2C_MUX_PCA_ADDR_SEC1	0x75 /* I2C bus multiplexer,secondary 1 */
+#define I2C_MUX_PCA_ADDR_SEC2	0x76 /* I2C bus multiplexer,secondary 2 */
+#define I2C_MUX_CH_DEFAULT	0x8
+
+
+/*
+ * RapidIO
+ */
+#define CONFIG_SYS_SRIO1_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
+#define CONFIG_SYS_SRIO1_MEM_SIZE	0x10000000 /* 256M */
+#define CONFIG_SYS_SRIO2_MEM_VIRT	0xb0000000
+#define CONFIG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
+#define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000 /* 256M */
+/*
+ * for slave u-boot IMAGE instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x80000 /* 512K */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
+/*
+ * for slave UCODE and ENV instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000	/* 256K */
+
+/* slave core release by master*/
+#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
+#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
+
+/*
+ * SRIO_PCIE_BOOT - SLAVE
+ */
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
+		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
+#endif
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#ifdef CONFIG_SPI_FLASH
+#define CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_BAR
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED	 10000000
+#define CONFIG_SF_DEFAULT_MODE	  0
+#endif
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+#define CONFIG_PCI		/* Enable PCI/PCIE */
+#define CONFIG_PCIE1		/* PCIE controler 1 */
+#define CONFIG_PCIE2		/* PCIE controler 2 */
+#define CONFIG_PCIE3		/* PCIE controler 3 */
+#define CONFIG_PCIE4		/* PCIE controler 4 */
+#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000      /* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 2, Slot 2, tgtid 2, Base address 201000 */
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000 /* 256M */
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 3, Slot 1, tgtid 1, Base address 202000 */
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0xb0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc30000000ull
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 4, Base address 203000 */
+#define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
+#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_PHYS	0xc40000000ull
+#define CONFIG_SYS_PCIE4_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
+#define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata LSZ ADD */
+#define CONFIG_NET_MULTI
+#define CONFIG_E1000
+#define CONFIG_PCI_PNP		/* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* Qman/Bman */
+#ifndef CONFIG_NOBQFMAN
+#define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS	18
+#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
+#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
+#define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
+#define CONFIG_SYS_QMAN_NUM_PORTALS	18
+#define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
+#define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
+#define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+#define CONFIG_SYS_PMAN
+#define CONFIG_SYS_DPAA_DCE
+#define CONFIG_SYS_DPAA_RMAN		/* RMan */
+#define CONFIG_SYS_INTERLAKEN
+
+/* Default address of microcode for the Linux Fman driver */
+#if defined(CONFIG_SPIFLASH)
+/*
+ * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
+ * env, so we got 0x110000.
+ */
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH
+#define CONFIG_SYS_FMAN_FW_ADDR		0x110000
+#define CONFIG_CORTINA_FW_ADDR		0x120000
+
+#elif defined(CONFIG_SDCARD)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 1MB (2048 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+#define CONFIG_SYS_CORTINA_FW_IN_MMC
+#define CONFIG_SYS_FMAN_FW_ADDR		(512 * 0x820)
+#define CONFIG_CORTINA_FW_ADDR		(512 * 0x8a0)
+
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_CORTINA_FW_IN_NAND
+#define CONFIG_SYS_FMAN_FW_ADDR		(3 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_CORTINA_FW_ADDR		(4 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+/*
+ * Slave has no ucode locally, it can fetch this from remote. When implementing
+ * in two corenet boards, slave's ucode could be stored in master's memory
+ * space, the address can be mapped from slave TLB->slave LAW->
+ * slave SRIO or PCIE outbound window->master inbound window->
+ * master LAW->the ucode address in master's memory space.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
+#define CONFIG_SYS_CORTINA_FW_IN_REMOTE
+#define CONFIG_SYS_FMAN_FW_ADDR		0xFFE00000
+#define CONFIG_CORTINA_FW_ADDR		0xFFE10000
+#else
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_CORTINA_FW_IN_NOR
+#define CONFIG_SYS_FMAN_FW_ADDR		0xEFF00000
+#define CONFIG_CORTINA_FW_ADDR		0xEFE00000
+#endif
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+#endif /* CONFIG_NOBQFMAN */
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_CORTINA
+#define CONFIG_PHY_AQ1202
+#define CONFIG_PHY_REALTEK
+#define CONFIG_CORTINA_FW_LENGTH	0x40000
+#define RGMII_PHY1_ADDR		0x01  /* RealTek RTL8211E */
+#define RGMII_PHY2_ADDR		0x02
+#define CORTINA_PHY_ADDR1	0x0c  /* Cortina CS4315 */
+#define CORTINA_PHY_ADDR2	0x0d
+#define FM1_10GEC3_PHY_ADDR	0x00  /* Aquantia AQ1202 10G Base-T */
+#define FM1_10GEC4_PHY_ADDR	0x01
+#endif
+
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_MII		/* MII PHY management */
+#define CONFIG_ETHPRIME		"FM1@DTSEC3"
+#define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
+#endif
+
+/*
+ * SATA
+ */
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+/*
+ * USB
+ */
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_CMD_EXT2
+#define CONFIG_HAS_FSL_DR_USB
+#endif
+
+/*
+ * SDHC
+ */
+#ifdef CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * Dynamic MTD Partition support with mtdparts
+ */
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_FLASH_CFI_MTD
+#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
+			"spi0=spife110000.1"
+#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
+			"128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \
+			"5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:" \
+			"1m(uboot),5m(kernel),128k(dtb),-(user)"
+#endif
+
+/*
+ * Environment
+ */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ERRATA
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_BDI
+
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_CMDLINE_EDITING		/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE		/* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT	"=> "	  /* Monitor Command Prompt */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE	1024	  /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	256	  /* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH	 "/opt/nfsroot"
+#define CONFIG_BOOTFILE	 "uImage"
+#define CONFIG_UBOOTPATH "u-boot.bin"	/* U-Boot image on TFTP server */
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
+#define __USB_PHY_TYPE		utmi
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hwconfig=fsl_ddr:"					\
+	"ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","	\
+	"bank_intlv=auto;"					\
+	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
+	"netdev=eth0\0"						\
+	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
+	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
+	"tftpflash=tftpboot $loadaddr $uboot && "		\
+	"protect off $ubootaddr +$filesize && "			\
+	"erase $ubootaddr +$filesize && "			\
+	"cp.b $loadaddr $ubootaddr $filesize && "		\
+	"protect on $ubootaddr +$filesize && "			\
+	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
+	"consoledev=ttyS0\0"					\
+	"ramdiskaddr=2000000\0"					\
+	"ramdiskfile=t2080rdb/ramdisk.uboot\0"			\
+	"fdtaddr=c00000\0"					\
+	"fdtfile=t2080rdb/t2080rdb.dtb\0"			\
+	"bdev=sda3\0"						\
+	"c=ffe\0"
+
+/*
+ * For emulation this causes u-boot to jump to the start of the
+ * proof point app code automatically
+ */
+#define CONFIG_PROOF_POINTS				\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"cpu 1 release 0x29000000 - - -;"		\
+	"cpu 2 release 0x29000000 - - -;"		\
+	"cpu 3 release 0x29000000 - - -;"		\
+	"cpu 4 release 0x29000000 - - -;"		\
+	"cpu 5 release 0x29000000 - - -;"		\
+	"cpu 6 release 0x29000000 - - -;"		\
+	"cpu 7 release 0x29000000 - - -;"		\
+	"go 0x29000000"
+
+#define CONFIG_HVBOOT				\
+	"setenv bootargs config-addr=0x60000000; "	\
+	"bootm 0x01000000 - 0x00f00000"
+
+#define CONFIG_ALU				\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"cpu 1 release 0x01000000 - - -;"		\
+	"cpu 2 release 0x01000000 - - -;"		\
+	"cpu 3 release 0x01000000 - - -;"		\
+	"cpu 4 release 0x01000000 - - -;"		\
+	"cpu 5 release 0x01000000 - - -;"		\
+	"cpu 6 release 0x01000000 - - -;"		\
+	"cpu 7 release 0x01000000 - - -;"		\
+	"go 0x01000000"
+
+#define CONFIG_LINUX				\
+	"setenv bootargs root=/dev/ram rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"setenv ramdiskaddr 0x02000000;"		\
+	"setenv fdtaddr 0x00c00000;"			\
+	"setenv loadaddr 0x1000000;"			\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_HDBOOT					\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND			\
+	"setenv bootargs root=/dev/nfs rw "	\
+	"nfsroot=$serverip:$rootpath "		\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"		\
+	"tftp $fdtaddr $fdtfile;"		\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND				\
+	"setenv bootargs root=/dev/ram rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $ramdiskaddr $ramdiskfile;"		\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_LINUX
+
+#ifdef CONFIG_SECURE_BOOT
+#include <asm/fsl_secure_boot.h>
+#undef CONFIG_CMD_USB
+#endif
+
+#endif	/* __T2080RDB_H */
diff --git a/qemu/roms/u-boot/include/configs/T4240EMU.h b/qemu/roms/u-boot/include/configs/T4240EMU.h
new file mode 100644
index 000000000..ad5a9a6f0
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/T4240EMU.h
@@ -0,0 +1,166 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * T4240 EMU board configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_T4240EMU
+#define CONFIG_PHYS_64BIT
+
+#define CONFIG_SYS_NO_FLASH		1
+#define CONFIG_SYS_FSL_DDR_EMU		1
+#define CONFIG_SYS_FSL_NO_QIXIS		1
+#define CONFIG_SYS_FSL_NO_SERDES	1
+
+#include "t4qds.h"
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_CACHE_FLUSH
+
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE         0x2000
+
+#define CONFIG_SYS_CLK_FREQ	100000000
+#define CONFIG_DDR_CLK_FREQ	133333333
+#define CONFIG_FSL_TBCLK_EXTRA_DIV 100
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_SPD_BUS_NUM	1
+#define SPD_EEPROM_ADDRESS1	0x51
+#define SPD_EEPROM_ADDRESS2	0x52
+#define SPD_EEPROM_ADDRESS3	0x53
+#define SPD_EEPROM_ADDRESS4	0x54
+#define SPD_EEPROM_ADDRESS5	0x55
+#define SPD_EEPROM_ADDRESS6	0x56
+#define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1	/* for p3041/p5010 */
+#define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+				+ 0x8000000) | \
+				CSPR_PORT_SIZE_32 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(0)
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x1) | \
+				FTIM0_NOR_TEADC(0x1) | \
+				FTIM0_NOR_TEAHC(0x1))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x1) | \
+				FTIM1_NOR_TRAD_NOR(0x1))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x0) | \
+				FTIM2_NOR_TCH(0x0) | \
+				FTIM2_NOR_TWP(0x1))
+#define CONFIG_SYS_NOR_FTIM3	0x04000000
+#define CONFIG_SYS_IFC_CCR	0x01000000
+
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+
+/* I2C */
+#define CONFIG_SYS_FSL_I2C_SPEED	4000000	/* faster speed for emulator */
+#define CONFIG_SYS_FSL_I2C2_SPEED	4000000
+
+/* Qman/Bman */
+#define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS	50
+#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
+#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
+#define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
+#define CONFIG_SYS_QMAN_NUM_PORTALS	50
+#define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
+#define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
+#define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+#define CONFIG_SYS_PMAN
+#define CONFIG_SYS_DPAA_DCE
+#define CONFIG_SYS_DPAA_RMAN
+#define CONFIG_SYS_INTERLAKEN
+
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_FMAN_FW_ADDR		0xEFF00000
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+
+#define CONFIG_BOOTDELAY	0
+
+/*
+ * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
+ * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
+ * interleaving. It can be cacheline, page, bank, superbank.
+ * See doc/README.fsl-ddr for details.
+ */
+#ifdef CONFIG_PPC_T4240
+#define CTRL_INTLV_PREFERED 3way_4KB
+#else
+#define CTRL_INTLV_PREFERED cacheline
+#endif
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hwconfig=fsl_ddr:"					\
+	"ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","	\
+	"bank_intlv=auto;"					\
+	"netdev=eth0\0"						\
+	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
+"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"		\
+	"consoledev=ttyS0\0"					\
+	"ramdiskaddr=2000000\0"					\
+	"ramdiskfile=t4240emu/ramdisk.uboot\0"			\
+	"fdtaddr=c00000\0"					\
+	"fdtfile=t4240emu/t4240emu.dtb\0"				\
+	"bdev=sda3\0"						\
+	"c=ffe\0"
+
+/*
+ * For emulation this causes u-boot to jump to the start of the proof point
+ * app code automatically
+ */
+#define CONFIG_PROOF_POINTS			\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"cpu 1 release 0x29000000 - - -;"		\
+	"cpu 2 release 0x29000000 - - -;"		\
+	"cpu 3 release 0x29000000 - - -;"		\
+	"cpu 4 release 0x29000000 - - -;"		\
+	"cpu 5 release 0x29000000 - - -;"		\
+	"cpu 6 release 0x29000000 - - -;"		\
+	"cpu 7 release 0x29000000 - - -;"		\
+	"go 0x29000000"
+
+#define CONFIG_HVBOOT				\
+	"setenv bootargs config-addr=0x60000000; "	\
+	"bootm 0x01000000 - 0x00f00000"
+
+#define CONFIG_LINUX					\
+	"errata;"					\
+	"setenv othbootargs ignore_loglevel;"		\
+	"setenv bootargs root=/dev/ram rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"setenv ramdiskaddr 0x02000000;"		\
+	"setenv fdtaddr 0x00c00000;"			\
+	"setenv loadaddr 0x1000000;"			\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_LINUX
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/T4240QDS.h b/qemu/roms/u-boot/include/configs/T4240QDS.h
new file mode 100644
index 000000000..e4eb30fbe
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/T4240QDS.h
@@ -0,0 +1,630 @@
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * T4240 QDS board configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_T4240QDS
+#define CONFIG_PHYS_64BIT
+
+#define CONFIG_FSL_SATA_V2
+#define CONFIG_PCIE4
+
+#define CONFIG_ICS307_REFCLK_HZ		25000000  /* ICS307 ref clk freq */
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_rcw.cfg
+#if !defined(CONFIG_NAND) && !defined(CONFIG_SDCARD)
+#define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
+#define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
+#else
+#define CONFIG_SPL
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_FSL_LAW                 /* Use common FSL init code */
+#define CONFIG_SYS_TEXT_BASE		0x00201000
+#define CONFIG_SPL_TEXT_BASE		0xFFFD8000
+#define CONFIG_SPL_PAD_TO		0x40000
+#define CONFIG_SPL_MAX_SIZE		0x28000
+#define RESET_VECTOR_OFFSET		0x27FFC
+#define BOOT_PAGE_OFFSET		0x27000
+
+#ifdef	CONFIG_NAND
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(256 << 10)
+#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#define CONFIG_SPL_NAND_BOOT
+#endif
+
+#ifdef	CONFIG_SDCARD
+#define	CONFIG_RESET_VECTOR_ADDRESS	0x200FFC
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_MMC_MINIMAL
+#define CONFIG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_DST	0x00200000
+#define CONFIG_SYS_MMC_U_BOOT_START	0x00200000
+#define CONFIG_SYS_MMC_U_BOOT_OFFS	(260 << 10)
+#ifndef CONFIG_SPL_BUILD
+#define	CONFIG_SYS_MPC85XX_NO_RESETVEC
+#endif
+#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#define CONFIG_SPL_MMC_BOOT
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_SKIP_RELOCATE
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#define CONFIG_SYS_NO_FLASH
+#endif
+
+#endif
+#endif /* CONFIG_RAMBOOT_PBL */
+
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+/* Set 1M boot space */
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
+		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CONFIG_SYS_NO_FLASH
+#endif
+
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
+#define CONFIG_DDR_ECC
+
+#include "t4qds.h"
+
+#ifdef CONFIG_SYS_NO_FLASH
+#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+#else
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#endif
+
+#if defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS              0
+#define CONFIG_ENV_SPI_CS               0
+#define CONFIG_ENV_SPI_MAX_HZ           10000000
+#define CONFIG_ENV_SPI_MODE             0
+#define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
+#define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
+#define CONFIG_ENV_SECT_SIZE            0x10000
+#elif defined(CONFIG_SDCARD)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV          0
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_OFFSET		(512 * 0x800)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_OFFSET		(10 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+#define CONFIG_ENV_IS_IN_REMOTE
+#define CONFIG_ENV_ADDR		0xffe20000
+#define CONFIG_ENV_SIZE		0x2000
+#elif defined(CONFIG_ENV_IS_NOWHERE)
+#define CONFIG_ENV_SIZE		0x2000
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+#endif
+
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk()
+#define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk()
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM	0
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_SPD_BUS_NUM	0
+#define SPD_EEPROM_ADDRESS1	0x51
+#define SPD_EEPROM_ADDRESS2	0x52
+#define SPD_EEPROM_ADDRESS3	0x53
+#define SPD_EEPROM_ADDRESS4	0x54
+#define SPD_EEPROM_ADDRESS5	0x55
+#define SPD_EEPROM_ADDRESS6	0x56
+#define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1	/* for p3041/p5010 */
+#define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+				+ 0x8000000) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR1_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
+
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
+				FTIM0_NOR_TEADC(0x5) | \
+				FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
+				FTIM1_NOR_TRAD_NOR(0x1A) |\
+				FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
+				FTIM2_NOR_TCH(0x4) | \
+				FTIM2_NOR_TWPH(0x0E) | \
+				FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3	0x0
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS \
+					+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
+
+#define CONFIG_FSL_QIXIS	/* use common QIXIS code */
+#define QIXIS_BASE			0xffdf0000
+#define QIXIS_LBMAP_SWITCH		6
+#define QIXIS_LBMAP_MASK		0x0f
+#define QIXIS_LBMAP_SHIFT		0
+#define QIXIS_LBMAP_DFLTBANK		0x00
+#define QIXIS_LBMAP_ALTBANK		0x04
+#define QIXIS_RST_CTL_RESET		0x83
+#define QIXIS_RST_FORCE_MEM		0x1
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+#define QIXIS_BRDCFG5			0x55
+#define QIXIS_MUX_SDHC			2
+#define QIXIS_MUX_SDHC_WIDTH8		1
+#define QIXIS_BASE_PHYS		(0xf00000000ull | QIXIS_BASE)
+
+#define CONFIG_SYS_CSPR3_EXT	(0xf)
+#define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 \
+				| CSPR_MSEL_GPCM \
+				| CSPR_V)
+#define CONFIG_SYS_AMASK3	IFC_AMASK(4*1024)
+#define CONFIG_SYS_CSOR3	0x0
+/* QIXIS Timing parameters for IFC CS3 */
+#define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
+					FTIM0_GPCM_TEADC(0x0e) | \
+					FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
+					FTIM1_GPCM_TRAD(0x3f))
+#define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
+					FTIM2_GPCM_TCH(0x0) | \
+					FTIM2_GPCM_TWP(0x1f))
+#define CONFIG_SYS_CS3_FTIM3		0x0
+
+/* NAND Flash on IFC */
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_BASE		0xff800000
+#define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
+
+#define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+
+#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
+				| CSOR_NAND_RAL_3	/* RAL = 2Byes */ \
+				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
+				| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
+				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+					FTIM0_NAND_TWP(0x18)   | \
+					FTIM0_NAND_TWCHT(0x07) | \
+					FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+					FTIM1_NAND_TWBE(0x39)  | \
+					FTIM1_NAND_TRR(0x0e)   | \
+					FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
+					FTIM2_NAND_TREH(0x0a) | \
+					FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3		0x0
+
+#define CONFIG_SYS_NAND_DDR_LAW		11
+
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+#define CONFIG_SYS_NAND_MAX_OOBFREE	2
+#define CONFIG_SYS_NAND_MAX_ECCPOS	256
+
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
+#endif
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+
+/* I2C */
+#define CONFIG_SYS_FSL_I2C_SPEED	100000	/* I2C speed */
+#define CONFIG_SYS_FSL_I2C2_SPEED	100000	/* I2C2 speed */
+#define I2C_MUX_PCA_ADDR_PRI		0x77 /* I2C bus multiplexer,primary */
+#define I2C_MUX_PCA_ADDR_SEC		0x76 /* I2C bus multiplexer,secondary */
+
+#define I2C_MUX_CH_DEFAULT	0x8
+#define I2C_MUX_CH_VOL_MONITOR	0xa
+#define I2C_MUX_CH_VSC3316_FS	0xc
+#define I2C_MUX_CH_VSC3316_BS	0xd
+
+/* Voltage monitor on channel 2*/
+#define I2C_VOL_MONITOR_ADDR		0x40
+#define I2C_VOL_MONITOR_BUS_V_OFFSET	0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF	0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT	3
+
+/* VSC Crossbar switches */
+#define CONFIG_VSC_CROSSBAR
+#define VSC3316_FSM_TX_ADDR	0x70
+#define VSC3316_FSM_RX_ADDR	0x71
+
+/*
+ * RapidIO
+ */
+
+/*
+ * for slave u-boot IMAGE instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000	/* 512K */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
+/*
+ * for slave UCODE and ENV instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000	/* 256K */
+
+/* slave core release by master*/
+#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
+#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
+
+/*
+ * SRIO_PCIE_BOOT - SLAVE
+ */
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
+		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
+#endif
+/*
+ * eSPI - Enhanced SPI
+ */
+#define CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED         10000000
+#define CONFIG_SF_DEFAULT_MODE          0
+
+
+/* Qman/Bman */
+#ifndef CONFIG_NOBQFMAN
+#define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS	50
+#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
+#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
+#define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
+#define CONFIG_SYS_QMAN_NUM_PORTALS	50
+#define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
+#define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
+#define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+#define CONFIG_SYS_PMAN
+#define CONFIG_SYS_DPAA_DCE
+#define CONFIG_SYS_DPAA_RMAN
+#define CONFIG_SYS_INTERLAKEN
+
+/* Default address of microcode for the Linux Fman driver */
+#if defined(CONFIG_SPIFLASH)
+/*
+ * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
+ * env, so we got 0x110000.
+ */
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_FMAN_FW_ADDR	0x110000
+#elif defined(CONFIG_SDCARD)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 1MB (2048 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+#define CONFIG_SYS_FMAN_FW_ADDR	(512 * 0x820)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_FMAN_FW_ADDR	(11 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+/*
+ * Slave has no ucode locally, it can fetch this from remote. When implementing
+ * in two corenet boards, slave's ucode could be stored in master's memory
+ * space, the address can be mapped from slave TLB->slave LAW->
+ * slave SRIO or PCIE outbound window->master inbound window->
+ * master LAW->the ucode address in master's memory space.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
+#define CONFIG_SYS_FMAN_FW_ADDR	0xFFE00000
+#else
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_FMAN_FW_ADDR		0xEFF00000
+#endif
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+#endif /* CONFIG_NOBQFMAN */
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_TERANETICS
+#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
+#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
+#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
+#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
+#define FM1_10GEC1_PHY_ADDR	0x0
+#define FM1_10GEC2_PHY_ADDR	0x1
+#define FM2_10GEC1_PHY_ADDR	0x2
+#define FM2_10GEC2_PHY_ADDR	0x3
+#endif
+
+
+/* SATA */
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
+
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_MII		/* MII PHY management */
+#define CONFIG_ETHPRIME		"FM1@DTSEC1"
+#define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
+#endif
+
+/*
+* USB
+*/
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_CMD_EXT2
+#define CONFIG_HAS_FSL_DR_USB
+
+#define CONFIG_MMC
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#define CONFIG_ESDHC_DETECT_QUIRK \
+	(!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \
+	IS_SVR_REV(get_svr(), 1, 0))
+#define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \
+	(!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8))
+#endif
+
+#define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
+
+#define __USB_PHY_TYPE	utmi
+
+/*
+ * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
+ * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
+ * interleaving. It can be cacheline, page, bank, superbank.
+ * See doc/README.fsl-ddr for details.
+ */
+#ifdef CONFIG_PPC_T4240
+#define CTRL_INTLV_PREFERED 3way_4KB
+#else
+#define CTRL_INTLV_PREFERED cacheline
+#endif
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hwconfig=fsl_ddr:"					\
+	"ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","	\
+	"bank_intlv=auto;"					\
+	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
+	"netdev=eth0\0"						\
+	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
+	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"		\
+	"tftpflash=tftpboot $loadaddr $uboot && "		\
+	"protect off $ubootaddr +$filesize && "			\
+	"erase $ubootaddr +$filesize && "			\
+	"cp.b $loadaddr $ubootaddr $filesize && "		\
+	"protect on $ubootaddr +$filesize && "			\
+	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
+	"consoledev=ttyS0\0"					\
+	"ramdiskaddr=2000000\0"					\
+	"ramdiskfile=t4240qds/ramdisk.uboot\0"			\
+	"fdtaddr=c00000\0"					\
+	"fdtfile=t4240qds/t4240qds.dtb\0"				\
+	"bdev=sda3\0"						\
+	"c=ffe\0"
+
+#define CONFIG_HVBOOT				\
+	"setenv bootargs config-addr=0x60000000; "	\
+	"bootm 0x01000000 - 0x00f00000"
+
+#define CONFIG_ALU				\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"cpu 1 release 0x01000000 - - -;"		\
+	"cpu 2 release 0x01000000 - - -;"		\
+	"cpu 3 release 0x01000000 - - -;"		\
+	"cpu 4 release 0x01000000 - - -;"		\
+	"cpu 5 release 0x01000000 - - -;"		\
+	"cpu 6 release 0x01000000 - - -;"		\
+	"cpu 7 release 0x01000000 - - -;"		\
+	"go 0x01000000"
+
+#define CONFIG_LINUX				\
+	"setenv bootargs root=/dev/ram rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"setenv ramdiskaddr 0x02000000;"		\
+	"setenv fdtaddr 0x00c00000;"			\
+	"setenv loadaddr 0x1000000;"			\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_HDBOOT					\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND			\
+	"setenv bootargs root=/dev/nfs rw "	\
+	"nfsroot=$serverip:$rootpath "		\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"		\
+	"tftp $fdtaddr $fdtfile;"		\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND				\
+	"setenv bootargs root=/dev/ram rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $ramdiskaddr $ramdiskfile;"		\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_LINUX
+
+#include <asm/fsl_secure_boot.h>
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/T4240RDB.h b/qemu/roms/u-boot/include/configs/T4240RDB.h
new file mode 100644
index 000000000..b1a8053a5
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/T4240RDB.h
@@ -0,0 +1,752 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * T4240 RDB board configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_T4240RDB
+#define CONFIG_PHYS_64BIT
+
+#define CONFIG_FSL_SATA_V2
+#define CONFIG_PCIE4
+
+#define CONFIG_ICS307_REFCLK_HZ		25000000  /* ICS307 ref clk freq */
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
+#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_rcw.cfg
+#endif
+
+#define CONFIG_DDR_ECC
+
+#define CONFIG_CMD_REGINFO
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE
+#define CONFIG_E500			/* BOOKE e500 family */
+#define CONFIG_E500MC			/* BOOKE e500mc family */
+#define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
+#define CONFIG_MP			/* support multiple processors */
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xeff40000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+#define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC		CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_FSL_IFC			/* Enable IFC Support */
+#define CONFIG_PCI			/* Enable PCI/PCIE */
+#define CONFIG_PCIE1			/* PCIE controler 1 */
+#define CONFIG_PCIE2			/* PCIE controler 2 */
+#define CONFIG_PCIE3			/* PCIE controler 3 */
+#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
+
+#define CONFIG_FSL_LAW			/* Use common FSL init code */
+
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BTB			/* toggle branch predition */
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#endif
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP		64	/* number of TLB1 entries */
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_PANIC_HANG	/* do not reset board on panic */
+
+/*
+ *  Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR		CONFIG_RAMBOOT_TEXT_BASE
+
+#define CONFIG_SYS_DCSRBAR		0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	4
+#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
+
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_FSL_DDR3
+
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE	0xe0000000
+#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe0ec000
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x118100
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 2, Slot 2, tgtid 2, Base address 201000 */
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 3, Slot 1, tgtid 1, Base address 202000 */
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0xc0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc40000000ull
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 4, Base address 203000 */
+#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_PHYS	0xc60000000ull
+#define CONFIG_SYS_PCIE4_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
+#define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+#define CONFIG_E1000
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif	/* CONFIG_PCI */
+
+/* SATA */
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
+
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_MII		/* MII PHY management */
+#define CONFIG_ETHPRIME		"FM1@DTSEC1"
+#define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ERRATA
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	"u-boot.bin"	/* U-Boot image on TFTP server*/
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+
+#define CONFIG_BAUDRATE	115200
+
+#define CONFIG_HVBOOT					\
+	"setenv bootargs config-addr=0x60000000; "	\
+	"bootm 0x01000000 - 0x00f00000"
+
+#ifdef CONFIG_SYS_NO_FLASH
+#ifndef CONFIG_RAMBOOT_PBL
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+#else
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#endif
+
+#if defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS              0
+#define CONFIG_ENV_SPI_CS               0
+#define CONFIG_ENV_SPI_MAX_HZ           10000000
+#define CONFIG_ENV_SPI_MODE             0
+#define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
+#define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
+#define CONFIG_ENV_SECT_SIZE            0x10000
+#elif defined(CONFIG_SDCARD)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV          0
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_OFFSET		(512 * 1658)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE			CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET		(7 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_ENV_IS_NOWHERE)
+#define CONFIG_ENV_SIZE		0x2000
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+#endif
+
+#define CONFIG_SYS_CLK_FREQ	66666666
+#define CONFIG_DDR_CLK_FREQ	133333333
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_SPD_BUS_NUM	0
+#define SPD_EEPROM_ADDRESS1	0x52
+#define SPD_EEPROM_ADDRESS2	0x54
+#define SPD_EEPROM_ADDRESS3	0x56
+#define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1	/* for p3041/p5010 */
+#define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+				+ 0x8000000) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR1_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80
+
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
+				FTIM0_NOR_TEADC(0x5) | \
+				FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
+				FTIM1_NOR_TRAD_NOR(0x1A) |\
+				FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
+				FTIM2_NOR_TCH(0x4) | \
+				FTIM2_NOR_TWPH(0x0E) | \
+				FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3	0x0
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS \
+					+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
+
+/* NAND Flash on IFC */
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_MAX_ECCPOS	256
+#define CONFIG_SYS_NAND_MAX_OOBFREE	2
+#define CONFIG_SYS_NAND_BASE		0xff800000
+#define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
+
+#define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+
+#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
+				| CSOR_NAND_RAL_3	/* RAL = 2Byes */ \
+				| CSOR_NAND_PGS_4K	/* Page Size = 4K */ \
+				| CSOR_NAND_SPRZ_224	/* Spare size = 224 */ \
+				| CSOR_NAND_PB(128))	/*Page Per Block = 128*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+					FTIM0_NAND_TWP(0x18)   | \
+					FTIM0_NAND_TWCHT(0x07) | \
+					FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+					FTIM1_NAND_TWBE(0x39)  | \
+					FTIM1_NAND_TRR(0x0e)   | \
+					FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
+					FTIM2_NAND_TREH(0x0a) | \
+					FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3		0x0
+
+#define CONFIG_SYS_NAND_DDR_LAW		11
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(512 * 1024)
+
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
+#endif
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+
+/* I2C */
+#define CONFIG_SYS_FSL_I2C_SPEED	100000	/* I2C speed */
+#define CONFIG_SYS_FSL_I2C2_SPEED	100000	/* I2C2 speed */
+#define I2C_MUX_PCA_ADDR_PRI		0x77 /* I2C bus multiplexer,primary */
+#define I2C_MUX_PCA_ADDR_SEC		0x76 /* I2C bus multiplexer,secondary */
+
+#define I2C_MUX_CH_DEFAULT	0x8
+#define I2C_MUX_CH_VOL_MONITOR	0xa
+#define I2C_MUX_CH_VSC3316_FS	0xc
+#define I2C_MUX_CH_VSC3316_BS	0xd
+
+/* Voltage monitor on channel 2*/
+#define I2C_VOL_MONITOR_ADDR		0x40
+#define I2C_VOL_MONITOR_BUS_V_OFFSET	0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF	0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT	3
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#define CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED         10000000
+#define CONFIG_SF_DEFAULT_MODE          0
+
+
+/* Qman/Bman */
+#ifndef CONFIG_NOBQFMAN
+#define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS	50
+#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
+#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
+#define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
+#define CONFIG_SYS_QMAN_NUM_PORTALS	50
+#define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
+#define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
+#define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+#define CONFIG_SYS_PMAN
+#define CONFIG_SYS_DPAA_DCE
+#define CONFIG_SYS_DPAA_RMAN
+#define CONFIG_SYS_INTERLAKEN
+
+/* Default address of microcode for the Linux Fman driver */
+#if defined(CONFIG_SPIFLASH)
+/*
+ * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
+ * env, so we got 0x110000.
+ */
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_FMAN_FW_ADDR	0x110000
+#elif defined(CONFIG_SDCARD)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 825KB (1650 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+#define CONFIG_SYS_FMAN_FW_ADDR	(512 * 1680)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_FMAN_FW_ADDR	(8 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#else
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_FMAN_FW_ADDR	0xEFF00000
+#endif
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+#endif /* CONFIG_NOBQFMAN */
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_CORTINA
+#define CONFIG_CORTINA_FW_ADDR		0xefe00000
+#define CONFIG_CORTINA_FW_LENGTH	0x40000
+#define CONFIG_PHY_TERANETICS
+#define SGMII_PHY_ADDR1 0x0
+#define SGMII_PHY_ADDR2 0x1
+#define SGMII_PHY_ADDR3 0x2
+#define SGMII_PHY_ADDR4 0x3
+#define SGMII_PHY_ADDR5 0x4
+#define SGMII_PHY_ADDR6 0x5
+#define SGMII_PHY_ADDR7 0x6
+#define SGMII_PHY_ADDR8 0x7
+#define FM1_10GEC1_PHY_ADDR	0x10
+#define FM1_10GEC2_PHY_ADDR	0x11
+#define FM2_10GEC1_PHY_ADDR	0x12
+#define FM2_10GEC2_PHY_ADDR	0x13
+#define CORTINA_PHY_ADDR1	FM1_10GEC1_PHY_ADDR
+#define CORTINA_PHY_ADDR2	FM1_10GEC2_PHY_ADDR
+#define CORTINA_PHY_ADDR3	FM2_10GEC1_PHY_ADDR
+#define CORTINA_PHY_ADDR4	FM2_10GEC2_PHY_ADDR
+#endif
+
+
+/* SATA */
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
+
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_MII		/* MII PHY management */
+#define CONFIG_ETHPRIME		"FM1@DTSEC1"
+#define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
+#endif
+
+/*
+* USB
+*/
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_CMD_EXT2
+#define CONFIG_HAS_FSL_DR_USB
+
+#define CONFIG_MMC
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+#define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
+
+#define __USB_PHY_TYPE	utmi
+
+/*
+ * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
+ * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
+ * interleaving. It can be cacheline, page, bank, superbank.
+ * See doc/README.fsl-ddr for details.
+ */
+#define CTRL_INTLV_PREFERED 3way_4KB
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hwconfig=fsl_ddr:"					\
+	"ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","	\
+	"bank_intlv=auto;"					\
+	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
+	"netdev=eth0\0"						\
+	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
+	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
+	"tftpflash=tftpboot $loadaddr $uboot && "		\
+	"protect off $ubootaddr +$filesize && "			\
+	"erase $ubootaddr +$filesize && "			\
+	"cp.b $loadaddr $ubootaddr $filesize && "		\
+	"protect on $ubootaddr +$filesize && "			\
+	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
+	"consoledev=ttyS0\0"					\
+	"ramdiskaddr=2000000\0"					\
+	"ramdiskfile=t4240rdb/ramdisk.uboot\0"			\
+	"fdtaddr=c00000\0"					\
+	"fdtfile=t4240rdb/t4240rdb.dtb\0"			\
+	"bdev=sda3\0"
+
+#define CONFIG_HVBOOT					\
+	"setenv bootargs config-addr=0x60000000; "	\
+	"bootm 0x01000000 - 0x00f00000"
+
+#define CONFIG_LINUX					\
+	"setenv bootargs root=/dev/ram rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"setenv ramdiskaddr 0x02000000;"		\
+	"setenv fdtaddr 0x00c00000;"			\
+	"setenv loadaddr 0x1000000;"			\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_HDBOOT					\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND			\
+	"setenv bootargs root=/dev/nfs rw "	\
+	"nfsroot=$serverip:$rootpath "		\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"		\
+	"tftp $fdtaddr $fdtfile;"		\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND				\
+	"setenv bootargs root=/dev/ram rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $ramdiskaddr $ramdiskfile;"		\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_LINUX
+
+#include <asm/fsl_secure_boot.h>
+
+#ifdef CONFIG_SECURE_BOOT
+/* Secure Boot target was not getting build for T4240 because of
+ * increased binary size. So the size is being reduced by removing USB
+ * which is anyways not used in Secure Environment.
+ */
+#undef CONFIG_CMD_USB
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/TASREG.h b/qemu/roms/u-boot/include/configs/TASREG.h
new file mode 100644
index 000000000..5ad938362
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/TASREG.h
@@ -0,0 +1,287 @@
+/*
+ * Configuation settings for the esd TASREG board.
+ *
+ * (C) Copyright 2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _TASREG_H
+#define _TASREG_H
+
+#ifndef __ASSEMBLY__
+#include <asm/m5249.h>
+#endif
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MCF52x2			/* define processor family */
+#define CONFIG_M5249			/* define processor type */
+
+#define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
+
+#define CONFIG_MCFTMR
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT		(0)
+#define CONFIG_BAUDRATE		19200
+
+#undef  CONFIG_WATCHDOG
+
+#undef CONFIG_MONITOR_IS_IN_RAM	              /* no pre-loader required!!! ;-) */
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+
+#undef CONFIG_CMD_NET
+
+
+#define CONFIG_BOOTDELAY	3
+
+#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
+#define CONFIG_LOOPW            1       /* enable loopw command         */
+#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
+
+#define CONFIG_SYS_LOAD_ADDR	        0x200000	/* default load address */
+
+#define CONFIG_SYS_MEMTEST_START	0x400
+#define CONFIG_SYS_MEMTEST_END		0x380000
+
+/*
+ * Clock configuration: enable only one of the following options
+ */
+
+#if 0 /* this setting will run the cpu at 11MHz */
+#define CONFIG_SYS_PLL_BYPASS          1                /* bypass PLL for test purpose */
+#undef  CONFIG_SYS_FAST_CLK                             /* MCF5249 can run at 140MHz   */
+#define CONFIG_SYS_CLK		        11289600         /* PLL bypass                  */
+#endif
+
+#if 0 /* this setting will run the cpu at 70MHz */
+#undef  CONFIG_SYS_PLL_BYPASS                           /* bypass PLL for test purpose */
+#undef  CONFIG_SYS_FAST_CLK                             /* MCF5249 can run at 140MHz   */
+#define CONFIG_SYS_CLK		        72185018         /* The next lower speed        */
+#endif
+
+#if 1 /* this setting will run the cpu at 140MHz */
+#undef  CONFIG_SYS_PLL_BYPASS                           /* bypass PLL for test purpose */
+#define CONFIG_SYS_FAST_CLK            1                /* MCF5249 can run at 140MHz   */
+#define	CONFIG_SYS_CLK		        132025600        /* MCF5249 can run at 140MHz   */
+#endif
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+#define CONFIG_SYS_MBAR		0x10000000	/* Register Base Addrs */
+#define	CONFIG_SYS_MBAR2	        0x80000000
+
+/*-----------------------------------------------------------------------
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED	100000
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0x7F
+
+#if 0 /* push-pull */
+#define	SDA	        0x00800000
+#define	SCL	        0x00000008
+#define DIR0            *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_EN))
+#define DIR1            *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_EN))
+#define OUT0	        *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_OUT))
+#define OUT1	        *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_OUT))
+#define IN0	        *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_READ))
+#define IN1	        *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_READ))
+#define	I2C_INIT	{OUT1|=SDA;OUT0|=SCL;}
+#define	I2C_READ	((IN1&SDA)?1:0)
+#define	I2C_SDA(x)	{if(x)OUT1|=SDA;else OUT1&=~SDA;}
+#define	I2C_SCL(x)	{if(x)OUT0|=SCL;else OUT0&=~SCL;}
+#define	I2C_DELAY	{udelay(5);}
+#define	I2C_ACTIVE	{DIR1|=SDA;}
+#define	I2C_TRISTATE    {DIR1&=~SDA;}
+#else /* open-collector */
+#define	SDA	        0x00800000
+#define	SCL	        0x00000008
+#define DIR0            *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_EN))
+#define DIR1            *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_EN))
+#define OUT0	        *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_OUT))
+#define OUT1	        *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_OUT))
+#define IN0	        *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_READ))
+#define IN1	        *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_READ))
+#define	I2C_INIT	{DIR1&=~SDA;DIR0&=~SCL;OUT1&=~SDA;OUT0&=~SCL;}
+#define	I2C_READ	((IN1&SDA)?1:0)
+#define	I2C_SDA(x)	{if(x)DIR1&=~SDA;else DIR1|=SDA;}
+#define	I2C_SCL(x)	{if(x)DIR0&=~SCL;else DIR0|=SCL;}
+#define	I2C_DELAY	{udelay(5);}
+#define	I2C_ACTIVE	{DIR1|=SDA;}
+#define	I2C_TRISTATE    {DIR1&=~SDA;}
+#endif
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC32	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2	/* Bytes of address	*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x01
+/*
+ * The Catalyst CAT24WC32 has 32 byte page write mode using
+ * last 5 bits of the address
+ */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in internal SRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_ADDR		0xFFC40000	/* Address of Environment Sector*/
+#define CONFIG_ENV_SIZE		0x10000	/* Total Size of Environment Sector	*/
+#define CONFIG_ENV_SECT_SIZE	0x10000 /* see README - env sector total size	*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_SIZE		16		/* SDRAM size in MB */
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
+
+#if 0 /* test-only */
+#define CONFIG_PRAM             512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
+#endif
+
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
+
+#define CONFIG_SYS_MONITOR_LEN		0x20000
+#define CONFIG_SYS_MALLOC_LEN		(1 * 1024*1024)	/* Reserve 1 MB for malloc()	*/
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16
+
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_DCM)
+#define CONFIG_SYS_CACHE_ACR1		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CEIB | \
+					 CF_CACR_DBWE)
+
+/*-----------------------------------------------------------------------
+ * Memory bank definitions
+ */
+
+/* CS0 - AMD Flash, address 0xffc00000 */
+#define	CONFIG_SYS_CS0_BASE		0xffc00000
+#define	CONFIG_SYS_CS0_CTRL		0x00001980	/* WS=0110, AA=1, PS=10         */
+/** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/
+#define	CONFIG_SYS_CS0_MASK		0x003f0021	/* 4MB, AA=0, WP=0, C/I=1, V=1  */
+
+/* CS1 - FPGA, address 0xe0000000 */
+#define	CONFIG_SYS_CS1_BASE		0xe0000000
+#define	CONFIG_SYS_CS1_CTRL		0x00000d80	/* WS=0011, AA=1, PS=10         */
+#define	CONFIG_SYS_CS1_MASK		0x00010001	/* 128kB, AA=0, WP=0, C/I=0, V=1*/
+
+/*-----------------------------------------------------------------------
+ * Port configuration
+ */
+#define	CONFIG_SYS_GPIO_FUNC           0x00000008      /* Set gpio pins: none          */
+#define	CONFIG_SYS_GPIO1_FUNC          0x00df00f0      /* 36-39(SWITCH),48-52(FPGAs),54*/
+#define	CONFIG_SYS_GPIO_EN             0x00000008      /* Set gpio output enable       */
+#define	CONFIG_SYS_GPIO1_EN            0x00c70000      /* Set gpio output enable       */
+#define	CONFIG_SYS_GPIO_OUT            0x00000008      /* Set outputs to default state */
+#define	CONFIG_SYS_GPIO1_OUT           0x00c70000      /* Set outputs to default state */
+
+#define CONFIG_SYS_GPIO1_LED           0x00400000      /* user led                     */
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ */
+#define CONFIG_SYS_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
+#define CONFIG_SYS_FPGA_MAX_SIZE	512*1024    /* 512kByte is enough for XC2S200*/
+
+/* FPGA program pin configuration */
+#define CONFIG_SYS_FPGA_PRG		0x00010000  /* FPGA program pin (ppc output) */
+#define CONFIG_SYS_FPGA_CLK		0x00040000  /* FPGA clk pin (ppc output)     */
+#define CONFIG_SYS_FPGA_DATA		0x00020000  /* FPGA data pin (ppc output)    */
+#define CONFIG_SYS_FPGA_INIT		0x00080000  /* FPGA init pin (ppc input)     */
+#define CONFIG_SYS_FPGA_DONE		0x00100000  /* FPGA done pin (ppc input)     */
+
+#endif	/* _TASREG_H */
diff --git a/qemu/roms/u-boot/include/configs/TB5200.h b/qemu/roms/u-boot/include/configs/TB5200.h
new file mode 100644
index 000000000..b4daedcee
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/TB5200.h
@@ -0,0 +1,496 @@
+/*
+ * (C) Copyright 2003-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004-2006
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5200		1	/* This is an MPC5200 CPU */
+#define CONFIG_TQM5200		1	/* ... on TQM5200 module */
+#define CONFIG_TB5200		1	/* ... on a TB5200 base board */
+
+/*
+ * Valid values for CONFIG_SYS_TEXT_BASE are:
+ * 0xFC000000	boot low (standard configuration with room for
+ *		max 64 MByte Flash ROM)
+ * 0xFFF00000	boot high (for a backup copy of U-Boot)
+ * 0x00100000	boot from RAM (for testing only)
+ */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xFC000000
+#endif
+
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
+
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	/* default console is on PSC1 */
+#define CONFIG_PSC_CONSOLE2	6	/* second console is on PSC6 */
+#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*
+ * Video console
+ */
+#if 1
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_SM501
+#define CONFIG_VIDEO_SM501_32BPP
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_CONSOLE_EXTRA_INFO
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#endif
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+/* USB */
+#define CONFIG_USB_OHCI
+#define CONFIG_USB_STORAGE
+
+/* POST support */
+#define CONFIG_POST		(CONFIG_SYS_POST_MEMORY   | \
+				 CONFIG_SYS_POST_CPU	   | \
+				 CONFIG_SYS_POST_I2C)
+
+#ifdef CONFIG_POST
+/* preserve space for the post_word at end of on-chip SRAM */
+#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
+#endif
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_USB
+
+#ifdef CONFIG_VIDEO
+#define CONFIG_CMD_BMP
+#endif
+
+#ifdef CONFIG_POST
+#define CONFIG_CMD_DIAG
+#endif
+
+
+#define	CONFIG_TIMESTAMP		/* display image timestamps */
+
+#if (CONFIG_SYS_TEXT_BASE == 0xFC000000)		/* Boot low */
+#   define CONFIG_SYS_LOWBOOT		1
+#endif
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT	"echo;" \
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#if defined(CONFIG_TQM5200_B)
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"rootpath=/opt/eldk/ppc_6xx\0"					\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"bootfile=/tftpboot/tqm5200/uImage\0"				\
+	"load=tftp 200000 ${u-boot}\0"					\
+	"u-boot=/tftpboot/tqm5200/u-boot.bin\0"				\
+	"update=protect off FC000000 FC07FFFF;"				\
+		"erase FC000000 FC07FFFF;"				\
+		"cp.b 200000 FC000000 ${filesize};"			\
+		"protect on FC000000 FC07FFFF\0"			\
+	""
+#else
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"rootpath=/opt/eldk/ppc_6xx\0"					\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"bootfile=/tftpboot/tqm5200/uImage\0"				\
+	"load=tftp 200000 $(u-boot)\0"					\
+	"u-boot=/tftpboot/tqm5200/u-boot.bin\0"				\
+	"update=protect off FC000000 FC05FFFF;"				\
+		"erase FC000000 FC05FFFF;"				\
+		"cp.b 200000 FC000000 ${filesize};"			\
+		"protect on FC000000 FC05FFFF\0"			\
+	""
+#endif /* CONFIG_TQM5200_B */
+
+#define CONFIG_BOOTCOMMAND	"run net_nfs"
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
+
+#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
+/*
+ * PCI Bus clocking configuration
+ *
+ * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
+ * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
+ * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
+ */
+#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2		/* define for 66MHz speed */
+#endif
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #2 */
+
+/*
+ * I2C clock frequency
+ *
+ * Please notice, that the resulting clock frequency could differ from the
+ * configured value. This is because the I2C clock is derived from system
+ * clock over a frequency divider with only a few divider values. U-boot
+ * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
+ * approximation allways lies below the configured value, never above.
+ */
+#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+
+/*
+ * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
+ * also). For other EEPROMs configuration should be verified. On Mini-FAP the
+ * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
+ * same configuration could be used.
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* =32 Bytes per write */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	20
+
+/* List of I2C addresses to be verified by POST */
+#undef CONFIG_SYS_POST_I2C_ADDRS
+#define CONFIG_SYS_POST_I2C_ADDRS	{CONFIG_SYS_I2C_EEPROM_ADDR,	\
+					 CONFIG_SYS_I2C_RTC_ADDR,	\
+					 CONFIG_SYS_I2C_SLAVE}
+
+/*
+ * Flash configuration
+ */
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_TEXT_BASE /* 0xFC000000 */
+
+/* use CFI flash driver */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_BOOTCS_START }
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_SIZE		0x04000000 /* 64 MByte */
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sects on one chip */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+
+#if !defined(CONFIG_SYS_LOWBOOT)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000)
+#else	/* CONFIG_SYS_LOWBOOT */
+#if defined(CONFIG_TQM5200_B)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00080000)
+#else
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00060000)
+#endif /* CONFIG_TQM5200_B */
+#endif	/* CONFIG_SYS_LOWBOOT */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks
+					   (= chip selects) */
+
+/* Dynamic MTD partition support */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
+#define MTDIDS_DEFAULT		"nor0=TQM5200-0"
+#if defined(CONFIG_TQM5200_B)
+#define MTDPARTS_DEFAULT	"mtdparts=TQM5200-0:768k(firmware),"	\
+						"1280k(kernel),"	\
+						"2m(initrd),"		\
+						"4m(small-fs),"		\
+						"16m(big-fs),"		\
+						"8m(misc)"
+#else
+#define MTDPARTS_DEFAULT	"mtdparts=TQM5200-0:640k(firmware),"	\
+						"1408k(kernel),"	\
+						"2m(initrd),"		\
+						"4m(small-fs),"		\
+						"16m(big-fs),"		\
+						"8m(misc)"
+#endif /* CONFIG_TQM5200_B */
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_SIZE		0x10000
+#if defined(CONFIG_TQM5200_B)
+#define CONFIG_ENV_SECT_SIZE	0x40000
+#else
+#define CONFIG_ENV_SECT_SIZE	0x20000
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+#endif /* CONFIG_TQM5200_B */
+
+/*
+ * Memory map
+ */
+#define CONFIG_SYS_MBAR		0xF0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
+
+/* Use ON-Chip SRAM until RAM will be available */
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+#ifdef CONFIG_POST
+/* preserve space for the post_word at end of on-chip SRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_POST_SIZE
+#else
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
+#endif
+
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
+#endif
+
+#if defined(CONFIG_TQM5200_B)
+#define CONFIG_SYS_MONITOR_LEN		(512 << 10)	/* Reserve 512 kB for Monitor	*/
+#else
+#define CONFIG_SYS_MONITOR_LEN		(384 << 10)	/* Reserve 384 kB for Monitor	*/
+#endif /* CONFIG_TQM5200_B */
+#define CONFIG_SYS_MALLOC_LEN		(1024 << 10)	/* Reserve 1024 kB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC	1
+#define CONFIG_MPC5xxx_FEC_MII100
+/*
+ * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
+ */
+/* #define CONFIG_MPC5xxx_FEC_MII10 */
+#define CONFIG_PHY_ADDR		0x00
+
+/*
+ * GPIO configuration
+ *
+ * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
+ *	Bit 0 (mask: 0x80000000): 1
+ * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
+ *	00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
+ *	01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
+ *	      Use for REV200 STK52XX boards. Do not use with REV100 modules
+ *	      (because, there I2C1 is used as I2C bus)
+ * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
+ * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
+ *	000 -> All PSC2 pins are GIOPs
+ *	001 -> CAN1/2 on PSC2 pins
+ *	       Use for REV100 STK52xx boards
+ * use PSC3: Bits 20:23 (mask: 0x00000300):
+ *      0001 -> USB2
+ *      0000 -> GPIO
+ * use PSC6:
+ *   on STK52xx:
+ *	use as UART. Pins PSC6_0 to PSC6_3 are used.
+ *	Bits 9:11 (mask: 0x00700000):
+ *	   101 -> PSC6 : Extended POST test is not available
+ *   on MINI-FAP and TQM5200_IB:
+ *	use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
+ *	   000 -> PSC6 could not be used as UART, CODEC or IrDA
+ *   GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
+ *   tests.
+ */
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x81500114
+
+/*
+ * RTC configuration
+ */
+#define CONFIG_RTC_M41T11	1
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR	1900    /* because Linux uses the same base
+					   year */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/* Enable an alternate, more extensive memory test */
+#define CONFIG_SYS_ALT_MEMTEST
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
+
+/*
+ * Enable loopw command.
+ */
+#define CONFIG_LOOPW
+
+/*
+ * Various low-level settings
+ */
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
+
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
+#define CONFIG_SYS_BOOTCS_CFG		0x0008DF30 /* for pci_clk  = 66 MHz */
+#else
+#define CONFIG_SYS_BOOTCS_CFG		0x0004DF30 /* for pci_clk = 33 MHz */
+#endif
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
+
+#define CONFIG_LAST_STAGE_INIT
+
+/*
+ * SRAM - Do not map below 2 GB in address space, because this area is used
+ * for SDRAM autosizing.
+ */
+#define CONFIG_SYS_CS2_START		0xE5000000
+#define CONFIG_SYS_CS2_SIZE		0x100000	/* 1 MByte */
+#define CONFIG_SYS_CS2_CFG		0x0004D930
+
+/*
+ * Grafic controller - Do not map below 2 GB in address space, because this
+ * area is used for SDRAM autosizing.
+ */
+#define SM501_FB_BASE		0xE0000000
+#define CONFIG_SYS_CS1_START		(SM501_FB_BASE)
+#define CONFIG_SYS_CS1_SIZE		0x4000000	/* 64 MByte */
+#define CONFIG_SYS_CS1_CFG		0x8F48FF70
+#define SM501_MMIO_BASE		CONFIG_SYS_CS1_START + 0x03E00000
+
+#define CONFIG_SYS_CS_BURST		0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE	0x33333311	/* 1 dead cycle for flash and SM501 */
+
+#define CONFIG_SYS_RESET_ADDRESS	0xff000000
+
+/*-----------------------------------------------------------------------
+ * USB stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_USB_CLOCK	0x0001BBBB
+#define CONFIG_USB_CONFIG	0x00001000
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+
+#undef	CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card Adapter */
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
+#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
+
+#define CONFIG_IDE_RESET		/* reset for ide supported	*/
+#define CONFIG_IDE_PREINIT
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	2	/* max. 2 drives per IDE bus	*/
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
+
+/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
+
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)
+
+/* Interval between registers						     */
+#define CONFIG_SYS_ATA_STRIDE		4
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/TK885D.h b/qemu/roms/u-boot/include/configs/TK885D.h
new file mode 100644
index 000000000..5e1c52d85
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/TK885D.h
@@ -0,0 +1,490 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2006
+ * Martin Krause, TQ-Systems GmBH, martin.krause@tqs.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC885		1	/* This is a MPC885 CPU		*/
+#define CONFIG_TQM885D		1	/* ...on a TQM88D module	*/
+#define CONFIG_TK885D		1	/* ...in a TK885D base board	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0x40000000
+
+#define CONFIG_8xx_OSCLK		10000000	/*  10 MHz - PLL input clock	*/
+#define CONFIG_SYS_8xx_CPUCLK_MIN		15000000	/*  15 MHz - CPU minimum clock	*/
+#define CONFIG_SYS_8xx_CPUCLK_MAX		133000000	/* 133 MHz - CPU maximum clock	*/
+#define CONFIG_8xx_CPUCLK_DEFAULT	66000000	/*  66 MHz - CPU default clock	*/
+						/* (it will be used if there is no	*/
+						/* 'cpuclk' variable with valid value)	*/
+
+#define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#define CONFIG_SYS_SMC_RXBUFLEN	128
+#define CONFIG_SYS_MAXIDLE	10
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+
+#define CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_PREBOOT	"echo;" \
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"ethprime=FEC\0"						\
+	"ethact=FEC\0"							\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_8xx\0"					\
+	"bootfile=/tftpboot/tk885d/uImage\0"				\
+	"u-boot=/tftpboot/tk885d/u-boot.bin\0"				\
+	"kernel_addr=40080000\0"					\
+	"ramdisk_addr=40180000\0"					\
+	"load=tftp 200000 ${u-boot}\0"					\
+	"update=protect off 40000000 +${filesize};"			\
+		"erase 40000000 +${filesize};"				\
+		"cp.b 200000 40000000 ${filesize};"			\
+		"protect on 40000000 +${filesize}\0"			\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+/* enable I2C and select the hardware/software driver */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT			/* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED	93000	/* 93 kHz is supposed to work */
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PB_SCL		0x00000020	/* PB 26 */
+#define PB_SDA		0x00000010	/* PB 27 */
+
+#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
+#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
+#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
+#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
+			else	immr->im_cpm.cp_pbdat &= ~PB_SDA
+#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
+			else	immr->im_cpm.cp_pbdat &= ~PB_SCL
+#define I2C_DELAY	udelay(2)	/* 1/4 I2C clock duration */
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50		/* EEPROM AT24C??	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2		/* two byte address	*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+
+# define CONFIG_RTC_DS1337 1
+# define CONFIG_SYS_I2C_RTC_ADDR 0x68
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#undef CONFIG_RTC_MPC8xx		/* MPC885 does not support RTC	*/
+
+#define	CONFIG_TIMESTAMP		/* but print image timestmps	*/
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0100000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0300000	/* 1 ... 3 MB in DRAM	*/
+#define CONFIG_SYS_ALT_MEMTEST				/* alternate, more extensive
+						   memory test.*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
+
+/*
+ * Enable loopw command.
+ */
+#define CONFIG_LOOPW
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+
+/* use CFI flash driver */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip */
+
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_OFFSET		0x40000 /*   Offset   of Environment Sector	*/
+#define CONFIG_ENV_SIZE		0x08000 /* Total Size of Environment		*/
+#define CONFIG_ENV_SECT_SIZE	0x40000 /* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size	  of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef CONFIG_CAN_DRIVER
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#else	/* we must activate GPL5 in the SIUMCR for CAN */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CONFIG_SYS_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_IDE_PREINIT	1	/* Use preinit IDE hook */
+#define CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card Adapter */
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
+#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_DER 0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/*
+ * FLASH timing: Default value of OR0 after reset
+ */
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
+				 OR_SCY_6_CLK | OR_TRLX)
+
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
+#define SDRAM_MAX_SIZE		(256 << 20)	/* max 256 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
+
+#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#ifndef CONFIG_CAN_DRIVER
+#define CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
+#define CONFIG_SYS_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CONFIG_SYS_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CONFIG_SYS_OR3_CAN		(CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CONFIG_SYS_BR3_CAN		((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
+					BR_PS_8 | BR_MS_UPMB | BR_V )
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*
+ * 4096	Rows from SDRAM example configuration
+ * 1000	factor s -> ms
+ * 64	PTP (pre-divider from MPTPR) from SDRAM example configuration
+ * 4	Number of refresh cycles per period
+ * 64	Refresh cycle in ms per number of rows
+ */
+#define CONFIG_SYS_PTA_PER_CLK	((4096 * 64 * 1000) / (4 * 64))
+
+/*
+ * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad)
+ *
+ *                        CPUclock(MHz) * 31.2
+ * CONFIG_SYS_MAMR_PTA = -----------------------------------     with DFBRG = 0
+ *                2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16
+ *
+ * CPU clock =  15 MHz:  CONFIG_SYS_MAMR_PTA =  29   ->  4 * 7.73 us
+ * CPU clock =  50 MHz:  CONFIG_SYS_MAMR_PTA =  97   ->  4 * 7.76 us
+ * CPU clock =  66 MHz:  CONFIG_SYS_MAMR_PTA = 128   ->  4 * 7.75 us
+ * CPU clock = 133 MHz:  CONFIG_SYS_MAMR_PTA = 255   ->  4 * 7.67 us
+ *
+ * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will
+ * be met also in the default configuration, i.e. if environment variable
+ * 'cpuclk' is not set.
+ */
+#define CONFIG_SYS_MAMR_PTA		128
+
+/*
+ * Memory Periodic Timer Prescaler Register (MPTPR) values.
+ */
+/* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16
+/* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 10 column SDRAM */
+#define CONFIG_SYS_MAMR_10COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9  |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+/*
+ * Network configuration
+ */
+#define CONFIG_FEC_ENET			/* enable ethernet on FEC */
+#define CONFIG_ETHER_ON_FEC1		/* ... for FEC1 */
+#define CONFIG_ETHER_ON_FEC2		/* ... for FEC2 */
+
+#define CONFIG_LAST_STAGE_INIT		1 /* Have to configure PHYs for Linux */
+
+/* CONFIG_SYS_DISCOVER_PHY only works with FEC if only one interface is enabled */
+#if (!defined(CONFIG_ETHER_ON_FEC1) || !defined(CONFIG_ETHER_ON_FEC2))
+#define CONFIG_SYS_DISCOVER_PHY
+#endif
+
+#ifndef CONFIG_SYS_DISCOVER_PHY
+/* PHY addresses - hard wired in hardware */
+#define CONFIG_FEC1_PHY	1
+#define CONFIG_FEC2_PHY	2
+#endif
+
+#define CONFIG_MII_INIT	1
+
+#define CONFIG_NET_RETRY_COUNT	3
+#define CONFIG_ETHPRIME		"FEC"
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_HWCONFIG		1
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/TOP5200.h b/qemu/roms/u-boot/include/configs/TOP5200.h
new file mode 100644
index 000000000..92128b958
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/TOP5200.h
@@ -0,0 +1,402 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * modified for TOP5200-series by Reinhard Meyer, www.emk-elektronik.de
+ *
+ * TOP5200 differences from IceCube:
+ * 1 FLASH Bank for one Chip only, up to 64 MB in 16 MB Banks
+ *   bank switch controlled by TIMER_6(LSB) and TIMER_7(MSB) Pins
+ * 1 SDRAM/DDRAM Bank up to 256 MB
+ * local VPD I2C Bus is software driven and uses
+ *   GPIO_WKUP_6 for SDA, GPIO_WKUP_7 for SCL
+ * FLASH is re-located at 0xff000000
+ * Internal regs are at 0xf0000000
+ * Reset jumps to 0x00000100
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5200		1	/* This is a MPC5200 CPU */
+#define CONFIG_TOP5200		1	/* ... on TOP5200 board - we need this for FEC.C */
+
+/*
+ * allowed and functional CONFIG_SYS_TEXT_BASE values:
+ * 0xff000000	low boot at 0x00000100 (default board setting)
+ * 0xfff00000	high boot at 0xfff00100 (board needs modification)
+ * 0x00100000	RAM load and test
+ */
+#define	CONFIG_SYS_TEXT_BASE	0xff000000
+
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
+
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
+#define CONFIG_BAUDRATE		9600	/* ... at 9600 bps */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+
+#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
+/*
+ * PCI Mapping:
+ * 0x40000000 - 0x4fffffff - PCI Memory
+ * 0x50000000 - 0x50ffffff - PCI IO Space
+ */
+#  define CONFIG_PCI		1
+#  define CONFIG_PCI_PNP		1
+#  define CONFIG_PCI_SCAN_SHOW	1
+#  define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1
+
+#  define CONFIG_PCI_MEM_BUS	0x40000000
+#  define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#  define CONFIG_PCI_MEM_SIZE	0x10000000
+
+#  define CONFIG_PCI_IO_BUS	0x50000000
+#  define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#  define CONFIG_PCI_IO_SIZE	0x01000000
+
+#endif
+
+/* USB */
+#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
+
+#  define CONFIG_USB_OHCI
+#  define CONFIG_USB_CLOCK	0x0001bbbb
+#  if defined (CONFIG_EVAL5200)
+#    define CONFIG_USB_CONFIG	0x00005100
+#  else
+#    define CONFIG_USB_CONFIG	0x00001000
+#  endif
+#  define CONFIG_DOS_PARTITION
+#  define CONFIG_USB_STORAGE
+
+#endif
+
+/* IDE */
+#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
+#  define CONFIG_DOS_PARTITION
+#endif
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_REGINFO
+
+#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_PCI
+#endif
+
+
+/*
+ * MUST be low boot - HIGHBOOT is not supported anymore
+ */
+#if (CONFIG_SYS_TEXT_BASE == 0xFF000000)		/* Boot low with 16 MB Flash */
+#   define CONFIG_SYS_LOWBOOT		1
+#   define CONFIG_SYS_LOWBOOT16	1
+#else
+#   error "CONFIG_SYS_TEXT_BASE must be 0xff000000"
+#endif
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_82xx\0"					\
+	"bootfile=/tftpboot/MPC5200/uImage\0"				\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
+
+/*
+ * I2C configuration
+ */
+/*
+ * EEPROM configuration
+ */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	70
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_EEPROM_SIZE 0x2000
+
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
+
+#if defined(CONFIG_SYS_I2C_SOFT)
+#  define CONFIG_SYS_I2C
+#  define CONFIG_SYS_I2C_SOFT_SPEED	100000
+#  define CONFIG_SYS_I2C_SOFT_SLAVE	0x7F
+/**/
+#  define SDA0			0x40
+#  define SCL0			0x80
+#  define GPIOE0		*((volatile uchar*)(CONFIG_SYS_MBAR+0x0c00))
+#  define DDR0			*((volatile uchar*)(CONFIG_SYS_MBAR+0x0c08))
+#  define DVO0			*((volatile uchar*)(CONFIG_SYS_MBAR+0x0c0c))
+#  define DVI0			*((volatile uchar*)(CONFIG_SYS_MBAR+0x0c20))
+#  define ODE0			*((volatile uchar*)(CONFIG_SYS_MBAR+0x0c04))
+#  define I2C_INIT		{GPIOE0|=(SDA0|SCL0);ODE0|=(SDA0|SCL0);DVO0|=(SDA0|SCL0);DDR0|=(SDA0|SCL0);}
+#  define I2C_READ		((DVI0&SDA0)?1:0)
+#  define I2C_SDA(x)	{if(x)DVO0|=SDA0;else DVO0&=~SDA0;}
+#  define I2C_SCL(x)	{if(x)DVO0|=SCL0;else DVO0&=~SCL0;}
+#  define I2C_DELAY		{udelay(5);}
+#  define I2C_ACTIVE	{DDR0|=SDA0;}
+#  define I2C_TRISTATE	{DDR0&=~SDA0;}
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
+#define CONFIG_SYS_I2C_FACT_ADDR	0x57
+#endif
+
+#if defined (CONFIG_HARD_I2C)
+#  define CONFIG_SYS_I2C_MODULE	2		/* Select I2C module #1 or #2 */
+#  define CONFIG_SYS_I2C_SPEED		100000	/* 100 kHz */
+#  define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
+#define CONFIG_SYS_I2C_FACT_ADDR	0x54
+#endif
+
+/*
+ * Flash configuration, expect one 16 Megabyte Bank at most
+ */
+#define CONFIG_SYS_FLASH_BASE		0xff000000
+#define CONFIG_SYS_FLASH_SIZE		0x01000000
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0)
+
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max num of sects on one chip */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+
+#undef CONFIG_FLASH_16BIT	/* Flash is 8-bit */
+
+/*
+ * DRAM configuration - will be read from VPD later... TODO!
+ */
+#if 0
+/* 2x MT48LC16M16A2 - 7.0 ns SDRAMS = 64 MegaBytes Total */
+#define	CONFIG_SYS_DRAM_DDR		0
+#define CONFIG_SYS_DRAM_EMODE		0
+#define CONFIG_SYS_DRAM_MODE		0x008D
+#define CONFIG_SYS_DRAM_CONTROL	0x514F0000
+#define CONFIG_SYS_DRAM_CONFIG1	0xC2233A00
+#define CONFIG_SYS_DRAM_CONFIG2	0x88B70004
+#define	CONFIG_SYS_DRAM_TAP_DEL	0x08
+#define CONFIG_SYS_DRAM_RAM_SIZE	0x19
+#endif
+#if 1
+/* 2x MT48LC16M16A2 - 7.5 ns SDRAMS = 64 MegaBytes Total */
+#define	CONFIG_SYS_DRAM_DDR		0
+#define CONFIG_SYS_DRAM_EMODE		0
+#define CONFIG_SYS_DRAM_MODE		0x00CD
+#define CONFIG_SYS_DRAM_CONTROL	0x514F0000
+#define CONFIG_SYS_DRAM_CONFIG1	0xD2333A00
+#define CONFIG_SYS_DRAM_CONFIG2	0x8AD70004
+#define	CONFIG_SYS_DRAM_TAP_DEL	0x08
+#define CONFIG_SYS_DRAM_RAM_SIZE	0x19
+#endif
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_IS_IN_EEPROM	1	/* turn on EEPROM env feature */
+#define CONFIG_ENV_OFFSET		0x1000
+#define CONFIG_ENV_SIZE		0x0700
+
+/*
+ * VPD settings
+ */
+#define CONFIG_SYS_FACT_OFFSET		0x1800
+#define CONFIG_SYS_FACT_SIZE		0x0800
+
+/*
+ * Memory map
+ *
+ * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000
+ */
+#define CONFIG_SYS_MBAR			0xf0000000	/* DO NOT CHANGE this */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
+
+/* Use SRAM until RAM will be available */
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */
+
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC	1
+#define CONFIG_MPC5xxx_FEC_MII10	/* Workaround for FEC 100Mbit problem */
+#define	CONFIG_PHY_ADDR		0x1f
+#define	CONFIG_PHY_TYPE		0x79c874
+/*
+ * GPIO configuration:
+ * PSC1,2,3 predefined as UART
+ * PCI disabled
+ * Ethernet 100 with MD
+ */
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x00058044
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#if defined(CONFIG_CMD_KGDB)
+#  define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#  define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x01f00000	/* 1 ... 31 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x200000	/* default load address */
+
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+
+#ifdef CONFIG_EVAL5200		/* M48T08 is available with the Evaluation board only */
+  #define CONFIG_RTC_MK48T59	1	/* use M48T08 on EVAL5200 */
+  #define RTC(reg)		(0xf0010000+reg)
+  /* setup CS2 for M48T08. Must MAP 64kB */
+  #define CONFIG_SYS_CS2_START	RTC(0)
+  #define CONFIG_SYS_CS2_SIZE	0x10000
+  /* setup CS2 configuration register: */
+  /* WaitP = 0, WaitX = 4, MX=0, AL=1, AA=1, CE=1 */
+  /* AS=2, DS=0, Bank=0, WTyp=0, WS=0, RS=0, WO=0, RO=0 */
+  #define CONFIG_SYS_CS2_CFG	0x00047800
+#else
+  #define CONFIG_RTC_MPC5200	1	/* use internal MPC5200 RTC */
+#endif
+
+/*
+ * Various low-level settings
+ */
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
+
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_CFG		0x00047801
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
+
+#define CONFIG_SYS_CS_BURST		0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE	0x33333333
+
+#define CONFIG_SYS_RESET_ADDRESS	0x7f000000
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+
+#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+
+#define CONFIG_IDE_RESET	1
+#define CONFIG_IDE_PREINIT
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
+
+/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
+
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005c)
+
+/* Interval between registers                                                */
+#define CONFIG_SYS_ATA_STRIDE          4
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/TOP860.h b/qemu/roms/u-boot/include/configs/TOP860.h
new file mode 100644
index 000000000..da68503a6
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/TOP860.h
@@ -0,0 +1,409 @@
+/*
+ * (C) Copyright 2003
+ * EMK Elektronik GmbH <www.emk-elektronik.de>
+ * Reinhard Meyer <r.meyer@emk-elektronik.de>
+ *
+ * Configuation settings for the TOP860 board.
+ *
+ * -----------------------------------------------------------------
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/*
+ * TOP860 is a simple module:
+ * 16-bit wide FLASH on CS0	(2MB or more)
+ * 32-bit wide DRAM on CS2 (either 4MB or 16MB)
+ * FEC with Am79C874 100-Base-T and Fiber Optic
+ * Ports available, but we choose SMC1 for Console
+ * 8k I2C EEPROM at address 0xae, 6k user available, 2k factory set
+ * 32768Hz crystal PLL set for 49.152MHz Core and 24.576MHz Bus Clock
+ *
+ * This config has been copied from MBX.h / MBX860T.h
+ */
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+/*-----------------------------------------------------------------------
+ * CPU and BOARD type
+ */
+#define CONFIG_MPC860	1	/* This is a MPC860 CPU		*/
+#define CONFIG_MPC860T	1	/* even better... an FEC!	*/
+#define CONFIG_TOP860	1	/* ...on a TOP860 module	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0x80000000
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+#define	CONFIG_IDENT_STRING " EMK TOP860"
+
+/*-----------------------------------------------------------------------
+ * CLOCK settings
+ */
+#define	CONFIG_SYSCLK	49152000
+#define	CONFIG_SYS_XTAL		32768
+#define	CONFIG_EBDF		1
+#define	CONFIG_COM		3
+#define	CONFIG_RTC_MPC8xx
+
+/*-----------------------------------------------------------------------
+ * Physical memory map as defined by EMK
+ */
+#define CONFIG_SYS_IMMR		0xFFF00000	/* Internal Memory Mapped Register */
+#define	CONFIG_SYS_FLASH_BASE	0x80000000	/* FLASH in final mapping */
+#define	CONFIG_SYS_DRAM_BASE	0x00000000	/* DRAM in final mapping */
+#define	CONFIG_SYS_FLASH_MAX	0x00400000	/* max FLASH to expect */
+#define	CONFIG_SYS_DRAM_MAX	0x01000000	/* max DRAM to expect */
+
+/*-----------------------------------------------------------------------
+ * derived values
+ */
+#define	CONFIG_SYS_MF			(CONFIG_SYSCLK/CONFIG_SYS_XTAL)
+#define	CONFIG_SYS_CPUCLOCK	CONFIG_SYSCLK
+#define	CONFIG_SYS_BRGCLOCK	CONFIG_SYSCLK
+#define	CONFIG_SYS_BUSCLOCK	(CONFIG_SYSCLK >> CONFIG_EBDF)
+#define	CONFIG_8xx_GCLK_FREQ	CONFIG_SYSCLK
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CONFIG_SYS_FLASH_CFI
+
+/*-----------------------------------------------------------------------
+ * Command interpreter
+ */
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#define CONFIG_BAUDRATE		9600
+
+/*
+ * Allow partial commands to be matched to uniqueness.
+ */
+#define CONFIG_SYS_MATCH_PARTIAL_CMD
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_BEDBUG
+
+
+#define	CONFIG_SOURCE			1
+#define	CONFIG_SYS_LOADS_BAUD_CHANGE	1
+#undef	CONFIG_LOADS_ECHO			/* NO echo on for serial download	*/
+
+
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+
+#undef	CONFIG_SYS_HUSH_PARSER			/* Hush parse for U-Boot	*/
+
+
+#if defined(CONFIG_CMD_KGDB)
+ #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+ #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+/*-----------------------------------------------------------------------
+ * Memory Test Command
+ */
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+/*-----------------------------------------------------------------------
+ * Environment handler
+ * only the first 6k in EEPROM are available for user. Of that we use 256b
+ */
+#define CONFIG_ENV_IS_IN_EEPROM	1	/* turn on EEPROM env feature */
+#define CONFIG_ENV_OFFSET		0x1000
+#define CONFIG_ENV_SIZE		0x0700
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
+#define CONFIG_SYS_FACT_OFFSET		0x1800
+#define CONFIG_SYS_FACT_SIZE		0x0800
+#define CONFIG_SYS_I2C_FACT_ADDR	0x57
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_EEPROM_SIZE 0x2000
+#define	CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED	100000
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
+/**/
+#define	SDA	0x00010
+#define	SCL	0x00020
+#define __I2C_DIR	immr->im_cpm.cp_pbdir
+#define __I2C_DAT	immr->im_cpm.cp_pbdat
+#define __I2C_PAR	immr->im_cpm.cp_pbpar
+#define	__I2C_ODR	immr->im_cpm.cp_pbodr
+#define	I2C_INIT	{ __I2C_PAR &= ~(SDA|SCL);	\
+			  __I2C_ODR &= ~(SDA|SCL);	\
+			  __I2C_DAT |= (SDA|SCL);	\
+			  __I2C_DIR|=(SDA|SCL);	}
+#define	I2C_READ	((__I2C_DAT & SDA) ? 1 : 0)
+#define	I2C_SDA(x)	{ if (x) __I2C_DAT |= SDA; else __I2C_DAT &= ~SDA; }
+#define	I2C_SCL(x)	{ if (x) __I2C_DAT |= SCL; else __I2C_DAT &= ~SCL; }
+#define	I2C_DELAY	{ udelay(5); }
+#define	I2C_ACTIVE	{ __I2C_DIR |= SDA; }
+#define	I2C_TRISTATE	{ __I2C_DIR &= ~SDA; }
+
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*-----------------------------------------------------------------------
+ * defines we need to get FEC running
+ */
+#define CONFIG_FEC_ENET		1	/* Ethernet only via FEC	*/
+#define	FEC_ENET		1	/* eth.c needs it that way... */
+#define CONFIG_SYS_DISCOVER_PHY	1
+#define CONFIG_MII		1
+#define CONFIG_MII_INIT		1
+#define CONFIG_PHY_ADDR		31
+
+/*-----------------------------------------------------------------------
+ * adresses
+ */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x80000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2f00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_VPD_SIZE	256 /* size in bytes reserved for vpd buffer */
+#define CONFIG_SYS_INIT_VPD_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_VPD_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_INIT_VPD_OFFSET-8)
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/* Interrupt level assignments.
+*/
+#define FEC_INTERRUPT	SIU_LEVEL1	/* FEC interrupt */
+
+/*-----------------------------------------------------------------------
+ * Debug Enable Register
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_DER 0					/* used in start.S */
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * set up PLPRCR (PLL, Low-Power, and Reset Control Register)
+ *	12	MF		calculated	Multiplication factor
+ *	4	0		0000
+ *	1	SPLSS	0			System PLL lock status sticky
+ *	1	TEXPS	1			Timer expired status
+ *	1	0		0
+ *	1	TMIST	0			Timers interrupt status
+ *	1	0		0
+ *	1	CSRC	0			Clock source (0=DFNH, 1=DFNL)
+ *	2	LPM		00			Low-power modes
+ *	1	CSR		0			Checkstop reset enable
+ *	1	LOLRE	0			Loss-of-lock reset enable
+ *	1	FIOPD	0			Force I/O pull down
+ *	5	0		00000
+ */
+#define CONFIG_SYS_PLPRCR	(PLPRCR_TEXPS | ((CONFIG_SYS_MF-1)<<20))
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * set up SYPCR:
+ *	16	SWTC	0xffff		Software watchdog timer count
+ *	8	BMT		0xff		Bus monitor timing
+ *	1	BME		1			Bus monitor enable
+ *	3	0		000
+ *	1	SWF		1			Software watchdog freeze
+ *	1	SWE		0/1			Software watchdog enable
+ *	1	SWRI	0/1			Software watchdog reset/interrupt select (1=HRESET)
+ *	1	SWP		0/1			Software watchdog prescale (1=/2048)
+ */
+#if defined (CONFIG_WATCHDOG)
+ #define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+					 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+ #define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * set up SIUMCR
+ *	1	EARB	0			External arbitration
+ *	3	EARP	000			External arbitration request priority
+ *	4	0		0000
+ *	1	DSHW	0			Data show cycles
+ *	2	DBGC	00			Debug pin configuration
+ *	2	DBPC	00			Debug port pins configuration
+ *	1	0		0
+ *	1	FRC		0			FRZ pin configuration
+ *	1	DLK		0			Debug register lock
+ *	1	OPAR	0			Odd parity
+ *	1	PNCS	0			Parity enable for non memory controller regions
+ *	1	DPC		0			Data parity pins configuration
+ *	1	MPRE	0			Multiprocessor reservation enable
+ *	2	MLRC	11			Multi level reservation control (00=IRQ4, 01=3State, 10=KR/RETRY, 11=SPKROUT)
+ *	1	AEME	0			Async external master enable
+ *	1	SEME	0			Sync external master enable
+ *	1	BSC		0			Byte strobe configuration
+ *	1	GB5E	0			GPL_B5 enable
+ *	1	B2DD	0			Bank 2 double drive
+ *	1	B3DD	0			Bank 3 double drive
+ *	4	0		0000
+ */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_MLRC11)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF | PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * set up SCCR (System Clock and Reset Control Register)
+ *	1	0		0
+ *	2	COM		11			Clock output module (00=full, 01=half, 11=off)
+ *	3	0		000
+ *	1	TBS		1			Timebase source (0=OSCCLK, 1=GCLK2)
+ *	1	RTDIV	0			Real-time clock divide (0=/4, 1=/512)
+ *	1	RTSEL	0			Real-time clock select (0=OSCM, 1=EXTCLK)
+ *	1	CRQEN	0			CPM request enable
+ *	1	PRQEN	0			Power management request enable
+ *	2	0		00
+ *	2	EBDF	xx			External bus division factor
+ *	2	0		00
+ *	2	DFSYNC	00			Division factor for SYNCLK
+ *	2	DFBRG	00			Division factor for BRGCLK
+ *	3	DFNL	000			Division factor low frequency
+ *	3	DFNH	000			Division factor high frequency
+ *	5	0		00000
+ */
+#define SCCR_MASK	0
+#ifdef CONFIG_EBDF
+ #define CONFIG_SYS_SCCR	(SCCR_COM11 | SCCR_TBS | SCCR_EBDF01)
+#else
+ #define CONFIG_SYS_SCCR	(SCCR_COM11 | SCCR_TBS)
+#endif
+
+/*-----------------------------------------------------------------------
+ * Chip Select 0 - FLASH
+ *-----------------------------------------------------------------------
+ * Preliminary Values
+ */
+/* FLASH timing: CSNT=1 ACS=10 BIH=1 SCY=4 SETA=0 TLRX=1 EHTR=1	*/
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_4_CLK | OR_TRLX | OR_EHTR)
+#define CONFIG_SYS_OR0_PRELIM	(-CONFIG_SYS_FLASH_MAX | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V )
+
+/*-----------------------------------------------------------------------
+ * misc
+ *-----------------------------------------------------------------------
+ *
+ */
+/*
+ * Set the autoboot delay in seconds.  A delay of -1 disables autoboot
+ */
+#define CONFIG_BOOTDELAY				5
+
+/*
+ * Pass the clock frequency to the Linux kernel in units of MHz
+ */
+#define	CONFIG_CLOCKS_IN_MHZ
+
+#define CONFIG_PREBOOT		\
+	"echo;echo"
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND	\
+	"bootp;" \
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
+	"bootm"
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Set default IP stuff just to get bootstrap entries into the
+ * environment so that we can source the full default environment.
+ */
+#define CONFIG_ETHADDR					9a:52:63:15:85:25
+#define CONFIG_SERVERIP					10.0.4.200
+#define CONFIG_IPADDR					10.0.4.111
+
+#define CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/TQM5200.h b/qemu/roms/u-boot/include/configs/TQM5200.h
new file mode 100644
index 000000000..69c0336ca
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/TQM5200.h
@@ -0,0 +1,743 @@
+/*
+ * (C) Copyright 2003-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004-2006
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5200		1	/* This is an MPC5200 CPU		*/
+#define CONFIG_TQM5200		1	/* ... on TQM5200 module		*/
+#undef CONFIG_TQM5200_REV100		/*  define for revision 100 modules	*/
+
+/*
+ * Valid values for CONFIG_SYS_TEXT_BASE are:
+ * 0xFC000000	boot low (standard configuration with room for
+ *		max 64 MByte Flash ROM)
+ * 0xFFF00000	boot high (for a backup copy of U-Boot)
+ * 0x00100000	boot from RAM (for testing only)
+ */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xFC000000
+#endif
+
+/* On a Cameron or on a FO300 board or ...				*/
+#if !defined(CONFIG_CAM5200) && !defined(CONFIG_CHARON) \
+	&& !defined(CONFIG_FO300)
+#define CONFIG_STK52XX		1	/* ... on a STK52XX board		*/
+#endif
+
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz		*/
+
+#define CONFIG_HIGH_BATS	1	/* High BATs supported			*/
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1			*/
+#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps			*/
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_BOOTCOUNT_LIMIT	1
+
+#ifdef CONFIG_FO300
+#define CONFIG_SYS_DEVICE_NULLDEV		1	/* enable null device */
+#define CONFIG_SILENT_CONSOLE		1	/* enable silent startup */
+#define CONFIG_BOARD_EARLY_INIT_F	1	/* used to detect S1 switch position */
+#define CONFIG_USB_BIN_FIXUP		1	/* for a buggy USB device */
+#if 0
+#define FO300_SILENT_CONSOLE_WHEN_S1_CLOSED	1	/* silent console on PSC1 when S1 */
+							/* switch is closed */
+#endif
+
+#undef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED		/* silent console on PSC1 when S1 */
+							/* switch is open */
+#endif	/* CONFIG_FO300 */
+
+#if defined(CONFIG_CHARON) || defined(CONFIG_STK52XX)
+#define CONFIG_PS2KBD			/* AT-PS/2 Keyboard		*/
+#define CONFIG_PS2MULT			/* .. on PS/2 Multiplexer	*/
+#define CONFIG_PS2SERIAL	6	/* .. on PSC6			*/
+#define CONFIG_PS2MULT_DELAY	(CONFIG_SYS_HZ/2)	/* Initial delay	*/
+#define CONFIG_BOARD_EARLY_INIT_R
+#endif /* CONFIG_STK52XX */
+
+/*
+ * PCI Mapping:
+ * 0x40000000 - 0x4fffffff - PCI Memory
+ * 0x50000000 - 0x50ffffff - PCI IO Space
+ */
+#if defined(CONFIG_CHARON) || defined(CONFIG_STK52XX)
+#define CONFIG_PCI		1
+#define CONFIG_PCI_PNP		1
+/* #define CONFIG_PCI_SCAN_SHOW	1 */
+
+#define CONFIG_PCI_MEM_BUS	0x40000000
+#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE	0x10000000
+
+#define CONFIG_PCI_IO_BUS	0x50000000
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0x01000000
+
+#define CONFIG_EEPRO100		1
+#define CONFIG_SYS_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
+#define CONFIG_NS8382X		1
+#endif	/* CONFIG_STK52XX */
+
+/*
+ * Video console
+ */
+#ifndef CONFIG_TQM5200S		/* No graphics controller on TQM5200S */
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_SM501
+#define CONFIG_VIDEO_SM501_32BPP
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_LOGO
+
+#ifndef CONFIG_FO300
+#define CONFIG_CONSOLE_EXTRA_INFO
+#else
+#define CONFIG_VIDEO_BMP_LOGO
+#endif
+
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#endif /* #ifndef CONFIG_TQM5200S */
+
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+/* USB */
+#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
+    defined(CONFIG_STK52XX)
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_OHCI_BE_CONTROLLER
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_USB
+
+#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE	MPC5XXX_USB
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"mpc5200"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
+
+#endif
+
+#ifndef CONFIG_CAM5200
+/* POST support */
+#define CONFIG_POST		(CONFIG_SYS_POST_MEMORY   | \
+				 CONFIG_SYS_POST_CPU	   | \
+				 CONFIG_SYS_POST_I2C)
+#endif
+
+#ifdef CONFIG_POST
+/* preserve space for the post_word at end of on-chip SRAM */
+#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
+#endif
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_BSP
+
+#ifdef CONFIG_VIDEO
+    #define CONFIG_CMD_BMP
+#endif
+
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1
+#endif
+
+#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
+	defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX)
+    #define CONFIG_CMD_IDE
+    #define CONFIG_CMD_FAT
+    #define CONFIG_CMD_EXT2
+#endif
+
+#if defined(CONFIG_CHARON) || defined(CONFIG_FO300) || \
+	defined(CONFIG_STK52XX)
+    #define CONFIG_CFG_USB
+    #define CONFIG_CFG_FAT
+#endif
+
+#ifdef CONFIG_POST
+    #define CONFIG_CMD_DIAG
+#endif
+
+
+#define	CONFIG_TIMESTAMP		/* display image timestamps */
+
+#if (CONFIG_SYS_TEXT_BASE != 0xFFF00000)
+#   define CONFIG_SYS_LOWBOOT		1	/* Boot low */
+#endif
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT	"echo;" \
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#if defined(CONFIG_TQM5200_B) && !defined(CONFIG_SYS_LOWBOOT)
+# define ENV_UPDT							\
+	"update=protect off FFF00000 +${filesize};"			\
+		"erase FFF00000 +${filesize};"				\
+		"cp.b 200000 FFF00000 ${filesize};"			\
+		"protect on FFF00000 +${filesize}\0"
+#else	/* default lowboot configuration */
+#   define ENV_UPDT							\
+	"update=protect off FC000000 +${filesize};"			\
+		"erase FC000000 +${filesize};"				\
+		"cp.b 200000 FC000000 ${filesize};"			\
+		"protect on FC000000 +${filesize}\0"
+#endif
+
+#if defined(CONFIG_TQM5200)
+#define CUSTOM_ENV_SETTINGS						\
+	"hostname=tqm5200\0"						\
+	"bootfile=/tftpboot/tqm5200/uImage\0"				\
+	"fdt_file=/tftpboot/tqm5200/tqm5200.dtb\0"			\
+	"u-boot=/tftpboot/tqm5200/u-boot.bin\0"
+#elif defined(CONFIG_CAM5200)
+#define CUSTOM_ENV_SETTINGS						\
+	"bootfile=cam5200/uImage\0"					\
+	"u-boot=cam5200/u-boot.bin\0"					\
+	"setup=tftp 200000 cam5200/setup.img; source 200000\0"
+#endif
+
+#if defined(CONFIG_TQM5200_B)
+#define ENV_FLASH_LAYOUT						\
+	"fdt_addr=FC100000\0"						\
+	"kernel_addr=FC140000\0"					\
+	"ramdisk_addr=FC600000\0"
+#elif defined(CONFIG_CHARON)
+#define ENV_FLASH_LAYOUT						\
+	"fdt_addr=FDFC0000\0"						\
+	"kernel_addr=FC0A0000\0"					\
+	"ramdisk_addr=FC200000\0"
+#else	/* !CONFIG_TQM5200_B */
+#define ENV_FLASH_LAYOUT						\
+	"fdt_addr=FC0A0000\0"						\
+	"kernel_addr=FC0C0000\0"					\
+	"ramdisk_addr=FC300000\0"
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"console=ttyPSC0\0"						\
+	ENV_FLASH_LAYOUT						\
+	"kernel_addr_r=400000\0"					\
+	"fdt_addr_r=600000\0"						\
+	"rootpath=/opt/eldk/ppc_6xx\0"					\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addcons=setenv bootargs ${bootargs} "				\
+		"console=${console},${baudrate}\0"			\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
+	"flash_self_old=sete console ttyS0; "				\
+		"run ramargs addip addcons addmtd; "			\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"flash_self=run ramargs addip addcons;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
+	"flash_nfs_old=sete console ttyS0; run nfsargs addip addcons;"	\
+		"bootm ${kernel_addr}\0"				\
+	"flash_nfs=run nfsargs addip addcons;"				\
+		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
+	"net_nfs_old=tftp ${kernel_addr_r} ${bootfile};"		\
+		"sete console ttyS0; run nfsargs addip addcons;bootm\0"	\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
+		"tftp ${fdt_addr_r} ${fdt_file}; "			\
+		"run nfsargs addip addcons addmtd; "			\
+		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
+	CUSTOM_ENV_SETTINGS						\
+	"load=tftp 200000 ${u-boot}\0"					\
+	ENV_UPDT							\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run net_nfs"
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
+
+#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) && !defined(CONFIG_CAM5200)
+/*
+ * PCI Bus clocking configuration
+ *
+ * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
+ * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock of
+ * 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
+ */
+#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2	/* define for 66MHz speed */
+#endif
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+#ifdef CONFIG_TQM5200_REV100
+#define CONFIG_SYS_I2C_MODULE		1	/* Select I2C module #1 for rev. 100 board */
+#else
+#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #2 for all other revs */
+#endif
+
+/*
+ * I2C clock frequency
+ *
+ * Please notice, that the resulting clock frequency could differ from the
+ * configured value. This is because the I2C clock is derived from system
+ * clock over a frequency divider with only a few divider values. U-boot
+ * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
+ * approximation allways lies below the configured value, never above.
+ */
+#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+
+/*
+ * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
+ * also). For other EEPROMs configuration should be verified. On Mini-FAP the
+ * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
+ * same configuration could be used.
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* =32 Bytes per write */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	20
+
+/*
+ * HW-Monitor configuration on Mini-FAP
+ */
+#if defined (CONFIG_MINIFAP)
+#define CONFIG_SYS_I2C_HWMON_ADDR		0x2C
+#endif
+
+/* List of I2C addresses to be verified by POST */
+#if defined (CONFIG_MINIFAP)
+#undef CONFIG_SYS_POST_I2C_ADDRS
+#define CONFIG_SYS_POST_I2C_ADDRS	{CONFIG_SYS_I2C_EEPROM_ADDR,	\
+					 CONFIG_SYS_I2C_HWMON_ADDR,	\
+					 CONFIG_SYS_I2C_SLAVE}
+#endif
+
+/*
+ * Flash configuration
+ */
+#define CONFIG_SYS_FLASH_BASE		0xFC000000
+
+#if defined(CONFIG_CAM5200) && defined(CONFIG_CAM5200_NIOSFLASH)
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max num of flash banks
+					   (= chip selects) */
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned int /* main flash device with */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
+
+#define CONFIG_SYS_FLASH_ADDR0		0x555
+#define CONFIG_SYS_FLASH_ADDR1		0x2AA
+#define CONFIG_SYS_FLASH_2ND_16BIT_DEV	1	/* NIOS flash is a 16bit device */
+#define CONFIG_SYS_MAX_FLASH_SECT	128
+#else
+/* use CFI flash driver */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
+#define CONFIG_FLASH_CFI_MTD		/* with MTD support */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_BOOTCS_START }
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks
+					   (= chip selects) */
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sects on one chip */
+#endif
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_SIZE		0x04000000 /* 64 MByte */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+
+#if defined (CONFIG_CAM5200)
+# define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00040000)
+#elif defined(CONFIG_TQM5200_B)
+# define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00080000)
+#else
+# define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00060000)
+#endif
+
+/* Dynamic MTD partition support */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define MTDIDS_DEFAULT		"nor0=fc000000.flash"
+
+#if defined(CONFIG_STK52XX)
+# if defined(CONFIG_TQM5200_B)
+#  if defined(CONFIG_SYS_LOWBOOT)
+#   define MTDPARTS_DEFAULT	"mtdparts=fc000000.flash:1m(firmware),"	\
+						"256k(dtb),"		\
+						"2304k(kernel),"	\
+						"2560k(small-fs),"	\
+						"2m(initrd),"		\
+						"8m(misc),"		\
+						"16m(big-fs)"
+#  else	/* highboot */
+#   define MTDPARTS_DEFAULT	"mtdparts=fc000000.flash:2560k(kernel),"\
+						"3584k(small-fs),"	\
+						"2m(initrd),"		\
+						"8m(misc),"		\
+						"15m(big-fs),"		\
+						"1m(firmware)"
+#  endif /* CONFIG_SYS_LOWBOOT */
+# else	/* !CONFIG_TQM5200_B */
+#   define MTDPARTS_DEFAULT	"mtdparts=fc000000.flash:640k(firmware),"\
+						"128k(dtb),"		\
+						"2304k(kernel),"	\
+						"2m(initrd),"		\
+						"4m(small-fs),"		\
+						"8m(misc),"		\
+						"15m(big-fs)"
+# endif /* CONFIG_TQM5200_B */
+#elif defined (CONFIG_CAM5200)
+#   define MTDPARTS_DEFAULT	"mtdparts=fc000000.flash:768k(firmware),"\
+						"1792k(kernel),"	\
+						"5632k(rootfs),"	\
+						"24m(home)"
+#elif defined (CONFIG_CHARON)
+#   define MTDPARTS_DEFAULT	"mtdparts=fc000000.flash:640k(firmware),"\
+						"1408k(kernel),"	\
+						"2m(initrd),"		\
+						"4m(small-fs),"		\
+						"24320k(big-fs),"	\
+						"256k(dts)"
+#elif defined (CONFIG_FO300)
+#   define MTDPARTS_DEFAULT	"mtdparts=fc000000.flash:640k(firmware),"\
+						"1408k(kernel),"	\
+						"2m(initrd),"		\
+						"4m(small-fs),"		\
+						"8m(misc),"		\
+						"16m(big-fs)"
+#else
+# error "Unknown Carrier Board"
+#endif	/* CONFIG_STK52XX */
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_SIZE		0x4000	/* 16 k - keep small for fast booting */
+#if defined(CONFIG_TQM5200_B) || defined (CONFIG_CAM5200)
+#define CONFIG_ENV_SECT_SIZE	0x40000
+#else
+#define CONFIG_ENV_SECT_SIZE	0x20000
+#endif /* CONFIG_TQM5200_B */
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+/*
+ * Memory map
+ */
+#define CONFIG_SYS_MBAR		0xF0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
+
+/* Use ON-Chip SRAM until RAM will be available */
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+#ifdef CONFIG_POST
+/* preserve space for the post_word at end of on-chip SRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_POST_SIZE
+#else
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
+#endif
+
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
+#endif
+
+#if defined (CONFIG_CAM5200)
+# define CONFIG_SYS_MONITOR_LEN	(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#elif defined(CONFIG_TQM5200_B)
+# define CONFIG_SYS_MONITOR_LEN	(512 << 10)	/* Reserve 512 kB for Monitor	*/
+#else
+# define CONFIG_SYS_MONITOR_LEN	(384 << 10)	/* Reserve 384 kB for Monitor	*/
+#endif
+
+#define CONFIG_SYS_MALLOC_LEN		(1024 << 10)	/* Reserve 1024 kB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC	1
+#define CONFIG_MPC5xxx_FEC_MII100
+/*
+ * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
+ */
+/* #define CONFIG_MPC5xxx_FEC_MII10 */
+#define CONFIG_PHY_ADDR		0x00
+
+/*
+ * GPIO configuration
+ *
+ * use CS1: Bit 0 (mask: 0x80000000):
+ *	   1 -> Pin gpio_wkup_6 as second SDRAM chip select (mem_cs1).
+ * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
+ *	  00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
+ *		SPI on PSC3 according to PSC3 setting. Use for CAM5200.
+ *	  01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
+ *		Use for REV200 STK52XX boards and FO300 boards. Do not use
+ *		with REV100 modules (because, there I2C1 is used as I2C bus).
+ * use ATA: Bits 6-7 (mask 0x03000000):
+ *	  00 -> No ATA chip selects, csb_4/5 used as normal chip selects.
+ *		Use for CAM5200 board.
+ *	  01 -> ATA cs0/1 on csb_4/5. Use for the remaining boards.
+ * use PSC6: Bits 9-11 (mask 0x00700000):
+ *	 000 -> use PSC6_0 to PSC6_3 as GPIO, PSC6 could not be used as
+ *		UART, CODEC or IrDA.
+ *		GPIO on PSC6_3 is used in post_hotkeys_pressed() to
+ *		enable extended POST tests.
+ *		Use for MINI-FAP and TQM5200_IB boards.
+ *	 101 -> use PSC6 as UART. Pins PSC6_0 to PSC6_3 are used.
+ *		Extended POST test is not available.
+ *		Use for STK52xx, FO300 and CAM5200 boards.
+ *		WARNING: When the extended POST is enabled, these bits will
+ *			 be overridden by this code as GPIOs!
+ * use PCI_DIS: Bit 16 (mask 0x00008000):
+ *	   1 -> disable PCI controller (on CAM5200 board).
+ * use USB: Bits 18-19 (mask 0x00003000):
+ *	  10 -> two UARTs (on FO300 and CAM5200).
+ * use PSC3: Bits 20-23 (mask: 0x00000f00):
+ *	0000 -> All PSC3 pins are GPIOs.
+ *	1100 -> UART/SPI (on FO300 board).
+ *	0100 -> UART (on CAM5200 board).
+ * use PSC2: Bits 25:27 (mask: 0x00000030):
+ *	 000 -> All PSC2 pins are GPIOs.
+ *	 100 -> UART (on CAM5200 board).
+ *	 001 -> CAN1/2 on PSC2 pins.
+ *		Use for REV100 STK52xx boards
+ *	 01x -> Use AC97 (on FO300 board).
+ * use PSC1: Bits 29-31 (mask: 0x00000007):
+ *	 100 -> UART (on all boards).
+ */
+#if !defined(CONFIG_SYS_GPS_PORT_CONFIG)
+#if defined (CONFIG_MINIFAP)
+# define CONFIG_SYS_GPS_PORT_CONFIG	0x91000004
+#elif defined (CONFIG_STK52XX)
+# if defined (CONFIG_STK52XX_REV100)
+#  define CONFIG_SYS_GPS_PORT_CONFIG	0x81500014
+# else /* STK52xx REV200 and above */
+#  if defined (CONFIG_TQM5200_REV100)
+#   error TQM5200 REV100 not supported on STK52XX REV200 or above
+#  else/* TQM5200 REV200 and above */
+#   define CONFIG_SYS_GPS_PORT_CONFIG	0x91500404
+#  endif
+# endif
+#elif defined (CONFIG_FO300)
+# define CONFIG_SYS_GPS_PORT_CONFIG	0x91502c24
+#elif defined (CONFIG_CAM5200)
+# define CONFIG_SYS_GPS_PORT_CONFIG	0x8050A444
+#else  /* TMQ5200 Inbetriebnahme-Board */
+# define CONFIG_SYS_GPS_PORT_CONFIG	0x81000004
+#endif
+#endif
+
+/*
+ * RTC configuration
+ */
+#if defined (CONFIG_STK52XX) && !defined (CONFIG_STK52XX_REV100)
+# define CONFIG_RTC_M41T11 1
+# define CONFIG_SYS_I2C_RTC_ADDR 0x68
+# define CONFIG_SYS_M41T11_BASE_YEAR	1900    /* because Linux uses the same base
+					   year */
+#else
+# define CONFIG_RTC_MPC5200	1	/* use internal MPC5200 RTC */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define	CONFIG_SYS_HUSH_PARSER		1	/* use "hush" command parser	*/
+
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+/* Enable an alternate, more extensive memory test */
+#define CONFIG_SYS_ALT_MEMTEST
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
+
+/*
+ * Enable loopw command.
+ */
+#define CONFIG_LOOPW
+
+/*
+ * Various low-level settings
+ */
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
+
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
+#define CONFIG_SYS_BOOTCS_CFG		0x0008DF30 /* for pci_clk  = 66 MHz */
+#else
+#define CONFIG_SYS_BOOTCS_CFG		0x0004DF30 /* for pci_clk = 33 MHz */
+#endif
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
+
+#define CONFIG_LAST_STAGE_INIT
+
+/*
+ * SRAM - Do not map below 2 GB in address space, because this area is used
+ * for SDRAM autosizing.
+ */
+#define CONFIG_SYS_CS2_START		0xE5000000
+#define CONFIG_SYS_CS2_SIZE		0x100000	/* 1 MByte */
+#define CONFIG_SYS_CS2_CFG		0x0004D930
+
+/*
+ * Grafic controller - Do not map below 2 GB in address space, because this
+ * area is used for SDRAM autosizing.
+ */
+#define SM501_FB_BASE		0xE0000000
+#define CONFIG_SYS_CS1_START		(SM501_FB_BASE)
+#define CONFIG_SYS_CS1_SIZE		0x4000000	/* 64 MByte */
+#define CONFIG_SYS_CS1_CFG		0x8F48FF70
+#define SM501_MMIO_BASE		CONFIG_SYS_CS1_START + 0x03E00000
+
+#define CONFIG_SYS_CS_BURST		0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE	0x33333311	/* 1 dead cycle for flash and SM501 */
+
+#if defined(CONFIG_CAM5200)
+#define CONFIG_SYS_CS4_START		0xB0000000
+#define CONFIG_SYS_CS4_SIZE		0x00010000
+#define CONFIG_SYS_CS4_CFG		0x01019C10
+
+#define CONFIG_SYS_CS5_START		0xD0000000
+#define CONFIG_SYS_CS5_SIZE		0x01208000
+#define CONFIG_SYS_CS5_CFG		0x1414BF10
+#endif
+
+#define CONFIG_SYS_RESET_ADDRESS	0xff000000
+
+/*-----------------------------------------------------------------------
+ * USB stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_USB_CLOCK	0x0001BBBB
+#define CONFIG_USB_CONFIG	0x00001000
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+
+#undef	CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card Adapter */
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
+#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
+
+#define CONFIG_IDE_RESET		/* reset for ide supported	*/
+#define CONFIG_IDE_PREINIT
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	2	/* max. 2 drives per IDE bus	*/
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
+
+/* Offset for data I/O */
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
+
+/* Offset for normal register accesses */
+#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers */
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)
+
+/* Interval between registers */
+#define CONFIG_SYS_ATA_STRIDE		4
+
+/* Support ATAPI devices */
+#define CONFIG_ATAPI			1
+
+/*-----------------------------------------------------------------------
+ * Open firmware flat tree support
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+#define OF_CPU			"PowerPC,5200@0"
+#define OF_SOC			"soc5200@f0000000"
+#define OF_TBCLK		(bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH		"/soc5200@f0000000/serial@2000"
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/TQM823L.h b/qemu/roms/u-boot/include/configs/TQM823L.h
new file mode 100644
index 000000000..cc2204586
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/TQM823L.h
@@ -0,0 +1,468 @@
+/*
+ * (C) Copyright 2000-2008
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC823		1	/* This is a MPC823 CPU		*/
+#define CONFIG_TQM823L		1	/* ...on a TQM8xxL module	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0x40000000
+
+#ifdef	CONFIG_LCD			/* with LCD controller ?	*/
+#define CONFIG_MPC8XX_LCD
+#define CONFIG_LCD_LOGO		1	/* print our logo on the LCD	*/
+#define CONFIG_LCD_INFO		1	/* ... and some board info	*/
+#define	CONFIG_SPLASH_SCREEN		/* ... with splashscreen support*/
+#endif
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#define CONFIG_SYS_SMC_RXBUFLEN	128
+#define CONFIG_SYS_MAXIDLE	10
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+
+#define	CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_8xx\0"					\
+	"hostname=TQM823L\0"						\
+	"bootfile=TQM823L/uImage\0"					\
+	"fdt_addr=40040000\0"						\
+	"kernel_addr=40060000\0"					\
+	"ramdisk_addr=40200000\0"					\
+	"u-boot=TQM823L/u-image.bin\0"					\
+	"load=tftp 200000 ${u-boot}\0"					\
+	"update=prot off 40000000 +${filesize};"			\
+		"era 40000000 +${filesize};"				\
+		"cp.b 200000 40000000 ${filesize};"			\
+		"sete filesize;save\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#if defined(CONFIG_LCD)
+# undef	 CONFIG_STATUS_LED		/* disturbs display		*/
+#else
+# define CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+#endif	/* CONFIG_LCD */
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
+#ifdef	CONFIG_SPLASH_SCREEN
+    #define CONFIG_CMD_BMP
+#endif
+
+
+#define CONFIG_NETCONSOLE
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#else
+#define	CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
+#endif
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+
+/* use CFI flash driver */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	71	/* max number of sectors on one chip */
+
+#define	CONFIG_ENV_IS_IN_FLASH	1
+#define	CONFIG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
+#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+
+#define CONFIG_MISC_INIT_R		/* Make sure to remap flashes correctly */
+
+/*-----------------------------------------------------------------------
+ * Dynamic MTD partition support
+ */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
+#define MTDIDS_DEFAULT		"nor0=TQM8xxL-0"
+
+#define MTDPARTS_DEFAULT	"mtdparts=TQM8xxL-0:256k(u-boot),"	\
+						"128k(dtb),"		\
+						"1664k(kernel),"	\
+						"2m(rootfs),"		\
+						"4m(data)"
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef	CONFIG_CAN_DRIVER
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#else	/* we must activate GPL5 in the SIUMCR for CAN */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ */
+#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CONFIG_SYS_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_IDE_PREINIT	1	/* Use preinit IDE hook */
+#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
+
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
+#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
+
+#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#ifndef	CONFIG_CAN_DRIVER
+#define	CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
+#define	CONFIG_SYS_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CONFIG_SYS_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CONFIG_SYS_OR3_CAN		(CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CONFIG_SYS_BR3_CAN		((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
+					BR_PS_8 | BR_MS_UPMB | BR_V )
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ *	gclk	  CPU clock (not bus clock!)
+ *	Trefresh  Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096  Rows from SDRAM example configuration
+ * 1000  factor s -> ms
+ *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
+ *    4  Number of refresh cycles per period
+ *   64  Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ * 50 MHz => 50.000.000 / Divider =  98
+ * 66 Mhz => 66.000.000 / Divider = 129
+ * 80 Mhz => 80.000.000 / Divider = 156
+ */
+
+#define CONFIG_SYS_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CONFIG_SYS_MAMR_PTA	98
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ */
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_HWCONFIG		1
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/TQM823M.h b/qemu/roms/u-boot/include/configs/TQM823M.h
new file mode 100644
index 000000000..4fd070f27
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/TQM823M.h
@@ -0,0 +1,464 @@
+/*
+ * (C) Copyright 2000-2008
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC823		1	/* This is a MPC823 CPU		*/
+#define CONFIG_TQM823M		1	/* ...on a TQM8xxM module	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0x40000000
+
+#ifdef	CONFIG_LCD			/* with LCD controller ?	*/
+#define CONFIG_MPC8XX_LCD
+/* #define CONFIG_NEC_NL6448BC20 1 / * use NEC NL6448BC20 display	*/
+#endif
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#define CONFIG_SYS_SMC_RXBUFLEN	128
+#define CONFIG_SYS_MAXIDLE	10
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+
+#define	CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_8xx\0"					\
+	"hostname=TQM823M\0"						\
+	"bootfile=TQM823M/uImage\0"					\
+	"fdt_addr=40080000\0"						\
+	"kernel_addr=400A0000\0"					\
+	"ramdisk_addr=40280000\0"					\
+	"u-boot=TQM823M/u-image.bin\0"					\
+	"load=tftp 200000 ${u-boot}\0"					\
+	"update=prot off 40000000 +${filesize};"			\
+		"era 40000000 +${filesize};"				\
+		"cp.b 200000 40000000 ${filesize};"			\
+		"sete filesize;save\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#ifdef CONFIG_LCD
+# undef	 CONFIG_STATUS_LED		/* disturbs display		*/
+#else
+# define CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+#endif	/* CONFIG_LCD */
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
+
+#define CONFIG_NETCONSOLE
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#else
+#define	CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
+#endif
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+
+/* use CFI flash driver */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip */
+
+#define	CONFIG_ENV_IS_IN_FLASH	1
+#define	CONFIG_ENV_OFFSET		0x40000	/*   Offset   of Environment Sector	*/
+#define	CONFIG_ENV_SIZE		0x08000	/* Total Size of Environment		*/
+#define	CONFIG_ENV_SECT_SIZE	0x20000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+
+#define CONFIG_MISC_INIT_R		/* Make sure to remap flashes correctly */
+
+/*-----------------------------------------------------------------------
+ * Dynamic MTD partition support
+ */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
+#define MTDIDS_DEFAULT		"nor0=TQM8xxM-0"
+
+#define MTDPARTS_DEFAULT	"mtdparts=TQM8xxM-0:512k(u-boot),"	\
+						"128k(dtb),"		\
+						"1920k(kernel),"	\
+						"5632(rootfs),"		\
+						"4m(data)"
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef	CONFIG_CAN_DRIVER
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#else	/* we must activate GPL5 in the SIUMCR for CAN */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ */
+#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CONFIG_SYS_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_IDE_PREINIT	1	/* Use preinit IDE hook */
+#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
+
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
+#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
+
+#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#ifndef	CONFIG_CAN_DRIVER
+#define	CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
+#define	CONFIG_SYS_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CONFIG_SYS_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CONFIG_SYS_OR3_CAN		(CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CONFIG_SYS_BR3_CAN		((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
+					BR_PS_8 | BR_MS_UPMB | BR_V )
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ *	gclk	  CPU clock (not bus clock!)
+ *	Trefresh  Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096  Rows from SDRAM example configuration
+ * 1000  factor s -> ms
+ *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
+ *    4  Number of refresh cycles per period
+ *   64  Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ * 50 MHz => 50.000.000 / Divider =  98
+ * 66 Mhz => 66.000.000 / Divider = 129
+ * 80 Mhz => 80.000.000 / Divider = 156
+ */
+
+#define CONFIG_SYS_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CONFIG_SYS_MAMR_PTA	98
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ */
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_HWCONFIG		1
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/TQM8260.h b/qemu/roms/u-boot/include/configs/TQM8260.h
new file mode 100644
index 000000000..7fd12d3fb
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/TQM8260.h
@@ -0,0 +1,620 @@
+/*
+ * (C) Copyright 2001-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Imported from global configuration:
+ *	CONFIG_MPC8255
+ *	CONFIG_MPC8265
+ *	CONFIG_200MHz
+ *	CONFIG_266MHz
+ *	CONFIG_300MHz
+ *	CONFIG_L2_CACHE
+ *	CONFIG_BUSMODE_60x
+ */
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define	CONFIG_SYS_TEXT_BASE	0x40000000
+
+
+#if 0
+#define CONFIG_TQM8260		100	/* ...on a TQM8260 module Rev.100	*/
+#else
+#define CONFIG_TQM8260		200	/* ...on a TQM8260 module Rev.200	*/
+#endif
+
+#define CONFIG_CPM2		1	/* Has a CPM2 */
+
+#define CONFIG_82xx_CONS_SMC1	1	/* console on SMC1			*/
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define	CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_6xx\0"					\
+	"bootfile=tqm8260/uImage\0"				\
+	"kernel_addr=400C0000\0"					\
+	"ramdisk_addr=40240000\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+/* enable I2C and select the hardware/software driver */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED	400000
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0x7F
+
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+
+/* TQM8260 Rev.100 has the clock and data pins swapped (!!!) on EEPROM */
+#if (CONFIG_TQM8260 <= 100)
+
+#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
+#define I2C_ACTIVE	(iop->pdir |=  0x00020000)
+#define I2C_TRISTATE	(iop->pdir &= ~0x00020000)
+#define I2C_READ	((iop->pdat & 0x00020000) != 0)
+#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00020000; \
+			else    iop->pdat &= ~0x00020000
+#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00010000; \
+			else    iop->pdat &= ~0x00010000
+#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
+
+#else
+
+#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
+#define I2C_ACTIVE	(iop->pdir |=  0x00010000)
+#define I2C_TRISTATE	(iop->pdir &= ~0x00010000)
+#define I2C_READ	((iop->pdat & 0x00010000) != 0)
+#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00010000; \
+			else    iop->pdat &= ~0x00010000
+#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00020000; \
+			else    iop->pdat &= ~0x00020000
+#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
+#endif
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+
+#define CONFIG_I2C_X
+
+/*
+ * select serial console configuration
+ *
+ * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ *
+ * if CONFIG_CONS_NONE is defined, then the serial console routines must
+ * defined elsewhere (for example, on the cogent platform, there are serial
+ * ports on the motherboard which are used for the serial console - see
+ * cogent/cma101/serial.[ch]).
+ */
+#define CONFIG_CONS_ON_SMC		/* define if console on SMC */
+#undef  CONFIG_CONS_ON_SCC		/* define if console on SCC */
+#undef  CONFIG_CONS_NONE		/* define if console on something else*/
+#ifdef CONFIG_82xx_CONS_SMC1
+#define CONFIG_CONS_INDEX	1	/* which serial channel for console */
+#endif
+#ifdef CONFIG_82xx_CONS_SMC2
+#define CONFIG_CONS_INDEX	2	/* which serial channel for console */
+#endif
+
+#undef  CONFIG_CONS_USE_EXTC		/* SMC/SCC use ext clock not brg_clk */
+#define CONFIG_CONS_EXTC_RATE	3686400	/* SMC/SCC ext clk rate in Hz */
+#define CONFIG_CONS_EXTC_PINSEL	0	/* pin select 0=CLK3/CLK9 */
+
+/*
+ * select ethernet configuration
+ *
+ * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
+ * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
+ * for FCC)
+ *
+ * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
+ *
+ * (On TQM8260 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the
+ * X.29 connector, and FCC2 is hardwired to the X.1 connector)
+ */
+#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC       */
+#define	CONFIG_ETHER_ON_FCC		/* define if ether on FCC       */
+#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
+#define	CONFIG_ETHER_INDEX    2		/* which SCC/FCC channel for ethernet */
+
+#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
+
+/*
+ *  - RX clk is CLK11
+ *  - TX clk is CLK12
+ */
+# define CONFIG_SYS_CMXSCR_VALUE1	(CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
+
+#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
+
+/*
+ * - Rx-CLK is CLK13
+ * - Tx-CLK is CLK14
+ * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
+ * - Enable Full Duplex in FSMR
+ */
+# define CONFIG_SYS_CMXFCR_MASK2	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
+# define CONFIG_SYS_CPMFCR_RAMTYPE	0
+# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+
+#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
+
+
+/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
+#if defined(CONFIG_MPC8255) || defined(CONFIG_MPC8265)
+#  define CONFIG_8260_CLKIN	66666666	/* in Hz */
+#else	/* !CONFIG_MPC8255 && !CONFIG_MPC8265 */
+# ifndef CONFIG_300MHz
+#  define CONFIG_8260_CLKIN	66666666	/* in Hz */
+# else
+#  define CONFIG_8260_CLKIN	83333000	/* in Hz */
+# endif
+#endif	/* CONFIG_MPC8255 */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address	*/
+
+#define	CONFIG_SYS_RESET_ADDRESS 0xFFFFFFFC	/* "bad" address		*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
+
+
+/* What should the base address of the main FLASH be and how big is
+ * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/tqm8260/config.mk
+ * The main FLASH is whichever is connected to *CS0.
+ */
+#define CONFIG_SYS_FLASH0_BASE 0x40000000
+#define CONFIG_SYS_FLASH1_BASE 0x60000000
+#define CONFIG_SYS_FLASH0_SIZE 32
+#define CONFIG_SYS_FLASH1_SIZE 32
+
+/* Flash bank size (for preliminary settings)
+ */
+#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+
+/* use CFI flash driver */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_FLASH_CFI_DRIVER		1	/* Use the common driver */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_FLASH_EMPTY_INFO	1
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
+
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x40000)
+#define CONFIG_ENV_SIZE		0x08000
+#define CONFIG_ENV_SECT_SIZE	0x40000
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * Hard Reset Configuration Words
+ *
+ * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
+ * defines for the various registers affected by the HRCW e.g. changing
+ * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
+ */
+#define	__HRCW__ALL__		(HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
+
+#if defined(CONFIG_MPC8255) || defined(CONFIG_MPC8265)
+#  define CONFIG_SYS_HRCW_MASTER	(__HRCW__ALL__ | HRCW_MODCK_H0111)
+#else	/* ! MPC8255 && !MPC8265 */
+# if defined(CONFIG_266MHz)
+#  define CONFIG_SYS_HRCW_MASTER	(__HRCW__ALL__ | HRCW_MODCK_H0111)
+# elif defined(CONFIG_300MHz)
+#  define CONFIG_SYS_HRCW_MASTER	(__HRCW__ALL__ | HRCW_MODCK_H0110)
+# else
+#  define CONFIG_SYS_HRCW_MASTER	(__HRCW__ALL__)
+# endif
+#endif	/* CONFIG_MPC8255 */
+
+/* no slaves so just fill with zeros */
+#define CONFIG_SYS_HRCW_SLAVE1		0
+#define CONFIG_SYS_HRCW_SLAVE2		0
+#define CONFIG_SYS_HRCW_SLAVE3		0
+#define CONFIG_SYS_HRCW_SLAVE4		0
+#define CONFIG_SYS_HRCW_SLAVE5		0
+#define CONFIG_SYS_HRCW_SLAVE6		0
+#define CONFIG_SYS_HRCW_SLAVE7		0
+
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000  /* Size of used area in DPRAM    */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ *
+ * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE, local SDRAM
+ * is mapped at SDRAM_BASE2_PRELIM.
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_FLASH0_BASE
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
+#if defined(CONFIG_CMD_KGDB)
+# define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * HIDx - Hardware Implementation-dependent Registers                    2-11
+ *-----------------------------------------------------------------------
+ * HID0 also contains cache control - initially enable both caches and
+ * invalidate contents, then the final state leaves only the instruction
+ * cache enabled. Note that Power-On and Hard reset invalidate the caches,
+ * but Soft reset does not.
+ *
+ * HID1 has only read-only information - nothing to set.
+ */
+#define CONFIG_SYS_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
+				HID0_IFEM|HID0_ABE)
+#define CONFIG_SYS_HID0_FINAL  (HID0_IFEM|HID0_ABE)
+#define CONFIG_SYS_HID2        0
+
+/*-----------------------------------------------------------------------
+ * RMR - Reset Mode Register                                     5-5
+ *-----------------------------------------------------------------------
+ * turn on Checkstop Reset Enable
+ */
+#define CONFIG_SYS_RMR         RMR_CSRE
+
+/*-----------------------------------------------------------------------
+ * BCR - Bus Configuration                                       4-25
+ *-----------------------------------------------------------------------
+ */
+#ifdef	CONFIG_BUSMODE_60x
+#define CONFIG_SYS_BCR         (BCR_EBM|BCR_L2C|BCR_LETM|\
+			 BCR_NPQM0|BCR_NPQM1|BCR_NPQM2)	/* 60x mode  */
+#else
+#define BCR_APD01	0x10000000
+#define CONFIG_SYS_BCR		(BCR_APD01|BCR_ETM|BCR_LETM)	/* 8260 mode */
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration                             4-31
+ *-----------------------------------------------------------------------
+ */
+#if 0
+#define CONFIG_SYS_SIUMCR      (SIUMCR_DPPC10|SIUMCR_APPC10)
+#else
+#define CONFIG_SYS_SIUMCR      (SIUMCR_DPPC00|SIUMCR_APPC10)
+#endif
+
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control                             4-35
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
+#else
+#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+			 SYPCR_SWRI|SYPCR_SWP)
+#endif /* CONFIG_WATCHDOG */
+
+/*-----------------------------------------------------------------------
+ * TMCNTSC - Time Counter Status and Control                     4-40
+ *-----------------------------------------------------------------------
+ * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
+ * and enable Time Counter
+ */
+#define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control                 4-42
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
+ * Periodic timer
+ */
+#define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control                                   9-8
+ *-----------------------------------------------------------------------
+ * Ensure DFBRG is Divide by 16
+ */
+#define CONFIG_SYS_SCCR        0
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration                         13-7
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RCCR        0
+
+/*
+ * Init Memory Controller:
+ *
+ * Bank Bus     Machine PortSz  Device
+ * ---- ---     ------- ------  ------
+ *  0   60x     GPCM    64 bit  FLASH
+ *  1   60x     SDRAM   64 bit  SDRAM
+ *  2   Local   SDRAM   32 bit  SDRAM
+ *
+ */
+
+	/* Initialize SDRAM on local bus
+	 */
+#define CONFIG_SYS_INIT_LOCAL_SDRAM
+
+#define SDRAM_MAX_SIZE	0x08000000	/* max. 128 MB		*/
+
+/* Minimum mask to separate preliminary
+ * address ranges for CS[0:2]
+ */
+#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT	(512<<20)	/* less than 512 MB */
+#define CONFIG_SYS_LOCAL_SDRAM_LIMIT	(128<<20)	/* less than 128 MB */
+
+#define CONFIG_SYS_MPTPR       0x4000
+
+/*-----------------------------------------------------------------------------
+ * Address for Mode Register Set (MRS) command
+ *-----------------------------------------------------------------------------
+ * In fact, the address is rather configuration data presented to the SDRAM on
+ * its address lines. Because the address lines may be mux'ed externally either
+ * for 8 column or 9 column devices, some bits appear twice in the 8260's
+ * address:
+ *
+ * |   (RFU)   |   (RFU)   | WBL |    TM    |     CL    |  BT | Burst Length |
+ * | BA1   BA0 | A12 : A10 |  A9 |  A8   A7 |  A6 : A4  |  A3 |   A2 :  A0   |
+ *  8 columns mux'ing:     |  A9 | A10  A21 | A22 : A24 | A25 |  A26 : A28   |
+ *  9 columns mux'ing:     |  A8 | A20  A21 | A22 : A24 | A25 |  A26 : A28   |
+ *  Settings:              |  0  |  0    0  |  0  1  0  |  0  |   0  1  0    |
+ *-----------------------------------------------------------------------------
+ */
+#define CONFIG_SYS_MRS_OFFS	0x00000110
+
+
+/* Bank 0 - FLASH
+ */
+#define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)  |\
+			 BRx_PS_64                      |\
+			 BRx_MS_GPCM_P                  |\
+			 BRx_V)
+
+#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE)      |\
+			 ORxG_CSNT                      |\
+			 ORxG_ACS_DIV1                  |\
+			 ORxG_SCY_3_CLK                 |\
+			 ORxG_EHTR                      |\
+			 ORxG_TRLX)
+
+	/* SDRAM on TQM8260 can have either 8 or 9 columns.
+	 * The number affects configuration values.
+	 */
+
+/* Bank 1 - 60x bus SDRAM
+ */
+#define CONFIG_SYS_PSRT        0x20
+#define CONFIG_SYS_LSRT        0x20
+#ifndef CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)  |\
+			 BRx_PS_64                      |\
+			 BRx_MS_SDRAM_P                 |\
+			 BRx_V)
+
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR1_8COL
+
+
+	/* SDRAM initialization values for 8-column chips
+	 */
+#define CONFIG_SYS_OR1_8COL    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+			 ORxS_BPD_4                     |\
+			 ORxS_ROWST_PBI1_A7             |\
+			 ORxS_NUMR_12)
+
+#define CONFIG_SYS_PSDMR_8COL  (PSDMR_PBI                      |\
+			 PSDMR_SDAM_A15_IS_A5           |\
+			 PSDMR_BSMA_A12_A14             |\
+			 PSDMR_SDA10_PBI1_A8            |\
+			 PSDMR_RFRC_7_CLK               |\
+			 PSDMR_PRETOACT_2W              |\
+			 PSDMR_ACTTORW_2W               |\
+			 PSDMR_LDOTOPRE_1C              |\
+			 PSDMR_WRC_2C                   |\
+			 PSDMR_EAMUX                    |\
+			 PSDMR_CL_2)
+
+	/* SDRAM initialization values for 9-column chips
+	 */
+#define CONFIG_SYS_OR1_9COL    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+			 ORxS_BPD_4                     |\
+			 ORxS_ROWST_PBI1_A5             |\
+			 ORxS_NUMR_13)
+
+#define CONFIG_SYS_PSDMR_9COL  (PSDMR_PBI                      |\
+			 PSDMR_SDAM_A16_IS_A5           |\
+			 PSDMR_BSMA_A12_A14             |\
+			 PSDMR_SDA10_PBI1_A7            |\
+			 PSDMR_RFRC_7_CLK               |\
+			 PSDMR_PRETOACT_2W              |\
+			 PSDMR_ACTTORW_2W               |\
+			 PSDMR_LDOTOPRE_1C              |\
+			 PSDMR_WRC_2C                   |\
+			 PSDMR_EAMUX                    |\
+			 PSDMR_CL_2)
+
+/* Bank 2 - Local bus SDRAM
+ */
+#ifdef CONFIG_SYS_INIT_LOCAL_SDRAM
+#define CONFIG_SYS_BR2_PRELIM  ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\
+			 BRx_PS_32                      |\
+			 BRx_MS_SDRAM_L                 |\
+			 BRx_V)
+
+#define CONFIG_SYS_OR2_PRELIM	CONFIG_SYS_OR2_8COL
+
+#define SDRAM_BASE2_PRELIM	0x80000000
+
+	/* SDRAM initialization values for 8-column chips
+	 */
+#define CONFIG_SYS_OR2_8COL    ((~(CONFIG_SYS_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+			 ORxS_BPD_4                     |\
+			 ORxS_ROWST_PBI1_A8             |\
+			 ORxS_NUMR_12)
+
+#define CONFIG_SYS_LSDMR_8COL  (PSDMR_PBI                      |\
+			 PSDMR_SDAM_A15_IS_A5           |\
+			 PSDMR_BSMA_A13_A15             |\
+			 PSDMR_SDA10_PBI1_A9            |\
+			 PSDMR_RFRC_7_CLK               |\
+			 PSDMR_PRETOACT_2W              |\
+			 PSDMR_ACTTORW_2W               |\
+			 PSDMR_BL                       |\
+			 PSDMR_LDOTOPRE_1C              |\
+			 PSDMR_WRC_2C                   |\
+			 PSDMR_CL_2)
+
+	/* SDRAM initialization values for 9-column chips
+	 */
+#define CONFIG_SYS_OR2_9COL    ((~(CONFIG_SYS_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+			 ORxS_BPD_4                     |\
+			 ORxS_ROWST_PBI1_A6             |\
+			 ORxS_NUMR_13)
+
+#define CONFIG_SYS_LSDMR_9COL  (PSDMR_PBI                      |\
+			 PSDMR_SDAM_A16_IS_A5           |\
+			 PSDMR_BSMA_A13_A15             |\
+			 PSDMR_SDA10_PBI1_A8            |\
+			 PSDMR_RFRC_7_CLK               |\
+			 PSDMR_PRETOACT_2W              |\
+			 PSDMR_ACTTORW_2W               |\
+			 PSDMR_BL                       |\
+			 PSDMR_LDOTOPRE_1C              |\
+			 PSDMR_WRC_2C                   |\
+			 PSDMR_CL_2)
+
+#endif /* CONFIG_SYS_INIT_LOCAL_SDRAM */
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/TQM8272.h b/qemu/roms/u-boot/include/configs/TQM8272.h
new file mode 100644
index 000000000..9c7e16305
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/TQM8272.h
@@ -0,0 +1,735 @@
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC8272_FAMILY   1
+#define CONFIG_TQM8272		1
+
+#define	CONFIG_SYS_TEXT_BASE	0x40000000
+
+#define	CONFIG_GET_CPU_STR_F	1	/* Get the CPU ID STR */
+#define CONFIG_BOARD_GET_CPU_CLK_F	1 /* Get the CLKIN from board fct */
+
+#define	STK82xx_150		1	/* on a STK82xx.150 */
+
+#define CONFIG_CPM2		1	/* Has a CPM2 */
+
+#define CONFIG_82xx_CONS_SMC1	1	/* console on SMC1		*/
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_BOARD_EARLY_INIT_R	1
+
+#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
+#define CONFIG_BAUDRATE		230400
+#else
+#define CONFIG_BAUDRATE		115200
+#endif
+
+#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"consdev=ttyCPM0\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"hostname=tqm8272\0"						\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addcons=setenv bootargs ${bootargs} "				\
+		"console=$(consdev),$(baudrate)\0"			\
+	"flash_nfs=run nfsargs addip addcons;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip addcons;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 300000 ${bootfile};"				\
+		"run nfsargs addip addcons;bootm\0"			\
+	"rootpath=/opt/eldk/ppc_82xx\0"					\
+	"bootfile=/tftpboot/tqm8272/uImage\0"				\
+	"kernel_addr=40080000\0"					\
+	"ramdisk_addr=40100000\0"					\
+	"load=tftp 300000 /tftpboot/tqm8272/u-boot.bin\0"		\
+	"update=protect off 40000000 4003ffff;era 40000000 4003ffff;"	\
+		"cp.b 300000 40000000 40000;"			        \
+		"setenv filesize;saveenv\0"				\
+	"cphwib=cp.b 4003fc00 33fc00 400\0"				\
+	"upd=run load cphwib update\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_I2C	1
+
+#if CONFIG_I2C
+/* enable I2C and select the hardware/software driver */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED	400000
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0x7F
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
+#define I2C_ACTIVE	(iop->pdir |=  0x00010000)
+#define I2C_TRISTATE	(iop->pdir &= ~0x00010000)
+#define I2C_READ	((iop->pdat & 0x00010000) != 0)
+#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00010000; \
+			else    iop->pdat &= ~0x00010000
+#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00020000; \
+			else    iop->pdat &= ~0x00020000
+#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
+
+#define CONFIG_I2C_X
+
+/* EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+#define CONFIG_SYS_I2C_MULTI_EEPROMS		1	/* more than one eeprom */
+
+/* I2C RTC */
+#define CONFIG_RTC_DS1337		/* Use ds1337 rtc via i2c	*/
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68	/* at address 0x68		*/
+
+/* I2C SYSMON (LM75) */
+#define CONFIG_DTT_LM75		1		/* ON Semi's LM75	*/
+#define CONFIG_DTT_SENSORS	{0}		/* Sensor addresses	*/
+#define CONFIG_SYS_DTT_MAX_TEMP	70
+#define CONFIG_SYS_DTT_LOW_TEMP	-30
+#define CONFIG_SYS_DTT_HYSTERESIS	3
+
+#else
+#undef CONFIG_SYS_I2C
+#undef CONFIG_HARD_I2C
+#undef CONFIG_SYS_I2C_SOFT
+#endif
+
+/*
+ * select serial console configuration
+ *
+ * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ *
+ * if CONFIG_CONS_NONE is defined, then the serial console routines must
+ * defined elsewhere (for example, on the cogent platform, there are serial
+ * ports on the motherboard which are used for the serial console - see
+ * cogent/cma101/serial.[ch]).
+ */
+#define CONFIG_CONS_ON_SMC		/* define if console on SMC */
+#undef  CONFIG_CONS_ON_SCC		/* define if console on SCC */
+#undef  CONFIG_CONS_NONE		/* define if console on something else*/
+#ifdef CONFIG_82xx_CONS_SMC1
+#define CONFIG_CONS_INDEX	1	/* which serial channel for console */
+#endif
+#ifdef CONFIG_82xx_CONS_SMC2
+#define CONFIG_CONS_INDEX	2	/* which serial channel for console */
+#endif
+
+#undef  CONFIG_CONS_USE_EXTC		/* SMC/SCC use ext clock not brg_clk */
+#define CONFIG_CONS_EXTC_RATE	3686400	/* SMC/SCC ext clk rate in Hz */
+#define CONFIG_CONS_EXTC_PINSEL	0	/* pin select 0=CLK3/CLK9 */
+
+/*
+ * select ethernet configuration
+ *
+ * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
+ * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
+ * for FCC)
+ *
+ * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
+ *
+ * (On TQM8272 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the
+ * X.29 connector, and FCC2 is hardwired to the X.1 connector)
+ */
+#define CONFIG_SYS_FCC_ETHERNET
+
+#if defined(CONFIG_SYS_FCC_ETHERNET)
+#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC       */
+#define	CONFIG_ETHER_ON_FCC		/* define if ether on FCC       */
+#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
+#define	CONFIG_ETHER_INDEX    2		/* which SCC/FCC channel for ethernet */
+#else
+#define	CONFIG_ETHER_ON_SCC		/* define if ether on SCC       */
+#undef	CONFIG_ETHER_ON_FCC		/* define if ether on FCC       */
+#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
+#define	CONFIG_ETHER_INDEX    1		/* which SCC/FCC channel for ethernet */
+#endif
+
+#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
+
+/*
+ *  - RX clk is CLK11
+ *  - TX clk is CLK12
+ */
+# define CONFIG_SYS_CMXSCR_VALUE	(CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
+
+#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
+
+/*
+ * - Rx-CLK is CLK13
+ * - Tx-CLK is CLK14
+ * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
+ * - Enable Full Duplex in FSMR
+ */
+# define CONFIG_SYS_CMXFCR_MASK2	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
+# define CONFIG_SYS_CPMFCR_RAMTYPE	0
+# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+
+#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
+
+#define CONFIG_MII			/* MII PHY management		*/
+#define CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
+/*
+ * GPIO pins used for bit-banged MII communications
+ */
+#define MDIO_PORT	2		/* Port C */
+#define MDIO_DECLARE	volatile ioport_t *iop = ioport_addr ( \
+				(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
+#define MDC_DECLARE	MDIO_DECLARE
+
+#if STK82xx_150
+#define CONFIG_SYS_MDIO_PIN	0x00008000	/* PC16 */
+#define CONFIG_SYS_MDC_PIN	0x00004000	/* PC17 */
+#endif
+
+#if STK82xx_100
+#define CONFIG_SYS_MDIO_PIN	0x00000002	/* PC30 */
+#define CONFIG_SYS_MDC_PIN	0x00000001	/* PC31 */
+#endif
+
+#if 1
+#define MDIO_ACTIVE	(iop->pdir |=  CONFIG_SYS_MDIO_PIN)
+#define MDIO_TRISTATE	(iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
+#define MDIO_READ	((iop->pdat &  CONFIG_SYS_MDIO_PIN) != 0)
+
+#define MDIO(bit)	if(bit) iop->pdat |=  CONFIG_SYS_MDIO_PIN; \
+			else	iop->pdat &= ~CONFIG_SYS_MDIO_PIN
+
+#define MDC(bit)	if(bit) iop->pdat |=  CONFIG_SYS_MDC_PIN; \
+			else	iop->pdat &= ~CONFIG_SYS_MDC_PIN
+#else
+#define MDIO_ACTIVE	({unsigned long tmp; tmp = iop->pdir; tmp |=  CONFIG_SYS_MDIO_PIN; iop->pdir = tmp;})
+#define MDIO_TRISTATE	({unsigned long tmp; tmp = iop->pdir; tmp &= ~CONFIG_SYS_MDIO_PIN; iop->pdir = tmp;})
+#define MDIO_READ	((iop->pdat &  CONFIG_SYS_MDIO_PIN) != 0)
+
+#define MDIO(bit)	if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |=  CONFIG_SYS_MDIO_PIN; iop->pdat = tmp;}\
+			else	{unsigned long tmp; tmp = iop->pdat; tmp &= ~CONFIG_SYS_MDIO_PIN; iop->pdat = tmp;}
+
+#define MDC(bit)	if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |=  CONFIG_SYS_MDC_PIN; iop->pdat = tmp;}\
+			else	{unsigned long tmp; tmp = iop->pdat; tmp &= ~CONFIG_SYS_MDC_PIN; iop->pdat = tmp;}
+#endif
+
+#define MIIDELAY	udelay(1)
+
+
+/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
+#define CONFIG_8260_CLKIN	66666666	/* in Hz */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SNTP
+
+#if CONFIG_I2C
+    #define CONFIG_CMD_I2C
+    #define CONFIG_CMD_DATE
+    #define CONFIG_CMD_DTT
+    #define CONFIG_CMD_EEPROM
+#endif
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+
+#if 0
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
+#endif
+
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CONFIG_SYS_LOAD_ADDR	0x300000	/* default load address	*/
+
+#define	CONFIG_SYS_RESET_ADDRESS 0x40000104	/* "bad" address		*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * CAN stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_CAN_BASE	0x51000000
+#define	CONFIG_SYS_CAN_SIZE	1
+#define CONFIG_SYS_CAN_BR	((CONFIG_SYS_CAN_BASE & BRx_BA_MSK)	|\
+			 BRx_PS_8			|\
+			 BRx_MS_UPMC			|\
+			 BRx_V)
+
+#define CONFIG_SYS_CAN_OR	(MEG_TO_AM(CONFIG_SYS_CAN_SIZE)	|\
+			 ORxU_BI)
+
+
+/* What should the base address of the main FLASH be and how big is
+ * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/tqm8272/config.mk
+ * The main FLASH is whichever is connected to *CS0.
+ */
+#define CONFIG_SYS_FLASH0_BASE 0x40000000
+#define CONFIG_SYS_FLASH0_SIZE 32	/* 32 MB */
+
+/* Flash bank size (for preliminary settings)
+ */
+#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
+
+#define CONFIG_SYS_FLASH_CFI				/* flash is CFI compat.	*/
+#define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver*/
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector	*/
+#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+
+#define CONFIG_SYS_UPDATE_FLASH_SIZE
+
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x40000)
+#define CONFIG_ENV_SIZE		0x20000
+#define CONFIG_ENV_SECT_SIZE	0x20000
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	0x20000
+
+/* Where is the Hardwareinformation Block (from Monitor Sources) */
+#define MON_RES_LENGTH		(0x0003FC00)
+#define HWIB_INFO_START_ADDR    (CONFIG_SYS_FLASH_BASE + MON_RES_LENGTH)
+#define HWIB_INFO_LEN           512
+#define CIB_INFO_START_ADDR     (CONFIG_SYS_FLASH_BASE + MON_RES_LENGTH + HWIB_INFO_LEN)
+#define CIB_INFO_LEN            512
+
+#define CONFIG_SYS_HWINFO_OFFSET	0x3fc00	/* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE		0x00000060	/* size   of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * NAND-FLASH stuff
+ *-----------------------------------------------------------------------
+ */
+#if defined(CONFIG_CMD_NAND)
+
+#define CONFIG_SYS_NAND_CS_DIST		0x80
+#define CONFIG_SYS_NAND_UPM_WRITE_CMD_OFS	0x20
+#define CONFIG_SYS_NAND_UPM_WRITE_ADDR_OFS	0x40
+
+#define CONFIG_SYS_NAND_BR	((CONFIG_SYS_NAND0_BASE & BRx_BA_MSK)	|\
+			 BRx_PS_8			|\
+			 BRx_MS_UPMB			|\
+			 BRx_V)
+
+#define CONFIG_SYS_NAND_OR	(MEG_TO_AM(CONFIG_SYS_NAND_SIZE)	|\
+			 ORxU_BI			|\
+			 ORxU_EHTR_8IDLE)
+
+#define CONFIG_SYS_NAND_SIZE	1
+#define CONFIG_SYS_NAND0_BASE 0x50000000
+#define CONFIG_SYS_NAND1_BASE (CONFIG_SYS_NAND0_BASE + CONFIG_SYS_NAND_CS_DIST)
+#define CONFIG_SYS_NAND2_BASE (CONFIG_SYS_NAND1_BASE + CONFIG_SYS_NAND_CS_DIST)
+#define CONFIG_SYS_NAND3_BASE (CONFIG_SYS_NAND2_BASE + CONFIG_SYS_NAND_CS_DIST)
+
+#define CONFIG_SYS_MAX_NAND_DEVICE     4       /* Max number of NAND devices           */
+
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, \
+			     CONFIG_SYS_NAND1_BASE, \
+			     CONFIG_SYS_NAND2_BASE, \
+			     CONFIG_SYS_NAND3_BASE, \
+			   }
+
+#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr)) = (__u8)d; } while(0)
+#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)(adr)))
+#define WRITE_NAND_UPM(d, adr, off) do \
+{ \
+	volatile unsigned char *addr = (unsigned char *) (adr + off); \
+	WRITE_NAND(d, addr); \
+} while(0)
+
+#endif /* CONFIG_CMD_NAND */
+
+#define	CONFIG_PCI
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
+#define CONFIG_PCI_PNP
+#define CONFIG_EEPRO100
+#define CONFIG_SYS_RX_ETH_BUFFER	8		/* use 8 rx buffer on eepro100	*/
+#define CONFIG_PCI_SCAN_SHOW
+#endif
+
+/*-----------------------------------------------------------------------
+ * Hard Reset Configuration Words
+ *
+ * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
+ * defines for the various registers affected by the HRCW e.g. changing
+ * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
+ */
+#if 0
+#define	__HRCW__ALL__		(HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
+
+#  define CONFIG_SYS_HRCW_MASTER	(__HRCW__ALL__ | HRCW_MODCK_H0111)
+#else
+#define CONFIG_SYS_HRCW_MASTER	(HRCW_BPS11 | HRCW_ISB111 | HRCW_BMS | HRCW_MODCK_H0111)
+#endif
+
+/* no slaves so just fill with zeros */
+#define CONFIG_SYS_HRCW_SLAVE1		0
+#define CONFIG_SYS_HRCW_SLAVE2		0
+#define CONFIG_SYS_HRCW_SLAVE3		0
+#define CONFIG_SYS_HRCW_SLAVE4		0
+#define CONFIG_SYS_HRCW_SLAVE5		0
+#define CONFIG_SYS_HRCW_SLAVE6		0
+#define CONFIG_SYS_HRCW_SLAVE7		0
+
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000  /* Size of used area in DPRAM    */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_FLASH0_BASE
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
+#if defined(CONFIG_CMD_KGDB)
+# define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * HIDx - Hardware Implementation-dependent Registers                    2-11
+ *-----------------------------------------------------------------------
+ * HID0 also contains cache control - initially enable both caches and
+ * invalidate contents, then the final state leaves only the instruction
+ * cache enabled. Note that Power-On and Hard reset invalidate the caches,
+ * but Soft reset does not.
+ *
+ * HID1 has only read-only information - nothing to set.
+ */
+#define CONFIG_SYS_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
+				HID0_IFEM|HID0_ABE)
+#define CONFIG_SYS_HID0_FINAL  (HID0_IFEM|HID0_ABE)
+#define CONFIG_SYS_HID2        0
+
+/*-----------------------------------------------------------------------
+ * RMR - Reset Mode Register                                     5-5
+ *-----------------------------------------------------------------------
+ * turn on Checkstop Reset Enable
+ */
+#define CONFIG_SYS_RMR         RMR_CSRE
+
+/*-----------------------------------------------------------------------
+ * BCR - Bus Configuration                                       4-25
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_BCR_60x         (BCR_EBM|BCR_NPQM0|BCR_NPQM2)	/* 60x mode  */
+#define BCR_APD01	0x10000000
+#define CONFIG_SYS_BCR_SINGLE		(BCR_APD01|BCR_ETM)	/* 8260 mode */
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration                             4-31
+ *-----------------------------------------------------------------------
+ */
+#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
+#define CONFIG_SYS_SIUMCR_LOW		(SIUMCR_DPPC00)
+#define CONFIG_SYS_SIUMCR_HIGH		(SIUMCR_DPPC00 | SIUMCR_ABE)
+#else
+#define CONFIG_SYS_SIUMCR		(SIUMCR_DPPC00)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control                             4-35
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
+#else
+#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+			 SYPCR_SWRI|SYPCR_SWP)
+#endif /* CONFIG_WATCHDOG */
+
+/*-----------------------------------------------------------------------
+ * TMCNTSC - Time Counter Status and Control                     4-40
+ *-----------------------------------------------------------------------
+ * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
+ * and enable Time Counter
+ */
+#define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control                 4-42
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
+ * Periodic timer
+ */
+#define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control                                   9-8
+ *-----------------------------------------------------------------------
+ * Ensure DFBRG is Divide by 16
+ */
+#define CONFIG_SYS_SCCR        SCCR_DFBRG01
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration                         13-7
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RCCR        0
+
+/*
+ * Init Memory Controller:
+ *
+ * Bank Bus     Machine PortSz  Device
+ * ---- ---     ------- ------  ------
+ *  0   60x     GPCM    32 bit  FLASH
+ *  1   60x     SDRAM   64 bit  SDRAM
+ *  2   60x	UPMB	 8 bit	NAND
+ *  3   60x	UPMC	 8 bit	CAN
+ *
+ */
+
+/* Initialize SDRAM
+	 */
+#undef CONFIG_SYS_INIT_LOCAL_SDRAM		/* No SDRAM on Local Bus */
+
+#define SDRAM_MAX_SIZE	0x20000000	/* max. 512 MB		*/
+
+/* Minimum mask to separate preliminary
+ * address ranges for CS[0:2]
+ */
+#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT	(512<<20)	/* less than 512 MB */
+
+#define CONFIG_SYS_MPTPR       0x4000
+
+/*-----------------------------------------------------------------------------
+ * Address for Mode Register Set (MRS) command
+ *-----------------------------------------------------------------------------
+ * In fact, the address is rather configuration data presented to the SDRAM on
+ * its address lines. Because the address lines may be mux'ed externally either
+ * for 8 column or 9 column devices, some bits appear twice in the 8260's
+ * address:
+ *
+ * |   (RFU)   |   (RFU)   | WBL |    TM    |     CL    |  BT | Burst Length |
+ * | BA1   BA0 | A12 : A10 |  A9 |  A8   A7 |  A6 : A4  |  A3 |   A2 :  A0   |
+ *  8 columns mux'ing:     |  A9 | A10  A21 | A22 : A24 | A25 |  A26 : A28   |
+ *  9 columns mux'ing:     |  A8 | A20  A21 | A22 : A24 | A25 |  A26 : A28   |
+ *  Settings:              |  0  |  0    0  |  0  1  0  |  0  |   0  1  0    |
+ *-----------------------------------------------------------------------------
+ */
+#define CONFIG_SYS_MRS_OFFS	0x00000110
+
+/* Bank 0 - FLASH
+ */
+#define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)  |\
+			 BRx_PS_32                      |\
+			 BRx_MS_GPCM_P                  |\
+			 BRx_V)
+
+#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE)      |\
+			 ORxG_CSNT                      |\
+			 ORxG_ACS_DIV4                  |\
+			 ORxG_SCY_8_CLK                 |\
+			 ORxG_TRLX)
+
+/* SDRAM on TQM8272 can have either 8 or 9 columns.
+ * The number affects configuration values.
+ */
+
+/* Bank 1 - 60x bus SDRAM
+ */
+#define CONFIG_SYS_PSRT        0x20	/* Low Value */
+/* #define CONFIG_SYS_PSRT        0x10	 Fast Value */
+#define CONFIG_SYS_LSRT        0x20	/* Local Bus */
+#ifndef CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)  |\
+			 BRx_PS_64                      |\
+			 BRx_MS_SDRAM_P                 |\
+			 BRx_V)
+
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR1_8COL
+
+/* SDRAM initialization values for 8-column chips
+ */
+#define CONFIG_SYS_OR1_8COL    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+			 ORxS_BPD_4                     |\
+			 ORxS_ROWST_PBI1_A7             |\
+			 ORxS_NUMR_12)
+
+#define CONFIG_SYS_PSDMR_8COL  (PSDMR_PBI                      |\
+			 PSDMR_SDAM_A15_IS_A5           |\
+			 PSDMR_BSMA_A12_A14             |\
+			 PSDMR_SDA10_PBI1_A8            |\
+			 PSDMR_RFRC_7_CLK               |\
+			 PSDMR_PRETOACT_2W              |\
+			 PSDMR_ACTTORW_2W               |\
+			 PSDMR_LDOTOPRE_1C              |\
+			 PSDMR_WRC_2C                   |\
+			 PSDMR_EAMUX                    |\
+			 PSDMR_BUFCMD			|\
+			 PSDMR_CL_2)
+
+
+/* SDRAM initialization values for 9-column chips
+ */
+#define CONFIG_SYS_OR1_9COL    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+			 ORxS_BPD_4                     |\
+			 ORxS_ROWST_PBI1_A5             |\
+			 ORxS_NUMR_13)
+
+#define CONFIG_SYS_PSDMR_9COL  (PSDMR_PBI                      |\
+			 PSDMR_SDAM_A16_IS_A5           |\
+			 PSDMR_BSMA_A12_A14             |\
+			 PSDMR_SDA10_PBI1_A7            |\
+			 PSDMR_RFRC_7_CLK               |\
+			 PSDMR_PRETOACT_2W              |\
+			 PSDMR_ACTTORW_2W               |\
+			 PSDMR_LDOTOPRE_1C              |\
+			 PSDMR_WRC_2C                   |\
+			 PSDMR_EAMUX                    |\
+			 PSDMR_BUFCMD			|\
+			 PSDMR_CL_2)
+
+#define CONFIG_SYS_OR1_10COL    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+			 ORxS_BPD_4                     |\
+			 ORxS_ROWST_PBI1_A4             |\
+			 ORxS_NUMR_13)
+
+#define CONFIG_SYS_PSDMR_10COL  (PSDMR_PBI                      |\
+			 PSDMR_SDAM_A17_IS_A5           |\
+			 PSDMR_BSMA_A12_A14             |\
+			 PSDMR_SDA10_PBI1_A4            |\
+			 PSDMR_RFRC_6_CLK               |\
+			 PSDMR_PRETOACT_2W              |\
+			 PSDMR_ACTTORW_2W               |\
+			 PSDMR_LDOTOPRE_1C              |\
+			 PSDMR_WRC_2C                   |\
+			 PSDMR_EAMUX                    |\
+			 PSDMR_BUFCMD			|\
+			 PSDMR_CL_2)
+
+#define PSDMR_RFRC_66MHZ_SINGLE         0x00028000  /* PSDMR[RFRC] at 66 MHz single mode */
+#define PSDMR_RFRC_100MHZ_SINGLE        0x00030000  /* PSDMR[RFRC] at 100 MHz single mode */
+#define PSDMR_RFRC_133MHZ_SINGLE        0x00030000  /* PSDMR[RFRC] at 133 MHz single mode */
+#define PSDMR_RFRC_66MHZ_60X            0x00030000  /* PSDMR[RFRC] at 66 MHz 60x mode */
+#define PSDMR_RFRC_100MHZ_60X           0x00028000  /* PSDMR[RFRC] at 100 MHz 60x mode */
+#define PSDMR_RFRC_DEFAULT              PSDMR_RFRC_133MHZ_SINGLE  /* PSDMR[RFRC] default value */
+
+#define PSDMR_PRETOACT_66MHZ_SINGLE     0x00002000  /* PSDMR[PRETOACT] at 66 MHz single mode */
+#define PSDMR_PRETOACT_100MHZ_SINGLE    0x00002000  /* PSDMR[PRETOACT] at 100 MHz single mode */
+#define PSDMR_PRETOACT_133MHZ_SINGLE    0x00002000  /* PSDMR[PRETOACT] at 133 MHz single mode */
+#define PSDMR_PRETOACT_66MHZ_60X        0x00001000  /* PSDMR[PRETOACT] at 66 MHz 60x mode */
+#define PSDMR_PRETOACT_100MHZ_60X       0x00001000  /* PSDMR[PRETOACT] at 100 MHz 60x mode */
+#define PSDMR_PRETOACT_DEFAULT          PSDMR_PRETOACT_133MHZ_SINGLE  /* PSDMR[PRETOACT] default value */
+
+#define PSDMR_WRC_66MHZ_SINGLE          0x00000020  /* PSDMR[WRC] at 66 MHz single mode */
+#define PSDMR_WRC_100MHZ_SINGLE         0x00000020  /* PSDMR[WRC] at 100 MHz single mode */
+#define PSDMR_WRC_133MHZ_SINGLE         0x00000010  /* PSDMR[WRC] at 133 MHz single mode */
+#define PSDMR_WRC_66MHZ_60X             0x00000010  /* PSDMR[WRC] at 66 MHz 60x mode */
+#define PSDMR_WRC_100MHZ_60X            0x00000010  /* PSDMR[WRC] at 100 MHz 60x mode */
+#define PSDMR_WRC_DEFAULT               PSDMR_WRC_133MHZ_SINGLE  /* PSDMR[WRC] default value */
+
+#define PSDMR_BUFCMD_66MHZ_SINGLE       0x00000000  /* PSDMR[BUFCMD] at 66 MHz single mode */
+#define PSDMR_BUFCMD_100MHZ_SINGLE      0x00000000  /* PSDMR[BUFCMD] at 100 MHz single mode */
+#define PSDMR_BUFCMD_133MHZ_SINGLE      0x00000004  /* PSDMR[BUFCMD] at 133 MHz single mode */
+#define PSDMR_BUFCMD_66MHZ_60X          0x00000000  /* PSDMR[BUFCMD] at 66 MHz 60x mode */
+#define PSDMR_BUFCMD_100MHZ_60X         0x00000000  /* PSDMR[BUFCMD] at 100 MHz 60x mode */
+#define PSDMR_BUFCMD_DEFAULT            PSDMR_BUFCMD_133MHZ_SINGLE  /* PSDMR[BUFCMD] default value */
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/TQM834x.h b/qemu/roms/u-boot/include/configs/TQM834x.h
new file mode 100644
index 000000000..6762e3a57
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/TQM834x.h
@@ -0,0 +1,574 @@
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * TQM8349 board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1	/* E300 Family */
+#define CONFIG_MPC834x		1	/* MPC834x specific */
+#define CONFIG_MPC8349		1	/* MPC8349 specific */
+#define CONFIG_TQM834X		1	/* TQM834X board specific */
+
+#define	CONFIG_SYS_TEXT_BASE	0x80000000
+
+/* IMMR Base Address Register, use Freescale default: 0xff400000 */
+#define CONFIG_SYS_IMMR		0xff400000
+
+/* System clock. Primary input clock when in PCI host mode */
+#define CONFIG_83XX_CLKIN	66666000	/* 66,666 MHz */
+
+/*
+ * Local Bus LCRR
+ *    LCRR:  DLL bypass, Clock divider is 8
+ *
+ *    for CSB = 266 MHz it gives LCB clock frequency = 33 MHz
+ *
+ * External Local Bus rate is
+ *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
+ */
+#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_8
+
+/* board pre init: do not call, nothing to do */
+#undef CONFIG_BOARD_EARLY_INIT_F
+
+/* detect the number of flash banks */
+#define CONFIG_BOARD_EARLY_INIT_R
+
+/*
+ * DDR Setup
+ */
+				/* DDR is system memory*/
+#define CONFIG_SYS_DDR_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE	CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
+#define DDR_CASLAT_25		/* CASLAT set to 2.5 */
+#undef CONFIG_DDR_ECC		/* only for ECC DDR module */
+#undef CONFIG_SPD_EEPROM	/* do not use SPD EEPROM for DDR setup */
+
+#undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
+#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00100000
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
+#define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
+#undef CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_BASE		0x80000000	/* start of FLASH   */
+#define CONFIG_SYS_FLASH_SIZE		8		/* FLASH size in MB */
+#define CONFIG_SYS_FLASH_EMPTY_INFO	/* print 'E' for empty sectors */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/*
+ * FLASH bank number detection
+ */
+
+/*
+ * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of
+ * Flash banks has to be determined at runtime and stored in a gloabl variable
+ * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is
+ * only used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array
+ * flash_info, and should be made sufficiently large to accomodate the number
+ * of banks that might actually be detected.  Since most (all?) Flash related
+ * functions use CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on
+ * the board, it is defined as tqm834x_num_flash_banks.
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT	2
+
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max sectors per device */
+
+/* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */
+#define CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_FLASH_BASE & BR_BA) \
+				| BR_MS_GPCM \
+				| BR_PS_32 \
+				| BR_V)
+
+/* FLASH timing (0x0000_0c54) */
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_GPCM_CSNT \
+					| OR_GPCM_ACS_DIV4 \
+					| OR_GPCM_SCY_5 \
+					| OR_GPCM_TRLX)
+
+#define CONFIG_SYS_PRELIM_OR_AM		OR_AM_1GB /* OR addr mask: 1 GiB */
+
+#define CONFIG_SYS_OR0_PRELIM		(CONFIG_SYS_PRELIM_OR_AM  \
+					| CONFIG_SYS_OR_TIMING_FLASH)
+
+#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_1GB)
+
+					/* Window base at flash base */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
+
+/* disable remaining mappings */
+#define CONFIG_SYS_BR1_PRELIM		0x00000000
+#define CONFIG_SYS_OR1_PRELIM		0x00000000
+#define CONFIG_SYS_LBLAWBAR1_PRELIM	0x00000000
+#define CONFIG_SYS_LBLAWAR1_PRELIM	0x00000000
+
+#define CONFIG_SYS_BR2_PRELIM		0x00000000
+#define CONFIG_SYS_OR2_PRELIM		0x00000000
+#define CONFIG_SYS_LBLAWBAR2_PRELIM	0x00000000
+#define CONFIG_SYS_LBLAWAR2_PRELIM	0x00000000
+
+#define CONFIG_SYS_BR3_PRELIM		0x00000000
+#define CONFIG_SYS_OR3_PRELIM		0x00000000
+#define CONFIG_SYS_LBLAWBAR3_PRELIM	0x00000000
+#define CONFIG_SYS_LBLAWAR3_PRELIM	0x00000000
+
+/*
+ * Monitor config
+ */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+# define CONFIG_SYS_RAMBOOT
+#else
+# undef  CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM*/
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+				/* Reserve 384 kB = 3 sect. for Mon */
+#define CONFIG_SYS_MONITOR_LEN	(384 * 1024)
+				/* Reserve 512 kB for malloc */
+#define CONFIG_SYS_MALLOC_LEN	(512 * 1024)
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+
+/* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2	/* 16 bit */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* 32 bytes/write */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	12	/* 10ms +/- 20% */
+#define CONFIG_SYS_I2C_MULTI_EEPROMS		/* more than one eeprom */
+
+/* I2C RTC */
+#define CONFIG_RTC_DS1337			/* use ds1337 rtc via i2c */
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68	/* at address 0x68 */
+
+/* I2C SYSMON (LM75) */
+#define CONFIG_DTT_LM75			1	/* ON Semi's LM75 */
+#define CONFIG_DTT_SENSORS		{0}	/* Sensor addresses */
+#define CONFIG_SYS_DTT_MAX_TEMP		70
+#define CONFIG_SYS_DTT_LOW_TEMP		-30
+#define CONFIG_SYS_DTT_HYSTERESIS	3
+
+/*
+ * TSEC
+ */
+#define CONFIG_TSEC_ENET		/* tsec ethernet support */
+#define CONFIG_MII
+
+#define CONFIG_SYS_TSEC1_OFFSET	0x24000
+#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
+#define CONFIG_SYS_TSEC2_OFFSET	0x25000
+#define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
+
+#if defined(CONFIG_TSEC_ENET)
+
+#define CONFIG_TSEC1		1
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_TSEC2		1
+#define CONFIG_TSEC2_NAME	"TSEC1"
+#define TSEC1_PHY_ADDR		2
+#define TSEC2_PHY_ADDR		1
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME		"TSEC0"
+
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_PCI
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+
+/* PCI1 host bridge */
+#define CONFIG_SYS_PCI1_MEM_BASE	0x90000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE	\
+			(CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
+#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE		0xe2000000
+#define CONFIG_SYS_PCI1_IO_PHYS		CONFIG_SYS_PCI1_IO_BASE
+#define CONFIG_SYS_PCI1_IO_SIZE		0x1000000	/* 16M */
+
+#undef CONFIG_EEPRO100
+#define CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+	#define PCI_ENET0_IOADDR	CONFIG_SYS_PCI1_IO_BASE
+	#define PCI_ENET0_MEMADDR	CONFIG_SYS_PCI1_MEM_BASE
+	#define PCI_IDSEL_NUMBER	0x1c    /* slot0 (IDSEL) = 28 */
+#endif
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID		0x1957  /* Freescale */
+
+#endif	/* CONFIG_PCI */
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_ADDR		\
+			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SECT_SIZE	0x20000	/* 128K (one sector) for env */
+#define CONFIG_ENV_SIZE		0x8000	/*  32K max size */
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+#define CONFIG_LOADS_ECHO		1 /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1 /* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SNTP
+
+#if defined(CONFIG_PCI)
+    #define CONFIG_CMD_PCI
+#endif
+
+#if defined(CONFIG_SYS_RAMBOOT)
+    #undef CONFIG_CMD_SAVEENV
+    #undef CONFIG_CMD_LOADS
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history */
+#define CONFIG_AUTO_COMPLETE		/* add autocompletion support */
+
+#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser */
+
+#if defined(CONFIG_CMD_KGDB)
+	#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
+#else
+	#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
+#endif
+
+				/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+				/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+#undef CONFIG_WATCHDOG		/* watchdog disabled */
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+				/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)
+
+#define CONFIG_SYS_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_1X1 |\
+	HRCWL_CSB_TO_CLKIN_4X1 |\
+	HRCWL_VCO_1X2 |\
+	HRCWL_CORE_TO_CSB_2X1)
+
+#if defined(PCI_64BIT)
+#define CONFIG_SYS_HRCW_HIGH (\
+	HRCWH_PCI_HOST |\
+	HRCWH_64_BIT_PCI |\
+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_PCI2_ARBITER_DISABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0X00000100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_TSEC1M_IN_GMII |\
+	HRCWH_TSEC2M_IN_GMII)
+#else
+#define CONFIG_SYS_HRCW_HIGH (\
+	HRCWH_PCI_HOST |\
+	HRCWH_32_BIT_PCI |\
+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_PCI2_ARBITER_DISABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0X00000100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_TSEC1M_IN_GMII |\
+	HRCWH_TSEC2M_IN_GMII)
+#endif
+
+/* System IO Config */
+#define CONFIG_SYS_SICRH	0
+#define CONFIG_SYS_SICRL	SICRL_LDP_A
+
+/* i-cache and d-cache disabled */
+#define CONFIG_SYS_HID0_INIT	0x000000000
+#define CONFIG_SYS_HID0_FINAL	(CONFIG_SYS_HID0_INIT | \
+				 HID0_ENABLE_INSTRUCTION_CACHE)
+#define CONFIG_SYS_HID2	HID2_HBE
+
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
+/* DDR 0 - 512M */
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE \
+				| BATL_PP_RW \
+				| BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_SDRAM_BASE + 0x10000000 \
+				| BATL_PP_RW \
+				| BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_SDRAM_BASE + 0x10000000 \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+
+/* stack in DCACHE @ 512M (no backing mem) */
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_INIT_RAM_ADDR \
+				| BATL_PP_RW \
+				| BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_INIT_RAM_ADDR \
+				| BATU_BL_128K \
+				| BATU_VS \
+				| BATU_VP)
+
+/* PCI */
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_PCI1_MEM_BASE \
+				| BATL_PP_RW \
+				| BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_PCI1_MEM_BASE \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCI1_MMIO_BASE \
+				| BATL_PP_RW \
+				| BATL_MEMCOHERENCE \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_PCI1_MMIO_BASE \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_PCI1_IO_BASE \
+				| BATL_PP_RW \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_PCI1_IO_BASE \
+				| BATU_BL_16M \
+				| BATU_VS \
+				| BATU_VP)
+#else
+#define CONFIG_SYS_IBAT3L	(0)
+#define CONFIG_SYS_IBAT3U	(0)
+#define CONFIG_SYS_IBAT4L	(0)
+#define CONFIG_SYS_IBAT4U	(0)
+#define CONFIG_SYS_IBAT5L	(0)
+#define CONFIG_SYS_IBAT5U	(0)
+#endif
+
+/* IMMRBAR */
+#define CONFIG_SYS_IBAT6L	(CONFIG_SYS_IMMR \
+				| BATL_PP_RW \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT6U	(CONFIG_SYS_IMMR \
+				| BATU_BL_1M \
+				| BATU_VS \
+				| BATU_VP)
+
+/* FLASH */
+#define CONFIG_SYS_IBAT7L	(CONFIG_SYS_FLASH_BASE \
+				| BATL_PP_RW \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT7U	(CONFIG_SYS_FLASH_BASE \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
+#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
+#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
+#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
+#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+				/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		400000
+
+#define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"hostname=tqm834x\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
+	"flash_nfs_old=run nfsargs addip addcons;"			\
+		"bootm ${kernel_addr}\0"				\
+	"flash_nfs=run nfsargs addip addcons;"				\
+		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
+	"flash_self_old=run ramargs addip addcons;"			\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"flash_self=run ramargs addip addcons;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
+	"net_nfs_old=tftp 400000 ${bootfile};"				\
+		"run nfsargs addip addcons;bootm\0"			\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
+		"tftp ${fdt_addr_r} ${fdt_file}; "			\
+		"run nfsargs addip addcons; "				\
+		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
+	"rootpath=/opt/eldk/ppc_6xx\0"					\
+	"bootfile=tqm834x/uImage\0"					\
+	"fdtfile=tqm834x/tqm834x.dtb\0"					\
+	"kernel_addr_r=400000\0"					\
+	"fdt_addr_r=600000\0"						\
+	"ramdisk_addr_r=800000\0"					\
+	"kernel_addr=800C0000\0"					\
+	"fdt_addr=800A0000\0"						\
+	"ramdisk_addr=80300000\0"					\
+	"u-boot=tqm834x/u-boot.bin\0"					\
+	"load=tftp 200000 ${u-boot}\0"					\
+	"update=protect off 80000000 +${filesize};"			\
+		"era 80000000 +${filesize};"				\
+		"cp.b 200000 80000000 ${filesize}\0"			\
+	"upd=run load update\0"						\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+/*
+ * JFFS2 partitions
+ */
+/* mtdparts command line support */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
+#define MTDIDS_DEFAULT		"nor0=TQM834x-0"
+
+/* default mtd partition table */
+#define MTDPARTS_DEFAULT	"mtdparts=TQM834x-0:256k(u-boot),256k(env)," \
+						"1m(kernel),2m(initrd)," \
+						"-(user);" \
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/TQM850L.h b/qemu/roms/u-boot/include/configs/TQM850L.h
new file mode 100644
index 000000000..ca3750d40
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/TQM850L.h
@@ -0,0 +1,452 @@
+/*
+ * (C) Copyright 2000-2008
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC850		1	/* This is a MPC850 CPU		*/
+#define CONFIG_TQM850L		1	/* ...on a TQM8xxL module	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0x40000000
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#define CONFIG_SYS_SMC_RXBUFLEN	128
+#define CONFIG_SYS_MAXIDLE	10
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+
+#define	CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_8xx\0"					\
+	"hostname=TQM850L\0"						\
+	"bootfile=TQM850L/uImage\0"					\
+	"fdt_addr=40040000\0"						\
+	"kernel_addr=40060000\0"					\
+	"ramdisk_addr=40200000\0"					\
+	"u-boot=TQM850L/u-image.bin\0"					\
+	"load=tftp 200000 ${u-boot}\0"					\
+	"update=prot off 40000000 +${filesize};"			\
+		"era 40000000 +${filesize};"				\
+		"cp.b 200000 40000000 ${filesize};"			\
+		"sete filesize;save\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
+
+#define CONFIG_NETCONSOLE
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#else
+#define	CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
+#endif
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+
+/* use CFI flash driver */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	71	/* max number of sectors on one chip */
+
+#define	CONFIG_ENV_IS_IN_FLASH	1
+#define	CONFIG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
+#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+
+#define CONFIG_MISC_INIT_R		/* Make sure to remap flashes correctly */
+
+/*-----------------------------------------------------------------------
+ * Dynamic MTD partition support
+ */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
+#define MTDIDS_DEFAULT		"nor0=TQM8xxL-0"
+
+#define MTDPARTS_DEFAULT	"mtdparts=TQM8xxL-0:256k(u-boot),"	\
+						"128k(dtb),"		\
+						"1664k(kernel),"	\
+						"2m(rootfs),"		\
+						"4m(data)"
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef	CONFIG_CAN_DRIVER
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#else	/* we must activate GPL5 in the SIUMCR for CAN */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ */
+#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CONFIG_SYS_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_IDE_PREINIT	1	/* Use preinit IDE hook */
+#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
+
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
+#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
+
+#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#ifndef	CONFIG_CAN_DRIVER
+#define	CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
+#define	CONFIG_SYS_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CONFIG_SYS_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CONFIG_SYS_OR3_CAN		(CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CONFIG_SYS_BR3_CAN		((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
+					BR_PS_8 | BR_MS_UPMB | BR_V )
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ *	gclk	  CPU clock (not bus clock!)
+ *	Trefresh  Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096  Rows from SDRAM example configuration
+ * 1000  factor s -> ms
+ *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
+ *    4  Number of refresh cycles per period
+ *   64  Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ * 50 MHz => 50.000.000 / Divider =  98
+ * 66 Mhz => 66.000.000 / Divider = 129
+ * 80 Mhz => 80.000.000 / Divider = 156
+ */
+
+#define CONFIG_SYS_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CONFIG_SYS_MAMR_PTA	98
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ */
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_HWCONFIG		1
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/TQM850M.h b/qemu/roms/u-boot/include/configs/TQM850M.h
new file mode 100644
index 000000000..659c9ad1c
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/TQM850M.h
@@ -0,0 +1,454 @@
+/*
+ * (C) Copyright 2000-2008
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC850		1	/* This is a MPC850 CPU		*/
+#define CONFIG_TQM850M		1	/* ...on a TQM8xxM module	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0x40000000
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#define CONFIG_SYS_SMC_RXBUFLEN	128
+#define CONFIG_SYS_MAXIDLE	10
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+
+#define	CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_8xx\0"					\
+	"hostname=TQM850M\0"						\
+	"bootfile=TQM850M/uImage\0"					\
+	"fdt_addr=40080000\0"						\
+	"kernel_addr=400A0000\0"					\
+	"ramdisk_addr=40280000\0"					\
+	"u-boot=TQM850M/u-image.bin\0"					\
+	"load=tftp 200000 ${u-boot}\0"					\
+	"update=prot off 40000000 +${filesize};"			\
+		"era 40000000 +${filesize};"				\
+		"cp.b 200000 40000000 ${filesize};"			\
+		"sete filesize;save\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
+
+#define CONFIG_NETCONSOLE
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#else
+#define	CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
+#endif
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+
+/* use CFI flash driver */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip */
+
+#define	CONFIG_ENV_IS_IN_FLASH	1
+#define	CONFIG_ENV_OFFSET		0x40000	/*   Offset   of Environment Sector	*/
+#define	CONFIG_ENV_SIZE		0x08000	/* Total Size of Environment		*/
+#define	CONFIG_ENV_SECT_SIZE	0x20000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+
+#define CONFIG_MISC_INIT_R		/* Make sure to remap flashes correctly */
+
+/*-----------------------------------------------------------------------
+ * Dynamic MTD partition support
+ */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
+#define MTDIDS_DEFAULT		"nor0=TQM8xxM-0"
+
+#define MTDPARTS_DEFAULT	"mtdparts=TQM8xxM-0:512k(u-boot),"	\
+						"128k(dtb),"		\
+						"1920k(kernel),"	\
+						"5632(rootfs),"		\
+						"4m(data)"
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef	CONFIG_CAN_DRIVER
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#else	/* we must activate GPL5 in the SIUMCR for CAN */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ */
+#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CONFIG_SYS_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_IDE_PREINIT	1	/* Use preinit IDE hook */
+#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
+
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
+#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
+
+#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#ifndef	CONFIG_CAN_DRIVER
+#define	CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
+#define	CONFIG_SYS_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CONFIG_SYS_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CONFIG_SYS_OR3_CAN		(CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CONFIG_SYS_BR3_CAN		((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
+					BR_PS_8 | BR_MS_UPMB | BR_V )
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ *	gclk	  CPU clock (not bus clock!)
+ *	Trefresh  Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096  Rows from SDRAM example configuration
+ * 1000  factor s -> ms
+ *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
+ *    4  Number of refresh cycles per period
+ *   64  Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ * 50 MHz => 50.000.000 / Divider =  98
+ * 66 Mhz => 66.000.000 / Divider = 129
+ * 80 Mhz => 80.000.000 / Divider = 156
+ */
+
+#define CONFIG_SYS_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CONFIG_SYS_MAMR_PTA	98
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ */
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_HWCONFIG		1
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/TQM855L.h b/qemu/roms/u-boot/include/configs/TQM855L.h
new file mode 100644
index 000000000..906d79b0c
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/TQM855L.h
@@ -0,0 +1,460 @@
+/*
+ * (C) Copyright 2000-2008
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC855		1	/* This is a MPC855 CPU		*/
+#define CONFIG_TQM855L		1	/* ...on a TQM8xxL module	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0x40000000
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#define CONFIG_SYS_SMC_RXBUFLEN	128
+#define CONFIG_SYS_MAXIDLE	10
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+
+#define	CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_8xx\0"					\
+	"hostname=TQM855L\0"						\
+	"bootfile=TQM855L/uImage\0"					\
+	"fdt_addr=40040000\0"						\
+	"kernel_addr=40060000\0"					\
+	"ramdisk_addr=40200000\0"					\
+	"u-boot=TQM855L/u-image.bin\0"					\
+	"load=tftp 200000 ${u-boot}\0"					\
+	"update=prot off 40000000 +${filesize};"			\
+		"era 40000000 +${filesize};"				\
+		"cp.b 200000 40000000 ${filesize};"			\
+		"sete filesize;save\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
+
+#define CONFIG_NETCONSOLE
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#else
+#define	CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
+#endif
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+
+/* use CFI flash driver */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	71	/* max number of sectors on one chip */
+
+#define	CONFIG_ENV_IS_IN_FLASH	1
+#define	CONFIG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
+#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+
+#define CONFIG_MISC_INIT_R		/* Make sure to remap flashes correctly */
+
+/*-----------------------------------------------------------------------
+ * Dynamic MTD partition support
+ */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
+#define MTDIDS_DEFAULT		"nor0=TQM8xxL-0"
+
+#define MTDPARTS_DEFAULT	"mtdparts=TQM8xxL-0:256k(u-boot),"	\
+						"128k(dtb),"		\
+						"1664k(kernel),"	\
+						"2m(rootfs),"		\
+						"4m(data)"
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef	CONFIG_CAN_DRIVER
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#else	/* we must activate GPL5 in the SIUMCR for CAN */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ */
+#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CONFIG_SYS_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_IDE_PREINIT	1	/* Use preinit IDE hook */
+#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
+
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
+#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
+
+#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#ifndef	CONFIG_CAN_DRIVER
+#define	CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
+#define	CONFIG_SYS_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CONFIG_SYS_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CONFIG_SYS_OR3_CAN		(CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CONFIG_SYS_BR3_CAN		((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
+					BR_PS_8 | BR_MS_UPMB | BR_V )
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ *	gclk	  CPU clock (not bus clock!)
+ *	Trefresh  Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096  Rows from SDRAM example configuration
+ * 1000  factor s -> ms
+ *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
+ *    4  Number of refresh cycles per period
+ *   64  Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ * 50 MHz => 50.000.000 / Divider =  98
+ * 66 Mhz => 66.000.000 / Divider = 129
+ * 80 Mhz => 80.000.000 / Divider = 156
+ */
+
+#define CONFIG_SYS_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CONFIG_SYS_MAMR_PTA	98
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ */
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+#define CONFIG_SCC1_ENET
+#define CONFIG_FEC_ENET
+#define CONFIG_ETHPRIME		"SCC"
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_HWCONFIG		1
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/TQM855M.h b/qemu/roms/u-boot/include/configs/TQM855M.h
new file mode 100644
index 000000000..44d456e16
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/TQM855M.h
@@ -0,0 +1,491 @@
+/*
+ * (C) Copyright 2000-2008
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC855		1	/* This is a MPC855 CPU		*/
+#define CONFIG_TQM855M		1	/* ...on a TQM8xxM module	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0x40000000
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#define CONFIG_SYS_SMC_RXBUFLEN	128
+#define CONFIG_SYS_MAXIDLE	10
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+
+#define	CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_8xx\0"					\
+	"hostname=TQM855M\0"						\
+	"bootfile=TQM855M/uImage\0"					\
+	"fdt_addr=40080000\0"						\
+	"kernel_addr=400A0000\0"					\
+	"ramdisk_addr=40280000\0"					\
+	"u-boot=TQM855M/u-image.bin\0"					\
+	"load=tftp 200000 ${u-boot}\0"					\
+	"update=prot off 40000000 +${filesize};"			\
+		"era 40000000 +${filesize};"				\
+		"cp.b 200000 40000000 ${filesize};"			\
+		"sete filesize;save\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+/* enable I2C and select the hardware/software driver */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED	93000	/* 93 kHz is supposed to work */
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PB_SCL		0x00000020	/* PB 26 */
+#define PB_SDA		0x00000010	/* PB 27 */
+
+#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
+#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
+#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
+#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
+#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
+#define I2C_DELAY	udelay(2)	/* 1/4 I2C clock duration */
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50		/* EEPROM AT24C64	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2		/* two byte address	*/
+#if 0
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* takes up to 10 msec	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5
+#endif
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
+
+#define CONFIG_NETCONSOLE
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#else
+#define	CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
+#endif
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+
+/* use CFI flash driver */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip */
+
+#define	CONFIG_ENV_IS_IN_FLASH	1
+#define	CONFIG_ENV_OFFSET		0x40000	/*   Offset   of Environment Sector	*/
+#define	CONFIG_ENV_SIZE		0x08000	/* Total Size of Environment		*/
+#define	CONFIG_ENV_SECT_SIZE	0x20000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+
+#define CONFIG_MISC_INIT_R		/* Make sure to remap flashes correctly */
+
+/*-----------------------------------------------------------------------
+ * Dynamic MTD partition support
+ */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
+#define MTDIDS_DEFAULT		"nor0=TQM8xxM-0"
+
+#define MTDPARTS_DEFAULT	"mtdparts=TQM8xxM-0:512k(u-boot),"	\
+						"128k(dtb),"		\
+						"1920k(kernel),"	\
+						"5632(rootfs),"		\
+						"4m(data)"
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef	CONFIG_CAN_DRIVER
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#else	/* we must activate GPL5 in the SIUMCR for CAN */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ */
+#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CONFIG_SYS_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_IDE_PREINIT	1	/* Use preinit IDE hook */
+#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
+
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
+#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
+
+#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#ifndef	CONFIG_CAN_DRIVER
+#define	CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
+#define	CONFIG_SYS_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CONFIG_SYS_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CONFIG_SYS_OR3_CAN		(CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CONFIG_SYS_BR3_CAN		((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
+					BR_PS_8 | BR_MS_UPMB | BR_V )
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ *	gclk	  CPU clock (not bus clock!)
+ *	Trefresh  Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096  Rows from SDRAM example configuration
+ * 1000  factor s -> ms
+ *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
+ *    4  Number of refresh cycles per period
+ *   64  Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ * 50 MHz => 50.000.000 / Divider =  98
+ * 66 Mhz => 66.000.000 / Divider = 129
+ * 80 Mhz => 80.000.000 / Divider = 156
+ */
+
+#define CONFIG_SYS_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CONFIG_SYS_MAMR_PTA	98
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ */
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+#define CONFIG_SCC1_ENET
+#define CONFIG_FEC_ENET
+#define CONFIG_ETHPRIME		"SCC"
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_HWCONFIG		1
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/TQM860L.h b/qemu/roms/u-boot/include/configs/TQM860L.h
new file mode 100644
index 000000000..855b0cddc
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/TQM860L.h
@@ -0,0 +1,459 @@
+/*
+ * (C) Copyright 2000-2008
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC860		1	/* This is a MPC860 CPU		*/
+#define CONFIG_TQM860L		1	/* ...on a TQM8xxL module	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0x40000000
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#define CONFIG_SYS_SMC_RXBUFLEN	128
+#define CONFIG_SYS_MAXIDLE	10
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+
+#define	CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_8xx\0"					\
+	"hostname=TQM860L\0"						\
+	"bootfile=TQM860L/uImage\0"					\
+	"fdt_addr=40040000\0"						\
+	"kernel_addr=40060000\0"					\
+	"ramdisk_addr=40200000\0"					\
+	"u-boot=TQM860L/u-image.bin\0"					\
+	"load=tftp 200000 ${u-boot}\0"					\
+	"update=prot off 40000000 +${filesize};"			\
+		"era 40000000 +${filesize};"				\
+		"cp.b 200000 40000000 ${filesize};"			\
+		"sete filesize;save\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
+
+#define CONFIG_NETCONSOLE
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#else
+#define	CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
+#endif
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+
+/* use CFI flash driver */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	71	/* max number of sectors on one chip */
+
+#define	CONFIG_ENV_IS_IN_FLASH	1
+#define	CONFIG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
+#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+
+#define CONFIG_MISC_INIT_R		/* Make sure to remap flashes correctly */
+
+/*-----------------------------------------------------------------------
+ * Dynamic MTD partition support
+ */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
+#define MTDIDS_DEFAULT		"nor0=TQM8xxL-0"
+
+#define MTDPARTS_DEFAULT	"mtdparts=TQM8xxL-0:256k(u-boot),"	\
+						"128k(dtb),"		\
+						"1664k(kernel),"	\
+						"2m(rootfs),"		\
+						"4m(data)"
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef	CONFIG_CAN_DRIVER
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#else	/* we must activate GPL5 in the SIUMCR for CAN */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ */
+#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CONFIG_SYS_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_IDE_PREINIT	1	/* Use preinit IDE hook */
+#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
+
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
+#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
+
+#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#ifndef	CONFIG_CAN_DRIVER
+#define	CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
+#define	CONFIG_SYS_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CONFIG_SYS_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CONFIG_SYS_OR3_CAN		(CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CONFIG_SYS_BR3_CAN		((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
+					BR_PS_8 | BR_MS_UPMB | BR_V )
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ *	gclk	  CPU clock (not bus clock!)
+ *	Trefresh  Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096  Rows from SDRAM example configuration
+ * 1000  factor s -> ms
+ *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
+ *    4  Number of refresh cycles per period
+ *   64  Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ * 50 MHz => 50.000.000 / Divider =  98
+ * 66 Mhz => 66.000.000 / Divider = 129
+ * 80 Mhz => 80.000.000 / Divider = 156
+ */
+
+#define CONFIG_SYS_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CONFIG_SYS_MAMR_PTA	98
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ */
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+#define CONFIG_SCC1_ENET
+#define CONFIG_FEC_ENET
+#define CONFIG_ETHPRIME		"SCC"
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT       1
+#define CONFIG_OF_BOARD_SETUP  1
+#define CONFIG_HWCONFIG		1
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/TQM860M.h b/qemu/roms/u-boot/include/configs/TQM860M.h
new file mode 100644
index 000000000..8109379ae
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/TQM860M.h
@@ -0,0 +1,464 @@
+/*
+ * (C) Copyright 2000-2008
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC860		1	/* This is a MPC860 CPU		*/
+#define CONFIG_TQM860M		1	/* ...on a TQM8xxM module	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0x40000000
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#define CONFIG_SYS_SMC_RXBUFLEN	128
+#define CONFIG_SYS_MAXIDLE	10
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+
+#define	CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_8xx\0"					\
+	"hostname=TQM860M\0"						\
+	"bootfile=TQM860M/uImage\0"					\
+	"fdt_addr=400C0000\0"						\
+	"kernel_addr=40100000\0"					\
+	"ramdisk_addr=40280000\0"					\
+	"u-boot=TQM860M/u-image.bin\0"					\
+	"load=tftp 200000 ${u-boot}\0"					\
+	"update=prot off 40000000 +${filesize};"			\
+		"era 40000000 +${filesize};"				\
+		"cp.b 200000 40000000 ${filesize};"			\
+		"sete filesize;save\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
+
+#define CONFIG_NETCONSOLE
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#else
+#define	CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
+#endif
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+/* use CFI flash driver */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip */
+
+#define	CONFIG_ENV_IS_IN_FLASH	1
+#define	CONFIG_ENV_OFFSET		0x40000	/*   Offset   of Environment Sector	*/
+#define	CONFIG_ENV_SIZE		0x08000	/* Total Size of Environment Sector	*/
+#define	CONFIG_ENV_SECT_SIZE	0x40000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+
+#define CONFIG_MISC_INIT_R		/* Make sure to remap flashes correctly */
+
+/*-----------------------------------------------------------------------
+ * Dynamic MTD partition support
+ */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
+#define MTDIDS_DEFAULT		"nor0=TQM8xxM-0"
+
+#define MTDPARTS_DEFAULT	"mtdparts=TQM8xxM-0:512k(u-boot),"	\
+						"128k(dtb),"		\
+						"1920k(kernel),"	\
+						"5632(rootfs),"		\
+						"4m(data)"
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef	CONFIG_CAN_DRIVER
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#else	/* we must activate GPL5 in the SIUMCR for CAN */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ */
+#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CONFIG_SYS_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_IDE_PREINIT	1	/* Use preinit IDE hook */
+#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
+
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
+#define	SDRAM_MAX_SIZE		0x08000000	/* max 128 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
+
+#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#ifndef	CONFIG_CAN_DRIVER
+#define	CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
+#define	CONFIG_SYS_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CONFIG_SYS_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CONFIG_SYS_OR3_CAN		(CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CONFIG_SYS_BR3_CAN		((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
+					BR_PS_8 | BR_MS_UPMB | BR_V )
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ *	gclk	  CPU clock (not bus clock!)
+ *	Trefresh  Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096  Rows from SDRAM example configuration
+ * 1000  factor s -> ms
+ *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
+ *    4  Number of refresh cycles per period
+ *   64  Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ * 50 MHz => 50.000.000 / Divider =  98
+ * 66 Mhz => 66.000.000 / Divider = 129
+ * 80 Mhz => 80.000.000 / Divider = 156
+ */
+
+#define CONFIG_SYS_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CONFIG_SYS_MAMR_PTA	98
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ */
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 10 column SDRAM */
+#define CONFIG_SYS_MAMR_10COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9  |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+#define CONFIG_SCC1_ENET
+#define CONFIG_FEC_ENET
+#define CONFIG_ETHPRIME		"SCC"
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_HWCONFIG		1
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/TQM862L.h b/qemu/roms/u-boot/include/configs/TQM862L.h
new file mode 100644
index 000000000..da4af93d2
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/TQM862L.h
@@ -0,0 +1,464 @@
+/*
+ * (C) Copyright 2000-2008
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC860		1
+#define CONFIG_MPC860T		1
+#define CONFIG_MPC862		1
+
+#define CONFIG_TQM862L		1	/* ...on a TQM8xxL module	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0x40000000
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#define CONFIG_SYS_SMC_RXBUFLEN	128
+#define CONFIG_SYS_MAXIDLE	10
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+
+#define	CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_8xx\0"					\
+	"hostname=TQM862L\0"						\
+	"bootfile=TQM862L/uImage\0"					\
+	"fdt_addr=40040000\0"						\
+	"kernel_addr=40060000\0"					\
+	"ramdisk_addr=40200000\0"					\
+	"u-boot=TQM862L/u-image.bin\0"					\
+	"load=tftp 200000 ${u-boot}\0"					\
+	"update=prot off 40000000 +${filesize};"			\
+		"era 40000000 +${filesize};"				\
+		"cp.b 200000 40000000 ${filesize};"			\
+		"sete filesize;save\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
+
+#define CONFIG_NETCONSOLE
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#else
+#define	CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
+#endif
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+
+/* use CFI flash driver */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	71	/* max number of sectors on one chip */
+
+#define	CONFIG_ENV_IS_IN_FLASH	1
+#define	CONFIG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
+#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+
+#define CONFIG_MISC_INIT_R		/* Make sure to remap flashes correctly */
+
+/*-----------------------------------------------------------------------
+ * Dynamic MTD partition support
+ */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
+#define MTDIDS_DEFAULT		"nor0=TQM8xxL-0"
+
+#define MTDPARTS_DEFAULT	"mtdparts=TQM8xxL-0:256k(u-boot),"	\
+						"128k(dtb),"		\
+						"1664k(kernel),"	\
+						"2m(rootfs),"		\
+						"4m(data)"
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef	CONFIG_CAN_DRIVER
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#else	/* we must activate GPL5 in the SIUMCR for CAN */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ */
+#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CONFIG_SYS_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_IDE_PREINIT	1	/* Use preinit IDE hook */
+#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #1	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
+
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
+#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
+
+#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#ifndef	CONFIG_CAN_DRIVER
+#define	CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
+#define	CONFIG_SYS_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CONFIG_SYS_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CONFIG_SYS_OR3_CAN		(CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CONFIG_SYS_BR3_CAN		((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
+					BR_PS_8 | BR_MS_UPMB | BR_V )
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ *	gclk	  CPU clock (not bus clock!)
+ *	Trefresh  Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096  Rows from SDRAM example configuration
+ * 1000  factor s -> ms
+ *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
+ *    4  Number of refresh cycles per period
+ *   64  Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ *  50 MHz =>  50.000.000 / Divider =  98
+ *  66 Mhz =>  66.000.000 / Divider = 129
+ *  80 Mhz =>  80.000.000 / Divider = 156
+ * 100 Mhz => 100.000.000 / Divider = 195
+ */
+
+#define CONFIG_SYS_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CONFIG_SYS_MAMR_PTA	98
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ */
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+#define CONFIG_SCC1_ENET
+#define CONFIG_FEC_ENET
+#define CONFIG_ETHPRIME		"SCC"
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_HWCONFIG		1
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/TQM862M.h b/qemu/roms/u-boot/include/configs/TQM862M.h
new file mode 100644
index 000000000..ec3a57b96
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/TQM862M.h
@@ -0,0 +1,465 @@
+/*
+ * (C) Copyright 2000-2008
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC860		1
+#define CONFIG_MPC860T		1
+#define CONFIG_MPC862		1
+
+#define CONFIG_TQM862M		1	/* ...on a TQM8xxM module	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0x40000000
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#define CONFIG_SYS_SMC_RXBUFLEN	128
+#define CONFIG_SYS_MAXIDLE	10
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+
+#define	CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_8xx\0"					\
+	"hostname=TQM862M\0"						\
+	"bootfile=TQM862M/uImage\0"					\
+	"fdt_addr=40080000\0"						\
+	"kernel_addr=400A0000\0"					\
+	"ramdisk_addr=40280000\0"					\
+	"u-boot=TQM862M/u-image.bin\0"					\
+	"load=tftp 200000 ${u-boot}\0"					\
+	"update=prot off 40000000 +${filesize};"			\
+		"era 40000000 +${filesize};"				\
+		"cp.b 200000 40000000 ${filesize};"			\
+		"sete filesize;save\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
+
+#define CONFIG_NETCONSOLE
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#else
+#define	CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
+#endif
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+
+/* use CFI flash driver */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip */
+
+#define	CONFIG_ENV_IS_IN_FLASH	1
+#define	CONFIG_ENV_OFFSET		0x40000	/*   Offset   of Environment Sector	*/
+#define	CONFIG_ENV_SIZE		0x08000	/* Total Size of Environment		*/
+#define	CONFIG_ENV_SECT_SIZE	0x20000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+
+#define CONFIG_MISC_INIT_R		/* Make sure to remap flashes correctly */
+
+/*-----------------------------------------------------------------------
+ * Dynamic MTD partition support
+ */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
+#define MTDIDS_DEFAULT		"nor0=TQM8xxM-0"
+
+#define MTDPARTS_DEFAULT	"mtdparts=TQM8xxM-0:512k(u-boot),"	\
+						"128k(dtb),"		\
+						"1920k(kernel),"	\
+						"5632(rootfs),"		\
+						"4m(data)"
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef	CONFIG_CAN_DRIVER
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#else	/* we must activate GPL5 in the SIUMCR for CAN */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ */
+#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CONFIG_SYS_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_IDE_PREINIT	1	/* Use preinit IDE hook */
+#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #1	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
+
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
+#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
+
+#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#ifndef	CONFIG_CAN_DRIVER
+#define	CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
+#define	CONFIG_SYS_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CONFIG_SYS_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CONFIG_SYS_OR3_CAN		(CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CONFIG_SYS_BR3_CAN		((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
+					BR_PS_8 | BR_MS_UPMB | BR_V )
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ *	gclk	  CPU clock (not bus clock!)
+ *	Trefresh  Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096  Rows from SDRAM example configuration
+ * 1000  factor s -> ms
+ *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
+ *    4  Number of refresh cycles per period
+ *   64  Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ *  50 MHz =>  50.000.000 / Divider =  98
+ *  66 Mhz =>  66.000.000 / Divider = 129
+ *  80 Mhz =>  80.000.000 / Divider = 156
+ * 100 Mhz => 100.000.000 / Divider = 195
+ */
+
+#define CONFIG_SYS_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CONFIG_SYS_MAMR_PTA	98
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ */
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+#define CONFIG_SCC1_ENET
+#define CONFIG_FEC_ENET
+#define CONFIG_ETHPRIME		"SCC"
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_HWCONFIG		1
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/TQM866M.h b/qemu/roms/u-boot/include/configs/TQM866M.h
new file mode 100644
index 000000000..cb8b84d3a
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/TQM866M.h
@@ -0,0 +1,483 @@
+/*
+ * (C) Copyright 2000-2008
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC866		1	/* This is a MPC866 CPU		*/
+#define CONFIG_TQM866M		1	/* ...on a TQM8xxM module	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0x40000000
+
+#define CONFIG_8xx_OSCLK		10000000	/*  10 MHz - PLL input clock	*/
+#define CONFIG_SYS_8xx_CPUCLK_MIN		15000000	/*  15 MHz - CPU minimum clock	*/
+#define CONFIG_SYS_8xx_CPUCLK_MAX		133000000	/* 133 MHz - CPU maximum clock	*/
+#define CONFIG_8xx_CPUCLK_DEFAULT	50000000	/*  50 MHz - CPU default clock	*/
+						/* (it will be used if there is no	*/
+						/* 'cpuclk' variable with valid value)	*/
+
+#undef CONFIG_SYS_MEASURE_CPUCLK			/* Measure real cpu clock	*/
+						/* (function measure_gclk()	*/
+						/* will be called)		*/
+#ifdef CONFIG_SYS_MEASURE_CPUCLK
+#define CONFIG_SYS_8XX_XIN		10000000	/* measure_gclk() needs this	*/
+#endif
+
+#define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#define CONFIG_SYS_SMC_RXBUFLEN	128
+#define CONFIG_SYS_MAXIDLE	10
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+
+#define CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_PREBOOT	"echo;" \
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_8xx\0"					\
+	"hostname=TQM866M\0"						\
+	"bootfile=TQM866M/uImage\0"					\
+	"fdt_addr=400C0000\0"						\
+	"kernel_addr=40100000\0"					\
+	"ramdisk_addr=40280000\0"					\
+	"u-boot=TQM866M/u-image.bin\0"					\
+	"load=tftp 200000 ${u-boot}\0"					\
+	"update=prot off 40000000 +${filesize};"			\
+		"era 40000000 +${filesize};"				\
+		"cp.b 200000 40000000 ${filesize};"			\
+		"sete filesize;save\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+/* enable I2C and select the hardware/software driver */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT			/* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED	93000	/* 93 kHz is supposed to work */
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
+
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PB_SCL		0x00000020	/* PB 26 */
+#define PB_SDA		0x00000010	/* PB 27 */
+
+#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
+#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
+#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
+#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
+			else	immr->im_cpm.cp_pbdat &= ~PB_SDA
+#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
+			else	immr->im_cpm.cp_pbdat &= ~PB_SCL
+#define I2C_DELAY	udelay(2)	/* 1/4 I2C clock duration */
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50		/* EEPROM AT24C256	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2		/* two byte address	*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#undef CONFIG_RTC_MPC8xx		/* MPC866 does not support RTC	*/
+
+#define	CONFIG_TIMESTAMP		/* but print image timestmps	*/
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
+
+#define CONFIG_NETCONSOLE
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+/* use CFI flash driver */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip */
+
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_OFFSET		0x40000 /*   Offset   of Environment Sector	*/
+#define CONFIG_ENV_SIZE		0x08000 /* Total Size of Environment Sector	*/
+#define CONFIG_ENV_SECT_SIZE	0x40000 /* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+
+#define CONFIG_MISC_INIT_R		/* Make sure to remap flashes correctly */
+
+/*-----------------------------------------------------------------------
+ * Dynamic MTD partition support
+ */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
+#define MTDIDS_DEFAULT		"nor0=TQM8xxM-0"
+
+#define MTDPARTS_DEFAULT	"mtdparts=TQM8xxM-0:512k(u-boot),"	\
+						"128k(dtb),"		\
+						"1920k(kernel),"	\
+						"5632(rootfs),"		\
+						"4m(data)"
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size	  of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef CONFIG_CAN_DRIVER
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#else	/* we must activate GPL5 in the SIUMCR for CAN */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CONFIG_SYS_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_IDE_PREINIT	1	/* Use preinit IDE hook */
+#define CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card Adapter */
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
+#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_DER 0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/*
+ * FLASH timing: Default value of OR0 after reset
+ */
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
+				 OR_SCY_15_CLK | OR_TRLX)
+
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
+#define SDRAM_MAX_SIZE		(256 << 20)	/* max 256 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
+
+#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#ifndef CONFIG_CAN_DRIVER
+#define CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
+#define CONFIG_SYS_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CONFIG_SYS_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CONFIG_SYS_OR3_CAN		(CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CONFIG_SYS_BR3_CAN		((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
+					BR_PS_8 | BR_MS_UPMB | BR_V )
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*
+ * 4096	Rows from SDRAM example configuration
+ * 1000	factor s -> ms
+ * 64	PTP (pre-divider from MPTPR) from SDRAM example configuration
+ * 4	Number of refresh cycles per period
+ * 64	Refresh cycle in ms per number of rows
+ */
+#define CONFIG_SYS_PTA_PER_CLK	((4096 * 64 * 1000) / (4 * 64))
+
+/*
+ * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad)
+ *
+ *                        CPUclock(MHz) * 31.2
+ * CONFIG_SYS_MAMR_PTA = -----------------------------------     with DFBRG = 0
+ *                2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16
+ *
+ * CPU clock =  15 MHz:  CONFIG_SYS_MAMR_PTA =  29   ->  4 * 7.73 us
+ * CPU clock =  50 MHz:  CONFIG_SYS_MAMR_PTA =  97   ->  4 * 7.76 us
+ * CPU clock =  66 MHz:  CONFIG_SYS_MAMR_PTA = 128   ->  4 * 7.75 us
+ * CPU clock = 133 MHz:  CONFIG_SYS_MAMR_PTA = 255   ->  4 * 7.67 us
+ *
+ * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will
+ * be met also in the default configuration, i.e. if environment variable
+ * 'cpuclk' is not set.
+ */
+#define CONFIG_SYS_MAMR_PTA		97
+
+/*
+ * Memory Periodic Timer Prescaler Register (MPTPR) values.
+ */
+/* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16
+/* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 10 column SDRAM */
+#define CONFIG_SYS_MAMR_10COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9  |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+#define CONFIG_SCC1_ENET
+#define CONFIG_FEC_ENET
+#define CONFIG_ETHPRIME		"SCC"
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_HWCONFIG		1
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/TQM885D.h b/qemu/roms/u-boot/include/configs/TQM885D.h
new file mode 100644
index 000000000..d1e6c5b2b
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/TQM885D.h
@@ -0,0 +1,482 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2006
+ * Martin Krause, TQ-Systems GmBH, martin.krause@tqs.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC885		1	/* This is a MPC885 CPU		*/
+#define CONFIG_TQM885D		1	/* ...on a TQM88D module	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0x40000000
+
+#define CONFIG_8xx_OSCLK		10000000	/*  10 MHz - PLL input clock	*/
+#define CONFIG_SYS_8xx_CPUCLK_MIN		15000000	/*  15 MHz - CPU minimum clock	*/
+#define CONFIG_SYS_8xx_CPUCLK_MAX		133000000	/* 133 MHz - CPU maximum clock	*/
+#define CONFIG_8xx_CPUCLK_DEFAULT	66000000	/*  66 MHz - CPU default clock	*/
+						/* (it will be used if there is no	*/
+						/* 'cpuclk' variable with valid value)	*/
+
+#define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#define CONFIG_SYS_SMC_RXBUFLEN	128
+#define CONFIG_SYS_MAXIDLE	10
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+
+#define CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_PREBOOT	"echo;" \
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_8xx\0"					\
+	"bootfile=/tftpboot/TQM885D/uImage\0"				\
+	"fdt_addr=400C0000\0"						\
+	"kernel_addr=40100000\0"					\
+	"ramdisk_addr=40280000\0"					\
+	"load=tftp 200000 ${u-boot}\0"					\
+	"update=protect off 40000000 +${filesize};"			\
+		"erase 40000000 +${filesize};"				\
+		"cp.b 200000 40000000 ${filesize};"			\
+		"protect on 40000000 +${filesize}\0"			\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+/* enable I2C and select the hardware/software driver */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT			/* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED	93000	/* 93 kHz is supposed to work */
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PB_SCL		0x00000020	/* PB 26 */
+#define PB_SDA		0x00000010	/* PB 27 */
+
+#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
+#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
+#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
+#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
+			else	immr->im_cpm.cp_pbdat &= ~PB_SDA
+#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
+			else	immr->im_cpm.cp_pbdat &= ~PB_SCL
+#define I2C_DELAY	udelay(2)	/* 1/4 I2C clock duration */
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50		/* EEPROM AT24C??	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2		/* two byte address	*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+
+# define CONFIG_RTC_DS1337 1
+# define CONFIG_SYS_I2C_RTC_ADDR 0x68
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#undef CONFIG_RTC_MPC8xx		/* MPC885 does not support RTC	*/
+
+#define	CONFIG_TIMESTAMP		/* but print image timestmps	*/
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0100000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0300000	/* 1 ... 3 MB in DRAM	*/
+#define CONFIG_SYS_ALT_MEMTEST				/* alternate, more extensive
+						   memory test.*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
+
+/*
+ * Enable loopw command.
+ */
+#define CONFIG_LOOPW
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+
+/* use CFI flash driver */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip */
+
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_OFFSET		0x40000 /*   Offset   of Environment Sector	*/
+#define CONFIG_ENV_SIZE		0x08000 /* Total Size of Environment		*/
+#define CONFIG_ENV_SECT_SIZE	0x40000 /* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size	  of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef CONFIG_CAN_DRIVER
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#else	/* we must activate GPL5 in the SIUMCR for CAN */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CONFIG_SYS_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_IDE_PREINIT	1	/* Use preinit IDE hook */
+#define CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card Adapter */
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
+#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_DER 0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/*
+ * FLASH timing: Default value of OR0 after reset
+ */
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
+				 OR_SCY_6_CLK | OR_TRLX)
+
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
+#define SDRAM_MAX_SIZE		(256 << 20)	/* max 256 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
+
+#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#ifndef CONFIG_CAN_DRIVER
+#define CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
+#define CONFIG_SYS_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CONFIG_SYS_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CONFIG_SYS_OR3_CAN		(CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CONFIG_SYS_BR3_CAN		((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
+					BR_PS_8 | BR_MS_UPMB | BR_V )
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*
+ * 4096	Rows from SDRAM example configuration
+ * 1000	factor s -> ms
+ * 64	PTP (pre-divider from MPTPR) from SDRAM example configuration
+ * 4	Number of refresh cycles per period
+ * 64	Refresh cycle in ms per number of rows
+ */
+#define CONFIG_SYS_PTA_PER_CLK	((4096 * 64 * 1000) / (4 * 64))
+
+/*
+ * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad)
+ *
+ *                        CPUclock(MHz) * 31.2
+ * CONFIG_SYS_MAMR_PTA = -----------------------------------     with DFBRG = 0
+ *                2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16
+ *
+ * CPU clock =  15 MHz:  CONFIG_SYS_MAMR_PTA =  29   ->  4 * 7.73 us
+ * CPU clock =  50 MHz:  CONFIG_SYS_MAMR_PTA =  97   ->  4 * 7.76 us
+ * CPU clock =  66 MHz:  CONFIG_SYS_MAMR_PTA = 128   ->  4 * 7.75 us
+ * CPU clock = 133 MHz:  CONFIG_SYS_MAMR_PTA = 255   ->  4 * 7.67 us
+ *
+ * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will
+ * be met also in the default configuration, i.e. if environment variable
+ * 'cpuclk' is not set.
+ */
+#define CONFIG_SYS_MAMR_PTA		128
+
+/*
+ * Memory Periodic Timer Prescaler Register (MPTPR) values.
+ */
+/* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16
+/* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 10 column SDRAM */
+#define CONFIG_SYS_MAMR_10COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9  |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+/*
+ * Network configuration
+ */
+#define CONFIG_SCC2_ENET		/* enable ethernet on SCC2 */
+#define CONFIG_FEC_ENET			/* enable ethernet on FEC */
+#define CONFIG_ETHER_ON_FEC1		/* ... for FEC1 */
+#define CONFIG_ETHER_ON_FEC2		/* ... for FEC2 */
+
+#if defined(CONFIG_CMD_MII)
+#define CONFIG_SYS_DISCOVER_PHY
+#define CONFIG_MII_INIT	1
+#endif
+
+#define CONFIG_NET_RETRY_COUNT 1	/* reduce max. timeout before
+					   switching to another netwok (if the
+					   tried network is unreachable) */
+
+#define CONFIG_ETHPRIME		"SCC"
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_HWCONFIG		1
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/Total5200.h b/qemu/roms/u-boot/include/configs/Total5200.h
new file mode 100644
index 000000000..a58eecab8
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/Total5200.h
@@ -0,0 +1,386 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Check valid setting of revision define.
+ * Total5100 and Total5200 Rev.1 are identical except for the processor.
+ */
+#if (CONFIG_TOTAL5200_REV!=1 && CONFIG_TOTAL5200_REV!=2)
+#error CONFIG_TOTAL5200_REV must be 1 or 2
+#endif
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5200		1	/* This is a MPC5200 CPU */
+#define CONFIG_TOTAL5200	1	/* ... on Total5200 board */
+
+/*
+ * Valid values for CONFIG_SYS_TEXT_BASE are:
+ * 0xFFF00000	boot high (standard configuration)
+ * 0xFE000000	boot low
+ * 0x00100000	boot from RAM (for testing only)
+ */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
+#endif
+
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
+
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	3	/* console is on PSC3 */
+#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*
+ * Video console
+ */
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_SED13806
+#define CONFIG_VIDEO_SED13806_16BPP
+
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_LOGO
+/* #define CONFIG_VIDEO_BMP_LOGO */
+#define CONFIG_CONSOLE_EXTRA_INFO
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_SPLASH_SCREEN
+
+
+/*
+ * PCI Mapping:
+ * 0x40000000 - 0x4fffffff - PCI Memory
+ * 0x50000000 - 0x50ffffff - PCI IO Space
+ */
+#define CONFIG_PCI		1
+#define CONFIG_PCI_PNP		1
+#define CONFIG_PCI_SCAN_SHOW	1
+#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1
+
+#define CONFIG_PCI_MEM_BUS	0x40000000
+#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE	0x10000000
+
+#define CONFIG_PCI_IO_BUS	0x50000000
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0x01000000
+
+#define CONFIG_MII		1
+#define CONFIG_EEPRO100		1
+#define CONFIG_SYS_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
+#define CONFIG_NS8382X		1
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+/* USB */
+#define CONFIG_USB_OHCI
+#define CONFIG_USB_STORAGE
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PCI
+
+#define CONFIG_CMD_BMP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+
+
+#if (CONFIG_SYS_TEXT_BASE == 0xFE000000)		/* Boot low */
+#   define CONFIG_SYS_LOWBOOT		1
+#endif
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT	\
+	"setenv stdout serial;setenv stderr serial;" \
+	"echo;" \
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_82xx\0"					\
+	"bootfile=/tftpboot/MPC5200/uImage\0"				\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+#define CONFIG_SYS_I2C_MODULE		1	/* Select I2C module #1 or #2 */
+
+#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	70
+
+/*
+ * Flash configuration
+ */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
+#if CONFIG_TOTAL5200_REV==2
+#   define CONFIG_SYS_MAX_FLASH_BANKS	3	/* max num of flash banks */
+#   define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS5_START, CONFIG_SYS_CS4_START, CONFIG_SYS_BOOTCS_START }
+#else
+#   define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks  */
+#   define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START }
+#endif
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
+
+#if CONFIG_TOTAL5200_REV==1
+#   define CONFIG_SYS_FLASH_BASE	0xFE000000
+#   define CONFIG_SYS_FLASH_SIZE	0x02000000
+#elif CONFIG_TOTAL5200_REV==2
+#   define CONFIG_SYS_FLASH_BASE	0xFA000000
+#   define CONFIG_SYS_FLASH_SIZE	0x06000000
+#endif /* CONFIG_TOTAL5200_REV */
+
+#if defined(CONFIG_SYS_LOWBOOT)
+#   define CONFIG_ENV_ADDR		0xFE040000
+#else	/* CONFIG_SYS_LOWBOOT */
+#   define CONFIG_ENV_ADDR		0xFFF40000
+#endif	/* CONFIG_SYS_LOWBOOT */
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_SIZE		0x40000
+#define CONFIG_ENV_SECT_SIZE	0x40000
+#define CONFIG_ENV_OVERWRITE	1
+
+/*
+ * Memory map
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
+#define CONFIG_SYS_MBAR		0xF0000000	/*   64 kB */
+#define CONFIG_SYS_FPGA_BASE		0xF0010000	/*   64 kB */
+#define CONFIG_SYS_CPLD_BASE		0xF0020000	/*   64 kB */
+#define CONFIG_SYS_LCD_BASE		0xF1000000	/* 4096 kB */
+
+/* Use SRAM until RAM will be available */
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC	1
+#define CONFIG_MPC5xxx_FEC_SEVENWIRE
+/* dummy, 7-wire FEC does not have phy address */
+#define CONFIG_PHY_ADDR		0x00
+
+/*
+ * GPIO configuration
+ *
+ * CS1:   SDRAM CS1 disabled, gpio_wkup_6 enabled                0
+ * Reserved                                                      0
+ * ALTs:  CAN1/2 on PSC2, SPI on PSC3                            00
+ * CS7:   Interrupt GPIO on PSC3_5                               0
+ * CS8:   Interrupt GPIO on PSC3_4                               0
+ * ATA:   reset default, changed in ATA driver                   00
+ * IR_USB_CLK: IrDA/USB 48MHz clock gen. int., pin is GPIO       0
+ * IRDA:  reset default, changed in IrDA driver                  000
+ * ETHER: reset default, changed in Ethernet driver              0000
+ * PCI_DIS: reset default, changed in PCI driver                 0
+ * USB_SE: reset default, changed in USB driver                  0
+ * USB:   reset default, changed in USB driver                   00
+ * PSC3:  SPI and UART functionality without CD                  1100
+ * Reserved                                                      0
+ * PSC2:  CAN1/2                                                 001
+ * Reserved                                                      0
+ * PSC1:  reset default, changed in AC'97 driver                 000
+ *
+ */
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x00000C10
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
+
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+
+/*
+ * Various low-level settings
+ */
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
+
+#if CONFIG_TOTAL5200_REV==1
+#   define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#   define CONFIG_SYS_BOOTCS_SIZE	0x02000000	/* 32 MB */
+#   define CONFIG_SYS_BOOTCS_CFG	0x0004DF00	/* 4WS, MX, AL, CE, AS_25, DS_32 */
+#   define CONFIG_SYS_CS0_START	CONFIG_SYS_FLASH_BASE
+#   define CONFIG_SYS_CS0_SIZE		0x02000000	/* 32 MB */
+#else
+#   define CONFIG_SYS_BOOTCS_START	(CONFIG_SYS_CS4_START + CONFIG_SYS_CS4_SIZE)
+#   define CONFIG_SYS_BOOTCS_SIZE	0x02000000	/* 32 MB */
+#   define CONFIG_SYS_BOOTCS_CFG	0x0004DF00	/* 4WS, MX, AL, CE, AS_25, DS_32 */
+#   define CONFIG_SYS_CS4_START	(CONFIG_SYS_CS5_START + CONFIG_SYS_CS5_SIZE)
+#   define CONFIG_SYS_CS4_SIZE		0x02000000	/* 32 MB */
+#   define CONFIG_SYS_CS4_CFG		0x0004DF00	/* 4WS, MX, AL, CE, AS_25, DS_32 */
+#   define CONFIG_SYS_CS5_START	CONFIG_SYS_FLASH_BASE
+#   define CONFIG_SYS_CS5_SIZE		0x02000000	/* 32 MB */
+#   define CONFIG_SYS_CS5_CFG		0x0004DF00	/* 4WS, MX, AL, CE, AS_25, DS_32 */
+#endif
+
+#define CONFIG_SYS_CS1_START		CONFIG_SYS_FPGA_BASE
+#define CONFIG_SYS_CS1_SIZE		0x00010000	/* 64 kB */
+#define CONFIG_SYS_CS1_CFG		0x0019FF00	/* 25WS, MX, AL, AA, CE, AS_25, DS_32 */
+
+#define CONFIG_SYS_CS2_START		CONFIG_SYS_LCD_BASE
+#define CONFIG_SYS_CS2_SIZE		0x00400000	/* 4096 kB */
+#define CONFIG_SYS_CS2_CFG		0x0032FD0C	/* 50WS, MX, AL, AA, CE, AS_25, DS_16, endian swapping */
+
+#if CONFIG_TOTAL5200_REV==1
+#   define CONFIG_SYS_CS3_START	CONFIG_SYS_CPLD_BASE
+#   define CONFIG_SYS_CS3_SIZE		0x00010000	/* 64 kB */
+#   define CONFIG_SYS_CS3_CFG		0x000ADF00	/* 10WS, MX, AL, CE, AS_25, DS_32 */
+#else
+#   define CONFIG_SYS_CS3_START	CONFIG_SYS_CPLD_BASE
+#   define CONFIG_SYS_CS3_SIZE		0x00010000	/* 64 kB */
+#   define CONFIG_SYS_CS3_CFG		0x000AD800	/* 10WS, MX, AL, CE, AS_24, DS_8 */
+#endif
+
+#define CONFIG_SYS_CS_BURST		0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE	0x33333333
+
+/*-----------------------------------------------------------------------
+ * USB stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_USB_CLOCK	0x0001BBBB
+#define CONFIG_USB_CONFIG	0x00001000
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+
+#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+
+#define	CONFIG_IDE_RESET		/* reset for ide supported	*/
+#define CONFIG_IDE_PREINIT
+
+#define CONFIG_SYS_ATA_CS_ON_I2C2
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
+
+/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
+
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)
+
+/* Interval between registers                                                */
+#define CONFIG_SYS_ATA_STRIDE          4
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/VCMA9.h b/qemu/roms/u-boot/include/configs/VCMA9.h
new file mode 100644
index 000000000..d40185e1e
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/VCMA9.h
@@ -0,0 +1,234 @@
+/*
+ * (C) Copyright 2002, 2003
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Gary Jennejohn <garyj@denx.de>
+ * David Mueller <d.mueller@elsoft.ch>
+ *
+ * Configuation settings for the MPL VCMA9 board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+
+#define MACH_TYPE_MPL_VCMA9	227
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARM920T		/* This is an ARM920T Core */
+#define CONFIG_S3C24X0		/* in a SAMSUNG S3C24x0-type SoC */
+#define CONFIG_S3C2410		/* specifically a SAMSUNG S3C2410 SoC */
+#define CONFIG_VCMA9		/* on a MPL VCMA9 Board  */
+#define CONFIG_MACH_TYPE	MACH_TYPE_MPL_VCMA9 /* Machine type */
+
+#define CONFIG_SYS_TEXT_BASE	0x0
+
+#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
+
+/* input clock of PLL (VCMA9 has 12MHz input clock) */
+#define CONFIG_SYS_CLK_FREQ	12000000
+
+#define CONFIG_CMDLINE_TAG	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NAND_YAFFS
+
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_CMDLINE_EDITING
+
+/*
+ * I2C stuff:
+ * the MPL VCMA9 is equipped with an ATMEL 24C256 EEPROM at
+ * address 0x50 with 16bit addressing
+ */
+#define CONFIG_SYS_I2C
+
+/* we use the built-in I2C controller */
+#define CONFIG_SYS_I2C_S3C24X0
+#define CONFIG_SYS_I2C_S3C24X0_SPEED    100000	/* I2C speed */
+#define CONFIG_SYS_I2C_S3C24X0_SLAVE    0x7F	/* I2C slave addr */
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+/* use EEPROM for environment vars */
+#define CONFIG_ENV_IS_IN_EEPROM		1
+/* environment starts at offset 0 */
+#define CONFIG_ENV_OFFSET		0x000
+/* 2KB should be more than enough */
+#define CONFIG_ENV_SIZE			0x800
+
+#undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
+/* 64 bytes page write mode on 24C256 */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_CS8900			/* we have a CS8900 on-board */
+#define CONFIG_CS8900_BASE		0x20000300
+#define CONFIG_CS8900_BUS16
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_S3C24X0_SERIAL
+#define CONFIG_SERIAL1		1	/* we use SERIAL 1 on VCMA9 */
+
+/* USB support (currently only works with D-cache off) */
+#define CONFIG_USB_OHCI
+#define CONFIG_USB_OHCI_S3C24XX
+#define CONFIG_USB_KEYBOARD
+#define CONFIG_USB_STORAGE
+#define CONFIG_DOS_PARTITION
+
+/* Enable needed helper functions */
+#define CONFIG_SYS_STDIO_DEREGISTER	/* needs stdio_deregister */
+
+/* RTC */
+#define CONFIG_RTC_S3C24X0
+
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE			9600
+
+#define CONFIG_BOOTDELAY		5
+#define CONFIG_BOOT_RETRY_TIME		-1
+#define CONFIG_RESET_TO_RETRY
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#define CONFIG_NETMASK			255.255.255.0
+#define CONFIG_IPADDR			10.0.0.110
+#define CONFIG_SERVERIP			10.0.0.1
+
+#if defined(CONFIG_CMD_KGDB)
+/* speed to run kgdb serial port */
+#define CONFIG_KGDB_BAUDRATE		115200
+#endif
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_PROMPT		"VCMA9 # "
+#define CONFIG_SYS_CBSIZE		256
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS		16
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+#define CONFIG_DISPLAY_CPUINFO				/* Display cpu info */
+#define CONFIG_DISPLAY_BOARDINFO			/* Display board info */
+
+#define CONFIG_SYS_MEMTEST_START	0x30000000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x31FFFFFF	/* 32 MB in DRAM */
+
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_SYS_LOAD_ADDR		0x30800000
+
+/* we configure PWM Timer 4 to 1ms 1000Hz  */
+
+/* support additional compression methods */
+#define CONFIG_BZIP2
+#define CONFIG_LZO
+#define CONFIG_LZMA
+
+/* Ident */
+/*#define VERSION_TAG "released"*/
+#define VERSION_TAG "unstable"
+#define CONFIG_IDENT_STRING "\n(c) 2003 - 2011 by MPL AG Switzerland, " \
+			    "MEV-10080-001 " VERSION_TAG
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1		0x30000000	/* SDRAM Bank #1 */
+#define PHYS_FLASH_1		0x00000000	/* Flash Bank #1 */
+
+#define CONFIG_SYS_FLASH_BASE	PHYS_FLASH_1
+
+/* FLASH and environment organization */
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_LEGACY
+#define CONFIG_SYS_FLASH_LEGACY_512Kx16
+#define CONFIG_FLASH_SHOW_PROGRESS	45
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_MAX_FLASH_SECT	(19)
+
+/*
+ * Size of malloc() pool
+ * BZIP2 / LZO / LZMA need a lot of RAM
+ */
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+
+/* NAND configuration */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_S3C2410
+#define CONFIG_SYS_S3C2410_NAND_HWECC
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x4E000000
+#define CONFIG_S3C24XX_CUSTOM_NAND_TIMING
+#define CONFIG_S3C24XX_TACLS		1
+#define CONFIG_S3C24XX_TWRPH0		5
+#define CONFIG_S3C24XX_TWRPH1		3
+#endif
+
+#define MULTI_PURPOSE_SOCKET_ADDR	0x08000000
+
+/* File system */
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_CMD_JFFS2
+#define CONFIG_YAFFS2
+#define CONFIG_RBTREE
+#define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_LZO
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 - \
+					GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/VOH405.h b/qemu/roms/u-boot/include/configs/VOH405.h
new file mode 100644
index 000000000..d4a4b68c8
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/VOH405.h
@@ -0,0 +1,407 @@
+/*
+ * (C) Copyright 2001-2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_VOH405		1	/* ...on a VOH405 board		*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFF80000
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
+
+#define CONFIG_SYS_CLK_FREQ     33333400 /* external frequency to pll   */
+
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+#undef	CONFIG_BOOTARGS
+#undef	CONFIG_BOOTCOMMAND
+
+#define CONFIG_PREBOOT                  /* enable preboot variable      */
+
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#undef  CONFIG_HAS_ETH1
+
+#define CONFIG_PPC4xx_EMAC
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
+
+#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_EEPROM
+
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_SUPPORT_VFAT
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_RTC_MC146818		/* DS1685 is MC146818 compatible*/
+#define CONFIG_SYS_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address		*/
+
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+
+#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CONFIG_CONS_INDEX	2	/* Use UART1			*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+
+#undef  CONFIG_SYS_EXT_SERIAL_CLOCK           /* no external serial clock used */
+#define CONFIG_SYS_BASE_BAUD       691200
+
+/* The following table includes the supported baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+#define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+
+/*-----------------------------------------------------------------------
+ * NAND-FLASH stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1         /* Max number of NAND devices */
+#define NAND_BIG_DELAY_US	25
+
+#define CONFIG_SYS_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
+#define CONFIG_SYS_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
+#define CONFIG_SYS_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
+#define CONFIG_SYS_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
+
+#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1       /* ".i" read skips bad blocks   */
+#define CONFIG_SYS_NAND_QUIET          1
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
+#define PCI_HOST_FORCE  1               /* configure as pci host        */
+#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_HOST	PCI_HOST_HOST   /* select pci host function     */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
+					/* resource configuration       */
+
+#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
+
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
+#define CONFIG_SYS_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
+#define CONFIG_SYS_PCI_PTM1LA  0x00000000      /* point to sdram               */
+#define CONFIG_SYS_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CONFIG_SYS_PCI_PTM2LA  0xffc00000      /* point to flash               */
+#define CONFIG_SYS_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
+#define CONFIG_SYS_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff
+ *-----------------------------------------------------------------------
+ */
+#undef	CONFIG_IDE_8xx_DIRECT		    /* no pcmcia interface required */
+#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
+#define CONFIG_IDE_RESET	1	/* reset for ide supported	*/
+
+#define CONFIG_SYS_IDE_MAXBUS		2		/* max. 2 IDE busses	*/
+#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
+
+#define CONFIG_SYS_ATA_BASE_ADDR	0xF0100000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE1_OFFSET	0x0010
+
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
+
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFF80000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(2 * 1024*1024)	/* Reserve 2 MB for malloc()	*/
+
+#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
+# define CONFIG_SYS_RAMBOOT		1
+#else
+# undef CONFIG_SYS_RAMBOOT
+#endif
+
+/*-----------------------------------------------------------------------
+ * Environment Variable setup
+ */
+#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CONFIG_ENV_OFFSET		0x100	/* environment starts at the beginning of the EEPROM */
+#define CONFIG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
+				   /* total size of a CAT24WC16 is 2048 bytes */
+
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
+#define CONFIG_SYS_NVRAM_SIZE		242			/* NVRAM size		*/
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		100000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT24WC08		*/
+#define CONFIG_SYS_EEPROM_WREN         1
+
+/* CAT24WC32/64... */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x01
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5	/* The Catalyst CAT24WC32 has	*/
+					/* 32 byte page write mode using*/
+					/* last 5 bits of the address	*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+#define CAN_BA		0xF0000000	    /* CAN Base Address			*/
+#define DUART0_BA	0xF0000400	    /* DUART Base Address		*/
+#define DUART1_BA	0xF0000408	    /* DUART Base Address		*/
+#define RTC_BA		0xF0000500	    /* RTC Base Address			*/
+#define VGA_BA		0xF1000000	    /* Epson VGA Base Address		*/
+#define CONFIG_SYS_NAND_BASE	0xF4000000	    /* NAND FLASH Base Address		*/
+
+/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
+#define CONFIG_SYS_EBC_PB0AP		0x92015480
+/*#define CONFIG_SYS_EBC_PB0AP		  0x08055880  /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
+#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization			*/
+#define CONFIG_SYS_EBC_PB1AP		0x92015480
+#define CONFIG_SYS_EBC_PB1CR		0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization		*/
+#define CONFIG_SYS_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization	*/
+#define CONFIG_SYS_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 4 (Epson VGA) initialization					*/
+#define CONFIG_SYS_EBC_PB4AP	0x03805380   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */
+#define CONFIG_SYS_EBC_PB4CR	VGA_BA | 0x7A000    /* BAS=0xF10,BS=8MB,BU=R/W,BW=16bit */
+
+/*-----------------------------------------------------------------------
+ * LCD Setup
+ */
+
+#define CONFIG_SYS_LCD_BIG_MEM         0xF1200000  /* Epson S1D13806 Mem Base Address  */
+#define CONFIG_SYS_LCD_BIG_REG         0xF1000000  /* Epson S1D13806 Reg Base Address  */
+#define CONFIG_SYS_LCD_SMALL_MEM       0xF1400000  /* Epson S1D13704 Mem Base Address  */
+#define CONFIG_SYS_LCD_SMALL_REG       0xF140FFE0  /* Epson S1D13704 Reg Base Address  */
+
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (1 << 20)
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ */
+
+#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0100100	    /* FPGA internal Base Address	*/
+
+/* FPGA internal regs */
+#define CONFIG_SYS_FPGA_CTRL		0x000
+
+/* FPGA Control Reg */
+#define CONFIG_SYS_FPGA_CTRL_CF_RESET	0x0001
+#define CONFIG_SYS_FPGA_CTRL_WDI	0x0002
+#define CONFIG_SYS_FPGA_CTRL_PS2_RESET 0x0020
+
+#define CONFIG_SYS_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
+#define CONFIG_SYS_FPGA_MAX_SIZE	128*1024    /* 128kByte is enough for XC2S50E*/
+
+/* FPGA program pin configuration */
+#define CONFIG_SYS_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
+#define CONFIG_SYS_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
+#define CONFIG_SYS_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
+#define CONFIG_SYS_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
+#define CONFIG_SYS_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CONFIG_SYS_TEMP_STACK_OCM	  1
+
+/* On Chip Memory location */
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
+
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO setup (PPC405EP specific)
+ *
+ * GPIO0[0]	- External Bus Controller BLAST output
+ * GPIO0[1-9]	- Instruction trace outputs -> GPIO
+ * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
+ * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
+ * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
+ * GPIO0[24-27] - UART0 control signal inputs/outputs
+ * GPIO0[28-29] - UART1 data signal input/output
+ * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs -> GPIO
+ */
+#define CONFIG_SYS_GPIO0_OSRL		0x00000550
+#define CONFIG_SYS_GPIO0_OSRH		0x00000110
+#define CONFIG_SYS_GPIO0_ISR1L		0x00000000
+#define CONFIG_SYS_GPIO0_ISR1H		0x15555440
+#define CONFIG_SYS_GPIO0_TSRL		0x00000000
+#define CONFIG_SYS_GPIO0_TSRH		0x00000000
+#define CONFIG_SYS_GPIO0_TCR		0x777E0017
+
+#define CONFIG_SYS_DUART_RST		(0x80000000 >> 14)
+#define CONFIG_SYS_LCD_ENDIAN		(0x80000000 >> 7)
+#define CONFIG_SYS_IIC_ON		(0x80000000 >> 8)
+#define CONFIG_SYS_LCD0_RST		(0x80000000 >> 30)
+#define CONFIG_SYS_LCD1_RST		(0x80000000 >> 31)
+#define CONFIG_SYS_EEPROM_WP		(0x80000000 >> 0)
+
+/*
+ * Default speed selection (cpu_plb_opb_ebc) in mhz.
+ * This value will be set if iic boot eprom is disabled.
+ */
+#if 1
+#define PLLMR0_DEFAULT	 PLLMR0_266_133_66_33
+#define PLLMR1_DEFAULT	 PLLMR1_266_133_66_33
+#endif
+#if 0
+#define PLLMR0_DEFAULT	 PLLMR0_200_100_50_33
+#define PLLMR1_DEFAULT	 PLLMR1_200_100_50_33
+#endif
+#if 0
+#define PLLMR0_DEFAULT	 PLLMR0_133_66_66_33
+#define PLLMR1_DEFAULT	 PLLMR1_133_66_66_33
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/VOM405.h b/qemu/roms/u-boot/include/configs/VOM405.h
new file mode 100644
index 000000000..c06897b89
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/VOM405.h
@@ -0,0 +1,274 @@
+/*
+ * (C) Copyright 2001-2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_VOM405		1	/* ...on a VOM405 board		*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFC8000
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
+
+#define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/
+
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+#undef	CONFIG_BOOTARGS
+#undef  CONFIG_BOOTCOMMAND
+
+#define CONFIG_PREBOOT                  /* enable preboot variable      */
+
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#undef  CONFIG_HAS_ETH1
+
+#define CONFIG_PPC4xx_EMAC
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_EEPROM
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+#undef  CONFIG_PRAM			/* no "protected RAM"           */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+
+#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CONFIG_SYS_BASE_BAUD	    691200
+
+/* The following table includes the supported baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+#define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*
+ * FLASH organization
+ */
+#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
+
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+/*
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(~(CONFIG_SYS_TEXT_BASE) + 1)
+#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)
+
+#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
+# define CONFIG_SYS_RAMBOOT		1
+#else
+# undef CONFIG_SYS_RAMBOOT
+#endif
+
+/*
+ * Environment Variable setup
+ */
+#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CONFIG_ENV_OFFSET		0x100	/* environment starts at the beginning of the EEPROM */
+#define CONFIG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
+				   /* total size of a CAT24WC16 is 2048 bytes */
+
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
+#define CONFIG_SYS_NVRAM_SIZE		242			/* NVRAM size		*/
+
+/*
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last 4 bits of the address	*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+
+/*
+ * External Bus Controller (EBC) Setup
+ */
+#define CAN_BA		0xF0000000	    /* CAN Base Address			*/
+
+/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
+#define CONFIG_SYS_EBC_PB0AP		0x92015480
+#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization		*/
+#define CONFIG_SYS_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+
+/*
+ * FPGA stuff
+ */
+#define CONFIG_SYS_XSVF_DEFAULT_ADDR	0xfffc0000
+
+/* FPGA program pin configuration */
+#define CONFIG_SYS_FPGA_PRG		0x04000000  /* JTAG TMS pin (ppc output)     */
+#define CONFIG_SYS_FPGA_CLK		0x02000000  /* JTAG TCK pin (ppc output)     */
+#define CONFIG_SYS_FPGA_DATA		0x01000000  /* JTAG TDO->TDI data pin (ppc output) */
+#define CONFIG_SYS_FPGA_INIT		0x00010000  /* unused (ppc input)	     */
+#define CONFIG_SYS_FPGA_DONE		0x00008000  /* JTAG TDI->TDO pin (ppc input) */
+
+/*
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CONFIG_SYS_TEMP_STACK_OCM	  1
+
+/* On Chip Memory location */
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
+
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * Definitions for GPIO setup (PPC405EP specific)
+ *
+ * GPIO0[0]	- External Bus Controller BLAST output
+ * GPIO0[1-9]	- Instruction trace outputs -> GPIO
+ * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
+ * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
+ * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
+ * GPIO0[24-27] - UART0 control signal inputs/outputs
+ * GPIO0[28-29] - UART1 data signal input/output
+ * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
+ */
+/* GPIO Input:		OSR=00, ISR=00, TSR=00, TCR=0 */
+/* GPIO Output:		OSR=00, ISR=00, TSR=00, TCR=1 */
+/* Alt. Funtion Input:	OSR=00, ISR=01, TSR=00, TCR=0 */
+/* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
+#define CONFIG_SYS_GPIO0_OSRL		0x40000500  /*	0 ... 15 */
+#define CONFIG_SYS_GPIO0_OSRH		0x00000110  /* 16 ... 31 */
+#define CONFIG_SYS_GPIO0_ISR1L		0x00000000  /*	0 ... 15 */
+#define CONFIG_SYS_GPIO0_ISR1H		0x14000045  /* 16 ... 31 */
+#define CONFIG_SYS_GPIO0_TSRL		0x00000000  /*	0 ... 15 */
+#define CONFIG_SYS_GPIO0_TSRH		0x00000000  /* 16 ... 31 */
+#define CONFIG_SYS_GPIO0_TCR		0xF7FE0014  /*	0 ... 31 */
+
+/*
+ * Default speed selection (cpu_plb_opb_ebc) in mhz.
+ * This value will be set if iic boot eprom is disabled.
+ */
+#define PLLMR0_DEFAULT	 PLLMR0_133_66_66_33
+#define PLLMR1_DEFAULT	 PLLMR1_133_66_66_33
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/VoVPN-GW.h b/qemu/roms/u-boot/include/configs/VoVPN-GW.h
new file mode 100644
index 000000000..1ceef113d
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/VoVPN-GW.h
@@ -0,0 +1,399 @@
+/*
+ * (C) Copyright 2004
+ * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de)
+ *
+ * Support for the Elmeg VoVPN Gateway Module
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* define cpu used */
+#define	CONFIG_MPC8272			1
+
+/* define busmode: 8260 */
+#undef	CONFIG_BUSMODE_60x
+
+#define	CONFIG_SYS_TEXT_BASE		0xfff00000
+
+/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
+#ifdef	CONFIG_CLKIN_66MHz
+#define	CONFIG_8260_CLKIN		66666666	/* in Hz */
+#else
+#define	CONFIG_8260_CLKIN		100000000	/* in Hz */
+#endif
+
+/* call board_early_init_f */
+#define	CONFIG_BOARD_EARLY_INIT_F	1
+
+/* have misc_init_r() function */
+#define CONFIG_MISC_INIT_R		1
+
+/* have reset_phy_r() function */
+#define CONFIG_RESET_PHY_R		1
+
+/* have special reset function */
+#define	CONFIG_HAVE_OWN_RESET		1
+
+/* allow serial and ethaddr to be overwritten */
+#define	CONFIG_ENV_OVERWRITE
+
+/* watchdog disabled */
+#undef	CONFIG_WATCHDOG
+
+/* include support for bzip2 compressed images */
+#undef	CONFIG_BZIP2
+
+/* status led */
+#undef	CONFIG_STATUS_LED		/* XXX jse */
+
+/* vendor parameter protection */
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * select serial console configuration
+ *
+ * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ */
+#define	CONFIG_CONS_ON_SMC
+#undef	CONFIG_CONS_ON_SCC
+#undef	CONFIG_CONS_NONE
+#define	CONFIG_CONS_INDEX		1
+
+/* serial port default baudrate */
+#define CONFIG_BAUDRATE			115200
+
+/* echo on for serial download	*/
+#define CONFIG_LOADS_ECHO		1
+
+/* don't allow baudrate change	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE
+
+/*
+ * select ethernet configuration
+ *
+ * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
+ * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
+ * for FCC)
+ *
+ * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
+ */
+#undef	CONFIG_ETHER_ON_SCC
+#define	CONFIG_ETHER_ON_FCC
+#undef	CONFIG_ETHER_NONE
+
+#ifdef	CONFIG_ETHER_ON_FCC
+
+/* which SCC/FCC channel for ethernet */
+#define	CONFIG_ETHER_INDEX		1
+
+/* Marvell Switch SMI base addr */
+#define CONFIG_SYS_PHY_ADDR			0x10
+
+/* FCC1 RMII REFCLK is CLK10 */
+#define CONFIG_SYS_CMXFCR_VALUE		CMXFCR_TF1CS_CLK10
+#define CONFIG_SYS_CMXFCR_MASK			(CMXFCR_FC1|CMXFCR_TF1CS_MSK)
+
+/* BDs and buffers on 60x bus */
+#define CONFIG_SYS_CPMFCR_RAMTYPE		0
+
+/* Local Protect, Full duplex, Flowcontrol, RMII */
+#define CONFIG_SYS_FCC_PSMR			(FCC_PSMR_LPB|FCC_PSMR_FDE|\
+					 FCC_PSMR_FCE|FCC_PSMR_RMII)
+
+/* bit-bang MII PHY management	*/
+#define CONFIG_BITBANGMII
+
+#define MDIO_PORT			1		/* Port B */
+
+#define MDIO_DECLARE		volatile ioport_t *iop = ioport_addr ( \
+					(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
+#define MDC_DECLARE		MDIO_DECLARE
+
+#define CONFIG_SYS_MDIO_PIN			0x00002000	/* PB18 */
+#define CONFIG_SYS_MDC_PIN			0x00001000	/* PB19 */
+#define MDIO_ACTIVE			(iop->pdir |=  CONFIG_SYS_MDIO_PIN)
+#define MDIO_TRISTATE			(iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
+#define MDIO_READ			((iop->pdat &  CONFIG_SYS_MDIO_PIN) != 0)
+#define MDIO(bit)			if(bit) iop->pdat |=  CONFIG_SYS_MDIO_PIN; \
+					else	iop->pdat &= ~CONFIG_SYS_MDIO_PIN
+#define MDC(bit)			if(bit) iop->pdat |=  CONFIG_SYS_MDC_PIN; \
+					else	iop->pdat &= ~CONFIG_SYS_MDC_PIN
+#define MIIDELAY			udelay(1)
+
+#endif
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_CONSOLE
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_IMLS
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_SOURCE
+
+
+/*
+ * boot options & environment
+ */
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_BOOTCOMMAND		"run flash_self"
+#undef  CONFIG_BOOTARGS
+#define	CONFIG_EXTRA_ENV_SETTINGS	\
+"clean_nv=erase fff20000 ffffffff\0" \
+"update_boss=tftp 100000 PPC/logic157.bin; protect off fff00000 ffffffff; erase fff00000 ffffffff; cp.b 100000 fff00000 ${filesize}; tftp 100000 PPC/bootmon157.bin; cp.b 100000 fff20000 ${filesize}\0" \
+"update_lx=tftp 100000 ${kernel}; erase ${kernel_addr} ffefffff; cp.b 100000 ${kernel_addr} ${filesize}\0" \
+"update_fs=tftp 100000 ${fs}.${fstype}; erase ff840000 ffdfffff; cp.b 100000 ff840000 ${filesize}\0" \
+"update_ub=tftp 100000 ${uboot}; protect off fff00000 fff1ffff; erase fff00000 fff1ffff; cp.b 100000 fff00000 ${filesize}; protect off ff820000 ff83ffff; erase ff820000 ff83ffff\0" \
+"flashargs=setenv bootargs root=${rootdev} rw rootfstype=${fstype}\0" \
+"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
+"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off\0" \
+"addmisc=setenv bootargs ${bootargs} console=${console},${baudrate} ethaddr=${ethaddr} panic=1\0" \
+"net_nfs=tftpboot 400000 ${kernel}; run nfsargs addip addmisc; bootm\0" \
+"net_self=tftpboot 400000 ${kernel}; run flashargs addmisc; bootm\0" \
+"flash_self=run flashargs addmisc; bootm ${kernel_addr}\0" \
+"flash_nfs=run nfsargs addip addmisc; bootm ${kernel_addr}\0" \
+"fstype=cramfs\0" \
+"rootpath=/root_fs\0" \
+"uboot=PPC/u-boot.bin\0" \
+"kernel=PPC/uImage\0" \
+"kernel_addr=ffe00000\0" \
+"fs=PPC/root_fs\0" \
+"console=ttyS0\0" \
+"netdev=eth0\0" \
+"rootdev=31:3\0" \
+"ethaddr=00:09:4f:01:02:03\0" \
+"ipaddr=10.0.0.201\0" \
+"netmask=255.255.255.0\0" \
+"serverip=10.0.0.136\0" \
+"gatewayip=10.0.0.10\0" \
+"hostname=bastard\0" \
+""
+
+
+/*
+ * miscellaneous configurable options
+ */
+
+/* undef to save memory */
+#define	CONFIG_SYS_LONGHELP
+
+/* monitor command prompt */
+
+/* console i/o buffer size */
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE			1024
+#else
+#define	CONFIG_SYS_CBSIZE			256
+#endif
+
+/* print buffer size */
+#define	CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* max number of command args */
+#define	CONFIG_SYS_MAXARGS			16
+
+/* boot argument buffer size */
+#define CONFIG_SYS_BARGSIZE			CONFIG_SYS_CBSIZE
+
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START		0x00100000
+/* 1 ... 15 MB in DRAM */
+#define CONFIG_SYS_MEMTEST_END			0x00f00000
+/* full featured memtest */
+#define CONFIG_SYS_ALT_MEMTEST
+
+/* default load address */
+#define	CONFIG_SYS_LOAD_ADDR			0x00100000
+
+/* decrementer freq: 1 ms ticks	*/
+
+/* configure flash */
+#define CONFIG_SYS_FLASH_BASE			0xff800000
+#define CONFIG_SYS_MAX_FLASH_BANKS		1
+#define CONFIG_SYS_MAX_FLASH_SECT		64
+#define CONFIG_SYS_FLASH_SIZE			8
+#undef	CONFIG_SYS_FLASH_16BIT
+#define CONFIG_SYS_FLASH_ERASE_TOUT		240000
+#define CONFIG_SYS_FLASH_WRITE_TOUT		500
+#define CONFIG_SYS_FLASH_LOCK_TOUT		500
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT		10000
+#define CONFIG_SYS_FLASH_PROTECTION
+
+/* monitor in flash */
+#define CONFIG_SYS_MONITOR_OFFSET		0x00700000
+
+/* environment in flash */
+#define CONFIG_ENV_IS_IN_FLASH		1
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x00020000)
+#define CONFIG_ENV_SIZE			0x00020000
+#define CONFIG_ENV_SECT_SIZE		0x00020000
+
+/*
+ * Initial memory map for linux
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ			(8 << 20)
+
+/* hard reset configuration words */
+#ifdef	CONFIG_CLKIN_66MHz
+#define CONFIG_SYS_HRCW_MASTER			0x04643050
+#else
+#error NO HRCW FOR 100MHZ SPECIFIED !!!
+#endif
+#define CONFIG_SYS_HRCW_SLAVE1			0x00000000
+#define CONFIG_SYS_HRCW_SLAVE2			0x00000000
+#define CONFIG_SYS_HRCW_SLAVE3			0x00000000
+#define CONFIG_SYS_HRCW_SLAVE4			0x00000000
+#define CONFIG_SYS_HRCW_SLAVE5			0x00000000
+#define CONFIG_SYS_HRCW_SLAVE6			0x00000000
+#define CONFIG_SYS_HRCW_SLAVE7			0x00000000
+
+/* internal memory mapped register */
+#define CONFIG_SYS_IMMR			0xF0000000
+
+/* definitions for initial stack pointer and data area (in DPRAM) */
+#define CONFIG_SYS_INIT_RAM_ADDR		CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_SIZE		0x2000
+#define CONFIG_SYS_GBL_DATA_OFFSET		(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET		CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE			0x00000000
+#define CONFIG_SYS_SDRAM_SIZE			(32*1024*1024)
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_FLASH		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_OFFSET)
+#define CONFIG_SYS_MONITOR_LEN			0x00020000
+#define CONFIG_SYS_MALLOC_LEN			0x00020000
+
+/* cache configuration */
+#define CONFIG_SYS_CACHELINE_SIZE		32      /* for MPC8260 */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT		5	/* log base 2 of above */
+#endif
+
+/*
+ * HIDx - Hardware Implementation-dependent Registers
+ *-----------------------------------------------------------------------
+ * HID0 also contains cache control - initially enable both caches and
+ * invalidate contents, then the final state leaves only the instruction
+ * cache enabled. Note that Power-On and Hard reset invalidate the caches,
+ * but Soft reset does not.
+ *
+ * HID1 has only read-only information - nothing to set.
+ */
+#define CONFIG_SYS_HID0_INIT			(HID0_ICE|HID0_DCE|\
+					 HID0_ICFI|HID0_DCI|HID0_IFEM|HID0_ABE)
+#define CONFIG_SYS_HID0_FINAL			(HID0_IFEM|HID0_ABE)
+#define CONFIG_SYS_HID2			0
+
+/* RMR - reset mode register - turn on checkstop reset enable */
+#define CONFIG_SYS_RMR				RMR_CSRE
+
+/* BCR - bus configuration */
+#define CONFIG_SYS_BCR				0x00000000
+
+/* SIUMCR - siu module configuration */
+#define CONFIG_SYS_SIUMCR			0x4905c000
+
+/* SYPCR - system protection control */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR			0xffffff87
+#else
+#define CONFIG_SYS_SYPCR			0xffffff83
+#endif
+
+/* TMCNTSC - time counter status and control */
+/* clear interrupts XXX jse */
+/*#define CONFIG_SYS_TMCNTSC			(TMCNTSC_SEC|TMCNTSC_ALR) */
+#define CONFIG_SYS_TMCNTSC			(TMCNTSC_SEC|TMCNTSC_ALR|\
+					 TMCNTSC_TCF|TMCNTSC_TCE)
+
+/* PISCR - periodic interrupt status and control */
+/* clear interrupts XXX jse */
+/*#define CONFIG_SYS_PISCR			(PISCR_PS) */
+#define CONFIG_SYS_PISCR			(PISCR_PS|PISCR_PTF|PISCR_PTE)
+
+/* SCCR - system clock control */
+#define CONFIG_SYS_SCCR			0x000001a9
+
+/* RCCR - risc controller configuration */
+#define CONFIG_SYS_RCCR			0
+
+/*
+ * MEMORY MAP
+ * ----------
+ * CS0 - FLASH    8MB/8Bit	base=0xff800000 (boot: 0xfe000000, 8x mirrored)
+ * CS1 - SDRAM   32MB/64Bit	base=0x00000000
+ * CS2 - DSP/SL1  1MB/16Bit	base=0xf0100000
+ * CS3 - DSP/SL2  1MB/16Bit	base=0xf0200000
+ * CS4 - DSP/SL3  1MB/16Bit	base=0xf0300000
+ * CS5 - DSP/SL4  1MB/16Bit	base=0xf0400000
+ * CS7 - DPRAM    1KB/8Bit	base=0xf0500000, size=32KB (32x mirrored)
+ *  x  - IMMR     384KB		base=0xf0000000
+ */
+/* XXX jse 100MHz TODO */
+#define CONFIG_SYS_BR0_PRELIM			0xff800801
+#define CONFIG_SYS_OR0_PRELIM			0xff801e44
+#define CONFIG_SYS_BR1_PRELIM			0x00000041
+#define CONFIG_SYS_OR1_PRELIM			0xfe002ec0
+#if 1
+#define CONFIG_SYS_BR2_PRELIM			0xf0101001
+#define CONFIG_SYS_OR2_PRELIM			0xfff00ef4
+#define CONFIG_SYS_BR3_PRELIM			0xf0201001
+#define CONFIG_SYS_OR3_PRELIM			0xfff00ef4
+#define CONFIG_SYS_BR4_PRELIM			0xf0301001
+#define CONFIG_SYS_OR4_PRELIM			0xfff00ef4
+#define CONFIG_SYS_BR5_PRELIM			0xf0401001
+#define CONFIG_SYS_OR5_PRELIM			0xfff00ef4
+#else
+#define CONFIG_SYS_BR2_PRELIM			0xf0101081
+#define CONFIG_SYS_OR2_PRELIM			0xfff00104
+#define CONFIG_SYS_BR3_PRELIM			0xf0201081
+#define CONFIG_SYS_OR3_PRELIM			0xfff00104
+#define CONFIG_SYS_BR4_PRELIM			0xf0301081
+#define CONFIG_SYS_OR4_PRELIM			0xfff00104
+#define CONFIG_SYS_BR5_PRELIM			0xf0401081
+#define CONFIG_SYS_OR5_PRELIM			0xfff00104
+#endif
+#define CONFIG_SYS_BR7_PRELIM			0xf0500881
+#define CONFIG_SYS_OR7_PRELIM			0xffff8104
+#define CONFIG_SYS_MPTPR			0x2700
+#define CONFIG_SYS_PSDMR			0x822a2452	/* optimal */
+/*#define CONFIG_SYS_PSDMR			0x822a48a3 */	/* relaxed */
+#define CONFIG_SYS_PSRT			0x1a
+
+/* "bad" address */
+#define	CONFIG_SYS_RESET_ADDRESS		0x40000000
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/W7OLMC.h b/qemu/roms/u-boot/include/configs/W7OLMC.h
new file mode 100644
index 000000000..895ad4611
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/W7OLMC.h
@@ -0,0 +1,314 @@
+/*
+ * (C) Copyright 2001
+ * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405GP		1		/* This is a PPC405GP CPU	*/
+#define CONFIG_W7O		1		/* ...on a Wave 7 Optics board	*/
+#define CONFIG_W7OLMC		1		/* ...specifically an LMC	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
+
+#define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_early_init_f	*/
+#define	CONFIG_MISC_INIT_F	1		/* and misc_init_f()		*/
+#define	CONFIG_MISC_INIT_R	1		/* and misc_init_r()		*/
+
+#define CONFIG_SYS_CLK_FREQ	33333333	/* external frequency to pll	*/
+
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	3		/* autoboot after 3 seconds	*/
+
+#if 1
+#define CONFIG_BOOTCOMMAND	"bootvx"	/* VxWorks boot command		*/
+#else
+#define CONFIG_BOOTCOMMAND	"bootp"		/* autoboot command		*/
+#endif
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_LOADADDR		F0080000
+
+#define CONFIG_ETHADDR		00:06:0D:00:00:00 /* Default, overridden at boot	*/
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
+#define CONFIG_IPADDR		192.168.1.1
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_SERVERIP		192.168.1.2
+
+#define CONFIG_LOADS_ECHO	1		/* echo on for serial download	*/
+#undef CONFIG_SYS_LOADS_BAUD_CHANGE			/* disallow baudrate change	*/
+
+#define CONFIG_PPC4xx_EMAC
+#define CONFIG_MII		1		/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0		/* PHY address			*/
+
+#define CONFIG_RTC_M48T35A	1		/* ST Electronics M48 timekeeper */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_REGINFO
+
+#undef CONFIG_WATCHDOG				/* watchdog disabled		*/
+#define CONFIG_HW_WATCHDOG			/* HW Watchdog, board specific	*/
+
+#define	CONFIG_SPD_EEPROM			/* SPD EEPROM for SDRAM param.	*/
+#define CONFIG_SPDDRAM_SILENT			/* No output if spd fails	*/
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT		"Wave7Optics> " /* Monitor Command Prompt	*/
+#undef  CONFIG_SYS_HUSH_PARSER				/* No hush parse for U-Boot       */
+#ifdef  CONFIG_SYS_HUSH_PARSER
+#endif
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size	*/
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM		*/
+
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+
+#undef  CONFIG_SYS_EXT_SERIAL_CLOCK			/* external serial clock */
+#define CONFIG_SYS_405_UART_ERRATA_59			/* 405GP/CR Rev. D silicon */
+#define CONFIG_SYS_BASE_BAUD		384000
+
+
+/* The following table includes the supported baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	{9600}
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address		*/
+#define CONFIG_SYS_EXTBDINFO		1		/* use extended board_info (bd_t) */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER	0		/* configure as pci adapter	*/
+#define PCI_HOST_FORCE		1		/* configure as pci host	*/
+#define PCI_HOST_AUTO		2		/* detected via arbiter enable	*/
+
+
+#define CONFIG_PCI				/* include pci support		*/
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_HOST		PCI_HOST_AUTO	/* select pci host function	*/
+#define CONFIG_PCI_PNP				/* pci plug-and-play		*/
+/* resource configuration	*/
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014		/* PCI Vendor ID: IBM		*/
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0156		/* PCI Device ID: 405GP		*/
+#define CONFIG_SYS_PCI_PTM1LA		0x00000000	/* point to sdram		*/
+#define CONFIG_SYS_PCI_PTM1MS		0x80000001	/* 2GB, enable hard-wired to 1	*/
+#define CONFIG_SYS_PCI_PTM1PCI		0x00000000      /* Host: use this pci address   */
+#define CONFIG_SYS_PCI_PTM2LA		0x00000000	/* disabled			*/
+#define CONFIG_SYS_PCI_PTM2MS		0x00000000	/* disabled			*/
+#define CONFIG_SYS_PCI_PTM2PCI		0x00000000      /* Host: use this pci address   */
+
+/*-----------------------------------------------------------------------
+ * Set up values for external bus controller
+ * used by cpu_init.c
+ *-----------------------------------------------------------------------
+ */
+ /* Don't use PerWE instead of PCI_INT ( these functions share a pin ) */
+#undef CONFIG_USE_PERWE
+
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CONFIG_SYS_TEMP_STACK_OCM        1
+
+/* bank 0 is boot flash */
+/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
+#define CONFIG_SYS_W7O_EBC_PB0AP   0x03050440
+/* BAS=0xFFE,BS=0x1(2MB),BU=0x3(R/W),BW=0x0(8 bits) */
+#define CONFIG_SYS_W7O_EBC_PB0CR   0xFFE38000
+
+/* bank 1 is main flash */
+/* BME=0,TWT=11,CSN=1,OEN=1,WBN=0,WBF=0,TH=1,RE=0,SOR=0,BEM=1,PEN=0 */
+#define CONFIG_SYS_EBC_PB1AP   0x05850240
+/* BAS=0xF00,BS=0x7(128MB),BU=0x3(R/W),BW=0x10(32 bits) */
+#define CONFIG_SYS_EBC_PB1CR   0xF00FC000
+
+/* bank 2 is RTC/NVRAM */
+/* BME=0,TWT=6,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
+#define CONFIG_SYS_EBC_PB2AP   0x03000440
+/* BAS=0xFC0,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
+#define CONFIG_SYS_EBC_PB2CR   0xFC018000
+
+/* bank 3 is FPGA 0 */
+/* BME=0,TWT=4,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=0,PEN=0 */
+#define CONFIG_SYS_EBC_PB3AP   0x02000400
+/* BAS=0xFD0,BS=0x0(1MB),BU=0x3(R/W),BW=0x1(16 bits) */
+#define CONFIG_SYS_EBC_PB3CR   0xFD01A000
+
+/* bank 4 is FPGA 1 */
+/* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */
+#define CONFIG_SYS_EBC_PB4AP   0x02000400
+/* BAS=,BS=,BU=0x3(R/W),BW=0x0(8 bits) */
+#define CONFIG_SYS_EBC_PB4CR   0xFD11A000
+
+/* bank 5 is FPGA 2 */
+/* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */
+#define CONFIG_SYS_EBC_PB5AP   0x02000400
+/* BAS=,BS=,BU=0x3(R/W),BW=0x1(16 bits) */
+#define CONFIG_SYS_EBC_PB5CR   0xFD21A000
+
+/* bank 6 is unused */
+/* PB6AP = 0 */
+#define CONFIG_SYS_EBC_PB6AP   0x00000000
+/* PB6CR = 0 */
+#define CONFIG_SYS_EBC_PB6CR   0x00000000
+
+/* bank 7 is LED register */
+/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
+#define CONFIG_SYS_W7O_EBC_PB7AP   0x03050440
+/* BAS=0xFE0,BS=0x0(1MB),BU=0x3(R/W),BW=0x2(32 bits) */
+#define CONFIG_SYS_W7O_EBC_PB7CR   0xFE01C000
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFFC0000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* max number of memory banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256		/* max number of sec on 1 chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000		/* Timeout, Flash Erase, in ms	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Timeout, Flash Write, in ms	*/
+#define CONFIG_SYS_FLASH_PROTECTION	1		/* Use real Flash protection	*/
+
+#if 1 /* Use NVRAM for environment variables */
+/*-----------------------------------------------------------------------
+ * NVRAM organization
+ */
+#define CONFIG_ENV_IS_IN_NVRAM	1		/* use NVRAM for env vars	*/
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xfc000000	/* NVRAM base address		*/
+#define CONFIG_SYS_NVRAM_SIZE		(32*1024)	/* NVRAM size			*/
+#define CONFIG_ENV_SIZE		0x1000		/* Size of Environment vars	*/
+/*define CONFIG_ENV_ADDR		 \
+	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) Env  */
+#define CONFIG_ENV_ADDR		CONFIG_SYS_NVRAM_BASE_ADDR
+
+#else /* Use Boot Flash for environment variables */
+/*-----------------------------------------------------------------------
+ * Flash EEPROM for environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_OFFSET		0x00040000	/* Offset of Environment Sector */
+#define CONFIG_ENV_SIZE		0x10000		/* Total Size of env. sector	*/
+
+#define CONFIG_ENV_SECT_SIZE	0x10000		/* see README - env sec tot sze */
+#endif
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC08) for environment
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"    */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last	4 bits of the address	*/
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+/*-----------------------------------------------------------------------
+ * Definitions for Serial Presence Detect EEPROM address
+ * (to get SDRAM settings)
+ */
+#define SPD_EEPROM_ADDRESS      0x50	/* XXX conflicting address!!! XXX */
+
+/*
+ * Init Memory Controller:
+ */
+#define FLASH_BASE0_PRELIM	0xFFE00000	/* FLASH bank #0		*/
+#define FLASH_BASE1_PRELIM	0xF0000000	/* FLASH bank #1		*/
+
+/* On Chip Memory location */
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in RAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
+#endif
+
+/*
+ * FPGA(s) configuration
+ */
+#define CONFIG_SYS_FPGA_IMAGE_LEN	0x80000		/* 512KB FPGA image		*/
+#define CONFIG_NUM_FPGAS	3		/* Number of FPGAs on board	*/
+#define CONFIG_MAX_FPGAS	6		/* Maximum number of FPGAs	*/
+#define CONFIG_FPGAS_BASE	0xFD000000L	/* Base address of FPGAs	*/
+#define CONFIG_FPGAS_BANK_SIZE	0x00100000L	/* FPGAs' mmap bank size	*/
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/W7OLMG.h b/qemu/roms/u-boot/include/configs/W7OLMG.h
new file mode 100644
index 000000000..2a38116dd
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/W7OLMG.h
@@ -0,0 +1,317 @@
+/*
+ * (C) Copyright 2001
+ * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405GP		1		/* This is a PPC405GP CPU	*/
+#define CONFIG_W7O		1		/* ...on a Wave 7 Optics board	*/
+#define CONFIG_W7OLMG		1		/* ...specifically an LMG	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
+
+#define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_early_init_f	*/
+#define	CONFIG_MISC_INIT_F	1		/* and misc_init_f()		*/
+#define	CONFIG_MISC_INIT_R	1		/* and misc_init_r()		*/
+
+#define CONFIG_SYS_CLK_FREQ	33333333	/* external frequency to pll	*/
+
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	3		/* autoboot after 3 seconds	*/
+
+#if 1
+#define CONFIG_BOOTCOMMAND	"bootvx"	/* VxWorks boot command		*/
+#else
+#define CONFIG_BOOTCOMMAND	"bootp"		/* autoboot command		*/
+#endif
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_LOADADDR		F0080000
+
+#define CONFIG_ETHADDR		00:06:0D:00:00:00 /* Default, overridden at boot	*/
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
+#define CONFIG_IPADDR		192.168.1.1
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_SERVERIP		192.168.1.2
+
+#define CONFIG_LOADS_ECHO	1		/* echo on for serial download	*/
+#undef CONFIG_SYS_LOADS_BAUD_CHANGE			/* disallow baudrate change	*/
+
+#define CONFIG_PPC4xx_EMAC
+#define CONFIG_MII		1		/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0		/* PHY address			*/
+
+#define CONFIG_RTC_M48T35A	1		/* ST Electronics M48 timekeeper */
+#define CONFIG_DTT_LM75     1                /* ON Semi's LM75 */
+#define CONFIG_DTT_SENSORS  {2, 4}           /* Sensor addresses */
+#define CONFIG_SYS_DTT_MAX_TEMP	70
+#define CONFIG_SYS_DTT_LOW_TEMP	-30
+#define CONFIG_SYS_DTT_HYSTERESIS	3
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_DTT
+
+
+#undef CONFIG_WATCHDOG				/* watchdog disabled		*/
+#define CONFIG_HW_WATCHDOG			/* HW Watchdog, board specific	*/
+
+#define	CONFIG_SPD_EEPROM			/* SPD EEPROM for SDRAM param.	*/
+#define CONFIG_SPDDRAM_SILENT			/* No output if spd fails	*/
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT		"Wave7Optics> " /* Monitor Command Prompt	*/
+#undef  CONFIG_SYS_HUSH_PARSER				/* No hush parse for U-Boot       */
+#ifdef  CONFIG_SYS_HUSH_PARSER
+#endif
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size	*/
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM		*/
+
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+
+#undef  CONFIG_SYS_EXT_SERIAL_CLOCK			/* external serial clock */
+#define CONFIG_SYS_405_UART_ERRATA_59			/* 405GP/CR Rev. D silicon */
+#define CONFIG_SYS_BASE_BAUD		384000
+
+
+/* The following table includes the supported baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	{9600}
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address		*/
+#define CONFIG_SYS_EXTBDINFO		1		/* use extended board_info (bd_t) */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER	0		/* configure as pci adapter	*/
+#define PCI_HOST_FORCE		1		/* configure as pci host	*/
+#define PCI_HOST_AUTO		2		/* detected via arbiter enable	*/
+
+#define CONFIG_PCI				/* include pci support		*/
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_HOST		PCI_HOST_AUTO	/* select pci host function	*/
+#define CONFIG_PCI_PNP				/* pci plug-and-play		*/
+/* resource configuration	*/
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014		/* PCI Vendor ID: IBM		*/
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0156		/* PCI Device ID: 405GP		*/
+#define CONFIG_SYS_PCI_PTM1LA		0x00000000	/* point to sdram		*/
+#define CONFIG_SYS_PCI_PTM1MS		0x80000001	/* 2GB, enable hard-wired to 1	*/
+#define CONFIG_SYS_PCI_PTM1PCI		0x00000000      /* Host: use this pci address   */
+#define CONFIG_SYS_PCI_PTM2LA		0x00000000	/* disabled			*/
+#define CONFIG_SYS_PCI_PTM2MS		0x00000000	/* disabled			*/
+#define CONFIG_SYS_PCI_PTM2PCI		0x00000000      /* Host: use this pci address   */
+
+/*-----------------------------------------------------------------------
+ * Set up values for external bus controller
+ * used by cpu_init.c
+ *-----------------------------------------------------------------------
+ */
+ /* use PerWE instead of PCI_INT ( these functions share a pin ) */
+#define CONFIG_USE_PERWE 1
+
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CONFIG_SYS_TEMP_STACK_OCM        1
+
+/* bank 0 is boot flash */
+/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
+#define CONFIG_SYS_W7O_EBC_PB0AP   0x03050440
+/* BAS=0xFFE,BS=0x1(2MB),BU=0x3(R/W),BW=0x0(8 bits) */
+#define CONFIG_SYS_W7O_EBC_PB0CR   0xFFE38000
+
+/* bank 1 is main flash */
+/* BME=0,TWT=9,CSN=1,OEN=1,WBN=0,WBF=0,TH=1,RE=0,SOR=0,BEM=1,PEN=0 */
+#define CONFIG_SYS_EBC_PB1AP   0x04850240
+/* BAS=0xF00,BS=0x7(128MB),BU=0x3(R/W),BW=0x10(32 bits) */
+#define CONFIG_SYS_EBC_PB1CR   0xF00FC000
+
+/* bank 2 is RTC/NVRAM */
+/* BME=0,TWT=6,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
+#define CONFIG_SYS_EBC_PB2AP   0x03000440
+/* BAS=0xFC0,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
+#define CONFIG_SYS_EBC_PB2CR   0xFC018000
+
+/* bank 3 is FPGA 0 */
+/* BME=0,TWT=4,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=0,PEN=0 */
+#define CONFIG_SYS_EBC_PB3AP   0x02000400
+/* BAS=0xFD0,BS=0x0(1MB),BU=0x3(R/W),BW=0x1(16 bits) */
+#define CONFIG_SYS_EBC_PB3CR   0xFD01A000
+
+/* bank 4 is SAM 8 bit range */
+/* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */
+#define CONFIG_SYS_EBC_PB4AP   0x02840380
+/* BAS=,BS=,BU=0x3(R/W),BW=0x0(8 bits) */
+#define CONFIG_SYS_EBC_PB4CR   0xFE878000
+
+/* bank 5 is SAM 16 bit range */
+/* BME=0,TWT=10,CSN=2,OEN=0,WBN=0,WBF=0,TH=6,RE=1,SOR=1,BEM=0,PEN=0 */
+#define CONFIG_SYS_EBC_PB5AP   0x05040d80
+/* BAS=,BS=,BU=0x3(R/W),BW=0x1(16 bits) */
+#define CONFIG_SYS_EBC_PB5CR   0xFD87A000
+
+/* bank 6 is unused */
+/* PB6AP = 0 */
+#define CONFIG_SYS_EBC_PB6AP   0x00000000
+/* PB6CR = 0 */
+#define CONFIG_SYS_EBC_PB6CR   0x00000000
+
+/* bank 7 is LED register */
+/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
+#define CONFIG_SYS_W7O_EBC_PB7AP   0x03050440
+/* BAS=0xFE0,BS=0x0(1MB),BU=0x3(R/W),BW=0x2(32 bits) */
+#define CONFIG_SYS_W7O_EBC_PB7CR   0xFE01C000
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFFC0000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 196 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* max number of memory banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256		/* max number of sec on 1 chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000		/* Timeout, Flash Erase, in ms	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Timeout, Flash Write, in ms	*/
+#define CONFIG_SYS_FLASH_PROTECTION	1		/* Use real Flash protection	*/
+
+#if 1 /* Use NVRAM for environment variables */
+/*-----------------------------------------------------------------------
+ * NVRAM organization
+ */
+#define CONFIG_ENV_IS_IN_NVRAM	1		/* use NVRAM for env vars	*/
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xfc000000	/* NVRAM base address		*/
+#define CONFIG_SYS_NVRAM_SIZE		(32*1024)	/* NVRAM size			*/
+#define CONFIG_ENV_SIZE		0x1000		/* Size of Environment vars	*/
+/*define CONFIG_ENV_ADDR		 \
+	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) Env  */
+#define CONFIG_ENV_ADDR		CONFIG_SYS_NVRAM_BASE_ADDR
+
+#else /* Use Boot Flash for environment variables */
+/*-----------------------------------------------------------------------
+ * Flash EEPROM for environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_OFFSET		0x00040000	/* Offset of Environment Sector */
+#define CONFIG_ENV_SIZE		0x10000		/* Total Size of env. sector	*/
+
+#define CONFIG_ENV_SECT_SIZE	0x10000		/* see README - env sec tot sze */
+#endif
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (ATMEL 24C04N)
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50		/* EEPROM ATMEL 24C04N		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1		/* Bytes of address		*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+/*-----------------------------------------------------------------------
+ * Definitions for Serial Presence Detect EEPROM address
+ * (to get SDRAM settings)
+ */
+#define SPD_EEPROM_ADDRESS      0x50	/* XXX conflicting address!!! XXX */
+
+/*
+ * Init Memory Controller:
+ */
+#define FLASH_BASE0_PRELIM	0xFFE00000	/* FLASH bank #0		*/
+#define FLASH_BASE1_PRELIM	0xF0000000	/* FLASH bank #1		*/
+
+/* On Chip Memory location */
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in RAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
+#endif
+
+/*
+ * FPGA(s) configuration
+ */
+#define CONFIG_SYS_FPGA_IMAGE_LEN	0x80000		/* 512KB FPGA image		*/
+#define CONFIG_NUM_FPGAS	1		/* Number of FPGAs on board	*/
+#define CONFIG_MAX_FPGAS	6		/* Maximum number of FPGAs	*/
+#define CONFIG_FPGAS_BASE	0xFD000000L	/* Base address of FPGAs	*/
+#define CONFIG_FPGAS_BANK_SIZE	0x00100000L	/* FPGAs' mmap bank size	*/
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/WUH405.h b/qemu/roms/u-boot/include/configs/WUH405.h
new file mode 100644
index 000000000..e4f0d19a4
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/WUH405.h
@@ -0,0 +1,346 @@
+/*
+ * (C) Copyright 2004
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_IDENT_STRING     " $Name:  $"
+
+#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_WUH405		1	/* ...on a WUH405 board		*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
+
+#define CONFIG_SYS_CLK_FREQ	33333300 /* external frequency to pll	*/
+
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
+
+#undef	CONFIG_BOOTARGS
+#undef  CONFIG_BOOTCOMMAND
+
+#define CONFIG_PREBOOT                  /* enable preboot variable      */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_PPC4xx_EMAC
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+
+#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_EEPROM
+
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_RTC_MC146818		/* DS1685 is MC146818 compatible*/
+#define CONFIG_SYS_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address		*/
+
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+
+#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CONFIG_CONS_INDEX	2	/* Use UART1			*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#define CONFIG_SYS_BASE_BAUD	    691200
+
+/* The following table includes the supported baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+#define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+
+/*-----------------------------------------------------------------------
+ * NAND-FLASH stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1         /* Max number of NAND devices */
+#define NAND_BIG_DELAY_US	25
+
+#define CONFIG_SYS_NAND_CE             (0x80000000 >> 1)   /* our CE is GPIO1  */
+#define CONFIG_SYS_NAND_RDY            (0x80000000 >> 4)   /* our RDY is GPIO4 */
+#define CONFIG_SYS_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
+#define CONFIG_SYS_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
+
+#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I      1  /* ".i" read skips bad blocks   */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_HOST PCI_HOST_HOST	/* select pci host function	*/
+#undef	CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+					/* resource configuration	*/
+
+#undef	CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
+#define CONFIG_SYS_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
+#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CONFIG_SYS_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CONFIG_SYS_PCI_PTM2LA	0xffc00000	/* point to flash		*/
+#define CONFIG_SYS_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
+#define CONFIG_SYS_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFFC0000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
+
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
+#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#if 0 /* test-only */
+#define CONFIG_SYS_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
+#define CONFIG_SYS_JFFS2_NUM_BANKS	1	    /* ! second bank contains U-Boot */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Environment Variable setup
+ */
+#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CONFIG_ENV_OFFSET		0x100	/* environment starts at the beginning of the EEPROM */
+#define CONFIG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
+				   /* total size of a CAT24WC16 is 2048 bytes */
+
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
+#define CONFIG_SYS_NVRAM_SIZE		242			/* NVRAM size		*/
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC16) for environment
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
+					/* 16 byte page write mode using*/
+					/* last 4 bits of the address	*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
+#define CONFIG_SYS_EBC_PB0AP		0x92015480
+/*#define CONFIG_SYS_EBC_PB0AP		  0x08055880  /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
+#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization			*/
+#define CONFIG_SYS_EBC_PB1AP		0x92015480
+#define CONFIG_SYS_EBC_PB1CR		0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization		*/
+#define CONFIG_SYS_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization	*/
+#define CONFIG_SYS_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CONFIG_SYS_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+
+#define CAN_BA		0xF0000000	    /* CAN Base Address			*/
+#define DUART0_BA	0xF0000400	    /* DUART Base Address		*/
+#define DUART1_BA	0xF0000408	    /* DUART Base Address		*/
+#define DUART2_BA	0xF0000410	    /* DUART Base Address		*/
+#define DUART3_BA	0xF0000418	    /* DUART Base Address		*/
+#define RTC_BA		0xF0000500	    /* RTC Base Address			*/
+#define CONFIG_SYS_NAND_BASE	0xF4000000
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ */
+#define CONFIG_SYS_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
+#define CONFIG_SYS_FPGA_MAX_SIZE	128*1024    /* 128kByte is enough for XC2S50E*/
+
+/* FPGA program pin configuration */
+#define CONFIG_SYS_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
+#define CONFIG_SYS_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
+#define CONFIG_SYS_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
+#define CONFIG_SYS_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
+#define CONFIG_SYS_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CONFIG_SYS_TEMP_STACK_OCM	  1
+
+/* On Chip Memory location */
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
+
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO setup (PPC405EP specific)
+ *
+ * GPIO0[0]	- External Bus Controller BLAST output
+ * GPIO0[1-9]	- Instruction trace outputs -> GPIO
+ * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
+ * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
+ * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
+ * GPIO0[24-27] - UART0 control signal inputs/outputs
+ * GPIO0[28-29] - UART1 data signal input/output
+ * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
+ */
+#define CONFIG_SYS_GPIO0_OSRL		0x40000550
+#define CONFIG_SYS_GPIO0_OSRH		0x00000110
+#define CONFIG_SYS_GPIO0_ISR1L		0x00000000
+#define CONFIG_SYS_GPIO0_ISR1H		0x15555445
+#define CONFIG_SYS_GPIO0_TSRL		0x00000000
+#define CONFIG_SYS_GPIO0_TSRH		0x00000000
+#define CONFIG_SYS_GPIO0_TCR		0xF7FE0014
+
+#define CONFIG_SYS_DUART_RST		(0x80000000 >> 14)
+
+/*
+ * Default speed selection (cpu_plb_opb_ebc) in mhz.
+ * This value will be set if iic boot eprom is disabled.
+ */
+#if 0
+#define PLLMR0_DEFAULT	 PLLMR0_266_133_66_33
+#define PLLMR1_DEFAULT	 PLLMR1_266_133_66_33
+#endif
+#if 1
+#define PLLMR0_DEFAULT	 PLLMR0_200_100_50_33
+#define PLLMR1_DEFAULT	 PLLMR1_200_100_50_33
+#endif
+#if 0
+#define PLLMR0_DEFAULT	 PLLMR0_133_66_66_33
+#define PLLMR1_DEFAULT	 PLLMR1_133_66_66_33
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/ZPC1900.h b/qemu/roms/u-boot/include/configs/ZPC1900.h
new file mode 100644
index 000000000..d76a14072
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/ZPC1900.h
@@ -0,0 +1,261 @@
+/*
+ * Copyright (C) 2003-2005 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * U-Boot configuration for Zephyr Engineering ZPC.1900 board.
+ * This port was developed and tested on Revision C board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_ZPC1900		1	/* ...on Zephyr ZPC.1900 board */
+
+#define	CONFIG_SYS_TEXT_BASE	0xFE000000
+
+#define CPU_ID_STR		"MPC8265"
+#define CONFIG_CPM2		1	/* Has a CPM2 */
+
+/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * Select serial console configuration
+ *
+ * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ */
+#define	CONFIG_CONS_ON_SMC		/* Console is on SMC         */
+#undef  CONFIG_CONS_ON_SCC		/* It's not on SCC           */
+#undef	CONFIG_CONS_NONE		/* It's not on external UART */
+#define CONFIG_CONS_INDEX	1	/* SMC1 is used for console  */
+
+/*
+ * Select ethernet configuration
+ *
+ * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
+ * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
+ * SCC, 1-3 for FCC)
+ *
+ * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
+ * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
+ * must be unset.
+ */
+#undef	CONFIG_ETHER_ON_SCC		/* Ethernet is not on SCC */
+#define CONFIG_ETHER_ON_FCC		/* Ethernet is on FCC     */
+#undef	CONFIG_ETHER_NONE		/* No external Ethernet   */
+
+#ifdef CONFIG_ETHER_ON_FCC
+
+#define CONFIG_ETHER_INDEX	2	/* FCC2 is used for Ethernet */
+
+#if (CONFIG_ETHER_INDEX == 2)
+/*
+ * - Rx clock is CLK13
+ * - Tx clock is CLK14
+ * - Select bus for bd/buffers (see 28-13)
+ * - Full duplex
+ */
+# define CONFIG_SYS_CMXFCR_MASK2	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
+# define CONFIG_SYS_CPMFCR_RAMTYPE	0
+# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
+
+#endif /* CONFIG_ETHER_INDEX */
+
+#define CONFIG_MII			/* MII PHY management        */
+#define CONFIG_BITBANGMII		/* Bit-banged MDIO interface */
+/*
+ * GPIO pins used for bit-banged MII communications
+ */
+#define MDIO_PORT		2	/* Port C */
+#define MDIO_DECLARE		volatile ioport_t *iop = ioport_addr ( \
+					(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
+#define MDC_DECLARE		MDIO_DECLARE
+
+#define MDIO_ACTIVE		(iop->pdir |=  0x00400000)
+#define MDIO_TRISTATE		(iop->pdir &= ~0x00400000)
+#define MDIO_READ		((iop->pdat &  0x00400000) != 0)
+
+#define MDIO(bit)		if(bit) iop->pdat |=  0x00400000; \
+				else	iop->pdat &= ~0x00400000
+
+#define MDC(bit)		if(bit) iop->pdat |=  0x00200000; \
+				else	iop->pdat &= ~0x00200000
+
+#define MIIDELAY		udelay(1)
+
+#endif /* CONFIG_ETHER_ON_FCC */
+
+#ifndef CONFIG_8260_CLKIN
+#define CONFIG_8260_CLKIN	66666666	/* in Hz */
+#endif
+
+#define CONFIG_BAUDRATE		38400
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+#define CONFIG_BOOTCOMMAND	"dhcp;bootm"	/* autoboot command */
+#define CONFIG_BOOTARGS		"root=/dev/nfs rw ip=:::::eth0:dhcp"
+
+#if defined(CONFIG_CMD_KGDB)
+#undef	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
+#define CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
+#undef	CONFIG_KGDB_NONE		/* define if kgdb on something else */
+#define CONFIG_KGDB_INDEX	2	/* which serial channel for kgdb */
+#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port at */
+#endif
+
+#define CONFIG_BZIP2	/* include support for bzip2 compressed images */
+#undef	CONFIG_WATCHDOG			/* disable platform specific watchdog */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size  */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size  */
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x03800000	/* 1 ... 56 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x400000	/* default load address */
+
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_SIZE		64
+
+#define CONFIG_SYS_IMMR		0xF0000000
+#define CONFIG_SYS_LSDRAM_BASE		0xFC000000
+#define CONFIG_SYS_FLASH_BASE		0xFE000000
+#define CONFIG_SYS_BCSR		0xFEA00000
+#define CONFIG_SYS_EEPROM		0xFEB00000
+#define CONFIG_SYS_FLSIMM_BASE		0xFF000000
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max num of flash banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	32	/* max num of sects on one chip */
+
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLSIMM_BASE }
+
+#define BCSR_PCI_MODE		0x01
+
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/* Hard reset configuration word */
+#define CONFIG_SYS_HRCW_MASTER		(HRCW_EBM | HRCW_BPS01| HRCW_CIP          |\
+				 HRCW_L2CPC10 | HRCW_DPPC00 | HRCW_ISB100 |\
+				 HRCW_BMS | HRCW_LBPC00 | HRCW_APPC10     |\
+				 HRCW_MODCK_H0111                          \
+				) /* 0x16848207 */
+/* No slaves */
+#define CONFIG_SYS_HRCW_SLAVE1		0
+#define CONFIG_SYS_HRCW_SLAVE2		0
+#define CONFIG_SYS_HRCW_SLAVE3		0
+#define CONFIG_SYS_HRCW_SLAVE4		0
+#define CONFIG_SYS_HRCW_SLAVE5		0
+#define CONFIG_SYS_HRCW_SLAVE6		0
+#define CONFIG_SYS_HRCW_SLAVE7		0
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(4096 << 10)	/* Reserve 4 MB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+#if !defined(CONFIG_ENV_IS_IN_FLASH) && !defined(CONFIG_ENV_IS_IN_NVRAM)
+#define CONFIG_ENV_IS_IN_NVRAM	1
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#  define CONFIG_ENV_SECT_SIZE	0x10000
+#  define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#else
+#  define CONFIG_ENV_ADDR		(CONFIG_SYS_EEPROM + 0x400)
+#  define CONFIG_ENV_SIZE		0x1000
+#  define CONFIG_SYS_NVRAM_ACCESS_ROUTINE
+#endif
+
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPU */
+#if defined(CONFIG_CMD_KGDB)
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+#define CONFIG_SYS_HID0_INIT		(HID0_ICFI)
+#define CONFIG_SYS_HID0_FINAL		(HID0_ICE | HID0_IFEM | HID0_ABE)
+
+#define CONFIG_SYS_HID2		0
+
+#define CONFIG_SYS_SIUMCR		0x42200000
+#define CONFIG_SYS_SYPCR		0xFFFFFFC3
+#define CONFIG_SYS_BCR			0x90000000
+#define CONFIG_SYS_SCCR		SCCR_DFBRG01
+
+#define CONFIG_SYS_RMR			RMR_CSRE
+#define CONFIG_SYS_TMCNTSC		(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+#define CONFIG_SYS_PISCR		(PISCR_PS|PISCR_PTF|PISCR_PTE)
+#define CONFIG_SYS_RCCR		0
+
+#define CONFIG_SYS_PSDMR		/* 0x834DA43B */0x014DA43A
+#define CONFIG_SYS_PSRT		0x0F/* 0x0C */
+#define CONFIG_SYS_LSDMR		0x0085A562
+#define CONFIG_SYS_LSRT		0x0F
+#define CONFIG_SYS_MPTPR		0x4000
+
+#define CONFIG_SYS_PSDRAM_BR		(CONFIG_SYS_SDRAM_BASE | 0x00000041)
+#define CONFIG_SYS_PSDRAM_OR		0xFC0028C0
+#define CONFIG_SYS_LSDRAM_BR		(CONFIG_SYS_LSDRAM_BASE | 0x00001861)
+#define CONFIG_SYS_LSDRAM_OR		0xFF803480
+
+#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | 0x00000801)
+#define CONFIG_SYS_OR0_PRELIM		0xFFE00856
+#define CONFIG_SYS_BR5_PRELIM		(CONFIG_SYS_EEPROM | 0x00000801)
+#define CONFIG_SYS_OR5_PRELIM		0xFFFF03F6
+#define CONFIG_SYS_BR6_PRELIM		(CONFIG_SYS_FLSIMM_BASE | 0x00001801)
+#define CONFIG_SYS_OR6_PRELIM		0xFF000856
+#define CONFIG_SYS_BR7_PRELIM		(CONFIG_SYS_BCSR | 0x00000801)
+#define CONFIG_SYS_OR7_PRELIM		0xFFFF83F6
+
+#define CONFIG_SYS_RESET_ADDRESS	0xC0000000
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/ZUMA.h b/qemu/roms/u-boot/include/configs/ZUMA.h
new file mode 100644
index 000000000..cac6a677b
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/ZUMA.h
@@ -0,0 +1,370 @@
+/*
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_GT_6426x        GT_64260 /* with a 64260 system controller */
+#define CONFIG_ETHER_PORT_MII	/* use two MII ports */
+#define CONFIG_INTEL_LXT97X	/* Intel LXT97X phy */
+
+#ifndef __ASSEMBLY__
+#include <galileo/core.h>
+#endif
+
+#include "../board/evb64260/local.h"
+
+#define CONFIG_EVB64260		1	/* this is an EVB64260 board	*/
+#define CONFIG_ZUMA_V2		1	/* always define this for ZUMA v2 */
+
+#define	CONFIG_SYS_TEXT_BASE	0xfff00000
+
+/* #define CONFIG_ZUMA_V2_OLD	1 */	/* backwards compat for old V2 board */
+
+#define CONFIG_BAUDRATE		38400	/* console baudrate = 38400	*/
+
+#define CONFIG_ECC			/* enable ECC support */
+
+#define CONFIG_750CX			/* we have a 750CX/CXe (override local.h) */
+
+/* which initialization functions to call for this board */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_SYS_BOARD_ASM_INIT
+
+#define CONFIG_SYS_BOARD_NAME		"Zuma APv2"
+
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * The following defines let you select what serial you want to use
+ * for your console driver.
+ *
+ * what to do:
+ * to use the DUART, undef CONFIG_MPSC.	 If you have hacked a serial
+ * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1
+ * to 0 below.
+ *
+ * to use the MPSC, #define CONFIG_MPSC.  If you have wired up another
+ * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
+ */
+#define CONFIG_MPSC
+
+#define CONFIG_MPSC_PORT	0
+
+
+/* define this if you want to enable GT MAC filtering */
+#define CONFIG_GT_USE_MAC_HASH_TABLE
+
+#if 1
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#undef	CONFIG_BOOTARGS
+
+#define CONFIG_BOOTCOMMAND							\
+	"tftpboot && "								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath " \
+	"ip=$ipaddr:$serverip:$gatewayip:"				\
+	"$netmask:$hostname:eth0:none panic=5 && bootm"
+
+#define CONFIG_LOADS_ECHO	0	/* echo off for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE		/* allow baudrate changes	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+#undef	CONFIG_ALTIVEC			/* undef to disable		*/
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+#define CONFIG_MII		/* enable MII commands */
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_DATE
+
+
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_CMD_MTDPARTS
+#define CONFIG_JFFS2_DEV		"nor0"
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET	0x00000000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_CMD_MTDPARTS
+#define MTDIDS_DEFAULT		"nor1=zuma-1,nor2=zuma-2"
+#define MTDPARTS_DEFAULT	"mtdparts=zuma-1:-(jffs2),zuma-2:-(user)"
+*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x00400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x00C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x00300000	/* default load address */
+
+#define CONFIG_SYS_BUS_CLK		133000000	/* 133 MHz		*/
+
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_LOCK
+
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xfff00000
+#define CONFIG_SYS_RESET_ADDRESS	0xfff00100
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc */
+
+/* areas to map different things with the GT in physical space */
+#define CONFIG_SYS_DRAM_BANKS		4
+#define CONFIG_SYS_DFL_GT_REGS		0x14000000	/* boot time GT_REGS */
+
+/* What to put in the bats. */
+#define CONFIG_SYS_MISC_REGION_BASE	0xf0000000
+
+/* Peripheral Device section */
+#define CONFIG_SYS_GT_REGS		0xf8000000	/* later mapped GT_REGS */
+#define CONFIG_SYS_DEV_BASE		0xf0000000
+#define CONFIG_SYS_DEV0_SIZE		_64M /* zuma flash @ 0xf000.0000*/
+#define CONFIG_SYS_DEV1_SIZE		 _8M /* zuma IDE   @ 0xf400.0000 */
+#define CONFIG_SYS_DEV2_SIZE		 _8M /* unused */
+#define CONFIG_SYS_DEV3_SIZE		 _8M /* unused */
+
+#define CONFIG_SYS_DEV0_PAR		0xc498243c
+	/*     c    4     9     8     2	    4     3     c */
+	/* 33 22|2222|22 22|111 1|11 11|1 1  |	   |      */
+	/* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */
+	/* 11|00|0100|10 01|100|0 00|10 0|100 0|011 1|100 */
+	/*  3| 0|.... ..| 1| 4 |  0 |  4 |   8 |   7 | 4  */
+
+#define CONFIG_SYS_DEV1_PAR		0xc01b6ac5
+	/*     c    0     1     b     6	    a     c     5 */
+	/* 33 22|2222|22 22|111 1|11 11|1 1  |	   |      */
+	/* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */
+	/* 11|00|0000|00 01|101|1 01|10 1|010 1|100 0|101 */
+	/*  3| 0|.... ..| 1| 5 |  5 |  5 |   5 |   8 | 5  */
+
+
+#define CONFIG_SYS_8BIT_BOOT_PAR	0xc00b5e7c
+
+#define CONFIG_SYS_MPP_CONTROL_0	0x00007777 /* GPP[7:4] : REQ0[1:0] GNT0[1:0] */
+#define CONFIG_SYS_MPP_CONTROL_1	0x00000000 /* GPP[15:12] : GPP[11:8] */
+#define CONFIG_SYS_MPP_CONTROL_2	0x00008888 /* GPP[23:20] : REQ1[1:0] GNT1[1:0] */
+#define CONFIG_SYS_MPP_CONTROL_3	0x00000000 /* GPP[31:28] (int[3:0]) */
+					   /* GPP[27:24] (27 is int4, rest are GPP) */
+
+#define CONFIG_SYS_SERIAL_PORT_MUX	0x00001101 /* 11=MPSC1/MPSC0 01=ETH,  0=only MII */
+#define CONFIG_SYS_GPP_LEVEL_CONTROL	0xf8000000 /* interrupt inputs: GPP[31:27] */
+
+#define CONFIG_SYS_SDRAM_CONFIG	0xe4e18200	/* 0x448 */
+				/* idmas use buffer 1,1
+				   comm use buffer 1
+				   pci use buffer 0,0 (pci1->0 pci0->0)
+				   cpu use buffer 1 (R*18)
+				   normal load (see also ifdef HVL)
+				   standard SDRAM (see also ifdef REG)
+				   non staggered refresh */
+				/* 31:26  25 23	 20 19 18 16 */
+				/* 111001 00 111 0  0  00 1 */
+
+				/* refresh count=0x200
+				   phy interleave disable (by default,
+				   set later by dram config..)
+				   virt interleave enable */
+				/* 15 14 13:0 */
+				/* 1  0	 0x200 */
+
+#define CONFIG_SYS_DEV0_SPACE		CONFIG_SYS_DEV_BASE
+#define CONFIG_SYS_DEV1_SPACE		(CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE)
+#define CONFIG_SYS_DEV2_SPACE		(CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE)
+#define CONFIG_SYS_DEV3_SPACE		(CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE)
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ */
+
+#define PCI_HOST_ADAPTER	0	/* configure ar pci adapter	*/
+#define PCI_HOST_FORCE		1	/* configure as pci host	*/
+#define PCI_HOST_AUTO		2	/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_HOST PCI_HOST_FORCE	/* select pci host function	*/
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+
+/* PCI MEMORY MAP section */
+#define CONFIG_SYS_PCI0_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI0_MEM_SIZE	_128M
+#define CONFIG_SYS_PCI1_MEM_BASE	0x88000000
+#define CONFIG_SYS_PCI1_MEM_SIZE	_128M
+
+#define CONFIG_SYS_PCI0_0_MEM_SPACE	(CONFIG_SYS_PCI0_MEM_BASE)
+#define CONFIG_SYS_PCI1_0_MEM_SPACE	(CONFIG_SYS_PCI1_MEM_BASE)
+
+/* PCI I/O MAP section */
+#define CONFIG_SYS_PCI0_IO_BASE	0xfa000000
+#define CONFIG_SYS_PCI0_IO_SIZE	_16M
+#define CONFIG_SYS_PCI1_IO_BASE	0xfb000000
+#define CONFIG_SYS_PCI1_IO_SIZE	_16M
+
+#define CONFIG_SYS_PCI0_IO_SPACE	(CONFIG_SYS_PCI0_IO_BASE)
+#define CONFIG_SYS_PCI0_IO_SPACE_PCI	0x00000000
+#define CONFIG_SYS_PCI1_IO_SPACE	(CONFIG_SYS_PCI1_IO_BASE)
+#define CONFIG_SYS_PCI1_IO_SPACE_PCI	0x00000000
+
+
+/*----------------------------------------------------------------------
+ * Initial BAT mappings
+ */
+
+/* NOTES:
+ * 1) GUARDED and WRITE_THRU not allowed in IBATS
+ * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
+ */
+
+/* SDRAM */
+#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
+
+/* init ram */
+#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
+
+/* PCI0, PCI1 memory space (starting at PCI0 base, mapped in one BAT) */
+#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
+#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
+#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* GT regs, bootrom, all the devices, PCI I/O */
+#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
+#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
+#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8<<20) /* Initial Memory map for Linux */
+
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	3	/* max number of memory banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	130	/* max number of sectors on one chip */
+
+#define CONFIG_SYS_EXTRA_FLASH_DEVICE	DEVICE0 /* extra flash at device 0 */
+#define CONFIG_SYS_EXTRA_FLASH_WIDTH	2	/* 16 bit */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
+#define CONFIG_SYS_FLASH_CFI		1
+
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_SIZE		0x1000	/* Total Size of Environment Sector */
+#define CONFIG_ENV_SECT_SIZE	0x10000 /* see README - env sect real size */
+#define CONFIG_ENV_ADDR		(0xfff80000 - CONFIG_ENV_SECT_SIZE)
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For all MPC74xx CPUs		 */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * L2CR setup -- make sure this is right for your board!
+ * look in include/74xx_7xx.h for the defines used here
+ */
+
+#define CONFIG_SYS_L2
+
+#ifdef CONFIG_750CX
+#define L2_INIT		0
+#else
+#define L2_INIT		(L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
+			L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
+#endif
+
+#define L2_ENABLE	(L2_INIT | L2CR_L2E)
+
+/*------------------------------------------------------------------------
+ * Real time clock
+ */
+#define CONFIG_RTC_DS1302
+
+
+/*------------------------------------------------------------------------
+ * Galileo I2C driver
+ */
+#define CONFIG_GT_I2C
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/a320evb.h b/qemu/roms/u-boot/include/configs/a320evb.h
new file mode 100644
index 000000000..0d3cf369b
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/a320evb.h
@@ -0,0 +1,211 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * Configuation settings for the Faraday A320 board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/a320.h>
+
+/*
+ * mach-type definition
+ */
+#define MACH_TYPE_FARADAY	758
+#define CONFIG_MACH_TYPE	MACH_TYPE_FARADAY
+
+/*
+ * Linux kernel tagged list
+ */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+
+/*
+ * CPU and Board Configuration Options
+ */
+#undef CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * Power Management Unit
+ */
+#define CONFIG_FTPMU010_POWER
+
+/*
+ * Timer
+ */
+
+/*
+ * Real Time Clock
+ */
+#define CONFIG_RTC_FTRTC010
+
+/*
+ * Serial console configuration
+ */
+
+/* FTUART is a high speed NS 16C550A compatible UART */
+#define CONFIG_BAUDRATE			38400
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_COM1		0x98200000
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#define CONFIG_SYS_NS16550_CLK		18432000
+
+/*
+ * Ethernet
+ */
+#define CONFIG_FTMAC100
+
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_PING
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_PROMPT	"A320 # "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE	\
+	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS	16
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)
+
+/*
+ * SDRAM controller configuration
+ */
+#define CONFIG_SYS_FTSDMC020_TP0	(FTSDMC020_TP0_TRAS(2) |	\
+					 FTSDMC020_TP0_TRP(1)  |	\
+					 FTSDMC020_TP0_TRCD(1) |	\
+					 FTSDMC020_TP0_TRF(3)  |	\
+					 FTSDMC020_TP0_TWR(1)  |	\
+					 FTSDMC020_TP0_TCL(2))
+
+#define CONFIG_SYS_FTSDMC020_TP1	(FTSDMC020_TP1_INI_PREC(4) |	\
+					 FTSDMC020_TP1_INI_REFT(8) |	\
+					 FTSDMC020_TP1_REF_INTV(0x180))
+
+#define CONFIG_SYS_FTSDMC020_BANK0_BSR	(FTSDMC020_BANK_ENABLE   |	\
+					 FTSDMC020_BANK_DDW_X16  |	\
+					 FTSDMC020_BANK_DSZ_256M |	\
+					 FTSDMC020_BANK_MBW_32   |	\
+					 FTSDMC020_BANK_SIZE_64M)
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1		0x10000000	/* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x04000000	/* 64 MB */
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 - \
+					GENERATED_GBL_DATA_SIZE)
+
+/*
+ * Load address and memory test area should agree with
+ * board/faraday/a320/config.mk. Be careful not to overwrite U-boot itself.
+ */
+#define CONFIG_SYS_LOAD_ADDR		(PHYS_SDRAM_1 + 0x2000000)
+
+/* memtest works on 63 MB in DRAM */
+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
+#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_1 + 0x3F00000)
+
+#define CONFIG_SYS_TEXT_BASE		0
+
+/*
+ * Static memory controller configuration
+ */
+
+#define CONFIG_FTSMC020
+#include <faraday/ftsmc020.h>
+
+#define FTSMC020_BANK0_CONFIG	(FTSMC020_BANK_ENABLE             |	\
+				 FTSMC020_BANK_BASE(PHYS_FLASH_1) |	\
+				 FTSMC020_BANK_SIZE_1M            |	\
+				 FTSMC020_BANK_MBW_8)
+
+#define FTSMC020_BANK0_TIMING	(FTSMC020_TPR_RBE      |	\
+				 FTSMC020_TPR_AST(3)   |	\
+				 FTSMC020_TPR_CTW(3)   |	\
+				 FTSMC020_TPR_ATI(0xf) |	\
+				 FTSMC020_TPR_AT2(3)   |	\
+				 FTSMC020_TPR_WTC(3)   |	\
+				 FTSMC020_TPR_AHT(3)   |	\
+				 FTSMC020_TPR_TRNA(0xf))
+
+#define FTSMC020_BANK1_CONFIG	(FTSMC020_BANK_ENABLE             |	\
+				 FTSMC020_BANK_BASE(PHYS_FLASH_2) |	\
+				 FTSMC020_BANK_SIZE_32M           |	\
+				 FTSMC020_BANK_MBW_32)
+
+#define FTSMC020_BANK1_TIMING	(FTSMC020_TPR_AST(3)   |	\
+				 FTSMC020_TPR_CTW(3)   |	\
+				 FTSMC020_TPR_ATI(0xf) |	\
+				 FTSMC020_TPR_AT2(3)   |	\
+				 FTSMC020_TPR_WTC(3)   |	\
+				 FTSMC020_TPR_AHT(3)   |	\
+				 FTSMC020_TPR_TRNA(0xf))
+
+#define CONFIG_SYS_FTSMC020_CONFIGS	{			\
+	{ FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, },	\
+	{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },	\
+}
+
+/*
+ * FLASH and environment organization
+ */
+
+/* use CFI framework */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+
+/* support JEDEC */
+#define CONFIG_FLASH_CFI_LEGACY
+#define CONFIG_SYS_FLASH_LEGACY_512Kx8
+
+#define PHYS_FLASH_1			0x00000000
+#define PHYS_FLASH_2			0x00400000
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ PHYS_FLASH_1, PHYS_FLASH_2, }
+
+#define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1
+
+/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2
+
+/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_SECT	512
+
+#undef CONFIG_SYS_FLASH_EMPTY_INFO
+
+/* environments */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR			(PHYS_FLASH_1 + 0x60000)
+#define CONFIG_ENV_SIZE			0x20000
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/a3m071.h b/qemu/roms/u-boot/include/configs/a3m071.h
new file mode 100644
index 000000000..205adfd8c
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/a3m071.h
@@ -0,0 +1,443 @@
+/*
+ * Copyright 2012-2013 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5200
+#define CONFIG_A3M071			/* A3M071 board */
+
+#define	CONFIG_SYS_TEXT_BASE	0x01000000	/* boot low for 32 MiB boards */
+
+#define CONFIG_SPL_TARGET	"u-boot-img.bin"
+
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33MHz */
+
+#define CONFIG_MISC_INIT_R
+#define CONFIG_SYS_LOWBOOT		/* Enable lowboot	*/
+
+#ifdef CONFIG_A4M2K
+#define CONFIG_HOSTNAME		a4m2k
+#else
+#define CONFIG_HOSTNAME		a3m071
+#endif
+
+#define CONFIG_BOOTCOUNT_LIMIT
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	    /* console is on PSC1 */
+#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
+#define CONFIG_SYS_BAUDRATE_TABLE		\
+	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_DHCP
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_SERVERIP
+#define CONFIG_BOOTP_MAY_FAIL
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_SERVERIP
+#define CONFIG_NET_RETRY_COUNT 3
+#define CONFIG_CMD_LINK_LOCAL
+#define CONFIG_LIB_RAND
+#define CONFIG_NETCONSOLE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_CMD_PING
+#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
+#define CONFIG_MTD_PARTITIONS	/* needed for UBI */
+#define CONFIG_FLASH_CFI_MTD
+#define MTDIDS_DEFAULT          "nor0=fc000000.flash"
+#define MTDPARTS_DEFAULT	"mtdparts=fc000000.flash:512k(u-boot),"	\
+						"128k(env1),"	\
+						"128k(env2),"	\
+						"128k(hwinfo),"	\
+						"1M(nvramsim),"	\
+						"128k(dtb),"	\
+						"5M(kernel),"	\
+						"128k(sysinfo),"	\
+						"7552k(root),"	\
+						"4M(app),"	\
+						"5376k(data),"	\
+						"8M(install)"
+
+#define CONFIG_LZO			/* needed for UBI */
+#define CONFIG_RBTREE			/* needed for UBI */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_FIT
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
+/* define for 66MHz speed - undef for 33MHz PCI clock speed */
+#ifdef CONFIG_A4M2K
+#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
+#else
+#undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
+#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE	8192
+
+#define OF_CPU			"PowerPC,5200@0"
+#define OF_SOC			"soc5200@f0000000"
+#define OF_TBCLK		(bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH		"/soc5200@f0000000/serial@2000"
+
+/*
+ * NOR flash configuration
+ */
+#define CONFIG_SYS_FLASH_BASE		0xfc000000
+#define CONFIG_SYS_FLASH_SIZE		0x02000000
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x80000)
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	256
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500
+#define CONFIG_SYS_FLASH_LOCK_TOUT	5
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	10000
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_FLASH_VERIFY
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SIZE		0x10000
+#define CONFIG_ENV_SECT_SIZE	0x20000
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
+
+/*
+ * Memory map
+ */
+#define CONFIG_SYS_MBAR			0xf0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR		0x80000000
+
+/* Use SRAM until RAM will be available */
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_END		MPC5XXX_SRAM_SIZE
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - \
+					 GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_MONITOR_LEN		(512 << 10)
+#define CONFIG_SYS_MALLOC_LEN		(4 << 20)
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC
+#define CONFIG_MPC5xxx_FEC_MII100
+#ifdef CONFIG_A4M2K
+#define CONFIG_PHY_ADDR			0x01
+#else
+#define CONFIG_PHY_ADDR			0x00
+#endif
+
+/*
+ * GPIO configuration
+ */
+
+/*
+ * GPIO-config depends on failsave-level
+ * failsave 0 means just MPX-config, no digiboard, no fpga
+ *          1 means digiboard ok
+ *          2 means fpga ok
+ */
+
+#ifdef CONFIG_A4M2K
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x1005C805
+#else
+/* for failsave-level 0 - full failsave */
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x1005C005
+/* for failsave-level 1 - only digiboard ok */
+#define CONFIG_SYS_GPS_PORT_CONFIG_1	0x1005C065
+/* for failsave-level 2 - all ok */
+#define CONFIG_SYS_GPS_PORT_CONFIG_2	0x1005C065
+#endif
+
+#define CONFIG_WDOG_GPIO_PIN		GPIO_WKUP_7
+#if defined(CONFIG_A4M2K) && !defined(CONFIG_SPL_BUILD)
+#define CONFIG_HW_WATCHDOG		/* Use external HW-Watchdog	*/
+#endif
+
+/*
+ * Configuration matrix
+ *                        MSB                            LSB
+ * failsave 0  0x1005C005  00010000000001011100000000000101  ( full failsave )
+ * failsave 1  0x1005C065  00010000000001011100000001100101  ( digib.-ver ok )
+ * failsave 2  0x1005C065  00010000000001011100000001100101  ( all ok )
+ *                         || ||| ||  |   ||| |   |   |   |
+ *                         || ||| ||  |   ||| |   |   |   |  bit rev name
+ *                         ++-+++-++--+---+++-+---+---+---+-  0   31 CS1
+ *                          +-+++-++--+---+++-+---+---+---+-  1   30 LPTZ
+ *                            ||| ||  |   ||| |   |   |   |   2   29 ALTs
+ *                            +++-++--+---+++-+---+---+---+-  3   28 ALTs
+ *                             ++-++--+---+++-+---+---+---+-  4   27 CS7
+ *                              +-++--+---+++-+---+---+---+-  5   26 CS6
+ *                                ||  |   ||| |   |   |   |   6   25 ATA
+ *                                ++--+---+++-+---+---+---+-  7   24 ATA
+ *                                 +--+---+++-+---+---+---+-  8   23 IR_USB_CLK
+ *                                    |   ||| |   |   |   |   9   22 IRDA
+ *                                    |   ||| |   |   |   |  10   21 IRDA
+ *                                    +---+++-+---+---+---+- 11   20 IRDA
+ *                                        ||| |   |   |   |  12   19 Ether
+ *                                        ||| |   |   |   |  13   18 Ether
+ *                                        ||| |   |   |   |  14   17 Ether
+ *                                        +++-+---+---+---+- 15   16 Ether
+ *                                         ++-+---+---+---+- 16   15 PCI_DIS
+ *                                          +-+---+---+---+- 17   14 USB_SE
+ *                                            |   |   |   |  18   13 USB
+ *                                            +---+---+---+- 19   12 USB
+ *                                                |   |   |  20   11 PSC3
+ *                                                |   |   |  21   10 PSC3
+ *                                                |   |   |  22    9 PSC3
+ *                                                +---+---+- 23    8 PSC3
+ *                                                    |   |  24    7 -
+ *                                                    |   |  25    6 PSC2
+ *                                                    |   |  26    5 PSC2
+ *                                                    +---+- 27    4 PSC2
+ *                                                        |  28    3 -
+ *                                                        |  29    2 PSC1
+ *                                                        |  30    1 PSC1
+ *                                                        +- 31    0 PSC1
+ */
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP
+
+#define CONFIG_CMDLINE_EDITING
+#define	CONFIG_SYS_HUSH_PARSER
+#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024
+#else
+#define CONFIG_SYS_CBSIZE		256
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000
+#define CONFIG_SYS_MEMTEST_END		0x00f00000
+
+#define CONFIG_SYS_LOAD_ADDR		0x00100000
+
+#define CONFIG_LOOPW
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	/* don't print console @ startup*/
+
+/*
+ * Various low-level settings
+ */
+#define CONFIG_SYS_HID0_INIT		(HID0_ICE | HID0_ICFI)
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
+
+#define CONFIG_SYS_BOOTCS_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
+
+#ifdef CONFIG_A4M2K
+/* external MRAM */
+#define CONFIG_SYS_CS1_START		0xf1000000
+#define CONFIG_SYS_CS1_SIZE		(512 << 10)	/* 512KiB MRAM */
+#endif
+
+#define CONFIG_SYS_CS2_START		0xe0000000
+#define CONFIG_SYS_CS2_SIZE		0x00100000
+
+/* FPGA slave io (512kiB / 1MiB) - see ticket #66 */
+#define CONFIG_SYS_CS3_START		0xE9000000
+#ifdef CONFIG_A4M2K
+#define CONFIG_SYS_CS3_SIZE		0x00100000
+#else
+#define CONFIG_SYS_CS3_SIZE		0x00080000
+#endif
+/* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0  = 0x0032B900 */
+#define CONFIG_SYS_CS3_CFG		0x0032B900
+
+#ifndef CONFIG_A4M2K
+/* Diagnosis Interface - see ticket #63 */
+#define CONFIG_SYS_CS4_START		0xEA000000
+#define CONFIG_SYS_CS4_SIZE		0x00000001
+/* 00000000 00000010 1 0 1 1 10 01 00 00 0 0 0 0  = 0x0002B900 */
+#define CONFIG_SYS_CS4_CFG		0x0002B900
+#endif
+
+/* FPGA master io (64kiB / 1MiB) - see ticket #66 */
+#define CONFIG_SYS_CS5_START		0xE8000000
+#ifdef CONFIG_A4M2K
+#define CONFIG_SYS_CS5_SIZE		0x00100000
+#else
+#define CONFIG_SYS_CS5_SIZE		0x00010000
+#endif
+/* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0  = 0x0032B900 */
+#define CONFIG_SYS_CS5_CFG		0x0032B900
+
+#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2	/* for pci_clk  = 66 MHz */
+#define CONFIG_SYS_BOOTCS_CFG		0x0006F900
+#define CONFIG_SYS_CS1_CFG		0x0008FD00
+#define CONFIG_SYS_CS2_CFG		0x0006F90C
+#else	/* for pci_clk = 33 MHz */
+#define CONFIG_SYS_BOOTCS_CFG		0x0002F900
+#define CONFIG_SYS_CS1_CFG		0x0001FB00
+#define CONFIG_SYS_CS2_CFG		0x0002F90C
+#endif
+
+#define CONFIG_SYS_CS_BURST		0x00000000
+/* set DC for FPGA CS5 and CS3 to 0 - see ticket #66 */
+/* R  7  R  6  R  5  R  4  R  3  R  2  R  1  R  0  */
+/* 00 11 00 11 00 00 00 11 00 00 00 00 00 00 00 00 */
+#define CONFIG_SYS_CS_DEADCYCLE		0x33030000
+
+#define CONFIG_SYS_RESET_ADDRESS	0xff000000
+
+/*
+ * Environment Configuration
+ */
+
+#define CONFIG_BOOTDELAY	3	/* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#define CONFIG_SYS_AUTOLOAD	"n"
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_mtd\" to boot from flash with mtd filesystem;" \
+	"echo Type \"run net_nfs\" to boot from tftp with nfs filesystem;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define CONFIG_SYS_OS_BASE	0xfc200000
+#define CONFIG_SYS_FDT_BASE	0xfc1e0000
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"verify=no\0"							\
+	"loadaddr=200000\0"						\
+	"kernel_addr=" __stringify(CONFIG_SYS_OS_BASE) "\0"		\
+	"kernel_addr_r=1000000\0"					\
+	"fdt_addr=" __stringify(CONFIG_SYS_FDT_BASE) "\0"		\
+	"fdt_addr_r=1800000\0"						\
+	"bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0"		\
+	"fdtfile=" __stringify(CONFIG_HOSTNAME) "/"			\
+		__stringify(CONFIG_HOSTNAME) ".dtb\0"			\
+	"rootpath=/opt/eldk-5.2.1/powerpc/"				\
+		"core-image-minimal-mtdutils-dropbear-generic\0"	\
+	"consoledev=ttyPSC0\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"mtdargs=setenv bootargs root=/dev/mtdblock8 "			\
+		"rootfstype=squashfs,jffs2\0"				\
+	"addhost=setenv bootargs ${bootargs} "				\
+		"hostname=${hostname}\0"				\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} "				\
+		"console=${consoledev},${baudrate}\0"			\
+	"flash_nfs=run nfsargs addip addtty addmtd addhost;"		\
+		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
+	"flash_mtd=run mtdargs addip addtty addmtd addhost;"		\
+		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
+	"flash_self=run ramargs addip addtty addmtd addhost;"		\
+		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
+		"tftp ${fdt_addr_r} ${fdtfile};"			\
+		"run nfsargs addip addtty addmtd addhost;"		\
+		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
+	"load=tftp ${loadaddr} " __stringify(CONFIG_HOSTNAME)		\
+		"/u-boot-img.bin\0"					\
+	"update=protect off fc000000 fc07ffff;"				\
+		"era fc000000 fc07ffff;"				\
+		"cp.b ${loadaddr} fc000000 ${filesize}\0"		\
+	"upd=run load;run update\0"					\
+	"upd_fdt=tftp 1800000 a3m071/a3m071.dtb;"			\
+		"run mtdargs addip addtty addmtd addhost;"		\
+		"fdt addr 1800000;fdt boardsetup;fdt chosen;"		\
+		"erase fc1e0000 fc1fffff;cp.b 1800000 fc1e0000 20000"	\
+	"upd_kernel=tftp 1000000 a3m071/uImage-uncompressed;"		\
+		"erase fc200000 fc6fffff;"				\
+		"cp.b 1000000 fc200000 ${filesize}"			\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
+	"mtdids=" MTDIDS_DEFAULT "\0"					\
+	"mtdparts=" MTDPARTS_DEFAULT "\0"				\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run flash_mtd"
+
+/*
+ * SPL related defines
+ */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_NOR_SUPPORT
+#define CONFIG_SPL_TEXT_BASE	0xfc000000
+#define	CONFIG_SPL_START_S_PATH	"arch/powerpc/cpu/mpc5xxx"
+#define CONFIG_SPL_LDSCRIPT	"arch/powerpc/cpu/mpc5xxx/u-boot-spl.lds"
+#define CONFIG_SPL_LIBCOMMON_SUPPORT	/* image.c */
+#define CONFIG_SPL_LIBGENERIC_SUPPORT	/* string.c */
+#define CONFIG_SPL_SERIAL_SUPPORT
+
+/* Place BSS for SPL near end of SDRAM */
+#define CONFIG_SPL_BSS_START_ADDR	((128 - 1) << 20)
+#define CONFIG_SPL_BSS_MAX_SIZE		(64 << 10)
+
+#define CONFIG_SPL_OS_BOOT
+#define CONFIG_SPL_ENV_SUPPORT
+/* Place patched DT blob (fdt) at this address */
+#define CONFIG_SYS_SPL_ARGS_ADDR	0x01800000
+
+/* Settings for real U-Boot to be loaded from NOR flash */
+#ifndef __ASSEMBLY__
+extern char __spl_flash_end[];
+#endif
+#define CONFIG_SYS_UBOOT_BASE		__spl_flash_end
+#define CONFIG_SYS_SPL_MAX_LEN		(32 << 10)
+#define CONFIG_SYS_UBOOT_START		0x1000100
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/a4m072.h b/qemu/roms/u-boot/include/configs/a4m072.h
new file mode 100644
index 000000000..cc88ac161
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/a4m072.h
@@ -0,0 +1,378 @@
+/*
+ * (C) Copyright 2003-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2010
+ * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5200		1	/* This is a MPC5200 CPU */
+#define CONFIG_A4M072		1	/* ... on A4M072 board */
+#define CONFIG_MPC5200_DDR	1	/* ... use DDR RAM */
+
+#define CONFIG_SYS_TEXT_BASE	0xFE000000
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
+
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
+#define CONFIG_BAUDRATE		9600	/* ... at 9600 bps */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+/* define to enable silent console */
+#define CONFIG_SILENT_CONSOLE
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device */
+
+/*
+ * PCI Mapping:
+ * 0x40000000 - 0x4fffffff - PCI Memory
+ * 0x50000000 - 0x50ffffff - PCI IO Space
+ */
+#define CONFIG_PCI
+
+#if defined(CONFIG_PCI)
+#define CONFIG_PCI_PNP		1
+#define CONFIG_PCI_SCAN_SHOW	1
+#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1
+
+#define CONFIG_PCI_MEM_BUS	0x40000000
+#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE	0x10000000
+
+#define CONFIG_PCI_IO_BUS	0x50000000
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0x01000000
+#endif
+
+#define CONFIG_SYS_XLB_PIPELINING	1
+
+#undef CONFIG_EEPRO100
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+/* USB */
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_USB_STORAGE
+#define CONFIG_SYS_OHCI_BE_CONTROLLER
+#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
+#define CONFIG_SYS_USB_OHCI_CPU_INIT	1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE	MPC5XXX_USB
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"mpc5200"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
+
+#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DISPLAY
+
+#if defined(CONFIG_PCI)
+#define CONFIG_CMD_PCI
+#endif
+
+#if (CONFIG_SYS_TEXT_BASE == 0xFE000000)		/* Boot low with 32 MB Flash */
+#define CONFIG_SYS_LOWBOOT		1
+#define CONFIG_SYS_LOWBOOT32		1
+#endif
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	2	/* autoboot after 2 seconds */
+
+#define CONFIG_SYS_AUTOLOAD	"n"
+
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT		"autoboot in %d seconds\n", bootdelay
+#define CONFIG_AUTOBOOT_DELAY_STR	"asdfg"
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_PREBOOT				"run try_update"
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"bk=run add_mtd ; run add_consolespec ; bootm 200000\0"		\
+	"cf1=diskboot 200000 0:1\0"					\
+	"bootcmd_cf1=run bcf1\0"					\
+	"bcf=setenv bootargs root=/dev/hda3\0"				\
+	"bootcmd_nfs=run bnfs\0"					\
+	"norargs=setenv bootargs root=/dev/mtdblock3 rootfstype=cramfs "\
+		"panic=1\0"						\
+	"bootcmd_nor=cp.b ${kernel_addr} 200000 100000;"		\
+			"run norargs addip; run bk\0"			\
+	"bnfs=nfs 200000 ${rootpath}/boot/uImage;"			\
+			"run nfsargs addip ; run bk\0"			\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+				"nfsroot=${serverip}:${rootpath}\0"	\
+	"try_update=usb start;sleep 2;usb start;sleep 1;"		\
+			"fatload usb 0 2F0000 PCPUUPDT 2FF;usb stop;"	\
+			"source 2F0000\0"				\
+	"env_addr=FE060000\0"						\
+	"kernel_addr=FE100000\0"					\
+	"rootfs_addr=FE200000\0"					\
+	"add_mtd=setenv bootargs ${bootargs} mtdparts="			\
+		"phys_mapped_flash:384k(u),640k(e),1m(k),30m(r)\0"	\
+	"bcf1=run cf1; run bcf; run addip; run bk\0"			\
+	"add_consolespec=setenv bootargs ${bootargs} "			\
+				"console=/dev/null quiet\0"		\
+	"addip=if test -n ${ethaddr};"					\
+		"then if test -n ${ipaddr};"				\
+			"then setenv bootargs ${bootargs} "		\
+				"ip=${ipaddr}:${serverip}:${gatewayip}:"\
+				"${netmask}:${hostname}:${netdev}:off;"	\
+			"fi;"						\
+		"else;"							\
+			"setenv bootargs ${bootargs} no_ethaddr;"	\
+		"fi\0"							\
+	"hostname=CPUP0\0"						\
+	"ethaddr=00:00:00:00:00:00\0"					\
+	"netdev=eth0\0"							\
+	"bootcmd=run bootcmd_nor\0" 					\
+	""
+/*
+ * IPB Bus clocking configuration.
+ */
+#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C			1	/* I2C with hardware support */
+#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #1 or #2 */
+
+#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x52	/* 1010010x */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
+#define CONFIG_SYS_EEPROM_WREN			1
+#define CONFIG_SYS_EEPROM_WP			GPIO_PSC2_4
+
+/*
+ * Flash configuration
+ */
+#define CONFIG_SYS_FLASH_BASE		0xFE000000
+#define CONFIG_SYS_FLASH_SIZE		0x02000000
+#if !defined(CONFIG_SYS_LOWBOOT)
+#error "CONFIG_SYS_LOWBOOT not defined?"
+#else	/* CONFIG_SYS_LOWBOOT */
+#if defined(CONFIG_SYS_LOWBOOT32)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00060000)
+#endif
+#endif	/* CONFIG_SYS_LOWBOOT */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max num of sects on one chip */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_CS0_START}
+#define CONFIG_SYS_FLASH_BANKS_SIZES	{CONFIG_SYS_CS0_SIZE}
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_SIZE		0x10000
+#define CONFIG_ENV_SECT_SIZE	0x20000
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+
+#define CONFIG_ENV_OVERWRITE	1
+
+/*
+ * Memory map
+ */
+#define CONFIG_SYS_MBAR		0xF0000000
+#define CONFIG_SYS_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
+
+/* Use SRAM until RAM will be available */
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_SIZE		MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */
+
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN		(384 << 10)	/* Reserve 384 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC	1
+#define CONFIG_MPC5xxx_FEC_MII100
+/*
+ * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
+ */
+/* #define CONFIG_MPC5xxx_FEC_MII10 */
+#define CONFIG_PHY_ADDR		0x1f
+#define CONFIG_PHY_TYPE		0x79c874		/* AMD Phy Controller */
+
+/*
+ * GPIO configuration
+ */
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x18000004
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_CMDLINE_EDITING	1
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
+
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+
+/*
+ * Various low-level settings
+ */
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
+/* Flash at CSBoot, CS0 */
+#define CONFIG_SYS_BOOTCS_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_CFG		0x0002DD00
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
+/* External SRAM at CS1 */
+#define CONFIG_SYS_CS1_START		0x62000000
+#define CONFIG_SYS_CS1_SIZE		0x00400000
+#define CONFIG_SYS_CS1_CFG		0x00009930
+#define CONFIG_SYS_SRAM_BASE		CONFIG_SYS_CS1_START
+#define CONFIG_SYS_SRAM_SIZE		CONFIG_SYS_CS1_SIZE
+/* LED display at CS7 */
+#define CONFIG_SYS_CS7_START		0x6a000000
+#define CONFIG_SYS_CS7_SIZE		(64*1024)
+#define CONFIG_SYS_CS7_CFG		0x0000bf30
+
+#define CONFIG_SYS_CS_BURST		0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE		0x33333003
+
+#define CONFIG_SYS_RESET_ADDRESS	0xff000000
+
+/*-----------------------------------------------------------------------
+ * USB stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_USB_CLOCK	0x0001BBBB
+#define CONFIG_USB_CONFIG	0x00001000 /* 0x4000 for SE mode */
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+
+#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+
+#define CONFIG_IDE_PREINIT
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 2 drives per IDE bus	*/
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
+
+/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
+
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)
+
+/* Interval between registers                                                */
+#define CONFIG_SYS_ATA_STRIDE          4
+
+#define CONFIG_ATAPI                   1
+
+/*-----------------------------------------------------------------------
+ * Open firmware flat tree support
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+#define OF_CPU			"PowerPC,5200@0"
+#define OF_SOC			"soc5200@f0000000"
+#define OF_TBCLK		(bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH		"/soc5200@f0000000/serial@2000"
+
+/* Support for the 7-segment display */
+#define CONFIG_SYS_DISP_CHR_RAM	     CONFIG_SYS_CS7_START
+#define CONFIG_SHOW_ACTIVITY		/* used for display realization */
+
+#define CONFIG_SHOW_BOOT_PROGRESS
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/ac14xx.h b/qemu/roms/u-boot/include/configs/ac14xx.h
new file mode 100644
index 000000000..f57820d8f
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/ac14xx.h
@@ -0,0 +1,573 @@
+/*
+ * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
+ * (C) Copyright 2010 DAVE Srl <www.dave.eu>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * ifm AC14xx (MPC5121e based) board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_AC14XX 1
+/*
+ * Memory map for the ifm AC14xx board:
+ *
+ * 0x0000_0000-0x0FFF_FFFF	DDR RAM (256 MB)
+ * 0x3000_0000-0x3001_FFFF	On Chip SRAM (128 KB)
+ * 0x8000_0000-0x803F_FFFF	IMMR (4 MB)
+ * 0xE000_0000-0xEFFF_FFFF	several LPB attached hardware (CSx)
+ * 0xFC00_0000-0xFFFF_FFFF	NOR Boot FLASH (64 MB)
+ */
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1	/* E300 Family */
+
+#define CONFIG_SYS_TEXT_BASE	0xFFF00000
+
+#if defined(CONFIG_VIDEO)
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#endif
+
+#define CONFIG_SYS_MPC512X_CLKIN	25000000	/* in Hz */
+#define SCFR1_IPS_DIV			2
+#define SCFR1_LPC_DIV			2
+#define SCFR1_NFC_DIV			2
+#define SCFR1_DIU_DIV			240
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_SYS_IMMR			0x80000000
+#define CONFIG_SYS_DIU_ADDR		(CONFIG_SYS_IMMR + 0x2100)
+
+/* more aggressive 'mtest' over a wider address range */
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_SYS_MEMTEST_START	0x00100000      /* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x0FE00000
+
+/*
+ * DDR Setup - manually set all parameters as there's no SPD etc.
+ */
+#define CONFIG_SYS_DDR_SIZE		256		/* MB */
+#define CONFIG_SYS_DDR_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_MAX_RAM_SIZE		0x20000000
+
+/*
+ * DDR Controller Configuration
+ *
+ * SYS_CFG:
+ *	[31:31]	MDDRC Soft Reset:	Diabled
+ *	[30:30]	DRAM CKE pin:		Enabled
+ *	[29:29]	DRAM CLK:		Enabled
+ *	[28:28]	Command Mode:		Enabled (For initialization only)
+ *	[27:25]	DRAM Row Select:	dram_row[15:0] = magenta_address[25:10]
+ *	[24:21]	DRAM Bank Select:	dram_bank[1:0] = magenta_address[11:10]
+ *	[20:19]	Read Test:		DON'T USE
+ *	[18:18]	Self Refresh:		Enabled
+ *	[17:17]	16bit Mode:		Disabled
+ *	[16:13] Ready Delay:		2
+ *	[12:12]	Half DQS Delay:		Disabled
+ *	[11:11]	Quarter DQS Delay:	Disabled
+ *	[10:08]	Write Delay:		2
+ *	[07:07]	Early ODT:		Disabled
+ *	[06:06]	On DIE Termination:	Disabled
+ *	[05:05]	FIFO Overflow Clear:	DON'T USE here
+ *	[04:04]	FIFO Underflow Clear:	DON'T USE here
+ *	[03:03]	FIFO Overflow Pending:	DON'T USE here
+ *	[02:02]	FIFO Underlfow Pending:	DON'T USE here
+ *	[01:01]	FIFO Overlfow Enabled:	Enabled
+ *	[00:00]	FIFO Underflow Enabled:	Enabled
+ * TIME_CFG0
+ *	[31:16]	DRAM Refresh Time:	0 CSB clocks
+ *	[15:8]	DRAM Command Time:	0 CSB clocks
+ *	[07:00]	DRAM Precharge Time:	0 CSB clocks
+ * TIME_CFG1
+ *	[31:26]	DRAM tRFC:
+ *	[25:21]	DRAM tWR1:
+ *	[20:17]	DRAM tWRT1:
+ *	[16:11]	DRAM tDRR:
+ *	[10:05]	DRAM tRC:
+ *	[04:00]	DRAM tRAS:
+ * TIME_CFG2
+ *	[31:28]	DRAM tRCD:
+ *	[27:23]	DRAM tFAW:
+ *	[22:19]	DRAM tRTW1:
+ *	[18:15]	DRAM tCCD:
+ *	[14:10] DRAM tRTP:
+ *	[09:05]	DRAM tRP:
+ *	[04:00] DRAM tRPA
+ */
+
+/*
+ * NOTE: although this board uses DDR1 only, the common source brings defaults
+ * for DDR2 init sequences, that's why we have to keep those here as well
+ */
+
+/* DDR1 -- 32bit, drive strength (pad configuration) 3 for control and data */
+#define CONFIG_SYS_IOCTRL_MUX_DDR	((0 << 6) | (3 << 3) | (3 << 0))
+
+#define CONFIG_SYS_MDDRC_SYS_CFG (/* 0xEAA09100 */ 0 \
+			| (1 << 31)	/* RST_B */ \
+			| (1 << 30)	/* CKE */ \
+			| (1 << 29)	/* CLK_ON */ \
+			| (0 << 28)	/* CMD_MODE */ \
+			| (5 << 25)	/* DRAM_ROW_SELECT */ \
+			| (5 << 21)	/* DRAM_BANK_SELECT */ \
+			| (0 << 18)	/* SELF_REF_EN */ \
+			| (0 << 17)	/* 16BIT_MODE */ \
+			| (4 << 13)	/* RDLY */ \
+			| (1 << 12)	/* HALF_DQS_DLY */ \
+			| (0 << 11)	/* QUART_DQS_DLY */ \
+			| (1 <<  8)	/* WDLY */ \
+			| (0 <<  7)	/* EARLY_ODT */ \
+			| (0 <<  6)	/* ON_DIE_TERMINATE */ \
+			| (0 <<  5)	/* FIFO_OV_CLEAR */ \
+			| (0 <<  4)	/* FIFO_UV_CLEAR */ \
+			| (0 <<  1)	/* FIFO_OV_EN */ \
+			| (0 <<  0)	/* FIFO_UV_EN */ \
+			)
+
+#define CONFIG_SYS_MDDRC_TIME_CFG0	0x04E03124
+#define CONFIG_SYS_MDDRC_TIME_CFG1	0x30CA1147
+#define CONFIG_SYS_MDDRC_TIME_CFG2	0x32B10864
+
+/* register address only, i.e. template without values */
+#define CONFIG_SYS_MICRON_BMODE		0x01000000
+#define CONFIG_SYS_MICRON_EMODE		0x01010000
+#define CONFIG_SYS_MICRON_EMODE2	0x01020000
+#define CONFIG_SYS_MICRON_EMODE3	0x01030000
+/*
+ * values for mode registers (without mode register address)
+ */
+/* CAS 2.5 (6), burst seq (0) and length 4 (2) */
+#define CONFIG_SYS_MICRON_BMODE_PARAM	0x00000062
+#define CONFIG_SYS_MICRON_BMODE_RSTDLL	0x00000100
+/* DLL enable, reduced drive strength */
+#define CONFIG_SYS_MICRON_EMODE_PARAM	0x00000002
+
+#define CONFIG_SYS_DDRCMD_NOP		0x01380000
+#define CONFIG_SYS_DDRCMD_PCHG_ALL	0x01100400
+#define CONFIG_SYS_MICRON_EMR	       ((1 << 24) |	/* CMD_REQ */ \
+					(0 << 22) |	/* DRAM_CS */ \
+					(0 << 21) |	/* DRAM_RAS */ \
+					(0 << 20) |	/* DRAM_CAS */ \
+					(0 << 19) |	/* DRAM_WEB */ \
+					(1 << 16) |	/* DRAM_BS[2:0] */ \
+					(0 << 15) |	/* */ \
+					(0 << 12) |	/* A12->out */ \
+					(0 << 11) |	/* A11->RDQS */ \
+					(0 << 10) |	/* A10->DQS# */ \
+					(0 <<  7) |	/* OCD program */ \
+					(0 <<  6) |	/* Rtt1 */ \
+					(0 <<  3) |	/* posted CAS# */ \
+					(0 <<  2) |	/* Rtt0 */ \
+					(1 <<  1) |	/* ODS */ \
+					(0 <<  0)	/* DLL */ \
+				     )
+#define CONFIG_SYS_MICRON_EMR2		0x01020000
+#define CONFIG_SYS_MICRON_EMR3		0x01030000
+#define CONFIG_SYS_DDRCMD_RFSH		0x01080000
+#define CONFIG_SYS_MICRON_INIT_DEV_OP	0x01000432
+#define CONFIG_SYS_MICRON_EMR_OCD      ((1 << 24) |	/* CMD_REQ */ \
+					(0 << 22) |	/* DRAM_CS */ \
+					(0 << 21) |	/* DRAM_RAS */ \
+					(0 << 20) |	/* DRAM_CAS */ \
+					(0 << 19) |	/* DRAM_WEB */ \
+					(1 << 16) |	/* DRAM_BS[2:0] */ \
+					(0 << 15) |	/* */ \
+					(0 << 12) |	/* A12->out */ \
+					(0 << 11) |	/* A11->RDQS */ \
+					(1 << 10) |	/* A10->DQS# */ \
+					(7 <<  7) |	/* OCD program */ \
+					(0 <<  6) |	/* Rtt1 */ \
+					(0 <<  3) |	/* posted CAS# */ \
+					(1 <<  2) |	/* Rtt0 */ \
+					(0 <<  1) |	/* ODS */ \
+					(0 <<  0)	/* DLL */ \
+				     )
+
+/*
+ * Backward compatible definitions,
+ * so we do not have to change arch/powerpc/cpu/mpc512x/fixed_sdram.c
+ */
+#define	CONFIG_SYS_DDRCMD_EM2		(CONFIG_SYS_MICRON_EMR2)
+#define CONFIG_SYS_DDRCMD_EM3		(CONFIG_SYS_MICRON_EMR3)
+#define CONFIG_SYS_DDRCMD_EN_DLL	(CONFIG_SYS_MICRON_EMR)
+#define CONFIG_SYS_DDRCMD_OCD_DEFAULT	(CONFIG_SYS_MICRON_EMR_OCD)
+
+/* DDR Priority Manager Configuration */
+#define CONFIG_SYS_MDDRCGRP_PM_CFG1	0x00077777
+#define CONFIG_SYS_MDDRCGRP_PM_CFG2	0x00000000
+#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG	0x00000001
+#define CONFIG_SYS_MDDRCGRP_LUT0_MU	0xFFEEDDCC
+#define CONFIG_SYS_MDDRCGRP_LUT0_ML	0xBBAAAAAA
+#define CONFIG_SYS_MDDRCGRP_LUT1_MU	0x66666666
+#define CONFIG_SYS_MDDRCGRP_LUT1_ML	0x55555555
+#define CONFIG_SYS_MDDRCGRP_LUT2_MU	0x44444444
+#define CONFIG_SYS_MDDRCGRP_LUT2_ML	0x44444444
+#define CONFIG_SYS_MDDRCGRP_LUT3_MU	0x55555555
+#define CONFIG_SYS_MDDRCGRP_LUT3_ML	0x55555558
+#define CONFIG_SYS_MDDRCGRP_LUT4_MU	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT4_ML	0x11111122
+#define CONFIG_SYS_MDDRCGRP_LUT0_AU	0xaaaaaaaa
+#define CONFIG_SYS_MDDRCGRP_LUT0_AL	0xaaaaaaaa
+#define CONFIG_SYS_MDDRCGRP_LUT1_AU	0x66666666
+#define CONFIG_SYS_MDDRCGRP_LUT1_AL	0x66666666
+#define CONFIG_SYS_MDDRCGRP_LUT2_AU	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT2_AL	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT3_AU	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT3_AL	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT4_AU	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT4_AL	0x11111111
+
+/*
+ * NOR FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_CFI				/* use the CFI code */
+#define CONFIG_FLASH_CFI_DRIVER				/* use the CFI driver */
+#define CONFIG_SYS_FLASH_BASE		0xFC000000	/* start of FLASH */
+#define CONFIG_SYS_FLASH_SIZE		0x04000000	/* max flash size */
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ \
+	CONFIG_SYS_FLASH_BASE + 0 * CONFIG_SYS_FLASH_SIZE, \
+	}
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max sectors per device */
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_PROTECTION
+
+/*
+ * SRAM support
+ */
+#define CONFIG_SYS_SRAM_BASE		0x30000000
+#define CONFIG_SYS_SRAM_SIZE		0x00020000	/* 128 KB */
+
+/*
+ * CS related parameters
+ */
+/* CS0 Flash */
+#define CONFIG_SYS_CS0_CFG		0x00031110
+#define CONFIG_SYS_CS0_START		0xFC000000
+#define CONFIG_SYS_CS0_SIZE		0x04000000
+/* CS1 FRAM */
+#define CONFIG_SYS_CS1_CFG		0x00011000
+#define CONFIG_SYS_CS1_START		0xE0000000
+#define CONFIG_SYS_CS1_SIZE		0x00010000
+/* CS2 AS-i 1 */
+#define CONFIG_SYS_CS2_CFG		0x00009100
+#define CONFIG_SYS_CS2_START		0xE0100000
+#define CONFIG_SYS_CS2_SIZE		0x00080000
+/* CS3 netX */
+#define CONFIG_SYS_CS3_CFG		0x000A1140
+#define CONFIG_SYS_CS3_START		0xE0300000
+#define CONFIG_SYS_CS3_SIZE		0x00020000
+/* CS5 safety */
+#define CONFIG_SYS_CS5_CFG		0x0011F000
+#define CONFIG_SYS_CS5_START		0xE0400000
+#define CONFIG_SYS_CS5_SIZE		0x00010000
+/* CS6 AS-i 2 */
+#define CONFIG_SYS_CS6_CFG		0x00009100
+#define CONFIG_SYS_CS6_START		0xE0200000
+#define CONFIG_SYS_CS6_SIZE		0x00080000
+
+/* Don't use alternative CS timing for any CS */
+#define CONFIG_SYS_CS_ALETIMING		0x00000000
+#define CONFIG_SYS_CS_BURST		0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE		0x00000020
+#define CONFIG_SYS_CS_HOLDCYCLE		0x00000020
+
+/* Use SRAM for initial stack */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_SRAM_BASE
+#define CONFIG_SYS_INIT_RAM_END		CONFIG_SYS_SRAM_SIZE
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - \
+					 GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
+
+#ifdef	CONFIG_FSL_DIU_FB
+#define CONFIG_SYS_MALLOC_LEN		(6 * 1024 * 1024)
+#else
+#define CONFIG_SYS_MALLOC_LEN		(512 * 1024)
+#endif
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX		1
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE		3	/* console on PSC3 */
+#define CONFIG_SYS_PSC3
+#if CONFIG_PSC_CONSOLE != 3
+#error CONFIG_PSC_CONSOLE must be 3
+#endif
+
+#define CONFIG_BAUDRATE			115200	/* ... at 115200 bps */
+
+#define CONSOLE_FIFO_TX_SIZE		FIFOC_PSC3_TX_SIZE
+#define CONSOLE_FIFO_TX_ADDR		FIFOC_PSC3_TX_ADDR
+#define CONSOLE_FIFO_RX_SIZE		FIFOC_PSC3_RX_SIZE
+#define CONSOLE_FIFO_RX_ADDR		FIFOC_PSC3_RX_ADDR
+
+/*
+ * Clocks in use
+ */
+#define SCCR1_CLOCKS_EN	(CLOCK_SCCR1_CFG_EN |		\
+			 CLOCK_SCCR1_LPC_EN |		\
+			 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
+			 CLOCK_SCCR1_PSC_EN(7) |	\
+			 CLOCK_SCCR1_PSCFIFO_EN |	\
+			 CLOCK_SCCR1_DDR_EN |		\
+			 CLOCK_SCCR1_FEC_EN |		\
+			 CLOCK_SCCR1_TPR_EN)
+
+#define SCCR2_CLOCKS_EN	(CLOCK_SCCR2_MEM_EN |		\
+			 CLOCK_SCCR2_SPDIF_EN |		\
+			 CLOCK_SCCR2_DIU_EN |		\
+			 CLOCK_SCCR2_I2C_EN)
+
+
+#define CONFIG_CMDLINE_EDITING		1	/* command line history */
+
+/* I2C */
+#define CONFIG_HARD_I2C			/* I2C with hardware support */
+#define CONFIG_I2C_MULTI_BUS
+
+/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+
+/*
+ * IIM - IC Identification Module
+ */
+#undef CONFIG_FSL_IIM
+
+/*
+ * EEPROM configuration for Atmel AT24C01:
+ * 8-bit addresses, 30ms write delay, 32-Byte Page Write Mode
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x52
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	30
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC512x_FEC		1
+#define CONFIG_NET_MULTI
+#define CONFIG_PHY_ADDR			0x1F
+#define CONFIG_MII			1	/* MII PHY management */
+#define CONFIG_FEC_AN_TIMEOUT		1
+#define CONFIG_HAS_ETH0
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH		1
+/* This has to be a multiple of the flash sector size */
+#define CONFIG_ENV_ADDR			0xFFF40000
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_SECT_SIZE		0x20000
+
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_ADDR_REDUND		(CONFIG_ENV_ADDR + \
+					 CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND		(CONFIG_ENV_SIZE)
+
+#define CONFIG_LOADS_ECHO		1
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_FUSE
+#define CONFIG_CMD_I2C
+#undef CONFIG_CMD_IDE
+#undef CONFIG_CMD_EXT2
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+
+#if defined(CONFIG_PCI)
+#define CONFIG_CMD_PCI
+#endif
+
+#if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2)
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION
+#define CONFIG_ISO_PARTITION
+#endif /* defined(CONFIG_CMD_IDE) */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT	"ac14xx> "	/* Monitor Command Prompt */
+
+#ifdef CONFIG_CMD_KGDB
+# define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+# define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
+				 sizeof(CONFIG_SYS_PROMPT) + 16)
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS	32
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)
+
+/* Cache Configuration */
+#define CONFIG_SYS_DCACHE_SIZE		32768
+#define CONFIG_SYS_CACHELINE_SIZE	32
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of 32 */
+#endif
+
+#define CONFIG_SYS_HID0_INIT		0x000000000
+#define CONFIG_SYS_HID0_FINAL		(HID0_ENABLE_MACHINE_CHECK | \
+					 HID0_ICE)
+#define CONFIG_SYS_HID2	HID2_HBE
+
+#define CONFIG_HIGH_BATS		1	/* High BATs supported */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD			0x01
+#define BOOTFLAG_WARM			0x02
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE		230400	/* speed of kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_TIMESTAMP
+
+/* default load addr for tftp and bootm */
+#define CONFIG_LOADADDR		400000
+
+#define CONFIG_BOOTDELAY	2	/* -1 disables auto-boot */
+
+/* the builtin environment and standard greeting */
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+	"echo"
+
+#define CONFIG_EXTRA_ENV_SETTINGS_DEVEL					\
+	"muster_nr=-00\0"						\
+	"fromram=run ramargs addip addtty; "				\
+		"tftp ${fdt_addr_r} ac14xx/ac14xx.dtb${muster_nr}; "	\
+		"tftp ${kernel_addr_r} ac14xx/uImage${muster_nr}; "	\
+		"tftp ${ramdisk_addr_r} ac14xx/uFS${muster_nr}; "	\
+		"bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0" \
+	"fromnfs=run nfsargs addip addtty; "				\
+		"tftp ${fdt_addr_r} ac14xx/ac14xx.dtb${muster_nr}; "	\
+		"tftp ${kernel_addr_r} ac14xx/uImage${muster_nr}; "	\
+		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
+	"fromflash=run nfsargs addip addtty; "				\
+		"bootm fc020000 - fc000000\0"				\
+	"mtdargsrec=setenv bootargs root=/dev/mtdblock1 ro\0"		\
+	"recovery=run mtdargsrec addip addtty; "			\
+		"bootm ffd20000 - ffee0000\0"				\
+	"production=run ramargs addip addtty; "				\
+		"bootm fc020000 fc400000 fc000000\0"			\
+	"mtdargs=setenv bootargs root=/dev/mtdblock1 ro\0"		\
+	"prodmtd=run mtdargs addip addtty; "				\
+		"bootm fc020000 - fc000000\0"				\
+	""
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"u-boot_addr_r=200000\0"					\
+	"kernel_addr_r=600000\0"					\
+	"fdt_addr_r=a00000\0"						\
+	"ramdisk_addr_r=b00000\0"					\
+	"u-boot_addr=FFF00000\0"					\
+	"kernel_addr=FC020000\0"					\
+	"fdt_addr=FC000000\0"						\
+	"ramdisk_addr=FC400000\0"					\
+	"verify=n\0"							\
+	"ramdiskfile=ac14xx/uRamdisk\0"					\
+	"u-boot=ac14xx/u-boot.bin\0"					\
+	"bootfile=ac14xx/uImage\0"					\
+	"fdtfile=ac14xx/ac14xx.dtb\0"					\
+	"netdev=eth0\0"							\
+	"consdev=ttyPSC0\0"						\
+	"hostname=ac14xx\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}${muster_nr}\0"	\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} "				\
+		"console=${consdev},${baudrate}\0"			\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
+		"tftp ${fdt_addr_r} ${fdtfile};"			\
+		"run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
+	"net_self=tftp ${kernel_addr_r} ${bootfile};"			\
+		"tftp ${ramdisk_addr_r} ${ramdiskfile};"		\
+		"tftp ${fdt_addr_r} ${fdtfile};"			\
+		"run ramargs addip addtty;"				\
+		"bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
+	"load=tftp ${u-boot_addr_r} ${u-boot}\0"			\
+	"update=protect off ${u-boot_addr} +${filesize};"		\
+		"era ${u-boot_addr} +${filesize};"			\
+		"cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0"	\
+	CONFIG_EXTRA_ENV_SETTINGS_DEVEL					\
+	"upd=run load update\0"						\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run production"
+
+#define CONFIG_ARP_TIMEOUT	200UL
+
+#define CONFIG_FIT		1
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES	1
+
+#define OF_CPU			"PowerPC,5121@0"
+#define OF_SOC_COMPAT		"fsl,mpc5121-immr"
+#define OF_TBCLK		(bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH		"/soc@80000000/serial@11300"
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/acadia.h b/qemu/roms/u-boot/include/configs/acadia.h
new file mode 100644
index 000000000..4dd5720d2
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/acadia.h
@@ -0,0 +1,265 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/************************************************************************
+ * acadia.h - configuration for AMCC Acadia (405EZ)
+ ***********************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_ACADIA		1		/* Board is Acadia	*/
+#define CONFIG_405EZ		1		/* Specifc 405EZ support*/
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xFFF80000
+#endif
+
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME		acadia
+#include "amcc-common.h"
+
+/* Detect Acadia PLL input clock automatically via CPLD bit		*/
+#define CONFIG_SYS_CLK_FREQ    ((in8(CONFIG_SYS_CPLD_BASE + 0) == 0x0c) ? \
+				66666666 : 33333000)
+
+#define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_early_init_f */
+#define CONFIG_MISC_INIT_F	1		/* Call misc_init_f	*/
+
+#define CONFIG_NO_SERIAL_EEPROM
+/*#undef CONFIG_NO_SERIAL_EEPROM*/
+
+#ifdef CONFIG_NO_SERIAL_EEPROM
+/*----------------------------------------------------------------------------
+ * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
+ * assuming a 66MHz input clock to the 405EZ.
+ *---------------------------------------------------------------------------*/
+/* #define PLLMR0_100_100_12 */
+#define PLLMR0_200_133_66
+/* #define PLLMR0_266_160_80 */
+/* #define PLLMR0_333_166_83 */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_FLASH_BASE		0xfe000000
+#define CONFIG_SYS_CPLD_BASE		0x80000000
+#define CONFIG_SYS_NAND_ADDR		0xd0000000
+#define CONFIG_SYS_USB_HOST		0xef603000	/* USB OHCI 1.1 controller	*/
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_TEMP_STACK_OCM	1		/* OCM as init ram	*/
+
+/* On Chip Memory location */
+#define CONFIG_SYS_OCM_DATA_ADDR	0xf8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x4000			/* 16K of onchip SRAM		*/
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR	/* inside of SRAM		*/
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE	/* Size of used area in RAM	*/
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK			/* external serial clock */
+#define CONFIG_SYS_BASE_BAUD		691200
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+#define CONFIG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible	*/
+#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
+
+#define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	0x40000 /* size of one complete sector	*/
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
+#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+#endif
+
+/*-----------------------------------------------------------------------
+ * RAM (CRAM)
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_MBYTES_RAM		64		/* 64MB			*/
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
+
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR	(0xa8>>1)
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+/* I2C SYSMON (LM75, AD7414 is almost compatible)			*/
+#define CONFIG_DTT_LM75		1		/* ON Semi's LM75	*/
+#define CONFIG_DTT_AD7414	1		/* use AD7414		*/
+#define CONFIG_DTT_SENSORS	{0}		/* Sensor addresses	*/
+#define CONFIG_SYS_DTT_MAX_TEMP	70
+#define CONFIG_SYS_DTT_LOW_TEMP	-30
+#define CONFIG_SYS_DTT_HYSTERESIS	3
+
+/*-----------------------------------------------------------------------
+ * Ethernet
+ *----------------------------------------------------------------------*/
+#define	CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_HAS_ETH0		1
+
+/*
+ * Default environment variables
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_AMCC_DEF_ENV						\
+	CONFIG_AMCC_DEF_ENV_POWERPC					\
+	CONFIG_AMCC_DEF_ENV_PPC_OLD					\
+	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
+	"kernel_addr=fff10000\0"					\
+	"ramdisk_addr=fff20000\0"					\
+	"kozio=bootm ffc60000\0"					\
+	""
+
+#define CONFIG_USB_OHCI
+#define CONFIG_USB_STORAGE
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+#define CONFIG_SUPPORT_VFAT
+
+/*
+ * Commands additional to the ones defined in amcc-common.h
+ */
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_USB
+
+/*-----------------------------------------------------------------------
+ * NAND FLASH
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		(CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
+#define CONFIG_SYS_NAND_SELECT_DEVICE  1	/* nand driver supports mutipl. chips	*/
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_NAND_CS		3
+/* Memory Bank 0 (Flash) initialization						*/
+#define CONFIG_SYS_EBC_PB0AP		0x03337200
+#define CONFIG_SYS_EBC_PB0CR		0xfe0bc000
+
+/* Memory Bank 3 (NAND-FLASH) initialization					*/
+#define CONFIG_SYS_EBC_PB3AP		0x018003c0
+#define CONFIG_SYS_EBC_PB3CR		(CONFIG_SYS_NAND_ADDR | 0x1c000)
+
+/* Just initial configuration for CRAM. Will be changed in memory.c to sync mode*/
+/* Memory Bank 1 (CRAM) initialization						*/
+#define CONFIG_SYS_EBC_PB1AP		0x030400c0
+#define CONFIG_SYS_EBC_PB1CR		0x000bc000
+
+/* Memory Bank 2 (CRAM) initialization						*/
+#define CONFIG_SYS_EBC_PB2AP		0x030400c0
+#define CONFIG_SYS_EBC_PB2CR		0x020bc000
+
+/* Memory Bank 4 (CPLD) initialization						*/
+#define CONFIG_SYS_EBC_PB4AP		0x04006000
+#define CONFIG_SYS_EBC_PB4CR		(CONFIG_SYS_CPLD_BASE | 0x18000)
+
+#define CONFIG_SYS_EBC_CFG		0xf8400000
+
+/*-----------------------------------------------------------------------
+ * GPIO Setup
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_GPIO_CRAM_CLK	8
+#define CONFIG_SYS_GPIO_CRAM_WAIT	9		/* GPIO-In		*/
+#define CONFIG_SYS_GPIO_CRAM_ADV	10
+#define CONFIG_SYS_GPIO_CRAM_CRE	(32 + 21)	/* GPIO-Out		*/
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO_0 setup (PPC405EZ specific)
+ *
+ * GPIO0[0-2]	- External Bus Controller CS_4 - CS_6 Outputs
+ * GPIO0[3]	- NAND FLASH Controller CE3 (NFCE3) Output
+ * GPIO0[4]	- External Bus Controller Hold Input
+ * GPIO0[5]	- External Bus Controller Priority Input
+ * GPIO0[6]	- External Bus Controller HLDA Output
+ * GPIO0[7]	- External Bus Controller Bus Request Output
+ * GPIO0[8]	- CRAM Clk Output
+ * GPIO0[9]	- External Bus Controller Ready Input
+ * GPIO0[10]	- CRAM Adv Output
+ * GPIO0[11-24]	- NAND Flash Control Data -> Bypasses GPIO when enabled
+ * GPIO0[25]	- External DMA Request Input
+ * GPIO0[26]	- External DMA EOT I/O
+ * GPIO0[25]	- External DMA Ack_n Output
+ * GPIO0[17-23]	- External Interrupts IRQ0 - IRQ6 inputs
+ * GPIO0[28-30]	- Trace Outputs / PWM Inputs
+ * GPIO0[31]	- PWM_8 I/O
+ */
+#define CONFIG_SYS_GPIO0_TCR		0xC0A00000
+#define CONFIG_SYS_GPIO0_OSRL		0x50004400
+#define CONFIG_SYS_GPIO0_OSRH		0x02000055
+#define CONFIG_SYS_GPIO0_ISR1L		0x00001000
+#define CONFIG_SYS_GPIO0_ISR1H		0x00000055
+#define CONFIG_SYS_GPIO0_TSRL		0x02000000
+#define CONFIG_SYS_GPIO0_TSRH		0x00000055
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO_1 setup (PPC405EZ specific)
+ *
+ * GPIO1[0-6]	- PWM_9 to PWM_15 I/O
+ * GPIO1[7]	- PWM_DIV_CLK (Out) / IRQ4 Input
+ * GPIO1[8]	- TS5 Output / DAC_IP_TRIG Input
+ * GPIO1[9]	- TS6 Output / ADC_IP_TRIG Input
+ * GPIO1[10-12]	- UART0 Control Inputs
+ * GPIO1[13]	- UART0_DTR_N Output/IEEE_1588_TS Output/TMRCLK Input
+ * GPIO1[14]	- UART0_RTS_N Output/SPI_SS_2_N Output
+ * GPIO1[15]	- SPI_SS_3_N Output/UART0_RI_N Input
+ * GPIO1[16]	- SPI_SS_1_N Output
+ * GPIO1[17-20]	- Trace Output/External Interrupts IRQ0 - IRQ3 inputs
+ */
+#define CONFIG_SYS_GPIO1_TCR		0xFFFF8414
+#define CONFIG_SYS_GPIO1_OSRL		0x40000110
+#define CONFIG_SYS_GPIO1_OSRH		0x55455555
+#define CONFIG_SYS_GPIO1_ISR1L		0x15555445
+#define CONFIG_SYS_GPIO1_ISR1H		0x00000000
+#define CONFIG_SYS_GPIO1_TSRL		0x00000000
+#define CONFIG_SYS_GPIO1_TSRH		0x00000000
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/adp-ag101.h b/qemu/roms/u-boot/include/configs/adp-ag101.h
new file mode 100644
index 000000000..e318c7543
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/adp-ag101.h
@@ -0,0 +1,387 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/ag101.h>
+
+/*
+ * CPU and Board Configuration Options
+ */
+#define CONFIG_ADP_AG101
+
+#define CONFIG_USE_INTERRUPT
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * Definitions related to passing arguments to kernel.
+ */
+#define CONFIG_CMDLINE_TAG			/* send commandline to Kernel */
+#define CONFIG_SETUP_MEMORY_TAGS	/* send memory definition to kernel */
+#define CONFIG_INITRD_TAG			/* send initrd params */
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_MEM_REMAP
+#endif
+
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_TEXT_BASE	0x03200000
+#else
+#define CONFIG_SYS_TEXT_BASE	0x00000000
+#endif
+
+/*
+ * Timer
+ */
+#define CONFIG_SYS_CLK_FREQ	48000000
+#define VERSION_CLOCK		CONFIG_SYS_CLK_FREQ
+
+/*
+ * Use Externel CLOCK or PCLK
+ */
+#undef CONFIG_FTRTC010_EXTCLK
+
+#ifndef CONFIG_FTRTC010_EXTCLK
+#define CONFIG_FTRTC010_PCLK
+#endif
+
+#ifdef CONFIG_FTRTC010_EXTCLK
+#define TIMER_CLOCK	32768			/* CONFIG_FTRTC010_EXTCLK */
+#else
+#define TIMER_CLOCK	CONFIG_SYS_HZ		/* CONFIG_FTRTC010_PCLK */
+#endif
+
+#define TIMER_LOAD_VAL	0xffffffff
+
+/*
+ * Real Time Clock
+ */
+#define CONFIG_RTC_FTRTC010
+
+/*
+ * Real Time Clock Divider
+ * RTC_DIV_COUNT			(OSC_CLK/OSC_5MHZ)
+ */
+#define OSC_5MHZ			(5*1000000)
+#define OSC_CLK				(2*OSC_5MHZ)
+#define RTC_DIV_COUNT			(OSC_CLK/OSC_5MHZ)
+
+/*
+ * Serial console configuration
+ */
+
+/* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
+#define CONFIG_BAUDRATE			38400
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_COM1		CONFIG_FTUART010_02_BASE
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#define CONFIG_SYS_NS16550_CLK		((46080000 * 20) / 25)	/* AG101 */
+
+/*
+ * Ethernet
+ */
+#define CONFIG_FTMAC100
+
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * SD (MMC) controller
+ */
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FTSDC010
+#define CONFIG_FTSDC010_NUMBER		1
+#define CONFIG_FTSDC010_SDIO
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_PING
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_PROMPT	"NDS32 # "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE	\
+	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS	16
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+/*
+ * Size of malloc() pool
+ */
+/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
+#define CONFIG_SYS_MALLOC_LEN		(512 << 10)
+
+/*
+ * AHB Controller configuration
+ */
+#define CONFIG_FTAHBC020S
+
+#ifdef CONFIG_FTAHBC020S
+#include <faraday/ftahbc020s.h>
+
+/* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
+#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE	0x100
+
+/*
+ * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
+ * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
+ * in C language.
+ */
+#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
+	(FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
+					FTAHBC020S_SLAVE_BSR_SIZE(0xb))
+#endif
+
+/*
+ * Watchdog
+ */
+#define CONFIG_FTWDT010_WATCHDOG
+
+/*
+ * PMU Power controller configuration
+ */
+#define CONFIG_PMU
+#define CONFIG_FTPMU010_POWER
+
+#ifdef CONFIG_FTPMU010_POWER
+#include <faraday/ftpmu010.h>
+#define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS		0x0E
+#define CONFIG_SYS_FTPMU010_SDRAMHTC	(FTPMU010_SDRAMHTC_EBICTRL_DCSR  | \
+					 FTPMU010_SDRAMHTC_EBIDATA_DCSR  | \
+					 FTPMU010_SDRAMHTC_SDRAMCS_DCSR  | \
+					 FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
+					 FTPMU010_SDRAMHTC_CKE_DCSR	 | \
+					 FTPMU010_SDRAMHTC_DQM_DCSR	 | \
+					 FTPMU010_SDRAMHTC_SDCLK_DCSR)
+#endif
+
+/*
+ * SDRAM controller configuration
+ */
+#define CONFIG_FTSDMC021
+
+#ifdef CONFIG_FTSDMC021
+#include <faraday/ftsdmc021.h>
+
+#define CONFIG_SYS_FTSDMC021_TP1	(FTSDMC021_TP1_TRP(1)	|	\
+					 FTSDMC021_TP1_TRCD(1)	|	\
+					 FTSDMC021_TP1_TRF(3)	|	\
+					 FTSDMC021_TP1_TWR(1)	|	\
+					 FTSDMC021_TP1_TCL(2))
+
+#define CONFIG_SYS_FTSDMC021_TP2	(FTSDMC021_TP2_INI_PREC(4) |	\
+					 FTSDMC021_TP2_INI_REFT(8) |	\
+					 FTSDMC021_TP2_REF_INTV(0x180))
+
+/*
+ * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S,
+ * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in
+ * C language.
+ */
+#define CONFIG_SYS_FTSDMC021_CR1	(FTSDMC021_CR1_DDW(2)	 |	\
+					 FTSDMC021_CR1_DSZ(3)	 |	\
+					 FTSDMC021_CR1_MBW(2)	 |	\
+					 FTSDMC021_CR1_BNKSIZE(6))
+
+#define CONFIG_SYS_FTSDMC021_CR2	(FTSDMC021_CR2_IPREC	 |	\
+					 FTSDMC021_CR2_IREF	 |	\
+					 FTSDMC021_CR2_ISMR)
+
+#define CONFIG_SYS_FTSDMC021_BANK0_BASE	CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
+#define CONFIG_SYS_FTSDMC021_BANK0_BSR	(FTSDMC021_BANK_ENABLE	 |	\
+					 CONFIG_SYS_FTSDMC021_BANK0_BASE)
+
+#define CONFIG_SYS_FTSDMC021_BANK1_BASE \
+	(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20))
+#define CONFIG_SYS_FTSDMC021_BANK1_BSR (FTSDMC021_BANK_ENABLE   |      \
+		CONFIG_SYS_FTSDMC021_BANK1_BASE)
+
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#if defined(CONFIG_MEM_REMAP) || defined(CONFIG_SKIP_LOWLEVEL_INIT)
+#define PHYS_SDRAM_0		0x00000000	/* SDRAM Bank #1 */
+#if defined(CONFIG_MEM_REMAP)
+#define PHYS_SDRAM_0_AT_INIT	0x10000000	/* SDRAM Bank #1 before remap*/
+#endif
+#else	/* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */
+#define PHYS_SDRAM_0		0x10000000	/* SDRAM Bank #1 */
+#endif
+#define PHYS_SDRAM_1 \
+	(PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)	/* SDRAM Bank #2 */
+
+#define CONFIG_NR_DRAM_BANKS	2		/* we have 2 bank of DRAM */
+#define PHYS_SDRAM_0_SIZE	0x04000000	/* 64 MB */
+#define PHYS_SDRAM_1_SIZE	0x04000000	/* 64 MB */
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_0
+
+#ifdef CONFIG_MEM_REMAP
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
+					GENERATED_GBL_DATA_SIZE)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 - \
+					GENERATED_GBL_DATA_SIZE)
+#endif /* CONFIG_MEM_REMAP */
+
+/*
+ * Load address and memory test area should agree with
+ * arch/nds32/config.mk. Be careful not to overwrite U-boot itself.
+ */
+#define CONFIG_SYS_LOAD_ADDR		0x300000
+
+/* memtest works on 63 MB in DRAM */
+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_0
+#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_0 + 0x03F00000)
+
+/*
+ * Static memory controller configuration
+ */
+#define CONFIG_FTSMC020
+
+#ifdef CONFIG_FTSMC020
+#include <faraday/ftsmc020.h>
+
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_FTSMC020_CONFIGS	{			\
+	{ FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, },	\
+	{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },	\
+}
+#else
+#define CONFIG_SYS_FTSMC020_CONFIGS	{			\
+	{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },	\
+}
+#endif
+
+/*
+ * There are 2 bank connected to FTSMC020 on ADP-AG101.
+ * You can use jumper and switch to force it booted from ROM or FLASH.
+ * MA17: Lo, SW5 = "0101": BANK0: ROM, BANK1: FLASH.
+ * MA17: Hi, SW5 = "1010": BANK0: FLASH; ROM is disabled.
+ */
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT	/* FLASH is on BANK 0 */
+#define FTSMC020_BANK0_LOWLV_CONFIG	(FTSMC020_BANK_ENABLE	|	\
+					 FTSMC020_BANK_SIZE_32M	|	\
+					 FTSMC020_BANK_MBW_32)
+
+#define FTSMC020_BANK0_LOWLV_TIMING	(FTSMC020_TPR_RBE	|	\
+					 FTSMC020_TPR_AST(1)	|	\
+					 FTSMC020_TPR_CTW(1)	|	\
+					 FTSMC020_TPR_ATI(1)	|	\
+					 FTSMC020_TPR_AT2(1)	|	\
+					 FTSMC020_TPR_WTC(1)	|	\
+					 FTSMC020_TPR_AHT(1)	|	\
+					 FTSMC020_TPR_TRNA(1))
+#endif
+
+/*
+ * This FTSMC020_BANK0_CONFIG indecates the setting of BANK0.
+ * 1. When CONFIG_SKIP_LOWLEVEL_INIT is enabled, BANK0 is EEPROM,
+ *    Do NOT enable BANK0 in FTSMC020_BANK0_CONFIG under this condition.
+ * 2. When CONFIG_SKIP_LOWLEVEL_INIT is undefined, BANK0 is FLASH.
+ */
+#define FTSMC020_BANK0_CONFIG	(FTSMC020_BANK_SIZE_32M           |	\
+				 FTSMC020_BANK_MBW_32)
+
+#define FTSMC020_BANK0_TIMING	(FTSMC020_TPR_RBE      |	\
+				 FTSMC020_TPR_AST(3)   |	\
+				 FTSMC020_TPR_CTW(3)   |	\
+				 FTSMC020_TPR_ATI(0xf) |	\
+				 FTSMC020_TPR_AT2(3)   |	\
+				 FTSMC020_TPR_WTC(3)   |	\
+				 FTSMC020_TPR_AHT(3)   |	\
+				 FTSMC020_TPR_TRNA(0xf))
+
+#define FTSMC020_BANK1_CONFIG	(FTSMC020_BANK_ENABLE	|	\
+				 FTSMC020_BANK_BASE(PHYS_FLASH_1) |	\
+				 FTSMC020_BANK_SIZE_32M	|	\
+				 FTSMC020_BANK_MBW_32)
+
+#define FTSMC020_BANK1_TIMING	(FTSMC020_TPR_RBE	|	\
+				 FTSMC020_TPR_AST(1)	|	\
+				 FTSMC020_TPR_CTW(1)	|	\
+				 FTSMC020_TPR_ATI(1)	|	\
+				 FTSMC020_TPR_AT2(1)	|	\
+				 FTSMC020_TPR_WTC(1)	|	\
+				 FTSMC020_TPR_AHT(1)	|	\
+				 FTSMC020_TPR_TRNA(1))
+#endif /* CONFIG_FTSMC020 */
+
+/*
+ * FLASH and environment organization
+ */
+/* use CFI framework */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/* support JEDEC */
+
+/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
+#define PHYS_FLASH_1			0x80400000	/* BANK 1 */
+#else	/* !CONFIG_SKIP_LOWLEVEL_INIT */
+#ifdef CONFIG_MEM_REMAP
+#define PHYS_FLASH_1			0x80000000	/* BANK 0 */
+#else
+#define PHYS_FLASH_1			0x00000000	/* BANK 0 */
+#endif	/* CONFIG_MEM_REMAP */
+#endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
+
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ PHYS_FLASH_1, }
+#define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* TO for Flash Erase (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* TO for Flash Write (ms) */
+
+/* max number of memory banks */
+/*
+ * There are 4 banks supported for this Controller,
+ * but we have only 1 bank connected to flash on board
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+
+/* max number of sectors on one chip */
+#define CONFIG_FLASH_SECTOR_SIZE	(0x10000*2*2)
+#define CONFIG_ENV_SECT_SIZE		CONFIG_FLASH_SECTOR_SIZE
+#define CONFIG_SYS_MAX_FLASH_SECT	128
+
+/* environments */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_MONITOR_BASE + 0x40000)
+#define CONFIG_ENV_SIZE			8192
+#define CONFIG_ENV_OVERWRITE
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/adp-ag101p.h b/qemu/roms/u-boot/include/configs/adp-ag101p.h
new file mode 100644
index 000000000..24904b0b7
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/adp-ag101p.h
@@ -0,0 +1,363 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/ag101.h>
+
+/*
+ * CPU and Board Configuration Options
+ */
+#define CONFIG_ADP_AG101P
+
+#define CONFIG_USE_INTERRUPT
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * Definitions related to passing arguments to kernel.
+ */
+#define CONFIG_CMDLINE_TAG			/* send commandline to Kernel */
+#define CONFIG_SETUP_MEMORY_TAGS	/* send memory definition to kernel */
+#define CONFIG_INITRD_TAG			/* send initrd params */
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_MEM_REMAP
+#endif
+
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_TEXT_BASE	0x03200000
+#else
+#define CONFIG_SYS_TEXT_BASE	0x00000000
+#endif
+
+/*
+ * Timer
+ */
+#define CONFIG_SYS_CLK_FREQ	39062500
+#define VERSION_CLOCK		CONFIG_SYS_CLK_FREQ
+
+/*
+ * Use Externel CLOCK or PCLK
+ */
+#undef CONFIG_FTRTC010_EXTCLK
+
+#ifndef CONFIG_FTRTC010_EXTCLK
+#define CONFIG_FTRTC010_PCLK
+#endif
+
+#ifdef CONFIG_FTRTC010_EXTCLK
+#define TIMER_CLOCK	32768			/* CONFIG_FTRTC010_EXTCLK */
+#else
+#define TIMER_CLOCK	CONFIG_SYS_HZ		/* CONFIG_FTRTC010_PCLK */
+#endif
+
+#define TIMER_LOAD_VAL	0xffffffff
+
+/*
+ * Real Time Clock
+ */
+#define CONFIG_RTC_FTRTC010
+
+/*
+ * Real Time Clock Divider
+ * RTC_DIV_COUNT			(OSC_CLK/OSC_5MHZ)
+ */
+#define OSC_5MHZ			(5*1000000)
+#define OSC_CLK				(4*OSC_5MHZ)
+#define RTC_DIV_COUNT			(0.5)	/* Why?? */
+
+/*
+ * Serial console configuration
+ */
+
+/* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
+#define CONFIG_BAUDRATE			38400
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_COM1		CONFIG_FTUART010_02_BASE
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#define CONFIG_SYS_NS16550_CLK		((18432000 * 20) / 25)	/* AG101P */
+
+/*
+ * Ethernet
+ */
+#define CONFIG_FTMAC100
+
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * SD (MMC) controller
+ */
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FTSDC010
+#define CONFIG_FTSDC010_NUMBER		1
+#define CONFIG_FTSDC010_SDIO
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_PING
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_PROMPT	"NDS32 # "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE	\
+	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS	16
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+/*
+ * Size of malloc() pool
+ */
+/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
+#define CONFIG_SYS_MALLOC_LEN		(512 << 10)
+
+/*
+ * AHB Controller configuration
+ */
+#define CONFIG_FTAHBC020S
+
+#ifdef CONFIG_FTAHBC020S
+#include <faraday/ftahbc020s.h>
+
+/* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
+#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE	0x100
+
+/*
+ * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
+ * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
+ * in C language.
+ */
+#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
+	(FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
+					FTAHBC020S_SLAVE_BSR_SIZE(0xb))
+#endif
+
+/*
+ * Watchdog
+ */
+#define CONFIG_FTWDT010_WATCHDOG
+
+/*
+ * PMU Power controller configuration
+ */
+#define CONFIG_PMU
+#define CONFIG_FTPMU010_POWER
+
+#ifdef CONFIG_FTPMU010_POWER
+#include <faraday/ftpmu010.h>
+#define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS		0x0E
+#define CONFIG_SYS_FTPMU010_SDRAMHTC	(FTPMU010_SDRAMHTC_EBICTRL_DCSR  | \
+					 FTPMU010_SDRAMHTC_EBIDATA_DCSR  | \
+					 FTPMU010_SDRAMHTC_SDRAMCS_DCSR  | \
+					 FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
+					 FTPMU010_SDRAMHTC_CKE_DCSR	 | \
+					 FTPMU010_SDRAMHTC_DQM_DCSR	 | \
+					 FTPMU010_SDRAMHTC_SDCLK_DCSR)
+#endif
+
+/*
+ * SDRAM controller configuration
+ */
+#define CONFIG_FTSDMC021
+
+#ifdef CONFIG_FTSDMC021
+#include <faraday/ftsdmc021.h>
+
+#define CONFIG_SYS_FTSDMC021_TP1	(FTSDMC021_TP1_TRAS(2)	|	\
+					 FTSDMC021_TP1_TRP(1)	|	\
+					 FTSDMC021_TP1_TRCD(1)	|	\
+					 FTSDMC021_TP1_TRF(3)	|	\
+					 FTSDMC021_TP1_TWR(1)	|	\
+					 FTSDMC021_TP1_TCL(2))
+
+#define CONFIG_SYS_FTSDMC021_TP2	(FTSDMC021_TP2_INI_PREC(4) |	\
+					 FTSDMC021_TP2_INI_REFT(8) |	\
+					 FTSDMC021_TP2_REF_INTV(0x180))
+
+/*
+ * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S,
+ * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in
+ * C language.
+ */
+#define CONFIG_SYS_FTSDMC021_CR1	(FTSDMC021_CR1_DDW(2)	 |	\
+					 FTSDMC021_CR1_DSZ(3)	 |	\
+					 FTSDMC021_CR1_MBW(2)	 |	\
+					 FTSDMC021_CR1_BNKSIZE(6))
+
+#define CONFIG_SYS_FTSDMC021_CR2	(FTSDMC021_CR2_IPREC	 |	\
+					 FTSDMC021_CR2_IREF	 |	\
+					 FTSDMC021_CR2_ISMR)
+
+#define CONFIG_SYS_FTSDMC021_BANK0_BASE	CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
+#define CONFIG_SYS_FTSDMC021_BANK0_BSR	(FTSDMC021_BANK_ENABLE	 |	\
+					 CONFIG_SYS_FTSDMC021_BANK0_BASE)
+
+#define CONFIG_SYS_FTSDMC021_BANK1_BASE	\
+	(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20))
+#define CONFIG_SYS_FTSDMC021_BANK1_BSR	(FTSDMC021_BANK_ENABLE	 |	\
+					 CONFIG_SYS_FTSDMC021_BANK1_BASE)
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#if defined(CONFIG_MEM_REMAP) || defined(CONFIG_SKIP_LOWLEVEL_INIT)
+#define PHYS_SDRAM_0		0x00000000	/* SDRAM Bank #1 */
+#if defined(CONFIG_MEM_REMAP)
+#define PHYS_SDRAM_0_AT_INIT	0x10000000	/* SDRAM Bank #1 before remap*/
+#endif
+#else	/* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */
+#define PHYS_SDRAM_0		0x10000000	/* SDRAM Bank #1 */
+#endif
+#define PHYS_SDRAM_1 \
+	(PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)	/* SDRAM Bank #2 */
+
+#define CONFIG_NR_DRAM_BANKS	2		/* we have 2 bank of DRAM */
+#define PHYS_SDRAM_0_SIZE	0x04000000	/* 64 MB */
+#define PHYS_SDRAM_1_SIZE	0x04000000	/* 64 MB */
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_0
+
+#ifdef CONFIG_MEM_REMAP
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
+					GENERATED_GBL_DATA_SIZE)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 - \
+					GENERATED_GBL_DATA_SIZE)
+#endif /* CONFIG_MEM_REMAP */
+
+/*
+ * Load address and memory test area should agree with
+ * arch/nds32/config.mk. Be careful not to overwrite U-boot itself.
+ */
+#define CONFIG_SYS_LOAD_ADDR		0x300000
+
+/* memtest works on 63 MB in DRAM */
+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_0
+#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_0 + 0x03F00000)
+
+/*
+ * Static memory controller configuration
+ */
+#define CONFIG_FTSMC020
+
+#ifdef CONFIG_FTSMC020
+#include <faraday/ftsmc020.h>
+
+#define CONFIG_SYS_FTSMC020_CONFIGS	{			\
+	{ FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, },	\
+	{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },	\
+}
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT	/* FLASH is on BANK 0 */
+#define FTSMC020_BANK0_LOWLV_CONFIG	(FTSMC020_BANK_ENABLE	|	\
+					 FTSMC020_BANK_SIZE_32M	|	\
+					 FTSMC020_BANK_MBW_32)
+
+#define FTSMC020_BANK0_LOWLV_TIMING	(FTSMC020_TPR_RBE	|	\
+					 FTSMC020_TPR_AST(1)	|	\
+					 FTSMC020_TPR_CTW(1)	|	\
+					 FTSMC020_TPR_ATI(1)	|	\
+					 FTSMC020_TPR_AT2(1)	|	\
+					 FTSMC020_TPR_WTC(1)	|	\
+					 FTSMC020_TPR_AHT(1)	|	\
+					 FTSMC020_TPR_TRNA(1))
+#endif
+
+/*
+ * FLASH on ADP_AG101P is connected to BANK0
+ * Just disalbe the other BANK to avoid detection error.
+ */
+#define FTSMC020_BANK0_CONFIG	(FTSMC020_BANK_ENABLE             |	\
+				 FTSMC020_BANK_BASE(PHYS_FLASH_1) |	\
+				 FTSMC020_BANK_SIZE_32M           |	\
+				 FTSMC020_BANK_MBW_32)
+
+#define FTSMC020_BANK0_TIMING	(FTSMC020_TPR_AST(3)   |	\
+				 FTSMC020_TPR_CTW(3)   |	\
+				 FTSMC020_TPR_ATI(0xf) |	\
+				 FTSMC020_TPR_AT2(3)   |	\
+				 FTSMC020_TPR_WTC(3)   |	\
+				 FTSMC020_TPR_AHT(3)   |	\
+				 FTSMC020_TPR_TRNA(0xf))
+
+#define FTSMC020_BANK1_CONFIG	(0x00)
+#define FTSMC020_BANK1_TIMING	(0x00)
+#endif /* CONFIG_FTSMC020 */
+
+/*
+ * FLASH and environment organization
+ */
+/* use CFI framework */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/* support JEDEC */
+
+/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
+#define PHYS_FLASH_1			0x80400000	/* BANK 1 */
+#else	/* !CONFIG_SKIP_LOWLEVEL_INIT */
+#ifdef CONFIG_MEM_REMAP
+#define PHYS_FLASH_1			0x80000000	/* BANK 0 */
+#else
+#define PHYS_FLASH_1			0x00000000	/* BANK 0 */
+#endif	/* CONFIG_MEM_REMAP */
+#endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
+
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ PHYS_FLASH_1, }
+#define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* TO for Flash Erase (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* TO for Flash Write (ms) */
+
+/* max number of memory banks */
+/*
+ * There are 4 banks supported for this Controller,
+ * but we have only 1 bank connected to flash on board
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+
+/* max number of sectors on one chip */
+#define CONFIG_FLASH_SECTOR_SIZE	(0x10000*2*2)
+#define CONFIG_ENV_SECT_SIZE		CONFIG_FLASH_SECTOR_SIZE
+#define CONFIG_SYS_MAX_FLASH_SECT	128
+
+/* environments */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_MONITOR_BASE + 0x140000)
+#define CONFIG_ENV_SIZE			8192
+#define CONFIG_ENV_OVERWRITE
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/adp-ag102.h b/qemu/roms/u-boot/include/configs/adp-ag102.h
new file mode 100644
index 000000000..39f7a3cd4
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/adp-ag102.h
@@ -0,0 +1,340 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/ag102.h>
+
+/*
+ * CPU and Board Configuration Options
+ */
+#define CONFIG_ADP_AG102
+
+#define CONFIG_USE_INTERRUPT
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_MEM_REMAP
+#endif
+
+#ifdef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_TEXT_BASE	0x04200000
+#else
+#define CONFIG_SYS_TEXT_BASE	0x00000000
+#endif
+
+/*
+ * Timer
+ */
+#define CONFIG_SYS_CLK_FREQ	(66000000 * 2)
+#define VERSION_CLOCK		CONFIG_SYS_CLK_FREQ
+
+/*
+ * Use Externel CLOCK or PCLK
+ */
+#undef CONFIG_FTRTC010_EXTCLK
+
+#ifndef CONFIG_FTRTC010_EXTCLK
+#define CONFIG_FTRTC010_PCLK
+#endif
+
+#ifdef CONFIG_FTRTC010_EXTCLK
+#define TIMER_CLOCK	32768			/* CONFIG_FTRTC010_EXTCLK */
+#else
+#define TIMER_CLOCK	CONFIG_SYS_HZ		/* CONFIG_FTRTC010_PCLK */
+#endif
+
+#define TIMER_LOAD_VAL	0xffffffff
+
+/*
+ * Real Time Clock
+ */
+#define CONFIG_RTC_FTRTC010
+
+/*
+ * Real Time Clock Divider
+ * RTC_DIV_COUNT			(OSC_CLK/OSC_5MHZ)
+ */
+#define OSC_5MHZ			(5*1000000)
+#define OSC_CLK				(2*OSC_5MHZ)
+#define RTC_DIV_COUNT			(OSC_CLK/OSC_5MHZ)
+
+/*
+ * Serial console configuration
+ */
+
+/* FTUART is a high speed NS 16C550A compatible UART */
+#define CONFIG_BAUDRATE			38400
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_COM1		CONFIG_FTUART010_01_BASE
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#define CONFIG_SYS_NS16550_CLK		33000000	/* AG102 */
+
+/*
+ * Ethernet
+ */
+#define CONFIG_NET_MULTI
+#define CONFIG_PHY_MAX_ADDR	32	/* this comes from <linux/phy.h> */
+#define CONFIG_SYS_DISCOVER_PHY
+#define CONFIG_FTGMAC100
+#define CONFIG_FTGMAC100_EGIGA
+
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * SD (MMC) controller
+ */
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FTSDC010
+#define CONFIG_FTSDC010_NUMBER		1
+#define CONFIG_FTSDC010_SDIO
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_ELF
+
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+
+/*
+ * PCI
+ */
+#define CONFIG_PCI
+#define CONFIG_FTPCI100
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_FTPCI100_MEM_BASE        0xa0000000
+#define CONFIG_FTPCI100_IO_SIZE         FTPCI100_BASE_IO_SIZE(256) /* 256M */
+#define CONFIG_FTPCI100_MEM_SIZE        FTPCI100_MEM_SIZE(128)  /* 128M */
+#define CONFIG_FTPCI100_MEM_BASE_SIZE1  0x50
+
+#define CONFIG_PCI_MEM_BUS	0xa0000000
+#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE	0x01000000		/* 256M */
+
+#define CONFIG_PCI_IO_BUS	0x90000000
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0x00100000		/* 1M */
+
+/*
+ * USB
+ */
+#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
+#if defined(CONFIG_FTPCI100)
+#define __io /* enable outl & inl */
+#define CONFIG_CMD_USB
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS      5
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI
+#define CONFIG_PCI_EHCI_DEVICE 0
+#define CONFIG_USB_EHCI_PCI
+#define CONFIG_PREBOOT                          "usb start;"
+#endif /* #if defiend(CONFIG_FTPCI100) */
+#endif /* #if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI) */
+
+/*
+ * IDE/ATA stuff
+ */
+#define __io
+#define CONFIG_IDE_AHB
+#define CONFIG_IDE_FTIDE020
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
+#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
+#define CONFIG_IDE_RESET	1	/* reset for ide supported	*/
+#define CONFIG_IDE_PREINIT	1	/* preinit for ide		*/
+
+/* max: 2 IDE busses */
+#define CONFIG_SYS_IDE_MAXBUS		1	/* origin: 2 */
+/* max: 2 drives per IDE bus */
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* origin: (MAXBUS * 2) */
+
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_FTIDE020S_BASE
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_IDE1_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* for data I/O */
+#define CONFIG_SYS_ATA_REG_OFFSET	0x0000	/* for normal regs access */
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0000	/* for alternate regs */
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SUPPORT_VFAT
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_PROMPT	"NDS32 # "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE	\
+	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS	16
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)
+
+/*
+ * AHB Controller configuration
+ */
+#define CONFIG_FTAHBC020S
+
+#ifdef CONFIG_FTAHBC020S
+#include <faraday/ftahbc020s.h>
+
+/* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
+#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE	0x100
+
+/*
+ * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
+ * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
+ * in C language.
+ */
+#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
+	(FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
+					 FTAHBC020S_SLAVE_BSR_SIZE(0xb))
+#endif
+
+/*
+ * Watchdog
+ */
+#define CONFIG_FTWDT010_WATCHDOG
+
+/*
+ * PCU Power Control Unit configuration
+ */
+#define CONFIG_ANDES_PCU
+
+#ifdef CONFIG_ANDES_PCU
+#include <andestech/andes_pcu.h>
+
+#endif
+
+/*
+ * DDR DRAM controller configuration
+ */
+#define CONFIG_DWCDDR21MCTL
+
+#ifdef CONFIG_DWCDDR21MCTL
+#include <synopsys/dwcddr21mctl.h>
+/* DCR:
+ *   2GB: 0x000025d2, 2GB (1Gb x8 2 ranks) Micron/innoDisk/Transcend
+ *   1GB: 0x000021d2, 1GB (1Gb x8 1 rank) Micron/Transcend/innoDisk
+ * 512MB: 0x000025cc, Micron 512MB (512Mb x16 2 ranks)
+ * 512MB: 0x000021ca, Trenscend/innoDisk 512MB (512Mb x8 1 rank)
+ * 256MB: 0x000020d4, Micron 256MB (1Gb x16 1 ranks)
+ */
+#define CONFIG_SYS_DWCDDR21MCTL_CCR	0x00020004
+#define CONFIG_SYS_DWCDDR21MCTL_CCR2	(DWCDDR21MCTL_CCR_DTT(0x1)	| \
+					DWCDDR21MCTL_CCR_DFTLM(0x4)	| \
+					DWCDDR21MCTL_CCR_HOSTEN(0x1))
+
+/* 0x04: 0x000020d4 */
+#define CONFIG_SYS_DWCDDR21MCTL_DCR	0x000020ca
+
+/* 0x08: 0x0000000f */
+#define CONFIG_SYS_DWCDDR21MCTL_IOCR	0x0000000f
+
+/* 0x10: 0x00034812 */
+#define CONFIG_SYS_DWCDDR21MCTL_DRR	(DWCDDR21MCTL_DRR_TRFC(0x12)	| \
+					DWCDDR21MCTL_DRR_TRFPRD(0x0348))
+/* 0x24 */
+#define CONFIG_SYS_DWCDDR21MCTL_DLLCR0	DWCDDR21MCTL_DLLCR_PHASE(0x0)
+
+/* 0x4c: 0x00000040 */
+#define CONFIG_SYS_DWCDDR21MCTL_RSLR0	0x00000040
+
+/* 0x5c: 0x000055CF */
+#define CONFIG_SYS_DWCDDR21MCTL_RDGR0	0x000055cf
+
+/* 0xa4: 0x00100000 */
+#define CONFIG_SYS_DWCDDR21MCTL_DTAR	(DWCDDR21MCTL_DTAR_DTBANK(0x0)	| \
+					DWCDDR21MCTL_DTAR_DTROW(0x0100)	| \
+					DWCDDR21MCTL_DTAR_DTCOL(0x0))
+/* 0x1f0: 0x00000852 */
+#define CONFIG_SYS_DWCDDR21MCTL_MR	(DWCDDR21MCTL_MR_WR(0x4)	| \
+					DWCDDR21MCTL_MR_CL(0x5)		| \
+					DWCDDR21MCTL_MR_BL(0x2))
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#if defined(CONFIG_MEM_REMAP) || defined(CONFIG_SKIP_LOWLEVEL_INIT)
+#define PHYS_SDRAM_0		0x00000000	/* SDRAM Bank #1 */
+#if defined(CONFIG_MEM_REMAP)
+#define PHYS_SDRAM_0_AT_INIT	0x80000000	/* SDRAM Bank #1 before remap*/
+#endif
+#else	/* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */
+#define PHYS_SDRAM_0		0x80000000	/* SDRAM Bank #1 */
+#endif
+
+#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
+#define PHYS_SDRAM_0_SIZE	0x10000000	/* 256 MB */
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_0
+
+#ifdef CONFIG_MEM_REMAP
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
+					GENERATED_GBL_DATA_SIZE)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 - \
+					GENERATED_GBL_DATA_SIZE)
+#endif /* CONFIG_MEM_REMAP */
+
+/*
+ * Load address and memory test area should agree with
+ * board/faraday/a320/config.mk
+ * Be careful not to overwrite U-boot itself.
+ */
+#define CONFIG_SYS_LOAD_ADDR		0x0CF00000
+
+/* memtest works on 63 MB in DRAM */
+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_0
+#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_0 + 0x03F00000)
+
+/*
+ * Static memory controller configuration
+ */
+
+/*
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * Env Storage Settings
+ */
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE			4096
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/aev.h b/qemu/roms/u-boot/include/configs/aev.h
new file mode 100644
index 000000000..2dffcfbed
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/aev.h
@@ -0,0 +1,390 @@
+/*
+ * (C) Copyright 2003-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004-2005
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5200		1	/* This is an MPC5200 CPU */
+#define CONFIG_TQM5200		1	/* ... on TQM5200 module */
+#undef CONFIG_TQM5200_REV100		/*  define for revision 100 modules */
+#define CONFIG_STK52XX		1	/* ... on a STK52XX base board */
+#define CONFIG_STK52XX_REV100	1	/*  define for revision 100 baseboards */
+#define CONFIG_AEVFIFO		1
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
+
+/*
+ * Valid values for CONFIG_SYS_TEXT_BASE are:
+ * 0xFC000000	boot low (standard configuration with room for
+ *		max 64 MByte Flash ROM)
+ * 0xFFF00000	boot high (for a backup copy of U-Boot)
+ * 0x00100000	boot from RAM (for testing only)
+ */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xFC000000
+#endif
+
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
+#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*
+ * PCI Mapping:
+ * 0x40000000 - 0x4fffffff - PCI Memory
+ * 0x50000000 - 0x50ffffff - PCI IO Space
+ */
+#ifdef CONFIG_AEVFIFO
+#define CONFIG_PCI		1
+#define CONFIG_PCI_PNP		1
+/* #define CONFIG_PCI_SCAN_SHOW	1 */
+#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE		1
+
+#define CONFIG_PCI_MEM_BUS	0x40000000
+#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE	0x10000000
+
+#define CONFIG_PCI_IO_BUS	0x50000000
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0x01000000
+
+#define CONFIG_EEPRO100		1
+#define CONFIG_SYS_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
+#define CONFIG_NS8382X		1
+#endif	/* CONFIG_AEVFIFO */
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+/* POST support */
+#define CONFIG_POST		(CONFIG_SYS_POST_MEMORY   | \
+				 CONFIG_SYS_POST_CPU	   | \
+				 CONFIG_SYS_POST_I2C)
+
+#ifdef CONFIG_POST
+/* preserve space for the post_word at end of on-chip SRAM */
+#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
+#endif
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SNTP
+
+#ifdef CONFIG_POST
+#define CONFIG_CMD_DIAG
+#endif
+
+
+#define	CONFIG_TIMESTAMP		/* display image timestamps */
+
+#if (CONFIG_SYS_TEXT_BASE == 0xFC000000)		/* Boot low */
+#   define CONFIG_SYS_LOWBOOT		1
+#endif
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT	"echo;" \
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"rootpath=/opt/eldk/ppc_6xx\0"					\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath} "			\
+		"console=ttyS0,${baudrate}\0"				\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"bootfile=/tftpboot/tqm5200/uImage\0"				\
+	"load=tftp 200000 ${u-boot}\0"					\
+	"u-boot=/tftpboot/tqm5200/u-boot.bin\0"				\
+	"update=protect off FC000000 FC05FFFF;"				\
+		"erase FC000000 FC05FFFF;"				\
+		"cp.b 200000 FC000000 ${filesize};"			\
+		"protect on FC000000 FC05FFFF\0"			\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run net_nfs"
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
+
+#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
+/*
+ * PCI Bus clocking configuration
+ *
+ * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
+ * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
+ * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
+ */
+#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2	/* define for 66MHz speed */
+#endif
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+#ifdef CONFIG_TQM5200_REV100
+#define CONFIG_SYS_I2C_MODULE		1	/* Select I2C module #1 for rev. 100 board */
+#else
+#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #2 for all other revs */
+#endif
+
+/*
+ * I2C clock frequency
+ *
+ * Please notice, that the resulting clock frequency could differ from the
+ * configured value. This is because the I2C clock is derived from system
+ * clock over a frequency divider with only a few divider values. U-boot
+ * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
+ * approximation allways lies below the configured value, never above.
+ */
+#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+
+/*
+ * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
+ * also). For other EEPROMs configuration should be verified. On Mini-FAP the
+ * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
+ * same configuration could be used.
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* =32 Bytes per write */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	20
+
+/*
+ * Flash configuration
+ */
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_TEXT_BASE /* 0xFC000000 */
+
+/* use CFI flash driver if no module variant is spezified */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_BOOTCS_START }
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_SIZE		0x04000000 /* 64 MByte */
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sects on one chip */
+#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE	/* not supported yet for AMD */
+
+#if !defined(CONFIG_SYS_LOWBOOT)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000)
+#else	/* CONFIG_SYS_LOWBOOT */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00060000)
+#endif	/* CONFIG_SYS_LOWBOOT */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks
+					   (= chip selects) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
+
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_SIZE		0x10000
+#define CONFIG_ENV_SECT_SIZE	0x20000
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define	CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+/*
+ * Memory map
+ */
+#define CONFIG_SYS_MBAR		0xF0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
+
+/* Use ON-Chip SRAM until RAM will be available */
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+#ifdef CONFIG_POST
+/* preserve space for the post_word at end of on-chip SRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_POST_SIZE
+#else
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
+#endif
+
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN		(384 << 10)	/* Reserve 384 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC	1
+#define CONFIG_MPC5xxx_FEC_MII100
+/*
+ * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
+ */
+/* #define CONFIG_MPC5xxx_FEC_MII10 */
+#define CONFIG_PHY_ADDR		0x00
+
+/*
+ * GPIO configuration
+ *
+ * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
+ *	Bit 0 (mask: 0x80000000): 1
+ * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
+ *	00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
+ *	01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
+ *	      Use for REV200 STK52XX boards. Do not use with REV100 modules
+ *	      (because, there I2C1 is used as I2C bus)
+ * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
+ * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
+ *	000 -> All PSC2 pins are GIOPs
+ *	001 -> CAN1/2 on PSC2 pins
+ *	       Use for REV100 STK52xx boards
+ * use PSC6:
+ *   on STK52xx:
+ *	use as UART. Pins PSC6_0 to PSC6_3 are used.
+ *	Bits 9:11 (mask: 0x00700000):
+ *	   101 -> PSC6 : Extended POST test is not available
+ *   on MINI-FAP and TQM5200_IB:
+ *	use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
+ *	   000 -> PSC6 could not be used as UART, CODEC or IrDA
+ *   GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
+ *   tests.
+ */
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x81500014
+
+/*
+ * RTC configuration
+ */
+#define CONFIG_RTC_MPC5200	1	/* use internal MPC5200 RTC */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+/* Enable an alternate, more extensive memory test */
+#define CONFIG_SYS_ALT_MEMTEST
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
+
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*
+ * Enable loopw command.
+ */
+#define CONFIG_LOOPW
+
+/*
+ * Various low-level settings
+ */
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
+
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
+#define CONFIG_SYS_BOOTCS_CFG		0x0008DF30 /* for pci_clk  = 66 MHz */
+#else
+#define CONFIG_SYS_BOOTCS_CFG		0x0004DF30 /* for pci_clk = 33 MHz */
+#endif
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
+
+#define CONFIG_LAST_STAGE_INIT
+
+/*
+ * SRAM - Do not map below 2 GB in address space, because this area is used
+ * for SDRAM autosizing.
+ */
+#define CONFIG_SYS_CS2_START		0xE5000000
+#define CONFIG_SYS_CS2_SIZE		0x80000		/* 512 kByte */
+#define CONFIG_SYS_CS2_CFG		0x0004D930
+
+/*
+ * Grafic controller - Do not map below 2 GB in address space, because this
+ * area is used for SDRAM autosizing.
+ */
+#define SM501_FB_BASE           0xE0000000
+#define CONFIG_SYS_CS1_START           (SM501_FB_BASE)
+#define CONFIG_SYS_CS1_SIZE            0x4000000       /* 64 MByte */
+#define CONFIG_SYS_CS1_CFG             0x8F48FF70
+#define SM501_MMIO_BASE         CONFIG_SYS_CS1_START + 0x03E00000
+
+#define CONFIG_SYS_CS_BURST            0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE        0x33333311      /* 1 dead cycle for flash and SM501 */
+
+#define CONFIG_SYS_RESET_ADDRESS	0xff000000
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/afeb9260.h b/qemu/roms/u-boot/include/configs/afeb9260.h
new file mode 100644
index 000000000..14bac155a
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/afeb9260.h
@@ -0,0 +1,157 @@
+/*
+ * (C) Copyright 2008 Sergey Lapin <slapin@ossfans.org>
+ *
+ * Configuation settings for the AFEB9260 board.
+ * Based on configuration for AT91SAM9260-EK
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+#define CONFIG_AT91SAM9260		/* Atmel AT91SAM9260 SoC*/
+#include <asm/arch/hardware.h>
+
+#define CONFIG_SYS_TEXT_BASE		0x21f00000
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_MAIN_CLOCK		18429952	/* from 18.432 MHz crystal */
+#define CONFIG_SYS_AT91_SLOW_CLOCK		32768
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_AFEB9260			/* AFEB9260 Board	*/
+#define CONFIG_ARCH_CPU_INIT
+
+#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG	1
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_ATMEL_LEGACY
+#define CONFIG_AT91_GPIO
+#define CONFIG_AT91_PULLUP	1
+
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE	ATMEL_BASE_DBGU
+#define CONFIG_USART_ID		ATMEL_ID_SYS
+#define CONFIG_USART3		/* USART 3 is DBGU */
+
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE	1
+#define CONFIG_BOOTP_BOOTPATH		1
+#define CONFIG_BOOTP_GATEWAY		1
+#define CONFIG_BOOTP_HOSTNAME		1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_SOURCE
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_USB
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
+#define CONFIG_SYS_SDRAM_SIZE		0x04000000	/* 64 megs */
+
+/* DataFlash */
+#define CONFIG_ATMEL_DATAFLASH_SPI
+#define CONFIG_HAS_DATAFLASH
+#define CONFIG_SYS_SPI_WRITE_TOUT		(5 * CONFIG_SYS_HZ)
+#define CONFIG_SYS_MAX_DATAFLASH_BANKS		2
+#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
+#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1	0xD0000000	/* CS1 */
+#define AT91_SPI_CLK			15000000
+#define DATAFLASH_TCSS			(0x1a << 16)
+#define DATAFLASH_TCHS			(0x1 << 24)
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE		1
+#define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3
+#define CONFIG_SYS_NAND_DBW_8
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PC14
+#define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PC13
+
+#endif
+
+/* NOR flash - no real flash on this board */
+#define CONFIG_SYS_NO_FLASH
+
+/* Ethernet */
+#define CONFIG_MACB
+#define CONFIG_RESET_PHY_R
+#define CONFIG_AT91_WANTS_COMMON_PHY
+#define CONFIG_NET_RETRY_COUNT		20
+
+/* USB */
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00500000	/* AT91SAM9260_UHP_BASE */
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9260"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	1
+#define CONFIG_USB_STORAGE
+
+#define CONFIG_SYS_LOAD_ADDR			0x21000000	/* load address */
+
+#define CONFIG_SYS_MEMTEST_START		CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END			0x21e00000
+
+#define CONFIG_SYS_USE_DATAFLASH_CS1
+#define CONFIG_SYS_INIT_SP_ADDR		(ATMEL_BASE_SRAM1 + 0x1000 -\
+					GENERATED_GBL_DATA_SIZE)
+
+/* bootstrap + u-boot + env + linux in dataflash on CS1 */
+#define CONFIG_ENV_IS_IN_DATAFLASH
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 + 0x8400)
+#define CONFIG_ENV_OFFSET		0x4200
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SIZE		0x4200
+#define CONFIG_BOOTCOMMAND	"nand read 0x21000000 0xa0000 0x200000; bootm"
+#define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
+				"root=/dev/mtdblock2 "			\
+				"rw rootfstype=jffs2 panic=20"
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_SYS_PROMPT		"U-Boot> "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/alpr.h b/qemu/roms/u-boot/include/configs/alpr.h
new file mode 100644
index 000000000..7849b222b
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/alpr.h
@@ -0,0 +1,357 @@
+/*
+ * (C) Copyright 2006-2008
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_ALPR		1	    /* Board is ebony		*/
+#define CONFIG_440GX		1	    /* Specifc GX support	*/
+#define CONFIG_440		1	    /* ... PPC440 family	*/
+#define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_pre_init	*/
+#define CONFIG_LAST_STAGE_INIT	1	    /* call last_stage_init()	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
+
+#define CONFIG_SYS_CLK_FREQ	33333333    /* external freq to pll	*/
+#define CONFIG_4xx_DCACHE		/* Enable i- and d-cache	*/
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000	/* _must_ be 0			*/
+#define CONFIG_SYS_FLASH_BASE		0xffe00000	/* start of FLASH		*/
+#define CONFIG_SYS_MONITOR_BASE	0xfffc0000	/* start of monitor		*/
+#define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped pci memory		*/
+#define	CONFIG_SYS_PCI_MEMSIZE		0x40000000	/* size of mapped pci memory	*/
+#define CONFIG_SYS_ISRAM_BASE		0xc0000000	/* internal SRAM		*/
+#define CONFIG_SYS_PCI_BASE		0xd0000000	/* internal PCI regs		*/
+#define CONFIG_SYS_PCI_MEMBASE1	CONFIG_SYS_PCI_MEMBASE  + 0x10000000
+#define CONFIG_SYS_PCI_MEMBASE2	CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
+#define CONFIG_SYS_PCI_MEMBASE3	CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
+
+
+#define CONFIG_SYS_FPGA_BASE	    (CONFIG_SYS_PERIPHERAL_BASE + 0x08300000)
+#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in internal SRAM)
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_TEMP_STACK_OCM  1
+#define CONFIG_SYS_OCM_DATA_ADDR   CONFIG_SYS_ISRAM_BASE
+#define CONFIG_SYS_INIT_RAM_ADDR   CONFIG_SYS_ISRAM_BASE  /* Initial RAM address	*/
+#define CONFIG_SYS_INIT_RAM_SIZE    0x2000	    /* Size of used area in RAM	*/
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
+
+#define CONFIG_SYS_MONITOR_LEN	    (256 * 1024)    /* Reserve 256 kB for Mon	*/
+#define CONFIG_SYS_MALLOC_LEN	    (128 * 1024)    /* Reserve 128 kB for malloc*/
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#define CONFIG_CONS_INDEX	2	/* Use UART1			*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_FLASH_CFI		1	/* The flash is CFI compatible		*/
+#define CONFIG_FLASH_CFI_DRIVER	1	/* Use common CFI driver		*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash	*/
+
+#define CONFIG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
+
+#define CONFIG_ENV_SECT_SIZE	0x10000	/* size of one complete sector		*/
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
+#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#undef CONFIG_SPD_EEPROM		/* Don't use SPD EEPROM for setup	*/
+#define CONFIG_SDRAM_BANK0	1	/* init onboard DDR SDRAM bank 0	*/
+#undef CONFIG_SDRAM_ECC			/* enable ECC support			*/
+#define CONFIG_SYS_SDRAM_TABLE	{ \
+		{(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \
+		{(64 << 20),  12, 0x00082001}} /* 64MB mode 2, 12x9(4)	*/
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		100000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
+#define CONFIG_SYS_I2C_NOPROBES	{ {0, 0x69} }	/* Don't probe these addrs */
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (PCF8594C)
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x54	/* EEPROM PCF8594C		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3	/* The Philips PCF8594C has	*/
+					/* 8 byte page write mode using */
+					/* last 3 bits of the address	*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	40   /* and takes up to 40 msec */
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run kernelx\" to boot the system;"			\
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth3\0"							\
+	"hostname=alpr\0"						\
+	"fdt_file=alpr/alpr.dtb\0"					\
+	"fdt_addr=400000\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath} ${init}\0"		\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate} " \
+		"mem=193M\0"						\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
+		"bootm\0"						\
+	"net_nfs_fdt=tftp 200000 ${bootfile};"				\
+		"tftp ${fdt_addr} ${fdt_file};"				\
+		"run nfsargs addip addtty;"				\
+		"bootm 200000 - ${fdt_addr}\0"				\
+	"rootpath=/opt/projects/alpr/nfs_root\0"			\
+	"bootfile=/alpr/uImage\0"					\
+	"kernel_addr=fff00000\0"					\
+	"ramdisk_addr=fff10000\0"					\
+	"load=tftp 100000 /alpr/u-boot/u-boot.bin\0"			\
+	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"	\
+		"cp.b 100000 fffc0000 40000;"			        \
+		"setenv filesize;saveenv\0"				\
+	"upd=run load update\0"						\
+	"ethprime=ppc_4xx_eth3\0"					\
+	"ethact=ppc_4xx_eth3\0"						\
+	"autoload=no\0"							\
+	"ipconfig=dhcp;setenv serverip 11.0.0.152\0"			\
+	"load_fpga=fpga load 0 ffe00000 10dd9a\0"			\
+	"mtdargs=setenv bootargs root=/dev/mtdblock6 rw "		\
+		"rootfstype=jffs2 init=/sbin/init\0"			\
+	"kernel1_mtd=nand read 200000 0 200000;run mtdargs addip addtty"\
+		";bootm 200000\0"					\
+	"kernel2_mtd=nand read 200000 200000 200000;run mtdargs addip "	\
+		"addtty;bootm 200000\0"					\
+	"kernel1=setenv actkernel 'kernel1';run load_fpga "		\
+		"kernel1_mtd\0"						\
+	"kernel2=setenv actkernel 'kernel2';run load_fpga "		\
+		"kernel2_mtd\0"						\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run kernel2"
+
+#define CONFIG_BOOTDELAY	2	/* autoboot after 5 seconds	*/
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_PPC4xx_EMAC
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0x02	/* dummy setting, no EMAC0 used	*/
+#define CONFIG_PHY1_ADDR	0x03	/* dummy setting, no EMAC1 used	*/
+#define CONFIG_PHY2_ADDR	0x01	/* PHY address for EMAC2	*/
+#define CONFIG_PHY3_ADDR	0x02	/* PHY address for EMAC3	*/
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+#define CONFIG_HAS_ETH3
+#define CONFIG_PHY_RESET	1	/* reset phy upon startup	*/
+#define CONFIG_M88E1111_PHY	1	/* needed for PHY specific setup*/
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+#define CONFIG_SYS_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_FPGA
+#define CONFIG_CMD_I2C
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_ALT_MEMTEST		1	/* Enable more extensive memtest*/
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_LOOPW            1       /* enable loopw command         */
+#define CONFIG_MX_CYCLIC	1       /* enable mdc/mwc commands      */
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE	1	/* include version env variable */
+
+#define CONFIG_SYS_4xx_RESET_TYPE	0x2	/* use chip reset on this board	*/
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+/* General PCI */
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
+#define CONFIG_SYS_PCI_TARGBASE    0x80000000	/* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
+#define CONFIG_PCI_BOOTDELAY	1       /* enable pci bootdelay variable*/
+
+/* Board-specific PCI */
+#define CONFIG_SYS_PCI_TARGET_INIT		/* let board init pci target    */
+#define CONFIG_SYS_PCI_MASTER_INIT
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
+
+/*-----------------------------------------------------------------------
+ * FPGA stuff
+ *-----------------------------------------------------------------------*/
+#define CONFIG_FPGA
+#define CONFIG_FPGA_ALTERA
+#define CONFIG_FPGA_CYCLON2
+#define CONFIG_SYS_FPGA_CHECK_CTRLC
+#define CONFIG_SYS_FPGA_PROG_FEEDBACK
+#define CONFIG_FPGA_COUNT       1		/* Ich habe 2 ... aber in
+					Reihe geschaltet -> sollte gehen,
+					aufpassen mit Datasize ist jetzt
+					halt doppelt so gross ... Seite 306
+					ist das mit den multiple Device in PS
+					Mode erklaert ...*/
+
+/* FPGA program pin configuration */
+#define CONFIG_SYS_GPIO_CLK		18	/* FPGA clk pin (cpu output)		*/
+#define CONFIG_SYS_GPIO_DATA		19	/* FPGA data pin (cpu output)		*/
+#define CONFIG_SYS_GPIO_STATUS		20	/* FPGA status pin (cpu input)		*/
+#define CONFIG_SYS_GPIO_CONFIG		21	/* FPGA CONFIG pin (cpu output)		*/
+#define CONFIG_SYS_GPIO_CON_DON	22	/* FPGA CONFIG_DONE pin (cpu input)	*/
+
+#define CONFIG_SYS_GPIO_SEL_DPR	14	/* cpu output */
+#define CONFIG_SYS_GPIO_SEL_AVR	15	/* cpu output */
+#define CONFIG_SYS_GPIO_PROG_EN	23	/* cpu output */
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO setup
+ *-----------------------------------------------------------------------*/
+#define CONFIG_SYS_GPIO_SHUTDOWN	(0x80000000 >> 6)
+#define CONFIG_SYS_GPIO_SSD_EMPTY	(0x80000000 >> 9)
+#define CONFIG_SYS_GPIO_EREADY		(0x80000000 >> 26)
+#define CONFIG_SYS_GPIO_REV0		(0x80000000 >> 14)
+#define CONFIG_SYS_GPIO_REV1		(0x80000000 >> 15)
+
+/*-----------------------------------------------------------------------
+ * NAND-FLASH stuff
+ *-----------------------------------------------------------------------*/
+#define CONFIG_SYS_MAX_NAND_DEVICE	4
+#define CONFIG_SYS_NAND_BASE		0xF0000000	/* NAND FLASH Base Address	*/
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE + 0, CONFIG_SYS_NAND_BASE + 2,	\
+				  CONFIG_SYS_NAND_BASE + 4, CONFIG_SYS_NAND_BASE + 6 }
+#define CONFIG_SYS_NAND_QUIET_TEST	1	/* don't warn upon unknown NAND flash	*/
+#define CONFIG_SYS_NAND_MAX_OOBFREE	2
+#define CONFIG_SYS_NAND_MAX_ECCPOS	56
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_FLASH		CONFIG_SYS_FLASH_BASE
+
+/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
+#define CONFIG_SYS_EBC_PB0AP		0x92015480
+#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_FLASH | 0x3A000) /* BS=2MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (NAND-FLASH) initialization					*/
+#define CONFIG_SYS_EBC_PB1AP		0x01840380	/* TWT=3			*/
+#define CONFIG_SYS_EBC_PB1CR		(CONFIG_SYS_NAND_BASE | 0x18000) /* BS=1MB,BU=R/W,BW=8bit */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/am335x_evm.h b/qemu/roms/u-boot/include/configs/am335x_evm.h
new file mode 100644
index 000000000..762f6d2e4
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/am335x_evm.h
@@ -0,0 +1,457 @@
+/*
+ * am335x_evm.h
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __CONFIG_AM335X_EVM_H
+#define __CONFIG_AM335X_EVM_H
+
+#include <configs/ti_am335x_common.h>
+
+#define MACH_TYPE_TIAM335EVM		3589	/* Until the next sync */
+#define CONFIG_MACH_TYPE		MACH_TYPE_TIAM335EVM
+#define CONFIG_BOARD_LATE_INIT
+
+/* Clock Defines */
+#define V_OSCK				24000000  /* Clock output from T2 */
+#define V_SCLK				(V_OSCK)
+
+/* Custom script for NOR */
+#define CONFIG_SYS_LDSCRIPT		"board/ti/am335x/u-boot.lds"
+
+/* Always 128 KiB env size */
+#define CONFIG_ENV_SIZE			(128 << 10)
+
+/* Enhance our eMMC support / experience. */
+#define CONFIG_CMD_GPT
+#define CONFIG_EFI_PARTITION
+#define CONFIG_PARTITION_UUIDS
+#define CONFIG_CMD_PART
+
+#ifdef CONFIG_NAND
+#define NANDARGS \
+	"mtdids=" MTDIDS_DEFAULT "\0" \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${nandroot} " \
+		"rootfstype=${nandrootfstype}\0" \
+	"nandroot=ubi0:rootfs rw ubi.mtd=7,2048\0" \
+	"nandrootfstype=ubifs rootwait=1\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nand read ${fdtaddr} u-boot-spl-os; " \
+		"nand read ${loadaddr} kernel; " \
+		"bootz ${loadaddr} - ${fdtaddr}\0"
+#else
+#define NANDARGS ""
+#endif
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	DEFAULT_LINUX_BOOT_ENV \
+	"boot_fdt=try\0" \
+	"bootpart=0:2\0" \
+	"bootdir=/boot\0" \
+	"bootfile=zImage\0" \
+	"fdtfile=undefined\0" \
+	"console=ttyO0,115200n8\0" \
+	"partitions=" \
+		"uuid_disk=${uuid_gpt_disk};" \
+		"name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \
+	"optargs=\0" \
+	"mmcdev=0\0" \
+	"mmcroot=/dev/mmcblk0p2 ro\0" \
+	"mmcrootfstype=ext4 rootwait\0" \
+	"rootpath=/export/rootfs\0" \
+	"nfsopts=nolock\0" \
+	"static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \
+		"::off\0" \
+	"ramroot=/dev/ram0 rw\0" \
+	"ramrootfstype=ext2\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0" \
+	"spiroot=/dev/mtdblock4 rw\0" \
+	"spirootfstype=jffs2\0" \
+	"spisrcaddr=0xe0000\0" \
+	"spiimgsize=0x362000\0" \
+	"spibusno=0\0" \
+	"spiargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${spiroot} " \
+		"rootfstype=${spirootfstype}\0" \
+	"netargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=/dev/nfs " \
+		"nfsroot=${serverip}:${rootpath},${nfsopts} rw " \
+		"ip=dhcp\0" \
+	"bootenv=uEnv.txt\0" \
+	"loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
+	"importbootenv=echo Importing environment from mmc ...; " \
+		"env import -t $loadaddr $filesize\0" \
+	"ramargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${ramroot} " \
+		"rootfstype=${ramrootfstype}\0" \
+	"loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
+	"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
+	"loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
+	"mmcloados=run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdtaddr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"mmcboot=mmc dev ${mmcdev}; " \
+		"if mmc rescan; then " \
+			"echo SD/MMC found on device ${mmcdev};" \
+			"if run loadbootenv; then " \
+				"echo Loaded environment from ${bootenv};" \
+				"run importbootenv;" \
+			"fi;" \
+			"if test -n $uenvcmd; then " \
+				"echo Running uenvcmd ...;" \
+				"run uenvcmd;" \
+			"fi;" \
+			"if run loadimage; then " \
+				"run mmcloados;" \
+			"fi;" \
+		"fi;\0" \
+	"spiboot=echo Booting from spi ...; " \
+		"run spiargs; " \
+		"sf probe ${spibusno}:0; " \
+		"sf read ${loadaddr} ${spisrcaddr} ${spiimgsize}; " \
+		"bootz ${loadaddr}\0" \
+	"netboot=echo Booting from network ...; " \
+		"setenv autoload no; " \
+		"dhcp; " \
+		"tftp ${loadaddr} ${bootfile}; " \
+		"tftp ${fdtaddr} ${fdtfile}; " \
+		"run netargs; " \
+		"bootz ${loadaddr} - ${fdtaddr}\0" \
+	"ramboot=echo Booting from ramdisk ...; " \
+		"run ramargs; " \
+		"bootz ${loadaddr} ${rdaddr} ${fdtaddr}\0" \
+	"findfdt="\
+		"if test $board_name = A335BONE; then " \
+			"setenv fdtfile am335x-bone.dtb; fi; " \
+		"if test $board_name = A335BNLT; then " \
+			"setenv fdtfile am335x-boneblack.dtb; fi; " \
+		"if test $board_name = A33515BB; then " \
+			"setenv fdtfile am335x-evm.dtb; fi; " \
+		"if test $board_name = A335X_SK; then " \
+			"setenv fdtfile am335x-evmsk.dtb; fi; " \
+		"if test $fdtfile = undefined; then " \
+			"echo WARNING: Could not determine device tree to use; fi; \0" \
+	NANDARGS \
+	DFUARGS
+#endif
+
+#define CONFIG_BOOTCOMMAND \
+	"run findfdt; " \
+	"run mmcboot;" \
+	"setenv mmcdev 1; " \
+	"setenv bootpart 1:2; " \
+	"run mmcboot;" \
+	"run nandboot;"
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550_COM1		0x44e09000	/* Base EVM has UART0 */
+#define CONFIG_SYS_NS16550_COM2		0x48022000	/* UART1 */
+#define CONFIG_SYS_NS16550_COM3		0x48024000	/* UART2 */
+#define CONFIG_SYS_NS16550_COM4		0x481a6000	/* UART3 */
+#define CONFIG_SYS_NS16550_COM5		0x481a8000	/* UART4 */
+#define CONFIG_SYS_NS16550_COM6		0x481aa000	/* UART5 */
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_CMD_EEPROM
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* Main EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+
+/* PMIC support */
+#define CONFIG_POWER_TPS65217
+#define CONFIG_POWER_TPS65910
+
+/* SPL */
+#ifndef CONFIG_NOR_BOOT
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_YMODEM_SUPPORT
+
+/* Bootcount using the RTC block */
+#define CONFIG_BOOTCOUNT_LIMIT
+#define CONFIG_BOOTCOUNT_AM33XX
+
+/* USB gadget RNDIS */
+#define CONFIG_SPL_MUSB_NEW_SUPPORT
+
+/* General network SPL, both CPSW and USB gadget RNDIS */
+#define CONFIG_SPL_NET_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_NET_VCI_STRING	"AM335x U-Boot SPL"
+
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/am33xx/u-boot-spl.lds"
+
+#ifdef CONFIG_NAND
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_NAND_OMAP_ELM
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
+					 CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
+					 10, 11, 12, 13, 14, 15, 16, 17, \
+					 18, 19, 20, 21, 22, 23, 24, 25, \
+					 26, 27, 28, 29, 30, 31, 32, 33, \
+					 34, 35, 36, 37, 38, 39, 40, 41, \
+					 42, 43, 44, 45, 46, 47, 48, 49, \
+					 50, 51, 52, 53, 54, 55, 56, 57, }
+
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	14
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+#endif
+#endif
+
+/*
+ * For NOR boot, we must set this to the start of where NOR is mapped
+ * in memory.
+ */
+#ifdef CONFIG_NOR_BOOT
+#define CONFIG_SYS_TEXT_BASE		0x08000000
+#endif
+
+/*
+ * USB configuration.  We enable MUSB support, both for host and for
+ * gadget.  We set USB0 as peripheral and USB1 as host, based on the
+ * board schematic and physical port wired to each.  Then for host we
+ * add mass storage support and for gadget we add both RNDIS ethernet
+ * and DFU.
+ */
+#define CONFIG_USB_MUSB_DSPS
+#define CONFIG_ARCH_MISC_INIT
+#define CONFIG_MUSB_GADGET
+#define CONFIG_MUSB_PIO_ONLY
+#define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT
+#define CONFIG_USB_GADGET
+#define CONFIG_USBDOWNLOAD_GADGET
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_VBUS_DRAW	2
+#define CONFIG_MUSB_HOST
+#define CONFIG_AM335X_USB0
+#define CONFIG_AM335X_USB0_MODE	MUSB_PERIPHERAL
+#define CONFIG_AM335X_USB1
+#define CONFIG_AM335X_USB1_MODE MUSB_HOST
+
+#ifdef CONFIG_MUSB_HOST
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#endif
+
+#ifdef CONFIG_MUSB_GADGET
+#define CONFIG_USB_ETHER
+#define CONFIG_USB_ETH_RNDIS
+#define CONFIG_USBNET_HOST_ADDR	"de:ad:be:af:00:00"
+
+/* USB TI's IDs */
+#define CONFIG_G_DNL_VENDOR_NUM 0x0403
+#define CONFIG_G_DNL_PRODUCT_NUM 0xBD00
+#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
+#endif /* CONFIG_MUSB_GADGET */
+
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT)
+/* disable host part of MUSB in SPL */
+#undef CONFIG_MUSB_HOST
+/* disable EFI partitions and partition UUID support */
+#undef CONFIG_PARTITION_UUIDS
+#undef CONFIG_EFI_PARTITION
+/*
+ * Disable CPSW SPL support so we fit within the 101KiB limit.
+ */
+#undef CONFIG_SPL_ETH_SUPPORT
+#endif
+
+/* USB Device Firmware Update support */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_DFU_FUNCTION
+#define CONFIG_DFU_MMC
+#define CONFIG_CMD_DFU
+#define DFU_ALT_INFO_MMC \
+	"dfu_alt_info_mmc=" \
+	"boot part 0 1;" \
+	"rootfs part 0 2;" \
+	"MLO fat 0 1;" \
+	"MLO.raw mmc 0x100 0x100;" \
+	"u-boot.img.raw mmc 0x300 0x400;" \
+	"spl-os-args.raw mmc 0x80 0x80;" \
+	"spl-os-image.raw mmc 0x900 0x2000;" \
+	"spl-os-args fat 0 1;" \
+	"spl-os-image fat 0 1;" \
+	"u-boot.img fat 0 1;" \
+	"uEnv.txt fat 0 1\0"
+#ifdef CONFIG_NAND
+#define CONFIG_DFU_NAND
+#define DFU_ALT_INFO_NAND \
+	"dfu_alt_info_nand=" \
+	"SPL part 0 1;" \
+	"SPL.backup1 part 0 2;" \
+	"SPL.backup2 part 0 3;" \
+	"SPL.backup3 part 0 4;" \
+	"u-boot part 0 5;" \
+	"u-boot-spl-os part 0 6;" \
+	"kernel part 0 8;" \
+	"rootfs part 0 9\0"
+#else
+#define DFU_ALT_INFO_NAND ""
+#endif
+#define CONFIG_DFU_RAM
+#define DFU_ALT_INFO_RAM \
+	"dfu_alt_info_ram=" \
+	"kernel ram 0x80200000 0xD80000;" \
+	"fdt ram 0x80F80000 0x80000;" \
+	"ramdisk ram 0x81000000 0x4000000\0"
+#define DFUARGS \
+	"dfu_alt_info_emmc=rawemmc mmc 0 3751936\0" \
+	DFU_ALT_INFO_MMC \
+	DFU_ALT_INFO_RAM \
+	DFU_ALT_INFO_NAND
+#endif
+
+/*
+ * Default to using SPI for environment, etc.
+ * 0x000000 - 0x020000 : SPL (128KiB)
+ * 0x020000 - 0x0A0000 : U-Boot (512KiB)
+ * 0x0A0000 - 0x0BFFFF : First copy of U-Boot Environment (128KiB)
+ * 0x0C0000 - 0x0DFFFF : Second copy of U-Boot Environment (128KiB)
+ * 0x0E0000 - 0x442000 : Linux Kernel
+ * 0x442000 - 0x800000 : Userland
+ */
+#if defined(CONFIG_SPI_BOOT)
+/* SPL related */
+#undef CONFIG_SPL_OS_BOOT		/* Not supported by existing map */
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_BUS		0
+#define CONFIG_SPL_SPI_CS		0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x20000
+
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
+#define CONFIG_ENV_SECT_SIZE		(4 << 10) /* 4 KB sectors */
+#define CONFIG_ENV_OFFSET		(768 << 10) /* 768 KiB in */
+#define CONFIG_ENV_OFFSET_REDUND	(896 << 10) /* 896 KiB in */
+#define MTDIDS_DEFAULT			"nor0=m25p80-flash.0"
+#define MTDPARTS_DEFAULT		"mtdparts=m25p80-flash.0:128k(SPL)," \
+					"512k(u-boot),128k(u-boot-env1)," \
+					"128k(u-boot-env2),3464k(kernel)," \
+					"-(rootfs)"
+#elif defined(CONFIG_EMMC_BOOT)
+#undef CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV		1
+#define CONFIG_SYS_MMC_ENV_PART		2
+#define CONFIG_ENV_OFFSET		0x0
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#endif
+
+/* SPI flash. */
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SF_DEFAULT_SPEED		24000000
+
+/* Network. */
+#define CONFIG_PHY_GIGE
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_SMSC
+
+/* NAND support */
+#ifdef CONFIG_NAND
+#define CONFIG_CMD_NAND
+#if !defined(CONFIG_SPI_BOOT) && !defined(CONFIG_NOR_BOOT)
+#define MTDIDS_DEFAULT			"nand0=omap2-nand.0"
+#define MTDPARTS_DEFAULT		"mtdparts=omap2-nand.0:128k(SPL)," \
+					"128k(SPL.backup1)," \
+					"128k(SPL.backup2)," \
+					"128k(SPL.backup3),1792k(u-boot)," \
+					"128k(u-boot-spl-os)," \
+					"128k(u-boot-env),5m(kernel),-(rootfs)"
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		0x260000 /* environment starts here */
+#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
+#endif
+#endif
+
+/*
+ * NOR Size = 16 MiB
+ * Number of Sectors/Blocks = 128
+ * Sector Size = 128 KiB
+ * Word length = 16 bits
+ * Default layout:
+ * 0x000000 - 0x07FFFF : U-Boot (512 KiB)
+ * 0x080000 - 0x09FFFF : First copy of U-Boot Environment (128 KiB)
+ * 0x0A0000 - 0x0BFFFF : Second copy of U-Boot Environment (128 KiB)
+ * 0x0C0000 - 0x4BFFFF : Linux Kernel (4 MiB)
+ * 0x4C0000 - 0xFFFFFF : Userland (11 MiB + 256 KiB)
+ */
+#if defined(CONFIG_NOR)
+#undef CONFIG_SYS_NO_FLASH
+#define CONFIG_CMD_FLASH
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_MTD
+#define CONFIG_SYS_MAX_FLASH_SECT	128
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_FLASH_BASE		(0x08000000)
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+/* Reduce SPL size by removing unlikey targets */
+#ifdef CONFIG_NOR_BOOT
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE		(128 << 10)	/* 128 KiB */
+#define CONFIG_ENV_OFFSET		(512 << 10)	/* 512 KiB */
+#define CONFIG_ENV_OFFSET_REDUND	(768 << 10)	/* 768 KiB */
+#define MTDIDS_DEFAULT			"nor0=physmap-flash.0"
+#define MTDPARTS_DEFAULT		"mtdparts=physmap-flash.0:" \
+					"512k(u-boot)," \
+					"128k(u-boot-env1)," \
+					"128k(u-boot-env2)," \
+					"4m(kernel),-(rootfs)"
+#endif
+#endif  /* NOR support */
+
+#endif	/* ! __CONFIG_AM335X_EVM_H */
diff --git a/qemu/roms/u-boot/include/configs/am335x_igep0033.h b/qemu/roms/u-boot/include/configs/am335x_igep0033.h
new file mode 100644
index 000000000..c17327fef
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/am335x_igep0033.h
@@ -0,0 +1,289 @@
+/*
+ * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __CONFIG_IGEP0033_H
+#define __CONFIG_IGEP0033_H
+
+#define CONFIG_AM33XX
+#define CONFIG_OMAP
+#define CONFIG_OMAP_COMMON
+
+#include <asm/arch/omap.h>
+
+/* Mach type */
+#define MACH_TYPE_IGEP0033		4521	/* Until the next sync */
+#define CONFIG_MACH_TYPE		MACH_TYPE_IGEP0033
+
+/* Clock defines */
+#define V_OSCK				24000000  /* Clock output from T2 */
+#define V_SCLK				(V_OSCK)
+
+#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
+#define CONFIG_SYS_MALLOC_LEN		(1024 << 10)
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT		"U-Boot# "
+#define CONFIG_SYS_NO_FLASH
+
+/* Display cpuinfo */
+#define CONFIG_DISPLAY_CPUINFO
+
+/* Flattened Device Tree */
+#define CONFIG_OF_LIBFDT
+
+/* Commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+
+/* Make the verbose messages from UBI stop printing */
+#define CONFIG_UBI_SILENCE_MSG
+#define CONFIG_UBIFS_SILENCE_MSG
+
+#define CONFIG_BOOTDELAY		1	/* negative for no autoboot */
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x80F80000\0" \
+	"dtbaddr=0x80200000\0" \
+	"bootdir=/boot\0" \
+	"bootfile=zImage\0" \
+	"dtbfile=am335x-base0033.dtb\0" \
+	"console=ttyO0,115200n8\0" \
+	"mtdids=" MTDIDS_DEFAULT "\0" \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"mmcdev=0\0" \
+	"mmcroot=/dev/mmcblk0p2 rw\0" \
+	"ubiroot=ubi0:filesystem rw ubi.mtd=3,2048\0" \
+	"mmcrootfstype=ext4 rootwait\0" \
+	"ubirootfstype=ubifs rootwait\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0" \
+	"ubiargs=setenv bootargs console=${console} " \
+		"root=${ubiroot} " \
+		"rootfstype=${ubirootfstype}\0" \
+	"bootenv=uEnv.txt\0" \
+	"loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
+	"importbootenv=echo Importing environment from mmc ...; " \
+		"env import -t ${loadaddr} ${filesize}\0" \
+	"mmcload=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}; " \
+		"load mmc ${mmcdev}:2 ${dtbaddr} ${bootdir}/${dtbfile}\0" \
+	"ubiload=ubi part filesystem 2048; ubifsmount ubi0; " \
+		"ubifsload ${loadaddr} ${bootdir}/${bootfile}; " \
+		"ubifsload ${dtbaddr} ${bootdir}/${dtbfile} \0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootz ${loadaddr} - ${dtbaddr}\0" \
+	"ubiboot=echo Booting from nand (ubifs) ...; " \
+		"run ubiargs; run ubiload; " \
+		"bootz ${loadaddr} - ${dtbaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"echo SD/MMC found on device ${mmcdev};" \
+		"if run loadbootenv; then " \
+			"echo Loaded environment from ${bootenv};" \
+			"run importbootenv;" \
+		"fi;" \
+		"if test -n $uenvcmd; then " \
+			"echo Running uenvcmd ...;" \
+			"run uenvcmd;" \
+		"fi;" \
+		"if run mmcload; then " \
+			"run mmcboot;" \
+		"fi;" \
+	"else " \
+		"run ubiboot;" \
+	"fi;" \
+
+/* Max number of command args */
+#define CONFIG_SYS_MAXARGS		16
+
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		512
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE \
+					+ sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_LOAD_ADDR		0x81000000 /* Default load address */
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS		1		/*  1 bank of DRAM */
+#define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 20)	/* 1GB */
+
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CONFIG_SYS_INIT_SP_ADDR         (NON_SECURE_SRAM_END - \
+						GENERATED_GBL_DATA_SIZE)
+/* Platform/Board specific defs */
+#define CONFIG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
+#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		(48000000)
+#define CONFIG_SYS_NS16550_COM1		0x44e09000	/* UART0 */
+
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+
+/* CPU */
+#define CONFIG_ARCH_CPU_INIT
+
+#define CONFIG_ENV_OVERWRITE		1
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+
+/* MMC support */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_DOS_PARTITION
+
+/* GPIO support */
+#define CONFIG_OMAP_GPIO
+
+/* Ethernet support */
+#define CONFIG_DRIVER_TI_CPSW
+#define CONFIG_MII
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_NET_RETRY_COUNT         10
+#define CONFIG_NET_MULTI
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_SMSC
+
+/* NAND support */
+#define CONFIG_NAND
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_NAND_OMAP_ELM
+#define CONFIG_SYS_NAND_BASE		(0x08000000)	/* phys address CS0 */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_ONFI_DETECTION	1
+#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		0x180000 /* environment starts here */
+#define CONFIG_ENV_ADDR_REDUND		(CONFIG_ENV_OFFSET + CONFIG_SYS_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND		(CONFIG_ENV_SIZE)
+
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+
+#define MTDIDS_DEFAULT			"nand0=omap2-nand.0"
+#define MTDPARTS_DEFAULT		"mtdparts=omap2-nand.0:512k(spl),"\
+					"1m(uboot),256k(environment),"\
+					"-(filesystem)"
+
+/* Unsupported features */
+#undef CONFIG_USE_IRQ
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+/*
+ * Place the image at the start of the ROM defined image space.
+ * We limit our size to the ROM-defined downloaded image area, and use the
+ * rest of the space for stack.
+ */
+#define CONFIG_SPL_TEXT_BASE		0x402F0400
+#define CONFIG_SPL_MAX_SIZE		(0x4030C000 - CONFIG_SPL_TEXT_BASE)
+#define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
+
+#define CONFIG_SPL_BSS_START_ADDR	0x80000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
+
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_YMODEM_SUPPORT
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/am33xx/u-boot-spl.lds"
+
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_NAND_AM33XX_BCH
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
+					 CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
+					 10, 11, 12, 13, 14, 15, 16, 17, \
+					 18, 19, 20, 21, 22, 23, 24, 25, \
+					 26, 27, 28, 29, 30, 31, 32, 33, \
+					 34, 35, 36, 37, 38, 39, 40, 41, \
+					 42, 43, 44, 45, 46, 47, 48, 49, \
+					 50, 51, 52, 53, 54, 55, 56, 57, }
+
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	14
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW
+
+#define	CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * other needs.
+ */
+#define CONFIG_SYS_TEXT_BASE		0x80800000
+#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
+
+/*
+ * Since SPL did pll and ddr initialization for us,
+ * we don't need to do it twice.
+ */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+#endif	/* ! __CONFIG_IGEP0033_H */
diff --git a/qemu/roms/u-boot/include/configs/am3517_crane.h b/qemu/roms/u-boot/include/configs/am3517_crane.h
new file mode 100644
index 000000000..4407b454d
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/am3517_crane.h
@@ -0,0 +1,356 @@
+/*
+ * am3517_crane.h - Default configuration for AM3517 CraneBoard.
+ *
+ * Author: Srinath.R <srinath@mistralsolutions.com>
+ *
+ * Based on include/configs/am3517evm.h
+ *
+ * Copyright (C) 2011 Mistral Solutions pvt Ltd
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_OMAP		1	/* in a TI OMAP core */
+#define CONFIG_OMAP34XX		1	/* which is a 34XX */
+#define CONFIG_OMAP3_AM3517CRANE	1	/* working with CRANEBOARD */
+#define CONFIG_OMAP_COMMON
+
+#define CONFIG_EMIF4	/* The chip has EMIF4 controller */
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO		1
+#define CONFIG_DISPLAY_BOARDINFO	1
+
+/* Clock Defines */
+#define V_OSCK			26000000	/* Clock output from T2 */
+#define V_SCLK			(V_OSCK >> 1)
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+#define CONFIG_REVISION_TAG		1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB sector */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
+						/* initial data */
+/*
+ * DDR related
+ */
+#define CONFIG_SYS_CS0_SIZE		(256 * 1024 * 1024)
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX		3
+#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
+#define CONFIG_SERIAL3			3	/* UART3 on CRANEBOARD */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
+					115200}
+#define CONFIG_GENERIC_MMC		1
+#define CONFIG_MMC			1
+#define CONFIG_OMAP_HSMMC		1
+#define CONFIG_DOS_PARTITION		1
+
+/*
+ * USB configuration
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDC for Device functionalities.
+ */
+#define CONFIG_USB_AM35X		1
+#define CONFIG_MUSB_HCD			1
+
+#ifdef CONFIG_USB_AM35X
+
+#ifdef CONFIG_MUSB_HCD
+#define CONFIG_CMD_USB
+
+#define CONFIG_USB_STORAGE
+#define CONGIG_CMD_STORAGE
+#define CONFIG_CMD_FAT
+
+#ifdef CONFIG_USB_KEYBOARD
+#define CONFIG_SYS_USB_EVENT_POLL
+#define CONFIG_PREBOOT "usb start"
+#endif /* CONFIG_USB_KEYBOARD */
+
+#endif /* CONFIG_MUSB_HCD */
+
+#ifdef CONFIG_MUSB_UDC
+/* USB device configuration */
+#define CONFIG_USB_DEVICE		1
+#define CONFIG_USB_TTY			1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
+/* Change these to suit your needs */
+#define CONFIG_USBD_VENDORID		0x0451
+#define CONFIG_USBD_PRODUCTID		0x5678
+#define CONFIG_USBD_MANUFACTURER	"Texas Instruments"
+#define CONFIG_USBD_PRODUCT_NAME	"AM3517CRANE"
+#endif /* CONFIG_MUSB_UDC */
+
+#endif /* CONFIG_USB_AM35X */
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
+#define CONFIG_CMD_FAT		/* FAT support			*/
+#define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
+
+#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
+#define CONFIG_CMD_MMC		/* MMC support			*/
+#define CONFIG_CMD_NAND		/* NAND support			*/
+#define CONFIG_CMD_DHCP
+#undef CONFIG_CMD_PING
+
+#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
+#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
+#undef CONFIG_CMD_IMI		/* iminfo			*/
+#undef CONFIG_CMD_IMLS		/* List all found images	*/
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
+#define CONFIG_SYS_I2C_OMAP34XX
+
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
+							/* to access nand */
+#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
+							/* to access */
+							/* nand at CS0 */
+
+#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
+							/* NAND devices */
+
+#define CONFIG_JFFS2_NAND
+/* nand device jffs2 lives on */
+#define CONFIG_JFFS2_DEV		"nand0"
+/* start of jffs2 partition */
+#define CONFIG_JFFS2_PART_OFFSET	0x680000
+#define CONFIG_JFFS2_PART_SIZE		0xf980000	/* sz of jffs2 part */
+
+/* Environment information */
+#define CONFIG_BOOTDELAY	10
+
+#define CONFIG_BOOTFILE		"uImage"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x82000000\0" \
+	"console=ttyS2,115200n8\0" \
+	"mmcdev=0\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"root=/dev/mmcblk0p2 rw " \
+		"rootfstype=ext3 rootwait\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"root=/dev/mtdblock4 rw " \
+		"rootfstype=jffs2\0" \
+	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source ${loadaddr}\0" \
+	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nand read ${loadaddr} 280000 400000; " \
+		"bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loaduimage; then " \
+				"run mmcboot; " \
+			"else run nandboot; " \
+			"fi; " \
+		"fi; " \
+	"else run nandboot; fi"
+
+#define CONFIG_AUTO_COMPLETE	1
+/*
+ * Miscellaneous configurable options
+ */
+#define V_PROMPT			"AM3517_CRANE # "
+
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT		V_PROMPT
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		32	/* max number of command */
+						/* args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
+#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
+					0x01F00000) /* 31MB */
+
+#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
+								/* address */
+
+/*
+ * AM3517 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
+#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
+#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+
+/* Configure the PISMO */
+#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
+#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M
+
+#define CONFIG_SYS_MAX_FLASH_SECT	520	/* max number of sectors */
+						/* on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
+
+#define CONFIG_SYS_FLASH_BASE		PISMO1_NAND_BASE
+
+/* Monitor at start of flash */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_ENV_IS_IN_NAND		1
+#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
+
+#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB sector */
+#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
+#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
+
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+/* timeout values are in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(100 * CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(100 * CONFIG_SYS_HZ)
+
+/* Flash banks JFFS2 should use */
+#define CONFIG_SYS_MAX_MTD_BANKS	(CONFIG_SYS_MAX_FLASH_BANKS + \
+					CONFIG_SYS_MAX_NAND_DEVICE)
+#define CONFIG_SYS_JFFS2_MEM_NAND
+/* use flash_info[2] */
+#define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
+#define CONFIG_SYS_JFFS2_NUM_BANKS	1
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE	0x800
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SPL_TEXT_BASE		0x40200800
+#define CONFIG_SPL_MAX_SIZE		(54 * 1024)	/* 8 KB for stack */
+#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
+
+#define CONFIG_SPL_BSS_START_ADDR	0x80000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
+
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
+
+/* NAND boot config */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9,\
+						10, 11, 12, 13}
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * other needs.
+ */
+#define CONFIG_SYS_TEXT_BASE		0x80100000
+#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/am3517_evm.h b/qemu/roms/u-boot/include/configs/am3517_evm.h
new file mode 100644
index 000000000..0102ff5b7
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/am3517_evm.h
@@ -0,0 +1,365 @@
+/*
+ * am3517_evm.h - Default configuration for AM3517 EVM board.
+ *
+ * Author: Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * Based on omap3_evm_config.h
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_OMAP		1	/* in a TI OMAP core */
+#define CONFIG_OMAP34XX		1	/* which is a 34XX */
+#define CONFIG_OMAP3_AM3517EVM	1	/* working with AM3517EVM */
+#define CONFIG_OMAP_COMMON
+
+#define CONFIG_EMIF4	/* The chip has EMIF4 controller */
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO		1
+#define CONFIG_DISPLAY_BOARDINFO	1
+
+/* Clock Defines */
+#define V_OSCK			26000000	/* Clock output from T2 */
+#define V_SCLK			(V_OSCK >> 1)
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+#define CONFIG_REVISION_TAG		1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB sector */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
+/*
+ * DDR related
+ */
+#define CONFIG_SYS_CS0_SIZE		(256 * 1024 * 1024)
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * OMAP GPIO configuration
+ */
+#define CONFIG_OMAP_GPIO
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX		3
+#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
+#define CONFIG_SERIAL3			3	/* UART3 on AM3517 EVM */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
+					115200}
+#define CONFIG_MMC			1
+#define CONFIG_GENERIC_MMC		1
+#define CONFIG_OMAP_HSMMC		1
+#define CONFIG_DOS_PARTITION		1
+
+/*
+ * USB configuration
+ * Enable CONFIG_MUSB_HOST for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_GADGET for Device functionalities.
+ */
+#define CONFIG_USB_MUSB_AM35X
+#define CONFIG_MUSB_HOST
+#define CONFIG_MUSB_PIO_ONLY
+
+#ifdef CONFIG_USB_MUSB_AM35X
+
+#ifdef CONFIG_MUSB_HOST
+#define CONFIG_CMD_USB
+
+#define CONFIG_USB_STORAGE
+#define CONGIG_CMD_STORAGE
+#define CONFIG_CMD_FAT
+
+#ifdef CONFIG_USB_KEYBOARD
+#define CONFIG_SYS_USB_EVENT_POLL
+#define CONFIG_PREBOOT "usb start"
+#endif /* CONFIG_USB_KEYBOARD */
+
+#endif /* CONFIG_MUSB_HOST */
+
+#ifdef CONFIG_MUSB_GADGET
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_ETHER
+#define CONFIG_USB_ETH_RNDIS
+#endif /* CONFIG_MUSB_GADGET */
+
+#endif /* CONFIG_USB_MUSB_AM35X */
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
+#define CONFIG_CMD_FAT		/* FAT support			*/
+#define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
+
+#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
+#define CONFIG_CMD_MMC		/* MMC support			*/
+#define CONFIG_CMD_NAND		/* NAND support			*/
+#define CONFIG_CMD_DHCP
+#undef CONFIG_CMD_PING
+
+#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
+#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
+#undef CONFIG_CMD_IMI		/* iminfo			*/
+#undef CONFIG_CMD_IMLS		/* List all found images	*/
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
+#define CONFIG_SYS_I2C_OMAP34XX
+
+/*
+ * Ethernet
+ */
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_DRIVER_TI_EMAC_USE_RMII
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT		10
+
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
+							/* to access nand */
+#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
+							/* to access */
+							/* nand at CS0 */
+
+#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
+							/* NAND devices */
+#define CONFIG_JFFS2_NAND
+/* nand device jffs2 lives on */
+#define CONFIG_JFFS2_DEV		"nand0"
+/* start of jffs2 partition */
+#define CONFIG_JFFS2_PART_OFFSET	0x680000
+#define CONFIG_JFFS2_PART_SIZE		0xf980000	/* sz of jffs2 part */
+
+/* Environment information */
+#define CONFIG_BOOTDELAY	10
+
+#define CONFIG_BOOTFILE		"uImage"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x82000000\0" \
+	"console=ttyO2,115200n8\0" \
+	"mmcdev=0\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"root=/dev/mmcblk0p2 rw rootwait\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"root=/dev/mtdblock4 rw " \
+		"rootfstype=jffs2\0" \
+	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source ${loadaddr}\0" \
+	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nand read ${loadaddr} 280000 400000; " \
+		"bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loaduimage; then " \
+				"run mmcboot; " \
+			"else run nandboot; " \
+			"fi; " \
+		"fi; " \
+	"else run nandboot; fi"
+
+#define CONFIG_AUTO_COMPLETE	1
+/*
+ * Miscellaneous configurable options
+ */
+#define V_PROMPT			"AM3517_EVM # "
+
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT		V_PROMPT
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		32	/* max number of command */
+						/* args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
+#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
+					0x01F00000) /* 31MB */
+
+#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
+								/* address */
+
+/*
+ * AM3517 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
+#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
+#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+
+/* Configure the PISMO */
+#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
+#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M
+
+#define CONFIG_SYS_MAX_FLASH_SECT	520	/* max number of sectors */
+						/* on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
+
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_SYS_FLASH_BASE		PISMO1_NAND_BASE
+#endif
+
+/* Monitor at start of flash */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_ENV_IS_IN_NAND		1
+#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
+
+#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
+#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
+#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
+
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+/* timeout values are in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(100 * CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(100 * CONFIG_SYS_HZ)
+
+/* Flash banks JFFS2 should use */
+#define CONFIG_SYS_MAX_MTD_BANKS	(CONFIG_SYS_MAX_FLASH_BANKS + \
+					CONFIG_SYS_MAX_NAND_DEVICE)
+#define CONFIG_SYS_JFFS2_MEM_NAND
+/* use flash_info[2] */
+#define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
+#define CONFIG_SYS_JFFS2_NUM_BANKS	1
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE	0x800
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SPL_TEXT_BASE		0x40200800
+#define CONFIG_SPL_MAX_SIZE		(54 * 1024)	/* 8 KB for stack */
+#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
+
+#define CONFIG_SPL_BSS_START_ADDR	0x80000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
+
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
+
+/* NAND boot config */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9,\
+						10, 11, 12, 13}
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * other needs.
+ */
+#define CONFIG_SYS_TEXT_BASE		0x80100000
+#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/am43xx_evm.h b/qemu/roms/u-boot/include/configs/am43xx_evm.h
new file mode 100644
index 000000000..d5e6c4b0d
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/am43xx_evm.h
@@ -0,0 +1,225 @@
+/*
+ * am43xx_evm.h
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_AM43XX_EVM_H
+#define __CONFIG_AM43XX_EVM_H
+
+#define CONFIG_AM43XX
+
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_SYS_CACHELINE_SIZE       32
+#define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 20)	/* 1GB */
+#define CONFIG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
+
+#include <asm/arch/omap.h>
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		48000000
+
+/* I2C Configuration */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* Main EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+
+/* SPL defines. */
+#define CONFIG_SPL_TEXT_BASE		0x40300350
+#define CONFIG_SPL_MAX_SIZE		(220 << 10)	/* 220KB */
+#define CONFIG_SYS_SPL_ARGS_ADDR	(CONFIG_SYS_SDRAM_BASE + \
+					 (128 << 20))
+#define CONFIG_SPL_YMODEM_SUPPORT
+
+/* Enabling L2 Cache */
+#define CONFIG_SYS_L2_PL310
+#define CONFIG_SYS_PL310_BASE	0x48242000
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
+/*
+ * Since SPL did pll and ddr initialization for us,
+ * we don't need to do it twice.
+ */
+#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+/* Now bring in the rest of the common code. */
+#include <configs/ti_armv7_common.h>
+
+/* Always 128 KiB env size */
+#define CONFIG_ENV_SIZE			(128 << 10)
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+/* Clock Defines */
+#define V_OSCK				24000000  /* Clock output from T2 */
+#define V_SCLK				(V_OSCK)
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550_COM1		0x44e09000	/* Base EVM has UART0 */
+
+#define CONFIG_ENV_IS_NOWHERE
+
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
+
+/* SPL USB Support */
+#define CONFIG_SPL_USB_SUPPORT
+#define CONFIG_SPL_USB_HOST_SUPPORT
+#define CONFIG_SYS_USB_FAT_BOOT_PARTITION		1
+
+#define CONFIG_CMD_USB
+#define CONFIG_USB_HOST
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_OMAP
+#define CONFIG_USB_STORAGE
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+
+#define CONFIG_OMAP_USB_PHY
+#define CONFIG_AM437X_USB2PHY2_HOST
+
+/* SPI */
+#undef CONFIG_OMAP3_SPI
+#define CONFIG_TI_QSPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_MACRONIX
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_TI_SPI_MMAP
+#define CONFIG_QSPI_SEL_GPIO                   48
+#define CONFIG_SF_DEFAULT_SPEED                48000000
+#define CONFIG_DEFAULT_SPI_MODE                SPI_MODE_3
+
+/* Enhance our eMMC support / experience. */
+#define CONFIG_CMD_GPT
+#define CONFIG_EFI_PARTITION
+#define CONFIG_PARTITION_UUIDS
+#define CONFIG_CMD_PART
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	DEFAULT_LINUX_BOOT_ENV \
+	"fdtfile=undefined\0" \
+	"bootpart=0:2\0" \
+	"bootdir=/boot\0" \
+	"bootfile=zImage\0" \
+	"console=ttyO0,115200n8\0" \
+	"partitions=" \
+		"uuid_disk=${uuid_gpt_disk};" \
+		"name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \
+	"optargs=\0" \
+	"mmcdev=0\0" \
+	"mmcroot=/dev/mmcblk0p2 rw\0" \
+	"mmcrootfstype=ext4 rootwait\0" \
+	"usbroot=/dev/sda2 rw\0" \
+	"usbrootfstype=ext4 rootwait\0" \
+	"usbdev=0\0" \
+	"ramroot=/dev/ram0 rw\0" \
+	"ramrootfstype=ext2\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0" \
+	"usbargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${usbroot} " \
+		"rootfstype=${usbrootfstype}\0" \
+	"bootenv=uEnv.txt\0" \
+	"loadbootenv=load ${devtype} ${devnum} ${loadaddr} ${bootenv}\0" \
+	"importbootenv=echo Importing environment from mmc ...; " \
+		"env import -t $loadaddr $filesize\0" \
+	"ramargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${ramroot} " \
+		"rootfstype=${ramrootfstype}\0" \
+	"loadramdisk=load ${devtype} ${devnum} ${rdaddr} ramdisk.gz\0" \
+	"loadimage=load ${devtype} ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
+	"loadfdt=load ${devtype} ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
+	"mmcboot=mmc dev ${mmcdev}; " \
+		"setenv devnum ${mmcdev}; " \
+		"if mmc rescan; then " \
+			"echo SD/MMC found on device ${devnum};" \
+			"if run loadbootenv; then " \
+				"echo Loaded environment from ${bootenv};" \
+				"run importbootenv;" \
+			"fi;" \
+			"if test -n $uenvcmd; then " \
+				"echo Running uenvcmd ...;" \
+				"run uenvcmd;" \
+			"fi;" \
+			"if run loadimage; then " \
+				"run loadfdt; " \
+				"echo Booting from mmc${mmcdev} ...; " \
+				"run mmcargs; " \
+				"bootz ${loadaddr} - ${fdtaddr}; " \
+			"fi;" \
+		"fi;\0" \
+	"usbboot=" \
+		"setenv devnum ${usbdev}; " \
+		"setenv devtype usb; " \
+		"usb start ${usbdev}; " \
+		"if usb dev ${usbdev}; then " \
+			"if run loadbootenv; then " \
+				"echo Loaded environment from ${bootenv};" \
+				"run importbootenv;" \
+			"fi;" \
+			"if test -n $uenvcmd; then " \
+				"echo Running uenvcmd ...;" \
+				"run uenvcmd;" \
+			"fi;" \
+			"if run loadimage; then " \
+				"run loadfdt; " \
+				"echo Booting from usb ${usbdev}...; " \
+				"run usbargs;" \
+				"bootz ${loadaddr} - ${fdtaddr}; " \
+			"fi;" \
+		"fi\0" \
+	"findfdt="\
+		"if test $board_name = AM43EPOS; then " \
+			"setenv fdtfile am43x-epos-evm.dtb; fi; " \
+		"if test $board_name = AM43__GP; then " \
+			"setenv fdtfile am437x-gp-evm.dtb; fi; " \
+		"if test $fdtfile = undefined; then " \
+			"echo WARNING: Could not determine device tree; fi; \0"
+
+#define CONFIG_BOOTCOMMAND \
+	"run findfdt; " \
+	"run mmcboot;" \
+	"run usbboot;"
+
+#endif
+
+/* CPSW Ethernet */
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MII
+#define CONFIG_DRIVER_TI_CPSW
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_NET_RETRY_COUNT		10
+#define CONFIG_NET_MULTI
+#define CONFIG_PHY_GIGE
+#define CONFIG_PHYLIB
+
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_NET_VCI_STRING	"AM43xx U-Boot SPL"
+
+#define CONFIG_SPL_ETH_SUPPORT
+#define CONFIG_SPL_NET_SUPPORT
+#define CONFIG_SYS_RX_ETH_BUFFER	64
+
+#endif	/* __CONFIG_AM43XX_EVM_H */
diff --git a/qemu/roms/u-boot/include/configs/amcc-common.h b/qemu/roms/u-boot/include/configs/amcc-common.h
new file mode 100644
index 000000000..2aea89937
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/amcc-common.h
@@ -0,0 +1,256 @@
+/*
+ * (C) Copyright 2008, 2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * Common configuration options for all AMCC boards
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __AMCC_COMMON_H
+#define __AMCC_COMMON_H
+
+#define CONFIG_SYS_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* Start of U-Boot	*/
+#define CONFIG_SYS_MONITOR_LEN		(0xFFFFFFFF - CONFIG_SYS_MONITOR_BASE + 1)
+#define CONFIG_SYS_MALLOC_LEN		(1 << 20)	/* Reserved for malloc	*/
+
+/*
+ * UART
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
+
+/*
+ * Ethernet/EMAC/PHY
+ */
+#define CONFIG_PPC4xx_EMAC
+#define CONFIG_MII			/* MII PHY management		*/
+#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
+#if defined(CONFIG_440)
+#define CONFIG_SYS_RX_ETH_BUFFER	32	/* number of eth rx buffers	*/
+#else
+#define CONFIG_SYS_RX_ETH_BUFFER	16	/* number of eth rx buffers	*/
+#endif
+
+/*
+ * Commands
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#if defined(CONFIG_440)
+#define CONFIG_CMD_CACHE
+#endif
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SETEXPR
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000 /* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000  /* default load address	*/
+#define CONFIG_SYS_EXTBDINFO			/* To use extended board_into (bd_t) */
+
+#define CONFIG_CMDLINE_EDITING		/* add command line history	*/
+#define CONFIG_AUTO_COMPLETE		/* add autocompletion support	*/
+#define CONFIG_LOOPW			/* enable loopw command         */
+#define CONFIG_MX_CYCLIC		/* enable mdc/mwc commands      */
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 	/* include version env variable */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	/* don't print console @ startup*/
+
+#define CONFIG_SYS_HUSH_PARSER		/* Use the HUSH parser		*/
+
+#define CONFIG_LOADS_ECHO		/* echo on for serial download	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change	*/
+
+#define CONFIG_REGEX			/* Enable regular expression support */
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_SUBNETMASK
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the 40x Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(16 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTM_LEN		(16 << 20) /* Increase max gunzip size */
+
+/*
+ * Internal Definitions
+ */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port*/
+#endif
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+/* Update size in "reg" property of NOR FLASH device tree nodes */
+#define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
+
+/*
+ * Booting and default environment
+ */
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+/*
+ * Only very few boards have default console not on ttyS0 (like Taishan)
+ */
+#if !defined(CONFIG_USE_TTY)
+#define CONFIG_USE_TTY	ttyS0
+#endif
+
+/*
+ * Only very few boards have default netdev not set to eth0 (like Arches)
+ */
+#if !defined(CONFIG_USE_NETDEV)
+#define CONFIG_USE_NETDEV	eth0
+#endif
+
+/*
+ * Only some 4xx PPC's are equipped with an FPU
+ */
+#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#define CONFIG_AMCC_DEF_ENV_ROOTPATH	"rootpath=/opt/eldk/ppc_4xxFP\0"
+#else
+#define CONFIG_AMCC_DEF_ENV_ROOTPATH	"rootpath=/opt/eldk/ppc_4xx\0"
+#endif
+
+/*
+ * Only some boards need to extend the bootargs by some additional
+ * parameters (like Makalu)
+ */
+#if !defined(CONFIG_ADDMISC)
+#define CONFIG_ADDMISC	"addmisc=setenv bootargs ${bootargs}\0"
+#endif
+
+/*
+ * General common environment variables shared on all AMCC eval boards
+ */
+#define CONFIG_AMCC_DEF_ENV						\
+	"netdev=" __stringify(CONFIG_USE_NETDEV) "\0"				\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs}"				\
+		" console=" __stringify(CONFIG_USE_TTY) ",${baudrate}\0"	\
+	CONFIG_ADDMISC							\
+	"initrd_high=30000000\0"					\
+	"kernel_addr_r=1000000\0"					\
+	"fdt_addr_r=1800000\0"						\
+	"ramdisk_addr_r=1900000\0"					\
+	"hostname=" __stringify(CONFIG_HOSTNAME) "\0"				\
+	"bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0"			\
+	"ramdisk_file=" __stringify(CONFIG_HOSTNAME) "/uRamdisk\0"		\
+	CONFIG_AMCC_DEF_ENV_ROOTPATH
+
+/*
+ * Default environment for arch/powerpc booting
+ * for boards that are ported to arch/powerpc
+ */
+#define CONFIG_AMCC_DEF_ENV_POWERPC					\
+	"flash_self=run ramargs addip addtty addmisc;"			\
+		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
+	"flash_nfs=run nfsargs addip addtty addmisc;"			\
+		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
+		"tftp ${fdt_addr_r} ${fdt_file}; "			\
+		"run nfsargs addip addtty addmisc;"			\
+		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
+	"net_self_load=tftp ${kernel_addr_r} ${bootfile};"		\
+		"tftp ${fdt_addr_r} ${fdt_file};"			\
+		"tftp ${ramdisk_addr_r} ${ramdisk_file};\0"		\
+	"net_self=run net_self_load;"					\
+		"run ramargs addip addtty addmisc;"			\
+		"bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0" \
+	"fdt_file=" __stringify(CONFIG_HOSTNAME) "/" __stringify(CONFIG_HOSTNAME) ".dtb\0"
+
+/*
+ * Default environment for arch/ppc booting,
+ * for boards that are not ported to arch/powerpc yet
+ */
+#define CONFIG_AMCC_DEF_ENV_PPC						\
+	"flash_self=run ramargs addip addtty addmisc;"			\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"flash_nfs=run nfsargs addip addtty addmisc;"			\
+		"bootm ${kernel_addr}\0"				\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
+		"run nfsargs addip addtty addmisc;"			\
+		"bootm ${kernel_addr_r}\0"
+
+/*
+ * Default environment for arch/ppc booting (old version),
+ * for boards that are ported to arch/ppc and arch/powerpc
+ */
+#define CONFIG_AMCC_DEF_ENV_PPC_OLD					\
+	"flash_self_old=run ramargs addip addtty addmisc;"		\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"flash_nfs_old=run nfsargs addip addtty addmisc;"		\
+		"bootm ${kernel_addr}\0"				\
+	"net_nfs_old=tftp ${kernel_addr_r} ${bootfile};"		\
+		"run nfsargs addip addtty addmisc;"			\
+		"bootm ${kernel_addr_r}\0"
+
+#define CONFIG_AMCC_DEF_ENV_NOR_UPD					\
+	"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0"		\
+	"load=tftp 200000 ${u-boot}\0"					\
+	"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) " FFFFFFFF;"	\
+		"era " __stringify(CONFIG_SYS_MONITOR_BASE) " FFFFFFFF;"	\
+		"cp.b ${fileaddr} " __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
+	"upd=run load update\0"						\
+
+#endif /* __AMCC_COMMON_H */
diff --git a/qemu/roms/u-boot/include/configs/ap325rxa.h b/qemu/roms/u-boot/include/configs/ap325rxa.h
new file mode 100644
index 000000000..462b2e291
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/ap325rxa.h
@@ -0,0 +1,159 @@
+/*
+ * Configuation settings for the Renesas Solutions AP-325RXA board
+ *
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __AP325RXA_H
+#define __AP325RXA_H
+
+#undef DEBUG
+#define CONFIG_CPU_SH7723	1
+#define CONFIG_AP325RXA	1
+
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_EXT2
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_BAUDRATE		38400
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTARGS		"console=ttySC2,38400"
+
+#define CONFIG_VERSION_VARIABLE
+#undef  CONFIG_SHOW_BOOT_PROGRESS
+
+/* SMC9118 */
+#define CONFIG_SMC911X 1
+#define CONFIG_SMC911X_32_BIT 1
+#define CONFIG_SMC911X_BASE 0xB6080000
+
+/* MEMORY */
+#define AP325RXA_SDRAM_BASE		(0x88000000)
+#define AP325RXA_FLASH_BASE_1		(0xA0000000)
+#define AP325RXA_FLASH_BANK_SIZE	(128 * 1024 * 1024)
+
+#define CONFIG_SYS_TEXT_BASE	0x8FFC0000
+
+/* undef to save memory	*/
+#define CONFIG_SYS_LONGHELP
+/* Monitor Command Prompt */
+/* Buffer size for input from the Console */
+#define CONFIG_SYS_CBSIZE		256
+/* Buffer size for Console output */
+#define CONFIG_SYS_PBSIZE		256
+/* max args accepted for monitor commands */
+#define CONFIG_SYS_MAXARGS		16
+/* Buffer size for Boot Arguments passed to kernel */
+#define CONFIG_SYS_BARGSIZE	512
+/* List of legal baudrate settings for this board */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 38400 }
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE 1
+#define CONFIG_SCIF_A		1 /* SH7723 has SCIF and SCIFA */
+#define CONFIG_CONS_SCIF5	1
+
+/* Suppress display of console information at boot */
+#undef  CONFIG_SYS_CONSOLE_INFO_QUIET
+#undef  CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#undef  CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+
+#define CONFIG_SYS_MEMTEST_START	(AP325RXA_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
+
+/* Enable alternate, more extensive, memory test */
+#undef  CONFIG_SYS_ALT_MEMTEST
+/* Scratch address used by the alternate memory test */
+#undef  CONFIG_SYS_MEMTEST_SCRATCH
+
+/* Enable temporary baudrate change while serial download */
+#undef  CONFIG_SYS_LOADS_BAUD_CHANGE
+
+#define CONFIG_SYS_SDRAM_BASE	(AP325RXA_SDRAM_BASE)
+/* maybe more, but if so u-boot doesn't know about it... */
+#define CONFIG_SYS_SDRAM_SIZE	(128 * 1024 * 1024)
+/* default load address for scripts ?!? */
+#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
+
+/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
+#define CONFIG_SYS_MONITOR_BASE	(AP325RXA_FLASH_BASE_1)
+/* Monitor size */
+#define CONFIG_SYS_MONITOR_LEN	(128 * 1024)
+/* Size of DRAM reserved for malloc() use */
+#define CONFIG_SYS_MALLOC_LEN	(256 * 1024)
+#define CONFIG_SYS_BOOTMAPSZ	(8 * 1024 * 1024)
+
+/* FLASH */
+#define CONFIG_FLASH_CFI_DRIVER 1
+#define CONFIG_SYS_FLASH_CFI
+#undef  CONFIG_SYS_FLASH_QUIET_TEST
+/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+/* Physical start address of Flash memory */
+#define CONFIG_SYS_FLASH_BASE	(AP325RXA_FLASH_BASE_1)
+/* Max number of sectors on each Flash chip */
+#define CONFIG_SYS_MAX_FLASH_SECT	512
+
+/*
+ * IDE support
+ */
+#define CONFIG_IDE_RESET	1
+#define CONFIG_SYS_PIO_MODE		1
+#define CONFIG_SYS_IDE_MAXBUS		1	/* IDE bus */
+#define CONFIG_SYS_IDE_MAXDEVICE	1
+#define CONFIG_SYS_ATA_BASE_ADDR	0xB4180000
+#define CONFIG_SYS_ATA_STRIDE		2	/* 1bit shift */
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x200	/* data reg offset */
+#define CONFIG_SYS_ATA_REG_OFFSET	0x200	/* reg offset */
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x210	/* alternate register offset */
+#define CONFIG_IDE_SWAP_IO
+
+/* if you use all NOR Flash , you change dip-switch. Please see Manual. */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + (0 * AP325RXA_FLASH_BANK_SIZE)}
+
+/* Timeout for Flash erase operations (in ms) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(3 * 1000)
+/* Timeout for Flash write operations (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(3 * 1000)
+/* Timeout for Flash set sector lock bit operations (in ms) */
+#define CONFIG_SYS_FLASH_LOCK_TOUT	(3 * 1000)
+/* Timeout for Flash clear lock bit operations (in ms) */
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	(3 * 1000)
+
+/*
+ * Use hardware flash sectors protection instead
+ * of U-Boot software protection
+ */
+#undef  CONFIG_SYS_FLASH_PROTECTION
+#undef  CONFIG_SYS_DIRECT_FLASH_TFTP
+
+/* ENV setting */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE	1
+#define CONFIG_ENV_SECT_SIZE	(128 * 1024)
+#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
+/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
+#define CONFIG_ENV_OFFSET		(CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
+
+/* Board Clock */
+#define CONFIG_SYS_CLK_FREQ	33333333
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_TMU_CLK_DIV		(4)	/* 4 (default), 16, 64, 256 or 1024 */
+
+#endif	/* __AP325RXA_H */
diff --git a/qemu/roms/u-boot/include/configs/ap_sh4a_4a.h b/qemu/roms/u-boot/include/configs/ap_sh4a_4a.h
new file mode 100644
index 000000000..4282d7026
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/ap_sh4a_4a.h
@@ -0,0 +1,159 @@
+/*
+ * Configuation settings for the Alpha Project AP-SH4A-4A board
+ *
+ * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __AP_SH4A_4A_H
+#define __AP_SH4A_4A_H
+
+#undef DEBUG
+#define CONFIG_CPU_SH7734	1
+#define CONFIG_AP_SH4A_4A	1
+#define CONFIG_400MHZ_MODE	1
+/* #define CONFIG_533MHZ_MODE	1 */
+
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_SYS_TEXT_BASE 0x8BFC0000
+
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
+
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTARGS		"console=ttySC4,115200"
+
+#define CONFIG_VERSION_VARIABLE
+#undef  CONFIG_SHOW_BOOT_PROGRESS
+
+/* Ether */
+#define CONFIG_SH_ETHER 1
+#define CONFIG_SH_ETHER_USE_PORT (0)
+#define CONFIG_SH_ETHER_PHY_ADDR (0x0)
+#define CONFIG_SH_ETHER_PHY_MODE (PHY_INTERFACE_MODE_GMII)
+#define CONFIG_SH_ETHER_SH7734_MII (0x02) /* GMII */
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL 1
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+
+/* I2C */
+#define CONFIG_CMD_I2C
+#define CONFIG_SH_SH7734_I2C	1
+#define CONFIG_HARD_I2C			1
+#define CONFIG_I2C_MULTI_BUS	1
+#define CONFIG_SYS_MAX_I2C_BUS	2
+#define CONFIG_SYS_I2C_MODULE	0
+#define CONFIG_SYS_I2C_SPEED	400000 /* 400 kHz */
+#define CONFIG_SYS_I2C_SLAVE	0x50
+#define CONFIG_SH_I2C_DATA_HIGH	4
+#define CONFIG_SH_I2C_DATA_LOW	5
+#define CONFIG_SH_I2C_CLOCK		500000000
+#define CONFIG_SH_I2C_BASE0		0xFFC70000
+#define CONFIG_SH_I2C_BASE1		0xFFC71000
+
+/* undef to save memory	*/
+#define CONFIG_SYS_LONGHELP
+/* Monitor Command Prompt */
+/* Buffer size for input from the Console */
+#define CONFIG_SYS_CBSIZE		256
+/* Buffer size for Console output */
+#define CONFIG_SYS_PBSIZE		256
+/* max args accepted for monitor commands */
+#define CONFIG_SYS_MAXARGS		16
+/* Buffer size for Boot Arguments passed to kernel */
+#define CONFIG_SYS_BARGSIZE	512
+/* List of legal baudrate settings for this board */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE	1
+#define CONFIG_SCIF			1
+#define CONFIG_CONS_SCIF4	1
+
+/* Suppress display of console information at boot */
+#undef  CONFIG_SYS_CONSOLE_INFO_QUIET
+#undef  CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#undef  CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+
+/* SDRAM */
+#define CONFIG_SYS_SDRAM_BASE	(0x88000000)
+#define CONFIG_SYS_SDRAM_SIZE	(64 * 1024 * 1024)
+#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
+
+#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END	 (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE)
+/* Enable alternate, more extensive, memory test */
+#undef  CONFIG_SYS_ALT_MEMTEST
+/* Scratch address used by the alternate memory test */
+#undef  CONFIG_SYS_MEMTEST_SCRATCH
+
+/* Enable temporary baudrate change while serial download */
+#undef  CONFIG_SYS_LOADS_BAUD_CHANGE
+
+/* FLASH */
+#define CONFIG_FLASH_CFI_DRIVER 1
+#define CONFIG_SYS_FLASH_CFI
+#undef  CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BASE	(0xA0000000)
+#define CONFIG_SYS_MAX_FLASH_SECT	512
+
+/* if you use all NOR Flash , you change dip-switch. Please see Manual. */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+
+/* Timeout for Flash erase operations (in ms) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(3 * 1000)
+/* Timeout for Flash write operations (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(3 * 1000)
+/* Timeout for Flash set sector lock bit operations (in ms) */
+#define CONFIG_SYS_FLASH_LOCK_TOUT	(3 * 1000)
+/* Timeout for Flash clear lock bit operations (in ms) */
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	(3 * 1000)
+
+/*
+ * Use hardware flash sectors protection instead
+ * of U-Boot software protection
+ */
+#undef  CONFIG_SYS_FLASH_PROTECTION
+#undef  CONFIG_SYS_DIRECT_FLASH_TFTP
+
+/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE)
+/* Monitor size */
+#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
+/* Size of DRAM reserved for malloc() use */
+#define CONFIG_SYS_MALLOC_LEN	(256 * 1024)
+#define CONFIG_SYS_BOOTMAPSZ	(8 * 1024 * 1024)
+
+/* ENV setting */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE	1
+#define CONFIG_ENV_SECT_SIZE	(128 * 1024)
+#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
+/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
+#define CONFIG_ENV_OFFSET	(CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
+
+/* Board Clock */
+#if defined(CONFIG_400MHZ_MODE)
+#define CONFIG_SYS_CLK_FREQ 50000000
+#else
+#define CONFIG_SYS_CLK_FREQ 44444444
+#endif
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_TMU_CLK_DIV      4
+
+#endif	/* __AP_SH4A_4A_H */
diff --git a/qemu/roms/u-boot/include/configs/apf27.h b/qemu/roms/u-boot/include/configs/apf27.h
new file mode 100644
index 000000000..b10c48c20
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/apf27.h
@@ -0,0 +1,384 @@
+/*
+ *
+ * Configuration settings for the Armadeus Project motherboard APF27
+ *
+ * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_ENV_VERSION	10
+#define CONFIG_IDENT_STRING	" apf27 patch 3.10"
+#define CONFIG_BOARD_NAME apf27
+
+/*
+ * SoC configurations
+ */
+#define CONFIG_ARM926EJS		/* this is an ARM926EJS CPU */
+#define CONFIG_MX27			/* in a Freescale i.MX27 Chip */
+#define CONFIG_MACH_TYPE	1698	/* APF27 */
+#define CONFIG_SYS_GENERIC_BOARD
+
+/*
+ * Enable the call to miscellaneous platform dependent initialization.
+ */
+#define CONFIG_SYS_NO_FLASH	/* to be define before <config_cmd_default.h> */
+
+/*
+ * Board display option
+ */
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_DISPLAY_CPUINFO
+
+/*
+ * SPL
+ */
+#define CONFIG_SPL
+#define CONFIG_SPL_TARGET	"u-boot-with-spl.bin"
+#define CONFIG_SPL_LDSCRIPT	"arch/$(ARCH)/cpu/u-boot-spl.lds"
+#define CONFIG_SPL_MAX_SIZE	2048
+#define CONFIG_SPL_TEXT_BASE    0xA0000000
+
+/* NAND boot config */
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x800
+#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	CONFIG_SYS_MONITOR_LEN - 0x800
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+
+#define CONFIG_HOSTNAME	CONFIG_BOARD_NAME
+#define CONFIG_ROOTPATH	"/tftpboot/" __stringify(CONFIG_BOARD_NAME) "-root"
+
+/*
+ * U-Boot Commands
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV	/* ask for env variable		*/
+#define CONFIG_CMD_BSP		/* Board Specific functions	*/
+#define CONFIG_CMD_CACHE	/* icache, dcache		*/
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP		/* DHCP Support			*/
+#define CONFIG_CMD_DNS
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT		/* FAT support			*/
+#define CONFIG_CMD_IMX_FUSE	/* imx iim fuse                 */
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII		/* MII support			*/
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_MTDPARTS	/* MTD partition support	*/
+#define CONFIG_CMD_NAND		/* NAND support			*/
+#define CONFIG_CMD_NAND_LOCK_UNLOCK
+#define CONFIG_CMD_NAND_TRIMFFS
+#define CONFIG_CMD_NFS		/* NFS support			*/
+#define CONFIG_CMD_PING		/* ping support			*/
+#define CONFIG_CMD_SETEXPR	/* setexpr support		*/
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+
+/*
+ * Memory configurations
+ */
+#define CONFIG_NR_DRAM_POPULATED 1
+#define CONFIG_NR_DRAM_BANKS	2
+
+#define ACFG_SDRAM_MBYTE_SYZE 64
+
+#define PHYS_SDRAM_1			0xA0000000
+#define PHYS_SDRAM_2			0xB0000000
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (512<<10))
+#define CONFIG_SYS_MEMTEST_START	0xA0000000	/* memtest test area  */
+#define CONFIG_SYS_MEMTEST_END		0xA0300000	/* 3 MiB RAM test */
+
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE	\
+		+ PHYS_SDRAM_1_SIZE - 0x0100000)
+
+#define CONFIG_SYS_TEXT_BASE		0xA0000800
+
+/*
+ * FLASH organization
+ */
+#define	ACFG_MONITOR_OFFSET		0x00000000
+#define	CONFIG_SYS_MONITOR_LEN		0x00100000	/* 1MiB */
+#define CONFIG_ENV_IS_IN_NAND
+#define	CONFIG_ENV_OVERWRITE
+#define	CONFIG_ENV_OFFSET		0x00100000	/* NAND offset */
+#define	CONFIG_ENV_SIZE			0x00020000	/* 128kB  */
+#define CONFIG_ENV_RANGE		0X00080000	/* 512kB */
+#define	CONFIG_ENV_OFFSET_REDUND	\
+		(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)	/* +512kB */
+#define	CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE	/* 512kB */
+#define	CONFIG_FIRMWARE_OFFSET		0x00200000
+#define	CONFIG_FIRMWARE_SIZE		0x00080000	/* 512kB  */
+#define	CONFIG_KERNEL_OFFSET		0x00300000
+#define	CONFIG_ROOTFS_OFFSET		0x00800000
+
+#define CONFIG_MTDMAP			"mxc_nand.0"
+#define MTDIDS_DEFAULT			"nand0=" CONFIG_MTDMAP
+#define MTDPARTS_DEFAULT	"mtdparts=" CONFIG_MTDMAP \
+				":1M(u-boot)ro," \
+				"512K(env)," \
+				"512K(env2)," \
+				"512K(firmware)," \
+				"512K(dtb)," \
+				"5M(kernel)," \
+				"-(rootfs)"
+
+/*
+ * U-Boot general configurations
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT		"BIOS> "	/* prompt string */
+#define CONFIG_SYS_CBSIZE		2048		/* console I/O buffer */
+#define CONFIG_SYS_PBSIZE		\
+				(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+						/* Print buffer size */
+#define CONFIG_SYS_MAXARGS		16		/* max command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+						/* Boot argument buffer size */
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_HUSH_PARSER			/* enable the "hush" shell */
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "	/* secondary prompt string */
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_PREBOOT			"run check_flash check_env;"
+
+
+/*
+ * Boot Linux
+ */
+#define CONFIG_CMDLINE_TAG		/* send commandline to Kernel	*/
+#define CONFIG_SETUP_MEMORY_TAGS	/* send memory definition to kernel */
+#define CONFIG_INITRD_TAG		/* send initrd params	*/
+
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_BOOTDELAY	5
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define	CONFIG_BOOTFILE		__stringify(CONFIG_BOARD_NAME) "-linux.bin"
+#define CONFIG_BOOTARGS		"console=" __stringify(ACFG_CONSOLE_DEV) "," \
+			__stringify(CONFIG_BAUDRATE) " " MTDPARTS_DEFAULT \
+			" ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs "
+
+#define ACFG_CONSOLE_DEV	ttySMX0
+#define CONFIG_BOOTCOMMAND	"run ubifsboot"
+#define CONFIG_SYS_AUTOLOAD	"no"
+/*
+ * Default load address for user programs and kernel
+ */
+#define CONFIG_LOADADDR			0xA0000000
+#define	CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+/*
+ * Extra Environments
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"env_version="		__stringify(CONFIG_ENV_VERSION)		"\0" \
+	"consoledev="		__stringify(ACFG_CONSOLE_DEV)		"\0" \
+	"mtdparts="		MTDPARTS_DEFAULT			"\0" \
+	"partition=nand0,6\0"						\
+	"u-boot_addr="		__stringify(ACFG_MONITOR_OFFSET)	"\0" \
+	"env_addr="		__stringify(CONFIG_ENV_OFFSET)		"\0" \
+	"firmware_addr="	__stringify(CONFIG_FIRMWARE_OFFSET)	"\0" \
+	"firmware_size="	__stringify(CONFIG_FIRMWARE_SIZE)	"\0" \
+	"kernel_addr="		__stringify(CONFIG_KERNEL_OFFSET)	"\0" \
+	"rootfs_addr="		__stringify(CONFIG_ROOTFS_OFFSET)	"\0" \
+	"board_name="		__stringify(CONFIG_BOARD_NAME)		"\0" \
+	"kernel_addr_r=A0000000\0" \
+	"check_env=if test -n ${flash_env_version}; "			\
+		"then env default env_version; "			\
+		"else env set flash_env_version ${env_version}; env save; "\
+		"fi; "							\
+		"if itest ${flash_env_version} < ${env_version}; then " \
+			"echo \"*** Warning - Environment version"	\
+			" change suggests: run flash_reset_env; reset\"; "\
+			"env default flash_reset_env; "\
+		"fi; \0"						\
+	"check_flash=nand lock; nand unlock ${env_addr}; \0"	\
+	"flash_reset_env=env default -f -a; saveenv; run update_env;"	\
+		"echo Flash environment variables erased!\0"		\
+	"download_uboot=tftpboot ${loadaddr} ${board_name}"		\
+		"-u-boot-with-spl.bin\0"				\
+	"flash_uboot=nand unlock ${u-boot_addr} ;"			\
+		"nand erase.part u-boot;"		\
+		"if nand write.trimffs ${fileaddr} ${u-boot_addr} ${filesize};"\
+			"then nand lock; nand unlock ${env_addr};"	\
+				"echo Flashing of uboot succeed;"	\
+			"else echo Flashing of uboot failed;"		\
+		"fi; \0"						\
+	"update_uboot=run download_uboot flash_uboot\0"			\
+	"download_env=tftpboot ${loadaddr} ${board_name}"		\
+		"-u-boot-env.txt\0"				\
+	"flash_env=env import -t ${loadaddr}; env save; \0"		\
+	"update_env=run download_env flash_env\0"			\
+	"update_all=run update_env update_uboot\0"			\
+	"unlock_regs=mw 10000008 0; mw 10020008 0\0"			\
+
+/*
+ * Serial Driver
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_MXC_UART_BASE		UART1_BASE
+
+/*
+ * GPIO
+ */
+#define CONFIG_MXC_GPIO
+
+/*
+ * NOR
+ */
+
+/*
+ * NAND
+ */
+#define CONFIG_NAND_MXC
+
+#define CONFIG_MXC_NAND_REGS_BASE	0xD8000000
+#define CONFIG_SYS_NAND_BASE		CONFIG_MXC_NAND_REGS_BASE
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+
+#define CONFIG_MXC_NAND_HWECC
+#define CONFIG_SYS_NAND_LARGEPAGE
+#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+#define CONFIG_SYS_NAND_PAGE_COUNT	CONFIG_SYS_NAND_BLOCK_SIZE / \
+						CONFIG_SYS_NAND_PAGE_SIZE
+#define CONFIG_SYS_NAND_SIZE		(256 * 1024 * 1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	11
+#define NAND_MAX_CHIPS			1
+
+#define CONFIG_FLASH_SHOW_PROGRESS	45
+#define CONFIG_SYS_NAND_QUIET		1
+
+/*
+ * Partitions & Filsystems
+ */
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SUPPORT_VFAT
+
+/*
+ * UBIFS
+ */
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+
+/*
+ * Ethernet (on SOC imx FEC)
+ */
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_MXC_PHYADDR		0x1f
+#define CONFIG_MII				/* MII PHY management	*/
+
+/*
+ * FPGA
+ */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_FPGA
+#endif
+#define CONFIG_FPGA_COUNT		1
+#define CONFIG_FPGA_XILINX
+#define CONFIG_FPGA_SPARTAN3
+#define CONFIG_SYS_FPGA_WAIT		250 /* 250 ms */
+#define CONFIG_SYS_FPGA_PROG_FEEDBACK
+#define CONFIG_SYS_FPGA_CHECK_CTRLC
+#define CONFIG_SYS_FPGA_CHECK_ERROR
+
+/*
+ * Fuses - IIM
+ */
+#ifdef CONFIG_CMD_IMX_FUSE
+#define IIM_MAC_BANK		0
+#define IIM_MAC_ROW		5
+#define IIM0_SCC_KEY		11
+#define IIM1_SUID		1
+#endif
+
+/*
+ * I2C
+ */
+
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_MXC_I2C1_SPEED	100000	/* 100 kHz */
+#define CONFIG_SYS_MXC_I2C1_SLAVE	0x7F
+#define CONFIG_SYS_MXC_I2C2_SPEED	100000	/* 100 kHz */
+#define CONFIG_SYS_MXC_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_I2C_NOPROBES		{ }
+
+#ifdef CONFIG_CMD_EEPROM
+# define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM 24LC02 */
+# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* bytes of address */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* msec */
+#endif /* CONFIG_CMD_EEPROM */
+#endif /* CONFIG_CMD_I2C */
+
+/*
+ * SD/MMC
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MXC_MMC
+#define CONFIG_MXC_MCI_REGS_BASE	0x10014000
+#endif
+
+/*
+ * RTC
+ */
+#ifdef CONFIG_CMD_DATE
+#define CONFIG_RTC_DS1374
+#define CONFIG_SYS_RTC_BUS_NUM		0
+#endif /* CONFIG_CMD_DATE */
+
+/*
+ * PLL
+ *
+ *  31 | x  |x| x x x x |x x x x x x x x x x |x x|x x x x|x x x x x x x x x x| 0
+ *     |CPLM|X|----PD---|--------MFD---------|XXX|--MFI--|-----MFN-----------|
+ */
+#define CONFIG_MX27_CLK32		32768	/* 32768 or 32000 Hz crystal */
+
+#if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */
+/* micron 64MB */
+#define PHYS_SDRAM_1_SIZE			0x04000000 /* 64 MB */
+#define PHYS_SDRAM_2_SIZE			0x04000000 /* 64 MB */
+#endif
+
+#if (ACFG_SDRAM_MBYTE_SYZE == 128)
+/* micron 128MB */
+#define PHYS_SDRAM_1_SIZE			0x08000000 /* 128 MB */
+#define PHYS_SDRAM_2_SIZE			0x08000000 /* 128 MB */
+#endif
+
+#if (ACFG_SDRAM_MBYTE_SYZE == 256)
+/* micron 256MB */
+#define PHYS_SDRAM_1_SIZE			0x10000000 /* 256 MB */
+#define PHYS_SDRAM_2_SIZE			0x10000000 /* 256 MB */
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/apx4devkit.h b/qemu/roms/u-boot/include/configs/apx4devkit.h
new file mode 100644
index 000000000..d1f18bc45
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/apx4devkit.h
@@ -0,0 +1,144 @@
+/*
+ * Copyright (C) 2012 Bluegiga Technologies Oy
+ *
+ * Authors:
+ * Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
+ * Lauri Hintsala <lauri.hintsala@bluegiga.com>
+ *
+ * Based on m28evk.h:
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __CONFIGS_APX4DEVKIT_H__
+#define __CONFIGS_APX4DEVKIT_H__
+
+/* System configurations */
+#define CONFIG_MX28				/* i.MX28 SoC */
+#define MACH_TYPE_APX4DEVKIT	3712
+#define CONFIG_MACH_TYPE	MACH_TYPE_APX4DEVKIT
+
+/* U-Boot Commands */
+#define CONFIG_SYS_NO_FLASH
+#include <config_cmd_default.h>
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_USB
+
+/* Memory configuration */
+#define CONFIG_NR_DRAM_BANKS		1		/* 1 bank of DRAM */
+#define PHYS_SDRAM_1			0x40000000	/* Base address */
+#define PHYS_SDRAM_1_SIZE		0x20000000	/* Max 512 MB RAM */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+
+
+/* Environment */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_IS_IN_NAND
+
+/* Environment is in MMC */
+#if defined(CONFIG_CMD_MMC) && defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_ENV_OFFSET		(256 * 1024)
+#define CONFIG_ENV_SIZE			(16 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#endif
+
+/* Environment is in NAND */
+#if defined(CONFIG_CMD_NAND) && defined(CONFIG_ENV_IS_IN_NAND)
+#define CONFIG_ENV_SECT_SIZE		(128 * 1024)
+#define CONFIG_ENV_SIZE			(128 * 1024)
+#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
+#define CONFIG_ENV_RANGE		(384 * 1024)
+#define CONFIG_ENV_OFFSET		0x120000
+#define CONFIG_ENV_OFFSET_REDUND	\
+		(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
+#endif
+
+/* UBI and NAND partitioning */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT			"nand0=gpmi-nand"
+#define MTDPARTS_DEFAULT \
+	"mtdparts=gpmi-nand:128k(bootstrap),1024k(boot),768k(env),-(root)"
+#else
+#define MTDPARTS_DEFAULT		""
+#endif
+
+/* FEC Ethernet on SoC */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_NET_MULTI
+#define CONFIG_ETHPRIME			"FEC"
+#define CONFIG_FEC_MXC_PHYADDR		0
+#define IMX_FEC_BASE			MXS_ENET0_BASE
+#endif
+
+/* USB */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_EHCI_MXS_PORT1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
+#define CONFIG_USB_STORAGE
+#endif
+
+
+/* RTC */
+#ifdef CONFIG_CMD_DATE
+#define CONFIG_RTC_PCF8563
+#define CONFIG_SYS_I2C_RTC_ADDR		0x51
+#endif
+
+/* Boot Linux */
+#define CONFIG_BOOTDELAY		1
+#define CONFIG_BOOTFILE			"uImage"
+#define CONFIG_BOOTCOMMAND		"run bootcmd_nand"
+#define CONFIG_LOADADDR			0x41000000
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_SERIAL_TAG
+#define CONFIG_REVISION_TAG
+
+/* Extra Environments */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"verify=no\0" \
+	"bootcmd=run bootcmd_nand\0" \
+	"kernelargs=console=tty0 console=ttyAMA0,115200 consoleblank=0\0" \
+	"bootargs_nand=" \
+		"setenv bootargs ${kernelargs} ubi.mtd=3,2048 " \
+		"root=ubi0:rootfs rootfstype=ubifs ${mtdparts} rw\0" \
+	"bootcmd_nand=" \
+		"run bootargs_nand && ubi part root 2048 && " \
+		"ubifsmount ubi:rootfs && ubifsload 41000000 boot/uImage && " \
+		"bootm 41000000\0" \
+	"bootargs_mmc=" \
+		"setenv bootargs ${kernelargs} " \
+		"root=/dev/mmcblk0p2 rootwait ${mtdparts} rw\0" \
+	"bootcmd_mmc=" \
+		"run bootargs_mmc && mmc rescan && " \
+		"ext2load mmc 0:2 41000000 boot/uImage && bootm 41000000\0" \
+""
+
+/* The rest of the configuration is shared */
+#include <configs/mxs.h>
+
+#endif /* __CONFIGS_APX4DEVKIT_H__ */
diff --git a/qemu/roms/u-boot/include/configs/arcangel4-be.h b/qemu/roms/u-boot/include/configs/arcangel4-be.h
new file mode 100644
index 000000000..88d27db08
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/arcangel4-be.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CONFIG_ARCANGEL4_H_
+#define _CONFIG_ARCANGEL4_H_
+
+/*
+ *  CPU configuration
+ */
+#define CONFIG_SYS_BIG_ENDIAN
+#define CONFIG_ARC700
+#define CONFIG_ARC_MMU_VER		3
+#define CONFIG_SYS_CACHELINE_SIZE	64
+#define CONFIG_SYS_CLK_FREQ		70000000
+#define CONFIG_SYS_TIMER_RATE		CONFIG_SYS_CLK_FREQ
+
+/*
+ * Board configuration
+ */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is in RAM already */
+
+#define CONFIG_ARCH_EARLY_INIT_R
+
+/*
+ * Memory configuration
+ */
+#define CONFIG_SYS_TEXT_BASE		0x81000000
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_SDRAM_SIZE		0x10000000	/* 256 Mb */
+
+#define CONFIG_SYS_INIT_SP_ADDR		\
+	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_MALLOC_LEN		0x200000	/* 2 MB */
+#define CONFIG_SYS_BOOTM_LEN		0x2000000	/* 32 MB */
+#define CONFIG_SYS_LOAD_ADDR		0x82000000
+
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * UART configuration
+ *
+ */
+#define CONFIG_ARC_SERIAL
+#define CONFIG_ARC_UART_BASE		0xC0FC1000
+#define CONFIG_BAUDRATE			115200
+
+/*
+ * Command line configuration
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ELF
+
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_MAXARGS		16
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE			0x00200		/* 512 bytes */
+#define CONFIG_ENV_OFFSET		0
+
+/*
+ * Environment configuration
+ */
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_BOOTFILE			"uImage"
+#define CONFIG_BOOTARGS			"console=ttyARC0,115200n8"
+#define CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR
+
+/*
+ * Console configuration
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT		"arcangel4# "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+						sizeof(CONFIG_SYS_PROMPT) + 16)
+
+#endif /* _CONFIG_ARCANGEL4_H_ */
diff --git a/qemu/roms/u-boot/include/configs/arcangel4.h b/qemu/roms/u-boot/include/configs/arcangel4.h
new file mode 100644
index 000000000..4579eb97c
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/arcangel4.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CONFIG_ARCANGEL4_H_
+#define _CONFIG_ARCANGEL4_H_
+
+/*
+ *  CPU configuration
+ */
+#define CONFIG_ARC700
+#define CONFIG_ARC_MMU_VER		3
+#define CONFIG_SYS_CACHELINE_SIZE	64
+#define CONFIG_SYS_CLK_FREQ		70000000
+#define CONFIG_SYS_TIMER_RATE		CONFIG_SYS_CLK_FREQ
+
+/*
+ * Board configuration
+ */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is in RAM already */
+
+#define CONFIG_ARCH_EARLY_INIT_R
+
+/*
+ * Memory configuration
+ */
+#define CONFIG_SYS_TEXT_BASE		0x81000000
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_SDRAM_SIZE		0x10000000	/* 256 Mb */
+
+#define CONFIG_SYS_INIT_SP_ADDR		\
+	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_MALLOC_LEN		0x200000	/* 2 MB */
+#define CONFIG_SYS_BOOTM_LEN		0x2000000	/* 32 MB */
+#define CONFIG_SYS_LOAD_ADDR		0x82000000
+
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * UART configuration
+ *
+ */
+#define CONFIG_ARC_SERIAL
+#define CONFIG_ARC_UART_BASE		0xC0FC1000
+#define CONFIG_BAUDRATE			115200
+
+/*
+ * Command line configuration
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ELF
+
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_MAXARGS		16
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE			0x00200		/* 512 bytes */
+#define CONFIG_ENV_OFFSET		0
+
+/*
+ * Environment configuration
+ */
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_BOOTFILE			"uImage"
+#define CONFIG_BOOTARGS			"console=ttyARC0,115200n8"
+#define CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR
+
+/*
+ * Console configuration
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT		"arcangel4# "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+						sizeof(CONFIG_SYS_PROMPT) + 16)
+
+#endif /* _CONFIG_ARCANGEL4_H_ */
diff --git a/qemu/roms/u-boot/include/configs/aria.h b/qemu/roms/u-boot/include/configs/aria.h
new file mode 100644
index 000000000..c36cf33f0
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/aria.h
@@ -0,0 +1,646 @@
+/*
+ * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
+ * (C) Copyright 2009, DAVE Srl <www.dave.eu>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Aria board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_ARIA 1
+/*
+ * Memory map for the ARIA board:
+ *
+ * 0x0000_0000-0x0FFF_FFFF	DDR RAM (256 MB)
+ * 0x3000_0000-0x3001_FFFF	On Chip SRAM (128 KB)
+ * 0x3010_0000-0x3011_FFFF	On Board SRAM (128 KB) - CS6
+ * 0x3020_0000-0x3021_FFFF	FPGA (128 KB) - CS2
+ * 0x8000_0000-0x803F_FFFF	IMMR (4 MB)
+ * 0x8400_0000-0x82FF_FFFF	PCI I/O space (16 MB)
+ * 0xA000_0000-0xAFFF_FFFF	PCI memory space (256 MB)
+ * 0xB000_0000-0xBFFF_FFFF	PCI memory mapped I/O space (256 MB)
+ * 0xFC00_0000-0xFFFF_FFFF	NOR Boot FLASH (64 MB)
+ */
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1	/* E300 Family */
+#define CONFIG_FSL_DIU_FB	1	/* FSL DIU */
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
+
+/* video */
+#undef CONFIG_VIDEO
+
+#if defined(CONFIG_VIDEO)
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#endif
+
+/* CONFIG_PCI is defined at config time */
+
+#define CONFIG_SYS_MPC512X_CLKIN	33000000	/* in Hz */
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_SYS_IMMR			0x80000000
+#define CONFIG_SYS_DIU_ADDR		(CONFIG_SYS_IMMR+0x2100)
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000      /* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+
+/*
+ * DDR Setup - manually set all parameters as there's no SPD etc.
+ */
+#define CONFIG_SYS_DDR_SIZE		256		/* MB */
+#define CONFIG_SYS_DDR_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_MAX_RAM_SIZE		0x20000000
+
+#define CONFIG_SYS_IOCTRL_MUX_DDR	0x00000036
+
+/* DDR Controller Configuration
+ *
+ * SYS_CFG:
+ *	[31:31]	MDDRC Soft Reset:	Diabled
+ *	[30:30]	DRAM CKE pin:		Enabled
+ *	[29:29]	DRAM CLK:		Enabled
+ *	[28:28]	Command Mode:		Enabled (For initialization only)
+ *	[27:25]	DRAM Row Select:	dram_row[15:0] = magenta_address[25:10]
+ *	[24:21]	DRAM Bank Select:	dram_bank[1:0] = magenta_address[11:10]
+ *	[20:19]	Read Test:		DON'T USE
+ *	[18:18]	Self Refresh:		Enabled
+ *	[17:17]	16bit Mode:		Disabled
+ *	[16:13] Ready Delay:		2
+ *	[12:12]	Half DQS Delay:		Disabled
+ *	[11:11]	Quarter DQS Delay:	Disabled
+ *	[10:08]	Write Delay:		2
+ *	[07:07]	Early ODT:		Disabled
+ *	[06:06]	On DIE Termination:	Disabled
+ *	[05:05]	FIFO Overflow Clear:	DON'T USE here
+ *	[04:04]	FIFO Underflow Clear:	DON'T USE here
+ *	[03:03]	FIFO Overflow Pending:	DON'T USE here
+ *	[02:02]	FIFO Underlfow Pending:	DON'T USE here
+ *	[01:01]	FIFO Overlfow Enabled:	Enabled
+ *	[00:00]	FIFO Underflow Enabled:	Enabled
+ * TIME_CFG0
+ *	[31:16]	DRAM Refresh Time:	0 CSB clocks
+ *	[15:8]	DRAM Command Time:	0 CSB clocks
+ *	[07:00]	DRAM Precharge Time:	0 CSB clocks
+ * TIME_CFG1
+ *	[31:26]	DRAM tRFC:
+ *	[25:21]	DRAM tWR1:
+ *	[20:17]	DRAM tWRT1:
+ *	[16:11]	DRAM tDRR:
+ *	[10:05]	DRAM tRC:
+ *	[04:00]	DRAM tRAS:
+ * TIME_CFG2
+ *	[31:28]	DRAM tRCD:
+ *	[27:23]	DRAM tFAW:
+ *	[22:19]	DRAM tRTW1:
+ *	[18:15]	DRAM tCCD:
+ *	[14:10] DRAM tRTP:
+ *	[09:05]	DRAM tRP:
+ *	[04:00] DRAM tRPA
+ */
+#define CONFIG_SYS_MDDRC_SYS_CFG     (	(1 << 31) |	/* RST_B */ \
+					(1 << 30) |	/* CKE */ \
+					(1 << 29) |	/* CLK_ON */ \
+					(0 << 28) |	/* CMD_MODE */ \
+					(4 << 25) |	/* DRAM_ROW_SELECT */ \
+					(3 << 21) |	/* DRAM_BANK_SELECT */ \
+					(0 << 18) |	/* SELF_REF_EN */ \
+					(0 << 17) |	/* 16BIT_MODE */ \
+					(2 << 13) |	/* RDLY */ \
+					(0 << 12) |	/* HALF_DQS_DLY */ \
+					(1 << 11) |	/* QUART_DQS_DLY */ \
+					(2 <<  8) |	/* WDLY */ \
+					(0 <<  7) |	/* EARLY_ODT */ \
+					(1 <<  6) |	/* ON_DIE_TERMINATE */ \
+					(0 <<  5) |	/* FIFO_OV_CLEAR */ \
+					(0 <<  4) |	/* FIFO_UV_CLEAR */ \
+					(0 <<  1) |	/* FIFO_OV_EN */ \
+					(0 <<  0) 	/* FIFO_UV_EN */ \
+				     )
+
+#define CONFIG_SYS_MDDRC_TIME_CFG0	0x030C3D2E
+#define CONFIG_SYS_MDDRC_TIME_CFG1	0x55D81189
+#define CONFIG_SYS_MDDRC_TIME_CFG2	0x34790863
+
+#define CONFIG_SYS_DDRCMD_NOP		0x01380000
+#define CONFIG_SYS_DDRCMD_PCHG_ALL	0x01100400
+#define CONFIG_SYS_MICRON_EMR	     (	(1 << 24) |	/* CMD_REQ */ \
+					(0 << 22) |	/* DRAM_CS */ \
+					(0 << 21) |	/* DRAM_RAS */ \
+					(0 << 20) |	/* DRAM_CAS */ \
+					(0 << 19) |	/* DRAM_WEB */ \
+					(1 << 16) |	/* DRAM_BS[2:0] */ \
+					(0 << 15) |	/* */ \
+					(0 << 12) |	/* A12->out */ \
+					(0 << 11) |	/* A11->RDQS */ \
+					(0 << 10) |	/* A10->DQS# */ \
+					(0 <<  7) |	/* OCD program */ \
+					(0 <<  6) |	/* Rtt1 */ \
+					(0 <<  3) |	/* posted CAS# */ \
+					(0 <<  2) |	/* Rtt0 */ \
+					(1 <<  1) |	/* ODS */ \
+					(0 <<  0)	/* DLL */ \
+				     )
+#define CONFIG_SYS_MICRON_EMR2		0x01020000
+#define CONFIG_SYS_MICRON_EMR3		0x01030000
+#define CONFIG_SYS_DDRCMD_RFSH		0x01080000
+#define CONFIG_SYS_MICRON_INIT_DEV_OP	0x01000432
+#define CONFIG_SYS_MICRON_EMR_OCD    (	(1 << 24) |	/* CMD_REQ */ \
+					(0 << 22) |	/* DRAM_CS */ \
+					(0 << 21) |	/* DRAM_RAS */ \
+					(0 << 20) |	/* DRAM_CAS */ \
+					(0 << 19) |	/* DRAM_WEB */ \
+					(1 << 16) |	/* DRAM_BS[2:0] */ \
+					(0 << 15) |	/* */ \
+					(0 << 12) |	/* A12->out */ \
+					(0 << 11) |	/* A11->RDQS */ \
+					(1 << 10) |	/* A10->DQS# */ \
+					(7 <<  7) |	/* OCD program */ \
+					(0 <<  6) |	/* Rtt1 */ \
+					(0 <<  3) |	/* posted CAS# */ \
+					(1 <<  2) |	/* Rtt0 */ \
+					(0 <<  1) |	/* ODS (Output Drive Strength) */ \
+					(0 <<  0)	/* DLL */ \
+				     )
+
+/*
+ * Backward compatible definitions,
+ * so we do not have to change arch/powerpc/cpu/mpc512x/fixed_sdram.c
+ */
+#define	CONFIG_SYS_DDRCMD_EM2		(CONFIG_SYS_MICRON_EMR2)
+#define CONFIG_SYS_DDRCMD_EM3		(CONFIG_SYS_MICRON_EMR3)
+#define CONFIG_SYS_DDRCMD_EN_DLL	(CONFIG_SYS_MICRON_EMR)
+#define CONFIG_SYS_DDRCMD_OCD_DEFAULT	(CONFIG_SYS_MICRON_EMR_OCD)
+
+/* DDR Priority Manager Configuration */
+#define CONFIG_SYS_MDDRCGRP_PM_CFG1	0x00077777
+#define CONFIG_SYS_MDDRCGRP_PM_CFG2	0x00000000
+#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG	0x00000001
+#define CONFIG_SYS_MDDRCGRP_LUT0_MU	0xFFEEDDCC
+#define CONFIG_SYS_MDDRCGRP_LUT0_ML	0xBBAAAAAA
+#define CONFIG_SYS_MDDRCGRP_LUT1_MU	0x66666666
+#define CONFIG_SYS_MDDRCGRP_LUT1_ML	0x55555555
+#define CONFIG_SYS_MDDRCGRP_LUT2_MU	0x44444444
+#define CONFIG_SYS_MDDRCGRP_LUT2_ML	0x44444444
+#define CONFIG_SYS_MDDRCGRP_LUT3_MU	0x55555555
+#define CONFIG_SYS_MDDRCGRP_LUT3_ML	0x55555558
+#define CONFIG_SYS_MDDRCGRP_LUT4_MU	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT4_ML	0x11111122
+#define CONFIG_SYS_MDDRCGRP_LUT0_AU	0xaaaaaaaa
+#define CONFIG_SYS_MDDRCGRP_LUT0_AL	0xaaaaaaaa
+#define CONFIG_SYS_MDDRCGRP_LUT1_AU	0x66666666
+#define CONFIG_SYS_MDDRCGRP_LUT1_AL	0x66666666
+#define CONFIG_SYS_MDDRCGRP_LUT2_AU	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT2_AL	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT3_AU	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT3_AL	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT4_AU	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT4_AL	0x11111111
+
+/*
+ * NOR FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_CFI				/* use the CFI code */
+#define CONFIG_FLASH_CFI_DRIVER				/* use the CFI driver */
+#define CONFIG_SYS_FLASH_BASE		0xF8000000	/* start of FLASH */
+#define CONFIG_SYS_FLASH_SIZE		0x08000000	/* max flash size */
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_MAX_FLASH_SECT	1024		/* max sectors */
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+
+/*
+ * NAND FLASH support
+ * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only)
+ */
+#define CONFIG_CMD_NAND					/* enable NAND support */
+#define CONFIG_JFFS2_NAND				/* with JFFS2 on it */
+#define CONFIG_NAND_MPC5121_NFC
+#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+
+/*
+ * Configuration parameters for MPC5121 NAND driver
+ */
+#define CONFIG_FSL_NFC_WIDTH		1
+#define CONFIG_FSL_NFC_WRITE_SIZE	2048
+#define CONFIG_FSL_NFC_SPARE_SIZE	64
+#define CONFIG_FSL_NFC_CHIPS		CONFIG_SYS_MAX_NAND_DEVICE
+
+#define CONFIG_SYS_SRAM_BASE		0x30000000
+#define CONFIG_SYS_SRAM_SIZE		0x00020000	/* 128 KB */
+
+/* Make two SRAM regions contiguous */
+#define CONFIG_SYS_ARIA_SRAM_BASE	(CONFIG_SYS_SRAM_BASE + \
+					 CONFIG_SYS_SRAM_SIZE)
+#define CONFIG_SYS_ARIA_SRAM_SIZE	0x00100000	/* reserve 1MB-window */
+#define CONFIG_SYS_CS6_START		CONFIG_SYS_ARIA_SRAM_BASE
+#define CONFIG_SYS_CS6_SIZE		CONFIG_SYS_ARIA_SRAM_SIZE
+
+#define CONFIG_SYS_ARIA_FPGA_BASE	(CONFIG_SYS_ARIA_SRAM_BASE + \
+					 CONFIG_SYS_ARIA_SRAM_SIZE)
+#define CONFIG_SYS_ARIA_FPGA_SIZE	0x20000		/* 128 KB */
+
+#define CONFIG_SYS_CS2_START		CONFIG_SYS_ARIA_FPGA_BASE
+#define CONFIG_SYS_CS2_SIZE		CONFIG_SYS_ARIA_FPGA_SIZE
+
+#define CONFIG_SYS_CS0_CFG		0x05059150
+#define CONFIG_SYS_CS2_CFG		(	(5 << 24) | \
+						(5 << 16) | \
+						(1 << 15) | \
+						(0 << 14) | \
+						(0 << 13) | \
+						(1 << 12) | \
+						(0 << 10) | \
+						(3 <<  8) | /* 32 bit */ \
+						(0 <<  7) | \
+						(1 <<  6) | \
+						(1 <<  4) | \
+						(0 <<  3) | \
+						(0 <<  2) | \
+						(0 <<  1) | \
+						(0 <<  0)   \
+					)
+#define CONFIG_SYS_CS6_CFG		0x05059150
+
+/* Use alternative CS timing for CS0 and CS2 */
+#define CONFIG_SYS_CS_ALETIMING	0x00000005
+
+/* Use SRAM for initial stack */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_SRAM_BASE
+#define CONFIG_SYS_INIT_RAM_SIZE		CONFIG_SYS_SRAM_SIZE
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(384 * 1024)
+
+#ifdef	CONFIG_FSL_DIU_FB
+#define CONFIG_SYS_MALLOC_LEN		(6 * 1024 * 1024)
+#else
+#define CONFIG_SYS_MALLOC_LEN		(512 * 1024)
+#endif
+
+/* FPGA */
+#define CONFIG_ARIA_FPGA		1
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX		1
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE		3	/* console on PSC3 */
+#define CONFIG_SYS_PSC3
+#if CONFIG_PSC_CONSOLE != 3
+#error CONFIG_PSC_CONSOLE must be 3
+#endif
+
+#define CONFIG_BAUDRATE			115200	/* ... at 115200 bps */
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CONSOLE_FIFO_TX_SIZE		FIFOC_PSC3_TX_SIZE
+#define CONSOLE_FIFO_TX_ADDR		FIFOC_PSC3_TX_ADDR
+#define CONSOLE_FIFO_RX_SIZE		FIFOC_PSC3_RX_SIZE
+#define CONSOLE_FIFO_RX_ADDR		FIFOC_PSC3_RX_ADDR
+
+#define CONFIG_CMDLINE_EDITING		1	/* command line history */
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef  CONFIG_SYS_HUSH_PARSER
+#endif
+
+/*
+ * PCI
+ */
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+
+#define CONFIG_SYS_PCI_MEM_BASE		0xA0000000
+#define CONFIG_SYS_PCI_MEM_PHYS		CONFIG_SYS_PCI_MEM_BASE
+#define CONFIG_SYS_PCI_MEM_SIZE		0x10000000	/* 256M */
+#define CONFIG_SYS_PCI_MMIO_BASE	(CONFIG_SYS_PCI_MEM_BASE + \
+					 CONFIG_SYS_PCI_MEM_SIZE)
+#define CONFIG_SYS_PCI_MMIO_PHYS	CONFIG_SYS_PCI_MMIO_BASE
+#define CONFIG_SYS_PCI_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI_IO_PHYS		0x84000000
+#define CONFIG_SYS_PCI_IO_SIZE		0x01000000	/* 16M */
+
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+
+#endif
+
+/* I2C */
+#define CONFIG_HARD_I2C			/* I2C with hardware support */
+#define CONFIG_I2C_MULTI_BUS
+
+/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#if 0
+#define CONFIG_SYS_I2C_NOPROBES	{{0,0x69}}	/* Don't probe these addrs */
+#endif
+
+/*
+ * IIM - IC Identification Module
+ */
+#undef CONFIG_FSL_IIM
+
+/*
+ * EEPROM configuration for Atmel AT24C32A-10TQ-2.7:
+ * 16-bit addresses, 10ms write delay, 32-Byte Page Write Mode
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC512x_FEC		1
+#define CONFIG_PHY_ADDR			0x17
+#define CONFIG_MII			1	/* MII PHY management */
+#define CONFIG_FEC_AN_TIMEOUT		1
+#define CONFIG_HAS_ETH0
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+/* This has to be a multiple of the flash sector size */
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_MONITOR_BASE + \
+					 CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_SECT_SIZE		0x20000	/* one sector (256K) */
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND		(CONFIG_ENV_ADDR + \
+					 CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND		(CONFIG_ENV_SIZE)
+
+#define CONFIG_LOADS_ECHO		1
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_FUSE
+#define CONFIG_CMD_I2C
+#undef CONFIG_CMD_IDE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+
+#if defined(CONFIG_PCI)
+#define CONFIG_CMD_PCI
+#endif
+
+#if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2)
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION
+#define CONFIG_ISO_PARTITION
+#endif /* defined(CONFIG_CMD_IDE) */
+
+/*
+ * Dynamic MTD partition support
+ */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
+#define MTDIDS_DEFAULT		"nor0=f8000000.flash,nand0=mpc5121.nand"
+
+/*
+ * NOR flash layout:
+ *
+ * F8000000 - FEAFFFFF	107 MiB		User Data
+ * FEB00000 - FFAFFFFF	 16 MiB		Root File System
+ * FFB00000 - FFFEFFFF	  4 MiB		Linux Kernel
+ * FFF00000 - FFFBFFFF	768 KiB		U-Boot (up to 512 KiB) and 2 x * env
+ * FFFC0000 - FFFFFFFF	256 KiB		Device Tree
+ *
+ * NAND flash layout: one big partition
+ */
+#define MTDPARTS_DEFAULT	"mtdparts=f8000000.flash:107m(user),"	\
+						"16m(rootfs),"		\
+						"4m(kernel),"		\
+						"768k(u-boot),"		\
+						"256k(dtb);"		\
+					"mpc5121.nand:-(data)"
+
+/*
+ * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
+ * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE
+ * is set to 0xFFFF, watchdog timeouts after about 64s. For details
+ * refer to chapter 36 of the MPC5121e Reference Manual.
+ */
+/* #define CONFIG_WATCHDOG */		/* enable watchdog */
+#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
+
+ /*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+#ifdef CONFIG_CMD_KGDB
+# define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+# define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
+				 sizeof(CONFIG_SYS_PROMPT) + 16)
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS	32
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)
+
+/* Cache Configuration */
+#define CONFIG_SYS_DCACHE_SIZE		32768
+#define CONFIG_SYS_CACHELINE_SIZE	32
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of 32 */
+#endif
+
+#define CONFIG_SYS_HID0_INIT		0x000000000
+#define CONFIG_SYS_HID0_FINAL		(HID0_ENABLE_MACHINE_CHECK | \
+					 HID0_ICE)
+#define CONFIG_SYS_HID2	HID2_HBE
+
+#define CONFIG_HIGH_BATS		1	/* High BATs supported */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE		230400	/* speed of kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_TIMESTAMP
+
+#define CONFIG_HOSTNAME			aria
+#define CONFIG_BOOTFILE			"aria/uImage"
+#define CONFIG_ROOTPATH			"/opt/eldk/ppc_6xx"
+
+#define CONFIG_LOADADDR			400000	/* default load addr */
+
+#define CONFIG_BOOTDELAY	5	/* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS			/* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+	"echo"
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"u-boot_addr_r=200000\0"					\
+	"kernel_addr_r=600000\0"					\
+	"fdt_addr_r=880000\0"						\
+	"ramdisk_addr_r=900000\0"					\
+	"u-boot_addr=FFF00000\0"					\
+	"kernel_addr=FFB00000\0"					\
+	"fdt_addr=FFFC0000\0"						\
+	"ramdisk_addr=FEB00000\0"					\
+	"ramdiskfile=aria/uRamdisk\0"				\
+	"u-boot=aria/u-boot.bin\0"					\
+	"fdtfile=aria/aria.dtb\0"					\
+	"netdev=eth0\0"							\
+	"consdev=ttyPSC0\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} "				\
+		"console=${consdev},${baudrate}\0"			\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
+		"tftp ${fdt_addr_r} ${fdtfile};"			\
+		"run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
+	"net_self=tftp ${kernel_addr_r} ${bootfile};"			\
+		"tftp ${ramdisk_addr_r} ${ramdiskfile};"		\
+		"tftp ${fdt_addr_r} ${fdtfile};"			\
+		"run ramargs addip addtty;"				\
+		"bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
+	"load=tftp ${u-boot_addr_r} ${u-boot}\0"			\
+	"update=protect off ${u-boot_addr} +${filesize};"		\
+		"era ${u-boot_addr} +${filesize};"			\
+		"cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0"	\
+	"upd=run load update\0"						\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES	1
+
+#define OF_CPU			"PowerPC,5121@0"
+#define OF_SOC_COMPAT		"fsl,mpc5121-immr"
+#define OF_TBCLK		(bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH		"/soc@80000000/serial@11300"
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff
+ *-----------------------------------------------------------------------
+ */
+
+#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for IDE not supported	*/
+
+#define CONFIG_IDE_RESET		/* reset for IDE supported	*/
+#define CONFIG_IDE_PREINIT
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	2	/* 1 drive per IDE bus	*/
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_BASE_ADDR	get_pata_base()
+
+/* Offset for data I/O			RefMan MPC5121EE Table 28-10	*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x00A0)
+
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers	RefMan MPC5121EE Table 28-23	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x00D8)
+
+/* Interval between registers	*/
+#define CONFIG_SYS_ATA_STRIDE		4
+
+#define ATA_BASE_ADDR			get_pata_base()
+
+/*
+ * Control register bit definitions
+ */
+#define FSL_ATA_CTRL_FIFO_RST_B		0x80000000
+#define FSL_ATA_CTRL_ATA_RST_B		0x40000000
+#define FSL_ATA_CTRL_FIFO_TX_EN		0x20000000
+#define FSL_ATA_CTRL_FIFO_RCV_EN	0x10000000
+#define FSL_ATA_CTRL_DMA_PENDING	0x08000000
+#define FSL_ATA_CTRL_DMA_ULTRA		0x04000000
+#define FSL_ATA_CTRL_DMA_WRITE		0x02000000
+#define FSL_ATA_CTRL_IORDY_EN		0x01000000
+
+/* Clocks in use */
+#define SCCR1_CLOCKS_EN	(CLOCK_SCCR1_CFG_EN |				\
+			 CLOCK_SCCR1_LPC_EN |				\
+			 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |	\
+			 CLOCK_SCCR1_PSCFIFO_EN |			\
+			 CLOCK_SCCR1_DDR_EN |				\
+			 CLOCK_SCCR1_FEC_EN |				\
+			 CLOCK_SCCR1_NFC_EN |				\
+			 CLOCK_SCCR1_PATA_EN |				\
+			 CLOCK_SCCR1_PCI_EN |				\
+			 CLOCK_SCCR1_TPR_EN)
+
+#define SCCR2_CLOCKS_EN	(CLOCK_SCCR2_MEM_EN |		\
+			 CLOCK_SCCR2_SPDIF_EN |		\
+			 CLOCK_SCCR2_DIU_EN |		\
+			 CLOCK_SCCR2_I2C_EN)
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/armadillo-800eva.h b/qemu/roms/u-boot/include/configs/armadillo-800eva.h
new file mode 100644
index 000000000..17a2da034
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/armadillo-800eva.h
@@ -0,0 +1,143 @@
+/*
+ * Configuation settings for the bonito board
+ *
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ARMADILLO_800EVA_H
+#define __ARMADILLO_800EVA_H
+
+#undef DEBUG
+#define CONFIG_ARMV7
+#define CONFIG_R8A7740
+#define CONFIG_RMOBILE
+#define CONFIG_RMOBILE_BOARD_STRING "Armadillo-800EVA Board\n"
+#define CONFIG_SH_GPIO_PFC
+
+#include <asm/arch/rmobile.h>
+
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_DFL
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_BOOTZ
+
+#define CONFIG_OF_LIBFDT
+#define BOARD_LATE_INIT
+
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTARGS		""
+
+#define CONFIG_VERSION_VARIABLE
+#undef	CONFIG_SHOW_BOOT_PROGRESS
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_USE_ARCH_MEMSET
+#define CONFIG_USE_ARCH_MEMCPY
+#define CONFIG_TMU_TIMER
+#define CONFIG_SYS_DCACHE_OFF
+
+/* STACK */
+#define CONFIG_SYS_INIT_SP_ADDR		0xE8083000
+#define STACK_AREA_SIZE				0xC000
+#define LOW_LEVEL_MERAM_STACK	\
+		(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
+
+/* MEMORY */
+#define ARMADILLO_800EVA_SDRAM_BASE	0x40000000
+#define ARMADILLO_800EVA_SDRAM_SIZE	(512 * 1024 * 1024)
+
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_PBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE		512
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE
+#define CONFIG_CONS_SCIF1
+#define SCIF0_BASE		0xe6c40000
+#define SCIF1_BASE		0xe6c50000
+#define SCIF2_BASE		0xe6c60000
+#define SCIF4_BASE		0xe6c80000
+#define	CONFIG_SCIF_A
+#undef	CONFIG_SYS_CONSOLE_INFO_QUIET
+#undef	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#undef	CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+
+#define CONFIG_SYS_MEMTEST_START	(ARMADILLO_800EVA_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
+					 504 * 1024 * 1024)
+#undef	CONFIG_SYS_ALT_MEMTEST
+#undef	CONFIG_SYS_MEMTEST_SCRATCH
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE
+
+#define CONFIG_SYS_SDRAM_BASE		(ARMADILLO_800EVA_SDRAM_BASE)
+#define CONFIG_SYS_SDRAM_SIZE		(ARMADILLO_800EVA_SDRAM_SIZE)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + \
+					 64 * 1024 * 1024)
+#define CONFIG_NR_DRAM_BANKS		1
+
+#define CONFIG_SYS_MONITOR_BASE		0x00000000
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(1 * 1024 * 1024)
+#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
+#define CONFIG_SYS_TEXT_BASE	0xE80C0000
+
+/* FLASH */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_BASE		0x00000000
+#define CONFIG_SYS_MAX_FLASH_SECT	512
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ (CONFIG_SYS_FLASH_BASE) }
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	3000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	3000
+#define CONFIG_SYS_FLASH_LOCK_TOUT	3000
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	3000
+
+/* ENV setting */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE	1
+#define CONFIG_ENV_SECT_SIZE	(128 * 1024)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + \
+				 CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_OFFSET	(CONFIG_ENV_ADDR)
+#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
+
+/* SH Ether */
+#define	CONFIG_NET_MULTI
+#define CONFIG_SH_ETHER
+#define CONFIG_SH_ETHER_USE_PORT	0
+#define CONFIG_SH_ETHER_PHY_ADDR	0x0
+#define CONFIG_SH_ETHER_BASE_ADDR	0xe9a00000
+#define CONFIG_SH_ETHER_SH7734_MII	(0x01)
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_SMSC
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+
+/* Board Clock */
+#define CONFIG_SYS_CLK_FREQ	50000000
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_TMU_CLK_DIV	4
+
+#endif	/* __ARMADILLO_800EVA_H */
diff --git a/qemu/roms/u-boot/include/configs/arndale.h b/qemu/roms/u-boot/include/configs/arndale.h
new file mode 100644
index 000000000..515facfd6
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/arndale.h
@@ -0,0 +1,252 @@
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Configuration settings for the SAMSUNG Arndale board.
+ */
+
+#ifndef __CONFIG_ARNDALE_H
+#define __CONFIG_ARNDALE_H
+
+/* High Level Configuration Options */
+#define CONFIG_SAMSUNG			/* in a SAMSUNG core */
+#define CONFIG_S5P			/* S5P Family */
+#define CONFIG_EXYNOS5			/* which is in a Exynos5 Family */
+#define CONFIG_EXYNOS5250
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
+/* Allow tracing to be enabled */
+#define CONFIG_TRACE
+#define CONFIG_CMD_TRACE
+#define CONFIG_TRACE_BUFFER_SIZE	(16 << 20)
+#define CONFIG_TRACE_EARLY_SIZE		(8 << 20)
+#define CONFIG_TRACE_EARLY
+#define CONFIG_TRACE_EARLY_ADDR		0x50000000
+
+/* Keep L2 Cache Disabled */
+#define CONFIG_SYS_DCACHE_OFF
+
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CONFIG_SYS_TEXT_BASE		0x43E00000
+
+/* input clock of PLL: SMDK5250 has 24MHz input clock */
+#define CONFIG_SYS_CLK_FREQ		24000000
+
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_EDITING
+
+/* Power Down Modes */
+#define S5P_CHECK_SLEEP			0x00000BAD
+#define S5P_CHECK_DIDLE			0xBAD00000
+#define S5P_CHECK_LPA			0xABAD0000
+
+/* Offset for inform registers */
+#define INFORM0_OFFSET			0x800
+#define INFORM1_OFFSET			0x804
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (4 << 20))
+
+/* select serial console configuration */
+#define CONFIG_BAUDRATE			115200
+#define EXYNOS5_DEFAULT_UART_OFFSET	0x010000
+#define CONFIG_SILENT_CONSOLE
+
+/* Console configuration */
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define EXYNOS_DEVICE_SETTINGS \
+		"stdin=serial\0" \
+		"stdout=serial\0" \
+		"stderr=serial\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	EXYNOS_DEVICE_SETTINGS
+
+/* SD/MMC configuration */
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_SDHCI
+#define CONFIG_S5P_SDHCI
+#define CONFIG_DWMMC
+#define CONFIG_EXYNOS_DWMMC
+#define CONFIG_SUPPORT_EMMC_BOOT
+#define CONFIG_BOUNCE_BUFFER
+
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* PWM */
+#define CONFIG_PWM
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Command definition*/
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_HASH
+
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+/* USB */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_EXYNOS
+#define CONFIG_USB_STORAGE
+
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	3
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+
+/* MMC SPL */
+#define CONFIG_EXYNOS_SPL
+#define CONFIG_SPL
+#define COPY_BL2_FNPTR_ADDR	0x02020030
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+
+/* specific .lds file */
+#define CONFIG_SPL_LDSCRIPT	"board/samsung/common/exynos-uboot-spl.lds"
+#define CONFIG_SPL_TEXT_BASE	0x02023400
+#define CONFIG_SPL_MAX_FOOTPRINT	(14 * 1024)
+
+#define CONFIG_BOOTCOMMAND	"mmc read 40007000 451 2000; bootm 40007000"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser	*/
+#define CONFIG_SYS_PROMPT		"ARNDALE # "
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE		384	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC2,115200n8\0"
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5E00000)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x3E00000)
+
+#define CONFIG_RD_LVL
+
+#define CONFIG_NR_DRAM_BANKS	8
+#define SDRAM_BANK_SIZE		(256UL << 20UL)	/* 256 MB */
+#define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_1_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_2		(CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
+#define PHYS_SDRAM_2_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_3		(CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_3_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_4		(CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_4_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_5		(CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_5_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_6		(CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_6_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_7		(CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_7_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_8		(CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_8_SIZE	SDRAM_BANK_SIZE
+
+#define CONFIG_SYS_MONITOR_BASE	0x00000000
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+#undef CONFIG_CMD_IMLS
+#define CONFIG_IDENT_STRING		" for ARNDALE"
+
+#define CONFIG_SYS_MMC_ENV_DEV		0
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SECURE_BL1_ONLY
+
+/* Secure FW size configuration */
+#ifdef	CONFIG_SECURE_BL1_ONLY
+#define	CONFIG_SEC_FW_SIZE		(8 << 10)	/* 8KB */
+#else
+#define	CONFIG_SEC_FW_SIZE		0
+#endif
+
+/* Configuration of BL1, BL2, ENV Blocks on mmc */
+#define CONFIG_RES_BLOCK_SIZE	(512)
+#define CONFIG_BL1_SIZE		(16 << 10) /*16 K reserved for BL1*/
+#define	CONFIG_BL2_SIZE		(512UL << 10UL)	/* 512 KB */
+#define CONFIG_ENV_SIZE		(16 << 10)	/* 16 KB */
+
+#define CONFIG_BL1_OFFSET	(CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
+#define CONFIG_BL2_OFFSET	(CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
+#define CONFIG_ENV_OFFSET	(CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE)
+
+/* U-boot copy size from boot Media to DRAM.*/
+#define BL2_START_OFFSET	(CONFIG_BL2_OFFSET/512)
+#define BL2_SIZE_BLOC_COUNT	(CONFIG_BL2_SIZE/512)
+
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+#define CONFIG_CMD_PART
+#define CONFIG_PARTITION_UUIDS
+
+
+#define CONFIG_IRAM_STACK	0x02050000
+
+#define CONFIG_SYS_INIT_SP_ADDR	CONFIG_IRAM_STACK
+
+/* I2C */
+#define CONFIG_SYS_I2C_INIT_BOARD
+#define CONFIG_SYS_I2C
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C_S3C24X0_SPEED	100000		/* 100 Kbps */
+#define CONFIG_SYS_I2C_S3C24X0
+#define CONFIG_MAX_I2C_NUM	8
+#define CONFIG_SYS_I2C_S3C24X0_SLAVE    0x0
+#define CONFIG_I2C_EDID
+
+/* PMIC */
+#define CONFIG_PMIC
+#define CONFIG_PMIC_I2C
+#define CONFIG_PMIC_MAX77686
+
+#define CONFIG_DEFAULT_DEVICE_TREE	exynos5250-arndale
+
+/* Ethernet Controllor Driver */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_BASE		0x5000000
+#define CONFIG_SMC911X_16_BIT
+#define CONFIG_ENV_SROM_BANK		1
+#endif /*CONFIG_CMD_NET*/
+
+/* Enable PXE Support */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_CMD_PXE
+#define CONFIG_MENU
+#endif
+
+/* Enable devicetree support */
+#define CONFIG_OF_LIBFDT
+
+/* Enable Time Command */
+#define CONFIG_CMD_TIME
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/aspenite.h b/qemu/roms/u-boot/include/configs/aspenite.h
new file mode 100644
index 000000000..727b14a6c
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/aspenite.h
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_ASPENITE_H
+#define __CONFIG_ASPENITE_H
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING	"\nMarvell-Aspenite DB"
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_SHEEVA_88SV331xV5	1	/* CPU Core subversion */
+#define CONFIG_ARMADA100		1	/* SOC Family Name */
+#define CONFIG_ARMADA168		1	/* SOC Used on this Board */
+#define CONFIG_MACH_ASPENITE			/* Machine type */
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+
+/*
+ * There is no internal RAM in ARMADA100, using DRAM
+ * TBD: dcache to be used for this
+ */
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE - 0x00200000)
+#define CONFIG_NR_DRAM_BANKS_MAX	2
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_I2C
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+#undef CONFIG_ARCH_MISC_INIT
+
+/*
+ * Environment variables configurations
+ */
+#define CONFIG_ENV_IS_NOWHERE	1	/* if env in SDRAM */
+#define CONFIG_ENV_SIZE	0x20000	/* 64k */
+
+#endif	/* __CONFIG_ASPENITE_H */
diff --git a/qemu/roms/u-boot/include/configs/astro_mcf5373l.h b/qemu/roms/u-boot/include/configs/astro_mcf5373l.h
new file mode 100644
index 000000000..d875753a6
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/astro_mcf5373l.h
@@ -0,0 +1,377 @@
+/*
+ * Configuration settings for the Sentec Cobra Board.
+ *
+ * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * configuration for ASTRO "Urmel" board.
+ * Originating from Cobra5272 configuration, messed up by
+ * Wolfgang Wegner <w.wegner@astro-kom.de>
+ * Please do not bother the original author with bug reports
+ * concerning this file.
+ */
+
+#ifndef _CONFIG_ASTRO_MCF5373L_H
+#define _CONFIG_ASTRO_MCF5373L_H
+
+#include <linux/stringify.h>
+
+/*
+ * set the card type to actually compile for; either of
+ * the possibilities listed below has to be used!
+ */
+#define CONFIG_ASTRO_V532	1
+
+#if CONFIG_ASTRO_V532
+#define ASTRO_ID	0xF8
+#elif CONFIG_ASTRO_V512
+#define ASTRO_ID	0xFA
+#elif CONFIG_ASTRO_TWIN7S2
+#define ASTRO_ID	0xF9
+#elif CONFIG_ASTRO_V912
+#define ASTRO_ID	0xFC
+#elif CONFIG_ASTRO_COFDMDUOS2
+#define ASTRO_ID	0xFB
+#else
+#error No card type defined!
+#endif
+
+/*
+ * Define processor
+ * possible values for Urmel board: only Coldfire M5373 processor supported
+ * (please do not change)
+ */
+
+/* it seems not clear yet which processor defines we should use */
+#define CONFIG_MCF537x			/* define processor family */
+#define CONFIG_MCF532x			/* define processor family */
+#define CONFIG_M5373			/* define processor type */
+#define CONFIG_ASTRO5373L		/* define board type */
+
+/* Command line configuration */
+#include <config_cmd_default.h>
+
+/*
+ * CONFIG_RAM defines if u-boot is loaded via BDM (or started from
+ * a different bootloader that has already performed RAM setup) or
+ * started directly from flash, which is the regular case for production
+ * boards.
+ */
+#ifdef CONFIG_RAM
+#define CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_SYS_TEXT_BASE		0x40020000
+#define ENABLE_JFFS	0
+#else
+#define CONFIG_SYS_TEXT_BASE		0x00000000
+#define ENABLE_JFFS	1
+#endif
+
+/* Define which commmands should be available at u-boot command prompt */
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_XIMG
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#if ENABLE_JFFS
+#define CONFIG_CMD_JFFS2
+#endif
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_FPGA
+#define CONFIG_CMDLINE_EDITING
+
+#define CONFIG_SYS_HUSH_PARSER
+
+#define CONFIG_MCFRTC
+#undef RTC_DEBUG
+
+/* Timer */
+#define CONFIG_MCFTMR
+#undef CONFIG_MCFPIT
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	80000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x58000
+#define CONFIG_SYS_IMMR			CONFIG_SYS_MBAR
+
+/*
+ * Defines processor clock - important for correct timings concerning serial
+ * interface etc.
+ */
+
+#define CONFIG_SYS_CLK			80000000
+#define CONFIG_SYS_CPU_CLK		(CONFIG_SYS_CLK * 3)
+#define CONFIG_SYS_SDRAM_SIZE		32		/* SDRAM size in MB */
+
+#define CONFIG_SYS_CORE_SRAM_SIZE	0x8000
+#define CONFIG_SYS_CORE_SRAM		0x80000000
+
+#define CONFIG_SYS_UNIFY_CACHE
+
+/*
+ * Define baudrate for UART1 (console output, tftp, ...)
+ * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud
+ * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected
+ * in u-boot command interface
+ */
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT		(2)
+#define CONFIG_SYS_UART2_ALT3_GPIO
+
+/*
+ * Watchdog configuration; Watchdog is disabled for running from RAM
+ * and set to highest possible value else. Beware there is no check
+ * in the watchdog code to validate the timeout value set here!
+ */
+
+#ifndef CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT 3355	/* timeout in milliseconds */
+#endif
+
+/*
+ * Configuration for environment
+ * Environment is located in the last sector of the flash
+ */
+
+#ifndef CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_ENV_OFFSET		0x1FF8000
+#define CONFIG_ENV_SECT_SIZE		0x8000
+#define CONFIG_ENV_IS_IN_FLASH		1
+#else
+/*
+ * environment in RAM - This is used to use a single PC-based application
+ * to load an image, load U-Boot, load an environment and then start U-Boot
+ * to execute the commands from the environment. Feedback is done via setting
+ * and reading memory locations.
+ */
+#define CONFIG_ENV_ADDR		0x40060000
+#define CONFIG_ENV_SECT_SIZE	0x8000
+#define CONFIG_ENV_IS_IN_FLASH	1
+#endif
+
+/* here we put our FPGA configuration... */
+#define CONFIG_MISC_INIT_R	1
+
+/* Define user parameters that have to be customized most likely */
+
+/* AUTOBOOT settings - booting images automatically by u-boot after power on */
+
+/*
+ * used for autoboot, delay in seconds u-boot will wait before starting
+ * defined (auto-)boot command, setting to -1 disables delay, setting to
+ * 0 will too prevent access to u-boot command interface: u-boot then has
+ * to be reflashed
+ * beware - watchdog is not serviced during autoboot delay time!
+ */
+#ifdef CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_BOOTDELAY	1
+#else
+#define CONFIG_BOOTDELAY	1
+#endif
+
+/*
+ * The following settings will be contained in the environment block ; if you
+ * want to use a neutral environment all those settings can be manually set in
+ * u-boot: 'set' command
+ */
+
+#define CONFIG_EXTRA_ENV_SETTINGS			\
+	"loaderversion=11\0"				\
+	"card_id="__stringify(ASTRO_ID)"\0"			\
+	"alterafile=0\0"				\
+	"xilinxfile=0\0"				\
+	"xilinxload=imxtract 0x540000 $xilinxfile 0x41000000&&"\
+		"fpga load 0 0x41000000 $filesize\0" \
+	"alteraload=imxtract 0x6c0000 $alterafile 0x41000000&&"\
+		"fpga load 1 0x41000000 $filesize\0" \
+	"env_default=1\0"				\
+	"env_check=if test $env_default -eq 1;"\
+		" then setenv env_default 0;saveenv;fi\0"
+
+/*
+ * "update" is a non-standard command that has to be supplied
+ * by external update.c; This is not included in mainline because
+ * it needs non-blocking CFI routines.
+ */
+#ifdef CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_BOOTCOMMAND	""	/* no autoboot in this case */
+#else
+#if CONFIG_ASTRO_V532
+#define CONFIG_BOOTCOMMAND	"protect off 0x80000 0x1ffffff;run env_check;"\
+				"run xilinxload&&run alteraload&&bootm 0x80000;"\
+				"update;reset"
+#else
+#define CONFIG_BOOTCOMMAND	"protect off 0x80000 0x1ffffff;run env_check;"\
+				"run xilinxload&&bootm 0x80000;update;reset"
+#endif
+#endif
+
+/* default bootargs that are considered during boot */
+#define CONFIG_BOOTARGS		" console=ttyS2,115200 rootfstype=romfs"\
+				" loaderversion=$loaderversion"
+
+#define CONFIG_SYS_PROMPT	"URMEL > "
+
+/* default RAM address for user programs */
+#define CONFIG_SYS_LOAD_ADDR	0x20000
+
+#define CONFIG_SYS_LONGHELP
+
+#if (CONFIG_COMMANDS & CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024
+#else
+#define CONFIG_SYS_CBSIZE		256
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+#define CONFIG_FPGA_COUNT	1
+#define CONFIG_FPGA
+#define	CONFIG_FPGA_XILINX
+#define	CONFIG_FPGA_SPARTAN3
+#define CONFIG_FPGA_ALTERA
+#define CONFIG_FPGA_CYCLON2
+#define CONFIG_SYS_FPGA_PROG_FEEDBACK
+#define CONFIG_SYS_FPGA_WAIT		1000
+
+/* End of user parameters to be customized */
+
+/* Defines memory range for test */
+
+#define CONFIG_SYS_MEMTEST_START	0x40020000
+#define CONFIG_SYS_MEMTEST_END		0x41ffffff
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/* Base register address */
+
+#define CONFIG_SYS_MBAR		0xFC000000	/* Register Base Addrs */
+
+/* System Conf. Reg. & System Protection Reg. */
+
+#define CONFIG_SYS_SCR		0x0003;
+#define CONFIG_SYS_SPR		0xffff;
+
+/*
+ * Definitions for initial stack pointer and data area (in internal SRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
+#define CONFIG_SYS_INIT_RAM_SIZE		0x8000
+#define CONFIG_SYS_INIT_RAM_CTRL	0x221
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * for MCF5373, the allowable range is 0x40000000 to 0x7FF00000
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+
+/*
+ * Chipselect bank definitions
+ *
+ * CS0 - Flash 32MB (first 16MB)
+ * CS1 - Flash 32MB (second half)
+ * CS2 - FPGA
+ * CS3 - FPGA
+ * CS4 - unused
+ * CS5 - unused
+ */
+#define CONFIG_SYS_CS0_BASE		0
+#define CONFIG_SYS_CS0_MASK		0x00ff0001
+#define CONFIG_SYS_CS0_CTRL		0x00001fc0
+
+#define CONFIG_SYS_CS1_BASE		0x01000000
+#define CONFIG_SYS_CS1_MASK		0x00ff0001
+#define CONFIG_SYS_CS1_CTRL		0x00001fc0
+
+#define CONFIG_SYS_CS2_BASE		0x20000000
+#define CONFIG_SYS_CS2_MASK		0x00ff0001
+#define CONFIG_SYS_CS2_CTRL		0x0000fec0
+
+#define CONFIG_SYS_CS3_BASE		0x21000000
+#define CONFIG_SYS_CS3_MASK		0x00ff0001
+#define CONFIG_SYS_CS3_CTRL		0x0000fec0
+
+#define CONFIG_SYS_FLASH_BASE		0x00000000
+
+#ifdef	CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+#else
+/* This is mainly used during relocation in start.S */
+#define CONFIG_SYS_MONITOR_BASE		(CONFIG_SYS_FLASH_BASE + 0x400)
+#endif
+/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)
+
+#define CONFIG_SYS_BOOTPARAMS_LEN	(64 * 1024)
+/* Reserve 128 kB for malloc() */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + \
+						(CONFIG_SYS_SDRAM_SIZE << 20))
+
+/* FLASH organization */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	259
+#define CONFIG_SYS_FLASH_ERASE_TOUT	1000
+
+#define CONFIG_SYS_FLASH_CFI		1
+#define CONFIG_FLASH_CFI_DRIVER		1
+#define CONFIG_SYS_FLASH_SIZE		0x2000000
+#define CONFIG_SYS_FLASH_PROTECTION	1
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+#define CONFIG_SYS_FLASH_CFI_NONBLOCK	1
+
+#if ENABLE_JFFS
+/* JFFS Partition offset set */
+#define CONFIG_SYS_JFFS2_FIRST_BANK    0
+#define CONFIG_SYS_JFFS2_NUM_BANKS     1
+/* 512k reserved for u-boot */
+#define CONFIG_SYS_JFFS2_FIRST_SECTOR  0x40
+#endif
+
+/* Cache Configuration */
+#define CONFIG_SYS_CACHELINE_SIZE	16
+
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINVA)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_EC | CF_CACR_CINVA | \
+					 CF_CACR_DCM_P)
+
+#endif	/* _CONFIG_ASTRO_MCF5373L_H */
diff --git a/qemu/roms/u-boot/include/configs/at91rm9200ek.h b/qemu/roms/u-boot/include/configs/at91rm9200ek.h
new file mode 100644
index 000000000..a30c016b4
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/at91rm9200ek.h
@@ -0,0 +1,214 @@
+/*
+ * Copyright (C) 2010 Andreas Bießmann <biessmann.devel@googlemail.com>
+ *
+ * based on previous work by
+ *
+ * Ulf Samuelsson <ulf@atmel.com>
+ * Rick Bronson <rick@efn.org>
+ *
+ * Configuration settings for the AT91RM9200EK board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __AT91RM9200EK_CONFIG_H__
+#define __AT91RM9200EK_CONFIG_H__
+
+#include <linux/sizes.h>
+
+/*
+ * set some initial configurations depending on configure target
+ *
+ * at91rm9200ek_config     -> boot from 0x0 in NOR Flash at CS0
+ * at91rm9200ek_ram_config -> continue booting from 0x20100000 in RAM; lowlevel
+ *                            initialisation was done by some preloader
+ */
+#ifdef CONFIG_RAMBOOT
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_TEXT_BASE 0x20100000
+#else
+#define CONFIG_SYS_TEXT_BASE 0x10000000
+#endif
+
+/*
+ * AT91C_XTAL_CLOCK is the frequency of external xtal in hertz
+ * AT91C_MAIN_CLOCK is the frequency of PLLA output
+ * AT91C_MASTER_CLOCK is the peripherial clock
+ * CONFIG_SYS_HZ_CLOCK is the value for CCR in tc0 (divider 2 is implicitely
+ *  set in arch/arm/cpu/arm920t/at91/timer.c)
+ * CONFIG_SYS_HZ is the tick rate for timer tc0
+ */
+#define AT91C_XTAL_CLOCK		18432000
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768
+#define AT91C_MAIN_CLOCK		((AT91C_XTAL_CLOCK / 4) * 39)
+#define AT91C_MASTER_CLOCK		(AT91C_MAIN_CLOCK / 3 )
+#define CONFIG_SYS_HZ_CLOCK		(AT91C_MASTER_CLOCK / 2)
+
+/* CPU configuration */
+#define CONFIG_AT91RM9200
+#define CONFIG_AT91RM9200EK
+#define CONFIG_CPUAT91
+#define USE_920T_MMU
+
+#include <asm/hardware.h>	/* needed for port definitions */
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_OF_LIBFDT
+
+/*
+ * Memory Configuration
+ */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE		0x20000000
+#define CONFIG_SYS_SDRAM_SIZE		SZ_32M
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		\
+		(CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - SZ_256K)
+
+/*
+ * LowLevel Init
+ */
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_USE_MAIN_OSCILLATOR
+/* flash */
+#define CONFIG_SYS_EBI_CFGR_VAL	0x00000000
+#define CONFIG_SYS_SMC_CSR0_VAL	0x00003284 /* 16bit, 2 TDF, 4 WS */
+
+/* clocks */
+#define CONFIG_SYS_PLLAR_VAL	0x20263E04 /* 179.712000 MHz for PCK */
+#define CONFIG_SYS_PLLBR_VAL	0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
+/* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
+#define CONFIG_SYS_MCKR_VAL	0x00000202
+
+/* sdram */
+#define CONFIG_SYS_PIOC_ASR_VAL	0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
+#define CONFIG_SYS_PIOC_BSR_VAL	0x00000000
+#define CONFIG_SYS_PIOC_PDR_VAL	0xFFFF0000
+#define CONFIG_SYS_EBI_CSA_VAL	0x00000002 /* CS1=CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRC_CR_VAL	0x2188c155 /* set up the CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRAM	CONFIG_SYS_SDRAM_BASE /* address of the SDRAM */
+#define CONFIG_SYS_SDRAM1	(CONFIG_SYS_SDRAM_BASE+0x80)
+#define CONFIG_SYS_SDRAM_VAL	0x00000000 /* value written to CONFIG_SYS_SDRAM */
+#define CONFIG_SYS_SDRC_MR_VAL	0x00000002 /* Precharge All */
+#define CONFIG_SYS_SDRC_MR_VAL1	0x00000004 /* refresh */
+#define CONFIG_SYS_SDRC_MR_VAL2	0x00000003 /* Load Mode Register */
+#define CONFIG_SYS_SDRC_MR_VAL3	0x00000000 /* Normal Mode */
+#define CONFIG_SYS_SDRC_TR_VAL	0x000002E0 /* Write refresh rate */
+#endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
+
+/*
+ * Hardware drivers
+ */
+/*
+ * Choose a USART for serial console
+ * CONFIG_DBGU is DBGU unit on J10
+ * CONFIG_USART1 is USART1 on J14
+ */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE	ATMEL_BASE_DBGU
+#define CONFIG_USART_ID		0/* ignored in arm */
+
+#define CONFIG_BAUDRATE			115200
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+#undef CONFIG_CMD_FPGA
+
+/*
+ * Network Driver Setting
+ */
+#define CONFIG_DRIVER_AT91EMAC
+#define CONFIG_SYS_RX_ETH_BUFFER	16
+#define CONFIG_RMII
+#define CONFIG_MII
+
+/*
+ * NOR Flash
+ */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_BASE		0x10000000
+#define PHYS_FLASH_1			CONFIG_SYS_FLASH_BASE
+#define PHYS_FLASH_SIZE			SZ_8M
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	256
+#define CONFIG_SYS_FLASH_PROTECTION
+
+/*
+ * USB Config
+ */
+#define CONFIG_USB_ATMEL			1
+#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
+#define CONFIG_USB_OHCI_NEW			1
+#define CONFIG_USB_KEYBOARD			1
+#define CONFIG_USB_STORAGE			1
+#define CONFIG_DOS_PARTITION			1
+
+#define CONFIG_SYS_USB_OHCI_CPU_INIT		1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		ATMEL_USB_HOST_BASE
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91rm9200"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
+
+/*
+ * Environment Settings
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+
+/*
+ * after u-boot.bin
+ */
+#define CONFIG_ENV_ADDR			\
+		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SIZE			SZ_64K /* sectors are 64K here */
+/* The following #defines are needed to get flash environment right */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		SZ_256K
+
+/*
+ * Boot option
+ */
+#define CONFIG_BOOTDELAY		3
+
+/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE + SZ_16M
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * Shell Settings
+ */
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT		"U-Boot> "
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		\
+		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + SZ_128K, \
+					     SZ_4K)
+
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + SZ_4K \
+					- GENERATED_GBL_DATA_SIZE)
+
+#endif /* __AT91RM9200EK_CONFIG_H__ */
diff --git a/qemu/roms/u-boot/include/configs/at91sam9260ek.h b/qemu/roms/u-boot/include/configs/at91sam9260ek.h
new file mode 100644
index 000000000..73917b0ec
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/at91sam9260ek.h
@@ -0,0 +1,275 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * Configuation settings for the AT91SAM9260EK & AT91SAM9G20EK boards.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * SoC must be defined first, before hardware.h is included.
+ * In this case SoC is defined in boards.cfg.
+ */
+#include <asm/hardware.h>
+
+/*
+ * Warning: changing CONFIG_SYS_TEXT_BASE requires
+ * adapting the initial boot program.
+ * Since the linker has to swallow that define, we must use a pure
+ * hex number here!
+ */
+#define CONFIG_SYS_TEXT_BASE		0x21f00000
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000	/* main clock xtal */
+
+/* Define actual evaluation board type from used processor type */
+#ifdef CONFIG_AT91SAM9G20
+# define CONFIG_AT91SAM9G20EK	/* It's an Atmel AT91SAM9G20 EK */
+#else
+# define CONFIG_AT91SAM9260EK	/* It's an Atmel AT91SAM9260 EK */
+#endif
+
+/* Misc CPU related */
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_OF_LIBFDT
+
+/* general purpose I/O */
+#define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
+#define CONFIG_AT91_GPIO
+#define CONFIG_AT91_GPIO_PULLUP	1	/* keep pullups on peripheral pins */
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
+#define	CONFIG_USART_ID			ATMEL_ID_SYS
+#define CONFIG_BAUDRATE			115200
+
+/* LED */
+#define CONFIG_AT91_LED
+#define	CONFIG_RED_LED		AT91_PIN_PA9	/* this is the power led */
+#define	CONFIG_GREEN_LED	AT91_PIN_PA6	/* this is the user led */
+
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE	1
+#define CONFIG_BOOTP_BOOTPATH		1
+#define CONFIG_BOOTP_GATEWAY		1
+#define CONFIG_BOOTP_HOSTNAME		1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_SOURCE
+
+#define CONFIG_CMD_PING		1
+#define CONFIG_CMD_DHCP		1
+#define CONFIG_CMD_NAND		1
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_USB		1
+
+/*
+ * SDRAM: 1 bank, min 32, max 128 MB
+ * Initialized before u-boot gets started.
+ */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
+#define CONFIG_SYS_SDRAM_SIZE		0x04000000
+
+/*
+ * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
+ * leaving the correct space for initial global data structure above
+ * that address while providing maximum stack area below.
+ */
+#ifdef CONFIG_AT91SAM9XE
+# define CONFIG_SYS_INIT_SP_ADDR \
+	(ATMEL_BASE_SRAM + 0x1000 - GENERATED_GBL_DATA_SIZE)
+#else
+# define CONFIG_SYS_INIT_SP_ADDR \
+	(ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
+#endif
+
+/*
+ * The (arm)linux board id set by generic code depending on configured board
+ * (see boards.cfg for different boards)
+ */
+#ifdef CONFIG_AT91SAM9G20
+	/* the sam9g20 variants have two different board ids */
+# ifdef CONFIG_AT91SAM9G20EK_2MMC
+	/* we may be setup for the 2MMC variant of at91sam9g20ek */
+#  define CONFIG_MACH_TYPE MACH_TYPE_AT91SAM9G20EK_2MMC
+# else
+	/* or the normal at91sam9g20ek */
+#  define CONFIG_MACH_TYPE MACH_TYPE_AT91SAM9G20EK
+# endif
+#else
+	/* otherwise default to good old at91sam9260ek */
+# define CONFIG_MACH_TYPE MACH_TYPE_AT91SAM9260EK
+#endif
+
+/* DataFlash */
+#ifndef CONFIG_AT91SAM9G20EK_2MMC
+#define CONFIG_ATMEL_DATAFLASH_SPI
+#define CONFIG_HAS_DATAFLASH		1
+#define CONFIG_SYS_SPI_WRITE_TOUT		(5*CONFIG_SYS_HZ)
+#define CONFIG_SYS_MAX_DATAFLASH_BANKS		2
+#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
+#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1	0xD0000000	/* CS1 */
+#define AT91_SPI_CLK			15000000
+#endif
+
+#ifdef CONFIG_AT91SAM9G20EK
+#define DATAFLASH_TCSS			(0x22 << 16)
+#else
+#define DATAFLASH_TCSS			(0x1a << 16)
+#endif
+#define DATAFLASH_TCHS			(0x1 << 24)
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
+#define CONFIG_SYS_NAND_DBW_8
+#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
+#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIN_PC14
+#define CONFIG_SYS_NAND_READY_PIN	AT91_PIN_PC13
+#endif
+
+/* MMC */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_GENERIC_ATMEL_MCI
+#endif
+
+/* FAT */
+#ifdef CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* NOR flash - no real flash on this board */
+#define CONFIG_SYS_NO_FLASH			1
+
+/* Ethernet */
+#define CONFIG_MACB			1
+#define CONFIG_RMII			1
+#define CONFIG_NET_RETRY_COUNT		20
+#define CONFIG_RESET_PHY_R		1
+#define CONFIG_AT91_WANTS_COMMON_PHY
+
+/* USB */
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
+#define CONFIG_USB_OHCI_NEW		1
+#define CONFIG_SYS_USB_OHCI_CPU_INIT		1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00500000	/* AT91SAM9260_UHP_BASE */
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9260"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+#define CONFIG_USB_STORAGE		1
+
+#define CONFIG_SYS_LOAD_ADDR			0x22000000	/* load address */
+
+#define CONFIG_SYS_MEMTEST_START		CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END			0x23e00000
+
+#ifdef CONFIG_SYS_USE_DATAFLASH_CS0
+
+/* bootstrap + u-boot + env + linux in dataflash on CS0 */
+#define CONFIG_ENV_IS_IN_DATAFLASH	1
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
+#define CONFIG_ENV_OFFSET		0x4200
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SIZE		0x4200
+#define CONFIG_BOOTCOMMAND	"cp.b 0xC0084000 0x22000000 0x210000; bootm"
+#define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
+				"root=/dev/mtdblock0 "			\
+				"mtdparts=atmel_nand:-(root) "		\
+				"rw rootfstype=jffs2"
+
+#elif CONFIG_SYS_USE_DATAFLASH_CS1
+
+/* bootstrap + u-boot + env + linux in dataflash on CS1 */
+#define CONFIG_ENV_IS_IN_DATAFLASH	1
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 + 0x8400)
+#define CONFIG_ENV_OFFSET		0x4200
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SIZE		0x4200
+#define CONFIG_BOOTCOMMAND	"cp.b 0xD0084000 0x22000000 0x210000; bootm"
+#define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
+				"root=/dev/mtdblock0 "			\
+				"mtdparts=atmel_nand:-(root) "		\
+				"rw rootfstype=jffs2"
+
+#elif defined(CONFIG_SYS_USE_NANDFLASH)
+
+/* bootstrap + u-boot + env + linux in nandflash */
+#define CONFIG_ENV_IS_IN_NAND	1
+#define CONFIG_ENV_OFFSET		0xc0000
+#define CONFIG_ENV_OFFSET_REDUND	0x100000
+#define CONFIG_ENV_SIZE		0x20000		/* 1 sector = 128 kB */
+#define CONFIG_BOOTCOMMAND	"nand read 0x22000000 0x200000 0x300000; bootm"
+#define CONFIG_BOOTARGS							\
+	"console=ttyS0,115200 earlyprintk "				\
+	"mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,"		\
+	"256k(env),256k(env_redundant),256k(spare),"			\
+	"512k(dtb),6M(kernel)ro,-(rootfs) "				\
+	"root=/dev/mtdblock7 rw rootfstype=jffs2"
+
+#else	/* CONFIG_SYS_USE_MMC */
+/* bootstrap + u-boot + env + linux in mmc */
+#define CONFIG_ENV_IS_IN_MMC
+/* For FAT system, most cases it should be in the reserved sector */
+#define CONFIG_ENV_OFFSET		0x2000
+#define CONFIG_ENV_SIZE			0x1000
+#define CONFIG_SYS_MMC_ENV_DEV		0
+
+#define CONFIG_BOOTCOMMAND						\
+	"fatload mmc 0:1 0x22000000 uImage; bootm"
+#define CONFIG_BOOTARGS							\
+	"console=ttyS0,115200 earlyprintk "				\
+	"mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,"		\
+	"256k(env),256k(env_redundant),256k(spare),"			\
+	"512k(dtb),6M(kernel)ro,-(rootfs) "				\
+	"root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait"
+#endif
+
+#define CONFIG_SYS_PROMPT		"U-Boot> "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP		1
+#define CONFIG_CMDLINE_EDITING	1
+#define CONFIG_AUTO_COMPLETE
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/at91sam9261ek.h b/qemu/roms/u-boot/include/configs/at91sam9261ek.h
new file mode 100644
index 000000000..226f8c161
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/at91sam9261ek.h
@@ -0,0 +1,224 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * Configuation settings for the AT91SAM9261EK board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000	/* 18.432 MHz crystal */
+
+#ifdef CONFIG_AT91SAM9G10
+#define CONFIG_AT91SAM9G10EK		/* It's an Atmel AT91SAM9G10 EK*/
+#else
+#define CONFIG_AT91SAM9261EK		/* It's an Atmel AT91SAM9261 EK*/
+#endif
+
+#include <asm/hardware.h>
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_ATMEL_LEGACY
+#define CONFIG_SYS_TEXT_BASE		0x21f00000
+
+/*
+ * Hardware drivers
+ */
+
+/* gpio */
+#define CONFIG_AT91_GPIO
+#define CONFIG_AT91_GPIO_PULLUP		1
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
+#define CONFIG_USART_ID			ATMEL_ID_SYS
+#define CONFIG_BAUDRATE			115200
+
+/* LCD */
+#define CONFIG_LCD
+#define LCD_BPP				LCD_COLOR8
+#define CONFIG_LCD_LOGO
+#undef LCD_TEST_PATTERN
+#define CONFIG_LCD_INFO
+#define CONFIG_LCD_INFO_BELOW_LOGO
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define CONFIG_ATMEL_LCD
+#ifdef CONFIG_AT91SAM9261EK
+#define CONFIG_ATMEL_LCD_BGR555
+#endif
+
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+/* LED */
+#define CONFIG_AT91_LED
+#define	CONFIG_RED_LED		AT91_PIN_PA23	/* this is the power led */
+#define	CONFIG_GREEN_LED	AT91_PIN_PA13	/* this is the user1 led */
+#define	CONFIG_YELLOW_LED	AT91_PIN_PA14	/* this is the user2 led */
+
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_SOURCE
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_USB
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE		0x20000000
+#define CONFIG_SYS_SDRAM_SIZE		0x04000000
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(ATMEL_BASE_SRAM + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+/* DataFlash */
+#define CONFIG_ATMEL_DATAFLASH_SPI
+#define CONFIG_HAS_DATAFLASH
+#define CONFIG_SYS_SPI_WRITE_TOUT		(5*CONFIG_SYS_HZ)
+#define CONFIG_SYS_MAX_DATAFLASH_BANKS		2
+#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
+#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3	0xD0000000	/* CS3 */
+#define AT91_SPI_CLK				15000000
+#define DATAFLASH_TCSS				(0x1a << 16)
+#define DATAFLASH_TCHS				(0x1 << 24)
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE		1
+#define CONFIG_SYS_NAND_BASE			0x40000000
+#define CONFIG_SYS_NAND_DBW_8
+/* our ALE is AD22 */
+#define CONFIG_SYS_NAND_MASK_ALE		(1 << 22)
+/* our CLE is AD21 */
+#define CONFIG_SYS_NAND_MASK_CLE		(1 << 21)
+#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PC14
+#define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PC15
+
+#endif
+
+/* NOR flash - no real flash on this board */
+#define CONFIG_SYS_NO_FLASH
+
+/* Ethernet */
+#define CONFIG_DRIVER_DM9000
+#define CONFIG_DM9000_BASE		0x30000000
+#define DM9000_IO			CONFIG_DM9000_BASE
+#define DM9000_DATA			(CONFIG_DM9000_BASE + 4)
+#define CONFIG_DM9000_USE_16BIT
+#define CONFIG_DM9000_NO_SROM
+#define CONFIG_NET_RETRY_COUNT		20
+#define CONFIG_RESET_PHY_R
+
+/* USB */
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00500000	/* AT91SAM9261_UHP_BASE */
+#ifdef CONFIG_AT91SAM9G10EK
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9g10"
+#else
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9261"
+#endif
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_FAT
+
+#define CONFIG_SYS_LOAD_ADDR			0x22000000	/* load address */
+
+#define CONFIG_SYS_MEMTEST_START		CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END			0x23e00000
+
+#ifdef CONFIG_SYS_USE_DATAFLASH_CS0
+
+/* bootstrap + u-boot + env + linux in dataflash on CS0 */
+#define CONFIG_ENV_IS_IN_DATAFLASH
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
+#define CONFIG_ENV_OFFSET	0x4200
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SIZE		0x4200
+#define CONFIG_BOOTCOMMAND	"cp.b 0xC0084000 0x22000000 0x210000; bootm"
+#define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
+				"root=/dev/mtdblock0 "			\
+				"mtdparts=atmel_nand:-(root) "		\
+				"rw rootfstype=jffs2"
+
+#elif CONFIG_SYS_USE_DATAFLASH_CS3
+
+/* bootstrap + u-boot + env + linux in dataflash on CS3 */
+#define CONFIG_ENV_IS_IN_DATAFLASH
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 + 0x8400)
+#define CONFIG_ENV_OFFSET	0x4200
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SIZE		0x4200
+#define CONFIG_BOOTCOMMAND	"cp.b 0xD0084000 0x22000000 0x210000; bootm"
+#define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
+				"root=/dev/mtdblock0 "			\
+				"mtdparts=atmel_nand:-(root) "		\
+				"rw rootfstype=jffs2"
+
+#else /* CONFIG_SYS_USE_NANDFLASH */
+
+/* bootstrap + u-boot + env + linux in nandflash */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		0xc0000
+#define CONFIG_ENV_OFFSET_REDUND	0x100000
+#define CONFIG_ENV_SIZE		0x20000		/* 1 sector = 128 kB */
+#define CONFIG_BOOTCOMMAND	"nand read 0x22000000 0x200000 0x300000; bootm"
+#define CONFIG_BOOTARGS							\
+	"console=ttyS0,115200 earlyprintk "				\
+	"mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,"		\
+	"256k(env),256k(env_redundant),256k(spare),"			\
+	"512k(dtb),6M(kernel)ro,-(rootfs) "				\
+	"root=/dev/mtdblock7 rw rootfstype=jffs2"
+#endif
+
+#define CONFIG_SYS_PROMPT		"U-Boot> "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/at91sam9263ek.h b/qemu/roms/u-boot/include/configs/at91sam9263ek.h
new file mode 100644
index 000000000..48c12ea88
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/at91sam9263ek.h
@@ -0,0 +1,354 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * Configuation settings for the AT91SAM9263EK board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * SoC must be defined first, before hardware.h is included.
+ * In this case SoC is defined in boards.cfg.
+ */
+#include <asm/hardware.h>
+
+#ifndef CONFIG_SYS_USE_BOOT_NORFLASH
+#define CONFIG_SYS_TEXT_BASE		0x21F00000
+#else
+#define CONFIG_SYS_TEXT_BASE		0x0000000
+#endif
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	16367660 /* 16.367 MHz crystal */
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768
+
+#define CONFIG_AT91SAM9263EK	1	/* It's an AT91SAM9263EK Board */
+
+#define CONFIG_ARCH_CPU_INIT
+
+#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG	1
+
+#ifndef CONFIG_SYS_USE_BOOT_NORFLASH
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#else
+#define CONFIG_SYS_USE_NORFLASH
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_OF_LIBFDT
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_ATMEL_LEGACY
+#define CONFIG_AT91_GPIO		1
+#define CONFIG_AT91_GPIO_PULLUP		1
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
+#define CONFIG_USART_ID			ATMEL_ID_SYS
+#define CONFIG_BAUDRATE			115200
+
+/* LCD */
+#define CONFIG_LCD			1
+#define LCD_BPP				LCD_COLOR8
+#define CONFIG_LCD_LOGO			1
+#undef LCD_TEST_PATTERN
+#define CONFIG_LCD_INFO			1
+#define CONFIG_LCD_INFO_BELOW_LOGO	1
+#define CONFIG_SYS_WHITE_ON_BLACK	1
+#define CONFIG_ATMEL_LCD		1
+#define CONFIG_ATMEL_LCD_BGR555		1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
+
+/* LED */
+#define CONFIG_AT91_LED
+#define	CONFIG_RED_LED		AT91_PIN_PB7	/* the power led */
+#define	CONFIG_GREEN_LED	AT91_PIN_PB8	/* the user1 led */
+#define	CONFIG_YELLOW_LED	AT91_PIN_PC29	/* the user2 led */
+
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE	1
+#define CONFIG_BOOTP_BOOTPATH		1
+#define CONFIG_BOOTP_GATEWAY		1
+#define CONFIG_BOOTP_HOSTNAME		1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_SOURCE
+
+#define CONFIG_CMD_PING		1
+#define CONFIG_CMD_DHCP		1
+#define CONFIG_CMD_NAND		1
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_USB		1
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
+#define CONFIG_SYS_SDRAM_SIZE		0x04000000
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+/* DataFlash */
+#define CONFIG_ATMEL_DATAFLASH_SPI
+#define CONFIG_HAS_DATAFLASH		1
+#define CONFIG_SYS_SPI_WRITE_TOUT		(5*CONFIG_SYS_HZ)
+#define CONFIG_SYS_MAX_DATAFLASH_BANKS		1
+#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
+#define AT91_SPI_CLK			15000000
+#define DATAFLASH_TCSS			(0x1a << 16)
+#define DATAFLASH_TCHS			(0x1 << 24)
+
+/* MMC */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_GENERIC_ATMEL_MCI
+#endif
+
+/* FAT */
+#ifdef CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* NOR flash, if populated */
+#ifdef CONFIG_SYS_USE_NORFLASH
+#define CONFIG_SYS_FLASH_CFI			1
+#define CONFIG_FLASH_CFI_DRIVER			1
+#define PHYS_FLASH_1				0x10000000
+#define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
+#define CONFIG_SYS_MAX_FLASH_SECT		256
+#define CONFIG_SYS_MAX_FLASH_BANKS		1
+
+#define CONFIG_SYS_MONITOR_SEC	1:0-3
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN	(256 << 10)
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x007E0000)
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR - CONFIG_ENV_SIZE)
+
+/* Address and size of Primary Environment Sector */
+#define CONFIG_ENV_SIZE		0x10000
+
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"monitor_base=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
+	"update=" \
+		"protect off ${monitor_base} +${filesize};" \
+		"erase ${monitor_base} +${filesize};" \
+		"cp.b ${fileaddr} ${monitor_base} ${filesize};" \
+		"protect on ${monitor_base} +${filesize}\0"
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#define MASTER_PLL_MUL		171
+#define MASTER_PLL_DIV		14
+#define MASTER_PLL_OUT		3
+
+/* clocks */
+#define CONFIG_SYS_MOR_VAL						\
+		(AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255))
+#define CONFIG_SYS_PLLAR_VAL					\
+	(AT91_PMC_PLLAR_29 |					\
+	AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) |			\
+	AT91_PMC_PLLXR_PLLCOUNT(63) |				\
+	AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | 		\
+	AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))
+
+/* PCK/2 = MCK Master Clock from PLLA */
+#define	CONFIG_SYS_MCKR1_VAL		\
+	(AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 |	\
+	 AT91_PMC_MCKR_MDIV_2)
+
+/* PCK/2 = MCK Master Clock from PLLA */
+#define	CONFIG_SYS_MCKR2_VAL		\
+	(AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | 	\
+	AT91_PMC_MCKR_MDIV_2)
+
+/* define PDC[31:16] as DATA[31:16] */
+#define CONFIG_SYS_PIOD_PDR_VAL1	0xFFFF0000
+/* no pull-up for D[31:16] */
+#define CONFIG_SYS_PIOD_PPUDR_VAL	0xFFFF0000
+/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
+#define CONFIG_SYS_MATRIX_EBICSA_VAL					\
+	(AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V |	\
+	 AT91_MATRIX_CSA_EBI_CS1A)
+
+/* SDRAM */
+/* SDRAMC_MR Mode register */
+#define CONFIG_SYS_SDRC_MR_VAL1		0
+/* SDRAMC_TR - Refresh Timer register */
+#define CONFIG_SYS_SDRC_TR_VAL1		0x13C
+/* SDRAMC_CR - Configuration register*/
+#define CONFIG_SYS_SDRC_CR_VAL							\
+		(AT91_SDRAMC_NC_9 |						\
+		 AT91_SDRAMC_NR_13 |						\
+		 AT91_SDRAMC_NB_4 |						\
+		 AT91_SDRAMC_CAS_3 |						\
+		 AT91_SDRAMC_DBW_32 |						\
+		 (1 <<  8) |		/* Write Recovery Delay */		\
+		 (7 << 12) |		/* Row Cycle Delay */			\
+		 (2 << 16) |		/* Row Precharge Delay */		\
+		 (2 << 20) |		/* Row to Column Delay */		\
+		 (5 << 24) |		/* Active to Precharge Delay */		\
+		 (1 << 28))		/* Exit Self Refresh to Active Delay */
+
+/* Memory Device Register -> SDRAM */
+#define CONFIG_SYS_SDRC_MDR_VAL		AT91_SDRAMC_MD_SDRAM
+#define CONFIG_SYS_SDRC_MR_VAL2		AT91_SDRAMC_MODE_PRECHARGE
+#define CONFIG_SYS_SDRAM_VAL1		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL3		AT91_SDRAMC_MODE_REFRESH
+#define CONFIG_SYS_SDRAM_VAL2		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL3		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL4		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL5		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL6		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL7		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL8		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL9		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL4		AT91_SDRAMC_MODE_LMR
+#define CONFIG_SYS_SDRAM_VAL10		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL5		AT91_SDRAMC_MODE_NORMAL
+#define CONFIG_SYS_SDRAM_VAL11		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_TR_VAL2		1200		/* SDRAM_TR */
+#define CONFIG_SYS_SDRAM_VAL12		0		/* SDRAM_BASE */
+
+/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
+#define CONFIG_SYS_SMC0_SETUP0_VAL				\
+	(AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) |	\
+	 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
+#define CONFIG_SYS_SMC0_PULSE0_VAL				\
+	(AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) |	\
+	 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
+#define CONFIG_SYS_SMC0_CYCLE0_VAL	\
+	(AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
+#define CONFIG_SYS_SMC0_MODE0_VAL				\
+	(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |		\
+	 AT91_SMC_MODE_DBW_16 |					\
+	 AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6))
+
+/* user reset enable */
+#define CONFIG_SYS_RSTC_RMR_VAL			\
+		(AT91_RSTC_KEY |		\
+		AT91_RSTC_MR_URSTEN |		\
+		AT91_RSTC_MR_ERSTL(15))
+
+/* Disable Watchdog */
+#define CONFIG_SYS_WDTC_WDMR_VAL				\
+		(AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT |	\
+		 AT91_WDT_MR_WDV(0xfff) |			\
+		 AT91_WDT_MR_WDDIS |				\
+		 AT91_WDT_MR_WDD(0xfff))
+
+#endif
+
+#else
+#define CONFIG_SYS_NO_FLASH			1
+#endif
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE		1
+#define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3
+#define CONFIG_SYS_NAND_DBW_8			1
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PD15
+#define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PA22
+#endif
+
+/* Ethernet */
+#define CONFIG_MACB			1
+#define CONFIG_RMII			1
+#define CONFIG_NET_RETRY_COUNT		20
+#define CONFIG_RESET_PHY_R		1
+#define CONFIG_AT91_WANTS_COMMON_PHY
+
+/* USB */
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
+#define CONFIG_USB_OHCI_NEW		1
+#define CONFIG_DOS_PARTITION		1
+#define CONFIG_SYS_USB_OHCI_CPU_INIT		1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00a00000	/* AT91SAM9263_UHP_BASE */
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9263"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+#define CONFIG_USB_STORAGE		1
+#define CONFIG_CMD_FAT			1
+
+#define CONFIG_SYS_LOAD_ADDR			0x22000000	/* load address */
+
+#define CONFIG_SYS_MEMTEST_START		CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END			0x23e00000
+
+#ifdef CONFIG_SYS_USE_DATAFLASH
+
+/* bootstrap + u-boot + env + linux in dataflash on CS0 */
+#define CONFIG_ENV_IS_IN_DATAFLASH	1
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
+#define CONFIG_ENV_OFFSET		0x4200
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SIZE		0x4200
+#define CONFIG_BOOTCOMMAND	"cp.b 0xC0084000 0x22000000 0x210000; bootm"
+#define CONFIG_BOOTARGS		"console=ttyS0,115200 " \
+				"root=/dev/mtdblock0 " \
+				"mtdparts=atmel_nand:-(root) "\
+				"rw rootfstype=jffs2"
+
+#elif CONFIG_SYS_USE_NANDFLASH
+
+/* bootstrap + u-boot + env + linux in nandflash */
+#define CONFIG_ENV_IS_IN_NAND		1
+#define CONFIG_ENV_OFFSET		0xc0000
+#define CONFIG_ENV_OFFSET_REDUND	0x100000
+#define CONFIG_ENV_SIZE		0x20000		/* 1 sector = 128 kB */
+#define CONFIG_BOOTCOMMAND	"nand read 0x22000000 0x200000 0x300000; bootm"
+#define CONFIG_BOOTARGS							\
+	"console=ttyS0,115200 earlyprintk "				\
+	"mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,"		\
+	"256k(env),256k(env_redundant),256k(spare),"			\
+	"512k(dtb),6M(kernel)ro,-(rootfs) "				\
+	"root=/dev/mtdblock7 rw rootfstype=jffs2"
+#endif
+
+#define CONFIG_SYS_PROMPT		"U-Boot> "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP		1
+#define CONFIG_CMDLINE_EDITING		1
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN	ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/at91sam9m10g45ek.h b/qemu/roms/u-boot/include/configs/at91sam9m10g45ek.h
new file mode 100644
index 000000000..ccfda71c9
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/at91sam9m10g45ek.h
@@ -0,0 +1,169 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * Configuation settings for the AT91SAM9M10G45EK board(and AT91SAM9G45EKES).
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/hardware.h>
+
+#define CONFIG_SYS_TEXT_BASE		0x73f00000
+
+#define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK      32768
+#define CONFIG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
+
+#define CONFIG_AT91SAM9M10G45EK
+#define CONFIG_AT91FAMILY
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_OF_LIBFDT
+
+/* general purpose I/O */
+#define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
+#define CONFIG_AT91_GPIO
+#define CONFIG_AT91_GPIO_PULLUP	1	/* keep pullups on peripheral pins */
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
+#define	CONFIG_USART_ID			ATMEL_ID_SYS
+
+/* LCD */
+#define CONFIG_LCD
+#define LCD_BPP				LCD_COLOR8
+#define CONFIG_LCD_LOGO
+#undef LCD_TEST_PATTERN
+#define CONFIG_LCD_INFO
+#define CONFIG_LCD_INFO_BELOW_LOGO
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define CONFIG_ATMEL_LCD
+#define CONFIG_ATMEL_LCD_RGB565
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+/* board specific(not enough SRAM) */
+#define CONFIG_AT91SAM9G45_LCD_BASE		0x73E00000
+
+/* LED */
+#define CONFIG_AT91_LED
+#define	CONFIG_RED_LED		AT91_PIN_PD31	/* this is the user1 led */
+#define	CONFIG_GREEN_LED	AT91_PIN_PD0	/* this is the user2 led */
+
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+
+/* No NOR flash */
+#define CONFIG_SYS_NO_FLASH
+
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_LOADS
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_USB
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE           ATMEL_BASE_CS6
+#define CONFIG_SYS_SDRAM_SIZE		0x08000000
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE		1
+#define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3
+#define CONFIG_SYS_NAND_DBW_8
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PC14
+#define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PC8
+
+#endif
+
+/* Ethernet */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_RETRY_COUNT		20
+#define CONFIG_RESET_PHY_R
+#define CONFIG_AT91_WANTS_COMMON_PHY
+
+/* USB */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_ATMEL
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	2
+#define CONFIG_DOS_PARTITION
+#define CONFIG_USB_STORAGE
+
+#define CONFIG_SYS_LOAD_ADDR		0x22000000	/* load address */
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		0x23e00000
+
+/* bootstrap + u-boot + env in nandflash */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		0xc0000
+#define CONFIG_ENV_OFFSET_REDUND	0x100000
+#define CONFIG_ENV_SIZE			0x20000
+
+#define CONFIG_BOOTCOMMAND						\
+	"nand read 0x70000000 0x200000 0x300000;"			\
+	"bootm 0x70000000"
+#define CONFIG_BOOTARGS							\
+	"console=ttyS0,115200 earlyprintk "				\
+	"mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,"		\
+	"256k(env),256k(env_redundant),256k(spare),"			\
+	"512k(dtb),6M(kernel)ro,-(rootfs) "				\
+	"root=/dev/mtdblock7 rw rootfstype=jffs2"
+
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_SYS_PROMPT		"U-Boot> "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/at91sam9n12ek.h b/qemu/roms/u-boot/include/configs/at91sam9n12ek.h
new file mode 100644
index 000000000..e23549d44
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/at91sam9n12ek.h
@@ -0,0 +1,235 @@
+/*
+ * (C) Copyright 2013 Atmel Corporation.
+ * Josh Wu <josh.wu@atmel.com>
+ *
+ * Configuation settings for the AT91SAM9N12-EK boards.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __AT91SAM9N12_CONFIG_H_
+#define __AT91SAM9N12_CONFIG_H_
+
+/*
+ * SoC must be defined first, before hardware.h is included.
+ * In this case SoC is defined in boards.cfg.
+ */
+#include <asm/hardware.h>
+
+#define CONFIG_SYS_TEXT_BASE		0x26f00000
+
+#define CONFIG_ARM926EJS
+#define CONFIG_AT91FAMILY
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	16000000	/* main clock xtal */
+
+/* Misc CPU related */
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_OF_LIBFDT
+
+/* general purpose I/O */
+#define CONFIG_AT91_GPIO
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
+#define CONFIG_USART_ID			ATMEL_ID_SYS
+#define CONFIG_BAUDRATE			115200
+
+/* LCD */
+#define CONFIG_LCD
+#define LCD_BPP				LCD_COLOR16
+#define LCD_OUTPUT_BPP			24
+#define CONFIG_LCD_LOGO
+#define CONFIG_LCD_INFO
+#define CONFIG_LCD_INFO_BELOW_LOGO
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define CONFIG_ATMEL_HLCD
+#define CONFIG_ATMEL_LCD_RGB565
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+#define CONFIG_BOOTDELAY		3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/* NOR flash - no real flash on this board */
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_FPGA
+
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_USB
+
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE		0x20000000
+#define CONFIG_SYS_SDRAM_SIZE		0x08000000
+
+/*
+ * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
+ * leaving the correct space for initial global data structure above
+ * that address while providing maximum stack area below.
+ */
+# define CONFIG_SYS_INIT_SP_ADDR \
+	(ATMEL_BASE_SRAM + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+/* DataFlash */
+#ifdef CONFIG_CMD_SF
+#define CONFIG_ATMEL_SPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_ATMEL
+#define CONFIG_SF_DEFAULT_SPEED		30000000
+#define CONFIG_ENV_SPI_MODE		SPI_MODE_3
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3
+#endif
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
+#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN	GPIO_PIN_PD(4)
+#define CONFIG_SYS_NAND_READY_PIN	GPIO_PIN_PD(5)
+
+/* PMECC & PMERRLOC */
+#define CONFIG_ATMEL_NAND_HWECC
+#define CONFIG_ATMEL_NAND_HW_PMECC
+#define CONFIG_PMECC_CAP		2
+#define CONFIG_PMECC_SECTOR_SIZE	512
+#define CONFIG_PMECC_INDEX_TABLE_OFFSET	0x8000
+
+#define CONFIG_CMD_NAND_TRIMFFS
+
+#endif
+
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_CMD_MTDPARTS
+#define MTDIDS_DEFAULT			"nand0=atmel_nand"
+#define MTDPARTS_DEFAULT						\
+	"mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,"		\
+	"256k(env),256k(env_redundant),256k(spare),"			\
+	"512k(dtb),6M(kernel)ro,-(rootfs)"
+
+#define CONFIG_EXTRA_ENV_SETTINGS                                       \
+	"console=console=ttyS0,115200\0"                                \
+	"mtdparts="MTDPARTS_DEFAULT"\0"					\
+	"bootargs_nand=rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs rw\0"\
+	"bootargs_mmc=root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait\0"
+
+/* MMC */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_GENERIC_ATMEL_MCI
+#endif
+
+/* FAT */
+#ifdef CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* Ethernet */
+#define CONFIG_KS8851_MLL
+#define CONFIG_KS8851_MLL_BASEADDR	0x30000000 /* use NCS2 */
+
+#define CONFIG_SYS_LOAD_ADDR		0x22000000 /* load address */
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		0x26e00000
+
+/* USB host */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE	ATMEL_BASE_OHCI
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"at91sam9n12"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	1
+#define CONFIG_USB_STORAGE
+#endif
+
+#ifdef CONFIG_SYS_USE_SPIFLASH
+
+/* bootstrap + u-boot + env + linux in dataflash on CS0 */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET		0x5000
+#define CONFIG_ENV_SIZE			0x3000
+#define CONFIG_ENV_SECT_SIZE		0x1000
+#define CONFIG_BOOTCOMMAND						\
+	"setenv bootargs ${console} ${mtdparts} ${bootargs_nand};"	\
+	"sf probe 0; sf read 0x22000000 0x100000 0x300000; "		\
+	"bootm 0x22000000"
+
+#elif defined(CONFIG_SYS_USE_NANDFLASH)
+
+/* bootstrap + u-boot + env + linux in nandflash */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		0xc0000
+#define CONFIG_ENV_OFFSET_REDUND	0x100000
+#define CONFIG_ENV_SIZE			0x20000		/* 1 sector = 128 kB */
+#define CONFIG_BOOTCOMMAND						\
+	"setenv bootargs ${console} ${mtdparts} ${bootargs_nand};"	\
+	"nand read 0x21000000 0x180000 0x080000;"			\
+	"nand read 0x22000000 0x200000 0x400000;"			\
+	"bootm 0x22000000 - 0x21000000"
+
+#else /* CONFIG_SYS_USE_MMC */
+
+/* bootstrap + u-boot + env + linux in mmc */
+#define CONFIG_ENV_IS_IN_MMC
+/* For FAT system, most cases it should be in the reserved sector */
+#define CONFIG_ENV_OFFSET		0x2000
+#define CONFIG_ENV_SIZE			0x1000
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_BOOTCOMMAND						\
+	"setenv bootargs ${console} ${mtdparts} ${bootargs_mmc};"	\
+	"fatload mmc 0:1 0x21000000 dtb;"				\
+	"fatload mmc 0:1 0x22000000 uImage;"				\
+	"bootm 0x22000000 - 0x21000000"
+
+#endif
+
+#define CONFIG_SYS_PROMPT	"U-Boot> "
+#define CONFIG_SYS_CBSIZE	256
+#define CONFIG_SYS_MAXARGS	16
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) \
+					+ 16)
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN	(4 * 1024 * 1024)
+#define CONFIG_STACKSIZE	(32 * 1024)	/* regular stack */
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/at91sam9rlek.h b/qemu/roms/u-boot/include/configs/at91sam9rlek.h
new file mode 100644
index 000000000..3747098d2
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/at91sam9rlek.h
@@ -0,0 +1,177 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * Configuation settings for the AT91SAM9RLEK board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/hardware.h>
+
+#define CONFIG_SYS_TEXT_BASE		0x21F00000
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	12000000	/* main clock xtal */
+
+#define CONFIG_AT91SAM9RLEK		1	/* It's an AT91SAM9RLEK Board */
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_ATMEL_LEGACY
+#define CONFIG_AT91_GPIO		1
+#define CONFIG_AT91_GPIO_PULLUP		1
+
+/*
+ * Hardware drivers
+ */
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
+#define CONFIG_USART_ID			ATMEL_ID_SYS
+#define CONFIG_BAUDRATE			115200
+
+/* LCD */
+#define CONFIG_LCD			1
+#define LCD_BPP				LCD_COLOR8
+#define CONFIG_LCD_LOGO			1
+#undef LCD_TEST_PATTERN
+#define CONFIG_LCD_INFO			1
+#define CONFIG_LCD_INFO_BELOW_LOGO	1
+#define CONFIG_SYS_WHITE_ON_BLACK	1
+#define CONFIG_ATMEL_LCD		1
+#define CONFIG_ATMEL_LCD_RGB565		1
+/* Let board_init_f handle the framebuffer allocation */
+#undef CONFIG_FB_ADDR
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
+
+
+/* LED */
+#define CONFIG_AT91_LED
+#define	CONFIG_RED_LED		AT91_PIN_PD14	/* this is the power led */
+#define	CONFIG_GREEN_LED	AT91_PIN_PD15	/* this is the user1 led */
+#define	CONFIG_YELLOW_LED	AT91_PIN_PD16	/* this is the user2 led */
+
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_SOURCE
+#undef CONFIG_CMD_USB
+
+#define CONFIG_CMD_NAND			1
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
+#define CONFIG_SYS_SDRAM_SIZE		0x04000000
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(ATMEL_BASE_SRAM + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+/* DataFlash */
+#define CONFIG_ATMEL_DATAFLASH_SPI
+#define CONFIG_HAS_DATAFLASH			1
+#define CONFIG_SYS_SPI_WRITE_TOUT		(5*CONFIG_SYS_HZ)
+#define CONFIG_SYS_MAX_DATAFLASH_BANKS		1
+#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
+#define AT91_SPI_CLK				15000000
+#define DATAFLASH_TCSS				(0x1a << 16)
+#define DATAFLASH_TCHS				(0x1 << 24)
+
+/* NOR flash - not present */
+#define CONFIG_SYS_NO_FLASH			1
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE		1
+#define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3
+#define CONFIG_SYS_NAND_DBW_8			1
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PB6
+#define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PD17
+
+#endif
+
+/* Ethernet - not present */
+
+/* USB - not supported */
+
+#define CONFIG_SYS_LOAD_ADDR			0x22000000	/* load address */
+
+#define CONFIG_SYS_MEMTEST_START		CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END			0x23e00000
+
+#ifdef CONFIG_SYS_USE_DATAFLASH
+
+/* bootstrap + u-boot + env + linux in dataflash on CS0 */
+#define CONFIG_ENV_IS_IN_DATAFLASH	1
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
+#define CONFIG_ENV_OFFSET		0x4200
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SIZE		0x4200
+#define CONFIG_BOOTCOMMAND	"cp.b 0xC0084000 0x22000000 0x210000; bootm"
+#define CONFIG_BOOTARGS		"console=ttyS0,115200 " \
+				"root=/dev/mtdblock0 " \
+				"mtdparts=atmel_nand:-(root) "\
+				"rw rootfstype=jffs2"
+
+#else /* CONFIG_SYS_USE_NANDFLASH */
+
+/* bootstrap + u-boot + env + linux in nandflash */
+#define CONFIG_ENV_IS_IN_NAND		1
+#define CONFIG_ENV_OFFSET		0x60000
+#define CONFIG_ENV_OFFSET_REDUND	0x80000
+#define CONFIG_ENV_SIZE		0x20000		/* 1 sector = 128 kB */
+#define CONFIG_BOOTCOMMAND	"nand read 0x22000000 0xA0000 0x200000; bootm"
+#define CONFIG_BOOTARGS		"console=ttyS0,115200 " \
+				"root=/dev/mtdblock5 " \
+				"mtdparts=atmel_nand:128k(bootstrap)ro,256k(uboot)ro,128k(env1)ro,128k(env2)ro,2M(linux),-(root) " \
+				"rw rootfstype=jffs2"
+
+#endif
+
+#define CONFIG_SYS_PROMPT		"U-Boot> "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP		1
+#define CONFIG_CMDLINE_EDITING		1
+#define CONFIG_AUTO_COMPLETE
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN	ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/at91sam9x5ek.h b/qemu/roms/u-boot/include/configs/at91sam9x5ek.h
new file mode 100644
index 000000000..f0a6757ff
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/at91sam9x5ek.h
@@ -0,0 +1,244 @@
+/*
+ * Copyright (C) 2012 Atmel Corporation
+ *
+ * Configuation settings for the AT91SAM9X5EK board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H__
+#define __CONFIG_H__
+
+#include <asm/hardware.h>
+
+#define CONFIG_SYS_TEXT_BASE		0x26f00000
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768
+#define CONFIG_SYS_AT91_MAIN_CLOCK	12000000	/* 12 MHz crystal */
+
+#define CONFIG_AT91SAM9X5EK
+#define CONFIG_AT91FAMILY
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_OF_LIBFDT
+
+/* general purpose I/O */
+#define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
+#define CONFIG_AT91_GPIO
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE	ATMEL_BASE_DBGU
+#define CONFIG_USART_ID		ATMEL_ID_SYS
+
+/* LCD */
+#define CONFIG_LCD
+#define LCD_BPP			LCD_COLOR16
+#define LCD_OUTPUT_BPP		24
+#define CONFIG_LCD_LOGO
+#define CONFIG_LCD_INFO
+#define CONFIG_LCD_INFO_BELOW_LOGO
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define CONFIG_ATMEL_HLCD
+#define CONFIG_ATMEL_LCD_RGB565
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/* no NOR flash */
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_USB
+
+/*
+ * define CONFIG_USB_EHCI to enable USB Hi-Speed (aka 2.0)
+ * NB: in this case, USB 1.1 devices won't be recognized.
+ */
+
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE		0x20000000
+#define CONFIG_SYS_SDRAM_SIZE		0x08000000	/* 128 megs */
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
+
+/* DataFlash */
+#ifdef CONFIG_CMD_SF
+#define CONFIG_ATMEL_SPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_ATMEL
+#define CONFIG_SF_DEFAULT_SPEED		30000000
+#endif
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CONFIG_SYS_NAND_DBW_8		1
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIN_PD4
+#define CONFIG_SYS_NAND_READY_PIN	AT91_PIN_PD5
+
+/* PMECC & PMERRLOC */
+#define CONFIG_ATMEL_NAND_HWECC		1
+#define CONFIG_ATMEL_NAND_HW_PMECC	1
+#define CONFIG_PMECC_CAP		2
+#define CONFIG_PMECC_SECTOR_SIZE	512
+
+#define CONFIG_CMD_NAND_TRIMFFS
+
+#define CONFIG_MTD_DEVICE
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#endif
+
+/* MMC */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_GENERIC_ATMEL_MCI
+#endif
+
+/* FAT */
+#ifdef CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* Ethernet */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_RETRY_COUNT		20
+#define CONFIG_MACB_SEARCH_PHY
+
+/* USB */
+#ifdef CONFIG_CMD_USB
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_ATMEL
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	2
+#else
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		ATMEL_BASE_OHCI
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9x5"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	3
+#endif
+#define CONFIG_USB_STORAGE
+#endif
+
+#define CONFIG_SYS_LOAD_ADDR		0x22000000	/* load address */
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		0x26e00000
+
+#ifdef CONFIG_SYS_USE_NANDFLASH
+/* bootstrap + u-boot + env + linux in nandflash */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		0xc0000
+#define CONFIG_ENV_OFFSET_REDUND	0x100000
+#define CONFIG_ENV_SIZE		0x20000		/* 1 sector = 128 kB */
+#define CONFIG_BOOTCOMMAND	"nand read " \
+				"0x22000000 0x200000 0x300000; " \
+				"bootm 0x22000000"
+#elif defined(CONFIG_SYS_USE_SPIFLASH)
+/* bootstrap + u-boot + env + linux in spi flash */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET	0x5000
+#define CONFIG_ENV_SIZE		0x3000
+#define CONFIG_ENV_SECT_SIZE	0x1000
+#define CONFIG_ENV_SPI_MAX_HZ	30000000
+#define CONFIG_BOOTCOMMAND	"sf probe 0; " \
+				"sf read 0x22000000 0x100000 0x300000; " \
+				"bootm 0x22000000"
+#elif defined(CONFIG_SYS_USE_DATAFLASH)
+/* bootstrap + u-boot + env + linux in data flash */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET	0x4200
+#define CONFIG_ENV_SIZE		0x4200
+#define CONFIG_ENV_SECT_SIZE	0x210
+#define CONFIG_ENV_SPI_MAX_HZ	30000000
+#define CONFIG_BOOTCOMMAND	"sf probe 0; " \
+				"sf read 0x22000000 0x84000 0x294000; " \
+				"bootm 0x22000000"
+#else /* CONFIG_SYS_USE_MMC */
+/* bootstrap + u-boot + env + linux in mmc */
+#define CONFIG_ENV_IS_IN_MMC
+/* For FAT system, most cases it should be in the reserved sector */
+#define CONFIG_ENV_OFFSET	0x2000
+#define CONFIG_ENV_SIZE		0x1000
+#define CONFIG_SYS_MMC_ENV_DEV	0
+#endif
+
+#ifdef CONFIG_SYS_USE_MMC
+#define CONFIG_BOOTARGS		"mem=128M console=ttyS0,115200 " \
+				"mtdparts=atmel_nand:" \
+				"8M(bootstrap/uboot/kernel)ro,-(rootfs) " \
+				"root=/dev/mmcblk0p2 " \
+				"rw rootfstype=ext4 rootwait"
+#else
+#define CONFIG_BOOTARGS							\
+	"console=ttyS0,115200 earlyprintk "				\
+	"mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,"		\
+	"256k(env),256k(env_redundant),256k(spare),"			\
+	"512k(dtb),6M(kernel)ro,-(rootfs) "				\
+	"rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs rw"
+#endif
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_SYS_PROMPT	"U-Boot> "
+#define CONFIG_SYS_CBSIZE	256
+#define CONFIG_SYS_MAXARGS	16
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) \
+					+ 16)
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(512 * 1024 + 0x1000)
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/atc.h b/qemu/roms/u-boot/include/configs/atc.h
new file mode 100644
index 000000000..77fa79a18
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/atc.h
@@ -0,0 +1,489 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_ATC		1	/* ...on a ATC board	*/
+#define CONFIG_CPM2		1	/* Has a CPM2 */
+
+#define	CONFIG_SYS_TEXT_BASE	0xFF000000
+
+/*
+ * select serial console configuration
+ *
+ * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ *
+ * if CONFIG_CONS_NONE is defined, then the serial console routines must
+ * defined elsewhere (for example, on the cogent platform, there are serial
+ * ports on the motherboard which are used for the serial console - see
+ * cogent/cma101/serial.[ch]).
+ */
+#define  CONFIG_CONS_ON_SMC		/* define if console on SMC */
+#undef CONFIG_CONS_ON_SCC		/* define if console on SCC */
+#undef  CONFIG_CONS_NONE		/* define if console on something else*/
+#define CONFIG_CONS_INDEX	2	/* which serial channel for console */
+
+#define CONFIG_BAUDRATE		115200
+
+/*
+ * select ethernet configuration
+ *
+ * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
+ * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
+ * for FCC)
+ *
+ * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
+ */
+#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC       */
+#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
+#define CONFIG_ETHER_ON_FCC
+
+#define CONFIG_ETHER_ON_FCC2
+
+/*
+ * - Rx-CLK is CLK13
+ * - Tx-CLK is CLK14
+ * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
+ * - Enable Full Duplex in FSMR
+ */
+# define CONFIG_SYS_CMXFCR_MASK2	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
+# define CONFIG_SYS_CPMFCR_RAMTYPE	0
+# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+
+#define CONFIG_ETHER_ON_FCC3
+
+/*
+ * - Rx-CLK is CLK15
+ * - Tx-CLK is CLK16
+ * - RAM for BD/Buffers is on the local Bus (see 28-13)
+ * - Enable Half Duplex in FSMR
+ */
+# define CONFIG_SYS_CMXFCR_MASK3	(CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE3	(CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
+
+/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
+#define CONFIG_8260_CLKIN	64000000	/* in Hz */
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#undef	CONFIG_CLOCKS_IN_MHZ		/* clocks passsed to Linux in Hz */
+
+#define CONFIG_PREBOOT							\
+	"echo;"								\
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;"\
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND						\
+	"bootp;"							\
+	"setenv bootargs root=/dev/nfs rw "				\
+	"nfsroot=${serverip}:${rootpath} "				\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"\
+	"bootm"
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configuration options
+ */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PCMCIA
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_IDE
+
+
+#define CONFIG_DOS_PARTITION
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address	*/
+
+#define CONFIG_SYS_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/
+
+#define	CONFIG_SYS_RESET_ADDRESS 0xFFF00100	/* "bad" address		*/
+
+#define CONFIG_SYS_ALLOC_DPRAM
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_SPI
+
+#define CONFIG_RTC_DS12887
+
+#define RTC_BASE_ADDR		0xF5000000
+#define RTC_PORT_ADDR		RTC_BASE_ADDR + 0x800
+#define RTC_PORT_DATA		RTC_BASE_ADDR + 0x808
+
+#define CONFIG_MISC_INIT_R
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * Flash configuration
+ */
+
+#define CONFIG_SYS_FLASH_BASE		0xFF000000
+#define CONFIG_SYS_FLASH_SIZE		0x00800000
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+
+#define CONFIG_FLASH_16BIT
+
+/*-----------------------------------------------------------------------
+ * Hard Reset Configuration Words
+ *
+ * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
+ * defines for the various registers affected by the HRCW e.g. changing
+ * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
+ */
+#define CONFIG_SYS_HRCW_MASTER		(HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
+				 HRCW_BPS10 |\
+				 HRCW_APPC10)
+
+/* no slaves so just fill with zeros */
+#define CONFIG_SYS_HRCW_SLAVE1		0
+#define CONFIG_SYS_HRCW_SLAVE2		0
+#define CONFIG_SYS_HRCW_SLAVE3		0
+#define CONFIG_SYS_HRCW_SLAVE4		0
+#define CONFIG_SYS_HRCW_SLAVE5		0
+#define CONFIG_SYS_HRCW_SLAVE6		0
+#define CONFIG_SYS_HRCW_SLAVE7		0
+
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xF0000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2F00  /* Size of used area in DPRAM    */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ *
+ * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE.
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_MAX_SIZE	0x08000000	/* max. 128 MB		*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+# define CONFIG_SYS_RAMBOOT
+#endif
+
+#define	CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define	CONFIG_PCI_PNP
+#define	CONFIG_SYS_PCI_MSTR_IO_BUS	0x00000000	/* PCI base   */
+
+#if 1
+/* environment is in Flash */
+#define CONFIG_ENV_IS_IN_FLASH	1
+# define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE+0x30000)
+# define CONFIG_ENV_SIZE		0x10000
+# define CONFIG_ENV_SECT_SIZE	0x10000
+#else
+#define CONFIG_ENV_IS_IN_EEPROM	1
+#define CONFIG_ENV_OFFSET		0
+#define CONFIG_ENV_SIZE		2048
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4	/* 16-byte page size	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
+#if defined(CONFIG_CMD_KGDB)
+# define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * HIDx - Hardware Implementation-dependent Registers                    2-11
+ *-----------------------------------------------------------------------
+ * HID0 also contains cache control - initially enable both caches and
+ * invalidate contents, then the final state leaves only the instruction
+ * cache enabled. Note that Power-On and Hard reset invalidate the caches,
+ * but Soft reset does not.
+ *
+ * HID1 has only read-only information - nothing to set.
+ */
+#define CONFIG_SYS_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|\
+			 HID0_DCI|HID0_IFEM|HID0_ABE)
+#define CONFIG_SYS_HID0_FINAL  (HID0_IFEM|HID0_ABE)
+#define CONFIG_SYS_HID2        0
+
+/*-----------------------------------------------------------------------
+ * RMR - Reset Mode Register                                     5-5
+ *-----------------------------------------------------------------------
+ * turn on Checkstop Reset Enable
+ */
+#define CONFIG_SYS_RMR         RMR_CSRE
+
+/*-----------------------------------------------------------------------
+ * BCR - Bus Configuration                                       4-25
+ *-----------------------------------------------------------------------
+ */
+#define BCR_APD01	0x10000000
+#define CONFIG_SYS_BCR		(BCR_APD01|BCR_ETM|BCR_LETM)	/* 8260 mode */
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration                             4-31
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_SIUMCR      (SIUMCR_BBD|SIUMCR_APPC10|\
+			 SIUMCR_CS10PC00|SIUMCR_BCTLC10)
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control                             4-35
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
+#else
+#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+			 SYPCR_SWRI|SYPCR_SWP)
+#endif /* CONFIG_WATCHDOG */
+
+/*-----------------------------------------------------------------------
+ * TMCNTSC - Time Counter Status and Control                     4-40
+ *-----------------------------------------------------------------------
+ * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
+ * and enable Time Counter
+ */
+#define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control                 4-42
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
+ * Periodic timer
+ */
+#define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control                                   9-8
+ *-----------------------------------------------------------------------
+ * Ensure DFBRG is Divide by 16
+ */
+#define CONFIG_SYS_SCCR        SCCR_DFBRG01
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration                         13-7
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RCCR        0
+
+#define CONFIG_SYS_MIN_AM_MASK	0xC0000000
+/*-----------------------------------------------------------------------
+ * MPTPR - Memory Refresh Timer Prescaler Register              10-18
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_MPTPR       0x1F00
+
+/*-----------------------------------------------------------------------
+ * PSRT - Refresh Timer Register                                10-16
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_PSRT        0x0f
+
+/*-----------------------------------------------------------------------
+ * PSRT - SDRAM Mode Register                                   10-10
+ *-----------------------------------------------------------------------
+ */
+
+	/* SDRAM initialization values for 8-column chips
+	 */
+#define CONFIG_SYS_OR2_8COL	(CONFIG_SYS_MIN_AM_MASK		|\
+			 ORxS_BPD_4			|\
+			 ORxS_ROWST_PBI1_A7		|\
+			 ORxS_NUMR_12)
+
+#define CONFIG_SYS_PSDMR_8COL	(PSDMR_PBI			|\
+			 PSDMR_SDAM_A15_IS_A5		|\
+			 PSDMR_BSMA_A15_A17		|\
+			 PSDMR_SDA10_PBI1_A7		|\
+			 PSDMR_RFRC_7_CLK		|\
+			 PSDMR_PRETOACT_3W		|\
+			 PSDMR_ACTTORW_2W		|\
+			 PSDMR_LDOTOPRE_1C		|\
+			 PSDMR_WRC_1C			|\
+			 PSDMR_CL_2)
+
+	/* SDRAM initialization values for 9-column chips
+	 */
+#define CONFIG_SYS_OR2_9COL	(CONFIG_SYS_MIN_AM_MASK		|\
+			 ORxS_BPD_4			|\
+			 ORxS_ROWST_PBI1_A6		|\
+			 ORxS_NUMR_12)
+
+#define CONFIG_SYS_PSDMR_9COL	(PSDMR_PBI			|\
+			 PSDMR_SDAM_A16_IS_A5		|\
+			 PSDMR_BSMA_A15_A17		|\
+			 PSDMR_SDA10_PBI1_A6		|\
+			 PSDMR_RFRC_7_CLK		|\
+			 PSDMR_PRETOACT_3W		|\
+			 PSDMR_ACTTORW_2W		|\
+			 PSDMR_LDOTOPRE_1C		|\
+			 PSDMR_WRC_1C			|\
+			 PSDMR_CL_2)
+
+/*
+ * Init Memory Controller:
+ *
+ * Bank Bus     Machine PortSz  Device
+ * ---- ---     ------- ------  ------
+ *  0   60x     GPCM    8  bit  Boot ROM
+ *  1   60x     GPCM    64 bit  FLASH
+ *  2   60x     SDRAM   64 bit  SDRAM
+ *
+ */
+
+#define CONFIG_SYS_MRS_OFFS	0x00000000
+
+/* Bank 0 - FLASH
+ */
+#define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)  |\
+			 BRx_PS_16                      |\
+			 BRx_MS_GPCM_P                  |\
+			 BRx_V)
+
+#define CONFIG_SYS_OR0_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE)     |\
+			 ORxG_CSNT                      |\
+			 ORxG_ACS_DIV1                  |\
+			 ORxG_SCY_3_CLK                 |\
+			 ORxU_EHTR_8IDLE)
+
+
+/* Bank 2 - 60x bus SDRAM
+ */
+#ifndef CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_BR2_PRELIM  ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)  |\
+			 BRx_PS_64                      |\
+			 BRx_MS_SDRAM_P                 |\
+			 BRx_V)
+
+#define CONFIG_SYS_OR2_PRELIM	 CONFIG_SYS_OR2_8COL
+
+#define CONFIG_SYS_PSDMR	 CONFIG_SYS_PSDMR_8COL
+#endif /* CONFIG_SYS_RAMBOOT */
+
+#define CONFIG_SYS_BR4_PRELIM  ((RTC_BASE_ADDR & BRx_BA_MSK)   |\
+			 BRx_PS_8                       |\
+			 BRx_MS_UPMA                    |\
+			 BRx_V)
+
+#define CONFIG_SYS_OR4_PRELIM  (ORxU_AM_MSK | ORxU_BI)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_I82365
+
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	0x81000000
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	0x1000
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_IDE_PREINIT	1	/* Use preinit IDE hook */
+#define CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card Adapter */
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
+#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_BASE_ADDR	0xa0000000
+
+/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x100
+
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	0x100
+
+/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x108
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/atngw100.h b/qemu/roms/u-boot/include/configs/atngw100.h
new file mode 100644
index 000000000..9c81e3199
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/atngw100.h
@@ -0,0 +1,164 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * Configuration settings for the AVR32 Network Gateway
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/hardware.h>
+
+#define CONFIG_AT32AP
+#define CONFIG_AT32AP7000
+#define CONFIG_ATNGW100
+
+/*
+ * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
+ * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
+ * and the PBA bus to run at 1/4 the PLL frequency.
+ */
+#define CONFIG_PLL
+#define CONFIG_SYS_POWER_MANAGER
+#define CONFIG_SYS_OSC0_HZ			20000000
+#define CONFIG_SYS_PLL0_DIV			1
+#define CONFIG_SYS_PLL0_MUL			7
+#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES	16
+#define CONFIG_SYS_CLKDIV_CPU			0
+#define CONFIG_SYS_CLKDIV_HSB			1
+#define CONFIG_SYS_CLKDIV_PBA			2
+#define CONFIG_SYS_CLKDIV_PBB			1
+
+/* Reserve VM regions for SDRAM and NOR flash */
+#define CONFIG_SYS_NR_VM_REGIONS		2
+
+/*
+ * The PLLOPT register controls the PLL like this:
+ *   icp = PLLOPT<2>
+ *   ivco = PLLOPT<1:0>
+ *
+ * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
+ */
+#define CONFIG_SYS_PLL0_OPT			0x04
+
+#define CONFIG_USART_BASE		ATMEL_BASE_USART1
+#define CONFIG_USART_ID			1
+/* User serviceable stuff */
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#define CONFIG_STACKSIZE		(2048)
+
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_BOOTARGS							\
+	"console=ttyS0 root=/dev/mtdblock1 rootfstype=jffs2"
+#define CONFIG_BOOTCOMMAND						\
+	"fsload; bootm"
+
+/*
+ * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
+ * data on the serial line may interrupt the boot sequence.
+ */
+#define CONFIG_BOOTDELAY		1
+#define CONFIG_AUTOBOOT
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT		\
+	"Press SPACE to abort autoboot in %d seconds\n", bootdelay
+#define CONFIG_AUTOBOOT_DELAY_STR	"d"
+#define CONFIG_AUTOBOOT_STOP_STR	" "
+
+/*
+ * After booting the board for the first time, new ethernet addresses
+ * should be generated and assigned to the environment variables
+ * "ethaddr" and "eth1addr". This is normally done during production.
+ */
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
+
+/*
+ * BOOTP/DHCP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_SOURCE
+#undef CONFIG_CMD_XIMG
+
+#define CONFIG_ATMEL_USART
+#define CONFIG_MACB
+#define CONFIG_PORTMUX_PIO
+#define CONFIG_SYS_NR_PIOS			5
+#define CONFIG_SYS_HSDRAMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_ATMEL_MCI
+#define CONFIG_GENERIC_MMC
+#define CONFIG_ATMEL_SPI
+
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_ATMEL
+
+#define CONFIG_SYS_DCACHE_LINESZ		32
+#define CONFIG_SYS_ICACHE_LINESZ		32
+
+#define CONFIG_NR_DRAM_BANKS		1
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+
+#define CONFIG_SYS_FLASH_BASE			0x00000000
+#define CONFIG_SYS_FLASH_SIZE			0x800000
+#define CONFIG_SYS_MAX_FLASH_BANKS		1
+#define CONFIG_SYS_MAX_FLASH_SECT		135
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_TEXT_BASE		0x00000000
+
+#define CONFIG_SYS_INTRAM_BASE			INTERNAL_SRAM_BASE
+#define CONFIG_SYS_INTRAM_SIZE			INTERNAL_SRAM_SIZE
+#define CONFIG_SYS_SDRAM_BASE			EBI_SDRAM_BASE
+
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SIZE			65536
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
+
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
+
+#define CONFIG_SYS_MALLOC_LEN			(256*1024)
+#define CONFIG_SYS_DMA_ALLOC_LEN		(16384)
+
+/* Allow 4MB for the kernel run-time image */
+#define CONFIG_SYS_LOAD_ADDR			(EBI_SDRAM_BASE + 0x00400000)
+#define CONFIG_SYS_BOOTPARAMS_LEN		(16 * 1024)
+
+/* Other configuration settings that shouldn't have to change all that often */
+#define CONFIG_SYS_PROMPT			"U-Boot> "
+#define CONFIG_SYS_CBSIZE			256
+#define CONFIG_SYS_MAXARGS			16
+#define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+
+#define CONFIG_SYS_MEMTEST_START		EBI_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END			(CONFIG_SYS_MEMTEST_START + 0x1f00000)
+
+#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/atngw100mkii.h b/qemu/roms/u-boot/include/configs/atngw100mkii.h
new file mode 100644
index 000000000..066d09ab0
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/atngw100mkii.h
@@ -0,0 +1,185 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * Copyright (C) 2012 Andreas Bießmann <andreas.devel@googlemail.com>
+ *
+ * Configuration settings for the AVR32 Network Gateway
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/hardware.h>
+
+#define CONFIG_AT32AP
+#define CONFIG_AT32AP7000
+#define CONFIG_ATNGW100MKII
+
+/*
+ * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
+ * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
+ * and the PBA bus to run at 1/4 the PLL frequency.
+ */
+#define CONFIG_PLL
+#define CONFIG_SYS_POWER_MANAGER
+#define CONFIG_SYS_OSC0_HZ		20000000
+#define CONFIG_SYS_PLL0_DIV		1
+#define CONFIG_SYS_PLL0_MUL		7
+#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES	16
+/*
+ * Set the CPU running at:
+ * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
+ */
+#define CONFIG_SYS_CLKDIV_CPU		0
+/*
+ * Set the HSB running at:
+ * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
+ */
+#define CONFIG_SYS_CLKDIV_HSB		1
+/*
+ * Set the PBA running at:
+ * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
+ */
+#define CONFIG_SYS_CLKDIV_PBA		2
+/*
+ * Set the PBB running at:
+ * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
+ */
+#define CONFIG_SYS_CLKDIV_PBB		1
+
+/* Reserve VM regions for NOR flash, NAND flash and SDRAM */
+#define CONFIG_SYS_NR_VM_REGIONS	3
+
+/*
+ * The PLLOPT register controls the PLL like this:
+ *   icp = PLLOPT<2>
+ *   ivco = PLLOPT<1:0>
+ *
+ * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
+ */
+#define CONFIG_SYS_PLL0_OPT		0x04
+
+#define CONFIG_USART_BASE		ATMEL_BASE_USART1
+#define CONFIG_USART_ID			1
+
+/* User serviceable stuff */
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#define CONFIG_STACKSIZE		(2048)
+
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_BOOTARGS							\
+	"root=mtd:main rootfstype=jffs2"
+#define CONFIG_BOOTCOMMAND						\
+	"fsload 0x10400000 /uImage; bootm"
+
+/*
+ * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
+ * data on the serial line may interrupt the boot sequence.
+ */
+#define CONFIG_BOOTDELAY		1
+#define CONFIG_AUTOBOOT
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT		\
+	"Press SPACE to abort autoboot in %d seconds\n", bootdelay
+#define CONFIG_AUTOBOOT_DELAY_STR	"d"
+#define CONFIG_AUTOBOOT_STOP_STR	" "
+
+/*
+ * After booting the board for the first time, new ethernet addresses
+ * should be generated and assigned to the environment variables
+ * "ethaddr" and "eth1addr". This is normally done during production.
+ */
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
+#define CONFIG_NET_MULTI
+
+/*
+ * BOOTP/DHCP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_MII
+
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
+
+#define CONFIG_ATMEL_USART
+#define CONFIG_MACB
+#define CONFIG_PORTMUX_PIO
+#define CONFIG_SYS_NR_PIOS		5
+#define CONFIG_SYS_HSDRAMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_ATMEL_MCI
+#define CONFIG_GENERIC_MMC
+#define CONFIG_ATMEL_SPI
+
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_ATMEL
+
+#define CONFIG_SYS_DCACHE_LINESZ	32
+#define CONFIG_SYS_ICACHE_LINESZ	32
+
+#define CONFIG_NR_DRAM_BANKS		1
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_PROTECTION
+
+#define CONFIG_SYS_FLASH_BASE		0x00000000
+#define CONFIG_SYS_FLASH_SIZE		0x800000
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	135
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_SYS_INTRAM_BASE		INTERNAL_SRAM_BASE
+#define CONFIG_SYS_INTRAM_SIZE		INTERNAL_SRAM_SIZE
+#define CONFIG_SYS_SDRAM_BASE		EBI_SDRAM_BASE
+
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SIZE			65536
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
+
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
+
+#define CONFIG_SYS_MALLOC_LEN		(256*1024)
+#define CONFIG_SYS_DMA_ALLOC_LEN	(16384)
+
+/* Allow 4MB for the kernel run-time image */
+#define CONFIG_SYS_LOAD_ADDR		(EBI_SDRAM_BASE + 0x00400000)
+#define CONFIG_SYS_BOOTPARAMS_LEN	(16 * 1024)
+
+/* Other configuration settings that shouldn't have to change all that often */
+#define CONFIG_SYS_PROMPT		"U-Boot> "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x1f00000)
+
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/atstk1002.h b/qemu/roms/u-boot/include/configs/atstk1002.h
new file mode 100644
index 000000000..8f3fd0bb0
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/atstk1002.h
@@ -0,0 +1,178 @@
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * Configuration settings for the ATSTK1002 CPU daughterboard
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/hardware.h>
+
+#define CONFIG_AT32AP
+#define CONFIG_AT32AP7000
+#define CONFIG_ATSTK1002
+#define CONFIG_ATSTK1000
+
+/*
+ * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
+ * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
+ * PLL frequency.
+ * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz
+ */
+#define CONFIG_PLL
+#define CONFIG_SYS_POWER_MANAGER
+#define CONFIG_SYS_OSC0_HZ			20000000
+#define CONFIG_SYS_PLL0_DIV			1
+#define CONFIG_SYS_PLL0_MUL			7
+#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES	16
+/*
+ * Set the CPU running at:
+ * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
+ */
+#define CONFIG_SYS_CLKDIV_CPU			0
+/*
+ * Set the HSB running at:
+ * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
+ */
+#define CONFIG_SYS_CLKDIV_HSB			1
+/*
+ * Set the PBA running at:
+ * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
+ */
+#define CONFIG_SYS_CLKDIV_PBA			2
+/*
+ * Set the PBB running at:
+ * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
+ */
+#define CONFIG_SYS_CLKDIV_PBB			1
+
+/* Reserve VM regions for SDRAM and NOR flash */
+#define CONFIG_SYS_NR_VM_REGIONS		2
+
+/*
+ * The PLLOPT register controls the PLL like this:
+ *   icp = PLLOPT<2>
+ *   ivco = PLLOPT<1:0>
+ *
+ * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
+ */
+#define CONFIG_SYS_PLL0_OPT			0x04
+
+#define CONFIG_USART_BASE		ATMEL_BASE_USART1
+#define CONFIG_USART_ID			1
+
+/* User serviceable stuff */
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#define CONFIG_STACKSIZE		(2048)
+
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_BOOTARGS							\
+	"console=ttyS0 root=/dev/mmcblk0p1 fbmem=600k rootwait=1"
+
+#define CONFIG_BOOTCOMMAND						\
+	"fsload; bootm $(fileaddr)"
+
+/*
+ * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
+ * data on the serial line may interrupt the boot sequence.
+ */
+#define CONFIG_BOOTDELAY		1
+#define CONFIG_AUTOBOOT
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT		\
+	"Press SPACE to abort autoboot in %d seconds\n", bootdelay
+#define CONFIG_AUTOBOOT_DELAY_STR	"d"
+#define CONFIG_AUTOBOOT_STOP_STR	" "
+
+/*
+ * After booting the board for the first time, new ethernet addresses
+ * should be generated and assigned to the environment variables
+ * "ethaddr" and "eth1addr". This is normally done during production.
+ */
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MMC
+
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_SOURCE
+#undef CONFIG_CMD_XIMG
+
+#define CONFIG_ATMEL_USART
+#define CONFIG_MACB
+#define CONFIG_PORTMUX_PIO
+#define CONFIG_SYS_NR_PIOS			5
+#define CONFIG_SYS_HSDRAMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_ATMEL_MCI
+#define CONFIG_GENERIC_MMC
+
+#define CONFIG_SYS_DCACHE_LINESZ		32
+#define CONFIG_SYS_ICACHE_LINESZ		32
+
+#define CONFIG_NR_DRAM_BANKS		1
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+
+#define CONFIG_SYS_FLASH_BASE			0x00000000
+#define CONFIG_SYS_FLASH_SIZE			0x800000
+#define CONFIG_SYS_MAX_FLASH_BANKS		1
+#define CONFIG_SYS_MAX_FLASH_SECT		135
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_TEXT_BASE		0x00000000
+
+#define CONFIG_SYS_INTRAM_BASE			INTERNAL_SRAM_BASE
+#define CONFIG_SYS_INTRAM_SIZE			INTERNAL_SRAM_SIZE
+#define CONFIG_SYS_SDRAM_BASE			EBI_SDRAM_BASE
+
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SIZE			65536
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
+
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
+
+#define CONFIG_SYS_MALLOC_LEN			(256*1024)
+#define CONFIG_SYS_DMA_ALLOC_LEN		(16384)
+
+/* Allow 4MB for the kernel run-time image */
+#define CONFIG_SYS_LOAD_ADDR			(EBI_SDRAM_BASE + 0x00400000)
+#define CONFIG_SYS_BOOTPARAMS_LEN		(16 * 1024)
+
+/* Other configuration settings that shouldn't have to change all that often */
+#define CONFIG_SYS_PROMPT			"U-Boot> "
+#define CONFIG_SYS_CBSIZE			256
+#define CONFIG_SYS_MAXARGS			16
+#define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+
+#define CONFIG_SYS_MEMTEST_START		EBI_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END			(CONFIG_SYS_MEMTEST_START + 0x700000)
+#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/atstk1003.h b/qemu/roms/u-boot/include/configs/atstk1003.h
new file mode 100644
index 000000000..63704b198
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/atstk1003.h
@@ -0,0 +1,161 @@
+/*
+ * Copyright (C) 2007 Atmel Corporation
+ *
+ * Configuration settings for the ATSTK1003 CPU daughterboard
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/hardware.h>
+
+#define CONFIG_AT32AP
+#define CONFIG_AT32AP7001
+#define CONFIG_ATSTK1003
+#define CONFIG_ATSTK1000
+
+/*
+ * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
+ * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
+ * PLL frequency.
+ * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz
+ */
+#define CONFIG_PLL
+#define CONFIG_SYS_POWER_MANAGER
+#define CONFIG_SYS_OSC0_HZ			20000000
+#define CONFIG_SYS_PLL0_DIV			1
+#define CONFIG_SYS_PLL0_MUL			7
+#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES	16
+/*
+ * Set the CPU running at:
+ * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
+ */
+#define CONFIG_SYS_CLKDIV_CPU			0
+/*
+ * Set the HSB running at:
+ * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
+ */
+#define CONFIG_SYS_CLKDIV_HSB			1
+/*
+ * Set the PBA running at:
+ * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
+ */
+#define CONFIG_SYS_CLKDIV_PBA			2
+/*
+ * Set the PBB running at:
+ * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
+ */
+#define CONFIG_SYS_CLKDIV_PBB			1
+
+/* Reserve VM regions for SDRAM and NOR flash */
+#define CONFIG_SYS_NR_VM_REGIONS		2
+
+/*
+ * The PLLOPT register controls the PLL like this:
+ *   icp = PLLOPT<2>
+ *   ivco = PLLOPT<1:0>
+ *
+ * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
+ */
+#define CONFIG_SYS_PLL0_OPT			0x04
+
+#define CONFIG_USART_BASE		ATMEL_BASE_USART1
+#define CONFIG_USART_ID			1
+
+/* User serviceable stuff */
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#define CONFIG_STACKSIZE		(2048)
+
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_BOOTARGS							\
+	"console=ttyS0 root=/dev/mmcblk0p1 rootwait"
+
+#define CONFIG_BOOTCOMMAND						\
+	"mmc rescan; ext2load mmc 0:1 0x10400000 /boot/uImage; bootm"
+
+/*
+ * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
+ * data on the serial line may interrupt the boot sequence.
+ */
+#define CONFIG_BOOTDELAY		1
+#define CONFIG_AUTOBOOT
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT		\
+	"Press SPACE to abort autoboot in %d seconds\n", bootdelay
+#define CONFIG_AUTOBOOT_DELAY_STR	"d"
+#define CONFIG_AUTOBOOT_STOP_STR	" "
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MMC
+
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
+
+#define CONFIG_ATMEL_USART
+#define CONFIG_PORTMUX_PIO
+#define CONFIG_SYS_HSDRAMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_ATMEL_MCI
+#define CONFIG_GENERIC_MMC
+
+#define CONFIG_SYS_DCACHE_LINESZ		32
+#define CONFIG_SYS_ICACHE_LINESZ		32
+
+#define CONFIG_NR_DRAM_BANKS		1
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+
+#define CONFIG_SYS_FLASH_BASE			0x00000000
+#define CONFIG_SYS_FLASH_SIZE			0x800000
+#define CONFIG_SYS_MAX_FLASH_BANKS		1
+#define CONFIG_SYS_MAX_FLASH_SECT		135
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_TEXT_BASE		0x00000000
+
+#define CONFIG_SYS_INTRAM_BASE			INTERNAL_SRAM_BASE
+#define CONFIG_SYS_INTRAM_SIZE			INTERNAL_SRAM_SIZE
+#define CONFIG_SYS_SDRAM_BASE			EBI_SDRAM_BASE
+
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SIZE			65536
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
+
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
+
+#define CONFIG_SYS_MALLOC_LEN			(256*1024)
+
+/* Allow 4MB for the kernel run-time image */
+#define CONFIG_SYS_LOAD_ADDR			(EBI_SDRAM_BASE + 0x00400000)
+#define CONFIG_SYS_BOOTPARAMS_LEN		(16 * 1024)
+
+/* Other configuration settings that shouldn't have to change all that often */
+#define CONFIG_SYS_PROMPT			"U-Boot> "
+#define CONFIG_SYS_CBSIZE			256
+#define CONFIG_SYS_MAXARGS			16
+#define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+
+#define CONFIG_SYS_MEMTEST_START		EBI_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END			(CONFIG_SYS_MEMTEST_START + 0x700000)
+#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/atstk1004.h b/qemu/roms/u-boot/include/configs/atstk1004.h
new file mode 100644
index 000000000..331a60d76
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/atstk1004.h
@@ -0,0 +1,161 @@
+/*
+ * Copyright (C) 2007 Atmel Corporation
+ *
+ * Configuration settings for the ATSTK1003 CPU daughterboard
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/hardware.h>
+
+#define CONFIG_AT32AP
+#define CONFIG_AT32AP7002
+#define CONFIG_ATSTK1004
+#define CONFIG_ATSTK1000
+
+/*
+ * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
+ * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
+ * PLL frequency.
+ * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz
+ */
+#define CONFIG_PLL
+#define CONFIG_SYS_POWER_MANAGER
+#define CONFIG_SYS_OSC0_HZ			20000000
+#define CONFIG_SYS_PLL0_DIV			1
+#define CONFIG_SYS_PLL0_MUL			7
+#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES	16
+/*
+ * Set the CPU running at:
+ * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
+ */
+#define CONFIG_SYS_CLKDIV_CPU			0
+/*
+ * Set the HSB running at:
+ * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
+ */
+#define CONFIG_SYS_CLKDIV_HSB			1
+/*
+ * Set the PBA running at:
+ * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
+ */
+#define CONFIG_SYS_CLKDIV_PBA			2
+/*
+ * Set the PBB running at:
+ * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
+ */
+#define CONFIG_SYS_CLKDIV_PBB			1
+
+/* Reserve VM regions for SDRAM and NOR flash */
+#define CONFIG_SYS_NR_VM_REGIONS		2
+
+/*
+ * The PLLOPT register controls the PLL like this:
+ *   icp = PLLOPT<2>
+ *   ivco = PLLOPT<1:0>
+ *
+ * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
+ */
+#define CONFIG_SYS_PLL0_OPT			0x04
+
+#define CONFIG_USART_BASE		ATMEL_BASE_USART1
+#define CONFIG_USART_ID			1
+
+/* User serviceable stuff */
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#define CONFIG_STACKSIZE		(2048)
+
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_BOOTARGS							\
+	"console=ttyS0 root=/dev/mmcblk0p1 rootwait"
+
+#define CONFIG_BOOTCOMMAND						\
+	"mmc rescan; ext2load mmc 0:1 0x10200000 /boot/uImage; bootm"
+
+/*
+ * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
+ * data on the serial line may interrupt the boot sequence.
+ */
+#define CONFIG_BOOTDELAY		1
+#define CONFIG_AUTOBOOT
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT		\
+	"Press SPACE to abort autoboot in %d seconds\n", bootdelay
+#define CONFIG_AUTOBOOT_DELAY_STR	"d"
+#define CONFIG_AUTOBOOT_STOP_STR	" "
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MMC
+
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
+
+#define CONFIG_ATMEL_USART
+#define CONFIG_PORTMUX_PIO
+#define CONFIG_SYS_HSDRAMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_ATMEL_MCI
+#define CONFIG_GENERIC_MMC
+
+#define CONFIG_SYS_DCACHE_LINESZ		32
+#define CONFIG_SYS_ICACHE_LINESZ		32
+
+#define CONFIG_NR_DRAM_BANKS		1
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+
+#define CONFIG_SYS_FLASH_BASE			0x00000000
+#define CONFIG_SYS_FLASH_SIZE			0x800000
+#define CONFIG_SYS_MAX_FLASH_BANKS		1
+#define CONFIG_SYS_MAX_FLASH_SECT		135
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_TEXT_BASE		0x00000000
+
+#define CONFIG_SYS_INTRAM_BASE			INTERNAL_SRAM_BASE
+#define CONFIG_SYS_INTRAM_SIZE			INTERNAL_SRAM_SIZE
+#define CONFIG_SYS_SDRAM_BASE			EBI_SDRAM_BASE
+
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SIZE			65536
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
+
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
+
+#define CONFIG_SYS_MALLOC_LEN			(256*1024)
+
+/* Allow 2MB for the kernel run-time image */
+#define CONFIG_SYS_LOAD_ADDR			(EBI_SDRAM_BASE + 0x00200000)
+#define CONFIG_SYS_BOOTPARAMS_LEN		(16 * 1024)
+
+/* Other configuration settings that shouldn't have to change all that often */
+#define CONFIG_SYS_PROMPT			"U-Boot> "
+#define CONFIG_SYS_CBSIZE			256
+#define CONFIG_SYS_MAXARGS			16
+#define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+
+#define CONFIG_SYS_MEMTEST_START		EBI_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END			(CONFIG_SYS_MEMTEST_START + 0x700000)
+#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/atstk1006.h b/qemu/roms/u-boot/include/configs/atstk1006.h
new file mode 100644
index 000000000..bbe0aea86
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/atstk1006.h
@@ -0,0 +1,179 @@
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * Configuration settings for the ATSTK1002 CPU daughterboard
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/hardware.h>
+
+#define CONFIG_AT32AP
+#define CONFIG_AT32AP7000
+#define CONFIG_ATSTK1006
+#define CONFIG_ATSTK1000
+
+
+/*
+ * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
+ * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
+ * PLL frequency.
+ * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz
+ */
+#define CONFIG_PLL
+#define CONFIG_SYS_POWER_MANAGER
+#define CONFIG_SYS_OSC0_HZ			20000000
+#define CONFIG_SYS_PLL0_DIV			1
+#define CONFIG_SYS_PLL0_MUL			7
+#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES	16
+/*
+ * Set the CPU running at:
+ * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
+ */
+#define CONFIG_SYS_CLKDIV_CPU			0
+/*
+ * Set the HSB running at:
+ * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
+ */
+#define CONFIG_SYS_CLKDIV_HSB			1
+/*
+ * Set the PBA running at:
+ * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
+ */
+#define CONFIG_SYS_CLKDIV_PBA			2
+/*
+ * Set the PBB running at:
+ * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
+ */
+#define CONFIG_SYS_CLKDIV_PBB			1
+
+/* Reserve VM regions for SDRAM and NOR flash */
+#define CONFIG_SYS_NR_VM_REGIONS		2
+
+/*
+ * The PLLOPT register controls the PLL like this:
+ *   icp = PLLOPT<2>
+ *   ivco = PLLOPT<1:0>
+ *
+ * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
+ */
+#define CONFIG_SYS_PLL0_OPT			0x04
+
+#define CONFIG_USART_BASE		ATMEL_BASE_USART1
+#define CONFIG_USART_ID			1
+
+/* User serviceable stuff */
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#define CONFIG_STACKSIZE		(2048)
+
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_BOOTARGS							\
+	"console=ttyS0 root=mtd3 fbmem=2400k"
+
+#define CONFIG_BOOTCOMMAND						\
+	"fsload; bootm $(fileaddr)"
+
+/*
+ * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
+ * data on the serial line may interrupt the boot sequence.
+ */
+#define CONFIG_BOOTDELAY		1
+#define CONFIG_AUTOBOOT
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT		\
+	"Press SPACE to abort autoboot in %d seconds\n", bootdelay
+#define CONFIG_AUTOBOOT_DELAY_STR	"d"
+#define CONFIG_AUTOBOOT_STOP_STR	" "
+
+/*
+ * After booting the board for the first time, new ethernet addresses
+ * should be generated and assigned to the environment variables
+ * "ethaddr" and "eth1addr". This is normally done during production.
+ */
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MMC
+
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_SOURCE
+#undef CONFIG_CMD_XIMG
+
+#define CONFIG_ATMEL_USART
+#define CONFIG_MACB
+#define CONFIG_PORTMUX_PIO
+#define CONFIG_SYS_NR_PIOS			5
+#define CONFIG_SYS_HSDRAMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_ATMEL_MCI
+#define CONFIG_GENERIC_MMC
+
+#define CONFIG_SYS_DCACHE_LINESZ		32
+#define CONFIG_SYS_ICACHE_LINESZ		32
+
+#define CONFIG_NR_DRAM_BANKS		1
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+
+#define CONFIG_SYS_FLASH_BASE			0x00000000
+#define CONFIG_SYS_FLASH_SIZE			0x800000
+#define CONFIG_SYS_MAX_FLASH_BANKS		1
+#define CONFIG_SYS_MAX_FLASH_SECT		135
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_TEXT_BASE		0x00000000
+
+#define CONFIG_SYS_INTRAM_BASE			INTERNAL_SRAM_BASE
+#define CONFIG_SYS_INTRAM_SIZE			INTERNAL_SRAM_SIZE
+#define CONFIG_SYS_SDRAM_BASE			EBI_SDRAM_BASE
+
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SIZE			65536
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
+
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
+
+#define CONFIG_SYS_MALLOC_LEN			(256*1024)
+#define CONFIG_SYS_DMA_ALLOC_LEN		(16384)
+
+/* Allow 4MB for the kernel run-time image */
+#define CONFIG_SYS_LOAD_ADDR			(EBI_SDRAM_BASE + 0x00400000)
+#define CONFIG_SYS_BOOTPARAMS_LEN		(16 * 1024)
+
+/* Other configuration settings that shouldn't have to change all that often */
+#define CONFIG_SYS_PROMPT			"U-Boot> "
+#define CONFIG_SYS_CBSIZE			256
+#define CONFIG_SYS_MAXARGS			16
+#define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+
+#define CONFIG_SYS_MEMTEST_START		EBI_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END			(CONFIG_SYS_MEMTEST_START + 0x3f00000)
+#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/axs101.h b/qemu/roms/u-boot/include/configs/axs101.h
new file mode 100644
index 000000000..c22d6d0c7
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/axs101.h
@@ -0,0 +1,181 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CONFIG_AXS101_H_
+#define _CONFIG_AXS101_H_
+
+/*
+ *  CPU configuration
+ */
+#define CONFIG_ARC700
+#define CONFIG_ARC_MMU_VER		3
+#define CONFIG_SYS_CACHELINE_SIZE	32
+#define CONFIG_SYS_CLK_FREQ		750000000
+#define CONFIG_SYS_TIMER_RATE		CONFIG_SYS_CLK_FREQ
+
+/* NAND controller DMA doesn't work correctly with D$ enabled */
+#define CONFIG_SYS_DCACHE_OFF
+
+/*
+ * Board configuration
+ */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is in RAM already */
+
+#define CONFIG_ARCH_EARLY_INIT_R
+
+#define ARC_FPGA_PERIPHERAL_BASE	0xE0000000
+#define ARC_APB_PERIPHERAL_BASE		0xF0000000
+#define ARC_DWMMC_BASE			(ARC_FPGA_PERIPHERAL_BASE + 0x15000)
+#define ARC_DWGMAC_BASE			(ARC_FPGA_PERIPHERAL_BASE + 0x18000)
+
+/*
+ * Memory configuration
+ */
+#define CONFIG_SYS_TEXT_BASE		0x81000000
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_SDRAM_SIZE		0x20000000	/* 512 Mb */
+
+#define CONFIG_SYS_INIT_SP_ADDR		\
+	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_MALLOC_LEN		0x200000	/* 2 MB */
+#define CONFIG_SYS_BOOTM_LEN		0x2000000	/* 32 MB */
+#define CONFIG_SYS_LOAD_ADDR		0x82000000
+
+/*
+ * NAND Flash configuration
+ */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_NAND_BASE		(ARC_FPGA_PERIPHERAL_BASE + 0x16000)
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+
+/*
+ * UART configuration
+ *
+ * CONFIG_CONS_INDEX = 1 - Debug UART
+ * CONFIG_CONS_INDEX = 4 - FPGA UART connected to FTDI/USB
+ */
+#define CONFIG_CONS_INDEX		4
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#if (CONFIG_CONS_INDEX == 1)
+	/* Debug UART */
+#	define CONFIG_SYS_NS16550_CLK		33333000
+#else
+	/* FPGA UARTs use different clock */
+#	define CONFIG_SYS_NS16550_CLK		33333333
+#endif
+#define CONFIG_SYS_NS16550_COM1		(ARC_APB_PERIPHERAL_BASE + 0x5000)
+#define CONFIG_SYS_NS16550_COM2		(ARC_FPGA_PERIPHERAL_BASE + 0x20000)
+#define CONFIG_SYS_NS16550_COM3		(ARC_FPGA_PERIPHERAL_BASE + 0x21000)
+#define CONFIG_SYS_NS16550_COM4		(ARC_FPGA_PERIPHERAL_BASE + 0x22000)
+#define CONFIG_SYS_NS16550_MEM32
+
+#define CONFIG_BAUDRATE			115200
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C
+#define CONFIG_DW_I2C
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_ENV_EEPROM_BUS	2
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_I2C_SLAVE		0
+#define CONFIG_SYS_I2C_BASE		0xE001D000
+#define CONFIG_SYS_I2C_BASE1		0xE001E000
+#define CONFIG_SYS_I2C_BASE2		0xE001F000
+#define CONFIG_SYS_I2C_BUS_MAX		3
+#define IC_CLK				50
+
+/*
+ * EEPROM configuration
+ */
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR		(0xA8 >> 1)
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	64
+
+/*
+ * SD/MMC configuration
+ */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DWMMC
+#define CONFIG_DOS_PARTITION
+
+/*
+ * Ethernet PHY configuration
+ */
+#define CONFIG_PHYLIB
+#define CONFIG_MII
+#define CONFIG_PHY_GIGE
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_DESIGNWARE_ETH
+#define CONFIG_DW_AUTONEG
+#define CONFIG_DW_SEARCH_PHY
+#define CONFIG_NET_MULTI
+
+/*
+ * Command line configuration
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_RARP
+
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_MAXARGS		16
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_IS_IN_EEPROM
+#define CONFIG_ENV_SIZE			0x00200		/* 512 bytes */
+#define CONFIG_ENV_OFFSET		0
+
+/*
+ * Environment configuration
+ */
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_BOOTFILE			"uImage"
+#define CONFIG_BOOTARGS			"console=ttyS3,115200n8"
+#define CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR
+
+/*
+ * Console configuration
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT		"AXS# "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+						sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/*
+ * Misc utility configuration
+ */
+#define CONFIG_BOUNCE_BUFFER
+
+#endif /* _CONFIG_AXS101_H_ */
diff --git a/qemu/roms/u-boot/include/configs/balloon3.h b/qemu/roms/u-boot/include/configs/balloon3.h
new file mode 100644
index 000000000..5228ba6ef
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/balloon3.h
@@ -0,0 +1,248 @@
+/*
+ * Balloon3 configuration file
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef	__CONFIG_H
+#define	__CONFIG_H
+
+/*
+ * High Level Board Configuration Options
+ */
+#define	CONFIG_CPU_PXA27X		1	/* Marvell PXA270 CPU */
+#define	CONFIG_BALLOON3		1	/* Balloon3 board */
+
+/*
+ * Environment settings
+ */
+#define	CONFIG_ENV_OVERWRITE
+#define	CONFIG_SYS_MALLOC_LEN		(128*1024)
+#define	CONFIG_ARCH_CPU_INIT
+#define	CONFIG_BOOTCOMMAND						\
+	"fpga load 0x0 0x50000 0x62638; "				\
+	"if usb reset && fatload usb 0 0xa4000000 uImage; then "	\
+		"bootm 0xa4000000; "					\
+	"fi; "								\
+	"bootm 0xd0000;"
+#define	CONFIG_BOOTARGS			"console=tty0 console=ttyS2,115200"
+#define	CONFIG_TIMESTAMP
+#define	CONFIG_BOOTDELAY		2	/* Autoboot delay */
+#define	CONFIG_CMDLINE_TAG
+#define	CONFIG_SETUP_MEMORY_TAGS
+#define	CONFIG_SYS_TEXT_BASE		0x0
+#define	CONFIG_LZMA			/* LZMA compression support */
+
+/*
+ * Serial Console Configuration
+ */
+#define	CONFIG_PXA_SERIAL
+#define	CONFIG_STUART			1
+#define CONFIG_CONS_INDEX		2
+#define	CONFIG_BAUDRATE			115200
+
+/*
+ * Bootloader Components Configuration
+ */
+#include <config_cmd_default.h>
+
+#undef	CONFIG_CMD_NET
+#undef	CONFIG_CMD_NFS
+#undef	CONFIG_CMD_ENV
+#undef	CONFIG_CMD_IMLS
+#define	CONFIG_CMD_USB
+#define	CONFIG_CMD_FPGA
+#undef	CONFIG_LCD
+
+/*
+ * KGDB
+ */
+#ifdef	CONFIG_CMD_KGDB
+#define	CONFIG_KGDB_BAUDRATE		230400	/* kgdb serial port speed */
+#endif
+
+/*
+ * HUSH Shell Configuration
+ */
+#define	CONFIG_SYS_HUSH_PARSER		1
+
+#define	CONFIG_SYS_LONGHELP
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define	CONFIG_SYS_PROMPT		"$ "
+#else
+#endif
+#define	CONFIG_SYS_CBSIZE		256
+#define	CONFIG_SYS_PBSIZE		\
+	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define	CONFIG_SYS_MAXARGS		16
+#define	CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+#define	CONFIG_SYS_DEVICE_NULLDEV	1
+
+/*
+ * Clock Configuration
+ */
+#undef	CONFIG_SYS_CLKS_IN_HZ
+#define	CONFIG_SYS_CPUSPEED		0x290		/* 520MHz */
+
+/*
+ * DRAM Map
+ */
+#define	CONFIG_NR_DRAM_BANKS		3		/* 2 banks of DRAM */
+#define	PHYS_SDRAM_1			0xa0000000	/* SDRAM Bank #1 */
+#define	PHYS_SDRAM_1_SIZE		0x08000000	/* 128 MB */
+#define	PHYS_SDRAM_2			0xb0000000	/* SDRAM Bank #2 */
+#define	PHYS_SDRAM_2_SIZE		0x08000000	/* 128 MB */
+#define	PHYS_SDRAM_3			0x80000000	/* SDRAM Bank #2 */
+#define	PHYS_SDRAM_3_SIZE		0x08000000	/* 128 MB */
+
+#define	CONFIG_SYS_DRAM_BASE		0xa0000000	/* CS0 */
+#define	CONFIG_SYS_DRAM_SIZE		0x18000000	/* 384 MB DRAM */
+
+#define	CONFIG_SYS_MEMTEST_START	0xa0400000	/* memtest works on */
+#define	CONFIG_SYS_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM */
+
+#define	CONFIG_SYS_LOAD_ADDR		0xa1000000
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define	CONFIG_SYS_INIT_SP_ADDR		\
+	(PHYS_SDRAM_1 + GENERATED_GBL_DATA_SIZE + 2048)
+
+/*
+ * NOR FLASH
+ */
+#ifdef	CONFIG_CMD_FLASH
+#define	PHYS_FLASH_1			0x00000000	/* Flash Bank #1 */
+#define	PHYS_FLASH_SIZE			0x00800000	/* 8 MB */
+#define	CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+
+#define	CONFIG_SYS_FLASH_CFI
+#define	CONFIG_FLASH_CFI_DRIVER		1
+#define	CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
+
+#define	CONFIG_SYS_MAX_FLASH_BANKS	1
+#define	CONFIG_SYS_MAX_FLASH_SECT	256
+
+#define	CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+
+#define	CONFIG_SYS_FLASH_ERASE_TOUT	240000
+#define	CONFIG_SYS_FLASH_WRITE_TOUT	240000
+#define	CONFIG_SYS_FLASH_LOCK_TOUT	240000
+#define	CONFIG_SYS_FLASH_UNLOCK_TOUT	240000
+#define	CONFIG_SYS_FLASH_PROTECTION
+#define	CONFIG_ENV_IS_IN_FLASH
+#else
+#define	CONFIG_SYS_NO_FLASH
+#define	CONFIG_SYS_ENV_IS_NOWHERE
+#endif
+
+#define	CONFIG_SYS_MONITOR_BASE		0x000000
+#define	CONFIG_SYS_MONITOR_LEN		0x40000
+
+#define	CONFIG_ENV_SIZE			0x2000
+#define	CONFIG_ENV_ADDR			0x40000
+#define	CONFIG_ENV_SECT_SIZE		0x10000
+
+/*
+ * GPIO settings
+ */
+#define	CONFIG_SYS_GPSR0_VAL	0x307dc7fd
+#define	CONFIG_SYS_GPSR1_VAL	0x03cffa4e
+#define	CONFIG_SYS_GPSR2_VAL	0x7131c000
+#define	CONFIG_SYS_GPSR3_VAL	0x01e1f3ff
+
+#define	CONFIG_SYS_GPCR0_VAL	0x0
+#define	CONFIG_SYS_GPCR1_VAL	0x0
+#define	CONFIG_SYS_GPCR2_VAL	0x0
+#define	CONFIG_SYS_GPCR3_VAL	0x0
+
+#define	CONFIG_SYS_GPDR0_VAL	0xc0f98e02
+#define	CONFIG_SYS_GPDR1_VAL	0xfcffa8b7
+#define	CONFIG_SYS_GPDR2_VAL	0x22e3ffff
+#define	CONFIG_SYS_GPDR3_VAL	0x000201fe
+
+#define	CONFIG_SYS_GAFR0_L_VAL	0x96c00000
+#define	CONFIG_SYS_GAFR0_U_VAL	0xa5e5459b
+#define	CONFIG_SYS_GAFR1_L_VAL	0x699b759a
+#define	CONFIG_SYS_GAFR1_U_VAL	0xaaa5a5aa
+#define	CONFIG_SYS_GAFR2_L_VAL	0xaaaaaaaa
+#define	CONFIG_SYS_GAFR2_U_VAL	0x01f9a6aa
+#define	CONFIG_SYS_GAFR3_L_VAL	0x54510003
+#define	CONFIG_SYS_GAFR3_U_VAL	0x00001599
+
+#define	CONFIG_SYS_PSSR_VAL	0x30
+
+/*
+ * Clock settings
+ */
+#define	CONFIG_SYS_CKEN		0xffffffff
+#define	CONFIG_SYS_CCCR		0x00000290
+
+/*
+ * Memory settings
+ */
+#define	CONFIG_SYS_MSC0_VAL	0x7ff07ff8
+#define	CONFIG_SYS_MSC1_VAL	0x7ff07ff0
+#define	CONFIG_SYS_MSC2_VAL	0x74a42491
+#define	CONFIG_SYS_MDCNFG_VAL	0x89d309d3
+#define	CONFIG_SYS_MDREFR_VAL	0x001d8018
+#define	CONFIG_SYS_MDMRS_VAL	0x00220022
+#define	CONFIG_SYS_FLYCNFG_VAL	0x00000000
+#define	CONFIG_SYS_SXCNFG_VAL	0x00000000
+#define	CONFIG_SYS_MEM_BUF_IMP	0x0f
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define	CONFIG_SYS_MECR_VAL	0x00000000
+#define	CONFIG_SYS_MCMEM0_VAL	0x00014307
+#define	CONFIG_SYS_MCMEM1_VAL	0x00014307
+#define	CONFIG_SYS_MCATT0_VAL	0x0001c787
+#define	CONFIG_SYS_MCATT1_VAL	0x0001c787
+#define	CONFIG_SYS_MCIO0_VAL	0x0001430f
+#define	CONFIG_SYS_MCIO1_VAL	0x0001430f
+
+/*
+ * LCD
+ */
+#ifdef	CONFIG_LCD
+#define	CONFIG_BALLOON3LCD
+#define	CONFIG_VIDEO_LOGO
+#define	CONFIG_CMD_BMP
+#define	CONFIG_SPLASH_SCREEN
+#define	CONFIG_SPLASH_SCREEN_ALIGN
+#define	CONFIG_VIDEO_BMP_GZIP
+#define	CONFIG_VIDEO_BMP_RLE8
+#define	CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(2 << 20)
+#endif
+
+/*
+ * USB
+ */
+#ifdef	CONFIG_CMD_USB
+#define	CONFIG_USB_OHCI_NEW
+#define	CONFIG_SYS_USB_OHCI_CPU_INIT
+#define	CONFIG_SYS_USB_OHCI_BOARD_INIT
+#define	CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+#define	CONFIG_SYS_USB_OHCI_REGS_BASE	0x4C000000
+#define	CONFIG_SYS_USB_OHCI_SLOT_NAME	"balloon3"
+#define	CONFIG_USB_STORAGE
+#define	CONFIG_DOS_PARTITION
+#define	CONFIG_CMD_FAT
+#define	CONFIG_CMD_EXT2
+#endif
+
+/*
+ * FPGA
+ */
+#ifdef	CONFIG_CMD_FPGA
+#define	CONFIG_FPGA
+#define	CONFIG_FPGA_XILINX
+#define	CONFIG_FPGA_SPARTAN3
+#define	CONFIG_SYS_FPGA_PROG_FEEDBACK
+#define	CONFIG_SYS_FPGA_WAIT	1000
+#define	CONFIG_MAX_FPGA_DEVICES	1
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/bamboo.h b/qemu/roms/u-boot/include/configs/bamboo.h
new file mode 100644
index 000000000..6ba4aaf8c
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/bamboo.h
@@ -0,0 +1,222 @@
+/*
+ * (C) Copyright 2005-2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/************************************************************************
+ * bamboo.h - configuration for BAMBOO board
+ ***********************************************************************/
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_BAMBOO		1	/* Board is BAMBOO              */
+#define CONFIG_440EP		1	/* Specific PPC440EP support    */
+#define CONFIG_440		1	/* ... PPC440 family	        */
+#define CONFIG_SYS_CLK_FREQ	33333333    /* external freq to pll	*/
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xFFFA0000
+#endif
+
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME		bamboo
+#include "amcc-common.h"
+
+#define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f	*/
+
+/*
+ * Please note that, if NAND support is enabled, the 2nd ethernet port
+ * can't be used because of pin multiplexing. So, if you want to use the
+ * 2nd ethernet port you have to "undef" the following define.
+ */
+#define CONFIG_BAMBOO_NAND      1       /* enable nand flash support    */
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_FLASH_BASE	        0xfff00000	    /* start of FLASH	*/
+#define CONFIG_SYS_PCI_MEMBASE	        0xa0000000	    /* mapped pci memory*/
+#define CONFIG_SYS_PCI_MEMBASE1        CONFIG_SYS_PCI_MEMBASE  + 0x10000000
+#define CONFIG_SYS_PCI_MEMBASE2        CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
+#define CONFIG_SYS_PCI_MEMBASE3        CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
+
+/*Don't change either of these*/
+#define CONFIG_SYS_PCI_BASE		0xe0000000	    /* internal PCI regs*/
+/*Don't change either of these*/
+
+#define CONFIG_SYS_USB_DEVICE          0x50000000
+#define CONFIG_SYS_NVRAM_BASE_ADDR     0x80000000
+#define CONFIG_SYS_BOOT_BASE_ADDR      0xf0000000
+#define CONFIG_SYS_NAND_ADDR           0x90000000
+#define CONFIG_SYS_NAND2_ADDR          0x94000000
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in SDRAM)
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_INIT_RAM_DCACHE	1		/* d-cache as init ram	*/
+#define CONFIG_SYS_INIT_RAM_ADDR	0x70000000	/* DCache       */
+#define CONFIG_SYS_INIT_RAM_SIZE	(4 << 10)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#define CONFIG_SYS_EXT_SERIAL_CLOCK	11059200 /* use external 11.059MHz clk	*/
+
+/*-----------------------------------------------------------------------
+ * NVRAM/RTC
+ *
+ * NOTE: The RTC registers are located at 0x7FFF0 - 0x7FFFF
+ * The DS1558 code assumes this condition
+ *
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_NVRAM_SIZE	        (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs     */
+#define CONFIG_RTC_DS1556	1		         /* DS1556 RTC		*/
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+#define CONFIG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	3	/* number of banks			*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* sectors per device			*/
+
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CONFIG_SYS_FLASH_ADDR0         0x555
+#define CONFIG_SYS_FLASH_ADDR1         0x2aa
+#define CONFIG_SYS_FLASH_WORD_SIZE     unsigned char
+
+#define CONFIG_SYS_FLASH_2ND_16BIT_DEV 1	/* bamboo has 8 and 16bit device	*/
+#define CONFIG_SYS_FLASH_2ND_ADDR      0x87800000  /* bamboo has 8 and 16bit device	*/
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	0x10000	/* size of one complete sector		*/
+#define CONFIG_ENV_ADDR		((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
+#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+#endif /* CONFIG_ENV_IS_IN_FLASH */
+
+/*-----------------------------------------------------------------------
+ * NAND FLASH
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_MAX_NAND_DEVICE	2
+#define CONFIG_SYS_NAND_BASE		(CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_ADDR + 2 }
+#define CONFIG_SYS_NAND_SELECT_DEVICE  1	/* nand driver supports mutipl. chips	*/
+#define CONFIG_SYS_NAND_CS		1
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------------- */
+#define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for setup             */
+#undef CONFIG_DDR_ECC			/* don't use ECC			*/
+#define CONFIG_SYS_SIMULATE_SPD_EEPROM	0xff	/* simulate spd eeprom on this address	*/
+#define SPD_EEPROM_ADDRESS	{CONFIG_SYS_SIMULATE_SPD_EEPROM, 0x50, 0x51}
+#define CONFIG_SYS_MBYTES_SDRAM	(64)	/* 64MB fixed size for early-sdram-init */
+#define CONFIG_PROG_SDRAM_TLB
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
+
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR	(0xa8>>1)
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+#ifdef CONFIG_ENV_IS_IN_EEPROM
+#define CONFIG_ENV_SIZE		0x200	    /* Size of Environment vars */
+#define CONFIG_ENV_OFFSET		0x0
+#endif /* CONFIG_ENV_IS_IN_EEPROM */
+
+/*
+ * Default environment variables
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_AMCC_DEF_ENV						\
+	CONFIG_AMCC_DEF_ENV_POWERPC					\
+	CONFIG_AMCC_DEF_ENV_PPC_OLD					\
+	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
+	"kernel_addr=fff00000\0"					\
+	"ramdisk_addr=fff10000\0"					\
+	""
+
+#define CONFIG_HAS_ETH0
+#define CONFIG_PHY_ADDR		0	/* PHY address, See schematics	*/
+#define CONFIG_PHY1_ADDR        1
+
+#ifndef CONFIG_BAMBOO_NAND
+#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
+#endif /* CONFIG_BAMBOO_NAND */
+
+#ifdef CONFIG_440EP
+/* USB */
+#define CONFIG_USB_OHCI
+#define CONFIG_USB_STORAGE
+
+/*Comment this out to enable USB 1.1 device*/
+#define USB_2_0_DEVICE
+#endif /*CONFIG_440EP*/
+
+/*
+ * Commands additional to the ones defined in amcc-common.h
+ */
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_USB
+
+#ifdef CONFIG_BAMBOO_NAND
+#define CONFIG_CMD_NAND
+#endif
+
+#define CONFIG_SUPPORT_VFAT
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+/* General PCI */
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#undef  CONFIG_PCI_PNP			/* do (not) pci plug-and-play   */
+#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
+#define CONFIG_SYS_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
+
+/* Board-specific PCI */
+#define CONFIG_SYS_PCI_TARGET_INIT
+#define CONFIG_SYS_PCI_MASTER_INIT
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
+#define CONFIG_SYS_PCI_SUBSYS_ID       0xcafe	/* Whatever */
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/bcm28155_ap.h b/qemu/roms/u-boot/include/configs/bcm28155_ap.h
new file mode 100644
index 000000000..e93b855f8
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/bcm28155_ap.h
@@ -0,0 +1,140 @@
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:      GPL-2.0+
+ */
+
+#ifndef __BCM28155_AP_H
+#define __BCM28155_AP_H
+
+#include <linux/sizes.h>
+#include <asm/arch/sysmap.h>
+
+/* Architecture, CPU, chip, mach, etc */
+#define CONFIG_ARMV7
+#define CONFIG_KONA
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * Memory configuration
+ */
+#define CONFIG_SYS_TEXT_BASE		0xae000000
+
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CONFIG_SYS_SDRAM_SIZE		0x80000000
+#define CONFIG_NR_DRAM_BANKS		1
+
+#define CONFIG_SYS_MALLOC_LEN		SZ_4M	/* see armv7/start.S. */
+#define CONFIG_STACKSIZE		SZ_256K
+
+/* GPIO Driver */
+#define CONFIG_KONA_GPIO
+
+/* MMC/SD Driver */
+#define CONFIG_SDHCI
+#define CONFIG_MMC_SDMA
+#define CONFIG_KONA_SDHCI
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+
+#define CONFIG_SYS_SDIO_BASE0 SDIO1_BASE_ADDR
+#define CONFIG_SYS_SDIO_BASE1 SDIO2_BASE_ADDR
+#define CONFIG_SYS_SDIO_BASE2 SDIO3_BASE_ADDR
+#define CONFIG_SYS_SDIO_BASE3 SDIO4_BASE_ADDR
+#define CONFIG_SYS_SDIO0_MAX_CLK 48000000
+#define CONFIG_SYS_SDIO1_MAX_CLK 48000000
+#define CONFIG_SYS_SDIO2_MAX_CLK 48000000
+#define CONFIG_SYS_SDIO3_MAX_CLK 48000000
+#define CONFIG_SYS_SDIO0 "sdio1"
+#define CONFIG_SYS_SDIO1 "sdio2"
+#define CONFIG_SYS_SDIO2 "sdio3"
+#define CONFIG_SYS_SDIO3 "sdio4"
+
+/* I2C Driver */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_KONA
+#define CONFIG_SYS_SPD_BUS_NUM	3	/* Start with PMU bus */
+#define CONFIG_SYS_MAX_I2C_BUS	4
+#define CONFIG_SYS_I2C_BASE0	BSC1_BASE_ADDR
+#define CONFIG_SYS_I2C_BASE1	BSC2_BASE_ADDR
+#define CONFIG_SYS_I2C_BASE2	BSC3_BASE_ADDR
+#define CONFIG_SYS_I2C_BASE3	PMU_BSC_BASE_ADDR
+
+/* Timer Driver */
+#define CONFIG_SYS_TIMER_RATE		32000
+#define CONFIG_SYS_TIMER_COUNTER	(TIMER_BASE_ADDR + 4) /* STCLO offset */
+
+/* Init functions */
+#define CONFIG_MISC_INIT_R	/* board's misc_init_r function */
+
+/* Some commands use this as the default load address */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE
+
+/* No mtest functions as recommended */
+#undef CONFIG_CMD_MEMORY
+
+/*
+ * This is the initial SP which is used only briefly for relocating the u-boot
+ * image to the top of SDRAM. After relocation u-boot moves the stack to the
+ * proper place.
+ */
+#define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SYS_TEXT_BASE
+
+/* Serial Info */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+/* Post pad 3 bytes after each reg addr */
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		13000000
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550_COM1		0x3e000000
+
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_ENV_SIZE			0x10000
+#define CONFIG_ENV_IS_NOWHERE
+
+#define CONFIG_SYS_NO_FLASH	/* Not using NAND/NOR unmanaged flash */
+
+/* console configuration */
+#define CONFIG_SYS_CBSIZE		1024	/* Console buffer size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+			sizeof(CONFIG_SYS_PROMPT) + 16)	/* Printbuffer size */
+#define CONFIG_SYS_MAXARGS		64
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+/*
+ * One partition type must be defined for part.c
+ * This is necessary for the fatls command to work on an SD card
+ * for example.
+ */
+#define CONFIG_DOS_PARTITION
+
+/* version string, parser, etc */
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+
+/* Initial upstream - boot to cmd prompt only */
+#define CONFIG_BOOTCOMMAND		""
+
+/* Commands */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_GPIO
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_FAT_WRITE
+
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+
+#endif /* __BCM28155_AP_H */
diff --git a/qemu/roms/u-boot/include/configs/bct-brettl2.h b/qemu/roms/u-boot/include/configs/bct-brettl2.h
new file mode 100644
index 000000000..c1eda9638
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/bct-brettl2.h
@@ -0,0 +1,152 @@
+/*
+ * U-boot - Configuration file for BF536 brettl2 board
+ */
+
+#ifndef __CONFIG_BCT_BRETTL2_H__
+#define __CONFIG_BCT_BRETTL2_H__
+
+#include <asm/config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU             bf536-0.3
+#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
+
+
+/*
+ * Clock Settings
+ *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz					*/
+#define CONFIG_CLKIN_HZ			16384000
+/* CLKIN_HALF controls the DF bit in PLL_CTL	  0 = CLKIN		*/
+/*						  1 = CLKIN / 2		*/
+#define CONFIG_CLKIN_HALF		0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
+/*						  1 = bypass PLL	*/
+#define CONFIG_PLL_BYPASS		0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
+/* Values can range from 0-63 (where 0 means 64)			*/
+#define CONFIG_VCO_MULT			24
+/* CCLK_DIV controls the core clock divider				*/
+/* Values can be 1, 2, 4, or 8 ONLY					*/
+#define CONFIG_CCLK_DIV			1
+/* SCLK_DIV controls the system clock divider				*/
+/* Values can range from 1-15						*/
+#define CONFIG_SCLK_DIV			3
+#define CONFIG_VR_CTL_VAL	(VLEV_110 | GAIN_20 | FREQ_1000)
+
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_ADD_WDTH	9
+#define CONFIG_MEM_SIZE		32
+
+
+/*
+ * SDRAM Settings
+ */
+#define CONFIG_EBIU_SDRRC_VAL	0x07f6
+#define CONFIG_EBIU_SDGCTL_VAL	0x9111cd
+
+#define CONFIG_EBIU_AMGCTL_VAL	(AMBEN_ALL)
+#define CONFIG_EBIU_AMBCTL0_VAL	(B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
+#define CONFIG_EBIU_AMBCTL1_VAL	(B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
+
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)
+
+
+/*
+ * Network Settings
+ */
+#ifndef __ADSPBF534__
+#define ADI_CMDS_NETWORK	1
+#define CONFIG_BFIN_MAC		1
+#define CONFIG_NETCONSOLE	1
+#define CONFIG_HOSTNAME		brettl2
+#define CONFIG_IPADDR		192.168.233.224
+#define CONFIG_GATEWAYIP	192.168.233.1
+#define CONFIG_SERVERIP		192.168.233.53
+#define CONFIG_ROOTPATH		"/romfs/brettl2"
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR	02:80:ad:20:31:e8 */
+#define CONFIG_LIB_RAND
+#endif
+
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_FLASH_BASE			0x20000000
+#define CONFIG_SYS_MAX_FLASH_BANKS		1
+#define CONFIG_SYS_MAX_FLASH_SECT		135
+
+
+/*
+ * Env Storage Settings
+ */
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_OFFSET	0x4000
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x10000
+
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
+#define ENV_IS_EMBEDDED
+#else
+#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
+#endif
+
+#ifdef ENV_IS_EMBEDDED
+/* WARNING - the following is hand-optimized to fit within
+ * the sector before the environment sector. If it throws
+ * an error during compilation remove an object here to get
+ * it linked after the configuration sector.
+ */
+# define LDS_BOARD_TEXT \
+	arch/blackfin/lib/built-in.o (.text*); \
+	arch/blackfin/cpu/built-in.o (.text*); \
+	. = DEFINED(env_offset) ? env_offset : .; \
+	common/env_embedded.o (.text*);
+#endif
+
+
+/*
+ * I2C Settings
+ */
+#define CONFIG_BFIN_TWI_I2C	1
+#define CONFIG_HARD_I2C		1
+
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_BOOTDELAY	1
+#define CONFIG_LOADADDR		0x800000
+#define CONFIG_MISC_INIT_R
+#define CONFIG_UART_CONSOLE	0
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+/* disable unnecessary features */
+#undef CONFIG_BOOTM_RTEMS
+#undef CONFIG_BZIP2
+#undef CONFIG_KALLSYMS
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/beaver.h b/qemu/roms/u-boot/include/configs/beaver.h
new file mode 100644
index 000000000..df9a98bca
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/beaver.h
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+
+#include "tegra30-common.h"
+
+/* Enable fdt support for Beaver. Flash the image in u-boot-dtb.bin */
+#define CONFIG_DEFAULT_DEVICE_TREE	tegra30-beaver
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
+/* High-level configuration options */
+#define V_PROMPT		"Tegra30 (Beaver) # "
+#define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Beaver"
+
+/* Board-specific serial config */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_TEGRA_ENABLE_UARTA
+#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
+
+#define MACH_TYPE_BEAVER		4597	/* not yet in mach-types.h */
+#define CONFIG_MACH_TYPE		MACH_TYPE_BEAVER
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* I2C */
+#define CONFIG_SYS_I2C_TEGRA
+#define CONFIG_SYS_I2C_INIT_BOARD
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_TEGRA_MMC
+#define CONFIG_CMD_MMC
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART		2
+
+/* SPI */
+#define CONFIG_TEGRA20_SLINK
+#define CONFIG_TEGRA_SLINK_CTRLS       6
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SF_DEFAULT_MODE         SPI_MODE_0
+#define CONFIG_SF_DEFAULT_SPEED        24000000
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH_SIZE          (4 << 20)
+
+/* USB Host support */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_TEGRA
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB
+
+/* USB networking support */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+
+/* General networking support */
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/bf506f-ezkit.h b/qemu/roms/u-boot/include/configs/bf506f-ezkit.h
new file mode 100644
index 000000000..eed2d5bce
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/bf506f-ezkit.h
@@ -0,0 +1,110 @@
+/*
+ * U-boot - Configuration file for BF506F EZ-Kit board
+ */
+
+#ifndef __CONFIG_BF506F_EZKIT_H__
+#define __CONFIG_BF506F_EZKIT_H__
+
+#include <asm/config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU             bf506-0.0
+#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
+
+
+/*
+ * Clock Settings
+ *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz					*/
+#define CONFIG_CLKIN_HZ			25000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
+/*                                                1 = CLKIN / 2		*/
+#define CONFIG_CLKIN_HALF		0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
+/*                                                1 = bypass PLL	*/
+#define CONFIG_PLL_BYPASS		0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
+/* Values can range from 0-63 (where 0 means 64)			*/
+#define CONFIG_VCO_MULT			16
+/* CCLK_DIV controls the core clock divider				*/
+/* Values can be 1, 2, 4, or 8 ONLY					*/
+#define CONFIG_CCLK_DIV			1
+/* SCLK_DIV controls the system clock divider				*/
+/* Values can range from 1-15						*/
+#define CONFIG_SCLK_DIV			5
+
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_SIZE		0
+
+#define CONFIG_EBIU_AMGCTL_VAL	(AMCKEN | AMBEN_ALL)
+#define CONFIG_EBIU_AMBCTL0_VAL	0xffc2ffc2
+#define CONFIG_EBIU_AMBCTL1_VAL	0xffc2ffc2
+
+#define CONFIG_SYS_MONITOR_BASE (L1_DATA_A_SRAM_END)
+#define CONFIG_SYS_MONITOR_LEN	(4 * 1024)
+#define CONFIG_SYS_MALLOC_LEN	(4 * 1024)
+
+
+/*
+ * Flash Settings
+ */
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_BASE		0x20000000
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	71
+#define CONFIG_CMD_FLASH
+#define CONFIG_MONITOR_IS_IN_RAM
+/*
+#define CONFIG_SYS_NO_FLASH
+*/
+
+/*
+ * SPI Settings
+ */
+#define CONFIG_BFIN_SPI
+#define CONFIG_ENV_SPI_MAX_HZ	30000000
+#define CONFIG_SF_DEFAULT_SPEED	30000000
+/*
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+*/
+
+/*
+ * Env Storage Settings
+ */
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE 0x400
+#undef CONFIG_CMD_EXPORTENV
+#undef CONFIG_CMD_IMPORTENV
+
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_ICACHE_OFF
+#define CONFIG_DCACHE_OFF
+#define CONFIG_UART_CONSOLE	0
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_BFIN_SERIAL
+
+#define CONFIG_CMD_MEMORY
+#undef CONFIG_GZIP
+#undef CONFIG_ZLIB
+#undef CONFIG_CMD_BOOTM
+#undef CONFIG_BOOTM_RTEMS
+#undef CONFIG_BOOTM_LINUX
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/bf518f-ezbrd.h b/qemu/roms/u-boot/include/configs/bf518f-ezbrd.h
new file mode 100644
index 000000000..9e374c402
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/bf518f-ezbrd.h
@@ -0,0 +1,165 @@
+/*
+ * U-boot - Configuration file for BF518F EZBrd board
+ */
+
+#ifndef __CONFIG_BF518F_EZBRD_H__
+#define __CONFIG_BF518F_EZBRD_H__
+
+#include <asm/config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU             bf518-0.0
+#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
+
+
+/*
+ * Clock Settings
+ *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz					*/
+#define CONFIG_CLKIN_HZ			25000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
+/*                                                1 = CLKIN / 2		*/
+#define CONFIG_CLKIN_HALF		0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
+/*                                                1 = bypass PLL	*/
+#define CONFIG_PLL_BYPASS		0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
+/* Values can range from 0-63 (where 0 means 64)			*/
+#define CONFIG_VCO_MULT			16
+/* CCLK_DIV controls the core clock divider				*/
+/* Values can be 1, 2, 4, or 8 ONLY					*/
+#define CONFIG_CCLK_DIV			1
+/* SCLK_DIV controls the system clock divider				*/
+/* Values can range from 1-15						*/
+#define CONFIG_SCLK_DIV			5
+
+
+/*
+ * Memory Settings
+ */
+/* This board has a 64meg MT48H32M16 */
+#define CONFIG_MEM_ADD_WDTH	10
+#define CONFIG_MEM_SIZE		64
+
+#define CONFIG_EBIU_SDRRC_VAL	0x0096
+#define CONFIG_EBIU_SDGCTL_VAL	(SCTLE | CL_3 | PASR_ALL | TRAS_6 | TRP_3 | TRCD_3 | TWR_2 | PSS)
+
+#define CONFIG_EBIU_AMGCTL_VAL	(AMCKEN | AMBEN_ALL)
+#define CONFIG_EBIU_AMBCTL0_VAL	(B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL)
+#define CONFIG_EBIU_AMBCTL1_VAL	(B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL)
+
+#define CONFIG_SYS_MONITOR_LEN	(512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN	(384 * 1024)
+
+
+/*
+ * Network Settings
+ */
+#if !defined(__ADSPBF512__) && !defined(__ADSPBF514__)
+#define ADI_CMDS_NETWORK	1
+#define CONFIG_BFIN_MAC
+#define CONFIG_BFIN_MAC_PINS \
+	{ \
+	P_MII0_ETxD0, \
+	P_MII0_ETxD1, \
+	P_MII0_ETxD2, \
+	P_MII0_ETxD3, \
+	P_MII0_ETxEN, \
+	P_MII0_TxCLK, \
+	P_MII0_PHYINT, \
+	P_MII0_COL, \
+	P_MII0_ERxD0, \
+	P_MII0_ERxD1, \
+	P_MII0_ERxD2, \
+	P_MII0_ERxD3, \
+	P_MII0_ERxDV, \
+	P_MII0_ERxCLK, \
+	P_MII0_CRS, \
+	P_MII0_MDC, \
+	P_MII0_MDIO, \
+	0 }
+#define CONFIG_NETCONSOLE	1
+#endif
+#define CONFIG_HOSTNAME		bf518f-ezbrd
+#define CONFIG_PHY_ADDR		3
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR	02:80:ad:20:31:e8 */
+#define CONFIG_LIB_RAND
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_BASE		0x20000000
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	71
+
+
+/*
+ * SPI Settings
+ */
+#define CONFIG_BFIN_SPI
+#define CONFIG_ENV_SPI_MAX_HZ	30000000
+#define CONFIG_SF_DEFAULT_SPEED	30000000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_SPI_FLASH_STMICRO
+
+
+/*
+ * Env Storage Settings
+ */
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET	0x10000
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OFFSET	0x4000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x2000
+#endif
+#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
+
+
+/*
+ * I2C Settings
+ */
+#define CONFIG_BFIN_TWI_I2C	1
+#define CONFIG_HARD_I2C		1
+
+
+/*
+ * SDH Settings
+ */
+#if !defined(__ADSPBF512__)
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_BFIN_SDH
+#endif
+
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MISC_INIT_R
+#define CONFIG_RTC_BFIN
+#define CONFIG_UART_CONSOLE	0
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/bf525-ucr2.h b/qemu/roms/u-boot/include/configs/bf525-ucr2.h
new file mode 100644
index 000000000..008f4b5ec
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/bf525-ucr2.h
@@ -0,0 +1,103 @@
+/*
+ * U-boot - Configuration file for bf525-ucr2 board
+ * The board includes ADSP-BF525 rev. 0.2,
+ * 32-bit SDRAM (SAMSUNG K4S561632H-UC75),
+ * USB 2.0 High Speed OTG USB WIFI,
+ * SPI flash (cFeon EN25Q128 16 MB),
+ * Support PPI and ITU-R656,
+ * See http://www.ucrobotics.com/?q=cn/ucr2
+ */
+
+#ifndef __CONFIG_BF525_UCR2_H__
+#define __CONFIG_BF525_UCR2_H__
+
+#include <asm/config-pre.h>
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU             bf525-0.2
+#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_SPI_MASTER
+
+/*
+ * Clock Settings
+ *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz					*/
+#define CONFIG_CLKIN_HZ			24000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
+/*                                                1 = CLKIN / 2		*/
+#define CONFIG_CLKIN_HALF		0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
+/*                                                1 = bypass PLL	*/
+#define CONFIG_PLL_BYPASS		0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
+/* Values can range from 0-63 (where 0 means 64)			*/
+#define CONFIG_VCO_MULT			20
+/* CCLK_DIV controls the core clock divider				*/
+/* Values can be 1, 2, 4, or 8 ONLY					*/
+#define CONFIG_CCLK_DIV			1
+/* SCLK_DIV controls the system clock divider				*/
+/* Values can range from 1-15						*/
+#define CONFIG_SCLK_DIV			4
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_ADD_WDTH	9
+#define CONFIG_MEM_SIZE		32
+
+/*
+ * SDRAM reference page
+ * http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
+ */
+#define CONFIG_EBIU_SDRRC_VAL   0x3f8
+#define CONFIG_EBIU_SDGCTL_VAL  0x9111cd
+
+#define CONFIG_EBIU_AMGCTL_VAL  (AMBEN_ALL)
+#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
+#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
+
+#define CONFIG_SYS_MONITOR_LEN	(320 * 1024)
+#define CONFIG_SYS_MALLOC_LEN	(320 * 1024)
+
+/* We don't have a parallel flash chip */
+#define CONFIG_SYS_NO_FLASH
+
+/* support for serial flash */
+#define CONFIG_BFIN_SPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_HZ	30000000
+#define CONFIG_SPI_FLASH_EON
+
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_MAX_HZ	30000000
+#define CONFIG_ENV_OFFSET	0x10000
+#define CONFIG_ENV_SIZE		0x10000
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#define CONFIG_ENV_OVERWRITE	1
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_UART_CONSOLE	0
+
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_BFIN_SERIAL
+#define CONFIG_BOOTARGS		"root=/dev/mtdblock0 rw"
+#define CONFIG_BOOTCOMMAND	"run sfboot"
+#define CONFIG_BOOTDELAY	5
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"sfboot=sf probe 1;" \
+		"sf read 0x1000000 0x20000 0x300000;" \
+		"bootm 0x1000000\0"
+
+/* this sets up the default list of enabled commands */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_NET	/* bootp, tftpboot, rarpboot */
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_IMLS
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/bf526-ezbrd.h b/qemu/roms/u-boot/include/configs/bf526-ezbrd.h
new file mode 100644
index 000000000..972eca9c1
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/bf526-ezbrd.h
@@ -0,0 +1,182 @@
+/*
+ * U-boot - Configuration file for BF526 EZBrd board
+ */
+
+#ifndef __CONFIG_BF526_EZBRD_H__
+#define __CONFIG_BF526_EZBRD_H__
+
+#include <asm/config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU             bf526-0.0
+#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
+
+
+/*
+ * Clock Settings
+ *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz					*/
+#define CONFIG_CLKIN_HZ			25000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
+/*                                                1 = CLKIN / 2		*/
+#define CONFIG_CLKIN_HALF		0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
+/*                                                1 = bypass PLL	*/
+#define CONFIG_PLL_BYPASS		0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
+/* Values can range from 0-63 (where 0 means 64)			*/
+#define CONFIG_VCO_MULT			16
+/* CCLK_DIV controls the core clock divider				*/
+/* Values can be 1, 2, 4, or 8 ONLY					*/
+#define CONFIG_CCLK_DIV			1
+/* SCLK_DIV controls the system clock divider				*/
+/* Values can range from 1-15						*/
+#define CONFIG_SCLK_DIV			5
+
+
+/*
+ * Memory Settings
+ */
+/* This board has a 64meg MT48H32M16 */
+#define CONFIG_MEM_ADD_WDTH	10
+#define CONFIG_MEM_SIZE		64
+
+#define CONFIG_EBIU_SDRRC_VAL	0x0267
+#define CONFIG_EBIU_SDGCTL_VAL	(SCTLE | CL_2 | PASR_ALL | TRAS_6 | TRP_4 | TRCD_2 | TWR_2 | PSS)
+
+#define CONFIG_EBIU_AMGCTL_VAL	(AMCKEN | AMBEN_ALL)
+#define CONFIG_EBIU_AMBCTL0_VAL	(B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL)
+#define CONFIG_EBIU_AMBCTL1_VAL	(B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL)
+
+#define CONFIG_SYS_MONITOR_LEN	(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN	(512 * 1024)
+
+
+/*
+ * NAND Settings
+ * (can't be used same time as ethernet)
+ */
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
+# define CONFIG_BFIN_NFC
+# define CONFIG_BFIN_NFC_BOOTROM_ECC
+#endif
+#ifdef CONFIG_BFIN_NFC
+#define CONFIG_BFIN_NFC_CTL_VAL	0x0033
+#define CONFIG_DRIVER_NAND_BFIN
+#define CONFIG_SYS_NAND_BASE		0 /* not actually used */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_CMD_NAND
+#endif
+
+
+/*
+ * Network Settings
+ */
+#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__) && \
+    !defined(__ADSPBF524__) && !defined(__ADSPBF525__) && !defined(CONFIG_BFIN_NFC)
+#define ADI_CMDS_NETWORK	1
+#define CONFIG_BFIN_MAC
+#define CONFIG_RMII
+#define CONFIG_NETCONSOLE	1
+#endif
+#define CONFIG_HOSTNAME		bf526-ezbrd
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR	02:80:ad:20:31:e8 */
+#define CONFIG_LIB_RAND
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_BASE		0x20000000
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	71
+
+
+/*
+ * SPI Settings
+ */
+#define CONFIG_BFIN_SPI
+#define CONFIG_ENV_SPI_MAX_HZ	30000000
+#define CONFIG_SF_DEFAULT_SPEED	30000000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SST
+
+
+/*
+ * Env Storage Settings
+ */
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET	0x4000
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x2000
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OFFSET	0x4000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x2000
+#endif
+#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
+
+
+/*
+ * I2C Settings
+ */
+#define CONFIG_BFIN_TWI_I2C	1
+#define CONFIG_HARD_I2C		1
+
+
+/*
+ * USB Settings
+ */
+#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__)
+#define CONFIG_USB
+#define CONFIG_MUSB_HCD
+#define CONFIG_USB_BLACKFIN
+#define CONFIG_USB_STORAGE
+#define CONFIG_MUSB_TIMEOUT 100000
+#endif
+
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_RTC_BFIN
+#define CONFIG_UART_CONSOLE	1
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
+
+/* define to enable run status via led */
+/* #define CONFIG_STATUS_LED */
+#ifdef CONFIG_STATUS_LED
+#define CONFIG_GPIO_LED
+#define CONFIG_BOARD_SPECIFIC_LED
+/* use LED0 to indicate booting/alive */
+#define STATUS_LED_BOOT 0
+#define STATUS_LED_BIT GPIO_PF8
+#define STATUS_LED_STATE STATUS_LED_ON
+#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 4)
+/* use LED1 to indicate crash */
+#define STATUS_LED_CRASH 1
+#define STATUS_LED_BIT1 GPIO_PG11
+#define STATUS_LED_STATE1 STATUS_LED_ON
+#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
+/* #define STATUS_LED_BIT2 GPIO_PG12 */
+#endif
+
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/bf527-ad7160-eval.h b/qemu/roms/u-boot/include/configs/bf527-ad7160-eval.h
new file mode 100644
index 000000000..c0dfe2685
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/bf527-ad7160-eval.h
@@ -0,0 +1,146 @@
+/*
+ * U-boot - Configuration file for BF527 AD7160-EVAL board
+ */
+
+#ifndef __CONFIG_BF527_AD7160_EVAL_H__
+#define __CONFIG_BF527_AD7160_EVAL_H__
+
+#include <asm/config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU             bf527-0.2
+#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_SPI_MASTER
+
+
+/*
+ * Clock Settings
+ *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz					*/
+#define CONFIG_CLKIN_HZ			24000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
+/*                                                1 = CLKIN / 2		*/
+#define CONFIG_CLKIN_HALF		0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
+/*                                                1 = bypass PLL	*/
+#define CONFIG_PLL_BYPASS		0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
+/* Values can range from 0-63 (where 0 means 64)			*/
+#define CONFIG_VCO_MULT			25
+/* CCLK_DIV controls the core clock divider				*/
+/* Values can be 1, 2, 4, or 8 ONLY					*/
+#define CONFIG_CCLK_DIV			1
+/* SCLK_DIV controls the system clock divider				*/
+/* Values can range from 1-15						*/
+#define CONFIG_SCLK_DIV			5
+
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_ADD_WDTH	10
+#define CONFIG_MEM_SIZE		64
+
+#define CONFIG_EBIU_SDRRC_VAL	0x03F6
+#define CONFIG_EBIU_SDGCTL_VAL	(SCTLE | CL_3 | PASR_ALL | TRAS_6 | TRP_3 | TRCD_3 | TWR_2 | PSS)
+
+#define CONFIG_EBIU_AMGCTL_VAL	(AMCKEN | AMBEN_ALL)
+#define CONFIG_EBIU_AMBCTL0_VAL	(B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL)
+#define CONFIG_EBIU_AMBCTL1_VAL	(B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL)
+
+#define CONFIG_SYS_MONITOR_LEN	(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN	(640 * 1024)
+
+
+/*
+ * NAND Settings
+ * (can't be used same time as ethernet)
+ */
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
+# define CONFIG_BFIN_NFC
+# define CONFIG_BFIN_NFC_BOOTROM_ECC
+#endif
+#ifdef CONFIG_BFIN_NFC
+#define CONFIG_BFIN_NFC_CTL_VAL	0x0033
+#define CONFIG_DRIVER_NAND_BFIN
+#define CONFIG_SYS_NAND_BASE		0 /* not actually used */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#endif
+
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_BASE		0x20000000
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	259
+
+
+/*
+ * SPI Settings
+ */
+#define CONFIG_BFIN_SPI
+#define CONFIG_ENV_SPI_MAX_HZ	30000000
+#define CONFIG_SF_DEFAULT_SPEED	30000000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+
+
+/*
+ * Env Storage Settings
+ */
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET	0x10000
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
+#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET	0x40000
+#define CONFIG_ENV_SIZE		0x20000
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OFFSET	0x4000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x2000
+#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
+#endif
+
+
+/*
+ * I2C Settings
+ */
+#define CONFIG_BFIN_TWI_I2C	1
+#define CONFIG_HARD_I2C		1
+
+
+/*
+ * SPI_MMC Settings
+ */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC_SPI
+
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_UART_CONSOLE	0
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/bf527-ezkit.h b/qemu/roms/u-boot/include/configs/bf527-ezkit.h
new file mode 100644
index 000000000..92c183e27
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/bf527-ezkit.h
@@ -0,0 +1,189 @@
+/*
+ * U-boot - Configuration file for BF537 STAMP board
+ */
+
+#ifndef __CONFIG_BF527_EZKIT_H__
+#define __CONFIG_BF527_EZKIT_H__
+
+#include <asm/config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU             bf527-0.0
+#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
+
+
+/*
+ * Clock Settings
+ *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz					*/
+#define CONFIG_CLKIN_HZ			25000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
+/*                                                1 = CLKIN / 2		*/
+#define CONFIG_CLKIN_HALF		0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
+/*                                                1 = bypass PLL	*/
+#define CONFIG_PLL_BYPASS		0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
+/* Values can range from 0-63 (where 0 means 64)			*/
+#define CONFIG_VCO_MULT			21
+/* CCLK_DIV controls the core clock divider				*/
+/* Values can be 1, 2, 4, or 8 ONLY					*/
+#define CONFIG_CCLK_DIV			1
+/* SCLK_DIV controls the system clock divider				*/
+/* Values can range from 1-15						*/
+#define CONFIG_SCLK_DIV			4
+
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_ADD_WDTH	10
+#define CONFIG_MEM_SIZE		64
+
+#define CONFIG_EBIU_SDRRC_VAL	0x03F6
+#define CONFIG_EBIU_SDGCTL_VAL	(SCTLE | CL_3 | PASR_ALL | TRAS_6 | TRP_3 | TRCD_3 | TWR_2 | PSS)
+
+#define CONFIG_EBIU_AMGCTL_VAL	(AMCKEN | AMBEN_ALL)
+#define CONFIG_EBIU_AMBCTL0_VAL	(B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL)
+#define CONFIG_EBIU_AMBCTL1_VAL	(B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL)
+
+#define CONFIG_SYS_MONITOR_LEN	(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN	(640 * 1024)
+
+
+/*
+ * NAND Settings
+ * (can't be used same time as ethernet)
+ */
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
+# define CONFIG_BFIN_NFC
+# define CONFIG_BFIN_NFC_BOOTROM_ECC
+#endif
+#ifdef CONFIG_BFIN_NFC
+#define CONFIG_BFIN_NFC_CTL_VAL	0x0033
+#define CONFIG_DRIVER_NAND_BFIN
+#define CONFIG_SYS_NAND_BASE		0 /* not actually used */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#endif
+
+
+/*
+ * Network Settings
+ */
+#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__) && \
+    !defined(__ADSPBF524__) && !defined(__ADSPBF525__) && !defined(CONFIG_BFIN_NFC)
+#define ADI_CMDS_NETWORK	1
+#define CONFIG_BFIN_MAC
+#define CONFIG_RMII
+#define CONFIG_NETCONSOLE	1
+#endif
+#define CONFIG_HOSTNAME		bf527-ezkit
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR	02:80:ad:20:31:e8 */
+#define CONFIG_LIB_RAND
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_BASE		0x20000000
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	259
+
+
+/*
+ * SPI Settings
+ */
+#define CONFIG_BFIN_SPI
+#define CONFIG_ENV_SPI_MAX_HZ	30000000
+#define CONFIG_SF_DEFAULT_SPEED	30000000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+
+
+/*
+ * Env Storage Settings
+ */
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET	0x10000
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
+#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET	0x40000
+#define CONFIG_ENV_SIZE		0x20000
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OFFSET	0x4000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x2000
+#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
+#endif
+
+
+/*
+ * I2C Settings
+ */
+#define CONFIG_BFIN_TWI_I2C	1
+#define CONFIG_HARD_I2C		1
+
+
+/*
+ * USB Settings
+ */
+#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__)
+#define CONFIG_USB
+#define CONFIG_MUSB_HCD
+#define CONFIG_USB_BLACKFIN
+#define CONFIG_USB_STORAGE
+#define CONFIG_MUSB_TIMEOUT 100000
+#endif
+
+/* Don't waste time transferring a logo over the UART */
+#if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART)
+/*# define CONFIG_VIDEO*/
+#endif
+
+/*
+ * Video Settings
+ */
+#ifdef CONFIG_VIDEO
+#ifdef CONFIG_BF527_EZKIT_REV_2_1
+# define CONFIG_LQ035Q1_SPI_BUS	0
+# define CONFIG_LQ035Q1_SPI_CS	7
+# define CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI
+#else
+# define CONFIG_LQ035Q1_USE_RGB888_8_BIT_PPI
+#endif
+
+#ifdef CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI
+# define EASYLOGO_HEADER <asm/bfin_logo_rgb565_230x230_lzma.h>
+#else
+# define EASYLOGO_HEADER <asm/bfin_logo_230x230_lzma.h>
+#endif
+#endif /* CONFIG_VIDEO */
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_RTC_BFIN
+#define CONFIG_UART_CONSOLE	1
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/bf527-sdp.h b/qemu/roms/u-boot/include/configs/bf527-sdp.h
new file mode 100644
index 000000000..458868af7
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/bf527-sdp.h
@@ -0,0 +1,122 @@
+/*
+ * U-boot - Configuration file for BF527 SDP board
+ */
+
+#ifndef __CONFIG_BF527_SDP_H__
+#define __CONFIG_BF527_SDP_H__
+
+#include <asm/config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU             bf527-0.2
+#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
+
+
+/*
+ * Clock Settings
+ *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz					*/
+#define CONFIG_CLKIN_HZ			24000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
+/*                                                1 = CLKIN / 2		*/
+#define CONFIG_CLKIN_HALF		0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
+/*                                                1 = bypass PLL	*/
+#define CONFIG_PLL_BYPASS		0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
+/* Values can range from 0-63 (where 0 means 64)			*/
+#define CONFIG_VCO_MULT			25
+/* CCLK_DIV controls the core clock divider				*/
+/* Values can be 1, 2, 4, or 8 ONLY					*/
+#define CONFIG_CCLK_DIV			1
+/* SCLK_DIV controls the system clock divider				*/
+/* Values can range from 1-15						*/
+#define CONFIG_SCLK_DIV			5
+
+#define CONFIG_PLL_LOCKCNT_VAL	0x0200
+#define CONFIG_PLL_CTL_VAL		0x2a00
+#define CONFIG_VR_CTL_VAL		0x7090
+
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_ADD_WDTH	9
+#define CONFIG_MEM_SIZE		32
+
+#define CONFIG_EBIU_SDRRC_VAL	0x00FE
+#define CONFIG_EBIU_SDGCTL_VAL	0x8011998d
+
+#define CONFIG_EBIU_AMGCTL_VAL	(AMCKEN | AMBEN_ALL)
+#define CONFIG_EBIU_AMBCTL0_VAL	(B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL)
+#define CONFIG_EBIU_AMBCTL1_VAL	(B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL)
+
+#define CONFIG_SYS_MONITOR_LEN	(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN	(640 * 1024)
+
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_BASE		0x20000000
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	259
+
+
+/*
+ * SPI Settings
+ */
+#define CONFIG_BFIN_SPI
+#define CONFIG_ENV_SPI_MAX_HZ	30000000
+#define CONFIG_SF_DEFAULT_SPEED	30000000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_ALL
+
+
+/*
+ * Env Storage Settings
+ */
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET	0x10000
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OFFSET	0x4000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x2000
+#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
+#endif
+
+
+/*
+ * I2C Settings
+ */
+#define CONFIG_BFIN_TWI_I2C	1
+#define CONFIG_HARD_I2C		1
+
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_UART_CONSOLE	0
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/bf533-ezkit.h b/qemu/roms/u-boot/include/configs/bf533-ezkit.h
new file mode 100644
index 000000000..b50352823
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/bf533-ezkit.h
@@ -0,0 +1,120 @@
+/*
+ * U-boot - Configuration file for BF533 EZKIT board
+ */
+
+#ifndef __CONFIG_BF533_EZKIT_H__
+#define __CONFIG_BF533_EZKIT_H__
+
+#include <asm/config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU             bf533-0.3
+#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
+
+
+/*
+ * Clock Settings
+ *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz					*/
+#define CONFIG_CLKIN_HZ			27000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
+/*                                                1 = CLKIN / 2		*/
+#define CONFIG_CLKIN_HALF		0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
+/*                                                1 = bypass PLL	*/
+#define CONFIG_PLL_BYPASS		0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
+/* Values can range from 0-63 (where 0 means 64)			*/
+#define CONFIG_VCO_MULT			22
+/* CCLK_DIV controls the core clock divider				*/
+/* Values can be 1, 2, 4, or 8 ONLY					*/
+#define CONFIG_CCLK_DIV			1
+/* SCLK_DIV controls the system clock divider				*/
+/* Values can range from 1-15						*/
+#define CONFIG_SCLK_DIV			5
+
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_SIZE		32
+/* Early EZKITs had 32megs, but later have 64megs */
+#if (CONFIG_MEM_SIZE == 64)
+# define CONFIG_MEM_ADD_WDTH	10
+#else
+# define CONFIG_MEM_ADD_WDTH	9
+#endif
+
+#define CONFIG_EBIU_SDRRC_VAL	0x398
+#define CONFIG_EBIU_SDGCTL_VAL	0x91118d
+
+#define CONFIG_EBIU_AMGCTL_VAL	0xFF
+#define CONFIG_EBIU_AMBCTL0_VAL	0x7BB07BB0
+#define CONFIG_EBIU_AMBCTL1_VAL	0xFFC27BB0
+
+#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN	(128 * 1024)
+
+
+/*
+ * Network Settings
+ */
+#define ADI_CMDS_NETWORK	1
+#define CONFIG_SMC91111	1
+#define CONFIG_SMC91111_BASE	0x20310300
+#define SMC91111_EEPROM_INIT() \
+	do { \
+		bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF1 | PF0); \
+		bfin_write_FIO_FLAG_C(PF1); \
+		bfin_write_FIO_FLAG_S(PF0); \
+		SSYNC(); \
+	} while (0)
+#define CONFIG_HOSTNAME		bf533-ezkit
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR	02:80:ad:20:31:e8 */
+
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_SYS_FLASH_BASE		0x20000000
+#define CONFIG_SYS_MAX_FLASH_BANKS	3
+#define CONFIG_SYS_MAX_FLASH_SECT	40
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR		0x20030000
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#define FLASH_TOT_SECT		40
+
+
+/*
+ * I2C Settings
+ */
+#define CONFIG_SYS_I2C_SOFT
+#ifdef CONFIG_SYS_I2C_SOFT
+#define CONFIG_SYS_I2C
+#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF0
+#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF1
+#define CONFIG_SYS_I2C_SOFT_SPEED	50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0
+#define I2C_DELAY              udelay(5)       /* 1/4 I2C clock duration */
+#endif
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_RTC_BFIN
+#define CONFIG_UART_CONSOLE	0
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/bf533-stamp.h b/qemu/roms/u-boot/include/configs/bf533-stamp.h
new file mode 100644
index 000000000..d82c5b203
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/bf533-stamp.h
@@ -0,0 +1,223 @@
+/*
+ * U-boot - Configuration file for BF533 STAMP board
+ */
+
+#ifndef __CONFIG_BF533_STAMP_H__
+#define __CONFIG_BF533_STAMP_H__
+
+#include <asm/config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU             bf533-0.3
+#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
+
+/*
+ * Clock Settings
+ *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz					*/
+#define CONFIG_CLKIN_HZ			11059200
+/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
+/*                                                1 = CLKIN / 2		*/
+#define CONFIG_CLKIN_HALF		0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
+/*                                                1 = bypass PLL	*/
+#define CONFIG_PLL_BYPASS		0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
+/* Values can range from 0-63 (where 0 means 64)			*/
+#define CONFIG_VCO_MULT			45
+/* CCLK_DIV controls the core clock divider				*/
+/* Values can be 1, 2, 4, or 8 ONLY					*/
+#define CONFIG_CCLK_DIV			1
+/* SCLK_DIV controls the system clock divider				*/
+/* Values can range from 1-15						*/
+#define CONFIG_SCLK_DIV			6 /* note: 1.2 boards can go faster */
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_ADD_WDTH	11
+#define CONFIG_MEM_SIZE		128
+
+#define CONFIG_EBIU_SDRRC_VAL	0x268
+#define CONFIG_EBIU_SDGCTL_VAL	0x911109
+
+#define CONFIG_EBIU_AMGCTL_VAL	0xFF
+#define CONFIG_EBIU_AMBCTL0_VAL	0xBBC3BBC3
+#define CONFIG_EBIU_AMBCTL1_VAL	0x99B39983
+
+#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN	(384 * 1024)
+
+
+/*
+ * Network Settings
+ */
+#define ADI_CMDS_NETWORK	1
+#define CONFIG_SMC91111	1
+#define CONFIG_SMC91111_BASE	0x20300300
+#define SMC91111_EEPROM_INIT() \
+	do { \
+		bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF1 | PF0); \
+		bfin_write_FIO_FLAG_C(PF1); \
+		bfin_write_FIO_FLAG_S(PF0); \
+		SSYNC(); \
+	} while (0)
+#define CONFIG_HOSTNAME		bf533-stamp
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR	02:80:ad:20:31:b8 */
+
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED	50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define CONFIG_SOFT_I2C_GPIO_SCL	GPIO_PF3
+#define CONFIG_SOFT_I2C_GPIO_SDA	GPIO_PF2
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_BASE		0x20000000
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI_AMD_RESET
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	67
+
+/*
+ * SPI Settings
+ */
+#define CONFIG_BFIN_SPI
+#define CONFIG_ENV_SPI_MAX_HZ	30000000
+#define CONFIG_SF_DEFAULT_SPEED	30000000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_ALL
+
+
+/*
+ * Env Storage Settings
+ */
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET	0x10000
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OFFSET	0x4000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x2000
+#endif
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
+#define ENV_IS_EMBEDDED
+#else
+#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
+#endif
+#ifdef ENV_IS_EMBEDDED
+/* WARNING - the following is hand-optimized to fit within
+ * the sector before the environment sector. If it throws
+ * an error during compilation remove an object here to get
+ * it linked after the configuration sector.
+ */
+# define LDS_BOARD_TEXT \
+	arch/blackfin/lib/built-in.o (.text*); \
+	arch/blackfin/cpu/built-in.o (.text*); \
+	. = DEFINED(env_offset) ? env_offset : .; \
+	common/env_embedded.o (.text*);
+#endif
+
+
+/*
+ * I2C Settings
+ */
+#define CONFIG_SYS_I2C_SOFT
+#ifdef CONFIG_SYS_I2C_SOFT
+#define CONFIG_SYS_I2C
+#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF3
+#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF2
+#define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
+#define CONFIG_SYS_I2C_SOFT_SPEED	50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0
+#endif
+
+/*
+ * Compact Flash / IDE / ATA Settings
+ */
+
+/* Enabled below option for CF support */
+/* #define CONFIG_STAMP_CF */
+#if defined(CONFIG_STAMP_CF)
+#define CONFIG_MISC_INIT_R
+#define CONFIG_DOS_PARTITION	1
+#undef  CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
+#undef  CONFIG_IDE_LED			/* no led for ide supported */
+#undef  CONFIG_IDE_RESET		/* no reset for ide supported */
+
+#define CONFIG_SYS_IDE_MAXBUS		1
+#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS * 1)
+
+#define CONFIG_SYS_ATA_BASE_ADDR	0x20200000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0020	/* data I/O */
+#define CONFIG_SYS_ATA_REG_OFFSET	0x0020	/* normal register accesses */
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0007	/* alternate registers */
+
+#define CONFIG_SYS_ATA_STRIDE		2
+
+#undef CONFIG_EBIU_AMBCTL1_VAL
+#define CONFIG_EBIU_AMBCTL1_VAL	0x99B3ffc2
+#endif
+
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_RTC_BFIN
+#define CONFIG_UART_CONSOLE	0
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
+
+/* FLASH/ETHERNET uses the same async bank */
+#define SHARED_RESOURCES 	1
+
+/* define to enable boot progress via leds */
+/* #define CONFIG_SHOW_BOOT_PROGRESS */
+
+/* define to enable run status via led */
+/* #define CONFIG_STATUS_LED */
+#ifdef CONFIG_STATUS_LED
+#define CONFIG_GPIO_LED
+#define CONFIG_BOARD_SPECIFIC_LED
+/* use LED0 to indicate booting/alive */
+#define STATUS_LED_BOOT 0
+#define STATUS_LED_BIT GPIO_PF2
+#define STATUS_LED_STATE STATUS_LED_ON
+#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 4)
+/* use LED1 to indicate crash */
+#define STATUS_LED_CRASH 1
+#define STATUS_LED_BIT1 GPIO_PF3
+#define STATUS_LED_STATE1 STATUS_LED_ON
+#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
+/* #define STATUS_LED_BIT2 GPIO_PF4 */
+#endif
+
+/* define to enable splash screen support */
+/* #define CONFIG_VIDEO */
+
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/bf537-minotaur.h b/qemu/roms/u-boot/include/configs/bf537-minotaur.h
new file mode 100644
index 000000000..3bc364ccf
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/bf537-minotaur.h
@@ -0,0 +1,202 @@
+/*
+ * U-boot - Configuration file for CSP Minotaur board
+ *
+ * Thu Oct 25 15:30:44 CEST 2007 <hackfin@section5.ch>
+ *    Minotaur config, brushed up for official uClinux dist.
+ *    Parallel flash support disabled, SPI flash boot command
+ *    added ('run flashboot').
+ *
+ * Flash image map:
+ *
+ * 0x00000000      u-boot bootstrap
+ * 0x00010000      environment
+ * 0x00020000      u-boot code
+ * 0x00030000      uImage.initramfs
+ *
+ */
+
+#ifndef __CONFIG_BF537_MINOTAUR_H__
+#define __CONFIG_BF537_MINOTAUR_H__
+
+#include <asm/config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU             bf537-0.2
+#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_SPI_MASTER
+
+
+/*
+ * Clock Settings
+ *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz					*/
+#define CONFIG_CLKIN_HZ			25000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
+/*                                                1 = CLKIN / 2		*/
+#define CONFIG_CLKIN_HALF		0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
+/*                                                1 = bypass PLL	*/
+#define CONFIG_PLL_BYPASS		0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
+/* Values can range from 0-63 (where 0 means 64)			*/
+#define CONFIG_VCO_MULT			20
+/* CCLK_DIV controls the core clock divider				*/
+/* Values can be 1, 2, 4, or 8 ONLY					*/
+#define CONFIG_CCLK_DIV			1
+/* SCLK_DIV controls the system clock divider				*/
+/* Values can range from 1-15						*/
+#define CONFIG_SCLK_DIV			5
+
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_SIZE			32
+#define CONFIG_MEM_ADD_WDTH		9
+
+#define CONFIG_EBIU_SDRRC_VAL		0x306
+#define CONFIG_EBIU_SDGCTL_VAL		0x91114d
+
+#define CONFIG_EBIU_AMGCTL_VAL		0xFF
+#define CONFIG_EBIU_AMBCTL0_VAL		0x7BB07BB0
+#define CONFIG_EBIU_AMBCTL1_VAL		0xFFC27BB0
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)
+
+
+/*
+ * Network Settings
+ */
+#ifndef __ADSPBF534__
+#define CONFIG_BFIN_MAC
+#define CONFIG_NETCONSOLE	1
+#endif
+#ifdef CONFIG_BFIN_MAC
+#define CONFIG_IPADDR		192.168.0.15
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_GATEWAYIP	192.168.0.1
+#define CONFIG_SERVERIP		192.168.0.2
+#define CONFIG_HOSTNAME		bf537-minotaur
+#endif
+
+#define CONFIG_SYS_AUTOLOAD	"no"
+#define CONFIG_ROOTPATH		"/romfs"
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR	02:80:ad:20:31:42 */
+
+#define CONFIG_LIB_RAND
+
+/*
+ * Flash Settings
+ */
+/* We don't have a parallel flash chip there */
+#define CONFIG_SYS_NO_FLASH
+
+
+/*
+ * SPI Settings
+ */
+#define CONFIG_BFIN_SPI
+#define CONFIG_ENV_SPI_MAX_HZ	30000000
+#define CONFIG_SF_DEFAULT_SPEED	30000000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+
+
+/*
+ * Env Storage Settings
+ */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET	0x10000
+#define CONFIG_ENV_SIZE		0x10000
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
+
+
+/*
+ * I2C settings
+ */
+#define CONFIG_BFIN_TWI_I2C	1
+#define CONFIG_HARD_I2C		1
+#define CONFIG_SYS_I2C_SPEED		50000
+#define CONFIG_SYS_I2C_SLAVE		0
+
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_SYS_LONGHELP		1
+#define CONFIG_CMDLINE_EDITING	1
+#define CONFIG_ENV_OVERWRITE	1
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_BAUDRATE		57600
+#define CONFIG_UART_CONSOLE	0
+#define CONFIG_BFIN_SERIAL
+
+#define CONFIG_PANIC_HANG	1
+#define CONFIG_RTC_BFIN		1
+#define CONFIG_BOOT_RETRY_TIME	-1
+#define CONFIG_LOADS_ECHO		1
+
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
+# define CONFIG_BOOTDELAY	-1
+#else
+# define CONFIG_BOOTDELAY	5
+#endif
+
+#include <config_cmd_default.h>
+
+#ifdef CONFIG_BFIN_MAC
+# define CONFIG_CMD_DHCP
+# define CONFIG_CMD_PING
+#else
+# undef CONFIG_CMD_NET
+# undef CONFIG_CMD_NFS
+#endif
+
+#define CONFIG_CMD_BOOTLDR
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ELF
+#undef CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_SF
+
+#define CONFIG_BOOTCOMMAND	"run ramboot"
+#define CONFIG_BOOTARGS	"root=/dev/mtdblock0 rw"
+#define CONFIG_SYS_PROMPT	"minotaur> "
+
+#define BOOT_ENV_SETTINGS \
+	"update=tftpboot $(loadaddr) u-boot.ldr;" \
+		"sf probe " __stringify(BFIN_BOOT_SPI_SSEL) ";" \
+		"sf erase 0 0x30000;" \
+		"sf write $(loadaddr) 0 $(filesize)" \
+	"flashboot=sf read 0x1000000 0x30000 0x320000;" \
+		"bootm 0x1000000\0"
+#ifdef CONFIG_BFIN_MAC
+# define NETWORK_ENV_SETTINGS \
+	"nfsargs=setenv bootargs root=/dev/nfs rw " \
+		"nfsroot=$(serverip):$(rootpath)\0" \
+	"addip=setenv bootargs $(bootargs) " \
+		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
+		":$(hostname):eth0:off\0" \
+	"ramboot=tftpboot $(loadaddr) linux;" \
+		"run ramargs;run addip;bootelf\0" \
+	"nfsboot=tftpboot $(loadaddr) linux;" \
+		"run nfsargs;run addip;bootelf\0"
+#else
+# define NETWORK_ENV_SETTINGS
+#endif
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	NETWORK_ENV_SETTINGS \
+	"ramargs=setenv bootargs " CONFIG_BOOTARGS "\0" \
+	BOOT_ENV_SETTINGS
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/bf537-pnav.h b/qemu/roms/u-boot/include/configs/bf537-pnav.h
new file mode 100644
index 000000000..ba74a695f
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/bf537-pnav.h
@@ -0,0 +1,172 @@
+/*
+ * U-boot - Configuration file for BF537 PNAV board
+ */
+
+#ifndef __CONFIG_BF537_PNAV_H__
+#define __CONFIG_BF537_PNAV_H__
+
+#include <asm/config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU             bf537-0.2
+#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_SPI_MASTER
+
+
+/*
+ * Clock Settings
+ *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz					*/
+#define CONFIG_CLKIN_HZ			24576000
+/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
+/*                                                1 = CLKIN / 2		*/
+#define CONFIG_CLKIN_HALF		0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
+/*                                                1 = bypass PLL	*/
+#define CONFIG_PLL_BYPASS		0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
+/* Values can range from 0-63 (where 0 means 64)			*/
+#define CONFIG_VCO_MULT			20
+/* CCLK_DIV controls the core clock divider				*/
+/* Values can be 1, 2, 4, or 8 ONLY					*/
+#define CONFIG_CCLK_DIV			1
+/* SCLK_DIV controls the system clock divider				*/
+/* Values can range from 1-15						*/
+#define CONFIG_SCLK_DIV			4
+
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_ADD_WDTH	10
+#define CONFIG_MEM_SIZE		64
+
+#define CONFIG_EBIU_SDRRC_VAL	0x3b7
+#define CONFIG_EBIU_SDGCTL_VAL	0x9111cd
+
+#define CONFIG_EBIU_AMGCTL_VAL	0xFF
+#define CONFIG_EBIU_AMBCTL0_VAL	0x7BB033B0
+#define CONFIG_EBIU_AMBCTL1_VAL	0xFFC27BB0
+
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)
+
+
+/*
+ * Network Settings
+ */
+#ifndef __ADSPBF534__
+#define ADI_CMDS_NETWORK	1
+#define CONFIG_BFIN_MAC
+#define CONFIG_RMII
+#endif
+#define CONFIG_HOSTNAME		bf537-pnav
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR	02:80:ad:24:21:18 */
+#define CONFIG_LIB_RAND
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_BASE		0x20000000
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	71
+
+
+/*
+ * SPI Settings
+ */
+#define CONFIG_BFIN_SPI
+#define CONFIG_ENV_SPI_MAX_HZ	30000000
+#define CONFIG_SF_DEFAULT_SPEED	30000000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+
+
+/*
+ * Env Storage Settings
+ */
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
+#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET	0x4000
+#else
+#define ENV_IS_EMBEDDED
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_ADDR		0x20004000
+#define CONFIG_ENV_OFFSET	0x4000
+#endif
+#define CONFIG_ENV_SIZE		0x1000
+#define CONFIG_ENV_SECT_SIZE	0x2000
+#ifdef ENV_IS_EMBEDDED
+/* WARNING - the following is hand-optimized to fit within
+ * the sector before the environment sector. If it throws
+ * an error during compilation remove an object here to get
+ * it linked after the configuration sector.
+ */
+# define LDS_BOARD_TEXT \
+	arch/blackfin/lib/built-in.o (.text*); \
+	arch/blackfin/cpu/built-in.o (.text*); \
+	. = DEFINED(env_offset) ? env_offset : .; \
+	common/env_embedded.o (.text*);
+#endif
+
+
+/*
+ * NAND Settings
+ */
+#define CONFIG_NAND_PLAT
+
+#define CONFIG_SYS_NAND_BASE		0x20100000
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+
+#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
+#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
+#define BFIN_NAND_WRITE(addr, cmd) \
+	do { \
+		bfin_write8(addr, cmd); \
+		SSYNC(); \
+	} while (0)
+
+#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
+#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
+#define NAND_PLAT_GPIO_DEV_READY       GPIO_PF12
+
+
+/*
+ * I2C settings
+ */
+#define CONFIG_BFIN_TWI_I2C	1
+#define CONFIG_HARD_I2C		1
+
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_MISC_INIT_R
+#define CONFIG_RTC_BFIN
+#define CONFIG_UART_CONSOLE	0
+
+/* JFFS Partition offset set  */
+#define CONFIG_SYS_JFFS2_FIRST_BANK	0
+#define CONFIG_SYS_JFFS2_NUM_BANKS	1
+/* 512k reserved for u-boot */
+#define CONFIG_SYS_JFFS2_FIRST_SECTOR	15
+
+#define CONFIG_BOOTCOMMAND	"run nandboot"
+#define CONFIG_BOOTARGS_ROOT	"/dev/mtdblock1 rw rootfstype=yaffs"
+
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/bf537-srv1.h b/qemu/roms/u-boot/include/configs/bf537-srv1.h
new file mode 100644
index 000000000..0b723cf93
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/bf537-srv1.h
@@ -0,0 +1,201 @@
+/*
+ * U-boot - Configuration file for CSP Minotaur board
+ *
+ * Thu Oct 25 15:30:44 CEST 2007 <hackfin@section5.ch>
+ *    Minotaur config, brushed up for official uClinux dist.
+ *    Parallel flash support disabled, SPI flash boot command
+ *    added ('run flashboot').
+ *
+ * Flash image map:
+ *
+ * 0x00000000      u-boot bootstrap
+ * 0x00010000      environment
+ * 0x00020000      u-boot code
+ * 0x00030000      uImage.initramfs
+ *
+ */
+
+#ifndef __CONFIG_BF537_SRV1_H__
+#define __CONFIG_BF537_SRV1_H__
+
+#include <asm/config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU             bf537-0.2
+#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_SPI_MASTER
+
+
+/*
+ * Clock Settings
+ *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz					*/
+#define CONFIG_CLKIN_HZ			22118400
+/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
+/*                                                1 = CLKIN / 2		*/
+#define CONFIG_CLKIN_HALF		0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
+/*                                                1 = bypass PLL	*/
+#define CONFIG_PLL_BYPASS		0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
+/* Values can range from 0-63 (where 0 means 64)			*/
+#define CONFIG_VCO_MULT			20
+/* CCLK_DIV controls the core clock divider				*/
+/* Values can be 1, 2, 4, or 8 ONLY					*/
+#define CONFIG_CCLK_DIV			1
+/* SCLK_DIV controls the system clock divider				*/
+/* Values can range from 1-15						*/
+#define CONFIG_SCLK_DIV			5
+
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_SIZE			32
+#define CONFIG_MEM_ADD_WDTH		9
+
+#define CONFIG_EBIU_SDRRC_VAL		0x2ac
+#define CONFIG_EBIU_SDGCTL_VAL		0x91110d
+
+#define CONFIG_EBIU_AMGCTL_VAL		0xFF
+#define CONFIG_EBIU_AMBCTL0_VAL		0x7BB07BB0
+#define CONFIG_EBIU_AMBCTL1_VAL		0xFFC27BB0
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)
+#define CONFIG_SYS_MALLOC_LEN		(384 << 10)
+
+
+/*
+ * Network Settings
+ */
+#ifndef __ADSPBF534__
+#define CONFIG_BFIN_MAC
+#define CONFIG_NETCONSOLE	1
+#endif
+#ifdef CONFIG_BFIN_MAC
+#define CONFIG_IPADDR		192.168.0.15
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_GATEWAYIP	192.168.0.1
+#define CONFIG_SERVERIP		192.168.0.2
+#define CONFIG_HOSTNAME		bf537-srv1
+#endif
+
+#define CONFIG_SYS_AUTOLOAD	"no"
+#define CONFIG_ROOTPATH		"/romfs"
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR	02:80:ad:20:31:42 */
+#define CONFIG_LIB_RAND
+
+/*
+ * Flash Settings
+ */
+/* We don't have a parallel flash chip there */
+#define CONFIG_SYS_NO_FLASH
+
+
+/*
+ * SPI Settings
+ */
+#define CONFIG_BFIN_SPI
+#define CONFIG_ENV_SPI_MAX_HZ	30000000
+#define CONFIG_SF_DEFAULT_SPEED	30000000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+
+
+/*
+ * Env Storage Settings
+ */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET	0x10000
+#define CONFIG_ENV_SIZE		0x10000
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
+
+
+/*
+ * I2C settings
+ */
+#define CONFIG_BFIN_TWI_I2C	1
+#define CONFIG_HARD_I2C		1
+#define CONFIG_SYS_I2C_SPEED		50000
+#define CONFIG_SYS_I2C_SLAVE		0
+
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_SYS_LONGHELP		1
+#define CONFIG_CMDLINE_EDITING	1
+#define CONFIG_ENV_OVERWRITE	1
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_UART_CONSOLE	0
+#define CONFIG_BFIN_SERIAL
+
+#define CONFIG_PANIC_HANG	1
+#define CONFIG_RTC_BFIN		1
+#define CONFIG_BOOT_RETRY_TIME	-1
+#define CONFIG_LOADS_ECHO		1
+
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
+# define CONFIG_BOOTDELAY	-1
+#else
+# define CONFIG_BOOTDELAY	5
+#endif
+
+#include <config_cmd_default.h>
+
+#ifdef CONFIG_BFIN_MAC
+# define CONFIG_CMD_DHCP
+# define CONFIG_CMD_PING
+#else
+# undef CONFIG_CMD_NET
+# undef CONFIG_CMD_NFS
+#endif
+
+#define CONFIG_CMD_BOOTLDR
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ELF
+#undef CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_SF
+
+#define CONFIG_BOOTCOMMAND	"run flashboot"
+#define CONFIG_BOOTARGS	"root=/dev/mtdblock0 rw"
+#define CONFIG_SYS_PROMPT	"srv1> "
+
+#define BOOT_ENV_SETTINGS \
+	"update=tftpboot $(loadaddr) u-boot.ldr;" \
+		"sf probe " __stringify(BFIN_BOOT_SPI_SSEL) ";" \
+		"sf erase 0 0x30000;" \
+		"sf write $(loadaddr) 0 $(filesize)" \
+	"flashboot=sf read 0x1000000 0x30000 0x320000;" \
+		"bootm 0x1000000\0"
+#ifdef CONFIG_BFIN_MAC
+# define NETWORK_ENV_SETTINGS \
+	"nfsargs=setenv bootargs root=/dev/nfs rw " \
+		"nfsroot=$(serverip):$(rootpath)\0" \
+	"addip=setenv bootargs $(bootargs) " \
+		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
+		":$(hostname):eth0:off\0" \
+	"ramboot=tftpboot $(loadaddr) linux;" \
+		"run ramargs;run addip;bootelf\0" \
+	"nfsboot=tftpboot $(loadaddr) linux;" \
+		"run nfsargs;run addip;bootelf\0"
+#else
+# define NETWORK_ENV_SETTINGS
+#endif
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	NETWORK_ENV_SETTINGS \
+	"ramargs=setenv bootargs " CONFIG_BOOTARGS "\0" \
+	BOOT_ENV_SETTINGS
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/bf537-stamp.h b/qemu/roms/u-boot/include/configs/bf537-stamp.h
new file mode 100644
index 000000000..a302f839a
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/bf537-stamp.h
@@ -0,0 +1,288 @@
+/*
+ * U-boot - Configuration file for BF537 STAMP board
+ */
+
+#ifndef __CONFIG_BF537_STAMP_H__
+#define __CONFIG_BF537_STAMP_H__
+
+#include <asm/config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU             bf537-0.2
+#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
+
+
+/*
+ * Clock Settings
+ *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz					*/
+#define CONFIG_CLKIN_HZ			25000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
+/*                                                1 = CLKIN / 2		*/
+#define CONFIG_CLKIN_HALF		0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
+/*                                                1 = bypass PLL	*/
+#define CONFIG_PLL_BYPASS		0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
+/* Values can range from 0-63 (where 0 means 64)			*/
+#define CONFIG_VCO_MULT			20
+/* CCLK_DIV controls the core clock divider				*/
+/* Values can be 1, 2, 4, or 8 ONLY					*/
+#define CONFIG_CCLK_DIV			1
+/* SCLK_DIV controls the system clock divider				*/
+/* Values can range from 1-15						*/
+#define CONFIG_SCLK_DIV			4
+
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_ADD_WDTH	10
+#define CONFIG_MEM_SIZE		64
+
+#define CONFIG_EBIU_SDRRC_VAL	0x306
+#define CONFIG_EBIU_SDGCTL_VAL	0x91114d
+
+#define CONFIG_EBIU_AMGCTL_VAL	0xFF
+#define CONFIG_EBIU_AMBCTL0_VAL	0x7BB07BB0
+#define CONFIG_EBIU_AMBCTL1_VAL	0xFFC27BB0
+
+#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(384 * 1024)
+
+
+/*
+ * Network Settings
+ */
+#ifndef __ADSPBF534__
+#define ADI_CMDS_NETWORK	1
+#define CONFIG_BFIN_MAC
+#define CONFIG_NETCONSOLE	1
+#endif
+#define CONFIG_HOSTNAME		bf537-stamp
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR	02:80:ad:20:31:e8 */
+#define CONFIG_LIB_RAND
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_BASE		0x20000000
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+/* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */
+#define CONFIG_SYS_MAX_FLASH_SECT	71
+
+
+/*
+ * SPI Settings
+ */
+#define CONFIG_BFIN_SPI
+#define CONFIG_ENV_SPI_MAX_HZ	30000000
+#define CONFIG_SF_DEFAULT_SPEED	30000000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_ALL
+
+
+/*
+ * Env Storage Settings
+ */
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET	0x10000
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OFFSET	0x4000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x2000
+#endif
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
+#define ENV_IS_EMBEDDED
+#else
+#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
+#endif
+#ifdef ENV_IS_EMBEDDED
+/* WARNING - the following is hand-optimized to fit within
+ * the sector before the environment sector. If it throws
+ * an error during compilation remove an object here to get
+ * it linked after the configuration sector.
+ */
+# define LDS_BOARD_TEXT \
+	arch/blackfin/lib/built-in.o (.text*); \
+	arch/blackfin/cpu/built-in.o (.text*); \
+	. = DEFINED(env_offset) ? env_offset : .; \
+	common/env_embedded.o (.text*);
+#endif
+
+
+/*
+ * I2C Settings
+ */
+#define CONFIG_BFIN_TWI_I2C	1
+#define CONFIG_HARD_I2C		1
+
+
+/*
+ * SPI_MMC Settings
+ */
+#define CONFIG_MMC_SPI
+#ifdef CONFIG_MMC_SPI
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#endif
+
+/*
+ * NAND Settings
+ */
+/* #define CONFIG_NAND_PLAT */
+#ifdef CONFIG_NAND_PLAT
+#define CONFIG_SYS_NAND_BASE		0x20212000
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+
+#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
+#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
+#define BFIN_NAND_WRITE(addr, cmd) \
+	do { \
+		bfin_write8(addr, cmd); \
+		SSYNC(); \
+	} while (0)
+
+#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
+#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
+#define NAND_PLAT_GPIO_DEV_READY       GPIO_PF3
+#endif /* CONFIG_NAND_PLAT */
+
+/*
+ * CF-CARD IDE-HDD Support
+ */
+
+/*
+ * Add CF flash card support in TRUE-IDE Mode (CF-IDE-NAND Card)
+ * Strange address mapping Blackfin A13 connects to CF_A0
+ */
+
+/* #define CONFIG_BFIN_TRUE_IDE */
+
+/*
+ * Add CF flash card support in Common Memory Mode (CF-IDE-NAND Card)
+ * This should be the preferred mode
+ */
+
+/* #define CONFIG_BFIN_CF_IDE */
+
+/*
+ * Add IDE Disk Drive (HDD) support
+ * See example interface here:
+ * http://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:drivers:ide-blackfin
+ */
+
+/* #define CONFIG_BFIN_HDD_IDE */
+
+#if defined(CONFIG_BFIN_CF_IDE) || \
+    defined(CONFIG_BFIN_HDD_IDE) || \
+    defined(CONFIG_BFIN_TRUE_IDE)
+# define CONFIG_BFIN_IDE	1
+# define CONFIG_CMD_IDE
+#endif
+
+#if defined(CONFIG_BFIN_IDE)
+
+#define CONFIG_DOS_PARTITION	1
+/*
+ * IDE/ATA stuff
+ */
+#undef  CONFIG_IDE_8xx_DIRECT	/* no pcmcia interface required */
+#undef  CONFIG_IDE_LED		/* no led for ide supported */
+#undef  CONFIG_IDE_RESET	/* no reset for ide supported */
+
+#define CONFIG_SYS_IDE_MAXBUS		1
+#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS * 1)
+
+#undef  CONFIG_EBIU_AMBCTL1_VAL
+#define CONFIG_EBIU_AMBCTL1_VAL		0xFFC3FFC3
+
+#define CONFIG_CF_ATASEL_DIS	0x20311800
+#define CONFIG_CF_ATASEL_ENA	0x20311802
+
+#if defined(CONFIG_BFIN_TRUE_IDE)
+/*
+ * Note that these settings aren't for the most part used in include/ata.h
+ * when all of the ATA registers are setup
+ */
+#define CONFIG_SYS_ATA_BASE_ADDR	0x2031C000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0020	/* data I/O */
+#define CONFIG_SYS_ATA_REG_OFFSET	0x0020	/* normal register accesses */
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x001C	/* alternate registers */
+#define CONFIG_SYS_ATA_STRIDE		2	/* CF.A0 --> Blackfin.A13 */
+
+#elif defined(CONFIG_BFIN_CF_IDE)
+#define CONFIG_SYS_ATA_BASE_ADDR	0x20211800
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* data I/O */
+#define CONFIG_SYS_ATA_REG_OFFSET	0x0000	/* normal register accesses */
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x000E	/* alternate registers */
+#define CONFIG_SYS_ATA_STRIDE		1	/* CF_A0=0, with /CE1 /CE2 odd/even byte selects */
+
+#elif defined(CONFIG_BFIN_HDD_IDE)
+#define CONFIG_SYS_ATA_BASE_ADDR	0x20314000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0020	/* data I/O */
+#define CONFIG_SYS_ATA_REG_OFFSET	0x0020	/* normal register accesses */
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x001C	/* alternate registers */
+#define CONFIG_SYS_ATA_STRIDE		2	/* CF.A0 --> Blackfin.A1 */
+#undef  CONFIG_SCLK_DIV
+#define CONFIG_SCLK_DIV		8
+#endif
+
+#endif
+
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_RTC_BFIN
+#define CONFIG_UART_CONSOLE	0
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
+
+/* Define if want to do post memory test */
+#undef CONFIG_POST
+#ifdef CONFIG_POST
+#define CONFIG_SYS_POST_HOTKEYS_GPIO	GPIO_PF5
+#define CONFIG_POST_BSPEC1_GPIO_LEDS \
+	GPIO_PF6, GPIO_PF7, GPIO_PF8, GPIO_PF9, GPIO_PF10, GPIO_PF11,
+#define CONFIG_POST_BSPEC2_GPIO_BUTTONS \
+	GPIO_PF5, GPIO_PF4, GPIO_PF3, GPIO_PF2,
+#define CONFIG_POST_BSPEC2_GPIO_NAMES \
+	10, 11, 12, 13,
+#define CONFIG_SYS_POST_FLASH_START	11
+#define CONFIG_SYS_POST_FLASH_END	71
+#endif
+
+/* These are for board tests */
+#if 0
+#define CONFIG_BOOTCOMMAND       "bootldr 0x203f0100"
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT \
+	"autoboot in %d seconds: press space to stop\n", bootdelay
+#define CONFIG_AUTOBOOT_STOP_STR " "
+#endif
+
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/bf538f-ezkit.h b/qemu/roms/u-boot/include/configs/bf538f-ezkit.h
new file mode 100644
index 000000000..742c299d2
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/bf538f-ezkit.h
@@ -0,0 +1,144 @@
+/*
+ * U-boot - Configuration file for BF538F EZ-Kit Lite board
+ */
+
+#ifndef __CONFIG_BF538F_EZKIT_H__
+#define __CONFIG_BF538F_EZKIT_H__
+
+#include <asm/config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU             bf538-0.4
+#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
+
+
+/*
+ * Clock Settings
+ *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz					*/
+#define CONFIG_CLKIN_HZ			25000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
+/*                                                1 = CLKIN / 2		*/
+#define CONFIG_CLKIN_HALF		0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
+/*                                                1 = bypass PLL	*/
+#define CONFIG_PLL_BYPASS		0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
+/* Values can range from 0-63 (where 0 means 64)			*/
+#define CONFIG_VCO_MULT			21
+/* CCLK_DIV controls the core clock divider				*/
+/* Values can be 1, 2, 4, or 8 ONLY					*/
+#define CONFIG_CCLK_DIV			1
+/* SCLK_DIV controls the system clock divider				*/
+/* Values can range from 1-15						*/
+#define CONFIG_SCLK_DIV			4
+
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_ADD_WDTH	10
+#define CONFIG_MEM_SIZE		64
+
+#define CONFIG_EBIU_SDRRC_VAL	(0x03F6)
+#define CONFIG_EBIU_SDGCTL_VAL	(SCTLE | PSS | TWR_2 | TRCD_3 | TRP_3 | TRAS_6 | PASR_ALL | CL_3)
+
+#define CONFIG_EBIU_AMGCTL_VAL	(CDPRIO | AMBEN_ALL | AMCKEN)
+#define CONFIG_EBIU_AMBCTL0_VAL	(B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
+#define CONFIG_EBIU_AMBCTL1_VAL	(B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
+
+#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN	(384 * 1024)
+
+
+/*
+ * Network Settings
+ */
+#define ADI_CMDS_NETWORK	1
+#define CONFIG_SMC91111	1
+#define CONFIG_SMC91111_BASE	0x20310300
+#define CONFIG_HOSTNAME		bf538f-ezkit
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR	02:80:ad:20:31:e8 */
+
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_BASE		0x20000000
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	71
+
+
+/*
+ * SPI Settings
+ */
+#define CONFIG_BFIN_SPI
+#define CONFIG_ENV_SPI_MAX_HZ	30000000
+#define CONFIG_SF_DEFAULT_SPEED	30000000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_ALL
+
+
+/*
+ * Env Storage Settings
+ */
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET	0x4000
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x2000
+#else
+#define	CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OFFSET	0x4000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SIZE		0x2000
+#define	CONFIG_ENV_SECT_SIZE	0x2000
+#endif
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
+#define ENV_IS_EMBEDDED
+#else
+#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
+#endif
+#ifdef ENV_IS_EMBEDDED
+/* WARNING - the following is hand-optimized to fit within
+ * the sector before the environment sector. If it throws
+ * an error during compilation remove an object here to get
+ * it linked after the configuration sector.
+ */
+# define LDS_BOARD_TEXT \
+	arch/blackfin/lib/built-in.o (.text*); \
+	arch/blackfin/cpu/built-in.o (.text*); \
+	. = DEFINED(env_offset) ? env_offset : .; \
+	common/env_embedded.o (.text*);
+#endif
+
+
+/*
+ * I2C Settings
+ */
+#define CONFIG_BFIN_TWI_I2C	1
+#define CONFIG_HARD_I2C		1
+
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_RTC_BFIN
+#define CONFIG_UART_CONSOLE	0
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/bf548-ezkit.h b/qemu/roms/u-boot/include/configs/bf548-ezkit.h
new file mode 100644
index 000000000..1a245a2b8
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/bf548-ezkit.h
@@ -0,0 +1,213 @@
+/*
+ * U-boot - Configuration file for BF548 STAMP board
+ */
+
+#ifndef __CONFIG_BF548_EZKIT_H__
+#define __CONFIG_BF548_EZKIT_H__
+
+#include <asm/config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU             bf548-0.0
+#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
+
+
+/*
+ * Clock Settings
+ *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz					*/
+#define CONFIG_CLKIN_HZ			25000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
+/*                                                1 = CLKIN / 2		*/
+#define CONFIG_CLKIN_HALF		0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
+/*                                                1 = bypass PLL	*/
+#define CONFIG_PLL_BYPASS		0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
+/* Values can range from 0-63 (where 0 means 64)			*/
+#define CONFIG_VCO_MULT			21
+/* CCLK_DIV controls the core clock divider				*/
+/* Values can be 1, 2, 4, or 8 ONLY					*/
+#define CONFIG_CCLK_DIV			1
+/* SCLK_DIV controls the system clock divider				*/
+/* Values can range from 1-15						*/
+#define CONFIG_SCLK_DIV			4
+
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_ADD_WDTH	10
+#define CONFIG_MEM_SIZE		64
+
+#define CONFIG_EBIU_DDRCTL0_VAL	0x218A83FE
+#define CONFIG_EBIU_DDRCTL1_VAL	0x20022222
+#define CONFIG_EBIU_DDRCTL2_VAL	0x00000021
+
+/* Default EZ-Kit bank mapping:
+ *	Async Bank 0 - 32MB Burst Flash
+ *	Async Bank 1 - Ethernet
+ *	Async Bank 2 - Nothing
+ *	Async Bank 3 - Nothing
+ */
+#define CONFIG_EBIU_AMGCTL_VAL	0xFF
+#define CONFIG_EBIU_AMBCTL0_VAL	0x7BB07BB0
+#define CONFIG_EBIU_AMBCTL1_VAL	0xFFC27BB0
+#define CONFIG_EBIU_FCTL_VAL	(BCLK_4)
+#define CONFIG_EBIU_MODE_VAL	(B0MODE_FLASH)
+
+#define CONFIG_SYS_MONITOR_LEN	(1024 * 1024)
+#define CONFIG_SYS_MALLOC_LEN	(768 * 1024)
+
+
+/*
+ * Network Settings
+ */
+#define ADI_CMDS_NETWORK	1
+#define CONFIG_SMC911X	1
+#define CONFIG_SMC911X_BASE	0x24000000
+#define CONFIG_SMC911X_16_BIT
+#define CONFIG_HOSTNAME		bf548-ezkit
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR	02:80:ad:20:31:e8 */
+
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_BASE		0x20000000
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	259
+
+
+/*
+ * SPI Settings
+ */
+#define CONFIG_BFIN_SPI
+#define CONFIG_ENV_SPI_MAX_HZ	30000000
+#define CONFIG_SF_DEFAULT_SPEED	30000000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+
+
+/*
+ * Env Storage Settings
+ */
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET	0x10000
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
+#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET	0x60000
+#define CONFIG_ENV_SIZE		0x20000
+#else
+/* The BF548-EZKIT uses a top boot flash */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_OFFSET	(0x1000000 - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_SECT_SIZE	0x8000
+#endif
+
+/*
+ * NAND Settings
+ */
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
+#define CONFIG_BFIN_NFC_CTL_VAL        0x0033
+#define CONFIG_BFIN_NFC_BOOTROM_ECC
+#define CONFIG_DRIVER_NAND_BFIN
+#define CONFIG_SYS_NAND_BASE           0 /* not actually used */
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#endif
+
+/*
+ * I2C Settings
+ */
+#define CONFIG_BFIN_TWI_I2C	1
+#define CONFIG_HARD_I2C		1
+
+
+/*
+ * SATA
+ */
+#if !defined(__ADSPBF544__)
+#define CONFIG_LIBATA
+#define CONFIG_SYS_SATA_MAX_DEVICE 1
+#define CONFIG_LBA48
+#define CONFIG_PATA_BFIN
+#define CONFIG_BFIN_ATAPI_BASE_ADDR	0xFFC03800
+#define CONFIG_BFIN_ATA_MODE	XFER_PIO_4
+#endif
+
+
+/*
+ * SDH Settings
+ */
+#if !defined(__ADSPBF544__)
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_BFIN_SDH
+#endif
+
+
+/*
+ * USB Settings
+ */
+#if !defined(__ADSPBF544__)
+#define CONFIG_USB
+#define CONFIG_MUSB_HCD
+#define CONFIG_USB_BLACKFIN
+#define CONFIG_USB_STORAGE
+#define CONFIG_MUSB_TIMEOUT 100000
+#endif
+
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_SIZE_LIMIT $$(( 512 * 1024 ))
+#define CONFIG_RTC_BFIN
+#define CONFIG_UART_CONSOLE	1
+#define CONFIG_BFIN_SPI_IMG_SIZE 0x50000
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
+
+#define CONFIG_ADI_GPIO2
+
+#undef CONFIG_VIDEO
+#ifdef CONFIG_VIDEO
+#define EASYLOGO_HEADER < asm/bfin_logo_230x230_gzip.h >
+#define CONFIG_DEB_DMA_URGENT
+#endif
+
+/* Define if want to do post memory test */
+#undef CONFIG_POST
+#ifdef CONFIG_POST
+#define CONFIG_POST_BSPEC1_GPIO_LEDS \
+	GPIO_PG6, GPIO_PG7, GPIO_PG8, GPIO_PG9, GPIO_PG10, GPIO_PG11,
+#define CONFIG_POST_BSPEC2_GPIO_BUTTONS \
+	GPIO_PB8, GPIO_PB9, GPIO_PB10, GPIO_PB11
+#define CONFIG_POST_BSPEC2_GPIO_NAMES \
+	13, 12, 11, 10,
+#define CONFIG_SYS_POST_FLASH_START	10
+#define CONFIG_SYS_POST_FLASH_END	127
+#endif
+
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/bf561-acvilon.h b/qemu/roms/u-boot/include/configs/bf561-acvilon.h
new file mode 100644
index 000000000..3db917e37
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/bf561-acvilon.h
@@ -0,0 +1,170 @@
+/*
+ * U-boot - Configuration file for BF561 Acvilon System On Module
+ * For more information please go to http://www.niistt.ru/
+ */
+
+#ifndef __CONFIG_BF561_ACVILON_H__
+#define __CONFIG_BF561_ACVILON_H__
+
+#include <asm/config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU             bf561-0.5
+#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
+
+
+/*
+ * Clock Settings
+ *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz					*/
+#define CONFIG_CLKIN_HZ				12000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
+/*                                                1 = CLKIN / 2		*/
+#define CONFIG_CLKIN_HALF			0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
+/*                                                1 = bypass PLL	*/
+#define CONFIG_PLL_BYPASS			0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
+/* Values can range from 0-63 (where 0 means 64)			*/
+#define CONFIG_VCO_MULT				50
+/* CCLK_DIV controls the core clock divider				*/
+/* Values can be 1, 2, 4, or 8 ONLY					*/
+#define CONFIG_CCLK_DIV				1
+/* SCLK_DIV controls the system clock divider				*/
+/* Values can range from 1-15						*/
+#define CONFIG_SCLK_DIV				5
+
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_ADD_WDTH			10
+#define CONFIG_MEM_SIZE				128
+
+#define CONFIG_EBIU_SDRRC_VAL		0x300
+#define CONFIG_EBIU_SDGCTL_VAL		0x00B11189
+
+#define CONFIG_EBIU_AMGCTL_VAL		0x4e
+#define CONFIG_EBIU_AMBCTL0_VAL		0xffc2ffc2
+#define CONFIG_EBIU_AMBCTL1_VAL		0x99b35554
+
+#define CONFIG_SYS_MONITOR_LEN		(384 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)
+
+
+/*
+ * RTC Settings
+ */
+#define CONFIG_RTC_DS1337
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+
+/* I2C SYSMON (LM75, AD7414 is almost compatible)                       */
+#define CONFIG_DTT_LM75         1               /* ON Semi's LM75       */
+#define CONFIG_DTT_SENSORS      {0}             /* Sensor addresses     */
+#define CONFIG_SYS_I2C_DTT_ADDR 0x49
+/*#define CONFIG_SYS_DTT_MAX_TEMP 70
+#define CONFIG_SYS_DTT_LOW_TEMP -30
+#define CONFIG_SYS_DTT_HYSTERESIS       3*/
+
+
+/*
+ * Network Settings
+ */
+#define ADI_CMDS_NETWORK			1
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DTT
+
+#if defined(CONFIG_CMD_NET)
+
+#define CONFIG_SMC911X				1
+#define CONFIG_SMC911X_32_BIT
+/* #define CONFIG_SMC911X_16_BIT */
+#define CONFIG_SMC911X_BASE			0x28000000
+
+#endif /* (CONFIG_CMD_NET) */
+
+#define CONFIG_HOSTNAME		bf561-acvilon
+
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR				02:80:ad:20:31:e8 */
+
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_SYS_NO_FLASH
+
+
+/*
+ * I2C Settings
+ */
+#define CONFIG_HARD_I2C
+/* Use 300kHz speed by default */
+#define CONFIG_SYS_I2C_SPEED			0x00
+#define CONFIG_PCA9564_I2C
+#define CONFIG_PCA9564_BASE			0x2c000000
+
+
+/*
+ * SPI Settings
+ */
+#define CONFIG_BFIN_SPI
+#define CONFIG_ENV_SPI_MAX_HZ		10000000
+#define CONFIG_SF_DEFAULT_SPEED		10000000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_ATMEL
+
+
+/*
+ * Env Storage Settings
+ */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+/* #define CONFIG_CMD_SAVEENV */
+#define CONFIG_ENV_SECT_SIZE		(1056 * 8)
+#define CONFIG_ENV_OFFSET			((16 + 256) * 1056)
+#define CONFIG_ENV_SIZE				(8 * 1056)
+
+
+/*
+ * NAND Settings
+ * We're using NAND_PLAT driver to make things simplier
+ */
+#define CONFIG_NAND_PLAT
+#define CONFIG_CMD_NAND
+#define CONFIG_SYS_NAND_BASE		0x24000000
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+
+#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
+#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 3))
+#define BFIN_NAND_WRITE(addr, cmd) \
+	do { \
+		bfin_write8(addr, cmd); \
+		SSYNC(); \
+	} while (0)
+
+#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
+#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
+#define NAND_PLAT_GPIO_DEV_READY       GPIO_PF10
+
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_UART_CONSOLE			0
+#define CONFIG_BAUDRATE				57600
+#define CONFIG_SYS_PROMPT "Acvilon> "
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+#endif				/* __CONFIG_BF561_ACVILON_H__ */
diff --git a/qemu/roms/u-boot/include/configs/bf561-ezkit.h b/qemu/roms/u-boot/include/configs/bf561-ezkit.h
new file mode 100644
index 000000000..0a309d926
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/bf561-ezkit.h
@@ -0,0 +1,118 @@
+/*
+ * U-boot - Configuration file for BF561 EZKIT board
+ */
+
+#ifndef __CONFIG_BF561_EZKIT_H__
+#define __CONFIG_BF561_EZKIT_H__
+
+#include <asm/config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU             bf561-0.3
+#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
+
+
+/*
+ * Clock Settings
+ *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz					*/
+#define CONFIG_CLKIN_HZ			30000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
+/*                                                1 = CLKIN / 2		*/
+#define CONFIG_CLKIN_HALF		0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
+/*                                                1 = bypass PLL	*/
+#define CONFIG_PLL_BYPASS		0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
+/* Values can range from 0-63 (where 0 means 64)			*/
+#define CONFIG_VCO_MULT			20
+/* CCLK_DIV controls the core clock divider				*/
+/* Values can be 1, 2, 4, or 8 ONLY					*/
+#define CONFIG_CCLK_DIV			1
+/* SCLK_DIV controls the system clock divider				*/
+/* Values can range from 1-15						*/
+#define CONFIG_SCLK_DIV			6
+
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_ADD_WDTH	9
+#define CONFIG_MEM_SIZE		64
+
+#define CONFIG_EBIU_SDRRC_VAL	0x306
+#define CONFIG_EBIU_SDGCTL_VAL	0x91114d
+
+#define CONFIG_EBIU_AMGCTL_VAL	0x3F
+#define CONFIG_EBIU_AMBCTL0_VAL	0x7BB07BB0
+#define CONFIG_EBIU_AMBCTL1_VAL	0xFFC27BB0
+
+#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN	(128 * 1024)
+
+
+/*
+ * Network Settings
+ */
+#define ADI_CMDS_NETWORK	1
+#define CONFIG_SMC91111	1
+#define CONFIG_SMC91111_BASE	0x2C010300
+#define CONFIG_SMC_USE_32_BIT	1
+#define CONFIG_HOSTNAME		bf561-ezkit
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR	02:80:ad:20:31:e8 */
+
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI_AMD_RESET
+#define CONFIG_SYS_FLASH_BASE		0x20000000
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	135
+/* The BF561-EZKIT uses a top boot flash */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_OFFSET	(0x800000 - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_SECT_SIZE	0x2000
+
+
+/*
+ * I2C Settings
+ */
+#define CONFIG_SYS_I2C_SOFT
+#ifdef CONFIG_SYS_I2C_SOFT
+#define CONFIG_SYS_I2C
+#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF0
+#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF1
+#define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
+#define CONFIG_SYS_I2C_SOFT_SPEED	50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0
+#endif
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_UART_CONSOLE	0
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
+
+/*
+ * Run core 1 from L1 SRAM start address when init uboot on core 0
+ */
+/* #define CONFIG_CORE1_RUN	1 */
+
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/bf609-ezkit.h b/qemu/roms/u-boot/include/configs/bf609-ezkit.h
new file mode 100644
index 000000000..12192ffb5
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/bf609-ezkit.h
@@ -0,0 +1,173 @@
+/*
+ * U-boot - Configuration file for BF609 EZ-Kit board
+ */
+
+#ifndef __CONFIG_BF609_EZKIT_H__
+#define __CONFIG_BF609_EZKIT_H__
+
+#include <asm/config-pre.h>
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU             bf609-0.0
+#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
+
+
+/* For ez-board version 1.0, else undef this */
+#define CONFIG_BFIN_BOARD_VERSION_1_0
+
+/*
+ * Clock Settings
+ *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ *	SCLK = (CLKIN * VCO_MULT) / SYSCLK_DIV
+ *	SCLK0 = SCLK / SCLK0_DIV
+ *	SCLK1 = SCLK / SCLK1_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz					*/
+#define CONFIG_CLKIN_HZ			(25000000)
+/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
+/*                                                1 = CLKIN / 2		*/
+#define CONFIG_CLKIN_HALF		(0)
+
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
+/* Values can range from 0-127 (where 0 means 128)			*/
+#define CONFIG_VCO_MULT			(20)
+
+/* CCLK_DIV controls the core clock divider				*/
+/* Values can range from 0-31 (where 0 means 32)			*/
+#define CONFIG_CCLK_DIV			(1)
+/* SCLK_DIV controls the system clock divider				*/
+/* Values can range from 0-31 (where 0 means 32)			*/
+#define CONFIG_SCLK_DIV		(4)
+/* Values can range from 0-7 (where 0 means 8)				*/
+#define CONFIG_SCLK0_DIV		(1)
+#define CONFIG_SCLK1_DIV		(1)
+/* DCLK_DIV controls the DDR clock divider				*/
+/* Values can range from 0-31 (where 0 means 32)			*/
+#define CONFIG_DCLK_DIV			(2)
+/* OCLK_DIV controls the output clock divider				*/
+/* Values can range from 0-127 (where 0 means 128)			*/
+#define CONFIG_OCLK_DIV			(16)
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_SIZE		128
+
+#define CONFIG_SMC_GCTL_VAL	0x00000010
+#define CONFIG_SMC_B0CTL_VAL	0x01007011
+#define CONFIG_SMC_B0TIM_VAL	0x08170977
+#define CONFIG_SMC_B0ETIM_VAL	0x00092231
+
+#define CONFIG_SYS_MONITOR_LEN	(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN	(512 * 1024)
+
+#define CONFIG_HW_WATCHDOG
+/*
+ * Network Settings
+ */
+#define ADI_CMDS_NETWORK
+#define CONFIG_NETCONSOLE
+#define CONFIG_NET_MULTI
+#define CONFIG_HOSTNAME		"bf609-ezkit"
+#define CONFIG_DESIGNWARE_ETH
+#define CONFIG_PHY_ADDR		1
+#define CONFIG_DW_PORTS		1
+#define CONFIG_DW_ALTDESCRIPTOR
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_MII
+#define CONFIG_PHYLIB
+
+/* i2c Settings */
+#define CONFIG_BFIN_TWI_I2C
+#define CONFIG_HARD_I2C
+
+/*
+ * Flash Settings
+ */
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_JFFS2
+#define CONFIG_SYS_FLASH_CFI_WIDTH     2
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_BASE          0xb0000000
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS     1
+#define CONFIG_SYS_MAX_FLASH_SECT      131
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+
+/*
+ * SPI Settings
+ */
+#define CONFIG_BFIN_SPI6XX
+#define CONFIG_ENV_SPI_MAX_HZ	25000000
+#define CONFIG_SF_DEFAULT_SPEED	25000000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_ALL
+
+/*
+ * Env Storage Settings
+ */
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET       0x10000
+#define CONFIG_ENV_SIZE         0x2000
+#define CONFIG_ENV_SECT_SIZE    0x10000
+#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
+#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET       0x60000
+#define CONFIG_ENV_SIZE         0x20000
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_OFFSET       0x8000
+#define CONFIG_ENV_SIZE         0x8000
+#define CONFIG_ENV_SECT_SIZE    0x8000
+#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
+#endif
+
+#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0xB0100000\0"
+
+/*
+ * SDH Settings
+ */
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_BFIN_SDH
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_UART_CONSOLE	0
+
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_SOFTSWITCH
+
+#define CONFIG_SYS_MEMTEST_END (CONFIG_STACKBASE - 20*1024*1024 + 4)
+#define CONFIG_BFIN_SOFT_SWITCH
+
+#define CONFIG_ADI_GPIO2
+
+#if 0
+#define CONFIG_UART_MEM 1024
+#undef CONFIG_UART_CONSOLE
+#undef CONFIG_JTAG_CONSOLE
+#undef CONFIG_UART_CONSOLE_IS_JTAG
+#endif
+
+#define CONFIG_BOARD_SIZE_LIMIT $$((512 * 1024))
+
+/*
+ * Run core 1 from L1 SRAM start address when init uboot on core 0
+ */
+/* #define CONFIG_CORE1_RUN	1 */
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+#endif
diff --git a/qemu/roms/u-boot/include/configs/bfin_adi_common.h b/qemu/roms/u-boot/include/configs/bfin_adi_common.h
new file mode 100644
index 000000000..ea9acf69d
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/bfin_adi_common.h
@@ -0,0 +1,330 @@
+/*
+ * U-Boot - Common settings for Analog Devices boards
+ */
+
+#ifndef __CONFIG_BFIN_ADI_COMMON_H__
+#define __CONFIG_BFIN_ADI_COMMON_H__
+
+/*
+ * Command Settings
+ */
+#ifndef _CONFIG_CMD_DEFAULT_H
+# include <config_cmd_default.h>
+# ifdef ADI_CMDS_NETWORK
+#  define CONFIG_CMD_DHCP
+#  define CONFIG_BOOTP_SUBNETMASK
+#  define CONFIG_BOOTP_GATEWAY
+#  define CONFIG_BOOTP_DNS
+#  define CONFIG_BOOTP_NTPSERVER
+#  define CONFIG_BOOTP_RANDOM_DELAY
+#  define CONFIG_LIB_RAND
+#  define CONFIG_KEEP_SERVERADDR
+#  define CONFIG_CMD_DNS
+#  define CONFIG_CMD_PING
+#  ifdef CONFIG_BFIN_MAC
+#   define CONFIG_CMD_MII
+#  endif
+# else
+#  undef CONFIG_CMD_BOOTD
+#  undef CONFIG_CMD_NET
+#  undef CONFIG_CMD_NFS
+# endif
+# ifdef CONFIG_LIBATA
+#  define CONFIG_CMD_FAT
+#  define CONFIG_CMD_SATA
+#  define CONFIG_DOS_PARTITION
+# endif
+# ifdef CONFIG_MMC
+#  define CONFIG_CMD_EXT2
+#  define CONFIG_CMD_FAT
+#  define CONFIG_CMD_MMC
+#  define CONFIG_DOS_PARTITION
+# endif
+# ifdef CONFIG_MMC_SPI
+#  define CONFIG_CMD_MMC_SPI
+# endif
+# ifdef CONFIG_USB
+#  define CONFIG_CMD_EXT2
+#  define CONFIG_CMD_FAT
+#  define CONFIG_CMD_USB
+#  define CONFIG_CMD_USB_STORAGE
+#  define CONFIG_DOS_PARTITION
+# endif
+# if defined(CONFIG_NAND_PLAT) || defined(CONFIG_DRIVER_NAND_BFIN)
+#  define CONFIG_CMD_NAND
+#  define CONFIG_CMD_NAND_LOCK_UNLOCK
+# endif
+# ifdef CONFIG_POST
+#  define CONFIG_CMD_DIAG
+# endif
+# ifdef CONFIG_RTC_BFIN
+#  define CONFIG_CMD_DATE
+#  ifdef ADI_CMDS_NETWORK
+#   define CONFIG_CMD_SNTP
+#  endif
+# endif
+# ifdef CONFIG_SPI
+#  define CONFIG_CMD_EEPROM
+# endif
+# if defined(CONFIG_BFIN_SPI) || defined(CONFIG_SOFT_SPI)
+#  define CONFIG_CMD_SPI
+# endif
+# ifdef CONFIG_SPI_FLASH
+#  define CONFIG_CMD_SF
+# endif
+# if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT)
+#  define CONFIG_CMD_I2C
+#  define CONFIG_SOFT_I2C_READ_REPEATED_START
+# endif
+# ifdef CONFIG_SYS_NO_FLASH
+#  undef CONFIG_CMD_FLASH
+#  undef CONFIG_CMD_IMLS
+# else
+#  define CONFIG_CMD_JFFS2
+# endif
+# ifdef CONFIG_CMD_JFFS2
+#  define CONFIG_JFFS2_SUMMARY
+# endif
+# define CONFIG_CMD_BOOTLDR
+# define CONFIG_CMD_CACHE
+# define CONFIG_CMD_CPLBINFO
+# define CONFIG_CMD_ELF
+# define CONFIG_CMD_GPIO
+# define CONFIG_CMD_KGDB
+# define CONFIG_CMD_LDRINFO
+# define CONFIG_CMD_REGINFO
+# define CONFIG_CMD_STRINGS
+# if defined(__ADSPBF51x__) || defined(__ADSPBF52x__) || defined(__ADSPBF54x__)
+#  define CONFIG_CMD_OTP
+#  define CONFIG_CMD_SPIBOOTLDR
+# endif
+#endif
+
+/*
+ * Console Settings
+ */
+#define CONFIG_SYS_LONGHELP	1
+#define CONFIG_CMDLINE_EDITING	1
+#define CONFIG_AUTO_COMPLETE	1
+#define CONFIG_LOADS_ECHO	1
+#define CONFIG_JTAG_CONSOLE
+#define CONFIG_SILENT_CONSOLE
+#ifndef CONFIG_BAUDRATE
+# define CONFIG_BAUDRATE	57600
+#endif
+#ifdef CONFIG_UART_CONSOLE
+# define CONFIG_BFIN_SERIAL
+#endif
+
+/*
+ * Debug Settings
+ */
+#define CONFIG_ENV_OVERWRITE	1
+#define CONFIG_DEBUG_DUMP	1
+#define CONFIG_KALLSYMS		1
+#define CONFIG_PANIC_HANG	1
+
+/*
+ * Env Settings
+ */
+#ifndef CONFIG_BOOTDELAY
+# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
+#  define CONFIG_BOOTDELAY	-1
+# else
+#  define CONFIG_BOOTDELAY	5
+# endif
+#endif
+#ifndef CONFIG_BOOTCOMMAND
+# define CONFIG_BOOTCOMMAND	"run ramboot"
+#endif
+#ifdef CONFIG_VIDEO
+# define CONFIG_BOOTARGS_VIDEO "console=tty0 "
+#else
+# define CONFIG_BOOTARGS_VIDEO ""
+#endif
+#ifndef CONFIG_BOOTARGS_ROOT
+# define CONFIG_BOOTARGS_ROOT "/dev/mtdblock0 rw"
+#endif
+#ifndef FLASHBOOT_ENV_SETTINGS
+# define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20100000\0"
+#endif
+#define CONFIG_BOOTARGS	\
+	"root=" CONFIG_BOOTARGS_ROOT " " \
+	"clkin_hz=" __stringify(CONFIG_CLKIN_HZ) " " \
+	"earlyprintk=" \
+		"serial," \
+		"uart" __stringify(CONFIG_UART_CONSOLE) "," \
+		__stringify(CONFIG_BAUDRATE) " " \
+	CONFIG_BOOTARGS_VIDEO \
+	"console=ttyBF" __stringify(CONFIG_UART_CONSOLE) "," \
+			__stringify(CONFIG_BAUDRATE)
+#if defined(CONFIG_CMD_NAND)
+# define NAND_ENV_SETTINGS \
+	"nandargs=set bootargs " CONFIG_BOOTARGS "\0" \
+	"nandboot=" \
+		"nand read $(loadaddr) 0x20000 0x100000;" \
+		"run nandargs;" \
+		"bootm" \
+		"\0"
+#else
+# define NAND_ENV_SETTINGS
+#endif
+#if defined(CONFIG_CMD_NET)
+# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
+#  define UBOOT_ENV_FILE "u-boot.bin"
+# else
+#  define UBOOT_ENV_FILE "u-boot.ldr"
+# endif
+# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
+#  ifdef CONFIG_SPI
+#   define UBOOT_ENV_UPDATE \
+		"eeprom write $(loadaddr) 0x0 $(filesize)"
+#  else
+#   ifndef CONFIG_BFIN_SPI_IMG_SIZE
+#    define CONFIG_BFIN_SPI_IMG_SIZE 0x40000
+#   endif
+#   define UBOOT_ENV_UPDATE \
+		"sf probe " __stringify(BFIN_BOOT_SPI_SSEL) ";" \
+		"sf erase 0 " __stringify(CONFIG_BFIN_SPI_IMG_SIZE) ";" \
+		"sf write $(loadaddr) 0 $(filesize)"
+#  endif
+# elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
+#  define UBOOT_ENV_UPDATE \
+		"nand unlock 0 0x40000;" \
+		"nand erase 0 0x40000;" \
+		"nand write $(loadaddr) 0 0x40000"
+# else
+#  ifndef UBOOT_ENV_UPDATE
+#   define UBOOT_ENV_UPDATE \
+		"protect off 0x20000000 +$(filesize);" \
+		"erase 0x20000000 +$(filesize);" \
+		"cp.b $(loadaddr) 0x20000000 $(filesize)"
+#  endif
+# endif
+# ifdef CONFIG_NETCONSOLE
+#  define NETCONSOLE_ENV \
+	"nc=" \
+		"set ncip ${serverip};" \
+		"set stdin nc;" \
+		"set stdout nc;" \
+		"set stderr nc" \
+		"\0"
+# else
+#  define NETCONSOLE_ENV
+# endif
+# define NETWORK_ENV_SETTINGS \
+	NETCONSOLE_ENV \
+	\
+	"ubootfile=" UBOOT_ENV_FILE "\0" \
+	"update=" \
+		"tftp $(loadaddr) $(ubootfile);" \
+		UBOOT_ENV_UPDATE \
+		"\0" \
+	"addip=set bootargs $(bootargs) " \
+		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):" \
+		   "$(hostname):eth0:off" \
+		"\0" \
+	\
+	"ramfile=uImage\0" \
+	"ramargs=set bootargs " CONFIG_BOOTARGS "\0" \
+	"ramboot=" \
+		"tftp $(loadaddr) $(ramfile);" \
+		"run ramargs;" \
+		"run addip;" \
+		"bootm" \
+		"\0" \
+	\
+	"nfsfile=vmImage\0" \
+	"nfsargs=set bootargs " \
+		"root=/dev/nfs rw " \
+		"nfsroot=$(serverip):$(rootpath),tcp,nfsvers=3" \
+		"\0" \
+	"nfsboot=" \
+		"tftp $(loadaddr) $(nfsfile);" \
+		"run nfsargs;" \
+		"run addip;" \
+		"bootm" \
+		"\0"
+#else
+# define NETWORK_ENV_SETTINGS
+#endif
+#ifndef BOARD_ENV_SETTINGS
+# define BOARD_ENV_SETTINGS
+#endif
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	NAND_ENV_SETTINGS \
+	NETWORK_ENV_SETTINGS \
+	FLASHBOOT_ENV_SETTINGS \
+	BOARD_ENV_SETTINGS
+
+/*
+ * Network Settings
+ */
+#ifdef CONFIG_CMD_NET
+# define CONFIG_NETMASK		255.255.255.0
+# ifndef CONFIG_IPADDR
+#  define CONFIG_IPADDR		192.168.0.15
+#  define CONFIG_GATEWAYIP	192.168.0.1
+#  define CONFIG_SERVERIP	192.168.0.2
+# endif
+# ifndef CONFIG_ROOTPATH
+#  define CONFIG_ROOTPATH	"/romfs"
+# endif
+# ifdef CONFIG_CMD_DHCP
+#  ifndef CONFIG_SYS_AUTOLOAD
+#   define CONFIG_SYS_AUTOLOAD "no"
+#  endif
+# endif
+# define CONFIG_IP_DEFRAG
+# define CONFIG_NET_RETRY_COUNT 20
+#endif
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_FLASH_SHOW_PROGRESS 45
+
+/*
+ * SPI Settings
+ */
+#ifdef CONFIG_SPI_FLASH_ALL
+# define CONFIG_SPI_FLASH_ATMEL
+# define CONFIG_SPI_FLASH_EON
+# define CONFIG_SPI_FLASH_MACRONIX
+# define CONFIG_SPI_FLASH_SPANSION
+# define CONFIG_SPI_FLASH_SST
+# define CONFIG_SPI_FLASH_STMICRO
+# define CONFIG_SPI_FLASH_WINBOND
+#endif
+
+/*
+ * I2C Settings
+ */
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C_SOFT)
+# ifndef CONFIG_SYS_I2C_SPEED
+#  define CONFIG_SYS_I2C_SPEED 50000
+# endif
+# ifndef CONFIG_SYS_I2C_SLAVE
+#  define CONFIG_SYS_I2C_SLAVE 0
+# endif
+#endif
+
+/*
+ * Misc Settings
+ */
+#ifndef CONFIG_BOARD_SIZE_LIMIT
+# define CONFIG_BOARD_SIZE_LIMIT $$(( 256 * 1024 ))
+#endif
+#define CONFIG_BFIN_SPI_GPIO_CS /* Only matters if BFIN_SPI is enabled */
+#define CONFIG_LZMA
+#define CONFIG_MONITOR_IS_IN_RAM
+#ifdef CONFIG_HW_WATCHDOG
+# define CONFIG_BFIN_WATCHDOG
+# ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS
+#  define CONFIG_WATCHDOG_TIMEOUT_MSECS 5000
+# endif
+#endif
+#ifndef CONFIG_ADI_GPIO2
+# define CONFIG_ADI_GPIO1
+#endif
+#endif
diff --git a/qemu/roms/u-boot/include/configs/bg0900.h b/qemu/roms/u-boot/include/configs/bg0900.h
new file mode 100644
index 000000000..507d972f3
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/bg0900.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __CONFIGS_BG0900_H__
+#define __CONFIGS_BG0900_H__
+
+/* System configurations */
+#define CONFIG_MX28				/* i.MX28 SoC */
+
+/* U-Boot Commands */
+#define CONFIG_SYS_NO_FLASH
+#include <config_cmd_default.h>
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_GPIO
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NAND_TRIMFFS
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+
+/* Memory configuration */
+#define CONFIG_NR_DRAM_BANKS		1		/* 1 bank of DRAM */
+#define PHYS_SDRAM_1			0x40000000	/* Base address */
+#define PHYS_SDRAM_1_SIZE		0x10000000	/* Max 256 MB RAM */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+
+/* Environment */
+#define CONFIG_ENV_SIZE			(16 * 1024)
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_IS_NOWHERE
+
+/* FEC Ethernet on SoC */
+#ifdef	CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_NET_MULTI
+#endif
+
+/* SPI */
+#ifdef CONFIG_CMD_SPI
+#define CONFIG_DEFAULT_SPI_BUS		2
+#define CONFIG_DEFAULT_SPI_CS		0
+#define CONFIG_DEFAULT_SPI_MODE		SPI_MODE_0
+
+/* SPI FLASH */
+#ifdef CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_BAR
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SF_DEFAULT_BUS		2
+#define CONFIG_SF_DEFAULT_CS		0
+#define CONFIG_SF_DEFAULT_SPEED		40000000
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
+
+#define CONFIG_ENV_SPI_BUS		2
+#define CONFIG_ENV_SPI_CS		0
+#define CONFIG_ENV_SPI_MAX_HZ		40000000
+#define CONFIG_ENV_SPI_MODE		SPI_MODE_0
+#endif
+
+#endif
+
+/* Boot Linux */
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_BOOTARGS		"console=ttyAMA0,115200"
+#define CONFIG_BOOTCOMMAND	"bootm"
+#define CONFIG_LOADADDR		0x42000000
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+
+/* Extra Environment */
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"update_spi_firmware_filename=u-boot.sb\0"			\
+	"update_spi_firmware_maxsz=0x80000\0"				\
+	"update_spi_firmware="	/* Update the SPI flash firmware */	\
+		"if sf probe 2:0 ; then "				\
+		"if tftp ${update_spi_firmware_filename} ; then "	\
+		"sf erase 0x0 +${filesize} ; "				\
+		"sf write ${loadaddr} 0x0 ${filesize} ; "		\
+		"fi ; "							\
+		"fi\0"
+
+/* The rest of the configuration is shared */
+#include <configs/mxs.h>
+
+#endif /* __CONFIGS_BG0900_H__ */
diff --git a/qemu/roms/u-boot/include/configs/blackstamp.h b/qemu/roms/u-boot/include/configs/blackstamp.h
new file mode 100644
index 000000000..7de425349
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/blackstamp.h
@@ -0,0 +1,248 @@
+/*
+ * U-boot - Configuration file for BlackStamp board
+ * Configuration by Ben Matthews for UR LLE using bf533-stamp.h
+ * as a template
+ * See http://blackfin.uclinux.org/gf/project/blackstamp/
+ */
+
+#ifndef __CONFIG_BLACKSTAMP_H__
+#define __CONFIG_BLACKSTAMP_H__
+
+#include <asm/config-pre.h>
+
+/*
+ * Debugging: Set these options if you're having problems
+ */
+/*
+ * #define CONFIG_DEBUG_EARLY_SERIAL
+ * #define DEBUG
+ * #define CONFIG_DEBUG_DUMP
+ * #define CONFIG_DEBUG_DUMP_SYMS
+*/
+#define CONFIG_PANIC_HANG 0
+
+/* CPU Options
+ * Be sure to set the Silicon Revision Correctly
+ */
+#define CONFIG_BFIN_CPU		bf532-0.5
+#define CONFIG_BFIN_BOOT_MODE	BFIN_BOOT_SPI_MASTER
+
+/*
+ * Board settings
+ */
+#define CONFIG_SMC91111	1
+#define CONFIG_SMC91111_BASE	0x20300300
+
+/* FLASH/ETHERNET uses the same address range
+ * Depending on what you have the CPLD doing
+ * this probably isn't needed
+ */
+#define SHARED_RESOURCES	1
+
+/* Is I2C bit-banged? */
+
+/*
+ * Clock Settings
+ *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz					*/
+#define CONFIG_CLKIN_HZ			25000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
+/*                                                1 = CLKIN / 2		*/
+#define CONFIG_CLKIN_HALF		0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
+/*                                                1 = bypass PLL	*/
+#define CONFIG_PLL_BYPASS		0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
+/* Values can range from 0-63 (where 0 means 64)			*/
+#define CONFIG_VCO_MULT			16
+/* CCLK_DIV controls the core clock divider				*/
+/* Values can be 1, 2, 4, or 8 ONLY					*/
+#define CONFIG_CCLK_DIV			1
+/* SCLK_DIV controls the system clock divider				*/
+/* Values can range from 1-15						*/
+#define CONFIG_SCLK_DIV			3
+
+/*
+ * Network settings
+ */
+
+#ifdef CONFIG_SMC91111
+#define CONFIG_IPADDR		192.168.0.15
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_GATEWAYIP	192.168.0.1
+#define CONFIG_SERVERIP		192.168.0.2
+#define CONFIG_HOSTNAME		blackstamp
+#define CONFIG_ROOTPATH		"/checkout/uClinux-dist/romfs"
+#define CONFIG_SYS_AUTOLOAD		"no"
+
+/* To remove hardcoding and enable MAC storage in EEPROM  */
+/* #define CONFIG_ETHADDR		02:80:ad:20:31:b8 */
+#endif
+
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET	0x40000
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x40000
+
+/*
+ * SDRAM settings & memory map
+ */
+
+#define CONFIG_MEM_SIZE		64	/* 128, 64, 32, 16 */
+#define CONFIG_MEM_ADD_WDTH	10	/* 8, 9, 10, 11    */
+
+#define CONFIG_SYS_MONITOR_LEN	(256 << 10)
+#define CONFIG_SYS_MALLOC_LEN	(384 << 10)
+
+/*
+ * Command settings
+ */
+
+#define CONFIG_SYS_LONGHELP		1
+#define CONFIG_CMDLINE_EDITING	1
+#define CONFIG_AUTO_COMPLETE	1
+#define CONFIG_ENV_OVERWRITE	1
+
+#include <config_cmd_default.h>
+
+#ifdef CONFIG_SMC91111
+# define CONFIG_CMD_DHCP
+# define CONFIG_CMD_PING
+#else
+# undef CONFIG_CMD_NET
+#endif
+
+#ifdef CONFIG_SYS_I2C_SOFT
+# define CONFIG_CMD_I2C
+#endif
+
+#define CONFIG_CMD_BOOTLDR
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_CPLBINFO
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_ELF
+
+#define CONFIG_BOOTDELAY     5
+#define CONFIG_BOOTCOMMAND   "run ramboot"
+#define CONFIG_BOOTARGS \
+	"root=/dev/mtdblock0 rw " \
+	"clkin_hz=" __stringify(CONFIG_CLKIN_HZ) " " \
+	"earlyprintk=" \
+		"serial," \
+		"uart" __stringify(CONFIG_UART_CONSOLE) "," \
+		__stringify(CONFIG_BAUDRATE) " " \
+	"console=ttyBF0," __stringify(CONFIG_BAUDRATE)
+
+#if defined(CONFIG_CMD_NET)
+# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
+#  define UBOOT_ENV_FILE "u-boot.bin"
+# else
+#  define UBOOT_ENV_FILE "u-boot.ldr"
+# endif
+# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
+#  ifdef CONFIG_SPI
+#   define UBOOT_ENV_UPDATE \
+		"eeprom write $(loadaddr) 0x0 $(filesize)"
+#  else
+#   define UBOOT_ENV_UPDATE \
+		"sf probe " __stringify(BFIN_BOOT_SPI_SSEL) ";" \
+		"sf erase 0 0x40000;" \
+		"sf write $(loadaddr) 0 $(filesize)"
+#  endif
+# else
+#  define UBOOT_ENV_UPDATE \
+		"protect off 0x20000000 0x2003FFFF;" \
+		"erase 0x20000000 0x2003FFFF;" \
+		"cp.b $(loadaddr) 0x20000000 $(filesize)"
+# endif
+# define NETWORK_ENV_SETTINGS \
+	"ubootfile=" UBOOT_ENV_FILE "\0" \
+	"update=" \
+		"tftp $(loadaddr) $(ubootfile);" \
+		UBOOT_ENV_UPDATE \
+		"\0" \
+	"addip=set bootargs $(bootargs) " \
+		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):" \
+		   "$(hostname):eth0:off" \
+		"\0" \
+	"ramargs=set bootargs " CONFIG_BOOTARGS "\0" \
+	"ramboot=" \
+		"tftp $(loadaddr) uImage;" \
+		"run ramargs;" \
+		"run addip;" \
+		"bootm" \
+		"\0" \
+	"nfsargs=set bootargs " \
+		"root=/dev/nfs rw " \
+		"nfsroot=$(serverip):$(rootpath),tcp,nfsvers=3" \
+		"\0" \
+	"nfsboot=" \
+		"tftp $(loadaddr) vmImage;" \
+		"run nfsargs;" \
+		"run addip;" \
+		"bootm" \
+		"\0"
+#else
+# define NETWORK_ENV_SETTINGS
+#endif
+
+/*
+ * Console settings
+ */
+#define CONFIG_BAUDRATE		57600
+#define CONFIG_LOADS_ECHO	1
+#define CONFIG_UART_CONSOLE	0
+#define CONFIG_BFIN_SERIAL
+
+/*
+ * I2C settings
+ * By default PF2 is used as SDA and PF3 as SCL on the Stamp board
+ * Located on the expansion connector on pins 86/85
+ * Note these pins are arbitrarily chosen because we aren't using
+ * them yet. You can (and probably should) change these values!
+ */
+#ifdef CONFIG_SYS_I2C_SOFT
+#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF9
+#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF8
+#define CONFIG_SYS_I2C_SOFT_SPEED	50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_RTC_BFIN		1
+
+/*
+ * Serial Flash Infomation
+ */
+#define CONFIG_BFIN_SPI
+/* For the M25P64 SCK Should be Kept < 15Mhz */
+#define CONFIG_ENV_SPI_MAX_HZ	15000000
+#define CONFIG_SF_DEFAULT_SPEED	15000000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+
+/*
+ * FLASH organization and environment definitions
+ */
+
+#define CONFIG_EBIU_AMGCTL_VAL		0xFF
+#define CONFIG_EBIU_AMBCTL0_VAL		0xBBC3BBC3
+#define CONFIG_EBIU_AMBCTL1_VAL		0x99B39983
+#define CONFIG_EBIU_SDRRC_VAL		0x268
+#define CONFIG_EBIU_SDGCTL_VAL		0x911109
+
+/* Even though Rev C boards have Parallel Flash
+ * We aren't supporting it. Newer versions of the
+ * hardware don't support Parallel Flash at all.
+ */
+#define CONFIG_SYS_NO_FLASH
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_JFFS2
+#undef CONFIG_CMD_FLASH
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/blackvme.h b/qemu/roms/u-boot/include/configs/blackvme.h
new file mode 100644
index 000000000..6e5774c6b
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/blackvme.h
@@ -0,0 +1,244 @@
+/* U-boot for BlackVME. (C) Wojtek Skulski 2010.
+ * The board includes ADSP-BF561 rev. 0.5,
+ * 32-bit SDRAM (2 * MT48LC16M16A2TG or MT48LC32M16A2TG),
+ * Gigabit Ether AX88180 (ASIX) + 88E1111 rev. B2 (Marvell),
+ * SPI  boot flash on PF2 (M25P64 8MB, or M25P128 16 MB),
+ * FPGA boot flash on PF3 (M25P64 8MB, or M25P128 16 MB),
+ * Spartan6-LX150 (memory-mapped; both PPIs also connected).
+ * See http://www.skutek.com
+ */
+
+#ifndef __CONFIG_BLACKVME_H__
+#define __CONFIG_BLACKVME_H__
+
+#include <asm/config-pre.h>
+
+/* Debugging: Set these options if you're having problems
+ * #define CONFIG_DEBUG_EARLY_SERIAL
+ * #define DEBUG
+ * #define CONFIG_DEBUG_DUMP
+ * #define CONFIG_DEBUG_DUMP_SYMS
+ * CONFIG_PANIC_HANG means that the board will not auto-reboot
+ */
+#define CONFIG_PANIC_HANG 0
+
+/* CPU Options */
+#define CONFIG_BFIN_CPU        bf561-0.5
+#define CONFIG_BFIN_BOOT_MODE  BFIN_BOOT_SPI_MASTER
+
+/*
+ *		CLOCK SETTINGS CAVEAT
+ * You CANNOT just change the clock settings, esp. the SCLK.
+ * The SDRAM timing, SPI baud, and the serial UART baud
+ * use SCLK frequency to set their own frequencies. Therefore,
+ * if you change the SCLK_DIV, you may also have to adjust
+ * SDRAM refresh and other timings.
+ * --------------------------------------------------------------
+ *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ *		25 *  8 / 1 = 200 MHz
+ *		25 * 16 / 1 = 400 MHz
+ *		25 * 24 / 1 = 600 MHz
+ *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ *		25 *  8 / 2 = 100 MHz
+ *		25 * 24 / 6 = 100 MHz
+ *		25 * 24 / 5 = 120 MHz
+ *		25 * 16 / 3 = 133 MHz
+ * 25 MHz because the oscillator also feeds the ether chip.
+ * CONFIG_CLKIN_HZ is 25 MHz written in Hz
+ * CLKIN_HALF controls the DF bit in PLL_CTL
+ *	0 = CLKIN	1 = CLKIN / 2
+ * PLL_BYPASS controls the BYPASS bit in PLL_CTL
+ *	0 = do not bypass	1 = bypass PLL
+ * VCO_MULT = MSEL (multiplier) in PLL_CTL
+ * Values can range from 0-63 (where 0 means 64)
+ * CCLK_DIV = core clock divider (1, 2, 4, or 8 ONLY)
+ * SCLK_DIV = system clock divider, 1 to 15
+ */
+#define CONFIG_CLKIN_HZ		25000000
+#define CONFIG_CLKIN_HALF	0
+#define CONFIG_PLL_BYPASS	0
+#define CONFIG_VCO_MULT		8
+#define CONFIG_CCLK_DIV		1
+#define CONFIG_SCLK_DIV		2
+
+/*
+ * Ether chip in async memory space AMS3, same as BF561-EZ-KIT.
+ * Used in 32-bit mode. 16-bit mode not supported.
+ * http://docs.blackfin.uclinux.org/doku.php?id=hw:cards:ax88180
+ */
+/*
+ * Network settings using a dedicated 2nd ether card in PC
+ * Windows will automatically acquire IP of that card
+ * Then use the dedicated card IP + 1 for the board
+ * http://docs.blackfin.uclinux.org/doku.php?id=setting_up_the_network
+ */
+#define CONFIG_DRIVER_AX88180	1
+#define AX88180_BASE		0x2c000000
+#define CONFIG_CMD_MII		/* enable probing PHY */
+
+#define CONFIG_HOSTNAME	blackvme	/* Bfin board  */
+#define CONFIG_IPADDR		169.254.144.145	/* Bfin board  */
+#define CONFIG_GATEWAYIP	169.254.144.144	/* dedic card  */
+#define CONFIG_SERVERIP	169.254.144.144	/* tftp server */
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_ROOTPATH		"/export/uClinux-dist/romfs"	/*NFS*/
+#define CFG_AUTOLOAD		"no"
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_ENV_OVERWRITE	1	/* enable changing MAC at runtime */
+/* Comment out hardcoded MAC to enable MAC storage in EEPROM */
+/* # define CONFIG_ETHADDR	ff:ee:dd:cc:bb:aa */
+
+/*
+ * SDRAM settings & memory map
+ */
+
+#define CONFIG_MEM_SIZE		64	/* 128, 64, 32, 16 */
+#define CONFIG_MEM_ADD_WDTH	 9	/* 8, 9, 10, 11    */
+/*
+ * SDRAM reference page
+ * http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
+ * NOTE: BlackVME populates only SDRAM bank 0
+ */
+/* CONFIG_EBIU_SDBCTL_VAL bank ctrl may be needed in future */
+#define CONFIG_EBIU_SDGCTL_VAL  0x91114d  /* global control */
+#define CONFIG_EBIU_SDRRC_VAL   0x306     /* refresh rate */
+
+/* Async memory global settings. (ASRAM, not SDRAM)
+ * HRM page 16-10. Global ASRAM control = 0x3F. Six lower bits = 1
+ * CLKOUT enabled, all async banks enabled, core has priority
+ * bank 0&1 16 bit (FPGA)
+ * bank 2&3 32 bit (ether and USB chips)
+ */
+#define CONFIG_EBIU_AMGCTL_VAL  0x3F   /* ASRAM setup */
+
+/* Async mem timing: BF561 HRM page 16-12 and 16-15.
+ * Default values 0xFFC2 FFC2 are the slowest supported.
+ * Example settings of CONFIG_EBIU_AMBCTL1_VAL
+ * 1. EZ-KIT settings: 0xFFC2 7BB0
+ * 2. Bank 3 good timing for AX88180 @ 125MHz = 0x8850 xxxx
+ *    See the following page:
+ *    http://docs.blackfin.uclinux.org/doku.php?id=hw:cards:ax88180
+ * 3. Bank 3 timing for AX88180 @ SCLK = 100 MHz:
+ * AX88180  WEN = 5 clocks  REN 6 clocks @ SCLK = 100 MHz
+ * One extra clock needed because AX88180 is asynchronous to CPU.
+ */
+			   /* bank 1   0 */
+#define CONFIG_EBIU_AMBCTL0_VAL 0xFFC2FFC2
+			   /* bank 3   2 */
+#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC2FFC2
+
+/* memory layout */
+
+#define CONFIG_SYS_MONITOR_LEN	(256 << 10)
+#define CONFIG_SYS_MALLOC_LEN	(384 << 10)
+
+/*
+ * Serial SPI Flash
+ * For the M25P64 SCK should be kept < 15 MHz
+ */
+#define CONFIG_BFIN_SPI
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET	0x40000
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x40000
+
+#define CONFIG_ENV_SPI_MAX_HZ	15000000
+#define CONFIG_SF_DEFAULT_SPEED	15000000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+
+/*
+ * Interactive command settings
+ */
+
+#define CONFIG_SYS_LONGHELP	1
+#define CONFIG_CMDLINE_EDITING	1
+#define CONFIG_AUTO_COMPLETE	1
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BOOTLDR
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_CPLBINFO
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_ELF
+
+/*
+ * Default: boot from SPI flash.
+ * "sfboot" is a composite command defined in extra settings
+ */
+#define CONFIG_BOOTDELAY	5
+#define CONFIG_BOOTCOMMAND	"run sfboot"
+
+/*
+ * Console settings
+ */
+#define CONFIG_BAUDRATE		57600
+#define CONFIG_LOADS_ECHO	1
+#define CONFIG_UART_CONSOLE	0
+#define CONFIG_BFIN_SERIAL
+
+/*
+ * U-Boot environment variables. Use "printenv" to examine.
+ * http://docs.blackfin.uclinux.org/doku.php?id=bootloaders:u-boot:env
+ */
+#define CONFIG_BOOTARGS \
+	"root=/dev/mtdblock0 rw " \
+	"clkin_hz=" __stringify(CONFIG_CLKIN_HZ) " " \
+	"earlyprintk=serial,uart0," \
+	__stringify(CONFIG_BAUDRATE) " " \
+	"console=ttyBF0," __stringify(CONFIG_BAUDRATE) " "
+
+/* Convenience env variables & commands.
+ * Reserve kernstart = 0x20000  = 128 kB for U-Boot.
+ * Reserve kernarea  = 0x500000 = 5 MB   for kernel (reasonable size).
+ * U-Boot image is saved at flash offset=0.
+ * Kernel image is saved at flash offset=$kernstart.
+ * Instructions. Ksave takes about a minute to complete.
+ *	1. Update U-Boot: run uget; run usave
+ *	2. Update kernel: run kget; run ksave
+ * After updating U-Boot also update the kernel per above instructions
+ * to make the saved environment consistent with the flash.
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"kernstart=0x20000\0" \
+	"kernarea=0x500000\0" \
+	"uget=tftp u-boot.ldr\0" \
+	"kget=tftp uImage\0" \
+	"usave=sf probe 2; " \
+		"sf erase 0 $(kernstart); " \
+		"sf write $(fileaddr) 0 $(filesize)\0" \
+	"ksave=sf probe 2; " \
+		"saveenv; " \
+		"echo Now patiently wait for the prompt...; " \
+		"sf erase $(kernstart) $(kernarea); " \
+		"sf write $(fileaddr) $(kernstart) $(filesize)\0" \
+	"sfboot=sf probe 2; " \
+		"sf read $(loadaddr) $(kernstart) $(filesize); " \
+		"run addip; bootm\0" \
+	"addip=setenv bootargs $(bootargs) " \
+	"ip=$(ipaddr):$(serverip):$(gatewayip):" \
+		"$(netmask):$(hostname):eth0:off\0"
+
+/*
+ * Soft I2C settings (BF561 does not have hard I2C)
+ * PF12,13 on SPI connector 0.
+ */
+#ifdef CONFIG_SYS_I2C_SOFT
+# define CONFIG_CMD_I2C
+# define CONFIG_SOFT_I2C_GPIO_SCL	GPIO_PF12
+# define CONFIG_SOFT_I2C_GPIO_SDA	GPIO_PF13
+# define CONFIG_SYS_I2C_SPEED		50000
+# define CONFIG_SYS_I2C_SLAVE		0xFE
+#endif
+
+/*
+ * No Parallel Flash on this board
+ */
+#define CONFIG_SYS_NO_FLASH
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_JFFS2
+#undef CONFIG_CMD_FLASH
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/bluestone.h b/qemu/roms/u-boot/include/configs/bluestone.h
new file mode 100644
index 000000000..8bd71c6a1
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/bluestone.h
@@ -0,0 +1,168 @@
+/*
+ * bluestone.h - configuration for Bluestone (APM821XX)
+ *
+ * Copyright (c) 2010, Applied Micro Circuits Corporation
+ * Author: Tirumala R Marri <tmarri@apm.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_APM821XX		1	/* APM821XX series    */
+#define CONFIG_HOSTNAME		bluestone
+
+#define CONFIG_440		1
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xFFFA0000
+#endif
+
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#include "amcc-common.h"
+#define CONFIG_SYS_CLK_FREQ	50000000
+
+#define CONFIG_BOARD_TYPES		1	/* support board types */
+#define CONFIG_BOARD_EARLY_INIT_F	1       /* Call board_early_init_f */
+#define CONFIG_MISC_INIT_R		1       /* Call misc_init_r */
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+/* EBC stuff */
+/* later mapped to this addr */
+#define CONFIG_SYS_FLASH_BASE		0xFFF00000
+#define CONFIG_SYS_FLASH_SIZE		(4 << 20)	/* 1MB usable */
+
+/* EBC Boot Space: 0xFF000000 */
+#define CONFIG_SYS_BOOT_BASE_ADDR	0xFF000000
+#define CONFIG_SYS_OCM_BASE		0xE3000000 /* OCM: 32k             */
+#define CONFIG_SYS_SRAM_BASE		0xE8000000 /* SRAM: 256k           */
+#define CONFIG_SYS_AHB_BASE		0xE2000000 /* internal AHB peripherals*/
+
+#define CONFIG_SYS_SRAM_SIZE            (256 << 10)
+/*
+ * Initial RAM & stack pointer (placed in OCM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_BASE	/* OCM    */
+#define CONFIG_SYS_INIT_RAM_SIZE		(4 << 10)
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * Environment
+ */
+/*
+ * Define here the location of the environment variables (FLASH).
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars */
+
+/*
+ * FLASH related
+ */
+#define CONFIG_SYS_FLASH_CFI	/* The flash is CFI compatible  */
+#define CONFIG_FLASH_CFI_DRIVER	/* Use common CFI driver        */
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE}
+/* max number of memory banks           */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+/* max number of sectors on one chip    */
+#define CONFIG_SYS_MAX_FLASH_SECT	80
+/* Timeout for Flash Erase (in ms)      */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000
+/* Timeout for Flash Write (in ms)      */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500
+/* use buffered writes (20x faster)     */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	0x10000	/* size of one complete sector  */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector   */
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+#endif /* CONFIG_ENV_IS_IN_FLASH */
+
+/* SDRAM */
+#define CONFIG_SPD_EEPROM	1       /* Use SPD EEPROM for setup     */
+#define SPD_EEPROM_ADDRESS	{0x53, 0x51}	/* SPD i2c spd addresses */
+#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION       /* IBM DDR autocalibration */
+#define CONFIG_AUTOCALIB	"silent\0"	/* default is non-verbose    */
+#define CONFIG_DDR_ECC		1	/* with ECC support             */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x54
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5	/* Data sheet */
+
+/* I2C bootstrap EEPROM */
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR	0x52
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET	0
+#define CONFIG_4xx_CONFIG_BLOCKSIZE		16
+
+/*
+ * Ethernet
+ */
+#define CONFIG_IBM_EMAC4_V4	1
+#define CONFIG_EMAC_PHY_MODE	EMAC_PHY_MODE_NONE_RGMII
+#define CONFIG_HAS_ETH0
+/* PHY address, See schematics  */
+#define CONFIG_PHY_ADDR			0x1f
+/* reset phy upon startup       */
+#define CONFIG_PHY_RESET		1
+/* Include GbE speed/duplex detection */
+#define CONFIG_PHY_GIGE			1
+#define CONFIG_PHY_DYNAMIC_ANEG		1
+
+/*
+ * External Bus Controller (EBC) Setup
+ **/
+#define CONFIG_SYS_EBC_CFG	(EBC_CFG_LE_LOCK    |	\
+				 EBC_CFG_PTD_ENABLE   |	\
+				 EBC_CFG_RTC_2048PERCLK | \
+				 EBC_CFG_ATC_HI | \
+				 EBC_CFG_DTC_HI | \
+				 EBC_CFG_CTC_HI | \
+				 EBC_CFG_OEO_PREVIOUS)
+/* NOR Flash */
+#define CONFIG_SYS_EBC_PB0AP 	(EBC_BXAP_BME_DISABLED   | \
+				EBC_BXAP_TWT_ENCODE(64)  | \
+				EBC_BXAP_BCE_DISABLE    | \
+				EBC_BXAP_BCT_2TRANS     | \
+				EBC_BXAP_CSN_ENCODE(1)  | \
+				EBC_BXAP_OEN_ENCODE(2)  | \
+				EBC_BXAP_WBN_ENCODE(2)  | \
+				EBC_BXAP_WBF_ENCODE(2)  | \
+				EBC_BXAP_TH_ENCODE(7)   | \
+				EBC_BXAP_SOR_DELAYED    | \
+				EBC_BXAP_BEM_WRITEONLY  | \
+				EBC_BXAP_PEN_DISABLED)
+/* Peripheral Bank Configuration Register - EBC_BxCR */
+#define CONFIG_SYS_EBC_PB0CR	\
+			(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
+			EBC_BXCR_BS_1MB                | \
+			EBC_BXCR_BU_RW                  | \
+			EBC_BXCR_BW_8BIT)
+
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/br4.h b/qemu/roms/u-boot/include/configs/br4.h
new file mode 100644
index 000000000..f8d3158d4
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/br4.h
@@ -0,0 +1,157 @@
+/*
+ * U-boot - Configuration file for BR4 Appliance
+ *
+ * based on bf537-stamp.h
+ * Copyright (c) Switchfin Org. <dpn@switchfin.org>
+ */
+
+#ifndef __CONFIG_BR4_H__
+#define __CONFIG_BR4_H__
+
+#include <asm/config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU             bf537-0.3
+#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_SPI_MASTER
+
+
+/*
+ * Clock Settings
+ *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz					*/
+#define CONFIG_CLKIN_HZ			25000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
+/*                                                1 = CLKIN / 2		*/
+#define CONFIG_CLKIN_HALF		0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
+/*                                                1 = bypass PLL	*/
+#define CONFIG_PLL_BYPASS		0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
+/* Values can range from 0-63 (where 0 means 64)			*/
+#define CONFIG_VCO_MULT			24
+/* CCLK_DIV controls the core clock divider				*/
+/* Values can be 1, 2, 4, or 8 ONLY					*/
+#define CONFIG_CCLK_DIV			1
+/* SCLK_DIV controls the system clock divider				*/
+/* Values can range from 1-15						*/
+#define CONFIG_SCLK_DIV			5
+
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_ADD_WDTH	10
+#define CONFIG_MEM_SIZE		64
+
+#define CONFIG_EBIU_SDRRC_VAL	0x306
+#define CONFIG_EBIU_SDGCTL_VAL	0x8091998d
+
+#define CONFIG_EBIU_AMGCTL_VAL	0xFF
+#define CONFIG_EBIU_AMBCTL0_VAL	0x7BB07BB0
+#define CONFIG_EBIU_AMBCTL1_VAL	0xFFC27BB0
+
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(384 * 1024)
+
+
+/*
+ * Network Settings
+ */
+#ifndef __ADSPBF534__
+#define ADI_CMDS_NETWORK	1
+#define CONFIG_BFIN_MAC
+#define CONFIG_NETCONSOLE
+#endif
+#define CONFIG_HOSTNAME		br4
+#define CONFIG_TFTP_BLOCKSIZE	4404
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR	5c:38:1a:80:a7:00 */
+
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_SYS_NO_FLASH	/* We have no parallel FLASH */
+
+
+/*
+ * SPI Settings
+ */
+#define CONFIG_BFIN_SPI
+#define CONFIG_ENV_SPI_MAX_HZ	30000000
+#define CONFIG_SF_DEFAULT_SPEED	30000000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+
+
+/*
+ * Env Storage Settings
+ */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET	0x10000
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
+
+
+/*
+ * I2C Settings
+ */
+#define CONFIG_BFIN_TWI_I2C
+#define CONFIG_HARD_I2C
+
+
+/*
+ * NAND Settings
+ */
+#define CONFIG_NAND_PLAT
+#define CONFIG_SYS_NAND_BASE		0x20000000
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+
+#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
+#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
+#define BFIN_NAND_WRITE(addr, cmd) \
+	do { \
+		bfin_write8(addr, cmd); \
+		SSYNC(); \
+	} while (0)
+
+#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
+#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
+#define NAND_PLAT_GPIO_DEV_READY       GPIO_PF9
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_RTC_BFIN
+#define CONFIG_UART_CONSOLE	0
+#define CONFIG_SYS_PROMPT	"br4>"
+#define CONFIG_BOOTCOMMAND	"run nandboot"
+#define CONFIG_BOOTDELAY	2
+#define CONFIG_LOADADDR		0x2000000
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+/*
+ * Overwrite some settings defined in bfin_adi_common.h
+ */
+#undef NAND_ENV_SETTINGS
+#define NAND_ENV_SETTINGS \
+	"nandargs=set bootargs " CONFIG_BOOTARGS "\0" \
+	"nandboot=" \
+		"nand read $(loadaddr) 0x0 0x900000;" \
+		"run nandargs;" \
+		"bootm" \
+		"\0"
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/bubinga.h b/qemu/roms/u-boot/include/configs/bubinga.h
new file mode 100644
index 000000000..ea7b10472
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/bubinga.h
@@ -0,0 +1,305 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_BUBINGA	        1	/* ...on a BUBINGA board	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
+
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME		bubinga
+#include "amcc-common.h"
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
+
+#define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
+
+#define CONFIG_NO_SERIAL_EEPROM
+/*#undef CONFIG_NO_SERIAL_EEPROM*/
+/*----------------------------------------------------------------------------*/
+#ifdef CONFIG_NO_SERIAL_EEPROM
+
+/*
+!-------------------------------------------------------------------------------
+! Defines for entry options.
+! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
+!       are plugged in the board will be utilized as non-ECC DIMMs.
+!-------------------------------------------------------------------------------
+*/
+#define        AUTO_MEMORY_CONFIG
+#define        DIMM_READ_ADDR 0xAB
+#define        DIMM_WRITE_ADDR 0xAA
+
+/*
+!-------------------------------------------------------------------------------
+! PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
+! assuming a 33MHz input clock to the 405EP from the C9531.
+!-------------------------------------------------------------------------------
+*/
+#define PLLMR0_DEFAULT   PLLMR0_266_133_66
+#define PLLMR1_DEFAULT   PLLMR1_266_133_66
+
+#endif
+/*----------------------------------------------------------------------------*/
+
+/*
+ * Define here the location of the environment variables (FLASH or NVRAM).
+ * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
+ *       supported for backward compatibility.
+ */
+#if 1
+#define CONFIG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
+#else
+#define CONFIG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
+#endif
+
+/*
+ * Default environment variables
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_AMCC_DEF_ENV						\
+	CONFIG_AMCC_DEF_ENV_PPC						\
+	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
+	"kernel_addr=fff80000\0"					\
+	"ramdisk_addr=fff90000\0"					\
+	""
+
+#define	CONFIG_PHY_ADDR		1	/* PHY address			*/
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_PHY1_ADDR	2	/* EMAC1 PHY address		*/
+
+#define CONFIG_RTC_DS174x	1	/* use DS1743 RTC in Bubinga	*/
+
+/*
+ * Commands additional to the ones defined in amcc-common.h
+ */
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
+
+#define CONFIG_SPD_EEPROM      1       /* use SPD EEPROM for setup    */
+
+/*
+ * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
+ * The Linux BASE_BAUD define should match this configuration.
+ *    baseBaud = cpuClock/(uartDivisor*16)
+ * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * set Linux BASE_BAUD to 403200.
+ */
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#undef  CONFIG_SYS_EXT_SERIAL_CLOCK           /* external serial clock */
+#undef  CONFIG_SYS_405_UART_ERRATA_59         /* 405GP/CR Rev. D silicon */
+#define CONFIG_SYS_BASE_BAUD       691200
+
+/*-----------------------------------------------------------------------
+ * I2C stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
+
+#define CONFIG_SYS_I2C_NOPROBES	{ {0, 0x69} }	/* avoid i2c probe hangup (?) */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	6	/* 24C02 requires 5ms delay */
+
+#if defined(CONFIG_CMD_EEPROM)
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* I2C boot EEPROM (24C02W)	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
+#define PCI_HOST_FORCE  1               /* configure as pci host        */
+#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_HOST	PCI_HOST_FORCE  /* select pci host function     */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
+					/* resource configuration       */
+#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
+#define CONFIG_SYS_PCI_CLASSCODE       0x0600  /* PCI Class Code: bridge/host  */
+#define CONFIG_SYS_PCI_PTM1LA  0x00000000      /* point to sdram               */
+#define CONFIG_SYS_PCI_PTM1MS  0x80000001      /* 2GB, enable hard-wired to 1  */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CONFIG_SYS_PCI_PTM2LA  0x00000000      /* disabled                     */
+#define CONFIG_SYS_PCI_PTM2MS  0x00000000      /* disabled                     */
+#define CONFIG_SYS_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+
+/*-----------------------------------------------------------------------
+ * External peripheral base address
+ *-----------------------------------------------------------------------
+ */
+#define	CONFIG_SYS_KEY_REG_BASE_ADDR	0xF0100000
+#define	CONFIG_SYS_IR_REG_BASE_ADDR	0xF0200000
+#define	CONFIG_SYS_FPGA_REG_BASE_ADDR	0xF0300000
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ */
+#define CONFIG_SYS_SRAM_BASE		0xFFF00000
+#define CONFIG_SYS_SRAM_SIZE		(256 << 10)
+#define CONFIG_SYS_FLASH_BASE		0xFFF80000
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CONFIG_SYS_FLASH_ADDR0         0x5555
+#define CONFIG_SYS_FLASH_ADDR1         0x2aaa
+#define CONFIG_SYS_FLASH_WORD_SIZE     unsigned char
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	0x10000	/* size of one complete sector	*/
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
+#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+#endif /* CONFIG_ENV_IS_IN_FLASH */
+
+/*-----------------------------------------------------------------------
+ * NVRAM organization
+ */
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xf0000000	/* NVRAM base address	*/
+#define CONFIG_SYS_NVRAM_SIZE		0x1ff8		/* NVRAM size	*/
+
+#ifdef CONFIG_ENV_IS_IN_NVRAM
+#define CONFIG_ENV_SIZE		0x0ff8		/* Size of Environment vars	*/
+#define CONFIG_ENV_ADDR		\
+	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE)	/* Env	*/
+#endif
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	CONFIG_SYS_FLASH_BASE	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0		/* FLASH bank #1	*/
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CONFIG_SYS_TEMP_STACK_OCM        1
+
+/* On Chip Memory location */
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
+
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash/SRAM) initialization                                    */
+#define CONFIG_SYS_EBC_PB0AP           0x04006000
+#define CONFIG_SYS_EBC_PB0CR           0xFFF18000  /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit  */
+
+/* Memory Bank 1 (NVRAM/RTC) initialization                                     */
+#define CONFIG_SYS_EBC_PB1AP           0x04041000
+#define CONFIG_SYS_EBC_PB1CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
+
+/* Memory Bank 2 (not used) initialization                                      */
+#define CONFIG_SYS_EBC_PB2AP           0x00000000
+#define CONFIG_SYS_EBC_PB2CR           0x00000000
+
+/* Memory Bank 2 (not used) initialization                                      */
+#define CONFIG_SYS_EBC_PB3AP           0x00000000
+#define CONFIG_SYS_EBC_PB3CR           0x00000000
+
+/* Memory Bank 4 (FPGA regs) initialization                                     */
+#define CONFIG_SYS_EBC_PB4AP           0x01815000
+#define CONFIG_SYS_EBC_PB4CR           0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit  */
+
+/*-----------------------------------------------------------------------
+ * Definitions for Serial Presence Detect EEPROM address
+ * (to get SDRAM settings)
+ */
+#define SPD_EEPROM_ADDRESS      0x55
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO setup (PPC405EP specific)
+ *
+ * GPIO0[0]     - External Bus Controller BLAST output
+ * GPIO0[1-9]   - Instruction trace outputs
+ * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
+ * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
+ * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
+ * GPIO0[24-27] - UART0 control signal inputs/outputs
+ * GPIO0[28-29] - UART1 data signal input/output
+ * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
+ */
+#define CONFIG_SYS_GPIO0_OSRL          0x55555555
+#define CONFIG_SYS_GPIO0_OSRH          0x40000110
+#define CONFIG_SYS_GPIO0_ISR1L         0x00000000
+#define CONFIG_SYS_GPIO0_ISR1H         0x15555445
+#define CONFIG_SYS_GPIO0_TSRL          0x00000000
+#define CONFIG_SYS_GPIO0_TSRH          0x00000000
+#define CONFIG_SYS_GPIO0_TCR           0xFFFF8014
+
+/*-----------------------------------------------------------------------
+ * Some BUBINGA stuff...
+ */
+#define NVRAM_BASE      0xF0000000
+#define FPGA_REG0       0xF0300000    /* FPGA Reg 0              */
+#define FPGA_REG1       0xF0300001    /* FPGA Reg 1              */
+#define NVRVFY1     0x4f532d4f    /* used to determine if state data in */
+#define NVRVFY2     0x50454e00    /* NVRAM initialized (ascii for OS-OPEN)*/
+
+#define FPGA_REG0_F_RANGE     0x80       /* SDRAM PLL freq range              */
+#define FPGA_REG0_EXT_INT_DIS 0x20       /* External interface disable        */
+#define FPGA_REG0_LED_MASK    0x07       /* Board LEDs DS9, DS10, and DS11    */
+#define FPGA_REG0_LED0        0x04       /* Turn on LED0                      */
+#define FPGA_REG0_LED1        0x02       /* Turn on LED1                      */
+#define FPGA_REG0_LED2        0x01       /* Turn on LED2                      */
+
+#define FPGA_REG1_SSPEC_DIS   0x80       /* C9531 Spread Spectrum disabled    */
+#define FPGA_REG1_OFFBD_PCICLK 0x40      /* Onboard PCI clock selected       */
+#define FPGA_REG1_CLOCK_MASK  0x30       /* Mask for C9531 output freq select */
+#define FPGA_REG1_CLOCK_BIT_SHIFT  4
+#define FPGA_REG1_PCI_INT_ARB 0x08       /* PCI Internal arbiter selected     */
+#define FPGA_REG1_PCI_FREQ    0x04       /* PCI Frequency select              */
+#define FPGA_REG1_OFFB_FLASH  0x02       /* Off board flash                   */
+#define FPGA_REG1_SRAM_BOOT   0x01       /* SRAM at 0xFFF80000 not Flash      */
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/bur_am335x_common.h b/qemu/roms/u-boot/include/configs/bur_am335x_common.h
new file mode 100644
index 000000000..7adc8c0fd
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/bur_am335x_common.h
@@ -0,0 +1,196 @@
+/*
+ * bur_am335x_common.h
+ *
+ * common parts used by B&R AM335x based boards
+ *
+ * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at> -
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ * SPDX-License-Identifier:        GPL-2.0+
+ */
+
+#ifndef __BUR_AM335X_COMMON_H__
+#define __BUR_AM335X_COMMON_H__
+/* ------------------------------------------------------------------------- */
+#define CONFIG_AM33XX
+#define CONFIG_OMAP
+#define CONFIG_OMAP_COMMON
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_SYS_CACHELINE_SIZE	64
+#define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 20)	/* 1GB */
+
+/* Timer information */
+#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
+#define CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC	/* enable 32kHz OSC at bootime */
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_POWER_TPS65217
+
+#define CONFIG_SYS_NO_FLASH		/* have no NOR-flash */
+
+#include <asm/arch/omap.h>
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		48000000
+#define CONFIG_SYS_NS16550_COM1		0x44e09000	/* UART0 */
+#define CONFIG_BAUDRATE			115200
+
+/* Network defines */
+#define CONFIG_CMD_NET			/* 'bootp' and 'tftp' */
+#define CONFIG_CMD_DHCP
+#define CONFIG_BOOTP_DNS		/* Configurable parts of CMD_DHCP */
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_NET_RETRY_COUNT		4
+#define CONFIG_CMD_PING
+#define CONFIG_DRIVER_TI_CPSW		/* Driver for IP block */
+#define CONFIG_MII			/* Required in net/eth.c */
+#define CONFIG_SPL_ETH_SUPPORT
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_NATSEMI
+#define CONFIG_SPL_NET_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT		/* used for a fetching MAC-Address */
+#define CONFIG_SPL_NET_VCI_STRING	"AM335x U-Boot SPL"
+
+/*
+ * SPL related defines.  The Public RAM memory map the ROM defines the
+ * area between 0x402F0400 and 0x4030B800 as a download area and
+ * 0x4030B800 to 0x4030CE00 as a public stack area.  The ROM also
+ * supports X-MODEM loading via UART, and we leverage this and then use
+ * Y-MODEM to load u-boot.img, when booted over UART.
+ */
+#define CONFIG_SPL_TEXT_BASE		0x402F0400
+#define CONFIG_SPL_MAX_SIZE		(0x4030B800 - CONFIG_SPL_TEXT_BASE)
+
+/*
+ * Since SPL did pll and ddr initialization for us,
+ * we don't need to do it twice.
+ */
+#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif /* !CONFIG_SPL_BUILD, ... */
+/*
+ * Our DDR memory always starts at 0x80000000 and U-Boot shall have
+ * relocated itself to higher in memory by the time this value is used.
+ */
+#define CONFIG_SYS_LOAD_ADDR		0x80000000
+/*
+ * ----------------------------------------------------------------------------
+ * DDR information.  We say (for simplicity) that we have 1 bank,
+ * always, even when we have more.  We always start at 0x80000000,
+ * and we place the initial stack pointer in our SRAM.
+ */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CONFIG_SYS_INIT_SP_ADDR		(NON_SECURE_SRAM_END - \
+					GENERATED_GBL_DATA_SIZE)
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
+#define CONFIG_SYS_I2C_OMAP24XX
+
+/* GPIO */
+#define CONFIG_OMAP_GPIO
+#define CONFIG_CMD_GPIO
+/*
+ * ----------------------------------------------------------------------------
+ * The following are general good-enough settings for U-Boot.  We set a
+ * large malloc pool as we generally have a lot of DDR, and we opt for
+ * function over binary size in the main portion of U-Boot as this is
+ * generally easily constrained later if needed.  We enable the config
+ * options that give us information in the environment about what board
+ * we are on so we do not need to rely on the command prompt.  We set a
+ * console baudrate of 115200 and use the default baud rate table.
+ */
+#define CONFIG_SYS_MALLOC_LEN		(1024 << 10)
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT		"U-Boot (BuR V2.0)# "
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+#define CONFIG_ENV_OVERWRITE		/* Overwrite ethaddr / serial# */
+
+/* As stated above, the following choices are optional. */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_VERSION_VARIABLE
+
+/* We set the max number of command args high to avoid HUSH bugs. */
+#define CONFIG_SYS_MAXARGS		64
+
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		512
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE +\
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+/*
+ * For commands to use, we take the default list and add a few other
+ * useful commands.  Note that we must have set CONFIG_SYS_NO_FLASH
+ * prior to this include, in order to skip a few commands.  When we do
+ * have flash, if we expect these commands they must be enabled in that
+ * config.  If desired, a specific list of desired commands can be used
+ * instead.
+ */
+#include <config_cmd_default.h>
+/* undefine commands, which we do not need */
+#undef CONFIG_CMD_EDITENV
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_ITEST
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
+#undef CONFIG_CMD_CRC32
+/* define command we need always */
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_SOURCE
+
+/*
+ * Our platforms make use of SPL to initalize the hardware (primarily
+ * memory) enough for full U-Boot to be loaded.  We also support Falcon
+ * Mode so that the Linux kernel can be booted directly from SPL
+ * instead, if desired.  We make use of the general SPL framework found
+ * under common/spl/.  Given our generally common memory map, we set a
+ * number of related defaults and sizes here.
+ */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+/*
+ * Place the image at the start of the ROM defined image space.
+ * We limit our size to the ROM-defined downloaded image area, and use the
+ * rest of the space for stack.  We load U-Boot itself into memory at
+ * 0x80800000 for legacy reasons (to not conflict with older SPLs).  We
+ * have our BSS be placed 1MiB after this, to allow for the default
+ * Linux kernel address of 0x80008000 to work, in the Falcon Mode case.
+ * We have the SPL malloc pool at the end of the BSS area.
+ *
+ * ----------------------------------------------------------------------------
+ */
+#define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
+#undef  CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE		0x80800000
+#define CONFIG_SPL_BSS_START_ADDR	0x80A00000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
+#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SPL_BSS_START_ADDR + \
+					CONFIG_SPL_BSS_MAX_SIZE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE	CONFIG_SYS_MALLOC_LEN
+
+/* General parts of the framework, required. */
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_YMODEM_SUPPORT
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/am33xx/u-boot-spl.lds"
+
+#endif	/* ! __BUR_AM335X_COMMON_H__ */
diff --git a/qemu/roms/u-boot/include/configs/calimain.h b/qemu/roms/u-boot/include/configs/calimain.h
new file mode 100644
index 000000000..febee45b3
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/calimain.h
@@ -0,0 +1,347 @@
+/*
+ * Copyright (C) 2011 OMICRON electronics GmbH
+ *
+ * Based on da850evm.h. Original Copyrights follow:
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Board
+ */
+#define CONFIG_DRIVER_TI_EMAC
+#define MACH_TYPE_CALIMAIN	3528
+#define CONFIG_MACH_TYPE	MACH_TYPE_CALIMAIN
+
+/*
+ * SoC Configuration
+ */
+#define CONFIG_MACH_DAVINCI_CALIMAIN
+#define CONFIG_ARM926EJS		/* arm926ejs CPU core */
+#define CONFIG_SOC_DA8XX		/* TI DA8xx SoC */
+#define CONFIG_SOC_DA850		/* TI DA850 SoC */
+#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
+#define CONFIG_SYS_CLK_FREQ		clk_get(DAVINCI_ARM_CLKID)
+#define CONFIG_SYS_OSCIN_FREQ		calimain_get_osc_freq()
+#define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
+#define CONFIG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
+#define CONFIG_SYS_TEXT_BASE		0x60000000
+#define CONFIG_DA850_LOWLEVEL
+#define CONFIG_SYS_DA850_PLL_INIT
+#define CONFIG_SYS_DA850_DDR_INIT
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DA8XX_GPIO
+#define CONFIG_HW_WATCHDOG
+#define CONFIG_SYS_WDTTIMERBASE	DAVINCI_TIMER1_BASE
+#define CONFIG_SYS_WDT_PERIOD_LOW \
+	(60 * CONFIG_SYS_OSCIN_FREQ) /* 60 s heartbeat */
+#define CONFIG_SYS_WDT_PERIOD_HIGH	0x0
+#define CONFIG_SYS_DV_NOR_BOOT_CFG	(0x11)
+
+/*
+ * PLL configuration
+ */
+#define CONFIG_SYS_DV_CLKMODE          0
+#define CONFIG_SYS_DA850_PLL0_POSTDIV  1
+#define CONFIG_SYS_DA850_PLL0_PLLDIV1  0x8000
+#define CONFIG_SYS_DA850_PLL0_PLLDIV2  0x8001
+#define CONFIG_SYS_DA850_PLL0_PLLDIV3  0x8002
+#define CONFIG_SYS_DA850_PLL0_PLLDIV4  0x8003
+#define CONFIG_SYS_DA850_PLL0_PLLDIV5  0x8002
+#define CONFIG_SYS_DA850_PLL0_PLLDIV6  CONFIG_SYS_DA850_PLL0_PLLDIV1
+#define CONFIG_SYS_DA850_PLL0_PLLDIV7  0x8005
+
+#define CONFIG_SYS_DA850_PLL1_POSTDIV  1
+#define CONFIG_SYS_DA850_PLL1_PLLDIV1  0x8000
+#define CONFIG_SYS_DA850_PLL1_PLLDIV2  0x8001
+#define CONFIG_SYS_DA850_PLL1_PLLDIV3  0x8002
+
+#define CONFIG_SYS_DA850_PLL0_PLLM \
+	((calimain_get_osc_freq() == 25000000) ? 23 : 24)
+#define CONFIG_SYS_DA850_PLL1_PLLM \
+	((calimain_get_osc_freq() == 25000000) ? 20 : 21)
+
+/*
+ * DDR2 memory configuration
+ */
+#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
+					DV_DDR_PHY_EXT_STRBEN | \
+					(0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
+
+#define CONFIG_SYS_DA850_DDR2_SDBCR (		\
+	(1 << DV_DDR_SDCR_DDR2EN_SHIFT) |	\
+	(1 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) |	\
+	(1 << DV_DDR_SDCR_DDREN_SHIFT) |	\
+	(1 << DV_DDR_SDCR_SDRAMEN_SHIFT) |	\
+	(1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) |	\
+	(0x3 << DV_DDR_SDCR_CL_SHIFT) |		\
+	(0x3 << DV_DDR_SDCR_IBANK_SHIFT) |	\
+	(0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
+
+/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
+#define CONFIG_SYS_DA850_DDR2_SDBCR2	0
+
+#define CONFIG_SYS_DA850_DDR2_SDTIMR (		\
+	(16 << DV_DDR_SDTMR1_RFC_SHIFT) |	\
+	(1 << DV_DDR_SDTMR1_RP_SHIFT) |		\
+	(1 << DV_DDR_SDTMR1_RCD_SHIFT) |	\
+	(1 << DV_DDR_SDTMR1_WR_SHIFT) |		\
+	(5 << DV_DDR_SDTMR1_RAS_SHIFT) |	\
+	(7 << DV_DDR_SDTMR1_RC_SHIFT) |		\
+	(1 << DV_DDR_SDTMR1_RRD_SHIFT) |	\
+	(1 << DV_DDR_SDTMR1_WTR_SHIFT))
+
+#define CONFIG_SYS_DA850_DDR2_SDTIMR2 (		\
+	(7 << DV_DDR_SDTMR2_RASMAX_SHIFT) |	\
+	(2 << DV_DDR_SDTMR2_XP_SHIFT) |		\
+	(0 << DV_DDR_SDTMR2_ODT_SHIFT) |	\
+	(18 << DV_DDR_SDTMR2_XSNR_SHIFT) |	\
+	(199 << DV_DDR_SDTMR2_XSRD_SHIFT) |	\
+	(0 << DV_DDR_SDTMR2_RTP_SHIFT) |	\
+	(2 << DV_DDR_SDTMR2_CKE_SHIFT))
+
+#define CONFIG_SYS_DA850_DDR2_SDRCR	0x000003FF
+#define CONFIG_SYS_DA850_DDR2_PBBPR	0x30
+
+/*
+ * Flash memory timing
+ */
+
+#define CONFIG_SYS_DA850_CS2CFG	(	\
+	DAVINCI_ABCR_WSETUP(2) |	\
+	DAVINCI_ABCR_WSTROBE(5)	|	\
+	DAVINCI_ABCR_WHOLD(3) |		\
+	DAVINCI_ABCR_RSETUP(1) |	\
+	DAVINCI_ABCR_RSTROBE(14) |	\
+	DAVINCI_ABCR_RHOLD(0) |		\
+	DAVINCI_ABCR_TA(3) |		\
+	DAVINCI_ABCR_ASIZE_16BIT)
+
+/* single 64 MB NOR flash device connected to CS2 and CS3 */
+#define CONFIG_SYS_DA850_CS3CFG CONFIG_SYS_DA850_CS2CFG
+
+/*
+ * Memory Info
+ */
+#define CONFIG_SYS_MALLOC_LEN	(0x10000 + 1*1024*1024) /* malloc() len */
+#define PHYS_SDRAM_1		DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
+#define PHYS_SDRAM_1_SIZE	(128 << 20) /* SDRAM size 128MB */
+#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
+
+#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (	\
+	DAVINCI_SYSCFG_SUSPSRC_TIMER0 |		\
+	DAVINCI_SYSCFG_SUSPSRC_SPI1 |		\
+	DAVINCI_SYSCFG_SUSPSRC_UART2 |		\
+	DAVINCI_SYSCFG_SUSPSRC_EMAC |		\
+	DAVINCI_SYSCFG_SUSPSRC_I2C)
+
+/* memtest start addr */
+#define CONFIG_SYS_MEMTEST_START	(PHYS_SDRAM_1 + 0x2000000)
+
+/* memtest will be run on 16MB */
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (16 << 20))
+
+#define CONFIG_NR_DRAM_BANKS	1 /* we have 1 bank of DRAM */
+
+/*
+ * Serial Driver info
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	-4	/* NS16550 register size */
+#define CONFIG_SYS_NS16550_COM1	DAVINCI_UART2_BASE /* Base address of UART2 */
+#define CONFIG_SYS_NS16550_CLK	clk_get(DAVINCI_UART2_CLKID)
+#define CONFIG_CONS_INDEX	1		/* use UART0 for console */
+#define CONFIG_BAUDRATE		115200		/* Default baud rate */
+
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_MAX_FLASH_BANKS  1 /* max number of flash banks */
+#define CONFIG_SYS_FLASH_SECT_SZ    (128 << 10) /* 128KB */
+#define CONFIG_SYS_FLASH_BASE       DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
+#define CONFIG_ENV_SECT_SIZE        CONFIG_SYS_FLASH_SECT_SZ
+#define CONFIG_ENV_ADDR \
+	(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SECT_SZ * 2)
+#define CONFIG_ENV_SIZE             (128 << 10)
+#define CONFIG_ENV_ADDR_REDUND      (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND      CONFIG_ENV_SIZE
+#define PHYS_FLASH_SIZE             (64 << 20) /* Flash size 64MB */
+#define CONFIG_SYS_MAX_FLASH_SECT \
+	((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ) + 3)
+
+/*
+ * Network & Ethernet Configuration
+ */
+#ifdef CONFIG_DRIVER_TI_EMAC
+#define CONFIG_EMAC_MDIO_PHY_NUM	1
+#define CONFIG_MII
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT	10
+#endif
+
+/*
+ * U-Boot general configuration
+ */
+#define CONFIG_BOOTFILE        "uImage" /* Boot file name */
+#define CONFIG_SYS_PROMPT      "Calimain > " /* Command Prompt */
+#define CONFIG_SYS_CBSIZE      1024 /* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE      (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS     16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE    CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
+#define CONFIG_SYS_LOAD_ADDR   (PHYS_SDRAM_1 + 0x700000)
+#define CONFIG_LOADADDR        0xc0700000
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+
+/*
+ * Linux Information
+ */
+#define LINUX_BOOT_PARAM_ADDR     (PHYS_SDRAM_1 + 0x100)
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTARGS           ""
+#define CONFIG_BOOTCOMMAND        "run checkupdate; run checkbutton;"
+#define CONFIG_BOOTDELAY          0
+#define CONFIG_ZERO_BOOTDELAY_CHECK   /* check for keypress on bootdelay==0 */
+#define CONFIG_BOOT_RETRY_TIME    60  /* continue boot after 60 s inactivity */
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_DELAY_STR "\x0d" /* press ENTER to interrupt BOOT */
+#define CONFIG_RESET_TO_RETRY
+
+/*
+ * Default environment settings
+ * gpio0 = button, gpio1 = led green, gpio2 = led red
+ * verify = n ... disable kernel checksum verification for faster booting
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"tftpdir=calimero\0"						\
+	"flashkernel=tftpboot $loadaddr $tftpdir/uImage; "		\
+		"erase 0x60800000 +0x400000; "				\
+		"cp.b $loadaddr 0x60800000 $filesize\0"			\
+	"flashrootfs="							\
+		"tftpboot $loadaddr $tftpdir/rootfs.jffs2; "		\
+		"erase 0x60c00000 +0x2e00000; "				\
+		"cp.b $loadaddr 0x60c00000 $filesize\0"			\
+	"flashuboot=tftpboot $loadaddr $tftpdir/u-boot.bin; "		\
+		"protect off all; "					\
+		"erase 0x60000000 +0x80000; "				\
+		"cp.b $loadaddr 0x60000000 $filesize\0"			\
+	"flashrlk=tftpboot $loadaddr $tftpdir/uImage-rlk; "		\
+		"erase 0x60080000 +0x780000; "				\
+		"cp.b $loadaddr 0x60080000 $filesize\0"			\
+	"erase_persistent=erase 0x63a00000 +0x600000;\0"		\
+	"bootnor=setenv bootargs console=ttyS2,115200n8 "		\
+		"root=/dev/mtdblock3 rw rootfstype=jffs2 "		\
+		"rootwait ethaddr=$ethaddr; "				\
+		"gpio c 1; gpio s 2; bootm 0x60800000\0"		\
+	"bootrlk=gpio s 1; gpio s 2;"					\
+		"setenv bootargs console=ttyS2,115200n8 "		\
+		"ethaddr=$ethaddr; bootm 0x60080000\0"			\
+	"boottftp=setenv bootargs console=ttyS2,115200n8 "		\
+		"root=/dev/mtdblock3 rw rootfstype=jffs2 "		\
+		"rootwait ethaddr=$ethaddr; "				\
+		"tftpboot $loadaddr $tftpdir/uImage;"			\
+		"gpio c 1; gpio s 2; bootm $loadaddr\0"			\
+	"checkupdate=if test -n $update_flag; then "			\
+		"echo Previous update failed - starting RLK; "		\
+		"run bootrlk; fi; "					\
+		"if test -n $initial_setup; then "			\
+		"echo Running initial setup procedure; "		\
+		"sleep 1; run flashall; fi\0"				\
+	"product=accessory\0"						\
+	"serial=XX12345\0"						\
+	"checknor="							\
+		"if gpio i 0; then run bootnor; fi;\0"			\
+	"checkrlk="							\
+		"if gpio i 0; then run bootrlk; fi;\0"			\
+	"checkbutton="							\
+		"run checknor; sleep 1;"				\
+		"run checknor; sleep 1;"				\
+		"run checknor; sleep 1;"				\
+		"run checknor; sleep 1;"				\
+		"run checknor;"						\
+		"gpio s 1; gpio s 2;"					\
+		"echo ---- Release button to boot RLK ----;"		\
+		"run checkrlk; sleep 1;"				\
+		"run checkrlk; sleep 1;"				\
+		"run checkrlk; sleep 1;"				\
+		"run checkrlk; sleep 1;"				\
+		"run checkrlk; sleep 1;"				\
+		"run checkrlk;"						\
+		"echo ---- Factory reset requested ----;"		\
+		"gpio c 1;"						\
+		"setenv factory_reset true;"				\
+		"saveenv;"						\
+		"run bootnor;\0"					\
+	"flashall=run flashrlk;"					\
+		"run flashkernel;"					\
+		"run flashrootfs;"					\
+		"setenv erase_datafs true;"				\
+		"setenv initial_setup;"					\
+		"saveenv;"						\
+		"run bootnor;\0"					\
+	"verify=n\0"							\
+	"clearenv=protect off all;"					\
+		"erase 0x60040000 +0x40000;\0"				\
+	"bootlimit=3\0"							\
+	"altbootcmd=run bootrlk\0"
+
+#define CONFIG_PREBOOT			\
+	"echo Version: $ver; "		\
+	"echo Serial: $serial; "	\
+	"echo MAC: $ethaddr; "		\
+	"echo Product: $product; "	\
+	"gpio c 1; gpio c 2;"
+
+/*
+ * U-Boot commands
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_GPIO
+
+#ifndef CONFIG_DRIVER_TI_EMAC
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_MII
+#undef CONFIG_CMD_PING
+#endif
+
+/* additions for new relocation code, must added to all boards */
+#define CONFIG_SYS_SDRAM_BASE		0xc0000000
+/* initial stack pointer in internal SRAM */
+#define CONFIG_SYS_INIT_SP_ADDR		(0x8001ff00)
+
+#define CONFIG_BOOTCOUNT_LIMIT
+#define CONFIG_SYS_BOOTCOUNT_LE		/* Use little-endian accessors */
+#define CONFIG_SYS_BOOTCOUNT_ADDR	DAVINCI_RTC_BASE
+
+#ifndef __ASSEMBLY__
+int calimain_get_osc_freq(void);
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/cam_enc_4xx.h b/qemu/roms/u-boot/include/configs/cam_enc_4xx.h
new file mode 100644
index 000000000..d1a8ff2a8
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/cam_enc_4xx.h
@@ -0,0 +1,514 @@
+/*
+ * Copyright (C) 2009 Texas Instruments Incorporated
+ *
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_NO_FLASH		/* that is, no *NOR* flash */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+
+/* SoC Configuration */
+#define CONFIG_ARM926EJS				/* arm926ejs CPU */
+#define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
+#define CONFIG_SYS_HZ_CLOCK		24000000	/* timer0 freq */
+#define CONFIG_SOC_DM365
+
+#define CONFIG_MACH_TYPE	MACH_TYPE_DAVINCI_DM365_EVM
+
+#define CONFIG_HOSTNAME			cam_enc_4xx
+
+#define	CONFIG_BOARD_LATE_INIT
+#define CONFIG_CAM_ENC_LED_MASK		0x0fc00000
+
+/* Memory Info */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM_1			0x80000000
+#define PHYS_SDRAM_1_SIZE		(256 << 20)	/* 256 MiB */
+#define DDR_4BANKS				/* 4-bank DDR2 (256MB) */
+#define CONFIG_MAX_RAM_BANK_SIZE	(256 << 20)	/* 256 MB */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+
+/* Serial Driver info: UART0 for console  */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#define CONFIG_SYS_NS16550_COM1		0x01c20000
+#define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_HZ_CLOCK
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+
+/* Network Configuration */
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_EMAC_MDIO_PHY_NUM	0
+#define	CONFIG_SYS_EMAC_TI_CLKDIV	0xa9	/* 1MHz */
+#define CONFIG_MII
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT	10
+#define CONFIG_CMD_MII
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_RESET_PHY_R
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DAVINCI
+#define CONFIG_SYS_DAVINCI_I2C_SPEED		400000
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE		0x10	/* SMBus host address */
+
+/* NAND: socketed, two chipselects, normally 2 GBytes */
+#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NAND_CS		2
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
+#define CONFIG_SYS_NAND_PAGE_2K
+
+#define CONFIG_SYS_NAND_LARGEPAGE
+#define CONFIG_SYS_NAND_BASE_LIST	{ 0x02000000, }
+/* socket has two chipselects, nCE0 gated by address BIT(14) */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+
+/* SPI support */
+#define CONFIG_SPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_DAVINCI_SPI
+#define CONFIG_SYS_SPI_BASE		DAVINCI_SPI1_BASE
+#define CONFIG_SYS_SPI_CLK		davinci_clk_get(SPI_PLLDIV)
+#define CONFIG_SF_DEFAULT_SPEED		3000000
+#define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
+#define CONFIG_CMD_SF
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DAVINCI_MMC
+#define CONFIG_MMC_MBLOCK
+
+/* U-Boot command configuration */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BDI
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+
+#ifdef CONFIG_CMD_BDI
+#define CONFIG_CLOCKS
+#endif
+
+#ifdef CONFIG_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_MMC
+#endif
+
+#ifdef CONFIG_NAND_DAVINCI
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#endif
+
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+
+/* U-Boot general configuration */
+#define CONFIG_BOOTFILE		"uImage"	/* Boot file name */
+#define CONFIG_SYS_PROMPT	"cam_enc_4xx> "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size  */
+#define CONFIG_SYS_PBSIZE			/* Print buffer size */ \
+		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_LONGHELP
+
+#define CONFIG_MENU
+#define CONFIG_MENU_SHOW
+#define CONFIG_FIT
+#define CONFIG_BOARD_IMG_ADDR_R 0x80000000
+
+#ifdef CONFIG_NAND_DAVINCI
+#define CONFIG_ENV_SIZE			(16 << 10)
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		0x180000
+#define CONFIG_ENV_RANGE		0x040000
+#define CONFIG_ENV_OFFSET_REDUND	0x1c0000
+#undef CONFIG_ENV_IS_IN_FLASH
+#endif
+
+#if defined(CONFIG_MMC) && !defined(CONFIG_ENV_IS_IN_NAND)
+#define CONFIG_CMD_ENV
+#define CONFIG_SYS_MMC_ENV_DEV	0
+#define CONFIG_ENV_SIZE		(16 << 10)	/* 16 KiB */
+#define CONFIG_ENV_OFFSET	(51 << 9)	/* Sector 51 */
+#define CONFIG_ENV_IS_IN_MMC
+#undef CONFIG_ENV_IS_IN_FLASH
+#endif
+
+#define CONFIG_BOOTDELAY	3
+/*
+ * 24MHz InputClock / 15 prediv -> 1.6 MHz timer running
+ * Timeout 1 second.
+ */
+#define CONFIG_AIT_TIMER_TIMEOUT	0x186a00
+
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_TIMESTAMP
+
+/* U-Boot memory configuration */
+#define CONFIG_SYS_MALLOC_LEN		(1 << 20)	/* 1 MiB */
+#define CONFIG_SYS_MEMTEST_START	0x80000000	/* physical address */
+#define CONFIG_SYS_MEMTEST_END		0x81000000	/* test 16MB RAM */
+
+/* Linux interfacing */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_SYS_BARGSIZE	1024			/* bootarg Size */
+#define CONFIG_SYS_LOAD_ADDR	0x80700000		/* kernel address */
+
+#define MTDIDS_DEFAULT		"nand0=davinci_nand.0"
+#define MTDPARTS_DEFAULT			\
+	"mtdparts="				\
+		"davinci_nand.0:"		\
+			"128k(spl),"		\
+			"384k(UBLheader),"	\
+			"1m(u-boot),"		\
+			"512k(env),"		\
+			"-(ubi)"
+
+#define CONFIG_SYS_NAND_PAGE_SIZE	0x800
+#define CONFIG_SYS_NAND_BLOCK_SIZE	0x20000
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_POST_MEM_SUPPORT
+#define CONFIG_SPL_LDSCRIPT		"$(BOARDDIR)/u-boot-spl.lds"
+#define CONFIG_SPL_STACK		(0x00010000 + 0x7f00)
+
+#define CONFIG_SPL_TEXT_BASE		0x00000020 /*CONFIG_SYS_SRAM_START*/
+/* Provide at least 16MB spacing between us and the Linux Kernel image */
+#define CONFIG_SPL_PAD_TO		12320
+#define CONFIG_SPL_MAX_FOOTPRINT	12288
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SYS_TEXT_BASE		0x81080000
+#endif
+
+#define CONFIG_SYS_NAND_BASE		0x02000000
+#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
+					CONFIG_SYS_NAND_PAGE_SIZE)
+
+#define CONFIG_SYS_NAND_ECCPOS		{				\
+				24, 25, 26, 27, 28,			\
+				29, 30, 31, 32, 33, 34, 35, 36, 37, 38,	\
+				39, 40, 41, 42, 43, 44, 45, 46, 47, 48,	\
+				49, 50, 51, 52, 53, 54, 55, 56, 57, 58,	\
+				59, 60, 61, 62, 63 }
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
+#define CONFIG_SYS_NAND_ECCSIZE		0x200
+#define CONFIG_SYS_NAND_ECCBYTES	10
+#define CONFIG_SYS_NAND_MAX_OOBFREE	2
+#define CONFIG_SYS_NAND_MAX_ECCPOS	56
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+
+/*
+ * RBL searches from Block n (n = 1..24)
+ * so we can define, how many UBL Headers
+ * we can write before the real spl code
+ */
+#define CONFIG_SYS_NROF_PAGES_NAND_SPL	6
+
+#define CONFIG_SYS_NAND_U_BOOT_DST	0x81080000 /* u-boot TEXT_BASE */
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
+
+/*
+ * Post tests for memory testing
+ */
+#define CONFIG_POST	CONFIG_SYS_POST_MEMORY
+#define _POST_WORD_ADDR	0x0
+
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SPL_STACK
+
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	0xa0000
+#define CONFIG_SYS_NAND_U_BOOT_ERA_SIZE	0x100000
+
+/* for UBL header */
+#define CONFIG_SYS_UBL_BLOCK		(CONFIG_SYS_NAND_PAGE_SIZE)
+
+#define CONFIG_SYS_DM36x_PLL1_PLLM	0x55
+#define CONFIG_SYS_DM36x_PLL1_PREDIV	0x8005
+#define CONFIG_SYS_DM36x_PLL2_PLLM	0x09
+#define CONFIG_SYS_DM36x_PLL2_PREDIV	0x8000
+#define CONFIG_SYS_DM36x_PERI_CLK_CTRL	0x243F04FC
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV1	0x801b
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV2	0x8001
+/* POST DIV 680/2 = 340Mhz  -> MJCP and HDVICP bus interface clock */
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV3	0x8001
+/*
+ * POST DIV 680/4 = 170Mhz  -> EDMA/Peripheral CFG0(1/2 MJCP/HDVICP bus
+ * interface clk)
+ */
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV4	0x8003
+/* POST DIV 680/2 = 340Mhz  -> VPSS */
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV5	0x8001
+/* POST DIV 680/9 = 75.6 Mhz -> VENC */
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV6	0x8008
+/*
+ * POST DIV 680/1 = 680Mhz -> DDRx2(with internal divider of 2, clock boils
+ * down to 340 Mhz)
+ */
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV7	0x8000
+/* POST DIV 680/7= 97Mhz-> MMC0/SD0 */
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV8	0x8006
+/* POST DIV 680/28 = 24.3Mhz-> CLKOUT */
+#define CONFIG_SYS_DM36x_PLL1_PLLDIV9	0x801b
+
+#define CONFIG_SYS_DM36x_PLL2_PLLDIV1	0x8011
+/* POST DIV 432/1=432 Mhz  -> ARM926/(HDVICP block) clk */
+#define CONFIG_SYS_DM36x_PLL2_PLLDIV2	0x8000
+#define CONFIG_SYS_DM36x_PLL2_PLLDIV3	0x8001
+/* POST DIV 432/21= 20.5714 Mhz->VOICE Codec clk */
+#define CONFIG_SYS_DM36x_PLL2_PLLDIV4	0x8014
+/* POST DIV 432/16=27 Mhz  -> VENC(For SD modes, requires) */
+#define CONFIG_SYS_DM36x_PLL2_PLLDIV5	0x800f
+
+/*
+ * READ LATENCY 7 (CL + 2)
+ * CONFIG_PWRDNEN = 1
+ * CONFIG_EXT_STRBEN = 1
+ */
+#define CONFIG_SYS_DM36x_DDR2_DDRPHYCR	(0 \
+	| DV_DDR_PHY_EXT_STRBEN \
+	| DV_DDR_PHY_PWRDNEN \
+	| (7 << DV_DDR_PHY_RD_LATENCY_SHIFT))
+
+/*
+ * T_RFC = (trfc/DDR_CLK) - 1 = (195 / 2.941) - 1
+ * T_RP  = (trp/DDR_CLK) - 1  = (12.5 / 2.941) - 1
+ * T_RCD = (trcd/DDR_CLK) - 1 = (12.5 / 2.941) - 1
+ * T_WR  = (twr/DDR_CLK) - 1  = (15 / 2.941) - 1
+ * T_RAS = (tras/DDR_CLK) - 1 = (45 / 2.941) - 1
+ * T_RC  = (trc/DDR_CLK) - 1  = (57.5 / 2.941) - 1
+ * T_RRD = (trrd/DDR_CLK) - 1 = (7.5 / 2.941) - 1
+ * T_WTR = (twtr/DDR_CLK) - 1 = (7.5 / 2.941) - 1
+ */
+#define CONFIG_SYS_DM36x_DDR2_SDTIMR	(0 \
+	| (66 << DV_DDR_SDTMR1_RFC_SHIFT) \
+	| (4  << DV_DDR_SDTMR1_RP_SHIFT) \
+	| (4  << DV_DDR_SDTMR1_RCD_SHIFT) \
+	| (5  << DV_DDR_SDTMR1_WR_SHIFT) \
+	| (14 << DV_DDR_SDTMR1_RAS_SHIFT) \
+	| (19 << DV_DDR_SDTMR1_RC_SHIFT) \
+	| (2  << DV_DDR_SDTMR1_RRD_SHIFT) \
+	| (2  << DV_DDR_SDTMR1_WTR_SHIFT))
+
+/*
+ * T_RASMAX = (trasmax/refresh_rate) - 1 = (70K / 7812.6) - 1
+ * T_XP  = tCKE - 1 = 3 - 2
+ * T_XSNR= ((trfc + 10)/DDR_CLK) - 1 = (205 / 2.941) - 1
+ * T_XSRD = txsrd - 1 = 200 - 1
+ * T_RTP = (trtp/DDR_CLK) - 1 = (7.5 / 2.941) - 1
+ * T_CKE = tcke - 1     = 3 - 1
+ */
+#define CONFIG_SYS_DM36x_DDR2_SDTIMR2	(0 \
+	| (8  << DV_DDR_SDTMR2_RASMAX_SHIFT) \
+	| (2  << DV_DDR_SDTMR2_XP_SHIFT) \
+	| (69 << DV_DDR_SDTMR2_XSNR_SHIFT) \
+	| (199 <<  DV_DDR_SDTMR2_XSRD_SHIFT) \
+	| (2 <<  DV_DDR_SDTMR2_RTP_SHIFT) \
+	| (2 <<  DV_DDR_SDTMR2_CKE_SHIFT))
+
+/* PR_OLD_COUNT = 0xfe */
+#define CONFIG_SYS_DM36x_DDR2_PBBPR	0x000000FE
+/* refresh rate = 0x768 */
+#define CONFIG_SYS_DM36x_DDR2_SDRCR	0x00000768
+
+#define CONFIG_SYS_DM36x_DDR2_SDBCR	(0 \
+	| (2 << DV_DDR_SDCR_PAGESIZE_SHIFT) \
+	| (3 << DV_DDR_SDCR_IBANK_SHIFT) \
+	| (5 << DV_DDR_SDCR_CL_SHIFT) \
+	| (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT)	\
+	| (1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT) \
+	| (1 << DV_DDR_SDCR_DDREN_SHIFT) \
+	| (0 << DV_DDR_SDCR_DDRDRIVE0_SHIFT)	\
+	| (1 << DV_DDR_SDCR_DDR2EN_SHIFT) \
+	| (1 << DV_DDR_SDCR_DDR_DDQS_SHIFT) \
+	| (1 << DV_DDR_SDCR_BOOTUNLOCK_SHIFT))
+
+#define CONFIG_SYS_DM36x_AWCCR	0xff
+#define CONFIG_SYS_DM36x_AB1CR	0x40400204
+#define CONFIG_SYS_DM36x_AB2CR	0x04ca2650
+
+/* All Video Inputs */
+#define CONFIG_SYS_DM36x_PINMUX0	0x00000000
+/*
+ * All Video Outputs,
+ * GPIO 86, 87 + 90 0x0000f030
+ */
+#define CONFIG_SYS_DM36x_PINMUX1	0x00530002
+#define CONFIG_SYS_DM36x_PINMUX2	0x00001815
+/*
+ * SPI1, UART1, I2C, SD0, SD1, McBSP0, CLKOUTs
+ * GPIO 25 0x60000000
+ */
+#define CONFIG_SYS_DM36x_PINMUX3	0x9b5affff
+/*
+ * MMC/SD0 instead of MS, SPI0
+ * GPIO 34 0x0000c000
+ */
+#define CONFIG_SYS_DM36x_PINMUX4	0x00002655
+
+/*
+ * Default environment settings
+ */
+
+#define DVN4XX_UBOOT_ADDR_R_RAM		0x80000000
+/* (DVN4XX_UBOOT_ADDR_R_RAM + CONFIG_SYS_NAND_PAGE_SIZE) */
+#define DVN4XX_UBOOT_ADDR_R_NAND_SPL	0x80000800
+/*
+ * (DVN4XX_UBOOT_ADDR_R_NAND_SPL + (CONFIG_SYS_NROF_PAGES_NAND_SPL * \
+ * CONFIG_SYS_NAND_PAGE_SIZE))
+ */
+#define DVN4XX_UBOOT_ADDR_R_UBOOT	0x80003800
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"u_boot_addr_r=" __stringify(DVN4XX_UBOOT_ADDR_R_RAM) "\0"	\
+	"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.ubl\0"		\
+	"load=tftp ${u_boot_addr_r} ${u-boot}\0"			\
+	"pagesz=" __stringify(CONFIG_SYS_NAND_PAGE_SIZE) "\0"		\
+	"writeheader=nandrbl rbl;nand erase 20000 ${pagesz};"		\
+		"nand write ${u_boot_addr_r} 20000 ${pagesz};"		\
+		"nandrbl uboot\0"					\
+	"writenand_spl=nandrbl rbl;nand erase 0 3000;"			\
+		"nand write " __stringify(DVN4XX_UBOOT_ADDR_R_NAND_SPL)	\
+		" 0 3000;nandrbl uboot\0"				\
+	"writeuboot=nandrbl uboot;"					\
+		"nand erase " __stringify(CONFIG_SYS_NAND_U_BOOT_OFFS) " "\
+		 __stringify(CONFIG_SYS_NAND_U_BOOT_ERA_SIZE)		\
+		";nand write " __stringify(DVN4XX_UBOOT_ADDR_R_UBOOT)	\
+		" " __stringify(CONFIG_SYS_NAND_U_BOOT_OFFS) " "	\
+		__stringify(CONFIG_SYS_NAND_U_BOOT_SIZE) "\0"		\
+	"update=run load writenand_spl writeuboot\0"			\
+	"bootcmd=run net_nfs\0"						\
+	"rootpath=/opt/eldk-arm/arm\0"					\
+	"mtdids=" MTDIDS_DEFAULT "\0"					\
+	"mtdparts=" MTDPARTS_DEFAULT "\0"				\
+	"netdev=eth0\0"							\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
+	"addmisc=setenv bootargs ${bootargs} app_reset=${app_reset}\0"	\
+	"addcon=setenv bootargs ${bootargs} console=ttyS0,"		\
+		"${baudrate}n8\0"					\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off eth=${ethaddr} panic=1\0"	\
+	"rootpath=/opt/eldk-arm/arm\0"					\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage \0"		\
+	"kernel_addr_r=80600000\0"					\
+	"load_kernel=tftp ${kernel_addr_r} ${bootfile}\0"		\
+	"ubi_load_kernel=ubi part ubi 2048;ubifsmount ubi:${img_volume};" \
+		"ubifsload ${kernel_addr_r} boot/uImage\0"		\
+	"fit_addr_r=" __stringify(CONFIG_BOARD_IMG_ADDR_R) "\0"		\
+	"img_addr_r=" __stringify(CONFIG_BOARD_IMG_ADDR_R) "\0"		\
+	"img_file=" __stringify(CONFIG_HOSTNAME) "/ait.itb\0"		\
+	"header_addr=20000\0"						\
+	"img_writeheader=nandrbl rbl;"					\
+		"nand erase ${header_addr} ${pagesz};"			\
+		"nand write ${img_addr_r} ${header_addr} ${pagesz};"	\
+		"nandrbl uboot\0"					\
+	"img_writespl=nandrbl rbl;nand erase 0 3000;"			\
+		"nand write ${img_addr_r} 0 3000;nandrbl uboot\0"	\
+	"img_writeuboot=nandrbl uboot;"					\
+		"nand erase " __stringify(CONFIG_SYS_NAND_U_BOOT_OFFS) " "\
+		 __stringify(CONFIG_SYS_NAND_U_BOOT_ERA_SIZE)		\
+		";nand write ${img_addr_r} "				\
+		__stringify(CONFIG_SYS_NAND_U_BOOT_OFFS) " "		\
+		__stringify(CONFIG_SYS_NAND_U_BOOT_SIZE) "\0"		\
+	"img_writedfenv=ubi part ubi 2048;"				\
+		"ubi write ${img_addr_r} default ${filesize}\0"		\
+	"img_volume=rootfs1\0"						\
+	"img_writeramdisk=ubi part ubi 2048;"				\
+		"ubi write ${img_addr_r} ${img_volume} ${filesize}\0"	\
+	"load_img=tftp ${fit_addr_r} ${img_file}\0"			\
+	"net_nfs=run load_kernel; "					\
+		"run nfsargs addip addcon addmtd addmisc;"		\
+		"bootm ${kernel_addr_r}\0"				\
+	"ubi_ubi=run ubi_load_kernel; "					\
+		"run ubiargs addip addcon addmtd addmisc;"		\
+		"bootm ${kernel_addr_r}\0"				\
+	"ubiargs=setenv bootargs ubi.mtd=4,2048"			\
+		" root=ubi0:${img_volume} rw rootfstype=ubifs\0"	\
+	"app_reset=no\0"						\
+	"dvn_app_vers=void\0"						\
+	"dvn_boot_vers=void\0"						\
+	"savenewvers=run savetmpparms restoreparms; saveenv;"		\
+		"run restoretmpparms\0"					\
+	"savetmpparms=setenv y_ipaddr ${ipaddr};"			\
+		"setenv y_netmask ${netmask};"				\
+		"setenv y_serverip ${serverip};"			\
+		"setenv y_gatewayip ${gatewayip}\0"			\
+	"saveparms=setenv x_ipaddr ${ipaddr};"				\
+		"setenv x_netmask ${netmask};"				\
+		"setenv x_serverip ${serverip};"			\
+		"setenv x_gatewayip ${gatewayip}\0"			\
+	"restoreparms=setenv ipaddr ${x_ipaddr};"			\
+		"setenv netmask ${x_netmask};"				\
+		"setenv serverip ${x_serverip};"			\
+		"setenv gatewayip ${x_gatewayip}\0"			\
+	"restoretmpparms=setenv ipaddr ${y_ipaddr};"			\
+		"setenv netmask ${y_netmask};"				\
+		"setenv serverip ${y_serverip};"			\
+		"setenv gatewayip ${y_gatewayip}\0"			\
+	"\0"
+
+/* USB Configuration */
+#define CONFIG_USB_DAVINCI
+#define CONFIG_MUSB_HCD
+#define CONFIG_DV_USBPHY_CTL (USBPHY_SESNDEN | USBPHY_VBDTCTEN | \
+				USBPHY_PHY24MHZ)
+
+#define CONFIG_CMD_USB         /* include support for usb cmd */
+#define CONFIG_USB_STORAGE     /* MSC class support */
+#define CONFIG_CMD_STORAGE     /* inclue support for usb-storage cmd */
+#define CONFIG_CMD_FAT         /* inclue support for FAT/storage */
+#define CONFIG_DOS_PARTITION   /* inclue support for FAT/storage */
+
+#undef DAVINCI_DM365EVM
+#define PINMUX4_USBDRVBUS_BITCLEAR       0x3000
+#define PINMUX4_USBDRVBUS_BITSET         0x2000
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/canmb.h b/qemu/roms/u-boot/include/configs/canmb.h
new file mode 100644
index 000000000..c90179380
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/canmb.h
@@ -0,0 +1,214 @@
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5200		1	/* This is a MPC5200 CPU */
+#define CONFIG_CANMB		1	/* ... on canmb board - we need this for FEC.C */
+
+/*
+ * allowed and functional CONFIG_SYS_TEXT_BASE values:
+ * 0xfe000000	low boot at 0x00000100 (default board setting)
+ * 0x00100000	RAM load and test
+ */
+#define	CONFIG_SYS_TEXT_BASE	0xFE000000
+
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
+
+#define CONFIG_BOARD_EARLY_INIT_R
+
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
+#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SNTP
+
+
+/*
+ * MUST be low boot - HIGHBOOT is not supported anymore
+ */
+#if (CONFIG_SYS_TEXT_BASE == 0xFE000000)		/* Boot low with 32 MB Flash */
+#   define CONFIG_SYS_LOWBOOT		1
+#   define CONFIG_SYS_LOWBOOT16	1
+#else
+#   error "CONFIG_SYS_TEXT_BASE must be 0xFE000000"
+#endif
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_6xx\0"					\
+	"bootfile=/tftpboot/canmb/uImage\0"				\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
+
+/*
+ * Flash configuration, expect one 16 Megabyte Bank at most
+ */
+#define CONFIG_SYS_FLASH_BASE		0xFE000000
+#define CONFIG_SYS_FLASH_SIZE		0x02000000
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max num of sects on one chip */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_OFFSET		(2*128*1024)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE       (128*1024)
+
+/*
+ * Memory map
+ *
+ * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000
+ */
+#define CONFIG_SYS_MBAR			0xf0000000	/* DO NOT CHANGE this */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
+
+/* Use SRAM until RAM will be available */
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */
+
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC	1
+#define CONFIG_MPC5xxx_FEC_MII100
+#define	CONFIG_PHY_ADDR		0x0
+/*
+ * GPIO configuration:
+ * PSC1,2,3 predefined as UART
+ * PCI disabled
+ * Ethernet 100 with MD
+ */
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x00058444
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#if defined(CONFIG_CMD_KGDB)
+#  define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#  define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x01f00000	/* 1 ... 31 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x200000	/* default load address */
+
+#define CONFIG_RTC_MPC5200	1	/* use internal MPC5200 RTC */
+
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*
+ * Various low-level settings
+ */
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
+
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_CFG		0x00047D01
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
+
+#define CONFIG_SYS_CS_BURST		0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE	0x33333333
+
+#define CONFIG_SYS_RESET_ADDRESS	0x7f000000
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/canyonlands.h b/qemu/roms/u-boot/include/configs/canyonlands.h
new file mode 100644
index 000000000..8eeb15c0e
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/canyonlands.h
@@ -0,0 +1,674 @@
+/*
+ * (C) Copyright 2008
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/************************************************************************
+ * canyonlands.h - configuration for Canyonlands (460EX)
+ ***********************************************************************/
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+/*
+ * This config file is used for Canyonlands (460EX) Glacier (460GT)
+ * and Arches dual (460GT)
+ */
+#ifdef CONFIG_CANYONLANDS
+#define CONFIG_460EX		1	/* Specific PPC460EX		*/
+#define CONFIG_HOSTNAME		canyonlands
+#else
+#define CONFIG_460GT		1	/* Specific PPC460GT		*/
+#ifdef CONFIG_GLACIER
+#define CONFIG_HOSTNAME		glacier
+#else
+#define CONFIG_HOSTNAME		arches
+#define CONFIG_USE_NETDEV	eth1
+#define CONFIG_BD_NUM_CPUS	2
+#endif
+#endif
+
+#define CONFIG_440		1
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xFFF80000
+#endif
+
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#include "amcc-common.h"
+
+#define CONFIG_SYS_CLK_FREQ	66666667	/* external freq to pll	*/
+
+#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_early_init_f */
+#define CONFIG_BOARD_EARLY_INIT_R	1	/* Call board_early_init_r */
+#define CONFIG_MISC_INIT_R		1	/* Call misc_init_r */
+#define CONFIG_BOARD_TYPES		1	/* support board types */
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped PCI memory	*/
+#define CONFIG_SYS_PCI_BASE		0xd0000000	/* internal PCI regs	*/
+#define CONFIG_SYS_PCI_TARGBASE	CONFIG_SYS_PCI_MEMBASE
+
+#define CONFIG_SYS_PCIE_MEMBASE	0xb0000000	/* mapped PCIe memory	*/
+#define CONFIG_SYS_PCIE_MEMSIZE	0x08000000	/* smallest incr for PCIe port */
+#define CONFIG_SYS_PCIE_BASE		0xc4000000	/* PCIe UTL regs */
+
+#define CONFIG_SYS_PCIE0_CFGBASE	0xc0000000
+#define CONFIG_SYS_PCIE1_CFGBASE	0xc1000000
+#define CONFIG_SYS_PCIE0_XCFGBASE	0xc3000000
+#define CONFIG_SYS_PCIE1_XCFGBASE	0xc3001000
+
+/*
+ * BCSR bits as defined in the Canyonlands board user manual.
+ */
+#define BCSR_USBCTRL_OTG_RST	0x32
+#define BCSR_USBCTRL_HOST_RST	0x01
+#define BCSR_SELECT_PCIE	0x10
+
+#define	CONFIG_SYS_PCIE0_UTLBASE	0xc08010000ULL	/* 36bit physical addr	*/
+
+/* base address of inbound PCIe window */
+#define CONFIG_SYS_PCIE_INBOUND_BASE	0x000000000ULL	/* 36bit physical addr	*/
+
+/* EBC stuff */
+#if !defined(CONFIG_ARCHES)
+#define CONFIG_SYS_BCSR_BASE		0xE1000000
+#define CONFIG_SYS_FLASH_BASE		0xFC000000	/* later mapped to this addr */
+#define CONFIG_SYS_FLASH_SIZE		(64 << 20)
+#else
+#define CONFIG_SYS_FPGA_BASE		0xE1000000
+#define CONFIG_SYS_CPLD_ADDR		(CONFIG_SYS_FPGA_BASE + 0x00080000)
+#define CONFIG_SYS_CPLD_DATA		(CONFIG_SYS_FPGA_BASE + 0x00080002)
+#define CONFIG_SYS_FLASH_BASE		0xFE000000	/* later mapped to this addr  */
+#define CONFIG_SYS_FLASH_SIZE		(32 << 20)
+#endif
+
+#define CONFIG_SYS_NAND_ADDR		0xE0000000
+#define CONFIG_SYS_BOOT_BASE_ADDR	0xFF000000	/* EBC Boot Space: 0xFF000000 */
+#define CONFIG_SYS_FLASH_BASE_PHYS_H	0x4
+#define CONFIG_SYS_FLASH_BASE_PHYS_L	0xCC000000
+#define CONFIG_SYS_FLASH_BASE_PHYS	(((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) |	\
+					 (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
+
+#define CONFIG_SYS_OCM_BASE		0xE3000000	/* OCM: 64k		*/
+#define CONFIG_SYS_SRAM_BASE		0xE8000000	/* SRAM: 256k		*/
+#define CONFIG_SYS_SRAM_SIZE		(256 << 10)
+#define CONFIG_SYS_LOCAL_CONF_REGS	0xEF000000
+
+#define CONFIG_SYS_AHB_BASE		0xE2000000	/* internal AHB peripherals	*/
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in OCM)
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_BASE	/* OCM			*/
+#define CONFIG_SYS_INIT_RAM_SIZE	(4 << 10)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+/*
+ * Define here the location of the environment variables (FLASH).
+ */
+#define	CONFIG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars */
+#define CONFIG_SYS_NOR_CS		0	/* NOR chip connected to CSx */
+#define CONFIG_SYS_NAND_CS		3	/* NAND chip connected to CSx */
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible	*/
+#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
+#define CONFIG_SYS_FLASH_CFI_AMD_RESET	1	/* Use AMD (Spansion) reset cmd */
+
+#define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	0x20000		/* size of one complete sector	*/
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+#endif /* CONFIG_ENV_IS_IN_FLASH */
+
+/*-----------------------------------------------------------------------
+ * NAND-FLASH related
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		(CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
+#define CONFIG_SYS_NAND_SELECT_DEVICE  1	/* nand driver supports mutipl. chips	*/
+
+/*------------------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------------*/
+#if !defined(CONFIG_ARCHES)
+/*
+ * NAND booting U-Boot version uses a fixed initialization, since the whole
+ * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot
+ * code.
+ */
+#define CONFIG_SPD_EEPROM	1	/* Use SPD EEPROM for setup	*/
+#define SPD_EEPROM_ADDRESS	{0x50, 0x51}	/* SPD i2c spd addresses*/
+#define CONFIG_DDR_ECC		1	/* with ECC support		*/
+#define CONFIG_DDR_RQDC_FIXED	0x80000038 /* fixed value for RQDC	*/
+
+#else /* defined(CONFIG_ARCHES) */
+
+#define CONFIG_AUTOCALIB	"silent\0"	/* default is non-verbose    */
+
+#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION	/* IBM DDR autocalibration   */
+#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION	/* dynamic DDR autocal debug */
+#undef CONFIG_PPC4xx_DDR_METHOD_A
+
+/* DDR1/2 SDRAM Device Control Register Data Values */
+/* Memory Queue */
+#define CONFIG_SYS_SDRAM_R0BAS		0x0000f000
+#define CONFIG_SYS_SDRAM_R1BAS		0x00000000
+#define CONFIG_SYS_SDRAM_R2BAS		0x00000000
+#define CONFIG_SYS_SDRAM_R3BAS		0x00000000
+#define CONFIG_SYS_SDRAM_PLBADDULL	0x00000000
+#define CONFIG_SYS_SDRAM_PLBADDUHB	0x00000008
+#define CONFIG_SYS_SDRAM_CONF1LL	0x00001080
+#define CONFIG_SYS_SDRAM_CONF1HB	0x00001080
+#define CONFIG_SYS_SDRAM_CONFPATHB	0x10a68000
+
+/* SDRAM Controller */
+#define CONFIG_SYS_SDRAM0_MB0CF		0x00000701
+#define CONFIG_SYS_SDRAM0_MB1CF		0x00000000
+#define CONFIG_SYS_SDRAM0_MB2CF		0x00000000
+#define CONFIG_SYS_SDRAM0_MB3CF		0x00000000
+#define CONFIG_SYS_SDRAM0_MCOPT1	0x05322000
+#define CONFIG_SYS_SDRAM0_MCOPT2	0x00000000
+#define CONFIG_SYS_SDRAM0_MODT0		0x01000000
+#define CONFIG_SYS_SDRAM0_MODT1		0x00000000
+#define CONFIG_SYS_SDRAM0_MODT2		0x00000000
+#define CONFIG_SYS_SDRAM0_MODT3		0x00000000
+#define CONFIG_SYS_SDRAM0_CODT		0x00800021
+#define CONFIG_SYS_SDRAM0_RTR		0x06180000
+#define CONFIG_SYS_SDRAM0_INITPLR0	0xb5380000
+#define CONFIG_SYS_SDRAM0_INITPLR1	0x82100400
+#define CONFIG_SYS_SDRAM0_INITPLR2	0x80820000
+#define CONFIG_SYS_SDRAM0_INITPLR3	0x80830000
+#define CONFIG_SYS_SDRAM0_INITPLR4	0x80810040
+#define CONFIG_SYS_SDRAM0_INITPLR5	0x80800532
+#define CONFIG_SYS_SDRAM0_INITPLR6	0x82100400
+#define CONFIG_SYS_SDRAM0_INITPLR7	0x8a080000
+#define CONFIG_SYS_SDRAM0_INITPLR8	0x8a080000
+#define CONFIG_SYS_SDRAM0_INITPLR9	0x8a080000
+#define CONFIG_SYS_SDRAM0_INITPLR10	0x8a080000
+#define CONFIG_SYS_SDRAM0_INITPLR11	0x80000432
+#define CONFIG_SYS_SDRAM0_INITPLR12	0x808103c0
+#define CONFIG_SYS_SDRAM0_INITPLR13	0x80810040
+#define CONFIG_SYS_SDRAM0_INITPLR14	0x00000000
+#define CONFIG_SYS_SDRAM0_INITPLR15	0x00000000
+#define CONFIG_SYS_SDRAM0_RQDC		0x80000038
+#define CONFIG_SYS_SDRAM0_RFDC		0x00000257
+#define CONFIG_SYS_SDRAM0_RDCC		0x40000000
+#define CONFIG_SYS_SDRAM0_DLCR		0x03000091
+#define CONFIG_SYS_SDRAM0_CLKTR		0x40000000
+#define CONFIG_SYS_SDRAM0_WRDTR		0x82000823
+#define CONFIG_SYS_SDRAM0_SDTR1		0x80201000
+#define CONFIG_SYS_SDRAM0_SDTR2		0x42204243
+#define CONFIG_SYS_SDRAM0_SDTR3		0x090c0d1a
+#define CONFIG_SYS_SDRAM0_MMODE		0x00000432
+#define CONFIG_SYS_SDRAM0_MEMODE	0x00000004
+#endif	/* !defined(CONFIG_ARCHES) */
+
+#define CONFIG_SYS_MBYTES_SDRAM	512	/* 512MB			*/
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
+
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR		(0xa8>>1)
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
+
+/* I2C bootstrap EEPROM */
+#if defined(CONFIG_ARCHES)
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR	0x54
+#else
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR	0x52
+#endif
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET	0
+#define CONFIG_4xx_CONFIG_BLOCKSIZE		16
+
+/* I2C SYSMON (LM75, AD7414 is almost compatible)			*/
+#define CONFIG_DTT_LM75		1		/* ON Semi's LM75	*/
+#define CONFIG_DTT_AD7414	1		/* use AD7414		*/
+#define CONFIG_DTT_SENSORS	{0}		/* Sensor addresses	*/
+#define CONFIG_SYS_DTT_MAX_TEMP	70
+#define CONFIG_SYS_DTT_LOW_TEMP	-30
+#define CONFIG_SYS_DTT_HYSTERESIS	3
+
+#if defined(CONFIG_ARCHES)
+#define CONFIG_SYS_I2C_DTT_ADDR	0x4a		/* AD7414 I2C address	*/
+#endif
+
+#if !defined(CONFIG_ARCHES)
+/* RTC configuration */
+#define CONFIG_RTC_M41T62	1
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68
+#endif
+
+/*-----------------------------------------------------------------------
+ * Ethernet
+ *----------------------------------------------------------------------*/
+#define CONFIG_IBM_EMAC4_V4	1
+
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+
+#if !defined(CONFIG_ARCHES)
+#define CONFIG_PHY_ADDR		0	/* PHY address, See schematics	*/
+#define CONFIG_PHY1_ADDR	1
+/* Only Glacier (460GT) has 4 EMAC interfaces */
+#ifdef CONFIG_460GT
+#define CONFIG_PHY2_ADDR	2
+#define CONFIG_PHY3_ADDR	3
+#define CONFIG_HAS_ETH2
+#define CONFIG_HAS_ETH3
+#endif
+
+#else /* defined(CONFIG_ARCHES) */
+
+#define CONFIG_FIXED_PHY	0xFFFFFFFF
+#define CONFIG_PHY_ADDR		CONFIG_FIXED_PHY
+#define CONFIG_PHY1_ADDR	0
+#define CONFIG_PHY2_ADDR	1
+#define CONFIG_HAS_ETH2
+
+#define CONFIG_SYS_FIXED_PHY_PORT(devnum, speed, duplex) \
+		{devnum, speed, duplex}
+#define CONFIG_SYS_FIXED_PHY_PORTS \
+		CONFIG_SYS_FIXED_PHY_PORT(0, 1000, FULL)
+
+#define CONFIG_M88E1112_PHY
+
+/*
+ * For the GPCS_PHYx_ADDR PHY address, choose some PHY address not
+ * used by CONFIG_PHYx_ADDR
+ */
+#define CONFIG_GPCS_PHY_ADDR    0xA
+#define CONFIG_GPCS_PHY1_ADDR   0xB
+#define CONFIG_GPCS_PHY2_ADDR   0xC
+#endif	/* !defined(CONFIG_ARCHES) */
+
+#define CONFIG_PHY_RESET	1	/* reset phy upon startup	*/
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+#define CONFIG_PHY_DYNAMIC_ANEG	1
+
+/*-----------------------------------------------------------------------
+ * USB-OHCI
+ *----------------------------------------------------------------------*/
+/* Only Canyonlands (460EX) has USB */
+#ifdef CONFIG_460EX
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_USB_STORAGE
+#undef CONFIG_SYS_OHCI_BE_CONTROLLER		/* 460EX has little endian descriptors	*/
+#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS	/* 460EX has little endian register	*/
+#define CONFIG_SYS_OHCI_USE_NPS		/* force NoPowerSwitching mode		*/
+#define CONFIG_SYS_USB_OHCI_REGS_BASE	(CONFIG_SYS_AHB_BASE | 0xd0000)
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"ppc440"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
+#define CONFIG_SYS_USB_OHCI_BOARD_INIT
+#endif
+
+/*
+ * Default environment variables
+ */
+#if !defined(CONFIG_ARCHES)
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_AMCC_DEF_ENV						\
+	CONFIG_AMCC_DEF_ENV_POWERPC					\
+	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
+	"kernel_addr=fc000000\0"					\
+	"fdt_addr=fc1e0000\0"						\
+	"ramdisk_addr=fc200000\0"					\
+	"pciconfighost=1\0"						\
+	"pcie_mode=RP:RP\0"						\
+	""
+#else /* defined(CONFIG_ARCHES) */
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_AMCC_DEF_ENV						\
+	CONFIG_AMCC_DEF_ENV_POWERPC					\
+	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
+	"kernel_addr=fe000000\0"					\
+	"fdt_addr=fe1e0000\0"						\
+	"ramdisk_addr=fe200000\0"					\
+	"pciconfighost=1\0"						\
+	"pcie_mode=RP:RP\0"						\
+	"ethprime=ppc_4xx_eth1\0"					\
+	""
+#endif	/* !defined(CONFIG_ARCHES) */
+
+/*
+ * Commands additional to the ones defined in amcc-common.h
+ */
+#define CONFIG_CMD_CHIP_CONFIG
+#if defined(CONFIG_ARCHES)
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_SDRAM
+#elif defined(CONFIG_CANYONLANDS)
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_SATA
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_USB
+#elif defined(CONFIG_GLACIER)
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
+#else
+#error "board type not defined"
+#endif
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *----------------------------------------------------------------------*/
+/* General PCI */
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play   */
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup  */
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE
+
+/* Board-specific PCI */
+#define CONFIG_SYS_PCI_TARGET_INIT		/* let board init pci target    */
+#undef	CONFIG_SYS_PCI_MASTER_INIT
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014	/* IBM				*/
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever			*/
+
+#ifdef CONFIG_460GT
+#if defined(CONFIG_ARCHES)
+/*-----------------------------------------------------------------------
+ * RapidIO I/O and Registers
+ *----------------------------------------------------------------------*/
+#define CONFIG_RAPIDIO
+#define CONFIG_SYS_460GT_SRIO_ERRATA_1
+
+#define SRGPL0_REG_BAR		0x0000000DAA000000ull	/*  16MB */
+#define SRGPL0_CFG_BAR		0x0000000DAB000000ull	/*  16MB */
+#define SRGPL0_MNT_BAR		0x0000000DAC000000ull	/*  16MB */
+#define SRGPL0_MSG_BAR		0x0000000DAD000000ull	/*  16MB */
+#define SRGPL0_OUT_BAR		0x0000000DB0000000ull	/* 256MB */
+
+#define CONFIG_SYS_SRGPL0_REG_BAR	0xAA000000		/*  16MB */
+#define CONFIG_SYS_SRGPL0_CFG_BAR	0xAB000000		/*  16MB */
+#define CONFIG_SYS_SRGPL0_MNT_BAR	0xAC000000		/*  16MB */
+#define CONFIG_SYS_SRGPL0_MSG_BAR	0xAD000000		/*  16MB */
+
+#define CONFIG_SYS_I2ODMA_BASE		0xCF000000
+#define CONFIG_SYS_I2ODMA_PHYS_ADDR	0x0000000400100000ull
+
+#define CONFIG_PPC4XX_RAPIDIO_PROMISCUOUS_MODE
+#undef CONFIG_PPC4XX_RAPIDIO_DEBUG
+#undef CONFIG_PPC4XX_RAPIDIO_IN_BAR_USE_OCM
+#define CONFIG_PPC4XX_RAPIDIO_USE_HB_PLB
+#undef CONFIG_PPC4XX_RAPIDIO_LOOPBACK
+#endif /* CONFIG_ARCHES */
+#endif /* CONFIG_460GT */
+
+/*
+ * SATA driver setup
+ */
+#ifdef CONFIG_CMD_SATA
+#define CONFIG_SATA_DWC
+#define CONFIG_LIBATA
+#define SATA_BASE_ADDR		0xe20d1000	/* PPC460EX SATA Base Address */
+#define SATA_DMA_REG_ADDR	0xe20d0800	/* PPC460EX SATA Base Address */
+#define CONFIG_SYS_SATA_MAX_DEVICE	1	/* SATA MAX DEVICE */
+/* Convert sectorsize to wordsize */
+#define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2)
+#endif
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ *----------------------------------------------------------------------*/
+
+/*
+ * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
+ * boot EBC mapping only supports a maximum of 16MBytes
+ * (4.ff00.0000 - 4.ffff.ffff).
+ * To solve this problem, the FLASH has to get remapped to another
+ * EBC address which accepts bigger regions:
+ *
+ * 0xfc00.0000 -> 4.cc00.0000
+ *
+ * Arches has 32MBytes of NOR FLASH (Spansion 29GL256), it will be
+ * remapped to:
+ *
+ * 0xfe00.0000 -> 4.ce00.0000
+ */
+
+/* Memory Bank 0 (NOR-FLASH) initialization					*/
+#define CONFIG_SYS_EBC_PB0AP		0x10055e00
+#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000)
+
+#if !defined(CONFIG_ARCHES)
+/* Memory Bank 3 (NAND-FLASH) initialization						*/
+#define CONFIG_SYS_EBC_PB3AP		0x018003c0
+#define CONFIG_SYS_EBC_PB3CR		(CONFIG_SYS_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/
+#endif
+
+#if !defined(CONFIG_ARCHES)
+/* Memory Bank 2 (CPLD) initialization						*/
+#define CONFIG_SYS_EBC_PB2AP		0x00804240
+#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_BCSR_BASE | 0x18000) /* BAS=CPLD,BS=1M,BU=RW,BW=32bit */
+
+#else /* defined(CONFIG_ARCHES) */
+
+/* Memory Bank 1 (FPGA) initialization  */
+#define CONFIG_SYS_EBC_PB1AP		0x7f8ffe80
+#define CONFIG_SYS_EBC_PB1CR		(CONFIG_SYS_FPGA_BASE | 0x3a000) /* BAS=FPGA,BS=2MB,BU=R/W,BW=16bit*/
+#endif	/* !defined(CONFIG_ARCHES) */
+
+#define CONFIG_SYS_EBC_CFG		0xbfc00000
+
+/*
+ * Arches doesn't use PerCS3 but GPIO43, so let's configure the GPIO
+ * pin multiplexing correctly
+ */
+#if defined(CONFIG_ARCHES)
+#define GPIO43_USE		GPIO_SEL	/* On Arches this pin is used as GPIO */
+#else
+#define GPIO43_USE		GPIO_ALT1	/* On Glacier this pin is used as ALT1 -> PerCS3 */
+#endif
+
+/*
+ * PPC4xx GPIO Configuration
+ */
+#ifdef CONFIG_460EX
+/* 460EX: Use USB configuration */
+#define CONFIG_SYS_4xx_GPIO_TABLE { /*	  Out		  GPIO	Alternate1	Alternate2	Alternate3 */ \
+{											\
+/* GPIO Core 0 */									\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0	GMC1TxD(0)	USB2HostD(0)	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1	GMC1TxD(1)	USB2HostD(1)	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2	GMC1TxD(2)	USB2HostD(2)	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO3	GMC1TxD(3)	USB2HostD(3)	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO4	GMC1TxD(4)	USB2HostD(4)	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO5	GMC1TxD(5)	USB2HostD(5)	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO6	GMC1TxD(6)	USB2HostD(6)	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO7	GMC1TxD(7)	USB2HostD(7)	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8	GMC1RxD(0)	USB2OTGD(0)	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9	GMC1RxD(1)	USB2OTGD(1)	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2)	USB2OTGD(2)	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3)	USB2OTGD(3)	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4)	USB2OTGD(4)	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5)	USB2OTGD(5)	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6)	USB2OTGD(6)	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7)	USB2OTGD(7)	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL,  GPIO_OUT_0}, /* GPIO16 GMC1TxER	USB2HostStop	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD		USB2HostNext	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER	USB2HostDir	*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO19 GMC1TxEN	USB2OTGStop	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS	USB2OTGNext	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV	USB2OTGDir	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0)				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1)				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2)				*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0	DMAReq2		IRQ(7)*/ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1	DMAAck2		IRQ(8)*/ \
+},											\
+{											\
+/* GPIO Core 1 */									\
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2	EOT2/TC2	IRQ(9)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3	DMAReq3		IRQ(4)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N	UART1_DSR_CTS_N	UART2_SOUT*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3	UART3_SIN*/ \
+{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N	EOT3/TC3	UART3_SOUT*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N	UART1_SOUT	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N	UART1_SIN	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3)				*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1)				*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2)				*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3)		DMAReq1		IRQ(10)*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4)		DMAAck1		IRQ(11)*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5)		EOT/TC1		IRQ(12)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5)	DMAReq0		IRQ(13)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6)	DMAAck0		IRQ(14)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7)	EOT/TC0		IRQ(15)*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit	*/	\
+}											\
+}
+#else
+/* 460GT: Use EMAC2+3 configuration */
+#define CONFIG_SYS_4xx_GPIO_TABLE { /*	  Out		  GPIO	Alternate1	Alternate2	Alternate3 */ \
+{											\
+/* GPIO Core 0 */									\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0	GMC1TxD(0)	USB2HostD(0)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1	GMC1TxD(1)	USB2HostD(1)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2	GMC1TxD(2)	USB2HostD(2)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3	GMC1TxD(3)	USB2HostD(3)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4	GMC1TxD(4)	USB2HostD(4)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5	GMC1TxD(5)	USB2HostD(5)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6	GMC1TxD(6)	USB2HostD(6)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7	GMC1TxD(7)	USB2HostD(7)	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8	GMC1RxD(0)	USB2OTGD(0)	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9	GMC1RxD(1)	USB2OTGD(1)	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2)	USB2OTGD(2)	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3)	USB2OTGD(3)	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4)	USB2OTGD(4)	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5)	USB2OTGD(5)	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6)	USB2OTGD(6)	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7)	USB2OTGD(7)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMC1TxER	USB2HostStop	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD		USB2HostNext	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER	USB2HostDir	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMC1TxEN	USB2OTGStop	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS	USB2OTGNext	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV	USB2OTGDir	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0)				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1)				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2)				*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0	DMAReq2		IRQ(7)*/ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1	DMAAck2		IRQ(8)*/ \
+},											\
+{											\
+/* GPIO Core 1 */									\
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2	EOT2/TC2	IRQ(9)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3	DMAReq3		IRQ(4)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N	UART1_DSR_CTS_N	UART2_SOUT*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3	UART3_SIN*/ \
+{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N	EOT3/TC3	UART3_SOUT*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N	UART1_SOUT	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N	UART1_SIN	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3)				*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1)				*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2)				*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO43_USE, GPIO_OUT_0},/* GPIO43 CS(3)		DMAReq1		IRQ(10)*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4)		DMAAck1		IRQ(11)*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5)		EOT/TC1		IRQ(12)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5)	DMAReq0		IRQ(13)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6)	DMAAck0		IRQ(14)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7)	EOT/TC0		IRQ(15)*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit	*/	\
+}											\
+}
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/cardhu.h b/qemu/roms/u-boot/include/configs/cardhu.h
new file mode 100644
index 000000000..e15b52737
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/cardhu.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+
+#include "tegra30-common.h"
+
+/* Enable fdt support for Cardhu. Flash the image in u-boot-dtb.bin */
+#define CONFIG_DEFAULT_DEVICE_TREE	tegra30-cardhu
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
+/* High-level configuration options */
+#define V_PROMPT		"Tegra30 (Cardhu) # "
+#define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Cardhu"
+
+#define BOARD_EXTRA_ENV_SETTINGS \
+	"board_name=cardhu-a04\0" \
+	"fdtfile=tegra30-cardhu-a04.dtb\0"
+
+/* Board-specific serial config */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_TEGRA_ENABLE_UARTA
+#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_CARDHU
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* I2C */
+#define CONFIG_SYS_I2C_TEGRA
+#define CONFIG_SYS_I2C_INIT_BOARD
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_MAX_I2C_BUS		TEGRA_I2C_NUM_CONTROLLERS
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_TEGRA_MMC
+#define CONFIG_CMD_MMC
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART		2
+
+/* SPI */
+#define CONFIG_TEGRA20_SLINK
+#define CONFIG_TEGRA_SLINK_CTRLS       6
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SF_DEFAULT_MODE         SPI_MODE_0
+#define CONFIG_SF_DEFAULT_SPEED        24000000
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH_SIZE          (4 << 20)
+
+/* USB Host support */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_TEGRA
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB
+
+/* USB networking support */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+
+/* General networking support */
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/cgtqmx6eval.h b/qemu/roms/u-boot/include/configs/cgtqmx6eval.h
new file mode 100644
index 000000000..b189bf116
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/cgtqmx6eval.h
@@ -0,0 +1,180 @@
+/*
+ *
+ * Congatec Conga-QEVAl board configuration file.
+ *
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ * Based on Freescale i.MX6Q Sabre Lite board configuration file.
+ * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
+ * Leo Sartre, <lsartre@adeneo-embedded.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_CGTQMX6EVAL_H
+#define __CONFIG_CGTQMX6EVAL_H
+
+#define CONFIG_MX6
+
+#include "mx6_common.h"
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_MACH_TYPE	4122
+
+#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/gpio.h>
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MISC_INIT_R
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	       UART2_BASE
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR      0
+
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+/* Miscellaneous commands */
+#define CONFIG_CMD_BMODE
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX	       1
+#define CONFIG_BAUDRATE			       115200
+
+/* Command definition */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY	       3
+
+#define CONFIG_LOADADDR			       0x12000000
+#define CONFIG_SYS_TEXT_BASE	       0x17800000
+
+#define CONFIG_DEFAULT_FDT_FILE "imx6q-congatec.dtb"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"image=zImage\0" \
+	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"boot_dir=/boot\0" \
+	"console=ttymxc1\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_addr=0x18000000\0" \
+	"boot_fdt=try\0" \
+	"mmcdev=1\0" \
+	"mmcpart=1\0" \
+	"mmcroot=/dev/mmcblk0p1 rootwait rw\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \
+		"${boot_dir}/${image}\0" \
+	"loadfdt=ext2load mmc ${mmcdev}:${mmcpart} ${fdt_addr} " \
+		"${boot_dir}/${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	   "mmc dev ${mmcdev};" \
+	   "mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "else "\
+				   "echo ERR: Fail to boot from mmc; " \
+			   "fi; " \
+		   "fi; " \
+	   "else echo ERR: Fail to boot from mmc; fi"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT	       "CGT-QMX6-Quad U-Boot > "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE	       256
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	       16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START       0x10000000
+#define CONFIG_SYS_MEMTEST_END	       0x10010000
+#define CONFIG_SYS_MEMTEST_SCRATCH     0x10800000
+
+#define CONFIG_SYS_LOAD_ADDR	       CONFIG_LOADADDR
+
+#define CONFIG_CMDLINE_EDITING
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS	       1
+#define PHYS_SDRAM		       MMDC0_ARB_BASE_ADDR
+#define PHYS_SDRAM_SIZE			       (1u * 1024 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE	       PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_SIZE			(8 * 1024)
+
+#define CONFIG_ENV_IS_IN_MMC
+
+#define CONFIG_ENV_OFFSET		(6 * 64 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+#endif
+
+#endif			       /* __CONFIG_CGTQMX6EVAL_H */
diff --git a/qemu/roms/u-boot/include/configs/charon.h b/qemu/roms/u-boot/include/configs/charon.h
new file mode 100644
index 000000000..2f537e0d4
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/charon.h
@@ -0,0 +1,65 @@
+/*
+ * (C) Copyright 2003-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004-2006
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * (C) Copyright 2010
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_CHARON_H
+#define __CONFIG_CHARON_H
+
+#define CONFIG_CHARON
+#define CONFIG_HOSTNAME		charon
+
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x81550414
+
+/* include common defines/options for TQM52xx boards */
+#include "TQM5200.h"
+
+/* defines special on charon board */
+#undef CONFIG_RTC_MPC5200
+#undef CONFIG_CMD_DATE
+
+#undef CUSTOM_ENV_SETTINGS
+#define CUSTOM_ENV_SETTINGS					\
+	"bootfile=/tftpboot/charon/uImage\0"			\
+	"fdt_file=/tftpboot/charon/charon.dtb\0"		\
+	"u-boot=/tftpboot/charon/u-boot.bin\0"			\
+	"mtdparts=" MTDPARTS_DEFAULT "\0"			\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"
+
+
+/* additional features on charon board */
+#define CONFIG_RESET_PHY_R
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_I2C_MULTI_BUS
+
+#define CONFIG_SYS_TFP410_ADDR	0x38
+#define CONFIG_SYS_TFP410_BUS	0
+
+/*
+ * FPGA configuration
+ */
+#define CONFIG_SYS_CS3_START		0xE8000000
+#define CONFIG_SYS_CS3_SIZE		0x80000	/* 512 KByte */
+
+/*
+ * CS3 Config Register Init:
+ * 	CS3 Enabled
+ * 	AddrBus: 8bits
+ *  	DataBus: 4bytes
+ *  	Multiplexed: Yes
+ *  	MuxBank: 00
+ */
+#define CONFIG_SYS_CS3_CFG		0x00009310
+
+#endif /* __CONFIG_CHARON_H */
diff --git a/qemu/roms/u-boot/include/configs/cm-bf527.h b/qemu/roms/u-boot/include/configs/cm-bf527.h
new file mode 100644
index 000000000..8d3ae4991
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/cm-bf527.h
@@ -0,0 +1,138 @@
+/*
+ * U-boot - Configuration file for CM-BF527 board
+ */
+
+#ifndef __CONFIG_CM_BF527_H__
+#define __CONFIG_CM_BF527_H__
+
+#include <asm/config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU             bf527-0.0
+#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
+
+
+/*
+ * Clock Settings
+ *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz					*/
+#define CONFIG_CLKIN_HZ			25000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
+/*                                                1 = CLKIN / 2		*/
+#define CONFIG_CLKIN_HALF		0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
+/*                                                1 = bypass PLL	*/
+#define CONFIG_PLL_BYPASS		0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
+/* Values can range from 0-63 (where 0 means 64)			*/
+#define CONFIG_VCO_MULT			21
+/* CCLK_DIV controls the core clock divider				*/
+/* Values can be 1, 2, 4, or 8 ONLY					*/
+#define CONFIG_CCLK_DIV			1
+/* SCLK_DIV controls the system clock divider				*/
+/* Values can range from 1-15						*/
+#define CONFIG_SCLK_DIV			4
+
+/* Decrease core voltage */
+#define CONFIG_VR_CTL_VAL (VLEV_120 | CLKBUFOE | FREQ_1000)
+
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_ADD_WDTH	9
+#define CONFIG_MEM_SIZE		32
+
+#define CONFIG_EBIU_SDRRC_VAL	0x3f8
+#define CONFIG_EBIU_SDGCTL_VAL	0x9111cd
+
+#define CONFIG_EBIU_AMGCTL_VAL	(AMBEN_ALL)
+#define CONFIG_EBIU_AMBCTL0_VAL	(B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
+#define CONFIG_EBIU_AMBCTL1_VAL	(B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
+
+#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN	(128 * 1024)
+
+
+/*
+ * NAND Settings
+ * (can't be used sametime as ethernet)
+ */
+/* #define CONFIG_BFIN_NFC */
+#ifdef CONFIG_BFIN_NFC
+#define CONFIG_BFIN_NFC_CTL_VAL	0x0033
+#define CONFIG_SYS_NAND_BASE		0 /* not actually used */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_CMD_NAND
+#endif
+
+
+/*
+ * Network Settings
+ */
+#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__) && \
+    !defined(__ADSPBF524__) && !defined(__ADSPBF525__) && !defined(CONFIG_BFIN_NFC)
+#define ADI_CMDS_NETWORK	1
+#define CONFIG_BFIN_MAC
+#define CONFIG_RMII
+#define CONFIG_NETCONSOLE	1
+#endif
+#define CONFIG_HOSTNAME		cm-bf527
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR	02:80:ad:20:31:e8 */
+#define CONFIG_LIB_RAND
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define CONFIG_SYS_FLASH_BASE		0x20000000
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT 	67
+
+
+/*
+ * Env Storage Settings
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_ADDR		0x20008000
+#define CONFIG_ENV_OFFSET	0x8000
+#define CONFIG_ENV_SIZE		0x8000
+#define CONFIG_ENV_SECT_SIZE	0x8000
+#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
+
+
+/*
+ * I2C Settings
+ */
+#define CONFIG_BFIN_TWI_I2C	1
+#define CONFIG_HARD_I2C		1
+
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_MISC_INIT_R
+#define CONFIG_RTC_BFIN
+#define CONFIG_UART_CONSOLE	0
+#define CONFIG_BOOTCOMMAND	"run flashboot"
+#define FLASHBOOT_ENV_SETTINGS \
+	"flashboot=flread 20040000 1000000 300000;" \
+	"bootm 0x1000000\0"
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/cm-bf533.h b/qemu/roms/u-boot/include/configs/cm-bf533.h
new file mode 100644
index 000000000..8bd499a7d
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/cm-bf533.h
@@ -0,0 +1,107 @@
+/*
+ * U-boot - Configuration file for CM-BF533 board
+ */
+
+#ifndef __CONFIG_CM_BF533_H__
+#define __CONFIG_CM_BF533_H__
+
+#include <asm/config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU             bf533-0.3
+#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
+
+
+/*
+ * Clock Settings
+ *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz					*/
+#define CONFIG_CLKIN_HZ			25000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
+/*                                                1 = CLKIN / 2		*/
+#define CONFIG_CLKIN_HALF		0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
+/*                                                1 = bypass PLL	*/
+#define CONFIG_PLL_BYPASS		0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
+/* Values can range from 0-63 (where 0 means 64)			*/
+#define CONFIG_VCO_MULT			22
+/* CCLK_DIV controls the core clock divider				*/
+/* Values can be 1, 2, 4, or 8 ONLY					*/
+#define CONFIG_CCLK_DIV			1
+/* SCLK_DIV controls the system clock divider				*/
+/* Values can range from 1-15						*/
+#define CONFIG_SCLK_DIV			5
+
+/* Decrease core voltage */
+#define CONFIG_VR_CTL_VAL (VLEV_115 | GAIN_20 | FREQ_1000)
+
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_ADD_WDTH	9
+#define CONFIG_MEM_SIZE		32
+
+#define CONFIG_EBIU_SDRRC_VAL	((((CONFIG_SCLK_HZ / 1000) * 64) / 8192) - (7 + 2))
+#define CONFIG_EBIU_SDGCTL_VAL	(SCTLE | PSS | TWR_2 | TRCD_2 | TRP_2 | TRAS_7 | PASR_ALL | CL_3)
+
+#define CONFIG_EBIU_AMGCTL_VAL	(AMBEN_ALL)
+#define CONFIG_EBIU_AMBCTL0_VAL	(B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
+#define CONFIG_EBIU_AMBCTL1_VAL	(B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
+
+#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN	(128 * 1024)
+
+
+/*
+ * Network Settings
+ */
+#define ADI_CMDS_NETWORK	1
+#define CONFIG_SMC91111	1
+#define CONFIG_SMC91111_BASE	0x20200300
+#define CONFIG_HOSTNAME		cm-bf533
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR	02:80:ad:20:31:e8 */
+
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_BASE		0x20000000
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	16
+
+
+/*
+ * Env Storage Settings
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_OFFSET	0x20000
+#define CONFIG_ENV_SECT_SIZE	0x20000
+#define CONFIG_ENV_SIZE		0x10000
+
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_UART_CONSOLE	0
+#define CONFIG_BOOTCOMMAND	"run flashboot"
+#define FLASHBOOT_ENV_SETTINGS	"flashboot=bootm 0x20040000\0"
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/cm-bf537e.h b/qemu/roms/u-boot/include/configs/cm-bf537e.h
new file mode 100644
index 000000000..47967d712
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/cm-bf537e.h
@@ -0,0 +1,156 @@
+/*
+ * U-boot - Configuration file for CM-BF537E board
+ */
+
+#ifndef __CONFIG_CM_BF537E_H__
+#define __CONFIG_CM_BF537E_H__
+
+#include <asm/config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU             bf537-0.2
+#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
+
+
+/*
+ * Clock Settings
+ *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz					*/
+#define CONFIG_CLKIN_HZ			25000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
+/*                                                1 = CLKIN / 2		*/
+#define CONFIG_CLKIN_HALF		0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
+/*                                                1 = bypass PLL	*/
+#define CONFIG_PLL_BYPASS		0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
+/* Values can range from 0-63 (where 0 means 64)			*/
+#define CONFIG_VCO_MULT			21
+/* CCLK_DIV controls the core clock divider				*/
+/* Values can be 1, 2, 4, or 8 ONLY					*/
+#define CONFIG_CCLK_DIV			1
+/* SCLK_DIV controls the system clock divider				*/
+/* Values can range from 1-15						*/
+#define CONFIG_SCLK_DIV			4
+
+/* Decrease core voltage */
+#define CONFIG_VR_CTL_VAL (VLEV_115 | CLKBUFOE | GAIN_20 | FREQ_1000)
+
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_ADD_WDTH	9
+#define CONFIG_MEM_SIZE		32
+
+#define CONFIG_EBIU_SDRRC_VAL	0x3f8
+#define CONFIG_EBIU_SDGCTL_VAL	0x9111cd
+
+#define CONFIG_EBIU_AMGCTL_VAL	(AMBEN_ALL)
+#define CONFIG_EBIU_AMBCTL0_VAL	(B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
+#define CONFIG_EBIU_AMBCTL1_VAL	(B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
+
+#define CONFIG_SYS_MONITOR_LEN	(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN	(128 * 1024)
+
+
+/*
+ * Network Settings
+ */
+#ifndef __ADSPBF534__
+#define ADI_CMDS_NETWORK	1
+#define CONFIG_BFIN_MAC
+#define CONFIG_SMC911X		1
+#define CONFIG_SMC911X_BASE	0x20308000
+#define CONFIG_SMC911X_16_BIT
+#define CONFIG_NETCONSOLE	1
+#endif
+#define CONFIG_HOSTNAME		cm-bf537e
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR	02:80:ad:20:31:e8 */
+#define CONFIG_LIB_RAND
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define CONFIG_SYS_FLASH_BASE		0x20000000
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	35
+
+
+/*
+ * SPI Settings
+ */
+#define CONFIG_BFIN_SPI
+#define CONFIG_ENV_SPI_MAX_HZ	30000000
+
+
+/*
+ * Env Storage Settings
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_OFFSET	0x8000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_SECT_SIZE	0x8000
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
+#define ENV_IS_EMBEDDED
+#endif
+#ifdef ENV_IS_EMBEDDED
+/* WARNING - the following is hand-optimized to fit within
+ * the sector before the environment sector. If it throws
+ * an error during compilation remove an object here to get
+ * it linked after the configuration sector.
+ */
+# define LDS_BOARD_TEXT \
+	arch/blackfin/lib/built-in.o (.text*); \
+	arch/blackfin/cpu/built-in.o (.text*); \
+	. = DEFINED(env_offset) ? env_offset : .; \
+	common/env_embedded.o (.text*);
+#endif
+
+
+/*
+ * I2C Settings
+ */
+#define CONFIG_BFIN_TWI_I2C	1
+#define CONFIG_HARD_I2C		1
+
+
+/*
+ * SPI_MMC Settings
+ */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC_SPI
+
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_MISC_INIT_R
+#define CONFIG_RTC_BFIN
+#define CONFIG_UART_CONSOLE	0
+#define CONFIG_BOOTCOMMAND	"run flashboot"
+#define FLASHBOOT_ENV_SETTINGS \
+	"flashboot=flread 20040000 1000000 3c0000;" \
+	"bootm 0x1000000\0"
+#define CONFIG_BOARD_SIZE_LIMIT $$((384 * 1024))
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/cm-bf537u.h b/qemu/roms/u-boot/include/configs/cm-bf537u.h
new file mode 100644
index 000000000..88c99821b
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/cm-bf537u.h
@@ -0,0 +1,153 @@
+/*
+ * U-boot - Configuration file for CM-BF537U board
+ */
+
+#ifndef __CONFIG_CM_BF537U_H__
+#define __CONFIG_CM_BF537U_H__
+
+#include <asm/config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU             bf537-0.2
+#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
+
+
+/*
+ * Clock Settings
+ *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz					*/
+#define CONFIG_CLKIN_HZ			30000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
+/*                                                1 = CLKIN / 2		*/
+#define CONFIG_CLKIN_HALF		0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
+/*                                                1 = bypass PLL	*/
+#define CONFIG_PLL_BYPASS		0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
+/* Values can range from 0-63 (where 0 means 64)			*/
+#define CONFIG_VCO_MULT			18
+/* CCLK_DIV controls the core clock divider				*/
+/* Values can be 1, 2, 4, or 8 ONLY					*/
+#define CONFIG_CCLK_DIV			1
+/* SCLK_DIV controls the system clock divider				*/
+/* Values can range from 1-15						*/
+#define CONFIG_SCLK_DIV			5
+/* Core voltage */
+#define CONFIG_VR_CTL_VAL (VLEV_110 | GAIN_20 | FREQ_1000)
+
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_ADD_WDTH	9
+#define CONFIG_MEM_SIZE		32
+
+#define CONFIG_EBIU_SDRRC_VAL	0x3f8
+#define CONFIG_EBIU_SDGCTL_VAL	0x9111cd
+
+#define CONFIG_EBIU_AMGCTL_VAL	(AMBEN_ALL)
+#define CONFIG_EBIU_AMBCTL0_VAL	(B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
+#define CONFIG_EBIU_AMBCTL1_VAL	(B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
+
+#define CONFIG_SYS_MONITOR_LEN	(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN	(128 * 1024)
+
+
+/*
+ * Network Settings
+ */
+#ifndef __ADSPBF534__
+#define ADI_CMDS_NETWORK	1
+#define CONFIG_SMC911X		1
+#define CONFIG_SMC911X_BASE	0x20308000
+#define CONFIG_SMC911X_16_BIT
+#define CONFIG_NETCONSOLE	1
+#endif
+#define CONFIG_HOSTNAME		cm-bf537u
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR	02:80:ad:20:31:e8 */
+#define CONFIG_LIB_RAND
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define CONFIG_SYS_FLASH_BASE		0x20000000
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	35
+
+
+/*
+ * SPI Settings
+ */
+#define CONFIG_BFIN_SPI
+#define CONFIG_ENV_SPI_MAX_HZ	30000000
+
+
+/*
+ * Env Storage Settings
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_OFFSET	0x8000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_SECT_SIZE	0x8000
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
+#define ENV_IS_EMBEDDED
+#endif
+#ifdef ENV_IS_EMBEDDED
+/* WARNING - the following is hand-optimized to fit within
+ * the sector before the environment sector. If it throws
+ * an error during compilation remove an object here to get
+ * it linked after the configuration sector.
+ */
+# define LDS_BOARD_TEXT \
+	arch/blackfin/lib/built-in.o (.text*); \
+	arch/blackfin/cpu/built-in.o (.text*); \
+	. = DEFINED(env_offset) ? env_offset : .; \
+	common/env_embedded.o (.text*);
+#endif
+
+
+/*
+ * I2C Settings
+ */
+#define CONFIG_BFIN_TWI_I2C	1
+#define CONFIG_HARD_I2C		1
+
+
+/*
+ * SPI_MMC Settings
+ */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC_SPI
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_MISC_INIT_R
+#define CONFIG_RTC_BFIN
+#define CONFIG_UART_CONSOLE	0
+#define CONFIG_BOOTCOMMAND	"run flashboot"
+#define FLASHBOOT_ENV_SETTINGS \
+	"flashboot=flread 20040000 1000000 300000;" \
+	"bootm 0x1000000\0"
+#define CONFIG_BOARD_SIZE_LIMIT $$((384 * 1024))
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/cm-bf548.h b/qemu/roms/u-boot/include/configs/cm-bf548.h
new file mode 100644
index 000000000..346e27f3e
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/cm-bf548.h
@@ -0,0 +1,146 @@
+/*
+ * U-boot - Configuration file for cm-bf548 board
+ */
+
+#ifndef __CONFIG_CM_BF548_H__
+#define __CONFIG_CM_BF548_H__
+
+#include <asm/config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU             bf548-0.0
+#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
+
+
+/*
+ * Clock Settings
+ *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz					*/
+#define CONFIG_CLKIN_HZ			25000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
+/*                                                1 = CLKIN / 2		*/
+#define CONFIG_CLKIN_HALF		0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
+/*                                                1 = bypass PLL	*/
+#define CONFIG_PLL_BYPASS		0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
+/* Values can range from 0-63 (where 0 means 64)			*/
+#define CONFIG_VCO_MULT			21
+/* CCLK_DIV controls the core clock divider				*/
+/* Values can be 1, 2, 4, or 8 ONLY					*/
+#define CONFIG_CCLK_DIV			1
+/* SCLK_DIV controls the system clock divider				*/
+/* Values can range from 1-15						*/
+#define CONFIG_SCLK_DIV			4
+
+/* Decrease core voltage */
+#define CONFIG_VR_CTL_VAL (VLEV_115 | GAIN_20 | FREQ_1000)
+
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_ADD_WDTH	10
+#define CONFIG_MEM_SIZE		64
+
+#define CONFIG_EBIU_DDRCTL0_VAL	0x218A83FE
+#define CONFIG_EBIU_DDRCTL1_VAL	0x20022222
+#define CONFIG_EBIU_DDRCTL2_VAL	0x00000021
+
+/* Default bank mapping:
+ *	Async Bank 0 - 32MB Burst Flash
+ *	Async Bank 1 - Ethernet
+ *	Async Bank 2 - Nothing
+ *	Async Bank 3 - Nothing
+ */
+#define CONFIG_EBIU_AMGCTL_VAL	0xFF
+#define CONFIG_EBIU_AMBCTL0_VAL	0x7BB07BB0
+#define CONFIG_EBIU_AMBCTL1_VAL	0xFFC27BB0
+#define CONFIG_EBIU_FCTL_VAL	(BCLK_4)
+#define CONFIG_EBIU_MODE_VAL	(B0MODE_FLASH)
+
+#define CONFIG_SYS_MONITOR_LEN	(512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN	(640 * 1024)
+
+
+/*
+ * Network Settings
+ */
+#define ADI_CMDS_NETWORK	1
+#define CONFIG_SMC911X	1
+#define CONFIG_SMC911X_BASE	0x24000000
+#define CONFIG_SMC911X_16_BIT
+#define CONFIG_HOSTNAME		cm-bf548
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR	02:80:ad:24:31:91 */
+
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_BASE		0x20000000
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	259
+
+
+/*
+ * Env Storage Settings
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_ADDR		0x20008000
+#define CONFIG_ENV_OFFSET	0x8000
+#define CONFIG_ENV_SIZE		0x8000
+#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
+
+
+/*
+ * I2C Settings
+ */
+#define CONFIG_BFIN_TWI_I2C	1
+#define CONFIG_HARD_I2C		1
+
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_RTC_BFIN
+#define CONFIG_UART_CONSOLE	1
+#define CONFIG_BOOTCOMMAND	"run flashboot"
+#define FLASHBOOT_ENV_SETTINGS	"flashboot=bootm 0x20040000\0"
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
+
+#define CONFIG_ADI_GPIO2
+
+#ifndef __ADSPBF542__
+/* Don't waste time transferring a logo over the UART */
+# if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART)
+#  define CONFIG_VIDEO
+#  define EASYLOGO_HEADER <asm/bfin_logo_230x230_gzip.h>
+# endif
+# define CONFIG_DEB_DMA_URGENT
+#endif
+
+/* Define if want to do post memory test */
+#undef CONFIG_POST
+#ifdef CONFIG_POST
+#define FLASH_START_POST_BLOCK 11       /* Should > = 11 */
+#define FLASH_END_POST_BLOCK   71       /* Should < = 71 */
+#endif
+
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/cm-bf561.h b/qemu/roms/u-boot/include/configs/cm-bf561.h
new file mode 100644
index 000000000..5265e5f6e
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/cm-bf561.h
@@ -0,0 +1,109 @@
+/*
+ * U-boot - Configuration file for CM-BF561 board
+ */
+
+#ifndef __CONFIG_CM_BF561_H__
+#define __CONFIG_CM_BF561_H__
+
+#include <asm/config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU             bf561-0.3
+#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
+
+
+/*
+ * Clock Settings
+ *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz					*/
+#define CONFIG_CLKIN_HZ			25000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
+/*                                                1 = CLKIN / 2		*/
+#define CONFIG_CLKIN_HALF		0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
+/*                                                1 = bypass PLL	*/
+#define CONFIG_PLL_BYPASS		0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
+/* Values can range from 0-63 (where 0 means 64)			*/
+#define CONFIG_VCO_MULT			20
+/* CCLK_DIV controls the core clock divider				*/
+/* Values can be 1, 2, 4, or 8 ONLY					*/
+#define CONFIG_CCLK_DIV			1
+/* SCLK_DIV controls the system clock divider				*/
+/* Values can range from 1-15						*/
+#define CONFIG_SCLK_DIV			5
+
+/* Decrease core voltage */
+#define CONFIG_VR_CTL_VAL (VLEV_110 | GAIN_20 | FREQ_1000)
+
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_ADD_WDTH	9
+#define CONFIG_MEM_SIZE		64
+
+#define CONFIG_EBIU_SDRRC_VAL	((((CONFIG_SCLK_HZ / 1000) * 64) / 4096) - (7 + 2))
+#define CONFIG_EBIU_SDGCTL_VAL	(SCTLE | PSS | TWR_2 | TRCD_2 | TRP_2 | TRAS_7 | PASR_ALL | CL_3)
+
+#define CONFIG_EBIU_AMGCTL_VAL	(CDPRIO | B3_PEN | B2_PEN | B1_PEN | B0_PEN | AMBEN_ALL | AMCKEN)
+#define CONFIG_EBIU_AMBCTL0_VAL	(B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
+#define CONFIG_EBIU_AMBCTL1_VAL	(B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
+
+#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN	(128 * 1024)
+
+
+/*
+ * Network Settings
+ */
+#define ADI_CMDS_NETWORK	1
+#define CONFIG_SMC911X		1
+#define CONFIG_SMC911X_BASE	0x24008000 /* AMS1 */
+#define CONFIG_SMC911X_16_BIT
+#define CONFIG_HOSTNAME		cm-bf561
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR	02:80:ad:20:31:cf */
+
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_BASE		0x20000000
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	67
+
+
+/*
+ * Env Storage Settings
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_OFFSET	0x20000
+#define CONFIG_ENV_SECT_SIZE	0x20000
+#define CONFIG_ENV_SIZE		0x10000
+#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
+
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_UART_CONSOLE	0
+#define CONFIG_BOOTCOMMAND	"run flashboot"
+#define FLASHBOOT_ENV_SETTINGS	"flashboot=bootm 0x20040000\0"
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/cm4008.h b/qemu/roms/u-boot/include/configs/cm4008.h
new file mode 100644
index 000000000..1cb54b322
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/cm4008.h
@@ -0,0 +1,104 @@
+/*
+ * (C) Copyright 2004
+ * Greg Ungerer <greg.ungerer@opengear.com>.
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_KS8695	1		/* it is a KS8695 CPU */
+#define CONFIG_CM4008	1		/* it is an OpenGear CM4008 boad */
+
+#define CONFIG_CMDLINE_TAG	 1	/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG	 1
+
+#define CONFIG_DRIVER_KS8695ETH		/* use KS8695 ethernet driver	*/
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_KS8695_SERIAL
+#define	CONFIG_SERIAL1
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		115200
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_SAVEENV
+
+
+#define CONFIG_BOOTDELAY	0
+#define CONFIG_BOOTARGS		"mem=16M console=ttyAM0,115200"
+#define CONFIG_BOOTCOMMAND	"gofsk 0x02200000"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT		"boot > "	/* Monitor Command Prompt	*/
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x00800000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x01000000	/* 16 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x00008000	/* default load address */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1		0x00000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x01000000 /* 16 MB */
+#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_1
+
+#define CONFIG_SYS_INIT_SP_ADDR	0x00020000 /* lowest 128k of RAM */
+
+#define PHYS_FLASH_1		0x02000000 /* Flash Bank #1 */
+#define PHYS_FLASH_SECT_SIZE    0x00020000 /* 128 KB sectors (x1) */
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	(128)	/* max number of sectors on one chip */
+
+/* timeout values are in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
+
+#define CONFIG_ENV_SIZE		0x20000     /* Total Size of Environment */
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/cm41xx.h b/qemu/roms/u-boot/include/configs/cm41xx.h
new file mode 100644
index 000000000..adebd4b7b
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/cm41xx.h
@@ -0,0 +1,104 @@
+/*
+ * (C) Copyright 2005
+ * Greg Ungerer <greg.ungerer@opengear.com>.
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_KS8695	1		/* it is a KS8695 CPU */
+#define CONFIG_CM41xx	1		/* it is an OpenGear CM41xx boad */
+
+#define CONFIG_CMDLINE_TAG	 1	/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG	 1
+
+#define CONFIG_DRIVER_KS8695ETH		/* use KS8695 ethernet driver	*/
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_KS8695_SERIAL
+#define	CONFIG_SERIAL1
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		115200
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_SAVEENV
+
+
+#define CONFIG_BOOTDELAY	0
+#define CONFIG_BOOTARGS		"mem=32M console=ttyAM0,115200"
+#define CONFIG_BOOTCOMMAND	"gofsk 0x02200000"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT		"boot > "	/* Monitor Command Prompt	*/
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x00800000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x01000000	/* 16 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x00008000	/* default load address */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1		0x00000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x02000000 /* 32 MB */
+#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_1
+
+#define CONFIG_SYS_INIT_SP_ADDR	0x00020000 /* lowest 128k of RAM */
+
+#define PHYS_FLASH_1		0x02000000 /* Flash Bank #1 */
+#define PHYS_FLASH_SECT_SIZE    0x00020000 /* 128 KB sectors (x1) */
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	(128)	/* max number of sectors on one chip */
+
+/* timeout values are in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
+
+#define CONFIG_ENV_SIZE		0x20000     /* Total Size of Environment */
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/cm5200.h b/qemu/roms/u-boot/include/configs/cm5200.h
new file mode 100644
index 000000000..7c693d62d
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/cm5200.h
@@ -0,0 +1,324 @@
+/*
+ * (C) Copyright 2003-2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_MPC5200		1	/* This is an MPC5200 CPU */
+#define CONFIG_CM5200		1	/* ... on CM5200 platform */
+
+#define	CONFIG_SYS_TEXT_BASE	0xfc000000
+
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
+/*
+ * Supported commands
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_USB
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
+#define CONFIG_BAUDRATE		57600	/* ... at 57600 bps */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SILENT_CONSOLE	1	/* needed to silence i2c_init() */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC	1
+#define CONFIG_MPC5xxx_FEC_MII100
+#define CONFIG_PHY_ADDR		0x00
+#define CONFIG_ENV_OVERWRITE	1	/* allow overwriting of ethaddr */
+/* use misc_init_r() to read ethaddr from I2C EEPROM (see CONFIG_SYS_I2C_EEPROM) */
+#define CONFIG_MISC_INIT_R	1
+#define CONFIG_MAC_OFFSET	0x35	/* MAC address offset in I2C EEPROM */
+
+/*
+ * POST support
+ */
+#define CONFIG_POST		(CONFIG_SYS_POST_MEMORY | CONFIG_SYS_POST_CPU | CONFIG_SYS_POST_I2C)
+#define MPC5XXX_SRAM_POST_SIZE	(MPC5XXX_SRAM_SIZE - 4)
+/* List of I2C addresses to be verified by POST */
+#define CONFIG_SYS_POST_I2C_ADDRS	{CONFIG_SYS_I2C_SLAVE,	\
+					 CONFIG_SYS_I2C_IO,	\
+					 CONFIG_SYS_I2C_EEPROM}
+
+/* display image timestamps */
+#define CONFIG_TIMESTAMP	1
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+#define CONFIG_PREBOOT	"echo;" \
+	"echo Type \"run net_nfs_fdt\" to mount root filesystem over NFS;" \
+	"echo"
+#undef CONFIG_BOOTARGS
+
+/*
+ * Default environment settings
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"netmask=255.255.0.0\0"						\
+	"ipaddr=192.168.160.33\0"					\
+	"serverip=192.168.1.1\0"					\
+	"gatewayip=192.168.1.1\0"					\
+	"console=ttyPSC0\0"						\
+	"u-boot_addr=100000\0"						\
+	"kernel_addr=200000\0"						\
+	"kernel_addr_flash=fc0c0000\0"					\
+	"fdt_addr=400000\0"						\
+	"fdt_addr_flash=fc0a0000\0"					\
+	"ramdisk_addr=500000\0"						\
+	"rootpath=/opt/eldk-4.1/ppc_6xx\0"				\
+	"u-boot=/tftpboot/cm5200/u-boot.bin\0"				\
+	"bootfile_fdt=/tftpboot/cm5200/uImage\0"			\
+	"fdt_file=/tftpboot/cm5200/cm5200.dtb\0"			\
+	"load=tftp ${u-boot_addr} ${u-boot}\0"				\
+	"update=prot off fc000000 +${filesize}; "			\
+		"era fc000000 +${filesize}; "				\
+		"cp.b ${u-boot_addr} fc000000 ${filesize}; "		\
+		"prot on fc000000 +${filesize}\0"			\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"flashargs=setenv bootargs root=/dev/mtdblock5 rw\0"		\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
+	"addinit=setenv bootargs ${bootargs} init=/linuxrc\0"		\
+	"addcons=setenv bootargs ${bootargs} "				\
+		"console=${console},${baudrate}\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:"		\
+		"${netmask}:${hostname}:${netdev}:off panic=1\0"	\
+	"flash_flash=run flashargs addinit addip addcons;"		\
+		"bootm ${kernel_addr_flash} - ${fdt_addr_flash}\0"	\
+	"net_nfs_fdt=tftp ${kernel_addr} ${bootfile_fdt}; "		\
+		"tftp ${fdt_addr} ${fdt_file}; run nfsargs addip "	\
+		"addcons; bootm ${kernel_addr} - ${fdt_addr}\0"		\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_flash"
+
+/*
+ * Low level configuration
+ */
+
+/*
+ * Clock configuration
+ */
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000	/* SYS_XTAL_IN = 33MHz */
+#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK	1	/* IPB = 133MHz */
+
+/*
+ * Memory map
+ */
+#define CONFIG_SYS_MBAR		0xF0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
+
+#define CONFIG_SYS_LOWBOOT		1
+
+/* Use ON-Chip SRAM until RAM will be available */
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+#ifdef CONFIG_POST
+/* preserve space for the post_word at end of on-chip SRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_POST_SIZE
+#else
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
+#endif
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_BOARD_TYPES	1	/* we use board_type */
+
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(384 << 10)	/* 384 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* 256 kB for malloc() */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* initial mem map for Linux */
+
+/*
+ * Flash configuration
+ */
+#define CONFIG_SYS_FLASH_CFI		1
+#define CONFIG_FLASH_CFI_DRIVER	1
+#define CONFIG_SYS_FLASH_BASE		0xfc000000
+/* we need these despite using CFI */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max num of sectors on one chip */
+#define CONFIG_SYS_FLASH_SIZE		0x02000000 /* 32 MiB */
+
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT		1
+#undef CONFIG_SYS_LOWBOOT
+#endif
+
+
+/*
+ * Chip selects configuration
+ */
+/* Boot Chipselect */
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_CFG		0x00087D31	/* for pci_clk = 33 MHz */
+/* use board_early_init_r to enable flash write in CS_BOOT */
+#define CONFIG_BOARD_EARLY_INIT_R
+
+/* Flash memory addressing */
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
+
+/* No burst, dead cycle = 1 for CS0 (Flash) */
+#define CONFIG_SYS_CS_BURST		0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE	0x00000001
+
+/*
+ * SDRAM configuration
+ * settings for k4s561632E-xx75, assuming XLB = 132 MHz
+ */
+#define SDRAM_MODE	0x00CD0000	/* CASL 3, burst length 8 */
+#define SDRAM_CONTROL	0x514F0000
+#define SDRAM_CONFIG1	0xE2333900
+#define SDRAM_CONFIG2	0x8EE70000
+
+/*
+ * MTD configuration
+ */
+#define CONFIG_CMD_MTDPARTS	1
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
+#define MTDIDS_DEFAULT		"nor0=cm5200-0"
+#define MTDPARTS_DEFAULT	"mtdparts=cm5200-0:"			\
+					"384k(uboot),128k(env),"	\
+					"128k(redund_env),128k(dtb),"	\
+					"2m(kernel),27904k(rootfs),"	\
+					"-(config)"
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #2 */
+#define CONFIG_SYS_I2C_SPEED		40000	/* 40 kHz */
+#define CONFIG_SYS_I2C_SLAVE		0x0
+#define CONFIG_SYS_I2C_IO		0x38	/* PCA9554AD I2C I/O port address */
+#define CONFIG_SYS_I2C_EEPROM		0x53	/* I2C EEPROM device address */
+
+/*
+ * RTC configuration
+ */
+#define CONFIG_RTC_MPC5200	1	/* use internal MPC5200 RTC */
+
+/*
+ * USB configuration
+ */
+#define CONFIG_USB_OHCI		1
+#define CONFIG_USB_STORAGE	1
+#define CONFIG_USB_CLOCK	0x0001BBBB
+#define CONFIG_USB_CONFIG	0x00001000
+/* Partitions (for USB) */
+#define CONFIG_MAC_PARTITION	1
+#define CONFIG_DOS_PARTITION	1
+#define CONFIG_ISO_PARTITION	1
+
+/*
+ * Invoke our last_stage_init function - needed by fwupdate
+ */
+#define CONFIG_LAST_STAGE_INIT	1
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_SIZE		0x10000
+#define CONFIG_ENV_SECT_SIZE	0x20000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
+/* Configuration of redundant environment */
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+/*
+ * Pin multiplexing configuration
+ */
+
+/*
+ * CS1/GPIO_WKUP_6: GPIO (default)
+ * ALTs: CAN1 on I2C1, CAN2 on TIMER0/1
+ * IRDA/PSC6: UART
+ * Ether: Ethernet 100Mbit with MD
+ * PCI_DIS: PCI controller disabled
+ * USB: USB
+ * PSC3: SPI with UART3
+ * PSC2: UART
+ * PSC1: UART
+ */
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x10559C44
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		1	/* undef to save memory */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_ALT_MEMTEST		1
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x03f00000	/* 1 .. 63 MiB in SDRAM */
+
+#define CONFIG_LOOPW		1
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
+
+/*
+ * Various low-level settings
+ */
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
+
+#define CONFIG_SYS_XLB_PIPELINING	1	/* enable transaction pipeling */
+
+/*
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*
+ * Flat Device Tree support
+ */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define OF_CPU			"PowerPC,5200@0"
+#define OF_SOC			"soc5200@f0000000"
+#define OF_TBCLK		(bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH		"/soc5200@f0000000/serial@2000"
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/cm_t335.h b/qemu/roms/u-boot/include/configs/cm_t335.h
new file mode 100644
index 000000000..26b615b8c
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/cm_t335.h
@@ -0,0 +1,181 @@
+/*
+ * Config file for Compulab CM-T335 board
+ *
+ * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Ilya Ledvich <ilya@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_CM_T335_H
+#define __CONFIG_CM_T335_H
+
+#define CONFIG_CM_T335
+#define CONFIG_NAND
+
+#include <configs/ti_am335x_common.h>
+
+#undef CONFIG_BOARD_LATE_INIT
+#undef CONFIG_SPI
+#undef CONFIG_OMAP3_SPI
+#undef CONFIG_CMD_SPI
+#undef CONFIG_SPL_OS_BOOT
+#undef CONFIG_BOOTCOUNT_LIMIT
+#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
+
+#undef CONFIG_MAX_RAM_BANK_SIZE
+#define CONFIG_MAX_RAM_BANK_SIZE	(512 << 20)	/* 512MB */
+
+#undef CONFIG_SYS_PROMPT
+#define CONFIG_SYS_PROMPT		"CM-T335 # "
+
+#define CONFIG_OMAP_COMMON
+
+#define MACH_TYPE_CM_T335		4586	/* Until the next sync */
+#define CONFIG_MACH_TYPE		MACH_TYPE_CM_T335
+
+/* Clock Defines */
+#define V_OSCK				25000000  /* Clock output from T2 */
+#define V_SCLK				(V_OSCK)
+
+#define CONFIG_ENV_SIZE			(16 << 10)	/* 16 KiB */
+
+#ifndef CONFIG_SPL_BUILD
+#define MMCARGS \
+	"mmcdev=0\0" \
+	"mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
+	"mmcrootfstype=ext4\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0"
+
+#define NANDARGS \
+	"mtdids=" MTDIDS_DEFAULT "\0" \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"nandroot=ubi0:rootfs rw\0" \
+	"nandrootfstype=ubifs\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"root=${nandroot} " \
+		"rootfstype=${nandrootfstype} " \
+		"ubi.mtd=${rootfs_name}\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nboot ${loadaddr} nand0 900000; " \
+		"bootm ${loadaddr}\0"
+
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=82000000\0" \
+	"console=ttyO0,115200n8\0" \
+	"rootfs_name=rootfs\0" \
+	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source ${loadaddr}\0" \
+	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+	MMCARGS \
+	NANDARGS
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loaduimage; then " \
+				"run mmcboot; " \
+			"else run nandboot; " \
+			"fi; " \
+		"fi; " \
+	"else run nandboot; fi"
+#endif /* CONFIG_SPL_BUILD */
+
+#define CONFIG_TIMESTAMP
+#define CONFIG_SYS_AUTOLOAD		"no"
+
+/* Serial console configuration */
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SERIAL1			1	/* UART0 */
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550_COM1		0x44e09000	/* UART0 */
+#define CONFIG_SYS_NS16550_COM2		0x48022000	/* UART1 */
+#define CONFIG_BAUDRATE			115200
+
+/* I2C Configuration */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* Main EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+
+/* SPL */
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/am33xx/u-boot-spl.lds"
+
+/* Network. */
+#define CONFIG_PHY_GIGE
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ATHEROS
+
+/* NAND support */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
+					 CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
+					 10, 11, 12, 13, 14, 15, 16, 17, \
+					 18, 19, 20, 21, 22, 23, 24, 25, \
+					 26, 27, 28, 29, 30, 31, 32, 33, \
+					 34, 35, 36, 37, 38, 39, 40, 41, \
+					 42, 43, 44, 45, 46, 47, 48, 49, \
+					 50, 51, 52, 53, 54, 55, 56, 57, }
+
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	14
+
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+
+#undef CONFIG_SYS_NAND_U_BOOT_OFFS
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x200000
+
+#define CONFIG_CMD_NAND
+#define GPMC_NAND_ECC_LP_x8_LAYOUT
+#define MTDIDS_DEFAULT			"nand0=nand"
+#define MTDPARTS_DEFAULT		"mtdparts=nand:2m(spl)," \
+					"1m(u-boot),1m(u-boot-env)," \
+					"1m(dtb),4m(splash)," \
+					"6m(kernel),-(rootfs)"
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		0x300000 /* environment starts here */
+#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* GPIO pin + bank to pin ID mapping */
+#define GPIO_PIN(_bank, _pin)		((_bank << 5) + _pin)
+
+/* Status LED */
+#define CONFIG_STATUS_LED
+#define CONFIG_GPIO_LED
+#define CONFIG_BOARD_SPECIFIC_LED
+#define STATUS_LED_BIT			GPIO_PIN(2, 0)
+/* Status LED polarity is inversed, so init it in the "off" state */
+#define STATUS_LED_STATE		STATUS_LED_OFF
+#define STATUS_LED_PERIOD		(CONFIG_SYS_HZ / 2)
+#define STATUS_LED_BOOT			0
+
+#ifndef CONFIG_SPL_BUILD
+/*
+ * Enable PCA9555 at I2C0-0x26.
+ * First select the I2C0 bus with "i2c dev 0", then use "pca953x" command.
+ */
+#define CONFIG_PCA953X
+#define CONFIG_CMD_PCA953X
+#define CONFIG_CMD_PCA953X_INFO
+#define CONFIG_SYS_I2C_PCA953X_ADDR	0x26
+#define CONFIG_SYS_I2C_PCA953X_WIDTH	{ {0x26, 16} }
+#endif /* CONFIG_SPL_BUILD */
+
+#endif	/* __CONFIG_CM_T335_H */
+
diff --git a/qemu/roms/u-boot/include/configs/cm_t35.h b/qemu/roms/u-boot/include/configs/cm_t35.h
new file mode 100644
index 000000000..aae05e033
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/cm_t35.h
@@ -0,0 +1,387 @@
+/*
+ * (C) Copyright 2011 CompuLab, Ltd.
+ * Mike Rapoport <mike@compulab.co.il>
+ * Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * Based on omap3_beagle.h
+ * (C) Copyright 2006-2008
+ * Texas Instruments.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_OMAP	/* in a TI OMAP core */
+#define CONFIG_OMAP34XX	/* which is a 34XX */
+#define CONFIG_OMAP_GPIO
+#define CONFIG_CMD_GPIO
+#define CONFIG_CM_T3X	/* working with CM-T35 and CM-T3730 */
+#define CONFIG_OMAP_COMMON
+
+#define CONFIG_SDRC	/* The chip has SDRC controller */
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Clock Defines */
+#define V_OSCK			26000000	/* Clock output from T2 */
+#define V_SCLK			(V_OSCK >> 1)
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_OF_LIBFDT		1
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_SERIAL_TAG
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE		(16 << 10)	/* 16 KiB */
+					/* Sector */
+#define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + (128 << 10))
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX		3
+#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
+#define CONFIG_SERIAL3			3	/* UART3 */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
+					115200}
+
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_DOS_PARTITION
+
+/* USB */
+#define CONFIG_USB_OMAP3
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_OMAP
+#define CONFIG_USB_STORAGE
+#define CONFIG_MUSB_UDC
+#define CONFIG_TWL4030_USB
+#define CONFIG_CMD_USB
+
+/* USB device configuration */
+#define CONFIG_USB_DEVICE
+#define CONFIG_USB_TTY
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+/* This delay is really for slow-to-power-on USB sticks, not the hub */
+#define CONFIG_USB_HUB_MIN_POWER_ON_DELAY 500
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
+#define CONFIG_CMD_FAT		/* FAT support			*/
+#define CONFIG_CMD_MTDPARTS	/* Enable MTD parts commands */
+#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
+#define CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT		"nand0=nand"
+#define MTDPARTS_DEFAULT	"mtdparts=nand:512k(x-loader),"\
+				"1920k(u-boot),256k(u-boot-env),"\
+				"4m(kernel),-(fs)"
+
+#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
+#define CONFIG_CMD_MMC		/* MMC support			*/
+#define CONFIG_CMD_NAND		/* NAND support			*/
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+
+#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
+#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
+#undef CONFIG_CMD_IMLS		/* List all found images	*/
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
+#define CONFIG_SYS_I2C_OMAP34XX
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_I2C_MULTI_BUS
+
+/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER
+#define CONFIG_TWL4030_LED
+
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_SYS_NAND_QUIET_TEST
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
+							/* to access nand */
+#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
+							/* to access nand at */
+							/* CS0 */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
+							/* devices */
+#define GPMC_NAND_ECC_LP_x8_LAYOUT
+
+/* Environment information */
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x82000000\0" \
+	"usbtty=cdc_acm\0" \
+	"console=ttyO2,115200n8\0" \
+	"mpurate=500\0" \
+	"vram=12M\0" \
+	"dvimode=1024x768MR-16@60\0" \
+	"defaultdisplay=dvi\0" \
+	"mmcdev=0\0" \
+	"mmcroot=/dev/mmcblk0p2 rw\0" \
+	"mmcrootfstype=ext4 rootwait\0" \
+	"nandroot=/dev/mtdblock4 rw\0" \
+	"nandrootfstype=ubifs\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"mpurate=${mpurate} " \
+		"vram=${vram} " \
+		"omapfb.mode=dvi:${dvimode} " \
+		"omapdss.def_disp=${defaultdisplay} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"mpurate=${mpurate} " \
+		"vram=${vram} " \
+		"omapfb.mode=dvi:${dvimode} " \
+		"omapdss.def_disp=${defaultdisplay} " \
+		"root=${nandroot} " \
+		"rootfstype=${nandrootfstype}\0" \
+	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source ${loadaddr}\0" \
+	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nand read ${loadaddr} 2a0000 400000; " \
+		"bootm ${loadaddr}\0" \
+
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loaduimage; then " \
+				"run mmcboot; " \
+			"else run nandboot; " \
+			"fi; " \
+		"fi; " \
+	"else run nandboot; fi"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_TIMESTAMP
+#define CONFIG_SYS_AUTOLOAD		"no"
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT		"CM-T3x # "
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
+
+#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)	/* memtest */
+								/* works on */
+#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
+					0x01F00000) /* 31MB */
+
+#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)	/* default */
+							/* load address */
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
+#define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1	/* CS1 is never populated */
+#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+/* Configure the PISMO */
+#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
+
+/* Monitor at start of flash */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
+
+#define CONFIG_ENV_IS_IN_NAND
+#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
+#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
+#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
+
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_32_BIT
+#define CM_T3X_SMC911X_BASE	0x2C000000
+#define SB_T35_SMC911X_BASE	(CM_T3X_SMC911X_BASE + (16 << 20))
+#define CONFIG_SMC911X_BASE	CM_T3X_SMC911X_BASE
+#endif /* (CONFIG_CMD_NET) */
+
+/* additions for new relocation code, must be added to all boards */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE	0x800
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR +	\
+					 CONFIG_SYS_INIT_RAM_SIZE -	\
+					 GENERATED_GBL_DATA_SIZE)
+
+/* Status LED */
+#define CONFIG_STATUS_LED		/* Status LED enabled */
+#define CONFIG_BOARD_SPECIFIC_LED
+#define CONFIG_GPIO_LED
+#define GREEN_LED_GPIO			186 /* CM-T35 Green LED is GPIO186 */
+#define GREEN_LED_DEV			0
+#define STATUS_LED_BIT			GREEN_LED_GPIO
+#define STATUS_LED_STATE		STATUS_LED_ON
+#define STATUS_LED_PERIOD		(CONFIG_SYS_HZ / 2)
+#define STATUS_LED_BOOT			GREEN_LED_DEV
+
+#define CONFIG_SPLASHIMAGE_GUARD
+
+/* GPIO banks */
+#ifdef CONFIG_STATUS_LED
+#define CONFIG_OMAP3_GPIO_6	/* GPIO186 is in GPIO bank 6  */
+#endif
+
+/* Display Configuration */
+#define CONFIG_OMAP3_GPIO_2
+#define CONFIG_OMAP3_GPIO_5
+#define CONFIG_VIDEO_OMAP3
+#define LCD_BPP		LCD_COLOR16
+
+#define CONFIG_LCD
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_CMD_BMP
+#define CONFIG_BMP_16BPP
+#define CONFIG_SCF0403_LCD
+
+#define CONFIG_OMAP3_SPI
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_NAND_SIMPLE
+
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
+
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_OMAP3_ID_NAND
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
+
+/* NAND boot config */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+/*
+ * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
+ * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
+ */
+#define CONFIG_SYS_NAND_ECCPOS		{ 1, 2, 3, 4, 5, 6, 7, 8, 9, \
+					 10, 11, 12 }
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW
+
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+
+#define CONFIG_SPL_TEXT_BASE		0x40200800
+#define CONFIG_SPL_MAX_SIZE		(54 * 1024)	/* 8 KB for stack */
+#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
+
+/*
+ * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
+ * older x-loader implementations. And move the BSS area so that it
+ * doesn't overlap with TEXT_BASE.
+ */
+#define CONFIG_SYS_TEXT_BASE		0x80008000
+#define CONFIG_SPL_BSS_START_ADDR	0x80100000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
+
+#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/cmi_mpc5xx.h b/qemu/roms/u-boot/include/configs/cmi_mpc5xx.h
new file mode 100644
index 000000000..32cecbdc9
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/cmi_mpc5xx.h
@@ -0,0 +1,254 @@
+/*
+ * (C) Copyright 2003
+ * Martin Winistoerfer, martinwinistoerfer@gmx.ch.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * File:		cmi_mpc5xx.h
+ *
+ * Discription:		Config header file for cmi
+ *			board  using an MPC5xx CPU
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+
+#define CONFIG_MPC555		1		/* This is an MPC555 CPU		*/
+#define CONFIG_CMI		1		/* Using the customized cmi board	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0x02000000	/* Boot from flash at location 0x00000000 */
+
+/* Serial Console Configuration */
+#define	CONFIG_5xx_CONS_SCI1
+#undef	CONFIG_5xx_CONS_SCI2
+
+#define CONFIG_BAUDRATE		57600
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#undef	CONFIG_CMD_NET		/* disabeled - causes compile errors */
+#undef	CONFIG_CMD_NFS
+
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_CONSOLE
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_IMI
+
+
+#if 0
+#define CONFIG_BOOTDELAY	-1		/* autoboot disabled			*/
+#else
+#define CONFIG_BOOTDELAY	5		/* autoboot after 5 seconds		*/
+#endif
+#define CONFIG_BOOTCOMMAND	"go 02034004"	/* autoboot command			*/
+
+#define CONFIG_BOOTARGS		""		/* Assuming OS Image in 4 flash sector at offset 4004 */
+
+#define CONFIG_WATCHDOG				/* turn on platform specific watchdog	*/
+
+#define CONFIG_STATUS_LED	1		/* Enable status led */
+
+#define CONFIG_LOADS_ECHO	1		/* Echo on for serial download */
+
+/*
+ * Miscellaneous configurable options
+ */
+
+#define	CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size	*/
+#else
+#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#endif
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16	       /* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END		0x000fa000	/* 1 MB in SRAM			*/
+
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address		*/
+
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 1250000 }
+
+
+/*
+ * Low Level Configuration Settings
+ */
+
+/*
+ * Internal Memory Mapped (This is not the IMMR content)
+ */
+#define CONFIG_SYS_IMMR		0x01000000		/* Physical start adress of internal memory map */
+
+/*
+ * Definitions for initial stack pointer and data area
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_IMMR + 0x003f9800)	/* Physical start adress of internal MPC555 writable RAM */
+#define	CONFIG_SYS_INIT_RAM_SIZE	(CONFIG_SYS_IMMR + 0x003fffff)	/* Physical end adress of internal MPC555 used RAM area	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_RAM_ADDR) - GENERATED_GBL_DATA_SIZE) /* Offset from the beginning of ram */
+#define	CONFIG_SYS_INIT_SP_ADDR	0x013fa000		/* Physical start adress of inital stack */
+
+/*
+ * Start addresses for the final memory configuration
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000	/* Monitor won't change memory map			*/
+#define CONFIG_SYS_FLASH_BASE		0x02000000	/* External flash */
+#define PLD_BASE		0x03000000	/* PLD  */
+#define ANYBUS_BASE		0x03010000	/* Anybus Module */
+
+#define CONFIG_SYS_RESET_ADRESS	0x01000000	/* Adress which causes reset */
+#define	CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE	/* CONFIG_SYS_TEXT_BASE is defined in the board config.mk file.	*/
+						/* This adress is given to the linker with -Ttext to	*/
+						/* locate the text section at this adress.		*/
+#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor				*/
+#define	CONFIG_SYS_MALLOC_LEN		(64 << 10)	/* Reserve 128 kB for malloc()				*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux		*/
+
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ *-----------------------------------------------------------------------
+ *
+ */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* Max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	64		/* Max number of sectors on one chip	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	180000		/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	600		/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_PROTECTION    1		/* Physically section protection on	*/
+
+#define	CONFIG_ENV_IS_IN_FLASH	1
+
+#ifdef	CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OFFSET		0x00020000	/* Environment starts at this adress	*/
+#define	CONFIG_ENV_SIZE		0x00010000	/* Set whole sector as env		*/
+#define	CONFIG_SYS_USE_PPCENV				/* Environment embedded in sect .ppcenv */
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWP)
+#endif	/* CONFIG_WATCHDOG */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF00
+#define CONFIG_SYS_SCCR	(SCCR_TBS     | SCCR_RTDIV    | SCCR_RTSEL    | \
+			 SCCR_COM00   | SCCR_DFNL000 | SCCR_DFNH000)
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration
+ *-----------------------------------------------------------------------
+ * Data show cycle
+ */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00)		/* Disable data show cycle	*/
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register
+ *-----------------------------------------------------------------------
+ * Set all bits to 40 Mhz
+ *
+ */
+#define CONFIG_SYS_OSC_CLK	((uint)4000000)		/* Oscillator clock is 4MHz	*/
+#define CONFIG_SYS_PLPRCR	(PLPRCR_MF_9 | PLPRCR_DIVF_0)
+
+
+/*-----------------------------------------------------------------------
+ * UMCR - UIMB Module Configuration Register
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_UMCR	(UMCR_FSPEED)		/* IMB clock same as U-bus	*/
+
+/*-----------------------------------------------------------------------
+ * ICTRL - I-Bus Support Control Register
+ */
+#define CONFIG_SYS_ICTRL	(ICTRL_ISCT_SER_7)	/* Take out of serialized mode	*/
+
+/*-----------------------------------------------------------------------
+ * USIU - Memory Controller Register
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | BR_V | BR_BI | BR_PS_16)
+#define CONFIG_SYS_OR0_PRELIM		(OR_ADDR_MK_FF | OR_SCY_3)
+#define CONFIG_SYS_BR1_PRELIM		(ANYBUS_BASE)
+#define CONFIG_SYS_OR1_PRELIM		(OR_ADDR_MK_FFFF | OR_SCY_1 | OR_ETHR)
+#define CONFIG_SYS_BR2_PRELIM		(CONFIG_SYS_SDRAM_BASE | BR_V | BR_PS_32)
+#define CONFIG_SYS_OR2_PRELIM		(OR_ADDR_MK_FF)
+#define CONFIG_SYS_BR3_PRELIM		(PLD_BASE | BR_V | BR_BI | BR_LBDIR | BR_PS_8)
+#define CONFIG_SYS_OR3_PRELIM		(OR_ADDR_MK_FF | OR_TRLX | OR_BSCY | OR_SCY_8 | \
+				 OR_ACS_10 | OR_ETHR | OR_CSNT)
+
+#define FLASH_BASE0_PRELIM	CONFIG_SYS_FLASH_BASE	/* We don't realign the flash	*/
+
+/*-----------------------------------------------------------------------
+ * DER - Timer Decrementer
+ *-----------------------------------------------------------------------
+ * Initialise to zero
+ */
+#define CONFIG_SYS_DER			0x00000000
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/cobra5272.h b/qemu/roms/u-boot/include/configs/cobra5272.h
new file mode 100644
index 000000000..464436930
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/cobra5272.h
@@ -0,0 +1,382 @@
+/*
+ * Configuation settings for the Sentec Cobra Board.
+ *
+ * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* ---
+ * Version: U-boot 1.0.0 - initial release for Sentec COBRA5272 board
+ * Date: 2004-03-29
+ * Author: Florian Schlote
+ *
+ * For a description of configuration options please refer also to the
+ * general u-boot-1.x.x/README file
+ * ---
+ */
+
+/* ---
+ * board/config.h - configuration options, board specific
+ * ---
+ */
+
+#ifndef _CONFIG_COBRA5272_H
+#define _CONFIG_COBRA5272_H
+
+/* ---
+ * Define processor
+ * possible values for Sentec board: only Coldfire M5272 processor supported
+ * (please do not change)
+ * ---
+ */
+
+#define CONFIG_MCF52x2			/* define processor family */
+#define CONFIG_M5272			/* define processor type */
+
+/* ---
+ * Defines processor clock - important for correct timings concerning serial
+ * interface etc.
+ * ---
+ */
+
+#define CONFIG_SYS_CLK			66000000
+#define CONFIG_SYS_SDRAM_SIZE		16		/* SDRAM size in MB */
+
+/* ---
+ * Enable use of Ethernet
+ * ---
+ */
+#define CONFIG_MCFFEC
+
+/* Enable Dma Timer */
+#define CONFIG_MCFTMR
+
+/* ---
+ * Define baudrate for UART1 (console output, tftp, ...)
+ * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud
+ * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected in u-boot command
+ * interface
+ * ---
+ */
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT		(0)
+#define CONFIG_BAUDRATE		19200
+
+/* ---
+ * set "#if 0" to "#if 1" if (Hardware)-WATCHDOG should be enabled & change
+ * timeout acc. to your needs
+ * #define CONFIG_WATCHDOG_TIMEOUT x , x is timeout in milliseconds, e. g. 10000
+ * for 10 sec
+ * ---
+ */
+
+#if 0
+#define CONFIG_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT 10000	/* timeout in milliseconds */
+#endif
+
+/* ---
+ * CONFIG_MONITOR_IS_IN_RAM defines if u-boot is started from a different
+ * bootloader residing in flash ('chainloading'); if you want to use
+ * chainloading or want to compile a u-boot binary that can be loaded into
+ * RAM via BDM set
+ *	"#if 0" to "#if 1"
+ * You will need a first stage bootloader then, e. g. colilo or a working BDM
+ * cable (Background Debug Mode)
+ *
+ * Setting #if 0: u-boot will start from flash and relocate itself to RAM
+ *
+ * Please do not forget to modify the setting of CONFIG_SYS_TEXT_BASE
+ * in board/cobra5272/config.mk accordingly (#if 0: 0xffe00000; #if 1: 0x20000)
+ *
+ * ---
+ */
+
+#if 0
+#define CONFIG_MONITOR_IS_IN_RAM /* monitor is started from a preloader */
+#endif
+
+/* ---
+ * Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ * ---
+ */
+
+#ifndef CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_ENV_OFFSET		0x4000
+#define CONFIG_ENV_SECT_SIZE	0x2000
+#define CONFIG_ENV_IS_IN_FLASH	1
+#else
+#define CONFIG_ENV_ADDR		0xffe04000
+#define CONFIG_ENV_SECT_SIZE	0x2000
+#define CONFIG_ENV_IS_IN_FLASH	1
+#endif
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_MII
+
+#ifdef CONFIG_MCFFEC
+#	define CONFIG_MII		1
+#	define CONFIG_MII_INIT		1
+#	define CONFIG_SYS_DISCOVER_PHY
+#	define CONFIG_SYS_RX_ETH_BUFFER	8
+#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+
+#	define CONFIG_SYS_FEC0_PINMUX		0
+#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
+#	define MCFFEC_TOUT_LOOP		50000
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+#	ifndef CONFIG_SYS_DISCOVER_PHY
+#		define FECDUPLEX	FULL
+#		define FECSPEED		_100BASET
+#	else
+#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#		endif
+#	endif			/* CONFIG_SYS_DISCOVER_PHY */
+#endif
+
+/*
+ *-----------------------------------------------------------------------------
+ * Define user parameters that have to be customized most likely
+ *-----------------------------------------------------------------------------
+ */
+
+/*AUTOBOOT settings - booting images automatically by u-boot after power on*/
+
+#define CONFIG_BOOTDELAY	5		/* used for autoboot, delay in
+seconds u-boot will wait before starting defined (auto-)boot command, setting
+to -1 disables delay, setting to 0 will too prevent access to u-boot command
+interface: u-boot then has to reflashed */
+
+
+/* The following settings will be contained in the environment block ; if you
+want to use a neutral environment all those settings can be manually set in
+u-boot: 'set' command */
+
+#if 0
+
+#define CONFIG_BOOTCOMMAND	"bootm 0xffe80000"	/*Autoboto command, please
+enter a valid image address in flash */
+
+#define CONFIG_BOOTARGS		" "			/* default bootargs that are
+considered during boot */
+
+/* User network settings */
+
+#define CONFIG_ETHADDR 00:00:00:00:00:09	/* default ethernet MAC addr. */
+#define CONFIG_IPADDR 192.168.100.2		/* default board IP address */
+#define CONFIG_SERVERIP 192.168.100.1	/* default tftp server IP address */
+
+#endif
+
+#define CONFIG_SYS_PROMPT		"COBRA > "	/* Layout of u-boot prompt*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x20000		/*Defines default RAM address
+from which user programs will be started */
+
+/*---*/
+
+#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+/*
+ *-----------------------------------------------------------------------------
+ * End of user parameters to be customized
+ *-----------------------------------------------------------------------------
+ */
+
+/* ---
+ * Defines memory range for test
+ * ---
+ */
+
+#define CONFIG_SYS_MEMTEST_START	0x400
+#define CONFIG_SYS_MEMTEST_END		0x380000
+
+/* ---
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ * ---
+ */
+
+/* ---
+ * Base register address
+ * ---
+ */
+
+#define CONFIG_SYS_MBAR		0x10000000	/* Register Base Addrs */
+
+/* ---
+ * System Conf. Reg. & System Protection Reg.
+ * ---
+ */
+
+#define CONFIG_SYS_SCR			0x0003
+#define CONFIG_SYS_SPR			0xffff
+
+/* ---
+ * Ethernet settings
+ * ---
+ */
+
+#define CONFIG_SYS_DISCOVER_PHY
+#define CONFIG_SYS_ENET_BD_BASE	0x780000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in internal SRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in internal SRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+
+/*
+ *-------------------------------------------------------------------------
+ * RAM SIZE (is defined above)
+ *-----------------------------------------------------------------------
+ */
+
+/* #define CONFIG_SYS_SDRAM_SIZE		16 */
+
+/*
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_SYS_FLASH_BASE		0xffe00000
+
+#ifdef	CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_SYS_MONITOR_BASE	0x20000
+#else
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN		0x20000
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	11	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	1000	/* flash timeout */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16
+
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
+					 CF_CACR_DISD | CF_CACR_INVI | \
+					 CF_CACR_CEIB | CF_CACR_DCM | \
+					 CF_CACR_EUSP)
+
+/*-----------------------------------------------------------------------
+ * Memory bank definitions
+ *
+ * Please refer also to Motorola Coldfire user manual - Chapter XXX
+ * <http://e-www.motorola.com/files/dsp/doc/ref_manual/MCF5272UM.pdf>
+ */
+#define CONFIG_SYS_BR0_PRELIM		0xFFE00201
+#define CONFIG_SYS_OR0_PRELIM		0xFFE00014
+
+#define CONFIG_SYS_BR1_PRELIM		0
+#define CONFIG_SYS_OR1_PRELIM		0
+
+#define CONFIG_SYS_BR2_PRELIM		0
+#define CONFIG_SYS_OR2_PRELIM		0
+
+#define CONFIG_SYS_BR3_PRELIM		0
+#define CONFIG_SYS_OR3_PRELIM		0
+
+#define CONFIG_SYS_BR4_PRELIM		0
+#define CONFIG_SYS_OR4_PRELIM		0
+
+#define CONFIG_SYS_BR5_PRELIM		0
+#define CONFIG_SYS_OR5_PRELIM		0
+
+#define CONFIG_SYS_BR6_PRELIM		0
+#define CONFIG_SYS_OR6_PRELIM		0
+
+#define CONFIG_SYS_BR7_PRELIM		0x00000701
+#define CONFIG_SYS_OR7_PRELIM		0xFF00007C
+
+/*-----------------------------------------------------------------------
+ * LED config
+ */
+#define	LED_STAT_0	0xffff /*all LEDs off*/
+#define	LED_STAT_1	0xfffe
+#define	LED_STAT_2	0xfffd
+#define	LED_STAT_3	0xfffb
+#define	LED_STAT_4	0xfff7
+#define	LED_STAT_5	0xffef
+#define	LED_STAT_6	0xffdf
+#define	LED_STAT_7	0xff00 /*all LEDs on*/
+
+/*-----------------------------------------------------------------------
+ * Port configuration (GPIO)
+ */
+#define CONFIG_SYS_PACNT		0x00000000		/* PortA control reg.: All pins are external
+GPIO*/
+#define CONFIG_SYS_PADDR		0x00FF			/* PortA direction reg.: PA7 to PA0 are outputs
+(1^=output, 0^=input) */
+#define CONFIG_SYS_PADAT		LED_STAT_0		/* PortA value reg.: Turn all LED off */
+#define CONFIG_SYS_PBCNT		0x55554155		/* PortB control reg.: Ethernet/UART
+configuration */
+#define CONFIG_SYS_PBDDR		0x0000			/* PortB direction: All pins configured as inputs */
+#define CONFIG_SYS_PBDAT		0x0000			/* PortB value reg. */
+#define CONFIG_SYS_PDCNT		0x00000000		/* PortD control reg. */
+
+#endif	/* _CONFIG_COBRA5272_H */
diff --git a/qemu/roms/u-boot/include/configs/cogent_common.h b/qemu/roms/u-boot/include/configs/cogent_common.h
new file mode 100644
index 000000000..1b5d6a565
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/cogent_common.h
@@ -0,0 +1,192 @@
+/*
+ * (C) Copyright 2000
+ * Murray Jensen, CSIRO-MST
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CONFIG_COGENT_COMMON_H
+#define _CONFIG_COGENT_COMMON_H
+
+/*
+ * Cogent Motherboard Capabilities
+ */
+#define CMA_MB_CAP_SERPAR	0x0001	/* has dual serial+parallel (16C552) */
+#define CMA_MB_CAP_LCD		0x0002	/* has LCD display (HD44780) */
+#define CMA_MB_CAP_FLASH	0x0004	/* has flash (E28F800B or AM29F800BB) */
+#define CMA_MB_CAP_RTC		0x0008	/* has RTC+NVRAM (MK48T02) */
+#define CMA_MB_CAP_ETHER	0x0010	/* has Ethernet (MB86964) */
+#define CMA_MB_CAP_SLOT1	0x0020	/* has CMABus slot 1 */
+#define CMA_MB_CAP_SLOT2	0x0040	/* has CMABus slot 2 */
+#define CMA_MB_CAP_SLOT3	0x0080	/* has CMABus slot 3 */
+#define CMA_MB_CAP_KBM		0x0100	/* has PS/2 keyboard+mouse (HT6542B) */
+#define CMA_MB_CAP_SER2		0x0200	/* has 2nd dual serial (16C2552) */
+#define CMA_MB_CAP_PCI		0x0400	/* has pci bridge (V360EPC) */
+#define CMA_MB_CAP_PCI_EXT	0x0800	/* can access extended pci space  */
+#define CMA_MB_CAP_PCI_ETHER	0x1000	/* has 10/100 ether on PCI (GD82559) */
+#define CMA_MB_CAP_PCI_VIDEO	0x2000	/* has video int'face on PCI (B69000) */
+#define CMA_MB_CAP_PCI_CARDBUS	0x4000	/* has Cardbus Ctlr on PCI (PD6832) */
+
+/*
+ * Cogent option sanity checking
+ */
+
+#if defined(CONFIG_MPC821) || defined(CONFIG_MPC823) || \
+      defined(CONFIG_MPC850) || defined(CONFIG_MPC860)
+
+/*
+ * check a PowerPC 8xx cpu module has been selected
+ */
+
+# if defined(CONFIG_CMA286_21)
+
+#  define COGENT_CPU_MODULE	"CMA286-21"
+
+# elif defined(CONFIG_CMA286_60_OLD)
+
+#  define COGENT_CPU_MODULE	"CMA286-60 (old)"
+
+# elif defined(CONFIG_CMA286_60)
+
+#  define COGENT_CPU_MODULE	"CMA286-60"
+
+# elif defined(CONFIG_CMA286_60P)
+
+#  define COGENT_CPU_MODULE	"CMA286-60P"
+
+# elif defined(CONFIG_CMA287_21)
+
+#  define COGENT_CPU_MODULE	"CMA287-21"
+
+# elif defined(CONFIG_CMA287_50)
+
+#  define COGENT_CPU_MODULE	"CMA287-50"
+
+# else
+
+#  error Cogent CPU Module must be a PowerPC MPC8xx module
+
+# endif
+
+#elif defined(CONFIG_MPC8260)
+
+/*
+ * check a PowerPC 8260 cpu module has been selected
+ */
+
+# if defined(CONFIG_CMA282)
+
+#  define COGENT_CPU_MODULE	"CMA282"
+
+# else
+
+#  error Cogent CPU Module must be a PowerPC MPC8260 module
+
+# endif
+
+#else
+
+# error CPU type must be PowerPC 8xx or 8260
+
+#endif
+
+/*
+ * check a motherboard has been selected
+ * define the motherboard capabilities while we're at it
+ */
+
+#if defined(CONFIG_CMA101)
+
+# define COGENT_MOTHERBOARD	"CMA101"
+# define CMA_MB_CAPS		(CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \
+				 CMA_MB_CAP_RTC | CMA_MB_CAP_ETHER | \
+				 CMA_MB_CAP_SLOT1 | CMA_MB_CAP_SLOT2 | \
+				 CMA_MB_CAP_SLOT3)
+# define CMA_MB_NSLOTS		3
+
+#elif defined(CONFIG_CMA102)
+
+# define COGENT_MOTHERBOARD	"CMA102"
+# define CMA_MB_CAPS		(CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \
+				 CMA_MB_CAP_RTC | CMA_MB_CAP_SLOT1 | \
+				 CMA_MB_CAP_SLOT2 | CMA_MB_CAP_SLOT3)
+# define CMA_MB_NSLOTS		3
+
+#elif defined(CONFIG_CMA110)
+
+# define COGENT_MOTHERBOARD	"CMA110"
+# define CMA_MB_CAPS		(CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \
+				 CMA_MB_CAP_FLASH | CMA_MB_CAP_RTC | \
+				 CMA_MB_CAP_KBM | CMA_MB_CAP_PCI)
+# define CMA_MB_NSLOTS		0
+
+#elif defined(CONFIG_CMA111)
+
+# define COGENT_MOTHERBOARD	"CMA111"
+# define CMA_MB_CAPS		(CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \
+				 CMA_MB_CAP_FLASH | CMA_MB_CAP_RTC | \
+				 CMA_MB_CAP_SLOT1 | CMA_MB_CAP_KBM | \
+				 CMA_MB_CAP_PCI | CMA_MB_CAP_PCI_EXT | \
+				 CMA_MB_CAP_PCI_ETHER)
+# define CMA_MB_NSLOTS		1
+
+#elif defined(CONFIG_CMA120)
+
+# define COGENT_MOTHERBOARD	"CMA120"
+# define CMA_MB_CAPS		(CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \
+				 CMA_MB_CAP_FLASH | CMA_MB_CAP_RTC | \
+				 CMA_MB_CAP_SLOT1 | CMA_MB_CAP_KBM | \
+				 CMA_MB_CAP_SER2 | CMA_MB_CAP_PCI | \
+				 CMA_MB_CAP_PCI_EXT | CMA_MB_CAP_PCI_ETHER | \
+				 CMA_MB_CAP_PCI_VIDEO | CMA_MB_CAP_PCI_CARDBUS)
+# define CMA_MB_NSLOTS		1
+
+#elif defined(CONFIG_CMA150)
+
+# define COGENT_MOTHERBOARD	"CMA150"
+# define CMA_MB_CAPS		(CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \
+				 CMA_MB_CAP_FLASH | CMA_MB_CAP_RTC | \
+				 CMA_MB_CAP_KBM)
+# define CMA_MB_NSLOTS		0
+
+#else
+
+# error Cogent Motherboard either unsupported or undefined
+
+#endif
+
+/*
+ * check a flash i/o module has been selected if no flash on m/b
+ */
+
+#if defined(CONFIG_CMA302)
+
+# define COGENT_FLASH_MODULE	"CMA302"
+
+#elif (CMA_MB_CAPS & CMA_MB_CAP_FLASH) == 0
+
+# error Cogent Flash I/O module (e.g. CMA302) is required with this Motherboard
+
+#endif
+
+/*
+ * some further sanity checks
+ */
+
+#if (CMA_MB_CAPS & CMA_MB_CAP_PCI) && (CMA_MB_CAPS & CMA_MB_CAP_SLOT2)
+#error Cogent Sanity Check: Both Slot2 and PCI are defined
+#endif
+
+#if (CMA_MB_CAPS & CMA_MB_CAP_PCI_EXT) && !(CMA_MB_CAPS & CMA_MB_CAP_PCI)
+#error Extended PCI capability defined without PCI capability
+#endif
+
+#if (CMA_MB_CAPS & CMA_MB_CAP_PCI_ETHER) && !(CMA_MB_CAPS & CMA_MB_CAP_PCI)
+#error Motherboard ethernet capability defined without PCI capability
+#endif
+
+#if (CMA_MB_CAPS & CMA_MB_CAP_SER2) && !(CMA_MB_CAPS & CMA_MB_CAP_SERPAR)
+#error 2nd dual serial capability defined without serial/parallel capability
+#endif
+#include "../board/cogent/mb.h"
+#endif	/* _CONFIG_COGENT_COMMON_H */
diff --git a/qemu/roms/u-boot/include/configs/cogent_mpc8260.h b/qemu/roms/u-boot/include/configs/cogent_mpc8260.h
new file mode 100644
index 000000000..02b25c644
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/cogent_mpc8260.h
@@ -0,0 +1,392 @@
+/*
+ * (C) Copyright 2000
+ * Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Config header file for Cogent platform using an MPC8xx CPU module
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU	*/
+#define CONFIG_COGENT		1	/* using Cogent Modular Architecture */
+#define CONFIG_CPM2		1	/* Has a CPM2 */
+
+#define	CONFIG_SYS_TEXT_BASE	0xfff00000
+
+#define	CONFIG_MISC_INIT_F	1	/* Use misc_init_f()		*/
+#define	CONFIG_MISC_INIT_R		/* Use misc_init_r()		*/
+
+/* Cogent Modular Architecture options */
+#define CONFIG_CMA282		1	/* ...on a CMA282 CPU module	*/
+#define CONFIG_CMA111		1	/* ...on a CMA111 motherboard	*/
+
+/*
+ * select serial console configuration
+ *
+ * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ *
+ * if CONFIG_CONS_NONE is defined, then the serial console routines must
+ * defined elsewhere (for example, on the cogent platform, there are serial
+ * ports on the motherboard which are used for the serial console - see
+ * cogent/cma101/serial.[ch]).
+ */
+#define	CONFIG_CONS_ON_SMC		/* define if console on SMC */
+#undef	CONFIG_CONS_ON_SCC		/* define if console on SCC */
+#undef	CONFIG_CONS_NONE		/* define if console on something else*/
+#define CONFIG_CONS_INDEX	1	/* which serial channel for console */
+#undef	CONFIG_CONS_USE_EXTC		/* SMC/SCC use ext clock not brg_clk */
+#define	CONFIG_CONS_EXTC_RATE	3686400	/* SMC/SCC ext clk rate in Hz */
+#define	CONFIG_CONS_EXTC_PINSEL	0	/* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
+
+/*
+ * select ethernet configuration
+ *
+ * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
+ * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
+ * for FCC)
+ *
+ * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
+ */
+#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC	*/
+#undef	CONFIG_ETHER_ON_FCC		/* define if ether on FCC	*/
+#define	CONFIG_ETHER_NONE		/* define if ether on something else */
+#define CONFIG_ETHER_INDEX	1	/* which channel for ether	*/
+
+/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
+#define CONFIG_8260_CLKIN	66666666	/* in Hz */
+
+#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
+#define CONFIG_BAUDRATE		230400
+#else
+#define CONFIG_BAUDRATE		9600
+#endif
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_KGDB
+
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+
+#ifdef DEBUG
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+#define CONFIG_BOOTCOMMAND	"bootm 04080000 04200000" /* autoboot command*/
+
+#define CONFIG_BOOTARGS		"root=/dev/ram rw"
+
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
+#undef	CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
+#undef	CONFIG_KGDB_NONE		/* define if kgdb on something else */
+#define CONFIG_KGDB_INDEX	2	/* which serial channel for kgdb */
+#define	CONFIG_KGDB_USE_EXTC		/* SMC/SCC use ext clock not brg_clk */
+#define	CONFIG_KGDB_EXTC_RATE	3686400	/* serial ext clk rate in Hz */
+#define	CONFIG_KGDB_EXTC_PINSEL	0	/* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
+# if defined(CONFIG_KGDB_NONE) || defined(CONFIG_KGDB_USE_EXTC)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port at */
+# else
+#define CONFIG_KGDB_BAUDRATE	9600	/* speed to run kgdb serial port at */
+# endif
+#endif
+
+#undef	CONFIG_WATCHDOG			/* disable platform specific watchdog */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x00400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x01c00000	/* 4 ... 28 MB in DRAM	*/
+
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Low Level Cogent settings
+ * if CONFIG_SYS_CMA_CONS_SERIAL is defined, make sure the 8260 CPM serial is not.
+ * also, make sure CONFIG_CONS_INDEX is still defined - the index will be
+ * 1 for serialA, 2 for serialB, 3 for ser2A, 4 for ser2B
+ * (second 2 for CMA120 only)
+ */
+#define CONFIG_SYS_CMA_MB_BASE		0x00000000	/* base of m/b address space */
+
+#include <configs/cogent_common.h>
+
+#ifdef CONFIG_CONS_NONE
+#define CONFIG_SYS_CMA_CONS_SERIAL	/* use Cogent motherboard serial for console */
+#endif
+#define CONFIG_SYS_CMA_LCD_HEARTBEAT	/* define for sec rotator in lcd corner */
+#define CONFIG_SHOW_ACTIVITY
+
+#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
+/*
+ * flash exists on the motherboard
+ * set these four according to TOP dipsw:
+ * TOP on  => ..._FLLOW_...	(boot EPROM space is high so FLASH is low )
+ * TOP off => ..._FLHIGH_...	(boot EPROM space is low  so FLASH is high)
+ */
+#define CMA_MB_FLASH_EXEC_BASE	CMA_MB_FLLOW_EXEC_BASE
+#define CMA_MB_FLASH_EXEC_SIZE	CMA_MB_FLLOW_EXEC_SIZE
+#define CMA_MB_FLASH_RDWR_BASE	CMA_MB_FLLOW_RDWR_BASE
+#define CMA_MB_FLASH_RDWR_SIZE	CMA_MB_FLLOW_RDWR_SIZE
+#endif
+#define CMA_MB_FLASH_BASE	CMA_MB_FLASH_EXEC_BASE
+#define CMA_MB_FLASH_SIZE	CMA_MB_FLASH_EXEC_SIZE
+
+/*-----------------------------------------------------------------------
+ * Hard Reset Configuration Words
+ *
+ * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
+ * defines for the various registers affected by the HRCW e.g. changing
+ * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
+ */
+#define CONFIG_SYS_HRCW_MASTER	(HRCW_EBM|HRCW_BPS10|HRCW_L2CPC10|HRCW_DPPC11|\
+			 HRCW_ISB100|HRCW_MMR11|HRCW_MODCK_H0101)
+/* no slaves so just duplicate the master hrcw */
+#define CONFIG_SYS_HRCW_SLAVE1	CONFIG_SYS_HRCW_MASTER
+#define CONFIG_SYS_HRCW_SLAVE2	CONFIG_SYS_HRCW_MASTER
+#define CONFIG_SYS_HRCW_SLAVE3	CONFIG_SYS_HRCW_MASTER
+#define CONFIG_SYS_HRCW_SLAVE4	CONFIG_SYS_HRCW_MASTER
+#define CONFIG_SYS_HRCW_SLAVE5	CONFIG_SYS_HRCW_MASTER
+#define CONFIG_SYS_HRCW_SLAVE6	CONFIG_SYS_HRCW_MASTER
+#define CONFIG_SYS_HRCW_SLAVE7	CONFIG_SYS_HRCW_MASTER
+
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xF0000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x4000	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define	CONFIG_SYS_SDRAM_BASE		CMA_MB_RAM_BASE
+#ifdef CONFIG_CMA302
+#define CONFIG_SYS_FLASH_BASE		CMA_MB_SLOT2_BASE	/* cma302 in slot 2 */
+#else
+#define CONFIG_SYS_FLASH_BASE		CMA_MB_FLASH_BASE	/* flash on m/b */
+#endif
+#define	CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Mem map for Linux*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max num of memory banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	67	/* max num of sects on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Flash Erase Timeout (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
+
+#define	CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_ADDR		CONFIG_SYS_FLASH_BASE /* Addr of Environment Sector */
+#ifdef CONFIG_CMA302
+#define	CONFIG_ENV_SIZE		0x1000	/* Total Size of Environment Sector */
+#define CONFIG_ENV_SECT_SIZE	(512*1024) /* see README - env sect real size */
+#else
+#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPU		*/
+#if defined(CONFIG_CMD_KGDB)
+# define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * HIDx - Hardware Implementation-dependent Registers			 2-11
+ *-----------------------------------------------------------------------
+ * HID0 also contains cache control - initially enable both caches and
+ * invalidate contents, then the final state leaves only the instruction
+ * cache enabled. Note that Power-On and Hard reset invalidate the caches,
+ * but Soft reset does not.
+ *
+ * HID1 has only read-only information - nothing to set.
+ */
+#define CONFIG_SYS_HID0_INIT	(HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
+				HID0_IFEM|HID0_ABE)
+#define CONFIG_SYS_HID0_FINAL	(HID0_ICE|HID0_IFEM|HID0_ABE)
+#define CONFIG_SYS_HID2	0
+
+/*-----------------------------------------------------------------------
+ * RMR - Reset Mode Register					 5-5
+ *-----------------------------------------------------------------------
+ * turn on Checkstop Reset Enable
+ */
+#define CONFIG_SYS_RMR		RMR_CSRE
+
+/*-----------------------------------------------------------------------
+ * BCR - Bus Configuration					 4-25
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_BCR		BCR_EBM
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				 4-31
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DPPC11|SIUMCR_L2CPC10|SIUMCR_MMR11)
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				 4-35
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
+#else
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+			 SYPCR_SWRI|SYPCR_SWP)
+#endif /* CONFIG_WATCHDOG */
+
+/*-----------------------------------------------------------------------
+ * TMCNTSC - Time Counter Status and Control			 4-40
+ *-----------------------------------------------------------------------
+ * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
+ * and enable Time Counter
+ */
+#define CONFIG_SYS_TMCNTSC	(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		 4-42
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
+ * Periodic timer
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS|PISCR_PTF|PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control					 9-8
+ *-----------------------------------------------------------------------
+ * Ensure DFBRG is Divide by 16
+ */
+#define CONFIG_SYS_SCCR	(SCCR_DFBRG01)
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration				13-7
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RCCR	0
+
+#if defined(CONFIG_CMA282)
+
+/*
+ * Init Memory Controller:
+ *
+ * According to the Cogent manual, only CS0 and CS2 are used - CS0 for EPROM
+ * and CS2 for (optional) local bus RAM on the CPU module.
+ *
+ * Note the motherboard address space (256 Mbyte in size) is connected
+ * to the 60x Bus and is located starting at address 0. The Hard Reset
+ * Configuration Word should put the 60x Bus into External Bus Mode, since
+ * we dont set up any memory controller maps for it (see BCR[EBM], 4-26).
+ *
+ * (the *_SIZE vars must be a power of 2)
+ */
+
+#define CONFIG_SYS_CMA_CS0_BASE	CONFIG_SYS_TEXT_BASE	/* EPROM */
+#define CONFIG_SYS_CMA_CS0_SIZE	(1 << 20)
+#if 0
+#define CONFIG_SYS_CMA_CS2_BASE	0x10000000	/* Local Bus SDRAM */
+#define CONFIG_SYS_CMA_CS2_SIZE	(16 << 20)
+#endif
+
+/*
+ * CS0 maps the EPROM on the cpu module
+ * Set it for 10 wait states, address CONFIG_SYS_MONITOR_BASE and size 1M
+ *
+ * Note: We must have already transferred control to the final location
+ * of the EPROM before these are used, because when BR0/OR0 are set, the
+ * mirror of the eprom at any other addresses will disappear.
+ */
+
+/* base address = CONFIG_SYS_CMA_CS0_BASE, 16-bit, no parity, r/o, gpcm (60x bus) */
+#define CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_CMA_CS0_BASE&BRx_BA_MSK)|BRx_PS_16|BRx_WP|BRx_V)
+/* mask size CONFIG_SYS_CMA_CS0_SIZE, csneg 1/4 early, adr-to-cs 1/2, 10-wait states */
+#define CONFIG_SYS_OR0_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_CMA_CS0_SIZE)|\
+				ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK)
+
+/*
+ * CS2 enables the Local Bus SDRAM on the CPU Module
+ *
+ * Will leave this unset for the moment, because a) my CPU module has no
+ * SDRAM installed (it is optional); and b) it will require programming
+ * one of the UPMs in SDRAM mode - not a trivial job, and hard to get right
+ * if you can't test it.
+ */
+
+#if 0
+/* base address = CONFIG_SYS_CMA_CS2_BASE, 32-bit, no parity, ??? */
+#define CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_CMA_CS2_BASE&BRx_BA_MSK)|BRx_PS_32|/*???*/|BRx_V)
+/* mask size CONFIG_SYS_CMA_CS2_SIZE, CS time normal, ??? */
+#define CONFIG_SYS_OR2_PRELIM	((~(CONFIG_SYS_CMA_CS2_SIZE-1)&ORx_AM_MSK)|/*???*/)
+#endif
+
+#endif
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/cogent_mpc8xx.h b/qemu/roms/u-boot/include/configs/cogent_mpc8xx.h
new file mode 100644
index 000000000..c98b687c0
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/cogent_mpc8xx.h
@@ -0,0 +1,349 @@
+/*
+ * (C) Copyright 2000-2010
+ * Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Config header file for Cogent platform using an MPC8xx CPU module
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC860		1	/* This is an MPC860 CPU	*/
+#define CONFIG_COGENT		1	/* using Cogent Modular Architecture */
+
+#define	CONFIG_SYS_TEXT_BASE	0xfff00000
+
+#define	CONFIG_MISC_INIT_F	1	/* Use misc_init_f()		*/
+#define	CONFIG_MISC_INIT_R		/* Use misc_init_r()		*/
+
+/* Cogent Modular Architecture options */
+#define CONFIG_CMA286_60_OLD	1	/* ...on an old CMA286-60 CPU module */
+#define CONFIG_CMA102		1	/* ...on a CMA102 motherboard	*/
+#define CONFIG_CMA302		1	/* ...with a CMA302 flash I/O module */
+
+/* serial console configuration */
+#undef	CONFIG_8xx_CONS_SMC1
+#undef	CONFIG_8xx_CONS_SMC2
+#define CONFIG_8xx_CONS_NONE	/* not on 8xx serial ports (eg on cogent m/b) */
+
+#if defined(CONFIG_CMA286_60_OLD)
+#define CONFIG_8xx_GCLK_FREQ	33333000 /* define if cant use get_gclk_freq */
+#endif
+
+#define CONFIG_BAUDRATE		230400
+
+#define CONFIG_HARD_I2C		/* I2C with hardware support */
+#define CONFIG_SYS_I2C_SPEED		400000  /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_KGDB
+#define CONFIG_CMD_I2C
+
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+#define CONFIG_BOOTCOMMAND	"bootm 04080000 04200000" /* autoboot command*/
+
+#define CONFIG_BOOTARGS		"root=/dev/ram rw"
+
+#if defined(CONFIG_CMD_KGDB)
+#undef	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
+#undef	CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
+#define	CONFIG_KGDB_NONE		/* define if kgdb on something else */
+#define CONFIG_KGDB_INDEX	2	/* which SMC/SCC channel for kgdb */
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+#define CONFIG_WATCHDOG			/* turn on platform specific watchdog */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x00400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x01c00000	/* 4 ... 28 MB in DRAM	*/
+
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#define CONFIG_SYS_ALLOC_DPRAM
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Low Level Cogent settings
+ * if CONFIG_SYS_CMA_CONS_SERIAL is defined, make sure the 8xx CPM serial is not.
+ * also, make sure CONFIG_CONS_INDEX is still defined - the index will be
+ * 1 for serialA, 2 for serialB, 3 for ser2A, 4 for ser2B
+ * (second 2 for CMA120 only)
+ */
+#define CONFIG_SYS_CMA_MB_BASE		0x00000000	/* base of m/b address space */
+
+#include <configs/cogent_common.h>
+
+#define CONFIG_SYS_CMA_CONS_SERIAL	/* use Cogent motherboard serial for console */
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_SYS_CMA_LCD_HEARTBEAT	/* define for sec rotator in lcd corner */
+#define CONFIG_SHOW_ACTIVITY
+#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
+/*
+ * flash exists on the motherboard
+ * set these four according to TOP dipsw:
+ * TOP on  => ..._FLLOW_...	(boot EPROM space is high so FLASH is low )
+ * TOP off => ..._FLHIGH_...	(boot EPROM space is low  so FLASH is high)
+ */
+#define CMA_MB_FLASH_EXEC_BASE	CMA_MB_FLLOW_EXEC_BASE
+#define CMA_MB_FLASH_EXEC_SIZE	CMA_MB_FLLOW_EXEC_SIZE
+#define CMA_MB_FLASH_RDWR_BASE	CMA_MB_FLLOW_RDWR_BASE
+#define CMA_MB_FLASH_RDWR_SIZE	CMA_MB_FLLOW_RDWR_SIZE
+#endif
+#define CMA_MB_FLASH_BASE	CMA_MB_FLASH_EXEC_BASE
+#define CMA_MB_FLASH_SIZE	CMA_MB_FLASH_EXEC_SIZE
+
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xFF000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define	CONFIG_SYS_SDRAM_BASE		CMA_MB_RAM_BASE
+#ifdef CONFIG_CMA302
+#define CONFIG_SYS_FLASH_BASE		CMA_MB_SLOT2_BASE	/* cma302 in slot 2 */
+#else
+#define CONFIG_SYS_FLASH_BASE		CMA_MB_FLASH_BASE	/* flash on m/b */
+#endif
+#define	CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#define	CONFIG_SYS_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_ADDR		CONFIG_SYS_FLASH_BASE /* Addr of Environment Sector */
+#ifdef CONFIG_CMA302
+#define	CONFIG_ENV_SIZE		0x1000	/* Total Size of Environment Sector	*/
+#define CONFIG_ENV_SECT_SIZE	(512*1024) /* see README - env sect real size */
+#else
+#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+#endif
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif	/* CONFIG_WATCHDOG */
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit - leave PLL multiplication factor unchanged !
+ */
+#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CONFIG_SYS_SCCR	(SCCR_TBS     | SCCR_RTDIV    | SCCR_RTSEL    | \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+/*#define	CONFIG_SYS_DER	0x2002000F*/
+#define CONFIG_SYS_DER	0
+
+#if defined(CONFIG_CMA286_60_OLD)
+
+/*
+ * Init Memory Controller:
+ *
+ * NOTE: although the names (CONFIG_SYS_xRn_PRELIM) suggest preliminary settings,
+ * they are actually the final settings for this cpu/board, because the
+ * flash and RAM are on the motherboard, accessed via the CMAbus, and the
+ * mappings are pretty much fixed.
+ *
+ * (the *_SIZE vars must be a power of 2)
+ */
+
+#define CONFIG_SYS_CMA_CS0_BASE	CONFIG_SYS_TEXT_BASE		/* EPROM */
+#define CONFIG_SYS_CMA_CS0_SIZE	(1 << 20)
+#define CONFIG_SYS_CMA_CS1_BASE	CMA_MB_RAM_BASE		/* RAM + I/O SLOT 1 */
+#define CONFIG_SYS_CMA_CS1_SIZE	(64 << 20)
+#define CONFIG_SYS_CMA_CS2_BASE	CMA_MB_SLOT2_BASE	/* I/O SLOTS 2 + 3 */
+#define CONFIG_SYS_CMA_CS2_SIZE	(64 << 20)
+#define CONFIG_SYS_CMA_CS3_BASE	CMA_MB_ROMLOW_BASE	/* M/B I/O */
+#define CONFIG_SYS_CMA_CS3_SIZE	(32 << 20)
+
+/*
+ * CS0 maps the EPROM on the cpu module
+ * Set it for 4 wait states, address CONFIG_SYS_MONITOR_BASE and size 1M
+ *
+ * Note: We must have already transferred control to the final location
+ * of the EPROM before these are used, because when BR0/OR0 are set, the
+ * mirror of the eprom at any other addresses will disappear.
+ */
+
+/* base address = CONFIG_SYS_CMA_CS0_BASE, 16-bit, no parity, r/o, gpcm */
+#define CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_CMA_CS0_BASE&BR_BA_MSK)|BR_PS_16|BR_WP|BR_V)
+/* mask size CONFIG_SYS_CMA_CS0_SIZE, CS time normal, burst inhibit, 4-wait states */
+#define CONFIG_SYS_OR0_PRELIM	((~(CONFIG_SYS_CMA_CS0_SIZE-1)&OR_AM_MSK)|OR_BI|OR_SCY_4_CLK)
+
+/*
+ * CS1 maps motherboard DRAM and motherboard I/O slot 1
+ * (each 32Mbyte in size)
+ */
+
+/* base address = CONFIG_SYS_CMA_CS1_BASE, 32-bit, no parity, r/w, gpcm */
+#define CONFIG_SYS_BR1_PRELIM	((CONFIG_SYS_CMA_CS1_BASE&BR_BA_MSK)|BR_V)
+/* mask size CONFIG_SYS_CMA_CS1_SIZE, CS time normal, burst ok, ext xfer ack */
+#define CONFIG_SYS_OR1_PRELIM	((~(CONFIG_SYS_CMA_CS1_SIZE-1)&OR_AM_MSK)|OR_SETA)
+
+/*
+ * CS2 maps motherboard I/O slots 2 and 3
+ * (each 32Mbyte in size)
+ */
+
+/* base address = CONFIG_SYS_CMA_CS2_BASE, 32-bit, no parity, r/w, gpcm */
+#define CONFIG_SYS_BR2_PRELIM	((CONFIG_SYS_CMA_CS2_BASE&BR_BA_MSK)|BR_V)
+/* mask size CONFIG_SYS_CMA_CS2_SIZE, CS time normal, burst ok, ext xfer ack */
+#define CONFIG_SYS_OR2_PRELIM	((~(CONFIG_SYS_CMA_CS2_SIZE-1)&OR_AM_MSK)|OR_SETA)
+
+/*
+ * CS3 maps motherboard I/O
+ * (32Mbyte in size)
+ */
+
+/* base address = CONFIG_SYS_CMA_CS3_BASE, 32-bit, no parity, r/w, gpcm */
+#define CONFIG_SYS_BR3_PRELIM	((CONFIG_SYS_CMA_CS3_BASE&BR_BA_MSK)|BR_V)
+/* mask size CONFIG_SYS_CMA_CS3_SIZE, CS time normal, burst inhibit, ext xfer ack */
+#define CONFIG_SYS_OR3_PRELIM	((~(CONFIG_SYS_CMA_CS3_SIZE-1)&OR_AM_MSK)|OR_BI|OR_SETA)
+
+#endif
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/colibri_pxa270.h b/qemu/roms/u-boot/include/configs/colibri_pxa270.h
new file mode 100644
index 000000000..08bd276b4
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/colibri_pxa270.h
@@ -0,0 +1,218 @@
+/*
+ * Toradex Colibri PXA270 configuration file
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Board Configuration Options
+ */
+#define	CONFIG_CPU_PXA27X		1	/* Marvell PXA270 CPU */
+#define	CONFIG_SYS_TEXT_BASE		0x0
+
+/*
+ * Environment settings
+ */
+#define	CONFIG_ENV_OVERWRITE
+#define	CONFIG_SYS_MALLOC_LEN		(128 * 1024)
+#define	CONFIG_ARCH_CPU_INIT
+#define	CONFIG_BOOTCOMMAND						\
+	"if mmc init && fatload mmc 0 0xa0000000 uImage; then "		\
+		"bootm 0xa0000000; "					\
+	"fi; "								\
+	"if usb reset && fatload usb 0 0xa0000000 uImage; then "	\
+		"bootm 0xa0000000; "					\
+	"fi; "								\
+	"bootm 0x80000;"
+#define	CONFIG_BOOTARGS			"console=tty0 console=ttyS0,115200"
+#define	CONFIG_TIMESTAMP
+#define	CONFIG_BOOTDELAY		2	/* Autoboot delay */
+#define	CONFIG_CMDLINE_TAG
+#define	CONFIG_SETUP_MEMORY_TAGS
+#define	CONFIG_LZMA			/* LZMA compression support */
+#define	CONFIG_OF_LIBFDT
+
+/*
+ * Serial Console Configuration
+ */
+#define	CONFIG_PXA_SERIAL
+#define	CONFIG_FFUART			1
+#define CONFIG_CONS_INDEX		3
+#define	CONFIG_BAUDRATE			115200
+
+/*
+ * Bootloader Components Configuration
+ */
+#include <config_cmd_default.h>
+
+#define	CONFIG_CMD_NET
+#define	CONFIG_CMD_ENV
+#undef	CONFIG_CMD_IMLS
+#define	CONFIG_CMD_MMC
+#define	CONFIG_CMD_USB
+#define	CONFIG_CMD_FLASH
+
+/*
+ * Networking Configuration
+ *  chip on the Voipac PXA270 board
+ */
+#ifdef	CONFIG_CMD_NET
+#define	CONFIG_CMD_PING
+#define	CONFIG_CMD_DHCP
+
+#define	CONFIG_DRIVER_DM9000		1
+#define CONFIG_DM9000_BASE		0x08000000
+#define DM9000_IO			(CONFIG_DM9000_BASE)
+#define DM9000_DATA			(CONFIG_DM9000_BASE + 4)
+#define	CONFIG_NET_RETRY_COUNT		10
+
+#define	CONFIG_BOOTP_BOOTFILESIZE
+#define	CONFIG_BOOTP_BOOTPATH
+#define	CONFIG_BOOTP_GATEWAY
+#define	CONFIG_BOOTP_HOSTNAME
+#endif
+
+/*
+ * HUSH Shell Configuration
+ */
+#define	CONFIG_SYS_HUSH_PARSER		1
+
+#define	CONFIG_SYS_LONGHELP
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define	CONFIG_SYS_PROMPT		"$ "
+#else
+#endif
+#define	CONFIG_SYS_CBSIZE		256
+#define	CONFIG_SYS_PBSIZE		\
+	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define	CONFIG_SYS_MAXARGS		16
+#define	CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+#define	CONFIG_SYS_DEVICE_NULLDEV	1
+#define	CONFIG_CMDLINE_EDITING		1
+#define	CONFIG_AUTO_COMPLETE		1
+
+
+/*
+ * Clock Configuration
+ */
+#define	CONFIG_SYS_CPUSPEED		0x290		/* 520MHz */
+
+/*
+ * DRAM Map
+ */
+#define	CONFIG_NR_DRAM_BANKS		1		/* We have 1 bank of DRAM */
+#define	PHYS_SDRAM_1			0xa0000000	/* SDRAM Bank #1 */
+#define	PHYS_SDRAM_1_SIZE		0x04000000	/* 64 MB */
+
+#define	CONFIG_SYS_DRAM_BASE		0xa0000000	/* CS0 */
+#define	CONFIG_SYS_DRAM_SIZE		0x04000000	/* 64 MB DRAM */
+
+#define CONFIG_SYS_MEMTEST_START	0xa0400000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM */
+
+#define	CONFIG_SYS_LOAD_ADDR		PHYS_SDRAM_1
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define	CONFIG_SYS_INIT_SP_ADDR		0x5c010000
+
+/*
+ * NOR FLASH
+ */
+#ifdef	CONFIG_CMD_FLASH
+#define	PHYS_FLASH_1			0x00000000	/* Flash Bank #1 */
+#define	CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+
+#define	CONFIG_SYS_FLASH_CFI
+#define	CONFIG_FLASH_CFI_DRIVER		1
+
+#define	CONFIG_SYS_MAX_FLASH_SECT	(4 + 255)
+#define	CONFIG_SYS_MAX_FLASH_BANKS	1
+
+#define	CONFIG_SYS_FLASH_ERASE_TOUT	(25 * CONFIG_SYS_HZ)
+#define	CONFIG_SYS_FLASH_WRITE_TOUT	(25 * CONFIG_SYS_HZ)
+
+#define	CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+#define	CONFIG_SYS_FLASH_PROTECTION		1
+
+#define CONFIG_ENV_IS_IN_FLASH		1
+
+#else	/* No flash */
+#define	CONFIG_SYS_NO_FLASH
+#define	CONFIG_SYS_ENV_IS_NOWHERE
+#endif
+
+#define	CONFIG_SYS_MONITOR_BASE		0x0
+#define	CONFIG_SYS_MONITOR_LEN		0x80000
+
+#define	CONFIG_ENV_ADDR			\
+			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define	CONFIG_ENV_SIZE			0x40000
+#define	CONFIG_ENV_SECT_SIZE		0x40000
+#define CONFIG_ENV_ADDR_REDUND		(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND		(CONFIG_ENV_SIZE)
+
+/*
+ * GPIO settings
+ */
+#define	CONFIG_SYS_GPSR0_VAL	0x00000000
+#define	CONFIG_SYS_GPSR1_VAL	0x00020000
+#define	CONFIG_SYS_GPSR2_VAL	0x0002C000
+#define	CONFIG_SYS_GPSR3_VAL	0x00000000
+
+#define	CONFIG_SYS_GPCR0_VAL	0x00000000
+#define	CONFIG_SYS_GPCR1_VAL	0x00000000
+#define	CONFIG_SYS_GPCR2_VAL	0x00000000
+#define	CONFIG_SYS_GPCR3_VAL	0x00000000
+
+#define	CONFIG_SYS_GPDR0_VAL	0x08000000
+#define	CONFIG_SYS_GPDR1_VAL	0x0002A981
+#define	CONFIG_SYS_GPDR2_VAL	0x0202FC00
+#define	CONFIG_SYS_GPDR3_VAL	0x00000000
+
+#define	CONFIG_SYS_GAFR0_L_VAL	0x00100000
+#define	CONFIG_SYS_GAFR0_U_VAL	0x00C00010
+#define	CONFIG_SYS_GAFR1_L_VAL	0x999A901A
+#define	CONFIG_SYS_GAFR1_U_VAL	0xAAA00008
+#define	CONFIG_SYS_GAFR2_L_VAL	0xAAAAAAAA
+#define	CONFIG_SYS_GAFR2_U_VAL	0x0109A000
+#define	CONFIG_SYS_GAFR3_L_VAL	0x54000300
+#define	CONFIG_SYS_GAFR3_U_VAL	0x00024001
+
+#define	CONFIG_SYS_PSSR_VAL	0x30
+
+/*
+ * Clock settings
+ */
+#define	CONFIG_SYS_CKEN		0x00500240
+#define	CONFIG_SYS_CCCR		0x02000290
+
+/*
+ * Memory settings
+ */
+#define	CONFIG_SYS_MSC0_VAL	0x000095f2
+#define	CONFIG_SYS_MSC1_VAL	0x00007ff4
+#define	CONFIG_SYS_MSC2_VAL	0x00000000
+#define	CONFIG_SYS_MDCNFG_VAL	0x08000ac9
+#define	CONFIG_SYS_MDREFR_VAL	0x2013e01e
+#define	CONFIG_SYS_MDMRS_VAL	0x00320032
+#define	CONFIG_SYS_FLYCNFG_VAL	0x00000000
+#define	CONFIG_SYS_SXCNFG_VAL	0x40044004
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define	CONFIG_SYS_MECR_VAL	0x00000001
+#define	CONFIG_SYS_MCMEM0_VAL	0x00014307
+#define	CONFIG_SYS_MCMEM1_VAL	0x00014307
+#define	CONFIG_SYS_MCATT0_VAL	0x0001c787
+#define	CONFIG_SYS_MCATT1_VAL	0x0001c787
+#define	CONFIG_SYS_MCIO0_VAL	0x0001430f
+#define	CONFIG_SYS_MCIO1_VAL	0x0001430f
+
+#include "pxa-common.h"
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/colibri_t20_iris.h b/qemu/roms/u-boot/include/configs/colibri_t20_iris.h
new file mode 100644
index 000000000..6f9e08cac
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/colibri_t20_iris.h
@@ -0,0 +1,68 @@
+/*
+ *  Copyright (C) 2012 Lucas Stach
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "tegra20-common.h"
+
+/* Enable FDT support */
+#define CONFIG_DEFAULT_DEVICE_TREE	tegra20-colibri_t20_iris
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
+/* High-level configuration options */
+#define V_PROMPT                   "Tegra20 (Colibri) # "
+#define CONFIG_TEGRA_BOARD_STRING  "Toradex Colibri T20 on Iris"
+
+/* Board-specific serial config */
+#define CONFIG_TEGRA_ENABLE_UARTA
+#define CONFIG_TEGRA_UARTA_SDIO1
+#define CONFIG_SYS_NS16550_COM1    NV_PA_APB_UARTA_BASE
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* SD/MMC support */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_TEGRA_MMC
+#define CONFIG_CMD_MMC
+
+/* USB host support */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_TEGRA
+#define CONFIG_USB_ULPI
+#define CONFIG_USB_ULPI_VIEWPORT
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
+#define CONFIG_CMD_USB
+
+/* USB networking support */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+
+/* NAND support */
+#define CONFIG_CMD_NAND
+#define CONFIG_TEGRA_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+
+/* Environment in NAND, 64K is a bit excessive but erase block is 512K anyway */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET              (SZ_2M)
+#undef  CONFIG_ENV_SIZE /* undef size from tegra20-common.h */
+#define CONFIG_ENV_SIZE                (SZ_64K)
+
+/* Debug commands */
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_CACHE
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/controlcenterd.h b/qemu/roms/u-boot/include/configs/controlcenterd.h
new file mode 100644
index 000000000..868813f29
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/controlcenterd.h
@@ -0,0 +1,518 @@
+/*
+ * (C) Copyright 2013
+ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
+ *
+ * based on P1022DS.h
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifdef CONFIG_36BIT
+#define CONFIG_PHYS_64BIT
+#endif
+
+#ifdef CONFIG_SDCARD
+#define CONFIG_RAMBOOT_SDCARD
+#endif
+
+#ifdef CONFIG_SPIFLASH
+#define CONFIG_RAMBOOT_SPIFLASH
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE			/* BOOKE */
+#define CONFIG_E500			/* BOOKE e500 family */
+#define CONFIG_P1022
+#define CONFIG_CONTROLCENTERD
+#define CONFIG_MP			/* support multiple processors */
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENABLE_36BIT_PHYS
+#define CONFIG_FSL_LAW			/* Use common FSL init code */
+
+#ifdef CONFIG_TRAILBLAZER
+#define CONFIG_IDENT_STRING	" controlcenterd trailblazer 0.01"
+#else
+#define CONFIG_IDENT_STRING	" controlcenterd 0.01"
+#endif
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
+#endif
+
+#define CONFIG_L2_CACHE
+#define CONFIG_BTB
+
+#define CONFIG_SYS_CLK_FREQ	66666600
+#define CONFIG_DDR_CLK_FREQ	66666600
+
+#define CONFIG_SYS_RAMBOOT
+
+#ifdef CONFIG_TRAILBLAZER
+
+#define CONFIG_SYS_TEXT_BASE		0xf8fc0000
+#define CONFIG_RESET_VECTOR_ADDRESS	0xf8fffffc
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
+
+/*
+ * Config the L2 Cache
+ */
+#define CONFIG_SYS_INIT_L2_ADDR		0xf8fc0000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	0xff8fc0000ull
+#else
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#endif
+#define CONFIG_SYS_L2_SIZE		(256 << 10)
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+
+#else /* CONFIG_TRAILBLAZER */
+
+#define CONFIG_SYS_TEXT_BASE		0x11000000
+#define CONFIG_RESET_VECTOR_ADDRESS	0x1107fffc
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+
+#endif /* CONFIG_TRAILBLAZER */
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
+
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000	0x3fff_ffff	DDR			1G Cacheable
+ * 0xc000_0000	0xdfff_ffff	PCI Express Mem		512M non-cacheable
+ * 0xffc0_0000	0xffc2_ffff	PCI IO range		192K non-cacheable
+ *
+ * Localbus non-cacheable
+ * 0xe000_0000	0xe00f_ffff	eLBC			1M non-cacheable
+ * 0xf8fc0000	0xf8ff_ffff	L2 SRAM			256k Cacheable
+ * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K Cacheable TLB0
+ * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
+ */
+
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000 /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000 /* used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#ifdef CONFIG_TRAILBLAZER
+/* leave CCSRBAR at default, because u-boot expects it to be exactly there */
+#define CONFIG_SYS_CCSRBAR		CONFIG_SYS_CCSRBAR_DEFAULT
+#else
+#define CONFIG_SYS_CCSRBAR		0xffe00000
+#endif
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+#define CONFIG_SYS_MPC85xx_GPIO3_ADDR	(CONFIG_SYS_CCSRBAR+0xf200)
+
+/*
+ * DDR Setup
+ */
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_SDRAM_SIZE 1024
+#define CONFIG_VERY_BIG_RAM
+
+#define CONFIG_SYS_FSL_DDR3
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+#define CONFIG_SYS_MEMTEST_START	0x00000000
+#define CONFIG_SYS_MEMTEST_END		0x3fffffff
+
+#ifdef CONFIG_TRAILBLAZER
+#define CONFIG_SPD_EEPROM
+#define SPD_EEPROM_ADDRESS 0x52
+/*#define CONFIG_FSL_DDR_INTERACTIVE*/
+#endif
+
+/*
+ * Local Bus Definitions
+ */
+#define CONFIG_FSL_ELBC			/* Has Enhanced localbus controller */
+
+#define CONFIG_SYS_ELBC_BASE		0xe0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_ELBC_BASE_PHYS	0xfe0000000ull
+#else
+#define CONFIG_SYS_ELBC_BASE_PHYS	CONFIG_SYS_ELBC_BASE
+#endif
+
+#define CONFIG_UART_BR_PRELIM  \
+	(BR_PHYS_ADDR((CONFIG_SYS_ELBC_BASE_PHYS)) | BR_PS_8 | BR_V)
+#define CONFIG_UART_OR_PRELIM	(OR_AM_32KB | 0xff7)
+
+#define CONFIG_SYS_BR0_PRELIM	0 /* CS0 was originally intended for FPGA */
+#define CONFIG_SYS_OR0_PRELIM	0 /* debugging, was never used */
+
+#define CONFIG_SYS_BR1_PRELIM	CONFIG_UART_BR_PRELIM
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_UART_OR_PRELIM
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX		2
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+/* Probing DP501 I2C-Bridge will hang */
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x30}, {0, 0x37}, {0, 0x3a}, \
+					  {0, 0x3b}, {0, 0x50} }
+
+#define CONFIG_PCA9698			/* NXP PCA9698 */
+
+#define CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+
+#ifndef CONFIG_TRAILBLAZER
+/*
+ * eSPI - Enhanced SPI
+ */
+#define CONFIG_HARD_SPI
+#define CONFIG_FSL_ESPI
+
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED		10000000
+#define CONFIG_SF_DEFAULT_MODE		0
+#endif
+
+/*
+ * TPM
+ */
+#define CONFIG_TPM_ATMEL_TWI
+#define CONFIG_TPM
+#define CONFIG_TPM_AUTH_SESSIONS
+#define CONFIG_SHA1
+#define CONFIG_CMD_TPM
+
+/*
+ * MMC
+ */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_MMC
+
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
+
+
+#ifndef CONFIG_TRAILBLAZER
+
+/*
+ * Video
+ */
+#define CONFIG_FSL_DIU_FB
+#define CONFIG_SYS_DIU_ADDR	(CONFIG_SYS_CCSRBAR + 0x10000)
+#define CONFIG_VIDEO
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_CMD_BMP
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+#define CONFIG_PCI			/* Enable PCI/PCIE */
+#define CONFIG_PCIE1			/* PCIE controler 1 (slot 1) */
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
+#define CONFIG_CMD_PCI
+
+#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
+#define CONFIG_FSL_PCIE_RESET		/* need PCIe reset errata */
+
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0xc0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc40000000ull
+#else
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc0000000
+#endif
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc20000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xfffc20000ull
+#else
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xffc20000
+#endif
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+
+/*
+ * SATA
+ */
+#define CONFIG_LIBATA
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+
+#define CONFIG_FSL_SATA
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
+
+/*
+ * Ethernet
+ */
+#define CONFIG_TSEC_ENET
+
+#define CONFIG_TSECV2
+
+#define CONFIG_MII			/* MII PHY management */
+#define CONFIG_TSEC1		1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define CONFIG_TSEC2		1
+#define CONFIG_TSEC2_NAME	"eTSEC2"
+
+#define TSEC1_PHY_ADDR		0
+#define TSEC2_PHY_ADDR		1
+
+#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+
+#define CONFIG_ETHPRIME		"eTSEC1"
+
+#define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
+
+/*
+ * USB
+ */
+#define CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+
+#define CONFIG_HAS_FSL_DR_USB
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+
+#endif /* CONFIG_TRAILBLAZER */
+
+/*
+ * Environment
+ */
+#if defined(CONFIG_TRAILBLAZER)
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE		0x2000		/* 8KB */
+#undef CONFIG_CMD_SAVEENV
+#elif defined(CONFIG_RAMBOOT_SPIFLASH)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS	0
+#define CONFIG_ENV_SPI_CS	0
+#define CONFIG_ENV_SPI_MAX_HZ	10000000
+#define CONFIG_ENV_SPI_MODE	0
+#define CONFIG_ENV_SIZE		0x2000		/* 8KB */
+#define CONFIG_ENV_OFFSET	0x100000	/* 1MB */
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#elif defined(CONFIG_RAMBOOT_SDCARD)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_FSL_FIXED_MMC_LOCATION
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_SYS_MMC_ENV_DEV	0
+#endif
+
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+/*
+ * Command line configuration.
+ */
+#ifndef CONFIG_TRAILBLAZER
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
+#endif /* CONFIG_TRAILBLAZER */
+
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	16
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+#include <config_cmd_default.h>
+
+#ifndef CONFIG_TRAILBLAZER
+
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ERRATA
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
+
+/*
+ * Board initialisation callbacks
+ */
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_MISC_INIT_R
+#define CONFIG_LAST_STAGE_INIT
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE
+
+#else /* CONFIG_TRAILBLAZER */
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_LAST_STAGE_INIT
+#undef CONFIG_CMD_BOOTM
+
+#endif /* CONFIG_TRAILBLAZER */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_HW_WATCHDOG
+#define CONFIG_LOADS_ECHO
+#define CONFIG_SYS_LOADS_BAUD_CHANGE
+#define CONFIG_DOS_PARTITION
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Linux Memory map */
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+/*
+ * Environment Configuration
+ */
+
+#ifdef CONFIG_TRAILBLAZER
+
+#define CONFIG_BOOTDELAY	0	/* -1 disables auto-boot */
+#define CONFIG_BAUDRATE	115200
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"mp_holdoff=1\0"
+
+#else
+
+#define CONFIG_HOSTNAME		controlcenterd
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP */
+
+#define CONFIG_LOADADDR		1000000
+
+#define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
+
+#define CONFIG_BAUDRATE	115200
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"netdev=eth0\0"						\
+	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
+	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
+	"tftpflash=tftpboot $loadaddr $uboot && "		\
+		"protect off $ubootaddr +$filesize && "		\
+		"erase $ubootaddr +$filesize && "		\
+		"cp.b $loadaddr $ubootaddr $filesize && "	\
+		"protect on $ubootaddr +$filesize && "		\
+		"cmp.b $loadaddr $ubootaddr $filesize\0"	\
+	"consoledev=ttyS1\0"					\
+	"ramdiskaddr=2000000\0"					\
+	"ramdiskfile=rootfs.ext2.gz.uboot\0"			\
+	"fdtaddr=c00000\0"					\
+	"fdtfile=controlcenterd.dtb\0"				\
+	"bdev=sda3\0"
+
+/* these are used and NUL-terminated in env_default.h */
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv bootargs root=/dev/nfs rw "				\
+	"nfsroot=$serverip:$rootpath "					\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs $videobootargs;"	\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+	"setenv bootargs root=/dev/ram rw "				\
+	"console=$consoledev,$baudrate $othbootargs $videobootargs;"	\
+	"tftp $ramdiskaddr $ramdiskfile;"				\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_RAMBOOTCOMMAND
+
+#endif /* CONFIG_TRAILBLAZER */
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/coreboot.h b/qemu/roms/u-boot/include/configs/coreboot.h
new file mode 100644
index 000000000..d1d732f21
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/coreboot.h
@@ -0,0 +1,308 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2008
+ * Graeme Russ, graeme.russ@gmail.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/ibmpc.h>
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_SYS_COREBOOT
+#define CONFIG_SHOW_BOOT_PROGRESS
+#define CONFIG_LAST_STAGE_INIT
+#define CONFIG_SYS_VSNPRINTF
+#define CONFIG_ZBOOT_32
+#define CONFIG_PHYSMEM
+#define CONFIG_SYS_EARLY_PCI_INIT
+
+#define CONFIG_LMB
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+#define CONFIG_DEFAULT_DEVICE_TREE	link
+
+#define CONFIG_BOOTSTAGE
+#define CONFIG_BOOTSTAGE_REPORT
+#define CONFIG_BOOTSTAGE_FDT
+#define CONFIG_CMD_BOOTSTAGE
+/* Place to stash bootstage data from first-stage U-Boot */
+#define CONFIG_BOOTSTAGE_STASH		0x0110f000
+#define CONFIG_BOOTSTAGE_STASH_SIZE	0x7fc
+#define CONFIG_BOOTSTAGE_USER_COUNT	60
+
+#define CONFIG_LZO
+#undef CONFIG_ZLIB
+#undef CONFIG_GZIP
+
+/*-----------------------------------------------------------------------
+ * Watchdog Configuration
+ */
+#undef CONFIG_WATCHDOG
+#undef CONFIG_HW_WATCHDOG
+
+/* SATA AHCI storage */
+
+#define CONFIG_SCSI_AHCI
+
+#ifdef CONFIG_SCSI_AHCI
+#define CONFIG_LIBATA
+#define CONFIG_SYS_64BIT_LBA
+#define CONFIG_SATA_INTEL		1
+#define CONFIG_SCSI_DEV_LIST		{PCI_VENDOR_ID_INTEL, \
+			PCI_DEVICE_ID_INTEL_NM10_AHCI},	      \
+	{PCI_VENDOR_ID_INTEL,		\
+			PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \
+	{PCI_VENDOR_ID_INTEL, \
+			PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \
+	{PCI_VENDOR_ID_INTEL,		\
+			PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	2
+#define CONFIG_SYS_SCSI_MAX_LUN		1
+#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+					 CONFIG_SYS_SCSI_MAX_LUN)
+#endif
+
+/* Generic TPM interfaced through LPC bus */
+#define CONFIG_TPM
+#define CONFIG_TPM_TIS_LPC
+#define CONFIG_TPM_TIS_BASE_ADDRESS        0xfed40000
+
+/*-----------------------------------------------------------------------
+ * Real Time Clock Configuration
+ */
+#define CONFIG_RTC_MC146818
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS	0
+#define CONFIG_SYS_ISA_IO      CONFIG_SYS_ISA_IO_BASE_ADDRESS
+
+/*-----------------------------------------------------------------------
+ * Serial Configuration
+ */
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		1843200
+#define CONFIG_BAUDRATE			9600
+#define CONFIG_SYS_BAUDRATE_TABLE	{300, 600, 1200, 2400, 4800, \
+					 9600, 19200, 38400, 115200}
+#define CONFIG_SYS_NS16550_COM1	UART0_BASE
+#define CONFIG_SYS_NS16550_COM2	UART1_BASE
+#define CONFIG_SYS_NS16550_PORT_MAPPED
+
+#define CONFIG_STD_DEVICES_SETTINGS     "stdin=usbkbd,vga,eserial0\0" \
+					"stdout=vga,eserial0,cbmem\0" \
+					"stderr=vga,eserial0,cbmem\0"
+
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_STDIO_DEREGISTER
+#define CONFIG_CBMEM_CONSOLE
+
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_COMMAND_HISTORY
+#define CONFIG_AUTOCOMPLETE
+
+#define CONFIG_SUPPORT_VFAT
+/************************************************************
+ * ATAPI support (experimental)
+ ************************************************************/
+#define CONFIG_ATAPI
+
+/************************************************************
+ * DISK Partition support
+ ************************************************************/
+#define CONFIG_EFI_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION
+#define CONFIG_ISO_PARTITION		/* Experimental */
+
+#define CONFIG_CMD_PART
+#define CONFIG_CMD_CBFS
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+#define CONFIG_PARTITION_UUIDS
+
+/*-----------------------------------------------------------------------
+ * Video Configuration
+ */
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_COREBOOT
+#define CONFIG_VIDEO_SW_CURSOR
+#define VIDEO_FB_16BPP_WORD_SWAP
+#define CONFIG_I8042_KBD
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+
+/* x86 GPIOs are accessed through a PCI device */
+#define CONFIG_INTEL_ICH6_GPIO
+
+/*-----------------------------------------------------------------------
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_TRACE
+#define CONFIG_CMD_TRACE
+#define CONFIG_TRACE_BUFFER_SIZE	(16 << 20)
+#define CONFIG_TRACE_EARLY_SIZE		(8 << 20)
+#define CONFIG_TRACE_EARLY
+#define CONFIG_TRACE_EARLY_ADDR		0x01400000
+
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_CONSOLE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ECHO
+#undef CONFIG_CMD_FLASH
+#define CONFIG_CMD_FPGA
+#define CONFIG_CMD_GPIO
+#define CONFIG_CMD_IMI
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_IO
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ITEST
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_SETGETDCR
+#define CONFIG_CMD_SOURCE
+#define CONFIG_CMD_TIME
+#define CONFIG_CMD_GETTIME
+#define CONFIG_CMD_XIMG
+#define CONFIG_CMD_SCSI
+
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+
+#define CONFIG_CMD_ZBOOT
+
+#define CONFIG_BOOTDELAY	2
+#define CONFIG_BOOTARGS		\
+	"root=/dev/sdb3 init=/sbin/init rootwait ro"
+#define CONFIG_BOOTCOMMAND	\
+	"ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
+
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE			115200
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT			"boot > "
+#define CONFIG_SYS_CBSIZE			256
+#define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE + \
+						 sizeof(CONFIG_SYS_PROMPT) + \
+						 16)
+#define CONFIG_SYS_MAXARGS			16
+#define CONFIG_SYS_BARGSIZE			CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START		0x00100000
+#define CONFIG_SYS_MEMTEST_END			0x01000000
+#define CONFIG_SYS_LOAD_ADDR			0x100000
+
+/*-----------------------------------------------------------------------
+ * SDRAM Configuration
+ */
+#define CONFIG_NR_DRAM_BANKS			4
+
+/* CONFIG_SYS_SDRAM_DRCTMCTL Overrides the following*/
+#undef CONFIG_SYS_SDRAM_PRECHARGE_DELAY
+#undef CONFIG_SYS_SDRAM_RAS_CAS_DELAY
+#undef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
+#undef CONFIG_SYS_SDRAM_CAS_LATENCY_3T
+
+/*-----------------------------------------------------------------------
+ * CPU Features
+ */
+
+#define CONFIG_SYS_X86_TSC_TIMER
+#define CONFIG_SYS_PCAT_INTERRUPTS
+#define CONFIG_SYS_PCAT_TIMER
+#define CONFIG_SYS_NUM_IRQS			16
+
+/*-----------------------------------------------------------------------
+ * Memory organization:
+ * 32kB Stack
+ * 16kB Cache-As-RAM @ 0x19200000
+ * 256kB Monitor
+ * (128kB + Environment Sector Size) malloc pool
+ */
+#define CONFIG_SYS_STACK_SIZE			(32 * 1024)
+#define CONFIG_SYS_CAR_ADDR			0x19200000
+#define CONFIG_SYS_CAR_SIZE			(16 * 1024)
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN			(256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN			(0x20000 + 128 * 1024)
+
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/*-----------------------------------------------------------------------
+ * FLASH configuration
+ */
+#define CONFIG_ICH_SPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_MACRONIX
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SPI_FLASH_GIGADEVICE
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SF_TEST
+#define CONFIG_CMD_SPI
+#define CONFIG_SPI
+
+/*-----------------------------------------------------------------------
+ * Environment configuration
+ */
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE			0x01000
+
+/*-----------------------------------------------------------------------
+ * PCI configuration
+ */
+#define CONFIG_PCI
+
+/*-----------------------------------------------------------------------
+ * USB configuration
+ */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_PCI
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS     12
+#define CONFIG_USB_MAX_CONTROLLER_COUNT        2
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_KEYBOARD
+#define CONFIG_SYS_USB_EVENT_POLL
+
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_SMSC95XX
+
+#define CONFIG_CMD_USB
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	CONFIG_STD_DEVICES_SETTINGS
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/corenet_ds.h b/qemu/roms/u-boot/include/configs/corenet_ds.h
new file mode 100644
index 000000000..c8b7c2dff
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/corenet_ds.h
@@ -0,0 +1,749 @@
+/*
+ * Copyright 2009-2012 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Corenet DS style board configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
+#include "../board/freescale/common/ics307_clk.h"
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
+#if defined(CONFIG_P3041DS)
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg
+#elif defined(CONFIG_P4080DS)
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg
+#elif defined(CONFIG_P5020DS)
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg
+#elif defined(CONFIG_P5040DS)
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg
+#endif
+#endif
+
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+/* Set 1M boot space */
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
+		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CONFIG_SYS_NO_FLASH
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE
+#define CONFIG_E500			/* BOOKE e500 family */
+#define CONFIG_E500MC			/* BOOKE e500mc family */
+#define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
+#define CONFIG_MP			/* support multiple processors */
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xeff40000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+#define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC		CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_FSL_ELBC			/* Has Enhanced localbus controller */
+#define CONFIG_PCI			/* Enable PCI/PCIE */
+#define CONFIG_PCIE1			/* PCIE controler 1 */
+#define CONFIG_PCIE2			/* PCIE controler 2 */
+#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
+
+#define CONFIG_FSL_LAW			/* Use common FSL init code */
+
+#define CONFIG_ENV_OVERWRITE
+
+#ifdef CONFIG_SYS_NO_FLASH
+#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+#else
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#endif
+
+#if defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS              0
+#define CONFIG_ENV_SPI_CS               0
+#define CONFIG_ENV_SPI_MAX_HZ           10000000
+#define CONFIG_ENV_SPI_MODE             0
+#define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
+#define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
+#define CONFIG_ENV_SECT_SIZE            0x10000
+#elif defined(CONFIG_SDCARD)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_FSL_FIXED_MMC_LOCATION
+#define CONFIG_SYS_MMC_ENV_DEV          0
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_OFFSET		(512 * 1658)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE			CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET		(7 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+#define CONFIG_ENV_IS_IN_REMOTE
+#define CONFIG_ENV_ADDR		0xffe20000
+#define CONFIG_ENV_SIZE		0x2000
+#elif defined(CONFIG_ENV_IS_NOWHERE)
+#define CONFIG_ENV_SIZE		0x2000
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+#endif
+
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk() /* sysclk for MPC85xx */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BACKSIDE_L2_CACHE
+#define CONFIG_SYS_INIT_L2CSR0		L2CSR0_L2E
+#define CONFIG_BTB			/* toggle branch predition */
+#define	CONFIG_DDR_ECC
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#endif
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP		64	/* number of TLB1 entries */
+#endif
+
+#define CONFIG_POST CONFIG_SYS_POST_MEMORY	/* test POST memory test */
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_PANIC_HANG	/* do not reset board on panic */
+
+/*
+ *  Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR		CONFIG_RAMBOOT_TEXT_BASE
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_L3_ADDR_PHYS	(0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
+#else
+#define CONFIG_SYS_INIT_L3_ADDR_PHYS	CONFIG_SYS_INIT_L3_ADDR
+#endif
+#define CONFIG_SYS_L3_SIZE		(1024 << 10)
+#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_DCSRBAR		0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
+#endif
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM	0
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(4 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_FSL_DDR3
+
+#define CONFIG_SYS_SPD_BUS_NUM	1
+#define SPD_EEPROM_ADDRESS1	0x51
+#define SPD_EEPROM_ADDRESS2	0x52
+#define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1	/* for p3041/p5010 */
+#define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
+
+/*
+ * Local Bus Definitions
+ */
+
+/* Set the local bus clock 1/8 of platform clock */
+#define CONFIG_SYS_LBC_LCRR		LCRR_CLKDIV_8
+
+#define CONFIG_SYS_FLASH_BASE		0xe0000000	/* Start of PromJet */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_FLASH_BASE_PHYS	0xfe0000000ull
+#else
+#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+#endif
+
+#define CONFIG_SYS_FLASH_BR_PRELIM \
+		(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \
+		 | BR_PS_16 | BR_V)
+#define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
+					| OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
+
+#define CONFIG_SYS_BR1_PRELIM \
+	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
+#define CONFIG_SYS_OR1_PRELIM	0xf8000ff7
+
+#define PIXIS_BASE		0xffdf0000	/* PIXIS registers */
+#ifdef CONFIG_PHYS_64BIT
+#define PIXIS_BASE_PHYS		0xfffdf0000ull
+#else
+#define PIXIS_BASE_PHYS		PIXIS_BASE
+#endif
+
+#define CONFIG_SYS_BR3_PRELIM	(BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR3_PRELIM	0xffffeff7	/* 32KB but only 4k mapped */
+
+#define PIXIS_LBMAP_SWITCH	7
+#define PIXIS_LBMAP_MASK	0xf0
+#define PIXIS_LBMAP_SHIFT	4
+#define PIXIS_LBMAP_ALTBANK	0x40
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS 	45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE	/* start of monitor */
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+/* Nand Flash */
+#ifdef CONFIG_NAND_FSL_ELBC
+#define CONFIG_SYS_NAND_BASE		0xffa00000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_NAND_BASE_PHYS	0xfffa00000ull
+#else
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#endif
+
+#define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+#define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
+
+/* NAND flash config */
+#define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+			       | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+			       | BR_PS_8	       /* Port Size = 8 bit */ \
+			       | BR_MS_FCM	       /* MSEL = FCM */ \
+			       | BR_V)		       /* valid */
+#define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000	      /* length 256K */ \
+			       | OR_FCM_PGS	       /* Large Page*/ \
+			       | OR_FCM_CSCT \
+			       | OR_FCM_CST \
+			       | OR_FCM_CHT \
+			       | OR_FCM_SCY_1 \
+			       | OR_FCM_TRLX \
+			       | OR_FCM_EHTR)
+
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
+#define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
+#else
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
+#define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
+#define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#endif
+#else
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
+#endif /* CONFIG_NAND_FSL_ELBC */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#else
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS	CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
+#endif
+#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000	/* Size of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x118100
+
+/*
+ * RapidIO
+ */
+#define CONFIG_SYS_SRIO1_MEM_VIRT	0xa0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
+#else
+#define CONFIG_SYS_SRIO1_MEM_PHYS	0xa0000000
+#endif
+#define CONFIG_SYS_SRIO1_MEM_SIZE	0x10000000	/* 256M */
+
+#define CONFIG_SYS_SRIO2_MEM_VIRT	0xb0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
+#else
+#define CONFIG_SYS_SRIO2_MEM_PHYS	0xb0000000
+#endif
+#define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000	/* 256M */
+
+/*
+ * for slave u-boot IMAGE instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000	/* 512K */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
+/*
+ * for slave UCODE and ENV instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000	/* 256K */
+
+/* slave core release by master*/
+#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
+#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
+
+/*
+ * SRIO_PCIE_BOOT - SLAVE
+ */
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
+		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
+#endif
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#define CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED         10000000
+#define CONFIG_SF_DEFAULT_MODE          0
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#else
+#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0x80000000
+#endif
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
+#else
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xf8000000
+#endif
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 2, Slot 2, tgtid 2, Base address 201000 */
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
+#else
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
+#endif
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
+#else
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xf8010000
+#endif
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 3, Slot 1, tgtid 1, Base address 202000 */
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0xc0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc40000000ull
+#else
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xc0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc0000000
+#endif
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
+#else
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xf8020000
+#endif
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 4, Base address 203000 */
+#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_PHYS	0xc60000000ull
+#define CONFIG_SYS_PCIE4_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
+#define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
+
+/* Qman/Bman */
+#define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS	10
+#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
+#else
+#define CONFIG_SYS_BMAN_MEM_PHYS	CONFIG_SYS_BMAN_MEM_BASE
+#endif
+#define CONFIG_SYS_BMAN_MEM_SIZE	0x00200000
+#define CONFIG_SYS_QMAN_NUM_PORTALS	10
+#define CONFIG_SYS_QMAN_MEM_BASE	0xf4200000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_QMAN_MEM_PHYS	0xff4200000ull
+#else
+#define CONFIG_SYS_QMAN_MEM_PHYS	CONFIG_SYS_QMAN_MEM_BASE
+#endif
+#define CONFIG_SYS_QMAN_MEM_SIZE	0x00200000
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+/* Default address of microcode for the Linux Fman driver */
+#if defined(CONFIG_SPIFLASH)
+/*
+ * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
+ * env, so we got 0x110000.
+ */
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_FMAN_FW_ADDR	0x110000
+#elif defined(CONFIG_SDCARD)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 825KB (1650 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+#define CONFIG_SYS_FMAN_FW_ADDR	(512 * 1680)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_FMAN_FW_ADDR	(8 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+/*
+ * Slave has no ucode locally, it can fetch this from remote. When implementing
+ * in two corenet boards, slave's ucode could be stored in master's memory
+ * space, the address can be mapped from slave TLB->slave LAW->
+ * slave SRIO or PCIE outbound window->master inbound window->
+ * master LAW->the ucode address in master's memory space.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
+#define CONFIG_SYS_FMAN_FW_ADDR	0xFFE00000
+#else
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_FMAN_FW_ADDR		0xEFF00000
+#endif
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_TERANETICS
+#endif
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+#define CONFIG_E1000
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif	/* CONFIG_PCI */
+
+/* SATA */
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
+
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR	0x1c
+#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR	0x1d
+#define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR	0x1e
+#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR	0x1f
+#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR	4
+
+#define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR	0x1c
+#define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR	0x1d
+#define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR	0x1e
+#define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR	0x1f
+#define CONFIG_SYS_FM2_10GEC1_PHY_ADDR	0
+
+#define CONFIG_SYS_TBIPA_VALUE	8
+#define CONFIG_MII		/* MII PHY management */
+#define CONFIG_ETHPRIME		"FM1@DTSEC1"
+#define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ERRATA
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
+
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
+/*
+* USB
+*/
+#define CONFIG_HAS_FSL_DR_USB
+#define CONFIG_HAS_FSL_MPH_USB
+
+#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_CMD_EXT2
+#endif
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+#define CONFIG_BOOTDELAY 	10	/* -1 disables auto-boot */
+
+#define CONFIG_BAUDRATE	115200
+
+#ifdef CONFIG_P4080DS
+#define __USB_PHY_TYPE	ulpi
+#else
+#define __USB_PHY_TYPE	utmi
+#endif
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hwconfig=fsl_ddr:ctlr_intlv=cacheline,"		\
+	"bank_intlv=cs0_cs1;"					\
+	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
+	"usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
+	"netdev=eth0\0"						\
+	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
+	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
+	"tftpflash=tftpboot $loadaddr $uboot && "		\
+	"protect off $ubootaddr +$filesize && "			\
+	"erase $ubootaddr +$filesize && "			\
+	"cp.b $loadaddr $ubootaddr $filesize && "		\
+	"protect on $ubootaddr +$filesize && "			\
+	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
+	"consoledev=ttyS0\0"					\
+	"ramdiskaddr=2000000\0"					\
+	"ramdiskfile=p4080ds/ramdisk.uboot\0"			\
+	"fdtaddr=c00000\0"					\
+	"fdtfile=p4080ds/p4080ds.dtb\0"				\
+	"bdev=sda3\0"						\
+	"c=ffe\0"
+
+#define CONFIG_HDBOOT					\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND			\
+	"setenv bootargs root=/dev/nfs rw "	\
+	"nfsroot=$serverip:$rootpath "		\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"		\
+	"tftp $fdtaddr $fdtfile;"		\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND				\
+	"setenv bootargs root=/dev/ram rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $ramdiskaddr $ramdiskfile;"		\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_HDBOOT
+
+#include <asm/fsl_secure_boot.h>
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/corvus.h b/qemu/roms/u-boot/include/configs/corvus.h
new file mode 100644
index 000000000..959e188d9
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/corvus.h
@@ -0,0 +1,164 @@
+/*
+ * Common board functions for siemens AT91SAM9G45 based boards
+ * (C) Copyright 2013 Siemens AG
+ *
+ * Based on:
+ * U-Boot file: include/configs/at91sam9m10g45ek.h
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/hardware.h>
+
+#define MACH_TYPE_CORVUS               2066
+
+/*
+ * Warning: changing CONFIG_SYS_TEXT_BASE requires
+ * adapting the initial boot program.
+ * Since the linker has to swallow that define, we must use a pure
+ * hex number here!
+ */
+
+#define CONFIG_SYS_TEXT_BASE  0x73f00000
+
+#define CONFIG_AT91_LEGACY
+#define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK      32768
+#define CONFIG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
+
+#define CONFIG_AT91FAMILY
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_OF_LIBFDT
+
+/* general purpose I/O */
+#define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
+#define CONFIG_AT91_GPIO
+#define CONFIG_AT91_GPIO_PULLUP	1	/* keep pullups on peripheral pins */
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
+#define CONFIG_USART_ID			ATMEL_ID_SYS
+
+/* LED */
+#define CONFIG_AT91_LED
+#define CONFIG_RED_LED		AT91_PIN_PD31	/* this is the user1 led */
+#define CONFIG_GREEN_LED	AT91_PIN_PD0	/* this is the user2 led */
+
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_LOADS
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_USB
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE           ATMEL_BASE_CS6
+#define CONFIG_SYS_SDRAM_SIZE		0x08000000
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
+
+/* No NOR flash */
+#define CONFIG_SYS_NO_FLASH
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE		1
+#define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3
+#define CONFIG_SYS_NAND_DBW_8
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PC14
+#define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PC8
+
+#endif
+
+/* Ethernet */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_RETRY_COUNT		20
+#define CONFIG_AT91_WANTS_COMMON_PHY
+
+/* USB */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_ATMEL
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	2
+#define CONFIG_DOS_PARTITION
+#define CONFIG_USB_STORAGE
+
+#define CONFIG_SYS_LOAD_ADDR		0x72000000	/* load address */
+
+/* bootstrap + u-boot + env in nandflash */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		0x100000
+#define CONFIG_ENV_OFFSET_REDUND	0x180000
+#define CONFIG_ENV_SIZE			0x20000
+
+#define CONFIG_BOOTCOMMAND						\
+	"nand read 0x70000000 0x200000 0x300000;"			\
+	"bootm 0x70000000"
+#define CONFIG_BOOTARGS							\
+	"console=ttyS0,115200 earlyprintk "				\
+	"mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,"		\
+	"256k(env),256k(env_redundant),256k(spare),"			\
+	"512k(dtb),6M(kernel)ro,-(rootfs) "				\
+	"root=/dev/mtdblock7 rw rootfstype=jffs2"
+
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_SYS_PROMPT		"U-Boot> "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE +	\
+				 sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN	ROUND(3 * CONFIG_ENV_SIZE + \
+				128*1024, 0x1000)
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/cpci5200.h b/qemu/roms/u-boot/include/configs/cpci5200.h
new file mode 100644
index 000000000..ec926fd22
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/cpci5200.h
@@ -0,0 +1,390 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+
+ */
+
+/*************************************************************************
+ * (c) 2005 esd gmbh Hannover
+ *
+ *
+ * from IceCube.h file
+ * by Reinhard Arlt reinhard.arlt@esd-electronics.com
+ *
+ *************************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5200		1	/* This is an MPC5200 CPU */
+#define CONFIG_ICECUBE		1	/* ... on IceCube board	  */
+#define CONFIG_CPCI5200		1	/* ... on CPCI5200  board */
+#define CONFIG_MPC5200_DDR	1	/* ... use DDR RAM	  */
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xFFF00000	/* Standard: boot high */
+#endif
+
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000	/* ... running at 33.000000MHz */
+
+#define CONFIG_HIGH_BATS	1	/* High BATs supported 	  */
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
+#define CONFIG_BAUDRATE		9600	/* ... at 115200 bps */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*
+ * PCI Mapping:
+ * 0x40000000 - 0x4fffffff - PCI Memory
+ * 0x50000000 - 0x50ffffff - PCI IO Space
+ */
+#if 1
+#define CONFIG_PCI		1
+#if 1
+#define CONFIG_PCI_PNP		1
+#endif
+#define CONFIG_PCI_SCAN_SHOW	1
+#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1
+
+#define CONFIG_PCI_MEM_BUS	0x40000000
+#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE	0x10000000
+
+#define CONFIG_PCI_IO_BUS	0x50000000
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0x01000000
+#endif
+
+#define CONFIG_MII
+#if 0				/* test-only !!! */
+#define CONFIG_EEPRO100		1
+#define CONFIG_SYS_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100	*/
+#define CONFIG_NS8382X		1
+#endif
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+/* USB */
+#if 0
+#define CONFIG_USB_OHCI
+#define CONFIG_USB_STORAGE
+#endif
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#if defined(CONFIG_PCI)
+#define CONFIG_CMD_PCI
+#endif
+
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_DATE
+
+#if (CONFIG_SYS_TEXT_BASE == 0xFF000000)	/* Boot low with 16 MB Flash */
+#   define CONFIG_SYS_LOWBOOT		1
+#   define CONFIG_SYS_LOWBOOT16	1
+#endif
+#if (CONFIG_SYS_TEXT_BASE == 0xFF800000)	/* Boot low with  8 MB Flash */
+#   define CONFIG_SYS_LOWBOOT		1
+#   define CONFIG_SYS_LOWBOOT08	1
+#endif
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	3	/* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Welcome to esd CPU CPCI/5200;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS \
+	"netdev=eth0\0" \
+	"flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
+	"flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
+	"net_vxworks=phypower 1;sleep 2;tftp ${loadaddr} ${image};run vxworks_args;bootvx\0" \
+	"vxworks_args=setenv bootargs fec(0,0)${host}:${image} h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script}\0" \
+	"ata_vxworks_args=setenv bootargs /ata0/vxWorks h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script} o=fec0 \0" \
+	"loadaddr=01000000\0" \
+	"serverip=192.168.2.99\0" \
+	"gatewayip=10.0.0.79\0" \
+	"user=mu\0" \
+	"target=cpci5200.esd\0" \
+	"script=cpci5200.bat\0" \
+	"image=/tftpboot/vxWorks_cpci5200\0" \
+	"ipaddr=10.0.13.196\0" \
+	"netmask=255.255.0.0\0" \
+	""
+
+#define CONFIG_BOOTCOMMAND	"run flash_vxworks0"
+
+#define CONFIG_RTC_M48T35A	1	/* ST Electronics M48 timekeeper */
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xfd010000
+#define CONFIG_SYS_NVRAM_SIZE		32*1024
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+#define CONFIG_SYS_I2C_MODULE		1	/* Select I2C module #1 or #2 */
+
+#define CONFIG_SYS_I2C_SPEED		86000	/* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	20
+#define CONFIG_SYS_I2C_MULTI_EEPROMS		1
+/*
+ * Flash configuration
+ */
+
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant	     */
+#define CONFIG_SYS_FLASH_BASE		0xFE000000
+#define CONFIG_SYS_FLASH_SIZE		0x02000000
+#define CONFIG_SYS_FLASH_INCREMENT	0x01000000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00000000)
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max num of memory banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	128
+
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* use hardware protection	     */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)  */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
+
+/*
+ * Environment settings
+ */
+#if 1				/* test-only */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_SIZE		0x20000
+#define CONFIG_ENV_SECT_SIZE	0x20000
+#define CONFIG_ENV_OVERWRITE	1
+#else
+#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CONFIG_ENV_OFFSET		0x0000	/* environment starts at the beginning of the EEPROM */
+#define CONFIG_ENV_SIZE		0x0400	/* 8192 bytes may be used for env vars */
+				   /* total size of a CAT24WC32 is 8192 bytes */
+#define CONFIG_ENV_OVERWRITE	1
+#endif
+
+/*
+ * Memory map
+ */
+#define CONFIG_SYS_MBAR		0xF0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
+
+/* Use SRAM until RAM will be available */
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC	1
+#define CONFIG_MPC5xxx_FEC_MII100
+/*
+ * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
+ */
+/* #define CONFIG_FEC_10MBIT 1 */
+#define CONFIG_PHY_ADDR		0x00
+#define CONFIG_UDP_CHECKSUM	1
+
+/*
+ * GPIO configuration
+ */
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x01052444
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory	    */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
+
+#define CONFIG_SYS_VXWORKS_MAC_PTR	0x00000000	/* Pass Ethernet MAC to VxWorks */
+
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*
+ * Various low-level settings
+ */
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
+
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_CFG		0x0004DD00
+
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
+
+#define CONFIG_SYS_CS1_START		0xfd000000
+#define CONFIG_SYS_CS1_SIZE		0x00010000
+#define CONFIG_SYS_CS1_CFG		0x10101410
+
+#define CONFIG_SYS_CS3_START		0xfd010000
+#define CONFIG_SYS_CS3_SIZE		0x00010000
+#define CONFIG_SYS_CS3_CFG		0x10109410
+
+#define CONFIG_SYS_CS_BURST		0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE	0x33333333
+
+#define CONFIG_SYS_RESET_ADDRESS	0xff000000
+
+/*-----------------------------------------------------------------------
+ * USB stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_USB_CLOCK	0x0001BBBB
+#define CONFIG_USB_CONFIG	0x00001000
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+
+#undef	CONFIG_IDE_8xx_PCCARD	/* Use IDE with PC Card Adapter */
+
+#undef	CONFIG_IDE_8xx_DIRECT	/* Direct IDE	 not supported	*/
+#undef	CONFIG_IDE_LED		/* LED	 for ide not supported	*/
+
+#define	CONFIG_IDE_RESET	/* reset for ide supported	*/
+#define CONFIG_IDE_PREINIT
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
+
+/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
+
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)
+
+/* Interval between registers						     */
+#define CONFIG_SYS_ATA_STRIDE		4
+
+/*-----------------------------------------------------------------------
+ * CPLD stuff
+ */
+#define CONFIG_SYS_FPGA_XC95XL		1	/* using Xilinx XC95XL CPLD	 */
+#define CONFIG_SYS_FPGA_MAX_SIZE	32*1024	/* 32kByte is enough for CPLD	 */
+
+/* CPLD program pin configuration */
+#define CONFIG_SYS_FPGA_PRG		0x20000000	/* JTAG TMS pin (ppc output)	       */
+#define CONFIG_SYS_FPGA_CLK		0x10000000	/* JTAG TCK pin (ppc output)	       */
+#define CONFIG_SYS_FPGA_DATA		0x20000000	/* JTAG TDO->TDI data pin (ppc output) */
+#define CONFIG_SYS_FPGA_DONE		0x10000000	/* JTAG TDI->TDO pin (ppc input)       */
+
+#define JTAG_GPIO_ADDR_TMS	(CONFIG_SYS_MBAR + 0xB10)	/* JTAG TMS pin (GPS data out value reg.)      */
+#define JTAG_GPIO_ADDR_TCK	(CONFIG_SYS_MBAR + 0xC0C)	/* JTAG TCK pin (GPW data out value reg.)      */
+#define JTAG_GPIO_ADDR_TDI	(CONFIG_SYS_MBAR + 0xC0C)	/* JTAG TDO->TDI pin (GPW data out value reg.) */
+#define JTAG_GPIO_ADDR_TDO	(CONFIG_SYS_MBAR + 0xB14)	/* JTAG TDI->TDO pin (GPS data in value reg.)  */
+
+#define JTAG_GPIO_ADDR_CFG	(CONFIG_SYS_MBAR + 0xB00)
+#define JTAG_GPIO_CFG_SET	0x00000000
+#define JTAG_GPIO_CFG_RESET	0x00F00000
+
+#define JTAG_GPIO_ADDR_EN_TMS	(CONFIG_SYS_MBAR + 0xB04)
+#define JTAG_GPIO_TMS_EN_SET	0x20000000	/* Enable for GPIO */
+#define JTAG_GPIO_TMS_EN_RESET	0x00000000
+#define JTAG_GPIO_ADDR_DDR_TMS	(CONFIG_SYS_MBAR + 0xB0C)
+#define JTAG_GPIO_TMS_DDR_SET	0x20000000	/* Set as output   */
+#define JTAG_GPIO_TMS_DDR_RESET 0x00000000
+
+#define JTAG_GPIO_ADDR_EN_TCK	(CONFIG_SYS_MBAR + 0xC00)
+#define JTAG_GPIO_TCK_EN_SET	0x20000000	/* Enable for GPIO */
+#define JTAG_GPIO_TCK_EN_RESET	0x00000000
+#define JTAG_GPIO_ADDR_DDR_TCK	(CONFIG_SYS_MBAR + 0xC08)
+#define JTAG_GPIO_TCK_DDR_SET	0x20000000	/* Set as output   */
+#define JTAG_GPIO_TCK_DDR_RESET 0x00000000
+
+#define JTAG_GPIO_ADDR_EN_TDI	(CONFIG_SYS_MBAR + 0xC00)
+#define JTAG_GPIO_TDI_EN_SET	0x10000000	/* Enable as GPIO  */
+#define JTAG_GPIO_TDI_EN_RESET	0x00000000
+#define JTAG_GPIO_ADDR_DDR_TDI	(CONFIG_SYS_MBAR + 0xC08)
+#define JTAG_GPIO_TDI_DDR_SET	0x10000000	/* Set as output   */
+#define JTAG_GPIO_TDI_DDR_RESET 0x00000000
+
+#define JTAG_GPIO_ADDR_EN_TDO	(CONFIG_SYS_MBAR + 0xB04)
+#define JTAG_GPIO_TDO_EN_SET	0x10000000	/* Enable as GPIO  */
+#define JTAG_GPIO_TDO_EN_RESET	0x00000000
+#define JTAG_GPIO_ADDR_DDR_TDO	(CONFIG_SYS_MBAR + 0xB0C)
+#define JTAG_GPIO_TDO_DDR_SET	0x00000000
+#define JTAG_GPIO_TDO_DDR_RESET 0x10000000	/* Set as input	   */
+
+#endif				/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/cpu9260.h b/qemu/roms/u-boot/include/configs/cpu9260.h
new file mode 100644
index 000000000..39f706238
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/cpu9260.h
@@ -0,0 +1,498 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ * Ilko Iliev <www.ronetix.at>
+ *
+ * (C) Copyright 2009
+ * Eric Benard <eric@eukrea.com>
+ *
+ * Configuration settings for the Eukrea CPU9260 board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* to be removed once maemory-map.h is fixed */
+#define AT91_BASE_SYS	0xffffe800
+#define AT91_DBGU	(0xfffff200 - AT91_BASE_SYS)
+
+#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768
+
+#if defined(CONFIG_CPU9G20)
+#define CONFIG_AT91SAM9G20
+#elif defined(CONFIG_CPU9260)
+#define CONFIG_AT91SAM9260
+#else
+#error "Unknown board"
+#endif
+
+#include <asm/arch/hardware.h>
+
+#define CONFIG_AT91FAMILY
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#if defined(CONFIG_NANDBOOT)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_TEXT_BASE           0x23f00000
+#else
+#define CONFIG_SYS_TEXT_BASE           0x00000000
+#endif
+
+/* clocks */
+#if defined(CONFIG_CPU9G20)
+#define MASTER_PLL_DIV		0x01
+#define MASTER_PLL_MUL		0x2B
+#elif defined(CONFIG_CPU9260)
+#define MASTER_PLL_DIV		0x09
+#define MASTER_PLL_MUL		0x61
+#endif
+
+/* CKGR_MOR - enable main osc. */
+#define CONFIG_SYS_MOR_VAL						\
+		(AT91_PMC_MOSCEN |					\
+		 (255 << 8))		/* Main Oscillator Start-up Time */
+#if defined(CONFIG_CPU9G20)
+#define CONFIG_SYS_PLLAR_VAL						\
+		(AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
+		 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
+#elif defined(CONFIG_CPU9260)
+#define CONFIG_SYS_PLLAR_VAL						\
+		(AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
+		 AT91_PMC_OUT |						\
+		 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
+#endif
+
+#if defined(CONFIG_CPU9G20)
+#define	CONFIG_SYS_MCKR1_VAL		\
+		(AT91_PMC_CSS_PLLA |	\
+		 AT91_PMC_PRES_1 |	\
+		 AT91SAM9_PMC_MDIV_6 |	\
+		 AT91_PMC_PDIV_2)
+#define	CONFIG_SYS_MCKR2_VAL		\
+		CONFIG_SYS_MCKR1_VAL
+#elif defined(CONFIG_CPU9260)
+#define	CONFIG_SYS_MCKR1_VAL		\
+		(AT91_PMC_CSS_SLOW |	\
+		 AT91_PMC_PRES_1 |	\
+		 AT91SAM9_PMC_MDIV_2 |	\
+		 AT91_PMC_PDIV_1)
+#define	CONFIG_SYS_MCKR2_VAL		\
+		(AT91_PMC_CSS_PLLA |	\
+		 AT91_PMC_PRES_1 |	\
+		 AT91SAM9_PMC_MDIV_2 |	\
+		 AT91_PMC_PDIV_1)
+#endif
+
+/* define PDC[31:16] as DATA[31:16] */
+#define CONFIG_SYS_PIOC_PDR_VAL1	0xFFFF0000
+/* no pull-up for D[31:16] */
+#define CONFIG_SYS_PIOC_PPUDR_VAL	0xFFFF0000
+
+/* EBI_CSA, 3.3V, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
+#define CONFIG_SYS_MATRIX_EBICSA_VAL		\
+		(AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A | \
+		AT91_MATRIX_CSA_EBI_CS3A | AT91_MATRIX_CSA_VDDIOMSEL_3_3V)
+
+/* SDRAM */
+/* SDRAMC_MR Mode register */
+#define CONFIG_SYS_SDRC_MR_VAL1		AT91_SDRAMC_MODE_NORMAL
+/* SDRAMC_TR - Refresh Timer register */
+#define CONFIG_SYS_SDRC_TR_VAL1		0x287
+/* SDRAMC_CR - Configuration register*/
+#if defined(CONFIG_CPU9G20)
+#define CONFIG_SYS_SDRC_CR_VAL_64MB					\
+		(AT91_SDRAMC_NC_9 |					\
+		 AT91_SDRAMC_NR_13 |					\
+		 AT91_SDRAMC_NB_4 |					\
+		 AT91_SDRAMC_CAS_2 |					\
+		 AT91_SDRAMC_DBW_32 |					\
+		 (2 <<  8) |	/* Write Recovery Delay */		\
+		 (9 << 12) |	/* Row Cycle Delay */			\
+		 (3 << 16) |	/* Row Precharge Delay */		\
+		 (3 << 20) |	/* Row to Column Delay */		\
+		 (6 << 24) |	/* Active to Precharge Delay */		\
+		 (10 << 28))	/* Exit Self Refresh to Active Delay */
+
+#define CONFIG_SYS_SDRC_CR_VAL_128MB					\
+		(AT91_SDRAMC_NC_10 |					\
+		 AT91_SDRAMC_NR_13 |					\
+		 AT91_SDRAMC_NB_4 |					\
+		 AT91_SDRAMC_CAS_2 |					\
+		 AT91_SDRAMC_DBW_32 |					\
+		 (2 <<  8) |	/* Write Recovery Delay */		\
+		 (9 << 12) |	/* Row Cycle Delay */			\
+		 (3 << 16) |	/* Row Precharge Delay */		\
+		 (3 << 20) |	/* Row to Column Delay */		\
+		 (6 << 24) |	/* Active to Precharge Delay */		\
+		 (10 << 28))	/* Exit Self Refresh to Active Delay */
+#elif defined(CONFIG_CPU9260)
+#define CONFIG_SYS_SDRC_CR_VAL_64MB					\
+		(AT91_SDRAMC_NC_9 |					\
+		 AT91_SDRAMC_NR_13 |					\
+		 AT91_SDRAMC_NB_4 |					\
+		 AT91_SDRAMC_CAS_2 |					\
+		 AT91_SDRAMC_DBW_32 |					\
+		 (2 <<  8) |	/* Write Recovery Delay */		\
+		 (7 << 12) |	/* Row Cycle Delay */			\
+		 (2 << 16) |	/* Row Precharge Delay */		\
+		 (2 << 20) |	/* Row to Column Delay */		\
+		 (5 << 24) |	/* Active to Precharge Delay */		\
+		 (8 << 28))	/* Exit Self Refresh to Active Delay */
+
+#define CONFIG_SYS_SDRC_CR_VAL_128MB					\
+		(AT91_SDRAMC_NC_10 |					\
+		 AT91_SDRAMC_NR_13 |					\
+		 AT91_SDRAMC_NB_4 |					\
+		 AT91_SDRAMC_CAS_2 |					\
+		 AT91_SDRAMC_DBW_32 |					\
+		 (2 <<  8) |	/* Write Recovery Delay */		\
+		 (7 << 12) |	/* Row Cycle Delay */			\
+		 (2 << 16) |	/* Row Precharge Delay */		\
+		 (2 << 20) |	/* Row to Column Delay */		\
+		 (5 << 24) |	/* Active to Precharge Delay */		\
+		 (8 << 28))	/* Exit Self Refresh to Active Delay */
+#endif
+
+/* Memory Device Register -> SDRAM */
+#define CONFIG_SYS_SDRC_MDR_VAL		AT91_SDRAMC_MD_SDRAM
+#define CONFIG_SYS_SDRC_MR_VAL2		AT91_SDRAMC_MODE_PRECHARGE
+#define CONFIG_SYS_SDRAM_VAL1		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL3		AT91_SDRAMC_MODE_REFRESH
+#define CONFIG_SYS_SDRAM_VAL2		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL3		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL4		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL5		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL6		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL7		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL8		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL9		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL4		AT91_SDRAMC_MODE_LMR
+#define CONFIG_SYS_SDRAM_VAL10		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL5		AT91_SDRAMC_MODE_NORMAL
+#define CONFIG_SYS_SDRAM_VAL11		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_TR_VAL2		1200		/* SDRAM_TR */
+#define CONFIG_SYS_SDRAM_VAL12		0		/* SDRAM_BASE */
+
+/* setup SMC0, CS0 (NOR Flash) - 16-bit */
+#if defined(CONFIG_CPU9G20)
+#define CONFIG_SYS_SMC0_SETUP0_VAL					\
+		(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |	\
+		 AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0))
+#define CONFIG_SYS_SMC0_PULSE0_VAL					\
+		(AT91_SMC_PULSE_NWE(8) | AT91_SMC_PULSE_NCS_WR(8) |	\
+		 AT91_SMC_PULSE_NRD(14) | AT91_SMC_PULSE_NCS_RD(14))
+#define CONFIG_SYS_SMC0_CYCLE0_VAL	\
+		(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(14))
+#define CONFIG_SYS_SMC0_MODE0_VAL				\
+		(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |	\
+		 AT91_SMC_MODE_DBW_16 |				\
+		 AT91_SMC_MODE_TDF |				\
+		 AT91_SMC_MODE_TDF_CYCLE(3))
+#elif defined(CONFIG_CPU9260)
+#define CONFIG_SYS_SMC0_SETUP0_VAL					\
+		(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |	\
+		 AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0))
+#define CONFIG_SYS_SMC0_PULSE0_VAL					\
+		(AT91_SMC_PULSE_NWE(6) | AT91_SMC_PULSE_NCS_WR(6) |	\
+		 AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(10))
+#define CONFIG_SYS_SMC0_CYCLE0_VAL	\
+		(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(10))
+#define CONFIG_SYS_SMC0_MODE0_VAL				\
+		(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |	\
+		 AT91_SMC_MODE_DBW_16 |				\
+		 AT91_SMC_MODE_TDF |				\
+		 AT91_SMC_MODE_TDF_CYCLE(2))
+#endif
+
+/* user reset enable */
+#define CONFIG_SYS_RSTC_RMR_VAL			\
+		(AT91_RSTC_KEY |		\
+		AT91_RSTC_CR_PROCRST |		\
+		AT91_RSTC_MR_ERSTL(1) |	\
+		AT91_RSTC_MR_ERSTL(2))
+
+/* Disable Watchdog */
+#define CONFIG_SYS_WDTC_WDMR_VAL				\
+		(AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT |	\
+		 AT91_WDT_MR_WDV(0xfff) |			\
+		 AT91_WDT_MR_WDDIS |				\
+		 AT91_WDT_MR_WDD(0xfff))
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_AT91SAM9_WATCHDOG
+#define CONFIG_AT91_GPIO
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE	ATMEL_BASE_DBGU
+#define CONFIG_USART_ID		ATMEL_ID_SYS
+
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_MII
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS	1
+#define CONFIG_SYS_SDRAM_BASE		0x20000000
+#if defined(CONFIG_CPU9260_128M) || defined(CONFIG_CPU9G20_128M)
+#define CONFIG_SYS_SDRAM_SIZE		(128 * 1024 * 1024)
+#define CONFIG_SYS_SDRC_CR_VAL	CONFIG_SYS_SDRC_CR_VAL_128MB
+#else
+#define CONFIG_SYS_SDRAM_SIZE		(64 * 1024 * 1024)
+#define CONFIG_SYS_SDRC_CR_VAL	CONFIG_SYS_SDRC_CR_VAL_64MB
+#endif
+
+/* NAND flash */
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE		1
+#define CONFIG_SYS_NAND_BASE			0x40000000
+#define CONFIG_SYS_NAND_DBW_8			1
+#define CONFIG_SYS_NAND_READY_PIN		GPIO_PIN_PC(13)
+#define CONFIG_SYS_NAND_ENABLE_PIN		GPIO_PIN_PC(14)
+#define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
+#define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
+
+/* NOR flash */
+#if defined(CONFIG_NANDBOOT)
+#define CONFIG_SYS_NO_FLASH
+#else
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define PHYS_FLASH_1				0x10000000
+#define PHYS_FLASH_2				0x12000000
+#define CONFIG_SYS_FLASH_BANKS_LIST		\
+		{ PHYS_FLASH_1, PHYS_FLASH_2 }
+#define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
+#define CONFIG_SYS_MAX_FLASH_SECT		(255+4)
+#define CONFIG_SYS_MAX_FLASH_BANKS		2
+#define CONFIG_SYS_FLASH_CFI_WIDTH		FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MONITOR_BASE			PHYS_FLASH_1
+#endif
+
+/* Ethernet */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_RETRY_COUNT			20
+#define CONFIG_MACB_SEARCH_PHY
+#define CONFIG_AT91_WANTS_COMMON_PHY
+
+/* LEDS */
+/* Status LED */
+#define CONFIG_STATUS_LED
+#define CONFIG_BOARD_SPECIFIC_LED
+#define STATUS_LED_RED				0
+#define STATUS_LED_GREEN			1
+#define STATUS_LED_YELLOW			2
+#define STATUS_LED_BLUE				3
+/* Red */
+#define STATUS_LED_BIT				STATUS_LED_RED
+#define STATUS_LED_STATE			STATUS_LED_OFF
+#define STATUS_LED_PERIOD			(CONFIG_SYS_HZ / 2)
+/* Green */
+#define STATUS_LED_BIT1				STATUS_LED_GREEN
+#define STATUS_LED_STATE1			STATUS_LED_OFF
+#define STATUS_LED_PERIOD1			(CONFIG_SYS_HZ / 2)
+/* Yellow */
+#define STATUS_LED_BIT2				STATUS_LED_YELLOW
+#define STATUS_LED_STATE2			STATUS_LED_OFF
+#define STATUS_LED_PERIOD2			(CONFIG_SYS_HZ / 2)
+/* Blue */
+#define STATUS_LED_BIT3				STATUS_LED_BLUE
+#define STATUS_LED_STATE3			STATUS_LED_ON
+#define STATUS_LED_PERIOD3			(CONFIG_SYS_HZ / 2)
+/* Optional value */
+#define STATUS_LED_BOOT				STATUS_LED_BIT
+
+#define CONFIG_RED_LED				AT91_PIO_PORTC, 11
+#define CONFIG_GREEN_LED			AT91_PIO_PORTC, 12
+#define CONFIG_YELLOW_LED			AT91_PIO_PORTC, 7
+#define CONFIG_BLUE_LED				AT91_PIO_PORTC, 9
+
+/* USB */
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00500000
+#if defined(CONFIG_CPU9G20)
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9g20"
+#elif defined(CONFIG_CPU9260)
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9260"
+#endif
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+#define CONFIG_USB_STORAGE
+
+#define CONFIG_SYS_LOAD_ADDR			0x21000000
+#define CONFIG_LOADADDR				CONFIG_SYS_LOAD_ADDR
+
+#define CONFIG_SYS_MEMTEST_START		CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END			\
+	(CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - 512 * 1024)
+
+#if defined(CONFIG_NANDBOOT)
+#define CONFIG_SYS_USE_NANDFLASH
+#undef CONFIG_SYS_USE_FLASH
+#else
+#define CONFIG_SYS_USE_FLASH
+#undef CONFIG_SYS_USE_NANDFLASH
+#endif
+
+#if defined(CONFIG_CPU9G20)
+#define CONFIG_SYS_BASEDIR	"cpu9G20"
+#elif defined(CONFIG_CPU9260)
+#define CONFIG_SYS_BASEDIR	"cpu9260"
+#endif
+
+#if defined(CONFIG_SYS_USE_FLASH)
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OFFSET		0x40000
+#define CONFIG_ENV_SECT_SIZE		0x20000
+#define	CONFIG_ENV_SIZE			0x20000
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BOOTCOMMAND		"run flashboot"
+
+#define MTDIDS_DEFAULT		"nor0=physmap-flash.0,nand0=atmel_nand"
+#define MTDPARTS_DEFAULT		\
+	"mtdparts=physmap-flash.0:"	\
+		"256k(u-boot)ro,"	\
+		"128k(u-boot-env)ro,"	\
+		"1792k(kernel),"	\
+		"-(rootfs);"		\
+	"atmel_nand:-(nand)"
+
+#define CONFIG_BOOTARGS "root=/dev/mtdblock3 rootfstype=jffs2 "
+
+#define CONFIG_EXTRA_ENV_SETTINGS				\
+	"mtdids=" MTDIDS_DEFAULT "\0"				\
+	"mtdparts=" MTDPARTS_DEFAULT "\0"			\
+	"partition=nand0,0\0"					\
+	"ramargs=setenv bootargs $(bootargs) $(mtdparts)\0"	\
+	"ramboot=tftpboot 0x22000000 $(basedir)/uImage;"	\
+		"run ramargs;bootm 22000000\0"			\
+	"flashboot=run ramargs;bootm 0x10060000\0"		\
+	"basedir=" CONFIG_SYS_BASEDIR "\0"			\
+	"updtub=tftp 0x24000000 $(basedir)/u-boot.bin;protect "	\
+		"off 0x10000000 0x1003ffff;erase 0x10000000 "	\
+		"0x1003ffff;cp.b 0x24000000 0x10000000 "	\
+		"$(filesize)\0" \
+	"updtui=tftp 0x24000000 $(basedir)/uImage;protect off"	\
+		" 0x10060000 0x1021ffff;erase 0x10060000 "	\
+		"0x1021ffff;cp.b 0x24000000 0x10060000 "	\
+		"$(filesize)\0" \
+	"updtrfs=tftp 0x24000000 $(basedir)/rootfs.jffs2; "	\
+		"protect off 0x10220000 0x13ffffff;erase "	\
+		"0x10220000 0x13ffffff;cp.b 0x24000000 "	\
+		"0x10220000 $(filesize)\0" \
+	""
+#elif defined(CONFIG_NANDBOOT)
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		0x60000
+#define CONFIG_ENV_OFFSET_REDUND	0x80000
+#define CONFIG_ENV_SECT_SIZE		0x20000
+#define	CONFIG_ENV_SIZE			0x20000
+#define CONFIG_ENV_SIZE_REDUND		(CONFIG_ENV_SIZE)
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BOOTCOMMAND		"run flashboot"
+
+#define MTDIDS_DEFAULT		"nand0=atmel_nand"
+#define MTDPARTS_DEFAULT		\
+	"mtdparts=atmel_nand:"		\
+		"128k(bootstrap)ro,"	\
+		"256k(u-boot)ro,"	\
+		"128k(u-boot-env)ro,"	\
+		"128k(u-boot-env2)ro,"	\
+		"2M(kernel),"	\
+		"-(rootfs)"
+
+#define CONFIG_BOOTARGS "root=ubi0:eukrea-cpu9260-rootfs "	\
+	"ubi.mtd=5 rootfstype=ubifs at91sam9_wdt.heartbeat=60"
+
+#define CONFIG_EXTRA_ENV_SETTINGS				\
+	"mtdids=" MTDIDS_DEFAULT "\0"				\
+	"mtdparts=" MTDPARTS_DEFAULT "\0"			\
+	"partition=nand0,5\0"					\
+	"ramargs=setenv bootargs $(bootargs) $(mtdparts)\0"	\
+	"ramboot=tftpboot 0x22000000 $(basedir)/uImage;"	\
+		"run ramargs;bootm 22000000\0"			\
+	"flashboot=run ramargs; nand read 0x22000000 0xA0000 "	\
+		"0x200000; bootm 0x22000000\0"			\
+	"basedir=" CONFIG_SYS_BASEDIR "\0"			\
+	"u-boot=u-boot-eukrea-cpu9260.bin\0"			\
+	"kernel=uImage-eukrea-cpu9260.bin\0"			\
+	"rootfs=image-eukrea-cpu9260.ubi\0"			\
+	"updtub=tftp ${loadaddr} $(basedir)/${u-boot}; "	\
+		"nand erase 20000 40000; "			\
+		"nand write ${loadaddr} 20000 40000\0"		\
+	"updtui=tftp ${loadaddr} $(basedir)/${kernel}; "	\
+		"nand erase a0000 200000; "			\
+		"nand write ${loadaddr} a0000 200000\0"		\
+	"updtrfs=tftp ${loadaddr} $(basedir)/${rootfs}; "	\
+		"nand erase  2a0000 fd60000; "			\
+		"nand write ${loadaddr} 2a0000 ${filesize}\0"
+#endif
+
+#define CONFIG_BAUDRATE			115200
+
+#if defined(CONFIG_CPU9G20)
+#define CONFIG_SYS_PROMPT		"CPU9G20=> "
+#elif defined(CONFIG_CPU9260)
+#define CONFIG_SYS_PROMPT		"CPU9260=> "
+#endif
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_PBSIZE		\
+		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SILENT_CONSOLE
+#define CONFIG_NETCONSOLE
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		\
+		ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
+
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - \
+				GENERATED_GBL_DATA_SIZE)
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/cpuat91.h b/qemu/roms/u-boot/include/configs/cpuat91.h
new file mode 100644
index 000000000..ce521012f
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/cpuat91.h
@@ -0,0 +1,236 @@
+/*
+ * CPUAT91 by (C) Copyright 2006-2010 Eric Benard
+ * eric@eukrea.com
+ *
+ * Configuration settings for the CPUAT91 board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CONFIG_CPUAT91_H
+#define _CONFIG_CPUAT91_H
+
+#include <linux/sizes.h>
+
+#ifdef CONFIG_RAMBOOT
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_TEXT_BASE		0x21F00000
+#else
+#define CONFIG_BOOTDELAY		1
+#define CONFIG_SYS_TEXT_BASE		0
+#endif
+
+#define AT91C_XTAL_CLOCK		18432000
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768
+#define AT91C_MAIN_CLOCK		((AT91C_XTAL_CLOCK / 4) * 39)
+#define AT91C_MASTER_CLOCK		(AT91C_MAIN_CLOCK / 3)
+#define CONFIG_SYS_HZ_CLOCK		(AT91C_MASTER_CLOCK / 2)
+
+#define CONFIG_ARM920T
+#define CONFIG_AT91RM9200
+#define CONFIG_CPUAT91
+#define USE_920T_MMU
+
+#include <asm/hardware.h>	/* needed for port definitions */
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_USE_MAIN_OSCILLATOR
+/* flash */
+#define CONFIG_SYS_MC_PUIA_VAL	0x00000000
+#define CONFIG_SYS_MC_PUP_VAL	0x00000000
+#define CONFIG_SYS_MC_PUER_VAL	0x00000000
+#define CONFIG_SYS_MC_ASR_VAL	0x00000000
+#define CONFIG_SYS_MC_AASR_VAL	0x00000000
+#define CONFIG_SYS_EBI_CFGR_VAL	0x00000000
+#define CONFIG_SYS_SMC_CSR0_VAL	0x00003284 /* 16bit, 2 TDF, 4 WS */
+
+/* clocks */
+#define CONFIG_SYS_PLLAR_VAL	0x20263E04 /* 179.712000 MHz for PCK */
+#define CONFIG_SYS_PLLBR_VAL	0x10483E0E /* 48.054857 MHz for USB */
+#define CONFIG_SYS_MCKR_VAL	0x00000202 /* PCK/3 = MCK Master Clock */
+
+/* sdram */
+#define CONFIG_SYS_PIOC_ASR_VAL	0xFFFF0000 /* Configure PIOC as D16/D31 */
+#define CONFIG_SYS_PIOC_BSR_VAL	0x00000000
+#define CONFIG_SYS_PIOC_PDR_VAL	0xFFFF0000
+#define CONFIG_SYS_EBI_CSA_VAL	0x00000002 /* CS1=SDRAM */
+#define CONFIG_SYS_SDRC_CR_VAL	0x2188C155 /* set up the SDRAM */
+#define CONFIG_SYS_SDRAM	0x20000000 /* address of the SDRAM */
+#define CONFIG_SYS_SDRAM1	0x20000080 /* address of the SDRAM */
+#define CONFIG_SYS_SDRAM_VAL	0x00000000 /* value written to SDRAM */
+#define CONFIG_SYS_SDRC_MR_VAL	0x00000002 /* Precharge All */
+#define CONFIG_SYS_SDRC_MR_VAL1	0x00000004 /* refresh */
+#define CONFIG_SYS_SDRC_MR_VAL2	0x00000003 /* Load Mode Register */
+#define CONFIG_SYS_SDRC_MR_VAL3	0x00000000 /* Normal Mode */
+#define CONFIG_SYS_SDRC_TR_VAL	0x000002E0 /* Write refresh rate */
+#endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
+
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE	ATMEL_BASE_DBGU
+#define CONFIG_USART_ID		0/* ignored in arm */
+
+#undef CONFIG_HARD_I2C
+#define AT91_PIN_SDA			(1<<25)
+#define AT91_PIN_SCL			(1<<26)
+
+#define CONFIG_SYS_I2C_INIT_BOARD
+#define	CONFIG_SYS_I2C_SPEED		50000
+#define CONFIG_SYS_I2C_SLAVE		0
+
+#define I2C_INIT	i2c_init_board();
+#define I2C_ACTIVE	writel(AT91_PMX_AA_TWD, &pio->pioa.mddr);
+#define I2C_TRISTATE	writel(AT91_PMX_AA_TWD, &pio->pioa.mder);
+#define I2C_READ	((readl(&pio->pioa.pdsr) & AT91_PMX_AA_TWD) != 0)
+#define I2C_SDA(bit)						\
+	if (bit)						\
+		writel(AT91_PMX_AA_TWD, &pio->pioa.sodr);	\
+	else							\
+		writel(AT91_PMX_AA_TWD, &pio->pioa.codr);
+#define I2C_SCL(bit)						\
+	if (bit)						\
+		writel(AT91_PMX_AA_TWCK, &pio->pioa.sodr);	\
+	else							\
+		writel(AT91_PMX_AA_TWCK, &pio->pioa.codr);
+
+#define I2C_DELAY	udelay(2500000/CONFIG_SYS_I2C_SPEED)
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x54
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	1
+#define	CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
+
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_CACHE
+#undef CONFIG_CMD_USB
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_DHCP
+
+#ifdef CONFIG_SYS_I2C_SOFT
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#endif
+
+#define CONFIG_NR_DRAM_BANKS			1
+#define CONFIG_SYS_SDRAM_BASE			0x20000000
+#define CONFIG_SYS_SDRAM_SIZE			(32 * 1024 * 1024)
+
+#define CONFIG_SYS_MEMTEST_START		CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END			\
+	(CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - 512 * 1024)
+
+#define CONFIG_DRIVER_AT91EMAC
+#define CONFIG_SYS_RX_ETH_BUFFER	16
+#define CONFIG_RMII
+#define CONFIG_MII
+#define CONFIG_DRIVER_AT91EMAC_PHYADDR	1
+#define CONFIG_NET_RETRY_COUNT			20
+#define CONFIG_KS8721_PHY
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_MAX_FLASH_BANKS		1
+#define CONFIG_SYS_FLASH_PROTECTION
+#define PHYS_FLASH_1				0x10000000
+#define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
+#define CONFIG_SYS_MAX_FLASH_SECT		128
+#define CONFIG_SYS_FLASH_CFI_WIDTH		FLASH_CFI_16BIT
+#define CONFIG_SYS_MONITOR_BASE			PHYS_FLASH_1
+#define PHYS_FLASH_SIZE				(16 * 1024 * 1024)
+#define CONFIG_SYS_FLASH_BANKS_LIST		\
+		{ PHYS_FLASH_1 }
+
+#if defined(CONFIG_CMD_USB)
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_USB_STORAGE
+#define CONFIG_DOS_PARTITION
+#define CONFIG_AT91C_PQFP_UHPBU
+#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		AT91_USB_HOST_BASE
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91rm9200"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
+#endif
+
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR				(PHYS_FLASH_1 + 128 * 1024)
+#define CONFIG_ENV_SIZE				(128 * 1024)
+#define CONFIG_ENV_SECT_SIZE		(128 * 1024)
+
+#define CONFIG_SYS_LOAD_ADDR		0x21000000
+
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_SYS_PROMPT		"CPUAT91=> "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_MAXARGS		32
+#define CONFIG_SYS_PBSIZE		\
+	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_CMDLINE_EDITING
+
+#define CONFIG_SYS_MALLOC_LEN		\
+			ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 4 * 1024)
+
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - \
+				GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_DEVICE_NULLDEV
+#define CONFIG_SILENT_CONSOLE
+
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT		\
+	"Press SPACE to abort autoboot\n"
+#define CONFIG_AUTOBOOT_STOP_STR	" "
+#define CONFIG_AUTOBOOT_DELAY_STR	"d"
+
+#define CONFIG_VERSION_VARIABLE
+
+#define MTDIDS_DEFAULT			"nor0=physmap-flash.0"
+#define MTDPARTS_DEFAULT		\
+	"mtdparts=physmap-flash.0:"	\
+		"128k(u-boot)ro,"	\
+		"128k(u-boot-env),"	\
+		"1792k(kernel),"	\
+		"-(rootfs)"
+
+#define CONFIG_BOOTARGS 		\
+	"root=/dev/mtdblock3 rootfstype=jffs2 console=ttyS0,115200"
+
+#define CONFIG_BOOTCOMMAND		"run flashboot"
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"mtdid=" MTDIDS_DEFAULT "\0"					\
+	"mtdparts=" MTDPARTS_DEFAULT "\0"				\
+	"flub=tftp 21000000 cpuat91/u-boot.bin; protect off 10000000 "	\
+		"1001FFFF; erase 10000000 1001FFFF; cp.b 21000000 "	\
+		"10000000 ${filesize}\0"				\
+	"flui=tftp 21000000 cpuat91/uImage; protect off 10040000 "	\
+		"1019ffff; erase 10040000 101fffff; cp.b 21000000 "	\
+		"10040000 ${filesize}\0"				\
+	"flrfs=tftp 21000000 cpuat91/rootfs.jffs2; protect off "	\
+		"10200000 10ffffff; erase 10200000 10ffffff; cp.b "	\
+		"21000000 10200000 ${filesize}\0"			\
+	"ramargs=setenv bootargs $(bootargs) $(mtdparts)\0"		\
+	"flashboot=run ramargs;bootm 10040000\0"			\
+	"netboot=run ramargs;tftpboot 21000000 cpuat91/uImage;"		\
+		"bootm 21000000\0"
+#endif	/* _CONFIG_CPUAT91_H */
diff --git a/qemu/roms/u-boot/include/configs/csb272.h b/qemu/roms/u-boot/include/configs/csb272.h
new file mode 100644
index 000000000..a5c6f8474
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/csb272.h
@@ -0,0 +1,284 @@
+/*
+ * (C) Copyright 2004
+ * Tolunay Orkun, Nextio Inc., torkun@nextio.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405GP		1	/* This is a PPC405GP CPU	*/
+#define CONFIG_CSB272		1	/* on a Cogent CSB272 board     */
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f()    */
+#define CONFIG_LAST_STAGE_INIT	1	/* Call last_stage_init()	*/
+#define CONFIG_SYS_CLK_FREQ     33000000 /* external frequency to pll   */
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
+
+/*
+ * OS Bootstrap configuration
+ *
+ */
+
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY	3	/* autoboot after X seconds	*/
+#endif
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check keypress when bootdelay = 0 */
+
+#if 1
+#undef  CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND \
+	"setenv bootargs console=ttyS0,38400 debug " \
+	"root=/dev/ram rw ramdisk_size=4096 " \
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
+	"bootm fe000000 fe100000"
+#endif
+
+#if 0
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND \
+	"bootp; " \
+	"setenv bootargs console=ttyS0,38400 debug " \
+	"root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
+	"bootm"
+#endif
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_DNS2
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+
+
+/*
+ * Serial download configuration
+ *
+ */
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+/*
+ * KGDB Configuration
+ *
+ */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ *
+ */
+#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser */
+
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
+#else
+#define	CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM */
+#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_info (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR		0x100000 /* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+
+/*
+ * watchdog configuration
+ *
+ */
+#undef  CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * UART configuration
+ *
+ */
+#define CONFIG_CONS_INDEX		1	/* Use UART0		*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+
+#define CONFIG_SYS_EXT_SERIAL_CLOCK	3868400	/* use external serial clock */
+#undef  CONFIG_SYS_BASE_BAUD
+#define CONFIG_BAUDRATE		38400	/* Default baud rate */
+#define CONFIG_SYS_BAUDRATE_TABLE      \
+    { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*
+ * I2C configuration
+ *
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		100000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F	/* I2C slave address */
+
+/*
+ * MII PHY configuration
+ *
+ */
+#define CONFIG_PPC4xx_EMAC
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_PHY_CMD_DELAY	40	/* PHY COMMAND delay		*/
+					/* 32usec min. for LXT971A	*/
+#define CONFIG_PHY_RESET_DELAY	300	/* PHY RESET recovery delay	*/
+
+/*
+ * RTC configuration
+ *
+ * Note that DS1307 RTC is limited to 100Khz I2C bus.
+ *
+ */
+#define CONFIG_RTC_DS1307		/* Use Dallas 1307 RTC		*/
+
+/*
+ * PCI stuff
+ *
+ */
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define PCI_HOST_ADAPTER	0	/* configure ar pci adapter     */
+#define PCI_HOST_FORCE		1	/* configure as pci host        */
+#define PCI_HOST_AUTO		2	/* detected via arbiter enable  */
+
+#define CONFIG_PCI_HOST	PCI_HOST_FORCE  /* select pci host function     */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
+					/* resource configuration       */
+#undef  CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
+#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000  /* PCI Vendor ID: to-do!!!      */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000  /* PCI Device ID: to-do!!!      */
+#define CONFIG_SYS_PCI_PTM1LA  0x00000000      /* point to sdram               */
+#define CONFIG_SYS_PCI_PTM1MS  0x80000001      /* 2GB, enable hard-wired to 1  */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CONFIG_SYS_PCI_PTM2LA  0x00000000      /* disabled                     */
+#define CONFIG_SYS_PCI_PTM2MS  0x00000000      /* disabled                     */
+#define CONFIG_SYS_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+
+/*
+ * IDE stuff
+ *
+ */
+#undef  CONFIG_IDE_PCMCIA               /* no pcmcia interface required */
+#undef  CONFIG_IDE_LED                  /* no led for ide supported     */
+#undef  CONFIG_IDE_RESET                /* no reset for ide supported   */
+
+/*
+ * Environment configuration
+ *
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1	/* environment is in FLASH	*/
+#undef CONFIG_ENV_IS_IN_NVRAM
+#undef CONFIG_ENV_IS_IN_EEPROM
+
+/*
+ * General Memory organization
+ *
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFE000000
+#define CONFIG_SYS_FLASH_SIZE		0x02000000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 KB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024) /* Reserve 128 KB for malloc() */
+
+#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_RAMSTART
+#endif
+
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+#define CONFIG_ENV_IN_OWN_SECTOR	1	   /* Give Environment own sector */
+#define CONFIG_ENV_ADDR		0xFFF00000 /* Address of Environment Sector */
+#define	CONFIG_ENV_SIZE		0x00001000 /* Size of Environment */
+#define CONFIG_ENV_SECT_SIZE	0x00040000 /* Size of Environment Sector */
+#endif
+
+/*
+ * FLASH Device configuration
+ *
+ */
+#define CONFIG_SYS_FLASH_CFI		1	/* flash is CFI conformant	*/
+#define CONFIG_FLASH_CFI_DRIVER	1	/* use common cfi driver	*/
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster) */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max # of memory banks	*/
+#define CONFIG_SYS_FLASH_INCREMENT	0	/* there is only one bank	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max # of sectors on one chip	*/
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* hardware flash protection	*/
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+
+/*
+ * On Chip Memory location/size
+ *
+ */
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+
+/*
+ * Global info and initial stack
+ *
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of on-chip SRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * Miscellaneous board specific definitions
+ *
+ */
+#define CONFIG_SYS_I2C_PLL_ADDR	0x58	/* I2C address of AMIS FS6377-01 PLL */
+#define CONFIG_I2CFAST		1	/* enable "i2cfast" env. setting     */
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/csb472.h b/qemu/roms/u-boot/include/configs/csb472.h
new file mode 100644
index 000000000..6aa98efd4
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/csb472.h
@@ -0,0 +1,283 @@
+/*
+ * (C) Copyright 2004
+ * Tolunay Orkun, Nextio Inc., torkun@nextio.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405GP		1	/* This is a PPC405GP CPU	*/
+#define CONFIG_CSB472		1	/* on a Cogent CSB472 board     */
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f()    */
+#define CONFIG_LAST_STAGE_INIT	1	/* Call last_stage_init()	*/
+#define CONFIG_SYS_CLK_FREQ     25000000 /* external frequency to pll   */
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
+
+/*
+ * OS Bootstrap configuration
+ *
+ */
+
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY	3	/* autoboot after X seconds	*/
+#endif
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check keypress when bootdelay = 0 */
+
+#if 1
+#undef  CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND \
+	"setenv bootargs console=ttyS0,38400 debug " \
+	"root=/dev/ram rw ramdisk_size=4096 " \
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
+	"bootm ff800000 ff900000"
+#endif
+
+#if 0
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND \
+	"bootp; " \
+	"setenv bootargs console=ttyS0,38400 debug " \
+	"root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
+	"bootm"
+#endif
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_DNS2
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+
+/*
+ * Serial download configuration
+ *
+ */
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+/*
+ * KGDB Configuration
+ *
+ */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ *
+ */
+#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser */
+
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
+#else
+#define	CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM */
+
+#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_info (bd_t) */
+#define CONFIG_SYS_LOAD_ADDR		0x100000 /* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+
+/*
+ * watchdog configuration
+ *
+ */
+#undef  CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * UART configuration
+ *
+ */
+#define CONFIG_CONS_INDEX		1	/* Use UART0		*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+
+#undef CONFIG_SYS_EXT_SERIAL_CLOCK		/* use internal serial clock */
+#define CONFIG_SYS_BASE_BAUD		691200
+#define CONFIG_BAUDRATE		38400	/* Default baud rate */
+#define CONFIG_SYS_BAUDRATE_TABLE      \
+    { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*
+ * I2C configuration
+ *
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		100000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F	/* I2C slave address */
+
+/*
+ * MII PHY configuration
+ *
+ */
+#define CONFIG_PPC4xx_EMAC
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_PHY_CMD_DELAY	40	/* PHY COMMAND delay		*/
+					/* 32usec min. for LXT971A	*/
+#define CONFIG_PHY_RESET_DELAY	300	/* PHY RESET recovery delay	*/
+
+/*
+ * RTC configuration
+ *
+ * Note that DS1307 RTC is limited to 100Khz I2C bus.
+ *
+ */
+#define CONFIG_RTC_DS1307		/* Use Dallas 1307 RTC		*/
+
+/*
+ * PCI stuff
+ *
+ */
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define PCI_HOST_ADAPTER	0	/* configure ar pci adapter     */
+#define PCI_HOST_FORCE		1	/* configure as pci host        */
+#define PCI_HOST_AUTO		2	/* detected via arbiter enable  */
+
+#define CONFIG_PCI_HOST	PCI_HOST_FORCE  /* select pci host function     */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play         */
+					/* resource configuration       */
+#undef  CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
+#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000  /* PCI Vendor ID: to-do!!!      */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000  /* PCI Device ID: to-do!!!      */
+#define CONFIG_SYS_PCI_PTM1LA  0x00000000      /* point to sdram               */
+#define CONFIG_SYS_PCI_PTM1MS  0x80000001      /* 2GB, enable hard-wired to 1  */
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CONFIG_SYS_PCI_PTM2LA  0x00000000      /* disabled                     */
+#define CONFIG_SYS_PCI_PTM2MS  0x00000000      /* disabled                     */
+#define CONFIG_SYS_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+
+/*
+ * IDE stuff
+ *
+ */
+#undef  CONFIG_IDE_PCMCIA               /* no pcmcia interface required */
+#undef  CONFIG_IDE_LED                  /* no led for ide supported     */
+#undef  CONFIG_IDE_RESET                /* no reset for ide supported   */
+
+/*
+ * Environment configuration
+ *
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1	/* environment is in FLASH	*/
+#undef CONFIG_ENV_IS_IN_NVRAM
+#undef CONFIG_ENV_IS_IN_EEPROM
+
+/*
+ * General Memory organization
+ *
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFF800000
+#define CONFIG_SYS_FLASH_SIZE		0x00800000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 KB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024) /* Reserve 128 KB for malloc() */
+
+#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_RAMSTART
+#endif
+
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+#define CONFIG_ENV_IN_OWN_SECTOR	1	   /* Give Environment own sector */
+#define CONFIG_ENV_ADDR		0xFFF00000 /* Address of Environment Sector */
+#define	CONFIG_ENV_SIZE		0x00001000 /* Size of Environment */
+#define CONFIG_ENV_SECT_SIZE	0x00040000 /* Size of Environment Sector */
+#endif
+
+/*
+ * FLASH Device configuration
+ *
+ */
+#define CONFIG_SYS_FLASH_CFI		1	/* flash is CFI conformant	*/
+#define CONFIG_FLASH_CFI_DRIVER	1	/* use common cfi driver	*/
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster) */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max # of memory banks	*/
+#define CONFIG_SYS_FLASH_INCREMENT	0	/* there is only one bank	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	64	/* max # of sectors on one chip	*/
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* hardware flash protection	*/
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+
+/*
+ * On Chip Memory location/size
+ *
+ */
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+
+/*
+ * Global info and initial stack
+ *
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of on-chip SRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * Miscellaneous board specific definitions
+ *
+ */
+#define CONFIG_I2CFAST		1	/* enable "i2cfast" env. setting     */
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/da830evm.h b/qemu/roms/u-boot/include/configs/da830evm.h
new file mode 100644
index 000000000..27171950a
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/da830evm.h
@@ -0,0 +1,294 @@
+/*
+ * Copyright (C) 2008 Texas Instruments, Inc <www.ti.com>
+ *
+ * Based on davinci_dvevm.h. Original Copyrights follow:
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Board
+ */
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_USE_SPIFLASH
+
+/*
+ * SoC Configuration
+ */
+#define CONFIG_MACH_DAVINCI_DA830_EVM
+#define CONFIG_ARM926EJS		/* arm926ejs CPU core */
+#define CONFIG_SOC_DA8XX		/* TI DA8xx SoC */
+#define CONFIG_SOC_DA830		/* TI DA830 SoC */
+#define CONFIG_SYS_CLK_FREQ		clk_get(DAVINCI_ARM_CLKID)
+#define CONFIG_SYS_OSCIN_FREQ		24000000
+#define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
+#define CONFIG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_TEXT_BASE		0xc1080000
+
+/*
+ * Memory Info
+ */
+#define CONFIG_SYS_MALLOC_LEN	(0x10000 + 1*1024*1024) /* malloc() len */
+#define PHYS_SDRAM_1			0xc0000000 /* SDRAM Start */
+#define CONFIG_SYS_MEMTEST_START	(PHYS_SDRAM_1 + 0x2000000)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
+						(32 << 20))
+#define CONFIG_NR_DRAM_BANKS	1 /* we have 1 bank of DRAM */
+
+/*
+ * Serial Driver info
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	-4	/* NS16550 register size */
+#define CONFIG_SYS_NS16550_COM1	DAVINCI_UART2_BASE /* Base address of UART2 */
+#define CONFIG_SYS_NS16550_CLK	clk_get(DAVINCI_UART2_CLKID)
+#define CONFIG_CONS_INDEX	1		/* use UART0 for console */
+#define CONFIG_BAUDRATE		115200		/* Default baud rate */
+
+/*
+ * I2C Configuration
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DAVINCI
+#define CONFIG_SYS_DAVINCI_I2C_SPEED     25000 /* 100Kbps won't work, H/W bug */
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE     10 /* Bogus, master-only in U-Boot */
+
+/*
+ * I2C EEPROM definitions for catalyst 24W256 EEPROM chip
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	20
+
+/*
+ * Network & Ethernet Configuration
+ */
+#ifdef CONFIG_DRIVER_TI_EMAC
+#define CONFIG_MII
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT	10
+#endif
+
+/*
+ * Flash & Environment
+ */
+#ifdef CONFIG_USE_NAND
+#undef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_IS_IN_NAND		/* U-Boot env in NAND Flash  */
+#define CONFIG_ENV_OFFSET		(512 << 10)
+#define CONFIG_ENV_SIZE			(10 << 10) /* 10KB */
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
+#define CONFIG_SYS_NAND_PAGE_2K
+#define CONFIG_SYS_NAND_CS		3
+#define CONFIG_SYS_NAND_BASE		DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
+#define CONFIG_SYS_NAND_PAGE_2K
+#define CONFIG_SYS_NAND_MASK_CLE		0x10
+#define CONFIG_SYS_NAND_MASK_ALE		0x8
+#define CONFIG_SYS_MAX_NAND_DEVICE	1 /* Max number of NAND devices */
+#endif
+
+#ifdef CONFIG_USE_NOR
+#define CONFIG_ENV_IS_IN_FLASH
+#undef CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_MAX_FLASH_BANKS	1 /* max number of flash banks */
+#define CONFIG_SYS_FLASH_SECT_SZ	(64 << 10) /* 64KB */
+#define CONFIG_ENV_OFFSET		(CONFIG_SYS_FLASH_SECT_SZ*3)
+#define CONFIG_SYS_FLASH_BASE		DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
+#define PHYS_FLASH_SIZE			(32 << 20) /* Flash size 32MB */
+#define CONFIG_SYS_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)
+#define CONFIG_ENV_SECT_SIZE		CONFIG_SYS_FLASH_SECT_SZ
+#define CONFIG_SYS_FLASH_SPL_ACCESS
+#endif
+
+#ifdef CONFIG_USE_SPIFLASH
+#undef CONFIG_ENV_IS_IN_FLASH
+#undef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE			(16 << 10)
+#define CONFIG_ENV_OFFSET		(256 << 10)
+#define CONFIG_ENV_SECT_SIZE		4096
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_DAVINCI_SPI
+#define CONFIG_SYS_SPI_BASE		DAVINCI_SPI0_BASE
+#define CONFIG_SYS_SPI_CLK		clk_get(DAVINCI_SPI0_CLKID)
+#define CONFIG_SF_DEFAULT_SPEED		30000000
+#define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
+#endif
+
+/*
+ * USB configuration
+ */
+#define CONFIG_USB_DA8XX	/* Platform hookup to MUSB controller */
+#define CONFIG_MUSB_HCD
+
+/*
+ * U-Boot general configuration
+ */
+#undef CONFIG_MISC_INIT_R
+#undef CONFIG_BOOTDELAY
+#define CONFIG_BOOTFILE		"uImage" /* Boot file name */
+#define CONFIG_SYS_PROMPT	"U-Boot > " /* Command Prompt */
+#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
+#define CONFIG_SYS_LOAD_ADDR	(PHYS_SDRAM_1 + 0x700000)
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE	/* Won't work with hush so far, may be later */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+
+/*
+ * Linux Information
+ */
+#define LINUX_BOOT_PARAM_ADDR	(PHYS_SDRAM_1 + 0x100)
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTARGS		"mem=32M console=ttyS2,115200n8 root=/dev/mtdblock/2 rw noinitrd ip=dhcp"
+#define CONFIG_BOOTCOMMAND	""
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * U-Boot commands
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_MEMORY
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+
+#ifdef CONFIG_CMD_BDI
+#define CONFIG_CLOCKS
+#endif
+
+#ifndef CONFIG_DRIVER_TI_EMAC
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_MII
+#undef CONFIG_CMD_PING
+#endif
+
+#ifdef CONFIG_USE_NAND
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE
+#endif
+
+#ifdef CONFIG_USE_SPIFLASH
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_FLASH
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SAVEENV
+#endif
+
+/* SD/MMC configuration */
+#ifndef CONFIG_USE_NAND
+#define CONFIG_MMC
+#define CONFIG_DAVINCI_MMC_SD1
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DAVINCI_MMC
+#endif
+
+/*
+ * Enable MMC commands only when
+ * MMC support is present
+ */
+#if defined(CONFIG_MMC) || defined(CONFIG_USB_DA8XX)
+#define CONFIG_DOS_PARTITION	/* include support for FAT/storage */
+#define CONFIG_CMD_FAT		/* include support for FAT cmd */
+#endif
+
+#ifdef CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_EXT2
+#endif
+
+#if !defined(CONFIG_USE_NAND) && \
+	!defined(CONFIG_USE_NOR) && \
+	!defined(CONFIG_USE_SPIFLASH)
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_SIZE		(16 << 10)
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_ENV
+#endif
+
+#ifdef CONFIG_USB_DA8XX
+
+#ifdef CONFIG_MUSB_HCD		/* include support for usb host */
+#define CONFIG_CMD_USB		/* include support for usb cmd */
+
+#define CONFIG_USB_STORAGE	/* MSC class support */
+#define CONFIG_CMD_STORAGE	/* inclue support for usb-storage cmd */
+
+#ifdef CONFIG_USB_KEYBOARD	/* HID class support */
+#define CONFIG_SYS_USB_EVENT_POLL
+#define CONFIG_PREBOOT "usb start"
+#endif /* CONFIG_USB_KEYBOARD */
+
+#endif /* CONFIG_MUSB_HCD */
+
+#ifdef CONFIG_MUSB_UDC
+/* USB device configuration */
+#define CONFIG_USB_DEVICE		1
+#define CONFIG_USB_TTY			1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
+/* Change these to suit your needs */
+#define CONFIG_USBD_VENDORID		0x0451
+#define CONFIG_USBD_PRODUCTID		0x5678
+#define CONFIG_USBD_MANUFACTURER	"Texas Instruments"
+#define CONFIG_USBD_PRODUCT_NAME	"DA830EVM"
+#endif /* CONFIG_MUSB_UDC */
+
+#endif /* CONFIG_USB_DA8XX */
+
+#ifdef CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT		"nand0=davinci_nand.1"
+#define PART_BOOT		"512k(bootloader)ro,"
+#define PART_PARAMS		"512k(params)ro,"
+#define PART_KERNEL		"4m(kernel),"
+#define PART_REST		"-(filesystem)"
+#define MTDPARTS_DEFAULT        \
+	"mtdparts=davinci_nand.1:" PART_BOOT PART_PARAMS PART_KERNEL PART_REST
+#endif
+
+#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
+
+/* additions for new relocation code, must be added to all boards */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR		\
+	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/da850evm.h b/qemu/roms/u-boot/include/configs/da850evm.h
new file mode 100644
index 000000000..860a11dd2
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/da850evm.h
@@ -0,0 +1,409 @@
+/*
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Based on davinci_dvevm.h. Original Copyrights follow:
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Board
+ */
+#define CONFIG_DRIVER_TI_EMAC
+/* check if direct NOR boot config is used */
+#ifndef CONFIG_DIRECT_NOR_BOOT
+#define CONFIG_USE_SPIFLASH
+#endif
+
+
+/*
+ * SoC Configuration
+ */
+#define CONFIG_MACH_DAVINCI_DA850_EVM
+#define CONFIG_ARM926EJS		/* arm926ejs CPU core */
+#define CONFIG_SOC_DA8XX		/* TI DA8xx SoC */
+#define CONFIG_SOC_DA850		/* TI DA850 SoC */
+#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
+#define CONFIG_SYS_CLK_FREQ		clk_get(DAVINCI_ARM_CLKID)
+#define CONFIG_SYS_OSCIN_FREQ		24000000
+#define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
+#define CONFIG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
+#define CONFIG_SYS_DA850_PLL_INIT
+#define CONFIG_SYS_DA850_DDR_INIT
+
+#ifdef CONFIG_DIRECT_NOR_BOOT
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DA8XX_GPIO
+#define CONFIG_SYS_TEXT_BASE		0x60000000
+#define CONFIG_SYS_DV_NOR_BOOT_CFG	(0x11)
+#define CONFIG_DA850_LOWLEVEL
+#else
+#define CONFIG_SYS_TEXT_BASE		0xc1080000
+#endif
+
+/*
+ * Memory Info
+ */
+#define CONFIG_SYS_MALLOC_LEN	(0x10000 + 1*1024*1024) /* malloc() len */
+#define PHYS_SDRAM_1		DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
+#define PHYS_SDRAM_1_SIZE	(64 << 20) /* SDRAM size 64MB */
+#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
+
+/* memtest start addr */
+#define CONFIG_SYS_MEMTEST_START	(PHYS_SDRAM_1 + 0x2000000)
+
+/* memtest will be run on 16MB */
+#define CONFIG_SYS_MEMTEST_END 	(PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
+
+#define CONFIG_NR_DRAM_BANKS	1 /* we have 1 bank of DRAM */
+
+#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (	\
+	DAVINCI_SYSCFG_SUSPSRC_TIMER0 |		\
+	DAVINCI_SYSCFG_SUSPSRC_SPI1 |		\
+	DAVINCI_SYSCFG_SUSPSRC_UART2 |		\
+	DAVINCI_SYSCFG_SUSPSRC_EMAC |		\
+	DAVINCI_SYSCFG_SUSPSRC_I2C)
+
+/*
+ * PLL configuration
+ */
+#define CONFIG_SYS_DV_CLKMODE          0
+#define CONFIG_SYS_DA850_PLL0_POSTDIV  1
+#define CONFIG_SYS_DA850_PLL0_PLLDIV1  0x8000
+#define CONFIG_SYS_DA850_PLL0_PLLDIV2  0x8001
+#define CONFIG_SYS_DA850_PLL0_PLLDIV3  0x8002
+#define CONFIG_SYS_DA850_PLL0_PLLDIV4  0x8003
+#define CONFIG_SYS_DA850_PLL0_PLLDIV5  0x8002
+#define CONFIG_SYS_DA850_PLL0_PLLDIV6  CONFIG_SYS_DA850_PLL0_PLLDIV1
+#define CONFIG_SYS_DA850_PLL0_PLLDIV7  0x8005
+
+#define CONFIG_SYS_DA850_PLL1_POSTDIV  1
+#define CONFIG_SYS_DA850_PLL1_PLLDIV1  0x8000
+#define CONFIG_SYS_DA850_PLL1_PLLDIV2  0x8001
+#define CONFIG_SYS_DA850_PLL1_PLLDIV3  0x8002
+
+#define CONFIG_SYS_DA850_PLL0_PLLM     24
+#define CONFIG_SYS_DA850_PLL1_PLLM     21
+
+/*
+ * DDR2 memory configuration
+ */
+#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
+					DV_DDR_PHY_EXT_STRBEN | \
+					(0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
+
+#define CONFIG_SYS_DA850_DDR2_SDBCR (		\
+	(1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) |	\
+	(1 << DV_DDR_SDCR_DDREN_SHIFT) |	\
+	(1 << DV_DDR_SDCR_SDRAMEN_SHIFT) |	\
+	(1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) |	\
+	(0x3 << DV_DDR_SDCR_CL_SHIFT) |		\
+	(0x2 << DV_DDR_SDCR_IBANK_SHIFT) |	\
+	(0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
+
+/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
+#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
+
+#define CONFIG_SYS_DA850_DDR2_SDTIMR (		\
+	(14 << DV_DDR_SDTMR1_RFC_SHIFT) |	\
+	(2 << DV_DDR_SDTMR1_RP_SHIFT) |		\
+	(2 << DV_DDR_SDTMR1_RCD_SHIFT) |	\
+	(1 << DV_DDR_SDTMR1_WR_SHIFT) |		\
+	(5 << DV_DDR_SDTMR1_RAS_SHIFT) |	\
+	(8 << DV_DDR_SDTMR1_RC_SHIFT) |		\
+	(1 << DV_DDR_SDTMR1_RRD_SHIFT) |	\
+	(0 << DV_DDR_SDTMR1_WTR_SHIFT))
+
+#define CONFIG_SYS_DA850_DDR2_SDTIMR2 (		\
+	(7 << DV_DDR_SDTMR2_RASMAX_SHIFT) |	\
+	(0 << DV_DDR_SDTMR2_XP_SHIFT) |		\
+	(0 << DV_DDR_SDTMR2_ODT_SHIFT) |	\
+	(17 << DV_DDR_SDTMR2_XSNR_SHIFT) |	\
+	(199 << DV_DDR_SDTMR2_XSRD_SHIFT) |	\
+	(0 << DV_DDR_SDTMR2_RTP_SHIFT) |	\
+	(0 << DV_DDR_SDTMR2_CKE_SHIFT))
+
+#define CONFIG_SYS_DA850_DDR2_SDRCR    0x00000494
+#define CONFIG_SYS_DA850_DDR2_PBBPR    0x30
+
+/*
+ * Serial Driver info
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	-4	/* NS16550 register size */
+#define CONFIG_SYS_NS16550_COM1	DAVINCI_UART2_BASE /* Base address of UART2 */
+#define CONFIG_SYS_NS16550_CLK	clk_get(DAVINCI_UART2_CLKID)
+#define CONFIG_CONS_INDEX	1		/* use UART0 for console */
+#define CONFIG_BAUDRATE		115200		/* Default baud rate */
+
+#define CONFIG_SPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_CMD_SF
+#define CONFIG_DAVINCI_SPI
+#define CONFIG_SYS_SPI_BASE		DAVINCI_SPI1_BASE
+#define CONFIG_SYS_SPI_CLK		clk_get(DAVINCI_SPI1_CLKID)
+#define CONFIG_SF_DEFAULT_SPEED		30000000
+#define CONFIG_ENV_SPI_MAX_HZ	CONFIG_SF_DEFAULT_SPEED
+
+#ifdef CONFIG_USE_SPIFLASH
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_BUS 0
+#define CONFIG_SPL_SPI_CS 0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x8000
+#define CONFIG_SYS_SPI_U_BOOT_SIZE	0x30000
+#endif
+
+/*
+ * I2C Configuration
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DAVINCI
+#define CONFIG_SYS_DAVINCI_I2C_SPEED		25000
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE   10 /* Bogus, master-only in U-Boot */
+#define CONFIG_SYS_I2C_EXPANDER_ADDR   0x20
+
+/*
+ * Flash & Environment
+ */
+#ifdef CONFIG_USE_NAND
+#undef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_IS_IN_NAND		/* U-Boot env in NAND Flash  */
+#define CONFIG_ENV_OFFSET		0x0 /* Block 0--not used by bootcode */
+#define CONFIG_ENV_SIZE			(128 << 10)
+#define	CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
+#define	CONFIG_SYS_NAND_PAGE_2K
+#define CONFIG_SYS_NAND_CS		3
+#define CONFIG_SYS_NAND_BASE		DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
+#define CONFIG_SYS_NAND_MASK_CLE		0x10
+#define CONFIG_SYS_NAND_MASK_ALE		0x8
+#undef CONFIG_SYS_NAND_HW_ECC
+#define CONFIG_SYS_MAX_NAND_DEVICE	1 /* Max number of NAND devices */
+#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_SIZE	(2 << 10)
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x28000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x60000
+#define CONFIG_SYS_NAND_U_BOOT_DST	0xc1080000
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
+#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP	(CONFIG_SYS_NAND_U_BOOT_DST - \
+					CONFIG_SYS_NAND_U_BOOT_SIZE - \
+					CONFIG_SYS_MALLOC_LEN -       \
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_NAND_ECCPOS		{				\
+				24, 25, 26, 27, 28, \
+				29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
+				39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
+				49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
+				59, 60, 61, 62, 63 }
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	10
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SPL_NAND_LOAD
+#endif
+
+/*
+ * Network & Ethernet Configuration
+ */
+#ifdef CONFIG_DRIVER_TI_EMAC
+#define CONFIG_MII
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT	10
+#endif
+
+#ifdef CONFIG_USE_NOR
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS	1 /* max number of flash banks */
+#define CONFIG_SYS_FLASH_SECT_SZ	(128 << 10) /* 128KB */
+#define CONFIG_ENV_OFFSET		(CONFIG_SYS_FLASH_SECT_SZ * 3)
+#define CONFIG_ENV_SIZE			(10 << 10) /* 10KB */
+#define CONFIG_SYS_FLASH_BASE		DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
+#define PHYS_FLASH_SIZE			(8 << 20) /* Flash size 8MB */
+#define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
+	       + 3)
+#define CONFIG_ENV_SECT_SIZE		CONFIG_SYS_FLASH_SECT_SZ
+#endif
+
+#ifdef CONFIG_USE_SPIFLASH
+#undef CONFIG_ENV_IS_IN_FLASH
+#undef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE			(64 << 10)
+#define CONFIG_ENV_OFFSET		(256 << 10)
+#define CONFIG_ENV_SECT_SIZE		(64 << 10)
+#define CONFIG_SYS_NO_FLASH
+#endif
+
+/*
+ * U-Boot general configuration
+ */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOOTFILE		"uImage" /* Boot file name */
+#define CONFIG_SYS_PROMPT	"U-Boot > " /* Command Prompt */
+#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
+#define CONFIG_SYS_LOAD_ADDR	(PHYS_SDRAM_1 + 0x700000)
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+
+/*
+ * Linux Information
+ */
+#define LINUX_BOOT_PARAM_ADDR	(PHYS_SDRAM_1 + 0x100)
+#define CONFIG_HWCONFIG		/* enable hwconfig */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTARGS		\
+	"mem=32M console=ttyS2,115200n8 root=/dev/mtdblock2 rw noinitrd ip=dhcp"
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_EXTRA_ENV_SETTINGS	"hwconfig=dsp:wake=yes"
+
+/*
+ * U-Boot commands
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_MEMORY
+
+#ifdef CONFIG_CMD_BDI
+#define CONFIG_CLOCKS
+#endif
+
+#ifndef CONFIG_DRIVER_TI_EMAC
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_MII
+#undef CONFIG_CMD_PING
+#endif
+
+#ifdef CONFIG_USE_NAND
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_NAND
+
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_LZO
+#define CONFIG_RBTREE
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#endif
+
+#ifdef CONFIG_USE_SPIFLASH
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_FLASH
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SAVEENV
+#endif
+
+#if !defined(CONFIG_USE_NAND) && \
+	!defined(CONFIG_USE_NOR) && \
+	!defined(CONFIG_USE_SPIFLASH)
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_SIZE		(16 << 10)
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_ENV
+#endif
+
+/* SD/MMC configuration */
+#ifndef CONFIG_USE_NOR
+#define CONFIG_MMC
+#define CONFIG_DAVINCI_MMC_SD1
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DAVINCI_MMC
+#endif
+
+/*
+ * Enable MMC commands only when
+ * MMC support is present
+ */
+#ifdef CONFIG_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_MMC
+#endif
+
+#ifndef CONFIG_DIRECT_NOR_BOOT
+/* defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_TEXT_BASE - \
+						CONFIG_SYS_MALLOC_LEN)
+#define CONFIG_SYS_SPL_MALLOC_SIZE	CONFIG_SYS_MALLOC_LEN
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_BUS 0
+#define CONFIG_SPL_SPI_CS 0
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LDSCRIPT	"board/$(BOARDDIR)/u-boot-spl-da850evm.lds"
+#define CONFIG_SPL_STACK	0x8001ff00
+#define CONFIG_SPL_TEXT_BASE	0x80000000
+#define CONFIG_SPL_MAX_FOOTPRINT	32768
+#endif
+
+/* Load U-Boot Image From MMC */
+#ifdef CONFIG_SPL_MMC_LOAD
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x75
+#undef CONFIG_SPL_SPI_SUPPORT
+#undef CONFIG_SPL_SPI_LOAD
+#endif
+
+/* additions for new relocation code, must added to all boards */
+#define CONFIG_SYS_SDRAM_BASE		0xc0000000
+
+#ifdef CONFIG_DIRECT_NOR_BOOT
+#define CONFIG_SYS_INIT_SP_ADDR		0x8001ff00
+#else
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
+					GENERATED_GBL_DATA_SIZE)
+#endif /* CONFIG_DIRECT_NOR_BOOT */
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/dalmore.h b/qemu/roms/u-boot/include/configs/dalmore.h
new file mode 100644
index 000000000..fd774a331
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/dalmore.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+
+#include "tegra114-common.h"
+
+/* Enable fdt support for Dalmore. Flash the image in u-boot-dtb.bin */
+#define CONFIG_DEFAULT_DEVICE_TREE	tegra114-dalmore
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
+/* High-level configuration options */
+#define V_PROMPT		"Tegra114 (Dalmore) # "
+#define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Dalmore"
+
+/* Board-specific serial config */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_TEGRA_ENABLE_UARTD
+#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_DALMORE
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* I2C */
+#define CONFIG_SYS_I2C_TEGRA
+#define CONFIG_SYS_I2C_INIT_BOARD
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_MAX_I2C_BUS		TEGRA_I2C_NUM_CONTROLLERS
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_TEGRA_MMC
+#define CONFIG_CMD_MMC
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART		2
+#define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE)
+
+#define MACH_TYPE_DALMORE	4304	/* not yet in mach-types.h */
+
+/* SPI */
+#define CONFIG_TEGRA114_SPI
+#define CONFIG_TEGRA114_SPI_CTRLS	6
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SF_DEFAULT_MODE         SPI_MODE_0
+#define CONFIG_SF_DEFAULT_SPEED        24000000
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH_SIZE          (4 << 20)
+
+/* USB Host support */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_TEGRA
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB
+
+/* USB networking support */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+
+/* General networking support */
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/davinci_dm355evm.h b/qemu/roms/u-boot/include/configs/davinci_dm355evm.h
new file mode 100644
index 000000000..c2e187e3d
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/davinci_dm355evm.h
@@ -0,0 +1,204 @@
+/*
+ * Copyright (C) 2009 David Brownell
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* Spectrum Digital TMS320DM355 EVM board */
+#define DAVINCI_DM355EVM
+
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is a 3rd stage loader */
+#define CONFIG_SYS_NO_FLASH		/* that is, no *NOR* flash */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+
+/* SoC Configuration */
+#define CONFIG_ARM926EJS				/* arm926ejs CPU */
+#define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
+#define CONFIG_SYS_HZ_CLOCK		24000000	/* timer0 freq */
+#define CONFIG_SOC_DM355
+
+/* Memory Info */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM_1			0x80000000
+#define PHYS_SDRAM_1_SIZE		(128 << 20)	/* 128 MiB */
+
+/* Serial Driver info: UART0 for console  */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#define CONFIG_SYS_NS16550_COM1		0x01c20000
+#define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_HZ_CLOCK
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+
+/* Ethernet:  external DM9000 */
+#define CONFIG_DRIVER_DM9000		1
+#define CONFIG_DM9000_BASE		0x04014000
+#define DM9000_IO			CONFIG_DM9000_BASE
+#define DM9000_DATA			(CONFIG_DM9000_BASE + 2)
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DAVINCI
+#define CONFIG_SYS_DAVINCI_I2C_SPEED		400000
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE		0x10	/* SMBus host address */
+
+/* NAND: socketed, two chipselects, normally 2 GBytes */
+#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NAND_CS		2
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
+#define CONFIG_SYS_NAND_PAGE_2K
+
+#define CONFIG_SYS_NAND_LARGEPAGE
+#define CONFIG_SYS_NAND_BASE_LIST	{ 0x02000000, }
+/* socket has two chipselects, nCE0 gated by address BIT(14) */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_MAX_CHIPS	2
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DAVINCI_MMC
+#define CONFIG_DAVINCI_MMC_SD1
+#define CONFIG_MMC_MBLOCK
+
+/* USB: OTG connector */
+/* NYET -- #define CONFIG_USB_DAVINCI */
+
+/* U-Boot command configuration */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+
+#ifdef CONFIG_CMD_BDI
+#define CONFIG_CLOCKS
+#endif
+
+#ifdef CONFIG_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_MMC
+#endif
+
+#ifdef CONFIG_NAND_DAVINCI
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_UBI
+#define CONFIG_RBTREE
+#endif
+
+#ifdef CONFIG_USB_DAVINCI
+#define CONFIG_MUSB_HCD
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#else
+#undef CONFIG_MUSB_HCD
+#undef CONFIG_CMD_USB
+#undef CONFIG_USB_STORAGE
+#endif
+
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+
+/* U-Boot general configuration */
+#define CONFIG_BOOTFILE		"uImage"	/* Boot file name */
+#define CONFIG_SYS_PROMPT	"DM355 EVM # "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size  */
+#define CONFIG_SYS_PBSIZE			/* Print buffer size */ \
+		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_LONGHELP
+
+#ifdef CONFIG_NAND_DAVINCI
+#define CONFIG_ENV_SIZE		(256 << 10)	/* 256 KiB */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET	0x3C0000
+#undef CONFIG_ENV_IS_IN_FLASH
+#endif
+
+#if defined(CONFIG_MMC) && !defined(CONFIG_ENV_IS_IN_NAND)
+#define CONFIG_CMD_ENV
+#define CONFIG_ENV_SIZE		(16 << 10)	/* 16 KiB */
+#define CONFIG_ENV_OFFSET	(51 << 9)	/* Sector 51 */
+#define CONFIG_ENV_IS_IN_MMC
+#undef CONFIG_ENV_IS_IN_FLASH
+#endif
+
+#define CONFIG_BOOTDELAY	5
+#define CONFIG_BOOTCOMMAND \
+		"dhcp;bootm"
+#define CONFIG_BOOTARGS \
+		"console=ttyS0,115200n8 " \
+		"root=/dev/mmcblk0p1 rootwait rootfstype=ext3 ro"
+
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_TIMESTAMP
+
+#define CONFIG_NET_RETRY_COUNT 10
+
+/* U-Boot memory configuration */
+#define CONFIG_SYS_MALLOC_LEN		(1 << 20)	/* 1 MiB */
+#define CONFIG_SYS_MEMTEST_START	0x87000000	/* physical address */
+#define CONFIG_SYS_MEMTEST_END		0x88000000	/* test 16MB RAM */
+
+/* Linux interfacing */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_SYS_BARGSIZE	1024			/* bootarg Size */
+#define CONFIG_SYS_LOAD_ADDR	0x80700000		/* kernel address */
+
+
+/* NAND configuration ... socketed with two chipselects.  It normally comes
+ * with a 2GByte SLC part with 2KB pages (and 128KB erase blocks); other
+ * 2GByte parts may have 4KB pages, 256KB erase blocks, and use MLC.  (MLC
+ * pretty much demands the 4-bit ECC support.)  You can of course swap in
+ * other parts, including small page ones.
+ *
+ * This presents a single read-only partition for all bootloader stuff.
+ * UBL (1+ block), U-Boot (256KB+), U-Boot environment (one block), and
+ * some extra space to help cope with bad blocks in that data.  Linux
+ * shouldn't care about its detailed layout, and will probably want to use
+ * UBI/UBFS for the rest (except maybe on smallpage chips).  It's easy to
+ * override this default partitioning using MTDPARTS and cmdlinepart.
+ */
+#define MTDIDS_DEFAULT		"nand0=davinci_nand.0"
+
+#ifdef CONFIG_SYS_NAND_LARGEPAGE
+/*  Use same layout for 128K/256K blocks; allow some bad blocks */
+#define PART_BOOT		"2m(bootloader)ro,"
+#else
+/* Assume 16K erase blocks; allow a few bad ones. */
+#define PART_BOOT		"512k(bootloader)ro,"
+#endif
+
+#define PART_KERNEL		"4m(kernel),"	/* kernel + initramfs */
+#define PART_REST		"-(filesystem)"
+
+#define MTDPARTS_DEFAULT	\
+	"mtdparts=davinci_nand.0:" PART_BOOT PART_KERNEL PART_REST
+
+#define CONFIG_MAX_RAM_BANK_SIZE	(256 << 20)	/* 256 MB */
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR		\
+	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/davinci_dm355leopard.h b/qemu/roms/u-boot/include/configs/davinci_dm355leopard.h
new file mode 100644
index 000000000..5188fdf87
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/davinci_dm355leopard.h
@@ -0,0 +1,149 @@
+/*
+ * Copyright (C) 2009 Texas Instruments Incorporated
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define DAVINCI_DM355LEOPARD
+
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is a 3rd stage loader */
+#define CONFIG_SYS_NO_FLASH		/* that is, no *NOR* flash */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+
+/* SoC Configuration */
+#define CONFIG_ARM926EJS				/* arm926ejs CPU */
+#define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
+#define CONFIG_SYS_HZ_CLOCK		24000000	/* timer0 freq */
+#define CONFIG_SOC_DM355				/* DM355 based board */
+
+/* Memory Info */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM_1			0x80000000
+#define PHYS_SDRAM_1_SIZE		(128 << 20)	/* 128 MiB */
+
+/* Serial Driver info: UART0 for console  */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#define CONFIG_SYS_NS16550_COM1		0x01c20000
+#define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_HZ_CLOCK
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+
+/* Ethernet:  external DM9000 */
+#define CONFIG_DRIVER_DM9000		1
+#define CONFIG_DM9000_BASE		0x04000000
+#define DM9000_IO			CONFIG_DM9000_BASE
+#define DM9000_DATA			(CONFIG_DM9000_BASE + 16)
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DAVINCI
+#define CONFIG_SYS_DAVINCI_I2C_SPEED		400000
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE		0x10
+
+/* NAND */
+#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NAND_CS		2
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_HW_ECC
+
+#define CONFIG_SYS_NAND_BASE_LIST	{ 0x02000000, }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+
+/* U-Boot command configuration */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+
+#ifdef CONFIG_CMD_BDI
+#define CONFIG_CLOCKS
+#endif
+
+#ifdef CONFIG_NAND_DAVINCI
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_UBI
+#define CONFIG_RBTREE
+#endif
+
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+
+/* U-Boot general configuration */
+#define CONFIG_BOOTFILE		"uImage"	/* Boot file name */
+#define CONFIG_SYS_PROMPT	"DM355 LEOPARD # "
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size  */
+#define CONFIG_SYS_PBSIZE			/* Print buffer size */ \
+		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_LONGHELP
+
+#ifdef CONFIG_NAND_DAVINCI
+#define CONFIG_ENV_SIZE		(256 << 10)	/* 256 KiB */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET	0x3C0000
+#undef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE
+#endif
+
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTCOMMAND	"dhcp;bootm"
+#define CONFIG_BOOTARGS		\
+			"console=ttyS0,115200n8 " \
+			"root=/dev/mmcblk0p1 rootwait rootfstype=ext3 ro"
+
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_TIMESTAMP
+
+#define CONFIG_NET_RETRY_COUNT 10
+
+/* U-Boot memory configuration */
+#define CONFIG_SYS_MALLOC_LEN		(1 << 20)	/* 1 MiB */
+#define CONFIG_SYS_MEMTEST_START	0x87000000	/* physical address */
+#define CONFIG_SYS_MEMTEST_END		0x88000000	/* test 16MB RAM */
+
+/* Linux interfacing */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_SYS_BARGSIZE	1024			/* bootarg Size */
+#define CONFIG_SYS_LOAD_ADDR	0x80700000		/* kernel address */
+
+#define MTDIDS_DEFAULT		"nand0=davinci_nand.0"
+
+#ifdef CONFIG_SYS_NAND_LARGEPAGE
+#define PART_BOOT		"2m(bootloader)ro,"
+#else
+/* Assume 16K erase blocks; allow a few bad ones. */
+#define PART_BOOT		"512k(bootloader)ro,"
+#endif
+
+#define PART_KERNEL		"4m(kernel),"	/* kernel + initramfs */
+#define PART_REST		"-(filesystem)"
+
+#define MTDPARTS_DEFAULT	\
+	"mtdparts=davinci_nand.0:" PART_BOOT PART_KERNEL PART_REST
+
+#define CONFIG_MAX_RAM_BANK_SIZE	(256 << 20)	/* 256 MB */
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR		\
+	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/davinci_dm365evm.h b/qemu/roms/u-boot/include/configs/davinci_dm365evm.h
new file mode 100644
index 000000000..c4fccfd39
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/davinci_dm365evm.h
@@ -0,0 +1,229 @@
+/*
+ * Copyright (C) 2009 Texas Instruments Incorporated
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* Spectrum Digital TMS320DM365 EVM board */
+#define DAVINCI_DM365EVM
+
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is a 3rd stage loader */
+#define CONFIG_SYS_NO_FLASH		/* that is, no *NOR* flash */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+
+/* SoC Configuration */
+#define CONFIG_ARM926EJS				/* arm926ejs CPU */
+#define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
+#define CONFIG_SYS_HZ_CLOCK		24000000	/* timer0 freq */
+#define CONFIG_SOC_DM365
+
+/* Memory Info */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM_1			0x80000000
+#define PHYS_SDRAM_1_SIZE		(128 << 20)	/* 128 MiB */
+
+/* Serial Driver info: UART0 for console  */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#define CONFIG_SYS_NS16550_COM1		0x01c20000
+#define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_HZ_CLOCK
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+
+/* EEPROM definitions for EEPROM on DM365 EVM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	20
+
+/* Network Configuration */
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_MII
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT	10
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DAVINCI
+#define CONFIG_SYS_DAVINCI_I2C_SPEED		400000
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE		0x10	/* SMBus host address */
+
+/* NAND: socketed, two chipselects, normally 2 GBytes */
+#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NAND_CS		2
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
+#define CONFIG_SYS_NAND_PAGE_2K
+
+#define CONFIG_SYS_NAND_LARGEPAGE
+#define CONFIG_SYS_NAND_BASE_LIST	{ 0x02000000, }
+/* socket has two chipselects, nCE0 gated by address BIT(14) */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_MAX_CHIPS	2
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DAVINCI_MMC
+#define CONFIG_DAVINCI_MMC_SD1
+#define CONFIG_MMC_MBLOCK
+
+#define PINMUX4_USBDRVBUS_BITCLEAR       0x3000
+#define PINMUX4_USBDRVBUS_BITSET         0x2000
+
+/* USB Configuration */
+#define CONFIG_USB_DAVINCI
+#define CONFIG_MUSB_HCD
+
+#ifdef CONFIG_USB_DAVINCI
+#define CONFIG_CMD_USB         /* include support for usb      */
+#define CONFIG_CMD_STORAGE     /* include support for usb      */
+#define CONFIG_CMD_FAT         /* include support for FAT/storage*/
+#define CONFIG_DOS_PARTITION   /* include support for FAT/storage*/
+#endif
+
+#ifdef CONFIG_MUSB_HCD         /* include support for usb host */
+#define CONFIG_CMD_USB         /* include support for usb cmd */
+#define CONFIG_USB_STORAGE     /* MSC class support */
+#define CONFIG_CMD_STORAGE     /* inclue support for usb-storage cmd */
+#define CONFIG_CMD_FAT         /* inclue support for FAT/storage */
+#define CONFIG_DOS_PARTITION   /* inclue support for FAT/storage */
+
+#ifdef CONFIG_USB_KEYBOARD     /* HID class support */
+#define CONFIG_SYS_USB_EVENT_POLL
+
+#define CONFIG_PREBOOT "usb start"
+#endif /* CONFIG_USB_KEYBOARD */
+#endif /* CONFIG_MUSB_HCD */
+
+#ifdef CONFIG_MUSB_UDC
+#define CONFIG_USB_DEVICE              1
+#define CONFIG_USB_TTY                 1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV   1
+#define CONFIG_USBD_VENDORID           0x0451
+#define CONFIG_USBD_PRODUCTID          0x5678
+#define CONFIG_USBD_MANUFACTURER       "Texas Instruments"
+#define CONFIG_USBD_PRODUCT_NAME       "DM365VM"
+#endif /* CONFIG_MUSB_UDC */
+
+/* U-Boot command configuration */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+
+#ifdef CONFIG_CMD_BDI
+#define CONFIG_CLOCKS
+#endif
+
+#ifdef CONFIG_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_MMC
+#endif
+
+#ifdef CONFIG_NAND_DAVINCI
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_UBI
+#define CONFIG_RBTREE
+#endif
+
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+
+/* U-Boot general configuration */
+#define CONFIG_BOOTFILE		"uImage"	/* Boot file name */
+#define CONFIG_SYS_PROMPT	"DM36x EVM # "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size  */
+#define CONFIG_SYS_PBSIZE			/* Print buffer size */ \
+		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_LONGHELP
+
+#ifdef CONFIG_NAND_DAVINCI
+#define CONFIG_ENV_SIZE		(256 << 10)	/* 256 KiB */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET	0x3C0000
+#undef CONFIG_ENV_IS_IN_FLASH
+#endif
+
+#if defined(CONFIG_MMC) && !defined(CONFIG_ENV_IS_IN_NAND)
+#define CONFIG_CMD_ENV
+#define CONFIG_ENV_SIZE		(16 << 10)	/* 16 KiB */
+#define CONFIG_ENV_OFFSET	(51 << 9)	/* Sector 51 */
+#define CONFIG_ENV_IS_IN_MMC
+#undef CONFIG_ENV_IS_IN_FLASH
+#endif
+
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTCOMMAND \
+		"dhcp;bootm"
+#define CONFIG_BOOTARGS \
+		"console=ttyS0,115200n8 " \
+		"root=/dev/mmcblk0p1 rootwait rootfstype=ext3 ro"
+
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_TIMESTAMP
+
+/* U-Boot memory configuration */
+#define CONFIG_SYS_MALLOC_LEN		(1 << 20)	/* 1 MiB */
+#define CONFIG_SYS_MEMTEST_START	0x87000000	/* physical address */
+#define CONFIG_SYS_MEMTEST_END		0x88000000	/* test 16MB RAM */
+
+/* Linux interfacing */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_SYS_BARGSIZE	1024			/* bootarg Size */
+#define CONFIG_SYS_LOAD_ADDR	0x80700000		/* kernel address */
+
+
+/* NAND configuration issocketed with two chipselects just like the DM355 EVM.
+ * It normally comes with a 2GByte SLC part with 2KB pages
+ * (and 128KB erase blocks); other
+ * 2GByte parts may have 4KB pages, 256KB erase blocks, and use MLC.  (MLC
+ * pretty much demands the 4-bit ECC support.)  You can of course swap in
+ * other parts, including small page ones.
+ */
+#define MTDIDS_DEFAULT		"nand0=davinci_nand.0"
+
+#ifdef CONFIG_SYS_NAND_LARGEPAGE
+/*  Use same layout for 128K/256K blocks; allow some bad blocks */
+#define PART_BOOT		"2m(bootloader)ro,"
+#else
+/* Assume 16K erase blocks; allow a few bad ones. */
+#define PART_BOOT		"512k(bootloader)ro,"
+#endif
+
+#define PART_KERNEL		"4m(kernel),"	/* kernel + initramfs */
+#define PART_REST		"-(filesystem)"
+
+#define MTDPARTS_DEFAULT	\
+	"mtdparts=davinci_nand.0:" PART_BOOT PART_KERNEL PART_REST
+
+#define CONFIG_MAX_RAM_BANK_SIZE	(256 << 20)	/* 256 MB */
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR		\
+	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/davinci_dm6467evm.h b/qemu/roms/u-boot/include/configs/davinci_dm6467evm.h
new file mode 100644
index 000000000..8a3c45334
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/davinci_dm6467evm.h
@@ -0,0 +1,145 @@
+/*
+ * Copyright (C) 2009 Texas Instruments Incorporated
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* Spectrum Digital TMS320DM6467 EVM board */
+#define DAVINCI_DM6467EVM
+#define CONFIG_SYS_USE_NAND
+#define CONFIG_SYS_NAND_SMALLPAGE
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* SoC Configuration */
+#define CONFIG_ARM926EJS				/* arm926ejs CPU */
+
+/* Clock rates detection */
+#ifndef __ASSEMBLY__
+extern unsigned int davinci_arm_clk_get(void);
+#endif
+
+/* Arm Clock frequency    */
+#define CONFIG_SYS_CLK_FREQ	davinci_arm_clk_get()
+/* Timer Input clock freq */
+#define CONFIG_SYS_HZ_CLOCK		(CONFIG_SYS_CLK_FREQ/2)
+#define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
+#define CONFIG_SOC_DM646X
+
+/* EEPROM definitions for EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	20
+
+/* Memory Info */
+#define CONFIG_SYS_MALLOC_LEN		(1 << 20)	/* 1 MiB */
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		0x81000000	/* 16MB RAM test */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM_1			0x80000000	/* DDR Start */
+#define PHYS_SDRAM_1_SIZE		(256 << 20)	/* DDR size 256MB */
+
+/* Linux interfacing */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_SYS_BARGSIZE		1024		/* Bootarg Size */
+#define CONFIG_SYS_LOAD_ADDR		0x80700000	/* kernel address */
+#define CONFIG_REVISION_TAG
+
+/* Serial Driver info */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	4
+#define CONFIG_SYS_NS16550_COM1		0x01c20000
+#define CONFIG_SYS_NS16550_CLK		24000000
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+
+/* I2C Configuration */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DAVINCI
+#define CONFIG_SYS_DAVINCI_I2C_SPEED		80000
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE		10
+
+/* Network & Ethernet Configuration */
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_MII
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT	10
+#define CONFIG_CMD_NET
+
+/* Flash & Environment */
+#define CONFIG_SYS_NO_FLASH
+#ifdef CONFIG_SYS_USE_NAND
+#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NAND_CS		2
+#undef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE			(16 << 10)	/* 16 KiB */
+#define CONFIG_SYS_NAND_BASE_LIST	{0x42000000, }
+#define CONFIG_SYS_NAND_HW_ECC
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_ENV_OFFSET		0
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE			(4 << 10)	/* 4 KiB */
+#endif
+
+/* U-Boot general configuration */
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTFILE		"uImage"	/* Boot file name */
+#define CONFIG_SYS_PROMPT	"DM6467 EVM > "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size  */
+#define CONFIG_SYS_PBSIZE		\
+			(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+#define CONFIG_BOOTCOMMAND		"source 0x82080000; dhcp; bootm"
+#define CONFIG_BOOTARGS			\
+					"mem=120M console=ttyS0,115200n8 " \
+					"root=/dev/hda1 rw noinitrd ip=dhcp"
+
+/* U-Boot commands */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#ifdef CONFIG_SYS_USE_NAND
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_NAND
+#endif
+
+#ifdef CONFIG_CMD_BDI
+#define CONFIG_CLOCKS
+#endif
+
+#define CONFIG_MAX_RAM_BANK_SIZE	(256 << 20)	/* 256 MB */
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/davinci_dvevm.h b/qemu/roms/u-boot/include/configs/davinci_dvevm.h
new file mode 100644
index 000000000..9b3d0febc
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/davinci_dvevm.h
@@ -0,0 +1,224 @@
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Define this to make U-Boot skip low level initialization when loaded
+ * by initial bootloader. Not required by NAND U-Boot version but IS
+ * required for a NOR version used to burn the real NOR U-Boot into
+ * NOR Flash. NAND and NOR support for DaVinci chips is mutually exclusive
+ * so it is NOT possible to build a U-Boot with both NAND and NOR routines.
+ * NOR U-Boot is loaded directly from Flash so it must perform all the
+ * low level initialization itself. NAND version is loaded by an initial
+ * bootloader (UBL in TI-ese) that performs such an initialization so it's
+ * skipped in NAND version. The third DaVinci boot mode loads a bootloader
+ * via UART0 and that bootloader in turn loads and runs U-Boot (or whatever)
+ * performing low level init prior to loading. All that means we can NOT use
+ * NAND version to put U-Boot into NOR because it doesn't have NOR support and
+ * we can NOT use NOR version because it performs low level initialization
+ * effectively destroying itself in DDR memory. That's why a separate NOR
+ * version with this define is needed. It is loaded via UART, then one uses
+ * it to somehow download a proper NOR version built WITHOUT this define to
+ * RAM (tftp?) and burn it to NOR Flash. I would be probably able to squeeze
+ * NOR support into the initial bootloader so it won't be needed but DaVinci
+ * static RAM might be too small for this (I have something like 2Kbytes left
+ * as of now, without NOR support) so this might've not happened...
+ *
+#define CONFIG_NOR_UART_BOOT
+ */
+
+/*=======*/
+/* Board */
+/*=======*/
+#define DV_EVM
+#define CONFIG_SYS_NAND_SMALLPAGE
+#define CONFIG_SYS_USE_NAND
+/*===================*/
+/* SoC Configuration */
+/*===================*/
+#define CONFIG_ARM926EJS			/* arm926ejs CPU core */
+#define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
+#define CONFIG_SYS_HZ_CLOCK		27000000	/* Timer Input clock freq */
+#define CONFIG_SOC_DM644X
+/*====================================================*/
+/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
+/* on Sonata/DV_EVM board. No EEPROM on schmoogie.    */
+/*====================================================*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	20
+/*=============*/
+/* Memory Info */
+/*=============*/
+#define CONFIG_SYS_MALLOC_LEN		(0x10000 + 128*1024)	/* malloc() len */
+#define CONFIG_SYS_MEMTEST_START	0x80000000	/* memtest start address */
+#define CONFIG_SYS_MEMTEST_END		0x81000000	/* 16MB RAM test */
+#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1		0x80000000	/* DDR Start */
+#define PHYS_SDRAM_1_SIZE	0x10000000	/* DDR size 256MB */
+
+#define DDR_8BANKS				/* 8-bank DDR2 (256MB) */
+/*====================*/
+/* Serial Driver info */
+/*====================*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	-4	/* NS16550 register size, byteorder */
+#define CONFIG_SYS_NS16550_COM1	0x01c20000	/* Base address of UART0 */
+#define CONFIG_SYS_NS16550_CLK	CONFIG_SYS_HZ_CLOCK	/* Input clock to NS16550 */
+#define CONFIG_CONS_INDEX	1		/* use UART0 for console */
+#define CONFIG_BAUDRATE		115200		/* Default baud rate */
+/*===================*/
+/* I2C Configuration */
+/*===================*/
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DAVINCI
+#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10	/* Bogus, master-only in U-Boot */
+/*==================================*/
+/* Network & Ethernet Configuration */
+/*==================================*/
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_MII
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT	10
+/*=====================*/
+/* Flash & Environment */
+/*=====================*/
+#ifdef CONFIG_SYS_USE_NAND
+#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NAND_CS		2
+#undef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_IS_IN_NAND		/* U-Boot env in NAND Flash  */
+#ifdef CONFIG_SYS_NAND_SMALLPAGE
+#define CONFIG_ENV_SECT_SIZE	512	/* Env sector Size */
+#define CONFIG_ENV_SIZE		(16 << 10)	/* 16 KiB */
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_CMD_MTDPARTS
+#define MTDIDS_DEFAULT		\
+	"nand0=davinci_nand.0"
+#define MTDPARTS_DEFAULT	\
+	"mtdparts=davinci_nand.0:384k(bootloader)ro,4m(kernel),-(filesystem)"
+#else
+#define CONFIG_ENV_SECT_SIZE	2048	/* Env sector Size */
+#define CONFIG_ENV_SIZE		(128 << 10)	/* 128 KiB */
+#endif
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is loaded by a bootloader */
+#define CONFIG_SYS_NAND_BASE		0x02000000
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_HW_ECC
+#define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND devices */
+#define CONFIG_ENV_OFFSET		0x0	/* Block 0--not used by bootcode */
+#elif defined(CONFIG_SYS_USE_NOR)
+#ifdef CONFIG_NOR_UART_BOOT
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is loaded by a bootloader */
+#else
+#undef CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+#define CONFIG_ENV_IS_IN_FLASH
+#undef CONFIG_SYS_NO_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* max number of flash banks */
+#define CONFIG_SYS_FLASH_SECT_SZ	0x10000		/* 64KB sect size AMD Flash */
+#define CONFIG_ENV_OFFSET		(CONFIG_SYS_FLASH_SECT_SZ*3)
+#define PHYS_FLASH_1		0x02000000	/* CS2 Base address	 */
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1	/* Flash Base for U-Boot */
+#define PHYS_FLASH_SIZE		0x2000000	/* Flash size 32MB	 */
+#define CONFIG_SYS_MAX_FLASH_SECT	(PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)
+#define CONFIG_ENV_SECT_SIZE	CONFIG_SYS_FLASH_SECT_SZ	/* Env sector Size */
+#endif
+/*==============================*/
+/* U-Boot general configuration */
+/*==============================*/
+#define CONFIG_MISC_INIT_R
+#undef CONFIG_BOOTDELAY
+#define CONFIG_BOOTFILE		"uImage"	/* Boot file name */
+#define CONFIG_SYS_PROMPT		"U-Boot > "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size  */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print buffer sz */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_LOAD_ADDR		0x80700000	/* default Linux kernel load address */
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE		/* Won't work with hush so far, may be later */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+#define CONFIG_MUSB_HCD
+#define CONFIG_USB_DAVINCI
+/*===================*/
+/* Linux Information */
+/*===================*/
+#define LINUX_BOOT_PARAM_ADDR	0x80000100
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTARGS		"mem=120M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp"
+#define CONFIG_BOOTCOMMAND	"setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot; bootm 0x2050000"
+/*=================*/
+/* U-Boot commands */
+/*=================*/
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_BDI
+
+#ifdef CONFIG_CMD_BDI
+#define CONFIG_CLOCKS
+#endif
+
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#ifdef CONFIG_SYS_USE_NAND
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_NAND
+#elif defined(CONFIG_SYS_USE_NOR)
+#define CONFIG_CMD_JFFS2
+#else
+#error "Either CONFIG_SYS_USE_NAND or CONFIG_SYS_USE_NOR _MUST_ be defined !!!"
+#endif
+/*==========================*/
+/* USB MSC support (if any) */
+/*==========================*/
+#ifdef CONFIG_USB_DAVINCI
+#define CONFIG_CMD_USB
+#ifdef CONFIG_MUSB_HCD
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_STORAGE
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+#ifdef CONFIG_USB_KEYBOARD
+#define CONFIG_SYS_USB_EVENT_POLL
+#define CONFIG_PREBOOT "usb start"
+#endif
+#endif
+
+#define CONFIG_MAX_RAM_BANK_SIZE	(256 << 20)	/* 256 MB */
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/davinci_schmoogie.h b/qemu/roms/u-boot/include/configs/davinci_schmoogie.h
new file mode 100644
index 000000000..96c8fe2a4
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/davinci_schmoogie.h
@@ -0,0 +1,144 @@
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*=======*/
+/* Board */
+/*=======*/
+#define SCHMOOGIE
+#define CONFIG_SYS_NAND_LARGEPAGE
+#define CONFIG_SYS_USE_NAND
+#define MACH_TYPE_SCHMOOGIE 1255
+#define CONFIG_MACH_TYPE MACH_TYPE_SCHMOOGIE
+
+/*===================*/
+/* SoC Configuration */
+/*===================*/
+#define CONFIG_ARM926EJS			/* arm926ejs CPU core */
+#define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
+#define CONFIG_SYS_HZ_CLOCK		27000000	/* Timer Input clock freq */
+#define CONFIG_SOC_DM644X
+/*=============*/
+/* Memory Info */
+/*=============*/
+#define CONFIG_SYS_MALLOC_LEN		(0x10000 + 256*1024)	/* malloc() len */
+#define CONFIG_SYS_MEMTEST_START	0x80000000	/* memtest start address */
+#define CONFIG_SYS_MEMTEST_END		0x81000000	/* 16MB RAM test */
+#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1		0x80000000	/* DDR Start */
+#define PHYS_SDRAM_1_SIZE	0x08000000	/* DDR size 128MB */
+#define DDR_4BANKS				/* 4-bank DDR2 (128MB) */
+/*====================*/
+/* Serial Driver info */
+/*====================*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	-4	/* NS16550 register size, byteorder */
+#define CONFIG_SYS_NS16550_COM1	0x01c20000	/* Base address of UART0 */
+#define CONFIG_SYS_NS16550_CLK	CONFIG_SYS_HZ_CLOCK	/* Input clock to NS16550 */
+#define CONFIG_CONS_INDEX	1		/* use UART0 for console */
+#define CONFIG_BAUDRATE		115200		/* Default baud rate */
+/*===================*/
+/* I2C Configuration */
+/*===================*/
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DAVINCI
+#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10    /* Bogus, master-only in U-Boot */
+/*==================================*/
+/* Network & Ethernet Configuration */
+/*==================================*/
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_MII
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT	10
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
+/*=====================*/
+/* Flash & Environment */
+/*=====================*/
+#undef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NAND_CS		2
+#define CONFIG_ENV_IS_IN_NAND		/* U-Boot env in NAND Flash  */
+#define CONFIG_ENV_SECT_SIZE	2048	/* Env sector Size */
+#define CONFIG_ENV_SIZE		(128 << 10)	/* 128 KiB */
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is loaded by a bootloader */
+#define CONFIG_SYS_NAND_BASE		0x02000000
+#define CONFIG_SYS_NAND_HW_ECC
+#define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND devices */
+#define CONFIG_ENV_OFFSET		0x0	/* Block 0--not used by bootcode */
+/*=====================*/
+/* Board related stuff */
+/*=====================*/
+#define CONFIG_RTC_DS1307		/* RTC chip on SCHMOOGIE */
+#define CONFIG_SYS_I2C_RTC_ADDR	0x6f	/* RTC chip I2C address */
+#define CONFIG_UID_DS28CM00		/* Unique ID on SCHMOOGIE */
+#define CONFIG_SYS_UID_ADDR		0x50	/* UID chip I2C address */
+/*==============================*/
+/* U-Boot general configuration */
+/*==============================*/
+#define CONFIG_MISC_INIT_R
+#undef CONFIG_BOOTDELAY
+#define CONFIG_BOOTFILE		"uImage"	/* Boot file name */
+#define CONFIG_SYS_PROMPT		"U-Boot > "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size  */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print buffer sz */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_LOAD_ADDR		0x80700000	/* default Linux kernel load address */
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE		/* Won't work with hush so far, may be later */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+/*===================*/
+/* Linux Information */
+/*===================*/
+#define LINUX_BOOT_PARAM_ADDR	0x80000100
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTARGS		"mem=56M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp"
+#define CONFIG_BOOTCOMMAND	"setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot"
+/*=================*/
+/* U-Boot commands */
+/*=================*/
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_NAND
+#undef CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+
+#ifdef CONFIG_CMD_BDI
+#define CONFIG_CLOCKS
+#endif
+
+#define CONFIG_MAX_RAM_BANK_SIZE	(256 << 20)	/* 256 MB */
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/davinci_sffsdr.h b/qemu/roms/u-boot/include/configs/davinci_sffsdr.h
new file mode 100644
index 000000000..6e07cce76
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/davinci_sffsdr.h
@@ -0,0 +1,137 @@
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
+ * Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* Board */
+#define SFFSDR
+#define CONFIG_SYS_NAND_LARGEPAGE
+#define CONFIG_SYS_USE_NAND
+#define CONFIG_SYS_USE_DSPLINK		/* don't power up the DSP. */
+/* SoC Configuration */
+#define CONFIG_ARM926EJS			/* arm926ejs CPU core */
+#define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
+#define CONFIG_SYS_HZ_CLOCK		27000000	/* Timer Input clock freq */
+#define CONFIG_SOC_DM644X
+/* EEPROM definitions for Atmel 24LC64 EEPROM chip */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	20
+/* Memory Info */
+#define CONFIG_SYS_MALLOC_LEN		(0x10000 + 256*1024)	/* malloc() len */
+#define CONFIG_SYS_MEMTEST_START	0x80000000	/* memtest start address */
+#define CONFIG_SYS_MEMTEST_END		0x81000000	/* 16MB RAM test */
+#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1		0x80000000	/* DDR Start */
+#define PHYS_SDRAM_1_SIZE	0x08000000	/* DDR size 128MB */
+#define DDR_4BANKS				/* 4-bank DDR2 (128MB) */
+/* Serial Driver info */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	-4	/* NS16550 register size, byteorder */
+#define CONFIG_SYS_NS16550_COM1	0x01c20000	/* Base address of UART0 */
+#define CONFIG_SYS_NS16550_CLK	CONFIG_SYS_HZ_CLOCK	/* Input clock to NS16550 */
+#define CONFIG_CONS_INDEX	1		/* use UART0 for console */
+#define CONFIG_BAUDRATE		115200		/* Default baud rate */
+/* I2C Configuration */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DAVINCI
+#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10    /* Bogus, master-only in U-Boot */
+/* Network & Ethernet Configuration */
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_MII
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT	10
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
+/* Flash & Environment */
+#undef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NAND_CS		2
+#define CONFIG_ENV_IS_IN_NAND		/* U-Boot env in NAND Flash  */
+#define CONFIG_ENV_SECT_SIZE	2048	/* Env sector Size */
+#define CONFIG_ENV_SIZE		(128 << 10)	/* 128 KiB */
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is loaded by a bootloader */
+#define CONFIG_SYS_NAND_BASE		0x02000000
+#define CONFIG_SYS_NAND_HW_ECC
+#define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND devices */
+#define CONFIG_ENV_OFFSET		0x0	/* Block 0--not used by bootcode */
+/* I2C switch definitions for PCA9543 chip */
+#define CONFIG_SYS_I2C_PCA9543_ADDR		0x70
+#define CONFIG_SYS_I2C_PCA9543_ADDR_LEN	0	/* Single register. */
+#define CONFIG_SYS_I2C_PCA9543_ENABLE_CH0	0x01	/* Enable channel 0. */
+/* U-Boot general configuration */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_BOOTDELAY	5		/* Autoboot after 5 seconds. */
+#define CONFIG_BOOTFILE		"uImage"	/* Boot file name */
+#define CONFIG_SYS_PROMPT		"U-Boot > "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size  */
+#define CONFIG_SYS_PBSIZE							\
+		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)	/* Print buffer size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_LOAD_ADDR		0x80700000	/* Default Linux kernel
+						 * load address. */
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE		/* Won't work with hush so far,
+					 * may be later */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+/* Linux Information */
+#define LINUX_BOOT_PARAM_ADDR	0x80000100
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTARGS			\
+	"mem=56M "			\
+	"console=ttyS0,115200n8 "	\
+	"root=/dev/nfs rw noinitrd ip=dhcp "	\
+	"nfsroot=${serverip}:/nfsroot/sffsdr "	\
+	"eth0=${ethaddr}"
+#define CONFIG_BOOTCOMMAND	\
+	"nand read 87A00000 100000 300000;"	\
+	"bootelf 87A00000"
+/* U-Boot commands */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF	/* Needed to load Integrity kernel. */
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+
+#ifdef CONFIG_CMD_BDI
+#define CONFIG_CLOCKS
+#endif
+
+#define CONFIG_MAX_RAM_BANK_SIZE	(256 << 20)	/* 256 MB */
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/davinci_sonata.h b/qemu/roms/u-boot/include/configs/davinci_sonata.h
new file mode 100644
index 000000000..cd23aaca2
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/davinci_sonata.h
@@ -0,0 +1,195 @@
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Define this to make U-Boot skip low level initialization when loaded
+ * by initial bootloader. Not required by NAND U-Boot version but IS
+ * required for a NOR version used to burn the real NOR U-Boot into
+ * NOR Flash. NAND and NOR support for DaVinci chips is mutually exclusive
+ * so it is NOT possible to build a U-Boot with both NAND and NOR routines.
+ * NOR U-Boot is loaded directly from Flash so it must perform all the
+ * low level initialization itself. NAND version is loaded by an initial
+ * bootloader (UBL in TI-ese) that performs such an initialization so it's
+ * skipped in NAND version. The third DaVinci boot mode loads a bootloader
+ * via UART0 and that bootloader in turn loads and runs U-Boot (or whatever)
+ * performing low level init prior to loading. All that means we can NOT use
+ * NAND version to put U-Boot into NOR because it doesn't have NOR support and
+ * we can NOT use NOR version because it performs low level initialization
+ * effectively destroying itself in DDR memory. That's why a separate NOR
+ * version with this define is needed. It is loaded via UART, then one uses
+ * it to somehow download a proper NOR version built WITHOUT this define to
+ * RAM (tftp?) and burn it to NOR Flash. I would be probably able to squeeze
+ * NOR support into the initial bootloader so it won't be needed but DaVinci
+ * static RAM might be too small for this (I have something like 2Kbytes left
+ * as of now, without NOR support) so this might've not happened...
+ *
+#define CONFIG_NOR_UART_BOOT
+ */
+
+/*=======*/
+/* Board */
+/*=======*/
+#define SONATA_BOARD
+#define CONFIG_SYS_NAND_SMALLPAGE
+#define CONFIG_SYS_USE_NOR
+#define MACH_TYPE_SONATA 1254
+#define CONFIG_MACH_TYPE MACH_TYPE_SONATA
+/*===================*/
+/* SoC Configuration */
+/*===================*/
+#define CONFIG_ARM926EJS			/* arm926ejs CPU core */
+#define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
+#define CONFIG_SYS_HZ_CLOCK		27000000	/* Timer Input clock freq */
+#define CONFIG_SOC_DM644X
+/*====================================================*/
+/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
+/* on Sonata/DV_EVM board. No EEPROM on schmoogie.    */
+/*====================================================*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	20
+/*=============*/
+/* Memory Info */
+/*=============*/
+#define CONFIG_SYS_MALLOC_LEN		(0x10000 + 128*1024)	/* malloc() len */
+#define CONFIG_SYS_MEMTEST_START	0x80000000	/* memtest start address */
+#define CONFIG_SYS_MEMTEST_END		0x81000000	/* 16MB RAM test */
+#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1		0x80000000	/* DDR Start */
+#define PHYS_SDRAM_1_SIZE	0x08000000	/* DDR size 128MB */
+#define DDR_4BANKS				/* 4-bank DDR2 (128MB) */
+/*====================*/
+/* Serial Driver info */
+/*====================*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	-4	/* NS16550 register size, byteorder */
+#define CONFIG_SYS_NS16550_COM1	0x01c20000	/* Base address of UART0 */
+#define CONFIG_SYS_NS16550_CLK	CONFIG_SYS_HZ_CLOCK	/* Input clock to NS16550 */
+#define CONFIG_CONS_INDEX	1		/* use UART0 for console */
+#define CONFIG_BAUDRATE		115200		/* Default baud rate */
+/*===================*/
+/* I2C Configuration */
+/*===================*/
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DAVINCI
+#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10    /* Bogus, master-only in U-Boot */
+/*==================================*/
+/* Network & Ethernet Configuration */
+/*==================================*/
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_MII
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT	10
+/*=====================*/
+/* Flash & Environment */
+/*=====================*/
+#ifdef CONFIG_SYS_USE_NAND
+#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NAND_CS		2
+#undef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_OVERWRITE		/* instead if obsoleted forceenv() */
+#define CONFIG_ENV_IS_IN_NAND		/* U-Boot env in NAND Flash  */
+#define CONFIG_ENV_SECT_SIZE	512	/* Env sector Size */
+#define CONFIG_ENV_SIZE		(16 << 10)	/* 16 KiB */
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is loaded by a bootloader */
+#define CONFIG_SYS_NAND_BASE		0x02000000
+#define CONFIG_SYS_NAND_HW_ECC
+#define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND devices */
+#define CONFIG_ENV_OFFSET		0x0	/* Block 0--not used by bootcode */
+#elif defined(CONFIG_SYS_USE_NOR)
+#ifdef CONFIG_NOR_UART_BOOT
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is loaded by a bootloader */
+#else
+#undef CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+#define CONFIG_ENV_IS_IN_FLASH
+#undef CONFIG_SYS_NO_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* max number of flash banks */
+#define CONFIG_SYS_FLASH_SECT_SZ	0x20000		/* 128KB sect size AMD Flash */
+#define CONFIG_ENV_OFFSET		(CONFIG_SYS_FLASH_SECT_SZ*2)
+#define CONFIG_ENV_SIZE		CONFIG_SYS_FLASH_SECT_SZ
+#define PHYS_FLASH_1		0x02000000	/* CS2 Base address	 */
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1	/* Flash Base for U-Boot */
+#define PHYS_FLASH_SIZE		0x2000000	/* Flash size 32MB	 */
+#define CONFIG_SYS_MAX_FLASH_SECT	(PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)
+#define CONFIG_ENV_SECT_SIZE	CONFIG_SYS_FLASH_SECT_SZ	/* Env sector Size */
+#endif
+/*==============================*/
+/* U-Boot general configuration */
+/*==============================*/
+#define CONFIG_MISC_INIT_R
+#undef CONFIG_BOOTDELAY
+#define CONFIG_BOOTFILE		"uImage"	/* Boot file name */
+#define CONFIG_SYS_PROMPT		"U-Boot > "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size  */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print buffer sz */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_LOAD_ADDR		0x80700000	/* default Linux kernel load address */
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE		/* Won't work with hush so far, may be later */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+/*===================*/
+/* Linux Information */
+/*===================*/
+#define LINUX_BOOT_PARAM_ADDR	0x80000100
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTARGS		"mem=56M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp"
+#define CONFIG_BOOTCOMMAND	"setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot; bootm 0x2060000"
+/*=================*/
+/* U-Boot commands */
+/*=================*/
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#ifdef CONFIG_SYS_USE_NAND
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_NAND
+#elif defined(CONFIG_SYS_USE_NOR)
+#define CONFIG_CMD_JFFS2
+#else
+#error "Either CONFIG_SYS_USE_NAND or CONFIG_SYS_USE_NOR _MUST_ be defined !!!"
+#endif
+
+#ifdef CONFIG_CMD_BDI
+#define CONFIG_CLOCKS
+#endif
+
+#define CONFIG_MAX_RAM_BANK_SIZE	(256 << 20)	/* 256 MB */
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/dbau1x00.h b/qemu/roms/u-boot/include/configs/dbau1x00.h
new file mode 100644
index 000000000..e0bf3dc61
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/dbau1x00.h
@@ -0,0 +1,240 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * This file contains the configuration parameters for the dbau1x00 board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_DBAU1X00		1
+#define CONFIG_SOC_AU1X00	1  /* alchemy series cpu */
+
+#ifdef CONFIG_DBAU1000
+/* Also known as Merlot */
+#define CONFIG_SOC_AU1000	1
+#else
+#ifdef CONFIG_DBAU1100
+#define CONFIG_SOC_AU1100	1
+#else
+#ifdef CONFIG_DBAU1500
+#define CONFIG_SOC_AU1500	1
+#else
+#ifdef CONFIG_DBAU1550
+/* Cabernet */
+#define CONFIG_SOC_AU1550	1
+#else
+#error "No valid board set"
+#endif
+#endif
+#endif
+#endif
+
+#define CONFIG_ETHADDR		DE:AD:BE:EF:01:01    /* Ethernet address */
+
+#define CONFIG_BOOTDELAY	2	/* autoboot after 2 seconds	*/
+
+#define CONFIG_BAUDRATE		115200
+
+/* valid baudrates */
+
+#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"addmisc=setenv bootargs ${bootargs} "				\
+		"console=ttyS0,${baudrate} "				\
+		"panic=1\0"						\
+	"bootfile=/tftpboot/vmlinux.srec\0"				\
+	"load=tftp 80500000 ${u-boot}\0"				\
+	""
+
+#ifdef CONFIG_DBAU1550
+/* Boot from flash by default, revert to bootp */
+#define CONFIG_BOOTCOMMAND	"bootm 0xbfc20000; bootp; bootm"
+#else /* CONFIG_DBAU1550 */
+#define CONFIG_BOOTCOMMAND	"bootp;bootm"
+#endif /* CONFIG_DBAU1550 */
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_BEDBUG
+#undef CONFIG_CMD_ELF
+#undef CONFIG_CMD_SAVEENV
+#undef CONFIG_CMD_FAT
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_MII
+#undef CONFIG_CMD_RUN
+
+
+#ifdef CONFIG_DBAU1550
+
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_NET
+
+#undef CONFIG_CMD_I2C
+#undef CONFIG_CMD_IDE
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_PCMCIA
+
+#else
+
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_DHCP
+
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+
+#endif
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_LONGHELP				/* undef to save memory      */
+
+#define	CONFIG_SYS_PROMPT		"DbAu1xx0 # "	/* Monitor Command Prompt    */
+
+#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size   */
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)  /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16		/* max number of command args*/
+
+#define CONFIG_SYS_MALLOC_LEN		128*1024
+
+#define CONFIG_SYS_BOOTPARAMS_LEN	128*1024
+
+#define CONFIG_SYS_MHZ			396
+
+#if (CONFIG_SYS_MHZ % 12) != 0
+#error "Invalid CPU frequency - must be multiple of 12!"
+#endif
+
+#define CONFIG_SYS_MIPS_TIMER_FREQ	(CONFIG_SYS_MHZ * 1000000)
+
+#define CONFIG_SYS_SDRAM_BASE		0x80000000     /* Cached addr */
+
+#define	CONFIG_SYS_LOAD_ADDR		0x81000000     /* default load address	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x80100000
+#define CONFIG_SYS_MEMTEST_END		0x80800000
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#ifdef CONFIG_DBAU1550
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	(512)	/* max number of sectors on one chip */
+
+#define PHYS_FLASH_1		0xb8000000 /* Flash Bank #1 */
+#define PHYS_FLASH_2		0xbc000000 /* Flash Bank #2 */
+
+#else /* CONFIG_DBAU1550 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	(128)	/* max number of sectors on one chip */
+
+#define PHYS_FLASH_1		0xbec00000 /* Flash Bank #1 */
+#define PHYS_FLASH_2		0xbfc00000 /* Flash Bank #2 */
+
+#endif /* CONFIG_DBAU1550 */
+
+#define CONFIG_SYS_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2}
+
+#define CONFIG_SYS_FLASH_CFI           1
+#define CONFIG_FLASH_CFI_DRIVER    1
+
+/* The following #defines are needed to get flash environment right */
+#define	CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)
+
+#define CONFIG_SYS_INIT_SP_OFFSET	0x400000
+
+/* We boot from this flash, selected with dip switch */
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_2
+
+/* timeout values are in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
+
+#define	CONFIG_ENV_IS_NOWHERE	1
+
+/* Address and size of Primary Environment Sector	*/
+#define CONFIG_ENV_ADDR		0xB0030000
+#define CONFIG_ENV_SIZE		0x10000
+
+#define CONFIG_FLASH_16BIT
+
+#define CONFIG_NR_DRAM_BANKS	2
+
+
+#ifdef CONFIG_DBAU1550
+#define MEM_SIZE 192
+#else
+#define MEM_SIZE 64
+#endif
+
+#define CONFIG_MEMSIZE_IN_BYTES
+
+#ifndef CONFIG_DBAU1550
+/*---ATA PCMCIA ------------------------------------*/
+#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
+#define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000
+#define CONFIG_PCMCIA_SLOT_A
+
+#define CONFIG_ATAPI 1
+#define CONFIG_MAC_PARTITION 1
+
+/* We run CF in "true ide" mode or a harddrive via pcmcia */
+#define CONFIG_IDE_PCMCIA 1
+
+/* We only support one slot for now */
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_BASE_ADDR       CONFIG_SYS_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_DATA_OFFSET     8
+
+/* Offset for normal register accesses  */
+#define CONFIG_SYS_ATA_REG_OFFSET      0
+
+/* Offset for alternate registers       */
+#define CONFIG_SYS_ATA_ALT_OFFSET      0x0100
+#endif /* CONFIG_DBAU1550 */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_DCACHE_SIZE		16384
+#define CONFIG_SYS_ICACHE_SIZE		16384
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/debris.h b/qemu/roms/u-boot/include/configs/debris.h
new file mode 100644
index 000000000..4631b8621
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/debris.h
@@ -0,0 +1,443 @@
+/*
+ * (C) Copyright 2001, 2002
+ * Sangmoon Kim, Etin Systems, dogoil@etinsys.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
+
+/* Environments */
+
+/* bootargs */
+#define CONFIG_BOOTARGS \
+	"console=ttyS0,9600 init=/linuxrc " \
+	"root=/dev/nfs rw nfsroot=192.168.0.1:" \
+	"/tftpboot/target " \
+	"ip=192.168.0.2:192.168.0.1:192.168.0.1:" \
+	"255.255.255.0:debris:eth0:none " \
+	"mtdparts=phys:12m(root),-(kernel)"
+
+/* bootcmd */
+#define CONFIG_BOOTCOMMAND \
+	"tftp 800000 pImage; " \
+	"setenv bootargs console=ttyS0,9600 init=/linuxrc " \
+	"root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+	"ip=${ipaddr}:${serverip}:${gatewayip}:" \
+	"${netmask}:${hostname}:eth0:none " \
+	"mtdparts=phys:12m(root),-(kernel); " \
+	"bootm 800000"
+
+/* bootdelay */
+#define CONFIG_BOOTDELAY	5	/* autoboot 5s */
+
+/* baudrate */
+#define CONFIG_BAUDRATE		9600	/* console baudrate = 9600bps	*/
+
+/* loads_echo */
+#define CONFIG_LOADS_ECHO	0	/* echo off for serial download */
+
+/* ethaddr */
+#undef CONFIG_ETHADDR
+
+/* eth2addr */
+#undef CONFIG_ETH2ADDR
+
+/* eth3addr */
+#undef CONFIG_ETH3ADDR
+
+/* ipaddr */
+#define CONFIG_IPADDR	192.168.0.2
+
+/* serverip */
+#define CONFIG_SERVERIP	192.168.0.1
+
+/* autoload */
+#undef CONFIG_SYS_AUTOLOAD
+
+/* rootpath */
+#define CONFIG_ROOTPATH "/tftpboot/target"
+
+/* gatewayip */
+#define CONFIG_GATEWAYIP 192.168.0.1
+
+/* netmask */
+#define CONFIG_NETMASK 255.255.255.0
+
+/* hostname */
+#define CONFIG_HOSTNAME debris
+
+/* bootfile */
+#define CONFIG_BOOTFILE "pImage"
+
+/* loadaddr */
+#define CONFIG_LOADADDR 800000
+
+/* preboot */
+#undef CONFIG_PREBOOT
+
+/* clocks_in_mhz */
+#undef CONFIG_CLOCKS_IN_MHZ
+
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC8245		1
+#define CONFIG_DEBRIS		1
+
+#if 0
+#define USE_DINK32		1
+#else
+#undef USE_DINK32
+#endif
+
+#define CONFIG_CONS_INDEX       1
+#define CONFIG_BAUDRATE		9600
+#define CONFIG_DRAM_SPEED	100		/* MHz */
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_KGDB
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_SDRAM
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		1		/* undef to save memory		*/
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size	*/
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address		*/
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_PCI				/* include pci support		*/
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_PNP
+
+#define CONFIG_EEPRO100
+#define CONFIG_SYS_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100  */
+#define CONFIG_EEPRO100_SROM_WRITE
+
+#define PCI_ENET0_IOADDR	0x80000000
+#define PCI_ENET0_MEMADDR	0x80000000
+#define	PCI_ENET1_IOADDR	0x81000000
+#define	PCI_ENET1_MEMADDR	0x81000000
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_MAX_RAM_SIZE	0x20000000
+#define CONFIG_VERY_BIG_RAM
+
+#define CONFIG_SYS_RESET_ADDRESS	0xFFF00100
+
+#if defined (USE_DINK32)
+#define CONFIG_SYS_MONITOR_LEN		0x00040000
+#define CONFIG_SYS_MONITOR_BASE	0x00090000
+#define CONFIG_SYS_RAMBOOT		1
+#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x10000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+#else
+#undef	CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_MONITOR_LEN		0x00040000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+
+
+#define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE      0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+#endif
+
+#define CONFIG_SYS_FLASH_BASE		0x7C000000
+#define CONFIG_SYS_FLASH_SIZE		(16*1024*1024)	/* debris has tiny eeprom	*/
+
+#define CONFIG_SYS_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END		0x04000000	/* 0 ... 32 MB in DRAM		*/
+
+#define CONFIG_SYS_EUMB_ADDR		0xFC000000
+
+#define CONFIG_SYS_FLASH_RANGE_BASE	0xFF000000	/* flash memory address range	*/
+#define CONFIG_SYS_FLASH_RANGE_SIZE	0x01000000
+#define FLASH_BASE0_PRELIM	0x7C000000	/* debris flash		*/
+
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_CMD_MTDPARTS
+#define CONFIG_JFFS2_DEV		"nor0"
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET	0x00000000
+
+/* mtdparts command line support */
+
+/* Use first bank for JFFS2, second bank contains U-Boot.
+ *
+ * Note: fake mtd_id's used, no linux mtd map file.
+ */
+/*
+#define CONFIG_CMD_MTDPARTS
+#define MTDIDS_DEFAULT		"nor0=debris-0"
+#define MTDPARTS_DEFAULT	"mtdparts=debris-0:-(jffs2)"
+*/
+
+#define CONFIG_ENV_IS_IN_NVRAM      1
+#define CONFIG_ENV_OVERWRITE     1
+#define CONFIG_SYS_NVRAM_ACCESS_ROUTINE 1
+#define CONFIG_ENV_ADDR		0xFF000000 /* right at the start of NVRAM  */
+#define CONFIG_ENV_SIZE		0x400	/* Size of the Environment - 8K	   */
+#define CONFIG_ENV_OFFSET		0	/* starting right at the beginning */
+
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xff000000
+
+/*
+ * CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_VXWORKS_OFFS =
+ * NV_RAM_ADDRS + NV_BOOT_OFFSET + NV_ENET_OFFSET
+ */
+#define CONFIG_SYS_NVRAM_VXWORKS_OFFS	0x6900
+
+/*
+ * select i2c support configuration
+ *
+ * Supported configurations are {none, software, hardware} drivers.
+ * If the software driver is chosen, there are some additional
+ * configuration items that the driver uses to drive the port pins.
+ */
+#define CONFIG_HARD_I2C		1		/* To enable I2C support	*/
+#undef  CONFIG_SYS_I2C_SOFT			/* I2C bit-banged */
+#define CONFIG_SYS_I2C_SPEED		400000		/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+
+#ifdef CONFIG_SYS_I2C_SOFT
+#error "Soft I2C is not configured properly.  Please review!"
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT_SPEED	50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0x7F
+#define I2C_PORT		3               /* Port A=0, B=1, C=2, D=3 */
+#define I2C_ACTIVE		(iop->pdir |=  0x00010000)
+#define I2C_TRISTATE		(iop->pdir &= ~0x00010000)
+#define I2C_READ		((iop->pdat & 0x00010000) != 0)
+#define I2C_SDA(bit)		if(bit) iop->pdat |=  0x00010000; \
+				else    iop->pdat &= ~0x00010000
+#define I2C_SCL(bit)		if(bit) iop->pdat |=  0x00020000; \
+				else    iop->pdat &= ~0x00020000
+#define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
+#endif /* CONFIG_SYS_I2C_SOFT */
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57		/* EEPROM IS24C02		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1		/* Bytes of address		*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+
+#define CONFIG_SYS_FLASH_BANKS		{ FLASH_BASE0_PRELIM }
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+
+#define CONFIG_SYS_NS16550_CLK		7372800
+
+#define CONFIG_SYS_NS16550_COM1	0xFF080000
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_NS16550_COM1 + 8)
+#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_NS16550_COM1 + 16)
+#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_NS16550_COM1 + 24)
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+#define CONFIG_SYS_CLK_FREQ  33333333	/* external frequency to pll */
+#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 3
+
+#define CONFIG_SYS_DLL_EXTEND		0x00
+#define CONFIG_SYS_PCI_HOLD_DEL	0x20
+
+#define CONFIG_SYS_ROMNAL	15	/* rom/flash next access time */
+#define CONFIG_SYS_ROMFAL	31	/* rom/flash access time */
+
+#define CONFIG_SYS_REFINT	430	/* # of clocks between CBR refresh cycles */
+
+#define CONFIG_SYS_DBUS_SIZE2	1	/* set for 8-bit RCS1, clear for 32,64 */
+
+/* the following are for SDRAM only*/
+#define CONFIG_SYS_BSTOPRE	121	/* Burst To Precharge, sets open page interval */
+#define CONFIG_SYS_REFREC	8	/* Refresh to activate interval		*/
+#define CONFIG_SYS_RDLAT	4	/* data latency from read command	*/
+#define CONFIG_SYS_PRETOACT	3	/* Precharge to activate interval	*/
+#define CONFIG_SYS_ACTTOPRE	5	/* Activate to Precharge interval	*/
+#define CONFIG_SYS_ACTORW		3	/* Activate to R/W			*/
+#define CONFIG_SYS_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
+#define CONFIG_SYS_SDMODE_WRAP		0	/* SDMODE wrap type			*/
+#if 0
+#define CONFIG_SYS_SDMODE_BURSTLEN	2	/* OBSOLETE!  SDMODE Burst length 2=4, 3=8		*/
+#endif
+
+#define CONFIG_SYS_REGISTERD_TYPE_BUFFER   1
+#define CONFIG_SYS_EXTROM 1
+#define CONFIG_SYS_REGDIMM 0
+
+
+/* memory bank settings*/
+/*
+ * only bits 20-29 are actually used from these vales to set the
+ * start/end address the upper two bits will be 0, and the lower 20
+ * bits will be set to 0x00000 for a start address, or 0xfffff for an
+ * end address
+ */
+#define CONFIG_SYS_BANK0_START		0x00000000
+#define CONFIG_SYS_BANK0_END		(0x4000000 - 1)
+#define CONFIG_SYS_BANK0_ENABLE	1
+#define CONFIG_SYS_BANK1_START		0x04000000
+#define CONFIG_SYS_BANK1_END		(0x8000000 - 1)
+#define CONFIG_SYS_BANK1_ENABLE	1
+#define CONFIG_SYS_BANK2_START		0x3ff00000
+#define CONFIG_SYS_BANK2_END		0x3fffffff
+#define CONFIG_SYS_BANK2_ENABLE	0
+#define CONFIG_SYS_BANK3_START		0x3ff00000
+#define CONFIG_SYS_BANK3_END		0x3fffffff
+#define CONFIG_SYS_BANK3_ENABLE	0
+#define CONFIG_SYS_BANK4_START		0x00000000
+#define CONFIG_SYS_BANK4_END		0x00000000
+#define CONFIG_SYS_BANK4_ENABLE	0
+#define CONFIG_SYS_BANK5_START		0x00000000
+#define CONFIG_SYS_BANK5_END		0x00000000
+#define CONFIG_SYS_BANK5_ENABLE	0
+#define CONFIG_SYS_BANK6_START		0x00000000
+#define CONFIG_SYS_BANK6_END		0x00000000
+#define CONFIG_SYS_BANK6_ENABLE	0
+#define CONFIG_SYS_BANK7_START		0x00000000
+#define CONFIG_SYS_BANK7_END		0x00000000
+#define CONFIG_SYS_BANK7_ENABLE	0
+/*
+ * Memory bank enable bitmask, specifying which of the banks defined above
+ are actually present. MSB is for bank #7, LSB is for bank #0.
+ */
+#define CONFIG_SYS_BANK_ENABLE		0x01
+
+#define CONFIG_SYS_ODCR		0x75	/* configures line driver impedances,	*/
+					/* see 8240 book for bit definitions	*/
+#define CONFIG_SYS_PGMAX		0x32	/* how long the 8240 retains the	*/
+					/* currently accessed page in memory	*/
+					/* see 8240 book for details		*/
+
+/* SDRAM 0 - 256MB */
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* stack in DCACHE @ 1GB (no backing mem) */
+#if defined(USE_DINK32)
+#define CONFIG_SYS_IBAT1L	(0x40000000 | BATL_PP_00 )
+#define CONFIG_SYS_IBAT1U	(0x40000000 | BATU_BL_128K )
+#else
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#endif
+
+/* PCI memory */
+#define CONFIG_SYS_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* Flash, config addrs, etc */
+#define CONFIG_SYS_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8240 CPU			*/
+#if defined(CONFIG_CMD_KGDB)
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/* values according to the manual */
+
+#define CONFIG_DRAM_50MHZ	1
+#define CONFIG_SDRAM_50MHZ
+
+#define CONFIG_DISK_SPINUP_TIME 1000000
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/devkit3250.h b/qemu/roms/u-boot/include/configs/devkit3250.h
new file mode 100644
index 000000000..bd96a7d3f
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/devkit3250.h
@@ -0,0 +1,101 @@
+/*
+ * Embest/Timll DevKit3250 board configuration file
+ *
+ * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_DEVKIT3250_H__
+#define __CONFIG_DEVKIT3250_H__
+
+/* SoC and board defines */
+#include <linux/sizes.h>
+#include <asm/arch/cpu.h>
+
+/*
+ * Define DevKit3250 machine type by hand until it lands in mach-types
+ */
+#define MACH_TYPE_DEVKIT3250		3697
+#define CONFIG_MACH_TYPE		MACH_TYPE_DEVKIT3250
+
+#define CONFIG_SYS_ICACHE_OFF
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/*
+ * Memory configurations
+ */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_MALLOC_LEN		SZ_1M
+#define CONFIG_SYS_SDRAM_BASE		EMC_DYCS0_BASE
+#define CONFIG_SYS_SDRAM_SIZE		SZ_64M
+#define CONFIG_SYS_TEXT_BASE		0x83FA0000
+#define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE + SZ_32K)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_TEXT_BASE - SZ_1M)
+
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + SZ_32K)
+
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + SZ_4K \
+					 - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * Serial Driver
+ */
+#define CONFIG_SYS_LPC32XX_UART		2   /* UART2 */
+#define CONFIG_BAUDRATE			115200
+
+/*
+ * NOR Flash
+ */
+#define CONFIG_CMD_FLASH
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	71
+#define CONFIG_SYS_FLASH_BASE		EMC_CS0_BASE
+#define CONFIG_SYS_FLASH_SIZE		SZ_4M
+#define CONFIG_SYS_FLASH_CFI
+
+/*
+ * U-Boot General Configurations
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_CBSIZE		1024
+#define CONFIG_SYS_PBSIZE		\
+	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE			SZ_128K
+
+/*
+ * U-Boot Commands
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_CACHE
+
+/*
+ * Boot Linux
+ */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define CONFIG_BOOTDELAY		3
+
+#define CONFIG_BOOTFILE			"uImage"
+#define CONFIG_BOOTARGS			"console=ttyS2,115200n8"
+#define CONFIG_LOADADDR			0x80008000
+
+/*
+ * Include SoC specific configuration
+ */
+#include <asm/arch/config.h>
+
+#endif  /* __CONFIG_DEVKIT3250_H__*/
diff --git a/qemu/roms/u-boot/include/configs/devkit8000.h b/qemu/roms/u-boot/include/configs/devkit8000.h
new file mode 100644
index 000000000..16a00ebe8
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/devkit8000.h
@@ -0,0 +1,356 @@
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * (C) Copyright 2009
+ * Frederik Kriewitz <frederik@kriewitz.eu>
+ *
+ * Configuration settings for the DevKit8000 board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_OMAP		1	/* in a TI OMAP core */
+#define CONFIG_OMAP34XX		1	/* which is a 34XX */
+#define CONFIG_OMAP3_DEVKIT8000	1	/* working with DevKit8000 */
+#define CONFIG_MACH_TYPE	MACH_TYPE_DEVKIT8000
+#define CONFIG_OMAP_GPIO
+#define CONFIG_OMAP_COMMON
+
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * other needs.
+ */
+#define CONFIG_SYS_TEXT_BASE	0x80100000
+
+#define CONFIG_SDRC	/* The chip has SDRC controller */
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/* Display CPU and Board information */
+#define CONFIG_DISPLAY_CPUINFO		1
+#define CONFIG_DISPLAY_BOARDINFO	1
+
+/* Clock Defines */
+#define V_OSCK				26000000	/* Clock output from T2 */
+#define V_SCLK				(V_OSCK >> 1)
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+#define CONFIG_REVISION_TAG		1
+
+#define CONFIG_OF_LIBFDT		1
+
+/* Size of malloc() pool */
+#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
+						/* Sector */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
+
+/* Hardware drivers */
+/* DM9000 */
+#define CONFIG_NET_RETRY_COUNT		20
+#define	CONFIG_DRIVER_DM9000		1
+#define	CONFIG_DM9000_BASE		0x2c000000
+#define	DM9000_IO			CONFIG_DM9000_BASE
+#define	DM9000_DATA			(CONFIG_DM9000_BASE + 0x400)
+#define	CONFIG_DM9000_USE_16BIT		1
+#define CONFIG_DM9000_NO_SROM		1
+#undef	CONFIG_DM9000_DEBUG
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		48000000 /* 48MHz (APLL96/2) */
+
+/* select serial console configuration */
+#define CONFIG_CONS_INDEX		3
+#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
+#define CONFIG_SERIAL3			3
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
+					115200}
+
+/* MMC */
+#define CONFIG_GENERIC_MMC		1
+#define CONFIG_MMC			1
+#define CONFIG_OMAP_HSMMC		1
+#define CONFIG_DOS_PARTITION		1
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
+#define CONFIG_SYS_I2C_OMAP34XX
+
+/* TWL4030 */
+#define CONFIG_TWL4030_POWER		1
+#define CONFIG_TWL4030_LED		1
+
+/* Board NAND Info */
+#define CONFIG_SYS_NO_FLASH		/* no NOR flash */
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define MTDIDS_DEFAULT			"nand0=nand"
+#define MTDPARTS_DEFAULT		"mtdparts=nand:" \
+						"512k(x-loader)," \
+						"1920k(u-boot)," \
+						"128k(u-boot-env)," \
+						"4m(kernel)," \
+						"-(fs)"
+
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
+							/* to access nand */
+#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
+							/* to access nand at */
+							/* CS0 */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
+							/* devices */
+#define CONFIG_JFFS2_NAND
+/* nand device jffs2 lives on */
+#define CONFIG_JFFS2_DEV		"nand0"
+/* start of jffs2 partition */
+#define CONFIG_JFFS2_PART_OFFSET	0x680000
+#define CONFIG_JFFS2_PART_SIZE		0xf980000	/* size of jffs2 */
+							/* partition */
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP			/* DHCP support			*/
+#define CONFIG_CMD_EXT2			/* EXT2 Support			*/
+#define CONFIG_CMD_FAT			/* FAT support			*/
+#define CONFIG_CMD_I2C			/* I2C serial bus support	*/
+#define CONFIG_CMD_JFFS2		/* JFFS2 Support		*/
+#define CONFIG_CMD_MMC			/* MMC support			*/
+#define CONFIG_CMD_MTDPARTS		/* Enable MTD parts commands	*/
+#define CONFIG_CMD_NAND			/* NAND support			*/
+#define CONFIG_CMD_NAND_LOCK_UNLOCK	/* nand (un)lock commands	*/
+
+#undef CONFIG_CMD_FPGA			/* FPGA configuration Support	*/
+#undef CONFIG_CMD_IMI			/* iminfo			*/
+
+/* BOOTP/DHCP options */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_NISDOMAIN
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_NTPSERVER
+#define CONFIG_BOOTP_TIMEOFFSET
+#undef CONFIG_BOOTP_VENDOREX
+
+/* Environment information */
+#define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */
+
+#define CONFIG_BOOTDELAY		3
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x82000000\0" \
+	"console=ttyO2,115200n8\0" \
+	"mmcdev=0\0" \
+	"vram=12M\0" \
+	"dvimode=1024x768MR-16@60\0" \
+	"defaultdisplay=dvi\0" \
+	"nfsopts=hard,tcp,rsize=65536,wsize=65536\0" \
+	"kernelopts=rw\0" \
+	"commonargs=" \
+		"setenv bootargs console=${console} " \
+		"vram=${vram} " \
+		"omapfb.mode=dvi:${dvimode} " \
+		"omapdss.def_disp=${defaultdisplay}\0" \
+	"mmcargs=" \
+		"run commonargs; " \
+		"setenv bootargs ${bootargs} " \
+		"root=/dev/mmcblk0p2 " \
+		"rootwait " \
+		"${kernelopts}\0" \
+	"nandargs=" \
+		"run commonargs; " \
+		"setenv bootargs ${bootargs} " \
+		"omapfb.mode=dvi:${dvimode} " \
+		"omapdss.def_disp=${defaultdisplay} " \
+		"root=/dev/mtdblock4 " \
+		"rootfstype=jffs2 " \
+		"${kernelopts}\0" \
+	"netargs=" \
+		"run commonargs; " \
+		"setenv bootargs ${bootargs} " \
+		"root=/dev/nfs " \
+		"nfsroot=${serverip}:${rootpath},${nfsopts} " \
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \
+		"${kernelopts} " \
+		"dnsip1=${dnsip} " \
+		"dnsip2=${dnsip2}\0" \
+	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source ${loadaddr}\0" \
+	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+	"eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nand read ${loadaddr} 280000 400000; " \
+		"bootm ${loadaddr}\0" \
+	"netboot=echo Booting from network ...; " \
+		"dhcp ${loadaddr}; " \
+		"run netargs; " \
+		"bootm ${loadaddr}\0" \
+	"autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
+			"if run loadbootscript; then " \
+				"run bootscript; " \
+			"else " \
+				"if run loaduimage; then " \
+					"run mmcboot; " \
+				"else run nandboot; " \
+				"fi; " \
+			"fi; " \
+		"else run nandboot; fi\0"
+
+
+#define CONFIG_BOOTCOMMAND "run autoboot"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_AUTO_COMPLETE		1
+#define CONFIG_SYS_PROMPT		"OMAP3 DevKit8000 # "
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		128	/* max number of command args */
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
+
+#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0 + 0x07000000)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
+					0x01000000) /* 16MB */
+
+#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0 + 0x02000000)
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
+#define CONFIG_SYS_PTV			2 /* Divisor: 2^(PTV+1) => 8 */
+
+/*  Physical Memory Map  */
+#define CONFIG_NR_DRAM_BANKS		2 /* CS1 may or may not be populated */
+#define PHYS_SDRAM_1			OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_2			OMAP34XX_SDRC_CS1
+
+/* NAND and environment organization  */
+#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
+
+#define CONFIG_ENV_IS_IN_NAND		1
+#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
+
+#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
+
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR        0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE        0x800
+#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR + \
+							 CONFIG_SYS_INIT_RAM_SIZE - \
+							 GENERATED_GBL_DATA_SIZE)
+
+/* SRAM config */
+#define CONFIG_SYS_SRAM_START              0x40200000
+#define CONFIG_SYS_SRAM_SIZE               0x10000
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_NAND_SIMPLE
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME        "u-boot.img"
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION    1
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
+
+#define CONFIG_SPL_TEXT_BASE		0x40200000 /*CONFIG_SYS_SRAM_START*/
+#define CONFIG_SPL_MAX_SIZE		(54 * 1024)	/* 8 KB for stack */
+#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
+
+#define CONFIG_SPL_BSS_START_ADDR       0x80000500 /* leave space for bootargs*/
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
+
+/* NAND boot config */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
+#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9,\
+						10, 11, 12, 13}
+
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW
+
+#define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x200000
+
+#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000	/* 1 MB */
+
+/* SPL OS boot options */
+#define CONFIG_SPL_OS_BOOT
+
+#define CONFIG_CMD_SPL
+#define CONFIG_CMD_SPL_WRITE_SIZE       0x400 /* 1024 byte */
+#define CONFIG_CMD_SPL_NAND_OFS (CONFIG_SYS_NAND_SPL_KERNEL_OFFS+\
+					0x400000)
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
+
+#define CONFIG_SPL_FAT_LOAD_KERNEL_NAME		"uImage"
+#define CONFIG_SPL_FAT_LOAD_ARGS_NAME		"args"
+
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0x500 /* address 0xa0000 */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0x8   /* address 0x1000 */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	8     /* 4KB */
+
+#define CONFIG_SYS_SPL_ARGS_ADDR        (PHYS_SDRAM_1 + 0x100)
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/dig297.h b/qemu/roms/u-boot/include/configs/dig297.h
new file mode 100644
index 000000000..af6f56bb3
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/dig297.h
@@ -0,0 +1,278 @@
+/*
+ * (C) Copyright 2011 Comelit Group SpA
+ * Luca Ceresoli <luca.ceresoli@comelit.it>
+ *
+ * Based on omap3_beagle.h:
+ * (C) Copyright 2006-2008
+ * Texas Instruments.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * Configuration settings for the Comelit DIG297 board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/mach-types.h>
+#ifdef MACH_TYPE_OMAP3_CPS
+#error "MACH_TYPE_OMAP3_CPS has been defined properly, please remove this."
+#else
+#define MACH_TYPE_OMAP3_CPS 2751
+#endif
+#define CONFIG_MACH_TYPE MACH_TYPE_OMAP3_CPS
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_OMAP		/* in a TI OMAP core */
+#define CONFIG_OMAP34XX		/* which is a 34XX */
+#define CONFIG_OMAP_GPIO
+#define CONFIG_OMAP_COMMON
+
+#define CONFIG_SYS_TEXT_BASE	0x80008000
+
+#define CONFIG_SDRC	/* The chip has SDRC controller */
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Clock Defines */
+#define V_OSCK			26000000	/* Clock output from T2 */
+#define V_SCLK			(V_OSCK >> 1)
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
+						/* Sector */
+#define CONFIG_SYS_MALLOC_LEN		(1024 << 10) /* UBI needs >= 512 kB */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+
+/*
+ * select serial console configuration: UART3 (ttyO2)
+ */
+#define CONFIG_CONS_INDEX		3
+#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
+#define CONFIG_SERIAL3			3
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
+					115200}
+#define CONFIG_GENERIC_MMC		1
+#define CONFIG_MMC			1
+#define CONFIG_OMAP_HSMMC		1
+#define CONFIG_DOS_PARTITION
+
+/* library portions to compile in */
+#define CONFIG_RBTREE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_LZO
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_FAT		/* FAT support			*/
+#define CONFIG_CMD_UBI		/* UBI Support			*/
+#define CONFIG_CMD_UBIFS	/* UBIFS Support		*/
+#define CONFIG_CMD_MTDPARTS	/* Enable MTD parts commands    */
+#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
+#define MTDIDS_DEFAULT		"nand0=omap2-nand.0"
+#define MTDPARTS_DEFAULT	"mtdparts=omap2-nand.0:896k(uboot),"\
+				"128k(uboot-env),3m(kernel),252m(ubi)"
+
+#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
+#define CONFIG_CMD_MMC		/* MMC support			*/
+#define CONFIG_CMD_NAND		/* NAND support			*/
+
+#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
+#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
+#undef CONFIG_CMD_IMI		/* iminfo			*/
+#undef CONFIG_CMD_IMLS		/* List all found images	*/
+#define CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot	*/
+#undef CONFIG_CMD_NFS		/* NFS support			*/
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
+#define CONFIG_SYS_I2C_OMAP34XX
+
+/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER
+#define CONFIG_TWL4030_LED
+
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
+							/* to access nand */
+#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
+							/* to access nand at */
+							/* CS0 */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
+
+#if defined(CONFIG_CMD_NET)
+/*
+ * SMSC9220 Ethernet
+ */
+
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_32_BIT
+#define CONFIG_SMC911X_BASE     0x2C000000
+
+#endif /* (CONFIG_CMD_NET) */
+
+/* Environment information */
+#define CONFIG_BOOTDELAY		1
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x82000000\0" \
+	"console=ttyO2,115200n8\0" \
+	"mtdids=" MTDIDS_DEFAULT "\0" \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"partition=nand0,3\0"\
+	"mmcroot=/dev/mmcblk0p2 rw\0" \
+	"mmcrootfstype=ext3 rootwait\0" \
+	"nandroot=ubi0:rootfs ro\0" \
+	"nandrootfstype=ubifs\0" \
+	"nfspath=/srv/nfs\0" \
+	"tftpfilename=uImage\0" \
+	"gatewayip=0.0.0.0\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"${mtdparts} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype} " \
+		"ip=${ipaddr}:${serverip}:${gatewayip}:" \
+			"${netmask}:${hostname}::off\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"${mtdparts} " \
+		"ubi.mtd=3 " \
+		"root=${nandroot} " \
+		"rootfstype=${nandrootfstype} " \
+		"ip=${ipaddr}:${serverip}:${gatewayip}:" \
+			"${netmask}:${hostname}::off\0" \
+	"netargs=setenv bootargs console=${console} " \
+		"${mtdparts} " \
+		"root=/dev/nfs rw " \
+		"nfsroot=${serverip}:${nfspath} " \
+		"ip=${ipaddr}:${serverip}:${gatewayip}:" \
+			"${netmask}:${hostname}::off\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nand read ${loadaddr} 100000 300000; " \
+		"bootm ${loadaddr}\0" \
+	"netboot=echo Booting from network ...; " \
+		"run netargs; " \
+		"tftp ${loadaddr} ${serverip}:${tftpfilename}; " \
+		"bootm ${loadaddr}\0" \
+	"resetenv=nand erase e0000 20000\0"\
+
+#define CONFIG_BOOTCOMMAND \
+	"run nandboot"
+
+#define CONFIG_AUTO_COMPLETE
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT		"DIG297# "
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
+
+#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)	/* memtest */
+								/* works on */
+#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
+					0x01F00000) /* 31MB */
+
+#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)	/* default */
+							/* load address */
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
+#define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
+#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+
+/* Configure the PISMO */
+#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
+
+#define CONFIG_SYS_FLASH_BASE		boot_flash_base
+
+/* Monitor at start of flash */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_ENV_IS_IN_NAND
+#define SMNAND_ENV_OFFSET		0x0E0000 /* environment starts here */
+
+#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
+#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
+#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE	0x800
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/digsy_mtc.h b/qemu/roms/u-boot/include/configs/digsy_mtc.h
new file mode 100644
index 000000000..2a8cb3940
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/digsy_mtc.h
@@ -0,0 +1,490 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2005-2007
+ * Modified for InterControl digsyMTC MPC5200 board by
+ * Frank Bodammer, GCD Hard- & Software GmbH,
+ *                 frank.bodammer@gcd-solutions.de
+ *
+ * (C) Copyright 2009 Semihalf
+ * Optimized for digsyMTC by: Grzegorz Bernacki <gjb@semihalf.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+
+#define CONFIG_MPC5200		1	/* This is an MPC5200 CPU */
+#define CONFIG_DIGSY_MTC	1	/* ... on InterControl digsyMTC board */
+
+/*
+ * Valid values for CONFIG_SYS_TEXT_BASE are:
+ * 0xFFF00000	boot high (standard configuration)
+ * 0xFE000000	boot low
+ * 0x00100000	boot from RAM (for testing only)
+ */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xFFF00000	/* Standard: boot high */
+#endif
+
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000
+
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	4	/* console is on PSC4  */
+#define CONFIG_BAUDRATE		115200	/* ... at 115200  bps  */
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*
+ * PCI Mapping:
+ * 0x40000000 - 0x4fffffff - PCI Memory
+ * 0x50000000 - 0x50ffffff - PCI IO Space
+ */
+#define CONFIG_PCI		1
+#define CONFIG_PCI_PNP		1
+#define CONFIG_PCI_SCAN_SHOW	1
+#define CONFIG_PCI_BOOTDELAY	250
+
+#define CONFIG_PCI_MEM_BUS	0x40000000
+#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE	0x10000000
+
+#define CONFIG_PCI_IO_BUS	0x50000000
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0x01000000
+
+/*
+ *  Partitions
+ */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_BZIP2
+
+/*
+ * Video
+ */
+#define CONFIG_VIDEO
+
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO_MB862xx
+#define CONFIG_VIDEO_MB862xx_ACCEL
+#define CONFIG_VIDEO_CORALP
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(2 << 20)	/* decompressed img */
+
+/* Coral-PA clock frequency, geo and other both 133MHz */
+#define CONFIG_SYS_MB862xx_CCF	0x00050000
+/* Video SDRAM parameters */
+#define CONFIG_SYS_MB862xx_MMR	0x11d7fa72
+#endif
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#ifdef CONFIG_VIDEO
+#define CONFIG_CMD_BMP
+#endif
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_USB
+
+#if (CONFIG_SYS_TEXT_BASE == 0xFF000000)
+#define CONFIG_SYS_LOWBOOT	1
+#endif
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	1
+
+#undef	CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"fw_image=digsyMPC.img\0"					\
+	"mtcb_start=mtc led diag orange; run mtcb_1\0"			\
+	"mtcb_clearled=for x in user1 user2 usbpwr usbbusy; "		\
+		"do mtc led $x; done\0"					\
+	"mtcb_1=if mtc key; then run mtcb_clearled mtcb_update; "	\
+		"else run mtcb_fw; fi\0"				\
+	"mtcb_fw=if bootm ff000000; then echo FIRMWARE OK!; "		\
+		"else echo BAD FIRMWARE CRC!; mtc led diag red; fi\0"	\
+	"mtcb_update=mtc led user1 orange;"				\
+		"while mtc key; do ; done; run mtcb_2;\0"		\
+	"mtcb_2=mtc led user1 green 2; usb reset; run mtcb_usb1;\0"	\
+	"mtcb_usb1=if fatload usb 0 400000 script.img; "		\
+		"then run mtcb_doscript; else run mtcb_usb2; fi\0"	\
+	"mtcb_usb2=if fatload usb 0 400000 $fw_image; "			\
+		"then run mtcb_dousb; else run mtcb_ide; fi\0"		\
+	"mtcb_doscript=run mtcb_usbleds; mtc led user2 orange 2; "	\
+		"run mtcb_wait_flickr mtcb_ds_1;\0"			\
+	"mtcb_ds_1=if imi 400000; then mtc led usbbusy; "		\
+		"source 400000; else run mtcb_error; fi\0"		\
+	"mtcb_dousb=run mtcb_usbleds mtcb_wait_flickr mtcb_du_1;\0"	\
+	"mtcb_du_1=if imi 400000; then run mtcb_du_2; "			\
+		"else run mtcb_error; fi\0"				\
+	"mtcb_du_2=run mtcb_clear mtcb_prog; mtc led usbbusy; "		\
+		"run mtcb_checkfw\0"					\
+	"mtcb_checkfw=if imi ff000000; then run mtcb_success; "		\
+		"else run mtcb_error; fi\0"				\
+	"mtcb_waitkey=mtc key; until test $? -eq 0; do mtc key; done\0"	\
+	"mtcb_wait_flickr=run mtcb_waitkey mtcb_uledflckr\0"		\
+	"mtcb_usbleds=mtc led usbpwr green; mtc led usbbusy orange 1;\0"\
+	"mtcb_uledflckr=mtc led user1 orange 11\0"			\
+	"mtcb_error=mtc led user1 red\0"				\
+	"mtcb_clear=erase ff000000 ff0fffff\0"				\
+	"mtcb_prog=cp.b 400000 ff000000 ${filesize}\0"			\
+	"mtcb_success=mtc led user1 green\0"				\
+	"mtcb_ide=if fatload ide 0 400000 $fw_image;"			\
+		"then run mtcb_doide; else run mtcb_error; fi\0"	\
+	"mtcb_doide=mtc led user2 green 1;"				\
+		"run mtcb_wait_flickr mtcb_di_1;\0"			\
+	"mtcb_di_1=if imi 400000; then run mtcb_di_2;"			\
+		"else run mtcb_error; fi\0"				\
+	"mtcb_di_2=run mtcb_clear; run mtcb_prog mtcb_checkfw\0"	\
+	"ramdisk_num_sector=16\0"					\
+	"flash_base=ff000000\0"						\
+	"flashdisk_size=e00000\0"					\
+	"env_sector=fff60000\0"						\
+	"flashdisk_start=ff100000\0"					\
+	"load_cmd=tftp 400000 digsyMPC.img\0"				\
+	"clear_cmd=erase ff000000 ff0fffff\0"				\
+	"flash_cmd=cp.b 400000 ff000000 ${filesize}\0"			\
+	"update_cmd=run load_cmd; "					\
+	"iminfo 400000; "						\
+	"run clear_cmd flash_cmd; "					\
+	"iminfo ff000000\0"						\
+	"spi_driver=yes\0"						\
+	"spi_watchdog=no\0"						\
+	"ftps_start=yes\0"						\
+	"ftps_user1=admin\0"						\
+	"ftps_pass1=admin\0"						\
+	"ftps_base1=/\0"						\
+	"ftps_home1=/\0"						\
+	"plc_sio_srv=no\0"						\
+	"plc_sio_baud=57600\0"						\
+	"plc_sio_parity=no\0"						\
+	"plc_sio_stop=1\0"						\
+	"plc_sio_com=2\0"						\
+	"plc_eth_srv=yes\0"						\
+	"plc_eth_port=1200\0"						\
+	"plc_root=/ide/\0"						\
+	"diag_level=0\0"						\
+	"webvisu=no\0"							\
+	"plc_can1_routing=no\0"						\
+	"plc_can1_baudrate=250\0"					\
+	"plc_can2_routing=no\0"						\
+	"plc_can2_baudrate=250\0"					\
+	"plc_can3_routing=no\0"						\
+	"plc_can3_baudrate=250\0"					\
+	"plc_can4_routing=no\0"						\
+	"plc_can4_baudrate=250\0"					\
+	"netdev=eth0\0"							\
+	"console=ttyPSC0\0"						\
+	"kernel_addr_r=400000\0"					\
+	"fdt_addr_r=600000\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+	"nfsroot=${serverip}:${rootpath}\0"				\
+	"addip=setenv bootargs ${bootargs} "				\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:"			\
+	"${netmask}:${hostname}:${netdev}:off panic=1\0"		\
+	"addcons=setenv bootargs ${bootargs} console=${console},${baudrate}\0"\
+	"rootpath=/opt/eldk/ppc_6xx\0"					\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
+		"tftp ${fdt_addr_r} ${fdt_file};"			\
+		"run nfsargs addip addcons;"				\
+		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
+	"load=tftp 200000 ${u-boot}\0"					\
+	"update=protect off FFF00000 +${filesize};"			\
+		"erase FFF00000 +${filesize};"				\
+		"cp.b 200000 FFF00000 ${filesize};"			\
+		"protect on FFF00000 +${filesize}\0"			\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run mtcb_start"
+
+/*
+ * SPI configuration
+ */
+#define CONFIG_HARD_SPI		1
+#define CONFIG_MPC52XX_SPI	1
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1
+#define CONFIG_SYS_I2C_MODULE	1
+#define CONFIG_SYS_I2C_SPEED	100000
+#define CONFIG_SYS_I2C_SLAVE	0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 	1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	70
+
+/*
+ * RTC configuration
+ */
+#if defined(CONFIG_DIGSY_REV5)
+#define CONFIG_SYS_I2C_RTC_ADDR	0x56
+#define CONFIG_RTC_RV3029
+/* Enable 5k Ohm trickle charge resistor */
+#define CONFIG_SYS_RV3029_TCR	0x20
+#else
+#define CONFIG_RTC_DS1337
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68
+#define CONFIG_SYS_DS1339_TCR_VAL	0xAB	/* diode + 4k resistor */
+#endif
+
+/*
+ * Flash configuration
+ */
+#define	CONFIG_SYS_FLASH_CFI		1
+#define	CONFIG_FLASH_CFI_DRIVER	1
+
+#if defined(CONFIG_DIGSY_REV5)
+#define CONFIG_SYS_FLASH_BASE		0xFE000000
+#define CONFIG_SYS_FLASH_BASE_CS1	0xFC000000
+#define CONFIG_SYS_MAX_FLASH_BANKS	2
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE, \
+					CONFIG_SYS_FLASH_BASE_CS1}
+#define CONFIG_SYS_UPDATE_FLASH_SIZE
+#define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
+#else
+#define CONFIG_SYS_FLASH_BASE		0xFF000000
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#endif
+
+#define CONFIG_SYS_MAX_FLASH_SECT	256
+#define CONFIG_FLASH_16BIT
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_SIZE	0x01000000
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500
+
+#define CONFIG_OF_LIBFDT  1
+#define CONFIG_OF_BOARD_SETUP	1
+
+#define OF_CPU			"PowerPC,5200@0"
+#define OF_SOC			"soc5200@f0000000"
+#define OF_TBCLK		(bd->bi_busfreq / 4)
+
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_MISC_INIT_R
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#if defined(CONFIG_LOWBOOT)
+#define CONFIG_ENV_ADDR		0xFF060000
+#else	/* CONFIG_LOWBOOT */
+#define CONFIG_ENV_ADDR		0xFFF60000
+#endif	/* CONFIG_LOWBOOT */
+#define CONFIG_ENV_SIZE		0x10000
+#define CONFIG_ENV_SECT_SIZE	0x20000
+#define CONFIG_ENV_OVERWRITE	1
+
+/*
+ * Memory map
+ */
+#define CONFIG_SYS_MBAR		0xF0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#if !defined(CONFIG_SYS_LOWBOOT)
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
+#else
+#define CONFIG_SYS_DEFAULT_MBAR	0xF0000000
+#endif
+
+/*
+ *  Use SRAM until RAM will be available
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_SIZE		MPC5XXX_SRAM_SIZE
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT		1
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN	(256 << 10)
+#define CONFIG_SYS_MALLOC_LEN	(4096 << 10)
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC	1
+#define CONFIG_MPC5xxx_FEC_MII100
+#if defined(CONFIG_DIGSY_REV5)
+#define CONFIG_PHY_ADDR		0x01
+#else
+#define CONFIG_PHY_ADDR		0x00
+#endif
+#define CONFIG_PHY_RESET_DELAY	1000
+
+#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
+
+/*
+ * GPIO configuration
+ * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1)
+ *  Bit 0   (mask 0x80000000) : 0x1
+ * SPI on Tmr2/3/4/5 pins
+ *  Bit 2:3 (mask 0x30000000) : 0x2
+ * ATA cs0/1 on csb_4/5
+ *  Bit 6:7 (mask 0x03000000) : 0x2
+ * Ethernet 100Mbit with MD
+ *  Bits 12:15 (mask 0x000f0000): 0x5
+ * USB - Two UARTs
+ *  Bits 18:19 (mask 0x00003000) : 0x2
+ * PSC3 - USB2 on PSC3
+ *  Bits 20:23 (mask 0x00000f00) : 0x1
+ * PSC2 - CAN1&2 on PSC2 pins
+ *  Bits 25:27 (mask 0x00000070) : 0x1
+ * PSC1 - AC97 functionality
+ *  Bits 29:31 (mask 0x00000007) : 0x2
+ */
+#define CONFIG_SYS_GPS_PORT_CONFIG	0xA2552112
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_AUTO_COMPLETE	1
+#define CONFIG_CMDLINE_EDITING	1
+#define CONFIG_SYS_HUSH_PARSER
+
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n", bootdelay
+#define CONFIG_AUTOBOOT_DELAY_STR	" "
+
+#define CONFIG_LOOPW		1
+#define CONFIG_MX_CYCLIC	1
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#define CONFIG_SYS_CBSIZE		1024
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS		32
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_SYS_MEMTEST_SCRATCH	0x00001000
+#define CONFIG_SYS_MEMTEST_START	0x00010000
+#define CONFIG_SYS_MEMTEST_END		0x019fffff
+
+#define CONFIG_SYS_LOAD_ADDR		0x00100000
+
+/*
+ * Various low-level settings
+ */
+#define CONFIG_SYS_SDRAM_CS1		1
+#define CONFIG_SYS_XLB_PIPELINING	1
+
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
+
+#if defined(CONFIG_SYS_LOWBOOT)
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_CFG		0x0002DD00
+#endif
+
+#define CONFIG_SYS_CS4_START		0x60000000
+#define CONFIG_SYS_CS4_SIZE		0x1000
+#define CONFIG_SYS_CS4_CFG		0x0008FC00
+
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_CS0_CFG		0x0002DD00
+
+#if defined(CONFIG_DIGSY_REV5)
+#define CONFIG_SYS_CS1_START		CONFIG_SYS_FLASH_BASE_CS1
+#define CONFIG_SYS_CS1_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_CS1_CFG		0x0002DD00
+#endif
+
+#define CONFIG_SYS_CS_BURST		0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE	0x11111111
+
+#if !defined(CONFIG_SYS_LOWBOOT)
+#define CONFIG_SYS_RESET_ADDRESS	0xfff00100
+#else
+#define CONFIG_SYS_RESET_ADDRESS	0xff000100
+#endif
+
+/*
+ * USB
+ */
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_OHCI_BE_CONTROLLER
+#define CONFIG_USB_STORAGE
+
+#define CONFIG_USB_CLOCK	0x00013333
+#define CONFIG_USB_CONFIG	0x00002000
+
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
+#define CONFIG_SYS_USB_OHCI_REGS_BASE	MPC5XXX_USB
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"mpc5200"
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+
+/*
+ * IDE/ATA
+ */
+#define CONFIG_IDE_RESET
+#define CONFIG_IDE_PREINIT
+
+#define CONFIG_SYS_ATA_CS_ON_I2C2
+#define CONFIG_SYS_IDE_MAXBUS		1
+#define CONFIG_SYS_IDE_MAXDEVICE	1
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
+#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)
+#define CONFIG_SYS_ATA_STRIDE		4
+
+#define CONFIG_ATAPI		1
+#define CONFIG_LBA48		1
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/dkb.h b/qemu/roms/u-boot/include/configs/dkb.h
new file mode 100644
index 000000000..7ffbb14e3
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/dkb.h
@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_DKB_H
+#define __CONFIG_DKB_H
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING	"\nMarvell-TTC DKB"
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_SHEEVA_88SV331xV5	1	/* CPU Core subversion */
+#define CONFIG_PANTHEON			1	/* SOC Family Name */
+#define CONFIG_MACH_TTC_DKB		1	/* Machine type */
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE - 0x00200000)
+#define CONFIG_NR_DRAM_BANKS_MAX	2
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MMC
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+#undef CONFIG_ARCH_MISC_INIT
+
+/*
+ * Environment variables configurations
+ */
+#define CONFIG_ENV_IS_NOWHERE	1	/* if env in SDRAM */
+#define CONFIG_ENV_SIZE	0x20000	/* 64k */
+
+#endif	/* __CONFIG_DKB_H */
diff --git a/qemu/roms/u-boot/include/configs/dlvision-10g.h b/qemu/roms/u-boot/include/configs/dlvision-10g.h
new file mode 100644
index 000000000..78778970f
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/dlvision-10g.h
@@ -0,0 +1,314 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_405EP		1	/* this is a PPC405 CPU */
+#define CONFIG_DLVISION_10G	1	/*  on a DLVision-10G board */
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
+
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME		dlvsion-10g
+#define CONFIG_IDENT_STRING	" dlvision-10g 0.05"
+#include "amcc-common.h"
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_MISC_INIT_R
+#define CONFIG_LAST_STAGE_INIT
+
+#define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll   */
+
+#undef CONFIG_ZERO_BOOTDELAY_CHECK     /* ignore keypress on bootdelay==0 */
+#define CONFIG_AUTOBOOT_KEYED          /* use key strings to stop autoboot */
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
+/*
+ * Configure PLL
+ */
+#define PLLMR0_DEFAULT PLLMR0_266_133_66
+#define PLLMR1_DEFAULT PLLMR1_266_133_66
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
+
+#define CONFIG_ENV_IS_IN_FLASH	/* use FLASH for environment vars */
+
+/*
+ * Default environment variables
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_AMCC_DEF_ENV						\
+	CONFIG_AMCC_DEF_ENV_POWERPC					\
+	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
+	"kernel_addr=fc000000\0"					\
+	"fdt_addr=fc1e0000\0"						\
+	"ramdisk_addr=fc200000\0"					\
+	""
+
+#define CONFIG_PHY_ADDR		4	/* PHY address			*/
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_PHY1_ADDR	0xc	/* EMAC1 PHY address		*/
+#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ
+
+/*
+ * Commands additional to the ones defined in amcc-common.h
+ */
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DTT
+#undef CONFIG_CMD_EEPROM
+
+/*
+ * SDRAM configuration (please see cpu/ppc/sdram.[ch])
+ */
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0 */
+
+/* SDRAM timings used in datasheet */
+#define CONFIG_SYS_SDRAM_CL             3	/* CAS latency */
+#define CONFIG_SYS_SDRAM_tRP           20	/* PRECHARGE command period */
+#define CONFIG_SYS_SDRAM_tRC           66	/* ACTIVE-to-ACTIVE period */
+#define CONFIG_SYS_SDRAM_tRCD          20	/* ACTIVE-to-READ delay */
+#define CONFIG_SYS_SDRAM_tRFC          66	/* Auto refresh period */
+
+/*
+ * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
+ * The Linux BASE_BAUD define should match this configuration.
+ *    baseBaud = cpuClock/(uartDivisor*16)
+ * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * set Linux BASE_BAUD to 403200.
+ */
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#undef  CONFIG_SYS_EXT_SERIAL_CLOCK	/* external serial clock */
+#undef  CONFIG_SYS_405_UART_ERRATA_59	/* 405GP/CR Rev. D silicon */
+#define CONFIG_SYS_BASE_BAUD		691200
+
+/*
+ * I2C stuff
+ */
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		100000
+
+/* Temp sensor/hwmon/dtt */
+#define CONFIG_DTT_LM63		1	/* National LM63	*/
+#define CONFIG_DTT_SENSORS	{ 0x4c, 0x4e, 0x18 } /* Sensor addresses */
+#define CONFIG_DTT_PWM_LOOKUPTABLE	\
+		{ { 46, 10 }, { 48, 14 }, { 50, 19 }, { 52, 23 },\
+		  { 54, 27 }, { 56, 31 }, { 58, 36 }, { 60, 40 } }
+#define CONFIG_DTT_TACH_LIMIT	0xa10
+
+/* EBC peripherals */
+
+#define CONFIG_SYS_FLASH_BASE		0xFC000000
+#define CONFIG_SYS_FPGA0_BASE		0x7f100000
+#define CONFIG_SYS_FPGA1_BASE		0x7f200000
+#define CONFIG_SYS_LATCH_BASE		0x7f300000
+
+#define CONFIG_SYS_FPGA_BASE(k) \
+	(k ? CONFIG_SYS_FPGA1_BASE : CONFIG_SYS_FPGA0_BASE)
+
+#define CONFIG_SYS_FPGA_DONE(k) \
+	(k ? 0x2000 : 0x1000)
+
+#define CONFIG_SYS_FPGA_COUNT		2
+
+#define CONFIG_SYS_FPGA_PTR { \
+	(struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, \
+	(struct ihs_fpga *)CONFIG_SYS_FPGA1_BASE }
+
+#define CONFIG_SYS_FPGA_COMMON
+
+#define CONFIG_SYS_LATCH0_RESET		0xffff
+#define CONFIG_SYS_LATCH0_BOOT		0xffff
+#define CONFIG_SYS_LATCH1_RESET		0xffbf
+#define CONFIG_SYS_LATCH1_BOOT		0xffff
+
+#define CONFIG_SYS_FPGA_NO_RFL_HI
+
+/*
+ * FLASH organization
+ */
+#define CONFIG_SYS_FLASH_CFI		/* The flash is CFI compatible	*/
+#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
+
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sectors per chip*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase/ms */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write/ms */
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buff'd writes */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO	/* 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* no warn upon unknown flash */
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector */
+#define CONFIG_ENV_ADDR		((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
+#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+#endif
+
+/*
+ * PPC405 GPIO Configuration
+ */
+#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO	Alternate1	*/ \
+{ \
+/* GPIO Core 0 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO0	PerBLast */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO1	TS1E */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO2	TS2E */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO3	TS1O */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO4	TS2O */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1      }, /* GPIO5	TS3 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO6	TS4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1      }, /* GPIO7	TS5 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO8	TS6 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO9	TrcClk */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10	PerCS1 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11	PerCS2 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12	PerCS3 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO13	PerCS4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14	PerAddr03 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15	PerAddr04 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16	PerAddr05 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17	IRQ0 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18	IRQ1 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19	IRQ2 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO20	IRQ3 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO21	IRQ4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO22	IRQ5 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO23	IRQ6 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24	UART0_DCD */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25	UART0_DSR */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26	UART0_RI */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27	UART0_DTR */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28	UART1_Rx */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29	UART1_Tx */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO30	RejectPkt0 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO31	RejectPkt1 */ \
+} \
+}
+
+/*
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory (OCM) for temperary stack until sdram is tested */
+#define CONFIG_SYS_TEMP_STACK_OCM	1
+
+/* On Chip Memory location */
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
+#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+	(CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (NOR-flash) */
+#define CONFIG_SYS_EBC_PB0AP	(EBC_BXAP_BME_ENABLED		|	\
+				 EBC_BXAP_FWT_ENCODE(8)		|	\
+				 EBC_BXAP_BWT_ENCODE(7)		|	\
+				 EBC_BXAP_BCE_DISABLE		|	\
+				 EBC_BXAP_BCT_2TRANS		|	\
+				 EBC_BXAP_CSN_ENCODE(0)		|	\
+				 EBC_BXAP_OEN_ENCODE(2)		|	\
+				 EBC_BXAP_WBN_ENCODE(2)		|	\
+				 EBC_BXAP_WBF_ENCODE(2)		|	\
+				 EBC_BXAP_TH_ENCODE(4)		|	\
+				 EBC_BXAP_RE_DISABLED		|	\
+				 EBC_BXAP_SOR_NONDELAYED	|	\
+				 EBC_BXAP_BEM_WRITEONLY		|	\
+				 EBC_BXAP_PEN_DISABLED)
+#define CONFIG_SYS_EBC_PB0CR	(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
+				 EBC_BXCR_BS_64MB		|	\
+				 EBC_BXCR_BU_RW			|	\
+				 EBC_BXCR_BW_16BIT)
+
+/* Memory Bank 1 (FPGA0) */
+#define CONFIG_SYS_EBC_PB1AP	(EBC_BXAP_BME_DISABLED		|	\
+				 EBC_BXAP_TWT_ENCODE(5)		|	\
+				 EBC_BXAP_BCE_DISABLE		|	\
+				 EBC_BXAP_BCT_2TRANS		|	\
+				 EBC_BXAP_CSN_ENCODE(0)		|	\
+				 EBC_BXAP_OEN_ENCODE(2)		|	\
+				 EBC_BXAP_WBN_ENCODE(1)		|	\
+				 EBC_BXAP_WBF_ENCODE(1)		|	\
+				 EBC_BXAP_TH_ENCODE(0)		|	\
+				 EBC_BXAP_RE_DISABLED		|	\
+				 EBC_BXAP_SOR_NONDELAYED	|	\
+				 EBC_BXAP_BEM_WRITEONLY		|	\
+				 EBC_BXAP_PEN_DISABLED)
+#define CONFIG_SYS_EBC_PB1CR	(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA0_BASE) | \
+				 EBC_BXCR_BS_1MB		|	\
+				 EBC_BXCR_BU_RW			|	\
+				 EBC_BXCR_BW_16BIT)
+
+/* Memory Bank 2 (FPGA1) */
+#define CONFIG_SYS_EBC_PB2AP	(EBC_BXAP_BME_DISABLED		|	\
+				 EBC_BXAP_TWT_ENCODE(6)		|	\
+				 EBC_BXAP_BCE_DISABLE		|	\
+				 EBC_BXAP_BCT_2TRANS		|	\
+				 EBC_BXAP_CSN_ENCODE(0)		|	\
+				 EBC_BXAP_OEN_ENCODE(2)		|	\
+				 EBC_BXAP_WBN_ENCODE(1)		|	\
+				 EBC_BXAP_WBF_ENCODE(1)		|	\
+				 EBC_BXAP_TH_ENCODE(0)		|	\
+				 EBC_BXAP_RE_DISABLED		|	\
+				 EBC_BXAP_SOR_NONDELAYED	|	\
+				 EBC_BXAP_BEM_WRITEONLY		|	\
+				 EBC_BXAP_PEN_DISABLED)
+#define CONFIG_SYS_EBC_PB2CR	(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA1_BASE) | \
+				 EBC_BXCR_BS_1MB		|	\
+				 EBC_BXCR_BU_RW			|	\
+				 EBC_BXCR_BW_16BIT)
+
+/* Memory Bank 3 (Latches) */
+#define CONFIG_SYS_EBC_PB3AP	(EBC_BXAP_BME_ENABLED		|	\
+				 EBC_BXAP_FWT_ENCODE(8)		|	\
+				 EBC_BXAP_BWT_ENCODE(4)		|	\
+				 EBC_BXAP_BCE_DISABLE		|	\
+				 EBC_BXAP_BCT_2TRANS		|	\
+				 EBC_BXAP_CSN_ENCODE(0)		|	\
+				 EBC_BXAP_OEN_ENCODE(1)		|	\
+				 EBC_BXAP_WBN_ENCODE(1)		|	\
+				 EBC_BXAP_WBF_ENCODE(1)		|	\
+				 EBC_BXAP_TH_ENCODE(2)		|	\
+				 EBC_BXAP_RE_DISABLED		|	\
+				 EBC_BXAP_SOR_NONDELAYED	|	\
+				 EBC_BXAP_BEM_WRITEONLY		|	\
+				 EBC_BXAP_PEN_DISABLED)
+#define CONFIG_SYS_EBC_PB3CR	(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_LATCH_BASE) | \
+				 EBC_BXCR_BS_1MB		|	\
+				 EBC_BXCR_BU_RW			|	\
+				 EBC_BXCR_BW_16BIT)
+
+/*
+ * OSD Setup
+ */
+#define CONFIG_SYS_ICS8N3QV01
+#define CONFIG_SYS_MPC92469AC
+#define CONFIG_SYS_SIL1178
+#define CONFIG_SYS_OSD_SCREENS		CONFIG_SYS_FPGA_COUNT
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/dlvision.h b/qemu/roms/u-boot/include/configs/dlvision.h
new file mode 100644
index 000000000..1e86c556a
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/dlvision.h
@@ -0,0 +1,208 @@
+/*
+ * (C) Copyright 2009
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_405EP		1	/* this is a PPC405 CPU */
+#define CONFIG_DLVISION	        1	/*  on a Neo board */
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
+
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME		dlvision
+#define CONFIG_IDENT_STRING	" dlvision 0.02"
+#include "amcc-common.h"
+
+#define CONFIG_BOARD_EARLY_INIT_F	/* call board_early_init_f */
+#define CONFIG_MISC_INIT_R		/* call misc_init_r */
+
+#define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll   */
+
+/*
+ * Configure PLL
+ */
+#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
+#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
+
+#define CONFIG_ENV_IS_IN_FLASH	/* use FLASH for environment vars */
+
+/*
+ * Default environment variables
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_AMCC_DEF_ENV						\
+	CONFIG_AMCC_DEF_ENV_POWERPC					\
+	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
+	"kernel_addr=fc000000\0"					\
+	"fdt_addr=fc1e0000\0"						\
+	"ramdisk_addr=fc200000\0"					\
+	""
+
+#define CONFIG_PHY_ADDR		4	/* PHY address			*/
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_PHY1_ADDR	0xc	/* EMAC1 PHY address		*/
+#define CONFIG_PHY_CLK_FREQ    EMAC_STACR_CLK_66MHZ
+
+/*
+ * Commands additional to the ones defined in amcc-common.h
+ */
+#define CONFIG_CMD_CACHE
+#undef CONFIG_CMD_EEPROM
+
+/*
+ * SDRAM configuration (please see cpu/ppc/sdram.[ch])
+ */
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0 */
+
+/* SDRAM timings used in datasheet */
+#define CONFIG_SYS_SDRAM_CL             3	/* CAS latency */
+#define CONFIG_SYS_SDRAM_tRP           20	/* PRECHARGE command period */
+#define CONFIG_SYS_SDRAM_tRC           66	/* ACTIVE-to-ACTIVE period */
+#define CONFIG_SYS_SDRAM_tRCD          20	/* ACTIVE-to-READ delay */
+#define CONFIG_SYS_SDRAM_tRFC          66	/* Auto refresh period */
+
+/*
+ * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
+ * The Linux BASE_BAUD define should match this configuration.
+ *    baseBaud = cpuClock/(uartDivisor*16)
+ * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * set Linux BASE_BAUD to 403200.
+ */
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#undef  CONFIG_SYS_EXT_SERIAL_CLOCK           /* external serial clock */
+#undef  CONFIG_SYS_405_UART_ERRATA_59         /* 405GP/CR Rev. D silicon */
+#define CONFIG_SYS_BASE_BAUD		691200
+
+/*
+ * I2C stuff
+ */
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		100000
+
+/*
+ * FLASH organization
+ */
+#define CONFIG_SYS_FLASH_CFI		/* The flash is CFI compatible	*/
+#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
+
+#define CONFIG_SYS_FLASH_BASE		0xFC000000
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sectors per chip*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase/ms */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write/ms */
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buff'd writes */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO	/* 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* no warn upon unknown flash */
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector */
+#define CONFIG_ENV_ADDR		((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
+#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+#endif
+
+/*
+ * PPC405 GPIO Configuration
+ */
+#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO	Alternate1	*/ \
+{ \
+/* GPIO Core 0 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0	PerBLast */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO1	TS1E */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO2	TS2E */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO3	TS1O */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO4	TS2O */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1      }, /* GPIO5	TS3 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO6	TS4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO7	TS5 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO8	TS6 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO9	TrcClk */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10	PerCS1 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11	PerCS2 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12	PerCS3 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13	PerCS4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14	PerAddr03 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15	PerAddr04 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16	PerAddr05 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17	IRQ0 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18	IRQ1 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19	IRQ2 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO20	IRQ3 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO21	IRQ4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO22	IRQ5 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO23	IRQ6 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24	UART0_DCD */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25	UART0_DSR */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26	UART0_RI */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27	UART0_DTR */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28	UART1_Rx */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29	UART1_Tx */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO30	RejectPkt0 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO31	RejectPkt1 */ \
+} \
+}
+
+/*
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory (OCM) for temperary stack until sdram is tested */
+#define CONFIG_SYS_TEMP_STACK_OCM        1
+
+/* On Chip Memory location */
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (NOR-FLASH) initialization */
+#define CONFIG_SYS_EBC_PB0AP		0x92015480
+/* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB0CR		0xFC0DA000
+
+/* Memory Bank 1 (NVRAM) initializatio */
+#define CONFIG_SYS_EBC_PB1AP		0x92015480
+/* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit  */
+#define CONFIG_SYS_EBC_PB1CR		0xFB858000
+
+/* Memory Bank 2 (UART) initialization */
+#define CONFIG_UART_BASE		0x7f100000
+#define CONFIG_SYS_EBC_PB2AP		0x92015480
+/* BAS=0x7f1,BS=1MB,BU=R/W,BW=8bit */
+#define CONFIG_SYS_EBC_PB2CR		0x7f118000
+
+/* Memory Bank 3 (Latches) initialization */
+#define CONFIG_SYS_LATCH_BASE		0x7f200000
+#define CONFIG_SYS_EBC_PB3AP		0x92015480
+/* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB3CR		0x7f21a000
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/dnp5370.h b/qemu/roms/u-boot/include/configs/dnp5370.h
new file mode 100644
index 000000000..3f1f9f384
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/dnp5370.h
@@ -0,0 +1,130 @@
+/*
+ * U-boot - Configuration file for SSV DNP5370 board
+ */
+
+#ifndef __CONFIG_DNP5370_H__
+#define __CONFIG_DNP5370_H__
+
+/* this must come first */
+#include <asm/config-pre.h>
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU       bf537-0.3
+#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
+
+/*
+ * Clock Settings
+ *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+#define CONFIG_CLKIN_HZ                 25000000
+#define CONFIG_CLKIN_HALF               0
+#define CONFIG_PLL_BYPASS               0
+#define CONFIG_VCO_MULT                 24
+#define CONFIG_CCLK_DIV                 1
+#define CONFIG_SCLK_DIV                 5
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_ADD_WDTH     9
+#define CONFIG_MEM_SIZE         32
+
+#define CONFIG_EBIU_SDRRC_VAL   0x03a0
+#define CONFIG_EBIU_SDBCTL_VAL  0x0013
+#define CONFIG_EBIU_SDGCTL_VAL  0x8091998d
+
+#define CONFIG_EBIU_AMGCTL_VAL  0xF7
+#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
+#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
+
+#define CONFIG_SYS_MONITOR_LEN  (256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN   (128 * 1024)
+
+/*
+ * Network Settings
+ */
+#ifndef __ADSPBF534__
+#define CONFIG_ROOTPATH        "/romfs"
+
+#define CONFIG_BFIN_MAC         1
+#define CONFIG_PHY_ADDR         0
+#define CONFIG_RMII             1
+
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+
+#define CONFIG_LIB_RAND
+#endif
+
+/*
+ * Flash Settings
+ *
+ * Only 3 MB of the 4 MB NOR flash are addressable.
+ * But limiting the flash size does not seem to work.
+ * It seems the CFI detection has precedence.
+ */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_BASE       0x20000000
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS  1
+#define CONFIG_SYS_MAX_FLASH_SECT   71 /* (M29W320EB) */
+
+/* 512k reserved for u-boot */
+#define CONFIG_SYS_JFFS2_FIRST_SECTOR 15
+
+/*
+ * Env Storage Settings
+ */
+#define CONFIG_ENV_IS_IN_FLASH     1
+#define CONFIG_ENV_ADDR       0x20004000
+#define CONFIG_ENV_SIZE       0x00002000
+#define CONFIG_ENV_SECT_SIZE  0x00002000 /* Total Size of Environment Sector */
+#define CONFIG_ENV_OFFSET     0x00004000 /* (CONFIG_ENV_ADDR - CONFIG_FLASH_BASE) */
+
+#define ENV_IS_EMBEDDED
+#define LDS_BOARD_TEXT \
+	arch/blackfin/lib/built-in.o (.text*); \
+	arch/blackfin/cpu/built-in.o (.text*); \
+	. = DEFINED(env_offset) ? env_offset : .; \
+	common/env_embedded.o (.text*);
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_CMD_GPIO
+#define CONFIG_CMD_STRINGS
+#define CONFIG_MISC_INIT_R
+#define CONFIG_RTC_BFIN
+#define CONFIG_SYS_LONGHELP
+
+/* This disables the hardware watchdog (not inside the bfin) */
+#define CONFIG_DNP5370_EXT_WD_DISABLE 1
+
+#define CONFIG_UART_CONSOLE 0
+#define CONFIG_BFIN_SERIAL
+#define CONFIG_BAUDRATE     115200
+#define CONFIG_BOOTCOMMAND  "bootm 0x20030000"
+#define CONFIG_BOOTARGS     "console=ttyBF0,115200 root=/dev/mtdblock3 rootfstype=ext2"
+
+/* Convenience commands to update Linux in NOR flash */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"fetchme=tftpboot 0x01000000 uImage;" \
+		"iminfo\0" \
+	"flashme=protect off 0x20030000 0x2003ffff;" \
+		"erase 0x20030000 0x202effff;" \
+		"cp.b 0x01000000 0x20030000 0x2c0000\0" \
+	"runme=bootm 0x01000000\0"
+
+/* this sets up the default list of enabled commands */
+#include <config_cmd_default.h>
+
+#ifndef CONFIG_BFIN_MAC
+# undef CONFIG_CMD_NET
+# undef CONFIG_CMD_NFS
+#endif
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/dns325.h b/qemu/roms/u-boot/include/configs/dns325.h
new file mode 100644
index 000000000..96db44f51
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/dns325.h
@@ -0,0 +1,170 @@
+/*
+ * Copyright (C) 2011
+ * Stefan Herbrechtsmeier <stefan@code.herbrechtsmeier.net>
+ *
+ * Based on Kirkwood support:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CONFIG_DNS325_H
+#define _CONFIG_DNS325_H
+
+/*
+ * Machine number definition
+ */
+#define MACH_TYPE_DNS325		3800
+#define CONFIG_MACH_TYPE		MACH_TYPE_DNS325
+#define CONFIG_IDENT_STRING		"\nD-Link DNS-325"
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_FEROCEON_88FR131		/* CPU Core subversion */
+#define CONFIG_KIRKWOOD			/* SOC Family Name */
+#define CONFIG_KW88F6281		/* SOC Name */
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_DATE
+#define CONFIG_SYS_MVFS
+
+#define CONFIG_NR_DRAM_BANKS		1
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/* Remove or override few declarations from mv-common.h */
+#undef CONFIG_SYS_PROMPT
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS		{1, 0} /* enable port 0 only */
+#define CONFIG_NETCONSOLE
+#endif
+
+/*
+ * SATA Driver configuration
+ */
+#ifdef CONFIG_MVSATA_IDE
+#define CONFIG_SYS_ATA_IDE0_OFFSET      MV_SATA_PORT0_OFFSET
+#define CONFIG_SYS_ATA_IDE1_OFFSET      MV_SATA_PORT1_OFFSET
+#endif
+
+/*
+ * RTC driver configuration
+ */
+#ifdef CONFIG_CMD_DATE
+#define CONFIG_RTC_MV
+#endif
+
+/*
+ * Enable GPI0 support
+ */
+#define CONFIG_KIRKWOOD_GPIO
+
+/*
+ * Use the HUSH parser
+ */
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Console configuration
+ */
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+/*
+ * Enable device tree support
+ */
+#define CONFIG_OF_LIBFDT
+
+/*
+ * Display cpu info at boot
+ */
+#define CONFIG_DISPLAY_CPUINFO
+
+/*
+ * Environment variables configurations
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SECT_SIZE		0x20000	/* 128KB */
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+#define CONFIG_ENV_SIZE			0x20000	/* 128KB */
+#define CONFIG_ENV_ADDR			0xe0000
+#define CONFIG_ENV_OFFSET		0xe0000	/* env starts here */
+
+/*
+ * Default environment variables
+ */
+#define MTDIDS_DEFAULT			"nand0=orion_nand"
+
+#define MTDPARTS_DEFAULT		"mtdparts=orion_nand:" \
+	"896k(u-boot),128k(u-boot-env),5m(kernel),-(rootfs)\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"stdin=serial\0" \
+	"stdout=serial\0" \
+	"stderr=serial\0" \
+	"loadaddr=0x800000\0" \
+	"autoload=no\0" \
+	"console=ttyS0,115200\0" \
+	"mtdparts="MTDPARTS_DEFAULT \
+	"optargs=\0" \
+	"bootenv=uEnv.txt\0" \
+	"importbootenv=echo Importing environment ...; " \
+		"env import -t ${loadaddr} ${filesize}\0" \
+	"loadbootenv=fatload usb 0 ${loadaddr} ${bootenv}\0" \
+	"setbootargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"${mtdparts} " \
+		"root=${bootenvroot} " \
+		"rootfstype=${bootenvrootfstype}\0" \
+	"subbootcmd=run setbootargs; " \
+		"if run bootenvloadimage; then " \
+			"bootm ${loadaddr};" \
+		"fi;\0" \
+	"nandroot=ubi0:rootfs ubi.mtd=rootfs\0" \
+	"nandrootfstype=ubifs\0" \
+	"nandloadimage=nand read ${loadaddr} kernel\0" \
+	"setnandbootenv=echo Booting from nand ...; " \
+		"setenv bootenvroot ${nandroot}; " \
+		"setenv bootenvrootfstype ${nandrootfstype}; " \
+		"setenv bootenvloadimage ${nandloadimage}\0"
+
+#define CONFIG_BOOTCOMMAND \
+	"if test -n ${bootenv} && usb start; then " \
+		"if run loadbootenv; then " \
+			"echo Loaded environment ${bootenv} from usb;" \
+			"run importbootenv;" \
+		"fi;" \
+		"if test -n ${bootenvcmd}; then " \
+			"echo Running bootenvcmd ...;" \
+			"run bootenvcmd;" \
+		"fi;" \
+	"fi;" \
+	"run setnandbootenv subbootcmd;"
+
+#endif /* _CONFIG_DNS325_H */
diff --git a/qemu/roms/u-boot/include/configs/dockstar.h b/qemu/roms/u-boot/include/configs/dockstar.h
new file mode 100644
index 000000000..d66bd2ab3
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/dockstar.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (C) 2010  Eric C. Cooper <ecc@cmu.edu>
+ *
+ * Based on sheevaplug.h originally written by
+ * Prafulla Wadaskar <prafulla@marvell.com>
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CONFIG_DOCKSTAR_H
+#define _CONFIG_DOCKSTAR_H
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING	"\nSeagate FreeAgent DockStar"
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_FEROCEON_88FR131	1	/* CPU Core subversion */
+#define CONFIG_KIRKWOOD		1	/* SOC Family Name */
+#define CONFIG_KW88F6281	1	/* SOC Name */
+#define CONFIG_MACH_DOCKSTAR	/* Machine type */
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+#undef CONFIG_SYS_PROMPT	/* previously defined in mv-common.h */
+#define CONFIG_SYS_PROMPT	"DockStar> "	/* Command Prompt */
+
+/*
+ *  Environment variables configurations
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_ENV_IS_IN_NAND		1
+#define CONFIG_ENV_SECT_SIZE		0x20000	/* 128K */
+#else
+#define CONFIG_ENV_IS_NOWHERE		1	/* if env in SDRAM */
+#endif
+/*
+ * max 4k env size is enough, but in case of nand
+ * it has to be rounded to sector size
+ */
+#define CONFIG_ENV_SIZE			0x20000	/* 128k */
+#define CONFIG_ENV_ADDR			0x60000
+#define CONFIG_ENV_OFFSET		0x60000	/* env starts here */
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_BOOTCOMMAND \
+	"setenv bootargs ${console} ${mtdparts} ${bootargs_root}; "	\
+	"ubi part root; " \
+	"ubifsmount ubi:root; " \
+	"ubifsload 0x800000 ${kernel}; " \
+	"ubifsload 0x1100000 ${initrd}; " \
+	"bootm 0x800000 0x1100000"
+
+#define CONFIG_MTDPARTS		"mtdparts=orion_nand:1m(uboot),-(root)\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"console=console=ttyS0,115200\0" \
+	"mtdids=nand0=orion_nand\0" \
+	"mtdparts="CONFIG_MTDPARTS \
+	"kernel=/boot/uImage\0" \
+	"initrd=/boot/uInitrd\0" \
+	"bootargs_root=ubi.mtd=1 root=ubi0:root rootfstype=ubifs ro\0"
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS	{1, 0}	/* enable port 0 only */
+#define CONFIG_PHY_BASE_ADR	0
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * File system
+ */
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_LZO
+
+#endif /* _CONFIG_DOCKSTAR_H */
diff --git a/qemu/roms/u-boot/include/configs/dra7xx_evm.h b/qemu/roms/u-boot/include/configs/dra7xx_evm.h
new file mode 100644
index 000000000..8d0a0eb8b
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/dra7xx_evm.h
@@ -0,0 +1,146 @@
+/*
+ * (C) Copyright 2013
+ * Texas Instruments Incorporated.
+ * Lokesh Vutla	  <lokeshvutla@ti.com>
+ *
+ * Configuration settings for the TI DRA7XX board.
+ * See ti_omap5_common.h for omap5 common settings.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_DRA7XX_EVM_H
+#define __CONFIG_DRA7XX_EVM_H
+
+#define CONFIG_DRA7XX
+
+#ifndef CONFIG_QSPI_BOOT
+/* MMC ENV related defines */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV		1	/* SLOT2: eMMC(1) */
+#define CONFIG_ENV_SIZE			(128 << 10)
+#define CONFIG_ENV_OFFSET		0xE0000
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#endif
+#define CONFIG_CMD_SAVEENV
+
+#if (CONFIG_CONS_INDEX == 1)
+#define CONSOLEDEV			"ttyO0"
+#elif (CONFIG_CONS_INDEX == 3)
+#define CONSOLEDEV			"ttyO2"
+#endif
+#define CONFIG_SYS_NS16550_COM1		UART1_BASE	/* Base EVM has UART0 */
+#define CONFIG_SYS_NS16550_COM2		UART2_BASE	/* UART2 */
+#define CONFIG_SYS_NS16550_COM3		UART3_BASE	/* UART3 */
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_SYS_OMAP_ABE_SYSCK
+
+/* Define the default GPT table for eMMC */
+#define PARTS_DEFAULT \
+	"uuid_disk=${uuid_gpt_disk};" \
+	"name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}"
+
+#include <configs/ti_omap5_common.h>
+
+/* Enhance our eMMC support / experience. */
+#define CONFIG_CMD_GPT
+#define CONFIG_EFI_PARTITION
+#define CONFIG_PARTITION_UUIDS
+#define CONFIG_CMD_PART
+
+/* CPSW Ethernet */
+#define CONFIG_CMD_NET			/* 'bootp' and 'tftp' */
+#define CONFIG_CMD_DHCP
+#define CONFIG_BOOTP_DNS		/* Configurable parts of CMD_DHCP */
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_NET_RETRY_COUNT		10
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MII
+#define CONFIG_DRIVER_TI_CPSW		/* Driver for IP block */
+#define CONFIG_MII			/* Required in net/eth.c */
+#define CONFIG_PHY_GIGE			/* per-board part of CPSW */
+#define CONFIG_PHYLIB
+
+/* SPI */
+#undef	CONFIG_OMAP3_SPI
+#define CONFIG_TI_QSPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_SPI_FLASH_BAR
+#define CONFIG_TI_SPI_MMAP
+#define CONFIG_SF_DEFAULT_SPEED                48000000
+#define CONFIG_DEFAULT_SPI_MODE                SPI_MODE_3
+
+/*
+ * Default to using SPI for environment, etc.
+ * 0x000000 - 0x010000 : QSPI.SPL (64KiB)
+ * 0x010000 - 0x020000 : QSPI.SPL.backup1 (64KiB)
+ * 0x020000 - 0x030000 : QSPI.SPL.backup2 (64KiB)
+ * 0x030000 - 0x040000 : QSPI.SPL.backup3 (64KiB)
+ * 0x040000 - 0x140000 : QSPI.u-boot (1MiB)
+ * 0x140000 - 0x1C0000 : QSPI.u-boot-spl-os (512KiB)
+ * 0x1C0000 - 0x1D0000 : QSPI.u-boot-env (64KiB)
+ * 0x1D0000 - 0x1E0000 : QSPI.u-boot-env.backup1 (64KiB)
+ * 0x1E0000 - 0x9E0000 : QSPI.kernel (8MiB)
+ * 0x9E0000 - 0x2000000 : USERLAND
+ */
+#define CONFIG_SYS_SPI_KERNEL_OFFS	0x1E0000
+#define CONFIG_SYS_SPI_ARGS_OFFS	0x140000
+#define CONFIG_SYS_SPI_ARGS_SIZE	0x80000
+#if defined(CONFIG_QSPI_BOOT)
+/* In SPL, use the environment and discard MMC support for space. */
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_SPL_MMC_SUPPORT
+#undef CONFIG_SPL_MAX_SIZE
+#define CONFIG_SPL_MAX_SIZE             (64 << 10) /* 64 KiB */
+#endif
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_SPI_MAX_HZ           CONFIG_SF_DEFAULT_SPEED
+#define CONFIG_ENV_SIZE			(64 << 10)
+#define CONFIG_ENV_SECT_SIZE		(64 << 10) /* 64 KB sectors */
+#define CONFIG_ENV_OFFSET		0x1C0000
+#define CONFIG_ENV_OFFSET_REDUND	0x1D0000
+#endif
+
+/* SPI SPL */
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_BUS             0
+#define CONFIG_SPL_SPI_CS              0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS     0x40000
+
+#define CONFIG_SUPPORT_EMMC_BOOT
+
+/* USB xHCI HOST */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_HOST
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_OMAP
+#define CONFIG_USB_STORAGE
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+
+#define CONFIG_OMAP_USB_PHY
+#define CONFIG_OMAP_USB2PHY2_HOST
+
+/* SATA */
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_CMD_SCSI
+#define CONFIG_LIBATA
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	1
+#define CONFIG_SYS_SCSI_MAX_LUN		1
+#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+						CONFIG_SYS_SCSI_MAX_LUN)
+
+#endif /* __CONFIG_DRA7XX_EVM_H */
diff --git a/qemu/roms/u-boot/include/configs/dreamplug.h b/qemu/roms/u-boot/include/configs/dreamplug.h
new file mode 100644
index 000000000..b1ca85925
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/dreamplug.h
@@ -0,0 +1,137 @@
+/*
+ * (C) Copyright 2011
+ * Jason Cooper <u-boot@lakedaemon.net>
+ *
+ * Based on work by:
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Siddarth Gore <gores@marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CONFIG_DREAMPLUG_H
+#define _CONFIG_DREAMPLUG_H
+
+/*
+ * FIXME: This belongs in mach-types.h.  However, we only pull mach-types
+ * from Linus' kernel.org tree.  This hasn't been updated primarily due to
+ * the recent arch/arm reshuffling.  So, in the meantime, we'll place it
+ * here.
+ */
+#include <asm/mach-types.h>
+#ifdef MACH_TYPE_DREAMPLUG
+#error "MACH_TYPE_DREAMPLUG has been defined properly, please remove this."
+#else
+#define MACH_TYPE_DREAMPLUG            3550
+#endif
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING	"\nMarvell-DreamPlug"
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_SHEEVA_88SV131	1	/* CPU Core subversion */
+#define CONFIG_KIRKWOOD		1	/* SOC Family Name */
+#define CONFIG_KW88F6281	1	/* SOC Name */
+#define CONFIG_MACH_TYPE	MACH_TYPE_DREAMPLUG
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_DATE
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/*
+ *  Environment variables configurations
+ */
+#ifdef CONFIG_SPI_FLASH
+#define CONFIG_ENV_IS_IN_SPI_FLASH	1
+#define CONFIG_ENV_SECT_SIZE		0x10000	/* 64k */
+#else
+#define CONFIG_ENV_IS_NOWHERE		1	/* if env in SDRAM */
+#endif
+
+#ifdef CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH		1
+#define CONFIG_HARD_SPI			1
+#define CONFIG_KIRKWOOD_SPI		1
+#define CONFIG_SPI_FLASH_MACRONIX	1
+#define CONFIG_ENV_SPI_BUS		0
+#define CONFIG_ENV_SPI_CS		0
+#define CONFIG_ENV_SPI_MAX_HZ		50000000 /* 50 MHz */
+#endif
+
+/*
+ * max 4k env size is enough, but in case of nand
+ * it has to be rounded to sector size
+ */
+#define CONFIG_ENV_SIZE			0x1000  /* 4k */
+#define CONFIG_ENV_ADDR			0x100000
+#define CONFIG_ENV_OFFSET		0x100000 /* env starts here */
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_BOOTCOMMAND		"setenv ethact egiga0; " \
+	"${x_bootcmd_ethernet}; setenv ethact egiga1; " \
+	"${x_bootcmd_ethernet}; ${x_bootcmd_usb}; ${x_bootcmd_kernel}; "\
+	"setenv bootargs ${x_bootargs} ${x_bootargs_root}; "	\
+	"bootm 0x6400000;"
+
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"x_bootcmd_ethernet=ping 192.168.2.1\0"	\
+	"x_bootcmd_usb=usb start\0"	\
+	"x_bootcmd_kernel=fatload usb 0 0x6400000 uImage\0" \
+	"x_bootargs=console=ttyS0,115200\0"	\
+	"x_bootargs_root=root=/dev/sda2 rootdelay=10\0"
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS	{1, 1}	/* enable both ports */
+#define CONFIG_PHY_BASE_ADR	0
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * SATA Driver configuration
+ */
+#ifdef CONFIG_MVSATA_IDE
+#define CONFIG_SYS_ATA_IDE0_OFFSET	MV_SATA_PORT0_OFFSET
+#endif /*CONFIG_MVSATA_IDE*/
+
+/*
+ * RTC driver configuration
+ */
+#ifdef CONFIG_CMD_DATE
+#define CONFIG_RTC_MV
+#endif /* CONFIG_CMD_DATE */
+
+#define CONFIG_SYS_ALT_MEMTEST
+
+/*
+ * display enhanced info about the cpu at boot.
+ */
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_OF_LIBFDT
+
+#endif /* _CONFIG_DREAMPLUG_H */
diff --git a/qemu/roms/u-boot/include/configs/dxr2.h b/qemu/roms/u-boot/include/configs/dxr2.h
new file mode 100644
index 000000000..75f7812e7
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/dxr2.h
@@ -0,0 +1,93 @@
+/*
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * U-Boot file:/include/configs/am335x_evm.h
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_DXR2_H
+#define __CONFIG_DXR2_H
+
+#define CONFIG_SIEMENS_DXR2
+#define MACH_TYPE_DXR2			4315
+#define CONFIG_SIEMENS_MACH_TYPE	MACH_TYPE_DXR2
+
+#include "siemens-am33x-common.h"
+
+#define CONFIG_SYS_MPUCLK	275
+#define DXR2_IOCTRL_VAL	0x18b
+#define DDR_PLL_FREQ	303
+#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
+
+#define BOARD_DFU_BUTTON_GPIO	27
+#define BOARD_DFU_BUTTON_LED	64
+#define GPIO_LAN9303_NRST	88	/* GPIO2_24 = gpio88 */
+
+#undef CONFIG_DOS_PARTITION
+#undef CONFIG_CMD_FAT
+
+
+ /* Physical Memory Map */
+#define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 20)	/* 1GB */
+
+/* I2C Configuration */
+#define CONFIG_SYS_I2C_SPEED		100000
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR              0x50
+#define EEPROM_ADDR_DDR3 0x90
+#define EEPROM_ADDR_CHIP 0x120
+
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x300
+
+#undef CONFIG_SPL_NET_SUPPORT
+#undef CONFIG_SPL_NET_VCI_STRING
+#undef CONFIG_SPL_ETH_SUPPORT
+
+#undef CONFIG_MII
+#undef CONFIG_PHY_GIGE
+#define CONFIG_PHY_SMSC
+
+#define CONFIG_FACTORYSET
+
+/* Watchdog */
+#define CONFIG_OMAP_WATCHDOG
+
+#ifndef CONFIG_SPL_BUILD
+
+/* Default env settings */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"hostname=dxr2\0" \
+	"nand_img_size=0x400000\0" \
+	"optargs=\0" \
+	CONFIG_COMMON_ENV_SETTINGS
+
+#ifndef CONFIG_RESTORE_FLASH
+/* set to negative value for no autoboot */
+#define CONFIG_BOOTDELAY		3
+
+#define CONFIG_BOOTCOMMAND \
+"if dfubutton; then " \
+	"run dfu_start; " \
+	"reset; " \
+"fi;" \
+"run nand_boot;" \
+"reset;"
+
+
+#else
+#define CONFIG_BOOTDELAY		0
+
+#define CONFIG_BOOTCOMMAND			\
+	"setenv autoload no; "			\
+	"dhcp; "				\
+	"if tftp 80000000 debrick.scr; then "	\
+		"source 80000000; "		\
+	"fi"
+#endif
+#endif	/* CONFIG_SPL_BUILD */
+#endif	/* ! __CONFIG_DXR2_H */
diff --git a/qemu/roms/u-boot/include/configs/eXalion.h b/qemu/roms/u-boot/include/configs/eXalion.h
new file mode 100644
index 000000000..940be1f5d
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/eXalion.h
@@ -0,0 +1,433 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+/* #define CONFIG_MPC8240	   1 */
+#define CONFIG_MPC8245		1
+#define CONFIG_EXALION		1
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
+
+#if defined (CONFIG_MPC8240)
+    /* #warning	 ---------- eXalion with MPC8240 --------------- */
+#elif defined (CONFIG_MPC8245)
+    /* #warning	 ++++++++++ eXalion with MPC8245 +++++++++++++++ */
+#elif defined (CONFIG_MPC8245) && defined (CONFIG_MPC8245)
+#error #### Both types of MPC824x defined (CONFIG_8240 and CONFIG_8245)
+#else
+#error #### Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
+#endif
+/* older kernels need clock in MHz newer in Hz */
+					/* #define CONFIG_CLOCKS_IN_MHZ 1 */ /* clocks passsed to Linux in MHz	    */
+#undef CONFIG_CLOCKS_IN_MHZ
+
+#define CONFIG_BOOTDELAY	10
+
+
+						    /*#define CONFIG_DRAM_SPEED	      66   */ /* MHz			     */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_PCI
+
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		1	/* undef to save memory		*/
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size	*/
+#define CONFIG_SYS_MAXARGS		8	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address		*/
+#define CONFIG_MISC_INIT_R	1
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_MAX_RAM_SIZE	0x10000000	/* 1 GBytes - initdram() will	   */
+					     /* return real value.		*/
+
+#define CONFIG_SYS_RESET_ADDRESS	0xFFF00100
+
+#undef	CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	    */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area
+ */
+#define CONFIG_SYS_INIT_DATA_SIZE	128
+
+#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
+#define CONFIG_SYS_INIT_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_DATA_SIZE)
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+
+#if defined (CONFIG_MPC8240)
+#define CONFIG_SYS_FLASH_BASE	    0xFFE00000
+#define CONFIG_SYS_FLASH_SIZE	    (2 * 1024 * 1024)	/* onboard 2MByte flash	    */
+#elif defined (CONFIG_MPC8245)
+#define CONFIG_SYS_FLASH_BASE	    0xFFC00000
+#define CONFIG_SYS_FLASH_SIZE	    (4 * 1024 * 1024)	/* onboard 4MByte flash	    */
+#else
+#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
+#endif
+
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* Size of one Flash sector */
+#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE	/* Use one Flash sector for environment	*/
+#define CONFIG_ENV_ADDR		0xFFFC0000
+#define CONFIG_ENV_OFFSET		0	/* starting right at the beginning  */
+
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+
+#define CONFIG_SYS_ALT_MEMTEST		1	/* use real memory test	    */
+#define CONFIG_SYS_MEMTEST_START	0x00004000	/* memtest works on	    */
+#define CONFIG_SYS_MEMTEST_END		0x02000000	/* 0 ... 32 MB in DRAM	    */
+
+#define CONFIG_SYS_EUMB_ADDR		0xFC000000
+
+/* #define CONFIG_SYS_ISA_MEM		   0xFD000000 */
+#define CONFIG_SYS_ISA_IO		0xFE000000
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* Max number of flash banks	    */
+#define CONFIG_SYS_MAX_FLASH_SECT	64	/* Max number of sectors per flash  */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
+
+#define FLASH_BASE0_PRELIM	CONFIG_SYS_FLASH_BASE
+#define FLASH_BASE1_PRELIM	0
+
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant		*/
+#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_FLASH_INCREMENT	0	/* there is only one bank		*/
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* use hardware protection		*/
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ */
+#define CONFIG_PCI		1	/* include pci support		*/
+#define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
+#undef	CONFIG_PCI_PNP
+
+
+#define CONFIG_EEPRO100		1
+
+#define PCI_ENET0_MEMADDR	0x80000000	/* Intel 82559ER */
+#define PCI_ENET0_IOADDR	0x80000000
+#define PCI_ENET1_MEMADDR	0x81000000	/* Intel 82559ER */
+#define PCI_ENET1_IOADDR	0x81000000
+#define PCI_ENET2_MEMADDR	0x82000000	/* Broadcom BCM569xx */
+#define PCI_ENET2_IOADDR	0x82000000
+#define PCI_ENET3_MEMADDR	0x83000000	/* Broadcom BCM56xx */
+#define PCI_ENET3_IOADDR	0x83000000
+
+/*-----------------------------------------------------------------------
+ * NS16550 Configuration
+ */
+#define CONFIG_SYS_NS16550		1
+#define CONFIG_SYS_NS16550_SERIAL	1
+
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		38400
+
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+
+#if (CONFIG_CONS_INDEX == 1)
+#define CONFIG_SYS_NS16550_CLK		1843200 /* COM1 only !	*/
+#else
+#define CONFIG_SYS_NS16550_CLK ({ extern ulong get_bus_freq (ulong); get_bus_freq (0); })
+#endif
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_ISA_IO + 0x3F8)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_EUMB_ADDR + 0x4500)
+#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_EUMB_ADDR + 0x4600)
+
+/*-----------------------------------------------------------------------
+ * select i2c support configuration
+ *
+ * Supported configurations are {none, software, hardware} drivers.
+ * If the software driver is chosen, there are some additional
+ * configuration items that the driver uses to drive the port pins.
+ */
+#define CONFIG_HARD_I2C		1	/* To enable I2C support	*/
+#undef	CONFIG_SYS_I2C_SOFT		/* I2C bit-banged		*/
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+
+/*-----------------------------------------------------------------------
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+#define CONFIG_SYS_CLK_FREQ	33333333	/* external frequency to pll	*/
+#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER  2	/* for MPC8240 only		*/
+
+				       /*#define CONFIG_133MHZ_DRAM	 1 */ /* For 133 MHZ DRAM only !!!!!!!!!!!    */
+
+#if defined (CONFIG_MPC8245)
+/* Bit-field values for PMCR2.							*/
+#if defined (CONFIG_133MHZ_DRAM)
+#define CONFIG_SYS_DLL_EXTEND		0x80	/* use DLL extended range - 133MHz only */
+#define CONFIG_SYS_PCI_HOLD_DEL	0x20	/* delay and hold timing - 133MHz only	*/
+#endif
+
+/* Bit-field values for MIOCR1.							*/
+#if !defined (CONFIG_133MHZ_DRAM)
+#define CONFIG_SYS_DLL_MAX_DELAY	0x04	/*  longer DLL delay line - 66MHz only	*/
+#endif
+/* Bit-field values for MIOCR2.							*/
+#define CONFIG_SYS_SDRAM_DSCD		0x20	/* SDRAM data in sample clock delay	*/
+					/*	- note bottom 3 bits MUST be 0	*/
+#endif
+
+/* Bit-field values for MCCR1.							*/
+#define CONFIG_SYS_ROMNAL		7	/*rom/flash next access time		*/
+#define CONFIG_SYS_ROMFAL	       11	/*rom/flash access time			*/
+
+/* Bit-field values for MCCR2.							*/
+#define CONFIG_SYS_TSWAIT		0x5	/* Transaction Start Wait States timer	*/
+#if defined (CONFIG_133MHZ_DRAM)
+#define CONFIG_SYS_REFINT		1300	/* no of clock cycles between CBR	*/
+#else  /* refresh cycles */
+#define CONFIG_SYS_REFINT		750
+#endif
+
+/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.		*/
+#if defined (CONFIG_133MHZ_DRAM)
+#define CONFIG_SYS_BSTOPRE		1023
+#else
+#define CONFIG_SYS_BSTOPRE		250
+#endif
+
+/* Bit-field values for MCCR3.							*/
+/* the following are for SDRAM only						*/
+
+#if defined (CONFIG_133MHZ_DRAM)
+#define CONFIG_SYS_REFREC		9	/* Refresh to activate interval		*/
+#else
+#define CONFIG_SYS_REFREC		5	/* Refresh to activate interval		*/
+#endif
+#if defined (CONFIG_MPC8240)
+#define CONFIG_SYS_RDLAT		2	/* data latency from read command	*/
+#endif
+
+/* Bit-field values for MCCR4.	*/
+#if defined (CONFIG_133MHZ_DRAM)
+#define CONFIG_SYS_PRETOACT		3	/* Precharge to activate interval	*/
+#define CONFIG_SYS_ACTTOPRE		7	/* Activate to Precharge interval	*/
+#define CONFIG_SYS_ACTORW		5	/* Activate to R/W			*/
+#define CONFIG_SYS_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
+#else
+#if 0
+#define CONFIG_SYS_PRETOACT		2	/* Precharge to activate interval	*/
+#define CONFIG_SYS_ACTTOPRE		3	/* Activate to Precharge interval	*/
+#define CONFIG_SYS_ACTORW		3	/* Activate to R/W			*/
+#define CONFIG_SYS_SDMODE_CAS_LAT	2	/* SDMODE CAS latency			*/
+#endif
+#define CONFIG_SYS_PRETOACT		2	/* Precharge to activate interval	*/
+#define CONFIG_SYS_ACTTOPRE		5	/* Activate to Precharge interval	*/
+#define CONFIG_SYS_ACTORW		3	/* Activate to R/W			*/
+#define CONFIG_SYS_SDMODE_CAS_LAT	3	/* SDMODE CAS latency			*/
+#endif
+#define CONFIG_SYS_SDMODE_WRAP		0	/* SDMODE wrap type			*/
+#define CONFIG_SYS_SDMODE_BURSTLEN	2	/* SDMODE Burst length 2=4, 3=8		*/
+#define CONFIG_SYS_REGDIMM		0
+#if defined (CONFIG_MPC8240)
+#define CONFIG_SYS_REGISTERD_TYPE_BUFFER   0
+#elif defined (CONFIG_MPC8245)
+#define CONFIG_SYS_REGISTERD_TYPE_BUFFER   1
+#define CONFIG_SYS_EXTROM		    0
+#else
+#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
+#endif
+
+
+/*-----------------------------------------------------------------------
+ memory bank settings
+ * only bits 20-29 are actually used from these vales to set the
+ * start/end address the upper two bits will be 0, and the lower 20
+ * bits will be set to 0x00000 for a start address, or 0xfffff for an
+ * end address
+ */
+#define CONFIG_SYS_BANK0_START		0x00000000
+#define CONFIG_SYS_BANK0_END		(CONFIG_SYS_MAX_RAM_SIZE - 1)
+#define CONFIG_SYS_BANK0_ENABLE	1
+#define CONFIG_SYS_BANK1_START		0x3ff00000
+#define CONFIG_SYS_BANK1_END		0x3fffffff
+#define CONFIG_SYS_BANK1_ENABLE	0
+#define CONFIG_SYS_BANK2_START		0x3ff00000
+#define CONFIG_SYS_BANK2_END		0x3fffffff
+#define CONFIG_SYS_BANK2_ENABLE	0
+#define CONFIG_SYS_BANK3_START		0x3ff00000
+#define CONFIG_SYS_BANK3_END		0x3fffffff
+#define CONFIG_SYS_BANK3_ENABLE	0
+#define CONFIG_SYS_BANK4_START		0x00000000
+#define CONFIG_SYS_BANK4_END		0x00000000
+#define CONFIG_SYS_BANK4_ENABLE	0
+#define CONFIG_SYS_BANK5_START		0x00000000
+#define CONFIG_SYS_BANK5_END		0x00000000
+#define CONFIG_SYS_BANK5_ENABLE	0
+#define CONFIG_SYS_BANK6_START		0x00000000
+#define CONFIG_SYS_BANK6_END		0x00000000
+#define CONFIG_SYS_BANK6_ENABLE	0
+#define CONFIG_SYS_BANK7_START		0x00000000
+#define CONFIG_SYS_BANK7_END		0x00000000
+#define CONFIG_SYS_BANK7_ENABLE	0
+
+/*-----------------------------------------------------------------------
+ * Memory bank enable bitmask, specifying which of the banks defined above
+ are actually present. MSB is for bank #7, LSB is for bank #0.
+ */
+#define CONFIG_SYS_BANK_ENABLE		0x01
+
+#if defined (CONFIG_MPC8240)
+#define CONFIG_SYS_ODCR		0xDF	/* configures line driver impedances,	*/
+					/* see 8240 book for bit definitions	*/
+#elif defined (CONFIG_MPC8245)
+#if defined (CONFIG_133MHZ_DRAM)
+#define CONFIG_SYS_ODCR		0xFE	/* configures line driver impedances - 133MHz	*/
+#else
+#define CONFIG_SYS_ODCR		0xDE	/* configures line driver impedances - 66MHz	*/
+#endif
+#else
+#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
+#endif
+
+#define CONFIG_SYS_PGMAX		0x32	/* how long the 8240 retains the	*/
+					/* currently accessed page in memory	*/
+					/* see 8240 book for details		*/
+
+/*-----------------------------------------------------------------------
+ * Block Address Translation (BAT) register settings.
+ */
+/* SDRAM 0 - 256MB */
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* stack in DCACHE @ 1GB (no backing mem) */
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+
+/* PCI memory */
+#define CONFIG_SYS_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* Flash, config addrs, etc */
+#define CONFIG_SYS_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
+
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	32
+#if defined(CONFIG_CMD_KGDB)
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/* values according to the manual */
+#define CONFIG_DRAM_50MHZ	1
+#define CONFIG_SDRAM_50MHZ
+
+#undef	NR_8259_INTS
+#define NR_8259_INTS		1
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff
+ */
+#define CONFIG_SYS_IDE_MAXBUS	    1	/* max. 2 IDE busses	*/
+#define CONFIG_SYS_IDE_MAXDEVICE   (CONFIG_SYS_IDE_MAXBUS*1)	/* max. 2 drives per IDE bus */
+
+#define CONFIG_SYS_ATA_BASE_ADDR   CONFIG_SYS_ISA_IO	/* base address */
+#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0	/* ide0 offste */
+#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0170	/* ide1 offset */
+#define CONFIG_SYS_ATA_DATA_OFFSET 0	/* data reg offset  */
+#define CONFIG_SYS_ATA_REG_OFFSET  0	/* reg offset */
+#define CONFIG_SYS_ATA_ALT_OFFSET  0x200	/* alternate register offset */
+
+#define CONFIG_ATAPI
+
+#undef	CONFIG_IDE_8xx_DIRECT	/* no pcmcia interface required */
+#undef	CONFIG_IDE_LED		/* no led for ide supported	*/
+#undef	CONFIG_IDE_RESET	/* reset for ide supported...	 */
+#undef	CONFIG_IDE_RESET_ROUTINE	/* with a special reset function */
+
+/*-----------------------------------------------------------------------
+ * DISK Partition support
+ */
+#define CONFIG_DOS_PARTITION
+
+/*-----------------------------------------------------------------------
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/ea20.h b/qemu/roms/u-boot/include/configs/ea20.h
new file mode 100644
index 000000000..1d50a37d2
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/ea20.h
@@ -0,0 +1,321 @@
+/*
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Based on davinci_dvevm.h. Original Copyrights follow:
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Board
+ */
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_USE_SPIFLASH
+#define	CONFIG_SYS_USE_NAND
+#define CONFIG_DRIVER_TI_EMAC_USE_RMII
+#define CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_VIDEO
+#define CONFIG_PREBOOT
+
+/*
+ * SoC Configuration
+ */
+#define CONFIG_MACH_DAVINCI_DA850_EVM
+#define CONFIG_ARM926EJS		/* arm926ejs CPU core */
+#define CONFIG_SOC_DA8XX		/* TI DA8xx SoC */
+#define CONFIG_SOC_DA850		/* TI DA850 SoC */
+#define CONFIG_SYS_CLK_FREQ		clk_get(DAVINCI_ARM_CLKID)
+#define CONFIG_SYS_OSCIN_FREQ		24000000
+#define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
+#define CONFIG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_TEXT_BASE		0xc1080000
+#define CONFIG_DA8XX_GPIO
+
+/*
+ * Memory Info
+ */
+#define CONFIG_SYS_MALLOC_LEN	(0x10000 + 4*1024*1024) /* malloc() len */
+#define PHYS_SDRAM_1		DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
+#define PHYS_SDRAM_1_SIZE	(64 << 20) /* SDRAM size 64MB */
+#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
+
+/* memtest start addr */
+#define CONFIG_SYS_MEMTEST_START	(PHYS_SDRAM_1 + 0x2000000)
+
+/* memtest will be run on 16MB */
+#define CONFIG_SYS_MEMTEST_END	(PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
+
+#define CONFIG_NR_DRAM_BANKS	1 /* we have 1 bank of DRAM */
+
+/*
+ * Serial Driver info
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	-4	/* NS16550 register size */
+#define CONFIG_SYS_NS16550_COM1	DAVINCI_UART0_BASE /* Base address of UART0 */
+#define CONFIG_SYS_NS16550_CLK	clk_get(DAVINCI_UART2_CLKID)
+#define CONFIG_CONS_INDEX	1		/* use UART0 for console */
+#define CONFIG_BAUDRATE		115200		/* Default baud rate */
+
+#define CONFIG_SPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_DAVINCI_SPI
+#define CONFIG_SYS_SPI_BASE		DAVINCI_SPI1_BASE
+#define CONFIG_SYS_SPI_CLK		clk_get(DAVINCI_SPI1_CLKID)
+#define CONFIG_SF_DEFAULT_SPEED		30000000
+#define CONFIG_ENV_SPI_MAX_HZ	CONFIG_SF_DEFAULT_SPEED
+
+/*
+ * I2C Configuration
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DAVINCI
+#define CONFIG_SYS_DAVINCI_I2C_SPEED		100000
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE   10 /* Bogus, master-only in U-Boot */
+
+/*
+ * Network & Ethernet Configuration
+ */
+#ifdef CONFIG_DRIVER_TI_EMAC
+#define CONFIG_EMAC_MDIO_PHY_NUM	0
+#define CONFIG_MII
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT	10
+#endif
+
+#ifdef CONFIG_USE_SPIFLASH
+#undef CONFIG_ENV_IS_IN_FLASH
+#undef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE			(8 << 10)
+#define CONFIG_ENV_OFFSET		0x80000
+#define CONFIG_ENV_SECT_SIZE		(64 << 10)
+#define CONFIG_SYS_NO_FLASH
+#endif
+
+
+#if defined(CONFIG_VIDEO)
+#define CONFIG_VIDEO_DA8XX
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_CMD_BMP
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#endif
+
+/*
+ * U-Boot general configuration
+ */
+#define CONFIG_BOOTFILE		"uImage" /* Boot file name */
+#define CONFIG_SYS_PROMPT	"ea20 > " /* Command Prompt */
+#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
+#define CONFIG_SYS_LOAD_ADDR	(PHYS_SDRAM_1 + 0x700000)
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+
+/*
+ * Linux Information
+ */
+#define LINUX_BOOT_PARAM_ADDR	(PHYS_SDRAM_1 + 0x100)
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * U-Boot commands
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_GPIO
+
+#ifdef CONFIG_CMD_BDI
+#define CONFIG_CLOCKS
+#endif
+
+#ifndef CONFIG_DRIVER_TI_EMAC
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_MII
+#undef CONFIG_CMD_PING
+#endif
+
+/* NAND Setup */
+#ifdef CONFIG_SYS_USE_NAND
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_NAND
+
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_LZO
+#define CONFIG_RBTREE
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+
+#define CONFIG_NAND_DAVINCI
+#define	CONFIG_SYS_NAND_PAGE_2K
+#define CONFIG_SYS_NAND_NO_SUBPAGE
+#define CONFIG_SYS_NAND_CS		2
+#define CONFIG_SYS_NAND_BASE		DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
+#undef CONFIG_SYS_NAND_HW_ECC
+#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
+#define	CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_MAX_NAND_DEVICE	1 /* Max number of NAND devices */
+#endif
+
+/* SPI Flash */
+#ifdef CONFIG_USE_SPIFLASH
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_FLASH
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SAVEENV
+#endif
+
+#if !defined(CONFIG_SYS_USE_NAND) && \
+	!defined(CONFIG_USE_NOR) && \
+	!defined(CONFIG_USE_SPIFLASH)
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_SIZE		(16 << 10)
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_ENV
+#endif
+
+/* additions for new relocation code, must added to all boards */
+#define CONFIG_SYS_SDRAM_BASE		0xc0000000
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 - \
+					GENERATED_GBL_DATA_SIZE)
+/*
+ * Default environment and default scripts
+ * to update uboot and load kernel
+ */
+
+#define CONFIG_HOSTNAME ea20
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"as=3\0"							\
+	"netdev=eth0\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"rfsbargs=setenv bootargs root=/dev/nfs rw "			\
+	"nfsroot=${serverip}:${rfsbpath}\0"				\
+	"testrfsargs=setenv bootargs root=/dev/nfs rw "		\
+	"nfsroot=${serverip}:${testrfspath}\0"				\
+	"ramargs=setenv bootargs root=/dev/ram rw initrd="		\
+	"0x${ramdisk_addr_r},4M\0"					\
+	"mtdids=nand0=davinci_nand.0\0"				\
+	"serverip=192.168.5.249\0"					\
+	"ipaddr=192.168.5.248\0"					\
+	"rootpath=/opt/eldk/arm\0"					\
+	"splashpos=230,180\0"						\
+	"testrfspath=/opt/eldk/test_arm\0"				\
+	"tempmac=setenv ethaddr 02:ea:20:ff:ff:ff\0"			\
+	"nandargs=setenv bootargs rootfstype=ubifs ro chk_data_crc "	\
+	"ubi.mtd=${as} root=ubi0:rootfs\0"				\
+	"nandrwargs=setenv bootargs rootfstype=ubifs rw chk_data_crc "	\
+	"ubi.mtd=${as} root=ubi0:rootfs\0"				\
+	"addip_sta=setenv bootargs ${bootargs} "			\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0"		\
+	"addip=if test -n ${ipdyn};then run addip_dyn;"		\
+		"else run addip_sta;fi\0"				\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
+	"addtty=setenv bootargs ${bootargs}"				\
+		" console=${consoledev},${baudrate}n8\0"		\
+	"addmisc=setenv bootargs ${bootargs} ${misc}\0"		\
+	"addmem=setenv bootargs ${bootargs} mem=${memory}\0"		\
+	"consoledev=ttyS0\0"						\
+	"loadaddr=c0000014\0"						\
+	"memory=32M\0"							\
+	"kernel_addr_r=c0700000\0"					\
+	"hostname=" __stringify(CONFIG_HOSTNAME) "\0"			\
+	"bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0"		\
+	"ramdisk_file=" __stringify(CONFIG_HOSTNAME) "/image.ext2\0"	\
+	"flash_self=run ramargs addip addtty addmtd addmisc addmem;"	\
+			"bootm ${kernel_addr_r}\0"			\
+	"flash_nfs=run nfsargs addip addtty addmtd addmisc addmem;"	\
+		"bootm ${kernel_addr}\0"				\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
+		"run nfsargs addip addtty addmtd addmisc addmem;"	\
+		"bootm ${kernel_addr_r}\0"				\
+	"net_rfsb=tftp ${kernel_addr_r} ${bootfile}; "			\
+		"run rfsbargs addip addtty addmtd addmisc addmem; "	\
+		"bootm ${kernel_addr_r}\0"				\
+	"net_testrfs=tftp ${kernel_addr_r} ${bootfile}; "		\
+		"run testrfsargs addip addtty addmtd addmisc addmem; "	\
+		"bootm ${kernel_addr_r}\0"				\
+	"net_self_load=tftp ${kernel_addr_r} ${bootfile};"		\
+		"tftp ${ramdisk_addr_r} ${ramdisk_file};\0"		\
+	"nand_nand=ubi part nand0,${as};ubifsmount ubi:rootfs;"		\
+		"ubifsload ${kernel_addr_r} /boot/uImage;"		\
+		"ubifsumount; run nandargs addip addtty "		\
+		"addmtd addmisc addmem;clrlogo;"			\
+		"bootm ${kernel_addr_r}\0"				\
+	"nand_nandrw=ubi part nand0,${as};ubifsmount ubi:rootfs;"	\
+		"ubifsload ${kernel_addr_r} /boot/uImage;"		\
+		"ubifsumount; run nandrwargs addip addtty "		\
+		"addmtd addmisc addmem;clrlogo;"			\
+		"bootm ${kernel_addr_r}\0"				\
+	"net_nandrw=tftp ${kernel_addr_r} ${bootfile}; run nandrwargs"	\
+		" addip addtty addmtd addmisc addmem;"			\
+		"clrlogo;bootm ${kernel_addr_r}\0"			\
+	"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0"		\
+	"load_magic=if sf probe 0;then sf "				\
+		"read c0000000 0x10000 0x60000;fi\0"			\
+	"load_nand=ubi part nand0,${as};ubifsmount ubi:rootfs;"		\
+		"if ubifsload c0000014 /boot/u-boot.bin;"		\
+		"then mw c0000008 ${filesize};else echo Error reading"	\
+		" u-boot from nand!;fi\0"				\
+	"load_net=if sf probe 0;then sf read c0000000 0x10000 "	\
+		"0x60000;tftp c0000014 ${u-boot};"			\
+		"mw c0000008 ${filesize};fi\0"				\
+	"upd=if sf probe 0;then sf erase 10000 60000;"			\
+		"sf write c0000000 10000 60000;fi\0"			\
+	"ublupdate=if tftp C0700000 ${ublname};then sf probe 0; "	\
+		"sf erase 0 10000;"					\
+		"sf write 0xc0700000 0 ${filesize};fi\0"		\
+	"ubootupd_net=if run load_net;then echo Updating u-boot;"	\
+		"if run upd; then echo U-Boot updated;"		\
+			"else echo Error updating u-boot !;"		\
+			"echo Board without bootloader !!;"		\
+		"fi;"							\
+		"else echo U-Boot not downloaded..exiting;fi\0"	\
+	"ubootupd_nand=echo run load_magic,run load_nand,run upd;\0"	\
+	"bootcmd=run tempmac;run net_testrfs\0"
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/eb_cpu5282.h b/qemu/roms/u-boot/include/configs/eb_cpu5282.h
new file mode 100644
index 000000000..bdca70587
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/eb_cpu5282.h
@@ -0,0 +1,293 @@
+/*
+ * Configuation settings for the BuS EB+CPU5283 boards (aka EB+MCF-EV123)
+ *
+ * (C) Copyright 2005-2009 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CONFIG_EB_CPU5282_H_
+#define _CONFIG_EB_CPU5282_H_
+
+#undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP
+
+/*----------------------------------------------------------------------*
+ * High Level Configuration Options (easy to change)                    *
+ *----------------------------------------------------------------------*/
+
+#define	CONFIG_MCF52x2			/* define processor family */
+#define CONFIG_M5282			/* define processor type */
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT		(0)
+#define CONFIG_BAUDRATE			115200
+
+#undef	CONFIG_MONITOR_IS_IN_RAM		/* starts uboot direct */
+
+#define CONFIG_BOOTCOMMAND "printenv"
+
+/*----------------------------------------------------------------------*
+ * Options								*
+ *----------------------------------------------------------------------*/
+
+#define CONFIG_BOOT_RETRY_TIME	-1
+#define CONFIG_RESET_TO_RETRY
+#define CONFIG_SPLASH_SCREEN
+
+#define CONFIG_HW_WATCHDOG
+
+#define CONFIG_STATUS_LED
+#define CONFIG_BOARD_SPECIFIC_LED
+#define STATUS_LED_ACTIVE		0
+#define STATUS_LED_BIT			0x0008	/* Timer7 GPIO */
+#define STATUS_LED_BOOT			0
+#define STATUS_LED_PERIOD		(CONFIG_SYS_HZ / 2)
+#define STATUS_LED_STATE		STATUS_LED_OFF
+
+/*----------------------------------------------------------------------*
+ * Configuration for environment					*
+ * Environment is in the second sector of the first 256k of flash	*
+ *----------------------------------------------------------------------*/
+
+#define CONFIG_ENV_ADDR		0xFF040000
+#define CONFIG_ENV_SECT_SIZE	0x00020000
+#define CONFIG_ENV_IS_IN_FLASH	1
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_CMDLINE_EDITING
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_LOADB
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_LED
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+
+#define CONFIG_MCFTMR
+
+#define CONFIG_BOOTDELAY	5
+#define CONFIG_SYS_PROMPT	"\nEB+CPU5282> "
+#define	CONFIG_SYS_LONGHELP	1
+
+#define	CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE 	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define	CONFIG_SYS_MAXARGS	16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_LOAD_ADDR		0x20000
+
+#define CONFIG_SYS_MEMTEST_START	0x100000
+#define CONFIG_SYS_MEMTEST_END		0x400000
+/*#define CONFIG_SYS_DRAM_TEST		1 */
+#undef CONFIG_SYS_DRAM_TEST
+
+/*----------------------------------------------------------------------*
+ * Clock and PLL Configuration						*
+ *----------------------------------------------------------------------*/
+#define	CONFIG_SYS_CLK			80000000      /* 8MHz * 8 */
+
+/* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */
+
+#define CONFIG_SYS_MFD		0x02	/* PLL Multiplication Factor Devider */
+#define CONFIG_SYS_RFD		0x00	/* PLL Reduce Frecuency Devider */
+
+/*----------------------------------------------------------------------*
+ * Network								*
+ *----------------------------------------------------------------------*/
+
+#define CONFIG_MCFFEC
+#define CONFIG_MII			1
+#define CONFIG_MII_INIT			1
+#define CONFIG_SYS_DISCOVER_PHY
+#define CONFIG_SYS_RX_ETH_BUFFER	8
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+
+#define CONFIG_SYS_FEC0_PINMUX		0
+#define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
+#define MCFFEC_TOUT_LOOP		50000
+
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
+
+/*-------------------------------------------------------------------------
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ *-----------------------------------------------------------------------*/
+
+#define	CONFIG_SYS_MBAR			0x40000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ *-----------------------------------------------------------------------*/
+
+#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x10000
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE0		0x00000000
+#define	CONFIG_SYS_SDRAM_SIZE0		16	/* SDRAM size in MB */
+
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_SDRAM_BASE0
+#define	CONFIG_SYS_SDRAM_SIZE		CONFIG_SYS_SDRAM_SIZE0
+
+#define CONFIG_SYS_MONITOR_LEN		0x20000
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define	CONFIG_SYS_BOOTMAPSZ	(8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_FLASH_SHOW_PROGRESS	45
+
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
+#define	CONFIG_SYS_INT_FLASH_BASE	0xF0000000
+#define CONFIG_SYS_INT_FLASH_ENABLE	0x21
+
+#define	CONFIG_SYS_MAX_FLASH_SECT	128
+#define	CONFIG_SYS_MAX_FLASH_BANKS	1
+#define	CONFIG_SYS_FLASH_ERASE_TOUT	10000000
+#define	CONFIG_SYS_FLASH_PROTECTION
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_SIZE		16*1024*1024
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16
+
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV + CF_CACR_DCM)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_DISD | \
+					 CF_CACR_CEIB | CF_CACR_DBWE | \
+					 CF_CACR_EUSP)
+
+/*-----------------------------------------------------------------------
+ * Memory bank definitions
+ */
+
+#define CONFIG_SYS_CS0_BASE		0xFF000000
+#define CONFIG_SYS_CS0_CTRL		0x00001980
+#define CONFIG_SYS_CS0_MASK		0x00FF0001
+
+#define CONFIG_SYS_CS2_BASE		0xE0000000
+#define CONFIG_SYS_CS2_CTRL		0x00001980
+#define CONFIG_SYS_CS2_MASK		0x000F0001
+
+#define CONFIG_SYS_CS3_BASE		0xE0100000
+#define CONFIG_SYS_CS3_CTRL		0x00001980
+#define CONFIG_SYS_CS3_MASK		0x000F0001
+
+/*-----------------------------------------------------------------------
+ * Port configuration
+ */
+#define CONFIG_SYS_PACNT		0x0000000	/* Port A D[31:24] */
+#define CONFIG_SYS_PADDR		0x0000000
+#define CONFIG_SYS_PADAT		0x0000000
+
+#define CONFIG_SYS_PBCNT		0x0000000	/* Port B D[23:16] */
+#define CONFIG_SYS_PBDDR		0x0000000
+#define CONFIG_SYS_PBDAT		0x0000000
+
+#define CONFIG_SYS_PCCNT		0x0000000	/* Port C D[15:08] */
+#define CONFIG_SYS_PCDDR		0x0000000
+#define CONFIG_SYS_PCDAT		0x0000000
+
+#define CONFIG_SYS_PDCNT		0x0000000	/* Port D D[07:00] */
+#define CONFIG_SYS_PCDDR		0x0000000
+#define CONFIG_SYS_PCDAT		0x0000000
+
+#define CONFIG_SYS_PASPAR		0x0F0F
+#define CONFIG_SYS_PEHLPAR		0xC0
+#define CONFIG_SYS_PUAPAR		0x0F
+#define CONFIG_SYS_DDRUA		0x05
+#define CONFIG_SYS_PJPAR		0xFF
+
+/*-----------------------------------------------------------------------
+ * I2C
+ */
+
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x00000300
+#define CONFIG_SYS_IMMR			CONFIG_SYS_MBAR
+
+#define CONFIG_SYS_FSL_I2C_SPEED	100000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0
+
+#ifdef CONFIG_CMD_DATE
+#define CONFIG_RTC_DS1338
+#define CONFIG_I2C_RTC_ADDR		0x68
+#endif
+
+/*-----------------------------------------------------------------------
+ * VIDEO configuration
+ */
+
+#define CONFIG_VIDEO
+
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO_VCXK			1
+
+#define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN	2
+#define	CONFIG_SYS_VCXK_DOUBLEBUFFERED		1
+#define CONFIG_SYS_VCXK_BASE			CONFIG_SYS_CS2_BASE
+
+#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT	MCFGPTB_GPTPORT
+#define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR		MCFGPTB_GPTDDR
+#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN		0x0001
+
+#define CONFIG_SYS_VCXK_ENABLE_PORT		MCFGPTB_GPTPORT
+#define CONFIG_SYS_VCXK_ENABLE_DDR		MCFGPTB_GPTDDR
+#define CONFIG_SYS_VCXK_ENABLE_PIN		0x0002
+
+#define CONFIG_SYS_VCXK_REQUEST_PORT		MCFGPTB_GPTPORT
+#define CONFIG_SYS_VCXK_REQUEST_DDR		MCFGPTB_GPTDDR
+#define CONFIG_SYS_VCXK_REQUEST_PIN		0x0004
+
+#define CONFIG_SYS_VCXK_INVERT_PORT		MCFGPIO_PORTE
+#define CONFIG_SYS_VCXK_INVERT_DDR		MCFGPIO_DDRE
+#define CONFIG_SYS_VCXK_INVERT_PIN		MCFGPIO_PORT2
+
+#endif /* CONFIG_VIDEO */
+#endif	/* _CONFIG_M5282EVB_H */
+/*---------------------------------------------------------------------*/
diff --git a/qemu/roms/u-boot/include/configs/eb_cpux9k2.h b/qemu/roms/u-boot/include/configs/eb_cpux9k2.h
new file mode 100644
index 000000000..f7e70aa57
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/eb_cpux9k2.h
@@ -0,0 +1,404 @@
+/*
+ * (C) Copyright 2008-2009
+ * BuS Elektronik GmbH & Co. KG <www.bus-elektronik.de>
+ * Jens Scharsig <esw@bus-elektronik.de>
+ *
+ * Configuation settings for the EB+CPUx9K2 board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CONFIG_EB_CPUx9K2_H_
+#define _CONFIG_EB_CPUx9K2_H_
+
+/*--------------------------------------------------------------------------*/
+
+#define CONFIG_AT91RM9200		/* It's an Atmel AT91RM9200 SoC	*/
+#define CONFIG_EB_CPUX9K2		/* on an EP+CPUX9K2 Board	*/
+#define USE_920T_MMU
+
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_IDENT_STRING	" on EB+CPUx9K2"
+
+#include <asm/hardware.h>	/* needed for port definitions */
+
+#define CONFIG_MISC_INIT_R
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define MACH_TYPE_EB_CPUX9K2		1977
+#define CONFIG_MACH_TYPE		MACH_TYPE_EB_CPUX9K2
+
+#define CONFIG_SYS_CACHELINE_SIZE	32
+#define CONFIG_SYS_DCACHE_OFF
+
+/*--------------------------------------------------------------------------*/
+#ifndef CONFIG_RAMBOOT
+#define CONFIG_SYS_TEXT_BASE		0x00000000
+#else
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_TEXT_BASE		0x21800000
+#endif
+#define CONFIG_SYS_LOAD_ADDR		0x21000000  /* default load address */
+#define CONFIG_STANDALONE_LOAD_ADDR	0x21000000
+
+#define CONFIG_BOOT_RETRY_TIME		30
+#define CONFIG_CMDLINE_EDITING
+
+#define CONFIG_SYS_PROMPT	"U-Boot> "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE	512		/* Console I/O Buffer Size */
+#define CONFIG_SYS_MAXARGS	32		/* max number of command args */
+#define CONFIG_SYS_PBSIZE	\
+	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+
+/*
+ * ARM asynchronous clock
+ */
+
+#define AT91C_MAIN_CLOCK	179404800	/* from 12.288 MHz * 73 / 5 */
+#define AT91C_MASTER_CLOCK	(AT91C_MAIN_CLOCK / 3)
+#define CONFIG_SYS_HZ_CLOCK 	(AT91C_MASTER_CLOCK / 2)
+
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock */
+
+#define CONFIG_CMDLINE_TAG		1
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+
+#define CONFIG_SYS_USE_MAIN_OSCILLATOR	1
+/* flash */
+#define CONFIG_SYS_EBI_CFGR_VAL		0x00000000
+#define CONFIG_SYS_SMC_CSR0_VAL		0x00003284 /* 16bit, 2 TDF, 4 WS */
+
+/* clocks */
+#define CONFIG_SYS_PLLAR_VAL		0x20483E05 /* 179.4048 MHz for PCK */
+#define CONFIG_SYS_PLLBR_VAL		0x104C3E0A /* 47.3088 MHz (for USB) */
+#define CONFIG_SYS_MCKR_VAL		0x00000202 /* PCK/3 = MCK Clock */
+
+/*
+ * Size of malloc() pool
+ */
+
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+
+/*
+ * sdram
+ */
+
+#define CONFIG_NR_DRAM_BANKS		1
+
+#define CONFIG_SYS_SDRAM_BASE		0x20000000
+#define CONFIG_SYS_SDRAM_SIZE		0x04000000  /* 64 megs */
+#define CONFIG_SYS_INIT_SP_ADDR		0x00204000  /* use internal SRAM */
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
+					CONFIG_SYS_SDRAM_SIZE - 0x00400000 - \
+					CONFIG_SYS_MALLOC_LEN)
+
+#define CONFIG_SYS_PIOC_ASR_VAL		0xFFFF0000 /* PIOC as D16/D31 */
+#define CONFIG_SYS_PIOC_BSR_VAL		0x00000000
+#define CONFIG_SYS_PIOC_PDR_VAL		0xFFFF0000
+#define CONFIG_SYS_EBI_CSA_VAL		0x00000002 /* CS1=SDRAM */
+#define CONFIG_SYS_SDRC_CR_VAL		0x2188c159 /* set up the SDRAM */
+#define CONFIG_SYS_SDRAM		0x20000000 /* address of the SDRAM */
+#define CONFIG_SYS_SDRAM1		0x20000080 /* address of the SDRAM */
+#define CONFIG_SYS_SDRAM_VAL		0x00000000 /* value written to SDRAM */
+#define CONFIG_SYS_SDRC_MR_VAL		0x00000002 /* Precharge All */
+#define CONFIG_SYS_SDRC_MR_VAL1		0x00000004 /* refresh */
+#define CONFIG_SYS_SDRC_MR_VAL2		0x00000003 /* Load Mode Register */
+#define CONFIG_SYS_SDRC_MR_VAL3		0x00000000 /* Normal Mode */
+#define CONFIG_SYS_SDRC_TR_VAL		0x000002E0 /* Write refresh rate */
+
+/*
+ * Command line configuration
+ */
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BMP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_PING
+#define CONFIG_I2C_CMD_TREE
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_UBIFS
+
+#define CONFIG_SYS_LONGHELP
+
+/*
+ * MTD defines
+ */
+
+#define CONFIG_FLASH_CFI_MTD
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+
+#define MTDIDS_DEFAULT		"nor0=physmap-flash.0,nand0=atmel_nand"
+#define MTDPARTS_DEFAULT	"mtdparts="				\
+					"physmap-flash.0:"		\
+						"512k(U-Boot),"		\
+						"128k(Env),"		\
+						"128k(Splash),"		\
+						"4M(Kernel),"		\
+						"384k(MiniFS),"		\
+						"-(FS)"			\
+					";"				\
+					"atmel_nand:"			\
+						"1M(emergency),"	\
+						"-(data)"
+/*
+ * Hardware drivers
+ */
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_AT91C_PQFP_UHPBUG
+#define CONFIG_USB_STORAGE
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+#define CONFIG_EFI_PARTITION
+
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	1
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00300000
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91rm9200"
+
+/*
+ * UART/CONSOLE
+ */
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE	ATMEL_BASE_DBGU
+#define CONFIG_USART_ID		0/* ignored in arm */
+
+/*
+ * network
+ */
+
+#define CONFIG_NET_RETRY_COUNT		10
+#define CONFIG_RESET_PHY_R		1
+
+#define CONFIG_DRIVER_AT91EMAC		1
+#define CONFIG_DRIVER_AT91EMAC_QUIET	1
+#define CONFIG_SYS_RX_ETH_BUFFER	8
+#define CONFIG_MII			1
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * I2C-Bus
+ */
+
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED	50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0
+
+/* Software  I2C driver configuration */
+
+#define AT91_PIN_SDA			(1<<25)		/* AT91C_PIO_PA25 */
+#define AT91_PIN_SCL			(1<<26)		/* AT91C_PIO_PA26 */
+
+#define CONFIG_SYS_I2C_INIT_BOARD
+
+#define I2C_INIT	i2c_init_board();
+#define I2C_ACTIVE	writel(ATMEL_PMX_AA_TWD, &pio->pioa.mddr);
+#define I2C_TRISTATE	writel(ATMEL_PMX_AA_TWD, &pio->pioa.mder);
+#define I2C_READ	((readl(&pio->pioa.pdsr) & ATMEL_PMX_AA_TWD) != 0)
+#define I2C_SDA(bit)						\
+	if (bit)						\
+		writel(ATMEL_PMX_AA_TWD, &pio->pioa.sodr);	\
+	else							\
+		writel(ATMEL_PMX_AA_TWD, &pio->pioa.codr);
+#define I2C_SCL(bit)						\
+	if (bit)						\
+		writel(ATMEL_PMX_AA_TWCK, &pio->pioa.sodr);	\
+	else							\
+		writel(ATMEL_PMX_AA_TWCK, &pio->pioa.codr);
+
+#define I2C_DELAY	udelay(2500000/CONFIG_SYS_I2C_SOFT_SPEED)
+
+/* I2C-RTC */
+
+#ifdef CONFIG_CMD_DATE
+#define CONFIG_RTC_DS1338
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68
+#endif
+
+/* EEPROM */
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+
+/* FLASH organization */
+
+/*  NOR-FLASH */
+#define CONFIG_FLASH_SHOW_PROGRESS	45
+
+#define CONFIG_FLASH_CFI_DRIVER	1
+
+#define PHYS_FLASH_1			0x10000000
+#define PHYS_FLASH_SIZE			0x01000000  /* 16 megs main flash */
+#define CONFIG_SYS_FLASH_CFI		1
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+
+#define CONFIG_SYS_FLASH_PROTECTION	1
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	512
+#define CONFIG_SYS_FLASH_ERASE_TOUT	6000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	2000
+
+/* NAND */
+
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CONFIG_SYS_NAND_DBW_8		1
+
+/* Status LED's */
+
+#define CONFIG_STATUS_LED		1
+#define CONFIG_BOARD_SPECIFIC_LED	1
+
+#define STATUS_LED_BOOT			1
+#define STATUS_LED_ACTIVE		0
+
+#define STATUS_LED_BIT			1	/* AT91C_PIO_PD0 green LED */
+#define STATUS_LED_PERIOD		(CONFIG_SYS_HZ / 2)
+#define STATUS_LED_STATE 		STATUS_LED_OFF		/* BLINKING */
+#define STATUS_LED_BIT1			2	/* AT91C_PIO_PD1  red LED */
+#define STATUS_LED_STATE1		STATUS_LED_ON		/* BLINKING */
+#define STATUS_LED_PERIOD1		(CONFIG_SYS_HZ / 4)
+
+#define	CONFIG_VIDEO			1
+
+/* Options */
+
+#ifdef CONFIG_VIDEO
+
+#define CONFIG_VIDEO_VCXK			1
+
+#define CONFIG_SPLASH_SCREEN			1
+
+#define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN	4
+#define CONFIG_SYS_VCXK_BASE	0x30000000
+
+#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN		(1<<3)
+#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT	piob
+#define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR		odr
+
+#define CONFIG_SYS_VCXK_ENABLE_PIN		(1<<5)
+#define CONFIG_SYS_VCXK_ENABLE_PORT		piob
+#define CONFIG_SYS_VCXK_ENABLE_DDR		oer
+
+#define CONFIG_SYS_VCXK_REQUEST_PIN		(1<<2)
+#define CONFIG_SYS_VCXK_REQUEST_PORT		piob
+#define CONFIG_SYS_VCXK_REQUEST_DDR		oer
+
+#define CONFIG_SYS_VCXK_INVERT_PIN		(1<<4)
+#define CONFIG_SYS_VCXK_INVERT_PORT		piob
+#define CONFIG_SYS_VCXK_INVERT_DDR		oer
+
+#define CONFIG_SYS_VCXK_RESET_PIN		(1<<6)
+#define CONFIG_SYS_VCXK_RESET_PORT		piob
+#define CONFIG_SYS_VCXK_RESET_DDR		oer
+
+#endif	/* CONFIG_VIDEO */
+
+/* Environment */
+
+#define CONFIG_BOOTDELAY		5
+
+#define CONFIG_ENV_IS_IN_FLASH		1
+#define CONFIG_ENV_ADDR			(PHYS_FLASH_1 + 0x80000)
+#define CONFIG_ENV_SIZE			0x20000 /* sectors are 128K here */
+
+#define CONFIG_BAUDRATE 		115200
+
+#define CONFIG_BOOTCOMMAND		"run nfsboot"
+
+#define CONFIG_NFSBOOTCOMMAND 						\
+		"dhcp $(copy_addr) uImage_cpux9k2;"			\
+		"run bootargsdefaults;"					\
+		"set bootargs $(bootargs) boot=nfs "			\
+		";echo $(bootargs)"					\
+	";bootm"
+
+#define CONFIG_EXTRA_ENV_SETTINGS 					\
+	"displaywidth=256\0"						\
+	"displayheight=512\0"						\
+	"displaybsteps=1023\0"						\
+	"ubootaddr=10000000\0"						\
+	"splashimage=100A0000\0"					\
+	"kerneladdr=100C0000\0"						\
+	"kernelsize=00400000\0"						\
+	"rootfsaddr=10520000\0"						\
+	"copy_addr=21200000\0"						\
+	"rootfssize=00AE0000\0"						\
+	"mtdids=" MTDIDS_DEFAULT "\0"					\
+	"mtdparts=" MTDPARTS_DEFAULT "\0"				\
+	"bootargsdefaults=set bootargs "				\
+		"console=ttyS0,115200 "					\
+		"video=vcxk_fb:xres:${displaywidth},"			\
+			"yres:${displayheight},"			\
+			"bres:${displaybsteps} "			\
+		"mem=62M "						\
+		"panic=10 "						\
+		"uboot=\\\"${ver}\\\" "					\
+		"\0"							\
+	"update_kernel=protect off $(kerneladdr) +$(kernelsize);"	\
+		"dhcp $(copy_addr) uImage_cpux9k2;"			\
+		"erase $(kerneladdr) +$(kernelsize);"			\
+		"cp.b $(fileaddr) $(kerneladdr) $(filesize);"		\
+		"protect on $(kerneladdr) +$(kernelsize)"		\
+		"\0"							\
+	"update_root=protect off $(rootfsaddr) +$(rootfssize);"		\
+		"dhcp $(copy_addr) rfs;"				\
+		"erase $(rootfsaddr) +$(rootfssize);"			\
+		"cp.b $(fileaddr) $(rootfsaddr) $(filesize);"		\
+		"\0"							\
+	"update_uboot=protect off 10000000 1007FFFF;"			\
+		"dhcp $(copy_addr) u-boot_eb_cpux9k2;"			\
+		"erase 10000000 1007FFFF;"				\
+		"cp.b $(fileaddr) $(ubootaddr) $(filesize);"		\
+		"protect on 10000000 1007FFFF;reset\0"			\
+	"update_splash=protect off $(splashimage) +20000;"		\
+		"dhcp $(copy_addr) splash_eb_cpux9k2.bmp;"		\
+		"erase $(splashimage) +20000;"				\
+		"cp.b $(fileaddr) $(splashimage) $(filesize);"		\
+		"protect on $(splashimage) +20000;reset\0"		\
+	"emergency=run bootargsdefaults;"				\
+		"set bootargs $(bootargs) root=initramfs boot=emergency " \
+		";bootm $(kerneladdr)\0"				\
+	"netemergency=run bootargsdefaults;"				\
+		"dhcp $(copy_addr) uImage_cpux9k2;"			\
+		"set bootargs $(bootargs) root=initramfs boot=emergency " \
+		";bootm $(copy_addr)\0"					\
+	"norboot=run bootargsdefaults;"					\
+		"set bootargs $(bootargs) root=initramfs boot=local "	\
+		";bootm $(kerneladdr)\0"				\
+	"nandboot=run bootargsdefaults;"				\
+		"set bootargs $(bootargs) root=initramfs boot=nand "	\
+		";bootm $(kerneladdr)\0"				\
+	" "
+
+/*--------------------------------------------------------------------------*/
+
+#endif
+
+/* EOF */
diff --git a/qemu/roms/u-boot/include/configs/ebony.h b/qemu/roms/u-boot/include/configs/ebony.h
new file mode 100644
index 000000000..3f0ad6973
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/ebony.h
@@ -0,0 +1,174 @@
+/*
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/************************************************************************
+ * board/config_EBONY.h - configuration for AMCC 440GP Ref (Ebony)
+ ***********************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_EBONY		1	    /* Board is ebony		*/
+#define CONFIG_440GP		1	    /* Specifc GP support	*/
+#define CONFIG_440		1	    /* ... PPC440 family	*/
+#define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_early_init_f	*/
+#define CONFIG_SYS_CLK_FREQ	33333333    /* external freq to pll	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
+
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME		ebony
+#include "amcc-common.h"
+
+/*
+ * Define here the location of the environment variables (FLASH or NVRAM).
+ * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
+ *       supported for backward compatibility.
+ */
+#if 1
+#define CONFIG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
+#else
+#define CONFIG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_SDRAM_BASE	    0x00000000	    /* _must_ be 0		*/
+#define CONFIG_SYS_FLASH_BASE	    0xff800000	    /* start of FLASH		*/
+#define CONFIG_SYS_PCI_MEMBASE	    0x80000000	    /* mapped pci memory	*/
+#define CONFIG_SYS_ISRAM_BASE	    0xc0000000	    /* internal SRAM		*/
+#define CONFIG_SYS_PCI_BASE	    0xd0000000	    /* internal PCI regs	*/
+
+#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
+#define CONFIG_SYS_FPGA_BASE	    (CONFIG_SYS_PERIPHERAL_BASE + 0x08300000)
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in internal SRAM)
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_INIT_RAM_ADDR   CONFIG_SYS_ISRAM_BASE  /* Initial RAM address	*/
+#define CONFIG_SYS_INIT_RAM_SIZE    0x2000	    /* Size of used area in RAM	*/
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#define CONFIG_SYS_EXT_SERIAL_CLOCK	(1843200 * 6)	/* Ext clk @ 11.059 MHz */
+
+/*-----------------------------------------------------------------------
+ * NVRAM/RTC
+ *
+ * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
+ * The DS1743 code assumes this condition (i.e. -- it assumes the base
+ * address for the RTC registers is:
+ *
+ *	CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE
+ *
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_NVRAM_SIZE	    (0x2000 - 8)    /* NVRAM size(8k)- RTC regs */
+#define CONFIG_RTC_DS174x	1		    /* DS1743 RTC		*/
+
+#ifdef CONFIG_ENV_IS_IN_NVRAM
+#define CONFIG_ENV_SIZE		0x1000	    /* Size of Environment vars */
+#define CONFIG_ENV_ADDR		\
+	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE)
+#endif /* CONFIG_ENV_IS_IN_NVRAM */
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	3		    /* number of banks	    */
+#define CONFIG_SYS_MAX_FLASH_SECT	32		    /* sectors per device   */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#define CONFIG_SYS_FLASH_ADDR0         0x5555
+#define CONFIG_SYS_FLASH_ADDR1         0x2aaa
+#define CONFIG_SYS_FLASH_WORD_SIZE     unsigned char
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	0x10000	/* size of one complete sector		*/
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
+#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+#endif /* CONFIG_ENV_IS_IN_FLASH */
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CONFIG_SPD_EEPROM	1	/* Use SPD EEPROM for setup	*/
+#define SPD_EEPROM_ADDRESS {0x53,0x52}	/* SPD i2c spd addresses	*/
+#define CONFIG_PROG_SDRAM_TLB	1	/* setup SDRAM TLB's dynamically*/
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
+
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR	(0xa8>>1)
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+/*
+ * Default environment variables
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_AMCC_DEF_ENV						\
+	CONFIG_AMCC_DEF_ENV_POWERPC					\
+	CONFIG_AMCC_DEF_ENV_PPC_OLD					\
+	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
+	"kernel_addr=ff800000\0"					\
+	"ramdisk_addr=ff810000\0"					\
+	""
+
+#define CONFIG_PHY_ADDR		8	/* PHY address			*/
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_PHY1_ADDR	9	/* EMAC1 PHY address		*/
+
+/*
+ * Commands additional to the ones defined in amcc-common.h
+ */
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+/* General PCI */
+#define CONFIG_PCI			            /* include pci support	        */
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_PNP			        /* do pci plug-and-play         */
+#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
+#define CONFIG_SYS_PCI_TARGBASE    0x80000000  /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
+
+/* Board-specific PCI */
+#define CONFIG_SYS_PCI_TARGET_INIT	            /* let board init pci target    */
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe  /* Whatever */
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/eco5pk.h b/qemu/roms/u-boot/include/configs/eco5pk.h
new file mode 100644
index 000000000..49c53e452
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/eco5pk.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (C) 2012 8D Technologies inc.
+ * Based on mt_ventoux.h, original banner below:
+ *
+ * Copyright (C) 2011
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * Copyright (C) 2009 TechNexion Ltd.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "tam3517-common.h"
+
+#undef CONFIG_USB_EHCI
+#undef CONFIG_USB_EHCI_OMAP
+#undef CONFIG_USB_OMAP3
+#undef CONFIG_CMD_USB
+
+/* Our console port is port3 */
+#undef CONFIG_CONS_INDEX
+#undef CONFIG_SYS_NS16550_COM1
+#undef CONFIG_SERIAL1
+
+#define CONFIG_CONS_INDEX	3
+#define CONFIG_SYS_NS16550_COM3	OMAP34XX_UART3
+#define CONFIG_SERIAL3
+
+#define MACH_TYPE_ECO5_PK	4017
+#define CONFIG_MACH_TYPE	MACH_TYPE_ECO5_PK
+
+#define CONFIG_BOOTDELAY	10
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_AUTO_COMPLETE
+
+/*
+ * Miscellaneous configurable options
+ */
+#define V_PROMPT		"ECO5-PK # "
+#define CONFIG_SYS_PROMPT	V_PROMPT
+
+/*
+ * Set its own mtdparts, different from common
+ */
+#undef MTDIDS_DEFAULT
+#undef MTDPARTS_DEFAULT
+#define MTDIDS_DEFAULT		"nand0=omap2-nand.0"
+#define MTDPARTS_DEFAULT	"mtdparts=omap2-nand.0:512k(xloader-nand)," \
+				"1024k(uboot-nand),256k(params-nand)," \
+				"5120k(kernel),-(ubifs)"
+
+/*
+ * The arithmetic in tam3517.h is wrong for us and the kernel gets overwritten.
+ */
+#undef CONFIG_ENV_OFFSET_REDUND
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
+						CONFIG_SYS_ENV_SECT_SIZE)
+
+#define	CONFIG_EXTRA_ENV_SETTINGS	CONFIG_TAM3517_SETTINGS \
+	"install_kernel=if dhcp $bootfile; then nand erase kernel;" \
+				"nand write $fileaddr kernel; fi\0" \
+	"mtdparts="MTDPARTS_DEFAULT"\0" \
+	"serverip=192.168.142.60\0"
+
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/ecovec.h b/qemu/roms/u-boot/include/configs/ecovec.h
new file mode 100644
index 000000000..e26591c14
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/ecovec.h
@@ -0,0 +1,179 @@
+/*
+ * Configuation settings for the Renesas Solutions ECOVEC board
+ *
+ * Copyright (C) 2009 - 2011 Renesas Solutions Corp.
+ * Copyright (C) 2009 Kuninori Morimoto <morimoto.kuninori@renesas.com>
+ * Copyright (C) 2010, 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ECOVEC_H
+#define __ECOVEC_H
+
+/*
+ *  Address      Interface        BusWidth
+ *-----------------------------------------
+ *  0x0000_0000  U-Boot           16bit
+ *  0x0004_0000  Linux romImage   16bit
+ *  0x0014_0000  MTD for Linux    16bit
+ *  0x0400_0000  Internal I/O     16/32bit
+ *  0x0800_0000  DRAM             32bit
+ *  0x1800_0000  MFI              16bit
+ */
+
+#undef DEBUG
+#define CONFIG_CPU_SH7724	1
+#define CONFIG_BOARD_LATE_INIT		1
+#define CONFIG_ECOVEC		1
+
+#define CONFIG_ECOVEC_ROMIMAGE_ADDR 0xA0040000
+#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
+
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_SAVEENV
+
+#define CONFIG_USB_STORAGE
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTARGS		"console=ttySC0,115200"
+
+#define CONFIG_VERSION_VARIABLE
+#undef  CONFIG_SHOW_BOOT_PROGRESS
+
+/* I2C */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SH
+#define CONFIG_SYS_I2C_SLAVE	0x7F
+#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 2
+#define CONFIG_SYS_I2C_SH_BASE0	0xA4470000
+#define CONFIG_SYS_I2C_SH_SPEED0	100000
+#define CONFIG_SYS_I2C_SH_BASE1	0xA4750000
+#define CONFIG_SYS_I2C_SH_SPEED1	100000
+#define CONFIG_SH_I2C_DATA_HIGH	4
+#define CONFIG_SH_I2C_DATA_LOW 	5
+#define CONFIG_SH_I2C_CLOCK  	41666666
+
+/* Ether */
+#define CONFIG_SH_ETHER 1
+#define CONFIG_SH_ETHER_USE_PORT (0)
+#define CONFIG_SH_ETHER_PHY_ADDR (0x1f)
+#define CONFIG_PHY_SMSC 1
+#define CONFIG_PHYLIB
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
+
+/* USB / R8A66597 */
+#define CONFIG_USB_R8A66597_HCD
+#define CONFIG_R8A66597_BASE_ADDR   0xA4D80000
+#define CONFIG_R8A66597_XTAL        0x0000  /* 12MHz */
+#define CONFIG_R8A66597_LDRV        0x8000  /* 3.3V */
+#define CONFIG_R8A66597_ENDIAN      0x0000  /* little */
+#define CONFIG_SUPERH_ON_CHIP_R8A66597
+
+/* undef to save memory	*/
+#define CONFIG_SYS_LONGHELP
+/* Monitor Command Prompt */
+/* Buffer size for input from the Console */
+#define CONFIG_SYS_CBSIZE		256
+/* Buffer size for Console output */
+#define CONFIG_SYS_PBSIZE		256
+/* max args accepted for monitor commands */
+#define CONFIG_SYS_MAXARGS		16
+/* Buffer size for Boot Arguments passed to kernel */
+#define CONFIG_SYS_BARGSIZE	512
+/* List of legal baudrate settings for this board */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE	1
+#define CONFIG_SCIF		1
+#define CONFIG_CONS_SCIF0	1
+
+/* Suppress display of console information at boot */
+#undef  CONFIG_SYS_CONSOLE_INFO_QUIET
+#undef  CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#undef  CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+
+/* SDRAM */
+#define CONFIG_SYS_SDRAM_BASE	(0x88000000)
+#define CONFIG_SYS_SDRAM_SIZE	(256 * 1024 * 1024)
+#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
+
+#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END	 (CONFIG_SYS_MEMTEST_START + 200 * 1024 * 1024)
+/* Enable alternate, more extensive, memory test */
+#undef  CONFIG_SYS_ALT_MEMTEST
+/* Scratch address used by the alternate memory test */
+#undef  CONFIG_SYS_MEMTEST_SCRATCH
+
+/* Enable temporary baudrate change while serial download */
+#undef  CONFIG_SYS_LOADS_BAUD_CHANGE
+
+/* FLASH */
+#define CONFIG_FLASH_CFI_DRIVER 1
+#define CONFIG_SYS_FLASH_CFI
+#undef  CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BASE	(0xA0000000)
+#define CONFIG_SYS_MAX_FLASH_SECT	512
+
+/* if you use all NOR Flash , you change dip-switch. Please see Manual. */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+
+/* Timeout for Flash erase operations (in ms) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(3 * 1000)
+/* Timeout for Flash write operations (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(3 * 1000)
+/* Timeout for Flash set sector lock bit operations (in ms) */
+#define CONFIG_SYS_FLASH_LOCK_TOUT	(3 * 1000)
+/* Timeout for Flash clear lock bit operations (in ms) */
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	(3 * 1000)
+
+/*
+ * Use hardware flash sectors protection instead
+ * of U-Boot software protection
+ */
+#undef  CONFIG_SYS_FLASH_PROTECTION
+#undef  CONFIG_SYS_DIRECT_FLASH_TFTP
+
+/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE)
+/* Monitor size */
+#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
+/* Size of DRAM reserved for malloc() use */
+#define CONFIG_SYS_MALLOC_LEN	(256 * 1024)
+#define CONFIG_SYS_BOOTMAPSZ	(8 * 1024 * 1024)
+
+/* ENV setting */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE	1
+#define CONFIG_ENV_SECT_SIZE	(128 * 1024)
+#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
+/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
+#define CONFIG_ENV_OFFSET	(CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
+
+/* Board Clock */
+#define CONFIG_SYS_CLK_FREQ 41666666
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_TMU_CLK_DIV      4
+
+#endif	/* __ECOVEC_H */
diff --git a/qemu/roms/u-boot/include/configs/edminiv2.h b/qemu/roms/u-boot/include/configs/edminiv2.h
new file mode 100644
index 000000000..8b9f66a29
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/edminiv2.h
@@ -0,0 +1,238 @@
+/*
+ * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
+ *
+ * Based on original Kirkwood support which is
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CONFIG_EDMINIV2_H
+#define _CONFIG_EDMINIV2_H
+
+/*
+ * Version number information
+ */
+
+#define CONFIG_IDENT_STRING	" EDMiniV2"
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+
+#define CONFIG_MARVELL		1
+#define CONFIG_ARM926EJS	1	/* Basic Architecture */
+#define CONFIG_FEROCEON		1	/* CPU Core subversion */
+#define CONFIG_ORION5X		1	/* SOC Family Name */
+#define CONFIG_88F5182		1	/* SOC Name */
+#define CONFIG_MACH_EDMINIV2	1	/* Machine type */
+
+#include <asm/arch/orion5x.h>
+/*
+ * CLKs configurations
+ */
+
+/*
+ * Board-specific values for Orion5x MPP low level init:
+ * - MPPs 12 to 15 are SATA LEDs (mode 5)
+ * - Others are GPIO/unused (mode 3 for MPP0, mode 5 for
+ *   MPP16 to MPP19, mode 0 for others
+ */
+
+#define ORION5X_MPP0_7		0x00000003
+#define ORION5X_MPP8_15		0x55550000
+#define ORION5X_MPP16_23	0x00005555
+
+/*
+ * Board-specific values for Orion5x GPIO low level init:
+ * - GPIO3 is input (RTC interrupt)
+ * - GPIO16 is Power LED control (0 = on, 1 = off)
+ * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16)
+ * - GPIO18 is Power Button status (0 = Released, 1 = Pressed)
+ * - GPIO19 is SATA disk power toggle (toggles on 0-to-1)
+ * - GPIO22 is SATA disk power status ()
+ * - GPIO23 is supply status for SATA disk ()
+ * - GPIO24 is supply control for board (write 1 to power off)
+ * Last GPIO is 25, further bits are supposed to be 0.
+ * Enable mask has ones for INPUT, 0 for OUTPUT.
+ * Default is LED ON, board ON :)
+ */
+
+#define ORION5X_GPIO_OUT_ENABLE		0xfef4f0ca
+#define ORION5X_GPIO_OUT_VALUE		0x00000000
+#define ORION5X_GPIO_IN_POLARITY	0x000000d0
+
+/*
+ * NS16550 Configuration
+ */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_TCLK
+#define CONFIG_SYS_NS16550_COM1		ORION5X_UART0_BASE
+
+/*
+ * Serial Port configuration
+ * The following definitions let you select what serial you want to use
+ * for your console driver.
+ */
+
+#define CONFIG_CONS_INDEX	1	/*Console on UART0 */
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE \
+	{ 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 }
+
+/*
+ * FLASH configuration
+ */
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_LEGACY
+#define CONFIG_SYS_MAX_FLASH_BANKS	1  /* max num of flash banks       */
+#define CONFIG_SYS_MAX_FLASH_SECT	11 /* max num of sects on one chip */
+#define CONFIG_SYS_FLASH_BASE		0xfff80000
+#define CONFIG_SYS_FLASH_SECTSZ \
+	{16384, 8192, 8192, 32768, \
+	 65536, 65536, 65536, 65536, 65536, 65536, 65536}
+
+/* auto boot */
+#define CONFIG_BOOTDELAY	3	/* default enable autoboot */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs  */
+#define CONFIG_INITRD_TAG	1	/* enable INITRD tag */
+#define CONFIG_SETUP_MEMORY_TAGS 1	/* enable memory tag */
+
+#define	CONFIG_SYS_PROMPT	"EDMiniV2> "	/* Command Prompt */
+#define	CONFIG_SYS_CBSIZE	1024	/* Console I/O Buff Size */
+#define	CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE \
+		+sizeof(CONFIG_SYS_PROMPT) + 16)	/* Print Buff */
+/*
+ * Commands configuration - using default command set for now
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_USB
+
+/*
+ * Network
+ */
+
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE				/* Enable Marvell GbE Driver */
+#define CONFIG_MVGBE_PORTS	{1}		/* enable port 0 only */
+#define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION	/* don't randomize MAC */
+#define CONFIG_PHY_BASE_ADR	0x8
+#define CONFIG_RESET_PHY_R	/* use reset_phy() to init mv8831116 PHY */
+#define CONFIG_NETCONSOLE	/* include NetConsole support   */
+#define	CONFIG_MII		/* expose smi ove miiphy interface */
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	/* detect link using phy */
+#define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
+#endif
+
+/*
+ * IDE
+ */
+#ifdef CONFIG_CMD_IDE
+#define __io
+#define CONFIG_IDE_PREINIT
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+/* ED Mini V has an IDE-compatible SATA connector for port 1 */
+#define CONFIG_MVSATA_IDE
+#define CONFIG_MVSATA_IDE_USE_PORT1
+/* Needs byte-swapping for ATA data register */
+#define CONFIG_IDE_SWAP_IO
+/* Data, registers and alternate blocks are at the same offset */
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0100)
+#define CONFIG_SYS_ATA_REG_OFFSET	(0x0100)
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x0100)
+/* Each 8-bit ATA register is aligned to a 4-bytes address */
+#define CONFIG_SYS_ATA_STRIDE		4
+/* Controller supports 48-bits LBA addressing */
+#define CONFIG_LBA48
+/* A single bus, a single device */
+#define CONFIG_SYS_IDE_MAXBUS		1
+#define CONFIG_SYS_IDE_MAXDEVICE	1
+/* ATA registers base is at SATA controller base */
+#define CONFIG_SYS_ATA_BASE_ADDR	ORION5X_SATA_BASE
+/* ATA bus 0 is orion5x port 1 on ED Mini V2 */
+#define CONFIG_SYS_ATA_IDE0_OFFSET	ORION5X_SATA_PORT1_OFFSET
+/* end of IDE defines */
+#endif /* CMD_IDE */
+
+/*
+ * Common USB/EHCI configuration
+ */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI		/* Enable EHCI USB support */
+#define CONFIG_USB_EHCI_MARVELL
+#define ORION5X_USB20_HOST_PORT_BASE ORION5X_USB20_PORT0_BASE
+#define CONFIG_USB_STORAGE
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+#define CONFIG_SUPPORT_VFAT
+#endif /* CONFIG_CMD_USB */
+
+/*
+ * I2C related stuff
+ */
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_I2C_MVTWSI
+#define CONFIG_I2C_MVTWSI_BASE		ORION5X_TWSI_BASE
+#define CONFIG_SYS_I2C_SLAVE		0x0
+#define CONFIG_SYS_I2C_SPEED		100000
+#endif
+
+/*
+ *  Environment variables configurations
+ */
+#define CONFIG_ENV_IS_IN_FLASH		1
+#define CONFIG_ENV_SECT_SIZE		0x2000	/* 16K */
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_OFFSET		0x4000	/* env starts here */
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN	(1024 * 256) /* 256kB for malloc() */
+
+/*
+ * Other required minimal configurations
+ */
+#define CONFIG_CONSOLE_INFO_QUIET	/* some code reduction */
+#define CONFIG_ARCH_CPU_INIT		/* call arch_cpu_init() */
+#define CONFIG_ARCH_MISC_INIT		/* call arch_misc_init() */
+#define CONFIG_DISPLAY_CPUINFO		/* Display cpu info */
+#define CONFIG_NR_DRAM_BANKS		1
+
+#define CONFIG_SYS_LOAD_ADDR		0x00800000
+#define CONFIG_SYS_MEMTEST_START	0x00400000
+#define CONFIG_SYS_MEMTEST_END		0x007fffff
+#define CONFIG_SYS_RESET_ADDRESS	0xffff0000
+#define CONFIG_SYS_MAXARGS		16
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+/* Enable command line editing */
+#define CONFIG_CMDLINE_EDITING
+
+/* provide extensive help */
+#define CONFIG_SYS_LONGHELP
+
+/* additions for new relocation code, must be added to all boards */
+#define CONFIG_SYS_SDRAM_BASE		0
+#define CONFIG_SYS_INIT_SP_ADDR	\
+	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+#endif /* _CONFIG_EDMINIV2_H */
diff --git a/qemu/roms/u-boot/include/configs/enbw_cmc.h b/qemu/roms/u-boot/include/configs/enbw_cmc.h
new file mode 100644
index 000000000..30ca95f02
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/enbw_cmc.h
@@ -0,0 +1,448 @@
+/*
+ * (C) Copyright 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Based on davinci_dvevm.h. Original Copyrights follow:
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Board
+ */
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT 7
+#define CONFIG_USE_NAND
+
+/*
+ * SoC Configuration
+ */
+#define CONFIG_ARM926EJS		/* arm926ejs CPU core */
+#define CONFIG_SOC_DA8XX		/* TI DA8xx SoC */
+#define CONFIG_SOC_DA850		/* TI DA850 SoC */
+#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
+#define CONFIG_SYS_CLK_FREQ		clk_get(DAVINCI_ARM_CLKID)
+#define CONFIG_SYS_OSCIN_FREQ		24000000
+#define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
+#define CONFIG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
+#define CONFIG_DA850_LOWLEVEL
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_SYS_DA850_PLL_INIT
+#define CONFIG_SYS_DA850_DDR_INIT
+#define CONFIG_DA8XX_GPIO
+#define CONFIG_HOSTNAME		enbw_cmc
+
+#define MACH_TYPE_ENBW_CMC	3585
+#define CONFIG_MACH_TYPE	MACH_TYPE_ENBW_CMC
+
+/*
+ * Memory Info
+ */
+#define CONFIG_SYS_MALLOC_LEN	(0x10000 + 1*1024*1024) /* malloc() len */
+#define PHYS_SDRAM_1		DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
+#define PHYS_SDRAM_1_SIZE	(64 << 20) /* SDRAM size 64MB */
+#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
+
+/* memtest start addr */
+#define CONFIG_SYS_MEMTEST_START	(PHYS_SDRAM_1 + 0x2000000)
+
+/* memtest will be run on 16MB */
+#define CONFIG_SYS_MEMTEST_END	(PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
+
+#define CONFIG_NR_DRAM_BANKS	1 /* we have 1 bank of DRAM */
+
+/*
+ * Serial Driver info
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	-4	/* NS16550 register size */
+#define CONFIG_SYS_NS16550_COM1	DAVINCI_UART2_BASE /* Base address of UART2 */
+#define CONFIG_SYS_NS16550_CLK	clk_get(DAVINCI_UART2_CLKID)
+#define CONFIG_CONS_INDEX	1		/* use UART0 for console */
+#define CONFIG_BAUDRATE		115200		/* Default baud rate */
+
+/*
+ * I2C Configuration
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DAVINCI
+#define CONFIG_SYS_DAVINCI_I2C_SPEED		80000
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE   10 /* Bogus, master-only in U-Boot */
+#define CONFIG_SYS_I2C_EXPANDER_ADDR   0x20
+#define CONFIG_CMD_I2C
+
+#define CONFIG_CMD_DTT
+#define CONFIG_DTT_LM75
+#define CONFIG_DTT_SENSORS	{0}	/* Sensor addresses		*/
+#define CONFIG_SYS_DTT_MAX_TEMP	70
+#define CONFIG_SYS_DTT_LOW_TEMP	-30
+#define CONFIG_SYS_DTT_HYSTERESIS	3
+
+/*
+ * SPI Configuration
+ */
+#define CONFIG_DAVINCI_SPI
+#define CONFIG_SYS_SPI_BASE		DAVINCI_SPI1_BASE
+#define CONFIG_SYS_SPI_CLK		clk_get(DAVINCI_SPI1_CLKID)
+#define CONFIG_CMD_SPI
+
+/*
+ * Flash & Environment
+ */
+#ifdef CONFIG_USE_NAND
+#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
+#define CONFIG_SYS_NAND_PAGE_2K
+#define CONFIG_SYS_NAND_CS		3
+#define CONFIG_SYS_NAND_BASE		DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
+#define CONFIG_SYS_NAND_MASK_CLE		0x10
+#define CONFIG_SYS_NAND_MASK_ALE		0x8
+#undef CONFIG_SYS_NAND_HW_ECC
+#define CONFIG_SYS_MAX_NAND_DEVICE	1 /* Max number of NAND devices */
+
+#define MTDIDS_DEFAULT		"nor0=physmap-flash.0,nand0=davinci_nand.1"
+#define MTDPARTS_DEFAULT			\
+	"mtdparts="				\
+		"physmap-flash.0:"		\
+			"512k(U-Boot),"		\
+			"64k(env1),"		\
+			"64k(env2),"		\
+			"-(rest);"		\
+		"davinci_nand.1:"		\
+			"128k(dtb),"		\
+			"3m(kernel),"		\
+			"4m(rootfs),"		\
+			"-(userfs)"
+
+
+#define CONFIG_CMD_MTDPARTS
+
+#endif
+
+/*
+ * Network & Ethernet Configuration
+ */
+#ifdef CONFIG_DRIVER_TI_EMAC
+#define CONFIG_MII
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT	10
+#endif
+
+/*
+ * Flash configuration
+ */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_MTD
+#define CONFIG_SYS_FLASH_BASE           0x60000000
+#define CONFIG_SYS_FLASH_SIZE           0x01000000
+#define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks */
+#define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_MAX_FLASH_SECT       128
+#define CONFIG_FLASH_16BIT              /* Flash is 16-bit */
+
+#define CONFIG_CMD_FLASH
+
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_SYS_MONITOR_LEN	0x80000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + \
+					CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SECT_SIZE	(64 << 10)
+#define CONFIG_ENV_SIZE		(16 << 10)	/* 16 KiB */
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + \
+					CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND		(CONFIG_ENV_SIZE)
+#undef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_DEFAULT_SETTINGS_ADDR	(CONFIG_ENV_ADDR_REDUND + \
+						CONFIG_ENV_SECT_SIZE)
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"u-boot_addr_r=c0000000\0"					\
+	"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0"		\
+	"load=tftp ${u-boot_addr_r} ${u-boot}\0"			\
+	"update=protect off " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};"\
+		"erase " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};"	\
+		"cp.b ${u-boot_addr_r} " __stringify(CONFIG_SYS_FLASH_BASE)	\
+		" ${filesize};"						\
+		"protect on " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize}\0"\
+	"netdev=eth0\0"							\
+	"rootpath=/opt/eldk-arm/arm\0"					\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"kernel_addr_r=c0700000\0"					\
+	"fdt_addr_r=c0600000\0"						\
+	"ramdisk_addr_r=c0b00000\0"					\
+	"fdt_file=" __stringify(CONFIG_HOSTNAME) "/"			\
+		__stringify(CONFIG_HOSTNAME) ".dtb\0"			\
+	"kernel_file=" __stringify(CONFIG_HOSTNAME) "/uImage \0"	\
+	"nand_ld_ramdsk=nand read ${ramdisk_addr_r} 320000 400000\0"	\
+	"nand_ld_kernel=nand read ${kernel_addr_r} 20000 300000\0"	\
+	"nand_ld_fdt=nand read ${fdt_addr_r} 0 2000\0"			\
+	"load_kernel=tftp ${kernel_addr_r} ${kernel_file}\0"		\
+	"load_fdt=tftp ${fdt_addr_r} ${fdt_file}\0"			\
+	"load_nand=run nand_ld_ramdsk nand_ld_kernel nand_ld_fdt\0"	\
+	"addcon=setenv bootargs ${bootargs} console=ttyS2,"		\
+		"${baudrate}n8\0"					\
+	"net_nfs=run load_fdt load_kernel; "				\
+		"run nfsargs addip addcon addmtd addmisc;"		\
+		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
+	"nand_selfnand=run load_nand ramargs addip addcon addmisc;bootm "\
+		"${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"	\
+	"bootcmd=run net_nfs\0"						\
+	"machid=e01\0"							\
+	"key_cmd_0=echo key:   0\0"					\
+	"key_cmd_1=echo key:   1\0"					\
+	"key_cmd_2=echo key:   2\0"					\
+	"key_cmd_3=echo key:   3\0"					\
+	"key_magic_0=0\0"						\
+	"key_magic_1=1\0"						\
+	"key_magic_2=2\0"						\
+	"key_magic_3=3\0"						\
+	"magic_keys=0123\0"						\
+	"hwconfig=switch:lan=on,pwl=off,config=0x60100000\0"		\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
+	"addmisc=setenv bootargs ${bootargs}\0"				\
+	"mtdids=" MTDIDS_DEFAULT "\0"					\
+	"mtdparts=" MTDPARTS_DEFAULT "\0"				\
+	"logversion=2\0"						\
+	"\0"
+
+/*
+ * U-Boot general configuration
+ */
+#define CONFIG_BOOTFILE		"uImage" /* Boot file name */
+#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
+#define CONFIG_SYS_LOAD_ADDR	(PHYS_SDRAM_1 + 0x700000)
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_HWCONFIG
+#define CONFIG_SHOW_BOOT_PROGRESS
+#define CONFIG_BOARD_LATE_INIT
+
+/*
+ * U-Boot commands
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_CACHE
+
+#ifdef CONFIG_CMD_BDI
+#define CONFIG_CLOCKS
+#endif
+
+#ifndef CONFIG_DRIVER_TI_EMAC
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_MII
+#undef CONFIG_CMD_PING
+#endif
+
+#ifdef CONFIG_USE_NAND
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_NAND
+
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_LZO
+#define CONFIG_RBTREE
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#endif
+
+#if !defined(CONFIG_USE_NAND) && \
+	!defined(CONFIG_USE_NOR) && \
+	!defined(CONFIG_USE_SPIFLASH)
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_SIZE		(16 << 10)
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_ENV
+#endif
+
+#define CONFIG_SYS_TEXT_BASE		0x60000000
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_SDRAM_BASE		0xc0000000
+#define CONFIG_SYS_INIT_SP_ADDR		(0x8001ff00)
+
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_PREBOOT	"echo;" \
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+	"echo"
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMC_RESET_PIN	0x04000000
+#define CONFIG_CMC_RESET_TIMEOUT	3
+
+#define CONFIG_HW_WATCHDOG
+#define CONFIG_SYS_WDTTIMERBASE		DAVINCI_TIMER1_BASE
+#define CONFIG_SYS_WDT_PERIOD_LOW	0x0c000000
+#define CONFIG_SYS_WDT_PERIOD_HIGH	0x0
+
+#define CONFIG_CMD_DATE
+#define CONFIG_RTC_DAVINCI
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DAVINCI_MMC
+#define CONFIG_MMC_MBLOCK
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_MMC
+
+/* GPIO */
+#define CONFIG_ENBW_CMC_BOARD_TYPE	57
+#define CONFIG_ENBW_CMC_HW_ID_BIT0	39
+#define CONFIG_ENBW_CMC_HW_ID_BIT1	38
+#define CONFIG_ENBW_CMC_HW_ID_BIT2	35
+
+/* FDT support */
+#define CONFIG_OF_LIBFDT
+
+/* LowLevel Init */
+/* PLL */
+#define CONFIG_SYS_DV_CLKMODE		0
+#define CONFIG_SYS_DA850_PLL0_POSTDIV	0
+#define CONFIG_SYS_DA850_PLL0_PLLDIV1	0x8000
+#define CONFIG_SYS_DA850_PLL0_PLLDIV2	0x8001
+#define CONFIG_SYS_DA850_PLL0_PLLDIV3	0x8002 /* 150MHz */
+#define CONFIG_SYS_DA850_PLL0_PLLDIV4	0x8003
+#define CONFIG_SYS_DA850_PLL0_PLLDIV5	0x8002
+#define CONFIG_SYS_DA850_PLL0_PLLDIV6	CONFIG_SYS_DA850_PLL0_PLLDIV1
+#define CONFIG_SYS_DA850_PLL0_PLLDIV7	0x8005
+
+#define CONFIG_SYS_DA850_PLL1_POSTDIV	1
+#define CONFIG_SYS_DA850_PLL1_PLLDIV1	0x8000
+#define CONFIG_SYS_DA850_PLL1_PLLDIV2	0x8001
+#define CONFIG_SYS_DA850_PLL1_PLLDIV3	0x8002
+
+#define CONFIG_SYS_DA850_PLL0_PLLM	18	/* PLL0 -> 456 MHz */
+#define CONFIG_SYS_DA850_PLL1_PLLM	24	/* PLL1 -> 300 MHz */
+
+/* DDR RAM */
+#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
+			DV_DDR_PHY_EXT_STRBEN   | \
+			(0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
+
+#define CONFIG_SYS_DA850_DDR2_SDBCR (0 | \
+		  (0 << DV_DDR_SDCR_DDR2TERM1_SHIFT) | \
+		  (0 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \
+		  (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
+		  (0x1 << DV_DDR_SDCR_DDREN_SHIFT)	| \
+		  (0x1 << DV_DDR_SDCR_SDRAMEN_SHIFT)	| \
+		  (0x1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT)	| \
+		  (0x1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT)	| \
+		  (0x3 << DV_DDR_SDCR_CL_SHIFT)		| \
+		  (0x2 << DV_DDR_SDCR_IBANK_SHIFT)		| \
+		  (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
+
+#define CONFIG_SYS_DA850_DDR2_SDBCR2 4 /* 13 row address bits */
+
+/*
+ * freq = 150MHz -> t = 7ns
+ */
+#define CONFIG_SYS_DA850_DDR2_SDTIMR (0 | \
+		(0x0d << DV_DDR_SDTMR1_RFC_SHIFT)	| \
+		(1 << DV_DDR_SDTMR1_RP_SHIFT)		| \
+		(1 << DV_DDR_SDTMR1_RCD_SHIFT)		| \
+		(1 << DV_DDR_SDTMR1_WR_SHIFT)		| \
+		(5 << DV_DDR_SDTMR1_RAS_SHIFT)		| \
+		(7 << DV_DDR_SDTMR1_RC_SHIFT)		| \
+		(1 << DV_DDR_SDTMR1_RRD_SHIFT)		| \
+		(readl(&dv_ddr2_regs_ctrl->sdtimr) & 0x4) |  /* Reserved */ \
+		((2 - 1) << DV_DDR_SDTMR1_WTR_SHIFT))
+
+/*
+ * freq = 150MHz -> t=7ns
+ */
+#define CONFIG_SYS_DA850_DDR2_SDTIMR2 (0 | \
+	(readl(&dv_ddr2_regs_ctrl->sdtimr2) & 0x80000000) | /* Reserved */ \
+	(8 << DV_DDR_SDTMR2_RASMAX_SHIFT)		| \
+	(2 << DV_DDR_SDTMR2_XP_SHIFT)			| \
+	(0 << DV_DDR_SDTMR2_ODT_SHIFT)			| \
+	(15 << DV_DDR_SDTMR2_XSNR_SHIFT)		| \
+	(27 << DV_DDR_SDTMR2_XSRD_SHIFT)		| \
+	(0 << DV_DDR_SDTMR2_RTP_SHIFT)			| \
+	(2 << DV_DDR_SDTMR2_CKE_SHIFT))
+
+#define CONFIG_SYS_DA850_DDR2_SDRCR	0x00000407
+#define CONFIG_SYS_DA850_DDR2_PBBPR	0x30
+#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
+					DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
+					DAVINCI_SYSCFG_SUSPSRC_UART2 | \
+					DAVINCI_SYSCFG_SUSPSRC_EMAC |\
+					DAVINCI_SYSCFG_SUSPSRC_I2C)
+
+#define CONFIG_SYS_DA850_CS2CFG	(DAVINCI_ABCR_WSETUP(2)	| \
+				DAVINCI_ABCR_WSTROBE(6)	| \
+				DAVINCI_ABCR_WHOLD(1)	| \
+				DAVINCI_ABCR_RSETUP(2)	| \
+				DAVINCI_ABCR_RSTROBE(6)	| \
+				DAVINCI_ABCR_RHOLD(1)	| \
+				DAVINCI_ABCR_ASIZE_16BIT)
+
+#define CONFIG_SYS_DA850_CS3CFG	(DAVINCI_ABCR_WSETUP(1)	| \
+				DAVINCI_ABCR_WSTROBE(2)	| \
+				DAVINCI_ABCR_WHOLD(1)	| \
+				DAVINCI_ABCR_RSETUP(1)	| \
+				DAVINCI_ABCR_RSTROBE(6)	| \
+				DAVINCI_ABCR_RHOLD(1)	| \
+				DAVINCI_ABCR_ASIZE_8BIT)
+
+/*
+ * NOR Bootconfiguration word:
+ * Method: Direc boot
+ * EMIFA access mode: 16 Bit
+ */
+#define CONFIG_SYS_DV_NOR_BOOT_CFG	(0x11)
+
+#define CONFIG_POST	(CONFIG_SYS_POST_MEMORY)
+#define CONFIG_POST_EXTERNAL_WORD_FUNCS
+#define CONFIG_SYS_POST_WORD_ADDR DAVINCI_RTC_BASE
+#define CONFIG_LOGBUFFER
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+#define CONFIG_BOOTCOUNT_LIMIT
+#define CONFIG_SYS_BOOTCOUNT_ADDR	DAVINCI_RTC_BASE
+#define CONFIG_SYS_BOOTCOUNT_BE
+
+#define CONFIG_SYS_NAND_U_BOOT_DST	0xc0080000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x60004000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x70000
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/ep8248.h b/qemu/roms/u-boot/include/configs/ep8248.h
new file mode 100644
index 000000000..f1af96ddb
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/ep8248.h
@@ -0,0 +1,253 @@
+/*
+ * Copyright (C) 2004 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * U-Boot configuration for Embedded Planet EP8248 boards.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MPC8248
+#define CPU_ID_STR		"MPC8248"
+
+#define CONFIG_EP8248			/* Embedded Planet EP8248 board */
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
+
+/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * Select serial console configuration
+ *
+ * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ */
+#define	CONFIG_CONS_ON_SMC		/* Console is on SMC         */
+#undef  CONFIG_CONS_ON_SCC		/* It's not on SCC           */
+#undef	CONFIG_CONS_NONE		/* It's not on external UART */
+#define CONFIG_CONS_INDEX	1	/* SMC1 is used for console  */
+
+#define CONFIG_SYS_BCSR		0xFA000000
+
+/* Pass open firmware flat device tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+#define OF_TBCLK        (bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH  "/soc/cpm/serial <at> 11a80"
+
+/* Select ethernet configuration */
+#undef	CONFIG_ETHER_ON_SCC		/* Ethernet is not on SCC */
+#define CONFIG_ETHER_ON_FCC		/* Ethernet is on FCC     */
+#undef	CONFIG_ETHER_NONE		/* No external Ethernet   */
+
+#define CONFIG_SYS_CPMFCR_RAMTYPE	0
+#define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
+
+#define CONFIG_HAS_ETH0
+#define CONFIG_ETHER_ON_FCC1		1
+/* - Rx clock is CLK10
+ * - Tx clock is CLK11
+ * - BDs/buffers on 60x bus
+ * - Full duplex
+ */
+#define CONFIG_SYS_CMXFCR_MASK1	(CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
+#define CONFIG_SYS_CMXFCR_VALUE1	(CMXFCR_RF1CS_CLK10 | CMXFCR_TF1CS_CLK11)
+
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETHER_ON_FCC2		1
+/* - Rx clock is CLK13
+ * - Tx clock is CLK14
+ * - BDs/buffers on 60x bus
+ * - Full duplex
+ */
+#define CONFIG_SYS_CMXFCR_MASK2	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+#define CONFIG_SYS_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
+
+#define CONFIG_MII			/* MII PHY management        */
+#define CONFIG_BITBANGMII		/* Bit-banged MDIO interface */
+/*
+ * GPIO pins used for bit-banged MII communications
+ */
+#define MDIO_PORT		0	/* Not used - implemented in BCSR */
+
+#define MDIO_ACTIVE		(*(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFB)
+#define MDIO_TRISTATE		(*(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x04)
+#define MDIO_READ		(*(vu_char *)(CONFIG_SYS_BCSR + 8) & 1)
+
+#define MDIO(bit)		if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x01; \
+				else	*(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFE
+
+#define MDC(bit)		if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x02; \
+				else	*(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFD
+
+#define MIIDELAY		udelay(1)
+
+#ifndef CONFIG_8260_CLKIN
+#define CONFIG_8260_CLKIN	66000000	/* in Hz */
+#endif
+
+#define CONFIG_BAUDRATE		38400
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+#define CONFIG_BOOTCOMMAND	"bootm FF860000"	/* autoboot command */
+#define CONFIG_BOOTARGS		"root=/dev/mtdblock1 rw mtdparts=phys:7M(root),-(root)ro"
+
+#if defined(CONFIG_CMD_KGDB)
+#undef	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
+#define CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
+#undef	CONFIG_KGDB_NONE		/* define if kgdb on something else */
+#define CONFIG_KGDB_INDEX	1	/* which serial channel for kgdb */
+#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port at */
+#endif
+
+#define CONFIG_BZIP2	/* include support for bzip2 compressed images */
+#undef	CONFIG_WATCHDOG			/* disable platform specific watchdog */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size  */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size  */
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
+
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#define CONFIG_SYS_FLASH_BASE		0xFF800000
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max num of sects on one chip */
+
+#define	CONFIG_SYS_DIRECT_FLASH_TFTP
+
+#if defined(CONFIG_CMD_JFFS2)
+#define CONFIG_SYS_JFFS2_FIRST_BANK	0
+#define CONFIG_SYS_JFFS2_NUM_BANKS	CONFIG_SYS_MAX_FLASH_BANKS
+#define CONFIG_SYS_JFFS2_FIRST_SECTOR  0
+#define CONFIG_SYS_JFFS2_LAST_SECTOR   62
+#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
+#define CONFIG_SYS_JFFS_CUSTOM_PART
+#endif
+
+#if defined(CONFIG_CMD_I2C)
+#define CONFIG_HARD_I2C		1	/* To enable I2C support	*/
+#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed			*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F	/* I2C slave address		*/
+#endif
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256KB for Monitor */
+
+#define CONFIG_ENV_IS_IN_FLASH
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	0x20000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#endif /* CONFIG_ENV_IS_IN_FLASH */
+
+#define CONFIG_SYS_DEFAULT_IMMR	0x00010000
+
+#define CONFIG_SYS_IMMR		0xF0000000
+
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/* Hard reset configuration word */
+#define CONFIG_SYS_HRCW_MASTER		0x0C40025A /* Not used - provided by FPGA */
+/* No slaves */
+#define CONFIG_SYS_HRCW_SLAVE1		0
+#define CONFIG_SYS_HRCW_SLAVE2		0
+#define CONFIG_SYS_HRCW_SLAVE3		0
+#define CONFIG_SYS_HRCW_SLAVE4		0
+#define CONFIG_SYS_HRCW_SLAVE5		0
+#define CONFIG_SYS_HRCW_SLAVE6		0
+#define CONFIG_SYS_HRCW_SLAVE7		0
+
+#define CONFIG_SYS_MALLOC_LEN		(4096 << 10)	/* Reserve 4 MB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPUs */
+#if defined(CONFIG_CMD_KGDB)
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+#define CONFIG_SYS_HID0_INIT		0
+#define CONFIG_SYS_HID0_FINAL		(HID0_ICE | HID0_IFEM | HID0_ABE)
+
+#define CONFIG_SYS_HID2		0
+
+#define CONFIG_SYS_SIUMCR		0x01240200
+#define CONFIG_SYS_SYPCR		0xFFFF0683
+#define CONFIG_SYS_BCR			0x00000000
+#define CONFIG_SYS_SCCR		SCCR_DFBRG01
+
+#define CONFIG_SYS_RMR			RMR_CSRE
+#define CONFIG_SYS_TMCNTSC		(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+#define CONFIG_SYS_PISCR		(PISCR_PS|PISCR_PTF|PISCR_PTE)
+#define CONFIG_SYS_RCCR		0
+
+#define CONFIG_SYS_MPTPR		0x1300
+#define CONFIG_SYS_PSDMR		0x82672522
+#define CONFIG_SYS_PSRT		0x4B
+
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_BR		(CONFIG_SYS_SDRAM_BASE | 0x00001841)
+#define CONFIG_SYS_SDRAM_OR		0xFF0030C0
+
+#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | 0x00001801)
+#define CONFIG_SYS_OR0_PRELIM		0xFF8008C2
+#define CONFIG_SYS_BR2_PRELIM		(CONFIG_SYS_BCSR | 0x00000801)
+#define CONFIG_SYS_OR2_PRELIM		0xFFF00864
+
+#define CONFIG_SYS_RESET_ADDRESS	0xC0000000
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/ep8260.h b/qemu/roms/u-boot/include/configs/ep8260.h
new file mode 100644
index 000000000..9cd3054a1
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/ep8260.h
@@ -0,0 +1,744 @@
+/*
+ * (C) Copyright 2002
+ * Frank Panno <fpanno@delphintech.com>, Delphin Technology AG
+ *
+ * This file is based on similar values for other boards found in other
+ * U-Boot config files, and some that I found in the EP8260 manual.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ *
+ * "EP8260 H, V.1.1"
+ *	- 64M 60x Bus SDRAM
+ *	- 32M Local Bus SDRAM
+ *	- 16M Flash (4 x AM29DL323DB90WDI)
+ *	- 128k NVRAM with RTC
+ *
+ * "EP8260 H2, V.1.3" (CONFIG_SYS_EP8260_H2)
+ *	- 300MHz/133MHz/66MHz
+ *	- 64M 60x Bus SDRAM
+ *	- 32M Local Bus SDRAM
+ *	- 32M Flash
+ *	- 128k NVRAM with RTC
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* Define this to enable support the EP8260 H2 version */
+#define CONFIG_SYS_EP8260_H2	1
+/* #undef CONFIG_SYS_EP8260_H2  */
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
+
+#define CONFIG_CPM2		1	/* Has a CPM2 */
+
+/* What is the oscillator's (UX2) frequency in Hz? */
+#define CONFIG_8260_CLKIN  (66 * 1000 * 1000)
+
+/*-----------------------------------------------------------------------
+ * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
+ *-----------------------------------------------------------------------
+ * What should MODCK_H be? It is dependent on the oscillator
+ * frequency, MODCK[1-3], and desired CPM and core frequencies.
+ * Here are some example values (all frequencies are in MHz):
+ *
+ * MODCK_H   MODCK[1-3]	 Osc	CPM    Core
+ * -------   ----------	 ---	---    ----
+ * 0x2	     0x2	 33	133    133
+ * 0x2	     0x3	 33	133    166
+ * 0x2	     0x4	 33	133    200
+ * 0x2	     0x5	 33	133    233
+ * 0x2	     0x6	 33	133    266
+ *
+ * 0x5	     0x5	 66	133    133
+ * 0x5	     0x6	 66	133    166
+ * 0x5	     0x7	 66	133    200 *
+ * 0x6	     0x0	 66	133    233
+ * 0x6	     0x1	 66	133    266
+ * 0x6	     0x2	 66	133    300
+ */
+#ifdef CONFIG_SYS_EP8260_H2
+#define CONFIG_SYS_SBC_MODCK_H  (HRCW_MODCK_H0110)
+#else
+#define CONFIG_SYS_SBC_MODCK_H  (HRCW_MODCK_H0110)
+#endif
+
+/* Define this if you want to boot from 0x00000100. If you don't define
+ * this, you will need to program the bootloader to 0xfff00000, and
+ * get the hardware reset config words at 0xfe000000. The simplest
+ * way to do that is to program the bootloader at both addresses.
+ * It is suggested that you just let U-Boot live at 0x00000000.
+ */
+/* #define CONFIG_SYS_SBC_BOOT_LOW 1 */	/* only for HRCW */
+/* #undef CONFIG_SYS_SBC_BOOT_LOW */
+
+/* The reset command will not work as expected if the reset address does
+ * not point to the correct address.
+ */
+
+#define CONFIG_SYS_RESET_ADDRESS	0xFFF00100
+
+/* What should the base address of the main FLASH be and how big is
+ * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/ep8260/config.mk
+ * The main FLASH is whichever is connected to *CS0. U-Boot expects
+ * this to be the SIMM.
+ */
+#ifdef CONFIG_SYS_EP8260_H2
+#define CONFIG_SYS_FLASH0_BASE 0xFE000000
+#define CONFIG_SYS_FLASH0_SIZE 32
+#else
+#define CONFIG_SYS_FLASH0_BASE 0xFF000000
+#define CONFIG_SYS_FLASH0_SIZE 16
+#endif
+
+/* What should the base address of the secondary FLASH be and how big
+ * is it (in Mbytes)? The secondary FLASH is whichever is connected
+ * to *CS6. U-Boot expects this to be the on board FLASH. If you don't
+ * want it enabled, don't define these constants.
+ */
+#define CONFIG_SYS_FLASH1_BASE 0
+#define CONFIG_SYS_FLASH1_SIZE 0
+#undef CONFIG_SYS_FLASH1_BASE
+#undef CONFIG_SYS_FLASH1_SIZE
+
+/* What should be the base address of SDRAM DIMM (60x bus) and how big is
+ * it (in Mbytes)?
+*/
+#define CONFIG_SYS_SDRAM0_BASE 0x00000000
+#define CONFIG_SYS_SDRAM0_SIZE 64
+
+/* define CONFIG_SYS_LSDRAM if you want to enable the 32M SDRAM on the
+ * local bus (8260 local bus is NOT cacheable!)
+*/
+/* #define CONFIG_SYS_LSDRAM */
+#undef CONFIG_SYS_LSDRAM
+
+#ifdef CONFIG_SYS_LSDRAM
+/* What should be the base address of SDRAM DIMM (local bus) and how big is
+ * it (in Mbytes)?
+*/
+  #define CONFIG_SYS_SDRAM1_BASE 0x04000000
+  #define CONFIG_SYS_SDRAM1_SIZE 32
+#else
+  #define CONFIG_SYS_SDRAM1_BASE 0
+  #define CONFIG_SYS_SDRAM1_SIZE 0
+  #undef CONFIG_SYS_SDRAM1_BASE
+  #undef CONFIG_SYS_SDRAM1_SIZE
+#endif /* CONFIG_SYS_LSDRAM */
+
+/* What should be the base address of NVRAM and how big is
+ * it (in Bytes)
+ */
+#define CONFIG_SYS_NVRAM_BASE_ADDR  0xFA080000
+#define CONFIG_SYS_NVRAM_SIZE       (128*1024)-16
+
+/* The RTC is a Dallas DS1556
+ */
+#define CONFIG_RTC_DS1556
+
+/* What should be the base address of the LEDs and switch S0?
+ * If you don't want them enabled, don't define this.
+ */
+#define CONFIG_SYS_LED_BASE 0x00000000
+#undef CONFIG_SYS_LED_BASE
+
+/*
+ * select serial console configuration
+ *
+ * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ *
+ * if CONFIG_CONS_NONE is defined, then the serial console routines must
+ * defined elsewhere.
+ */
+#define CONFIG_CONS_ON_SMC          /* define if console on SMC */
+#undef  CONFIG_CONS_ON_SCC          /* define if console on SCC */
+#undef  CONFIG_CONS_NONE            /* define if console on neither */
+#define CONFIG_CONS_INDEX    1      /* which SMC/SCC channel for console */
+
+/*
+ * select ethernet configuration
+ *
+ * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
+ * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
+ * for FCC)
+ *
+ * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
+ */
+#undef  CONFIG_ETHER_ON_SCC           /* define if ethernet on SCC    */
+#define CONFIG_ETHER_ON_FCC           /* define if ethernet on FCC    */
+#undef  CONFIG_ETHER_NONE             /* define if ethernet on neither */
+#define CONFIG_ETHER_INDEX      3     /* which SCC/FCC channel for ethernet */
+
+#if ( CONFIG_ETHER_INDEX == 3 )
+
+/*
+ * - Rx-CLK is CLK15
+ * - Tx-CLK is CLK16
+ * - RAM for BD/Buffers is on the local Bus (see 28-13)
+ * - Enable Half Duplex in FSMR
+ */
+# define CONFIG_SYS_CMXFCR_MASK3	(CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE3	(CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
+
+/*
+ * - RAM for BD/Buffers is on the local Bus (see 28-13)
+ */
+#ifdef CONFIG_SYS_LSDRAM
+  #define CONFIG_SYS_CPMFCR_RAMTYPE	3
+#else /* CONFIG_SYS_LSDRAM */
+  #define CONFIG_SYS_CPMFCR_RAMTYPE	0
+#endif /* CONFIG_SYS_LSDRAM */
+
+/* - Enable Half Duplex in FSMR */
+/* # define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB) */
+# define CONFIG_SYS_FCC_PSMR		0
+
+#else /* CONFIG_ETHER_INDEX */
+# error "on EP8260 ethernet must be FCC3"
+#endif /* CONFIG_ETHER_INDEX */
+
+/*
+ * select i2c support configuration
+ *
+ * Supported configurations are {none, software, hardware} drivers.
+ * If the software driver is chosen, there are some additional
+ * configuration items that the driver uses to drive the port pins.
+ */
+#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
+
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F	/* This is for HARD, must go */
+
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#ifdef CONFIG_SYS_I2C_SOFT
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT_SPEED	50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
+#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
+#define I2C_ACTIVE	(iop->pdir |=  0x00010000)
+#define I2C_TRISTATE	(iop->pdir &= ~0x00010000)
+#define I2C_READ	((iop->pdat & 0x00010000) != 0)
+#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00010000; \
+			else    iop->pdat &= ~0x00010000
+#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00020000; \
+			else    iop->pdat &= ~0x00020000
+#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
+#endif /* CONFIG_SYS_I2C_SOFT */
+
+/* #define CONFIG_RTC_DS174x */
+
+/* Define this to reserve an entire FLASH sector (256 KB) for
+ * environment variables. Otherwise, the environment will be
+ * put in the same sector as U-Boot, and changing variables
+ * will erase U-Boot temporarily
+ */
+#define CONFIG_ENV_IN_OWN_SECT
+
+/* Define to allow the user to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* What should the console's baud rate be? */
+#ifdef CONFIG_SYS_EP8260_H2
+#define CONFIG_BAUDRATE         9600
+#else
+#define CONFIG_BAUDRATE         115200
+#endif
+
+/* Ethernet MAC address */
+#define CONFIG_ETHADDR          00:10:EC:00:30:8C
+
+#define CONFIG_IPADDR		192.168.254.130
+#define CONFIG_SERVERIP         192.168.254.49
+
+/* Set to a positive value to delay for running BOOTCOMMAND */
+#define CONFIG_BOOTDELAY        -1
+
+/* undef this to save memory */
+#define CONFIG_SYS_LONGHELP
+
+/* Monitor Command Prompt       */
+
+/* Define this variable to enable the "hush" shell (from
+   Busybox) as command line interpreter, thus enabling
+   powerful command line syntax like
+   if...then...else...fi conditionals or `&&' and '||'
+   constructs ("shell scripts").
+   If undefined, you get the old, much simpler behaviour
+   with a somewhat smapper memory footprint.
+*/
+#define CONFIG_SYS_HUSH_PARSER
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_CDP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_PORTIO
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
+
+#undef CONFIG_CMD_XIMG
+
+/* Where do the internal registers live? */
+#define CONFIG_SYS_IMMR               0xF0000000
+#define CONFIG_SYS_DEFAULT_IMMR       0x00010000
+
+/* Where do the on board registers (CS4) live? */
+#define CONFIG_SYS_REGS_BASE          0xFA000000
+
+/*****************************************************************************
+ *
+ * You should not have to modify any of the following settings
+ *
+ *****************************************************************************/
+
+#define CONFIG_EP8260           11      /* on an Embedded Planet EP8260 Board, Rev. 11 */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_early_init_f	*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#if defined(CONFIG_CMD_KGDB)
+#  define CONFIG_SYS_CBSIZE              1024       /* Console I/O Buffer Size      */
+#else
+#  define CONFIG_SYS_CBSIZE              256        /* Console I/O Buffer Size      */
+#endif
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE        (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
+
+#define CONFIG_SYS_MAXARGS       8            /* max number of command args   */
+
+#define CONFIG_SYS_BARGSIZE      CONFIG_SYS_CBSIZE   /* Boot Argument Buffer Size    */
+
+#ifdef CONFIG_SYS_LSDRAM
+  #define CONFIG_SYS_MEMTEST_START 0x04000000   /* memtest works on  */
+  #define CONFIG_SYS_MEMTEST_END   0x06000000   /* 64-96 MB in SDRAM */
+#else
+  #define CONFIG_SYS_MEMTEST_START 0x00000000   /* memtest works on  */
+  #define CONFIG_SYS_MEMTEST_END   0x02000000   /* 0-32 MB in SDRAM */
+#endif /* CONFIG_SYS_LSDRAM */
+
+#define	CONFIG_CLOCKS_IN_MHZ	1      /* clocks passsed to Linux in MHz */
+
+#define CONFIG_SYS_LOAD_ADDR     0x00100000   /* default load address */
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+#define CONFIG_SYS_FLASH_BASE    CONFIG_SYS_FLASH0_BASE
+#define CONFIG_SYS_SDRAM_BASE    CONFIG_SYS_SDRAM0_BASE
+
+/*-----------------------------------------------------------------------
+ * Hard Reset Configuration Words
+ */
+
+#if defined(CONFIG_SYS_SBC_BOOT_LOW)
+#  define  CONFIG_SYS_SBC_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
+#else
+#  define  CONFIG_SYS_SBC_HRCW_BOOT_FLAGS  (0x00000000)
+#endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */
+
+#ifdef CONFIG_SYS_EP8260_H2
+/* get the HRCW ISB field from CONFIG_SYS_DEFAULT_IMMR */
+#define CONFIG_SYS_SBC_HRCW_IMMR ( ((CONFIG_SYS_DEFAULT_IMMR & 0x10000000) >> 10) |\
+			    ((CONFIG_SYS_DEFAULT_IMMR & 0x01000000) >> 7)  |\
+			    ((CONFIG_SYS_DEFAULT_IMMR & 0x00100000) >> 4) )
+
+#define CONFIG_SYS_HRCW_MASTER (HRCW_EBM                |\
+			 HRCW_L2CPC01            |\
+			 CONFIG_SYS_SBC_HRCW_IMMR       |\
+			 HRCW_APPC10             |\
+			 HRCW_CS10PC01           |\
+			 CONFIG_SYS_SBC_MODCK_H	 |\
+			 CONFIG_SYS_SBC_HRCW_BOOT_FLAGS)
+#else
+#define CONFIG_SYS_HRCW_MASTER 0x10400245
+#endif
+
+/* no slaves */
+#define CONFIG_SYS_HRCW_SLAVE1 0
+#define CONFIG_SYS_HRCW_SLAVE2 0
+#define CONFIG_SYS_HRCW_SLAVE3 0
+#define CONFIG_SYS_HRCW_SLAVE4 0
+#define CONFIG_SYS_HRCW_SLAVE5 0
+#define CONFIG_SYS_HRCW_SLAVE6 0
+#define CONFIG_SYS_HRCW_SLAVE7 0
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR       CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_SIZE        0x4000  /* Size of used area in DPRAM    */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent.
+ */
+#define CONFIG_SYS_MONITOR_BASE          CONFIG_SYS_TEXT_BASE
+
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#  define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN      (256 << 10)     /* Reserve 256 kB for Monitor   */
+#define CONFIG_SYS_MALLOC_LEN       (128 << 10)     /* Reserve 128 kB for malloc()  */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS   1       /* max number of memory banks         */
+#ifdef CONFIG_SYS_EP8260_H2
+#define CONFIG_SYS_MAX_FLASH_SECT    128      /* max number of sectors on one chip  */
+#else
+#define CONFIG_SYS_MAX_FLASH_SECT    71      /* max number of sectors on one chip  */
+#endif
+
+#ifdef CONFIG_SYS_EP8260_H2
+#define CONFIG_SYS_FLASH_ERASE_TOUT  240000  /* Timeout for Flash Erase (in ms)    */
+#define CONFIG_SYS_FLASH_WRITE_TOUT  500     /* Timeout for Flash Write (in ms)    */
+#else
+#define CONFIG_SYS_FLASH_ERASE_TOUT  8000    /* Timeout for Flash Erase (in ms)    */
+#define CONFIG_SYS_FLASH_WRITE_TOUT  1       /* Timeout for Flash Write (in ms)    */
+#endif
+
+#ifndef CONFIG_SYS_RAMBOOT
+#  define CONFIG_ENV_IS_IN_FLASH  1
+
+#  ifdef CONFIG_ENV_IN_OWN_SECT
+#    define CONFIG_ENV_ADDR       (CONFIG_SYS_MONITOR_BASE + 0x40000)
+#    define CONFIG_ENV_SECT_SIZE  0x40000
+#  else
+#    define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE)
+#    define CONFIG_ENV_SIZE       0x1000  /* Total Size of Environment Sector */
+#    define CONFIG_ENV_SECT_SIZE  0x10000 /* see README - env sect real size */
+#  endif /* CONFIG_ENV_IN_OWN_SECT */
+#else
+#  define CONFIG_ENV_IS_IN_NVRAM  1
+#  define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
+#  define CONFIG_ENV_SIZE         0x200
+#endif /* CONFIG_SYS_RAMBOOT */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE      32      /* For MPC8260 CPU */
+
+#if defined(CONFIG_CMD_KGDB)
+#  define CONFIG_SYS_CACHELINE_SHIFT     5     /* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * HIDx - Hardware Implementation-dependent Registers                    2-11
+ *-----------------------------------------------------------------------
+ * HID0 also contains cache control - initially enable both caches and
+ * invalidate contents, then the final state leaves only the instruction
+ * cache enabled. Note that Power-On and Hard reset invalidate the caches,
+ * but Soft reset does not.
+ *
+ * HID1 has only read-only information - nothing to set.
+ */
+#define CONFIG_SYS_HID0_INIT   (HID0_ICE  |\
+			 HID0_DCE  |\
+			 HID0_ICFI |\
+			 HID0_DCI  |\
+			 HID0_IFEM |\
+			 HID0_ABE)
+#ifdef CONFIG_SYS_LSDRAM
+/* 8260 local bus is NOT cacheable */
+#define CONFIG_SYS_HID0_FINAL  (/*HID0_ICE  |*/\
+			 HID0_IFEM |\
+			 HID0_ABE  |\
+			 HID0_EMCP)
+#else /* !CONFIG_SYS_LSDRAM */
+#define CONFIG_SYS_HID0_FINAL  (HID0_ICE  |\
+			 HID0_IFEM |\
+			 HID0_ABE  |\
+			 HID0_EMCP)
+#endif /* CONFIG_SYS_LSDRAM */
+
+#define CONFIG_SYS_HID2        0
+
+/*-----------------------------------------------------------------------
+ * RMR - Reset Mode Register
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RMR         0
+
+/*-----------------------------------------------------------------------
+ * BCR - Bus Configuration                                       4-25
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_BCR         (BCR_EBM   |\
+			 BCR_PLDP  |\
+			 BCR_EAV   |\
+			 BCR_NPQM0)
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration                             4-31
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_SIUMCR      (SIUMCR_L2CPC01 |\
+			 SIUMCR_APPC10  |\
+			 SIUMCR_CS10PC01)
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control                            11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
+ */
+#ifdef CONFIG_SYS_EP8260_H2
+/* TBD: Find out why setting the BMT to 0xff causes the FCC to
+ * generate TX buffer underrun errors for large packets under
+ * Linux
+ */
+#define CONFIG_SYS_SYPCR_BMT	0x00000600
+#else
+#define CONFIG_SYS_SYPCR_BMT	SYPCR_BMT
+#endif
+
+#ifdef CONFIG_SYS_LSDRAM
+#define CONFIG_SYS_SYPCR       (SYPCR_SWTC |\
+			 CONFIG_SYS_SYPCR_BMT  |\
+			 SYPCR_PBME |\
+			 SYPCR_LBME |\
+			 SYPCR_SWP)
+#else
+#define CONFIG_SYS_SYPCR       (SYPCR_SWTC |\
+			 CONFIG_SYS_SYPCR_BMT  |\
+			 SYPCR_PBME |\
+			 SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * TMCNTSC - Time Counter Status and Control                     4-40
+ *-----------------------------------------------------------------------
+ * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
+ * and enable Time Counter
+ */
+#define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC |\
+			 TMCNTSC_ALR |\
+			 TMCNTSC_TCF |\
+			 TMCNTSC_TCE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control                 4-42
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
+ * Periodic timer
+ */
+#ifdef CONFIG_SYS_EP8260_H2
+#define CONFIG_SYS_PISCR       (PISCR_PS  |\
+			 PISCR_PTF |\
+			 PISCR_PTE)
+#else
+#define CONFIG_SYS_PISCR	0
+#endif
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control                                   9-8
+ *-----------------------------------------------------------------------
+ */
+#ifdef CONFIG_SYS_EP8260_H2
+#define CONFIG_SYS_SCCR        (SCCR_DFBRG00)
+#else
+#define CONFIG_SYS_SCCR        (SCCR_DFBRG01)
+#endif
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration                         13-7
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RCCR        0
+
+/*-----------------------------------------------------------------------
+ * MPTPR - Memory Refresh Timer Prescale Register               10-32
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_MPTPR	(0x0A00 & MPTPR_PTP_MSK)
+
+/*
+ * Init Memory Controller:
+ *
+ * Bank Bus     Machine PortSz  Device
+ * ---- ---     ------- ------  ------
+ *  0   60x     GPCM    64 bit  FLASH (BGA - 16MB AMD AM29DL323DB90WDI)
+ *  1   60x     SDRAM   64 bit  SDRAM (BGA - 64MB Micron 48LC8M16A2TG)
+ *  2   Local   SDRAM   32 bit  SDRAM (BGA - 32MB Micron 48LC8M16A2TG)
+ *  3   unused
+ *  4   60x     GPCM     8 bit  Board Regs, NVRTC
+ *  5   unused
+ *  6   unused
+ *  7   unused
+ *  8   PCMCIA
+ *  9   unused
+ * 10   unused
+ * 11   unused
+*/
+
+/*-----------------------------------------------------------------------
+ * BRx - Base Register
+ *     Ref: Section 10.3.1 on page 10-14
+ * ORx - Option Register
+ *     Ref: Section 10.3.2 on page 10-18
+ *-----------------------------------------------------------------------
+ */
+
+/* Bank 0 - FLASH
+ *
+ */
+#define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\
+			 BRx_PS_64                      |\
+			 BRx_DECC_NONE                  |\
+			 BRx_MS_GPCM_P                  |\
+			 BRx_V)
+
+#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE)     |\
+			 ORxG_CSNT                      |\
+			 ORxG_ACS_DIV1                  |\
+			 ORxG_SCY_8_CLK                 |\
+			 ORxG_EHTR)
+
+/* Bank 1 - SDRAM
+ * PSDRAM
+ */
+#define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
+			 BRx_PS_64                      |\
+			 BRx_MS_SDRAM_P                 |\
+			 BRx_V)
+
+#define CONFIG_SYS_OR1_PRELIM  (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE)     |\
+			 ORxS_BPD_4                     |\
+			 ORxS_ROWST_PBI1_A6             |\
+			 ORxS_NUMR_12)
+
+#ifdef CONFIG_SYS_EP8260_H2
+#define CONFIG_SYS_PSDMR       0xC34E246E
+#else
+#define CONFIG_SYS_PSDMR       0xC34E2462
+#endif
+
+#define CONFIG_SYS_PSRT	0x64
+
+#ifdef CONFIG_SYS_LSDRAM
+/* Bank 2 - SDRAM
+ * LSDRAM
+ */
+
+  #define CONFIG_SYS_BR2_PRELIM  ((CONFIG_SYS_SDRAM1_BASE & BRx_BA_MSK) |\
+			   BRx_PS_32                      |\
+			   BRx_MS_SDRAM_L                 |\
+			   BRx_V)
+
+  #define CONFIG_SYS_OR2_PRELIM  (MEG_TO_AM(CONFIG_SYS_SDRAM1_SIZE)     |\
+			   ORxS_BPD_4                     |\
+			   ORxS_ROWST_PBI0_A9             |\
+			   ORxS_NUMR_12)
+
+  #define CONFIG_SYS_LSDMR      0x416A2562
+  #define CONFIG_SYS_LSRT	0x64
+#else
+  #define CONFIG_SYS_LSRT	0x0
+#endif /* CONFIG_SYS_LSDRAM */
+
+/* Bank 4 - On board registers
+ * NVRTC and BCSR
+ */
+#define CONFIG_SYS_BR4_PRELIM   ((CONFIG_SYS_REGS_BASE & BRx_BA_MSK)  |\
+			   BRx_PS_8                     |\
+			   BRx_MS_GPCM_P                |\
+			   BRx_V)
+/*
+#define CONFIG_SYS_OR4_PRELIM    (ORxG_AM_MSK                 |\
+			   ORxG_CSNT                   |\
+			   ORxG_ACS_DIV1               |\
+			   ORxG_SCY_10_CLK              |\
+			   ORxG_TRLX)
+*/
+#define CONFIG_SYS_OR4_PRELIM 0xfff00854
+
+#ifdef _NOT_USED_SINCE_NOT_WORKING_
+/* Bank 8 - On board registers
+ * PCMCIA (currently not working!)
+ */
+#define CONFIG_SYS_BR8_PRELIM   ((CONFIG_SYS_REGS_BASE & BRx_BA_MSK)  |\
+			   BRx_PS_16                     |\
+			   BRx_MS_GPCM_P                |\
+			   BRx_V)
+
+#define CONFIG_SYS_OR8_PRELIM    (ORxG_AM_MSK                 |\
+			   ORxG_CSNT                   |\
+			   ORxG_ACS_DIV1               |\
+			   ORxG_SETA                   |\
+			   ORxG_SCY_10_CLK)
+#endif
+
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_CMD_MTDPARTS
+#define CONFIG_JFFS2_DEV		"nor0"
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET	0x00000000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_CMD_MTDPARTS
+#define MTDIDS_DEFAULT		""
+#define MTDPARTS_DEFAULT	""
+*/
+
+#endif  /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/ep82xxm.h b/qemu/roms/u-boot/include/configs/ep82xxm.h
new file mode 100644
index 000000000..cf31f0f14
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/ep82xxm.h
@@ -0,0 +1,383 @@
+/*
+ * Copyright (C) 2006 Embedded Planet, LLC.
+ *
+ * U-Boot configuration for Embedded Planet EP82xxM boards.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CPU_ID_STR		"MPC8270"
+
+#define CONFIG_EP82XXM	/* Embedded Planet EP82xxM H 1.0 board */
+			/* 256MB SDRAM / 64MB FLASH */
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f */
+
+/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * Select serial console configuration
+ *
+ * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ */
+#define	CONFIG_CONS_ON_SMC		/* Console is on SMC         */
+#undef  CONFIG_CONS_ON_SCC		/* It's not on SCC           */
+#undef	CONFIG_CONS_NONE		/* It's not on external UART */
+#define CONFIG_CONS_INDEX	1	/* SMC1 is used for console  */
+
+#define CONFIG_SYS_BCSR		0xFA000000
+
+/*
+ * Select ethernet configuration
+ *
+ * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
+ * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
+ * SCC, 1-3 for FCC)
+ *
+ * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
+ * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
+ * must be unset.
+ */
+#undef	CONFIG_ETHER_ON_SCC		/* Ethernet is not on SCC */
+#define CONFIG_ETHER_ON_FCC		/* Ethernet is on FCC     */
+#undef	CONFIG_ETHER_NONE		/* No external Ethernet   */
+
+
+#define CONFIG_ETHER_ON_FCC2
+#define CONFIG_ETHER_ON_FCC3
+
+#define CONFIG_SYS_CMXFCR_MASK3	(CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
+#define CONFIG_SYS_CMXFCR_VALUE3	(CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK16)
+#define CONFIG_SYS_CMXFCR_MASK2	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+#define CONFIG_SYS_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
+
+#define CONFIG_SYS_CPMFCR_RAMTYPE	0
+#define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
+
+#define CONFIG_MII			/* MII PHY management        */
+#define CONFIG_BITBANGMII		/* Bit-banged MDIO interface */
+
+/*
+ * GPIO pins used for bit-banged MII communications
+ */
+#define MDIO_PORT		0	/* Not used - implemented in BCSR */
+
+#define MDIO_ACTIVE		(*(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFB)
+#define MDIO_TRISTATE		(*(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x04)
+#define MDIO_READ		(*(vu_char *)(CONFIG_SYS_BCSR + 8) & 1)
+
+#define MDIO(bit)		if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x01; \
+				else	*(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFE
+
+#define MDC(bit)		if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x02; \
+				else	*(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFD
+
+#define MIIDELAY		udelay(1)
+
+
+#ifndef CONFIG_8260_CLKIN
+#define CONFIG_8260_CLKIN	66000000 /* in Hz */
+#endif
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_SYS_VXWORKS_MAC_PTR 0x4300 /* Pass Ethernet MAC to VxWorks */
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_DIAG
+
+
+#define CONFIG_ETHADDR		00:10:EC:00:88:65
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR		00:10:EC:80:88:65
+#define CONFIG_IPADDR		10.0.0.245
+#define CONFIG_HOSTNAME		EP82xxM
+#define CONFIG_SERVERIP		10.0.0.26
+#define CONFIG_GATEWAYIP	10.0.0.1
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+#define CONFIG_ENV_IN_OWN_SECT	1
+#define CONFIG_AUTO_COMPLETE	1
+#define	CONFIG_EXTRA_ENV_SETTINGS	"ethprime=FCC3"
+
+#if defined(CONFIG_CMD_KGDB)
+#undef	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
+#define CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
+#undef	CONFIG_KGDB_NONE		/* define if kgdb on something else */
+#define CONFIG_KGDB_INDEX	1	/* which serial channel for kgdb */
+#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port at */
+#endif
+
+#define CONFIG_BZIP2	/* include support for bzip2 compressed images */
+#undef	CONFIG_WATCHDOG			/* disable platform specific watchdog */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#define CONFIG_SYS_PROMPT		"ep82xxm=> "	/* Monitor Command Prompt   */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size  */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size  */
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
+
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+/*
+ * Define here the location of the environment variables (FLASH or EEPROM).
+ * Note: DENX encourages to use redundant environment in FLASH.
+ */
+#if 1
+#define CONFIG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
+#else
+#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_FLASH_BASE		0xFC000000
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sects on one chip */
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector in flinfo */
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	0x20000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#endif /* CONFIG_ENV_IS_IN_FLASH */
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+/* EEPROM Configuration */
+#define CONFIG_SYS_EEPROM_SIZE	0x1000
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x54
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
+
+#ifdef CONFIG_ENV_IS_IN_EEPROM
+#define CONFIG_ENV_SIZE		0x200	    /* Size of Environment vars */
+#define CONFIG_ENV_OFFSET		0x0
+#endif /* CONFIG_ENV_IS_IN_EEPROM */
+
+/* RTC Configuration */
+#define CONFIG_RTC_M41T11	1	/* uses a M41T81 */
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68
+#define CONFIG_M41T11_BASE_YEAR	1900
+
+/* I2C SYSMON (LM75) */
+#define CONFIG_DTT_LM75		1
+#define CONFIG_DTT_SENSORS	{0}
+#define CONFIG_SYS_DTT_MAX_TEMP	70
+#define CONFIG_SYS_DTT_LOW_TEMP	-30
+#define	CONFIG_SYS_DTT_HYSTERESIS	3
+
+/*-----------------------------------------------------------------------
+ * NVRAM Configuration
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xFA080000
+#define CONFIG_SYS_NVRAM_SIZE		(128*1024)-16
+
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+/* General PCI */
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play   */
+#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
+#define CONFIG_PCI_BOOTDELAY	0
+
+/* PCI Memory map (if different from default map */
+#define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE		/* Local base */
+#define CONFIG_SYS_PCI_SLV_MEM_BUS		0x00000000	/* PCI base */
+#define CONFIG_SYS_PICMR0_MASK_ATTRIB	(PICMR_MASK_512MB | PICMR_ENABLE | \
+				 PICMR_PREFETCH_EN)
+
+/*
+ * These are the windows that allow the CPU to access PCI address space.
+ * All three PCI master windows, which allow the CPU to access PCI
+ * prefetch, non prefetch, and IO space (see below), must all fit within
+ * these windows.
+ */
+
+/*
+ * Master window that allows the CPU to access PCI Memory (prefetch).
+ * This window will be setup with the second set of Outbound ATU registers
+ * in the bridge.
+ */
+
+#define CONFIG_SYS_PCI_MSTR_MEM_LOCAL	0x80000000          /* Local base */
+#define CONFIG_SYS_PCI_MSTR_MEM_BUS	0x80000000          /* PCI base   */
+#define	CONFIG_SYS_CPU_PCI_MEM_START	PCI_MSTR_MEM_LOCAL
+#define CONFIG_SYS_PCI_MSTR_MEM_SIZE	0x20000000          /* 512MB */
+#define CONFIG_SYS_POCMR0_MASK_ATTRIB	(POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
+
+/*
+ * Master window that allows the CPU to access PCI Memory (non-prefetch).
+ * This window will be setup with the second set of Outbound ATU registers
+ * in the bridge.
+ */
+
+#define CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL    0xA0000000          /* Local base */
+#define CONFIG_SYS_PCI_MSTR_MEMIO_BUS      0xA0000000          /* PCI base   */
+#define CONFIG_SYS_CPU_PCI_MEMIO_START     PCI_MSTR_MEMIO_LOCAL
+#define CONFIG_SYS_PCI_MSTR_MEMIO_SIZE     0x20000000          /* 512MB */
+#define CONFIG_SYS_POCMR1_MASK_ATTRIB      (POCMR_MASK_512MB | POCMR_ENABLE)
+
+/*
+ * Master window that allows the CPU to access PCI IO space.
+ * This window will be setup with the first set of Outbound ATU registers
+ * in the bridge.
+ */
+
+#define CONFIG_SYS_PCI_MSTR_IO_LOCAL       0xF6000000          /* Local base */
+#define CONFIG_SYS_PCI_MSTR_IO_BUS         0x00000000          /* PCI base   */
+#define CONFIG_SYS_CPU_PCI_IO_START        PCI_MSTR_IO_LOCAL
+#define CONFIG_SYS_PCI_MSTR_IO_SIZE        0x02000000          /* 64MB */
+#define CONFIG_SYS_POCMR2_MASK_ATTRIB      (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO)
+
+
+/* PCIBR0 - for PCI IO*/
+#define CONFIG_SYS_PCI_MSTR0_LOCAL		CONFIG_SYS_PCI_MSTR_IO_LOCAL		/* Local base */
+#define CONFIG_SYS_PCIMSK0_MASK		~(CONFIG_SYS_PCI_MSTR_IO_SIZE - 1U)	/* Size of window */
+/* PCIBR1 - prefetch and non-prefetch regions joined together */
+#define CONFIG_SYS_PCI_MSTR1_LOCAL		CONFIG_SYS_PCI_MSTR_MEM_LOCAL
+#define CONFIG_SYS_PCIMSK1_MASK		~(CONFIG_SYS_PCI_MSTR_MEM_SIZE + CONFIG_SYS_PCI_MSTR_MEMIO_SIZE - 1U)
+
+
+#define	CONFIG_SYS_DIRECT_FLASH_TFTP
+
+#if defined(CONFIG_CMD_JFFS2)
+#define CONFIG_SYS_JFFS2_FIRST_BANK	0
+#define CONFIG_SYS_JFFS2_NUM_BANKS	CONFIG_SYS_MAX_FLASH_BANKS
+#define CONFIG_SYS_JFFS2_FIRST_SECTOR  0
+#define CONFIG_SYS_JFFS2_LAST_SECTOR   62
+#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
+#define CONFIG_SYS_JFFS_CUSTOM_PART
+#endif
+
+#if defined(CONFIG_CMD_I2C)
+#define CONFIG_HARD_I2C		1	/* To enable I2C support	*/
+#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed			*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F	/* I2C slave address		*/
+#endif
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN		(512 << 10)	/* Reserve 256KB for Monitor */
+
+#define CONFIG_SYS_DEFAULT_IMMR	0x00010000
+#define CONFIG_SYS_IMMR		0xF0000000
+
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+
+/* Hard reset configuration word */
+#define CONFIG_SYS_HRCW_MASTER		0 /*0x1C800641*/  /* Not used - provided by CPLD */
+/* No slaves */
+#define CONFIG_SYS_HRCW_SLAVE1		0
+#define CONFIG_SYS_HRCW_SLAVE2		0
+#define CONFIG_SYS_HRCW_SLAVE3		0
+#define CONFIG_SYS_HRCW_SLAVE4		0
+#define CONFIG_SYS_HRCW_SLAVE5		0
+#define CONFIG_SYS_HRCW_SLAVE6		0
+#define CONFIG_SYS_HRCW_SLAVE7		0
+
+#define CONFIG_SYS_MALLOC_LEN		(4096 << 10)	/* Reserve 4 MB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPUs */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+#define CONFIG_SYS_HID0_INIT		0
+#define CONFIG_SYS_HID0_FINAL		0
+
+#define CONFIG_SYS_HID2		0
+
+#define CONFIG_SYS_SIUMCR		0x02610000
+#define CONFIG_SYS_SYPCR		0xFFFF0689
+#define CONFIG_SYS_BCR			0x8080E000
+#define CONFIG_SYS_SCCR		0x00000001
+
+#define CONFIG_SYS_RMR			0
+#define CONFIG_SYS_TMCNTSC		0x000000C3
+#define CONFIG_SYS_PISCR		0x00000083
+#define CONFIG_SYS_RCCR		0
+
+#define CONFIG_SYS_MPTPR		0x0A00
+#define CONFIG_SYS_PSDMR		0xC432246E
+#define CONFIG_SYS_PSRT		0x32
+
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_BR		(CONFIG_SYS_SDRAM_BASE | 0x00000041)
+#define CONFIG_SYS_SDRAM_OR		0xF0002900
+
+#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | 0x00001801)
+#define CONFIG_SYS_OR0_PRELIM		0xFC000882
+#define CONFIG_SYS_BR4_PRELIM		(CONFIG_SYS_BCSR | 0x00001001)
+#define CONFIG_SYS_OR4_PRELIM		0xFFF00050
+
+#define CONFIG_SYS_RESET_ADDRESS	0xFFF00100
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/espt.h b/qemu/roms/u-boot/include/configs/espt.h
new file mode 100644
index 000000000..de16be70b
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/espt.h
@@ -0,0 +1,111 @@
+/*
+ * Configuation settings for the ESPT-GIGA board
+ *
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ESPT_H
+#define __ESPT_H
+
+#define CONFIG_CPU_SH7763	1
+#define CONFIG_ESPT	1
+#define __LITTLE_ENDIAN		1
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SAVEENV
+
+#define CONFIG_BOOTDELAY        -1
+#define CONFIG_BOOTARGS         "console=ttySC0,115200 root=1f01"
+#define CONFIG_ENV_OVERWRITE    1
+
+#define CONFIG_VERSION_VARIABLE
+#undef  CONFIG_SHOW_BOOT_PROGRESS
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE		1
+#define CONFIG_BAUDRATE         115200
+#define CONFIG_CONS_SCIF0		1
+
+#define CONFIG_SYS_TEXT_BASE	0x8FFC0000
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_CBSIZE		256	/* Buffer size for input from the Console */
+#define CONFIG_SYS_PBSIZE		256	/* Buffer size for Console output */
+#define CONFIG_SYS_MAXARGS		16	/* max args accepted for monitor commands */
+#define CONFIG_SYS_BARGSIZE	512	/* Buffer size for Boot Arguments
+								passed to kernel */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }	/* List of legal baudrate
+												settings for this board */
+
+/* SDRAM */
+#define CONFIG_SYS_SDRAM_BASE		(0x8C000000)
+#define CONFIG_SYS_SDRAM_SIZE		(64 * 1024 * 1024)
+#define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
+
+/* Flash(NOR) S29JL064H */
+#define CONFIG_SYS_FLASH_BASE		(0xA0000000)
+#define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT)
+#define CONFIG_SYS_MAX_FLASH_BANKS (1)
+#define CONFIG_SYS_MAX_FLASH_SECT  (150)
+
+/* U-boot setting */
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_MONITOR_LEN		(128 * 1024)
+/* Size of DRAM reserved for malloc() use */
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
+#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#undef  CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_SYS_FLASH_EMPTY_INFO	/* print 'E' for empty sector on flinfo */
+/* Timeout for Flash erase operations (in ms) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(3 * 1000)
+/* Timeout for Flash write operations (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(3 * 1000)
+/* Timeout for Flash set sector lock bit operations (in ms) */
+#define CONFIG_SYS_FLASH_LOCK_TOUT		(3 * 1000)
+/* Timeout for Flash clear lock bit operations (in ms) */
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	(3 * 1000)
+/* Use hardware flash sectors protection instead of U-Boot software protection */
+#undef  CONFIG_SYS_FLASH_PROTECTION
+#undef  CONFIG_SYS_DIRECT_FLASH_TFTP
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	(128 * 1024)
+#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE))
+/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
+#define CONFIG_ENV_OFFSET		(CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
+
+/* Clock */
+#define CONFIG_SYS_CLK_FREQ	66666666
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_TMU_CLK_DIV      4
+
+/* Ether */
+#define CONFIG_SH_ETHER 1
+#define CONFIG_SH_ETHER_USE_PORT (1)
+#define CONFIG_SH_ETHER_PHY_ADDR (0x00)
+#define CONFIG_PHYLIB
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
+
+#endif /* __SH7763RDP_H */
diff --git a/qemu/roms/u-boot/include/configs/ethernut5.h b/qemu/roms/u-boot/include/configs/ethernut5.h
new file mode 100644
index 000000000..480d8678c
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/ethernut5.h
@@ -0,0 +1,269 @@
+/*
+ * (C) Copyright 2011
+ * egnite GmbH <info@egnite.de>
+ *
+ * Configuation settings for Ethernut 5 with AT91SAM9XE.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/hardware.h>
+
+/* The first stage boot loader expects u-boot running at this address. */
+#define CONFIG_SYS_TEXT_BASE	0x27000000	/* 16MB available */
+
+/* The first stage boot loader takes care of low level initialization. */
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* Set our official architecture number. */
+#define MACH_TYPE_ETHERNUT5 1971
+#define CONFIG_MACH_TYPE MACH_TYPE_ETHERNUT5
+
+/* CPU information */
+#define CONFIG_ARM926EJS
+#define CONFIG_AT91FAMILY
+#define CONFIG_DISPLAY_CPUINFO		/* Display at console. */
+#define CONFIG_ARCH_CPU_INIT
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768	/* slow clock xtal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000 /* 18.432 MHz crystal */
+
+/* 32kB internal SRAM */
+#define CONFIG_SRAM_BASE	0x00300000 /*AT91SAM9XE_SRAM_BASE */
+#define CONFIG_SRAM_SIZE	(32 << 10)
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SRAM_BASE + CONFIG_SRAM_SIZE - \
+				GENERATED_GBL_DATA_SIZE)
+
+/* 128MB SDRAM in 1 bank */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE		0x20000000
+#define CONFIG_SYS_SDRAM_SIZE		(128 << 20)
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE
+#define CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (1 << 20))
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_TEXT_BASE \
+					- CONFIG_SYS_MALLOC_LEN)
+
+/* 512kB on-chip NOR flash */
+# define CONFIG_SYS_MAX_FLASH_BANKS	1
+# define CONFIG_SYS_FLASH_BASE		0x00200000 /* AT91SAM9XE_FLASH_BASE */
+# define CONFIG_AT91_EFLASH
+# define CONFIG_SYS_MAX_FLASH_SECT	32
+# define CONFIG_SYS_FLASH_PROTECTION	/* First stage loader in sector 0 */
+# define CONFIG_EFLASH_PROTSECTORS	1
+
+/* 512kB DataFlash at NPCS0 */
+#define CONFIG_SYS_MAX_DATAFLASH_BANKS	1
+#define CONFIG_HAS_DATAFLASH
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_ATMEL
+#define CONFIG_ATMEL_DATAFLASH_SPI
+#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000
+#define DATAFLASH_TCSS			(0x1a << 16)
+#define DATAFLASH_TCHS			(0x1 << 24)
+
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET		0x3DE000
+#define CONFIG_ENV_SECT_SIZE		(132 << 10)
+#define CONFIG_ENV_SIZE			CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 \
+					+ CONFIG_ENV_OFFSET)
+#define CONFIG_SYS_MONITOR_BASE		(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 \
+					+ 0x042000)
+
+/* SPI */
+#define CONFIG_ATMEL_SPI
+#define CONFIG_SYS_SPI_WRITE_TOUT	(5 * CONFIG_SYS_HZ)
+#define AT91_SPI_CLK			15000000
+
+/* Serial port */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART3			/* USART 3 is DBGU */
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
+#define	CONFIG_USART_ID			ATMEL_ID_SYS
+
+/* Misc. hardware drivers */
+#define CONFIG_AT91_GPIO
+
+/* Command line configuration */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_LOADS
+
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_SPI
+
+#ifdef MINIMAL_LOADER
+#undef CONFIG_CMD_CONSOLE
+#undef CONFIG_CMD_EDITENV
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_ITEST
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
+#else
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_CDP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DNS
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_RARP
+#define CONFIG_CMD_REISER
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_CMD_UNZIP
+#define CONFIG_CMD_USB
+#endif
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CONFIG_SYS_NAND_DBW_8
+#define CONFIG_NAND_ATMEL
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN	GPIO_PIN_PC(14)
+#endif
+
+/* JFFS2 */
+#ifdef CONFIG_CMD_JFFS2
+#define CONFIG_MTD_NAND_ECC_JFFS2
+#define CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_NAND
+#endif
+
+/* Ethernet */
+#define CONFIG_NET_RETRY_COUNT		20
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_PHY_ID			0
+#define CONFIG_MACB_SEARCH_PHY
+
+/* MMC */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_GENERIC_ATMEL_MCI
+#define CONFIG_SYS_MMC_CD_PIN		AT91_PIO_PORTC, 8
+#endif
+
+/* USB */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE	0x00500000
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"host"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+#define CONFIG_USB_STORAGE
+#endif
+
+/* RTC */
+#if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP)
+#define CONFIG_RTC_PCF8563
+#define CONFIG_SYS_I2C_RTC_ADDR		0x51
+#endif
+
+/* I2C */
+#define CONFIG_SYS_MAX_I2C_BUS	1
+
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT			/* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED	100000
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0
+
+#define I2C_SOFT_DECLARATIONS
+
+#define GPIO_I2C_SCL		AT91_PIO_PORTA, 24
+#define GPIO_I2C_SDA		AT91_PIO_PORTA, 23
+
+#define I2C_INIT { \
+	at91_set_pio_periph(AT91_PIO_PORTA, 23, 0); \
+	at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \
+	at91_set_pio_periph(AT91_PIO_PORTA, 24, 0); \
+	at91_set_pio_output(AT91_PIO_PORTA, 24, 0); \
+	at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \
+}
+
+#define I2C_ACTIVE	at91_set_pio_output(AT91_PIO_PORTA, 23, 0)
+#define I2C_TRISTATE	at91_set_pio_input(AT91_PIO_PORTA, 23, 0)
+#define I2C_SCL(bit)	at91_set_pio_value(AT91_PIO_PORTA, 24, bit)
+#define I2C_SDA(bit)	at91_set_pio_value(AT91_PIO_PORTA, 23, bit)
+#define I2C_DELAY	udelay(100)
+#define I2C_READ	at91_get_pio_value(AT91_PIO_PORTA, 23)
+
+/* DHCP/BOOTP options */
+#ifdef CONFIG_CMD_DHCP
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_SYS_AUTOLOAD	"n"
+#endif
+
+/* File systems */
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#if defined(CONFIG_CMD_MTDPARTS) || defined(CONFIG_CMD_NAND)
+#define MTDIDS_DEFAULT		"nand0=atmel_nand"
+#define MTDPARTS_DEFAULT	"mtdparts=atmel_nand:-(root)"
+#endif
+#if defined(CONFIG_CMD_REISER) || defined(CONFIG_CMD_EXT2) || \
+	defined(CONFIG_CMD_USB) || defined(CONFIG_MMC)
+#define CONFIG_DOS_PARTITION
+#endif
+#define CONFIG_LZO
+#define CONFIG_RBTREE
+
+/* Boot command */
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_BOOTCOMMAND	"cp.b 0xC00C6000 ${loadaddr} 0x294000; bootm"
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_BOOTARGS		"console=ttyS0,115200 " \
+				"root=/dev/mtdblock0 " \
+				MTDPARTS_DEFAULT \
+				" rw rootfstype=jffs2"
+#endif
+
+/* Misc. u-boot settings */
+#define CONFIG_SYS_PROMPT		"U-Boot> "
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + 16 \
+					+ sizeof(CONFIG_SYS_PROMPT))
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/exynos4-dt.h b/qemu/roms/u-boot/include/configs/exynos4-dt.h
new file mode 100644
index 000000000..cbd2d204c
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/exynos4-dt.h
@@ -0,0 +1,137 @@
+/*
+ * Copyright (C) 2014 Samsung Electronics
+ *
+ * Configuration settings for the SAMSUNG EXYNOS5 board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_SAMSUNG			/* in a SAMSUNG core */
+#define CONFIG_S5P			/* S5P Family */
+#define CONFIG_EXYNOS4			/* which is in a Exynos4 Family */
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_COMMON
+
+/* Enable fdt support */
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
+/* input clock of PLL: EXYNOS4 boards have 24MHz input clock */
+#define CONFIG_SYS_CLK_FREQ		24000000
+
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_EDITING
+
+#include <linux/sizes.h>
+
+/* SD/MMC configuration */
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_S5P_SDHCI
+#define CONFIG_SDHCI
+#define CONFIG_MMC_SDMA
+#define CONFIG_MMC_DEFAULT_DEV	0
+
+/* PWM */
+#define CONFIG_PWM
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Command definition*/
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_MISC
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_XIMG
+#undef CONFIG_CMD_CACHE
+#undef CONFIG_CMD_ONENAND
+#undef CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_DFU
+#define CONFIG_CMD_GPT
+#define CONFIG_CMD_PMIC
+#define CONFIG_CMD_SETEXPR
+
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+/* FAT */
+#define CONFIG_CMD_FAT
+#define CONFIG_FAT_WRITE
+
+/* EXT4 */
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+
+/* USB Composite download gadget - g_dnl */
+#define CONFIG_USBDOWNLOAD_GADGET
+
+/* TIZEN THOR downloader support */
+#define CONFIG_CMD_THOR_DOWNLOAD
+#define CONFIG_THOR_FUNCTION
+
+#define CONFIG_DFU_FUNCTION
+#define CONFIG_DFU_MMC
+#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M
+#define DFU_DEFAULT_POLL_TIMEOUT 300
+
+/* USB Samsung's IDs */
+#define CONFIG_G_DNL_VENDOR_NUM 0x04E8
+#define CONFIG_G_DNL_PRODUCT_NUM 0x6601
+#define CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM
+#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D
+#define CONFIG_G_DNL_MANUFACTURER "Samsung"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser	*/
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE		384	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
+
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+#define CONFIG_CMD_PART
+#define CONFIG_PARTITION_UUIDS
+
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_GADGET_S3C_UDC_OTG
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_VBUS_DRAW	2
+
+#define CONFIG_CMD_USB_MASS_STORAGE
+#define CONFIG_USB_GADGET_MASS_STORAGE
+
+/* Enable devicetree support */
+#define CONFIG_OF_LIBFDT
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/exynos5-dt.h b/qemu/roms/u-boot/include/configs/exynos5-dt.h
new file mode 100644
index 000000000..414db420d
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/exynos5-dt.h
@@ -0,0 +1,291 @@
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ *
+ * Configuration settings for the SAMSUNG EXYNOS5 board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_SAMSUNG			/* in a SAMSUNG core */
+#define CONFIG_S5P			/* S5P Family */
+#define CONFIG_EXYNOS5			/* which is in a Exynos5 Family */
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_COMMON
+#define CONFIG_ARCH_EARLY_INIT_R
+#define CONFIG_EXYNOS_SPL
+
+/* Enable fdt support for Exynos5250 */
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
+/* Allow tracing to be enabled */
+#define CONFIG_TRACE
+#define CONFIG_CMD_TRACE
+#define CONFIG_TRACE_BUFFER_SIZE	(16 << 20)
+#define CONFIG_TRACE_EARLY_SIZE		(8 << 20)
+#define CONFIG_TRACE_EARLY
+#define CONFIG_TRACE_EARLY_ADDR		0x50000000
+
+/* Keep L2 Cache Disabled */
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
+/* Enable ACE acceleration for SHA1 and SHA256 */
+#define CONFIG_EXYNOS_ACE_SHA
+#define CONFIG_SHA_HW_ACCEL
+
+/* input clock of PLL: SMDK5250 has 24MHz input clock */
+#define CONFIG_SYS_CLK_FREQ		24000000
+
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_EDITING
+
+/* Power Down Modes */
+#define S5P_CHECK_SLEEP			0x00000BAD
+#define S5P_CHECK_DIDLE			0xBAD00000
+#define S5P_CHECK_LPA			0xABAD0000
+
+/* Offset for inform registers */
+#define INFORM0_OFFSET			0x800
+#define INFORM1_OFFSET			0x804
+#define INFORM2_OFFSET			0x808
+#define INFORM3_OFFSET			0x80c
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (4 << 20))
+
+/* select serial console configuration */
+#define CONFIG_BAUDRATE			115200
+#define EXYNOS5_DEFAULT_UART_OFFSET	0x010000
+#define CONFIG_SILENT_CONSOLE
+
+/* Enable keyboard */
+#define CONFIG_CROS_EC		/* CROS_EC protocol */
+#define CONFIG_CROS_EC_SPI		/* Support CROS_EC over SPI */
+#define CONFIG_CROS_EC_I2C		/* Support CROS_EC over I2C */
+#define CONFIG_CROS_EC_KEYB	/* CROS_EC keyboard input */
+#define CONFIG_CMD_CROS_EC
+#define CONFIG_KEYBOARD
+
+/* Console configuration */
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define EXYNOS_DEVICE_SETTINGS \
+		"stdin=serial,cros-ec-keyb\0" \
+		"stdout=serial,lcd\0" \
+		"stderr=serial,lcd\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	EXYNOS_DEVICE_SETTINGS
+
+/* SD/MMC configuration */
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_SDHCI
+#define CONFIG_S5P_SDHCI
+#define CONFIG_DWMMC
+#define CONFIG_EXYNOS_DWMMC
+#define CONFIG_SUPPORT_EMMC_BOOT
+#define CONFIG_BOUNCE_BUFFER
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* PWM */
+#define CONFIG_PWM
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Command definition*/
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_HASH
+
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+/* Thermal Management Unit */
+#define CONFIG_EXYNOS_TMU
+#define CONFIG_CMD_DTT
+#define CONFIG_TMU_CMD_DTT
+
+/* TPM */
+#define CONFIG_TPM
+#define CONFIG_CMD_TPM
+#define CONFIG_TPM_TIS_I2C
+#define CONFIG_TPM_TIS_I2C_BUS_NUMBER	3
+#define CONFIG_TPM_TIS_I2C_SLAVE_ADDR	0x20
+
+/* MMC SPL */
+#define CONFIG_SPL
+#define COPY_BL2_FNPTR_ADDR	0x02020030
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+
+/* specific .lds file */
+#define CONFIG_SPL_LDSCRIPT	"board/samsung/common/exynos-uboot-spl.lds"
+#define CONFIG_SPL_MAX_FOOTPRINT	(14 * 1024)
+
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser	*/
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE		384	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC1,115200n8\0"
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5E00000)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x3E00000)
+
+#define CONFIG_RD_LVL
+
+#define CONFIG_NR_DRAM_BANKS	8
+#define SDRAM_BANK_SIZE		(256UL << 20UL)	/* 256 MB */
+#define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_1_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_2		(CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
+#define PHYS_SDRAM_2_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_3		(CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_3_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_4		(CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_4_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_5		(CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_5_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_6		(CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_6_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_7		(CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_7_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_8		(CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_8_SIZE	SDRAM_BANK_SIZE
+
+#define CONFIG_SYS_MONITOR_BASE	0x00000000
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_SYS_MMC_ENV_DEV		0
+
+#define CONFIG_SECURE_BL1_ONLY
+
+/* Secure FW size configuration */
+#ifdef CONFIG_SECURE_BL1_ONLY
+#define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */
+#else
+#define CONFIG_SEC_FW_SIZE 0
+#endif
+
+/* Configuration of BL1, BL2, ENV Blocks on mmc */
+#define CONFIG_RES_BLOCK_SIZE	(512)
+#define CONFIG_BL1_SIZE	(16 << 10) /*16 K reserved for BL1*/
+#define CONFIG_BL2_SIZE	(512UL << 10UL) /* 512 KB */
+#define CONFIG_ENV_SIZE	(16 << 10) /* 16 KB */
+
+#define CONFIG_BL1_OFFSET	(CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
+#define CONFIG_BL2_OFFSET	(CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
+#define CONFIG_ENV_OFFSET	(CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE)
+
+/* U-boot copy size from boot Media to DRAM.*/
+#define BL2_START_OFFSET	(CONFIG_BL2_OFFSET/512)
+#define BL2_SIZE_BLOC_COUNT	(CONFIG_BL2_SIZE/512)
+
+#define CONFIG_SPI_BOOTING
+#define EXYNOS_COPY_SPI_FNPTR_ADDR	0x02020058
+#define SPI_FLASH_UBOOT_POS	(CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
+
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+#define CONFIG_CMD_PART
+#define CONFIG_PARTITION_UUIDS
+
+/* I2C */
+#define CONFIG_SYS_I2C_INIT_BOARD
+#define CONFIG_SYS_I2C
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C_S3C24X0_SPEED	100000		/* 100 Kbps */
+#define CONFIG_SYS_I2C_S3C24X0
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C_S3C24X0_SLAVE    0x0
+#define CONFIG_I2C_EDID
+
+/* SPI */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_SPI_FLASH
+#define CONFIG_ENV_SPI_BASE	0x12D30000
+
+#ifdef CONFIG_SPI_FLASH
+#define CONFIG_EXYNOS_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SPI_FLASH_GIGADEVICE
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
+#define CONFIG_SF_DEFAULT_SPEED		50000000
+#define EXYNOS5_SPI_NUM_CONTROLLERS	5
+#define CONFIG_OF_SPI
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_MODE	SPI_MODE_0
+#define CONFIG_ENV_SECT_SIZE	CONFIG_ENV_SIZE
+#define CONFIG_ENV_SPI_BUS	1
+#define CONFIG_ENV_SPI_MAX_HZ	50000000
+#endif
+
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+
+/* Ethernet Controllor Driver */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_BASE		0x5000000
+#define CONFIG_SMC911X_16_BIT
+#define CONFIG_ENV_SROM_BANK		1
+#endif /*CONFIG_CMD_NET*/
+
+/* Enable PXE Support */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_CMD_PXE
+#define CONFIG_MENU
+#endif
+
+/* Enable devicetree support */
+#define CONFIG_OF_LIBFDT
+
+/* SHA hashing */
+#define CONFIG_CMD_HASH
+#define CONFIG_HASH_VERIFY
+#define CONFIG_SHA1
+#define CONFIG_SHA256
+
+/* Enable Time Command */
+#define CONFIG_CMD_TIME
+
+#define CONFIG_CMD_BOOTZ
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/exynos5250-dt.h b/qemu/roms/u-boot/include/configs/exynos5250-dt.h
new file mode 100644
index 000000000..b7ff47236
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/exynos5250-dt.h
@@ -0,0 +1,72 @@
+
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Configuration settings for the SAMSUNG EXYNOS5250 board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_5250_H
+#define __CONFIG_5250_H
+
+#include <configs/exynos5-dt.h>
+#define CONFIG_EXYNOS5250
+
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CONFIG_SYS_TEXT_BASE		0x43E00000
+
+/* MACH_TYPE_SMDK5250 macro will be removed once added to mach-types */
+#define MACH_TYPE_SMDK5250		3774
+#define CONFIG_MACH_TYPE		MACH_TYPE_SMDK5250
+
+/* USB */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_EXYNOS
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	2
+#define CONFIG_USB_STORAGE
+
+/* USB boot mode */
+#define CONFIG_USB_BOOTING
+#define EXYNOS_COPY_USB_FNPTR_ADDR	0x02020070
+#define EXYNOS_USB_SECONDARY_BOOT	0xfeed0002
+#define EXYNOS_IRAM_SECONDARY_BASE	0x02020018
+
+#define CONFIG_SPL_TEXT_BASE	0x02023400
+
+#define CONFIG_BOOTCOMMAND	"mmc read 40007000 451 2000; bootm 40007000"
+
+#define CONFIG_SYS_PROMPT		"SMDK5250 # "
+#define CONFIG_IDENT_STRING		" for SMDK5250"
+
+#define CONFIG_IRAM_STACK	0x02050000
+
+#define CONFIG_SYS_INIT_SP_ADDR	CONFIG_IRAM_STACK
+
+/* PMIC */
+#define CONFIG_PMIC_MAX77686
+
+/* Sound */
+#define CONFIG_CMD_SOUND
+#ifdef CONFIG_CMD_SOUND
+#define CONFIG_SOUND
+#define CONFIG_I2S_SAMSUNG
+#define CONFIG_I2S
+#define CONFIG_SOUND_MAX98095
+#define CONFIG_SOUND_WM8994
+#endif
+
+/* I2C */
+#define CONFIG_MAX_I2C_NUM	8
+
+/* Display */
+#define CONFIG_LCD
+#ifdef CONFIG_LCD
+#define CONFIG_EXYNOS_FB
+#define CONFIG_EXYNOS_DP
+#define LCD_XRES			2560
+#define LCD_YRES			1600
+#define LCD_BPP			LCD_COLOR16
+#endif
+#endif  /* __CONFIG_5250_H */
diff --git a/qemu/roms/u-boot/include/configs/favr-32-ezkit.h b/qemu/roms/u-boot/include/configs/favr-32-ezkit.h
new file mode 100644
index 000000000..338d3dc78
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/favr-32-ezkit.h
@@ -0,0 +1,182 @@
+/*
+ * Copyright (C) 2008 Atmel Corporation
+ *
+ * Configuration settings for the Favr-32 EarthLCD LCD kit.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/hardware.h>
+
+#define CONFIG_AT32AP
+#define CONFIG_AT32AP7000
+#define CONFIG_FAVR32_EZKIT
+
+#define CONFIG_FAVR32_EZKIT_EXT_FLASH
+
+/*
+ * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
+ * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
+ * PLL frequency.
+ * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz
+ */
+#define CONFIG_PLL
+#define CONFIG_SYS_POWER_MANAGER
+#define CONFIG_SYS_OSC0_HZ			20000000
+#define CONFIG_SYS_PLL0_DIV			1
+#define CONFIG_SYS_PLL0_MUL			7
+#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES	16
+/*
+ * Set the CPU running at:
+ * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
+ */
+#define CONFIG_SYS_CLKDIV_CPU			0
+/*
+ * Set the HSB running at:
+ * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
+ */
+#define CONFIG_SYS_CLKDIV_HSB			1
+/*
+ * Set the PBA running at:
+ * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
+ */
+#define CONFIG_SYS_CLKDIV_PBA			2
+/*
+ * Set the PBB running at:
+ * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
+ */
+#define CONFIG_SYS_CLKDIV_PBB			1
+
+/* Reserve VM regions for SDRAM and NOR flash */
+#define CONFIG_SYS_NR_VM_REGIONS		2
+
+/*
+ * The PLLOPT register controls the PLL like this:
+ *   icp = PLLOPT<2>
+ *   ivco = PLLOPT<1:0>
+ *
+ * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
+ */
+#define CONFIG_SYS_PLL0_OPT			0x04
+
+#define CONFIG_USART_BASE		ATMEL_BASE_USART3
+#define CONFIG_USART_ID			3
+
+/* User serviceable stuff */
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#define CONFIG_STACKSIZE		(2048)
+
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_BOOTARGS							\
+	"root=/dev/mtdblock1 rootfstype=jffs fbmem=1800k"
+
+#define CONFIG_BOOTCOMMAND						\
+	"fsload; bootm $(fileaddr)"
+
+/*
+ * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
+ * data on the serial line may interrupt the boot sequence.
+ */
+#define CONFIG_BOOTDELAY		1
+#define CONFIG_AUTOBOOT
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT		\
+	"Press SPACE to abort autoboot in %d seconds\n", bootdelay
+#define CONFIG_AUTOBOOT_DELAY_STR	"d"
+#define CONFIG_AUTOBOOT_STOP_STR	" "
+
+/*
+ * After booting the board for the first time, new ethernet addresses
+ * should be generated and assigned to the environment variables
+ * "ethaddr" and "eth1addr". This is normally done during production.
+ */
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MMC
+
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_SOURCE
+#undef CONFIG_CMD_XIMG
+
+#define CONFIG_ATMEL_USART
+#define CONFIG_MACB
+#define CONFIG_PORTMUX_PIO
+#define CONFIG_SYS_NR_PIOS			5
+#define CONFIG_SYS_HSDRAMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_ATMEL_MCI
+#define CONFIG_GENERIC_MMC
+
+#define CONFIG_SYS_DCACHE_LINESZ		32
+#define CONFIG_SYS_ICACHE_LINESZ		32
+
+#define CONFIG_NR_DRAM_BANKS		1
+
+/* External flash on Favr-32 */
+#if 0
+#define CONFIG_SYS_FLASH_CFI			1
+#define CONFIG_FLASH_CFI_DRIVER		1
+#endif
+
+#define CONFIG_SYS_FLASH_BASE			0x00000000
+#define CONFIG_SYS_FLASH_SIZE			0x800000
+#define CONFIG_SYS_MAX_FLASH_BANKS		1
+#define CONFIG_SYS_MAX_FLASH_SECT		135
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_TEXT_BASE		0x00000000
+
+#define CONFIG_SYS_INTRAM_BASE			INTERNAL_SRAM_BASE
+#define CONFIG_SYS_INTRAM_SIZE			INTERNAL_SRAM_SIZE
+#define CONFIG_SYS_SDRAM_BASE			EBI_SDRAM_BASE
+
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SIZE			65536
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
+
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
+
+#define CONFIG_SYS_MALLOC_LEN			(256*1024)
+#define CONFIG_SYS_DMA_ALLOC_LEN		(16384)
+
+/* Allow 4MB for the kernel run-time image */
+#define CONFIG_SYS_LOAD_ADDR			(EBI_SDRAM_BASE + 0x00400000)
+#define CONFIG_SYS_BOOTPARAMS_LEN		(16 * 1024)
+
+/* Other configuration settings that shouldn't have to change all that often */
+#define CONFIG_SYS_PROMPT			"U-Boot> "
+#define CONFIG_SYS_CBSIZE			256
+#define CONFIG_SYS_MAXARGS			16
+#define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+
+#define CONFIG_SYS_MEMTEST_START		EBI_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END			(CONFIG_SYS_MEMTEST_START + 0x700000)
+#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/flea3.h b/qemu/roms/u-boot/include/configs/flea3.h
new file mode 100644
index 000000000..84175676c
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/flea3.h
@@ -0,0 +1,258 @@
+/*
+ * (C) Copyright 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * Configuration for the flea3 board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+
+ /* High Level Configuration Options */
+#define CONFIG_ARM1136	/* This is an arm1136 CPU core */
+#define CONFIG_MX35
+
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
+#define CONFIG_DISPLAY_CPUINFO
+
+/* Only in case the value is not present in mach-types.h */
+#ifndef MACH_TYPE_FLEA3
+#define MACH_TYPE_FLEA3                3668
+#endif
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_FLEA3
+
+/* Set TEXT at the beginning of the NOR flash */
+#define CONFIG_SYS_TEXT_BASE	0xA0000000
+
+/* This is required to setup the ESDC controller */
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+#define CONFIG_REVISION_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 1024 * 1024)
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_SPD_BUS_NUM		2 /* I2C3 */
+#define CONFIG_SYS_MXC_I2C3_SLAVE	0xfe
+#define CONFIG_MXC_SPI
+#define CONFIG_MXC_GPIO
+
+/*
+ * UART (console)
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	UART3_BASE
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		115200
+
+/*
+ * Command definition
+ */
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_DNS
+
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_CACHE
+
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_NET_RETRY_COUNT	100
+
+#define CONFIG_BOOTDELAY	3
+
+#define CONFIG_LOADADDR		0x80800000	/* loadaddr env var */
+
+
+/*
+ * Ethernet on SOC (FEC)
+ */
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE	FEC_BASE_ADDR
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_FEC_MXC_PHYADDR	0x1
+
+#define CONFIG_MII
+
+#define CONFIG_ARP_TIMEOUT	200UL
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP	/* undef to save memory */
+#define CONFIG_SYS_PROMPT	"flea3 U-Boot > "
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_HUSH_PARSER	/* Use the HUSH parser */
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START	0	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x10000
+
+#undef	CONFIG_SYS_CLKS_IN_HZ	/* everything, incl board info, in Hz */
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM_1		CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE	(128 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE		CSD0_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR + 0x10000)
+#define CONFIG_SYS_INIT_RAM_SIZE		(IRAM_SIZE / 2)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					CONFIG_SYS_GBL_DATA_OFFSET)
+
+/*
+ * MTD Command for mtdparts
+ */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_FLASH_CFI_MTD
+#define CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT		"nand0=mxc_nand,nor0=physmap-flash.0"
+#define MTDPARTS_DEFAULT	"mtdparts=mxc_nand:50m(root1)," \
+				"32m(rootfb)," \
+				"64m(pcache)," \
+				"64m(app1)," \
+				"10m(app2),-(spool);" \
+				"physmap-flash.0:512k(u-boot),64k(env1)," \
+				"64k(env2),3776k(kernel1),3776k(kernel2)"
+
+/*
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_FLASH_BASE		CS0_BASE_ADDR
+#define CONFIG_SYS_MAX_FLASH_BANKS 1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512	/* max number of sectors on one chip */
+/* Monitor at beginning of flash */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+
+#define CONFIG_ENV_SECT_SIZE	(64 * 1024)
+#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + \
+				CONFIG_SYS_MONITOR_LEN)
+
+#define CONFIG_ENV_IS_IN_FLASH
+
+/*
+ * CFI FLASH driver setup
+ */
+#define CONFIG_SYS_FLASH_CFI		/* Flash memory is CFI compliant */
+#define CONFIG_FLASH_CFI_DRIVER
+
+/* A non-standard buffered write algorithm */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	/* faster */
+#define CONFIG_SYS_FLASH_PROTECTION	/* Use hardware sector protection */
+
+/*
+ * NAND FLASH driver setup
+ */
+#define CONFIG_NAND_MXC
+#define CONFIG_MXC_NAND_REGS_BASE	(NFC_BASE_ADDR)
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		(NFC_BASE_ADDR)
+#define CONFIG_MXC_NAND_HWECC
+#define CONFIG_SYS_NAND_LARGEPAGE
+
+/*
+ * Default environment and default scripts
+ * to update uboot and load kernel
+ */
+
+#define CONFIG_HOSTNAME flea3
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip_sta=setenv bootargs ${bootargs} "			\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0"		\
+	"addip=if test -n ${ipdyn};then run addip_dyn;"			\
+		"else run addip_sta;fi\0"				\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
+	"addtty=setenv bootargs ${bootargs}"				\
+		" console=ttymxc2,${baudrate}\0"			\
+	"addmisc=setenv bootargs ${bootargs} ${misc}\0"			\
+	"loadaddr=80800000\0"						\
+	"kernel_addr_r=80800000\0"					\
+	"hostname=" __stringify(CONFIG_HOSTNAME) "\0"			\
+	"bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0"		\
+	"ramdisk_file=" __stringify(CONFIG_HOSTNAME) "/uRamdisk\0"	\
+	"flash_self=run ramargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"flash_nfs=run nfsargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr}\0"				\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
+		"run nfsargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr_r}\0"				\
+	"net_self_load=tftp ${kernel_addr_r} ${bootfile};"		\
+		"tftp ${ramdisk_addr_r} ${ramdisk_file};\0"		\
+	"net_self=if run net_self_load;then "				\
+		"run ramargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr_r} ${ramdisk_addr_r};"		\
+		"else echo Images not loades;fi\0"			\
+	"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0"		\
+	"load=tftp ${loadaddr} ${u-boot}\0"				\
+	"uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0"		\
+	"update=protect off ${uboot_addr} +40000;"			\
+		"erase ${uboot_addr} +40000;"				\
+		"cp.b ${loadaddr} ${uboot_addr} ${filesize}\0"		\
+	"upd=if run load;then echo Updating u-boot;if run update;"	\
+		"then echo U-Boot updated;"				\
+			"else echo Error updating u-boot !;"		\
+			"echo Board without bootloader !!;"		\
+		"fi;"							\
+		"else echo U-Boot not downloaded..exiting;fi\0"		\
+	"bootcmd=run net_nfs\0"
+
+#endif				/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/fx12mm.h b/qemu/roms/u-boot/include/configs/fx12mm.h
new file mode 100644
index 000000000..d0083fd6f
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/fx12mm.h
@@ -0,0 +1,52 @@
+/*
+ * (C) Copyright 2008
+ *
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * This work has been supported by: QTechnology  http://qtec.com
+ *
+ * Georg Schardt <schardt@team-ctech.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Configuration file for the Virtex4FX12 Minimodul by Avnet/Memec,
+ * see http://www.em.avnet.com
+ */
+
+#ifndef __CONFIG_FX12_H
+#define __CONFIG_FX12_H
+
+#include "../board/avnet/fx12mm/xparameters.h"
+
+/* cmd config */
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
+#undef CONFIG_CMD_NET
+
+/* sdram */
+#define CONFIG_SYS_SDRAM_SIZE_MB       64
+
+/* environment */
+#define CONFIG_ENV_IS_IN_FLASH  1
+#define CONFIG_ENV_SIZE         0x10000
+#define CONFIG_ENV_SECT_SIZE    0x10000
+#define CONFIG_SYS_ENV_OFFSET   0xA0000
+#define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_ENV_OFFSET)
+#define CONFIG_ENV_OVERWRITE 	1
+
+/*Misc*/
+#define CONFIG_SYS_PROMPT	"FX12MM:/# " /* Monitor Command Prompt */
+#define CONFIG_PREBOOT      	"echo U-Boot is up and running;"
+
+/*Flash*/
+#define CONFIG_SYS_FLASH_SIZE          (4*1024*1024)
+#define CONFIG_SYS_MAX_FLASH_SECT      71
+#define MTDIDS_DEFAULT		"nor0=fx12mm-flash"
+#define MTDPARTS_DEFAULT	"mtdparts=fx12mm-flash:-(user)"
+
+#include "configs/xilinx-ppc405.h"
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/galaxy5200.h b/qemu/roms/u-boot/include/configs/galaxy5200.h
new file mode 100644
index 000000000..b555d82dd
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/galaxy5200.h
@@ -0,0 +1,431 @@
+/*
+ * (C) Copyright 2003-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2006
+ * Eric Schumann, Phytec Messatechnik GmbH
+ *
+ * (C) Copyright 2009
+ * Jon Smirl <jonsmirl@gmail.com>
+ *
+ * (C) Copyright 2009
+ * Eric Millbrandt, DEKA Research and Development Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_BOARDINFO	 "galaxy5200"
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MPC5200		1	/* This is an MPC5200 CPU */
+#define CONFIG_SYS_MPC5XXX_CLKIN 33333333	/* ... running at 33.333333MHz */
+
+/*
+ * Valid values for CONFIG_SYS_TEXT_BASE are:
+ * 0xFFF00000	boot high (standard configuration)
+ * 0xFE000000	boot low
+ * 0x00100000	boot from RAM (for testing only) does not work
+ */
+#ifdef CONFIG_galaxy5200_LOWBOOT
+#define	CONFIG_SYS_TEXT_BASE	0xFE000000
+#endif
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xFFF00000	/* Standard: boot high */
+#endif
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	4	/* console is on PSC4 -> */
+					/* define gps port conf. */
+					/* register later on to  */
+					/* enable UART function! */
+#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_FAT
+
+#define	CONFIG_TIMESTAMP	1	/* Print image info with timestamp */
+
+#if (CONFIG_SYS_TEXT_BASE == 0xFE000000)		/* Boot low */
+#define CONFIG_SYS_LOWBOOT 1
+#endif
+/* RAMBOOT will be defined automatically in memory section */
+
+#define MTDIDS_DEFAULT		"nor0=physmap-flash.0"
+#define MTDPARTS_DEFAULT	"mtdparts=physmap-flash.0:256k(ubootl)," \
+	"1792k(kernel),13312k(jffs2),256k(uboot)ro,256k(oftree),-(space)"
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	10	/* autoboot after 10 seconds */
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* allow stopping of boot process */
+					/* even with bootdelay=0 */
+#define CONFIG_BOOT_RETRY_TIME 120	/* Reset if no command is entered  */
+#define CONFIG_RESET_TO_RETRY
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Welcome to U-Boot;"\
+	"echo"
+
+#define CONFIG_BOOTCOMMAND     "go ff300004 0; go ff300004 2 2;" \
+	"bootm ff040000 ff900000 fffc0000"
+#define CONFIG_BOOTARGS        "console=ttyPSC0,115200"
+#define CONFIG_EXTRA_ENV_SETTINGS "epson=yes\0"
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK	/* define for 133MHz speed */
+#define CONFIG_SYS_XLB_PIPELINING	1
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C 1		/* I2C with hardware support */
+#define CONFIG_SYS_I2C_MODULE 2		/* Select I2C module #1 or #2 */
+#define CONFIG_SYS_I2C_SPEED 100000	/* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_INIT_MPC5XXX	/* Reset devices on i2c bus */
+
+/*
+ * EEPROM CAT24WC32 configuration
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x52	/* 1010100x */
+#define CONFIG_SYS_I2C_FACT_ADDR	0x52	/* EEPROM CAT24WC32 */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2	/* Bytes of address */
+#define CONFIG_SYS_EEPROM_SIZE		4096
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 15
+
+/*
+ * RTC configuration
+ */
+#define RTC
+#define CONFIG_RTC_DS3231		1
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68
+
+/*
+ * Flash configuration
+ */
+
+#define CONFIG_SYS_FLASH_BASE		0xfe000000
+/*
+ * The flash size is autoconfigured, but arch/powerpc/cpu/mpc5xxx/cpu_init.c needs this
+ * variable defined
+ */
+#define CONFIG_SYS_FLASH_SIZE		0x02000000
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+
+#define CONFIG_SYS_FLASH_CFI 1		/* Flash is CFI conformant */
+#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_MAX_FLASH_SECT 259	/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1	/* max num of flash banks */
+					/* (= chip selects) */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/*
+ * Use hardware protection. This seems required, as the BDI uses hardware
+ * protection. Without this, U-Boot can't work with this sectors as its
+ * protection is software only by default.
+ */
+#define CONFIG_SYS_FLASH_PROTECTION	1
+
+/*
+ * Environment settings
+ */
+
+#define CONFIG_ENV_IS_IN_EEPROM	1
+#define CONFIG_ENV_OFFSET	0x00	/* environment starts at the */
+					/* beginning of the EEPROM */
+#define CONFIG_ENV_SIZE		CONFIG_SYS_EEPROM_SIZE
+
+#define CONFIG_ENV_OVERWRITE	1
+
+/*
+ * SDRAM configuration
+ */
+#define SDRAM_DDR	1
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x71500F00
+#define SDRAM_CONFIG1	0x73711930
+#define SDRAM_CONFIG2	0x47770000
+
+/*
+ * Memory map
+ */
+#define CONFIG_SYS_MBAR	0xF0000000	/* MBAR has to be switched by other */
+					/* bootloader or debugger config */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR		0x80000000
+
+/* Use SRAM until RAM will be available */
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+
+/* End of used area in SPRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE		MPC5XXX_SRAM_SIZE
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+						GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#	define CONFIG_SYS_RAMBOOT		1
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN (192 << 10)	/* Reserve 192 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN (128 << 10)	/* Reserve 128 kB for malloc() */
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20)	/* Initial Memory map for Linux */
+
+/* Chip Select configuration for NAND flash */
+#define CONFIG_SYS_CS1_START		0x20000000
+#define CONFIG_SYS_CS1_SIZE		0x90000
+#define CONFIG_SYS_CS1_CFG		0x00025b00
+
+/* Chip Select configuration for Epson S1D13513 */
+#define CONFIG_SYS_CS3_START		0x10000000
+#define CONFIG_SYS_CS3_SIZE		0x400000
+#define CONFIG_SYS_CS3_CFG		0xffff3d10
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC		1
+#define CONFIG_MPC5xxx_FEC_MII100
+#define CONFIG_PHY_ADDR			0x01
+#define CONFIG_NO_AUTOLOAD		1
+
+/*
+ * GPIO configuration
+ *
+ * GPS port configuration
+ *
+ * [29:31] = 01x
+ * AC97 on PSC1
+ * PSC1_0 -> AC97 SDATA out
+ * PSC1_1 -> AC97 SDTA in
+ * PSC1_2 -> AC97 SYNC out
+ * PSC1_3 -> AC97 bitclock out
+ * PSC1_4 -> AC97 reset out
+ *
+ * [28] = Reserved
+ *
+ * [25:27] = 110
+ * SPI on PSC2
+ * PSC2_0 -> MOSI
+ * PSC2_1 -> MISO
+ * PSC2_2 -> n/a
+ * PSC2_3 -> CLK
+ * PSC2_4 -> SS
+ *
+ * [24] = Reserved
+ *
+ * [20:23] = 0001
+ * USB on PSC3
+ * PSC3_0 -> USB_OE OE out
+ * PSC3_1 -> USB_TXN Tx- out
+ * PSC3_2 -> USB_TXP Tx+ out
+ * PSC3_3 -> USB_TXD
+ * PSC3_4 -> USB_RXP Rx+ in
+ * PSC3_5 -> USB_RXN Rx- in
+ * PSC3_6 -> USB_PWR PortPower out
+ * PSC3_7 -> USB_SPEED speed out
+ * PSC3_8 -> USB_SUSPEND suspend
+ * PSC3_9 -> USB_OVRCURNT overcurrent in
+ *
+ * [18:19] = 10
+ * Two UARTs
+ *
+ * [17] = 0
+ * USB differential mode
+ *
+ * [16] = 1
+ * PCI disabled
+ *
+ * [12:15] = 0101
+ * Ethernet 100Mbit with MD
+ * ETH_0 -> ETH Txen
+ * ETH_1 -> ETH TxD0
+ * ETH_2 -> ETH TxD1
+ * ETH_3 -> ETH TxD2
+ * ETH_4 -> ETH TxD3
+ * ETH_5 -> ETH Txerr
+ * ETH_6 -> ETH MDC
+ * ETH_7 -> ETH MDIO
+ * ETH_8 -> ETH RxDv
+ * ETH_9 -> ETH RxCLK
+ * ETH_10 -> ETH Collision
+ * ETH_11 -> ETH TxD
+ * ETH_12 -> ETH RxD0
+ * ETH_13 -> ETH RxD1
+ * ETH_14 -> ETH RxD2
+ * ETH_15 -> ETH RxD3
+ * ETH_16 -> ETH Rxerr
+ * ETH_17 -> ETH CRS
+ *
+ * [9:11] = 111
+ * SPI on PSC6
+ * PSC6_0 -> MISO
+ * PSC6_1 -> SS#
+ * PSC6_2 -> MOSI
+ * PSC6_3 -> CLK
+ *
+ * [8] = 0
+ * IrDA/USB 48MHz clock generated internally
+ *
+ * [6:7] = 01
+ * ATA chip selects on csb_4/5
+ * CSB_4 -> ATA_CS0 out
+ * CSB_5 -> ATA_CS1 out
+ *
+ * [5] = 1
+ * PSC3_4 is used as CS6
+ *
+ * [4] = 1
+ * PSC3_5 is used as CS7
+ *
+ * [2:3] = 00
+ * No Alternatives
+ *
+ * [1] = 0
+ * gpio_wkup_7 is GPIO
+ *
+ * [0] = 0
+ * gpio_wkup_6 is GPIO
+ *
+ */
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x0d75a162
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_PROMPT "uboot> "		/* Monitor Command Prompt */
+
+#define CONFIG_CMDLINE_EDITING 1		/* add command line history */
+
+#define CONFIG_SYS_CACHELINE_SIZE 32		/* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT 5		/* log base 2 of the above value */
+#endif
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE 1024			/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE 512			/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+						/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 32			/* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START 0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x00f00000	/* 1 ... 15 MB in DRAM */
+
+#define CONFIG_SYS_LOAD_ADDR 0x400000		/* default load address */
+
+#define CONFIG_DISPLAY_BOARDINFO 1
+
+#define CONFIG_SYS_HUSH_PARSER 1
+
+#define CONFIG_CRC32_VERIFY  1
+
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+
+#define CONFIG_VERSION_VARIABLE 1
+
+/*
+ * Various low-level settings
+ */
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
+
+/* no burst access on the LPB */
+#define CONFIG_SYS_CS_BURST		0x00000000
+/* one deadcycle for the 33MHz statemachine */
+#define CONFIG_SYS_CS_DEADCYCLE		0x33333331
+
+#define CONFIG_SYS_BOOTCS_CFG		0x0002d900
+#define CONFIG_SYS_BOOTCS_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+
+#define CONFIG_SYS_RESET_ADDRESS	0xff000000
+
+/*
+ * USB settings
+ */
+#define CONFIG_USB_CLOCK		0x0001bbbb
+/* USB is on PSC3 */
+#define CONFIG_PSC3_USB
+#define CONFIG_USB_CONFIG		0x00000100
+#define CONFIG_USB_OHCI
+#define CONFIG_USB_STORAGE
+
+/*
+ * IDE/ATA stuff Supports IDE harddisk
+ */
+#undef  CONFIG_IDE_8xx_PCCARD	/* Use IDE with PC Card Adapter */
+#undef	CONFIG_IDE_8xx_DIRECT	/* Direct IDE not supported */
+#undef	CONFIG_IDE_LED		/* LED for ide not supported */
+
+#define	CONFIG_IDE_RESET 1	/* reset for ide supported */
+#define CONFIG_IDE_PREINIT
+#define CONFIG_SYS_IDE_MAXBUS 1	/* max. 1 IDE bus */
+#define CONFIG_SYS_IDE_MAXDEVICE 2	/* max. 2 drives per IDE bus */
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
+/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
+/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)
+/* Interval between registers */
+#define CONFIG_SYS_ATA_STRIDE		4
+#define CONFIG_ATAPI			1
+
+/* we enable IDE and FAT support, so we also need partition support */
+#define CONFIG_DOS_PARTITION 1
+
+/*
+ * Open Firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT		1
+#define CONFIG_OF_BOARD_SETUP		1
+
+#define OF_CPU				"PowerPC,5200@0"
+#define OF_TBCLK			CONFIG_SYS_MPC5XXX_CLKIN
+#define OF_SOC				"soc5200@f0000000"
+#define OF_STDOUT_PATH			"/soc5200@f0000000/serial@2600"
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/gdppc440etx.h b/qemu/roms/u-boot/include/configs/gdppc440etx.h
new file mode 100644
index 000000000..6810b3bef
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/gdppc440etx.h
@@ -0,0 +1,186 @@
+/*
+ * (C) Copyright 2008
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * Based on include/configs/yosemite.h
+ * (C) Copyright 2005-2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * gdppc440etx.h - configuration for G&D 440EP/GR ETX-Module
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_440GR		1		/* Specific PPC440GR support */
+#define CONFIG_HOSTNAME		gdppc440etx
+#define CONFIG_440		1		/* ... PPC440 family         */
+#define CONFIG_SYS_CLK_FREQ	66666666	/* external freq to pll      */
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFF80000
+
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#include "amcc-common.h"
+
+#define CONFIG_BOARD_EARLY_INIT_F	1	/* call board_early_init_f*/
+#define CONFIG_MISC_INIT_R		1	/* call misc_init_r()     */
+
+#undef CONFIG_ZERO_BOOTDELAY_CHECK     /* ignore keypress on bootdelay==0 */
+#define CONFIG_AUTOBOOT_KEYED          /* use key strings to stop autoboot */
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_FLASH_BASE		0xfc000000	/* start of FLASH    */
+#define CONFIG_SYS_PCI_MEMBASE		0xa0000000	/* mapped pci memory */
+#define CONFIG_SYS_PCI_MEMBASE1		CONFIG_SYS_PCI_MEMBASE  + 0x10000000
+#define CONFIG_SYS_PCI_MEMBASE2		CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
+#define CONFIG_SYS_PCI_MEMBASE3		CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
+
+/*Don't change either of these*/
+#define CONFIG_SYS_PCI_BASE		0xe0000000	/* internal PCI regs */
+/*Don't change either of these*/
+
+#define CONFIG_SYS_USB_DEVICE		0x50000000
+#define CONFIG_SYS_BOOT_BASE_ADDR	0xf0000000
+
+/*
+ * Initial RAM & stack pointer (placed in SDRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_DCACHE	1		/* d-cache as init ram*/
+#define CONFIG_SYS_INIT_RAM_ADDR	0x70000000	/* DCache             */
+#define CONFIG_SYS_INIT_RAM_SIZE		(4 << 10)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE \
+					 - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX	2	/* Use UART1			*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+#define CONFIG_SYS_EXT_SERIAL_CLOCK	11059200	/* ext. 11.059MHz clk */
+
+/*
+ * Environment
+ * Define here the location of the environment variables (FLASH or EEPROM).
+ * Note: DENX encourages to use redundant environment in FLASH.
+ */
+#define CONFIG_ENV_IS_IN_FLASH		1		/* FLASH for env. vars*/
+
+/*
+ * FLASH related
+ */
+#define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible*/
+#define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver      */
+#define CONFIG_SYS_FLASH_CFI_AMD_RESET	1	/* AMD RESET for STM 29W320DB!*/
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors/chip */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT 	120000	/* Timeout/Flash Erase (in ms)*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout/Flash Write (in ms)*/
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1/* use buffered writes (20x faster)*/
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE		0x20000 /* size of one complete sector*/
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE			0x2000 /* Total Size of Env. Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_ADDR_REDUND		(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND		(CONFIG_ENV_SIZE)
+#endif /* CONFIG_ENV_IS_IN_FLASH */
+
+/*
+ * DDR SDRAM
+ */
+#undef CONFIG_SPD_EEPROM		/* Don't use SPD EEPROM for setup*/
+#define CONFIG_SYS_KBYTES_SDRAM		(128 * 1024)    /* 128MB         */
+#define CONFIG_SYS_SDRAM_BANKS		(2)
+
+#define CONFIG_SDRAM_BANK0
+#define CONFIG_SDRAM_BANK1
+
+#define CONFIG_SYS_SDRAM0_TR0		0x410a4012
+#define CONFIG_SYS_SDRAM0_WDDCTR	0x40000000
+#define CONFIG_SYS_SDRAM0_RTR		0x04080000
+#define CONFIG_SYS_SDRAM0_CFG0		0x80000000
+
+#undef CONFIG_SDRAM_ECC
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_AMCC_DEF_ENV						\
+	CONFIG_AMCC_DEF_ENV_POWERPC					\
+	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
+	"kernel_addr=fc000000\0"					\
+	"ramdisk_addr=fc180000\0"					\
+	""
+
+#define CONFIG_HAS_ETH1			1	/* add support for "eth1addr" */
+#define CONFIG_PHY_ADDR			1
+#define CONFIG_PHY1_ADDR		3
+
+#ifdef DEBUG
+#define CONFIG_PANIC_HANG
+#endif
+
+/*
+ * Commands additional to the ones defined in amcc-common.h
+ */
+#define CONFIG_CMD_PCI
+#undef CONFIG_CMD_EEPROM
+
+/*
+ * PCI stuff
+ */
+
+/* General PCI */
+#define CONFIG_PCI				/* include pci support        */
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#undef  CONFIG_PCI_PNP				/* do (not) pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW			/* show pci devices on startup*/
+#define CONFIG_SYS_PCI_TARGBASE		0x80000000	/* PCIaddr mapped to \
+							CONFIG_SYS_PCI_MEMBASE*/
+
+/* Board-specific PCI */
+#define CONFIG_SYS_PCI_TARGET_INIT
+#define CONFIG_SYS_PCI_MASTER_INIT
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID	0x10e8	/* AMCC */
+#define CONFIG_SYS_PCI_SUBSYS_ID	0xcafe	/* tbd */
+
+/*
+ * External Bus Controller (EBC) Setup
+ */
+#define CONFIG_SYS_FLASH		CONFIG_SYS_FLASH_BASE
+
+/* Memory Bank 0 (NOR-FLASH) initialization */
+#define CONFIG_SYS_EBC_PB0AP		0x03017200
+#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_FLASH | 0xda000)
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/goflexhome.h b/qemu/roms/u-boot/include/configs/goflexhome.h
new file mode 100644
index 000000000..30a5859c5
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/goflexhome.h
@@ -0,0 +1,135 @@
+/*
+ * Copyright (C) 2013 Suriyan Ramasami <suriyan.r@gmail.com>
+ *
+ * Based on dockstar.h originally written by
+ * Copyright (C) 2010  Eric C. Cooper <ecc@cmu.edu>
+ *
+ * Based on sheevaplug.h originally written by
+ * Prafulla Wadaskar <prafulla@marvell.com>
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CONFIG_GOFLEXHOME_H
+#define _CONFIG_GOFLEXHOME_H
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING	"\nSeagate GoFlex Home"
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_FEROCEON_88FR131	1	/* CPU Core subversion */
+#define CONFIG_KIRKWOOD		1	/* SOC Family Name */
+#define CONFIG_KW88F6281	1	/* SOC Name */
+#define CONFIG_MACH_GOFLEXHOME		/* Machine type */
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+
+/*
+ * Default GPIO configuration and LED status
+ */
+#define GOFLEXHOME_OE_LOW               (~(0))
+#define GOFLEXHOME_OE_HIGH              (~(0))
+#define GOFLEXHOME_OE_VAL_LOW           (1 << 29)       /* USB_PWEN low */
+#define GOFLEXHOME_OE_VAL_HIGH          (1 << 17)       /* LED pin high */
+
+/* PHY related */
+#define MV88E1116_LED_FCTRL_REG         10
+#define MV88E1116_CPRSP_CR3_REG         21
+#define MV88E1116_MAC_CTRL_REG          21
+#define MV88E1116_PGADR_REG             22
+#define MV88E1116_RGMII_TXTM_CTRL       (1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL       (1 << 5)
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+#include <config_cmd_default.h>
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_EXT4
+#define CONFIG_SYS_MVFS         /* Picks up Filesystem from mv-common.h */
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+#undef CONFIG_SYS_PROMPT	/* previously defined in mv-common.h */
+#define CONFIG_SYS_PROMPT	"GoFlexHome> "	/* Command Prompt */
+
+/*
+ *  Environment variables configurations
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_ENV_IS_IN_NAND		1
+#define CONFIG_ENV_SECT_SIZE		0x20000	/* 128K */
+#else
+#define CONFIG_ENV_IS_NOWHERE		1	/* if env in SDRAM */
+#endif
+/*
+ * max 4k env size is enough, but in case of nand
+ * it has to be rounded to sector size
+ */
+#define CONFIG_ENV_SIZE			0x20000	/* 128k */
+#define CONFIG_ENV_ADDR			0xC0000
+#define CONFIG_ENV_OFFSET		0xC0000	/* env starts here */
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_BOOTCOMMAND \
+	"setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \
+	"ubi part root; " \
+	"ubifsmount ubi:root; " \
+	"ubifsload 0x800000 ${kernel}; " \
+	"bootm 0x800000"
+
+#define CONFIG_MTDPARTS \
+	"mtdparts=orion_nand:1m(uboot),6M(uImage),-(root)\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"console=console=ttyS0,115200\0" \
+	"mtdids=nand0=orion_nand\0" \
+	"mtdparts="CONFIG_MTDPARTS \
+	"kernel=/boot/uImage\0" \
+	"bootargs_root=ubi.mtd=root root=ubi0:root rootfstype=ubifs ro\0"
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS	{1, 0}	/* enable port 0 only */
+#define CONFIG_PHY_BASE_ADR	0
+#endif /* CONFIG_CMD_NET */
+
+/*
+ *  * SATA Driver configuration
+ *   */
+#ifdef CONFIG_MVSATA_IDE
+#define CONFIG_SYS_ATA_IDE0_OFFSET      MV_SATA_PORT0_OFFSET
+#endif /*CONFIG_MVSATA_IDE*/
+
+/*
+ *  * RTC driver configuration
+ *   */
+#ifdef CONFIG_CMD_DATE
+#define CONFIG_RTC_MV
+#endif /* CONFIG_CMD_DATE */
+
+#endif /* _CONFIG_GOFLEXHOME_H */
diff --git a/qemu/roms/u-boot/include/configs/gplugd.h b/qemu/roms/u-boot/include/configs/gplugd.h
new file mode 100644
index 000000000..404c56af1
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/gplugd.h
@@ -0,0 +1,134 @@
+/*
+ * (C) Copyright 2011
+ * eInfochips Ltd. <www.einfochips.com>
+ * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
+ *
+ * Based on Aspenite:
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_GPLUGD_H
+#define __CONFIG_GPLUGD_H
+
+/*
+ * FIXME: fix for error caused due to recent update to mach-types.h
+ */
+#include <asm/mach-types.h>
+#ifdef MACH_TYPE_SHEEVAD
+#error "MACH_TYPE_SHEEVAD has been defined properly, please remove this."
+#else
+#define MACH_TYPE_SHEEVAD	2625
+#endif
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING	"\nMarvell-gplugD"
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_SHEEVA_88SV331xV5	1	/* CPU Core subversion */
+#define CONFIG_ARMADA100		1	/* SOC Family Name */
+#define CONFIG_ARMADA168		1	/* SOC Used on this Board */
+#define CONFIG_MACH_TYPE		MACH_TYPE_SHEEVAD /* Machine type */
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+
+#define	CONFIG_SYS_TEXT_BASE	0x00f00000
+
+/*
+ * There is no internal RAM in ARMADA100, using DRAM
+ * TBD: dcache to be used for this
+ */
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE - 0x00200000)
+#define CONFIG_NR_DRAM_BANKS_MAX	2
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_I2C
+#undef CONFIG_CMD_FPGA
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+
+/* Disable DCACHE */
+#define CONFIG_SYS_DCACHE_OFF
+
+/* Network configuration */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_ARMADA100_FEC
+
+/* DHCP Support */
+#define CONFIG_CMD_DHCP
+#define CONFIG_BOOTP_DHCP_REQUEST_DELAY		50000
+#endif /* CONFIG_CMD_NET */
+
+/* GPIO Support */
+#define CONFIG_MARVELL_GPIO
+
+/* PHY configuration */
+#define CONFIG_MII
+#define CONFIG_CMD_MII
+#define CONFIG_RESET_PHY_R
+/* 88E3015 register definition */
+#define PHY_LED_PAR_SEL_REG		22
+#define PHY_LED_MAN_REG			25
+#define PHY_LED_VAL			0x5b	/* LINK LED1, ACT LED2 */
+/* GPIO Configuration for PHY */
+#define CONFIG_SYS_GPIO_PHY_RST		104	/* GPIO104 */
+
+/* SPI Support */
+#define CONFIG_ARMADA100_SPI
+#define CONFIG_ENV_SPI_CS		110
+#define CONFIG_SYS_SSP_PORT		2
+
+/* Flash Support */
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH_ATMEL
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+#undef CONFIG_ARCH_MISC_INIT
+
+#ifdef CONFIG_SYS_NS16550_COM1
+#undef CONFIG_SYS_NS16550_COM1
+#endif /* CONFIG_SYS_NS16550_COM1 */
+
+#define CONFIG_SYS_NS16550_COM1 ARMD1_UART3_BASE
+
+/*
+ * Environment variables configurations
+ */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SECT_SIZE		0x4000
+#define CONFIG_ENV_SIZE			0x4000
+#define CONFIG_ENV_OFFSET		0x07C000
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_EDITENV
+#define CONFIG_CMD_SAVEENV
+
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_ARMADA100
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_STORAGE
+#endif /* CONFIG_CMD_USB */
+
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+#define CONFIG_SUPPORT_VFAT
+
+#endif	/* __CONFIG_GPLUGD_H */
diff --git a/qemu/roms/u-boot/include/configs/gr_cpci_ax2000.h b/qemu/roms/u-boot/include/configs/gr_cpci_ax2000.h
new file mode 100644
index 000000000..854807d48
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/gr_cpci_ax2000.h
@@ -0,0 +1,358 @@
+/* Configuration header file for Gaisler GR-CPCI-AX2000
+ * AX board. Note that since the AX is removable the configuration
+ * for this board must be edited below.
+ *
+ * (C) Copyright 2003-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2008
+ * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H__
+#define __CONFIG_H__
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_CPCI_AX2000	1	/* ... on GR-CPCI-AX2000 board */
+
+#define CONFIG_LEON_RAM_SRAM 1
+#define CONFIG_LEON_RAM_SDRAM 2
+#define CONFIG_LEON_RAM_SDRAM_NOSRAM 3
+
+/* Select Memory to run from
+ *
+ * SRAM          - UBoot is run in SRAM, SRAM-0x40000000, SDRAM-0x60000000
+ * SDRAM         - UBoot is run in SDRAM, SRAM-0x40000000 and SDRAM-0x60000000
+ * SDRAM_NOSRAM  - UBoot is run in SDRAM, SRAM not available, SDRAM at 0x40000000
+ *
+ * Note, if Linux is to be used, SDRAM or SDRAM_NOSRAM is required since
+ * it doesn't fit into the 4Mb SRAM.
+ *
+ * SRAM is default since it will work for all systems, however will not
+ * be able to boot linux.
+ */
+#define CONFIG_LEON_RAM_SELECT CONFIG_LEON_RAM_SRAM
+
+/* CPU / AMBA BUS configuration */
+#define CONFIG_SYS_CLK_FREQ	20000000	/* 20MHz */
+
+/* Number of SPARC register windows */
+#define CONFIG_SYS_SPARC_NWINDOWS 8
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_BAUDRATE		38400	/* ... at 38400 bps */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/* Partitions */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION
+#define CONFIG_ISO_PARTITION
+
+/*
+ * Supported commands
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_AMBAPP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_IRQ
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS_BASE					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs console=ttyS0,38400 root=/dev/nfs rw "	\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"getkernel=tftpboot $(scratch) $(bootfile)\0" \
+	"bootargs=console=ttyS0,38400 root=/dev/nfs rw nfsroot=192.168.0.20:/export/rootfs ip=192.168.0.206:192.168.0.20:192.168.0.1:255.255.255.0:ax2000:eth0\0"
+
+#if CONFIG_LEON_RAM_SELECT == CONFIG_LEON_RAM_SRAM
+#define CONFIG_EXTRA_ENV_SETTINGS_SELECT \
+	"net_nfs=tftp 40000000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"scratch=40200000\0"					\
+	""
+#elif CONFIG_LEON_RAM_SELECT == CONFIG_LEON_RAM_SDRAM
+#define CONFIG_EXTRA_ENV_SETTINGS_SELECT \
+	"net_nfs=tftp 60000000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"scratch=60800000\0"					\
+	""
+#else
+/* More than 4Mb is assumed when running from SDRAM */
+#define CONFIG_EXTRA_ENV_SETTINGS_SELECT \
+	"net_nfs=tftp 40000000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"scratch=40800000\0"					\
+	""
+#endif
+
+#define	CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_SETTINGS_BASE CONFIG_EXTRA_ENV_SETTINGS_SELECT
+
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_GATEWAYIP 192.168.0.1
+#define CONFIG_SERVERIP 192.168.0.20
+#define CONFIG_IPADDR 192.168.0.206
+#define CONFIG_ROOTPATH "/export/rootfs"
+#define CONFIG_HOSTNAME  ax2000
+#define CONFIG_BOOTFILE "/uImage"
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+/* Memory MAP
+ *
+ *  Flash:
+ *  |--------------------------------|
+ *  | 0x00000000 Text & Data & BSS   | *
+ *  |            for Monitor         | *
+ *  | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| *
+ *  | UNUSED / Growth                | * 256kb
+ *  |--------------------------------|
+ *  | 0x00050000 Base custom area    | *
+ *  |            kernel / FS         | *
+ *  |                                | * Rest of Flash
+ *  |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~|
+ *  | END-0x00008000 Environment     | * 32kb
+ *  |--------------------------------|
+ *
+ *
+ *
+ *  Main Memory (4Mb SRAM or XMb SDRAM):
+ *  |--------------------------------|
+ *  | UNUSED / scratch area          |
+ *  |                                |
+ *  |                                |
+ *  |                                |
+ *  |                                |
+ *  |--------------------------------|
+ *  | Monitor .Text / .DATA / .BSS   | * 256kb
+ *  | Relocated!                     | *
+ *  |--------------------------------|
+ *  | Monitor Malloc                 | * 128kb (contains relocated environment)
+ *  |--------------------------------|
+ *  | Monitor/kernel STACK           | * 64kb
+ *  |--------------------------------|
+ *  | Page Table for MMU systems     | * 2k
+ *  |--------------------------------|
+ *  | PROM Code accessed from Linux  | * 6kb-128b
+ *  |--------------------------------|
+ *  | Global data (avail from kernel)| * 128b
+ *  |--------------------------------|
+ *
+ */
+
+/*
+ * Flash configuration (8,16 or 32 MB)
+ * TEXT base always at 0xFFF00000
+ * ENV_ADDR always at  0xFFF40000
+ * FLASH_BASE at 0xFC000000 for 64 MB
+ *               0xFE000000 for 32 MB
+ *               0xFF000000 for 16 MB
+ *               0xFF800000 for  8 MB
+ */
+/*#define CONFIG_SYS_NO_FLASH		1*/
+#define CONFIG_SYS_FLASH_BASE		0x00000000
+#define CONFIG_SYS_FLASH_SIZE		0x00800000
+
+#define PHYS_FLASH_SECT_SIZE	0x00020000	/* 128 KB sectors */
+#define CONFIG_SYS_MAX_FLASH_SECT	64	/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
+#define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
+
+/*** CFI CONFIG ***/
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+/* Bypass cache when reading regs from flash memory */
+#define CONFIG_SYS_FLASH_CFI_BYPASS_READ
+/* Buffered writes (32byte/go) instead of single accesses */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/*
+ * Environment settings
+ */
+/*#define CONFIG_ENV_IS_NOWHERE 1*/
+#define CONFIG_ENV_IS_IN_FLASH	1
+/* CONFIG_ENV_ADDR need to be at sector boundary */
+#define CONFIG_ENV_SIZE		0x8000
+#define CONFIG_ENV_SECT_SIZE	0x20000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE+CONFIG_SYS_FLASH_SIZE-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_OVERWRITE	1
+
+/*
+ * Memory map
+ *
+ * Always 4Mb SRAM available
+ * SDRAM module may be available on 0x60000000, SDRAM
+ * is configured as if a 128Mb SDRAM module is available.
+ */
+
+#if CONFIG_LEON_RAM_SELECT == CONFIG_LEON_RAM_SDRAM_NOSRAM
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#else
+#define CONFIG_SYS_SDRAM_BASE		0x60000000
+#endif
+
+#define CONFIG_SYS_SDRAM_SIZE		0x08000000
+#define CONFIG_SYS_SDRAM_END		(CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_SDRAM_SIZE)
+
+/* 4Mb SRAM available */
+#if CONFIG_LEON_RAM_SELECT != CONFIG_LEON_RAM_SDRAM_NOSRAM
+#define CONFIG_SYS_SRAM_BASE 0x40000000
+#define CONFIG_SYS_SRAM_SIZE 0x400000
+#define CONFIG_SYS_SRAM_END  (CONFIG_SYS_SRAM_BASE+CONFIG_SYS_SRAM_SIZE)
+#endif
+
+/* Select RAM used to run U-BOOT from... */
+#if CONFIG_LEON_RAM_SELECT == CONFIG_LEON_RAM_SRAM
+#define CONFIG_SYS_RAM_BASE CONFIG_SYS_SRAM_BASE
+#define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SRAM_SIZE
+#define CONFIG_SYS_RAM_END CONFIG_SYS_SRAM_END
+#else
+#define CONFIG_SYS_RAM_BASE CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SDRAM_SIZE
+#define CONFIG_SYS_RAM_END CONFIG_SYS_SDRAM_END
+#endif
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_RAM_END - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_PROM_SIZE		(8192-GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_PROM_OFFSET		(CONFIG_SYS_GBL_DATA_OFFSET-CONFIG_SYS_PROM_SIZE)
+
+#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_PROM_OFFSET-32)
+#define CONFIG_SYS_STACK_SIZE		(0x10000-32)
+
+#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor   */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()  */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+#define CONFIG_SYS_MALLOC_END		(CONFIG_SYS_INIT_SP_OFFSET-CONFIG_SYS_STACK_SIZE)
+#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MALLOC_END-CONFIG_SYS_MALLOC_LEN)
+
+/* relocated monitor area */
+#define CONFIG_SYS_RELOC_MONITOR_MAX_END   CONFIG_SYS_MALLOC_BASE
+#define CONFIG_SYS_RELOC_MONITOR_BASE     (CONFIG_SYS_RELOC_MONITOR_MAX_END-CONFIG_SYS_MONITOR_LEN)
+
+/* make un relocated address from relocated address */
+#define UN_RELOC(address) (address-(CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE))
+
+/*
+ * Ethernet configuration uses on board SMC91C111
+ */
+#define CONFIG_SMC91111          1
+#define CONFIG_SMC91111_BASE		0x20000300	/* chip select 3         */
+#define CONFIG_SMC_USE_32_BIT		1	/* 32 bit bus  */
+#undef  CONFIG_SMC_91111_EXT_PHY	/* we use internal phy   */
+/*#define CONFIG_SHOW_ACTIVITY*/
+#define CONFIG_NET_RETRY_COUNT		10	/* # of retries          */
+
+#define CONFIG_ETHADDR   00:00:7a:cc:00:13
+#define CONFIG_PHY_ADDR	 0x00
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory     */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args   */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM  */
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
+
+/*
+ * Various low-level settings
+ */
+
+/*-----------------------------------------------------------------------
+ * USB stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_USB_CLOCK	0x0001BBBB
+#define CONFIG_USB_CONFIG	0x00005000
+
+/***** Gaisler GRLIB IP-Cores Config ********/
+
+/* AMBA Plug & Play info display on startup */
+/*#define CONFIG_SYS_AMBAPP_PRINT_ON_STARTUP*/
+
+#define CONFIG_SYS_GRLIB_SDRAM    0
+
+/* See, GRLIB Docs (grip.pdf) on how to set up
+ * These the memory controller registers.
+ */
+#define CONFIG_SYS_GRLIB_MEMCFG1   (0x10f800ff | (1<<11))
+#if CONFIG_LEON_RAM_SELECT == CONFIG_LEON_RAM_SDRAM_NOSRAM
+#define CONFIG_SYS_GRLIB_MEMCFG2   0x82206000
+#else
+#define CONFIG_SYS_GRLIB_MEMCFG2   0x82205260
+#endif
+#define CONFIG_SYS_GRLIB_MEMCFG3   0x0809a000
+
+#define CONFIG_SYS_GRLIB_FT_MEMCFG1   (0x10f800ff | (1<<11))
+#if CONFIG_LEON_RAM_SELECT == CONFIG_LEON_RAM_SDRAM_NOSRAM
+#define CONFIG_SYS_GRLIB_FT_MEMCFG2   0x82206000
+#else
+#define CONFIG_SYS_GRLIB_FT_MEMCFG2   0x82205260
+#endif
+#define CONFIG_SYS_GRLIB_FT_MEMCFG3   0x0809a000
+
+/* no DDR controller */
+#define CONFIG_SYS_GRLIB_DDR_CFG   0x00000000
+
+/* no DDR2 Controller */
+#define CONFIG_SYS_GRLIB_DDR2_CFG1 0x00000000
+#define CONFIG_SYS_GRLIB_DDR2_CFG3 0x00000000
+
+/* Calculate scaler register value from default baudrate */
+#define CONFIG_SYS_GRLIB_APBUART_SCALER \
+ ((((CONFIG_SYS_CLK_FREQ*10)/(CONFIG_BAUDRATE*8))-5)/10)
+
+/* Identification string */
+#define CONFIG_IDENT_STRING "GAISLER LEON3 GR-CPCI-AX2000"
+
+/* default kernel command line */
+#define CONFIG_DEFAULT_KERNEL_COMMAND_LINE "console=ttyS0,38400\0\0"
+
+#endif				/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/gr_ep2s60.h b/qemu/roms/u-boot/include/configs/gr_ep2s60.h
new file mode 100644
index 000000000..ed2dd2a84
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/gr_ep2s60.h
@@ -0,0 +1,333 @@
+/* Configuration header file for Gaisler Research AB's Template
+ * design (GPL Open Source SPARC/LEON3 96MHz) for Altera NIOS
+ * Development board Stratix II edition, with the FPGA device
+ * EP2S60.
+ *
+ * (C) Copyright 2003-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2008
+ * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H__
+#define __CONFIG_H__
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+/* Altera NIOS Development board, Stratix II board */
+#define CONFIG_GR_EP2S60	1
+
+/* CPU / AMBA BUS configuration */
+#define CONFIG_SYS_CLK_FREQ	96000000	/* 96MHz */
+
+/* Number of SPARC register windows */
+#define CONFIG_SYS_SPARC_NWINDOWS 8
+
+/* Define this is the GR-2S60-MEZZ mezzanine is available and you
+ * want to use the USB and GRETH functionality of the board
+ */
+#undef GR_2S60_MEZZ
+
+#ifdef GR_2S60_MEZZ
+#define USE_GRETH 1
+#define USE_GRUSB 1
+#endif
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_BAUDRATE		38400	/* ... at 38400 bps */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/* Partitions */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION
+#define CONFIG_ISO_PARTITION
+
+/*
+ * Supported commands
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_AMBAPP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_IRQ
+
+/* USB support */
+#if USE_GRUSB
+#define CONFIG_USB_UHCI
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+/* Enable needed helper functions */
+#define CONFIG_SYS_STDIO_DEREGISTER	/* needs stdio_deregister */
+#endif
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs console=ttyS0,38400 root=/dev/nfs rw "	\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 40000000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"scratch=40800000\0"					\
+	"getkernel=tftpboot $(scratch) $(bootfile)\0" \
+	"bootargs=console=ttyS0,38400 root=/dev/nfs rw nfsroot=192.168.0.20:/export/rootfs ip=192.168.0.207:192.168.0.20:192.168.0.1:255.255.255.0:ml401:eth0\0" \
+	""
+
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_GATEWAYIP 192.168.0.1
+#define CONFIG_SERVERIP 192.168.0.20
+#define CONFIG_IPADDR 192.168.0.207
+#define CONFIG_ROOTPATH "/export/rootfs"
+#define CONFIG_HOSTNAME  ml401
+#define CONFIG_BOOTFILE "/uImage"
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+/* Memory MAP
+ *
+ *  Flash:
+ *  |--------------------------------|
+ *  | 0x00000000 Text & Data & BSS   | *
+ *  |            for Monitor         | *
+ *  | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| *
+ *  | UNUSED / Growth                | * 256kb
+ *  |--------------------------------|
+ *  | 0x00050000 Base custom area    | *
+ *  |            kernel / FS         | *
+ *  |                                | * Rest of Flash
+ *  |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~|
+ *  | END-0x00008000 Environment     | * 32kb
+ *  |--------------------------------|
+ *
+ *
+ *
+ *  Main Memory:
+ *  |--------------------------------|
+ *  | UNUSED / scratch area          |
+ *  |                                |
+ *  |                                |
+ *  |                                |
+ *  |                                |
+ *  |--------------------------------|
+ *  | Monitor .Text / .DATA / .BSS   | * 512kb
+ *  | Relocated!                     | *
+ *  |--------------------------------|
+ *  | Monitor Malloc                 | * 128kb (contains relocated environment)
+ *  |--------------------------------|
+ *  | Monitor/kernel STACK           | * 64kb
+ *  |--------------------------------|
+ *  | Page Table for MMU systems     | * 2k
+ *  |--------------------------------|
+ *  | PROM Code accessed from Linux  | * 6kb-128b
+ *  |--------------------------------|
+ *  | Global data (avail from kernel)| * 128b
+ *  |--------------------------------|
+ *
+ */
+
+/*
+ * Flash configuration (8,16 or 32 MB)
+ * TEXT base always at 0xFFF00000
+ * ENV_ADDR always at  0xFFF40000
+ * FLASH_BASE at 0xFC000000 for 64 MB
+ *               0xFE000000 for 32 MB
+ *               0xFF000000 for 16 MB
+ *               0xFF800000 for  8 MB
+ */
+/*#define CONFIG_SYS_NO_FLASH		1*/
+#define CONFIG_SYS_FLASH_BASE		0x00000000
+#define CONFIG_SYS_FLASH_SIZE		0x00400000	/* FPGA Bit file is in top of FLASH, we only ues the bottom 4Mb */
+
+#define PHYS_FLASH_SECT_SIZE	0x00010000	/* 64 KB sectors */
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
+#define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
+
+/*** CFI CONFIG ***/
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+/* Bypass cache when reading regs from flash memory */
+#define CONFIG_SYS_FLASH_CFI_BYPASS_READ
+/* Buffered writes (32byte/go) instead of single accesses */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/*
+ * Environment settings
+ */
+/*#define CONFIG_ENV_IS_NOWHERE 1*/
+#define CONFIG_ENV_IS_IN_FLASH	1
+/* CONFIG_ENV_ADDR need to be at sector boundary */
+#define CONFIG_ENV_SIZE		0x8000
+#define CONFIG_ENV_SECT_SIZE	0x20000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE+CONFIG_SYS_FLASH_SIZE-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_OVERWRITE	1
+
+/*
+ * Memory map
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CONFIG_SYS_SDRAM_SIZE		0x02000000
+#define CONFIG_SYS_SDRAM_END		(CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_SDRAM_SIZE)
+
+/* no SRAM available */
+#undef CONFIG_SYS_SRAM_BASE
+#undef CONFIG_SYS_SRAM_SIZE
+
+#define CONFIG_SYS_RAM_BASE CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SDRAM_SIZE
+#define CONFIG_SYS_RAM_END CONFIG_SYS_SDRAM_END
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_SDRAM_END - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_PROM_SIZE		(8192-GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_PROM_OFFSET		(CONFIG_SYS_GBL_DATA_OFFSET-CONFIG_SYS_PROM_SIZE)
+
+#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_PROM_OFFSET-32)
+#define CONFIG_SYS_STACK_SIZE		(0x10000-32)
+
+#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN		(512 << 10)	/* Reserve 512 kB for Monitor   */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()  */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+#define CONFIG_SYS_MALLOC_END		(CONFIG_SYS_INIT_SP_OFFSET-CONFIG_SYS_STACK_SIZE)
+#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MALLOC_END-CONFIG_SYS_MALLOC_LEN)
+
+/* relocated monitor area */
+#define CONFIG_SYS_RELOC_MONITOR_MAX_END   CONFIG_SYS_MALLOC_BASE
+#define CONFIG_SYS_RELOC_MONITOR_BASE     (CONFIG_SYS_RELOC_MONITOR_MAX_END-CONFIG_SYS_MONITOR_LEN)
+
+/* make un relocated address from relocated address */
+#define UN_RELOC(address) (address-(CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE))
+
+/*
+ * Ethernet configuration uses on board SMC91C111, however if a mezzanine
+ * with a PHY is attached the GRETH can be used on this board.
+ * Define USE_GRETH in order to use the mezzanine provided PHY with the
+ * onchip GRETH network MAC, note that this is not supported by the
+ * template design.
+ */
+#ifndef USE_GRETH
+
+/* USE SMC91C111 MAC */
+#define CONFIG_SMC91111          1
+#define CONFIG_SMC91111_BASE		0x20000300	/* chip select 3         */
+#define CONFIG_SMC_USE_32_BIT		1	/* 32 bit bus  */
+#undef  CONFIG_SMC_91111_EXT_PHY	/* we use internal phy   */
+/*#define CONFIG_SHOW_ACTIVITY*/
+#define CONFIG_NET_RETRY_COUNT		10	/* # of retries          */
+
+#else
+
+/* USE GRETH Ethernet Driver */
+#define CONFIG_GRETH	1
+
+/* Default GRETH Ethernet HARDWARE address */
+#define GRETH_HWADDR_0 0x00
+#define GRETH_HWADDR_1 0x00
+#define GRETH_HWADDR_2 0x7a
+#define GRETH_HWADDR_3 0xcc
+#define GRETH_HWADDR_4 0x00
+#define GRETH_HWADDR_5 0x13
+#endif
+
+#define CONFIG_ETHADDR   00:00:7a:cc:00:13
+#define CONFIG_PHY_ADDR	 0x00
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory     */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args   */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM  */
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
+
+/*-----------------------------------------------------------------------
+ * USB stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_USB_CLOCK	0x0001BBBB
+#define CONFIG_USB_CONFIG	0x00005000
+
+/***** Gaisler GRLIB IP-Cores Config ********/
+
+/* AMBA Plug & Play info display on startup */
+/*#define CONFIG_SYS_AMBAPP_PRINT_ON_STARTUP*/
+
+#define CONFIG_SYS_GRLIB_SDRAM    0
+
+/* See, GRLIB Docs (grip.pdf) on how to set up
+ * These the memory controller registers.
+ */
+#define CONFIG_SYS_GRLIB_MEMCFG1  (0x10f800ff | (1<<11))
+#define CONFIG_SYS_GRLIB_MEMCFG2  0x00000000
+#define CONFIG_SYS_GRLIB_MEMCFG3  0x00000000
+
+#define CONFIG_SYS_GRLIB_FT_MEMCFG1  (0x10f800ff | (1<<11))
+#define CONFIG_SYS_GRLIB_FT_MEMCFG2  0x00000000
+#define CONFIG_SYS_GRLIB_FT_MEMCFG3  0x00000000
+
+#define CONFIG_SYS_GRLIB_DDR_CFG  0xa900830a
+
+#define CONFIG_SYS_GRLIB_DDR2_CFG1 0x00000000
+#define CONFIG_SYS_GRLIB_DDR2_CFG3 0x00000000
+
+/* Calculate scaler register value from default baudrate */
+#define CONFIG_SYS_GRLIB_APBUART_SCALER \
+ ((((CONFIG_SYS_CLK_FREQ*10)/(CONFIG_BAUDRATE*8))-5)/10)
+
+/* Identification string */
+#define CONFIG_IDENT_STRING "GAISLER LEON3 EP2S60"
+
+/* default kernel command line */
+#define CONFIG_DEFAULT_KERNEL_COMMAND_LINE "console=ttyS0,38400\0\0"
+
+#endif				/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/gr_xc3s_1500.h b/qemu/roms/u-boot/include/configs/gr_xc3s_1500.h
new file mode 100644
index 000000000..e3cbb6f59
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/gr_xc3s_1500.h
@@ -0,0 +1,298 @@
+/* Configuration header file for Gaisler GR-XC3S-1500
+ * spartan board.
+ *
+ * (C) Copyright 2003-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2007
+ * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H__
+#define __CONFIG_H__
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_GRXC3S1500	1	/* ... on GR-XC3S-1500 board */
+
+/* CPU / AMBA BUS configuration */
+#define CONFIG_SYS_CLK_FREQ	40000000	/* 40MHz */
+
+/* Number of SPARC register windows */
+#define CONFIG_SYS_SPARC_NWINDOWS 8
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_BAUDRATE		38400	/* ... at 38400 bps */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/* Partitions */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION
+#define CONFIG_ISO_PARTITION
+
+/*
+ * Supported commands
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_AMBAPP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_IRQ
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs console=ttyS0,38400 root=/dev/nfs rw "	\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 40000000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"scratch=40200000\0"					\
+	"getkernel=tftpboot $(scratch) $(bootfile)\0" \
+	"bootargs=console=ttyS0,38400 root=/dev/nfs rw nfsroot=192.168.0.20:/export/rootfs ip=192.168.0.206:192.168.0.20:192.168.0.1:255.255.255.0:grxc3s1500_daniel:eth0\0" \
+	""
+
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_GATEWAYIP 192.168.0.1
+#define CONFIG_SERVERIP 192.168.0.20
+#define CONFIG_IPADDR 192.168.0.206
+#define CONFIG_ROOTPATH "/export/rootfs"
+#define CONFIG_HOSTNAME  grxc3s1500
+#define CONFIG_BOOTFILE "/uImage"
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+/* Memory MAP
+ *
+ *  Flash:
+ *  |--------------------------------|
+ *  | 0x00000000 Text & Data & BSS   | *
+ *  |            for Monitor         | *
+ *  | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| *
+ *  | UNUSED / Growth                | * 256kb
+ *  |--------------------------------|
+ *  | 0x00050000 Base custom area    | *
+ *  |            kernel / FS         | *
+ *  |                                | * Rest of Flash
+ *  |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~|
+ *  | END-0x00008000 Environment     | * 32kb
+ *  |--------------------------------|
+ *
+ *
+ *
+ *  Main Memory:
+ *  |--------------------------------|
+ *  | UNUSED / scratch area          |
+ *  |                                |
+ *  |                                |
+ *  |                                |
+ *  |                                |
+ *  |--------------------------------|
+ *  | Monitor .Text / .DATA / .BSS   | * 256kb
+ *  | Relocated!                     | *
+ *  |--------------------------------|
+ *  | Monitor Malloc                 | * 128kb (contains relocated environment)
+ *  |--------------------------------|
+ *  | Monitor/kernel STACK           | * 64kb
+ *  |--------------------------------|
+ *  | Page Table for MMU systems     | * 2k
+ *  |--------------------------------|
+ *  | PROM Code accessed from Linux  | * 6kb-128b
+ *  |--------------------------------|
+ *  | Global data (avail from kernel)| * 128b
+ *  |--------------------------------|
+ *
+ */
+
+/*
+ * Flash configuration (8,16 or 32 MB)
+ * TEXT base always at 0xFFF00000
+ * ENV_ADDR always at  0xFFF40000
+ * FLASH_BASE at 0xFC000000 for 64 MB
+ *               0xFE000000 for 32 MB
+ *               0xFF000000 for 16 MB
+ *               0xFF800000 for  8 MB
+ */
+/*#define CONFIG_SYS_NO_FLASH		1*/
+#define CONFIG_SYS_FLASH_BASE		0x00000000
+#define CONFIG_SYS_FLASH_SIZE		0x00800000
+
+#define PHYS_FLASH_SECT_SIZE	0x00020000	/* 128 KB sectors */
+#define CONFIG_SYS_MAX_FLASH_SECT	64	/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
+#define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
+
+/*** CFI CONFIG ***/
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+/* Bypass cache when reading regs from flash memory */
+#define CONFIG_SYS_FLASH_CFI_BYPASS_READ
+/* Buffered writes (32byte/go) instead of single accesses */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/*
+ * Environment settings
+ */
+/*#define CONFIG_ENV_IS_NOWHERE 1*/
+#define CONFIG_ENV_IS_IN_FLASH	1
+/* CONFIG_ENV_ADDR need to be at sector boundary */
+#define CONFIG_ENV_SIZE		0x8000
+#define CONFIG_ENV_SECT_SIZE	0x20000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE+CONFIG_SYS_FLASH_SIZE-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_OVERWRITE	1
+
+/*
+ * Memory map
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CONFIG_SYS_SDRAM_SIZE		0x4000000
+#define CONFIG_SYS_SDRAM_END		(CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_SDRAM_SIZE)
+
+/* no SRAM available */
+#undef CONFIG_SYS_SRAM_BASE
+#undef CONFIG_SYS_SRAM_SIZE
+
+/* Always Run U-Boot from SDRAM */
+#define CONFIG_SYS_RAM_BASE CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SDRAM_SIZE
+#define CONFIG_SYS_RAM_END CONFIG_SYS_SDRAM_END
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_RAM_END - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_PROM_SIZE		(8192-GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_PROM_OFFSET		(CONFIG_SYS_GBL_DATA_OFFSET-CONFIG_SYS_PROM_SIZE)
+
+#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_PROM_OFFSET-32)
+#define CONFIG_SYS_STACK_SIZE		(0x10000-32)
+
+#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor   */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()  */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+#define CONFIG_SYS_MALLOC_END		(CONFIG_SYS_INIT_SP_OFFSET-CONFIG_SYS_STACK_SIZE)
+#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MALLOC_END-CONFIG_SYS_MALLOC_LEN)
+
+/* relocated monitor area */
+#define CONFIG_SYS_RELOC_MONITOR_MAX_END   CONFIG_SYS_MALLOC_BASE
+#define CONFIG_SYS_RELOC_MONITOR_BASE     (CONFIG_SYS_RELOC_MONITOR_MAX_END-CONFIG_SYS_MONITOR_LEN)
+
+/* make un relocated address from relocated address */
+#define UN_RELOC(address) (address-(CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE))
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_GRETH	1
+
+/* Default GRETH Ethernet HARDWARE address */
+#define GRETH_HWADDR_0 0x00
+#define GRETH_HWADDR_1 0x00
+#define GRETH_HWADDR_2 0x7a
+#define GRETH_HWADDR_3 0xcc
+#define GRETH_HWADDR_4 0x00
+#define GRETH_HWADDR_5 0x12
+
+#define CONFIG_ETHADDR   00:00:7a:cc:00:12
+#define CONFIG_PHY_ADDR	 0x00
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory     */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args   */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM  */
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
+
+/*
+ * Various low-level settings
+ */
+
+/*-----------------------------------------------------------------------
+ * USB stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_USB_CLOCK	0x0001BBBB
+#define CONFIG_USB_CONFIG	0x00005000
+
+/***** Gaisler GRLIB IP-Cores Config ********/
+
+/* AMBA Plug & Play info display on startup */
+/*#define CONFIG_SYS_AMBAPP_PRINT_ON_STARTUP*/
+
+#define CONFIG_SYS_GRLIB_SDRAM    0
+
+/* See, GRLIB Docs (grip.pdf) on how to set up
+ * These the memory controller registers.
+ */
+#define CONFIG_SYS_GRLIB_MEMCFG1   (0x000000ff | (1<<11))
+#define CONFIG_SYS_GRLIB_MEMCFG2   0x82206000
+#define CONFIG_SYS_GRLIB_MEMCFG3   0x00136000
+
+#define CONFIG_SYS_GRLIB_FT_MEMCFG1   (0x000000ff | (1<<11))
+#define CONFIG_SYS_GRLIB_FT_MEMCFG2   0x82206000
+#define CONFIG_SYS_GRLIB_FT_MEMCFG3   0x00136000
+
+/* no DDR controller */
+#define CONFIG_SYS_GRLIB_DDR_CFG   0x00000000
+
+/* no DDR2 Controller */
+#define CONFIG_SYS_GRLIB_DDR2_CFG1 0x00000000
+#define CONFIG_SYS_GRLIB_DDR2_CFG3 0x00000000
+
+/* Calculate scaler register value from default baudrate */
+#define CONFIG_SYS_GRLIB_APBUART_SCALER \
+ ((((CONFIG_SYS_CLK_FREQ*10)/(CONFIG_BAUDRATE*8))-5)/10)
+
+/* Identification string */
+#define CONFIG_IDENT_STRING "GAISLER LEON3 GR-XC3S-1500"
+
+/* default kernel command line */
+#define CONFIG_DEFAULT_KERNEL_COMMAND_LINE "console=ttyS0,38400\0\0"
+
+#endif				/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/grasshopper.h b/qemu/roms/u-boot/include/configs/grasshopper.h
new file mode 100644
index 000000000..73534addf
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/grasshopper.h
@@ -0,0 +1,172 @@
+/*
+ * Copyright (C) 2011
+ * Corscience GmbH & Co.KG, Andreas Bießmann <biessmann@corscience.de>
+ *
+ * Configuration settings for the grasshopper (ICnova AP7000) board
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __GRASSHOPPER_CONFIG_H
+#define __GRASSHOPPER_CONFIG_H
+
+#include <asm/arch/hardware.h>
+
+#define CONFIG_AT32AP
+#define CONFIG_AT32AP7000
+
+/*
+ * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
+ * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
+ * PLL frequency.
+ * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz
+ */
+#define CONFIG_PLL
+#define CONFIG_SYS_POWER_MANAGER
+#define CONFIG_SYS_OSC0_HZ		20000000
+#define CONFIG_SYS_PLL0_DIV		1
+#define CONFIG_SYS_PLL0_MUL		7
+#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES	16
+/*
+ * Set the CPU running at:
+ * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
+ */
+#define CONFIG_SYS_CLKDIV_CPU		0
+/*
+ * Set the HSB running at:
+ * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
+ */
+#define CONFIG_SYS_CLKDIV_HSB		1
+/*
+ * Set the PBA running at:
+ * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
+ */
+#define CONFIG_SYS_CLKDIV_PBA		2
+/*
+ * Set the PBB running at:
+ * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
+ */
+#define CONFIG_SYS_CLKDIV_PBB		1
+
+/* Reserve VM regions for SDRAM and NOR flash */
+#define CONFIG_SYS_NR_VM_REGIONS	2
+
+/*
+ * The PLLOPT register controls the PLL like this:
+ *   icp = PLLOPT<2>
+ *   ivco = PLLOPT<1:0>
+ *
+ * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
+ */
+#define CONFIG_SYS_PLL0_OPT		0x04
+
+#define CONFIG_USART_BASE		ATMEL_BASE_USART1
+#define CONFIG_USART_ID			1
+
+/* User serviceable stuff */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#define CONFIG_STACKSIZE		(2048)
+
+#define CONFIG_BAUDRATE			115200
+
+/*
+ * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
+ * data on the serial line may interrupt the boot sequence.
+ */
+#define CONFIG_BOOTDELAY		1
+#define CONFIG_AUTOBOOT
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT		"Press SPACE to abort autoboot in %d" \
+					" seconds\n", bootdelay
+#define CONFIG_AUTOBOOT_DELAY_STR	"d"
+#define CONFIG_AUTOBOOT_STOP_STR	" "
+
+/*
+ * After booting the board for the first time, new ethernet addresses
+ * should be generated and assigned to the environment variables
+ * "ethaddr". This is normally done during production.
+ */
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+/* remove unneeded commands */
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+
+/* add useful commands */
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+
+#define CONFIG_ATMEL_USART
+#define CONFIG_MACB
+#define CONFIG_PORTMUX_PIO
+#define CONFIG_SYS_NR_PIOS		5
+#define CONFIG_SYS_HSDRAMC
+
+#define CONFIG_SYS_DCACHE_LINESZ	32
+#define CONFIG_SYS_ICACHE_LINESZ	32
+
+#define CONFIG_NR_DRAM_BANKS		1
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+
+#define CONFIG_SYS_FLASH_BASE		0x00000000
+#define CONFIG_SYS_FLASH_SIZE		0x800000
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	135
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_TEXT_BASE		0x00000000
+
+#define CONFIG_SYS_INTRAM_BASE		INTERNAL_SRAM_BASE
+#define CONFIG_SYS_INTRAM_SIZE		INTERNAL_SRAM_SIZE
+#define CONFIG_SYS_SDRAM_BASE		EBI_SDRAM_BASE
+
+#define CONFIG_ENV_IS_IN_FLASH
+/* place u-boot env in flash sector after u-boot */
+#define CONFIG_ENV_SIZE			0x10000
+#define CONFIG_ENV_ADDR			0x20000
+
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INTRAM_BASE + \
+					 CONFIG_SYS_INTRAM_SIZE)
+
+#define CONFIG_SYS_MALLOC_LEN		(256*1024)
+#define CONFIG_SYS_DMA_ALLOC_LEN	(16384)
+
+/* Allow 4MB for the kernel run-time image */
+#define CONFIG_SYS_LOAD_ADDR		(EBI_SDRAM_BASE + 0x00400000)
+#define CONFIG_SYS_BOOTPARAMS_LEN	(16 * 1024)
+
+/* Other configuration settings that shouldn't have to change all that often */
+#define CONFIG_SYS_PROMPT		"U-Boot> "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					 sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+
+#define CONFIG_SYS_MEMTEST_START	EBI_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x700000)
+
+#endif /* __GRASSHOPPER_CONFIG_H */
+/* vim: set ts=8 noet: */
diff --git a/qemu/roms/u-boot/include/configs/grsim.h b/qemu/roms/u-boot/include/configs/grsim.h
new file mode 100644
index 000000000..556c749f9
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/grsim.h
@@ -0,0 +1,314 @@
+/* Configuration header file for LEON3 GRSIM, trying to be similar
+ * to Gaisler's GR-XC3S-1500 board.
+ *
+ * (C) Copyright 2003-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2007
+ * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H__
+#define __CONFIG_H__
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ *
+ * Select between TSIM or GRSIM by setting CONFIG_GRSIM or CONFIG_TSIM to 1.
+ *
+ * TSIM command
+ *  tsim-leon3 -sdram 0 -ram 32000 -rom 8192 -mmu
+ *
+ */
+
+#define CONFIG_GRSIM		0	/* ... not running on GRSIM */
+#define CONFIG_TSIM		1	/* ... running on TSIM */
+
+/* CPU / AMBA BUS configuration */
+#define CONFIG_SYS_CLK_FREQ	40000000	/* 40MHz */
+
+/* Number of SPARC register windows */
+#define CONFIG_SYS_SPARC_NWINDOWS 8
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_BAUDRATE		38400	/* ... at 38400 bps */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/* Partitions */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION
+#define CONFIG_ISO_PARTITION
+
+/*
+ * Supported commands
+ */
+#define CONFIG_CMD_AMBAPP	/* AMBA Plyg&Play information	*/
+#define CONFIG_CMD_BDI		/* bdinfo			*/
+#define CONFIG_CMD_CONSOLE	/* coninfo			*/
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_ECHO		/* echo arguments		*/
+#define CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ITEST	/* Integer (and string) test	*/
+#define CONFIG_CMD_LOADB	/* loadb			*/
+#define CONFIG_CMD_LOADS	/* loads			*/
+#define CONFIG_CMD_MISC		/* Misc functions like sleep etc */
+#define CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot	*/
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_RUN		/* run command in env variable	*/
+#define CONFIG_CMD_SETGETDCR	/* DCR support on 4xx		*/
+#define CONFIG_CMD_SOURCE	/* "source" command support	*/
+#define CONFIG_CMD_XIMG		/* Load part of Multi Image	*/
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+/*#define CONFIG_SYS_HUSH_PARSER 0*/
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 40000000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/export/roofs\0"					\
+	"scratch=40000000\0"					\
+	"getkernel=tftpboot $(scratch) $(bootfile)\0" \
+	"ethaddr=00:00:7A:CC:00:12\0" \
+	"bootargs=console=ttyS0,38400" \
+	""
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_GATEWAYIP 192.168.0.1
+#define CONFIG_SERVERIP 192.168.0.81
+#define CONFIG_IPADDR 192.168.0.80
+#define CONFIG_ROOTPATH "/export/rootfs"
+#define CONFIG_HOSTNAME  grxc3s1500
+#define CONFIG_BOOTFILE "/uImage"
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+/* Memory MAP
+ *
+ *  Flash:
+ *  |--------------------------------|
+ *  | 0x00000000 Text & Data & BSS   | *
+ *  |            for Monitor         | *
+ *  | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| *
+ *  | UNUSED / Growth                | * 256kb
+ *  |--------------------------------|
+ *  | 0x00050000 Base custom area    | *
+ *  |            kernel / FS         | *
+ *  |                                | * Rest of Flash
+ *  |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~|
+ *  | END-0x00008000 Environment     | * 32kb
+ *  |--------------------------------|
+ *
+ *
+ *
+ *  Main Memory:
+ *  |--------------------------------|
+ *  | UNUSED / scratch area          |
+ *  |                                |
+ *  |                                |
+ *  |                                |
+ *  |                                |
+ *  |--------------------------------|
+ *  | Monitor .Text / .DATA / .BSS   | * 256kb
+ *  | Relocated!                     | *
+ *  |--------------------------------|
+ *  | Monitor Malloc                 | * 128kb (contains relocated environment)
+ *  |--------------------------------|
+ *  | Monitor/kernel STACK           | * 64kb
+ *  |--------------------------------|
+ *  | Page Table for MMU systems     | * 2k
+ *  |--------------------------------|
+ *  | PROM Code accessed from Linux  | * 6kb-128b
+ *  |--------------------------------|
+ *  | Global data (avail from kernel)| * 128b
+ *  |--------------------------------|
+ *
+ */
+
+/*
+ * Flash configuration (8,16 or 32 MB)
+ * TEXT base always at 0xFFF00000
+ * ENV_ADDR always at  0xFFF40000
+ * FLASH_BASE at 0xFC000000 for 64 MB
+ *               0xFE000000 for 32 MB
+ *               0xFF000000 for 16 MB
+ *               0xFF800000 for  8 MB
+ */
+#define CONFIG_SYS_NO_FLASH		1
+#define CONFIG_SYS_FLASH_BASE		0x00000000
+#define CONFIG_SYS_FLASH_SIZE		0x00800000
+#define CONFIG_ENV_SIZE		0x8000
+
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE+CONFIG_SYS_FLASH_SIZE-CONFIG_ENV_SIZE)
+
+#define PHYS_FLASH_SECT_SIZE	0x00020000	/* 128 KB sectors */
+#define CONFIG_SYS_MAX_FLASH_SECT	64	/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
+
+#ifdef ENABLE_FLASH_SUPPORT
+/* For use with grsim FLASH emulation extension */
+#define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
+
+#undef CONFIG_FLASH_8BIT	/* Flash is 32-bit */
+
+/*** CFI CONFIG ***/
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#endif
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_IS_NOWHERE 1
+/*#define CONFIG_ENV_IS_IN_FLASH*/
+/*#define CONFIG_ENV_SIZE		0x8000*/
+#define CONFIG_ENV_SECT_SIZE	0x40000
+#define CONFIG_ENV_OVERWRITE	1
+
+/*
+ * Memory map
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CONFIG_SYS_SDRAM_SIZE		0x02000000
+#define CONFIG_SYS_SDRAM_END		(CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_SDRAM_SIZE)
+
+/* no SRAM available */
+#undef CONFIG_SYS_SRAM_BASE
+#undef CONFIG_SYS_SRAM_SIZE
+
+/* Always Run U-Boot from SDRAM */
+#define CONFIG_SYS_RAM_BASE CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SDRAM_SIZE
+#define CONFIG_SYS_RAM_END CONFIG_SYS_SDRAM_END
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_RAM_END - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_PROM_SIZE		(8192-GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_PROM_OFFSET		(CONFIG_SYS_GBL_DATA_OFFSET-CONFIG_SYS_PROM_SIZE)
+
+#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_PROM_OFFSET-32)
+#define CONFIG_SYS_STACK_SIZE		(0x10000-32)
+
+#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor   */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()  */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+#define CONFIG_SYS_MALLOC_END		(CONFIG_SYS_INIT_SP_OFFSET-CONFIG_SYS_STACK_SIZE)
+#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MALLOC_END-CONFIG_SYS_MALLOC_LEN)
+
+/* relocated monitor area */
+#define CONFIG_SYS_RELOC_MONITOR_MAX_END   CONFIG_SYS_MALLOC_BASE
+#define CONFIG_SYS_RELOC_MONITOR_BASE     (CONFIG_SYS_RELOC_MONITOR_MAX_END-CONFIG_SYS_MONITOR_LEN)
+
+/* make un relocated address from relocated address */
+#define UN_RELOC(address) (address-(CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE))
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_GRETH	1
+
+/* Default HARDWARE address */
+#define GRETH_HWADDR_0 0x00
+#define GRETH_HWADDR_1 0x00
+#define GRETH_HWADDR_2 0x7A
+#define GRETH_HWADDR_3 0xcc
+#define GRETH_HWADDR_4 0x00
+#define GRETH_HWADDR_5 0x12
+
+#define CONFIG_ETHADDR   00:00:7a:cc:00:12
+
+/*
+ * Define CONFIG_GRETH_10MBIT to force GRETH at 10Mb/s
+ */
+/* #define CONFIG_GRETH_10MBIT 1 */
+#define CONFIG_PHY_ADDR		0x00
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory     */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args   */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM  */
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
+
+/***** Gaisler GRLIB IP-Cores Config ********/
+
+/* AMBA Plug & Play info display on startup */
+/*#define CONFIG_SYS_AMBAPP_PRINT_ON_STARTUP*/
+
+#define CONFIG_SYS_GRLIB_SDRAM     0
+#define CONFIG_SYS_GRLIB_MEMCFG1   (0x000000ff | (1<<11))
+#if CONFIG_GRSIM
+/* GRSIM configuration */
+#define CONFIG_SYS_GRLIB_MEMCFG2   0x82206000
+#else
+/* TSIM configuration */
+#define CONFIG_SYS_GRLIB_MEMCFG2   0x00001820
+#endif
+#define CONFIG_SYS_GRLIB_MEMCFG3   0x00136000
+
+#define CONFIG_SYS_GRLIB_FT_MEMCFG1   (0x000000ff | (1<<11))
+#define CONFIG_SYS_GRLIB_FT_MEMCFG2   0x82206000
+#define CONFIG_SYS_GRLIB_FT_MEMCFG3   0x00136000
+
+/* no DDR controller */
+#define CONFIG_SYS_GRLIB_DDR_CFG   0x00000000
+
+/* no DDR2 Controller */
+#define CONFIG_SYS_GRLIB_DDR2_CFG1 0x00000000
+#define CONFIG_SYS_GRLIB_DDR2_CFG3 0x00000000
+
+#define CONFIG_SYS_GRLIB_APBUART_SCALER \
+ ((((CONFIG_SYS_CLK_FREQ*10)/(CONFIG_BAUDRATE*8))-5)/10)
+
+/* default kernel command line */
+#define CONFIG_DEFAULT_KERNEL_COMMAND_LINE "console=ttyS0,38400\0\0"
+
+#define CONFIG_IDENT_STRING "Gaisler GRSIM"
+
+#endif				/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/grsim_leon2.h b/qemu/roms/u-boot/include/configs/grsim_leon2.h
new file mode 100644
index 000000000..8be98983c
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/grsim_leon2.h
@@ -0,0 +1,323 @@
+/* Configuration header file for LEON2 GRSIM.
+ *
+ * (C) Copyright 2003-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2007
+ * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H__
+#define __CONFIG_H__
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ *
+ * Select between TSIM or GRSIM by setting CONFIG_GRSIM or CONFIG_TSIM to 1.
+ *
+ * TSIM command
+ *  tsim-leon -sdram 0 -ram 32000 -rom 8192 -mmu
+ *
+ */
+
+#define CONFIG_GRSIM		0	/* ... not running on GRSIM */
+#define CONFIG_TSIM		1	/* ... running on TSIM */
+
+/* CPU / AMBA BUS configuration */
+#define CONFIG_SYS_CLK_FREQ	40000000	/* 40MHz */
+
+/* Number of SPARC register windows */
+#define CONFIG_SYS_SPARC_NWINDOWS 8
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_BAUDRATE		38400	/* ... at 38400 bps */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/* Partitions */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION
+#define CONFIG_ISO_PARTITION
+
+/*
+ * Supported commands
+ */
+#define CONFIG_CMD_BDI		/* bdinfo			*/
+#define CONFIG_CMD_CONSOLE	/* coninfo			*/
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_ECHO		/* echo arguments		*/
+#define CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ITEST	/* Integer (and string) test	*/
+#define CONFIG_CMD_LOADB	/* loadb			*/
+#define CONFIG_CMD_LOADS	/* loads			*/
+#define CONFIG_CMD_MISC		/* Misc functions like sleep etc */
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_RUN		/* run command in env variable	*/
+#define CONFIG_CMD_SETGETDCR	/* DCR support on 4xx		*/
+#define CONFIG_CMD_SOURCE	/* "source" command support	*/
+#define CONFIG_CMD_XIMG		/* Load part of Multi Image	*/
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+/*#define CONFIG_SYS_HUSH_PARSER 0*/
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 40000000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/export/roofs\0"					\
+	"scratch=40000000\0"					\
+	"getkernel=tftpboot $(scratch) $(bootfile)\0" \
+	"ethaddr=00:00:7A:CC:00:12\0" \
+	"bootargs=console=ttyS0,38400" \
+	""
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_GATEWAYIP 192.168.0.1
+#define CONFIG_SERVERIP 192.168.0.81
+#define CONFIG_IPADDR 192.168.0.80
+#define CONFIG_ROOTPATH "/export/rootfs"
+#define CONFIG_HOSTNAME  grxc3s1500
+#define CONFIG_BOOTFILE "/uImage"
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+/* Memory MAP
+ *
+ *  Flash:
+ *  |--------------------------------|
+ *  | 0x00000000 Text & Data & BSS   | *
+ *  |            for Monitor         | *
+ *  | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| *
+ *  | UNUSED / Growth                | * 256kb
+ *  |--------------------------------|
+ *  | 0x00050000 Base custom area    | *
+ *  |            kernel / FS         | *
+ *  |                                | * Rest of Flash
+ *  |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~|
+ *  | END-0x00008000 Environment     | * 32kb
+ *  |--------------------------------|
+ *
+ *
+ *
+ *  Main Memory:
+ *  |--------------------------------|
+ *  | UNUSED / scratch area          |
+ *  |                                |
+ *  |                                |
+ *  |                                |
+ *  |                                |
+ *  |--------------------------------|
+ *  | Monitor .Text / .DATA / .BSS   | * 256kb
+ *  | Relocated!                     | *
+ *  |--------------------------------|
+ *  | Monitor Malloc                 | * 128kb (contains relocated environment)
+ *  |--------------------------------|
+ *  | Monitor/kernel STACK           | * 64kb
+ *  |--------------------------------|
+ *  | Page Table for MMU systems     | * 2k
+ *  |--------------------------------|
+ *  | PROM Code accessed from Linux  | * 6kb-128b
+ *  |--------------------------------|
+ *  | Global data (avail from kernel)| * 128b
+ *  |--------------------------------|
+ *
+ */
+
+/*
+ * Flash configuration (8,16 or 32 MB)
+ * TEXT base always at 0xFFF00000
+ * ENV_ADDR always at  0xFFF40000
+ * FLASH_BASE at 0xFC000000 for 64 MB
+ *               0xFE000000 for 32 MB
+ *               0xFF000000 for 16 MB
+ *               0xFF800000 for  8 MB
+ */
+#define CONFIG_SYS_NO_FLASH		1
+#define CONFIG_SYS_FLASH_BASE		0x00000000
+#define CONFIG_SYS_FLASH_SIZE		0x00800000
+#define CONFIG_ENV_SIZE		0x8000
+
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE+CONFIG_SYS_FLASH_SIZE-CONFIG_ENV_SIZE)
+
+#define PHYS_FLASH_SECT_SIZE	0x00020000	/* 128 KB sectors */
+#define CONFIG_SYS_MAX_FLASH_SECT	64	/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */
+
+#ifdef ENABLE_FLASH_SUPPORT
+/* For use with grsim FLASH emulation extension */
+#define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
+
+#undef CONFIG_FLASH_8BIT	/* Flash is 32-bit */
+
+/*** CFI CONFIG ***/
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#endif
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_IS_NOWHERE 1
+/*#define CONFIG_ENV_IS_IN_FLASH*/
+/*#define CONFIG_ENV_SIZE		0x8000*/
+#define CONFIG_ENV_SECT_SIZE	0x40000
+#define CONFIG_ENV_OVERWRITE	1
+
+/*
+ * Memory map
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CONFIG_SYS_SDRAM_SIZE		0x00800000
+#define CONFIG_SYS_SDRAM_END		(CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_SDRAM_SIZE)
+
+/* no SRAM available */
+#undef CONFIG_SYS_SRAM_BASE
+#undef CONFIG_SYS_SRAM_SIZE
+
+
+/* Always Run U-Boot from SDRAM */
+#define CONFIG_SYS_RAM_BASE CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SDRAM_SIZE
+#define CONFIG_SYS_RAM_END CONFIG_SYS_SDRAM_END
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_RAM_END - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_PROM_SIZE		(8192-GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_PROM_OFFSET		(CONFIG_SYS_GBL_DATA_OFFSET-CONFIG_SYS_PROM_SIZE)
+
+#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_PROM_OFFSET-32)
+#define CONFIG_SYS_STACK_SIZE		(0x10000-32)
+
+#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor   */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()  */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+#define CONFIG_SYS_MALLOC_END		(CONFIG_SYS_INIT_SP_OFFSET-CONFIG_SYS_STACK_SIZE)
+#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MALLOC_END-CONFIG_SYS_MALLOC_LEN)
+
+/* relocated monitor area */
+#define CONFIG_SYS_RELOC_MONITOR_MAX_END   CONFIG_SYS_MALLOC_BASE
+#define CONFIG_SYS_RELOC_MONITOR_BASE     (CONFIG_SYS_RELOC_MONITOR_MAX_END-CONFIG_SYS_MONITOR_LEN)
+
+/* make un relocated address from relocated address */
+#define UN_RELOC(address) (address-(CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE))
+
+/*
+ * Ethernet configuration
+ */
+/*#define CONFIG_GRETH	1*/
+
+/* Default HARDWARE address */
+#define GRETH_HWADDR_0 0x00
+#define GRETH_HWADDR_1 0x00
+#define GRETH_HWADDR_2 0x7A
+#define GRETH_HWADDR_3 0xcc
+#define GRETH_HWADDR_4 0x00
+#define GRETH_HWADDR_5 0x12
+
+#define CONFIG_ETHADDR   00:00:7a:cc:00:12
+
+/*
+ * Define CONFIG_GRETH_10MBIT to force GRETH at 10Mb/s
+ */
+/* #define CONFIG_GRETH_10MBIT 1 */
+#define CONFIG_PHY_ADDR		0x00
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory     */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args   */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM  */
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
+
+/***** Gaisler GRLIB IP-Cores Config ********/
+
+#define CONFIG_SYS_GRLIB_SDRAM    0
+#define CONFIG_SYS_GRLIB_MEMCFG1  (0x000000ff | (1<<11))
+#if CONFIG_GRSIM
+#define CONFIG_SYS_GRLIB_MEMCFG2  0x82206000
+#else
+#define CONFIG_SYS_GRLIB_MEMCFG2  0x00001820
+#endif
+#define CONFIG_SYS_GRLIB_MEMCFG3  0x00136000
+
+/*** LEON2 UART 1 ***/
+#define CONFIG_SYS_LEON2_UART1_SCALER \
+	((((CONFIG_SYS_CLK_FREQ*10)/(CONFIG_BAUDRATE*8))-5)/10)
+
+/* UART1 Define to 1 or 0 */
+#define LEON2_UART1_LOOPBACK_ENABLE 0
+#define LEON2_UART1_FLOWCTRL_ENABLE 0
+#define LEON2_UART1_PARITY_ENABLE 0
+#define LEON2_UART1_ODDPAR_ENABLE 0
+
+/*** LEON2 UART 2 ***/
+
+#define CONFIG_SYS_LEON2_UART2_SCALER \
+	((((CONFIG_SYS_CLK_FREQ*10)/(CONFIG_BAUDRATE*8))-5)/10)
+
+/* UART2 Define to 1 or 0 */
+#define LEON2_UART2_LOOPBACK_ENABLE 0
+#define LEON2_UART2_FLOWCTRL_ENABLE 0
+#define LEON2_UART2_PARITY_ENABLE 0
+#define LEON2_UART2_ODDPAR_ENABLE 0
+
+#define LEON_CONSOLE_UART1 1
+#define LEON_CONSOLE_UART2 2
+
+/* Use UART2 as console */
+#define LEON2_CONSOLE_SELECT LEON_CONSOLE_UART1
+
+/* LEON2 I/O Port */
+/*#define LEON2_IO_PORT_DIR 0x0000aa00*/
+
+/* default kernel command line */
+#define CONFIG_DEFAULT_KERNEL_COMMAND_LINE "console=ttyS0,38400\0\0"
+
+#define CONFIG_IDENT_STRING "Gaisler GRSIM LEON2"
+
+#endif				/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/guruplug.h b/qemu/roms/u-boot/include/configs/guruplug.h
new file mode 100644
index 000000000..e401e7e9b
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/guruplug.h
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Siddarth Gore <gores@marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CONFIG_GURUPLUG_H
+#define _CONFIG_GURUPLUG_H
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING	"\nMarvell-GuruPlug"
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_SHEEVA_88SV131	1	/* CPU Core subversion */
+#define CONFIG_KIRKWOOD		1	/* SOC Family Name */
+#define CONFIG_KW88F6281	1	/* SOC Name */
+#define CONFIG_MACH_GURUPLUG	/* Machine type */
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_IDE
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/*
+ *  Environment variables configurations
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_ENV_IS_IN_NAND		1
+#define CONFIG_ENV_SECT_SIZE		0x20000	/* 128K */
+#else
+#define CONFIG_ENV_IS_NOWHERE		1	/* if env in SDRAM */
+#endif
+/*
+ * max 4k env size is enough, but in case of nand
+ * it has to be rounded to sector size
+ */
+#define CONFIG_ENV_SIZE			0x20000	/* 128k */
+#define CONFIG_ENV_ADDR			0x60000
+#define CONFIG_ENV_OFFSET		0x60000	/* env starts here */
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_BOOTCOMMAND		"setenv ethact egiga0; " \
+	"${x_bootcmd_ethernet}; setenv ethact egiga1; " \
+	"${x_bootcmd_ethernet}; ${x_bootcmd_usb}; ${x_bootcmd_kernel}; "\
+	"setenv bootargs ${x_bootargs} ${x_bootargs_root}; "	\
+	"bootm 0x6400000;"
+
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"x_bootcmd_ethernet=ping 192.168.2.1\0"	\
+	"x_bootcmd_usb=usb start\0"	\
+	"x_bootcmd_kernel=nand read.e 0x6400000 0x100000 0x400000\0" \
+	"x_bootargs=console=ttyS0,115200\0"	\
+	"x_bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs\0"
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS	{1, 1}	/* enable both ports */
+#define CONFIG_PHY_BASE_ADR	0
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * SATA Driver configuration
+ */
+#ifdef CONFIG_MVSATA_IDE
+#define CONFIG_SYS_ATA_IDE0_OFFSET	MV_SATA_PORT0_OFFSET
+#endif /*CONFIG_MVSATA_IDE*/
+
+#define CONFIG_SYS_ALT_MEMTEST
+
+#endif /* _CONFIG_GURUPLUG_H */
diff --git a/qemu/roms/u-boot/include/configs/gw8260.h b/qemu/roms/u-boot/include/configs/gw8260.h
new file mode 100644
index 000000000..262c9e9e9
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/gw8260.h
@@ -0,0 +1,800 @@
+/*
+ * (C) Copyright 2000
+ * Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ *
+ * (C) Copyright 2000
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2001
+ * Advent Networks, Inc. <http://www.adventnetworks.com>
+ * Jay Monkman <jmonkman@adventnetworks.com>
+ *
+ * (C) Copyright 2001
+ * Advent Networks, Inc. <http://www.adventnetworks.com>
+ * Oliver Brown <obrown@adventnetworks.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*********************************************************************/
+/* DESCRIPTION:
+ *   This file contains the board configuartion for the GW8260 board.
+ *
+ * MODULE DEPENDENCY:
+ *   None
+ *
+ * RESTRICTIONS/LIMITATIONS:
+ *   None
+ *
+ * Copyright (c) 2001, Advent Networks, Inc.
+ */
+/*********************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define	CONFIG_SYS_TEXT_BASE	0x40000000
+
+/* Enable debug prints */
+#undef DEBUG_BOOTP_EXT        /* Debug received vendor fields */
+
+/* What is the oscillator's (UX2) frequency in Hz? */
+#define CONFIG_8260_CLKIN  (66 * 1000 * 1000)
+
+/*-----------------------------------------------------------------------
+ * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
+ *-----------------------------------------------------------------------
+ * What should MODCK_H be? It is dependent on the oscillator
+ * frequency, MODCK[1-3], and desired CPM and core frequencies.
+ * Here are some example values (all frequencies are in MHz):
+ *
+ * MODCK_H   MODCK[1-3]  Osc    CPM    Core  S2-6   S2-7   S2-8
+ * -------   ----------  ---    ---    ----  -----  -----  -----
+ * 0x5       0x5     66 133     133    Open  Close  Open
+ * 0x5       0x6     66 133     166    Open  Open   Close
+ * 0x5       0x7     66 133     200    Open  Open   Open
+ * 0x6       0x0     66 133     233    Close Close  Close
+ * 0x6       0x1     66 133     266    Close Close  Open
+ * 0x6       0x2     66 133     300    Close Open   Close
+ */
+#define CONFIG_SYS_SBC_MODCK_H 0x05
+
+/* Define this if you want to boot from 0x00000100. If you don't define
+ * this, you will need to program the bootloader to 0xfff00000, and
+ * get the hardware reset config words at 0xfe000000. The simplest
+ * way to do that is to program the bootloader at both addresses.
+ * It is suggested that you just let U-Boot live at 0x00000000.
+ */
+#define CONFIG_SYS_SBC_BOOT_LOW 1
+
+/* What should the base address of the main FLASH be and how big is
+ * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE.
+ * The main FLASH is whichever is connected to *CS0. U-Boot expects
+ * this to be the SIMM.
+ */
+#define CONFIG_SYS_FLASH0_BASE 0x40000000
+#define CONFIG_SYS_FLASH0_SIZE 8
+
+/* Define CONFIG_SYS_FLASH_CHECKSUM to enable flash checksum during boot.
+ * Note: the 'flashchecksum' environment variable must also be set to 'y'.
+ */
+#define CONFIG_SYS_FLASH_CHECKSUM
+
+/* What should be the base address of SDRAM DIMM and how big is
+ * it (in Mbytes)?
+ */
+#define CONFIG_SYS_SDRAM0_BASE 0x00000000
+#define CONFIG_SYS_SDRAM0_SIZE 64
+
+/*
+ * DRAM tests
+ *   CONFIG_SYS_DRAM_TEST - enables the following tests.
+ *
+ *   CONFIG_SYS_DRAM_TEST_DATA - Enables test for shorted or open data lines
+ *                        Environment variable 'test_dram_data' must be
+ *                        set to 'y'.
+ *   CONFIG_SYS_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
+ *                        addressable. Environment variable
+ *                        'test_dram_address' must be set to 'y'.
+ *   CONFIG_SYS_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
+ *                        This test takes about 6 minutes to test 64 MB.
+ *                        Environment variable 'test_dram_walk' must be
+ *                        set to 'y'.
+ */
+#define CONFIG_SYS_DRAM_TEST
+#if defined(CONFIG_SYS_DRAM_TEST)
+#define CONFIG_SYS_DRAM_TEST_DATA
+#define CONFIG_SYS_DRAM_TEST_ADDRESS
+#define CONFIG_SYS_DRAM_TEST_WALK
+#endif /* CONFIG_SYS_DRAM_TEST */
+
+/*
+ * GW8260 with 16 MB DIMM:
+ *
+ *     0x0000 0000     Exception Vector code, 8k
+ *           :
+ *     0x0000 1FFF
+ *     0x0000 2000     Free for Application Use
+ *           :
+ *           :
+ *
+ *           :
+ *           :
+ *     0x00F5 FF30     Monitor Stack (Growing downward)
+ *                     Monitor Stack Buffer (0x80)
+ *     0x00F5 FFB0     Board Info Data
+ *     0x00F6 0000     Malloc Arena
+ *           :          CONFIG_ENV_SECT_SIZE, 256k
+ *           :          CONFIG_SYS_MALLOC_LEN,    128k
+ *     0x00FC 0000     RAM Copy of Monitor Code
+ *           :              CONFIG_SYS_MONITOR_LEN,   256k
+ *     0x00FF FFFF     [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1
+ */
+
+/*
+ * GW8260 with 64 MB DIMM:
+ *
+ *     0x0000 0000     Exception Vector code, 8k
+ *           :
+ *     0x0000 1FFF
+ *     0x0000 2000     Free for Application Use
+ *           :
+ *           :
+ *
+ *           :
+ *           :
+ *     0x03F5 FF30     Monitor Stack (Growing downward)
+ *                     Monitor Stack Buffer (0x80)
+ *     0x03F5 FFB0     Board Info Data
+ *     0x03F6 0000     Malloc Arena
+ *           :          CONFIG_ENV_SECT_SIZE, 256k
+ *           :          CONFIG_SYS_MALLOC_LEN,    128k
+ *     0x03FC 0000     RAM Copy of Monitor Code
+ *           :              CONFIG_SYS_MONITOR_LEN,   256k
+ *     0x03FF FFFF     [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1
+ */
+
+
+/*
+ * select serial console configuration
+ *
+ * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ *
+ * if CONFIG_CONS_NONE is defined, then the serial console routines must
+ * defined elsewhere.
+ */
+#define CONFIG_CONS_ON_SMC  1   /* define if console on SMC */
+#undef  CONFIG_CONS_ON_SCC      /* define if console on SCC */
+#undef  CONFIG_CONS_NONE        /* define if console on neither */
+#define CONFIG_CONS_INDEX   1   /* which SMC/SCC channel for console */
+
+/*
+ * select ethernet configuration
+ *
+ * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
+ * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
+ * for FCC)
+ *
+ * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
+ */
+
+#undef  CONFIG_ETHER_ON_SCC
+#define CONFIG_ETHER_ON_FCC
+#undef  CONFIG_ETHER_NONE       /* define if ethernet on neither */
+
+#ifdef  CONFIG_ETHER_ON_SCC
+#define CONFIG_ETHER_INDEX  1   /* which SCC/FCC channel for ethernet */
+#endif  /* CONFIG_ETHER_ON_SCC */
+
+#ifdef  CONFIG_ETHER_ON_FCC
+#define CONFIG_ETHER_INDEX  2   /* which SCC/FCC channel for ethernet */
+#define CONFIG_MII              /* MII PHY management           */
+#define CONFIG_BITBANGMII       /* bit-bang MII PHY management  */
+/*
+ * Port pins used for bit-banged MII communictions (if applicable).
+ */
+#define MDIO_PORT   2       /* Port C */
+
+#define MDIO_DECLARE	volatile ioport_t *iop = ioport_addr ( \
+				(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
+#define MDC_DECLARE	MDIO_DECLARE
+
+#define MDIO_ACTIVE    (iop->pdir |=  0x00400000)
+#define MDIO_TRISTATE  (iop->pdir &= ~0x00400000)
+#define MDIO_READ     ((iop->pdat &  0x00400000) != 0)
+
+#define MDIO(bit)   if(bit) iop->pdat |=  0x00400000; \
+	    else            iop->pdat &= ~0x00400000
+
+#define MDC(bit)    if(bit) iop->pdat |=  0x00200000; \
+	    else    iop->pdat &= ~0x00200000
+
+#define MIIDELAY    udelay(1)
+#endif  /* CONFIG_ETHER_ON_FCC */
+
+#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
+
+/*
+ * - Rx-CLK is CLK13
+ * - Tx-CLK is CLK14
+ * - Select bus for bd/buffers (see 28-13)
+ * - Enable Full Duplex in FSMR
+ */
+# define CONFIG_SYS_CMXFCR_MASK2	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
+# define CONFIG_SYS_CPMFCR_RAMTYPE	0
+# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
+
+#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
+
+/*
+ * - Rx-CLK is CLK15
+ * - Tx-CLK is CLK16
+ * - Select bus for bd/buffers (see 28-13)
+ * - Enable Full Duplex in FSMR
+ */
+# define CONFIG_SYS_CMXFCR_MASK3	(CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE3	(CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
+# define CONFIG_SYS_CPMFCR_RAMTYPE	0
+# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
+
+#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
+
+/* Define this to reserve an entire FLASH sector (256 KB) for
+ * environment variables. Otherwise, the environment will be
+ * put in the same sector as U-Boot, and changing variables
+ * will erase U-Boot temporarily
+ */
+#define CONFIG_ENV_IN_OWN_SECT
+
+/* Define to allow the user to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* What should the console's baud rate be? */
+#define CONFIG_BAUDRATE     115200
+
+/* Ethernet MAC address - This is set to all zeros to force an
+ *                        an error if we use BOOTP without setting
+ *                        the MAC address
+ */
+#define CONFIG_ETHADDR      00:00:00:00:00:00
+
+/* Set to a positive value to delay for running BOOTCOMMAND */
+#define CONFIG_BOOTDELAY    5   /* autoboot after 5 seconds */
+
+/* Be selective on what keys can delay or stop the autoboot process
+ *     To stop  use: " "
+ */
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT	\
+	"Autobooting in %d seconds, press \" \" to stop\n", bootdelay
+#define CONFIG_AUTOBOOT_STOP_STR    " "
+#undef  CONFIG_AUTOBOOT_DELAY_STR
+#define DEBUG_BOOTKEYS      0
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_DNS
+
+/* undef this to save memory */
+#define CONFIG_SYS_LONGHELP
+
+/* Monitor Command Prompt */
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_MII
+
+#undef CONFIG_CMD_KGDB
+
+
+/* Where do the internal registers live? */
+#define CONFIG_SYS_IMMR        0xf0000000
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef  CONFIG_SYS_HUSH_PARSER
+#endif
+
+/* What is the address of IO controller */
+#define CONFIG_SYS_IO_BASE 0xe0000000
+
+/*****************************************************************************
+ *
+ * You should not have to modify any of the following settings
+ *
+ *****************************************************************************/
+
+#define CONFIG_GW8260       1   /* on an GW8260 Board  */
+#define CONFIG_CPM2		1	/* Has a CPM2 */
+
+/*
+ * Miscellaneous configurable options
+ */
+#if defined(CONFIG_CMD_KGDB)
+#  define CONFIG_SYS_CBSIZE        1024    /* Console I/O Buffer Size       */
+#else
+#  define CONFIG_SYS_CBSIZE        256     /* Console I/O Buffer Size       */
+#endif
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE    (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
+
+#define CONFIG_SYS_MAXARGS     8          /* max number of command args   */
+
+#define CONFIG_SYS_BARGSIZE    CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size    */
+
+/* Convert clocks to MHZ when passing board info to kernel.
+ * This must be defined for eariler 2.4 kernels (~2.4.4).
+ */
+#define CONFIG_CLOCKS_IN_MHZ
+
+#define CONFIG_SYS_LOAD_ADDR   0x100000 /* default load address */
+
+
+/* memtest works from the end of the exception vector table
+ * to the end of the DRAM less monitor and malloc area
+ */
+#define CONFIG_SYS_MEMTEST_START   0x2000
+
+#define CONFIG_SYS_STACK_USAGE     0x10000 /* Reserve 64k for the stack usage */
+
+#define CONFIG_SYS_MEM_END_USAGE   ( CONFIG_SYS_MONITOR_LEN \
+			    + CONFIG_SYS_MALLOC_LEN \
+			    + CONFIG_ENV_SECT_SIZE \
+			    + CONFIG_SYS_STACK_USAGE )
+
+#define CONFIG_SYS_MEMTEST_END     ( CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 \
+			    - CONFIG_SYS_MEM_END_USAGE )
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+#define CONFIG_SYS_FLASH_BASE  CONFIG_SYS_FLASH0_BASE
+#define CONFIG_SYS_FLASH_SIZE  CONFIG_SYS_FLASH0_SIZE
+#define CONFIG_SYS_SDRAM_BASE  CONFIG_SYS_SDRAM0_BASE
+#define CONFIG_SYS_SDRAM_SIZE  CONFIG_SYS_SDRAM0_SIZE
+
+/*-----------------------------------------------------------------------
+ * Hard Reset Configuration Words
+ */
+#if defined(CONFIG_SYS_SBC_BOOT_LOW)
+#  define  CONFIG_SYS_SBC_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
+#else
+#  define  CONFIG_SYS_SBC_HRCW_BOOT_FLAGS  (0)
+#endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */
+
+/* get the HRCW ISB field from CONFIG_SYS_IMMR */
+#define CONFIG_SYS_SBC_HRCW_IMMR   ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) | \
+		  ((CONFIG_SYS_IMMR & 0x01000000) >>  7) | \
+		  ((CONFIG_SYS_IMMR & 0x00100000) >>  4) )
+
+#define CONFIG_SYS_HRCW_MASTER     ( HRCW_BPS11                | \
+		  HRCW_DPPC11               | \
+		  CONFIG_SYS_SBC_HRCW_IMMR         | \
+		  HRCW_MMR00                | \
+		  HRCW_LBPC11               | \
+		  HRCW_APPC10               | \
+		  HRCW_CS10PC00             | \
+		  (CONFIG_SYS_SBC_MODCK_H & HRCW_MODCK_H1111)  | \
+		  CONFIG_SYS_SBC_HRCW_BOOT_FLAGS )
+
+/* no slaves */
+#define CONFIG_SYS_HRCW_SLAVE1     0
+#define CONFIG_SYS_HRCW_SLAVE2     0
+#define CONFIG_SYS_HRCW_SLAVE3     0
+#define CONFIG_SYS_HRCW_SLAVE4     0
+#define CONFIG_SYS_HRCW_SLAVE5     0
+#define CONFIG_SYS_HRCW_SLAVE6     0
+#define CONFIG_SYS_HRCW_SLAVE7     0
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR    CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_SIZE     0x4000  /* Size of used area in DPRAM    */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET   CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent.
+ */
+#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_FLASH0_BASE
+
+#define CONFIG_SYS_MONITOR_LEN     (256 * 1024) /* Reserve 256 kB for Monitor   */
+#define CONFIG_SYS_MALLOC_LEN      (128 * 1024) /* Reserve 128 kB for malloc()  */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ       (8 * 1024 * 1024) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS   1    /* max number of memory banks        */
+#define CONFIG_SYS_MAX_FLASH_SECT    32   /* max number of sectors on one chip */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT  8000 /* Timeout for Flash Erase (in ms)   */
+#define CONFIG_SYS_FLASH_WRITE_TOUT  1    /* Timeout for Flash Write (in ms)   */
+
+#define CONFIG_ENV_IS_IN_FLASH   1
+
+#ifdef CONFIG_ENV_IN_OWN_SECT
+#  define CONFIG_ENV_ADDR        (CONFIG_SYS_MONITOR_BASE +  (256 * 1024))
+#  define CONFIG_ENV_SECT_SIZE   (256 * 1024)
+#else
+#  define CONFIG_ENV_SIZE        (16 * 1024)/* Size of Environment Sector  */
+#  define CONFIG_ENV_ADD  ((CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) - CONFIG_ENV_SIZE)
+#  define CONFIG_ENV_SECT_SIZE (256 * 1024)/* see README - env sect real size  */
+#endif /* CONFIG_ENV_IN_OWN_SECT */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE  32      /* For MPC8260 CPU */
+
+#if defined(CONFIG_CMD_KGDB)
+# define CONFIG_SYS_CACHELINE_SHIFT    5   /* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * HIDx - Hardware Implementation-dependent Registers            2-11
+ *-----------------------------------------------------------------------
+ * HID0 also contains cache control - initially enable both caches and
+ * invalidate contents, then the final state leaves only the instruction
+ * cache enabled. Note that Power-On and Hard reset invalidate the caches,
+ * but Soft reset does not.
+ *
+ * HID1 has only read-only information - nothing to set.
+ */
+#define CONFIG_SYS_HID0_INIT   (HID0_ICE  |\
+			 HID0_DCE  |\
+			 HID0_ICFI |\
+			 HID0_DCI  |\
+			 HID0_IFEM |\
+			 HID0_ABE)
+
+#define CONFIG_SYS_HID0_FINAL  (HID0_ICE  |\
+			 HID0_IFEM |\
+			 HID0_ABE  |\
+			 HID0_EMCP)
+#define CONFIG_SYS_HID2    0
+
+/*-----------------------------------------------------------------------
+ * RMR - Reset Mode Register
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RMR     0
+
+/*-----------------------------------------------------------------------
+ * BCR - Bus Configuration                           4-25
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_BCR     (BCR_ETM)
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration                 4-31
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_SIUMCR  (SIUMCR_DPPC11  |\
+		     SIUMCR_L2CPC00 |\
+		     SIUMCR_APPC10  |\
+		     SIUMCR_MMR00)
+
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control                11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
+ */
+#define CONFIG_SYS_SYPCR   (SYPCR_SWTC |\
+		     SYPCR_BMT  |\
+		     SYPCR_PBME |\
+		     SYPCR_LBME |\
+		     SYPCR_SWRI |\
+		     SYPCR_SWP)
+
+/*-----------------------------------------------------------------------
+ * TMCNTSC - Time Counter Status and Control             4-40
+ *-----------------------------------------------------------------------
+ * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
+ * and enable Time Counter
+ */
+#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC |\
+		     TMCNTSC_ALR |\
+		     TMCNTSC_TCF |\
+		     TMCNTSC_TCE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control         4-42
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
+ * Periodic timer
+ */
+#define CONFIG_SYS_PISCR   (PISCR_PS  |\
+		     PISCR_PTF |\
+		     PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control                           9-8
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_SCCR    0
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration                 13-7
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RCCR    0
+
+/*
+ * Initialize Memory Controller:
+ *
+ * Bank Bus   Machine PortSz  Device
+ * ---- ---   ------- ------  ------
+ *  0   60x   GPCM    32 bit  FLASH (SIMM - 4MB)
+ *  1   60x   GPCM    32 bit  unused
+ *  2   60x   SDRAM   64 bit  SDRAM (DIMM - 16MB or 64MB)
+ *  3   60x   SDRAM   64 bit  unused
+ *  4   Local GPCM     8 bit  IO    (on board - 64k)
+ *  5   60x   GPCM     8 bit  unused
+ *  6   60x   GPCM     8 bit  unused
+ *  7   60x   GPCM     8 bit  unused
+ *
+ */
+
+/*-----------------------------------------------------------------------
+ * BR0 - Base Register
+ *     Ref: Section 10.3.1 on page 10-14
+ * OR0 - Option Register
+ *     Ref: Section 10.3.2 on page 10-18
+ *-----------------------------------------------------------------------
+ */
+
+/* Bank 0,1 - FLASH SIMM
+ *
+ * This expects the FLASH SIMM to be connected to *CS0
+ * It consists of 4 AM29F016D parts.
+ *
+ * Note: For the 8 MB SIMM, *CS1 is unused.
+ */
+
+/* BR0 is configured as follows:
+ *
+ *     - Base address of 0x40000000
+ *     - 32 bit port size
+ *     - Data errors checking is disabled
+ *     - Read and write access
+ *     - GPCM 60x bus
+ *     - Access are handled by the memory controller according to MSEL
+ *     - Not used for atomic operations
+ *     - No data pipelining is done
+ *     - Valid
+ */
+#define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\
+			  BRx_PS_32                     |\
+			  BRx_MS_GPCM_P                 |\
+			  BRx_V)
+
+/* OR0 is configured as follows:
+ *
+ *     - 8 MB
+ *     - *BCTL0 is asserted upon access to the current memory bank
+ *     - *CW / *WE are negated a quarter of a clock earlier
+ *     - *CS is output at the same time as the address lines
+ *     - Uses a clock cycle length of 5
+ *     - *PSDVAL is generated internally by the memory controller
+ *       unless *GTA is asserted earlier externally.
+ *     - Relaxed timing is generated by the GPCM for accesses
+ *       initiated to this memory region.
+ *     - One idle clock is inserted between a read access from the
+ *       current bank and the next access.
+ */
+#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE) |\
+			 ORxG_CSNT          |\
+			 ORxG_ACS_DIV1      |\
+			 ORxG_SCY_5_CLK     |\
+			 ORxG_TRLX          |\
+			 ORxG_EHTR)
+
+/*-----------------------------------------------------------------------
+ * BR2 - Base Register
+ *     Ref: Section 10.3.1 on page 10-14
+ * OR2 - Option Register
+ *     Ref: Section 10.3.2 on page 10-16
+ *-----------------------------------------------------------------------
+ */
+
+/* Bank 2 - SDRAM DIMM
+ *
+ *     16MB DIMM: P/N
+ *     64MB DIMM: P/N  1W-8864X8-4-P1-EST or
+ *                     MT4LSDT864AG-10EB1 (Micron)
+ *
+ * Note: *CS3 is unused for this DIMM
+ */
+
+/* With a 16 MB or 64 MB DIMM, the BR2 is configured as follows:
+ *
+ *     - Base address of 0x00000000
+ *     - 64 bit port size (60x bus only)
+ *     - Data errors checking is disabled
+ *     - Read and write access
+ *     - SDRAM 60x bus
+ *     - Access are handled by the memory controller according to MSEL
+ *     - Not used for atomic operations
+ *     - No data pipelining is done
+ *     - Valid
+ */
+#define CONFIG_SYS_BR2_PRELIM  ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
+			  BRx_PS_64          |\
+			  BRx_MS_SDRAM_P     |\
+			  BRx_V)
+
+/* With a 16 MB DIMM, the OR2 is configured as follows:
+ *
+ *     - 16 MB
+ *     - 2 internal banks per device
+ *     - Row start address bit is A9 with PSDMR[PBI] = 0
+ *     - 11 row address lines
+ *     - Back-to-back page mode
+ *     - Internal bank interleaving within save device enabled
+ */
+#if (CONFIG_SYS_SDRAM0_SIZE == 16)
+#define CONFIG_SYS_OR2_PRELIM  (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\
+			 ORxS_BPD_2         |\
+			 ORxS_ROWST_PBI0_A9 |\
+			 ORxS_NUMR_11)
+
+/* With a 16 MB DIMM, the PSDMR is configured as follows:
+ *
+ *     - Page Based Interleaving,
+ *     - Refresh Enable,
+ *     - Address Multiplexing where A5 is output on A14 pin
+ *       (A6 on A15, and so on),
+ *     - use address pins A16-A18 as bank select,
+ *     - A9 is output on SDA10 during an ACTIVATE command,
+ *     - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
+ *     - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
+ *       is 3 clocks,
+ *     - earliest timing for READ/WRITE command after ACTIVATE command is
+ *       2 clocks,
+ *     - earliest timing for PRECHARGE after last data was read is 1 clock,
+ *     - earliest timing for PRECHARGE after last data was written is 1 clock,
+ *     - CAS Latency is 2.
+ */
+
+/*-----------------------------------------------------------------------
+ * PSDMR - 60x Bus SDRAM Mode Register
+ *     Ref: Section 10.3.3 on page 10-21
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_PSDMR   (PSDMR_RFEN       |\
+		     PSDMR_SDAM_A14_IS_A5 |\
+		     PSDMR_BSMA_A16_A18   |\
+		     PSDMR_SDA10_PBI0_A9  |\
+		     PSDMR_RFRC_7_CLK     |\
+		     PSDMR_PRETOACT_3W    |\
+		     PSDMR_ACTTORW_2W     |\
+		     PSDMR_LDOTOPRE_1C    |\
+		     PSDMR_WRC_1C         |\
+		     PSDMR_CL_2)
+#endif /* (CONFIG_SYS_SDRAM0_SIZE == 16) */
+
+/* With a 64 MB DIMM, the OR2 is configured as follows:
+ *
+ *     - 64 MB
+ *     - 4 internal banks per device
+ *     - Row start address bit is A8 with PSDMR[PBI] = 0
+ *     - 12 row address lines
+ *     - Back-to-back page mode
+ *     - Internal bank interleaving within save device enabled
+ */
+#if (CONFIG_SYS_SDRAM0_SIZE == 64)
+#define CONFIG_SYS_OR2_PRELIM  (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\
+	     ORxS_BPD_4         |\
+	     ORxS_ROWST_PBI0_A8     |\
+	     ORxS_NUMR_12)
+
+/* With a 64 MB DIMM, the PSDMR is configured as follows:
+ *
+ *     - Page Based Interleaving,
+ *     - Refresh Enable,
+ *     - Address Multiplexing where A5 is output on A14 pin
+ *       (A6 on A15, and so on),
+ *     - use address pins A14-A16 as bank select,
+ *     - A9 is output on SDA10 during an ACTIVATE command,
+ *     - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
+ *     - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
+ *       is 3 clocks,
+ *     - earliest timing for READ/WRITE command after ACTIVATE command is
+ *       2 clocks,
+ *     - earliest timing for PRECHARGE after last data was read is 1 clock,
+ *     - earliest timing for PRECHARGE after last data was written is 1 clock,
+ *     - CAS Latency is 2.
+ */
+
+/*-----------------------------------------------------------------------
+ * PSDMR - 60x Bus SDRAM Mode Register
+ *     Ref: Section 10.3.3 on page 10-21
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_PSDMR   (PSDMR_RFEN       |\
+		     PSDMR_SDAM_A14_IS_A5 |\
+		     PSDMR_BSMA_A14_A16   |\
+		     PSDMR_SDA10_PBI0_A9  |\
+		     PSDMR_RFRC_7_CLK     |\
+		     PSDMR_PRETOACT_3W    |\
+		     PSDMR_ACTTORW_2W     |\
+		     PSDMR_LDOTOPRE_1C    |\
+		     PSDMR_WRC_1C         |\
+		     PSDMR_CL_2)
+#endif  /* (CONFIG_SYS_SDRAM0_SIZE == 64) */
+
+#define CONFIG_SYS_PSRT    0x0e
+#define CONFIG_SYS_MPTPR   MPTPR_PTP_DIV32
+
+
+/*-----------------------------------------------------------------------
+ * BR4 - Base Register
+ *     Ref: Section 10.3.1 on page 10-14
+ * OR4 - Option Register
+ *     Ref: Section 10.3.2 on page 10-18
+ *-----------------------------------------------------------------------
+ */
+/* Bank 4 - Onboard Memory Mapped IO controller
+ *
+ * This expects the onboard IO controller to connected to *CS4 and
+ * the local bus.
+ *     - Base address of 0xe0000000
+ *     - 8 bit port size (local bus only)
+ *     - Read and write access
+ *     - GPCM local bus
+ *     - Not used for atomic operations
+ *     - No data pipelining is done
+ *     - Valid
+ *     - extended hold time
+ *     - 11 wait states
+ */
+
+#ifdef CONFIG_SYS_IO_BASE
+#  define CONFIG_SYS_BR4_PRELIM  ((CONFIG_SYS_IO_BASE & BRx_BA_MSK)  |\
+			    BRx_PS_8                   |\
+			    BRx_MS_GPCM_L              |\
+			    BRx_V)
+
+#  define CONFIG_SYS_OR4_PRELIM   (ORxG_AM_MSK                |\
+			    ORxG_SCY_11_CLK            |\
+			    ORxG_EHTR)
+#endif /* CONFIG_SYS_IO_BASE */
+#endif  /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/gw_ventana.h b/qemu/roms/u-boot/include/configs/gw_ventana.h
new file mode 100644
index 000000000..33983907f
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/gw_ventana.h
@@ -0,0 +1,425 @@
+/*
+ * Copyright (C) 2013 Gateworks Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+#define CONFIG_MX6
+#define CONFIG_DISPLAY_CPUINFO         /* display cpu info */
+#define CONFIG_DISPLAY_BOARDINFO_LATE  /* display board info (after reloc) */
+
+#define CONFIG_MACH_TYPE	4520   /* Gateworks Ventana Platform */
+
+#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/gpio.h>
+
+/* ATAGs */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_SERIAL_TAG
+#define CONFIG_REVISION_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
+
+/* Init Functions */
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MISC_INIT_R
+
+/* GPIO */
+#define CONFIG_MXC_GPIO
+
+/* Serial */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	       UART2_BASE
+
+#ifdef CONFIG_SPI_FLASH
+
+/* SPI */
+#define CONFIG_CMD_SF
+#ifdef CONFIG_CMD_SF
+  #define CONFIG_MXC_SPI
+  #define CONFIG_SPI_FLASH_MTD
+  #define CONFIG_SPI_FLASH_BAR
+  #define CONFIG_SPI_FLASH_WINBOND
+  #define CONFIG_SF_DEFAULT_BUS              0
+  #define CONFIG_SF_DEFAULT_CS               (0|(IMX_GPIO_NR(3, 19)<<8))
+					     /* GPIO 3-19 (21248) */
+  #define CONFIG_SF_DEFAULT_SPEED            30000000
+  #define CONFIG_SF_DEFAULT_MODE             (SPI_MODE_0)
+#endif
+
+#else
+/* Enable NAND support */
+#define CONFIG_CMD_TIME
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NAND_TRIMFFS
+#ifdef CONFIG_CMD_NAND
+  #define CONFIG_NAND_MXS
+  #define CONFIG_SYS_MAX_NAND_DEVICE	1
+  #define CONFIG_SYS_NAND_BASE		0x40000000
+  #define CONFIG_SYS_NAND_5_ADDR_CYCLE
+  #define CONFIG_SYS_NAND_ONFI_DETECTION
+
+  /* DMA stuff, needed for GPMI/MXS NAND support */
+  #define CONFIG_APBH_DMA
+  #define CONFIG_APBH_DMA_BURST
+  #define CONFIG_APBH_DMA_BURST8
+#endif
+
+#endif /* CONFIG_SPI_FLASH */
+
+/* Flattened Image Tree Suport */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE
+
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_SPEED		  100000
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR      0
+#define CONFIG_SYS_FSL_USDHC_NUM       1
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_BOUNCE_BUFFER
+
+/* Filesystem support */
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_UBIFS
+#define CONFIG_DOS_PARTITION
+
+/* Network config - Allow larger/faster download for TFTP/NFS */
+#define CONFIG_IP_DEFRAG
+#define CONFIG_TFTP_BLOCKSIZE 4096
+#define CONFIG_NFS_READ_SIZE  4096
+
+/*
+ * SATA Configs
+ */
+#define CONFIG_CMD_SATA
+#ifdef CONFIG_CMD_SATA
+  #define CONFIG_DWC_AHSATA
+  #define CONFIG_SYS_SATA_MAX_DEVICE	1
+  #define CONFIG_DWC_AHSATA_PORT_ID	0
+  #define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
+  #define CONFIG_LBA48
+  #define CONFIG_LIBATA
+#endif
+
+/*
+ * PCI express
+ */
+#define CONFIG_CMD_PCI
+#ifdef CONFIG_CMD_PCI
+#define CONFIG_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_PCIE_IMX
+#endif
+
+/*
+ * PMIC
+ */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
+
+/* Various command support */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_BMODE         /* set eFUSE shadow for a boot dev and reset */
+#define CONFIG_CMD_HDMIDETECT    /* detect HDMI output device */
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_GSC
+#define CONFIG_CMD_UBI
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define CONFIG_CMD_FUSE          /* eFUSE read/write support */
+#ifdef CONFIG_CMD_FUSE
+#define CONFIG_MXC_OCOTP
+#endif
+
+
+/* Ethernet support */
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE             ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE      RGMII
+#define CONFIG_ETHPRIME          "FEC"
+#define CONFIG_FEC_MXC_PHYADDR   0
+#define CONFIG_PHYLIB
+#define CONFIG_ARP_TIMEOUT       200UL
+
+/* USB Configs */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET  /* For OTG port */
+#define CONFIG_MXC_USB_PORTSC     (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS      0
+#define CONFIG_USB_KEYBOARD
+#define CONFIG_CI_UDC
+#define CONFIG_USBD_HS
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_ETHER
+#define CONFIG_USB_ETH_CDC
+#define CONFIG_NETCONSOLE
+#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
+#define CONFIG_USB_HUB_MIN_POWER_ON_DELAY 1200
+
+/* serial console (ttymxc1,115200) */
+#define CONFIG_CONS_INDEX              1
+#define CONFIG_BAUDRATE                115200
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT	             "Ventana > "
+#define CONFIG_SYS_CBSIZE	             1024
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_HWCONFIG
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	           16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/* Memory configuration */
+#define CONFIG_SYS_MEMTEST_START       0x10000000
+#define CONFIG_SYS_MEMTEST_END	       0x10010000
+#define CONFIG_SYS_MEMTEST_SCRATCH     0x10800000
+#define CONFIG_SYS_TEXT_BASE	         0x17800000
+#define CONFIG_SYS_LOAD_ADDR           0x12000000
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS           1
+#define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH  /* no NOR flash */
+
+/*
+ * MTD Command for mtdparts
+ */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#ifdef CONFIG_SPI_FLASH
+#define MTDIDS_DEFAULT    "nor0=nor"
+#define MTDPARTS_DEFAULT  \
+	"mtdparts=nor:512k(uboot),64k(env),2m(kernel),-(rootfs)"
+#else
+#define MTDIDS_DEFAULT    "nand0=nand"
+#define MTDPARTS_DEFAULT  "mtdparts=nand:16m(uboot),1m(env),-(rootfs)"
+#endif
+
+/* Persistent Environment Config */
+#define CONFIG_ENV_OVERWRITE    /* allow to overwrite serial and ethaddr */
+#ifdef CONFIG_SPI_FLASH
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#else
+#define CONFIG_ENV_IS_IN_NAND
+#endif
+#if defined(CONFIG_ENV_IS_IN_MMC)
+  #define CONFIG_ENV_OFFSET              (6 * 64 * 1024)
+  #define CONFIG_ENV_SIZE                (8 * 1024)
+  #define CONFIG_SYS_MMC_ENV_DEV         0
+#elif defined(CONFIG_ENV_IS_IN_NAND)
+  #define CONFIG_ENV_OFFSET              (16 << 20)
+  #define CONFIG_ENV_SECT_SIZE           (128 << 10)
+  #define CONFIG_ENV_SIZE                CONFIG_ENV_SECT_SIZE
+  #define CONFIG_ENV_OFFSET_REDUND       (CONFIG_ENV_OFFSET + (512 << 10))
+  #define CONFIG_ENV_SIZE_REDUND         CONFIG_ENV_SIZE
+#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+  #define CONFIG_ENV_OFFSET              (512 * 1024)
+  #define CONFIG_ENV_SECT_SIZE           (64 * 1024)
+  #define CONFIG_ENV_SIZE                (8 * 1024)
+  #define CONFIG_ENV_SPI_BUS             CONFIG_SF_DEFAULT_BUS
+  #define CONFIG_ENV_SPI_CS              CONFIG_SF_DEFAULT_CS
+  #define CONFIG_ENV_SPI_MODE            CONFIG_SF_DEFAULT_MODE
+  #define CONFIG_ENV_SPI_MAX_HZ          CONFIG_SF_DEFAULT_SPEED
+#endif
+
+/* Environment */
+#define CONFIG_BOOTDELAY          3
+#define CONFIG_LOADADDR           CONFIG_SYS_LOAD_ADDR
+#define CONFIG_IPADDR             192.168.1.1
+#define CONFIG_SERVERIP           192.168.1.146
+#define HWCONFIG_DEFAULT \
+	"hwconfig=rs232;" \
+	"dio0:mode=gpio;dio1:mode=gpio;dio2:mode=gpio;dio3:mode=gpio\0" \
+
+#define CONFIG_EXTRA_ENV_SETTINGS_COMMON \
+	"console=ttymxc1\0" \
+	"bootdevs=usb mmc sata flash\0" \
+	HWCONFIG_DEFAULT \
+	"video=\0" \
+	\
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"mtdids=" MTDIDS_DEFAULT "\0" \
+	\
+	"fdt_high=0xffffffff\0" \
+	"fdt_addr=0x18000000\0" \
+	"loadfdt=" \
+		"if ${fsload} ${fdt_addr} boot/${fdt_file}; then " \
+			"echo Loaded DTB from boot/${fdt_file}; " \
+		"elif ${fsload} ${fdt_addr} boot/${fdt_file1}; then " \
+			"echo Loaded DTB from boot/${fdt_file1}; " \
+		"elif ${fsload} ${fdt_addr} boot/${fdt_file2}; then " \
+				"echo Loaded DTB from boot/${fdt_file2}; " \
+		"fi\0" \
+	\
+	"script=boot/6x_bootscript-ventana\0" \
+	"loadscript=" \
+		"if ${fsload} ${loadaddr} ${script}; then " \
+			"source; " \
+		"fi\0" \
+	\
+	"uimage=boot/uImage\0" \
+	"mmc_root=/dev/mmcblk0p1 rootfstype=ext4 rootwait rw\0" \
+	"mmc_boot=" \
+		"setenv fsload 'ext2load mmc 0:1'; " \
+		"mmc dev 0 && mmc rescan && " \
+		"run loadscript; " \
+		"if ${fsload} ${loadaddr} ${uimage}; then " \
+			"setenv bootargs console=${console},${baudrate} " \
+				"root=/dev/mmcblk0p1 rootfstype=ext4 " \
+				"rootwait rw ${video} ${extra}; " \
+			"if run loadfdt && fdt addr ${fdt_addr}; then " \
+				"bootm ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"bootm; " \
+			"fi; " \
+		"fi\0" \
+	\
+	"sata_boot=" \
+		"setenv fsload 'ext2load sata 0:1'; sata init && " \
+		"run loadscript; " \
+		"if ${fsload} ${loadaddr} ${uimage}; then " \
+			"setenv bootargs console=${console},${baudrate} " \
+				"root=/dev/sda1 rootfstype=ext4 " \
+				"rootwait rw ${video} ${extra}; " \
+			"if run loadfdt && fdt addr ${fdt_addr}; then " \
+				"bootm ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"bootm; " \
+			"fi; " \
+		"fi\0" \
+	"usb_boot=" \
+		"setenv fsload 'ext2load usb 0:1'; usb start && usb dev 0 && " \
+		"run loadscript; " \
+		"if ${fsload} ${loadaddr} ${uimage}; then " \
+			"setenv bootargs console=${console},${baudrate} " \
+				"root=/dev/sda1 rootfstype=ext4 " \
+				"rootwait rw ${video} ${extra}; " \
+			"if run loadfdt && fdt addr ${fdt_addr}; then " \
+				"bootm ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"bootm; " \
+			"fi; " \
+		"fi\0"
+
+#ifdef CONFIG_SPI_FLASH
+	#define CONFIG_EXTRA_ENV_SETTINGS \
+	CONFIG_EXTRA_ENV_SETTINGS_COMMON \
+	"image_os=ventana/openwrt-imx6-imx6q-gw5400-a-squashfs.bin\0" \
+	"image_uboot=ventana/u-boot_spi.imx\0" \
+	\
+	"spi_koffset=0x90000\0" \
+	"spi_klen=0x200000\0" \
+	\
+	"spi_updateuboot=echo Updating uboot from " \
+		"${serverip}:${image_uboot}...; " \
+		"tftpboot ${loadaddr} ${image_uboot} && " \
+		"sf probe && sf erase 0 80000 && " \
+			"sf write ${loadaddr} 400 ${filesize}\0" \
+	"spi_update=echo Updating OS from ${serverip}:${image_os} " \
+		"to ${spi_koffset} ...; " \
+		"tftp ${loadaddr} ${image_os} && " \
+		"sf probe && " \
+		"sf update ${loadaddr} ${spi_koffset} ${filesize}\0" \
+	\
+	"flash_boot=" \
+		"if sf probe && " \
+		"sf read ${loadaddr} ${spi_koffset} ${spi_klen}; then " \
+			"setenv bootargs console=${console},${baudrate} " \
+				"root=/dev/mtdblock3 " \
+				"rootfstype=squashfs,jffs2 " \
+				"${video} ${extra}; " \
+			"bootm; " \
+		"fi\0"
+#else
+	#define CONFIG_EXTRA_ENV_SETTINGS \
+	CONFIG_EXTRA_ENV_SETTINGS_COMMON \
+	"image_rootfs=openwrt-imx6-ventana-rootfs.ubi\0" \
+	\
+	"nand_update=echo Updating NAND from ${serverip}:${image_rootfs}...; " \
+		"tftp ${loadaddr} ${image_rootfs} && " \
+		"nand erase.part rootfs && " \
+		"nand write ${loadaddr} rootfs ${filesize}\0" \
+	\
+	"flash_boot=" \
+		"setenv fsload 'ubifsload'; " \
+		"ubi part rootfs && ubifsmount ubi0:rootfs; " \
+		"run loadscript; " \
+		"if ${fsload} ${loadaddr} ${uimage}; then " \
+			"setenv bootargs console=${console},${baudrate} " \
+				"root=ubi0:rootfs ubi.mtd=2 " \
+				"rootfstype=ubifs ${video} ${extra}; " \
+			"if run loadfdt && fdt addr ${fdt_addr}; then " \
+				"ubifsumount; " \
+				"bootm ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"ubifsumount; bootm; " \
+			"fi; " \
+		"fi\0"
+#endif
+
+#define CONFIG_BOOTCOMMAND \
+	"for btype in ${bootdevs}; do " \
+		"echo; echo Attempting ${btype} boot...; " \
+		"if run ${btype}_boot; then; fi; " \
+	"done"
+
+/* Device Tree Support */
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_LIBFDT
+#define CONFIG_FDT_FIXUP_PARTITIONS
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+  #define CONFIG_CMD_CACHE
+#endif
+
+#endif			       /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/h2200.h b/qemu/roms/u-boot/include/configs/h2200.h
new file mode 100644
index 000000000..d02648420
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/h2200.h
@@ -0,0 +1,168 @@
+/*
+ * iPAQ h2200 board configuration
+ *
+ * Copyright (C) 2012 Lukasz Dalek <luk0104@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define MACH_TYPE_H2200			341
+#define CONFIG_MACH_TYPE		MACH_TYPE_H2200
+
+#define CONFIG_CPU_PXA25X		1
+#define CONFIG_BOARD_H2200
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM_1			0xa0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE		0x04000000 /* 64 MB */
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_SDRAM_SIZE		PHYS_SDRAM_1_SIZE
+
+#define CONFIG_SYS_INIT_SP_ADDR		0xfffff800
+
+#define CONFIG_ENV_SIZE			0x00040000
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
+
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_LOAD_ADDR		0xa3000000 /* default load address */
+
+/*
+ * iPAQ 1st stage bootloader loads 2nd stage bootloader
+ * at address 0xa0040000 but bootloader requires header
+ * which is 0x1000 long.
+ *
+ * --- Header begin ---
+ *	.word 0xea0003fe ; b 0x1000
+ *
+ *	.org 0x40
+ *	.ascii "ECEC"
+ *
+ *	.org 0x1000
+ * --- Header end ---
+ */
+
+#define CONFIG_SYS_TEXT_BASE		0xa0041000
+
+/*
+ * Static chips
+ */
+
+#define CONFIG_SYS_MSC0_VAL		0x246c7ffc
+#define CONFIG_SYS_MSC1_VAL		0x7ff07ff0
+#define CONFIG_SYS_MSC2_VAL		0x7ff07ff0
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+
+#define CONFIG_SYS_MECR_VAL		0x00000000
+#define CONFIG_SYS_MCMEM0_VAL		0x00000000
+#define CONFIG_SYS_MCMEM1_VAL		0x00000000
+#define CONFIG_SYS_MCATT0_VAL		0x00000000
+#define CONFIG_SYS_MCATT1_VAL		0x00000000
+#define CONFIG_SYS_MCIO0_VAL		0x00000000
+#define CONFIG_SYS_MCIO1_VAL		0x00000000
+
+#define CONFIG_SYS_FLYCNFG_VAL		0x00000000
+#define CONFIG_SYS_SXCNFG_VAL		0x00040004
+
+#define CONFIG_SYS_MDREFR_VAL		0x0099E018
+#define CONFIG_SYS_MDCNFG_VAL		0x01C801CB
+#define CONFIG_SYS_MDMRS_VAL		0x00220022
+
+#define CONFIG_SYS_PSSR_VAL		0x00000000
+#define CONFIG_SYS_CKEN			0x00004840
+#define CONFIG_SYS_CCCR			0x00000161
+
+/*
+ * GPIOs
+ */
+
+#define CONFIG_SYS_GPSR0_VAL		0x01000000
+#define CONFIG_SYS_GPSR1_VAL		0x00000000
+#define CONFIG_SYS_GPSR2_VAL		0x00010000
+
+#define CONFIG_SYS_GPCR0_VAL		0x00000000
+#define CONFIG_SYS_GPCR1_VAL		0x00000000
+#define CONFIG_SYS_GPCR2_VAL		0x00000000
+
+#define CONFIG_SYS_GPDR0_VAL		0xF7E38C00
+#define CONFIG_SYS_GPDR1_VAL		0xBCFFBF83
+#define CONFIG_SYS_GPDR2_VAL		0x000157FF
+
+#define CONFIG_SYS_GAFR0_L_VAL		0x80401000
+#define CONFIG_SYS_GAFR0_U_VAL		0x00000112
+#define CONFIG_SYS_GAFR1_L_VAL		0x600A9550
+#define CONFIG_SYS_GAFR1_U_VAL		0x0005AAAA
+#define CONFIG_SYS_GAFR2_L_VAL		0x20000000
+#define CONFIG_SYS_GAFR2_U_VAL		0x00000000
+
+/*
+ * Serial port
+ */
+
+#define CONFIG_PXA_SERIAL
+#define CONFIG_FFUART
+#define CONFIG_CONS_INDEX		3
+
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 38400, 115200 }
+
+#define CONFIG_CMD_IMPORTENV		1
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_SOURCE
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_IMI
+
+#define CONFIG_FIT
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT		"> "
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"$ "
+
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		256
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+
+#define CONFIG_BOOTARGS "root=/dev/ram0 ro console=ttyS0,115200n8"
+
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_USB_DEV_PULLUP_GPIO	33
+/* USB VBUS GPIO 3 */
+
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+
+#define CONFIG_BOOTDELAY		2
+#define CONFIG_BOOTCOMMAND		\
+	"setenv downloaded 0 ; while test $downloaded -eq 0 ; do " \
+	"if bootp ; then setenv downloaded 1 ; fi ; done ; " \
+	"source :script ; " \
+	"bootm ; "
+
+#define CONFIG_USB_GADGET_PXA2XX
+#define CONFIG_USB_ETHER
+#define CONFIG_USB_ETH_SUBSET
+
+#define CONFIG_USBNET_DEV_ADDR		"de:ad:be:ef:00:01"
+#define CONFIG_USBNET_HOST_ADDR	"de:ad:be:ef:00:02"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"stdin=serial\0" \
+	"stdout=serial\0" \
+	"stderr=serial\0"
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/hammerhead.h b/qemu/roms/u-boot/include/configs/hammerhead.h
new file mode 100644
index 000000000..4f0603abc
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/hammerhead.h
@@ -0,0 +1,158 @@
+/*
+ * Copyright (C) 2008 Miromico AG
+ *
+ * Configuration settings for the Miromico Hammerhead AVR32 board
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_AT32AP
+#define CONFIG_AT32AP7000
+#define CONFIG_HAMMERHEAD
+
+/*
+ * Set up the PLL to run at 125 MHz, the CPU to run at the PLL
+ * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
+ * and the PBA bus to run at 1/4 the PLL frequency.
+ */
+#define CONFIG_PLL
+#define CONFIG_SYS_POWER_MANAGER
+#define CONFIG_SYS_OSC0_HZ			25000000
+#define CONFIG_SYS_PLL0_DIV			1
+#define CONFIG_SYS_PLL0_MUL			5
+#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES	16
+#define CONFIG_SYS_CLKDIV_CPU			0
+#define CONFIG_SYS_CLKDIV_HSB			1
+#define CONFIG_SYS_CLKDIV_PBA			2
+#define CONFIG_SYS_CLKDIV_PBB			1
+
+/* Reserve VM regions for SDRAM and NOR flash */
+#define CONFIG_SYS_NR_VM_REGIONS		2
+
+/*
+ * The PLLOPT register controls the PLL like this:
+ *   icp = PLLOPT<2>
+ *   ivco = PLLOPT<1:0>
+ *
+ * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
+ */
+#define CONFIG_SYS_PLL0_OPT			0x04
+
+#define CONFIG_USART_BASE			ATMEL_BASE_USART1
+#define CONFIG_USART_ID				1
+
+#define CONFIG_HOSTNAME			hammerhead
+
+/* User serviceable stuff */
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#define CONFIG_STACKSIZE		(2048)
+
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_BOOTARGS							\
+	"console=ttyS0 root=mtd1 rootfstype=jffs2"
+#define CONFIG_BOOTCOMMAND						\
+	"fsload; bootm"
+
+/*
+ * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
+ * data on the serial line may interrupt the boot sequence.
+ */
+#define CONFIG_BOOTDELAY		1
+#define CONFIG_AUTOBOOT
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT				\
+	"Press SPACE to abort autoboot in %d seconds\n", bootdelay
+#define CONFIG_AUTOBOOT_DELAY_STR	"d"
+#define CONFIG_AUTOBOOT_STOP_STR	" "
+
+/*
+ * After booting the board for the first time, new ethernet address
+ * should be generated and assigned to the environment variables
+ * "ethaddr". This is normally done during production.
+ */
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
+
+/*
+ * BOOTP/DHCP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MMC
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+
+#define CONFIG_ATMEL_USART
+#define CONFIG_MACB
+#define CONFIG_PORTMUX_PIO
+#define CONFIG_SYS_NR_PIOS			5
+#define CONFIG_SYS_HSDRAMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_ATMEL_MCI
+#define CONFIG_GENERIC_MMC
+
+#define CONFIG_SYS_DCACHE_LINESZ		32
+#define CONFIG_SYS_ICACHE_LINESZ		32
+
+#define CONFIG_NR_DRAM_BANKS		1
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+
+#define CONFIG_SYS_FLASH_BASE			0x00000000
+#define CONFIG_SYS_FLASH_SIZE			0x800000
+#define CONFIG_SYS_MAX_FLASH_BANKS		1
+#define CONFIG_SYS_MAX_FLASH_SECT		135
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_TEXT_BASE		0x00000000
+
+#define CONFIG_SYS_INTRAM_BASE			0x24000000
+#define CONFIG_SYS_INTRAM_SIZE			0x8000
+
+#define CONFIG_SYS_SDRAM_BASE			0x10000000
+
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SIZE			65536
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
+
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
+
+#define CONFIG_SYS_MALLOC_LEN			(256*1024)
+
+#define CONFIG_SYS_DMA_ALLOC_LEN		(16384)
+
+/* Allow 4MB for the kernel run-time image */
+#define CONFIG_SYS_LOAD_ADDR			(CONFIG_SYS_SDRAM_BASE + 0x00400000)
+#define CONFIG_SYS_BOOTPARAMS_LEN		(16 * 1024)
+
+/* Other configuration settings that shouldn't have to change all that often */
+#define CONFIG_SYS_PROMPT			"Hammerhead> "
+#define CONFIG_SYS_CBSIZE			256
+#define CONFIG_SYS_MAXARGS			16
+#define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+
+#define CONFIG_SYS_MEMTEST_START		CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END			(CONFIG_SYS_MEMTEST_START + 0x1f00000)
+
+#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/harmony.h b/qemu/roms/u-boot/include/configs/harmony.h
new file mode 100644
index 000000000..3ec0e418c
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/harmony.h
@@ -0,0 +1,82 @@
+/*
+ *  (C) Copyright 2010-2012
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+#include "tegra20-common.h"
+
+/* Enable fdt support for Harmony. Flash the image in u-boot-dtb.bin */
+#define CONFIG_DEFAULT_DEVICE_TREE	tegra20-harmony
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
+/* High-level configuration options */
+#define V_PROMPT		"Tegra20 (Harmony) # "
+#define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Harmony"
+
+/* Board-specific serial config */
+#define CONFIG_TEGRA_ENABLE_UARTD
+
+/* UARTD: keyboard satellite board UART, default */
+#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
+#ifdef CONFIG_TEGRA_ENABLE_UARTA
+/* UARTA: debug board UART */
+#define CONFIG_SYS_NS16550_COM2		NV_PA_APB_UARTA_BASE
+#endif
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_HARMONY
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT		/* Make sure LCD init is complete */
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_TEGRA_MMC
+#define CONFIG_CMD_MMC
+
+/* NAND support */
+#define CONFIG_CMD_NAND
+#define CONFIG_TEGRA_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+
+/* Environment in NAND (which is 512M), aligned to start of last sector */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET	(SZ_512M - SZ_128K) /* 128K sector size */
+
+/* USB Host support */
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_TEGRA
+#define CONFIG_USB_ULPI
+#define CONFIG_USB_ULPI_VIEWPORT
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB
+
+/* USB networking support */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_MCS7830
+#define CONFIG_USB_ETHER_SMSC95XX
+
+/* General networking support */
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+
+/* LCD support */
+#define CONFIG_LCD
+#define CONFIG_PWM_TEGRA
+#define CONFIG_VIDEO_TEGRA
+#define LCD_BPP				LCD_COLOR16
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define CONFIG_CONSOLE_SCROLL_LINES	10
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/hawkboard.h b/qemu/roms/u-boot/include/configs/hawkboard.h
new file mode 100644
index 000000000..73e162437
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/hawkboard.h
@@ -0,0 +1,222 @@
+/*
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Based on davinci_dvevm.h. Original Copyrights follow:
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Board
+ */
+#define	CONFIG_SYS_USE_NAND	1
+
+/*
+ * SoC Configuration
+ */
+#define CONFIG_MACH_DAVINCI_HAWK
+#define CONFIG_ARM926EJS		/* arm926ejs CPU core */
+#define CONFIG_SOC_DA8XX		/* TI DA8xx SoC */
+#define CONFIG_SOC_DA850		/* TI DA850 SoC */
+#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
+#define CONFIG_SYS_CLK_FREQ		clk_get(DAVINCI_ARM_CLKID)
+#define CONFIG_SYS_OSCIN_FREQ		24000000
+#define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
+#define CONFIG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_AIS_CONFIG_FILE		"board/$(BOARDDIR)/hawkboard-ais-nand.cfg"
+
+#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (	\
+	DAVINCI_SYSCFG_SUSPSRC_EMAC |		\
+	DAVINCI_SYSCFG_SUSPSRC_I2C  |		\
+	DAVINCI_SYSCFG_SUSPSRC_SPI1 |		\
+	DAVINCI_SYSCFG_SUSPSRC_TIMER0 |		\
+	DAVINCI_SYSCFG_SUSPSRC_UART2)
+
+#if defined(CONFIG_UART_U_BOOT)
+#define CONFIG_SYS_TEXT_BASE		0xc1080000
+#elif !defined(CONFIG_SPL_BUILD)
+#define CONFIG_SYS_TEXT_BASE		0xc1180000
+#endif
+
+/* Spl */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SPL_LIBGENERIC_SUPPORT	/* for udelay and __div64_32 for NAND */
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_LDSCRIPT		"board/$(BOARDDIR)/u-boot-spl-hawk.lds"
+#define CONFIG_SPL_TEXT_BASE		0xc1080000
+#define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
+
+/*
+ * Memory Info
+ */
+#define CONFIG_SYS_MALLOC_LEN		(1*1024*1024) /* malloc() len */
+#define PHYS_SDRAM_1			DAVINCI_DDR_EMIF_DATA_BASE
+#define PHYS_SDRAM_1_SIZE		(128 << 20) /* SDRAM size 128MB */
+#define CONFIG_SYS_SDRAM_BASE		0xc0000000
+#define CONFIG_MAX_RAM_BANK_SIZE	(512 << 20)
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 -\
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_MONITOR_LEN		0x60000
+
+/* memtest start addr */
+#define CONFIG_SYS_MEMTEST_START	(PHYS_SDRAM_1)
+
+/* memtest will be run on 16MB */
+#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_1 + 16*1024*1024)
+
+#define CONFIG_NR_DRAM_BANKS		1 /* we have 1 bank of DRAM */
+
+/*
+ * Serial Driver info
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#define CONFIG_SYS_NS16550_COM1		DAVINCI_UART2_BASE
+#define CONFIG_SYS_NS16550_CLK		clk_get(DAVINCI_UART2_CLKID)
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+
+/*
+ * Network & Ethernet Configuration
+ */
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_MII
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT		10
+
+/*
+ * Nand Flash
+ */
+#ifdef CONFIG_SYS_USE_NAND
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE			(128 << 10)
+#define CONFIG_SYS_NAND_BASE		DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
+#define CONFIG_CLE_MASK			0x10
+#define CONFIG_ALE_MASK			0x8
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
+#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST /* SPL nand driver configuration */
+#define CFG_DAVINCI_STD_NAND_LAYOUT
+#define CONFIG_SYS_NAND_CS		3
+#define CONFIG_SYS_NAND_PAGE_2K
+/* Max number of NAND devices */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE_LIST	{ 0x62000000, }
+/* Block 0--not used by bootcode */
+#define CONFIG_ENV_OFFSET		0x0
+
+#define CONFIG_SYS_NAND_PAGE_SIZE	(2 << 10)
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0xe0000
+#define CONFIG_SYS_NAND_U_BOOT_DST	0xc1180000
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
+#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP	(CONFIG_SYS_NAND_U_BOOT_DST - \
+					CONFIG_SYS_NAND_U_BOOT_SIZE - \
+					CONFIG_SYS_MALLOC_LEN -       \
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_NAND_ECCPOS		{				\
+				24, 25, 26, 27, 28,			\
+				29, 30, 31, 32, 33, 34, 35, 36, 37, 38,	\
+				39, 40, 41, 42, 43, 44, 45, 46, 47, 48,	\
+				49, 50, 51, 52, 53, 54, 55, 56, 57, 58,	\
+				59, 60, 61, 62, 63 }
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	10
+#define CONFIG_SYS_NAND_OOBSIZE		64
+
+#endif /* CONFIG_SYS_USE_NAND */
+
+/* USB Configs */
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_USB_OHCI_DA8XX
+#define CONFIG_USB_STORAGE
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x01E25000
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"hawkboard"
+
+/*
+ * U-Boot general configuration
+ */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_BOOTFILE		"uImage" /* Boot file name */
+#define CONFIG_SYS_PROMPT	"hawkboard > " /* Command Prompt */
+#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
+#define CONFIG_SYS_LOAD_ADDR	(PHYS_SDRAM_1 + 0x700000)
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+
+/*
+ * Linux Information
+ */
+#define LINUX_BOOT_PARAM_ADDR	(CONFIG_SYS_MEMTEST_START + 0x100)
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTARGS		\
+	"mem=128M console=ttyS2,115200n8 root=/dev/ram0 rw initrd=0xc1180000,"\
+					"4M ip=static"
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * U-Boot commands
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_EXT2
+
+#ifdef CONFIG_CMD_BDI
+#define CONFIG_CLOCKS
+#endif
+
+#ifdef CONFIG_SYS_USE_NAND
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_NAND
+#endif
+
+#ifndef CONFIG_DRIVER_TI_EMAC
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_MII
+#undef CONFIG_CMD_PING
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/hermes.h b/qemu/roms/u-boot/include/configs/hermes.h
new file mode 100644
index 000000000..736ffb613
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/hermes.h
@@ -0,0 +1,315 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC860		1	/* This is a MPC860T CPU	*/
+#define CONFIG_HERMES		1	/* ...on a HERMES-PRO board	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xFE000000
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		9600
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define	CONFIG_SHOW_BOOT_PROGRESS 1	/* Show boot progress on LEDs	*/
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND							\
+	"bootp; "								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
+	"bootm"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x00F00000	/* 1 ... 15MB in DRAM	*/
+
+#define	CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address	*/
+
+#define	CONFIG_SYS_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/
+
+#define	CONFIG_SYS_ALLOC_DPRAM		1	/* use allocation routines	*/
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xFF000000	/* Non-Standard value!	*/
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFE000000
+#ifdef	DEBUG
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#else
+#define	CONFIG_SYS_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
+#endif
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	124	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CONFIG_ENV_IS_IN_FLASH	1
+#define	CONFIG_ENV_OFFSET		0x4000	/*   Offset   of Environment Sector	*/
+#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ * +0x0004
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * +0x0000 => 0x000000C0
+ */
+#define CONFIG_SYS_SIUMCR	0
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ * +0x0200 => 0x00C2
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ * +0x0240 => 0x0082
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit, set PLL multiplication factor !
+ */
+/* +0x0286 => 0x00B0D0C0 */
+#define CONFIG_SYS_PLPRCR							\
+		(	(11 << PLPRCR_MF_SHIFT) |			\
+			PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST |	\
+			/*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |		\
+			PLPRCR_CSR   | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/	\
+		)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+/* +0x0282 => 0x03800000 */
+#define CONFIG_SYS_SCCR	(SCCR_COM00	|   SCCR_TBS	  |	\
+			 SCCR_RTDIV	|   SCCR_RTSEL	  |	\
+			 /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/	\
+			 SCCR_EBDF00	|   SCCR_DFSYNC00 |	\
+			 SCCR_DFBRG00	|   SCCR_DFNL000  |	\
+			 SCCR_DFNH000)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+/* +0x0220 => 0x00C3 */
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration Register		19-4
+ *-----------------------------------------------------------------------
+ */
+/* +0x09C4 => TIMEP=1 */
+#define CONFIG_SYS_RCCR 0x0100
+
+/*-----------------------------------------------------------------------
+ * RMDS - RISC Microcode Development Support Control Register
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RMDS 0
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0 and OR0 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0xFE000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+/* allow for max 4 MB of Flash */
+#define CONFIG_SYS_REMAP_OR_AM		0xFFC00000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xFFC00000	/* OR addr mask */
+
+/* FLASH timing: ACS = 11, TRLX = 1, CSNT = 1, SCY = 5, EHTR = 0	*/
+#define CONFIG_SYS_OR_TIMING_FLASH	( OR_CSNT_SAM | /*OR_ACS_DIV4 |*/ OR_BI | \
+				 OR_SCY_5_CLK | OR_TRLX)
+
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+/* 8 bit, bank valid */
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
+
+/*
+ * BR1/OR1 - SDRAM
+ *
+ * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
+ */
+#define SDRAM_BASE_PRELIM	0x00000000	/* SDRAM bank */
+#define SDRAM_PRELIM_OR_AM	0xF8000000	/* map max. 128 MB */
+#define SDRAM_TIMING		0x00000A00	/* SDRAM-Timing */
+
+#define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB SDRAM */
+
+#define CONFIG_SYS_OR1_PRELIM	(SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
+#define CONFIG_SYS_BR1_PRELIM	((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+/*
+ * BR2/OR2 - HPRO2: PEB2256   @ 0xE0000000, 8 Bit wide
+ */
+#define HPRO2_BASE		0xE0000000
+#define HPRO2_OR_AM		0xFFFF8000
+#define HPRO2_TIMING		0x00000934
+
+#define CONFIG_SYS_OR2 (HPRO2_OR_AM | HPRO2_TIMING)
+#define CONFIG_SYS_BR2	((HPRO2_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
+
+/*
+ * BR3/OR3: not used
+ * BR4/OR4: not used
+ * BR5/OR5: not used
+ * BR6/OR6: not used
+ * BR7/OR7: not used
+ */
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* periodic timer for refresh */
+#define CONFIG_SYS_MAMR_PTA	97		/* start with divider for 100 MHz	*/
+
+/* 8 column SDRAM */
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/highbank.h b/qemu/roms/u-boot/include/configs/highbank.h
new file mode 100644
index 000000000..a6202cfab
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/highbank.h
@@ -0,0 +1,103 @@
+/*
+ * Copyright 2010-2011 Calxeda, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <config_distro_defaults.h>
+
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_SYS_THUMB_BUILD
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_FIT
+#define CONFIG_SYS_BOOTMAPSZ		(16 << 20)
+
+#define CONFIG_SYS_TIMER_RATE		(150000000/256)
+#define CONFIG_SYS_TIMER_COUNTER	(0xFFF34000 + 0x4)
+#define CONFIG_SYS_TIMER_COUNTS_DOWN
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(512 * 1024)
+
+#define CONFIG_PL011_SERIAL
+#define CONFIG_PL011_CLOCK		150000000
+#define CONFIG_PL01x_PORTS		{ (void *)(0xFFF36000) }
+#define CONFIG_CONS_INDEX		0
+
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_BOOTCOUNT_LIMIT
+#define CONFIG_SYS_BOOTCOUNT_SINGLEWORD
+#define CONFIG_SYS_BOOTCOUNT_LE		/* Use little-endian accessors */
+#define CONFIG_SYS_BOOTCOUNT_ADDR	0xfff3cf0c
+
+#define CONFIG_MISC_INIT_R
+#define CONFIG_LIBATA
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	5
+#define CONFIG_SYS_SCSI_MAX_LUN		1
+#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+					CONFIG_SYS_SCSI_MAX_LUN)
+
+#define CONFIG_CALXEDA_XGMAC
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_SCSI
+
+#define CONFIG_BOOT_RETRY_TIME		-1
+#define CONFIG_RESET_TO_RETRY
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds...\nPress <s> to stop or <d> to delay\n", bootdelay
+#define CONFIG_AUTOBOOT_KEYED_CTRLC
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of cmd args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					 sizeof(CONFIG_SYS_PROMPT)+16)
+
+#define CONFIG_SYS_LOAD_ADDR		0x800000
+#define CONFIG_SYS_64BIT_LBA
+
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM_1_SIZE		(4089 << 20)
+#define CONFIG_SYS_MEMTEST_START	0x100000
+#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_1_SIZE - 0x100000)
+
+/* Environment data setup
+*/
+#define CONFIG_ENV_IS_IN_NVRAM
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xfff88000	/* NVRAM base address */
+#define CONFIG_SYS_NVRAM_SIZE		0x8000		/* NVRAM size */
+#define CONFIG_ENV_SIZE			0x2000		/* Size of Environ */
+#define CONFIG_ENV_ADDR			CONFIG_SYS_NVRAM_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_TEXT_BASE		0x00008000
+#define CONFIG_SYS_INIT_SP_ADDR		0x01000000
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/hmi1001.h b/qemu/roms/u-boot/include/configs/hmi1001.h
new file mode 100644
index 000000000..a1a88b5e3
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/hmi1001.h
@@ -0,0 +1,339 @@
+/*
+ * (C) Copyright 2003-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5200		1	/* This is an MPC5200 CPU	*/
+#define CONFIG_HMI1001		1	/* HMI1001 board		*/
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xFFF00000
+#endif
+
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz		*/
+
+#define CONFIG_BOARD_EARLY_INIT_R
+
+#define CONFIG_HIGH_BATS	1	/* High BATs supported			*/
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1	*/
+#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps	*/
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/* Partitions */
+#define CONFIG_DOS_PARTITION
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DISPLAY
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_SNTP
+
+
+#define	CONFIG_TIMESTAMP	1	/* Print image info with timestamp */
+
+#if (CONFIG_SYS_TEXT_BASE == 0xFFF00000) /* Boot low */
+#   define CONFIG_SYS_LOWBOOT		1
+#endif
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT	"echo;" \
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_82xx\0"					\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run net_nfs"
+
+#define CONFIG_MISC_INIT_R	1
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #1 or #2 */
+
+#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x58
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
+
+/*
+ * RTC configuration
+ */
+#define CONFIG_RTC_PCF8563
+#define CONFIG_SYS_I2C_RTC_ADDR		0x51
+
+/*
+ * Flash configuration
+ */
+#define CONFIG_SYS_FLASH_BASE		0xFF800000
+
+#define CONFIG_SYS_FLASH_SIZE		0x00800000 /* 8 MByte */
+#define CONFIG_SYS_MAX_FLASH_SECT	67	/* max num of sects on one chip */
+
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_TEXT_BASE+0x40000) /* second sector */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks
+					   (= chip selects) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_CFI_AMD_RESET
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_SIZE		0x4000
+#define CONFIG_ENV_SECT_SIZE	0x20000
+#define CONFIG_ENV_OFFSET_REDUND   (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND     (CONFIG_ENV_SIZE)
+
+/*
+ * Memory map
+ */
+#define CONFIG_SYS_MBAR		0xF0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
+#define CONFIG_SYS_DISPLAY_BASE	0x80600000
+#define CONFIG_SYS_STATUS1_BASE	0x80600200
+#define CONFIG_SYS_STATUS2_BASE	0x80600300
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_DDR	 1
+#define SDRAM_MODE      0x018D0000
+#define SDRAM_EMODE     0x40090000
+#define SDRAM_CONTROL   0x714f0f00
+#define SDRAM_CONFIG1   0x73722930
+#define SDRAM_CONFIG2   0x47770000
+#define SDRAM_TAPDELAY  0x10000000
+
+/* Use ON-Chip SRAM until RAM will be available */
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+
+/* preserve space for the post_word at end of on-chip SRAM */
+#define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)
+
+#ifdef CONFIG_POST
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_POST_SIZE
+#else
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
+#endif
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(512 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC	1
+#define CONFIG_MPC5xxx_FEC_MII100
+#define CONFIG_PHY_ADDR		0x00
+#define CONFIG_MII		1		/* MII PHY management		*/
+
+/*
+ * GPIO configuration
+ */
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x01051004
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs			*/
+#if defined(CONFIG_CMD_KGDB)
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/* Enable an alternate, more extensive memory test */
+#define CONFIG_SYS_ALT_MEMTEST
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
+
+/*
+ * Enable loopw command.
+ */
+#define CONFIG_LOOPW
+
+/*
+ * Various low-level settings
+ */
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
+
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_CFG		0x0004FB00
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
+
+/* 8Mbit SRAM @0x80100000 */
+#define CONFIG_SYS_CS1_START		0x80100000
+#define CONFIG_SYS_CS1_SIZE		0x00100000
+#define CONFIG_SYS_CS1_CFG		0x19B00
+
+/* FRAM 32Kbyte @0x80700000 */
+#define CONFIG_SYS_CS2_START		0x80700000
+#define CONFIG_SYS_CS2_SIZE		0x00008000
+#define CONFIG_SYS_CS2_CFG		0x19800
+
+/* Display H1, Status Inputs, EPLD @0x80600000 */
+#define CONFIG_SYS_CS3_START		0x80600000
+#define CONFIG_SYS_CS3_SIZE		0x00100000
+#define CONFIG_SYS_CS3_CFG		0x00019800
+
+#define CONFIG_SYS_CS_BURST		0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE	0x33333333
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+
+#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	2	/* max. 2 drives per IDE bus	*/
+
+#define CONFIG_IDE_PREINIT	1
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
+
+/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
+
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)
+
+/* Interval between registers                                                */
+#define CONFIG_SYS_ATA_STRIDE          4
+
+#define CONFIG_ATAPI            1
+
+#define CONFIG_VIDEO_SMI_LYNXEM
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_VIDEO_LOGO
+
+/*
+ * PCI Mapping:
+ * 0x40000000 - 0x4fffffff - PCI Memory
+ * 0x50000000 - 0x50ffffff - PCI IO Space
+ */
+#define CONFIG_PCI		1
+#define CONFIG_PCI_PNP		1
+#define CONFIG_PCI_SCAN_SHOW	1
+#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1
+
+#define CONFIG_PCI_MEM_BUS	0x40000000
+#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE	0x10000000
+
+#define CONFIG_PCI_IO_BUS	0x50000000
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0x01000000
+
+#define CONFIG_SYS_ISA_IO		CONFIG_PCI_IO_BUS
+
+/*---------------------------------------------------------------------*/
+/* Display addresses						       */
+/*---------------------------------------------------------------------*/
+
+#define CONFIG_PDSP188x
+#define CONFIG_SYS_DISP_CHR_RAM	(CONFIG_SYS_DISPLAY_BASE + 0x38)
+#define CONFIG_SYS_DISP_CWORD		(CONFIG_SYS_DISPLAY_BASE + 0x30)
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/hummingboard.h b/qemu/roms/u-boot/include/configs/hummingboard.h
new file mode 100644
index 000000000..289552334
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/hummingboard.h
@@ -0,0 +1,225 @@
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2013 SolidRun ltd.
+ * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>
+ *
+ * Configuration settings for the SolidRun Hummingboard.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/gpio.h>
+#include <linux/sizes.h>
+
+#define CONFIG_MX6
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_MACH_TYPE		4773
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(2 * SZ_1M)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART1_BASE
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+
+/* Command definition */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_I2C
+
+#define CONFIG_CMD_BMODE
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_BOOTDELAY		3
+
+#define CONFIG_SYS_MEMTEST_START	0x10000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 500 * SZ_1M)
+#define CONFIG_LOADADDR			0x12000000
+#define CONFIG_SYS_TEXT_BASE		0x17800000
+
+/* MMC Configuration */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_USDHC_NUM	1
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+/* Ethernet Configuration */
+#define CONFIG_FEC_MXC
+#ifdef CONFIG_FEC_MXC
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_MII
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE		RGMII
+#define CONFIG_FEC_MXC_PHYADDR		0
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ATHEROS
+#endif
+
+#if defined(CONFIG_MX6S)
+#define CONFIG_DEFAULT_FDT_FILE		"imx6dl-hummingboard.dtb"
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"image=zImage\0" \
+	"console=ttymxc0\0" \
+	"splashpos=m,m\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"fdt_addr=0x18000000\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
+	"mmcpart=1\0" \
+	"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
+	"update_sd_firmware_filename=u-boot.imx\0" \
+	"update_sd_firmware=" \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"if mmc dev ${mmcdev}; then "	\
+			"if ${get_cmd} ${update_sd_firmware_filename}; then " \
+				"setexpr fw_sz ${filesize} / 0x200; " \
+				"setexpr fw_sz ${fw_sz} + 1; "	\
+				"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
+			"fi; "	\
+		"fi\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs " \
+	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+		"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	   "mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "else run netboot; " \
+			   "fi; " \
+		   "fi; " \
+	   "else run netboot; fi"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE		1024
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	       16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+#define CONFIG_CMDLINE_EDITING
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_SIZE			(8 * 1024)
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET		(6 * 64 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+#endif
+
+#endif			       /* __CONFIG_H * */
diff --git a/qemu/roms/u-boot/include/configs/hymod.h b/qemu/roms/u-boot/include/configs/hymod.h
new file mode 100644
index 000000000..c973365e1
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/hymod.h
@@ -0,0 +1,728 @@
+/*
+ * (C) Copyright 2000
+ * Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Config header file for Hymod board
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_HYMOD		1	/* ...on a Hymod board		*/
+#define CONFIG_CPM2		1	/* Has a CPM2 */
+
+#define	CONFIG_SYS_TEXT_BASE	0x40000000
+
+#define	CONFIG_MISC_INIT_F	1	/* Use misc_init_f()		*/
+
+#define CONFIG_BOARD_POSTCLK_INIT	/* have board_postclk_init() function */
+
+/*
+ * select serial console configuration
+ *
+ * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ *
+ * if CONFIG_CONS_NONE is defined, then the serial console routines must
+ * defined elsewhere (for example, on the cogent platform, there are serial
+ * ports on the motherboard which are used for the serial console - see
+ * cogent/cma101/serial.[ch]).
+ */
+#undef	CONFIG_CONS_ON_SMC		/* define if console on SMC */
+#define	CONFIG_CONS_ON_SCC		/* define if console on SCC */
+#undef	CONFIG_CONS_NONE		/* define if console on something else*/
+#define	CONFIG_CONS_INDEX	1	/* which serial channel for console */
+#define	CONFIG_CONS_USE_EXTC		/* SMC/SCC use ext clock not brg_clk */
+#define	CONFIG_CONS_EXTC_RATE	3686400	/* SMC/SCC ext clk rate in Hz */
+#define	CONFIG_CONS_EXTC_PINSEL	0	/* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
+
+/*
+ * select ethernet configuration
+ *
+ * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
+ * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
+ * for FCC)
+ *
+ * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
+ */
+#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC	*/
+#define	CONFIG_ETHER_ON_FCC		/* define if ether on FCC	*/
+#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
+#define CONFIG_ETHER_INDEX	1	/* which channel for ether	*/
+#define CONFIG_ETHER_LOOPBACK_TEST	/* add ether external loopback test */
+
+#ifdef CONFIG_ETHER_ON_FCC
+
+#if (CONFIG_ETHER_INDEX == 1)
+
+/*
+ * - Rx-CLK is CLK10
+ * - Tx-CLK is CLK11
+ * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
+ * - Enable Full Duplex in FSMR
+ */
+# define CONFIG_SYS_CMXFCR_MASK1	(CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE1	(CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK11)
+# define CONFIG_SYS_CPMFCR_RAMTYPE	0
+# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+
+# define MDIO_PORT		0		/* Port A */
+# define MDIO_DECLARE		volatile ioport_t *iop = ioport_addr ( \
+					(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
+# define MDC_DECLARE		MDIO_DECLARE
+
+# define MDIO_DATA_PINMASK	0x00040000	/* Pin 13 */
+# define MDIO_CLCK_PINMASK	0x00080000	/* Pin 12 */
+
+#elif (CONFIG_ETHER_INDEX == 2)
+
+/*
+ * - Rx-CLK is CLK13
+ * - Tx-CLK is CLK14
+ * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
+ * - Enable Full Duplex in FSMR
+ */
+# define CONFIG_SYS_CMXFCR_MASK2	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
+# define CONFIG_SYS_CPMFCR_RAMTYPE	0
+# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+
+# define MDIO_PORT		0		/* Port A */
+# define MDIO_DECLARE		volatile ioport_t *iop = ioport_addr ( \
+					(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
+# define MDC_DECLARE		MDIO_DECLARE
+
+# define MDIO_DATA_PINMASK	0x00000040	/* Pin 25 */
+# define MDIO_CLCK_PINMASK	0x00000080	/* Pin 24 */
+
+#elif (CONFIG_ETHER_INDEX == 3)
+
+/*
+ * - Rx-CLK is CLK15
+ * - Tx-CLK is CLK16
+ * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
+ * - Enable Full Duplex in FSMR
+ */
+# define CONFIG_SYS_CMXFCR_MASK3	(CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE3	(CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
+# define CONFIG_SYS_CPMFCR_RAMTYPE	0
+# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+
+# define MDIO_PORT		0		/* Port A */
+# define MDIO_DECLARE		volatile ioport_t *iop = ioport_addr ( \
+					(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
+# define MDC_DECLARE		MDIO_DECLARE
+
+# define MDIO_DATA_PINMASK	0x00000100	/* Pin 23 */
+# define MDIO_CLCK_PINMASK	0x00000200	/* Pin 22 */
+
+#endif	/* CONFIG_ETHER_INDEX */
+
+#define CONFIG_MII			/* MII PHY management	*/
+#define CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
+
+#define MDIO_ACTIVE	(iop->pdir |=  MDIO_DATA_PINMASK)
+#define MDIO_TRISTATE	(iop->pdir &= ~MDIO_DATA_PINMASK)
+#define MDIO_READ	((iop->pdat &  MDIO_DATA_PINMASK) != 0)
+
+#define MDIO(bit)	if(bit) iop->pdat |=  MDIO_DATA_PINMASK; \
+			else	iop->pdat &= ~MDIO_DATA_PINMASK
+
+#define MDC(bit)	if(bit) iop->pdat |=  MDIO_CLCK_PINMASK; \
+			else	iop->pdat &= ~MDIO_CLCK_PINMASK
+
+#define MIIDELAY	udelay(1)
+
+#endif	/* CONFIG_ETHER_ON_FCC */
+
+
+/* other options */
+#define CONFIG_HARD_I2C		1	/* To enable I2C hardware support	*/
+#define CONFIG_DTT_ADM1021	1	/* ADM1021 temp sensor support */
+
+/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
+#ifdef DEBUG
+#define CONFIG_8260_CLKIN	33333333	/* in Hz */
+#else
+#define CONFIG_8260_CLKIN	66666666	/* in Hz */
+#endif
+
+#if defined(CONFIG_CONS_USE_EXTC)
+#define CONFIG_BAUDRATE		115200
+#else
+#define CONFIG_BAUDRATE		9600
+#endif
+
+/* default ip addresses - these will be overridden */
+#define CONFIG_IPADDR		192.168.1.1	/* hymod "boot" address */
+#define CONFIG_SERVERIP		192.168.1.254	/* hymod "server" address */
+
+#define CONFIG_LAST_STAGE_INIT
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_CDP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_KGDB
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_PORTIO
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
+
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_XIMG
+
+#ifdef DEBUG
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#define CONFIG_BOOT_RETRY_TIME 30	/* retry autoboot after 30 secs	*/
+#define CONFIG_BOOT_RETRY_MIN	1	/* can go down to 1 second timeout */
+/* Be selective on what keys can delay or stop the autoboot process
+ *	To stop use: " "
+ */
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT		"Autobooting in %d seconds, " \
+					"press <SPACE> to stop\n", bootdelay
+#define CONFIG_AUTOBOOT_STOP_STR	" "
+#undef CONFIG_AUTOBOOT_DELAY_STR
+#define DEBUG_BOOTKEYS		0
+#endif
+
+#if defined(CONFIG_CMD_KGDB)
+#undef	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
+#define	CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
+#undef	CONFIG_KGDB_NONE		/* define if kgdb on something else */
+#define CONFIG_KGDB_INDEX	2	/* which serial channel for kgdb */
+#define	CONFIG_KGDB_USE_EXTC		/* SMC/SCC use ext clock not brg_clk */
+#define	CONFIG_KGDB_EXTC_RATE	3686400	/* serial ext clk rate in Hz */
+#define	CONFIG_KGDB_EXTC_PINSEL	0	/* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
+# if defined(CONFIG_KGDB_USE_EXTC)
+#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port at */
+# else
+#define CONFIG_KGDB_BAUDRATE	9600	/* speed to run kgdb serial port at */
+# endif
+#endif
+
+#undef	CONFIG_WATCHDOG			/* disable platform specific watchdog */
+
+#define CONFIG_RTC_PCF8563		/* use Philips PCF8563 RTC	*/
+
+/*
+ * Hymod specific configurable options
+ */
+#undef	CONFIG_SYS_HYMOD_DBLEDS			/* walk mezz board LEDs */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x00400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x03c00000	/* 4 ... 60 MB in DRAM	*/
+
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#define	CONFIG_SYS_I2C_SPEED		50000
+#define	CONFIG_SYS_I2C_SLAVE		0x7e
+
+/* these are for the ST M24C02 2kbit serial i2c eeprom */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50		/* base address */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1		/* bytes of address */
+/* mask of address bits that overflow into the "EEPROM chip address"    */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4	/* 16 byte write page size */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+
+#define CONFIG_SYS_I2C_MULTI_EEPROMS	1		/* hymod has two eeproms */
+
+#define CONFIG_SYS_I2C_RTC_ADDR	0x51	/* philips PCF8563 RTC address */
+
+/*
+ * standard dtt sensor configuration - bottom bit will determine local or
+ * remote sensor of the ADM1021, the rest determines index into
+ * CONFIG_SYS_DTT_ADM1021 array below.
+ *
+ * On HYMOD board, the remote sensor should be connected to the MPC8260
+ * temperature diode thingy, but an errata said this didn't work and
+ * should be disabled - so it isn't connected.
+ */
+#if 0
+#define CONFIG_DTT_SENSORS		{ 0, 1 }
+#else
+#define CONFIG_DTT_SENSORS		{ 0 }
+#endif
+
+/*
+ * ADM1021 temp sensor configuration (see dtt/adm1021.c for details).
+ * there will be one entry in this array for each two (dummy) sensors in
+ * CONFIG_DTT_SENSORS.
+ *
+ * For HYMOD board:
+ * - only one ADM1021
+ * - i2c addr 0x2a (both ADD0 and ADD1 are N/C)
+ * - conversion rate 0x02 = 0.25 conversions/second
+ * - ALERT ouput disabled
+ * - local temp sensor enabled, min set to 0 deg, max set to 85 deg
+ * - remote temp sensor disabled (see comment for CONFIG_DTT_SENSORS above)
+ */
+#define CONFIG_SYS_DTT_ADM1021		{ { 0x2a, 0x02, 0, 1, 0, 85, 0, } }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Hard Reset Configuration Words
+ *
+ * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
+ * defines for the various registers affected by the HRCW e.g. changing
+ * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
+ */
+#ifdef DEBUG
+#define CONFIG_SYS_HRCW_MASTER	(HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\
+			 HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\
+			 HRCW_MODCK_H0010)
+#else
+#define CONFIG_SYS_HRCW_MASTER	(HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\
+			 HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\
+			 HRCW_MODCK_H0101)
+#endif
+/* no slaves so just duplicate the master hrcw */
+#define CONFIG_SYS_HRCW_SLAVE1	CONFIG_SYS_HRCW_MASTER
+#define CONFIG_SYS_HRCW_SLAVE2	CONFIG_SYS_HRCW_MASTER
+#define CONFIG_SYS_HRCW_SLAVE3	CONFIG_SYS_HRCW_MASTER
+#define CONFIG_SYS_HRCW_SLAVE4	CONFIG_SYS_HRCW_MASTER
+#define CONFIG_SYS_HRCW_SLAVE5	CONFIG_SYS_HRCW_MASTER
+#define CONFIG_SYS_HRCW_SLAVE6	CONFIG_SYS_HRCW_MASTER
+#define CONFIG_SYS_HRCW_SLAVE7	CONFIG_SYS_HRCW_MASTER
+
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xF0000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x4000	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_TEXT_BASE
+#define	CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_FPGA_BASE		0x80000000
+/*
+ * unfortunately, CONFIG_SYS_MONITOR_LEN must include the
+ * (very large i.e. 256kB) environment flash sector
+ */
+#define	CONFIG_SYS_MONITOR_LEN		(512 << 10)	/* Reserve 512 kB for Monitor*/
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Mem map for Linux*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max num of memory banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	67	/* max num of sects on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Flash Erase Timeout (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
+
+#define	CONFIG_ENV_IS_IN_FLASH	1
+#define	CONFIG_ENV_SIZE		0x40000	/* Total Size of Environment Sector */
+#define CONFIG_ENV_SECT_SIZE	0x40000	/* see README - env sect real size */
+#define	CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE)
+#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPU		*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * HIDx - Hardware Implementation-dependent Registers			 2-11
+ *-----------------------------------------------------------------------
+ * HID0 also contains cache control - initially enable both caches and
+ * invalidate contents, then the final state leaves only the instruction
+ * cache enabled. Note that Power-On and Hard reset invalidate the caches,
+ * but Soft reset does not.
+ *
+ * HID1 has only read-only information - nothing to set.
+ */
+#define CONFIG_SYS_HID0_INIT	(HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
+				HID0_IFEM|HID0_ABE)
+#ifdef DEBUG
+#define CONFIG_SYS_HID0_FINAL	0
+#else
+#define CONFIG_SYS_HID0_FINAL	(HID0_ICE|HID0_IFEM|HID0_ABE)
+#endif
+#define CONFIG_SYS_HID2	0
+
+/*-----------------------------------------------------------------------
+ * RMR - Reset Mode Register					 5-5
+ *-----------------------------------------------------------------------
+ * turn on Checkstop Reset Enable
+ */
+#ifdef DEBUG
+#define CONFIG_SYS_RMR		0
+#else
+#define CONFIG_SYS_RMR		RMR_CSRE
+#endif
+
+/*-----------------------------------------------------------------------
+ * BCR - Bus Configuration					 4-25
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_BCR		(BCR_ETM)
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				 4-31
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DPPC10|SIUMCR_L2CPC01|\
+			 SIUMCR_APPC10|SIUMCR_MMR11)
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				 4-35
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Watchdog & Bus Monitor Timer max, 60x & Local Bus Monitor enable
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
+#else
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+			 SYPCR_SWRI|SYPCR_SWP)
+#endif /* CONFIG_WATCHDOG */
+
+/*-----------------------------------------------------------------------
+ * TMCNTSC - Time Counter Status and Control			 4-40
+ *-----------------------------------------------------------------------
+ * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
+ * and enable Time Counter
+ */
+#define CONFIG_SYS_TMCNTSC	(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		 4-42
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
+ * Periodic timer
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS|PISCR_PTF|PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control					 9-8
+ *-----------------------------------------------------------------------
+ * Ensure DFBRG is Divide by 16
+ */
+#define CONFIG_SYS_SCCR	(SCCR_DFBRG01)
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration				13-7
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RCCR	0
+
+/*
+ * Init Memory Controller:
+ *
+ * Bank	Bus	Machine	PortSz	Device
+ * ----	---	-------	------	------
+ *  0	60x	GPCM	32 bit	FLASH
+ *  1	60x	GPCM	32 bit	FLASH (same as 0 - unused for now)
+ *  2	60x	SDRAM	64 bit	SDRAM
+ *  3	Local	UPMC	 8 bit	Main Xilinx configuration
+ *  4	Local	GPCM	32 bit	Main Xilinx register mode
+ *  5	Local	UPMB	32 bit	Main Xilinx port mode
+ *  6	Local	UPMC	 8 bit	Mezz Xilinx configuration
+ */
+
+/*
+ * Bank 0 - FLASH
+ *
+ * Quotes from the HYMOD IO Board Reference manual:
+ *
+ * "The flash memory is two Intel StrataFlash chips, each configured for
+ *  16 bit operation and connected to give a 32 bit wide port."
+ *
+ * "The chip select logic is configured to respond to both *CS0 and *CS1.
+ *  Therefore the FLASH memory will be mapped to both bank 0 and bank 1.
+ *  It is suggested that bank 0 be read-only and bank 1 be read/write. The
+ *  FLASH will then appear as ROM during boot."
+ *
+ * Initially, we are only going to use bank 0 in read/write mode.
+ */
+
+/* 32 bit, read-write, GPCM on 60x bus */
+#define	CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_FLASH_BASE&BRx_BA_MSK)|\
+				BRx_PS_32|BRx_MS_GPCM_P|BRx_V)
+/* up to 32 Mb */
+#define	CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(32)|ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK)
+
+/*
+ * Bank 2 - SDRAM
+ *
+ * Quotes from the HYMOD IO Board Reference manual:
+ *
+ * "The main memory is implemented using TC59SM716FTL-10 SDRAM and has a
+ *  fixed size of 64 Mbytes. The Toshiba TC59SM716FTL-10 is a CMOS synchronous
+ *  dynamic random access memory organised as 4 banks by 4096 rows by 512
+ *  columns by 16 bits. Four chips provide a 64-bit port on the 60x bus."
+ *
+ * "The locations in SDRAM are accessed using multiplexed address pins to
+ *  specify row and column. The pins also act to specify commands. The state
+ *  of the inputs *RAS, *CAS and *WE defines the required action. The a10/AP
+ *  pin may function as a row address or as the AUTO PRECHARGE control line,
+ *  depending on the cycle type. The 60x bus SDRAM machine allows the MPC8260
+ *  address lines to be configured to the required multiplexing scheme."
+ */
+
+#define CONFIG_SYS_SDRAM_SIZE	64
+
+/* 64 bit, read-write, SDRAM on 60x bus */
+#define	CONFIG_SYS_BR2_PRELIM	((CONFIG_SYS_SDRAM_BASE&BRx_BA_MSK)|\
+				BRx_PS_64|BRx_MS_SDRAM_P|BRx_V)
+/* 64 Mb, 4 int banks per dev, row start addr bit = A6, 12 row addr lines */
+#define	CONFIG_SYS_OR2_PRELIM	(MEG_TO_AM(CONFIG_SYS_SDRAM_SIZE)|\
+				ORxS_BPD_4|ORxS_ROWST_PBI1_A6|ORxS_NUMR_12)
+
+/*
+ * The 60x Bus SDRAM Mode Register (PDSMR) is set as follows:
+ *
+ * Page Based Interleaving, Refresh Enable, Address Multiplexing where A5
+ * is output on A16 pin (A6 on A17, and so on), use address pins A14-A16
+ * as bank select, A7 is output on SDA10 during an ACTIVATE command,
+ * earliest timing for ACTIVATE command after REFRESH command is 6 clocks,
+ * earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
+ * is 2 clocks, earliest timing for READ/WRITE command after ACTIVATE
+ * command is 2 clocks, earliest timing for PRECHARGE after last data
+ * was read is 1 clock, earliest timing for PRECHARGE after last data
+ * was written is 1 clock, CAS Latency is 2.
+ */
+
+#define CONFIG_SYS_PSDMR	(PSDMR_PBI|PSDMR_SDAM_A16_IS_A5|\
+				PSDMR_BSMA_A14_A16|PSDMR_SDA10_PBI1_A7|\
+				PSDMR_RFRC_6_CLK|PSDMR_PRETOACT_2W|\
+				PSDMR_ACTTORW_2W|PSDMR_LDOTOPRE_1C|\
+				PSDMR_WRC_1C|PSDMR_CL_2)
+
+/*
+ * The 60x bus-assigned SDRAM Refresh Timer (PSRT) (10-31) and the Refresh
+ * Timers Prescale (PTP) value in the Memory Refresh Timer Prescaler Register
+ * (MPTPR) (10-32) must also be set up (it used to be called the Periodic Timer
+ * Prescaler, hence the P instead of the R). The refresh timer period is given
+ * by (note that there was a change in the 8260 UM Errata):
+ *
+ *	TimerPeriod = (PSRT + 1) / Fmptc
+ *
+ * where Fmptc is the BusClock divided by PTP. i.e.
+ *
+ *	TimerPeriod = (PSRT + 1) / (BusClock / PTP)
+ *
+ * or
+ *
+ *	TImerPeriod = (PTP * (PSRT + 1)) / BusClock
+ *
+ * The requirement for the Toshiba TC59SM716FTL-10 is that there must be
+ * 4K refresh cycles every 64 ms. i.e. one refresh cycle every 64000/4096
+ * = 15.625 usecs.
+ *
+ * So PTP * (PSRT + 1) <= 15.625 * BusClock. At 66.666MHz, PSRT=31 and PTP=32
+ * appear to be reasonable.
+ */
+
+#ifdef DEBUG
+#define CONFIG_SYS_PSRT	39
+#define CONFIG_SYS_MPTPR	MPTPR_PTP_DIV8
+#else
+#define CONFIG_SYS_PSRT	31
+#define CONFIG_SYS_MPTPR	MPTPR_PTP_DIV32
+#endif
+
+/*
+ * Banks 3,4,5 and 6 - FPGA access
+ *
+ * Quotes from the HYMOD IO Board Reference manual:
+ *
+ * "The IO Board is fitted with a Xilinx XCV300E main FPGA. Provision is made
+ *  for configuring an optional FPGA on the mezzanine interface.
+ *
+ *  Access to the FPGAs may be divided into several catagories:
+ *
+ *  1. Configuration
+ *  2. Register mode access
+ *  3. Port mode access
+ *
+ *  The main FPGA is supported for modes 1, 2 and 3. The mezzanine FPGA can be
+ *  configured only (mode 1). Consequently there are four access types.
+ *
+ *  To improve interface performance and simplify software design, the four
+ *  possible access types are separately mapped to different memory banks.
+ *
+ *  All are accessed using the local bus."
+ *
+ *	 Device		    Mode      Memory Bank Machine Port Size    Access
+ *
+ *	  Main		Configuration	   3	   UPMC	     8bit	R/W
+ *	  Main		  Register	   4	   GPCM	    32bit	R/W
+ *	  Main		    Port	   5	   UPMB	    32bit	R/W
+ *	Mezzanine	Configuration	   6	   UPMC	     8bit	W/O
+ *
+ * "Note that mezzanine mode 1 access is write-only."
+ */
+
+/* all the bank sizes must be a power of two, greater or equal to 32768 */
+#define FPGA_MAIN_CFG_BASE	(CONFIG_SYS_FPGA_BASE)
+#define FPGA_MAIN_CFG_SIZE	32768
+#define FPGA_MAIN_REG_BASE	(FPGA_MAIN_CFG_BASE + FPGA_MAIN_CFG_SIZE)
+#define FPGA_MAIN_REG_SIZE	32768
+#define FPGA_MAIN_PORT_BASE	(FPGA_MAIN_REG_BASE + FPGA_MAIN_REG_SIZE)
+#define FPGA_MAIN_PORT_SIZE	32768
+#define FPGA_MEZZ_CFG_BASE	(FPGA_MAIN_PORT_BASE + FPGA_MAIN_PORT_SIZE)
+#define FPGA_MEZZ_CFG_SIZE	32768
+
+/* 8 bit, read-write, UPMC */
+#define	CONFIG_SYS_BR3_PRELIM	(FPGA_MAIN_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V)
+/* up to 32Kbyte, burst inhibit */
+#define	CONFIG_SYS_OR3_PRELIM	(P2SZ_TO_AM(FPGA_MAIN_CFG_SIZE)|ORxU_BI)
+
+/* 32 bit, read-write, GPCM */
+#define	CONFIG_SYS_BR4_PRELIM	(FPGA_MAIN_REG_BASE|BRx_PS_32|BRx_MS_GPCM_L|BRx_V)
+/* up to 32Kbyte */
+#define	CONFIG_SYS_OR4_PRELIM	(P2SZ_TO_AM(FPGA_MAIN_REG_SIZE))
+
+/* 32 bit, read-write, UPMB */
+#define	CONFIG_SYS_BR5_PRELIM	(FPGA_MAIN_PORT_BASE|BRx_PS_32|BRx_MS_UPMB|BRx_V)
+/* up to 32Kbyte */
+#define	CONFIG_SYS_OR5_PRELIM	(P2SZ_TO_AM(FPGA_MAIN_PORT_SIZE)|ORxU_BI)
+
+/* 8 bit, write-only, UPMC */
+#define	CONFIG_SYS_BR6_PRELIM	(FPGA_MEZZ_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V)
+/* up to 32Kbyte, burst inhibit */
+#define	CONFIG_SYS_OR6_PRELIM	(P2SZ_TO_AM(FPGA_MEZZ_CFG_SIZE)|ORxU_BI)
+
+/*-----------------------------------------------------------------------
+ * MBMR - Machine B Mode					10-27
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_MBMR	(MxMR_BSEL|MxMR_OP_NORM)	/* XXX - needs more */
+
+/*-----------------------------------------------------------------------
+ * MCMR - Machine C Mode					10-27
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_MCMR	(MxMR_BSEL|MxMR_DSx_2_CYCL)	/* XXX - needs more */
+
+/*
+ * FPGA I/O Port/Bit information
+ */
+
+#define FPGA_MAIN_PROG_PORT	IOPIN_PORTA
+#define FPGA_MAIN_PROG_PIN	4	/* PA4 */
+#define FPGA_MAIN_INIT_PORT	IOPIN_PORTA
+#define FPGA_MAIN_INIT_PIN	5	/* PA5 */
+#define FPGA_MAIN_DONE_PORT	IOPIN_PORTA
+#define FPGA_MAIN_DONE_PIN	6	/* PA6 */
+
+#define FPGA_MEZZ_PROG_PORT	IOPIN_PORTA
+#define FPGA_MEZZ_PROG_PIN	0	/* PA0 */
+#define FPGA_MEZZ_INIT_PORT	IOPIN_PORTA
+#define FPGA_MEZZ_INIT_PIN	1	/* PA1 */
+#define FPGA_MEZZ_DONE_PORT	IOPIN_PORTA
+#define FPGA_MEZZ_DONE_PIN	2	/* PA2 */
+#define FPGA_MEZZ_ENABLE_PORT	IOPIN_PORTA
+#define FPGA_MEZZ_ENABLE_PIN	3	/* PA3 */
+
+/*
+ * FPGA Interrupt configuration
+ */
+#define FPGA_MAIN_IRQ		SIU_INT_IRQ2
+
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_CMD_MTDPARTS
+#define CONFIG_JFFS2_DEV		"nor0"
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET	0x00000000
+
+/* mtdparts command line support */
+/*
+#define CONFIG_CMD_MTDPARTS
+#define MTDIDS_DEFAULT		""
+#define MTDPARTS_DEFAULT	""
+*/
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/ib62x0.h b/qemu/roms/u-boot/include/configs/ib62x0.h
new file mode 100644
index 000000000..186fd35fd
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/ib62x0.h
@@ -0,0 +1,146 @@
+/*
+ * Copyright (C) 2011-2012
+ * Gerald Kerma <dreagle@doukki.net>
+ * Luka Perkov <luka@openwrt.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CONFIG_IB62x0_H
+#define _CONFIG_IB62x0_H
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING	" RaidSonic ICY BOX IB-NAS62x0"
+
+/*
+ * High level configuration options
+ */
+#define CONFIG_FEROCEON_88FR131		/* CPU Core subversion */
+#define CONFIG_KIRKWOOD			/* SOC Family Name */
+#define CONFIG_KW88F6281		/* SOC Name */
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+
+/*
+ * Machine type
+ */
+#define CONFIG_MACH_TYPE	MACH_TYPE_NAS6210
+
+/*
+ * Enable device tree support
+ */
+#define CONFIG_OF_LIBFDT
+
+/*
+ * Compression configuration
+ */
+#define CONFIG_BZIP2
+#define CONFIG_LZMA
+#define CONFIG_LZO
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH		/* declare no flash (NOR/SPI) */
+#define CONFIG_SYS_MVFS
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+#undef CONFIG_SYS_PROMPT
+#define CONFIG_SYS_PROMPT	"ib62x0 => "
+
+/*
+ * Environment variables configuration
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SECT_SIZE	0x20000
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+#define CONFIG_ENV_SIZE		0x20000
+#define CONFIG_ENV_OFFSET	0xe0000
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_BOOTCOMMAND \
+	"setenv bootargs ${console} ${mtdparts} ${bootargs_root}; "	\
+	"ubi part root; "						\
+	"ubifsmount ubi:rootfs; "					\
+	"ubifsload 0x800000 ${kernel}; "				\
+	"ubifsload 0x700000 ${fdt}; "					\
+	"ubifsumount; "							\
+	"fdt addr 0x700000; fdt resize; fdt chosen; "			\
+	"bootz 0x800000 - 0x700000"
+
+#define CONFIG_MTDPARTS \
+	"mtdparts=orion_nand:"						\
+	"0xe0000@0x0(uboot),"						\
+	"0x20000@0xe0000(uboot_env),"					\
+	"-@0x100000(root)\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"console=console=ttyS0,115200\0"				\
+	"mtdids=nand0=orion_nand\0"					\
+	"mtdparts="CONFIG_MTDPARTS					\
+	"kernel=/boot/zImage\0"						\
+	"fdt=/boot/ib62x0.dtb\0"					\
+	"bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs rw\0"
+
+/*
+ * Ethernet driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS	{1, 0}	/* enable port 0 only */
+#define CONFIG_PHY_BASE_ADR	0
+#undef CONFIG_RESET_PHY_R
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * SATA driver configuration
+ */
+#ifdef CONFIG_CMD_IDE
+#define __io
+#define CONFIG_IDE_PREINIT
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MVSATA_IDE_USE_PORT0
+#define CONFIG_MVSATA_IDE_USE_PORT1
+#define CONFIG_SYS_ATA_IDE0_OFFSET	MV_SATA_PORT0_OFFSET
+#define CONFIG_SYS_ATA_IDE1_OFFSET	MV_SATA_PORT1_OFFSET
+#endif /* CONFIG_CMD_IDE */
+
+/*
+ * RTC driver configuration
+ */
+#ifdef CONFIG_CMD_DATE
+#define CONFIG_RTC_MV
+#endif /* CONFIG_CMD_DATE */
+
+/*
+ * File system
+ */
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+
+#endif /* _CONFIG_IB62x0_H */
diff --git a/qemu/roms/u-boot/include/configs/ibf-dsp561.h b/qemu/roms/u-boot/include/configs/ibf-dsp561.h
new file mode 100644
index 000000000..ac5ca9af3
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/ibf-dsp561.h
@@ -0,0 +1,124 @@
+/*
+ * U-boot - Configuration file for IBF-DSP561 board
+ */
+
+#ifndef __CONFIG_IBF_DSP561__H__
+#define __CONFIG_IBF_DSP561__H__
+
+#include <asm/config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU             bf561-0.5
+#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
+
+
+/*
+ * Clock Settings
+ *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz					*/
+#define CONFIG_CLKIN_HZ			25000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
+/*                                                1 = CLKIN / 2		*/
+#define CONFIG_CLKIN_HALF		0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
+/*                                                1 = bypass PLL	*/
+#define CONFIG_PLL_BYPASS		0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
+/* Values can range from 0-63 (where 0 means 64)			*/
+#define CONFIG_VCO_MULT			24
+/* CCLK_DIV controls the core clock divider				*/
+/* Values can be 1, 2, 4, or 8 ONLY					*/
+#define CONFIG_CCLK_DIV			1
+/* SCLK_DIV controls the system clock divider				*/
+/* Values can range from 1-15						*/
+#define CONFIG_SCLK_DIV			5
+
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_ADD_WDTH	9
+#define CONFIG_MEM_SIZE		64
+
+#define CONFIG_EBIU_SDRRC_VAL	0x377
+#define CONFIG_EBIU_SDGCTL_VAL	0x91998d
+#define CONFIG_EBIU_SDBCTL_VAL	0x15
+
+#define CONFIG_EBIU_AMGCTL_VAL	0x3F
+#define CONFIG_EBIU_AMBCTL0_VAL	0x7BB07BB0
+#define CONFIG_EBIU_AMBCTL1_VAL	0xFFC27BB0
+
+#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN	(128 * 1024)
+
+
+/*
+ * Network Settings
+ */
+#define ADI_CMDS_NETWORK	1
+#define CONFIG_DRIVER_AX88180	1
+#define AX88180_BASE		0x2c000000
+#define CONFIG_HOSTNAME		ibf-dsp561
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR	02:80:ad:20:31:e8 */
+
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_SYS_FLASH_CFI		/* The flash is CFI compatible */
+#define CONFIG_FLASH_CFI_DRIVER	/* Use common CFI driver */
+#define CONFIG_SYS_FLASH_CFI_AMD_RESET
+#define CONFIG_SYS_FLASH_BASE		0x20000000
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	135	/* max number of sectors on one chip */
+/* The BF561-EZKIT uses a top boot flash */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_OFFSET		0x4000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x10000	/* Total Size of Environment Sector */
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
+#define ENV_IS_EMBEDDED
+#else
+#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
+#endif
+#ifdef ENV_IS_EMBEDDED
+/* WARNING - the following is hand-optimized to fit within
+ * the sector before the environment sector. If it throws
+ * an error during compilation remove an object here to get
+ * it linked after the configuration sector.
+ */
+# define LDS_BOARD_TEXT \
+	arch/blackfin/lib/built-in.o (.text*); \
+	arch/blackfin/cpu/built-in.o (.text*); \
+	. = DEFINED(env_offset) ? env_offset : .; \
+	common/env_embedded.o (.text*);
+#endif
+
+
+/*
+ * I2C Settings
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
+#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF0
+#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF1
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_UART_CONSOLE	0
+
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/icon.h b/qemu/roms/u-boot/include/configs/icon.h
new file mode 100644
index 000000000..bbe9b59b5
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/icon.h
@@ -0,0 +1,314 @@
+/*
+ * (C) Copyright 2009-2010
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * icon.h - configuration for Mosaixtech ICON (440SPe)
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ICON		1		/* Board is icon	*/
+#define CONFIG_440		1		/* ... PPC440 family	*/
+#define CONFIG_440SPE		1		/* Specifc SPe support	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFA0000
+
+#define CONFIG_SYS_CLK_FREQ	33333333	/* external freq to pll	*/
+#define CONFIG_SYS_4xx_RESET_TYPE 0x2	/* use chip reset on this board	*/
+
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME		icon
+#include "amcc-common.h"
+
+#define CONFIG_BOARD_EARLY_INIT_F	/* Call board_pre_init	*/
+#define CONFIG_BOARD_EARLY_INIT_R	/* Call board_early_init_r */
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_FLASH_BASE	0xfc000000	/* later mapped to this addr */
+#define CONFIG_SYS_ISRAM_BASE	0x90000000	/* internal SRAM	*/
+
+#define CONFIG_SYS_PCI_MEMBASE	0x80000000	/* mapped PCI memory	*/
+#define CONFIG_SYS_PCI_BASE	0xd0000000	/* internal PCI regs	*/
+#define CONFIG_SYS_PCI_TARGBASE	CONFIG_SYS_PCI_MEMBASE
+
+#define CONFIG_SYS_PCIE_MEMBASE	0xb0000000	/* mapped PCIe memory	*/
+#define CONFIG_SYS_PCIE_MEMSIZE	0x08000000	/* incr for PCIe port */
+#define CONFIG_SYS_PCIE_BASE	0xe0000000	/* PCIe UTL regs */
+
+#define CONFIG_SYS_PCIE0_CFGBASE	0xc0000000
+#define CONFIG_SYS_PCIE1_CFGBASE	0xc1000000
+#define CONFIG_SYS_PCIE2_CFGBASE	0xc2000000
+#define CONFIG_SYS_PCIE0_XCFGBASE	0xc3000000
+#define CONFIG_SYS_PCIE1_XCFGBASE	0xc3001000
+#define CONFIG_SYS_PCIE2_XCFGBASE	0xc3002000
+
+/* base address of inbound PCIe window */
+#define CONFIG_SYS_PCIE_INBOUND_BASE	0x0000000000000000ULL
+
+/* System RAM mapped to PCI space */
+#define CONFIG_PCI_SYS_MEM_BUS	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_PHYS	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_SIZE	(1024 * 1024 * 1024)
+
+#define CONFIG_SYS_ACE_BASE		0xfb000000	/* Xilinx ACE CF */
+#define CONFIG_SYS_ACE_BASE_PHYS_H	0x4
+#define CONFIG_SYS_ACE_BASE_PHYS_L	0xfe000000
+
+#define CONFIG_SYS_FLASH_SIZE		(64 << 20)
+#define CONFIG_SYS_BOOT_BASE_ADDR	0xFF000000	/* EBC Boot Space */
+#define CONFIG_SYS_FLASH_BASE_PHYS_H	0x4
+#define CONFIG_SYS_FLASH_BASE_PHYS_L	0xEC000000
+#define CONFIG_SYS_FLASH_BASE_PHYS	(((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) | \
+					 (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
+
+/*
+ * Initial RAM & stack pointer (placed in internal SRAM)
+ */
+#define CONFIG_SYS_TEMP_STACK_OCM	1
+#define CONFIG_SYS_OCM_DATA_ADDR	CONFIG_SYS_ISRAM_BASE
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_ISRAM_BASE	/* Init RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000		/* size of used area */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#undef CONFIG_SYS_EXT_SERIAL_CLOCK
+
+/*
+ * DDR2 SDRAM
+ */
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for setup	*/
+#define SPD_EEPROM_ADDRESS	{ 0x51 } /* SPD I2C SPD addresses	*/
+#define CONFIG_DDR_ECC			/* with ECC support		*/
+#define CONFIG_DDR_RQDC_FIXED	0x80000038 /* fixed value for RQDC	*/
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0	100000
+
+#define CONFIG_SYS_SPD_BUS_NUM	0	/* The I2C bus for SPD		*/
+
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+/* I2C bootstrap EEPROM */
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR	0x50
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET	0
+#define CONFIG_4xx_CONFIG_BLOCKSIZE		8
+
+/* I2C RTC */
+#define CONFIG_RTC_M41T11
+#define CONFIG_SYS_RTC_BUS_NUM	1	/* The I2C bus for RTC		*/
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with linux	*/
+
+/*
+ * Video options
+ */
+#define CONFIG_VIDEO
+
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO_SM501
+#define CONFIG_VIDEO_SM501_32BPP
+#define CONFIG_VIDEO_SM501_PCI
+#define VIDEO_FB_LITTLE_ENDIAN
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_CONSOLE_EXTRA_INFO
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CFG_CONSOLE_IS_IN_ENV
+#endif
+
+/*
+ * Environment
+ */
+#define	CONFIG_ENV_IS_IN_FLASH	1	/* Environment uses flash	*/
+
+/*
+ * Default environment variables
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_AMCC_DEF_ENV						\
+	CONFIG_AMCC_DEF_ENV_POWERPC					\
+	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
+	"kernel_addr=fc000000\0"					\
+	"fdt_addr=fc1e0000\0"						\
+	"ramdisk_addr=fc200000\0"					\
+	"pciconfighost=1\0"						\
+	"pcie_mode=RP:RP:RP\0"						\
+	""
+
+/*
+ * Commands additional to the ones defined in amcc-common.h
+ */
+#define CONFIG_CMD_CHIP_CONFIG
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
+#ifdef CONFIG_VIDEO
+#define CONFIG_CMD_BMP
+#endif
+
+#define	CONFIG_IBM_EMAC4_V4		/* 440SPe has this EMAC version	*/
+#define CONFIG_PHY_ADDR		1	/* PHY address, See schematics	*/
+#define CONFIG_HAS_ETH0
+#define CONFIG_PHY_RESET		/* reset phy upon startup	*/
+#define CONFIG_PHY_RESET_DELAY	1000
+#define CONFIG_CIS8201_PHY		/* Enable RGMII mode for Cicada phy */
+#define CONFIG_PHY_GIGE			/* Include GbE speed/duplex det. */
+
+/*
+ * FLASH related
+ */
+#define CONFIG_SYS_FLASH_CFI		/* The flash is CFI compatible	*/
+#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
+#define CONFIG_SYS_FLASH_CFI_AMD_RESET	/* Use AMD (Spansion) reset cmd */
+#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* use status poll method	*/
+
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* TO for Flash Erase (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* TO for Flash Write (ms) */
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	/* use buffered writes	*/
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* 'E' for empty sector */
+
+#define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector	*/
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Env Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+/*
+ * PCI stuff
+ */
+/* General PCI */
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE
+#define CONFIG_PCI_BOOTDELAY	1000	/* enable pci bootdelay variable*/
+
+/* Board-specific PCI */
+#define CONFIG_SYS_PCI_TARGET_INIT	/* let board init pci target    */
+#undef	CONFIG_SYS_PCI_MASTER_INIT
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014	/* IBM			*/
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever		*/
+
+/*
+ * Xilinx System ACE support
+ */
+#define CONFIG_SYSTEMACE		/* Enable SystemACE support	*/
+#define CONFIG_SYS_SYSTEMACE_WIDTH	16	/* Data bus width is 16	*/
+#define CONFIG_SYS_SYSTEMACE_BASE	CONFIG_SYS_ACE_BASE
+#define CONFIG_DOS_PARTITION
+
+/*
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash) initialization					*/
+#define CONFIG_SYS_EBC_PB0AP	(EBC_BXAP_BME_DISABLED      |		\
+				 EBC_BXAP_TWT_ENCODE(7)     |		\
+				 EBC_BXAP_BCE_DISABLE       |		\
+				 EBC_BXAP_BCT_2TRANS        |		\
+				 EBC_BXAP_CSN_ENCODE(0)     |		\
+				 EBC_BXAP_OEN_ENCODE(0)     |		\
+				 EBC_BXAP_WBN_ENCODE(0)     |		\
+				 EBC_BXAP_WBF_ENCODE(0)     |		\
+				 EBC_BXAP_TH_ENCODE(0)      |		\
+				 EBC_BXAP_RE_DISABLED       |		\
+				 EBC_BXAP_SOR_DELAYED       |		\
+				 EBC_BXAP_BEM_WRITEONLY     |		\
+				 EBC_BXAP_PEN_DISABLED)
+#define CONFIG_SYS_EBC_PB0CR	(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
+				 EBC_BXCR_BS_64MB                    |	\
+				 EBC_BXCR_BU_RW                      |	\
+				 EBC_BXCR_BW_16BIT)
+
+/* Memory Bank 1 (Xilinx System ACE controller) initialization		*/
+#define CONFIG_SYS_EBC_PB1AP	(EBC_BXAP_BME_DISABLED      |		\
+				 EBC_BXAP_TWT_ENCODE(4)     |		\
+				 EBC_BXAP_BCE_DISABLE       |		\
+				 EBC_BXAP_BCT_2TRANS        |		\
+				 EBC_BXAP_CSN_ENCODE(0)     |		\
+				 EBC_BXAP_OEN_ENCODE(0)     |		\
+				 EBC_BXAP_WBN_ENCODE(0)     |		\
+				 EBC_BXAP_WBF_ENCODE(0)     |		\
+				 EBC_BXAP_TH_ENCODE(0)      |		\
+				 EBC_BXAP_RE_DISABLED       |		\
+				 EBC_BXAP_SOR_NONDELAYED    |		\
+				 EBC_BXAP_BEM_WRITEONLY     |		\
+				 EBC_BXAP_PEN_DISABLED)
+#define CONFIG_SYS_EBC_PB1CR	(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_ACE_BASE_PHYS_L) | \
+				 EBC_BXCR_BS_1MB                    |	\
+				 EBC_BXCR_BU_RW                     |	\
+				 EBC_BXCR_BW_16BIT)
+
+/*
+ * Initialize EBC CONFIG -
+ * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
+ * default value : 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
+ */
+#define CONFIG_SYS_EBC_CFG	(EBC_CFG_LE_UNLOCK    |	\
+				 EBC_CFG_PTD_ENABLE   |	\
+				 EBC_CFG_RTC_16PERCLK | \
+				 EBC_CFG_ATC_PREVIOUS | \
+				 EBC_CFG_DTC_PREVIOUS | \
+				 EBC_CFG_CTC_PREVIOUS | \
+				 EBC_CFG_OEO_PREVIOUS | \
+				 EBC_CFG_EMC_DEFAULT  |	\
+				 EBC_CFG_PME_DISABLE  |	\
+				 EBC_CFG_PR_16)
+
+/*
+ * GPIO Setup
+ */
+#define CONFIG_SYS_GPIO_PCIE_PRESENT0	17
+#define CONFIG_SYS_GPIO_PCIE_PRESENT1	21
+#define CONFIG_SYS_GPIO_PCIE_PRESENT2	23
+#define CONFIG_SYS_GPIO_RS232_FORCEOFF	30
+
+#define CONFIG_SYS_PFC0		(GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0) | \
+				 GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1) | \
+				 GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2) | \
+				 GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF))
+#define CONFIG_SYS_GPIO_OR	GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
+#define CONFIG_SYS_GPIO_TCR	GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
+#define CONFIG_SYS_GPIO_ODR	0
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/iconnect.h b/qemu/roms/u-boot/include/configs/iconnect.h
new file mode 100644
index 000000000..a58f076c2
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/iconnect.h
@@ -0,0 +1,115 @@
+/*
+ * (C) Copyright 2009-2012
+ * Wojciech Dubowik <wojciech.dubowik@neratec.com>
+ * Luka Perkov <luka@openwrt.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CONFIG_ICONNECT_H
+#define _CONFIG_ICONNECT_H
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING	" Iomega iConnect"
+
+/*
+ * High level configuration options
+ */
+#define CONFIG_FEROCEON_88FR131		/* CPU Core subversion */
+#define CONFIG_KIRKWOOD			/* SOC Family Name */
+#define CONFIG_KW88F6281		/* SOC Name */
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+
+/*
+ * Machine type
+ */
+#define CONFIG_MACH_TYPE	MACH_TYPE_ICONNECT
+
+/*
+ * Compression configuration
+ */
+#define CONFIG_BZIP2
+#define CONFIG_LZMA
+#define CONFIG_LZO
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH		/* declare no flash (NOR/SPI) */
+#define CONFIG_SYS_MVFS
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+#undef CONFIG_SYS_PROMPT
+#define CONFIG_SYS_PROMPT	"iconnect => "
+
+/*
+ * Environment variables configuration
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SECT_SIZE	0x20000
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+#define CONFIG_ENV_SIZE		0x20000
+#define CONFIG_ENV_OFFSET	0x80000
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_BOOTCOMMAND \
+	"setenv bootargs ${console} ${mtdparts} ${bootargs_root}; "	\
+	"ubi part rootfs; "						\
+	"ubifsmount ubi:rootfs; "					\
+	"ubifsload 0x800000 ${kernel}; "				\
+	"bootm 0x800000"
+
+#define CONFIG_MTDPARTS \
+	"mtdparts=orion_nand:"		\
+	"0x80000@0x0(uboot),"		\
+	"0x20000@0x80000(uboot_env),"	\
+	"-@0xa0000(rootfs)\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"console=console=ttyS0,115200\0"	\
+	"mtdids=nand0=orion_nand\0"		\
+	"mtdparts="CONFIG_MTDPARTS		\
+	"kernel=/boot/uImage\0"			\
+	"bootargs_root=noinitrd ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs\0"
+
+/*
+ * Ethernet driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS	{1, 0}	/* enable port 0 only */
+#define CONFIG_PHY_BASE_ADR	11
+#undef CONFIG_RESET_PHY_R
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * File system
+ */
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+
+#endif /* _CONFIG_ICONNECT_H */
diff --git a/qemu/roms/u-boot/include/configs/ids8313.h b/qemu/roms/u-boot/include/configs/ids8313.h
new file mode 100644
index 000000000..c1b3b633e
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/ids8313.h
@@ -0,0 +1,586 @@
+/*
+ * (C) Copyright 2013
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * Copyright (c) 2011 IDS GmbH, Germany
+ * Sergej Stepanov <ste@ids.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_MPC831x
+#define CONFIG_MPC8313
+#define CONFIG_IDS8313
+
+#define CONFIG_FSL_ELBC
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT	\
+	"\nEnter password - autoboot in %d seconds...\n", CONFIG_BOOTDELAY
+#define CONFIG_AUTOBOOT_DELAY_STR	"ids"
+#define CONFIG_BOOT_RETRY_TIME		900
+#define CONFIG_BOOT_RETRY_MIN		30
+#define CONFIG_BOOTDELAY		1
+#define CONFIG_RESET_TO_RETRY
+
+#define CONFIG_83XX_CLKIN		66000000	/* in Hz */
+#define CONFIG_SYS_CLK_FREQ		CONFIG_83XX_CLKIN
+
+#define CONFIG_SYS_IMMR		0xF0000000
+
+#define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
+#define CONFIG_SYS_ACR_RPTCNT		3	/* Arbiter repeat count (0-7) */
+
+/*
+ * Hardware Reset Configuration Word
+ * if CLKIN is 66.000MHz, then
+ * CSB = 132MHz, CORE = 264MHz, DDRC = 264MHz, LBC = 132MHz
+ */
+#define CONFIG_SYS_HRCW_LOW (0x20000000 /* reserved, must be set */ |\
+			     HRCWL_DDR_TO_SCB_CLK_2X1 |\
+			     HRCWL_CSB_TO_CLKIN_2X1 |\
+			     HRCWL_CORE_TO_CSB_2X1)
+
+#define CONFIG_SYS_HRCW_HIGH	(HRCWH_PCI_HOST |\
+				 HRCWH_CORE_ENABLE |\
+				 HRCWH_FROM_0XFFF00100 |\
+				 HRCWH_BOOTSEQ_DISABLE |\
+				 HRCWH_SW_WATCHDOG_DISABLE |\
+				 HRCWH_ROM_LOC_LOCAL_8BIT |\
+				 HRCWH_RL_EXT_LEGACY |\
+				 HRCWH_TSEC1M_IN_MII |\
+				 HRCWH_TSEC2M_IN_MII |\
+				 HRCWH_BIG_ENDIAN)
+
+#define CONFIG_SYS_SICRH	0x00000000
+#define CONFIG_SYS_SICRL	(SICRL_LBC | SICRL_SPI_D)
+
+#define CONFIG_HWCONFIG
+
+#define CONFIG_SYS_HID0_INIT	0x000000000
+#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK |\
+				 HID0_ENABLE_INSTRUCTION_CACHE |\
+				 HID0_DISABLE_DYNAMIC_POWER_MANAGMENT)
+
+#define CONFIG_SYS_HID2	(HID2_HBE | 0x00020000)
+
+/*
+ * Definitions for initial stack pointer and data area (in DCACHE )
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000  /* End of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_SIZE	0x100
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE \
+					 - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * Local Bus LCRR and LBCR regs
+ */
+#define CONFIG_SYS_LCRR_EADC		LCRR_EADC_1
+#define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_2
+#define CONFIG_SYS_LBC_LBCR		(0x00040000 |\
+					 (0xFF << LBCR_BMT_SHIFT) |\
+					 0xF)
+
+#define CONFIG_SYS_LBC_MRTPR		0x20000000
+
+/*
+ * Internal Definitions
+ */
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_DDR_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
+
+/*
+ * Manually set up DDR parameters,
+ * as this board has not the SPD connected to I2C.
+ */
+#define CONFIG_SYS_DDR_SIZE		256		/* MB */
+#define CONFIG_SYS_DDR_CONFIG		(CSCONFIG_EN |\
+					 0x00010000 |\
+					 CSCONFIG_ROW_BIT_13 |\
+					 CSCONFIG_COL_BIT_10)
+
+#define CONFIG_SYS_DDR_CONFIG_256	(CONFIG_SYS_DDR_CONFIG | \
+					 CSCONFIG_BANK_BIT_3)
+
+#define CONFIG_SYS_DDR_TIMING_3	(1 << 16)	/* ext refrec */
+#define CONFIG_SYS_DDR_TIMING_0	((3 << TIMING_CFG0_RWT_SHIFT) |\
+				(3 << TIMING_CFG0_WRT_SHIFT) |\
+				(3 << TIMING_CFG0_RRT_SHIFT) |\
+				(3 << TIMING_CFG0_WWT_SHIFT) |\
+				(6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) |\
+				(2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) |\
+				(8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
+				(2 << TIMING_CFG0_MRS_CYC_SHIFT))
+#define CONFIG_SYS_DDR_TIMING_1	((4 << TIMING_CFG1_PRETOACT_SHIFT) |\
+				(12 << TIMING_CFG1_ACTTOPRE_SHIFT) |\
+				(4 << TIMING_CFG1_ACTTORW_SHIFT) |\
+				(7 << TIMING_CFG1_CASLAT_SHIFT) |\
+				(4 << TIMING_CFG1_REFREC_SHIFT) |\
+				(4 << TIMING_CFG1_WRREC_SHIFT) |\
+				(2 << TIMING_CFG1_ACTTOACT_SHIFT) |\
+				(2 << TIMING_CFG1_WRTORD_SHIFT))
+#define CONFIG_SYS_DDR_TIMING_2	((1 << TIMING_CFG2_ADD_LAT_SHIFT) |\
+				(5 << TIMING_CFG2_CPO_SHIFT) |\
+				(4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) |\
+				(2 << TIMING_CFG2_RD_TO_PRE_SHIFT) |\
+				(0 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) |\
+				(1 << TIMING_CFG2_CKE_PLS_SHIFT) |\
+				(6 << TIMING_CFG2_FOUR_ACT_SHIFT))
+
+#define CONFIG_SYS_DDR_INTERVAL	((0x800 << SDRAM_INTERVAL_REFINT_SHIFT) |\
+				(0x800 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
+
+#define CONFIG_SYS_SDRAM_CFG		(SDRAM_CFG_SREN |\
+					 SDRAM_CFG_2T_EN | SDRAM_CFG_HSE |\
+					 SDRAM_CFG_DBW_32 |\
+					 SDRAM_CFG_SDRAM_TYPE_DDR2)
+
+#define CONFIG_SYS_SDRAM_CFG2		0x00401000
+#define CONFIG_SYS_DDR_MODE		((0x0448 << SDRAM_MODE_ESD_SHIFT) |\
+					 (0x0242 << SDRAM_MODE_SD_SHIFT))
+#define CONFIG_SYS_DDR_MODE_2		0x00000000
+#define CONFIG_SYS_DDR_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075
+#define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN |\
+					 DDRCDR_PZ_NOMZ |\
+					 DDRCDR_NZ_NOMZ |\
+					 DDRCDR_ODT |\
+					 DDRCDR_M_ODR |\
+					 DDRCDR_Q_DRN)
+
+/*
+ * on-board devices
+ */
+#define CONFIG_TSEC1
+#define CONFIG_TSEC2
+#define CONFIG_TSEC_ENET
+#define CONFIG_NET_MULTI
+#define CONFIG_HARD_SPI
+#define CONFIG_HARD_I2C
+
+/*
+ * NOR FLASH setup
+ */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
+#define CONFIG_FLASH_SHOW_PROGRESS	50
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+#define CONFIG_SYS_FLASH_BASE		0xFF800000
+#define CONFIG_SYS_FLASH_SIZE		8
+#define CONFIG_SYS_FLASH_PROTECTION
+
+#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_LBLAWAR0_PRELIM	0x80000016
+
+#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE |\
+					 BR_PS_8 |\
+					 BR_MS_GPCM |\
+					 BR_V)
+
+#define CONFIG_SYS_OR0_PRELIM		(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
+					 OR_GPCM_SCY_10 |\
+					 OR_GPCM_EHTR |\
+					 OR_GPCM_TRLX |\
+					 OR_GPCM_CSNT |\
+					 OR_GPCM_EAD)
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	128
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500
+
+/*
+ * NAND FLASH setup
+ */
+#define CONFIG_SYS_NAND_BASE		0xE1000000
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_MAX_CHIPS	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_NAND_FSL_ELBC
+#define CONFIG_SYS_NAND_PAGE_SIZE	(2048)
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 << 10)
+#define NAND_CACHE_PAGES		64
+
+#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_NAND_BASE
+#define CONFIG_SYS_LBLAWAR1_PRELIM	0x8000000E
+#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
+#define CONFIG_SYS_NAND_LBLAWAR_PRELIM	CONFIG_SYS_LBLAWAR1_PRELIM
+
+#define CONFIG_SYS_BR1_PRELIM	((CONFIG_SYS_NAND_BASE) |\
+				 (2<<BR_DECC_SHIFT) |\
+				 BR_PS_8 |\
+				 BR_MS_FCM |\
+				 BR_V)
+
+#define CONFIG_SYS_OR1_PRELIM	(0xFFFF8000 |\
+				 OR_FCM_PGS |\
+				 OR_FCM_CSCT |\
+				 OR_FCM_CST |\
+				 OR_FCM_CHT |\
+				 OR_FCM_SCY_4 |\
+				 OR_FCM_TRLX |\
+				 OR_FCM_EHTR |\
+				 OR_FCM_RST)
+
+/*
+ * MRAM setup
+ */
+#define CONFIG_SYS_MRAM_BASE		0xE2000000
+#define CONFIG_SYS_MRAM_SIZE		0x20000	/* 128 Kb */
+#define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_MRAM_BASE
+#define CONFIG_SYS_LBLAWAR2_PRELIM	0x80000010	/* 128 Kb  */
+
+#define CONFIG_SYS_OR_TIMING_MRAM
+
+#define CONFIG_SYS_BR2_PRELIM		(CONFIG_SYS_MRAM_BASE |\
+					 BR_PS_8 |\
+					 BR_MS_GPCM |\
+					 BR_V)
+
+#define CONFIG_SYS_OR2_PRELIM		0xFFFE0C74
+
+/*
+ * CPLD setup
+ */
+#define CONFIG_SYS_CPLD_BASE		0xE3000000
+#define CONFIG_SYS_CPLD_SIZE		0x8000
+#define CONFIG_SYS_LBLAWBAR3_PRELIM	CONFIG_SYS_CPLD_BASE
+#define CONFIG_SYS_LBLAWAR3_PRELIM	0x8000000E
+
+#define CONFIG_SYS_OR_TIMING_MRAM
+
+#define CONFIG_SYS_BR3_PRELIM		(CONFIG_SYS_CPLD_BASE |\
+					 BR_PS_8 |\
+					 BR_MS_GPCM |\
+					 BR_V)
+
+#define CONFIG_SYS_OR3_PRELIM		0xFFFF8814
+
+/*
+ * HW-Watchdog
+ */
+#define CONFIG_WATCHDOG		1
+#define CONFIG_SYS_WATCHDOG_VALUE	0xFFFF
+
+/*
+ * I2C setup
+ */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3100
+#define CONFIG_RTC_PCF8563
+#define CONFIG_SYS_I2C_RTC_ADDR	0x51
+
+/*
+ * SPI setup
+ */
+#ifdef CONFIG_HARD_SPI
+#define CONFIG_MPC8XXX_SPI
+#define CONFIG_CMD_SPI
+#define CONFIG_SYS_GPIO1_PRELIM
+#define CONFIG_SYS_GPIO1_DIR		0x00000001
+#define CONFIG_SYS_GPIO1_DAT		0x00000001
+#endif
+
+/*
+ * Ethernet setup
+ */
+#ifdef CONFIG_TSEC1
+#define CONFIG_HAS_ETH0
+#define CONFIG_TSEC1_NAME		"TSEC0"
+#define CONFIG_SYS_TSEC1_OFFSET	0x24000
+#define TSEC1_PHY_ADDR			0x1
+#define TSEC1_FLAGS			TSEC_GIGABIT
+#define TSEC1_PHYIDX			0
+#endif
+
+#ifdef CONFIG_TSEC2
+#define CONFIG_HAS_ETH1
+#define CONFIG_TSEC2_NAME		"TSEC1"
+#define CONFIG_SYS_TSEC2_OFFSET	0x25000
+#define TSEC2_PHY_ADDR			0x3
+#define TSEC2_FLAGS			TSEC_GIGABIT
+#define TSEC2_PHYIDX			0
+#endif
+#define CONFIG_ETHPRIME		"TSEC1"
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)
+#define CONFIG_SYS_NS16550_CLK		(CONFIG_83XX_CLKIN * 2)
+
+#define CONFIG_HAS_FSL_DR_USB
+#define CONFIG_SYS_SCCR_USBDRCM	3
+
+/*
+ * BAT's
+ */
+#define CONFIG_HIGH_BATS
+
+/* DDR @ 0x00000000 */
+#define CONFIG_SYS_IBAT0L		(CONFIG_SYS_SDRAM_BASE |\
+					 BATL_PP_10)
+#define CONFIG_SYS_IBAT0U		(CONFIG_SYS_SDRAM_BASE |\
+					 BATU_BL_256M |\
+					 BATU_VS |\
+					 BATU_VP)
+#define CONFIG_SYS_DBAT0L		CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U		CONFIG_SYS_IBAT0U
+
+/* Initial RAM @ 0xFD000000 */
+#define CONFIG_SYS_IBAT1L		(CONFIG_SYS_INIT_RAM_ADDR |\
+					 BATL_PP_10 |\
+					 BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT1U		(CONFIG_SYS_INIT_RAM_ADDR |\
+					 BATU_BL_256K |\
+					 BATU_VS |\
+					 BATU_VP)
+#define CONFIG_SYS_DBAT1L		CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U		CONFIG_SYS_IBAT1U
+
+/* FLASH @ 0xFF800000 */
+#define CONFIG_SYS_IBAT2L		(CONFIG_SYS_FLASH_BASE |\
+					 BATL_PP_10 |\
+					 BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT2U		(CONFIG_SYS_FLASH_BASE |\
+					 BATU_BL_8M |\
+					 BATU_VS |\
+					 BATU_VP)
+#define CONFIG_SYS_DBAT2L		(CONFIG_SYS_FLASH_BASE |\
+					 BATL_PP_10 |\
+					 BATL_CACHEINHIBIT |\
+					 BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U		CONFIG_SYS_IBAT2U
+
+#define CONFIG_SYS_IBAT3L		(0)
+#define CONFIG_SYS_IBAT3U		(0)
+#define CONFIG_SYS_DBAT3L		CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U		CONFIG_SYS_IBAT3U
+
+#define CONFIG_SYS_IBAT4L		(0)
+#define CONFIG_SYS_IBAT4U		(0)
+#define CONFIG_SYS_DBAT4L		CONFIG_SYS_IBAT4L
+#define CONFIG_SYS_DBAT4U		CONFIG_SYS_IBAT4U
+
+/* IMMRBAR @ 0xF0000000 */
+#define CONFIG_SYS_IBAT5L		(CONFIG_SYS_IMMR |\
+					 BATL_PP_10 |\
+					 BATL_CACHEINHIBIT |\
+					 BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT5U		(CONFIG_SYS_IMMR |\
+					 BATU_BL_128M |\
+					 BATU_VS |\
+					 BATU_VP)
+#define CONFIG_SYS_DBAT5L		CONFIG_SYS_IBAT5L
+#define CONFIG_SYS_DBAT5U		CONFIG_SYS_IBAT5U
+
+/* NAND-Flash @ 0xE1000000, MRAM @ 0xE2000000, CPLD @ 0xE3000000 */
+#define CONFIG_SYS_IBAT6L		(0xE0000000 |\
+					 BATL_PP_10 |\
+					 BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT6U		(0xE0000000 |\
+					 BATU_BL_256M |\
+					 BATU_VS |\
+					 BATU_VP)
+#define CONFIG_SYS_DBAT6L		CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U		CONFIG_SYS_IBAT6U
+
+#define CONFIG_SYS_IBAT7L		(0)
+#define CONFIG_SYS_IBAT7U		(0)
+#define CONFIG_SYS_DBAT7L		CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U		CONFIG_SYS_IBAT7U
+
+/*
+ * U-Boot environment setup
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_DATE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_CMD_EDITENV
+#define CONFIG_CMD_JFFS2
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/*
+ * The reserved memory
+ */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(8 * 1024 * 1024)
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE \
+				+ CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SIZE		0x20000
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+
+#define CONFIG_NETDEV			eth1
+#define CONFIG_HOSTNAME		ids8313
+#define CONFIG_ROOTPATH		"/opt/eldk-4.2/ppc_6xx"
+#define CONFIG_BOOTFILE		"ids8313/uImage"
+#define CONFIG_UBOOTPATH		"ids8313/u-boot.bin"
+#define CONFIG_FDTFILE			"ids8313/ids8313.dtb"
+#define CONFIG_LOADADDR		0x400000
+#define CONFIG_CMD_ENV_FLAGS
+#define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo"
+
+#define CONFIG_BAUDRATE		115200
+
+/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ		(256 << 20)
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT		"=> "
+#define CONFIG_SYS_CBSIZE		1024
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE \
+					 + sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser	*/
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+
+#define CONFIG_SYS_MEMTEST_START	0x00001000
+#define CONFIG_SYS_MEMTEST_END		0x00C00000
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000
+#define CONFIG_MII
+#define CONFIG_LOADS_ECHO
+#define CONFIG_TIMESTAMP
+#define CONFIG_PREBOOT			"echo;" \
+					"echo Type \\\"run nfsboot\\\" " \
+					"to mount root filesystem over NFS;echo"
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND		"run boot_cramfs"
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE
+
+#define CONFIG_JFFS2_NAND
+#define CONFIG_JFFS2_DEV		"0"
+
+/* mtdparts command line support */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_FLASH_CFI_MTD
+#define CONFIG_MTD_DEVICE
+#define MTDIDS_DEFAULT		"nor0=ff800000.flash,nand0=e1000000.flash"
+#define MTDPARTS_DEFAULT	"mtdparts=ff800000.flash:7m(dum)," \
+					"768k(BOOT-BIN)," \
+					"128k(BOOT-ENV),128k(BOOT-REDENV);" \
+					"e1000000.flash:-(ubi)"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"netdev=" __stringify(CONFIG_NETDEV) "\0"			\
+	"ethprime=TSEC1\0"						\
+	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
+	"tftpflash=tftpboot ${loadaddr} ${uboot}; "			\
+		"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
+		" +${filesize}; "					\
+		"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
+		" +${filesize}; "					\
+		"cp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE)	\
+		" ${filesize}; "					\
+		"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
+		" +${filesize}; "					\
+		"cmp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE)	\
+		" ${filesize}\0"					\
+	"console=ttyS0\0"						\
+	"fdtaddr=0x780000\0"						\
+	"kernel_addr=ff800000\0"					\
+	"fdtfile=" __stringify(CONFIG_FDTFILE) "\0"			\
+	"setbootargs=setenv bootargs "					\
+		"root=${rootdev} rw console=${console},"		\
+			"${baudrate} ${othbootargs}\0"			\
+	"setipargs=setenv bootargs root=${rootdev} rw "			\
+			"nfsroot=${serverip}:${rootpath} "		\
+			"ip=${ipaddr}:${serverip}:${gatewayip}:"	\
+			"${netmask}:${hostname}:${netdev}:off "		\
+			"console=${console},${baudrate} ${othbootargs}\0" \
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
+	"mtdids=" MTDIDS_DEFAULT "\0"					\
+	"mtdparts=" MTDPARTS_DEFAULT "\0"				\
+	"\0"
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv rootdev /dev/nfs;"					\
+	"run setipargs;run addmtd;"					\
+	"tftp ${loadaddr} ${bootfile};"				\
+	"tftp ${fdtaddr} ${fdtfile};"					\
+	"fdt addr ${fdtaddr};"						\
+	"bootm ${loadaddr} - ${fdtaddr}"
+
+/* UBI Support */
+#define CONFIG_CMD_NAND_TRIMFFS
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define CONFIG_MTD_PARTITIONS
+
+/* bootcount support */
+#define CONFIG_BOOTCOUNT_LIMIT
+#define CONFIG_BOOTCOUNT_I2C
+#define CONFIG_BOOTCOUNT_ALEN	1
+#define CONFIG_SYS_BOOTCOUNT_ADDR	0x9
+
+#define CONFIG_VERSION_VARIABLE
+
+#define CONFIG_FIT
+#define CONFIG_FIT_SIGNATURE
+#define CONFIG_CMD_FDT
+#define CONFIG_CMD_HASH
+#define CONFIG_RSA
+#define CONFIG_SHA1
+#define CONFIG_SHA256
+#define CONFIG_OF_CONTROL
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/ima3-mx53.h b/qemu/roms/u-boot/include/configs/ima3-mx53.h
new file mode 100644
index 000000000..ad1614abb
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/ima3-mx53.h
@@ -0,0 +1,242 @@
+/*
+ * (C) Copyright 2012, Stefano Babic <sbabic@denx.de>
+ *
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the MX53-EVK Freescale board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* SOC type must be included before imx-regs.h */
+#define CONFIG_MX53
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#define CONFIG_OF_LIBFDT
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* Enable GPIOs */
+#define CONFIG_MXC_GPIO
+
+/* UART */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	UART4_BASE_ADDR
+
+/* MMC */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_ESDHC_NUM	1
+
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DOS_PARTITION
+
+/* Ethernet on FEC */
+#define CONFIG_NET_MULTI
+#define CONFIG_MII
+
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE			FEC_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR		0x01
+#define CONFIG_PHY_ADDR			CONFIG_FEC_MXC_PHYADDR
+#define CONFIG_RESET_PHY_R
+#define CONFIG_FEC_MXC_NO_ANEG
+#define CONFIG_ETHPRIME			"FEC0"
+
+/* SPI */
+#define CONFIG_HARD_SPI
+#define CONFIG_MXC_SPI
+#define CONFIG_DEFAULT_SPI_BUS		1
+#define CONFIG_DEFAULT_SPI_MODE		SPI_MODE_0
+
+/* SPI FLASH - not used for environment */
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
+#define CONFIG_SF_DEFAULT_SPEED		25000000
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+
+/* Command definition */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_GPIO
+
+#define CONFIG_BOOTDELAY	3
+
+#define CONFIG_LOADADDR		0x70800000	/* loadaddr env var */
+#define CONFIG_SYS_TEXT_BASE    0xf0001400 /* uboot in nor flash */
+
+#define CONFIG_ARP_TIMEOUT	200UL
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT		"IMA3 MX53 U-Boot > "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START       0x70000000
+#define CONFIG_SYS_MEMTEST_END         0x10000
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+#define CONFIG_CMDLINE_EDITING
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM_1		CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE	(1024 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR)
+#define CONFIG_SYS_INIT_RAM_SIZE	(IRAM_SIZE)
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define MTDIDS_DEFAULT		"nor0=f0000000.flash"
+
+/* FLASH and environment organization */
+
+#define CONFIG_SYS_FLASH_BASE		0xF0000000
+#define CONFIG_SYS_FLASH_CFI		/* Flash is CFI conformant */
+#define CONFIG_FLASH_CFI_DRIVER		/* Use the common driver */
+#define CONFIG_FLASH_CFI_MTD		/* with MTD support */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	1024
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+
+#define CONFIG_ENV_SIZE        (8 * 1024)
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + \
+				CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SECT_SIZE	0x20000
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
+					CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+
+/*
+ * Default environment and default scripts
+ * to update uboot and load kernel
+ */
+
+#define HOSTNAME ima3-mx53
+
+#define CONFIG_HOSTNAME ima3-mx53
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram0 rw\0"			\
+	"addip_sta=setenv bootargs ${bootargs} "			\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0"		\
+	"addip=if test -n ${ipdyn};then run addip_dyn;"			\
+		"else run addip_sta;fi\0"	\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
+	"addtty=setenv bootargs ${bootargs}"				\
+		" console=${console},${baudrate}\0"			\
+	"addmisc=setenv bootargs ${bootargs} ${misc}\0"			\
+	"console=ttymxc3\0"						\
+	"loadaddr=70800000\0"						\
+	"kernel_addr_r=70800000\0"					\
+	"ramdisk_addr_r=71000000\0"					\
+	"hostname=" __stringify(CONFIG_HOSTNAME) "\0"			\
+	"bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0"		\
+	"ramdisk_file=" __stringify(CONFIG_HOSTNAME) "/uRamdisk\0"	\
+	"mmcargs=setenv bootargs root=${mmcroot} "			\
+		"rootfstype=${mmcrootfstype}\0"				\
+	"mmcroot=/dev/mmcblk0p3 rw\0"					\
+	"mmcboot=echo Booting from mmc ...; "				\
+		"run mmcargs addip addtty addmtd addmisc mmcload;"	\
+		"bootm\0"						\
+	"mmcload=fatload mmc ${mmcdev}:${mmcpart} "			\
+		"${loadaddr} ${uimage}\0"				\
+	"mmcrootfstype=ext3 rootwait\0"					\
+	"flash_self=run ramargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"flash_nfs=run nfsargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr}\0"				\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
+		"run nfsargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr_r}\0"				\
+	"net_self_load=tftp ${ramdisk_addr_r} ${ramdisk_file};"		\
+		"tftp ${kernel_addr_r} ${bootfile}\0"			\
+	"net_self=if run net_self_load;then "				\
+		"run ramargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr_r} ${ramdisk_addr_r};"		\
+		"else echo Images not loades;fi\0"			\
+	"satargs=setenv bootargs root=/dev/sda1\0"			\
+	"satafile=boot/uImage\0"					\
+	"ssdboot=echo Booting from ssd ...; "				\
+		"run satargs addip addtty addmtd addmisc;"		\
+		"sata init;ext2load sata 0:1 ${kernel_addr_r} "		\
+		"${satafile};bootm\0"					\
+	"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.imx\0"		\
+	"uimage=uImage\0"						\
+	"load=tftp ${loadaddr} ${u-boot}\0"				\
+	"uboot_addr=0xf0001000\0"					\
+	"update=protect off 0xf0000000 +60000;"				\
+		"erase ${uboot_addr} +60000;"				\
+		"cp.b ${loadaddr} ${uboot_addr} ${filesize}\0"		\
+	"upd=if run load;then echo Updating u-boot;if run update;"	\
+		"then echo U-Boot updated;"				\
+			"else echo Error updating u-boot !;"		\
+			"echo Board without bootloader !!;"		\
+		"fi;"							\
+		"else echo U-Boot not downloaded..exiting;fi\0"		\
+	"bootcmd=run net_nfs\0"
+
+
+#define CONFIG_CMD_SATA
+#ifdef CONFIG_CMD_SATA
+	#define CONFIG_DWC_AHSATA
+	#define CONFIG_SYS_SATA_MAX_DEVICE      1
+	#define CONFIG_DWC_AHSATA_PORT_ID       0
+	#define CONFIG_DWC_AHSATA_BASE_ADDR     SATA_BASE_ADDR
+	#define CONFIG_LBA48
+	#define CONFIG_LIBATA
+#endif
+
+#endif				/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/imx27lite-common.h b/qemu/roms/u-boot/include/configs/imx27lite-common.h
new file mode 100644
index 000000000..9c25efe85
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/imx27lite-common.h
@@ -0,0 +1,225 @@
+/*
+ * Copyright (C) 2010 Heiko Schocher <hs@denx.de>
+ *
+ * based on:
+ * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __IMX27LITE_COMMON_CONFIG_H
+#define __IMX27LITE_COMMON_CONFIG_H
+
+/*
+ * SoC Configuration
+ */
+#define CONFIG_ARM926EJS			/* arm926ejs CPU core */
+#define CONFIG_MX27
+#define CONFIG_MX27_CLK32	32768		/* OSC32K frequency */
+
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_SYS_TEXT_BASE		0xc0000000
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+
+/*
+ * Lowlevel configuration
+ */
+#define SDRAM_ESDCFG_REGISTER_VAL(cas)	\
+		(ESDCFG_TRC(10) |	\
+		ESDCFG_TRCD(3) |	\
+		ESDCFG_TCAS(cas) |	\
+		ESDCFG_TRRD(1) |	\
+		ESDCFG_TRAS(5) |	\
+		ESDCFG_TWR |		\
+		ESDCFG_TMRD(2) |	\
+		ESDCFG_TRP(2) |		\
+		ESDCFG_TXP(3))
+
+#define SDRAM_ESDCTL_REGISTER_VAL	\
+		(ESDCTL_PRCT(0) |	\
+		 ESDCTL_BL |		\
+		 ESDCTL_PWDT(0) |	\
+		 ESDCTL_SREFR(3) |	\
+		 ESDCTL_DSIZ_32 |	\
+		 ESDCTL_COL10 |		\
+		 ESDCTL_ROW13 |		\
+		 ESDCTL_SDE)
+
+#define SDRAM_ALL_VAL		0xf00
+
+#define SDRAM_MODE_REGISTER_VAL	0x33	/* BL: 8, CAS: 3 */
+#define SDRAM_EXT_MODE_REGISTER_VAL	0x1000000
+
+#define MPCTL0_VAL	0x1ef15d5
+
+#define SPCTL0_VAL	0x043a1c09
+
+#define CSCR_VAL	0x33f08107
+
+#define PCDR0_VAL	0x120470c3
+#define PCDR1_VAL	0x03030303
+#define PCCR0_VAL	0xffffffff
+#define PCCR1_VAL	0xfffffffc
+
+#define AIPI1_PSR0_VAL	0x20040304
+#define AIPI1_PSR1_VAL	0xdffbfcfb
+#define AIPI2_PSR0_VAL	0x07ffc200
+#define AIPI2_PSR1_VAL	0xffffffff
+
+/*
+ * Memory Info
+ */
+/* malloc() len */
+#define CONFIG_SYS_MALLOC_LEN		(0x10000 + 512 * 1024)
+/* memtest start address */
+#define CONFIG_SYS_MEMTEST_START	0xA0000000
+#define CONFIG_SYS_MEMTEST_END		0xA1000000	/* 16MB RAM test */
+#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1		0xA0000000	/* DDR Start */
+#define PHYS_SDRAM_1_SIZE	0x08000000	/* DDR size 128MB */
+
+/*
+ * Serial Driver info
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	UART1_BASE
+#define CONFIG_CONS_INDEX	1		/* use UART0 for console */
+#define CONFIG_BAUDRATE		115200		/* Default baud rate */
+
+/*
+ * Flash & Environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+/* Use buffered writes (~10x faster) */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+/* Use hardware sector protection */
+#define CONFIG_SYS_FLASH_PROTECTION		1
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of flash banks */
+/* CS2 Base address */
+#define PHYS_FLASH_1			0xc0000000
+/* Flash Base for U-Boot */
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_MAX_FLASH_SECT	(PHYS_FLASH_SIZE / \
+		CONFIG_SYS_FLASH_SECT_SZ)
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		0x40000		/* Reserve 256KiB */
+#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+
+/*
+ * Ethernet
+ */
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_MXC_PHYADDR		0x1f
+#define CONFIG_MII
+
+/*
+ * MTD
+ */
+#define CONFIG_FLASH_CFI_MTD
+#define CONFIG_MTD_DEVICE
+
+/*
+ * NAND
+ */
+#define CONFIG_NAND_MXC
+#define CONFIG_MXC_NAND_REGS_BASE	0xd8000000
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0xd8000000
+#define CONFIG_JFFS2_NAND
+#define CONFIG_MXC_NAND_HWECC
+
+/*
+ * SD/MMC
+ */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MXC_MMC
+#define CONFIG_DOS_PARTITION
+
+/*
+ * GPIO
+ */
+#define CONFIG_MXC_GPIO
+
+/*
+ * MTD partitions
+ */
+#define CONFIG_CMD_MTDPARTS
+
+/*
+ * U-Boot general configuration
+ */
+#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size  */
+/* Print buffer sz */
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
+		sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+
+/*
+ * U-Boot commands
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_PING
+
+#define CONFIG_BOOTDELAY	5
+
+#define CONFIG_LOADADDR		0xa0800000	/* loadaddr env var */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs}"				\
+		" console=ttymxc0,${baudrate}\0"			\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
+	"addmisc=setenv bootargs ${bootargs}\0"				\
+	"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0"		\
+	"kernel_addr_r=a0800000\0"					\
+	"bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0"		\
+	"rootpath=/opt/eldk-4.2-arm/arm\0"				\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
+		"run nfsargs addip addtty addmtd addmisc;"		\
+		"bootm\0"						\
+	"bootcmd=run net_nfs\0"						\
+	"load=tftp ${loadaddr} ${u-boot}\0"				\
+	"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)	\
+		" +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
+		" +${filesize};cp.b ${fileaddr} "			\
+		__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"	\
+	"upd=run load update\0"						\
+	"mtdids=" MTDIDS_DEFAULT "\0"					\
+	"mtdparts=" MTDPARTS_DEFAULT "\0"				\
+
+/* additions for new relocation code, must be added to all boards */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
+					GENERATED_GBL_DATA_SIZE)
+#endif /* __IMX27LITE_COMMON_CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/imx27lite.h b/qemu/roms/u-boot/include/configs/imx27lite.h
new file mode 100644
index 000000000..c18c35ef5
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/imx27lite.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* include common defines/options for all imx27lite related boards */
+#include "imx27lite-common.h"
+/*
+ * SoC Configuration
+ */
+#define CONFIG_IMX27LITE
+#define CONFIG_HOSTNAME		imx27
+#define CONFIG_BOARDNAME	"LogicPD imx27lite\n"
+
+/*
+ * Flash & Environment
+ */
+#define CONFIG_SYS_FLASH_SECT_SZ	0x2000	/* 8KB sect size Intel Flash */
+#define CONFIG_ENV_OFFSET		(PHYS_FLASH_SIZE - 0x20000)
+#define PHYS_FLASH_SIZE			0x200000
+#define CONFIG_ENV_SECT_SIZE		0x10000		/* Env sector Size */
+
+/*
+ * SD/MMC
+ */
+#define CONFIG_MXC_MCI_REGS_BASE	0x10014000
+
+/*
+ * MTD partitions
+ */
+#define MTDIDS_DEFAULT		"nor0=physmap-flash.0,nand0=mxc_nand.0"
+#define MTDPARTS_DEFAULT			\
+	"mtdparts="				\
+		"physmap-flash.0:"		\
+			"256k(U-Boot),"		\
+			"1664k(user),"		\
+			"64k(env1),"		\
+			"64k(env2);"		\
+		"mxc_nand.0:"			\
+			"128k(IPL-SPL),"	\
+			"4m(kernel),"		\
+			"22m(rootfs),"		\
+			"-(userfs)"
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/imx31_litekit.h b/qemu/roms/u-boot/include/configs/imx31_litekit.h
new file mode 100644
index 000000000..8428d8449
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/imx31_litekit.h
@@ -0,0 +1,176 @@
+/*
+ * (C) Copyright 2004
+ * Texas Instruments.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Kshitij Gupta <kshitij@ti.com>
+ *
+ * Configuration settings for the LogicPD i.MX31 Litekit board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+
+ /* High Level Configuration Options */
+#define CONFIG_ARM1136		1    /* This is an arm1136 CPU core */
+#define CONFIG_MX31		1    /* in a mx31 */
+#define CONFIG_MX31_CLK32	32000
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_SYS_TEXT_BASE	0xa0000000
+
+#define CONFIG_MACH_TYPE	MACH_TYPE_MX31LITE
+
+/* Temporarily disabled */
+#if 0
+#define CONFIG_OF_LIBFDT		1
+#define CONFIG_FIT			1
+#define CONFIG_FIT_VERBOSE		1
+#endif
+
+#define CONFIG_CMDLINE_TAG		1    /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)
+
+/*
+ * Hardware drivers
+ */
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	UART1_BASE
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_HARD_SPI		1
+#define CONFIG_MXC_SPI		1
+#define CONFIG_DEFAULT_SPI_BUS	1
+#define CONFIG_DEFAULT_SPI_MODE	(SPI_MODE_0 | SPI_CS_HIGH)
+
+/* PMIC Controller */
+#define CONFIG_POWER
+#define CONFIG_POWER_SPI
+#define CONFIG_POWER_FSL
+#define CONFIG_FSL_PMIC_BUS	1
+#define CONFIG_FSL_PMIC_CS	0
+#define CONFIG_FSL_PMIC_CLK	1000000
+#define CONFIG_FSL_PMIC_MODE	(SPI_MODE_0 | SPI_CS_HIGH)
+#define CONFIG_FSL_PMIC_BITLEN	32
+#define CONFIG_RTC_MC13XXX
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		115200
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_NAND
+
+#define CONFIG_BOOTDELAY	3
+
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_IPADDR		192.168.23.168
+#define CONFIG_SERVERIP		192.168.23.2
+
+#define	CONFIG_EXTRA_ENV_SETTINGS											\
+	"bootargs_base=setenv bootargs console=ttySMX0,115200\0"							\
+	"bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0"	\
+	"bootcmd=run bootcmd_net\0"											\
+	"bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; tftpboot 0x80000000 uImage-mx31; bootm\0"		\
+	"prg_uboot=tftpboot 0x80000000 u-boot-imx31_litekit.bin; protect off all; erase 0xa00d0000 0xa01effff; cp.b 0x80000000 0xa00d0000 $(filesize)\0"
+
+
+#define CONFIG_SMC911X		1
+#define CONFIG_SMC911X_BASE	(CS4_BASE + 0x00020000)
+#define CONFIG_SMC911X_32_BIT	1
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_PROMPT		"uboot> "
+#define CONFIG_SYS_CBSIZE		256  /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS		16          /* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE  /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START	0  /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x10000
+
+#define CONFIG_SYS_LOAD_ADDR		0 /* default load address */
+
+#define CONFIG_CMDLINE_EDITING	1
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM_1		CSD0_BASE
+#define PHYS_SDRAM_1_SIZE	(128 * 1024 * 1024)
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE		IRAM_SIZE
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_FLASH_BASE		CS0_BASE
+#define CONFIG_SYS_MAX_FLASH_BANKS	1           /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	128	     /* max number of sectors on one chip */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */
+
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x001f0000)
+#define	CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_SECT_SIZE	(64 * 1024)
+#define CONFIG_ENV_SIZE		(64 * 1024)
+
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash memory is CFI compliant */
+#define CONFIG_FLASH_CFI_DRIVER	1	/* Use drivers/cfi_flash.c */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* Use buffered writes (~10x faster) */
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* Use hardware sector protection */
+
+/* timeout values are in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(100*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(100*CONFIG_SYS_HZ) /* Timeout for Flash Write */
+
+/*
+ * JFFS2 partitions
+ */
+#undef CONFIG_CMD_MTDPARTS
+#define CONFIG_JFFS2_DEV	"nor0"
+
+/*
+ * NAND flash
+ */
+#define CONFIG_NAND_MXC
+#define CONFIG_MXC_NAND_REGS_BASE	NFC_BASE_ADDR
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		NFC_BASE_ADDR
+#define CONFIG_MXC_NAND_HWECC
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/imx31_phycore.h b/qemu/roms/u-boot/include/configs/imx31_phycore.h
new file mode 100644
index 000000000..ffb67c2eb
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/imx31_phycore.h
@@ -0,0 +1,203 @@
+/*
+ * (C) Copyright 2004
+ * Texas Instruments.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Kshitij Gupta <kshitij@ti.com>
+ *
+ * Configuration settings for the phyCORE-i.MX31 board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+
+/* High Level Configuration Options */
+#define CONFIG_ARM1136			/* This is an arm1136 CPU core */
+#define CONFIG_MX31			/* in a mx31 */
+#define CONFIG_MX31_CLK32	32000
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 512 * 1024)
+
+/*
+ * Hardware drivers
+ */
+
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_CLK_OFFSET	I2C2_CLK_OFFSET
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART1_BASE
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		115200
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+
+#define CONFIG_BOOTDELAY	3
+
+#define MTDPARTS_DEFAULT	"mtdparts=physmap-flash.0:128k(uboot)ro," \
+					"1536k(kernel),-(root)"
+
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_IPADDR		192.168.23.168
+#define CONFIG_SERVERIP		192.168.23.2
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"bootargs_base=setenv bootargs console=ttySMX0,115200\0"	\
+	"bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs "	\
+		"ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0"	\
+	"bootargs_flash=setenv bootargs $(bootargs) "			\
+		"root=/dev/mtdblock2 rootfstype=jffs2\0"		\
+	"bootargs_mtd=setenv bootargs $(bootargs) $(mtdparts)\0"	\
+	"bootcmd=run bootcmd_net\0"					\
+	"bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs;"	\
+		"tftpboot 0x80000000 $(uimage);bootm\0"			\
+	"bootcmd_flash=run bootargs_base bootargs_mtd bootargs_flash;"	\
+		"bootm 0x80000000\0"					\
+	"unlock=yes\0"							\
+	"mtdparts=" MTDPARTS_DEFAULT "\0"				\
+	"prg_uboot=tftpboot 0x80000000 $(uboot);"			\
+		"protect off 0xa0000000 +0x20000;"			\
+		"erase 0xa0000000 +0x20000;"				\
+		"cp.b 0x80000000 0xa0000000 $(filesize)\0"		\
+	"prg_kernel=tftpboot 0x80000000 $(uimage);"			\
+		"erase 0xa0040000 +0x180000;"				\
+		"cp.b 0x80000000 0xa0040000 $(filesize)\0"		\
+	"prg_jffs2=tftpboot 0x80000000 $(jffs2);"			\
+		"erase 0xa01c0000 0xa1ffffff;"				\
+		"cp.b 0x80000000 0xa01c0000 $(filesize)\0"		\
+	"videomode=video=ctfb:x:240,y:320,depth:16,mode:0,"		\
+		"pclk:185925,le:9,ri:17,up:7,lo:10,hs:1,vs:1,"		\
+		"sync:1241513985,vmode:0\0"
+
+
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_BASE	0xa8000000
+#define CONFIG_SMC911X_32_BIT
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_PROMPT		"uboot> "
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		256
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					 sizeof(CONFIG_SYS_PROMPT) + 16)
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS		16
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START	0  /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x10000
+
+#define CONFIG_SYS_LOAD_ADDR		0 /* default load address */
+
+#define CONFIG_CMDLINE_EDITING
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM_1			0x80000000
+#define PHYS_SDRAM_1_SIZE		(128 * 1024 * 1024)
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_SYS_TEXT_BASE		0xA0000000
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+						GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_INIT_RAM_ADDR + \
+						CONFIG_SYS_GBL_DATA_OFFSET)
+
+/*
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_FLASH_BASE		0xa0000000
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max # of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	259	/* max # of sectors/chip */
+/* Monitor at beginning of flash */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_ENV_IS_IN_EEPROM
+#define CONFIG_ENV_OFFSET			0x00	/* env. starts here */
+#define CONFIG_ENV_SIZE				4096
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x52
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* 5 bits = 32 octets */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* 10 ms delay */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2	/* byte addr. lenght */
+
+/*
+ * CFI FLASH driver setup
+ */
+#define CONFIG_SYS_FLASH_CFI		/* Flash memory is CFI compliant */
+#define CONFIG_FLASH_CFI_DRIVER		/* Use drivers/mtd/cfi_flash.c */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffered writes (~10x faster) */
+#define CONFIG_SYS_FLASH_PROTECTION	/* Use hardware sector protection */
+
+/*
+ * Timeout for Flash Erase and Flash Write
+ * timeout values are in ticks
+ */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(100*CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(100*CONFIG_SYS_HZ)
+
+/*
+ * JFFS2 partitions
+ */
+#undef CONFIG_CMD_MTDPARTS
+#define CONFIG_JFFS2_DEV	"nor0"
+
+/* EET platform additions */
+#ifdef CONFIG_IMX31_PHYCORE_EET
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_HARD_SPI
+#define CONFIG_MXC_SPI
+#define CONFIG_CMD_SPI
+
+#define CONFIG_S6E63D6
+
+#define CONFIG_VIDEO
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_MX3
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_CMD_BMP
+#define CONFIG_BMP_16BPP
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/inka4x0.h b/qemu/roms/u-boot/include/configs/inka4x0.h
new file mode 100644
index 000000000..f321975c4
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/inka4x0.h
@@ -0,0 +1,419 @@
+/*
+ * (C) Copyright 2009
+ * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
+ *
+ * (C) Copyright 2003-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5200		1	/* This is an MPC5200 CPU	*/
+#define CONFIG_INKA4X0		1	/* INKA4x0 board		*/
+
+/*
+ * Valid values for CONFIG_SYS_TEXT_BASE are:
+ * 0xFFE00000	boot low
+ * 0x00100000	boot from RAM (for testing only)
+ */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xFFE00000	/* Standard: boot low */
+#endif
+#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds"
+
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz		*/
+
+#define CONFIG_MISC_INIT_F	1	/* Use misc_init_f()			*/
+
+#define CONFIG_HIGH_BATS	1	/* High BATs supported			*/
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1	*/
+#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps	*/
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*
+ * PCI Mapping:
+ * 0x40000000 - 0x4fffffff - PCI Memory
+ * 0x50000000 - 0x50ffffff - PCI IO Space
+ */
+#define CONFIG_PCI		1
+#define CONFIG_PCI_PNP		1
+#define CONFIG_PCI_SCAN_SHOW	1
+#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1
+
+#define CONFIG_PCI_MEM_BUS	0x40000000
+#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE	0x10000000
+
+#define CONFIG_PCI_IO_BUS	0x50000000
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0x01000000
+
+#define CONFIG_SYS_XLB_PIPELINING	1
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_USB
+
+#define	CONFIG_TIMESTAMP	1	/* Print image info with timestamp */
+
+#if (CONFIG_SYS_TEXT_BASE == 0xFFE00000)		/* Boot low */
+#   define CONFIG_SYS_LOWBOOT		1
+#endif
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	1	/* autoboot after 1 second */
+
+#define CONFIG_PREBOOT	"echo;" \
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_ETHADDR		00:a0:a4:03:00:00
+#define	CONFIG_OVERWRITE_ETHADDR_ONCE
+
+#define	CONFIG_IPADDR		192.168.100.2
+#define	CONFIG_SERVERIP		192.168.100.1
+#define	CONFIG_NETMASK		255.255.255.0
+#define HOSTNAME		inka4x0
+#define CONFIG_BOOTFILE		"/tftpboot/inka4x0/uImage"
+#define	CONFIG_ROOTPATH		"/opt/eldk/ppc_6xx"
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addcons=setenv bootargs ${bootargs} "				\
+		"console=ttyS0,${baudrate}\0"				\
+	"flash_nfs=run nfsargs addip addcons;"				\
+		"bootm ${kernel_addr}\0"				\
+	"net_nfs=tftp 200000 ${bootfile};"				\
+		"run nfsargs addip addcons;bootm\0"			\
+	"enable_disp=mw.l 100000 04000000 1;"				\
+		"cp.l 100000 f0000b20 1;"				\
+		"cp.l 100000 f0000b28 1\0"				\
+	"ideargs=setenv bootargs root=/dev/hda1 rw\0"			\
+	"ide_boot=ext2load ide 0:1 200000 uImage;"			\
+		"run ideargs addip addcons enable_disp;bootm\0"		\
+	"brightness=255\0"						\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run ide_boot"
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
+
+/*
+ * Flash configuration
+ */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_FLASH_CFI_DRIVER	1
+#define CONFIG_SYS_FLASH_BASE		0xffe00000
+#define CONFIG_SYS_FLASH_SIZE		0x00200000
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster) */
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x4000)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x2000
+#define CONFIG_ENV_OVERWRITE	1
+#define CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+
+/*
+ * Memory map
+ */
+#define CONFIG_SYS_MBAR		0xF0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
+
+/*
+ * SDRAM controller configuration
+ */
+#undef CONFIG_SDR_MT48LC16M16A2
+#undef CONFIG_DDR_MT46V16M16
+#undef CONFIG_DDR_MT46V32M16
+#undef CONFIG_DDR_HYB25D512160BF
+#define CONFIG_DDR_K4H511638C
+
+/* Use ON-Chip SRAM until RAM will be available */
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+
+/* preserve space for the post_word at end of on-chip SRAM */
+#define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)
+
+#ifdef CONFIG_POST
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_POST_SIZE
+#else
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
+#endif
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC	1
+#define CONFIG_MPC5xxx_FEC_MII100
+/*
+ * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
+ */
+/* #define CONFIG_MPC5xxx_FEC_MII10 */
+#define CONFIG_PHY_ADDR		0x00
+#define CONFIG_MII
+
+/*
+ * GPIO configuration
+ *
+ * use CS1 as gpio_wkup_6 output
+ *	Bit 0 (mask: 0x80000000): 0
+ * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
+ *	00 -> No Alternatives, I2C1 is used for onboard EEPROM
+ *	01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard
+ *	      EEPROM
+ * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
+ * use PSC2 as UART: Bits 24-27 (mask: 0x00000070): 0100
+ * use PSC3 as UART: Bits 20-23 (mask: 0x00000700): 0100
+ * use PSC6 as UART: Bits  9-11 (mask: 0x00700000): 0101
+ */
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x01501444
+
+/*
+ * RTC configuration
+ */
+#define CONFIG_RTC_RTC4543 	1	/* use external RTC */
+
+/*
+ * Software (bit-bang) three wire serial configuration
+ *
+ * Note that we need the ifdefs because otherwise compilation of
+ * mkimage.c fails.
+ */
+#define CONFIG_SOFT_TWS		1
+
+#ifdef TWS_IMPLEMENTATION
+#include <mpc5xxx.h>
+#include <asm/io.h>
+
+#define TWS_CE		MPC5XXX_GPIO_WKUP_PSC1_4 /* GPIO_WKUP_0 */
+#define TWS_WR		MPC5XXX_GPIO_WKUP_PSC2_4 /* GPIO_WKUP_1 */
+#define TWS_DATA	MPC5XXX_GPIO_SINT_PSC3_4 /* GPIO_SINT_0 */
+#define TWS_CLK		MPC5XXX_GPIO_SINT_PSC3_5 /* GPIO_SINT_1 */
+
+static inline void tws_ce(unsigned bit)
+{
+	struct mpc5xxx_wu_gpio *wu_gpio =
+		(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
+	if (bit)
+		setbits_8(&wu_gpio->dvo, TWS_CE);
+	else
+		clrbits_8(&wu_gpio->dvo, TWS_CE);
+}
+
+static inline void tws_wr(unsigned bit)
+{
+	struct mpc5xxx_wu_gpio *wu_gpio =
+		(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
+	if (bit)
+		setbits_8(&wu_gpio->dvo, TWS_WR);
+	else
+		clrbits_8(&wu_gpio->dvo, TWS_WR);
+}
+
+static inline void tws_clk(unsigned bit)
+{
+	struct mpc5xxx_gpio *gpio =
+		(struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+	if (bit)
+		setbits_8(&gpio->sint_dvo, TWS_CLK);
+	else
+		clrbits_8(&gpio->sint_dvo, TWS_CLK);
+}
+
+static inline void tws_data(unsigned bit)
+{
+	struct mpc5xxx_gpio *gpio =
+		(struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+	if (bit)
+		setbits_8(&gpio->sint_dvo, TWS_DATA);
+	else
+		clrbits_8(&gpio->sint_dvo, TWS_DATA);
+}
+
+static inline unsigned tws_data_read(void)
+{
+	struct mpc5xxx_gpio *gpio =
+			(struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+	return !!(in_8(&gpio->sint_ival) & TWS_DATA);
+}
+
+static inline void tws_data_config_output(unsigned output)
+{
+	struct mpc5xxx_gpio *gpio =
+		(struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+	if (output)
+		setbits_8(&gpio->sint_ddr, TWS_DATA);
+	else
+		clrbits_8(&gpio->sint_ddr, TWS_DATA);
+}
+#endif /* TWS_IMPLEMENTATION */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs			*/
+#if defined(CONFIG_CMD_KGDB)
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/* Enable an alternate, more extensive memory test */
+#define CONFIG_SYS_ALT_MEMTEST
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
+
+/*
+ * Enable loopw command.
+ */
+#define CONFIG_LOOPW
+
+/*
+ * Various low-level settings
+ */
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
+
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_CFG		0x00087800 /* for pci_clk  = 66 MHz */
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
+
+/* 32Mbit SRAM @0x30000000 */
+#define CONFIG_SYS_CS1_START		0x30000000
+#define CONFIG_SYS_CS1_SIZE		0x00400000
+#define CONFIG_SYS_CS1_CFG		0x31800 /* for pci_clk = 33 MHz */
+
+/* 2 quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
+#define CONFIG_SYS_CS2_START		0x80000000
+#define CONFIG_SYS_CS2_SIZE		0x0001000
+#define CONFIG_SYS_CS2_CFG		0x21800  /* for pci_clk = 33 MHz */
+
+/* GPIO in @0x30400000 */
+#define CONFIG_SYS_CS3_START		0x30400000
+#define CONFIG_SYS_CS3_SIZE		0x00100000
+#define CONFIG_SYS_CS3_CFG		0x31800 /* for pci_clk = 33 MHz */
+
+#define CONFIG_SYS_CS_BURST		0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE	0x33333333
+
+/*-----------------------------------------------------------------------
+ * USB stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_USB_OHCI
+#define CONFIG_USB_CLOCK	0x00015555
+#define CONFIG_USB_CONFIG	0x00001000
+#define CONFIG_USB_STORAGE
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+
+#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+
+#define CONFIG_IDE_PREINIT
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	2	/* max. 1 drive per IDE bus	*/
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0060	/* Offset for data I/O		*/
+#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) /* Offset for normal register accesses */
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x005C	/* Offset for alternate registers */
+#define CONFIG_SYS_ATA_STRIDE          4	/* Interval between registers	*/
+
+#define CONFIG_ATAPI            1
+
+#define CONFIG_SYS_BRIGHTNESS          0xFF	/* LCD Default Brightness (255 = off) */
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/integrator-common.h b/qemu/roms/u-boot/include/configs/integrator-common.h
new file mode 100644
index 000000000..267a92b2d
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/integrator-common.h
@@ -0,0 +1,87 @@
+/*
+ * (C) Copyright 2012
+ * Linaro
+ * Linus Walleij <linus.walleij@linaro.org>
+ * Common ARM Integrator configuration settings
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#define CONFIG_INTEGRATOR
+
+#define CONFIG_SYS_TEXT_BASE		0x01000000
+#define CONFIG_SYS_MEMTEST_START	0x100000
+#define CONFIG_SYS_MEMTEST_END		0x10000000
+#define CONFIG_SYS_TIMERBASE		0x13000100	/* Timer1 */
+#define CONFIG_SYS_LOAD_ADDR		0x7fc0	/* default load address */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size*/
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size*/
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024) /* Size of malloc() pool */
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs  */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_OF_LIBFDT		/* enable passing a Device Tree */
+#define CONFIG_MISC_INIT_R		/* call misc_init_r during start up */
+
+/*
+ * There are various dependencies on the core module (CM) fitted
+ * Users should refer to their CM user guide
+ */
+#include "armcoremodule.h"
+
+/*
+ * Initialize and remap the core module, use SPD to detect memory size
+ * If CONFIG_SKIP_LOWLEVEL_INIT is not defined &
+ * the core module has a CM_INIT register
+ * then the U-Boot initialisation code will
+ * e.g. ARM Boot Monitor or pre-loader is repeated once
+ * (to re-initialise any existing CM_INIT settings to safe values).
+ *
+ * This is usually not the desired behaviour since the platform
+ * will either reboot into the ARM monitor (or pre-loader)
+ * or continuously cycle thru it without U-Boot running,
+ * depending upon the setting of Integrator/CP switch S2-4.
+ *
+ * However it may be needed if Integrator/CP switch S2-1
+ * is set OFF to boot direct into U-Boot.
+ * In that case comment out the line below.
+ */
+#define CONFIG_CM_INIT
+#define CONFIG_CM_REMAP
+#define CONFIG_CM_SPD_DETECT
+
+/*
+ * The ARM boot monitor initializes the board.
+ * However, the default U-Boot code also performs the initialization.
+ * If desired, this can be prevented by defining SKIP_LOWLEVEL_INIT
+ * - see documentation supplied with board for details of how to choose the
+ * image to run at reset/power up
+ * e.g. whether the ARM Boot Monitor runs before U-Boot
+ */
+/* #define CONFIG_SKIP_LOWLEVEL_INIT */
+
+/*
+ * The ARM boot monitor does not relocate U-Boot.
+ * However, the default U-Boot code performs the relocation check,
+ * and may relocate the code if the memory map is changed.
+ * If necessary this can be prevented by defining SKIP_RELOCATE_UBOOT
+ */
+/* #define SKIP_CONFIG_RELOCATE_UBOOT */
+
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1		0x00000000	/* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x08000000	/* 128 MB */
+#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_SIZE PHYS_SDRAM_1_SIZE
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \
+				    CONFIG_SYS_INIT_RAM_SIZE - \
+				    GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET
diff --git a/qemu/roms/u-boot/include/configs/integratorap.h b/qemu/roms/u-boot/include/configs/integratorap.h
new file mode 100644
index 000000000..edea769a9
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/integratorap.h
@@ -0,0 +1,97 @@
+/*
+ * (C) Copyright 2003
+ * Texas Instruments.
+ * Kshitij Gupta <kshitij@ti.com>
+ * Configuation settings for the TI OMAP Innovator board.
+ *
+ * (C) Copyright 2004
+ * ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ * Configuration for Integrator AP board.
+ *.
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "integrator-common.h"
+
+/* Integrator/AP-specific configuration */
+#define CONFIG_ARCH_INTEGRATOR
+#define CONFIG_SYS_HZ_CLOCK		24000000	/* Timer 1 is clocked at 24Mhz */
+
+/*
+ * PL010 Configuration
+ */
+#define CONFIG_PL010_SERIAL
+#define CONFIG_CONS_INDEX	0
+#define CONFIG_BAUDRATE		38400
+#define CONFIG_PL01x_PORTS	{ (void *) (CONFIG_SYS_SERIAL0), (void *) (CONFIG_SYS_SERIAL1) }
+#define CONFIG_SYS_SERIAL0		0x16000000
+#define CONFIG_SYS_SERIAL1		0x17000000
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_BOOTDELAY	2
+#define CONFIG_BOOTARGS		"root=/dev/mtdblock0 console=ttyAM0 console=tty"
+#define CONFIG_BOOTCOMMAND	""
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_PROMPT	"Integrator-AP # "	/* Monitor Command Prompt   */
+
+#define CONFIG_SYS_FLASH_BASE	0x24000000
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_FLASH_CFI		1
+#define CONFIG_FLASH_CFI_DRIVER		1
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* max number of memory banks */
+/* timeout values are in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(2*CONFIG_SYS_HZ)	/* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(2*CONFIG_SYS_HZ)	/* Timeout for Flash Write */
+#define CONFIG_SYS_MAX_FLASH_SECT	128
+#define CONFIG_ENV_SIZE			32768
+
+
+/*-----------------------------------------------------------------------
+ * PCI definitions
+ */
+
+#define CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_PCI_PNP
+
+#define CONFIG_NET_MULTI
+#define CONFIG_TULIP
+#define CONFIG_EEPRO100
+#define CONFIG_SYS_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100	*/
+
+
+/*-----------------------------------------------------------------------
+ * There are various dependencies on the core module (CM) fitted
+ * Users should refer to their CM user guide
+ * - when porting adjust u-boot/Makefile accordingly
+ *   to define the necessary CONFIG_ s for the CM involved
+ * see e.g. integratorcp_CM926EJ-S_config
+ */
+#include "armcoremodule.h"
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/integratorcp.h b/qemu/roms/u-boot/include/configs/integratorcp.h
new file mode 100644
index 000000000..608719a7e
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/integratorcp.h
@@ -0,0 +1,109 @@
+/*
+ * (C) Copyright 2003
+ * Texas Instruments.
+ * Kshitij Gupta <kshitij@ti.com>
+ * Configuation settings for the TI OMAP Innovator board.
+ *
+ * (C) Copyright 2004
+ * ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ * Configuration for Compact Integrator board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "integrator-common.h"
+
+/* Integrator CP-specific configuration */
+#define CONFIG_ARCH_CINTEGRATOR
+#define CONFIG_SYS_HZ_CLOCK		1000000	/* Timer 1 is clocked at 1Mhz */
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_SMC91111
+#define CONFIG_SMC_USE_32_BIT
+#define CONFIG_SMC91111_BASE    0xC8000000
+#undef CONFIG_SMC91111_EXT_PHY
+
+/* PL011 configuration */
+#define CONFIG_PL011_SERIAL
+#define CONFIG_PL011_CLOCK	14745600
+#define CONFIG_PL01x_PORTS	{ (void *)CONFIG_SYS_SERIAL0, (void *)CONFIG_SYS_SERIAL1 }
+#define CONFIG_CONS_INDEX	0
+#define CONFIG_BAUDRATE		38400
+#define CONFIG_SYS_SERIAL0		0x16000000
+#define CONFIG_SYS_SERIAL1		0x17000000
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_BOOTDELAY	2
+#define CONFIG_BOOTARGS	"root=/dev/mtdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0"
+#define CONFIG_BOOTCOMMAND "tftpboot ; bootm"
+#define CONFIG_SERVERIP 192.168.1.100
+#define CONFIG_IPADDR 192.168.1.104
+#define CONFIG_BOOTFILE "uImage"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_PROMPT	"Integrator-CP # "	/* Monitor Command Prompt */
+
+/*
+ * FLASH and environment organization
+ * Top varies according to amount fitted
+ * Reserve top 4 blocks of flash
+ * - ARM Boot Monitor
+ * - Unused
+ * - SIB block
+ * - U-Boot environment
+ *
+ * Base is always 0x24000000
+ */
+#define CONFIG_SYS_FLASH_BASE		0x24000000
+#define CONFIG_SYS_FLASH_CFI		1
+#define CONFIG_FLASH_CFI_DRIVER		1
+#define CONFIG_SYS_MAX_FLASH_SECT	64
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* max number of memory banks */
+#define PHYS_FLASH_SIZE			0x01000000	/* 16MB */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(2*CONFIG_SYS_HZ)	/* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(2*CONFIG_SYS_HZ)	/* Timeout for Flash Write */
+
+#define CONFIG_SYS_MONITOR_LEN		0x00100000
+#define CONFIG_ENV_IS_IN_FLASH	1
+
+/*
+ * Move up the U-Boot & monitor area if more flash is fitted.
+ * If this U-Boot is to be run on Integrators with varying flash sizes,
+ * drivers/mtd/cfi_flash.c::flash_init() can read the Integrator CP_FLASHPROG
+ * register and dynamically assign CONFIG_ENV_ADDR & CONFIG_SYS_MONITOR_BASE
+ * - CONFIG_SYS_MONITOR_BASE is set to indicate that the environment is not
+ * embedded in the boot monitor(s) area
+ */
+#if ( PHYS_FLASH_SIZE == 0x04000000 )
+
+#define CONFIG_ENV_ADDR		0x27F00000
+#define CONFIG_SYS_MONITOR_BASE	0x27F40000
+
+#elif (PHYS_FLASH_SIZE == 0x02000000 )
+
+#define CONFIG_ENV_ADDR		0x25F00000
+#define CONFIG_SYS_MONITOR_BASE	0x25F40000
+
+#else
+
+#define CONFIG_ENV_ADDR		0x24F00000
+#define CONFIG_SYS_MONITOR_BASE	0x27F40000
+
+#endif
+
+#define CONFIG_ENV_SECT_SIZE	0x40000		/* 256KB */
+#define CONFIG_ENV_SIZE		8192		/* 8KB */
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/intip.h b/qemu/roms/u-boot/include/configs/intip.h
new file mode 100644
index 000000000..b56b3aa34
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/intip.h
@@ -0,0 +1,430 @@
+/*
+ * (C) Copyright 2009
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * Based on include/configs/canyonlands.h
+ * (C) Copyright 2008
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * intip.h - configuration for CompactCenter aka intip (460EX) and DevCon-Center
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+/*
+ * This config file is used for CompactCenter(codename intip) and DevCon-Center
+ */
+#define CONFIG_460EX		1	/* Specific PPC460EX		*/
+#ifdef CONFIG_DEVCONCENTER
+#define CONFIG_HOSTNAME		devconcenter
+#define CONFIG_IDENT_STRING	" devconcenter 0.06"
+#else
+#define CONFIG_HOSTNAME		intip
+#define CONFIG_IDENT_STRING	" intip 0.06"
+#endif
+#define CONFIG_440		1
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xFFFA0000
+#endif
+
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#include "amcc-common.h"
+
+#define CONFIG_SYS_CLK_FREQ	66666667	/* external freq to pll	*/
+
+#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_early_init_f */
+#define CONFIG_BOARD_EARLY_INIT_R	1	/* Call board_early_init_r */
+#define CONFIG_MISC_INIT_R		1	/* Call misc_init_r */
+#define CONFIG_BOARD_TYPES		1	/* support board types */
+#define CONFIG_FIT
+#define CFG_ALT_MEMTEST
+
+#undef CONFIG_ZERO_BOOTDELAY_CHECK     /* ignore keypress on bootdelay==0 */
+#define CONFIG_AUTOBOOT_KEYED          /* use key strings to stop autoboot */
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped PCI memory */
+#define CONFIG_SYS_PCI_BASE		0xd0000000	/* internal PCI regs */
+#define CONFIG_SYS_PCI_TARGBASE	CONFIG_SYS_PCI_MEMBASE
+
+/* EBC stuff */
+#ifdef CONFIG_DEVCONCENTER               /* Devcon-Center has 128 MB of flash */
+#define CONFIG_SYS_FLASH_BASE		0xF8000000	/* later mapped here */
+#define CONFIG_SYS_FLASH_SIZE		(128 << 20)
+#else
+#define CONFIG_SYS_FLASH_BASE		0xFC000000	/* later mapped here */
+#define CONFIG_SYS_FLASH_SIZE		(64 << 20)
+#endif
+
+#define CONFIG_SYS_NVRAM_BASE		0xE0000000
+#define CONFIG_SYS_UART_BASE		0xE0100000
+#define CONFIG_SYS_IO_BASE		0xE0200000
+
+#define CONFIG_SYS_BOOT_BASE_ADDR	0xFF000000	/* EBC Boot Space */
+#define CONFIG_SYS_FLASH_BASE_PHYS_H	0x4
+#ifdef CONFIG_DEVCONCENTER               /* Devcon-Center has 128 MB of flash */
+#define CONFIG_SYS_FLASH_BASE_PHYS_L	0xC8000000
+#else
+#define CONFIG_SYS_FLASH_BASE_PHYS_L	0xCC000000
+#endif
+#define CONFIG_SYS_FLASH_BASE_PHYS \
+	(((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) \
+	| (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
+
+#define CONFIG_SYS_OCM_BASE		0xE3000000	/* OCM: 64k */
+#define CONFIG_SYS_SRAM_BASE		0xE8000000	/* SRAM: 256k */
+#define CONFIG_SYS_SRAM_SIZE		(256 << 10)
+#define CONFIG_SYS_LOCAL_CONF_REGS	0xEF000000
+
+#define CONFIG_SYS_AHB_BASE		0xE2000000	/* int. AHB periph. */
+
+/*
+ * Initial RAM & stack pointer (placed in OCM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_BASE	/* OCM */
+#define CONFIG_SYS_INIT_RAM_SIZE	(4 << 10)
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+
+/*
+ * Environment
+ */
+/*
+ * Define here the location of the environment variables (FLASH).
+ */
+#define	CONFIG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars */
+#define CONFIG_SYS_NOR_CS		0	/* NOR chip connected to CSx */
+
+/*
+ * FLASH related
+ */
+#define CONFIG_SYS_FLASH_CFI		/* The flash is CFI compatible	*/
+#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
+#define CONFIG_SYS_FLASH_CFI_AMD_RESET	1	/* Use AMD reset cmd */
+
+#define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks */
+#ifdef CONFIG_DEVCONCENTER
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* max num of sectors per chip*/
+#else
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sectors per chip*/
+#endif
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase/ms */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write/ms */
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* buff'd writes (20x faster) */
+#define CONFIG_SYS_FLASH_EMPTY_INFO	/* 'E' for empty sector on flinfo */
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	0x20000		/* size of one complete sector*/
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+#endif /* CONFIG_ENV_IS_IN_FLASH */
+
+/*
+ * DDR SDRAM
+ */
+
+#define CONFIG_AUTOCALIB	"silent\0"	/* default is non-verbose    */
+
+#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION	/* IBM DDR autocalibration   */
+#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION	/* dynamic DDR autocal debug */
+#undef CONFIG_PPC4xx_DDR_METHOD_A
+
+/* DDR1/2 SDRAM Device Control Register Data Values */
+/* Memory Queue */
+#define CONFIG_SYS_SDRAM_R0BAS		0x0000f800
+#define CONFIG_SYS_SDRAM_R1BAS		0x00000000
+#define CONFIG_SYS_SDRAM_R2BAS		0x00000000
+#define CONFIG_SYS_SDRAM_R3BAS		0x00000000
+#define CONFIG_SYS_SDRAM_PLBADDULL	0x00000000
+#define CONFIG_SYS_SDRAM_PLBADDUHB	0x00000008
+#define CONFIG_SYS_SDRAM_CONF1LL	0x80001C00
+#define CONFIG_SYS_SDRAM_CONF1HB	0x80001C80
+#define CONFIG_SYS_SDRAM_CONFPATHB	0x10a68000
+
+/* SDRAM Controller */
+#define CONFIG_SYS_SDRAM0_MB0CF		0x00000201
+#define CONFIG_SYS_SDRAM0_MB1CF		0x00000000
+#define CONFIG_SYS_SDRAM0_MB2CF		0x00000000
+#define CONFIG_SYS_SDRAM0_MB3CF		0x00000000
+#define CONFIG_SYS_SDRAM0_MCOPT1	0x05120000
+#define CONFIG_SYS_SDRAM0_MCOPT2	0x00000000
+#define CONFIG_SYS_SDRAM0_MODT0		0x00000000
+#define CONFIG_SYS_SDRAM0_MODT1		0x00000000
+#define CONFIG_SYS_SDRAM0_MODT2		0x00000000
+#define CONFIG_SYS_SDRAM0_MODT3		0x00000000
+#define CONFIG_SYS_SDRAM0_CODT		0x00000020
+#define CONFIG_SYS_SDRAM0_RTR		0x06180000
+#define CONFIG_SYS_SDRAM0_INITPLR0	0xA8380000
+#define CONFIG_SYS_SDRAM0_INITPLR1	0x81900400
+#define CONFIG_SYS_SDRAM0_INITPLR2	0x81020000
+#define CONFIG_SYS_SDRAM0_INITPLR3	0x81030000
+#define CONFIG_SYS_SDRAM0_INITPLR4	0x81010002
+#define CONFIG_SYS_SDRAM0_INITPLR5	0xE4000552
+#define CONFIG_SYS_SDRAM0_INITPLR6	0x81900400
+#define CONFIG_SYS_SDRAM0_INITPLR7	0x8A880000
+#define CONFIG_SYS_SDRAM0_INITPLR8	0x8A880000
+#define CONFIG_SYS_SDRAM0_INITPLR9	0x8A880000
+#define CONFIG_SYS_SDRAM0_INITPLR10	0x8A880000
+#define CONFIG_SYS_SDRAM0_INITPLR11	0x81000452
+#define CONFIG_SYS_SDRAM0_INITPLR12	0x81010382
+#define CONFIG_SYS_SDRAM0_INITPLR13	0x81010002
+#define CONFIG_SYS_SDRAM0_INITPLR14	0x00000000
+#define CONFIG_SYS_SDRAM0_INITPLR15	0x00000000
+#define CONFIG_SYS_SDRAM0_RQDC		0x80000038
+#define CONFIG_SYS_SDRAM0_RFDC		0x00000257
+#define CONFIG_SYS_SDRAM0_RDCC		0x40000000
+#define CONFIG_SYS_SDRAM0_DLCR		0x00000000
+#define CONFIG_SYS_SDRAM0_CLKTR		0x40000000
+#define CONFIG_SYS_SDRAM0_WRDTR		0x86000823
+#define CONFIG_SYS_SDRAM0_SDTR1		0x80201000
+#define CONFIG_SYS_SDRAM0_SDTR2		0x32204232
+#define CONFIG_SYS_SDRAM0_SDTR3		0x090C0D15
+#define CONFIG_SYS_SDRAM0_MMODE		0x00000452
+#define CONFIG_SYS_SDRAM0_MEMODE	0x00000002
+
+#define CONFIG_SYS_MBYTES_SDRAM	256	/* 256MB */
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
+
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR		(0xa8>>1)
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
+
+/* I2C bootstrap EEPROM */
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR	0x54
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET	0
+#define CONFIG_4xx_CONFIG_BLOCKSIZE		16
+
+/* I2C SYSMON */
+#define CONFIG_DTT_LM63         1       /* National LM63        */
+#define CONFIG_DTT_SENSORS      { 0 }   /* Sensor addresses     */
+#define CONFIG_DTT_PWM_LOOKUPTABLE      \
+	{ { 40, 10 }, { 50, 20 }, { 60, 40 } }
+#define CONFIG_DTT_TACH_LIMIT   0xa10
+
+/* RTC configuration */
+#define CONFIG_RTC_DS1337	1
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68
+
+/*
+ * Ethernet
+ */
+#define CONFIG_IBM_EMAC4_V4	1
+
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+
+#define CONFIG_PHY_ADDR		2	/* PHY address, See schematics	*/
+#define CONFIG_PHY1_ADDR	3
+
+#define CONFIG_PHY_RESET	1	/* reset phy upon startup	*/
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+#define CONFIG_PHY_DYNAMIC_ANEG	1
+
+/*
+ * USB-OHCI
+ */
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_USB_STORAGE
+#undef CONFIG_SYS_OHCI_BE_CONTROLLER	/* 460EX has little endian descriptors*/
+#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS	/* 460EX has little endian register */
+#define CONFIG_SYS_OHCI_USE_NPS		/* force NoPowerSwitching mode */
+#define CONFIG_SYS_USB_OHCI_REGS_BASE	(CONFIG_SYS_AHB_BASE | 0xd0000)
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"ppc440"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_AMCC_DEF_ENV						\
+	CONFIG_AMCC_DEF_ENV_POWERPC					\
+	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
+	"kernel_addr=fc000000\0"					\
+	"fdt_addr=fc1e0000\0"						\
+	"ramdisk_addr=fc200000\0"					\
+	"pciconfighost=1\0"						\
+	"pcie_mode=RP:RP\0"						\
+	""
+
+/*
+ * Commands additional to the ones defined in amcc-common.h
+ */
+#define CONFIG_CMD_CHIP_CONFIG
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_USB
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+/*
+ * PCI stuff
+ */
+/* General PCI */
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play   */
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup  */
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE
+#define CONFIG_PCI_DISABLE_PCIE
+
+/* Board-specific PCI */
+#define CONFIG_SYS_PCI_TARGET_INIT	/* let board init pci target */
+#undef	CONFIG_SYS_PCI_MASTER_INIT
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014	/* IBM */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
+
+
+/*
+ * External Bus Controller (EBC) Setup
+ */
+
+/*
+ * CompactCenter has 64MBytes of NOR FLASH (Spansion 29GL512), but the
+ * boot EBC mapping only supports a maximum of 16MBytes
+ * (4.ff00.0000 - 4.ffff.ffff).
+ * To solve this problem, the FLASH has to get remapped to another
+ * EBC address which accepts bigger regions:
+ *
+ * 0xfc00.0000 -> 4.cc00.0000
+ */
+
+
+/* Memory Bank 0 (NOR-FLASH) initialization */
+#define CONFIG_SYS_EBC_PB0AP		0x10055e00
+#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000)
+
+/* Memory Bank 1 (NVRAM) initialization	*/
+#define CONFIG_SYS_EBC_PB1AP		0x02815480
+/* BAS=NVRAM,BS=1MB,BU=R/W,BW=8bit*/
+#define CONFIG_SYS_EBC_PB1CR		(CONFIG_SYS_NVRAM_BASE | 0x18000)
+
+/* Memory Bank 2 (UART) initialization	*/
+#define CONFIG_SYS_EBC_PB2AP		0x02815480
+/* BAS=UART,BS=1MB,BU=R/W,BW=16bit*/
+#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_UART_BASE | 0x1A000)
+
+/* Memory Bank 3 (IO) initialization */
+#define CONFIG_SYS_EBC_PB3AP		0x02815480
+/* BAS=IO,BS=1MB,BU=R/W,BW=16bit*/
+#define CONFIG_SYS_EBC_PB3CR		(CONFIG_SYS_IO_BASE | 0x1A000)
+
+/*
+ * PPC4xx GPIO Configuration
+ */
+/* 460EX: Use USB configuration */
+#define CONFIG_SYS_4xx_GPIO_TABLE { /*	  Out		  GPIO	Alternate1	Alternate2	Alternate3 */ \
+{											\
+/* GPIO Core 0 */									\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0	GMC1TxD(0)	USB2HostD(0)	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1	GMC1TxD(1)	USB2HostD(1)	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2	GMC1TxD(2)	USB2HostD(2)	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO3	GMC1TxD(3)	USB2HostD(3)	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO4	GMC1TxD(4)	USB2HostD(4)	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO5	GMC1TxD(5)	USB2HostD(5)	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO6	GMC1TxD(6)	USB2HostD(6)	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO7	GMC1TxD(7)	USB2HostD(7)	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8	GMC1RxD(0)	USB2OTGD(0)	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9	GMC1RxD(1)	USB2OTGD(1)	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2)	USB2OTGD(2)	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3)	USB2OTGD(3)	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4)	USB2OTGD(4)	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5)	USB2OTGD(5)	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6)	USB2OTGD(6)	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7)	USB2OTGD(7)	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL,  GPIO_OUT_0}, /* GPIO16 GMC1TxER	USB2HostStop	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD		USB2HostNext	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER	USB2HostDir	*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO19 GMC1TxEN	USB2OTGStop	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS	USB2OTGNext	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV	USB2OTGDir	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0)				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1)				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2)				*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0	DMAReq2		IRQ(7)*/ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1	DMAAck2		IRQ(8)*/ \
+},											\
+{											\
+/* GPIO Core 1 */									\
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2	EOT2/TC2	IRQ(9)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3	DMAReq3		IRQ(4)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N	UART1_DSR_CTS_N	UART2_SOUT*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3	UART3_SIN*/ \
+{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N	EOT3/TC3	UART3_SOUT*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N	UART1_SOUT	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N	UART1_SIN	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3)				*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1)				*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2)				*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3)		DMAReq1		IRQ(10)*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4)		DMAAck1		IRQ(11)*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5)		EOT/TC1		IRQ(12)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5)	DMAReq0		IRQ(13)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6)	DMAAck0		IRQ(14)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7)	EOT/TC0		IRQ(15)*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50  USB_SERVICE_SUSPEND_N		*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO51  SPI_CSS_N			*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO52  FPGA_PROGRAM_UC_N		*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53  FPGA_INIT_UC_N		*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO54  WD_STROBE			*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55  LED_2_OUT			*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO56  LED_1_OUT			*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO61  STARTUP_FINISHED_N		*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO62  STARTUP_FINISHED		*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63  SERVICE_PORT_ACTIVE		*/	\
+}											\
+}
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/io.h b/qemu/roms/u-boot/include/configs/io.h
new file mode 100644
index 000000000..9da6cc685
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/io.h
@@ -0,0 +1,246 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_405EP		1	/* this is a PPC405 CPU */
+#define CONFIG_IO	        1	/*  on a Io board */
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
+
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME		io
+#define CONFIG_IDENT_STRING	" io 0.06"
+#include "amcc-common.h"
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_MISC_INIT_R
+#define CONFIG_LAST_STAGE_INIT
+
+#define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll   */
+
+/*
+ * Configure PLL
+ */
+#define PLLMR0_DEFAULT PLLMR0_266_133_66
+#define PLLMR1_DEFAULT PLLMR1_266_133_66
+
+#undef CONFIG_ZERO_BOOTDELAY_CHECK	/* ignore keypress on bootdelay==0 */
+#define CONFIG_AUTOBOOT_KEYED		/* use key strings to stop autoboot */
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
+
+#define CONFIG_ENV_IS_IN_FLASH	/* use FLASH for environment vars */
+
+/*
+ * Default environment variables
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_AMCC_DEF_ENV						\
+	CONFIG_AMCC_DEF_ENV_POWERPC					\
+	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
+	"kernel_addr=fc000000\0"					\
+	"fdt_addr=fc1e0000\0"						\
+	"ramdisk_addr=fc200000\0"					\
+	""
+
+#define CONFIG_PHY_ADDR		4	/* PHY address			*/
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_PHY1_ADDR	0xc	/* EMAC1 PHY address		*/
+#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ
+
+/*
+ * Commands additional to the ones defined in amcc-common.h
+ */
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DTT
+#undef CONFIG_CMD_EEPROM
+
+/*
+ * SDRAM configuration (please see cpu/ppc/sdram.[ch])
+ */
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0 */
+
+/* SDRAM timings used in datasheet */
+#define CONFIG_SYS_SDRAM_CL             3	/* CAS latency */
+#define CONFIG_SYS_SDRAM_tRP           20	/* PRECHARGE command period */
+#define CONFIG_SYS_SDRAM_tRC           66	/* ACTIVE-to-ACTIVE period */
+#define CONFIG_SYS_SDRAM_tRCD          20	/* ACTIVE-to-READ delay */
+#define CONFIG_SYS_SDRAM_tRFC          66	/* Auto refresh period */
+
+/*
+ * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
+ * The Linux BASE_BAUD define should match this configuration.
+ *    baseBaud = cpuClock/(uartDivisor*16)
+ * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * set Linux BASE_BAUD to 403200.
+ */
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#undef  CONFIG_SYS_EXT_SERIAL_CLOCK	/* external serial clock */
+#undef  CONFIG_SYS_405_UART_ERRATA_59	/* 405GP/CR Rev. D silicon */
+#define CONFIG_SYS_BASE_BAUD		691200
+
+/*
+ * I2C stuff
+ */
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		100000
+
+/* Temp sensor/hwmon/dtt */
+#define CONFIG_DTT_LM63		1	/* National LM63	*/
+#define CONFIG_DTT_SENSORS	{ 0 }	/* Sensor addresses	*/
+#define CONFIG_DTT_PWM_LOOKUPTABLE	\
+		{ { 40, 10 }, { 50, 20 }, { 60, 40 } }
+#define CONFIG_DTT_TACH_LIMIT	0xa10
+
+/*
+ * FLASH organization
+ */
+#define CONFIG_SYS_FLASH_CFI		/* The flash is CFI compatible	*/
+#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
+
+#define CONFIG_SYS_FLASH_BASE		0xFC000000
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sectors per chip*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase/ms */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write/ms */
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buff'd writes */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO	/* 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* no warn upon unknown flash */
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector */
+#define CONFIG_ENV_ADDR		((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
+#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+#endif
+
+/* Gbit PHYs */
+#define CONFIG_BITBANGMII		/* bit-bang MII PHY management */
+#define CONFIG_BITBANGMII_MULTI
+
+#define CONFIG_SYS_MDIO_PIN  (0x80000000 >> 13)	/* our MDIO is GPIO0 */
+#define CONFIG_SYS_MDC_PIN   (0x80000000 >> 7)	/* our MDC  is GPIO7 */
+
+#define CONFIG_SYS_GBIT_MII_BUSNAME	"io_miiphy"
+
+/*
+ * PPC405 GPIO Configuration
+ */
+#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO	Alternate1	*/ \
+{ \
+/* GPIO Core 0 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO0	PerBLast */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO1	TS1E */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO2	TS2E */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO3	TS1O */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO4	TS2O */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1      }, /* GPIO5	TS3 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO6	TS4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1      }, /* GPIO7	TS5 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO8	TS6 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO9	TrcClk */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10	PerCS1 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11	PerCS2 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12	PerCS3 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO13	PerCS4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14	PerAddr03 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15	PerAddr04 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16	PerAddr05 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17	IRQ0 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18	IRQ1 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19	IRQ2 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO20	IRQ3 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO21	IRQ4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO22	IRQ5 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO23	IRQ6 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24	UART0_DCD */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25	UART0_DSR */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26	UART0_RI */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27	UART0_DTR */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28	UART1_Rx */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29	UART1_Tx */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO30	RejectPkt0 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO31	RejectPkt1 */ \
+} \
+}
+
+/*
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory (OCM) for temperary stack until sdram is tested */
+#define CONFIG_SYS_TEMP_STACK_OCM        1
+
+/* On Chip Memory location */
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
+#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+	(CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (NOR-FLASH) initialization */
+#define CONFIG_SYS_EBC_PB0AP		0xa382a880
+/* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB0CR		0xFC0DA000
+
+/* Memory Bank 1 (NVRAM) initializatio */
+#define CONFIG_SYS_EBC_PB1AP		0x92015480
+/* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit  */
+#define CONFIG_SYS_EBC_PB1CR		0x7f318000
+
+/* Memory Bank 2 (FPGA) initialization */
+#define CONFIG_SYS_FPGA0_BASE		0x7f100000
+#define CONFIG_SYS_EBC_PB2AP		0x02025080
+/* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB2CR		0x7f11a000
+
+#define CONFIG_SYS_FPGA_BASE(k)		CONFIG_SYS_FPGA0_BASE
+#define CONFIG_SYS_FPGA_DONE(k)		0x0010
+
+#define CONFIG_SYS_FPGA_COUNT		1
+
+#define CONFIG_SYS_FPGA_PTR \
+	{ (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE }
+
+#define CONFIG_SYS_FPGA_COMMON
+
+/* Memory Bank 3 (Latches) initialization */
+#define CONFIG_SYS_LATCH_BASE		0x7f200000
+#define CONFIG_SYS_EBC_PB3AP		0xa2015480
+/* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */
+#define CONFIG_SYS_EBC_PB3CR		0x7f21a000
+
+#define CONFIG_SYS_LATCH0_RESET		0xffff
+#define CONFIG_SYS_LATCH0_BOOT		0xffff
+#define CONFIG_SYS_LATCH1_RESET		0xffbf
+#define CONFIG_SYS_LATCH1_BOOT		0xffff
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/io64.h b/qemu/roms/u-boot/include/configs/io64.h
new file mode 100644
index 000000000..6915b2071
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/io64.h
@@ -0,0 +1,555 @@
+/*
+ * (C) Copyright 2011
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * based on kilauea.h
+ * by Stefan Roese, DENX Software Engineering, sr@denx.de.
+ * and Grant Erickson <gerickson@nuovations.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/************************************************************************
+ * io64.h - configuration for Guntermann & Drunck Io64 (405EX)
+ ***********************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_IO64		1		/* Board is Io64 */
+#define CONFIG_405EX		1		/* Specifc 405EX support*/
+#define CONFIG_SYS_CLK_FREQ	33333333	/* ext frequency to pll */
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xFFFA0000
+#endif
+
+/*
+ * CHIP_21 errata
+ */
+#define CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY
+
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME		io64
+#define CONFIG_IDENT_STRING	" io64 0.02"
+#include "amcc-common.h"
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_MISC_INIT_R
+#define CONFIG_LAST_STAGE_INIT
+
+#undef CONFIG_ZERO_BOOTDELAY_CHECK	/* ignore keypress on bootdelay==0 */
+#define CONFIG_AUTOBOOT_KEYED		/* use key strings to stop autoboot */
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_FLASH_BASE		0xFC000000
+#define CONFIG_SYS_NVRAM_BASE		0xF0000000
+#define CONFIG_SYS_FPGA0_BASE		0xF0100000
+#define CONFIG_SYS_FPGA1_BASE		0xF0108000
+#define CONFIG_SYS_LATCH_BASE		0xF0200000
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & Stack Pointer Configuration Options
+ *
+ *   There are traditionally three options for the primordial
+ *   (i.e. initial) stack usage on the 405-series:
+ *
+ *      1) On-chip Memory (OCM) (i.e. SRAM)
+ *      2) Data cache
+ *      3) SDRAM
+ *
+ *   For the 405EX(r), there is no OCM, so we are left with (2) or (3)
+ *   the latter of which is less than desireable since it requires
+ *   setting up the SDRAM and ECC in assembly code.
+ *
+ *   To use (2), define 'CONFIG_SYS_INIT_DCACHE_CS' to be an unused chip
+ *   select on the External Bus Controller (EBC) and then select a
+ *   value for 'CONFIG_SYS_INIT_RAM_ADDR' outside of the range of valid,
+ *   physical SDRAM. Otherwise, undefine 'CONFIG_SYS_INIT_DCACHE_CS' and
+ *   select a value for 'CONFIG_SYS_INIT_RAM_ADDR' within the range of valid,
+ *   physical SDRAM to use (3).
+ *-----------------------------------------------------------------------*/
+
+#define CONFIG_SYS_INIT_DCACHE_CS	4
+
+#if defined(CONFIG_SYS_INIT_DCACHE_CS)
+#define CONFIG_SYS_INIT_RAM_ADDR \
+	(CONFIG_SYS_SDRAM_BASE + (1 << 30))	/*  1 GiB */
+#else
+#define CONFIG_SYS_INIT_RAM_ADDR \
+	(CONFIG_SYS_SDRAM_BASE + (32 << 20))	/* 32 MiB */
+#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
+
+#define CONFIG_SYS_INIT_RAM_SIZE \
+	(4 << 10)				/*  4 KiB */
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * If the data cache is being used for the primordial stack and global
+ * data area, the POST word must be placed somewhere else. The General
+ * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves
+ * its compare and mask register contents across reset, so it is used
+ * for the POST word.
+ */
+
+#if defined(CONFIG_SYS_INIT_DCACHE_CS)
+# define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+# define CONFIG_SYS_POST_WORD_ADDR \
+	(CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
+#else
+# define CONFIG_SYS_INIT_EXTRA_SIZE	16
+# define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_EXTRA_SIZE)
+# define CONFIG_SYS_OCM_DATA_ADDR	CONFIG_SYS_INIT_RAM_ADDR
+#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#define CONFIG_CONS_INDEX	1	/* Use UART0 */
+#define CONFIG_SYS_BASE_BAUD	691200
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+#define CONFIG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars */
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_FLASH_CFI		/* The flash is CFI compatible */
+#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver */
+
+#define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	512
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
+#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+#endif /* CONFIG_ENV_IS_IN_FLASH */
+
+/* Gbit PHYs */
+#define CONFIG_BITBANGMII		/* bit-bang MII PHY management */
+#define CONFIG_BITBANGMII_MULTI
+
+#define CONFIG_SYS_MDIO_PIN  (0x80000000 >> 12)	/* MDIO is GPIO12 */
+#define CONFIG_SYS_MDC_PIN   (0x80000000 >> 13)	/* MDC  is GPIO13 */
+
+#define CONFIG_SYS_GBIT_MII_BUSNAME	"io_miiphy0"
+
+#define CONFIG_SYS_MDIO1_PIN  (0x80000000 >> 2)	/* MDIO is GPIO2 */
+#define CONFIG_SYS_MDC1_PIN   (0x80000000 >> 3)	/* MDC  is GPIO3 */
+
+#define CONFIG_SYS_GBIT_MII1_BUSNAME	"io_miiphy1"
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_MBYTES_SDRAM        (128)	/* 128MB */
+
+/*
+ * CONFIG_PPC4xx_DDR_AUTOCALIBRATION
+ *
+ * Note: DDR Autocalibration Method_A scans the full range of possible PPC4xx
+ *       SDRAM Controller DDR autocalibration values and takes a lot longer
+ *       to run than Method_B.
+ * (See the Method_A and Method_B algorithm discription in the file:
+ *	arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c)
+ * Define CONFIG_PPC4xx_DDR_METHOD_A to use DDR autocalibration Method_A
+ *
+ * DDR Autocalibration Method_B is the default.
+ */
+#define	CONFIG_PPC4xx_DDR_AUTOCALIBRATION
+#define	DEBUG_PPC4xx_DDR_AUTOCALIBRATION
+#undef	CONFIG_PPC4xx_DDR_METHOD_A
+
+#define	CONFIG_SYS_SDRAM0_MB0CF_BASE	((0 << 20) + CONFIG_SYS_SDRAM_BASE)
+
+/* DDR1/2 SDRAM Device Control Register Data Values */
+#define CONFIG_SYS_SDRAM0_MB0CF	((CONFIG_SYS_SDRAM0_MB0CF_BASE >> 3) | \
+				 SDRAM_RXBAS_SDSZ_128MB | \
+				 SDRAM_RXBAS_SDAM_MODE2 | \
+				 SDRAM_RXBAS_SDBE_ENABLE)
+#define CONFIG_SYS_SDRAM0_MB1CF	SDRAM_RXBAS_SDBE_DISABLE
+#define CONFIG_SYS_SDRAM0_MB2CF	SDRAM_RXBAS_SDBE_DISABLE
+#define CONFIG_SYS_SDRAM0_MB3CF	SDRAM_RXBAS_SDBE_DISABLE
+#define CONFIG_SYS_SDRAM0_MCOPT1	(SDRAM_MCOPT1_PMU_OPEN | \
+				 SDRAM_MCOPT1_4_BANKS | \
+				 SDRAM_MCOPT1_DDR2_TYPE | \
+				 SDRAM_MCOPT1_QDEP | \
+				 SDRAM_MCOPT1_DCOO_DISABLED)
+#define CONFIG_SYS_SDRAM0_MCOPT2	0x00000000
+#define CONFIG_SYS_SDRAM0_MODT0	(SDRAM_MODT_EB0W_ENABLE | \
+				 SDRAM_MODT_EB0R_ENABLE)
+#define CONFIG_SYS_SDRAM0_MODT1	0x00000000
+#define CONFIG_SYS_SDRAM0_CODT		(SDRAM_CODT_RK0R_ON | \
+				 SDRAM_CODT_CKLZ_36OHM | \
+				 SDRAM_CODT_DQS_1_8_V_DDR2 | \
+				 SDRAM_CODT_IO_NMODE)
+#define CONFIG_SYS_SDRAM0_RTR		SDRAM_RTR_RINT_ENCODE(1560)
+#define CONFIG_SYS_SDRAM0_INITPLR0	(SDRAM_INITPLR_ENABLE | \
+		SDRAM_INITPLR_IMWT_ENCODE(80) | \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP))
+#define CONFIG_SYS_SDRAM0_INITPLR1	(SDRAM_INITPLR_ENABLE | \
+		SDRAM_INITPLR_IMWT_ENCODE(3) | \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \
+		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
+		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
+#define CONFIG_SYS_SDRAM0_INITPLR2	(SDRAM_INITPLR_ENABLE | \
+		SDRAM_INITPLR_IMWT_ENCODE(2) | \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
+		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2) | \
+		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL))
+#define CONFIG_SYS_SDRAM0_INITPLR3	(SDRAM_INITPLR_ENABLE | \
+		SDRAM_INITPLR_IMWT_ENCODE(2) | \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
+		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3) | \
+		SDRAM_INITPLR_IMA_ENCODE(0))
+#define CONFIG_SYS_SDRAM0_INITPLR4	(SDRAM_INITPLR_ENABLE | \
+		SDRAM_INITPLR_IMWT_ENCODE(2) | \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
+		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
+		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_DISABLE | \
+					 JEDEC_MA_EMR_RTT_75OHM))
+#define CONFIG_SYS_SDRAM0_INITPLR5	(SDRAM_INITPLR_ENABLE | \
+		SDRAM_INITPLR_IMWT_ENCODE(2) | \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
+		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
+		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
+					 JEDEC_MA_MR_CL_DDR2_5_0_CLK | \
+					 JEDEC_MA_MR_BLEN_4 | \
+					 JEDEC_MA_MR_DLL_RESET))
+#define CONFIG_SYS_SDRAM0_INITPLR6	(SDRAM_INITPLR_ENABLE | \
+		SDRAM_INITPLR_IMWT_ENCODE(3) | \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \
+		SDRAM_INITPLR_IBA_ENCODE(0x0) | \
+		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
+#define CONFIG_SYS_SDRAM0_INITPLR7	(SDRAM_INITPLR_ENABLE | \
+		SDRAM_INITPLR_IMWT_ENCODE(26) | \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
+#define CONFIG_SYS_SDRAM0_INITPLR8	(SDRAM_INITPLR_ENABLE | \
+		SDRAM_INITPLR_IMWT_ENCODE(26) | \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
+#define CONFIG_SYS_SDRAM0_INITPLR9	(SDRAM_INITPLR_ENABLE | \
+		SDRAM_INITPLR_IMWT_ENCODE(26) | \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
+#define CONFIG_SYS_SDRAM0_INITPLR10	(SDRAM_INITPLR_ENABLE | \
+		SDRAM_INITPLR_IMWT_ENCODE(26) | \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
+#define CONFIG_SYS_SDRAM0_INITPLR11	(SDRAM_INITPLR_ENABLE | \
+		SDRAM_INITPLR_IMWT_ENCODE(2) | \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
+		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
+		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
+					 JEDEC_MA_MR_CL_DDR2_5_0_CLK | \
+					 JEDEC_MA_MR_BLEN_4))
+#define CONFIG_SYS_SDRAM0_INITPLR12	(SDRAM_INITPLR_ENABLE | \
+		SDRAM_INITPLR_IMWT_ENCODE(2) | \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
+		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
+		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER | \
+					 JEDEC_MA_EMR_RDQS_DISABLE | \
+					 JEDEC_MA_EMR_DQS_DISABLE | \
+					 JEDEC_MA_EMR_RTT_DISABLED | \
+					 JEDEC_MA_EMR_ODS_NORMAL))
+#define CONFIG_SYS_SDRAM0_INITPLR13	(SDRAM_INITPLR_ENABLE | \
+		SDRAM_INITPLR_IMWT_ENCODE(2) | \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
+		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
+		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT | \
+					 JEDEC_MA_EMR_RDQS_DISABLE | \
+					 JEDEC_MA_EMR_DQS_DISABLE | \
+					 JEDEC_MA_EMR_RTT_DISABLED | \
+					 JEDEC_MA_EMR_ODS_NORMAL))
+#define CONFIG_SYS_SDRAM0_INITPLR14	(SDRAM_INITPLR_DISABLE)
+#define CONFIG_SYS_SDRAM0_INITPLR15	(SDRAM_INITPLR_DISABLE)
+#define CONFIG_SYS_SDRAM0_RQDC		(SDRAM_RQDC_RQDE_ENABLE | \
+				 SDRAM_RQDC_RQFD_ENCODE(56))
+#define CONFIG_SYS_SDRAM0_RFDC		SDRAM_RFDC_RFFD_ENCODE(521)
+#define CONFIG_SYS_SDRAM0_RDCC		(SDRAM_RDCC_RDSS_T2)
+#define CONFIG_SYS_SDRAM0_DLCR		(SDRAM_DLCR_DCLM_AUTO | \
+				 SDRAM_DLCR_DLCS_CONT_DONE | \
+				 SDRAM_DLCR_DLCV_ENCODE(165))
+#define CONFIG_SYS_SDRAM0_CLKTR	(SDRAM_CLKTR_CLKP_180_DEG_ADV)
+#define CONFIG_SYS_SDRAM0_WRDTR	0x00000000
+#define CONFIG_SYS_SDRAM0_SDTR1	(SDRAM_SDTR1_LDOF_2_CLK | \
+				 SDRAM_SDTR1_RTW_2_CLK | \
+				 SDRAM_SDTR1_WTWO_1_CLK | \
+				 SDRAM_SDTR1_RTRO_1_CLK)
+#define CONFIG_SYS_SDRAM0_SDTR2	(SDRAM_SDTR2_RCD_3_CLK | \
+				 SDRAM_SDTR2_WTR_2_CLK | \
+				 SDRAM_SDTR2_XSNR_32_CLK | \
+				 SDRAM_SDTR2_WPC_4_CLK | \
+				 SDRAM_SDTR2_RPC_2_CLK | \
+				 SDRAM_SDTR2_RP_3_CLK | \
+				 SDRAM_SDTR2_RRD_2_CLK)
+#define CONFIG_SYS_SDRAM0_SDTR3	(SDRAM_SDTR3_RAS_ENCODE(9) | \
+				 SDRAM_SDTR3_RC_ENCODE(12) | \
+				 SDRAM_SDTR3_XCS | \
+				 SDRAM_SDTR3_RFC_ENCODE(21))
+#define CONFIG_SYS_SDRAM0_MMODE	(SDRAM_MMODE_WR_DDR2_3_CYC | \
+				 SDRAM_MMODE_DCL_DDR2_5_0_CLK | \
+				 SDRAM_MMODE_BLEN_4)
+#define CONFIG_SYS_SDRAM0_MEMODE	(SDRAM_MEMODE_DQS_DISABLE | \
+				 SDRAM_MEMODE_RTT_75OHM)
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0	400000
+
+#define CONFIG_PCA9698		1	/* NXP PCA9698 */
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x52	/* I2C boot EEPROM (24C02BN) */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
+
+/* I2C bootstrap EEPROM */
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR	0x54
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET	0
+#define CONFIG_4xx_CONFIG_BLOCKSIZE		16
+
+/* Temp sensor/hwmon/dtt */
+#define CONFIG_DTT_LM63		1	/* National LM63 */
+#define CONFIG_DTT_SENSORS	{ 0x18, 0x4c, 0x4e }	/* Sensor addresses */
+#define CONFIG_DTT_PWM_LOOKUPTABLE	\
+		{ { 40, 10 }, { 43, 13 }, { 46, 16 },  \
+		  { 50, 20 }, { 53, 27 }, { 56, 34 }, { 60, 40 } }
+#define CONFIG_DTT_TACH_LIMIT	0xa10
+
+/*-----------------------------------------------------------------------
+ * Ethernet
+ *----------------------------------------------------------------------*/
+#define CONFIG_M88E1111_PHY	1
+#define CONFIG_IBM_EMAC4_V4	1
+#define CONFIG_EMAC_PHY_MODE	EMAC_PHY_MODE_RGMII_RGMII
+#define CONFIG_PHY_ADDR		0x12	/* PHY address, See schematics */
+
+#define CONFIG_PHY_RESET	1	/* reset phy upon startup */
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+
+#define CONFIG_HAS_ETH0		1
+
+#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"   */
+#define CONFIG_PHY1_ADDR	0x13
+
+/* Debug messages for the DDR autocalibration */
+#define CONFIG_AUTOCALIB		"silent\0"
+
+/*
+ * Default environment variables
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_AMCC_DEF_ENV						\
+	CONFIG_AMCC_DEF_ENV_POWERPC					\
+	CONFIG_AMCC_DEF_ENV_PPC_OLD					\
+	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
+	"logversion=2\0"						\
+	"kernel_addr=fc000000\0"					\
+	"fdt_addr=fc1e0000\0"						\
+	"ramdisk_addr=fc200000\0"					\
+	"pciconfighost=1\0"						\
+	"pcie_mode=RP:RP\0"						\
+	""
+
+/*
+ * Commands additional to the ones defined in amcc-common.h
+ */
+#define CONFIG_CMD_CHIP_CONFIG
+#define CONFIG_CMD_DTT
+
+#define CONFIG_SYS_POST_MEMORY_ON	CONFIG_SYS_POST_MEMORY
+
+/* POST support */
+#define CONFIG_POST		(CONFIG_SYS_POST_CACHE		| \
+				 CONFIG_SYS_POST_CPU		| \
+				 CONFIG_SYS_POST_ETHER		| \
+				 CONFIG_SYS_POST_I2C		| \
+				 CONFIG_SYS_POST_MEMORY_ON	| \
+				 CONFIG_SYS_POST_UART)
+
+/* Define here the base-addresses of the UARTs to test in POST */
+#define CONFIG_SYS_POST_UART_TABLE	{ CONFIG_SYS_NS16550_COM1, \
+			CONFIG_SYS_NS16550_COM2 }
+
+#define CONFIG_LOGBUFFER
+#define CONFIG_SYS_POST_CACHE_ADDR	0x00800000 /* free virtual address */
+
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ *----------------------------------------------------------------------*/
+
+/* Memory Bank 0 (NOR-flash) */
+#define CONFIG_SYS_EBC_PB0AP	(EBC_BXAP_BME_DISABLED		|	\
+				 EBC_BXAP_TWT_ENCODE(11)	|	\
+				 EBC_BXAP_BCE_DISABLE		|	\
+				 EBC_BXAP_BCT_2TRANS		|	\
+				 EBC_BXAP_CSN_ENCODE(0)		|	\
+				 EBC_BXAP_OEN_ENCODE(0)		|	\
+				 EBC_BXAP_WBN_ENCODE(1)		|	\
+				 EBC_BXAP_WBF_ENCODE(2)		|	\
+				 EBC_BXAP_TH_ENCODE(2)		|	\
+				 EBC_BXAP_RE_DISABLED		|	\
+				 EBC_BXAP_SOR_NONDELAYED	|	\
+				 EBC_BXAP_BEM_WRITEONLY		|	\
+				 EBC_BXAP_PEN_DISABLED)
+#define CONFIG_SYS_EBC_PB0CR	(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
+				 EBC_BXCR_BS_64MB		|	\
+				 EBC_BXCR_BU_RW			|	\
+				 EBC_BXCR_BW_16BIT)
+
+/* Memory Bank 1 (NVRAM/Uart) */
+#define CONFIG_SYS_EBC_PB1AP	(EBC_BXAP_BME_ENABLED		|	\
+				 EBC_BXAP_FWT_ENCODE(8)		|	\
+				 EBC_BXAP_BWT_ENCODE(4)		|	\
+				 EBC_BXAP_BCE_DISABLE		|	\
+				 EBC_BXAP_BCT_2TRANS		|	\
+				 EBC_BXAP_CSN_ENCODE(0)		|	\
+				 EBC_BXAP_OEN_ENCODE(1)		|	\
+				 EBC_BXAP_WBN_ENCODE(1)		|	\
+				 EBC_BXAP_WBF_ENCODE(1)		|	\
+				 EBC_BXAP_TH_ENCODE(2)		|	\
+				 EBC_BXAP_RE_DISABLED		|	\
+				 EBC_BXAP_SOR_NONDELAYED	|	\
+				 EBC_BXAP_BEM_WRITEONLY		|	\
+				 EBC_BXAP_PEN_DISABLED)
+#define CONFIG_SYS_EBC_PB1CR	(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_NVRAM_BASE) | \
+				 EBC_BXCR_BS_1MB		|	\
+				 EBC_BXCR_BU_RW			|	\
+				 EBC_BXCR_BW_8BIT)
+
+/* Memory Bank 2 (FPGA) */
+#define CONFIG_SYS_EBC_PB2AP	(EBC_BXAP_BME_DISABLED		|	\
+				 EBC_BXAP_TWT_ENCODE(5)		|	\
+				 EBC_BXAP_BCE_DISABLE		|	\
+				 EBC_BXAP_BCT_2TRANS		|	\
+				 EBC_BXAP_CSN_ENCODE(0)		|	\
+				 EBC_BXAP_OEN_ENCODE(2)		|	\
+				 EBC_BXAP_WBN_ENCODE(1)		|	\
+				 EBC_BXAP_WBF_ENCODE(1)		|	\
+				 EBC_BXAP_TH_ENCODE(0)		|	\
+				 EBC_BXAP_RE_DISABLED		|	\
+				 EBC_BXAP_SOR_NONDELAYED	|	\
+				 EBC_BXAP_BEM_WRITEONLY		|	\
+				 EBC_BXAP_PEN_DISABLED)
+#define CONFIG_SYS_EBC_PB2CR	(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA0_BASE) | \
+				 EBC_BXCR_BS_1MB		|	\
+				 EBC_BXCR_BU_RW			|	\
+				 EBC_BXCR_BW_16BIT)
+
+/* Memory Bank 3 (Latches) */
+#define CONFIG_SYS_EBC_PB3AP	(EBC_BXAP_BME_ENABLED		|	\
+				 EBC_BXAP_FWT_ENCODE(8)		|	\
+				 EBC_BXAP_BWT_ENCODE(4)		|	\
+				 EBC_BXAP_BCE_DISABLE		|	\
+				 EBC_BXAP_BCT_2TRANS		|	\
+				 EBC_BXAP_CSN_ENCODE(0)		|	\
+				 EBC_BXAP_OEN_ENCODE(1)		|	\
+				 EBC_BXAP_WBN_ENCODE(1)		|	\
+				 EBC_BXAP_WBF_ENCODE(1)		|	\
+				 EBC_BXAP_TH_ENCODE(2)		|	\
+				 EBC_BXAP_RE_DISABLED		|	\
+				 EBC_BXAP_SOR_NONDELAYED	|	\
+				 EBC_BXAP_BEM_WRITEONLY		|	\
+				 EBC_BXAP_PEN_DISABLED)
+#define CONFIG_SYS_EBC_PB3CR	(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_LATCH_BASE) | \
+				 EBC_BXCR_BS_1MB		|	\
+				 EBC_BXCR_BU_RW			|	\
+				 EBC_BXCR_BW_16BIT)
+
+/* EBC peripherals */
+
+#define CONFIG_SYS_FPGA_BASE(k) \
+	(k ? CONFIG_SYS_FPGA1_BASE : CONFIG_SYS_FPGA0_BASE)
+
+#define CONFIG_SYS_FPGA_DONE(k) \
+	(k ? 0x0040 : 0x0080)
+
+#define CONFIG_SYS_FPGA_COUNT		2
+
+#define CONFIG_SYS_FPGA_PTR { \
+	(struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, \
+	(struct ihs_fpga *)CONFIG_SYS_FPGA1_BASE }
+
+#define CONFIG_SYS_FPGA_COMMON
+
+#define CONFIG_SYS_LATCH0_RESET		0xffff
+#define CONFIG_SYS_LATCH0_BOOT		0xffff
+#define CONFIG_SYS_LATCH1_RESET		0xffbf
+#define CONFIG_SYS_LATCH1_BOOT		0xffff
+
+/*-----------------------------------------------------------------------
+ * GPIO Setup
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_4xx_GPIO_TABLE { /*	  Out		GPIO */ \
+{ \
+/* GPIO Core 0 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1     }, /* GPIO0 */ \
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG}, /* GPIO1 */ \
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG}, /* GPIO2 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1     }, /* GPIO3 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG}, /* GPIO4 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG}, /* GPIO5 */ \
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG}, /* GPIO6 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1     }, /* GPIO7 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0     }, /* GPIO8 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0     }, /* GPIO9 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0     }, /* GPIO10 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1     }, /* GPIO11 */ \
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG}, /* GPIO12 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1     }, /* GPIO13 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG}, /* GPIO14 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG}, /* GPIO15 */ \
+{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0     }, /* GPIO16 */ \
+{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0     }, /* GPIO17 */ \
+{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0     }, /* GPIO18 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0     }, /* GPIO19 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0     }, /* GPIO20 */ \
+{GPIO0_BASE, GPIO_IN,  GPIO_ALT2, GPIO_OUT_0     }, /* GPIO21 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG}, /* GPIO22 */ \
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG}, /* GPIO23 */ \
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0     }, /* GPIO24 */ \
+{GPIO0_BASE, GPIO_IN,  GPIO_ALT3, GPIO_OUT_0     }, /* GPIO25 */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0     }, /* GPIO26 */ \
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0     }, /* GPIO27 */ \
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0     }, /* GPIO28 */ \
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0     }, /* GPIO29 */ \
+{GPIO0_BASE, GPIO_IN,  GPIO_ALT2, GPIO_OUT_0     }, /* GPIO30 */ \
+{GPIO0_BASE, GPIO_IN,  GPIO_ALT2, GPIO_OUT_0     }, /* GPIO31 */ \
+} \
+}
+
+#define CONFIG_SYS_GPIO_STARTUP_FINISHED	15
+#define CONFIG_SYS_GPIO_STARTUP_FINISHED_N	14
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/iocon.h b/qemu/roms/u-boot/include/configs/iocon.h
new file mode 100644
index 000000000..f36c2a350
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/iocon.h
@@ -0,0 +1,292 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_405EP		1	/* this is a PPC405 CPU */
+#define CONFIG_IOCON		1	/*  on a IoCon board */
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
+
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME		iocon
+#define CONFIG_IDENT_STRING	" iocon 0.05"
+#include "amcc-common.h"
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_LAST_STAGE_INIT
+
+#define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll   */
+
+/*
+ * Configure PLL
+ */
+#define PLLMR0_DEFAULT PLLMR0_266_133_66
+#define PLLMR1_DEFAULT PLLMR1_266_133_66
+
+#undef CONFIG_ZERO_BOOTDELAY_CHECK	/* ignore keypress on bootdelay==0 */
+#define CONFIG_AUTOBOOT_KEYED		/* use key strings to stop autoboot */
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
+
+#define CONFIG_ENV_IS_IN_FLASH	/* use FLASH for environment vars */
+
+/*
+ * Default environment variables
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_AMCC_DEF_ENV						\
+	CONFIG_AMCC_DEF_ENV_POWERPC					\
+	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
+	"kernel_addr=fc000000\0"					\
+	"fdt_addr=fc1e0000\0"						\
+	"ramdisk_addr=fc200000\0"					\
+	""
+
+#define CONFIG_PHY_ADDR		4	/* PHY address			*/
+#define CONFIG_HAS_ETH0
+#define CONFIG_PHY_CLK_FREQ    EMAC_STACR_CLK_66MHZ
+
+/*
+ * Commands additional to the ones defined in amcc-common.h
+ */
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_FPGAD
+#undef CONFIG_CMD_EEPROM
+
+/*
+ * SDRAM configuration (please see cpu/ppc/sdram.[ch])
+ */
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0 */
+
+/* SDRAM timings used in datasheet */
+#define CONFIG_SYS_SDRAM_CL             3	/* CAS latency */
+#define CONFIG_SYS_SDRAM_tRP           20	/* PRECHARGE command period */
+#define CONFIG_SYS_SDRAM_tRC           66	/* ACTIVE-to-ACTIVE period */
+#define CONFIG_SYS_SDRAM_tRCD          20	/* ACTIVE-to-READ delay */
+#define CONFIG_SYS_SDRAM_tRFC          66	/* Auto refresh period */
+
+/*
+ * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
+ * The Linux BASE_BAUD define should match this configuration.
+ *    baseBaud = cpuClock/(uartDivisor*16)
+ * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * set Linux BASE_BAUD to 403200.
+ */
+#define CONFIG_CONS_INDEX		1	/* Use UART0 */
+#undef  CONFIG_SYS_EXT_SERIAL_CLOCK		/* external serial clock */
+#undef  CONFIG_SYS_405_UART_ERRATA_59		/* 405GP/CR Rev. D silicon */
+#define CONFIG_SYS_BASE_BAUD		691200
+
+/*
+ * I2C stuff
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
+
+#define CONFIG_SYS_I2C_SPEED		400000
+
+#define CONFIG_PCA953X			/* NXP PCA9554 */
+#define CONFIG_PCA9698			/* NXP PCA9698 */
+
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define CONFIG_SYS_I2C_SOFT
+#define CONFIG_SYS_I2C_SOFT_SPEED		50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE		0x7F
+#define I2C_SOFT_DECLARATIONS2
+#define CONFIG_SYS_I2C_SOFT_SPEED_2		50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_2		0x7F
+#define I2C_SOFT_DECLARATIONS3
+#define CONFIG_SYS_I2C_SOFT_SPEED_3		50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_3		0x7F
+#define I2C_SOFT_DECLARATIONS4
+#define CONFIG_SYS_I2C_SOFT_SPEED_4		50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_4		0x7F
+
+#define CONFIG_SYS_CH7301_I2C			{1, 2, 3, 4}
+
+#ifndef __ASSEMBLY__
+void fpga_gpio_set(unsigned int bus, int pin);
+void fpga_gpio_clear(unsigned int bus, int pin);
+int fpga_gpio_get(unsigned int bus, int pin);
+#endif
+
+#define I2C_ACTIVE	{ }
+#define I2C_TRISTATE	{ }
+#define I2C_READ \
+	(fpga_gpio_get(I2C_ADAP_HWNR, 0x0040) ? 1 : 0)
+#define I2C_SDA(bit) \
+	do { \
+		if (bit) \
+			fpga_gpio_set(I2C_ADAP_HWNR, 0x0040); \
+		else \
+			fpga_gpio_clear(I2C_ADAP_HWNR, 0x0040); \
+	} while (0)
+#define I2C_SCL(bit) \
+	do { \
+		if (bit) \
+			fpga_gpio_set(I2C_ADAP_HWNR, 0x0020); \
+		else \
+			fpga_gpio_clear(I2C_ADAP_HWNR, 0x0020); \
+	} while (0)
+#define I2C_DELAY	udelay(25)	/* 1/4 I2C clock duration */
+
+/*
+ * OSD hardware
+ */
+#define CONFIG_SYS_MPC92469AC
+#define CONFIG_SYS_CH7301
+
+/*
+ * FLASH organization
+ */
+#define CONFIG_SYS_FLASH_CFI		/* The flash is CFI compatible	*/
+#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
+
+#define CONFIG_SYS_FLASH_BASE		0xFC000000
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sectors per chip*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase/ms */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write/ms */
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buff'd writes */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO	/* 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* no warn upon unknown flash */
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector */
+#define CONFIG_ENV_ADDR		((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
+#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+#endif
+
+/*
+ * PPC405 GPIO Configuration
+ */
+#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO	Alternate1	*/ \
+{ \
+/* GPIO Core 0 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0	PerBLast */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO1	TS1E */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO2	TS2E */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO3	TS1O */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO4	TS2O */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1      }, /* GPIO5	TS3 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO6	TS4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO7	TS5 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO8	TS6 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO9	TrcClk */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10	PerCS1 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11	PerCS2 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12	PerCS3 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13	PerCS4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14	PerAddr03 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15	PerAddr04 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16	PerAddr05 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17	IRQ0 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18	IRQ1 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19	IRQ2 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO20	IRQ3 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO21	IRQ4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO22	IRQ5 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO23	IRQ6 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24	UART0_DCD */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25	UART0_DSR */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26	UART0_RI */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27	UART0_DTR */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28	UART1_Rx */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29	UART1_Tx */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO30	RejectPkt0 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO31	RejectPkt1 */ \
+} \
+}
+
+/*
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory (OCM) for temperary stack until sdram is tested */
+#define CONFIG_SYS_TEMP_STACK_OCM        1
+
+/* On Chip Memory location */
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
+#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+	(CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (NOR-FLASH) initialization */
+#define CONFIG_SYS_EBC_PB0AP		0xa382a880
+#define CONFIG_SYS_EBC_PB0CR		0xFC0DA000
+
+/* Memory Bank 1 (NVRAM) initializatio */
+#define CONFIG_SYS_EBC_PB1AP		0x92015480
+#define CONFIG_SYS_EBC_PB1CR		0xFB858000
+
+/* Memory Bank 2 (FPGA0) initialization */
+#define CONFIG_SYS_FPGA0_BASE		0x7f100000
+#define CONFIG_SYS_EBC_PB2AP		0x02825080
+#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_FPGA0_BASE | 0x1a000)
+
+#define CONFIG_SYS_FPGA_BASE(k)		CONFIG_SYS_FPGA0_BASE
+#define CONFIG_SYS_FPGA_DONE(k)		0x0010
+
+#define CONFIG_SYS_FPGA_COUNT		1
+
+#define CONFIG_SYS_MCLINK_MAX		3
+
+#define CONFIG_SYS_FPGA_PTR \
+	{ (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
+
+/* Memory Bank 3 (Latches) initialization */
+#define CONFIG_SYS_LATCH_BASE		0x7f200000
+#define CONFIG_SYS_EBC_PB3AP		0x02025080
+#define CONFIG_SYS_EBC_PB3CR		0x7f21a000
+
+#define CONFIG_SYS_LATCH0_RESET		0xffef
+#define CONFIG_SYS_LATCH0_BOOT		0xffff
+#define CONFIG_SYS_LATCH1_RESET		0xffff
+#define CONFIG_SYS_LATCH1_BOOT		0xffff
+
+/*
+ * OSD Setup
+ */
+#define CONFIG_SYS_MPC92469AC
+#define CONFIG_SYS_CH7301
+#define CONFIG_SYS_OSD_SCREENS		1
+
+#define CONFIG_BITBANGMII		/* bit-bang MII PHY management */
+#define CONFIG_BITBANGMII_MULTI
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/ip04.h b/qemu/roms/u-boot/include/configs/ip04.h
new file mode 100644
index 000000000..3767502fa
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/ip04.h
@@ -0,0 +1,150 @@
+/*
+ * U-boot - Configuration file for IP04 board (having BF532 processor)
+ *
+ * Copyright (c) 2006 Intratrade Ltd., Ivan Danov, idanov@gmail.com
+ *
+ * Copyright (c) 2005-2010 Analog Devices Inc.
+ *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __CONFIG_IP04_H__
+#define __CONFIG_IP04_H__
+
+#include <asm/config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU             bf532-0.5
+#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_NAND
+
+
+/*
+ * Clock Settings
+ *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz					*/
+#define CONFIG_CLKIN_HZ			10000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
+/*                                                1 = CLKIN / 2		*/
+#define CONFIG_CLKIN_HALF		0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
+/*                                                1 = bypass PLL	*/
+#define CONFIG_PLL_BYPASS		0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
+/* Values can range from 0-63 (where 0 means 64)			*/
+#define CONFIG_VCO_MULT			40
+/* CCLK_DIV controls the core clock divider				*/
+/* Values can be 1, 2, 4, or 8 ONLY					*/
+#define CONFIG_CCLK_DIV			1
+/* SCLK_DIV controls the system clock divider				*/
+/* Values can range from 1-15						*/
+#define CONFIG_SCLK_DIV			3
+
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_ADD_WDTH	10
+#define CONFIG_MEM_SIZE		64
+
+#define CONFIG_EBIU_SDRRC_VAL	0x408
+#define CONFIG_EBIU_SDGCTL_VAL	0x9111cd
+
+#define CONFIG_EBIU_AMGCTL_VAL	0xFF
+#define CONFIG_EBIU_AMBCTL0_VAL	0xffc2ffc2
+#define CONFIG_EBIU_AMBCTL1_VAL	0xffc2ffc2
+
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)
+
+
+/*
+ * Network Settings
+ */
+#define ADI_CMDS_NETWORK	1
+#define CONFIG_HOSTNAME		IP04
+
+#define CONFIG_DRIVER_DM9000	1
+#define CONFIG_DM9000_NO_SROM
+#define CONFIG_DM9000_BASE	0x20100000
+#define DM9000_IO		CONFIG_DM9000_BASE
+#define DM9000_DATA		(CONFIG_DM9000_BASE + 2)
+
+#define CONFIG_LIB_RAND
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_ENV_OVERWRITE	1
+#define CONFIG_SYS_NO_FLASH		/* we have only NAND */
+
+
+/*
+ * SPI Settings
+ */
+#define CONFIG_BFIN_SPI
+#define CONFIG_ENV_SPI_MAX_HZ	30000000
+#define CONFIG_SF_DEFAULT_SPEED	30000000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_WINBOND
+
+
+/*
+ * Env Storage Settings
+ */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_PREBOOT		"echo starting from spi flash"
+#define CONFIG_ENV_OFFSET	0x30000
+#define CONFIG_ENV_SIZE		0x10000
+#define CONFIG_ENV_SECT_SIZE	0x10000
+
+
+/*
+ * NAND Settings
+ */
+#define CONFIG_NAND_PLAT
+#define CONFIG_SYS_NAND_BASE		0x20000000
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+
+#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
+#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
+#define BFIN_NAND_WRITE(addr, cmd) \
+	do { \
+		bfin_write8(addr, cmd); \
+		SSYNC(); \
+	} while (0)
+
+#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
+#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
+#define NAND_PLAT_GPIO_DEV_READY       GPIO_PF10
+
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_MISC_INIT_R	/* needed for MAC address */
+#define CONFIG_UART_CONSOLE	0
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
+
+#undef CONFIG_SHOW_BOOT_PROGRESS
+/* Enable this if bootretry required; currently it's disabled */
+#define CONFIG_BOOT_RETRY_TIME	-1
+#define CONFIG_BOOTCOMMAND	"run nandboot"
+#define CONFIG_AUTOBOOT_PROMPT	"autoboot in %d seconds\n"
+
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/ipam390.h b/qemu/roms/u-boot/include/configs/ipam390.h
new file mode 100644
index 000000000..fdd568074
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/ipam390.h
@@ -0,0 +1,339 @@
+/*
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ * Based on:
+ * U-Boot:include/configs/da850evm.h
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Based on davinci_dvevm.h. Original Copyrights follow:
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Board
+ */
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_BARIX_IPAM390
+
+/*
+ * SoC Configuration
+ */
+#define CONFIG_MACH_DAVINCI_DA850_EVM
+#define CONFIG_ARM926EJS		/* arm926ejs CPU core */
+#define CONFIG_SOC_DA8XX		/* TI DA8xx SoC */
+#define CONFIG_SOC_DA850		/* TI DA850 SoC */
+#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
+#define CONFIG_SYS_CLK_FREQ		clk_get(DAVINCI_ARM_CLKID)
+#define CONFIG_SYS_OSCIN_FREQ		24000000
+#define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
+#define CONFIG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
+#define CONFIG_SYS_DA850_PLL_INIT
+#define CONFIG_SYS_DA850_DDR_INIT
+#define CONFIG_SYS_TEXT_BASE		0xc1080000
+
+/*
+ * Memory Info
+ */
+#define CONFIG_SYS_MALLOC_LEN	(0x10000 + 1*1024*1024) /* malloc() len */
+#define PHYS_SDRAM_1		DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
+#define PHYS_SDRAM_1_SIZE	(128 << 20) /* SDRAM size 128MB */
+#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
+
+/* memtest start addr */
+#define CONFIG_SYS_MEMTEST_START	(PHYS_SDRAM_1 + 0x2000000)
+
+/* memtest will be run on 16MB */
+#define CONFIG_SYS_MEMTEST_END	(CONFIG_SYS_MEMTEST_START + 16 * 1024 * 1024)
+
+#define CONFIG_NR_DRAM_BANKS	1 /* we have 1 bank of DRAM */
+
+#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (	\
+	DAVINCI_SYSCFG_SUSPSRC_TIMER0 |		\
+	DAVINCI_SYSCFG_SUSPSRC_UART2 |		\
+	DAVINCI_SYSCFG_SUSPSRC_UART0 |		\
+	DAVINCI_SYSCFG_SUSPSRC_EMAC)
+
+/*
+ * PLL configuration
+ */
+#define CONFIG_SYS_DV_CLKMODE          0
+#define CONFIG_SYS_DA850_PLL0_POSTDIV  1
+#define CONFIG_SYS_DA850_PLL0_PLLDIV1  0x8000
+#define CONFIG_SYS_DA850_PLL0_PLLDIV2  0x8001
+#define CONFIG_SYS_DA850_PLL0_PLLDIV3  0x8002
+#define CONFIG_SYS_DA850_PLL0_PLLDIV4  0x8003
+#define CONFIG_SYS_DA850_PLL0_PLLDIV5  0x8002
+#define CONFIG_SYS_DA850_PLL0_PLLDIV6  CONFIG_SYS_DA850_PLL0_PLLDIV1
+#define CONFIG_SYS_DA850_PLL0_PLLDIV7  0x8005
+
+#define CONFIG_SYS_DA850_PLL1_POSTDIV  1
+#define CONFIG_SYS_DA850_PLL1_PLLDIV1  0x8000
+#define CONFIG_SYS_DA850_PLL1_PLLDIV2  0x8001
+#define CONFIG_SYS_DA850_PLL1_PLLDIV3  0x8002
+
+#define CONFIG_SYS_DA850_PLL0_PLLM     24
+#define CONFIG_SYS_DA850_PLL1_PLLM     24
+
+/*
+ * DDR2 memory configuration
+ */
+#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
+					DV_DDR_PHY_EXT_STRBEN | \
+					(0x2 << DV_DDR_PHY_RD_LATENCY_SHIFT))
+#define CONFIG_SYS_DA850_DDR2_SDRCR	0x00000498
+
+#define CONFIG_SYS_DA850_DDR2_SDBCR2	0x00000004
+#define CONFIG_SYS_DA850_DDR2_PBBPR	0x00000020
+
+
+#define CONFIG_SYS_DA850_DDR2_SDTIMR (		\
+	(13 << DV_DDR_SDTMR1_RFC_SHIFT) |	\
+	(2 << DV_DDR_SDTMR1_RP_SHIFT) |		\
+	(2 << DV_DDR_SDTMR1_RCD_SHIFT) |	\
+	(2 << DV_DDR_SDTMR1_WR_SHIFT) |		\
+	(5 << DV_DDR_SDTMR1_RAS_SHIFT) |	\
+	(8 << DV_DDR_SDTMR1_RC_SHIFT) |		\
+	(1 << DV_DDR_SDTMR1_RRD_SHIFT) |	\
+	(1 << DV_DDR_SDTMR1_WTR_SHIFT))
+
+#define CONFIG_SYS_DA850_DDR2_SDTIMR2 (		\
+	(8 << DV_DDR_SDTMR2_RASMAX_SHIFT) |	\
+	(2 << DV_DDR_SDTMR2_XP_SHIFT) |		\
+	(0 << DV_DDR_SDTMR2_ODT_SHIFT) |	\
+	(14 << DV_DDR_SDTMR2_XSNR_SHIFT) |	\
+	(0xc7 << DV_DDR_SDTMR2_XSRD_SHIFT) |	\
+	(1 << DV_DDR_SDTMR2_RTP_SHIFT) |	\
+	(2 << DV_DDR_SDTMR2_CKE_SHIFT))
+
+#define CONFIG_SYS_DA850_DDR2_SDBCR (		\
+	(1 << DV_DDR_SDCR_DDR2EN_SHIFT) |	\
+	(1 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) |	\
+	(1 << DV_DDR_SDCR_DDREN_SHIFT) |	\
+	(1 << DV_DDR_SDCR_SDRAMEN_SHIFT) |	\
+	(1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) |	\
+	(2 << DV_DDR_SDCR_CL_SHIFT) |	\
+	(3 << DV_DDR_SDCR_IBANK_SHIFT) |	\
+	(2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
+
+#define CONFIG_SYS_DA850_CS3CFG	(DAVINCI_ABCR_WSETUP(1)	| \
+				DAVINCI_ABCR_WSTROBE(2)	| \
+				DAVINCI_ABCR_WHOLD(0)	| \
+				DAVINCI_ABCR_RSETUP(1)	| \
+				DAVINCI_ABCR_RSTROBE(2)	| \
+				DAVINCI_ABCR_RHOLD(1)	| \
+				DAVINCI_ABCR_TA(0)	| \
+				DAVINCI_ABCR_ASIZE_8BIT)
+
+
+/*
+ * Serial Driver info
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	-4	/* NS16550 register size */
+#define CONFIG_SYS_NS16550_COM1	DAVINCI_UART0_BASE /* Base address of UART0 */
+#define CONFIG_SYS_NS16550_CLK	clk_get(DAVINCI_UART2_CLKID)
+#define CONFIG_CONS_INDEX	1		/* use UART0 for console */
+#define CONFIG_BAUDRATE		115200		/* Default baud rate */
+
+/*
+ * Flash & Environment
+ */
+#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_IS_IN_NAND		/* U-Boot env in NAND Flash  */
+#define CONFIG_ENV_OFFSET		0x0 /* Block 0--not used by bootcode */
+#define CONFIG_ENV_SIZE			(128 << 10)
+#define	CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
+#define	CONFIG_SYS_NAND_PAGE_2K
+#define CONFIG_SYS_NAND_CS		3
+#define CONFIG_SYS_NAND_BASE		DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
+#define CONFIG_SYS_NAND_MASK_CLE		0x10
+#define CONFIG_SYS_NAND_MASK_ALE		0x8
+#undef CONFIG_SYS_NAND_HW_ECC
+#define CONFIG_SYS_MAX_NAND_DEVICE	1 /* Max number of NAND devices */
+#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
+#define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_SIZE	(2 << 10)
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x40000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x120000
+#define CONFIG_SYS_NAND_U_BOOT_DST	0xc1080000
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
+#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP	(CONFIG_SYS_NAND_U_BOOT_DST - \
+					CONFIG_SYS_NAND_U_BOOT_SIZE - \
+					CONFIG_SYS_MALLOC_LEN -       \
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_NAND_ECCPOS		{				\
+			6,   7,  8,  9, 10,	11, 12, 13, 14, 15,	\
+			22, 23, 24, 25, 26,	27, 28, 29, 30, 31,	\
+			38, 39, 40, 41, 42,	43, 44, 45, 46, 47,	\
+			54, 55, 56, 57, 58,	59, 60, 61, 62, 63}
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	10
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SPL_NAND_LOAD
+
+/*
+ * Network & Ethernet Configuration
+ */
+#ifdef CONFIG_DRIVER_TI_EMAC
+#define CONFIG_DRIVER_TI_EMAC_USE_RMII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT	10
+#endif
+
+/*
+ * U-Boot general configuration
+ */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOOTFILE		"uImage" /* Boot file name */
+#define CONFIG_SYS_PROMPT	"U-Boot > " /* Command Prompt */
+#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
+#define CONFIG_SYS_LOAD_ADDR	(PHYS_SDRAM_1 + 0x700000)
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+
+/*
+ * Linux Information
+ */
+#define LINUX_BOOT_PARAM_ADDR	(PHYS_SDRAM_1 + 0x100)
+#define CONFIG_HWCONFIG		/* enable hwconfig */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTDELAY	2
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"defbootargs=setenv bootargs mem=128M console=ttyS0,115200n8 " \
+		"root=/dev/mtdblock5 rw noinitrd " \
+		"rootfstype=jffs2 noinitrd\0" \
+	"hwconfig=dsp:wake=yes\0" \
+	"bootcmd=nboot kernel;run defbootargs addmtd;bootm 0xc0700000\0" \
+	"bootfile=uImage\0" \
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"	\
+	"mtddevname=uboot-env\0" \
+	"mtddevnum=0\0" \
+	"mtdids=" MTDIDS_DEFAULT "\0"				\
+	"mtdparts=" MTDPARTS_DEFAULT "\0"			\
+	"u-boot=/tftpboot/ipam390/u-boot.ais\0"			\
+	"upd_uboot=tftp c0000000 ${u-boot};nand erase.part u-boot;" \
+		"nand write c0000000 20000 ${filesize}\0"	\
+	"setbootparms=nand read c0100000 200000 400000;"	\
+		"run defbootargs addmtd;"			\
+		"spl export atags c0100000;"			\
+		"nand erase.part bootparms;"			\
+		"nand write c0000100 180000 20000\0"		\
+	"\0"
+
+/*
+ * U-Boot commands
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_MEMORY
+
+#ifdef CONFIG_CMD_BDI
+#define CONFIG_CLOCKS
+#endif
+
+#ifndef CONFIG_DRIVER_TI_EMAC
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_MII
+#undef CONFIG_CMD_PING
+#endif
+
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NAND_TRIMFFS
+
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_LZO
+#define CONFIG_RBTREE
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+
+#define MTDIDS_NAME_STR		"davinci_nand.0"
+#define MTDIDS_DEFAULT		"nand0=" MTDIDS_NAME_STR
+#define MTDPARTS_DEFAULT	"mtdparts=" MTDIDS_NAME_STR ":" \
+					"128k(u-boot-env),"	\
+					"1408k(u-boot),"	\
+					"128k(bootparms),"	\
+					"384k(factory-info),"	\
+					"4M(kernel),"	\
+					"-(rootfs)"
+
+/* defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_TEXT_BASE - \
+						CONFIG_SYS_MALLOC_LEN)
+#define CONFIG_SYS_SPL_MALLOC_SIZE	CONFIG_SYS_MALLOC_LEN
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LDSCRIPT	"board/$(BOARDDIR)/u-boot-spl-ipam390.lds"
+#define CONFIG_SPL_STACK	0x8001ff00
+#define CONFIG_SPL_TEXT_BASE	0x80000000
+#define CONFIG_SPL_MAX_SIZE	0x20000
+#define CONFIG_SPL_MAX_FOOTPRINT	32768
+
+/* additions for new relocation code, must added to all boards */
+#define CONFIG_SYS_SDRAM_BASE		0xc0000000
+
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 - \
+					GENERATED_GBL_DATA_SIZE)
+
+/* add FALCON boot mode */
+#define CONFIG_CMD_SPL
+#define CONFIG_SPL_OS_BOOT
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x00200000
+#define CONFIG_SYS_SPL_ARGS_ADDR	LINUX_BOOT_PARAM_ADDR
+#define CONFIG_CMD_SPL_NAND_OFS		0x00180000
+#define CONFIG_CMD_SPL_WRITE_SIZE	0x400
+
+/* GPIO support */
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_DA8XX_GPIO
+#define CONFIG_IPAM390_GPIO_BOOTMODE	((16 * 7) + 14)
+
+#define CONFIG_SHOW_BOOT_PROGRESS
+#define CONFIG_IPAM390_GPIO_LED_RED	((16 * 7) + 11)
+#define CONFIG_IPAM390_GPIO_LED_GREEN	((16 * 7) + 12)
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/ipek01.h b/qemu/roms/u-boot/include/configs/ipek01.h
new file mode 100644
index 000000000..41ced15c4
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/ipek01.h
@@ -0,0 +1,376 @@
+/*
+ * (C) Copyright 2006
+ * MicroSys GmbH
+ *
+ * (C) Copyright 2009
+ * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+
+#define CONFIG_MPC5200
+#define CONFIG_MPX5200		1	/* MPX5200 board */
+#define CONFIG_MPC5200_DDR	1	/* use DDR RAM */
+#define CONFIG_IPEK01           	/* Motherboard is ipek01 */
+
+#define	CONFIG_SYS_TEXT_BASE	0xfc000000
+
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33MHz */
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_SYS_CACHELINE_SIZE	32 /* For MPC5xxx CPUs */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CACHELINE_SHIFT	5  /* log base 2 of the above value */
+#endif
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
+#define CONFIG_BAUDRATE		115200	/* ... at 9600 bps */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history */
+
+/*
+ * Video configuration for LIME GDC
+ */
+#define CONFIG_VIDEO
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO_MB862xx
+#define CONFIG_VIDEO_MB862xx_ACCEL
+#define VIDEO_FB_16BPP_WORD_SWAP
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_CONSOLE_EXTRA_INFO
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(2 << 20)	/* decompressed img */
+/* Lime clock frequency */
+#define CONFIG_SYS_MB862xx_CCF	0x90000	/* geo 166MHz other 133MHz */
+/* SDRAM parameter */
+#define CONFIG_SYS_MB862xx_MMR	0x41c767e3
+#endif
+
+/*
+ * PCI Mapping:
+ * 0x40000000 - 0x4fffffff - PCI Memory
+ * 0x50000000 - 0x50ffffff - PCI IO Space
+ */
+#define CONFIG_PCI		1
+#define CONFIG_PCI_PNP		1
+#define CONFIG_PCI_SCAN_SHOW	1
+
+#define CONFIG_PCI_MEM_BUS	0x40000000
+#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE	0x10000000
+
+#define CONFIG_PCI_IO_BUS	0x50000000
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0x01000000
+
+#define CONFIG_MII		1
+#define CONFIG_EEPRO100		1
+#define CONFIG_SYS_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
+
+/* Partitions */
+#define CONFIG_DOS_PARTITION
+
+/* USB */
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_OHCI_BE_CONTROLLER
+#define CONFIG_USB_STORAGE
+
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		MPC5XXX_USB
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"mpc5200"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#ifdef CONFIG_VIDEO
+#define CONFIG_CMD_BMP		/* BMP support */
+#endif
+#define CONFIG_CMD_DATE		/* support for RTC, date/time...*/
+#define CONFIG_CMD_DHCP		/* DHCP Support */
+#define CONFIG_CMD_FAT		/* FAT support */
+#define CONFIG_CMD_I2C		/* I2C serial bus support */
+#define CONFIG_CMD_IDE		/* IDE harddisk support */
+#define CONFIG_CMD_IRQ		/* irqinfo */
+#define CONFIG_CMD_MII		/* MII support */
+#define CONFIG_CMD_PCI		/* pciinfo */
+#define CONFIG_CMD_USB		/* USB Support */
+
+#define CONFIG_SYS_LOWBOOT	1
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"consoledev=ttyPSC0\0"						\
+	"hostname=ipek01\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} "				\
+		"console=${consoledev},${baudrate}\0"			\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr} - ${fdtaddr}\0"			\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr} ${fdtaddr}\0"	\
+	"net_nfs=tftp 200000 ${bootfile}; tftp ${fdtaddr} ${fdtfile};"  \
+		"run nfsargs addip addtty;"    				\
+		 "bootm ${loadaddr} - ${fdtaddr}\0"			\
+	"rootpath=/opt/eldk/ppc_6xx\0"					\
+	"bootfile=ipek01/uImage\0"					\
+	"load=tftp 100000 ipek01/u-boot.bin\0"				\
+	"update=protect off FC000000 +60000; era FC000000 +60000; "	\
+		"cp.b 100000 FC000000 ${filesize}\0"   			\
+	"upd=run load;run update\0"					\
+	"fdtaddr=800000\0"						\
+	"loadaddr=400000\0"						\
+	"fdtfile=ipek01/ipek01.dtb\0"					\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK 	/* for 133MHz */
+/* PCI clock must be 33, because board will not boot */
+#undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2	/* for 66MHz */
+
+/*
+ * Open firmware flat tree support
+ */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+#define OF_CPU			"PowerPC,5200@0"
+#define OF_SOC			"soc5200@f0000000"
+#define OF_TBCLK		(bd->bi_busfreq / 4)
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+#define CONFIG_SYS_I2C_MODULE	2	/* Select I2C module #1 or #2 */
+
+#define CONFIG_SYS_I2C_SPEED	100000	/* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE	0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x53
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
+
+/*
+ * RTC configuration
+ */
+#define CONFIG_RTC_PCF8563
+#define CONFIG_SYS_I2C_RTC_ADDR		0x51
+
+#define CONFIG_SYS_FLASH_BASE		0xFC000000
+#define CONFIG_SYS_FLASH_SIZE		0x01000000
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + \
+					 CONFIG_SYS_MONITOR_LEN)
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1    /* max num of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	256  /* max num of sects on one chip */
+#define CONFIG_SYS_FLASH_PROTECTION  /* "Real" (hardware) sectors protection */
+
+/* use CFI flash driver */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_IS_IN_FLASH		1
+#define CONFIG_ENV_SIZE			0x10000
+#define CONFIG_ENV_SECT_SIZE		0x20000
+#define CONFIG_ENV_OVERWRITE		1
+#define CONFIG_ENV_ADDR_REDUND		(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
+
+/*
+ * Memory map
+ */
+#define CONFIG_SYS_MBAR			0xf0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR		0x80000000
+#define	CONFIG_SYS_SRAM_BASE		0xF1000000
+#define	CONFIG_SYS_SRAM_SIZE		0x00200000
+#define	CONFIG_SYS_LIME_BASE		0xE4000000
+#define	CONFIG_SYS_LIME_SIZE		0x04000000
+#define	CONFIG_SYS_FPGA_BASE		0xC0000000
+#define	CONFIG_SYS_FPGA_SIZE		0x10000000
+#define	CONFIG_SYS_MPEG_BASE		0xe2000000
+#define	CONFIG_SYS_MPEG_SIZE		0x01000000
+#define CONFIG_SYS_CF_BASE		0xe1000000
+#define CONFIG_SYS_CF_SIZE		0x01000000
+
+/* Use SRAM until RAM will be available */
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+/* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE		MPC5XXX_SRAM_SIZE
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN	(384 << 10)  /* Reserve 384 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN	(4 << 20)    /* Reserve 128 kB for malloc() */
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)    /* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC		1
+#define CONFIG_MPC5xxx_FEC_MII100
+#define CONFIG_PHY_ADDR			0x00
+
+/*
+ * GPIO configuration
+ */
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x1d556624
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+#endif
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					 sizeof(CONFIG_SYS_PROMPT) + 16)
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS		16
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1...15 MB in DRAM */
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000 /* default load address */
+
+#define CONFIG_LOOPW
+
+/*
+ * Various low-level settings
+ */
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
+
+#define CONFIG_SYS_BOOTCS_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_CS1_START		CONFIG_SYS_SRAM_BASE
+#define CONFIG_SYS_CS1_SIZE		CONFIG_SYS_SRAM_SIZE
+#define CONFIG_SYS_CS3_START		CONFIG_SYS_LIME_BASE
+#define CONFIG_SYS_CS3_SIZE		CONFIG_SYS_LIME_SIZE
+#define	CONFIG_SYS_CS6_START		CONFIG_SYS_FPGA_BASE
+#define	CONFIG_SYS_CS6_SIZE		CONFIG_SYS_FPGA_SIZE
+#define	CONFIG_SYS_CS5_START		CONFIG_SYS_CF_BASE
+#define	CONFIG_SYS_CS5_SIZE		CONFIG_SYS_CF_SIZE
+#define	CONFIG_SYS_CS7_START		CONFIG_SYS_MPEG_BASE
+#define	CONFIG_SYS_CS7_SIZE		CONFIG_SYS_MPEG_SIZE
+
+#ifdef CONFIG_SYS_PCISPEED_66
+#define CONFIG_SYS_BOOTCS_CFG		0x0006F900
+#define CONFIG_SYS_CS1_CFG		0x0004FB00
+#define CONFIG_SYS_CS2_CFG		0x0006F900
+#else
+#define CONFIG_SYS_BOOTCS_CFG		0x0002F900
+#define CONFIG_SYS_CS1_CFG		0x0001FB00
+#define CONFIG_SYS_CS2_CFG		0x0002F90C
+#endif
+
+/*
+ * Ack active, Muxed mode, AS=24 bit address, DS=32 bit data, 0
+ * waitstates, writeswap and readswap enabled
+ */
+#define CONFIG_SYS_CS3_CFG		0x00FFFB0C
+#define	CONFIG_SYS_CS6_CFG		0x00FFFB0C
+#define	CONFIG_SYS_CS7_CFG		0x4040751C
+
+#define CONFIG_SYS_CS_BURST		0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE		0x33330000
+
+#define CONFIG_SYS_RESET_ADDRESS	0xff000000
+
+/*-----------------------------------------------------------------------
+ * USB stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_USB_CLOCK		0x0001BBBB
+#define CONFIG_USB_CONFIG		0x00005000
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_IDE_PREINIT
+
+#define CONFIG_SYS_IDE_MAXBUS		1 /* max. 1 IDE bus */
+#define CONFIG_SYS_IDE_MAXDEVICE	2 /* max. 2 drives per IDE bus */
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
+
+/* Offset for data I/O */
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
+
+/* Offset for normal register accesses */
+#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers */
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)
+
+/* Interval between registers */
+#define CONFIG_SYS_ATA_STRIDE		4
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/jadecpu.h b/qemu/roms/u-boot/include/configs/jadecpu.h
new file mode 100644
index 000000000..b34e3422d
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/jadecpu.h
@@ -0,0 +1,274 @@
+/*
+ * (C) Copyright 2010
+ * Matthias Weisser <weisserm@arcor.de>
+ *
+ * Configuation settings for the jadecpu board
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MB86R0x
+#define CONFIG_MB86R0x_IOCLK	get_bus_freq(0)
+#define CONFIG_SYS_TEXT_BASE	0x10000000
+
+#define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core	*/
+
+#define CONFIG_USE_ARCH_MEMCPY
+#define CONFIG_USE_ARCH_MEMSET
+
+#define MACH_TYPE_JADECPU	2636
+
+#define CONFIG_MACH_TYPE MACH_TYPE_JADECPU
+
+/*
+ * Environment settings
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"gs_fast_boot=setenv bootdelay 5\0" \
+	"gs_slow_boot=setenv bootdelay 10\0" \
+	"bootcmd=dcache off; mw.l 0x40000000 0 1024; usb start;" \
+		"fatls usb 0; fatload usb 0 0x40000000 jadecpu-init.bin;" \
+		"bootelf 0x40000000\0" \
+	""
+
+#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG	1
+#define CONFIG_BOARD_LATE_INIT
+
+/*
+ * Compressions
+ */
+#define CONFIG_LZO
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * Serial
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE		(-4)
+#define CONFIG_SYS_NS16550_CLK			get_bus_freq(0)
+#define CONFIG_SYS_NS16550_COM1			0xfffe1000	/* UART 0 */
+#define CONFIG_SYS_NS16550_COM2			0xfff50000	/* UART 2 */
+#define CONFIG_SYS_NS16550_COM3			0xfff51000	/* UART 3 */
+#define CONFIG_SYS_NS16550_COM4			0xfff43000	/* UART 4 */
+
+#define CONFIG_CONS_INDEX	4
+
+/*
+ * Ethernet
+ */
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_BASE	0x02000000
+#define CONFIG_SMC911X_16_BIT
+
+/*
+ * Video
+ */
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_MB86R0xGDC
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE  (800*480 + 256*4 + 10*1024)
+#define VIDEO_FB_16BPP_WORD_SWAP
+#define VIDEO_KBD_INIT_FCT		0
+#define VIDEO_TSTC_FCT			serial_tstc
+#define VIDEO_GETC_FCT			serial_getc
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE	1
+#define CONFIG_BOOTP_BOOTPATH		1
+#define CONFIG_BOOTP_GATEWAY		1
+#define CONFIG_BOOTP_HOSTNAME		1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_SOURCE
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_XIMG
+
+#define CONFIG_CMD_BMP
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_CACHE
+
+#define CONFIG_SYS_HUSH_PARSER
+
+/* USB */
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_REGS_BASE       0xFFF81000
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME       "mb86r0x"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS  1
+#define CONFIG_USB_STORAGE
+#define CONFIG_DOS_PARTITION
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM		0x40000000	/* Start address of DDRRAM */
+#define PHYS_SDRAM_SIZE	0x08000000	/* 128 megs */
+
+#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM
+#define CONFIG_SYS_INIT_SP_ADDR	0x01008000
+
+/*
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_FLASH_BASE		0x10000000
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	256
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00040000)
+#define CONFIG_ENV_IS_IN_FLASH		1
+#define CONFIG_ENV_SECT_SIZE		(128 * 1024)
+#define CONFIG_ENV_SIZE		(128 * 1024)
+
+/*
+ * CFI FLASH driver setup
+ */
+#define CONFIG_SYS_FLASH_CFI		1
+#define CONFIG_FLASH_CFI_DRIVER	1
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1	/* ~10x faster */
+
+#define CONFIG_SYS_LOAD_ADDR		0x40000000	/* load address */
+
+#define CONFIG_SYS_MEMTEST_START	(PHYS_SDRAM + (512*1024))
+#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM + PHYS_SDRAM_SIZE)
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_SYS_PROMPT	"jade> "
+#define CONFIG_SYS_CBSIZE	256
+#define CONFIG_SYS_MAXARGS	16
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
+				sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP	1
+#define CONFIG_CMDLINE_EDITING	1
+
+#define CONFIG_PREBOOT  ""
+
+#define CONFIG_BOOTDELAY	5
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT "boot in %d s\n", bootdelay
+#define CONFIG_AUTOBOOT_DELAY_STR	"delaygs"
+#define CONFIG_AUTOBOOT_STOP_STR	"stopgs"
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN	(10 << 20)
+#define CONFIG_SYS_MEM_TOP_HIDE	(4 << 20)
+
+/*
+ * Clock reset generator init
+ */
+#define CONFIG_SYS_CRG_CRHA_INIT		0xffff
+#define CONFIG_SYS_CRG_CRPA_INIT		0xffff
+#define CONFIG_SYS_CRG_CRPB_INIT		0xfffe
+#define CONFIG_SYS_CRG_CRHB_INIT		0xffff
+#define CONFIG_SYS_CRG_CRAM_INIT		0xffef
+
+/*
+ * Memory controller settings
+ */
+#define CONFIG_SYS_MEMC_MCFMODE0_INIT	0x00000001	/* 16bit */
+#define CONFIG_SYS_MEMC_MCFMODE2_INIT	0x00000001	/* 16bit */
+#define CONFIG_SYS_MEMC_MCFMODE4_INIT	0x00000021	/* 16bit, Page*/
+#define CONFIG_SYS_MEMC_MCFTIM0_INIT	0x16191008
+#define CONFIG_SYS_MEMC_MCFTIM2_INIT	0x03061008
+#define CONFIG_SYS_MEMC_MCFTIM4_INIT	0x03061804
+#define CONFIG_SYS_MEMC_MCFAREA0_INIT	0x000000c0	/* 0x0c000000 1MB */
+#define CONFIG_SYS_MEMC_MCFAREA2_INIT	0x00000020	/* 0x02000000 1MB */
+#define CONFIG_SYS_MEMC_MCFAREA4_INIT	0x001f0000	/* 0x10000000 32 MB */
+
+/*
+ * DDR2 controller init settings
+ */
+#define CONFIG_SYS_DDR2_DRIMS_INIT	0x5555
+#define CONFIG_SYS_CCNT_CDCRC_INIT_1	0x00000002
+#define CONFIG_SYS_CCNT_CDCRC_INIT_2	0x00000003
+#define CONFIG_SYS_DDR2_DRIC1_INIT	0x003f
+#define CONFIG_SYS_DDR2_DRIC2_INIT	0x0000
+#define CONFIG_SYS_DDR2_DRCA_INIT	0xc124	/* 512Mbit DDR2SDRAM x 2 */
+#define CONFIG_SYS_DDR2_DRCM_INIT	0x0032
+#define CONFIG_SYS_DDR2_DRCST1_INIT	0x3418
+#define CONFIG_SYS_DDR2_DRCST2_INIT	0x6e32
+#define CONFIG_SYS_DDR2_DRCR_INIT	0x0141
+#define CONFIG_SYS_DDR2_DRCF_INIT	0x0002
+#define CONFIG_SYS_DDR2_DRASR_INIT	0x0001
+#define CONFIG_SYS_DDR2_DROBS_INIT	0x0001
+#define CONFIG_SYS_DDR2_DROABA_INIT	0x0103
+#define CONFIG_SYS_DDR2_DRIBSODT1_INIT	0x003F
+#define CONFIG_SYS_DDR2_DROS_INIT	0x0001
+
+/*
+ * DRAM init sequence
+ */
+
+/* PALL Command */
+#define CONFIG_SYS_DDR2_INIT_DRIC1_1	0x0017
+#define CONFIG_SYS_DDR2_INIT_DRIC2_1	0x0400
+
+/* EMR(2) command */
+#define CONFIG_SYS_DDR2_INIT_DRIC1_2	0x0006
+#define CONFIG_SYS_DDR2_INIT_DRIC2_2	0x0000
+
+/* EMR(3) command */
+#define CONFIG_SYS_DDR2_INIT_DRIC1_3	0x0007
+#define CONFIG_SYS_DDR2_INIT_DRIC2_3	0x0000
+
+/* EMR(1) command */
+#define CONFIG_SYS_DDR2_INIT_DRIC1_4	0x0005
+#define CONFIG_SYS_DDR2_INIT_DRIC2_4	0x0000
+
+/* MRS command */
+#define CONFIG_SYS_DDR2_INIT_DRIC1_5	0x0004
+#define CONFIG_SYS_DDR2_INIT_DRIC2_5	0x0532
+
+/* PALL command */
+#define CONFIG_SYS_DDR2_INIT_DRIC1_6	0x0017
+#define CONFIG_SYS_DDR2_INIT_DRIC2_6	0x0400
+
+/* REF command 1 */
+#define CONFIG_SYS_DDR2_INIT_DRIC1_7	0x000f
+#define CONFIG_SYS_DDR2_INIT_DRIC2_7	0x0000
+
+/* MRS command */
+#define CONFIG_SYS_DDR2_INIT_DRIC1_8	0x0004
+#define CONFIG_SYS_DDR2_INIT_DRIC2_8	0x0432
+
+/* EMR(1) command */
+#define CONFIG_SYS_DDR2_INIT_DRIC1_9	0x0005
+#define CONFIG_SYS_DDR2_INIT_DRIC2_9	0x0380
+
+/* EMR(1) command */
+#define CONFIG_SYS_DDR2_INIT_DRIC1_10	0x0005
+#define CONFIG_SYS_DDR2_INIT_DRIC2_10	0x0002
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/jetson-tk1.h b/qemu/roms/u-boot/include/configs/jetson-tk1.h
new file mode 100644
index 000000000..6255750c3
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/jetson-tk1.h
@@ -0,0 +1,79 @@
+/*
+ * (C) Copyright 2013-2014
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+
+#include "tegra124-common.h"
+
+/* Enable fdt support for Jetson TK1. Flash the image in u-boot-dtb.bin */
+#define CONFIG_DEFAULT_DEVICE_TREE	tegra124-jetson-tk1
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
+/* High-level configuration options */
+#define V_PROMPT			"Tegra124 (Jetson TK1) # "
+#define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Jetson TK1"
+
+/* Board-specific serial config */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_TEGRA_ENABLE_UARTD
+#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* I2C */
+#define CONFIG_SYS_I2C_TEGRA
+#define CONFIG_SYS_I2C_INIT_BOARD
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_MAX_I2C_BUS		TEGRA_I2C_NUM_CONTROLLERS
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_TEGRA_MMC
+#define CONFIG_CMD_MMC
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART		2
+
+/* SPI */
+#define CONFIG_TEGRA114_SPI		/* Compatible w/ Tegra114 SPI */
+#define CONFIG_TEGRA114_SPI_CTRLS	6
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
+#define CONFIG_SF_DEFAULT_SPEED		24000000
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH_SIZE		(4 << 20)
+
+/* USB Host support */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_TEGRA
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB
+
+/* USB networking support */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+
+/* General networking support */
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/jornada.h b/qemu/roms/u-boot/include/configs/jornada.h
new file mode 100644
index 000000000..7e18d8e7b
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/jornada.h
@@ -0,0 +1,132 @@
+/*
+ * Copyright 2010 (C)
+ * Kristoffer Ericson <kristoffer.ericson@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_SA1110			1	/* This is an SA110 CPU */
+#define CONFIG_JORNADA700		1	/* on an HP Jornada 700 series */
+#define CONFIG_SYS_FLASH_PROTECTION	1
+
+#define CONFIG_SYS_TEXT_BASE		0xC1F00000
+
+/* we will never enable dcache, because we have to setup MMU first */
+#define CONFIG_SYS_DCACHE_OFF
+
+/* Console setting */
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs      */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SA1100_SERIAL	1
+#define CONFIG_SERIAL3		1	/* we use serial 3 */
+#define CONFIG_BAUDRATE	19200
+#define CONFIG_LOADS_ECHO	1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_JFFS2
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_MISC
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
+
+#define CONFIG_BOOTDELAY	5
+#define CONFIG_BOOTARGS	"root=/dev/hda1 console=ttySA0,19200n8 console=tty1"
+#define CONFIG_BOOTCOMMAND	"run boot_kernel"
+#define CONFIG_SYS_AUTOLOAD	"n"	/* No autoload */
+#define CONFIG_SYS_LOAD_ADDR	0xc0000000
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP	/* undef to save memory */
+#define CONFIG_SYS_PROMPT		"HP Jornada# "
+#define CONFIG_SYS_CBSIZE		256	/* console buffsize */
+#define CONFIG_SYS_PBSIZE		(256+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		256	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_MEMTEST_START	0xc0040000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0xc2000000	/* 4..128 MB */
+#define CONFIG_SYS_CPUSPEED		0x0a /* core clock 206MHz */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 19200, 38400, 57600, 115200 }
+
+#define CONFIG_SYS_FLASH_CFI		1
+#define CONFIG_FLASH_CFI_DRIVER	1
+#define CONFIG_FLASH_CFI_WIDTH		FLASH_CFI_32BIT
+#define CONFIG_SYS_FLASH_BASE		0x00000000
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(4096)
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(4096)
+#define CONFIG_SYS_FLASH_INCREMENT	0x02000000
+#define PHYS_FLASH_1			0x00000000	/* starts at 0x0 */
+#define PHYS_FLASH_SIZE		0x04000000	/* 64MB */
+#define PHYS_FLASH_SECT_SIZE		0x00040000	/* 256KB Sectors */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	260
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ PHYS_FLASH_1 }
+#define CONFIG_SYS_FLASH_EMPTY_INFO	1
+#define CONFIG_SYS_MONITOR_LEN		0x00040000
+#define CONFIG_SYS_MONITOR_BASE	0x00000000
+#define CONFIG_FLASH_SHOW_PROGRESS	1
+
+/* Environment */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_ADDR		0x00040000
+#define CONFIG_ENV_OFFSET	0x00040000
+#define CONFIG_ENV_SIZE		0x00040000
+#define CONFIG_ENV_SECT_SIZE	0x00040000
+#define CONFIG_ENV_OVERWRITE	1
+
+/*
+  Monitor -     0x00000000 - 0x00040000 (256kb)
+  Environment - 0x00040000 - 0x00080000 (256kb)
+  Kernel -      0x00080000 - 0x00380000 (3mb)
+  Rootfs -      0x00380000 - 0x........ (rest)
+*/
+
+#define CONFIG_NR_DRAM_BANKS		2
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_INTRAM_BASE		INTERNAL_SRAM_BASE
+#define CONFIG_SYS_INTRAM_SIZE		INTERNAL_SRAM_SIZE
+#define CONFIG_SYS_INIT_SP_ADDR	0x0
+#define PHYS_SDRAM_1			0xc0000000	/* SDRAM Bank #1 */
+#define PHYS_SDRAM_2			0xc4000000	/* SDRAM Bank #2 */
+#define PHYS_SDRAM_1_SIZE		0x04000000	/* 64 MB */
+#define PHYS_SDRAM_2_SIZE		0x04000000	/* 64 MB */
+
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_FLASH_CFI_MTD
+#define MTDIDS_DEFAULT		"nor0=jornada7xx-0"
+#define MTDPARTS_DEFAULT	"mtdparts=jornada7xx-0:256k(u-boot),256k(env),"\
+		"3m(kernel),-(user);"
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"flash_kernel=protect off all; "				\
+	"erase 00080000 0037ffff;cp.b c0000000 00080000 00300000;\0"	\
+	"flash_uboot=protect off all; "					\
+	"erase 00000000 0003ffff;cp.b c0000000 00000000 00040000;\0"	\
+	"boot_kernel=cp.b 00080000 c0000000 00300000;bootm;\0"
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/jupiter.h b/qemu/roms/u-boot/include/configs/jupiter.h
new file mode 100644
index 000000000..7dfaa221e
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/jupiter.h
@@ -0,0 +1,285 @@
+/*
+ * (C) Copyright 2007
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5200		1	/* This is an MPC5200 CPU */
+#define CONFIG_JUPITER		1	/* ... on Jupiter board */
+
+/*
+ * Valid values for CONFIG_SYS_TEXT_BASE are:
+ * 0xFFF00000	boot high (standard configuration)
+ * 0x00100000	boot from RAM (for testing only)
+ */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xFFF00000
+#endif
+
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
+
+#define CONFIG_BOARD_EARLY_INIT_R	1
+#define CONFIG_BOARD_EARLY_INIT_F	1
+
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
+#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*
+ * PCI Mapping:
+ * 0x40000000 - 0x4fffffff - PCI Memory
+ * 0x50000000 - 0x50ffffff - PCI IO Space
+ */
+/*#define CONFIG_PCI		*/
+
+#if defined(CONFIG_PCI)
+#define CONFIG_PCI_PNP		1
+#define CONFIG_PCI_SCAN_SHOW	1
+#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1
+
+#define CONFIG_PCI_MEM_BUS	0x40000000
+#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE	0x10000000
+
+#define CONFIG_PCI_IO_BUS	0x50000000
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0x01000000
+#endif
+
+#define CONFIG_SYS_XLB_PIPELINING	1
+
+#define CONFIG_MII		1
+#define CONFIG_SYS_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
+#if defined(CONFIG_PCI)
+#define CODFIG_CMD_PCI
+#endif
+
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip addcons;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"addcons=setenv bootargs ${bootargs} console=${contyp},"	\
+		"${baudrate}\0"						\
+	"contyp=ttyS0\0"						\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcons;"	\
+		"bootm\0"						\
+	"rootpath=/opt/eldk/ppc_6xx\0"					\
+	"bootfile=/tftpboot/jupiter/uImage\0"				\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#undef CONFIG_SYS_IPBSPEED_133			/* define for 133MHz speed */
+
+#if 0
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+#define OF_CPU			"PowerPC,5200@0"
+#define OF_SOC			"soc5200@f0000000"
+#define OF_TBCLK		(bd->bi_busfreq / 8)
+#define OF_STDOUT_PATH		"/soc5200@f0000000/serial@2000"
+#endif
+
+#if 0
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #1 or #2 */
+
+#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	70
+#endif
+
+/*
+ * Flash configuration
+ */
+#define CONFIG_SYS_FLASH_BASE		0xFF000000
+#define CONFIG_SYS_FLASH_SIZE		0x01000000
+
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
+
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_TEXT_BASE + 0x40000) /* third sector */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks */
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
+#define CONFIG_SYS_UPDATE_FLASH_SIZE	1
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_SIZE		0x20000
+#define CONFIG_ENV_SECT_SIZE	0x20000
+#define CONFIG_ENV_OVERWRITE	1
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+/*
+ * Memory map
+ */
+#define CONFIG_SYS_MBAR		0xF0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
+
+/* Use SRAM until RAM will be available */
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */
+
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC	1
+#define CONFIG_MPC5xxx_FEC_MII100
+/*
+ * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
+ */
+/* #define CONFIG_MPC5xxx_FEC_MII10 */
+#define CONFIG_PHY_ADDR		0x00
+
+/*
+ * GPIO configuration
+ */
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x10000004
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+#define CONFIG_SYS_ALT_MEMTEST		1
+
+#define CONFIG_SYS_LOAD_ADDR		0x200000	/* default load address */
+
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*
+ * Various low-level settings
+ */
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
+
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_CFG		0x00047801
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
+
+#define CONFIG_SYS_CS_BURST		0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE	0x33333333
+
+#define CONFIG_SYS_RESET_ADDRESS	0xff000000
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/k2hk_evm.h b/qemu/roms/u-boot/include/configs/k2hk_evm.h
new file mode 100644
index 000000000..9bb8f342b
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/k2hk_evm.h
@@ -0,0 +1,256 @@
+/*
+ * Configuration header file for TI's k2hk-evm
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __CONFIG_K2HK_EVM_H
+#define __CONFIG_K2HK_EVM_H
+
+/* Platform type */
+#define CONFIG_SOC_K2HK
+#define CONFIG_K2HK_EVM
+
+/* U-Boot Build Configuration */
+#define CONFIG_SKIP_LOWLEVEL_INIT       /* U-Boot is a 2nd stage loader */
+#define CONFIG_SYS_NO_FLASH             /* that is, no *NOR* flash */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_SYS_THUMB_BUILD
+
+/* SoC Configuration */
+#define CONFIG_ARMV7
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_SYS_ARCH_TIMER
+#define CONFIG_SYS_HZ                   1000
+#define CONFIG_SYS_TEXT_BASE            0x0c001000
+#define CONFIG_SPL_TARGET               "u-boot-spi.gph"
+#define CONFIG_SYS_DCACHE_OFF
+
+/* Memory Configuration */
+#define CONFIG_NR_DRAM_BANKS            2
+#define CONFIG_SYS_SDRAM_BASE           0x80000000
+#define CONFIG_SYS_LPAE_SDRAM_BASE      0x800000000
+#define CONFIG_MAX_RAM_BANK_SIZE        (2 << 30)       /* 2GB */
+#define CONFIG_STACKSIZE                (512 << 10)     /* 512 KiB */
+#define CONFIG_SYS_MALLOC_LEN           (4 << 20)       /* 4 MiB */
+#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_TEXT_BASE - \
+					 GENERATED_GBL_DATA_SIZE)
+
+/* SPL SPI Loader Configuration */
+#define CONFIG_SPL_TEXT_BASE            0x0c200000
+#define CONFIG_SPL_PAD_TO               65536
+#define CONFIG_SPL_MAX_SIZE             (CONFIG_SPL_PAD_TO - 8)
+#define CONFIG_SPL_BSS_START_ADDR       (CONFIG_SPL_TEXT_BASE + \
+					 CONFIG_SPL_MAX_SIZE)
+#define CONFIG_SPL_BSS_MAX_SIZE         (32 * 1024)
+#define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SPL_BSS_START_ADDR + \
+					 CONFIG_SPL_BSS_MAX_SIZE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE      (32 * 1024)
+#define CONFIG_SPL_STACK_SIZE           (8 * 1024)
+#define CONFIG_SPL_STACK                (CONFIG_SYS_SPL_MALLOC_START + \
+					 CONFIG_SYS_SPL_MALLOC_SIZE + \
+					 CONFIG_SPL_STACK_SIZE - 4)
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_BUS              0
+#define CONFIG_SPL_SPI_CS               0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS      CONFIG_SPL_PAD_TO
+#define CONFIG_SPL_FRAMEWORK
+
+/* UART Configuration */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_NS16550_REG_SIZE     -4
+#define CONFIG_SYS_NS16550_COM1         K2HK_UART0_BASE
+#define CONFIG_SYS_NS16550_CLK          clk_get_rate(K2HK_CLK1_6)
+#define CONFIG_CONS_INDEX               1
+#define CONFIG_BAUDRATE                 115200
+
+/* SPI Configuration */
+#define CONFIG_SPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_DAVINCI_SPI
+#define CONFIG_SYS_SPI0
+#define CONFIG_SYS_SPI_BASE             K2HK_SPI_BASE
+#define CONFIG_SYS_SPI0_NUM_CS          4
+#define CONFIG_SYS_SPI1
+#define CONFIG_SYS_SPI1_BASE            K2HK_SPI1_BASE
+#define CONFIG_SYS_SPI1_NUM_CS          4
+#define CONFIG_SYS_SPI2
+#define CONFIG_SYS_SPI2_NUM_CS          4
+#define CONFIG_SYS_SPI2_BASE            K2HK_SPI2_BASE
+#define CONFIG_CMD_SPI
+#define CONFIG_SYS_SPI_CLK              clk_get_rate(K2HK_LPSC_EMIF25_SPI)
+#define CONFIG_SF_DEFAULT_SPEED         30000000
+#define CONFIG_ENV_SPI_MAX_HZ           CONFIG_SF_DEFAULT_SPEED
+
+/* I2C Configuration */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DAVINCI
+#define CONFIG_SYS_DAVINCI_I2C_SPEED    100000
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE    0x10 /* SMBus host address */
+#define CONFIG_SYS_DAVINCI_I2C_SPEED1   100000
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE1   0x10 /* SMBus host address */
+#define CONFIG_SYS_DAVINCI_I2C_SPEED2   100000
+#define CONFIG_SYS_DAVINCI_I2C_SLAVE2   0x10 /* SMBus host address */
+#define I2C_BUS_MAX                     3
+
+/* EEPROM definitions */
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN         2
+#define CONFIG_SYS_I2C_EEPROM_ADDR             0x50
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS      6
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS  20
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+
+/* Network Configuration */
+#define CONFIG_DRIVER_TI_KEYSTONE_NET
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT                 32
+#define CONFIG_NET_MULTI
+#define CONFIG_GET_LINK_STATUS_ATTEMPTS        5
+#define CONFIG_SYS_SGMII_REFCLK_MHZ            312
+#define CONFIG_SYS_SGMII_LINERATE_MHZ          1250
+#define CONFIG_SYS_SGMII_RATESCALE             2
+
+/* NAND Configuration */
+#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NAND_CS                     2
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
+#define CONFIG_SYS_NAND_PAGE_2K
+
+#define CONFIG_SYS_NAND_LARGEPAGE
+#define CONFIG_SYS_NAND_BASE_LIST       { 0x30000000, }
+#define CONFIG_SYS_MAX_NAND_DEVICE      1
+#define CONFIG_SYS_NAND_MAX_CHIPS       1
+#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
+#define CONFIG_ENV_SIZE                 (256 << 10)  /* 256 KiB */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET               0x100000
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define MTDPARTS_DEFAULT                "mtdparts=davinci_nand.0:" \
+					"1024k(bootloader)ro,512k(params)ro," \
+					"-(ubifs)"
+/* U-Boot command configuration */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_EEPROM
+
+/* U-Boot general configuration */
+#define CONFIG_SYS_PROMPT               "K2HK EVM # "
+#define CONFIG_SYS_CBSIZE               1024
+#define CONFIG_SYS_PBSIZE		2048
+#define CONFIG_SYS_MAXARGS              16
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_TIMESTAMP
+
+#define CONFIG_BOOTDELAY                3
+#define CONFIG_BOOTFILE                 "uImage"
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"boot=ramfs\0"							\
+	"tftp_root=/\0"							\
+	"nfs_root=/export\0"						\
+	"mem_lpae=1\0"							\
+	"mem_reserve=512M\0"						\
+	"addr_fdt=0x87000000\0"						\
+	"addr_kern=0x88000000\0"					\
+	"addr_mon=0x0c5f0000\0"						\
+	"addr_uboot=0x87000000\0"					\
+	"addr_fs=0x82000000\0"						\
+	"addr_ubi=0x82000000\0"						\
+	"fdt_high=0xffffffff\0"						\
+	"name_fdt=uImage-k2hk-evm.dtb\0"				\
+	"name_fs=arago-console-image.cpio.gz\0"				\
+	"name_kern=uImage-keystone-evm.bin\0"				\
+	"name_mon=skern-keystone-evm.bin\0"				\
+	"name_uboot=u-boot-spi-keystone-evm.gph\0"			\
+	"name_ubi=keystone-evm-ubifs.ubi\0"				\
+	"run_mon=mon_install ${addr_mon}\0"				\
+	"run_kern=bootm ${addr_kern} - ${addr_fdt}\0"			\
+	"init_net=run args_all args_net\0"				\
+	"init_ubi=run args_all args_ubi; "				\
+		"ubi part ubifs; ubifsmount boot\0"			\
+	"get_fdt_net=dhcp ${addr_fdt} ${tftp_root}/${name_fdt}\0"	\
+	"get_fdt_ubi=ubifsload ${addr_fdt} ${name_fdt}\0"		\
+	"get_kern_net=dhcp ${addr_kern} ${tftp_root}/${name_kern}\0"	\
+	"get_kern_ubi=ubifsload ${addr_kern} ${name_kern}\0"		\
+	"get_mon_net=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0"	\
+	"get_mon_ubi=ubifsload ${addr_mon} ${name_mon}\0"		\
+	"get_uboot_net=dhcp ${addr_uboot} ${tftp_root}/${name_uboot}\0"	\
+	"burn_uboot=sf probe; sf erase 0 0x100000; "			\
+		"sf write ${addr_uboot} 0 ${filesize}\0"		\
+	"args_all=setenv bootargs console=ttyS0,115200n8 rootwait=1\0"	\
+	"args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "	\
+		"root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0"	\
+	"args_net=setenv bootargs ${bootargs} rootfstype=nfs "		\
+		"root=/dev/nfs rw nfsroot=${serverip}:${nfs_root},"	\
+		"${nfs_options} ip=dhcp\0"				\
+	"nfs_options=v3,tcp,rsize=4096,wsize=4096\0"			\
+	"get_fdt_ramfs=dhcp ${addr_fdt} ${tftp_root}/${name_fdt}\0"	\
+	"get_kern_ramfs=dhcp ${addr_kern} ${tftp_root}/${name_kern}\0"	\
+	"get_mon_ramfs=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0"	\
+	"get_fs_ramfs=dhcp ${addr_fs} ${tftp_root}/${name_fs}\0"	\
+	"get_ubi_net=dhcp ${addr_ubi} ${tftp_root}/${name_ubi}\0"	\
+	"burn_ubi=nand erase.part ubifs; "				\
+		"nand write ${addr_ubi} ubifs ${filesize}\0"		\
+	"init_ramfs=run args_all args_ramfs get_fs_ramfs\0"		\
+	"args_ramfs=setenv bootargs ${bootargs} earlyprintk "		\
+		"rdinit=/sbin/init rw root=/dev/ram0 "			\
+		"initrd=0x802000000,9M\0"				\
+	"no_post=1\0"							\
+	"mtdparts=mtdparts=davinci_nand.0:"				\
+		"1024k(bootloader)ro,512k(params)ro,522752k(ubifs)\0"
+#define CONFIG_BOOTCOMMAND						\
+	"run init_${boot} get_fdt_${boot} get_mon_${boot} "		\
+		"get_kern_${boot} run_mon run_kern"
+#define CONFIG_BOOTARGS							\
+
+/* Linux interfacing */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_OF_LIBFDT                1
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_SYS_BARGSIZE             1024
+#define CONFIG_SYS_LOAD_ADDR            (CONFIG_SYS_SDRAM_BASE + 0x08000000)
+
+#define CONFIG_SUPPORT_RAW_INITRD
+
+/* we may include files below only after all above definitions */
+#include <asm/arch/hardware.h>
+#include <asm/arch/clock.h>
+#define CONFIG_SYS_HZ_CLOCK             clk_get_rate(K2HK_CLK1_6)
+
+#endif /* __CONFIG_K2HK_EVM_H */
diff --git a/qemu/roms/u-boot/include/configs/katmai.h b/qemu/roms/u-boot/include/configs/katmai.h
new file mode 100644
index 000000000..fa72eb02f
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/katmai.h
@@ -0,0 +1,324 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/************************************************************************
+ * katmai.h - configuration for AMCC Katmai (440SPe)
+ ***********************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_KATMAI			1	/* Board is Katmai	*/
+#define CONFIG_440			1	/* ... PPC440 family	*/
+#define CONFIG_440SPE			1	/* Specifc SPe support	*/
+#define CONFIG_440SPE_REVA		1	/* Support old Rev A.	*/
+#define CONFIG_SYS_CLK_FREQ	33333333	/* external freq to pll	*/
+#define CONFIG_SYS_4xx_RESET_TYPE	0x2	/* use chip reset on this board	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFA0000
+
+/*
+ * Enable this board for more than 2GB of SDRAM
+ */
+#define CONFIG_PHYS_64BIT
+#define	CONFIG_VERY_BIG_RAM
+
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME		katmai
+#include "amcc-common.h"
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_pre_init		*/
+#undef  CONFIG_SHOW_BOOT_PROGRESS
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_FLASH_BASE		0xff000000	/* start of FLASH	*/
+#define CONFIG_SYS_ISRAM_BASE		0x90000000	/* internal SRAM	*/
+
+#define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped PCI memory	*/
+#define CONFIG_SYS_PCI_BASE		0xd0000000	/* internal PCI regs	*/
+#define CONFIG_SYS_PCI_TARGBASE	CONFIG_SYS_PCI_MEMBASE
+
+#define CONFIG_SYS_PCIE_MEMBASE	0xb0000000	/* mapped PCIe memory	*/
+#define CONFIG_SYS_PCIE_MEMSIZE	0x08000000	/* smallest incr for PCIe port */
+#define CONFIG_SYS_PCIE_BASE		0xe0000000	/* PCIe UTL regs */
+
+#define CONFIG_SYS_PCIE0_CFGBASE	0xc0000000
+#define CONFIG_SYS_PCIE1_CFGBASE	0xc1000000
+#define CONFIG_SYS_PCIE2_CFGBASE	0xc2000000
+#define CONFIG_SYS_PCIE0_XCFGBASE	0xc3000000
+#define CONFIG_SYS_PCIE1_XCFGBASE	0xc3001000
+#define CONFIG_SYS_PCIE2_XCFGBASE	0xc3002000
+
+/* base address of inbound PCIe window */
+#define CONFIG_SYS_PCIE_INBOUND_BASE	0x0000000000000000ULL
+
+/* System RAM mapped to PCI space */
+#define CONFIG_PCI_SYS_MEM_BUS	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_PHYS	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_SIZE	(1024 * 1024 * 1024)
+
+#define CONFIG_SYS_ACE_BASE		0xfe000000	/* Xilinx ACE controller - Compact Flash */
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in internal SRAM)
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_TEMP_STACK_OCM	1
+#define CONFIG_SYS_OCM_DATA_ADDR	CONFIG_SYS_ISRAM_BASE
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_ISRAM_BASE	/* Initial RAM address	*/
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000		/* Size of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#undef CONFIG_SYS_EXT_SERIAL_CLOCK
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CONFIG_SPD_EEPROM	1	/* Use SPD EEPROM for setup	*/
+#define SPD_EEPROM_ADDRESS	{0x51, 0x52}	/* SPD i2c spd addresses*/
+#define CONFIG_DDR_ECC		1	/* with ECC support		*/
+#define CONFIG_DDR_RQDC_FIXED	0x80000038 /* optimal value found by GDA*/
+#undef  CONFIG_STRESS
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		100000
+
+#define CONFIG_SYS_SPD_BUS_NUM		0	/* The I2C bus for SPD		*/
+
+#define IIC0_BOOTPROM_ADDR	0x50
+#define IIC0_ALT_BOOTPROM_ADDR	0x54
+
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR	(0x50)
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+/* I2C bootstrap EEPROM */
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR	0x50
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET	0
+#define CONFIG_4xx_CONFIG_BLOCKSIZE		8
+
+/* I2C RTC */
+#define CONFIG_RTC_M41T11	1
+#define CONFIG_SYS_RTC_BUS_NUM		1	/* The I2C bus for RTC		*/
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR	1900	/* play along with linux	*/
+
+/* I2C DTT */
+#define CONFIG_DTT_ADM1021	1	/* ADM1021 temp sensor support	*/
+#define CONFIG_SYS_DTT_BUS_NUM		1	/* The I2C bus for DTT		*/
+/*
+ * standard dtt sensor configuration - bottom bit will determine local or
+ * remote sensor of the ADM1021, the rest determines index into
+ * CONFIG_SYS_DTT_ADM1021 array below.
+ */
+#define CONFIG_DTT_SENSORS	{ 0, 1 }
+
+/*
+ * ADM1021 temp sensor configuration (see dtt/adm1021.c for details).
+ * there will be one entry in this array for each two (dummy) sensors in
+ * CONFIG_DTT_SENSORS.
+ *
+ * For Katmai board:
+ * - only one ADM1021
+ * - i2c addr 0x18
+ * - conversion rate 0x02 = 0.25 conversions/second
+ * - ALERT ouput disabled
+ * - local temp sensor enabled, min set to 0 deg, max set to 85 deg
+ * - remote temp sensor enabled, min set to 0 deg, max set to 85 deg
+ */
+#define CONFIG_SYS_DTT_ADM1021		{ { 0x18, 0x02, 0, 1, 0, 85, 1, 0, 58} }
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+#define	CONFIG_ENV_IS_IN_FLASH	1	/* Environment uses flash	*/
+
+/*
+ * Default environment variables
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_AMCC_DEF_ENV						\
+	CONFIG_AMCC_DEF_ENV_POWERPC					\
+	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
+	"kernel_addr=ff000000\0"					\
+	"fdt_addr=ff1e0000\0"						\
+	"ramdisk_addr=ff200000\0"					\
+	"pciconfighost=1\0"						\
+	"pcie_mode=RP:RP:RP\0"						\
+	""
+
+/*
+ * Commands additional to the ones defined in amcc-common.h
+ */
+#define CONFIG_CMD_CHIP_CONFIG
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ECCTEST
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
+
+#define	CONFIG_IBM_EMAC4_V4	1	/* 440SPe has this EMAC version	*/
+#define CONFIG_PHY_ADDR		1	/* PHY address, See schematics	*/
+#define CONFIG_HAS_ETH0
+#define CONFIG_PHY_RESET        1	/* reset phy upon startup	*/
+#define CONFIG_PHY_RESET_DELAY	1000
+#define CONFIG_CIS8201_PHY	1	/* Enable 'special' RGMII mode for Cicada phy */
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+
+#define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_MAX_FLASH_BANKS     1		    /* number of banks	    */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024		    /* sectors per device   */
+
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* size of one complete sector	*/
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
+#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+/* General PCI */
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_PNP		1	/* do pci plug-and-play		*/
+#define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup	*/
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE
+
+/* Board-specific PCI */
+#define CONFIG_SYS_PCI_TARGET_INIT		/* let board init pci target    */
+#undef	CONFIG_SYS_PCI_MASTER_INIT
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014	/* IBM				*/
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever			*/
+/* #define CONFIG_SYS_PCI_SUBSYS_ID	CONFIG_SYS_PCI_SUBSYS_DEVICEID */
+
+/*
+ *  NETWORK Support (PCI):
+ */
+/* Support for Intel 82557/82559/82559ER chips. */
+#define CONFIG_EEPRO100
+
+/*-----------------------------------------------------------------------
+ * Xilinx System ACE support
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYSTEMACE	1	/* Enable SystemACE support	*/
+#define CONFIG_SYS_SYSTEMACE_WIDTH	16	/* Data bus width is 16		*/
+#define CONFIG_SYS_SYSTEMACE_BASE	CONFIG_SYS_ACE_BASE
+#define CONFIG_DOS_PARTITION	1
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ *----------------------------------------------------------------------*/
+
+/* Memory Bank 0 (Flash) initialization					*/
+#define CONFIG_SYS_EBC_PB0AP		(EBC_BXAP_BME_DISABLED      |		\
+				 EBC_BXAP_TWT_ENCODE(7)     |		\
+				 EBC_BXAP_BCE_DISABLE       |		\
+				 EBC_BXAP_BCT_2TRANS        |		\
+				 EBC_BXAP_CSN_ENCODE(0)     |		\
+				 EBC_BXAP_OEN_ENCODE(0)     |		\
+				 EBC_BXAP_WBN_ENCODE(0)     |		\
+				 EBC_BXAP_WBF_ENCODE(0)     |		\
+				 EBC_BXAP_TH_ENCODE(0)      |		\
+				 EBC_BXAP_RE_DISABLED       |		\
+				 EBC_BXAP_SOR_DELAYED       |		\
+				 EBC_BXAP_BEM_WRITEONLY     |		\
+				 EBC_BXAP_PEN_DISABLED)
+#define CONFIG_SYS_EBC_PB0CR		(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |	\
+				 EBC_BXCR_BS_16MB                    |	\
+				 EBC_BXCR_BU_RW                      |	\
+				 EBC_BXCR_BW_16BIT)
+
+/* Memory Bank 1 (Xilinx System ACE controller) initialization		*/
+#define CONFIG_SYS_EBC_PB1AP		(EBC_BXAP_BME_DISABLED      |		\
+				 EBC_BXAP_TWT_ENCODE(4)     |		\
+				 EBC_BXAP_BCE_DISABLE       |		\
+				 EBC_BXAP_BCT_2TRANS        |		\
+				 EBC_BXAP_CSN_ENCODE(0)     |		\
+				 EBC_BXAP_OEN_ENCODE(0)     |		\
+				 EBC_BXAP_WBN_ENCODE(0)     |		\
+				 EBC_BXAP_WBF_ENCODE(0)     |		\
+				 EBC_BXAP_TH_ENCODE(0)      |		\
+				 EBC_BXAP_RE_DISABLED       |		\
+				 EBC_BXAP_SOR_NONDELAYED    |		\
+				 EBC_BXAP_BEM_WRITEONLY     |		\
+				 EBC_BXAP_PEN_DISABLED)
+#define CONFIG_SYS_EBC_PB1CR		(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_ACE_BASE)  |	\
+				 EBC_BXCR_BS_1MB                    |	\
+				 EBC_BXCR_BU_RW                     |	\
+				 EBC_BXCR_BW_16BIT)
+
+/*-------------------------------------------------------------------------
+ * Initialize EBC CONFIG -
+ * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
+ * default value : 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
+ *-------------------------------------------------------------------------*/
+#define CONFIG_SYS_EBC_CFG		(EBC_CFG_LE_UNLOCK    |	\
+				 EBC_CFG_PTD_ENABLE   |	\
+				 EBC_CFG_RTC_16PERCLK | \
+				 EBC_CFG_ATC_PREVIOUS | \
+				 EBC_CFG_DTC_PREVIOUS | \
+				 EBC_CFG_CTC_PREVIOUS | \
+				 EBC_CFG_OEO_PREVIOUS | \
+				 EBC_CFG_EMC_DEFAULT  |	\
+				 EBC_CFG_PME_DISABLE  |	\
+				 EBC_CFG_PR_16)
+
+/*-----------------------------------------------------------------------
+ * GPIO Setup
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_GPIO_PCIE_PRESENT0	17
+#define CONFIG_SYS_GPIO_PCIE_PRESENT1	21
+#define CONFIG_SYS_GPIO_PCIE_PRESENT2	23
+#define CONFIG_SYS_GPIO_RS232_FORCEOFF	30
+
+#define CONFIG_SYS_PFC0		(GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0) | \
+				 GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1) | \
+				 GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2) | \
+				 GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF))
+#define CONFIG_SYS_GPIO_OR		GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
+#define CONFIG_SYS_GPIO_TCR		GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
+#define CONFIG_SYS_GPIO_ODR		0
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/kilauea.h b/qemu/roms/u-boot/include/configs/kilauea.h
new file mode 100644
index 000000000..1990b2df1
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/kilauea.h
@@ -0,0 +1,534 @@
+/*
+ * Copyright (c) 2008 Nuovation System Designs, LLC
+ *   Grant Erickson <gerickson@nuovations.com>
+ *
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/************************************************************************
+ * kilauea.h - configuration for AMCC Kilauea (405EX)
+ ***********************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_KILAUEA		1		/* Board is Kilauea	*/
+#define CONFIG_405EX		1		/* Specifc 405EX support*/
+#define CONFIG_SYS_CLK_FREQ	33333333	/* ext frequency to pll	*/
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xFFFA0000
+#endif
+
+/*
+ * CHIP_21 errata - you must set this to match your exact CPU, else your
+ * board will not boot.  DO NOT enable this unless you have JTAG available
+ * for recovery, in the event you get it wrong.
+ *
+ * Kilauea uses the 405EX, while Haleakala uses the 405EXr.  Either board
+ * may be equipped for security or not.  You must look at the CPU part
+ * number to be sure what you have.
+ */
+/* #define CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY */
+/* #define CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY */
+/* #define CONFIG_SYS_4xx_CHIP_21_405EXr_NO_SECURITY */
+/* #define CONFIG_SYS_4xx_CHIP_21_405EXr_SECURITY */
+
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME		kilauea
+#include "amcc-common.h"
+
+#define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_early_init_f */
+#define CONFIG_MISC_INIT_R	1		/* Call misc_init_r	*/
+#define CONFIG_BOARD_TYPES
+#define CONFIG_BOARD_EMAC_COUNT
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_FLASH_BASE		0xFC000000
+#define CONFIG_SYS_NAND_ADDR		0xF8000000
+#define CONFIG_SYS_FPGA_BASE		0xF0000000
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & Stack Pointer Configuration Options
+ *
+ *   There are traditionally three options for the primordial
+ *   (i.e. initial) stack usage on the 405-series:
+ *
+ *      1) On-chip Memory (OCM) (i.e. SRAM)
+ *      2) Data cache
+ *      3) SDRAM
+ *
+ *   For the 405EX(r), there is no OCM, so we are left with (2) or (3)
+ *   the latter of which is less than desireable since it requires
+ *   setting up the SDRAM and ECC in assembly code.
+ *
+ *   To use (2), define 'CONFIG_SYS_INIT_DCACHE_CS' to be an unused chip
+ *   select on the External Bus Controller (EBC) and then select a
+ *   value for 'CONFIG_SYS_INIT_RAM_ADDR' outside of the range of valid,
+ *   physical SDRAM. Otherwise, undefine 'CONFIG_SYS_INIT_DCACHE_CS' and
+ *   select a value for 'CONFIG_SYS_INIT_RAM_ADDR' within the range of valid,
+ *   physical SDRAM to use (3).
+ *-----------------------------------------------------------------------*/
+
+#define CONFIG_SYS_INIT_DCACHE_CS	4
+
+#if defined(CONFIG_SYS_INIT_DCACHE_CS)
+#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_SDRAM_BASE + ( 1 << 30))	/*  1 GiB */
+#else
+#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_SDRAM_BASE + (32 << 20))	/* 32 MiB */
+#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
+
+#define CONFIG_SYS_INIT_RAM_SIZE        (4 << 10)			/*  4 KiB */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * If the data cache is being used for the primordial stack and global
+ * data area, the POST word must be placed somewhere else. The General
+ * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves
+ * its compare and mask register contents across reset, so it is used
+ * for the POST word.
+ */
+
+#if defined(CONFIG_SYS_INIT_DCACHE_CS)
+# define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+# define CONFIG_SYS_POST_WORD_ADDR	(CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
+#else
+# define CONFIG_SYS_INIT_EXTRA_SIZE	16
+# define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_EXTRA_SIZE)
+# define CONFIG_SYS_OCM_DATA_ADDR	CONFIG_SYS_INIT_RAM_ADDR
+#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_EXT_SERIAL_CLOCK	11059200	/* ext. 11.059MHz clk	*/
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+#define CONFIG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible	*/
+#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
+
+#define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector	*/
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
+#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+#endif /* CONFIG_ENV_IS_IN_FLASH */
+
+/*-----------------------------------------------------------------------
+ * NAND FLASH
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		(CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
+#define CONFIG_SYS_NAND_SELECT_DEVICE  1	/* nand driver supports mutipl. chips	*/
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_MBYTES_SDRAM        (256)		/* 256MB			*/
+
+/*
+ * CONFIG_PPC4xx_DDR_AUTOCALIBRATION
+ *
+ * Note: DDR Autocalibration Method_A scans the full range of possible PPC4xx
+ *       SDRAM Controller DDR autocalibration values and takes a lot longer
+ *       to run than Method_B.
+ * (See the Method_A and Method_B algorithm discription in the file:
+ *	arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c)
+ * Define CONFIG_PPC4xx_DDR_METHOD_A to use DDR autocalibration Method_A
+ *
+ * DDR Autocalibration Method_B is the default.
+ */
+#define	CONFIG_PPC4xx_DDR_AUTOCALIBRATION	/* IBM DDR autocalibration */
+#define	DEBUG_PPC4xx_DDR_AUTOCALIBRATION	/* dynamic DDR autocal debug */
+#undef	CONFIG_PPC4xx_DDR_METHOD_A
+
+#define	CONFIG_SYS_SDRAM0_MB0CF_BASE	((  0 << 20) + CONFIG_SYS_SDRAM_BASE)
+
+/* DDR1/2 SDRAM Device Control Register Data Values */
+#define CONFIG_SYS_SDRAM0_MB0CF	((CONFIG_SYS_SDRAM0_MB0CF_BASE >> 3)	| \
+				 SDRAM_RXBAS_SDSZ_256MB		| \
+				 SDRAM_RXBAS_SDAM_MODE7		| \
+				 SDRAM_RXBAS_SDBE_ENABLE)
+#define CONFIG_SYS_SDRAM0_MB1CF	SDRAM_RXBAS_SDBE_DISABLE
+#define CONFIG_SYS_SDRAM0_MB2CF	SDRAM_RXBAS_SDBE_DISABLE
+#define CONFIG_SYS_SDRAM0_MB3CF	SDRAM_RXBAS_SDBE_DISABLE
+#define CONFIG_SYS_SDRAM0_MCOPT1	(SDRAM_MCOPT1_PMU_OPEN		| \
+				 SDRAM_MCOPT1_8_BANKS		| \
+				 SDRAM_MCOPT1_DDR2_TYPE		| \
+				 SDRAM_MCOPT1_QDEP		| \
+				 SDRAM_MCOPT1_DCOO_DISABLED)
+#define CONFIG_SYS_SDRAM0_MCOPT2	0x00000000
+#define CONFIG_SYS_SDRAM0_MODT0	(SDRAM_MODT_EB0W_ENABLE | \
+				 SDRAM_MODT_EB0R_ENABLE)
+#define CONFIG_SYS_SDRAM0_MODT1	0x00000000
+#define CONFIG_SYS_SDRAM0_CODT		(SDRAM_CODT_RK0R_ON		| \
+				 SDRAM_CODT_CKLZ_36OHM		| \
+				 SDRAM_CODT_DQS_1_8_V_DDR2	| \
+				 SDRAM_CODT_IO_NMODE)
+#define CONFIG_SYS_SDRAM0_RTR		SDRAM_RTR_RINT_ENCODE(1560)
+#define CONFIG_SYS_SDRAM0_INITPLR0	(SDRAM_INITPLR_ENABLE			| \
+		SDRAM_INITPLR_IMWT_ENCODE(80)				| \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP))
+#define CONFIG_SYS_SDRAM0_INITPLR1	(SDRAM_INITPLR_ENABLE			| \
+		SDRAM_INITPLR_IMWT_ENCODE(3)				| \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE)		| \
+		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)			| \
+		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
+#define CONFIG_SYS_SDRAM0_INITPLR2	(SDRAM_INITPLR_ENABLE			| \
+		SDRAM_INITPLR_IMWT_ENCODE(2)				| \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)		| \
+		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2)			| \
+		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL))
+#define CONFIG_SYS_SDRAM0_INITPLR3	(SDRAM_INITPLR_ENABLE			| \
+		SDRAM_INITPLR_IMWT_ENCODE(2)				| \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)		| \
+		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3)			| \
+		SDRAM_INITPLR_IMA_ENCODE(0))
+#define CONFIG_SYS_SDRAM0_INITPLR4	(SDRAM_INITPLR_ENABLE			| \
+		SDRAM_INITPLR_IMWT_ENCODE(2)				| \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)		| \
+		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)			| \
+		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_DISABLE | \
+					 JEDEC_MA_EMR_RTT_75OHM))
+#define CONFIG_SYS_SDRAM0_INITPLR5	(SDRAM_INITPLR_ENABLE			| \
+		SDRAM_INITPLR_IMWT_ENCODE(2)				| \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)		| \
+		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)			| \
+		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
+					 JEDEC_MA_MR_CL_DDR2_4_0_CLK | \
+					 JEDEC_MA_MR_BLEN_4 | \
+					 JEDEC_MA_MR_DLL_RESET))
+#define CONFIG_SYS_SDRAM0_INITPLR6	(SDRAM_INITPLR_ENABLE			| \
+		SDRAM_INITPLR_IMWT_ENCODE(3)				| \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE)		| \
+		SDRAM_INITPLR_IBA_ENCODE(0x0)				| \
+		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
+#define CONFIG_SYS_SDRAM0_INITPLR7	(SDRAM_INITPLR_ENABLE			| \
+		SDRAM_INITPLR_IMWT_ENCODE(26)				| \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
+#define CONFIG_SYS_SDRAM0_INITPLR8	(SDRAM_INITPLR_ENABLE			| \
+		SDRAM_INITPLR_IMWT_ENCODE(26)				| \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
+#define CONFIG_SYS_SDRAM0_INITPLR9	(SDRAM_INITPLR_ENABLE			| \
+		SDRAM_INITPLR_IMWT_ENCODE(26)				| \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
+#define CONFIG_SYS_SDRAM0_INITPLR10	(SDRAM_INITPLR_ENABLE			| \
+		SDRAM_INITPLR_IMWT_ENCODE(26)				| \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
+#define CONFIG_SYS_SDRAM0_INITPLR11	(SDRAM_INITPLR_ENABLE			| \
+		SDRAM_INITPLR_IMWT_ENCODE(2)				| \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)		| \
+		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)			| \
+		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
+					 JEDEC_MA_MR_CL_DDR2_4_0_CLK | \
+					 JEDEC_MA_MR_BLEN_4))
+#define CONFIG_SYS_SDRAM0_INITPLR12	(SDRAM_INITPLR_ENABLE			| \
+		SDRAM_INITPLR_IMWT_ENCODE(2)				| \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)		| \
+		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)			| \
+		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER	| \
+					 JEDEC_MA_EMR_RDQS_DISABLE | \
+					 JEDEC_MA_EMR_DQS_DISABLE | \
+					 JEDEC_MA_EMR_RTT_DISABLED | \
+					 JEDEC_MA_EMR_ODS_NORMAL))
+#define CONFIG_SYS_SDRAM0_INITPLR13	(SDRAM_INITPLR_ENABLE			| \
+		SDRAM_INITPLR_IMWT_ENCODE(2)				| \
+		SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)		| \
+		SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)			| \
+		SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT | \
+					 JEDEC_MA_EMR_RDQS_DISABLE | \
+					 JEDEC_MA_EMR_DQS_DISABLE | \
+					 JEDEC_MA_EMR_RTT_DISABLED | \
+					 JEDEC_MA_EMR_ODS_NORMAL))
+#define CONFIG_SYS_SDRAM0_INITPLR14	(SDRAM_INITPLR_DISABLE)
+#define CONFIG_SYS_SDRAM0_INITPLR15	(SDRAM_INITPLR_DISABLE)
+#define CONFIG_SYS_SDRAM0_RQDC		(SDRAM_RQDC_RQDE_ENABLE | \
+				 SDRAM_RQDC_RQFD_ENCODE(56))
+#define CONFIG_SYS_SDRAM0_RFDC		SDRAM_RFDC_RFFD_ENCODE(521)
+#define CONFIG_SYS_SDRAM0_RDCC		(SDRAM_RDCC_RDSS_T2)
+#define CONFIG_SYS_SDRAM0_DLCR		(SDRAM_DLCR_DCLM_AUTO		| \
+				 SDRAM_DLCR_DLCS_CONT_DONE	| \
+				 SDRAM_DLCR_DLCV_ENCODE(165))
+#define CONFIG_SYS_SDRAM0_CLKTR	(SDRAM_CLKTR_CLKP_180_DEG_ADV)
+#define CONFIG_SYS_SDRAM0_WRDTR	0x00000000
+#define CONFIG_SYS_SDRAM0_SDTR1	(SDRAM_SDTR1_LDOF_2_CLK	| \
+				 SDRAM_SDTR1_RTW_2_CLK	| \
+				 SDRAM_SDTR1_RTRO_1_CLK)
+#define CONFIG_SYS_SDRAM0_SDTR2	(SDRAM_SDTR2_RCD_3_CLK		| \
+				 SDRAM_SDTR2_WTR_2_CLK		| \
+				 SDRAM_SDTR2_XSNR_32_CLK	| \
+				 SDRAM_SDTR2_WPC_4_CLK		| \
+				 SDRAM_SDTR2_RPC_2_CLK		| \
+				 SDRAM_SDTR2_RP_3_CLK		| \
+				 SDRAM_SDTR2_RRD_2_CLK)
+#define CONFIG_SYS_SDRAM0_SDTR3	(SDRAM_SDTR3_RAS_ENCODE(8)	| \
+				 SDRAM_SDTR3_RC_ENCODE(11)	| \
+				 SDRAM_SDTR3_XCS		| \
+				 SDRAM_SDTR3_RFC_ENCODE(26))
+#define CONFIG_SYS_SDRAM0_MMODE	(SDRAM_MMODE_WR_DDR2_3_CYC | \
+				 SDRAM_MMODE_DCL_DDR2_4_0_CLK | \
+				 SDRAM_MMODE_BLEN_4)
+#define CONFIG_SYS_SDRAM0_MEMODE	(SDRAM_MEMODE_DQS_DISABLE | \
+				 SDRAM_MEMODE_RTT_75OHM)
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x52	/* I2C boot EEPROM (24C02BN)	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
+
+/* I2C bootstrap EEPROM */
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR	0x52
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET	0
+#define CONFIG_4xx_CONFIG_BLOCKSIZE		16
+
+/* Standard DTT sensor configuration */
+#define CONFIG_DTT_DS1775	1
+#define CONFIG_DTT_SENSORS	{ 0 }
+#define CONFIG_SYS_I2C_DTT_ADDR	0x48
+
+/* RTC configuration */
+#define CONFIG_RTC_DS1338	1
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68
+
+/*-----------------------------------------------------------------------
+ * Ethernet
+ *----------------------------------------------------------------------*/
+#define CONFIG_M88E1111_PHY	1
+#define CONFIG_IBM_EMAC4_V4	1
+#define CONFIG_EMAC_PHY_MODE	EMAC_PHY_MODE_RGMII_RGMII
+#define CONFIG_PHY_ADDR		1	/* PHY address, See schematics	*/
+
+#define CONFIG_PHY_RESET	1	/* reset phy upon startup	*/
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+
+#define CONFIG_HAS_ETH0		1
+
+#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"   */
+#define CONFIG_PHY1_ADDR	2
+
+/* Debug messages for the DDR autocalibration */
+#define CONFIG_AUTOCALIB		"silent\0"  /* default is non-verbose */
+
+/*
+ * Default environment variables
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_AMCC_DEF_ENV						\
+	CONFIG_AMCC_DEF_ENV_POWERPC					\
+	CONFIG_AMCC_DEF_ENV_PPC_OLD					\
+	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
+	"logversion=2\0"						\
+	"kernel_addr=fc000000\0"					\
+	"fdt_addr=fc1e0000\0"						\
+	"ramdisk_addr=fc200000\0"					\
+	"pciconfighost=1\0"						\
+	"pcie_mode=RP:RP\0"						\
+	""
+
+/*
+ * Commands additional to the ones defined in amcc-common.h
+ */
+#define CONFIG_CMD_CHIP_CONFIG
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_SNTP
+
+#define CONFIG_SYS_POST_MEMORY_ON	CONFIG_SYS_POST_MEMORY
+
+/* POST support */
+#define CONFIG_POST		(CONFIG_SYS_POST_CACHE		| \
+				 CONFIG_SYS_POST_CPU		| \
+				 CONFIG_SYS_POST_ETHER		| \
+				 CONFIG_SYS_POST_I2C		| \
+				 CONFIG_SYS_POST_MEMORY_ON	| \
+				 CONFIG_SYS_POST_UART)
+
+/* Define here the base-addresses of the UARTs to test in POST */
+#define CONFIG_SYS_POST_UART_TABLE	{ CONFIG_SYS_NS16550_COM1, \
+			CONFIG_SYS_NS16550_COM2 }
+
+#define CONFIG_LOGBUFFER
+#define CONFIG_SYS_POST_CACHE_ADDR	0x00800000 /* free virtual address	*/
+
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *----------------------------------------------------------------------*/
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_PNP		1	/* do pci plug-and-play		*/
+#define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup	*/
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE
+
+/*-----------------------------------------------------------------------
+ * PCIe stuff
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_PCIE_MEMBASE	0x90000000	/* mapped PCIe memory	*/
+#define CONFIG_SYS_PCIE_MEMSIZE	0x08000000      /* 128 Meg, smallest incr per port */
+
+#define	CONFIG_SYS_PCIE0_CFGBASE	0xa0000000      /* remote access */
+#define	CONFIG_SYS_PCIE0_XCFGBASE	0xb0000000      /* local access */
+#define	CONFIG_SYS_PCIE0_CFGMASK	0xe0000001      /* 512 Meg */
+
+#define	CONFIG_SYS_PCIE1_CFGBASE	0xc0000000      /* remote access */
+#define	CONFIG_SYS_PCIE1_XCFGBASE	0xd0000000      /* local access */
+#define	CONFIG_SYS_PCIE1_CFGMASK	0xe0000001      /* 512 Meg */
+
+#define	CONFIG_SYS_PCIE0_UTLBASE	0xef502000
+#define	CONFIG_SYS_PCIE1_UTLBASE	0xef503000
+
+/* base address of inbound PCIe window */
+#define CONFIG_SYS_PCIE_INBOUND_BASE	0x0000000000000000ULL
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_NAND_CS		1		/* NAND chip connected to CSx	*/
+
+/* Memory Bank 0 (NOR-FLASH) initialization					*/
+#define CONFIG_SYS_EBC_PB0AP		0x05806500
+#define CONFIG_SYS_EBC_PB0CR           0xFC0DA000  /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/
+
+/* Memory Bank 1 (NAND-FLASH) initialization					*/
+#define CONFIG_SYS_EBC_PB1AP		0x018003c0
+#define CONFIG_SYS_EBC_PB1CR		(CONFIG_SYS_NAND_ADDR | 0x1e000)
+
+/* Memory Bank 2 (FPGA) initialization					*/
+#define CONFIG_SYS_EBC_PB2AP		(EBC_BXAP_BME_ENABLED |		\
+					 EBC_BXAP_FWT_ENCODE(6) |	\
+					 EBC_BXAP_BWT_ENCODE(1) |	\
+					 EBC_BXAP_BCE_DISABLE |		\
+					 EBC_BXAP_BCT_2TRANS |		\
+					 EBC_BXAP_CSN_ENCODE(0) |	\
+					 EBC_BXAP_OEN_ENCODE(0) |	\
+					 EBC_BXAP_WBN_ENCODE(3) |	\
+					 EBC_BXAP_WBF_ENCODE(1) |	\
+					 EBC_BXAP_TH_ENCODE(4) |	\
+					 EBC_BXAP_RE_DISABLED |		\
+					 EBC_BXAP_SOR_DELAYED |		\
+					 EBC_BXAP_BEM_WRITEONLY |	\
+					 EBC_BXAP_PEN_DISABLED)
+#define CONFIG_SYS_EBC_PB2CR	(CONFIG_SYS_FPGA_BASE | 0x18000)
+
+#define CONFIG_SYS_EBC_CFG		0x7FC00000 /*  EBC0_CFG */
+
+/*-----------------------------------------------------------------------
+ * GPIO Setup
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_4xx_GPIO_TABLE { /*	  Out		  GPIO	Alternate1	Alternate2	Alternate3 */ \
+{											\
+/* GPIO Core 0 */									\
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO0	EBC_DATA_PAR(0)			*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO1	EBC_DATA_PAR(1)			*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO2	EBC_DATA_PAR(2)			*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO3	EBC_DATA_PAR(3)			*/	\
+{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO4	EBC_DATA(20)	USB2_DATA(4)	*/	\
+{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO5	EBC_DATA(21)	USB2_DATA(5)	*/	\
+{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO6	EBC_DATA(22)	USB2_DATA(6)	*/	\
+{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO7	EBC_DATA(23)	USB2_DATA(7)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8	CS(1)/NFCE(1)	IRQ(7)		*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9	CS(2)/NFCE(2)	IRQ(8)		*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 CS(3)/NFCE(3)	IRQ(9)		*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 IRQ(6)				*/	\
+{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO12 EBC_DATA(16)	USB2_DATA(0)	*/	\
+{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO13 EBC_DATA(17)	USB2_DATA(1)	*/	\
+{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO14 EBC_DATA(18)	USB2_DATA(2)	*/	\
+{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO15 EBC_DATA(19)	USB2_DATA(3)	*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 UART0_DCD	UART1_CTS	*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 UART0_DSR	UART1_RTS	*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 UART0_CTS			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 UART0_RTS			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO20 UART0_DTR	UART1_TX	*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO21 UART0_RI	UART1_RX	*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO22 EBC_HOLD_REQ	DMA_ACK2	*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO23 EBC_HOLD_ACK	DMA_REQ2	*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO24 EBC_EXT_REQ	DMA_EOT2	IRQ(4) */ \
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO25 EBC_EXT_ACK	DMA_ACK3	IRQ(3) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 EBC_ADDR(5)	DMA_EOT0	TS(3) */ \
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO27 EBC_BUS_REQ	DMA_EOT3	IRQ(5) */ \
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO28				*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO29 DMA_EOT1	IRQ(2)		*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO30 DMA_REQ1	IRQ(1)		*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO31 DMA_ACK1	IRQ(0)		*/	\
+}												\
+}
+
+/*-----------------------------------------------------------------------
+ * Some Kilauea stuff..., mainly fpga registers
+ */
+#define CONFIG_SYS_FPGA_REG_BASE		CONFIG_SYS_FPGA_BASE
+#define CONFIG_SYS_FPGA_FIFO_BASE		(CONFIG_SYS_FPGA_BASE | (1 << 10))
+
+/* interrupt */
+#define CONFIG_SYS_FPGA_SLIC0_R_DPRAM_INT	0x80000000
+#define CONFIG_SYS_FPGA_SLIC0_W_DPRAM_INT	0x40000000
+#define CONFIG_SYS_FPGA_SLIC1_R_DPRAM_INT	0x20000000
+#define CONFIG_SYS_FPGA_SLIC1_W_DPRAM_INT	0x10000000
+#define CONFIG_SYS_FPGA_PHY0_INT		0x08000000
+#define CONFIG_SYS_FPGA_PHY1_INT		0x04000000
+#define CONFIG_SYS_FPGA_SLIC0_INT		0x02000000
+#define CONFIG_SYS_FPGA_SLIC1_INT		0x01000000
+
+/* DPRAM setting */
+/* 00: 32B; 01: 64B; 10: 128B; 11: 256B  */
+#define CONFIG_SYS_FPGA_DPRAM_R_INT_LINE	0x00400000	/* 64 B */
+#define CONFIG_SYS_FPGA_DPRAM_W_INT_LINE	0x00100000	/* 64 B */
+#define CONFIG_SYS_FPGA_DPRAM_RW_TYPE		0x00080000
+#define CONFIG_SYS_FPGA_DPRAM_RST		0x00040000
+#define CONFIG_SYS_FPGA_UART0_FO		0x00020000
+#define CONFIG_SYS_FPGA_UART1_FO		0x00010000
+
+/* loopback */
+#define CONFIG_SYS_FPGA_CHIPSIDE_LOOPBACK	0x00004000
+#define CONFIG_SYS_FPGA_LINESIDE_LOOPBACK	0x00008000
+#define CONFIG_SYS_FPGA_SLIC0_ENABLE		0x00002000
+#define CONFIG_SYS_FPGA_SLIC1_ENABLE		0x00001000
+#define CONFIG_SYS_FPGA_SLIC0_CS		0x00000800
+#define CONFIG_SYS_FPGA_SLIC1_CS		0x00000400
+#define CONFIG_SYS_FPGA_USER_LED0		0x00000200
+#define CONFIG_SYS_FPGA_USER_LED1		0x00000100
+
+#define CONFIG_SYS_FPGA_MAGIC_MASK		0xffff0000
+#define CONFIG_SYS_FPGA_MAGIC			0xabcd0000
+#define CONFIG_SYS_FPGA_VER_MASK		0x0000ff00
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/km/keymile-common.h b/qemu/roms/u-boot/include/configs/km/keymile-common.h
new file mode 100644
index 000000000..517f46a3a
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/km/keymile-common.h
@@ -0,0 +1,253 @@
+/*
+ * (C) Copyright 2008-2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_KEYMILE_H
+#define __CONFIG_KEYMILE_H
+
+#define CONFIG_BOOTCOUNT_LIMIT
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DEFAULTENV_VARS
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_SETEXPR
+
+#undef	CONFIG_WATCHDOG		/* disable platform specific watchdog */
+
+#define CONFIG_BOOTDELAY	2 /* autoboot after 2 seconds */
+#undef	CONFIG_BOOTARGS		/* the boot command will set bootargs */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	  */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size  */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS		32 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+
+#define CONFIG_HUSH_INIT_VAR
+
+#define CONFIG_SYS_ALT_MEMTEST		/* memory test, takes time */
+
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#define CONFIG_LOADS_ECHO
+#define CONFIG_SYS_LOADS_BAUD_CHANGE
+
+/* Support the IVM EEprom */
+#define	CONFIG_SYS_IVM_EEPROM_ADR	0x50
+#define CONFIG_SYS_IVM_EEPROM_MAX_LEN	0x400
+#define CONFIG_SYS_IVM_EEPROM_PAGE_LEN	0x100
+
+#define	CONFIG_SYS_FLASH_PROTECTION
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/* UBI Support for all Keymile boards */
+#define CONFIG_CMD_UBI
+#define CONFIG_RBTREE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_CONCAT
+
+#define CONFIG_CMD_CRAMFS
+#define CONFIG_CRAMFS_CMDLINE
+
+#ifndef CONFIG_KM_DEF_ENV_BOOTPARAMS
+#define CONFIG_KM_DEF_ENV_BOOTPARAMS \
+	"actual_bank=0\0"
+#endif
+
+#ifndef CONFIG_KM_DEF_NETDEV
+#define CONFIG_KM_DEF_NETDEV	\
+	"netdev=eth0\0"
+#endif
+
+#ifndef CONFIG_KM_UBI_PARTITION_NAME_BOOT
+#define CONFIG_KM_UBI_PARTITION_NAME_BOOT	"ubi0"
+#endif /* CONFIG_KM_UBI_PARTITION_NAME_BOOT */
+
+#ifndef CONFIG_KM_UBI_PART_BOOT_OPTS
+#define CONFIG_KM_UBI_PART_BOOT_OPTS		""
+#endif /* CONFIG_KM_UBI_PART_BOOT_OPTS */
+
+#ifndef CONFIG_KM_UBI_PARTITION_NAME_APP
+/* one flash chip only called boot */
+/* boot: CONFIG_KM_UBI_PARTITION_NAME_BOOT */
+# define CONFIG_KM_UBI_LINUX_MTD					\
+	"ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT			\
+	CONFIG_KM_UBI_PART_BOOT_OPTS
+# define CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI				\
+	"ubiattach=ubi part " CONFIG_KM_UBI_PARTITION_NAME_BOOT "\0"
+#else /* CONFIG_KM_UBI_PARTITION_NAME_APP */
+/* two flash chips called boot and app */
+/* boot: CONFIG_KM_UBI_PARTITION_NAME_BOOT */
+/* app:  CONFIG_KM_UBI_PARTITION_NAME_APP */
+# define CONFIG_KM_UBI_LINUX_MTD					\
+	"ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT			\
+	CONFIG_KM_UBI_PART_BOOT_OPTS " "				\
+	"ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_APP
+# define CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI				\
+	"ubiattach=if test ${boot_bank} -eq 0; then; "			\
+	"ubi part " CONFIG_KM_UBI_PARTITION_NAME_BOOT "; else; "	\
+	"ubi part " CONFIG_KM_UBI_PARTITION_NAME_APP "; fi\0"
+#endif /* CONFIG_KM_UBI_PARTITION_NAME_APP */
+
+#ifdef CONFIG_NAND_ECC_BCH
+#define CONFIG_KM_UIMAGE_NAME "ecc_bch_uImage\0"
+#define CONFIG_KM_ECC_MODE    " eccmode=bch"
+#else
+#define CONFIG_KM_UIMAGE_NAME "uImage\0"
+#define CONFIG_KM_ECC_MODE
+#endif
+
+/*
+ * boottargets
+ * - set 'subbootcmds'
+ * - set 'bootcmd' and 'altbootcmd'
+ * available targets:
+ * - 'release': for a standalone system		kernel/rootfs from flash
+ */
+#define CONFIG_KM_DEF_ENV_BOOTTARGETS					\
+	"subbootcmds=ubiattach ubicopy cramfsloadfdt set_fdthigh "	\
+		"cramfsloadkernel flashargs add_default addpanic boot\0"\
+	"develop="							\
+		"tftp 200000 scripts/develop-${arch}.txt && "		\
+		"env import -t 200000 ${filesize} && "			\
+		"run setup_debug_env\0"					\
+	"ramfs="							\
+		"tftp 200000 scripts/ramfs-${arch}.txt && "		\
+		"env import -t 200000 ${filesize} && "			\
+		"run setup_debug_env\0"					\
+	""
+
+/*
+ * bootargs
+ * - modify 'bootargs'
+ *
+ * - 'add_default': default bootargs common for all arm/ppc boards
+ * - 'addpanic': add kernel panic options
+ * - 'flashargs': defaults arguments for flash base boot
+ *
+ */
+#define CONFIG_KM_DEF_ENV_BOOTARGS					\
+	"add_default="							\
+		"setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off:"				\
+		" console=" CONFIG_KM_CONSOLE_TTY ",${baudrate}"	\
+		" mem=${kernelmem} init=${init}"			\
+		CONFIG_KM_ECC_MODE					\
+		" phram.phram=phvar,${varaddr}," __stringify(CONFIG_KM_PHRAM)\
+		" " CONFIG_KM_UBI_LINUX_MTD " "				\
+		CONFIG_KM_DEF_BOOT_ARGS_CPU				\
+		"\0"							\
+	"addpanic="							\
+		"setenv bootargs ${bootargs} panic=1 panic_on_oops=1\0"	\
+	"flashargs="							\
+		"setenv bootargs "					\
+		"root=mtdblock:rootfs${boot_bank} "			\
+		"rootfstype=squashfs ro\0"				\
+	""
+
+/*
+ * flash_boot
+ * - commands for booting from flash
+ *
+ * - 'cramfsloadkernel': copy kernel from a cramfs to ram
+ * - 'ubiattach': attach ubi partition
+ * - 'ubicopy': copy ubi volume to ram
+ *              - volume names: bootfs0, bootfs1, bootfs2, ...
+ *
+ * processor specific settings
+ * - 'cramfsloadfdt': copy fdt from a cramfs to ram
+ */
+#define CONFIG_KM_DEF_ENV_FLASH_BOOT					\
+	"cramfsaddr=" __stringify(CONFIG_KM_CRAMFS_ADDR) "\0"		\
+	"cramfsloadkernel=cramfsload ${load_addr_r} ${uimage}\0"	\
+	"ubicopy=ubi read "__stringify(CONFIG_KM_CRAMFS_ADDR)		\
+			" bootfs${boot_bank}\0"				\
+	"uimage=" CONFIG_KM_UIMAGE_NAME					\
+	CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI
+
+/*
+ * constants
+ * - KM specific constants and commands
+ *
+ * - 'default': setup default environment
+ */
+#define CONFIG_KM_DEF_ENV_CONSTANTS					\
+	"backup_bank=0\0"						\
+	"release=run newenv; reset\0"					\
+	"pnvramsize=" __stringify(CONFIG_KM_PNVRAM) "\0"		\
+	"testbootcmd=setenv boot_bank ${test_bank}; "			\
+		"run ${subbootcmds}; reset\0"				\
+	""
+
+#ifndef CONFIG_KM_DEF_ENV
+#define CONFIG_KM_DEF_ENV	\
+	CONFIG_KM_DEF_ENV_BOOTPARAMS					\
+	CONFIG_KM_DEF_NETDEV						\
+	CONFIG_KM_DEF_ENV_CPU						\
+	CONFIG_KM_DEF_ENV_BOOTTARGETS					\
+	CONFIG_KM_DEF_ENV_BOOTARGS					\
+	CONFIG_KM_DEF_ENV_FLASH_BOOT					\
+	CONFIG_KM_DEF_ENV_CONSTANTS					\
+	"altbootcmd=run bootcmd\0"					\
+	"boot=bootm ${load_addr_r} - ${fdt_addr_r}\0"			\
+	"bootcmd=km_checkbidhwk &&  "					\
+		"setenv bootcmd \'if km_checktestboot; then; "          \
+				"setenv boot_bank ${test_bank}; else; " \
+				"setenv boot_bank ${actual_bank}; fi;"  \
+			"run ${subbootcmds}; reset\' && "		\
+		"setenv altbootcmd \'setenv boot_bank ${backup_bank}; "	\
+			"run ${subbootcmds}; reset\' && "		\
+		"saveenv && saveenv && boot\0"				\
+	"bootlimit=3\0"							\
+	"cramfsloadfdt="						\
+		"cramfsload ${fdt_addr_r} "				\
+		"fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0"		\
+	"fdt_addr_r="__stringify(CONFIG_KM_FDT_ADDR) "\0"		\
+	"init=/sbin/init-overlay.sh\0"					\
+	"load_addr_r="__stringify(CONFIG_KM_KERNEL_ADDR) "\0"		\
+	"load=tftpboot ${load_addr_r} ${u-boot}\0"			\
+	"mtdids=" MTDIDS_DEFAULT "\0"					\
+	"mtdparts=" MTDPARTS_DEFAULT "\0"				\
+	""
+#endif /* CONFIG_KM_DEF_ENV */
+
+#define CONFIG_VERSION_VARIABLE	/* include version env variable */
+
+#endif /* __CONFIG_KEYMILE_H */
diff --git a/qemu/roms/u-boot/include/configs/km/km-powerpc.h b/qemu/roms/u-boot/include/configs/km/km-powerpc.h
new file mode 100644
index 000000000..763c5bad8
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/km/km-powerpc.h
@@ -0,0 +1,83 @@
+/*
+ * (C) Copyright 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_KEYMILE_POWERPC_H
+#define __CONFIG_KEYMILE_POWERPC_H
+
+/* Do boardspecific init for all boards */
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_LAST_STAGE_INIT
+
+#define CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_CMD_DTT
+#define CONFIG_JFFS2_CMDLINE
+
+/* standard km ethernet_present for piggy */
+#define CONFIG_KM_COMMON_ETH_INIT
+
+/* EEprom support 24C08, 24C16, 24C64 */
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3  /* 8 Byte write page */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
+
+#define CONFIG_ENV_SIZE		0x04000		/* Size of Environment */
+#define CONFIG_FLASH_CFI_MTD
+
+#define CONFIG_SYS_MEMTEST_START 0x00100000	/* memtest works on */
+
+#define CONFIG_SYS_MEMTEST_END	0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+
+/* Reserve 4 MB for malloc */
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+
+/******************************************************************************
+ * (PRAM usage)
+ * ... -------------------------------------------------------
+ * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM
+ * ... |<------------------- pram -------------------------->|
+ * ... -------------------------------------------------------
+ * @END_OF_RAM:
+ * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose
+ * @CONFIG_KM_PHRAM: address for /var
+ * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application)
+ * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM
+ */
+
+/* size of rootfs in RAM */
+#define CONFIG_KM_ROOTFSSIZE	0x0
+/* pseudo-non volatile RAM [hex] */
+#define CONFIG_KM_PNVRAM	0x80000
+/* physical RAM MTD size [hex] */
+#define CONFIG_KM_PHRAM		0x100000
+/* resereved pram area at the end of memroy [hex] */
+#define CONFIG_KM_RESERVED_PRAM	0x0
+/* enable protected RAM */
+#define CONFIG_PRAM		0
+
+#define CONFIG_KM_CRAMFS_ADDR	0x800000
+#define CONFIG_KM_KERNEL_ADDR	0x400000	/* 3968Kbytes */
+#define CONFIG_KM_FDT_ADDR	0x7E0000	/* 128Kbytes */
+
+/* architecture specific default bootargs */
+#define CONFIG_KM_DEF_BOOT_ARGS_CPU		""
+
+#define CONFIG_KM_DEF_ENV_CPU						\
+	"u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.bin\0"		\
+	"update="							\
+		"protect off " __stringify(BOOTFLASH_START) " +${filesize} && "\
+		"erase " __stringify(BOOTFLASH_START) "  +${filesize} && "\
+		"cp.b ${load_addr_r} " __stringify(BOOTFLASH_START)	\
+		"  ${filesize} && "					\
+		"protect on " __stringify(BOOTFLASH_START) "  +${filesize}\0"\
+	"set_fdthigh=true\0"						\
+	""
+
+#endif /* __CONFIG_KEYMILE_POWERPC_H */
diff --git a/qemu/roms/u-boot/include/configs/km/km8309-common.h b/qemu/roms/u-boot/include/configs/km/km8309-common.h
new file mode 100644
index 000000000..c8df23b53
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/km/km8309-common.h
@@ -0,0 +1,170 @@
+/*
+ * Copyright (C) 2012 Keymile AG
+ *                    Gerlando Falauto <gerlando.falauto@keymile.com>
+ *
+ * Based on km8321-common.h, see respective copyright notice for credits
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_KM8309_COMMON_H
+#define __CONFIG_KM8309_COMMON_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1	/* E300 family */
+#define CONFIG_QE		1	/* Has QE */
+#define CONFIG_MPC830x		1	/* MPC830x family */
+#define CONFIG_MPC8309		1	/* MPC8309 CPU specific */
+
+#define CONFIG_KM_DEF_ARCH	"arch=ppc_82xx\0"
+#define CONFIG_CMD_DIAG		1
+
+/* include common defines/options for all 83xx Keymile boards */
+#include "km83xx-common.h"
+
+/* QE microcode/firmware address */
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+/* at end of uboot partition, before env */
+#define CONFIG_SYS_QE_FW_ADDR   0xF00B0000
+
+/*
+ * System IO Config
+ */
+/* 0x14000180 SICR_1 */
+#define CONFIG_SYS_SICRL (0			\
+		| SICR_1_UART1_UART1RTS		\
+		| SICR_1_I2C_CKSTOP		\
+		| SICR_1_IRQ_A_IRQ		\
+		| SICR_1_IRQ_B_IRQ		\
+		| SICR_1_GPIO_A_GPIO		\
+		| SICR_1_GPIO_B_GPIO		\
+		| SICR_1_GPIO_C_GPIO		\
+		| SICR_1_GPIO_D_GPIO		\
+		| SICR_1_GPIO_E_GPIO		\
+		| SICR_1_GPIO_F_GPIO		\
+		| SICR_1_USB_A_UART2S		\
+		| SICR_1_USB_B_UART2RTS		\
+		| SICR_1_FEC1_FEC1		\
+		| SICR_1_FEC2_FEC2		\
+		)
+
+/* 0x00080400 SICR_2 */
+#define CONFIG_SYS_SICRH (0			\
+		| SICR_2_FEC3_FEC3		\
+		| SICR_2_HDLC1_A_HDLC1		\
+		| SICR_2_ELBC_A_LA		\
+		| SICR_2_ELBC_B_LCLK		\
+		| SICR_2_HDLC2_A_HDLC2		\
+		| SICR_2_USB_D_GPIO		\
+		| SICR_2_PCI_PCI		\
+		| SICR_2_HDLC1_B_HDLC1		\
+		| SICR_2_HDLC1_C_HDLC1		\
+		| SICR_2_HDLC2_B_GPIO		\
+		| SICR_2_HDLC2_C_HDLC2		\
+		| SICR_2_QUIESCE_B		\
+		)
+
+/* GPR_1 */
+#define CONFIG_SYS_GPR1  0x50008060
+
+#define CONFIG_SYS_GP1DIR 0x00000000
+#define CONFIG_SYS_GP1ODR 0x00000000
+#define CONFIG_SYS_GP2DIR 0xFF000000
+#define CONFIG_SYS_GP2ODR 0x00000000
+
+/*
+ * Hardware Reset Configuration Word
+ */
+#define CONFIG_SYS_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
+	HRCWL_DDR_TO_SCB_CLK_2X1 | \
+	HRCWL_CSB_TO_CLKIN_2X1 | \
+	HRCWL_CORE_TO_CSB_2X1 | \
+	HRCWL_CE_PLL_VCO_DIV_2 | \
+	HRCWL_CE_TO_PLL_1X3)
+
+#define CONFIG_SYS_HRCW_HIGH (\
+	HRCWH_PCI_AGENT | \
+	HRCWH_PCI_ARBITER_DISABLE | \
+	HRCWH_CORE_ENABLE | \
+	HRCWH_FROM_0X00000100 | \
+	HRCWH_BOOTSEQ_DISABLE | \
+	HRCWH_SW_WATCHDOG_DISABLE | \
+	HRCWH_ROM_LOC_LOCAL_16BIT | \
+	HRCWH_BIG_ENDIAN | \
+	HRCWH_LALE_NORMAL)
+
+#define CONFIG_SYS_DDR_CS0_BNDS		0x0000007f
+#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SDRAM_TYPE_DDR2 | \
+					 SDRAM_CFG_32_BE | \
+					 SDRAM_CFG_SREN | \
+					 SDRAM_CFG_HSE)
+
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
+#define CONFIG_SYS_DDR_CLK_CNTL		(DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+#define CONFIG_SYS_DDR_INTERVAL	((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
+				 (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
+
+#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_AP | \
+					 CSCONFIG_ODT_RD_NEVER | \
+					 CSCONFIG_ODT_WR_ONLY_CURRENT | \
+					 CSCONFIG_ROW_BIT_13 | \
+					 CSCONFIG_COL_BIT_10)
+
+#define CONFIG_SYS_DDR_MODE	0x47860242
+#define CONFIG_SYS_DDR_MODE2	0x8080c000
+
+#define CONFIG_SYS_DDR_TIMING_0	((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
+				 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
+				 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
+				 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
+				 (0 << TIMING_CFG0_WWT_SHIFT) | \
+				 (0 << TIMING_CFG0_RRT_SHIFT) | \
+				 (0 << TIMING_CFG0_WRT_SHIFT) | \
+				 (0 << TIMING_CFG0_RWT_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_1	((TIMING_CFG1_CASLAT_40) | \
+				 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
+				 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
+				 (3 << TIMING_CFG1_WRREC_SHIFT) | \
+				 (7 << TIMING_CFG1_REFREC_SHIFT) | \
+				 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
+				 (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
+				 (3 << TIMING_CFG1_PRETOACT_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_2	((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
+				 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
+				 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
+				 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
+				 (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
+				 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
+				 (5 << TIMING_CFG2_CPO_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_3	0x00000000
+
+#define CONFIG_SYS_KMBEC_FPGA_BASE	0xE8000000
+#define CONFIG_SYS_KMBEC_FPGA_SIZE	128
+
+/* EEprom support */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+
+/*
+ * Local Bus Configuration & Clock Setup
+ */
+#define CONFIG_SYS_LCRR_DBYP	0x80000000
+#define CONFIG_SYS_LCRR_EADC	0x00010000
+#define CONFIG_SYS_LCRR_CLKDIV	0x00000002
+
+#define CONFIG_SYS_LBC_LBCR	0x00000000
+
+/*
+ * MMU Setup
+ */
+#define CONFIG_SYS_IBAT7L	(0)
+#define CONFIG_SYS_IBAT7U	(0)
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
+
+#endif /* __CONFIG_KM8309_COMMON_H */
diff --git a/qemu/roms/u-boot/include/configs/km/km8321-common.h b/qemu/roms/u-boot/include/configs/km/km8321-common.h
new file mode 100644
index 000000000..149895cb7
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/km/km8321-common.h
@@ -0,0 +1,135 @@
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ *                    Dave Liu <daveliu@freescale.com>
+ *
+ * Copyright (C) 2007 Logic Product Development, Inc.
+ *                    Peter Barada <peterb@logicpd.com>
+ *
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ *                    Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * (C) Copyright 2008
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * (C) Copyright 2010
+ * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
+ *
+ * (C) Copyright 2010-2011
+ * Thomas Reufer, KEYMILE Ltd, thomas.reufer@keymile.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_KM8321_COMMON_H
+#define __CONFIG_KM8321_COMMON_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_QE	/* Has QE */
+#define CONFIG_MPC832x	/* MPC832x CPU specific */
+#define CONFIG_KM8321	/* Keymile PBEC8321 board specific */
+
+#define CONFIG_KM_DEF_ARCH	"arch=ppc_8xx\0"
+
+/* include common defines/options for all 83xx Keymile boards */
+#include "km83xx-common.h"
+
+/*
+ * System IO Config
+ */
+#define CONFIG_SYS_SICRL	SICRL_IRQ_CKS
+
+/*
+ * Hardware Reset Configuration Word
+ */
+#define CONFIG_SYS_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
+	HRCWL_DDR_TO_SCB_CLK_2X1 | \
+	HRCWL_CSB_TO_CLKIN_2X1 | \
+	HRCWL_CORE_TO_CSB_2_5X1 | \
+	HRCWL_CE_PLL_VCO_DIV_2 | \
+	HRCWL_CE_TO_PLL_1X3)
+
+#define CONFIG_SYS_HRCW_HIGH (\
+	HRCWH_PCI_AGENT | \
+	HRCWH_PCI_ARBITER_DISABLE | \
+	HRCWH_CORE_ENABLE | \
+	HRCWH_FROM_0X00000100 | \
+	HRCWH_BOOTSEQ_DISABLE | \
+	HRCWH_SW_WATCHDOG_DISABLE | \
+	HRCWH_ROM_LOC_LOCAL_16BIT | \
+	HRCWH_BIG_ENDIAN | \
+	HRCWH_LALE_NORMAL)
+
+#define CONFIG_SYS_DDR_CS0_BNDS		0x0000007f
+#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SDRAM_TYPE_DDR2 | \
+					 SDRAM_CFG_32_BE | \
+					 SDRAM_CFG_SREN | \
+					 SDRAM_CFG_HSE)
+
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
+#define CONFIG_SYS_DDR_CLK_CNTL		(DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+#define CONFIG_SYS_DDR_INTERVAL	((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
+				 (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
+
+#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_AP | \
+					 CSCONFIG_ODT_WR_CFG | \
+					 CSCONFIG_ROW_BIT_13 | \
+					 CSCONFIG_COL_BIT_10)
+
+#define CONFIG_SYS_DDR_MODE	0x47860242
+#define CONFIG_SYS_DDR_MODE2	0x8080c000
+
+#define CONFIG_SYS_DDR_TIMING_0	((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
+				 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
+				 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
+				 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
+				 (0 << TIMING_CFG0_WWT_SHIFT) | \
+				 (0 << TIMING_CFG0_RRT_SHIFT) | \
+				 (0 << TIMING_CFG0_WRT_SHIFT) | \
+				 (0 << TIMING_CFG0_RWT_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_1	((TIMING_CFG1_CASLAT_40) | \
+				 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
+				 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
+				 (3 << TIMING_CFG1_WRREC_SHIFT) | \
+				 (7 << TIMING_CFG1_REFREC_SHIFT) | \
+				 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
+				 (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
+				 (3 << TIMING_CFG1_PRETOACT_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_2	((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
+				 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
+				 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
+				 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
+				 (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
+				 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
+				 (5 << TIMING_CFG2_CPO_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_3	0x00000000
+
+#define CONFIG_SYS_KMBEC_FPGA_BASE	0xE8000000
+#define CONFIG_SYS_KMBEC_FPGA_SIZE	128
+
+/* EEprom support */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+
+/*
+ * Local Bus Configuration & Clock Setup
+ */
+#define CONFIG_SYS_LCRR_DBYP	0x80000000
+#define CONFIG_SYS_LCRR_EADC	0x00010000
+#define CONFIG_SYS_LCRR_CLKDIV	0x00000002
+
+#define CONFIG_SYS_LBC_LBCR	0x00000000
+
+/*
+ * MMU Setup
+ */
+#define CONFIG_SYS_IBAT7L	(0)
+#define CONFIG_SYS_IBAT7U	(0)
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
+
+#endif /* __CONFIG_KM8321_COMMON_H */
diff --git a/qemu/roms/u-boot/include/configs/km/km83xx-common.h b/qemu/roms/u-boot/include/configs/km/km83xx-common.h
new file mode 100644
index 000000000..ae6b6dcf2
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/km/km83xx-common.h
@@ -0,0 +1,332 @@
+/*
+ * (C) Copyright 2010
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_KM83XX_H
+#define __CONFIG_KM83XX_H
+
+/* include common defines/options for all Keymile boards */
+#include "keymile-common.h"
+#include "km-powerpc.h"
+
+#ifndef MTDIDS_DEFAULT
+# define MTDIDS_DEFAULT	"nor0=boot"
+#endif /* MTDIDS_DEFAULT */
+
+#ifndef MTDPARTS_DEFAULT
+# define MTDPARTS_DEFAULT	"mtdparts="			\
+	"boot:"							\
+		"768k(u-boot),"					\
+		"128k(env),"					\
+		"128k(envred),"					\
+		"-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");"
+#endif /* MTDPARTS_DEFAULT */
+
+#define CONFIG_MISC_INIT_R
+/*
+ * System Clock Setup
+ */
+#define CONFIG_83XX_CLKIN		66000000
+#define CONFIG_SYS_CLK_FREQ		66000000
+#define CONFIG_83XX_PCICLK		66000000
+
+/*
+ * IMMR new address
+ */
+#define CONFIG_SYS_IMMR		0xE0000000
+
+/*
+ * Bus Arbitration Configuration Register (ACR)
+ */
+#define CONFIG_SYS_ACR_PIPE_DEP 3       /* pipeline depth 4 transactions */
+#define CONFIG_SYS_ACR_RPTCNT   3       /* 4 consecutive transactions */
+#define CONFIG_SYS_ACR_APARK    0       /* park bus to master (below) */
+#define CONFIG_SYS_ACR_PARKM    3       /* parking master = QuiccEngine */
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE2	(CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
+					DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+
+#define CFG_83XX_DDR_USES_CS0
+
+/*
+ * Manually set up DDR parameters
+ */
+#define CONFIG_DDR_II
+#define CONFIG_SYS_DDR_SIZE		2048 /* MB */
+
+/*
+ * The reserved memory
+ */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_FLASH_BASE		0xF0000000
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+/* Reserve 768 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
+
+/*
+ * Initial RAM Base Address Setup
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* End of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+						GENERATED_GBL_DATA_SIZE)
+
+/*
+ * Init Local Bus Memory Controller:
+ *
+ * Bank Bus     Machine PortSz  Size  Device
+ * ---- ---     ------- ------  -----  ------
+ *  0   Local   GPCM    16 bit  256MB FLASH
+ *  1   Local   GPCM     8 bit  128MB GPIO/PIGGY
+ *
+ */
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
+#define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
+#define CONFIG_SYS_FLASH_SIZE		256 /* max FLASH size is 256M */
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_256MB)
+
+#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE | \
+				BR_PS_16 | /* 16 bit port size */ \
+				BR_MS_GPCM | /* MSEL = GPCM */ \
+				BR_V)
+
+#define CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
+				OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
+				OR_GPCM_SCY_5 | \
+				OR_GPCM_TRLX_SET | OR_GPCM_EAD)
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1   /* max num of flash banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	512 /* max num of sects on one chip */
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+
+/*
+ * PRIO1/PIGGY on the local bus CS1
+ */
+/* Window base at flash base */
+#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_KMBEC_FPGA_BASE
+#define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_128MB)
+
+#define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_KMBEC_FPGA_BASE | \
+				BR_PS_8 | /* 8 bit port size */ \
+				BR_MS_GPCM | /* MSEL = GPCM */ \
+				BR_V)
+#define CONFIG_SYS_OR1_PRELIM	(MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
+				OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
+				OR_GPCM_SCY_2 | \
+				OR_GPCM_TRLX_SET | OR_GPCM_EAD)
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
+
+/* Pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/*
+ * QE UEC ethernet configuration
+ */
+#define CONFIG_UEC_ETH
+#define CONFIG_ETHPRIME		"UEC0"
+
+#if !defined(CONFIG_MPC8309)
+#define CONFIG_UEC_ETH1		/* GETH1 */
+#define UEC_VERBOSE_DEBUG	1
+#endif
+
+#ifdef CONFIG_UEC_ETH1
+#define CONFIG_SYS_UEC1_UCC_NUM	3	/* UCC4 */
+#define CONFIG_SYS_UEC1_RX_CLK		QE_CLK_NONE /* not used in RMII Mode */
+#define CONFIG_SYS_UEC1_TX_CLK		QE_CLK17
+#define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
+#define CONFIG_SYS_UEC1_PHY_ADDR	0
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE	PHY_INTERFACE_MODE_RMII
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED	100
+#endif
+
+/*
+ * Environment
+ */
+
+#ifndef CONFIG_SYS_RAMBOOT
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + \
+					CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env */
+#define CONFIG_ENV_OFFSET	(CONFIG_SYS_MONITOR_LEN)
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
+						CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+#else /* CFG_SYS_RAMBOOT */
+#define CONFIG_SYS_NO_FLASH		/* Flash is not usable now */
+#define CONFIG_ENV_IS_NOWHERE		/* Store ENV in memory only */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
+#define CONFIG_ENV_SIZE		0x2000
+#endif /* CFG_SYS_RAMBOOT */
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_NUM_I2C_BUSES	4
+#define CONFIG_SYS_I2C_MAX_HOPS		1
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	200000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_I2C_OFFSET		0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	200000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+#define CONFIG_SYS_I2C_BUSES	{{0, {I2C_NULL_HOP} }, \
+		{0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
+		{0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
+		{1, {I2C_NULL_HOP} } }
+
+#define CONFIG_KM_IVM_BUS		2	/* I2C2 (Mux-Port 1)*/
+
+/* I2C SYSMON (LM75, AD7414 is almost compatible) */
+#define CONFIG_DTT_LM75		/* ON Semi's LM75 */
+#define CONFIG_DTT_SENSORS	{0, 1, 2, 3}	/* Sensor addresses */
+#define CONFIG_SYS_DTT_MAX_TEMP	70
+#define CONFIG_SYS_DTT_HYSTERESIS	3
+#define CONFIG_SYS_DTT_BUS_NUM		1
+
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_NAND_KMETER1
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		CONFIG_SYS_KMBEC_FPGA_BASE
+#endif
+
+#if defined(CONFIG_PCI)
+#define CONFIG_CMD_PCI
+#endif
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)
+
+/*
+ * Core HID Setup
+ */
+#define CONFIG_SYS_HID0_INIT		0x000000000
+#define CONFIG_SYS_HID0_FINAL		(HID0_ENABLE_MACHINE_CHECK | \
+					 HID0_ENABLE_INSTRUCTION_CACHE)
+#define CONFIG_SYS_HID2			HID2_HBE
+
+/*
+ * MMU Setup
+ */
+
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
+/* DDR: cache cacheable */
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
+				BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
+					BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+
+/* IMMRBAR & PCI IO: cache-inhibit and guarded */
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR | BATL_PP_RW | \
+				BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \
+					| BATU_VP)
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+
+/* PRIO1, PIGGY:  icache cacheable, but dcache-inhibit and guarded */
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
+				BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \
+				BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
+				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+
+/* FLASH: icache cacheable, but dcache-inhibit and guarded */
+#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
+					BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \
+					BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT3L	(CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
+				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
+
+/* Stack in dcache: cacheable, no memory coherence */
+#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
+#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
+					BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
+#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
+
+/*
+ * Internal Definitions
+ */
+#define BOOTFLASH_START	0xF0000000
+
+#define CONFIG_KM_CONSOLE_TTY	"ttyS0"
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+#ifndef CONFIG_KM_DEF_ENV		/* if not set by keymile-common.h */
+#define CONFIG_KM_DEF_ENV "km-common=empty\0"
+#endif
+
+#ifndef CONFIG_KM_DEF_ARCH
+#define CONFIG_KM_DEF_ARCH	"arch=ppc_82xx\0"
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	CONFIG_KM_DEF_ENV						\
+	CONFIG_KM_DEF_ARCH						\
+	"newenv="							\
+		"prot off 0xF00C0000 +0x40000 && "			\
+		"era 0xF00C0000 +0x40000\0"				\
+	"unlock=yes\0"							\
+	""
+
+#if defined(CONFIG_UEC_ETH)
+#define CONFIG_HAS_ETH0
+#endif
+
+#endif /* __CONFIG_KM83XX_H */
diff --git a/qemu/roms/u-boot/include/configs/km/km_arm.h b/qemu/roms/u-boot/include/configs/km/km_arm.h
new file mode 100644
index 000000000..6d77680c8
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/km/km_arm.h
@@ -0,0 +1,338 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * (C) Copyright 2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2010-2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * for linking errors see
+ * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html
+ */
+
+#ifndef _CONFIG_KM_ARM_H
+#define _CONFIG_KM_ARM_H
+
+/* We got removed from Linux mach-types.h */
+#define MACH_TYPE_KM_KIRKWOOD          2255
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_MARVELL
+#define CONFIG_FEROCEON_88FR131		/* CPU Core subversion */
+#define CONFIG_KIRKWOOD			/* SOC Family Name */
+#define CONFIG_KW88F6281		/* SOC Name */
+#define CONFIG_MACH_KM_KIRKWOOD		/* Machine type */
+
+#define CONFIG_MACH_TYPE	MACH_TYPE_KM_KIRKWOOD
+
+#define CONFIG_NAND_ECC_BCH
+#define CONFIG_BCH
+
+/* include common defines/options for all Keymile boards */
+#include "keymile-common.h"
+
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_SF
+
+/* SPI NOR Flash default params, used by sf commands */
+#define CONFIG_SF_DEFAULT_SPEED		8100000
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3
+
+#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR
+#define CONFIG_ENV_SPI_BUS		0
+#define CONFIG_ENV_SPI_CS		0
+#define CONFIG_ENV_SPI_MAX_HZ		8100000
+#define CONFIG_ENV_SPI_MODE		SPI_MODE_3
+#endif
+
+/* Reserve 4 MB for malloc */
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+
+#include "asm/arch/config.h"
+
+#define CONFIG_SYS_TEXT_BASE	0x07d00000	/* code address before reloc */
+#define CONFIG_SYS_MEMTEST_START 0x00400000	/* 4M */
+#define CONFIG_SYS_MEMTEST_END	0x007fffff	/*(_8M -1) */
+#define CONFIG_SYS_LOAD_ADDR	0x00800000	/* default load adr- 8M */
+
+/* pseudo-non volatile RAM [hex] */
+#define CONFIG_KM_PNVRAM	0x80000
+/* physical RAM MTD size [hex] */
+#define CONFIG_KM_PHRAM		0x17F000
+
+#define CONFIG_KM_CRAMFS_ADDR	0x2400000
+#define CONFIG_KM_KERNEL_ADDR	0x2000000	/* 3098KBytes */
+#define CONFIG_KM_FDT_ADDR	0x23E0000	/*  128KBytes */
+
+/* architecture specific default bootargs */
+#define CONFIG_KM_DEF_BOOT_ARGS_CPU					\
+		"bootcountaddr=${bootcountaddr} ${mtdparts}"		\
+		" boardid=0x${IVM_BoardId} hwkey=0x${IVM_HWKey}"
+
+#define CONFIG_KM_DEF_ENV_CPU						\
+	"u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.kwb\0"		\
+	CONFIG_KM_UPDATE_UBOOT						\
+	"set_fdthigh=setenv fdt_high ${kernelmem}\0"			\
+	""
+
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+#define CONFIG_MISC_INIT_R
+
+/* Pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_TCLK
+#define CONFIG_SYS_NS16550_COM1		KW_UART0_BASE
+#define CONFIG_SYS_NS16550_COM2		KW_UART1_BASE
+
+/*
+ * Serial Port configuration
+ * The following definitions let you select what serial you want to use
+ * for your console driver.
+ */
+
+#define CONFIG_CONS_INDEX	1	/* Console on UART0 */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_BOOTMAPSZ	(8 << 20)	/* Initial Memmap for Linux */
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs  */
+#define CONFIG_INITRD_TAG		/* enable INITRD tag */
+#define CONFIG_SETUP_MEMORY_TAGS	/* enable memory tag */
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_NFS
+
+/*
+ * Without NOR FLASH we need this
+ */
+#define CONFIG_SYS_NO_FLASH
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+
+/*
+ * NAND Flash configuration
+ */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+
+#define BOOTFLASH_START		0x0
+
+/* Kirkwood has two serial IF */
+#if (CONFIG_CONS_INDEX == 2)
+#define CONFIG_KM_CONSOLE_TTY	"ttyS1"
+#else
+#define CONFIG_KM_CONSOLE_TTY	"ttyS0"
+#endif
+
+/*
+ * Other required minimal configurations
+ */
+#define CONFIG_CONSOLE_INFO_QUIET	/* some code reduction */
+#define CONFIG_ARCH_CPU_INIT		/* call arch_cpu_init() */
+#define CONFIG_ARCH_MISC_INIT		/* call arch_misc_init() */
+#define CONFIG_DISPLAY_CPUINFO		/* Display cpu info */
+#define CONFIG_NR_DRAM_BANKS	4
+#define CONFIG_SYS_RESET_ADDRESS 0xffff0000	/* Rst Vector Adr */
+
+/*
+ * Ethernet Driver configuration
+ */
+#define CONFIG_NETCONSOLE	/* include NetConsole support   */
+#define CONFIG_MII		/* expose smi ove miiphy interface */
+#define CONFIG_CMD_MII		/* to debug mdio phy config */
+#define CONFIG_MVGBE		/* Enable Marvell Gbe Controller Driver */
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	/* detect link using phy */
+#define CONFIG_MVGBE_PORTS	{1, 0}	/* enable port 0 only */
+#define CONFIG_PHY_BASE_ADR	0
+#define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
+#define CONFIG_KM_COMMON_ETH_INIT /* standard km ethernet_present for piggy */
+
+/*
+ * UBI related stuff
+ */
+#define CONFIG_SYS_USE_UBI
+
+/*
+ * I2C related stuff
+ */
+#undef CONFIG_I2C_MVTWSI
+#define CONFIG_SYS_I2C
+#define	CONFIG_SYS_I2C_SOFT	/* I2C bit-banged	*/
+#define CONFIG_SYS_I2C_INIT_BOARD
+
+#define	CONFIG_KIRKWOOD_GPIO		/* Enable GPIO Support */
+#define CONFIG_SYS_NUM_I2C_BUSES	6
+#define CONFIG_SYS_I2C_MAX_HOPS		1
+#define CONFIG_SYS_I2C_BUSES	{	{0, {I2C_NULL_HOP} }, \
+					{0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
+					{0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
+					{0, {{I2C_MUX_PCA9547, 0x70, 3} } }, \
+					{0, {{I2C_MUX_PCA9547, 0x70, 4} } }, \
+					{0, {{I2C_MUX_PCA9547, 0x70, 5} } }, \
+				}
+
+#ifndef __ASSEMBLY__
+#include <asm/arch-kirkwood/gpio.h>
+extern void __set_direction(unsigned pin, int high);
+void set_sda(int state);
+void set_scl(int state);
+int get_sda(void);
+int get_scl(void);
+#define KM_KIRKWOOD_SDA_PIN	8
+#define KM_KIRKWOOD_SCL_PIN	9
+#define KM_KIRKWOOD_SOFT_I2C_GPIOS	0x0300
+#define KM_KIRKWOOD_ENV_WP	38
+
+#define I2C_ACTIVE	__set_direction(KM_KIRKWOOD_SDA_PIN, 0)
+#define I2C_TRISTATE	__set_direction(KM_KIRKWOOD_SDA_PIN, 1)
+#define I2C_READ	(kw_gpio_get_value(KM_KIRKWOOD_SDA_PIN) ? 1 : 0)
+#define I2C_SDA(bit)	kw_gpio_set_value(KM_KIRKWOOD_SDA_PIN, bit)
+#define I2C_SCL(bit)	kw_gpio_set_value(KM_KIRKWOOD_SCL_PIN, bit)
+#endif
+
+#define I2C_DELAY	udelay(1)
+#define I2C_SOFT_DECLARATIONS
+
+#define	CONFIG_SYS_I2C_SOFT_SLAVE	0x0
+#define	CONFIG_SYS_I2C_SOFT_SPEED	100000
+
+/* EEprom support 24C128, 24C256 valid for environment eeprom */
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6 /* 64 Byte write page */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+
+/*
+ *  Environment variables configurations
+ */
+#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR
+#define CONFIG_ENV_IS_IN_SPI_FLASH  /* use SPI-Flash for environment vars */
+#define CONFIG_ENV_OFFSET		0xc0000     /* no bracets! */
+#define CONFIG_ENV_SIZE			0x02000     /* Size of Environment */
+#define CONFIG_ENV_SECT_SIZE		0x10000
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
+					CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_TOTAL_SIZE		0x20000     /* no bracets! */
+#else
+#define CONFIG_ENV_IS_IN_EEPROM		/* use EEPROM for environment vars */
+#define CONFIG_SYS_DEF_EEPROM_ADDR	0x50
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_EEPROM_WREN
+#define CONFIG_ENV_OFFSET		0x0 /* no bracets! */
+#define CONFIG_ENV_SIZE			(0x2000 - CONFIG_ENV_OFFSET)
+#define CONFIG_I2C_ENV_EEPROM_BUS	KM_ENV_BUS
+#define CONFIG_ENV_OFFSET_REDUND	0x2000 /* no bracets! */
+#define CONFIG_ENV_SIZE_REDUND		(CONFIG_ENV_SIZE)
+#endif
+
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+
+/* SPI bus claim MPP configuration */
+#define CONFIG_SYS_KW_SPI_MPP	0x0
+
+#define FLASH_GPIO_PIN			0x00010000
+#define KM_FLASH_GPIO_PIN	16
+
+#ifndef MTDIDS_DEFAULT
+# define MTDIDS_DEFAULT		"nand0=orion_nand"
+#endif /* MTDIDS_DEFAULT */
+
+#ifndef MTDPARTS_DEFAULT
+# define MTDPARTS_DEFAULT	"mtdparts="			\
+	"orion_nand:"						\
+		"-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");"
+#endif /* MTDPARTS_DEFAULT */
+
+#define	CONFIG_KM_UPDATE_UBOOT						\
+	"update="							\
+		"sf probe 0;sf erase 0 +${filesize};"			\
+		"sf write ${load_addr_r} 0 ${filesize};\0"
+
+#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR
+#define CONFIG_KM_NEW_ENV						\
+	"newenv=sf probe 0;"						\
+		"sf erase " __stringify(CONFIG_ENV_OFFSET) " "		\
+		__stringify(CONFIG_ENV_TOTAL_SIZE)"\0"
+#else
+#define CONFIG_KM_NEW_ENV						\
+	"newenv=setenv addr 0x100000 && "				\
+		"i2c dev " __stringify(CONFIG_I2C_ENV_EEPROM_BUS) "; "  \
+		"mw.b ${addr} 0 4 && "					\
+		"eeprom write " __stringify(CONFIG_SYS_DEF_EEPROM_ADDR)	\
+		" ${addr} " __stringify(CONFIG_ENV_OFFSET) " 4 && "	\
+		"eeprom write " __stringify(CONFIG_SYS_DEF_EEPROM_ADDR)	\
+		" ${addr} " __stringify(CONFIG_ENV_OFFSET_REDUND) " 4\0"
+#endif
+
+#ifndef CONFIG_KM_BOARD_EXTRA_ENV
+#define CONFIG_KM_BOARD_EXTRA_ENV       ""
+#endif
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_KM_BOARD_EXTRA_ENV					\
+	CONFIG_KM_DEF_ENV						\
+	CONFIG_KM_NEW_ENV						\
+	"arch=arm\0"							\
+	""
+
+#if defined(CONFIG_SYS_NO_FLASH)
+#undef	CONFIG_FLASH_CFI_MTD
+#undef	CONFIG_JFFS2_CMDLINE
+#endif
+
+/* additions for new relocation code, must be added to all boards */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+/* Do early setups now in board_init_f() */
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/*
+ * resereved pram area at the end of memroy [hex]
+ * 8Mbytes for switch + 4Kbytes for bootcount
+ */
+#define CONFIG_KM_RESERVED_PRAM 0x801000
+/* address for the bootcount (taken from end of RAM) */
+#define BOOTCOUNT_ADDR          (CONFIG_KM_RESERVED_PRAM)
+/* Use generic bootcount RAM driver */
+#define CONFIG_BOOTCOUNT_RAM
+
+/* enable POST tests */
+#define CONFIG_POST	(CONFIG_SYS_POST_MEM_REGIONS)
+#define CONFIG_POST_SKIP_ENV_FLAGS
+#define CONFIG_POST_EXTERNAL_WORD_FUNCS
+#define CONFIG_CMD_DIAG
+
+/* we do the whole PCIe FPGA config stuff here */
+#define	CONFIG_BOARD_LATE_INIT
+
+#endif /* _CONFIG_KM_ARM_H */
diff --git a/qemu/roms/u-boot/include/configs/km/kmp204x-common.h b/qemu/roms/u-boot/include/configs/km/kmp204x-common.h
new file mode 100644
index 000000000..efd96352e
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/km/kmp204x-common.h
@@ -0,0 +1,465 @@
+/*
+ * (C) Copyright 2013 Keymile AG
+ * Valentin Longchamp <valentin.longchamp@keymile.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CONFIG_KMP204X_H
+#define _CONFIG_KMP204X_H
+
+#define CONFIG_PHYS_64BIT
+#define CONFIG_PPC_P2041
+
+#define CONFIG_SYS_TEXT_BASE	0xfff80000
+
+#define CONFIG_KM_DEF_NETDEV	"netdev=eth0\0"
+
+/* an additionnal option is required for UBI as subpage access is
+ * supported in u-boot */
+#define CONFIG_KM_UBI_PART_BOOT_OPTS		",2048"
+
+#define CONFIG_NAND_ECC_BCH
+
+/* common KM defines */
+#include "keymile-common.h"
+
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_RAMBOOT_PBL
+#define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
+#define CONFIG_SYS_FSL_PBL_PBI board/keymile/kmp204x/pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW board/keymile/kmp204x/rcw_kmp204x.cfg
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE
+#define CONFIG_E500			/* BOOKE e500 family */
+#define CONFIG_E500MC			/* BOOKE e500mc family */
+#define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
+#define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
+#define CONFIG_MP			/* support multiple processors */
+
+#define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC		CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_FSL_ELBC			/* Has Enhanced localbus controller */
+#define CONFIG_PCI			/* Enable PCI/PCIE */
+#define CONFIG_PCIE1			/* PCIE controler 1 */
+#define CONFIG_PCIE3			/* PCIE controler 3 */
+#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
+
+#define CONFIG_SYS_DPAA_RMAN		/* RMan */
+
+#define CONFIG_FSL_LAW			/* Use common FSL init code */
+
+/* Environment in SPI Flash */
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS              0
+#define CONFIG_ENV_SPI_CS               0
+#define CONFIG_ENV_SPI_MAX_HZ           20000000
+#define CONFIG_ENV_SPI_MODE             0
+#define CONFIG_ENV_OFFSET               0x100000	/* 1MB for u-boot */
+#define CONFIG_ENV_SIZE			0x004000	/* 16K env */
+#define CONFIG_ENV_SECT_SIZE            0x010000
+#define CONFIG_ENV_OFFSET_REDUND	0x110000
+#define CONFIG_ENV_TOTAL_SIZE		0x020000
+
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(unsigned long dummy);
+#endif
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0)
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BACKSIDE_L2_CACHE
+#define CONFIG_SYS_INIT_L2CSR0		L2CSR0_L2E
+#define CONFIG_BTB			/* toggle branch predition */
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP		64	/* number of TLB1 entries */
+
+#define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS	/* POST memory regions test */
+
+/*
+ *  Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR		CONFIG_RAMBOOT_TEXT_BASE
+#define CONFIG_SYS_INIT_L3_ADDR_PHYS	(0xf00000000ull | \
+		CONFIG_RAMBOOT_TEXT_BASE)
+#define CONFIG_SYS_L3_SIZE		(1024 << 10)
+#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
+
+#define CONFIG_SYS_DCSRBAR		0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(4 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_FSL_DDR3
+#define CONFIG_FSL_DDR_INTERACTIVE
+
+#define CONFIG_SYS_SPD_BUS_NUM	0
+#define SPD_EEPROM_ADDRESS	0x54
+#define CONFIG_SYS_SDRAM_SIZE	4096	/* for fixed parameter use */
+
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+
+/******************************************************************************
+ * (PRAM usage)
+ * ... -------------------------------------------------------
+ * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM
+ * ... |<------------------- pram -------------------------->|
+ * ... -------------------------------------------------------
+ * @END_OF_RAM:
+ * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose
+ * @CONFIG_KM_PHRAM: address for /var
+ * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application)
+ * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM
+ */
+
+/* size of rootfs in RAM */
+#define CONFIG_KM_ROOTFSSIZE	0x0
+/* pseudo-non volatile RAM [hex] */
+#define CONFIG_KM_PNVRAM	0x80000
+/* physical RAM MTD size [hex] */
+#define CONFIG_KM_PHRAM		0x100000
+/* reserved pram area at the end of memory [hex]
+ * u-boot reserves some memory for the MP boot page */
+#define CONFIG_KM_RESERVED_PRAM	0x1000
+/* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable
+ * is not valid yet, which is the case for when u-boot copies itself to RAM */
+#define CONFIG_PRAM		((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM)>>10)
+
+#define CONFIG_KM_CRAMFS_ADDR	0x2000000
+#define CONFIG_KM_KERNEL_ADDR	0x1000000	/* max kernel size 15.5Mbytes */
+#define CONFIG_KM_FDT_ADDR	0x1F80000	/* max dtb    size  0.5Mbytes */
+
+/*
+ * Local Bus Definitions
+ */
+
+/* Set the local bus clock 1/8 of plat clk, 2 clk delay LALE */
+#define CONFIG_SYS_LBC_LCRR		(LCRR_CLKDIV_8 | LCRR_EADC_2)
+
+/* Nand Flash */
+#define CONFIG_NAND_FSL_ELBC
+#define CONFIG_SYS_NAND_BASE		0xffa00000
+#define CONFIG_SYS_NAND_BASE_PHYS	0xfffa00000ull
+
+#define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+#define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
+
+#define CONFIG_BCH
+
+/* NAND flash config */
+#define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+			       | BR_PS_8	       /* Port Size = 8 bit */ \
+			       | BR_MS_FCM	       /* MSEL = FCM */ \
+			       | BR_V)		       /* valid */
+
+#define CONFIG_SYS_NAND_OR_PRELIM  (OR_AM_256KB	      /* length 256K */ \
+			       | OR_FCM_BCTLD	/* LBCTL not ass */	\
+			       | OR_FCM_SCY_1	/* 1 clk wait cycle */	\
+			       | OR_FCM_RST	/* 1 clk read setup */	\
+			       | OR_FCM_PGS	/* Large page size */	\
+			       | OR_FCM_CST)	/* 0.25 command setup */
+
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+
+/* QRIO FPGA */
+#define CONFIG_SYS_QRIO_BASE		0xfb000000
+#define CONFIG_SYS_QRIO_BASE_PHYS	0xffb000000ull
+
+#define CONFIG_SYS_QRIO_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE_PHYS) \
+				| BR_PS_8	/* Port Size 8 bits */ \
+				| BR_DECC_OFF	/* no error corr */ \
+				| BR_MS_GPCM	/* MSEL = GPCM */ \
+				| BR_V)		/* valid */
+
+#define CONFIG_SYS_QRIO_OR_PRELIM  (OR_AM_64KB	/* length 64K */ \
+				| OR_GPCM_BCTLD /* no LCTL assert */ \
+				| OR_GPCM_ACS_DIV4 /* LCS 1/4 clk after */ \
+				| OR_GPCM_SCY_2 /* 2 clk wait cycles */ \
+				| OR_GPCM_TRLX /* relaxed tmgs */ \
+				| OR_GPCM_EAD) /* extra bus clk cycles */
+
+#define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */
+#define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */
+
+/* bootcounter in QRIO */
+#define CONFIG_BOOTCOUNT_LIMIT
+#define CONFIG_SYS_BOOTCOUNT_ADDR	(CONFIG_SYS_QRIO_BASE + 0x20)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
+#define CONFIG_MISC_INIT_F
+#define CONFIG_MISC_INIT_R
+#define CONFIG_LAST_STAGE_INIT
+
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
+
+#define CONFIG_KM_CONSOLE_TTY	"ttyS0"
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
+
+/* I2C */
+
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_INIT_BOARD
+#define CONFIG_SYS_I2C_SPEED		100000 /* deblocking */
+#define CONFIG_SYS_NUM_I2C_BUSES	3
+#define CONFIG_SYS_I2C_MAX_HOPS		1
+#define CONFIG_SYS_I2C_FSL		/* Use FSL I2C driver */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
+#define CONFIG_SYS_I2C_BUSES	{	{0, {I2C_NULL_HOP} }, \
+					{0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
+					{0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \
+				}
+#ifndef __ASSEMBLY__
+void set_sda(int state);
+void set_scl(int state);
+int get_sda(void);
+int get_scl(void);
+#endif
+
+#define CONFIG_KM_IVM_BUS		1	/* I2C1 (Mux-Port 1)*/
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#define CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_BAR	/* 4 byte-addressing */
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED         20000000
+#define CONFIG_SF_DEFAULT_MODE          0
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 3, Slot 1, tgtid 1, Base address 202000 */
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc20000000ull
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8010000
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8010000ull
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
+
+/* Qman/Bman */
+#define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS	10
+#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
+#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
+#define CONFIG_SYS_BMAN_MEM_SIZE	0x00200000
+#define CONFIG_SYS_QMAN_NUM_PORTALS	10
+#define CONFIG_SYS_QMAN_MEM_BASE	0xf4200000
+#define CONFIG_SYS_QMAN_MEM_PHYS	0xff4200000ull
+#define CONFIG_SYS_QMAN_MEM_SIZE	0x00200000
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+/* Default address of microcode for the Linux Fman driver
+ * env is stored at 0x100000, sector size is 0x10000, x2 (redundant)
+ * ucode is stored after env, so we got 0x120000.
+ */
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_FMAN_FW_ADDR	0x120000
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_MARVELL		/* there is a marvell phy */
+
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+#define CONFIG_E1000
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+
+/* RGMII (FM1@DTESC5) is used as debug itf, it's the only one configured */
+#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR	0x11
+#define CONFIG_SYS_TBIPA_VALUE	8
+#define CONFIG_PHYLIB		/* recommended PHY management */
+#define CONFIG_ETHPRIME		"FM1@DTSEC5"
+#define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
+
+/*
+ * Environment
+ */
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+ * additionnal command line configuration.
+ */
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_ERRATA
+
+/* we don't need flash support */
+#define CONFIG_SYS_NO_FLASH
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_FLASH_CFI_MTD
+#undef CONFIG_JFFS2_CMDLINE
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory for Linux */
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+#define __USB_PHY_TYPE	utmi
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+#ifndef CONFIG_KM_DEF_ENV		/* if not set by keymile-common.h */
+#define CONFIG_KM_DEF_ENV "km-common=empty\0"
+#endif
+
+#ifndef MTDIDS_DEFAULT
+# define MTDIDS_DEFAULT		"nand0=fsl_elbc_nand"
+#endif /* MTDIDS_DEFAULT */
+
+#ifndef MTDPARTS_DEFAULT
+# define MTDPARTS_DEFAULT	"mtdparts="			\
+	"fsl_elbc_nand:"						\
+		"-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");"
+#endif /* MTDPARTS_DEFAULT */
+
+/* architecture specific default bootargs */
+#define CONFIG_KM_DEF_BOOT_ARGS_CPU		""
+
+/* FIXME: FDT_ADDR is unspecified */
+#define CONFIG_KM_DEF_ENV_CPU						\
+	"boot=bootm ${load_addr_r} - ${fdt_addr_r}\0"			\
+	"cramfsloadfdt="						\
+		"cramfsload ${fdt_addr_r} "				\
+		"fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0"		\
+	"fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0"		\
+	"u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.pbl\0"		\
+	"update="							\
+		"sf probe 0;sf erase 0 +${filesize};"			\
+		"sf write ${load_addr_r} 0 ${filesize};\0"		\
+	"set_fdthigh=true\0"						\
+	""
+
+#define CONFIG_HW_ENV_SETTINGS						\
+	"hwconfig=fsl_ddr:ctlr_intlv=cacheline\0"			\
+	"usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0"		\
+	"usb_dr_mode=host\0"
+
+#define CONFIG_KM_NEW_ENV						\
+	"newenv=sf probe 0;"						\
+		"sf erase " __stringify(CONFIG_ENV_OFFSET) " "		\
+		__stringify(CONFIG_ENV_TOTAL_SIZE)"\0"
+
+/* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */
+#ifndef CONFIG_KM_DEF_ARCH
+#define CONFIG_KM_DEF_ARCH	"arch=ppc_82xx\0"
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_KM_DEF_ENV						\
+	CONFIG_KM_DEF_ARCH						\
+	CONFIG_KM_NEW_ENV						\
+	CONFIG_HW_ENV_SETTINGS						\
+	"EEprom_ivm=pca9547:70:9\0"					\
+	""
+
+#endif /* _CONFIG_KMP204X_H */
diff --git a/qemu/roms/u-boot/include/configs/km82xx.h b/qemu/roms/u-boot/include/configs/km82xx.h
new file mode 100644
index 000000000..029c34828
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/km82xx.h
@@ -0,0 +1,440 @@
+/*
+ * (C) Copyright 2007-2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC8247
+/* MGCOGE */
+#if defined(CONFIG_MGCOGE)
+#define CONFIG_HOSTNAME		mgcoge
+#define CONFIG_KM_BOARD_EXTRA_ENV	""
+
+/* MGCOGE3NE */
+#elif defined(CONFIG_MGCOGE3NE)
+#define CONFIG_HOSTNAME		mgcoge3ne
+#define CONFIG_KM_82XX
+#define CONFIG_KM_BOARD_EXTRA_ENV	"bobcatreset=true\0"
+
+#else
+#error ("Board unsupported")
+#endif
+
+#define	CONFIG_SYS_TEXT_BASE	0xFE000000
+
+/* include common defines/options for all Keymile boards */
+#include "km/keymile-common.h"
+#include "km/km-powerpc.h"
+
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFE000000
+#define CONFIG_SYS_FLASH_SIZE		32
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+
+/* MGCOGE */
+#if defined(CONFIG_MGCOGE)
+#define CONFIG_SYS_MAX_FLASH_BANKS	3
+/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_SECT	512
+
+#define CONFIG_SYS_FLASH_BASE_1	0x50000000
+#define CONFIG_SYS_FLASH_SIZE_1	32
+#define CONFIG_SYS_FLASH_BASE_2	0x52000000
+#define CONFIG_SYS_FLASH_SIZE_2	32
+
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
+					CONFIG_SYS_FLASH_BASE_1, \
+					CONFIG_SYS_FLASH_BASE_2 }
+#define MTDIDS_DEFAULT		"nor3=app"
+
+/*
+ * Bank 1 - 60x bus SDRAM
+ */
+#define SDRAM_MAX_SIZE	0x08000000			/* max. 128 MB	*/
+#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT	(256 << 20)	/* less than 256 MB */
+
+/* SDRAM initialization values
+*/
+
+#define CONFIG_SYS_OR1	((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & \
+			   ORxS_SDAM_MSK)		|\
+			ORxS_BPD_8			|\
+			ORxS_ROWST_PBI0_A7		|\
+			ORxS_NUMR_13)
+
+#define CONFIG_SYS_PSDMR (				\
+			PSDMR_SDAM_A14_IS_A5		|\
+			PSDMR_BSMA_A14_A16		|\
+			PSDMR_SDA10_PBI0_A9		|\
+			PSDMR_RFRC_5_CLK		|\
+			PSDMR_PRETOACT_2W		|\
+			PSDMR_ACTTORW_2W		|\
+			PSDMR_LDOTOPRE_1C		|\
+			PSDMR_WRC_1C			|\
+			PSDMR_CL_2)
+
+/* MGCOGE3NE */
+#elif defined(CONFIG_MGCOGE3NE)
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max num of flash banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/*
+						 * max num of sects on one
+						 * chip
+						 */
+
+#define CONFIG_SYS_FLASH_BASE_1	0x50000000
+#define CONFIG_SYS_FLASH_SIZE_1	128
+
+#define CONFIG_SYS_FLASH_SIZE_2 0	/* dummy value to calc SYS_OR5 */
+
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
+					CONFIG_SYS_FLASH_BASE_1 }
+
+#define MTDIDS_DEFAULT		"nor2=app"
+
+/*
+ * Bank 1 - 60x bus SDRAM
+ * mgcoge3ne has 256MB
+ * mgcoge2ne has 128MB
+ */
+#define SDRAM_MAX_SIZE 0x10000000			/* max. 256 MB	*/
+#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT	(512 << 20)	/* less than 512 MB */
+
+#define CONFIG_SYS_OR1	((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & \
+			   ORxS_SDAM_MSK)		|\
+			ORxS_BPD_4			|\
+			ORxS_NUMR_13			|\
+			ORxS_IBID)
+
+#define CONFIG_SYS_PSDMR (				\
+			PSDMR_PBI			|\
+			PSDMR_RFEN			|\
+			PSDMR_BSMA_A13_A15		|\
+			PSDMR_RFRC_5_CLK		|\
+			PSDMR_PRETOACT_2W		|\
+			PSDMR_ACTTORW_2W		|\
+			PSDMR_LDOTOPRE_1C		|\
+			PSDMR_WRC_1C			|\
+			PSDMR_CL_2)
+
+#define CONFIG_SYS_SDRAM_LIST	{					\
+	{	.size	= 256 << 20,					\
+		.or1	= ORxS_ROWST_PBI1_A4,				\
+		.psdmr	= PSDMR_SDAM_A17_IS_A5 | PSDMR_SDA10_PBI1_A6,	\
+	},								\
+	{	.size	= 128 << 20,					\
+		.or1	= ORxS_ROWST_PBI1_A5,				\
+		.psdmr	= PSDMR_SDAM_A16_IS_A5 | PSDMR_SDA10_PBI1_A7,	\
+	},								\
+}
+#endif /* defined(CONFIG_MGCOGE3NE) */
+
+/* include further common stuff for all keymile 82xx boards */
+/*
+ * Select serial console configuration
+ *
+ * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ */
+#define	CONFIG_CONS_ON_SMC		/* Console is on SMC         */
+#undef  CONFIG_CONS_ON_SCC		/* It's not on SCC           */
+#undef	CONFIG_CONS_NONE		/* It's not on external UART */
+#define CONFIG_CONS_INDEX	2	/* SMC2 is used for console  */
+#define CONFIG_SYS_SMC_RXBUFLEN	128
+#define CONFIG_SYS_MAXIDLE	10
+
+/*
+ * Select ethernet configuration
+ *
+ * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
+ * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
+ * SCC, 1-3 for FCC)
+ *
+ * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
+ * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
+ * must be unset.
+ */
+#define	CONFIG_ETHER_ON_SCC		/* Ethernet is on SCC */
+#undef	CONFIG_ETHER_ON_FCC		/* Ethernet is not on FCC     */
+#undef	CONFIG_ETHER_NONE		/* No external Ethernet   */
+
+#define CONFIG_ETHER_INDEX	4
+#define CONFIG_HAS_ETH0
+#define CONFIG_SYS_SCC_TOUT_LOOP	10000000
+
+#define CONFIG_SYS_CMXSCR_VALUE	(CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8)
+
+#ifndef CONFIG_8260_CLKIN
+#define CONFIG_8260_CLKIN	66000000	/* in Hz */
+#endif
+
+#define BOOTFLASH_START		0xFE000000
+
+#define CONFIG_KM_CONSOLE_TTY	"ttyCPM0"
+
+#define MTDPARTS_DEFAULT	"mtdparts="				\
+	"app:"								\
+		"768k(u-boot),"						\
+		"128k(env),"						\
+		"128k(envred),"						\
+		"3072k(free),"						\
+		"-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ")"
+
+/*
+ * Default environment settings
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_KM_BOARD_EXTRA_ENV					\
+	CONFIG_KM_DEF_ENV						\
+	"unlock=yes\0"							\
+	"newenv="							\
+		"prot off 0xFE0C0000 +0x40000 && "			\
+		"era 0xFE0C0000 +0x40000\0"				\
+	"arch=ppc_82xx\0"					\
+	""
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN		(768 << 10)
+
+#define CONFIG_ENV_IS_IN_FLASH
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	0x20000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + \
+					CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_OFFSET	CONFIG_SYS_MONITOR_LEN
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
+						CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND		(CONFIG_ENV_SIZE)
+#endif /* CONFIG_ENV_IS_IN_FLASH */
+
+/* enable I2C and select the hardware/software driver */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
+#define CONFIG_SYS_I2C_INIT_BOARD
+#define CONFIG_SYS_NUM_I2C_BUSES	3
+#define CONFIG_SYS_I2C_MAX_HOPS		1
+#define CONFIG_SYS_I2C_SOFT_SPEED	50000
+#define CONFIG_SYS_I2C_SPEED		CONFIG_SYS_I2C_SOFT_SPEED
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0x7F
+#define CONFIG_SYS_I2C_BUSES	{{0, {I2C_NULL_HOP} }, \
+			{0, {{I2C_MUX_PCA9542, 0x70, 0} } }, \
+			{0, {{I2C_MUX_PCA9542, 0x70, 1} } } }
+
+#define CONFIG_KM_IVM_BUS		1	/* I2C2 (Mux-Port 1)*/
+#define CONFIG_KM_I2C_ABORT
+
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+
+#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
+#define I2C_ACTIVE	(iop->pdir |=  0x00010000)
+#define I2C_TRISTATE	(iop->pdir &= ~0x00010000)
+#define I2C_READ	((iop->pdat & 0x00010000) != 0)
+#define I2C_SDA(bit)	do { \
+				if (bit) \
+					iop->pdat |=  0x00010000; \
+				else \
+					iop->pdat &= ~0x00010000; \
+			} while (0)
+#define I2C_SCL(bit)	do { \
+				if (bit) \
+					iop->pdat |=  0x00020000; \
+				else \
+					iop->pdat &= ~0x00020000; \
+			} while (0)
+#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
+
+#ifndef __ASSEMBLY__
+void set_sda(int state);
+void set_scl(int state);
+int get_sda(void);
+int get_scl(void);
+#endif
+
+/* I2C SYSMON (LM75, AD7414 is almost compatible)			*/
+#define CONFIG_DTT_LM75			/* ON Semi's LM75		*/
+#define CONFIG_DTT_SENSORS	{0}	/* Sensor addresses		*/
+#define CONFIG_SYS_DTT_MAX_TEMP	70
+#define CONFIG_SYS_DTT_HYSTERESIS	3
+#define CONFIG_SYS_DTT_BUS_NUM		2
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+
+#define CONFIG_SYS_IMMR		0xF0000000
+
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000 /* used size in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+						GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/* Hard reset configuration word */
+#define CONFIG_SYS_HRCW_MASTER		0x0604b211
+
+/* No slaves */
+#define CONFIG_SYS_HRCW_SLAVE1		0
+#define CONFIG_SYS_HRCW_SLAVE2		0
+#define CONFIG_SYS_HRCW_SLAVE3		0
+#define CONFIG_SYS_HRCW_SLAVE4		0
+#define CONFIG_SYS_HRCW_SLAVE5		0
+#define CONFIG_SYS_HRCW_SLAVE6		0
+#define CONFIG_SYS_HRCW_SLAVE7		0
+
+/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)
+
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPUs */
+#if defined(CONFIG_CMD_KGDB)
+#  define CONFIG_SYS_CACHELINE_SHIFT	5 /* log base 2 of the above value */
+#endif
+
+#define CONFIG_SYS_HID0_INIT		0
+#define CONFIG_SYS_HID0_FINAL		(HID0_ICE | HID0_IFEM | HID0_ABE)
+
+#define CONFIG_SYS_HID2		0
+
+#define CONFIG_SYS_SIUMCR		0x4020c200
+#define CONFIG_SYS_SYPCR		0xFFFFFF83
+#define CONFIG_SYS_BCR			0x10000000
+#define CONFIG_SYS_SCCR		(SCCR_PCI_MODE | SCCR_PCI_MODCK)
+
+/*
+ *-----------------------------------------------------------------------
+ * RMR - Reset Mode Register                                     5-5
+ *-----------------------------------------------------------------------
+ * turn on Checkstop Reset Enable
+ */
+#define CONFIG_SYS_RMR         0
+
+/*
+ *-----------------------------------------------------------------------
+ * TMCNTSC - Time Counter Status and Control                     4-40
+ *-----------------------------------------------------------------------
+ * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
+ * and enable Time Counter
+ */
+#define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+
+/*
+ *-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control                 4-42
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
+ * Periodic timer
+ */
+#define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
+
+/*
+ *-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration                         13-7
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RCCR        0
+
+/*
+ * Init Memory Controller:
+ *
+ * Bank Bus     Machine PortSz  Device
+ * ---- ---     ------- ------  ------
+ *  0   60x     GPCM     8 bit  FLASH
+ *  1   60x     SDRAM   32 bit  SDRAM
+ *  3   60x     GPCM     8 bit  GPIO/PIGGY
+ *  5   60x     GPCM    16 bit  CFG-Flash
+ *
+ */
+/* Bank 0 - FLASH
+ */
+#define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)	|\
+			 BRx_PS_8			|\
+			 BRx_MS_GPCM_P			|\
+			 BRx_V)
+
+#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE)	|\
+			 ORxG_CSNT			|\
+			 ORxG_ACS_DIV2			|\
+			 ORxG_SCY_5_CLK			|\
+			 ORxG_TRLX)
+
+#define CONFIG_SYS_MPTPR       0x1800
+
+/*
+ *-----------------------------------------------------------------------------
+ * Address for Mode Register Set (MRS) command
+ *-----------------------------------------------------------------------------
+ */
+#define CONFIG_SYS_MRS_OFFS	0x00000110
+#define CONFIG_SYS_PSRT        0x0e
+
+#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
+			 BRx_PS_64		|\
+			 BRx_MS_SDRAM_P		|\
+			 BRx_V)
+
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR1
+
+/*
+ * UPIO FPGA (GPIO/PIGGY) on CS3 initialization values
+ */
+#define CONFIG_SYS_KMBEC_FPGA_BASE	0x30000000
+#define CONFIG_SYS_KMBEC_FPGA_SIZE	128
+
+#define CONFIG_SYS_BR3_PRELIM	((CONFIG_SYS_KMBEC_FPGA_BASE & BRx_BA_MSK) |\
+			 BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
+
+#define CONFIG_SYS_OR3_PRELIM	(MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) |\
+			 ORxG_CSNT | ORxG_ACS_DIV2 |\
+			 ORxG_SCY_3_CLK | ORxG_TRLX)
+
+/*
+ * BFTICU board FPGA on CS4 initialization values
+ */
+#define CONFIG_SYS_FPGA_BASE	0x40000000
+#define CONFIG_SYS_FPGA_SIZE	1 /*1KB*/
+
+#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_FPGA_BASE & BRx_BA_MSK) |\
+			BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
+
+#define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FPGA_SIZE << 10) |\
+			 ORxG_CSNT | ORxG_ACS_DIV2 |\
+			 ORxG_SCY_3_CLK | ORxG_TRLX)
+
+/*
+ * CFG-Flash on CS5 initialization values
+ */
+#define CONFIG_SYS_BR5_PRELIM	((CONFIG_SYS_FLASH_BASE_1 & BRx_BA_MSK) |\
+			 BRx_PS_16 | BRx_MS_GPCM_P | BRx_V)
+
+#define CONFIG_SYS_OR5_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE_1 + \
+				 CONFIG_SYS_FLASH_SIZE_2) |\
+				 ORxG_CSNT | ORxG_ACS_DIV2 |\
+				 ORxG_SCY_5_CLK | ORxG_TRLX)
+
+#define	CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC	/* "bad" address */
+
+/* pass open firmware flat tree */
+#define CONFIG_FIT		1
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+#define OF_TBCLK		(bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH		"/soc/cpm/serial@11a90"
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/km8360.h b/qemu/roms/u-boot/include/configs/km8360.h
new file mode 100644
index 000000000..f5ac32a33
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/km8360.h
@@ -0,0 +1,288 @@
+/*
+ * (C) Copyright 2012
+ * Holger Brunck, Keymile GmbH Hannover, <holger.brunck@keymile.com>
+ * Christian Herzig, Keymile AG Switzerland, <christian.herzig@keymile.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* KMBEC FPGA (PRIO) */
+#define CONFIG_SYS_KMBEC_FPGA_BASE	0xE8000000
+#define CONFIG_SYS_KMBEC_FPGA_SIZE	64
+
+#if defined CONFIG_KMETER1
+#define CONFIG_HOSTNAME		kmeter1
+#define CONFIG_KM_BOARD_NAME   "kmeter1"
+#define CONFIG_KM_DEF_NETDEV	"netdev=eth2\0"
+#elif defined CONFIG_KMCOGE5NE
+#define CONFIG_HOSTNAME		kmcoge5ne
+#define CONFIG_KM_BOARD_NAME	"kmcoge5ne"
+#define CONFIG_KM_DEF_NETDEV	"netdev=eth1\0"
+#define CONFIG_CMD_NAND
+#define CONFIG_NAND_ECC_BCH
+#define CONFIG_BCH
+#define CONFIG_NAND_KMETER1
+#define CONFIG_SYS_MAX_NAND_DEVICE		1
+#define NAND_MAX_CHIPS				1
+#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
+
+#define CONFIG_KM_UBI_PARTITION_NAME_BOOT	"ubi0"
+#define CONFIG_KM_UBI_PARTITION_NAME_APP	"ubi1"
+#define MTDIDS_DEFAULT			"nor0=boot,nand0=app"
+
+#define MTDPARTS_DEFAULT		"mtdparts="			\
+	"boot:"								\
+		"768k(u-boot),"						\
+		"128k(env),"						\
+		"128k(envred),"						\
+		"-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");"		\
+	"app:"								\
+		"-(" CONFIG_KM_UBI_PARTITION_NAME_APP ");"
+#else
+#error ("Board not supported")
+#endif
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_QE			/* Has QE */
+#define CONFIG_MPC8360			/* MPC8360 CPU specific */
+
+#define	CONFIG_SYS_TEXT_BASE	0xF0000000
+
+/* include common defines/options for all 83xx Keymile boards */
+#include "km/km83xx-common.h"
+
+/*
+ * System IO Setup
+ */
+#define CONFIG_SYS_SICRH		(SICRH_UC1EOBI | SICRH_UC2E1OBI)
+
+/*
+ * Hardware Reset Configuration Word
+ */
+#define CONFIG_SYS_HRCW_LOW (\
+	HRCWL_CSB_TO_CLKIN_4X1 | \
+	HRCWL_CORE_TO_CSB_2X1 | \
+	HRCWL_CE_PLL_VCO_DIV_2 | \
+	HRCWL_CE_TO_PLL_1X6)
+
+#define CONFIG_SYS_HRCW_HIGH (\
+	HRCWH_CORE_ENABLE | \
+	HRCWH_FROM_0X00000100 | \
+	HRCWH_BOOTSEQ_DISABLE | \
+	HRCWH_SW_WATCHDOG_DISABLE | \
+	HRCWH_ROM_LOC_LOCAL_16BIT | \
+	HRCWH_BIG_ENDIAN | \
+	HRCWH_LALE_EARLY | \
+	HRCWH_LDP_CLEAR)
+
+/**
+ * DDR RAM settings
+ */
+#define CONFIG_SYS_DDR_SDRAM_CFG (\
+	SDRAM_CFG_SDRAM_TYPE_DDR2 | \
+	SDRAM_CFG_SREN | \
+	SDRAM_CFG_HSE)
+
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
+
+#ifdef CONFIG_KMCOGE5NE
+/**
+ * KMCOGE5NE has 512 MB RAM
+ */
+#define CONFIG_SYS_DDR_CS0_CONFIG (\
+	CSCONFIG_EN | \
+	CSCONFIG_AP | \
+	CSCONFIG_ODT_RD_ONLY_CURRENT | \
+	CSCONFIG_BANK_BIT_3 | \
+	CSCONFIG_ROW_BIT_13 | \
+	CSCONFIG_COL_BIT_10)
+#else
+#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_AP | \
+					 CSCONFIG_ROW_BIT_13 | \
+					 CSCONFIG_COL_BIT_10 | \
+					 CSCONFIG_ODT_RD_ONLY_CURRENT)
+#endif
+
+#define CONFIG_SYS_DDR_CLK_CNTL (\
+	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+
+#define CONFIG_SYS_DDR_INTERVAL (\
+	(0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
+	(0x203 << SDRAM_INTERVAL_REFINT_SHIFT))
+
+#define CONFIG_SYS_DDR_CS0_BNDS			0x0000007f
+
+#define CONFIG_SYS_DDRCDR (\
+	DDRCDR_EN | \
+	DDRCDR_Q_DRN)
+#define CONFIG_SYS_DDR_MODE		0x47860452
+#define CONFIG_SYS_DDR_MODE2		0x8080c000
+
+#define CONFIG_SYS_DDR_TIMING_0 (\
+	(2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
+	(8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
+	(6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
+	(2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
+	(0 << TIMING_CFG0_WWT_SHIFT) | \
+	(0 << TIMING_CFG0_RRT_SHIFT) | \
+	(0 << TIMING_CFG0_WRT_SHIFT) | \
+	(0 << TIMING_CFG0_RWT_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_1	((TIMING_CFG1_CASLAT_50) | \
+				 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
+				 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
+				 (3 << TIMING_CFG1_WRREC_SHIFT) | \
+				 (7 << TIMING_CFG1_REFREC_SHIFT) | \
+				 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
+				 (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
+				 (3 << TIMING_CFG1_PRETOACT_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_2 (\
+	(0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \
+	(3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
+	(2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
+	(2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
+	(4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
+	(5 << TIMING_CFG2_CPO_SHIFT) | \
+	(0 << TIMING_CFG2_ADD_LAT_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_3			0x00000000
+
+/* EEprom support */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+
+/*
+ * Local Bus Configuration & Clock Setup
+ */
+#define CONFIG_SYS_LCRR_DBYP		LCRR_DBYP
+#define CONFIG_SYS_LCRR_EADC		LCRR_EADC_2
+#define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_4
+
+/*
+ * PAXE on the local bus CS3
+ */
+#define CONFIG_SYS_PAXE_BASE		0xA0000000
+#define CONFIG_SYS_PAXE_SIZE		256
+
+#define CONFIG_SYS_LBLAWBAR3_PRELIM	CONFIG_SYS_PAXE_BASE
+
+#define CONFIG_SYS_LBLAWAR3_PRELIM	0x8000001C /* 512MB window size */
+
+#define CONFIG_SYS_BR3_PRELIM (\
+	CONFIG_SYS_PAXE_BASE | \
+	(1 << BR_PS_SHIFT) | \
+	BR_V)
+
+#define CONFIG_SYS_OR3_PRELIM (\
+	MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \
+	OR_GPCM_CSNT | \
+	OR_GPCM_ACS_DIV2 | \
+	OR_GPCM_SCY_2 | \
+	OR_GPCM_TRLX | \
+	OR_GPCM_EAD)
+
+#ifdef CONFIG_KMCOGE5NE
+/*
+ * BFTIC3 on the local bus CS4
+ */
+#define CONFIG_SYS_BFTIC3_BASE			0xB0000000
+#define CONFIG_SYS_BFTIC3_SIZE			256
+
+#define CONFIG_SYS_BR4_PRELIM (\
+	CONFIG_SYS_BFTIC3_BASE |\
+	(1 << BR_PS_SHIFT) | \
+	BR_V)
+
+#define CONFIG_SYS_OR4_PRELIM (\
+	MEG_TO_AM(CONFIG_SYS_BFTIC3_SIZE) |\
+	OR_GPCM_CSNT | \
+	OR_GPCM_ACS_DIV2 |\
+	OR_GPCM_SCY_2 |\
+	OR_GPCM_TRLX |\
+	OR_GPCM_EAD)
+#endif
+
+/*
+ * MMU Setup
+ */
+
+/* PAXE:  icache cacheable, but dcache-inhibit and guarded */
+#define CONFIG_SYS_IBAT5L (\
+	CONFIG_SYS_PAXE_BASE | \
+	BATL_PP_10 | \
+	BATL_MEMCOHERENCE)
+
+#define CONFIG_SYS_IBAT5U (\
+	CONFIG_SYS_PAXE_BASE | \
+	BATU_BL_256M | \
+	BATU_VS | \
+	BATU_VP)
+
+#define CONFIG_SYS_DBAT5L (\
+	CONFIG_SYS_PAXE_BASE | \
+	BATL_PP_10 | \
+	BATL_CACHEINHIBIT | \
+	BATL_GUARDEDSTORAGE)
+
+#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
+
+
+#ifdef CONFIG_KMCOGE5NE
+/* BFTIC3:  icache cacheable, but dcache-inhibit and guarded */
+#define CONFIG_SYS_IBAT6L (\
+	CONFIG_SYS_BFTIC3_BASE | \
+	BATL_PP_10 | \
+	BATL_MEMCOHERENCE)
+
+#define CONFIG_SYS_IBAT6U (\
+	CONFIG_SYS_BFTIC3_BASE | \
+	BATU_BL_256M | \
+	BATU_VS | \
+	BATU_VP)
+
+#define CONFIG_SYS_DBAT6L (\
+	CONFIG_SYS_BFTIC3_BASE | \
+	BATL_PP_10 | \
+	BATL_CACHEINHIBIT | \
+	BATL_GUARDEDSTORAGE)
+
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
+
+/* DDR/LBC SDRAM next 256M: cacheable */
+#define CONFIG_SYS_IBAT7L (\
+	CONFIG_SYS_SDRAM_BASE2 |\
+	BATL_PP_10 |\
+	BATL_CACHEINHIBIT |\
+	BATL_GUARDEDSTORAGE)
+
+#define CONFIG_SYS_IBAT7U (\
+	CONFIG_SYS_SDRAM_BASE2 |\
+	BATU_BL_256M |\
+	BATU_VS |\
+	BATU_VP)
+/* enable POST tests */
+#define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS)
+#define CONFIG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */
+#define CPM_POST_WORD_ADDR  CONFIG_SYS_MEMTEST_END
+#define CONFIG_TESTPIN_REG  gprt3	/* for kmcoge5ne */
+#define CONFIG_TESTPIN_MASK 0x20	/* for kmcoge5ne */
+#define CONFIG_CMD_DIAG	/* so that testpin is inquired for POST test */
+
+#else
+#define CONFIG_SYS_IBAT6L	(0)
+#define CONFIG_SYS_IBAT6U	(0)
+#define CONFIG_SYS_IBAT7L	(0)
+#define CONFIG_SYS_IBAT7U	(0)
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
+#endif
+
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
+
+#endif /* CONFIG */
diff --git a/qemu/roms/u-boot/include/configs/km_kirkwood.h b/qemu/roms/u-boot/include/configs/km_kirkwood.h
new file mode 100644
index 000000000..9eb1ad339
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/km_kirkwood.h
@@ -0,0 +1,185 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * (C) Copyright 2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2011-2012
+ * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com
+ * Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * for linking errors see
+ * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html
+ */
+
+#ifndef _CONFIG_KM_KIRKWOOD_H
+#define _CONFIG_KM_KIRKWOOD_H
+
+/* KM_KIRKWOOD */
+#if defined(CONFIG_KM_KIRKWOOD)
+#define CONFIG_IDENT_STRING		"\nKeymile Kirkwood"
+#define CONFIG_HOSTNAME			km_kirkwood
+#define CONFIG_KM_DISABLE_PCIE
+#define CONFIG_KM_IVM_BUS		1	/* I2C2 (Mux-Port 1)*/
+
+/* KM_KIRKWOOD_PCI */
+#elif defined(CONFIG_KM_KIRKWOOD_PCI)
+#define CONFIG_IDENT_STRING		"\nKeymile Kirkwood PCI"
+#define CONFIG_HOSTNAME			km_kirkwood_pci
+#define CONFIG_KM_IVM_BUS		1	/* I2C2 (Mux-Port 1)*/
+#define CONFIG_KM_FPGA_CONFIG
+
+/* KM_KIRKWOOD_128M16 */
+#elif defined(CONFIG_KM_KIRKWOOD_128M16)
+#define CONFIG_IDENT_STRING		"\nKeymile Kirkwood 128M16"
+#define CONFIG_HOSTNAME			km_kirkwood_128m16
+#undef CONFIG_SYS_KWD_CONFIG
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
+#define CONFIG_KM_DISABLE_PCIE
+#define CONFIG_KM_IVM_BUS		1	/* I2C2 (Mux-Port 1)*/
+
+/* KM_NUSA / KM_SUGP1 */
+#elif defined(CONFIG_KM_NUSA) || defined(CONFIG_KM_SUGP1)
+#define CONFIG_KM_IVM_BUS		1	/* I2C2 (Mux-Port 1)*/
+
+# if defined(CONFIG_KM_NUSA)
+#define CONFIG_IDENT_STRING		"\nKeymile NUSA"
+#define CONFIG_HOSTNAME			kmnusa
+# elif defined(CONFIG_KM_SUGP1)
+#define CONFIG_IDENT_STRING		"\nKeymile SUGP1"
+#define CONFIG_HOSTNAME			kmsugp1
+#define KM_PCIE_RESET_MPP7
+#endif
+
+#undef CONFIG_SYS_KWD_CONFIG
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
+#define CONFIG_KM_ENV_IS_IN_SPI_NOR
+#define CONFIG_KM_FPGA_CONFIG
+#define CONFIG_KM_PIGGY4_88E6352
+#define CONFIG_MV88E6352_SWITCH
+#define CONFIG_KM_MVEXTSW_ADDR		0x10
+
+/* KM_MGCOGE3UN */
+#elif defined(CONFIG_KM_MGCOGE3UN)
+#define CONFIG_IDENT_STRING		"\nKeymile COGE3UN"
+#define CONFIG_HOSTNAME			mgcoge3un
+#define CONFIG_KM_IVM_BUS		1	/* I2C2 (Mux-Port 1)*/
+#undef CONFIG_SYS_KWD_CONFIG
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-memphis.cfg
+#define CONFIG_KM_BOARD_EXTRA_ENV	"waitforne=true\0"
+#define CONFIG_PIGGY_MAC_ADRESS_OFFSET  3
+#define CONFIG_KM_DISABLE_PCIE
+#define CONFIG_KM_PIGGY4_88E6061
+
+/* KMCOGE5UN */
+#elif defined(CONFIG_KM_COGE5UN)
+#define CONFIG_IDENT_STRING		"\nKeymile COGE5UN"
+#define CONFIG_KM_IVM_BUS		1	/* I2C2 (Mux-Port 1)*/
+#undef	CONFIG_SYS_KWD_CONFIG
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_256M8_1.cfg
+#define CONFIG_KM_ENV_IS_IN_SPI_NOR
+#define CONFIG_PIGGY_MAC_ADRESS_OFFSET	3
+#define CONFIG_HOSTNAME			kmcoge5un
+#define CONFIG_KM_DISABLE_PCIE
+#define CONFIG_KM_PIGGY4_88E6352
+
+/* KM_PORTL2 */
+#elif defined(CONFIG_KM_PORTL2)
+#define CONFIG_IDENT_STRING		"\nKeymile Port-L2"
+#define CONFIG_HOSTNAME			portl2
+#define CONFIG_KM_IVM_BUS		1	/* I2C2 (Mux-Port 1)*/
+#define CONFIG_KM_PIGGY4_88E6061
+
+/* KM_SUV31 */
+#elif defined(CONFIG_KM_SUV31)
+#define CONFIG_KM_IVM_BUS		1	/* I2C2 (Mux-Port 1)*/
+#define CONFIG_IDENT_STRING		"\nKeymile SUV31"
+#define CONFIG_HOSTNAME			kmsuv31
+#undef CONFIG_SYS_KWD_CONFIG
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
+#define CONFIG_KM_ENV_IS_IN_SPI_NOR
+#define CONFIG_KM_FPGA_CONFIG
+
+#else
+#error ("Board unsupported")
+#endif
+
+/* include common defines/options for all arm based Keymile boards */
+#include "km/km_arm.h"
+
+#ifndef CONFIG_KM_ENV_IS_IN_SPI_NOR
+#define KM_ENV_BUS	5	/* I2C2 (Mux-Port 5)*/
+#endif
+
+#if defined(CONFIG_KM_PIGGY4_88E6352)
+/*
+ * Some keymile boards like mgcoge5un & nusa1 have their PIGGY4 connected via
+ * an Marvell 88E6352 simple switch.
+ * In this case we have to change the default settings for the etherent mac.
+ * There is NO ethernet phy. The ARM and Switch are conencted directly over
+ * RGMII in MAC-MAC mode
+ * In this case 1GBit full duplex and autoneg off
+ */
+#define PORT_SERIAL_CONTROL_VALUE		( \
+	MVGBE_FORCE_LINK_PASS			    | \
+	MVGBE_DIS_AUTO_NEG_FOR_DUPLX		| \
+	MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL	| \
+	MVGBE_ADV_NO_FLOW_CTRL			    | \
+	MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX	| \
+	MVGBE_FORCE_BP_MODE_NO_JAM		    | \
+	(1 << 9) /* Reserved bit has to be 1 */	| \
+	MVGBE_DO_NOT_FORCE_LINK_FAIL		| \
+	MVGBE_DIS_AUTO_NEG_SPEED_GMII		| \
+	MVGBE_DTE_ADV_0				        | \
+	MVGBE_MIIPHY_MAC_MODE			    | \
+	MVGBE_AUTO_NEG_NO_CHANGE		    | \
+	MVGBE_MAX_RX_PACKET_1552BYTE		| \
+	MVGBE_CLR_EXT_LOOPBACK			    | \
+	MVGBE_SET_FULL_DUPLEX_MODE		    | \
+	MVGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	|\
+	MVGBE_SET_GMII_SPEED_TO_1000	    |\
+	MVGBE_SET_MII_SPEED_TO_100)
+
+#endif
+
+#ifdef CONFIG_KM_PIGGY4_88E6061
+/*
+ * Some keymile boards like mgcoge3un have their PIGGY4 connected via
+ * an Marvell 88E6061 simple switch.
+ * In this case we have to change the default settings for the
+ * ethernet phy connected to the kirkwood.
+ * In this case 100MB full duplex and autoneg off
+ */
+#define PORT_SERIAL_CONTROL_VALUE		( \
+	MVGBE_FORCE_LINK_PASS			| \
+	MVGBE_DIS_AUTO_NEG_FOR_DUPLX		| \
+	MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL	| \
+	MVGBE_ADV_NO_FLOW_CTRL			| \
+	MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX	| \
+	MVGBE_FORCE_BP_MODE_NO_JAM		| \
+	(1 << 9) /* Reserved bit has to be 1 */	| \
+	MVGBE_DO_NOT_FORCE_LINK_FAIL		| \
+	MVGBE_DIS_AUTO_NEG_SPEED_GMII		| \
+	MVGBE_DTE_ADV_0				| \
+	MVGBE_MIIPHY_MAC_MODE			| \
+	MVGBE_AUTO_NEG_NO_CHANGE		| \
+	MVGBE_MAX_RX_PACKET_1552BYTE		| \
+	MVGBE_CLR_EXT_LOOPBACK			| \
+	MVGBE_SET_FULL_DUPLEX_MODE		| \
+	MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	|\
+	MVGBE_SET_GMII_SPEED_TO_10_100	|\
+	MVGBE_SET_MII_SPEED_TO_100)
+#endif
+
+#ifdef CONFIG_KM_DISABLE_PCI
+#undef  CONFIG_KIRKWOOD_PCIE_INIT
+#endif
+
+
+#endif /* _CONFIG_KM_KIRKWOOD */
diff --git a/qemu/roms/u-boot/include/configs/kmp204x.h b/qemu/roms/u-boot/include/configs/kmp204x.h
new file mode 100644
index 000000000..8bb357169
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/kmp204x.h
@@ -0,0 +1,73 @@
+/*
+ * (C) Copyright 2013 Keymile AG
+ * Valentin Longchamp <valentin.longchamp@keymile.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* KMLION1 */
+#if defined(CONFIG_KMLION1)
+#define CONFIG_HOSTNAME		kmlion1
+#define CONFIG_KM_BOARD_NAME	"kmlion1"
+
+/* KMCOGE4 */
+#elif defined(CONFIG_KMCOGE4)
+#define CONFIG_HOSTNAME		kmcoge4
+#define CONFIG_KM_BOARD_NAME	"kmcoge4"
+
+#else
+#error ("Board not supported")
+#endif
+
+#define CONFIG_KMP204X
+
+#include "km/kmp204x-common.h"
+
+#if defined(CONFIG_KMLION1)
+/* App1 Local bus */
+#define CONFIG_SYS_LBAPP1_BASE		0xD0000000
+#define CONFIG_SYS_LBAPP1_BASE_PHYS	0xFD0000000ull
+
+#define CONFIG_SYS_LBAPP1_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_LBAPP1_BASE_PHYS) \
+				| BR_PS_8	/* Port Size 8 bits */ \
+				| BR_DECC_OFF	/* no error corr */ \
+				| BR_MS_GPCM	/* MSEL = GPCM */ \
+				| BR_V)		/* valid */
+
+#define CONFIG_SYS_LBAPP1_OR_PRELIM (OR_AM_256MB	/* length 256MB */ \
+				| OR_GPCM_ACS_DIV2 /* LCS 1/2 clk after */ \
+				| OR_GPCM_CSNT /* LCS 1/4 clk before */ \
+				| OR_GPCM_SCY_2 /* 2 clk wait cycles */ \
+				| OR_GPCM_TRLX /* relaxed tmgs */ \
+				| OR_GPCM_EAD) /* extra bus clk cycles */
+/* Local bus app1 Base Address */
+#define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_LBAPP1_BR_PRELIM
+/* Local bus app1 Options */
+#define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_LBAPP1_OR_PRELIM
+#endif
+
+/* App2 Local bus */
+#define CONFIG_SYS_LBAPP2_BASE		0xE0000000
+#define CONFIG_SYS_LBAPP2_BASE_PHYS	0xFE0000000ull
+
+#define CONFIG_SYS_LBAPP2_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_LBAPP2_BASE_PHYS) \
+				| BR_PS_8	/* Port Size 8 bits */ \
+				| BR_DECC_OFF	/* no error corr */ \
+				| BR_MS_GPCM	/* MSEL = GPCM */ \
+				| BR_V)		/* valid */
+
+#define CONFIG_SYS_LBAPP2_OR_PRELIM (OR_AM_256MB	/* length 256MB */ \
+				| OR_GPCM_ACS_DIV2 /* LCS 1/2 clk after */ \
+				| OR_GPCM_CSNT /* LCS 1/4 clk before */ \
+				| OR_GPCM_SCY_2 /* 2 clk wait cycles */ \
+				| OR_GPCM_TRLX /* relaxed tmgs */ \
+				| OR_GPCM_EAD) /* extra bus clk cycles */
+/* Local bus app2 Base Address */
+#define CONFIG_SYS_BR3_PRELIM  CONFIG_SYS_LBAPP2_BR_PRELIM
+/* Local bus app2 Options */
+#define CONFIG_SYS_OR3_PRELIM  CONFIG_SYS_LBAPP2_OR_PRELIM
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/koelsch.h b/qemu/roms/u-boot/include/configs/koelsch.h
new file mode 100644
index 000000000..90e2d7a03
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/koelsch.h
@@ -0,0 +1,192 @@
+/*
+ * include/configs/koelsch.h
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __KOELSCH_H
+#define __KOELSCH_H
+
+#undef DEBUG
+#define CONFIG_ARMV7
+#define CONFIG_R8A7791
+#define CONFIG_RMOBILE
+#define CONFIG_RMOBILE_BOARD_STRING "Koelsch"
+#define CONFIG_SH_GPIO_PFC
+
+#include <asm/arch/rmobile.h>
+
+#define CONFIG_CMD_EDITENV
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_DFL
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_BOOTZ
+
+#if defined(CONFIG_SYS_USE_BOOT_NORFLASH)
+#define	CONFIG_CMD_FLASH
+#define CONFIG_SYS_TEXT_BASE	0x00000000
+#else
+/* SPI flash boot is default. */
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_SYS_TEXT_BASE	0xE6304000
+#endif
+
+#define	CONFIG_CMDLINE_TAG
+#define	CONFIG_SETUP_MEMORY_TAGS
+#define	CONFIG_INITRD_TAG
+#define	CONFIG_CMDLINE_EDITING
+
+#define CONFIG_OF_LIBFDT
+#define BOARD_LATE_INIT
+
+#define CONFIG_BAUDRATE		38400
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTARGS		""
+
+#define CONFIG_VERSION_VARIABLE
+#undef	CONFIG_SHOW_BOOT_PROGRESS
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_USE_ARCH_MEMSET
+#define CONFIG_USE_ARCH_MEMCPY
+#define CONFIG_TMU_TIMER
+
+/* STACK */
+#define CONFIG_SYS_INIT_SP_ADDR		0xE633fffc
+#define STACK_AREA_SIZE				0xC000
+#define LOW_LEVEL_MERAM_STACK	\
+		(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
+
+/* MEMORY */
+#define KOELSCH_SDRAM_BASE	0x40000000
+#define KOELSCH_SDRAM_SIZE	(2048u * 1024 * 1024)
+#define KOELSCH_UBOOT_SDRAM_SIZE	(512 * 1024 * 1024)
+
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_PBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE		512
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 38400, 115200 }
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE
+#define CONFIG_CONS_SCIF0
+#define SCIF0_BASE		0xe6e60000
+#undef	CONFIG_SYS_CONSOLE_INFO_QUIET
+#undef	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#undef	CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+
+#define CONFIG_SYS_MEMTEST_START	(KOELSCH_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
+					 504 * 1024 * 1024)
+#undef	CONFIG_SYS_ALT_MEMTEST
+#undef	CONFIG_SYS_MEMTEST_SCRATCH
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE
+
+#define CONFIG_SYS_SDRAM_BASE		(KOELSCH_SDRAM_BASE)
+#define CONFIG_SYS_SDRAM_SIZE		(KOELSCH_UBOOT_SDRAM_SIZE)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x7fc0)
+#define CONFIG_NR_DRAM_BANKS		1
+
+#define CONFIG_SYS_MONITOR_BASE		0x00000000
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(1 * 1024 * 1024)
+#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
+
+/* FLASH */
+#if defined(CONFIG_SYS_USE_BOOT_NORFLASH)
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define	CONFIG_FLASH_CFI_DRIVER
+#define	CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define	CONFIG_FLASH_SHOW_PROGRESS	45
+#define CONFIG_SYS_FLASH_BASE		0x00000000
+#define	CONFIG_SYS_FLASH_SIZE		0x04000000	/* 64 MB */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ (CONFIG_SYS_FLASH_BASE) }
+#define	CONFIG_SYS_FLASH_BANKS_SIZES	{ (CONFIG_SYS_FLASH_SIZE) }
+#define CONFIG_SYS_FLASH_ERASE_TOUT	3000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	3000
+#define CONFIG_SYS_FLASH_LOCK_TOUT	3000
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	3000
+/* ENV setting */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + \
+				 CONFIG_SYS_MONITOR_LEN)
+
+#else /* CONFIG_SYS_USE_BOOT_NORFLASH */
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SPI
+#define CONFIG_SH_QSPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_BAR
+#define CONFIG_SPI_FLASH_SPANSION
+/* ENV setting */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_ADDR	0xC0000
+
+#endif /* CONFIG_SYS_USE_BOOT_NORFLASH */
+
+/* Common ENV setting */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_SECT_SIZE	(256 * 1024)
+#define CONFIG_ENV_OFFSET	(CONFIG_ENV_ADDR)
+#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_SYS_MONITOR_LEN)
+
+/* SH Ether */
+#define	CONFIG_NET_MULTI
+#define CONFIG_SH_ETHER
+#define CONFIG_SH_ETHER_USE_PORT	0
+#define CONFIG_SH_ETHER_PHY_ADDR	0x1
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
+#define CONFIG_SH_ETHER_CACHE_WRITEBACK
+#define CONFIG_SH_ETHER_CACHE_INVALIDATE
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
+
+/* Board Clock */
+#define	CONFIG_SYS_CLK_FREQ	10000000
+#define CONFIG_SH_TMU_CLK_FREQ	CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ	14745600
+#define CONFIG_SYS_TMU_CLK_DIV	4
+
+/* i2c */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SH
+#define CONFIG_SYS_I2C_SLAVE	0x7F
+#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS	3
+#define CONFIG_SYS_I2C_SH_BASE0		0xE6500000
+#define CONFIG_SYS_I2C_SH_SPEED0	400000
+#define CONFIG_SYS_I2C_SH_BASE1		0xE6510000
+#define CONFIG_SYS_I2C_SH_SPEED1	400000
+#define CONFIG_SYS_I2C_SH_BASE2		0xE60B0000
+#define CONFIG_SYS_I2C_SH_SPEED2	400000
+#define CONFIG_SH_I2C_DATA_HIGH	4
+#define CONFIG_SH_I2C_DATA_LOW	5
+#define CONFIG_SH_I2C_CLOCK	10000000
+
+#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
+
+#endif	/* __KOELSCH_H */
diff --git a/qemu/roms/u-boot/include/configs/korat.h b/qemu/roms/u-boot/include/configs/korat.h
new file mode 100644
index 000000000..5494a6007
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/korat.h
@@ -0,0 +1,550 @@
+/*
+ * (C) Copyright 2007-2009
+ * Larry Johnson, lrj@acm.org
+ *
+ * (C) Copyright 2006-2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2006
+ * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
+ * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * korat.h - configuration for Korat board
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_440EPX		1	/* Specific PPC440EPx		*/
+#define CONFIG_SYS_CLK_FREQ	33333333
+
+#ifdef CONFIG_KORAT_PERMANENT
+#define CONFIG_SYS_TEXT_BASE	0xFFFA0000
+#else
+#define	CONFIG_SYS_TEXT_BASE	0xF7F60000
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
+#define CONFIG_MISC_INIT_R	1	/* Call misc_init_r		*/
+
+/*
+ * Manufacturer's information serial EEPROM parameters
+ */
+#define MAN_DATA_EEPROM_ADDR	0x53	/* EEPROM I2C address		*/
+#define MAN_INFO_FIELD		2
+#define MAN_INFO_LENGTH		9
+#define MAN_MAC_ADDR_FIELD	3
+#define MAN_MAC_ADDR_LENGTH	12
+
+/*
+ * Base addresses -- Note these are effective addresses where the actual
+ * resources get mapped (not physical addresses).
+ */
+#define CONFIG_SYS_MONITOR_LEN		(384 * 1024) /* Reserve 384 kiB for Monitor  */
+#define CONFIG_SYS_MALLOC_LEN		(256 * 1024) /* Reserve 256 kiB for malloc() */
+
+#define CONFIG_SYS_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
+#define CONFIG_SYS_FLASH0_SIZE		0x01000000
+#define CONFIG_SYS_FLASH0_ADDR		(-CONFIG_SYS_FLASH0_SIZE)
+#define CONFIG_SYS_FLASH1_TOP		0xF8000000
+#define CONFIG_SYS_FLASH1_MAX_SIZE	0x08000000
+#define CONFIG_SYS_FLASH1_ADDR		(CONFIG_SYS_FLASH1_TOP - CONFIG_SYS_FLASH1_MAX_SIZE)
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_FLASH1_ADDR	/* start of FLASH	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_OCM_BASE		0xe0010000	/* ocm			*/
+#define CONFIG_SYS_OCM_DATA_ADDR	CONFIG_SYS_OCM_BASE
+#define CONFIG_SYS_PCI_BASE		0xe0000000	/* Internal PCI regs	*/
+#define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped pci memory	*/
+#define CONFIG_SYS_PCI_MEMBASE2		(CONFIG_SYS_PCI_MEMBASE + 0x20000000)
+
+#define CONFIG_SYS_USB2D0_BASE		0xe0000100
+#define CONFIG_SYS_USB_DEVICE		0xe0000000
+#define CONFIG_SYS_USB_HOST		0xe0000400
+#define CONFIG_SYS_CPLD_BASE		0xc0000000
+
+/*
+ * Initial RAM & stack pointer
+ */
+/* 440EPx has 16KB of internal SRAM, so no need for D-Cache		*/
+#undef CONFIG_SYS_INIT_RAM_DCACHE
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_BASE	/* OCM			*/
+#define CONFIG_SYS_INIT_RAM_SIZE	(4 << 10)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+#define CONFIG_SYS_EXT_SERIAL_CLOCK	11059200	/* ext. 11.059MHz clk	*/
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_SYS_BAUDRATE_TABLE						\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1	/* use FLASH for environ vars	*/
+
+/*
+ * FLASH related
+ */
+#define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible	      */
+#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	      */
+#define CONFIG_FLASH_CFI_LEGACY		/* Allow hard-coded config for FLASH0 */
+
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH1_ADDR, CONFIG_SYS_FLASH0_ADDR }
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks	      */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* max number of sectors on one chip  */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)    */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)    */
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)   */
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* use hardware flash protection      */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO	      /* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash      */
+
+#define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector	      */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH1_TOP - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector   */
+
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+
+/*
+ * DDR SDRAM
+ */
+#define CONFIG_DDR_DATA_EYE		/* use DDR2 optimization	*/
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for setup	*/
+#define CONFIG_ZERO_SDRAM		/* Zero SDRAM after setup	*/
+#define CONFIG_DDR_ECC			/* Use ECC when available	*/
+#define SPD_EEPROM_ADDRESS	{0x50}
+#define CONFIG_PROG_SDRAM_TLB
+#define CONFIG_SYS_MEM_TOP_HIDE	(4 << 10) /* don't use last 4 KiB as	*/
+					/* per 440EPx Errata CHIP_11	*/
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
+
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR	(0xa8>>1)
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+/* I2C RTC */
+#define CONFIG_RTC_M41T60	1
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68
+
+/* I2C SYSMON (LM73)							*/
+#define CONFIG_DTT_LM73		1	/* National Semi's LM73		*/
+#define CONFIG_DTT_SENSORS	{2}	/* Sensor addresses		*/
+#define CONFIG_SYS_DTT_MAX_TEMP	70
+#define CONFIG_SYS_DTT_MIN_TEMP	-30
+
+#define CONFIG_PREBOOT	"echo;"						\
+	"echo Type \\\"run flash_cf\\\" to mount from CompactFlash(R);" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+/* Setup some board specific values for the default environment variables */
+#define CONFIG_HOSTNAME		korat
+
+/* Note: kernel_addr and ramdisk_addr assume that FLASH1 is 64 MiB. */
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"u_boot=korat/u-boot.bin\0"					\
+	"load=tftp 200000 ${u_boot}\0"					\
+	"update=protect off F7F60000 F7FBFFFF;erase F7F60000 F7FBFFFF;"	\
+		"cp.b ${fileaddr} F7F60000 ${filesize};protect on "	\
+		"F7F60000 F7FBFFFF\0"					\
+	"upd=run load update\0"						\
+	"bootfile=korat/uImage\0"					\
+	"dtb=korat/korat.dtb\0"						\
+	"kernel_addr=F4000000\0"					\
+	"ramdisk_addr=F4400000\0"					\
+	"dtb_addr=F41E0000\0"						\
+	"udl=tftp 200000 ${bootfile}; erase F4000000 F41DFFFF; "	\
+		"cp.b ${fileaddr} F4000000 ${filesize}\0"		\
+	"udd=tftp 200000 ${dtb}; erase F41E0000 F41FFFFF; "		\
+		"cp.b ${fileaddr} F41E0000 ${filesize}\0"		\
+	"ll=setenv kernel_addr 200000; setenv dtb_addr 1000000; "	\
+		"tftp ${kernel_addr} ${uImage}; tftp ${dtb_addr} "	\
+		"${dtb}\0"						\
+	"rd_size=73728\0"						\
+	"ramargs=setenv bootargs root=/dev/ram rw "			\
+		"ramdisk_size=${rd_size}\0"				\
+	"usbdev=sda1\0"							\
+	"usbargs=setenv bootargs root=/dev/${usbdev} ro rootdelay=10\0"	\
+	"rootpath=/opt/eldk/ppc_4xxFP\0"				\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"pciclk=33\0"							\
+	"addide=setenv bootargs ${bootargs} ide=reverse "		\
+		"idebus=${pciclk}\0"					\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+	"flash_cf=run usbargs addide addip addtty; "			\
+		"bootm ${kernel_addr} - ${dtb_addr}\0"			\
+	"flash_nfs=run nfsargs addide addip addtty; "			\
+		"bootm ${kernel_addr} - ${dtb_addr}\0"			\
+	"flash_self=run ramargs addip addtty; "				\
+		"bootm ${kernel_addr} ${ramdisk_addr} ${dtb_addr}\0"	\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run flash_cf"
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_PPC4xx_EMAC
+#define CONFIG_IBM_EMAC4_V4	1
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		2	/* PHY address, See schematics	*/
+#define CONFIG_PHY_DYNAMIC_ANEG	1
+
+#undef CONFIG_PHY_RESET			/* Don't do software PHY reset	*/
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+
+#define CONFIG_HAS_ETH0
+#define CONFIG_SYS_RX_ETH_BUFFER	32	/* Number of ethernet rx	*/
+					/*   buffers & descriptors	*/
+#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
+#define CONFIG_PHY1_ADDR	3
+
+/* USB */
+#define CONFIG_USB_OHCI
+#define CONFIG_USB_STORAGE
+
+/* Comment this out to enable USB 1.1 device */
+#define USB_2_0_DEVICE
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_SUBNETMASK
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_USB
+
+/* POST support */
+#define CONFIG_POST		(CONFIG_SYS_POST_CACHE	| \
+				 CONFIG_SYS_POST_CPU	| \
+				 CONFIG_SYS_POST_ECC	| \
+				 CONFIG_SYS_POST_ETHER	| \
+				 CONFIG_SYS_POST_FPU	| \
+				 CONFIG_SYS_POST_I2C	| \
+				 CONFIG_SYS_POST_MEMORY	| \
+				 CONFIG_SYS_POST_RTC	| \
+				 CONFIG_SYS_POST_SPR	| \
+				 CONFIG_SYS_POST_UART)
+
+#define CONFIG_LOGBUFFER
+#define CONFIG_SYS_POST_CACHE_ADDR	0xC8000000	/* free virtual address     */
+
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	/* Otherwise it catches logbuffer as output */
+
+#define CONFIG_SUPPORT_VFAT
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	        1024	/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	        256	/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+					/* Print Buffer Size		*/
+#define CONFIG_SYS_MAXARGS	        16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	        CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000 /* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000  /* default load address	*/
+#define CONFIG_SYS_EXTBDINFO		1  /* To use extended board_into (bd_t)	*/
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_LOOPW		1	/* enable loopw command		*/
+#define CONFIG_MX_CYCLIC	1	/* enable mdc/mwc commands	*/
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable	*/
+
+/*
+ * Korat-specific options
+ */
+#define CONFIG_SYS_KORAT_MAN_RESET_MS	10000	/* timeout for manufacturer reset */
+
+/*
+ * PCI stuff
+ */
+/* General PCI */
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+#define CONFIG_SYS_PCI_CACHE_LINE_SIZE	0	/* to avoid problems with PNP	*/
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
+#define CONFIG_SYS_PCI_TARGBASE	0x80000000	/* PCIaddr mapped to	*/
+						/*   CONFIG_SYS_PCI_MEMBASE	*/
+/* Board-specific PCI */
+#define CONFIG_SYS_PCI_TARGET_INIT
+#define CONFIG_SYS_PCI_MASTER_INIT
+#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC				*/
+#define CONFIG_SYS_PCI_SUBSYS_ID       0xcafe	/* Whatever			*/
+
+/*
+ * For booting Linux, the board info and command line data have to be in the
+ * first 8 MB of memory, since this is the maximum mapped by the Linux kernel
+ * during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+
+/*
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (NOR-FLASH) initialization				*/
+#if CONFIG_SYS_FLASH0_SIZE == 0x01000000
+#define CONFIG_SYS_EBC_PB0AP		0x04017300
+#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_FLASH0_ADDR | 0x0009A000)
+#elif CONFIG_SYS_FLASH0_SIZE == 0x04000000
+#define CONFIG_SYS_EBC_PB0AP		0x04017300
+#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_FLASH0_ADDR | 0x000DA000)
+#else
+#error Unable to configure chip select for current CONFIG_SYS_FLASH0_SIZE
+#endif
+
+/* Memory Bank 1 (NOR-FLASH) initialization				*/
+#if CONFIG_SYS_FLASH1_MAX_SIZE == 0x08000000
+#define CONFIG_SYS_EBC_PB1AP		0x04017300
+#define CONFIG_SYS_EBC_PB1CR		(CONFIG_SYS_FLASH1_ADDR | 0x000FA000)
+#else
+#error Unable to configure chip select for current CONFIG_SYS_FLASH1_MAX_SIZE
+#endif
+
+/* Memory Bank 2 (CPLD) initialization					*/
+#define CONFIG_SYS_EBC_PB2AP		0x04017300
+#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_CPLD_BASE | 0x00038000)
+
+/*
+ * GPIO Setup
+ *
+ * Korat GPIO usage:
+ *
+ *                   Init.
+ * Pin    Source I/O value Function
+ * ------ ------ --- ----- ---------------------------------
+ * GPIO00  Alt1  I/O   x   PerAddr07
+ * GPIO01  Alt1  I/O   x   PerAddr06
+ * GPIO02  Alt1  I/O   x   PerAddr05
+ * GPIO03  GPIO   x    x   GPIO03 to expansion bus connector
+ * GPIO04  GPIO   x    x   GPIO04 to expansion bus connector
+ * GPIO05  GPIO   x    x   GPIO05 to expansion bus connector
+ * GPIO06  Alt1   O    x   PerCS1 (2nd NOR flash)
+ * GPIO07  Alt1   O    x   PerCS2 (CPLD)
+ * GPIO08  Alt1   O    x   PerCS3 to expansion bus connector
+ * GPIO09  Alt1   O    x   PerCS4 to expansion bus connector
+ * GPIO10  Alt1   O    x   PerCS5 to expansion bus connector
+ * GPIO11  Alt1   I    x   PerErr
+ * GPIO12  GPIO   O    0   ATMega !Reset
+ * GPIO13  GPIO   x    x   Test Point 2 (TP2)
+ * GPIO14  GPIO   O    1   Write protect EEPROM #1 (0xA8)
+ * GPIO15  GPIO   O    0   CPU Run LED !On
+ * GPIO16  Alt1   O    x   GMC1TxD0
+ * GPIO17  Alt1   O    x   GMC1TxD1
+ * GPIO18  Alt1   O    x   GMC1TxD2
+ * GPIO19  Alt1   O    x   GMC1TxD3
+ * GPIO20  Alt1   I    x   RejectPkt0
+ * GPIO21  Alt1   I    x   RejectPkt1
+ * GPIO22  GPIO   I    x   PGOOD_DDR
+ * GPIO23  Alt1   O    x   SCPD0
+ * GPIO24  Alt1   O    x   GMC0TxD2
+ * GPIO25  Alt1   O    x   GMC0TxD3
+ * GPIO26  GPIO? I/O   x   IIC0SDA (selected in SDR0_PFC4)
+ * GPIO27  GPIO   O    0   PHY #0 1000BASE-X select
+ * GPIO28  GPIO   O    0   PHY #1 1000BASE-X select
+ * GPIO29  GPIO   I    x   Test jumper !Present
+ * GPIO30  GPIO   I    x   SFP module #0 !Present
+ * GPIO31  GPIO   I    x   SFP module #1 !Present
+ *
+ * GPIO32  GPIO   O    1   SFP module #0 Tx !Enable
+ * GPIO33  GPIO   O    1   SFP module #1 Tx !Enable
+ * GPIO34  Alt2   I    x   !UART1_CTS
+ * GPIO35  Alt2   O    x   !UART1_RTS
+ * GPIO36  Alt1   I    x   !UART0_CTS
+ * GPIO37  Alt1   O    x   !UART0_RTS
+ * GPIO38  Alt2   O    x   UART1_Tx
+ * GPIO39  Alt2   I    x   UART1_Rx
+ * GPIO40  Alt1   I    x   IRQ0 (Ethernet 0)
+ * GPIO41  Alt1   I    x   IRQ1 (Ethernet 1)
+ * GPIO42  Alt1   I    x   IRQ2 (PCI interrupt)
+ * GPIO43  Alt1   I    x   IRQ3 (System Alert from CPLD)
+ * GPIO44  xxxx   x    x   (grounded through pulldown)
+ * GPIO45  GPIO   O    0   PHY #0 Enable
+ * GPIO46  GPIO   O    0   PHY #1 Enable
+ * GPIO47  GPIO   I    x   Reset switch !Pressed
+ * GPIO48  GPIO   I    x   Shutdown switch !Pressed
+ * GPIO49  xxxx   x    x   (reserved for trace port)
+ *   .      .     .    .               .
+ *   .      .     .    .               .
+ *   .      .     .    .               .
+ * GPIO63  xxxx   x    x   (reserved for trace port)
+ */
+
+#define CONFIG_SYS_GPIO_ATMEGA_RESET_	12
+#define CONFIG_SYS_GPIO_ATMEGA_SS_	13
+#define CONFIG_SYS_GPIO_PHY0_FIBER_SEL	27
+#define CONFIG_SYS_GPIO_PHY1_FIBER_SEL	28
+#define CONFIG_SYS_GPIO_SFP0_PRESENT_	30
+#define CONFIG_SYS_GPIO_SFP1_PRESENT_	31
+#define CONFIG_SYS_GPIO_SFP0_TX_EN_	32
+#define CONFIG_SYS_GPIO_SFP1_TX_EN_	33
+#define CONFIG_SYS_GPIO_PHY0_EN	45
+#define CONFIG_SYS_GPIO_PHY1_EN	46
+#define CONFIG_SYS_GPIO_RESET_PRESSED_	47
+
+/*
+ * PPC440 GPIO Configuration
+ */
+#define CONFIG_SYS_4xx_GPIO_TABLE { /*	  Out		  GPIO	Alternate1	Alternate2	Alternate3 */ \
+{											\
+/* GPIO Core 0 */									\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0	EBC_ADDR(7)	DMA_REQ(2)	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1	EBC_ADDR(6)	DMA_ACK(2)	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2	EBC_ADDR(5)	DMA_EOT/TC(2)	*/	\
+{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO3	EBC_ADDR(4)	DMA_REQ(3)	*/	\
+{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO4	EBC_ADDR(3)	DMA_ACK(3)	*/	\
+{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO5	EBC_ADDR(2)	DMA_EOT/TC(3)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6	EBC_CS_N(1)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7	EBC_CS_N(2)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8	EBC_CS_N(3)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9	EBC_CS_N(4)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5)			*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12				*/	\
+{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO13				*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14				*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO15				*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO16 GMCTxD(4)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO17 GMCTxD(5)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO18 GMCTxD(6)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO19 GMCTxD(7)			*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0			*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1			*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO22				*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0				*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO24 GMCTxD(2)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO25 GMCTxD(3)			*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26				*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ	USB2D_RXERROR	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28		USB2D_TXVALID	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA	USB2D_PAD_SUSPNDM */	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK	USB2D_XCVRSELECT*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ	USB2D_TERMSELECT*/	\
+},											\
+{											\
+/* GPIO Core 1 */									\
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 USB2D_OPMODE0	EBC_DATA(2)	*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 USB2D_OPMODE1	EBC_DATA(3)	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N	UART1_DSR_CTS_N	UART2_SOUT*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0)	UART3_SIN*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO37 UART0_RTS_N	EBC_DATA(1)	UART3_SOUT*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N	UART1_SOUT	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N	UART1_SIN	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0)			*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1)			*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2)			*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3)			*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4)	DMA_ACK(1)	*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6)	DMA_EOT/TC(1)	*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7)	DMA_REQ(0)	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8)	DMA_ACK(0)	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9)	DMA_EOT/TC(0)	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit	*/	\
+}											\
+}
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400 /* speed to run kgdb serial port	*/
+#endif
+
+/* Pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/kvme080.h b/qemu/roms/u-boot/include/configs/kvme080.h
new file mode 100644
index 000000000..c352a1c80
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/kvme080.h
@@ -0,0 +1,251 @@
+/*
+ * (C) Copyright 2005
+ * Sangmoon Kim, dogoil@etinsys.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MPC8245		1
+#define CONFIG_KVME080		1
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
+
+#define CONFIG_CONS_INDEX	1
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_BOOTDELAY	5
+
+#define CONFIG_IPADDR		192.168.0.2
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_SERVERIP		192.168.0.1
+
+#define CONFIG_BOOTARGS \
+	"console=ttyS0,115200 " \
+	"root=/dev/nfs rw nfsroot=192.168.0.1:/opt/eldk/ppc_82xx " \
+	"ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:" \
+	"kvme080:eth0:none " \
+	"mtdparts=phys_mapped_flash:12m(root),-(kernel)"
+
+#define CONFIG_BOOTCOMMAND \
+	"tftp 800000 kvme080/uImage; " \
+	"bootm 800000"
+
+#define CONFIG_LOADADDR		800000
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_LOADS_ECHO	1
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE
+
+#undef	CONFIG_WATCHDOG
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_RTC_DS164x
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
+
+
+#define CONFIG_NETCONSOLE
+
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START	0x00400000
+#define CONFIG_SYS_MEMTEST_END		0x07C00000
+
+#define CONFIG_SYS_LOAD_ADDR		0x00100000
+
+#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x7C000000
+#define CONFIG_SYS_EUMB_ADDR		0xFC000000
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xFF000000
+#define CONFIG_SYS_NS16550_COM1	0xFF080000
+#define CONFIG_SYS_NS16550_COM2	0xFF080010
+#define CONFIG_SYS_NS16550_COM3	0xFF080020
+#define CONFIG_SYS_NS16550_COM4	0xFF080030
+#define CONFIG_SYS_RESET_ADDRESS	0xFFF00100
+
+#define CONFIG_SYS_MAX_RAM_SIZE	0x20000000
+#define CONFIG_SYS_FLASH_SIZE		(16 * 1024 * 1024)
+#define CONFIG_SYS_NVRAM_SIZE		0x7FFF8
+
+#define CONFIG_VERY_BIG_RAM
+
+#define CONFIG_SYS_MONITOR_LEN		0x00040000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MALLOC_LEN		(512 << 10)
+
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_PROTECT_CLEAR
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	256
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500
+
+#define CONFIG_SYS_JFFS2_FIRST_BANK	0
+#define CONFIG_SYS_JFFS2_NUM_BANKS	1
+
+#define CONFIG_ENV_IS_IN_NVRAM	1
+#define CONFIG_ENV_OVERWRITE	1
+#define CONFIG_SYS_NVRAM_ACCESS_ROUTINE
+#define CONFIG_ENV_ADDR		CONFIG_SYS_NVRAM_BASE_ADDR
+#define CONFIG_ENV_SIZE		0x400
+#define CONFIG_ENV_OFFSET		0
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		14745600
+
+#define CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_PCI_PNP
+
+#define CONFIG_EEPRO100
+#define CONFIG_EEPRO100_SROM_WRITE
+
+#define CONFIG_SYS_RX_ETH_BUFFER	8
+
+#define CONFIG_HARD_I2C		1
+#define CONFIG_SYS_I2C_SPEED		400000
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
+
+#define CONFIG_SYS_CLK_FREQ	33333333
+
+#define CONFIG_SYS_CACHELINE_SIZE	32
+#if defined(CONFIG_CMD_KGDB)
+#  define CONFIG_SYS_CACHELINE_SHIFT	5
+#endif
+
+#define CONFIG_SYS_DLL_EXTEND		0x00
+#define CONFIG_SYS_PCI_HOLD_DEL	0x20
+
+#define CONFIG_SYS_ROMNAL		15
+#define CONFIG_SYS_ROMFAL		31
+
+#define CONFIG_SYS_REFINT		430
+
+#define CONFIG_SYS_DBUS_SIZE2		1
+
+#define CONFIG_SYS_BSTOPRE		121
+#define CONFIG_SYS_REFREC		8
+#define CONFIG_SYS_RDLAT		4
+#define CONFIG_SYS_PRETOACT		3
+#define CONFIG_SYS_ACTTOPRE		5
+#define CONFIG_SYS_ACTORW		3
+#define CONFIG_SYS_SDMODE_CAS_LAT	3
+#define CONFIG_SYS_SDMODE_WRAP		0
+
+#define CONFIG_SYS_REGISTERD_TYPE_BUFFER	1
+#define CONFIG_SYS_EXTROM			1
+#define CONFIG_SYS_REGDIMM			0
+
+#define CONFIG_SYS_BANK0_START		0x00000000
+#define CONFIG_SYS_BANK0_END		(0x4000000 - 1)
+#define CONFIG_SYS_BANK0_ENABLE	1
+#define CONFIG_SYS_BANK1_START		0x04000000
+#define CONFIG_SYS_BANK1_END		(0x8000000 - 1)
+#define CONFIG_SYS_BANK1_ENABLE	1
+#define CONFIG_SYS_BANK2_START		0x3ff00000
+#define CONFIG_SYS_BANK2_END		0x3fffffff
+#define CONFIG_SYS_BANK2_ENABLE	0
+#define CONFIG_SYS_BANK3_START		0x3ff00000
+#define CONFIG_SYS_BANK3_END		0x3fffffff
+#define CONFIG_SYS_BANK3_ENABLE	0
+#define CONFIG_SYS_BANK4_START		0x00000000
+#define CONFIG_SYS_BANK4_END		0x00000000
+#define CONFIG_SYS_BANK4_ENABLE	0
+#define CONFIG_SYS_BANK5_START		0x00000000
+#define CONFIG_SYS_BANK5_END		0x00000000
+#define CONFIG_SYS_BANK5_ENABLE	0
+#define CONFIG_SYS_BANK6_START		0x00000000
+#define CONFIG_SYS_BANK6_END		0x00000000
+#define CONFIG_SYS_BANK6_ENABLE	0
+#define CONFIG_SYS_BANK7_START		0x00000000
+#define CONFIG_SYS_BANK7_END		0x00000000
+#define CONFIG_SYS_BANK7_ENABLE	0
+
+#define CONFIG_SYS_BANK_ENABLE		0x03
+
+#define CONFIG_SYS_ODCR		0x75
+#define CONFIG_SYS_PGMAX		0x32
+
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT2L	(0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U	(0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT3L	(0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/kwb.h b/qemu/roms/u-boot/include/configs/kwb.h
new file mode 100644
index 000000000..0f631c0f6
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/kwb.h
@@ -0,0 +1,128 @@
+/*
+ * kwb.h
+ *
+ * specific parts for B&R KWB Motherboard
+ *
+ * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at> -
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ * SPDX-License-Identifier:        GPL-2.0+
+ */
+
+#ifndef __CONFIG_KWB_H__
+#define __CONFIG_KWB_H__
+
+#include <configs/bur_am335x_common.h>
+/* ------------------------------------------------------------------------- */
+/* Clock Defines */
+#define V_OSCK				26000000  /* Clock output from T2 */
+#define V_SCLK				(V_OSCK)
+
+#define CONFIG_POWER_TPS65217
+
+#define CONFIG_MACH_TYPE		3589
+/* I2C IP block */
+#define CONFIG_SYS_OMAP24_I2C_SPEED_PSOC	20000
+
+/* GPIO */
+#define CONFIG_SPL_GPIO_SUPPORT
+
+/* MMC/SD IP block */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_CMD_MMC
+#define CONFIG_SUPPORT_EMMC_BOOT
+/* RAW SD card / eMMC locations. */
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /*addr. 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS		0x200 /* 256 KB */
+#define CONFIG_SPL_MMC_SUPPORT
+
+#undef CONFIG_SPL_OS_BOOT
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_SYS_SPL_ARGS_ADDR		0x80F80000
+
+/* RAW SD card / eMMC */
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0x900	/* address 0x120000 */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0x80	/* address 0x10000 */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	0x80	/* 64KiB */
+
+#endif /* CONFIG_SPL_OS_BOOT */
+
+/* Always 128 KiB env size */
+#define CONFIG_ENV_SIZE			(128 << 10)
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"autoload=0\0" \
+	"loadaddr=0x80100000\0" \
+	"bootfile=arimg\0" \
+	"usbboot=echo Booting from USB-Stick ...; " \
+		"usb start; " \
+		"fatload usb 0 ${loadaddr} ${bootfile}; " \
+		"usb stop; " \
+		"go ${loadaddr};\0" \
+	"netboot=echo Booting from network ...; " \
+		"setenv autoload 0; " \
+		"dhcp; " \
+		"tftp ${loadaddr} arimg; " \
+		"go ${loadaddr}\0" \
+	"usbupdate=echo Updating UBOOT from USB-Stick ...; " \
+		"usb start; " \
+		"fatload usb 0 0x80000000 updateubootusb.img; " \
+		"source;\0" \
+	"netupdate=echo Updating UBOOT from Network (TFTP) ...; " \
+		"setenv autoload 0; " \
+		"dhcp;" \
+		"tftp 0x80000000 updateUBOOT.img;" \
+		"source;\0"
+#endif /* !CONFIG_SPL_BUILD*/
+
+#define CONFIG_BOOTCOMMAND \
+	"run usbupdate;"
+#define CONFIG_BOOTDELAY		1 /* TODO: für release auf 0 setzen */
+
+/* undefine command which we not need here */
+#undef	CONFIG_BOOTM_LINUX
+#undef	CONFIG_BOOTM_NETBSD
+#undef	CONFIG_BOOTM_PLAN9
+#undef	CONFIG_BOOTM_RTEMS
+#undef	CONFIG_GZIP
+#undef	CONFIG_ZLIB
+#undef CONFIG_CMD_CRC32
+
+/* USB configuration */
+#define CONFIG_USB_MUSB_DSPS
+#define CONFIG_ARCH_MISC_INIT
+#define CONFIG_MUSB_PIO_ONLY
+#define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT
+/* attention! not only for gadget, enables also highspeed in hostmode */
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_MUSB_HOST
+#define CONFIG_AM335X_USB0
+#define CONFIG_AM335X_USB0_MODE	MUSB_HOST
+
+#ifdef CONFIG_MUSB_HOST
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#endif /* CONFIG_MUSB_HOST */
+
+#undef CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV		1
+#define CONFIG_SYS_MMC_ENV_PART		2
+#define CONFIG_ENV_OFFSET		0x40000	/* TODO: Adresse definieren */
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+/*
+ * Common filesystems support.  When we have removable storage we
+ * enabled a number of useful commands and support.
+ */
+#if defined(CONFIG_MMC) || defined(CONFIG_USB_STORAGE)
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_FAT
+#define CONFIG_FAT_WRITE
+#define CONFIG_CMD_FS_GENERIC
+#endif /* CONFIG_MMC, ... */
+
+#endif	/* ! __CONFIG_TSERIES_H__ */
diff --git a/qemu/roms/u-boot/include/configs/kzm9g.h b/qemu/roms/u-boot/include/configs/kzm9g.h
new file mode 100644
index 000000000..5a13ad113
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/kzm9g.h
@@ -0,0 +1,159 @@
+/*
+ * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __KZM9G_H
+#define __KZM9G_H
+
+#undef DEBUG
+
+#define CONFIG_RMOBILE
+#define CONFIG_SH73A0
+#define CONFIG_KZM_A9_GT
+#define CONFIG_RMOBILE_BOARD_STRING	"KMC KZM-A9-GT"
+#define CONFIG_MACH_TYPE MACH_TYPE_KZM9G
+#define CONFIG_SYS_GENERIC_BOARD
+
+#include <asm/arch/rmobile.h>
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_OF_LIBFDT
+
+#include <config_cmd_default.h>
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_BOOTZ
+
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_BOOTARGS		"root=/dev/null console=ttySC4,115200"
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_VERSION_VARIABLE
+#undef  CONFIG_SHOW_BOOT_PROGRESS
+
+/* MEMORY */
+#define KZM_SDRAM_BASE	(0x40000000)
+#define PHYS_SDRAM		KZM_SDRAM_BASE
+#define PHYS_SDRAM_SIZE		(512 * 1024 * 1024)
+#define CONFIG_NR_DRAM_BANKS	(1)
+
+/* NOR Flash */
+#define KZM_FLASH_BASE	(0x00000000)
+#define CONFIG_SYS_FLASH_BASE		(KZM_FLASH_BASE)
+#define CONFIG_SYS_FLASH_CFI_WIDTH	(FLASH_CFI_16BIT)
+#define CONFIG_SYS_MAX_FLASH_BANKS	(1)
+#define CONFIG_SYS_MAX_FLASH_SECT	(512)
+
+/* prompt */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT		"KZM-A9-GT# "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_PBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE		512
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE
+#define CONFIG_CONS_SCIF4
+#undef  CONFIG_SYS_CONSOLE_INFO_QUIET
+#undef  CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#undef  CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+
+#define CONFIG_SYS_MEMTEST_START	(KZM_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END \
+	(CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
+#undef  CONFIG_SYS_ALT_MEMTEST
+#undef  CONFIG_SYS_MEMTEST_SCRATCH
+#undef  CONFIG_SYS_LOADS_BAUD_CHANGE
+
+#define CONFIG_SYS_INIT_RAM_ADDR	(0xE5600000) /* on MERAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	(0x10000)
+#define LOW_LEVEL_MERAM_STACK		(CONFIG_SYS_INIT_RAM_ADDR - 4)
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SDRAM_OFFSET_FOR_RT	(16 * 1024 * 1024)
+#define CONFIG_SYS_SDRAM_BASE	(KZM_SDRAM_BASE + CONFIG_SDRAM_OFFSET_FOR_RT)
+#define CONFIG_SYS_SDRAM_SIZE	(PHYS_SDRAM_SIZE - CONFIG_SDRAM_OFFSET_FOR_RT)
+#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
+
+#define CONFIG_SYS_MONITOR_BASE	(KZM_FLASH_BASE)
+#define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + 128 * 1024)
+#define CONFIG_SYS_BOOTMAPSZ	(8 * 1024 * 1024)
+
+#define CONFIG_SYS_TEXT_BASE		0x00000000
+#define CONFIG_STANDALONE_LOAD_ADDR	0x41000000
+
+/* FLASH */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#undef  CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define FLASH_SECTOR_SIZE	(256 * 1024)	/* 256 KB sectors */
+#define CONFIG_ENV_SIZE		FLASH_SECTOR_SIZE
+#define CONFIG_ENV_OFFSET	FLASH_SECTOR_SIZE
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+
+/* Timeout for Flash erase operations (in ms) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(3 * 1000)
+/* Timeout for Flash write operations (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(3 * 1000)
+/* Timeout for Flash set sector lock bit operations (in ms) */
+#define CONFIG_SYS_FLASH_LOCK_TOUT		(3 * 1000)
+/* Timeout for Flash clear lock bit operations (in ms) */
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	(3 * 1000)
+
+#undef  CONFIG_SYS_FLASH_PROTECTION
+#undef  CONFIG_SYS_DIRECT_FLASH_TFTP
+#define CONFIG_ENV_IS_IN_FLASH
+
+/* GPIO / PFC */
+#define CONFIG_SH_GPIO_PFC
+
+/* Clock */
+#define CONFIG_GLOBAL_TIMER
+#define CONFIG_SYS_CLK_FREQ	(48000000)
+#define CONFIG_SYS_CPU_CLK	(1196000000)
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define TMU_CLK_DIVIDER		(4)	/* 4 (default), 16, 64, 256 or 1024 */
+
+/* Ether */
+#define CONFIG_NET_MULTI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_BASE	(0x10000000)
+#define CONFIG_SMC911X_32_BIT
+#define CONFIG_NFS_TIMEOUT 10000UL
+
+/* I2C */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SH
+#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 5
+#define CONFIG_SYS_I2C_SH_BASE0	0xE6820000
+#define CONFIG_SYS_I2C_SH_SPEED0	100000
+#define CONFIG_SYS_I2C_SH_BASE1	0xE6822000
+#define CONFIG_SYS_I2C_SH_SPEED1	100000
+#define CONFIG_SYS_I2C_SH_BASE2	0xE6824000
+#define CONFIG_SYS_I2C_SH_SPEED2	100000
+#define CONFIG_SYS_I2C_SH_BASE3	0xE6826000
+#define CONFIG_SYS_I2C_SH_SPEED3	100000
+#define CONFIG_SYS_I2C_SH_BASE4	0xE6828000
+#define CONFIG_SYS_I2C_SH_SPEED4	100000
+#define CONFIG_SH_I2C_8BIT
+#define CONFIG_SH_I2C_DATA_HIGH 4
+#define CONFIG_SH_I2C_DATA_LOW  5
+#define CONFIG_SH_I2C_CLOCK     104000000 /* 104 MHz */
+
+#endif /* __KZM9G_H */
diff --git a/qemu/roms/u-boot/include/configs/lacie_kw.h b/qemu/roms/u-boot/include/configs/lacie_kw.h
new file mode 100644
index 000000000..2d2e23a2a
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/lacie_kw.h
@@ -0,0 +1,216 @@
+/*
+ * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CONFIG_LACIE_KW_H
+#define _CONFIG_LACIE_KW_H
+
+/*
+ * Machine number definition
+ */
+#if defined(CONFIG_INETSPACE_V2)
+#define CONFIG_MACH_TYPE		MACH_TYPE_INETSPACE_V2
+#define CONFIG_IDENT_STRING		" IS v2"
+#elif defined(CONFIG_NETSPACE_V2)
+#define CONFIG_MACH_TYPE		MACH_TYPE_NETSPACE_V2
+#define CONFIG_IDENT_STRING		" NS v2"
+#elif defined(CONFIG_NETSPACE_LITE_V2)
+#define MACH_TYPE_NETSPACE_LITE_V2	2983 /* missing in mach-types.h */
+#define CONFIG_MACH_TYPE		MACH_TYPE_NETSPACE_LITE_V2
+#define CONFIG_IDENT_STRING		" NS v2 Lite"
+#elif defined(CONFIG_NETSPACE_MINI_V2)
+#define MACH_TYPE_NETSPACE_MINI_V2	2831 /* missing in mach-types.h */
+#define CONFIG_MACH_TYPE		MACH_TYPE_NETSPACE_MINI_V2
+#define CONFIG_IDENT_STRING		" NS v2 Mini"
+#elif defined(CONFIG_NETSPACE_MAX_V2)
+#define CONFIG_MACH_TYPE		MACH_TYPE_NETSPACE_MAX_V2
+#define CONFIG_IDENT_STRING		" NS Max v2"
+#elif defined(CONFIG_D2NET_V2)
+#define CONFIG_MACH_TYPE		MACH_TYPE_D2NET_V2
+#define CONFIG_IDENT_STRING		" D2 v2"
+#elif defined(CONFIG_NET2BIG_V2)
+#define CONFIG_MACH_TYPE		MACH_TYPE_NET2BIG_V2
+#define CONFIG_IDENT_STRING		" 2Big v2"
+#else
+#error "Unknown board"
+#endif
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_FEROCEON_88FR131		/* CPU Core subversion */
+#define CONFIG_KIRKWOOD			/* SoC Family Name */
+/* SoC name */
+#if defined(CONFIG_NETSPACE_LITE_V2) || defined(CONFIG_NETSPACE_MINI_V2)
+#define CONFIG_KW88F6192
+#else
+#define CONFIG_KW88F6281
+#endif
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#ifndef CONFIG_NETSPACE_MINI_V2 /* No USB ports on Network Space v2 Mini */
+#define CONFIG_CMD_USB
+#endif
+
+/*
+ * Core clock definition
+ */
+#define CONFIG_SYS_TCLK			166000000 /* 166MHz */
+
+/*
+ * SDRAM configuration
+ */
+#define CONFIG_NR_DRAM_BANKS		1
+
+/*
+ * Different SDRAM configuration and size for some of the boards derived
+ * from the Network Space v2
+ */
+#if defined(CONFIG_INETSPACE_V2)
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-is2.cfg
+#elif defined(CONFIG_NETSPACE_LITE_V2) || defined(CONFIG_NETSPACE_MINI_V2)
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-ns2l.cfg
+#endif
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/* Remove or override few declarations from mv-common.h */
+#undef CONFIG_RBTREE
+#undef CONFIG_ENV_SPI_MAX_HZ
+#undef CONFIG_SYS_IDE_MAXBUS
+#undef CONFIG_SYS_IDE_MAXDEVICE
+#undef CONFIG_SYS_PROMPT
+#define CONFIG_ENV_SPI_MAX_HZ           20000000 /* 20Mhz */
+#define CONFIG_SYS_IDE_MAXBUS           1
+#define CONFIG_SYS_IDE_MAXDEVICE        1
+#if defined(CONFIG_D2NET_V2)
+#define CONFIG_SYS_PROMPT		"d2v2> "
+#elif defined(CONFIG_NET2BIG_V2)
+#define CONFIG_SYS_PROMPT		"2big2> "
+#else
+#define CONFIG_SYS_PROMPT		"ns2> "
+#endif
+
+/*
+ * Enable platform initialisation via misc_init_r() function
+ */
+#define CONFIG_MISC_INIT_R
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS		{1, 0} /* enable port 0 only */
+#define CONFIG_NETCONSOLE
+#endif
+
+/*
+ * SATA Driver configuration
+ */
+#ifdef CONFIG_MVSATA_IDE
+#define CONFIG_SYS_ATA_IDE0_OFFSET      MV_SATA_PORT0_OFFSET
+#if defined(CONFIG_NETSPACE_MAX_V2) || defined(CONFIG_D2NET_V2) || \
+	defined(CONFIG_NET2BIG_V2)
+#define CONFIG_SYS_ATA_IDE1_OFFSET      MV_SATA_PORT1_OFFSET
+#endif
+#endif /* CONFIG_MVSATA_IDE */
+
+/*
+ * Enable GPI0 support
+ */
+#define CONFIG_KIRKWOOD_GPIO
+
+/*
+ * Enable I2C support
+ */
+#ifdef CONFIG_CMD_I2C
+/* I2C EEPROM HT24LC04 (512B - 32 pages of 16 Bytes) */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4 /* 16-byte page size */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1 /* 8-bit device address */
+#if defined(CONFIG_NET2BIG_V2)
+#define CONFIG_SYS_I2C_G762_ADDR		0x3e
+#endif
+#endif /* CONFIG_CMD_I2C */
+
+/*
+ * Partition support
+ */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+
+/*
+ * File systems support
+ */
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+
+/*
+ * Use the HUSH parser
+ */
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Console configuration
+ */
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+/*
+ * Enable device tree support
+ */
+#define CONFIG_OF_LIBFDT
+
+/*
+ * Environment variables configurations
+ */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SECT_SIZE		0x10000	/* 64KB */
+#define CONFIG_ENV_SIZE			0x1000	/* 4KB */
+#define CONFIG_ENV_ADDR			0x70000
+#define CONFIG_ENV_OFFSET		0x70000	/* env starts here */
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_BOOTARGS "console=ttyS0,115200"
+
+#define CONFIG_BOOTCOMMAND					\
+	"dhcp && run netconsole; "				\
+	"if run usbload || run diskload; then bootm; fi"
+
+#define CONFIG_EXTRA_ENV_SETTINGS				\
+	"stdin=serial\0"					\
+	"stdout=serial\0"					\
+	"stderr=serial\0"					\
+	"bootfile=uImage\0"					\
+	"loadaddr=0x800000\0"					\
+	"autoload=no\0"						\
+	"netconsole="						\
+		"set stdin $stdin,nc; "				\
+		"set stdout $stdout,nc; "			\
+		"set stderr $stderr,nc;\0"			\
+	"diskload=ide reset && "				\
+		"ext2load ide 0:1 $loadaddr /boot/$bootfile\0"	\
+	"usbload=usb start && "					\
+		"fatload usb 0:1 $loadaddr /boot/$bootfile\0"
+
+#endif /* _CONFIG_LACIE_KW_H */
diff --git a/qemu/roms/u-boot/include/configs/lager.h b/qemu/roms/u-boot/include/configs/lager.h
new file mode 100644
index 000000000..b420e45e6
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/lager.h
@@ -0,0 +1,199 @@
+/*
+ * include/configs/lager.h
+ *     This file is lager board configuration.
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __LAGER_H
+#define __LAGER_H
+
+#undef DEBUG
+#define CONFIG_ARMV7
+#define CONFIG_R8A7790
+#define CONFIG_RMOBILE
+#define CONFIG_RMOBILE_BOARD_STRING "Lager"
+#define CONFIG_SH_GPIO_PFC
+#define MACH_TYPE_LAGER		4538
+#define CONFIG_MACH_TYPE	MACH_TYPE_LAGER
+
+#include <asm/arch/rmobile.h>
+
+#define	CONFIG_CMD_EDITENV
+#define	CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_DFL
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_BOOTZ
+
+#if defined(CONFIG_SYS_USE_BOOT_NORFLASH)
+#define CONFIG_CMD_FLASH
+#define CONFIG_SYS_TEXT_BASE	0x00000000
+#else
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_SYS_TEXT_BASE	0xE8080000
+#endif
+
+#define	CONFIG_CMDLINE_TAG
+#define	CONFIG_SETUP_MEMORY_TAGS
+#define	CONFIG_INITRD_TAG
+#define	CONFIG_CMDLINE_EDITING
+#define	CONFIG_OF_LIBFDT
+
+/* #define CONFIG_OF_LIBFDT */
+#define BOARD_LATE_INIT
+
+#define CONFIG_BAUDRATE		38400
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTARGS		""
+
+#define CONFIG_VERSION_VARIABLE
+#undef	CONFIG_SHOW_BOOT_PROGRESS
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_USE_ARCH_MEMSET
+#define CONFIG_USE_ARCH_MEMCPY
+#define CONFIG_TMU_TIMER
+
+/* STACK */
+#define CONFIG_SYS_INIT_SP_ADDR		0xE827fffc
+#define STACK_AREA_SIZE				0xC000
+#define LOW_LEVEL_MERAM_STACK	\
+		(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
+
+/* MEMORY */
+#define LAGER_SDRAM_BASE	0x40000000
+#define LAGER_SDRAM_SIZE	(2048u * 1024 * 1024)
+#define LAGER_UBOOT_SDRAM_SIZE	(512 * 1024 * 1024)
+
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_PBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE		512
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 38400, 115200 }
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE
+#define CONFIG_CONS_SCIF0
+#define SCIF0_BASE		0xe6e60000
+#undef	CONFIG_SYS_CONSOLE_INFO_QUIET
+#undef	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#undef	CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+
+#define CONFIG_SYS_MEMTEST_START	(LAGER_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
+					 504 * 1024 * 1024)
+#undef	CONFIG_SYS_ALT_MEMTEST
+#undef	CONFIG_SYS_MEMTEST_SCRATCH
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE
+
+#define CONFIG_SYS_SDRAM_BASE		(LAGER_SDRAM_BASE)
+#define CONFIG_SYS_SDRAM_SIZE		(LAGER_UBOOT_SDRAM_SIZE)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x7fc0)
+#define CONFIG_NR_DRAM_BANKS		1
+
+#define CONFIG_SYS_MONITOR_BASE		0x00000000
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(1 * 1024 * 1024)
+#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
+
+#if defined(CONFIG_SYS_USE_BOOT_NORFLASH)
+/* USE NOR FLASH */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define	CONFIG_FLASH_CFI_DRIVER
+#define	CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define	CONFIG_FLASH_SHOW_PROGRESS	45
+#define CONFIG_SYS_FLASH_BASE		0x00000000
+#define	CONFIG_SYS_FLASH_SIZE		0x04000000	/* 64 MB */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ (CONFIG_SYS_FLASH_BASE) }
+#define	CONFIG_SYS_FLASH_BANKS_SIZES	{ (CONFIG_SYS_FLASH_SIZE) }
+#define CONFIG_SYS_FLASH_ERASE_TOUT	3000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	3000
+#define CONFIG_SYS_FLASH_LOCK_TOUT	3000
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	3000
+
+/* ENV setting */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + \
+				 CONFIG_SYS_MONITOR_LEN)
+
+#else /* CONFIG_SYS_USE_BOOT_NORFLASH */
+
+/* USE SPI */
+#define CONFIG_SPI
+#define CONFIG_SPI_FLASH_BAR
+#define CONFIG_SH_QSPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_SYS_NO_FLASH
+
+/* ENV setting */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_ADDR	0xC0000
+#endif
+
+/* Common ENV setting */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_SECT_SIZE	(256 * 1024)
+#define CONFIG_ENV_OFFSET	(CONFIG_ENV_ADDR)
+#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_SYS_MONITOR_LEN)
+
+/* SH Ether */
+#define	CONFIG_NET_MULTI
+#define CONFIG_SH_ETHER
+#define CONFIG_SH_ETHER_USE_PORT	0
+#define CONFIG_SH_ETHER_PHY_ADDR	0x1
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
+#define CONFIG_SH_ETHER_ALIGNE_SIZE	64
+#define CONFIG_SH_ETHER_CACHE_WRITEBACK
+#define CONFIG_SH_ETHER_CACHE_INVALIDATE
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_RCAR
+#define CONFIG_SYS_RCAR_I2C0_BASE	0xE6508000
+#define CONFIG_SYS_RCAR_I2C0_SPEED	400000
+#define CONFIG_SYS_RCAR_I2C1_BASE	0xE6518000
+#define CONFIG_SYS_RCAR_I2C1_SPEED	400000
+#define CONFIG_SYS_RCAR_I2C2_BASE	0xE6530000
+#define CONFIG_SYS_RCAR_I2C2_SPEED	400000
+#define CONFIG_SYS_RCAR_I2C3_BASE	0xE6540000
+#define CONFIG_SYS_RCAR_I2C3_SPEED	400000
+#define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS	4
+
+#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
+
+/* Board Clock */
+#define CONFIG_BASE_CLK_FREQ	20000000u
+#define CONFIG_SH_TMU_CLK_FREQ	(CONFIG_BASE_CLK_FREQ / 2) /* EXT / 2 */
+#define CONFIG_PLL1_CLK_FREQ	(CONFIG_BASE_CLK_FREQ * 156 / 2)
+#define CONFIG_PLL1_DIV2_CLK_FREQ	(CONFIG_PLL1_CLK_FREQ / 2)
+#define CONFIG_MP_CLK_FREQ	(CONFIG_PLL1_DIV2_CLK_FREQ / 15)
+#define CONFIG_HP_CLK_FREQ	(CONFIG_PLL1_CLK_FREQ / 12)
+#define CONFIG_SH_SCIF_CLK_FREQ	CONFIG_MP_CLK_FREQ
+
+#define CONFIG_SYS_TMU_CLK_DIV	4
+
+#endif	/* __LAGER_H */
diff --git a/qemu/roms/u-boot/include/configs/lp8x4x.h b/qemu/roms/u-boot/include/configs/lp8x4x.h
new file mode 100644
index 000000000..a26937265
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/lp8x4x.h
@@ -0,0 +1,241 @@
+/*
+ * ICP DAS LP-8x4x configuration file
+ *
+ * Copyright (C) 2013 Sergey Yanovich <ynvich@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef	__CONFIG_H
+#define	__CONFIG_H
+
+/*
+ * High Level Board Configuration Options
+ */
+#define	CONFIG_CPU_PXA27X			/* Marvell PXA270 CPU */
+#define	MACH_TYPE_LP8X4X		4539	/* ICP DAS LP-8x4x */
+#define	CONFIG_MACH_TYPE		MACH_TYPE_LP8X4X
+#define	CONFIG_SYS_TEXT_BASE		0x00000000
+
+#define	CONFIG_SYS_MALLOC_LEN		(128*1024)
+#define	CONFIG_ARCH_CPU_INIT
+#define	CONFIG_BOOTCOMMAND		\
+	"bootm 80000 - 240000;"
+
+#define	CONFIG_BOOTARGS			\
+	"console=ttyS0,115200 mem=128M root=/dev/mmcblk0p1 rw" \
+	"init=/sbin/init rootfstype=ext4 rootwait"
+
+#define	CONFIG_TIMESTAMP
+#define	CONFIG_BOOTDELAY		2	/* Autoboot delay */
+#define	CONFIG_CMDLINE_TAG
+#define	CONFIG_SETUP_MEMORY_TAGS
+#define	CONFIG_LZMA			/* LZMA compression support */
+#define	CONFIG_OF_LIBFDT
+
+/*
+ * Serial Console Configuration
+ */
+#define	CONFIG_PXA_SERIAL
+#define	CONFIG_FFUART			1
+#define	CONFIG_CONS_INDEX		3
+#define	CONFIG_BAUDRATE			115200
+
+/*
+ * Bootloader Components Configuration
+ */
+#include <config_cmd_default.h>
+
+#define	CONFIG_CMD_NET
+#define	CONFIG_CMD_ENV
+#undef	CONFIG_CMD_IMLS
+#define	CONFIG_CMD_MMC
+#define	CONFIG_CMD_USB
+#undef	CONFIG_LCD
+#undef	CONFIG_CMD_IDE
+
+/*
+ * Networking Configuration
+ * chip on the ICPDAS LINPAC board
+ */
+#ifdef	CONFIG_CMD_NET
+#define	CONFIG_CMD_PING
+#define	CONFIG_CMD_DHCP
+
+#define	CONFIG_DRIVER_DM9000		1
+#define	CONFIG_DM9000_BASE		0x0C000000
+#define	DM9000_IO			0x0C000000
+#define	DM9000_DATA			0x0C004000
+#define	DM9000_IO_2			0x0D000000
+#define	DM9000_DATA_2			0x0D004000
+#define	CONFIG_NET_RETRY_COUNT		10
+
+#define	CONFIG_BOOTP_BOOTFILESIZE
+#define	CONFIG_BOOTP_BOOTPATH
+#define	CONFIG_BOOTP_GATEWAY
+#define	CONFIG_BOOTP_HOSTNAME
+#endif
+
+/*
+ * MMC Card Configuration
+ */
+#ifdef	CONFIG_CMD_MMC
+#define	CONFIG_MMC
+#define	CONFIG_GENERIC_MMC
+#define	CONFIG_PXA_MMC_GENERIC
+#define	CONFIG_CMD_FAT
+#define	CONFIG_CMD_EXT2
+#define	CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * KGDB
+ */
+#ifdef	CONFIG_CMD_KGDB
+#define	CONFIG_KGDB_BAUDRATE		230400	/* kgdb serial port speed */
+#endif
+
+/*
+ * HUSH Shell Configuration
+ */
+#define	CONFIG_SYS_HUSH_PARSER		1
+
+#define	CONFIG_SYS_LONGHELP
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define	CONFIG_SYS_PROMPT		"$ "
+#else
+#endif
+#define	CONFIG_SYS_CBSIZE		256
+#define	CONFIG_SYS_PBSIZE		\
+	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define	CONFIG_SYS_MAXARGS		16
+#define	CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+#define	CONFIG_SYS_DEVICE_NULLDEV	1
+#define	CONFIG_CMDLINE_EDITING		1
+#define	CONFIG_AUTO_COMPLETE		1
+
+/*
+ * DRAM Map
+ */
+#define	CONFIG_NR_DRAM_BANKS		1		/* 1 bank of DRAM */
+#define	PHYS_SDRAM_1			0xa0000000	/* SDRAM Bank #1 */
+#define	PHYS_SDRAM_1_SIZE		0x08000000	/* 128 MB */
+
+#define	CONFIG_SYS_DRAM_BASE		0xa0000000	/* CS0 */
+#define	CONFIG_SYS_DRAM_SIZE		0x08000000	/* 128 MB DRAM */
+
+#define	CONFIG_SYS_MEMTEST_START	0xa0400000	/* memtest works on */
+#define	CONFIG_SYS_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM */
+
+#define	CONFIG_SYS_LOAD_ADDR		0xa0008000
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+/* Use first 64kb bank of the internal SRAM */
+#define	CONFIG_SYS_INIT_SP_ADDR		0x5c010000
+
+/*
+ * NOR FLASH
+ */
+#define	CONFIG_SYS_MONITOR_BASE		0x0
+#define	CONFIG_SYS_MONITOR_LEN		0x40000
+#define	CONFIG_ENV_ADDR			\
+			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define	CONFIG_ENV_SIZE			0x40000
+#define	CONFIG_ENV_SECT_SIZE		0x40000
+
+#define	PHYS_FLASH_1			0x00000000	/* Flash Bank #1 */
+#define	PHYS_FLASH_2			0x04000000	/* Flash Bank #2 */
+
+#define	CONFIG_SYS_FLASH_CFI
+#define	CONFIG_FLASH_CFI_DRIVER		1
+
+#define	CONFIG_SYS_MAX_FLASH_SECT	(4 + 255)
+#define	CONFIG_SYS_MAX_FLASH_BANKS	2
+#define	CONFIG_SYS_FLASH_BANKS_LIST	{ PHYS_FLASH_1, PHYS_FLASH_2 }
+
+#define	CONFIG_SYS_FLASH_ERASE_TOUT	(25*CONFIG_SYS_HZ)
+#define	CONFIG_SYS_FLASH_WRITE_TOUT	(25*CONFIG_SYS_HZ)
+
+#define	CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+#define	CONFIG_SYS_FLASH_PROTECTION		1
+
+#define	CONFIG_ENV_IS_IN_FLASH		1
+
+/*
+ * GPIO settings
+ */
+#define	CONFIG_SYS_GPSR0_VAL	0x0808c014
+#define	CONFIG_SYS_GPSR1_VAL	0x00cf0002
+#define	CONFIG_SYS_GPSR2_VAL	0x0221c000
+#define	CONFIG_SYS_GPSR3_VAL	0x00020000
+
+#define	CONFIG_SYS_GPCR0_VAL	0x00000000
+#define	CONFIG_SYS_GPCR1_VAL	0x0000ab80
+#define	CONFIG_SYS_GPCR2_VAL	0x00100000
+#define	CONFIG_SYS_GPCR3_VAL	0x0
+
+#define	CONFIG_SYS_GPDR0_VAL	0xc0e9ddf4
+#define	CONFIG_SYS_GPDR1_VAL	0xfcffab83
+#define	CONFIG_SYS_GPDR2_VAL	0x02f1ffff
+#define	CONFIG_SYS_GPDR3_VAL	0x00021b81
+
+#define	CONFIG_SYS_GAFR0_L_VAL	0x80000000
+#define	CONFIG_SYS_GAFR0_U_VAL	0xa5e54018
+#define	CONFIG_SYS_GAFR1_L_VAL	0x999a955a
+#define	CONFIG_SYS_GAFR1_U_VAL	0xaaa5a00a
+#define	CONFIG_SYS_GAFR2_L_VAL	0xaaaaaaaa
+#define	CONFIG_SYS_GAFR2_U_VAL	0x55f9a402
+#define	CONFIG_SYS_GAFR3_L_VAL	0x540a950c
+#define	CONFIG_SYS_GAFR3_U_VAL	0x00001599
+
+#define	CONFIG_SYS_PSSR_VAL	0x32
+
+/*
+ * Clock settings
+ */
+#define	CONFIG_SYS_CKEN		0x005002c0
+#define	CONFIG_SYS_CCCR		0x02000290
+#define	CONFIG_SYS_CLKCFG	0x0000000b
+
+/*
+ * Memory settings
+ */
+#define	CONFIG_SYS_MSC0_VAL	0x2bd8aad2
+#define	CONFIG_SYS_MSC1_VAL	0xb8c9b8dc
+#define	CONFIG_SYS_MSC2_VAL	0xfff9b8c9
+#define	CONFIG_SYS_FLYCNFG_VAL	0x00010001
+#define	CONFIG_SYS_MDREFR_VAL	0x2093e018
+#define	CONFIG_SYS_MDCNFG_VAL	0x890009d1
+#define	CONFIG_SYS_MDMRS_VAL	0x00220022
+#define	CONFIG_SYS_SXCNFG_VAL	0x40044004
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define	CONFIG_SYS_MECR_VAL	0x00000001
+#define	CONFIG_SYS_MCMEM0_VAL	0x0000c497
+#define	CONFIG_SYS_MCMEM1_VAL	0x0000c497
+#define	CONFIG_SYS_MCATT0_VAL	0x0000c497
+#define	CONFIG_SYS_MCATT1_VAL	0x0000c497
+#define	CONFIG_SYS_MCIO0_VAL	0x00008407
+#define	CONFIG_SYS_MCIO1_VAL	0x00008407
+
+/*
+ * LCD
+ */
+#ifdef	CONFIG_LCD
+#define	CONFIG_VOIPAC_LCD
+#endif
+
+/*
+ * USB
+ */
+#ifdef	CONFIG_CMD_USB
+#define	CONFIG_USB_OHCI_NEW
+#define	CONFIG_SYS_USB_OHCI_BOARD_INIT
+#define	CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+#define	CONFIG_SYS_USB_OHCI_REGS_BASE	0x4C000000
+#define	CONFIG_SYS_USB_OHCI_SLOT_NAME	"lp8x4x"
+#define	CONFIG_USB_STORAGE
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/lsxl.h b/qemu/roms/u-boot/include/configs/lsxl.h
new file mode 100644
index 000000000..96a889fe8
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/lsxl.h
@@ -0,0 +1,166 @@
+/*
+ * Copyright (c) 2012 Michael Walle
+ * Michael Walle <michael@walle.cc>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CONFIG_LSXL_H
+#define _CONFIG_LSXL_H
+
+/*
+ * Version number information
+ */
+#if defined(CONFIG_LSCHLV2)
+#define CONFIG_IDENT_STRING " LS-CHLv2"
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-lschl.cfg
+#define CONFIG_MACH_TYPE 3006
+#define CONFIG_SYS_TCLK 166666667 /* 166 MHz */
+#elif defined(CONFIG_LSXHL)
+#define CONFIG_IDENT_STRING " LS-XHL"
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-lsxhl.cfg
+#define CONFIG_MACH_TYPE 2663
+/* CONFIG_SYS_TCLK is 200000000 by default */
+#else
+#error "unknown board"
+#endif
+
+/*
+ * General configuration options
+ */
+#define CONFIG_FEROCEON_88FR131		/* CPU Core subversion */
+#define CONFIG_KIRKWOOD			/* SOC Family Name */
+#define CONFIG_KW88F6281		/* SOC Name */
+
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_SHOW_BOOT_PROGRESS
+
+#define CONFIG_RANDOM_MACADDR
+#define CONFIG_LIB_RAND
+#define CONFIG_KIRKWOOD_GPIO
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+
+/*
+ * Enable u-boot API for standalone programs.
+ */
+#define CONFIG_API
+
+/*
+ * Commands configuration
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_USB
+
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/* ST M25P40 */
+#undef CONFIG_SPI_FLASH_MACRONIX
+#define CONFIG_SPI_FLASH_STMICRO
+#undef CONFIG_ENV_SPI_MAX_HZ
+#define CONFIG_ENV_SPI_MAX_HZ		25000000
+#undef CONFIG_SF_DEFAULT_SPEED
+#define CONFIG_SF_DEFAULT_SPEED		25000000
+
+
+#undef CONFIG_SYS_PROMPT
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+
+/*
+ *  Environment variables configurations
+ */
+#ifdef CONFIG_SPI_FLASH
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	8
+#define CONFIG_ENV_IS_IN_SPI_FLASH	1
+#define CONFIG_ENV_SECT_SIZE		0x10000 /* 64K */
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+#define CONFIG_ENV_SIZE			0x10000 /* 64k */
+#define CONFIG_ENV_OFFSET		0x70000 /* env starts here */
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_LOADADDR		0x00800000
+#define CONFIG_BOOTCOMMAND	"run bootcmd_${bootsource}"
+#define CONFIG_BOOTARGS		"console=ttyS0,115200 root=/dev/sda2"
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"bootsource=hdd\0"						\
+	"hdpart=0:1\0"							\
+	"bootcmd_net=bootp 0x00100000 uImage "				\
+		"&& tftpboot 0x00800000 uInitrd "			\
+		"&& bootm 0x00100000 0x00800000\0"			\
+	"bootcmd_hdd=ide reset "					\
+		"&& ext2load ide ${hdpart} 0x00100000 /uImage "		\
+		"&& ext2load ide ${hdpart} 0x00800000 /uInitrd "	\
+		"&& bootm 0x00100000 0x00800000\0"			\
+	"bootcmd_usb=usb start "					\
+		"&& fatload usb 0:1 0x00100000 /uImage "		\
+		"&& fatload usb 0:1 0x00800000 /uInitrd "		\
+		"&& bootm 0x00100000 0x00800000\0"			\
+	"bootcmd_rescue=run config_nc_dhcp; run nc\0"			\
+	"eraseenv=sf probe 0 "						\
+		"&& sf erase " __stringify(CONFIG_ENV_OFFSET)		\
+			" +" __stringify(CONFIG_ENV_SIZE) "\0"		\
+	"config_nc_dhcp=setenv autoload_old ${autoload}; "		\
+		"setenv autoload no "					\
+		"&& bootp "						\
+		"&& setenv ncip "					\
+		"&& setenv autoload ${autoload_old}; "			\
+		"setenv autoload_old\0"					\
+	"standard_env=setenv ipaddr; setenv netmask; setenv serverip; "	\
+		"setenv ncip; setenv gatewayip; setenv ethact; "	\
+		"setenv bootfile; setenv dnsip; "			\
+		"setenv bootsource hdd; run ser\0"			\
+	"restore_env=run standard_env; saveenv; reset\0"		\
+	"ser=setenv stdin serial; setenv stdout serial; "		\
+		"setenv stderr serial\0"				\
+	"nc=setenv stdin nc; setenv stdout nc; setenv stderr nc\0"	\
+	"stdin=serial\0"						\
+	"stdout=serial\0"						\
+	"stderr=serial\0"
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS		{0, 1} /* enable port 1 only */
+#define CONFIG_PHY_BASE_ADR		7
+#undef CONFIG_RESET_PHY_R
+#endif /* CONFIG_CMD_NET */
+
+#ifdef CONFIG_CMD_IDE
+#undef CONFIG_IDE_LED
+#undef CONFIG_SYS_IDE_MAXBUS
+#define CONFIG_SYS_IDE_MAXBUS		1
+#undef CONFIG_SYS_IDE_MAXDEVICE
+#define CONFIG_SYS_IDE_MAXDEVICE	1
+#define CONFIG_SYS_ATA_IDE0_OFFSET	MV_SATA_PORT0_OFFSET
+#endif
+
+#endif /* _CONFIG_LSXL_H */
diff --git a/qemu/roms/u-boot/include/configs/luan.h b/qemu/roms/u-boot/include/configs/luan.h
new file mode 100644
index 000000000..15e4a7e5c
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/luan.h
@@ -0,0 +1,177 @@
+/*
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ * John Otken, jotken@softadvances.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/************************************************************************
+ * luan.h - configuration for LUAN board
+ ***********************************************************************/
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_LUAN		1	/* Board is Luan		*/
+#define CONFIG_440SP		1	/* Specific PPC440SP support    */
+#define CONFIG_440		1
+#define CONFIG_SYS_CLK_FREQ	33333333 /* external freq to pll	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFB0000
+
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME		luan
+#include "amcc-common.h"
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_LARGE_FLASH		0xffc00000	/* 4MB flash address CS0 */
+#define CONFIG_SYS_SMALL_FLASH		0xff900000	/* 1MB flash address CS2 */
+#define CONFIG_SYS_SRAM_BASE		0xff800000	/* 1MB SRAM  address CS2 */
+#define CONFIG_SYS_SRAM_SIZE		(1 << 20)
+#define CONFIG_SYS_EPLD_BASE		0xff000000	/* EPLD and FRAM     CS1 */
+
+#define CONFIG_SYS_ISRAM_BASE	        0xf8000000	/* internal 8k SRAM (L2 cache) */
+
+#define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped pci memory */
+#define CONFIG_SYS_PCI_BASE		0xd0000000	/* internal PCI regs */
+#define CONFIG_SYS_PCI_TARGBASE	0x80000000	/* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
+
+#if CONFIG_SYS_LARGE_FLASH == 0xffc00000
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_LARGE_FLASH
+#else
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_SMALL_FLASH
+#endif
+
+#if CONFIG_SYS_SRAM_BASE
+#define CONFIG_SYS_KBYTES_SDRAM	1024*2
+#else
+#define CONFIG_SYS_KBYTES_SDRAM	1024
+#endif
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in SDRAM)
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_ISRAM_BASE
+#define CONFIG_SYS_INIT_RAM_SIZE	(8 << 10)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#define CONFIG_SYS_EXT_SERIAL_CLOCK	11059200 /* external 11.059MHz clk */
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+/*
+ * Define here the location of the environment variables (FLASH or EEPROM).
+ * Note: DENX encourages to use redundant environment in FLASH.
+ */
+#define CONFIG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	3	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#define CONFIG_SYS_FLASH_ADDR0         0x555
+#define CONFIG_SYS_FLASH_ADDR1         0x2aa
+#define CONFIG_SYS_FLASH_WORD_SIZE     unsigned char
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	0x10000 /* size of one complete sector	*/
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+#endif /* CONFIG_ENV_IS_IN_FLASH */
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CONFIG_SPD_EEPROM	1	/* Use SPD EEPROM for setup	*/
+#define SPD_EEPROM_ADDRESS	{0x53, 0x52}	/* SPD i2c spd addresses*/
+#define CONFIG_DDR_ECC		1	/* with ECC support		*/
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
+
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR	(0xa8>>1)
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+/*
+ * Default environment variables
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_AMCC_DEF_ENV						\
+	CONFIG_AMCC_DEF_ENV_PPC						\
+	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
+	"kernel_addr=fc000000\0"					\
+	"ramdisk_addr=fc100000\0"					\
+	""
+
+#define CONFIG_HAS_ETH0
+#define CONFIG_PHY_ADDR		1
+#define CONFIG_CIS8201_PHY	1	/* Enable 'special' RGMII mode for Cicada phy */
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+
+#ifdef DEBUG
+#define CONFIG_PANIC_HANG
+#else
+#define CONFIG_HW_WATCHDOG			/* watchdog */
+#endif
+
+/*
+ * Commands additional to the ones defined in amcc-common.h
+ */
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_SDRAM
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#if defined(CONFIG_CMD_PCI)
+
+/* General PCI */
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_PNP			/* do (not) pci plug-and-play   */
+#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
+
+/* Board-specific PCI */
+#define CONFIG_SYS_PCI_TARGET_INIT
+#undef  CONFIG_SYS_PCI_MASTER_INIT
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x4403	/* whatever */
+
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/lwmon.h b/qemu/roms/u-boot/include/configs/lwmon.h
new file mode 100644
index 000000000..f20458733
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/lwmon.h
@@ -0,0 +1,587 @@
+/*
+ * (C) Copyright 2001-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* External logbuffer support */
+#define CONFIG_LOGBUFFER
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC823		1	/* This is a MPC823E CPU	*/
+#define CONFIG_LWMON		1	/* ...on a LWMON board		*/
+
+#define	CONFIG_SYS_TEXT_BASE	0x40000000
+
+/* Default Ethernet MAC address */
+#define CONFIG_ETHADDR          00:11:B0:00:00:00
+
+/* The default Ethernet MAC address can be overwritten just once */
+#ifdef CONFIG_ETHADDR
+#define CONFIG_OVERWRITE_ETHADDR_ONCE   1
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f()	*/
+#define CONFIG_BOARD_POSTCLK_INIT 1	/* Call board_postclk_init()	*/
+#define CONFIG_MISC_INIT_R	1	/* Call misc_init_r()		*/
+
+#define CONFIG_LCD		1	/* use LCD controller ...	*/
+#define CONFIG_MPC8XX_LCD
+#define CONFIG_HLD1045		1	/* ... with a HLD1045 display	*/
+
+#define CONFIG_LCD_LOGO		1	/* print our logo on the LCD	*/
+#define CONFIG_LCD_INFO		1	/* ... and some board info	*/
+#define	CONFIG_SPLASH_SCREEN		/* ... with splashscreen support*/
+
+#define CONFIG_8xx_CONS_SMC2	1	/* Console is on SMC2		*/
+#define CONFIG_8xx_CONS_SCC2	1	/* Console is on SCC2		*/
+
+#define CONFIG_BAUDRATE		115200	/* with watchdog >= 38400 needed */
+
+#define CONFIG_BOOTDELAY	1	/* autoboot after 1 second	*/
+
+#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+
+/* pre-boot commands */
+#define	CONFIG_PREBOOT		"setenv bootdelay 15"
+
+#undef	CONFIG_BOOTARGS
+
+/* POST support */
+#define CONFIG_POST		(CONFIG_SYS_POST_CACHE	   | \
+				 CONFIG_SYS_POST_WATCHDOG | \
+				 CONFIG_SYS_POST_RTC	   | \
+				 CONFIG_SYS_POST_MEMORY   | \
+				 CONFIG_SYS_POST_CPU	   | \
+				 CONFIG_SYS_POST_UART	   | \
+				 CONFIG_SYS_POST_ETHER    | \
+				 CONFIG_SYS_POST_I2C	   | \
+				 CONFIG_SYS_POST_SPI	   | \
+				 CONFIG_SYS_POST_USB	   | \
+				 CONFIG_SYS_POST_SPR	   | \
+				 CONFIG_SYS_POST_SYSMON)
+
+/*
+ * Keyboard commands:
+ * # = 0x28 = ENTER :		enable bootmessages on LCD
+ * 2 = 0x3A+0x3C = F1 + F3 :	enable update mode
+ * 3 = 0x3C+0x3F = F3 + F6 :	enable test mode
+ */
+
+#define CONFIG_BOOTCOMMAND "source 40040000;saveenv"
+
+/*	"gatewayip=10.8.211.250\0"			                \ */
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"kernel_addr=40080000\0"					\
+	"ramdisk_addr=40280000\0"					\
+	"netmask=255.255.192.0\0"				        \
+	"serverip=10.8.2.101\0"				                \
+	"ipaddr=10.8.57.0\0"				                \
+	"magic_keys=#23\0"						\
+	"key_magic#=28\0"						\
+	"key_cmd#=setenv addfb setenv 'bootargs $bootargs console=tty0'\0" \
+	"key_magic2=3A+3C\0"						\
+	"key_cmd2=echo *** Entering Update Mode ***;"			\
+		"if fatload ide 0:3 10000 update.scr;"			\
+			"then source 10000;"				\
+			"else echo *** UPDATE FAILED ***;"		\
+		"fi\0"							\
+	"key_magic3=3C+3F\0"						\
+	"key_cmd3=echo *** Entering Test Mode ***;"			\
+		"setenv add_misc 'setenv bootargs $bootargs testmode'\0" \
+	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath\0" \
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addfb=setenv bootargs $bootargs console=ttyS1,$baudrate\0"	\
+	"addip=setenv bootargs $bootargs "				\
+		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \
+		"panic=1\0"						\
+	"add_wdt=setenv bootargs $bootargs $wdt_args\0"			\
+	"add_misc=setenv bootargs $bootargs runmode\0"			\
+	"flash_nfs=run nfsargs addip add_wdt addfb add_misc;"		\
+		"bootm $kernel_addr\0"					\
+	"flash_self=run ramargs addip add_wdt addfb add_misc;"		\
+		"bootm $kernel_addr $ramdisk_addr\0"			\
+	"net_nfs=tftp 100000 /tftpboot/uImage.lwmon;"			\
+		"run nfsargs addip add_wdt addfb;bootm\0"		\
+	"rootpath=/opt/eldk/ppc_8xx\0"					\
+	"load=tftp 100000 /tftpboot/u-boot.bin\0"			\
+	"update=protect off 1:0;era 1:0;cp.b 100000 40000000 $filesize\0" \
+	"wdt_args=wdt_8xx=off\0"					\
+	"verify=no"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#define	CONFIG_WATCHDOG		1	/* watchdog enabled		*/
+#define	CONFIG_SYS_WATCHDOG_FREQ       (CONFIG_SYS_HZ / 20)
+
+#undef	CONFIG_STATUS_LED		/* Status LED disabled		*/
+
+/* enable I2C and select the hardware/software driver */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED	93000	/* 93 kHz is supposed to work */
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PB_SCL		0x00000020	/* PB 26 */
+#define PB_SDA		0x00000010	/* PB 27 */
+
+#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
+#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
+#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
+#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
+#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
+#define I2C_DELAY	udelay(2)	/* 1/4 I2C clock duration */
+
+
+#define CONFIG_RTC_PCF8563		/* use Philips PCF8563 RTC	*/
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BMP
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
+#ifdef CONFIG_POST
+#define CONFIG_CMD_DIAG
+#endif
+
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+
+#define	CONFIG_SYS_HUSH_PARSER		1	/* use "hush" command parser	*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x00F00000	/* 1 ... 15MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address */
+
+#define CONFIG_SYS_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/
+
+/*
+ * When the watchdog is enabled, output must be fast enough in Linux.
+ */
+#ifdef CONFIG_WATCHDOG
+#define CONFIG_SYS_BAUDRATE_TABLE	{		38400, 57600, 115200 }
+#endif
+
+/*----------------------------------------------------------------------*/
+#define CONFIG_MODEM_SUPPORT	1	/* enable modem initialization stuff */
+#undef CONFIG_MODEM_SUPPORT_DEBUG
+
+#define	CONFIG_MODEM_KEY_MAGIC	"3C+3D"	/* press F3 + F4 keys to enable modem */
+#define	CONFIG_POST_KEY_MAGIC	"3C+3E"	/* press F3 + F5 keys to force POST */
+#if 0
+#define	CONFIG_AUTOBOOT_KEYED		/* Enable "password" protection	*/
+#define CONFIG_AUTOBOOT_PROMPT	\
+	"\nEnter password - autoboot in %d sec...\n", bootdelay
+#define CONFIG_AUTOBOOT_DELAY_STR	"  "	/* "password"	*/
+#endif
+/*----------------------------------------------------------------------*/
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#if defined(DEBUG) || defined(CONFIG_CMD_IDE)
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#else
+#define CONFIG_SYS_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
+#endif
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	180000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	600	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_BUFFER_WRITE_TOUT	2048	/* Timeout for Flash Buffer Write (in ms)	*/
+/* Buffer size.
+   We have two flash devices connected in parallel.
+   Each device incorporates a Write Buffer of 32 bytes.
+ */
+#define CONFIG_SYS_FLASH_BUFFER_SIZE	(2*32)
+
+/* Put environment in flash which is much faster to boot than using the EEPROM	*/
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_ADDR	    0x40040000	/* Address    of Environment Sector	*/
+#define CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment		*/
+#define CONFIG_ENV_SECT_SIZE	0x40000 /* we have BIG sectors only :-(		*/
+
+/*-----------------------------------------------------------------------
+ * I2C/EEPROM Configuration
+ */
+
+#define CONFIG_SYS_I2C_AUDIO_ADDR	0x28	/* Audio volume control			*/
+#define CONFIG_SYS_I2C_SYSMON_ADDR	0x2E	/* LM87 System Monitor			*/
+#define CONFIG_SYS_I2C_RTC_ADDR	0x51	/* PCF8563 RTC				*/
+#define CONFIG_SYS_I2C_POWER_A_ADDR	0x52	/* PCMCIA/USB power switch, channel A	*/
+#define CONFIG_SYS_I2C_POWER_B_ADDR	0x53	/* PCMCIA/USB power switch, channel B	*/
+#define CONFIG_SYS_I2C_KEYBD_ADDR	0x56	/* PIC LWE keyboard			*/
+#define CONFIG_SYS_I2C_PICIO_ADDR	0x57	/* PIC IO Expander			*/
+
+#undef	CONFIG_USE_FRAM			/* Use FRAM instead of EEPROM	*/
+
+#ifdef CONFIG_USE_FRAM	/* use FRAM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x55	/* FRAM FM24CL64		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+#else			/* use EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x58	/* EEPROM AT24C164		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* takes up to 10 msec	*/
+#endif	/* CONFIG_USE_FRAM */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+
+/* List of I2C addresses to be verified by POST */
+#ifdef CONFIG_USE_FRAM
+#define CONFIG_SYS_POST_I2C_ADDRS	{/* CONFIG_SYS_I2C_AUDIO_ADDR, */ \
+					 CONFIG_SYS_I2C_SYSMON_ADDR,	\
+					 CONFIG_SYS_I2C_RTC_ADDR,	\
+					 CONFIG_SYS_I2C_POWER_A_ADDR,	\
+					 CONFIG_SYS_I2C_POWER_B_ADDR,	\
+					 CONFIG_SYS_I2C_KEYBD_ADDR,	\
+					 CONFIG_SYS_I2C_PICIO_ADDR,	\
+					 CONFIG_SYS_I2C_EEPROM_ADDR,	\
+					}
+#else	/* Use EEPROM - which show up on 8 consequtive addresses */
+#define CONFIG_SYS_POST_I2C_ADDRS	{/* CONFIG_SYS_I2C_AUDIO_ADDR, */ \
+					 CONFIG_SYS_I2C_SYSMON_ADDR,	\
+					 CONFIG_SYS_I2C_RTC_ADDR,	\
+					 CONFIG_SYS_I2C_POWER_A_ADDR,	\
+					 CONFIG_SYS_I2C_POWER_B_ADDR,	\
+					 CONFIG_SYS_I2C_KEYBD_ADDR,	\
+					 CONFIG_SYS_I2C_PICIO_ADDR,	\
+					 CONFIG_SYS_I2C_EEPROM_ADDR+0,	\
+					 CONFIG_SYS_I2C_EEPROM_ADDR+1,	\
+					 CONFIG_SYS_I2C_EEPROM_ADDR+2,	\
+					 CONFIG_SYS_I2C_EEPROM_ADDR+3,	\
+					 CONFIG_SYS_I2C_EEPROM_ADDR+4,	\
+					 CONFIG_SYS_I2C_EEPROM_ADDR+5,	\
+					 CONFIG_SYS_I2C_EEPROM_ADDR+6,	\
+					 CONFIG_SYS_I2C_EEPROM_ADDR+7,	\
+					}
+#endif	/* CONFIG_USE_FRAM */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if 0 && defined(CONFIG_WATCHDOG)	/* LWMON uses external MAX706TESA WD */
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+/* EARB, DBGC and DBPC are initialised by the HCW */
+/* => 0x000000C0 */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_GB5E)
+/*#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit, set PLL multiplication factor !
+ */
+/* 0x00405000 */
+#define CONFIG_SYS_PLPRCR_MF	4	/* (4+1) * 13.2 = 66 MHz Clock */
+#define CONFIG_SYS_PLPRCR							\
+		(	(CONFIG_SYS_PLPRCR_MF << PLPRCR_MF_SHIFT) |		\
+			PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST |	\
+			/*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |		\
+			PLPRCR_CSR    /*| PLPRCR_LOLRE|PLPRCR_FIOPD*/	\
+		)
+
+#define CONFIG_8xx_GCLK_FREQ	((CONFIG_SYS_PLPRCR_MF+1)*13200000)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+/* 0x01800000 */
+#define CONFIG_SYS_SCCR	(SCCR_COM00	| /*SCCR_TBS|*/		\
+			 SCCR_RTDIV	|   SCCR_RTSEL	  |	\
+			 /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/	\
+			 SCCR_EBDF00 |	 SCCR_DFSYNC00 |	\
+			 SCCR_DFBRG00	|   SCCR_DFNL000  |	\
+			 SCCR_DFNH000	|   SCCR_DFLCD100 |	\
+			 SCCR_DFALCD01)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+/* 0x00C3 => 0x0003 */
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration Register		19-4
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RCCR 0x0000
+
+/*-----------------------------------------------------------------------
+ * RMDS - RISC Microcode Development Support Control Register
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RMDS 0
+
+/*-----------------------------------------------------------------------
+ *
+ * Interrupt Levels
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_CPM_INTERRUPT	13	/* SIU_LEVEL6	*/
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0x50000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0x54000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0x58000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0x5C000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_IDE_PREINIT	1	/* Use preinit IDE hook */
+#define CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card Adapter */
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
+#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
+
+#define CONFIG_SUPPORT_VFAT		/* enable VFAT support */
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_DER 0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH) - second Flash bank optional
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x41000000	/* FLASH bank #1	*/
+
+/* used to re-map FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CONFIG_SYS_REMAP_OR_AM		0xFF000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xFF000000	/* OR addr mask */
+
+/* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 8, EHTR = 0	*/
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_SCY_8_CLK)
+
+#define CONFIG_SYS_OR0_REMAP	( CONFIG_SYS_REMAP_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
+				CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \
+				CONFIG_SYS_OR_TIMING_FLASH)
+/* 16 bit, bank valid */
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
+
+#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
+
+/*
+ * BR3/OR3: SDRAM
+ *
+ * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
+ */
+#define SDRAM_BASE3_PRELIM	0x00000000	/* SDRAM bank */
+#define SDRAM_PRELIM_OR_AM	0xF0000000	/* map 256 MB (>SDRAM_MAX_SIZE!) */
+#define SDRAM_TIMING		OR_SCY_0_CLK	/* SDRAM-Timing */
+
+#define SDRAM_MAX_SIZE		0x08000000	/* max 128 MB SDRAM */
+
+#define CONFIG_SYS_OR3_PRELIM	(SDRAM_PRELIM_OR_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING )
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+/*
+ * BR5/OR5: Touch Panel
+ *
+ * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0
+ */
+#define TOUCHPNL_BASE		0x20000000
+#define TOUCHPNL_OR_AM		0xFFFF8000
+#define TOUCHPNL_TIMING		OR_SCY_0_CLK
+
+#define CONFIG_SYS_OR5_PRELIM	(TOUCHPNL_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
+			 TOUCHPNL_TIMING )
+#define CONFIG_SYS_BR5_PRELIM	((TOUCHPNL_BASE & BR_BA_MSK) | BR_PS_32 | BR_V )
+
+#define	CONFIG_SYS_MEMORY_75
+#undef	CONFIG_SYS_MEMORY_7E
+#undef	CONFIG_SYS_MEMORY_8E
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CONFIG_SYS_MPTPR	0x200
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+#define CONFIG_SYS_MAMR_8COL	0x80802114
+#define CONFIG_SYS_MAMR_9COL	0x80904114
+
+/*
+ * MAR setting for SDRAM
+ */
+#define CONFIG_SYS_MAR		0x00000088
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/lwmon5.h b/qemu/roms/u-boot/include/configs/lwmon5.h
new file mode 100644
index 000000000..07ddfc401
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/lwmon5.h
@@ -0,0 +1,699 @@
+/*
+ * (C) Copyright 2007-2013
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * lwmon5.h - configuration for lwmon5 board
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Liebherr extra version info
+ */
+#define CONFIG_IDENT_STRING	" - v2.0"
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_LWMON5		1		/* Board is lwmon5	*/
+#define CONFIG_440EPX		1		/* Specific PPC440EPx	*/
+#define CONFIG_440		1		/* ... PPC440 family	*/
+
+#ifdef CONFIG_LCD4_LWMON5
+#define	CONFIG_SYS_TEXT_BASE	0x01000000 /* SPL U-Boot TEXT_BASE */
+#define CONFIG_HOSTNAME		lcd4_lwmon5
+#else
+#define CONFIG_SYS_TEXT_BASE	0xFFF80000
+#define CONFIG_HOSTNAME		lwmon5
+#endif
+
+#define CONFIG_SYS_CLK_FREQ	33300000	/* external freq to pll	*/
+
+#define CONFIG_4xx_DCACHE		/* enable cache in SDRAM	*/
+
+#define CONFIG_BOARD_EARLY_INIT_F	/* Call board_early_init_f	*/
+#define CONFIG_BOARD_EARLY_INIT_R	/* Call board_early_init_r	*/
+#define CONFIG_BOARD_POSTCLK_INIT	/* Call board_postclk_init	*/
+#define CONFIG_MISC_INIT_R		/* Call misc_init_r		*/
+#define CONFIG_BOARD_RESET		/* Call board_reset		*/
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE	/* Start of U-Boot	*/
+#define CONFIG_SYS_MONITOR_LEN		0x80000
+#define CONFIG_SYS_MALLOC_LEN		(1 << 20)	/* Reserved for malloc	*/
+
+#define CONFIG_SYS_BOOT_BASE_ADDR	0xf0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
+#define CONFIG_SYS_FLASH_BASE		0xf8000000	/* start of FLASH	*/
+#define CONFIG_SYS_LIME_BASE_0		0xc0000000
+#define CONFIG_SYS_LIME_BASE_1		0xc1000000
+#define CONFIG_SYS_LIME_BASE_2		0xc2000000
+#define CONFIG_SYS_LIME_BASE_3		0xc3000000
+#define CONFIG_SYS_FPGA_BASE_0		0xc4000000
+#define CONFIG_SYS_FPGA_BASE_1		0xc4200000
+#define CONFIG_SYS_OCM_BASE		0xe0010000      /* ocm			*/
+#define CONFIG_SYS_PCI_BASE		0xe0000000      /* Internal PCI regs	*/
+#define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped pci memory	*/
+#define CONFIG_SYS_PCI_MEMBASE1		(CONFIG_SYS_PCI_MEMBASE  + 0x10000000)
+#define CONFIG_SYS_PCI_MEMBASE2		(CONFIG_SYS_PCI_MEMBASE1 + 0x10000000)
+#define CONFIG_SYS_PCI_MEMBASE3		(CONFIG_SYS_PCI_MEMBASE2 + 0x10000000)
+
+#ifndef CONFIG_LCD4_LWMON5
+#define CONFIG_SYS_USB2D0_BASE		0xe0000100
+#define CONFIG_SYS_USB_DEVICE		0xe0000000
+#define CONFIG_SYS_USB_HOST		0xe0000400
+#endif
+
+/*
+ * Initial RAM & stack pointer
+ *
+ * On LWMON5 we use D-cache as init-ram and stack pointer. We also move
+ * the POST_WORD from OCM to a 440EPx register that preserves it's
+ * content during reset (GPT0_COMP6). This way we reserve the OCM (16k)
+ * for logbuffer only. (GPT0_COMP1-COMP5 are reserved for logbuffer header.)
+ */
+#ifndef CONFIG_LCD4_LWMON5
+#define CONFIG_SYS_INIT_RAM_DCACHE	1		/* d-cache as init ram	*/
+#define CONFIG_SYS_INIT_RAM_ADDR	0x70000000		/* DCache       */
+#define CONFIG_SYS_INIT_RAM_SIZE		(4 << 10)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+#else
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_BASE
+#define CONFIG_SYS_INIT_RAM_SIZE	(4 << 10)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
+#endif
+/* unused GPT0 COMP reg	*/
+#define CONFIG_SYS_POST_WORD_ADDR	(CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
+#define CONFIG_SYS_OCM_SIZE		(16 << 10)
+/* 440EPx errata CHIP 11: don't use last 4kbytes */
+#define CONFIG_SYS_MEM_TOP_HIDE		(4 << 10)
+
+/* Additional registers for watchdog timer post test */
+#define CONFIG_SYS_WATCHDOG_TIME_ADDR	(CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK2)
+#define CONFIG_SYS_WATCHDOG_FLAGS_ADDR	(CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK1)
+#define CONFIG_SYS_DSPIC_TEST_ADDR	CONFIG_SYS_WATCHDOG_FLAGS_ADDR
+#define CONFIG_SYS_OCM_STATUS_ADDR	CONFIG_SYS_WATCHDOG_FLAGS_ADDR
+#define CONFIG_SYS_WATCHDOG_MAGIC	0x12480000
+#define CONFIG_SYS_WATCHDOG_MAGIC_MASK	0xFFFF0000
+#define CONFIG_SYS_DSPIC_TEST_MASK	0x00000001
+#define CONFIG_SYS_OCM_STATUS_OK	0x00009A00
+#define CONFIG_SYS_OCM_STATUS_FAIL	0x0000A300
+#define CONFIG_SYS_OCM_STATUS_MASK	0x0000FF00
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX	2	/* Use UART1			*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+#undef CONFIG_SYS_EXT_SERIAL_CLOCK		/* no external clock provided	*/
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_SYS_BAUDRATE_TABLE						\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH		/* use FLASH for environment vars	*/
+
+/*
+ * FLASH related
+ */
+#define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible	*/
+#define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/
+
+#define CONFIG_SYS_FLASH0		0xFC000000
+#define CONFIG_SYS_FLASH1		0xF8000000
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
+
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 	/* use buffered writes (20x faster)	*/
+#define CONFIG_SYS_FLASH_PROTECTION		/* use hardware flash protection	*/
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_QUIET_TEST		/* don't warn upon unknown flash	*/
+
+#define CONFIG_ENV_SECT_SIZE	0x40000	/* size of one complete sector		*/
+#define CONFIG_ENV_ADDR		((-CONFIG_SYS_MONITOR_LEN) - CONFIG_ENV_SECT_SIZE)
+#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+/*
+ * DDR SDRAM
+ */
+#define CONFIG_SYS_MBYTES_SDRAM		256
+#define CONFIG_SYS_DDR_CACHED_ADDR	0x40000000	/* setup 2nd TLB cached here	*/
+#define CONFIG_DDR_DATA_EYE			/* use DDR2 optimization	*/
+#ifndef CONFIG_LCD4_LWMON5
+#define CONFIG_DDR_ECC				/* enable ECC			*/
+#endif
+
+#ifndef CONFIG_LCD4_LWMON5
+/* POST support */
+#define CONFIG_POST		(CONFIG_SYS_POST_CACHE		| \
+				 CONFIG_SYS_POST_CPU		| \
+				 CONFIG_SYS_POST_ECC		| \
+				 CONFIG_SYS_POST_ETHER		| \
+				 CONFIG_SYS_POST_FPU		| \
+				 CONFIG_SYS_POST_I2C		| \
+				 CONFIG_SYS_POST_MEMORY		| \
+				 CONFIG_SYS_POST_OCM		| \
+				 CONFIG_SYS_POST_RTC		| \
+				 CONFIG_SYS_POST_SPR		| \
+				 CONFIG_SYS_POST_UART		| \
+				 CONFIG_SYS_POST_SYSMON		| \
+				 CONFIG_SYS_POST_WATCHDOG	| \
+				 CONFIG_SYS_POST_DSP		| \
+				 CONFIG_SYS_POST_BSPEC1		| \
+				 CONFIG_SYS_POST_BSPEC2		| \
+				 CONFIG_SYS_POST_BSPEC3		| \
+				 CONFIG_SYS_POST_BSPEC4		| \
+				 CONFIG_SYS_POST_BSPEC5)
+
+/* Define here the base-addresses of the UARTs to test in POST */
+#define CONFIG_SYS_POST_UART_TABLE	{ CONFIG_SYS_NS16550_COM1, \
+			CONFIG_SYS_NS16550_COM2 }
+
+#define CONFIG_POST_UART  {				\
+	"UART test",					\
+	"uart",						\
+	"This test verifies the UART operation.",	\
+	POST_RAM | POST_SLOWTEST | POST_ALWAYS | POST_MANUAL,	\
+	&uart_post_test,				\
+	NULL,						\
+	NULL,						\
+	CONFIG_SYS_POST_UART				\
+	}
+
+#define CONFIG_POST_WATCHDOG  {				\
+	"Watchdog timer test",				\
+	"watchdog",					\
+	"This test checks the watchdog timer.",		\
+	POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT, \
+	&lwmon5_watchdog_post_test,			\
+	NULL,						\
+	NULL,						\
+	CONFIG_SYS_POST_WATCHDOG			\
+	}
+
+#define CONFIG_POST_BSPEC1    {				\
+	"dsPIC init test",				\
+	"dspic_init",					\
+	"This test returns result of dsPIC READY test run earlier.",	\
+	POST_RAM | POST_ALWAYS,				\
+	&dspic_init_post_test,				\
+	NULL,						\
+	NULL,						\
+	CONFIG_SYS_POST_BSPEC1				\
+	}
+
+#define CONFIG_POST_BSPEC2    {				\
+	"dsPIC test",					\
+	"dspic",					\
+	"This test gets result of dsPIC POST and dsPIC version.",	\
+	POST_RAM | POST_ALWAYS,				\
+	&dspic_post_test,				\
+	NULL,						\
+	NULL,						\
+	CONFIG_SYS_POST_BSPEC2				\
+	}
+
+#define CONFIG_POST_BSPEC3    {				\
+	"FPGA test",					\
+	"fpga",						\
+	"This test checks FPGA registers and memory.",	\
+	POST_RAM | POST_ALWAYS | POST_MANUAL,		\
+	&fpga_post_test,				\
+	NULL,						\
+	NULL,						\
+	CONFIG_SYS_POST_BSPEC3				\
+	}
+
+#define CONFIG_POST_BSPEC4    {				\
+	"GDC test",					\
+	"gdc",						\
+	"This test checks GDC registers and memory.",	\
+	POST_RAM | POST_ALWAYS | POST_MANUAL,\
+	&gdc_post_test,					\
+	NULL,						\
+	NULL,						\
+	CONFIG_SYS_POST_BSPEC4				\
+	}
+
+#define CONFIG_POST_BSPEC5    {				\
+	"SYSMON1 test",					\
+	"sysmon1",					\
+	"This test checks GPIO_62_EPX pin indicating power failure.",	\
+	POST_RAM | POST_MANUAL | POST_NORMAL | POST_SLOWTEST,	\
+	&sysmon1_post_test,				\
+	NULL,						\
+	NULL,						\
+	CONFIG_SYS_POST_BSPEC5				\
+	}
+
+#define CONFIG_SYS_POST_CACHE_ADDR	0x7fff0000 /* free virtual address	*/
+#define CONFIG_LOGBUFFER
+/* Reserve GPT0_COMP1-COMP5 for logbuffer header */
+#define CONFIG_ALT_LH_ADDR	(CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP1)
+#define CONFIG_ALT_LB_ADDR	(CONFIG_SYS_OCM_BASE)
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
+#endif
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		100000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
+
+#define CONFIG_SYS_I2C_RTC_ADDR	0x51	/* RTC				*/
+#define CONFIG_SYS_I2C_EEPROM_CPU_ADDR	0x52	/* EEPROM          (CPU Modul)	*/
+#define CONFIG_SYS_I2C_EEPROM_MB_ADDR	0x53	/* EEPROM AT24C128 (MainBoard)	*/
+#define CONFIG_SYS_I2C_DSPIC_ADDR	0x54	/* dsPIC   			*/
+#define CONFIG_SYS_I2C_DSPIC_2_ADDR	0x55	/* dsPIC			*/
+#define CONFIG_SYS_I2C_DSPIC_KEYB_ADDR	0x56	/* dsPIC			*/
+#define CONFIG_SYS_I2C_DSPIC_IO_ADDR	0x57	/* dsPIC			*/
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2	/* Bytes of address		*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6	/* The Atmel AT24C128 has	*/
+					/* 64 byte page write mode using*/
+					/* last 6 bits of the address	*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
+
+#define CONFIG_RTC_PCF8563			/* enable Philips PCF8563 RTC	*/
+#define CONFIG_SYS_I2C_RTC_ADDR		0x51	/* Philips PCF8563 RTC address	*/
+#define CONFIG_SYS_I2C_KEYBD_ADDR	0x56	/* PIC LWE keyboard		*/
+#define CONFIG_SYS_I2C_DSPIC_IO_ADDR	0x57	/* PIC I/O addr               */
+
+#define CONFIG_SYS_POST_I2C_ADDRS	{CONFIG_SYS_I2C_RTC_ADDR,	\
+					 CONFIG_SYS_I2C_EEPROM_CPU_ADDR,\
+					 CONFIG_SYS_I2C_EEPROM_MB_ADDR,	\
+					 CONFIG_SYS_I2C_DSPIC_ADDR,	\
+					 CONFIG_SYS_I2C_DSPIC_2_ADDR,	\
+					 CONFIG_SYS_I2C_DSPIC_KEYB_ADDR,\
+					 CONFIG_SYS_I2C_DSPIC_IO_ADDR }
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+/* Update size in "reg" property of NOR FLASH device tree nodes */
+#define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
+
+#define CONFIG_FIT			/* enable FIT image support	*/
+
+#define	CONFIG_POST_KEY_MAGIC	"3C+3E"	/* press F3 + F5 keys to force POST */
+
+#define	CONFIG_PREBOOT		"setenv bootdelay 15"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"hostname=lwmon5\0"						\
+	"netdev=eth0\0"							\
+	"unlock=yes\0"							\
+	"logversion=2\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\
+	"addmisc=setenv bootargs ${bootargs} rtc-pcf8563.probe=0,0x51\0"\
+	"flash_nfs=run nfsargs addip addtty addmisc;"			\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip addtty addmisc;"			\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};"				\
+		"run nfsargs addip addtty addmisc;bootm\0"		\
+	"rootpath=/opt/eldk/ppc_4xxFP\0"				\
+	"bootfile=/tftpboot/lwmon5/uImage\0"				\
+	"kernel_addr=FC000000\0"					\
+	"ramdisk_addr=FC180000\0"					\
+	"load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0"		\
+	"update=protect off FFF80000 FFFFFFFF;era FFF80000 FFFFFFFF;"	\
+		"cp.b 200000 FFF80000 80000\0"			        \
+	"upd=run load update\0"						\
+	"lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;"	\
+		"autoscr 200000\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_PPC4xx_EMAC
+#define	CONFIG_IBM_EMAC4_V4	1
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		3	/* PHY address, See schematics	*/
+
+#define CONFIG_PHY_RESET        1	/* reset phy upon startup         */
+#define CONFIG_PHY_RESET_DELAY	300
+
+#define CONFIG_HAS_ETH0
+#define CONFIG_SYS_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
+#define CONFIG_PHY1_ADDR	1
+
+/* Video console */
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_MB862xx
+#define CONFIG_VIDEO_MB862xx_ACCEL
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_CONSOLE_EXTRA_INFO
+#define VIDEO_FB_16BPP_PIXEL_SWAP
+#define VIDEO_FB_16BPP_WORD_SWAP
+
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_SPLASH_SCREEN
+
+#ifndef CONFIG_LCD4_LWMON5
+/*
+ * USB/EHCI
+ */
+#define CONFIG_USB_EHCI			/* Enable EHCI USB support	*/
+#define CONFIG_USB_EHCI_PPC4XX		/* on PPC4xx platform		*/
+#define CONFIG_SYS_PPC4XX_USB_ADDR	0xe0000300
+#define CONFIG_EHCI_MMIO_BIG_ENDIAN
+#define CONFIG_EHCI_DESC_BIG_ENDIAN
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */
+#define CONFIG_USB_STORAGE
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+#endif
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SDRAM
+
+#ifdef CONFIG_VIDEO
+#define CONFIG_CMD_BMP
+#endif
+
+#ifndef CONFIG_LCD4_LWMON5
+#ifdef CONFIG_440EPX
+#define CONFIG_CMD_USB
+#endif
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SUPPORT_VFAT
+
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+
+#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	        1024	/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	        256	/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	        16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	        CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000 /* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000  /* default load address	*/
+#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_LOOPW            1       /* enable loopw command         */
+#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	/* don't print console @ startup*/
+
+#ifndef CONFIG_LCD4_LWMON5
+#ifndef DEBUG
+#define CONFIG_HW_WATCHDOG	1	/* Use external HW-Watchdog	*/
+#endif
+#define CONFIG_WD_PERIOD	40000	/* in usec */
+#define CONFIG_WD_MAX_RATE	66600	/* in ticks */
+#endif
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the 40x Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(16 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTM_LEN		(16 << 20) /* Increase max gunzip size */
+
+/*
+ * External Bus Controller (EBC) Setup
+ */
+#define CONFIG_SYS_FLASH		CONFIG_SYS_FLASH_BASE
+
+/* Memory Bank 0 (NOR-FLASH) initialization					*/
+#define CONFIG_SYS_EBC_PB0AP		0x03000280
+#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_FLASH | 0xfc000)
+
+/* Memory Bank 1 (Lime) initialization						*/
+#define CONFIG_SYS_EBC_PB1AP		0x01004380
+#define CONFIG_SYS_EBC_PB1CR		(CONFIG_SYS_LIME_BASE_0 | 0xbc000)
+
+/* Memory Bank 2 (FPGA) initialization						*/
+#define CONFIG_SYS_EBC_PB2AP		0x01004400
+#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_FPGA_BASE_0 | 0x1c000)
+
+/* Memory Bank 3 (FPGA2) initialization						*/
+#define CONFIG_SYS_EBC_PB3AP		0x01004400
+#define CONFIG_SYS_EBC_PB3CR		(CONFIG_SYS_FPGA_BASE_1 | 0x1c000)
+
+#define CONFIG_SYS_EBC_CFG		0xb8400000
+
+/*
+ * Graphics (Fujitsu Lime)
+ */
+/* SDRAM Clock frequency adjustment register */
+#define CONFIG_SYS_LIME_SDRAM_CLOCK	0xC1FC0038
+#if 1 /* 133MHz is not tested enough, use 100MHz for now */
+/* Lime Clock frequency is to set 100MHz */
+#define CONFIG_SYS_LIME_CLOCK_100MHZ	0x00000
+#else
+/* Lime Clock frequency for 133MHz */
+#define CONFIG_SYS_LIME_CLOCK_133MHZ	0x10000
+#endif
+
+/* SDRAM Parameter register */
+#define CONFIG_SYS_LIME_MMR		0xC1FCFFFC
+/*
+ * SDRAM parameter value; was 0x414FB7F2, caused several vertical bars
+ * and pixel flare on display when 133MHz was configured. According to
+ * SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed
+ * Grade
+ */
+#ifdef CONFIG_SYS_LIME_CLOCK_133MHZ
+#define CONFIG_SYS_MB862xx_MMR	0x414FB7F3
+#define CONFIG_SYS_MB862xx_CCF	CONFIG_SYS_LIME_CLOCK_133MHZ
+#else
+#define CONFIG_SYS_MB862xx_MMR	0x414FB7F2
+#define CONFIG_SYS_MB862xx_CCF	CONFIG_SYS_LIME_CLOCK_100MHZ
+#endif
+
+/*
+ * GPIO Setup
+ */
+#define CONFIG_SYS_GPIO_PHY1_RST	12
+#define CONFIG_SYS_GPIO_FLASH_WP	14
+#define CONFIG_SYS_GPIO_PHY0_RST	22
+#define CONFIG_SYS_GPIO_PERM_VOLT_FEED	49
+#define CONFIG_SYS_GPIO_DSPIC_READY	51
+#define CONFIG_SYS_GPIO_CAN_ENABLE	53
+#define CONFIG_SYS_GPIO_LSB_ENABLE	54
+#define CONFIG_SYS_GPIO_EEPROM_EXT_WP	55
+#define CONFIG_SYS_GPIO_HIGHSIDE	56
+#define CONFIG_SYS_GPIO_EEPROM_INT_WP	57
+#define CONFIG_SYS_GPIO_BOARD_RESET	58
+#define CONFIG_SYS_GPIO_LIME_S		59
+#define CONFIG_SYS_GPIO_LIME_RST	60
+#define CONFIG_SYS_GPIO_SYSMON_STATUS	62
+#define CONFIG_SYS_GPIO_WATCHDOG	63
+
+/* On LCD4, GPIO49 has to be configured to 0 instead of 1 */
+#ifdef CONFIG_LCD4_LWMON5
+#define GPIO49_VAL	0
+#else
+#define GPIO49_VAL	1
+#endif
+
+/*
+ * PPC440 GPIO Configuration
+ */
+#define CONFIG_SYS_4xx_GPIO_TABLE { /*	  Out		  GPIO	Alternate1	Alternate2	Alternate3 */ \
+{											\
+/* GPIO Core 0 */									\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0	EBC_ADDR(7)	DMA_REQ(2)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1	EBC_ADDR(6)	DMA_ACK(2)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2	EBC_ADDR(5)	DMA_EOT/TC(2)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3	EBC_ADDR(4)	DMA_REQ(3)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4	EBC_ADDR(3)	DMA_ACK(3)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5	EBC_ADDR(2)	DMA_EOT/TC(3)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6	EBC_CS_N(1)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7	EBC_CS_N(2)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8	EBC_CS_N(3)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9	EBC_CS_N(4)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5)			*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12				*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13				*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14				*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO15				*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMCTxD(7)			*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0			*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO22				*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0				*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 GMCTxD(2)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 GMCTxD(3)			*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ	USB2D_RXERROR	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28		USB2D_TXVALID	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA	USB2D_PAD_SUSPNDM */	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK	USB2D_XCVRSELECT*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ	USB2D_TERMSELECT*/	\
+},											\
+{											\
+/* GPIO Core 1 */									\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO32 USB2D_OPMODE0	EBC_DATA(2)	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO33 USB2D_OPMODE1	EBC_DATA(3)	*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N	UART1_DSR_CTS_N	UART2_SOUT*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0)	UART3_SIN*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N	EBC_DATA(1)	UART3_SOUT*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO38 UART0_DTR_N	UART1_SOUT	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N	UART1_SIN	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0)			*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1)			*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2)			*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3)			*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4)	DMA_ACK(1)	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6)	DMA_EOT/TC(1)	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7)	DMA_REQ(0)	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8)	DMA_ACK(0)	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9)	DMA_EOT/TC(0)	*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO49_VAL}, /* GPIO49  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO57  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit	*/	\
+}											\
+}
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * SPL related defines
+ */
+#ifdef CONFIG_LCD4_LWMON5
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_NOR_SUPPORT
+#define CONFIG_SPL_TEXT_BASE		0xffff0000 /* last 64 KiB for SPL */
+#define CONFIG_SYS_SPL_MAX_LEN		(64 << 10)
+#define CONFIG_UBOOT_PAD_TO		458752	/* decimal for 'dd' */
+#define	CONFIG_SPL_START_S_PATH	"arch/powerpc/cpu/ppc4xx"
+#define CONFIG_SPL_LDSCRIPT	"arch/powerpc/cpu/ppc4xx/u-boot-spl.lds"
+#define CONFIG_SPL_LIBCOMMON_SUPPORT	/* image.c */
+#define CONFIG_SPL_LIBGENERIC_SUPPORT	/* string.c */
+#define CONFIG_SPL_SERIAL_SUPPORT
+
+/* Place BSS for SPL near end of SDRAM */
+#define CONFIG_SPL_BSS_START_ADDR	((256 - 1) << 20)
+#define CONFIG_SPL_BSS_MAX_SIZE		(64 << 10)
+
+#define CONFIG_SPL_OS_BOOT
+/* Place patched DT blob (fdt) at this address */
+#define CONFIG_SYS_SPL_ARGS_ADDR	0x01800000
+
+#define CONFIG_SPL_TARGET		"u-boot-img-spl-at-end.bin"
+
+/* Settings for real U-Boot to be loaded from NOR flash */
+#define CONFIG_SYS_UBOOT_BASE		(-CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_UBOOT_START		0x01002100
+
+#define CONFIG_SYS_OS_BASE		0xf8000000
+#define CONFIG_SYS_FDT_BASE		0xf87c0000
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/m28evk.h b/qemu/roms/u-boot/include/configs/m28evk.h
new file mode 100644
index 000000000..bb1fa44d8
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/m28evk.h
@@ -0,0 +1,204 @@
+/*
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __CONFIGS_M28EVK_H__
+#define __CONFIGS_M28EVK_H__
+
+
+/* System configurations */
+#define CONFIG_MX28				/* i.MX28 SoC */
+#define MACH_TYPE_M28EVK	3613
+#define CONFIG_MACH_TYPE	MACH_TYPE_M28EVK
+
+/* U-Boot Commands */
+#define CONFIG_SYS_NO_FLASH
+#include <config_cmd_default.h>
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_GPIO
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NAND_TRIMFFS
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_USB
+#define	CONFIG_VIDEO
+
+#define CONFIG_REGEX			/* Enable regular expression support */
+
+/* Memory configuration */
+#define CONFIG_NR_DRAM_BANKS		1		/* 1 bank of DRAM */
+#define PHYS_SDRAM_1			0x40000000	/* Base address */
+#define PHYS_SDRAM_1_SIZE		0x20000000	/* Max 512 MB RAM */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+
+/* Environment */
+#define CONFIG_ENV_SIZE			(16 * 1024)
+#define CONFIG_ENV_IS_IN_NAND
+
+/* Environment is in NAND */
+#if defined(CONFIG_CMD_NAND) && defined(CONFIG_ENV_IS_IN_NAND)
+#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
+#define CONFIG_ENV_SECT_SIZE		(128 * 1024)
+#define CONFIG_ENV_RANGE		(512 * 1024)
+#define CONFIG_ENV_OFFSET		0x300000
+#define CONFIG_ENV_OFFSET_REDUND	\
+		(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
+
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT			"nand0=gpmi-nand"
+#define MTDPARTS_DEFAULT			\
+	"mtdparts=gpmi-nand:"			\
+		"3m(bootloader)ro,"		\
+		"512k(environment),"		\
+		"512k(redundant-environment),"	\
+		"4m(kernel),"			\
+		"128k(fdt),"			\
+		"8m(ramdisk),"			\
+		"-(filesystem)"
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+/* FEC Ethernet on SoC */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#endif
+
+/* EEPROM */
+#ifdef CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+#endif
+
+/* RTC */
+#ifdef CONFIG_CMD_DATE
+/* Use the internal RTC in the MXS chip */
+#define CONFIG_RTC_INTERNAL
+#ifdef CONFIG_RTC_INTERNAL
+#define CONFIG_RTC_MXS
+#else
+#define CONFIG_RTC_M41T62
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR	2000
+#endif
+#endif
+
+/* USB */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_EHCI_MXS_PORT0
+#define CONFIG_EHCI_MXS_PORT1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2
+#define CONFIG_USB_STORAGE
+#endif
+
+/* SPI */
+#ifdef CONFIG_CMD_SPI
+#define CONFIG_DEFAULT_SPI_BUS		2
+#define CONFIG_DEFAULT_SPI_CS		0
+#define CONFIG_DEFAULT_SPI_MODE		SPI_MODE_0
+
+/* SPI FLASH */
+#ifdef CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SF_DEFAULT_BUS		2
+#define CONFIG_SF_DEFAULT_CS		0
+#define CONFIG_SF_DEFAULT_SPEED		40000000
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
+
+#define CONFIG_ENV_SPI_BUS		2
+#define CONFIG_ENV_SPI_CS		0
+#define CONFIG_ENV_SPI_MAX_HZ		40000000
+#define CONFIG_ENV_SPI_MODE		SPI_MODE_0
+#endif
+
+#endif
+
+/* LCD */
+#ifdef CONFIG_VIDEO
+#define	CONFIG_VIDEO_LOGO
+#define	CONFIG_SPLASH_SCREEN
+#define	CONFIG_CMD_BMP
+#define	CONFIG_BMP_16BPP
+#define	CONFIG_VIDEO_BMP_RLE8
+#define	CONFIG_VIDEO_BMP_GZIP
+#define	CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(512 << 10)
+#endif
+
+/* Booting Linux */
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_BOOTARGS		"console=ttyAMA0,115200n8 "
+#define CONFIG_BOOTCOMMAND	"run bootcmd_net"
+#define CONFIG_LOADADDR		0x42000000
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+
+/* Extra Environment */
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"update_nand_full_filename=u-boot.nand\0"			\
+	"update_nand_firmware_filename=u-boot.sb\0"			\
+	"update_sd_firmware_filename=u-boot.sd\0"			\
+	"update_nand_firmware_maxsz=0x100000\0"				\
+	"update_nand_stride=0x40\0"	/* MX28 datasheet ch. 12.12 */	\
+	"update_nand_count=0x4\0"	/* MX28 datasheet ch. 12.12 */	\
+	"update_nand_get_fcb_size="	/* Get size of FCB blocks */	\
+		"nand device 0 ; "					\
+		"nand info ; "						\
+		"setexpr fcb_sz ${update_nand_stride} * ${update_nand_count};" \
+		"setexpr update_nand_fcb ${fcb_sz} * ${nand_writesize}\0" \
+	"update_nand_full="		/* Update FCB, DBBT and FW */	\
+		"if tftp ${update_nand_full_filename} ; then "		\
+		"run update_nand_get_fcb_size ; "			\
+		"nand scrub -y 0x0 ${filesize} ; "			\
+		"nand write.raw ${loadaddr} 0x0 ${fcb_sz} ; "	\
+		"setexpr update_off ${loadaddr} + ${update_nand_fcb} ; " \
+		"setexpr update_sz ${filesize} - ${update_nand_fcb} ; " \
+		"nand write ${update_off} ${update_nand_fcb} ${update_sz} ; " \
+		"fi\0"							\
+	"update_nand_firmware="		/* Update only firmware */	\
+		"if tftp ${update_nand_firmware_filename} ; then "	\
+		"run update_nand_get_fcb_size ; "			\
+		"setexpr fcb_sz ${update_nand_fcb} * 2 ; " /* FCB + DBBT */ \
+		"setexpr fw_sz ${update_nand_firmware_maxsz} * 2 ; "	\
+		"setexpr fw_off ${fcb_sz} + ${update_nand_firmware_maxsz};" \
+		"nand erase ${fcb_sz} ${fw_sz} ; "			\
+		"nand write ${loadaddr} ${fcb_sz} ${filesize} ; "	\
+		"nand write ${loadaddr} ${fw_off} ${filesize} ; "	\
+		"fi\0"							\
+	"update_sd_firmware="		/* Update the SD firmware partition */ \
+		"if mmc rescan ; then "					\
+		"if tftp ${update_sd_firmware_filename} ; then "	\
+		"setexpr fw_sz ${filesize} / 0x200 ; "	/* SD block size */ \
+		"setexpr fw_sz ${fw_sz} + 1 ; "				\
+		"mmc write ${loadaddr} 0x800 ${fw_sz} ; "		\
+		"fi ; "							\
+		"fi\0"
+
+/* The rest of the configuration is shared */
+#include <configs/mxs.h>
+
+#endif /* __CONFIGS_M28EVK_H__ */
diff --git a/qemu/roms/u-boot/include/configs/m53evk.h b/qemu/roms/u-boot/include/configs/m53evk.h
new file mode 100644
index 000000000..f40147025
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/m53evk.h
@@ -0,0 +1,259 @@
+/*
+ * DENX M53 configuration
+ * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __M53EVK_CONFIG_H__
+#define __M53EVK_CONFIG_H__
+
+#define CONFIG_MX53
+#define CONFIG_MXC_GPIO
+
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_REVISION_TAG
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * U-Boot Commands
+ */
+#include <config_cmd_default.h>
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SATA
+#define CONFIG_CMD_USB
+#define CONFIG_VIDEO
+
+#define CONFIG_REGEX			/* Enable regular expression support */
+
+/*
+ * Memory configurations
+ */
+#define CONFIG_NR_DRAM_BANKS		2
+#define PHYS_SDRAM_1			CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE		(gd->bd->bi_dram[0].size)
+#define PHYS_SDRAM_2			CSD1_BASE_ADDR
+#define PHYS_SDRAM_2_SIZE		(gd->bd->bi_dram[1].size)
+#define PHYS_SDRAM_SIZE			(gd->ram_size)
+#define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
+#define CONFIG_SYS_MEMTEST_START	0x70000000
+#define CONFIG_SYS_MEMTEST_END		0x8ff00000
+
+#define CONFIG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR)
+#define CONFIG_SYS_INIT_RAM_SIZE	(IRAM_SIZE)
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_SYS_TEXT_BASE		0x71000000
+
+/*
+ * U-Boot general configurations
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O buffer size */
+#define CONFIG_SYS_PBSIZE	\
+	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+						/* Print buffer size */
+#define CONFIG_SYS_MAXARGS	32		/* Max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+						/* Boot argument buffer size */
+#define CONFIG_VERSION_VARIABLE			/* U-BOOT version */
+#define CONFIG_AUTO_COMPLETE			/* Command auto complete */
+#define CONFIG_CMDLINE_EDITING			/* Command history etc */
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Serial Driver
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART2_BASE
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+
+/*
+ * MMC Driver
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_ESDHC_NUM	1
+#endif
+
+/*
+ * NAND
+ */
+#define CONFIG_ENV_SIZE			(16 * 1024)
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		NFC_BASE_ADDR_AXI
+#define CONFIG_NAND_MXC
+#define CONFIG_MXC_NAND_REGS_BASE	NFC_BASE_ADDR_AXI
+#define CONFIG_MXC_NAND_IP_REGS_BASE	NFC_BASE_ADDR
+#define CONFIG_SYS_NAND_LARGEPAGE
+#define CONFIG_MXC_NAND_HWECC
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+
+/* Environment is in NAND */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
+#define CONFIG_ENV_SECT_SIZE		(128 * 1024)
+#define CONFIG_ENV_RANGE		(512 * 1024)
+#define CONFIG_ENV_OFFSET		0x100000
+#define CONFIG_ENV_OFFSET_REDUND	\
+		(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
+
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT			"nand0=mxc_nand"
+#define MTDPARTS_DEFAULT			\
+	"mtdparts=mxc_nand:"			\
+		"1m(bootloader)ro,"		\
+		"512k(environment),"		\
+		"512k(redundant-environment),"	\
+		"4m(kernel),"			\
+		"128k(fdt),"			\
+		"8m(ramdisk),"			\
+		"-(filesystem)"
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+/*
+ * Ethernet on SOC (FEC)
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE			FEC_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR		0x0
+#define CONFIG_MII
+#define CONFIG_DISCOVER_PHY
+#define CONFIG_FEC_XCV_TYPE		RMII
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#endif
+
+/*
+ * I2C
+ */
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_SPD_BUS_NUM		1 /* I2C2 */
+#endif
+
+/*
+ * RTC
+ */
+#ifdef CONFIG_CMD_DATE
+#define CONFIG_RTC_M41T62
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR	2000
+#endif
+
+/*
+ * USB
+ */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX5
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_MCS7830
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_MXC_USB_PORT		1
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS		0
+#endif
+
+/*
+ * SATA
+ */
+#ifdef CONFIG_CMD_SATA
+#define CONFIG_DWC_AHSATA
+#define CONFIG_SYS_SATA_MAX_DEVICE	1
+#define CONFIG_DWC_AHSATA_PORT_ID	0
+#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_BASE_ADDR
+#define CONFIG_LBA48
+#define CONFIG_LIBATA
+#endif
+
+/*
+ * LCD
+ */
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO_IPUV3
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_IPUV3_CLK	200000000
+#endif
+
+/*
+ * Boot Linux
+ */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTFILE		"m53evk/uImage"
+#define CONFIG_BOOTARGS		"console=ttymxc1,115200"
+#define CONFIG_LOADADDR		0x70800000
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+#define CONFIG_OF_LIBFDT
+
+/*
+ * NAND SPL
+ */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TARGET		"u-boot-with-nand-spl.imx"
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_TEXT_BASE		0x70008000
+#define CONFIG_SPL_PAD_TO		0x8000
+#define CONFIG_SPL_STACK		0x70004000
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	CONFIG_SPL_PAD_TO
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_SIZE		(256 * 1024 * 1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
+
+#endif	/* __M53EVK_CONFIG_H__ */
diff --git a/qemu/roms/u-boot/include/configs/magnesium.h b/qemu/roms/u-boot/include/configs/magnesium.h
new file mode 100644
index 000000000..3364bde71
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/magnesium.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2010 Heiko Schocher <hs@denx.de>
+ *
+ * based on:
+ * Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* include common defines/options for all imx27lite related boards */
+#include "imx27lite-common.h"
+
+/*
+ * SoC Configuration
+ */
+#define CONFIG_MAGNESIUM
+#define CONFIG_HOSTNAME		magnesium
+#define CONFIG_BOARDNAME	"Projectiondesign magnesium\n"
+
+/*
+ * Flash & Environment
+ */
+#define CONFIG_SYS_FLASH_SECT_SZ	0x8000	/* 64KB sect size */
+#define CONFIG_ENV_OFFSET		(PHYS_FLASH_SIZE - 0x40000)
+#define PHYS_FLASH_SIZE			0x800000
+#define CONFIG_ENV_SECT_SIZE		0x20000		/* Env sector Size */
+
+/*
+ * NAND
+ */
+#define CONFIG_SYS_NAND_LARGEPAGE
+
+/*
+ * SD/MMC
+ */
+#define CONFIG_MXC_MCI_REGS_BASE	0x10013000
+
+/*
+ * MTD partitions
+ */
+#define MTDIDS_DEFAULT		"nor0=physmap-flash.0,nand0=mxc_nand.0"
+#define MTDPARTS_DEFAULT			\
+	"mtdparts="				\
+		"physmap-flash.0:"		\
+			"256k(U-Boot),"		\
+			"7680k(user),"		\
+			"128k(env1),"		\
+			"128k(env2);"		\
+		"mxc_nand.0:"			\
+			"128k(IPL-SPL),"	\
+			"4m(kernel),"		\
+			"22m(rootfs),"		\
+			"-(userfs)"
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/makalu.h b/qemu/roms/u-boot/include/configs/makalu.h
new file mode 100644
index 000000000..fd4c26eb9
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/makalu.h
@@ -0,0 +1,345 @@
+/*
+ * Copyright (c) 2008 Nuovation System Designs, LLC
+ *   Grant Erickson <gerickson@nuovations.com>
+ *
+ * (C) Copyright 2007-2008
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/************************************************************************
+ * makalu.h - configuration for AMCC Makalu (405EX)
+ ***********************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_MAKALU		1		/* Board is Makalu	*/
+#define CONFIG_405EX		1		/* Specifc 405EX support*/
+#define CONFIG_SYS_CLK_FREQ	33330000	/* ext frequency to pll	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFA0000
+
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME	makalu
+#define CONFIG_ADDMISC	"addmisc=setenv bootargs ${bootargs} rtc-x1205.probe=0,0x6f\0"
+#include "amcc-common.h"
+
+#define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_early_init_f */
+#define CONFIG_MISC_INIT_R	1		/* Call misc_init_r	*/
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_FLASH_BASE		0xFC000000
+#define CONFIG_SYS_FPGA_BASE		0xF0000000
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & Stack Pointer Configuration Options
+ *
+ *   There are traditionally three options for the primordial
+ *   (i.e. initial) stack usage on the 405-series:
+ *
+ *      1) On-chip Memory (OCM) (i.e. SRAM)
+ *      2) Data cache
+ *      3) SDRAM
+ *
+ *   For the 405EX(r), there is no OCM, so we are left with (2) or (3)
+ *   the latter of which is less than desireable since it requires
+ *   setting up the SDRAM and ECC in assembly code.
+ *
+ *   To use (2), define 'CONFIG_SYS_INIT_DCACHE_CS' to be an unused chip
+ *   select on the External Bus Controller (EBC) and then select a
+ *   value for 'CONFIG_SYS_INIT_RAM_ADDR' outside of the range of valid,
+ *   physical SDRAM. Otherwise, undefine 'CONFIG_SYS_INIT_DCACHE_CS' and
+ *   select a value for 'CONFIG_SYS_INIT_RAM_ADDR' within the range of valid,
+ *   physical SDRAM to use (3).
+ *-----------------------------------------------------------------------*/
+
+#define CONFIG_SYS_INIT_DCACHE_CS	4
+
+#if defined(CONFIG_SYS_INIT_DCACHE_CS)
+#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_SDRAM_BASE + ( 1 << 30))	/*  1 GiB */
+#else
+#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_SDRAM_BASE + (32 << 20))	/* 32 MiB */
+#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
+
+#define CONFIG_SYS_INIT_RAM_SIZE        (4 << 10)			/*  4 KiB */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * If the data cache is being used for the primordial stack and global
+ * data area, the POST word must be placed somewhere else. The General
+ * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves
+ * its compare and mask register contents across reset, so it is used
+ * for the POST word.
+ */
+
+#if defined(CONFIG_SYS_INIT_DCACHE_CS)
+# define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+# define CONFIG_SYS_POST_WORD_ADDR	(CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
+#else
+# define CONFIG_SYS_INIT_EXTRA_SIZE	16
+# define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_EXTRA_SIZE)
+# define CONFIG_SYS_OCM_DATA_ADDR	CONFIG_SYS_INIT_RAM_ADDR
+#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#undef CONFIG_SYS_EXT_SERIAL_CLOCK			/* no ext. clk		*/
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+#define CONFIG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible	*/
+#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
+
+#define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector	*/
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
+#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+#endif /* CONFIG_ENV_IS_IN_FLASH */
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_MBYTES_SDRAM        (256)		/* 256MB			*/
+
+#define	CONFIG_SYS_SDRAM0_MB0CF_BASE	((  0 << 20) + CONFIG_SYS_SDRAM_BASE)
+#define	CONFIG_SYS_SDRAM0_MB1CF_BASE	((128 << 20) + CONFIG_SYS_SDRAM_BASE)
+
+/* DDR1/2 SDRAM Device Control Register Data Values */
+#define CONFIG_SYS_SDRAM0_MB0CF	((CONFIG_SYS_SDRAM0_MB0CF_BASE >> 3)	| \
+				 SDRAM_RXBAS_SDSZ_128MB 	| \
+				 SDRAM_RXBAS_SDAM_MODE2 	| \
+				 SDRAM_RXBAS_SDBE_ENABLE)
+#define CONFIG_SYS_SDRAM0_MB1CF	((CONFIG_SYS_SDRAM0_MB1CF_BASE >> 3)	| \
+				 SDRAM_RXBAS_SDSZ_128MB 	| \
+				 SDRAM_RXBAS_SDAM_MODE2 	| \
+				 SDRAM_RXBAS_SDBE_ENABLE)
+#define CONFIG_SYS_SDRAM0_MB2CF	SDRAM_RXBAS_SDBE_DISABLE
+#define CONFIG_SYS_SDRAM0_MB3CF	SDRAM_RXBAS_SDBE_DISABLE
+#define CONFIG_SYS_SDRAM0_MCOPT1	0x04322000
+#define CONFIG_SYS_SDRAM0_MCOPT2	0x00000000
+#define CONFIG_SYS_SDRAM0_MODT0	0x01800000
+#define CONFIG_SYS_SDRAM0_MODT1	0x00000000
+#define CONFIG_SYS_SDRAM0_CODT		0x0080f837
+#define CONFIG_SYS_SDRAM0_RTR		0x06180000
+#define CONFIG_SYS_SDRAM0_INITPLR0	0xa8380000
+#define CONFIG_SYS_SDRAM0_INITPLR1	0x81900400
+#define CONFIG_SYS_SDRAM0_INITPLR2	0x81020000
+#define CONFIG_SYS_SDRAM0_INITPLR3	0x81030000
+#define CONFIG_SYS_SDRAM0_INITPLR4	0x81010404
+#define CONFIG_SYS_SDRAM0_INITPLR5	0x81000542
+#define CONFIG_SYS_SDRAM0_INITPLR6	0x81900400
+#define CONFIG_SYS_SDRAM0_INITPLR7	0x8D080000
+#define CONFIG_SYS_SDRAM0_INITPLR8	0x8D080000
+#define CONFIG_SYS_SDRAM0_INITPLR9	0x8D080000
+#define CONFIG_SYS_SDRAM0_INITPLR10	0x8D080000
+#define CONFIG_SYS_SDRAM0_INITPLR11	0x81000442
+#define CONFIG_SYS_SDRAM0_INITPLR12	0x81010780
+#define CONFIG_SYS_SDRAM0_INITPLR13	0x81010400
+#define CONFIG_SYS_SDRAM0_INITPLR14	0x00000000
+#define CONFIG_SYS_SDRAM0_INITPLR15	0x00000000
+#define CONFIG_SYS_SDRAM0_RQDC		0x80000038
+#define CONFIG_SYS_SDRAM0_RFDC		0x00000209
+#define CONFIG_SYS_SDRAM0_RDCC		0x40000000
+#define CONFIG_SYS_SDRAM0_DLCR		0x030000a5
+#define CONFIG_SYS_SDRAM0_CLKTR	0x80000000
+#define CONFIG_SYS_SDRAM0_WRDTR	0x00000000
+#define CONFIG_SYS_SDRAM0_SDTR1	0x80201000
+#define CONFIG_SYS_SDRAM0_SDTR2	0x32204232
+#define CONFIG_SYS_SDRAM0_SDTR3	0x080b0d1a
+#define CONFIG_SYS_SDRAM0_MMODE	0x00000442
+#define CONFIG_SYS_SDRAM0_MEMODE	0x00000404
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
+
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	6	/* 24C02 requires 5ms delay */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x52	/* I2C boot EEPROM (24C02BN)	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
+
+/* Standard DTT sensor configuration */
+#define CONFIG_DTT_DS1775	1
+#define CONFIG_DTT_SENSORS	{ 0 }
+#define CONFIG_SYS_I2C_DTT_ADDR	0x48
+
+/* RTC configuration */
+#define CONFIG_RTC_X1205	1
+#define CONFIG_SYS_I2C_RTC_ADDR	0x6f
+
+/*-----------------------------------------------------------------------
+ * Ethernet
+ *----------------------------------------------------------------------*/
+#define CONFIG_M88E1111_PHY	1
+#define CONFIG_IBM_EMAC4_V4	1
+#define CONFIG_EMAC_PHY_MODE	EMAC_PHY_MODE_RGMII_RGMII
+#define CONFIG_PHY_ADDR		6	/* PHY address, See schematics	*/
+
+#define CONFIG_PHY_RESET	1	/* reset phy upon startup	*/
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+
+#define CONFIG_HAS_ETH0		1
+
+#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"   */
+#define CONFIG_PHY1_ADDR	0
+
+/*
+ * Default environment variables
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_AMCC_DEF_ENV						\
+	CONFIG_AMCC_DEF_ENV_POWERPC					\
+	CONFIG_AMCC_DEF_ENV_PPC_OLD					\
+	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
+	"kernel_addr=fc000000\0"					\
+	"fdt_addr=fc1e0000\0"						\
+	"ramdisk_addr=fc200000\0"					\
+	"pciconfighost=1\0"						\
+	"pcie_mode=RP:RP\0"						\
+	""
+
+/*
+ * Commands additional to the ones defined in amcc-common.h
+ */
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_SNTP
+
+/* POST support */
+#define CONFIG_POST		(CONFIG_SYS_POST_CACHE		| \
+				 CONFIG_SYS_POST_CPU		| \
+				 CONFIG_SYS_POST_ETHER		| \
+				 CONFIG_SYS_POST_I2C		| \
+				 CONFIG_SYS_POST_MEMORY	| \
+				 CONFIG_SYS_POST_UART)
+
+/* Define here the base-addresses of the UARTs to test in POST */
+#define CONFIG_SYS_POST_UART_TABLE	{ CONFIG_SYS_NS16550_COM1, \
+			CONFIG_SYS_NS16550_COM2 }
+
+#define CONFIG_LOGBUFFER
+#define CONFIG_SYS_POST_CACHE_ADDR	0x00800000 /* free virtual address	*/
+
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *----------------------------------------------------------------------*/
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_PNP		1	/* do pci plug-and-play		*/
+#define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup	*/
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE
+
+/*-----------------------------------------------------------------------
+ * PCIe stuff
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_PCIE_MEMBASE	0x90000000	/* mapped PCIe memory	*/
+#define CONFIG_SYS_PCIE_MEMSIZE	0x08000000      /* 128 Meg, smallest incr per port */
+
+#define	CONFIG_SYS_PCIE0_CFGBASE	0xa0000000      /* remote access */
+#define	CONFIG_SYS_PCIE0_XCFGBASE	0xb0000000      /* local access */
+#define	CONFIG_SYS_PCIE0_CFGMASK	0xe0000001      /* 512 Meg */
+
+#define	CONFIG_SYS_PCIE1_CFGBASE	0xc0000000      /* remote access */
+#define	CONFIG_SYS_PCIE1_XCFGBASE	0xd0000000      /* local access */
+#define	CONFIG_SYS_PCIE1_CFGMASK	0xe0000001      /* 512 Meg */
+
+#define	CONFIG_SYS_PCIE0_UTLBASE	0xef502000
+#define	CONFIG_SYS_PCIE1_UTLBASE	0xef503000
+
+/* base address of inbound PCIe window */
+#define CONFIG_SYS_PCIE_INBOUND_BASE	0x0000000000000000ULL
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ *----------------------------------------------------------------------*/
+/* Memory Bank 0 (NOR-FLASH) initialization					*/
+#define CONFIG_SYS_EBC_PB0AP		0x08033700
+#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_FLASH_BASE | 0xda000)
+
+/* Memory Bank 2 (CPLD) initialization						*/
+#define CONFIG_SYS_EBC_PB2AP           0x9400C800
+#define CONFIG_SYS_EBC_PB2CR           0xF0018000 /*  BAS=0x800,BS=1MB,BU=R/W,BW=8bit	*/
+
+#define CONFIG_SYS_EBC_CFG		0x7FC00000 /*  EBC0_CFG */
+
+/*-----------------------------------------------------------------------
+ * GPIO Setup
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_4xx_GPIO_TABLE { /*	  Out		  GPIO	Alternate1	Alternate2	Alternate3 */ \
+{											\
+/* GPIO Core 0 */									\
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO0	EBC_DATA_PAR(0)			*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO1	EBC_DATA_PAR(1)			*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO2	EBC_DATA_PAR(2)			*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO3	EBC_DATA_PAR(3)			*/	\
+{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO4	EBC_DATA(20)	USB2_DATA(4)	*/	\
+{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO5	EBC_DATA(21)	USB2_DATA(5)	*/	\
+{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO6	EBC_DATA(22)	USB2_DATA(6)	*/	\
+{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO7	EBC_DATA(23)	USB2_DATA(7)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8	CS(1)/NFCE(1)	IRQ(7)		*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9	CS(2)/NFCE(2)	IRQ(8)		*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 CS(3)/NFCE(3)	IRQ(9)		*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 IRQ(6)				*/	\
+{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO12 EBC_DATA(16)	USB2_DATA(0)	*/	\
+{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO13 EBC_DATA(17)	USB2_DATA(1)	*/	\
+{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO14 EBC_DATA(18)	USB2_DATA(2)	*/	\
+{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO15 EBC_DATA(19)	USB2_DATA(3)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 UART0_DCD	UART1_CTS	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 UART0_DSR	UART1_RTS	*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 UART0_CTS			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 UART0_RTS			*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO20 UART0_DTR	UART1_TX	*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO21 UART0_RI	UART1_RX	*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO22 EBC_HOLD_REQ	DMA_ACK2	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_0}, /* GPIO23 EBC_HOLD_ACK	DMA_REQ2	*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO24 EBC_EXT_REQ	DMA_EOT2	IRQ(4) */ \
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO25 EBC_EXT_ACK	DMA_ACK3	IRQ(3) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 EBC_ADDR(5)	DMA_EOT0	TS(3) */ \
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EBC_BUS_REQ	DMA_EOT3	IRQ(5) */ \
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL , GPIO_OUT_0}, /* GPIO28				*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO29 DMA_EOT1	IRQ(2)		*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO30 DMA_REQ1	IRQ(1)		*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO31 DMA_ACK1	IRQ(0)		*/	\
+}												\
+}
+
+#define CONFIG_SYS_GPIO_PCIE_RST	23
+#define CONFIG_SYS_GPIO_PCIE_CLKREQ	27
+#define CONFIG_SYS_GPIO_PCIE_WAKE	28
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/malta.h b/qemu/roms/u-boot/include/configs/malta.h
new file mode 100644
index 000000000..a29b86b4f
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/malta.h
@@ -0,0 +1,128 @@
+/*
+ * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef _MALTA_CONFIG_H
+#define _MALTA_CONFIG_H
+
+#include <asm/addrspace.h>
+#include <asm/malta.h>
+
+/*
+ * System configuration
+ */
+#define CONFIG_MALTA
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_MEMSIZE_IN_BYTES
+
+#define CONFIG_PCI
+#define CONFIG_PCI_GT64120
+#define CONFIG_PCI_MSC01
+#define CONFIG_PCI_PNP
+#define CONFIG_PCNET
+#define CONFIG_PCNET_79C973
+#define PCNET_HAS_PROM
+
+#define CONFIG_MISC_INIT_R
+#define CONFIG_RTC_MC146818
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS	0
+
+/*
+ * CPU Configuration
+ */
+#define CONFIG_SYS_MHZ			250	/* arbitrary value */
+#define CONFIG_SYS_MIPS_TIMER_FREQ	(CONFIG_SYS_MHZ * 1000000)
+
+#define CONFIG_SWAP_IO_SPACE
+
+/*
+ * Memory map
+ */
+#define CONFIG_SYS_TEXT_BASE		0xbe000000 /* Rom version */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_SDRAM_BASE		0x80000000 /* Cached addr */
+#define CONFIG_SYS_MEM_SIZE		(256 * 1024 * 1024)
+
+#define CONFIG_SYS_INIT_SP_OFFSET	0x400000
+
+#define CONFIG_SYS_LOAD_ADDR		0x81000000
+#define CONFIG_SYS_MEMTEST_START	0x80100000
+#define CONFIG_SYS_MEMTEST_END		0x80800000
+
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)
+#define CONFIG_SYS_BOOTPARAMS_LEN	(128 * 1024)
+#define CONFIG_SYS_BOOTM_LEN		(64 * 1024 * 1024)
+
+/*
+ * Console configuration
+ */
+#if defined(CONFIG_SYS_LITTLE_ENDIAN)
+#define CONFIG_SYS_PROMPT		"maltael # "
+#else
+#define CONFIG_SYS_PROMPT		"malta # "
+#endif
+
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					 sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+
+/*
+ * Serial driver
+ */
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		(115200 * 16)
+#define CONFIG_SYS_NS16550_COM1		CKSEG1ADDR(MALTA_GT_UART0_BASE)
+#define CONFIG_SYS_NS16550_COM2		CKSEG1ADDR(MALTA_MSC01_UART0_BASE)
+#define CONFIG_CONS_INDEX		1
+
+/*
+ * Flash configuration
+ */
+#define CONFIG_SYS_FLASH_BASE		(KSEG1 | MALTA_FLASH_BASE)
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	128
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE		0x20000
+#define CONFIG_ENV_SIZE			CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_ADDR \
+	(CONFIG_SYS_FLASH_BASE + (4 << 20) - CONFIG_ENV_SIZE)
+
+/*
+ * Commands
+ */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_NFS
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+
+#define CONFIG_SYS_LONGHELP		/* verbose help, undef to save memory */
+
+#endif /* _MALTA_CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/manroland/common.h b/qemu/roms/u-boot/include/configs/manroland/common.h
new file mode 100644
index 000000000..ab4a4710c
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/manroland/common.h
@@ -0,0 +1,125 @@
+/*
+ * (C) Copyright 2009
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MANROLAND_COMMON_H
+#define __MANROLAND_COMMON_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_BOARD_EARLY_INIT_R
+
+/* Partitions */
+#define CONFIG_DOS_PARTITION
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DISPLAY
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_SNTP
+
+/*
+ * 8-symbol LED display (can be accessed with 'display' command)
+ */
+#define CONFIG_PDSP188x
+
+#define	CONFIG_TIMESTAMP	1	/* Print image info with timestamp */
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT	"echo;" \
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addwdt=setenv bootargs ${bootargs} wdt=off\0"			\
+	"logval=4\0"							\
+	"addlog=setenv bootargs ${bootargs} loglevel=${logval}\0"	\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"kernel_addr=ff810000\0"					\
+	"fdt_addr="__stringify(CONFIG_SYS_FLASH_BASE)"\0"		\
+	"flash_nfs=run nfsargs addip addcon addwdt addlog;"		\
+		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
+	"rootpath=/opt/eldk/ppc_82xx\0"					\
+	"kernel_addr_r=300000\0"					\
+	"fdt_addr_r=200000\0"						\
+	"fdt_file=" __stringify(CONFIG_HOSTNAME) "/" 			\
+		__stringify(CONFIG_HOSTNAME) ".dtb\0"			\
+	"kernel_file=" __stringify(CONFIG_HOSTNAME) "/uImage \0" 	\
+	"load_fdt=tftp ${fdt_addr_r} ${fdt_file};\0"			\
+	"load_kernel=tftp ${kernel_addr_r} ${kernel_file};\0" 		\
+	"addcon=setenv bootargs ${bootargs} console=ttyPSC0,${baudrate}\0"\
+	"net_nfs=run load_fdt load_kernel; "				\
+		"run nfsargs addip addcon addwdt addlog;"		\
+		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
+	"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin \0" 	\
+	"u-boot_addr_r=200000\0"					\
+	"load=tftp ${u-boot_addr_r} ${u-boot}\0"			\
+	"update=protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +${filesize};"\
+		"erase " __stringify(CONFIG_SYS_TEXT_BASE) " +${filesize};"\
+		"cp.b ${u-boot_addr_r} " __stringify(CONFIG_SYS_TEXT_BASE) \
+		" ${filesize};"						\
+		"protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +${filesize}\0"\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run net_nfs"
+
+#define CONFIG_MISC_INIT_R	1
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+#define CONFIG_CMDLINE_EDITING		1	/* add command line history */
+#define CONFIG_AUTO_COMPLETE		/* add autocompletion support	*/
+
+/* Enable an alternate, more extensive memory test */
+#define CONFIG_SYS_ALT_MEMTEST
+
+/*
+ * Enable loopw command.
+ */
+#define CONFIG_LOOPW
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+#endif /* __MANROLAND_COMMON_H */
diff --git a/qemu/roms/u-boot/include/configs/manroland/mpc5200-common.h b/qemu/roms/u-boot/include/configs/manroland/mpc5200-common.h
new file mode 100644
index 000000000..60e8716a7
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/manroland/mpc5200-common.h
@@ -0,0 +1,205 @@
+/*
+ * (C) Copyright 2009
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MANROLAND_MPC52XX__COMMON_H
+#define __MANROLAND_MPC52XX__COMMON_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MPC5200		1	/* MPC5200 CPU */
+
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz	*/
+
+#define CONFIG_HIGH_BATS	1	/* High BATs supported 			*/
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1	*/
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200,\
+					 230400 }
+
+#if (CONFIG_SYS_TEXT_BASE == 0xFFF00000) /* Boot low */
+#   define CONFIG_SYS_LOWBOOT		1
+#endif
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #1 or #2 */
+
+#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x58
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
+
+/*
+ * RTC configuration
+ */
+#define CONFIG_RTC_PCF8563
+#define CONFIG_SYS_I2C_RTC_ADDR		0x51
+
+/* I2C SYSMON (LM75) */
+#define CONFIG_DTT_LM81			1	/* ON Semi's LM75	*/
+#define CONFIG_DTT_SENSORS		{0}	/* Sensor addresses	*/
+#define CONFIG_SYS_DTT_MAX_TEMP		70
+#define CONFIG_SYS_DTT_LOW_TEMP		-30
+#define CONFIG_SYS_DTT_HYSTERESIS		3
+
+/*
+ * Flash configuration
+ */
+#define CONFIG_SYS_FLASH_BASE		0xFF800000
+
+#define CONFIG_SYS_FLASH_SIZE		0x00800000 /* 8 MByte */
+
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_TEXT_BASE+0x40000) /* second sector */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks
+					   (= chip selects) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout [ms]*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout [ms]*/
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_CFI_AMD_RESET
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_SIZE		0x4000
+#define CONFIG_ENV_OFFSET_REDUND   (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND     (CONFIG_ENV_SIZE)
+
+/*
+ * Memory map
+ */
+#define CONFIG_SYS_MBAR		0xF0000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE -\
+					 GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SRAM_BASE	0x80100000	/* CS 1 */
+#define CONFIG_SYS_DISPLAY_BASE	0x80600000	/* CS 3 */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_DDR	 1
+#define SDRAM_MODE      0x018D0000
+#define SDRAM_EMODE     0x40090000
+#define SDRAM_CONTROL   0x714f0f00
+#define SDRAM_CONFIG1   0x73722930
+#define SDRAM_CONFIG2   0x47770000
+#define SDRAM_TAPDELAY  0x10000000
+
+/* Use ON-Chip SRAM until RAM will be available */
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+#ifdef CONFIG_POST
+/* preserve space for the post_word at end of on-chip SRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_POST_SIZE
+#else
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
+#endif
+
+#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN		(192 << 10)
+#define CONFIG_SYS_MALLOC_LEN		(512 << 10)
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC	1
+#define CONFIG_MPC5xxx_FEC_MII100
+#define CONFIG_PHY_ADDR		0x00
+#define CONFIG_MII		1
+
+/*use  Hardware WDT */
+#define CONFIG_HW_WATCHDOG
+
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs		*/
+#if defined(CONFIG_CMD_KGDB)
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value*/
+#endif
+
+/*
+ * Various low-level settings
+ */
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
+
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
+
+/* 8Mbit SRAM @0x80100000 */
+#define CONFIG_SYS_CS1_START		CONFIG_SYS_SRAM_BASE
+
+#define CONFIG_SYS_CS_BURST		0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE	0x33333333
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+
+#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus	*/
+
+#define CONFIG_IDE_PREINIT	1
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
+
+/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
+
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)
+
+/* Interval between registers	*/
+#define CONFIG_SYS_ATA_STRIDE          4
+
+#define CONFIG_ATAPI            1
+
+#define OF_CPU			"PowerPC,5200@0"
+#define OF_SOC			"soc5200@f0000000"
+#define OF_TBCLK		(bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH		"/soc5200@f0000000/serial@2000"
+#define CONFIG_OF_IDE_FIXUP
+
+#endif /* __MANROLAND_MPC52XX__COMMON_H */
diff --git a/qemu/roms/u-boot/include/configs/mcc200.h b/qemu/roms/u-boot/include/configs/mcc200.h
new file mode 100644
index 000000000..a317782db
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/mcc200.h
@@ -0,0 +1,397 @@
+/*
+ * (C) Copyright 2006-2008
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5200
+#define CONFIG_MCC200		1	/* MCC200 board */
+
+/*
+ * Valid values for CONFIG_SYS_TEXT_BASE are:
+ * 0xFC000000	boot low (standard configuration)
+ * 0xFFF00000	boot high
+ * 0x00100000	boot from RAM (for testing only)
+ */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xFC000000
+#endif
+
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33MHz		*/
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_HIGH_BATS	1	/* High BATs supported			*/
+
+/*
+ * Serial console configuration
+ *
+ *  To select console on the one of 8 external UARTs,
+ * define CONFIG_QUART_CONSOLE as 1, 2, 3, or 4 for the first Quad UART,
+ * or as 5, 6, 7, or 8 for the second Quad UART.
+ * COM11, COM12, COM13, COM14 are located on the second Quad UART.
+ *
+ *  CONFIG_PSC_CONSOLE must be undefined in this case.
+ */
+#if !defined(CONFIG_PRS200)
+/* MCC200 configuration: */
+#ifdef CONFIG_CONSOLE_COM12
+#define CONFIG_QUART_CONSOLE	6	/* console is on UARTF of QUART2	*/
+#else
+#define CONFIG_QUART_CONSOLE	8	/* console is on UARTH of QUART2	*/
+#endif
+#else
+/* PRS200 configuration: */
+#undef CONFIG_QUART_CONSOLE
+#endif /* CONFIG_PRS200 */
+/*
+ *  To select console on PSC1, define CONFIG_PSC_CONSOLE as 1
+ * and undefine CONFIG_QUART_CONSOLE.
+ */
+#if !defined(CONFIG_PRS200)
+/* MCC200 configuration: */
+#define CONFIG_PSC_CONSOLE	1	/* PSC1 may be COM */
+#define CONFIG_PSC_CONSOLE2	2	/* PSC2 is PSoC */
+#else
+/* PRS200 configuration: */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1		*/
+#endif
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#define CONFIG_MII		1
+
+#define CONFIG_DOS_PARTITION
+
+/* USB */
+#define CONFIG_USB_OHCI
+#define CONFIG_USB_STORAGE
+/* automatic software updates (see board/mcc200/auto_update.c) */
+#define CONFIG_AUTO_UPDATE 1
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_USB
+
+#undef	CONFIG_CMD_NET
+#undef	CONFIG_CMD_NFS
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	1	/* autoboot after 1 second */
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#ifdef CONFIG_PRS200
+# define CONFIG_SYS__BOARDNAME		"prs200"
+# define CONFIG_SYS__LINUX_CONSOLE	"ttyS0"
+#else
+# define CONFIG_SYS__BOARDNAME		"mcc200"
+# define CONFIG_SYS__LINUX_CONSOLE	"ttyEU5"
+#endif
+
+/* Network */
+#define CONFIG_ETHADDR	00:17:17:ff:00:00
+#define CONFIG_IPADDR	10.76.9.29
+#define CONFIG_SERVERIP	10.76.9.1
+
+#include <version.h> /* For U-Boot version */
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"ubootver=" U_BOOT_VERSION "\0"					\
+	"netdev=eth0\0"							\
+	"hostname=" CONFIG_SYS__BOARDNAME "\0"				\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/mtdblock2 "			\
+		"rootfstype=cramfs\0"					\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addcons=setenv bootargs ${bootargs} "				\
+		"console=${console},${baudrate} "			\
+		"ubootver=${ubootver} board=${board}\0"			\
+	"flash_nfs=run nfsargs addip addcons;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip addcons;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};"				\
+		"run nfsargs addip addcons;bootm\0"			\
+	"console=" CONFIG_SYS__LINUX_CONSOLE "\0"				\
+	"rootpath=/opt/eldk/ppc_6xx\0"					\
+	"bootfile=/tftpboot/" CONFIG_SYS__BOARDNAME "/uImage\0"		\
+	"load=tftp 200000 /tftpboot/" CONFIG_SYS__BOARDNAME "/u-boot.bin\0"	\
+	"text_base=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"		\
+	"kernel_addr=0xFC0C0000\0"					\
+	"update=protect off ${text_base} +${filesize};"			\
+		"era ${text_base} +${filesize};"			\
+		"cp.b 200000 ${text_base} ${filesize}\0"		\
+	"unlock=yes\0"							\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_SYS_HUSH_PARSER		1	/* use "hush" command parser	*/
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #1 or #2 */
+
+#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+
+/*
+ * Flash configuration (8,16 or 32 MB)
+ * TEXT base always at 0xFFF00000
+ * ENV_ADDR always at  0xFFF40000
+ * FLASH_BASE at 0xFC000000 for 64 MB (only 32MB are supported, not enough addr lines!!!)
+ *		 0xFE000000 for 32 MB
+ *		 0xFF000000 for 16 MB
+ *		 0xFF800000 for  8 MB
+ */
+#define CONFIG_SYS_FLASH_BASE		0xfc000000
+#define CONFIG_SYS_FLASH_SIZE		0x04000000
+
+#define CONFIG_SYS_FLASH_CFI				/* The flash is CFI compatible	*/
+#define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/
+
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* hardware flash protection		*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash	*/
+
+#define CONFIG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars	*/
+
+#define CONFIG_ENV_SECT_SIZE	0x40000	/* size of one complete sector	*/
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+#define CONFIG_ENV_OVERWRITE	1	/* allow modification of vendor params */
+
+#if CONFIG_SYS_TEXT_BASE == CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_LOWBOOT	1
+#endif
+
+/*
+ * Memory map
+ */
+#define CONFIG_SYS_MBAR		0xf0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
+
+/* Use SRAM until RAM will be available */
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */
+
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(512 << 10)	/* Reserve 512 kB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+/* #define CONFIG_MPC5xxx_FEC	1 */
+/* #define CONFIG_MPC5xxx_FEC_MII100 */
+/*
+ * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
+ */
+/* #define CONFIG_MPC5xxx_FEC_MII10 */
+#define CONFIG_PHY_ADDR		1
+
+/*
+ * LCD Splash Screen
+ */
+#if !defined(CONFIG_PRS200)
+#define CONFIG_LCD		1
+#define CONFIG_PROGRESSBAR 1
+#endif
+
+#if defined(CONFIG_LCD)
+#define CONFIG_SPLASH_SCREEN	1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
+#define LCD_BPP			LCD_MONOCHROME
+#endif
+
+/*
+ * GPIO configuration
+ */
+/* 0x10000004 = 32MB SDRAM */
+/* 0x90000004 = 64MB SDRAM */
+#if defined(CONFIG_LCD)
+/* set PSC2 in UART mode */
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x00000044
+#else
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x00000004
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size	*/
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
+
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs			*/
+#if defined(CONFIG_CMD_KGDB)
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Various low-level settings
+ */
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
+
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_CFG		0x0004fb00
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
+
+/* Quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
+#define CONFIG_SYS_CS2_START		0x80000000
+#define CONFIG_SYS_CS2_SIZE		0x00001000
+#define CONFIG_SYS_CS2_CFG		0x1d300
+
+/* Second Quad UART @0x80010000 */
+#define CONFIG_SYS_CS1_START		0x80010000
+#define CONFIG_SYS_CS1_SIZE		0x00001000
+#define CONFIG_SYS_CS1_CFG		0x1d300
+
+/* Leica - build revision resistors */
+/*
+#define CONFIG_SYS_CS3_START		0x80020000
+#define CONFIG_SYS_CS3_SIZE		0x00000004
+#define CONFIG_SYS_CS3_CFG		0x1d300
+*/
+
+/*
+ *  Select one of quarts as a default
+ * console. If undefined - PSC console
+ * wil be default
+ */
+#define CONFIG_SYS_CS_BURST		0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE	0x33333333
+
+#define CONFIG_SYS_RESET_ADDRESS	0xff000000
+
+/*
+ * QUART Expanders support
+ */
+#if defined(CONFIG_QUART_CONSOLE)
+/*
+ * We'll use NS16550 chip routines,
+ */
+#define CONFIG_SYS_NS16550		1
+#define CONFIG_SYS_NS16550_SERIAL	1
+#define CONFIG_CONS_INDEX	1
+/*
+ *  To achieve necessary offset on SC16C554
+ * A0-A2 (register select) pins with NS16550
+ * functions (in struct NS16550), REG_SIZE
+ * should be 4, because A0-A2 pins are connected
+ * to DA2-DA4 address bus lines.
+ */
+#define CONFIG_SYS_NS16550_REG_SIZE	4
+/*
+ * LocalPlus Bus already inited in cpu_init_f(),
+ * so can work with QUART's chip selects.
+ * One of four SC16C554 UARTs is selected with
+ * A3-A4 (DA5-DA6) lines.
+ */
+#if (CONFIG_QUART_CONSOLE > 0) && (CONFIG_QUART_CONSOLE < 5) && !defined(CONFIG_PRS200)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CS2_START | (CONFIG_QUART_CONSOLE - 1)<<5)
+#elif (CONFIG_QUART_CONSOLE > 4) && (CONFIG_QUART_CONSOLE < 9)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CS1_START | (CONFIG_QUART_CONSOLE - 5)<<5)
+#else
+#error "Wrong QUART expander number."
+#endif
+
+/*
+ * SC16C554 chip's external crystal oscillator frequency
+ * is 7.3728 MHz
+ */
+#define CONFIG_SYS_NS16550_CLK		7372800
+#endif /* CONFIG_QUART_CONSOLE */
+/*-----------------------------------------------------------------------
+ * USB stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_USB_CLOCK	0x0001BBBB
+#define CONFIG_USB_CONFIG	0x00005000
+
+#define CONFIG_AUTOBOOT_KEYED		/* use key strings to stop autoboot	*/
+#define CONFIG_AUTOBOOT_STOP_STR	"432"
+#define CONFIG_SILENT_CONSOLE	1
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/mcx.h b/qemu/roms/u-boot/include/configs/mcx.h
new file mode 100644
index 000000000..47244c003
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/mcx.h
@@ -0,0 +1,426 @@
+/*
+ * Copyright (C) 2011 Ilya Yanok, Emcraft Systems
+ *
+ * Based on omap3_evm_config.h
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_OMAP			/* in a TI OMAP core */
+#define CONFIG_OMAP34XX			/* which is a 34XX */
+#define CONFIG_OMAP3_MCX		/* working with mcx */
+#define CONFIG_OMAP_GPIO
+#define CONFIG_OMAP_COMMON
+
+#define MACH_TYPE_MCX			3656
+#define CONFIG_MACH_TYPE	MACH_TYPE_MCX
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
+#define CONFIG_EMIF4	/* The chip has EMIF4 controller */
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_FIT
+
+/*
+ * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader
+ * and older u-boot.bin with the new U-Boot SPL.
+ */
+#define CONFIG_SYS_TEXT_BASE		0x80008000
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Clock Defines */
+#define V_OSCK			26000000	/* Clock output from T2 */
+#define V_SCLK			(V_OSCK >> 1)
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB sector */
+#define CONFIG_SYS_MALLOC_LEN		(1024 << 10)
+/*
+ * DDR related
+ */
+#define CONFIG_SYS_CS0_SIZE		(256 * 1024 * 1024)
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX		3
+#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
+#define CONFIG_SERIAL3			3	/* UART3 */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
+					115200}
+#define CONFIG_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DOS_PARTITION
+
+/* EHCI */
+#define CONFIG_USB_STORAGE
+#define CONFIG_OMAP3_GPIO_2
+#define CONFIG_OMAP3_GPIO_5
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_OMAP
+#define CONFIG_USB_ULPI
+#define CONFIG_USB_ULPI_VIEWPORT_OMAP
+#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO	57
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
+#define CONFIG_CMD_FAT		/* FAT support			*/
+#define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
+#define CONFIG_CMD_MMC		/* MMC support			*/
+#define CONFIG_CMD_FAT		/* FAT support			*/
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_NAND		/* NAND support			*/
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_GPIO
+
+#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
+#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
+#undef CONFIG_CMD_IMI		/* iminfo			*/
+#undef CONFIG_CMD_IMLS		/* List all found images	*/
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
+#define CONFIG_SYS_I2C_OMAP34XX
+
+/* RTC */
+#define CONFIG_RTC_DS1337
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68
+
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
+							/* to access nand */
+#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
+							/* to access */
+							/* nand at CS0 */
+
+#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
+							/* NAND devices */
+#define CONFIG_JFFS2_NAND
+/* nand device jffs2 lives on */
+#define CONFIG_JFFS2_DEV		"nand0"
+/* start of jffs2 partition */
+#define CONFIG_JFFS2_PART_OFFSET	0x680000
+#define CONFIG_JFFS2_PART_SIZE		0xf980000	/* sz of jffs2 part */
+
+/* Environment information */
+#define CONFIG_BOOTDELAY	3
+
+#define CONFIG_BOOTFILE		"uImage"
+
+#define xstr(s)	str(s)
+#define str(s)	#s
+
+/* Setup MTD for NAND on the SOM */
+#define MTDIDS_DEFAULT		"nand0=omap2-nand.0"
+#define MTDPARTS_DEFAULT	"mtdparts=omap2-nand.0:512k(MLO),"	\
+				"1m(u-boot),256k(env1),"		\
+				"256k(env2),6m(kernel),6m(k_recovery),"	\
+				"8m(fs_recovery),-(common_data)"
+
+#define CONFIG_HOSTNAME mcx
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"adddbg=setenv bootargs ${bootargs} trace_buf_size=64M\0"	\
+	"adddebug=setenv bootargs ${bootargs} earlyprintk=serial\0"	\
+	"addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0"	\
+	"addfb=setenv bootargs ${bootargs} vram=6M "			\
+		"omapfb.vram=1:2M,2:2M,3:2M omapdss.def_disp=lcd\0"	\
+	"addip_sta=setenv bootargs ${bootargs} "			\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:"		\
+		"${netmask}:${hostname}:eth0:off\0"			\
+	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0"		\
+	"addip=if test -n ${ipdyn};then run addip_dyn;"			\
+		"else run addip_sta;fi\0"				\
+	"addmisc=setenv bootargs ${bootargs} ${misc}\0"			\
+	"addtty=setenv bootargs ${bootargs} "				\
+		"console=${consoledev},${baudrate}\0"			\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
+	"baudrate=115200\0"						\
+	"consoledev=ttyO2\0"						\
+	"hostname=" xstr(CONFIG_HOSTNAME) "\0"				\
+	"loadaddr=0x82000000\0"						\
+	"load=tftp ${loadaddr} ${u-boot}\0"				\
+	"load_k=tftp ${loadaddr} ${bootfile}\0"				\
+	"loaduimage=fatload mmc 0 ${loadaddr} uImage\0"			\
+	"loadmlo=tftp ${loadaddr} ${mlo}\0"				\
+	"mlo=" xstr(CONFIG_HOSTNAME) "/MLO\0"				\
+	"mmcargs=root=/dev/mmcblk0p2 rw "				\
+		"rootfstype=ext3 rootwait\0"				\
+	"mmcboot=echo Booting from mmc ...; "				\
+		"run mmcargs; "						\
+		"run addip addtty addmtd addfb addeth addmisc;"		\
+		"run loaduimage; "					\
+		"bootm ${loadaddr}\0"					\
+	"net_nfs=run load_k; "						\
+		"run nfsargs; "						\
+		"run addip addtty addmtd addfb addeth addmisc;"		\
+		"bootm ${loadaddr}\0"					\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.img\0"			\
+	"uboot_addr=0x80000\0"						\
+	"update=nandecc sw;nand erase ${uboot_addr} 100000;"		\
+		"nand write ${loadaddr} ${uboot_addr} 80000\0"		\
+	"updatemlo=nandecc hw;nand erase 0 20000;"			\
+		"nand write ${loadaddr} 0 20000\0"			\
+	"upd=if run load;then echo Updating u-boot;if run update;"	\
+		"then echo U-Boot updated;"				\
+			"else echo Error updating u-boot !;"		\
+			"echo Board without bootloader !!;"		\
+		"fi;"							\
+		"else echo U-Boot not downloaded..exiting;fi\0"		\
+	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0"		\
+	"bootscript=echo Running bootscript from mmc ...; "		\
+		"source ${loadaddr}\0"					\
+	"nandargs=setenv bootargs ubi.mtd=7 "				\
+		"root=ubi0:rootfs rootfstype=ubifs\0"			\
+	"nandboot=echo Booting from nand ...; "				\
+		"run nandargs; "					\
+		"ubi part nand0,4;"					\
+		"ubi readvol ${loadaddr} kernel;"			\
+		"run addtty addmtd addfb addeth addmisc;"		\
+		"bootm ${loadaddr}\0"					\
+	"preboot=ubi part nand0,7;"					\
+		"ubi readvol ${loadaddr} splash;"			\
+		"bmp display ${loadaddr};"				\
+		"gpio set 55\0"						\
+	"swupdate_args=setenv bootargs root=/dev/ram "			\
+		"quiet loglevel=1 "					\
+		"consoleblank=0 ${swupdate_misc}\0"			\
+	"swupdate=echo Running Sw-Update...;"				\
+		"if printenv mtdparts;then echo Starting SwUpdate...; "	\
+		"else mtdparts default;fi; "				\
+		"ubi part nand0,5;"					\
+		"ubi readvol 0x82000000 kernel_recovery;"		\
+		"ubi part nand0,6;"					\
+		"ubi readvol 0x84000000 fs_recovery;"			\
+		"run swupdate_args; "					\
+		"setenv bootargs ${bootargs} "				\
+			"${mtdparts} "					\
+			"vram=6M omapfb.vram=1:2M,2:2M,3:2M "		\
+			"omapdss.def_disp=lcd;"				\
+		"bootm 0x82000000 0x84000000\0"				\
+	"bootcmd=mmc rescan;if fatload mmc 0 82000000 loadbootscr.scr;"	\
+		"then source 82000000;else run nandboot;fi\0"
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+
+/*
+ * Miscellaneous configurable options
+ */
+#define V_PROMPT			"mcx # "
+
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT		V_PROMPT
+#define CONFIG_SYS_CBSIZE		1024/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16	/* max number of command */
+						/* args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
+#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
+					0x01F00000) /* 31MB */
+
+#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
+								/* address */
+#define CONFIG_PREBOOT
+
+/*
+ * AM3517 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
+#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
+#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
+
+/*
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+
+/* Configure the PISMO */
+#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
+
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_ENV_IS_IN_NAND
+#define SMNAND_ENV_OFFSET		0x180000 /* environment starts here */
+
+/* Redundant Environment */
+#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
+#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
+#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
+						2 * CONFIG_SYS_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
+
+/* Flash banks JFFS2 should use */
+#define CONFIG_SYS_MAX_MTD_BANKS	(CONFIG_SYS_MAX_FLASH_BANKS + \
+					CONFIG_SYS_MAX_NAND_DEVICE)
+#define CONFIG_SYS_JFFS2_MEM_NAND
+/* use flash_info[2] */
+#define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
+#define CONFIG_SYS_JFFS2_NUM_BANKS	1
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE	0x800
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_NAND_SIMPLE
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
+
+#define CONFIG_SPL_TEXT_BASE		0x40200000 /*CONFIG_SYS_SRAM_START*/
+#define CONFIG_SPL_MAX_SIZE		(54 * 1024)	/* 8 KB for stack */
+#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
+
+/* move malloc and bss high to prevent clashing with the main image */
+#define CONFIG_SYS_SPL_MALLOC_START	0x8f000000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
+#define CONFIG_SPL_BSS_START_ADDR	0x8f080000 /* end of RAM */
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
+
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
+
+/* NAND boot config */
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
+#define CONFIG_SYS_NAND_ECCPOS		{40, 41, 42, 43, 44, 45, 46, 47,\
+					 48, 49, 50, 51, 52, 53, 54, 55,\
+					 56, 57, 58, 59, 60, 61, 62, 63}
+#define CONFIG_SYS_NAND_ECCSIZE		256
+#define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_SW
+#define CONFIG_SPL_NAND_SOFTECC
+
+#define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+
+/*
+ * ethernet support
+ *
+ */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_DRIVER_TI_EMAC_USE_RMII
+#define CONFIG_MII
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT 10
+#endif
+
+#define CONFIG_VIDEO
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_CMD_BMP
+#define CONFIG_VIDEO_OMAP3
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/mecp5123.h b/qemu/roms/u-boot/include/configs/mecp5123.h
new file mode 100644
index 000000000..6c19817f8
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/mecp5123.h
@@ -0,0 +1,440 @@
+/*
+ * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
+ * (C) Copyright 2009, DAVE Srl <www.dave.eu>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ * modifications for the MECP5123 by reinhard.arlt@esd-electronics.com
+ *
+ */
+
+/*
+ * MECP5123 board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MECP5123 1
+/*
+ * Memory map for the MECP5123 board:
+ *
+ * 0x0000_0000 - 0x1FFF_FFFF	DDR RAM (512 MB)
+ * 0x3000_0000 - 0x3001_FFFF	SRAM (128 KB)
+ * 0x8000_0000 - 0x803F_FFFF	IMMR (4 MB)
+ * 0x8200_0000 - 0x8200_FFFF	VPC-3 (64 KB)
+ * 0xFFC0_0000 - 0xFFFF_FFFF	NOR Boot FLASH (64 MB)
+ */
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1	/* E300 Family */
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
+
+#define CONFIG_SYS_MPC512X_CLKIN	33333333	/* in Hz */
+
+#define CONFIG_BOARD_EARLY_INIT_F		/* call board_early_init_f() */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_SYS_IMMR		        0x80000000
+#define CONFIG_SYS_DIU_ADDR		(CONFIG_SYS_IMMR+0x2100)
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000      /* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+
+/*
+ * DDR Setup - manually set all parameters as there's no SPD etc.
+ */
+#define CONFIG_SYS_DDR_SIZE		512		/* MB */
+
+#define CONFIG_SYS_DDR_BASE		0x00000000	/* DDR is sys memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_MAX_RAM_SIZE		0x20000000
+
+#define CONFIG_SYS_IOCTRL_MUX_DDR	0x00000036
+
+/* DDR Controller Configuration
+ *
+ * SYS_CFG:
+ *	[31:31]	MDDRC Soft Reset:	Diabled
+ *	[30:30]	DRAM CKE pin:		Enabled
+ *	[29:29]	DRAM CLK:		Enabled
+ *	[28:28]	Command Mode:		Enabled (For initialization only)
+ *	[27:25]	DRAM Row Select:	dram_row[15:0] = magenta_address[25:10]
+ *	[24:21]	DRAM Bank Select:	dram_bank[1:0] = magenta_address[11:10]
+ *	[20:19]	Read Test:		DON'T USE
+ *	[18:18]	Self Refresh:		Enabled
+ *	[17:17]	16bit Mode:		Disabled
+ *	[16:13] Ready Delay:		2
+ *	[12:12]	Half DQS Delay:		Disabled
+ *	[11:11]	Quarter DQS Delay:	Disabled
+ *	[10:08]	Write Delay:		2
+ *	[07:07]	Early ODT:		Disabled
+ *	[06:06]	On DIE Termination:	Disabled
+ *	[05:05]	FIFO Overflow Clear:	DON'T USE here
+ *	[04:04]	FIFO Underflow Clear:	DON'T USE here
+ *	[03:03]	FIFO Overflow Pending:	DON'T USE here
+ *	[02:02]	FIFO Underlfow Pending:	DON'T USE here
+ *	[01:01]	FIFO Overlfow Enabled:	Enabled
+ *	[00:00]	FIFO Underflow Enabled:	Enabled
+ * TIME_CFG0
+ *	[31:16]	DRAM Refresh Time:	0 CSB clocks
+ *	[15:8]	DRAM Command Time:	0 CSB clocks
+ *	[07:00]	DRAM Precharge Time:	0 CSB clocks
+ * TIME_CFG1
+ *	[31:26]	DRAM tRFC:
+ *	[25:21]	DRAM tWR1:
+ *	[20:17]	DRAM tWRT1:
+ *	[16:11]	DRAM tDRR:
+ *	[10:05]	DRAM tRC:
+ *	[04:00]	DRAM tRAS:
+ * TIME_CFG2
+ *	[31:28]	DRAM tRCD:
+ *	[27:23]	DRAM tFAW:
+ *	[22:19]	DRAM tRTW1:
+ *	[18:15]	DRAM tCCD:
+ *	[14:10] DRAM tRTP:
+ *	[09:05]	DRAM tRP:
+ *	[04:00] DRAM tRPA
+ */
+#define CONFIG_SYS_MDDRC_SYS_CFG	 0xEA804A00
+#define CONFIG_SYS_MDDRC_TIME_CFG0	 0x06183D2E
+#define CONFIG_SYS_MDDRC_TIME_CFG1	 0x68EC1168
+#define CONFIG_SYS_MDDRC_TIME_CFG2	 0x34310864
+
+#define CONFIG_SYS_DDRCMD_NOP		0x01380000
+#define CONFIG_SYS_DDRCMD_PCHG_ALL	0x01100400
+#define CONFIG_SYS_DDRCMD_EM2		0x01020000
+#define CONFIG_SYS_DDRCMD_EM3		0x01030000
+#define CONFIG_SYS_DDRCMD_EN_DLL	0x01010000
+#define CONFIG_SYS_DDRCMD_RFSH		0x01080000
+#define CONFIG_SYS_MICRON_INIT_DEV_OP	0x01000432
+#define CONFIG_SYS_DDRCMD_OCD_DEFAULT	0x01010780
+
+/* DDR Priority Manager Configuration */
+#define CONFIG_SYS_MDDRCGRP_PM_CFG1	0x00077777
+#define CONFIG_SYS_MDDRCGRP_PM_CFG2	0x00000000
+#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG	0x00000001
+#define CONFIG_SYS_MDDRCGRP_LUT0_MU	0xFFEEDDCC
+#define CONFIG_SYS_MDDRCGRP_LUT0_ML	0xBBAAAAAA
+#define CONFIG_SYS_MDDRCGRP_LUT1_MU	0x66666666
+#define CONFIG_SYS_MDDRCGRP_LUT1_ML	0x55555555
+#define CONFIG_SYS_MDDRCGRP_LUT2_MU	0x44444444
+#define CONFIG_SYS_MDDRCGRP_LUT2_ML	0x44444444
+#define CONFIG_SYS_MDDRCGRP_LUT3_MU	0x55555555
+#define CONFIG_SYS_MDDRCGRP_LUT3_ML	0x55555558
+#define CONFIG_SYS_MDDRCGRP_LUT4_MU	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT4_ML	0x11111122
+#define CONFIG_SYS_MDDRCGRP_LUT0_AU	0xaaaaaaaa
+#define CONFIG_SYS_MDDRCGRP_LUT0_AL	0xaaaaaaaa
+#define CONFIG_SYS_MDDRCGRP_LUT1_AU	0x66666666
+#define CONFIG_SYS_MDDRCGRP_LUT1_AL	0x66666666
+#define CONFIG_SYS_MDDRCGRP_LUT2_AU	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT2_AL	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT3_AU	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT3_AL	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT4_AU	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT4_AL	0x11111111
+
+/*
+ * NOR FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
+#define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
+
+#define CONFIG_SYS_FLASH_BASE		0xFFC00000	/* start of FLASH */
+#define CONFIG_SYS_FLASH_SIZE		0x00400000	/* max flash size */
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max sectors per device */
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+
+/*
+ * NAND FLASH
+ * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only)
+ */
+#define CONFIG_CMD_NAND
+#define CONFIG_NAND_MPC5121_NFC
+#define CONFIG_SYS_NAND_BASE            0x40000000
+#define CONFIG_SYS_MAX_NAND_DEVICE      1
+
+/*
+ * Configuration parameters for MPC5121 NAND driver
+ */
+#define CONFIG_FSL_NFC_WIDTH		1
+#define CONFIG_FSL_NFC_WRITE_SIZE	2048
+#define CONFIG_FSL_NFC_SPARE_SIZE	64
+#define CONFIG_FSL_NFC_CHIPS		1
+
+#define CONFIG_SYS_SRAM_BASE		0x30000000
+#define CONFIG_SYS_SRAM_SIZE		0x00020000	/* 128 KB */
+
+/* Initialize Local Window for NOR FLASH access */
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
+
+/* ALE active low, data size 4bytes */
+#define CONFIG_SYS_CS0_CFG		0x05051150
+
+/* Use not alternative CS timing */
+#define CONFIG_SYS_CS_ALETIMING		0x00000000
+
+/* ALE active low, data size 4bytes */
+#define CONFIG_SYS_CS1_CFG		0x1f1f3090
+#define CONFIG_SYS_VPC3_BASE		0x82000000	/* start of VPC3 space */
+#define CONFIG_SYS_VPC3_SIZE		0x00010000	/* max VPC3 size */
+/* Initialize Local Window for VPC3 access */
+#define CONFIG_SYS_CS1_START		CONFIG_SYS_VPC3_BASE
+#define CONFIG_SYS_CS1_SIZE		CONFIG_SYS_VPC3_SIZE
+
+/* Use SRAM for initial stack */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_SRAM_BASE /* Init RAM addr */
+#define CONFIG_SYS_INIT_RAM_SIZE		CONFIG_SYS_SRAM_SIZE
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE	/* Start of monitor */
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Monitor length */
+#define CONFIG_SYS_MALLOC_LEN		(6 * 1024 * 1024) /* Malloc size */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX     1
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	3	/* console is on PSC3 */
+#define CONFIG_SYS_PSC3
+#if CONFIG_PSC_CONSOLE != 3
+#error CONFIG_PSC_CONSOLE must be 3
+#endif
+#define CONFIG_BAUDRATE		9600	/* ... at 9600 bps */
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONSOLE_FIFO_TX_SIZE	FIFOC_PSC3_TX_SIZE
+#define CONSOLE_FIFO_TX_ADDR	FIFOC_PSC3_TX_ADDR
+#define CONSOLE_FIFO_RX_SIZE	FIFOC_PSC3_RX_SIZE
+#define CONSOLE_FIFO_RX_ADDR	FIFOC_PSC3_RX_ADDR
+
+/*
+ * Clocks in use
+ */
+#define SCCR1_CLOCKS_EN	(CLOCK_SCCR1_CFG_EN |				\
+			 CLOCK_SCCR1_LPC_EN |				\
+			 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |	\
+			 CLOCK_SCCR1_PSCFIFO_EN |			\
+			 CLOCK_SCCR1_DDR_EN |				\
+			 CLOCK_SCCR1_FEC_EN |				\
+			 CLOCK_SCCR1_NFC_EN |				\
+			 CLOCK_SCCR1_PCI_EN |				\
+			 CLOCK_SCCR1_TPR_EN)
+
+#define SCCR2_CLOCKS_EN	(CLOCK_SCCR2_MEM_EN |	\
+			 CLOCK_SCCR2_I2C_EN)
+
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef  CONFIG_SYS_HUSH_PARSER
+#endif
+
+/* I2C */
+#define CONFIG_HARD_I2C			/* I2C with hardware support */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed */
+#define CONFIG_SYS_I2C_SLAVE		0x7F	/* slave address */
+
+/*
+ * IIM - IC Identification Module
+ */
+#undef CONFIG_FSL_IIM
+
+/*
+ * EEPROM configuration
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2	/* 16-bit EEPROM address */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* Atmel: AT24C32A-10TQ-2.7 */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10	/* 10ms of delay */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5	/* 32-Byte Page Write Mode */
+#define CONFIG_SYS_EEPROM_WREN			/* Use EEPROM write protect */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC512x_FEC	1
+#define CONFIG_PHY_ADDR		0x1
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_FEC_AN_TIMEOUT	1
+#define CONFIG_HAS_ETH0
+
+/*
+ * Configure on-board RTC
+ */
+#define CONFIG_SYS_RTC_BUS_NUM  0x01
+#define CONFIG_SYS_I2C_RTC_ADDR 0x32
+#define CONFIG_RTC_RX8025
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_EEPROM		/* Store env in I2C EEPROM	*/
+#define CONFIG_ENV_SIZE		0x1000
+#define CONFIG_ENV_OFFSET       0x0000	/* environment starts here	*/
+
+#define CONFIG_LOADS_ECHO		/* echo on for serial download	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change	*/
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_DATE
+#undef CONFIG_CMD_FUSE
+#undef CONFIG_CMD_IDE
+#undef CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_ELF
+#define CONFIG_DOS_PARTITION
+
+/*
+ * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
+ * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set
+ * to 0xFFFF, watchdog timeouts after about 64s. For details refer
+ * to chapter 36 of the MPC5121e Reference Manual.
+ */
+/* #define CONFIG_WATCHDOG */		/* enable watchdog */
+#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
+
+ /*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+#ifdef CONFIG_CMD_KGDB
+# define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+# define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
+				 sizeof(CONFIG_SYS_PROMPT) + 16)
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS	32
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)	/* Linux initial memory map */
+
+/* Cache Configuration */
+#define CONFIG_SYS_DCACHE_SIZE		32768
+#define CONFIG_SYS_CACHELINE_SIZE	32
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CACHELINE_SHIFT	5
+#endif
+
+#define CONFIG_SYS_HID0_INIT	0x000000000
+#define CONFIG_SYS_HID0_FINAL	HID0_ENABLE_MACHINE_CHECK
+#define CONFIG_SYS_HID2		HID2_HBE
+
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_TIMESTAMP
+
+#define CONFIG_HOSTNAME		mecp512x
+#define CONFIG_BOOTFILE		"/tftpboot/mecp512x/uImage"
+#define CONFIG_ROOTPATH		"/tftpboot/mecp512x/target_root"
+
+#define CONFIG_LOADADDR		400000	/* def. location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY	5	/* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS			/* the boot command will set bootargs*/
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Welcome to MECP5123" \
+	"echo"
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"u-boot_addr_r=200000\0"					\
+	"kernel_addr_r=600000\0"					\
+	"fdt_addr_r=880000\0"						\
+	"ramdisk_addr_r=900000\0"					\
+	"u-boot_addr=FFF00000\0"					\
+	"kernel_addr=FFC40000\0"					\
+	"fdt_addr=FFEC0000\0"						\
+	"ramdisk_addr=FC040000\0"					\
+	"ramdiskfile=/tftpboot/mecp512x/uRamdisk\0"			\
+	"u-boot=/tftpboot/mecp512x/u-boot.bin\0"			\
+	"bootfile=/tftpboot/mecp512x/uImage\0"				\
+	"fdtfile=/tftpboot/mecp512x/mecp512x.dtb\0"			\
+	"rootpath=/tftpboot/mecp512x/target_root\n"	      		\
+	"netdev=eth0\0"							\
+	"consdev=ttyPSC0\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} "				\
+		"console=${consdev},${baudrate}\0"			\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
+		"tftp ${fdt_addr_r} ${fdtfile};"			\
+		"run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
+	"net_self=tftp ${kernel_addr_r} ${bootfile};"			\
+		"tftp ${ramdisk_addr_r} ${ramdiskfile};"		\
+		"tftp ${fdt_addr_r} ${fdtfile};"			\
+		"run ramargs addip addtty;"				\
+		"bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
+	"load=tftp ${u-boot_addr_r} ${u-boot}\0"			\
+	"update=protect off ${u-boot_addr} +${filesize};"		\
+		"era ${u-boot_addr} +${filesize};"			\
+		"cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0"	\
+	"upd=run load update\0"						\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+
+#define OF_CPU			"PowerPC,5121@0"
+#define OF_SOC_COMPAT		"fsl,mpc5121-immr"
+#define OF_TBCLK		(bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH		"/soc@80000000/serial@11300"
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/mecp5200.h b/qemu/roms/u-boot/include/configs/mecp5200.h
new file mode 100644
index 000000000..b270429dd
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/mecp5200.h
@@ -0,0 +1,319 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+
+/*************************************************************************
+ * (c) 2005 esd gmbh Hannover
+ *
+ *
+ * from IceCube.h file
+ * by Reinhard Arlt reinhard.arlt@esd-electronics.com
+ *
+ *************************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5200		1	/* This is an MPC5200 CPU */
+#define CONFIG_ICECUBE		1	/* ... on IceCube board */
+#define CONFIG_MECP5200		1	/* ... on MECP5200  board */
+#define CONFIG_MPC5200_DDR      1       /* ... use DDR RAM      */
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xFFF00000
+#endif
+
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
+
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
+#if 0 /* test-only */
+#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
+#else
+#define CONFIG_BAUDRATE		9600	/* ... at 115200 bps */
+#endif
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#define CONFIG_MII
+#if 0 /* test-only !!! */
+#define CONFIG_EEPRO100		1
+#define CONFIG_SYS_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
+#define CONFIG_NS8382X		1
+#endif
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+/* USB */
+#if 0
+#define CONFIG_USB_OHCI
+#define CONFIG_USB_STORAGE
+#endif
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_ELF
+
+
+#if (CONFIG_SYS_TEXT_BASE == 0xFF000000)		/* Boot low with 16 MB Flash */
+#   define CONFIG_SYS_LOWBOOT		1
+#   define CONFIG_SYS_LOWBOOT16	1
+#endif
+#if (CONFIG_SYS_TEXT_BASE == 0xFF800000)		/* Boot low with  8 MB Flash */
+#   define CONFIG_SYS_LOWBOOT		1
+#   define CONFIG_SYS_LOWBOOT08	1
+#endif
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	3	/* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Welcome to CBX-CPU5200 (mecp5200);" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS \
+	"netdev=eth0\0" \
+	"flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
+	"flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
+	"net_vxworks=tftp $(loadaddr) $(image);run vxworks_args;bootvx\0" \
+	"vxworks_args=setenv bootargs fec(0,0)$(host):$(image) h=$(serverip) e=$(ipaddr) g=$(gatewayip) u=$(user) $(pass) tn=$(target) s=$(script)\0" \
+	"ata_vxworks_args=setenv bootargs /ata0/vxWorks h=$(serverip) e=$(ipaddr) g=$(gatewayip) u=$(user) $(pass) tn=$(target) s=$(script) o=fec0 \0" \
+	"loadaddr=01000000\0" \
+	"serverip=192.168.2.99\0" \
+	"gatewayip=10.0.0.79\0" \
+	"user=mu\0" \
+	"target=mecp5200.esd\0" \
+	"script=mecp5200.bat\0" \
+	"image=/tftpboot/vxWorks_mecp5200\0" \
+	"ipaddr=10.0.13.196\0" \
+	"netmask=255.255.0.0\0" \
+	""
+
+#define CONFIG_BOOTCOMMAND	"run flash_vxworks0"
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#undef CONFIG_SYS_IPBSPEED_133			/* define for 133MHz speed */
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #1 or #2 */
+
+#define CONFIG_SYS_I2C_SPEED		86000 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	20
+#define CONFIG_SYS_I2C_MULTI_EEPROMS		1
+/*
+ * Flash configuration
+ */
+#define CONFIG_SYS_FLASH_BASE		0xFFC00000
+#define CONFIG_SYS_FLASH_SIZE		0x00400000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x003E0000)
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks      */
+#define CONFIG_SYS_MAX_FLASH_SECT	512
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
+
+/*
+ * Environment settings
+ */
+#if 1 /* test-only */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_SIZE		0x10000
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#define CONFIG_ENV_OVERWRITE	1
+#else
+#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CONFIG_ENV_OFFSET		0x0000	/* environment starts at the beginning of the EEPROM */
+#define CONFIG_ENV_SIZE		0x0400	/* 8192 bytes may be used for env vars*/
+				   /* total size of a CAT24WC32 is 8192 bytes */
+#define CONFIG_ENV_OVERWRITE	1
+#endif
+
+#define CONFIG_FLASH_CFI_DRIVER	1	   /* Flash is CFI conformant		*/
+#define CONFIG_SYS_FLASH_CFI		1	   /* Flash is CFI conformant		*/
+#define CONFIG_SYS_FLASH_PROTECTION	1	   /* use hardware protection		*/
+#if 0
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1       /* use buffered writes (20x faster)  */
+#endif
+#define CONFIG_SYS_FLASH_INCREMENT	0x00400000 /* size of  flash bank		*/
+#define CONFIG_SYS_FLASH_BANKS_LIST  { CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_FLASH_EMPTY_INFO	1	   /* show if bank is empty		*/
+
+
+/*
+ * Memory map
+ */
+#define CONFIG_SYS_MBAR		0xF0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
+
+/* Use SRAM until RAM will be available */
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */
+
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC	1
+#define CONFIG_MPC5xxx_FEC_MII100
+/*
+ * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
+ */
+/* #define CONFIG_MPC5xxx_FEC_MII10 */
+#define CONFIG_PHY_ADDR		0x00
+#define CONFIG_UDP_CHECKSUM     1
+
+
+/*
+ * GPIO configuration
+ */
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x01052444
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
+
+#define CONFIG_SYS_VXWORKS_MAC_PTR	0x00000000	/* Pass Ethernet MAC to VxWorks */
+
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*
+ * Various low-level settings
+ */
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
+
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_CFG		0x00085d00
+
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
+
+#define CONFIG_SYS_CS1_START		0xfd000000
+#define CONFIG_SYS_CS1_SIZE		0x00010000
+#define CONFIG_SYS_CS1_CFG		0x10101410
+
+#define CONFIG_SYS_CS_BURST		0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE	0x33333333
+
+#define CONFIG_SYS_RESET_ADDRESS	0xff000000
+
+/*-----------------------------------------------------------------------
+ * USB stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_USB_CLOCK	0x0001BBBB
+#define CONFIG_USB_CONFIG	0x00001000
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+
+#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+
+#define	CONFIG_IDE_RESET		/* reset for ide supported	*/
+#define CONFIG_IDE_PREINIT
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
+
+/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
+
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)
+
+/* Interval between registers		*/
+#define CONFIG_SYS_ATA_STRIDE		4
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/medcom-wide.h b/qemu/roms/u-boot/include/configs/medcom-wide.h
new file mode 100644
index 000000000..40155c379
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/medcom-wide.h
@@ -0,0 +1,72 @@
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *  (C) Copyright 2011-2012
+ *  Avionic Design GmbH <www.avionic-design.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "tegra20-common.h"
+
+/* Enable fdt support for Medcom-Wide. Flash the image in u-boot-dtb.bin */
+#define CONFIG_DEFAULT_DEVICE_TREE	tegra20-medcom-wide
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
+/* High-level configuration options */
+#define V_PROMPT			"Tegra20 (Medcom-Wide) # "
+#define CONFIG_TEGRA_BOARD_STRING	"Avionic Design Medcom-Wide"
+
+/* Board-specific serial config */
+#define CONFIG_TEGRA_ENABLE_UARTD	/* UARTD: debug UART */
+#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_TEGRA_MMC
+#define CONFIG_CMD_MMC
+
+/* NAND support */
+#define CONFIG_CMD_NAND
+#define CONFIG_TEGRA_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+
+/* Environment in NAND, aligned to start of last sector */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		(SZ_512M - SZ_128K) /* 128K sectors */
+
+/* USB host support */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_TEGRA
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB
+
+/* USB networking support */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_SMSC95XX
+
+/* General networking support */
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+
+/* LCD support */
+#define CONFIG_LCD
+#define CONFIG_PWM_TEGRA
+#define CONFIG_VIDEO_TEGRA
+#define LCD_BPP LCD_COLOR16
+#define CONFIG_SYS_WHITE_ON_BLACK
+
+/* support the new (FDT-based) image format */
+#define CONFIG_FIT
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/meesc.h b/qemu/roms/u-boot/include/configs/meesc.h
new file mode 100644
index 000000000..86ce5f239
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/meesc.h
@@ -0,0 +1,206 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * (C) Copyright 2009-2011
+ * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
+ * esd electronic system design gmbh <www.esd.eu>
+ *
+ * Configuation settings for the esd MEESC board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * SoC must be defined first, before hardware.h is included.
+ * In this case SoC is defined in boards.cfg.
+ */
+#include <asm/hardware.h>
+
+/*
+ * Warning: changing CONFIG_SYS_TEXT_BASE requires
+ * adapting the initial boot program.
+ * Since the linker has to swallow that define, we must use a pure
+ * hex number here!
+ */
+#define CONFIG_SYS_TEXT_BASE		0x20002000
+
+/*
+ * since a number of boards are not being listed in linux
+ * arch/arm/tools/mach-types any more, the mach-types have to be
+ * defined here
+ */
+#define MACH_TYPE_MEESC			2165
+#define MACH_TYPE_ETHERCAN2		2407
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768	/* 32.768 kHz crystal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	16000000/* 16.0 MHz crystal */
+
+/* Misc CPU related */
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_BOARD_EARLY_INIT_F		/* call board_early_init_f() */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_SERIAL_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
+#define CONFIG_MISC_INIT_R			/* Call misc_init_r */
+
+#define CONFIG_DISPLAY_BOARDINFO		/* call checkboard() */
+#define CONFIG_DISPLAY_CPUINFO			/* display cpu info and speed */
+#define CONFIG_PREBOOT				/* enable preboot variable */
+
+/*
+ * Hardware drivers
+ */
+
+/* required until arch/arm/include/asm/arch-at91/at91sam9263.h is reworked */
+#define ATMEL_PMC_UHP			AT91SAM926x_PMC_UHP
+
+/* general purpose I/O */
+#define CONFIG_AT91_GPIO
+
+/* Console output */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
+#define CONFIG_USART_ID			ATMEL_ID_SYS
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_USB
+
+/* LED */
+#define CONFIG_AT91_LED
+
+/*
+ * SDRAM: 1 bank, min 32, max 128 MB
+ * Initialized before u-boot gets started.
+ */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE		0x20000000 /* ATMEL_BASE_CS1 */
+#define CONFIG_SYS_SDRAM_SIZE		0x02000000
+
+#define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE + 0x00100000)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x01E00000)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x00100000)
+
+/*
+ * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
+ * leaving the correct space for initial global data structure above
+ * that address while providing maximum stack area below.
+ */
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(ATMEL_BASE_SRAM0 + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+/* DataFlash */
+#ifdef CONFIG_SYS_USE_DATAFLASH
+# define CONFIG_ATMEL_DATAFLASH_SPI
+# define CONFIG_HAS_DATAFLASH
+# define CONFIG_SYS_SPI_WRITE_TOUT		(5 * CONFIG_SYS_HZ)
+# define CONFIG_SYS_MAX_DATAFLASH_BANKS		1
+# define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
+# define AT91_SPI_CLK				15000000
+# define DATAFLASH_TCSS				(0x1a << 16)
+# define DATAFLASH_TCHS				(0x1 << 24)
+#endif
+
+/* NOR flash is not populated, disable it */
+#define CONFIG_SYS_NO_FLASH
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+# define CONFIG_NAND_ATMEL
+# define CONFIG_SYS_MAX_NAND_DEVICE		1
+# define CONFIG_SYS_NAND_BASE			0x40000000 /* ATMEL_BASE_CS3 */
+# define CONFIG_SYS_NAND_DBW_8
+# define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
+# define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
+# define CONFIG_SYS_NAND_ENABLE_PIN		GPIO_PIN_PD(15)
+# define CONFIG_SYS_NAND_READY_PIN		GPIO_PIN_PA(22)
+#endif
+
+/* Ethernet */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_FIT
+#define CONFIG_NET_RETRY_COUNT			20
+#undef CONFIG_RESET_PHY_R
+
+/* USB */
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00a00000
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9263"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+
+/* CAN */
+#define CONFIG_AT91_CAN
+
+/* hw-controller addresses */
+#define CONFIG_ET1100_BASE		0x70000000
+
+#ifdef CONFIG_SYS_USE_DATAFLASH
+
+/* bootstrap + u-boot + env in dataflash on CS0 */
+# define CONFIG_ENV_IS_IN_DATAFLASH
+# define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \
+					0x8400)
+# define CONFIG_ENV_OFFSET		0x4200
+# define CONFIG_ENV_ADDR		(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \
+					CONFIG_ENV_OFFSET)
+# define CONFIG_ENV_SIZE		0x4200
+
+#elif CONFIG_SYS_USE_NANDFLASH
+
+/* bootstrap + u-boot + env + linux in nandflash */
+# define CONFIG_ENV_IS_IN_NAND		1
+# define CONFIG_ENV_OFFSET		0xC0000
+# define CONFIG_ENV_SIZE		0x20000
+
+#endif
+
+#define CONFIG_SYS_CBSIZE		512
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + \
+					128*1024, 0x1000)
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/microblaze-generic.h b/qemu/roms/u-boot/include/configs/microblaze-generic.h
new file mode 100644
index 000000000..06b7e9418
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/microblaze-generic.h
@@ -0,0 +1,510 @@
+/*
+ * (C) Copyright 2007-2010 Michal Simek
+ *
+ * Michal SIMEK <monstr@monstr.eu>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "../board/xilinx/microblaze-generic/xparameters.h"
+
+/* MicroBlaze CPU */
+#define	CONFIG_MICROBLAZE	1
+#define	MICROBLAZE_V5		1
+
+/* Open Firmware DTS */
+#define CONFIG_OF_CONTROL	1
+#define CONFIG_OF_EMBED		1
+#define CONFIG_DEFAULT_DEVICE_TREE microblaze-generic
+
+/* linear and spi flash memory */
+#ifdef XILINX_FLASH_START
+#define	FLASH
+#undef	SPIFLASH
+#undef	RAMENV	/* hold environment in flash */
+#else
+#ifdef XILINX_SPI_FLASH_BASEADDR
+#undef	FLASH
+#define	SPIFLASH
+#undef	RAMENV	/* hold environment in flash */
+#else
+#undef	FLASH
+#undef	SPIFLASH
+#define	RAMENV	/* hold environment in RAM */
+#endif
+#endif
+
+/* uart */
+#ifdef XILINX_UARTLITE_BASEADDR
+# define CONFIG_XILINX_UARTLITE
+# define CONFIG_SERIAL_BASE	XILINX_UARTLITE_BASEADDR
+# define CONFIG_BAUDRATE	XILINX_UARTLITE_BAUDRATE
+# define CONFIG_SYS_BAUDRATE_TABLE	{ CONFIG_BAUDRATE }
+# define CONSOLE_ARG	"console=console=ttyUL0,115200\0"
+#elif XILINX_UART16550_BASEADDR
+# define CONFIG_SYS_NS16550		1
+# define CONFIG_SYS_NS16550_SERIAL
+# if defined(__MICROBLAZEEL__)
+#  define CONFIG_SYS_NS16550_REG_SIZE	-4
+# else
+#  define CONFIG_SYS_NS16550_REG_SIZE	4
+# endif
+# define CONFIG_CONS_INDEX		1
+# define CONFIG_SYS_NS16550_COM1 \
+		((XILINX_UART16550_BASEADDR & ~0xF) + 0x1000)
+# define CONFIG_SYS_NS16550_CLK	XILINX_UART16550_CLOCK_HZ
+# define CONFIG_BAUDRATE	115200
+
+/* The following table includes the supported baudrates */
+# define CONFIG_SYS_BAUDRATE_TABLE \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+# define CONSOLE_ARG	"console=console=ttyS0,115200\0"
+#else
+# error Undefined uart
+#endif
+
+/* setting reset address */
+/*#define	CONFIG_SYS_RESET_ADDRESS	CONFIG_SYS_TEXT_BASE*/
+
+/* ethernet */
+#undef CONFIG_SYS_ENET
+#if defined(XILINX_EMACLITE_BASEADDR) || defined(CONFIG_OF_CONTROL)
+# define CONFIG_XILINX_EMACLITE	1
+# define CONFIG_SYS_ENET
+#endif
+#if defined(XILINX_LLTEMAC_BASEADDR)
+# define CONFIG_XILINX_LL_TEMAC	1
+# define CONFIG_SYS_ENET
+#endif
+#if defined(XILINX_AXIEMAC_BASEADDR)
+# define CONFIG_XILINX_AXIEMAC	1
+# define CONFIG_SYS_ENET
+#endif
+
+#undef ET_DEBUG
+
+/* gpio */
+#ifdef XILINX_GPIO_BASEADDR
+# define CONFIG_XILINX_GPIO
+# define CONFIG_SYS_GPIO_0_ADDR		XILINX_GPIO_BASEADDR
+#endif
+
+/* interrupt controller */
+#ifdef XILINX_INTC_BASEADDR
+# define CONFIG_SYS_INTC_0_ADDR		XILINX_INTC_BASEADDR
+# define CONFIG_SYS_INTC_0_NUM		XILINX_INTC_NUM_INTR_INPUTS
+#endif
+
+/* timer */
+#if defined(XILINX_TIMER_BASEADDR) && defined(XILINX_TIMER_IRQ)
+#  define CONFIG_SYS_TIMER_0_ADDR	XILINX_TIMER_BASEADDR
+#  define CONFIG_SYS_TIMER_0_IRQ	XILINX_TIMER_IRQ
+#endif
+
+/* watchdog */
+#if defined(XILINX_WATCHDOG_BASEADDR) && defined(XILINX_WATCHDOG_IRQ)
+# define CONFIG_WATCHDOG_BASEADDR	XILINX_WATCHDOG_BASEADDR
+# define CONFIG_WATCHDOG_IRQ		XILINX_WATCHDOG_IRQ
+# define CONFIG_HW_WATCHDOG
+# define CONFIG_XILINX_TB_WATCHDOG
+#endif
+
+/*
+ * memory layout - Example
+ * CONFIG_SYS_TEXT_BASE = 0x1200_0000;	defined in config.mk
+ * CONFIG_SYS_SRAM_BASE = 0x1000_0000;
+ * CONFIG_SYS_SRAM_SIZE = 0x0400_0000;	64MB
+ *
+ * CONFIG_SYS_MONITOR_LEN = 0x40000
+ * CONFIG_SYS_MALLOC_LEN = 3 * CONFIG_SYS_MONITOR_LEN = 0xC0000
+ *
+ * CONFIG_SYS_GBL_DATA_OFFSET = 0x1000_0000 + 0x0400_0000 - 0x1000 = 0x13FF_F000
+ * CONFIG_SYS_MONITOR_BASE = 0x13FF_F000 - CONFIG_SYS_MONITOR_LEN = 0x13FB_F000
+ * CONFIG_SYS_MALLOC_BASE = 0x13FB_F000 - CONFIG_SYS_MALLOC_LEN = 0x13EF_F000
+ *
+ * 0x1000_0000	CONFIG_SYS_SDRAM_BASE
+ *					MEMTEST_AREA	 64kB
+ *					FREE
+ * 0x1200_0000	CONFIG_SYS_TEXT_BASE
+ *		U-BOOT code
+ * 0x1202_0000
+ *					FREE
+ *
+ *					STACK
+ * 0x13EF_F000	CONFIG_SYS_MALLOC_BASE
+ *					MALLOC_AREA	768kB	Alloc
+ * 0x13FB_F000	CONFIG_SYS_MONITOR_BASE
+ *					MONITOR_CODE	256kB	Env
+ * 0x13FF_F000	CONFIG_SYS_GBL_DATA_OFFSET
+ *					GLOBAL_DATA	4kB	bd, gd
+ * 0x1400_0000	CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE
+ */
+
+/* ddr sdram - main memory */
+#define	CONFIG_SYS_SDRAM_BASE		XILINX_RAM_START
+#define	CONFIG_SYS_SDRAM_SIZE		XILINX_RAM_SIZE
+#define	CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define	CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x1000)
+
+/* global pointer */
+/* start of global data */
+#define	CONFIG_SYS_GBL_DATA_OFFSET \
+		(CONFIG_SYS_SDRAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+/* monitor code */
+#define	SIZE				0x40000
+#define	CONFIG_SYS_MONITOR_LEN		SIZE
+#define	CONFIG_SYS_MONITOR_BASE	\
+		(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET \
+			- CONFIG_SYS_MONITOR_LEN - GENERATED_BD_INFO_SIZE)
+#define	CONFIG_SYS_MONITOR_END \
+			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define	CONFIG_SYS_MALLOC_LEN		(SIZE * 3)
+#define	CONFIG_SYS_MALLOC_BASE \
+			(CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
+
+/* stack */
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_MALLOC_BASE
+
+/*
+ * CFI flash memory layout - Example
+ * CONFIG_SYS_FLASH_BASE = 0x2200_0000;
+ * CONFIG_SYS_FLASH_SIZE = 0x0080_0000;	  8MB
+ *
+ * SECT_SIZE = 0x20000;			128kB is one sector
+ * CONFIG_ENV_SIZE = SECT_SIZE;		128kB environment store
+ *
+ * 0x2200_0000	CONFIG_SYS_FLASH_BASE
+ *					FREE		256kB
+ * 0x2204_0000	CONFIG_ENV_ADDR
+ *					ENV_AREA	128kB
+ * 0x2206_0000
+ *					FREE
+ * 0x2280_0000	CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE
+ *
+ */
+
+#ifdef FLASH
+# define CONFIG_SYS_FLASH_BASE		XILINX_FLASH_START
+# define CONFIG_SYS_FLASH_SIZE		XILINX_FLASH_SIZE
+# define CONFIG_SYS_FLASH_CFI		1
+# define CONFIG_FLASH_CFI_DRIVER	1
+/* ?empty sector */
+# define CONFIG_SYS_FLASH_EMPTY_INFO	1
+/* max number of memory banks */
+# define CONFIG_SYS_MAX_FLASH_BANKS	1
+/* max number of sectors on one chip */
+# define CONFIG_SYS_MAX_FLASH_SECT	512
+/* hardware flash protection */
+# define CONFIG_SYS_FLASH_PROTECTION
+/* use buffered writes (20x faster) */
+# define	CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+# ifdef	RAMENV
+#  define CONFIG_ENV_IS_NOWHERE	1
+#  define CONFIG_ENV_SIZE	0x1000
+#  define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
+
+# else	/* FLASH && !RAMENV */
+#  define CONFIG_ENV_IS_IN_FLASH	1
+/* 128K(one sector) for env */
+#  define CONFIG_ENV_SECT_SIZE	0x20000
+#  define CONFIG_ENV_ADDR \
+			(CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
+#  define CONFIG_ENV_SIZE	0x20000
+# endif /* FLASH && !RAMBOOT */
+#else /* !FLASH */
+
+#ifdef SPIFLASH
+# define CONFIG_SYS_NO_FLASH		1
+# define CONFIG_SYS_SPI_BASE		XILINX_SPI_FLASH_BASEADDR
+# define CONFIG_XILINX_SPI		1
+# define CONFIG_SPI			1
+# define CONFIG_SPI_FLASH		1
+# define CONFIG_SPI_FLASH_STMICRO	1
+# define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3
+# define CONFIG_SF_DEFAULT_SPEED	XILINX_SPI_FLASH_MAX_FREQ
+# define CONFIG_SF_DEFAULT_CS		XILINX_SPI_FLASH_CS
+
+# ifdef	RAMENV
+#  define CONFIG_ENV_IS_NOWHERE	1
+#  define CONFIG_ENV_SIZE	0x1000
+#  define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
+
+# else	/* SPIFLASH && !RAMENV */
+#  define CONFIG_ENV_IS_IN_SPI_FLASH	1
+#  define CONFIG_ENV_SPI_MODE		SPI_MODE_3
+#  define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
+#  define CONFIG_ENV_SPI_CS		CONFIG_SF_DEFAULT_CS
+/* 128K(two sectors) for env */
+#  define CONFIG_ENV_SECT_SIZE	0x10000
+#  define CONFIG_ENV_SIZE	(2 * CONFIG_ENV_SECT_SIZE)
+/* Warning: adjust the offset in respect of other flash content and size */
+#  define CONFIG_ENV_OFFSET	(128 * CONFIG_ENV_SECT_SIZE) /* at 8MB */
+# endif /* SPIFLASH && !RAMBOOT */
+#else /* !SPIFLASH */
+
+/* ENV in RAM */
+# define CONFIG_SYS_NO_FLASH	1
+# define CONFIG_ENV_IS_NOWHERE	1
+# define CONFIG_ENV_SIZE	0x1000
+# define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
+#endif /* !SPIFLASH */
+#endif /* !FLASH */
+
+/* system ace */
+#ifdef XILINX_SYSACE_BASEADDR
+# define CONFIG_SYSTEMACE
+/* #define DEBUG_SYSTEMACE */
+# define SYSTEMACE_CONFIG_FPGA
+# define CONFIG_SYS_SYSTEMACE_BASE	XILINX_SYSACE_BASEADDR
+# define CONFIG_SYS_SYSTEMACE_WIDTH	XILINX_SYSACE_MEM_WIDTH
+# define CONFIG_DOS_PARTITION
+#endif
+
+#if defined(XILINX_USE_ICACHE)
+# define CONFIG_ICACHE
+#else
+# undef CONFIG_ICACHE
+#endif
+
+#if defined(XILINX_USE_DCACHE)
+# define CONFIG_DCACHE
+#else
+# undef CONFIG_DCACHE
+#endif
+
+#ifndef XILINX_DCACHE_BYTE_SIZE
+#define XILINX_DCACHE_BYTE_SIZE	32768
+#endif
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MFSL
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_GPIO
+
+#if defined(CONFIG_DCACHE) || defined(CONFIG_ICACHE)
+# define CONFIG_CMD_CACHE
+#else
+# undef CONFIG_CMD_CACHE
+#endif
+
+#ifndef CONFIG_SYS_ENET
+# undef CONFIG_CMD_NET
+# undef CONFIG_CMD_NFS
+#else
+# define CONFIG_CMD_PING
+# define CONFIG_CMD_DHCP
+# define CONFIG_CMD_TFTPPUT
+#endif
+
+#if defined(CONFIG_SYSTEMACE)
+# define CONFIG_CMD_EXT2
+# define CONFIG_CMD_FAT
+#endif
+
+#if defined(FLASH)
+# define CONFIG_CMD_ECHO
+# define CONFIG_CMD_FLASH
+# define CONFIG_CMD_IMLS
+# define CONFIG_CMD_JFFS2
+# define CONFIG_CMD_UBI
+# undef CONFIG_CMD_UBIFS
+
+# if !defined(RAMENV)
+#  define CONFIG_CMD_SAVEENV
+#  define CONFIG_CMD_SAVES
+# endif
+
+#else
+#if defined(SPIFLASH)
+# define CONFIG_CMD_SF
+
+# if !defined(RAMENV)
+#  define CONFIG_CMD_SAVEENV
+#  define CONFIG_CMD_SAVES
+# endif
+#else
+# undef CONFIG_CMD_IMLS
+# undef CONFIG_CMD_FLASH
+# undef CONFIG_CMD_JFFS2
+# undef CONFIG_CMD_UBI
+# undef CONFIG_CMD_UBIFS
+#endif
+#endif
+
+#if defined(CONFIG_CMD_JFFS2)
+# define CONFIG_MTD_PARTITIONS
+#endif
+
+#if defined(CONFIG_CMD_UBIFS)
+# define CONFIG_CMD_UBI
+# define CONFIG_LZO
+#endif
+
+#if defined(CONFIG_CMD_UBI)
+# define CONFIG_MTD_PARTITIONS
+# define CONFIG_RBTREE
+#endif
+
+#if defined(CONFIG_MTD_PARTITIONS)
+/* MTD partitions */
+#define CONFIG_CMD_MTDPARTS	/* mtdparts command line support */
+#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
+#define MTDIDS_DEFAULT		"nor0=flash-0"
+
+/* default mtd partition table */
+#define MTDPARTS_DEFAULT	"mtdparts=flash-0:256k(u-boot),"\
+				"256k(env),3m(kernel),1m(romfs),"\
+				"1m(cramfs),-(jffs2)"
+#endif
+
+/* Miscellaneous configurable options */
+#define	CONFIG_SYS_PROMPT	"U-Boot-mONStR> "
+/* size of console buffer */
+#define	CONFIG_SYS_CBSIZE	512
+ /* print buffer size */
+#define	CONFIG_SYS_PBSIZE \
+		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+/* max number of command args */
+#define	CONFIG_SYS_MAXARGS	15
+#define	CONFIG_SYS_LONGHELP
+/* default load address */
+#define	CONFIG_SYS_LOAD_ADDR	XILINX_RAM_START
+
+#define	CONFIG_BOOTDELAY	-1	/* -1 disables auto-boot */
+#define	CONFIG_BOOTARGS		"root=romfs"
+#define	CONFIG_HOSTNAME		XILINX_BOARD_NAME
+#define	CONFIG_BOOTCOMMAND	"base 0;tftp 11000000 image.img;bootm"
+#define	CONFIG_IPADDR		192.168.0.3
+#define	CONFIG_SERVERIP		192.168.0.5
+#define	CONFIG_GATEWAYIP	192.168.0.1
+#define	CONFIG_ETHADDR		00:E0:0C:00:00:FD
+
+/* architecture dependent code */
+#define	CONFIG_SYS_USR_EXCEP	/* user exception */
+
+#define	CONFIG_PREBOOT	"echo U-BOOT for ${hostname};setenv preboot;echo"
+
+#define	CONFIG_EXTRA_ENV_SETTINGS	"unlock=yes\0" \
+					"nor0=flash-0\0"\
+					"mtdparts=mtdparts=flash-0:"\
+					"256k(u-boot),256k(env),3m(kernel),"\
+					"1m(romfs),1m(cramfs),-(jffs2)\0"\
+					"nc=setenv stdout nc;"\
+					"setenv stdin nc\0" \
+					"serial=setenv stdout serial;"\
+					"setenv stdin serial\0"
+
+#define CONFIG_CMDLINE_EDITING
+
+#define CONFIG_NETCONSOLE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+/* Enable flat device tree support */
+#define CONFIG_LMB		1
+#define CONFIG_FIT		1
+#define CONFIG_OF_LIBFDT	1
+
+#if defined(CONFIG_XILINX_LL_TEMAC) || defined(CONFIG_XILINX_AXIEMAC)
+# define CONFIG_MII		1
+# define CONFIG_CMD_MII		1
+# define CONFIG_PHY_GIGE	1
+# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	1
+# define CONFIG_PHYLIB		1
+# define CONFIG_PHY_ATHEROS	1
+# define CONFIG_PHY_BROADCOM	1
+# define CONFIG_PHY_DAVICOM	1
+# define CONFIG_PHY_LXT		1
+# define CONFIG_PHY_MARVELL	1
+# define CONFIG_PHY_MICREL	1
+# define CONFIG_PHY_NATSEMI	1
+# define CONFIG_PHY_REALTEK	1
+# define CONFIG_PHY_VITESSE	1
+#else
+# undef CONFIG_MII
+# undef CONFIG_CMD_MII
+# undef CONFIG_PHYLIB
+#endif
+
+/* SPL part */
+#define CONFIG_SPL
+#define CONFIG_CMD_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_BOARD_INIT
+
+#define CONFIG_SPL_LDSCRIPT	"arch/microblaze/cpu/u-boot-spl.lds"
+
+#define CONFIG_SPL_RAM_DEVICE
+#define CONFIG_SPL_NOR_SUPPORT
+
+/* for booting directly linux */
+#define CONFIG_SPL_OS_BOOT
+
+#define CONFIG_SYS_OS_BASE		(CONFIG_SYS_FLASH_BASE + \
+					 0x60000)
+#define CONFIG_SYS_FDT_BASE		(CONFIG_SYS_FLASH_BASE + \
+					 0x40000)
+#define CONFIG_SYS_SPL_ARGS_ADDR	(CONFIG_SYS_TEXT_BASE + \
+					 0x1000000)
+
+/* SP location before relocation, must use scratch RAM */
+/* BRAM start */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x0
+/* BRAM size - will be generated */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x10000
+/* Stack pointer prior relocation, must situated at on-chip RAM */
+#define CONFIG_SYS_SPL_MALLOC_END	(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100
+
+/*
+ * The main reason to do it in this way is that MALLOC_START
+ * can't be defined - common/spl/spl.c
+ */
+#if (CONFIG_SYS_SPL_MALLOC_SIZE != 0)
+# define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_SPL_MALLOC_END - \
+					 CONFIG_SYS_SPL_MALLOC_SIZE)
+# define CONFIG_SPL_STACK_ADDR		CONFIG_SYS_SPL_MALLOC_START
+#else
+# define CONFIG_SPL_STACK_ADDR		CONFIG_SYS_SPL_MALLOC_END
+#endif
+
+/* Just for sure that there is a space for stack */
+#define CONFIG_SPL_STACK_SIZE		0x100
+
+#define CONFIG_SYS_UBOOT_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_UBOOT_START		CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SPL_MAX_FOOTPRINT	(CONFIG_SYS_INIT_RAM_SIZE - \
+					 CONFIG_SYS_INIT_RAM_ADDR - \
+					 GENERATED_GBL_DATA_SIZE - \
+					 CONFIG_SYS_SPL_MALLOC_SIZE - \
+					 CONFIG_SPL_STACK_SIZE)
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/mimc200.h b/qemu/roms/u-boot/include/configs/mimc200.h
new file mode 100644
index 000000000..fc7ecfaee
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/mimc200.h
@@ -0,0 +1,178 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * Configuration settings for the AVR32 Network Gateway
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/hardware.h>
+
+#define CONFIG_AT32AP
+#define CONFIG_AT32AP7000
+#define CONFIG_MIMC200
+
+#define CONFIG_MIMC200_EXT_FLASH
+
+/*
+ * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
+ * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
+ * and the PBA bus to run at 1/4 the PLL frequency.
+ */
+#define CONFIG_PLL
+#define CONFIG_SYS_POWER_MANAGER
+#define CONFIG_SYS_OSC0_HZ			10000000
+#define CONFIG_SYS_PLL0_DIV			1
+#define CONFIG_SYS_PLL0_MUL			15
+#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES	16
+#define CONFIG_SYS_CLKDIV_CPU			0
+#define CONFIG_SYS_CLKDIV_HSB			1
+#define CONFIG_SYS_CLKDIV_PBA			2
+#define CONFIG_SYS_CLKDIV_PBB			1
+
+/* Reserve VM regions for SDRAM, NOR flash and FRAM */
+#define CONFIG_SYS_NR_VM_REGIONS		3
+
+/*
+ * The PLLOPT register controls the PLL like this:
+ *   icp = PLLOPT<2>
+ *   ivco = PLLOPT<1:0>
+ *
+ * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
+ */
+#define CONFIG_SYS_PLL0_OPT			0x04
+
+#define CONFIG_USART_BASE			ATMEL_BASE_USART1
+#define CONFIG_USART_ID				1
+
+#define CONFIG_MIMC200_DBGLINK		1
+
+/* User serviceable stuff */
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#define CONFIG_STACKSIZE		(2048)
+
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_BOOTARGS							\
+	"root=/dev/mtdblock1 rootfstype=jffs2 fbmem=512k console=ttyS1"
+#define CONFIG_BOOTCOMMAND						\
+	"fsload boot/uImage; bootm"
+
+#define CONFIG_SILENT_CONSOLE       /* enable silent startup */
+#define CONFIG_DISABLE_CONSOLE      /* disable console */
+#define CONFIG_SYS_DEVICE_NULLDEV   /* include nulldev device */
+
+#define CONFIG_LCD			1
+
+/*
+ * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
+ * data on the serial line may interrupt the boot sequence.
+ */
+#define CONFIG_BOOTDELAY		0
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define CONFIG_AUTOBOOT
+
+/*
+ * After booting the board for the first time, new ethernet addresses
+ * should be generated and assigned to the environment variables
+ * "ethaddr" and "eth1addr". This is normally done during production.
+ */
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
+
+/*
+ * BOOTP/DHCP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NET
+
+#define CONFIG_ATMEL_USART
+#define CONFIG_MACB
+#define CONFIG_PORTMUX_PIO
+#define CONFIG_SYS_NR_PIOS			5
+#define CONFIG_SYS_HSDRAMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_ATMEL_MCI
+#define CONFIG_GENERIC_MMC
+
+#if defined(CONFIG_LCD)
+#define CONFIG_CMD_BMP
+#define CONFIG_ATMEL_LCD		1
+#define LCD_BPP				LCD_COLOR16
+#define CONFIG_BMP_16BPP		1
+#define CONFIG_FB_ADDR			0x10600000
+#define CONFIG_WHITE_ON_BLACK		1
+#define CONFIG_VIDEO_BMP_GZIP 		1
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE		262144
+#define CONFIG_ATMEL_LCD_BGR555		1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
+#define CONFIG_SPLASH_SCREEN		1
+#endif
+
+#define CONFIG_SYS_DCACHE_LINESZ		32
+#define CONFIG_SYS_ICACHE_LINESZ		32
+
+#define CONFIG_NR_DRAM_BANKS		1
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+
+#define CONFIG_SYS_FLASH_BASE			0x00000000
+#define CONFIG_SYS_FLASH_SIZE			0x800000
+#define CONFIG_SYS_MAX_FLASH_BANKS		1
+#define CONFIG_SYS_MAX_FLASH_SECT		135
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_TEXT_BASE		0x00000000
+
+#define CONFIG_SYS_INTRAM_BASE			INTERNAL_SRAM_BASE
+#define CONFIG_SYS_INTRAM_SIZE			INTERNAL_SRAM_SIZE
+#define CONFIG_SYS_SDRAM_BASE			EBI_SDRAM_BASE
+
+#define CONFIG_SYS_FRAM_BASE			0x08000000
+#define CONFIG_SYS_FRAM_SIZE			0x20000
+
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SIZE			65536
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
+
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
+
+#define CONFIG_SYS_MALLOC_LEN			(1024*1024)
+#define CONFIG_SYS_DMA_ALLOC_LEN		(16384)
+
+/* Allow 4MB for the kernel run-time image */
+#define CONFIG_SYS_LOAD_ADDR			(EBI_SDRAM_BASE + 0x00400000)
+#define CONFIG_SYS_BOOTPARAMS_LEN		(16 * 1024)
+
+/* Other configuration settings that shouldn't have to change all that often */
+#define CONFIG_SYS_PROMPT			"U-Boot> "
+#define CONFIG_SYS_CBSIZE			256
+#define CONFIG_SYS_MAXARGS			16
+#define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+
+#define CONFIG_SYS_MEMTEST_START		EBI_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END			(CONFIG_SYS_MEMTEST_START + 0x1f00000)
+
+#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/ml507.h b/qemu/roms/u-boot/include/configs/ml507.h
new file mode 100644
index 000000000..b9ecb091b
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/ml507.h
@@ -0,0 +1,39 @@
+/*
+ * (C) Copyright 2008
+ *  Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ *  This work has been supported by: QTechnology  http://qtec.com/
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*CPU*/
+#define CONFIG_440		1
+#define CONFIG_XILINX_ML507	1
+#include "../board/xilinx/ml507/xparameters.h"
+
+/*Mem Map*/
+#define CONFIG_SYS_SDRAM_SIZE_MB	256
+
+/*Env*/
+#define	CONFIG_ENV_IS_IN_FLASH	1
+#define	CONFIG_ENV_SIZE		0x20000
+#define	CONFIG_ENV_SECT_SIZE	0x20000
+#define CONFIG_ENV_OFFSET	0x340000
+#define CONFIG_ENV_ADDR		(XPAR_FLASH_MEM0_BASEADDR+CONFIG_ENV_OFFSET)
+
+/*Misc*/
+#define CONFIG_SYS_PROMPT	"ml507:/# "	/* Monitor Command Prompt    */
+#define CONFIG_PREBOOT		"echo U-Boot is up and runnining;"
+
+/*Flash*/
+#define	CONFIG_SYS_FLASH_SIZE	(32*1024*1024)
+#define	CONFIG_SYS_MAX_FLASH_SECT	259
+#define MTDIDS_DEFAULT		"nor0=ml507-flash"
+#define MTDPARTS_DEFAULT	"mtdparts=ml507-flash:-(user)"
+
+/*Generic Configs*/
+#include <configs/xilinx-ppc440.h>
+
+#endif						/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/motionpro.h b/qemu/roms/u-boot/include/configs/motionpro.h
new file mode 100644
index 000000000..e8b05932a
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/motionpro.h
@@ -0,0 +1,401 @@
+/*
+ * (C) Copyright 2003-2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Based on Motion-PRO board config file by Robert McCullough, rob@promessinc.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+
+/* CPU and board */
+#define CONFIG_MPC5200		1	/* This is a MPC5200 CPU */
+#define CONFIG_MOTIONPRO	1	/* ... on Promess Motion-PRO board */
+
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
+#define	CONFIG_SYS_TEXT_BASE	0xfff00000
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
+#define CONFIG_NETCONSOLE	1	/* network console */
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC	1
+#define CONFIG_MPC5xxx_FEC_MII100
+#define CONFIG_PHY_ADDR		0x2
+#define CONFIG_PHY_TYPE		0x79c874
+#define CONFIG_RESET_PHY_R	1
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	2	/* autoboot after 2 seconds */
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_STOP_STR	"\x1b\x1b"
+#define DEBUG_BOOTKEYS		0
+#undef CONFIG_AUTOBOOT_DELAY_STR
+#undef CONFIG_BOOTARGS
+#define CONFIG_AUTOBOOT_PROMPT	"Autobooting in %d seconds, "		\
+				"press \"<Esc><Esc>\" to stop\n", bootdelay
+
+#define CONFIG_CMDLINE_EDITING		1	/* add command line history	*/
+#define	CONFIG_SYS_HUSH_PARSER		1	/* use "hush" command parser	*/
+#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+
+#define CONFIG_ETHADDR		00:50:C2:40:10:00
+#define CONFIG_OVERWRITE_ETHADDR_ONCE	1
+#define CONFIG_VERSION_VARIABLE	1	/* include version env variable */
+
+/*
+ * Default environment settings
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"hostname=motionpro\0"						\
+	"netmask=255.255.255.0\0"					\
+	"ipaddr=192.168.1.106\0"					\
+	"serverip=192.168.1.100\0"					\
+	"gatewayip=192.168.1.100\0"					\
+	"console=ttyPSC0,115200\0"					\
+	"u-boot_addr=400000\0"						\
+	"kernel_addr=400000\0"						\
+	"fdt_addr=700000\0"						\
+	"ramdisk_addr=800000\0"						\
+	"multi_image_addr=800000\0"					\
+	"rootpath=/opt/eldk-4.2/ppc_6xx\0"				\
+	"u-boot=/tftpboot/motionpro/u-boot.bin\0"			\
+	"bootfile=/tftpboot/motionpro/uImage\0"				\
+	"fdt_file=/tftpboot/motionpro/motionpro.dtb\0"			\
+	"ramdisk_file=/tftpboot/motionpro/uRamdisk\0"			\
+	"multi_image_file=kernel+initrd+dtb.img\0"			\
+	"load=tftp ${u-boot_addr} ${u-boot}\0"				\
+	"update=prot off fff00000 +${filesize};"			\
+		"era fff00000 +${filesize}; "				\
+		"cp.b ${u-boot_addr} fff00000 ${filesize};"		\
+		"prot on fff00000 +${filesize}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"fat_args=setenv bootargs root=/dev/sda rw\0"			\
+	"mtdids=nor0=ff000000.flash\0"					\
+	"mtdparts=ff000000.flash:13m(fs),2m(kernel),384k(uboot)," 	\
+				"128k(env),128k(redund_env),"	  	\
+				"128k(dtb),128k(user_data)\0"		\
+	"addcons=setenv bootargs ${bootargs} console=${console}\0"	\
+	"addmtd=setenv bootargs ${bootargs} mtdparts=${mtdparts}\0"	\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:"		\
+		"${netmask}:${hostname}:${netdev}:off panic=1 "		\
+		"console=${console}\0"					\
+	"net_nfs=tftp ${kernel_addr} ${bootfile}; "			\
+		"tftp ${fdt_addr} ${fdt_file}; "			\
+		"run nfsargs addip addmtd; "				\
+		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
+	"net_self=tftp ${kernel_addr} ${bootfile}; "			\
+		"tftp ${fdt_addr} ${fdt_file}; "			\
+		"tftp ${ramdisk_addr} ${ramdisk_file}; "		\
+		"nfs ${ramdisk_addr} ${serverip}:${rootpath}/images/uRamdisk; "	\
+		"run ramargs addip addcons addmtd; "			\
+		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
+	"fat_multi=run fat_args addip addmtd; fatload ide 0:1 "		\
+		"${multi_image_addr} ${multi_image_file}; "		\
+		"bootm ${multi_image_addr}\0"				\
+	""
+#define CONFIG_BOOTCOMMAND	"run fat_multi"
+
+/*
+ * do board-specific init
+ */
+#define CONFIG_BOARD_EARLY_INIT_R	1
+
+/*
+ * Low level configuration
+ */
+
+/*
+ * Clock configuration: SYS_XTALIN = 33MHz
+ */
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000
+
+/*
+ * Set IPB speed to 100MHz
+ */
+#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK
+
+/*
+ * Memory map
+ */
+/*
+ * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000.
+ * Setting MBAR to otherwise will cause system hang when using SmartDMA such
+ * as network commands.
+ */
+#define CONFIG_SYS_MBAR			0xf0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+
+/*
+ * If building for running out of SDRAM, then MBAR has been set up beforehand
+ * (e.g., by the BDI). Otherwise we must specify the default boot-up value of
+ * MBAR, as given in the doccumentation.
+ */
+#if CONFIG_SYS_TEXT_BASE == 0x00100000
+#define CONFIG_SYS_DEFAULT_MBAR	0xf0000000
+#else /* CONFIG_SYS_TEXT_BASE != 0x00100000 */
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
+#define CONFIG_SYS_LOWBOOT		1
+#endif /* CONFIG_SYS_TEXT_BASE == 0x00100000 */
+
+/* Use SRAM until RAM will be available */
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT		1
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN		(384 << 10)	/* 384 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN		(1024 << 10)	/* 1 MiB for malloc() */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* initial mem map for Linux */
+
+/*
+ * Chip selects configuration
+ */
+/* Boot Chipselect */
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_CFG		0x00045D00
+
+/* Flash memory addressing */
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_CS0_CFG		CONFIG_SYS_BOOTCS_CFG
+
+/* Dual Port SRAM -- Kollmorgen Drive memory addressing */
+#define CONFIG_SYS_CS1_START		0x50000000
+#define CONFIG_SYS_CS1_SIZE		0x10000
+#define CONFIG_SYS_CS1_CFG		0x05055800
+
+/* Local register access */
+#define CONFIG_SYS_CS2_START		0x50010000
+#define CONFIG_SYS_CS2_SIZE		0x10000
+#define CONFIG_SYS_CS2_CFG		0x05055800
+
+/* Anybus CompactCom Module memory addressing */
+#define CONFIG_SYS_CS3_START		0x50020000
+#define CONFIG_SYS_CS3_SIZE		0x10000
+#define CONFIG_SYS_CS3_CFG		0x05055800
+
+/* No burst and dead cycle = 2 for all CSs */
+#define CONFIG_SYS_CS_BURST		0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE	0x22222222
+
+/*
+ * SDRAM configuration
+ */
+/* 2 x MT48LC16M16A2BG-75 IT:D, CASL 3, 32 bit data bus */
+#define SDRAM_CONFIG1		0x62322900
+#define SDRAM_CONFIG2		0x88c70000
+#define SDRAM_CONTROL		0x504f0000
+#define SDRAM_MODE		0x00cd0000
+
+/*
+ * Flash configuration
+ */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_FLASH_CFI_DRIVER	1
+#define CONFIG_SYS_FLASH_BASE		0xff000000
+#define CONFIG_SYS_FLASH_SIZE		0x01000000
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
+#define CONFIG_FLASH_16BIT		/* Flash is 16-bit */
+
+/*
+ * MTD configuration
+ */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
+#define MTDIDS_DEFAULT		"nor0=motionpro-0"
+#define MTDPARTS_DEFAULT	"mtdparts=motionpro-0:"			  \
+					"13m(fs),2m(kernel),384k(uboot)," \
+					"128k(env),128k(redund_env),"	  \
+					"128k(dtb),-(user_data)"
+
+/*
+ * IDE/ATA configuration
+ */
+#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
+#define CONFIG_SYS_IDE_MAXBUS		1
+#define CONFIG_SYS_IDE_MAXDEVICE	1
+#define CONFIG_IDE_PREINIT
+
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0060
+#define CONFIG_SYS_ATA_REG_OFFSET	CONFIG_SYS_ATA_DATA_OFFSET
+#define CONFIG_SYS_ATA_STRIDE		4
+#define CONFIG_DOS_PARTITION
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+#define CONFIG_SYS_I2C_MODULE		2	/* select I2C module #2 */
+#define CONFIG_SYS_I2C_SPEED		100000	/* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	1	/* 2 bytes per write cycle */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5	/* 2ms/cycle + 3ms extra */
+#define CONFIG_SYS_I2C_MULTI_EEPROMS		1	/* 2 EEPROMs (addr:50,52) */
+
+/*
+ * RTC configuration
+ */
+#define CONFIG_RTC_DS1337	1
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68
+
+/*
+ * Status LED configuration
+ */
+#define CONFIG_STATUS_LED		/* Status LED enabled */
+#define CONFIG_BOARD_SPECIFIC_LED
+
+#define ENABLE_GPIO_OUT		0x00000024
+#define LED_ON			0x00000010
+
+#ifndef __ASSEMBLY__
+/*
+ * In case of Motion-PRO, a LED is identified by its corresponding
+ * GPT Enable and Mode Select Register.
+ */
+typedef volatile unsigned long * led_id_t;
+
+extern void __led_init(led_id_t id, int state);
+extern void __led_toggle(led_id_t id);
+extern void __led_set(led_id_t id, int state);
+#endif /* __ASSEMBLY__ */
+
+/*
+ * Temperature sensor
+ */
+#define CONFIG_DTT_LM75		1
+#define CONFIG_DTT_SENSORS	{ 0x49 }
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+/* This has to be a multiple of the Flash sector size */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SIZE		0x1000
+#define CONFIG_ENV_SECT_SIZE	0x20000
+
+/* Configuration of redundant environment */
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+/*
+ * Pin multiplexing configuration
+ */
+
+/* PSC1: UART1
+ * PSC2: GPIO (default)
+ * PSC3: GPIO (default)
+ * USB: 2xUART4/5
+ * Ethernet: Ethernet 100Mbit with MD
+ * Timer: CAN2/GPIO
+ * PSC6/IRDA: GPIO (default)
+ */
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x1105a004
+
+/*
+ * Motion-PRO's CPLD revision control register
+ */
+#define CPLD_REV_REGISTER	(CONFIG_SYS_CS2_START + 0x06)
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory    */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x03e00000	/* 1 ... 62 MiB in DRAM */
+#define CONFIG_SYS_ALT_MEMTEST
+
+#define CONFIG_SYS_LOAD_ADDR		0x200000	/* default kernel load addr */
+
+/*
+ * Various low-level settings
+ */
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
+
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+
+/* Not needed for MPC 5xxx U-Boot, but used by tools/updater */
+#define CONFIG_SYS_RESET_ADDRESS	0xfff00100
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+#define OF_CPU			"PowerPC,5200@0"
+#define OF_SOC			"soc5200@f0000000"
+#define OF_TBCLK		(bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH		"/soc5200@f0000000/serial@2000"
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/mpc5121-common.h b/qemu/roms/u-boot/include/configs/mpc5121-common.h
new file mode 100644
index 000000000..0d70e8344
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/mpc5121-common.h
@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2010 DENX Software Engineering
+ * Anatolij Gustschin <agust@denx.de>
+ *
+ * Common configuration options for MPC5121 based boards
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MPC5121_COMMON_H
+#define __MPC5121_COMMON_H
+
+/* Use SRAM for initial stack */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_SRAM_BASE /* Init RAM base */
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_SRAM_SIZE /* Size of area */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+
+/*
+ * Serial console
+ */
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_SYS_BAUDRATE_TABLE \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_CMDLINE_EDITING		1	/* command line history */
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+#endif /* __MPC5121_COMMON_H */
diff --git a/qemu/roms/u-boot/include/configs/mpc5121ads.h b/qemu/roms/u-boot/include/configs/mpc5121ads.h
new file mode 100644
index 000000000..7de245b33
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/mpc5121ads.h
@@ -0,0 +1,643 @@
+/*
+ * (C) Copyright 2007-2009 DENX Software Engineering
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * MPC5121ADS board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MPC5121ADS 1
+/*
+ * Memory map for the MPC5121ADS board:
+ *
+ * 0x0000_0000 - 0x0FFF_FFFF	DDR RAM (256 MB)
+ * 0x3000_0000 - 0x3001_FFFF	SRAM (128 KB)
+ * 0x8000_0000 - 0x803F_FFFF	IMMR (4 MB)
+ * 0x8200_0000 - 0x8200_001F	CPLD (32 B)
+ * 0x8400_0000 - 0x82FF_FFFF	PCI I/O space (16 MB)
+ * 0xA000_0000 - 0xAFFF_FFFF	PCI memory space (256 MB)
+ * 0xB000_0000 - 0xBFFF_FFFF	PCI memory mapped I/O space (256 MB)
+ * 0xFC00_0000 - 0xFFFF_FFFF	NOR Boot FLASH (64 MB)
+ */
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1	/* E300 Family */
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
+
+/* video */
+#ifdef CONFIG_FSL_DIU_FB
+#define CONFIG_SYS_DIU_ADDR	(CONFIG_SYS_IMMR + 0x2100)
+#define CONFIG_VIDEO
+#define CONFIG_CMD_BMP
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#endif
+
+/* CONFIG_PCI is defined at config time */
+
+#ifdef CONFIG_MPC5121ADS_REV2
+#define CONFIG_SYS_MPC512X_CLKIN	66000000	/* in Hz */
+#else
+#define CONFIG_SYS_MPC512X_CLKIN	33333333	/* in Hz */
+#define CONFIG_PCI
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_F		/* call board_early_init_f() */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_SYS_IMMR		0x80000000
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000      /* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+
+/*
+ * DDR Setup - manually set all parameters as there's no SPD etc.
+ */
+#ifdef CONFIG_MPC5121ADS_REV2
+#define CONFIG_SYS_DDR_SIZE		256		/* MB */
+#else
+#define CONFIG_SYS_DDR_SIZE		512		/* MB */
+#endif
+#define CONFIG_SYS_DDR_BASE		0x00000000	/* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_MAX_RAM_SIZE		0x20000000
+
+#define CONFIG_SYS_IOCTRL_MUX_DDR	0x00000036
+
+/* DDR Controller Configuration
+ *
+ * SYS_CFG:
+ *	[31:31]	MDDRC Soft Reset:	Diabled
+ *	[30:30]	DRAM CKE pin:		Enabled
+ *	[29:29]	DRAM CLK:		Enabled
+ *	[28:28]	Command Mode:		Enabled (For initialization only)
+ *	[27:25]	DRAM Row Select:	dram_row[15:0] = magenta_address[25:10]
+ *	[24:21]	DRAM Bank Select:	dram_bank[1:0] = magenta_address[11:10]
+ *	[20:19]	Read Test:		DON'T USE
+ *	[18:18]	Self Refresh:		Enabled
+ *	[17:17]	16bit Mode:		Disabled
+ *	[16:13] Ready Delay:		2
+ *	[12:12]	Half DQS Delay:		Disabled
+ *	[11:11]	Quarter DQS Delay:	Disabled
+ *	[10:08]	Write Delay:		2
+ *	[07:07]	Early ODT:		Disabled
+ *	[06:06]	On DIE Termination:	Disabled
+ *	[05:05]	FIFO Overflow Clear:	DON'T USE here
+ *	[04:04]	FIFO Underflow Clear:	DON'T USE here
+ *	[03:03]	FIFO Overflow Pending:	DON'T USE here
+ *	[02:02]	FIFO Underlfow Pending:	DON'T USE here
+ *	[01:01]	FIFO Overlfow Enabled:	Enabled
+ *	[00:00]	FIFO Underflow Enabled:	Enabled
+ * TIME_CFG0
+ *	[31:16]	DRAM Refresh Time:	0 CSB clocks
+ *	[15:8]	DRAM Command Time:	0 CSB clocks
+ *	[07:00]	DRAM Precharge Time:	0 CSB clocks
+ * TIME_CFG1
+ *	[31:26]	DRAM tRFC:
+ *	[25:21]	DRAM tWR1:
+ *	[20:17]	DRAM tWRT1:
+ *	[16:11]	DRAM tDRR:
+ *	[10:05]	DRAM tRC:
+ *	[04:00]	DRAM tRAS:
+ * TIME_CFG2
+ *	[31:28]	DRAM tRCD:
+ *	[27:23]	DRAM tFAW:
+ *	[22:19]	DRAM tRTW1:
+ *	[18:15]	DRAM tCCD:
+ *	[14:10] DRAM tRTP:
+ *	[09:05]	DRAM tRP:
+ *	[04:00] DRAM tRPA
+ */
+#ifdef CONFIG_MPC5121ADS_REV2
+#define CONFIG_SYS_MDDRC_SYS_CFG	0xE8604A00
+#define CONFIG_SYS_MDDRC_TIME_CFG1	0x54EC1168
+#define CONFIG_SYS_MDDRC_TIME_CFG2	0x35210864
+#else
+#define CONFIG_SYS_MDDRC_SYS_CFG	0xEA804A00
+#define CONFIG_SYS_MDDRC_TIME_CFG1	0x68EC1168
+#define CONFIG_SYS_MDDRC_TIME_CFG2	0x34310864
+#endif
+#define CONFIG_SYS_MDDRC_TIME_CFG0	0x06183D2E
+
+#define CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA	 	0xEA802B00
+#define CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA	0x690e1189
+#define CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA	0x35310864
+
+#define CONFIG_SYS_DDRCMD_NOP		0x01380000
+#define CONFIG_SYS_DDRCMD_PCHG_ALL	0x01100400
+#define CONFIG_SYS_DDRCMD_EM2		0x01020000
+#define CONFIG_SYS_DDRCMD_EM3		0x01030000
+#define CONFIG_SYS_DDRCMD_EN_DLL	0x01010000
+#define CONFIG_SYS_DDRCMD_RFSH		0x01080000
+
+#define DDRCMD_EMR_OCD(pr, ohm) ( \
+	(1 << 24)	   | /* MDDRC Command Request	*/ \
+	(1 << 16)	   | /* MODE Reg BA[2:0] 	*/ \
+	(0 << 12)	   | /* Outputs 0=Enabled	*/ \
+	(0 << 11)	   | /* RDQS 			*/ \
+	(1 << 10)	   | /* DQS# 			*/ \
+	(pr <<  7)	   | /* OCD prog 7=deflt,0=exit	*/ \
+		    /* ODT Rtt[1:0] 0=0,1=75,2=150,3=50 */ \
+	((ohm & 0x2) <<  5)| /* Rtt1			*/ \
+	(0 <<  3)	   | /* additive posted CAS#	*/ \
+	((ohm & 0x1) <<  2)| /* Rtt0			*/ \
+	(0 <<  0)	   | /* Output Drive Strength	*/ \
+	(0 <<  0))	     /* DLL Enable 0=Normal	*/
+
+#define CONFIG_SYS_DDRCMD_OCD_DEFAULT	DDRCMD_EMR_OCD(7, 0)
+#define CONFIG_SYS_ELPIDA_OCD_EXIT	DDRCMD_EMR_OCD(0, 0)
+
+#define DDRCMD_MODE_REG(cas, wr) ( \
+	(1 << 24)    | /* MDDRC Command Request			*/ \
+	(0 << 16)    | /* MODE Reg BA[2:0] 			*/ \
+	((wr-1) << 9)| /* Write Recovery 			*/ \
+	(cas << 4)   | /* CAS 					*/ \
+	(0 << 3)     | /* Burst Type:0=Sequential,1=Interleaved	*/ \
+	(2 << 0))      /* 4 or 8 Burst Length:0x2=4 0x3=8	*/
+
+#define CONFIG_SYS_MICRON_INIT_DEV_OP	DDRCMD_MODE_REG(3, 3)
+#define CONFIG_SYS_ELPIDA_INIT_DEV_OP	DDRCMD_MODE_REG(4, 4)
+#define CONFIG_SYS_ELPIDA_RES_DLL	(DDRCMD_MODE_REG(4, 4) | (1 << 8))
+
+/* DDR Priority Manager Configuration */
+#define CONFIG_SYS_MDDRCGRP_PM_CFG1	0x00077777
+#define CONFIG_SYS_MDDRCGRP_PM_CFG2	0x00000000
+#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG	0x00000001
+#define CONFIG_SYS_MDDRCGRP_LUT0_MU	0xFFEEDDCC
+#define CONFIG_SYS_MDDRCGRP_LUT0_ML	0xBBAAAAAA
+#define CONFIG_SYS_MDDRCGRP_LUT1_MU	0x66666666
+#define CONFIG_SYS_MDDRCGRP_LUT1_ML	0x55555555
+#define CONFIG_SYS_MDDRCGRP_LUT2_MU	0x44444444
+#define CONFIG_SYS_MDDRCGRP_LUT2_ML	0x44444444
+#define CONFIG_SYS_MDDRCGRP_LUT3_MU	0x55555555
+#define CONFIG_SYS_MDDRCGRP_LUT3_ML	0x55555558
+#define CONFIG_SYS_MDDRCGRP_LUT4_MU	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT4_ML	0x11111122
+#define CONFIG_SYS_MDDRCGRP_LUT0_AU	0xaaaaaaaa
+#define CONFIG_SYS_MDDRCGRP_LUT0_AL	0xaaaaaaaa
+#define CONFIG_SYS_MDDRCGRP_LUT1_AU	0x66666666
+#define CONFIG_SYS_MDDRCGRP_LUT1_AL	0x66666666
+#define CONFIG_SYS_MDDRCGRP_LUT2_AU	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT2_AL	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT3_AU	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT3_AL	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT4_AU	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT4_AL	0x11111111
+
+/*
+ * NOR FLASH on the Local Bus
+ */
+#undef CONFIG_BKUP_FLASH
+#define CONFIG_SYS_FLASH_CFI				/* use the Common Flash Interface */
+#define CONFIG_FLASH_CFI_DRIVER			/* use the CFI driver */
+#ifdef CONFIG_BKUP_FLASH
+#define CONFIG_SYS_FLASH_BASE		0xFF800000	/* start of FLASH   */
+#define CONFIG_SYS_FLASH_SIZE		0x00800000	/* max flash size in bytes */
+#else
+#define CONFIG_SYS_FLASH_BASE		0xFC000000	/* start of FLASH   */
+#define CONFIG_SYS_FLASH_SIZE		0x04000000	/* max flash size in bytes */
+#endif
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_MAX_FLASH_SECT	256		/* max sectors per device */
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+
+/*
+ * NAND FLASH
+ * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only)
+ */
+#define CONFIG_CMD_NAND					/* enable NAND support */
+#define CONFIG_JFFS2_NAND				/* with JFFS2 on it */
+#define CONFIG_NAND_MPC5121_NFC
+#define CONFIG_SYS_NAND_BASE            0x40000000
+
+#define CONFIG_SYS_MAX_NAND_DEVICE      2
+#define CONFIG_SYS_NAND_SELECT_DEVICE	/* driver supports mutipl. chips */
+
+/*
+ * Configuration parameters for MPC5121 NAND driver
+ */
+#define CONFIG_FSL_NFC_WIDTH 1
+#define CONFIG_FSL_NFC_WRITE_SIZE 2048
+#define CONFIG_FSL_NFC_SPARE_SIZE 64
+#define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
+
+/*
+ * CPLD registers area is really only 32 bytes in size, but the smallest possible LP
+ * window is 64KB
+ */
+#define CONFIG_SYS_CPLD_BASE		0x82000000
+#define CONFIG_SYS_CPLD_SIZE		0x00010000	/* 64 KB */
+#define CONFIG_SYS_CS2_START		CONFIG_SYS_CPLD_BASE
+#define CONFIG_SYS_CS2_SIZE		CONFIG_SYS_CPLD_SIZE
+
+#define CONFIG_SYS_SRAM_BASE		0x30000000
+#define CONFIG_SYS_SRAM_SIZE		0x00020000	/* 128 KB */
+
+#define CONFIG_SYS_CS0_CFG		0x05059310	/* ALE active low, data size 4bytes */
+#define CONFIG_SYS_CS2_CFG		0x05059010	/* ALE active low, data size 1byte */
+#define CONFIG_SYS_CS_ALETIMING	0x00000005	/* Use alternative CS timing for CS0 and CS2 */
+
+/* Use SRAM for initial stack */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_SRAM_BASE		/* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_SRAM_SIZE		/* Size of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE		/* Start of monitor */
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)		/* Reserve 512 kB for Mon */
+#ifdef	CONFIG_FSL_DIU_FB
+#define CONFIG_SYS_MALLOC_LEN		(6 * 1024 * 1024)	/* Reserved for malloc */
+#else
+#define CONFIG_SYS_MALLOC_LEN		(512 * 1024)
+#endif
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX     1
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	3	/* console is on PSC3 */
+#define CONFIG_SYS_PSC3
+#if CONFIG_PSC_CONSOLE != 3
+#error CONFIG_PSC_CONSOLE must be 3
+#endif
+#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CONSOLE_FIFO_TX_SIZE	FIFOC_PSC3_TX_SIZE
+#define CONSOLE_FIFO_TX_ADDR	FIFOC_PSC3_TX_ADDR
+#define CONSOLE_FIFO_RX_SIZE	FIFOC_PSC3_RX_SIZE
+#define CONSOLE_FIFO_RX_ADDR	FIFOC_PSC3_RX_ADDR
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef  CONFIG_SYS_HUSH_PARSER
+#endif
+
+/*
+ * Clocks in use
+ */
+#define SCCR1_CLOCKS_EN	(CLOCK_SCCR1_CFG_EN |				\
+			 CLOCK_SCCR1_DDR_EN |				\
+			 CLOCK_SCCR1_FEC_EN |				\
+			 CLOCK_SCCR1_LPC_EN |				\
+			 CLOCK_SCCR1_NFC_EN |				\
+			 CLOCK_SCCR1_PATA_EN |				\
+			 CLOCK_SCCR1_PCI_EN |				\
+			 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |	\
+			 CLOCK_SCCR1_PSCFIFO_EN |			\
+			 CLOCK_SCCR1_TPR_EN)
+
+#define SCCR2_CLOCKS_EN	(CLOCK_SCCR2_DIU_EN |		\
+			 CLOCK_SCCR2_I2C_EN |		\
+			 CLOCK_SCCR2_MEM_EN |		\
+			 CLOCK_SCCR2_SPDIF_EN |		\
+			 CLOCK_SCCR2_USB1_EN |		\
+			 CLOCK_SCCR2_USB2_EN)
+
+/*
+ * PCI
+ */
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+
+/*
+ * General PCI
+ */
+#define CONFIG_SYS_PCI_MEM_BASE	0xA0000000
+#define CONFIG_SYS_PCI_MEM_PHYS	CONFIG_SYS_PCI_MEM_BASE
+#define CONFIG_SYS_PCI_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI_MMIO_BASE	(CONFIG_SYS_PCI_MEM_BASE + CONFIG_SYS_PCI_MEM_SIZE)
+#define CONFIG_SYS_PCI_MMIO_PHYS	CONFIG_SYS_PCI_MMIO_BASE
+#define CONFIG_SYS_PCI_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI_IO_PHYS		0x84000000
+#define CONFIG_SYS_PCI_IO_SIZE		0x01000000	/* 16M */
+
+
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+
+#endif
+
+/* I2C */
+#define CONFIG_HARD_I2C			/* I2C with hardware support */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#if 0
+#define CONFIG_SYS_I2C_NOPROBES	{{0,0x69}}	/* Don't probe these addrs */
+#endif
+
+/*
+ * IIM - IC Identification Module
+ */
+#undef CONFIG_FSL_IIM
+
+/*
+ * EEPROM configuration
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2	/* 16-bit EEPROM address */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* Atmel: AT24C32A-10TQ-2.7 */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* 10ms of delay */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* 32-Byte Page Write Mode */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC512x_FEC	1
+#define CONFIG_PHY_ADDR		0x1
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_FEC_AN_TIMEOUT	1
+#define CONFIG_HAS_ETH0
+
+/*
+ * Configure on-board RTC
+ */
+#define CONFIG_RTC_M41T62			/* use M41T62 rtc via i2 */
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68	/* at address 0x68		*/
+
+/*
+ * USB  Support
+ */
+#define CONFIG_CMD_USB
+
+#if defined(CONFIG_CMD_USB)
+#define CONFIG_USB_EHCI				/* Enable EHCI Support	*/
+#define CONFIG_USB_EHCI_FSL			/* On a FSL platform	*/
+#define CONFIG_EHCI_MMIO_BIG_ENDIAN		/* With big-endian regs	*/
+#define CONFIG_EHCI_DESC_BIG_ENDIAN
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_STORAGE
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+/* This has to be a multiple of the Flash sector size */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SIZE		0x2000
+#ifdef CONFIG_BKUP_FLASH
+#define CONFIG_ENV_SECT_SIZE	0x20000	/* one sector (256K) for env */
+#else
+#define CONFIG_ENV_SECT_SIZE	0x40000	/* one sector (256K) for env */
+#endif
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+
+#undef CONFIG_CMD_FUSE
+
+#if defined(CONFIG_PCI)
+#define CONFIG_CMD_PCI
+#endif
+
+/*
+ * Dynamic MTD partition support
+ */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
+#define MTDIDS_DEFAULT		"nor0=fc000000.flash,nand0=mpc5121.nand"
+
+/*
+ * NOR flash layout:
+ *
+ * FC000000 - FEABFFFF 42.75 MiB	User Data
+ * FEAC0000 - FFABFFFF  16 MiB		Root File System
+ * FFAC0000 - FFEBFFFF   4 MiB		Linux Kernel
+ * FFEC0000 - FFEFFFFF 256 KiB		Device Tree
+ * FFF00000 - FFFFFFFF   1 MiB		U-Boot (up to 512 KiB) and 2 x * env
+ *
+ * NAND flash layout: one big partition
+ */
+#define MTDPARTS_DEFAULT	"mtdparts=fc000000.flash:43776k(user),"	\
+						"16m(rootfs),"		\
+						"4m(kernel),"		\
+						"256k(dtb),"		\
+						"1m(u-boot);"		\
+					"mpc5121.nand:-(data)"
+
+
+#if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2) || defined(CONFIG_CMD_USB)
+
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION
+#define CONFIG_ISO_PARTITION
+
+#define CONFIG_CMD_FAT
+#define CONFIG_SUPPORT_VFAT
+
+#endif /* defined(CONFIG_CMD_IDE) */
+
+/*
+ * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
+ * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set
+ * to 0xFFFF, watchdog timeouts after about 64s. For details refer
+ * to chapter 36 of the MPC5121e Reference Manual.
+ */
+/* #define CONFIG_WATCHDOG */		/* enable watchdog */
+#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
+
+ /*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+#ifdef CONFIG_CMD_KGDB
+	#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
+#else
+	#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
+#endif
+
+
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)	/* Initial Memory map for Linux*/
+
+/* Cache Configuration */
+#define CONFIG_SYS_DCACHE_SIZE		32768
+#define CONFIG_SYS_CACHELINE_SIZE	32
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
+#endif
+
+#define CONFIG_SYS_HID0_INIT	0x000000000
+#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | HID0_ICE)
+#define CONFIG_SYS_HID2	HID2_HBE
+
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_TIMESTAMP
+
+#define CONFIG_HOSTNAME		mpc5121ads
+#define CONFIG_BOOTFILE		"mpc5121ads/uImage"
+#define CONFIG_ROOTPATH		"/opt/eldk/ppc_6xx"
+
+#define CONFIG_LOADADDR		400000	/* default location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY	5	/* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS			/* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+	"echo"
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"u-boot_addr_r=200000\0"					\
+	"kernel_addr_r=600000\0"					\
+	"fdt_addr_r=880000\0"						\
+	"ramdisk_addr_r=900000\0"					\
+	"u-boot_addr=FFF00000\0"					\
+	"kernel_addr=FFAC0000\0"					\
+	"fdt_addr=FFEC0000\0"						\
+	"ramdisk_addr=FEAC0000\0"					\
+	"ramdiskfile=mpc5121ads/uRamdisk\0"				\
+	"u-boot=mpc5121ads/u-boot.bin\0"				\
+	"bootfile=mpc5121ads/uImage\0"					\
+	"fdtfile=mpc5121ads/mpc5121ads.dtb\0"				\
+	"rootpath=/opt/eldk/ppc_6xx\n"					\
+	"netdev=eth0\0"							\
+	"consdev=ttyPSC0\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} "				\
+		"console=${consdev},${baudrate}\0"			\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
+		"tftp ${fdt_addr_r} ${fdtfile};"			\
+		"run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
+	"net_self=tftp ${kernel_addr_r} ${bootfile};"			\
+		"tftp ${ramdisk_addr_r} ${ramdiskfile};"		\
+		"tftp ${fdt_addr_r} ${fdtfile};"			\
+		"run ramargs addip addtty;"				\
+		"bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
+	"load=tftp ${u-boot_addr_r} ${u-boot}\0"			\
+	"update=protect off ${u-boot_addr} +${filesize};"		\
+		"era ${u-boot_addr} +${filesize};"			\
+		"cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0"	\
+	"upd=run load update\0"						\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES	1
+
+#define OF_CPU			"PowerPC,5121@0"
+#define OF_SOC_COMPAT		"fsl,mpc5121-immr"
+#define OF_TBCLK		(bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH		"/soc@80000000/serial@11300"
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff
+ *-----------------------------------------------------------------------
+ */
+
+#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for IDE not supported	*/
+
+#define CONFIG_IDE_RESET		/* reset for IDE supported	*/
+#define CONFIG_IDE_PREINIT
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	2	/* max. 1 drive per IDE bus	*/
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_BASE_ADDR	get_pata_base()
+
+/* Offset for data I/O			RefMan MPC5121EE Table 28-10	*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x00A0)
+
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers	RefMan MPC5121EE Table 28-23	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x00D8)
+
+/* Interval between registers	*/
+#define CONFIG_SYS_ATA_STRIDE		4
+
+#define ATA_BASE_ADDR			get_pata_base()
+
+/*
+ * Control register bit definitions
+ */
+#define FSL_ATA_CTRL_FIFO_RST_B		0x80000000
+#define FSL_ATA_CTRL_ATA_RST_B		0x40000000
+#define FSL_ATA_CTRL_FIFO_TX_EN		0x20000000
+#define FSL_ATA_CTRL_FIFO_RCV_EN	0x10000000
+#define FSL_ATA_CTRL_DMA_PENDING	0x08000000
+#define FSL_ATA_CTRL_DMA_ULTRA		0x04000000
+#define FSL_ATA_CTRL_DMA_WRITE		0x02000000
+#define FSL_ATA_CTRL_IORDY_EN		0x01000000
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/mpc7448hpc2.h b/qemu/roms/u-boot/include/configs/mpc7448hpc2.h
new file mode 100644
index 000000000..0308c52bc
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/mpc7448hpc2.h
@@ -0,0 +1,386 @@
+/*
+ * Copyright (c) 2005 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2006
+ * Alex Bounine , Tundra Semiconductor Corp.
+ * Roy Zang	, <tie-fei.zang@freescale.com> Freescale Corp.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board specific configuration options for Freescale
+ * MPC7448HPC2 (High-Performance Computing II) (Taiga) board
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* Board Configuration Definitions */
+/* MPC7448HPC2 (High-Performance Computing II) (Taiga) board */
+
+#define CONFIG_MPC7448HPC2
+
+#define CONFIG_74xx
+#define CONFIG_HIGH_BATS	/* High BATs supported */
+#define CONFIG_ALTIVEC		/* undef to disable */
+
+#define	CONFIG_SYS_TEXT_BASE	0xFF000000
+
+#define CONFIG_SYS_BOARD_NAME		"MPC7448 HPC II"
+#define CONFIG_IDENT_STRING	" Freescale MPC7448 HPC II"
+
+#define CONFIG_SYS_OCN_CLK		133000000	/* 133 MHz */
+#define CONFIG_SYS_BUS_CLK		133000000
+
+#define CONFIG_SYS_CLK_SPREAD		/* Enable Spread-Spectrum Clock generation */
+
+#undef  CONFIG_ECC		/* disable ECC support */
+
+#ifndef __ASSEMBLY__
+#include <galileo/core.h>
+#endif
+
+/* Board-specific Initialization Functions to be called */
+#define CONFIG_SYS_BOARD_ASM_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115000 */
+
+/*#define CONFIG_SYS_HUSH_PARSER */
+#undef CONFIG_SYS_HUSH_PARSER
+
+
+/* Pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+#define OF_TSI			"tsi108@c0000000"
+#define OF_TBCLK		(bd->bi_busfreq / 8)
+#define OF_STDOUT_PATH		"/tsi108@c0000000/serial@7808"
+
+/*
+ * The following defines let you select what serial you want to use
+ * for your console driver.
+ *
+ * what to do:
+ * If you have hacked a serial cable onto the second DUART channel,
+ * change the CONFIG_SYS_DUART port from 1 to 0 below.
+ *
+ */
+
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_OCN_CLK * 8
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_TSI108_CSR_RST_BASE+0x7808)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_TSI108_CSR_RST_BASE+0x7C08)
+
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds */
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#undef CONFIG_BOOTARGS
+/* #define CONFIG_PREBOOT  "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" */
+
+#if (CONFIG_BOOTDELAY >= 0)
+#define CONFIG_BOOTCOMMAND	"tftpboot 0x400000 zImage.initrd.elf;\
+ setenv bootargs $(bootargs) $(bootargs_root) nfsroot=$(serverip):$(rootpath) \
+ ip=$(ipaddr):$(serverip)$(bootargs_end);  bootm 0x400000; "
+
+#define CONFIG_BOOTARGS "console=ttyS0,115200"
+#endif
+
+#undef CONFIG_EXTRA_ENV_SETTINGS
+
+#define CONFIG_SERIAL	"No. 1"
+
+/* Networking Configuration */
+
+#define CONFIG_TSI108_ETH
+#define CONFIG_TSI108_ETH_NUM_PORTS	2
+
+
+#define CONFIG_BOOTFILE		"zImage.initrd.elf"
+#define CONFIG_LOADADDR		0x400000
+
+/*-------------------------------------------------------------------------- */
+
+#define CONFIG_LOADS_ECHO	0	/* echo off for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate changes */
+
+#undef CONFIG_WATCHDOG		/* watchdog disabled */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DATE
+
+
+/*set date in u-boot*/
+#define CONFIG_RTC_M48T35A
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xfc000000
+#define CONFIG_SYS_NVRAM_SIZE		0x8000
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_VERSION_VARIABLE		1
+#define CONFIG_TSI108_I2C
+#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed */
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* I2C EEPROM page 1 */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1	/* Bytes of address */
+
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
+#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port at */
+#else
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+#endif
+
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START	0x00400000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x07c00000	/* 4 ... 124 MB in DRAM */
+
+#define CONFIG_SYS_LOAD_ADDR	0x00400000	/* default load address */
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area
+ */
+
+/*
+ * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS
+ * To an unused memory region. The stack will remain in cache until RAM
+ * is initialized
+ */
+#undef  CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0x07d00000	/* unused memory region */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000/* larger space - we have SDRAM initialized */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+
+#define CONFIG_SYS_SDRAM_BASE		0x00000000	/* first 256 MB of SDRAM */
+#define CONFIG_SYS_SDRAM1_BASE		0x10000000	/* next 256MB of SDRAM */
+
+#define CONFIG_SYS_SDRAM2_BASE	0x40000000	/* beginning of non-cacheable alias for SDRAM - first 256MB */
+#define CONFIG_SYS_SDRAM3_BASE	0x50000000	/* next Non-Cacheable 256MB of SDRAM */
+
+#define CONFIG_SYS_PCI_PFM_BASE	0x80000000	/* Prefetchable (cacheable) PCI/X PFM and SDRAM OCN (128MB+128MB) */
+
+#define CONFIG_SYS_PCI_MEM32_BASE	0xE0000000	/* Non-Cacheable PCI/X MEM and SDRAM OCN (128MB+128MB) */
+
+#define CONFIG_SYS_MISC_REGION_BASE	0xf0000000	/* Base Address for (PCI/X + Flash) region */
+
+#define CONFIG_SYS_FLASH_BASE	0xff000000	/* Base Address of Flash device */
+#define CONFIG_SYS_FLASH_BASE2	0xfe000000	/* Alternate Flash Base Address */
+
+#define CONFIG_VERY_BIG_RAM	/* we will use up to 256M memory for cause we are short of BATS */
+
+#define PCI0_IO_BASE_BOOTM	0xfd000000
+
+#define CONFIG_SYS_RESET_ADDRESS	0x3fffff00
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* u-boot code base */
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc */
+
+/* Peripheral Device section */
+
+/*
+ * Resources on the Tsi108
+ */
+
+#define CONFIG_SYS_TSI108_CSR_RST_BASE	0xC0000000	/* Tsi108 CSR base after reset */
+#define CONFIG_SYS_TSI108_CSR_BASE	CONFIG_SYS_TSI108_CSR_RST_BASE	/* Runtime Tsi108 CSR base */
+
+#define ENABLE_PCI_CSR_BAR	/* enables access to Tsi108 CSRs from the PCI/X bus */
+
+#undef  DISABLE_PBM
+
+/*
+ * PCI stuff
+ *
+ */
+
+#define CONFIG_PCI		/* include pci support */
+#define CONFIG_TSI108_PCI	/* include tsi108 pci support */
+
+#define PCI_HOST_ADAPTER	0	/* configure as pci adapter */
+#define PCI_HOST_FORCE		1	/* configure as pci host */
+#define PCI_HOST_AUTO		2	/* detected via arbiter enable */
+
+#define CONFIG_PCI_HOST PCI_HOST_FORCE	/* select pci host function */
+#define CONFIG_PCI_PNP		/* do pci plug-and-play */
+
+/* PCI MEMORY MAP section */
+
+/* PCI view of System Memory */
+#define CONFIG_SYS_PCI_MEMORY_BUS	0x00000000
+#define CONFIG_SYS_PCI_MEMORY_PHYS	0x00000000
+#define CONFIG_SYS_PCI_MEMORY_SIZE	0x80000000
+
+/* PCI Memory Space */
+#define CONFIG_SYS_PCI_MEM_BUS		(CONFIG_SYS_PCI_MEM_PHYS)
+#define CONFIG_SYS_PCI_MEM_PHYS	(CONFIG_SYS_PCI_MEM32_BASE)	/* 0xE0000000 */
+#define CONFIG_SYS_PCI_MEM_SIZE	0x10000000	/* 256 MB space for PCI/X Mem + SDRAM OCN */
+
+/* PCI I/O Space */
+#define CONFIG_SYS_PCI_IO_BUS		0x00000000
+#define CONFIG_SYS_PCI_IO_PHYS		0xfa000000	/* Changed from fd000000 */
+
+#define CONFIG_SYS_PCI_IO_SIZE		0x01000000	/* 16MB */
+
+/* PCI Config Space mapping */
+#define CONFIG_SYS_PCI_CFG_BASE	0xfb000000	/* Changed from FE000000 */
+#define CONFIG_SYS_PCI_CFG_SIZE	0x01000000	/* 16MB */
+
+#define CONFIG_SYS_IBAT0U	0xFE0003FF
+#define CONFIG_SYS_IBAT0L	0xFE000002
+
+#define CONFIG_SYS_IBAT1U	0x00007FFF
+#define CONFIG_SYS_IBAT1L	0x00000012
+
+#define CONFIG_SYS_IBAT2U	0x80007FFF
+#define CONFIG_SYS_IBAT2L	0x80000022
+
+#define CONFIG_SYS_IBAT3U	0x00000000
+#define CONFIG_SYS_IBAT3L	0x00000000
+
+#define CONFIG_SYS_IBAT4U	0x00000000
+#define CONFIG_SYS_IBAT4L	0x00000000
+
+#define CONFIG_SYS_IBAT5U	0x00000000
+#define CONFIG_SYS_IBAT5L	0x00000000
+
+#define CONFIG_SYS_IBAT6U	0x00000000
+#define CONFIG_SYS_IBAT6L	0x00000000
+
+#define CONFIG_SYS_IBAT7U	0x00000000
+#define CONFIG_SYS_IBAT7L	0x00000000
+
+#define CONFIG_SYS_DBAT0U	0xE0003FFF
+#define CONFIG_SYS_DBAT0L	0xE000002A
+
+#define CONFIG_SYS_DBAT1U	0x00007FFF
+#define CONFIG_SYS_DBAT1L	0x00000012
+
+#define CONFIG_SYS_DBAT2U	0x00000000
+#define CONFIG_SYS_DBAT2L	0x00000000
+
+#define CONFIG_SYS_DBAT3U	0xC0000003
+#define CONFIG_SYS_DBAT3L	0xC000002A
+
+#define CONFIG_SYS_DBAT4U	0x00000000
+#define CONFIG_SYS_DBAT4L	0x00000000
+
+#define CONFIG_SYS_DBAT5U	0x00000000
+#define CONFIG_SYS_DBAT5L	0x00000000
+
+#define CONFIG_SYS_DBAT6U	0x00000000
+#define CONFIG_SYS_DBAT6L	0x00000000
+
+#define CONFIG_SYS_DBAT7U	0x00000000
+#define CONFIG_SYS_DBAT7L	0x00000000
+
+/* I2C addresses for the two DIMM SPD chips */
+#define DIMM0_I2C_ADDR	0x51
+#define DIMM1_I2C_ADDR	0x52
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(8<<20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* Flash can be at one of two addresses */
+#define FLASH_BANK_SIZE		0x01000000	/* 16 MB Total */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE, /* CONFIG_SYS_FLASH_BASE2 */ }
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_WRITE_SWAPPED_DATA
+
+#define PHYS_FLASH_SIZE		0x01000000
+#define CONFIG_SYS_MAX_FLASH_SECT	(128)
+
+#define CONFIG_ENV_IS_IN_NVRAM
+#define CONFIG_ENV_ADDR		0xFC000000
+
+#define CONFIG_ENV_OFFSET	0x00000000	/* Offset of Environment Sector */
+#define CONFIG_ENV_SIZE	0x00000400	/* Total Size of Environment Space */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For all MPC74xx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * L2CR setup -- make sure this is right for your board!
+ * look in include/mpc74xx.h for the defines used here
+ */
+#undef CONFIG_SYS_L2
+
+#define L2_INIT		0
+#define L2_ENABLE	(L2_INIT | L2CR_L2E)
+#define CONFIG_SYS_SERIAL_HANG_IN_EXCEPTION
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/mpc8308_p1m.h b/qemu/roms/u-boot/include/configs/mpc8308_p1m.h
new file mode 100644
index 000000000..4ae9afd4e
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/mpc8308_p1m.h
@@ -0,0 +1,532 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
+ *
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1 /* E300 family */
+#define CONFIG_MPC830x		1 /* MPC830x family */
+#define CONFIG_MPC8308		1 /* MPC8308 CPU specific */
+#define CONFIG_MPC8308_P1M	1 /* mpc8308_p1m board specific */
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xFC000000
+#endif
+
+/*
+ * On-board devices
+ *
+ * TSECs
+ */
+#define CONFIG_TSEC1
+#define CONFIG_TSEC2
+
+/*
+ * System Clock Setup
+ */
+#define CONFIG_83XX_CLKIN	33333333 /* in Hz */
+#define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN
+
+/*
+ * Hardware Reset Configuration Word
+ * if CLKIN is 66.66MHz, then
+ * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
+ * We choose the A type silicon as default, so the core is 400Mhz.
+ */
+#define CONFIG_SYS_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_2X1 |\
+	HRCWL_SVCOD_DIV_2 |\
+	HRCWL_CSB_TO_CLKIN_4X1 |\
+	HRCWL_CORE_TO_CSB_3X1)
+/*
+ * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
+ * in 8308's HRCWH according to the manual, but original Freescale's
+ * code has them and I've expirienced some problems using the board
+ * with BDI3000 attached when I've tried to set these bits to zero
+ * (UART doesn't work after the 'reset run' command).
+ */
+#define CONFIG_SYS_HRCW_HIGH (\
+	HRCWH_PCI_HOST |\
+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0X00000100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_RL_EXT_LEGACY |\
+	HRCWH_TSEC1M_IN_MII |\
+	HRCWH_TSEC2M_IN_MII |\
+	HRCWH_BIG_ENDIAN)
+
+/*
+ * System IO Config
+ */
+#define CONFIG_SYS_SICRH (\
+	SICRH_ESDHC_A_GPIO |\
+	SICRH_ESDHC_B_GPIO |\
+	SICRH_ESDHC_C_GTM |\
+	SICRH_GPIO_A_TSEC2 |\
+	SICRH_GPIO_B_TSEC2_TX_CLK |\
+	SICRH_IEEE1588_A_GPIO |\
+	SICRH_USB |\
+	SICRH_GTM_GPIO |\
+	SICRH_IEEE1588_B_GPIO |\
+	SICRH_ETSEC2_CRS |\
+	SICRH_GPIOSEL_1 |\
+	SICRH_TMROBI_V3P3 |\
+	SICRH_TSOBI1_V3P3 |\
+	SICRH_TSOBI2_V3P3)	/* 0xf577d100 */
+#define CONFIG_SYS_SICRL (\
+	SICRL_SPI_PF0 |\
+	SICRL_UART_PF0 |\
+	SICRL_IRQ_PF0 |\
+	SICRL_I2C2_PF0 |\
+	SICRL_ETSEC1_TX_CLK)	/* 0x00000000 */
+
+#define CONFIG_SYS_GPIO1_PRELIM
+/* GPIO Default input/output settings */
+#define CONFIG_SYS_GPIO1_DIR        0x7AAF8C00
+/*
+ * Default GPIO values:
+ * LED#1 enabled; WLAN enabled; Both COM LED on (orange)
+ */
+#define CONFIG_SYS_GPIO1_DAT        0x08008C00
+
+/*
+ * IMMR new address
+ */
+#define CONFIG_SYS_IMMR		0xE0000000
+
+/*
+ * SERDES
+ */
+#define CONFIG_FSL_SERDES
+#define CONFIG_FSL_SERDES1	0xe3000
+
+/*
+ * Arbiter Setup
+ */
+#define CONFIG_SYS_ACR_PIPE_DEP	3 /* Arbiter pipeline depth is 4 */
+#define CONFIG_SYS_ACR_RPTCNT	3 /* Arbiter repeat count is 4 */
+#define CONFIG_SYS_SPCR_TSECEP	3 /* eTSEC emergency priority is highest */
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+#define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN \
+				| DDRCDR_PZ_LOZ \
+				| DDRCDR_NZ_LOZ \
+				| DDRCDR_ODT \
+				| DDRCDR_Q_DRN)
+				/* 0x7b880001 */
+/*
+ * Manually set up DDR parameters
+ * consist of two chips HY5PS12621BFP-C4 from HYNIX
+ */
+
+#define CONFIG_SYS_DDR_SIZE		128 /* MB */
+
+#define CONFIG_SYS_DDR_CS0_BNDS	0x00000007
+#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
+					| CSCONFIG_ODT_RD_NEVER \
+					| CSCONFIG_ODT_WR_ONLY_CURRENT \
+					| CSCONFIG_ROW_BIT_13 \
+					| CSCONFIG_COL_BIT_10)
+					/* 0x80010102 */
+#define CONFIG_SYS_DDR_TIMING_3	0x00000000
+#define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
+				| (0 << TIMING_CFG0_WRT_SHIFT) \
+				| (0 << TIMING_CFG0_RRT_SHIFT) \
+				| (0 << TIMING_CFG0_WWT_SHIFT) \
+				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
+				| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
+				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
+				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
+				/* 0x00220802 */
+#define CONFIG_SYS_DDR_TIMING_1	((2 << TIMING_CFG1_PRETOACT_SHIFT) \
+				| (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
+				| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
+				| (5 << TIMING_CFG1_CASLAT_SHIFT) \
+				| (6 << TIMING_CFG1_REFREC_SHIFT) \
+				| (2 << TIMING_CFG1_WRREC_SHIFT) \
+				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
+				| (2 << TIMING_CFG1_WRTORD_SHIFT))
+				/* 0x27256222 */
+#define CONFIG_SYS_DDR_TIMING_2	((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
+				| (4 << TIMING_CFG2_CPO_SHIFT) \
+				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
+				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
+				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
+				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
+				| (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
+				/* 0x121048c5 */
+#define CONFIG_SYS_DDR_INTERVAL	((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
+				| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
+				/* 0x03600100 */
+#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
+				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
+				| SDRAM_CFG_DBW_32)
+				/* 0x43080000 */
+
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000 /* 1 posted refresh */
+#define CONFIG_SYS_DDR_MODE		((0x0448 << SDRAM_MODE_ESD_SHIFT) \
+				| (0x0232 << SDRAM_MODE_SD_SHIFT))
+				/* ODT 150ohm CL=3, AL=1 on SDRAM */
+#define CONFIG_SYS_DDR_MODE2		0x00000000
+
+/*
+ * Memory test
+ */
+#define CONFIG_SYS_MEMTEST_START	0x00001000 /* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x07f00000
+
+/*
+ * The reserved memory
+ */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE /* start of monitor */
+
+#define CONFIG_SYS_MONITOR_LEN	(384 * 1024) /* Reserve 384 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN	(512 * 1024) /* Reserved for malloc */
+
+/*
+ * Initial RAM Base Address Setup
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * Local Bus Configuration & Clock Setup
+ */
+#define CONFIG_SYS_LCRR_DBYP		LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_2
+#define CONFIG_SYS_LBC_LBCR		0x00040000
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
+#define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+
+#define CONFIG_SYS_FLASH_BASE		0xFC000000 /* FLASH base address */
+#define CONFIG_SYS_FLASH_SIZE		64 /* FLASH size is 64M */
+#define CONFIG_SYS_FLASH_PROTECTION	1 /* Use h/w Flash protection. */
+
+/* Window base at flash base */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_64MB)
+
+#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE \
+				| BR_PS_16	/* 16 bit port */ \
+				| BR_MS_GPCM	/* MSEL = GPCM */ \
+				| BR_V)		/* valid */
+#define CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+				| OR_UPM_XAM \
+				| OR_GPCM_CSNT \
+				| OR_GPCM_ACS_DIV2 \
+				| OR_GPCM_XACS \
+				| OR_GPCM_SCY_4 \
+				| OR_GPCM_TRLX_SET \
+				| OR_GPCM_EHTR_SET)
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	512
+
+/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(1000 * 1024)
+/* Flash Write Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(500 * 1024)
+
+/*
+ * SJA1000 CAN controller on Local Bus
+ */
+#define CONFIG_SYS_SJA1000_BASE	0xFBFF0000
+#define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_SJA1000_BASE \
+				| BR_PS_8	/* 8 bit port size */ \
+				| BR_MS_GPCM	/* MSEL = GPCM */ \
+				| BR_V)		/* valid */
+#define CONFIG_SYS_OR1_PRELIM	(OR_AM_32KB \
+				| OR_GPCM_SCY_5 \
+				| OR_GPCM_EHTR_SET)
+				/* 0xFFFF8052 */
+
+#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_SJA1000_BASE
+#define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)
+
+/*
+ * CPLD on Local Bus
+ */
+#define CONFIG_SYS_CPLD_BASE	0xFBFF8000
+#define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_CPLD_BASE \
+				| BR_PS_8	/* 8 bit port */ \
+				| BR_MS_GPCM	/* MSEL = GPCM */ \
+				| BR_V)		/* valid */
+#define CONFIG_SYS_OR2_PRELIM	(OR_AM_32KB \
+				| OR_GPCM_SCY_4 \
+				| OR_GPCM_EHTR_SET)
+				/* 0xFFFF8042 */
+
+#define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_CPLD_BASE
+#define CONFIG_SYS_LBLAWAR2_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX	1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+/* Pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCIE1_BASE		0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_BASE	0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000
+#define CONFIG_SYS_PCIE1_CFG_BASE	0xB0000000
+#define CONFIG_SYS_PCIE1_CFG_SIZE	0x01000000
+#define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xB1000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000
+
+/* enable PCIE clock */
+#define CONFIG_SYS_SCCR_PCIEXP1CM	1
+
+#define CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_PCIE
+
+#define CONFIG_PCI_PNP		/* do pci plug-and-play */
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
+#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
+
+/*
+ * TSEC
+ */
+#define CONFIG_TSEC_ENET	/* TSEC ethernet support */
+#define CONFIG_SYS_TSEC1_OFFSET	0x24000
+#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
+#define CONFIG_SYS_TSEC2_OFFSET	0x25000
+#define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
+
+/*
+ * TSEC ethernet configuration
+ */
+#define CONFIG_MII		1 /* MII PHY management */
+#define CONFIG_TSEC1_NAME	"eTSEC0"
+#define CONFIG_TSEC2_NAME	"eTSEC1"
+#define TSEC1_PHY_ADDR		1
+#define TSEC2_PHY_ADDR		2
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC1_FLAGS		0
+#define TSEC2_FLAGS		0
+
+/* Options are: eTSEC[0-1] */
+#define CONFIG_ETHPRIME		"eTSEC0"
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + \
+				 CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env */
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
+
+#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */
+
+/*
+ * Core HID Setup
+ */
+#define CONFIG_SYS_HID0_INIT	0x000000000
+#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
+				 HID0_ENABLE_INSTRUCTION_CACHE | \
+				 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
+#define CONFIG_SYS_HID2		HID2_HBE
+
+/*
+ * MMU Setup
+ */
+
+/* DDR: cache cacheable */
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
+					BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
+					BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+
+/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR | BATL_PP_RW | \
+			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
+					BATU_VP)
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+
+/* FLASH: icache cacheable, but dcache-inhibit and guarded */
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
+					BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
+					BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
+					BATL_CACHEINHIBIT | \
+					BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+
+/* Stack in dcache: cacheable, no memory coherence */
+#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
+#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
+					BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
+
+/*
+ * Environment Configuration
+ */
+
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#endif
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY	5	/* -1 disables auto-boot */
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"consoledev=ttyS0\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs}"				\
+		" console=${consoledev},${baudrate}\0"			\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
+	"addmisc=setenv bootargs ${bootargs}\0"				\
+	"kernel_addr=FC0A0000\0"					\
+	"fdt_addr=FC2A0000\0"						\
+	"ramdisk_addr=FC2C0000\0"					\
+	"u-boot=mpc8308_p1m/u-boot.bin\0"				\
+	"kernel_addr_r=1000000\0"					\
+	"fdt_addr_r=C00000\0"						\
+	"hostname=mpc8308_p1m\0"					\
+	"bootfile=mpc8308_p1m/uImage\0"					\
+	"fdtfile=mpc8308_p1m/mpc8308_p1m.dtb\0"				\
+	"rootpath=/opt/eldk-4.2/ppc_6xx\0"				\
+	"flash_self=run ramargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
+	"flash_nfs=run nfsargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
+		"tftp ${fdt_addr_r} ${fdtfile};"			\
+		"run nfsargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
+	"bootcmd=run flash_self\0"					\
+	"load=tftp ${loadaddr} ${u-boot}\0"				\
+	"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)	\
+		" +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
+		" +${filesize};cp.b ${fileaddr} "			\
+		__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"	\
+	"upd=run load update\0"						\
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/mpr2.h b/qemu/roms/u-boot/include/configs/mpr2.h
new file mode 100644
index 000000000..8ae497c6d
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/mpr2.h
@@ -0,0 +1,75 @@
+/*
+ * Configuation settings for MPR2
+ *
+ * Copyright (C) 2008
+ * Mark Jonas <mark.jonas@de.bosch.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MPR2_H
+#define __MPR2_H
+
+/* Supported commands */
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_FLASH
+
+/* Default environment variables */
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_BOOTARGS		"console=ttySC0,115200"
+#define CONFIG_BOOTFILE		"/boot/zImage"
+#define CONFIG_LOADADDR		0x8E000000
+#define CONFIG_VERSION_VARIABLE
+
+/* CPU and platform */
+#define CONFIG_CPU_SH7720	1
+#define CONFIG_MPR2		1
+
+/* U-Boot internals */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_SYS_CBSIZE		256	/* Buffer size for input from the Console */
+#define CONFIG_SYS_PBSIZE		256	/* Buffer size for Console output */
+#define CONFIG_SYS_MAXARGS		16	/* max args accepted for monitor commands */
+#define CONFIG_SYS_BARGSIZE		512	/* Buffer size for Boot Arguments passed to kernel */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }	/* List of legal baudrate settings for this board */
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(128 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)
+
+#define CONFIG_SYS_TEXT_BASE	0x8FFC0000
+
+/* Memory */
+#define CONFIG_SYS_SDRAM_BASE		0x8C000000
+#define CONFIG_SYS_SDRAM_SIZE		(64 * 1024 * 1024)
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
+
+/* Flash */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BASE		0xA0000000
+#define CONFIG_SYS_MAX_FLASH_SECT	256
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	(128 * 1024)
+#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500
+
+/* Clocks */
+#define CONFIG_SYS_CLK_FREQ	24000000
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_TMU_CLK_DIV		4	/* 4 (default), 16, 64, 256 or 1024 */
+
+/* UART */
+#define CONFIG_SCIF_CONSOLE	1
+#define CONFIG_CONS_SCIF0	1
+
+#endif	/* __MPR2_H */
diff --git a/qemu/roms/u-boot/include/configs/ms7720se.h b/qemu/roms/u-boot/include/configs/ms7720se.h
new file mode 100644
index 000000000..585d68f20
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/ms7720se.h
@@ -0,0 +1,109 @@
+/*
+ * Configuation settings for the Hitachi Solution Engine 7720
+ *
+ * Copyright (C) 2007 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MS7720SE_H
+#define __MS7720SE_H
+
+#define CONFIG_CPU_SH7720	1
+#define CONFIG_MS7720SE		1
+
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_PCMCIA
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_EXT2
+
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_BOOTARGS		"console=ttySC0,115200"
+#define CONFIG_BOOTFILE		"/boot/zImage"
+#define CONFIG_LOADADDR		0x8E000000
+
+#define CONFIG_VERSION_VARIABLE
+#undef  CONFIG_SHOW_BOOT_PROGRESS
+
+/* MEMORY */
+#define MS7720SE_SDRAM_BASE		0x8C000000
+#define MS7720SE_FLASH_BASE_1		0xA0000000
+#define MS7720SE_FLASH_BANK_SIZE	(8 * 1024 * 1024)
+
+#define CONFIG_SYS_TEXT_BASE	0x8FFC0000
+#define CONFIG_SYS_LONGHELP		/* undef to save memory	*/
+#define CONFIG_SYS_CBSIZE	256	/* Buffer size for input from the Console */
+#define CONFIG_SYS_PBSIZE	256	/* Buffer size for Console output */
+#define CONFIG_SYS_MAXARGS	16	/* max args accepted for monitor commands */
+/* Buffer size for Boot Arguments passed to kernel */
+#define CONFIG_SYS_BARGSIZE	512
+/* List of legal baudrate settings for this board */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE	1
+#define CONFIG_CONS_SCIF0	1
+
+#define CONFIG_SYS_MEMTEST_START	MS7720SE_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
+
+#define CONFIG_SYS_SDRAM_BASE		MS7720SE_SDRAM_BASE
+#define CONFIG_SYS_SDRAM_SIZE		(64 * 1024 * 1024)
+
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
+#define CONFIG_SYS_MONITOR_BASE	MS7720SE_FLASH_BASE_1
+#define CONFIG_SYS_MONITOR_LEN		(128 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)
+#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
+
+
+/* FLASH */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#undef  CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_SYS_FLASH_EMPTY_INFO	/* print 'E' for empty sector on flinfo */
+
+#define CONFIG_SYS_FLASH_BASE		MS7720SE_FLASH_BASE_1
+
+#define CONFIG_SYS_MAX_FLASH_SECT	150
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	(64 * 1024)
+#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500
+
+/* Board Clock */
+#define CONFIG_SYS_CLK_FREQ	33333333
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_TMU_CLK_DIV		4	/* 4 (default), 16, 64, 256 or 1024 */
+
+/* PCMCIA */
+#define CONFIG_IDE_PCMCIA	1
+#define CONFIG_MARUBUN_PCCARD	1
+#define CONFIG_PCMCIA_SLOT_A	1
+#define CONFIG_SYS_IDE_MAXDEVICE	1
+#define CONFIG_SYS_MARUBUN_MRSHPC	0xb83fffe0
+#define CONFIG_SYS_MARUBUN_MW1		0xb8400000
+#define CONFIG_SYS_MARUBUN_MW2		0xb8500000
+#define CONFIG_SYS_MARUBUN_IO		0xb8600000
+
+#define CONFIG_SYS_PIO_MODE		1
+#define CONFIG_SYS_IDE_MAXBUS		1
+#define CONFIG_DOS_PARTITION	1
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_MARUBUN_IO	/* base address */
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x01F0		/* ide0 offste */
+#define CONFIG_SYS_ATA_DATA_OFFSET	0		/* data reg offset */
+#define CONFIG_SYS_ATA_REG_OFFSET	0		/* reg offset */
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x200		/* alternate register offset */
+#define CONFIG_IDE_SWAP_IO
+
+#endif	/* __MS7720SE_H */
diff --git a/qemu/roms/u-boot/include/configs/ms7722se.h b/qemu/roms/u-boot/include/configs/ms7722se.h
new file mode 100644
index 000000000..1c8ada6c0
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/ms7722se.h
@@ -0,0 +1,115 @@
+/*
+ * Configuation settings for the Hitachi Solution Engine 7722
+ *
+ * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MS7722SE_H
+#define __MS7722SE_H
+
+#define CONFIG_CPU_SH7722	1
+#define CONFIG_MS7722SE		1
+
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_SAVEENV
+
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTARGS		"console=ttySC0,115200 root=1f01"
+
+#define CONFIG_VERSION_VARIABLE
+#undef  CONFIG_SHOW_BOOT_PROGRESS
+
+/* SMC9111 */
+#define CONFIG_SMC91111
+#define CONFIG_SMC91111_BASE    (0xB8000000)
+
+/* MEMORY */
+#define MS7722SE_SDRAM_BASE	(0x8C000000)
+#define MS7722SE_FLASH_BASE_1	(0xA0000000)
+#define MS7722SE_FLASH_BANK_SIZE	(8*1024 * 1024)
+
+#define CONFIG_SYS_TEXT_BASE	0x8FFC0000
+#define CONFIG_SYS_LONGHELP				/* undef to save memory	*/
+#define CONFIG_SYS_CBSIZE		256		/* Buffer size for input from the Console */
+#define CONFIG_SYS_PBSIZE		256		/* Buffer size for Console output */
+#define CONFIG_SYS_MAXARGS		16		/* max args accepted for monitor commands */
+#define CONFIG_SYS_BARGSIZE		512		/* Buffer size for Boot Arguments passed to kernel */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }	/* List of legal baudrate settings for this board */
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE	1
+#define CONFIG_CONS_SCIF0	1
+#undef  CONFIG_SYS_CONSOLE_INFO_QUIET			/* Suppress display of console information at boot */
+#undef  CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#undef  CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+
+#define CONFIG_SYS_MEMTEST_START	(MS7722SE_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
+
+#undef  CONFIG_SYS_ALT_MEMTEST		/* Enable alternate, more extensive, memory test */
+#undef  CONFIG_SYS_MEMTEST_SCRATCH	/* Scratch address used by the alternate memory test */
+
+#undef  CONFIG_SYS_LOADS_BAUD_CHANGE	/* Enable temporary baudrate change while serial download */
+
+#define CONFIG_SYS_SDRAM_BASE	(MS7722SE_SDRAM_BASE)
+#define CONFIG_SYS_SDRAM_SIZE	(64 * 1024 * 1024)	/* maybe more, but if so u-boot doesn't know about it... */
+
+#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)	/* default load address for scripts ?!? */
+
+#define CONFIG_SYS_MONITOR_BASE	(MS7722SE_FLASH_BASE_1)	/* Address of u-boot image
+							in Flash (NOT run time address in SDRAM) ?!? */
+#define CONFIG_SYS_MONITOR_LEN	(128 * 1024)		/* */
+#define CONFIG_SYS_MALLOC_LEN	(256 * 1024)		/* Size of DRAM reserved for malloc() use */
+#define CONFIG_SYS_BOOTMAPSZ	(8 * 1024 * 1024)
+
+/* FLASH */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#undef  CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_SYS_FLASH_EMPTY_INFO			/* print 'E' for empty sector on flinfo */
+
+#define CONFIG_SYS_FLASH_BASE		(MS7722SE_FLASH_BASE_1)	/* Physical start address of Flash memory */
+
+#define CONFIG_SYS_MAX_FLASH_SECT	150		/* Max number of sectors on each
+							Flash chip */
+
+/* if you use all NOR Flash , you change dip-switch. Please see MS7722SE01 Manual. */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE + (0 * MS7722SE_FLASH_BANK_SIZE), \
+				  CONFIG_SYS_FLASH_BASE + (1 * MS7722SE_FLASH_BANK_SIZE), \
+				}
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(3 * 1000)	/* Timeout for Flash erase operations (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(3 * 1000)	/* Timeout for Flash write operations (in ms) */
+#define CONFIG_SYS_FLASH_LOCK_TOUT	(3 * 1000)	/* Timeout for Flash set sector lock bit operations (in ms) */
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	(3 * 1000)	/* Timeout for Flash clear lock bit operations (in ms) */
+
+#undef  CONFIG_SYS_FLASH_PROTECTION			/* Use hardware flash sectors protection instead of U-Boot software protection */
+
+#undef  CONFIG_SYS_DIRECT_FLASH_TFTP
+
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE	1
+#define CONFIG_ENV_SECT_SIZE	(8 * 1024)
+#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE))
+#define CONFIG_ENV_OFFSET		(CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)	/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
+
+/* Board Clock */
+#define CONFIG_SYS_CLK_FREQ	33333333
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_TMU_CLK_DIV		(4)	/* 4 (default), 16, 64, 256 or 1024 */
+
+#endif	/* __MS7722SE_H */
diff --git a/qemu/roms/u-boot/include/configs/ms7750se.h b/qemu/roms/u-boot/include/configs/ms7750se.h
new file mode 100644
index 000000000..4cf8efeca
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/ms7750se.h
@@ -0,0 +1,86 @@
+/*
+ * Configuation settings for the Hitachi Solution Engine 7750
+ *
+ * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MS7750SE_H
+#define __MS7750SE_H
+
+#define CONFIG_CPU_SH7750	1
+/* #define CONFIG_CPU_SH7751	1 */
+/* #define CONFIG_CPU_TYPE_R	1 */
+#define CONFIG_MS7750SE		1
+#define __LITTLE_ENDIAN__	1
+
+/*
+ * Command line configuration.
+ */
+/*#include <config_cmd_default.h>*/
+
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_SAVEENV
+
+#define CONFIG_SCIF_CONSOLE	1
+#define CONFIG_BAUDRATE		38400
+#define CONFIG_CONS_SCIF1	1
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_BOOTDELAY	-1
+#define CONFIG_BOOTARGS		"console=ttySC0,38400"
+#define CONFIG_ENV_OVERWRITE	1
+
+/* SDRAM */
+#define CONFIG_SYS_SDRAM_BASE		(0x8C000000)
+#define CONFIG_SYS_SDRAM_SIZE		(64 * 1024 * 1024)
+
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_PBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE		512
+
+#define CONFIG_SYS_TEXT_BASE		0x8FFC0000
+#define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_TEXT_BASE - 0x100000)
+
+/* NOR Flash */
+/* #define CONFIG_SYS_FLASH_BASE		(0xA1000000)*/
+#define CONFIG_SYS_FLASH_BASE		(0xA0000000)
+#define CONFIG_SYS_MAX_FLASH_BANKS	(1)	/* Max number of
+					 * Flash memory banks
+					 */
+#define CONFIG_SYS_MAX_FLASH_SECT	142
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE)	/* Address of u-boot image in Flash */
+#define CONFIG_SYS_MONITOR_LEN		(128 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)		/* Size of DRAM reserved for malloc() use */
+
+#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
+#define CONFIG_SYS_RX_ETH_BUFFER	(8)
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#undef CONFIG_SYS_FLASH_CFI_BROKEN_TABLE
+#undef  CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_SYS_FLASH_EMPTY_INFO				/* print 'E' for empty sector on flinfo */
+
+
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	0x20000
+#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500
+
+/* Board Clock */
+#define CONFIG_SYS_CLK_FREQ	33333333
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_TMU_CLK_DIV		4
+
+#endif /* __MS7750SE_H */
diff --git a/qemu/roms/u-boot/include/configs/mt_ventoux.h b/qemu/roms/u-boot/include/configs/mt_ventoux.h
new file mode 100644
index 000000000..e7afd07b9
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/mt_ventoux.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (C) 2011
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ *
+ * Configuration settings for the Teejet mt_ventoux board.
+ *
+ * Copyright (C) 2009 TechNexion Ltd.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "tam3517-common.h"
+
+#undef CONFIG_SYS_MALLOC_LEN
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10) + \
+					6 * 1024 * 1024)
+
+#define MACH_TYPE_AM3517_MT_VENTOUX	3832
+#define CONFIG_MACH_TYPE	MACH_TYPE_AM3517_MT_VENTOUX
+
+#define CONFIG_BOOTDELAY	10
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_AUTO_COMPLETE
+
+#define CONFIG_OMAP3_GPIO_4
+#define CONFIG_HOSTNAME mt_ventoux
+
+/*
+ * Miscellaneous configurable options
+ */
+#define V_PROMPT			"mt_ventoux => "
+#define CONFIG_SYS_PROMPT		V_PROMPT
+
+/*
+ * Set its own mtdparts, different from common
+ */
+#undef MTDIDS_DEFAULT
+#undef MTDPARTS_DEFAULT
+#define MTDIDS_DEFAULT		"nand0=omap2-nand.0"
+#define MTDPARTS_DEFAULT	"mtdparts=omap2-nand.0:512k(MLO)," \
+				"1m(u-boot),256k(env1)," \
+				"256k(env2),8m(ubisystem),-(rootfs)"
+
+/*
+ * FPGA
+ */
+#define CONFIG_CMD_FPGA
+#define CONFIG_FPGA
+#define CONFIG_FPGA_XILINX
+#define CONFIG_FPGA_SPARTAN3
+#define CONFIG_SYS_FPGA_PROG_FEEDBACK
+#define CONFIG_SYS_FPGA_WAIT	10000
+#define CONFIG_MAX_FPGA_DEVICES	1
+#define CONFIG_FPGA_DELAY() udelay(1)
+#define CONFIG_SYS_FPGA_PROG_FEEDBACK
+
+#define CONFIG_VIDEO
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_CMD_BMP
+#define CONFIG_VIDEO_OMAP3	/* DSS Support			*/
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+#define	CONFIG_EXTRA_ENV_SETTINGS	CONFIG_TAM3517_SETTINGS \
+	"bootcmd=run net_nfs\0"
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/muas3001.h b/qemu/roms/u-boot/include/configs/muas3001.h
new file mode 100644
index 000000000..7343c947c
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/muas3001.h
@@ -0,0 +1,395 @@
+/*
+ * (C) Copyright 2008
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MUAS3001		1
+
+#define	CONFIG_SYS_TEXT_BASE	0xFF000000
+
+#define CONFIG_CPM2		1	/* Has a CPM2 */
+
+/* Do boardspecific init */
+#define CONFIG_BOARD_EARLY_INIT_R       1
+
+/* enable Watchdog */
+#define CONFIG_WATCHDOG		1
+
+/*
+ * Select serial console configuration
+ *
+ * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ */
+#define	CONFIG_CONS_ON_SMC		/* Console is on SMC         */
+#undef  CONFIG_CONS_ON_SCC		/* It's not on SCC           */
+#undef	CONFIG_CONS_NONE		/* It's not on external UART */
+#if defined(CONFIG_MUAS_DEV_BOARD)
+#define CONFIG_CONS_INDEX	2	/* SMC2 is used for console  */
+#else
+#define CONFIG_CONS_INDEX	1	/* SMC1 is used for console  */
+#endif
+
+/*
+ * Select ethernet configuration
+ *
+ * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
+ * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
+ * SCC, 1-3 for FCC)
+ *
+ * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
+ * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
+ * must be unset.
+ */
+#undef	CONFIG_ETHER_ON_SCC		/* Ethernet is not on SCC */
+#define	CONFIG_ETHER_ON_FCC		/* Ethernet is on FCC     */
+#undef	CONFIG_ETHER_NONE		/* No external Ethernet   */
+
+#define CONFIG_ETHER_INDEX	1
+#define CONFIG_ETHER_ON_FCC1
+#define CONFIG_HAS_ETH0
+#define FCC_ENET
+
+/*
+ * - Rx-CLK is CLK11
+ * - Tx-CLK is CLK12
+ */
+# define CONFIG_SYS_CMXFCR_VALUE1	(CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12)
+# define CONFIG_SYS_CMXFCR_MASK1	(CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
+/*
+ * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
+ */
+# define CONFIG_SYS_CPMFCR_RAMTYPE	(0)
+/* know on local Bus */
+/* define CONFIG_SYS_CPMFCR_RAMTYPE	(CPMFCR_DTB | CPMFCR_BDB) */
+/*
+ * - Enable Full Duplex in FSMR
+ */
+# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+
+#define CONFIG_MII			/* MII PHY management		*/
+#define CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
+# define CONFIG_SYS_PHY_ADDR		1
+/*
+ * GPIO pins used for bit-banged MII communications
+ */
+#define MDIO_PORT	0		/* Port A */
+#define MDIO_DECLARE	volatile ioport_t *iop = ioport_addr ( \
+				(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
+#define MDC_DECLARE	MDIO_DECLARE
+
+
+#define CONFIG_SYS_MDIO_PIN	0x00200000	/* PA10 */
+#define CONFIG_SYS_MDC_PIN	0x00400000	/* PA9  */
+
+#define MDIO_ACTIVE	(iop->pdir |=  CONFIG_SYS_MDIO_PIN)
+#define MDIO_TRISTATE	(iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
+#define MDIO_READ	((iop->pdat &  CONFIG_SYS_MDIO_PIN) != 0)
+
+#define MDIO(bit)	if(bit) iop->pdat |=  CONFIG_SYS_MDIO_PIN; \
+			else	iop->pdat &= ~CONFIG_SYS_MDIO_PIN
+
+#define MDC(bit)	if(bit) iop->pdat |=  CONFIG_SYS_MDC_PIN; \
+			else	iop->pdat &= ~CONFIG_SYS_MDC_PIN
+
+#define MIIDELAY	udelay(1)
+
+#ifndef CONFIG_8260_CLKIN
+#define CONFIG_8260_CLKIN	66000000	/* in Hz */
+#endif
+
+#define CONFIG_BAUDRATE		115200
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+
+/*
+ * Default environment settings
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS						\
+	"netdev=eth0\0"								\
+	"u-boot_addr_r=100000\0"						\
+	"kernel_addr_r=200000\0"						\
+	"fdt_addr_r=400000\0"							\
+	"rootpath=/opt/eldk/ppc_6xx\0"						\
+	"u-boot=muas3001/u-boot.bin\0"						\
+	"bootfile=muas3001/uImage\0"						\
+	"fdt_file=muas3001/muas3001.dtb\0"					\
+	"ramdisk_file=uRamdisk\0"						\
+	"load=tftp ${u-boot_addr_r} ${u-boot}\0"				\
+	"update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; "		\
+		"cp.b ${u-boot_addr_r} ff000000 ${filesize};"			\
+		"prot on ff000000 ff03ffff\0"					\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"				\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "				\
+		"nfsroot=${serverip}:${rootpath}\0"				\
+	"addcons=setenv bootargs ${bootargs} console=ttyCPM0,${baudrate}\0"	\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"			\
+	"addip=setenv bootargs ${bootargs} "					\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:"			\
+		"${netmask}:${hostname}:${netdev}:off panic=1\0"		\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "				\
+		"tftp ${fdt_addr_r} ${fdt_file}; run nfsargs addip addcons;"	\
+		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"			\
+	"net_self=tftp ${kernel_addr_r} ${bootfile}; "				\
+		"tftp ${fdt_addr_r} ${fdt_file}; "				\
+		"tftp ${ramdisk_addr} ${ramdisk_file}; "			\
+		"run ramargs addip; "						\
+		"bootm ${kernel_addr_r} ${ramdisk_addr} ${fdt_addr_r}\0"	\
+	"ramdisk_addr=ff210000\0"						\
+	"kernel_addr=ff050000\0"						\
+	"fdt_addr=ff200000\0"							\
+	"flash_self=run ramargs addip addcons;bootm ${kernel_addr}"		\
+	" ${ramdisk_addr} ${fdt_addr}\0"					\
+	"updateramdisk=era ${ramdisk_addr} +1f0000;tftpb ${kernel_addr_r}"	\
+	" ${ramdisk_file};"							\
+	"cp.b ${kernel_addr_r} ${ramdisk_addr} ${filesize}\0"			\
+	"updatekernel=era ${kernel_addr} +1b0000;tftpb ${kernel_addr_r}"	\
+	" ${bootfile};"								\
+	"cp.b ${kernel_addr_r} ${kernel_addr} ${filesize}\0"			\
+	"updatefdt=era ${fdt_addr} +10000;tftpb ${fdt_addr_r} ${fdt_file};"	\
+	"cp.b ${fdt_addr_r} ${fdt_addr} ${filesize}\0"				\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run net_nfs"
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size  */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size  */
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
+
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFF000000
+#define CONFIG_SYS_FLASH_SIZE		32
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sects on one chip */
+
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256KB for Monitor */
+
+#define CONFIG_ENV_IS_IN_FLASH
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#endif /* CONFIG_ENV_IS_IN_FLASH */
+
+/*
+ * I2C Bus
+ */
+#define CONFIG_HARD_I2C		1	/* To enable I2C support	*/
+#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed and slave address	*/
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+
+#define	CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+/* I2C SYSMON (LM75, AD7414 is almost compatible)                       */
+#define	CONFIG_DTT_LM75		1	/* ON Semi's LM75               */
+#define	CONFIG_DTT_SENSORS	{0}	/* Sensor addresses             */
+#define	CONFIG_SYS_DTT_MAX_TEMP	70
+#define	CONFIG_SYS_DTT_LOW_TEMP	-30
+#define	CONFIG_SYS_DTT_HYSTERESIS	3
+
+#define CONFIG_SYS_IMMR		0xF0000000
+#define CONFIG_SYS_DEFAULT_IMMR	0x0F010000
+
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/* Hard reset configuration word */
+#define CONFIG_SYS_HRCW_MASTER		0x0E028200	/* BPS=11 CIP=1 ISB=010 BMS=1 */
+
+/* No slaves */
+#define CONFIG_SYS_HRCW_SLAVE1 	0
+#define CONFIG_SYS_HRCW_SLAVE2 	0
+#define CONFIG_SYS_HRCW_SLAVE3 	0
+#define CONFIG_SYS_HRCW_SLAVE4 	0
+#define CONFIG_SYS_HRCW_SLAVE5 	0
+#define CONFIG_SYS_HRCW_SLAVE6 	0
+#define CONFIG_SYS_HRCW_SLAVE7 	0
+
+#define CONFIG_SYS_MALLOC_LEN		(4096 << 10)	/* Reserve 4 MB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPUs */
+#if defined(CONFIG_CMD_KGDB)
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+#define CONFIG_SYS_HID0_INIT		0
+#define CONFIG_SYS_HID0_FINAL		(HID0_ICE | HID0_IFEM | HID0_ABE)
+
+#define CONFIG_SYS_HID2		0
+
+#define CONFIG_SYS_SIUMCR		0x00200000
+#define CONFIG_SYS_BCR			0x004c0000
+#define CONFIG_SYS_SCCR		0x0
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control                             4-35
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
+#else
+#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
+			 SYPCR_SWRI|SYPCR_SWP)
+#endif /* CONFIG_WATCHDOG */
+
+/*-----------------------------------------------------------------------
+ * RMR - Reset Mode Register                                     5-5
+ *-----------------------------------------------------------------------
+ * turn on Checkstop Reset Enable
+ */
+#define CONFIG_SYS_RMR         0
+
+/*-----------------------------------------------------------------------
+ * TMCNTSC - Time Counter Status and Control                     4-40
+ *-----------------------------------------------------------------------
+ * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
+ * and enable Time Counter
+ */
+#define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control                 4-42
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
+ * Periodic timer
+ */
+#define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration                         13-7
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RCCR        0
+
+/*
+ * Init Memory Controller:
+ *
+ * Bank Bus     Machine PortSz  Device
+ * ---- ---     ------- ------  ------
+ *  0   60x     GPCM    32 bit  FLASH
+ *  1   60x     SDRAM   64 bit  SDRAM
+ *  4   60x     GPCM    16 bit  I/O Ctrl
+ *
+ */
+/* Bank 0 - FLASH
+ */
+#define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)	|\
+			 BRx_PS_32			|\
+			 BRx_MS_GPCM_P			|\
+			 BRx_V)
+
+#define CONFIG_SYS_OR0_PRELIM (0xff000020)
+
+/* Bank 1 - 60x bus SDRAM
+ */
+#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT	(256 << 20)	/* less than 256 MB */
+
+#define CONFIG_SYS_MPTPR       0x2800
+
+/*-----------------------------------------------------------------------------
+ * Address for Mode Register Set (MRS) command
+ *-----------------------------------------------------------------------------
+ */
+#define CONFIG_SYS_MRS_OFFS	0x00000110
+#define CONFIG_SYS_PSRT        0x13
+
+#define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)  |\
+			 BRx_PS_64                      |\
+			 BRx_MS_SDRAM_P                 |\
+			 BRx_V)
+
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR1_LITTLE
+
+/* SDRAM initialization values
+*/
+#define CONFIG_SYS_OR1_LITTLE	((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+			 ORxS_BPD_4                     |\
+			 ORxS_ROWST_PBI1_A7		|\
+			 ORxS_NUMR_12)
+
+#define CONFIG_SYS_PSDMR_LITTLE	0x004b36a3
+
+#define CONFIG_SYS_OR1_BIG	((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+			 ORxS_BPD_4                     |\
+			 ORxS_ROWST_PBI1_A4		|\
+			 ORxS_NUMR_12)
+
+#define CONFIG_SYS_PSDMR_BIG		0x014f36a3
+
+/* IO on CS4 initialization values
+*/
+#define CONFIG_SYS_IO_BASE	0xc0000000
+#define CONFIG_SYS_IO_SIZE	1
+
+#define CONFIG_SYS_BR4_PRELIM	((CONFIG_SYS_IO_BASE & BRx_BA_MSK) |\
+			 BRx_PS_16 | BRx_MS_GPCM_L | BRx_V)
+
+#define CONFIG_SYS_OR4_PRELIM	(0xfff80020)
+
+#define	CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC	/* "bad" address		*/
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+#define OF_TBCLK		(bd->bi_busfreq / 4)
+#if defined(CONFIG_MUAS_DEV_BOARD)
+#define OF_STDOUT_PATH		"/soc/cpm/serial@11a90"
+#else
+#define OF_STDOUT_PATH		"/soc/cpm/serial@11a80"
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/mucmc52.h b/qemu/roms/u-boot/include/configs/mucmc52.h
new file mode 100644
index 000000000..ff75ead29
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/mucmc52.h
@@ -0,0 +1,126 @@
+/*
+ * (C) Copyright 2008-2009
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * (C) Copyright 2003-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define	CONFIG_MUCMC52		1	/* MUCMC52 board	*/
+#define	CONFIG_HOSTNAME		mucmc52
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xFFF00000
+#endif
+
+#include "manroland/common.h"
+#include "manroland/mpc5200-common.h"
+
+#define	CONFIG_LAST_STAGE_INIT
+/*
+ * Serial console configuration
+ */
+#define	CONFIG_BAUDRATE		38400	/* ... at 38400 bps	*/
+
+#define	CONFIG_CMD_PCI
+
+/*
+ * Flash configuration
+ */
+#define	CONFIG_SYS_MAX_FLASH_SECT	67
+
+/*
+ * Environment settings
+ */
+#define	CONFIG_ENV_SECT_SIZE	0x20000
+
+/*
+ * Memory map
+ */
+#define	CONFIG_SYS_STATUS1_BASE	0x80600200
+#define	CONFIG_SYS_STATUS2_BASE	0x80600300
+#define	CONFIG_SYS_PMI_UNI_BASE	0x80800000
+#define	CONFIG_SYS_PMI_BROAD_BASE	0x80810000
+
+/*
+ * GPIO configuration
+ */
+#define	CONFIG_SYS_GPS_PORT_CONFIG	0x8D550644
+
+#define	CONFIG_SYS_MEMTEST_START	0x00100000
+#define	CONFIG_SYS_MEMTEST_END		0x00f00000
+
+#define	CONFIG_SYS_LOAD_ADDR		0x100000
+
+#define	CONFIG_SYS_BOOTCS_CFG		0x0004FB00
+
+/* 8Mbit SRAM @0x80100000 */
+#define	CONFIG_SYS_CS1_SIZE		0x00100000
+#define	CONFIG_SYS_CS1_CFG		0x00019B00
+
+#define CONFIG_SYS_SRAM_SIZE		CONFIG_SYS_CS1_SIZE
+
+/* FRAM 32Kbyte @0x80700000 */
+#define	CONFIG_SYS_CS2_START		0x80700000
+#define	CONFIG_SYS_CS2_SIZE		0x00008000
+#define	CONFIG_SYS_CS2_CFG		0x00019800
+
+/* Display H1, Status Inputs, EPLD @0x80600000 */
+#define	CONFIG_SYS_CS3_START		0x80600000
+#define	CONFIG_SYS_CS3_SIZE		0x00100000
+#define	CONFIG_SYS_CS3_CFG		0x00019800
+
+/* PMI Unicast 32Kbyte @0x80800000 */
+#define	CONFIG_SYS_CS6_START		CONFIG_SYS_PMI_UNI_BASE
+#define	CONFIG_SYS_CS6_SIZE		0x00008000
+#define	CONFIG_SYS_CS6_CFG		0xFFFFF930
+
+/* PMI Broadcast 32Kbyte @0x80810000 */
+#define	CONFIG_SYS_CS7_START		CONFIG_SYS_PMI_BROAD_BASE
+#define	CONFIG_SYS_CS7_SIZE		0x00008000
+#define	CONFIG_SYS_CS7_CFG		0xFF00F930
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+#define	CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 2 drives per IDE bus	*/
+
+/*
+ * PCI Mapping:
+ * 0x40000000 - 0x4fffffff - PCI Memory
+ * 0x50000000 - 0x50ffffff - PCI IO Space
+ */
+#define	CONFIG_PCI		1
+#define	CONFIG_PCI_PNP		1
+#define	CONFIG_PCI_SCAN_SHOW	1
+#define	CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1
+
+#define	CONFIG_PCI_MEM_BUS	0x40000000
+#define	CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#define	CONFIG_PCI_MEM_SIZE	0x10000000
+
+#define	CONFIG_PCI_IO_BUS	0x50000000
+#define	CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define	CONFIG_PCI_IO_SIZE	0x01000000
+
+#define	CONFIG_SYS_ISA_IO		CONFIG_PCI_IO_BUS
+
+/*---------------------------------------------------------------------*/
+/* Display addresses						       */
+/*---------------------------------------------------------------------*/
+
+#define	CONFIG_SYS_DISP_CHR_RAM	(CONFIG_SYS_DISPLAY_BASE + 0x38)
+#define	CONFIG_SYS_DISP_CWORD		(CONFIG_SYS_DISPLAY_BASE + 0x30)
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/munices.h b/qemu/roms/u-boot/include/configs/munices.h
new file mode 100644
index 000000000..e65a14af2
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/munices.h
@@ -0,0 +1,200 @@
+/*
+ * (C) Copyright 2007
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MPC5200		1	/* This is an MPC5200 CPU */
+#define CONFIG_MPC5200_DDR	1	/* (with DDR-SDRAM) */
+#define CONFIG_MUNICES		1	/* ... on MUNICes board */
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xFFF00000
+#endif
+
+#define CONFIG_SYS_MPC5XXX_CLKIN	33333333 /* ... running at 33.333333MHz */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+
+#if defined(CONFIG_CMD_KGDB)
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
+#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#define	CONFIG_TIMESTAMP	1	/* Print image info with timestamp */
+#define CONFIG_BOOTDELAY	5   /* autoboot after 5 seconds */
+#undef	CONFIG_BOOTARGS
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run net_nfs\" to load Kernel over TFTP and to mount root filesystem over NFS;" \
+	"echo"
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=$(serverip):$(rootpath)\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs $(bootargs) "				\
+		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
+		":$(hostname):$(netdev):off panic=5\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm $(kernel_addr)\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm $(kernel_addr) $(ramdisk_addr)\0"		\
+	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_6xx\0"					\
+	"bootfile=/tftpboot/munices/u-boot.bin\0"			\
+	"update=tftpboot 200000 ${bootfile};protect off fff00000 fff3ffff;" \
+	"erase fff00000 fff3ffff; cp.b 200000 FFF00000 ${filesize}\0"	\
+	""
+#define CONFIG_BOOTCOMMAND	"run net_nfs"
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#define  CONFIG_SYS_IPBSPEED_133		/* define for 133MHz speed */
+#if defined(CONFIG_SYS_IPBSPEED_133)
+/*
+ * PCI Bus clocking configuration
+ *
+ * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
+ * CONFIG_SYS_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
+ * been tested with a IPB Bus Clock of 66 MHz.
+ */
+#define CONFIG_SYS_PCISPEED_66		/* define for 66MHz speed */
+#else
+#undef CONFIG_SYS_PCISPEED_66			/* for 33MHz speed */
+#endif
+
+/*
+ * Memory map
+ */
+#define CONFIG_SYS_MBAR		0xF0000000 /* MBAR hast to be switched by other bootloader or debugger config  */
+
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+/* Use SRAM until RAM will be available */
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*
+ * Flash configuration
+ */
+#define CONFIG_SYS_FLASH_BASE		0xFF000000
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_SIZE		0x01000000 /* 16 MByte */
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	 /* max num of flash banks (= chip selects) */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	/* not supported yet for AMD */
+
+/*
+ * Chip selects configuration
+ */
+/* Boot Chipselect */
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_CFG		0x00047800
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_OFFSET		0x40000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_TEXT_BASE + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SECT_SIZE	0x20000
+#define CONFIG_ENV_SIZE		0x4000
+#define CONFIG_ENV_OFFSET_REDUND   (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_SYS_TEXT_BASE + CONFIG_ENV_OFFSET_REDUND)
+#define CONFIG_ENV_SIZE_REDUND     (CONFIG_ENV_SIZE)
+#define CONFIG_ENV_OVERWRITE	1
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC	1
+#define CONFIG_MPC5xxx_FEC_MII100
+#define CONFIG_PHY_ADDR		0x01
+#define CONFIG_MII		1
+
+/*
+ * GPIO configuration
+ */
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x00058044 /* PSC1=UART, PSC2=UART ; Ether=100MBit with MD
+						no PCI */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x200000	/* default load address */
+
+#define CONFIG_DISPLAY_BOARDINFO 1
+#define CONFIG_CMDLINE_EDITING  1
+
+/*
+ * Various low-level settings
+ */
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
+
+#define CONFIG_SYS_CS_BURST		0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE	0x33333333
+#define CONFIG_SYS_RESET_ADDRESS	0xff000000
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+#define OF_CPU			"PowerPC,5200@0"
+#define OF_TBCLK		(bd->bi_busfreq / 4)
+#define OF_SOC                  "soc5200@f0000000"
+#define OF_STDOUT_PATH		"/soc5200@f0000000/serial@2000"
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/mv-common.h b/qemu/roms/u-boot/include/configs/mv-common.h
new file mode 100644
index 000000000..721b75dae
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/mv-common.h
@@ -0,0 +1,154 @@
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * This file contains Marvell Board Specific common defincations.
+ * This file should be included in board config header file.
+ *
+ * It supports common definations for Kirkwood platform
+ * TBD: support for Orion5X platforms
+ */
+
+#ifndef _MV_COMMON_H
+#define _MV_COMMON_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_MARVELL		1
+
+/*
+ * Custom CONFIG_SYS_TEXT_BASE can be done in <board>.h
+ */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define	CONFIG_SYS_TEXT_BASE	0x00600000
+#endif /* CONFIG_SYS_TEXT_BASE */
+
+/* additions for new ARM relocation support */
+#define CONFIG_SYS_SDRAM_BASE	0x00000000
+
+/*
+ * CLKs configurations
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_TCLK
+#define CONFIG_SYS_NS16550_COM1		MV_UART_CONSOLE_BASE
+
+/*
+ * Serial Port configuration
+ * The following definitions let you select what serial you want to use
+ * for your console driver.
+ */
+
+#define CONFIG_CONS_INDEX	1	/*Console on UART0 */
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, \
+					  115200,230400, 460800, 921600 }
+/* auto boot */
+#define CONFIG_BOOTDELAY	3	/* default enable autoboot */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs  */
+#define CONFIG_INITRD_TAG	1	/* enable INITRD tag */
+#define CONFIG_SETUP_MEMORY_TAGS 1	/* enable memory tag */
+
+#define	CONFIG_SYS_PROMPT	"Marvell>> "	/* Command Prompt */
+#define	CONFIG_SYS_CBSIZE	1024	/* Console I/O Buff Size */
+#define	CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE \
+		+sizeof(CONFIG_SYS_PROMPT) + 16)	/* Print Buff */
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN	(1024 * 1024 * 4) /* 4MiB for malloc() */
+
+/*
+ * Other required minimal configurations
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_CONSOLE_INFO_QUIET	/* some code reduction */
+#define CONFIG_ARCH_CPU_INIT	/* call arch_cpu_init() */
+#define CONFIG_ARCH_MISC_INIT	/* call arch_misc_init() */
+#define CONFIG_BOARD_EARLY_INIT_F /* call board_init_f for early inits */
+#define CONFIG_DISPLAY_CPUINFO	/* Display cpu info */
+#define CONFIG_SYS_LOAD_ADDR	0x00800000	/* default load adr- 8M */
+#define CONFIG_SYS_MEMTEST_START 0x00800000	/* 8M */
+#define CONFIG_SYS_MEMTEST_END	0x00ffffff	/*(_16M -1) */
+#define CONFIG_SYS_RESET_ADDRESS 0xffff0000	/* Rst Vector Adr */
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+
+/* ====> Include platform Common Definitions */
+#include <asm/arch/config.h>
+
+/*
+ * DRAM Banks configuration, Custom config can be done in <board>.h
+ */
+#ifndef CONFIG_NR_DRAM_BANKS
+#define CONFIG_NR_DRAM_BANKS	CONFIG_NR_DRAM_BANKS_MAX
+#else
+#if (CONFIG_NR_DRAM_BANKS > CONFIG_NR_DRAM_BANKS_MAX)
+#error CONFIG_NR_DRAM_BANKS Configurated more than available
+#endif
+#endif /* CONFIG_NR_DRAM_BANKS */
+
+/* ====> Include driver Common Definitions */
+/*
+ * Common NAND configuration
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#endif
+
+/*
+ * Common SPI Flash configuration
+ */
+#ifdef CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH		1
+#define CONFIG_SPI_FLASH_MACRONIX	1
+#endif
+
+/*
+ * Common USB/EHCI configuration
+ */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI		/* Enable EHCI USB support */
+#define CONFIG_USB_STORAGE
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+#define CONFIG_SUPPORT_VFAT
+#endif /* CONFIG_CMD_USB */
+
+/*
+ * File system
+ */
+#ifdef CONFIG_SYS_MVFS
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_LZO
+#endif
+
+#endif /* _MV_COMMON_H */
diff --git a/qemu/roms/u-boot/include/configs/mv88f6281gtw_ge.h b/qemu/roms/u-boot/include/configs/mv88f6281gtw_ge.h
new file mode 100644
index 000000000..f6c06eea2
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/mv88f6281gtw_ge.h
@@ -0,0 +1,90 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CONFIG_MV88F6281GTW_GE_H
+#define _CONFIG_MV88F6281GTW_GE_H
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING	"\nMarvell-MV88F6281GTW_GE"
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_FEROCEON_88FR131	1	/* CPU Core subversion */
+#define CONFIG_KIRKWOOD		1	/* SOC Family Name */
+#define CONFIG_KW88F6281	1	/* SOC Name */
+#define CONFIG_MACH_MV88F6281GTW_GE	/* Machine type */
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_USB
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/* Unwanted stuffs from mv-common.h */
+#undef	CONFIG_CMD_EXT2
+#undef	CONFIG_CMD_JFFS2
+#undef	CONFIG_CMD_FAT
+#undef	CONFIG_CMD_UBI
+#undef	CONFIG_CMD_UBIFS
+#undef	CONFIG_RBTREE
+
+/*
+ *  Environment variables configurations
+ */
+#ifdef CONFIG_SPI_FLASH
+#define CONFIG_ENV_IS_IN_SPI_FLASH	1
+#define CONFIG_ENV_SECT_SIZE		0x10000	/* 64K */
+#else
+#define CONFIG_ENV_IS_NOWHERE		1	/* if env in SDRAM */
+#endif
+#define CONFIG_ENV_SIZE			0x1000	/* 4k */
+#define CONFIG_ENV_ADDR			0x30000
+#define CONFIG_ENV_OFFSET		0x30000	/* env starts here */
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_BOOTCOMMAND		"${x_bootcmd_kernel}; "	\
+	"setenv bootargs ${x_bootargs} ${x_bootargs_root}; "	\
+	"${x_bootcmd_usb}; bootm 0x6400000;"
+
+#define CONFIG_MTDPARTS			"spi0.0:512k(uboot),"	\
+	"512k@512k(psm),2m@1m(kernel),13m@3m(rootfs)\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS	"x_bootargs=console"	\
+	"=ttyS0,115200 mtdparts="CONFIG_MTDPARTS	\
+	"x_bootcmd_kernel=cp.b 0xE8100000 0x6400000 0x200000\0" \
+	"x_bootcmd_usb=usb start\0" \
+	"x_bootargs_root=root=/dev/mtdblock3 ro rootfstype=squashfs\0"
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS	{1, 0}	/* enable port 0 only */
+#define CONFIG_MV88E61XX_SWITCH	/* Enable mv88e61xx switch driver */
+#endif /* CONFIG_CMD_NET */
+
+#endif /* _CONFIG_MV88F6281GTW_GE_H */
diff --git a/qemu/roms/u-boot/include/configs/mx23_olinuxino.h b/qemu/roms/u-boot/include/configs/mx23_olinuxino.h
new file mode 100644
index 000000000..e377fea24
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/mx23_olinuxino.h
@@ -0,0 +1,159 @@
+/*
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __CONFIGS_MX23_OLINUXINO_H__
+#define __CONFIGS_MX23_OLINUXINO_H__
+
+/* System configurations */
+#define CONFIG_MX23				/* i.MX23 SoC */
+#define CONFIG_MACH_TYPE	4105
+
+/* U-Boot Commands */
+#define CONFIG_SYS_NO_FLASH
+#include <config_cmd_default.h>
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_GPIO
+#define CONFIG_CMD_LED
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_USB
+
+/* Memory configuration */
+#define CONFIG_NR_DRAM_BANKS		1		/* 1 bank of DRAM */
+#define PHYS_SDRAM_1			0x40000000	/* Base address */
+#define PHYS_SDRAM_1_SIZE		0x08000000	/* Max 128 MB RAM */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+
+/* Environment */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OVERWRITE
+
+/* Environment is in MMC */
+#if defined(CONFIG_CMD_MMC) && defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_ENV_OFFSET	(256 * 1024)
+#define CONFIG_ENV_SIZE		(16 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV	0
+#endif
+
+/* Status LED */
+#define CONFIG_STATUS_LED
+#define CONFIG_GPIO_LED
+#define CONFIG_BOARD_SPECIFIC_LED
+#define STATUS_LED_BOOT		0
+#define STATUS_LED_BIT		MX23_PAD_SSP1_DETECT__GPIO_2_1
+#define STATUS_LED_STATE	STATUS_LED_ON
+#define STATUS_LED_PERIOD	(CONFIG_SYS_HZ / 2)
+
+/* USB */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_EHCI_MXS_PORT0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#define CONFIG_USB_STORAGE
+#endif
+
+/* Ethernet */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_SMSC95XX
+#endif
+
+/* Booting Linux */
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_LOADADDR		0x42000000
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+
+/* Extra Environment */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"update_sd_firmware_filename=u-boot.sd\0" \
+	"update_sd_firmware="		/* Update the SD firmware partition */ \
+		"if mmc rescan ; then "	\
+		"if tftp ${update_sd_firmware_filename} ; then " \
+		"setexpr fw_sz ${filesize} / 0x200 ; "	/* SD block size */ \
+		"setexpr fw_sz ${fw_sz} + 1 ; "	\
+		"mmc write ${loadaddr} 0x800 ${fw_sz} ; " \
+		"fi ; "	\
+		"fi\0" \
+	"script=boot.scr\0"	\
+	"uimage=uImage\0" \
+	"console=ttyAMA0\0" \
+	"fdt_file=imx23-olinuxino.dtb\0" \
+	"fdt_addr=0x41000000\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"mmcdev=0\0" \
+	"mmcpart=2\0" \
+	"mmcroot=/dev/mmcblk0p3 rw rootwait\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript="  \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; "	\
+		"source\0" \
+	"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootm ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootm; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootm; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"usb start; " \
+		"run netargs; "	\
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${uimage}; " \
+		"if test ${boot_fdt} = yes; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootm ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootm; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi;" \
+			"fi; " \
+		"else " \
+			"bootm; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loaduimage; then " \
+				"run mmcboot; " \
+			"else run netboot; " \
+			"fi; " \
+		"fi; " \
+	"else run netboot; fi"
+
+/* The rest of the configuration is shared */
+#include <configs/mxs.h>
+
+#endif /* __CONFIGS_MX23_OLINUXINO_H__ */
diff --git a/qemu/roms/u-boot/include/configs/mx23evk.h b/qemu/roms/u-boot/include/configs/mx23evk.h
new file mode 100644
index 000000000..b496892f0
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/mx23evk.h
@@ -0,0 +1,135 @@
+/*
+ * Freescale i.MX23 EVK board config
+ *
+ * Copyright (C) 2013 Otavio Salvador <otavio@ossystems.com.br>
+ * on behalf of O.S. Systems Software LTDA.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __CONFIGS_MX23EVK_H__
+#define __CONFIGS_MX23EVK_H__
+
+/* System configurations */
+#define CONFIG_MX23				/* i.MX23 SoC */
+#define CONFIG_MACH_TYPE	MACH_TYPE_MX23EVK
+
+/* U-Boot Commands */
+#define CONFIG_SYS_NO_FLASH
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_GPIO
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_VIDEO
+
+/* Memory configuration */
+#define CONFIG_NR_DRAM_BANKS		1		/* 1 bank of DRAM */
+#define PHYS_SDRAM_1			0x40000000	/* Base address */
+#define PHYS_SDRAM_1_SIZE		0x08000000	/* Max 128 MB RAM */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+
+/* Environment */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_IS_IN_MMC
+
+/* Environment is in MMC */
+#if defined(CONFIG_CMD_MMC) && defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_ENV_OFFSET	(256 * 1024)
+#define CONFIG_ENV_SIZE		(16 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV	0
+#endif
+
+/* USB */
+#ifdef	CONFIG_CMD_USB
+#define CONFIG_EHCI_MXS_PORT0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#define CONFIG_USB_STORAGE
+#endif
+
+/* Framebuffer support */
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_CMD_BMP
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(512 << 10)
+#endif
+
+/* Boot Linux */
+#define CONFIG_BOOTDELAY	1
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_LOADADDR		0x42000000
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+
+/* Extra Environments */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"update_sd_firmware_filename=u-boot.sd\0" \
+	"update_sd_firmware="		/* Update the SD firmware partition */ \
+		"if mmc rescan ; then "	\
+		"if tftp ${update_sd_firmware_filename} ; then " \
+		"setexpr fw_sz ${filesize} / 0x200 ; "	/* SD block size */ \
+		"setexpr fw_sz ${fw_sz} + 1 ; "	\
+		"mmc write ${loadaddr} 0x800 ${fw_sz} ; " \
+		"fi ; "	\
+		"fi\0" \
+	"script=boot.scr\0"	\
+	"image=zImage\0" \
+	"console=ttyAMA0\0" \
+	"fdt_file=imx23-evk.dtb\0" \
+	"fdt_addr=0x41000000\0" \
+	"boot_fdt=try\0" \
+	"mmcdev=0\0" \
+	"mmcpart=2\0" \
+	"mmcroot=/dev/mmcblk0p3 rw rootwait\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript="  \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; "	\
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loadimage; then " \
+				"run mmcboot; " \
+			"else " \
+				"echo ERR: Fail to boot from MMC; " \
+			"fi; " \
+		"fi; " \
+	"else exit; fi"
+
+/* The rest of the configuration is shared */
+#include <configs/mxs.h>
+
+#endif /* __CONFIGS_MX23EVK_H__ */
diff --git a/qemu/roms/u-boot/include/configs/mx25pdk.h b/qemu/roms/u-boot/include/configs/mx25pdk.h
new file mode 100644
index 000000000..aff2419f8
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/mx25pdk.h
@@ -0,0 +1,236 @@
+/*
+ * (C) Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+
+/* High Level Configuration Options */
+
+#define CONFIG_MX25
+#define CONFIG_SYS_TEXT_BASE		0x81200000
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_SYS_TIMER_RATE		32768
+#define CONFIG_SYS_TIMER_COUNTER	\
+	(&((struct gpt_regs *)IMX_GPT1_BASE)->counter)
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#define CONFIG_MACH_TYPE	MACH_TYPE_MX25_3DS
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+
+/* Physical Memory Map */
+
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM_1		0x80000000
+#define PHYS_SDRAM_1_SIZE	(64 * 1024 * 1024)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR	IMX_RAM_BASE
+#define CONFIG_SYS_INIT_RAM_SIZE	IMX_RAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Memory Test */
+#define CONFIG_SYS_MEMTEST_START	(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE/2)
+#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
+
+/* Serial Info */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	UART1_BASE
+#define CONFIG_CONS_INDEX	1	/* use UART0 for console */
+#define CONFIG_BAUDRATE		115200	/* Default baud rate */
+
+/* No NOR flash present */
+#define CONFIG_ENV_OFFSET      (6 * 64 * 1024)
+#define CONFIG_ENV_SIZE        (8 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+/* U-Boot general configuration */
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size  */
+/* Print buffer sz */
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
+		sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+
+/* U-Boot commands */
+#include <config_cmd_default.h>
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+
+/* Ethernet */
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_MXC_PHYADDR		0x1f
+#define CONFIG_MII
+#define CONFIG_CMD_NET
+#define CONFIG_ENV_OVERWRITE
+
+/* ESDHC driver */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_ESDHC_NUM	1
+
+/* PMIC Configs */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_FSL
+#define CONFIG_PMIC_FSL_MC34704
+#define CONFIG_SYS_FSL_PMIC_I2C_ADDR	0x54
+
+#define CONFIG_DOS_PARTITION
+
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+
+/* RTC */
+#define CONFIG_RTC_IMXDI
+#define CONFIG_CMD_DATE
+
+/* Ethernet Configs */
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+
+#define CONFIG_BOOTDELAY	1
+
+#define CONFIG_LOADADDR		0x81000000	/* loadaddr env var */
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+
+#define CONFIG_DEFAULT_FDT_FILE		"imx25-pdk.dtb"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"image=zImage\0" \
+	"console=ttymxc0\0" \
+	"splashpos=m,m\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"fdt_addr=0x82000000\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
+	"mmcpart=1\0" \
+	"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
+	"update_sd_firmware_filename=u-boot.imx\0" \
+	"update_sd_firmware=" \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"if mmc dev ${mmcdev}; then "	\
+			"if ${get_cmd} ${update_sd_firmware_filename}; then " \
+				"setexpr fw_sz ${filesize} / 0x200; " \
+				"setexpr fw_sz ${fw_sz} + 1; "	\
+				"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
+			"fi; "	\
+		"fi\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs " \
+	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+		"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	   "mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "else run netboot; " \
+			   "fi; " \
+		   "fi; " \
+	   "else run netboot; fi"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_AUTO_COMPLETE
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	       16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/mx28evk.h b/qemu/roms/u-boot/include/configs/mx28evk.h
new file mode 100644
index 000000000..9b9124ac1
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/mx28evk.h
@@ -0,0 +1,324 @@
+/*
+ * (C) Copyright 2011 Freescale Semiconductor, Inc.
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * Based on m28evk.h:
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __CONFIGS_MX28EVK_H__
+#define __CONFIGS_MX28EVK_H__
+
+/* System configurations */
+#define CONFIG_MX28				/* i.MX28 SoC */
+#define CONFIG_MACH_TYPE	MACH_TYPE_MX28EVK
+
+/* U-Boot Commands */
+#define CONFIG_SYS_NO_FLASH
+#include <config_cmd_default.h>
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_GPIO
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NAND_TRIMFFS
+#define CONFIG_VIDEO
+
+/* Memory configuration */
+#define CONFIG_NR_DRAM_BANKS		1		/* 1 bank of DRAM */
+#define PHYS_SDRAM_1			0x40000000	/* Base address */
+#define PHYS_SDRAM_1_SIZE		0x40000000	/* Max 1 GB RAM */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+
+/* Environment */
+#define CONFIG_ENV_SIZE			(16 * 1024)
+#define CONFIG_ENV_OVERWRITE
+
+/* Environment is in MMC */
+#if defined(CONFIG_CMD_MMC) && defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_ENV_OFFSET		(256 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#endif
+
+/* Environment is in NAND */
+#if defined(CONFIG_CMD_NAND) && defined(CONFIG_ENV_IS_IN_NAND)
+#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
+#define CONFIG_ENV_SECT_SIZE		(128 * 1024)
+#define CONFIG_ENV_RANGE		(512 * 1024)
+#define CONFIG_ENV_OFFSET		0x300000
+#define CONFIG_ENV_OFFSET_REDUND	\
+		(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
+#endif
+
+/* Environemnt is in SPI flash */
+#if defined(CONFIG_CMD_SF) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_SIZE			0x1000		/* 4KB */
+#define CONFIG_ENV_OFFSET		0x40000		/* 256K */
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SECT_SIZE		0x1000
+#define CONFIG_ENV_SPI_CS		0
+#define CONFIG_ENV_SPI_BUS		2
+#define CONFIG_ENV_SPI_MAX_HZ		24000000
+#define CONFIG_ENV_SPI_MODE		SPI_MODE_0
+#endif
+
+/* UBI and NAND partitioning */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT			"nand0=gpmi-nand"
+#define MTDPARTS_DEFAULT			\
+	"mtdparts=gpmi-nand:"			\
+		"3m(bootloader)ro,"		\
+		"512k(environment),"		\
+		"512k(redundant-environment),"	\
+		"4m(kernel),"			\
+		"512k(fdt),"			\
+		"8m(ramdisk),"			\
+		"-(filesystem)"
+#endif
+
+/* FEC Ethernet on SoC */
+#ifdef	CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_NET_MULTI
+#define CONFIG_MX28_FEC_MAC_IN_OCOTP
+#endif
+
+/* RTC */
+#ifdef	CONFIG_CMD_DATE
+#define	CONFIG_RTC_MXS
+#endif
+
+/* USB */
+#ifdef	CONFIG_CMD_USB
+#define CONFIG_EHCI_MXS_PORT1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
+#define	CONFIG_USB_STORAGE
+#define	CONFIG_USB_HOST_ETHER
+#define	CONFIG_USB_ETHER_ASIX
+#define	CONFIG_USB_ETHER_SMSC95XX
+#endif
+
+/* SPI */
+#ifdef CONFIG_CMD_SPI
+#define CONFIG_DEFAULT_SPI_BUS		2
+#define CONFIG_DEFAULT_SPI_MODE		SPI_MODE_0
+
+/* SPI Flash */
+#ifdef CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SF_DEFAULT_BUS		2
+#define CONFIG_SF_DEFAULT_CS		0
+/* this may vary and depends on the installed chip */
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
+#define CONFIG_SF_DEFAULT_SPEED		24000000
+#endif
+
+#endif
+
+/* Framebuffer support */
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_CMD_BMP
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(512 << 10)
+#endif
+
+/* Boot Linux */
+#define CONFIG_BOOTDELAY	1
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_LOADADDR		0x42000000
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+
+/* Extra Environment */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"ubifs_file=filesystem.ubifs\0" \
+	"update_nand_full_filename=u-boot.nand\0" \
+	"update_nand_firmware_filename=u-boot.sb\0"	\
+	"update_nand_firmware_maxsz=0x100000\0"	\
+	"update_nand_stride=0x40\0"	/* MX28 datasheet ch. 12.12 */ \
+	"update_nand_count=0x4\0"	/* MX28 datasheet ch. 12.12 */ \
+	"update_nand_get_fcb_size="	/* Get size of FCB blocks */ \
+		"nand device 0 ; " \
+		"nand info ; " \
+		"setexpr fcb_sz ${update_nand_stride} * ${update_nand_count};" \
+		"setexpr update_nand_fcb ${fcb_sz} * ${nand_writesize}\0" \
+	"update_nand_firmware_full=" /* Update FCB, DBBT and FW */ \
+		"if tftp ${update_nand_full_filename} ; then " \
+		"run update_nand_get_fcb_size ; " \
+		"nand scrub -y 0x0 ${filesize} ; " \
+		"nand write.raw ${loadaddr} 0x0 ${fcb_sz} ; " \
+		"setexpr update_off ${loadaddr} + ${update_nand_fcb} ; " \
+		"setexpr update_sz ${filesize} - ${update_nand_fcb} ; " \
+		"nand write ${update_off} ${update_nand_fcb} ${update_sz} ; " \
+		"fi\0" \
+	"update_nand_firmware="		/* Update only firmware */ \
+		"if tftp ${update_nand_firmware_filename} ; then " \
+		"run update_nand_get_fcb_size ; " \
+		"setexpr fcb_sz ${update_nand_fcb} * 2 ; " /* FCB + DBBT */ \
+		"setexpr fw_sz ${update_nand_firmware_maxsz} * 2 ; " \
+		"setexpr fw_off ${fcb_sz} + ${update_nand_firmware_maxsz};" \
+		"nand erase ${fcb_sz} ${fw_sz} ; " \
+		"nand write ${loadaddr} ${fcb_sz} ${filesize} ; " \
+		"nand write ${loadaddr} ${fw_off} ${filesize} ; " \
+		"fi\0" \
+	"update_nand_kernel="		/* Update kernel */ \
+		"mtdparts default; " \
+		"nand erase.part kernel; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${image}; " \
+		"nand write ${loadaddr} kernel ${filesize}\0" \
+	"update_nand_fdt="		/* Update fdt */ \
+		"mtdparts default; " \
+		"nand erase.part fdt; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${fdt_file}; " \
+		"nand write ${loadaddr} fdt ${filesize}\0" \
+	"update_nand_filesystem="		/* Update filesystem */ \
+		"mtdparts default; " \
+		"nand erase.part filesystem; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${ubifs_file}; " \
+		"ubi part filesystem; " \
+		"ubi create filesystem; " \
+		"ubi write ${loadaddr} filesystem ${filesize}\0" \
+	"nandargs=setenv bootargs console=${console_mainline},${baudrate} " \
+		"rootfstype=ubifs ubi.mtd=6 root=ubi0_0 ${mtdparts}\0" \
+	"nandboot="		/* Boot from NAND */ \
+		"mtdparts default; " \
+		"run nandargs; " \
+		"nand read ${loadaddr} kernel 0x00400000; " \
+		"if test ${boot_fdt} = yes; then " \
+			"nand read ${fdt_addr} fdt 0x00080000; " \
+			"bootz ${loadaddr} - ${fdt_addr}; " \
+		"else " \
+			"if test ${boot_fdt} = no; then " \
+				"bootz; " \
+			"else " \
+				"echo \"ERROR: Set boot_fdt to yes or no.\"; " \
+			"fi; " \
+		"fi\0" \
+	"update_sd_firmware_filename=u-boot.sd\0" \
+	"update_sd_firmware="		/* Update the SD firmware partition */ \
+		"if mmc rescan ; then "	\
+		"if tftp ${update_sd_firmware_filename} ; then " \
+		"setexpr fw_sz ${filesize} / 0x200 ; "	/* SD block size */ \
+		"setexpr fw_sz ${fw_sz} + 1 ; "	\
+		"mmc write ${loadaddr} 0x800 ${fw_sz} ; " \
+		"fi ; "	\
+		"fi\0" \
+	"script=boot.scr\0"	\
+	"image=zImage\0" \
+	"console_fsl=ttyAM0\0" \
+	"console_mainline=ttyAMA0\0" \
+	"fdt_file=imx28-evk.dtb\0" \
+	"fdt_addr=0x41000000\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"mmcdev=0\0" \
+	"mmcpart=2\0" \
+	"mmcroot=/dev/mmcblk0p3 rw rootwait\0" \
+	"mmcargs=setenv bootargs console=${console_mainline},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript="  \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; "	\
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console_mainline},${baudrate} " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs; "	\
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${image}; " \
+		"if test ${boot_fdt} = yes; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi;" \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loadimage; then " \
+				"run mmcboot; " \
+			"else run netboot; " \
+			"fi; " \
+		"fi; " \
+	"else run netboot; fi"
+
+/* The rest of the configuration is shared */
+#include <configs/mxs.h>
+
+#endif /* __CONFIGS_MX28EVK_H__ */
diff --git a/qemu/roms/u-boot/include/configs/mx31ads.h b/qemu/roms/u-boot/include/configs/mx31ads.h
new file mode 100644
index 000000000..51b1a141e
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/mx31ads.h
@@ -0,0 +1,189 @@
+/*
+ * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * Configuration settings for the MX31ADS Freescale board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+
+ /* High Level Configuration Options */
+#define CONFIG_ARM1136		1		/* This is an arm1136 CPU core */
+#define CONFIG_MX31		1		/* in a mx31 */
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_SYS_TEXT_BASE		0xA0000000
+
+#define CONFIG_MACH_TYPE	MACH_TYPE_MX31ADS
+
+/*
+ * Disabled for now due to build problems under Debian and a significant increase
+ * in the final file size: 144260 vs. 109536 Bytes.
+ */
+#if 0
+#define CONFIG_OF_LIBFDT		1
+#define CONFIG_FIT			1
+#define CONFIG_FIT_VERBOSE		1
+#endif
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)
+
+/*
+ * Hardware drivers
+ */
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	UART1_BASE
+
+#define CONFIG_HARD_SPI		1
+#define CONFIG_MXC_SPI		1
+#define CONFIG_DEFAULT_SPI_BUS	1
+#define CONFIG_DEFAULT_SPI_MODE	(SPI_MODE_0 | SPI_CS_HIGH)
+#define CONFIG_MXC_GPIO
+
+/* PMIC Controller */
+#define CONFIG_POWER
+#define CONFIG_POWER_SPI
+#define CONFIG_POWER_FSL
+#define CONFIG_FSL_PMIC_BUS	1
+#define CONFIG_FSL_PMIC_CS	0
+#define CONFIG_FSL_PMIC_CLK	1000000
+#define CONFIG_FSL_PMIC_MODE	(SPI_MODE_0 | SPI_CS_HIGH)
+#define CONFIG_FSL_PMIC_BITLEN	32
+#define CONFIG_RTC_MC13XXX
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		115200
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_DATE
+
+#define CONFIG_BOOTDELAY	3
+
+#define CONFIG_LOADADDR		0x80800000	/* loadaddr env var */
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"uboot_addr=0xa0000000\0"					\
+	"uboot=mx31ads/u-boot.bin\0"					\
+	"kernel=mx31ads/uImage\0"					\
+	"nfsroot=/opt/eldk/arm\0"					\
+	"bootargs_base=setenv bootargs console=ttymxc0,115200\0"	\
+	"bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "	\
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"	\
+	"bootcmd=run bootcmd_net\0"					\
+	"bootcmd_net=run bootargs_base bootargs_nfs; "			\
+		"tftpboot ${loadaddr} ${kernel}; bootm\0"		\
+	"prg_uboot=tftpboot ${loadaddr} ${uboot}; "			\
+		"protect off ${uboot_addr} 0xa003ffff; "		\
+		"erase ${uboot_addr} 0xa003ffff; "			\
+		"cp.b ${loadaddr} ${uboot_addr} ${filesize}; "		\
+		"setenv filesize; saveenv\0"
+
+#define CONFIG_CS8900
+#define CONFIG_CS8900_BASE	0xb4020300
+#define CONFIG_CS8900_BUS16		1	/* follow the Linux driver */
+
+/*
+ * The MX31ADS board seems to have a hardware "peculiarity" confirmed under
+ * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A
+ * controller inverted. The controller is capable of detecting and correcting
+ * this, but it needs 4 network packets for that. Which means, at startup, you
+ * will not receive answers to the first 4 packest, unless there have been some
+ * broadcasts on the network, or your board is on a hub. Reducing the ARP
+ * timeout from default 5 seconds to 200ms we speed up the initial TFTP
+ * transfer, should the user wish one, significantly.
+ */
+#define CONFIG_ARP_TIMEOUT	200UL
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START	0		/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x10000
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+#define CONFIG_CMDLINE_EDITING	1
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM_1		CSD0_BASE
+#define PHYS_SDRAM_1_SIZE	(128 * 1024 * 1024)
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+						GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_INIT_RAM_ADDR + \
+						CONFIG_SYS_GBL_DATA_OFFSET)
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_FLASH_BASE		CS0_BASE
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	262		/* max number of sectors on one chip */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE	/* Monitor at beginning of flash */
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256KiB */
+
+#define	CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_SECT_SIZE	(128 * 1024)
+#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+
+
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+#define CONFIG_SYS_FLASH_CFI			1 /* Flash memory is CFI compliant */
+#define CONFIG_FLASH_CFI_DRIVER		1 /* Use drivers/cfi_flash.c */
+#define CONFIG_FLASH_SPANSION_S29WS_N	1 /* A non-standard buffered write algorithm */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1 /* Use buffered writes (~10x faster) */
+#define CONFIG_SYS_FLASH_PROTECTION		1 /* Use hardware sector protection */
+
+/*
+ * JFFS2 partitions
+ */
+#undef CONFIG_CMD_MTDPARTS
+#define CONFIG_JFFS2_DEV	"nor0"
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/mx31pdk.h b/qemu/roms/u-boot/include/configs/mx31pdk.h
new file mode 100644
index 000000000..f223788e5
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/mx31pdk.h
@@ -0,0 +1,215 @@
+/*
+ * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
+ *
+ * (C) Copyright 2004
+ * Texas Instruments.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Kshitij Gupta <kshitij@ti.com>
+ *
+ * Configuration settings for the Freescale i.MX31 PDK board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+
+/* High Level Configuration Options */
+#define CONFIG_ARM1136			/* This is an arm1136 CPU core */
+#define CONFIG_MX31			/* in a mx31 */
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#define CONFIG_MACH_TYPE	MACH_TYPE_MX31_3DS
+
+#define CONFIG_SPL
+#define CONFIG_SPL_TARGET	"u-boot-with-spl.bin"
+#define CONFIG_SPL_LDSCRIPT	"arch/$(ARCH)/cpu/u-boot-spl.lds"
+#define CONFIG_SPL_MAX_SIZE	2048
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+
+#define CONFIG_SPL_TEXT_BASE	0x87dc0000
+#define CONFIG_SYS_TEXT_BASE	0x87e00000
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(2*CONFIG_ENV_SIZE + 2 * 128 * 1024)
+
+/*
+ * Hardware drivers
+ */
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	UART1_BASE
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_HARD_SPI
+#define CONFIG_MXC_SPI
+#define CONFIG_DEFAULT_SPI_BUS	1
+#define CONFIG_DEFAULT_SPI_MODE	(SPI_MODE_0 | SPI_CS_HIGH)
+
+/* PMIC Controller */
+#define CONFIG_POWER
+#define CONFIG_POWER_SPI
+#define CONFIG_POWER_FSL
+#define CONFIG_FSL_PMIC_BUS	1
+#define CONFIG_FSL_PMIC_CS	2
+#define CONFIG_FSL_PMIC_CLK	1000000
+#define CONFIG_FSL_PMIC_MODE	(SPI_MODE_0 | SPI_CS_HIGH)
+#define CONFIG_FSL_PMIC_BITLEN	32
+#define CONFIG_RTC_MC13XXX
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_BOOTZ
+
+/*
+ * Disabled due to compilation errors in cmd_bootm.c (IMLS seems to require
+ * that CFG_NO_FLASH is undefined).
+ */
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_BOOTDELAY	1
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"bootargs_base=setenv bootargs console=ttymxc0,115200\0"	\
+	"bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs "	\
+		"ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0"	\
+	"bootcmd=run bootcmd_net\0"					\
+	"bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; "	\
+		"tftpboot 0x81000000 uImage-mx31; bootm\0"		\
+	"prg_uboot=tftpboot 0x81000000 u-boot-with-spl.bin; "		\
+		"nand erase 0x0 0x40000; "				\
+		"nand write 0x81000000 0x0 0x40000\0"
+
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_BASE	0xB6000000
+#define CONFIG_SMC911X_32_BIT
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP	/* undef to save memory */
+#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
+				sizeof(CONFIG_SYS_PROMPT)+16)
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS	16
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		0x80010000
+
+/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x81000000
+
+#define CONFIG_CMDLINE_EDITING
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM_1		CSD0_BASE
+#define PHYS_SDRAM_1_SIZE	(128 * 1024 * 1024)
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+						GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_INIT_RAM_ADDR + \
+						CONFIG_SYS_INIT_RAM_SIZE)
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+/* No NOR flash present */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		0x40000
+#define CONFIG_ENV_OFFSET_REDUND	0x60000
+#define CONFIG_ENV_SIZE			(128 * 1024)
+
+/*
+ * NAND driver
+ */
+#define CONFIG_NAND_MXC
+#define CONFIG_MXC_NAND_REGS_BASE      NFC_BASE_ADDR
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#define CONFIG_SYS_NAND_BASE           NFC_BASE_ADDR
+#define CONFIG_MXC_NAND_HWECC
+#define CONFIG_SYS_NAND_LARGEPAGE
+
+/* NAND configuration for the NAND_SPL */
+
+/* Start copying real U-boot from the second page */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	CONFIG_SPL_PAD_TO
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x3f800
+/* Load U-Boot to this address */
+#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
+
+#define CONFIG_SYS_NAND_PAGE_SIZE	0x800
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_SIZE		(256 * 1024 * 1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
+
+
+/* Configuration of lowlevel_init.S (clocks and SDRAM) */
+#define CCM_CCMR_SETUP		0x074B0BF5
+#define CCM_PDR0_SETUP_532MHZ	(PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \
+				 PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) |    \
+				 PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) |    \
+				 PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0))
+#define CCM_MPCTL_SETUP_532MHZ	(PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) |  \
+				 PLL_MFN(12))
+
+#define ESDMISC_MDDR_SETUP	0x00000004
+#define ESDMISC_MDDR_RESET_DL	0x0000000c
+#define ESDCFG0_MDDR_SETUP	0x006ac73a
+
+#define ESDCTL_ROW_COL		(ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2))
+#define ESDCTL_SETTINGS		(ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \
+				 ESDCTL_DSIZ(2) | ESDCTL_BL(1))
+#define ESDCTL_PRECHARGE	(ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE)
+#define ESDCTL_AUTOREFRESH	(ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH)
+#define ESDCTL_LOADMODEREG	(ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG)
+#define ESDCTL_RW		ESDCTL_SETTINGS
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/mx35pdk.h b/qemu/roms/u-boot/include/configs/mx35pdk.h
new file mode 100644
index 000000000..0a46f4c30
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/mx35pdk.h
@@ -0,0 +1,300 @@
+/*
+ * (C) Copyright 2010, Stefano Babic <sbabic@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * Configuration for the MX35pdk Freescale board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+
+ /* High Level Configuration Options */
+#define CONFIG_ARM1136	/* This is an arm1136 CPU core */
+#define CONFIG_MX35
+
+#define CONFIG_DISPLAY_CPUINFO
+
+/* Set TEXT at the beginning of the NOR flash */
+#define CONFIG_SYS_TEXT_BASE	0xA0000000
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+#define CONFIG_REVISION_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 1024 * 1024)
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_MXC_SPI
+#define CONFIG_MXC_GPIO
+
+
+/*
+ * PMIC Configs
+ */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_FSL
+#define CONFIG_PMIC_FSL_MC13892
+#define CONFIG_SYS_FSL_PMIC_I2C_ADDR	0x08
+#define CONFIG_RTC_MC13XXX
+
+/*
+ * MFD MC9SDZ60
+ */
+#define CONFIG_FSL_MC9SDZ60
+#define CONFIG_SYS_FSL_MC9SDZ60_I2C_ADDR	0x69
+
+/*
+ * UART (console)
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	UART1_BASE
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		115200
+
+/*
+ * Command definition
+ */
+
+#include <config_cmd_default.h>
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_DNS
+
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_CACHE
+
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_NET_RETRY_COUNT	100
+#define CONFIG_CMD_DATE
+
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+
+#define CONFIG_BOOTDELAY	1
+
+#define CONFIG_LOADADDR		0x80800000	/* loadaddr env var */
+
+/*
+ * Ethernet on the debug board (SMC911)
+ */
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_16_BIT 1
+#define CONFIG_SMC911X_BASE CS5_BASE_ADDR
+
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETHPRIME
+
+/*
+ * Ethernet on SOC (FEC)
+ */
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE	FEC_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR	0x1F
+
+#define CONFIG_MII
+
+#define CONFIG_ARP_TIMEOUT	200UL
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP	/* undef to save memory */
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_HUSH_PARSER	/* Use the HUSH parser */
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START	0	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x10000
+
+#undef	CONFIG_SYS_CLKS_IN_HZ	/* everything, incl board info, in Hz */
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	2
+#define PHYS_SDRAM_1		CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE	(128 * 1024 * 1024)
+#define PHYS_SDRAM_2		CSD1_BASE_ADDR
+#define PHYS_SDRAM_2_SIZE	(128 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE		CSD0_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR + 0x10000)
+#define CONFIG_SYS_INIT_RAM_SIZE		(IRAM_SIZE / 2)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					CONFIG_SYS_GBL_DATA_OFFSET)
+
+/*
+ * MTD Command for mtdparts
+ */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_FLASH_CFI_MTD
+#define CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT		"nand0=mxc_nand,nor0=physmap-flash.0"
+#define MTDPARTS_DEFAULT	"mtdparts=mxc_nand:1m(boot),5m(linux),"	\
+				"96m(root),8m(cfg),1938m(user);"	\
+				"physmap-flash.0:512k(b),4m(k),30m(u),28m(r)"
+
+/*
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_FLASH_BASE		CS0_BASE_ADDR
+#define CONFIG_SYS_MAX_FLASH_BANKS 1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512	/* max number of sectors on one chip */
+/* Monitor at beginning of flash */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+
+#define CONFIG_ENV_SECT_SIZE	(128 * 1024)
+#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + \
+				CONFIG_SYS_MONITOR_LEN)
+
+#define CONFIG_ENV_IS_IN_FLASH
+
+#if defined(CONFIG_FSL_ENV_IN_NAND)
+	#define CONFIG_ENV_IS_IN_NAND
+	#define CONFIG_ENV_OFFSET       (1024 * 1024)
+#endif
+
+/*
+ * CFI FLASH driver setup
+ */
+#define CONFIG_SYS_FLASH_CFI		/* Flash memory is CFI compliant */
+#define CONFIG_FLASH_CFI_DRIVER
+
+/* A non-standard buffered write algorithm */
+#define CONFIG_FLASH_SPANSION_S29WS_N
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	/* faster */
+#define CONFIG_SYS_FLASH_PROTECTION	/* Use hardware sector protection */
+
+/*
+ * NAND FLASH driver setup
+ */
+#define CONFIG_NAND_MXC
+#define CONFIG_MXC_NAND_REGS_BASE	(NFC_BASE_ADDR)
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		(NFC_BASE_ADDR)
+#define CONFIG_MXC_NAND_HWECC
+#define CONFIG_SYS_NAND_LARGEPAGE
+
+/* EHCI driver */
+#define CONFIG_USB_EHCI
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	1
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_EHCI_MXC
+#define CONFIG_MXC_USB_PORT	0
+#define CONFIG_MXC_USB_FLAGS	(MXC_EHCI_INTERFACE_DIFF_UNI | \
+				 MXC_EHCI_POWER_PINS_ENABLED | \
+				 MXC_EHCI_OC_PIN_ACTIVE_LOW)
+#define CONFIG_MXC_USB_PORTSC	(MXC_EHCI_UTMI_16BIT | MXC_EHCI_MODE_UTMI)
+
+/* mmc driver */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_ESDHC_NUM	1
+
+/*
+ * Default environment and default scripts
+ * to update uboot and load kernel
+ */
+
+#define CONFIG_HOSTNAME "mx35pdk"
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth1\0"							\
+	"ethprime=smc911x\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip_sta=setenv bootargs ${bootargs} "			\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0"		\
+	"addip=if test -n ${ipdyn};then run addip_dyn;"			\
+		"else run addip_sta;fi\0"				\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
+	"addtty=setenv bootargs ${bootargs}"				\
+		" console=ttymxc0,${baudrate}\0"			\
+	"addmisc=setenv bootargs ${bootargs} ${misc}\0"			\
+	"loadaddr=80800000\0"						\
+	"kernel_addr_r=80800000\0"					\
+	"hostname=" __stringify(CONFIG_HOSTNAME) "\0"			\
+	"bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0"		\
+	"ramdisk_file=" __stringify(CONFIG_HOSTNAME) "/uRamdisk\0"	\
+	"flash_self=run ramargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"flash_nfs=run nfsargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr}\0"				\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
+		"run nfsargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr_r}\0"				\
+	"net_self_load=tftp ${kernel_addr_r} ${bootfile};"		\
+		"tftp ${ramdisk_addr_r} ${ramdisk_file};\0"		\
+	"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0"		\
+	"load=tftp ${loadaddr} ${u-boot}\0"				\
+	"uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0"		\
+	"update=protect off ${uboot_addr} +80000;"			\
+		"erase ${uboot_addr} +80000;"				\
+		"cp.b ${loadaddr} ${uboot_addr} ${filesize}\0"		\
+	"upd=if run load;then echo Updating u-boot;if run update;"	\
+		"then echo U-Boot updated;"				\
+			"else echo Error updating u-boot !;"		\
+			"echo Board without bootloader !!;"		\
+		"fi;"							\
+		"else echo U-Boot not downloaded..exiting;fi\0"		\
+	"bootcmd=run net_nfs\0"
+
+#endif				/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/mx51_efikamx.h b/qemu/roms/u-boot/include/configs/mx51_efikamx.h
new file mode 100644
index 000000000..0f2a4ef97
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/mx51_efikamx.h
@@ -0,0 +1,251 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the MX51EVK Board
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <config_cmd_default.h>
+
+/*
+ * High Level Board Configuration Options
+ */
+/* An i.MX51 CPU */
+#define CONFIG_MX51
+
+#define	machine_is_efikamx()	(CONFIG_MACH_TYPE == MACH_TYPE_MX51_EFIKAMX)
+#define	machine_is_efikasb()	(CONFIG_MACH_TYPE == MACH_TYPE_MX51_EFIKASB)
+
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_SYS_TEXT_BASE		0x97800000
+
+#define	CONFIG_SYS_ICACHE_OFF
+#define	CONFIG_SYS_DCACHE_OFF
+
+/*
+ * Bootloader Components Configuration
+ */
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DATE
+#undef CONFIG_CMD_IMLS
+
+/*
+ * Environmental settings
+ */
+
+#define CONFIG_ENV_OFFSET		(6 * 64 * 1024)
+#define CONFIG_ENV_SECT_SIZE		(1 * 64 * 1024)
+#define CONFIG_ENV_SIZE			(4 * 1024)
+
+/*
+ * ATAG setup
+ */
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+#define CONFIG_REVISION_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#define CONFIG_OF_LIBFDT		1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART1_BASE
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_MXC_GPIO
+
+/*
+ * SPI Interface
+ */
+#ifdef CONFIG_CMD_SPI
+
+#define CONFIG_HARD_SPI
+#define CONFIG_MXC_SPI
+#define CONFIG_DEFAULT_SPI_BUS		1
+#define CONFIG_DEFAULT_SPI_MODE		(SPI_MODE_0 | SPI_CS_HIGH)
+
+/* SPI FLASH */
+#ifdef CONFIG_CMD_SF
+
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_SF_DEFAULT_CS		(1 | 121 << 8)
+#define CONFIG_SF_DEFAULT_MODE		(SPI_MODE_0)
+#define CONFIG_SF_DEFAULT_SPEED		25000000
+
+#define CONFIG_ENV_SPI_CS		(1 | 121 << 8)
+#define CONFIG_ENV_SPI_BUS		0
+#define CONFIG_ENV_SPI_MAX_HZ		25000000
+#define CONFIG_ENV_SPI_MODE		(SPI_MODE_0)
+#define CONFIG_FSL_ENV_IN_SF
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_SYS_NO_FLASH
+
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+/* SPI PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_SPI
+#define CONFIG_POWER_FSL
+#define CONFIG_FSL_PMIC_BUS		0
+#define CONFIG_FSL_PMIC_CS		(0 | 120 << 8)
+#define CONFIG_FSL_PMIC_CLK		25000000
+#define CONFIG_FSL_PMIC_MODE		(SPI_MODE_0 | SPI_CS_HIGH)
+#define CONFIG_FSL_PMIC_BITLEN	32
+#define CONFIG_RTC_MC13XXX
+#endif
+
+/*
+ * MMC Configs
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_ESDHC_NUM	2
+#endif
+
+/*
+ * ATA/IDE
+ */
+#ifdef CONFIG_CMD_IDE
+#define CONFIG_LBA48
+#undef CONFIG_IDE_LED
+#undef CONFIG_IDE_RESET
+
+#define CONFIG_MX51_PATA
+
+#define __io
+
+#define CONFIG_SYS_IDE_MAXBUS		1
+#define CONFIG_SYS_IDE_MAXDEVICE	1
+
+#define CONFIG_SYS_ATA_BASE_ADDR	0x83fe0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0
+
+#define CONFIG_SYS_ATA_DATA_OFFSET	0xa0
+#define CONFIG_SYS_ATA_REG_OFFSET	0xa0
+#define CONFIG_SYS_ATA_ALT_OFFSET	0xd8
+
+#define CONFIG_SYS_ATA_STRIDE		4
+
+#define CONFIG_IDE_PREINIT
+#define CONFIG_MXC_ATA_PIO_MODE		4
+#endif
+
+/*
+ * USB
+ */
+#define	CONFIG_CMD_USB
+#ifdef	CONFIG_CMD_USB
+#define	CONFIG_USB_EHCI			/* Enable EHCI USB support */
+#define	CONFIG_USB_EHCI_MX5
+#define	CONFIG_USB_ULPI
+#define	CONFIG_USB_ULPI_VIEWPORT
+#define	CONFIG_MXC_USB_PORT	1
+#if	(CONFIG_MXC_USB_PORT == 0)
+#define	CONFIG_MXC_USB_PORTSC	(1 << 28)
+#define	CONFIG_MXC_USB_FLAGS	MXC_EHCI_INTERNAL_PHY
+#else
+#define	CONFIG_MXC_USB_PORTSC	(2 << 30)
+#define	CONFIG_MXC_USB_FLAGS	0
+#endif
+#define	CONFIG_EHCI_IS_TDI
+#define	CONFIG_USB_STORAGE
+#define	CONFIG_USB_HOST_ETHER
+#define	CONFIG_USB_KEYBOARD
+#define	CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
+#define CONFIG_PREBOOT
+/* USB NET */
+#ifdef	CONFIG_CMD_NET
+#define	CONFIG_USB_ETHER_ASIX
+#define	CONFIG_CMD_PING
+#define	CONFIG_CMD_DHCP
+#endif
+#endif /* CONFIG_CMD_USB */
+
+/*
+ * Filesystems
+ */
+#ifdef CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#ifdef	CONFIG_CMD_NET
+#define	CONFIG_CMD_NFS
+#endif
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_LOADADDR			0x90800000
+
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT		"Efika> "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START	0x90000000
+#define CONFIG_SYS_MEMTEST_END		0x90010000
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+#define CONFIG_CMDLINE_EDITING
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM_1			CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE		(512 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR)
+#define CONFIG_SYS_INIT_RAM_SIZE	(IRAM_SIZE)
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_SYS_DDR_CLKSEL		0
+#define CONFIG_SYS_CLKTL_CBCDR		0x59E35145
+#define CONFIG_SYS_MAIN_PWR_ON
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/mx51evk.h b/qemu/roms/u-boot/include/configs/mx51evk.h
new file mode 100644
index 000000000..b389475eb
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/mx51evk.h
@@ -0,0 +1,268 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the MX51EVK Board
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+ /* High Level Configuration Options */
+
+#define CONFIG_MX51	/* in a mx51 */
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_SYS_TEXT_BASE	0x97800000
+
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_MACH_TYPE	MACH_TYPE_MX51_BABBAGE
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
+
+#define CONFIG_BOARD_LATE_INIT
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_FSL_IIM
+#define CONFIG_CMD_FUSE
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	UART1_BASE
+#define CONFIG_MXC_GPIO
+
+/*
+ * SPI Configs
+ * */
+#define CONFIG_CMD_SPI
+
+#define CONFIG_MXC_SPI
+
+/* PMIC Controller */
+#define CONFIG_POWER
+#define CONFIG_POWER_SPI
+#define CONFIG_POWER_FSL
+#define CONFIG_FSL_PMIC_BUS	0
+#define CONFIG_FSL_PMIC_CS	0
+#define CONFIG_FSL_PMIC_CLK	2500000
+#define CONFIG_FSL_PMIC_MODE	(SPI_MODE_0 | SPI_CS_HIGH)
+#define CONFIG_FSL_PMIC_BITLEN	32
+#define CONFIG_RTC_MC13XXX
+
+/*
+ * MMC Configs
+ * */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_ESDHC_NUM	2
+
+#define CONFIG_MMC
+
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+/*
+ * Eth Configs
+ */
+#define CONFIG_MII
+
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE	FEC_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR	0x1F
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+
+/* USB Configs */
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_FAT
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX5
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_MXC_USB_PORT	1
+#define CONFIG_MXC_USB_PORTSC	PORT_PTS_ULPI
+#define CONFIG_MXC_USB_FLAGS	MXC_EHCI_POWER_PINS_ENABLED
+
+/* Framebuffer and LCD */
+#define CONFIG_PREBOOT
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_IPUV3
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_IPUV3_CLK	133000000
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+#define CONFIG_CMD_BOOTZ
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_CMD_DATE
+
+#define CONFIG_BOOTDELAY	1
+
+#define CONFIG_ETHPRIME		"FEC0"
+
+#define CONFIG_LOADADDR		0x92000000	/* loadaddr env var */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"image=zImage\0" \
+	"fdt_file=imx51-babbage.dtb\0" \
+	"fdt_addr=0x91000000\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"mmcdev=0\0" \
+	"mmcpart=1\0" \
+	"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
+	"mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=ttymxc0,${baudrate} " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${image}; " \
+		"if test ${boot_fdt} = yes ||  test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo ERROR: Cannot load the DT; " \
+					"exit; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loadimage; then " \
+				"run mmcboot; " \
+			"else run netboot; " \
+			"fi; " \
+		"fi; " \
+	"else run netboot; fi"
+
+#define CONFIG_ARP_TIMEOUT	200UL
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START       0x90000000
+#define CONFIG_SYS_MEMTEST_END         0x90010000
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+#define CONFIG_CMDLINE_EDITING
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM_1		CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE	(512 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR)
+#define CONFIG_SYS_INIT_RAM_SIZE	(IRAM_SIZE)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_SYS_DDR_CLKSEL	0
+#define CONFIG_SYS_CLKTL_CBCDR	0x59E35100
+#define CONFIG_SYS_MAIN_PWR_ON
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_OFFSET      (6 * 64 * 1024)
+#define CONFIG_ENV_SIZE        (8 * 1024)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/mx53ard.h b/qemu/roms/u-boot/include/configs/mx53ard.h
new file mode 100644
index 000000000..797a637bf
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/mx53ard.h
@@ -0,0 +1,235 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the MX53ARD Freescale board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MX53
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_MACH_TYPE	MACH_TYPE_MX53_ARD
+
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		NFC_BASE_ADDR_AXI
+#define CONFIG_NAND_MXC
+#define CONFIG_MXC_NAND_REGS_BASE	NFC_BASE_ADDR_AXI
+#define CONFIG_MXC_NAND_IP_REGS_BASE	NFC_BASE_ADDR
+#define CONFIG_SYS_NAND_LARGEPAGE
+#define CONFIG_MXC_NAND_HWECC
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_CMD_NAND
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	UART1_BASE
+
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_ESDHC_NUM	2
+
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+/* Eth Configs */
+#define CONFIG_HAS_ETH1
+#define CONFIG_MII
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+
+/* Command definition */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_SETEXPR
+
+#define CONFIG_BOOTDELAY	3
+
+#define CONFIG_ETHPRIME		"smc911x"
+
+/*Support LAN9217*/
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_16_BIT
+#define CONFIG_SMC911X_BASE CS1_BASE_ADDR
+
+#define CONFIG_LOADADDR		0x72000000	/* loadaddr env var */
+#define CONFIG_SYS_TEXT_BASE    0x77800000
+
+#define CONFIG_DEFAULT_FDT_FILE		"imx53-ard.dtb"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"uimage=uImage\0" \
+	"console=ttymxc0\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"fdt_addr=0x71000000\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
+	"mmcpart=1\0" \
+	"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
+	"update_sd_firmware_filename=u-boot.imx\0" \
+	"update_sd_firmware=" \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"if mmc dev ${mmcdev}; then "	\
+			"if ${get_cmd} ${update_sd_firmware_filename}; then " \
+				"setexpr fw_sz ${filesize} / 0x200; " \
+				"setexpr fw_sz ${fw_sz} + 1; "	\
+				"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
+			"fi; "	\
+		"fi\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootm ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootm; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootm; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs " \
+	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+		"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${uimage}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootm ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootm; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootm; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	   "mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loaduimage; then " \
+				   "run mmcboot; " \
+			   "else run netboot; " \
+			   "fi; " \
+		   "fi; " \
+	   "else run netboot; fi"
+
+#define CONFIG_ARP_TIMEOUT	200UL
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT		"MX53ARD U-Boot > "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START       0x70000000
+#define CONFIG_SYS_MEMTEST_END         0x70010000
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+#define CONFIG_CMDLINE_EDITING
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS	2
+#define PHYS_SDRAM_1		CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE	(512 * 1024 * 1024)
+#define PHYS_SDRAM_2		CSD1_BASE_ADDR
+#define PHYS_SDRAM_2_SIZE	(512 * 1024 * 1024)
+#define PHYS_SDRAM_SIZE         (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
+
+#define CONFIG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR)
+#define CONFIG_SYS_INIT_RAM_SIZE	(IRAM_SIZE)
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_OFFSET      (6 * 64 * 1024)
+#define CONFIG_ENV_SIZE        (8 * 1024)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV	0
+
+#define CONFIG_OF_LIBFDT
+
+#define MX53ARD_CS1GCR1		(CSEN | DSZ(2))
+#define MX53ARD_CS1RCR1		(RCSN(2) | OEN (1) | RWSC(22))
+#define MX53ARD_CS1RCR2		RBEN(2)
+#define MX53ARD_CS1WCR1		(WCSN(2) | WEN(2) | WBEN(2) | WWSC(22))
+
+#endif				/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/mx53evk.h b/qemu/roms/u-boot/include/configs/mx53evk.h
new file mode 100644
index 000000000..3f0d80ac6
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/mx53evk.h
@@ -0,0 +1,174 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the MX53-EVK Freescale board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MX53
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_MACH_TYPE	MACH_TYPE_MX53_EVK
+
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+#define CONFIG_OF_LIBFDT
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	UART1_BASE
+
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+
+/* PMIC Configs */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_FSL
+#define CONFIG_SYS_FSL_PMIC_I2C_ADDR    8
+#define CONFIG_PMIC_FSL_MC13892
+#define CONFIG_RTC_MC13XXX
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_ESDHC_NUM	2
+
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+/* Eth Configs */
+#define CONFIG_MII
+
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE	FEC_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR	0x1F
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DATE
+
+/* Miscellaneous commands */
+#define CONFIG_CMD_BMODE
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+
+/* Command definition */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY	3
+
+#define CONFIG_ETHPRIME		"FEC0"
+
+#define CONFIG_LOADADDR		0x70800000	/* loadaddr env var */
+#define CONFIG_SYS_TEXT_BASE    0x77800000
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"uimage=uImage\0" \
+	"mmcdev=0\0" \
+	"mmcpart=2\0" \
+	"mmcroot=/dev/mmcblk0p3 rw\0" \
+	"mmcrootfstype=ext3 rootwait\0" \
+	"mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm\0" \
+	"netargs=setenv bootargs console=ttymxc0,${baudrate} " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"dhcp ${uimage}; bootm\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loaduimage; then " \
+				"run mmcboot; " \
+			"else run netboot; " \
+			"fi; " \
+		"fi; " \
+	"else run netboot; fi"
+
+#define CONFIG_ARP_TIMEOUT	200UL
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START       0x70000000
+#define CONFIG_SYS_MEMTEST_END         0x70010000
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+#define CONFIG_CMDLINE_EDITING
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM_1		CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE	(512 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR)
+#define CONFIG_SYS_INIT_RAM_SIZE	(IRAM_SIZE)
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_OFFSET      (6 * 64 * 1024)
+#define CONFIG_ENV_SIZE        (8 * 1024)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#endif				/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/mx53loco.h b/qemu/roms/u-boot/include/configs/mx53loco.h
new file mode 100644
index 000000000..5859f360e
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/mx53loco.h
@@ -0,0 +1,246 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * Jason Liu <r64343@freescale.com>
+ *
+ * Configuration settings for Freescale MX53 low cost board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MX53
+
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_MACH_TYPE	MACH_TYPE_MX53_LOCO
+
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_MXC_GPIO
+#define CONFIG_REVISION_TAG
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	UART1_BASE
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_ESDHC_NUM	2
+
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_DOS_PARTITION
+
+/* Eth Configs */
+#define CONFIG_MII
+
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE	FEC_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR	0x1F
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+
+/* USB Configs */
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_FAT
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX5
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_MCS7830
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_MXC_USB_PORT	1
+#define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS	0
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+
+/* PMIC Controller */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_DIALOG_POWER
+#define CONFIG_POWER_FSL
+#define CONFIG_PMIC_FSL_MC13892
+#define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR	0x48
+#define CONFIG_SYS_FSL_PMIC_I2C_ADDR	0x8
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+
+/* Command definition */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_BOOTZ
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY	1
+
+#define CONFIG_ETHPRIME		"FEC0"
+
+#define CONFIG_LOADADDR		0x72000000	/* loadaddr env var */
+#define CONFIG_SYS_TEXT_BASE    0x77800000
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"image=zImage\0" \
+	"fdt_file=imx53-qsb.dtb\0" \
+	"fdt_addr=0x71000000\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"mmcdev=0\0" \
+	"mmcpart=1\0" \
+	"mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
+	"mmcargs=setenv bootargs console=ttymxc0,${baudrate} root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=ttymxc0,${baudrate} " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${image}; " \
+		"if test ${boot_fdt} = yes ||  test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo ERROR: Cannot load the DT; " \
+					"exit; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loadimage; then " \
+				"run mmcboot; " \
+			"else run netboot; " \
+			"fi; " \
+		"fi; " \
+	"else run netboot; fi"
+
+#define CONFIG_ARP_TIMEOUT	200UL
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START       0x70000000
+#define CONFIG_SYS_MEMTEST_END         0x70010000
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+#define CONFIG_CMDLINE_EDITING
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS	2
+#define PHYS_SDRAM_1			CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE		(gd->bd->bi_dram[0].size)
+#define PHYS_SDRAM_2			CSD1_BASE_ADDR
+#define PHYS_SDRAM_2_SIZE		(gd->bd->bi_dram[1].size)
+#define PHYS_SDRAM_SIZE			(gd->ram_size)
+
+#define CONFIG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR)
+#define CONFIG_SYS_INIT_RAM_SIZE	(IRAM_SIZE)
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_OFFSET      (6 * 64 * 1024)
+#define CONFIG_ENV_SIZE        (8 * 1024)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_CMD_SATA
+#ifdef CONFIG_CMD_SATA
+	#define CONFIG_DWC_AHSATA
+	#define CONFIG_SYS_SATA_MAX_DEVICE      1
+	#define CONFIG_DWC_AHSATA_PORT_ID       0
+	#define CONFIG_DWC_AHSATA_BASE_ADDR     SATA_BASE_ADDR
+	#define CONFIG_LBA48
+	#define CONFIG_LIBATA
+#endif
+
+/* Framebuffer and LCD */
+#define CONFIG_PREBOOT
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_IPUV3
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_IPUV3_CLK	200000000
+
+#endif				/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/mx53smd.h b/qemu/roms/u-boot/include/configs/mx53smd.h
new file mode 100644
index 000000000..a04e7c7a3
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/mx53smd.h
@@ -0,0 +1,164 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the MX53SMD Freescale board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MX53
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_MACH_TYPE	MACH_TYPE_MX53_SMD
+
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	UART1_BASE
+
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_ESDHC_NUM	1
+
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+/* Eth Configs */
+#define CONFIG_HAS_ETH1
+#define CONFIG_MII
+
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE	FEC_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR	0x1F
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+
+/* Command definition */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY	3
+
+#define CONFIG_ETHPRIME		"FEC0"
+
+#define CONFIG_LOADADDR		0x70800000	/* loadaddr env var */
+#define CONFIG_SYS_TEXT_BASE    0x77800000
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"uimage=uImage\0" \
+	"mmcdev=0\0" \
+	"mmcpart=2\0" \
+	"mmcroot=/dev/mmcblk0p3 rw\0" \
+	"mmcrootfstype=ext3 rootwait\0" \
+	"mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm\0" \
+	"netargs=setenv bootargs console=ttymxc0,${baudrate} " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"dhcp ${uimage}; bootm\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loaduimage; then " \
+				"run mmcboot; " \
+			"else run netboot; " \
+			"fi; " \
+		"fi; " \
+	"else run netboot; fi"
+#define CONFIG_ARP_TIMEOUT	200UL
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START       0x70000000
+#define CONFIG_SYS_MEMTEST_END         0x70010000
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+#define CONFIG_CMDLINE_EDITING
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS	2
+#define PHYS_SDRAM_1		CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE	(512 * 1024 * 1024)
+#define PHYS_SDRAM_2		CSD1_BASE_ADDR
+#define PHYS_SDRAM_2_SIZE	(512 * 1024 * 1024)
+#define PHYS_SDRAM_SIZE         (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
+
+#define CONFIG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR)
+#define CONFIG_SYS_INIT_RAM_SIZE	(IRAM_SIZE)
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_OFFSET      (6 * 64 * 1024)
+#define CONFIG_ENV_SIZE        (8 * 1024)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#define CONFIG_OF_LIBFDT
+
+#endif				/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/mx6_common.h b/qemu/roms/u-boot/include/configs/mx6_common.h
new file mode 100644
index 000000000..8a8920f6c
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/mx6_common.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __MX6_COMMON_H
+#define __MX6_COMMON_H
+
+#define CONFIG_ARM_ERRATA_742230
+#define CONFIG_ARM_ERRATA_743622
+#define CONFIG_ARM_ERRATA_751472
+#define CONFIG_ARM_ERRATA_794072
+#define CONFIG_ARM_ERRATA_761320
+#define CONFIG_BOARD_POSTCLK_INIT
+
+#ifndef CONFIG_SYS_L2CACHE_OFF
+#define CONFIG_SYS_L2_PL310
+#define CONFIG_SYS_PL310_BASE	L2_PL310_BASE
+#endif
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/mx6qarm2.h b/qemu/roms/u-boot/include/configs/mx6qarm2.h
new file mode 100644
index 000000000..fd651cfa5
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/mx6qarm2.h
@@ -0,0 +1,157 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6Q Armadillo2 board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MX6
+#define CONFIG_MX6Q
+
+#include "mx6_common.h"
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART4_BASE
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define	CONFIG_FEC_MXC
+#define	CONFIG_MII
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define	CONFIG_FEC_XCV_TYPE		RGMII
+#define CONFIG_FEC_MXC_PHYADDR		0
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+
+/* Command definition */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY		3
+
+#define CONFIG_LOADADDR			0x10800000
+#define CONFIG_SYS_TEXT_BASE		0x17800000
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"image=zImage\0" \
+	"console=ttymxc3\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"mmcdev=1\0" \
+	"mmcpart=2\0" \
+	"mmcroot=/dev/mmcblk0p3 rootwait rw\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootz\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"dhcp ${image}; bootz\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev};" \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loadimage; then " \
+				"run mmcboot; " \
+			"else run netboot; " \
+			"fi; " \
+		"fi; " \
+	"else run netboot; fi"
+
+#define CONFIG_ARP_TIMEOUT	200UL
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE		256
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START	0x10000000
+#define CONFIG_SYS_MEMTEST_END		0x10010000
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+#define CONFIG_CMDLINE_EDITING
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+#define PHYS_SDRAM_SIZE			(2u * 1024 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_OFFSET		(6 * 64 * 1024)
+#define CONFIG_ENV_SIZE			(8 * 1024)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV		1
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
+
+#endif				/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/mx6qsabreauto.h b/qemu/roms/u-boot/include/configs/mx6qsabreauto.h
new file mode 100644
index 000000000..bd0144f5c
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/mx6qsabreauto.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6Q SabreAuto board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MX6QSABREAUTO_CONFIG_H
+#define __MX6QSABREAUTO_CONFIG_H
+
+#define CONFIG_MACH_TYPE	3529
+#define CONFIG_MXC_UART_BASE	UART4_BASE
+#define CONFIG_CONSOLE_DEV		"ttymxc3"
+#define CONFIG_DEFAULT_FDT_FILE	"imx6q-sabreauto.dtb"
+#define CONFIG_MMCROOT			"/dev/mmcblk0p2"
+#define PHYS_SDRAM_SIZE		(2u * 1024 * 1024 * 1024)
+
+/* USB Configs */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET	/* For OTG port */
+#define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS	0
+
+#include "mx6sabre_common.h"
+
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#endif
+
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_SPEED		100000
+
+#define CONFIG_OF_SEPARATE
+#define CONFIG_DEFAULT_DEVICE_TREE   imx6q-sabreauto
+
+#endif                         /* __MX6QSABREAUTO_CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/mx6sabre_common.h b/qemu/roms/u-boot/include/configs/mx6sabre_common.h
new file mode 100644
index 000000000..7a2c172d4
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/mx6sabre_common.h
@@ -0,0 +1,261 @@
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6Q SabreSD board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MX6QSABRE_COMMON_CONFIG_H
+#define __MX6QSABRE_COMMON_CONFIG_H
+
+#define CONFIG_MX6
+
+#include "mx6_common.h"
+#include <linux/sizes.h>
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/gpio.h>
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(10 * SZ_1M)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_MXC_UART
+
+#define CONFIG_CMD_FUSE
+#ifdef CONFIG_CMD_FUSE
+#define CONFIG_MXC_OCOTP
+#endif
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR      0
+
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE		RGMII
+#define CONFIG_ETHPRIME			"FEC"
+#define CONFIG_FEC_MXC_PHYADDR		1
+
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ATHEROS
+
+#define CONFIG_CMD_SF
+#ifdef CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_MXC_SPI
+#define CONFIG_SF_DEFAULT_BUS		0
+#define CONFIG_SF_DEFAULT_CS		(0 | (IMX_GPIO_NR(4, 9) << 8))
+#define CONFIG_SF_DEFAULT_SPEED		20000000
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
+#endif
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX              1
+#define CONFIG_BAUDRATE                        115200
+
+/* Command definition */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BMODE
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_SETEXPR
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY               1
+
+#define CONFIG_LOADADDR                        0x12000000
+#define CONFIG_SYS_TEXT_BASE           0x17800000
+
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
+#define EMMC_ENV \
+	"emmcdev=2\0" \
+	"update_emmc_firmware=" \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"if ${get_cmd} ${update_sd_firmware_filename}; then " \
+			"if mmc dev ${emmcdev} && " \
+				"mmc open ${emmcdev} 1; then "	\
+				"setexpr fw_sz ${filesize} / 0x200; " \
+				"setexpr fw_sz ${fw_sz} + 1; "	\
+				"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
+				"mmc close ${emmcdev} 1; " \
+			"fi; "	\
+		"fi\0"
+#else
+#define EMMC_ENV ""
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"image=zImage\0" \
+	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"fdt_addr=0x18000000\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"console=" CONFIG_CONSOLE_DEV "\0" \
+	"fdt_high=0xffffffff\0"	  \
+	"initrd_high=0xffffffff\0" \
+	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
+	"mmcpart=1\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"update_sd_firmware=" \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"if mmc dev ${mmcdev}; then "	\
+			"if ${get_cmd} ${update_sd_firmware_filename}; then " \
+				"setexpr fw_sz ${filesize} / 0x200; " \
+				"setexpr fw_sz ${fw_sz} + 1; "	\
+				"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
+			"fi; "	\
+		"fi\0" \
+	EMMC_ENV	  \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev};" \
+	"if mmc rescan; then " \
+		"if run loadbootscript; then " \
+		"run bootscript; " \
+		"else " \
+			"if run loadimage; then " \
+				"run mmcboot; " \
+			"else run netboot; " \
+			"fi; " \
+		"fi; " \
+	"else run netboot; fi"
+
+#define CONFIG_ARP_TIMEOUT     200UL
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE              256
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS             16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START       0x10000000
+#define CONFIG_SYS_MEMTEST_END         0x10010000
+#define CONFIG_SYS_MEMTEST_SCRATCH     0x10800000
+
+#define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
+
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_STACKSIZE               (128 * 1024)
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS           1
+#define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_SIZE			(8 * 1024)
+
+#define CONFIG_ENV_IS_IN_MMC
+
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_ENV_OFFSET		(6 * 64 * 1024)
+#endif
+
+#define CONFIG_OF_LIBFDT
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+#endif
+
+#endif                         /* __MX6QSABRE_COMMON_CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/mx6sabresd.h b/qemu/roms/u-boot/include/configs/mx6sabresd.h
new file mode 100644
index 000000000..5d02d23ec
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/mx6sabresd.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6Q SabreSD board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MX6QSABRESD_CONFIG_H
+#define __MX6QSABRESD_CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/gpio.h>
+
+#define CONFIG_MACH_TYPE	3980
+#define CONFIG_MXC_UART_BASE	UART1_BASE
+#define CONFIG_CONSOLE_DEV		"ttymxc0"
+#define CONFIG_MMCROOT			"/dev/mmcblk1p2"
+#if defined(CONFIG_MX6Q)
+#define CONFIG_DEFAULT_FDT_FILE	"imx6q-sabresd.dtb"
+#elif defined(CONFIG_MX6DL)
+#define CONFIG_DEFAULT_FDT_FILE	"imx6dl-sabresd.dtb"
+#endif
+#define PHYS_SDRAM_SIZE		(1u * 1024 * 1024 * 1024)
+
+#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
+
+#include "mx6sabre_common.h"
+
+#define CONFIG_SYS_FSL_USDHC_NUM	3
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_SYS_MMC_ENV_DEV		1	/* SDHC3 */
+#endif
+
+/* Framebuffer */
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_IPUV3
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_IPUV3_CLK 260000000
+#define CONFIG_IMX_HDMI
+
+#define CONFIG_CMD_PCI
+#ifdef CONFIG_CMD_PCI
+#define CONFIG_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_PCIE_IMX
+#define CONFIG_PCIE_IMX_PERST_GPIO	IMX_GPIO_NR(7, 12)
+#define CONFIG_PCIE_IMX_POWER_GPIO	IMX_GPIO_NR(3, 19)
+#endif
+
+#endif                         /* __MX6QSABRESD_CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/mx6slevk.h b/qemu/roms/u-boot/include/configs/mx6slevk.h
new file mode 100644
index 000000000..1876dbf35
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/mx6slevk.h
@@ -0,0 +1,199 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6SL EVK board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+#include <linux/sizes.h>
+#include "mx6_common.h"
+
+#define CONFIG_MX6
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define MACH_TYPE_MX6SLEVK		4307
+#define CONFIG_MACH_TYPE		MACH_TYPE_MX6SLEVK
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(3 * SZ_1M)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART1_IPS_BASE_ADDR
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE		RMII
+#define CONFIG_ETHPRIME			"FEC"
+#define CONFIG_FEC_MXC_PHYADDR		0
+
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_SMSC
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+
+/* Command definition */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY		3
+
+#define CONFIG_LOADADDR			0x82000000
+#define CONFIG_SYS_TEXT_BASE		0x87800000
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"image=zImage\0" \
+	"console=ttymxc0\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_file=imx6sl-evk.dtb\0" \
+	"fdt_addr=0x88000000\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"mmcdev=0\0" \
+	"mmcpart=1\0" \
+	"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs " \
+	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+		"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	   "mmc dev ${mmcdev};" \
+	   "mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "else run netboot; " \
+			   "fi; " \
+		   "fi; " \
+	   "else run netboot; fi"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE		256
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + SZ_512M)
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_STACKSIZE		SZ_128K
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+#define PHYS_SDRAM_SIZE			SZ_1G
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_OFFSET		(6 * SZ_64K)
+#define CONFIG_ENV_SIZE			SZ_8K
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV		0
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+#endif
+
+#endif				/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/mxs.h b/qemu/roms/u-boot/include/configs/mxs.h
new file mode 100644
index 000000000..ba55177e7
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/mxs.h
@@ -0,0 +1,204 @@
+/*
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __CONFIGS_MXS_H__
+#define __CONFIGS_MXS_H__
+
+/*
+ * Includes
+ */
+
+#if defined(CONFIG_MX23) && defined(CONFIG_MX28)
+#error Select either CONFIG_MX23 or CONFIG_MX28 , never both!
+#elif !defined(CONFIG_MX23) && !defined(CONFIG_MX28)
+#error Select one of CONFIG_MX23 or CONFIG_MX28 !
+#endif
+
+#include <asm/arch/regs-base.h>
+
+#if defined(CONFIG_MX23)
+#include <asm/arch/iomux-mx23.h>
+#elif defined(CONFIG_MX28)
+#include <asm/arch/iomux-mx28.h>
+#endif
+
+/*
+ * CPU specifics
+ */
+
+/* MXS uses FDT */
+#define CONFIG_OF_LIBFDT
+
+/* Startup hooks */
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_ARCH_MISC_INIT
+
+/* SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_NO_CPU_SUPPORT_CODE
+#define CONFIG_SPL_START_S_PATH	"arch/arm/cpu/arm926ejs/mxs"
+#define CONFIG_SPL_LDSCRIPT	"arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds"
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+
+/* Memory sizes */
+#define CONFIG_SYS_MALLOC_LEN		0x00400000	/* 4 MB for malloc */
+#define CONFIG_SYS_MEMTEST_START	0x40000000	/* Memtest start adr */
+#define CONFIG_SYS_MEMTEST_END		0x40400000	/* 4 MB RAM test */
+
+/* OCRAM at 0x0 ; 32kB on MX23 ; 128kB on MX28 */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x00000000
+#if defined(CONFIG_MX23)
+#define CONFIG_SYS_INIT_RAM_SIZE	(32 * 1024)
+#elif defined(CONFIG_MX28)
+#define CONFIG_SYS_INIT_RAM_SIZE	(128 * 1024)
+#endif
+
+/* Point initial SP in SRAM so SPL can use it too. */
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/*
+ * We need to sacrifice first 4 bytes of RAM here to avoid triggering some
+ * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot
+ * binary. In case there was more of this mess, 0x100 bytes are skipped.
+ *
+ * In case of a HAB boot, we cannot for some weird reason use the first 4KiB
+ * of DRAM when loading. Moreover, we use the first 4 KiB for IVT and CST
+ * blocks, thus U-Boot starts at offset +8 KiB of DRAM start.
+ *
+ * As for the SPL, we must avoid the first 4 KiB as well, but we load the
+ * IVT and CST to 0x8000, so we don't need to waste the subsequent 4 KiB.
+ */
+#define CONFIG_SYS_TEXT_BASE		0x40002000
+#define CONFIG_SPL_TEXT_BASE		0x00001000
+
+/* U-Boot general configuration */
+#define CONFIG_SYS_LONGHELP
+#ifndef CONFIG_SYS_PROMPT
+#endif
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O buffer size */
+#define CONFIG_SYS_PBSIZE	\
+	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+						/* Print buffer size */
+#define CONFIG_SYS_MAXARGS	32		/* Max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+						/* Boot argument buffer size */
+#define CONFIG_VERSION_VARIABLE			/* U-BOOT version */
+#define CONFIG_AUTO_COMPLETE			/* Command auto complete */
+#define CONFIG_CMDLINE_EDITING			/* Command history etc */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+
+/* Booting Linux */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+
+/*
+ * Drivers
+ */
+
+/* APBH DMA */
+#define CONFIG_APBH_DMA
+
+/* GPIO */
+#define CONFIG_MXS_GPIO
+
+/*
+ * DUART Serial Driver.
+ * Conflicts with AUART driver which can be set by board.
+ */
+#ifndef CONFIG_MXS_AUART
+#define CONFIG_PL011_SERIAL
+#define CONFIG_PL011_CLOCK		24000000
+#define CONFIG_PL01x_PORTS		{ (void *)MXS_UARTDBG_BASE }
+#define CONFIG_CONS_INDEX		0
+#endif
+/* Default baudrate can be overriden by board! */
+#ifndef CONFIG_BAUDRATE
+#define CONFIG_BAUDRATE			115200
+#endif
+
+/* FEC Ethernet on SoC */
+#ifdef CONFIG_FEC_MXC
+#define CONFIG_MII
+#ifndef CONFIG_ETHPRIME
+#define CONFIG_ETHPRIME			"FEC0"
+#endif
+#ifndef CONFIG_FEC_XCV_TYPE
+#define CONFIG_FEC_XCV_TYPE		RMII
+#endif
+#endif
+
+/* I2C */
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_I2C_MXS
+#define CONFIG_HARD_I2C
+#ifndef CONFIG_SYS_I2C_SPEED
+#define CONFIG_SYS_I2C_SPEED		400000
+#endif
+#endif
+
+/* LCD */
+#ifdef CONFIG_VIDEO
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_MXS
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#endif
+
+/* MMC */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_MXS_MMC
+#endif
+
+/* NAND */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_MXS
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x60000000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#endif
+
+/* OCOTP */
+#ifdef CONFIG_CMD_FUSE
+#define CONFIG_MXS_OCOTP
+#endif
+
+/* SPI */
+#ifdef CONFIG_CMD_SPI
+#define CONFIG_HARD_SPI
+#define CONFIG_MXS_SPI
+#define CONFIG_SPI_HALF_DUPLEX
+#endif
+
+/* USB */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MXS
+#define CONFIG_EHCI_IS_TDI
+#endif
+
+#endif	/* __CONFIGS_MXS_H__ */
diff --git a/qemu/roms/u-boot/include/configs/neo.h b/qemu/roms/u-boot/include/configs/neo.h
new file mode 100644
index 000000000..d54998588
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/neo.h
@@ -0,0 +1,238 @@
+/*
+ * (C) Copyright 2007-2008
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+
+#define CONFIG_405EP		1	/* this is a PPC405 CPU */
+#define CONFIG_NEO	        1	/*  on a Neo board */
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
+
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME		neo
+#define CONFIG_IDENT_STRING	" neo 0.02"
+#include "amcc-common.h"
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_MISC_INIT_R
+#define CONFIG_LAST_STAGE_INIT
+
+#define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll   */
+
+/*
+ * Configure PLL
+ */
+#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
+#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
+
+#define CONFIG_ENV_IS_IN_FLASH	/* use FLASH for environment vars */
+
+/*
+ * Default environment variables
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_AMCC_DEF_ENV						\
+	CONFIG_AMCC_DEF_ENV_POWERPC					\
+	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
+	"kernel_addr=fc000000\0"					\
+	"fdt_addr=fc1e0000\0"						\
+	"ramdisk_addr=fc200000\0"					\
+	""
+
+#define CONFIG_PHY_ADDR		4	/* PHY address			*/
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_PHY1_ADDR	0xc	/* EMAC1 PHY address		*/
+#define CONFIG_PHY_CLK_FREQ    EMAC_STACR_CLK_66MHZ
+
+/*
+ * Commands additional to the ones defined in amcc-common.h
+ */
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DTT
+#undef CONFIG_CMD_EEPROM
+
+/*
+ * SDRAM configuration (please see cpu/ppc/sdram.[ch])
+ */
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0 */
+
+/* SDRAM timings used in datasheet */
+#define CONFIG_SYS_SDRAM_CL            3	/* CAS latency */
+#define CONFIG_SYS_SDRAM_tRP           20	/* PRECHARGE command period */
+#define CONFIG_SYS_SDRAM_tRC           66	/* ACTIVE-to-ACTIVE command period */
+#define CONFIG_SYS_SDRAM_tRCD          20	/* ACTIVE-to-READ delay */
+#define CONFIG_SYS_SDRAM_tRFC		66	/* Auto refresh period */
+
+/*
+ * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
+ * The Linux BASE_BAUD define should match this configuration.
+ *    baseBaud = cpuClock/(uartDivisor*16)
+ * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * set Linux BASE_BAUD to 403200.
+ */
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+
+#undef  CONFIG_SYS_EXT_SERIAL_CLOCK           /* external serial clock */
+#undef  CONFIG_SYS_405_UART_ERRATA_59         /* 405GP/CR Rev. D silicon */
+#define CONFIG_SYS_BASE_BAUD		691200
+
+/*
+ * I2C stuff
+ */
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		100000
+
+/* RTC */
+#define CONFIG_RTC_DS1337
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68
+
+/* Temp sensor/hwmon/dtt */
+#define CONFIG_DTT_LM63		1	/* National LM63	*/
+#define CONFIG_DTT_SENSORS	{ 0 }	/* Sensor addresses	*/
+#define CONFIG_DTT_PWM_LOOKUPTABLE	\
+		{ { 40, 10 }, { 50, 20 }, { 60, 40 } }
+#define CONFIG_DTT_TACH_LIMIT	0xa10
+
+/*
+ * FLASH organization
+ */
+#define CONFIG_SYS_FLASH_CFI				/* The flash is CFI compatible	*/
+#define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/
+
+#define CONFIG_SYS_FLASH_BASE		0xFC000000
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash	*/
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector		*/
+#define CONFIG_ENV_ADDR		0xFFF00000
+#define	CONFIG_ENV_SIZE		0x20000	/* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	0xFFF20000
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+#endif
+
+/*
+ * PPC405 GPIO Configuration
+ */
+#define CONFIG_SYS_4xx_GPIO_TABLE { \
+{ \
+/* GPIO Core 0 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0	PerBLast   */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO1	TS1E	   */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO2	TS2E	   */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO3	TS1O	   */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO4	TS2O	   */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1      }, /* GPIO5	TS3	   */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO6	TS4	   */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO7	TS5	   */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO8	TS6	   */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO9	TrcClk	   */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10	PerCS1	   */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11	PerCS2	   */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12	PerCS3	   */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13	PerCS4	   */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14	PerAddr03  */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15	PerAddr04  */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16	PerAddr05  */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17	IRQ0	   */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18	IRQ1	   */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19	IRQ2	   */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO20	IRQ3	   */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO21	IRQ4	   */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO22	IRQ5	   */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO23	IRQ6	   */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24	UART0_DCD  */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25	UART0_DSR  */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26	UART0_RI   */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27	UART0_DTR  */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28	UART1_Rx   */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29	UART1_Tx   */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO30	RejectPkt0 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO31	RejectPkt1 */ \
+} \
+}
+
+/*
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory (OCM) for temperary stack until sdram is tested */
+#define CONFIG_SYS_TEMP_STACK_OCM        1
+
+/* On Chip Memory location */
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (NOR-FLASH) initialization                    */
+#define CONFIG_SYS_EBC_PB0AP		0x92015480
+#define CONFIG_SYS_EBC_PB0CR		0xFC0DA000  /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (NVRAM) initialization                                        */
+#define CONFIG_SYS_EBC_PB1AP		0x92015480
+#define CONFIG_SYS_EBC_PB1CR		0xFB85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit  */
+
+/* Memory Bank 2 (FPGA) initialization                 */
+#define CONFIG_SYS_FPGA0_BASE		0x7f100000
+#define CONFIG_SYS_EBC_PB2AP		0x92015480
+#define CONFIG_SYS_EBC_PB2CR		0x7f11a000  /* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */
+
+#define CONFIG_SYS_FPGA_BASE(k)		CONFIG_SYS_FPGA0_BASE
+
+#define CONFIG_SYS_FPGA_COUNT		1
+
+#define CONFIG_SYS_FPGA_PTR \
+	{ (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE }
+
+#define CONFIG_SYS_FPGA_COMMON
+
+/* Memory Bank 3 (Latches) initialization                      */
+#define CONFIG_SYS_LATCH_BASE		0x7f200000
+#define CONFIG_SYS_EBC_PB3AP		0x92015480
+#define CONFIG_SYS_EBC_PB3CR		0x7f21a000  /* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */
+
+#define CONFIG_SYS_LATCH0_RESET		0xffff
+#define CONFIG_SYS_LATCH0_BOOT		0xffff
+#define CONFIG_SYS_LATCH1_RESET		0xffbf
+#define CONFIG_SYS_LATCH1_BOOT		0xffff
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/nhk8815.h b/qemu/roms/u-boot/include/configs/nhk8815.h
new file mode 100644
index 000000000..4d3428cb8
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/nhk8815.h
@@ -0,0 +1,181 @@
+/*
+ * (C) Copyright 2005
+ * STMicroelectronics.
+ * Configuration settings for the "Nomadik Hardware Kit" NHK-8815,
+ * the evaluation board for the Nomadik 8815 System on Chip.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <nomadik.h>
+
+#define CONFIG_ARM926EJS
+#define CONFIG_NOMADIK
+#define CONFIG_NOMADIK_8815	/* cpu variant */
+#define CONFIG_NOMADIK_NHK8815	/* board variant */
+
+#define CONFIG_SKIP_LOWLEVEL_INIT /* we have already been loaded to RAM */
+
+/* commands */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NFS
+/* There is no NOR flash, so undefine these commands */
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#define CONFIG_SYS_NO_FLASH
+/* There is NAND storage */
+#define CONFIG_NAND_NOMADIK
+#define CONFIG_CMD_JFFS2
+
+/* user interface */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT		"Nomadik> "
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE \
+					+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */
+#define CONFIG_SYS_MAXARGS	16
+#define CONFIG_SYS_LOAD_ADDR	0x800000	/* default load address */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE
+
+/* boot config */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_BOOTDELAY	1
+#define CONFIG_BOOTARGS	"root=/dev/ram0 console=ttyAMA1,115200n8 init=linuxrc"
+#define CONFIG_BOOTCOMMAND	"fsload 0x100000 kernel.uimg;" \
+				" fsload 0x800000 initrd.gz.uimg;" \
+				" bootm 0x100000 0x800000"
+
+/* memory-related information */
+#define CONFIG_NR_DRAM_BANKS	2
+#define PHYS_SDRAM_1		0x00000000	/* DDR-SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x04000000	/* 64 MB */
+#define PHYS_SDRAM_2		0x08000000	/* SDR-SDRAM BANK #2*/
+#define PHYS_SDRAM_2_SIZE	0x04000000	/* 64 MB */
+#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_1
+#define CONFIG_SYS_SDRAM_SIZE	(PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
+/* The IPL loads us at 0, tell so to u-boot. Put stack pointer 1M into RAM */
+#define CONFIG_SYS_TEXT_BASE    0x00000000
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + (1<<20))
+
+#define CONFIG_SYS_MEMTEST_START	0x00000000
+#define CONFIG_SYS_MEMTEST_END		0x0FFFFFFF
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 256 * 1024)
+
+#define CONFIG_BOARD_LATE_INIT	/* call board_late_init during start up */
+
+/* timing informazion */
+#define CONFIG_SYS_TIMERBASE	0x101E2000
+
+/* serial port (PL011) configuration */
+#define CONFIG_PL011_SERIAL
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		115200
+#define CFG_SERIAL0		0x101FD000
+#define CFG_SERIAL1		0x101FB000
+
+#define CONFIG_PL01x_PORTS	{ (void *)CFG_SERIAL0, (void *)CFG_SERIAL1 }
+#define CONFIG_PL011_CLOCK	48000000
+
+/* i2c, for the port extenders (uses gpio.c in board directory) */
+#ifndef __ASSEMBLY__
+#include <asm/arch/gpio.h>
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define	CONFIG_SYS_I2C_SOFT	1	/* I2C bit-banged	*/
+#define I2C_SOFT_DEFS
+#define CONFIG_SYS_I2C_SOFT_SPEED	400000
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0x7F
+#define __SDA			63
+#define __SCL			62
+#define I2C_SDA(x)		nmk_gpio_set(__SDA, x)
+#define I2C_SCL(x)		nmk_gpio_set(__SCL, x)
+#define I2C_READ		(nmk_gpio_get(__SDA)!=0)
+#define I2C_ACTIVE		nmk_gpio_dir(__SDA, 1)
+#define I2C_TRISTATE		nmk_gpio_dir(__SDA, 0)
+#define I2C_DELAY     (udelay(2))
+#endif /* __ASSEMBLY__ */
+
+/* Ethernet */
+#define PCI_MEMORY_VADDR	0xe8000000
+#define PCI_IO_VADDR		0xee000000
+#define __io(a)			((void __iomem *)(PCI_IO_VADDR + (a)))
+#define __mem_isa(a)		((a) + PCI_MEMORY_VADDR)
+
+#define CONFIG_SMC91111	/* Using SMC91c111*/
+#define CONFIG_SMC91111_BASE	0x34000300
+#undef  CONFIG_SMC91111_EXT_PHY	/* Internal PHY */
+#define CONFIG_SMC_USE_32_BIT
+#define CONFIG_BOOTFILE		"uImage"
+
+#define CONFIG_IP_DEFRAG	/* Allows faster download, TFTP and NFS */
+#define CONFIG_TFTP_BLOCKSIZE	4096
+#define CONFIG_NFS_READ_SIZE	4096
+
+/* Storage information: onenand and nand */
+#define CONFIG_CMD_ONENAND
+#define CONFIG_MTD_ONENAND_VERIFY_WRITE
+#define CONFIG_SYS_ONENAND_BASE		0x30000000
+
+#define CONFIG_CMD_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x40000000 /* SMPS0n */
+
+/*
+ * Filesystem information
+ *
+ * Since U-Boot has been loaded to RAM by vendor code, we could use
+ * either or both OneNand and Nand. However, we need to know where the
+ * filesystem lives. Comments below report vendor-selected partitions
+ */
+#ifdef CONFIG_BOOT_ONENAND
+   /* Partition				Size	Start
+    * XloaderTOC + X-Loader		256KB	0x00000000
+    * Memory init function		256KB	0x00040000
+    * U-Boot + env			2MB	0x00080000
+    * Sysimage (kernel + ramdisk)	4MB	0x00280000
+    * JFFS2 Root filesystem		22MB	0x00680000
+    * JFFS2 User Data			227.5MB	0x01C80000
+    */
+#   define CONFIG_JFFS2_DEV		"onenand0"
+#   define CONFIG_JFFS2_PART_SIZE	0x01600000
+#   define CONFIG_JFFS2_PART_OFFSET	0x00680000
+#   define CONFIG_ENV_IS_IN_ONENAND
+#   define CONFIG_ENV_SIZE		0x20000 /* 128 Kb - one sector */
+#   define CONFIG_ENV_ADDR		(0x00280000 - CONFIG_ENV_SIZE)
+
+#else /*  BOOT_NAND */
+   /* Partition				Size	Start
+    * XloaderTOC + X-Loader		256KB	0x00000000
+    * Memory init function		256KB	0x00040000
+    * U-Boot + env			2MB	0x00080000
+    * Kernel Image			3MB	0x00280000
+    * JFFS2 Root filesystem		22MB	0x00580000
+    * JFFS2 User Data			100.5MB	0x01b80000
+    */
+#   define CONFIG_JFFS2_DEV		"nand0"
+#   define CONFIG_JFFS2_NAND		1 /* For the jffs2 support*/
+#   define CONFIG_JFFS2_PART_SIZE	0x01600000
+#   define CONFIG_JFFS2_PART_OFFSET	0x00580000
+#   define CONFIG_ENV_IS_IN_NAND
+#   define CONFIG_ENV_SIZE		0x20000 /* 128 Kb - one sector */
+#   define CONFIG_ENV_OFFSET		(0x00280000 - CONFIG_ENV_SIZE)
+
+#endif /* CONFIG_BOOT_ONENAND */
+
+/* this is needed to make hello_world.c and other stuff happy */
+#define CONFIG_SYS_MAX_FLASH_SECT	512
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/nios2-generic.h b/qemu/roms/u-boot/include/configs/nios2-generic.h
new file mode 100644
index 000000000..1578b010b
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/nios2-generic.h
@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * BOARD/CPU
+ */
+#include "../board/altera/nios2-generic/custom_fpga.h" /* fpga parameters */
+#define CONFIG_BOARD_NAME "nios2-generic" /* custom board name */
+#define CONFIG_BOARD_EARLY_INIT_F	/* enable early board-spec. init */
+#define CONFIG_SYS_NIOS_SYSID_BASE	CONFIG_SYS_SYSID_BASE
+
+/*
+ * SERIAL
+ */
+#define CONFIG_ALTERA_UART
+#if defined(CONFIG_ALTERA_JTAG_UART)
+# define CONFIG_SYS_NIOS_CONSOLE	CONFIG_SYS_JTAG_UART_BASE
+#else
+# define CONFIG_SYS_NIOS_CONSOLE	CONFIG_SYS_UART_BASE
+#endif
+
+#define CONFIG_ALTERA_JTAG_UART_BYPASS
+#define CONFIG_SYS_NIOS_FIXEDBAUD
+#define CONFIG_BAUDRATE		CONFIG_SYS_UART_BAUD
+#define CONFIG_SYS_BAUDRATE_TABLE	{CONFIG_BAUDRATE}
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	/* Suppress console info */
+
+/*
+ * TIMER
+ */
+#define CONFIG_SYS_LOW_RES_TIMER
+#define CONFIG_SYS_NIOS_TMRBASE	CONFIG_SYS_TIMER_BASE
+#define CONFIG_SYS_NIOS_TMRIRQ		CONFIG_SYS_TIMER_IRQ
+#define CONFIG_SYS_NIOS_TMRMS		10	/* Desired period (msec)*/
+#define CONFIG_SYS_NIOS_TMRCNT \
+	(CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_TIMER_FREQ / 1000) - 1)
+
+/*
+ * STATUS LED
+ */
+#define CONFIG_ALTERA_PIO
+#define CONFIG_SYS_ALTERA_PIO_NUM	1
+#define CONFIG_SYS_ALTERA_PIO_GPIO_NUM	LED_PIO_WIDTH
+
+#define CONFIG_STATUS_LED		/* Enable status driver */
+#define CONFIG_BOARD_SPECIFIC_LED
+#define CONFIG_GPIO_LED		/* Enable GPIO LED driver */
+#define CONFIG_GPIO			/* Enable GPIO driver */
+
+#define STATUS_LED_BIT			0	/* Bit-0 on GPIO */
+#define STATUS_LED_STATE		1	/* Blinking */
+#define STATUS_LED_PERIOD	(500 / CONFIG_SYS_NIOS_TMRMS) /* 500 msec */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BOOTD
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_ITEST
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
+
+#ifdef CONFIG_CMD_NET
+# define CONFIG_CMD_DHCP
+# define CONFIG_CMD_PING
+#endif
+
+/*
+ * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
+ * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
+ * reset address, no? This will keep the environment in user region
+ * of flash. NOTE: the monitor length must be multiple of sector size
+ * (which is common practice).
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+
+#define CONFIG_ENV_SIZE		0x10000	/* 64k, 1 sector */
+#define CONFIG_ENV_OVERWRITE		/* Serial change Ok	*/
+#define CONFIG_ENV_ADDR		((CONFIG_SYS_RESET_ADDR + \
+					  CONFIG_SYS_MONITOR_LEN) | \
+					 CONFIG_SYS_FLASH_BASE)
+
+/*
+ * MEMORY ORGANIZATION
+ * -Monitor at top of sdram.
+ * -The heap is placed below the monitor
+ * -The stack is placed below the heap (&grows down).
+ */
+#define CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_SYS_MONITOR_LEN		0x40000	/* Reserve 256k */
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_SDRAM_BASE + \
+					 CONFIG_SYS_SDRAM_SIZE - \
+					 CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 0x20000)
+#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MONITOR_BASE - \
+					 CONFIG_SYS_MALLOC_LEN)
+#define CONFIG_SYS_INIT_SP		CONFIG_SYS_MALLOC_BASE
+
+/*
+ * MISC
+ */
+#define CONFIG_SYS_LONGHELP		/* Provide extended help */
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O buf size */
+#define CONFIG_SYS_MAXARGS		16	/* Max command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Bootarg buf size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + \
+					 16)	/* Print buf size */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_INIT_SP - 0x20000)
+#define CONFIG_CMDLINE_EDITING
+
+#define CONFIG_SYS_HUSH_PARSER
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/nitrogen6x.h b/qemu/roms/u-boot/include/configs/nitrogen6x.h
new file mode 100644
index 000000000..f7e7315a9
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/nitrogen6x.h
@@ -0,0 +1,366 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Boundary Devices Nitrogen6X
+ * and Freescale i.MX6Q Sabre Lite boards.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+#define CONFIG_MX6
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_MACH_TYPE	3769
+
+#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/gpio.h>
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MISC_INIT_R
+#define CONFIG_MXC_GPIO
+#define CONFIG_CI_UDC
+#define CONFIG_USBD_HS
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_ETHER
+#define CONFIG_USB_ETH_CDC
+#define CONFIG_NETCONSOLE
+
+#define CONFIG_CMD_FUSE
+#ifdef CONFIG_CMD_FUSE
+#define CONFIG_MXC_OCOTP
+#endif
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	       UART2_BASE
+
+#define CONFIG_CMD_SF
+#ifdef CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_MXC_SPI
+#define CONFIG_SF_DEFAULT_BUS  0
+#define CONFIG_SF_DEFAULT_CS   (0|(IMX_GPIO_NR(3, 19)<<8))
+#define CONFIG_SF_DEFAULT_SPEED 25000000
+#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
+#endif
+
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_SPEED		100000
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR      0
+#define CONFIG_SYS_FSL_USDHC_NUM       2
+
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+#ifdef CONFIG_MX6Q
+#define CONFIG_CMD_SATA
+#endif
+
+/*
+ * SATA Configs
+ */
+#ifdef CONFIG_CMD_SATA
+#define CONFIG_DWC_AHSATA
+#define CONFIG_SYS_SATA_MAX_DEVICE	1
+#define CONFIG_DWC_AHSATA_PORT_ID	0
+#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
+#define CONFIG_LBA48
+#define CONFIG_LIBATA
+#endif
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE		RGMII
+#define CONFIG_ETHPRIME			"FEC"
+#define CONFIG_FEC_MXC_PHYADDR		6
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9021
+
+/* USB Configs */
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_FAT
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_MCS7830
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET	/* For OTG port */
+#define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS	0
+
+/* Miscellaneous commands */
+#define CONFIG_CMD_BMODE
+#define CONFIG_CMD_SETEXPR
+
+/* Framebuffer and LCD */
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_IPUV3
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_IPUV3_CLK 260000000
+#define CONFIG_CMD_HDMIDETECT
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_IMX_HDMI
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX	       1
+#define CONFIG_BAUDRATE			       115200
+
+/* Command definition */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY	       1
+
+#define CONFIG_PREBOOT                 ""
+
+#define CONFIG_LOADADDR			       0x12000000
+#define CONFIG_SYS_TEXT_BASE	       0x17800000
+
+#ifdef CONFIG_CMD_SATA
+#define CONFIG_DRIVE_SATA "sata "
+#else
+#define CONFIG_DRIVE_SATA
+#endif
+
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_DRIVE_MMC "mmc "
+#else
+#define CONFIG_DRIVE_MMC
+#endif
+
+#define CONFIG_DRIVE_TYPES CONFIG_DRIVE_SATA CONFIG_DRIVE_MMC
+
+#if defined(CONFIG_SABRELITE)
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"uimage=uImage\0" \
+	"console=ttymxc1\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_file=imx6q-sabrelite.dtb\0" \
+	"fdt_addr=0x18000000\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"mmcdev=0\0" \
+	"mmcpart=1\0" \
+	"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootm ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootm; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootm; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs " \
+	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+		"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${uimage}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootm ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootm; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootm; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	   "mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loaduimage; then " \
+				   "run mmcboot; " \
+			   "else run netboot; " \
+			   "fi; " \
+		   "fi; " \
+	   "else run netboot; fi"
+#else
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"console=ttymxc1\0" \
+	"clearenv=if sf probe || sf probe || sf probe 1 ; then " \
+		"sf erase 0xc0000 0x2000 && " \
+		"echo restored environment to factory default ; fi\0" \
+	"bootcmd=for dtype in " CONFIG_DRIVE_TYPES \
+		"; do " \
+			"for disk in 0 1 ; do ${dtype} dev ${disk} ;" \
+				"for fs in fat ext2 ; do " \
+					"${fs}load " \
+						"${dtype} ${disk}:1 " \
+						"10008000 " \
+						"/6x_bootscript" \
+						"&& source 10008000 ; " \
+				"done ; " \
+			"done ; " \
+		"done; " \
+		"setenv stdout serial,vga ; " \
+		"echo ; echo 6x_bootscript not found ; " \
+		"echo ; echo serial console at 115200, 8N1 ; echo ; " \
+		"echo details at http://boundarydevices.com/6q_bootscript ; " \
+		"setenv stdout serial\0" \
+	"upgradeu=for dtype in " CONFIG_DRIVE_TYPES \
+		"; do " \
+		"for disk in 0 1 ; do ${dtype} dev ${disk} ;" \
+		     "for fs in fat ext2 ; do " \
+				"${fs}load ${dtype} ${disk}:1 10008000 " \
+					"/6x_upgrade " \
+					"&& source 10008000 ; " \
+			"done ; " \
+		"done ; " \
+	"done\0" \
+
+#endif
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT	       "U-Boot > "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE	       1024
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	       16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START       0x10000000
+#define CONFIG_SYS_MEMTEST_END	       0x10010000
+#define CONFIG_SYS_MEMTEST_SCRATCH     0x10800000
+
+#define CONFIG_SYS_LOAD_ADDR	       CONFIG_LOADADDR
+
+#define CONFIG_CMDLINE_EDITING
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS	       1
+#define PHYS_SDRAM		       MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE	       PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_SIZE			(8 * 1024)
+
+#if defined(CONFIG_SABRELITE)
+#define CONFIG_ENV_IS_IN_MMC
+#else
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#endif
+
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_ENV_OFFSET		(6 * 64 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+#define CONFIG_ENV_OFFSET		(768 * 1024)
+#define CONFIG_ENV_SECT_SIZE		(8 * 1024)
+#define CONFIG_ENV_SPI_BUS		CONFIG_SF_DEFAULT_BUS
+#define CONFIG_ENV_SPI_CS		CONFIG_SF_DEFAULT_CS
+#define CONFIG_ENV_SPI_MODE		CONFIG_SF_DEFAULT_MODE
+#define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
+#endif
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+#endif
+
+#define CONFIG_CMD_BMP
+
+#define CONFIG_CMD_TIME
+#define CONFIG_SYS_ALT_MEMTEST
+
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_SUPPORT_RAW_INITRD
+#define CONFIG_CMD_FS_GENERIC
+
+/*
+ * PCI express
+ */
+#ifdef CONFIG_CMD_PCI
+#define CONFIG_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_PCIE_IMX
+#endif
+
+#endif	       /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/nokia_rx51.h b/qemu/roms/u-boot/include/configs/nokia_rx51.h
new file mode 100644
index 000000000..e0c0fac8e
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/nokia_rx51.h
@@ -0,0 +1,470 @@
+/*
+ * (C) Copyright 2011-2012
+ * Pali Rohár <pali.rohar@gmail.com>
+ *
+ * (C) Copyright 2010
+ * Alistair Buxton <a.j.buxton@gmail.com>
+ *
+ * Derived from Beagle Board code:
+ * (C) Copyright 2006-2008
+ * Texas Instruments.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * Configuration settings for the Nokia RX-51 aka N900.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+
+#define CONFIG_OMAP			/* in a TI OMAP core */
+#define CONFIG_OMAP34XX			/* which is a 34XX */
+#define CONFIG_OMAP3430			/* which is in a 3430 */
+#define CONFIG_OMAP3_RX51		/* working with RX51 */
+#define CONFIG_SYS_L2CACHE_OFF		/* pretend there is no L2 CACHE */
+#define CONFIG_OMAP_COMMON
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_NOKIA_RX51
+
+/*
+ * Nokia X-Loader loading secondary image to address 0x80400000
+ * NOLO loading boot image to random place, so it doesn't really
+ * matter what we set this to. We have to copy u-boot to this address
+ */
+#define CONFIG_SYS_TEXT_BASE	0x80008000
+
+#define CONFIG_SDRC			/* The chip has SDRC controller */
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+#include <asm/arch/omap3.h>
+#include <asm/arch/mem.h>
+#include <linux/stringify.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Clock Defines */
+#define V_OSCK			26000000	/* Clock output from T2 */
+#define V_SCLK			(V_OSCK >> 1)
+
+#undef CONFIG_USE_IRQ				/* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_SKIP_LOWLEVEL_INIT		/* X-Loader set everything up */
+
+#define CONFIG_CMDLINE_TAG	/* enable passing kernel command line string */
+#define CONFIG_INITRD_TAG			/* enable passing initrd */
+#define CONFIG_REVISION_TAG			/* enable passing revision tag*/
+#define CONFIG_SETUP_MEMORY_TAGS		/* enable memory tag */
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE			(128 << 10)
+#define CONFIG_UBI_SIZE			(512 << 10)
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + CONFIG_UBI_SIZE + \
+					(128 << 10))
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK		48000000		/* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX		3
+#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
+#define CONFIG_SERIAL3			3		/* UART3 on RX-51 */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_DOS_PARTITION
+
+/* USB */
+#define CONFIG_MUSB_UDC
+#define CONFIG_MUSB_HDC
+#define CONFIG_USB_OMAP3
+#define CONFIG_TWL4030_USB
+
+/* USB device configuration */
+#define CONFIG_USB_DEVICE
+#define CONFIG_USBD_VENDORID		0x0421
+#define CONFIG_USBD_PRODUCTID		0x01c8
+#define CONFIG_USBD_MANUFACTURER	"Nokia"
+#define CONFIG_USBD_PRODUCT_NAME	"N900"
+
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_NO_FLASH
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_EXT2			/* EXT2 Support */
+#define CONFIG_CMD_EXT4			/* EXT4 Support */
+#define CONFIG_CMD_FAT			/* FAT support */
+
+#define CONFIG_CMD_I2C			/* I2C serial bus support */
+#define CONFIG_CMD_MMC			/* MMC support */
+#define CONFIG_CMD_GPIO			/* Enable gpio command */
+
+#define CONFIG_CMDLINE_EDITING		/* add command line history */
+#define CONFIG_AUTO_COMPLETE		/* add autocompletion support */
+
+#define CONFIG_CMD_BOOTMENU		/* ANSI terminal Boot Menu */
+#define CONFIG_CMD_CLEAR		/* ANSI terminal clear screen command */
+
+#ifdef ONENAND_SUPPORT
+
+#define CONFIG_CMD_ONENAND		/* ONENAND support */
+#define CONFIG_CMD_MTDPARTS		/* mtd parts support */
+
+#ifdef UBIFS_SUPPORT
+#define CONFIG_CMD_UBI			/* UBI Support */
+#define CONFIG_CMD_UBIFS		/* UBIFS Support */
+#endif
+
+#endif
+
+/* commands not needed from config_cmd_default.h */
+#undef CONFIG_CMD_FPGA			/* FPGA configuration Support */
+#undef CONFIG_CMD_IMI			/* iminfo */
+#undef CONFIG_CMD_NET			/* bootp, tftpboot, rarpboot */
+#undef CONFIG_CMD_NFS			/* NFS support */
+#undef CONFIG_CMD_SAVEENV		/* saveenv */
+#undef CONFIG_CMD_SETGETDCR		/* DCR support on 4xx */
+
+#define CONFIG_OMAP3_SPI
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
+#define CONFIG_SYS_I2C_OMAP34XX
+
+/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER
+#define CONFIG_TWL4030_LED
+#define CONFIG_TWL4030_KEYPAD
+
+#define CONFIG_OMAP_GPIO
+#define GPIO_SLIDE			71
+
+/*
+ * Board ONENAND Info.
+ */
+
+#define PART1_NAME			"bootloader"
+#define PART1_SIZE			128
+#define PART1_MULL			1024
+#define PART1_SUFF			"k"
+#define PART1_OFFS			0x00000000
+#define PART1_MASK			0x00000003
+
+#define PART2_NAME			"config"
+#define PART2_SIZE			384
+#define PART2_MULL			1024
+#define PART2_SUFF			"k"
+#define PART2_OFFS			0x00020000
+#define PART2_MASK			0x00000000
+
+#define PART3_NAME			"log"
+#define PART3_SIZE			256
+#define PART3_MULL			1024
+#define PART3_SUFF			"k"
+#define PART3_OFFS			0x00080000
+#define PART3_MASK			0x00000000
+
+#define PART4_NAME			"kernel"
+#define PART4_SIZE			2
+#define PART4_MULL			1024*1024
+#define PART4_SUFF			"m"
+#define PART4_OFFS			0x000c0000
+#define PART4_MASK			0x00000000
+
+#define PART5_NAME			"initfs"
+#define PART5_SIZE			2
+#define PART5_MULL			1024*1024
+#define PART5_SUFF			"m"
+#define PART5_OFFS			0x002c0000
+#define PART5_MASK			0x00000000
+
+#define PART6_NAME			"rootfs"
+#define PART6_SIZE			257280
+#define PART6_MULL			1024
+#define PART6_SUFF			"k"
+#define PART6_OFFS			0x004c0000
+#define PART6_MASK			0x00000000
+
+#ifdef ONENAND_SUPPORT
+
+#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
+#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M
+#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+
+#ifdef UBIFS_SUPPORT
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#endif
+
+#define MTDIDS_DEFAULT			"onenand0=onenand"
+#define MTDPARTS_DEFAULT		"mtdparts=onenand:" \
+		__stringify(PART1_SIZE) PART1_SUFF "(" PART1_NAME ")ro," \
+		__stringify(PART2_SIZE) PART2_SUFF "(" PART2_NAME ")," \
+		__stringify(PART3_SIZE) PART3_SUFF "(" PART3_NAME ")," \
+		__stringify(PART4_SIZE) PART4_SUFF "(" PART4_NAME ")," \
+		__stringify(PART5_SIZE) PART5_SUFF "(" PART5_NAME ")," \
+		"-(" PART6_NAME ")"
+
+#endif
+
+/* Watchdog support */
+#define CONFIG_HW_WATCHDOG
+
+/*
+ * Framebuffer
+ */
+/* Video console */
+#define CONFIG_VIDEO
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_CFB_CONSOLE_ANSI	/* Enable ANSI escape codes in framebuffer */
+#define CONFIG_VIDEO_LOGO
+#define VIDEO_FB_16BPP_PIXEL_SWAP
+#define VIDEO_FB_16BPP_WORD_SWAP
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_SPLASH_SCREEN
+
+/* functions for cfb_console */
+#define VIDEO_KBD_INIT_FCT		rx51_kp_init()
+#define VIDEO_TSTC_FCT			rx51_kp_tstc
+#define VIDEO_GETC_FCT			rx51_kp_getc
+#ifndef __ASSEMBLY__
+int rx51_kp_init(void);
+int rx51_kp_tstc(void);
+int rx51_kp_getc(void);
+#endif
+
+#ifndef MTDPARTS_DEFAULT
+#define MTDPARTS_DEFAULT
+#endif
+
+/* Environment information */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"usbtty=cdc_acm\0" \
+	"stdin=vga\0" \
+	"stdout=vga\0" \
+	"stderr=vga\0" \
+	"setcon=setenv stdin ${con};" \
+		"setenv stdout ${con};" \
+		"setenv stderr ${con}\0" \
+	"sercon=setenv con serial; run setcon\0" \
+	"usbcon=setenv con usbtty; run setcon\0" \
+	"vgacon=setenv con vga; run setcon\0" \
+	"slide=gpio input " __stringify(GPIO_SLIDE) "\0" \
+	"switchmmc=mmc dev ${mmcnum}\0" \
+	"kernaddr=0x82008000\0" \
+	"initrdaddr=0x84008000\0" \
+	"scriptaddr=0x86008000\0" \
+	"fileload=${mmctype}load mmc ${mmcnum}:${mmcpart} " \
+		"${loadaddr} ${mmcfile}\0" \
+	"kernload=setenv loadaddr ${kernaddr};" \
+		"setenv mmcfile ${mmckernfile};" \
+		"run fileload\0" \
+	"initrdload=setenv loadaddr ${initrdaddr};" \
+		"setenv mmcfile ${mmcinitrdfile};" \
+		"run fileload\0" \
+	"scriptload=setenv loadaddr ${scriptaddr};" \
+		"setenv mmcfile ${mmcscriptfile};" \
+		"run fileload\0" \
+	"scriptboot=echo Running ${mmcscriptfile} from mmc " \
+		"${mmcnum}:${mmcpart} ...; source ${scriptaddr}\0" \
+	"kernboot=echo Booting ${mmckernfile} from mmc " \
+		"${mmcnum}:${mmcpart} ...; bootm ${kernaddr}\0" \
+	"kerninitrdboot=echo Booting ${mmckernfile} ${mmcinitrdfile} from mmc "\
+		"${mmcnum}:${mmcpart} ...; bootm ${kernaddr} ${initrdaddr}\0" \
+	"attachboot=echo Booting attached kernel image ...;" \
+		"setenv setup_omap_atag 1;" \
+		"bootm ${attkernaddr};" \
+		"setenv setup_omap_atag\0" \
+	"trymmcscriptboot=if run switchmmc; then " \
+			"if run scriptload; then " \
+				"run scriptboot;" \
+			"fi;" \
+		"fi\0" \
+	"trymmckernboot=if run switchmmc; then " \
+			"if run kernload; then " \
+				"run kernboot;" \
+			"fi;" \
+		"fi\0" \
+	"trymmckerninitrdboot=if run switchmmc; then " \
+			"if run initrdload; then " \
+				"if run kernload; then " \
+					"run kerninitrdboot;" \
+				"fi;" \
+			"fi; " \
+		"fi\0" \
+	"trymmcpartboot=setenv mmcscriptfile boot.scr; run trymmcscriptboot;" \
+		"setenv mmckernfile uImage; run trymmckernboot\0" \
+	"trymmcallpartboot=setenv mmcpart 1; run trymmcpartboot;" \
+		"setenv mmcpart 2; run trymmcpartboot;" \
+		"setenv mmcpart 3; run trymmcpartboot;" \
+		"setenv mmcpart 4; run trymmcpartboot\0" \
+	"trymmcboot=if run switchmmc; then " \
+			"setenv mmctype fat;" \
+			"run trymmcallpartboot;" \
+			"setenv mmctype ext2;" \
+			"run trymmcallpartboot;" \
+			"setenv mmctype ext4;" \
+			"run trymmcallpartboot;" \
+		"fi\0" \
+	"emmcboot=setenv mmcnum 1; run trymmcboot\0" \
+	"sdboot=setenv mmcnum 0; run trymmcboot\0" \
+	"menucmd=bootmenu\0" \
+	"bootmenu_0=Attached kernel=run attachboot\0" \
+	"bootmenu_1=Internal eMMC=run emmcboot\0" \
+	"bootmenu_2=External SD card=run sdboot\0" \
+	"bootmenu_3=U-Boot boot order=boot\0" \
+	"bootmenu_delay=30\0" \
+	""
+
+#define CONFIG_PREBOOT \
+	"setenv mmcnum 1; setenv mmcpart 1;" \
+	"setenv mmcscriptfile bootmenu.scr;" \
+	"if run switchmmc; then " \
+		"setenv mmcdone true;" \
+		"setenv mmctype fat;" \
+		"if run scriptload; then true; else " \
+			"setenv mmctype ext2;" \
+			"if run scriptload; then true; else " \
+				"setenv mmctype ext4;" \
+				"if run scriptload; then true; else " \
+					"setenv mmcdone false;" \
+				"fi;" \
+			"fi;" \
+		"fi;" \
+		"if ${mmcdone}; then " \
+			"run scriptboot;" \
+		"fi;" \
+	"fi;" \
+	"if run slide; then true; else " \
+		"setenv bootmenu_delay 0;" \
+		"setenv bootdelay 0;" \
+	"fi"
+
+#define CONFIG_POSTBOOTMENU \
+	"echo;" \
+	"echo Extra commands:;" \
+	"echo run sercon - Use serial port for control.;" \
+	"echo run usbcon - Use usbtty for control.;" \
+	"echo run vgacon - Use framebuffer/keyboard.;" \
+	"echo run sdboot - Boot from SD card slot.;" \
+	"echo run emmcboot - Boot internal eMMC memory.;" \
+	"echo run attachboot - Boot attached kernel image.;" \
+	"echo"
+
+#define CONFIG_BOOTCOMMAND \
+	"run sdboot;" \
+	"run emmcboot;" \
+	"run attachboot;" \
+	"echo"
+
+#define CONFIG_BOOTDELAY 30
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_MENU
+#define CONFIG_MENU_SHOW
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_PROMPT		"Nokia RX-51 # "
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+						sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
+
+#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
+#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + 0x01F00000)/*31MB*/
+
+/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
+#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE		(128 << 10) /* regular stack 128 KiB */
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS		2
+#define PHYS_SDRAM_1			OMAP34XX_SDRC_CS0
+
+/*
+ * FLASH and environment organization
+ */
+
+#define CONFIG_ENV_IS_NOWHERE
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE	0x800
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+			CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * Attached kernel image
+ */
+
+#define SDRAM_SIZE			0x10000000	/* 256 MB */
+#define SDRAM_END			(CONFIG_SYS_SDRAM_BASE + SDRAM_SIZE)
+
+#define IMAGE_MAXSIZE			0x1FF800	/* 2 MB - 2 kB */
+#define KERNEL_OFFSET			0x40000		/* 256 kB */
+#define KERNEL_MAXSIZE			(IMAGE_MAXSIZE-KERNEL_OFFSET)
+#define KERNEL_ADDRESS			(SDRAM_END-KERNEL_MAXSIZE)
+
+/* Reserve protected RAM for attached kernel */
+#define CONFIG_PRAM			((KERNEL_MAXSIZE >> 10)+1)
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/o2d.h b/qemu/roms/u-boot/include/configs/o2d.h
new file mode 100644
index 000000000..eff1bcef3
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/o2d.h
@@ -0,0 +1,77 @@
+/*
+ * (C) Copyright 2012
+ * DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Valid values for CONFIG_SYS_TEXT_BASE are:
+ * 0xFC000000   boot low boot high (standard configuration)
+ * 0x00100000   boot from RAM (for testing only)
+ */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xfc000000	/* Standard: boot low */
+#endif
+
+/* Board specific flash config */
+#define CONFIG_SYS_FLASH_BASE		0xfc000000
+#define CONFIG_SYS_FLASH_SIZE		0x04000000      /* maximum 64MB */
+/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_SECT	512
+
+/*
+ * Include common defines for all ifm boards
+ */
+#include "o2dnt-common.h"
+
+/* additional commands */
+#define CONFIG_CMD_ITEST
+
+/*
+ * GPIO configuration:
+ * CS1 SDRAM activate + no CAN + no PCI
+ */
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x8000A004
+
+/* Other board specific configs */
+#define CONFIG_SYS_BOOTCS_CFG		0x00057d01
+#define CONFIG_SYS_RESET_ADDRESS	0xfc000000
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000      /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x07f00000	/* 1 - 127 MB in DRAM */
+
+#define CONFIG_BOARD_NAME		"o2d"
+#define CONFIG_BOARD_BOOTCMD		"run dhcp_boot"
+#define CONFIG_BOARD_MEM_LIMIT		xstr(126)
+#define BOARD_POST_CRC32_END		xstr(0x01000000)
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_IFM_DEFAULT_ENV_SETTINGS					\
+	CONFIG_IFM_DEFAULT_ENV_OLD					\
+	CONFIG_IFM_DEFAULT_ENV_NEW					\
+	"linbot=fc060000\0"						\
+	"lintop=fc15ffff\0"						\
+	"rambot=fc160000\0"						\
+	"ramtop=fc55ffff\0"						\
+	"jffbot=fc560000\0"						\
+	"jfftop=fcffffff\0"						\
+	"ubobot=" xstr(CONFIG_SYS_FLASH_BASE) "\0"			\
+	"ubotop=fc03ffff\0"						\
+	"kernel_addr=0xfc060000\0"					\
+	"ramdisk_addr=0xfc160000\0"					\
+	"progCram=tftp ${fileaddr} ${cramfsname};"			\
+		"erase ${rambot} ${ramtop};"				\
+		"cp.b ${fileaddr} ${rambot} ${filesize}\0"		\
+	"flash_for_configs=22396\0"					\
+	"flash_mtd=run mtd_args addip addmem;"				\
+		"bootm ${kernel_addr}\0"				\
+	"mtd_args=setenv bootargs root=/dev/mtdblock3 "			\
+		"rw rootfstype=cramfs\0"				\
+	"master=mw f0000b00 0x8005A006;mw f0000b0c ${IOpin};"		\
+		"mw f0000b04 ${IOpin};mw f0000b10 0x20\0"		\
+	"dhcp_boot=run dhcpcmd;run flash_mtd\0"				\
+	"hostname=IFM_SENSOR\0"						\
+	"netretry=once\0"						\
+	"autoload=no\0"							\
+	"sensorType=O2D222AG\0"
diff --git a/qemu/roms/u-boot/include/configs/o2d300.h b/qemu/roms/u-boot/include/configs/o2d300.h
new file mode 100644
index 000000000..1af53834f
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/o2d300.h
@@ -0,0 +1,81 @@
+/*
+ * (C) Copyright 2012
+ * DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Valid values for CONFIG_SYS_TEXT_BASE are:
+ * 0xFC000000   boot low boot high (standard configuration)
+ * 0x00100000   boot from RAM (for testing only)
+ */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xfc000000	/* Standard: boot low */
+#endif
+
+/* Board specific flash config */
+#define CONFIG_SYS_FLASH_BASE		0xfc000000
+#define CONFIG_SYS_FLASH_SIZE		0x04000000      /* maximum 64MB */
+/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_SECT	512
+
+/*
+ * Include common defines for all ifm boards
+ */
+#include "o2dnt-common.h"
+
+/*
+ * GPIO configuration:
+ * CS1 SDRAM activate + no CAN + no PCI
+ */
+#define CONFIG_SYS_GPS_PORT_CONFIG      0x8000A004
+
+/* Other board specific configs */
+#define CONFIG_SYS_BOOTCS_CFG		0x00057d01
+#define CONFIG_SYS_RESET_ADDRESS	0xfc000000
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000      /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x07f00000	/* 1 - 127 MB in DRAM */
+
+/* Use redundant environment */
+#define CONFIG_ENV_ADDR_REDUND		(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND		(CONFIG_ENV_SIZE)
+
+#define CONFIG_BOARD_NAME		"o2d300"
+#define CONFIG_BOARD_BOOTCMD		"run dhcp_boot"
+#define CONFIG_BOARD_MEM_LIMIT		xstr(126)
+#define BOARD_POST_CRC32_END		xstr(0x02000000)
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_IFM_DEFAULT_ENV_SETTINGS					\
+	CONFIG_IFM_DEFAULT_ENV_OLD					\
+	CONFIG_IFM_DEFAULT_ENV_NEW					\
+	"autoload=no\0"							\
+	"dhcp_boot=run dhcpcmd;run flash_mtd\0"				\
+	"flash_mtd=run mtd_args addip addmem;"				\
+		"bootm ${kernel_addr}\0"				\
+	"mtd_args=setenv bootargs root=/dev/mtdblock4 "			\
+		"rw rootfstype=cramfs\0"				\
+	"linbot=fc080000\0"						\
+	"lintop=fc17ffff\0"						\
+	"rambot=fc180000\0"						\
+	"ramtop=fc57ffff\0"						\
+	"jffbot=fc580000\0"						\
+	"jfftop=fd39ffff\0"						\
+	"ubobot=" xstr(CONFIG_SYS_FLASH_BASE) "\0"			\
+	"ubotop=fc03ffff\0"						\
+	"halname="CONFIG_BOARD_NAME"/"CONFIG_BOARD_NAME"_halcon\0"	\
+	"halbot=fd3a0000\0"						\
+	"haltop=fdf9ffff\0"						\
+	"progHal=tftp 200000 ${halname};erase ${halbot} ${haltop};"	\
+		"cp.b ${fileaddr} ${halbot} ${filesize}\0"		\
+	"kernel_addr=0xfc060000\0"					\
+	"ramdisk_addr=0xfc160000\0"					\
+	"master=mw f0000b00 0x8005A006;mw f0000b0c ${IOpin};"		\
+		"mw f0000b04 ${IOpin};mw f0000b10 0x20\0"		\
+	"netretry=once\0"						\
+	"protcmd=protect on ${linbot} ${lintop};"			\
+		"protect on ${rambot} ${ramtop}\0"			\
+	"o2derror=def_env\0"						\
+	"sensorType=O2D300AA\0"
diff --git a/qemu/roms/u-boot/include/configs/o2dnt-common.h b/qemu/roms/u-boot/include/configs/o2dnt-common.h
new file mode 100644
index 000000000..133dc6f8c
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/o2dnt-common.h
@@ -0,0 +1,358 @@
+/*
+ *  Common configuration options for ifm camera boards
+ *
+ * (C) Copyright 2005
+ * Sebastien Cazaux, ifm electronic gmbh
+ *
+ * (C) Copyright 2012
+ * DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __O2D_CONFIG_H
+#define __O2D_CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_MPC5200
+
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* running at 33.000000MHz */
+
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+/* log base 2 of the above value */
+#define CONFIG_SYS_CACHELINE_SHIFT	5
+#endif
+
+/*
+#define CONFIG_POST	(CONFIG_SYS_POST_MEMORY | \
+			 CONFIG_SYS_POST_I2C)
+*/
+
+#ifdef CONFIG_POST
+/* preserve space for the post_word at end of on-chip SRAM */
+#define MPC5XXX_SRAM_POST_SIZE	(MPC5XXX_SRAM_SIZE - 4)
+#endif
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	5	/* console is on PSC5 */
+#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
+#define CONFIG_SYS_BAUDRATE_TABLE \
+	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*
+ * PCI Mapping:
+ * 0x40000000 - 0x4fffffff - PCI Memory
+ * 0x50000000 - 0x50ffffff - PCI IO Space
+ */
+#undef CONFIG_PCI
+#define CONFIG_PCI_PNP		1
+
+#define CONFIG_PCI_MEM_BUS	0x40000000
+#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE	0x10000000
+
+#define CONFIG_PCI_IO_BUS	0x50000000
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0x01000000
+
+#define CONFIG_SYS_XLB_PIPELINING	1
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+#define CONFIG_TIMESTAMP	/* Print image info with timestamp */
+
+#define CONFIG_SYS_ALT_MEMTEST	/* Much more complex memory test */
+
+/*
+ * Supported commands
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#endif
+#ifdef CONFIG_POST
+#define CONFIG_CMD_DIAG
+#endif
+
+#if (CONFIG_SYS_TEXT_BASE == 0xFC000000) || (CONFIG_SYS_TEXT_BASE == 0xFF000000)
+/* Boot low with 16 or 32 MB Flash */
+#define CONFIG_SYS_LOWBOOT	1
+#elif (CONFIG_SYS_TEXT_BASE != 0x00100000)
+#error "CONFIG_SYS_TEXT_BASE value is invalid"
+#endif
+
+/*
+ * Autobooting
+ * Be selective on what keys can delay or stop the autoboot process
+ * To stop use: "++++++++++"
+ */
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT	"Autobooting in %d seconds, " \
+				"press password to stop\n", bootdelay
+#define CONFIG_AUTOBOOT_STOP_STR	"++++++++++"
+#undef CONFIG_AUTOBOOT_DELAY_STR
+#define DEBUG_BOOTKEYS		0
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT	"run master"
+
+#undef	CONFIG_BOOTARGS
+
+#define xstr(s) str(s)
+#define str(s)  #s
+
+#if !defined(CONFIG_CONSOLE_DEV)
+#define CONFIG_CONSOLE_DEV	"ttyPSC1"
+#endif
+
+/*
+ * Default environment for booting old and new kernel versions
+ */
+#define CONFIG_IFM_DEFAULT_ENV_OLD					\
+	"flash_self_old=run ramargs addip addmem;"			\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"flash_nfs_old=run nfsargs addip addmem;"			\
+		"bootm ${kernel_addr}\0"				\
+	"net_nfs_old=tftp ${kernel_addr_r} ${bootfile};"		\
+		"run nfsargs addip addmem;"				\
+		"bootm ${kernel_addr_r}\0"
+
+#define CONFIG_IFM_DEFAULT_ENV_NEW					\
+	"fdt_addr_r=900000\0"						\
+	"fdt_file="CONFIG_BOARD_NAME"/"CONFIG_BOARD_NAME".dtb\0"	\
+	"flash_self=run ramargs addip addtty addmisc;"			\
+		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
+	"flash_nfs=run nfsargs addip addtty addmisc;"			\
+		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
+		"tftp ${fdt_addr_r} ${fdt_file}; "			\
+		"run nfsargs addip addtty addmisc;"			\
+		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
+
+#define	CONFIG_IFM_DEFAULT_ENV_SETTINGS					\
+	"IOpin=0x64\0"							\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addmem=setenv bootargs ${bootargs} ${memlimit}\0"		\
+	"addmisc=sete bootargs ${bootargs} ${miscargs}\0"		\
+	"addtty=sete bootargs ${bootargs} console="			\
+		CONFIG_CONSOLE_DEV ",${baudrate}\0"			\
+	"bootfile="CONFIG_BOARD_NAME"/uImage_"CONFIG_BOARD_NAME"_act\0"	\
+	"kernel_addr_r=600000\0"					\
+	"initrd_high=0x03e00000\0"					\
+	"memlimit=mem="CONFIG_BOARD_MEM_LIMIT"M\0"			\
+	"memtest=mtest 0x00100000 "xstr(CONFIG_SYS_MEMTEST_END)" 0 1\0"	\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"linuxname="CONFIG_BOARD_NAME"/uImage_"CONFIG_BOARD_NAME"_act\0"\
+	"progLinux=tftp 200000 ${linuxname};erase ${linbot} ${lintop};" \
+		"cp.b ${fileaddr} ${linbot} ${filesize}\0"		\
+	"ramname="CONFIG_BOARD_NAME"/uRamdisk_"CONFIG_BOARD_NAME"_act\0"\
+	"progRam=tftp 200000 ${ramname};erase ${rambot} ${ramtop};"	\
+		"cp.b ${fileaddr} ${rambot} ${filesize}\0"		\
+	"jffname="CONFIG_BOARD_NAME"/uJFFS2_"CONFIG_BOARD_NAME"_act\0"	\
+	"progJff=tftp 200000 ${jffname};erase ${jffbot} ${jfftop};"	\
+		"cp.b ${fileaddr} ${jffbot} ${filesize}\0"		\
+	"rootpath=/opt/eldk/ppc_6xx\0"					\
+	"uboname=" CONFIG_BOARD_NAME					\
+		"/u-boot.bin_" CONFIG_BOARD_NAME "_act\0"		\
+	"progubo=tftp 200000 ${uboname};"				\
+		"protect off ${ubobot} ${ubotop};"			\
+		"erase ${ubobot} ${ubotop};"				\
+		"cp.b ${fileaddr} ${ubobot} ${filesize}\0"		\
+	"unlock=yes\0"							\
+	"post=echo !!! "CONFIG_BOARD_NAME" POWER ON SELF TEST !!!;"	\
+		"setenv bootdelay 1;"					\
+		"crc32 "xstr(CONFIG_SYS_TEXT_BASE)" "			\
+			BOARD_POST_CRC32_END";"				\
+		"setenv bootcmd "CONFIG_BOARD_BOOTCMD";saveenv;reset\0"
+
+#define CONFIG_BOOTCOMMAND	"run post"
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
+
+#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
+/*
+ * PCI Bus clocking configuration
+ *
+ * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
+ * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
+ * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
+ */
+#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2	/* define for 66MHz speed */
+#endif
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C			1	/* I2C with hardware support */
+#define CONFIG_SYS_I2C_MODULE		1	/* Select I2C module #1 or #2 */
+#define CONFIG_SYS_I2C_SPEED		100000	/* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+
+/*
+ * EEPROM configuration:
+ *
+ * O2DNT board is equiped with Ramtron FRAM device FM24CL16
+ * 16 Kib Ferroelectric Nonvolatile serial RAM memory
+ * organized as 2048 x 8 bits and addressable as eight I2C devices
+ * 0x50 ... 0x57 each 256 bytes in size
+ *
+ */
+#define CONFIG_SYS_I2C_FRAM
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+/*
+ * There is no write delay with FRAM, write operations are performed at bus
+ * speed. Thus, no status polling or write delay is needed.
+ */
+
+/*
+ * Flash configuration
+ */
+#define CONFIG_SYS_FLASH_CFI		1
+#define CONFIG_FLASH_CFI_DRIVER		1
+#define CONFIG_FLASH_16BIT
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_CFI_AMD_RESET
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Erase Timeout (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Write Timeout (in ms) */
+/* Timeout for Flash Clear Lock Bits (in ms) */
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	10000
+/* "Real" (hardware) sectors protection */
+#define CONFIG_SYS_FLASH_PROTECTION
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_SIZE		0x20000
+#define CONFIG_ENV_SECT_SIZE	0x20000
+#define CONFIG_ENV_OVERWRITE	1
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00040000)
+
+/*
+ * Memory map
+ */
+#define CONFIG_SYS_MBAR		0xF0000000
+#define CONFIG_SYS_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
+
+/* Use SRAM until RAM will be available */
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+#ifdef CONFIG_POST
+/* preserve space for the post_word at end of on-chip SRAM */
+#define CONFIG_SYS_INIT_RAM_END		MPC5XXX_SRAM_POST_SIZE
+#else
+/* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_END		MPC5XXX_SRAM_SIZE
+#endif
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - \
+					 GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(192 << 10) /* 192 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10) /* 128 kB for malloc() */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)   /* Initial map for Linux */
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT		1
+#endif
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC
+#define CONFIG_MPC5xxx_FEC_MII100
+#define CONFIG_PHY_ADDR			0x00
+#define CONFIG_RESET_PHY_R
+
+/*
+ * GPIO configuration
+ */
+#define CONFIG_SYS_GPIO_DATADIR		0x00000064 /* PSC1_2, PSC2_1,2 output */
+#define CONFIG_SYS_GPIO_OPENDRAIN	0x00000000 /* No open drain */
+#define CONFIG_SYS_GPIO_DATAVALUE	0x00000000 /* PSC1_1 to 1, rest to 0 */
+#define CONFIG_SYS_GPIO_ENABLE		0x00000064 /* PSC1_2, PSC2_1,2 enable */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_HUSH_PARSER
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					 sizeof(CONFIG_SYS_PROMPT) + 16)
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS		16
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x100000
+
+/* decrementer freq: 1 ms ticks */
+
+/*
+ * Various low-level settings
+ */
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
+
+#define CONFIG_SYS_BOOTCS_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
+
+#define CONFIG_BOARD_EARLY_INIT_R
+
+#define CONFIG_SYS_CS_BURST		0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE		0x33333333
+
+/*
+ * DT support
+ */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+#define OF_CPU			"PowerPC,5200@0"
+#define OF_SOC			"soc5200@f0000000"
+#define OF_TBCLK		(bd->bi_busfreq / 4)
+
+#endif /* __O2D_CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/o2dnt2.h b/qemu/roms/u-boot/include/configs/o2dnt2.h
new file mode 100644
index 000000000..3636c0e1d
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/o2dnt2.h
@@ -0,0 +1,69 @@
+/*
+ * (C) Copyright 2012
+ * DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Valid values for CONFIG_SYS_TEXT_BASE are:
+ * 0xFC000000   boot low boot high (standard configuration)
+ * 0x00100000   boot from RAM (for testing only)
+ */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xfc000000	/* Standard: boot low */
+#endif
+
+/* Board specific flash config */
+#define CONFIG_SYS_FLASH_BASE		0xfc000000
+#define CONFIG_SYS_FLASH_SIZE		0x04000000      /* maximum 64MB */
+/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_SECT	512
+
+/*
+ * Include common defines for all ifm boards
+ */
+#include "o2dnt-common.h"
+
+/* additional commands */
+#define CONFIG_CMD_ITEST
+
+/*
+ * GPIO configuration:
+ * CS1 SDRAM activate + no CAN + no PCI
+ */
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x8000A004
+
+/* Other board specific configs */
+#define CONFIG_SYS_BOOTCS_CFG		0x00057d01
+#define CONFIG_SYS_RESET_ADDRESS	0xfc000000
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000      /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x07f00000	/* 1 - 127 MB in DRAM */
+
+#define CONFIG_BOARD_NAME		"o2dnt2"
+#define CONFIG_BOARD_BOOTCMD		"run flash_self"
+#define CONFIG_BOARD_MEM_LIMIT		xstr(126)
+#define BOARD_POST_CRC32_END		xstr(0x01000000)
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_IFM_DEFAULT_ENV_SETTINGS					\
+	CONFIG_IFM_DEFAULT_ENV_OLD					\
+	CONFIG_IFM_DEFAULT_ENV_NEW					\
+	"linbot=fc060000\0"						\
+	"lintop=fc15ffff\0"						\
+	"rambot=fc160000\0"						\
+	"ramtop=fc55ffff\0"						\
+	"jffbot=fc560000\0"						\
+	"jfftop=fce5ffff\0"						\
+	"ubobot=" xstr(CONFIG_SYS_FLASH_BASE) "\0"			\
+	"ubotop=fc03ffff\0"						\
+	"calname="CONFIG_BOARD_NAME"/uCal_"CONFIG_BOARD_NAME"_act\0"	\
+	"calbot=fce60000\0"						\
+	"caltop=fcffffff\0"						\
+	"progCal=tftp 200000 ${calname};erase ${calbot} ${caltop};"	\
+		"cp.b ${fileaddr} ${calbot} ${filesize}\0"		\
+	"kernel_addr=0xfc060000\0"					\
+	"ramdisk_addr=0xfc160000\0"					\
+	"master=mw f0000b00 0x8005A006;mw f0000b0c ${IOpin};"		\
+		"mw f0000b04 ${IOpin};mw f0000b10 0x20\0"
diff --git a/qemu/roms/u-boot/include/configs/o2i.h b/qemu/roms/u-boot/include/configs/o2i.h
new file mode 100644
index 000000000..8fe1da58b
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/o2i.h
@@ -0,0 +1,66 @@
+/*
+ * (C) Copyright 2012
+ * DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Valid values for CONFIG_SYS_TEXT_BASE are:
+ * 0xFF000000   boot low boot high (standard configuration)
+ * 0x00100000   boot from RAM (for testing only)
+ */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xff000000	/* Standard: boot low */
+#endif
+
+/* Board specific flash config */
+#define CONFIG_SYS_FLASH_BASE		0xff000000
+#define CONFIG_SYS_FLASH_SIZE		0x01000000      /* maximum 16MB */
+/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_SECT	128
+
+/*
+ * Include common defines for all ifm boards
+ */
+#include "o2dnt-common.h"
+
+/* GPIO configuration */
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x00002006	/* no CAN */
+
+/* Other board specific configs */
+#define CONFIG_SYS_BOOTCS_CFG		0x00087801
+#define CONFIG_SYS_RESET_ADDRESS	0xff000000
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000      /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x03f00000	/* 1 - 63 MB in DRAM  */
+
+#define CONFIG_BOARD_NAME		"o2i"
+#define CONFIG_BOARD_BOOTCMD		"run dhcp_boot"
+#define CONFIG_BOARD_MEM_LIMIT		xstr(62)
+#define BOARD_POST_CRC32_END		xstr(0x01000000)
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_IFM_DEFAULT_ENV_SETTINGS					\
+	CONFIG_IFM_DEFAULT_ENV_OLD					\
+	CONFIG_IFM_DEFAULT_ENV_NEW					\
+	"linbot=ff060000\0"						\
+	"lintop=ff15ffff\0"						\
+	"rambot=ff160000\0"						\
+	"ramtop=ff55ffff\0"						\
+	"jffbot=ff560000\0"						\
+	"jfftop=ffebffff\0"						\
+	"kernel_addr=0xff060000\0"					\
+	"ramdisk_addr=0xff160000\0"					\
+	"ubobot=" xstr(CONFIG_SYS_FLASH_BASE) "\0"			\
+	"ubotop=ff03ffff\0"						\
+	"autoload=no\0"							\
+	"dhcp_boot=run dhcpcmd; run flash_mtd\0"			\
+	"hostname=IFM_SENSOR\0"						\
+	"flash_mtd=run mtd_args addip addmem;bootm ${kernel_addr}\0"	\
+	"mtd_args=setenv bootargs root=/dev/mtdblock3 "			\
+		"rw rootfstype=cramfs\0"				\
+	"sensorType=O2I100AA\0"						\
+	"netretry=once\0"						\
+	"master=mw f0000b00 0x00052006;mw f0000b0c ${IOpin};"		\
+		"mw f0000b04 ${IOpin};mw f0000b10 0x20\0"
diff --git a/qemu/roms/u-boot/include/configs/o2mnt.h b/qemu/roms/u-boot/include/configs/o2mnt.h
new file mode 100644
index 000000000..c2164b5ef
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/o2mnt.h
@@ -0,0 +1,74 @@
+/*
+ * (C) Copyright 2012
+ * DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Valid values for CONFIG_SYS_TEXT_BASE are:
+ * 0xFF000000   boot low boot high (standard configuration)
+ * 0x00100000   boot from RAM (for testing only)
+ */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xff000000	/* Standard: boot low */
+#endif
+
+/* Board specific flash config */
+#define CONFIG_SYS_FLASH_BASE		0xff000000
+#define CONFIG_SYS_FLASH_SIZE		0x01000000      /* maximum 16MB */
+/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_SECT	128
+
+/*
+ * Include common defines for all ifm boards
+ */
+#include "o2dnt-common.h"
+
+/* GPIO configuration */
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x00002004	/* no CAN */
+
+/* Other board specific configs */
+#define CONFIG_NETCONSOLE
+
+#define CONFIG_SYS_BOOTCS_CFG		0x00087801
+#define CONFIG_SYS_RESET_ADDRESS	0xff000000
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000      /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x03f00000	/* 1 - 63 MB in DRAM  */
+
+#define CONFIG_BOARD_NAME		"o2mnt"
+#define CONFIG_BOARD_BOOTCMD		"${newcmd}"
+#define CONFIG_BOARD_MEM_LIMIT		xstr(62)
+#define BOARD_POST_CRC32_END		xstr(0x01000000)
+
+#ifndef CONFIG_IFM_SENSOR_TYPE
+#define CONFIG_IFM_SENSOR_TYPE		"O2M110"
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_IFM_DEFAULT_ENV_SETTINGS					\
+	CONFIG_IFM_DEFAULT_ENV_OLD					\
+	CONFIG_IFM_DEFAULT_ENV_NEW					\
+	"linbot=ff060000\0"						\
+	"lintop=ff25ffff\0"						\
+	"rambot=ff260000\0"						\
+	"ramtop=ffc5ffff\0"						\
+	"jffbot=ffc60000\0"						\
+	"jfftop=ffffffff\0"						\
+	"ubobot=" xstr(CONFIG_SYS_FLASH_BASE) "\0"			\
+	"ubotop=ff03ffff\0"						\
+	"kernel_addr=0xff060000\0"					\
+	"ramdisk_addr=0xff260000\0"					\
+	"newcmd=run scrprot;run flash_ext2\0"				\
+	"scrprot=protect on ${linbot} ${lintop};protect on ${rambot} "	\
+		"${ramtop}\0"						\
+	"flash_ext2=run ext2args addip addmem;bootm ${kernel_addr}\0"	\
+	"ext2args=setenv bootargs root=/dev/mtdblock3 ro "		\
+		"rootfstype=ext2\0"					\
+	"pwm=mw f0000674 0x10006;mw f0000678 0x30000;"			\
+		"mw f0000678 0x30001;mw f0000670 0x3\0"			\
+	"master=mw f0000b00 0x00052006;mw f0000b0c $(IOpin);"		\
+		"mw f0000b04 $(IOpin);mw f0000b10 0x24;run pwm\0"	\
+	"sensortyp="CONFIG_IFM_SENSOR_TYPE"\0"				\
+	"srelease=0.00\0"
diff --git a/qemu/roms/u-boot/include/configs/o3dnt.h b/qemu/roms/u-boot/include/configs/o3dnt.h
new file mode 100644
index 000000000..05cd36081
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/o3dnt.h
@@ -0,0 +1,70 @@
+/*
+ * (C) Copyright 2012
+ * DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Valid values for CONFIG_SYS_TEXT_BASE are:
+ * 0xFC000000   boot low boot high (standard configuration)
+ * 0x00100000   boot from RAM (for testing only)
+ */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xfc000000	/* Standard: boot low */
+#endif
+
+/* Board specific flash config */
+#define CONFIG_SYS_FLASH_BASE		0xfc000000
+#define CONFIG_SYS_FLASH_SIZE		0x04000000      /* maximum 64MB */
+/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_SECT	512
+
+/*
+ * Include common defines for all ifm boards
+ */
+#include "o2dnt-common.h"
+
+/* Additional commands */
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_REGINFO
+
+/*
+ * GPIO configuration:
+ * no CAN + no PCI
+ */
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x0000A000
+
+/* Other board specific configs */
+#define CONFIG_SYS_BOOTCS_CFG		0x00057d01
+#define CONFIG_SYS_RESET_ADDRESS	0xfc000000
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000      /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x03f00000	/* 1 - 63 MB in DRAM */
+
+#define CONFIG_BOARD_NAME		"o3dnt"
+#define CONFIG_BOARD_BOOTCMD		"run flash_self"
+#define CONFIG_BOARD_MEM_LIMIT		xstr(62)
+#define BOARD_POST_CRC32_END		xstr(0x01000000)
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_IFM_DEFAULT_ENV_SETTINGS					\
+	CONFIG_IFM_DEFAULT_ENV_OLD					\
+	CONFIG_IFM_DEFAULT_ENV_NEW					\
+	"linbot=fc060000\0"						\
+	"lintop=fc15ffff\0"						\
+	"rambot=fc160000\0"						\
+	"ramtop=fc55ffff\0"						\
+	"jffbot=fc560000\0"						\
+	"jfftop=fce5ffff\0"						\
+	"ubobot=" xstr(CONFIG_SYS_FLASH_BASE) "\0"			\
+	"ubotop=fc03ffff\0"						\
+	"calname="CONFIG_BOARD_NAME"/uCal_"CONFIG_BOARD_NAME"_act\0"	\
+	"calbot=fce60000\0"						\
+	"caltop=fcffffff\0"						\
+	"progCal=tftp 200000 ${calname};erase ${calbot} ${caltop};"	\
+		"cp.b ${fileaddr} ${calbot} ${filesize}\0"		\
+	"kernel_addr=0xfc060000\0"					\
+	"ramdisk_addr=0xfc160000\0"					\
+	"master=mw f0000b00 0x0005A006;mw f0000b0c ${IOpin};"		\
+		"mw f0000b04 ${IOpin};mw f0000b10 0x20\0"
diff --git a/qemu/roms/u-boot/include/configs/ocotea.h b/qemu/roms/u-boot/include/configs/ocotea.h
new file mode 100644
index 000000000..4ff2f05c8
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/ocotea.h
@@ -0,0 +1,194 @@
+/*
+ * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
+ *
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/************************************************************************
+ * 1 March 2004	 Travis B. Sawyer <tsawyer@sandburst.com>
+ * Adapted to current Das U-Boot source
+ ***********************************************************************/
+
+
+/************************************************************************
+ * OCOTEA.h - configuration for AMCC 440GX Ref (Ocotea)
+ ***********************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_OCOTEA		1	    /* Board is ebony		*/
+#define CONFIG_440GX		1	    /* Specifc GX support	*/
+#define CONFIG_440		1	    /* ... PPC440 family	*/
+#define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_pre_init	*/
+#define CONFIG_SYS_CLK_FREQ	33333333    /* external freq to pll	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
+
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME		ocotea
+#include "amcc-common.h"
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_FLASH_BASE	    0xff800000	    /* start of FLASH		*/
+#define CONFIG_SYS_PCI_MEMBASE	    0x80000000	    /* mapped pci memory	*/
+#define CONFIG_SYS_ISRAM_BASE	    0xc0000000	    /* internal SRAM		*/
+#define CONFIG_SYS_PCI_BASE	    0xd0000000	    /* internal PCI regs	*/
+
+#define CONFIG_SYS_FPGA_BASE	    (CONFIG_SYS_PERIPHERAL_BASE + 0x08300000)
+#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in internal SRAM)
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_TEMP_STACK_OCM  1
+#define CONFIG_SYS_OCM_DATA_ADDR   CONFIG_SYS_ISRAM_BASE
+#define CONFIG_SYS_INIT_RAM_ADDR   CONFIG_SYS_ISRAM_BASE  /* Initial RAM address	*/
+#define CONFIG_SYS_INIT_RAM_SIZE    0x2000	    /* Size of used area in RAM	*/
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#define CONFIG_SYS_EXT_SERIAL_CLOCK	(1843200 * 6)	/* Ext clk @ 11.059 MHz */
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+/*
+ * Define here the location of the environment variables (FLASH or NVRAM).
+ * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
+ *       supported for backward compatibility.
+ */
+#if 1
+#define CONFIG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
+#else
+#define CONFIG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
+#endif
+
+
+/*-----------------------------------------------------------------------
+ * NVRAM/RTC
+ *
+ * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
+ * The DS1743 code assumes this condition (i.e. -- it assumes the base
+ * address for the RTC registers is:
+ *
+ *	CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE
+ *
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_NVRAM_SIZE	    (0x2000 - 8)    /* NVRAM size(8k)- RTC regs */
+#define CONFIG_RTC_DS174x	1		    /* DS1743 RTC		*/
+
+#ifdef CONFIG_ENV_IS_IN_NVRAM
+#define CONFIG_ENV_SIZE		0x1000	    /* Size of Environment vars */
+#define CONFIG_ENV_ADDR		\
+	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE)
+#endif /* CONFIG_ENV_IS_IN_NVRAM */
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	3		    /* number of banks	    */
+#define CONFIG_SYS_MAX_FLASH_SECT	64		    /* sectors per device   */
+
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CONFIG_SYS_FLASH_ADDR0         0x5555
+#define CONFIG_SYS_FLASH_ADDR1         0x2aaa
+#define CONFIG_SYS_FLASH_WORD_SIZE     unsigned char
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	0x10000		/* size of one complete sector	*/
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
+#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+#endif /* CONFIG_ENV_IS_IN_FLASH */
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CONFIG_SPD_EEPROM	1	/* Use SPD EEPROM for setup	*/
+#define SPD_EEPROM_ADDRESS {0x53,0x52}	/* SPD i2c spd addresses	*/
+#define CONFIG_PROG_SDRAM_TLB	1	/* setup SDRAM TLB's dynamically*/
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
+
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR	(0xa8>>1)
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+/*
+ * Default environment variables
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_AMCC_DEF_ENV						\
+	CONFIG_AMCC_DEF_ENV_PPC						\
+	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
+	"kernel_addr=fff00000\0"					\
+	"ramdisk_addr=fff10000\0"					\
+	""
+
+#define CONFIG_PHY_ADDR		1	/* PHY address, See schematics	*/
+#define CONFIG_PHY1_ADDR	2
+#define CONFIG_PHY2_ADDR	0x10
+#define CONFIG_PHY3_ADDR	0x18
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+#define CONFIG_HAS_ETH3
+#define CONFIG_CIS8201_PHY	1	/* Enable 'special' RGMII mode for Cicada phy */
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+#define CONFIG_PHY_RESET        1       /* reset phy upon startup         */
+#define CONFIG_PHY_RESET_DELAY	1000
+
+/*
+ * Commands additional to the ones defined in amcc-common.h
+ */
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+/* General PCI */
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
+#define CONFIG_SYS_PCI_TARGBASE    0x80000000	/* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
+
+/* Board-specific PCI */
+#define CONFIG_SYS_PCI_TARGET_INIT		/* let board init pci target    */
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/omap1510.h b/qemu/roms/u-boot/include/configs/omap1510.h
new file mode 100644
index 000000000..41f7973f2
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/omap1510.h
@@ -0,0 +1,772 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *   OMAP hardware map
+ *
+ * Copyright (C) 2001 RidgeRun, Inc. (http://www.ridgerun.com)
+ * Author: RidgeRun, Inc.
+ *	   Greg Lonnon (glonnon@ridgerun.com) or info@ridgerun.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/sizes.h>
+
+/*
+  There are 2 sets of general I/O -->
+  1. GPIO (shared between ARM & DSP, configured by ARM)
+  2. MPUIO which can be used only by the ARM.
+
+  Base address FFFB:5000 is where the ARM accesses the MPUIO control registers
+  (see 7.2.2 of the TRM for MPUIO reg definitions).
+
+  Base address E101:5000 is reserved for ARM access of the same MPUIO control
+  regs, but via the DSP I/O map.  This address is unavailable on 1510.
+
+  Base address FFFC:E000 is where the ARM accesses the GPIO config registers
+  directly via its own peripheral bus.
+
+  Base address E101:E000 is where the ARM can access the same GPIO config
+  registers, but the access takes place through the ARM port interface (called
+  API or MPUI) via the DSP's peripheral bus (DSP I/O space).
+
+  Therefore, the ARM should setup the GPIO regs thru the FFFC:E000 addresses
+  instead of the E101:E000 addresses.  The DSP has only read access of the pin
+  control register, so this may explain the inability to write to E101:E018.
+  Try accessing pin control reg at FFFC:E018.
+ */
+#define OMAP1510_GPIO_BASE	 0xfffce000
+#define OMAP1510_GPIO_START	 OMAP1510_GPIO_BASE
+#define OMAP1510_GPIO_SIZE	 SZ_4K
+
+#define OMAP1510_MCBSP1_BASE	 0xE1011000
+#define OMAP1510_MCBSP1_SIZE	 SZ_4K
+#define OMAP1510_MCBSP1_START	 0xE1011000
+
+#define OMAP1510_MCBSP2_BASE	 0xFFFB1000
+
+#define OMAP1510_MCBSP3_BASE	 0xE1017000
+#define OMAP1510_MCBSP3_SIZE	 SZ_4K
+#define OMAP1510_MCBSP3_START	 0xE1017000
+
+/*
+ * Where's the flush address (for flushing D and I cache?)
+ */
+#define FLUSH_BASE		0xdf000000
+#define FLUSH_BASE_PHYS 0x00000000
+
+#ifndef __ASSEMBLER__
+
+#define PCIO_BASE		0
+
+/*
+ * RAM definitions
+ */
+#define MAPTOPHYS(a)		((unsigned long)(a) - PAGE_OFFSET)
+#define KERNTOPHYS(a)		((unsigned long)(&a))
+#define KERNEL_BASE		(0x10008000)
+#endif
+
+/* macro to get at IO space when running virtually */
+#define IO_ADDRESS(x) ((x))
+
+/* ----------------------------------------------------------------------------
+ *  OMAP1510 system registers
+ * ----------------------------------------------------------------------------
+ */
+
+#define OMAP1510_UART1_BASE	    0xfffb0000	 /* "BLUETOOTH-UART" */
+#define OMAP1510_UART2_BASE	    0xfffb0800	 /* "MODEM-UART" */
+#define OMAP1510_RTC_BASE	    0xfffb4800	 /* RTC */
+#define OMAP1510_UART3_BASE	    0xfffb9800	 /* Shared MPU/DSP UART */
+#define OMAP1510_COM_MCBSP2_BASE    0xffff1000	 /* Com McBSP2 */
+#define OMAP1510_AUDIO_MCBSP_BASE   0xffff1800	 /* Audio McBSP2 */
+#define OMAP1510_ARMIO_BASE	    0xfffb5000	 /* keyboard/gpio */
+
+/*
+ * OMAP1510 UART3 Registers
+ */
+
+#define OMAP_MPU_UART3_BASE  0xFFFB9800 /* UART3 through MPU bus */
+
+/* UART3 Registers Maping through MPU bus */
+
+#define UART3_RHR	 (OMAP_MPU_UART3_BASE + 0)
+#define UART3_THR	 (OMAP_MPU_UART3_BASE + 0)
+#define UART3_DLL	 (OMAP_MPU_UART3_BASE + 0)
+#define UART3_IER	 (OMAP_MPU_UART3_BASE + 4)
+#define UART3_DLH	 (OMAP_MPU_UART3_BASE + 4)
+#define UART3_IIR	 (OMAP_MPU_UART3_BASE + 8)
+#define UART3_FCR	 (OMAP_MPU_UART3_BASE + 8)
+#define UART3_EFR	 (OMAP_MPU_UART3_BASE + 8)
+#define UART3_LCR	 (OMAP_MPU_UART3_BASE + 0x0C)
+#define UART3_MCR	 (OMAP_MPU_UART3_BASE + 0x10)
+#define UART3_XON1_ADDR1 (OMAP_MPU_UART3_BASE + 0x10)
+#define UART3_XON2_ADDR2 (OMAP_MPU_UART3_BASE + 0x14)
+#define UART3_LSR	 (OMAP_MPU_UART3_BASE + 0x14)
+#define UART3_TCR	 (OMAP_MPU_UART3_BASE + 0x18)
+#define UART3_MSR	 (OMAP_MPU_UART3_BASE + 0x18)
+#define UART3_XOFF1	 (OMAP_MPU_UART3_BASE + 0x18)
+#define UART3_XOFF2	 (OMAP_MPU_UART3_BASE + 0x1C)
+#define UART3_SPR	 (OMAP_MPU_UART3_BASE + 0x1C)
+#define UART3_TLR	 (OMAP_MPU_UART3_BASE + 0x1C)
+#define UART3_MDR1	 (OMAP_MPU_UART3_BASE + 0x20)
+#define UART3_MDR2	 (OMAP_MPU_UART3_BASE + 0x24)
+#define UART3_SFLSR	 (OMAP_MPU_UART3_BASE + 0x28)
+#define UART3_TXFLL	 (OMAP_MPU_UART3_BASE + 0x28)
+#define UART3_RESUME	 (OMAP_MPU_UART3_BASE + 0x2C)
+#define UART3_TXFLH	 (OMAP_MPU_UART3_BASE + 0x2C)
+#define UART3_SFREGL	 (OMAP_MPU_UART3_BASE + 0x30)
+#define UART3_RXFLL	 (OMAP_MPU_UART3_BASE + 0x30)
+#define UART3_SFREGH	 (OMAP_MPU_UART3_BASE + 0x34)
+#define UART3_RXFLH	 (OMAP_MPU_UART3_BASE + 0x34)
+#define UART3_BLR	 (OMAP_MPU_UART3_BASE + 0x38)
+#define UART3_ACREG	 (OMAP_MPU_UART3_BASE + 0x3C)
+#define UART3_DIV16	 (OMAP_MPU_UART3_BASE + 0x3C)
+#define UART3_SCR	 (OMAP_MPU_UART3_BASE + 0x40)
+#define UART3_SSR	 (OMAP_MPU_UART3_BASE + 0x44)
+#define UART3_EBLR	 (OMAP_MPU_UART3_BASE + 0x48)
+#define UART3_OSC_12M_SEL (OMAP_MPU_UART3_BASE + 0x4C)
+#define UART3_MVR	 (OMAP_MPU_UART3_BASE + 0x50)
+
+/*
+ * Configuration Registers
+ */
+#define FUNC_MUX_CTRL_0		0xfffe1000
+#define FUNC_MUX_CTRL_1		0xfffe1004
+#define FUNC_MUX_CTRL_2		0xfffe1008
+#define COMP_MODE_CTRL_0	0xfffe100c
+#define FUNC_MUX_CTRL_3		0xfffe1010
+#define FUNC_MUX_CTRL_4		0xfffe1014
+#define FUNC_MUX_CTRL_5		0xfffe1018
+#define FUNC_MUX_CTRL_6		0xfffe101C
+#define FUNC_MUX_CTRL_7		0xfffe1020
+#define FUNC_MUX_CTRL_8		0xfffe1024
+#define FUNC_MUX_CTRL_9		0xfffe1028
+#define FUNC_MUX_CTRL_A		0xfffe102C
+#define FUNC_MUX_CTRL_B		0xfffe1030
+#define FUNC_MUX_CTRL_C		0xfffe1034
+#define FUNC_MUX_CTRL_D		0xfffe1038
+#define PULL_DWN_CTRL_0		0xfffe1040
+#define PULL_DWN_CTRL_1		0xfffe1044
+#define PULL_DWN_CTRL_2		0xfffe1048
+#define PULL_DWN_CTRL_3		0xfffe104c
+#define GATE_INH_CTRL_0		0xfffe1050
+#define VOLTAGE_CTRL_0		0xfffe1060
+#define TEST_DBG_CTRL_0		0xfffe1070
+
+#define MOD_CONF_CTRL_0		0xfffe1080
+
+#ifdef CONFIG_OMAP1610 /* 1610 Configuration Register */
+
+#define USB_OTG_CTRL			0xFFFB040C
+#define USB_TRANSCEIVER_CTRL	0xFFFE1064
+#define PULL_DWN_CTRL_4 0xFFFE10AC
+#define PU_PD_SEL_0		0xFFFE10B4
+#define PU_PD_SEL_1		0xFFFE10B8
+#define PU_PD_SEL_2		0xFFFE10BC
+#define PU_PD_SEL_3		0xFFFE10C0
+#define PU_PD_SEL_4		0xFFFE10C4
+
+#endif
+/*
+ * Traffic Controller Memory Interface Registers
+ */
+#define TCMIF_BASE		0xfffecc00
+#define IMIF_PRIO		(TCMIF_BASE + 0x00)
+#define EMIFS_PRIO_REG		(TCMIF_BASE + 0x04)
+#define EMIFF_PRIO_REG		(TCMIF_BASE + 0x08)
+#define EMIFS_CONFIG_REG	(TCMIF_BASE + 0x0c)
+#define EMIFS_CS0_CONFIG	(TCMIF_BASE + 0x10)
+#define EMIFS_CS1_CONFIG	(TCMIF_BASE + 0x14)
+#define EMIFS_CS2_CONFIG	(TCMIF_BASE + 0x18)
+#define EMIFS_CS3_CONFIG	(TCMIF_BASE + 0x1c)
+#define EMIFF_SDRAM_CONFIG	(TCMIF_BASE + 0x20)
+#define EMIFF_MRS		(TCMIF_BASE + 0x24)
+#define TC_TIMEOUT1		(TCMIF_BASE + 0x28)
+#define TC_TIMEOUT2		(TCMIF_BASE + 0x2c)
+#define TC_TIMEOUT3		(TCMIF_BASE + 0x30)
+#define TC_ENDIANISM		(TCMIF_BASE + 0x34)
+#define EMIFF_SDRAM_CONFIG_2	(TCMIF_BASE + 0x3c)
+#define EMIF_CFG_DYNAMIC_WS	(TCMIF_BASE + 0x40)
+
+/*
+ * LCD Panel
+ */
+#define TI925_LCD_BASE		0xFFFEC000
+#define TI925_LCD_CONTROL	(TI925_LCD_BASE)
+#define TI925_LCD_TIMING0	(TI925_LCD_BASE+0x4)
+#define TI925_LCD_TIMING1	(TI925_LCD_BASE+0x8)
+#define TI925_LCD_TIMING2	(TI925_LCD_BASE+0xc)
+#define TI925_LCD_STATUS	(TI925_LCD_BASE+0x10)
+#define TI925_LCD_SUBPANEL	(TI925_LCD_BASE+0x14)
+
+#define OMAP_LCD_CONTROL	TI925_LCD_CONTROL
+
+/* I2C Registers */
+
+#define I2C_BASE		0xfffb3800
+
+#define I2C_REV			(I2C_BASE + 0x00)
+#define I2C_IE			(I2C_BASE + 0x04)
+#define I2C_STAT		(I2C_BASE + 0x08)
+#define I2C_IV			(I2C_BASE + 0x0c)
+#define I2C_BUF			(I2C_BASE + 0x14)
+#define I2C_CNT			(I2C_BASE + 0x18)
+#define I2C_DATA		(I2C_BASE + 0x1c)
+#define I2C_CON			(I2C_BASE + 0x24)
+#define I2C_OA			(I2C_BASE + 0x28)
+#define I2C_SA			(I2C_BASE + 0x2c)
+#define I2C_PSC			(I2C_BASE + 0x30)
+#define I2C_SCLL		(I2C_BASE + 0x34)
+#define I2C_SCLH		(I2C_BASE + 0x38)
+#define I2C_SYSTEST		(I2C_BASE + 0x3c)
+
+/* I2C masks */
+
+/* I2C Interrupt Enable Register (I2C_IE): */
+
+#define I2C_IE_XRDY_IE	(1 << 4)	/* Transmit data ready interrupt enable */
+#define I2C_IE_RRDY_IE	(1 << 3)	/* Receive data ready interrupt enable */
+#define I2C_IE_ARDY_IE	(1 << 2)	/* Register access ready interrupt enable */
+#define I2C_IE_NACK_IE	(1 << 1)	/* No acknowledgment interrupt enable */
+#define I2C_IE_AL_IE	(1 << 0)	/* Arbitration lost interrupt enable */
+
+/* I2C Status Register (I2C_STAT): */
+
+#define I2C_STAT_SBD	(1 << 15)	/* Single byte data */
+#define I2C_STAT_BB	(1 << 12)	/* Bus busy */
+#define I2C_STAT_ROVR	(1 << 11)	/* Receive overrun */
+#define I2C_STAT_XUDF	(1 << 10)	/* Transmit underflow */
+#define I2C_STAT_AAS	(1 << 9)	/* Address as slave */
+#define I2C_STAT_AD0	(1 << 8)	/* Address zero */
+#define I2C_STAT_XRDY	(1 << 4)	/* Transmit data ready */
+#define I2C_STAT_RRDY	(1 << 3)	/* Receive data ready */
+#define I2C_STAT_ARDY	(1 << 2)	/* Register access ready */
+#define I2C_STAT_NACK	(1 << 1)	/* No acknowledgment interrupt enable */
+#define I2C_STAT_AL	(1 << 0)	/* Arbitration lost interrupt enable */
+
+/* I2C Interrupt Vector Register (I2C_IV): */
+
+/* I2C Interrupt Code Register (I2C_INTCODE): */
+
+#define I2C_INTCODE_MASK	7
+#define I2C_INTCODE_NONE	0
+#define I2C_INTCODE_AL		1	/* Arbitration lost */
+#define I2C_INTCODE_NAK		2	/* No acknowledgement/general call */
+#define I2C_INTCODE_ARDY	3	/* Register access ready */
+#define I2C_INTCODE_RRDY	4	/* Rcv data ready */
+#define I2C_INTCODE_XRDY	5	/* Xmit data ready */
+
+/* I2C Buffer Configuration Register (I2C_BUF): */
+
+#define I2C_BUF_RDMA_EN		(1 << 15)	/* Receive DMA channel enable */
+#define I2C_BUF_XDMA_EN		(1 << 7)	/* Transmit DMA channel enable */
+
+/* I2C Configuration Register (I2C_CON): */
+
+#define I2C_CON_EN	(1 << 15)	/* I2C module enable */
+#define I2C_CON_BE	(1 << 14)	/* Big endian mode */
+#define I2C_CON_STB	(1 << 11)	/* Start byte mode (master mode only) */
+#define I2C_CON_MST	(1 << 10)	/* Master/slave mode */
+#define I2C_CON_TRX	(1 << 9)	/* Transmitter/receiver mode (master mode only) */
+#define I2C_CON_XA	(1 << 8)	/* Expand address */
+#define I2C_CON_RM	(1 << 2)	/* Repeat mode (master mode only) */
+#define I2C_CON_STP	(1 << 1)	/* Stop condition (master mode only) */
+#define I2C_CON_STT	(1 << 0)	/* Start condition (master mode only) */
+
+/* I2C System Test Register (I2C_SYSTEST): */
+
+#define I2C_SYSTEST_ST_EN	(1 << 15)	/* System test enable */
+#define I2C_SYSTEST_FREE	(1 << 14)	/* Free running mode (on breakpoint) */
+#define I2C_SYSTEST_TMODE_MASK	(3 << 12)	/* Test mode select */
+#define I2C_SYSTEST_TMODE_SHIFT (12)		/* Test mode select */
+#define I2C_SYSTEST_SCL_I	(1 << 3)	/* SCL line sense input value */
+#define I2C_SYSTEST_SCL_O	(1 << 2)	/* SCL line drive output value */
+#define I2C_SYSTEST_SDA_I	(1 << 1)	/* SDA line sense input value */
+#define I2C_SYSTEST_SDA_O	(1 << 0)	/* SDA line drive output value */
+
+/*
+ * MMC/SD Host Controller Registers
+ */
+
+#define OMAP_MMC_CMD	 0xFFFB7800 /* MMC Command */
+#define OMAP_MMC_ARGL	 0xFFFB7804 /* MMC argument low */
+#define OMAP_MMC_ARGH	 0xFFFB7808 /* MMC argument high */
+#define OMAP_MMC_CON	 0xFFFB780C /* MMC system configuration */
+#define OMAP_MMC_STAT	 0xFFFB7810 /* MMC status */
+#define OMAP_MMC_IE	 0xFFFB7814 /* MMC system interrupt enable */
+#define OMAP_MMC_CTO	 0xFFFB7818 /* MMC command time-out */
+#define OMAP_MMC_DTO	 0xFFFB781C /* MMC data time-out */
+#define OMAP_MMC_DATA	 0xFFFB7820 /* MMC TX/RX FIFO data */
+#define OMAP_MMC_BLEN	 0xFFFB7824 /* MMC block length */
+#define OMAP_MMC_NBLK	 0xFFFB7828 /* MMC number of blocks */
+#define OMAP_MMC_BUF	 0xFFFB782C /* MMC buffer configuration */
+#define OMAP_MMC_SPI	 0xFFFB7830 /* MMC serial port interface */
+#define OMAP_MMC_SDIO	 0xFFFB7834 /* MMC SDIO mode configuration */
+#define OMAP_MMC_SYST	 0xFFFB7838 /* MMC system test */
+#define OMAP_MMC_REV	 0xFFFB783C /* MMC module version */
+#define OMAP_MMC_RSP0	 0xFFFB7840 /* MMC command response 0 */
+#define OMAP_MMC_RSP1	 0xFFFB7844 /* MMC command response 1 */
+#define OMAP_MMC_RSP2	 0xFFFB7848 /* MMC command response 2 */
+#define OMAP_MMC_RSP3	 0xFFFB784C /* MMC command response 3 */
+#define OMAP_MMC_RSP4	 0xFFFB7850 /* MMC command response 4 */
+#define OMAP_MMC_RSP5	 0xFFFB7854 /* MMC command response 5 */
+#define OMAP_MMC_RSP6	 0xFFFB7858 /* MMC command response 6 */
+#define OMAP_MMC_RSP7	 0xFFFB785C /* MMC command response 4 */
+
+/* MMC masks */
+
+#define OMAP_MMC_END_OF_CMD	(1 << 0)	/* End of command phase */
+#define OMAP_MMC_CARD_BUSY	(1 << 2)	/* Card enter busy state */
+#define OMAP_MMC_BLOCK_RS	(1 << 3)	/* Block received/sent */
+#define OMAP_MMC_EOF_BUSY	(1 << 4)	/* Card exit busy state */
+#define OMAP_MMC_DATA_TIMEOUT	(1 << 5)	/* Data response time-out */
+#define OMAP_MMC_DATA_CRC	(1 << 6)	/* Date CRC error */
+#define OMAP_MMC_CMD_TIMEOUT	(1 << 7)	/* Command response time-out */
+#define OMAP_MMC_CMD_CRC	(1 << 8)	/* Command CRC error */
+#define OMAP_MMC_A_FULL		(1 << 10)	/* Buffer almost full */
+#define OMAP_MMC_A_EMPTY	(1 << 11)	/* Buffer almost empty */
+#define OMAP_MMC_OCR_BUSY	(1 << 12)	/* OCR busy */
+#define OMAP_MMC_CARD_IRQ	(1 << 13)	/* Card IRQ received */
+#define OMAP_MMC_CARD_ERR	(1 << 14)	/* Card status error in response */
+
+/* 2.9.2 MPUI Interface Registers FFFE:C900 */
+
+#define MPUI_CTRL_REG		(volatile __u32 *)(0xfffec900)
+#define MPUI_DEBUG_ADDR		(volatile __u32 *)(0xfffec904)
+#define MPUI_DEBUG_DATA		(volatile __u32 *)(0xfffec908)
+#define MPUI_DEBUG_FLAG		(volatile __u16 *)(0xfffec90c)
+#define MPUI_STATUS_REG		(volatile __u16 *)(0xfffec910)
+#define MPUI_DSP_STATUS_REG	(volatile __u16 *)(0xfffec914)
+#define MPUI_DSP_BOOT_CONFIG	(volatile __u16 *)(0xfffec918)
+#define MPUI_DSP_API_CONFIG	(volatile __u16 *)(0xfffec91c)
+
+/* 2.9.6 Traffic Controller Memory Interface Registers: */
+#define OMAP_IMIF_PRIO_REG		0xfffecc00
+#define OMAP_EMIFS_PRIO_REG		0xfffecc04
+#define OMAP_EMIFF_PRIO_REG		0xfffecc08
+#define OMAP_EMIFS_CONFIG_REG		0xfffecc0c
+#define OMAP_EMIFS_CS0_CONFIG		0xfffecc10
+#define OMAP_EMIFS_CS1_CONFIG		0xfffecc14
+#define OMAP_EMIFS_CS2_CONFIG		0xfffecc18
+#define OMAP_EMIFS_CS3_CONFIG		0xfffecc1c
+#define OMAP_EMIFF_SDRAM_CONFIG		0xfffecc20
+#define OMAP_EMIFF_MRS			0xfffecc24
+#define OMAP_TIMEOUT1			0xfffecc28
+#define OMAP_TIMEOUT2			0xfffecc2c
+#define OMAP_TIMEOUT3			0xfffecc30
+#define OMAP_ENDIANISM			0xfffecc34
+
+/* 2.9.10 EMIF Slow Interface Configuration Register (EMIFS_CONFIG_REG): */
+#define OMAP_EMIFS_CONFIG_FR		(1 << 4)
+#define OMAP_EMIFS_CONFIG_PDE		(1 << 3)
+#define OMAP_EMIFS_CONFIG_PWD_EN	(1 << 2)
+#define OMAP_EMIFS_CONFIG_BM		(1 << 1)
+#define OMAP_EMIFS_CONFIG_WP		(1 << 0)
+
+/*
+ * Memory chunk set aside for the Framebuffer in SRAM
+ */
+#define SRAM_FRAMEBUFFER_MEMORY OMAP1510_SRAM_BASE
+
+
+/*
+ * DMA
+ */
+
+#define OMAP1510_DMA_BASE 0xFFFED800
+#define OMAP_DMA_BASE	  OMAP1510_DMA_BASE
+
+/* Global Register selection */
+#define NO_GLOBAL_DMA_ACCESS 0
+
+/* Channel select field
+ * NOTE: all other channels are linear, chan0 is 0, chan1 is 1, etc...
+ */
+#define LCD_CHANNEL 0xc
+
+/* Register Select Field (LCD) */
+#define DMA_LCD_CTRL		0
+#define DMA_LCD_TOP_F1_L	1
+#define DMA_LCD_TOP_F1_U	2
+#define DMA_LCD_BOT_F1_L	3
+#define DMA_LCD_BOT_F1_U	4
+
+#define LCD_FRAME_MODE		(1<<0)
+#define LCD_FRAME_IT_IE		(1<<1)
+#define LCD_BUS_ERROR_IT_IE	(1<<2)
+#define LCD_FRAME_1_IT_COND	(1<<3)
+#define LCD_FRAME_2_IT_COND	(1<<4)
+#define LCD_BUS_ERROR_IT_COND	(1<<5)
+#define LCD_SOURCE_IMIF		(1<<6)
+
+/*
+ * Real-Time Clock
+ */
+
+#define RTC_SECONDS		(volatile __u8 *)(OMAP1510_RTC_BASE + 0x00)
+#define RTC_MINUTES		(volatile __u8 *)(OMAP1510_RTC_BASE + 0x04)
+#define RTC_HOURS		(volatile __u8 *)(OMAP1510_RTC_BASE + 0x08)
+#define RTC_DAYS		(volatile __u8 *)(OMAP1510_RTC_BASE + 0x0C)
+#define RTC_MONTHS		(volatile __u8 *)(OMAP1510_RTC_BASE + 0x10)
+#define RTC_YEARS		(volatile __u8 *)(OMAP1510_RTC_BASE + 0x14)
+#define RTC_CTRL		(volatile __u8 *)(OMAP1510_RTC_BASE + 0x40)
+
+
+/* ---------------------------------------------------------------------------
+ *  OMAP1510 Interrupt Handlers
+ * ---------------------------------------------------------------------------
+ *
+ */
+#define OMAP_IH1_BASE		0xfffecb00
+#define OMAP_IH2_BASE		0xfffe0000
+#define OMAP1510_ITR		0x0
+#define OMAP1510_MASK		0x4
+
+#define INTERRUPT_HANDLER_BASE	 OMAP_IH1_BASE
+#define INTERRUPT_INPUT_REGISTER OMAP1510_ITR
+#define INTERRUPT_MASK_REGISTER	 OMAP1510_MASK
+
+
+/* ---------------------------------------------------------------------------
+ *  OMAP1510 TIMERS
+ * ---------------------------------------------------------------------------
+ *
+ */
+
+#define OMAP1510_32kHz_TIMER_BASE 0xfffb9000
+
+/* 32k Timer Registers */
+#define TIMER32k_CR	0x08
+#define TIMER32k_TVR	0x00
+#define TIMER32k_TCR	0x04
+
+/* 32k Timer Control Register definition */
+#define TIMER32k_TSS	(1<<0)
+#define TIMER32k_TRB	(1<<1)
+#define TIMER32k_INT	(1<<2)
+#define TIMER32k_ARL	(1<<3)
+
+/* MPU Timer base addresses  */
+#define OMAP1510_MPUTIMER_BASE	0xfffec500
+#define OMAP1510_MPUTIMER_OFF	0x00000100
+
+#define OMAP1510_TIMER1_BASE	0xfffec500
+#define OMAP1510_TIMER2_BASE	0xfffec600
+#define OMAP1510_TIMER3_BASE	0xfffec700
+
+/* MPU Timer Registers */
+#define CNTL_TIMER	0
+#define LOAD_TIM	4
+#define READ_TIM	8
+
+/*  CNTL_TIMER register bits */
+#define MPUTIM_FREE		(1<<6)
+#define MPUTIM_CLOCK_ENABLE	(1<<5)
+#define MPUTIM_PTV_MASK		(0x7<<MPUTIM_PTV_BIT)
+#define MPUTIM_PTV_BIT		2
+#define MPUTIM_AR		(1<<1)
+#define MPUTIM_ST		(1<<0)
+
+/* ---------------------------------------------------------------------------
+ *  OMAP1510 GPIO (SHARED)
+ * ---------------------------------------------------------------------------
+ *
+ */
+#define GPIO_DATA_INPUT_REG	(OMAP1510_GPIO_BASE + 0x0)
+#define GPIO_DATA_OUTPUT_REG	(OMAP1510_GPIO_BASE + 0x4)
+#define GPIO_DIR_CONTROL_REG	(OMAP1510_GPIO_BASE + 0x8)
+#define GPIO_INT_CONTROL_REG	(OMAP1510_GPIO_BASE + 0xc)
+#define GPIO_INT_MASK_REG	(OMAP1510_GPIO_BASE + 0x10)
+#define GPIO_INT_STATUS_REG	(OMAP1510_GPIO_BASE + 0x14)
+#define GPIO_PIN_CONTROL_REG	(OMAP1510_GPIO_BASE + 0x18)
+
+
+/* ---------------------------
+ * OMAP1510 MPUIO (ARM only)
+ *----------------------------
+ */
+#define OMAP1510_MPUIO_BASE	0xFFFB5000
+#define MPUIO_DATA_INPUT_REG	(OMAP1510_MPUIO_BASE + 0x0)
+#define MPUIO_DATA_OUTPUT_REG	(OMAP1510_MPUIO_BASE + 0x4)
+#define MPUIO_DIR_CONTROL_REG	(OMAP1510_MPUIO_BASE + 0x8)
+
+/* ---------------------------------------------------------------------------
+ *  OMAP1510 TIPB (only)
+ * ---------------------------------------------------------------------------
+ *
+ */
+#define TIPB_PUBLIC_CNTL_BASE		0xfffed300
+#define MPU_PUBLIC_TIPB_CNTL_REG	(TIPB_PUBLIC_CNTL_BASE + 0x8)
+#define TIPB_PRIVATE_CNTL_BASE		0xfffeca00
+#define MPU_PRIVATE_TIPB_CNTL_REG	(TIPB_PRIVATE_CNTL_BASE + 0x8)
+
+/*
+ * ---------------------------------------------------------------------------
+ *  OMAP1510 Camera Interface
+ * ---------------------------------------------------------------------------
+ */
+#define CAMERA_BASE		(IO_BASE + 0x6800)
+#define CAM_CTRLCLOCK_REG	(CAMERA_BASE + 0x00)
+#define CAM_IT_STATUS_REG	(CAMERA_BASE + 0x04)
+#define CAM_MODE_REG		(CAMERA_BASE + 0x08)
+#define CAM_STATUS_REG		(CAMERA_BASE + 0x0C)
+#define CAM_CAMDATA_REG		(CAMERA_BASE + 0x10)
+#define CAM_GPIO_REG		(CAMERA_BASE + 0x14)
+#define CAM_PEAK_CTR_REG	(CAMERA_BASE + 0x18)
+
+#if 0
+#ifndef __ASSEMBLY__
+typedef struct {
+	__u32 ctrlclock;
+	__u32 it_status;
+	__u32 mode;
+	__u32 status;
+	__u32 camdata;
+	__u32 gpio;
+	__u32 peak_counter;
+} camera_regs_t;
+#endif
+#endif
+
+/* CTRLCLOCK bit shifts */
+#define FOSCMOD_BIT	0
+#define FOSCMOD_MASK	(0x7 << FOSCMOD_BIT)
+#define	 FOSCMOD_12MHz	0x0
+#define	 FOSCMOD_6MHz	0x2
+#define	 FOSCMOD_9_6MHz 0x4
+#define	 FOSCMOD_24MHz	0x5
+#define	 FOSCMOD_8MHz	0x6
+#define POLCLK		(1<<3)
+#define CAMEXCLK_EN	(1<<4)
+#define MCLK_EN		(1<<5)
+#define DPLL_EN		(1<<6)
+#define LCLK_EN		(1<<7)
+
+/* IT_STATUS bit shifts */
+#define V_UP		(1<<0)
+#define V_DOWN		(1<<1)
+#define H_UP		(1<<2)
+#define H_DOWN		(1<<3)
+#define FIFO_FULL	(1<<4)
+#define DATA_XFER	(1<<5)
+
+/* MODE bit shifts */
+#define CAMOSC		(1<<0)
+#define IMGSIZE_BIT	1
+#define IMGSIZE_MASK	(0x3 << IMGSIZE_BIT)
+#define	 IMGSIZE_CIF	(0x0 << IMGSIZE_BIT)	/* 352x288 */
+#define	 IMGSIZE_QCIF	(0x1 << IMGSIZE_BIT)	/* 176x144 */
+#define	 IMGSIZE_VGA	(0x2 << IMGSIZE_BIT)	/* 640x480 */
+#define	 IMGSIZE_QVGA	(0x3 << IMGSIZE_BIT)	/* 320x240 */
+#define ORDERCAMD	(1<<3)
+#define EN_V_UP		(1<<4)
+#define EN_V_DOWN	(1<<5)
+#define EN_H_UP		(1<<6)
+#define EN_H_DOWN	(1<<7)
+#define EN_DMA		(1<<8)
+#define THRESHOLD	(1<<9)
+#define THRESHOLD_BIT	9
+#define THRESHOLD_MASK	(0x7f<<9)
+#define EN_NIRQ		(1<<16)
+#define EN_FIFO_FULL	(1<<17)
+#define RAZ_FIFO	(1<<18)
+
+/* STATUS bit shifts */
+#define VSTATUS		(1<<0)
+#define HSTATUS		(1<<1)
+
+/* GPIO bit shifts */
+#define CAM_RST		(1<<0)
+
+
+/*********************
+ * Watchdog timer.
+ *********************/
+#define WDTIM_BASE	0xfffec800
+#define WDTIM_CONTROL	(WDTIM_BASE+0x00)
+#define WDTIM_LOAD	(WDTIM_BASE+0x04)
+#define WDTIM_READ	(WDTIM_BASE+0x04)
+#define WDTIM_MODE	(WDTIM_BASE+0x08)
+
+/* Values to write to mode register to disable the watchdog function. */
+#define DISABLE_SEQ1	0xF5
+#define DISABLE_SEQ2	0xA0
+
+/* WDTIM_CONTROL bit definitions. */
+#define WDTIM_CONTROL_ST	BIT7
+
+
+/* ---------------------------------------------------------------------------
+ *  Differentiating processor versions for those who care.
+ * ---------------------------------------------------------------------------
+ *
+ */
+#define OMAP1509 0
+#define OMAP1510 1
+
+#define OMAP1510_ID_CODE_REG 0xfffed404
+
+#ifndef __ASSEMBLY__
+int cpu_type(void);
+#endif
+
+/*
+ * EVM Implementation Specifics.
+ *
+ * *** NOTE ***
+ * Any definitions in these files should be prefixed by an identifier -
+ * eg. OMAP1510P1_FLASH0_BASE .
+ *
+ */
+#ifdef CONFIG_OMAP_INNOVATOR
+#include "innovator.h"
+#endif
+
+#ifdef CONFIG_OMAP_1510P1
+#include "omap1510p1.h"
+#endif
+
+/*****************************************************************************/
+
+#define CLKGEN_RESET_BASE (0xfffece00)
+#define ARM_CKCTL	(volatile __u16 *)(CLKGEN_RESET_BASE + 0x0)
+#define ARM_IDLECT1	(volatile __u16 *)(CLKGEN_RESET_BASE + 0x4)
+#define ARM_IDLECT2	(volatile __u16 *)(CLKGEN_RESET_BASE + 0x8)
+#define ARM_EWUPCT	(volatile __u16 *)(CLKGEN_RESET_BASE + 0xC)
+#define ARM_RSTCT1	(volatile __u16 *)(CLKGEN_RESET_BASE + 0x10)
+#define ARM_RSTCT2	(volatile __u16 *)(CLKGEN_RESET_BASE + 0x14)
+#define ARM_SYSST	(volatile __u16 *)(CLKGEN_RESET_BASE + 0x18)
+
+
+#define CK_CLKIN	12 /* MHz */
+#define CK_RATEF	1
+#define CK_IDLEF	2
+#define CK_ENABLEF	4
+#define CK_SELECTF	8
+#ifndef __ASSEMBLER__
+#define CK_DPLL1	((volatile __u16 *)0xfffecf00)
+#else
+#define CK_DPLL1 (0xfffecf00)
+#endif
+#define SETARM_IDLE_SHIFT
+
+/* ARM_CKCTL bit shifts */
+#define PERDIV		0
+#define LCDDIV		2
+#define ARMDIV		4
+#define DSPDIV		6
+#define TCDIV		8
+#define DSPMMUDIV	10
+#define ARM_TIMXO	12
+#define EN_DSPCK	13
+#define ARM_INTHCK_SEL	14 /* REVISIT -- where is this used? */
+
+#define ARM_CKCTL_RSRVD_BIT15		(1 << 15)
+#define ARM_CKCTL_ARM_INTHCK_SEL	(1 << 14)
+#define ARM_CKCTL_EN_DSPCK		(1 << 13)
+#define ARM_CKCTL_ARM_TIMXO		(1 << 12)
+#define ARM_CKCTL_DSPMMU_DIV1		(1 << 11)
+#define ARM_CKCTL_DSPMMU_DIV2		(1 << 10)
+#define ARM_CKCTL_TCDIV1		(1 << 9)
+#define ARM_CKCTL_TCDIV2		(1 << 8)
+#define ARM_CKCTL_DSPDIV1		(1 << 7)
+#define ARM_CKCTL_DSPDIV0		(1 << 6)
+#define ARM_CKCTL_ARMDIV1		(1 << 5)
+#define ARM_CKCTL_ARMDIV0		(1 << 4)
+#define ARM_CKCTL_LCDDIV1		(1 << 3)
+#define ARM_CKCTL_LCDDIV0		(1 << 2)
+#define ARM_CKCTL_PERDIV1		(1 << 1)
+#define ARM_CKCTL_PERDIV0		(1 << 0)
+
+/* ARM_IDLECT1 bit shifts */
+#define IDLWDT_ARM	0
+#define IDLXORP_ARM	1
+#define IDLPER_ARM	2
+#define IDLLCD_ARM	3
+#define IDLLB_ARM	4
+#define IDLHSAB_ARM	5
+#define IDLIF_ARM	6
+#define IDLDPLL_ARM	7
+#define IDLAPI_ARM	8
+#define IDLTIM_ARM	9
+#define SETARM_IDLE	11
+
+/* ARM_IDLECT2 bit shifts */
+#define EN_WDTCK	0
+#define EN_XORPCK	1
+#define EN_PERCK	2
+#define EN_LCDCK	3
+#define EN_LBCK		4
+#define EN_HSABCK	5
+#define EN_APICK	6
+#define EN_TIMCK	7
+#define DMACK_REQ	8
+#define EN_GPIOCK	9
+#define EN_LBFREECK	10
+
+#define ARM_RSTCT1_SW_RST	(1 << 3)
+#define ARM_RSTCT1_DSP_RST	(1 << 2)
+#define ARM_RSTCT1_DSP_EN	(1 << 1)
+#define ARM_RSTCT1_ARM_RST	(1 << 0)
+
+/* ARM_RSTCT2 bit shifts */
+#define EN_PER		0
+
+#define ARM_SYSST_RSRVD_BIT15	(1 << 15)
+#define ARM_SYSST_RSRVD_BIT14	(1 << 14)
+#define ARM_SYSST_CLOCK_SELECT2 (1 << 13)
+#define ARM_SYSST_CLOCK_SELECT1 (1 << 12)
+#define ARM_SYSST_CLOCK_SELECT0 (1 << 11)
+#define ARM_SYSST_RSRVD_BIT10	(1 << 10)
+#define ARM_SYSST_RSRVD_BIT9	(1 << 9)
+#define ARM_SYSST_RSRVD_BIT8	(1 << 8)
+#define ARM_SYSST_RSRVD_BIT7	(1 << 7)
+#define ARM_SYSST_IDLE_DSP	(1 << 6)
+#define ARM_SYSST_POR		(1 << 5)
+#define ARM_SYSST_EXT_RST	(1 << 4)
+#define ARM_SYSST_ARM_MCRST	(1 << 3)
+#define ARM_SYSST_ARM_WDRST	(1 << 2)
+#define ARM_SYSST_GLOB_SWRST	(1 << 1)
+#define ARM_SYSST_DSP_WDRST	(1 << 0)
+
+/* Table 15-23. DPLL Control Registers: */
+#define DPLL_CTL_REG		(volatile __u16 *)(0xfffecf00)
+
+/* Table 15-24. Control Register (CTL_REG): */
+
+#define DPLL_CTL_REG_IOB		(1 << 13)
+#define DPLL_CTL_REG_PLL_MULT		Fld(5,0)
+
+/*****************************************************************************/
+
+/* OMAP INTERRUPT REGISTERS */
+#define IRQ_ITR			0x00
+#define IRQ_MIR			0x04
+#define IRQ_SIR_IRQ		0x10
+#define IRQ_SIR_FIQ		0x14
+#define IRQ_CONTROL_REG		0x18
+#define IRQ_ISR			0x9c
+#define IRQ_ILR0		0x1c
+
+#define REG_IHL1_MIR  (OMAP_IH1_BASE+IRQ_MIR)
+#define REG_IHL2_MIR  (OMAP_IH2_BASE+IRQ_MIR)
+
+/* INTERRUPT LEVEL REGISTER BITS */
+#define ILR_PRIORITY_MASK	(0x3c)
+#define ILR_PRIORITY_SHIFT	(2)
+#define ILR_LEVEL_TRIGGER	(1<<1)
+#define ILR_FIQ			(1<<0)
+
+#define IRQ_LEVEL_INT		1
+#define IRQ_EDGE_INT		0
+
+/* Macros to access registers */
+#define outb(v,p) *(volatile u8 *) (p) = v
+#define outw(v,p) *(volatile u16 *) (p) = v
+#define outl(v,p) *(volatile u32 *) (p) = v
+
+#define inb(p)	*(volatile u8 *) (p)
+#define inw(p)	*(volatile u16 *) (p)
+#define inl(p)	*(volatile u32 *) (p)
diff --git a/qemu/roms/u-boot/include/configs/omap3_beagle.h b/qemu/roms/u-boot/include/configs/omap3_beagle.h
new file mode 100644
index 000000000..fae0e6ffc
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/omap3_beagle.h
@@ -0,0 +1,295 @@
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * Configuration settings for the TI OMAP3530 Beagle board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
+
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * other needs.  We use this rather than the inherited defines from
+ * ti_armv7_common.h for backwards compatibility.
+ */
+#define CONFIG_SYS_TEXT_BASE		0x80100000
+#define CONFIG_SPL_BSS_START_ADDR	0x80000000
+#define CONFIG_SPL_BSS_MAX_SIZE		(512 << 10)	/* 512 KB */
+#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
+
+#include <configs/ti_omap3_common.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO		1
+#define CONFIG_DISPLAY_BOARDINFO	1
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_REVISION_TAG		1
+#define CONFIG_ENV_OVERWRITE
+
+/* Status LED */
+#define CONFIG_STATUS_LED		1
+#define CONFIG_BOARD_SPECIFIC_LED	1
+#define STATUS_LED_BIT			0x01
+#define STATUS_LED_STATE		STATUS_LED_ON
+#define STATUS_LED_PERIOD		(CONFIG_SYS_HZ / 2)
+#define STATUS_LED_BIT1			0x02
+#define STATUS_LED_STATE1		STATUS_LED_ON
+#define STATUS_LED_PERIOD1		(CONFIG_SYS_HZ / 2)
+#define STATUS_LED_BOOT			STATUS_LED_BIT
+#define STATUS_LED_GREEN		STATUS_LED_BIT1
+
+/* Enable Multi Bus support for I2C */
+#define CONFIG_I2C_MULTI_BUS		1
+
+/* Probe all devices */
+#define CONFIG_SYS_I2C_NOPROBES		{{0x0, 0x0}}
+
+/* USB */
+#define CONFIG_MUSB_GADGET
+#define CONFIG_USB_MUSB_OMAP2PLUS
+#define CONFIG_MUSB_PIO_ONLY
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_TWL4030_USB		1
+#define CONFIG_USB_ETHER
+#define CONFIG_USB_ETHER_RNDIS
+
+/* USB EHCI */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+
+#define CONFIG_USB_EHCI_OMAP
+#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO	147
+
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_MCS7830
+#define CONFIG_USB_ETHER_SMSC95XX
+
+/* GPIO banks */
+#define CONFIG_OMAP3_GPIO_5		/* GPIO128..159 is in GPIO bank 5 */
+#define CONFIG_OMAP3_GPIO_6		/* GPIO160..191 is in GPIO bank 6 */
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+
+#define CONFIG_CMD_CACHE
+
+#define MTDIDS_DEFAULT			"nand0=nand"
+#define MTDPARTS_DEFAULT		"mtdparts=nand:512k(x-loader),"\
+					"1920k(u-boot),128k(u-boot-env),"\
+					"4m(kernel),-(fs)"
+
+#define CONFIG_USB_STORAGE	/* USB storage support		*/
+#define CONFIG_CMD_NAND		/* NAND support			*/
+#define CONFIG_CMD_LED		/* LED support			*/
+#define CONFIG_CMD_SETEXPR	/* Evaluate expressions		*/
+#define CONFIG_CMD_GPIO     /* Enable gpio command */
+
+#define CONFIG_VIDEO_OMAP3	/* DSS Support			*/
+
+/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_LED		1
+
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_SYS_NAND_QUIET_TEST	1
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
+							/* devices */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x80200000\0" \
+	"rdaddr=0x81000000\0" \
+	"fdt_high=0xffffffff\0" \
+	"fdtaddr=0x80f80000\0" \
+	"usbtty=cdc_acm\0" \
+	"bootfile=uImage\0" \
+	"ramdisk=ramdisk.gz\0" \
+	"bootdir=/boot\0" \
+	"bootpart=0:2\0" \
+	"console=ttyO2,115200n8\0" \
+	"mpurate=auto\0" \
+	"buddy=none\0" \
+	"optargs=\0" \
+	"camera=none\0" \
+	"vram=12M\0" \
+	"dvimode=640x480MR-16@60\0" \
+	"defaultdisplay=dvi\0" \
+	"mmcdev=0\0" \
+	"mmcroot=/dev/mmcblk0p2 rw\0" \
+	"mmcrootfstype=ext3 rootwait\0" \
+	"nandroot=ubi0:rootfs ubi.mtd=4\0" \
+	"nandrootfstype=ubifs\0" \
+	"ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=0x81000000,64M\0" \
+	"ramrootfstype=ext2\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"mpurate=${mpurate} " \
+		"buddy=${buddy} "\
+		"camera=${camera} "\
+		"vram=${vram} " \
+		"omapfb.mode=dvi:${dvimode} " \
+		"omapdss.def_disp=${defaultdisplay} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"mpurate=${mpurate} " \
+		"buddy=${buddy} "\
+		"camera=${camera} "\
+		"vram=${vram} " \
+		"omapfb.mode=dvi:${dvimode} " \
+		"omapdss.def_disp=${defaultdisplay} " \
+		"root=${nandroot} " \
+		"rootfstype=${nandrootfstype}\0" \
+	"findfdt=" \
+		"if test $beaglerev = AxBx; then " \
+			"setenv fdtfile omap3-beagle.dtb; fi; " \
+		"if test $beaglerev = Cx; then " \
+			"setenv fdtfile omap3-beagle.dtb; fi; " \
+		"if test $beaglerev = C4; then " \
+			"setenv fdtfile omap3-beagle.dtb; fi; " \
+		"if test $beaglerev = xMAB; then " \
+			"setenv fdtfile omap3-beagle-xm.dtb; fi; " \
+		"if test $beaglerev = xMC; then " \
+			"setenv fdtfile omap3-beagle-xm.dtb; fi; " \
+		"if test $fdtfile = undefined; then " \
+			"echo WARNING: Could not determine device tree to use; fi; \0" \
+	"bootenv=uEnv.txt\0" \
+	"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
+	"importbootenv=echo Importing environment from mmc ...; " \
+		"env import -t $loadaddr $filesize\0" \
+	"ramargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"mpurate=${mpurate} " \
+		"buddy=${buddy} "\
+		"vram=${vram} " \
+		"omapfb.mode=dvi:${dvimode} " \
+		"omapdss.def_disp=${defaultdisplay} " \
+		"root=${ramroot} " \
+		"rootfstype=${ramrootfstype}\0" \
+	"loadramdisk=load mmc ${bootpart} ${rdaddr} ${bootdir}/${ramdisk}\0" \
+	"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
+	"loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0" \
+	"mmcbootz=echo Booting with DT from mmc${mmcdev} ...; " \
+		"run mmcargs; " \
+		"bootz ${loadaddr} - ${fdtaddr}\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nand read ${loadaddr} 280000 400000; " \
+		"bootm ${loadaddr}\0" \
+	"ramboot=echo Booting from ramdisk ...; " \
+		"run ramargs; " \
+		"bootm ${loadaddr}\0" \
+	"userbutton=if gpio input 173; then run userbutton_xm; " \
+		"else run userbutton_nonxm; fi;\0" \
+	"userbutton_xm=gpio input 4;\0" \
+	"userbutton_nonxm=gpio input 7;\0"
+/* "run userbutton" will return 1 (false) if pressed and 0 (true) if not */
+#define CONFIG_BOOTCOMMAND \
+	"run findfdt; " \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"if run userbutton; then " \
+			"setenv bootenv uEnv.txt;" \
+		"else " \
+			"setenv bootenv user.txt;" \
+		"fi;" \
+		"echo SD/MMC found on device ${mmcdev};" \
+		"if run loadbootenv; then " \
+			"echo Loaded environment from ${bootenv};" \
+			"run importbootenv;" \
+		"fi;" \
+		"if test -n $uenvcmd; then " \
+			"echo Running uenvcmd ...;" \
+			"run uenvcmd;" \
+		"fi;" \
+		"if run loadimage; then " \
+			"run mmcboot;" \
+		"fi;" \
+	"fi;" \
+	"run nandboot;" \
+	"setenv bootfile zImage;" \
+	"if run loadimage; then " \
+		"run loadfdt;" \
+		"run mmcbootz; " \
+	"fi; " \
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+
+/* Configure the PISMO */
+#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
+#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M
+
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_SYS_FLASH_BASE		PISMO1_NAND_BASE
+#endif
+
+/* Monitor at start of flash */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
+
+#define CONFIG_ENV_IS_IN_NAND		1
+#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
+#define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
+#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
+
+#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
+#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
+#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
+
+#define CONFIG_OMAP3_SPI
+
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
+/* Defines for SPL */
+#define CONFIG_SPL_OMAP3_ID_NAND
+
+/* NAND boot config */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
+#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9,\
+						10, 11, 12, 13}
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/omap3_evm.h b/qemu/roms/u-boot/include/configs/omap3_evm.h
new file mode 100644
index 000000000..b7638fb8a
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/omap3_evm.h
@@ -0,0 +1,161 @@
+/*
+ * Configuration settings for the TI OMAP3 EVM board.
+ *
+ * Copyright (C) 2006-2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Author :
+ *	Manikandan Pillai <mani.pillai@ti.com>
+ * Derived from Beagle Board and 3430 SDP code by
+ *	Richard Woodruff <r-woodruff2@ti.com>
+ *	Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * Manikandan Pillai <mani.pillai@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __OMAP3EVM_CONFIG_H
+#define __OMAP3EVM_CONFIG_H
+
+#include <asm/arch/cpu.h>
+#include <asm/arch/omap3.h>
+
+/* ----------------------------------------------------------------------------
+ * Supported U-boot commands
+ * ----------------------------------------------------------------------------
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
+
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+
+#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
+#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
+#undef CONFIG_CMD_IMI		/* iminfo			*/
+#undef CONFIG_CMD_IMLS		/* List all found images	*/
+
+/* ----------------------------------------------------------------------------
+ * Supported U-boot features
+ * ----------------------------------------------------------------------------
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+
+/* Display CPU and Board information */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Add auto-completion support */
+#define CONFIG_AUTO_COMPLETE
+
+/* ----------------------------------------------------------------------------
+ * Supported hardware
+ * ----------------------------------------------------------------------------
+ */
+
+/* MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_OMAP_HSMMC
+
+/* SPL */
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
+
+/* Partition tables */
+#define CONFIG_EFI_PARTITION
+#define CONFIG_DOS_PARTITION
+
+/* USB
+ *
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+#define CONFIG_USB_OMAP3
+#define CONFIG_MUSB_HCD
+/* #define CONFIG_MUSB_UDC */
+
+/* NAND SPL */
+#define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
+#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9,\
+						10, 11, 12, 13}
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW
+#define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+
+/* -----------------------------------------------------------------------------
+ * Include common board configuration
+ * -----------------------------------------------------------------------------
+ */
+#include "omap3_evm_common.h"
+
+/* -----------------------------------------------------------------------------
+ * Default environment
+ * -----------------------------------------------------------------------------
+ */
+#define CONFIG_BOOTDELAY	3
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x82000000\0" \
+	"usbtty=cdc_acm\0" \
+	"mmcdev=0\0" \
+	"console=ttyO0,115200n8\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"root=/dev/mmcblk0p2 rw " \
+		"rootfstype=ext3 rootwait\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"root=/dev/mtdblock4 rw " \
+		"rootfstype=jffs2\0" \
+	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source ${loadaddr}\0" \
+	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"onenand read ${loadaddr} 280000 400000; " \
+		"bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loaduimage; then " \
+				"run mmcboot; " \
+			"else run nandboot; " \
+			"fi; " \
+		"fi; " \
+	"else run nandboot; fi"
+
+#endif /* __OMAP3EVM_CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/omap3_evm_common.h b/qemu/roms/u-boot/include/configs/omap3_evm_common.h
new file mode 100644
index 000000000..7f3424b4f
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/omap3_evm_common.h
@@ -0,0 +1,292 @@
+/*
+ * Common configuration settings for the TI OMAP3 EVM board.
+ *
+ * Copyright (C) 2006-2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __OMAP3_EVM_COMMON_H
+#define __OMAP3_EVM_COMMON_H
+
+/*
+ * High level configuration options
+ */
+#define CONFIG_OMAP			/* This is TI OMAP core */
+#define CONFIG_OMAP34XX			/* belonging to 34XX family */
+#define CONFIG_OMAP_GPIO
+#define CONFIG_OMAP_COMMON
+
+#define CONFIG_SDRC			/* The chip has SDRC controller */
+
+#define CONFIG_OMAP3_EVM		/* This is a OMAP3 EVM */
+#define CONFIG_TWL4030_POWER		/* with TWL4030 PMIC */
+
+/*
+ * Clock related definitions
+ */
+#define V_OSCK			26000000	/* Clock output from T2 */
+#define V_SCLK			(V_OSCK >> 1)
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
+#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
+
+/* Size of environment - 128KB */
+#define CONFIG_ENV_SIZE			(128 << 10)
+
+/* Size of malloc pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
+
+/*
+ * Physical Memory Map
+ * Note 1: CS1 may or may not be populated
+ * Note 2: SDRAM size is expected to be at least 32MB
+ */
+#define CONFIG_NR_DRAM_BANKS		2
+#define PHYS_SDRAM_1			OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_2			OMAP34XX_SDRC_CS1
+
+/* Limits for memtest */
+#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
+#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
+						0x01F00000) /* 31MB */
+
+/* Default load address */
+#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)
+
+/* -----------------------------------------------------------------------------
+ * Hardware drivers
+ * -----------------------------------------------------------------------------
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SERIAL1			1	/* UART1 on OMAP3 EVM */
+#define CONFIG_SYS_NS16550_COM1		OMAP34XX_UART1
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
+					115200}
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
+#define CONFIG_SYS_I2C_OMAP34XX
+
+/*
+ * PISMO support
+ */
+#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
+#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M
+
+/* Monitor at start of flash - Reserve 2 sectors */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)
+
+/* Start location & size of environment */
+#define ONENAND_ENV_OFFSET		0x260000
+#define SMNAND_ENV_OFFSET		0x260000
+
+#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
+
+/*
+ * NAND
+ */
+/* Physical address to access NAND */
+#define CONFIG_SYS_NAND_ADDR		NAND_BASE
+
+/* Physical address to access NAND at CS0 */
+#define CONFIG_SYS_NAND_BASE		NAND_BASE
+
+/* Max number of NAND devices */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+
+/* Timeout values (in ticks) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(100 * CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(100 * CONFIG_SYS_HZ)
+
+/* Flash banks JFFS2 should use */
+#define CONFIG_SYS_MAX_MTD_BANKS	(CONFIG_SYS_MAX_FLASH_BANKS + \
+						CONFIG_SYS_MAX_NAND_DEVICE)
+
+#define CONFIG_SYS_JFFS2_MEM_NAND
+#define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
+#define CONFIG_SYS_JFFS2_NUM_BANKS	1
+
+#define CONFIG_JFFS2_NAND
+/* nand device jffs2 lives on */
+#define CONFIG_JFFS2_DEV		"nand0"
+/* Start of jffs2 partition */
+#define CONFIG_JFFS2_PART_OFFSET	0x680000
+/* Size of jffs2 partition */
+#define CONFIG_JFFS2_PART_SIZE		0xf980000
+
+/*
+ * USB
+ */
+#ifdef CONFIG_USB_OMAP3
+
+#ifdef CONFIG_MUSB_HCD
+#define CONFIG_CMD_USB
+
+#define CONFIG_USB_STORAGE
+#define CONGIG_CMD_STORAGE
+#define CONFIG_CMD_FAT
+
+#ifdef CONFIG_USB_KEYBOARD
+#define CONFIG_SYS_USB_EVENT_POLL
+#define CONFIG_PREBOOT			"usb start"
+#endif /* CONFIG_USB_KEYBOARD */
+
+#endif /* CONFIG_MUSB_HCD */
+
+#ifdef CONFIG_MUSB_UDC
+/* USB device configuration */
+#define CONFIG_USB_DEVICE
+#define CONFIG_USB_TTY
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+/* Change these to suit your needs */
+#define CONFIG_USBD_VENDORID		0x0451
+#define CONFIG_USBD_PRODUCTID		0x5678
+#define CONFIG_USBD_MANUFACTURER	"Texas Instruments"
+#define CONFIG_USBD_PRODUCT_NAME	"EVM"
+#endif /* CONFIG_MUSB_UDC */
+
+#endif /* CONFIG_USB_OMAP3 */
+
+/* ----------------------------------------------------------------------------
+ * U-boot features
+ * ----------------------------------------------------------------------------
+ */
+#define CONFIG_SYS_PROMPT		"OMAP3_EVM # "
+#define CONFIG_SYS_MAXARGS		16	/* max args for a command */
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/* Size of Console IO buffer */
+#define CONFIG_SYS_CBSIZE		512
+
+/* Size of print buffer */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+						sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Size of bootarg buffer */
+#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
+
+#define CONFIG_BOOTFILE			"uImage"
+
+/*
+ * NAND / OneNAND
+ */
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_SYS_FLASH_BASE		PISMO1_NAND_BASE
+
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
+#elif defined(CONFIG_CMD_ONENAND)
+#define CONFIG_SYS_FLASH_BASE		PISMO1_ONEN_BASE
+#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
+#endif
+
+#if !defined(CONFIG_ENV_IS_NOWHERE)
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_ENV_IS_IN_NAND
+#elif defined(CONFIG_CMD_ONENAND)
+#define CONFIG_ENV_IS_IN_ONENAND
+#define CONFIG_ENV_OFFSET		ONENAND_ENV_OFFSET
+#endif
+#endif /* CONFIG_ENV_IS_NOWHERE */
+
+#define CONFIG_ENV_ADDR			CONFIG_ENV_OFFSET
+
+#if defined(CONFIG_CMD_NET)
+
+/* Ethernet (SMSC9115 from SMSC9118 family) */
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_32_BIT
+#define CONFIG_SMC911X_BASE		0x2C000000
+
+/* BOOTP fields */
+#define CONFIG_BOOTP_SUBNETMASK		0x00000001
+#define CONFIG_BOOTP_GATEWAY		0x00000002
+#define CONFIG_BOOTP_HOSTNAME		0x00000004
+#define CONFIG_BOOTP_BOOTPATH		0x00000010
+
+#endif /* CONFIG_CMD_NET */
+
+/* Support for relocation */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE	0x800
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+
+/* -----------------------------------------------------------------------------
+ * Board specific
+ * -----------------------------------------------------------------------------
+ */
+#define CONFIG_SYS_NO_FLASH
+
+/* Uncomment to define the board revision statically */
+/* #define CONFIG_STATIC_BOARD_REV	OMAP3EVM_BOARD_GEN_2 */
+
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE		0x40200800
+#define CONFIG_SPL_MAX_SIZE		(54 * 1024)	/* 8 KB for stack */
+#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
+
+#define CONFIG_SPL_BSS_START_ADDR	0x80000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
+
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_OMAP3_ID_NAND
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
+
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * other needs.
+ */
+#define CONFIG_SYS_TEXT_BASE		0x80100000
+#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
+
+#endif /* __OMAP3_EVM_COMMON_H */
diff --git a/qemu/roms/u-boot/include/configs/omap3_evm_quick_mmc.h b/qemu/roms/u-boot/include/configs/omap3_evm_quick_mmc.h
new file mode 100644
index 000000000..50929aaea
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/omap3_evm_quick_mmc.h
@@ -0,0 +1,93 @@
+/*
+ * Configuration settings for quick boot from MMC on OMAP3 EVM.
+ *
+ * Copyright (C) 2006-2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Author :
+ *     Sanjeev Premi <premi@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __OMAP3_EVM_QUICK_MMC_H
+#define __OMAP3_EVM_QUICK_MMC_H
+
+#include <asm/arch/cpu.h>
+#include <asm/arch/omap3.h>
+
+/* ----------------------------------------------------------------------------
+ * Supported U-boot commands
+ * ----------------------------------------------------------------------------
+ */
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_FAT
+
+/*
+ * Board revision is detected by probing the Ethernet chip.
+ *
+ * When revision is statically configured via CONFIG_STATIC_BOARD_REV,
+ * this option can be removed. Generated binary is leaner by ~16Kbytes.
+ */
+#define CONFIG_CMD_NET
+
+/* ----------------------------------------------------------------------------
+ * Supported U-boot features
+ * ----------------------------------------------------------------------------
+ */
+#define CONFIG_SILENT_CONSOLE
+#define CONFIG_ENV_IS_NOWHERE
+
+/* ----------------------------------------------------------------------------
+ * Supported hardware
+ * ----------------------------------------------------------------------------
+ */
+
+/* MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_DOS_PARTITION
+
+/* -----------------------------------------------------------------------------
+ * Include common board configuration
+ * -----------------------------------------------------------------------------
+ */
+#include "omap3_evm_common.h"
+
+/* -----------------------------------------------------------------------------
+ * Default environment
+ * -----------------------------------------------------------------------------
+ */
+#define CONFIG_BOOTDELAY	0
+
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"verify=no\0"			\
+	"silent=1"
+
+#define CONFIG_BOOTCOMMAND			\
+	"mmc rescan 0; "			\
+	"fatload mmc 0 0x82000000 uImage; "	\
+	"bootm 0x82000000;"
+
+/*
+ * Update the bootargs as necessary e.g. size of memory, partition and fstype
+ */
+#define CONFIG_BOOTARGS			\
+	"quiet "			\
+	"console=ttyO0,115200n8 "	\
+	"mem=128M "			\
+	"noinitrd "			\
+	"root=/dev/mmcblk0p2 rw "	\
+	"rootfstype=ext3 rootwait"
+
+/*
+ * SPL
+ */
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
+
+#endif /* __OMAP3_EVM_QUICK_MMC_H */
diff --git a/qemu/roms/u-boot/include/configs/omap3_evm_quick_nand.h b/qemu/roms/u-boot/include/configs/omap3_evm_quick_nand.h
new file mode 100644
index 000000000..4427e88b7
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/omap3_evm_quick_nand.h
@@ -0,0 +1,93 @@
+/*
+ * Configuration settings for quick boot from NAND on OMAP3 EVM.
+ *
+ * Copyright (C) 2006-2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Author :
+ *     Sanjeev Premi <premi@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __OMAP3_EVM_QUICK_NAND_H
+#define __OMAP3_EVM_QUICK_NAND_H
+
+#include <asm/arch/cpu.h>
+#include <asm/arch/omap3.h>
+
+/* ----------------------------------------------------------------------------
+ * Supported U-boot commands
+ * ----------------------------------------------------------------------------
+ */
+#define CONFIG_CMD_NAND
+
+/*
+ * Board revision is detected by probing the Ethernet chip.
+ *
+ * When revision is statically configured via CONFIG_STATIC_BOARD_REV,
+ * this option can be removed. Generated binary is leaner by ~16Kbytes.
+ */
+#define CONFIG_CMD_NET
+
+/* ----------------------------------------------------------------------------
+ * Supported U-boot features
+ * ----------------------------------------------------------------------------
+ */
+#define CONFIG_SILENT_CONSOLE
+#define CONFIG_ENV_IS_NOWHERE
+
+/* -----------------------------------------------------------------------------
+ * Include common board configuration
+ * -----------------------------------------------------------------------------
+ */
+#include "omap3_evm_common.h"
+
+/* -----------------------------------------------------------------------------
+ * Default environment
+ * -----------------------------------------------------------------------------
+ */
+#define CONFIG_BOOTDELAY	0
+
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"verify=no\0"			\
+	"silent=1"
+
+#define CONFIG_BOOTCOMMAND				\
+	"nandecc hw; "	\
+	"nand read.i 0x80000000 280000 300000; "	\
+	"bootm 0x80000000;"
+
+/*
+ * Update the bootargs as necessary e.g. size of memory, partition and fstype
+ */
+#define CONFIG_BOOTARGS				\
+	"quiet "			\
+	"console=ttyO0,115200n8 "	\
+	"mem=128M "			\
+	"noinitrd "			\
+	"root=/dev/mtdblock4 rw "	\
+	"rootfstype=jffs2 "
+
+/*
+ * SPL
+ */
+#define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
+#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9,\
+						10, 11, 12, 13}
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW
+#define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+
+#endif /* __OMAP3_EVM_QUICK_NAND_H */
diff --git a/qemu/roms/u-boot/include/configs/omap3_igep00x0.h b/qemu/roms/u-boot/include/configs/omap3_igep00x0.h
new file mode 100644
index 000000000..d56d5b00c
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/omap3_igep00x0.h
@@ -0,0 +1,203 @@
+/*
+ * Common configuration settings for IGEP technology based boards
+ *
+ * (C) Copyright 2012
+ * ISEE 2007 SL, <www.iseebcn.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __IGEP00X0_H
+#define __IGEP00X0_H
+
+#ifdef CONFIG_BOOT_NAND
+#define CONFIG_NAND
+#endif
+
+#define CONFIG_NR_DRAM_BANKS            2
+
+#include <configs/ti_omap3_common.h>
+#include <asm/mach-types.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO		1
+#define CONFIG_DISPLAY_BOARDINFO	1
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_REVISION_TAG		1
+
+#define CONFIG_SUPPORT_RAW_INITRD
+
+/* define to enable boot progress via leds */
+#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \
+    (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
+#define CONFIG_SHOW_BOOT_PROGRESS
+#endif
+
+/* GPIO banks */
+#define CONFIG_OMAP3_GPIO_3		/* GPIO64 .. 95 is in GPIO bank 3 */
+#define CONFIG_OMAP3_GPIO_5		/* GPIO128..159 is in GPIO bank 5 */
+#define CONFIG_OMAP3_GPIO_6		/* GPIO160..191 is in GPIO bank 6 */
+
+/* USB */
+#define CONFIG_MUSB_UDC			1
+#define CONFIG_USB_OMAP3		1
+#define CONFIG_TWL4030_USB		1
+
+/* USB device configuration */
+#define CONFIG_USB_DEVICE		1
+#define CONFIG_USB_TTY			1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
+
+/* Change these to suit your needs */
+#define CONFIG_USBD_VENDORID		0x0451
+#define CONFIG_USBD_PRODUCTID		0x5678
+#define CONFIG_USBD_MANUFACTURER	"Texas Instruments"
+#define CONFIG_USBD_PRODUCT_NAME	"IGEP"
+
+#define CONFIG_CMD_CACHE
+#ifdef CONFIG_BOOT_ONENAND
+#define CONFIG_CMD_ONENAND	/* ONENAND support		*/
+#endif
+#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \
+    (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0032)
+#define CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot	*/
+#endif
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_NFS		/* NFS support			*/
+
+/*#undef CONFIG_ENV_IS_NOWHERE*/
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"usbtty=cdc_acm\0" \
+	"loadaddr=0x82000000\0" \
+	"dtbaddr=0x81600000\0" \
+	"bootdir=/boot\0" \
+	"bootfile=zImage\0" \
+	"usbtty=cdc_acm\0" \
+	"console=ttyO2,115200n8\0" \
+	"mpurate=auto\0" \
+	"vram=12M\0" \
+	"dvimode=1024x768MR-16@60\0" \
+	"defaultdisplay=dvi\0" \
+	"mmcdev=0\0" \
+	"mmcroot=/dev/mmcblk0p2 rw\0" \
+	"mmcrootfstype=ext4 rootwait\0" \
+	"nandroot=/dev/mtdblock4 rw\0" \
+	"nandrootfstype=jffs2\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"mpurate=${mpurate} " \
+		"vram=${vram} " \
+		"omapfb.mode=dvi:${dvimode} " \
+		"omapfb.debug=y " \
+		"omapdss.def_disp=${defaultdisplay} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"mpurate=${mpurate} " \
+		"vram=${vram} " \
+		"omapfb.mode=dvi:${dvimode} " \
+		"omapfb.debug=y " \
+		"omapdss.def_disp=${defaultdisplay} " \
+		"root=${nandroot} " \
+		"rootfstype=${nandrootfstype}\0" \
+	"loadbootenv=load mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
+	"importbootenv=echo Importing environment from mmc ...; " \
+		"env import -t $loadaddr $filesize\0" \
+	"loadzimage=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}\0" \
+	"loadfdt=load mmc ${mmcdev}:2 ${dtbaddr} ${bootdir}/${dtbfile}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootz ${loadaddr}\0" \
+	"mmcbootfdt=echo Booting with DT from mmc ...; " \
+		"bootz ${loadaddr} - ${dtbaddr}\0" \
+	"nandboot=echo Booting from onenand ...; " \
+		"run nandargs; " \
+		"onenand read ${loadaddr} 280000 400000; " \
+		"bootz ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"echo SD/MMC found on device ${mmcdev};" \
+		"if run loadbootenv; then " \
+			"run importbootenv;" \
+		"fi;" \
+		"if test -n $uenvcmd; then " \
+			"echo Running uenvcmd ...;" \
+			"run uenvcmd;" \
+		"fi;" \
+		"if run loadzimage; then " \
+			"if test -n $dtbfile; then " \
+				"if run loadfdt; then " \
+					"run mmcbootfdt;" \
+				"fi;" \
+			"fi;" \
+			"run mmcboot;" \
+		"fi;" \
+	"fi;" \
+	"run nandboot;" \
+
+/*
+ * FLASH and environment organization
+ */
+
+#ifdef CONFIG_BOOT_ONENAND
+#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M /* Configure the PISMO */
+
+#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
+
+#define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
+
+#define CONFIG_ENV_IS_IN_ONENAND	1
+#define CONFIG_ENV_SIZE			(512 << 10) /* Total Size Environment */
+#define CONFIG_ENV_ADDR			ONENAND_ENV_OFFSET
+#endif
+
+#ifdef CONFIG_NAND
+#define PISMO1_NAND_SIZE		GPMC_SIZE_128M /* Configure the PISMO */
+#define CONFIG_ENV_OFFSET		0x260000 /* environment starts here */
+#define CONFIG_ENV_IS_IN_NAND	        1
+#define CONFIG_ENV_SIZE			(512 << 10) /* Total Size Environment */
+#define CONFIG_ENV_ADDR			NAND_ENV_OFFSET
+#endif
+
+/*
+ * SMSC911x Ethernet
+ */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_32_BIT
+#define CONFIG_SMC911X_BASE	0x2C000000
+#endif /* (CONFIG_CMD_NET) */
+
+/* OneNAND boot config */
+#ifdef CONFIG_BOOT_ONENAND
+#define CONFIG_SPL_ONENAND_SUPPORT
+#define CONFIG_SYS_ONENAND_U_BOOT_OFFS  0x80000
+#define CONFIG_SYS_ONENAND_PAGE_SIZE	2048
+#define CONFIG_SPL_ONENAND_LOAD_ADDR    0x80000
+#define CONFIG_SPL_ONENAND_LOAD_SIZE    \
+	(512 * 1024 - CONFIG_SPL_ONENAND_LOAD_ADDR)
+
+#endif
+
+/* NAND boot config */
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
+#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9,\
+						10, 11, 12, 13}
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW
+#endif
+
+#endif /* __IGEP00X0_H */
diff --git a/qemu/roms/u-boot/include/configs/omap3_logic.h b/qemu/roms/u-boot/include/configs/omap3_logic.h
new file mode 100644
index 000000000..0d03c75ce
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/omap3_logic.h
@@ -0,0 +1,332 @@
+/*
+ * (C) Copyright 2011 Logic Product Development <www.logicpd.com>
+ *	Peter Barada <peter.barada@logicpd.com>
+ *
+ * Configuration settings for the Logic OMAP35x/DM37x SOM LV/Torpedo
+ * reference boards.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_OMAP			/* in a TI OMAP core */
+#define CONFIG_OMAP34XX			/* which is a 34XX */
+#define CONFIG_OMAP3_LOGIC		/* working with Logic OMAP boards */
+#define CONFIG_OMAP_GPIO
+#define CONFIG_OMAP_COMMON
+
+#define CONFIG_SYS_TEXT_BASE	0x80400000
+
+#define CONFIG_SDRC	/* The chip has SDRC controller */
+
+#include <asm/arch/cpu.h>	/* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Clock Defines */
+#define V_OSCK			26000000	/* Clock output from T2 */
+#define V_SCLK			(V_OSCK >> 1)
+
+#define CONFIG_MISC_INIT_R		/* misc_init_r dumps the die id */
+
+#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+#define CONFIG_CMDLINE_EDITING			/* cmd line edit/history */
+#define CONFIG_ZERO_BOOTDELAY_CHECK		/* check keypress w/no delay */
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
+						/* Sector */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550_COM1		OMAP34XX_UART1
+#define CONFIG_SERIAL1			1	/* UART1 on OMAP Logic boards */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
+					115200}
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_DOS_PARTITION
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
+#define CONFIG_CMD_FAT		/* FAT support			*/
+#define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
+#define CONFIG_CMD_MTDPARTS	/* Enable MTD parts commands */
+#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
+#define MTDIDS_DEFAULT			"nand0=omap2-nand.0"
+#define MTDPARTS_DEFAULT		"mtdparts=omap2-nand.0:512k(x-loader),"\
+					"1920k(u-boot),128k(u-boot-env),"\
+					"4m(kernel),-(fs)"
+
+#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
+#define CONFIG_CMD_MMC		/* MMC support			*/
+#define CONFIG_CMD_NAND		/* NAND support			*/
+#define CONFIG_CMD_NAND_LOCK_UNLOCK	/* nand (un)lock commands	*/
+#define CONFIG_CMD_NET      /* bootp, tftpboot, rarpboot    */
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_SETEXPR	/* Evaluate expressions		*/
+
+#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
+#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
+#undef CONFIG_CMD_IMI		/* iminfo			*/
+#undef CONFIG_CMD_IMLS		/* List all found images	*/
+
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
+#define CONFIG_SYS_I2C_OMAP34XX
+
+/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER
+
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_SYS_NAND_QUIET_TEST
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
+							/* to access nand */
+#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
+							/* to access nand at */
+							/* CS0 */
+
+#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
+							/* NAND devices */
+#define CONFIG_JFFS2_NAND
+/* nand device jffs2 lives on */
+#define CONFIG_JFFS2_DEV		"nand0"
+/* start of jffs2 partition */
+#define CONFIG_JFFS2_PART_OFFSET	0x680000
+#define CONFIG_JFFS2_PART_SIZE		0xf980000	/* size of jffs2 */
+							/* partition */
+
+/* Environment information */
+#define CONFIG_BOOTDELAY		2
+
+/*
+ * PREBOOT assumes the 4.3" display is attached.  User can interrupt
+ * and modify display variable to suit their needs.
+ */
+#define CONFIG_PREBOOT \
+	"echo ======================NOTICE============================;"\
+	"echo \"The u-boot environment is not set.\";"			\
+	"echo \"If using a display a valid display varible for your panel\";" \
+	"echo \"needs to be set.\";"					\
+	"echo \"Valid display options are:\";"				\
+	"echo \"  2 == LQ121S1DG31     TFT SVGA    (12.1)  Sharp\";"	\
+	"echo \"  3 == LQ036Q1DA01     TFT QVGA    (3.6)   Sharp w/ASIC\";" \
+	"echo \"  5 == LQ064D343       TFT VGA     (6.4)   Sharp\";"	\
+	"echo \"  7 == LQ10D368        TFT VGA     (10.4)  Sharp\";"	\
+	"echo \" 15 == LQ043T1DG01     TFT WQVGA   (4.3)   Sharp (DEFAULT)\";" \
+	"echo \" vga[-dvi or -hdmi]    LCD VGA     640x480\";"          \
+	"echo \" svga[-dvi or -hdmi]   LCD SVGA    800x600\";"          \
+	"echo \" xga[-dvi or -hdmi]    LCD XGA     1024x768\";"         \
+	"echo \" 720p[-dvi or -hdmi]   LCD 720P    1280x720\";"         \
+	"echo \"Defaulting to 4.3 LCD panel (display=15).\";"		\
+	"setenv display 15;"						\
+	"setenv preboot;"						\
+	"saveenv;"
+
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x81000000\0" \
+	"bootfile=uImage\0" \
+	"mtdids=" MTDIDS_DEFAULT "\0"	\
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"mmcdev=0\0" \
+	"autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
+			"if run loadbootscript; then " \
+				"run bootscript; " \
+			"else " \
+				"run defaultboot;" \
+			"fi; " \
+		"else run defaultboot; fi\0" \
+	"defaultboot=run mmcramboot\0" \
+	"consoledevice=ttyO0\0" \
+	"display=15\0" \
+	"setconsole=setenv console ${consoledevice},${baudrate}n8\0" \
+	"dump_bootargs=echo 'Bootargs: '; echo $bootargs\0" \
+	"rotation=0\0" \
+	"vrfb_arg=if itest ${rotation} -ne 0; then " \
+		"setenv bootargs ${bootargs} omapfb.vrfb=y " \
+		"omapfb.rotate=${rotation}; " \
+		"fi\0" \
+	"otherbootargs=ignore_loglevel early_printk no_console_suspend\0" \
+	"addmtdparts=setenv bootargs ${bootargs} ${mtdparts}\0" \
+	"common_bootargs=setenv bootargs ${bootargs} display=${display} " \
+		"${otherbootargs};" \
+		"run addmtdparts; " \
+		"run vrfb_arg\0" \
+	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+	"bootscript=echo 'Running bootscript from mmc ...'; " \
+		"source ${loadaddr}\0" \
+	"loaduimage=mmc rescan ${mmcdev}; " \
+		"fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \
+	"ramdisksize=64000\0" \
+	"ramdiskaddr=0x82000000\0" \
+	"ramdiskimage=rootfs.ext2.gz.uboot\0" \
+	"ramargs=run setconsole; setenv bootargs console=${console} " \
+		"root=/dev/ram rw ramdisk_size=${ramdisksize}\0" \
+	"mmcramboot=echo 'Booting kernel from mmc w/ramdisk...'; " \
+		"run ramargs; " \
+		"run common_bootargs; " \
+		"run dump_bootargs; " \
+		"run loaduimage; " \
+		"fatload mmc ${mmcdev} ${ramdiskaddr} ${ramdiskimage}; "\
+		"bootm ${loadaddr} ${ramdiskaddr}\0" \
+	"ramboot=echo 'Booting kernel/ramdisk rootfs from tftp...'; " \
+		"run ramargs; " \
+		"run common_bootargs; " \
+		"run dump_bootargs; " \
+		"tftpboot ${loadaddr} ${bootfile}; "\
+		"tftpboot ${ramdiskaddr} ${ramdiskimage}; "\
+		"bootm ${loadaddr} ${ramdiskaddr}\0"
+
+#define CONFIG_BOOTCOMMAND \
+	"run autoboot"
+
+#define CONFIG_AUTO_COMPLETE
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT		"OMAP Logic # "
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
+#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
+					0x01F00000) /* 31MB */
+
+#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
+								/* address */
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
+#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
+#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
+
+/*
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+
+/* Configure the PISMO */
+#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
+
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_SYS_FLASH_BASE		PISMO1_NAND_BASE
+#elif defined(CONFIG_CMD_ONENAND)
+#define CONFIG_SYS_FLASH_BASE		PISMO1_ONEN_BASE
+#endif
+
+/* Monitor at start of flash */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+
+#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
+
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
+#endif
+
+#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
+#define CONFIG_ENV_ADDR			CONFIG_ENV_OFFSET
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE	0x800
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+
+/*
+ * SMSC922x Ethernet
+ */
+#if defined(CONFIG_CMD_NET)
+
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_16_BIT
+#define CONFIG_SMC911X_BASE	0x08000000
+
+#endif /* (CONFIG_CMD_NET) */
+
+/*
+ * BOOTP fields
+ */
+
+#define CONFIG_BOOTP_SUBNETMASK		0x00000001
+#define CONFIG_BOOTP_GATEWAY		0x00000002
+#define CONFIG_BOOTP_HOSTNAME		0x00000004
+#define CONFIG_BOOTP_BOOTPATH		0x00000010
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/omap3_mvblx.h b/qemu/roms/u-boot/include/configs/omap3_mvblx.h
new file mode 100644
index 000000000..8d11010f8
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/omap3_mvblx.h
@@ -0,0 +1,284 @@
+/*
+ * MATRIX VISION GmbH mvBlueLYNX-X
+ *
+ * Derived from omap3_beagle.h:
+ * (C) Copyright 2006-2008
+ * Texas Instruments.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * Configuration settings for the TI OMAP3530 Beagle board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMV7		1	/* This is an ARM V7 CPU core */
+#define CONFIG_OMAP		1	/* in a TI OMAP core */
+#define CONFIG_OMAP34XX		1	/* which is a 34XX */
+#define CONFIG_MVBLX		1	/* working with mvBlueLYNX-X */
+#define CONFIG_MACH_TYPE	MACH_TYPE_MVBLX
+#define CONFIG_OMAP_GPIO
+#define CONFIG_OMAP_COMMON
+
+#define CONFIG_SDRC	/* The chip has SDRC controller */
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO		1
+#define CONFIG_DISPLAY_BOARDINFO	1
+
+/* Clock Defines */
+#define V_OSCK			26000000	/* Clock output from T2 */
+#define V_SCLK			(V_OSCK >> 1)
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_OF_LIBFDT		1
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+#define CONFIG_REVISION_TAG		1
+#define CONFIG_SERIAL_TAG		1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE			(2 << 10)	/* 2 KiB */
+						/* Sector */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550_COM1		OMAP34XX_UART1
+#define CONFIG_SERIAL1			1	/* UART1 */
+
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
+					115200}
+#define CONFIG_GENERIC_MMC		1
+#define CONFIG_MMC			1
+#define CONFIG_OMAP_HSMMC		1
+#define CONFIG_DOS_PARTITION		1
+
+/* silent console by default */
+#define CONFIG_SYS_DEVICE_NULLDEV	1
+#define CONFIG_SILENT_CONSOLE		1
+
+/* USB */
+#define CONFIG_MUSB_UDC			1
+#define CONFIG_USB_OMAP3		1
+#define CONFIG_TWL4030_USB		1
+
+/* USB device configuration */
+#define CONFIG_USB_DEVICE		1
+#define CONFIG_USB_TTY			1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1
+#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 1
+#define CONFIG_USBD_VENDORID			0x164c
+#define CONFIG_USBD_PRODUCTID_GSERIAL	0x0201
+#define CONFIG_USBD_PRODUCTID_CDCACM	0x0201
+#define CONFIG_USBD_MANUFACTURER		"MATRIX VISION GmbH"
+#define CONFIG_USBD_PRODUCT_NAME		"mvBlueLYNX-X"
+
+/* no FLASH available */
+#define CONFIG_SYS_NO_FLASH
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
+#define CONFIG_CMD_FAT		/* FAT support			*/
+#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
+#define CONFIG_CMD_MMC		/* MMC support			*/
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_IMI		/* iminfo			*/
+#undef CONFIG_CMD_IMLS		/* List all found images	*/
+#define CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot	*/
+#define CONFIG_CMD_NFS		/* NFS support			*/
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_FPGA
+
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
+#define CONFIG_SYS_I2C_OMAP34XX
+
+/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER		1
+
+/* Environment information */
+#undef CONFIG_ENV_OVERWRITE	/* disallow overwriting serial# and ethaddr */
+#define CONFIG_BOOTDELAY		0
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_STOP_STR "S"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"silent=true\0" \
+	"loadaddr=0x82000000\0" \
+	"usbtty=cdc_acm\0" \
+	"console=ttyO0,115200n8\0" \
+	"mpurate=600\0" \
+	"vram=12M\0" \
+	"dvimode=1024x768-24@60\0" \
+	"defaultdisplay=dvi\0" \
+	"loadfpga=if ext2load mmc ${mmcdev}:2 ${loadaddr} "\
+		"/lib/firmware/mvblx/${fpgafilename}; then " \
+			"fpga load 0 ${loadaddr} ${filesize}; " \
+		"fi;\0" \
+	"mmcdev=0\0" \
+	"mmcroot=/dev/mmcblk0p2 rw\0" \
+	"mmcrootfstype=ext3 rootwait\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"mpurate=${mpurate} " \
+		"vram=${vram} " \
+		"omapfb.mode=dvi:${dvimode} " \
+		"omapfb.debug=y " \
+		"omapdss.def_disp=${defaultdisplay} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype} " \
+		"mvfw.fpgavers=${fpgavers} " \
+		"${cmdline_suffix}\0" \
+	"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
+	"importbootenv=echo Importing environment from mmc ...; " \
+		"env import -t $loadaddr $filesize\0" \
+	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0" \
+	"mmcbootcmd= " \
+		"echo Trying mmc${mmcdev}; " \
+		"mmc dev ${mmcdev}; " \
+		"if mmc rescan; then " \
+			"setenv mmcroot /dev/mmcblk${mmcdev}p2 rw; " \
+			"echo SD/MMC found on device ${mmcdev};" \
+			"if run loadbootenv; then " \
+			   "echo Loading boot environment from mmc${mmcdev}; " \
+			   "run importbootenv; " \
+			"fi;" \
+			"run loadfpga; " \
+			"if test -n $uenvcmd; then " \
+				"echo Running uenvcmd ...;" \
+				"run uenvcmd;" \
+			"fi;" \
+			"if run loaduimage; then " \
+				"run mmcboot; " \
+			"fi;" \
+		"fi\0"
+
+#define CONFIG_BOOTCOMMAND \
+	"setenv mmcdev 1;" \
+	"run mmcbootcmd || " \
+	"setenv mmcdev 0;" \
+	"run mmcbootcmd"
+
+
+#define CONFIG_AUTO_COMPLETE		1
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT		"mvblx # "
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
+
+#define CONFIG_SYS_ALT_MEMTEST      1 /* alternative memtest with looping */
+#define CONFIG_SYS_MEMTEST_START	(0x82000000)	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		(0x9dffffff)	/* end = 448 MB */
+#define CONFIG_SYS_MEMTEST_SCRATCH	(0x81000000)    /* dummy address */
+
+/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
+#define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
+
+#define CONFIG_ENV_IS_NOWHERE	1
+
+/*----------------------------------------------------------------------------
+ * Network Subsystem (SMSC9211 Ethernet from SMSC9118 family)
+ *----------------------------------------------------------------------------
+ */
+#if defined(CONFIG_CMD_NET)
+  #define CONFIG_SMC911X		1
+  #define CONFIG_SMC911X_32_BIT
+  #define CONFIG_SMC911X_BASE     0x2C000000
+#endif /* (CONFIG_CMD_NET) */
+
+#define CONFIG_FPGA_COUNT	1
+#define CONFIG_FPGA
+#define CONFIG_FPGA_ALTERA
+#define CONFIG_FPGA_CYCLON2
+#define CONFIG_SYS_FPGA_PROG_FEEDBACK
+#define CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 0xA0>>1 */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4  /* 2^4 = 16-byte pages */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+#define CONFIG_SYS_EEPROM_SIZE 256 /* Bytes */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_EEPROM_BUS_NUM	2
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE	0x800
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_OMAP3_SPI
+
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/omap3_overo.h b/qemu/roms/u-boot/include/configs/omap3_overo.h
new file mode 100644
index 000000000..007e27f9f
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/omap3_overo.h
@@ -0,0 +1,329 @@
+/*
+ * Configuration settings for the Gumstix Overo board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_OMAP				/* in a TI OMAP core */
+#define CONFIG_OMAP34XX				/* which is a 34XX */
+#define CONFIG_OMAP3_OVERO			/* working with overo */
+#define CONFIG_OMAP_GPIO
+#define CONFIG_OMAP_COMMON
+
+#define CONFIG_SDRC				/* The chip has SDRC controller */
+
+#include <asm/arch/cpu.h>			/* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Clock Defines */
+#define V_OSCK			26000000	/* Clock output from T2 */
+#define V_SCLK			(V_OSCK >> 1)
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+#define CONFIG_OF_LIBFDT
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE		(128 << 10)	/* 128 KiB */
+						/* Sector */
+#define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + (128 << 10))
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK		48000000	/* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX		3
+#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
+#define CONFIG_SERIAL3			3
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600, \
+					115200}
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_DOS_PARTITION
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
+#define CONFIG_CMD_FAT		/* FAT support			*/
+#define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
+
+#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
+#define CONFIG_CMD_MMC		/* MMC support			*/
+#define CONFIG_CMD_NAND		/* NAND support			*/
+
+#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
+#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
+#undef CONFIG_CMD_IMI		/* iminfo			*/
+#undef CONFIG_CMD_IMLS		/* List all found images	*/
+#undef CONFIG_CMD_NFS		/* NFS support			*/
+#define CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot	*/
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
+#define CONFIG_SYS_I2C_OMAP34XX
+
+/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER
+#define CONFIG_TWL4030_LED
+
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_SYS_NAND_QUIET_TEST
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
+							/* to access nand */
+#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
+							/* to access nand */
+							/* at CS0 */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND */
+						/* devices */
+#define CONFIG_JFFS2_NAND
+/* nand device jffs2 lives on */
+#define CONFIG_JFFS2_DEV		"nand0"
+/* start of jffs2 partition */
+#define CONFIG_JFFS2_PART_OFFSET	0x680000
+#define CONFIG_JFFS2_PART_SIZE		0xf980000	/* size of jffs2 */
+							/* partition */
+
+/* Environment information */
+#define CONFIG_BOOTDELAY		5
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x82000000\0" \
+	"console=ttyO2,115200n8\0" \
+	"mpurate=500\0" \
+	"optargs=\0" \
+	"vram=12M\0" \
+	"dvimode=1024x768MR-16@60\0" \
+	"defaultdisplay=dvi\0" \
+	"mmcdev=0\0" \
+	"mmcroot=/dev/mmcblk0p2 rw\0" \
+	"mmcrootfstype=ext3 rootwait\0" \
+	"nandroot=ubi0:rootfs ubi.mtd=4\0" \
+	"nandrootfstype=ubifs\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"mpurate=${mpurate} " \
+		"vram=${vram} " \
+		"omapfb.mode=dvi:${dvimode} " \
+		"omapdss.def_disp=${defaultdisplay} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"mpurate=${mpurate} " \
+		"vram=${vram} " \
+		"omapfb.mode=dvi:${dvimode} " \
+		"omapdss.def_disp=${defaultdisplay} " \
+		"root=${nandroot} " \
+		"rootfstype=${nandrootfstype}\0" \
+	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source ${loadaddr}\0" \
+	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nand read ${loadaddr} 280000 400000; " \
+		"bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loaduimage; then " \
+				"run mmcboot; " \
+			"else run nandboot; " \
+			"fi; " \
+		"fi; " \
+	"else run nandboot; fi"
+
+#define CONFIG_AUTO_COMPLETE	1
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT		"Overo # "
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16	/* max number of command */
+						/* args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
+#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
+					0x01F00000) /* 31MB */
+
+#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
+								/* address */
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
+#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
+#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+
+/* Configure the PISMO */
+#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
+#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
+
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_SYS_FLASH_BASE		PISMO1_NAND_BASE
+#endif
+
+/* Monitor at start of flash */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
+
+#define CONFIG_ENV_IS_IN_NAND
+#define ONENAND_ENV_OFFSET		0x240000 /* environment starts here */
+#define SMNAND_ENV_OFFSET		0x240000 /* environment starts here */
+
+#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
+#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
+#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
+
+#if defined(CONFIG_CMD_NET)
+/*----------------------------------------------------------------------------
+ * SMSC9211 Ethernet from SMSC9118 family
+ *----------------------------------------------------------------------------
+ */
+
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_32_BIT
+#define CONFIG_SMC911X_BASE		0x2C000000
+
+#endif /* (CONFIG_CMD_NET) */
+
+/*
+ * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader
+ * and older u-boot.bin with the new U-Boot SPL.
+ */
+#define CONFIG_SYS_TEXT_BASE		0x80008000
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE	0x800
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SPL_TEXT_BASE		0x40200800
+#define CONFIG_SPL_MAX_SIZE		(54 * 1024)	/* 8 KB for stack */
+#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
+
+/* move malloc and bss high to prevent clashing with the main image */
+#define CONFIG_SYS_SPL_MALLOC_START	0x87000000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
+#define CONFIG_SPL_BSS_START_ADDR	0x87080000	/* end of minimum RAM */
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
+
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
+
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
+
+/* NAND boot config */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9,\
+						10, 11, 12, 13}
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+
+#endif				/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/omap3_pandora.h b/qemu/roms/u-boot/include/configs/omap3_pandora.h
new file mode 100644
index 000000000..da67787e6
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/omap3_pandora.h
@@ -0,0 +1,246 @@
+/*
+ * (C) Copyright 2008-2010
+ * Gražvydas Ignotas <notasas@gmail.com>
+ *
+ * Configuration settings for the OMAP3 Pandora.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_OMAP		1	/* in a TI OMAP core */
+#define CONFIG_OMAP34XX		1	/* which is a 34XX */
+#define CONFIG_OMAP3_PANDORA	1	/* working with pandora */
+#define CONFIG_OMAP_GPIO
+#define CONFIG_OMAP_COMMON
+
+#define CONFIG_SDRC	/* The chip has SDRC controller */
+
+#include <asm/arch/cpu.h>	/* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO		1
+#define CONFIG_DISPLAY_BOARDINFO	1
+
+/* Clock Defines */
+#define V_OSCK			26000000	/* Clock output from T2 */
+#define V_SCLK			(V_OSCK >> 1)
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+#define CONFIG_REVISION_TAG		1
+
+#define CONFIG_OF_LIBFDT		1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024 + CONFIG_ENV_SIZE)
+
+/*
+ * Hardware drivers
+ */
+
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
+#define CONFIG_SYS_DEVICE_NULLDEV	1
+
+/* USB */
+#define CONFIG_MUSB_UDC			1
+#define CONFIG_USB_OMAP3		1
+#define CONFIG_TWL4030_USB		1
+
+/* USB device configuration */
+#define CONFIG_USB_DEVICE		1
+#define CONFIG_USB_TTY			1
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX		3
+#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
+#define CONFIG_SERIAL3			3
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600, \
+					115200}
+#define CONFIG_GENERIC_MMC		1
+#define CONFIG_MMC			1
+#define CONFIG_OMAP_HSMMC		1
+#define CONFIG_DOS_PARTITION		1
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
+#define CONFIG_CMD_FAT		/* FAT support			*/
+
+#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
+#define CONFIG_CMD_MMC		/* MMC support			*/
+#define CONFIG_CMD_NAND		/* NAND support			*/
+#define CONFIG_CMD_CACHE	/* Cache control		*/
+
+#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
+#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
+#undef CONFIG_CMD_IMI		/* iminfo			*/
+#undef CONFIG_CMD_IMLS		/* List all found images	*/
+#undef CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot	*/
+#undef CONFIG_CMD_NFS		/* NFS support			*/
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
+#define CONFIG_SYS_I2C_OMAP34XX
+
+/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER		1
+#define CONFIG_TWL4030_LED		1
+
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
+							/* to access nand */
+#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
+							/* to access nand */
+							/* at CS0 */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND */
+						/* devices */
+
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+
+#define MTDIDS_DEFAULT			"nand0=nand"
+#define MTDPARTS_DEFAULT		"mtdparts=nand:512k(xloader),"\
+					"1920k(uboot),128k(uboot-env),"\
+					"10m(boot),-(rootfs)"
+#else
+#define MTDPARTS_DEFAULT
+#endif
+
+/* Environment information */
+#define CONFIG_BOOTDELAY		1
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"usbtty=cdc_acm\0" \
+	"loadaddr=0x82000000\0" \
+	"bootargs=ubi.mtd=4 ubi.mtd=3 root=ubi0:rootfs rootfstype=ubifs " \
+		"rw rootflags=bulk_read vram=6272K omapfb.vram=0:3000K\0" \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"if mmc rescan && fatload mmc1 0 ${loadaddr} autoboot.scr || " \
+			"ext2load mmc1 0 ${loadaddr} autoboot.scr; then " \
+		"source ${loadaddr}; " \
+	"fi; " \
+	"ubi part boot && ubifsmount ubi:boot && " \
+		"ubifsload ${loadaddr} uImage && bootm ${loadaddr}"
+
+#define CONFIG_AUTO_COMPLETE	1
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT		"Pandora # "
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16	/* max number of command */
+						/* args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
+#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
+					0x01F00000) /* 31MB */
+
+#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
+								/* address */
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
+#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
+#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
+
+#define CONFIG_SYS_TEXT_BASE		0x80008000
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE	0x800
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+
+/* Configure the PISMO */
+#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
+#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
+
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_SYS_FLASH_BASE		PISMO1_NAND_BASE
+#endif
+
+/* Monitor at start of flash */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_ENV_IS_IN_NAND		1
+#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
+
+#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
+#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
+#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
+
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
+#endif				/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/omap3_sdp3430.h b/qemu/roms/u-boot/include/configs/omap3_sdp3430.h
new file mode 100644
index 000000000..a3e8a5997
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/omap3_sdp3430.h
@@ -0,0 +1,324 @@
+/*
+ * (C) Copyright 2006-2009
+ * Texas Instruments Incorporated.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ * Nishanth Menon <nm@ti.com>
+ *
+ * Configuration settings for the 3430 TI SDP3430 board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* TODO: REMOVE THE FOLLOWING
+ * Retained the following till size.h is removed in u-boot
+ */
+#include <linux/sizes.h>
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_OMAP		1	/* in a TI OMAP core */
+#define CONFIG_OMAP34XX		1	/* which is a 34XX */
+#define CONFIG_OMAP3_3430SDP	1	/* working with SDP Rev2 */
+#define CONFIG_OMAP_COMMON
+
+#define CONFIG_SDRC	/* The chip has SDRC controller */
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/*
+ * NOTE:  these #defines presume standard SDP jumper settings.
+ * In particular:
+ *  - 26 MHz clock (not 19.2 or 38.4 MHz)
+ *  - Boot from 128MB NOR, not NAND or OneNAND
+ *
+ * At this writing, OMAP3 U-Boot support doesn't permit concurrent
+ * support for all the flash types the board supports.
+ */
+#define CONFIG_DISPLAY_CPUINFO		1
+#define CONFIG_DISPLAY_BOARDINFO	1
+
+/* Clock Defines */
+#define V_OSCK			26000000	/* Clock output from T2 */
+#define V_SCLK			(V_OSCK >> 1)
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+#define CONFIG_REVISION_TAG		1
+
+#define CONFIG_OF_LIBFDT		1
+
+/*
+ * Size of malloc() pool
+ * Total Size Environment - 256k
+ * Malloc - add 256k
+ */
+#define CONFIG_ENV_SIZE			(256 << 10)
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (256 << 10))
+
+/*--------------------------------------------------------------------------*/
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER		1
+
+/*
+ * serial port - NS16550 compatible
+ */
+#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+
+/* Original SDP u-boot used UART1 and thus J8 (innermost); that can be
+ * swapped with UART2 via jumpering.  Downsides of using J8:  it doesn't
+ * support UART boot (that's only for UART3); it prevents sharing a Linux
+ * kernel (LL_DEBUG_UART3) or filesystem (getty ttyS2) with most boards.
+ *
+ * UART boot uses UART3 on J9, and the SDP user's guide says to use
+ * that for console.  Downsides of using J9:  you can't use IRDA too;
+ * since UART3 isn't in the CORE power domain, it may be a bit less
+ * usable in certain PM-sensitive debug scenarios.
+ */
+#undef CONSOLE_J9			/* else J8/UART1 (innermost) */
+
+#ifdef CONSOLE_J9
+#define CONFIG_CONS_INDEX		3
+#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
+#define CONFIG_SERIAL3			3	/* UART3 */
+#else
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550_COM1		OMAP34XX_UART1
+#define CONFIG_SERIAL1			1	/* UART1 */
+#endif
+
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
+					115200}
+
+/*
+ * I2C for power management setup
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
+#define CONFIG_SYS_I2C_OMAP34XX
+
+/* OMITTED:  single 1 Gbit MT29F1G NAND flash */
+
+/*
+ * NOR boot support - single 1 Gbit PF48F6000M0 Strataflash
+ */
+#define CONFIG_SYS_FLASH_BASE		0x10000000
+#define CONFIG_FLASH_CFI_DRIVER		1	/* Use drivers/cfi_flash.c */
+#define CONFIG_SYS_FLASH_CFI		1	/* use CFI geometry data */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* ~10x faster writes */
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* hardware sector protection */
+#define CONFIG_SYS_FLASH_EMPTY_INFO	1	/* flinfo 'E' for empty */
+#define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_MAX_FLASH_BANKS      1	/* max number of flash banks */
+
+#define CONFIG_SYS_FLASH_CFI_WIDTH	2
+#define PHYS_FLASH_SIZE			(128 << 20)
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max sectors on one chip */
+
+/* OMITTED:  single 2 Gbit KFM2G16 OneNAND flash */
+
+#define CONFIG_ENV_IS_IN_FLASH		1
+#define CONFIG_SYS_ENV_SECT_SIZE	(256 << 10)
+#define CONFIG_ENV_OFFSET		CONFIG_SYS_ENV_SECT_SIZE
+#define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_ENV_SECT_SIZE)
+/*--------------------------------------------------------------------------*/
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+/* Enabled commands */
+#define CONFIG_CMD_DHCP		/* DHCP Support			*/
+#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
+#define CONFIG_CMD_FAT		/* FAT support			*/
+#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
+#define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
+#define CONFIG_CMD_MMC		/* MMC support			*/
+#define CONFIG_CMD_NET
+
+/* Disabled commands */
+#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
+#undef CONFIG_CMD_IMLS		/* List all found images	*/
+
+/*--------------------------------------------------------------------------*/
+/*
+ * MMC boot support
+ */
+
+#if defined(CONFIG_CMD_MMC)
+#define CONFIG_GENERIC_MMC		1
+#define CONFIG_MMC			1
+#define CONFIG_OMAP_HSMMC		1
+#define CONFIG_DOS_PARTITION		1
+#endif
+
+/*----------------------------------------------------------------------------
+ * SMSC9115 Ethernet from SMSC9118 family
+ *----------------------------------------------------------------------------
+ */
+#if defined(CONFIG_CMD_NET)
+
+#define CONFIG_LAN91C96
+#define CONFIG_LAN91C96_BASE	DEBUG_BASE
+#define CONFIG_LAN91C96_EXT_PHY
+
+#define CONFIG_BOOTP_SEND_HOSTNAME
+/*
+ * BOOTP fields
+ */
+#define CONFIG_BOOTP_SUBNETMASK		0x00000001
+#define CONFIG_BOOTP_GATEWAY		0x00000002
+#define CONFIG_BOOTP_HOSTNAME		0x00000004
+#define CONFIG_BOOTP_BOOTPATH		0x00000010
+#endif /* (CONFIG_CMD_NET) */
+
+/*
+ * Environment setup
+ *
+ * Default boot order:  mmc bootscript, MMC uImage, NOR image.
+ * Network booting environment must be configured at site.
+ */
+
+/* allow overwriting serial config and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x82000000\0" \
+	"console=ttyS0,115200n8\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"root=/dev/mmcblk0p2 rw " \
+		"rootfstype=ext3 rootwait\0" \
+	"norargs=setenv bootargs console=${console} " \
+		"root=/dev/mtdblock3 rw " \
+		"rootfstype=jffs2\0" \
+	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running bootscript from MMC/SD ...; " \
+		"autoscr ${loadaddr}\0" \
+	"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
+	"mmcboot=echo Booting from MMC/SD ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0" \
+	"norboot=echo Booting from NOR ...; " \
+		"run norargs; " \
+		"bootm 0x80000\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"if mmcinit; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loaduimage; then " \
+				"run mmcboot; " \
+			"else run norboot; " \
+			"fi; " \
+		"fi; " \
+	"else run norboot; fi"
+
+#define CONFIG_AUTO_COMPLETE		1
+
+/*--------------------------------------------------------------------------*/
+
+/*
+ * Miscellaneous configurable options
+ */
+
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT		"OMAP34XX SDP # "
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
+
+/* SDRAM Test range - start at 16 meg boundary -ends at 32Meg -
+ * a basic sanity check ONLY
+ * IF you would like to increase coverage, increase the end address
+ * or run the test with custom options
+ */
+#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0 + 0x01000000)
+#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + (32 << 20))
+
+/* Default load address */
+#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)
+
+/*--------------------------------------------------------------------------*/
+
+/*
+ * 3430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
+ * 32KHz clk, or from external sig. This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
+#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE	0x800
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+/*
+ * SDRAM Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
+#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
+
+/*--------------------------------------------------------------------------*/
+
+/*
+ * NOR FLASH usage ... default nCS0:
+ *  - one 256KB sector for U-Boot
+ *  - one 256KB sector for its parameters (not all used)
+ *  - eight sectors (2 MB) for kernel
+ *  - rest for JFFS2
+ */
+
+/* Monitor at start of flash */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)
+
+/*
+ * NAND FLASH usage ... default nCS1:
+ *  - four 128KB sectors for X-Loader
+ *  - four 128KB sectors for U-Boot
+ *  - two 128KB sector for its parameters
+ *  - 32 sectors (4 MB) for kernel
+ *  - rest for filesystem
+ */
+
+/*
+ * OneNAND FLASH usage ... default nCS2:
+ *  - four 128KB sectors for X-Loader
+ *  - two 128KB sectors for U-Boot
+ *  - one 128KB sector for its parameters
+ *  - sixteen sectors (2 MB) for kernel
+ *  - rest for filesystem
+ */
+
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
+#endif				/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/omap3_zoom1.h b/qemu/roms/u-boot/include/configs/omap3_zoom1.h
new file mode 100644
index 000000000..7c5540ff6
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/omap3_zoom1.h
@@ -0,0 +1,198 @@
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ * Nishanth Menon <nm@ti.com>
+ *
+ * Configuration settings for the TI OMAP3430 Zoom MDK board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_OMAP3_ZOOM1	1	/* working with Zoom MDK Rev1 */
+#define CONFIG_SYS_GENERIC_BOARD
+
+#define CONFIG_NAND
+#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+#include <asm/arch/omap3.h>
+#include <configs/ti_omap3_common.h>
+
+/* Remove SPL boot option - we do not support that on LDP yet */
+#undef CONFIG_SPL
+#undef CONFIG_SPL_FRAMEWORK
+#undef CONFIG_SPL_OS_BOOT
+
+/* Generic NAND definition conflicts with debug_base */
+#undef CONFIG_SYS_NAND_BASE
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO		1
+#define CONFIG_DISPLAY_BOARDINFO	1
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_REVISION_TAG		1
+
+#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
+
+/*
+ * Hardware drivers
+ */
+
+/* USB */
+#define CONFIG_MUSB_UDC			1
+#define CONFIG_USB_OMAP3		1
+#define CONFIG_TWL4030_USB		1
+
+/* USB device configuration */
+#define CONFIG_USB_DEVICE		1
+#define CONFIG_USB_TTY			1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
+/* Change these to suit your needs */
+#define CONFIG_USBD_VENDORID		0x0451
+#define CONFIG_USBD_PRODUCTID		0x5678
+#define CONFIG_USBD_MANUFACTURER	"Texas Instruments"
+#define CONFIG_USBD_PRODUCT_NAME	"Zoom1"
+
+#define MTDIDS_DEFAULT			"nand0=nand"
+#define MTDPARTS_DEFAULT		"mtdparts=nand:512k(x-loader),"\
+					"1920k(u-boot),128k(u-boot-env),"\
+					"4m(kernel),-(fs)"
+
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_CMD_NAND_LOCK_UNLOCK /* Enable lock/unlock support */
+#endif
+
+#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
+#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
+#undef CONFIG_CMD_IMI		/* iminfo			*/
+#undef CONFIG_CMD_IMLS		/* List all found images	*/
+#define CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot	*/
+#define CONFIG_CMD_NFS		/* NFS support			*/
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+
+#undef CONFIG_SYS_I2C_OMAP24XX
+#define CONFIG_SYS_I2C_OMAP34XX
+
+/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_LED		1
+
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
+							/* to access nand */
+#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
+							/* to access nand at */
+							/* CS0 */
+
+/* Environment information */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x82000000\0" \
+	"fdtaddr=0x80f80000\0" \
+	"bootfile=uImage\0" \
+	"fdtfile=omap3-ldp.dtb\0" \
+	"bootdir=/\0" \
+	"bootpart=0:1\0" \
+	"usbtty=cdc_acm\0" \
+	"console=ttyO2,115200n8\0" \
+	"mmcdev=0\0" \
+	"videomode=1024x768@60,vxres=1024,vyres=768\0" \
+	"videospec=omapfb:vram:2M,vram:4M\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"video=${videospec},mode:${videomode} " \
+		"root=/dev/mmcblk0p2 rw " \
+		"rootfstype=ext3 rootwait\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"video=${videospec},mode:${videomode} " \
+		"root=/dev/mtdblock4 rw " \
+		"rootfstype=jffs2\0" \
+	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source ${loadaddr}\0" \
+	"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
+	"loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
+	"loadzimage=setenv bootfile zImage; if run loadimage; then run loadfdt;fi\0"\
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0" \
+	"mmczboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootz ${loadaddr} - ${fdtaddr}\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nand read ${loadaddr} 280000 400000; " \
+		"bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loadimage; then " \
+				"run mmcboot; " \
+			"else if run loadzimage; then " \
+				"run mmczboot; " \
+			"else run nandboot; " \
+			"fi; fi;" \
+		"fi; " \
+	"else run nandboot; fi"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_MEMTEST_START	(PHYS_SDRAM_1)	/* memtest */
+#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_2 + \
+					0x01F00000) /* 31MB */
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+
+/* Configure the PISMO */
+#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
+#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M
+
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_SYS_FLASH_BASE		PISMO1_NAND_BASE
+#endif
+
+/* Monitor at start of flash */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
+
+#define CONFIG_ENV_IS_IN_NAND		1
+#define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
+#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
+
+#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
+#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
+#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
+
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
+#ifdef CONFIG_CMD_NET
+/* Ethernet (LAN9211 from SMSC9118 family) */
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_32_BIT
+#define CONFIG_SMC911X_BASE		DEBUG_BASE
+
+#endif
+
+#endif				/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/omap4_panda.h b/qemu/roms/u-boot/include/configs/omap4_panda.h
new file mode 100644
index 000000000..7378acdb2
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/omap4_panda.h
@@ -0,0 +1,50 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated.
+ * Steve Sakoman  <steve@sakoman.com>
+ *
+ * Configuration settings for the TI OMAP4 Panda board.
+ * See ti_omap4_common.h for OMAP4 common part
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_PANDA_H
+#define __CONFIG_PANDA_H
+
+/*
+ * High Level Configuration Options
+ */
+
+/* USB UHH support options */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_HOST
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_OMAP
+#define CONFIG_USB_STORAGE
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
+
+#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 1
+#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 62
+
+/* USB Networking options */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_SMSC95XX
+
+#define CONFIG_UBOOT_ENABLE_PADS_ALL
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+
+#include <configs/ti_omap4_common.h>
+#define CONFIG_CMD_NET
+
+/* GPIO */
+#define CONFIG_CMD_GPIO
+
+/* ENV related config options */
+#define CONFIG_ENV_IS_NOWHERE
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+#endif /* __CONFIG_PANDA_H */
diff --git a/qemu/roms/u-boot/include/configs/omap4_sdp4430.h b/qemu/roms/u-boot/include/configs/omap4_sdp4430.h
new file mode 100644
index 000000000..a83797454
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/omap4_sdp4430.h
@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated.
+ * Aneesh V       <aneesh@ti.com>
+ * Steve Sakoman  <steve@sakoman.com>
+ *
+ * Configuration settings for the TI SDP4430 board.
+ * See ti_omap4_common.h for OMAP4 common part
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_SDP4430_H
+#define __CONFIG_SDP4430_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_4430SDP		1	/* working with SDP */
+#define CONFIG_MACH_TYPE	MACH_TYPE_OMAP_4430SDP
+
+#include <configs/ti_omap4_common.h>
+
+/* Battery Charger */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_CMD_BAT			1
+#endif
+
+/* ENV related config options */
+#define CONFIG_ENV_IS_IN_MMC		1
+#define CONFIG_SYS_MMC_ENV_DEV		1	/* SLOT2: eMMC(1) */
+#define CONFIG_ENV_OFFSET		0xE0000
+#define CONFIG_CMD_SAVEENV
+
+#endif /* __CONFIG_SDP4430_H */
diff --git a/qemu/roms/u-boot/include/configs/omap5912osk.h b/qemu/roms/u-boot/include/configs/omap5912osk.h
new file mode 100644
index 000000000..376dfdb14
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/omap5912osk.h
@@ -0,0 +1,174 @@
+/*
+ * (C) Copyright 2003
+ * Texas Instruments.
+ * Kshitij Gupta <kshitij@ti.com>
+ * Configuation settings for the TI OMAP Innovator board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARM926EJS	1	/* This is an arm926ejs CPU core  */
+#define CONFIG_OMAP	1			/* in a TI OMAP core    */
+#define CONFIG_OMAP1610	1		/* 5912 is same as 1610  */
+#define CONFIG_OSK_OMAP5912	1	/*  a OSK Board  */
+
+#define CONFIG_DISPLAY_CPUINFO	1	/* display cpu info (and speed)	*/
+#define CONFIG_DISPLAY_BOARDINFO 1	/* display board info		*/
+
+/* input clock of PLL */
+/* the OMAP5912 OSK has 12MHz input clock */
+#define CONFIG_SYS_CLK_FREQ	12000000
+
+#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs  */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG      1       /* Required for ramdisk support */
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + 128*1024)
+
+/*
+ * Hardware drivers
+ */
+/*
+*/
+#define CONFIG_LAN91C96
+#define CONFIG_LAN91C96_BASE 0x04800300
+#define CONFIG_LAN91C96_EXT_PHY
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK	(48000000)	/* can be 12M/32Khz or 48Mhz */
+#define CONFIG_SYS_NS16550_COM1	0xfffb0000	/* uart1, bluetooth uart
+						on helen */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL1	1	/* we use SERIAL 1 on OMAP5912 OSK */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE	115200
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+
+
+#include <configs/omap1510.h>
+
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTARGS	"mem=32M console=ttyS0,115200n8 noinitrd \
+				root=/dev/nfs rw nfsroot=157.87.82.48:\
+				/home/mwd/myfs/target ip=dhcp"
+#define CONFIG_NETMASK	255.255.254.0	/* talk on MY local net */
+#define CONFIG_IPADDR	156.117.97.156	/* static IP I currently own */
+#define CONFIG_SERVERIP	156.117.97.139	/* current IP of my dev pc */
+#define CONFIG_BOOTFILE	"uImage"	/* file to load */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP	/* undef to save memory     */
+#define CONFIG_SYS_PROMPT	"OMAP5912 OSK # "	/* Monitor Command Prompt   */
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size  */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args   */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
+
+#define CONFIG_SYS_MEMTEST_START	0x10000000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END	0x12000000	/* 32 MB in DRAM    */
+
+#define CONFIG_SYS_LOAD_ADDR	0x10000000	/* default load address */
+
+/* The 1610 has 6 timers, they can be driven by the RefClk (12Mhz) or by
+ * DPLL1. This time is further subdivided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE	0xFFFEC500	/* use timer 1 */
+#define CONFIG_SYS_PTV		7	/* 2^(PTV+1), divide by 256 */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1	/* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1		0x10000000	/* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x02000000	/* 32 MB */
+
+#define PHYS_FLASH_1		0x00000000	/* Flash Bank #1 */
+#define PHYS_FLASH_2		0x01000000	/* Flash Bank #2 */
+
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+
+#define CONFIG_SYS_MONITOR_BASE       CONFIG_SYS_FLASH_BASE  /* Monitor at beginning of flash */
+
+#define PHYS_SRAM		0x20000000
+
+/*-----------------------------------------------------------------------
+ * FLASH driver setup
+ */
+#define CONFIG_SYS_FLASH_CFI          1       /* Flash memory is CFI compliant */
+#define CONFIG_FLASH_CFI_DRIVER   1       /* Use drivers/mtd/cfi_flash.c */
+
+#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
+#define PHYS_FLASH_SIZE	0x02000000	/* 32MB */
+#define CONFIG_SYS_MAX_FLASH_SECT	(259)	/* max number of sectors on one chip */
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE     1       /* Use buffered writes (~10x faster) */
+#define CONFIG_SYS_FLASH_PROTECTION   1       /* Use hardware sector protection */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+/* timeout values are in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(20*CONFIG_SYS_HZ)	/* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(20*CONFIG_SYS_HZ)	/* Timeout for Flash Write */
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+/* addr of environment */
+#define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+
+#define CONFIG_ENV_SIZE		0x20000	/* Total Size of Environment Sector */
+#define CONFIG_ENV_OFFSET	0x40000	/* environment starts here  */
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR        PHYS_SRAM
+#define CONFIG_SYS_INIT_RAM_SIZE        (250 * 1024)
+#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE)
+
+#endif							/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/omap5_uevm.h b/qemu/roms/u-boot/include/configs/omap5_uevm.h
new file mode 100644
index 000000000..7e2ecd53f
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/omap5_uevm.h
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2013
+ * Texas Instruments Incorporated.
+ * Sricharan R	  <r.sricharan@ti.com>
+ *
+ * Configuration settings for the TI EVM5430 board.
+ * See ti_omap5_common.h for omap5 common settings.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_OMAP5_EVM_H
+#define __CONFIG_OMAP5_EVM_H
+
+/* Define the default GPT table for eMMC */
+#define PARTS_DEFAULT \
+	"uuid_disk=${uuid_gpt_disk};" \
+	"name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}"
+
+#include <configs/ti_omap5_common.h>
+
+#define CONFIG_CONS_INDEX		3
+#define CONFIG_SYS_NS16550_COM3		UART3_BASE
+#define CONFIG_BAUDRATE			115200
+
+/* MMC ENV related defines */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV		1	/* SLOT2: eMMC(1) */
+#define CONFIG_ENV_SIZE			(128 << 10)
+#define CONFIG_ENV_OFFSET		0xE0000
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_CMD_SAVEENV
+
+/* Enhance our eMMC support / experience. */
+#define CONFIG_CMD_GPT
+#define CONFIG_EFI_PARTITION
+#define CONFIG_PARTITION_UUIDS
+#define CONFIG_CMD_PART
+#define CONFIG_HSMMC2_8BIT
+#define CONFIG_SUPPORT_EMMC_BOOT
+
+/* Required support for the TCA642X GPIO we have on the uEVM */
+#define CONFIG_TCA642X
+#define CONFIG_CMD_TCA642X
+#define CONFIG_SYS_I2C_TCA642X_BUS_NUM 4
+#define CONFIG_SYS_I2C_TCA642X_ADDR 0x22
+
+/* USB UHH support options */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_HOST
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_OMAP
+#define CONFIG_USB_STORAGE
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+
+#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 80
+#define CONFIG_OMAP_EHCI_PHY3_RESET_GPIO 79
+
+/* Enabled commands */
+#define CONFIG_CMD_DHCP		/* DHCP Support			*/
+#define CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot	*/
+#define CONFIG_CMD_NFS		/* NFS support			*/
+
+/* USB Networking options */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_SMSC95XX
+
+#define CONSOLEDEV		"ttyO2"
+
+/* Max time to hold reset on this board, see doc/README.omap-reset-time */
+#define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC	16296
+
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_CMD_SCSI
+#define CONFIG_LIBATA
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	1
+#define CONFIG_SYS_SCSI_MAX_LUN		1
+#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+						CONFIG_SYS_SCSI_MAX_LUN)
+
+#endif /* __CONFIG_OMAP5_EVM_H */
diff --git a/qemu/roms/u-boot/include/configs/openrd.h b/qemu/roms/u-boot/include/configs/openrd.h
new file mode 100644
index 000000000..8fab6e63e
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/openrd.h
@@ -0,0 +1,126 @@
+/*
+ * (C) Copyright 2009
+ * Net Insight <www.netinsight.net>
+ * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
+ *
+ * Based on sheevaplug.h:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CONFIG_OPENRD_H
+#define _CONFIG_OPENRD_H
+
+/*
+ * Version number information
+ */
+#ifdef CONFIG_BOARD_IS_OPENRD_ULTIMATE
+# define CONFIG_IDENT_STRING	"\nOpenRD-Ultimate"
+#else
+# ifdef CONFIG_BOARD_IS_OPENRD_CLIENT
+#  define CONFIG_IDENT_STRING	"\nOpenRD-Client"
+# else
+#  ifdef CONFIG_BOARD_IS_OPENRD_BASE
+#   define CONFIG_IDENT_STRING	"\nOpenRD-Base"
+#  else
+#   error Unknown OpenRD board specified
+#  endif
+# endif
+#endif
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_SHEEVA_88SV131	1	/* CPU Core subversion */
+#define CONFIG_KIRKWOOD		1	/* SOC Family Name */
+#define CONFIG_KW88F6281	1	/* SOC Name */
+#define CONFIG_MACH_OPENRD_BASE	/* Machine type */
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
+#define CONFIG_SYS_MVFS
+#include <config_cmd_default.h>
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_IDE
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/*
+ *  Environment variables configurations
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_ENV_IS_IN_NAND		1
+#define CONFIG_ENV_SECT_SIZE		0x20000	/* 128K */
+#else
+#define CONFIG_ENV_IS_NOWHERE		1	/* if env in SDRAM */
+#endif
+/*
+ * max 4k env size is enough, but in case of nand
+ * it has to be rounded to sector size
+ */
+#define CONFIG_ENV_SIZE			0x20000	/* 128k */
+#define CONFIG_ENV_ADDR			0x60000
+#define CONFIG_ENV_OFFSET		0x60000	/* env starts here */
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_BOOTCOMMAND		"${x_bootcmd_kernel}; "	\
+	"setenv bootargs ${x_bootargs} ${x_bootargs_root}; "	\
+	"${x_bootcmd_usb}; bootm 0x6400000;"
+
+#define MTDIDS_DEFAULT		"nand0=nand_mtd"
+#define MTDPARTS_DEFAULT	"mtdparts=nand_mtd:0x100000@0x000000(uboot),"\
+	"0x400000@0x100000(uImage),"\
+	"0x1fb00000@0x500000(rootfs)"
+
+#define CONFIG_EXTRA_ENV_SETTINGS	"x_bootargs=console"		\
+	"=ttyS0,115200 "MTDPARTS_DEFAULT " rw ubi.mtd=2,2048\0"		\
+	"x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0"	\
+	"x_bootcmd_usb=usb start\0"					\
+	"x_bootargs_root=root=ubi0:rootfs rootfstype=ubifs\0"		\
+	"mtdids="MTDIDS_DEFAULT"\0"					\
+	"mtdparts="MTDPARTS_DEFAULT"\0"
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+# ifdef CONFIG_BOARD_IS_OPENRD_BASE
+#  define CONFIG_MVGBE_PORTS	{1, 0}	/* enable port 0 only */
+# else
+#  define CONFIG_MVGBE_PORTS	{1, 1}	/* enable both ports */
+# endif
+# ifdef CONFIG_BOARD_IS_OPENRD_ULTIMATE
+#  define CONFIG_PHY_BASE_ADR	0x0
+#  define PHY_NO		"88E1121"
+# else
+#  define CONFIG_PHY_BASE_ADR	0x8
+#  define PHY_NO		"88E1116"
+# endif
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * SATA Driver configuration
+ */
+#ifdef CONFIG_MVSATA_IDE
+#define CONFIG_SYS_ATA_IDE0_OFFSET	MV_SATA_PORT0_OFFSET
+#define CONFIG_SYS_ATA_IDE1_OFFSET	MV_SATA_PORT1_OFFSET
+#endif /*CONFIG_MVSATA_IDE*/
+
+#endif /* _CONFIG_OPENRD_BASE_H */
diff --git a/qemu/roms/u-boot/include/configs/openrisc-generic.h b/qemu/roms/u-boot/include/configs/openrisc-generic.h
new file mode 100644
index 000000000..d4de3c355
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/openrisc-generic.h
@@ -0,0 +1,140 @@
+/*
+ * (C) Copyright 2011, Stefan Kristiansson, stefan.kristianssons@saunalahti.fi
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * BOARD/CPU
+ */
+
+#define CONFIG_SYS_CLK_FREQ		50000000
+#define CONFIG_SYS_RESET_ADDR		0x00000100
+
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_SIZE		0x02000000
+
+#define CONFIG_SYS_CACHELINE_SIZE	16
+
+#define CONFIG_SYS_UART_BASE		0x90000000
+#define CONFIG_SYS_UART_FREQ		CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_UART_BAUD		115200
+
+#define CONFIG_BOARD_NAME		"OpenRISC Generic"
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_MAX_FLASH_SECT	0
+
+/*
+ * SERIAL
+ */
+# define CONFIG_SYS_NS16550
+# define CONFIG_SYS_NS16550_SERIAL
+# define CONFIG_SYS_NS16550_REG_SIZE	1
+# define CONFIG_CONS_INDEX		1
+# define CONFIG_SYS_NS16550_COM1	(0x90000000)
+# define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_CLK_FREQ
+
+#define CONFIG_BAUDRATE			CONFIG_SYS_UART_BAUD
+#define CONFIG_SYS_BAUDRATE_TABLE	{CONFIG_BAUDRATE}
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	/* Suppress console info */
+#define CONSOLE_ARG			"console=console=ttyS0,115200\0"
+
+/*
+ * Ethernet
+ */
+#define CONFIG_ETHOC
+#define CONFIG_SYS_ETHOC_BASE		0x92000000
+
+#define CONFIG_BOOTFILE			"boot.img"
+#define CONFIG_LOADADDR			0x100000 /* 1MB mark */
+
+/*
+ * TIMER
+ */
+#define CONFIG_SYS_OPENRISC_TMR_HZ	100
+
+/*
+ * Memory organisation:
+ *
+ * RAM start ---------------------------
+ *           | ...                     |
+ *           ---------------------------
+ *           | Stack                   |
+ *           ---------------------------
+ *           | Global data             |
+ *           ---------------------------
+ *           | Environment             |
+ *           ---------------------------
+ *           | Monitor                 |
+ * RAM end   ---------------------------
+ */
+/* We're running in RAM */
+#define CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_SYS_MONITOR_LEN	0x40000	/* Reserve 256k */
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_SDRAM_BASE + \
+				CONFIG_SYS_SDRAM_SIZE - \
+				CONFIG_SYS_MONITOR_LEN)
+
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE		0x20000 /* Total Size of Environment, 128KB */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
+
+/*
+ * Global data object and stack pointer
+ */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_ENV_ADDR \
+					- GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_ADDR	CONFIG_SYS_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SYS_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+#define CONFIG_SYS_STACK_LENGTH		0x10000 /* 64KB */
+#define CONFIG_SYS_MALLOC_LEN		0x400000 /* 4MB */
+#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_INIT_SP_OFFSET \
+					- CONFIG_SYS_STACK_LENGTH \
+					- CONFIG_SYS_MALLOC_LEN)
+/*
+ * MISC
+ */
+#define CONFIG_SYS_LONGHELP		/* Provide extended help */
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O buf size */
+#define CONFIG_SYS_MAXARGS		16	/* Max command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Bootarg buf size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + \
+					16)	/* Print buf size */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE + 0x2000)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_INIT_SP_ADDR - 0x20000)
+#define CONFIG_CMDLINE_EDITING
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_BSP
+
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_LMB
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/origen.h b/qemu/roms/u-boot/include/configs/origen.h
new file mode 100644
index 000000000..82583382f
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/origen.h
@@ -0,0 +1,98 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics
+ *
+ * Configuration settings for the SAMSUNG ORIGEN (EXYNOS4210) board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_ORIGEN_H
+#define __CONFIG_ORIGEN_H
+
+#include <configs/exynos4-dt.h>
+
+#define CONFIG_SYS_PROMPT		"ORIGEN # "
+
+#undef CONFIG_DEFAULT_DEVICE_TREE
+#define CONFIG_DEFAULT_DEVICE_TREE	exynos4210-origen
+
+/* High Level Configuration Options */
+#define CONFIG_EXYNOS4210		1	/* which is a EXYNOS4210 SoC */
+#define CONFIG_ORIGEN			1	/* working with ORIGEN*/
+
+#define CONFIG_SYS_DCACHE_OFF		1
+
+/* ORIGEN has 4 bank of DRAM */
+#define CONFIG_NR_DRAM_BANKS		4
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define PHYS_SDRAM_1			CONFIG_SYS_SDRAM_BASE
+#define SDRAM_BANK_SIZE			(256 << 20)	/* 256 MB */
+
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x6000000)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x3E00000)
+
+#define CONFIG_SYS_TEXT_BASE		0x43E00000
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_ORIGEN
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (80 * SZ_1M))
+
+/* select serial console configuration */
+#define CONFIG_SERIAL2
+#define CONFIG_BAUDRATE			115200
+
+/* Console configuration */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC1,115200n8\0"
+
+#define CONFIG_SYS_MEM_TOP_HIDE	(1 << 20)	/* ram console */
+
+#define CONFIG_SYS_MONITOR_BASE	0x00000000
+
+/* Power Down Modes */
+#define S5P_CHECK_SLEEP			0x00000BAD
+#define S5P_CHECK_DIDLE			0xBAD00000
+#define S5P_CHECK_LPA			0xABAD0000
+
+#undef CONFIG_CMD_PING
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_DHCP
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+
+/* MMC SPL */
+#define CONFIG_SPL
+#define COPY_BL2_FNPTR_ADDR	0x02020030
+#define CONFIG_SPL_TEXT_BASE	0x02021410
+
+#define CONFIG_BOOTCOMMAND	"fatload mmc 0 40007000 uImage; bootm 40007000"
+
+#define CONFIG_IDENT_STRING		" for ORIGEN"
+
+#define CONFIG_CLK_1000_400_200
+
+/* MIU (Memory Interleaving Unit) */
+#define CONFIG_MIU_2BIT_21_7_INTERLEAVED
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_ENV_SIZE			(16 << 10)	/* 16 KB */
+#define RESERVE_BLOCK_SIZE		(512)
+#define BL1_SIZE			(16 << 10) /*16 K reserved for BL1*/
+#define CONFIG_ENV_OFFSET		(RESERVE_BLOCK_SIZE + BL1_SIZE)
+
+#define CONFIG_SPL_LDSCRIPT	"board/samsung/common/exynos-uboot-spl.lds"
+#define CONFIG_SPL_MAX_FOOTPRINT	(14 * 1024)
+
+#define CONFIG_SYS_INIT_SP_ADDR		0x02040000
+
+/* U-boot copy size from boot Media to DRAM.*/
+#define COPY_BL2_SIZE		0x80000
+#define BL2_START_OFFSET	((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512)
+#define BL2_SIZE_BLOC_COUNT	(COPY_BL2_SIZE/512)
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/otc570.h b/qemu/roms/u-boot/include/configs/otc570.h
new file mode 100644
index 000000000..629967d05
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/otc570.h
@@ -0,0 +1,258 @@
+/*
+ * (C) Copyright 2010-2011
+ * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
+ * esd electronic system design gmbh <www.esd.eu>
+ *
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * Configuation settings for the esd OTC570 board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * SoC must be defined first, before hardware.h is included.
+ * In this case SoC is defined in boards.cfg.
+ */
+#include <asm/hardware.h>
+
+/*
+ * Warning: changing CONFIG_SYS_TEXT_BASE requires
+ * adapting the initial boot program.
+ * Since the linker has to swallow that define, we must use a pure
+ * hex number here!
+ */
+#define CONFIG_SYS_TEXT_BASE		0x20002000
+
+/*
+ * since a number of boards are not being listed in linux
+ * arch/arm/tools/mach-types any more, the mach-types have to be
+ * defined here
+ */
+#define MACH_TYPE_OTC570		2166
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768	/* 32.768 kHz crystal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	16000000/* 16.0 MHz crystal */
+
+/* Misc CPU related */
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_BOARD_EARLY_INIT_F		/* call board_early_init_f() */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_SERIAL_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
+#define CONFIG_MISC_INIT_R			/* Call misc_init_r */
+
+#define CONFIG_DISPLAY_BOARDINFO		/* call checkboard() */
+#define CONFIG_DISPLAY_CPUINFO			/* display cpu info and speed */
+#define CONFIG_PREBOOT				/* enable preboot variable */
+
+/*
+ * Hardware drivers
+ */
+
+/* required until arch/arm/include/asm/arch-at91/at91sam9263.h is reworked */
+#define ATMEL_PMC_UHP			AT91SAM926x_PMC_UHP
+
+/* general purpose I/O */
+#define CONFIG_AT91_GPIO
+
+/* Console output */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
+#define CONFIG_USART_ID			ATMEL_ID_SYS
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+/* LCD */
+#define CONFIG_LCD
+#undef CONFIG_SPLASH_SCREEN
+
+#ifdef CONFIG_LCD
+# define LCD_BPP			LCD_COLOR8
+
+# ifndef CONFIG_SPLASH_SCREEN
+#  define CONFIG_LCD_LOGO
+#  define CONFIG_LCD_INFO
+#  undef CONFIG_LCD_INFO_BELOW_LOGO
+# endif /* CONFIG_SPLASH_SCREEN */
+
+# undef LCD_TEST_PATTERN
+# define CONFIG_SYS_WHITE_ON_BLACK
+# define CONFIG_ATMEL_LCD
+# define CONFIG_SYS_CONSOLE_IS_IN_ENV
+# define CONFIG_OTC570_LCD_BASE		(CONFIG_SYS_SDRAM_BASE + 0x03fa5000)
+# define CONFIG_CMD_BMP
+#endif /* CONFIG_LCD */
+
+/* RTC and I2C stuff */
+#define CONFIG_RTC_DS1338
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68
+
+#define CONFIG_SYS_I2C
+#define	CONFIG_SYS_I2C_SOFT	/* I2C bit-banged	*/
+#ifdef CONFIG_SYS_I2C_SOFT
+#define CONFIG_SYS_I2C_SOFT_SPEED	100000
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0x7F
+
+/* Configure data and clock pins for pio */
+# define I2C_INIT { \
+	at91_set_pio_output(AT91_PIO_PORTB, 4, 0); \
+	at91_set_pio_output(AT91_PIO_PORTB, 5, 0); \
+}
+# define I2C_SOFT_DECLARATIONS
+/* Configure data pin as output */
+# define I2C_ACTIVE		at91_set_pio_output(AT91_PIO_PORTB, 4, 0)
+/* Configure data pin as input */
+# define I2C_TRISTATE		at91_set_pio_input(AT91_PIO_PORTB, 4, 0)
+/* Read data pin */
+# define I2C_READ		at91_get_pio_value(AT91_PIO_PORTB, 4)
+/* Set data pin */
+# define I2C_SDA(bit)		at91_set_pio_value(AT91_PIO_PORTB, 4, bit)
+/* Set clock pin */
+# define I2C_SCL(bit)		at91_set_pio_value(AT91_PIO_PORTB, 5, bit)
+# define I2C_DELAY		udelay(2) /* 1/4 I2C clock duration */
+#endif /* CONFIG_SYS_I2C_SOFT */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_DATE
+
+/* LED */
+#define CONFIG_AT91_LED
+
+/*
+ * SDRAM: 1 bank, min 32, max 128 MB
+ * Initialized before u-boot gets started.
+ */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE		0x20000000 /* ATMEL_BASE_CS1 */
+#define CONFIG_SYS_SDRAM_SIZE		0x04000000
+
+#define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE + 0x00100000)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x01E00000)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x00100000)
+
+/*
+ * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
+ * leaving the correct space for initial global data structure above
+ * that address while providing maximum stack area below.
+ */
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(ATMEL_BASE_SRAM0 + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+/* DataFlash */
+#ifdef CONFIG_SYS_USE_DATAFLASH
+# define CONFIG_ATMEL_DATAFLASH_SPI
+# define CONFIG_HAS_DATAFLASH
+# define CONFIG_SYS_SPI_WRITE_TOUT		(5 * CONFIG_SYS_HZ)
+# define CONFIG_SYS_MAX_DATAFLASH_BANKS		1
+# define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
+# define AT91_SPI_CLK				15000000
+# define DATAFLASH_TCSS				(0x1a << 16)
+# define DATAFLASH_TCHS				(0x1 << 24)
+#endif
+
+/* NOR flash is not populated, disable it */
+#define CONFIG_SYS_NO_FLASH
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+# define CONFIG_NAND_ATMEL
+# define CONFIG_SYS_MAX_NAND_DEVICE		1
+# define CONFIG_SYS_NAND_BASE			0x40000000 /* ATMEL_BASE_CS3 */
+# define CONFIG_SYS_NAND_DBW_8
+# define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
+# define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
+# define CONFIG_SYS_NAND_ENABLE_PIN		GPIO_PIN_PD(15)
+# define CONFIG_SYS_NAND_READY_PIN		GPIO_PIN_PA(22)
+#endif
+
+/* Ethernet */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_FIT
+#define CONFIG_NET_RETRY_COUNT			20
+#undef CONFIG_RESET_PHY_R
+
+/* USB */
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00a00000
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9263"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_FAT
+
+/* CAN */
+#define CONFIG_AT91_CAN
+
+/* hw-controller addresses */
+#define CONFIG_ET1100_BASE		0x70000000 /* ATMEL_BASE_CS6 */
+
+#ifdef CONFIG_SYS_USE_DATAFLASH
+
+/* bootstrap + u-boot + env in dataflash on CS0 */
+# define CONFIG_ENV_IS_IN_DATAFLASH
+# define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \
+					0x8400)
+# define CONFIG_ENV_OFFSET		0x4200
+# define CONFIG_ENV_ADDR		(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \
+					CONFIG_ENV_OFFSET)
+# define CONFIG_ENV_SIZE		0x4200
+
+#elif CONFIG_SYS_USE_NANDFLASH
+
+/* bootstrap + u-boot + env + linux in nandflash */
+# define CONFIG_ENV_IS_IN_NAND		1
+# define CONFIG_ENV_OFFSET		0xC0000
+# define CONFIG_ENV_SIZE		0x20000
+
+#endif
+
+#define CONFIG_SYS_CBSIZE		512
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + \
+					128*1024, 0x1000)
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/p1_p2_rdb_pc.h b/qemu/roms/u-boot/include/configs/p1_p2_rdb_pc.h
new file mode 100644
index 000000000..56b638e23
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/p1_p2_rdb_pc.h
@@ -0,0 +1,1062 @@
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * QorIQ RDB boards configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+
+#ifdef CONFIG_36BIT
+#define CONFIG_PHYS_64BIT
+#endif
+
+#if defined(CONFIG_P1020MBG)
+#define CONFIG_BOARDNAME "P1020MBG-PC"
+#define CONFIG_P1020
+#define CONFIG_VSC7385_ENET
+#define CONFIG_SLIC
+#define __SW_BOOT_MASK		0x03
+#define __SW_BOOT_NOR		0xe4
+#define __SW_BOOT_SD		0x54
+#define CONFIG_SYS_L2_SIZE	(256 << 10)
+#endif
+
+#if defined(CONFIG_P1020UTM)
+#define CONFIG_BOARDNAME "P1020UTM-PC"
+#define CONFIG_P1020
+#define __SW_BOOT_MASK		0x03
+#define __SW_BOOT_NOR		0xe0
+#define __SW_BOOT_SD		0x50
+#define CONFIG_SYS_L2_SIZE	(256 << 10)
+#endif
+
+#if defined(CONFIG_P1020RDB_PC)
+#define CONFIG_BOARDNAME "P1020RDB-PC"
+#define CONFIG_NAND_FSL_ELBC
+#define CONFIG_P1020
+#define CONFIG_SPI_FLASH
+#define CONFIG_VSC7385_ENET
+#define CONFIG_SLIC
+#define __SW_BOOT_MASK		0x03
+#define __SW_BOOT_NOR		0x5c
+#define __SW_BOOT_SPI		0x1c
+#define __SW_BOOT_SD		0x9c
+#define __SW_BOOT_NAND		0xec
+#define __SW_BOOT_PCIE		0x6c
+#define CONFIG_SYS_L2_SIZE	(256 << 10)
+#endif
+
+/*
+ * P1020RDB-PD board has user selectable switches for evaluating different
+ * frequency and boot options for the P1020 device. The table that
+ * follow describe the available options. The front six binary number was in
+ * accordance with SW3[1:6].
+ * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off
+ * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off
+ * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off
+ * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off
+ * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off
+ * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off
+ * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off
+ */
+#if defined(CONFIG_P1020RDB_PD)
+#define CONFIG_BOARDNAME "P1020RDB-PD"
+#define CONFIG_NAND_FSL_ELBC
+#define CONFIG_P1020
+#define CONFIG_SPI_FLASH
+#define CONFIG_VSC7385_ENET
+#define CONFIG_SLIC
+#define __SW_BOOT_MASK		0x03
+#define __SW_BOOT_NOR		0x64
+#define __SW_BOOT_SPI		0x34
+#define __SW_BOOT_SD		0x24
+#define __SW_BOOT_NAND		0x44
+#define __SW_BOOT_PCIE		0x74
+#define CONFIG_SYS_L2_SIZE	(256 << 10)
+#endif
+
+#if defined(CONFIG_P1021RDB)
+#define CONFIG_BOARDNAME "P1021RDB-PC"
+#define CONFIG_NAND_FSL_ELBC
+#define CONFIG_P1021
+#define CONFIG_QE
+#define CONFIG_SPI_FLASH
+#define CONFIG_VSC7385_ENET
+#define CONFIG_SYS_LBC_LBCR	0x00080000	/* Implement conversion of
+						addresses in the LBC */
+#define __SW_BOOT_MASK		0x03
+#define __SW_BOOT_NOR		0x5c
+#define __SW_BOOT_SPI		0x1c
+#define __SW_BOOT_SD		0x9c
+#define __SW_BOOT_NAND		0xec
+#define __SW_BOOT_PCIE		0x6c
+#define CONFIG_SYS_L2_SIZE	(256 << 10)
+#endif
+
+#if defined(CONFIG_P1024RDB)
+#define CONFIG_BOARDNAME "P1024RDB"
+#define CONFIG_NAND_FSL_ELBC
+#define CONFIG_P1024
+#define CONFIG_SLIC
+#define CONFIG_SPI_FLASH
+#define __SW_BOOT_MASK		0xf3
+#define __SW_BOOT_NOR		0x00
+#define __SW_BOOT_SPI		0x08
+#define __SW_BOOT_SD		0x04
+#define __SW_BOOT_NAND		0x0c
+#define CONFIG_SYS_L2_SIZE	(256 << 10)
+#endif
+
+#if defined(CONFIG_P1025RDB)
+#define CONFIG_BOARDNAME "P1025RDB"
+#define CONFIG_NAND_FSL_ELBC
+#define CONFIG_P1025
+#define CONFIG_QE
+#define CONFIG_SLIC
+#define CONFIG_SPI_FLASH
+
+#define CONFIG_SYS_LBC_LBCR	0x00080000	/* Implement conversion of
+						addresses in the LBC */
+#define __SW_BOOT_MASK		0xf3
+#define __SW_BOOT_NOR		0x00
+#define __SW_BOOT_SPI		0x08
+#define __SW_BOOT_SD		0x04
+#define __SW_BOOT_NAND		0x0c
+#define CONFIG_SYS_L2_SIZE	(256 << 10)
+#endif
+
+#if defined(CONFIG_P2020RDB)
+#define CONFIG_BOARDNAME "P2020RDB-PCA"
+#define CONFIG_NAND_FSL_ELBC
+#define CONFIG_P2020
+#define CONFIG_SPI_FLASH
+#define CONFIG_VSC7385_ENET
+#define __SW_BOOT_MASK		0x03
+#define __SW_BOOT_NOR		0xc8
+#define __SW_BOOT_SPI		0x28
+#define __SW_BOOT_SD		0x68 /* or 0x18 */
+#define __SW_BOOT_NAND		0xe8
+#define __SW_BOOT_PCIE		0xa8
+#define CONFIG_SYS_L2_SIZE	(512 << 10)
+#endif
+
+#ifdef CONFIG_SDCARD
+#define CONFIG_SPL
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_MMC_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_FSL_LAW                 /* Use common FSL init code */
+#define CONFIG_SYS_TEXT_BASE		0x11001000
+#define CONFIG_SPL_TEXT_BASE		0xf8f81000
+#define CONFIG_SPL_PAD_TO		0x20000
+#define CONFIG_SPL_MAX_SIZE		(128 * 1024)
+#define CONFIG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_DST	(0x11000000)
+#define CONFIG_SYS_MMC_U_BOOT_START	(0x11000000)
+#define CONFIG_SYS_MMC_U_BOOT_OFFS	(128 << 10)
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#define CONFIG_SPL_MMC_BOOT
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_COMMON_INIT_DDR
+#endif
+#endif
+
+#ifdef CONFIG_SPIFLASH
+#define CONFIG_SPL
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_FSL_LAW         /* Use common FSL init code */
+#define CONFIG_SYS_TEXT_BASE		0x11001000
+#define CONFIG_SPL_TEXT_BASE		0xf8f81000
+#define CONFIG_SPL_PAD_TO		0x20000
+#define CONFIG_SPL_MAX_SIZE		(128 * 1024)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE	(768 << 10)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST		(0x11000000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_START	(0x11000000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS	(128 << 10)
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#define CONFIG_SPL_SPI_BOOT
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_COMMON_INIT_DDR
+#endif
+#endif
+
+#ifdef CONFIG_NAND
+#define CONFIG_SPL
+#define CONFIG_TPL
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SPL_NAND_BOOT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_NAND_INIT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SPL_MAX_SIZE		(128 << 10)
+#define CONFIG_SPL_TEXT_BASE		0xf8f81000
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(832 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	(0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_START	(0x11000000)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	((128 + 128) << 10)
+#elif defined(CONFIG_SPL_BUILD)
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SPL_TEXT_BASE		0xff800000
+#define CONFIG_SPL_MAX_SIZE		4096
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(128 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	0xf8f80000
+#define CONFIG_SYS_NAND_U_BOOT_START	0xf8f80000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(128 << 10)
+#endif /* not CONFIG_TPL_BUILD */
+
+#define CONFIG_SPL_PAD_TO		0x20000
+#define CONFIG_TPL_PAD_TO		0x20000
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SYS_TEXT_BASE		0x11001000
+#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#endif
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE		0xeff40000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE
+#define CONFIG_E500
+
+#define CONFIG_MP
+
+#define CONFIG_FSL_ELBC
+#define CONFIG_PCI
+#define CONFIG_PCIE1	/* PCIE controler 1 (slot 1) */
+#define CONFIG_PCIE2	/* PCIE controler 2 (slot 2) */
+#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_FSL_PCIE_RESET	/* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
+
+#define CONFIG_FSL_LAW
+#define CONFIG_TSEC_ENET	/* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_CMD_SATA
+#define CONFIG_SATA_SIL
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
+#define CONFIG_LIBATA
+#define CONFIG_LBA48
+
+#if defined(CONFIG_P2020RDB)
+#define CONFIG_SYS_CLK_FREQ	100000000
+#else
+#define CONFIG_SYS_CLK_FREQ	66666666
+#endif
+#define CONFIG_DDR_CLK_FREQ	66666666
+
+#define CONFIG_HWCONFIG
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE
+#define CONFIG_BTB
+
+#define CONFIG_BOARD_EARLY_INIT_F	/* Call board_pre_init */
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP			1
+#define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
+#endif
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x1fffffff
+#define CONFIG_PANIC_HANG	/* do not reset board on panic */
+
+#define CONFIG_SYS_CCSRBAR		0xffe00000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+
+/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
+       SPL code*/
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#endif
+
+/* DDR Setup */
+#define CONFIG_SYS_FSL_DDR3
+#define CONFIG_SYS_DDR_RAW_TIMING
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_SPD_BUS_NUM 1
+#define SPD_EEPROM_ADDRESS 0x52
+#undef CONFIG_FSL_DDR_INTERACTIVE
+
+#if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD))
+#define CONFIG_SYS_SDRAM_SIZE_LAW	LAW_SIZE_2G
+#define CONFIG_CHIP_SELECTS_PER_CTRL	2
+#else
+#define CONFIG_SYS_SDRAM_SIZE_LAW	LAW_SIZE_1G
+#define CONFIG_CHIP_SELECTS_PER_CTRL	1
+#endif
+#define CONFIG_SYS_SDRAM_SIZE		(1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+
+/* Default settings for DDR3 */
+#ifndef CONFIG_P2020RDB
+#define CONFIG_SYS_DDR_CS0_BNDS		0x0000003f
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80014302
+#define CONFIG_SYS_DDR_CS0_CONFIG_2	0x00000000
+#define CONFIG_SYS_DDR_CS1_BNDS		0x0040007f
+#define CONFIG_SYS_DDR_CS1_CONFIG	0x80014302
+#define CONFIG_SYS_DDR_CS1_CONFIG_2	0x00000000
+
+#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
+#define CONFIG_SYS_DDR_INIT_ADDR	0x00000000
+#define CONFIG_SYS_DDR_INIT_EXT_ADDR	0x00000000
+#define CONFIG_SYS_DDR_MODE_CONTROL	0x00000000
+
+#define CONFIG_SYS_DDR_ZQ_CONTROL	0x89080600
+#define CONFIG_SYS_DDR_WRLVL_CONTROL	0x8655A608
+#define CONFIG_SYS_DDR_SR_CNTR		0x00000000
+#define CONFIG_SYS_DDR_RCW_1		0x00000000
+#define CONFIG_SYS_DDR_RCW_2		0x00000000
+#define CONFIG_SYS_DDR_CONTROL		0xC70C0000	/* Type = DDR3	*/
+#define CONFIG_SYS_DDR_CONTROL_2	0x04401050
+#define CONFIG_SYS_DDR_TIMING_4		0x00220001
+#define CONFIG_SYS_DDR_TIMING_5		0x03402400
+
+#define CONFIG_SYS_DDR_TIMING_3		0x00020000
+#define CONFIG_SYS_DDR_TIMING_0		0x00330004
+#define CONFIG_SYS_DDR_TIMING_1		0x6f6B4846
+#define CONFIG_SYS_DDR_TIMING_2		0x0FA8C8CF
+#define CONFIG_SYS_DDR_CLK_CTRL		0x03000000
+#define CONFIG_SYS_DDR_MODE_1		0x40461520
+#define CONFIG_SYS_DDR_MODE_2		0x8000c000
+#define CONFIG_SYS_DDR_INTERVAL		0x0C300000
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000 0x7fff_ffff	DDR		Up to 2GB cacheable
+ * 0x8000_0000 0xdfff_ffff	PCI Express Mem	1.5G non-cacheable(PCIe * 3)
+ * 0xec00_0000 0xefff_ffff	NOR flash	Up to 64M non-cacheable	CS0/1
+ * 0xf8f8_0000 0xf8ff_ffff	L2 SRAM		Up to 512K cacheable
+ *   (early boot only)
+ * 0xff80_0000 0xff80_7fff	NAND flash	32K non-cacheable	CS1/0
+ * 0xff98_0000 0xff98_ffff	PMC		64K non-cacheable	CS2
+ * 0xffa0_0000 0xffaf_ffff	CPLD		1M non-cacheable	CS3
+ * 0xffb0_0000 0xffbf_ffff	VSC7385 switch  1M non-cacheable	CS2
+ * 0xffc0_0000 0xffc3_ffff	PCI IO range	256k non-cacheable
+ * 0xffd0_0000 0xffd0_3fff	L1 for stack	16K cacheable
+ * 0xffe0_0000 0xffef_ffff	CCSR		1M non-cacheable
+ */
+
+
+/*
+ * Local Bus Definitions
+ */
+#if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD))
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* 64M */
+#define CONFIG_SYS_FLASH_BASE		0xec000000
+#elif defined(CONFIG_P1020UTM)
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* 32M */
+#define CONFIG_SYS_FLASH_BASE		0xee000000
+#else
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* 16M */
+#define CONFIG_SYS_FLASH_BASE		0xef000000
+#endif
+
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+#else
+#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+#endif
+
+#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
+	| BR_PS_16 | BR_V)
+
+#define CONFIG_FLASH_OR_PRELIM	0xfc000ff7
+
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS}
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/* Nand Flash */
+#ifdef CONFIG_NAND_FSL_ELBC
+#define CONFIG_SYS_NAND_BASE		0xff800000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_NAND_BASE_PHYS	0xfff800000ull
+#else
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#endif
+
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+#if defined(CONFIG_P1020RDB_PD)
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+#else
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(16 * 1024)
+#endif
+
+#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+	| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
+	| BR_PS_8	/* Port Size = 8 bit */ \
+	| BR_MS_FCM	/* MSEL = FCM */ \
+	| BR_V)	/* valid */
+#if defined(CONFIG_P1020RDB_PD)
+#define CONFIG_SYS_NAND_OR_PRELIM	(OR_AM_32KB \
+	| OR_FCM_PGS	/* Large Page*/ \
+	| OR_FCM_CSCT \
+	| OR_FCM_CST \
+	| OR_FCM_CHT \
+	| OR_FCM_SCY_1 \
+	| OR_FCM_TRLX \
+	| OR_FCM_EHTR)
+#else
+#define CONFIG_SYS_NAND_OR_PRELIM	(OR_AM_32KB	/* small page */ \
+	| OR_FCM_CSCT \
+	| OR_FCM_CST \
+	| OR_FCM_CHT \
+	| OR_FCM_SCY_1 \
+	| OR_FCM_TRLX \
+	| OR_FCM_EHTR)
+#endif
+#endif /* CONFIG_NAND_FSL_ELBC */
+
+#define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
+
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000 /* stack in RAM */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#else
+/* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS	CONFIG_SYS_INIT_RAM_ADDR
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
+#endif
+/* Size of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN	(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN	(1024 * 1024)/* Reserved for malloc */
+
+#define CONFIG_SYS_CPLD_BASE	0xffa00000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_CPLD_BASE_PHYS	0xfffa00000ull
+#else
+#define CONFIG_SYS_CPLD_BASE_PHYS	CONFIG_SYS_CPLD_BASE
+#endif
+/* CPLD config size: 1Mb */
+#define CONFIG_CPLD_BR_PRELIM	(BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
+					BR_PS_8 | BR_V)
+#define CONFIG_CPLD_OR_PRELIM	(0xfff009f7)
+
+#define CONFIG_SYS_PMC_BASE	0xff980000
+#define CONFIG_SYS_PMC_BASE_PHYS	CONFIG_SYS_PMC_BASE
+#define CONFIG_PMC_BR_PRELIM	(BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
+					BR_PS_8 | BR_V)
+#define CONFIG_PMC_OR_PRELIM	(OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
+				 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
+				 OR_GPCM_EAD)
+
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_BR0_PRELIM	CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
+#define CONFIG_SYS_OR0_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#define CONFIG_SYS_BR1_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_FLASH_OR_PRELIM	/* NOR Options */
+#else
+#define CONFIG_SYS_BR0_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM	CONFIG_FLASH_OR_PRELIM	/* NOR Options */
+#ifdef CONFIG_NAND_FSL_ELBC
+#define CONFIG_SYS_BR1_PRELIM	CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#endif
+#endif
+#define CONFIG_SYS_BR3_PRELIM	CONFIG_CPLD_BR_PRELIM	/* CPLD Base Address */
+#define CONFIG_SYS_OR3_PRELIM	CONFIG_CPLD_OR_PRELIM	/* CPLD Options */
+
+
+/* Vsc7385 switch */
+#ifdef CONFIG_VSC7385_ENET
+#define CONFIG_SYS_VSC7385_BASE		0xffb00000
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_VSC7385_BASE_PHYS	0xfffb00000ull
+#else
+#define CONFIG_SYS_VSC7385_BASE_PHYS	CONFIG_SYS_VSC7385_BASE
+#endif
+
+#define CONFIG_SYS_VSC7385_BR_PRELIM	\
+	(BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
+#define CONFIG_SYS_VSC7385_OR_PRELIM	(OR_AM_128KB | OR_GPCM_CSNT | \
+			OR_GPCM_XACS |  OR_GPCM_SCY_15 | OR_GPCM_SETA | \
+			OR_GPCM_TRLX |  OR_GPCM_EHTR | OR_GPCM_EAD)
+
+#define CONFIG_SYS_BR2_PRELIM	CONFIG_SYS_VSC7385_BR_PRELIM
+#define CONFIG_SYS_OR2_PRELIM	CONFIG_SYS_VSC7385_OR_PRELIM
+
+/* The size of the VSC7385 firmware image */
+#define CONFIG_VSC7385_IMAGE_SIZE	8192
+#endif
+
+/*
+ * Config the L2 Cache as L2 SRAM
+*/
+#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE	0xf8f81000
+#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
+#define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE	(32 << 10)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
+#if defined(CONFIG_P2020RDB)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(364 << 10)
+#else
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(108 << 10)
+#endif
+#elif defined(CONFIG_NAND)
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE	0xf8f81000
+#define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(48 << 10)
+#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
+#else
+#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE	(CONFIG_SYS_INIT_L2_END - 0x2000)
+#define CONFIG_SPL_RELOC_STACK		((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
+#endif /* CONFIG_TPL_BUILD */
+#endif
+#endif
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX		1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x29} }
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x52
+#define CONFIG_SYS_SPD_BUS_NUM		1 /* For rom_loc and flash bank */
+
+/*
+ * I2C2 EEPROM
+ */
+#undef CONFIG_ID_EEPROM
+
+#define CONFIG_RTC_PT7C4338
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68
+#define CONFIG_SYS_I2C_PCA9557_ADDR	0x18
+
+/* enable read and write access to EEPROM */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#define CONFIG_HARD_SPI
+#define CONFIG_FSL_ESPI
+
+#if defined(CONFIG_SPI_FLASH)
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED	10000000
+#define CONFIG_SF_DEFAULT_MODE	0
+#endif
+
+#if defined(CONFIG_PCI)
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 2, direct to uli, tgtid 2, Base address 9000 */
+#define CONFIG_SYS_PCIE2_NAME		"PCIe SLOT"
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xc0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
+#else
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
+#endif
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xffc10000
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xfffc10000ull
+#else
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
+#endif
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 1, Slot 2, tgtid 1, Base address a000 */
+#define CONFIG_SYS_PCIE1_NAME		"mini PCIe SLOT"
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#else
+#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0x80000000
+#endif
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc00000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xfffc00000ull
+#else
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xffc00000
+#endif
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+
+#define CONFIG_PCI_PNP	/* do pci plug-and-play */
+#define CONFIG_E1000	/* Defind e1000 pci Ethernet card*/
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+
+#define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif /* CONFIG_PCI */
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_MII		/* MII PHY management */
+#define CONFIG_TSEC1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define CONFIG_TSEC2
+#define CONFIG_TSEC2_NAME	"eTSEC2"
+#define CONFIG_TSEC3
+#define CONFIG_TSEC3_NAME	"eTSEC3"
+
+#define TSEC1_PHY_ADDR	2
+#define TSEC2_PHY_ADDR	0
+#define TSEC3_PHY_ADDR	1
+
+#define TSEC1_FLAGS	(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS	(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_FLAGS	(TSEC_GIGABIT | TSEC_REDUCED)
+
+#define TSEC1_PHYIDX	0
+#define TSEC2_PHYIDX	0
+#define TSEC3_PHYIDX	0
+
+#define CONFIG_ETHPRIME	"eTSEC1"
+
+#define CONFIG_PHY_GIGE	1	/* Include GbE speed/duplex detection */
+
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+#endif /* CONFIG_TSEC_ENET */
+
+#ifdef CONFIG_QE
+/* QE microcode/firmware address */
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_QE_FW_ADDR	0xefec0000
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#endif /* CONFIG_QE */
+
+#ifdef CONFIG_P1025RDB
+/*
+ * QE UEC ethernet configuration
+ */
+#define CONFIG_MIIM_ADDRESS	(CONFIG_SYS_CCSRBAR + 0x82120)
+
+#undef CONFIG_UEC_ETH
+#define CONFIG_PHY_MODE_NEED_CHANGE
+
+#define CONFIG_UEC_ETH1	/* ETH1 */
+#define CONFIG_HAS_ETH0
+
+#ifdef CONFIG_UEC_ETH1
+#define CONFIG_SYS_UEC1_UCC_NUM	0	/* UCC1 */
+#define CONFIG_SYS_UEC1_RX_CLK	QE_CLK12 /* CLK12 for MII */
+#define CONFIG_SYS_UEC1_TX_CLK	QE_CLK9 /* CLK9 for MII */
+#define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
+#define CONFIG_SYS_UEC1_PHY_ADDR	0x0	/* 0x0 for MII */
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED	100
+#endif /* CONFIG_UEC_ETH1 */
+
+#define CONFIG_UEC_ETH5	/* ETH5 */
+#define CONFIG_HAS_ETH1
+
+#ifdef CONFIG_UEC_ETH5
+#define CONFIG_SYS_UEC5_UCC_NUM	4	/* UCC5 */
+#define CONFIG_SYS_UEC5_RX_CLK	QE_CLK_NONE
+#define CONFIG_SYS_UEC5_TX_CLK	QE_CLK13 /* CLK 13 for RMII */
+#define CONFIG_SYS_UEC5_ETH_TYPE	FAST_ETH
+#define CONFIG_SYS_UEC5_PHY_ADDR	0x3	/* 0x3 for RMII */
+#define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
+#define CONFIG_SYS_UEC5_INTERFACE_SPEED	100
+#endif /* CONFIG_UEC_ETH5 */
+#endif /* CONFIG_P1025RDB */
+
+/*
+ * Environment
+ */
+#ifdef CONFIG_SPIFLASH
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS	0
+#define CONFIG_ENV_SPI_CS	0
+#define CONFIG_ENV_SPI_MAX_HZ	10000000
+#define CONFIG_ENV_SPI_MODE	0
+#define CONFIG_ENV_SIZE		0x2000	/* 8KB */
+#define CONFIG_ENV_OFFSET	0x100000	/* 1MB */
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#elif defined(CONFIG_SDCARD)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_FSL_FIXED_MMC_LOCATION
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_SYS_MMC_ENV_DEV	0
+#elif defined(CONFIG_NAND)
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
+#else
+#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
+#endif
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET	(1024 * 1024)
+#define CONFIG_ENV_RANGE	(3 * CONFIG_ENV_SIZE)
+#elif defined(CONFIG_SYS_RAMBOOT)
+#define CONFIG_ENV_IS_NOWHERE	/* Store ENV in memory only */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
+#define CONFIG_ENV_SIZE		0x2000
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+#endif
+
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
+
+/*
+ * USB
+ */
+#define CONFIG_HAS_FSL_DR_USB
+
+#if defined(CONFIG_HAS_FSL_DR_USB)
+#define CONFIG_USB_EHCI
+
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_USB_STORAGE
+#endif
+#endif
+
+#define CONFIG_MMC
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#endif
+
+#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
+		 || defined(CONFIG_FSL_SATA)
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+#undef CONFIG_WATCHDOG	/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_HOSTNAME		unknown
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	u-boot.bin /* U-Boot image on TFTP server */
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR	1000000
+
+#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
+#define CONFIG_BOOTARGS	/* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE	115200
+
+#ifdef __SW_BOOT_NOR
+#define __NOR_RST_CMD	\
+norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
+i2c mw 18 3 __SW_BOOT_MASK 1; reset
+#endif
+#ifdef __SW_BOOT_SPI
+#define __SPI_RST_CMD	\
+spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
+i2c mw 18 3 __SW_BOOT_MASK 1; reset
+#endif
+#ifdef __SW_BOOT_SD
+#define __SD_RST_CMD	\
+sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
+i2c mw 18 3 __SW_BOOT_MASK 1; reset
+#endif
+#ifdef __SW_BOOT_NAND
+#define __NAND_RST_CMD	\
+nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
+i2c mw 18 3 __SW_BOOT_MASK 1; reset
+#endif
+#ifdef __SW_BOOT_PCIE
+#define __PCIE_RST_CMD	\
+pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
+i2c mw 18 3 __SW_BOOT_MASK 1; reset
+#endif
+
+#define	CONFIG_EXTRA_ENV_SETTINGS	\
+"netdev=eth0\0"	\
+"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"	\
+"loadaddr=1000000\0"	\
+"bootfile=uImage\0"	\
+"tftpflash=tftpboot $loadaddr $uboot; "	\
+	"protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+	"erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
+	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
+	"protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
+	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
+"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"    \
+"consoledev=ttyS0\0"	\
+"ramdiskaddr=2000000\0"	\
+"ramdiskfile=rootfs.ext2.gz.uboot\0"	\
+"fdtaddr=c00000\0"	\
+"bdev=sda1\0" \
+"jffs2nor=mtdblock3\0"	\
+"norbootaddr=ef080000\0"	\
+"norfdtaddr=ef040000\0"	\
+"jffs2nand=mtdblock9\0"	\
+"nandbootaddr=100000\0"	\
+"nandfdtaddr=80000\0"		\
+"ramdisk_size=120000\0"	\
+"map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
+"map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
+__stringify(__NOR_RST_CMD)"\0" \
+__stringify(__SPI_RST_CMD)"\0" \
+__stringify(__SD_RST_CMD)"\0" \
+__stringify(__NAND_RST_CMD)"\0" \
+__stringify(__PCIE_RST_CMD)"\0"
+
+#define CONFIG_NFSBOOTCOMMAND	\
+"setenv bootargs root=/dev/nfs rw "	\
+"nfsroot=$serverip:$rootpath "	\
+"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+"console=$consoledev,$baudrate $othbootargs;" \
+"tftp $loadaddr $bootfile;"	\
+"tftp $fdtaddr $fdtfile;"	\
+"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_HDBOOT	\
+"setenv bootargs root=/dev/$bdev rw rootdelay=30 "	\
+"console=$consoledev,$baudrate $othbootargs;" \
+"usb start;"	\
+"ext2load usb 0:1 $loadaddr /boot/$bootfile;"	\
+"ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"	\
+"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_USB_FAT_BOOT	\
+"setenv bootargs root=/dev/ram rw "	\
+"console=$consoledev,$baudrate $othbootargs " \
+"ramdisk_size=$ramdisk_size;"	\
+"usb start;"	\
+"fatload usb 0:2 $loadaddr $bootfile;"	\
+"fatload usb 0:2 $fdtaddr $fdtfile;"	\
+"fatload usb 0:2 $ramdiskaddr $ramdiskfile;"	\
+"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_USB_EXT2_BOOT	\
+"setenv bootargs root=/dev/ram rw "	\
+"console=$consoledev,$baudrate $othbootargs " \
+"ramdisk_size=$ramdisk_size;"	\
+"usb start;"	\
+"ext2load usb 0:4 $loadaddr $bootfile;"	\
+"ext2load usb 0:4 $fdtaddr $fdtfile;" \
+"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
+"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_NORBOOT	\
+"setenv bootargs root=/dev/$jffs2nor rw "	\
+"console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;"	\
+"bootm $norbootaddr - $norfdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND	\
+"setenv bootargs root=/dev/ram rw "	\
+"console=$consoledev,$baudrate $othbootargs " \
+"ramdisk_size=$ramdisk_size;"	\
+"tftp $ramdiskaddr $ramdiskfile;"	\
+"tftp $loadaddr $bootfile;"	\
+"tftp $fdtaddr $fdtfile;"	\
+"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND	CONFIG_HDBOOT
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/p1_twr.h b/qemu/roms/u-boot/include/configs/p1_twr.h
new file mode 100644
index 000000000..911203d85
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/p1_twr.h
@@ -0,0 +1,609 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * QorIQ P1 Tower boards configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#if defined(CONFIG_TWR_P1025)
+#define CONFIG_BOARDNAME "TWR-P1025"
+#define CONFIG_P1025
+#define CONFIG_PHY_ATHEROS
+#define CONFIG_QE
+#define CONFIG_SYS_LBC_LBCR	0x00080000	/* Conversion of LBC addr */
+#define CONFIG_SYS_LBC_LCRR	0x80000002	/* LB clock ratio reg */
+#endif
+
+#ifdef CONFIG_SDCARD
+#define CONFIG_RAMBOOT_SDCARD
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_SYS_TEXT_BASE		0x11000000
+#define CONFIG_RESET_VECTOR_ADDRESS	0x110bfffc
+#endif
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE		0xeff40000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE
+#define CONFIG_E500
+
+#define CONFIG_MP
+
+#define CONFIG_FSL_ELBC
+#define CONFIG_PCI
+#define CONFIG_PCIE1	/* PCIE controler 1 (slot 1) */
+#define CONFIG_PCIE2	/* PCIE controler 2 (slot 2) */
+#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_FSL_PCIE_RESET	/* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
+
+#define CONFIG_FSL_LAW
+#define CONFIG_TSEC_ENET	/* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_CMD_SATA
+#define CONFIG_SATA_SIL3114
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
+#define CONFIG_LIBATA
+#define CONFIG_LBA48
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_board_sys_clk(unsigned long dummy);
+#endif
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0) /*sysclk for TWR-P1025 */
+
+#define CONFIG_DDR_CLK_FREQ	66666666
+
+#define CONFIG_HWCONFIG
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE
+#define CONFIG_BTB
+
+#define CONFIG_BOARD_EARLY_INIT_F	/* Call board_pre_init */
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x1fffffff
+#define CONFIG_PANIC_HANG	/* do not reset board on panic */
+
+#define CONFIG_SYS_CCSRBAR		0xffe00000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+
+/* DDR Setup */
+#define CONFIG_SYS_FSL_DDR3
+
+#define CONFIG_SYS_SDRAM_SIZE_LAW	LAW_SIZE_512M
+#define CONFIG_CHIP_SELECTS_PER_CTRL	1
+
+#define CONFIG_SYS_SDRAM_SIZE		(1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+
+/* Default settings for DDR3 */
+#define CONFIG_SYS_DDR_CS0_BNDS		0x0000001f
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80014202
+#define CONFIG_SYS_DDR_CS0_CONFIG_2	0x00000000
+#define CONFIG_SYS_DDR_CS1_BNDS		0x00000000
+#define CONFIG_SYS_DDR_CS1_CONFIG	0x00000000
+#define CONFIG_SYS_DDR_CS1_CONFIG_2	0x00000000
+
+#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
+#define CONFIG_SYS_DDR_INIT_ADDR	0x00000000
+#define CONFIG_SYS_DDR_INIT_EXT_ADDR	0x00000000
+#define CONFIG_SYS_DDR_MODE_CONTROL	0x00000000
+
+#define CONFIG_SYS_DDR_ZQ_CONTROL	0x89080600
+#define CONFIG_SYS_DDR_WRLVL_CONTROL	0x8655a608
+#define CONFIG_SYS_DDR_SR_CNTR		0x00000000
+#define CONFIG_SYS_DDR_RCW_1		0x00000000
+#define CONFIG_SYS_DDR_RCW_2		0x00000000
+#define CONFIG_SYS_DDR_CONTROL		0xc70c0000	/* Type = DDR3	*/
+#define CONFIG_SYS_DDR_CONTROL_2	0x04401050
+#define CONFIG_SYS_DDR_TIMING_4		0x00220001
+#define CONFIG_SYS_DDR_TIMING_5		0x03402400
+
+#define CONFIG_SYS_DDR_TIMING_3		0x00020000
+#define CONFIG_SYS_DDR_TIMING_0		0x00220004
+#define CONFIG_SYS_DDR_TIMING_1		0x5c5b6544
+#define CONFIG_SYS_DDR_TIMING_2		0x0fa880de
+#define CONFIG_SYS_DDR_CLK_CTRL		0x03000000
+#define CONFIG_SYS_DDR_MODE_1		0x80461320
+#define CONFIG_SYS_DDR_MODE_2		0x00008000
+#define CONFIG_SYS_DDR_INTERVAL		0x09480000
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000 0x1fff_ffff	DDR		Up to 512MB cacheable
+ * 0x8000_0000 0xdfff_ffff	PCI Express Mem	1.5G non-cacheable(PCIe * 3)
+ * 0xffc0_0000 0xffc3_ffff	PCI IO range	256k non-cacheable
+ *
+ * Localbus
+ * 0xe000_0000 0xe002_0000	SSD1289		128K non-cacheable
+ * 0xec00_0000 0xefff_ffff	FLASH		Up to 64M non-cacheable
+ *
+ * 0xff90_0000 0xff97_ffff	L2 SRAM		Up to 512K cacheable
+ * 0xffd0_0000 0xffd0_3fff	init ram	16K Cacheable
+ * 0xffe0_0000 0xffef_ffff	CCSR		1M non-cacheable
+ */
+
+/*
+ * Local Bus Definitions
+ */
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* 64M */
+#define CONFIG_SYS_FLASH_BASE		0xec000000
+
+#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \
+	| BR_PS_16 | BR_V)
+
+#define CONFIG_FLASH_OR_PRELIM	0xfc0000b1
+
+#define CONFIG_SYS_SSD_BASE	0xe0000000
+#define CONFIG_SYS_SSD_BASE_PHYS	CONFIG_SYS_SSD_BASE
+#define CONFIG_SSD_BR_PRELIM	(BR_PHYS_ADDR(CONFIG_SYS_SSD_BASE_PHYS) | \
+					BR_PS_16 | BR_V)
+#define CONFIG_SSD_OR_PRELIM	(OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
+				 OR_GPCM_ACS_DIV2 | OR_GPCM_SCY | \
+				 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
+
+#define CONFIG_SYS_BR2_PRELIM CONFIG_SSD_BR_PRELIM
+#define CONFIG_SYS_OR2_PRELIM CONFIG_SSD_OR_PRELIM
+
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS}
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+#define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
+
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000
+/* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS	CONFIG_SYS_INIT_RAM_ADDR
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
+/* Size of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN	(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN	(1024 * 1024)/* Reserved for malloc */
+
+#define CONFIG_SYS_BR0_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM	CONFIG_FLASH_OR_PRELIM	/* NOR Options */
+
+/* Serial Port
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX		1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#endif
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL			/* Use FSL common I2C driver */
+#define CONFIG_SYS_FSL_I2C_SPEED	400000	/* I2C spd and slave address */
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x52
+
+/*
+ * I2C2 EEPROM
+ */
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000	/* I2C spd and slave address */
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+
+#define CONFIG_SYS_I2C_PCA9555_ADDR	0x23
+
+/* enable read and write access to EEPROM */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#define CONFIG_HARD_SPI
+#define CONFIG_FSL_ESPI
+
+#if defined(CONFIG_PCI)
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 2, direct to uli, tgtid 2, Base address 9000 */
+#define CONFIG_SYS_PCIE2_NAME		"TWR-ELEV PCIe SLOT"
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xffc10000
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 1, tgtid 1, Base address a000 */
+#define CONFIG_SYS_PCIE1_NAME		"mini PCIe SLOT"
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc00000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xffc00000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP	/* do pci plug-and-play */
+#define CONFIG_E1000	/* Defind e1000 pci Ethernet card*/
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+
+#define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif /* CONFIG_PCI */
+
+#if defined(CONFIG_TSEC_ENET)
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI
+#endif
+
+#define CONFIG_MII		/* MII PHY management */
+#define CONFIG_TSEC1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#undef CONFIG_TSEC2
+#undef CONFIG_TSEC2_NAME
+#define CONFIG_TSEC3
+#define CONFIG_TSEC3_NAME	"eTSEC3"
+
+#define TSEC1_PHY_ADDR	2
+#define TSEC2_PHY_ADDR	0
+#define TSEC3_PHY_ADDR	1
+
+#define TSEC1_FLAGS	(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS	(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_FLAGS	(TSEC_GIGABIT | TSEC_REDUCED)
+
+#define TSEC1_PHYIDX	0
+#define TSEC2_PHYIDX	0
+#define TSEC3_PHYIDX	0
+
+#define CONFIG_ETHPRIME	"eTSEC1"
+
+#define CONFIG_PHY_GIGE	1	/* Include GbE speed/duplex detection */
+
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#undef CONFIG_HAS_ETH2
+#endif /* CONFIG_TSEC_ENET */
+
+#ifdef CONFIG_QE
+/* QE microcode/firmware address */
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_QE_FW_ADDR	0xefec0000
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#endif /* CONFIG_QE */
+
+#ifdef CONFIG_TWR_P1025
+/*
+ * QE UEC ethernet configuration
+ */
+#define CONFIG_MIIM_ADDRESS	(CONFIG_SYS_CCSRBAR + 0x82120)
+
+#undef CONFIG_UEC_ETH
+#define CONFIG_PHY_MODE_NEED_CHANGE
+
+#define CONFIG_UEC_ETH1	/* ETH1 */
+#define CONFIG_HAS_ETH0
+
+#ifdef CONFIG_UEC_ETH1
+#define CONFIG_SYS_UEC1_UCC_NUM	0	/* UCC1 */
+#define CONFIG_SYS_UEC1_RX_CLK	QE_CLK12 /* CLK12 for MII */
+#define CONFIG_SYS_UEC1_TX_CLK	QE_CLK9 /* CLK9 for MII */
+#define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
+#define CONFIG_SYS_UEC1_PHY_ADDR	0x18	/* 0x18 for MII */
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED	100
+#endif /* CONFIG_UEC_ETH1 */
+
+#define CONFIG_UEC_ETH5	/* ETH5 */
+#define CONFIG_HAS_ETH1
+
+#ifdef CONFIG_UEC_ETH5
+#define CONFIG_SYS_UEC5_UCC_NUM	4	/* UCC5 */
+#define CONFIG_SYS_UEC5_RX_CLK	QE_CLK_NONE
+#define CONFIG_SYS_UEC5_TX_CLK	QE_CLK13 /* CLK 13 for RMII */
+#define CONFIG_SYS_UEC5_ETH_TYPE	FAST_ETH
+#define CONFIG_SYS_UEC5_PHY_ADDR	0x19	/* 0x19 for RMII */
+#define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
+#define CONFIG_SYS_UEC5_INTERFACE_SPEED	100
+#endif /* CONFIG_UEC_ETH5 */
+#endif /* CONFIG_TWR-P1025 */
+
+/*
+ * Environment
+ */
+#ifdef CONFIG_SYS_RAMBOOT
+#ifdef CONFIG_RAMBOOT_SDCARD
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_SYS_MMC_ENV_DEV	0
+#else
+#define CONFIG_ENV_IS_NOWHERE	/* Store ENV in memory only */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
+#define CONFIG_ENV_SIZE		0x2000
+#endif
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+#endif
+
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
+
+/*
+ * USB
+ */
+#define CONFIG_HAS_FSL_DR_USB
+
+#if defined(CONFIG_HAS_FSL_DR_USB)
+#define CONFIG_USB_EHCI
+
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_USB_STORAGE
+#endif
+#endif
+
+#define CONFIG_MMC
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#endif
+
+#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
+		 || defined(CONFIG_FSL_SATA)
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+#undef CONFIG_WATCHDOG	/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_HOSTNAME		unknown
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	u-boot.bin /* U-Boot image on TFTP server */
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR	1000000
+
+#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
+#define CONFIG_BOOTARGS	/* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE	115200
+
+#define	CONFIG_EXTRA_ENV_SETTINGS	\
+"netdev=eth0\0"	\
+"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"	\
+"loadaddr=1000000\0"	\
+"bootfile=uImage\0"	\
+"dtbfile=twr-p1025twr.dtb\0"	\
+"ramdiskfile=rootfs.ext2.gz.uboot\0"	\
+"qefirmwarefile=fsl_qe_ucode_1021_10_A.bin\0"	\
+"tftpflash=tftpboot $loadaddr $uboot; "	\
+	"protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+	"erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
+	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
+	"protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
+	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
+"kernelflash=tftpboot $loadaddr $bootfile; "	\
+	"protect off 0xefa80000 +$filesize; "	\
+	"erase 0xefa80000 +$filesize; "	\
+	"cp.b $loadaddr 0xefa80000 $filesize; "	\
+	"protect on 0xefa80000 +$filesize; "	\
+	"cmp.b $loadaddr 0xefa80000 $filesize\0"	\
+"dtbflash=tftpboot $loadaddr $dtbfile; "	\
+	"protect off 0xefe80000 +$filesize; "	\
+	"erase 0xefe80000 +$filesize; "	\
+	"cp.b $loadaddr 0xefe80000 $filesize; "	\
+	"protect on 0xefe80000 +$filesize; "	\
+	"cmp.b $loadaddr 0xefe80000 $filesize\0"	\
+"ramdiskflash=tftpboot $loadaddr $ramdiskfile; "	\
+	"protect off 0xeeb80000 +$filesize; "	\
+	"erase 0xeeb80000 +$filesize; "	\
+	"cp.b $loadaddr 0xeeb80000 $filesize; "	\
+	"protect on 0xeeb80000 +$filesize; "	\
+	"cmp.b $loadaddr 0xeeb80000 $filesize\0"	\
+"qefirmwareflash=tftpboot $loadaddr $qefirmwarefile; "	\
+	"protect off 0xefec0000 +$filesize; "	\
+	"erase 0xefec0000 +$filesize; "	\
+	"cp.b $loadaddr 0xefec0000 $filesize; "	\
+	"protect on 0xefec0000 +$filesize; "	\
+	"cmp.b $loadaddr 0xefec0000 $filesize\0"	\
+"consoledev=ttyS0\0"	\
+"ramdiskaddr=2000000\0"	\
+"ramdiskfile=rootfs.ext2.gz.uboot\0"	\
+"fdtaddr=c00000\0"	\
+"bdev=sda1\0"	\
+"norbootaddr=ef080000\0"	\
+"norfdtaddr=ef040000\0"	\
+"ramdisk_size=120000\0" \
+"usbboot=setenv bootargs root=/dev/sda1 rw rootdelay=5 " \
+"console=$consoledev,$baudrate $othbootargs ; bootm 0xefa80000 - 0xefe80000"
+
+#define CONFIG_NFSBOOTCOMMAND	\
+"setenv bootargs root=/dev/nfs rw "	\
+"nfsroot=$serverip:$rootpath "	\
+"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+"console=$consoledev,$baudrate $othbootargs;" \
+"tftp $loadaddr $bootfile&&"	\
+"tftp $fdtaddr $fdtfile&&"	\
+"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_HDBOOT	\
+"setenv bootargs root=/dev/$bdev rw rootdelay=30 "	\
+"console=$consoledev,$baudrate $othbootargs;" \
+"usb start;"	\
+"ext2load usb 0:1 $loadaddr /boot/$bootfile;"	\
+"ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"	\
+"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_USB_FAT_BOOT	\
+"setenv bootargs root=/dev/ram rw "	\
+"console=$consoledev,$baudrate $othbootargs " \
+"ramdisk_size=$ramdisk_size;"	\
+"usb start;"	\
+"fatload usb 0:2 $loadaddr $bootfile;"	\
+"fatload usb 0:2 $fdtaddr $fdtfile;"	\
+"fatload usb 0:2 $ramdiskaddr $ramdiskfile;"	\
+"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_USB_EXT2_BOOT	\
+"setenv bootargs root=/dev/ram rw "	\
+"console=$consoledev,$baudrate $othbootargs " \
+"ramdisk_size=$ramdisk_size;"	\
+"usb start;"	\
+"ext2load usb 0:4 $loadaddr $bootfile;"	\
+"ext2load usb 0:4 $fdtaddr $fdtfile;" \
+"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
+"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_NORBOOT	\
+"setenv bootargs root=/dev/mtdblock3 rw "	\
+"console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;"	\
+"bootm $norbootaddr - $norfdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND_TFTP	\
+"setenv bootargs root=/dev/ram rw "	\
+"console=$consoledev,$baudrate $othbootargs " \
+"ramdisk_size=$ramdisk_size;"	\
+"tftp $ramdiskaddr $ramdiskfile;"	\
+"tftp $loadaddr $bootfile;"	\
+"tftp $fdtaddr $fdtfile;"	\
+"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND	\
+"setenv bootargs root=/dev/ram rw "	\
+"console=$consoledev,$baudrate $othbootargs " \
+"ramdisk_size=$ramdisk_size;"	\
+"bootm 0xefa80000 0xeeb80000 0xefe80000"
+
+#define CONFIG_BOOTCOMMAND	CONFIG_RAMBOOTCOMMAND
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/p3mx.h b/qemu/roms/u-boot/include/configs/p3mx.h
new file mode 100644
index 000000000..a210e293a
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/p3mx.h
@@ -0,0 +1,434 @@
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * Based on original work by
+ *      Roel Loeffen, (C) Copyright 2006 Prodrive B.V.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/************************************************************************
+ * p3mx.h - configuration for Prodrive P3M750 & P3M7448 boards
+ *
+ * The defines:
+ * CONFIG_P3M750 or
+ * CONFIG_P3M7448
+ * are written into include/config.h by the "make xxx_config" command
+ ***********************************************************************/
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_P3Mx			/* used for both board versions	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xfff00000
+
+#if defined (CONFIG_P3M750)
+#define CONFIG_750FX			/* 750GL/GX/FX			*/
+#define CONFIG_HIGH_BATS		/* High BATs supported		*/
+#define CONFIG_SYS_BOARD_NAME		"P3M750"
+#define CONFIG_SYS_BUS_CLK		100000000
+#define CONFIG_SYS_TCLK		100000000
+#elif defined (CONFIG_P3M7448)
+#define CONFIG_74xx
+#define CONFIG_SYS_BOARD_NAME		"P3M7448"
+#define CONFIG_SYS_BUS_CLK		133333333
+#define CONFIG_SYS_TCLK		133333333
+#endif
+#define CONFIG_SYS_GT_DUAL_CPU			/* also for JTAG even with one cpu */
+
+/* which initialization functions to call for this board */
+#define CONFIG_SYS_BOARD_ASM_INIT	1
+#define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f	*/
+#define CONFIG_MISC_INIT_R      1	/* Call misc_init_r()		*/
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#ifdef CONFIG_P3M750
+#define CONFIG_SYS_SDRAM1_BASE		0x10000000	/* each 256 MByte	*/
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#if defined (CONFIG_P3M750)
+#define CONFIG_SYS_FLASH_BASE		0xff800000	/* start of flash banks	*/
+#define CONFIG_SYS_BOOT_SIZE		_8M		/* boot flash		*/
+#elif defined (CONFIG_P3M7448)
+#define CONFIG_SYS_FLASH_BASE		0xff000000	/* start of flash banks	*/
+#define CONFIG_SYS_BOOT_SIZE		_16M		/* boot flash		*/
+#endif
+#define CONFIG_SYS_BOOT_SPACE		CONFIG_SYS_FLASH_BASE	/* BOOT_CS0 flash 0    */
+#define CONFIG_SYS_MONITOR_BASE	0xfff00000
+#define CONFIG_SYS_RESET_ADDRESS	0xfff00100
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc */
+#define CONFIG_SYS_MISC_REGION_BASE	0xf0000000
+
+#define CONFIG_SYS_DFL_GT_REGS		0xf1000000	/* boot time GT_REGS */
+#define CONFIG_SYS_GT_REGS		0xf1000000	/* GT Registers are mapped here */
+#define CONFIG_SYS_INT_SRAM_BASE	0x42000000	/* GT offers 256k internal SRAM */
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in internal SRAM)
+ *----------------------------------------------------------------------*/
+ /*
+ * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS
+ * To an unused memory region. The stack will remain in cache until RAM
+ * is initialized
+*/
+#undef	CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0x42000000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#define CONFIG_MPSC			/* MV64460 Serial		*/
+#define CONFIG_MPSC_PORT	0
+#define CONFIG_BAUDRATE		115200	/* console baudrate		*/
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+/*-----------------------------------------------------------------------
+ * Ethernet
+ *----------------------------------------------------------------------*/
+/* Change the default ethernet port, use this define (options: 0, 1, 2) */
+#define CONFIG_SYS_ETH_PORT		ETH_0
+#define MV_ETH_DEVS		2
+#define CONFIG_PHY_RESET        1	/* reset phy upon startup         */
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible		*/
+#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver		*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* use hardware flash protection	*/
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#define CONFIG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
+#if defined (CONFIG_P3M750)
+#define CONFIG_ENV_SECT_SIZE	0x20000	/* one sector (1 device)		*/
+#elif defined (CONFIG_P3M7448)
+#define CONFIG_ENV_SECT_SIZE	0x40000	/* two sectors (2 devices parallel	*/
+#endif
+#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CONFIG_MV64460_ECC
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_I2C_SPEED		100000		/* I2C speed default	*/
+
+/* I2C RTC */
+#define CONFIG_RTC_M41T11	1
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR	1900	/* play along with linux	*/
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *----------------------------------------------------------------------*/
+#define PCI_HOST_ADAPTER 0		/* configure ar pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#undef CONFIG_PCI			/* include pci support		*/
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_HOST PCI_HOST_FORCE	/* select pci host function	*/
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+#define CONFIG_PCI_SCAN_SHOW		/* show devices on bus		*/
+#endif /* CONFIG_PCI */
+
+/* PCI MEMORY MAP section */
+#define CONFIG_SYS_PCI0_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI0_MEM_SIZE	_128M
+#define CONFIG_SYS_PCI1_MEM_BASE	0x88000000
+#define CONFIG_SYS_PCI1_MEM_SIZE	_128M
+
+#define CONFIG_SYS_PCI0_0_MEM_SPACE	(CONFIG_SYS_PCI0_MEM_BASE)
+#define CONFIG_SYS_PCI1_0_MEM_SPACE	(CONFIG_SYS_PCI1_MEM_BASE)
+
+/* PCI I/O MAP section */
+#define CONFIG_SYS_PCI0_IO_BASE	0xfa000000
+#define CONFIG_SYS_PCI0_IO_SIZE	_16M
+#define CONFIG_SYS_PCI1_IO_BASE	0xfb000000
+#define CONFIG_SYS_PCI1_IO_SIZE	_16M
+
+#define CONFIG_SYS_PCI0_IO_SPACE	(CONFIG_SYS_PCI0_IO_BASE)
+#define CONFIG_SYS_PCI0_IO_SPACE_PCI	0x00000000
+#define CONFIG_SYS_PCI1_IO_SPACE	(CONFIG_SYS_PCI1_IO_BASE)
+#define CONFIG_SYS_PCI1_IO_SPACE_PCI	0x00000000
+
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS (CONFIG_SYS_PCI0_IO_BASE)
+#define CONFIG_SYS_PCI_IDSEL 0x30
+
+#undef	CONFIG_BOOTARGS
+#define	CONFIG_EXTRA_ENV_SETTINGS_COMMON				\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
+		"bootm\0"						\
+	"rootpath=/opt/eldk/ppc_6xx\0"					\
+	"u-boot=p3mx/u-boot/u-boot.bin\0"				\
+	"load=tftp 100000 ${u-boot}\0"					\
+	"update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;"	\
+		"cp.b 100000 fff00000 40000;"			        \
+		"setenv filesize;saveenv\0"				\
+	"upd=run load update\0"						\
+	"serverip=11.0.0.152\0"
+
+#if defined (CONFIG_P3M750)
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_EXTRA_ENV_SETTINGS_COMMON				\
+	"hostname=p3m750\0"						\
+	"bootfile=/tftpboot/p3mx/vxWorks.st\0"				\
+	"kernel_addr=fc000000\0"					\
+	"ramdisk_addr=fc180000\0"					\
+	"vxfile=p3m750/vxWorks\0"					\
+	"vxuser=ddg\0"							\
+	"vxpass=ddg\0"							\
+	"vxtarget=target\0"						\
+	"vxflags=0x8\0"							\
+	"vxargs=setenv bootargs mgi(0,0)host:${vxfile} h=${serverip} "	\
+		"e=${ipaddr} u=${vxuser} pw=${vxpass} tn=${vxtarget} "	\
+		"f=${vxflags}\0"
+#elif defined (CONFIG_P3M7448)
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_EXTRA_ENV_SETTINGS_COMMON				\
+	"hostname=p3m7448\0"
+#endif
+
+#if defined (CONFIG_P3M750)
+#define CONFIG_BOOTCOMMAND	"tftp;run vxargs;bootvx"
+#elif defined (CONFIG_P3M7448)
+#define CONFIG_BOOTCOMMAND	" "
+#endif
+
+#define CONFIG_BOOTDELAY	3	/* autoboot after 5 seconds */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_SDRAM
+
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_HUSH_PARSER
+
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	        1024	/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	        256	/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	        16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	        CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000 /* memtest works on	        */
+#define CONFIG_SYS_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x08000000	/* default load address */
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_LOOPW            1       /* enable loopw command         */
+#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+/*-----------------------------------------------------------------------
+ * Marvell MV64460 config settings
+ *----------------------------------------------------------------------*/
+/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected device width */
+#if defined (CONFIG_P3M750)
+#define CONFIG_SYS_BOOT_PAR		0x8FDFF87F	/* 16 bit flash, disable burst*/
+#elif defined (CONFIG_P3M7448)
+#define CONFIG_SYS_BOOT_PAR		0x8FEFFFFF	/* 32 bit flash, burst enabled */
+#endif
+
+/*
+ * MPP[0]	Serial Port 0 TxD	TxD	OUT	Connected to P14 (buffered)
+ * MPP[1]	Serial Port 0 RxD	RxD	IN	Connected to P14 (buffered)
+ * MPP[2]	NC
+ * MPP[3]	Serial Port 1 TxD	TxD	OUT	Connected to P14 (buffered)
+ * MPP[4]	PCI Monarch#		GPIO	IN	Connected to P12
+ * MPP[5]	Serial Port 1 RxD	RxD	IN	Connected to P14 (buffered)
+ * MPP[6]	PMC Carrier Interrupt 0	Int	IN	Connected to P14
+ * MPP[7]	PMC Carrier Interrupt 1	Int	IN	Connected to P14
+ * MPP[8]	Reserved				Do not use
+ * MPP[9]	Reserved				Do not use
+ * MPP[10]	Reserved				Do not use
+ * MPP[11]	Reserved				Do not use
+ * MPP[12]	Phy 0 Interrupt		Int	IN
+ * MPP[13]	Phy 1 Interrupt		Int	IN
+ * MPP[14]	NC
+ * MPP[15]	NC
+ * MPP[16]	PCI Interrupt C		Int	IN	Connected to P11
+ * MPP[17]	PCI Interrupt D		Int	IN	Connected to P11
+ * MPP[18]	Watchdog NMI#		GPIO	IN	Connected to MPP[24]
+ * MPP[19]	Watchdog Expired#	WDE	OUT	Connected to rst logic
+ * MPP[20]	Watchdog Status		WD_STS	IN	Read back of rst by watchdog
+ * MPP[21]	NC
+ * MPP[22]	GP LED Green		GPIO	OUT
+ * MPP[23]	GP LED Red		GPIO	OUT
+ * MPP[24]	Watchdog NMI#		Int	OUT
+ * MPP[25]	NC
+ * MPP[26]	NC
+ * MPP[27]	PCI Interrupt A		Int	IN	Connected to P11
+ * MPP[28]	NC
+ * MPP[29]	PCI Interrupt B		Int	IN	Connected to P11
+ * MPP[30]	Module reset		GPIO	OUT	Board reset
+ * MPP[31]	PCI EReady		GPIO	IN	Connected to P12
+ */
+#define CONFIG_SYS_MPP_CONTROL_0	0x00303022
+#define CONFIG_SYS_MPP_CONTROL_1	0x00000000
+#define CONFIG_SYS_MPP_CONTROL_2	0x00004000
+#define CONFIG_SYS_MPP_CONTROL_3	0x00000004
+#define CONFIG_SYS_GPP_LEVEL_CONTROL	0x280730D0
+
+/*----------------------------------------------------------------------
+ * Initial BAT mappings
+ */
+
+/* NOTES:
+ * 1) GUARDED and WRITE_THRU not allowed in IBATS
+ * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
+ */
+/* SDRAM */
+#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
+
+/* init ram */
+#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
+
+/* PCI0, PCI1 in one BAT */
+#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
+#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
+#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* GT regs, bootrom, all the devices, PCI I/O */
+#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
+#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
+#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
+
+#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
+
+/* set rest out of range for Linux !!!!!!!!!!! */
+
+/* IBAT5 and DBAT5 */
+#define CONFIG_SYS_IBAT5L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT5U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT5L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
+
+/* IBAT6 and DBAT6 */
+#define CONFIG_SYS_IBAT6L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT6U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT6L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
+
+/* IBAT7 and DBAT7 */
+#define CONFIG_SYS_IBAT7L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT7U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT7L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8<<20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_VXWORKS_MAC_PTR	0x42010000 /* use some memory in SRAM that's not used!!! */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For all MPC74xx CPUs		 */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * L2CR setup -- make sure this is right for your board!
+ * look in include/mpc74xx.h for the defines used here
+ */
+#define CONFIG_SYS_L2
+
+#if defined (CONFIG_750CX) || defined (CONFIG_750FX)
+#define L2_INIT 0
+#else
+#define L2_INIT		(L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
+			L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
+#endif
+
+#define L2_ENABLE	(L2_INIT | L2CR_L2E)
+
+#ifndef __ASSEMBLY__
+#include <../board/Marvell/include/core.h>
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/p3p440.h b/qemu/roms/u-boot/include/configs/p3p440.h
new file mode 100644
index 000000000..225567bd9
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/p3p440.h
@@ -0,0 +1,306 @@
+/*
+ * (C) Copyright 2005-2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/************************************************************************
+ * board/config_p3p440.h - configuration for Prodrive P3P440
+ ***********************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_P3P440		1	    /* Board is P3P440		*/
+#define CONFIG_440GP		1	    /* Specifc GP support	*/
+#define CONFIG_440		1	    /* ... PPC440 family	*/
+#define CONFIG_BOARD_EARLY_INIT_F 1	    /* Call board_early_init_f	*/
+#define CONFIG_MISC_INIT_R	1	    /* Call misc_init_r		*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
+
+#define CONFIG_SYS_CLK_FREQ	33333333    /* external freq to pll	*/
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_SDRAM_BASE	    0x00000000	    /* _must_ be 0		*/
+#define CONFIG_SYS_FLASH_BASE	    0xff800000	    /* start of FLASH		*/
+#define CONFIG_SYS_MONITOR_BASE    0xfffc0000	    /* start of monitor		*/
+#define CONFIG_SYS_PCI_MEMBASE	    0x80000000	    /* mapped pci memory	*/
+#define CONFIG_SYS_ISRAM_BASE	    0xc0000000	    /* internal SRAM		*/
+#define CONFIG_SYS_PCI_BASE	    0xd0000000	    /* internal PCI regs	*/
+
+#define CONFIG_SYS_USB_BASE	    (CONFIG_SYS_PERIPHERAL_BASE + 0x00000000)
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in internal SRAM)
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_ISRAM_BASE  /* Initial RAM address	*/
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000	    /* Size of used area in RAM	*/
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon*/
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc*/
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CONFIG_SDRAM_BANK0	1	/* init onboard DDR SDRAM bank 0*/
+#define CONFIG_SDRAM_ECC		/* enable ECC support		*/
+#define CONFIG_SYS_SDRAM_TABLE	{ \
+		{(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \
+		{(64 << 20),  12, 0x00082001}} /* 64MB mode 2, 12x9(4)	*/
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+
+#undef CONFIG_SYS_EXT_SERIAL_CLOCK
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_SYS_BAUDRATE_TABLE						\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,		\
+			57600, 115200, 230400, 460800, 921600 }
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		100000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
+#define CONFIG_SYS_I2C_NOPROBES	{ {0, 0x69} }	/* Don't probe these addrs */
+
+/*-----------------------------------------------------------------------
+ * I2C RTC
+ *----------------------------------------------------------------------*/
+#define CONFIG_RTC_MAX6900	1		/* MAX6900 RTC		*/
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (PCF8594C) for environment
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x54	/* EEPROM PCF8594C		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
+/* mask of address bits that overflow into the "EEPROM chip address"	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3	/* The Philips PCF8594C has	*/
+					/* 8 byte page write mode using */
+					/* last 3 bits of the address	*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	40   /* and takes up to 40 msec */
+
+/*-----------------------------------------------------------------------
+ * Default configuration (environment varibles...)
+ *----------------------------------------------------------------------*/
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"hostname=p3p440\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
+		"bootm\0"						\
+	"rootpath=/opt/eldk/ppc_4xx\0"					\
+	"bootfile=/tftpboot/p3p440/uImage\0"				\
+	"kernel_addr=ff800000\0"					\
+	"ramdisk_addr=ff810000\0"					\
+	"load=tftp 100000 /tftpboot/p3p440/u-boot.bin\0"		\
+	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"	\
+		"cp.b 100000 fffc0000 40000;"			        \
+		"setenv filesize;saveenv\0"				\
+	"upd=run load update\0"						\
+	"unlock=yes\0"							\
+	""
+#define CONFIG_BOOTCOMMAND	"run net_nfs"
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_PPC4xx_EMAC
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0x1c	/* PHY address			*/
+#define CONFIG_HAS_ETH1
+#define CONFIG_PHY1_ADDR	0x1d	/* EMAC1 PHY address		*/
+#define CONFIG_SYS_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_SNTP
+
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+
+#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
+#define CONFIG_LOOPW            1       /* enable loopw command         */
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *----------------------------------------------------------------------*/
+/* General PCI */
+#define CONFIG_PCI			            /* include pci support	        */
+#define	CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
+#define CONFIG_PCI_PNP			        /* do pci plug-and-play         */
+#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
+#define CONFIG_SYS_PCI_TARGBASE    0x80000000  /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
+
+/* Board-specific PCI */
+#define CONFIG_SYS_PCI_TARGET_INIT	            /* let board init pci target    */
+
+#define CONFIG_DISABLE_PISE_TEST	/* disable PISE test (PCIX only)*/
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe  /* Whatever */
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_FLASH0		0xFF800000
+#define CONFIG_SYS_FLASH1		0xFF000000
+#define CONFIG_SYS_FLASH2		0xFE800000
+#define CONFIG_SYS_FLASH3		0xFE000000
+#define CONFIG_SYS_USB			0xF0000000
+
+/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
+#define CONFIG_SYS_EBC_PB0AP		0x03050200
+#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_FLASH0 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (Flash Bank 1, NOR-FLASH) initialization			*/
+#define CONFIG_SYS_EBC_PB1AP		0x03050200
+#define CONFIG_SYS_EBC_PB1CR		(CONFIG_SYS_FLASH1 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 2 (Flash Bank 2, NOR-FLASH) initialization			*/
+#define CONFIG_SYS_EBC_PB2AP		0x03050200
+#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_FLASH2 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 3 (Flash Bank 3, NOR-FLASH) initialization			*/
+#define CONFIG_SYS_EBC_PB3AP		0x03050200
+#define CONFIG_SYS_EBC_PB3CR		(CONFIG_SYS_FLASH3 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 7 (USB controller) initialization				*/
+#define CONFIG_SYS_EBC_PB7AP		0x02015000
+#define CONFIG_SYS_EBC_PB7CR		(CONFIG_SYS_USB | 0xFE000) /* BAS=0xF00,BS=128MB,BU=R/W,BW=16bit*/
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_FLASH_CFI				/* The flash is CFI compatible	*/
+#define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/
+
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH3, CONFIG_SYS_FLASH2, CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	4	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* use hardware flash protection	*/
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash	*/
+
+#define CONFIG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
+
+#define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector		*/
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
+#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/palmld.h b/qemu/roms/u-boot/include/configs/palmld.h
new file mode 100644
index 000000000..9480d8daf
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/palmld.h
@@ -0,0 +1,254 @@
+/*
+ * Palm LifeDrive configuration file
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef	__CONFIG_H
+#define	__CONFIG_H
+
+/*
+ * High Level Board Configuration Options
+ */
+#define	CONFIG_CPU_PXA27X		1	/* Marvell PXA270 CPU */
+#define	CONFIG_PALMLD		1	/* Palm LifeDrive board */
+
+/* we will never enable dcache, because we have to setup MMU first */
+#define CONFIG_SYS_DCACHE_OFF
+
+/*
+ * Environment settings
+ */
+#define	CONFIG_ENV_OVERWRITE
+#define	CONFIG_SYS_MALLOC_LEN		(128*1024)
+#define	CONFIG_SYS_TEXT_BASE	0x0
+
+#define	CONFIG_BOOTCOMMAND						\
+	"if mmcinfo && fatload mmc 0 0xa0000000 uboot.script ; then "	\
+		"source 0xa0000000; "					\
+	"else "								\
+		"bootm 0x0x60000; "					\
+	"fi; "
+#define	CONFIG_BOOTARGS			"console=tty0 console=ttyS0,9600"
+#define	CONFIG_TIMESTAMP
+#define	CONFIG_BOOTDELAY		2	/* Autoboot delay */
+#define	CONFIG_CMDLINE_TAG
+#define	CONFIG_SETUP_MEMORY_TAGS
+
+#define	CONFIG_LZMA			/* LZMA compression support */
+
+/*
+ * Serial Console Configuration
+ */
+#define	CONFIG_PXA_SERIAL
+#define	CONFIG_FFUART			1
+#define CONFIG_CONS_INDEX		3
+#define	CONFIG_BAUDRATE			9600
+
+/*
+ * Bootloader Components Configuration
+ */
+#include <config_cmd_default.h>
+
+#undef	CONFIG_CMD_NET
+#undef	CONFIG_CMD_NFS
+#define	CONFIG_CMD_ENV
+#undef	CONFIG_CMD_IMLS
+#define	CONFIG_CMD_MMC
+#define	CONFIG_CMD_IDE
+#define	CONFIG_LCD
+#define	CONFIG_PXA_LCD
+
+/*
+ * MMC Card Configuration
+ */
+#ifdef	CONFIG_CMD_MMC
+#define	CONFIG_MMC
+#define	CONFIG_GENERIC_MMC
+#define	CONFIG_PXA_MMC_GENERIC
+#define	CONFIG_SYS_MMC_BASE		0xF0000000
+#define	CONFIG_CMD_FAT
+#define	CONFIG_CMD_EXT2
+#define	CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * LCD
+ */
+#ifdef CONFIG_LCD
+#define	CONFIG_LQ038J7DH53
+#define	CONFIG_VIDEO_LOGO
+#define	CONFIG_CMD_BMP
+#define	CONFIG_SPLASH_SCREEN
+#define	CONFIG_SPLASH_SCREEN_ALIGN
+#define	CONFIG_VIDEO_BMP_GZIP
+#define	CONFIG_VIDEO_BMP_RLE8
+#define	CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(2 << 20)
+#endif
+
+/*
+ * KGDB
+ */
+#ifdef	CONFIG_CMD_KGDB
+#define	CONFIG_KGDB_BAUDRATE		230400	/* kgdb serial port speed */
+#endif
+
+/*
+ * HUSH Shell Configuration
+ */
+#define	CONFIG_SYS_HUSH_PARSER		1
+
+#define	CONFIG_SYS_LONGHELP
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define	CONFIG_SYS_PROMPT		"$ "
+#endif
+#define	CONFIG_SYS_CBSIZE		256
+#define	CONFIG_SYS_PBSIZE		\
+	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define	CONFIG_SYS_MAXARGS		16
+#define	CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+#define	CONFIG_SYS_DEVICE_NULLDEV	1
+
+/*
+ * Clock Configuration
+ */
+#undef	CONFIG_SYS_CLKS_IN_HZ
+#define	CONFIG_SYS_CPUSPEED		0x210		/* 416MHz ; N=2,L=16 */
+
+/*
+ * DRAM Map
+ */
+#define	CONFIG_NR_DRAM_BANKS		1		/* 1 bank of DRAM */
+#define	PHYS_SDRAM_1			0xa0000000	/* SDRAM Bank #1 */
+#define	PHYS_SDRAM_1_SIZE		0x02000000	/* 32 MB */
+
+#define	CONFIG_SYS_DRAM_BASE		0xa0000000	/* CS0 */
+#define	CONFIG_SYS_DRAM_SIZE		0x02000000	/* 32 MB DRAM */
+
+#define	CONFIG_SYS_MEMTEST_START	0xa0400000	/* memtest works on */
+#define	CONFIG_SYS_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM */
+
+#define	CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_DRAM_BASE
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
+/*
+ * NOR FLASH
+ */
+#ifdef	CONFIG_CMD_FLASH
+#define	PHYS_FLASH_1			0x00000000	/* Flash Bank #1 */
+#define	PHYS_FLASH_SIZE			0x00080000	/* 512 KB */
+#define	CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+
+#define	CONFIG_SYS_FLASH_CFI
+#define	CONFIG_FLASH_CFI_DRIVER		1
+
+#define	CONFIG_FLASH_CFI_LEGACY
+#define	CONFIG_SYS_FLASH_LEGACY_512Kx16
+
+#define	CONFIG_SYS_MONITOR_BASE		0
+#define	CONFIG_SYS_MONITOR_LEN		0x40000
+
+#define	CONFIG_SYS_MAX_FLASH_BANKS	1
+#define	CONFIG_SYS_MAX_FLASH_SECT	256
+
+#define	CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+
+#define	CONFIG_SYS_FLASH_ERASE_TOUT	240000
+#define	CONFIG_SYS_FLASH_WRITE_TOUT	240000
+#define	CONFIG_SYS_FLASH_LOCK_TOUT	240000
+#define	CONFIG_SYS_FLASH_UNLOCK_TOUT	240000
+#define	CONFIG_SYS_FLASH_PROTECTION
+
+#define	CONFIG_ENV_IS_IN_FLASH		1
+#define	CONFIG_ENV_SECT_SIZE		0x10000
+#else
+#define	CONFIG_SYS_NO_FLASH
+#define	CONFIG_ENV_IS_NOWHERE
+#endif
+
+#define	CONFIG_ENV_ADDR			0x40000
+#define	CONFIG_ENV_SIZE			0x4000
+
+/*
+ * IDE
+ */
+#ifdef	CONFIG_CMD_IDE
+#define	CONFIG_LBA48
+#undef	CONFIG_IDE_LED
+#undef	CONFIG_IDE_RESET
+
+#define	__io
+
+#define	CONFIG_SYS_IDE_MAXBUS		1
+#define	CONFIG_SYS_IDE_MAXDEVICE	1
+
+#define	CONFIG_SYS_ATA_BASE_ADDR	0x20000000
+#define	CONFIG_SYS_ATA_IDE0_OFFSET	0x0
+
+#define	CONFIG_SYS_ATA_DATA_OFFSET	0x10
+#define	CONFIG_SYS_ATA_REG_OFFSET	0x10
+#define	CONFIG_SYS_ATA_ALT_OFFSET	0x10
+
+#define	CONFIG_SYS_ATA_STRIDE		1
+#endif
+
+/*
+ * GPIO settings
+ */
+#define	CONFIG_SYS_GAFR0_L_VAL	0x00000000
+#define	CONFIG_SYS_GAFR0_U_VAL	0xa5180012
+#define	CONFIG_SYS_GAFR1_L_VAL	0x69988056
+#define	CONFIG_SYS_GAFR1_U_VAL	0xaaa580aa
+#define	CONFIG_SYS_GAFR2_L_VAL	0x6aaaaaaa
+#define	CONFIG_SYS_GAFR2_U_VAL	0x01040001
+#define	CONFIG_SYS_GAFR3_L_VAL	0x540a950c
+#define	CONFIG_SYS_GAFR3_U_VAL	0x00000009
+#define	CONFIG_SYS_GPCR0_VAL	0x00000000
+#define	CONFIG_SYS_GPCR1_VAL	0x00000000
+#define	CONFIG_SYS_GPCR2_VAL	0x00000000
+#define	CONFIG_SYS_GPCR3_VAL	0x00000000
+#define	CONFIG_SYS_GPDR0_VAL	0xc26b0000
+#define	CONFIG_SYS_GPDR1_VAL	0xfcdfaa93
+#define	CONFIG_SYS_GPDR2_VAL	0x7bbaffff
+#define	CONFIG_SYS_GPDR3_VAL	0x006ff38d
+#define	CONFIG_SYS_GPSR0_VAL	0x0d9e45ee
+#define	CONFIG_SYS_GPSR1_VAL	0x03affdae
+#define	CONFIG_SYS_GPSR2_VAL	0x07554000
+#define	CONFIG_SYS_GPSR3_VAL	0x01bc0785
+
+#define	CONFIG_SYS_PSSR_VAL	0x30
+
+/*
+ * Clock settings
+ */
+#define	CONFIG_SYS_CKEN		0x01ffffff
+#define	CONFIG_SYS_CCCR		0x02000210
+
+/*
+ * Memory settings
+ */
+#define	CONFIG_SYS_MSC0_VAL	0x7ff844c8
+#define	CONFIG_SYS_MSC1_VAL	0x7ff86ab4
+#define	CONFIG_SYS_MSC2_VAL	0x7ff87ff8
+#define	CONFIG_SYS_MDCNFG_VAL	0x0B880acd
+#define	CONFIG_SYS_MDREFR_VAL	0x201fa031
+#define	CONFIG_SYS_MDMRS_VAL	0x00320032
+#define	CONFIG_SYS_FLYCNFG_VAL	0x00000000
+#define	CONFIG_SYS_SXCNFG_VAL	0x40044004
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define	CONFIG_SYS_MECR_VAL	0x00000003
+#define	CONFIG_SYS_MCMEM0_VAL	0x0001c391
+#define	CONFIG_SYS_MCMEM1_VAL	0x0001c391
+#define	CONFIG_SYS_MCATT0_VAL	0x0001c391
+#define	CONFIG_SYS_MCATT1_VAL	0x0001c391
+#define	CONFIG_SYS_MCIO0_VAL	0x00014611
+#define	CONFIG_SYS_MCIO1_VAL	0x0001c391
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/palmtc.h b/qemu/roms/u-boot/include/configs/palmtc.h
new file mode 100644
index 000000000..8abce1b42
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/palmtc.h
@@ -0,0 +1,227 @@
+/*
+ * Palm Tungsten|C configuration file
+ *
+ * Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef	__CONFIG_H
+#define	__CONFIG_H
+
+#include <asm/arch/pxa-regs.h>
+
+/*
+ * High Level Board Configuration Options
+ */
+#define	CONFIG_CPU_PXA25X			1	/* Intel PXA255 CPU */
+#define	CONFIG_PALMTC			1	/* Palm Tungsten|C board */
+
+/* we will never enable dcache, because we have to setup MMU first */
+#define CONFIG_SYS_DCACHE_OFF
+
+/*
+ * Environment settings
+ */
+#define	CONFIG_ENV_OVERWRITE
+#define	CONFIG_SYS_MALLOC_LEN		(128*1024)
+#define	CONFIG_SYS_TEXT_BASE	0x0
+
+#define	CONFIG_BOOTCOMMAND						\
+	"if mmc init && fatload mmc 0 0xa0000000 uboot.script ; then "	\
+		"source 0xa0000000; "					\
+	"else "								\
+		"bootm 0x80000; "					\
+	"fi; "
+#define	CONFIG_BOOTARGS							\
+	"console=tty0 console=ttyS0,115200"
+#define	CONFIG_TIMESTAMP
+#define	CONFIG_BOOTDELAY		2	/* Autoboot delay */
+#define	CONFIG_CMDLINE_TAG
+#define	CONFIG_SETUP_MEMORY_TAGS
+
+#define	CONFIG_LZMA			/* LZMA compression support */
+
+/*
+ * Serial Console Configuration
+ * STUART - the lower serial port on Colibri board
+ */
+#define	CONFIG_PXA_SERIAL
+#define	CONFIG_FFUART			1
+#define CONFIG_CONS_INDEX		3
+#define	CONFIG_BAUDRATE			115200
+
+/*
+ * Bootloader Components Configuration
+ */
+#include <config_cmd_default.h>
+
+#undef	CONFIG_CMD_NET
+#undef	CONFIG_CMD_NFS
+#define	CONFIG_CMD_ENV
+#define	CONFIG_CMD_MMC
+#define	CONFIG_LCD
+#define	CONFIG_PXA_LCD
+
+/*
+ * MMC Card Configuration
+ */
+#ifdef	CONFIG_CMD_MMC
+#define	CONFIG_MMC
+#define	CONFIG_GENERIC_MMC
+#define	CONFIG_PXA_MMC_GENERIC
+#define	CONFIG_SYS_MMC_BASE		0xF0000000
+#define	CONFIG_CMD_FAT
+#define	CONFIG_CMD_EXT2
+#define	CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * LCD
+ */
+#ifdef	CONFIG_LCD
+#define	CONFIG_ACX517AKN
+#define	CONFIG_VIDEO_LOGO
+#define	CONFIG_CMD_BMP
+#define	CONFIG_SPLASH_SCREEN
+#define	CONFIG_SPLASH_SCREEN_ALIGN
+#define	CONFIG_VIDEO_BMP_GZIP
+#define	CONFIG_VIDEO_BMP_RLE8
+#define	CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(2 << 20)
+#endif
+
+/*
+ * KGDB
+ */
+#ifdef	CONFIG_CMD_KGDB
+#define	CONFIG_KGDB_BAUDRATE		230400	/* kgdb serial port speed */
+#endif
+
+/*
+ * HUSH Shell Configuration
+ */
+#define	CONFIG_SYS_HUSH_PARSER		1
+
+#define	CONFIG_SYS_LONGHELP
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define	CONFIG_SYS_PROMPT		"$ "
+#endif
+#define	CONFIG_SYS_CBSIZE		256
+#define	CONFIG_SYS_PBSIZE		\
+	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define	CONFIG_SYS_MAXARGS		16
+#define	CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+#define	CONFIG_SYS_DEVICE_NULLDEV	1
+
+/*
+ * Clock Configuration
+ */
+#undef	CONFIG_SYS_CLKS_IN_HZ
+#define	CONFIG_SYS_CPUSPEED		0x161		/* 400MHz;L=1 M=3 T=1 */
+
+/*
+ * DRAM Map
+ */
+#define	CONFIG_NR_DRAM_BANKS		1		/* 1 bank of DRAM */
+#define	PHYS_SDRAM_1			0xa0000000	/* SDRAM Bank #1 */
+#define	PHYS_SDRAM_1_SIZE		0x04000000	/* 64 MB */
+
+#define	CONFIG_SYS_DRAM_BASE		0xa0000000	/* CS0 */
+#define	CONFIG_SYS_DRAM_SIZE		0x04000000	/* 64 MB DRAM */
+
+#define	CONFIG_SYS_MEMTEST_START	0xa0400000	/* memtest works on */
+#define	CONFIG_SYS_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM */
+
+#define	CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_DRAM_BASE
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define	CONFIG_SYS_INIT_SP_ADDR		0xfffff800
+
+/*
+ * NOR FLASH
+ */
+#ifdef	CONFIG_CMD_FLASH
+#define	PHYS_FLASH_1			0x00000000	/* Flash Bank #1 */
+#define	PHYS_FLASH_SIZE			0x01000000	/* 16 MB */
+#define	CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+
+#define	CONFIG_SYS_FLASH_CFI
+#define	CONFIG_FLASH_CFI_DRIVER		1
+#define	CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_32BIT
+
+#define	CONFIG_SYS_MAX_FLASH_BANKS	1
+#define	CONFIG_SYS_MAX_FLASH_SECT	64
+
+#define	CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+
+#define	CONFIG_SYS_FLASH_ERASE_TOUT	240000
+#define	CONFIG_SYS_FLASH_WRITE_TOUT	240000
+#define	CONFIG_SYS_FLASH_LOCK_TOUT	240000
+#define	CONFIG_SYS_FLASH_UNLOCK_TOUT	240000
+#define	CONFIG_SYS_FLASH_PROTECTION
+
+#define	CONFIG_ENV_IS_IN_FLASH		1
+#define	CONFIG_ENV_SECT_SIZE		0x40000
+#else
+#define	CONFIG_SYS_NO_FLASH
+#define	CONFIG_ENV_IS_NOWHERE
+#endif
+
+#define	CONFIG_SYS_MONITOR_BASE		0x0
+#define	CONFIG_SYS_MONITOR_LEN		0x40000
+
+#define	CONFIG_ENV_SIZE			0x4000
+#define	CONFIG_ENV_ADDR			0x40000
+
+/*
+ * GPIO settings
+ */
+#define	CONFIG_SYS_GAFR0_L_VAL	0x00011004
+#define	CONFIG_SYS_GAFR0_U_VAL	0xa5000008
+#define	CONFIG_SYS_GAFR1_L_VAL	0x60888050
+#define	CONFIG_SYS_GAFR1_U_VAL	0xaaa50aaa
+#define	CONFIG_SYS_GAFR2_L_VAL	0x0aaaaaaa
+#define	CONFIG_SYS_GAFR2_U_VAL	0x00000000
+#define	CONFIG_SYS_GPCR0_VAL	0x0
+#define	CONFIG_SYS_GPCR1_VAL	0x0
+#define	CONFIG_SYS_GPCR2_VAL	0x0
+#define	CONFIG_SYS_GPDR0_VAL	0xcfff8140
+#define	CONFIG_SYS_GPDR1_VAL	0xfcbfbef3
+#define	CONFIG_SYS_GPDR2_VAL	0x0001ffff
+#define	CONFIG_SYS_GPSR0_VAL	0x00010f8f
+#define	CONFIG_SYS_GPSR1_VAL	0x00bf5de5
+#define	CONFIG_SYS_GPSR2_VAL	0x03fe0800
+
+#define	CONFIG_SYS_PSSR_VAL	PSSR_RDH
+
+/* Clock setup:
+ * CKEN[1] - PWM1 ; CKEN[6] - FFUART
+ * CKEN[12] - MMC ; CKEN[16] - LCD
+ */
+#define	CONFIG_SYS_CKEN		0x00011042
+#define	CONFIG_SYS_CCCR		0x00000161
+
+/*
+ * Memory settings
+ */
+#define	CONFIG_SYS_MSC0_VAL	0x800092c2
+#define	CONFIG_SYS_MSC1_VAL	0x80008000
+#define	CONFIG_SYS_MSC2_VAL	0x80008000
+#define	CONFIG_SYS_MDCNFG_VAL	0x00001ac9
+#define	CONFIG_SYS_MDREFR_VAL	0x00118018
+#define	CONFIG_SYS_MDMRS_VAL	0x00220032
+#define	CONFIG_SYS_FLYCNFG_VAL	0x01fe01fe
+#define	CONFIG_SYS_SXCNFG_VAL	0x00000000
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define	CONFIG_SYS_MECR_VAL	0x00000000
+#define	CONFIG_SYS_MCMEM0_VAL	0x00010504
+#define	CONFIG_SYS_MCMEM1_VAL	0x00010504
+#define	CONFIG_SYS_MCATT0_VAL	0x00010504
+#define	CONFIG_SYS_MCATT1_VAL	0x00010504
+#define	CONFIG_SYS_MCIO0_VAL	0x00010e04
+#define	CONFIG_SYS_MCIO1_VAL	0x00010e04
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/palmtreo680.h b/qemu/roms/u-boot/include/configs/palmtreo680.h
new file mode 100644
index 000000000..36626639d
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/palmtreo680.h
@@ -0,0 +1,283 @@
+/*
+ * Palm Treo 680 configuration file
+ *
+ * Copyright (C) 2013 Mike Dunn <mikedunn@newsguy.com>
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+ *
+ */
+
+#ifndef	__CONFIG_H
+#define	__CONFIG_H
+
+/*
+ * High Level Board Configuration Options
+ */
+#define CONFIG_CPU_PXA27X
+#define CONFIG_PALMTREO680
+#define CONFIG_MACH_TYPE                MACH_TYPE_TREO680
+
+#define CONFIG_SYS_MALLOC_LEN           (4096*1024)
+
+#define CONFIG_LZMA
+
+/*
+ * Serial Console Configuration
+ */
+#define CONFIG_PXA_SERIAL
+#define CONFIG_FFUART                   1
+#define CONFIG_BAUDRATE                 9600
+#define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_CONS_INDEX               3
+
+/* we have nand (although technically nand *is* flash...) */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_LCD
+/* #define CONFIG_KEYBOARD */  /* TODO */
+
+/*
+ * Bootloader Components Configuration
+ */
+#include <config_cmd_default.h>
+#undef  CONFIG_CMD_FPGA
+#undef  CONFIG_CMD_LOADS
+#undef  CONFIG_CMD_NET
+#undef  CONFIG_CMD_NFS
+#undef  CONFIG_CMD_IMLS
+#undef  CONFIG_CMD_FLASH
+#undef  CONFIG_CMD_SETGETDCR
+#undef  CONFIG_CMD_SOURCE
+#undef  CONFIG_CMD_XIMG
+
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NAND
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+
+/*
+ * MMC Card Configuration
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_PXA_MMC_GENERIC
+
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * LCD
+ */
+#ifdef CONFIG_LCD
+#define CONFIG_PXA_LCD
+#define CONFIG_ACX544AKN
+#define CONFIG_LCD_LOGO
+#define CONFIG_SYS_LCD_PXA_NO_L_BIAS /* don't configure GPIO77 as L_BIAS */
+#define LCD_BPP LCD_COLOR16
+#define CONFIG_FB_ADDR 0x5c000000    /* internal SRAM */
+#define CONFIG_CMD_BMP
+#define CONFIG_SPLASH_SCREEN         /* requires "splashimage" env var */
+#define CONFIG_SPLASH_SCREEN_ALIGN   /* requires "splashpos" env var */
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE  (2 << 20)
+
+#endif
+
+/*
+ * KGDB
+ */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE            230400  /* kgdb serial port speed */
+#endif
+
+/*
+ * HUSH Shell Configuration
+ */
+#define CONFIG_SYS_HUSH_PARSER          1
+#define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
+
+#define CONFIG_SYS_LONGHELP
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT               "$ "
+#else
+#endif
+#define CONFIG_SYS_CBSIZE               256
+#define CONFIG_SYS_PBSIZE               \
+	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS              16
+#define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_DEVICE_NULLDEV       1
+
+/*
+ * Clock Configuration
+ */
+#undef  CONFIG_SYS_CLKS_IN_HZ
+#define CONFIG_SYS_CPUSPEED             0x210           /* 416MHz ; N=2,L=16 */
+
+/*
+ * Stack sizes
+ */
+#define CONFIG_STACKSIZE                (128*1024)      /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ            (4*1024)        /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ            (4*1024)        /* FIQ stack */
+#endif
+
+/*
+ * DRAM Map
+ */
+#define CONFIG_NR_DRAM_BANKS            1               /* 1 bank of DRAM */
+#define PHYS_SDRAM_1                    0xa0000000      /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE               0x04000000      /* 64 MB */
+
+#define CONFIG_SYS_DRAM_BASE            0xa0000000
+#define CONFIG_SYS_DRAM_SIZE            0x04000000      /* 64 MB DRAM */
+
+#define CONFIG_SYS_MEMTEST_START        0xa0400000      /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END          0xa0800000      /* 4 ... 8 MB in DRAM */
+#define CONFIG_SYS_LOAD_ADDR            CONFIG_SYS_DRAM_BASE
+#define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
+
+/*
+ * GPIO settings
+ */
+#define CONFIG_SYS_GAFR0_L_VAL  0x0E000000
+#define CONFIG_SYS_GAFR0_U_VAL  0xA500001A
+#define CONFIG_SYS_GAFR1_L_VAL  0x60000002
+#define CONFIG_SYS_GAFR1_U_VAL  0xAAA07959
+#define CONFIG_SYS_GAFR2_L_VAL  0x02AAAAAA
+#define CONFIG_SYS_GAFR2_U_VAL  0x41440F08
+#define CONFIG_SYS_GAFR3_L_VAL  0x56AA95FF
+#define CONFIG_SYS_GAFR3_U_VAL  0x00001401
+#define CONFIG_SYS_GPCR0_VAL    0x1FF80400
+#define CONFIG_SYS_GPCR1_VAL    0x03003FC1
+#define CONFIG_SYS_GPCR2_VAL    0x01C1E000
+#define CONFIG_SYS_GPCR3_VAL    0x01C1E000
+#define CONFIG_SYS_GPDR0_VAL    0xCFF90400
+#define CONFIG_SYS_GPDR1_VAL    0xFB22BFC1
+#define CONFIG_SYS_GPDR2_VAL    0x93CDFFDF
+#define CONFIG_SYS_GPDR3_VAL    0x0069FF81
+#define CONFIG_SYS_GPSR0_VAL    0x02000018
+#define CONFIG_SYS_GPSR1_VAL    0x00000000
+#define CONFIG_SYS_GPSR2_VAL    0x000C0000
+#define CONFIG_SYS_GPSR3_VAL    0x00080000
+
+#define CONFIG_SYS_PSSR_VAL     0x30
+
+/*
+ * Clock settings
+ */
+#define CONFIG_SYS_CKEN         0x01ffffff
+#define CONFIG_SYS_CCCR         0x02000210
+
+/*
+ * Memory settings
+ */
+#define CONFIG_SYS_MSC0_VAL     0x7ff844c8
+#define CONFIG_SYS_MSC1_VAL     0x7ff86ab4
+#define CONFIG_SYS_MSC2_VAL     0x7ff87ff8
+#define CONFIG_SYS_MDCNFG_VAL   0x0B880acd
+#define CONFIG_SYS_MDREFR_VAL   0x201fa031
+#define CONFIG_SYS_MDMRS_VAL    0x00320032
+#define CONFIG_SYS_FLYCNFG_VAL  0x00000000
+#define CONFIG_SYS_SXCNFG_VAL   0x40044004
+#define CONFIG_SYS_MECR_VAL     0x00000003
+#define CONFIG_SYS_MCMEM0_VAL   0x0001c391
+#define CONFIG_SYS_MCMEM1_VAL   0x0001c391
+#define CONFIG_SYS_MCATT0_VAL   0x0001c391
+#define CONFIG_SYS_MCATT1_VAL   0x0001c391
+#define CONFIG_SYS_MCIO0_VAL    0x00014611
+#define CONFIG_SYS_MCIO1_VAL    0x0001c391
+
+/*
+ * USB
+ */
+#define CONFIG_USB_DEVICE
+#define CONFIG_USB_TTY
+#define CONFIG_USB_DEV_PULLUP_GPIO 114
+
+/*
+ * SPL
+ */
+#define CONFIG_SPL
+#define CONFIG_SPL_TEXT_BASE    0xa1700000 /* IPL loads SPL here */
+#define CONFIG_SPL_STACK        0x5c040000 /* end of internal SRAM */
+#define CONFIG_SPL_NAND_SUPPORT /* build libnand for spl */
+#define CONFIG_SPL_NAND_DOCG4   /* use lean docg4 nand spl driver */
+#define CONFIG_SPL_LIBGENERIC_SUPPORT  /* spl uses memcpy */
+
+/*
+ * NAND
+ */
+#define CONFIG_NAND_DOCG4
+#define CONFIG_SYS_NAND_SELF_INIT
+#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* only one device */
+#define CONFIG_SYS_NAND_BASE 0x00000000 /* mapped to reset vector */
+#define CONFIG_SYS_NAND_PAGE_SIZE 0x200
+#define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000
+#define CONFIG_BITREVERSE       /* needed by docg4 driver */
+#define CONFIG_BCH              /* needed by docg4 driver */
+
+/*
+ * IMPORTANT NOTE: this is the size of the concatenated spl + u-boot image.  It
+ * will be rounded up to the next 64k boundary (the spl flash block size), so it
+ * does not have to be exact, but you must ensure that it is not less than the
+ * actual image size, or it may fail to boot (bricked phone)!
+ * (Tip: reduces to three blocks with lcd and mmc support removed from u-boot.)
+*/
+#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x40000 /* four 64k flash blocks */
+
+/*
+ * This is the byte offset into the flash at which the concatenated spl + u-boot
+ * image is placed.  It must be at the start of a block (256k boundary).  Blocks
+ * 0 - 5 are write-protected, so we start at block 6.
+ */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x180000  /* block 6 */
+
+/* DRAM address to which u-boot proper is loaded (before it relocates itself) */
+#define CONFIG_SYS_NAND_U_BOOT_DST  0xa0000000
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
+
+/* passed to linker by Makefile as arg to -Ttext option */
+#define CONFIG_SYS_TEXT_BASE 0xa0000000
+
+#define CONFIG_SYS_INIT_SP_ADDR         0x5c040000 /* end of internal SRAM */
+
+/*
+ * environment
+ */
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_BUILD_ENVCRC
+#define CONFIG_ENV_SIZE 0x200
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_EXTRA_ENV_SETTINGS  \
+	"stdin=usbtty\0"           \
+	"stdout=usbtty\0"          \
+	"stderr=usbtty"
+#define CONFIG_BOOTARGS "mtdparts=Msys_Diskonchip_G4:1536k(protected_part)ro,1024k(bootloader_part),-(filesys_part) \
+ip=192.168.11.102:::255.255.255.0:treo:usb0"
+#define CONFIG_BOOTDELAY   3
+
+#if 0 /* example: try 2nd mmc partition, then nand */
+#define CONFIG_BOOTCOMMAND                                              \
+	"mmc rescan; "                                                  \
+	"if mmcinfo && ext2load mmc 0:2 0xa1000000 uImage; then "       \
+	    "bootm 0xa1000000; "					\
+	"elif nand read 0xa1000000 0x280000 0x240000; then "            \
+	    "bootm 0xa1000000; "					\
+	"fi; "
+#endif
+
+/* u-boot lives at end of SDRAM, so use start of SDRAM for stand alone apps */
+#define CONFIG_STANDALONE_LOAD_ADDR 0xa0000000
+
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_SYS_ICACHE_OFF
+
+#endif  /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/paz00.h b/qemu/roms/u-boot/include/configs/paz00.h
new file mode 100644
index 000000000..dd0abf8de
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/paz00.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2010-2012 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+#include "tegra20-common.h"
+
+/* Enable fdt support for Paz00. Flash the image in u-boot-dtb.bin */
+#define CONFIG_DEFAULT_DEVICE_TREE	tegra20-paz00
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
+/* High-level configuration options */
+#define V_PROMPT		"Tegra20 (Paz00) MOD # "
+#define CONFIG_TEGRA_BOARD_STRING	"Compal Paz00"
+
+/* Board-specific serial config */
+#define CONFIG_TEGRA_ENABLE_UARTA
+#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_PAZ00
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_TEGRA_MMC
+#define CONFIG_CMD_MMC
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_SYS_MMC_ENV_PART 2
+
+/* USB Host support */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_TEGRA
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB
+
+/* USB networking support */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+
+/* General networking support */
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+
+/* LCD support */
+#define CONFIG_LCD
+#define CONFIG_PWM_TEGRA
+#define CONFIG_VIDEO_TEGRA
+#define LCD_BPP				LCD_COLOR16
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define CONFIG_CONSOLE_SCROLL_LINES	10
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/pb1x00.h b/qemu/roms/u-boot/include/configs/pb1x00.h
new file mode 100644
index 000000000..f92496571
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/pb1x00.h
@@ -0,0 +1,192 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * This file contains the configuration parameters for the dbau1x00 board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_PB1X00		1
+#define CONFIG_SOC_AU1X00	1  /* alchemy series cpu */
+
+#ifdef CONFIG_PB1000
+#define CONFIG_SOC_AU1000	1
+#else
+#ifdef CONFIG_PB1100
+#define CONFIG_SOC_AU1100	1
+#else
+#ifdef CONFIG_PB1500
+#define CONFIG_SOC_AU1500	1
+#else
+#error "No valid board set"
+#endif
+#endif
+#endif
+
+#define CONFIG_SYS_LITTLE_ENDIAN
+
+#define CONFIG_ETHADDR		DE:AD:BE:EF:01:01    /* Ethernet address */
+
+#define CONFIG_BOOTDELAY	2	/* autoboot after 2 seconds	*/
+
+#define CONFIG_BAUDRATE		115200
+
+#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"addmisc=setenv bootargs ${bootargs} "				\
+		"console=ttyS0,${baudrate} "				\
+		"panic=1\0"						\
+	"bootfile=/vmlinux.img\0"				\
+	"load=tftp 80500000 ${u-boot}\0"				\
+	""
+/* Boot from NFS root */
+#define CONFIG_BOOTCOMMAND	"bootp; setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; bootm"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_LONGHELP				/* undef to save memory      */
+#define	CONFIG_SYS_PROMPT		"Pb1x00 # "	/* Monitor Command Prompt    */
+#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size   */
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)  /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16		/* max number of command args*/
+
+#define CONFIG_SYS_MALLOC_LEN		128*1024
+
+#define CONFIG_SYS_BOOTPARAMS_LEN	128*1024
+
+#define CONFIG_SYS_MIPS_TIMER_FREQ	396000000
+
+#define CONFIG_SYS_SDRAM_BASE		0x80000000     /* Cached addr */
+
+#define	CONFIG_SYS_LOAD_ADDR		0x81000000     /* default load address	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x80100000
+#undef CONFIG_SYS_MEMTEST_START
+#define CONFIG_SYS_MEMTEST_START       0x80200000
+#define CONFIG_SYS_MEMTEST_END		0x83800000
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	(128)	/* max number of sectors on one chip */
+
+#define PHYS_FLASH_1		0xbec00000 /* Flash Bank #1 */
+#define PHYS_FLASH_2		0xbfc00000 /* Flash Bank #2 */
+
+/* The following #defines are needed to get flash environment right */
+#define	CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)
+
+#define CONFIG_SYS_INIT_SP_OFFSET	0x4000000
+
+/* We boot from this flash, selected with dip switch */
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_2
+
+/* timeout values are in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
+
+#define	CONFIG_ENV_IS_NOWHERE	1
+
+/* Address and size of Primary Environment Sector	*/
+#define CONFIG_ENV_ADDR		0xB0030000
+#define CONFIG_ENV_SIZE		0x10000
+
+#define CONFIG_FLASH_16BIT
+
+#define CONFIG_NR_DRAM_BANKS	2
+
+
+#define CONFIG_MEMSIZE_IN_BYTES
+
+
+/*---USB -------------------------------------------*/
+#if 0
+#define CONFIG_USB_OHCI
+#define CONFIG_USB_STORAGE
+#define CONFIG_DOS_PARTITION
+#endif
+
+/*---ATA PCMCIA ------------------------------------*/
+#if 0
+#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
+#define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000
+#define CONFIG_PCMCIA_SLOT_A
+
+#define CONFIG_ATAPI 1
+#define CONFIG_MAC_PARTITION 1
+
+/* We run CF in "true ide" mode or a harddrive via pcmcia */
+#define CONFIG_IDE_PCMCIA 1
+
+/* We only support one slot for now */
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_BASE_ADDR       CONFIG_SYS_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_DATA_OFFSET     8
+
+/* Offset for normal register accesses  */
+#define CONFIG_SYS_ATA_REG_OFFSET      0
+
+/* Offset for alternate registers       */
+#define CONFIG_SYS_ATA_ALT_OFFSET      0x0100
+
+#endif
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_DCACHE_SIZE		16384
+#define CONFIG_SYS_ICACHE_SIZE		16384
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+
+#undef CONFIG_CMD_SAVEENV
+#undef CONFIG_CMD_FAT
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IDE
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_RUN
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_ELF
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_BEDBUG
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/pcm030.h b/qemu/roms/u-boot/include/configs/pcm030.h
new file mode 100644
index 000000000..31a93c87d
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/pcm030.h
@@ -0,0 +1,433 @@
+/*
+ * (C) Copyright 2003-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2006
+ * Eric Schumann, Phytec Messatechnik GmbH
+ *
+ * (C) Copyright 2009
+ * Jon Smirl <jonsmirl@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_BOARDINFO	 "phyCORE-MPC5200B-tiny"
+
+/*-----------------------------------------------------------------------------
+High Level Configuration Options
+(easy to change)
+-----------------------------------------------------------------------------*/
+#define CONFIG_MPC5200		1	/* This is an MPC5200 CPU */
+#define CONFIG_MPC5200_DDR	1	/* (with DDR-SDRAM) */
+#define CONFIG_PHYCORE_MPC5200B_TINY 1	/* phyCORE-MPC5200B -> */
+					/* FEC configuration and IDE */
+
+/*
+ * Valid values for CONFIG_SYS_TEXT_BASE are:
+ * 0xFFF00000	boot high (standard configuration)
+ * 0xFF000000	boot low
+ * 0x00100000	boot from RAM (for testing only)
+ */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xFFF00000
+#endif
+
+#define CONFIG_SYS_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */
+
+/*-----------------------------------------------------------------------------
+Serial console configuration
+-----------------------------------------------------------------------------*/
+#define CONFIG_PSC_CONSOLE	3	/* console is on PSC3 -> */
+					/*define gps port conf. */
+					/* register later on to */
+					/*enable UART function! */
+#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+
+#define	CONFIG_TIMESTAMP	1	/* Print image info with timestamp */
+
+#if (CONFIG_SYS_TEXT_BASE == 0xFF000000)	/* Boot low */
+#define CONFIG_SYS_LOWBOOT 1
+#endif
+/* RAMBOOT will be defined automatically in memory section */
+
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT 		"nor0=physmap-flash.0"
+#define MTDPARTS_DEFAULT   	"mtdparts=physmap-flash.0:256k(ubootl)," \
+	"1792k(kernel),13312k(jffs2),256k(uboot)ro,256k(oftree),-(space)"
+
+/*-----------------------------------------------------------------------------
+Autobooting
+-----------------------------------------------------------------------------*/
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds */
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* allow stopping of boot process */
+					/* even with bootdelay=0 */
+#undef	CONFIG_BOOTARGS
+
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run bootcmd_net\" to load Kernel over TFTP and to "\
+		"mount root filesystem over NFS;" \
+	"echo"
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"uimage=uImage-pcm030\0"					\
+	"oftree=oftree-pcm030.dtb\0"					\
+	"jffs2=root-pcm030.jffs2\0" 					\
+	"uboot=u-boot-pcm030.bin\0"					\
+	"bargs_base=setenv bootargs console=ttyPSC0,$(baudrate)"	\
+		" $(mtdparts) rw\0" 					\
+	"bargs_flash=setenv bootargs $(bootargs) root=/dev/mtdblock2"	\
+		" rootfstype=jffs2\0" 					\
+	"bargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs"		\
+		" ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)::"	\
+		"$(netdev):off nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
+	"bcmd_net=run bargs_base bargs_nfs; tftpboot 0x500000 $(uimage);" \
+		" tftp 0x400000 $(oftree); bootm 0x500000 - 0x400000\0"	\
+	"bcmd_flash=run bargs_base bargs_flash; bootm 0xff040000 - "	\
+		"0xfff40000\0" 						\
+		" cp.b 0x400000 0xff040000 $(filesize)\0" 		\
+	"prg_jffs2=tftp 0x400000 $(jffs2); erase 0xff200000 0xffefffff; " \
+		"cp.b 0x400000 0xff200000 $(filesize)\0" 		\
+	"prg_oftree=tftp 0x400000 $(oftree); erase 0xfff40000 0xfff5ffff;" \
+		" cp.b 0x400000 0xfff40000 $(filesize)\0" 		\
+	"update=tftpboot 0x400000 $(uboot);erase 0xFFF00000 0xfff3ffff;" \
+		" cp.b 0x400000 0xFFF00000 $(filesize)\0"		\
+	"unlock=yes\0"							\
+	""
+
+#define CONFIG_BOOTCOMMAND		"run bcmd_flash"
+
+/*--------------------------------------------------------------------------
+IPB Bus clocking configuration.
+ ---------------------------------------------------------------------------*/
+#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK	/* define for 133MHz speed */
+
+/*-------------------------------------------------------------------------
+ * PCI Mapping:
+ * 0x40000000 - 0x4fffffff - PCI Memory
+ * 0x50000000 - 0x50ffffff - PCI IO Space
+ * -----------------------------------------------------------------------*/
+#define CONFIG_PCI			1
+#define CONFIG_PCI_PNP			1
+#define CONFIG_PCI_SCAN_SHOW		1
+#define CONFIG_PCI_MEM_BUS		0x40000000
+#define CONFIG_PCI_MEM_PHYS		CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE		0x10000000
+#define CONFIG_PCI_IO_BUS		0x50000000
+#define CONFIG_PCI_IO_PHYS		CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE		0x01000000
+#define CONFIG_SYS_XLB_PIPELINING	1
+
+/*---------------------------------------------------------------------------
+ I2C configuration
+---------------------------------------------------------------------------*/
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
+#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+
+/*---------------------------------------------------------------------------
+ EEPROM CAT24WC32 configuration
+---------------------------------------------------------------------------*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x52	/* 1010100x */
+#define CONFIG_SYS_I2C_FACT_ADDR	0x52	/* EEPROM CAT24WC32 */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2	/* Bytes of address */
+#define CONFIG_SYS_EEPROM_SIZE		2048
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 15
+
+/*---------------------------------------------------------------------------
+RTC configuration
+---------------------------------------------------------------------------*/
+#define RTC
+#define CONFIG_RTC_PCF8563		1
+#define CONFIG_SYS_I2C_RTC_ADDR		0x51
+
+/*---------------------------------------------------------------------------
+ Flash configuration
+---------------------------------------------------------------------------*/
+
+#define CONFIG_SYS_FLASH_BASE		0xff000000
+#define CONFIG_SYS_FLASH_SIZE		0x01000000
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_MAX_FLASH_SECT 260 /* max num of sects on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
+						/* (= chip selects) */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/*
+ * Use also hardware protection. This seems required, as the BDI uses
+ * hardware protection. Without this, U-Boot can't work with this sectors,
+ * as its protection is software only by default
+ */
+#define CONFIG_SYS_FLASH_PROTECTION	1
+
+/*---------------------------------------------------------------------------
+ Environment settings
+---------------------------------------------------------------------------*/
+
+/* pcm030 ships with environment is EEPROM by default */
+#define CONFIG_ENV_IS_IN_EEPROM	1
+#define CONFIG_ENV_OFFSET	0x00	/* environment starts at the */
+					/*beginning of the EEPROM */
+#define CONFIG_ENV_SIZE		CONFIG_SYS_EEPROM_SIZE
+
+#define CONFIG_ENV_OVERWRITE	1
+
+/*-----------------------------------------------------------------------------
+  Memory map
+-----------------------------------------------------------------------------*/
+#define CONFIG_SYS_MBAR	0xF0000000	/* MBAR has to be switched by other */
+					/* bootloader or debugger config */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR		0x80000000
+/* Use SRAM until RAM will be available */
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used */
+								/* area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+						GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#	define CONFIG_SYS_RAMBOOT		1
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------------
+ Ethernet configuration
+-----------------------------------------------------------------------------*/
+#define CONFIG_MPC5xxx_FEC		1
+#define CONFIG_MPC5xxx_FEC_MII100
+#define CONFIG_PHY_ADDR			0x01
+
+/*---------------------------------------------------------------------------
+ GPIO configuration
+ ---------------------------------------------------------------------------*/
+
+/* GPIO port configuration
+ *
+ * Pin mapping:
+ *
+ * [29:31] = 01x
+ * PSC1_0 -> AC97 SDATA out
+ * PSC1_1 -> AC97 SDTA in
+ * PSC1_2 -> AC97 SYNC out
+ * PSC1_3 -> AC97 bitclock out
+ * PSC1_4 -> AC97 reset out
+ *
+ * [25:27] = 001
+ * PSC2_0 -> CAN 1 Tx out
+ * PSC2_1 -> CAN 1 Rx in
+ * PSC2_2 -> CAN 2 Tx out
+ * PSC2_3 -> CAN 2 Rx in
+ * PSC2_4 -> GPIO (claimed for ATA reset, active low)
+ *
+ *
+ * [20:23] = 1100
+ * PSC3_0 -> UART Tx out
+ * PSC3_1 -> UART Rx in
+ * PSC3_2 -> UART RTS (in/out FIXME)
+ * PSC3_3 -> UART CTS (in/out FIXME)
+ * PSC3_4 -> LocalPlus Bus CS6 \
+ * PSC3_5 -> LocalPlus Bus CS7 / --> see [4] and [5]
+ * PSC3_6 -> dedicated SPI MOSI out (master case)
+ * PSC3_7 -> dedicated SPI MISO in (master case)
+ * PSC3_8 -> dedicated SPI SS out (master case)
+ * PSC3_9 -> dedicated SPI CLK out (master case)
+ *
+ * [18:19] = 01
+ * USB_0 -> USB OE out
+ * USB_1 -> USB Tx- out
+ * USB_2 -> USB Tx+ out
+ * USB_3 -> USB RxD (in/out FIXME)
+ * USB_4 -> USB Rx+ in
+ * USB_5 -> USB Rx- in
+ * USB_6 -> USB PortPower out
+ * USB_7 -> USB speed out
+ * USB_8 -> USB suspend (in/out FIXME)
+ * USB_9 -> USB overcurrent in
+ *
+ * [17] = 0
+ * USB differential mode
+ *
+ * [16] = 0
+ * PCI enabled
+ *
+ * [12:15] = 0101
+ * ETH_0 -> ETH Txen
+ * ETH_1 -> ETH TxD0
+ * ETH_2 -> ETH TxD1
+ * ETH_3 -> ETH TxD2
+ * ETH_4 -> ETH TxD3
+ * ETH_5 -> ETH Txerr
+ * ETH_6 -> ETH MDC
+ * ETH_7 -> ETH MDIO
+ * ETH_8 -> ETH RxDv
+ * ETH_9 -> ETH RxCLK
+ * ETH_10 -> ETH Collision
+ * ETH_11 -> ETH TxD
+ * ETH_12 -> ETH RxD0
+ * ETH_13 -> ETH RxD1
+ * ETH_14 -> ETH RxD2
+ * ETH_15 -> ETH RxD3
+ * ETH_16 -> ETH Rxerr
+ * ETH_17 -> ETH CRS
+ *
+ * [9:11] = 101
+ * PSC6_0 -> UART RxD in
+ * PSC6_1 -> UART CTS (in/out FIXME)
+ * PSC6_2 -> UART TxD out
+ * PSC6_3 -> UART RTS (in/out FIXME)
+ *
+ * [2:3/6:7] = 00/11
+ * TMR_0 -> ATA_CS0 out
+ * TMR_1 -> ATA_CS1 out
+ * TMR_2 -> GPIO
+ * TMR_3 -> GPIO
+ * TMR_4 -> GPIO
+ * TMR_5 -> GPIO
+ * TMR_6 -> GPIO
+ * TMR_7 -> GPIO
+ * I2C_0 -> I2C 1 Clock out
+ * I2C_1 -> I2C 1 IO in/out
+ * I2C_2 -> I2C 2 Clock out
+ * I2C_3 -> I2C 2 IO in/out
+ *
+ * [4] = 1
+ * PSC3_5 is used as CS7
+ *
+ * [5] = 1
+ * PSC3_4 is used as CS6
+ *
+ * [1] = 0
+ * gpio_wkup_7 is GPIO
+ *
+ * [0] = 0
+ * gpio_wkup_6 is GPIO
+ *
+ */
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x0f551c12
+
+/*-----------------------------------------------------------------------------
+ Miscellaneous configurable options
+-------------------------------------------------------------------------------*/
+#define CONFIG_SYS_LONGHELP	/* undef to save memory */
+#define CONFIG_SYS_PROMPT "uboot> " /* Monitor Command Prompt */
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+
+#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+							/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
+
+#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
+
+#define CONFIG_DISPLAY_BOARDINFO 1
+
+/*-----------------------------------------------------------------------------
+ Various low-level settings
+-----------------------------------------------------------------------------*/
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
+
+/* no burst access on the LPB */
+#define CONFIG_SYS_CS_BURST		0x00000000
+/* one deadcycle for the 33MHz statemachine */
+#define CONFIG_SYS_CS_DEADCYCLE		0x33333331
+/* one additional waitstate for the 33MHz statemachine */
+#define CONFIG_SYS_BOOTCS_CFG		0x0001dd00
+#define CONFIG_SYS_BOOTCS_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+
+#define CONFIG_SYS_RESET_ADDRESS 	0xff000000
+
+/*-----------------------------------------------------------------------
+ * USB stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_USB_CLOCK		0x0001BBBB
+#define CONFIG_USB_CONFIG		0x00001000
+
+/*---------------------------------------------------------------------------
+ IDE/ATA stuff Supports IDE harddisk
+----------------------------------------------------------------------------*/
+
+#undef  CONFIG_IDE_8xx_PCCARD	/* Use IDE with PC Card Adapter */
+#undef	CONFIG_IDE_8xx_DIRECT	/* Direct IDE not supported */
+#undef	CONFIG_IDE_LED		/* LED for ide not supported */
+#define CONFIG_SYS_ATA_CS_ON_TIMER01
+#define	CONFIG_IDE_RESET 1	/* reset for ide supported */
+#define CONFIG_IDE_PREINIT
+#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
+#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
+/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
+/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)
+/* Interval between registers */
+#define CONFIG_SYS_ATA_STRIDE		4
+#define CONFIG_ATAPI			1
+
+/* we enable IDE and FAT support, so we also need partition support */
+#define CONFIG_DOS_PARTITION 1
+
+/* USB */
+#define CONFIG_USB_OHCI
+#define CONFIG_USB_STORAGE
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT		1
+#define CONFIG_OF_BOARD_SETUP		1
+
+#define OF_CPU				"PowerPC,5200@0"
+#define OF_TBCLK			CONFIG_SYS_MPC5XXX_CLKIN
+#define OF_SOC				"soc5200@f0000000"
+#define OF_STDOUT_PATH			"/soc5200@f0000000/serial@2400"
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/pcm051.h b/qemu/roms/u-boot/include/configs/pcm051.h
new file mode 100644
index 000000000..9af3efd4b
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/pcm051.h
@@ -0,0 +1,302 @@
+/*
+ * pcm051.h
+ *
+ * Phytec phyCORE-AM335x (pcm051) boards information header
+ *
+ * Copyright (C) 2013 Lemonage Software GmbH
+ * Author Lars Poeschel <poeschel@lemonage.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __CONFIG_PCM051_H
+#define __CONFIG_PCM051_H
+
+#define CONFIG_AM33XX
+#define CONFIG_OMAP
+#define CONFIG_OMAP_COMMON
+
+#include <asm/arch/omap.h>
+
+#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
+#define CONFIG_SYS_MALLOC_LEN		(1024 << 10)
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT		"U-Boot# "
+#define CONFIG_SYS_NO_FLASH
+#define MACH_TYPE_PCM051		4144	/* Until the next sync */
+#define CONFIG_MACH_TYPE		MACH_TYPE_PCM051
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_VERSION_VARIABLE
+
+/* set to negative value for no autoboot */
+#define CONFIG_BOOTDELAY		1
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x80007fc0\0" \
+	"fdtaddr=0x80000000\0" \
+	"rdaddr=0x81000000\0" \
+	"bootfile=uImage\0" \
+	"fdtfile=pcm051.dtb\0" \
+	"console=ttyO0,115200n8\0" \
+	"optargs=\0" \
+	"mmcdev=0\0" \
+	"mmcroot=/dev/mmcblk0p2 ro\0" \
+	"mmcrootfstype=ext4 rootwait\0" \
+	"ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \
+	"ramrootfstype=ext2\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0" \
+	"bootenv=uEnv.txt\0" \
+	"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
+	"importbootenv=echo Importing environment from mmc ...; " \
+		"env import -t $loadaddr $filesize\0" \
+	"ramargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${ramroot} " \
+		"rootfstype=${ramrootfstype}\0" \
+	"loadramdisk=fatload mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
+	"loaduimagefat=fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \
+	"loaduimage=ext2load mmc ${mmcdev}:2 ${loadaddr} ${bootfile}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0" \
+	"ramboot=echo Booting from ramdisk ...; " \
+		"run ramargs; " \
+		"bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"echo SD/MMC found on device ${mmcdev};" \
+		"if run loadbootenv; then " \
+			"echo Loaded environment from ${bootenv};" \
+			"run importbootenv;" \
+		"fi;" \
+		"if test -n $uenvcmd; then " \
+			"echo Running uenvcmd ...;" \
+			"run uenvcmd;" \
+		"fi;" \
+		"if run loaduimage; then " \
+			"run mmcboot;" \
+		"fi;" \
+	"fi;" \
+
+/* Clock Defines */
+#define V_OSCK				25000000  /* Clock output from T2 */
+#define V_SCLK				(V_OSCK)
+
+#define CONFIG_CMD_ECHO
+
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS		16
+
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		512
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE \
+					+ sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+/*
+ * memtest works on 8 MB in DRAM after skipping 32MB from
+ * start addr of ram disk
+ */
+#define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE + (64 << 20))
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START \
+					+ (8 * 1024 * 1024))
+
+#define CONFIG_SYS_LOAD_ADDR		0x80007fc0 /* Default load address */
+
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_CMD_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+
+#define CONFIG_SPI
+#define CONFIG_OMAP3_SPI
+#define CONFIG_MTD_DEVICE
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED		24000000
+
+ /* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS		1		/*  1 bank of DRAM */
+#define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 19)	/* 512MiB */
+
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CONFIG_SYS_INIT_SP_ADDR         (NON_SECURE_SRAM_END - \
+						GENERATED_GBL_DATA_SIZE)
+ /* Platform/Board specific defs */
+#define CONFIG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
+#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
+
+#define CONFIG_CONS_INDEX		1
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		(48000000)
+#define CONFIG_SYS_NS16550_COM1		0x44e09000	/* Base EVM has UART0 */
+#define CONFIG_SYS_NS16550_COM2		0x48022000	/* UART1 */
+#define CONFIG_SYS_NS16550_COM3		0x48024000	/* UART2 */
+#define CONFIG_SYS_NS16550_COM4		0x481a6000	/* UART3 */
+#define CONFIG_SYS_NS16550_COM5		0x481a8000	/* UART4 */
+#define CONFIG_SYS_NS16550_COM6		0x481aa000	/* UART5 */
+
+/* I2C Configuration */
+#define CONFIG_I2C
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
+#define CONFIG_SYS_I2C_OMAP24XX
+#define CONFIG_CMD_EEPROM
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* Main EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+
+#define CONFIG_OMAP_GPIO
+
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 110, 300, 600, 1200, 2400, \
+4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 }
+
+/* CPU */
+#define CONFIG_ARCH_CPU_INIT
+
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+
+#define CONFIG_ENV_IS_NOWHERE
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_BOARD_INIT
+/*
+ * Place the image at the start of the ROM defined image space.
+ * We limit our size to the ROM-defined downloaded image area, and use the
+ * rest of the space for stack.
+ */
+#define CONFIG_SPL_TEXT_BASE		0x402F0400
+#define CONFIG_SPL_MAX_SIZE		(0x4030C000 - CONFIG_SPL_TEXT_BASE)
+#define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
+
+#define CONFIG_SPL_BSS_START_ADDR	0x80000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
+
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_YMODEM_SUPPORT
+#define CONFIG_SPL_NET_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_NET_VCI_STRING	"pcm051 U-Boot SPL"
+#define CONFIG_SPL_ETH_SUPPORT
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_BUS		0
+#define CONFIG_SPL_SPI_CS		0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x20000
+#define CONFIG_SYS_SPI_U_BOOT_SIZE	0x40000
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/am33xx/u-boot-spl.lds"
+
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * other needs.
+ */
+#define CONFIG_SYS_TEXT_BASE		0x80800000
+#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
+
+/* Since SPL did pll and ddr initialization for us,
+ * we don't need to do it twice.
+ */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+/*
+ * USB configuration
+ */
+#define CONFIG_USB_MUSB_DSPS
+#define CONFIG_ARCH_MISC_INIT
+#define CONFIG_MUSB_GADGET
+#define CONFIG_MUSB_PIO_ONLY
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_MUSB_HOST
+#define CONFIG_AM335X_USB0
+#define CONFIG_AM335X_USB0_MODE	MUSB_PERIPHERAL
+#define CONFIG_AM335X_USB1
+#define CONFIG_AM335X_USB1_MODE MUSB_HOST
+
+#ifdef CONFIG_MUSB_HOST
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#endif
+
+#ifdef CONFIG_MUSB_GADGET
+#define CONFIG_USB_ETHER
+#define CONFIG_USB_ETH_RNDIS
+#endif /* CONFIG_MUSB_GADGET */
+
+/* Unsupported features */
+#undef CONFIG_USE_IRQ
+
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_DRIVER_TI_CPSW
+#define CONFIG_MII
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_NET_RETRY_COUNT         10
+#define CONFIG_NET_MULTI
+#define CONFIG_PHY_GIGE
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_SMSC
+
+#endif	/* ! __CONFIG_PCM051_H */
diff --git a/qemu/roms/u-boot/include/configs/pcs440ep.h b/qemu/roms/u-boot/include/configs/pcs440ep.h
new file mode 100644
index 000000000..e6e06f2d2
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/pcs440ep.h
@@ -0,0 +1,460 @@
+/*
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/************************************************************************
+ * pcs440ep.h - configuration for PCS440EP board
+ ***********************************************************************/
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+
+/* new uImage format support */
+#define CONFIG_FIT		1
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_FIT_VERBOSE	1 /* enable fit_format_{error,warning}() */
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_PCS440EP		1	/* Board is PCS440EP            */
+#define CONFIG_440EP		1	/* Specific PPC440EP support    */
+#define CONFIG_440		1	/* ... PPC440 family	        */
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFA0000
+
+#define CONFIG_SYS_CLK_FREQ	33333333    /* external freq to pll	*/
+
+#define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f	*/
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_MONITOR_LEN		(384 * 1024)	/* Reserve 384 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_BASE	(-CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_SDRAM_BASE	        0x00000000	    /* _must_ be 0	*/
+#define CONFIG_SYS_FLASH_BASE	        0xfff00000	    /* start of FLASH	*/
+#define CONFIG_SYS_PCI_MEMBASE	        0xa0000000	    /* mapped pci memory*/
+#define CONFIG_SYS_PCI_MEMBASE1        CONFIG_SYS_PCI_MEMBASE  + 0x10000000
+#define CONFIG_SYS_PCI_MEMBASE2        CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
+#define CONFIG_SYS_PCI_MEMBASE3        CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
+
+/*Don't change either of these*/
+#define CONFIG_SYS_PCI_BASE	        0xe0000000	    /* internal PCI regs*/
+/*Don't change either of these*/
+
+#define CONFIG_SYS_USB_DEVICE          0x50000000
+#define CONFIG_SYS_BOOT_BASE_ADDR      0xf0000000
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in SDRAM)
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_INIT_RAM_DCACHE	1		/* d-cache as init ram	*/
+#define CONFIG_SYS_INIT_RAM_ADDR	0x70000000		/* DCache       */
+#define CONFIG_SYS_INIT_RAM_SIZE	(4 << 10)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+#undef CONFIG_SYS_EXT_SERIAL_CLOCK		/* no external clk used		*/
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+#define CONFIG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned char	/* flash word size (width)	*/
+#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
+#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	0x10000	/* size of one complete sector		*/
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
+
+#define CONFIG_ENV_OVERWRITE	1
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+#endif /* CONFIG_ENV_IS_IN_FLASH */
+
+#define ENV_NAME_REVLEV	"revision_level"
+#define ENV_NAME_SOLDER	"solder_switch"
+#define ENV_NAME_DIP	"dip"
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for setup             */
+#undef CONFIG_DDR_ECC			/* don't use ECC			*/
+#define SPD_EEPROM_ADDRESS      {0x50}
+#define	CONFIG_PROG_SDRAM_TLB	1
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		100000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	(0xa4>>1)
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"hostname=pcs440ep\0"						\
+	"use_eeprom_ethaddr=default\0"					\
+	"cs_test=off\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
+		"bootm\0"						\
+	"rootpath=/opt/eldk/ppc_4xx\0"					\
+	"bootfile=/tftpboot/pcs440ep/uImage\0"				\
+	"kernel_addr=FFF00000\0"					\
+	"ramdisk_addr=FFF00000\0"					\
+	"load=tftp 100000 /tftpboot/pcs440ep/u-boot.bin\0"		\
+	"update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;"	\
+		"cp.b 100000 FFFA0000 60000\0"			        \
+	"upd=run load update\0"						\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+/* check U-Boot image with SHA1 sum */
+#define CONFIG_SHA1_CHECK_UB_IMG	1
+#define CONFIG_SHA1_START		CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SHA1_LEN			CONFIG_SYS_MONITOR_LEN
+
+/*-----------------------------------------------------------------------
+ * Definitions for status LED
+ */
+#define CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+#define CONFIG_BOARD_SPECIFIC_LED	1
+
+#define STATUS_LED_BIT		0x08			/* DIAG1 is on GPIO_PPC_1 */
+#define STATUS_LED_PERIOD	((CONFIG_SYS_HZ / 2) / 5)	/* blink at 5 Hz */
+#define STATUS_LED_STATE	STATUS_LED_OFF
+#define STATUS_LED_BIT1		0x04			/* DIAG2 is on GPIO_PPC_2 */
+#define STATUS_LED_PERIOD1	((CONFIG_SYS_HZ / 2) / 5)	/* blink at 5 Hz */
+#define STATUS_LED_STATE1	STATUS_LED_ON
+#define STATUS_LED_BIT2		0x02			/* DIAG3 is on GPIO_PPC_3 */
+#define STATUS_LED_PERIOD2	((CONFIG_SYS_HZ / 2) / 5)	/* blink at 5 Hz */
+#define STATUS_LED_STATE2	STATUS_LED_OFF
+#define STATUS_LED_BIT3		0x01			/* DIAG4 is on GPIO_PPC_4 */
+#define STATUS_LED_PERIOD3	((CONFIG_SYS_HZ / 2) / 5)	/* blink at 5 Hz */
+#define STATUS_LED_STATE3	STATUS_LED_OFF
+
+#define CONFIG_SHOW_BOOT_PROGRESS	1
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_PPC4xx_EMAC
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
+#define CONFIG_PHY_ADDR		1	/* PHY address, See schematics	*/
+#define CONFIG_PHY1_ADDR        2
+
+#define CONFIG_SYS_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */
+
+#define CONFIG_NETCONSOLE		/* include NetConsole support	*/
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+#ifdef CONFIG_440EP
+/* USB */
+#define CONFIG_USB_OHCI
+#define CONFIG_USB_STORAGE
+
+/*Comment this out to enable USB 1.1 device*/
+#define USB_2_0_DEVICE
+#endif /*CONFIG_440EP*/
+
+#ifdef DEBUG
+#define CONFIG_PANIC_HANG
+#else
+#define CONFIG_HW_WATCHDOG			/* watchdog */
+#endif
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_REISER
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_USB
+
+#define CONFIG_SUPPORT_VFAT
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	        1024	/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	        256	/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	        16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	        CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000 /* memtest works on	        */
+#define CONFIG_SYS_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+#define CONFIG_LYNXKDI          1       /* support kdi files            */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+/* General PCI */
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#undef  CONFIG_PCI_PNP			/* do (not) pci plug-and-play   */
+#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
+#define CONFIG_SYS_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
+
+/* Board-specific PCI */
+#define CONFIG_SYS_PCI_TARGET_INIT
+#define CONFIG_SYS_PCI_MASTER_INIT
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
+#define CONFIG_SYS_PCI_SUBSYS_ID       0xcafe	/* Whatever */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ *----------------------------------------------------------------------*/
+#define FLASH_BASE0_PRELIM	0xFFF00000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0xFFF80000	/* FLASH bank #1	*/
+
+#define CONFIG_SYS_FLASH		FLASH_BASE0_PRELIM
+#define CONFIG_SYS_SRAM		0xF1000000
+#define CONFIG_SYS_FPGA		0xF2000000
+#define CONFIG_SYS_CF1			0xF0000000
+#define CONFIG_SYS_CF2			0xF0100000
+
+/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
+#define CONFIG_SYS_EBC_PB0AP		0x02010000	/* TWT=4,OEN=1			*/
+#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_FLASH | 0x18000) /* BS=1MB,BU=R/W,BW=8bit	*/
+
+/* Memory Bank 1 (SRAM) initialization						*/
+#define CONFIG_SYS_EBC_PB1AP		0x01810040	/* TWT=3,OEN=1,BEM=1		*/
+#define CONFIG_SYS_EBC_PB1CR		(CONFIG_SYS_SRAM | 0x5A000) /* BS=4MB,BU=R/W,BW=16bit	*/
+
+/* Memory Bank 2 (FPGA) initialization						*/
+#define CONFIG_SYS_EBC_PB2AP		0x01010440	/* TWT=2,OEN=1,TH=2,BEM=1	*/
+#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_FPGA | 0x5A000) /* BS=4MB,BU=R/W,BW=16bit	*/
+
+/* Memory Bank 3 (CompactFlash) initialization					*/
+#define CONFIG_SYS_EBC_PB3AP		0x080BD400
+#define CONFIG_SYS_EBC_PB3CR		(CONFIG_SYS_CF1 | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit	*/
+
+/* Memory Bank 4 (CompactFlash) initialization					*/
+#define CONFIG_SYS_EBC_PB4AP		0x080BD400
+#define CONFIG_SYS_EBC_PB4CR		(CONFIG_SYS_CF2 | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit	*/
+
+/*-----------------------------------------------------------------------
+ * PPC440 GPIO Configuration
+ */
+#define CONFIG_SYS_4xx_GPIO_TABLE { /*	  Out		       GPIO	Alternate1	Alternate2   Alternate3 */ \
+{											\
+/* GPIO Core 0 */									\
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO0	EBC_ADDR(7)	DMA_REQ(2)	*/ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO1	EBC_ADDR(6)	DMA_ACK(2)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO2	EBC_ADDR(5)	DMA_EOT/TC(2)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO3	EBC_ADDR(4)	DMA_REQ(3)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO4	EBC_ADDR(3)	DMA_ACK(3)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO5	EBC_ADDR(2)	DMA_EOT/TC(3)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO6	EBC_CS_N(1)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO7	EBC_CS_N(2)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO8	EBC_CS_N(3)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO9	EBC_CS_N(4)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO10	EBC_CS_N(5)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO11	EBC_BUS_ERR			*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO12	ZII_p0Rxd(0)			*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO13	ZII_p0Rxd(1)			*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO14	ZII_p0Rxd(2)			*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO15	ZII_p0Rxd(3)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO16	ZII_p0Txd(0)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO17	ZII_p0Txd(1)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO18	ZII_p0Txd(2)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO19	ZII_p0Txd(3)			*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO20	ZII_p0Rx_er			*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO21	ZII_p0Rx_dv			*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO22	ZII_p0RxCrs			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO23	ZII_p0Tx_er			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO24	ZII_p0Tx_en			*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO25	ZII_p0Col			*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO26			USB2D_RXVALID	*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO27	EXT_EBC_REQ	USB2D_RXERROR	*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO28			USB2D_TXVALID	*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO29	EBC_EXT_HDLA	USB2D_PAD_SUSPNDM */	\
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO30	EBC_EXT_ACK	USB2D_XCVRSELECT*/	\
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO31	EBC_EXR_BUSREQ	USB2D_TERMSELECT*/	\
+},											\
+{											\
+/* GPIO Core 1 */									\
+{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO32	USB2D_OPMODE0			*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO33	USB2D_OPMODE1			*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_NO_CHG}, /* GPIO34	UART0_DCD_N	UART1_DSR_CTS_N	UART2_SOUT*/ \
+{GPIO1_BASE, GPIO_IN,  GPIO_ALT3, GPIO_OUT_NO_CHG}, /* GPIO35	UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
+{GPIO1_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO36	UART0_8PIN_CTS_N		UART3_SIN*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO37	UART0_RTS_N			*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_NO_CHG}, /* GPIO38	UART0_DTR_N	UART1_SOUT	*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_ALT2, GPIO_OUT_NO_CHG}, /* GPIO39	UART0_RI_N	UART1_SIN	*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO40	UIC_IRQ(0)			*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO41	UIC_IRQ(1)			*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO42	UIC_IRQ(2)			*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO43	UIC_IRQ(3)			*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO44	UIC_IRQ(4)	DMA_ACK(1)	*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO45	UIC_IRQ(6)	DMA_EOT/TC(1)	*/	\
+{GPIO1_BASE, GPIO_BI,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO46	UIC_IRQ(7)	DMA_REQ(0)	*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO47	UIC_IRQ(8)	DMA_ACK(0)	*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO48	UIC_IRQ(9)	DMA_EOT/TC(0)	*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO49  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO50  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO51  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO52  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO53  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO54  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO55  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO56  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO57  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO58  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO59  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO60  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO61  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO62  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN,  GPIO_SEL, GPIO_OUT_NO_CHG},  /* GPIO63  Unselect via TraceSelect Bit	*/	\
+}											\
+}
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+
+#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/
+
+#undef  CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef  CONFIG_IDE_LED			/* LED   for ide not supported	*/
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 2 drives per IDE bus	*/
+
+#define CONFIG_IDE_PREINIT	1
+#define CONFIG_IDE_RESET	1
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_CF1
+
+/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	0
+
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x0000)
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/pdm360ng.h b/qemu/roms/u-boot/include/configs/pdm360ng.h
new file mode 100644
index 000000000..553eb8f96
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/pdm360ng.h
@@ -0,0 +1,481 @@
+/*
+ * (C) Copyright 2009-2010
+ * Michael Weiß, ifm ecomatic gmbh, michael.weiss@ifm.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * pdm360ng board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_PDM360NG 1
+
+/*
+ * Memory map for the PDM360NG board:
+ *
+ * 0x0000_0000 - 0x1FFF_FFFF	DDR RAM (512 MB)
+ * 0x2000_0000 - 0x3FFF_FFFF	reserved (DDR RAM (512 MB)
+ * 0x5000_0000 - 0x5001_FFFF	SRAM (128 KB)
+ * 0x5004_0000 - 0x5005_FFFF	MRAM (CS2) (128 KB)
+ * 0x8000_0000 - 0x803F_FFFF	IMMR (4 MB)
+ * 0xF000_0000 - 0xF7FF_FFFF	NOR FLASH (CS0) (128 MB)
+ * 0xF800_0000 - 0xFFFF_FFFF	NOR FLASH (CS1) (128 MB) optional
+ */
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1	/* E300 Family */
+#define CONFIG_FSL_DIU_FB	1	/* FSL DIU */
+
+#define	CONFIG_SYS_TEXT_BASE	0xF0000000
+
+/* Used for silent command in environment */
+#define CONFIG_SYS_DEVICE_NULLDEV
+#define CONFIG_SILENT_CONSOLE
+
+/* Video */
+#define CONFIG_VIDEO
+
+#if defined(CONFIG_VIDEO)
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_RLE8
+#endif
+
+#define CONFIG_SYS_MPC512X_CLKIN	33333333	/* in Hz */
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_SYS_IMMR			0x80000000
+#define CONFIG_SYS_DIU_ADDR		((CONFIG_SYS_IMMR) + 0x2100)
+
+/*
+ * DDR Setup
+ */
+
+/* DDR is system memory */
+#define CONFIG_SYS_DDR_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_MAX_RAM_SIZE		0x40000000
+
+/* DDR pin mux and slew rate */
+#define CONFIG_SYS_IOCTRL_MUX_DDR	0x00000012
+
+/* Manually set all parameters as there's no SPD etc. */
+/*
+ * DDR Controller Configuration for Micron DDR2 SDRAM MT47H128M8-3
+ *
+ * SYS_CFG:
+ *	[31:31]	MDDRC Soft Reset:	Diabled
+ *	[30:30]	DRAM CKE pin:		Enabled
+ *	[29:29]	DRAM CLK:		Enabled
+ *	[28:28]	Command Mode:		Enabled (For initialization only)
+ *	[27:25]	DRAM Row Select:	dram_row[15:0] = magenta_address[25:10]
+ *	[24:21]	DRAM Bank Select:	dram_bank[1:0] = magenta_address[11:10]
+ *	[20:19]	Read Test:		DON'T USE
+ *	[18:18]	Self Refresh:		Enabled
+ *	[17:17]	16bit Mode:		Disabled
+ *	[16:13] Read Delay:		3
+ *	[12:12]	Half DQS Delay:		Disabled
+ *	[11:11]	Quarter DQS Delay:	Disabled
+ *	[10:08]	Write Delay:		2
+ *	[07:07]	Early ODT:		Disabled
+ *	[06:06]	On DIE Termination:	Enabled
+ *	[05:05]	FIFO Overflow Clear:	DON'T USE here
+ *	[04:04]	FIFO Underflow Clear:	DON'T USE here
+ *	[03:03]	FIFO Overflow Pending:	DON'T USE here
+ *	[02:02]	FIFO Underlfow Pending:	DON'T USE here
+ *	[01:01]	FIFO Overlfow Enabled:	Enabled
+ *	[00:00]	FIFO Underflow Enabled:	Enabled
+ * TIME_CFG0
+ *	[31:16]	DRAM Refresh Time:	0 CSB clocks
+ *	[15:8]	DRAM Command Time:	0 CSB clocks
+ *	[07:00]	DRAM Precharge Time:	0 CSB clocks
+ * TIME_CFG1
+ *	[31:26]	DRAM tRFC:
+ *	[25:21]	DRAM tWR1:
+ *	[20:17]	DRAM tWRT1:
+ *	[16:11]	DRAM tDRR:
+ *	[10:05]	DRAM tRC:
+ *	[04:00]	DRAM tRAS:
+ * TIME_CFG2
+ *	[31:28]	DRAM tRCD:
+ *	[27:23]	DRAM tFAW:
+ *	[22:19]	DRAM tRTW1:
+ *	[18:15]	DRAM tCCD:
+ *	[14:10] DRAM tRTP:
+ *	[09:05]	DRAM tRP:
+ *	[04:00] DRAM tRPA
+ */
+#define CONFIG_SYS_MDDRC_SYS_CFG	0xEA804A40
+#define CONFIG_SYS_MDDRC_TIME_CFG0	0x030C3D2E
+#define CONFIG_SYS_MDDRC_TIME_CFG1	0x68EC1168
+#define CONFIG_SYS_MDDRC_TIME_CFG2	0x34310864
+
+/*
+ * Alternative 1: small RAM (128 MB) configuration
+ */
+#define CONFIG_SYS_MDDRC_SYS_CFG_ALT1	0xE8604A40
+#define CONFIG_SYS_MDDRC_TIME_CFG0_ALT1	0x030C3D2E
+#define CONFIG_SYS_MDDRC_TIME_CFG1_ALT1	0x3CEC1168
+#define CONFIG_SYS_MDDRC_TIME_CFG2_ALT1	0x33310863
+
+#define CONFIG_SYS_MDDRC_SYS_CFG_EN	0xF0000000
+
+#define CONFIG_SYS_DDRCMD_NOP		0x01380000
+#define CONFIG_SYS_DDRCMD_PCHG_ALL	0x01100400
+#define CONFIG_SYS_DDRCMD_EM2		0x01020000  /* EMR2 */
+#define CONFIG_SYS_DDRCMD_EM3		0x01030000  /* EMR3 */
+/* EMR with 150 ohm ODT todo: verify */
+#define CONFIG_SYS_DDRCMD_EN_DLL	0x01010040
+#define CONFIG_SYS_DDRCMD_RES_DLL	0x01000100
+#define CONFIG_SYS_DDRCMD_RFSH		0x01080000
+#define CONFIG_SYS_MICRON_INIT_DEV_OP	0x01000432
+/* EMR with 150 ohm ODT todo: verify */
+#define CONFIG_SYS_DDRCMD_OCD_DEFAULT	0x010107C0
+/* EMR new command with 150 ohm ODT todo: verify */
+#define CONFIG_SYS_DDRCMD_OCD_EXIT	0x01010440
+
+/* DDR Priority Manager Configuration */
+#define CONFIG_SYS_MDDRCGRP_PM_CFG1	0x00077777
+#define CONFIG_SYS_MDDRCGRP_PM_CFG2	0x00000000
+#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG	0x00000001
+#define CONFIG_SYS_MDDRCGRP_LUT0_MU	0xFFEEDDCC
+#define CONFIG_SYS_MDDRCGRP_LUT0_ML	0xBBAAAAAA
+#define CONFIG_SYS_MDDRCGRP_LUT1_MU	0x66666666
+#define CONFIG_SYS_MDDRCGRP_LUT1_ML	0x55555555
+#define CONFIG_SYS_MDDRCGRP_LUT2_MU	0x44444444
+#define CONFIG_SYS_MDDRCGRP_LUT2_ML	0x44444444
+#define CONFIG_SYS_MDDRCGRP_LUT3_MU	0x55555555
+#define CONFIG_SYS_MDDRCGRP_LUT3_ML	0x55555558
+#define CONFIG_SYS_MDDRCGRP_LUT4_MU	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT4_ML	0x11111122
+#define CONFIG_SYS_MDDRCGRP_LUT0_AU	0xaaaaaaaa
+#define CONFIG_SYS_MDDRCGRP_LUT0_AL	0xaaaaaaaa
+#define CONFIG_SYS_MDDRCGRP_LUT1_AU	0x66666666
+#define CONFIG_SYS_MDDRCGRP_LUT1_AL	0x66666666
+#define CONFIG_SYS_MDDRCGRP_LUT2_AU	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT2_AL	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT3_AU	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT3_AL	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT4_AU	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT4_AL	0x11111111
+
+/*
+ * NOR FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_CFI		/* use Common Flash Interface */
+#define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+#define CONFIG_SYS_FLASH_BASE		0xF0000000 /* start of FLASH-Bank0 */
+#define CONFIG_SYS_FLASH_SIZE		0x08000000 /* max size of a Bank */
+/* start of FLASH-Bank1 */
+#define CONFIG_SYS_FLASH1_BASE		(CONFIG_SYS_FLASH_BASE + \
+					 CONFIG_SYS_FLASH_SIZE)
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max sectors per device */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
+#define CONFIG_SYS_FLASH_BANKS_LIST \
+	{CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH1_BASE}
+
+#define CONFIG_SYS_SRAM_BASE		0x50000000
+#define CONFIG_SYS_SRAM_SIZE		0x00020000	/* 128 KB */
+
+#define CONFIG_SYS_CS1_START		CONFIG_SYS_FLASH1_BASE
+#define CONFIG_SYS_CS1_SIZE		CONFIG_SYS_FLASH_SIZE
+
+/* ALE active low, data size 4 bytes */
+#define CONFIG_SYS_CS0_CFG		0x05059350
+/* ALE active low, data size 4 bytes */
+#define CONFIG_SYS_CS1_CFG		0x05059350
+
+#define CONFIG_SYS_MRAM_BASE		0x50040000
+#define CONFIG_SYS_MRAM_SIZE		0x00020000
+#define CONFIG_SYS_CS2_START		CONFIG_SYS_MRAM_BASE
+#define CONFIG_SYS_CS2_SIZE		CONFIG_SYS_MRAM_SIZE
+
+/* ALE active low, data size 4 bytes */
+#define CONFIG_SYS_CS2_CFG		0x05059110
+
+/* alt. CS timing for CS0, CS1, CS2 */
+#define CONFIG_SYS_CS_ALETIMING		0x00000007
+
+/*
+ * NAND FLASH
+ */
+#define CONFIG_CMD_NAND			/* enable NAND support */
+#define CONFIG_NAND_MPC5121_NFC
+#define CONFIG_SYS_NAND_BASE            0x40000000
+#define CONFIG_SYS_MAX_NAND_DEVICE      1
+#define CONFIG_SYS_NAND_SELECT_DEVICE	/* driver supports mutipl. chips */
+
+/*
+ * Configuration parameters for MPC5121 NAND driver
+ */
+#define CONFIG_FSL_NFC_WIDTH 1
+#define CONFIG_FSL_NFC_WRITE_SIZE 2048
+#define CONFIG_FSL_NFC_SPARE_SIZE 64
+#define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
+
+/*
+ * Dynamic MTD partition support
+ */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
+#define MTDIDS_DEFAULT		"nor0=f0000000.flash,nor1=f8000000.flash," \
+						"nand0=MPC5121 NAND"
+
+/*
+ * Flash layout
+ */
+#define MTDPARTS_DEFAULT	"mtdparts=f0000000.flash:512k(u-boot),"	\
+						"256k(environment1),"	\
+						"256k(environment2),"	\
+						"256k(splash-factory)," \
+						"2m(FIT: recovery),"	\
+						"4608k(fs-recovery),"   \
+						"256k(splash-customer),"\
+						"5m(FIT: kernel+dtb),"	\
+						"64m(rootfs squash)ro,"	\
+						"51m(userfs ubi);"	\
+					"f8000000.flash:-(unused);"	\
+					"MPC5121 NAND:1024m(extended-userfs)"
+
+/*
+ * Override partitions in device tree using info
+ * in "mtdparts" environment variable
+ */
+#ifdef CONFIG_CMD_MTDPARTS
+#define CONFIG_FDT_FIXUP_PARTITIONS
+#endif
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE	/* Start of monitor */
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* 512 kB for monitor */
+#ifdef	CONFIG_FSL_DIU_FB
+#define CONFIG_SYS_MALLOC_LEN		(6 * 1024 * 1024) /* for malloc */
+#else
+#define CONFIG_SYS_MALLOC_LEN		(512 * 1024)
+#endif
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX     1
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	6	/* console is on PSC6 */
+#if CONFIG_PSC_CONSOLE != 6
+#error CONFIG_PSC_CONSOLE must be 6
+#endif
+
+#define CONSOLE_FIFO_TX_SIZE	FIFOC_PSC6_TX_SIZE
+#define CONSOLE_FIFO_TX_ADDR	FIFOC_PSC6_TX_ADDR
+#define CONSOLE_FIFO_RX_SIZE	FIFOC_PSC6_RX_SIZE
+#define CONSOLE_FIFO_RX_ADDR	FIFOC_PSC6_RX_ADDR
+
+/*
+ * Clocks in use
+ */
+#define SCCR1_CLOCKS_EN	(CLOCK_SCCR1_CFG_EN |				\
+			 CLOCK_SCCR1_LPC_EN |				\
+			 CLOCK_SCCR1_NFC_EN |				\
+			 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |	\
+			 CLOCK_SCCR1_PSCFIFO_EN |			\
+			 CLOCK_SCCR1_DDR_EN |				\
+			 CLOCK_SCCR1_FEC_EN |				\
+			 CLOCK_SCCR1_TPR_EN)
+
+#define SCCR2_CLOCKS_EN	(CLOCK_SCCR2_MEM_EN |		\
+			 CLOCK_SCCR2_SPDIF_EN |		\
+			 CLOCK_SCCR2_DIU_EN |		\
+			 CLOCK_SCCR2_I2C_EN)
+
+/*
+ * Used PSC UART devices
+ */
+#define CONFIG_SYS_PSC1
+#define CONFIG_SYS_PSC4
+#define CONFIG_SYS_PSC6
+
+/*
+ * Co-processor communication parameters
+ */
+#define CONFIG_SYS_PDM360NG_COPROC_READ_DELAY	5000
+#define CONFIG_SYS_PDM360NG_COPROC_BAUDRATE	38400
+
+/*
+ * I2C
+ */
+#define CONFIG_HARD_I2C			/* I2C with hardware support */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+
+/*
+ * IIM - IC Identification Module
+ */
+#undef CONFIG_FSL_IIM
+
+/*
+ * EEPROM configuration
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2	/* 16-bit EEPROM addr */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* ST AT24C01 */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* 10ms of delay */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4	/* 16-Byte Write Mode */
+
+/*
+ * MAC addr in EEPROM
+ */
+#define CONFIG_SYS_I2C_EEPROM_BUS_NUM		0
+#define CONFIG_SYS_I2C_EEPROM_MAC_OFFSET	0x10
+/*
+ * Enabled only to delete "ethaddr" before testing
+ * "ethaddr" setting from EEPROM
+ */
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC512x_FEC	1
+#define CONFIG_PHY_ADDR		0x1F
+#define CONFIG_MII		1	/* MII PHY management	*/
+#define CONFIG_FEC_AN_TIMEOUT	1
+#define CONFIG_HAS_ETH0
+
+/*
+ * Configure on-board RTC
+ */
+#define CONFIG_RTC_M41T62			/* use M41T00 rtc via i2c */
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68	/* at address 0x68	*/
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+/* This has to be a multiple of the Flash sector size */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + \
+				 CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x40000		/* one sector (256K) for env */
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+
+#undef CONFIG_CMD_FUSE
+
+#ifdef CONFIG_VIDEO
+#define CONFIG_CMD_BMP
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+#ifdef CONFIG_CMD_KGDB
+	#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
+#else
+	#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
+#endif
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+/* Max number of command args */
+#define CONFIG_SYS_MAXARGS	16
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+/* Decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)
+
+/* Cache Configuration */
+#define CONFIG_SYS_DCACHE_SIZE		32768
+#define CONFIG_SYS_CACHELINE_SIZE	32
+#ifdef CONFIG_CMD_KGDB
+/* log base 2 of the above value */
+#define CONFIG_SYS_CACHELINE_SHIFT	5
+#endif
+
+#define CONFIG_SYS_HID0_INIT	0x000000000
+#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | HID0_ICE)
+#define CONFIG_SYS_HID2	HID2_HBE
+
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
+#endif
+
+/* POST support */
+#define CONFIG_POST             (CONFIG_SYS_POST_COPROC)
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_TIMESTAMP
+
+#define CONFIG_HOSTNAME		pdm360ng
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		400000
+
+#define CONFIG_BOOTDELAY	5	/* -1 disables auto-boot */
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo PDM360NG SAMPLE;" \
+	"echo"
+
+#define CONFIG_BOOTCOMMAND	"run env_cont"
+
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES	1
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE
+
+#define OF_CPU			"PowerPC,5121@0"
+#define OF_SOC_COMPAT		"fsl,mpc5121-immr"
+#define OF_TBCLK		(bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH		"/soc@80000000/serial@11600"
+
+/*
+ * Include common options for all mpc5121 boards
+ */
+#include "mpc5121-common.h"
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/pengwyn.h b/qemu/roms/u-boot/include/configs/pengwyn.h
new file mode 100644
index 000000000..fc25966e0
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/pengwyn.h
@@ -0,0 +1,207 @@
+/*
+ * pengwyn.h
+ *
+ * Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com>
+ *
+ * based on am335x_evm.h, Copyright (C) 2011 Texas Instruments Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_PENGWYN_H
+#define __CONFIG_PENGWYN_H
+
+#define CONFIG_NAND
+#define CONFIG_SERIAL1
+#define CONFIG_CONS_INDEX		1
+
+#include <configs/ti_am335x_common.h>
+
+/* Clock Defines */
+#define V_OSCK				24000000
+#define V_SCLK				V_OSCK
+
+/* set env size */
+#define CONFIG_ENV_SIZE			0x4000
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x80200000\0" \
+	"fdtaddr=0x80F80000\0" \
+	"bootpart=0:2\0" \
+	"bootdir=/boot\0" \
+	"bootfile=zImage\0" \
+	"fdtfile=am335x-pengwyn.dtb\0" \
+	"console=ttyO0,115200n8\0" \
+	"optargs=\0" \
+	"mmcdev=0\0" \
+	"mmcroot=/dev/mmcblk0p2 ro\0" \
+	"mmcrootfstype=ext4 rootwait\0" \
+	"rootpath=/export/rootfs\0" \
+	"nfsopts=nolock\0" \
+	"static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \
+		"::off\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0" \
+	"netargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=/dev/nfs " \
+		"nfsroot=${serverip}:${rootpath},${nfsopts} rw " \
+		"ip=dhcp\0" \
+	"bootenv=uEnv.txt\0" \
+	"loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
+	"importbootenv=echo Importing environment from mmc ...; " \
+		"env import -t $loadaddr $filesize\0" \
+	"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
+	"loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
+	"mmcloados=run mmcargs; " \
+		"bootz ${loadaddr} - ${fdtaddr};\0" \
+	"mmcboot=mmc dev ${mmcdev}; " \
+		"if mmc rescan; then " \
+			"echo SD/MMC found on device ${mmcdev};" \
+			"if run loadbootenv; then " \
+				"echo Loaded environment from ${bootenv};" \
+				"run importbootenv;" \
+			"fi;" \
+			"if test -n $uenvcmd; then " \
+				"echo Running uenvcmd ...;" \
+				"run uenvcmd;" \
+			"fi;" \
+			"if run loadimage; then " \
+				"run loadfdt;" \
+				"run mmcloados;" \
+			"fi;" \
+		"fi;\0" \
+	"netboot=echo Booting from network ...; " \
+		"setenv autoload no; " \
+		"dhcp; " \
+		"tftp ${loadaddr} ${bootfile}; " \
+		"tftp ${fdtaddr} ${fdtfile}; " \
+		"run netargs; " \
+		"bootz ${loadaddr} - ${fdtaddr}\0" \
+	"mtdids=" MTDIDS_DEFAULT "\0" \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${nandroot} " \
+		"rootfstype=${nandrootfstype}\0" \
+	"nandroot=ubi0:rootfs rw ubi.mtd=7,2048\0" \
+	"nandrootfstype=ubifs rootwait=1\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nand read ${fdtaddr} u-boot-spl-os; " \
+		"nand read ${loadaddr} kernel; " \
+		"bootz ${loadaddr} - ${fdtaddr}\0"
+#endif
+
+#define CONFIG_BOOTCOMMAND \
+	"run mmcboot;" \
+	"run nandboot;"
+
+/* NS16550 Configuration: primary UART via FDTI */
+#define CONFIG_SYS_NS16550_COM1		0x44e09000
+#define CONFIG_BAUDRATE			115200
+
+/* I2C Configuration */
+#define	CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_CMD_EEPROM
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+
+/* SPL */
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_YMODEM_SUPPORT
+
+/* General network SPL */
+#define CONFIG_SPL_NET_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_NET_VCI_STRING	"AM335x U-Boot SPL"
+
+/* NAND support */
+#define CONFIG_CMD_NAND
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_NAND_OMAP_ELM
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
+					 CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
+					 10, 11, 12, 13, 14, 15, 16, 17, \
+					 18, 19, 20, 21, 22, 23, 24, 25, \
+					 26, 27, 28, 29, 30, 31, 32, 33, \
+					 34, 35, 36, 37, 38, 39, 40, 41, \
+					 42, 43, 44, 45, 46, 47, 48, 49, \
+					 50, 51, 52, 53, 54, 55, 56, 57, }
+
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	14
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+
+#define GPMC_NAND_ECC_LP_x8_LAYOUT	1
+#define MTDIDS_DEFAULT			"nand0=omap2-nand.0"
+#define MTDPARTS_DEFAULT		"mtdparts=omap2-nand.0:128k(SPL)," \
+					"128k(SPL.backup1)," \
+					"128k(SPL.backup2)," \
+					"128k(SPL.backup3),1792k(u-boot)," \
+					"128k(u-boot-spl-os)," \
+					"128k(u-boot-env),5m(kernel),-(rootfs)"
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		0x260000 /* environment starts here */
+#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
+
+/*
+ * USB configuration.  We enable MUSB support, both for host and for
+ * gadget.  We set USB0 as peripheral and USB1 as host, based on the
+ * board schematic and physical port wired to each.  Then for host we
+ * add mass storage support.
+ */
+#define CONFIG_USB_MUSB_DSPS
+#define CONFIG_ARCH_MISC_INIT
+#define CONFIG_MUSB_GADGET
+#define CONFIG_MUSB_PIO_ONLY
+#define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_VBUS_DRAW	2
+#define CONFIG_MUSB_HOST
+#define CONFIG_AM335X_USB0
+#define CONFIG_AM335X_USB0_MODE	MUSB_PERIPHERAL
+#define CONFIG_AM335X_USB1
+#define CONFIG_AM335X_USB1_MODE MUSB_HOST
+
+#if defined(CONFIG_MUSB_HOST)
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#endif
+
+#if defined(CONFIG_SPL_BUILD)
+/* disable host part of MUSB in SPL */
+#undef CONFIG_MUSB_HOST
+/* Disable CPSW SPL support so we fit within the 101KiB limit. */
+#undef CONFIG_SPL_ETH_SUPPORT
+#endif
+
+/* Network */
+#define CONFIG_CMD_MII
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_RESET	1
+#define CONFIG_PHY_NATSEMI
+
+/* CPSW support */
+#define CONFIG_SPL_ETH_SUPPORT
+
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/am33xx/u-boot-spl.lds"
+
+#endif	/* ! __CONFIG_PENGWYN_H */
diff --git a/qemu/roms/u-boot/include/configs/pf5200.h b/qemu/roms/u-boot/include/configs/pf5200.h
new file mode 100644
index 000000000..be76478c3
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/pf5200.h
@@ -0,0 +1,372 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*************************************************************************
+ * (c) 2005 esd gmbh Hannover
+ *
+ *
+ * from IceCube.h file
+ * by Reinhard Arlt reinhard.arlt@esd-electronics.com
+ *
+ *************************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5200		1	/* This is an MPC5200 CPU */
+#define CONFIG_ICECUBE		1	/* ... on IceCube board */
+#define CONFIG_PF5200		1	/* ... on PF5200  board */
+#define CONFIG_MPC5200_DDR	1	/* ... use DDR RAM	*/
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xFFF00000
+#endif
+
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000	/* ... running at 33.000000MHz */
+
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
+#if 0				/* test-only */
+#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
+#else
+#define CONFIG_BAUDRATE		9600	/* ... at 115200 bps */
+#endif
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*
+ * PCI Mapping:
+ * 0x40000000 - 0x4fffffff - PCI Memory
+ * 0x50000000 - 0x50ffffff - PCI IO Space
+ */
+#define CONFIG_PCI		1
+#define CONFIG_PCI_PNP		1
+#define CONFIG_PCI_SCAN_SHOW	1
+#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1
+
+#define CONFIG_PCI_MEM_BUS	0x40000000
+#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE	0x10000000
+
+#define CONFIG_PCI_IO_BUS	0x50000000
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0x01000000
+
+#define CONFIG_MII		1
+#if 0				/* test-only !!! */
+#define CONFIG_EEPRO100		1
+#define CONFIG_SYS_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100	*/
+#define CONFIG_NS8382X		1
+#endif
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+/* USB */
+#if 0
+#define CONFIG_USB_OHCI
+#define CONFIG_USB_STORAGE
+#endif
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+
+#define CONFIG_CMD_PCI
+
+
+#if (CONFIG_SYS_TEXT_BASE == 0xFF000000)	/* Boot low with 16 MB Flash */
+#   define CONFIG_SYS_LOWBOOT		1
+#   define CONFIG_SYS_LOWBOOT16	1
+#endif
+#if (CONFIG_SYS_TEXT_BASE == 0xFF800000)	/* Boot low with  8 MB Flash */
+#   define CONFIG_SYS_LOWBOOT		1
+#   define CONFIG_SYS_LOWBOOT08	1
+#endif
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	3	/* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Welcome to ParaFinder pf5200;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS \
+	"netdev=eth0\0" \
+	"flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
+	"flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
+	"net_vxworks=phypower 1;sleep 2;tftp ${loadaddr} ${image};run vxworks_args;bootvx\0" \
+	"vxworks_args=setenv bootargs fec(0,0)${host}:${image} h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script}\0" \
+	"ata_vxworks_args=setenv bootargs /ata0/vxWorks h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script} o=fec0 \0" \
+	"loadaddr=01000000\0" \
+	"serverip=192.168.2.99\0" \
+	"gatewayip=10.0.0.79\0" \
+	"user=mu\0" \
+	"target=pf5200.esd\0" \
+	"script=pf5200.bat\0" \
+	"image=/tftpboot/vxWorks_pf5200\0" \
+	"ipaddr=10.0.13.196\0" \
+	"netmask=255.255.0.0\0" \
+	""
+
+#define CONFIG_BOOTCOMMAND	"run flash_vxworks0"
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #1 or #2 */
+
+#define CONFIG_SYS_I2C_SPEED		86000	/* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	20
+#define CONFIG_SYS_I2C_MULTI_EEPROMS		1
+/*
+ * Flash configuration
+ */
+#define CONFIG_SYS_FLASH_BASE		0xFE000000
+#define CONFIG_SYS_FLASH_SIZE		0x02000000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00000000)
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	512
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/
+
+/*
+ * Environment settings
+ */
+#if 1				/* test-only */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SIZE		0x10000
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#define CONFIG_ENV_OVERWRITE	1
+#else
+#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
+#define CONFIG_ENV_OFFSET		0x0000	/* environment starts at the beginning of the EEPROM */
+#define CONFIG_ENV_SIZE		0x0400	/* 8192 bytes may be used for env vars */
+				   /* total size of a CAT24WC32 is 8192 bytes */
+#define CONFIG_ENV_OVERWRITE	1
+#endif
+
+/*
+ * Memory map
+ */
+#define CONFIG_SYS_MBAR		0xF0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
+
+/* Use SRAM until RAM will be available */
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC	1
+#define CONFIG_MPC5xxx_FEC_MII100
+/*
+ * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
+ */
+/* #define CONFIG_MPC5xxx_FEC_MII10 */
+#define CONFIG_PHY_ADDR		0x00
+#define CONFIG_UDP_CHECKSUM	1
+
+/*
+ * GPIO configuration
+ */
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x01052444
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory	    */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
+
+#define CONFIG_SYS_VXWORKS_MAC_PTR	0x00000000	/* Pass Ethernet MAC to VxWorks */
+
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*
+ * Various low-level settings
+ */
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
+
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_CFG		0x0004DD00
+
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
+
+#define CONFIG_SYS_CS1_START		0xfd000000
+#define CONFIG_SYS_CS1_SIZE		0x00010000
+#define CONFIG_SYS_CS1_CFG		0x10101410
+
+#define CONFIG_SYS_CS_BURST		0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE	0x33333333
+
+#define CONFIG_SYS_RESET_ADDRESS	0xff000000
+
+/*-----------------------------------------------------------------------
+ * USB stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_USB_CLOCK	0x0001BBBB
+#define CONFIG_USB_CONFIG	0x00001000
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+
+#undef	CONFIG_IDE_8xx_PCCARD	/* Use IDE with PC Card Adapter */
+
+#undef	CONFIG_IDE_8xx_DIRECT	/* Direct IDE	 not supported	*/
+#undef	CONFIG_IDE_LED		/* LED	 for ide not supported	*/
+
+#define	CONFIG_IDE_RESET	/* reset for ide supported	*/
+#define CONFIG_IDE_PREINIT
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
+
+/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
+
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)
+
+/* Interval between registers						     */
+#define CONFIG_SYS_ATA_STRIDE		4
+
+/*-----------------------------------------------------------------------
+ * CPLD stuff
+ */
+#define CONFIG_SYS_FPGA_XC95XL		1	/* using Xilinx XC95XL CPLD	 */
+#define CONFIG_SYS_FPGA_MAX_SIZE	32*1024	/* 32kByte is enough for CPLD	 */
+
+/* CPLD program pin configuration */
+#define CONFIG_SYS_FPGA_PRG		0x20000000	/* JTAG TMS pin (ppc output)	       */
+#define CONFIG_SYS_FPGA_CLK		0x10000000	/* JTAG TCK pin (ppc output)	       */
+#define CONFIG_SYS_FPGA_DATA		0x20000000	/* JTAG TDO->TDI data pin (ppc output) */
+#define CONFIG_SYS_FPGA_DONE		0x10000000	/* JTAG TDI->TDO pin (ppc input)       */
+
+#define JTAG_GPIO_ADDR_TMS	(CONFIG_SYS_MBAR + 0xB10)	/* JTAG TMS pin (GPS data out value reg.)      */
+#define JTAG_GPIO_ADDR_TCK	(CONFIG_SYS_MBAR + 0xC0C)	/* JTAG TCK pin (GPW data out value reg.)      */
+#define JTAG_GPIO_ADDR_TDI	(CONFIG_SYS_MBAR + 0xC0C)	/* JTAG TDO->TDI pin (GPW data out value reg.) */
+#define JTAG_GPIO_ADDR_TDO	(CONFIG_SYS_MBAR + 0xB14)	/* JTAG TDI->TDO pin (GPS data in value reg.)  */
+
+#define JTAG_GPIO_ADDR_CFG	(CONFIG_SYS_MBAR + 0xB00)
+#define JTAG_GPIO_CFG_SET	0x00000000
+#define JTAG_GPIO_CFG_RESET	0x00F00000
+
+#define JTAG_GPIO_ADDR_EN_TMS	(CONFIG_SYS_MBAR + 0xB04)
+#define JTAG_GPIO_TMS_EN_SET	0x20000000	/* Enable for GPIO */
+#define JTAG_GPIO_TMS_EN_RESET	0x00000000
+#define JTAG_GPIO_ADDR_DDR_TMS	(CONFIG_SYS_MBAR + 0xB0C)
+#define JTAG_GPIO_TMS_DDR_SET	0x20000000	/* Set as output   */
+#define JTAG_GPIO_TMS_DDR_RESET 0x00000000
+
+#define JTAG_GPIO_ADDR_EN_TCK	(CONFIG_SYS_MBAR + 0xC00)
+#define JTAG_GPIO_TCK_EN_SET	0x20000000	/* Enable for GPIO */
+#define JTAG_GPIO_TCK_EN_RESET	0x00000000
+#define JTAG_GPIO_ADDR_DDR_TCK	(CONFIG_SYS_MBAR + 0xC08)
+#define JTAG_GPIO_TCK_DDR_SET	0x20000000	/* Set as output   */
+#define JTAG_GPIO_TCK_DDR_RESET 0x00000000
+
+#define JTAG_GPIO_ADDR_EN_TDI	(CONFIG_SYS_MBAR + 0xC00)
+#define JTAG_GPIO_TDI_EN_SET	0x10000000	/* Enable as GPIO  */
+#define JTAG_GPIO_TDI_EN_RESET	0x00000000
+#define JTAG_GPIO_ADDR_DDR_TDI	(CONFIG_SYS_MBAR + 0xC08)
+#define JTAG_GPIO_TDI_DDR_SET	0x10000000	/* Set as output   */
+#define JTAG_GPIO_TDI_DDR_RESET 0x00000000
+
+#define JTAG_GPIO_ADDR_EN_TDO	(CONFIG_SYS_MBAR + 0xB04)
+#define JTAG_GPIO_TDO_EN_SET	0x10000000	/* Enable as GPIO  */
+#define JTAG_GPIO_TDO_EN_RESET	0x00000000
+#define JTAG_GPIO_ADDR_DDR_TDO	(CONFIG_SYS_MBAR + 0xB0C)
+#define JTAG_GPIO_TDO_DDR_SET	0x00000000
+#define JTAG_GPIO_TDO_DDR_RESET 0x10000000	/* Set as input	   */
+
+#endif				/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/plutux.h b/qemu/roms/u-boot/include/configs/plutux.h
new file mode 100644
index 000000000..a473f232f
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/plutux.h
@@ -0,0 +1,65 @@
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *  (C) Copyright 2011-2012
+ *  Avionic Design GmbH <www.avionic-design.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "tegra20-common.h"
+
+/* Enable fdt support for Plutux. Flash the image in u-boot-dtb.bin */
+#define CONFIG_DEFAULT_DEVICE_TREE	tegra20-plutux
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
+/* High-level configuration options */
+#define V_PROMPT			"Tegra20 (Plutux) # "
+#define CONFIG_TEGRA_BOARD_STRING	"Avionic Design Plutux"
+
+/* Board-specific serial config */
+#define CONFIG_TEGRA_ENABLE_UARTD	/* UARTD: debug UART */
+#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_TEGRA_MMC
+#define CONFIG_CMD_MMC
+
+/* NAND support */
+#define CONFIG_CMD_NAND
+#define CONFIG_TEGRA_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+
+/* Environment in NAND, aligned to start of last sector */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		(SZ_512M - SZ_128K) /* 128K sectors */
+
+/* USB host support */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_TEGRA
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB
+
+/* USB networking support */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_SMSC95XX
+
+/* General networking support */
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+
+/* support the new (FDT-based) image format */
+#define CONFIG_FIT
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/pm9261.h b/qemu/roms/u-boot/include/configs/pm9261.h
new file mode 100644
index 000000000..4a7192721
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/pm9261.h
@@ -0,0 +1,363 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ * Ilko Iliev <www.ronetix.at>
+ *
+ * Configuation settings for the RONETIX PM9261 board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * SoC must be defined first, before hardware.h is included.
+ * In this case SoC is defined in boards.cfg.
+ */
+
+#include <asm/hardware.h>
+/* ARM asynchronous clock */
+
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define MASTER_PLL_DIV		15
+#define MASTER_PLL_MUL		162
+#define MAIN_PLL_DIV		2
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000
+
+#define CONFIG_SYS_AT91_CPU_NAME	"AT91SAM9261"
+#define CONFIG_PM9261		1	/* on a Ronetix PM9261 Board	*/
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_SYS_TEXT_BASE	0
+
+#define MACH_TYPE_PM9261	1187
+#define CONFIG_MACH_TYPE	MACH_TYPE_PM9261
+
+/* clocks */
+/* CKGR_MOR - enable main osc. */
+#define CONFIG_SYS_MOR_VAL						\
+		(AT91_PMC_MOR_MOSCEN |					\
+		 (255 << 8))		/* Main Oscillator Start-up Time */
+#define CONFIG_SYS_PLLAR_VAL						\
+		(AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \
+		 AT91_PMC_PLLXR_OUT(3) |						\
+		 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
+
+/* PCK/2 = MCK Master Clock from PLLA */
+#define	CONFIG_SYS_MCKR1_VAL		\
+		(AT91_PMC_MCKR_CSS_SLOW |	\
+		 AT91_PMC_MCKR_PRES_1 |	\
+		 AT91_PMC_MCKR_MDIV_2)
+
+/* PCK/2 = MCK Master Clock from PLLA */
+#define	CONFIG_SYS_MCKR2_VAL		\
+		(AT91_PMC_MCKR_CSS_PLLA |	\
+		 AT91_PMC_MCKR_PRES_1 |	\
+		 AT91_PMC_MCKR_MDIV_2)
+
+/* define PDC[31:16] as DATA[31:16] */
+#define CONFIG_SYS_PIOC_PDR_VAL1	0xFFFF0000
+/* no pull-up for D[31:16] */
+#define CONFIG_SYS_PIOC_PPUDR_VAL	0xFFFF0000
+
+/* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
+#define CONFIG_SYS_MATRIX_EBICSA_VAL		\
+	(AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A)
+
+/* SDRAM */
+/* SDRAMC_MR Mode register */
+#define CONFIG_SYS_SDRC_MR_VAL1		AT91_SDRAMC_MODE_NORMAL
+/* SDRAMC_TR - Refresh Timer register */
+#define CONFIG_SYS_SDRC_TR_VAL1		0x13C
+/* SDRAMC_CR - Configuration register*/
+#define CONFIG_SYS_SDRC_CR_VAL							\
+		(AT91_SDRAMC_NC_9 |						\
+		 AT91_SDRAMC_NR_13 |						\
+		 AT91_SDRAMC_NB_4 |						\
+		 AT91_SDRAMC_CAS_3 |						\
+		 AT91_SDRAMC_DBW_32 |						\
+		 (1 <<  8) |		/* Write Recovery Delay */		\
+		 (7 << 12) |		/* Row Cycle Delay */			\
+		 (3 << 16) |		/* Row Precharge Delay */		\
+		 (2 << 20) |		/* Row to Column Delay */		\
+		 (5 << 24) |		/* Active to Precharge Delay */		\
+		 (1 << 28))		/* Exit Self Refresh to Active Delay */
+
+/* Memory Device Register -> SDRAM */
+#define CONFIG_SYS_SDRC_MDR_VAL		AT91_SDRAMC_MD_SDRAM
+#define CONFIG_SYS_SDRC_MR_VAL2		AT91_SDRAMC_MODE_PRECHARGE
+#define CONFIG_SYS_SDRAM_VAL1		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL3		AT91_SDRAMC_MODE_REFRESH
+#define CONFIG_SYS_SDRAM_VAL2		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL3		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL4		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL5		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL6		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL7		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL8		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL9		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL4		AT91_SDRAMC_MODE_LMR
+#define CONFIG_SYS_SDRAM_VAL10		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL5		AT91_SDRAMC_MODE_NORMAL
+#define CONFIG_SYS_SDRAM_VAL11		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_TR_VAL2		1200		/* SDRAM_TR */
+#define CONFIG_SYS_SDRAM_VAL12		0		/* SDRAM_BASE */
+
+/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
+#define CONFIG_SYS_SMC0_SETUP0_VAL					\
+		(AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) |	\
+		 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
+#define CONFIG_SYS_SMC0_PULSE0_VAL					\
+		(AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) |	\
+		 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
+#define CONFIG_SYS_SMC0_CYCLE0_VAL	\
+		(AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
+#define CONFIG_SYS_SMC0_MODE0_VAL				\
+		(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |	\
+		 AT91_SMC_MODE_DBW_16 |				\
+		 AT91_SMC_MODE_TDF |				\
+		 AT91_SMC_MODE_TDF_CYCLE(6))
+
+/* user reset enable */
+#define CONFIG_SYS_RSTC_RMR_VAL			\
+		(AT91_RSTC_KEY |		\
+		AT91_RSTC_CR_PROCRST |		\
+		AT91_RSTC_MR_ERSTL(1) |	\
+		AT91_RSTC_MR_ERSTL(2))
+
+/* Disable Watchdog */
+#define CONFIG_SYS_WDTC_WDMR_VAL				\
+		(AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT |	\
+		 AT91_WDT_MR_WDV(0xfff) |					\
+		 AT91_WDT_MR_WDDIS |				\
+		 AT91_WDT_MR_WDD(0xfff))
+
+#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG	1
+
+#undef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_AT91_GPIO	1
+#define CONFIG_ATMEL_USART	1
+#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
+#define	CONFIG_USART_ID			ATMEL_ID_SYS
+
+/* LCD */
+#define CONFIG_LCD			1
+#define LCD_BPP				LCD_COLOR8
+#define CONFIG_LCD_LOGO			1
+#undef LCD_TEST_PATTERN
+#define CONFIG_LCD_INFO			1
+#define CONFIG_LCD_INFO_BELOW_LOGO	1
+#define CONFIG_SYS_WHITE_ON_BLACK	1
+#define CONFIG_ATMEL_LCD		1
+#define CONFIG_ATMEL_LCD_BGR555		1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
+
+/* LED */
+#define CONFIG_AT91_LED
+#define CONFIG_RED_LED		GPIO_PIN_PC(12)
+#define CONFIG_GREEN_LED	GPIO_PIN_PC(13)
+#define CONFIG_YELLOW_LED	GPIO_PIN_PC(15)
+
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE	1
+#define CONFIG_BOOTP_BOOTPATH		1
+#define CONFIG_BOOTP_GATEWAY		1
+#define CONFIG_BOOTP_HOSTNAME		1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_PING		1
+#define CONFIG_CMD_DHCP		1
+#define CONFIG_CMD_NAND		1
+#define CONFIG_CMD_USB		1
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS			1
+#define PHYS_SDRAM				0x20000000
+#define PHYS_SDRAM_SIZE				0x04000000	/* 64 megs */
+
+/* DataFlash */
+#define CONFIG_ATMEL_DATAFLASH_SPI
+#define CONFIG_HAS_DATAFLASH
+#define CONFIG_SYS_SPI_WRITE_TOUT		(5 * CONFIG_SYS_HZ)
+#define CONFIG_SYS_MAX_DATAFLASH_BANKS		1
+#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
+#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3	0xD0000000	/* CS3 */
+#define AT91_SPI_CLK				15000000
+#define DATAFLASH_TCSS				(0x1a << 16)
+#define DATAFLASH_TCHS				(0x1 << 24)
+
+/* NAND flash */
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE		1
+#define CONFIG_SYS_NAND_BASE			0x40000000
+#define CONFIG_SYS_NAND_DBW_8			1
+/* our ALE is AD22 */
+#define CONFIG_SYS_NAND_MASK_ALE		(1 << 22)
+/* our CLE is AD21 */
+#define CONFIG_SYS_NAND_MASK_CLE		(1 << 21)
+#define CONFIG_SYS_NAND_ENABLE_PIN		GPIO_PIN_PC(14)
+#define CONFIG_SYS_NAND_READY_PIN		GPIO_PIN_PA(16)
+
+/* NOR flash */
+#define CONFIG_SYS_FLASH_CFI			1
+#define CONFIG_FLASH_CFI_DRIVER			1
+#define PHYS_FLASH_1				0x10000000
+#define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
+#define CONFIG_SYS_MAX_FLASH_SECT		256
+#define CONFIG_SYS_MAX_FLASH_BANKS		1
+
+/* Ethernet */
+#define CONFIG_DRIVER_DM9000			1
+#define CONFIG_DM9000_BASE			0x30000000
+#define DM9000_IO				CONFIG_DM9000_BASE
+#define DM9000_DATA				(CONFIG_DM9000_BASE + 4)
+#define CONFIG_DM9000_USE_16BIT			1
+#define CONFIG_NET_RETRY_COUNT			20
+#define CONFIG_RESET_PHY_R			1
+
+/* USB */
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
+#define CONFIG_USB_OHCI_NEW			1
+#define CONFIG_DOS_PARTITION			1
+#define CONFIG_SYS_USB_OHCI_CPU_INIT		1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00500000
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9261"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+#define CONFIG_USB_STORAGE			1
+
+#define CONFIG_SYS_LOAD_ADDR			0x22000000
+
+#define CONFIG_SYS_MEMTEST_START		PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END			0x23e00000
+
+#undef CONFIG_SYS_USE_DATAFLASH_CS0
+#undef CONFIG_SYS_USE_NANDFLASH
+#define CONFIG_SYS_USE_FLASH	1
+
+#ifdef CONFIG_SYS_USE_DATAFLASH_CS0
+
+/* bootstrap + u-boot + env + linux in dataflash on CS0 */
+#define CONFIG_ENV_IS_IN_DATAFLASH	1
+#define CONFIG_SYS_MONITOR_BASE		\
+		(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
+#define CONFIG_ENV_OFFSET	0x4200
+#define CONFIG_ENV_ADDR		\
+		(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SIZE		0x4200
+#define CONFIG_BOOTCOMMAND	"cp.b 0xC0042000 0x22000000 0x210000; bootm"
+#define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
+				"root=/dev/mtdblock0 "			\
+				"mtdparts=atmel_nand:-(root) "		\
+				"rw rootfstype=jffs2"
+
+#elif defined(CONFIG_SYS_USE_NANDFLASH) /* CONFIG_SYS_USE_NANDFLASH */
+
+/* bootstrap + u-boot + env + linux in nandflash */
+#define CONFIG_ENV_IS_IN_NAND		1
+#define CONFIG_ENV_OFFSET		0x60000
+#define CONFIG_ENV_OFFSET_REDUND	0x80000
+#define CONFIG_ENV_SIZE			0x20000		/* 1 sector = 128 kB */
+#define CONFIG_BOOTCOMMAND	"nand read 0x22000000 0xA0000 0x200000; bootm"
+#define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
+				"root=/dev/mtdblock5 "			\
+				"mtdparts=atmel_nand:128k(bootstrap)ro,"	\
+				"256k(uboot)ro,128k(env1)ro,"		\
+				"128k(env2)ro,2M(linux),-(root) "	\
+				"rw rootfstype=jffs2"
+
+#elif defined (CONFIG_SYS_USE_FLASH)
+
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_OFFSET	0x40000
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#define	CONFIG_ENV_SIZE		0x10000
+#define CONFIG_ENV_OVERWRITE	1
+
+/* JFFS Partition offset set */
+#define CONFIG_SYS_JFFS2_FIRST_BANK	0
+#define CONFIG_SYS_JFFS2_NUM_BANKS	1
+
+/* 512k reserved for u-boot */
+#define CONFIG_SYS_JFFS2_FIRST_SECTOR	11
+
+#define CONFIG_BOOTCOMMAND	"run flashboot"
+
+#define MTDIDS_DEFAULT		"nor0=physmap-flash.0,nand0=nand"
+#define MTDPARTS_DEFAULT		\
+	"mtdparts=physmap-flash.0:"	\
+		"256k(u-boot)ro,"	\
+		"64k(u-boot-env)ro,"	\
+		"1408k(kernel),"	\
+		"-(rootfs);"		\
+	"nand:-(nand)"
+
+#define CONFIG_CON_ROT "fbcon=rotate:3 "
+#define CONFIG_BOOTARGS "root=/dev/mtdblock4 rootfstype=jffs2 " CONFIG_CON_ROT
+
+#define CONFIG_EXTRA_ENV_SETTINGS				\
+	"mtdids=" MTDIDS_DEFAULT "\0"				\
+	"mtdparts=" MTDPARTS_DEFAULT "\0"			\
+	"partition=nand0,0\0"					\
+	"ramargs=setenv bootargs $(bootargs) $(mtdparts)\0"	\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "		\
+		CONFIG_CON_ROT					\
+		"nfsroot=$(serverip):$(rootpath) $(mtdparts)\0"	\
+	"addip=setenv bootargs $(bootargs) "			\
+		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\
+		":$(hostname):eth0:off\0"			\
+	"ramboot=tftpboot 0x22000000 vmImage;"			\
+		"run ramargs;run addip;bootm 22000000\0"	\
+	"nfsboot=tftpboot 0x22000000 vmImage;"			\
+		"run nfsargs;run addip;bootm 22000000\0"	\
+	"flashboot=run ramargs;run addip;bootm 0x10050000\0"	\
+	""
+#else
+#error "Undefined memory device"
+#endif
+
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_SYS_PROMPT		"pm9261> "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_PBSIZE		\
+		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP		1
+#define CONFIG_CMDLINE_EDITING	1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		\
+		ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
+
+#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE + 0x1000 - \
+				GENERATED_GBL_DATA_SIZE)
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/pm9263.h b/qemu/roms/u-boot/include/configs/pm9263.h
new file mode 100644
index 000000000..d9c04d14b
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/pm9263.h
@@ -0,0 +1,397 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ * Ilko Iliev <www.ronetix.at>
+ *
+ * Configuation settings for the RONETIX PM9263 board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * SoC must be defined first, before hardware.h is included.
+ * In this case SoC is defined in boards.cfg.
+ */
+#include <asm/hardware.h>
+
+/* ARM asynchronous clock */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define MASTER_PLL_DIV		6
+#define MASTER_PLL_MUL		65
+#define MAIN_PLL_DIV		2	/* 2 or 4 */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
+
+#define CONFIG_SYS_AT91_CPU_NAME	"AT91SAM9263"
+#define CONFIG_PM9263		1	/* on a Ronetix PM9263 Board	*/
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_SYS_TEXT_BASE	0
+
+#define MACH_TYPE_PM9263	1475
+#define CONFIG_MACH_TYPE	MACH_TYPE_PM9263
+
+/* clocks */
+#define CONFIG_SYS_MOR_VAL						\
+		(AT91_PMC_MOR_MOSCEN |					\
+		 (255 << 8))		/* Main Oscillator Start-up Time */
+#define CONFIG_SYS_PLLAR_VAL						\
+		(AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \
+		 AT91_PMC_PLLXR_OUT(3) |				\
+		 AT91_PMC_PLLXR_PLLCOUNT(0x3f) |	/* PLL Counter */\
+		 (2 << 28) |		/* PLL Clock Frequency Range */	\
+		 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
+
+#if (MAIN_PLL_DIV == 2)
+/* PCK/2 = MCK Master Clock from PLLA */
+#define	CONFIG_SYS_MCKR1_VAL		\
+		(AT91_PMC_MCKR_CSS_SLOW |	\
+		 AT91_PMC_MCKR_PRES_1 |	\
+		 AT91_PMC_MCKR_MDIV_2)
+/* PCK/2 = MCK Master Clock from PLLA */
+#define	CONFIG_SYS_MCKR2_VAL		\
+		(AT91_PMC_MCKR_CSS_PLLA |	\
+		 AT91_PMC_MCKR_PRES_1 |	\
+		 AT91_PMC_MCKR_MDIV_2)
+#else
+/* PCK/4 = MCK Master Clock from PLLA */
+#define	CONFIG_SYS_MCKR1_VAL			\
+		(AT91_PMC_MCKR_CSS_SLOW |		\
+		 AT91_PMC_MCKR_PRES_1 |		\
+		 AT91_PMC_MCKR_MDIV_4)
+/* PCK/4 = MCK Master Clock from PLLA */
+#define	CONFIG_SYS_MCKR2_VAL			\
+		(AT91_PMC_MCKR_CSS_PLLA |		\
+		 AT91_PMC_MCKR_PRES_1 |		\
+		 AT91_PMC_MCKR_MDIV_4)
+#endif
+/* define PDC[31:16] as DATA[31:16] */
+#define CONFIG_SYS_PIOD_PDR_VAL1	0xFFFF0000
+/* no pull-up for D[31:16] */
+#define CONFIG_SYS_PIOD_PPUDR_VAL	0xFFFF0000
+/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
+#define CONFIG_SYS_MATRIX_EBI0CSA_VAL					\
+	(AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V |	\
+	 AT91_MATRIX_CSA_EBI_CS1A)
+
+/* SDRAM */
+/* SDRAMC_MR Mode register */
+#define CONFIG_SYS_SDRC_MR_VAL1		0
+/* SDRAMC_TR - Refresh Timer register */
+#define CONFIG_SYS_SDRC_TR_VAL1		0x3AA
+/* SDRAMC_CR - Configuration register*/
+#define CONFIG_SYS_SDRC_CR_VAL							\
+		(AT91_SDRAMC_NC_9 |						\
+		 AT91_SDRAMC_NR_13 |						\
+		 AT91_SDRAMC_NB_4 |						\
+		 AT91_SDRAMC_CAS_2 |						\
+		 AT91_SDRAMC_DBW_32 |						\
+		 (2 <<  8) |	/* tWR -  Write Recovery Delay */		\
+		 (7 << 12) |	/* tRC -  Row Cycle Delay */			\
+		 (2 << 16) |	/* tRP -  Row Precharge Delay */		\
+		 (2 << 20) |	/* tRCD - Row to Column Delay */		\
+		 (5 << 24) |	/* tRAS - Active to Precharge Delay */		\
+		 (8 << 28))	/* tXSR - Exit Self Refresh to Active Delay */
+
+/* Memory Device Register -> SDRAM */
+#define CONFIG_SYS_SDRC_MDR_VAL		AT91_SDRAMC_MD_SDRAM
+#define CONFIG_SYS_SDRC_MR_VAL2		AT91_SDRAMC_MODE_PRECHARGE
+#define CONFIG_SYS_SDRAM_VAL1		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL3		AT91_SDRAMC_MODE_REFRESH
+#define CONFIG_SYS_SDRAM_VAL2		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL3		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL4		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL5		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL6		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL7		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL8		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL9		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL4		AT91_SDRAMC_MODE_LMR
+#define CONFIG_SYS_SDRAM_VAL10		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL5		AT91_SDRAMC_MODE_NORMAL
+#define CONFIG_SYS_SDRAM_VAL11		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_TR_VAL2		1200		/* SDRAM_TR */
+#define CONFIG_SYS_SDRAM_VAL12		0		/* SDRAM_BASE */
+
+/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
+#define CONFIG_SYS_SMC0_SETUP0_VAL					\
+		(AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) |	\
+		 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
+#define CONFIG_SYS_SMC0_PULSE0_VAL					\
+		(AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) |	\
+		 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
+#define CONFIG_SYS_SMC0_CYCLE0_VAL	\
+		(AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
+#define CONFIG_SYS_SMC0_MODE0_VAL				\
+		(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |	\
+		 AT91_SMC_MODE_DBW_16 |				\
+		 AT91_SMC_MODE_TDF |				\
+		 AT91_SMC_MODE_TDF_CYCLE(6))
+
+/* user reset enable */
+#define CONFIG_SYS_RSTC_RMR_VAL			\
+		(AT91_RSTC_KEY |		\
+		AT91_RSTC_CR_PROCRST |		\
+		AT91_RSTC_MR_ERSTL(1) |	\
+		AT91_RSTC_MR_ERSTL(2))
+
+/* Disable Watchdog */
+#define CONFIG_SYS_WDTC_WDMR_VAL				\
+		(AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT |	\
+		 AT91_WDT_MR_WDV(0xfff) |					\
+		 AT91_WDT_MR_WDDIS |				\
+		 AT91_WDT_MR_WDD(0xfff))
+
+#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG	1
+
+#undef CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_USER_LOWLEVEL_INIT	1
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_AT91_GPIO	1
+#define CONFIG_ATMEL_USART	1
+#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
+#define	CONFIG_USART_ID			ATMEL_ID_SYS
+
+/* LCD */
+#define CONFIG_LCD			1
+#define LCD_BPP				LCD_COLOR8
+#define CONFIG_LCD_LOGO			1
+#undef LCD_TEST_PATTERN
+#define CONFIG_LCD_INFO			1
+#define CONFIG_LCD_INFO_BELOW_LOGO	1
+#define CONFIG_SYS_WHITE_ON_BLACK	1
+#define CONFIG_ATMEL_LCD		1
+#define CONFIG_ATMEL_LCD_BGR555		1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
+
+#define CONFIG_LCD_IN_PSRAM		1
+
+/* LED */
+#define CONFIG_AT91_LED
+#define CONFIG_RED_LED		GPIO_PIN_PB(7) /* this is the power led */
+#define CONFIG_GREEN_LED	GPIO_PIN_PB(8) /* this is the user1 led */
+
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE	1
+#define CONFIG_BOOTP_BOOTPATH		1
+#define CONFIG_BOOTP_GATEWAY		1
+#define CONFIG_BOOTP_HOSTNAME		1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_PING		1
+#define CONFIG_CMD_DHCP		1
+#define CONFIG_CMD_NAND		1
+#define CONFIG_CMD_USB		1
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM		0x20000000
+#define PHYS_SDRAM_SIZE		0x04000000	/* 64 megs */
+
+/* DataFlash */
+#define CONFIG_ATMEL_DATAFLASH_SPI
+#define CONFIG_HAS_DATAFLASH			1
+#define CONFIG_SYS_SPI_WRITE_TOUT		(5 * CONFIG_SYS_HZ)
+#define CONFIG_SYS_MAX_DATAFLASH_BANKS		1
+#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
+#define AT91_SPI_CLK				15000000
+#define DATAFLASH_TCSS				(0x1a << 16)
+#define DATAFLASH_TCHS				(0x1 << 24)
+
+/* NOR flash, if populated */
+#define CONFIG_SYS_FLASH_CFI		1
+#define CONFIG_FLASH_CFI_DRIVER		1
+#define PHYS_FLASH_1			0x10000000
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_MAX_FLASH_SECT	256
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CONFIG_SYS_NAND_DBW_8		1
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN	GPIO_PIN_PD(15)
+#define CONFIG_SYS_NAND_READY_PIN	GPIO_PIN_PB(30)
+
+#endif
+
+#define CONFIG_CMD_JFFS2		1
+#define CONFIG_JFFS2_CMDLINE		1
+#define CONFIG_JFFS2_NAND		1
+#define CONFIG_JFFS2_DEV		"nand0" /* NAND device jffs2 lives on */
+#define CONFIG_JFFS2_PART_OFFSET	0	/* start of jffs2 partition */
+#define CONFIG_JFFS2_PART_SIZE		(256 * 1024 * 1024) /* partition size*/
+
+/* PSRAM */
+#define	PHYS_PSRAM			0x70000000
+#define	PHYS_PSRAM_SIZE			0x00400000	/* 4MB */
+/* Slave EBI1, PSRAM connected */
+#define CONFIG_PSRAM_SCFG		(AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY	| \
+					 AT91_MATRIX_SCFG_FIXED_DEFMSTR(5)	| \
+					 AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED	| \
+					 AT91_MATRIX_SCFG_SLOT_CYCLE(255))
+
+/* Ethernet */
+#define CONFIG_MACB			1
+#define CONFIG_RMII			1
+#define CONFIG_NET_RETRY_COUNT		20
+#define CONFIG_RESET_PHY_R		1
+
+/* USB */
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
+#define CONFIG_USB_OHCI_NEW			1
+#define CONFIG_DOS_PARTITION			1
+#define CONFIG_SYS_USB_OHCI_CPU_INIT		1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00a00000	/* AT91SAM9263_UHP_BASE */
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9263"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+#define CONFIG_USB_STORAGE			1
+
+#define CONFIG_SYS_LOAD_ADDR			0x22000000	/* load address */
+
+#define CONFIG_SYS_MEMTEST_START		PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END			0x23e00000
+
+#define CONFIG_SYS_USE_FLASH	1
+#undef CONFIG_SYS_USE_DATAFLASH
+#undef CONFIG_SYS_USE_NANDFLASH
+
+#ifdef CONFIG_SYS_USE_DATAFLASH
+
+/* bootstrap + u-boot + env + linux in dataflash on CS0 */
+#define CONFIG_ENV_IS_IN_DATAFLASH
+#define CFG_MONITOR_BASE	(CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
+#define CONFIG_ENV_OFFSET	0x4200
+#define CONFIG_ENV_ADDR		(CFG_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SIZE		0x4200
+#define CONFIG_BOOTCOMMAND	"cp.b 0xC0042000 0x22000000 0x210000; bootm"
+#define CONFIG_BOOTARGS		"console=ttyS0,115200 " \
+				"root=/dev/mtdblock0 " \
+				"mtdparts=atmel_nand:-(root) "\
+				"rw rootfstype=jffs2"
+
+#elif defined(CONFIG_SYS_USE_NANDFLASH) /* CFG_USE_NANDFLASH */
+
+/* bootstrap + u-boot + env + linux in nandflash */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		0x60000
+#define CONFIG_ENV_OFFSET_REDUND	0x80000
+#define CONFIG_ENV_SIZE		0x20000		/* 1 sector = 128 kB */
+#define CONFIG_BOOTCOMMAND	"nand read 0x22000000 0xA0000 0x200000; bootm"
+#define CONFIG_BOOTARGS		"console=ttyS0,115200 "		\
+				"root=/dev/mtdblock5 "		\
+				"mtdparts=atmel_nand:"		\
+					"128k(bootstrap)ro,"	\
+					"256k(uboot)ro,"	\
+					"128k(env1)ro,"		\
+					"128k(env2)ro,"		\
+					"2M(linux),"		\
+					"-(root) "		\
+				"rw rootfstype=jffs2"
+
+#elif defined(CONFIG_SYS_USE_FLASH) /* CFG_USE_FLASH */
+
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_OFFSET	0x40000
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#define	CONFIG_ENV_SIZE		0x10000
+#define CONFIG_ENV_OVERWRITE	1
+
+/* JFFS Partition offset set */
+#define CONFIG_SYS_JFFS2_FIRST_BANK	0
+#define CONFIG_SYS_JFFS2_NUM_BANKS	1
+
+/* 512k reserved for u-boot */
+#define CONFIG_SYS_JFFS2_FIRST_SECTOR	11
+
+#define CONFIG_BOOTCOMMAND		"run flashboot"
+#define CONFIG_ROOTPATH			"/ronetix/rootfs"
+#define CONFIG_AUTOBOOT_PROMPT		"autoboot in %d seconds\n", bootdelay
+
+#define CONFIG_CON_ROT			"fbcon=rotate:3 "
+#define CONFIG_BOOTARGS			"root=/dev/mtdblock4 rootfstype=jffs2 "\
+					CONFIG_CON_ROT
+
+#define MTDIDS_DEFAULT			"nor0=physmap-flash.0,nand0=nand"
+#define MTDPARTS_DEFAULT		\
+	"mtdparts=physmap-flash.0:"	\
+		"256k(u-boot)ro,"	\
+		"64k(u-boot-env)ro,"	\
+		"1408k(kernel),"	\
+		"-(rootfs);"		\
+	"nand:-(nand)"
+
+#define CONFIG_EXTRA_ENV_SETTINGS				\
+	"mtdids=" MTDIDS_DEFAULT "\0"				\
+	"mtdparts=" MTDPARTS_DEFAULT "\0"			\
+	"partition=nand0,0\0"					\
+	"ramargs=setenv bootargs $(bootargs) $(mtdparts)\0"	\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "		\
+		CONFIG_CON_ROT					\
+		"nfsroot=$(serverip):$(rootpath) $(mtdparts)\0"	\
+	"addip=setenv bootargs $(bootargs) "			\
+		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\
+		":$(hostname):eth0:off\0"			\
+	"ramboot=tftpboot 0x22000000 vmImage;"			\
+		"run ramargs;run addip;bootm 22000000\0"	\
+	"nfsboot=tftpboot 0x22000000 vmImage;"			\
+		"run nfsargs;run addip;bootm 22000000\0"	\
+	"flashboot=run ramargs;run addip;bootm 0x10050000\0"	\
+	""
+
+#else
+#error "Undefined memory device"
+#endif
+
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_SYS_PROMPT		"u-boot-pm9263> "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_PBSIZE		\
+		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP		1
+#define CONFIG_CMDLINE_EDITING		1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN	ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
+
+#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE + 0x1000 - \
+				GENERATED_GBL_DATA_SIZE)
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/pm9g45.h b/qemu/roms/u-boot/include/configs/pm9g45.h
new file mode 100644
index 000000000..f78e0ec17
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/pm9g45.h
@@ -0,0 +1,175 @@
+/*
+ * (C) Copyright 2010
+ * Ilko Iliev <iliev@ronetix.at>
+ * Asen Dimov <dimov@ronetix.at>
+ * Ronetix GmbH <www.ronetix.at>
+ *
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * Configuation settings for the PM9G45 board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * SoC must be defined first, before hardware.h is included.
+ * In this case SoC is defined in boards.cfg.
+ */
+#include <asm/hardware.h>
+
+#define CONFIG_PM9G45		1	/* It's an Ronetix PM9G45 */
+#define CONFIG_SYS_AT91_CPU_NAME	"AT91SAM9G45"
+
+#define MACH_TYPE_PM9G45	2672
+#define CONFIG_MACH_TYPE	MACH_TYPE_PM9G45
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	12000000 /* from 12 MHz crystal */
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
+#define CONFIG_SYS_TEXT_BASE		0x73f00000
+
+#define CONFIG_ARCH_CPU_INIT
+
+#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG	1
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_AT91_GPIO	1
+#define CONFIG_ATMEL_USART	1
+#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
+#define	CONFIG_USART_ID			ATMEL_ID_SYS
+
+#define CONFIG_SYS_USE_NANDFLASH	1
+
+/* LED */
+#define CONFIG_AT91_LED
+#define CONFIG_RED_LED		GPIO_PIN_PD(31) /* this is the user1 led */
+#define CONFIG_GREEN_LED	GPIO_PIN_PD(0)  /* this is the user2 led */
+
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE	1
+#define CONFIG_BOOTP_BOOTPATH		1
+#define CONFIG_BOOTP_GATEWAY		1
+#define CONFIG_BOOTP_HOSTNAME		1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_PING		1
+#define CONFIG_CMD_DHCP		1
+#define CONFIG_CMD_NAND		1
+#define CONFIG_CMD_USB		1
+
+#define CONFIG_CMD_JFFS2		1
+#define CONFIG_JFFS2_CMDLINE		1
+#define CONFIG_JFFS2_NAND		1
+#define CONFIG_JFFS2_DEV		"nand0" /* NAND dev jffs2 lives on */
+#define CONFIG_JFFS2_PART_OFFSET	0	/* start of jffs2 partition */
+#define CONFIG_JFFS2_PART_SIZE		(256 * 1024 * 1024) /* partition */
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			0x70000000
+#define PHYS_SDRAM_SIZE			0x08000000	/* 128 megs */
+
+/* NOR flash, not available */
+#define CONFIG_SYS_NO_FLASH		1
+#undef CONFIG_CMD_FLASH
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CONFIG_SYS_NAND_DBW_8		1
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN	GPIO_PIN_PC(14)
+#define CONFIG_SYS_NAND_READY_PIN	GPIO_PIN_PD(3)
+
+#endif
+
+/* Ethernet */
+#define CONFIG_MACB			1
+#define CONFIG_RMII			1
+#define CONFIG_NET_RETRY_COUNT		20
+#define CONFIG_RESET_PHY_R		1
+
+/* USB */
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
+#define CONFIG_USB_OHCI_NEW		1
+#define CONFIG_DOS_PARTITION		1
+#define CONFIG_SYS_USB_OHCI_CPU_INIT	1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE	0x00700000 /* _UHP_OHCI_BASE */
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"at91sam9g45"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+#define CONFIG_USB_STORAGE		1
+
+/* board specific(not enough SRAM) */
+#define CONFIG_AT91SAM9G45_LCD_BASE	PHYS_SDRAM + 0xE00000
+
+#define CONFIG_SYS_LOAD_ADDR		PHYS_SDRAM + 0x2000000 /* load addr */
+
+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END		CONFIG_AT91SAM9G45_LCD_BASE
+
+/* bootstrap + u-boot + env + linux in nandflash */
+#define CONFIG_ENV_IS_IN_NAND		1
+#define CONFIG_ENV_OFFSET		0x60000
+#define CONFIG_ENV_OFFSET_REDUND	0x80000
+#define CONFIG_ENV_SIZE			0x20000		/* 1 sector = 128 kB */
+#define CONFIG_BOOTCOMMAND	"nand read 0x72000000 0x200000 0x200000; bootm"
+#define CONFIG_BOOTARGS		"fbcon=rotate:3 console=tty0 " \
+				"console=ttyS0,115200 " \
+				"root=/dev/mtdblock4 " \
+				"mtdparts=atmel_nand:128k(bootstrap)ro," \
+				"256k(uboot)ro,1664k(env)," \
+				"2M(linux)ro,-(root) rw " \
+				"rootfstype=jffs2"
+
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_SYS_PROMPT		"U-Boot> "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP		1
+#define CONFIG_CMDLINE_EDITING		1
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + 128*1024,\
+					0x1000)
+
+#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE + 0x1000 - \
+				GENERATED_GBL_DATA_SIZE)
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/pogo_e02.h b/qemu/roms/u-boot/include/configs/pogo_e02.h
new file mode 100644
index 000000000..a81d45219
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/pogo_e02.h
@@ -0,0 +1,105 @@
+/*
+ * Copyright (C) 2012
+ * David Purdy <david.c.purdy@gmail.com>
+ *
+ * Based on Kirkwood support:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CONFIG_POGO_E02_H
+#define _CONFIG_POGO_E02_H
+
+/*
+ * Machine type definition and ID
+ */
+#define MACH_TYPE_POGO_E02		3542
+#define CONFIG_MACH_TYPE		MACH_TYPE_POGO_E02
+#define CONFIG_IDENT_STRING		"\nPogo E02"
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_FEROCEON_88FR131		/* CPU Core subversion */
+#define CONFIG_KIRKWOOD			/* SOC Family Name */
+#define CONFIG_KW88F6281		/* SOC Name */
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
+#define CONFIG_SYS_MVFS
+#include <config_cmd_default.h>
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/* Remove or override few declarations from mv-common.h */
+#undef CONFIG_SYS_PROMPT	/* previously defined in mv-common.h */
+#define CONFIG_SYS_PROMPT	"PogoE02> "
+
+/*
+ *  Environment variables configurations
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SECT_SIZE		0x20000	/* 128K */
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+#define CONFIG_ENV_SIZE			0x20000	/* 128k */
+#define CONFIG_ENV_OFFSET		0x60000	/* env starts here */
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_BOOTCOMMAND \
+	"setenv bootargs $(bootargs_console); " \
+	"run bootcmd_usb; " \
+	"bootm 0x00800000 0x01100000"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"mtdparts=mtdparts=orion_nand:1M(u-boot),4M(uImage)," \
+	"32M(rootfs),-(data)\0"\
+	"mtdids=nand0=orion_nand\0"\
+	"bootargs_console=console=ttyS0,115200\0" \
+	"bootcmd_usb=usb start; ext2load usb 0:1 0x00800000 /uImage; " \
+	"ext2load usb 0:1 0x01100000 /uInitrd\0"
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS	{1, 0}	/* enable port 0 only */
+#define CONFIG_PHY_BASE_ADR	0
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * File system
+ */
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_LZO
+
+#endif /* _CONFIG_POGO_E02_H */
diff --git a/qemu/roms/u-boot/include/configs/ppmc7xx.h b/qemu/roms/u-boot/include/configs/ppmc7xx.h
new file mode 100644
index 000000000..18f9a6cc2
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/ppmc7xx.h
@@ -0,0 +1,416 @@
+/*
+ * ppmc7xx.h
+ * ---------
+ *
+ * Wind River PPMC 7xx/74xx board configuration file.
+ *
+ * By Richard Danter (richard.danter@windriver.com)
+ * Copyright (C) 2005 Wind River Systems
+ */
+
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_PPMC7XX
+
+
+/*===================================================================
+ *
+ * User configurable settings - Modify to your preference
+ *
+ *===================================================================
+ */
+
+/*
+ * Debug
+ *
+ * DEBUG		- Define this is you want extra debug info
+ * GTREGREAD		- Required to build with debug
+ * do_bdinfo		- Required to build with debug
+ */
+
+#ifdef	DEBUG
+#define	GTREGREAD(x)	0xFFFFFFFF
+#define	do_bdinfo(a,b,c,d)
+#endif
+
+/*
+ * CPU type
+ *
+ * CONFIG_7xx		- We have a 750 or 755 CPU
+ * CONFIG_74xx		- We have a 7400 CPU
+ * CONFIG_ALTIVEC	- We have altivec enabled CPU (only 7400)
+ * CONFIG_BUS_CLK	- System bus clock in Hz
+ */
+
+#define	CONFIG_7xx
+#undef	CONFIG_74xx
+#undef	CONFIG_ALTIVEC
+#define CONFIG_BUS_CLK	66000000
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
+
+#ifndef __ASSEMBLY__
+#include <galileo/core.h>
+#endif
+
+/*
+ * Monitor configuration
+ *
+ * List of command sets to include in shell
+ *
+ * The following command sets have been tested and known to work:
+ *
+ * CMD_CACHE		- Cache control commands
+ * CMD_MEMORY		- Memory display, change and test commands
+ * CMD_FLASH		- Erase and program flash
+ * CMD_ENV		- Environment commands
+ * CMD_RUN		- Run commands stored in env vars
+ * CMD_ELF		- Load ELF files
+ * CMD_NET		- Networking/file download commands
+ * CMD_PIN		- ICMP Echo Request command
+ * CMD_PCI		- PCI Bus scanning command
+ */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_PCI
+
+#undef CONFIG_CMD_KGDB
+
+
+/*
+ * Serial configuration
+ *
+ * CONFIG_CONS_INDEX		- Serial console port number (COM1)
+ * CONFIG_BAUDRATE		- Serial speed
+ */
+
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		9600
+
+
+/*
+ * PCI config
+ *
+ * CONFIG_PCI			- Enable PCI bus
+ * CONFIG_PCI_PNP		- Enable Plug & Play support
+ * CONFIG_PCI_SCAN_SHOW		- Enable display of devices at startup
+ */
+
+#define	CONFIG_PCI
+#define	CONFIG_PCI_INDIRECT_BRIDGE
+#define	CONFIG_PCI_PNP
+#undef	CONFIG_PCI_SCAN_SHOW
+
+
+/*
+ * Network config
+ *
+ * CONFIG_EEPRO100		- Intel 8255x Ethernet Controller
+ * CONFIG_EEPRO100_SROM_WRITE	- Enable writing to network card ROM
+ */
+
+#define	CONFIG_EEPRO100
+#define	CONFIG_EEPRO100_SROM_WRITE
+
+
+/*
+ * Enable extra init functions
+ *
+ * CONFIG_MISC_INIT_F		- Call pre-relocation init functions
+ * CONFIG_MISC_INIT_R		- Call post relocation init functions
+ */
+
+#undef	CONFIG_MISC_INIT_F
+#define CONFIG_MISC_INIT_R
+
+
+/*
+ * Boot config
+ *
+ * CONFIG_BOOTCOMMAND		- Command(s) to execute to auto-boot
+ * CONFIG_BOOTDELAY		- How long to wait before auto-boot (in sec)
+ */
+
+#define CONFIG_BOOTCOMMAND		\
+	"bootp;" \
+	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
+	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
+	"bootm"
+#define CONFIG_BOOTDELAY		5
+
+
+/*===================================================================
+ *
+ * Board configuration settings - You should not need to modify these
+ *
+ *===================================================================
+ */
+
+
+/*
+ * Memory map
+ *
+ * This board runs in a standard CHRP (Map-B) configuration.
+ *
+ *	Type	    Start	End	    Size    Width   Chip Sel
+ *	----------- ----------- ----------- ------- ------- --------
+ *	SDRAM	    0x00000000	0x04000000  64MB    64b	    SDRAMCS0
+ *	User LED's  0x78000000				    RCS3
+ *	UART	    0x7C000000				    RCS2
+ *	Mailbox	    0xFF000000				    RCS1
+ *	Flash	    0xFFC00000	0xFFFFFFFF   4MB    64b	    RCS0
+ *
+ * Flash sectors are laid out as follows.
+ *
+ *	Sector	Start		End	Size	Comments
+ *	------- ----------- ----------- ------- -----------
+ *	 0	0xFFC00000  0xFFC3FFFF	256KB
+ *	 1	0xFFC40000  0xFFC7FFFF	256KB
+ *	 2	0xFFC80000  0xFFCBFFFF	256KB
+ *	 3	0xFFCC0000  0xFFCFFFFF	256KB
+ *	 4	0xFFD00000  0xFFD3FFFF	256KB
+ *	 5	0xFFD40000  0xFFD7FFFF	256KB
+ *	 6	0xFFD80000  0xFFDBFFFF	256KB
+ *	 7	0xFFDC0000  0xFFDFFFFF	256KB
+ *	 8	0xFFE00000  0xFFE3FFFF	256KB
+ *	 9	0xFFE40000  0xFFE7FFFF	256KB
+ *	10	0xFFE80000  0xFFEBFFFF	256KB
+ *	11	0xFFEC0000  0xFFEFFFFF	256KB
+ *	12	0xFFF00000  0xFFF3FFFF	256KB	U-Boot code here
+ *	13	0xFFF40000  0xFFF7FFFF	256KB
+ *	14	0xFFF80000  0xFFFBFFFF	256KB
+ *	15	0xFFFC0000  0xFFFDFFFF	128KB
+ *	16	0xFFFE0000  0xFFFE7FFF	 32KB	U-Boot env vars here
+ *	17	0xFFFE8000  0xFFFEFFFF	 32KB	U-Boot backup copy of env vars here
+ *	18	0xFFFF0000  0xFFFFFFFF	 64KB
+ */
+
+
+/*
+ * SDRAM config - see memory map details above.
+ *
+ * CONFIG_SYS_SDRAM_BASE		- Start address of SDRAM, this _must_ be zero!
+ * CONFIG_SYS_SDRAM_SIZE		- Total size of contiguous SDRAM bank(s)
+ */
+
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_SIZE		0x04000000
+
+
+/*
+ * Flash config - see memory map details above.
+ *
+ * CONFIG_SYS_FLASH_BASE		- Start address of flash memory
+ * CONFIG_SYS_FLASH_SIZE		- Total size of contiguous flash mem
+ * CONFIG_SYS_FLASH_ERASE_TOUT		- Erase timeout in ms
+ * CONFIG_SYS_FLASH_WRITE_TOUT		- Write timeout in ms
+ * CONFIG_SYS_MAX_FLASH_BANKS		- Number of banks of flash on board
+ * CONFIG_SYS_MAX_FLASH_SECT		- Number of sectors in a bank
+ */
+
+#define CONFIG_SYS_FLASH_BASE		0xFFC00000
+#define CONFIG_SYS_FLASH_SIZE		0x00400000
+#define CONFIG_SYS_FLASH_ERASE_TOUT	250000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	5000
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	128
+
+
+/*
+ * Monitor config - see memory map details above
+ *
+ * CONFIG_SYS_MONITOR_BASE		- Base address of monitor code
+ * CONFIG_SYS_MALLOC_LEN		- Size of malloc pool (128KB)
+ */
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MALLOC_LEN		0x20000
+
+
+/*
+ * Command shell settings
+ *
+ * CONFIG_SYS_BARGSIZE			- Boot Argument buffer size
+ * CONFIG_SYS_BOOTMAPSZ		- Size of app's mapped RAM at boot (Linux=8MB)
+ * CONFIG_SYS_CBSIZE			- Console Buffer (input) size
+ * CONFIG_SYS_LOAD_ADDR		- Default load address
+ * CONFIG_SYS_LONGHELP			- Provide more detailed help
+ * CONFIG_SYS_MAXARGS			- Number of args accepted by monitor commands
+ * CONFIG_SYS_MEMTEST_START		- Start address of test to run on RAM
+ * CONFIG_SYS_MEMTEST_END		- End address of RAM test
+ * CONFIG_SYS_PBSIZE			- Print Buffer (output) size
+ * CONFIG_SYS_PROMPT			- Prompt string
+ */
+
+#define CONFIG_SYS_BARGSIZE		1024
+#define CONFIG_SYS_BOOTMAPSZ		0x800000
+#define CONFIG_SYS_CBSIZE		1024
+#define CONFIG_SYS_LOAD_ADDR		0x100000
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_MEMTEST_START	0x00040000
+#define CONFIG_SYS_MEMTEST_END		0x00040100
+#define CONFIG_SYS_PBSIZE		1024
+
+
+/*
+ * Environment config - see memory map details above
+ *
+ * CONFIG_ENV_IS_IN_FLASH		- The env variables are stored in flash
+ * CONFIG_ENV_ADDR			- Address of the sector containing env vars
+ * CONFIG_ENV_SIZE			- Ammount of RAM for env vars (used to save RAM, 4KB)
+ * CONFIG_ENV_SECT_SIZE		- Size of sector containing env vars (32KB)
+ */
+
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_ADDR		0xFFFE0000
+#define CONFIG_ENV_SIZE		0x1000
+#define CONFIG_ENV_ADDR_REDUND	0xFFFE8000
+#define CONFIG_ENV_SIZE_REDUND	0x1000
+#define CONFIG_ENV_SECT_SIZE	0x8000
+
+
+/*
+ * Initial RAM config
+ *
+ * Since the main system RAM is initialised very early, we place the INIT_RAM
+ * in the main system RAM just above the exception vectors. The contents are
+ * copied to top of RAM by the init code.
+ *
+ * CONFIG_SYS_INIT_RAM_ADDR		- Address of Init RAM, above exception vect
+ * CONFIG_SYS_INIT_RAM_SIZE		- Size of Init RAM
+ * GENERATED_GBL_DATA_SIZE		- Ammount of RAM to reserve for global data
+ * CONFIG_SYS_GBL_DATA_OFFSET		- Start of global data, top of stack
+ */
+
+#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_SDRAM_BASE + 0x4000)
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+
+/*
+ * Initial BAT config
+ *
+ * BAT0	- System SDRAM
+ * BAT1 - LED's and Serial Port
+ * BAT2 - PCI Memory
+ * BAT3 - PCI I/O including Flash Memory
+ */
+
+#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
+
+#define CONFIG_SYS_IBAT1L (0x70000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT1L (0x70000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT2L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT3L (0xF0000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+
+/*
+ * Cache config
+ *
+ * CONFIG_SYS_CACHELINE_SIZE		- Size of a cache line (CPU specific)
+ * CONFIG_SYS_L2			- L2 cache enabled if defined
+ * L2_INIT			- L2 cache init flags
+ * L2_ENABLE			- L2 cache enable flags
+ */
+
+#define CONFIG_SYS_CACHELINE_SIZE	32
+#undef	CONFIG_SYS_L2
+#define L2_INIT			0
+#define L2_ENABLE		0
+
+
+/*
+ * Clocks config
+ *
+ * CONFIG_SYS_BUS_CLK			- Bus clock frequency in Hz
+ * CONFIG_SYS_HZ			- Decrementer freq in Hz
+ */
+
+#define CONFIG_SYS_BUS_CLK		CONFIG_BUS_CLK
+
+
+/*
+ * Serial port config
+ *
+ * CONFIG_SYS_NS16550			- Include the NS16550 driver
+ * CONFIG_SYS_NS16550_SERIAL		- Include the serial (wrapper) driver
+ * CONFIG_SYS_NS16550_CLK		- Frequency of reference clock
+ * CONFIG_SYS_NS16550_REG_SIZE		- 64-bit accesses to 8-bit port
+ * CONFIG_SYS_NS16550_COM1		- Base address of 1st serial port
+ */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_CLK		3686400
+#define CONFIG_SYS_NS16550_REG_SIZE	-8
+#define CONFIG_SYS_NS16550_COM1	0x7C000000
+
+
+/*
+ * PCI Config - Address Map B (CHRP)
+ */
+
+#define CONFIG_SYS_PCI_MEMORY_BUS	0x00000000
+#define CONFIG_SYS_PCI_MEMORY_PHYS	0x00000000
+#define CONFIG_SYS_PCI_MEMORY_SIZE	0x40000000
+#define CONFIG_SYS_PCI_MEM_BUS		0x80000000
+#define CONFIG_SYS_PCI_MEM_PHYS	0x80000000
+#define CONFIG_SYS_PCI_MEM_SIZE	0x7D000000
+#define CONFIG_SYS_ISA_MEM_BUS		0x00000000
+#define CONFIG_SYS_ISA_MEM_PHYS	0xFD000000
+#define CONFIG_SYS_ISA_MEM_SIZE	0x01000000
+#define CONFIG_SYS_PCI_IO_BUS		0x00800000
+#define CONFIG_SYS_PCI_IO_PHYS		0xFE800000
+#define CONFIG_SYS_PCI_IO_SIZE		0x00400000
+#define CONFIG_SYS_ISA_IO_BUS		0x00000000
+#define CONFIG_SYS_ISA_IO_PHYS		0xFE000000
+#define CONFIG_SYS_ISA_IO_SIZE		0x00800000
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_ISA_IO_PHYS
+#define CONFIG_SYS_ISA_IO		CONFIG_SYS_ISA_IO_PHYS
+#define CONFIG_SYS_60X_PCI_IO_OFFSET	CONFIG_SYS_ISA_IO_PHYS
+
+
+/*
+ * Extra init functions
+ *
+ * CONFIG_SYS_BOARD_ASM_INIT		- Call assembly init code
+ */
+
+#define CONFIG_SYS_BOARD_ASM_INIT
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/ppmc8260.h b/qemu/roms/u-boot/include/configs/ppmc8260.h
new file mode 100644
index 000000000..5dcd9cc0d
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/ppmc8260.h
@@ -0,0 +1,986 @@
+/*
+ * (C) Copyright 2000
+ * Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ *
+ * (C) Copyright 2000
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2001
+ * Advent Networks, Inc. <http://www.adventnetworks.com>
+ * Jay Monkman <jtm@smoothsmoothie.com>
+ *
+ * Configuation settings for the WindRiver PPMC8260 board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define	CONFIG_SYS_TEXT_BASE	0xfe000000
+
+/*****************************************************************************
+ *
+ * These settings must match the way _your_ board is set up
+ *
+ *****************************************************************************/
+
+/* What is the oscillator's (UX2) frequency in Hz? */
+#define CONFIG_8260_CLKIN  (66 * 1000 * 1000)
+
+/*-----------------------------------------------------------------------
+ * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
+ *-----------------------------------------------------------------------
+ * What should MODCK_H be? It is dependent on the oscillator
+ * frequency, MODCK[1-3], and desired CPM and core frequencies.
+ * Here are some example values (all frequencies are in MHz):
+ *
+ * MODCK_H   MODCK[1-3]	 Osc	CPM    Core  S2-6   S2-7   S2-8
+ * -------   ----------	 ---	---    ----  -----  -----  -----
+ * 0x2	     0x2	 33	133    133   Close  Open   Close
+ * 0x2	     0x3	 33	133    166   Close  Open   Open
+ * 0x2	     0x4	 33	133    200   Open   Close  Close
+ * 0x2	     0x5	 33	133    233   Open   Close  Open
+ * 0x2	     0x6	 33	133    266   Open   Open   Close
+ *
+ * 0x5	     0x5	 66	133    133   Open   Close  Open
+ * 0x5	     0x6	 66	133    166   Open   Open   Close
+ * 0x5	     0x7	 66	133    200   Open   Open   Open
+ * 0x6	     0x0	 66	133    233   Close  Close  Close
+ * 0x6	     0x1	 66	133    266   Close  Close  Open
+ * 0x6	     0x2	 66	133    300   Close  Open   Close
+ */
+#define CONFIG_SYS_PPMC_MODCK_H 0x05
+
+/* Define this if you want to boot from 0x00000100. If you don't define
+ * this, you will need to program the bootloader to 0xfff00000, and
+ * get the hardware reset config words at 0xfe000000. The simplest
+ * way to do that is to program the bootloader at both addresses.
+ * It is suggested that you just let U-Boot live at 0x00000000.
+ */
+#define CONFIG_SYS_PPMC_BOOT_LOW 1
+
+/* What should the base address of the main FLASH be and how big is
+ * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/ppmc8260/config.mk
+ * The main FLASH is whichever is connected to *CS0. U-Boot expects
+ * this to be the SIMM.
+ */
+#define CONFIG_SYS_FLASH0_BASE 0xFE000000
+#define CONFIG_SYS_FLASH0_SIZE 16
+
+/* What should be the base address of the first SDRAM DIMM and how big is
+ * it (in Mbytes)?
+*/
+#define CONFIG_SYS_SDRAM0_BASE 0x00000000
+#define CONFIG_SYS_SDRAM0_SIZE 128
+
+/* What should be the base address of the second SDRAM DIMM and how big is
+ * it (in Mbytes)?
+*/
+#define CONFIG_SYS_SDRAM1_BASE 0x08000000
+#define CONFIG_SYS_SDRAM1_SIZE 128
+
+/* What should be the base address of the on board SDRAM and how big is
+ * it (in Mbytes)?
+*/
+#define CONFIG_SYS_SDRAM2_BASE 0x38000000
+#define CONFIG_SYS_SDRAM2_SIZE 16
+
+/* What should be the base address of the MAILBOX  and how big is it
+ * (in Bytes)
+ * The eeprom lives at CONFIG_SYS_MAILBOX_BASE + 0x80000000
+ */
+#define CONFIG_SYS_MAILBOX_BASE 0x32000000
+#define CONFIG_SYS_MAILBOX_SIZE 8192
+
+/* What is the base address of the I/O select lines and how big is it
+ * (In Mbytes)?
+ */
+
+#define CONFIG_SYS_IOSELECT_BASE 0xE0000000
+#define CONFIG_SYS_IOSELECT_SIZE 32
+
+
+/* What should be the base address of the LEDs and switch S0?
+ * If you don't want them enabled, don't define this.
+ */
+#define CONFIG_SYS_LED_BASE 0xF1000000
+
+/*
+ * PPMC8260 with 256 16 MB DIMM:
+ *
+ *     0x0000 0000     Exception Vector code, 8k
+ *	     :
+ *     0x0000 1FFF
+ *     0x0000 2000     Free for Application Use
+ *	     :
+ *	     :
+ *
+ *	     :
+ *	     :
+ *     0x0FF5 FF30     Monitor Stack (Growing downward)
+ *		       Monitor Stack Buffer (0x80)
+ *     0x0FF5 FFB0     Board Info Data
+ *     0x0FF6 0000     Malloc Arena
+ *	     :		    CONFIG_ENV_SECT_SIZE, 256k
+ *	     :		    CONFIG_SYS_MALLOC_LEN,    128k
+ *     0x0FFC 0000     RAM Copy of Monitor Code
+ *	     :		    CONFIG_SYS_MONITOR_LEN,   256k
+ *     0x0FFF FFFF     [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1
+ */
+
+
+/*
+ * select serial console configuration
+ *
+ * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ *
+ * if CONFIG_CONS_NONE is defined, then the serial console routines must
+ * defined elsewhere.
+ * The console can be on SMC1 or SMC2
+ */
+#define CONFIG_CONS_ON_SMC	1	/* define if console on SMC */
+#undef	CONFIG_CONS_ON_SCC		/* define if console on SCC */
+#undef	CONFIG_CONS_NONE		/* define if console on neither */
+#define CONFIG_CONS_INDEX	1	/* which SMC/SCC channel for console */
+
+/*
+ * select ethernet configuration
+ *
+ * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
+ * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
+ * for FCC)
+ *
+ * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
+ */
+
+#undef	CONFIG_ETHER_ON_SCC		/* define if ethernet on SCC	*/
+#define CONFIG_ETHER_ON_FCC		/* define if ethernet on FCC	*/
+#undef	CONFIG_ETHER_NONE		/* define if ethernet on neither */
+#define CONFIG_ETHER_INDEX	2	/* which SCC/FCC channel for ethernet */
+#define CONFIG_MII			/* MII PHY management	*/
+#define CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
+/*
+ * Port pins used for bit-banged MII communictions (if applicable).
+ */
+#define MDIO_PORT	2	/* Port C */
+#define MDIO_DECLARE	volatile ioport_t *iop = ioport_addr ( \
+				(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
+#define MDC_DECLARE	MDIO_DECLARE
+
+#define MDIO_ACTIVE	(iop->pdir |=  0x00400000)
+#define MDIO_TRISTATE	(iop->pdir &= ~0x00400000)
+#define MDIO_READ	((iop->pdat &  0x00400000) != 0)
+
+#define MDIO(bit)	if(bit) iop->pdat |=  0x00400000; \
+			else	iop->pdat &= ~0x00400000
+
+#define MDC(bit)	if(bit) iop->pdat |=  0x00200000; \
+			else	iop->pdat &= ~0x00200000
+
+#define MIIDELAY	udelay(1)
+
+
+/* Define this to reserve an entire FLASH sector (256 KB) for
+ * environment variables. Otherwise, the environment will be
+ * put in the same sector as U-Boot, and changing variables
+ * will erase U-Boot temporarily
+ */
+#define CONFIG_ENV_IN_OWN_SECT	1
+
+/* Define to allow the user to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* What should the console's baud rate be? */
+#define CONFIG_BAUDRATE		9600
+
+/* Ethernet MAC address */
+
+#define CONFIG_ETHADDR		00:a0:1e:90:2b:00
+
+/* Define this to set the last octet of the ethernet address
+ * from the DS0-DS7 switch and light the leds with the result
+ * The DS0-DS7 switch and the leds are backwards with respect
+ * to each other. DS7 is on the board edge side of both the
+ * led strip and the DS0-DS7 switch.
+ */
+#define CONFIG_MISC_INIT_R
+
+/* Set to a positive value to delay for running BOOTCOMMAND */
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+
+#if 0
+/* Be selective on what keys can delay or stop the autoboot process
+ *     To stop	use: " "
+ */
+# define CONFIG_AUTOBOOT_KEYED
+# define CONFIG_AUTOBOOT_PROMPT \
+	"Autobooting in %d seconds, press \" \" to stop\n", bootdelay
+# define CONFIG_AUTOBOOT_STOP_STR	" "
+# undef CONFIG_AUTOBOOT_DELAY_STR
+# define DEBUG_BOOTKEYS		0
+#endif
+
+/* Define a command string that is automatically executed when no character
+ * is read on the console interface withing "Boot Delay" after reset.
+ */
+#undef	CONFIG_BOOT_ROOT_INITRD		/* Use ram disk for the root file system */
+#define	CONFIG_BOOT_ROOT_NFS		/* Use a NFS mounted root file system */
+
+#ifdef CONFIG_BOOT_ROOT_INITRD
+#define CONFIG_BOOTCOMMAND \
+	"version;" \
+	"echo;" \
+	"bootp;" \
+	"setenv bootargs root=/dev/ram0 rw " \
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
+	"bootm"
+#endif /* CONFIG_BOOT_ROOT_INITRD */
+
+#ifdef CONFIG_BOOT_ROOT_NFS
+#define CONFIG_BOOTCOMMAND \
+	"version;" \
+	"echo;" \
+	"bootp;" \
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
+	"bootm"
+#endif /* CONFIG_BOOT_ROOT_NFS */
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_DNS
+
+
+/* undef this to save memory */
+#define CONFIG_SYS_LONGHELP
+
+/* Monitor Command Prompt */
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_IMMAP
+
+#undef CONFIG_CMD_KGDB
+
+
+/* Where do the internal registers live? */
+#define CONFIG_SYS_IMMR		0xf0000000
+
+/*****************************************************************************
+ *
+ * You should not have to modify any of the following settings
+ *
+ *****************************************************************************/
+
+#define CONFIG_PPMC8260		1	/* on an Wind River PPMC8260 Board  */
+#define CONFIG_CPM2		1	/* Has a CPM2 */
+
+/*
+ * Miscellaneous configurable options
+ */
+#if defined(CONFIG_CMD_KGDB)
+#  define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	     */
+#else
+#  define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	     */
+#endif
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE	  (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
+
+#define CONFIG_SYS_MAXARGS		32	/* max number of command args	*/
+
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size	   */
+
+#define CONFIG_SYS_LOAD_ADDR		0x140000   /* default load address */
+
+#define CONFIG_SYS_MEMTEST_START	0x2000	/* memtest works from the end of */
+					/* the exception vector table */
+					/* to the end of the DRAM  */
+					/* less monitor and malloc area */
+#define CONFIG_SYS_STACK_USAGE		0x10000 /* Reserve 64k for the stack usage */
+#define CONFIG_SYS_MEM_END_USAGE	( CONFIG_SYS_MONITOR_LEN \
+				+ CONFIG_SYS_MALLOC_LEN \
+				+ CONFIG_ENV_SECT_SIZE \
+				+ CONFIG_SYS_STACK_USAGE )
+
+#define CONFIG_SYS_MEMTEST_END		( CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 \
+				- CONFIG_SYS_MEM_END_USAGE )
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
+/*
+ *  Attention: This is board specific
+ *  - RX clk is CLK11
+ *  - TX clk is CLK12
+ */
+#define CONFIG_SYS_CMXSCR_VALUE       (CMXSCR_RS1CS_CLK11  |\
+				CMXSCR_TS1CS_CLK12)
+
+#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
+/*
+ * Attention: this is board-specific
+ * - Rx-CLK is CLK13
+ * - Tx-CLK is CLK14
+ * - Select bus for bd/buffers (see 28-13)
+ * - Enable Full Duplex in FSMR
+ */
+#define CONFIG_SYS_CMXFCR_MASK2		(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
+#define CONFIG_SYS_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
+#define CONFIG_SYS_CPMFCR_RAMTYPE	0
+#define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
+#endif	/* CONFIG_ETHER_INDEX */
+
+#define CONFIG_SYS_FLASH_BASE	CONFIG_SYS_FLASH0_BASE
+#define CONFIG_SYS_FLASH_SIZE	CONFIG_SYS_FLASH0_SIZE
+#define CONFIG_SYS_SDRAM_BASE	CONFIG_SYS_SDRAM0_BASE
+#define CONFIG_SYS_SDRAM_SIZE	(CONFIG_SYS_SDRAM0_SIZE + CONFIG_SYS_SDRAM1_SIZE)
+
+/*-----------------------------------------------------------------------
+ * Hard Reset Configuration Words
+ */
+#if defined(CONFIG_SYS_PPMC_BOOT_LOW)
+#  define  CONFIG_SYS_PPMC_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
+#else
+#  define  CONFIG_SYS_PPMC_HRCW_BOOT_FLAGS  (0)
+#endif /* defined(CONFIG_SYS_PPMC_BOOT_LOW) */
+
+/* get the HRCW ISB field from CONFIG_SYS_IMMR */
+#define CONFIG_SYS_PPMC_HRCW_IMMR	( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) | \
+				  ((CONFIG_SYS_IMMR & 0x01000000) >>  7) | \
+				  ((CONFIG_SYS_IMMR & 0x00100000) >>  4) )
+
+#define CONFIG_SYS_HRCW_MASTER		( HRCW_EBM				| \
+				  HRCW_BPS11				| \
+				  HRCW_L2CPC10				| \
+				  HRCW_DPPC00				| \
+				  CONFIG_SYS_PPMC_HRCW_IMMR			| \
+				  HRCW_MMR00				| \
+				  HRCW_LBPC00				| \
+				  HRCW_APPC10				| \
+				  HRCW_CS10PC00				| \
+				  (CONFIG_SYS_PPMC_MODCK_H & HRCW_MODCK_H1111) | \
+				  CONFIG_SYS_PPMC_HRCW_BOOT_FLAGS )
+
+/* no slaves */
+#define CONFIG_SYS_HRCW_SLAVE1		0
+#define CONFIG_SYS_HRCW_SLAVE2		0
+#define CONFIG_SYS_HRCW_SLAVE3		0
+#define CONFIG_SYS_HRCW_SLAVE4		0
+#define CONFIG_SYS_HRCW_SLAVE5		0
+#define CONFIG_SYS_HRCW_SLAVE6		0
+#define CONFIG_SYS_HRCW_SLAVE7		0
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent.
+ */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH0_BASE
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE	0x0ff80000
+#endif
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#  define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 374 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant		*/
+#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_FLASH_INCREMENT	0	/* there is only one bank		*/
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* use hardware protection		*/
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster)     */
+
+
+#ifndef CONFIG_SYS_RAMBOOT
+
+#  define CONFIG_ENV_IS_IN_FLASH	1
+#  ifdef CONFIG_ENV_IN_OWN_SECT
+#    define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE + 0x40000)
+#    define CONFIG_ENV_SECT_SIZE	0x40000
+#  else
+#    define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE)
+#    define CONFIG_ENV_SIZE	0x1000	/* Total Size of Environment Sector	*/
+#    define CONFIG_ENV_SECT_SIZE	0x40000 /* see README - env sect real size	*/
+#  endif /* CONFIG_ENV_IN_OWN_SECT */
+
+#else
+#  define CONFIG_ENV_IS_IN_FLASH	1
+#  define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x40000)
+#define CONFIG_ENV_SIZE		0x1000
+#  define CONFIG_ENV_SECT_SIZE	0x40000
+#endif /* CONFIG_SYS_RAMBOOT */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPU */
+
+#if defined(CONFIG_CMD_KGDB)
+# define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * HIDx - Hardware Implementation-dependent Registers			 2-11
+ *-----------------------------------------------------------------------
+ * HID0 also contains cache control - initially enable both caches and
+ * invalidate contents, then the final state leaves only the instruction
+ * cache enabled. Note that Power-On and Hard reset invalidate the caches,
+ * but Soft reset does not.
+ *
+ * HID1 has only read-only information - nothing to set.
+ */
+#define CONFIG_SYS_HID0_INIT	(HID0_ICE  |\
+			 HID0_DCE  |\
+			 HID0_ICFI |\
+			 HID0_DCI  |\
+			 HID0_IFEM |\
+			 HID0_ABE)
+
+#define CONFIG_SYS_HID0_FINAL	(HID0_ICE  |\
+			 HID0_IFEM |\
+			 HID0_ABE  |\
+			 HID0_EMCP)
+#define CONFIG_SYS_HID2	0
+
+/*-----------------------------------------------------------------------
+ * RMR - Reset Mode Register
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RMR		0
+
+/*-----------------------------------------------------------------------
+ * BCR - Bus Configuration					 4-25
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_BCR		(BCR_EBM      |\
+			 0x30000000)
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				 4-31
+ * Ref Section 4.3.2.6	page 4-31
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_SYS_SIUMCR	(SIUMCR_ESE	 |\
+			 SIUMCR_DPPC00	 |\
+			 SIUMCR_L2CPC10	 |\
+			 SIUMCR_LBPC00	 |\
+			 SIUMCR_APPC10	 |\
+			 SIUMCR_CS10PC00 |\
+			 SIUMCR_BCTLC00	 |\
+			 SIUMCR_MMR00)
+
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
+ */
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC |\
+			 SYPCR_BMT  |\
+			 SYPCR_PBME |\
+			 SYPCR_LBME |\
+			 SYPCR_SWRI |\
+			 SYPCR_SWP)
+
+/*-----------------------------------------------------------------------
+ * TMCNTSC - Time Counter Status and Control			 4-40
+ *-----------------------------------------------------------------------
+ * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
+ * and enable Time Counter
+ */
+#define CONFIG_SYS_TMCNTSC	(TMCNTSC_SEC |\
+			 TMCNTSC_ALR |\
+			 TMCNTSC_TCF |\
+			 TMCNTSC_TCE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		 4-42
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
+ * Periodic timer
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS  |\
+			 PISCR_PTF |\
+			 PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control					 9-8
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_SCCR	0
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration				13-7
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RCCR	0
+
+/*
+ * Initialize Memory Controller:
+ *
+ * Bank Bus	Machine PortSz	Device
+ * ---- ---	------- ------	------
+ *  0	60x	GPCM	32 bit	FLASH (SIMM - 32MB) *
+ *  1	unused
+ *  2	60x	SDRAM	64 bit	SDRAM (DIMM - 128MB)
+ *  3	60x	SDRAM	64 bit	SDRAM (DIMM - 128MB)
+ *  4	Local	SDRAM	32 bit	SDRAM (on board - 16MB)
+ *  5	60x	GPCM	 8 bit	Mailbox/EEPROM (8KB)
+ *  6	60x	GPCM	 8 bit	FLASH  (on board - 2MB) *
+ *  7	60x	GPCM	 8 bit	LEDs, switches
+ *
+ *  (*) This configuration requires the PPMC8260 be configured
+ *	so that *CS0 goes to the FLASH SIMM, and *CS6 goes to
+ *	the on board FLASH. In other words, JP24 should have
+ *	pins 1 and 2 jumpered and pins 3 and 4 jumpered.
+ *
+ */
+
+/*-----------------------------------------------------------------------
+ * BR0,BR1 - Base Register
+ *     Ref: Section 10.3.1 on page 10-14
+ * OR0,OR1 - Option Register
+ *     Ref: Section 10.3.2 on page 10-18
+ *-----------------------------------------------------------------------
+ */
+
+/* Bank 0,1 - FLASH SIMM
+ *
+ * This expects the FLASH SIMM to be connected to *CS0
+ * It consists of 4 AM29F080B parts.
+ *
+ * Note: For the 4 MB SIMM, *CS1 is unused.
+ */
+
+/* BR0 is configured as follows:
+ *
+ *     - Base address of 0xFE000000
+ *     - 32 bit port size
+ *     - Data errors checking is disabled
+ *     - Read and write access
+ *     - GPCM 60x bus
+ *     - Access are handled by the memory controller according to MSEL
+ *     - Not used for atomic operations
+ *     - No data pipelining is done
+ *     - Valid
+ */
+#define CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\
+			 BRx_PS_32			|\
+			 BRx_MS_GPCM_P			|\
+			 BRx_V)
+
+/* OR0 is configured as follows:
+ *
+ *     - 32 MB
+ *     - *BCTL0 is asserted upon access to the current memory bank
+ *     - *CW / *WE are negated a quarter of a clock earlier
+ *     - *CS is output at the same time as the address lines
+ *     - Uses a clock cycle length of 5
+ *     - *PSDVAL is generated internally by the memory controller
+ *	 unless *GTA is asserted earlier externally.
+ *     - Relaxed timing is generated by the GPCM for accesses
+ *	 initiated to this memory region.
+ *     - One idle clock is inserted between a read access from the
+ *	 current bank and the next access.
+ */
+#define CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE)	|\
+			 ORxG_CSNT			|\
+			 ORxG_ACS_DIV1			|\
+			 ORxG_SCY_5_CLK			|\
+			 ORxG_TRLX			|\
+			 ORxG_EHTR)
+
+/*-----------------------------------------------------------------------
+ * BR2,BR3 - Base Register
+ *     Ref: Section 10.3.1 on page 10-14
+ * OR2,OR3 - Option Register
+ *     Ref: Section 10.3.2 on page 10-16
+ *-----------------------------------------------------------------------
+ */
+
+/*
+ * Bank 2,3 - 128 MB SDRAM DIMM
+ */
+
+/* With a 128 MB DIMM, the BR2 is configured as follows:
+ *
+ *     - Base address of 0x00000000/0x08000000
+ *     - 64 bit port size (60x bus only)
+ *     - Data errors checking is disabled
+ *     - Read and write access
+ *     - SDRAM 60x bus
+ *     - Access are handled by the memory controller according to MSEL
+ *     - Not used for atomic operations
+ *     - No data pipelining is done
+ *     - Valid
+ */
+#define CONFIG_SYS_BR2_PRELIM	((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
+			 BRx_PS_64			|\
+			 BRx_MS_SDRAM_P			|\
+			 BRx_V)
+
+#define CONFIG_SYS_BR3_PRELIM	((CONFIG_SYS_SDRAM1_BASE & BRx_BA_MSK) |\
+			 BRx_PS_64			|\
+			 BRx_MS_SDRAM_P			|\
+			 BRx_V)
+
+/* With a 128 MB DIMM, the OR2 is configured as follows:
+ *
+ *     - 128 MB
+ *     - 4 internal banks per device
+ *     - Row start address bit is A8 with PSDMR[PBI] = 0
+ *     - 13 row address lines
+ *     - Back-to-back page mode
+ *     - Internal bank interleaving within save device enabled
+ */
+
+#define CONFIG_SYS_OR2_PRELIM	(MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE)	|\
+			 ORxS_BPD_4			|\
+			 ORxS_ROWST_PBI0_A7		|\
+			 ORxS_NUMR_13)
+
+#define CONFIG_SYS_OR3_PRELIM	(MEG_TO_AM(CONFIG_SYS_SDRAM1_SIZE)	|\
+			 ORxS_BPD_4			|\
+			 ORxS_ROWST_PBI0_A7		|\
+			 ORxS_NUMR_13)
+
+
+/*-----------------------------------------------------------------------
+ * PSDMR - 60x Bus SDRAM Mode Register
+ *     Ref: Section 10.3.3 on page 10-21
+ *-----------------------------------------------------------------------
+ */
+
+/* With a 128 MB DIMM, the PSDMR is configured as follows:
+ *
+ *     - Page Based Interleaving,
+ *     - Refresh Enable,
+ *     - Normal Operation
+ *     - Address Multiplexing where A5 is output on A14 pin
+ *	 (A6 on A15, and so on),
+ *     - use address pins A13-A15 as bank select,
+ *     - A9 is output on SDA10 during an ACTIVATE command,
+ *     - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
+ *     - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
+ *	 is 3 clocks,
+ *     - earliest timing for READ/WRITE command after ACTIVATE command is
+ *	 2 clocks,
+ *     - earliest timing for PRECHARGE after last data was read is 1 clock,
+ *     - earliest timing for PRECHARGE after last data was written is 1 clock,
+ *     - External Address Multiplexing enabled
+ *     - CAS Latency is 2.
+ */
+#define CONFIG_SYS_PSDMR	(PSDMR_RFEN	      |\
+			 PSDMR_SDAM_A14_IS_A5 |\
+			 PSDMR_BSMA_A13_A15   |\
+			 PSDMR_SDA10_PBI0_A9  |\
+			 PSDMR_RFRC_7_CLK     |\
+			 PSDMR_PRETOACT_3W    |\
+			 PSDMR_ACTTORW_2W     |\
+			 PSDMR_LDOTOPRE_1C    |\
+			 PSDMR_WRC_1C	      |\
+			 PSDMR_EAMUX	      |\
+			 PSDMR_CL_2)
+
+
+#define CONFIG_SYS_PSRT	0x0e
+#define CONFIG_SYS_MPTPR	MPTPR_PTP_DIV32
+
+
+/*-----------------------------------------------------------------------
+ * BR4 - Base Register
+ *     Ref: Section 10.3.1 on page 10-14
+ * OR4 - Option Register
+ *     Ref: Section 10.3.2 on page 10-16
+ *-----------------------------------------------------------------------
+ */
+
+/*
+ * Bank 4 - On board SDRAM
+ *
+ */
+/* With 16 MB of onboard SDRAM	BR4 is configured as follows
+ *
+ *     - Base address 0x38000000
+ *     - 32 bit port size
+ *     - Data error checking disabled
+ *     - Read/Write access
+ *     - SDRAM local bus
+ *     - Not used for atomic operations
+ *     - No data pipelining is done
+ *     - Valid
+ *
+ */
+
+#define CONFIG_SYS_BR4_PRELIM	((CONFIG_SYS_SDRAM2_BASE & BRx_BA_MSK) |\
+			 BRx_PS_32			|\
+			 BRx_DECC_NONE			|\
+			 BRx_MS_SDRAM_L			|\
+			 BRx_V)
+
+/*
+ * With 16MB SDRAM, OR4 is configured as follows
+ *     - 4 internal banks per device
+ *     - Row start address bit is A10 with LSDMR[PBI] = 0
+ *     - 12 row address lines
+ *     - Back-to-back page mode
+ *     - Internal bank interleaving within save device enabled
+ */
+
+#define CONFIG_SYS_OR4_PRELIM	(MEG_TO_AM(CONFIG_SYS_SDRAM2_SIZE)	|\
+			 ORxS_BPD_4			|\
+			 ORxS_ROWST_PBI0_A10		|\
+			 ORxS_NUMR_12)
+
+
+/*-----------------------------------------------------------------------
+ * LSDMR - Local Bus SDRAM Mode Register
+ *     Ref: Section 10.3.4 on page 10-24
+ *-----------------------------------------------------------------------
+ */
+
+/* With a 16 MB onboard SDRAM, the LSDMR is configured as follows:
+ *
+ *     - Page Based Interleaving,
+ *     - Refresh Enable,
+ *     - Normal Operation
+ *     - Address Multiplexing where A5 is output on A13 pin
+ *	 (A6 on A15, and so on),
+ *     - use address pins A15-A17 as bank select,
+ *     - A11 is output on SDA10 during an ACTIVATE command,
+ *     - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
+ *     - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
+ *	 is 2 clocks,
+ *     - earliest timing for READ/WRITE command after ACTIVATE command is
+ *	 2 clocks,
+ *     - SDRAM burst length is 8
+ *     - earliest timing for PRECHARGE after last data was read is 1 clock,
+ *     - earliest timing for PRECHARGE after last data was written is 1 clock,
+ *     - External Address Multiplexing disabled
+ *     - CAS Latency is 2.
+ */
+#define CONFIG_SYS_LSDMR	(PSDMR_RFEN	      |\
+			 PSDMR_SDAM_A13_IS_A5 |\
+			 PSDMR_BSMA_A15_A17   |\
+			 PSDMR_SDA10_PBI0_A11 |\
+			 PSDMR_RFRC_7_CLK     |\
+			 PSDMR_PRETOACT_2W    |\
+			 PSDMR_ACTTORW_2W     |\
+			 PSDMR_BL	      |\
+			 PSDMR_LDOTOPRE_1C    |\
+			 PSDMR_WRC_1C	      |\
+			 PSDMR_CL_2)
+
+#define CONFIG_SYS_LSRT	0x0e
+
+/*-----------------------------------------------------------------------
+ * BR5 - Base Register
+ *     Ref: Section 10.3.1 on page 10-14
+ * OR5 - Option Register
+ *     Ref: Section 10.3.2 on page 10-16
+ *-----------------------------------------------------------------------
+ */
+
+/*
+ * Bank 5 EEProm and Mailbox
+ *
+ * The EEPROM and mailbox live on the same chip select.
+ * the eeprom is selected if the MSb of the address is set and the mailbox is
+ * selected if the MSb of the address is clear.
+ *
+ */
+
+/* BR5 is configured as follows:
+ *
+ *     - Base address of 0x32000000/0xF2000000
+ *     - 8 bit
+ *     - Data error checking disabled
+ *     - Read/Write access
+ *     - GPCM 60x Bus
+ *     - SDRAM local bus
+ *     - No data pipelining is done
+ *     - Valid
+ */
+
+#define CONFIG_SYS_BR5_PRELIM	((CONFIG_SYS_MAILBOX_BASE & BRx_BA_MSK) |\
+			 BRx_PS_8			 |\
+			 BRx_DECC_NONE			 |\
+			 BRx_MS_GPCM_P			 |\
+			 BRx_V)
+/* OR5 is configured as follows
+ *     - buffer control enabled
+ *     - chip select negated normally
+ *     - CS output 1/2 clock after address
+ *     - 15 wait states
+ *     - *PSDVAL is generated internally by the memory controller
+ *	 unless *GTA is asserted earlier externally.
+ *     - Relaxed timing is generated by the GPCM for accesses
+ *	 initiated to this memory region.
+ *     - One idle clock is inserted between a read access from the
+ *	 current bank and the next access.
+ */
+
+#define CONFIG_SYS_OR5_PRELIM ((P2SZ_TO_AM(CONFIG_SYS_MAILBOX_SIZE) & ~0x80000000) |\
+			 ORxG_ACS_DIV2				     |\
+			 ORxG_SCY_15_CLK			     |\
+			 ORxG_TRLX				     |\
+			 ORxG_EHTR)
+
+/*-----------------------------------------------------------------------
+ * BR6 - Base Register
+ *     Ref: Section 10.3.1 on page 10-14
+ * OR6 - Option Register
+ *     Ref: Section 10.3.2 on page 10-18
+ *-----------------------------------------------------------------------
+ */
+
+/* Bank 6 - I/O select
+ *
+ */
+
+/* BR6 is configured as follows:
+ *
+ *     - Base address of 0xE0000000
+ *     - 16 bit port size
+ *     - Data errors checking is disabled
+ *     - Read and write access
+ *     - GPCM 60x bus
+ *     - Access are handled by the memory controller according to MSEL
+ *     - Not used for atomic operations
+ *     - No data pipelining is done
+ *     - Valid
+ */
+#define CONFIG_SYS_BR6_PRELIM	((CONFIG_SYS_IOSELECT_BASE & BRx_BA_MSK) |\
+			   BRx_PS_16			  |\
+			   BRx_MS_GPCM_P		  |\
+			   BRx_V)
+
+/* OR6 is configured as follows
+ *     - buffer control enabled
+ *     - chip select negated normally
+ *     - CS output 1/2 clock after address
+ *     - 15 wait states
+ *     - *PSDVAL is generated internally by the memory controller
+ *	 unless *GTA is asserted earlier externally.
+ *     - Relaxed timing is generated by the GPCM for accesses
+ *	 initiated to this memory region.
+ *     - One idle clock is inserted between a read access from the
+ *	 current bank and the next access.
+ */
+
+#define CONFIG_SYS_OR6_PRELIM (MEG_TO_AM(CONFIG_SYS_IOSELECT_SIZE) |\
+			 ORxG_ACS_DIV2		     |\
+			 ORxG_SCY_15_CLK	     |\
+			 ORxG_TRLX		     |\
+			 ORxG_EHTR)
+
+
+/*-----------------------------------------------------------------------
+ * BR7 - Base Register
+ *     Ref: Section 10.3.1 on page 10-14
+ * OR7 - Option Register
+ *     Ref: Section 10.3.2 on page 10-18
+ *-----------------------------------------------------------------------
+ */
+
+/* Bank 7 - LEDs and switches
+ *
+ *  LEDs     are at 0x00001 (write only)
+ *  switches are at 0x00001 (read only)
+ */
+#ifdef CONFIG_SYS_LED_BASE
+
+/* BR7 is configured as follows:
+ *
+ *     - Base address of 0xA0000000
+ *     - 8 bit port size
+ *     - Data errors checking is disabled
+ *     - Read and write access
+ *     - GPCM 60x bus
+ *     - Access are handled by the memory controller according to MSEL
+ *     - Not used for atomic operations
+ *     - No data pipelining is done
+ *     - Valid
+ */
+#define CONFIG_SYS_BR7_PRELIM	((CONFIG_SYS_LED_BASE & BRx_BA_MSK)	 |\
+			   BRx_PS_8			 |\
+			   BRx_DECC_NONE		 |\
+			   BRx_MS_GPCM_P		 |\
+			   BRx_V)
+
+/* OR7 is configured as follows:
+ *
+ *     - 1 byte
+ *     - *BCTL0 is asserted upon access to the current memory bank
+ *     - *CW / *WE are negated a quarter of a clock earlier
+ *     - *CS is output at the same time as the address lines
+ *     - Uses a clock cycle length of 15
+ *     - *PSDVAL is generated internally by the memory controller
+ *	 unless *GTA is asserted earlier externally.
+ *     - Relaxed timing is generated by the GPCM for accesses
+ *	 initiated to this memory region.
+ *     - One idle clock is inserted between a read access from the
+ *	 current bank and the next access.
+ */
+#define CONFIG_SYS_OR7_PRELIM	(ORxG_AM_MSK		       |\
+			 ORxG_CSNT		       |\
+			 ORxG_ACS_DIV1		       |\
+			 ORxG_SCY_15_CLK	       |\
+			 ORxG_TRLX		       |\
+			 ORxG_EHTR)
+#endif /* CONFIG_SYS_LED_BASE */
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/pr1.h b/qemu/roms/u-boot/include/configs/pr1.h
new file mode 100644
index 000000000..e96ed4b4f
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/pr1.h
@@ -0,0 +1,157 @@
+/*
+ * U-boot - Configuration file for PR1 Appliance
+ *
+ * based on bf537-stamp.h
+ * Copyright (c) Switchfin Org. <dpn@switchfin.org>
+ */
+
+#ifndef __CONFIG_PR1_H__
+#define __CONFIG_PR1_H__
+
+#include <asm/config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU             bf537-0.3
+#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_SPI_MASTER
+
+
+/*
+ * Clock Settings
+ *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz					*/
+#define CONFIG_CLKIN_HZ			25000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
+/*                                                1 = CLKIN / 2		*/
+#define CONFIG_CLKIN_HALF		0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
+/*                                                1 = bypass PLL	*/
+#define CONFIG_PLL_BYPASS		0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
+/* Values can range from 0-63 (where 0 means 64)			*/
+#define CONFIG_VCO_MULT			24
+/* CCLK_DIV controls the core clock divider				*/
+/* Values can be 1, 2, 4, or 8 ONLY					*/
+#define CONFIG_CCLK_DIV			1
+/* SCLK_DIV controls the system clock divider				*/
+/* Values can range from 1-15						*/
+#define CONFIG_SCLK_DIV			5
+
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_ADD_WDTH	11
+#define CONFIG_MEM_SIZE		128
+
+#define CONFIG_EBIU_SDRRC_VAL	0x306
+#define CONFIG_EBIU_SDGCTL_VAL	0x8091998d
+
+#define CONFIG_EBIU_AMGCTL_VAL	0xFF
+#define CONFIG_EBIU_AMBCTL0_VAL	0x7BB07BB0
+#define CONFIG_EBIU_AMBCTL1_VAL	0xFFC27BB0
+
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(384 * 1024)
+
+
+/*
+ * Network Settings
+ */
+#ifndef __ADSPBF534__
+#define ADI_CMDS_NETWORK	1
+#define CONFIG_BFIN_MAC
+#define CONFIG_NETCONSOLE
+#endif
+#define CONFIG_HOSTNAME		pr1
+#define CONFIG_TFTP_BLOCKSIZE	4404
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR	02:80:ad:20:31:e8 */
+
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_SYS_NO_FLASH	/* We have no parallel FLASH */
+
+
+/*
+ * SPI Settings
+ */
+#define CONFIG_BFIN_SPI
+#define CONFIG_ENV_SPI_MAX_HZ	30000000
+#define CONFIG_SF_DEFAULT_SPEED	30000000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+
+
+/*
+ * Env Storage Settings
+ */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET	0x10000
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
+
+
+/*
+ * I2C Settings
+ */
+#define CONFIG_BFIN_TWI_I2C
+#define CONFIG_HARD_I2C
+
+
+/*
+ * NAND Settings
+ */
+#define CONFIG_NAND_PLAT
+#define CONFIG_SYS_NAND_BASE		0x20000000
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+
+#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
+#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
+#define BFIN_NAND_WRITE(addr, cmd) \
+	do { \
+		bfin_write8(addr, cmd); \
+		SSYNC(); \
+	} while (0)
+
+#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
+#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
+#define NAND_PLAT_GPIO_DEV_READY       GPIO_PF9
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_RTC_BFIN
+#define CONFIG_UART_CONSOLE	0
+#define CONFIG_SYS_PROMPT	"pr1>"
+#define CONFIG_BOOTCOMMAND	"run nandboot"
+#define CONFIG_BOOTDELAY	2
+#define CONFIG_LOADADDR		0x2000000
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+/*
+ * Overwrite some settings defined in bfin_adi_common.h
+ */
+#undef NAND_ENV_SETTINGS
+#define NAND_ENV_SETTINGS \
+	"nandargs=set bootargs " CONFIG_BOOTARGS "\0" \
+	"nandboot=" \
+		"nand read $(loadaddr) 0x0 0x900000;" \
+		"run nandargs;" \
+		"bootm" \
+		"\0"
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/pxa-common.h b/qemu/roms/u-boot/include/configs/pxa-common.h
new file mode 100644
index 000000000..f0ecc3458
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/pxa-common.h
@@ -0,0 +1,46 @@
+/*
+ * Toradex Colibri PXA270 configuration file
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef	__CONFIG_PXA_COMMON_H__
+#define	__CONFIG_PXA_COMMON_H__
+
+#define	CONFIG_DISPLAY_CPUINFO
+
+/*
+ * KGDB
+ */
+#ifdef	CONFIG_CMD_KGDB
+#define	CONFIG_KGDB_BAUDRATE		230400
+#endif
+
+/*
+ * MMC Card Configuration
+ */
+#ifdef	CONFIG_CMD_MMC
+#define	CONFIG_MMC
+#define	CONFIG_GENERIC_MMC
+#define	CONFIG_PXA_MMC_GENERIC
+#define	CONFIG_CMD_FAT
+#define	CONFIG_CMD_EXT2
+#define	CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * OHCI USB
+ */
+#ifdef	CONFIG_CMD_USB
+#define	CONFIG_USB_OHCI_NEW
+#define	CONFIG_SYS_USB_OHCI_CPU_INIT
+#define	CONFIG_SYS_USB_OHCI_BOARD_INIT
+#define	CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+#define	CONFIG_SYS_USB_OHCI_REGS_BASE		0x4c000000
+#define	CONFIG_SYS_USB_OHCI_SLOT_NAME		"pxa-ohci"
+#define	CONFIG_USB_STORAGE
+#endif
+
+#endif	/* __CONFIG_PXA_COMMON_H__ */
diff --git a/qemu/roms/u-boot/include/configs/pxa255_idp.h b/qemu/roms/u-boot/include/configs/pxa255_idp.h
new file mode 100644
index 000000000..af7c076df
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/pxa255_idp.h
@@ -0,0 +1,336 @@
+/*
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Copied from lubbock.h
+ *
+ * (C) Copyright 2004
+ * BEC Systems <http://bec-systems.com>
+ * Cliff Brake <cliff.brake@gmail.com>
+ * Configuation settings for the Accelent/Vibren PXA255 IDP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/pxa-regs.h>
+
+/*
+ * If we are developing, we might want to start U-Boot from RAM
+ * so we MUST NOT initialize critical regs like mem-timing ...
+ */
+#undef CONFIG_SKIP_LOWLEVEL_INIT			/* define for developing */
+#define	CONFIG_SYS_TEXT_BASE	0x0
+
+/*
+ * define the following to enable debug blinks.  A debug blink function
+ * must be defined in memsetup.S
+ */
+#undef DEBUG_BLINK_ENABLE
+#undef DEBUG_BLINKC_ENABLE
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_CPU_PXA25X		1	/* This is an PXA250 CPU    */
+
+#undef CONFIG_LCD
+#ifdef CONFIG_LCD
+#define CONFIG_PXA_LCD
+#define CONFIG_SHARP_LM8V31
+#endif
+
+#define CONFIG_MMC		1
+#define CONFIG_DOS_PARTITION	1
+#define CONFIG_BOARD_LATE_INIT
+
+/* we will never enable dcache, because we have to setup MMU first */
+#define CONFIG_SYS_DCACHE_OFF
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN	    (CONFIG_ENV_SIZE + 128*1024)
+
+/*
+ * PXA250 IDP memory map information
+ */
+
+#define IDP_CS5_ETH_OFFSET	0x03400000
+
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_SMC91111
+#define CONFIG_SMC91111_BASE	(PXA_CS5_PHYS + IDP_CS5_ETH_OFFSET + 0x300)
+#define CONFIG_SMC_USE_32_BIT	1
+/* #define CONFIG_SMC_USE_IOFUNCS */
+
+/* the following has to be set high -- suspect something is wrong with
+ * with the tftp timeout routines. FIXME!!!
+ */
+#define CONFIG_NET_RETRY_COUNT	100
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_PXA_SERIAL
+#define CONFIG_FFUART	       1       /* we use FFUART on LUBBOCK */
+#define CONFIG_CONS_INDEX	3
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE		115200
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_DHCP
+
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTCOMMAND	"bootm 40000"
+#define CONFIG_BOOTARGS		"root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+/* #define CONFIG_INITRD_TAG		1 */
+
+/*
+ * Current memory map for Vibren supplied Linux images:
+ *
+ * Flash:
+ * 0 - 0x3ffff (size = 0x40000): bootloader
+ * 0x40000 - 0x13ffff (size = 0x100000): kernel
+ * 0x140000 - 0x1f3ffff (size = 0x1e00000): jffs
+ *
+ * RAM:
+ * 0xa0008000 - kernel is loaded
+ * 0xa3000000 - Uboot runs (48MB into RAM)
+ *
+ */
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"prog_boot_mmc="						\
+			"mw.b 0xa0000000 0xff 0x40000; "		\
+			"if	 mmcinit && "				\
+				"fatload mmc 0 0xa0000000 u-boot.bin; "	\
+			"then "						\
+				"protect off 0x0 0x3ffff; "		\
+				"erase 0x0 0x3ffff; "			\
+				"cp.b 0xa0000000 0x0 0x40000; "		\
+				"reset;"				\
+			"fi\0"						\
+	"prog_uzImage_mmc="						\
+			"mw.b 0xa0000000 0xff 0x100000; "		\
+			"if	 mmcinit && "				\
+				"fatload mmc 0 0xa0000000 uzImage; "	\
+			"then "						\
+				"protect off 0x40000 0xfffff; "		\
+				"erase 0x40000 0xfffff; "		\
+				"cp.b 0xa0000000 0x40000 0x100000; "	\
+			"fi\0"						\
+	"prog_jffs_mmc="						\
+			"mw.b 0xa0000000 0xff 0x1e00000; "		\
+			"if	 mmcinit && "				\
+				"fatload mmc 0 0xa0000000 root.jffs; "	\
+			"then "						\
+				"protect off 0x140000 0x1f3ffff; "	\
+				"erase 0x140000 0x1f3ffff; "		\
+				"cp.b 0xa0000000 0x140000 0x1e00000; "	\
+			"fi\0"						\
+	"boot_mmc="							\
+			"if	 mmcinit && "				\
+				"fatload mmc 0 0xa1000000 uzImage && "	\
+			"then "						\
+				"bootm 0xa1000000; "			\
+			"fi\0"						\
+	"prog_boot_net="						\
+			"mw.b 0xa0000000 0xff 0x100000; "		\
+			"if	 bootp 0xa0000000 u-boot.bin; "		\
+			"then "						\
+				"protect off 0x0 0x3ffff; "		\
+				"erase 0x0 0x3ffff; "			\
+				"cp.b 0xa0000000 0x0 0x40000; "		\
+				"reset; "				\
+			"fi\0"						\
+	"prog_uzImage_net="						\
+			"mw.b 0xa0000000 0xff 0x100000; "		\
+			"if	 bootp 0xa0000000 uzImage; "		\
+			"then "						\
+				"protect off 0x40000 0xfffff; "		\
+				"erase 0x40000 0xfffff; "		\
+				"cp.b 0xa0000000 0x40000 0x100000; "	\
+			"fi\0"						\
+	"prog_jffs_net="						\
+			"mw.b 0xa0000000 0xff 0x1e00000; "		\
+			"if	 bootp 0xa0000000 root.jffs; "		\
+			"then "						\
+				"protect off 0x140000 0x1f3ffff; "	\
+				"erase 0x140000 0x1f3ffff; "		\
+				"cp.b 0xa0000000 0x140000 0x1e00000; "	\
+			"fi\0"
+
+
+/*	"erase_env="			*/
+/*			"protect off"	*/
+
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	115200		/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_HUSH_PARSER		1
+
+#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT		"$ "		/* Monitor Command Prompt */
+#else
+#endif
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_DEVICE_NULLDEV	1
+
+#define CONFIG_SYS_MEMTEST_START	0xa0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0xa0800000	/* default load address */
+
+#define CONFIG_SYS_CPUSPEED		0x161		/* set core clock to 400/200/100 MHz */
+
+#define RTC	1				/* enable 32KHz osc */
+
+#ifdef CONFIG_MMC
+#define	CONFIG_GENERIC_MMC
+#define	CONFIG_PXA_MMC_GENERIC
+#define CONFIG_CMD_MMC
+#define CONFIG_SYS_MMC_BASE		0xF0000000
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1		0xa0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x04000000 /* 64 MB */
+#define PHYS_SDRAM_2		0xa4000000 /* SDRAM Bank #2 */
+#define PHYS_SDRAM_2_SIZE	0x00000000 /* 0 MB */
+#define PHYS_SDRAM_3		0xa8000000 /* SDRAM Bank #3 */
+#define PHYS_SDRAM_3_SIZE	0x00000000 /* 0 MB */
+#define PHYS_SDRAM_4		0xac000000 /* SDRAM Bank #4 */
+#define PHYS_SDRAM_4_SIZE	0x00000000 /* 0 MB */
+
+#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
+#define PHYS_FLASH_2		0x04000000 /* Flash Bank #2 */
+#define PHYS_FLASH_SIZE		0x02000000 /* 32 MB */
+#define PHYS_FLASH_BANK_SIZE	0x02000000 /* 32 MB Banks */
+#define PHYS_FLASH_SECT_SIZE	0x00040000 /* 256 KB sectors (x2) */
+
+#define CONFIG_SYS_DRAM_BASE		0xa0000000
+#define CONFIG_SYS_DRAM_SIZE		0x04000000
+
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define	CONFIG_SYS_INIT_SP_ADDR		0xfffff800
+
+/*
+ * GPIO settings
+ */
+
+#define CONFIG_SYS_GAFR0_L_VAL	0x80001005
+#define CONFIG_SYS_GAFR0_U_VAL	0xa5128012
+#define CONFIG_SYS_GAFR1_L_VAL	0x699a9558
+#define CONFIG_SYS_GAFR1_U_VAL	0xaaa5aa6a
+#define CONFIG_SYS_GAFR2_L_VAL	0xaaaaaaaa
+#define CONFIG_SYS_GAFR2_U_VAL	0x2
+#define CONFIG_SYS_GPCR0_VAL	0x1800400
+#define CONFIG_SYS_GPCR1_VAL	0x0
+#define CONFIG_SYS_GPCR2_VAL	0x0
+#define CONFIG_SYS_GPDR0_VAL	0xc1818440
+#define CONFIG_SYS_GPDR1_VAL	0xfcffab82
+#define CONFIG_SYS_GPDR2_VAL	0x1ffff
+#define CONFIG_SYS_GPSR0_VAL	0x8000
+#define CONFIG_SYS_GPSR1_VAL	0x3f0002
+#define CONFIG_SYS_GPSR2_VAL	0x1c000
+
+#define CONFIG_SYS_PSSR_VAL		0x20
+
+#define	CONFIG_SYS_CCCR			CCCR_L27|CCCR_M2|CCCR_N10
+#define	CONFIG_SYS_CKEN			0x0
+
+/*
+ * Memory settings
+ */
+#define CONFIG_SYS_MSC0_VAL		0x29DCA4D2
+#define CONFIG_SYS_MSC1_VAL		0x43AC494C
+#define CONFIG_SYS_MSC2_VAL		0x39D449D4
+#define CONFIG_SYS_MDCNFG_VAL		0x090009C9
+#define CONFIG_SYS_MDREFR_VAL		0x0085C017
+#define CONFIG_SYS_MDMRS_VAL		0x00220022
+#define	CONFIG_SYS_FLYCNFG_VAL		0x00000000
+#define	CONFIG_SYS_SXCNFG_VAL		0x00000000
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define CONFIG_SYS_MECR_VAL		0x00000003
+#define CONFIG_SYS_MCMEM0_VAL		0x00014405
+#define CONFIG_SYS_MCMEM1_VAL		0x00014405
+#define CONFIG_SYS_MCATT0_VAL		0x00014405
+#define CONFIG_SYS_MCATT1_VAL		0x00014405
+#define CONFIG_SYS_MCIO0_VAL		0x00014405
+#define CONFIG_SYS_MCIO1_VAL		0x00014405
+
+/*
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER	1
+
+#define CONFIG_SYS_MONITOR_BASE	0
+#define CONFIG_SYS_MONITOR_LEN		PHYS_FLASH_SECT_SIZE
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	128  /* max number of sectors on one chip    */
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+
+/* timeout values are in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(25*CONFIG_SYS_HZ) /* Timeout for Flash Write */
+
+/* put cfg at end of flash for now */
+#define CONFIG_ENV_IS_IN_FLASH	1
+ /* Addr of Environment Sector	*/
+#define CONFIG_ENV_ADDR		(PHYS_FLASH_1 + PHYS_FLASH_SIZE - 0x40000)
+#define CONFIG_ENV_SIZE		PHYS_FLASH_SECT_SIZE	/* Total Size of Environment Sector	*/
+#define	CONFIG_ENV_SECT_SIZE	(PHYS_FLASH_SECT_SIZE / 16)
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/pxm2.h b/qemu/roms/u-boot/include/configs/pxm2.h
new file mode 100644
index 000000000..6276d4339
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/pxm2.h
@@ -0,0 +1,153 @@
+/*
+ * siemens pxm2
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * U-Boot file:/include/configs/am335x_evm.h
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_PXM2_H
+#define __CONFIG_PXM2_H
+
+#define CONFIG_SIEMENS_PXM2
+#define MACH_TYPE_PXM2			4309
+#define CONFIG_SIEMENS_MACH_TYPE	MACH_TYPE_PXM2
+
+#include "siemens-am33x-common.h"
+
+#define CONFIG_SYS_MPUCLK	720
+#define DXR2_IOCTRL_VAL		0x18b
+#define DDR_PLL_FREQ		266
+
+#define BOARD_DFU_BUTTON_GPIO	59
+#define BOARD_DFU_BUTTON_LED	117
+#define BOARD_LCD_POWER		111
+#define BOARD_BACK_LIGHT	112
+#define BOARD_TOUCH_POWER	57
+
+ /* Physical Memory Map */
+#define CONFIG_MAX_RAM_BANK_SIZE	(512 << 20)	/* 1GB */
+
+/* I2C Configuration */
+#define CONFIG_SYS_I2C_SPEED		400000
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+
+
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x300
+
+#undef CONFIG_SPL_NET_SUPPORT
+#undef CONFIG_SPL_NET_VCI_STRING
+#undef CONFIG_SPL_ETH_SUPPORT
+
+#define CONFIG_PHY_ATHEROS
+
+#define CONFIG_FACTORYSET
+
+/* UBI Support */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#endif
+
+/* Watchdog */
+#define CONFIG_OMAP_WATCHDOG
+
+#ifndef CONFIG_SPL_BUILD
+
+/* Default env settings */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"hostname=pxm2\0" \
+	"nand_img_size=0x500000\0" \
+	"optargs=\0" \
+	"splashpos=m,m\0"	\
+	CONFIG_COMMON_ENV_SETTINGS \
+	"mmc_dev=0\0" \
+	"mmc_root=/dev/mmcblk0p2 rw\0" \
+	"mmc_root_fs_type=ext4 rootwait\0" \
+	"mmc_load_uimage=" \
+		"mmc rescan; " \
+		"setenv bootfile uImage;" \
+		"fatload mmc ${mmc_dev} ${kloadaddr} ${bootfile}\0" \
+	"loadbootenv=fatload mmc ${mmc_dev} ${loadaddr} ${bootenv}\0" \
+	"importbootenv=echo Importing environment from mmc ...; " \
+		"env import -t $loadaddr $filesize\0" \
+	"mmc_args=run bootargs_defaults;" \
+		"mtdparts default;" \
+		"setenv bootargs ${bootargs} " \
+		"root=${mmc_root} ${mtdparts}" \
+		"rootfstype=${mmc_root_fs_type} ip=${ip_method} " \
+		"eth=${ethaddr} " \
+		"\0" \
+	"mmc_boot=run mmc_args; " \
+		"run mmc_load_uimage; " \
+		"bootm ${kloadaddr}\0" \
+	""
+
+#ifndef CONFIG_RESTORE_FLASH
+/* set to negative value for no autoboot */
+#define CONFIG_BOOTDELAY		3
+
+#define CONFIG_BOOTCOMMAND \
+	"if dfubutton; then " \
+		"run dfu_start; " \
+		"reset; " \
+	"fi; " \
+	"if mmc rescan; then " \
+		"echo SD/MMC found on device ${mmc_dev};" \
+		"if run loadbootenv; then " \
+			"echo Loaded environment from ${bootenv};" \
+			"run importbootenv;" \
+		"fi;" \
+		"if test -n $uenvcmd; then " \
+			"echo Running uenvcmd ...;" \
+			"run uenvcmd;" \
+		"fi;" \
+		"if run mmc_load_uimage; then " \
+			"run mmc_args;" \
+			"bootm ${kloadaddr};" \
+		"fi;" \
+	"fi;" \
+	"run nand_boot;" \
+	"reset;"
+
+#else
+#define CONFIG_BOOTDELAY		0
+
+#define CONFIG_BOOTCOMMAND			\
+	"setenv autoload no; "			\
+	"dhcp; "				\
+	"if tftp 80000000 debrick.scr; then "	\
+		"source 80000000; "		\
+	"fi"
+#endif
+#endif	/* CONFIG_SPL_BUILD */
+
+#define CONFIG_VIDEO
+#if defined(CONFIG_VIDEO)
+#define CONFIG_VIDEO_DA8XX
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_CMD_BMP
+#define DA8XX_LCD_CNTL_BASE	LCD_CNTL_BASE
+#define PWM_TICKS	0x1388
+#define PWM_DUTY	0x200
+#define CONFIG_SYS_CONSOLE_BG_COL	0xff
+#define CONFIG_SYS_CONSOLE_FG_COL	0x00
+#endif
+
+#endif	/* ! __CONFIG_PXM2_H */
diff --git a/qemu/roms/u-boot/include/configs/qemu-mips.h b/qemu/roms/u-boot/include/configs/qemu-mips.h
new file mode 100644
index 000000000..98ed8bc97
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/qemu-mips.h
@@ -0,0 +1,154 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * This file contains the configuration parameters for qemu-mips target.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_QEMU_MIPS
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_BOOTDELAY	10	/* autoboot after 10 seconds */
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_TIMESTAMP		/* Print image info with timestamp */
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"addmisc=setenv bootargs ${bootargs} "				\
+		"console=ttyS0,${baudrate} "				\
+		"panic=1\0"						\
+	"bootfile=/tftpboot/vmlinux\0"				\
+	"load=tftp 80500000 ${u-boot}\0"				\
+	""
+
+#define CONFIG_BOOTCOMMAND	"bootp;bootelf"
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+#define CONFIG_CMD_DHCP
+
+#define CONFIG_DRIVER_NE2000
+#define CONFIG_DRIVER_NE2000_BASE	0xb4000300
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		115200
+#define CONFIG_SYS_NS16550_COM1		0xb40003f8
+#define CONFIG_CONS_INDEX		1
+
+#define CONFIG_CMD_IDE
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_SYS_IDE_MAXBUS		2
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x1f0
+#define CONFIG_SYS_ATA_IDE1_OFFSET	0x170
+#define CONFIG_SYS_ATA_DATA_OFFSET	0
+#define CONFIG_SYS_ATA_REG_OFFSET	0
+#define CONFIG_SYS_ATA_BASE_ADDR	0xb4000000
+
+#define CONFIG_SYS_IDE_MAXDEVICE	4
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+
+/* Monitor Command Prompt */
+#if defined(CONFIG_SYS_LITTLE_ENDIAN)
+#define CONFIG_SYS_PROMPT		"qemu-mipsel # "
+#else
+#define CONFIG_SYS_PROMPT		"qemu-mips # "
+#endif
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_HUSH_PARSER
+
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		256
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS		16
+
+#define CONFIG_SYS_MALLOC_LEN		128*1024
+
+#define CONFIG_SYS_BOOTPARAMS_LEN	128*1024
+
+#define CONFIG_SYS_MHZ			132
+
+#define CONFIG_SYS_MIPS_TIMER_FREQ	(CONFIG_SYS_MHZ * 1000000)
+
+/* Cached addr */
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+
+/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0x81000000
+
+#define CONFIG_SYS_MEMTEST_START	0x80100000
+#define CONFIG_SYS_MEMTEST_END		0x80800000
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+/* The following #defines are needed to get flash environment right */
+#define CONFIG_SYS_TEXT_BASE		0xbfc00000 /* Rom version */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(192 << 10)
+
+#define CONFIG_SYS_INIT_SP_OFFSET	0x400000
+
+/* We boot from this flash, selected with dip switch */
+#define CONFIG_SYS_FLASH_BASE		0xbfc00000
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	128
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
+
+/* Address and size of Primary Environment Sector */
+#define CONFIG_ENV_SIZE		0x8000
+
+#define CONFIG_ENV_OVERWRITE	1
+
+#define MEM_SIZE		128
+
+#define CONFIG_LZMA
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_DCACHE_SIZE		16384
+#define CONFIG_SYS_ICACHE_SIZE		16384
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/qemu-mips64.h b/qemu/roms/u-boot/include/configs/qemu-mips64.h
new file mode 100644
index 000000000..e8f5a4c9e
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/qemu-mips64.h
@@ -0,0 +1,156 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * This file contains the configuration parameters for qemu-mips64 target.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_QEMU_MIPS
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_BOOTDELAY	10	/* autoboot after 10 seconds */
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_TIMESTAMP		/* Print image info with timestamp */
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"addmisc=setenv bootargs ${bootargs} "				\
+		"console=ttyS0,${baudrate} "				\
+		"panic=1\0"						\
+	"bootfile=/tftpboot/vmlinux\0"					\
+	"load=tftp ffffffff80500000 ${u-boot}\0"			\
+	""
+
+#define CONFIG_BOOTCOMMAND	"bootp;bootelf"
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+#define CONFIG_CMD_DHCP
+
+#define CONFIG_DRIVER_NE2000
+#define CONFIG_DRIVER_NE2000_BASE	0xffffffffb4000300
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		115200
+#define CONFIG_SYS_NS16550_COM1		0xffffffffb40003f8
+#define CONFIG_CONS_INDEX		1
+
+#define CONFIG_CMD_IDE
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_SYS_IDE_MAXBUS		2
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x1f0
+#define CONFIG_SYS_ATA_IDE1_OFFSET	0x170
+#define CONFIG_SYS_ATA_DATA_OFFSET	0
+#define CONFIG_SYS_ATA_REG_OFFSET	0
+#define CONFIG_SYS_ATA_BASE_ADDR	0xffffffffb4000000
+
+#define CONFIG_SYS_IDE_MAXDEVICE	4
+
+#define CONFIG_CMD_RARP
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+
+/* Monitor Command Prompt */
+#if defined(CONFIG_SYS_LITTLE_ENDIAN)
+#define CONFIG_SYS_PROMPT		"qemu-mips64el # "
+#else
+#define CONFIG_SYS_PROMPT		"qemu-mips64 # "
+#endif
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_HUSH_PARSER
+
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		256
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS		16
+
+#define CONFIG_SYS_MALLOC_LEN		128*1024
+
+#define CONFIG_SYS_BOOTPARAMS_LEN	128*1024
+
+#define CONFIG_SYS_MHZ			132
+
+#define CONFIG_SYS_MIPS_TIMER_FREQ	(CONFIG_SYS_MHZ * 1000000)
+
+/* Cached addr */
+#define CONFIG_SYS_SDRAM_BASE		0xffffffff80000000
+
+/* default load address */
+#define CONFIG_SYS_LOAD_ADDR		0xffffffff81000000
+
+#define CONFIG_SYS_MEMTEST_START	0xffffffff80100000
+#define CONFIG_SYS_MEMTEST_END		0xffffffff80800000
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+/* The following #defines are needed to get flash environment right */
+#define CONFIG_SYS_TEXT_BASE		0xffffffffbfc00000 /* Rom version */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(192 << 10)
+
+#define CONFIG_SYS_INIT_SP_OFFSET	0x400000
+
+/* We boot from this flash, selected with dip switch */
+#define CONFIG_SYS_FLASH_BASE		0xffffffffbfc00000
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	128
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
+
+/* Address and size of Primary Environment Sector */
+#define CONFIG_ENV_SIZE		0x8000
+
+#define CONFIG_ENV_OVERWRITE	1
+
+#define MEM_SIZE		128
+
+#define CONFIG_LZMA
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_DCACHE_SIZE		16384
+#define CONFIG_SYS_ICACHE_SIZE		16384
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/qemu-ppce500.h b/qemu/roms/u-boot/include/configs/qemu-ppce500.h
new file mode 100644
index 000000000..763a47ac3
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/qemu-ppce500.h
@@ -0,0 +1,207 @@
+/*
+ * Copyright 2011-2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Corenet DS style board configuration file
+ */
+#ifndef __QEMU_PPCE500_H
+#define __QEMU_PPCE500_H
+
+#define CONFIG_CMD_REGINFO
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE
+#define CONFIG_E500			/* BOOKE e500 family */
+#define CONFIG_QEMU_E500
+
+#undef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xf01000 /* 15 MB */
+#define CONFIG_SYS_GENERIC_BOARD
+
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+
+#define CONFIG_SYS_RAMBOOT
+
+#define CONFIG_PCI			/* Enable PCI/PCIE */
+#define CONFIG_PCI1		1	/* PCI controller 1 */
+#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_PANIC_HANG	/* do not reset board on panic */
+
+/* Needed to fill the ccsrbar pointer */
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* Virtual address to CCSRBAR */
+#define CONFIG_SYS_CCSRBAR		0xe0000000
+/* Physical address should be a function call */
+#ifndef __ASSEMBLY__
+extern unsigned long long get_phys_ccsrbar_addr_early(void);
+#endif
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+
+/* Virtual address range for PCI region maps */
+#define CONFIG_SYS_PCI_MAP_START	0x80000000
+#define CONFIG_SYS_PCI_MAP_END		0xe8000000
+
+/* Virtual address to a temporary map if we need it (max 128MB) */
+#define CONFIG_SYS_TMPVIRT		0xe8000000
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_CHIP_SELECTS_PER_CTRL	0
+
+#define CONFIG_SYS_CLK_FREQ        33000000
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_SYS_BOOT_BLOCK		0x00000000	/* boot TLB */
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_ENV_IS_NOWHERE
+
+#define CONFIG_HWCONFIG
+
+#define CONFIG_SYS_INIT_RAM_ADDR		0x00100000
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0x0
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0x00100000
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0))
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+#define CONFIG_E1000
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif	/* CONFIG_PCI */
+
+#define CONFIG_LBA48
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_SIZE		0x2000
+
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+
+#define CONFIG_LAST_STAGE_INIT
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	"u-boot.bin"	/* U-Boot image on TFTP server*/
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+#define CONFIG_BAUDRATE	115200
+
+#define CONFIG_BOOTDELAY        1
+#define CONFIG_BOOTCOMMAND		\
+	"test -n \"$qemu_kernel_addr\" && bootm $qemu_kernel_addr - $fdt_addr_r\0"
+
+#endif	/* __QEMU_PPCE500_H */
diff --git a/qemu/roms/u-boot/include/configs/qong.h b/qemu/roms/u-boot/include/configs/qong.h
new file mode 100644
index 000000000..f9d6642cc
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/qong.h
@@ -0,0 +1,289 @@
+/*
+ * Copyright (C) 2009, Ilya Yanok, Emcraft Systems, <yanok@emcraft.com>
+ *
+ * Configuration settings for the Dave/DENX QongEVB-LITE board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+
+/* High Level Configuration Options */
+#define CONFIG_ARM1136			/* This is an arm1136 CPU core */
+#define CONFIG_MX31			/* in a mx31 */
+#define CONFIG_QONG
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_SYS_TEXT_BASE 0xa0000000
+
+#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 1536 * 1024)
+
+/*
+ * Hardware drivers
+ */
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	UART1_BASE
+
+#define CONFIG_MXC_GPIO
+#define CONFIG_HW_WATCHDOG
+#define CONFIG_IMX_WATCHDOG
+
+#define CONFIG_MXC_SPI
+#define CONFIG_DEFAULT_SPI_BUS	1
+#define CONFIG_DEFAULT_SPI_MODE	(SPI_MODE_0 | SPI_CS_HIGH)
+#define CONFIG_RTC_MC13XXX
+
+#define CONFIG_POWER
+#define CONFIG_POWER_SPI
+#define CONFIG_POWER_FSL
+#define CONFIG_FSL_PMIC_BUS	1
+#define CONFIG_FSL_PMIC_CS	0
+#define CONFIG_FSL_PMIC_CLK	100000
+#define CONFIG_FSL_PMIC_MODE	(SPI_MODE_0 | SPI_CS_HIGH)
+#define CONFIG_FSL_PMIC_BITLEN	32
+
+/* FPGA */
+#define CONFIG_FPGA
+#define CONFIG_QONG_FPGA
+#define CONFIG_FPGA_BASE	(CS1_BASE)
+#define CONFIG_FPGA_LATTICE
+#define CONFIG_FPGA_COUNT	1
+
+#ifdef CONFIG_QONG_FPGA
+/* Ethernet */
+#define CONFIG_DNET
+#define CONFIG_DNET_BASE	(CS1_BASE + QONG_FPGA_PERIPH_SIZE)
+
+/* Framebuffer and LCD */
+#define CONFIG_VIDEO
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_MX3
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_CMD_BMP
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(512 << 10)
+
+/* USB */
+#define CONFIG_CMD_USB
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI			/* Enable EHCI USB support */
+#define CONFIG_USB_EHCI_MXC
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORT	2
+#define CONFIG_MXC_USB_PORTSC	(MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT)
+#define CONFIG_MXC_USB_FLAGS	MXC_EHCI_POWER_PINS_ENABLED
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_STORAGE
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SUPPORT_VFAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#endif /* CONFIG_CMD_USB */
+
+/*
+ * Reducing the ARP timeout from default 5 seconds to 200ms we speed up the
+ * initial TFTP transfer, should the user wish one, significantly.
+ */
+#define CONFIG_ARP_TIMEOUT	200UL
+
+#endif /* CONFIG_QONG_FPGA */
+
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		115200
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_UNZIP
+
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_BOOTDELAY	5
+
+#define CONFIG_LOADADDR		0x80800000	/* loadaddr env var */
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs}"				\
+		" console=ttymxc0,${baudrate}\0"			\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
+	"addmisc=setenv bootargs ${bootargs}\0"				\
+	"uboot_addr=A0000000\0"						\
+	"kernel_addr=A00C0000\0"					\
+	"ramdisk_addr=A0300000\0"					\
+	"u-boot=qong/u-boot.bin\0"					\
+	"kernel_addr_r=80800000\0"					\
+	"hostname=qong\0"						\
+	"bootfile=qong/uImage\0"					\
+	"rootpath=/opt/eldk-4.2-arm/armVFP\0"				\
+	"flash_self=run ramargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"flash_nfs=run nfsargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr}\0"				\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
+		"run nfsargs addip addtty addmtd addmisc;"		\
+		"bootm\0"						\
+	"bootcmd=run flash_self\0"					\
+	"load=tftp ${loadaddr} ${u-boot}\0"				\
+	"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)	\
+		" +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
+		" +${filesize};cp.b ${fileaddr} "			\
+		__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"	\
+	"upd=run load update\0"						\
+	"videomode=video=ctfb:x:640,y:480,depth:16,mode:0,pclk:40000,"	\
+		"le:120,ri:40,up:35,lo:10,hs:30,vs:3,sync:100663296,"	\
+		"vmode:0\0"						\
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+		sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		32	/* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+/* memtest works on first 255MB of RAM */
+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
+#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_1 + 0xff000000)
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_HUSH_PARSER			/* Use the HUSH parser */
+
+#define CONFIG_MISC_INIT_R
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM_1		CSD0_BASE
+#define PHYS_SDRAM_1_SIZE	0x10000000	/* 256 MB */
+
+/*
+ * NAND driver
+ */
+
+#ifndef __ASSEMBLY__
+extern void qong_nand_plat_init(void *chip);
+extern int qong_nand_rdy(void *chip);
+#endif
+#define CONFIG_NAND_PLAT
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#define CONFIG_SYS_NAND_BASE	CS3_BASE
+#define NAND_PLAT_INIT() qong_nand_plat_init(nand)
+
+#define QONG_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 24))
+#define QONG_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 23))
+#define QONG_NAND_WRITE(addr, cmd) \
+	do { \
+		__REG8(addr) = cmd; \
+	} while (0)
+
+#define NAND_PLAT_WRITE_CMD(chip, cmd) QONG_NAND_WRITE(QONG_NAND_CLE(chip), cmd)
+#define NAND_PLAT_WRITE_ADR(chip, cmd) QONG_NAND_WRITE(QONG_NAND_ALE(chip), cmd)
+#define NAND_PLAT_DEV_READY(chip)      (qong_nand_rdy(chip))
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_FLASH_BASE		CS0_BASE
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
+/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024
+/* Monitor at beginning of flash */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		0x40000		/* Reserve 256KiB */
+
+#define	CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	0x20000
+#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x80000)
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+/* Flash memory is CFI compliant */
+#define CONFIG_SYS_FLASH_CFI
+/* Use drivers/cfi_flash.c */
+#define CONFIG_FLASH_CFI_DRIVER
+/* Use buffered writes (~10x faster) */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+/* Use hardware sector protection */
+#define CONFIG_SYS_FLASH_PROTECTION
+
+/*
+ * Filesystem
+ */
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_LZO
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
+#define MTDIDS_DEFAULT		"nor0=physmap-flash.0,"		\
+				"nand0=gen_nand"
+#define MTDPARTS_DEFAULT	\
+	"mtdparts=physmap-flash.0:"				\
+			"512k(U-Boot),128k(env1),128k(env2),"	\
+			"2304k(kernel),13m(ramdisk),-(user);"	\
+		"gen_nand:"					\
+			"128m(nand)"
+
+/* additions for new relocation code, must be added to all boards */
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE		IRAM_SIZE
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/quad100hd.h b/qemu/roms/u-boot/include/configs/quad100hd.h
new file mode 100644
index 000000000..e91e805bb
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/quad100hd.h
@@ -0,0 +1,281 @@
+/*
+ * (C) Copyright 2008
+ * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/************************************************************************
+ * quad100hd.h - configuration for Quad100hd board
+ ***********************************************************************/
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_QUAD100HD	1		/* Board is Quad100hd	*/
+#define CONFIG_405EP		1		/* Specifc 405EP support*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
+
+#define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_early_init_f */
+
+#define PLLMR0_DEFAULT		PLLMR0_266_133_66 /* no PCI */
+#define PLLMR1_DEFAULT		PLLMR1_266_133_66 /* no PCI */
+
+/* the environment is in the EEPROM by default */
+#define CONFIG_ENV_IS_IN_EEPROM
+#undef CONFIG_ENV_IS_IN_FLASH
+
+#define CONFIG_PPC4xx_EMAC
+#define CONFIG_HAS_ETH1		1
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0x01	/* PHY address			*/
+#define CONFIG_SYS_RX_ETH_BUFFER	16	/* Number of ethernet rx buffers & descriptors */
+#define CONFIG_PHY_RESET	1
+#define CONFIG_PHY_RESET_DELAY	300	/* PHY RESET recovery delay	*/
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_ASKENV
+#undef CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#undef CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#undef CONFIG_CMD_IRQ
+#define CONFIG_CMD_JFFS2
+#undef CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#undef CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/*-----------------------------------------------------------------------
+ * SDRAM
+ *----------------------------------------------------------------------*/
+/*
+ * SDRAM configuration (please see cpu/ppc/sdram.[ch])
+ */
+#define CONFIG_SDRAM_BANK0  1
+
+/* FIX! SDRAM timings used in datasheet */
+#define CONFIG_SYS_SDRAM_CL            3       /* CAS latency */
+#define CONFIG_SYS_SDRAM_tRP           20      /* PRECHARGE command period */
+#define CONFIG_SYS_SDRAM_tRC           66      /* ACTIVE-to-ACTIVE command period */
+#define CONFIG_SYS_SDRAM_tRCD          20      /* ACTIVE-to-READ delay */
+#define CONFIG_SYS_SDRAM_tRFC          66      /* Auto refresh period */
+
+/*
+ * JFFS2
+ */
+#define CONFIG_SYS_JFFS2_FIRST_BANK    0
+#ifdef  CONFIG_SYS_KERNEL_IN_JFFS2
+#define CONFIG_SYS_JFFS2_FIRST_SECTOR  0   /* JFFS starts at block 0 */
+#else /* kernel not in JFFS */
+#define CONFIG_SYS_JFFS2_FIRST_SECTOR  8   /* block 0-7 is kernel (1MB = 8 sectors) */
+#endif
+#define CONFIG_SYS_JFFS2_NUM_BANKS     1
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK			/* external serial clock */
+#define CONFIG_SYS_BASE_BAUD		691200
+#define CONFIG_BAUDRATE		115200
+
+/* The following table includes the supported baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	        1024	/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	        256	/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	        16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	        CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000 /* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000  /* default load address	*/
+#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_info (bd_t) */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_LOOPW            1       /* enable loopw command         */
+#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50		/* base address */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2		/* bytes of address */
+
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* 8 byte write page size */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+#define CONFIG_SYS_EEPROM_SIZE			0x2000
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFC00000
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_TEXT_BASE)
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible	*/
+#define	CONFIG_FLASH_CFI_DRIVER
+
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max number of sectors on one chip */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster) */
+#define CONFIG_SYS_FLASH_INCREMENT      0       /* there is only one bank         */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash */
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	0x10000	/* size of one complete sector	*/
+/* the environment is located before u-boot */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_TEXT_BASE - CONFIG_ENV_SECT_SIZE)
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_EEPROM
+#define CONFIG_ENV_SIZE		0x400		/* Size of Environment vars */
+#define CONFIG_ENV_OFFSET		0x00000000
+#define CONFIG_SYS_ENABLE_CRC_16	1       /* Intrinsyc formatting used crc16 */
+#endif
+
+/* partly from PPCBoot */
+/* NAND */
+#define CONFIG_NAND
+#ifdef CONFIG_NAND
+#define CONFIG_SYS_NAND_BASE   0x60000000
+#define CONFIG_SYS_NAND_CS	10   /* our CS is GPIO10 */
+#define CONFIG_SYS_NAND_RDY	23   /* our RDY is GPIO23 */
+#define CONFIG_SYS_NAND_CE	24   /* our CE is GPIO24  */
+#define CONFIG_SYS_NAND_CLE	31   /* our CLE is GPIO31 */
+#define CONFIG_SYS_NAND_ALE	30   /* our ALE is GPIO30 */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+
+#endif
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory (OCM) for temperary stack until sdram is tested */
+/* see ./arch/powerpc/cpu/ppc4xx/start.S */
+#define CONFIG_SYS_TEMP_STACK_OCM	1
+
+/* On Chip Memory location */
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of OCM		*/
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ * Taken from PPCBoot board/icecube/icecube.h
+ */
+
+/* see ./arch/powerpc/cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/ndfc.c */
+#define CONFIG_SYS_EBC_PB0AP		0x04002480
+/* AMD NOR flash - this corresponds to FLASH_BASE so may be correct */
+#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000
+#define CONFIG_SYS_EBC_PB1AP           0x04005480
+#define CONFIG_SYS_EBC_PB1CR           0x60018000
+#define CONFIG_SYS_EBC_PB2AP           0x00000000
+#define CONFIG_SYS_EBC_PB2CR           0x00000000
+#define CONFIG_SYS_EBC_PB3AP           0x00000000
+#define CONFIG_SYS_EBC_PB3CR           0x00000000
+#define CONFIG_SYS_EBC_PB4AP           0x00000000
+#define CONFIG_SYS_EBC_PB4CR           0x00000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO setup (PPC405EP specific)
+ *
+ * Taken in part from PPCBoot board/icecube/icecube.h
+ */
+/* see ./arch/powerpc/cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/start.S */
+#define CONFIG_SYS_GPIO0_OSRL		0x55555550
+#define CONFIG_SYS_GPIO0_OSRH		0x00000110
+#define CONFIG_SYS_GPIO0_ISR1L		0x00000000
+#define CONFIG_SYS_GPIO0_ISR1H		0x15555445
+#define CONFIG_SYS_GPIO0_TSRL		0x00000000
+#define CONFIG_SYS_GPIO0_TSRH		0x00000000
+#define CONFIG_SYS_GPIO0_TCR		0xFFFF8097
+#define CONFIG_SYS_GPIO0_ODR		0x00000000
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
+#endif
+
+/* ENVIRONMENT VARS */
+
+#define CONFIG_IPADDR		192.168.1.67
+#define CONFIG_SERVERIP		192.168.1.50
+#define CONFIG_GATEWAYIP	192.168.1.1
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_LOADADDR		300000
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/quantum.h b/qemu/roms/u-boot/include/configs/quantum.h
new file mode 100644
index 000000000..f3540c142
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/quantum.h
@@ -0,0 +1,430 @@
+/*
+ * (C) Copyright 2003-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ * changes for 16M board
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#undef CONFIG_MPC860
+#define CONFIG_MPC850		1	/* This is a MPC850 CPU		*/
+#define CONFIG_RPXLITE		1	/* QUANTUM is the RPXlite clone */
+#define CONFIG_RMU		1   /* The QUNATUM is based on our RMU */
+
+#define	CONFIG_SYS_TEXT_BASE	0xfff00000
+
+#define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		9600	/* console baudrate = 9600bps	*/
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+/* default developmenmt environment */
+
+#define CONFIG_ETHADDR 00:0B:17:00:00:00
+
+#define CONFIG_IPADDR  10.10.69.10
+#define CONFIG_SERVERIP 10.10.69.49
+#define CONFIG_NETMASK	255.255.255.0
+#define CONFIG_HOSTNAME QUANTUM
+#define CONFIG_ROOTPATH "/opt/eldk/pcc_8xx"
+
+#define CONFIG_BOOTARGS	 "root=/dev/ram rw"
+
+#define CONFIG_BOOTCOMMAND "bootm ff000000"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+    "serial#=12345\0"		\
+	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0"	\
+	"ramargs=setenv bootargs root=/dev/ram rw\0" \
+    "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0"
+
+/*
+ * Select the more full-featured memory test (Barr embedded systems)
+ */
+#define CONFIG_SYS_ALT_MEMTEST
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+
+/* M48T02 Paralled access timekeeper with same interface as the M48T35A*/
+#define CONFIG_RTC_M48T35A 1
+
+#if 0
+#define CONFIG_WATCHDOG 1		/* watchdog enabled		*/
+#else
+#undef CONFIG_WATCHDOG
+#endif
+
+/*  NVRAM and RTC */
+#define CONFIG_SYS_NVRAM_BASE_ADDR 0xFA000000
+#define CONFIG_SYS_NVRAM_SIZE 2048
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SNTP
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+#define CONFIG_AUTOBOOT_KEYED	/* Enable password protection */
+#define CONFIG_AUTOBOOT_PROMPT		\
+	"\nEnter password - autoboot in %d sec...\n", bootdelay
+#define CONFIG_AUTOBOOT_DELAY_STR	"system"
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x00040000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x01f00000	/* 256K ... 15 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xFA200000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE	0xFF000000
+
+#if 1
+    #define CONFIG_FLASH_CFI_DRIVER
+#else
+    #undef CONFIG_FLASH_CFI_DRIVER
+#endif
+
+
+#ifdef CONFIG_FLASH_CFI_DRIVER
+    #define CONFIG_SYS_FLASH_CFI 1
+    #undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+    #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
+#endif
+
+/*%%% #define CONFIG_SYS_FLASH_BASE		0xFFF00000 */
+#if defined(DEBUG) || defined(CONFIG_CMD_IDE)
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#else
+#define CONFIG_SYS_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
+#endif
+#define CONFIG_SYS_MONITOR_BASE	0xFFF00000
+/*%%% #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_OFFSET	    0x00040000	/*   Offset   of Environment Sector	absolute address 0xfff40000*/
+#define CONFIG_ENV_SECT_SIZE	0x40000	/* Total Size of Environment Sector	*/
+#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+/* FPGA */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_SYS_FPGA_SPARTAN2
+#define CONFIG_SYS_FPGA_PROG_FEEDBACK
+
+
+/*-----------------------------------------------------------------------
+ * Reset address
+ */
+#define CONFIG_SYS_RESET_ADDRESS	((ulong)((((immap_t *)CONFIG_SYS_IMMR)->im_clkrst.res)))
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_MLRC10)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+/*%%%#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ *
+ * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
+ */
+/* up to 50 MHz we use a 1:1 clock */
+#define CONFIG_SYS_PLPRCR	( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF00
+/* up to 50 MHz we use a 1:1 clock */
+#define CONFIG_SYS_SCCR	(SCCR_COM00 | SCCR_TBS)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_IDE_PREINIT	1	/* Use preinit IDE hook */
+#define CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card Adapter */
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
+#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+/*#define	CONFIG_SYS_DER 0x2002000F*/
+#define CONFIG_SYS_DER 0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0 and OR0 (FLASH)
+ */
+
+#define FLASH_BASE_PRELIM	0xFE000000	/* FLASH base */
+#define CONFIG_SYS_PRELIM_OR_AM	0xFE000000	/* OR addr mask */
+
+/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
+#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
+
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
+
+/*
+ * BR1 and OR1 (SDRAM)
+ *
+ */
+#define SDRAM_BASE_PRELIM	0x00000000	/* SDRAM base	*/
+#define SDRAM_MAX_SIZE		0x08000000	/* max 128 MB */
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000E00
+
+#define CONFIG_SYS_OR1_PRELIM	(0xF0000000 | CONFIG_SYS_OR_TIMING_SDRAM ) /* map 256 MB */
+#define CONFIG_SYS_BR1_PRELIM	((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+/* RPXLITE mem setting */
+#define CONFIG_SYS_BR3_PRELIM	0xFA400001		/* FPGA */
+#define CONFIG_SYS_OR3_PRELIM	0xFFFF8910
+
+#define CONFIG_SYS_BR4_PRELIM	0xFA000401		/* NVRAM&SRAM */
+#define CONFIG_SYS_OR4_PRELIM	0xFFFE0970
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CONFIG_SYS_MAMR_PTA	20
+
+/*
+ * Refresh clock Prescalar
+ */
+#define CONFIG_SYS_MPTPR	MPTPR_PTP_DIV2
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 9 column SDRAM */
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_16X | MAMR_WLFA_16X | MAMR_TLFA_16X)
+
+/*
+ * BCSRx
+ *
+ * Board Status and Control Registers
+ *
+ */
+
+#define BCSR0 0xFA400000
+#define BCSR1 0xFA400001
+#define BCSR2 0xFA400002
+#define BCSR3 0xFA400003
+
+#define BCSR0_ENMONXCVR 0x01	/* Monitor XVCR Control */
+#define BCSR0_ENNVRAM	0x02	/* CS4# Control */
+#define BCSR0_LED5	0x04	/* LED5 control 0='on' 1='off' */
+#define BCSR0_LED4	0x08	/* LED4 control 0='on' 1='off' */
+#define BCSR0_FULLDPLX	0x10	/* Ethernet XCVR Control */
+#define BCSR0_COLTEST	0x20
+#define BCSR0_ETHLPBK	0x40
+#define BCSR0_ETHEN	0x80
+
+#define BCSR1_PCVCTL7	0x01	/* PC Slot B Control */
+#define BCSR1_PCVCTL6	0x02
+#define BCSR1_PCVCTL5	0x04
+#define BCSR1_PCVCTL4	0x08
+#define BCSR1_IPB5SEL	0x10
+
+#define BCSR2_ENPA5HDR	0x08	/* USB Control */
+#define BCSR2_ENUSBCLK	0x10
+#define BCSR2_USBPWREN	0x20
+#define BCSR2_USBSPD	0x40
+#define BCSR2_USBSUSP	0x80
+
+#define BCSR3_BWRTC	0x01	/* Real Time Clock Battery */
+#define BCSR3_BWNVR	0x02	/* NVRAM Battery */
+#define BCSR3_RDY_BSY	0x04	/* Flash Operation */
+#define BCSR3_RPXL	0x08	/* Reserved (reads back '1') */
+#define BCSR3_D27	0x10	/* Dip Switch settings */
+#define BCSR3_D26	0x20
+#define BCSR3_D25	0x40
+#define BCSR3_D24	0x80
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/r0p7734.h b/qemu/roms/u-boot/include/configs/r0p7734.h
new file mode 100644
index 000000000..a71709bc7
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/r0p7734.h
@@ -0,0 +1,165 @@
+/*
+ * Configuation settings for the Renesas Solutions r0p7734 board
+ *
+ * Copyright (C) 2010, 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __R0P7734_H
+#define __R0P7734_H
+
+#undef DEBUG
+#define CONFIG_CPU_SH7734	1
+#define CONFIG_R0P7734		1
+#define CONFIG_400MHZ_MODE	1
+/* #define CONFIG_533MHZ_MODE	1 */
+
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
+
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
+
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTARGS		"console=ttySC3,115200"
+
+#define CONFIG_VERSION_VARIABLE
+#undef  CONFIG_SHOW_BOOT_PROGRESS
+
+/* Ether */
+#define CONFIG_SH_ETHER 1
+#define CONFIG_SH_ETHER_USE_PORT (0)
+#define CONFIG_SH_ETHER_PHY_ADDR (0x0)
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_SMSC 1
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+#define CONFIG_SH_ETHER_SH7734_MII (0x00) /* MII */
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
+#ifndef CONFIG_SH_ETHER
+# define CONFIG_SMC911X
+# define CONFIG_SMC911X_16_BIT
+# define CONFIG_SMC911X_BASE (0x84000000)
+#endif
+
+
+/* I2C */
+#define CONFIG_CMD_I2C
+#define CONFIG_SH_SH7734_I2C	1
+#define CONFIG_HARD_I2C			1
+#define CONFIG_I2C_MULTI_BUS	1
+#define CONFIG_SYS_MAX_I2C_BUS	2
+#define CONFIG_SYS_I2C_MODULE	0
+#define CONFIG_SYS_I2C_SPEED	100000 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE	0x50
+#define CONFIG_SH_I2C_DATA_HIGH	4
+#define CONFIG_SH_I2C_DATA_LOW	5
+#define CONFIG_SH_I2C_CLOCK		500000000
+#define CONFIG_SH_I2C_BASE0		0xFFC70000
+#define CONFIG_SH_I2C_BASE1		0xFFC7100
+
+/* undef to save memory	*/
+#define CONFIG_SYS_LONGHELP
+/* Monitor Command Prompt */
+/* Buffer size for input from the Console */
+#define CONFIG_SYS_CBSIZE		256
+/* Buffer size for Console output */
+#define CONFIG_SYS_PBSIZE		256
+/* max args accepted for monitor commands */
+#define CONFIG_SYS_MAXARGS		16
+/* Buffer size for Boot Arguments passed to kernel */
+#define CONFIG_SYS_BARGSIZE	512
+/* List of legal baudrate settings for this board */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE	1
+#define CONFIG_SCIF			1
+#define CONFIG_CONS_SCIF3	1
+
+/* Suppress display of console information at boot */
+#undef  CONFIG_SYS_CONSOLE_INFO_QUIET
+#undef  CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#undef  CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+
+/* SDRAM */
+#define CONFIG_SYS_SDRAM_BASE	(0x88000000)
+#define CONFIG_SYS_SDRAM_SIZE	(128 * 1024 * 1024)
+#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
+
+#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END	 (CONFIG_SYS_MEMTEST_START + 100 * 1024 * 1024)
+/* Enable alternate, more extensive, memory test */
+#undef  CONFIG_SYS_ALT_MEMTEST
+/* Scratch address used by the alternate memory test */
+#undef  CONFIG_SYS_MEMTEST_SCRATCH
+
+/* Enable temporary baudrate change while serial download */
+#undef  CONFIG_SYS_LOADS_BAUD_CHANGE
+
+/* FLASH */
+#define CONFIG_FLASH_CFI_DRIVER 1
+#define CONFIG_SYS_FLASH_CFI
+#undef  CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BASE	(0xA0000000)
+#define CONFIG_SYS_MAX_FLASH_SECT	512
+
+/* if you use all NOR Flash , you change dip-switch. Please see Manual. */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+
+/* Timeout for Flash erase operations (in ms) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(3 * 1000)
+/* Timeout for Flash write operations (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(3 * 1000)
+/* Timeout for Flash set sector lock bit operations (in ms) */
+#define CONFIG_SYS_FLASH_LOCK_TOUT	(3 * 1000)
+/* Timeout for Flash clear lock bit operations (in ms) */
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	(3 * 1000)
+
+/*
+ * Use hardware flash sectors protection instead
+ * of U-Boot software protection
+ */
+#undef  CONFIG_SYS_FLASH_PROTECTION
+#undef  CONFIG_SYS_DIRECT_FLASH_TFTP
+
+/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE)
+/* Monitor size */
+#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
+/* Size of DRAM reserved for malloc() use */
+#define CONFIG_SYS_MALLOC_LEN	(256 * 1024)
+#define CONFIG_SYS_BOOTMAPSZ	(8 * 1024 * 1024)
+
+/* ENV setting */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE	1
+#define CONFIG_ENV_SECT_SIZE	(128 * 1024)
+#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
+/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
+#define CONFIG_ENV_OFFSET	(CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
+
+/* Board Clock */
+#if defined(CONFIG_400MHZ_MODE)
+#define CONFIG_SYS_CLK_FREQ 50000000
+#else
+#define CONFIG_SYS_CLK_FREQ 44444444
+#endif
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_TMU_CLK_DIV      4
+
+#endif	/* __R0P7734_H */
diff --git a/qemu/roms/u-boot/include/configs/r2dplus.h b/qemu/roms/u-boot/include/configs/r2dplus.h
new file mode 100644
index 000000000..24d0c34db
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/r2dplus.h
@@ -0,0 +1,122 @@
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#undef DEBUG
+
+#define CONFIG_CPU_SH7751	1
+#define CONFIG_CPU_SH_TYPE_R	1
+#define CONFIG_R2DPLUS		1
+#define __LITTLE_ENDIAN__	1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_EXT2
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_SH_ZIMAGEBOOT
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE	1
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_CONS_SCIF1	1
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_BOOTDELAY	-1
+#define CONFIG_BOOTARGS		"console=ttySC0,115200"
+#define CONFIG_ENV_OVERWRITE	1
+
+/* SDRAM */
+#define CONFIG_SYS_SDRAM_BASE		(0x8C000000)
+#define CONFIG_SYS_SDRAM_SIZE		(0x04000000)
+
+#define CONFIG_SYS_TEXT_BASE	0x0FFC0000
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_PBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE		512
+
+#define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_TEXT_BASE - 0x100000)
+
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
+/* Address of u-boot image in Flash */
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
+/* Size of DRAM reserved for malloc() use */
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
+#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
+
+/*
+ * NOR Flash ( Spantion S29GL256P )
+ */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_BASE		(0xA0000000)
+#define CONFIG_SYS_MAX_FLASH_BANKS (1)
+#define CONFIG_SYS_MAX_FLASH_SECT  256
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	0x40000
+#define CONFIG_ENV_SIZE        (CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR        (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+
+/*
+ * SuperH Clock setting
+ */
+#define CONFIG_SYS_CLK_FREQ	60000000
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_TMU_CLK_DIV		4
+#define	CONFIG_SYS_PLL_SETTLING_TIME	100/* in us */
+
+/*
+ * IDE support
+ */
+#define CONFIG_IDE_RESET	1
+#define CONFIG_SYS_PIO_MODE		1
+#define CONFIG_SYS_IDE_MAXBUS		1 /* IDE bus */
+#define CONFIG_SYS_IDE_MAXDEVICE	1
+#define CONFIG_SYS_ATA_BASE_ADDR	0xb4000000
+#define CONFIG_SYS_ATA_STRIDE		2 /* 1bit shift */
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x1000	/* data reg offset */
+#define CONFIG_SYS_ATA_REG_OFFSET	0x1000	/* reg offset */
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x800	/* alternate register offset */
+#define CONFIG_IDE_SWAP_IO
+
+/*
+ * SuperH PCI Bridge Configration
+ */
+#define CONFIG_PCI
+#define CONFIG_SH4_PCI
+#define CONFIG_SH7751_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW	1
+#define __io
+#define __mem_pci
+
+#define CONFIG_PCI_MEM_BUS	0xFD000000	/* Memory space base addr */
+#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE	0x01000000	/* Size of Memory window */
+#define CONFIG_PCI_IO_BUS	0xFE240000	/* IO space base address */
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0x00040000	/* Size of IO window */
+#define CONFIG_PCI_SYS_BUS	(CONFIG_SYS_SDRAM_BASE & 0x1fffffff)
+#define CONFIG_PCI_SYS_PHYS	(CONFIG_SYS_SDRAM_BASE & 0x1fffffff)
+#define CONFIG_PCI_SYS_SIZE	CONFIG_SYS_SDRAM_SIZE
+
+/*
+ * Network device (RTL8139) support
+ */
+#define CONFIG_RTL8139
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/r7780mp.h b/qemu/roms/u-boot/include/configs/r7780mp.h
new file mode 100644
index 000000000..8156724f7
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/r7780mp.h
@@ -0,0 +1,154 @@
+/*
+ * Configuation settings for the Renesas R7780MP board
+ *
+ * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __R7780RP_H
+#define __R7780RP_H
+
+#undef DEBUG
+#define CONFIG_CPU_SH7780	1
+#define CONFIG_R7780MP		1
+#define CONFIG_SYS_R7780MP_OLD_FLASH	1
+#define __LITTLE_ENDIAN__ 1
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_EXT2
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_SCIF_CONSOLE	1
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_CONS_SCIF0	1
+
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTARGS		"console=ttySC0,115200"
+#define CONFIG_ENV_OVERWRITE	1
+
+/* check for keypress on bootdelay==0 */
+/*#define CONFIG_ZERO_BOOTDELAY_CHECK*/
+
+#define CONFIG_SYS_TEXT_BASE		0x0FFC0000
+#define CONFIG_SYS_SDRAM_BASE		(0x08000000)
+#define CONFIG_SYS_SDRAM_SIZE		(128 * 1024 * 1024)
+
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_PBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE	512
+
+#define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_TEXT_BASE - 0x100000)
+
+/* Flash board support */
+#define CONFIG_SYS_FLASH_BASE		(0xA0000000)
+#ifdef CONFIG_SYS_R7780MP_OLD_FLASH
+/* NOR Flash (S29PL127J60TFI130) */
+# define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_32BIT
+# define CONFIG_SYS_MAX_FLASH_BANKS	(2)
+# define CONFIG_SYS_MAX_FLASH_SECT	270
+# define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE,\
+				CONFIG_SYS_FLASH_BASE + 0x100000,\
+				CONFIG_SYS_FLASH_BASE + 0x400000,\
+				CONFIG_SYS_FLASH_BASE + 0x700000, }
+#else /* CONFIG_SYS_R7780MP_OLD_FLASH */
+/* NOR Flash (Spantion S29GL256P) */
+# define CONFIG_SYS_MAX_FLASH_BANKS	(1)
+# define CONFIG_SYS_MAX_FLASH_SECT		256
+# define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#endif /* CONFIG_SYS_R7780MP_OLD_FLASH */
+
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
+/* Address of u-boot image in Flash */
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
+/* Size of DRAM reserved for malloc() use */
+#define CONFIG_SYS_MALLOC_LEN		(1204 * 1024)
+
+#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
+#define CONFIG_SYS_RX_ETH_BUFFER	(8)
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#undef CONFIG_SYS_FLASH_CFI_BROKEN_TABLE
+#undef  CONFIG_SYS_FLASH_QUIET_TEST
+/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	(256 * 1024)
+#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500
+
+/* Board Clock */
+#define CONFIG_SYS_CLK_FREQ	33333333
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_TMU_CLK_DIV		4
+
+/* PCI Controller */
+#if defined(CONFIG_CMD_PCI)
+#define CONFIG_PCI
+#define CONFIG_SH4_PCI
+#define CONFIG_SH7780_PCI
+#define CONFIG_SH7780_PCI_LSR	0x07f00001
+#define CONFIG_SH7780_PCI_LAR	CONFIG_SYS_SDRAM_SIZE
+#define CONFIG_SH7780_PCI_BAR	CONFIG_SYS_SDRAM_SIZE
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW	1
+#define __io
+#define __mem_pci
+
+#define CONFIG_PCI_MEM_BUS	0xFD000000	/* Memory space base addr */
+#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE	0x01000000	/* Size of Memory window */
+
+#define CONFIG_PCI_IO_BUS	0xFE200000	/* IO space base address */
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0x00200000	/* Size of IO window */
+#define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE
+#define CONFIG_PCI_SYS_BUS  CONFIG_SYS_SDRAM_BASE
+#define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE
+#endif /* CONFIG_CMD_PCI */
+
+#if defined(CONFIG_CMD_NET)
+/*
+#define CONFIG_RTL8169
+*/
+/* AX88796L Support(NE2000 base chip) */
+#define CONFIG_DRIVER_AX88796L
+#define CONFIG_DRIVER_NE2000_BASE	0xA4100000
+#endif
+
+/* Compact flash Support */
+#if defined(CONFIG_CMD_IDE)
+#define CONFIG_IDE_RESET        1
+#define CONFIG_SYS_PIO_MODE            1
+#define CONFIG_SYS_IDE_MAXBUS          1   /* IDE bus */
+#define CONFIG_SYS_IDE_MAXDEVICE       1
+#define CONFIG_SYS_ATA_BASE_ADDR       0xb4000000
+#define CONFIG_SYS_ATA_STRIDE          2               /* 1bit shift */
+#define CONFIG_SYS_ATA_DATA_OFFSET     0x1000          /* data reg offset */
+#define CONFIG_SYS_ATA_REG_OFFSET      0x1000          /* reg offset */
+#define CONFIG_SYS_ATA_ALT_OFFSET      0x800           /* alternate register offset */
+#define CONFIG_IDE_SWAP_IO
+#endif /* CONFIG_CMD_IDE */
+
+#endif /* __R7780RP_H */
diff --git a/qemu/roms/u-boot/include/configs/rd6281a.h b/qemu/roms/u-boot/include/configs/rd6281a.h
new file mode 100644
index 000000000..9856516c1
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/rd6281a.h
@@ -0,0 +1,98 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CONFIG_RD6281A_H
+#define _CONFIG_RD6281A_H
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING	"\nMarvell-RD6281A"
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_FEROCEON_88FR131	1	/* CPU Core subversion */
+#define CONFIG_KIRKWOOD		1	/* SOC Family Name */
+#define CONFIG_KW88F6281	1	/* SOC Name */
+#define CONFIG_MACH_RD6281A		/* Machine type */
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_IDE
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/*
+ * Environment variables configurations
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_ENV_IS_IN_NAND		1
+#define CONFIG_ENV_SECT_SIZE		0x20000	/* 128K */
+#else
+#define CONFIG_ENV_IS_NOWHERE		1	/* if env in SDRAM */
+#endif
+/*
+ * max 4k env size is enough, but in case of nand
+ * it has to be rounded to sector size
+ */
+#define CONFIG_ENV_SIZE			0x20000	/* 128k */
+#define CONFIG_ENV_ADDR			0x40000
+#define CONFIG_ENV_OFFSET		0x40000	/* env starts here */
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_BOOTCOMMAND		"${x_bootcmd_kernel}; "	\
+	"setenv bootargs ${x_bootargs} ${x_bootargs_root}; "	\
+	"${x_bootcmd_usb}; bootm 0x6400000;"
+
+#define CONFIG_MTDPARTS		"orion_nand:512k(uboot),"	\
+	"3m@1m(kernel),1m@4m(psm),13m@5m(rootfs) rw\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS	"x_bootargs=console"	\
+	"=ttyS0,115200 mtdparts="CONFIG_MTDPARTS	\
+	"x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \
+	"x_bootcmd_usb=usb start\0" \
+	"x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0"
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS	{1, 1}	/* enable both ports */
+#define CONFIG_MV88E61XX_MULTICHIP_ADRMODE
+#define CONFIG_DIS_AUTO_NEG_SPEED_GMII /*Disable Auto speed negociation */
+#define CONFIG_PHY_SPEED	_1000BASET	/*Force PHYspeed to 1GBPs */
+#define CONFIG_PHY_BASE_ADR	0x0A
+#define CONFIG_MV88E61XX_SWITCH	/* Enable MV88E61XX switch driver */
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * SATA Driver configuration
+ */
+#ifdef CONFIG_MVSATA_IDE
+#define CONFIG_SYS_ATA_IDE0_OFFSET	MV_SATA_PORT0_OFFSET
+#define CONFIG_SYS_ATA_IDE1_OFFSET	MV_SATA_PORT1_OFFSET
+#endif /*CONFIG_MVSATA_IDE*/
+
+#endif /* _CONFIG_RD6281A_H */
diff --git a/qemu/roms/u-boot/include/configs/redwood.h b/qemu/roms/u-boot/include/configs/redwood.h
new file mode 100644
index 000000000..622b7c79e
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/redwood.h
@@ -0,0 +1,172 @@
+/*
+ * Configuration for AMCC 460SX Ref (redwood)
+ *
+ * (C) Copyright 2008
+ * Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_440			1	/* ... PPC460 family	*/
+#define CONFIG_460SX			1	/* ... PPC460 family	*/
+#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xfffb0000
+
+/*-----------------------------------------------------------------------
+ * Include common defines/options for all AMCC boards
+ *----------------------------------------------------------------------*/
+#define CONFIG_HOSTNAME		redwood
+
+#include "amcc-common.h"
+
+#define CONFIG_SYS_CLK_FREQ	33333333	/* external freq to pll	*/
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_FLASH_BASE		0xfff00000	/* start of FLASH	*/
+#define CONFIG_SYS_ISRAM_BASE		0x90000000	/* internal SRAM	*/
+
+#define CONFIG_SYS_PCI_BASE		0xd0000000	/* internal PCI regs	*/
+
+#define CONFIG_SYS_PCIE_MEMBASE	0x90000000	/* mapped PCIe memory	*/
+#define CONFIG_SYS_PCIE0_MEMBASE	0x90000000	/* mapped PCIe memory	*/
+#define CONFIG_SYS_PCIE1_MEMBASE	0xa0000000	/* mapped PCIe memory	*/
+#define CONFIG_SYS_PCIE_MEMSIZE	0x01000000
+
+#define CONFIG_SYS_PCIE0_XCFGBASE	0xb0000000
+#define CONFIG_SYS_PCIE1_XCFGBASE	0xb2000000
+#define CONFIG_SYS_PCIE2_XCFGBASE	0xb4000000
+#define CONFIG_SYS_PCIE0_CFGBASE	0xb6000000
+#define CONFIG_SYS_PCIE1_CFGBASE	0xb8000000
+#define CONFIG_SYS_PCIE2_CFGBASE	0xba000000
+
+/* PCIe mapped UTL registers */
+#define CONFIG_SYS_PCIE0_REGBASE   0xd0000000
+#define CONFIG_SYS_PCIE1_REGBASE   0xd0010000
+#define CONFIG_SYS_PCIE2_REGBASE   0xd0020000
+
+/* System RAM mapped to PCI space */
+#define CONFIG_PCI_SYS_MEM_BUS	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_PHYS	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_SIZE	(1024 * 1024 * 1024)
+
+#define CONFIG_SYS_FPGA_BASE		0xe2000000	/* epld			*/
+#define CONFIG_SYS_OPER_FLASH		0xe7000000	/* SRAM - OPER Flash	*/
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in internal SRAM)
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_TEMP_STACK_OCM	1
+#define CONFIG_SYS_OCM_DATA_ADDR	CONFIG_SYS_ISRAM_BASE
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_ISRAM_BASE	/* Initial RAM address	*/
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000		/* Size of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CONFIG_SPD_EEPROM	1	/* Use SPD EEPROM for setup	*/
+#define CONFIG_DDR_ECC		1	/* with ECC support		*/
+
+#define CONFIG_SYS_SPD_MAX_DIMMS	2
+
+/* SPD i2c spd addresses */
+#define SPD_EEPROM_ADDRESS     {IIC0_DIMM0_ADDR, IIC0_DIMM1_ADDR}
+#define IIC0_DIMM0_ADDR		       0x53
+#define IIC0_DIMM1_ADDR		       0x52
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
+
+#define IIC0_BOOTPROM_ADDR	0x50
+#define IIC0_ALT_BOOTPROM_ADDR	0x54
+
+/* Don't probe these addrs */
+#define CONFIG_SYS_I2C_NOPROBES	{ {0, 0x50}, {0, 0x52}, {0, 0x53}, {0, 0x54} }
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2	/* Bytes of address		*/
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+#undef	CONFIG_ENV_IS_IN_NVRAM		/* ... not in NVRAM		*/
+#define	CONFIG_ENV_IS_IN_FLASH	1	/* Environment uses flash	*/
+#undef	CONFIG_ENV_IS_IN_EEPROM		/* ... not in EEPROM		*/
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_AMCC_DEF_ENV						\
+	CONFIG_AMCC_DEF_ENV_POWERPC					\
+	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
+	"kernel_addr=fc000000\0"					\
+	"fdt_addr=fc1e0000\0"						\
+	"ramdisk_addr=fc200000\0"					\
+	""
+
+/*----------------------------------------------------------------------------+
+| Commands in addition to amcc-common.h
++----------------------------------------------------------------------------*/
+#define CONFIG_CMD_SDRAM
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define	CONFIG_IBM_EMAC4_V4	1
+#define CONFIG_PHY_RESET	1	/* reset phy upon startup	*/
+#define CONFIG_PHY_RESET_DELAY	1000
+#define CONFIG_M88E1141_PHY	1	/* Enable phy */
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_PHY_ADDR		0	/* PHY address, See schematics	*/
+#define CONFIG_PHY1_ADDR	1	/* PHY address, See schematics	*/
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible	*/
+#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
+#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1	/* Use AMD (Spansion) reset cmd */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	3	/* number of banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* sectors per device		*/
+
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	0x10000	/* size of one complete sector	*/
+#define CONFIG_ENV_ADDR		0xfffa0000
+#define CONFIG_ENV_SIZE		0x10000	/* Size of Environment vars	*/
+#endif /* CONFIG_ENV_IS_IN_FLASH */
+
+/*---------------------------------------------------------------------------*/
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/rpi_b.h b/qemu/roms/u-boot/include/configs/rpi_b.h
new file mode 100644
index 000000000..ed8b4dfb5
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/rpi_b.h
@@ -0,0 +1,240 @@
+/*
+ * (C) Copyright 2012 Stephen Warren
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+
+/* Architecture, CPU, etc.*/
+#define CONFIG_ARM1176
+#define CONFIG_BCM2835
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_SYS_DCACHE_OFF
+/*
+ * 2835 is a SKU in a series for which the 2708 is the first or primary SoC,
+ * so 2708 has historically been used rather than a dedicated 2835 ID.
+ */
+#define CONFIG_MACH_TYPE		MACH_TYPE_BCM2708
+
+/* Memory layout */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_TEXT_BASE		0x00008000
+#define CONFIG_SYS_UBOOT_BASE		CONFIG_SYS_TEXT_BASE
+/*
+ * The board really has 256M. However, the VC (VideoCore co-processor) shares
+ * the RAM, and uses a configurable portion at the top. We tell U-Boot that a
+ * smaller amount of RAM is present in order to avoid stomping on the area
+ * the VC uses.
+ */
+#define CONFIG_SYS_SDRAM_SIZE		SZ_128M
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + \
+					 CONFIG_SYS_SDRAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_MALLOC_LEN		SZ_4M
+#define CONFIG_SYS_MEMTEST_START	0x00100000
+#define CONFIG_SYS_MEMTEST_END		0x00200000
+#define CONFIG_LOADADDR			0x00200000
+
+/* Flash */
+#define CONFIG_SYS_NO_FLASH
+
+/* Devices */
+/* GPIO */
+#define CONFIG_BCM2835_GPIO
+/* LCD */
+#define CONFIG_LCD
+#define CONFIG_LCD_DT_SIMPLEFB
+#define LCD_BPP				LCD_COLOR16
+/*
+ * Prevent allocation of RAM for FB; the real FB address is queried
+ * dynamically from the VideoCore co-processor, and comes from RAM
+ * not owned by the ARM CPU.
+ */
+#define CONFIG_FB_ADDR			0
+#define CONFIG_VIDEO_BCM2835
+#define CONFIG_SYS_WHITE_ON_BLACK
+
+/* SD/MMC configuration */
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_SDHCI
+#define CONFIG_MMC_SDHCI_IO_ACCESSORS
+#define CONFIG_BCM2835_SDHCI
+
+/* Console UART */
+#define CONFIG_PL011_SERIAL
+#define CONFIG_PL011_CLOCK		3000000
+#define CONFIG_PL01x_PORTS		{ (void *)0x20201000 }
+#define CONFIG_CONS_INDEX		0
+#define CONFIG_BAUDRATE			115200
+
+/* Console configuration */
+#define CONFIG_SYS_CBSIZE		1024
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE +		\
+					 sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Environment */
+#define CONFIG_ENV_SIZE			SZ_16K
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_SYS_LOAD_ADDR		0x1000000
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_PREBOOT \
+	"if load mmc 0:1 ${loadaddr} /uEnv.txt; then " \
+		"env import -t ${loadaddr} ${filesize}; " \
+	"fi"
+
+#define ENV_DEVICE_SETTINGS \
+	"stdin=serial,lcd\0" \
+	"stdout=serial,lcd\0" \
+	"stderr=serial,lcd\0"
+
+/*
+ * Memory layout for where various images get loaded by boot scripts:
+ *
+ * scriptaddr can be pretty much anywhere that doesn't conflict with something
+ *   else. Put it low in memory to avoid conflicts.
+ *
+ * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
+ *   something else. Put it low in memory to avoid conflicts.
+ *
+ * kernel_addr_r must be within the first 128M of RAM in order for the
+ *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
+ *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
+ *   should not overlap that area, or the kernel will have to copy itself
+ *   somewhere else before decompression. Similarly, the address of any other
+ *   data passed to the kernel shouldn't overlap the start of RAM. Pushing
+ *   this up to 16M allows for a sizable kernel to be decompressed below the
+ *   compressed load address.
+ *
+ * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
+ *   the compressed kernel to be up to 16M too.
+ *
+ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
+ *   for the FDT/DTB to be up to 1M, which is hopefully plenty.
+ */
+#define ENV_MEM_LAYOUT_SETTINGS \
+	"scriptaddr=0x00000000\0" \
+	"pxefile_addr_r=0x00100000\0" \
+	"kernel_addr_r=0x01000000\0" \
+	"fdt_addr_r=0x02000000\0" \
+	"fdtfile=bcm2835-rpi-b.dtb\0" \
+	"ramdisk_addr_r=0x02100000\0" \
+
+#define BOOTCMDS_MMC \
+	"mmc_boot=" \
+		"setenv devtype mmc; " \
+		"if mmc dev ${devnum}; then " \
+			"run scan_boot; " \
+		"fi\0" \
+	"bootcmd_mmc0=setenv devnum 0; run mmc_boot;\0"
+#define BOOT_TARGETS_MMC "mmc0"
+
+#define BOOTCMDS_COMMON \
+	"rootpart=1\0" \
+	\
+	"do_script_boot="                                                 \
+		"load ${devtype} ${devnum}:${rootpart} "                  \
+			"${scriptaddr} ${prefix}${script}; "              \
+		"source ${scriptaddr}\0"                                  \
+	\
+	"script_boot="                                                    \
+		"for script in ${boot_scripts}; do "                      \
+			"if test -e ${devtype} ${devnum}:${rootpart} "    \
+					"${prefix}${script}; then "       \
+				"echo Found ${prefix}${script}; "         \
+				"run do_script_boot; "                    \
+				"echo SCRIPT FAILED: continuing...; "     \
+			"fi; "                                            \
+		"done\0"                                                  \
+	\
+	"do_sysboot_boot="                                                \
+		"sysboot ${devtype} ${devnum}:${rootpart} any "           \
+			"${scriptaddr} ${prefix}extlinux/extlinux.conf\0" \
+	\
+	"sysboot_boot="                                                   \
+		"if test -e ${devtype} ${devnum}:${rootpart} "            \
+				"${prefix}extlinux/extlinux.conf; then "  \
+			"echo Found ${prefix}extlinux/extlinux.conf; "    \
+			"run do_sysboot_boot; "                           \
+			"echo SCRIPT FAILED: continuing...; "             \
+		"fi\0"                                                    \
+	\
+	"scan_boot="                                                      \
+		"echo Scanning ${devtype} ${devnum}...; "                 \
+		"for prefix in ${boot_prefixes}; do "                     \
+			"run sysboot_boot; "                              \
+			"run script_boot; "                               \
+		"done\0"                                                  \
+	\
+	"boot_targets=" \
+		BOOT_TARGETS_MMC " " \
+		"\0" \
+	\
+	"boot_prefixes=/\0" \
+	\
+	"boot_scripts=boot.scr.uimg\0" \
+	\
+	BOOTCMDS_MMC
+
+#define CONFIG_BOOTCOMMAND \
+	"for target in ${boot_targets}; do run bootcmd_${target}; done"
+
+#define CONFIG_BOOTCOMMAND \
+	"for target in ${boot_targets}; do run bootcmd_${target}; done"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	ENV_DEVICE_SETTINGS \
+	ENV_MEM_LAYOUT_SETTINGS \
+	BOOTCMDS_COMMON
+
+#define CONFIG_BOOTDELAY 2
+
+/* Shell */
+#define CONFIG_SYS_MAXARGS		8
+#define CONFIG_SYS_PROMPT		"U-Boot> "
+#define CONFIG_COMMAND_HISTORY
+
+/* Commands */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_GPIO
+#define CONFIG_CMD_MMC
+#define CONFIG_PARTITION_UUIDS
+#define CONFIG_CMD_PART
+
+/* Device tree support */
+#define CONFIG_OF_BOARD_SETUP
+/* ATAGs support for bootm/bootz */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+
+#include <config_distro_defaults.h>
+
+/* Some things don't make sense on this HW or yet */
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_SAVEENV
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_MII
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_PING
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/rsk7203.h b/qemu/roms/u-boot/include/configs/rsk7203.h
new file mode 100644
index 000000000..543632458
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/rsk7203.h
@@ -0,0 +1,95 @@
+/*
+ * Configuation settings for the Renesas Technology RSK 7203
+ *
+ * Copyright (C) 2008 Nobuhiro Iwamatsu
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __RSK7203_H
+#define __RSK7203_H
+
+#undef DEBUG
+#define CONFIG_SH2A		1
+#define CONFIG_CPU_SH7203	1
+#define CONFIG_RSK7203	1
+
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_CACHE
+
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_BOOTARGS		"console=ttySC0,115200"
+#define CONFIG_LOADADDR		0x0C100000 /* RSK7203_SDRAM_BASE + 1MB */
+
+#define CONFIG_VERSION_VARIABLE
+#undef	CONFIG_SHOW_BOOT_PROGRESS
+
+/* MEMORY */
+#define RSK7203_SDRAM_BASE	0x0C000000
+#define RSK7203_FLASH_BASE_1	0x20000000	/* Non cache */
+#define RSK7203_FLASH_BANK_SIZE	(4 * 1024 * 1024)
+
+#define CONFIG_SYS_TEXT_BASE	0x0C7C0000
+#define CONFIG_SYS_LONGHELP		/* undef to save memory	*/
+#define CONFIG_SYS_CBSIZE	256	/* Buffer size for input from the Console */
+#define CONFIG_SYS_PBSIZE	256	/* Buffer size for Console output */
+#define CONFIG_SYS_MAXARGS	16	/* max args accepted for monitor commands */
+/* Buffer size for Boot Arguments passed to kernel */
+#define CONFIG_SYS_BARGSIZE	512
+/* List of legal baudrate settings for this board */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE	1
+#define CONFIG_CONS_SCIF0	1
+
+#define CONFIG_SYS_MEMTEST_START	RSK7203_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (3 * 1024 * 1024))
+
+#define CONFIG_SYS_SDRAM_BASE		RSK7203_SDRAM_BASE
+#define CONFIG_SYS_SDRAM_SIZE		(32 * 1024 * 1024)
+
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 1024 * 1024)
+#define CONFIG_SYS_MONITOR_BASE	RSK7203_FLASH_BASE_1
+#define CONFIG_SYS_MONITOR_LEN		(128 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)
+#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
+
+/* FLASH */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#undef	CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_SYS_FLASH_EMPTY_INFO	/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_BASE		RSK7203_FLASH_BASE_1
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_MAX_FLASH_SECT	64
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	(64 * 1024)
+#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_FLASH_ERASE_TOUT	12000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500
+
+/* Board Clock */
+#define CONFIG_SYS_CLK_FREQ	33333333
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CMT_CLK_DIVIDER	32	/* 8 (default), 32, 128 or 512 */
+#define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
+
+/* Network interface */
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_16_BIT
+#define CONFIG_SMC911X_BASE (0x24000000)
+
+#endif	/* __RSK7203_H */
diff --git a/qemu/roms/u-boot/include/configs/rsk7264.h b/qemu/roms/u-boot/include/configs/rsk7264.h
new file mode 100644
index 000000000..4aaa3ef74
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/rsk7264.h
@@ -0,0 +1,75 @@
+/*
+ * Configuation settings for the Renesas RSK2+SH7264 board
+ *
+ * Copyright (C) 2011 Renesas Electronics Europe Ltd.
+ * Copyright (C) 2008 Nobuhiro Iwamatsu
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __RSK7264_H
+#define __RSK7264_H
+
+#undef DEBUG
+#define CONFIG_SH2A		1
+#define CONFIG_CPU_SH7264	1
+#define CONFIG_RSK7264		1
+
+#ifndef _CONFIG_CMD_DEFAULT_H
+# include <config_cmd_default.h>
+#endif
+
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_BOOTARGS		"console=ttySC3,115200"
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_SYS_BAUDRATE_TABLE	{ CONFIG_BAUDRATE }
+
+#define CONFIG_SYS_LONGHELP	1	/* undef to save memory	*/
+#define CONFIG_SYS_CBSIZE	256	/* Buffer size for input from the Console */
+#define CONFIG_SYS_PBSIZE	256	/* Buffer size for Console output */
+#define CONFIG_SYS_MAXARGS	16	/* max args accepted for monitor commands */
+
+/* Serial */
+#define CONFIG_SCIF_CONSOLE	1
+#define CONFIG_CONS_SCIF3	1
+
+/* Memory */
+/* u-boot relocated to top 256KB of ram */
+#define CONFIG_SYS_TEXT_BASE		0x0CFC0000
+#define CONFIG_SYS_SDRAM_BASE		0x0C000000
+#define CONFIG_SYS_SDRAM_SIZE		(64 * 1024 * 1024)
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_TEXT_BASE - 0x100000)
+#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)
+#define CONFIG_SYS_MONITOR_LEN		(128 * 1024)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 4*1024*1024)
+
+/* Flash */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI_WIDTH 	FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_BASE		0x20000000 /* Non-cached */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	512
+
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_OFFSET	(128 * 1024)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SECT_SIZE	(128 * 1024)
+#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
+
+/* Board Clock */
+#define CONFIG_SYS_CLK_FREQ	36000000
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CMT_CLK_DIVIDER		32	/* 8 (default), 32, 128 or 512 */
+#define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
+
+/* Network interface */
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_16_BIT
+#define CONFIG_SMC911X_BASE	0x28000000
+
+#endif	/* __RSK7264_H */
diff --git a/qemu/roms/u-boot/include/configs/rsk7269.h b/qemu/roms/u-boot/include/configs/rsk7269.h
new file mode 100644
index 000000000..11fc231fa
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/rsk7269.h
@@ -0,0 +1,74 @@
+/*
+ * Configuation settings for the Renesas RSK2+SH7269 board
+ *
+ * Copyright (C) 2012 Renesas Electronics Europe Ltd.
+ * Copyright (C) 2012 Phil Edworthy
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __RSK7269_H
+#define __RSK7269_H
+
+#undef DEBUG
+#define CONFIG_SH2A		1
+#define CONFIG_CPU_SH7269	1
+#define CONFIG_RSK7269		1
+
+#ifndef _CONFIG_CMD_DEFAULT_H
+# include <config_cmd_default.h>
+#endif
+
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_BOOTARGS		"console=ttySC7,115200"
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_SYS_BAUDRATE_TABLE	{ CONFIG_BAUDRATE }
+
+#define CONFIG_SYS_LONGHELP		/* undef to save memory	*/
+#define CONFIG_SYS_CBSIZE	256	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_PBSIZE	256	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+
+/* Serial */
+#define CONFIG_SCIF_CONSOLE
+#define CONFIG_CONS_SCIF7
+
+/* Memory */
+/* u-boot relocated to top 256KB of ram */
+#define CONFIG_SYS_TEXT_BASE		0x0DFC0000
+#define CONFIG_SYS_SDRAM_BASE		0x0C000000
+#define CONFIG_SYS_SDRAM_SIZE		(32 * 1024 * 1024)
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_TEXT_BASE - 0x100000)
+#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)
+#define CONFIG_SYS_MONITOR_LEN		(128 * 1024)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 4*1024*1024)
+
+/* NOR Flash */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_BASE		0x20000000 /* Non-cached */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	512
+
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_OFFSET	(128 * 1024)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SECT_SIZE	(64 * 1024)
+#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
+
+/* Board Clock */
+#define CONFIG_SYS_CLK_FREQ	66125000
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CMT_CLK_DIVIDER		32	/* 8 (default), 32, 128 or 512 */
+#define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
+
+/* Network interface */
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_16_BIT
+#define CONFIG_SMC911X_BASE	0x24000000
+
+#endif	/* __RSK7269_H */
diff --git a/qemu/roms/u-boot/include/configs/rut.h b/qemu/roms/u-boot/include/configs/rut.h
new file mode 100644
index 000000000..6bddededa
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/rut.h
@@ -0,0 +1,157 @@
+/*
+ * siemens rut
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * U-Boot file:/include/configs/am335x_evm.h
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_RUT_H
+#define __CONFIG_RUT_H
+
+#define CONFIG_SIEMENS_RUT
+#define MACH_TYPE_RUT			4316
+#define CONFIG_SIEMENS_MACH_TYPE	MACH_TYPE_RUT
+
+#include "siemens-am33x-common.h"
+
+#define CONFIG_SYS_MPUCLK	600
+#define RUT_IOCTRL_VAL	0x18b
+#define DDR_PLL_FREQ	303
+
+ /* Physical Memory Map */
+#define CONFIG_MAX_RAM_BANK_SIZE	(256 << 20) /* 256 MiB */
+
+/* I2C Configuration */
+#define CONFIG_SYS_I2C_SPEED		100000
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR              0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       6       /* 64 byte pages */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* take up to 10 msec */
+
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200
+
+#undef CONFIG_SPL_NET_SUPPORT
+#undef CONFIG_SPL_NET_VCI_STRING
+#undef CONFIG_SPL_ETH_SUPPORT
+
+#define CONFIG_PHY_NATSEMI
+
+#define CONFIG_FACTORYSET
+
+/* UBI Support */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#endif
+
+/* Watchdog */
+#define WATCHDOG_TRIGGER_GPIO	14
+
+#ifndef CONFIG_SPL_BUILD
+
+/* Default env settings */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"hostname=rut\0" \
+	"nand_img_size=0x500000\0" \
+	"splashpos=m,m\0" \
+	"optargs=fixrtc --no-log consoleblank=0 \0" \
+	CONFIG_COMMON_ENV_SETTINGS \
+	"mmc_dev=0\0" \
+	"mmc_root=/dev/mmcblk0p2 rw\0" \
+	"mmc_root_fs_type=ext4 rootwait\0" \
+	"mmc_load_uimage=" \
+		"mmc rescan; " \
+		"setenv bootfile uImage;" \
+		"fatload mmc ${mmc_dev} ${kloadaddr} ${bootfile}\0" \
+	"loadbootenv=fatload mmc ${mmc_dev} ${loadaddr} ${bootenv}\0" \
+	"importbootenv=echo Importing environment from mmc ...; " \
+		"env import -t $loadaddr $filesize\0" \
+	"mmc_args=run bootargs_defaults;" \
+		"mtdparts default;" \
+		"setenv bootargs ${bootargs} " \
+		"root=${mmc_root} ${mtdparts}" \
+		"rootfstype=${mmc_root_fs_type} ip=${ip_method} " \
+		"eth=${ethaddr} " \
+		"\0" \
+	"mmc_boot=run mmc_args; " \
+		"run mmc_load_uimage; " \
+		"bootm ${kloadaddr}\0" \
+	""
+
+#ifndef CONFIG_RESTORE_FLASH
+/* set to negative value for no autoboot */
+#define CONFIG_BOOTDELAY		3
+
+#define CONFIG_BOOTCOMMAND \
+	"if mmc rescan; then " \
+		"echo SD/MMC found on device ${mmc_dev};" \
+		"if run loadbootenv; then " \
+			"echo Loaded environment from ${bootenv};" \
+			"run importbootenv;" \
+		"fi;" \
+		"if test -n $uenvcmd; then " \
+			"echo Running uenvcmd ...;" \
+			"run uenvcmd;" \
+		"fi;" \
+		"if run mmc_load_uimage; then " \
+			"run mmc_args;" \
+			"bootm ${kloadaddr};" \
+		"fi;" \
+	"fi;" \
+	"run nand_boot;" \
+	"reset;"
+
+#else
+#define CONFIG_BOOTDELAY		0
+
+#define CONFIG_BOOTCOMMAND			\
+	"setenv autoload no; "			\
+	"dhcp; "				\
+	"if tftp 80000000 debrick.scr; then "	\
+		"source 80000000; "		\
+	"fi"
+#endif
+
+#endif /* CONFIG_SPL_BUILD */
+
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_HW_WATCHDOG
+#endif
+
+#define CONFIG_VIDEO
+#if defined(CONFIG_VIDEO)
+#define CONFIG_VIDEO_DA8XX
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_CMD_BMP
+#define DA8XX_LCD_CNTL_BASE	LCD_CNTL_BASE
+
+#define CONFIG_SPI
+#define CONFIG_OMAP3_SPI
+
+#define BOARD_LCD_RESET		115	/* Bank 3 pin 19 */
+#define CONFIG_ARCH_EARLY_INIT_R
+#define CONFIG_FORMIKE
+#define DISPL_PLL_SPREAD_SPECTRUM
+#define CONFIG_SYS_CONSOLE_BG_COL	0xff
+#define CONFIG_SYS_CONSOLE_FG_COL	0x00
+#endif
+
+#endif	/* ! __CONFIG_RUT_H */
diff --git a/qemu/roms/u-boot/include/configs/s5p_goni.h b/qemu/roms/u-boot/include/configs/s5p_goni.h
new file mode 100644
index 000000000..991c43e1c
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/s5p_goni.h
@@ -0,0 +1,230 @@
+/*
+ * Copyright (C) 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * Configuation settings for the SAMSUNG Universal (s5pc100) board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_SAMSUNG		1	/* in a SAMSUNG core */
+#define CONFIG_S5P		1	/* which is in a S5P Family */
+#define CONFIG_S5PC110		1	/* which is in a S5PC110 */
+#define CONFIG_MACH_GONI	1	/* working with Goni */
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* input clock of PLL: has 24MHz input clock at S5PC110 */
+#define CONFIG_SYS_CLK_FREQ_C110	24000000
+
+/* DRAM Base */
+#define CONFIG_SYS_SDRAM_BASE		0x30000000
+
+/* Text Base */
+#define CONFIG_SYS_TEXT_BASE		0x34800000
+
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_EDITING
+
+/*
+ * Size of malloc() pool
+ * 1MB = 0x100000, 0x100000 = 1024 * 1024
+ */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (1 << 20))
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL2			1	/* use SERIAL2 */
+#define CONFIG_BAUDRATE			115200
+
+/* MMC */
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_SDHCI
+#define CONFIG_S5P_SDHCI
+
+/* PWM */
+#define CONFIG_PWM			1
+
+/* It should define before config_cmd_default.h */
+#define CONFIG_SYS_NO_FLASH		1
+
+/* Command definition */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_MISC
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_XIMG
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_ONENAND
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_MMC
+
+#define CONFIG_BOOTDELAY		1
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+
+/* Actual modem binary size is 16MiB. Add 2MiB for bad block handling */
+#define MTDIDS_DEFAULT		"onenand0=samsung-onenand"
+#define MTDPARTS_DEFAULT	"mtdparts=samsung-onenand:1m(bootloader)"\
+				",256k(params)"\
+				",2816k(config)"\
+				",8m(csa)"\
+				",7m(kernel)"\
+				",1m(log)"\
+				",12m(modem)"\
+				",60m(qboot)"\
+				",-(UBI)\0"
+
+#define NORMAL_MTDPARTS_DEFAULT MTDPARTS_DEFAULT
+
+#define CONFIG_BOOTCOMMAND	"run ubifsboot"
+
+#define CONFIG_DEFAULT_CONSOLE	"console=ttySAC2,115200n8\0"
+
+#define CONFIG_RAMDISK_BOOT	"root=/dev/ram0 rw rootfstype=ext2" \
+		" ${console} ${meminfo}"
+
+#define CONFIG_COMMON_BOOT	"${console} ${meminfo} ${mtdparts}"
+
+#define CONFIG_BOOTARGS	"root=/dev/mtdblock8 ubi.mtd=8 ubi.mtd=3 ubi.mtd=6" \
+		" rootfstype=cramfs " CONFIG_COMMON_BOOT
+
+#define CONFIG_UPDATEB	"updateb=onenand erase 0x0 0x100000;" \
+			" onenand write 0x32008000 0x0 0x100000\0"
+
+#define CONFIG_UBI_MTD	" ubi.mtd=${ubiblock} ubi.mtd=3 ubi.mtd=6"
+
+#define CONFIG_UBIFS_OPTION	"rootflags=bulk_read,no_chk_data_crc"
+
+#define CONFIG_MISC_COMMON
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_UPDATEB \
+	"updatek=" \
+		"onenand erase 0xc00000 0x600000;" \
+		"onenand write 0x31008000 0xc00000 0x600000\0" \
+	"updateu=" \
+		"onenand erase 0x01560000 0x1eaa0000;" \
+		"onenand write 0x32000000 0x1260000 0x8C0000\0" \
+	"bootk=" \
+		"onenand read 0x30007FC0 0xc00000 0x600000;" \
+		"bootm 0x30007FC0\0" \
+	"flashboot=" \
+		"set bootargs root=/dev/mtdblock${bootblock} " \
+		"rootfstype=${rootfstype}" CONFIG_UBI_MTD " ${opts} " \
+		"${lcdinfo} " CONFIG_COMMON_BOOT "; run bootk\0" \
+	"ubifsboot=" \
+		"set bootargs root=ubi0!rootfs rootfstype=ubifs " \
+		CONFIG_UBIFS_OPTION CONFIG_UBI_MTD " ${opts} ${lcdinfo} " \
+		CONFIG_COMMON_BOOT "; run bootk\0" \
+	"tftpboot=" \
+		"set bootargs root=ubi0!rootfs rootfstype=ubifs " \
+		CONFIG_UBIFS_OPTION CONFIG_UBI_MTD " ${opts} ${lcdinfo} " \
+		CONFIG_COMMON_BOOT "; tftp 0x30007FC0 uImage; " \
+		"bootm 0x30007FC0\0" \
+	"ramboot=" \
+		"set bootargs " CONFIG_RAMDISK_BOOT \
+		" initrd=0x33000000,8M ramdisk=8192\0" \
+	"mmcboot=" \
+		"set bootargs root=${mmcblk} rootfstype=${rootfstype}" \
+		CONFIG_UBI_MTD " ${opts} ${lcdinfo} " \
+		CONFIG_COMMON_BOOT "; run bootk\0" \
+	"boottrace=setenv opts initcall_debug; run bootcmd\0" \
+	"bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \
+	"verify=n\0" \
+	"rootfstype=cramfs\0" \
+	"console=" CONFIG_DEFAULT_CONSOLE \
+	"mtdparts=" MTDPARTS_DEFAULT \
+	"meminfo=mem=80M mem=256M@0x40000000 mem=128M@0x50000000\0" \
+	"mmcblk=/dev/mmcblk1p1\0" \
+	"bootblock=9\0" \
+	"ubiblock=8\0" \
+	"ubi=enabled\0" \
+	"opts=always_resume=1"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser	*/
+#define CONFIG_SYS_PROMPT	"Goni # "
+#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE	384	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5000000)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x4000000)
+
+/* Goni has 3 banks of DRAM, but swap the bank */
+#define CONFIG_NR_DRAM_BANKS	3
+#define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE	/* OneDRAM Bank #0 */
+#define PHYS_SDRAM_1_SIZE	(80 << 20)		/* 80 MB in Bank #0 */
+#define PHYS_SDRAM_2		0x40000000		/* mDDR DMC1 Bank #1 */
+#define PHYS_SDRAM_2_SIZE	(256 << 20)		/* 256 MB in Bank #1 */
+#define PHYS_SDRAM_3		0x50000000		/* mDDR DMC2 Bank #2 */
+#define PHYS_SDRAM_3_SIZE	(128 << 20)		/* 128 MB in Bank #2 */
+
+#define CONFIG_SYS_MONITOR_BASE		0x00000000
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* 256 KiB */
+
+/* FLASH and environment organization */
+#define CONFIG_ENV_IS_IN_ONENAND	1
+#define CONFIG_ENV_SIZE			(256 << 10)	/* 256 KiB, 0x40000 */
+#define CONFIG_ENV_ADDR			(1 << 20)	/* 1 MB, 0x100000 */
+
+#define CONFIG_USE_ONENAND_BOARD_INIT
+#define CONFIG_SAMSUNG_ONENAND		1
+#define CONFIG_SYS_ONENAND_BASE		0xB0000000
+
+#define CONFIG_DOS_PARTITION		1
+
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_LOAD_ADDR - 0x1000000)
+
+#define CONFIG_SYS_CACHELINE_SIZE       64
+
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_MAX8998
+
+#include <asm/arch/gpio.h>
+/*
+ * I2C Settings
+ */
+#define CONFIG_SOFT_I2C_GPIO_SCL s5pc110_gpio_get(j4, 3)
+#define CONFIG_SOFT_I2C_GPIO_SDA s5pc110_gpio_get(j4, 0)
+
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED	50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0x7F
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_MAX_I2C_BUS	7
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_GADGET_S3C_UDC_OTG
+#define CONFIG_USB_GADGET_DUALSPEED
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/s5pc210_universal.h b/qemu/roms/u-boot/include/configs/s5pc210_universal.h
new file mode 100644
index 000000000..2da887109
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/s5pc210_universal.h
@@ -0,0 +1,256 @@
+/*
+ * Copyright (C) 2010 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * Configuation settings for the SAMSUNG Universal (EXYNOS4210) board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_UNIVERSAL_H
+#define __CONFIG_UNIVERSAL_H
+
+#include <configs/exynos4-dt.h>
+
+#define CONFIG_SYS_PROMPT	"Universal # "	/* Monitor Command Prompt */
+
+#undef CONFIG_DEFAULT_DEVICE_TREE
+#define CONFIG_DEFAULT_DEVICE_TREE	exynos4210-universal_c210
+
+#define CONFIG_TIZEN			/* TIZEN lib */
+
+/* Keep L2 Cache Disabled */
+#define CONFIG_SYS_L2CACHE_OFF		1
+
+/* Universal has 2 banks of DRAM */
+#define CONFIG_NR_DRAM_BANKS		2
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define PHYS_SDRAM_1			CONFIG_SYS_SDRAM_BASE
+
+#define SDRAM_BANK_SIZE			(256 << 20)	/* 256 MB */
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (80 * SZ_1M))
+
+/* select serial console configuration */
+#define CONFIG_SERIAL2
+#define CONFIG_BAUDRATE			115200
+
+/* Console configuration */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+#define CONFIG_BOOTARGS			"Please use defined boot"
+#define CONFIG_BOOTCOMMAND		"run mmcboot"
+#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC1,115200n8\0"
+
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_LOAD_ADDR \
+					- GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_MEM_TOP_HIDE	(1 << 20)	/* ram console */
+
+#define CONFIG_SYS_MONITOR_BASE	0x00000000
+
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5000000)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x4800000)
+
+#define CONFIG_SYS_TEXT_BASE		0x44800000
+
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+
+/* Actual modem binary size is 16MiB. Add 2MiB for bad block handling */
+#define MTDIDS_DEFAULT		"onenand0=samsung-onenand"
+
+#define MTDPARTS_DEFAULT	"mtdparts=samsung-onenand:"\
+				"128k(s-boot)"\
+				",896k(bootloader)"\
+				",256k(params)"\
+				",2816k(config)"\
+				",8m(csa)"\
+				",7m(kernel)"\
+				",1m(log)"\
+				",12m(modem)"\
+				",60m(qboot)"\
+				",-(UBI)\0"
+
+#define NORMAL_MTDPARTS_DEFAULT MTDPARTS_DEFAULT
+
+#define MBRPARTS_DEFAULT	"20M(permanent)"\
+				",20M(boot)"\
+				",1G(system)"\
+				",100M(swap)"\
+				",-(UMS)\0"
+
+#define CONFIG_ENV_UBI_MTD	" ubi.mtd=${ubiblock} ubi.mtd=4 ubi.mtd=7"
+#define CONFIG_BOOTBLOCK	"10"
+#define CONFIG_UBIBLOCK		"9"
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV		CONFIG_MMC_DEFAULT_DEV
+#define CONFIG_ENV_SIZE			4096
+#define CONFIG_ENV_OFFSET		((32 - 4) << 10) /* 32KiB - 4KiB */
+
+#define CONFIG_ENV_UBIFS_OPTION	" rootflags=bulk_read,no_chk_data_crc "
+#define CONFIG_ENV_FLASHBOOT	CONFIG_ENV_UBI_MTD CONFIG_ENV_UBIFS_OPTION \
+				"${mtdparts}"
+
+#define CONFIG_ENV_COMMON_BOOT	"${console} ${meminfo}"
+
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"updateb=" \
+		"onenand erase 0x0 0x100000;" \
+		"onenand write 0x42008000 0x0 0x100000\0" \
+	"updatek=" \
+		"onenand erase 0xc00000 0x500000;" \
+		"onenand write 0x41008000 0xc00000 0x500000\0" \
+	"bootk=" \
+		"run loaduimage; bootm 0x40007FC0\0" \
+	"updatemmc=" \
+		"mmc boot 0 1 1 1; mmc write 0 0x42008000 0 0x200;" \
+		"mmc boot 0 1 1 0\0" \
+	"updatebackup=" \
+		"mmc boot 0 1 1 2; mmc write 0 0x42100000 0 0x200;" \
+		"mmc boot 0 1 1 0\0" \
+	"updatebootb=" \
+		"mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \
+	"lpj=lpj=3981312\0" \
+	"ubifsboot=" \
+		"set bootargs root=ubi0!rootfs rootfstype=ubifs ${lpj} " \
+		CONFIG_ENV_FLASHBOOT " ${opts} ${lcdinfo} " \
+		CONFIG_ENV_COMMON_BOOT "; run bootk\0" \
+	"tftpboot=" \
+		"set bootargs root=ubi0!rootfs rootfstype=ubifs " \
+		CONFIG_ENV_FLASHBOOT " ${opts} ${lcdinfo} " \
+		CONFIG_ENV_COMMON_BOOT \
+		"; tftp 0x40007FC0 uImage; bootm 0x40007FC0\0" \
+	"nfsboot=" \
+		"set bootargs root=/dev/nfs rw " \
+		"nfsroot=${nfsroot},nolock,tcp " \
+		"ip=${ipaddr}:${serverip}:${gatewayip}:" \
+		"${netmask}:generic:usb0:off " CONFIG_ENV_COMMON_BOOT \
+		"; run bootk\0" \
+	"ramfsboot=" \
+		"set bootargs root=/dev/ram0 rw rootfstype=ext2 " \
+		"${console} ${meminfo} " \
+		"initrd=0x43000000,8M ramdisk=8192\0" \
+	"mmcboot=" \
+		"set bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
+		"${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \
+		"run loaduimage; bootm 0x40007FC0\0" \
+	"bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \
+	"boottrace=setenv opts initcall_debug; run bootcmd\0" \
+	"mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \
+	"verify=n\0" \
+	"rootfstype=ext4\0" \
+	"console=" CONFIG_DEFAULT_CONSOLE \
+	"mtdparts=" MTDPARTS_DEFAULT \
+	"mbrparts=" MBRPARTS_DEFAULT \
+	"meminfo=crashkernel=32M@0x50000000\0" \
+	"nfsroot=/nfsroot/arm\0" \
+	"bootblock=" CONFIG_BOOTBLOCK "\0" \
+	"ubiblock=" CONFIG_UBIBLOCK" \0" \
+	"ubi=enabled\0" \
+	"loaduimage=fatload mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \
+	"mmcdev=0\0" \
+	"mmcbootpart=2\0" \
+	"mmcrootpart=3\0" \
+	"opts=always_resume=1"
+
+#define CONFIG_USE_ONENAND_BOARD_INIT
+#define CONFIG_SAMSUNG_ONENAND
+#define CONFIG_SYS_ONENAND_BASE		0x0C000000
+
+#include <asm/arch/gpio.h>
+/*
+ * I2C Settings
+ */
+#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_get(1, b, 7)
+#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_get(1, b, 6)
+
+#define CONFIG_CMD_I2C
+
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED	50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0
+#define CONFIG_SOFT_I2C_READ_REPEATED_START
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_MAX_I2C_BUS	7
+
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_MAX8998
+
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_GADGET_S3C_UDC_OTG
+#define CONFIG_USB_GADGET_DUALSPEED
+
+/*
+ * SPI Settings
+ */
+#define CONFIG_SOFT_SPI
+#define CONFIG_SOFT_SPI_MODE SPI_MODE_3
+#define CONFIG_SOFT_SPI_GPIO_SCLK exynos4_gpio_get(2, y3, 1)
+#define CONFIG_SOFT_SPI_GPIO_MOSI exynos4_gpio_get(2, y3, 3)
+#define CONFIG_SOFT_SPI_GPIO_MISO exynos4_gpio_get(2, y3, 0)
+#define CONFIG_SOFT_SPI_GPIO_CS exynos4_gpio_get(2, y4, 3)
+
+#define SPI_DELAY udelay(1)
+#undef SPI_INIT
+#define SPI_SCL(bit) universal_spi_scl(bit)
+#define SPI_SDA(bit) universal_spi_sda(bit)
+#define SPI_READ universal_spi_read()
+#ifndef	__ASSEMBLY__
+void universal_spi_scl(int bit);
+void universal_spi_sda(int bit);
+int universal_spi_read(void);
+#endif
+
+/* Common misc for Samsung */
+#define CONFIG_MISC_COMMON
+
+#define CONFIG_MISC_INIT_R
+
+/* Download menu - Samsung common */
+#define CONFIG_LCD_MENU
+#define CONFIG_LCD_MENU_BOARD
+
+/* Download menu - definitions for check keys */
+#ifndef __ASSEMBLY__
+#include <power/max8998_pmic.h>
+
+#define KEY_PWR_PMIC_NAME		"MAX8998_PMIC"
+#define KEY_PWR_STATUS_REG		MAX8998_REG_STATUS1
+#define KEY_PWR_STATUS_MASK		(1 << 7)
+#define KEY_PWR_INTERRUPT_REG		MAX8998_REG_IRQ1
+#define KEY_PWR_INTERRUPT_MASK		(1 << 7)
+
+#define KEY_VOL_UP_GPIO			exynos4_gpio_get(2, x2, 0)
+#define KEY_VOL_DOWN_GPIO		exynos4_gpio_get(2, x2, 1)
+#endif /* __ASSEMBLY__ */
+
+/* LCD console */
+#define LCD_BPP			LCD_COLOR16
+#define CONFIG_SYS_WHITE_ON_BLACK
+
+/*
+ * LCD Settings
+ */
+#define CONFIG_EXYNOS_FB
+#define CONFIG_LCD
+#define CONFIG_CMD_BMP
+#define CONFIG_BMP_16BPP
+#define CONFIG_LD9040
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)
+
+#define LCD_XRES	480
+#define LCD_YRES	800
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/sacsng.h b/qemu/roms/u-boot/include/configs/sacsng.h
new file mode 100644
index 000000000..b5064ab37
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/sacsng.h
@@ -0,0 +1,1039 @@
+/*
+ * (C) Copyright 2000
+ * Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ *
+ * (C) Copyright 2000
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2001
+ * Advent Networks, Inc. <http://www.adventnetworks.com>
+ * Jay Monkman <jtm@smoothsmoothie.com>
+ *
+ * Configuration settings for the SACSng 8260 board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define	CONFIG_SYS_TEXT_BASE	0x40000000
+
+#undef DEBUG_BOOTP_EXT	      /* Debug received vendor fields */
+
+#undef CONFIG_LOGBUFFER       /* External logbuffer support */
+
+/*****************************************************************************
+ *
+ * These settings must match the way _your_ board is set up
+ *
+ *****************************************************************************/
+
+/* What is the oscillator's (UX2) frequency in Hz? */
+#define CONFIG_8260_CLKIN  66666600
+
+/*-----------------------------------------------------------------------
+ * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
+ *-----------------------------------------------------------------------
+ * What should MODCK_H be? It is dependent on the oscillator
+ * frequency, MODCK[1-3], and desired CPM and core frequencies.
+ * Here are some example values (all frequencies are in MHz):
+ *
+ * MODCK_H   MODCK[1-3]	 Osc	CPM    Core  S2-6   S2-7   S2-8
+ * -------   ----------	 ---	---    ----  -----  -----  -----
+ * 0x1	     0x5	 33	100    133   Open   Close  Open
+ * 0x1	     0x6	 33	100    166   Open   Open   Close
+ * 0x1	     0x7	 33	100    200   Open   Open   Open
+ *
+ * 0x2	     0x2	 33	133    133   Close  Open   Close
+ * 0x2	     0x3	 33	133    166   Close  Open   Open
+ * 0x2	     0x4	 33	133    200   Open   Close  Close
+ * 0x2	     0x5	 33	133    233   Open   Close  Open
+ * 0x2	     0x6	 33	133    266   Open   Open   Close
+ *
+ * 0x5	     0x5	 66	133    133   Open   Close  Open
+ * 0x5	     0x6	 66	133    166   Open   Open   Close
+ * 0x5	     0x7	 66	133    200   Open   Open   Open
+ * 0x6	     0x0	 66	133    233   Close  Close  Close
+ * 0x6	     0x1	 66	133    266   Close  Close  Open
+ * 0x6	     0x2	 66	133    300   Close  Open   Close
+ */
+#define CONFIG_SYS_SBC_MODCK_H 0x05
+
+/* Define this if you want to boot from 0x00000100. If you don't define
+ * this, you will need to program the bootloader to 0xfff00000, and
+ * get the hardware reset config words at 0xfe000000. The simplest
+ * way to do that is to program the bootloader at both addresses.
+ * It is suggested that you just let U-Boot live at 0x00000000.
+ */
+#define CONFIG_SYS_SBC_BOOT_LOW 1
+
+/* What should the base address of the main FLASH be and how big is
+ * it (in MBytes)?  This must contain CONFIG_SYS_TEXT_BASE from board/sacsng/config.mk
+ * The main FLASH is whichever is connected to *CS0.
+ */
+#define CONFIG_SYS_FLASH0_BASE 0x40000000
+#define CONFIG_SYS_FLASH0_SIZE 2
+
+/* What should the base address of the secondary FLASH be and how big
+ * is it (in Mbytes)?  The secondary FLASH is whichever is connected
+ * to *CS6.
+ */
+#define CONFIG_SYS_FLASH1_BASE 0x60000000
+#define CONFIG_SYS_FLASH1_SIZE 2
+
+/* Define CONFIG_VERY_BIG_RAM to allow use of SDRAMs larger than 256MBytes
+ */
+#define CONFIG_VERY_BIG_RAM	1
+
+/* What should be the base address of SDRAM DIMM and how big is
+ * it (in Mbytes)?  This will normally auto-configure via the SPD.
+*/
+#define CONFIG_SYS_SDRAM0_BASE 0x00000000
+#define CONFIG_SYS_SDRAM0_SIZE 64
+
+/*
+ * Memory map example with 64 MB DIMM:
+ *
+ *     0x0000 0000     Exception Vector code, 8k
+ *	     :
+ *     0x0000 1FFF
+ *     0x0000 2000     Free for Application Use
+ *	     :
+ *	     :
+ *
+ *	     :
+ *	     :
+ *     0x03F5 FF30     Monitor Stack (Growing downward)
+ *		       Monitor Stack Buffer (0x80)
+ *     0x03F5 FFB0     Board Info Data
+ *     0x03F6 0000     Malloc Arena
+ *	     :		    CONFIG_ENV_SECT_SIZE, 16k
+ *	     :		    CONFIG_SYS_MALLOC_LEN,    128k
+ *     0x03FC 0000     RAM Copy of Monitor Code
+ *	     :		    CONFIG_SYS_MONITOR_LEN,   256k
+ *     0x03FF FFFF     [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1
+ */
+
+#define CONFIG_POST		(CONFIG_SYS_POST_MEMORY | \
+				 CONFIG_SYS_POST_CPU)
+
+
+/*
+ * select serial console configuration
+ *
+ * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ *
+ * if CONFIG_CONS_NONE is defined, then the serial console routines must
+ * defined elsewhere.
+ */
+#define CONFIG_CONS_ON_SMC	1	/* define if console on SMC */
+#undef	CONFIG_CONS_ON_SCC		/* define if console on SCC */
+#undef	CONFIG_CONS_NONE		/* define if console on neither */
+#define CONFIG_CONS_INDEX	1	/* which SMC/SCC channel for console */
+
+/*
+ * select ethernet configuration
+ *
+ * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
+ * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
+ * for FCC)
+ *
+ * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
+ */
+
+#undef	CONFIG_ETHER_ON_SCC
+#define CONFIG_ETHER_ON_FCC
+#undef	CONFIG_ETHER_NONE		/* define if ethernet on neither */
+
+#ifdef	CONFIG_ETHER_ON_SCC
+#define CONFIG_ETHER_INDEX	1	/* which SCC/FCC channel for ethernet */
+#endif	/* CONFIG_ETHER_ON_SCC */
+
+#ifdef	CONFIG_ETHER_ON_FCC
+#define CONFIG_ETHER_INDEX	2	/* which SCC/FCC channel for ethernet */
+#undef  CONFIG_ETHER_LOOPBACK_TEST      /* Ethernet external loopback test */
+#define CONFIG_MII			/* MII PHY management		*/
+#define CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
+/*
+ * Port pins used for bit-banged MII communictions (if applicable).
+ */
+
+#define MDIO_PORT	2	        /* Port A=0, B=1, C=2, D=3 */
+#define MDIO_DECLARE	volatile ioport_t *iop = ioport_addr ( \
+				(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
+#define MDC_DECLARE	MDIO_DECLARE
+
+#define MDIO_ACTIVE	(iop->pdir |=  0x40000000)
+#define MDIO_TRISTATE	(iop->pdir &= ~0x40000000)
+#define MDIO_READ	((iop->pdat &  0x40000000) != 0)
+
+#define MDIO(bit)	if(bit) iop->pdat |=  0x40000000; \
+			else	iop->pdat &= ~0x40000000
+
+#define MDC(bit)	if(bit) iop->pdat |=  0x80000000; \
+			else	iop->pdat &= ~0x80000000
+
+#define MIIDELAY	udelay(50)
+#endif	/* CONFIG_ETHER_ON_FCC */
+
+#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
+
+/*
+ *  - RX clk is CLK11
+ *  - TX clk is CLK12
+ */
+# define CONFIG_SYS_CMXSCR_VALUE1	(CMXSCR_RS1CS_CLK11  | CMXSCR_TS1CS_CLK12)
+
+#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
+
+/*
+ * - Rx-CLK is CLK13
+ * - Tx-CLK is CLK14
+ * - Select bus for bd/buffers (see 28-13)
+ * - Enable Full Duplex in FSMR
+ */
+# define CONFIG_SYS_CMXFCR_MASK2	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
+# define CONFIG_SYS_CPMFCR_RAMTYPE	0
+# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
+
+#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
+
+#define CONFIG_SHOW_BOOT_PROGRESS 1	/* boot progress enabled	*/
+
+/*
+ * Configure for RAM tests.
+ */
+#undef  CONFIG_SYS_DRAM_TEST			/* calls other tests in board.c	*/
+
+
+/*
+ * Status LED for power up status feedback.
+ */
+#define CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+
+#define STATUS_LED_PAR		im_ioport.iop_ppara
+#define STATUS_LED_DIR		im_ioport.iop_pdira
+#define STATUS_LED_ODR		im_ioport.iop_podra
+#define STATUS_LED_DAT		im_ioport.iop_pdata
+
+#define STATUS_LED_BIT		0x00000800	/* LED 0 is on PA.20	*/
+#define STATUS_LED_PERIOD	(CONFIG_SYS_HZ)
+#define STATUS_LED_STATE	STATUS_LED_OFF
+#define STATUS_LED_BIT1		0x00001000	/* LED 1 is on PA.19	*/
+#define STATUS_LED_PERIOD1	(CONFIG_SYS_HZ)
+#define STATUS_LED_STATE1	STATUS_LED_OFF
+#define STATUS_LED_BIT2		0x00002000	/* LED 2 is on PA.18	*/
+#define STATUS_LED_PERIOD2	(CONFIG_SYS_HZ/2)
+#define STATUS_LED_STATE2	STATUS_LED_ON
+
+#define STATUS_LED_ACTIVE	0		/* LED on for bit == 0	*/
+
+#define STATUS_LED_YELLOW	0
+#define STATUS_LED_GREEN	1
+#define STATUS_LED_RED		2
+#define STATUS_LED_BOOT		1
+
+
+/*
+ * Select SPI support configuration
+ */
+#define CONFIG_SOFT_SPI		/* Enable SPI driver */
+#define MAX_SPI_BYTES   4	/* Maximum number of bytes we can handle */
+#undef  DEBUG_SPI               /* Disable SPI debugging */
+
+/*
+ * Software (bit-bang) SPI driver configuration
+ */
+#ifdef CONFIG_SOFT_SPI
+
+/*
+ * Software (bit-bang) SPI driver configuration
+ */
+#define I2C_SCLK	0x00002000      /* PD 18: Shift clock */
+#define I2C_MOSI	0x00004000      /* PD 17: Master Out, Slave In */
+#define I2C_MISO	0x00008000      /* PD 16: Master In, Slave Out */
+
+#undef  SPI_INIT			/* no port initialization needed */
+#define SPI_READ        ((immr->im_ioport.iop_pdatd & I2C_MISO) != 0)
+#define SPI_SDA(bit)    do {						\
+			if(bit) immr->im_ioport.iop_pdatd |=  I2C_MOSI; \
+			else    immr->im_ioport.iop_pdatd &= ~I2C_MOSI;	\
+			} while (0)
+#define SPI_SCL(bit)    do {						\
+			if(bit) immr->im_ioport.iop_pdatd |=  I2C_SCLK; \
+			else    immr->im_ioport.iop_pdatd &= ~I2C_SCLK;	\
+			} while (0)
+#define SPI_DELAY                       /* No delay is needed */
+#endif /* CONFIG_SOFT_SPI */
+
+
+/*
+ * select I2C support configuration
+ *
+ * Supported configurations are {none, software, hardware} drivers.
+ * If the software driver is chosen, there are some additional
+ * configuration items that the driver uses to drive the port pins.
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED	400000
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0x7F
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
+#define I2C_ACTIVE	(iop->pdir |=  0x00010000)
+#define I2C_TRISTATE	(iop->pdir &= ~0x00010000)
+#define I2C_READ	((iop->pdat & 0x00010000) != 0)
+#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00010000; \
+			else    iop->pdat &= ~0x00010000
+#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00020000; \
+			else    iop->pdat &= ~0x00020000
+#define I2C_DELAY	udelay(20)	/* 1/4 I2C clock duration */
+
+/* Define this to reserve an entire FLASH sector for
+ * environment variables. Otherwise, the environment will be
+ * put in the same sector as U-Boot, and changing variables
+ * will erase U-Boot temporarily
+ */
+#define CONFIG_ENV_IN_OWN_SECT	1
+
+/* Define this to contain any number of null terminated strings that
+ * will be part of the default environment compiled into the boot image.
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+"quiet=0\0" \
+"serverip=192.168.123.205\0" \
+"ipaddr=192.168.123.203\0" \
+"checkhostname=VR8500\0" \
+"reprog="\
+    "bootp; " \
+    "tftpboot 0x140000 /bdi2000/u-boot.bin; " \
+    "protect off 60000000 6003FFFF; " \
+    "erase 60000000 6003FFFF; " \
+    "cp.b 140000 60000000 ${filesize}; " \
+    "protect on 60000000 6003FFFF\0" \
+"copyenv="\
+    "protect off 60040000 6004FFFF; " \
+    "erase 60040000 6004FFFF; " \
+    "cp.b 40040000 60040000 10000; " \
+    "protect on 60040000 6004FFFF\0" \
+"copyprog="\
+    "protect off 60000000 6003FFFF; " \
+    "erase 60000000 6003FFFF; " \
+    "cp.b 40000000 60000000 40000; " \
+    "protect on 60000000 6003FFFF\0" \
+"zapenv="\
+    "protect off 40040000 4004FFFF; " \
+    "erase 40040000 4004FFFF; " \
+    "protect on 40040000 4004FFFF\0" \
+"zapotherenv="\
+    "protect off 60040000 6004FFFF; " \
+    "erase 60040000 6004FFFF; " \
+    "protect on 60040000 6004FFFF\0" \
+"root-on-initrd="\
+    "setenv bootcmd "\
+    "version\\;" \
+    "echo\\;" \
+    "bootp\\;" \
+    "setenv bootargs root=/dev/ram0 rw quiet " \
+    "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
+    "run boot-hook\\;" \
+    "bootm\0" \
+"root-on-initrd-debug="\
+    "setenv bootcmd "\
+    "version\\;" \
+    "echo\\;" \
+    "bootp\\;" \
+    "setenv bootargs root=/dev/ram0 rw debug " \
+    "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
+    "run debug-hook\\;" \
+    "run boot-hook\\;" \
+    "bootm\0" \
+"root-on-nfs="\
+    "setenv bootcmd "\
+    "version\\;" \
+    "echo\\;" \
+    "bootp\\;" \
+    "setenv bootargs root=/dev/nfs rw quiet " \
+    "nfsroot=\\${serverip}:\\${rootpath} " \
+    "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
+    "run boot-hook\\;" \
+    "bootm\0" \
+"root-on-nfs-debug="\
+    "setenv bootcmd "\
+    "version\\;" \
+    "echo\\;" \
+    "bootp\\;" \
+    "setenv bootargs root=/dev/nfs rw debug " \
+    "nfsroot=\\${serverip}:\\${rootpath} " \
+    "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
+    "run debug-hook\\;" \
+    "run boot-hook\\;" \
+    "bootm\0" \
+"debug-checkout="\
+    "setenv checkhostname;" \
+    "setenv ethaddr 00:09:70:00:00:01;" \
+    "bootp;" \
+    "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} debug " \
+    "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
+    "run debug-hook;" \
+    "run boot-hook;" \
+    "bootm\0" \
+"debug-hook="\
+    "echo ipaddr    ${ipaddr};" \
+    "echo serverip  ${serverip};" \
+    "echo gatewayip ${gatewayip};" \
+    "echo netmask   ${netmask};" \
+    "echo hostname  ${hostname}\0" \
+"ana=run adc ; run dac\0" \
+"adc=run adc-12 ; run adc-34\0" \
+"adc-12=echo ### ADC-12 ; i2c md e 81 e\0" \
+"adc-34=echo ### ADC-34 ; i2c md f 81 e\0" \
+"dac=echo ### DAC ; i2c md 11 81 5\0" \
+"boot-hook=echo\0"
+
+/* What should the console's baud rate be? */
+#define CONFIG_BAUDRATE		9600
+
+/* Ethernet MAC address */
+#define CONFIG_ETHADDR		00:09:70:00:00:00
+
+/* The default Ethernet MAC address can be overwritten just once  */
+#ifdef  CONFIG_ETHADDR
+#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
+#endif
+
+/*
+ * Define this to do some miscellaneous board-specific initialization.
+ */
+#define CONFIG_MISC_INIT_R
+
+/* Set to a positive value to delay for running BOOTCOMMAND */
+#define CONFIG_BOOTDELAY	1	/* autoboot after 1 second */
+
+/* Be selective on what keys can delay or stop the autoboot process
+ *     To stop	use: " "
+ */
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT	"Autobooting...\n"
+#define CONFIG_AUTOBOOT_STOP_STR	" "
+#undef  CONFIG_AUTOBOOT_DELAY_STR
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define DEBUG_BOOTKEYS		0
+
+/* Define a command string that is automatically executed when no character
+ * is read on the console interface withing "Boot Delay" after reset.
+ */
+#undef	CONFIG_BOOT_ROOT_INITRD		/* Use ram disk for the root file system */
+#define	CONFIG_BOOT_ROOT_NFS		/* Use a NFS mounted root file system */
+
+#ifdef CONFIG_BOOT_ROOT_INITRD
+#define CONFIG_BOOTCOMMAND \
+	"version;" \
+	"echo;" \
+	"bootp;" \
+	"setenv bootargs root=/dev/ram0 rw quiet " \
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
+	"run boot-hook;" \
+	"bootm"
+#endif /* CONFIG_BOOT_ROOT_INITRD */
+
+#ifdef CONFIG_BOOT_ROOT_NFS
+#define CONFIG_BOOTCOMMAND \
+	"version;" \
+	"echo;" \
+	"bootp;" \
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} quiet " \
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
+	"run boot-hook;" \
+	"bootm"
+#endif /* CONFIG_BOOT_ROOT_NFS */
+
+#define CONFIG_BOOTP_RANDOM_DELAY       /* Randomize the BOOTP retry delay */
+#define CONFIG_LIB_RAND
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define  CONFIG_BOOTP_DNS
+#define  CONFIG_BOOTP_DNS2
+#define  CONFIG_BOOTP_SEND_HOSTNAME
+
+
+/* undef this to save memory */
+#define CONFIG_SYS_LONGHELP
+
+/* Monitor Command Prompt */
+
+#undef  CONFIG_SYS_HUSH_PARSER
+#ifdef  CONFIG_SYS_HUSH_PARSER
+#endif
+
+/* When CONFIG_TIMESTAMP is selected, the timestamp (date and time)
+ * of an image is printed by image commands like bootm or iminfo.
+ */
+#define CONFIG_TIMESTAMP
+
+/* If this variable is defined, an environment variable named "ver"
+ * is created by U-Boot showing the U-Boot version.
+ */
+#define CONFIG_VERSION_VARIABLE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_PING
+
+#undef CONFIG_CMD_KGDB
+
+#ifdef CONFIG_ETHER_ON_FCC
+#define CONFIG_CMD_MII
+#endif
+
+
+/* Where do the internal registers live? */
+#define CONFIG_SYS_IMMR		0xF0000000
+
+#undef	CONFIG_WATCHDOG			/* disable the watchdog */
+
+/*****************************************************************************
+ *
+ * You should not have to modify any of the following settings
+ *
+ *****************************************************************************/
+
+#define CONFIG_SACSng		1	/* munged for the SACSng */
+#define CONFIG_CPM2		1	/* Has a CPM2 */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_BOOTM_HEADER_QUIET 1        /* Suppress the image header dump    */
+					/* in the bootm command.             */
+#define CONFIG_SYS_BOOTM_PROGESS_QUIET 1       /* Suppress the progress displays,   */
+					/* "## <message>" from the bootm cmd */
+#define CONFIG_SYS_BOOTP_CHECK_HOSTNAME 1      /* If checkhostname environment is   */
+					/* defined, then the hostname param  */
+					/* validated against checkhostname.  */
+#define CONFIG_SYS_BOOTP_RETRY_COUNT 0x40000000 /* # of timeouts before giving up   */
+#define CONFIG_SYS_BOOTP_SHORT_RANDOM_DELAY 1  /* Use a short random delay value    */
+					/* (limited to maximum of 1024 msec) */
+#define CONFIG_SYS_CHK_FOR_ABORT_AT_LEAST_ONCE 1
+					/* Check for abort key presses       */
+					/* at least once in dependent of the */
+					/* CONFIG_BOOTDELAY value.           */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET 1        /* Don't print console @ startup     */
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1      /* Echo the inverted Ethernet link   */
+					/* state to the fault LED.           */
+#define CONFIG_SYS_FAULT_MII_ADDR 0x02         /* MII addr of the PHY to check for  */
+					/* the Ethernet link state.          */
+#define CONFIG_SYS_STATUS_FLASH_UNTIL_TFTP_OK 1 /* Keeping the status LED flashing  */
+					/* until the TFTP is successful.     */
+#define CONFIG_SYS_STATUS_OFF_AFTER_NETBOOT 1  /* After a successful netboot,       */
+					/* turn off the STATUS LEDs.         */
+#define CONFIG_SYS_TFTP_BLINK_STATUS_ON_DATA_IN 1 /* Blink status LED based on      */
+					/* incoming data.                    */
+#define CONFIG_SYS_TFTP_BLOCKS_PER_HASH 100    /* For every XX blocks, output a '#' */
+					/* to signify that tftp is moving.   */
+#define CONFIG_SYS_TFTP_HASHES_PER_FLASH 200   /* For every '#' hashes,             */
+					/* flash the status LED.             */
+#define CONFIG_SYS_TFTP_HASHES_PER_LINE 65     /* Only output XX '#'s per line      */
+					/* during the tftp file transfer.    */
+#define CONFIG_SYS_TFTP_PROGESS_QUIET 1        /* Suppress the progress displays    */
+					/* '#'s from the tftp command.       */
+#define CONFIG_SYS_TFTP_STATUS_QUIET 1         /* Suppress the status displays      */
+					/* issued during the tftp command.   */
+#define CONFIG_SYS_TFTP_TIMEOUT_COUNT 5        /* How many timeouts TFTP will allow */
+					/* before it gives up.               */
+
+#if defined(CONFIG_CMD_KGDB)
+#  define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	     */
+#else
+#  define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	     */
+#endif
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE	  (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
+
+#define CONFIG_SYS_MAXARGS		32	/* max number of command args	*/
+
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size	   */
+
+#define CONFIG_SYS_LOAD_ADDR		0x400000   /* default load address */
+
+#define CONFIG_SYS_ALT_MEMTEST                 /* Select full-featured memory test */
+#define CONFIG_SYS_MEMTEST_START	0x2000	/* memtest works from the end of */
+					/* the exception vector table */
+					/* to the end of the DRAM  */
+					/* less monitor and malloc area */
+#define CONFIG_SYS_STACK_USAGE		0x10000 /* Reserve 64k for the stack usage */
+#define CONFIG_SYS_MEM_END_USAGE	( CONFIG_SYS_MONITOR_LEN \
+				+ CONFIG_SYS_MALLOC_LEN \
+				+ CONFIG_ENV_SECT_SIZE \
+				+ CONFIG_SYS_STACK_USAGE )
+
+#define CONFIG_SYS_MEMTEST_END		( CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 \
+				- CONFIG_SYS_MEM_END_USAGE )
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+#define CONFIG_SYS_FLASH_BASE	CONFIG_SYS_FLASH0_BASE
+#define CONFIG_SYS_FLASH_SIZE	CONFIG_SYS_FLASH0_SIZE
+#define CONFIG_SYS_SDRAM_BASE	CONFIG_SYS_SDRAM0_BASE
+#define CONFIG_SYS_SDRAM_SIZE	CONFIG_SYS_SDRAM0_SIZE
+
+/*-----------------------------------------------------------------------
+ * Hard Reset Configuration Words
+ */
+#if defined(CONFIG_SYS_SBC_BOOT_LOW)
+#  define  CONFIG_SYS_SBC_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
+#else
+#  define  CONFIG_SYS_SBC_HRCW_BOOT_FLAGS  (0)
+#endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */
+
+/* get the HRCW ISB field from CONFIG_SYS_IMMR */
+#define CONFIG_SYS_SBC_HRCW_IMMR	( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) | \
+				  ((CONFIG_SYS_IMMR & 0x01000000) >>  7) | \
+				  ((CONFIG_SYS_IMMR & 0x00100000) >>  4) )
+
+#define CONFIG_SYS_HRCW_MASTER		( HRCW_BPS10				| \
+				  HRCW_DPPC11				| \
+				  CONFIG_SYS_SBC_HRCW_IMMR			| \
+				  HRCW_MMR00				| \
+				  HRCW_LBPC11				| \
+				  HRCW_APPC10				| \
+				  HRCW_CS10PC00				| \
+				  (CONFIG_SYS_SBC_MODCK_H & HRCW_MODCK_H1111)	| \
+				  CONFIG_SYS_SBC_HRCW_BOOT_FLAGS )
+
+/* no slaves */
+#define CONFIG_SYS_HRCW_SLAVE1		0
+#define CONFIG_SYS_HRCW_SLAVE2		0
+#define CONFIG_SYS_HRCW_SLAVE3		0
+#define CONFIG_SYS_HRCW_SLAVE4		0
+#define CONFIG_SYS_HRCW_SLAVE5		0
+#define CONFIG_SYS_HRCW_SLAVE6		0
+#define CONFIG_SYS_HRCW_SLAVE7		0
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent.
+ */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH0_BASE
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#  define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant		*/
+#undef  CONFIG_SYS_FLASH_PROTECTION		/* use hardware protection		*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	(64+4)	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	8000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	1	/* Timeout for Flash Write (in ms)	*/
+
+#ifndef CONFIG_SYS_RAMBOOT
+#  define CONFIG_ENV_IS_IN_FLASH	1
+
+#  ifdef CONFIG_ENV_IN_OWN_SECT
+#    define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#    define CONFIG_ENV_SECT_SIZE	0x10000
+#  else
+#    define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE)
+#    define CONFIG_ENV_SIZE	0x1000	/* Total Size of Environment Sector	*/
+#    define CONFIG_ENV_SECT_SIZE	0x10000 /* see README - env sect real size	*/
+#  endif /* CONFIG_ENV_IN_OWN_SECT */
+
+#else
+#  define CONFIG_ENV_IS_IN_NVRAM	1
+#  define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
+#  define CONFIG_ENV_SIZE		0x200
+#endif /* CONFIG_SYS_RAMBOOT */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPU */
+
+#if defined(CONFIG_CMD_KGDB)
+# define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * HIDx - Hardware Implementation-dependent Registers			 2-11
+ *-----------------------------------------------------------------------
+ * HID0 also contains cache control - initially enable both caches and
+ * invalidate contents, then the final state leaves only the instruction
+ * cache enabled. Note that Power-On and Hard reset invalidate the caches,
+ * but Soft reset does not.
+ *
+ * HID1 has only read-only information - nothing to set.
+ */
+#define CONFIG_SYS_HID0_INIT	(HID0_ICE  |\
+			 HID0_DCE  |\
+			 HID0_ICFI |\
+			 HID0_DCI  |\
+			 HID0_IFEM |\
+			 HID0_ABE)
+
+#define CONFIG_SYS_HID0_FINAL	(HID0_ICE  |\
+			 HID0_IFEM |\
+			 HID0_ABE  |\
+			 HID0_EMCP)
+#define CONFIG_SYS_HID2	0
+
+/*-----------------------------------------------------------------------
+ * RMR - Reset Mode Register
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RMR		0
+
+/*-----------------------------------------------------------------------
+ * BCR - Bus Configuration					 4-25
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_BCR		(BCR_ETM)
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				 4-31
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DPPC11	|\
+			 SIUMCR_L2CPC00 |\
+			 SIUMCR_APPC10	|\
+			 SIUMCR_MMR00)
+
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC |\
+			 SYPCR_BMT  |\
+			 SYPCR_PBME |\
+			 SYPCR_LBME |\
+			 SYPCR_SWRI |\
+			 SYPCR_SWP  |\
+			 SYPCR_SWE)
+#else
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC |\
+			 SYPCR_BMT  |\
+			 SYPCR_PBME |\
+			 SYPCR_LBME |\
+			 SYPCR_SWRI |\
+			 SYPCR_SWP)
+#endif /* CONFIG_WATCHDOG */
+
+/*-----------------------------------------------------------------------
+ * TMCNTSC - Time Counter Status and Control			 4-40
+ *-----------------------------------------------------------------------
+ * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
+ * and enable Time Counter
+ */
+#define CONFIG_SYS_TMCNTSC	(TMCNTSC_SEC |\
+			 TMCNTSC_ALR |\
+			 TMCNTSC_TCF |\
+			 TMCNTSC_TCE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		 4-42
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
+ * Periodic timer
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS  |\
+			 PISCR_PTF |\
+			 PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control					 9-8
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_SCCR	0
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration				13-7
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RCCR	0
+
+/*
+ * Initialize Memory Controller:
+ *
+ * Bank Bus	Machine PortSz	Device
+ * ---- ---	------- ------	------
+ *  0	60x	GPCM	16 bit	FLASH (primary flash - 2MB)
+ *  1	60x	GPCM	-- bit	(Unused)
+ *  2	60x	SDRAM	64 bit	SDRAM (DIMM)
+ *  3	60x	SDRAM	64 bit	SDRAM (DIMM)
+ *  4	60x	GPCM	-- bit	(Unused)
+ *  5	60x	GPCM	-- bit	(Unused)
+ *  6	60x	GPCM	16 bit	FLASH  (secondary flash - 2MB)
+ */
+
+/*-----------------------------------------------------------------------
+ * BR0,BR1 - Base Register
+ *     Ref: Section 10.3.1 on page 10-14
+ * OR0,OR1 - Option Register
+ *     Ref: Section 10.3.2 on page 10-18
+ *-----------------------------------------------------------------------
+ */
+
+/* Bank 0 - Primary FLASH
+ */
+
+/* BR0 is configured as follows:
+ *
+ *     - Base address of 0x40000000
+ *     - 16 bit port size
+ *     - Data errors checking is disabled
+ *     - Read and write access
+ *     - GPCM 60x bus
+ *     - Access are handled by the memory controller according to MSEL
+ *     - Not used for atomic operations
+ *     - No data pipelining is done
+ *     - Valid
+ */
+#define CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\
+			 BRx_PS_16			|\
+			 BRx_MS_GPCM_P			|\
+			 BRx_V)
+
+/* OR0 is configured as follows:
+ *
+ *     - 4 MB
+ *     - *BCTL0 is asserted upon access to the current memory bank
+ *     - *CW / *WE are negated a quarter of a clock earlier
+ *     - *CS is output at the same time as the address lines
+ *     - Uses a clock cycle length of 5
+ *     - *PSDVAL is generated internally by the memory controller
+ *	 unless *GTA is asserted earlier externally.
+ *     - Relaxed timing is generated by the GPCM for accesses
+ *	 initiated to this memory region.
+ *     - One idle clock is inserted between a read access from the
+ *	 current bank and the next access.
+ */
+#define CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE)	|\
+			 ORxG_CSNT			|\
+			 ORxG_ACS_DIV1			|\
+			 ORxG_SCY_5_CLK			|\
+			 ORxG_TRLX			|\
+			 ORxG_EHTR)
+
+/*-----------------------------------------------------------------------
+ * BR2,BR3 - Base Register
+ *     Ref: Section 10.3.1 on page 10-14
+ * OR2,OR3 - Option Register
+ *     Ref: Section 10.3.2 on page 10-16
+ *-----------------------------------------------------------------------
+ */
+
+/* Bank 2,3 - SDRAM DIMM
+ */
+
+/* The BR2 is configured as follows:
+ *
+ *     - Base address of 0x00000000
+ *     - 64 bit port size (60x bus only)
+ *     - Data errors checking is disabled
+ *     - Read and write access
+ *     - SDRAM 60x bus
+ *     - Access are handled by the memory controller according to MSEL
+ *     - Not used for atomic operations
+ *     - No data pipelining is done
+ *     - Valid
+ */
+#define CONFIG_SYS_BR2_PRELIM	((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
+			 BRx_PS_64			|\
+			 BRx_MS_SDRAM_P			|\
+			 BRx_V)
+
+#define CONFIG_SYS_BR3_PRELIM	((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
+			 BRx_PS_64			|\
+			 BRx_MS_SDRAM_P			|\
+			 BRx_V)
+
+/* With a 64 MB DIMM, the OR2 is configured as follows:
+ *
+ *     - 64 MB
+ *     - 4 internal banks per device
+ *     - Row start address bit is A8 with PSDMR[PBI] = 0
+ *     - 12 row address lines
+ *     - Back-to-back page mode
+ *     - Internal bank interleaving within save device enabled
+ */
+#if (CONFIG_SYS_SDRAM0_SIZE == 64)
+#define CONFIG_SYS_OR2_PRELIM	(MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE)	|\
+			 ORxS_BPD_4			|\
+			 ORxS_ROWST_PBI0_A8		|\
+			 ORxS_NUMR_12)
+#else
+#error "INVALID SDRAM CONFIGURATION"
+#endif
+
+/*-----------------------------------------------------------------------
+ * PSDMR - 60x Bus SDRAM Mode Register
+ *     Ref: Section 10.3.3 on page 10-21
+ *-----------------------------------------------------------------------
+ */
+
+/* Address that the DIMM SPD memory lives at.
+ */
+#define SDRAM_SPD_ADDR 0x50
+
+#if (CONFIG_SYS_SDRAM0_SIZE == 64)
+/* With a 64 MB DIMM, the PSDMR is configured as follows:
+ *
+ *     - Bank Based Interleaving,
+ *     - Refresh Enable,
+ *     - Address Multiplexing where A5 is output on A14 pin
+ *	 (A6 on A15, and so on),
+ *     - use address pins A14-A16 as bank select,
+ *     - A9 is output on SDA10 during an ACTIVATE command,
+ *     - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
+ *     - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
+ *	 is 3 clocks,
+ *     - earliest timing for READ/WRITE command after ACTIVATE command is
+ *	 2 clocks,
+ *     - earliest timing for PRECHARGE after last data was read is 1 clock,
+ *     - earliest timing for PRECHARGE after last data was written is 1 clock,
+ *     - CAS Latency is 2.
+ */
+#define CONFIG_SYS_PSDMR	(PSDMR_RFEN	      |\
+			 PSDMR_SDAM_A14_IS_A5 |\
+			 PSDMR_BSMA_A14_A16   |\
+			 PSDMR_SDA10_PBI0_A9  |\
+			 PSDMR_RFRC_7_CLK     |\
+			 PSDMR_PRETOACT_3W    |\
+			 PSDMR_ACTTORW_2W     |\
+			 PSDMR_LDOTOPRE_1C    |\
+			 PSDMR_WRC_1C	      |\
+			 PSDMR_CL_2)
+#else
+#error "INVALID SDRAM CONFIGURATION"
+#endif
+
+/*
+ * Shoot for approximately 1MHz on the prescaler.
+ */
+#if (CONFIG_8260_CLKIN >= (60 * 1000 * 1000))
+#define CONFIG_SYS_MPTPR	MPTPR_PTP_DIV64
+#elif (CONFIG_8260_CLKIN >= (30 * 1000 * 1000))
+#define CONFIG_SYS_MPTPR	MPTPR_PTP_DIV32
+#else
+#warning "Unconfigured bus clock freq: check CONFIG_SYS_MPTPR and CONFIG_SYS_PSRT are OK"
+#define CONFIG_SYS_MPTPR	MPTPR_PTP_DIV32
+#endif
+#define CONFIG_SYS_PSRT	14
+
+
+/*-----------------------------------------------------------------------
+ * BR6 - Base Register
+ *     Ref: Section 10.3.1 on page 10-14
+ * OR6 - Option Register
+ *     Ref: Section 10.3.2 on page 10-18
+ *-----------------------------------------------------------------------
+ */
+
+/* Bank 6 - Secondary FLASH
+ *
+ * The secondary FLASH is connected to *CS6
+ */
+#if (defined(CONFIG_SYS_FLASH1_BASE) && defined(CONFIG_SYS_FLASH1_SIZE))
+
+/* BR6 is configured as follows:
+ *
+ *     - Base address of 0x60000000
+ *     - 16 bit port size
+ *     - Data errors checking is disabled
+ *     - Read and write access
+ *     - GPCM 60x bus
+ *     - Access are handled by the memory controller according to MSEL
+ *     - Not used for atomic operations
+ *     - No data pipelining is done
+ *     - Valid
+ */
+#  define CONFIG_SYS_BR6_PRELIM  ((CONFIG_SYS_FLASH1_BASE & BRx_BA_MSK) |\
+			   BRx_PS_16			  |\
+			   BRx_MS_GPCM_P		  |\
+			   BRx_V)
+
+/* OR6 is configured as follows:
+ *
+ *     - 2 MB
+ *     - *BCTL0 is asserted upon access to the current memory bank
+ *     - *CW / *WE are negated a quarter of a clock earlier
+ *     - *CS is output at the same time as the address lines
+ *     - Uses a clock cycle length of 5
+ *     - *PSDVAL is generated internally by the memory controller
+ *	 unless *GTA is asserted earlier externally.
+ *     - Relaxed timing is generated by the GPCM for accesses
+ *	 initiated to this memory region.
+ *     - One idle clock is inserted between a read access from the
+ *	 current bank and the next access.
+ */
+#  define CONFIG_SYS_OR6_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH1_SIZE)  |\
+			   ORxG_CSNT		       |\
+			   ORxG_ACS_DIV1	       |\
+			   ORxG_SCY_5_CLK	       |\
+			   ORxG_TRLX		       |\
+			   ORxG_EHTR)
+#endif /* (defined(CONFIG_SYS_FLASH1_BASE) && defined(CONFIG_SYS_FLASH1_SIZE)) */
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/sama5d3_xplained.h b/qemu/roms/u-boot/include/configs/sama5d3_xplained.h
new file mode 100644
index 000000000..41c946d1e
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/sama5d3_xplained.h
@@ -0,0 +1,202 @@
+/*
+ * Configuration settings for the SAMA5D3 Xplained board.
+ *
+ * Copyright (C) 2014 Atmel Corporation
+ *		      Bo Shen <voice.shen@atmel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/hardware.h>
+
+#define CONFIG_SYS_TEXT_BASE		0x26f00000
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK      32768
+#define CONFIG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
+
+#define CONFIG_AT91FAMILY
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_OF_LIBFDT		/* Device Tree support */
+
+/* general purpose I/O */
+#define CONFIG_AT91_GPIO
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
+#define CONFIG_USART_ID			ATMEL_ID_DBGU
+
+/*
+ * This needs to be defined for the OHCI code to work but it is defined as
+ * ATMEL_ID_UHPHS in the CPU specific header files.
+ */
+#define ATMEL_ID_UHP			ATMEL_ID_UHPHS
+
+/*
+ * Specify the clock enable bit in the PMC_SCER register.
+ */
+#define ATMEL_PMC_UHP			AT91SAM926x_PMC_UHP
+
+#define CONFIG_BOOTDELAY		3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/* No NOR flash */
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_LOADS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE           ATMEL_BASE_DDRCS
+#define CONFIG_SYS_SDRAM_SIZE		0x10000000
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
+
+/* NAND flash */
+#define CONFIG_CMD_NAND
+
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+/* PMECC & PMERRLOC */
+#define CONFIG_ATMEL_NAND_HWECC
+#define CONFIG_ATMEL_NAND_HW_PMECC
+#define CONFIG_PMECC_CAP		4
+#define CONFIG_PMECC_SECTOR_SIZE	512
+#define CONFIG_CMD_NAND_TRIMFFS
+#define CONFIG_CMD_MTDPARTS
+
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#endif
+
+/* Ethernet Hardware */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_MULTI
+#define CONFIG_NET_RETRY_COUNT		20
+#define CONFIG_MACB_SEARCH_PHY
+#define CONFIG_RGMII
+#define CONFIG_CMD_MII
+#define CONFIG_PHYLIB
+
+/* MMC */
+#define CONFIG_CMD_MMC
+
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_GENERIC_ATMEL_MCI
+#define CONFIG_ATMEL_MCI_8BIT
+#endif
+
+/* USB */
+#define CONFIG_CMD_USB
+
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		ATMEL_BASE_OHCI
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"SAMA5D3 Xplained"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+#define CONFIG_DOS_PARTITION
+#define CONFIG_USB_STORAGE
+#endif
+
+#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
+#define CONFIG_CMD_FAT
+#define CONFIG_FAT_WRITE
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+#endif
+
+#define CONFIG_SYS_LOAD_ADDR			0x22000000 /* load address */
+
+#if CONFIG_SYS_USE_NANDFLASH
+/* bootstrap + u-boot + env in nandflash */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		0xc0000
+#define CONFIG_ENV_OFFSET_REDUND	0x100000
+#define CONFIG_ENV_SIZE			0x20000
+#define CONFIG_BOOTCOMMAND	"nand read 0x21000000 0x180000 0x80000;" \
+				"nand read 0x22000000 0x200000 0x600000;" \
+				"bootz 0x22000000 - 0x21000000"
+#elif CONFIG_SYS_USE_MMC
+/* bootstrap + u-boot + env in sd card */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET	0x2000
+#define CONFIG_ENV_SIZE		0x1000
+#define CONFIG_BOOTCOMMAND	"fatload mmc 0:1 0x21000000 at91-sama5d3_xplained.dtb; " \
+				"fatload mmc 0:1 0x22000000 zImage; " \
+				"bootz 0x22000000 - 0x21000000"
+#define CONFIG_SYS_MMC_ENV_DEV	0
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+#ifdef CONFIG_SYS_USE_MMC
+#define CONFIG_BOOTARGS							\
+	"console=ttyS0,115200 earlyprintk "				\
+	"root=/dev/mmcblk0p2 rw rootwait"
+#else
+#define CONFIG_BOOTARGS							\
+	"console=ttyS0,115200 earlyprintk "				\
+	"mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,"		\
+	"256K(env),256k(evn_redundent),256k(spare),"			\
+	"512k(dtb),6M(kernel)ro,-(rootfs) "				\
+	"rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs"
+#endif
+
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_SYS_PROMPT		"U-Boot> "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/sama5d3xek.h b/qemu/roms/u-boot/include/configs/sama5d3xek.h
new file mode 100644
index 000000000..516be85fe
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/sama5d3xek.h
@@ -0,0 +1,295 @@
+/*
+ * Configuation settings for the SAMA5D3xEK board.
+ *
+ * Copyright (C) 2012 - 2013 Atmel
+ *
+ * based on at91sam9m10g45ek.h by:
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/hardware.h>
+
+#define CONFIG_SYS_TEXT_BASE		0x26f00000
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK      32768
+#define CONFIG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
+
+#define CONFIG_AT91FAMILY
+#define CONFIG_ARCH_CPU_INIT
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_OF_LIBFDT		/* Device Tree support */
+
+/* general purpose I/O */
+#define CONFIG_AT91_GPIO
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
+#define	CONFIG_USART_ID			ATMEL_ID_DBGU
+
+/*
+ * This needs to be defined for the OHCI code to work but it is defined as
+ * ATMEL_ID_UHPHS in the CPU specific header files.
+ */
+#define ATMEL_ID_UHP			ATMEL_ID_UHPHS
+
+/*
+ * Specify the clock enable bit in the PMC_SCER register.
+ */
+#define ATMEL_PMC_UHP			AT91SAM926x_PMC_UHP
+
+/* LCD */
+#define CONFIG_LCD
+#define LCD_BPP				LCD_COLOR16
+#define LCD_OUTPUT_BPP                  24
+#define CONFIG_LCD_LOGO
+#define CONFIG_LCD_INFO
+#define CONFIG_LCD_INFO_BELOW_LOGO
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define CONFIG_ATMEL_HLCD
+#define CONFIG_ATMEL_LCD_RGB565
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+/* board specific (not enough SRAM) */
+#define CONFIG_SAMA5D3_LCD_BASE		0x23E00000
+
+#define CONFIG_BOOTDELAY		3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/* No NOR flash */
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_LOADS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE           ATMEL_BASE_DDRCS
+#define CONFIG_SYS_SDRAM_SIZE		0x20000000
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_INIT_SP_ADDR		0x310000
+#else
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
+#endif
+
+/* SerialFlash */
+#define CONFIG_CMD_SF
+
+#ifdef CONFIG_CMD_SF
+#define CONFIG_ATMEL_SPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_ATMEL
+#define CONFIG_SF_DEFAULT_SPEED		30000000
+#endif
+
+/* NAND flash */
+#define CONFIG_CMD_NAND
+
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+/* PMECC & PMERRLOC */
+#define CONFIG_ATMEL_NAND_HWECC
+#define CONFIG_ATMEL_NAND_HW_PMECC
+#define CONFIG_PMECC_CAP		4
+#define CONFIG_PMECC_SECTOR_SIZE	512
+#define CONFIG_CMD_NAND_TRIMFFS
+#endif
+
+/* Ethernet Hardware */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_RETRY_COUNT		20
+#define CONFIG_MACB_SEARCH_PHY
+#define CONFIG_RGMII
+#define CONFIG_CMD_MII
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9021
+
+/* MMC */
+#define CONFIG_CMD_MMC
+
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_GENERIC_ATMEL_MCI
+#define ATMEL_BASE_MMCI			ATMEL_BASE_MCI0
+#endif
+
+/* USB */
+#define CONFIG_CMD_USB
+
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		ATMEL_BASE_OHCI
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"sama5d3"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	3
+#define CONFIG_DOS_PARTITION
+#define CONFIG_USB_STORAGE
+#endif
+
+/* USB device */
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_ATMEL_USBA
+#define CONFIG_USB_ETHER
+#define CONFIG_USB_ETH_RNDIS
+#define CONFIG_USBNET_MANUFACTURER      "Atmel SAMA5D3xEK"
+
+#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
+#define CONFIG_CMD_FAT
+#endif
+
+#define CONFIG_SYS_LOAD_ADDR			0x22000000 /* load address */
+
+#ifdef CONFIG_SYS_USE_SERIALFLASH
+/* bootstrap + u-boot + env + linux in serial flash */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET       0x5000
+#define CONFIG_ENV_SIZE         0x3000
+#define CONFIG_ENV_SECT_SIZE    0x1000
+#define CONFIG_BOOTCOMMAND      "sf probe 0; " \
+				"sf read 0x22000000 0x42000 0x300000; " \
+				"bootm 0x22000000"
+#elif CONFIG_SYS_USE_NANDFLASH
+/* bootstrap + u-boot + env in nandflash */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		0xc0000
+#define CONFIG_ENV_OFFSET_REDUND	0x100000
+#define CONFIG_ENV_SIZE			0x20000
+#define CONFIG_BOOTCOMMAND	"nand read 0x21000000 0x180000 0x80000;" \
+				"nand read 0x22000000 0x200000 0x600000;" \
+				"bootm 0x22000000 - 0x21000000"
+#elif CONFIG_SYS_USE_MMC
+/* bootstrap + u-boot + env in sd card */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET	0x2000
+#define CONFIG_ENV_SIZE		0x1000
+#define CONFIG_BOOTCOMMAND	"fatload mmc 0:1 0x21000000 dtb; " \
+				"fatload mmc 0:1 0x22000000 uImage; " \
+				"bootm 0x22000000 - 0x21000000"
+#define CONFIG_SYS_MMC_ENV_DEV	0
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+#ifdef CONFIG_SYS_USE_MMC
+#define CONFIG_BOOTARGS							\
+	"console=ttyS0,115200 earlyprintk "				\
+	"root=/dev/mmcblk0p2 rw rootwait"
+#else
+#define CONFIG_BOOTARGS							\
+	"console=ttyS0,115200 earlyprintk "				\
+	"mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,"		\
+	"256K(env),256k(evn_redundent),256k(spare),"			\
+	"512k(dtb),6M(kernel)ro,-(rootfs) "				\
+	"rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs"
+#endif
+
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_SYS_PROMPT		"U-Boot> "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
+
+/* SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE		0x300000
+#define CONFIG_SPL_MAX_SIZE		0x10000
+#define CONFIG_SPL_BSS_START_ADDR	0x20000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
+#define CONFIG_SYS_SPL_MALLOC_START	0x20080000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SYS_MONITOR_LEN		(512 << 10)
+
+#ifdef CONFIG_SYS_USE_MMC
+#define CONFIG_SPL_LDSCRIPT		arch/arm/cpu/at91-common/u-boot-spl.lds
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x400
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+
+#elif CONFIG_SYS_USE_NANDFLASH
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x40000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_SIZE	0x800
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	0x20000
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0x0
+
+#elif CONFIG_SYS_USE_SERIALFLASH
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_BUS		0
+#define CONFIG_SPL_SPI_CS		0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x8400
+
+#endif
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/sandbox.h b/qemu/roms/u-boot/include/configs/sandbox.h
new file mode 100644
index 000000000..6bb2546ed
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/sandbox.h
@@ -0,0 +1,186 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifdef FTRACE
+#define CONFIG_TRACE
+#define CONFIG_CMD_TRACE
+#define CONFIG_TRACE_BUFFER_SIZE	(16 << 20)
+#define CONFIG_TRACE_EARLY_SIZE		(8 << 20)
+#define CONFIG_TRACE_EARLY
+#define CONFIG_TRACE_EARLY_ADDR		0x00100000
+
+#endif
+
+#define CONFIG_SYS_TIMER_RATE		1000000
+
+#define CONFIG_BOOTSTAGE
+#define CONFIG_BOOTSTAGE_REPORT
+#define CONFIG_DM
+#define CONFIG_CMD_DEMO
+#define CONFIG_CMD_DM
+#define CONFIG_DM_DEMO
+#define CONFIG_DM_DEMO_SIMPLE
+#define CONFIG_DM_DEMO_SHAPE
+#define CONFIG_DM_GPIO
+#define CONFIG_DM_TEST
+
+/* Number of bits in a C 'long' on this architecture */
+#define CONFIG_SANDBOX_BITS_PER_LONG	64
+
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_HOSTFILE
+#define CONFIG_OF_LIBFDT
+#define CONFIG_LMB
+#define CONFIG_FIT
+#define CONFIG_FIT_SIGNATURE
+#define CONFIG_RSA
+#define CONFIG_CMD_FDT
+#define CONFIG_DEFAULT_DEVICE_TREE	sandbox
+
+#define CONFIG_FS_FAT
+#define CONFIG_FS_EXT4
+#define CONFIG_EXT4_WRITE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+#define CONFIG_CMD_PART
+#define CONFIG_DOS_PARTITION
+#define CONFIG_HOST_MAX_DEVICES 4
+#define CONFIG_CMD_FS_GENERIC
+
+#define CONFIG_SYS_VSNPRINTF
+
+#define CONFIG_CMD_GPIO
+#define CONFIG_SANDBOX_GPIO
+#define CONFIG_SANDBOX_GPIO_COUNT	128
+
+#define CONFIG_CMD_GPT
+#define CONFIG_PARTITION_UUIDS
+#define CONFIG_EFI_PARTITION
+
+/*
+ * Size of malloc() pool, although we don't actually use this yet.
+ */
+#define CONFIG_SYS_MALLOC_LEN		(32 << 20)	/* 32MB  */
+
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_LONGHELP			/* #undef to save memory */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	16
+
+/* turn on command-line edit/c/auto */
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_COMMAND_HISTORY
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_BOOTDELAY	3
+
+#define CONFIG_ENV_SIZE		8192
+#define CONFIG_ENV_IS_NOWHERE
+
+/* SPI */
+#define CONFIG_SANDBOX_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SF_TEST
+#define CONFIG_CMD_SPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_OF_SPI
+#define CONFIG_OF_SPI_FLASH
+#define CONFIG_SPI_FLASH_SANDBOX
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_WINBOND
+
+/* Memory things - we don't really want a memory test */
+#define CONFIG_SYS_LOAD_ADDR		0x00000000
+#define CONFIG_SYS_MEMTEST_START	0x00100000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x1000)
+#define CONFIG_SYS_FDT_LOAD_ADDR	        0x100
+
+#define CONFIG_PHYSMEM
+
+/* Size of our emulated memory */
+#define CONFIG_SYS_SDRAM_BASE		0
+#define CONFIG_SYS_SDRAM_SIZE		(128 << 20)
+#define CONFIG_SYS_TEXT_BASE		0
+#define CONFIG_SYS_MONITOR_BASE	0
+#define CONFIG_NR_DRAM_BANKS		1
+
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
+					115200}
+#define CONFIG_SANDBOX_SERIAL
+
+#define CONFIG_SYS_NO_FLASH
+
+/* include default commands */
+#include <config_cmd_default.h>
+
+/* We don't have networking support yet */
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+
+#define CONFIG_CMD_HASH
+#define CONFIG_HASH_VERIFY
+#define CONFIG_SHA1
+#define CONFIG_SHA256
+
+#define CONFIG_TPM_TIS_SANDBOX
+
+#define CONFIG_CMD_SANDBOX
+
+#define CONFIG_BOOTARGS ""
+
+#define CONFIG_CROS_EC
+#define CONFIG_CMD_CROS_EC
+#define CONFIG_CROS_EC_SANDBOX
+#define CONFIG_ARCH_EARLY_INIT_R
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_SOUND
+#define CONFIG_SOUND_SANDBOX
+#define CONFIG_CMD_SOUND
+
+#ifndef SANDBOX_NO_SDL
+#define CONFIG_SANDBOX_SDL
+#endif
+
+/* LCD and keyboard require SDL support */
+#ifdef CONFIG_SANDBOX_SDL
+#define CONFIG_LCD
+#define CONFIG_VIDEO_SANDBOX_SDL
+#define CONFIG_CMD_BMP
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define LCD_BPP			LCD_COLOR16
+
+#define CONFIG_CROS_EC_KEYB
+#define CONFIG_KEYBOARD
+
+#define CONFIG_EXTRA_ENV_SETTINGS	"stdin=serial,cros-ec-keyb\0" \
+					"stdout=serial,lcd\0" \
+					"stderr=serial,lcd\0"
+#else
+
+#define CONFIG_EXTRA_ENV_SETTINGS	"stdin=serial\0" \
+					"stdout=serial,lcd\0" \
+					"stderr=serial,lcd\0"
+#endif
+
+#define CONFIG_GZIP_COMPRESSED
+#define CONFIG_BZIP2
+#define CONFIG_LZO
+#define CONFIG_LZMA
+
+#define CONFIG_TPM_TIS_SANDBOX
+
+#define CONFIG_CMD_LZMADEC
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/sansa_fuze_plus.h b/qemu/roms/u-boot/include/configs/sansa_fuze_plus.h
new file mode 100644
index 000000000..8cce34af7
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/sansa_fuze_plus.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __CONFIGS_SANSA_FUZE_PLUS_H__
+#define __CONFIGS_SANSA_FUZE_PLUS_H__
+
+/* System configurations */
+#define CONFIG_MX23				/* i.MX23 SoC */
+
+/* U-Boot Commands */
+#define CONFIG_SYS_NO_FLASH
+#include <config_cmd_default.h>
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_GPIO
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+#define CONFIG_VIDEO
+#define CONFIG_CMD_MEMTEST
+
+/* Memory configuration */
+#define CONFIG_NR_DRAM_BANKS		1		/* 1 bank of DRAM */
+#define PHYS_SDRAM_1			0x40000000	/* Base address */
+#define PHYS_SDRAM_1_SIZE		0x08000000	/* Max 128 MB RAM */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+
+/* Environment */
+#define CONFIG_ENV_SIZE			(16 * 1024)
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_OVERWRITE
+
+/* Booting Linux */
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_BOOTARGS		"console=ttyAMA0,115200n8 "
+#define CONFIG_LOADADDR		0x42000000
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+
+/* LCD */
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO_FONT_4X6
+#define CONFIG_VIDEO_MXS_MODE_SYSTEM
+#define CONFIG_SYS_BLACK_IN_WRITE
+#define LCD_BPP	LCD_COLOR16
+#endif
+
+/* USB */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_EHCI_MXS_PORT0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+
+#define CONFIG_CI_UDC		/* ChipIdea CI13xxx UDC */
+#define CONFIG_USB_GADGET_DUALSPEED
+
+#define CONFIG_USB_ETHER
+#define CONFIG_USB_ETH_CDC
+#define CONFIG_NETCONSOLE
+#endif
+
+/* The rest of the configuration is shared */
+#include <configs/mxs.h>
+
+#endif	/* __CONFIGS_SANSA_FUZE_PLUS_H__ */
diff --git a/qemu/roms/u-boot/include/configs/sbc35_a9g20.h b/qemu/roms/u-boot/include/configs/sbc35_a9g20.h
new file mode 100644
index 000000000..a1b5751d0
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/sbc35_a9g20.h
@@ -0,0 +1,170 @@
+/*
+ * Copyright (C) 2009
+ * Albin Tonnerre, Free Electrons <albin.tonnerre@free-electrons.com>
+ *
+ * Configuation settings for the Calao SBC35-A9G20 board
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* SoC type is defined in boards.cfg */
+#include <asm/hardware.h>
+#include <linux/sizes.h>
+
+#if defined(CONFIG_SYS_USE_NANDFLASH)
+#define CONFIG_ENV_IS_IN_NAND
+#else
+#define CONFIG_ENV_IS_IN_EEPROM
+#endif
+
+#define MACH_TYPE_SBC35_A9G20		1848
+#define CONFIG_MACH_TYPE		MACH_TYPE_SBC35_A9G20
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	12000000	/* 12.000 MHz crystal */
+
+#define CONFIG_ARCH_CPU_INIT
+
+#define CONFIG_CMDLINE_TAG              /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* GPIO */
+#define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
+#define CONFIG_AT91_GPIO
+
+/* Serial */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE               ATMEL_BASE_DBGU
+#define CONFIG_USART_ID                 ATMEL_ID_SYS
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_SOURCE
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_USB
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS	1
+#define CONFIG_SYS_SDRAM_BASE	ATMEL_BASE_CS1
+#define CONFIG_SYS_SDRAM_SIZE	0x04000000	/* 64 megs */
+#define CONFIG_SYS_INIT_SP_ADDR	(ATMEL_BASE_SRAM1 + 0x1000 - \
+				 GENERATED_GBL_DATA_SIZE)
+
+/* SPI EEPROM */
+#define CONFIG_SPI
+#define CONFIG_CMD_SPI
+#define CONFIG_ATMEL_SPI
+#define CONFIG_SYS_SPI_WRITE_TOUT	(5 * CONFIG_SYS_HZ)
+
+#define CONFIG_CMD_EEPROM
+#define CONFIG_SPI_M95XXX
+#define CONFIG_SYS_EEPROM_SIZE 0x10000
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
+
+/* SPI RTC */
+#define CONFIG_CMD_DATE
+#define CONFIG_RTC_M41T94
+#define CONFIG_M41T94_SPI_BUS 0
+#define CONFIG_M41T94_SPI_CS 0
+
+/* NAND flash */
+#define CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE		1
+#define CONFIG_SYS_NAND_BASE			0x40000000
+#define CONFIG_SYS_NAND_DBW_8
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PC14
+#define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PC13
+
+/* NOR flash - no real flash on this board */
+#define CONFIG_SYS_NO_FLASH			1
+
+/* Ethernet */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_RETRY_COUNT		20
+#define CONFIG_RESET_PHY_R
+#define CONFIG_MACB_SEARCH_PHY
+#define CONFIG_AT91_WANTS_COMMON_PHY
+
+/* USB */
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE	0x00500000	/* AT91SAM9260_UHP_BASE */
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"at91sam9260"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_FAT
+
+#define CONFIG_SYS_LOAD_ADDR		0x22000000	/* load address */
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		0x23e00000
+
+/* Env in EEPROM, bootstrap + u-boot in NAND*/
+#ifdef CONFIG_ENV_IS_IN_EEPROM
+#define CONFIG_ENV_OFFSET	0x20
+#define CONFIG_ENV_SIZE		0x1000
+#endif
+
+/* Env, bootstrap and u-boot in NAND */
+#ifdef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		0x60000
+#define CONFIG_ENV_OFFSET_REDUND	0x80000
+#define CONFIG_ENV_SIZE			0x20000
+#endif
+
+#define CONFIG_BOOTCOMMAND	"nboot 0x21000000 0 400000"
+#define CONFIG_BOOTARGS		"console=ttyS0,115200 " \
+				"root=/dev/mtdblock1 " \
+				"mtdparts=atmel_nand:16M(kernel)ro," \
+				"120M(rootfs),-(other) " \
+				"rw rootfstype=jffs2"
+
+
+#define CONFIG_SYS_PROMPT	"U-Boot> "
+#define CONFIG_SYS_CBSIZE	256
+#define CONFIG_SYS_MAXARGS	16
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP	1
+#define CONFIG_CMDLINE_EDITING	1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN	ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/sbc405.h b/qemu/roms/u-boot/include/configs/sbc405.h
new file mode 100644
index 000000000..69dc21091
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/sbc405.h
@@ -0,0 +1,255 @@
+/*
+ * (C) Copyright 2001
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_SBC405		1	/* ...on a WR SBC405 board	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
+
+#define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll	*/
+
+#define CONFIG_BAUDRATE		9600
+
+#define CONFIG_PREBOOT	"echo;echo Welcome to U-Boot for the sbc405;echo;echo Type \"? or help\" to get on-line help;echo"
+
+#define CONFIG_RAMBOOT								\
+	"setenv bootargs root=/dev/ram rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"	\
+	"bootm ffc00000 ffca0000"
+#define CONFIG_NFSBOOT								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"	\
+	"bootm ffc00000"
+
+#undef CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND      "version;echo;tftpboot ${loadaddr} ${loadfile};bootvx"      /* autoboot command     */
+
+
+#define CONFIG_PPC4xx_EMAC
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_PHY_RESET_DELAY	300	/* Intel LXT971A needs this	*/
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"bootargs=emac(0,0)host:/T221ppc/target/config/sbc405/vxWorks.st " \
+		"e=192.168.193.102:ffffffe0 h=192.168.193.100 u=target pw=hello " \
+		"f=0x08 tn=sbc405 o=emac \0" \
+	"env_startaddr=FF000000\0" \
+	"env_endaddr=FF03FFFF\0" \
+	"loadfile=vxWorks.st\0" \
+	"loadaddr=0x01000000\0" \
+	"net_load=tftpboot ${loadaddr} ${loadfile}\0" \
+	"uboot_startaddr=FFFC0000\0" \
+	"uboot_endaddr=FFFFFFFF\0" \
+	"update=tftp ${loadaddr} u-boot.bin;" \
+		"protect off ${uboot_startaddr} ${uboot_endaddr};" \
+		"era ${uboot_startaddr} ${uboot_endaddr};" \
+		"cp.b ${loadaddr} ${uboot_startaddr} ${filesize};" \
+		"protect on ${uboot_startaddr} ${uboot_endaddr}\0" \
+	"zapenv=protect off ${env_startaddr} ${env_endaddr};" \
+		"era ${env_startaddr} ${env_endaddr};" \
+		"protect on ${env_startaddr} ${env_endaddr}\0"
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+#define CONFIG_ENV_OVERWRITE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SDRAM
+
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
+
+#define CONFIG_ETHADDR	DE:AD:BE:EF:01:01	/* Ethernet address	*/
+#define CONFIG_IPADDR		192.168.193.102
+#define CONFIG_NETMASK		255.255.255.224
+#define CONFIG_SERVERIP		192.168.193.119
+#define CONFIG_GATEWAYIP	192.168.193.97
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+
+#undef CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+
+#undef CONFIG_SYS_EXT_SERIAL_CLOCK		/* no external serial clock used */
+#define CONFIG_SYS_BASE_BAUD		691200
+
+/* The following table includes the supported baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE					\
+	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,	\
+	 57600, 115200, 230400, 460800, 921600 }
+
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_info (bd_t) */
+
+#define CONFIG_VERSION_VARIABLE	1	/* include version env variable */
+
+#define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
+
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER	0	/* configure as pci adapter	*/
+#define PCI_HOST_FORCE		1	/* configure as pci host	*/
+#define PCI_HOST_AUTO		2	/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_HOST	PCI_HOST_FORCE	/* select pci host function	*/
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+					/* resource configuration	*/
+
+#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID	0x12FE	/* PCI Vendor ID: esd gmbh	*/
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID	0x0408	/* PCI Device ID: PMC-405	*/
+#define CONFIG_SYS_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
+#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CONFIG_SYS_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
+#define CONFIG_SYS_PCI_PTM1PCI	0x00000000	/* Host: use this pci address	*/
+#define CONFIG_SYS_PCI_PTM2LA	0xffc00000	/* point to flash		*/
+#define CONFIG_SYS_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
+#define CONFIG_SYS_PCI_PTM2PCI	0x04000000	/* Host: use this pci address	*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_MONITOR_BASE	0xFFFC0000
+#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN	(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_FLASH_BASE		0xFF000000
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant		*/
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Flash Erase Timeout (in ms)		*/
+#define CONFIG_SYS_FLASH_INCREMENT	0x01000000
+#undef CONFIG_SYS_FLASH_PROTECTION		/* don't use hardware protection	*/
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)		*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
+
+/*-----------------------------------------------------------------------
+ * Environment Variable setup
+ */
+#define CONFIG_ENV_ADDR	CONFIG_SYS_FLASH_BASE	/* starting right at the beginning	*/
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_OFFSET		0	/* starting right at the beginning	*/
+#define CONFIG_ENV_SECT_SIZE	0x40000	/* see README - env sector total size	*/
+#define CONFIG_ENV_SIZE		0x40000	/* Total Size of Environment Sector	*/
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+#define FLASH0_BA	CONFIG_SYS_FLASH_BASE		/* FLASH 0 Base Address		*/
+
+/* Memory Bank 0 (Flash Bank 0) initialization					*/
+#define CONFIG_SYS_EBC_PB0AP	0x92015480
+#define CONFIG_SYS_EBC_PB0CR	FLASH0_BA | 0x9C000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=32bit*/
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+
+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
+#define CONFIG_SYS_TEMP_STACK_OCM	1
+
+/* On Chip Memory location */
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Definitions for Serial Presence Detect EEPROM address
+ * (to get SDRAM settings)
+ */
+#define SPD_EEPROM_ADDRESS	0x50
+#define CONFIG_SPD_EEPROM	1	/* use SPD EEPROM for setup		*/
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/sbc8349.h b/qemu/roms/u-boot/include/configs/sbc8349.h
new file mode 100644
index 000000000..2516a3e97
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/sbc8349.h
@@ -0,0 +1,713 @@
+/*
+ * WindRiver SBC8349 U-Boot configuration file.
+ * Copyright (c) 2006, 2007 Wind River Systems, Inc.
+ *
+ * Paul Gortmaker <paul.gortmaker@windriver.com>
+ * Based on the MPC8349EMDS config.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * sbc8349 board configuration file.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1	/* E300 Family */
+#define CONFIG_MPC834x		1	/* MPC834x family */
+#define CONFIG_MPC8349		1	/* MPC8349 specific */
+#define CONFIG_SBC8349		1	/* WRS SBC8349 board specific */
+
+#define	CONFIG_SYS_TEXT_BASE	0xFF800000
+
+/* Don't enable PCI2 on sbc834x - it doesn't exist physically. */
+#undef CONFIG_MPC83XX_PCI2		/* support for 2nd PCI controller */
+
+/*
+ * The default if PCI isn't enabled, or if no PCI clk setting is given
+ * is 66MHz; this is what the board defaults to when the PCI slot is
+ * physically empty.  The board will automatically (i.e w/o jumpers)
+ * clock down to 33MHz if you insert a 33MHz PCI card.
+ */
+#ifdef CONFIG_PCI_33M
+#define CONFIG_83XX_CLKIN	33000000	/* in Hz */
+#else	/* 66M */
+#define CONFIG_83XX_CLKIN	66000000	/* in Hz */
+#endif
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#ifdef CONFIG_PCI_33M
+#define CONFIG_SYS_CLK_FREQ	33000000
+#define HRCWL_CSB_TO_CLKIN	HRCWL_CSB_TO_CLKIN_8X1
+#else	/* 66M */
+#define CONFIG_SYS_CLK_FREQ	66000000
+#define HRCWL_CSB_TO_CLKIN	HRCWL_CSB_TO_CLKIN_4X1
+#endif
+#endif
+
+#undef CONFIG_BOARD_EARLY_INIT_F		/* call board_pre_init */
+
+#define CONFIG_SYS_IMMR		0xE0000000
+
+#undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
+#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00100000
+
+/*
+ * DDR Setup
+ */
+#undef CONFIG_DDR_ECC			/* only for ECC DDR module */
+#undef CONFIG_DDR_ECC_CMD		/* use DDR ECC user commands */
+#define CONFIG_SPD_EEPROM		/* use SPD EEPROM for DDR setup*/
+#define CONFIG_SYS_83XX_DDR_USES_CS0	/* WRS; Fsl board uses CS2/CS3 */
+
+/*
+ * 32-bit data path mode.
+ *
+ * Please note that using this mode for devices with the real density of 64-bit
+ * effectively reduces the amount of available memory due to the effect of
+ * wrapping around while translating address to row/columns, for example in the
+ * 256MB module the upper 128MB get aliased with contents of the lower
+ * 128MB); normally this define should be used for devices with real 32-bit
+ * data path.
+ */
+#undef CONFIG_DDR_32BIT
+
+#define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
+				DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
+#define CONFIG_DDR_2T_TIMING
+
+#if defined(CONFIG_SPD_EEPROM)
+/*
+ * Determine DDR configuration from I2C interface.
+ */
+#define SPD_EEPROM_ADDRESS	0x52		/* DDR DIMM */
+
+#else
+/*
+ * Manually set up DDR parameters
+ * NB: manual DDR setup untested on sbc834x
+ */
+#define CONFIG_SYS_DDR_SIZE		256		/* MB */
+#define CONFIG_SYS_DDR_CS2_CONFIG	(CSCONFIG_EN \
+					| CSCONFIG_ROW_BIT_13 \
+					| CSCONFIG_COL_BIT_10)
+#define CONFIG_SYS_DDR_TIMING_1	0x36332321
+#define CONFIG_SYS_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
+#define CONFIG_SYS_DDR_CONTROL	0xc2000000	/* unbuffered,no DYN_PWR */
+#define CONFIG_SYS_DDR_INTERVAL	0x04060100	/* autocharge,no open page */
+
+#if defined(CONFIG_DDR_32BIT)
+/* set burst length to 8 for 32-bit data path */
+				/* DLL,normal,seq,4/2.5, 8 burst len */
+#define CONFIG_SYS_DDR_MODE	0x00000023
+#else
+/* the default burst length is 4 - for 64-bit data path */
+				/* DLL,normal,seq,4/2.5, 4 burst len */
+#define CONFIG_SYS_DDR_MODE	0x00000022
+#endif
+#endif
+
+/*
+ * SDRAM on the Local Bus
+ */
+#define CONFIG_SYS_LBC_SDRAM_BASE	0xF0000000	/* Localbus SDRAM */
+#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
+#define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
+#define CONFIG_SYS_FLASH_BASE		0xFF800000	/* start of FLASH   */
+#define CONFIG_SYS_FLASH_SIZE		8		/* flash size in MB */
+/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
+
+#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE \
+					| BR_PS_16	/* 16 bit port */ \
+					| BR_MS_GPCM	/* MSEL = GPCM */ \
+					| BR_V)		/* valid */
+
+#define CONFIG_SYS_OR0_PRELIM		(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+					| OR_GPCM_XAM \
+					| OR_GPCM_CSNT \
+					| OR_GPCM_ACS_DIV2 \
+					| OR_GPCM_XACS \
+					| OR_GPCM_SCY_15 \
+					| OR_GPCM_TRLX_SET \
+					| OR_GPCM_EHTR_SET \
+					| OR_GPCM_EAD)
+					/* 0xFF806FF7 */
+
+					/* window base at flash base */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_8MB)
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	64	/* sectors per device */
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef  CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+					/* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000
+					/* Size of used area in RAM*/
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)	/* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN	(256 * 1024)	/* Reserved for malloc */
+
+/*
+ * Local Bus LCRR and LBCR regs
+ *    LCRR:  DLL bypass, Clock divider is 4
+ * External Local Bus rate is
+ *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
+ */
+#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_4
+#define CONFIG_SYS_LBC_LBCR	0x00000000
+
+#undef CONFIG_SYS_LB_SDRAM	/* if board has SDRAM on local bus */
+
+#ifdef CONFIG_SYS_LB_SDRAM
+/* Local bus BR2, OR2 definition for SDRAM if soldered on the board*/
+/*
+ * Base Register 2 and Option Register 2 configure SDRAM.
+ * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
+ *
+ * For BR2, need:
+ *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
+ *    port-size = 32-bits = BR2[19:20] = 11
+ *    no parity checking = BR2[21:22] = 00
+ *    SDRAM for MSEL = BR2[24:26] = 011
+ *    Valid = BR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
+ */
+
+#define CONFIG_SYS_BR2_PRELIM		(CONFIG_SYS_LBC_SDRAM_BASE \
+					| BR_PS_32 \
+					| BR_MS_SDRAM \
+					| BR_V)
+					/* 0xF0001861 */
+#define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_LBC_SDRAM_BASE
+#define CONFIG_SYS_LBLAWAR2_PRELIM	(LBLAWAR_EN | LBLAWAR_64MB)
+
+/*
+ * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
+ *
+ * For OR2, need:
+ *    64MB mask for AM, OR2[0:7] = 1111 1100
+ *                 XAM, OR2[17:18] = 11
+ *    9 columns OR2[19-21] = 010
+ *    13 rows   OR2[23-25] = 100
+ *    EAD set for extra time OR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
+ */
+
+#define CONFIG_SYS_OR2_PRELIM	(MEG_TO_AM(CONFIG_SYS_LBC_SDRAM_SIZE) \
+			| OR_SDRAM_XAM \
+			| ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
+			| ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
+			| OR_SDRAM_EAD)
+			/* 0xFC006901 */
+
+				/* LB sdram refresh timer, about 6us */
+#define CONFIG_SYS_LBC_LSRT	0x32000000
+				/* LB refresh timer prescal, 266MHz/32 */
+#define CONFIG_SYS_LBC_MRTPR	0x20000000
+
+#define CONFIG_SYS_LBC_LSDMR_COMMON	(LSDMR_RFEN \
+					| LSDMR_BSMA1516 \
+					| LSDMR_RFCR8 \
+					| LSDMR_PRETOACT6 \
+					| LSDMR_ACTTORW3 \
+					| LSDMR_BL8 \
+					| LSDMR_WRC3 \
+					| LSDMR_CL3)
+
+/*
+ * SDRAM Controller configuration sequence.
+ */
+#define CONFIG_SYS_LBC_LSDMR_1	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
+#define CONFIG_SYS_LBC_LSDMR_2	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_3	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_4	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
+#define CONFIG_SYS_LBC_LSDMR_5	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
+#endif
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX     1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE    1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_IMMR+0x4500)
+#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_IMMR+0x4600)
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_AUTO_COMPLETE		/* add autocompletion support   */
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69}, {1, 0x69} }
+/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
+
+/* TSEC */
+#define CONFIG_SYS_TSEC1_OFFSET 0x24000
+#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
+#define CONFIG_SYS_TSEC2_OFFSET 0x25000
+#define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
+#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS		0xE2000000
+#define CONFIG_SYS_PCI1_IO_SIZE		0x00100000	/* 1M */
+
+#define CONFIG_SYS_PCI2_MEM_BASE	0xA0000000
+#define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BASE
+#define CONFIG_SYS_PCI2_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI2_MMIO_BASE	0xB0000000
+#define CONFIG_SYS_PCI2_MMIO_PHYS	CONFIG_SYS_PCI2_MMIO_BASE
+#define CONFIG_SYS_PCI2_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI2_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI2_IO_PHYS		0xE2100000
+#define CONFIG_SYS_PCI2_IO_SIZE		0x00100000	/* 1M */
+
+#if defined(CONFIG_PCI)
+
+#define PCI_64BIT
+#define PCI_ONE_PCI1
+#if defined(PCI_64BIT)
+#undef PCI_ALL_PCI1
+#undef PCI_TWO_PCI1
+#undef PCI_ONE_PCI1
+#endif
+
+#define CONFIG_PCI_PNP		/* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+	#define PCI_ENET0_IOADDR	0xFIXME
+	#define PCI_ENET0_MEMADDR	0xFIXME
+	#define PCI_IDSEL_NUMBER	0xFIXME
+#endif
+
+#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
+
+#endif	/* CONFIG_PCI */
+
+/*
+ * TSEC configuration
+ */
+#define CONFIG_TSEC_ENET		/* TSEC ethernet support */
+
+#if defined(CONFIG_TSEC_ENET)
+
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"TSEC1"
+#define CONFIG_PHY_BCM5421S	1
+#define TSEC1_PHY_ADDR		0x19
+#define TSEC2_PHY_ADDR		0x1a
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME		"TSEC0"
+
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#ifndef CONFIG_SYS_RAMBOOT
+	#define CONFIG_ENV_IS_IN_FLASH	1
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
+	#define CONFIG_ENV_SECT_SIZE	0x20000	/* 128K(one sector) for env */
+	#define CONFIG_ENV_SIZE		0x2000
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+#else
+	#define CONFIG_SYS_NO_FLASH	1	/* Flash is not usable now */
+	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
+	#define CONFIG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+
+#if defined(CONFIG_PCI)
+    #define CONFIG_CMD_PCI
+#endif
+
+#if defined(CONFIG_SYS_RAMBOOT)
+    #undef CONFIG_CMD_SAVEENV
+    #undef CONFIG_CMD_LOADS
+#endif
+
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+#if defined(CONFIG_CMD_KGDB)
+	#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
+#else
+	#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
+#endif
+
+				/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+				/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+				/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)
+
+#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
+
+#if 1 /*528/264*/
+#define CONFIG_SYS_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_1X1 |\
+	HRCWL_CSB_TO_CLKIN |\
+	HRCWL_VCO_1X2 |\
+	HRCWL_CORE_TO_CSB_2X1)
+#elif 0 /*396/132*/
+#define CONFIG_SYS_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_1X1 |\
+	HRCWL_CSB_TO_CLKIN |\
+	HRCWL_VCO_1X4 |\
+	HRCWL_CORE_TO_CSB_3X1)
+#elif 0 /*264/132*/
+#define CONFIG_SYS_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_1X1 |\
+	HRCWL_CSB_TO_CLKIN |\
+	HRCWL_VCO_1X4 |\
+	HRCWL_CORE_TO_CSB_2X1)
+#elif 0 /*132/132*/
+#define CONFIG_SYS_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_1X1 |\
+	HRCWL_CSB_TO_CLKIN |\
+	HRCWL_VCO_1X4 |\
+	HRCWL_CORE_TO_CSB_1X1)
+#elif 0 /*264/264 */
+#define CONFIG_SYS_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_1X1 |\
+	HRCWL_CSB_TO_CLKIN |\
+	HRCWL_VCO_1X4 |\
+	HRCWL_CORE_TO_CSB_1X1)
+#endif
+
+#if defined(PCI_64BIT)
+#define CONFIG_SYS_HRCW_HIGH (\
+	HRCWH_PCI_HOST |\
+	HRCWH_64_BIT_PCI |\
+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_PCI2_ARBITER_DISABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0X00000100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_TSEC1M_IN_GMII |\
+	HRCWH_TSEC2M_IN_GMII)
+#else
+#define CONFIG_SYS_HRCW_HIGH (\
+	HRCWH_PCI_HOST |\
+	HRCWH_32_BIT_PCI |\
+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_PCI2_ARBITER_ENABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0X00000100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_TSEC1M_IN_GMII |\
+	HRCWH_TSEC2M_IN_GMII)
+#endif
+
+/* System IO Config */
+#define CONFIG_SYS_SICRH 0
+#define CONFIG_SYS_SICRL SICRL_LDP_A
+
+#define CONFIG_SYS_HID0_INIT	0x000000000
+#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK \
+				| HID0_ENABLE_INSTRUCTION_CACHE)
+
+/* #define CONFIG_SYS_HID0_FINAL	(\
+	HID0_ENABLE_INSTRUCTION_CACHE |\
+	HID0_ENABLE_M_BIT |\
+	HID0_ENABLE_ADDRESS_BROADCAST) */
+
+
+#define CONFIG_SYS_HID2 HID2_HBE
+
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
+/* DDR @ 0x00000000 */
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE \
+				| BATL_PP_RW \
+				| BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+
+/* PCI @ 0x80000000 */
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_BASE \
+				| BATL_PP_RW \
+				| BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_PCI1_MEM_BASE \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_MMIO_BASE \
+				| BATL_PP_RW \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PCI1_MMIO_BASE \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+#else
+#define CONFIG_SYS_IBAT1L	(0)
+#define CONFIG_SYS_IBAT1U	(0)
+#define CONFIG_SYS_IBAT2L	(0)
+#define CONFIG_SYS_IBAT2U	(0)
+#endif
+
+#ifdef CONFIG_MPC83XX_PCI2
+#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_PCI2_MEM_BASE \
+				| BATL_PP_RW \
+				| BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_PCI2_MEM_BASE \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCI2_MMIO_BASE \
+				| BATL_PP_RW \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_PCI2_MMIO_BASE \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+#else
+#define CONFIG_SYS_IBAT3L	(0)
+#define CONFIG_SYS_IBAT3U	(0)
+#define CONFIG_SYS_IBAT4L	(0)
+#define CONFIG_SYS_IBAT4U	(0)
+#endif
+
+/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
+#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_IMMR \
+				| BATL_PP_RW \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_IMMR \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+
+/* LBC SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
+#define CONFIG_SYS_IBAT6L	(CONFIG_SYS_LBC_SDRAM_BASE \
+				| BATL_PP_RW \
+				| BATL_MEMCOHERENCE \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT6U	(CONFIG_SYS_LBC_SDRAM_BASE \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+
+#define CONFIG_SYS_IBAT7L	(0)
+#define CONFIG_SYS_IBAT7U	(0)
+
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
+#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
+#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
+#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
+#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#endif
+
+#define CONFIG_HOSTNAME		SBC8349
+#define CONFIG_ROOTPATH		"/tftpboot/rootfs"
+#define CONFIG_BOOTFILE		"uImage"
+
+				/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		800000
+
+#define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE	 115200
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"hostname=sbc8349\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"	\
+		"bootm\0"						\
+	"load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0"		\
+	"update=protect off ff800000 ff83ffff; "			\
+		"era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \
+	"upd=run load update\0"						\
+	"fdtaddr=780000\0"						\
+	"fdtfile=sbc8349.dtb\0"						\
+	""
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv bootargs root=/dev/nfs rw "				\
+		"nfsroot=$serverip:$rootpath "				\
+		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"	\
+							"$netdev:off "	\
+		"console=$consoledev,$baudrate $othbootargs;"		\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+	"setenv bootargs root=/dev/ram rw "				\
+		"console=$consoledev,$baudrate $othbootargs;"		\
+	"tftp $ramdiskaddr $ramdiskfile;"				\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/sbc8548.h b/qemu/roms/u-boot/include/configs/sbc8548.h
new file mode 100644
index 000000000..f28f350fc
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/sbc8548.h
@@ -0,0 +1,644 @@
+/*
+ * Copyright 2007,2009 Wind River Systems <www.windriver.com>
+ * Copyright 2007 Embedded Specialties, Inc.
+ * Copyright 2004, 2007 Freescale Semiconductor.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * sbc8548 board configuration file
+ * Please refer to doc/README.sbc8548 for more info.
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Top level Makefile configuration choices
+ */
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_PCI1
+#endif
+
+#ifdef CONFIG_66
+#define CONFIG_SYS_CLK_DIV 1
+#endif
+
+#ifdef CONFIG_33
+#define CONFIG_SYS_CLK_DIV 2
+#endif
+
+#ifdef CONFIG_PCIE
+#define CONFIG_PCIE1
+#endif
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_BOOKE		1	/* BOOKE */
+#define CONFIG_E500		1	/* BOOKE e500 family */
+#define CONFIG_MPC8548		1	/* MPC8548 specific */
+#define CONFIG_SBC8548		1	/* SBC8548 board specific */
+
+/*
+ * If you want to boot from the SODIMM flash, instead of the soldered
+ * on flash, set this, and change JP12, SW2:8 accordingly.
+ */
+#undef CONFIG_SYS_ALT_BOOT
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#ifdef CONFIG_SYS_ALT_BOOT
+#define CONFIG_SYS_TEXT_BASE	0xfff00000
+#else
+#define CONFIG_SYS_TEXT_BASE	0xfffa0000
+#endif
+#endif
+
+#undef CONFIG_RIO
+
+#ifdef CONFIG_PCI
+#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT    1	/* enable 64-bit PCI resources */
+#endif
+#ifdef CONFIG_PCIE1
+#define CONFIG_FSL_PCIE_RESET   1	/* need PCIe reset errata */
+#endif
+
+#define CONFIG_TSEC_ENET		/* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */
+
+#define CONFIG_FSL_LAW		1	/* Use common FSL init code */
+
+/*
+ * Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4]
+ */
+#ifndef CONFIG_SYS_CLK_DIV
+#define CONFIG_SYS_CLK_DIV	1	/* 2, if 33MHz PCI card installed */
+#endif
+#define CONFIG_SYS_CLK_FREQ	(66000000 / CONFIG_SYS_CLK_DIV)
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* toggle branch predition */
+
+/*
+ * Only possible on E500 Version 2 or newer cores.
+ */
+#define CONFIG_ENABLE_36BIT_PHYS	1
+
+#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
+
+#undef	CONFIG_SYS_DRAM_TEST			/* memory test, takes time */
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+
+#define CONFIG_SYS_CCSRBAR		0xe0000000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+
+/* DDR Setup */
+#define CONFIG_SYS_FSL_DDR2
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#undef CONFIG_DDR_ECC			/* only for ECC DDR module */
+/*
+ * A hardware errata caused the LBC SDRAM SPD and the DDR2 SPD
+ * to collide, meaning you couldn't reliably read either. So
+ * physically remove the LBC PC100 SDRAM module from the board
+ * before enabling the two SPD options below, or check that you
+ * have the hardware fix on your board via "i2c probe" and looking
+ * for a device at 0x53.
+ */
+#undef CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
+#undef CONFIG_DDR_SPD
+
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
+
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	2
+
+/*
+ * The hardware fix for the I2C address collision puts the DDR
+ * SPD at 0x53, but if we are running on an older board w/o the
+ * fix, it will still be at 0x51.  We check 0x53 1st.
+ */
+#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
+#define ALT_SPD_EEPROM_ADDRESS	0x53	/* CTLR 0 DIMM 0 */
+
+/*
+ * Make sure required options are set
+ */
+#ifndef CONFIG_SPD_EEPROM
+	#define CONFIG_SYS_SDRAM_SIZE	256		/* DDR is 256MB */
+	#define CONFIG_SYS_DDR_CONTROL	0xc300c000
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+/*
+ * FLASH on the Local Bus
+ * Two banks, one 8MB the other 64MB, using the CFI driver.
+ * JP12+SW2.8 are used to swap CS0 and CS6, defaults are to have
+ * CS0 the 8MB boot flash, and CS6 the 64MB flash.
+ *
+ *	Default:
+ *	ec00_0000	efff_ffff	64MB SODIMM
+ *	ff80_0000	ffff_ffff	8MB soldered flash
+ *
+ *	Alternate:
+ *	ef80_0000	efff_ffff	8MB soldered flash
+ *	fc00_0000	ffff_ffff	64MB SODIMM
+ *
+ * BR0_8M:
+ *    Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0
+ *    Port Size = 8 bits = BRx[19:20] = 01
+ *    Use GPCM = BRx[24:26] = 000
+ *    Valid = BRx[31] = 1
+ *
+ * BR0_64M:
+ *    Base address 0 = 0xfc00_0000 = BR0[0:16] = 1111 1100 0000 0000 0
+ *    Port Size = 32 bits = BRx[19:20] = 11
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801    BR0_8M
+ * 1111 1100 0000 0000 0001 1000 0000 0001 = fc001801    BR0_64M
+ */
+#define CONFIG_SYS_BR0_8M	0xff800801
+#define CONFIG_SYS_BR0_64M	0xfc001801
+
+/*
+ * BR6_8M:
+ *    Base address 6 = 0xef80_0000 = BR6[0:16] = 1110 1111 1000 0000 0
+ *    Port Size = 8 bits = BRx[19:20] = 01
+ *    Use GPCM = BRx[24:26] = 000
+ *    Valid = BRx[31] = 1
+
+ * BR6_64M:
+ *    Base address 6 = 0xec00_0000 = BR6[0:16] = 1110 1100 0000 0000 0
+ *    Port Size = 32 bits = BRx[19:20] = 11
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1110 1111 1000 0000 0000 1000 0000 0001 = ef800801    BR6_8M
+ * 1110 1100 0000 0000 0001 1000 0000 0001 = ec001801    BR6_64M
+ */
+#define CONFIG_SYS_BR6_8M	0xef800801
+#define CONFIG_SYS_BR6_64M	0xec001801
+
+/*
+ * OR0_8M:
+ *    Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0
+ *    XAM = OR0[17:18] = 11
+ *    CSNT = OR0[20] = 1
+ *    ACS = half cycle delay = OR0[21:22] = 11
+ *    SCY = 6 = OR0[24:27] = 0110
+ *    TRLX = use relaxed timing = OR0[29] = 1
+ *    EAD = use external address latch delay = OR0[31] = 1
+ *
+ * OR0_64M:
+ *    Addr Mask = 64M = OR1[0:16] = 1111 1100 0000 0000 0
+ *
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    OR0_8M
+ * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65    OR0_64M
+ */
+#define CONFIG_SYS_OR0_8M	0xff806e65
+#define CONFIG_SYS_OR0_64M	0xfc006e65
+
+/*
+ * OR6_8M:
+ *    Addr Mask = 8M = OR6[0:16] = 1111 1111 1000 0000 0
+ *    XAM = OR6[17:18] = 11
+ *    CSNT = OR6[20] = 1
+ *    ACS = half cycle delay = OR6[21:22] = 11
+ *    SCY = 6 = OR6[24:27] = 0110
+ *    TRLX = use relaxed timing = OR6[29] = 1
+ *    EAD = use external address latch delay = OR6[31] = 1
+ *
+ * OR6_64M:
+ *    Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    OR6_8M
+ * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65    OR6_64M
+ */
+#define CONFIG_SYS_OR6_8M	0xff806e65
+#define CONFIG_SYS_OR6_64M	0xfc006e65
+
+#ifndef CONFIG_SYS_ALT_BOOT		/* JP12 in default position */
+#define CONFIG_SYS_BOOT_BLOCK		0xff800000	/* start of 8MB Flash */
+#define CONFIG_SYS_ALT_FLASH		0xec000000	/* 64MB "user" flash */
+
+#define CONFIG_SYS_BR0_PRELIM		CONFIG_SYS_BR0_8M
+#define CONFIG_SYS_OR0_PRELIM		CONFIG_SYS_OR0_8M
+
+#define CONFIG_SYS_BR6_PRELIM		CONFIG_SYS_BR6_64M
+#define CONFIG_SYS_OR6_PRELIM		CONFIG_SYS_OR6_64M
+#else					/* JP12 in alternate position */
+#define CONFIG_SYS_BOOT_BLOCK		0xfc000000	/* start 64MB Flash */
+#define CONFIG_SYS_ALT_FLASH		0xef800000	/* 8MB soldered flash */
+
+#define CONFIG_SYS_BR0_PRELIM		CONFIG_SYS_BR0_64M
+#define CONFIG_SYS_OR0_PRELIM		CONFIG_SYS_OR0_64M
+
+#define CONFIG_SYS_BR6_PRELIM		CONFIG_SYS_BR6_8M
+#define CONFIG_SYS_OR6_PRELIM		CONFIG_SYS_OR6_8M
+#endif
+
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_BOOT_BLOCK
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE, \
+					 CONFIG_SYS_ALT_FLASH}
+#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	256		/* sectors per device */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+/* CS5 = Local bus peripherals controlled by the EPLD */
+
+#define CONFIG_SYS_BR5_PRELIM		0xf8000801
+#define CONFIG_SYS_OR5_PRELIM		0xff006e65
+#define CONFIG_SYS_EPLD_BASE		0xf8000000
+#define CONFIG_SYS_LED_DISP_BASE	0xf8000000
+#define CONFIG_SYS_USER_SWITCHES_BASE	0xf8100000
+#define CONFIG_SYS_BD_REV		0xf8300000
+#define CONFIG_SYS_EEPROM_BASE		0xf8b00000
+
+/*
+ * SDRAM on the Local Bus (CS3 and CS4)
+ * Note that most boards have a hardware errata where both the
+ * LBC SDRAM and the DDR2 SDRAM decode at 0x51, making it impossible
+ * to use CONFIG_DDR_SPD unless you physically remove the LBC DIMM.
+ * A hardware workaround is also available, see README.sbc8548 file.
+ */
+#define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
+#define CONFIG_SYS_LBC_SDRAM_SIZE	128		/* LBC SDRAM is 128MB */
+
+/*
+ * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM.
+ * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
+ *
+ * For BR3, need:
+ *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
+ *    port-size = 32-bits = BR2[19:20] = 11
+ *    no parity checking = BR2[21:22] = 00
+ *    SDRAM for MSEL = BR2[24:26] = 011
+ *    Valid = BR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
+ *
+ */
+
+#define CONFIG_SYS_BR3_PRELIM		0xf0001861
+
+/*
+ * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
+ *
+ * For OR3, need:
+ *    64MB mask for AM, OR3[0:7] = 1111 1100
+ *		   XAM, OR3[17:18] = 11
+ *    10 columns OR3[19-21] = 011
+ *    12 rows   OR3[23-25] = 011
+ *    EAD set for extra time OR[31] = 0
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
+ */
+
+#define CONFIG_SYS_OR3_PRELIM		0xfc006cc0
+
+/*
+ * Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM.
+ * The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000.
+ *
+ * For BR4, need:
+ *    Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0
+ *    port-size = 32-bits = BR2[19:20] = 11
+ *    no parity checking = BR2[21:22] = 00
+ *    SDRAM for MSEL = BR2[24:26] = 011
+ *    Valid = BR[31] = 1
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 0000 0000 0000 0001 1000 0110 0001 = f4001861
+ *
+ */
+
+#define CONFIG_SYS_BR4_PRELIM		0xf4001861
+
+/*
+ * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
+ *
+ * For OR4, need:
+ *    64MB mask for AM, OR3[0:7] = 1111 1100
+ *		   XAM, OR3[17:18] = 11
+ *    10 columns OR3[19-21] = 011
+ *    12 rows   OR3[23-25] = 011
+ *    EAD set for extra time OR[31] = 0
+ *
+ * 0    4    8    12   16   20   24   28
+ * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
+ */
+
+#define CONFIG_SYS_OR4_PRELIM		0xfc006cc0
+
+#define CONFIG_SYS_LBC_LCRR		0x00000002    /* LB clock ratio reg */
+#define CONFIG_SYS_LBC_LBCR		0x00000000    /* LB config reg */
+#define CONFIG_SYS_LBC_LSRT		0x20000000  /* LB sdram refresh timer */
+#define CONFIG_SYS_LBC_MRTPR		0x00000000  /* LB refresh timer prescal*/
+
+/*
+ * Common settings for all Local Bus SDRAM commands.
+ */
+#define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_RFCR16		\
+				| LSDMR_BSMA1516	\
+				| LSDMR_PRETOACT3	\
+				| LSDMR_ACTTORW3	\
+				| LSDMR_BUFCMD		\
+				| LSDMR_BL8		\
+				| LSDMR_WRC2		\
+				| LSDMR_CL3		\
+				)
+
+#define CONFIG_SYS_LBC_LSDMR_PCHALL	\
+	 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
+#define CONFIG_SYS_LBC_LSDMR_ARFRSH	\
+	 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
+#define CONFIG_SYS_LBC_LSDMR_MRW	\
+	 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
+#define CONFIG_SYS_LBC_LSDMR_RFEN	\
+	 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_RFEN)
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */
+
+#define CONFIG_SYS_INIT_L2_ADDR	0xf8f80000	/* relocate boot L2SRAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * For soldered on flash, (128kB/sector) we use 2 sectors for u-boot and
+ * one for env+bootpg (CONFIG_SYS_TEXT_BASE=0xfffa_0000, 384kB total).  For SODIMM
+ * flash (512kB/sector) we use 1 sector for u-boot, and one for env+bootpg
+ * (CONFIG_SYS_TEXT_BASE=0xfff0_0000, 1MB total).  This dynamically sets the right
+ * thing for MONITOR_LEN in both cases.
+ */
+#define CONFIG_SYS_MONITOR_LEN		(~CONFIG_SYS_TEXT_BASE + 1)
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024) /* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		(400000000 / CONFIG_SYS_CLK_DIV)
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT		1
+#define CONFIG_OF_BOARD_SETUP		1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+#define CONFIG_SYS_PCI_VIRT		0x80000000	/* 1G PCI TLB */
+#define CONFIG_SYS_PCI_PHYS		0x80000000	/* 1G PCI TLB */
+
+#define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCI1_MEM_BUS		0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCI1_IO_VIRT		0xe2000000
+#define CONFIG_SYS_PCI1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS		0xe2000000
+#define CONFIG_SYS_PCI1_IO_SIZE		0x00800000	/* 8M */
+
+#ifdef CONFIG_PCIE1
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xe2800000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xe2800000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000	/* 8M */
+#endif
+
+#ifdef CONFIG_RIO
+/*
+ * RapidIO MMU
+ */
+#define CONFIG_SYS_RIO_MEM_BASE	0xC0000000
+#define CONFIG_SYS_RIO_MEM_SIZE	0x20000000	/* 512M */
+#endif
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+
+#endif	/* CONFIG_PCI */
+
+
+#if defined(CONFIG_TSEC_ENET)
+
+#define CONFIG_MII		1	/* MII PHY management */
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"eTSEC0"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"eTSEC1"
+#undef CONFIG_MPC85XX_FEC
+
+#define TSEC1_PHY_ADDR		0x19
+#define TSEC2_PHY_ADDR		0x1a
+
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
+
+/* Options are: eTSEC[0-3] */
+#define CONFIG_ETHPRIME		"eTSEC0"
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_SIZE		0x2000
+#if CONFIG_SYS_TEXT_BASE == 0xfff00000	/* Boot from 64MB SODIMM */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x80000)
+#define CONFIG_ENV_SECT_SIZE	0x80000	/* 512K(one sector) for env */
+#elif CONFIG_SYS_TEXT_BASE == 0xfffa0000	/* Boot from 8MB soldered flash */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
+#define CONFIG_ENV_SECT_SIZE	0x20000	/* 128K(one sector) for env */
+#else
+#warning undefined environment size/location.
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_REGINFO
+
+#if defined(CONFIG_PCI)
+    #define CONFIG_CMD_PCI
+#endif
+
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_CMDLINE_EDITING			/* undef to save memory */
+#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+/* The mac addresses for all ethernet interface */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_ETHADDR	 02:E0:0C:00:00:FD
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR	 02:E0:0C:00:01:FD
+#endif
+
+#define CONFIG_IPADDR	 192.168.0.55
+
+#define CONFIG_HOSTNAME	 sbc8548
+#define CONFIG_ROOTPATH	 "/opt/eldk/ppc_85xx"
+#define CONFIG_BOOTFILE	 "/uImage"
+#define CONFIG_UBOOTPATH /u-boot.bin	/* TFTP server */
+
+#define CONFIG_SERVERIP	 192.168.0.2
+#define CONFIG_GATEWAYIP 192.168.0.1
+#define CONFIG_NETMASK	 255.255.255.0
+
+#define CONFIG_LOADADDR	1000000	/*default location for tftp and bootm*/
+
+#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
+#undef	CONFIG_BOOTARGS		/* the boot command will set bootargs*/
+
+#define CONFIG_BAUDRATE	115200
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+"netdev=eth0\0"						\
+"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"				\
+"tftpflash=tftpboot $loadaddr $uboot; "			\
+	"protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+	"erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
+	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
+	"protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
+	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
+"consoledev=ttyS0\0"				\
+"ramdiskaddr=2000000\0"			\
+"ramdiskfile=uRamdisk\0"			\
+"fdtaddr=c00000\0"				\
+"fdtfile=sbc8548.dtb\0"
+
+#define CONFIG_NFSBOOTCOMMAND						\
+   "setenv bootargs root=/dev/nfs rw "					\
+      "nfsroot=$serverip:$rootpath "					\
+      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+      "console=$consoledev,$baudrate $othbootargs;"			\
+   "tftp $loadaddr $bootfile;"						\
+   "tftp $fdtaddr $fdtfile;"						\
+   "bootm $loadaddr - $fdtaddr"
+
+
+#define CONFIG_RAMBOOTCOMMAND \
+   "setenv bootargs root=/dev/ram rw "					\
+      "console=$consoledev,$baudrate $othbootargs;"			\
+   "tftp $ramdiskaddr $ramdiskfile;"					\
+   "tftp $loadaddr $bootfile;"						\
+   "tftp $fdtaddr $fdtfile;"						\
+   "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND	CONFIG_RAMBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/sbc8641d.h b/qemu/roms/u-boot/include/configs/sbc8641d.h
new file mode 100644
index 000000000..8eb727661
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/sbc8641d.h
@@ -0,0 +1,599 @@
+/*
+ * Copyright 2007 Wind River Systems <www.windriver.com>
+ * Copyright 2007 Embedded Specialties, Inc.
+ * Joe Hamman <joe.hamman@embeddedspecialties.com>
+ *
+ * Copyright 2006 Freescale Semiconductor.
+ *
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * SBC8641D board configuration file
+ *
+ * Make sure you change the MAC address and other network params first,
+ * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_MPC8641		1	/* MPC8641 specific */
+#define CONFIG_SBC8641D		1	/* SBC8641D board specific */
+#define CONFIG_MP		1	/* support multiple processors */
+#define CONFIG_LINUX_RESET_VEC  0x100   /* Reset vector used by Linux */
+
+#define	CONFIG_SYS_TEXT_BASE	0xfff00000
+
+#ifdef RUN_DIAG
+#define CONFIG_SYS_DIAG_ADDR        0xff800000
+#endif
+
+#define CONFIG_SYS_RESET_ADDRESS    0xfff00100
+
+/*
+ * virtual address to be used for temporary mappings.  There
+ * should be 128k free at this VA.
+ */
+#define CONFIG_SYS_SCRATCH_VA	0xe8000000
+
+#define CONFIG_SYS_SRIO
+#define CONFIG_SRIO1			/* SRIO port 1 */
+
+#define CONFIG_PCI		1	/* Enable PCIE */
+#define CONFIG_PCIE1		1	/* PCIE controler 1 (slot 1) */
+#define CONFIG_PCIE2		1	/* PCIE controler 2 (slot 2) */
+#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
+#define CONFIG_FSL_LAW		1	/* Use common FSL init code */
+
+#define CONFIG_TSEC_ENET		/* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAT_RW		1	/* Use common BAT rw code */
+#define CONFIG_HIGH_BATS	1	/* High BATs supported and enabled */
+
+#undef CONFIG_SPD_EEPROM		/* Do not use SPD EEPROM for DDR setup*/
+#undef CONFIG_DDR_ECC			/* only for ECC DDR module */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+#define CONFIG_NUM_DDR_CONTROLLERS     2
+#define CACHE_LINE_INTERLEAVING		0x20000000
+#define PAGE_INTERLEAVING		0x21000000
+#define BANK_INTERLEAVING		0x22000000
+#define SUPER_BANK_INTERLEAVING		0x23000000
+
+
+#define CONFIG_ALTIVEC          1
+
+/*
+ * L2CR setup -- make sure this is right for your board!
+ */
+#define CONFIG_SYS_L2
+#define L2_INIT		0
+#define L2_ENABLE	(L2CR_L2E)
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
+
+#undef	CONFIG_SYS_DRAM_TEST				/* memory test, takes time */
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
+#define CONFIG_SYS_CCSRBAR		0xf8000000	/* relocated CCSRBAR */
+#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
+
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0x0
+#define CONFIG_SYS_CCSRBAR_PHYS		CONFIG_SYS_CCSRBAR_PHYS_LOW
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory */
+#define CONFIG_SYS_DDR_SDRAM_BASE2	0x10000000	/* DDR bank 2 */
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_SDRAM_BASE2		CONFIG_SYS_DDR_SDRAM_BASE2
+#define CONFIG_SYS_MAX_DDR_BAT_SIZE	0x80000000	/* BAT mapping size */
+#define CONFIG_VERY_BIG_RAM
+
+#define CONFIG_NUM_DDR_CONTROLLERS	2
+#define CONFIG_DIMM_SLOTS_PER_CTLR	2
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+#if defined(CONFIG_SPD_EEPROM)
+    /*
+     * Determine DDR configuration from I2C interface.
+     */
+    #define SPD_EEPROM_ADDRESS1		0x51		/* DDR DIMM */
+    #define SPD_EEPROM_ADDRESS2		0x52		/* DDR DIMM */
+    #define SPD_EEPROM_ADDRESS3		0x53		/* DDR DIMM */
+    #define SPD_EEPROM_ADDRESS4		0x54		/* DDR DIMM */
+
+#else
+    /*
+     * Manually set up DDR1 & DDR2 parameters
+     */
+
+    #define CONFIG_SYS_SDRAM_SIZE	512		/* DDR is 512MB */
+
+    #define CONFIG_SYS_DDR_CS0_BNDS	0x0000000F
+    #define CONFIG_SYS_DDR_CS1_BNDS	0x00000000
+    #define CONFIG_SYS_DDR_CS2_BNDS	0x00000000
+    #define CONFIG_SYS_DDR_CS3_BNDS	0x00000000
+    #define CONFIG_SYS_DDR_CS0_CONFIG	0x80010102
+    #define CONFIG_SYS_DDR_CS1_CONFIG	0x00000000
+    #define CONFIG_SYS_DDR_CS2_CONFIG	0x00000000
+    #define CONFIG_SYS_DDR_CS3_CONFIG	0x00000000
+    #define CONFIG_SYS_DDR_TIMING_3 0x00000000
+    #define CONFIG_SYS_DDR_TIMING_0	0x00220802
+    #define CONFIG_SYS_DDR_TIMING_1	0x38377322
+    #define CONFIG_SYS_DDR_TIMING_2	0x002040c7
+    #define CONFIG_SYS_DDR_CFG_1A	0x43008008
+    #define CONFIG_SYS_DDR_CFG_2	0x24401000
+    #define CONFIG_SYS_DDR_MODE_1	0x23c00542
+    #define CONFIG_SYS_DDR_MODE_2	0x00000000
+    #define CONFIG_SYS_DDR_MODE_CTL	0x00000000
+    #define CONFIG_SYS_DDR_INTERVAL	0x05080100
+    #define CONFIG_SYS_DDR_DATA_INIT	0x00000000
+    #define CONFIG_SYS_DDR_CLK_CTRL	0x03800000
+    #define CONFIG_SYS_DDR_CFG_1B	0xC3008008
+
+    #define CONFIG_SYS_DDR2_CS0_BNDS	0x0010001F
+    #define CONFIG_SYS_DDR2_CS1_BNDS	0x00000000
+    #define CONFIG_SYS_DDR2_CS2_BNDS	0x00000000
+    #define CONFIG_SYS_DDR2_CS3_BNDS	0x00000000
+    #define CONFIG_SYS_DDR2_CS0_CONFIG	0x80010102
+    #define CONFIG_SYS_DDR2_CS1_CONFIG	0x00000000
+    #define CONFIG_SYS_DDR2_CS2_CONFIG	0x00000000
+    #define CONFIG_SYS_DDR2_CS3_CONFIG	0x00000000
+    #define CONFIG_SYS_DDR2_EXT_REFRESH 0x00000000
+    #define CONFIG_SYS_DDR2_TIMING_0	0x00220802
+    #define CONFIG_SYS_DDR2_TIMING_1	0x38377322
+    #define CONFIG_SYS_DDR2_TIMING_2	0x002040c7
+    #define CONFIG_SYS_DDR2_CFG_1A	0x43008008
+    #define CONFIG_SYS_DDR2_CFG_2	0x24401000
+    #define CONFIG_SYS_DDR2_MODE_1	0x23c00542
+    #define CONFIG_SYS_DDR2_MODE_2	0x00000000
+    #define CONFIG_SYS_DDR2_MODE_CTL	0x00000000
+    #define CONFIG_SYS_DDR2_INTERVAL	0x05080100
+    #define CONFIG_SYS_DDR2_DATA_INIT	0x00000000
+    #define CONFIG_SYS_DDR2_CLK_CTRL	0x03800000
+    #define CONFIG_SYS_DDR2_CFG_1B	0xC3008008
+
+
+#endif
+
+/* #define CONFIG_ID_EEPROM	1
+#define ID_EEPROM_ADDR 0x57 */
+
+/*
+ * The SBC8641D contains 16MB flash space at ff000000.
+ */
+#define CONFIG_SYS_FLASH_BASE      0xff000000  /* start of FLASH 16M */
+
+/* Flash */
+#define CONFIG_SYS_BR0_PRELIM		0xff001001	/* port size 16bit */
+#define CONFIG_SYS_OR0_PRELIM		0xff006e65	/* 16MB Boot Flash area */
+
+/* 64KB EEPROM */
+#define CONFIG_SYS_BR1_PRELIM		0xf0000801	/* port size 16bit */
+#define CONFIG_SYS_OR1_PRELIM		0xffff6e65	/* 64K EEPROM area */
+
+/* EPLD - User switches, board id, LEDs */
+#define CONFIG_SYS_BR2_PRELIM		0xf1000801	/* port size 16bit */
+#define CONFIG_SYS_OR2_PRELIM		0xfff06e65	/* EPLD (switches, board ID, LEDs) area */
+
+/* Local bus SDRAM 128MB */
+#define CONFIG_SYS_BR3_PRELIM		0xe0001861	/* port size ?bit */
+#define CONFIG_SYS_OR3_PRELIM		0xfc006cc0	/* 128MB local bus SDRAM area (1st half) */
+#define CONFIG_SYS_BR4_PRELIM		0xe4001861	/* port size ?bit */
+#define CONFIG_SYS_OR4_PRELIM		0xfc006cc0	/* 128MB local bus SDRAM area (2nd half) */
+
+/* Disk on Chip (DOC) 128MB */
+#define CONFIG_SYS_BR5_PRELIM		0xe8001001	/* port size ?bit */
+#define CONFIG_SYS_OR5_PRELIM		0xf8006e65	/* 128MB local bus SDRAM area (2nd half) */
+
+/* LCD */
+#define CONFIG_SYS_BR6_PRELIM		0xf4000801	/* port size ?bit */
+#define CONFIG_SYS_OR6_PRELIM		0xfff06e65	/* 128MB local bus SDRAM area (2nd half) */
+
+/* Control logic & misc peripherals */
+#define CONFIG_SYS_BR7_PRELIM		0xf2000801	/* port size ?bit */
+#define CONFIG_SYS_OR7_PRELIM		0xfff06e65	/* 128MB local bus SDRAM area (2nd half) */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	131		/* sectors per device */
+
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000	/* early monitor loc */
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_WRITE_SWAPPED_DATA
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_PROTECTION
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#ifndef CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0x0fd00000	/* Initial RAM address */
+#else
+#define CONFIG_SYS_INIT_RAM_ADDR	0xf8400000	/* Initial RAM address */
+#endif
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)    /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)    /* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX     1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE    1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef  CONFIG_SYS_HUSH_PARSER
+#endif
+
+/*
+ * Pass open firmware flat tree to kernel
+ */
+#define CONFIG_OF_LIBFDT		1
+#define CONFIG_OF_BOARD_SETUP		1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3100
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
+
+/*
+ * RapidIO MMU
+ */
+#define CONFIG_SYS_SRIO1_MEM_BASE	0xc0000000	/* base address */
+#define CONFIG_SYS_SRIO1_MEM_PHYS	CONFIG_SYS_SRIO1_MEM_BASE
+#define CONFIG_SYS_SRIO1_MEM_SIZE	0x20000000	/* 128M */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BUS
+#define CONFIG_SYS_PCIE1_MEM_VIRT	CONFIG_SYS_PCIE1_MEM_BUS
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_BUS		0xe2000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	CONFIG_SYS_PCIE1_IO_BUS
+#define CONFIG_SYS_PCIE1_IO_VIRT	CONFIG_SYS_PCIE1_IO_BUS
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x1000000	/* 16M */
+
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	CONFIG_SYS_PCIE2_MEM_BUS
+#define CONFIG_SYS_PCIE2_MEM_VIRT	CONFIG_SYS_PCIE2_MEM_BUS
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE2_IO_BUS		0xe3000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	CONFIG_SYS_PCIE2_IO_BUS
+#define CONFIG_SYS_PCIE2_IO_VIRT	CONFIG_SYS_PCIE2_IO_BUS
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x1000000	/* 16M */
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
+
+#undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
+
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+    #define PCI_ENET0_IOADDR	0xe0000000
+    #define PCI_ENET0_MEMADDR	0xe0000000
+    #define PCI_IDSEL_NUMBER	0x0c	/* slot0->3(IDSEL)=12->15 */
+#endif
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+
+#define CONFIG_DOS_PARTITION
+#undef CONFIG_SCSI_AHCI
+
+#ifdef CONFIG_SCSI_AHCI
+#define CONFIG_SATA_ULI5288
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	4
+#define CONFIG_SYS_SCSI_MAX_LUN	1
+#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
+#define CONFIG_SYS_SCSI_MAXDEVICE	CONFIG_SYS_SCSI_MAX_DEVICE
+#endif
+
+#endif	/* CONFIG_PCI */
+
+#if defined(CONFIG_TSEC_ENET)
+
+/* #define CONFIG_MII		1 */	/* MII PHY management */
+
+#define CONFIG_TSEC1    1
+#define CONFIG_TSEC1_NAME       "eTSEC1"
+#define CONFIG_TSEC2    1
+#define CONFIG_TSEC2_NAME       "eTSEC2"
+#define CONFIG_TSEC3    1
+#define CONFIG_TSEC3_NAME       "eTSEC3"
+#define CONFIG_TSEC4    1
+#define CONFIG_TSEC4_NAME       "eTSEC4"
+
+#define TSEC1_PHY_ADDR		0x1F
+#define TSEC2_PHY_ADDR		0x00
+#define TSEC3_PHY_ADDR		0x01
+#define TSEC4_PHY_ADDR		0x02
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC3_PHYIDX		0
+#define TSEC4_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
+#define TSEC3_FLAGS		TSEC_GIGABIT
+#define TSEC4_FLAGS		TSEC_GIGABIT
+
+#define CONFIG_SYS_TBIPA_VALUE	0x1e	/* Set TBI address not to conflict with TSEC1_PHY_ADDR */
+
+#define CONFIG_ETHPRIME		"eTSEC1"
+
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * BAT0         2G     Cacheable, non-guarded
+ * 0x0000_0000  2G     DDR
+ */
+#define CONFIG_SYS_DBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_DBAT0U	(BATU_BL_2G | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE )
+#define CONFIG_SYS_IBAT0U	CONFIG_SYS_DBAT0U
+
+/*
+ * BAT1         1G     Cache-inhibited, guarded
+ * 0x8000_0000  512M   PCI-Express 1 Memory
+ * 0xa000_0000  512M   PCI-Express 2 Memory
+ *	Changed it for operating from 0xd0000000
+ */
+#define CONFIG_SYS_DBAT1L	( CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW \
+			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT1U	(CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT1U	CONFIG_SYS_DBAT1U
+
+/*
+ * BAT2         512M   Cache-inhibited, guarded
+ * 0xc000_0000  512M   RapidIO Memory
+ */
+#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW \
+			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U	(CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U	CONFIG_SYS_DBAT2U
+
+/*
+ * BAT3         4M     Cache-inhibited, guarded
+ * 0xf800_0000  4M     CCSR
+ */
+#define CONFIG_SYS_DBAT3L	( CONFIG_SYS_CCSRBAR | BATL_PP_RW \
+			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT3U	(CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U	CONFIG_SYS_DBAT3U
+
+#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
+#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
+				       | BATL_PP_RW | BATL_CACHEINHIBIT \
+				       | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
+				       | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
+				       | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
+#endif
+
+/*
+ * BAT4         32M    Cache-inhibited, guarded
+ * 0xe200_0000  16M    PCI-Express 1 I/O
+ * 0xe300_0000  16M    PCI-Express 2 I/0
+ *    Note that this is at 0xe0000000
+ */
+#define CONFIG_SYS_DBAT4L	( CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW \
+			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT4U	(CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT4U	CONFIG_SYS_DBAT4U
+
+/*
+ * BAT5         128K   Cacheable, non-guarded
+ * 0xe401_0000  128K   Init RAM for stack in the CPU DCache (no backing memory)
+ */
+#define CONFIG_SYS_DBAT5L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_DBAT5U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT5L	CONFIG_SYS_DBAT5L
+#define CONFIG_SYS_IBAT5U	CONFIG_SYS_DBAT5U
+
+/*
+ * BAT6         32M    Cache-inhibited, guarded
+ * 0xfe00_0000  32M    FLASH
+ */
+#define CONFIG_SYS_DBAT6L	((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW \
+			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6U	((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6L	((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U	CONFIG_SYS_DBAT6U
+
+/* Map the last 1M of flash where we're running from reset */
+#define CONFIG_SYS_DBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
+				 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6U_EARLY	(CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
+				 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U_EARLY	CONFIG_SYS_DBAT6U_EARLY
+
+#define CONFIG_SYS_DBAT7L	0x00000000
+#define CONFIG_SYS_DBAT7U	0x00000000
+#define CONFIG_SYS_IBAT7L	0x00000000
+#define CONFIG_SYS_IBAT7U	0x00000000
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
+#define CONFIG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
+#define CONFIG_ENV_SIZE		0x2000
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+#include <config_cmd_default.h>
+    #define CONFIG_CMD_PING
+    #define CONFIG_CMD_I2C
+    #define CONFIG_CMD_REGINFO
+
+#if defined(CONFIG_PCI)
+    #define CONFIG_CMD_PCI
+#endif
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+#if defined(CONFIG_CMD_KGDB)
+    #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+    #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+
+/* Cache Configuration */
+#define CONFIG_SYS_DCACHE_SIZE		32768
+#define CONFIG_SYS_CACHELINE_SIZE	32
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
+#endif
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+/* The mac addresses for all ethernet interface */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_ETHADDR   02:E0:0C:00:00:01
+#define CONFIG_ETH1ADDR  02:E0:0C:00:01:FD
+#define CONFIG_ETH2ADDR  02:E0:0C:00:02:FD
+#define CONFIG_ETH3ADDR  02:E0:0C:00:03:FD
+#endif
+
+#define CONFIG_HAS_ETH0		1
+#define CONFIG_HAS_ETH1		1
+#define CONFIG_HAS_ETH2		1
+#define CONFIG_HAS_ETH3		1
+
+#define CONFIG_IPADDR		192.168.0.50
+
+#define CONFIG_HOSTNAME		sbc8641d
+#define CONFIG_ROOTPATH		"/opt/eldk/ppc_74xx"
+#define CONFIG_BOOTFILE		"uImage"
+
+#define CONFIG_SERVERIP		192.168.0.2
+#define CONFIG_GATEWAYIP	192.168.0.1
+#define CONFIG_NETMASK		255.255.255.0
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE	115200
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+   "netdev=eth0\0"							\
+   "consoledev=ttyS0\0"							\
+   "ramdiskaddr=2000000\0"						\
+   "ramdiskfile=uRamdisk\0"						\
+   "dtbaddr=400000\0"							\
+   "dtbfile=sbc8641d.dtb\0"						\
+   "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0"	\
+   "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0"	\
+   "maxcpus=1"
+
+#define CONFIG_NFSBOOTCOMMAND						\
+   "setenv bootargs root=/dev/nfs rw "					\
+      "nfsroot=$serverip:$rootpath "					\
+      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "	\
+      "console=$consoledev,$baudrate $othbootargs;"			\
+   "tftp $loadaddr $bootfile;"						\
+   "tftp $dtbaddr $dtbfile;"						\
+   "bootm $loadaddr - $dtbaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+   "setenv bootargs root=/dev/ram rw "					\
+      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "	\
+      "console=$consoledev,$baudrate $othbootargs;"			\
+   "tftp $ramdiskaddr $ramdiskfile;"					\
+   "tftp $loadaddr $bootfile;"						\
+   "tftp $dtbaddr $dtbfile;"						\
+   "bootm $loadaddr $ramdiskaddr $dtbaddr"
+
+#define CONFIG_FLASHBOOTCOMMAND						\
+   "setenv bootargs root=/dev/ram rw "					\
+      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "	\
+      "console=$consoledev,$baudrate $othbootargs;"			\
+   "bootm ffd00000 ffb00000 ffa00000"
+
+#define CONFIG_BOOTCOMMAND  CONFIG_FLASHBOOTCOMMAND
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/sc3.h b/qemu/roms/u-boot/include/configs/sc3.h
new file mode 100644
index 000000000..14e033dd8
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/sc3.h
@@ -0,0 +1,549 @@
+/*
+ * (C) Copyright 2007
+ * Heiko Schocher, DENX Software Engineering, <hs@denx.de>.
+ *
+ * From:
+ * (C) Copyright 2003
+ * Juergen Beisert, EuroDesign embedded technologies, jbeisert@eurodsn.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#undef USE_VGA_GRAPHICS
+
+/* Memory Map
+ * 0x00000000 .... 0x03FFFFFF -> RAM (up to 128MiB)
+ * 0x74000000 .... 0x740FFFFF -> CS#6
+ * 0x74100000 .... 0x741FFFFF -> CS#7
+ * 0x74200000 .... 0x742FFFFF -> CS4# if no internal USB
+ * 0x74300000 .... 0x743FFFFF -> CS5# if no boosted IDE
+ * 0x77C00000 .... 0x77CFFFFF -> CS4# USB HC (1 MiB)
+ * 0x77D00000 .... 0x77DFFFFF -> CS1# NAND-Flash (1 MiB)
+ * 0x78000000 .... 0x78FFFFFF -> CS2# ISA-Bus Speicherzugriff (16 MiB)
+ * 0x79000000 .... 0x7900FFFF -> CS2# ISA-Bus IO-Zugriff (16 MiB, mapped: 64kiB)
+ * 0x79010000 .... 0x79FFFFFF -> CS2# ISA-Bus IO-Zugriff (mirrored)
+ * 0x7A000000 .... 0x7A0FFFFF -> CS5# IDE emulation (1MiB)
+ *
+ * 0x80000000 .... 0x9FFFFFFF -> PCI-Bus Speicherzugriff (512MiB, mapped: 1:1)
+ * 0xA0000000 .... 0xBFFFFFFF -> PCI-Bus Speicherzugriff (512MiB, mapped: 0x00000000...0x1FFFFFFF)
+ * 0xE8000000 .... 0xE800FFFF -> PCI-Bus IO-Zugriff (64kiB, translated to PCI: 0x0000...0xFFFF)
+ * 0xE8800000 .... 0xEBFFFFFF -> PCI-Bus IO-Zugriff (56MiB, translated to PCI: 0x00800000...0x3FFFFFF)
+ * 0xEED00000 .... 0xEED00003 -> PCI-Bus
+ * 0xEF400000 .... 0xEF40003F -> PCI-Bus Local Configuration Registers
+ * 0xEF40003F .... 0xEF5FFFFF -> reserved
+ * 0xEF600000 .... 0xEFFFFFFF -> 405GP internal Devices (10 MiB)
+ * 0xF0000000 .... 0xF01FFFFF -> Flash-ROM (2 MiB)
+ * 0xF0200000 .... 0xF7FFFFFF -> free for flash devices
+ * 0xF8000000 .... 0xF8000FFF -> OnChipMemory (4kiB)
+ * 0xF8001000 .... 0xFFDFFFFF -> free for flash devices
+ * 0xFFE00000 .... 0xFFFFFFFF -> BOOT-ROM (2 MiB)
+ */
+
+#define CONFIG_SC3	1
+#define CONFIG_405GP	1
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFA0000
+
+#define CONFIG_BOARD_EARLY_INIT_F	1
+#define CONFIG_MISC_INIT_R		1	/* Call misc_init_r() */
+
+/*
+ * Define IDE_USES_ISA_EMULATION for slower IDE access in the ISA-IO address range
+ * If undefined, IDE access uses a seperat emulation with higher access speed.
+ * Consider to inform your Linux IDE driver about the different addresses!
+ * IDE_USES_ISA_EMULATION is only used if you define CONFIG_CMD_IDE!
+ */
+#define IDE_USES_ISA_EMULATION
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+
+/*
+ * define CONFIG_SYS_CLK_FREQ to your base crystal clock in Hz
+ */
+#define CONFIG_SYS_CLK_FREQ	33333333
+
+/*
+ * define CONFIG_BAUDRATE to the baudrate value you want to use as default
+ */
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_BOOTDELAY	3 /* autoboot after 3 seconds	      */
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"nand_args=setenv bootargs root=/dev/mtdblock5 rw"		\
+		"rootfstype=jffs2\0"					\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addcons=setenv bootargs ${bootargs} "				\
+		"console=ttyS0,${baudrate}\0"				\
+	"flash_nfs=run nfsargs addip addcons;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_nand=run nand_args addip addcons;bootm ${kernel_addr}\0"	\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcons;"	\
+		"bootm\0"						\
+	"rootpath=/opt/eldk/ppc_4xx\0"					\
+	"bootfile=/tftpboot/sc3/uImage\0"				\
+	"u-boot=/tftpboot/sc3/u-boot.bin\0"				\
+	"setup=tftp 200000 /tftpboot/sc3/setup.img;source 200000\0"	\
+	"kernel_addr=FFE08000\0"					\
+	""
+#undef CONFIG_BOOTCOMMAND
+
+#define CONFIG_SILENT_CONSOLE	1	/* enable silent startup */
+#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
+
+#if 1	/* feel free to disable for development */
+#define CONFIG_AUTOBOOT_KEYED		/* Enable password protection	*/
+#define CONFIG_AUTOBOOT_PROMPT		\
+	"\nSC3 - booting... stop with ENTER\n"
+#define CONFIG_AUTOBOOT_DELAY_STR	"\r"	/* 1st "password"	*/
+#define CONFIG_AUTOBOOT_DELAY_STR2	"\n"	/* 1st "password"	*/
+#endif
+
+/*
+ * define CONFIG_BOOTCOMMAND to the autoboot commands. They will running after
+ * the CONFIG_BOOTDELAY delay to boot your machine
+ */
+#define CONFIG_BOOTCOMMAND	"bootp;dcache on;bootm"
+
+/*
+ * define CONFIG_BOOTARGS to the default kernel parameters. They will used if you don't
+ * set different values at the u-boot prompt
+ */
+#ifdef USE_VGA_GRAPHICS
+ #define CONFIG_BOOTARGS	"root=/dev/nfs rw ip=bootp nfsroot=/tftpboot/solidcard3re"
+#else
+ #define CONFIG_BOOTARGS	"console=ttyS0,115200 root=/dev/nfs rw ip=bootp"
+#endif
+/*
+ * Is the USB host controller assembled? If yes define CONFIG_ISP1161_PRESENT
+ * This reserves memory bank #4 for this purpose
+ */
+#undef CONFIG_ISP1161_PRESENT
+
+#undef CONFIG_LOADS_ECHO   /* no echo on for serial download	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+/* #define CONFIG_EEPRO100_SROM_WRITE */
+/* #define CONFIG_SHOW_MAC */
+#define CONFIG_EEPRO100
+
+#define CONFIG_PPC4xx_EMAC
+#define CONFIG_MII 1			/* add 405GP MII PHY management		*/
+#define CONFIG_PHY_ADDR 1	/* the connected Phy defaults to address 1 */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SOURCE
+
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP	1		/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"SC3> "	/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+/*
+ * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
+ * The Linux BASE_BAUD define should match this configuration.
+ *    baseBaud = cpuClock/(uartDivisor*16)
+ * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * set Linux BASE_BAUD to 403200.
+ *
+ * Consider the OPB clock! If it get lower the BASE_BAUD must be lower to
+ * (see 405GP datasheet for descritpion)
+ */
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK		/* external serial clock */
+#undef	CONFIG_SYS_405_UART_ERRATA_59		/* 405GP/CR Rev. D silicon */
+#define CONFIG_SYS_BASE_BAUD		921600	/* internal clock */
+
+/* The following table includes the supported baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+
+#define CONFIG_SYS_LOAD_ADDR		0x1000000	/* default load address */
+#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+
+/*-----------------------------------------------------------------------
+ * IIC stuff
+ *-----------------------------------------------------------------------
+ */
+#define  CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+
+#define I2C_INIT
+#define I2C_ACTIVE 0
+#define I2C_TRISTATE 0
+
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		100000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F	/* mask valid bits */
+
+#define CONFIG_RTC_DS1337
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0		/* configure ar pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_HOST	PCI_HOST_FORCE	/* select pci host function	*/
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+					/* resource configuration	*/
+
+/* If you want to see, whats connected to your PCI bus */
+/* #define CONFIG_PCI_SCAN_SHOW */
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000	/* PCI Vendor ID: to-do!!!	*/
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000	/* PCI Device ID: to-do!!!	*/
+#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CONFIG_SYS_PCI_PTM1MS	0x80000001	/* 2GB, enable hard-wired to 1	*/
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CONFIG_SYS_PCI_PTM2LA	0x00000000	/* disabled			*/
+#define CONFIG_SYS_PCI_PTM2MS	0x00000000	/* disabled			*/
+#define CONFIG_SYS_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+
+/*-----------------------------------------------------------------------
+ * External peripheral base address
+ *-----------------------------------------------------------------------
+ */
+#if !defined(CONFIG_CMD_IDE)
+
+#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
+#undef	CONFIG_IDE_RESET		/* no reset for ide supported	*/
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff
+ *-----------------------------------------------------------------------
+ */
+#else
+#define CONFIG_START_IDE	1	/* check, if use IDE */
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
+#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
+#undef	CONFIG_IDE_RESET		/* no reset for ide supported	*/
+
+#define	CONFIG_ATAPI
+#define	CONFIG_DOS_PARTITION
+#define	CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+
+#ifndef IDE_USES_ISA_EMULATION
+
+/* New and faster access */
+#define	CONFIG_SYS_ATA_BASE_ADDR		0x7A000000	/* start of ISA IO emulation */
+
+/* How many IDE busses are available */
+#define	CONFIG_SYS_IDE_MAXBUS		1
+
+/* What IDE ports are available */
+#define	CONFIG_SYS_ATA_IDE0_OFFSET	0x000		/* first is available */
+#undef	CONFIG_SYS_ATA_IDE1_OFFSET			/* second not available */
+
+/* access to the data port is calculated:
+   CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_DATA_OFFSET + 0 */
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O */
+
+/* access to the registers is calculated:
+   CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_REG_OFFSET + [1..7] */
+#define	CONFIG_SYS_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
+
+/* access to the alternate register is calculated:
+   CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_ALT_OFFSET + 6 */
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x008		/* Offset for alternate registers	*/
+
+#else /* IDE_USES_ISA_EMULATION */
+
+#define	CONFIG_SYS_ATA_BASE_ADDR		0x79000000	/* start of ISA IO emulation */
+
+/* How many IDE busses are available */
+#define	CONFIG_SYS_IDE_MAXBUS		1
+
+/* What IDE ports are available */
+#define	CONFIG_SYS_ATA_IDE0_OFFSET	0x01F0	/* first is available */
+#undef	CONFIG_SYS_ATA_IDE1_OFFSET				/* second not available */
+
+/* access to the data port is calculated:
+   CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_DATA_OFFSET + 0 */
+#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O */
+
+/* access to the registers is calculated:
+   CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_REG_OFFSET + [1..7] */
+#define	CONFIG_SYS_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
+
+/* access to the alternate register is calculated:
+   CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_ALT_OFFSET + 6 */
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x03F0		/* Offset for alternate registers	*/
+
+#endif /* IDE_USES_ISA_EMULATION */
+
+#endif
+
+/*
+#define	CONFIG_SYS_KEY_REG_BASE_ADDR	0xF0100000
+#define	CONFIG_SYS_IR_REG_BASE_ADDR	0xF0200000
+#define	CONFIG_SYS_FPGA_REG_BASE_ADDR	0xF0300000
+*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ *
+ * CONFIG_SYS_FLASH_BASE   -> start address of internal flash
+ * CONFIG_SYS_MONITOR_BASE -> start of u-boot
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFFE00000
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* Start of U-Boot	*/
+#define CONFIG_SYS_MONITOR_LEN		(0xFFFFFFFF - CONFIG_SYS_MONITOR_BASE + 1)
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 KiB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MiB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization ## FIXME: lookup in datasheet
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_CFI			/* flash is CFI compat.	*/
+#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver*/
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector	*/
+#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_WRITE_SWAPPED_DATA		/* swap Databytes between reading/writing */
+
+#define CONFIG_ENV_IS_IN_FLASH	1
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OFFSET		0x00000000  /* Offset of Environment Sector in bottom type */
+#define CONFIG_ENV_SIZE		0x4000	    /* Total Size of Environment Sector	*/
+#define CONFIG_ENV_SECT_SIZE	0x4000	    /* see README - env sector total size	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+#endif
+/* let us changing anything in our environment */
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * NAND-FLASH stuff
+ */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x77D00000
+
+#define CONFIG_JFFS2_NAND 1			/* jffs2 on nand support */
+
+/* No command line, one static partition */
+#undef	CONFIG_CMD_MTDPARTS
+#define CONFIG_JFFS2_DEV		"nand0"
+#define CONFIG_JFFS2_PART_SIZE		0x01000000
+#define CONFIG_JFFS2_PART_OFFSET	0x00000000
+
+/*
+ * Init Memory Controller:
+ *
+ */
+
+#define FLASH_BASE0_PRELIM	CONFIG_SYS_FLASH_BASE
+#define FLASH_BASE1_PRELIM	0
+
+/*-----------------------------------------------------------------------
+ * Some informations about the internal SRAM (OCM=On Chip Memory)
+ *
+ * CONFIG_SYS_OCM_DATA_ADDR -> location
+ * CONFIG_SYS_OCM_DATA_SIZE -> size
+*/
+
+#define CONFIG_SYS_TEMP_STACK_OCM	1
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM):
+ * - we are using the internal 4k SRAM, so we don't need data cache mapping
+ * - internal SRAM (OCM=On Chip Memory) is placed to CONFIG_SYS_OCM_DATA_ADDR
+ * - Stackpointer will be located to
+ *   (CONFIG_SYS_INIT_RAM_ADDR&0xFFFF0000) | (CONFIG_SYS_INIT_SP_OFFSET&0x0000FFFF)
+ *   in arch/powerpc/cpu/ppc4xx/start.S
+ */
+
+#undef CONFIG_SYS_INIT_DCACHE_CS
+/* Where the internal SRAM starts */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR
+/* Where the internal SRAM ends (only offset) */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x0F00
+
+/*
+
+ CONFIG_SYS_INIT_RAM_ADDR ------> ------------ lower address
+			   |	      |
+			   |  ^       |
+			   |  |       |
+			   |  | Stack |
+ CONFIG_SYS_GBL_DATA_OFFSET ----> ------------
+			   |	      |
+			   | 64 Bytes |
+			   |	      |
+ CONFIG_SYS_INIT_RAM_SIZE  ------> ------------ higher address
+  (offset only)
+
+*/
+#define CONFIG_SYS_GBL_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+/* Initial value of the stack pointern in internal SRAM */
+#define CONFIG_SYS_INIT_SP_OFFSET    CONFIG_SYS_GBL_DATA_OFFSET
+
+/* ################################################################################### */
+/* These defines will be used in arch/powerpc/cpu/ppc4xx/cpu_init.c to setup external chip selects  */
+/* They are currently undefined cause they are initiaized in board/solidcard3/init.S   */
+
+/* This chip select accesses the boot device */
+/* It depends on boot select switch if this device is 16 or 8 bit */
+
+#undef CONFIG_SYS_EBC_PB0AP
+#undef CONFIG_SYS_EBC_PB0CR
+
+#undef CONFIG_SYS_EBC_PB1AP
+#undef CONFIG_SYS_EBC_PB1CR
+
+#undef CONFIG_SYS_EBC_PB2AP
+#undef CONFIG_SYS_EBC_PB2CR
+
+#undef CONFIG_SYS_EBC_PB3AP
+#undef CONFIG_SYS_EBC_PB3CR
+
+#undef CONFIG_SYS_EBC_PB4AP
+#undef CONFIG_SYS_EBC_PB4CR
+
+#undef CONFIG_SYS_EBC_PB5AP
+#undef CONFIG_SYS_EBC_PB5CR
+
+#undef CONFIG_SYS_EBC_PB6AP
+#undef CONFIG_SYS_EBC_PB6CR
+
+#undef CONFIG_SYS_EBC_PB7AP
+#undef CONFIG_SYS_EBC_PB7CR
+
+#define CONFIG_SYS_EBC_CFG    0xb84ef000
+
+#undef CONFIG_SDRAM_BANK0	/* use private SDRAM initialization */
+#undef CONFIG_SPD_EEPROM
+
+/*
+ * Define this to get more information about system configuration
+ */
+/* #define SC3_DEBUGOUT */
+#undef SC3_DEBUGOUT
+
+/***********************************************************************
+ * External peripheral base address
+ ***********************************************************************/
+
+#define CONFIG_SYS_ISA_MEM_BASE_ADDRESS 0x78000000
+/*
+ Die Grafik-Treiber greifen über die Adresse in diesem Macro auf den Chip zu.
+ Das funktioniert bei deren Karten, weil sie eine PCI-Bridge benutzen, die
+ das gleiche Mapping durchführen kann, wie der SC520 (also Aufteilen von IO-Zugriffen
+ auf ISA- und PCI-Zyklen)
+ */
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS  0xE8000000
+/*#define CONFIG_SYS_ISA_IO_BASE_ADDRESS  0x79000000 */
+
+/************************************************************
+ * Video support
+ ************************************************************/
+
+#ifdef USE_VGA_GRAPHICS
+#define CONFIG_VIDEO		/* To enable video controller support */
+#define CONFIG_VIDEO_CT69000
+#define CONFIG_CFB_CONSOLE
+/* #define CONFIG_VIDEO_LOGO */
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_VIDEO_SW_CURSOR
+/* #define CONFIG_VIDEO_HW_CURSOR */
+#define CONFIG_VIDEO_ONBOARD	/* Video controller is on-board */
+
+#define VIDEO_HW_RECTFILL
+#define VIDEO_HW_BITBLT
+
+#endif
+
+/************************************************************
+ * Ident
+ ************************************************************/
+#define CONFIG_SC3_VERSION "r1.4"
+
+#define POST_OUT(x) (*((volatile unsigned char*)(0x79000080))=x)
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/sc_sps_1.h b/qemu/roms/u-boot/include/configs/sc_sps_1.h
new file mode 100644
index 000000000..16d2e2d22
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/sc_sps_1.h
@@ -0,0 +1,91 @@
+/*
+ * SchulerControl GmbH, SC_SPS_1 module config
+ *
+ * Copyright (C) 2012 Marek Vasut <marex@denx.de>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __CONFIGS_SC_SPS_1_H__
+#define __CONFIGS_SC_SPS_1_H__
+
+/* System configuration */
+#define CONFIG_MX28				/* i.MX28 SoC */
+#define MACH_TYPE_SC_SPS_1	4172
+#define CONFIG_MACH_TYPE	MACH_TYPE_SC_SPS_1
+
+/* U-Boot Commands */
+#define CONFIG_SYS_NO_FLASH
+#include <config_cmd_default.h>
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_GPIO
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_USB
+
+/* Memory configuration */
+#define CONFIG_NR_DRAM_BANKS		1		/* 1 bank of DRAM */
+#define PHYS_SDRAM_1			0x40000000	/* Base address */
+#define PHYS_SDRAM_1_SIZE		0x40000000	/* Max 1 GB RAM */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+
+/* Environment */
+#define CONFIG_ENV_SIZE			(16 * 1024)
+#define CONFIG_ENV_IS_IN_MMC
+
+/* Environment is in MMC */
+#if defined(CONFIG_CMD_MMC) && defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_ENV_OFFSET		(256 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+/* FEC Ethernet on SoC */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_SMSC
+#endif
+
+/* USB */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_EHCI_MXS_PORT0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	1
+#define CONFIG_USB_STORAGE
+#endif
+
+/* Booting Linux */
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_BOOTARGS		"console=ttyAMA0,115200"
+#define CONFIG_BOOTCOMMAND	"bootm"
+#define CONFIG_LOADADDR		0x42000000
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+
+/* Extra Environment */
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"update_sd_firmware_filename=u-boot.sd\0"			\
+	"update_sd_firmware="		/* Update the SD firmware partition */ \
+		"if mmc rescan ; then "					\
+		"if tftp ${update_sd_firmware_filename} ; then "	\
+		"setexpr fw_sz ${filesize} / 0x200 ; "	/* SD block size */ \
+		"setexpr fw_sz ${fw_sz} + 1 ; "				\
+		"mmc write ${loadaddr} 0x800 ${fw_sz} ; "		\
+		"fi ; "							\
+		"fi\0"
+
+/* The rest of the configuration is shared */
+#include <configs/mxs.h>
+
+#endif /* __CONFIGS_SC_SPS_1_H__ */
diff --git a/qemu/roms/u-boot/include/configs/scb9328.h b/qemu/roms/u-boot/include/configs/scb9328.h
new file mode 100644
index 000000000..e6d272dd1
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/scb9328.h
@@ -0,0 +1,322 @@
+/*
+ * Copyright (C) 2003 ETC s.r.o.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ * Written by Peter Figuli <peposh@etc.sk>, 2003.
+ *
+ * 2003/13/06 Initial MP10 Support copied from wepep250
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_ARM920T		1     /* this is an ARM920T CPU	    */
+#define CONFIG_IMX		1     /* in a Motorola MC9328MXL Chip */
+#define CONFIG_SCB9328		1     /* on a scb9328tronix board */
+
+#define CONFIG_IMX_SERIAL
+#define CONFIG_IMX_SERIAL1
+/*
+ * Select serial console configuration
+ */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+
+#undef CONFIG_CMD_CONSOLE
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_SOURCE
+
+/*
+ * Boot options. Setting delay to -1 stops autostart count down.
+ * NOTE: Sending parameters to kernel depends on kernel version and
+ * 2.4.19-rmk6-pxa1 patch used while my u-boot coding didn't accept
+ * parameters at all! Do not get confused by them so.
+ */
+#define CONFIG_BOOTDELAY   -1
+#define CONFIG_BOOTARGS	   "console=ttySMX0,115200n8 root=/dev/mtdblock3 rootfstype=jffs2 mtdparts=scb9328_flash:128k(U-boot)ro,128k(U-boot_env),1m(kernel),4m(root),4m(fs) eval_board=evk9328"
+#define CONFIG_BOOTCOMMAND "bootm 10040000"
+#define CONFIG_SHOW_BOOT_PROGRESS
+#define CONFIG_ETHADDR		80:81:82:83:84:85
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_IPADDR		10.10.10.9
+#define CONFIG_SERVERIP		10.10.10.10
+
+/*
+ * General options for u-boot. Modify to save memory foot print
+ */
+#define CONFIG_SYS_LONGHELP				      /* undef saves memory  */
+#define CONFIG_SYS_PROMPT		"scb9328> "	      /* prompt string	     */
+#define CONFIG_SYS_CBSIZE		256		      /* console I/O buffer  */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* print buffer size   */
+#define CONFIG_SYS_MAXARGS		16		      /* max command args    */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	      /* boot args buf size  */
+
+#define CONFIG_SYS_MEMTEST_START	0x08100000	      /* memtest test area   */
+#define CONFIG_SYS_MEMTEST_END		0x08F00000
+
+#define CONFIG_SYS_CPUSPEED		0x141	     /* core clock - register value  */
+
+#define CONFIG_BAUDRATE 115200
+/*
+ * Definitions related to passing arguments to kernel.
+ */
+#define CONFIG_CMDLINE_TAG	     1	 /* send commandline to Kernel	     */
+#define CONFIG_SETUP_MEMORY_TAGS     1	 /* send memory definition to kernel */
+#define CONFIG_INITRD_TAG	     1	 /* send initrd params		     */
+
+/*
+ * Malloc pool need to host env + 128 Kb reserve for other allocations.
+ */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128<<10) )
+
+/* SDRAM Setup Values
+0x910a8300 Precharge Command CAS 3
+0x910a8200 Precharge Command CAS 2
+
+0xa10a8300 AutoRefresh Command CAS 3
+0xa10a8200 Set AutoRefresh Command CAS 2 */
+
+#define PRECHARGE_CMD 0x910a8200
+#define AUTOREFRESH_CMD 0xa10a8200
+
+/*
+ * SDRAM Memory Map
+ */
+/* SH FIXME */
+#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of SDRAM */
+#define SCB9328_SDRAM_1		0x08000000	/* SDRAM bank #1	   */
+#define SCB9328_SDRAM_1_SIZE	0x01000000	/* 16 MB		   */
+
+#define CONFIG_SYS_TEXT_BASE	0x10000000
+
+#define CONFIG_SYS_SDRAM_BASE	SCB9328_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR	(SCB9328_SDRAM_1 + 0xf00000)
+
+/*
+ * Configuration for FLASH memory for the Synertronixx board
+ */
+
+/* #define SCB9328_FLASH_32M */
+
+/* 32MB */
+#ifdef SCB9328_FLASH_32M
+#define CONFIG_SYS_MAX_FLASH_BANKS		1	/* FLASH banks count (not chip count)*/
+#define CONFIG_SYS_MAX_FLASH_SECT		256	/* number of sector in FLASH bank    */
+#define SCB9328_FLASH_BUS_WIDTH		2	/* we use 16 bit FLASH memory...     */
+#define SCB9328_FLASH_INTERLEAVE	1	/* ... made of 1 chip		     */
+#define SCB9328_FLASH_BANK_SIZE	 0x02000000	/* size of one flash bank	     */
+#define SCB9328_FLASH_SECT_SIZE	 0x00020000	/* size of erase sector		     */
+#define SCB9328_FLASH_BASE	 0x10000000	/* location of flash memory	     */
+#define SCB9328_FLASH_UNLOCK		1	/* perform hw unlock first	     */
+#else
+
+/* 16MB */
+#define CONFIG_SYS_MAX_FLASH_BANKS		1	/* FLASH banks count (not chip count)*/
+#define CONFIG_SYS_MAX_FLASH_SECT		128	/* number of sector in FLASH bank    */
+#define SCB9328_FLASH_BUS_WIDTH		2	/* we use 16 bit FLASH memory...     */
+#define SCB9328_FLASH_INTERLEAVE	1	/* ... made of 1 chip		     */
+#define SCB9328_FLASH_BANK_SIZE	 0x01000000	/* size of one flash bank	     */
+#define SCB9328_FLASH_SECT_SIZE	 0x00020000	/* size of erase sector		     */
+#define SCB9328_FLASH_BASE	 0x10000000	/* location of flash memory	     */
+#define SCB9328_FLASH_UNLOCK		1	/* perform hw unlock first	     */
+#endif /* SCB9328_FLASH_32M */
+
+/* This should be defined if CFI FLASH device is present. Actually benefit
+   is not so clear to me. In other words we can provide more informations
+   to user, but this expects more complex flash handling we do not provide
+   now.*/
+#undef	CONFIG_SYS_FLASH_CFI
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000    /* timeout for Erase operation */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	240000    /* timeout for Write operation */
+
+#define CONFIG_SYS_FLASH_BASE		SCB9328_FLASH_BASE
+
+/*
+ * This is setting for JFFS2 support in u-boot.
+ * Right now there is no gain for user, but later on booting kernel might be
+ * possible. Consider using XIP kernel running from flash to save RAM
+ * footprint.
+ * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
+ */
+#define CONFIG_SYS_JFFS2_FIRST_BANK		0
+#define CONFIG_SYS_JFFS2_FIRST_SECTOR		5
+#define CONFIG_SYS_JFFS2_NUM_BANKS		1
+
+/*
+ * Environment setup. Definitions of monitor location and size with
+ * definition of environment setup ends up in 2 possibilities.
+ * 1. Embeded environment - in u-boot code is space for environment
+ * 2. Environment is read from predefined sector of flash
+ * Right now we support 2. possiblity, but expecting no env placed
+ * on mentioned address right now. This also needs to provide whole
+ * sector for it - for us 256Kb is really waste of memory. U-boot uses
+ * default env. and until kernel parameters could be sent to kernel
+ * env. has no sense to us.
+ */
+
+/* Setup for PA23 which is Reset Default PA23 but has to become
+   CS5 */
+
+#define CONFIG_SYS_GPR_A_VAL		0x00800000
+#define CONFIG_SYS_GIUS_A_VAL		0x0043fffe
+
+#define CONFIG_SYS_MONITOR_BASE	0x10000000
+#define CONFIG_SYS_MONITOR_LEN		0x20000		/* 128b ( 1 flash sector )  */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_ADDR		0x10020000	/* absolute address for now  */
+#define CONFIG_ENV_SIZE		0x20000
+
+#define	 CONFIG_ENV_OVERWRITE  1		/* env is not writable now   */
+
+/*
+ * CSxU_VAL:
+ * 63| x	x x x | x x x x | x x  x    x | x x x x | x x x x | x x x x | x x x x | x x x x|32
+ *   |DTACK_SEL|0|BCD |	  BCS	| PSZ|PME|SYNC|	 DOL	| CNC|	  WSC	    | 0| WWS  |	  EDC  |
+ *
+ * CSxL_VAL:
+ * 31| x x x x | x x x x | x x x x | x x x x | x x x x |  x x x x | x x	 x x | x x  x	 x| 0
+ *   |	 OEA   |   OEN	 |   WEA   |   WEN   |	 CSA   |EBC| DSZ  | 0|SP|0|WP| 0 0|PA|CSEN|
+ */
+
+#define CONFIG_SYS_CS0U_VAL 0x000F2000
+#define CONFIG_SYS_CS0L_VAL 0x11110d01
+#define CONFIG_SYS_CS1U_VAL 0x000F0a00
+#define CONFIG_SYS_CS1L_VAL 0x11110601
+#define CONFIG_SYS_CS2U_VAL 0x0
+#define CONFIG_SYS_CS2L_VAL 0x0
+
+#define CONFIG_SYS_CS3U_VAL 0x000FFFFF
+#define CONFIG_SYS_CS3L_VAL 0x00000303
+
+#define CONFIG_SYS_CS4U_VAL 0x000F0a00
+#define CONFIG_SYS_CS4L_VAL 0x11110301
+
+/* CNC == 3 too long
+   #define CONFIG_SYS_CS5U_VAL 0x0000C210 */
+
+/* #define CONFIG_SYS_CS5U_VAL 0x00008400
+   mal laenger mahcen, ob der bei 150MHz laenger haelt dann und
+   kaum langsamer ist */
+/* #define CONFIG_SYS_CS5U_VAL 0x00009400
+   #define CONFIG_SYS_CS5L_VAL 0x11010D03 */
+
+#define CONFIG_SYS_CS5U_VAL 0x00008400
+#define CONFIG_SYS_CS5L_VAL 0x00000D03
+
+#define CONFIG_DRIVER_DM9000		1
+#define CONFIG_DM9000_BASE		0x16000000
+#define DM9000_IO			CONFIG_DM9000_BASE
+#define DM9000_DATA			(CONFIG_DM9000_BASE+4)
+
+/* f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1)
+   f_ref=16,777MHz
+
+   0x002a141f: 191,9944MHz
+   0x040b2007: 144MHz
+   0x042a141f: 96MHz
+   0x0811140d: 64MHz
+   0x040e200e: 150MHz
+   0x00321431: 200MHz
+
+   0x08001800: 64MHz mit 16er Quarz
+   0x04001800: 96MHz mit 16er Quarz
+   0x04002400: 144MHz mit 16er Quarz
+
+   31 |x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x| 0
+      |XXX|--PD---|-------MFD---------|XXX|--MFI--|-----MFN-----------|	    */
+
+#define CPU200
+
+#ifdef CPU200
+#define CONFIG_SYS_MPCTL0_VAL 0x00321431
+#else
+#define CONFIG_SYS_MPCTL0_VAL 0x040e200e
+#endif
+
+/* #define BUS64 */
+#define BUS72
+
+#ifdef BUS72
+#define CONFIG_SYS_SPCTL0_VAL 0x04002400
+#endif
+
+#ifdef BUS96
+#define CONFIG_SYS_SPCTL0_VAL 0x04001800
+#endif
+
+#ifdef BUS64
+#define CONFIG_SYS_SPCTL0_VAL 0x08001800
+#endif
+
+/* Das ist der BCLK Divider, der aus der System PLL
+   BCLK und HCLK erzeugt:
+   31 | xxxx xxxx xxxx xxxx xx10 11xx xxxx xxxx | 0
+   0x2f008403 : 192MHz/2=96MHz, 144MHz/2=72MHz PRESC=1->BCLKDIV=2
+   0x2f008803 : 192MHz/3=64MHz, 240MHz/3=80MHz PRESC=1->BCLKDIV=2
+   0x2f001003 : 192MHz/5=38,4MHz
+   0x2f000003 : 64MHz/1
+   Bit 22: SPLL Restart
+   Bit 21: MPLL Restart */
+
+#ifdef BUS64
+#define CONFIG_SYS_CSCR_VAL 0x2f030003
+#endif
+
+#ifdef BUS72
+#define CONFIG_SYS_CSCR_VAL 0x2f030403
+#endif
+
+/*
+ * Well this has to be defined, but on the other hand it is used differently
+ * one may expect. For instance loadb command do not cares :-)
+ * So advice is - do not relay on this...
+ */
+#define CONFIG_SYS_LOAD_ADDR 0x08400000
+
+#define MHZ16QUARZINUSE
+
+#ifdef MHZ16QUARZINUSE
+#define CONFIG_SYSPLL_CLK_FREQ 16000000
+#else
+#define CONFIG_SYSPLL_CLK_FREQ 16780000
+#endif
+
+#define CONFIG_SYS_CLK_FREQ 16780000
+
+/* FMCR Bit 0 becomes 0 to make CS3 CS3 :P */
+#define CONFIG_SYS_FMCR_VAL 0x00000001
+
+/* Bit[0:3] contain PERCLK1DIV for UART 1
+   0x000b00b ->b<- -> 192MHz/12=16MHz
+   0x000b00b ->8<- -> 144MHz/09=16MHz
+   0x000b00b ->3<- -> 64MHz/4=16MHz */
+
+#ifdef BUS96
+#define CONFIG_SYS_PCDR_VAL 0x000b00b5
+#endif
+
+#ifdef BUS64
+#define CONFIG_SYS_PCDR_VAL 0x000b00b3
+#endif
+
+#ifdef BUS72
+#define CONFIG_SYS_PCDR_VAL 0x000b00b8
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/seaboard.h b/qemu/roms/u-boot/include/configs/seaboard.h
new file mode 100644
index 000000000..fc4f976d8
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/seaboard.h
@@ -0,0 +1,101 @@
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+
+/* LP0 suspend / resume */
+#define CONFIG_TEGRA_LP0
+#define CONFIG_AES
+#define CONFIG_TEGRA_PMU
+#define CONFIG_TPS6586X_POWER
+#define CONFIG_TEGRA_CLOCK_SCALING
+
+#include "tegra20-common.h"
+
+/* Enable fdt support for Seaboard. Flash the image in u-boot-dtb.bin */
+#define CONFIG_DEFAULT_DEVICE_TREE	tegra20-seaboard
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
+/* High-level configuration options */
+#define V_PROMPT		"Tegra20 (SeaBoard) # "
+#define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Seaboard"
+
+/* Board-specific serial config */
+#define CONFIG_TEGRA_ENABLE_UARTD
+#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
+
+/* On Seaboard: GPIO_PI3 = Port I = 8, bit = 3 */
+#define CONFIG_UART_DISABLE_GPIO	GPIO_PI3
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_SEABOARD
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT		/* Make sure LCD init is complete */
+
+/* I2C */
+#define CONFIG_SYS_I2C_TEGRA
+#define CONFIG_SYS_I2C_INIT_BOARD
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_TEGRA_MMC
+#define CONFIG_CMD_MMC
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_SYS_MMC_ENV_PART 2
+
+/* USB Host support */
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_TEGRA
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB
+
+/* USB networking support */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+
+/* General networking support */
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+
+/* Enable keyboard */
+#define CONFIG_TEGRA_KEYBOARD
+#define CONFIG_KEYBOARD
+
+/* USB keyboard */
+#define CONFIG_USB_KEYBOARD
+
+/* LCD support */
+#define CONFIG_LCD
+#define CONFIG_PWM_TEGRA
+#define CONFIG_VIDEO_TEGRA
+#define LCD_BPP				LCD_COLOR16
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define CONFIG_CONSOLE_SCROLL_LINES	10
+
+/* NAND support */
+#define CONFIG_CMD_NAND
+#define CONFIG_TEGRA_NAND
+
+/* Max number of NAND devices */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/sequoia.h b/qemu/roms/u-boot/include/configs/sequoia.h
new file mode 100644
index 000000000..b6a5e6a59
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/sequoia.h
@@ -0,0 +1,435 @@
+/*
+ * (C) Copyright 2006-2008
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2006
+ * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
+ * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * sequoia.h - configuration for Sequoia & Rainier boards
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+/* This config file is used for Sequoia (440EPx) and Rainier (440GRx)	*/
+#ifndef CONFIG_RAINIER
+#define CONFIG_440EPX		1	/* Specific PPC440EPx		*/
+#define CONFIG_HOSTNAME		sequoia
+#else
+#define CONFIG_440GRX		1	/* Specific PPC440GRx		*/
+#define CONFIG_HOSTNAME		rainier
+#endif
+#define CONFIG_440		1	/* ... PPC440 family		*/
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xFFF80000
+#endif
+
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#include "amcc-common.h"
+
+/* Detect Sequoia PLL input clock automatically via CPLD bit		*/
+#define CONFIG_SYS_CLK_FREQ    ((in8(CONFIG_SYS_BCSR_BASE + 3) & 0x80) ? \
+				33333333 : 33000000)
+
+/*
+ * Define this if you want support for video console with radeon 9200 pci card
+ * Also set CONFIG_SYS_TEXT_BASE to 0xFFF80000 in board/amcc/sequoia/config.mk in this case
+ */
+#undef CONFIG_VIDEO
+
+#ifdef CONFIG_VIDEO
+/*
+ * 44x dcache supported is working now on sequoia, but we don't enable
+ * it yet since it needs further testing
+ */
+#define CONFIG_4xx_DCACHE		/* enable dcache		*/
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
+#define CONFIG_MISC_INIT_R	1	/* Call misc_init_r		*/
+
+/*
+ * Base addresses -- Note these are effective addresses where the actual
+ * resources get mapped (not physical addresses).
+ */
+#define CONFIG_SYS_TLB_FOR_BOOT_FLASH	0x0003
+#define CONFIG_SYS_BOOT_BASE_ADDR	0xf0000000
+#define CONFIG_SYS_FLASH_BASE		0xfc000000	/* start of FLASH	*/
+#define CONFIG_SYS_NAND_ADDR		0xd0000000	/* NAND Flash		*/
+#define CONFIG_SYS_OCM_BASE		0xe0010000	/* ocm			*/
+#define CONFIG_SYS_OCM_DATA_ADDR	CONFIG_SYS_OCM_BASE
+#define CONFIG_SYS_PCI_BASE		0xe0000000	/* Internal PCI regs	*/
+#define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped pci memory	*/
+#define CONFIG_SYS_PCI_MEMBASE1	CONFIG_SYS_PCI_MEMBASE  + 0x10000000
+#define CONFIG_SYS_PCI_MEMBASE2	CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
+#define CONFIG_SYS_PCI_MEMBASE3	CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
+
+#define CONFIG_SYS_USB2D0_BASE		0xe0000100
+#define CONFIG_SYS_USB_DEVICE		0xe0000000
+#define CONFIG_SYS_USB_HOST		0xe0000400
+#define CONFIG_SYS_BCSR_BASE		0xc0000000
+
+/*
+ * Initial RAM & stack pointer
+ */
+/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache	*/
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_BASE	/* OCM			*/
+#define CONFIG_SYS_INIT_RAM_SIZE	(4 << 10)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#define CONFIG_SYS_EXT_SERIAL_CLOCK	11059200	/* ext. 11.059MHz clk	*/
+
+/*
+ * Environment
+ */
+#if defined(CONFIG_SYS_RAMBOOT)
+#define CONFIG_ENV_IS_NOWHERE		/* Store env in memory only	*/
+#define CONFIG_ENV_SIZE		(8 << 10)
+/*
+ * In RAM-booting version, we have no environment storage. So we need to
+ * provide at least preliminary MAC addresses for the 4xx EMAC driver to
+ * register the interfaces. Those two addresses are generated via the
+ * tools/gen_eth_addr tool and should only be used in a closed laboratory
+ * environment.
+ */
+#define	CONFIG_ETHADDR		4a:56:49:22:3e:43
+#define	CONFIG_ETH1ADDR		02:93:53:d5:06:98
+#else
+#define CONFIG_ENV_IS_IN_FLASH		/* use FLASH for environ vars	*/
+#endif
+
+#if defined(CONFIG_CMD_FLASH)
+/*
+ * FLASH related
+ */
+#define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible	*/
+#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
+
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks	      */
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip  */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)    */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)    */
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)   */
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* use hardware flash protection      */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO	      /* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash      */
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector	      */
+#define CONFIG_ENV_ADDR		((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
+#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector   */
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+#endif
+#endif /* CONFIG_CMD_FLASH */
+
+/*
+ * DDR SDRAM
+ */
+#define CONFIG_SYS_MBYTES_SDRAM        (256)	/* 256MB			*/
+#if !defined(CONFIG_SYS_RAMBOOT)
+#define CONFIG_DDR_DATA_EYE		/* use DDR2 optimization	*/
+#endif
+#define CONFIG_SYS_MEM_TOP_HIDE	(4 << 10) /* don't use last 4kbytes	*/
+					/* 440EPx errata CHIP 11	*/
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
+
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR	(0xa8>>1)
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+/* I2C bootstrap EEPROM */
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR	0x52
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET	0
+#define CONFIG_4xx_CONFIG_BLOCKSIZE		16
+
+/* I2C SYSMON (LM75, AD7414 is almost compatible)			*/
+#define CONFIG_DTT_LM75		1	/* ON Semi's LM75		*/
+#define CONFIG_DTT_AD7414	1	/* use AD7414			*/
+#define CONFIG_DTT_SENSORS	{0}	/* Sensor addresses		*/
+#define CONFIG_SYS_DTT_MAX_TEMP	70
+#define CONFIG_SYS_DTT_LOW_TEMP	-30
+#define CONFIG_SYS_DTT_HYSTERESIS	3
+
+/*
+ * Default environment variables
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_AMCC_DEF_ENV						\
+	CONFIG_AMCC_DEF_ENV_POWERPC					\
+	CONFIG_AMCC_DEF_ENV_PPC_OLD					\
+	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
+	"kernel_addr=FC000000\0"					\
+	"ramdisk_addr=FC180000\0"					\
+	""
+
+#define CONFIG_M88E1111_PHY	1
+#define	CONFIG_IBM_EMAC4_V4	1
+#define CONFIG_PHY_ADDR		0	/* PHY address, See schematics	*/
+
+#define CONFIG_PHY_RESET        1	/* reset phy upon startup	*/
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
+#define CONFIG_PHY1_ADDR	1
+
+/* USB */
+#ifdef CONFIG_440EPX
+
+#undef CONFIG_USB_EHCI	/* OHCI by default */
+
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_PPC4XX
+#define CONFIG_SYS_PPC4XX_USB_ADDR	0xe0000300
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_EHCI_MMIO_BIG_ENDIAN
+#define CONFIG_EHCI_DESC_BIG_ENDIAN
+#else /* CONFIG_USB_EHCI */
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_OHCI_BE_CONTROLLER
+
+#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
+#define CONFIG_SYS_USB_OHCI_CPU_INIT	1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE	CONFIG_SYS_USB_HOST
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"ppc440"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
+#endif
+
+#define CONFIG_USB_STORAGE
+/* Comment this out to enable USB 1.1 device */
+#define USB_2_0_DEVICE
+
+#endif /* CONFIG_440EPX */
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+/*
+ * Commands additional to the ones defined in amcc-common.h
+ */
+#define CONFIG_CMD_CHIP_CONFIG
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_SDRAM
+
+#ifdef CONFIG_440EPX
+#define CONFIG_CMD_USB
+#endif
+
+#ifndef CONFIG_RAINIER
+#define CONFIG_SYS_POST_FPU_ON		CONFIG_SYS_POST_FPU
+#else
+#define CONFIG_SYS_POST_FPU_ON		0
+#endif
+
+/*
+ * Don't run the memory POST on the NAND-booting version. It will
+ * overwrite part of the U-Boot image which is already loaded from NAND
+ * to SDRAM.
+ */
+#if defined(CONFIG_SYS_RAMBOOT)
+#define CONFIG_SYS_POST_MEMORY_ON	0
+#else
+#define CONFIG_SYS_POST_MEMORY_ON	CONFIG_SYS_POST_MEMORY
+#endif
+
+/* POST support */
+#define CONFIG_POST		(CONFIG_SYS_POST_CACHE	   | \
+				 CONFIG_SYS_POST_CPU	   | \
+				 CONFIG_SYS_POST_ETHER	   | \
+				 CONFIG_SYS_POST_FPU_ON    | \
+				 CONFIG_SYS_POST_I2C	   | \
+				 CONFIG_SYS_POST_MEMORY_ON | \
+				 CONFIG_SYS_POST_SPR	   | \
+				 CONFIG_SYS_POST_UART)
+
+#define CONFIG_LOGBUFFER
+#define CONFIG_SYS_POST_CACHE_ADDR	0x7fff0000	/* free virtual address     */
+
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	/* Otherwise it catches logbuffer as output */
+
+#define CONFIG_SUPPORT_VFAT
+
+/*
+ * PCI stuff
+ */
+/* General PCI */
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+#define CONFIG_SYS_PCI_CACHE_LINE_SIZE	0	/* to avoid problems with PNP	*/
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
+#define CONFIG_SYS_PCI_TARGBASE	0x80000000	/* PCIaddr mapped to	*/
+						/*   CONFIG_SYS_PCI_MEMBASE	*/
+/* Board-specific PCI */
+#define CONFIG_SYS_PCI_TARGET_INIT
+#define CONFIG_SYS_PCI_MASTER_INIT
+#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC				*/
+#define CONFIG_SYS_PCI_SUBSYS_ID       0xcafe	/* Whatever			*/
+
+/*
+ * External Bus Controller (EBC) Setup
+ */
+
+/*
+ * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
+ */
+#if !defined(CONFIG_SYS_RAMBOOT)
+#define CONFIG_SYS_NAND_CS		3	/* NAND chip connected to CSx	*/
+/* Memory Bank 0 (NOR-FLASH) initialization				*/
+#define CONFIG_SYS_EBC_PB0AP		0x03017200
+#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_FLASH_BASE | 0xda000)
+
+/* Memory Bank 3 (NAND-FLASH) initialization				*/
+#define CONFIG_SYS_EBC_PB3AP		0x018003c0
+#define CONFIG_SYS_EBC_PB3CR		(CONFIG_SYS_NAND_ADDR | 0x1c000)
+#else
+#define CONFIG_SYS_NAND_CS		0	/* NAND chip connected to CSx	*/
+/* Memory Bank 3 (NOR-FLASH) initialization				*/
+#define CONFIG_SYS_EBC_PB3AP		0x03017200
+#define CONFIG_SYS_EBC_PB3CR		(CONFIG_SYS_FLASH_BASE | 0xda000)
+
+/* Memory Bank 0 (NAND-FLASH) initialization				*/
+#define CONFIG_SYS_EBC_PB0AP		0x018003c0
+#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_NAND_ADDR | 0x1c000)
+#endif
+
+/* Memory Bank 2 (CPLD) initialization					*/
+#define CONFIG_SYS_EBC_PB2AP		0x24814580
+#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_BCSR_BASE | 0x38000)
+
+#define CONFIG_SYS_BCSR5_PCI66EN	0x80
+
+/*
+ * NAND FLASH
+ */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		(CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
+#define CONFIG_SYS_NAND_SELECT_DEVICE  1	/* nand driver supports mutipl. chips */
+
+/*
+ * PPC440 GPIO Configuration
+ */
+/* test-only: take GPIO init from pcs440ep ???? in config file */
+#define CONFIG_SYS_4xx_GPIO_TABLE { /*	  Out		  GPIO	Alternate1	Alternate2	Alternate3 */ \
+{											\
+/* GPIO Core 0 */									\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0	EBC_ADDR(7)	DMA_REQ(2)	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1	EBC_ADDR(6)	DMA_ACK(2)	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO2	EBC_ADDR(5)	DMA_EOT/TC(2)	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO3	EBC_ADDR(4)	DMA_REQ(3)	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO4	EBC_ADDR(3)	DMA_ACK(3)	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO5	EBC_ADDR(2)	DMA_EOT/TC(3)	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO6	EBC_CS_N(1)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7	EBC_CS_N(2)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8	EBC_CS_N(3)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9	EBC_CS_N(4)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5)			*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR			*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO12				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO13				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO14				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO15				*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO16 GMCTxD(4)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO17 GMCTxD(5)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO18 GMCTxD(6)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO19 GMCTxD(7)			*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO20 RejectPkt0			*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO21 RejectPkt1			*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO22				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO23 SCPD0				*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO24 GMCTxD(2)			*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO25 GMCTxD(3)			*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ	USB2D_RXERROR	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO28		USB2D_TXVALID	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO29 EBC_EXT_HDLA	USB2D_PAD_SUSPNDM */	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO30 EBC_EXT_ACK	USB2D_XCVRSELECT*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO31 EBC_EXR_BUSREQ	USB2D_TERMSELECT*/	\
+},											\
+{											\
+/* GPIO Core 1 */									\
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO32 USB2D_OPMODE0	EBC_DATA(2)	*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO33 USB2D_OPMODE1	EBC_DATA(3)	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO34 UART0_8PIN_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO36 UART0_CTS_N	EBC_DATA(0)	UART3_SIN*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO37 UART0_RTS_N	EBC_DATA(1)	UART3_SOUT*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_8PIN_DTR_N UART1_SOUT	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_8PIN_RI_N UART1_SIN	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0)			*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1)			*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2)			*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3)			*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4)	DMA_ACK(1)	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6)	DMA_EOT/TC(1)	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7)	DMA_REQ(0)	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8)	DMA_ACK(0)	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9)	DMA_EOT/TC(0)	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit	*/	\
+}											\
+}
+
+#ifdef CONFIG_VIDEO
+#define CONFIG_BIOSEMU			/* x86 bios emulator for vga bios */
+#define CONFIG_ATI_RADEON_FB		/* use radeon framebuffer driver */
+#define VIDEO_IO_OFFSET			0xe8000000
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS		VIDEO_IO_OFFSET
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_CMD_BMP
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/sh7752evb.h b/qemu/roms/u-boot/include/configs/sh7752evb.h
new file mode 100644
index 000000000..f06abbca0
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/sh7752evb.h
@@ -0,0 +1,135 @@
+/*
+ * Configuation settings for the sh7752evb board
+ *
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __SH7752EVB_H
+#define __SH7752EVB_H
+
+#undef DEBUG
+#define CONFIG_SH_32BIT		1
+#define CONFIG_CPU_SH7752	1
+#define CONFIG_SH7752EVB	1
+
+#define CONFIG_SYS_TEXT_BASE	0x5ff80000
+#define CONFIG_SYS_LDSCRIPT	"board/renesas/sh7752evb/u-boot.lds"
+
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_DFL
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_MD5SUM
+#define CONFIG_MD5
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION
+
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTARGS		"console=ttySC2,115200 root=/dev/nfs ip=dhcp"
+
+#define CONFIG_VERSION_VARIABLE
+#undef	CONFIG_SHOW_BOOT_PROGRESS
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+
+/* MEMORY */
+#define SH7752EVB_SDRAM_BASE		(0x40000000)
+#define SH7752EVB_SDRAM_SIZE		(512 * 1024 * 1024)
+
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_PBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE		512
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE	1
+#define CONFIG_CONS_SCIF2	1
+#undef	CONFIG_SYS_CONSOLE_INFO_QUIET
+#undef	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#undef	CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+
+#define CONFIG_SYS_MEMTEST_START	(SH7752EVB_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
+					 480 * 1024 * 1024)
+#undef	CONFIG_SYS_ALT_MEMTEST
+#undef	CONFIG_SYS_MEMTEST_SCRATCH
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE
+
+#define CONFIG_SYS_SDRAM_BASE		(SH7752EVB_SDRAM_BASE)
+#define CONFIG_SYS_SDRAM_SIZE		(SH7752EVB_SDRAM_SIZE)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + \
+					 128 * 1024 * 1024)
+
+#define CONFIG_SYS_MONITOR_BASE		0x00000000
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
+
+/* FLASH */
+#define CONFIG_SYS_NO_FLASH
+
+/* Ether */
+#define CONFIG_SH_ETHER			1
+#define CONFIG_SH_ETHER_USE_PORT	0
+#define CONFIG_SH_ETHER_PHY_ADDR	18
+#define CONFIG_SH_ETHER_CACHE_WRITEBACK	1
+#define CONFIG_SH_ETHER_USE_GETHER	1
+#define CONFIG_PHYLIB
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII
+#define CONFIG_PHY_VITESSE
+
+#define SH7752EVB_ETHERNET_MAC_BASE_SPI	0x00090000
+#define SH7752EVB_SPI_SECTOR_SIZE	(64 * 1024)
+#define SH7752EVB_ETHERNET_MAC_BASE	SH7752EVB_ETHERNET_MAC_BASE_SPI
+#define SH7752EVB_ETHERNET_MAC_SIZE	17
+#define SH7752EVB_ETHERNET_NUM_CH	2
+#define CONFIG_BOARD_LATE_INIT
+
+/* SPI */
+#define CONFIG_SH_SPI			1
+#define CONFIG_SH_SPI_BASE		0xfe002000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO	1
+#define CONFIG_SPI_FLASH_MACRONIX	1
+
+/* MMCIF */
+#define CONFIG_MMC			1
+#define CONFIG_GENERIC_MMC		1
+#define CONFIG_SH_MMCIF			1
+#define CONFIG_SH_MMCIF_ADDR		0xffcb0000
+#define CONFIG_SH_MMCIF_CLK		48000000
+
+/* ENV setting */
+#define CONFIG_ENV_IS_EMBEDDED
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SECT_SIZE	(64 * 1024)
+#define CONFIG_ENV_ADDR		(0x00080000)
+#define CONFIG_ENV_OFFSET	(CONFIG_ENV_ADDR)
+#define CONFIG_ENV_OVERWRITE	1
+#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_EXTRA_ENV_SETTINGS				\
+		"netboot=bootp; bootm\0"
+
+/* Board Clock */
+#define CONFIG_SYS_CLK_FREQ	48000000
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_TMU_CLK_DIV	4
+#endif	/* __SH7752EVB_H */
diff --git a/qemu/roms/u-boot/include/configs/sh7753evb.h b/qemu/roms/u-boot/include/configs/sh7753evb.h
new file mode 100644
index 000000000..e400db08a
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/sh7753evb.h
@@ -0,0 +1,135 @@
+/*
+ * Configuation settings for the sh7753evb board
+ *
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __SH7753EVB_H
+#define __SH7753EVB_H
+
+#undef DEBUG
+#define CONFIG_SH_32BIT		1
+#define CONFIG_CPU_SH7753	1
+#define CONFIG_SH7753EVB	1
+
+#define CONFIG_SYS_TEXT_BASE	0x5ff80000
+#define CONFIG_SYS_LDSCRIPT	"board/renesas/sh7753evb/u-boot.lds"
+
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_DFL
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_MD5SUM
+#define CONFIG_MD5
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION
+
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTARGS		"console=ttySC2,115200 root=/dev/nfs ip=dhcp"
+
+#define CONFIG_VERSION_VARIABLE
+#undef	CONFIG_SHOW_BOOT_PROGRESS
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+
+/* MEMORY */
+#define SH7753EVB_SDRAM_BASE		(0x40000000)
+#define SH7753EVB_SDRAM_SIZE		(512 * 1024 * 1024)
+
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_PBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE		512
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE	1
+#define CONFIG_CONS_SCIF2	1
+#undef	CONFIG_SYS_CONSOLE_INFO_QUIET
+#undef	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#undef	CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+
+#define CONFIG_SYS_MEMTEST_START	(SH7753EVB_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
+					 480 * 1024 * 1024)
+#undef	CONFIG_SYS_ALT_MEMTEST
+#undef	CONFIG_SYS_MEMTEST_SCRATCH
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE
+
+#define CONFIG_SYS_SDRAM_BASE		(SH7753EVB_SDRAM_BASE)
+#define CONFIG_SYS_SDRAM_SIZE		(SH7753EVB_SDRAM_SIZE)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + \
+					 128 * 1024 * 1024)
+
+#define CONFIG_SYS_MONITOR_BASE		0x00000000
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
+
+/* FLASH */
+#define CONFIG_SYS_NO_FLASH
+
+/* Ether */
+#define CONFIG_SH_ETHER			1
+#define CONFIG_SH_ETHER_USE_PORT	0
+#define CONFIG_SH_ETHER_PHY_ADDR	18
+#define CONFIG_SH_ETHER_CACHE_WRITEBACK	1
+#define CONFIG_SH_ETHER_USE_GETHER	1
+#define CONFIG_PHYLIB
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII
+#define CONFIG_PHY_VITESSE
+
+#define SH7753EVB_ETHERNET_MAC_BASE_SPI	0x00090000
+#define SH7753EVB_SPI_SECTOR_SIZE	(64 * 1024)
+#define SH7753EVB_ETHERNET_MAC_BASE	SH7753EVB_ETHERNET_MAC_BASE_SPI
+#define SH7753EVB_ETHERNET_MAC_SIZE	17
+#define SH7753EVB_ETHERNET_NUM_CH	2
+#define CONFIG_BOARD_LATE_INIT
+
+/* SPI */
+#define CONFIG_SH_SPI			1
+#define CONFIG_SH_SPI_BASE		0xfe002000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO	1
+#define CONFIG_SPI_FLASH_MACRONIX	1
+
+/* MMCIF */
+#define CONFIG_MMC			1
+#define CONFIG_GENERIC_MMC		1
+#define CONFIG_SH_MMCIF			1
+#define CONFIG_SH_MMCIF_ADDR		0xffcb0000
+#define CONFIG_SH_MMCIF_CLK		48000000
+
+/* ENV setting */
+#define CONFIG_ENV_IS_EMBEDDED
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SECT_SIZE	(64 * 1024)
+#define CONFIG_ENV_ADDR		(0x00080000)
+#define CONFIG_ENV_OFFSET	(CONFIG_ENV_ADDR)
+#define CONFIG_ENV_OVERWRITE	1
+#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_EXTRA_ENV_SETTINGS				\
+		"netboot=bootp; bootm\0"
+
+/* Board Clock */
+#define CONFIG_SYS_CLK_FREQ	48000000
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_TMU_CLK_DIV	4
+#endif	/* __SH7753EVB_H */
diff --git a/qemu/roms/u-boot/include/configs/sh7757lcr.h b/qemu/roms/u-boot/include/configs/sh7757lcr.h
new file mode 100644
index 000000000..08bff1da3
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/sh7757lcr.h
@@ -0,0 +1,143 @@
+/*
+ * Configuation settings for the sh7757lcr board
+ *
+ * Copyright (C) 2011 Renesas Solutions Corp.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __SH7757LCR_H
+#define __SH7757LCR_H
+
+#undef DEBUG
+#define CONFIG_SH_32BIT		1
+#define CONFIG_CPU_SH7757	1
+#define CONFIG_SH7757LCR	1
+#define CONFIG_SH7757LCR_DDR_ECC	1
+
+#define CONFIG_SYS_TEXT_BASE	0x8ef80000
+#define CONFIG_SYS_LDSCRIPT	"board/renesas/sh7757lcr/u-boot.lds"
+
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_MD5SUM
+#define CONFIG_MD5
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION
+
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTARGS		"console=ttySC2,115200 root=/dev/nfs ip=dhcp"
+
+#define CONFIG_VERSION_VARIABLE
+#undef	CONFIG_SHOW_BOOT_PROGRESS
+
+/* MEMORY */
+#define SH7757LCR_SDRAM_BASE		(0x80000000)
+#define SH7757LCR_SDRAM_SIZE		(240 * 1024 * 1024)
+#define SH7757LCR_SDRAM_ECC_SETTING	0x0f000000	/* 240MByte */
+#define SH7757LCR_SDRAM_DVC_SIZE	(16 * 1024 * 1024)
+
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_PBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE		512
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE	1
+#define CONFIG_CONS_SCIF2	1
+#undef	CONFIG_SYS_CONSOLE_INFO_QUIET
+#undef	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#undef	CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+
+#define CONFIG_SYS_MEMTEST_START	(SH7757LCR_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
+					 224 * 1024 * 1024)
+#undef	CONFIG_SYS_ALT_MEMTEST
+#undef	CONFIG_SYS_MEMTEST_SCRATCH
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE
+
+#define CONFIG_SYS_SDRAM_BASE		(SH7757LCR_SDRAM_BASE)
+#define CONFIG_SYS_SDRAM_SIZE		(SH7757LCR_SDRAM_SIZE)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + \
+					 (128 + 16) * 1024 * 1024)
+
+#define CONFIG_SYS_MONITOR_BASE		0x00000000
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
+
+/* FLASH */
+#define CONFIG_SYS_NO_FLASH
+
+/* Ether */
+#define CONFIG_SH_ETHER			1
+#define CONFIG_SH_ETHER_USE_PORT	0
+#define CONFIG_SH_ETHER_PHY_ADDR	1
+#define CONFIG_SH_ETHER_CACHE_WRITEBACK	1
+#define CONFIG_PHYLIB
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
+
+#define SH7757LCR_ETHERNET_MAC_BASE_SPI	0x000b0000
+#define SH7757LCR_SPI_SECTOR_SIZE	(64 * 1024)
+#define SH7757LCR_ETHERNET_MAC_BASE	SH7757LCR_ETHERNET_MAC_BASE_SPI
+#define SH7757LCR_ETHERNET_MAC_SIZE	17
+#define SH7757LCR_ETHERNET_NUM_CH	2
+#define CONFIG_BOARD_LATE_INIT
+
+/* Gigabit Ether */
+#define SH7757LCR_GIGA_ETHERNET_NUM_CH	2
+
+/* SPI */
+#define CONFIG_SH_SPI			1
+#define CONFIG_SH_SPI_BASE		0xfe002000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO	1
+
+/* MMCIF */
+#define CONFIG_MMC			1
+#define CONFIG_GENERIC_MMC		1
+#define CONFIG_SH_MMCIF			1
+#define CONFIG_SH_MMCIF_ADDR		0xffcb0000
+#define CONFIG_SH_MMCIF_CLK		48000000
+
+/* SH7757 board */
+#define SH7757LCR_SDRAM_PHYS_TOP	0x40000000
+#define SH7757LCR_GRA_OFFSET		0x1f000000
+#define SH7757LCR_PCIEBRG_ADDR_B0	0x000a0000
+#define SH7757LCR_PCIEBRG_SIZE_B0	(64 * 1024)
+#define SH7757LCR_PCIEBRG_ADDR		0x00090000
+#define SH7757LCR_PCIEBRG_SIZE		(96 * 1024)
+
+/* ENV setting */
+#define CONFIG_ENV_IS_EMBEDDED
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SECT_SIZE	(64 * 1024)
+#define CONFIG_ENV_ADDR		(0x00080000)
+#define CONFIG_ENV_OFFSET	(CONFIG_ENV_ADDR)
+#define CONFIG_ENV_OVERWRITE	1
+#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_EXTRA_ENV_SETTINGS				\
+		"netboot=bootp; bootm\0"
+
+/* Board Clock */
+#define CONFIG_SYS_CLK_FREQ	48000000
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_TMU_CLK_DIV	4
+#endif	/* __SH7757LCR_H */
diff --git a/qemu/roms/u-boot/include/configs/sh7763rdp.h b/qemu/roms/u-boot/include/configs/sh7763rdp.h
new file mode 100644
index 000000000..2438318fc
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/sh7763rdp.h
@@ -0,0 +1,111 @@
+/*
+ * Configuation settings for the Renesas SH7763RDP board
+ *
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __SH7763RDP_H
+#define __SH7763RDP_H
+
+#define CONFIG_CPU_SH7763	1
+#define CONFIG_SH7763RDP	1
+#define __LITTLE_ENDIAN		1
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_JFFS2
+
+#define CONFIG_BOOTDELAY        -1
+#define CONFIG_BOOTARGS         "console=ttySC2,115200 root=1f01"
+#define CONFIG_ENV_OVERWRITE    1
+
+#define CONFIG_VERSION_VARIABLE
+#undef  CONFIG_SHOW_BOOT_PROGRESS
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE        1
+#define CONFIG_BAUDRATE         115200
+#define CONFIG_CONS_SCIF2		1
+
+#define CONFIG_SYS_TEXT_BASE	0x8FFC0000
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_CBSIZE		256	/* Buffer size for input from the Console */
+#define CONFIG_SYS_PBSIZE		256	/* Buffer size for Console output */
+#define CONFIG_SYS_MAXARGS		16	/* max args accepted for monitor commands */
+#define CONFIG_SYS_BARGSIZE	512	/* Buffer size for Boot Arguments
+								passed to kernel */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }	/* List of legal baudrate
+												settings for this board */
+
+/* SDRAM */
+#define CONFIG_SYS_SDRAM_BASE		(0x8C000000)
+#define CONFIG_SYS_SDRAM_SIZE		(64 * 1024 * 1024)
+#define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
+
+/* Flash(NOR) */
+#define CONFIG_SYS_FLASH_BASE		(0xA0000000)
+#define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT)
+#define CONFIG_SYS_MAX_FLASH_BANKS (1)
+#define CONFIG_SYS_MAX_FLASH_SECT  (520)
+
+/* U-boot setting */
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_MONITOR_LEN		(128 * 1024)
+/* Size of DRAM reserved for malloc() use */
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
+#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#undef  CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_SYS_FLASH_EMPTY_INFO	/* print 'E' for empty sector on flinfo */
+/* Timeout for Flash erase operations (in ms) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(3 * 1000)
+/* Timeout for Flash write operations (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(3 * 1000)
+/* Timeout for Flash set sector lock bit operations (in ms) */
+#define CONFIG_SYS_FLASH_LOCK_TOUT		(3 * 1000)
+/* Timeout for Flash clear lock bit operations (in ms) */
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	(3 * 1000)
+/* Use hardware flash sectors protection instead of U-Boot software protection */
+#undef  CONFIG_SYS_FLASH_PROTECTION
+#undef  CONFIG_SYS_DIRECT_FLASH_TFTP
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	(128 * 1024)
+#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE))
+/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
+#define CONFIG_ENV_OFFSET		(CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
+
+/* Clock */
+#define CONFIG_SYS_CLK_FREQ	66666666
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_TMU_CLK_DIV		(4)	/* 4 (default), 16, 64, 256 or 1024 */
+
+/* Ether */
+#define CONFIG_SH_ETHER 1
+#define CONFIG_SH_ETHER_USE_PORT (1)
+#define CONFIG_SH_ETHER_PHY_ADDR (0x01)
+#define CONFIG_PHYLIB
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
+
+#endif /* __SH7763RDP_H */
diff --git a/qemu/roms/u-boot/include/configs/sh7785lcr.h b/qemu/roms/u-boot/include/configs/sh7785lcr.h
new file mode 100644
index 000000000..2723eaf2d
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/sh7785lcr.h
@@ -0,0 +1,176 @@
+/*
+ * Configuation settings for the Renesas Technology R0P7785LC0011RL board
+ *
+ * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __SH7785LCR_H
+#define __SH7785LCR_H
+
+#undef DEBUG
+#define CONFIG_CPU_SH7785	1
+#define CONFIG_SH7785LCR	1
+
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_SH_ZIMAGEBOOT
+
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION
+
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTARGS		"console=ttySC1,115200 root=/dev/nfs ip=dhcp"
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"bootdevice=0:1\0"						\
+	"usbload=usb reset;usbboot;usb stop;bootm\0"
+
+#define CONFIG_VERSION_VARIABLE
+#undef	CONFIG_SHOW_BOOT_PROGRESS
+
+/* MEMORY */
+#if defined(CONFIG_SH_32BIT)
+#define CONFIG_SYS_TEXT_BASE		0x8FF80000
+/* 0x40000000 - 0x47FFFFFF does not use */
+#define CONFIG_SH_SDRAM_OFFSET		(0x8000000)
+#define SH7785LCR_SDRAM_PHYS_BASE	(0x40000000 + CONFIG_SH_SDRAM_OFFSET)
+#define SH7785LCR_SDRAM_BASE		(0x80000000 + CONFIG_SH_SDRAM_OFFSET)
+#define SH7785LCR_SDRAM_SIZE		(384 * 1024 * 1024)
+#define SH7785LCR_FLASH_BASE_1		(0xa0000000)
+#define SH7785LCR_FLASH_BANK_SIZE	(64 * 1024 * 1024)
+#define SH7785LCR_USB_BASE		(0xa6000000)
+#else
+#define CONFIG_SYS_TEXT_BASE		0x0FF80000
+#define SH7785LCR_SDRAM_BASE		(0x08000000)
+#define SH7785LCR_SDRAM_SIZE		(128 * 1024 * 1024)
+#define SH7785LCR_FLASH_BASE_1		(0xa0000000)
+#define SH7785LCR_FLASH_BANK_SIZE	(64 * 1024 * 1024)
+#define SH7785LCR_USB_BASE		(0xb4000000)
+#endif
+
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_PBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE		512
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE	1
+#define CONFIG_CONS_SCIF1	1
+#define CONFIG_SCIF_EXT_CLOCK	1
+#undef	CONFIG_SYS_CONSOLE_INFO_QUIET
+#undef	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#undef	CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+
+
+#define CONFIG_SYS_MEMTEST_START	(SH7785LCR_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
+					(SH7785LCR_SDRAM_SIZE) - \
+					 4 * 1024 * 1024)
+#undef	CONFIG_SYS_ALT_MEMTEST
+#undef	CONFIG_SYS_MEMTEST_SCRATCH
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE
+
+#define CONFIG_SYS_SDRAM_BASE	(SH7785LCR_SDRAM_BASE)
+#define CONFIG_SYS_SDRAM_SIZE	(SH7785LCR_SDRAM_SIZE)
+#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
+
+#define CONFIG_SYS_MONITOR_BASE	(SH7785LCR_FLASH_BASE_1)
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(512 * 1024)
+#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
+
+/* FLASH */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#undef	CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BASE		(SH7785LCR_FLASH_BASE_1)
+#define CONFIG_SYS_MAX_FLASH_SECT	512
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE + \
+				 (0 * SH7785LCR_FLASH_BANK_SIZE) }
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(3 * 1000)
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(3 * 1000)
+#define CONFIG_SYS_FLASH_LOCK_TOUT	(3 * 1000)
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	(3 * 1000)
+
+#undef	CONFIG_SYS_FLASH_PROTECTION
+#undef	CONFIG_SYS_DIRECT_FLASH_TFTP
+
+/* R8A66597 */
+#define CONFIG_USB_R8A66597_HCD
+#define CONFIG_R8A66597_BASE_ADDR	SH7785LCR_USB_BASE
+#define CONFIG_R8A66597_XTAL		0x0000	/* 12MHz */
+#define CONFIG_R8A66597_LDRV		0x8000	/* 3.3V */
+#define CONFIG_R8A66597_ENDIAN		0x0000	/* little */
+
+/* PCI Controller */
+#define CONFIG_PCI
+#define CONFIG_SH4_PCI
+#define CONFIG_SH7780_PCI
+#if defined(CONFIG_SH_32BIT)
+#define CONFIG_SH7780_PCI_LSR	0x1ff00001
+#define CONFIG_SH7780_PCI_LAR	0x5f000000
+#define CONFIG_SH7780_PCI_BAR	0x5f000000
+#else
+#define CONFIG_SH7780_PCI_LSR	0x07f00001
+#define CONFIG_SH7780_PCI_LAR	CONFIG_SYS_SDRAM_SIZE
+#define CONFIG_SH7780_PCI_BAR	CONFIG_SYS_SDRAM_SIZE
+#endif
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW	1
+
+#define CONFIG_PCI_MEM_BUS	0xFD000000	/* Memory space base addr */
+#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE	0x01000000	/* Size of Memory window */
+
+#define CONFIG_PCI_IO_BUS	0xFE200000	/* IO space base address */
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0x00200000	/* Size of IO window */
+
+#if defined(CONFIG_SH_32BIT)
+#define CONFIG_PCI_SYS_PHYS	SH7785LCR_SDRAM_PHYS_BASE
+#else
+#define CONFIG_PCI_SYS_PHYS	CONFIG_SYS_SDRAM_BASE
+#endif
+#define CONFIG_PCI_SYS_BUS	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_PCI_SYS_SIZE	CONFIG_SYS_SDRAM_SIZE
+
+/* Network device (RTL8169) support */
+#define CONFIG_RTL8169
+
+/* ENV setting */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE	1
+#define CONFIG_ENV_SECT_SIZE	(256 * 1024)
+#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_OFFSET		(CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
+
+/* Board Clock */
+/* The SCIF used external clock. system clock only used timer. */
+#define CONFIG_SYS_CLK_FREQ	50000000
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_TMU_CLK_DIV		4
+
+#endif	/* __SH7785LCR_H */
diff --git a/qemu/roms/u-boot/include/configs/sheevaplug.h b/qemu/roms/u-boot/include/configs/sheevaplug.h
new file mode 100644
index 000000000..ecc93bc53
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/sheevaplug.h
@@ -0,0 +1,98 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CONFIG_SHEEVAPLUG_H
+#define _CONFIG_SHEEVAPLUG_H
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING	"\nMarvell-Sheevaplug"
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_FEROCEON_88FR131	1	/* CPU Core subversion */
+#define CONFIG_KIRKWOOD		1	/* SOC Family Name */
+#define CONFIG_KW88F6281	1	/* SOC Name */
+#define CONFIG_MACH_SHEEVAPLUG	/* Machine type */
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/*
+ *  Environment variables configurations
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_ENV_IS_IN_NAND		1
+#define CONFIG_ENV_SECT_SIZE		0x20000	/* 128K */
+#else
+#define CONFIG_ENV_IS_NOWHERE		1	/* if env in SDRAM */
+#endif
+/*
+ * max 4k env size is enough, but in case of nand
+ * it has to be rounded to sector size
+ */
+#define CONFIG_ENV_SIZE			0x20000	/* 128k */
+#define CONFIG_ENV_ADDR			0x60000
+#define CONFIG_ENV_OFFSET		0x60000	/* env starts here */
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_BOOTCOMMAND		"${x_bootcmd_kernel}; "	\
+	"setenv bootargs ${x_bootargs} ${x_bootargs_root}; "	\
+	"${x_bootcmd_usb}; bootm 0x6400000;"
+
+#define CONFIG_MTDPARTS		"orion_nand:512k(uboot),"	\
+	"3m@1m(kernel),1m@4m(psm),13m@5m(rootfs) rw\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS	"x_bootargs=console"	\
+	"=ttyS0,115200 mtdparts="CONFIG_MTDPARTS	\
+	"x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \
+	"x_bootcmd_usb=usb start\0" \
+	"x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0"
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS	{1, 0}	/* enable port 0 only */
+#define CONFIG_PHY_BASE_ADR	0
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * File system
+ */
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_LZO
+
+#endif /* _CONFIG_SHEEVAPLUG_H */
diff --git a/qemu/roms/u-boot/include/configs/shmin.h b/qemu/roms/u-boot/include/configs/shmin.h
new file mode 100644
index 000000000..4d38f6c55
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/shmin.h
@@ -0,0 +1,110 @@
+/*
+ * Configuation settings for shmin (T-SH7706LAN, T-SH7706LSR)
+ *
+ * Copyright (C) 2010, 2011 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __SHMIN_H
+#define __SHMIN_H
+
+#define CONFIG_CPU_SH7706	1
+/* T-SH7706LAN */
+#define CONFIG_SHMIN		1
+/* T-SH7706LSR*/
+/* #define CONFIG_T_SH7706LSR	1 */
+
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
+
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_BOOTARGS		"console=ttySC0,115200"
+
+/*
+ * This board has original boot loader. If you write u-boot to 0x0,
+ * you should set undef.
+ */
+#define CONFIG_VERSION_VARIABLE
+#undef  CONFIG_SHOW_BOOT_PROGRESS
+
+/* system */
+#define SHMIN_SDRAM_BASE		(0x8C000000)
+#define SHMIN_FLASH_BASE_1		(0xA0000000)
+
+#define CONFIG_SYS_TEXT_BASE	0x8DFB0000
+#define CONFIG_SYS_LONGHELP		/* undef to save memory	*/
+#define CONFIG_SYS_CBSIZE	256	/* Buffer size for input from the Console */
+#define CONFIG_SYS_PBSIZE	256	/* Buffer size for Console output */
+#define CONFIG_SYS_MAXARGS	16	/* max args accepted for monitor commands */
+/* Buffer size for Boot Arguments passed to kernel */
+#define CONFIG_SYS_BARGSIZE	512
+/* List of legal baudrate settings for this board */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600,14400,19200,38400,57600,115200 }
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE	1
+#define CONFIG_CONS_SCIF0	1
+
+/* memory */
+#define CONFIG_SYS_SDRAM_BASE		SHMIN_SDRAM_BASE
+#define CONFIG_SYS_SDRAM_SIZE		(32 * 1024 * 1024)
+#define CONFIG_SYS_MEMTEST_START	SHMIN_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - (256 * 1024))
+
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 1 * 1024 * 1024)
+#define CONFIG_SYS_MONITOR_BASE		(SHMIN_FLASH_BASE_1 + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_SYS_MONITOR_LEN		(128 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)
+#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
+
+/* FLASH */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#undef  CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_SYS_FLASH_EMPTY_INFO	/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_BASE		SHMIN_FLASH_BASE_1
+#define CONFIG_SYS_MAX_FLASH_SECT 11
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+
+#define CONFIG_FLASH_CFI_LEGACY
+#define CONFIG_SYS_ATMEL_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_ATMEL_TOTALSECT	CONFIG_SYS_MAX_FLASH_SECT
+#define CONFIG_SYS_ATMEL_REGION		4
+#define CONFIG_SYS_ATMEL_SECT		{1, 2, 1, 7}
+#define CONFIG_SYS_ATMEL_SECTSZ		{0x4000, 0x2000, 0x8000, 0x10000}
+
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	(64 * 1024)
+#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
+
+#ifdef CONFIG_T_SH7706LSR
+#define CONFIG_ENV_ADDR		(SHMIN_FLASH_BASE_1 + 70000)
+#else
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#endif
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500
+
+/* Board Clock */
+#ifdef CONFIG_T_SH7706LSR
+#define CONFIG_SYS_CLK_FREQ 40000000
+#else
+#define CONFIG_SYS_CLK_FREQ 33333333
+#endif /* CONFIG_T_SH7706LSR */
+#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_TMU_CLK_DIV	4
+
+/* Network device */
+#define CONFIG_DRIVER_NE2000
+#define CONFIG_DRIVER_NE2000_BASE   (0xb0000300)
+
+#endif	/* __SHMIN_H */
diff --git a/qemu/roms/u-boot/include/configs/siemens-am33x-common.h b/qemu/roms/u-boot/include/configs/siemens-am33x-common.h
new file mode 100644
index 000000000..721c4e6ba
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/siemens-am33x-common.h
@@ -0,0 +1,496 @@
+/*
+ * siemens am33x common board options
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * U-Boot file:/include/configs/am335x_evm.h
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_SIEMENS_AM33X_COMMON_H
+#define __CONFIG_SIEMENS_AM33X_COMMON_H
+
+#define CONFIG_AM33XX
+#define CONFIG_OMAP
+#define CONFIG_OMAP_COMMON
+
+#include <asm/arch/omap.h>
+
+#define CONFIG_DMA_COHERENT
+#define CONFIG_DMA_COHERENT_SIZE	(1 << 20)
+
+#define CONFIG_ENV_SIZE			(0x2000)
+#define CONFIG_SYS_MALLOC_LEN		(16 * 1024 * 1024)
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT		"U-Boot# "
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_MACH_TYPE		CONFIG_SIEMENS_MACH_TYPE
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#define CONFIG_SYS_CACHELINE_SIZE       64
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_CACHE
+
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_ROOTPATH		"/opt/eldk"
+#endif
+
+#define CONFIG_ENV_OVERWRITE		1
+#define CONFIG_ENV_IS_NOWHERE
+
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_AUTOLOAD	"yes"
+
+/* Clock Defines */
+#define V_OSCK				24000000  /* Clock output from T2 */
+#define V_SCLK				(V_OSCK)
+
+/* We set the max number of command args high to avoid HUSH bugs. */
+#define CONFIG_SYS_MAXARGS		32
+
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		512
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE \
+					+ sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+/*
+ * memtest works on 8 MB in DRAM after skipping 32MB from
+ * start addr of ram disk
+ */
+#define CONFIG_SYS_MEMTEST_START	(PHYS_DRAM_1 + (64 * 1024 * 1024))
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START \
+					+ (8 * 1024 * 1024))
+
+#define CONFIG_SYS_LOAD_ADDR		0x81000000 /* Default load address */
+
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_CMD_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+
+#define CONFIG_SPI
+#define CONFIG_OMAP3_SPI
+#define CONFIG_MTD_DEVICE
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED		(75000000)
+
+ /* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS		1		/*  1 bank of DRAM */
+#define PHYS_DRAM_1			0x80000000	/* DRAM Bank #1 */
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_DRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR         (NON_SECURE_SRAM_END - \
+						GENERATED_GBL_DATA_SIZE)
+ /* Platform/Board specific defs */
+#define CONFIG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
+#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		(48000000)
+#define CONFIG_SYS_NS16550_COM1		0x44e09000
+#define CONFIG_SYS_NS16550_COM4		0x481a6000
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+#define CONFIG_SERIAL1                  1
+#define CONFIG_CONS_INDEX               1
+
+/* I2C Configuration */
+#define CONFIG_I2C
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED	OMAP_I2C_STANDARD
+#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
+#define CONFIG_SYS_I2C_OMAP24XX
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE		0x402F0400
+#define CONFIG_SPL_MAX_SIZE		(101 * 1024)
+#define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
+
+#define CONFIG_SPL_BSS_START_ADDR	0x80000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
+
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_FS_FAT
+#define CONFIG_SPL_I2C_SUPPORT
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_YMODEM_SUPPORT
+
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_BUS		0
+#define CONFIG_SPL_SPI_CS		0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x20000
+
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/am33xx/u-boot-spl.lds"
+
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_NAND_AM33XX_BCH
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
+					 CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
+					 10, 11, 12, 13, 14, 15, 16, 17, \
+					 18, 19, 20, 21, 22, 23, 24, 25, \
+					 26, 27, 28, 29, 30, 31, 32, 33, \
+					 34, 35, 36, 37, 38, 39, 40, 41, \
+					 42, 43, 44, 45, 46, 47, 48, 49, \
+					 50, 51, 52, 53, 54, 55, 56, 57, }
+
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	14
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW
+
+#define CONFIG_SYS_NAND_ECCSTEPS	4
+#define	CONFIG_SYS_NAND_ECCTOTAL	(CONFIG_SYS_NAND_ECCBYTES * \
+						CONFIG_SYS_NAND_ECCSTEPS)
+
+#define	CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * other needs.
+ */
+#define CONFIG_SYS_TEXT_BASE		0x80100000
+#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
+
+/*
+ * Since SPL did pll and ddr initialization for us,
+ * we don't need to do it twice.
+ */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+#ifndef CONFIG_SPL_BUILD
+/*
+ * USB configuration
+ */
+#define CONFIG_USB_MUSB_DSPS
+#define CONFIG_ARCH_MISC_INIT
+#define CONFIG_MUSB_GADGET
+#define CONFIG_MUSB_PIO_ONLY
+#define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_VBUS_DRAW	2
+#define CONFIG_MUSB_HOST
+
+#define CONFIG_AM335X_USB0
+#define CONFIG_AM335X_USB0_MODE	MUSB_PERIPHERAL
+#define CONFIG_AM335X_USB1
+#define CONFIG_AM335X_USB1_MODE MUSB_HOST
+#ifdef CONFIG_MUSB_HOST
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#endif
+
+#ifdef CONFIG_MUSB_GADGET
+#define CONFIG_USB_ETHER
+#define CONFIG_USB_ETH_RNDIS
+#define CONFIG_USBNET_HOST_ADDR	"de:ad:be:af:00:00"
+#endif /* CONFIG_MUSB_GADGET */
+
+#define CONFIG_USB_GADGET
+#define CONFIG_USBDOWNLOAD_GADGET
+
+/* USB DRACO ID as default */
+#define CONFIG_USBD_HS
+#define CONFIG_G_DNL_VENDOR_NUM 0x0908
+#define CONFIG_G_DNL_PRODUCT_NUM 0x02d2
+#define CONFIG_G_DNL_MANUFACTURER "Siemens AG"
+
+/* USB Device Firmware Update support */
+#define CONFIG_DFU_FUNCTION
+#define CONFIG_DFU_NAND
+#define CONFIG_CMD_DFU
+#define CONFIG_SYS_DFU_DATA_BUF_SIZE	(1 << 20)
+#define DFU_MANIFEST_POLL_TIMEOUT	25000
+
+#endif /* CONFIG_SPL_BUILD */
+
+/*
+ * Default to using SPI for environment, etc.  We have multiple copies
+ * of SPL as the ROM will check these locations.
+ * 0x0 - 0x20000 : First copy of SPL
+ * 0x20000 - 0x40000 : Second copy of SPL
+ * 0x40000 - 0x60000 : Third copy of SPL
+ * 0x60000 - 0x80000 : Fourth copy of SPL
+ * 0x80000 - 0xDF000 : U-Boot
+ * 0xDF000 - 0xE0000 : U-Boot Environment
+ * 0xE0000 - 0x442000 : Linux Kernel
+ * 0x442000 - 0x800000 : Userland
+ */
+#if defined(CONFIG_SPI_BOOT)
+# undef CONFIG_ENV_IS_NOWHERE
+# define CONFIG_ENV_IS_IN_SPI_FLASH
+# define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
+# define CONFIG_ENV_OFFSET		(892 << 10) /* 892 KiB in */
+# define CONFIG_ENV_SECT_SIZE		(4 << 10) /* 4 KB sectors */
+#endif /* SPI support */
+
+/* Unsupported features */
+#undef CONFIG_USE_IRQ
+
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_DRIVER_TI_CPSW
+#define CONFIG_MII
+#define CONFIG_PHY_GIGE
+#define CONFIG_PHYLIB
+#define CONFIG_CMD_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_NET_RETRY_COUNT         10
+#define CONFIG_NET_MULTI
+
+#define CONFIG_NAND
+/* NAND support */
+#ifdef CONFIG_NAND
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_MTDPARTS
+
+#define MTDIDS_NAME_STR		"omap2-nand.0"
+#define MTDIDS_DEFAULT		"nand0=" MTDIDS_NAME_STR
+#define MTDPARTS_DEFAULT	"mtdparts=" MTDIDS_NAME_STR ":" \
+					"128k(spl),"		\
+					"128k(spl.backup1),"	\
+					"128k(spl.backup2),"	\
+					"128k(spl.backup3),"	\
+					"1920k(u-boot),"	\
+					"128k(uboot.env),"	\
+					"5120k(kernel_a),"	\
+					"5120k(kernel_b),"	\
+					"8192k(mtdoops),"	\
+					"-(rootfs)"
+/*
+ * chip-size = 256MiB
+ *|         name |        size |           address area |
+ *-------------------------------------------------------
+ *|          spl | 128.000 KiB | 0x       0..0x   1ffff |
+ *|  spl.backup1 | 128.000 KiB | 0x   20000..0x   3ffff |
+ *|  spl.backup2 | 128.000 KiB | 0x   40000..0x   5ffff |
+ *|  spl.backup3 | 128.000 KiB | 0x   60000..0x   7ffff |
+ *|       u-boot |   1.875 MiB | 0x   80000..0x  25ffff |
+ *|    uboot.env | 128.000 KiB | 0x  260000..0x  27ffff |
+ *|     kernel_a |   5.000 MiB | 0x  280000..0x  77ffff |
+ *|     kernel_b |   5.000 MiB | 0x  780000..0x  c7ffff |
+ *|      mtdoops |   8.000 MiB | 0x  c80000..0x 147ffff |
+ *|       rootfs | 235.500 MiB | 0x 1480000..0x fffffff |
+ *-------------------------------------------------------
+ */
+
+#define DFU_ALT_INFO_NAND \
+	"spl part 0 1;" \
+	"spl.backup1 part 0 2;" \
+	"spl.backup2 part 0 3;" \
+	"spl.backup3 part 0 4;" \
+	"u-boot part 0 5;" \
+	"u-boot.env part 0 6;" \
+	"kernel_a part 0 7;" \
+	"kernel_b part 0 8;" \
+	"rootfs partubi 0 10"
+
+#define CONFIG_COMMON_ENV_SETTINGS \
+	"verify=no \0" \
+	"project_dir=systemone\0" \
+	"upgrade_available=0\0" \
+	"altbootcmd=run bootcmd\0" \
+	"bootlimit=3\0" \
+	"partitionset_active=A\0" \
+	"loadaddr=0x82000000\0" \
+	"kloadaddr=0x81000000\0" \
+	"script_addr=0x81900000\0" \
+	"console=console=ttyMTD,mtdoops console=ttyO0,115200n8 panic=5\0" \
+	"nand_active_ubi_vol=rootfs_a\0" \
+	"nand_active_ubi_vol_A=rootfs_a\0" \
+	"nand_active_ubi_vol_B=rootfs_b\0" \
+	"nand_root_fs_type=ubifs rootwait=1\0" \
+	"nand_src_addr=0x280000\0" \
+	"nand_src_addr_A=0x280000\0" \
+	"nand_src_addr_B=0x780000\0" \
+	"nfsopts=nolock rw mem=128M\0" \
+	"ip_method=none\0" \
+	"bootenv=uEnv.txt\0" \
+	"bootargs_defaults=setenv bootargs " \
+		"console=${console} " \
+		"${testargs} " \
+		"${optargs}\0" \
+	"nand_args=run bootargs_defaults;" \
+		"mtdparts default;" \
+		"setenv ${partitionset_active} true;" \
+		"if test -n ${A}; then " \
+			"setenv nand_active_ubi_vol ${nand_active_ubi_vol_A};" \
+			"setenv nand_src_addr ${nand_src_addr_A};" \
+		"fi;" \
+		"if test -n ${B}; then " \
+			"setenv nand_active_ubi_vol ${nand_active_ubi_vol_B};" \
+			"setenv nand_src_addr ${nand_src_addr_B};" \
+		"fi;" \
+		"setenv nand_root ubi0:${nand_active_ubi_vol} rw " \
+		"ubi.mtd=9,2048;" \
+		"setenv bootargs ${bootargs} " \
+		"root=${nand_root} noinitrd ${mtdparts} " \
+		"rootfstype=${nand_root_fs_type} ip=${ip_method} " \
+		"console=ttyMTD,mtdoops console=ttyO0,115200n8 mtdoops.mtddev" \
+		"=mtdoops\0" \
+	"dfu_args=run bootargs_defaults;" \
+		"setenv bootargs ${bootargs} ;" \
+		"mtdparts default; " \
+		"dfu 0 nand 0; \0" \
+		"dfu_alt_info=" DFU_ALT_INFO_NAND "\0" \
+	"net_args=run bootargs_defaults;" \
+		"mtdparts default;" \
+		"setenv bootfile ${project_dir}/kernel/uImage;" \
+		"setenv rootpath /home/projects/${project_dir}/rootfs;" \
+		"setenv bootargs ${bootargs} " \
+		"root=/dev/nfs ${mtdparts} " \
+		"nfsroot=${serverip}:${rootpath},${nfsopts} " \
+		"ip=${ipaddr}:${serverip}:" \
+		"${gatewayip}:${netmask}:${hostname}:eth0:off\0" \
+	"nand_boot=echo Booting from nand; " \
+		"if test ${upgrade_available} -eq 1; then " \
+			"if test ${bootcount} -gt ${bootlimit}; " \
+				"then " \
+				"setenv upgrade_available 0;" \
+				"setenv ${partitionset_active} true;" \
+				"if test -n ${A}; then " \
+					"setenv partitionset_active B; " \
+					"env delete A; " \
+				"fi;" \
+				"if test -n ${B}; then " \
+					"setenv partitionset_active A; " \
+					"env delete B; " \
+				"fi;" \
+				"saveenv; " \
+			"fi;" \
+		"fi;" \
+		"echo set ${partitionset_active}...;" \
+		"run nand_args; " \
+		"nand read.i ${kloadaddr} ${nand_src_addr} " \
+		"${nand_img_size}; bootm ${kloadaddr}\0" \
+	"net_nfs=echo Booting from network ...; " \
+		"run net_args; " \
+		"tftpboot ${kloadaddr} ${serverip}:${bootfile}; " \
+		"bootm ${kloadaddr}\0" \
+	"flash_self=run nand_boot\0" \
+	"flash_self_test=setenv testargs test; " \
+		"run nand_boot\0" \
+	"dfu_start=echo Preparing for dfu mode ...; " \
+		"run dfu_args; \0" \
+	"preboot=echo; "\
+		"echo Type 'run flash_self' to use kernel and root " \
+		"filesystem on memory; echo Type 'run flash_self_test' to " \
+		"use kernel and root filesystem on memory, boot in test " \
+		"mode; echo Not ready yet: 'run flash_nfs' to use kernel " \
+		"from memory and root filesystem over NFS; echo Type " \
+		"'run net_nfs' to get Kernel over TFTP and mount root " \
+		"filesystem over NFS; " \
+		"echo Set partitionset_active variable to 'A' " \
+		"or 'B' to select kernel and rootfs partition; " \
+		"echo" \
+		"\0"
+
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_NAND_OMAP_ELM
+#define CONFIG_SYS_NAND_BASE		(0x08000000)	/* physical address */
+							/* to access nand at */
+							/* CS0 */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND
+							   devices */
+#if !defined(CONFIG_SPI_BOOT)
+#undef CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		0x260000 /* environment starts here */
+#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
+#endif
+#endif
+
+#define CONFIG_OMAP_GPIO
+
+/* Watchdog */
+#define CONFIG_HW_WATCHDOG
+
+/* Stop autoboot with ESC ESC key detected */
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_STOP_STR	"\x1b\x1b"
+#define CONFIG_AUTOBOOT_PROMPT	"Autobooting in %d seconds, "		\
+				"press \"<Esc><Esc>\" to stop\n", bootdelay
+
+/* Reboot after 60 sec if bootcmd fails */
+#define CONFIG_RESET_TO_RETRY
+#define CONFIG_BOOT_RETRY_TIME 60
+
+#define CONFIG_BOOTCOUNT_LIMIT
+#define CONFIG_BOOTCOUNT_ENV
+
+/* Enable Device-Tree (FDT) support */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_FDT
+
+#endif	/* ! __CONFIG_SIEMENS_AM33X_COMMON_H */
diff --git a/qemu/roms/u-boot/include/configs/smdk2410.h b/qemu/roms/u-boot/include/configs/smdk2410.h
new file mode 100644
index 000000000..d4ae19f96
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/smdk2410.h
@@ -0,0 +1,200 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Gary Jennejohn <garyj@denx.de>
+ * David Mueller <d.mueller@elsoft.ch>
+ *
+ * Configuation settings for the SAMSUNG SMDK2410 board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARM920T		/* This is an ARM920T Core */
+#define CONFIG_S3C24X0		/* in a SAMSUNG S3C24x0-type SoC */
+#define CONFIG_S3C2410		/* specifically a SAMSUNG S3C2410 SoC */
+#define CONFIG_SMDK2410		/* on a SAMSUNG SMDK2410 Board */
+
+#define CONFIG_SYS_TEXT_BASE	0x0
+
+#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
+
+/* input clock of PLL (the SMDK2410 has 12MHz input clock) */
+#define CONFIG_SYS_CLK_FREQ	12000000
+
+#define CONFIG_CMDLINE_TAG	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_CS8900		/* we have a CS8900 on-board */
+#define CONFIG_CS8900_BASE	0x19000300
+#define CONFIG_CS8900_BUS16	/* the Linux driver does accesses as shorts */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_S3C24X0_SERIAL
+#define CONFIG_SERIAL1		1	/* we use SERIAL 1 on SMDK2410 */
+
+/************************************************************
+ * USB support (currently only works with D-cache off)
+ ************************************************************/
+#define CONFIG_USB_OHCI
+#define CONFIG_USB_OHCI_S3C24XX
+#define CONFIG_USB_KEYBOARD
+#define CONFIG_USB_STORAGE
+#define CONFIG_DOS_PARTITION
+
+/************************************************************
+ * RTC
+ ************************************************************/
+#define CONFIG_RTC_S3C24X0
+
+
+#define CONFIG_BAUDRATE		115200
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_USB
+
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_CMDLINE_EDITING
+
+/* autoboot */
+#define CONFIG_BOOTDELAY	5
+#define CONFIG_BOOT_RETRY_TIME	-1
+#define CONFIG_RESET_TO_RETRY
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_IPADDR		10.0.0.110
+#define CONFIG_SERVERIP		10.0.0.1
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_PROMPT	"SMDK2410 # "
+#define CONFIG_SYS_CBSIZE	256
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
+				sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+#define CONFIG_DISPLAY_CPUINFO				/* Display cpu info */
+
+#define CONFIG_SYS_MEMTEST_START	0x30000000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x33F00000	/* 63 MB in DRAM */
+
+#define CONFIG_SYS_LOAD_ADDR		0x30800000
+
+/* support additional compression methods */
+#define CONFIG_BZIP2
+#define CONFIG_LZO
+#define CONFIG_LZMA
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1          /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1		0x30000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x04000000 /* 64 MB */
+
+#define PHYS_FLASH_1		0x00000000 /* Flash Bank #0 */
+
+#define CONFIG_SYS_FLASH_BASE	PHYS_FLASH_1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_LEGACY
+#define CONFIG_SYS_FLASH_LEGACY_512Kx16
+#define CONFIG_FLASH_SHOW_PROGRESS	45
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_MAX_FLASH_SECT	(19)
+
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x070000)
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SIZE			0x10000
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * Size of malloc() pool
+ * BZIP2 / LZO / LZMA need a lot of RAM
+ */
+#define CONFIG_SYS_MALLOC_LEN	(4 * 1024 * 1024)
+
+#define CONFIG_SYS_MONITOR_LEN	(448 * 1024)
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+
+/*
+ * NAND configuration
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_S3C2410
+#define CONFIG_SYS_S3C2410_NAND_HWECC
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x4E000000
+#endif
+
+/*
+ * File system
+ */
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_YAFFS2
+#define CONFIG_RBTREE
+
+/* additions for new relocation code, must be added to all boards */
+#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE + 0x1000 - \
+				GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/smdk5250.h b/qemu/roms/u-boot/include/configs/smdk5250.h
new file mode 100644
index 000000000..183aae726
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/smdk5250.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Configuration settings for the SAMSUNG SMDK5250 board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_SMDK_H
+#define __CONFIG_SMDK_H
+
+#include <configs/exynos5250-dt.h>
+
+#undef CONFIG_DEFAULT_DEVICE_TREE
+#define CONFIG_DEFAULT_DEVICE_TREE	exynos5250-smdk5250
+
+#endif	/* __CONFIG_SMDK_H */
diff --git a/qemu/roms/u-boot/include/configs/smdk5420.h b/qemu/roms/u-boot/include/configs/smdk5420.h
new file mode 100644
index 000000000..b96eea889
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/smdk5420.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ *
+ * Configuration settings for the SAMSUNG EXYNOS5420 board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_5420_H
+#define __CONFIG_5420_H
+
+#include <configs/exynos5-dt.h>
+
+#define CONFIG_EXYNOS5420		/* which is in a Exynos5 Family */
+#define CONFIG_SMDK5420			/* which is in a SMDK5420 */
+
+#undef CONFIG_DEFAULT_DEVICE_TREE
+#define CONFIG_DEFAULT_DEVICE_TREE	exynos5420-smdk5420
+
+#define CONFIG_VAR_SIZE_SPL
+
+#define CONFIG_SYS_SDRAM_BASE		0x20000000
+#define CONFIG_SYS_TEXT_BASE		0x23E00000
+
+#define CONFIG_BOARD_REV_GPIO_COUNT	2
+
+/* MACH_TYPE_SMDK5420 macro will be removed once added to mach-types */
+#define MACH_TYPE_SMDK5420		8002 /* Temporary number */
+#define CONFIG_MACH_TYPE		MACH_TYPE_SMDK5420
+
+/* select serial console configuration */
+#define CONFIG_SERIAL3			/* use SERIAL 3 */
+
+#ifdef CONFIG_VAR_SIZE_SPL
+#define CONFIG_SPL_TEXT_BASE		0x02024410
+#else
+#define CONFIG_SPL_TEXT_BASE	0x02024400
+#endif
+
+#define CONFIG_BOOTCOMMAND	"mmc read 20007000 451 2000; bootm 20007000"
+
+#define CONFIG_SYS_PROMPT		"SMDK5420 # "
+#define CONFIG_IDENT_STRING		" for SMDK5420"
+
+#define CONFIG_IRAM_TOP		0x02074000
+/*
+ * Put the initial stack pointer 1KB below this to allow room for the
+ * SPL marker. This value is arbitrary, but gd_t is placed starting here.
+ */
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_IRAM_TOP - 0x800)
+
+#define CONFIG_MAX_I2C_NUM	11
+
+#endif	/* __CONFIG_5420_H */
diff --git a/qemu/roms/u-boot/include/configs/smdkc100.h b/qemu/roms/u-boot/include/configs/smdkc100.h
new file mode 100644
index 000000000..c9a2e1568
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/smdkc100.h
@@ -0,0 +1,220 @@
+/*
+ * (C) Copyright 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * HeungJun Kim <riverful.kim@samsung.com>
+ * Inki Dae <inki.dae@samsung.com>
+ *
+ * Configuation settings for the SAMSUNG SMDKC100 board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_SAMSUNG		1	/* in a SAMSUNG core */
+#define CONFIG_S5P		1	/* which is in a S5P Family */
+#define CONFIG_S5PC100		1	/* which is in a S5PC100 */
+#define CONFIG_SMDKC100		1	/* working with SMDKC100 */
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+
+#define CONFIG_ARCH_CPU_INIT
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* input clock of PLL: SMDKC100 has 12MHz input clock */
+#define CONFIG_SYS_CLK_FREQ		12000000
+
+/* DRAM Base */
+#define CONFIG_SYS_SDRAM_BASE		0x30000000
+
+/* Text Base */
+#define CONFIG_SYS_TEXT_BASE		0x34800000
+
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_EDITING
+
+/*
+ * Size of malloc() pool
+ * 1MB = 0x100000, 0x100000 = 1024 * 1024
+ */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (1 << 20))
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL0			1	/* use SERIAL 0 on SMDKC100 */
+
+/* PWM */
+#define CONFIG_PWM			1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE			115200
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_NAND
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_ONENAND
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_MTDPARTS
+
+#define CONFIG_BOOTDELAY	3
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+
+#define MTDIDS_DEFAULT		"onenand0=s3c-onenand"
+#define MTDPARTS_DEFAULT	"mtdparts=s3c-onenand:256k(bootloader)"\
+				",128k@0x40000(params)"\
+				",3m@0x60000(kernel)"\
+				",16m@0x360000(test)"\
+				",-(UBI)"
+
+#define NORMAL_MTDPARTS_DEFAULT MTDPARTS_DEFAULT
+
+#define CONFIG_BOOTCOMMAND	"run ubifsboot"
+
+#define CONFIG_RAMDISK_BOOT	"root=/dev/ram0 rw rootfstype=ext2" \
+				" console=ttySAC0,115200n8" \
+				" mem=128M"
+
+#define CONFIG_COMMON_BOOT	"console=ttySAC0,115200n8" \
+				" mem=128M " \
+				" " MTDPARTS_DEFAULT
+
+#define CONFIG_BOOTARGS	"root=/dev/mtdblock5 ubi.mtd=4" \
+			" rootfstype=cramfs " CONFIG_COMMON_BOOT
+
+#define CONFIG_UPDATEB	"updateb=onenand erase 0x0 0x40000;" \
+			" onenand write 0x32008000 0x0 0x40000\0"
+
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_UPDATEB \
+	"updatek=" \
+		"onenand erase 0x60000 0x300000;" \
+		"onenand write 0x31008000 0x60000 0x300000\0" \
+	"updateu=" \
+		"onenand erase block 147-4095;" \
+		"onenand write 0x32000000 0x1260000 0x8C0000\0" \
+	"bootk=" \
+		"onenand read 0x30007FC0 0x60000 0x300000;" \
+		"bootm 0x30007FC0\0" \
+	"flashboot=" \
+		"set bootargs root=/dev/mtdblock${bootblock} " \
+		"rootfstype=${rootfstype} " \
+		"ubi.mtd=${ubiblock} ${opts} " CONFIG_COMMON_BOOT ";" \
+		"run bootk\0" \
+	"ubifsboot=" \
+		"set bootargs root=ubi0!rootfs rootfstype=ubifs " \
+		" ubi.mtd=${ubiblock} ${opts} " CONFIG_COMMON_BOOT "; " \
+		"run bootk\0" \
+	"boottrace=setenv opts initcall_debug; run bootcmd\0" \
+	"android=" \
+		"set bootargs root=ubi0!ramdisk ubi.mtd=${ubiblock} " \
+		"rootfstype=ubifs init=/init.sh " CONFIG_COMMON_BOOT "; " \
+		"run bootk\0" \
+	"nfsboot=" \
+		"set bootargs root=/dev/nfs ubi.mtd=${ubiblock} " \
+		"nfsroot=${nfsroot},nolock " \
+		"ip=${ipaddr}:${serverip}:${gatewayip}:" \
+		"${netmask}:nowplus:usb0:off " CONFIG_COMMON_BOOT "; " \
+		"run bootk\0" \
+	"ramboot=" \
+		"set bootargs " CONFIG_RAMDISK_BOOT \
+		" initrd=0x33000000,8M ramdisk=8192\0" \
+	"rootfstype=cramfs\0" \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"meminfo=mem=128M\0" \
+	"nfsroot=/nfsroot/arm\0" \
+	"bootblock=5\0" \
+	"ubiblock=4\0" \
+	"ubi=enabled"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser	*/
+#define CONFIG_SYS_PROMPT		"SMDKC100 # "
+#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE	384	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5e00000)
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE
+
+/* SMDKC100 has 1 banks of DRAM, we use only one in U-Boot */
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE	/* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	(128 << 20)	/* 0x8000000, 128 MB Bank #1 */
+
+#define CONFIG_SYS_MONITOR_BASE	0x00000000
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_NO_FLASH		1
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* 256 KiB */
+#define CONFIG_IDENT_STRING		" for SMDKC100"
+
+#if !defined(CONFIG_NAND_SPL) && (CONFIG_SYS_TEXT_BASE >= 0xc0000000)
+#define CONFIG_ENABLE_MMU
+#endif
+
+#ifdef CONFIG_ENABLE_MMU
+#define CONFIG_SYS_MAPPED_RAM_BASE	0xc0000000
+#else
+#define CONFIG_SYS_MAPPED_RAM_BASE	CONFIG_SYS_SDRAM_BASE
+#endif
+
+/*-----------------------------------------------------------------------
+ * Boot configuration
+ */
+#define CONFIG_ENV_IS_IN_ONENAND	1
+#define CONFIG_ENV_SIZE			(128 << 10)	/* 128KiB, 0x20000 */
+#define CONFIG_ENV_ADDR			(256 << 10)	/* 256KiB, 0x40000 */
+#define CONFIG_ENV_OFFSET		(256 << 10)	/* 256KiB, 0x40000 */
+
+#define CONFIG_USE_ONENAND_BOARD_INIT
+#define CONFIG_SAMSUNG_ONENAND		1
+#define CONFIG_SYS_ONENAND_BASE		0xE7100000
+
+#define CONFIG_DOS_PARTITION		1
+
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_LOAD_ADDR - 0x1000000)
+
+/*
+ * Ethernet Contoller driver
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_SMC911X         1       /* we have a SMC9115 on-board   */
+#define CONFIG_SMC911X_16_BIT  1       /* SMC911X_16_BIT Mode          */
+#define CONFIG_SMC911X_BASE    0x98800300      /* SMC911X Drive Base   */
+#define CONFIG_ENV_SROM_BANK   3       /* Select SROM Bank-3 for Ethernet*/
+#endif /* CONFIG_CMD_NET */
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/smdkv310.h b/qemu/roms/u-boot/include/configs/smdkv310.h
new file mode 100644
index 000000000..1388f4998
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/smdkv310.h
@@ -0,0 +1,151 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics
+ *
+ * Configuration settings for the SAMSUNG SMDKV310 (EXYNOS4210) board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_SAMSUNG			1	/* in a SAMSUNG core */
+#define CONFIG_S5P			1	/* S5P Family */
+#define CONFIG_EXYNOS4210		1	/* which is a EXYNOS4210 SoC */
+#define CONFIG_SMDKV310			1	/* working with SMDKV310*/
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* Mach Type */
+#define CONFIG_MACH_TYPE		MACH_TYPE_SMDKV310
+
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CONFIG_SYS_TEXT_BASE		0x43E00000
+
+/* input clock of PLL: SMDKV310 has 24MHz input clock */
+#define CONFIG_SYS_CLK_FREQ		24000000
+
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_EDITING
+
+/* Handling Sleep Mode*/
+#define S5P_CHECK_SLEEP			0x00000BAD
+#define S5P_CHECK_DIDLE			0xBAD00000
+#define S5P_CHECK_LPA			0xABAD0000
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (1 << 20))
+
+/* select serial console configuration */
+#define CONFIG_SERIAL1			1	/* use SERIAL 1 */
+#define CONFIG_BAUDRATE			115200
+#define EXYNOS4_DEFAULT_UART_OFFSET	0x010000
+
+/* SD/MMC configuration */
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_SDHCI
+#define CONFIG_S5P_SDHCI
+
+/* PWM */
+#define CONFIG_PWM			1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Command definition*/
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_FAT
+
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+/* MMC SPL */
+#define CONFIG_SPL
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define COPY_BL2_FNPTR_ADDR	0x00002488
+
+#define CONFIG_SPL_TEXT_BASE	0x02021410
+
+#define CONFIG_BOOTCOMMAND	"fatload mmc 0 40007000 uImage; bootm 40007000"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser	*/
+#define CONFIG_SYS_PROMPT		"SMDKV310 # "
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size*/
+#define CONFIG_SYS_PBSIZE		384	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC2,115200n8\0"
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x6000000)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x3E00000)
+
+/* SMDKV310 has 4 bank of DRAM */
+#define CONFIG_NR_DRAM_BANKS	4
+#define SDRAM_BANK_SIZE		(512UL << 20UL)	/* 512 MB */
+#define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_1_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_2		(CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
+#define PHYS_SDRAM_2_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_3		(CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_3_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_4		(CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_4_SIZE	SDRAM_BANK_SIZE
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH		1
+#undef	CONFIG_CMD_IMLS
+#define CONFIG_IDENT_STRING		" for SMDKC210/V310"
+
+#define CONFIG_CLK_1000_400_200
+
+/* MIU (Memory Interleaving Unit) */
+#define CONFIG_MIU_2BIT_INTERLEAVED
+
+#define CONFIG_ENV_IS_IN_MMC		1
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_ENV_SIZE			(16 << 10)	/* 16 KB */
+#define RESERVE_BLOCK_SIZE		(512)
+#define BL1_SIZE			(16 << 10) /*16 K reserved for BL1*/
+#define CONFIG_ENV_OFFSET		(RESERVE_BLOCK_SIZE + BL1_SIZE)
+#define CONFIG_DOS_PARTITION		1
+
+#define CONFIG_SPL_LDSCRIPT	"board/samsung/common/exynos-uboot-spl.lds"
+#define CONFIG_SPL_MAX_FOOTPRINT	(14 * 1024)
+
+#define CONFIG_SYS_INIT_SP_ADDR		0x02040000
+
+/* U-boot copy size from boot Media to DRAM.*/
+#define	COPY_BL2_SIZE		0x80000
+#define BL2_START_OFFSET	((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512)
+#define BL2_SIZE_BLOC_COUNT	(COPY_BL2_SIZE/512)
+
+/* Ethernet Controllor Driver */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_BASE		0x5000000
+#define CONFIG_SMC911X_16_BIT
+#define CONFIG_ENV_SROM_BANK		1
+#endif /*CONFIG_CMD_NET*/
+
+/* Enable devicetree support */
+#define CONFIG_OF_LIBFDT
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/snapper9260.h b/qemu/roms/u-boot/include/configs/snapper9260.h
new file mode 100644
index 000000000..1ebee714b
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/snapper9260.h
@@ -0,0 +1,169 @@
+/*
+ * Bluewater Systems Snapper 9260 and 9G20 modules
+ *
+ * (C) Copyright 2011 Bluewater Systems
+ *   Author: Andre Renaud <andre@bluewatersys.com>
+ *   Author: Ryan Mallon <ryan@bluewatersys.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* SoC type is defined in boards.cfg */
+#include <asm/hardware.h>
+#include <linux/sizes.h>
+
+#define CONFIG_SYS_TEXT_BASE		0x20000000
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000 /* External Crystal, in Hz */
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768
+
+/* CPU */
+#define CONFIG_ARCH_CPU_INIT
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SKIP_RELOCATE_UBOOT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_FIT
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
+#define CONFIG_SYS_SDRAM_SIZE		(64 * 1024 * 1024) /* 64MB */
+#define CONFIG_SYS_INIT_SP_ADDR		(ATMEL_BASE_SRAM1 + 0x1000 - \
+					 GENERATED_GBL_DATA_SIZE)
+
+/* Mem test settings */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + (1024 * 1024))
+
+/* NAND Flash */
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
+#define CONFIG_SYS_NAND_DBW_8
+#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21) /* AD21 */
+#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22) /* AD22 */
+#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIN_PC14
+#define CONFIG_SYS_NAND_READY_PIN	AT91_PIN_PC13
+
+/* Ethernet */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_RETRY_COUNT		20
+#define CONFIG_RESET_PHY_R
+#define CONFIG_AT91_WANTS_COMMON_PHY
+#define CONFIG_TFTP_PORT
+#define CONFIG_TFTP_TSIZE
+
+/* USB */
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE	ATMEL_UHP_BASE
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"at91sam9260"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+#define CONFIG_USB_STORAGE
+
+/* GPIOs and IO expander */
+#define CONFIG_ATMEL_LEGACY
+#define CONFIG_AT91_GPIO
+#define CONFIG_AT91_GPIO_PULLUP		1
+#define CONFIG_PCA953X
+#define CONFIG_SYS_I2C_PCA953X_ADDR	0x28
+#define CONFIG_SYS_I2C_PCA953X_WIDTH	{ {0x28, 16} }
+
+/* UARTs/Serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
+#define CONFIG_USART_ID			ATMEL_ID_SYS
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_PROMPT		"Snapper> "
+
+/* I2C - Bit-bashed */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED	100000
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0x7F
+#define CONFIG_SOFT_I2C_READ_REPEATED_START
+#define I2C_INIT do {							\
+		at91_set_gpio_output(AT91_PIN_PA23, 1);			\
+		at91_set_gpio_output(AT91_PIN_PA24, 1);			\
+		at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1);	\
+		at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1);	\
+	} while (0)
+#define I2C_SOFT_DECLARATIONS
+#define I2C_ACTIVE
+#define I2C_TRISTATE	at91_set_gpio_input(AT91_PIN_PA23, 1);
+#define I2C_READ	at91_get_gpio_value(AT91_PIN_PA23);
+#define I2C_SDA(bit) do {						\
+		if (bit) {						\
+			at91_set_gpio_input(AT91_PIN_PA23, 1);		\
+		} else {						\
+			at91_set_gpio_output(AT91_PIN_PA23, 1);		\
+			at91_set_gpio_value(AT91_PIN_PA23, bit);	\
+		}							\
+	} while (0)
+#define I2C_SCL(bit)	at91_set_pio_value(AT91_PIO_PORTA, 24, bit)
+#define I2C_DELAY	udelay(2)
+
+/* Boot options */
+#define CONFIG_SYS_LOAD_ADDR		0x23000000
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/* Environment settings */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		(512 << 10)
+#define CONFIG_ENV_SIZE			(256 << 10)
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BOOTARGS			"console=ttyS0,115200 ip=any"
+
+/* Console settings */
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE +		\
+					 sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+
+/* U-Boot memory settings */
+#define CONFIG_SYS_MALLOC_LEN		(1 << 20)
+
+/* Command line configuration */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_SOURCE
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#undef CONFIG_CMD_GPIO
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_PCA953X
+#define CONFIG_CMD_PCA953X_INFO
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/snow.h b/qemu/roms/u-boot/include/configs/snow.h
new file mode 100644
index 000000000..ed5c0b614
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/snow.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ *
+ * Configuration settings for the SAMSUNG EXYNOS5 Snow board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_SNOW_H
+#define __CONFIG_SNOW_H
+
+#include <configs/exynos5250-dt.h>
+
+#undef CONFIG_DEFAULT_DEVICE_TREE
+#define CONFIG_DEFAULT_DEVICE_TREE	exynos5250-snow
+
+#endif	/* __CONFIG_SNOW_H */
diff --git a/qemu/roms/u-boot/include/configs/snowball.h b/qemu/roms/u-boot/include/configs/snowball.h
new file mode 100644
index 000000000..dacb5604c
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/snowball.h
@@ -0,0 +1,246 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2009
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * #define DEBUG 1
+ */
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SNOWBALL
+#define CONFIG_SYS_ICACHE_OFF
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_BOARD_LATE_INIT
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_U8500
+
+#define CONFIG_SYS_MEMTEST_START	0x00000000
+#define CONFIG_SYS_MEMTEST_END	0x1FFFFFFF
+
+/*-----------------------------------------------------------------------
+ * Size of environment and malloc() pool
+ */
+/*
+ * If you use U-Boot as crash kernel, make sure that it does not overwrite
+ * information saved by kexec during panic. Kexec expects the start
+ * address of the executable 32K above "crashkernel" address.
+ */
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE		(8*1024)
+#define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + 256*1024)
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_ENV_OFFSET		0x0118000
+#define CONFIG_SYS_MMC_ENV_DEV          0              /* SLOT2: eMMC */
+
+/*
+ * PL011 Configuration
+ */
+#define CONFIG_PL011_SERIAL
+#define CONFIG_PL011_SERIAL_RLCR
+#define CONFIG_PL011_SERIAL_FLUSH_ON_INIT
+
+/*
+ * U8500 UART registers base for 3 serial devices
+ */
+#define CFG_UART0_BASE		0x80120000
+#define CFG_UART1_BASE		0x80121000
+#define CFG_UART2_BASE		0x80007000
+#define CFG_SERIAL0		CFG_UART0_BASE
+#define CFG_SERIAL1		CFG_UART1_BASE
+#define CFG_SERIAL2		CFG_UART2_BASE
+#define CONFIG_PL011_CLOCK	38400000
+#define CONFIG_PL01x_PORTS	{ (void *)CFG_SERIAL0, (void *)CFG_SERIAL1, \
+				  (void *)CFG_SERIAL2 }
+#define CONFIG_CONS_INDEX	2
+#define CONFIG_BAUDRATE		115200
+
+/*
+ * Devices and file systems
+ */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DOS_PARTITION
+
+/*
+ * Commands
+ */
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_CONSOLE
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_SOURCE
+
+#ifndef CONFIG_BOOTDELAY
+#define CONFIG_BOOTDELAY	1
+#endif
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+#undef CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND \
+"mmc dev 1; "								\
+	"if run loadbootscript; "					\
+		"then run bootscript; "					\
+	"else "								\
+		"if run mmcload; "					\
+			"then run mmcboot; "				\
+		"else "							\
+			"mmc dev 0; "					\
+			"if run emmcloadbootscript; "			\
+				"then run bootscript; "			\
+			"else "						\
+				"if run emmcload; "			\
+					"then run emmcboot; "		\
+				"else "					\
+					"echo No media to boot from; "	\
+				"fi; "					\
+			"fi; "						\
+		"fi; "							\
+	"fi; "
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"verify=n\0"							\
+	"loadaddr=0x00100000\0"						\
+	"console=ttyAMA2,115200n8\0"					\
+	"loadbootscript=fatload mmc 1:1 ${loadaddr} boot.scr\0"		\
+	"emmcloadbootscript=fatload mmc 0:2 ${loadaddr} boot.scr\0"	\
+	"bootscript=echo Running bootscript "				\
+		"from mmc ...; source ${loadaddr}\0"			\
+	"memargs256=mem=96M@0 mem_modem=32M@96M mem=32M@128M "		\
+		"hwmem=22M@160M pmem_hwb=42M@182M mem_mali=32@224M\0"	\
+	"memargs512=mem=96M@0 mem_modem=32M@96M hwmem=32M@128M "	\
+		"mem=64M@160M mem_mali=32M@224M "			\
+		"pmem_hwb=128M@256M mem=128M@384M\0"			\
+	"memargs1024=mem=128M@0 mali.mali_mem=32M@128M "		\
+		"hwmem=168M@M160M mem=48M@328M "			\
+		"mem_issw=1M@383M mem=640M@384M\0"			\
+	"memargs=setenv bootargs ${bootargs} ${memargs1024}\0"		\
+	"emmcload=fatload mmc 0:2 ${loadaddr} uImage\0"			\
+	"mmcload=fatload mmc 1:1 ${loadaddr} uImage\0"			\
+	"commonargs=setenv bootargs console=${console} "		\
+	"vmalloc=300M\0"						\
+	"emmcargs=setenv bootargs ${bootargs} "				\
+		"root=/dev/mmcblk0p3 "					\
+		"rootwait\0"						\
+	"addcons=setenv bootargs ${bootargs} "				\
+		"console=${console}\0"					\
+	"emmcboot=echo Booting from eMMC ...; "				\
+		"run commonargs emmcargs memargs; "			\
+		"bootm ${loadaddr}\0"					\
+	"mmcargs=setenv bootargs ${bootargs} "				\
+		"root=/dev/mmcblk1p2 "					\
+		"rootwait earlyprintk\0"				\
+	"mmcboot=echo Booting from external MMC ...; "			\
+		"run commonargs mmcargs memargs; "			\
+		"bootm ${loadaddr}\0"					\
+	"fdt_high=0x2BC00000\0"						\
+	"stdout=serial,usbtty\0"					\
+	"stdin=serial,usbtty\0"						\
+	"stderr=serial,usbtty\0"
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ */
+
+#define CONFIG_SYS_LONGHELP			/* undef to save memory     */
+#define CONFIG_SYS_PROMPT	"U8500 $ "	/* Monitor Command Prompt   */
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size  */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE \
+					+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	32	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */
+
+#undef	CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#define CONFIG_SYS_LOAD_ADDR		0x00100000 /* default load address */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1
+
+#define CONFIG_SYS_HUSH_PARSER		1
+#define CONFIG_CMDLINE_EDITING
+
+#define CONFIG_SETUP_MEMORY_TAGS	2
+#define CONFIG_INITRD_TAG		1
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs  */
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM_1			0x00000000	/* DDR-SDRAM Bank #1 */
+
+/*
+ * additions for new relocation code
+ */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_MAX_RAM_SIZE	0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x100000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_SDRAM_BASE + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SYS_GBL_DATA_OFFSET
+
+/* landing address before relocation */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE            0x0
+#endif
+
+/*
+ * MMC related configs
+ */
+#define CONFIG_ARM_PL180_MMCI
+#define MMC_BLOCK_SIZE			512
+#define CFG_EMMC_BASE                   0x80114000
+#define CFG_MMC_BASE                    0x80126000
+
+/*
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * base register values for U8500
+ */
+#define CFG_PRCMU_BASE		0x80157000	/* Power, reset and clock */
+
+
+/*
+ * U8500 GPIO register base for 9 banks
+ */
+#define CONFIG_DB8500_GPIO
+#define CFG_GPIO_0_BASE			0x8012E000
+#define CFG_GPIO_1_BASE			0x8012E080
+#define CFG_GPIO_2_BASE			0x8000E000
+#define CFG_GPIO_3_BASE			0x8000E080
+#define CFG_GPIO_4_BASE			0x8000E100
+#define CFG_GPIO_5_BASE			0x8000E180
+#define CFG_GPIO_6_BASE			0x8011E000
+#define CFG_GPIO_7_BASE			0x8011E080
+#define CFG_GPIO_8_BASE			0xA03FE000
+
+#define CFG_FSMC_BASE		0x80000000	/* FSMC Controller */
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/socfpga_cyclone5.h b/qemu/roms/u-boot/include/configs/socfpga_cyclone5.h
new file mode 100644
index 000000000..025424975
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/socfpga_cyclone5.h
@@ -0,0 +1,240 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/socfpga_base_addrs.h>
+#include "../../board/altera/socfpga/pinmux_config.h"
+#include "../../board/altera/socfpga/pll_config.h"
+
+/*
+ * High level configuration
+ */
+/* Virtual target or real hardware */
+#define CONFIG_SOCFPGA_VIRTUAL_TARGET
+
+#define CONFIG_ARMV7
+#define CONFIG_SYS_DCACHE_OFF
+#undef CONFIG_USE_IRQ
+
+#define CONFIG_MISC_INIT_R
+#define CONFIG_SINGLE_BOOTLOADER
+#define CONFIG_SOCFPGA
+
+/* base address for .text section */
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define CONFIG_SYS_TEXT_BASE		0x08000040
+#else
+#define CONFIG_SYS_TEXT_BASE		0x01000040
+#endif
+#define CONFIG_SYS_LOAD_ADDR		0x7fc0
+
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		256
+/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT		"SOCFPGA_CYCLONE5 # "
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/*
+ * Display CPU and Board Info
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/*
+ * Enable early stage initialization at C environment
+ */
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* flat device tree */
+#define CONFIG_OF_LIBFDT
+/* skip updating the FDT blob */
+#define CONFIG_FDT_BLOB_SKIP_UPDATE
+/* Initial Memory map size for Linux, minus 4k alignment for DFT blob */
+#define CONFIG_SYS_BOOTMAPSZ		((256*1024*1024) - (4*1024))
+
+#define CONFIG_SPL_RAM_DEVICE
+#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start))
+#define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start)
+
+/*
+ * Memory allocation (MALLOC)
+ */
+/* Room required on the stack for the environment data */
+#define CONFIG_ENV_SIZE			1024
+/* Size of DRAM reserved for malloc() use */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
+
+/* SP location before relocation, must use scratch RAM */
+#define CONFIG_SYS_INIT_RAM_ADDR	0xFFFF0000
+/* Reserving 0x100 space at back of scratch RAM for debug info */
+#define CONFIG_SYS_INIT_RAM_SIZE	(0x10000 - 0x100)
+/* Stack pointer prior relocation, must situated at on-chip RAM */
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_SYS_NO_FLASH
+#include <config_cmd_default.h>
+/* FAT file system support */
+#define CONFIG_CMD_FAT
+
+
+/*
+ * Misc
+ */
+#define CONFIG_DOS_PARTITION            1
+
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_PARTITIONS
+#endif
+
+/*
+ * Environment setup
+ */
+
+/* Delay before automatically booting the default image */
+#define CONFIG_BOOTDELAY		3
+/* Enable auto completion of commands using TAB */
+#define CONFIG_AUTO_COMPLETE
+/* use "hush" command parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_CMD_RUN
+
+#define CONFIG_BOOTCOMMAND "run ramboot"
+
+/*
+ * arguments passed to the bootm command. The value of
+ * CONFIG_BOOTARGS goes into the environment value "bootargs".
+ * Do note the value will overide also the chosen node in FDT blob.
+ */
+#define CONFIG_BOOTARGS "console=ttyS0,57600,mem=256M@0x0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"verify=n\0" \
+	"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
+		"bootm ${loadaddr} - ${fdt_addr}\0" \
+	"bootimage=uImage\0" \
+	"fdt_addr=100\0" \
+	"fsloadcmd=ext2load\0" \
+		"bootm ${loadaddr} - ${fdt_addr}\0" \
+	"qspiroot=/dev/mtdblock0\0" \
+	"qspirootfstype=jffs2\0" \
+	"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
+		" root=${qspiroot} rw rootfstype=${qspirootfstype};"\
+		"bootm ${loadaddr} - ${fdt_addr}\0"
+
+/* using environment setting for stdin, stdout, stderr */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+/* Enable the call to overwrite_console() */
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+/* Enable overwrite of previous console environment settings */
+#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+
+/* max number of command args	 */
+#define CONFIG_SYS_MAXARGS		16
+
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * SDRAM Memory Map
+ */
+/* We have 1 bank of DRAM */
+#define CONFIG_NR_DRAM_BANKS		1
+/* SDRAM Bank #1 */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+/* SDRAM memory size */
+#define PHYS_SDRAM_1_SIZE		0x40000000
+
+#define PHYS_SDRAM_1			CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_START	0x00000000
+#define CONFIG_SYS_MEMTEST_END		PHYS_SDRAM_1_SIZE
+
+/*
+ * NS16550 Configuration
+ */
+#define UART0_BASE			SOCFPGA_UART0_ADDRESS
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK
+#define CONFIG_CONS_INDEX               1
+#define CONFIG_SYS_NS16550_COM1		UART0_BASE
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define V_NS16550_CLK			1000000
+#else
+#define V_NS16550_CLK			100000000
+#endif
+#define CONFIG_BAUDRATE			115200
+
+/*
+ * FLASH
+ */
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * L4 OSC1 Timer 0
+ */
+/* This timer use eosc1 where the clock frequency is fixed
+ * throughout any condition */
+#define CONFIG_SYS_TIMERBASE		SOCFPGA_OSC1TIMER0_ADDRESS
+/* reload value when timer count to zero */
+#define TIMER_LOAD_VAL			0xFFFFFFFF
+/* Timer info */
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define CONFIG_SYS_TIMER_RATE		2400000
+#else
+#define CONFIG_SYS_TIMER_RATE		25000000
+#endif
+#define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMERBASE + 0x4)
+
+#define CONFIG_ENV_IS_NOWHERE
+
+/*
+ * SPL "Second Program Loader" aka Initial Software
+ */
+
+/* Enable building of SPL globally */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+
+/* TEXT_BASE for linking the SPL binary */
+#define CONFIG_SPL_TEXT_BASE		0xFFFF0000
+
+/* Stack size for SPL */
+#define CONFIG_SPL_STACK_SIZE		(4 * 1024)
+
+/* MALLOC size for SPL */
+#define CONFIG_SPL_MALLOC_SIZE		(5 * 1024)
+
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_BOARD_INIT
+
+#define CHUNKSZ_CRC32			(1 * 1024)
+
+#define CONFIG_CRC32_VERIFY
+
+/* Linker script for SPL */
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds"
+
+/* Support for common/libcommon.o in SPL binary */
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+/* Support for lib/libgeneric.o in SPL binary */
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/socrates.h b/qemu/roms/u-boot/include/configs/socrates.h
new file mode 100644
index 000000000..c654a0e4e
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/socrates.h
@@ -0,0 +1,449 @@
+/*
+ * (C) Copyright 2008
+ * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
+ *
+ * Wolfgang Denk <wd@denx.de>
+ * Copyright 2004 Freescale Semiconductor.
+ * (C) Copyright 2002,2003 Motorola,Inc.
+ * Xianghua Xiao <X.Xiao@motorola.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Socrates
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* new uImage format support */
+#define CONFIG_FIT		1
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_FIT_VERBOSE	1 /* enable fit_format_{error,warning}() */
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE		1	/* BOOKE			*/
+#define CONFIG_E500		1	/* BOOKE e500 family		*/
+#define CONFIG_MPC8544		1
+#define CONFIG_SOCRATES		1
+
+#define	CONFIG_SYS_TEXT_BASE	0xfff80000
+
+#define CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+
+#define CONFIG_TSEC_ENET		/* tsec ethernet support	*/
+
+#define CONFIG_MISC_INIT_R	1	/* Call misc_init_r		*/
+#define CONFIG_BOARD_EARLY_INIT_R 1	/* Call board_early_init_r	*/
+
+#define CONFIG_FSL_LAW		1	/* Use common FSL init code */
+
+/*
+ * Only possible on E500 Version 2 or newer cores.
+ */
+#define CONFIG_ENABLE_36BIT_PHYS	1
+
+/*
+ * sysclk for MPC85xx
+ *
+ * Two valid values are:
+ *    33000000
+ *    66000000
+ *
+ * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
+ * is likely the desired value here, so that is now the default.
+ * The board, however, can run at 66MHz.  In any event, this value
+ * must match the settings of some switches.  Details can be found
+ * in the README.mpc85xxads.
+ */
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_CLK_FREQ	66666666
+#endif
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache		*/
+#define CONFIG_BTB			/* toggle branch predition	*/
+
+#define CONFIG_SYS_INIT_DBCR DBCR_IDM		/* Enable Debug Exceptions	*/
+
+#undef	CONFIG_SYS_DRAM_TEST			/* memory test, takes time	*/
+#define CONFIG_SYS_MEMTEST_START	0x00400000
+#define CONFIG_SYS_MEMTEST_END		0x00C00000
+
+#define CONFIG_SYS_CCSRBAR		0xE0000000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+
+/* DDR Setup */
+#define CONFIG_SYS_FSL_DDR2
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
+#define CONFIG_DDR_SPD
+
+#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
+
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	2
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x50	/* CTLR 0 DIMM 0 */
+
+#define CONFIG_DDR_DEFAULT_CL	30		/* CAS latency 3	*/
+
+/* Hardcoded values, to use instead of SPD */
+#define CONFIG_SYS_DDR_CS0_BNDS		0x0000000f
+#define CONFIG_SYS_DDR_CS0_CONFIG		0x80010102
+#define CONFIG_SYS_DDR_TIMING_0		0x00260802
+#define CONFIG_SYS_DDR_TIMING_1		0x3935D322
+#define CONFIG_SYS_DDR_TIMING_2		0x14904CC8
+#define CONFIG_SYS_DDR_MODE			0x00480432
+#define CONFIG_SYS_DDR_INTERVAL		0x030C0100
+#define CONFIG_SYS_DDR_CONFIG_2		0x04400000
+#define CONFIG_SYS_DDR_CONFIG			0xC3008000
+#define CONFIG_SYS_DDR_CLK_CONTROL		0x03800000
+#define CONFIG_SYS_SDRAM_SIZE			256 /* in Megs */
+
+/*
+ * Flash on the LocalBus
+ */
+#define CONFIG_SYS_LBC_CACHE_BASE	0xf0000000	/* Localbus cacheable	 */
+
+#define CONFIG_SYS_FLASH0		0xFE000000
+#define CONFIG_SYS_FLASH1		0xFC000000
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
+
+#define CONFIG_SYS_LBC_FLASH_BASE	CONFIG_SYS_FLASH1	/* Localbus flash start	*/
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH	*/
+
+#define CONFIG_SYS_BR0_PRELIM		0xfe001001	/* port size 16bit	*/
+#define CONFIG_SYS_OR0_PRELIM		0xfe000030	/* 32MB Flash		*/
+#define CONFIG_SYS_BR1_PRELIM		0xfc001001	/* port size 16bit	*/
+#define CONFIG_SYS_OR1_PRELIM		0xfe000030	/* 32MB Flash		*/
+
+#define CONFIG_SYS_FLASH_CFI				/* flash is CFI compat.	*/
+#define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver*/
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256		/* sectors per device	*/
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms)	*/
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor	*/
+
+#define CONFIG_SYS_LBC_LCRR		0x00030004    /* LB clock ratio reg	*/
+#define CONFIG_SYS_LBC_LBCR		0x00000000    /* LB config reg		*/
+#define CONFIG_SYS_LBC_LSRT		0x20000000    /* LB sdram refresh timer	*/
+#define CONFIG_SYS_LBC_MRTPR		0x20000000    /* LB refresh timer presc.*/
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address	*/
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size used area in RAM*/
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(384 * 1024)	/* Reserve 384KiB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(4 << 20)	/* Reserve 4 MB for malloc */
+
+/* FPGA and NAND */
+#define CONFIG_SYS_FPGA_BASE		0xc0000000
+#define CONFIG_SYS_FPGA_SIZE		0x00100000	/* 1 MB		*/
+#define CONFIG_SYS_HMI_BASE		0xc0010000
+#define CONFIG_SYS_BR3_PRELIM		0xc0001881	/* UPMA, 32-bit */
+#define CONFIG_SYS_OR3_PRELIM		0xfff00000	/* 1 MB 	*/
+
+#define CONFIG_SYS_NAND_BASE		(CONFIG_SYS_FPGA_BASE + 0x70)
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_CMD_NAND
+
+/* LIME GDC */
+#define CONFIG_SYS_LIME_BASE		0xc8000000
+#define CONFIG_SYS_LIME_SIZE		0x04000000	/* 64 MB	*/
+#define CONFIG_SYS_BR2_PRELIM		0xc80018a1	/* UPMB, 32-bit	*/
+#define CONFIG_SYS_OR2_PRELIM		0xfc000000	/* 64 MB	*/
+
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_MB862xx
+#define CONFIG_VIDEO_MB862xx_ACCEL
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_CONSOLE_EXTRA_INFO
+#define VIDEO_FB_16BPP_PIXEL_SWAP
+#define VIDEO_FB_16BPP_WORD_SWAP
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(2 << 20)	/* decompressed img */
+
+/* SDRAM Clock frequency, 100MHz (0x0000) or 133MHz (0x10000) */
+#define CONFIG_SYS_MB862xx_CCF		0x10000
+/* SDRAM parameter */
+#define CONFIG_SYS_MB862xx_MMR		0x4157BA63
+
+/* Serial Port */
+
+#define CONFIG_CONS_INDEX     1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+
+#define CONFIG_BAUDRATE         115200
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_AUTO_COMPLETE	1	/* add autocompletion support */
+#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
+
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	102124
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	102124
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+
+/* I2C RTC */
+#define CONFIG_RTC_RX8025		/* Use Epson rx8025 rtc via i2c	*/
+#define CONFIG_SYS_I2C_RTC_ADDR	0x32	/* at address 0x32		*/
+
+/* I2C W83782G HW-Monitoring IC */
+#define CONFIG_SYS_I2C_W83782G_ADDR	0x28	/* W83782G address 		*/
+
+/* I2C temp sensor */
+/* Socrates uses Maxim's	DS75, which is compatible with LM75 */
+#define CONFIG_DTT_LM75		1
+#define CONFIG_DTT_SENSORS	{4}		/* Sensor addresses	*/
+#define CONFIG_SYS_DTT_MAX_TEMP	125
+#define CONFIG_SYS_DTT_LOW_TEMP	-55
+#define CONFIG_SYS_DTT_HYSTERESIS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1.
+ */
+#define CONFIG_SYS_PCI_PHYS		0x80000000	/* 1G PCI TLB */
+
+/* PCI is clocked by the external source at 33 MHz */
+#define CONFIG_PCI_CLK_FREQ	33000000
+#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M			*/
+#define CONFIG_SYS_PCI1_IO_BASE	0xE2000000
+#define CONFIG_SYS_PCI1_IO_PHYS	CONFIG_SYS_PCI1_IO_BASE
+#define CONFIG_SYS_PCI1_IO_SIZE	0x01000000	/* 16M			*/
+
+#if defined(CONFIG_PCI)
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
+#endif	/* CONFIG_PCI */
+
+
+#define CONFIG_MII		1	/* MII PHY management */
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_TSEC3	1
+#define CONFIG_TSEC3_NAME	"TSEC1"
+#undef CONFIG_MPC85XX_FEC
+
+#define TSEC1_PHY_ADDR		0
+#define TSEC3_PHY_ADDR		1
+
+#define TSEC1_PHYIDX		0
+#define TSEC3_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC3_FLAGS		TSEC_GIGABIT
+
+/* Options are: TSEC[0,1] */
+#define CONFIG_ETHPRIME		"TSEC0"
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env	*/
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x4000
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define	CONFIG_TIMESTAMP		/* Print image info with ts	*/
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BMP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DTT
+#undef CONFIG_CMD_EEPROM
+#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_MII
+#undef CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_REGINFO
+
+#if defined(CONFIG_PCI)
+    #define CONFIG_CMD_PCI
+#endif
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address		*/
+
+#if defined(CONFIG_CMD_KGDB)
+    #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+    #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buf Size	*/
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux	*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port*/
+#endif
+
+
+#define CONFIG_LOADADDR	 200000		/* default addr for tftp & bootm*/
+
+#define CONFIG_BOOTDELAY 1		/* -1 disables auto-boot	*/
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Welcome on the ABB Socrates Board;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS		/* the boot command will set bootargs	*/
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"consdev=ttyS0\0"						\
+	"uboot_file=/home/tftp/syscon3/u-boot.bin\0"			\
+	"bootfile=/home/tftp/syscon3/uImage\0"				\
+	"fdt_file=/home/tftp/syscon3/socrates.dtb\0"			\
+	"initrd_file=/home/tftp/syscon3/uinitrd.gz\0"			\
+	"uboot_addr=FFFA0000\0"						\
+	"kernel_addr=FE000000\0"					\
+	"fdt_addr=FE1E0000\0"						\
+	"ramdisk_addr=FE200000\0"					\
+	"fdt_addr_r=B00000\0"						\
+	"kernel_addr_r=200000\0"					\
+	"ramdisk_addr_r=400000\0"					\
+	"rootpath=/opt/eldk/ppc_85xxDP\0"				\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=$serverip:$rootpath\0"				\
+	"addcons=setenv bootargs $bootargs "				\
+		"console=$consdev,$baudrate\0"				\
+	"addip=setenv bootargs $bootargs "				\
+		"ip=$ipaddr:$serverip:$gatewayip:$netmask"		\
+		":$hostname:$netdev:off panic=1\0"			\
+	"boot_nor=run ramargs addcons;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
+		"tftp ${fdt_addr_r} ${fdt_file}; "			\
+		"run nfsargs addip addcons;"				\
+		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
+	"update_uboot=tftp 100000 ${uboot_file};"			\
+		"protect off fffa0000 ffffffff;"			\
+		"era fffa0000 ffffffff;"				\
+		"cp.b 100000 fffa0000 ${filesize};"			\
+		"setenv filesize;saveenv\0"				\
+	"update_kernel=tftp 100000 ${bootfile};"			\
+		"era fe000000 fe1dffff;"				\
+		"cp.b 100000 fe000000 ${filesize};"			\
+		"setenv filesize;saveenv\0"				\
+	"update_fdt=tftp 100000 ${fdt_file};" 				\
+		"era fe1e0000 fe1fffff;"				\
+		"cp.b 100000 fe1e0000 ${filesize};"			\
+		"setenv filesize;saveenv\0"				\
+	"update_initrd=tftp 100000 ${initrd_file};" 			\
+		"era fe200000 fe9fffff;"				\
+		"cp.b 100000 fe200000 ${filesize};"			\
+		"setenv filesize;saveenv\0"				\
+	"clean_data=era fea00000 fff5ffff\0"				\
+	"usbargs=setenv bootargs root=/dev/sda1 rw\0" 			\
+	"load_usb=usb start;" 						\
+		"ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0"	\
+	"boot_usb=run load_usb usbargs addcons;"			\
+		"bootm ${kernel_addr_r} - ${fdt_addr};"			\
+		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
+	""
+#define CONFIG_BOOTCOMMAND	"run boot_nor"
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+/* USB support */
+#define CONFIG_USB_OHCI_NEW		1
+#define CONFIG_PCI_OHCI			1
+#define CONFIG_PCI_OHCI_DEVNO		3 /* Number in PCI list */
+#define CONFIG_PCI_EHCI_DEVNO		(CONFIG_PCI_OHCI_DEVNO / 2)
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"ohci_pci"
+#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS	1
+#define CONFIG_DOS_PARTITION		1
+#define CONFIG_USB_STORAGE		1
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/spc1920.h b/qemu/roms/u-boot/include/configs/spc1920.h
new file mode 100644
index 000000000..127de000f
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/spc1920.h
@@ -0,0 +1,405 @@
+/*
+ * (C) Copyright 2006
+ * Markus Klotzbuecher, DENX Software Engineering, mk@denx.de
+ *
+ * Configuation settings for the SPC1920 board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __H
+#define __CONFIG_H
+
+#define CONFIG_SPC1920			1	/* SPC1920 board */
+#define CONFIG_MPC885			1	/* MPC885 CPU */
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
+
+#define	CONFIG_8xx_CONS_SMC1		/* Console is on SMC1 */
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+
+#define CONFIG_MII
+#define CONFIG_MII_INIT		1
+#undef CONFIG_ETHER_ON_FEC1
+#define CONFIG_ETHER_ON_FEC2
+#define FEC_ENET
+#define CONFIG_FEC2_PHY		1
+
+#define CONFIG_BAUDRATE		19200
+
+/* use PLD CLK4 instead of brg */
+#define CONFIG_SYS_SPC1920_SMC1_CLK4
+
+#define CONFIG_8xx_OSCLK		10000000 /* 10 MHz oscillator on EXTCLK  */
+#define CONFIG_8xx_CPUCLK_DEFAULT	50000000
+#define CONFIG_SYS_8xx_CPUCLK_MIN		40000000
+#define CONFIG_SYS_8xx_CPUCLK_MAX		133000000
+
+#define CONFIG_SYS_RESET_ADDRESS		0xC0000000
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_LAST_STAGE_INIT
+
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_NFSBOOTCOMMAND							\
+    "dhcp;"									\
+    "setenv bootargs root=/dev/nfs rw nfsroot=$rootpath "			\
+    "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;"		\
+    "bootm"
+
+#define CONFIG_BOOTCOMMAND							\
+    "setenv bootargs root=/dev/mtdblock2 rw mtdparts=phys:1280K(ROM)ro,-(root) "\
+    "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;"		\
+    "bootm fe080000"
+
+#undef CONFIG_BOOTARGS
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+#define CONFIG_BZIP2	 /* include support for bzip2 compressed images */
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#define CONFIG_SYS_HUSH_PARSER
+
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size	*/
+#else
+#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#endif
+
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size	*/
+#define	CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x00100000
+
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 2400, 4800, 9600, 19200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xF0000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 KB for monitor	*/
+
+#ifdef CONFIG_BZIP2
+#define	CONFIG_SYS_MALLOC_LEN		(2500 << 10)	/* Reserve ~2.5 MB for malloc()	*/
+#else
+#define	CONFIG_SYS_MALLOC_LEN		(384 << 10)	/* Reserve 384 kB for malloc()	*/
+#endif /* CONFIG_BZIP2 */
+
+#define	CONFIG_SYS_ALLOC_DPRAM		1	/* use allocation routines	*/
+
+/*
+ * Flash
+ */
+/*-----------------------------------------------------------------------
+ * Flash organisation
+ */
+#define CONFIG_SYS_FLASH_BASE          0xFE000000
+#define CONFIG_SYS_FLASH_CFI                           /* The flash is CFI compatible  */
+#define CONFIG_FLASH_CFI_DRIVER                    /* Use common CFI driver        */
+#define CONFIG_SYS_MAX_FLASH_BANKS     1               /* Max number of flash banks    */
+#define CONFIG_SYS_MAX_FLASH_SECT      128             /* Max num of sects on one chip */
+
+/* Environment is in flash */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE       0x40000         /* We use one complete sector   */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+
+#define CONFIG_ENV_OVERWRITE
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+
+#ifdef CONFIG_CMD_DATE
+# define CONFIG_RTC_DS3231
+# define CONFIG_SYS_I2C_RTC_ADDR      0x68
+#endif
+
+/*-----------------------------------------------------------------------
+ * I2C configuration
+ */
+#if defined(CONFIG_CMD_I2C)
+/* enable I2C and select the hardware/software driver */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED	93000	/* 93 kHz is supposed to work */
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PB_SCL         0x00000020      /* PB 26 */
+#define PB_SDA         0x00000010      /* PB 27 */
+
+#define I2C_INIT       (immr->im_cpm.cp_pbdir |=  PB_SCL)
+#define I2C_ACTIVE     (immr->im_cpm.cp_pbdir |=  PB_SDA)
+#define I2C_TRISTATE   (immr->im_cpm.cp_pbdir &= ~PB_SDA)
+#define I2C_READ       ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+#define I2C_SDA(bit)   if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
+		       else    immr->im_cpm.cp_pbdat &= ~PB_SDA
+#define I2C_SCL(bit)   if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
+		       else    immr->im_cpm.cp_pbdat &= ~PB_SCL
+#define I2C_DELAY      udelay(2)       /* 1/4 I2C clock duration */
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CONFIG_SYS_SIUMCR      (SIUMCR_FRC)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+/* #define CONFIG_SYS_SCCR	SCCR_TBS */
+#define CONFIG_SYS_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * DER - Debug Enable Register
+ *-----------------------------------------------------------------------
+ * Set to zero to prevent the processor from entering debug mode
+ */
+#define CONFIG_SYS_DER		 0
+
+
+/* Because of the way the 860 starts up and assigns CS0 the entire
+ * address space, we have to set the memory controller differently.
+ * Normally, you write the option register first, and then enable the
+ * chip select by writing the base register.  For CS0, you must write
+ * the base register first, followed by the option register.
+ */
+
+
+/*
+ * Init Memory Controller:
+ */
+
+/* BR0 and OR0 (FLASH) */
+#define FLASH_BASE0_PRELIM	CONFIG_SYS_FLASH_BASE	/* FLASH bank #0 */
+
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+				 OR_SCY_6_CLK | OR_EHTR | OR_BI)
+
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+
+/*
+ * SDRAM CS1 UPMB
+ */
+#define	CONFIG_SYS_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE_PRELIM CONFIG_SYS_SDRAM_BASE
+#define SDRAM_MAX_SIZE	0x4000000 /* max 64 MB */
+
+#define CONFIG_SYS_PRELIM_OR1_AM	0xF0000000
+/* #define CONFIG_SYS_OR1_TIMING  OR_CSNT_SAM/\*  | OR_G5LS /\\* *\\/ *\/ */
+#define SDRAM_TIMING	OR_SCY_0_CLK	/* SDRAM-Timing */
+
+#define CONFIG_SYS_OR1_PRELIM	(CONFIG_SYS_PRELIM_OR1_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING)
+#define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V)
+
+/* #define CONFIG_SYS_OR1_FINAL   ((CONFIG_SYS_OR1_AM & OR_AM_MSK) | CONFIG_SYS_OR1_TIMING) */
+/* #define CONFIG_SYS_BR1_FINAL   ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V) */
+
+#define CONFIG_SYS_PTB_PER_CLK	((4096 * 16 * 1000) / (4 * 64))
+#define CONFIG_SYS_PTA_PER_CLK 195
+#define CONFIG_SYS_MBMR_PTB	195
+#define CONFIG_SYS_MPTPR	MPTPR_PTP_DIV16
+#define CONFIG_SYS_MAR		0x88
+
+#define CONFIG_SYS_MBMR_8COL  ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \
+			MBMR_AMB_TYPE_0 | \
+			MBMR_G0CLB_A10 | \
+			MBMR_DSB_1_CYCL | \
+			MBMR_RLFB_1X | \
+			MBMR_WLFB_1X | \
+			MBMR_TLFB_4X) /* 0x04804114 */ /* 0x10802114 */
+
+#define CONFIG_SYS_MBMR_9COL  ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \
+			MBMR_AMB_TYPE_1 | \
+			MBMR_G0CLB_A10 | \
+			MBMR_DSB_1_CYCL | \
+			MBMR_RLFB_1X | \
+			MBMR_WLFB_1X | \
+			MBMR_TLFB_4X) /* 0x04804114 */ /* 0x10802114 */
+
+
+/*
+ * DSP Host Port Interface CS3
+ */
+#define CONFIG_SYS_SPC1920_HPI_BASE   0x90000000
+#define CONFIG_SYS_PRELIM_OR3_AM      0xF8000000
+
+#define CONFIG_SYS_OR3         (CONFIG_SYS_PRELIM_OR3_AM | \
+				       OR_G5LS | \
+				       OR_SCY_0_CLK | \
+				       OR_BI)
+
+#define CONFIG_SYS_BR3 ((CONFIG_SYS_SPC1920_HPI_BASE & BR_BA_MSK) | \
+					       BR_MS_UPMA | \
+					       BR_PS_16 | \
+					       BR_V)
+
+#define CONFIG_SYS_MAMR (MAMR_GPL_A4DIS | \
+		MAMR_RLFA_5X | \
+		MAMR_WLFA_5X)
+
+#define CONFIG_SPC1920_HPI_TEST
+
+#ifdef CONFIG_SPC1920_HPI_TEST
+#define HPI_REG(x)             (*((volatile u16 *) (CONFIG_SYS_SPC1920_HPI_BASE + x)))
+#define HPI_HPIC_1             HPI_REG(0)
+#define HPI_HPIC_2             HPI_REG(2)
+#define HPI_HPIA_1             HPI_REG(0x2000008)
+#define HPI_HPIA_2             HPI_REG(0x2000008 + 2)
+#define HPI_HPID_INC_1         HPI_REG(0x1000004)
+#define HPI_HPID_INC_2         HPI_REG(0x1000004 + 2)
+#define HPI_HPID_NOINC_1       HPI_REG(0x300000c)
+#define HPI_HPID_NOINC_2       HPI_REG(0x300000c + 2)
+#endif /* CONFIG_SPC1920_HPI_TEST */
+
+/*
+ * Ramtron FM18L08 FRAM 32KB on CS4
+ */
+#define CONFIG_SYS_SPC1920_FRAM_BASE	0x80100000
+#define CONFIG_SYS_PRELIM_OR4_AM	0xffff8000
+#define CONFIG_SYS_OR4		(CONFIG_SYS_PRELIM_OR4_AM | \
+					OR_ACS_DIV2 | \
+					OR_BI | \
+					OR_SCY_4_CLK | \
+					OR_TRLX)
+
+#define CONFIG_SYS_BR4 ((CONFIG_SYS_SPC1920_FRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
+
+/*
+ * PLD CS5
+ */
+#define CONFIG_SYS_SPC1920_PLD_BASE	0x80000000
+#define CONFIG_SYS_PRELIM_OR5_AM	0xffff8000
+
+#define CONFIG_SYS_OR5_PRELIM		(CONFIG_SYS_PRELIM_OR5_AM | \
+					OR_CSNT_SAM | \
+					OR_ACS_DIV1 | \
+					OR_BI | \
+					OR_SCY_0_CLK | \
+					OR_TRLX)
+
+#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_SPC1920_PLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/spear-common.h b/qemu/roms/u-boot/include/configs/spear-common.h
new file mode 100644
index 000000000..c0eba3721
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/spear-common.h
@@ -0,0 +1,241 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SPEAR_COMMON_H
+#define _SPEAR_COMMON_H
+/*
+ * Common configurations used for both spear3xx as well as spear6xx
+ */
+
+/* U-boot Load Address */
+#define CONFIG_SYS_TEXT_BASE			0x00700000
+
+/* Ethernet driver configuration */
+#define CONFIG_MII
+#define CONFIG_DESIGNWARE_ETH
+#define CONFIG_NET_MULTI
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_RESET_DELAY			10000		/* in usec */
+#define CONFIG_PHY_GIGE			/* Include GbE speed/duplex detection */
+
+/* USBD driver configuration */
+#if defined(CONFIG_SPEAR_USBTTY)
+#define CONFIG_DW_UDC
+#define CONFIG_USB_DEVICE
+#define CONFIG_USBD_HS
+#define CONFIG_USB_TTY
+
+#define CONFIG_USBD_PRODUCT_NAME		"SPEAr SoC"
+#define CONFIG_USBD_MANUFACTURER		"ST Microelectronics"
+
+#endif
+
+#define CONFIG_EXTRA_ENV_USBTTY			"usbtty=cdc_acm\0"
+
+/* I2C driver configuration */
+#define CONFIG_HARD_I2C
+#define CONFIG_DW_I2C
+#if defined(CONFIG_SPEAR600)
+#define CONFIG_SYS_I2C_BASE			0xD0200000
+#elif defined(CONFIG_SPEAR300)
+#define CONFIG_SYS_I2C_BASE			0xD0180000
+#elif defined(CONFIG_SPEAR310)
+#define CONFIG_SYS_I2C_BASE			0xD0180000
+#elif defined(CONFIG_SPEAR320)
+#define CONFIG_SYS_I2C_BASE			0xD0180000
+#endif
+#define CONFIG_SYS_I2C_SPEED			400000
+#define CONFIG_SYS_I2C_SLAVE			0x02
+
+#define CONFIG_I2C_CHIPADDRESS			0x50
+
+/* Timer, HZ specific defines */
+
+/* Flash configuration */
+#if defined(CONFIG_FLASH_PNOR)
+#define CONFIG_SPEAR_EMI
+#else
+#define CONFIG_ST_SMI
+#endif
+
+#if defined(CONFIG_ST_SMI)
+
+#define CONFIG_SYS_MAX_FLASH_BANKS		2
+#define CONFIG_SYS_FLASH_BASE			0xF8000000
+#define CONFIG_SYS_CS1_FLASH_BASE		0xF9000000
+#define CONFIG_SYS_FLASH_BANK_SIZE		0x01000000
+#define CONFIG_SYS_FLASH_ADDR_BASE		{CONFIG_SYS_FLASH_BASE, \
+						CONFIG_SYS_CS1_FLASH_BASE}
+#define CONFIG_SYS_MAX_FLASH_SECT		128
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT		(3 * CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT		(3 * CONFIG_SYS_HZ)
+
+#endif
+
+/*
+ * Serial Configuration (PL011)
+ * CONFIG_PL01x_PORTS is defined in specific files
+ */
+#define CONFIG_PL011_SERIAL
+#define CONFIG_PL011_CLOCK			(48 * 1000 * 1000)
+#define CONFIG_CONS_INDEX			0
+#define CONFIG_BAUDRATE				115200
+#define CONFIG_SYS_BAUDRATE_TABLE		{ 9600, 19200, 38400, \
+						57600, 115200 }
+
+#define CONFIG_SYS_LOADS_BAUD_CHANGE
+
+/* NAND FLASH Configuration */
+#define CONFIG_SYS_NAND_SELF_INIT
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_NAND_FSMC
+#define CONFIG_SYS_MAX_NAND_DEVICE		1
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_SYS_NAND_QUIET_TEST
+
+/*
+ * Command support defines
+ */
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+
+/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <config_cmd_default.h>
+
+/*
+ * Default Environment Varible definitions
+ */
+#if defined(CONFIG_SPEAR_USBTTY)
+#define CONFIG_BOOTDELAY			-1
+#else
+#define CONFIG_BOOTDELAY			1
+#endif
+
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * U-Boot Environment placing definitions.
+ */
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+#ifdef CONFIG_ST_SMI
+/*
+ * Environment is in serial NOR flash
+ */
+#define CONFIG_SYS_MONITOR_LEN			0x00040000
+#define CONFIG_ENV_SECT_SIZE			0x00010000
+#define CONFIG_FSMTDBLK				"/dev/mtdblock3 "
+
+#define CONFIG_BOOTCOMMAND			"bootm 0xf8050000"
+
+#elif defined(CONFIG_SPEAR_EMI)
+/*
+ * Environment is in parallel NOR flash
+ */
+#define CONFIG_SYS_MONITOR_LEN			0x00060000
+#define CONFIG_ENV_SECT_SIZE			0x00020000
+#define CONFIG_FSMTDBLK				"/dev/mtdblock3 "
+
+#define CONFIG_BOOTCOMMAND			"cp.b 0x50080000 0x1600000 " \
+						"0x4C0000; bootm 0x1600000"
+#endif
+
+#define CONFIG_ENV_ADDR				(CONFIG_SYS_FLASH_BASE + \
+						CONFIG_SYS_MONITOR_LEN)
+#elif defined(CONFIG_ENV_IS_IN_NAND)
+/*
+ * Environment is in NAND
+ */
+
+#define CONFIG_ENV_OFFSET			0x60000
+#define CONFIG_ENV_RANGE			0x10000
+#define CONFIG_FSMTDBLK				"/dev/mtdblock7 "
+
+#define CONFIG_BOOTCOMMAND			"nand read.jffs2 0x1600000 " \
+						"0x80000 0x4C0000; " \
+						"bootm 0x1600000"
+#endif
+
+#define CONFIG_BOOTARGS				"console=ttyAMA0,115200 " \
+						"mem=128M " \
+						"root="CONFIG_FSMTDBLK \
+						"rootfstype=jffs2"
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"bootp; "							\
+	"setenv bootargs root=/dev/nfs rw "				\
+	"nfsroot=$(serverip):$(rootpath) "				\
+	"ip=$(ipaddr):$(serverip):$(gatewayip):"			\
+			"$(netmask):$(hostname):$(netdev):off "		\
+			"console=ttyAMA0,115200 $(othbootargs);"	\
+	"bootm; "
+
+#define CONFIG_RAMBOOTCOMMAND						\
+	"setenv bootargs root=/dev/ram rw "				\
+		"console=ttyAMA0,115200 $(othbootargs);"		\
+	CONFIG_BOOTCOMMAND
+
+
+#define CONFIG_ENV_SIZE				0x02000
+#define CONFIG_SYS_MONITOR_BASE			CONFIG_SYS_TEXT_BASE
+
+/* Miscellaneous configurable options */
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_BOOT_PARAMS_ADDR			0x00000100
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_MISC_INIT_R
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_STOP_STR		" "
+#define CONFIG_AUTOBOOT_PROMPT			\
+		"Hit SPACE in %d seconds to stop autoboot.\n", bootdelay
+
+#define CONFIG_SYS_MEMTEST_START		0x00800000
+#define CONFIG_SYS_MEMTEST_END			0x04000000
+#define CONFIG_SYS_MALLOC_LEN			(1024*1024)
+#define CONFIG_IDENT_STRING			"-SPEAr"
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT			"u-boot> "
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_CBSIZE			256
+#define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE + \
+						sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS			16
+#define CONFIG_SYS_BARGSIZE			CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_LOAD_ADDR			0x00800000
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS			1
+#define PHYS_SDRAM_1				0x00000000
+#define PHYS_SDRAM_1_MAXSIZE			0x40000000
+
+#define CONFIG_SYS_SDRAM_BASE			PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR		0xD2800000
+#define CONFIG_SYS_INIT_RAM_SIZE		0x2000
+
+#define CONFIG_SYS_INIT_SP_OFFSET		\
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_INIT_SP_ADDR			\
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/spear3xx_evb.h b/qemu/roms/u-boot/include/configs/spear3xx_evb.h
new file mode 100644
index 000000000..8090bc897
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/spear3xx_evb.h
@@ -0,0 +1,157 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#if defined(CONFIG_spear300)
+#define CONFIG_SPEAR3XX
+#define CONFIG_SPEAR300
+#elif defined(CONFIG_spear310)
+#define CONFIG_SPEAR3XX
+#define CONFIG_SPEAR310
+#elif defined(CONFIG_spear320)
+#define CONFIG_SPEAR3XX
+#define CONFIG_SPEAR320
+#endif
+
+#if defined(CONFIG_usbtty)
+#define CONFIG_SPEAR_USBTTY
+#endif
+
+#if defined(CONFIG_nand)
+#define CONFIG_ENV_IS_IN_NAND
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#endif
+
+#include <configs/spear-common.h>
+
+/* Ethernet driver configuration */
+#define CONFIG_DW_ALTDESCRIPTOR
+
+#if defined(CONFIG_SPEAR310)
+#define CONFIG_MACB
+#define CONFIG_MACB0_PHY			0x01
+#define CONFIG_MACB1_PHY			0x03
+#define CONFIG_MACB2_PHY			0x05
+#define CONFIG_MACB3_PHY			0x07
+
+#elif defined(CONFIG_SPEAR320)
+#define CONFIG_MACB
+#define CONFIG_MACB0_PHY			0x01
+
+#endif
+
+/* Serial Configuration (PL011) */
+#define CONFIG_SYS_SERIAL0			0xD0000000
+
+#if defined(CONFIG_SPEAR300)
+#define CONFIG_PL01x_PORTS			{(void *)CONFIG_SYS_SERIAL0}
+
+#elif defined(CONFIG_SPEAR310)
+
+#if (CONFIG_CONS_INDEX)
+#undef  CONFIG_PL011_CLOCK
+#define CONFIG_PL011_CLOCK			(83 * 1000 * 1000)
+#endif
+
+#define CONFIG_SYS_SERIAL1			0xB2000000
+#define CONFIG_SYS_SERIAL2			0xB2080000
+#define CONFIG_SYS_SERIAL3			0xB2100000
+#define CONFIG_SYS_SERIAL4			0xB2180000
+#define CONFIG_SYS_SERIAL5			0xB2200000
+#define CONFIG_PL01x_PORTS			{(void *)CONFIG_SYS_SERIAL0, \
+						(void *)CONFIG_SYS_SERIAL1, \
+						(void *)CONFIG_SYS_SERIAL2, \
+						(void *)CONFIG_SYS_SERIAL3, \
+						(void *)CONFIG_SYS_SERIAL4, \
+						(void *)CONFIG_SYS_SERIAL5 }
+#elif defined(CONFIG_SPEAR320)
+
+#if (CONFIG_CONS_INDEX)
+#undef  CONFIG_PL011_CLOCK
+#define CONFIG_PL011_CLOCK			(83 * 1000 * 1000)
+#endif
+
+#define CONFIG_SYS_SERIAL1			0xA3000000
+#define CONFIG_SYS_SERIAL2			0xA4000000
+#define CONFIG_PL01x_PORTS			{(void *)CONFIG_SYS_SERIAL0, \
+						(void *)CONFIG_SYS_SERIAL1, \
+						(void *)CONFIG_SYS_SERIAL2 }
+#endif
+
+#if defined(CONFIG_SPEAR_EMI)
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+
+#if defined(CONFIG_SPEAR310)
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_FLASH_BASE			0x50000000
+#define CONFIG_SYS_CS1_FLASH_BASE		0x60000000
+#define CONFIG_SYS_CS2_FLASH_BASE		0x70000000
+#define CONFIG_SYS_CS3_FLASH_BASE		0x80000000
+#define CONFIG_SYS_CS4_FLASH_BASE		0x90000000
+#define CONFIG_SYS_CS5_FLASH_BASE		0xA0000000
+#define CONFIG_SYS_FLASH_BANKS_LIST		{ CONFIG_SYS_FLASH_BASE,   \
+						CONFIG_SYS_CS1_FLASH_BASE, \
+						CONFIG_SYS_CS2_FLASH_BASE, \
+						CONFIG_SYS_CS3_FLASH_BASE, \
+						CONFIG_SYS_CS4_FLASH_BASE, \
+						CONFIG_SYS_CS5_FLASH_BASE }
+#define CONFIG_SYS_MAX_FLASH_BANKS		6
+
+#elif defined(CONFIG_SPEAR320)
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_FLASH_BASE			0x44000000
+#define CONFIG_SYS_CS1_FLASH_BASE		0x45000000
+#define CONFIG_SYS_CS2_FLASH_BASE		0x46000000
+#define CONFIG_SYS_CS3_FLASH_BASE		0x47000000
+#define CONFIG_SYS_FLASH_BANKS_LIST		{ CONFIG_SYS_FLASH_BASE,   \
+						CONFIG_SYS_CS1_FLASH_BASE, \
+						CONFIG_SYS_CS2_FLASH_BASE, \
+						CONFIG_SYS_CS3_FLASH_BASE }
+#define CONFIG_SYS_MAX_FLASH_BANKS		4
+
+#endif
+
+#define CONFIG_SYS_MAX_FLASH_SECT		(127 + 8)
+#define CONFIG_SYS_FLASH_QUIET_TEST
+
+#endif
+
+/* NAND flash configuration */
+#define CONFIG_SYS_FSMC_NAND_SP
+#define CONFIG_SYS_FSMC_NAND_8BIT
+
+#if defined(CONFIG_SPEAR300)
+#define CONFIG_SYS_NAND_BASE			0x80000000
+
+#elif defined(CONFIG_SPEAR310)
+#define CONFIG_SYS_NAND_BASE			0x40000000
+
+#elif defined(CONFIG_SPEAR320)
+#define CONFIG_SYS_NAND_BASE			0x50000000
+
+#endif
+
+/* Environment Settings */
+#if defined(CONFIG_SPEAR300)
+#define CONFIG_EXTRA_ENV_SETTINGS              CONFIG_EXTRA_ENV_USBTTY
+
+#elif defined(CONFIG_SPEAR310) || defined(CONFIG_SPEAR320)
+#define CONFIG_EXTRA_ENV_UNLOCK                        "unlock=yes\0"
+#define CONFIG_EXTRA_ENV_SETTINGS              CONFIG_EXTRA_ENV_USBTTY \
+						CONFIG_EXTRA_ENV_UNLOCK
+#endif
+
+#endif  /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/spear6xx_evb.h b/qemu/roms/u-boot/include/configs/spear6xx_evb.h
new file mode 100644
index 000000000..28dddcc5b
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/spear6xx_evb.h
@@ -0,0 +1,46 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_SPEAR600
+
+#if defined(CONFIG_usbtty)
+#define CONFIG_SPEAR_USBTTY
+#endif
+
+#if defined(CONFIG_nand)
+#define CONFIG_ENV_IS_IN_NAND
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#endif
+
+#include <configs/spear-common.h>
+
+/* Serial Configuration (PL011) */
+#define CONFIG_SYS_SERIAL0			0xD0000000
+#define CONFIG_SYS_SERIAL1			0xD0080000
+#define CONFIG_PL01x_PORTS			{ (void *)CONFIG_SYS_SERIAL0, \
+						(void *)CONFIG_SYS_SERIAL1 }
+
+/* NAND flash configuration */
+#define CONFIG_SYS_FSMC_NAND_SP
+#define CONFIG_SYS_FSMC_NAND_8BIT
+#define CONFIG_SYS_NAND_BASE			0xD2000000
+
+/* Ethernet PHY configuration */
+#define CONFIG_PHY_NATSEMI
+
+/* Environment Settings */
+#define CONFIG_EXTRA_ENV_SETTINGS              CONFIG_EXTRA_ENV_USBTTY
+
+#endif  /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/stamp9g20.h b/qemu/roms/u-boot/include/configs/stamp9g20.h
new file mode 100644
index 000000000..01085dc5c
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/stamp9g20.h
@@ -0,0 +1,255 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * (C) Copyright 2010
+ * Achim Ehrlich <aehrlich@taskit.de>
+ * taskit GmbH <www.taskit.de>
+ *
+ * (C) Copyright 2012
+ * Markus Hubig <mhubig@imko.de>
+ * IMKO GmbH <www.imko.de>
+ *
+ * Configuation settings for the stamp9g20 CPU module.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * SoC must be defined first, before hardware.h is included.
+ * In this case SoC is defined in boards.cfg.
+ */
+#include <asm/hardware.h>
+
+/*
+ * Warning: changing CONFIG_SYS_TEXT_BASE requires adapting the initial boot
+ * program. Since the linker has to swallow that define, we must use a pure
+ * hex number here!
+ */
+#define CONFIG_SYS_TEXT_BASE		0x23f00000
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000	/* 18.432MHz crystal */
+
+/* misc settings */
+#define CONFIG_CMDLINE_TAG		/* pass commandline to Kernel */
+#define CONFIG_SETUP_MEMORY_TAGS	/* pass memory defs to kernel */
+#define CONFIG_INITRD_TAG		/* pass initrd param to kernel */
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is loaded by a bootloader */
+#define CONFIG_BOARD_EARLY_INIT_f	/* call board_early_init_f() */
+#define CONFIG_BOARD_POSTCLK_INIT	/* call board_postclk_init() */
+#define CONFIG_DISPLAY_CPUINFO		/* display CPU Info at startup */
+
+/* setting board specific options */
+#ifdef CONFIG_PORTUXG20
+# define CONFIG_MACH_TYPE		MACH_TYPE_PORTUXG20
+# define CONFIG_MACB
+#else
+# define CONFIG_MACH_TYPE		MACH_TYPE_STAMP9G20
+#endif
+
+/*
+ * SDRAM: 1 bank, 64 MB, base address 0x20000000
+ * Already initialized before u-boot gets started.
+ */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
+#define CONFIG_SYS_SDRAM_SIZE		(64 << 20)
+
+/*
+ * Perform a SDRAM Memtest from the start of SDRAM
+ * till the beginning of the U-Boot position in RAM.
+ */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_TEXT_BASE - 0x100000)
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN \
+	ROUND(3 * CONFIG_ENV_SIZE + (128 << 10), 0x1000)
+
+/*
+ * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
+ * leaving the correct space for initial global data structure above that
+ * address while providing maximum stack area below.
+ */
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+/* NAND flash settings */
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
+#define CONFIG_SYS_NAND_DBW_8
+#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
+#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIN_PC14
+#define CONFIG_SYS_NAND_READY_PIN	AT91_PIN_PC13
+
+/* general purpose I/O */
+#define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
+#define CONFIG_AT91_GPIO		/* enable the GPIO features */
+#define CONFIG_AT91_GPIO_PULLUP	1	/* keep pullups on peripheral pins */
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
+#define CONFIG_USART_ID			ATMEL_ID_SYS
+#define CONFIG_BAUDRATE			115200
+
+/* LED configuration */
+#define CONFIG_STATUS_LED
+#define CONFIG_BOARD_SPECIFIC_LED
+
+/* The LED PINs */
+#define CONFIG_RED_LED			AT91_PIN_PC5
+#define CONFIG_GREEN_LED		AT91_PIN_PC4
+#define CONFIG_YELLOW_LED		AT91_PIN_PC10
+
+#define STATUS_LED_RED			0
+#define STATUS_LED_GREEN		1
+#define STATUS_LED_YELLOW		2
+
+/* Red LED */
+#define STATUS_LED_BIT			STATUS_LED_RED
+#define STATUS_LED_STATE		STATUS_LED_OFF
+#define STATUS_LED_PERIOD		(CONFIG_SYS_HZ / 2)
+
+/* Green LED */
+#define STATUS_LED_BIT1			STATUS_LED_GREEN
+#define STATUS_LED_STATE1		STATUS_LED_ON
+#define STATUS_LED_PERIOD1		(CONFIG_SYS_HZ / 2)
+
+/* Yellow LED */
+#define STATUS_LED_BIT2			STATUS_LED_YELLOW
+#define STATUS_LED_STATE2		STATUS_LED_OFF
+#define STATUS_LED_PERIOD2		(CONFIG_SYS_HZ / 2)
+
+/* Boot status LED */
+#define STATUS_LED_BOOT			STATUS_LED_GREEN
+
+/*
+ * Ethernet configuration
+ *
+ * PortuxG20 has always ethernet but for Stamp9G20 you
+ * can enable it here if your baseboard features ethernet.
+ */
+
+#define CONFIG_MACB
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_MCS7830
+
+#ifdef CONFIG_MACB
+# define CONFIG_RMII			/* use reduced MII inteface */
+# define CONFIG_NET_RETRY_COUNT	20      /* # of DHCP/BOOTP retries */
+#define CONFIG_AT91_WANTS_COMMON_PHY
+
+/* BOOTP and DHCP options */
+# define CONFIG_BOOTP_BOOTFILESIZE
+# define CONFIG_BOOTP_BOOTPATH
+# define CONFIG_BOOTP_GATEWAY
+# define CONFIG_BOOTP_HOSTNAME
+# define CONFIG_NFSBOOTCOMMAND						\
+	"setenv autoload yes; setenv autoboot yes; "			\
+	"setenv bootargs ${basicargs} ${mtdparts} "			\
+	"root=/dev/nfs ip=dhcp nfsroot=${serverip}:/srv/nfs/rootfs; "	\
+	"dhcp"
+#endif /* CONFIG_MACB */
+
+/* Enable the watchdog */
+#define CONFIG_AT91SAM9_WATCHDOG
+#define CONFIG_HW_WATCHDOG
+
+/* USB configuration */
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_USB_STORAGE
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE	ATMEL_UHP_BASE
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"at91sam9260"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+
+/* General Boot Parameter */
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_BOOTCOMMAND		"run flashboot"
+#define CONFIG_SYS_PROMPT		"U-Boot> "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_PBSIZE \
+	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+
+/*
+ * RAM Memory address where to put the
+ * Linux Kernel befor starting.
+ */
+#define CONFIG_SYS_LOAD_ADDR		0x22000000
+
+/*
+ * The NAND Flash partitions:
+ * ==========================================
+ * 0x0000000-0x001ffff -> 128k, bootstrap
+ * 0x0020000-0x005ffff -> 256k, u-boot
+ * 0x0060000-0x007ffff -> 128k, env1
+ * 0x0080000-0x009ffff -> 128k, env2 (backup)
+ * 0x0100000-0x06fffff ->   6M, kernel
+ * 0x0700000-0x8000000 -> 121M, RootFS
+ */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		((128 + 256) << 10)
+#define CONFIG_ENV_OFFSET_REDUND	((128 + 256 + 128) << 10)
+#define CONFIG_ENV_SIZE			(128 << 10)
+
+/*
+ * Predefined environment variables.
+ * Usefull to define some easy to use boot commands.
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+									\
+	"basicargs=console=ttyS0,115200\0"				\
+									\
+	"mtdparts=mtdparts=atmel_nand:128k(bootstrap)ro,"		\
+		"256k(uboot)ro,128k(env1)ro,"				\
+		"128k(env2)ro,6M(linux),-(root)rw\0"			\
+									\
+	"flashboot=setenv bootargs ${basicargs} ${mtdparts} "		\
+		"root=/dev/mtdblock5 rootfstype=jffs2; "		\
+		"nand read 0x22000000 0x100000 0x600000; "		\
+		"bootm 22000000\0"					\
+									\
+	"sdboot=setenv bootargs ${basicargs} ${mtdparts} "		\
+		"root=/dev/mmcblk0p1 rootwait; "			\
+		"nand read 0x22000000 0x100000 0x600000; "		\
+		"bootm 22000000"
+
+/* Command line & features configuration */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_LOADS
+
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_LED
+
+#ifdef CONFIG_MACB
+# define CONFIG_CMD_PING
+# define CONFIG_CMD_DHCP
+#else
+# undef CONFIG_CMD_BOOTD
+# undef CONFIG_CMD_NET
+# undef CONFIG_CMD_NFS
+#endif /* CONFIG_MACB */
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/stxgp3.h b/qemu/roms/u-boot/include/configs/stxgp3.h
new file mode 100644
index 000000000..5fb40ebf8
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/stxgp3.h
@@ -0,0 +1,364 @@
+/*
+ * (C) Copyright 2003 Embedded Edge, LLC
+ * Dan Malek <dan@embeddededge.com>
+ * Copied from ADS85xx.
+ * Updates for Silicon Tx GP3 8560 board.
+ *
+ * (C) Copyright 2002,2003 Motorola,Inc.
+ * Xianghua Xiao <X.Xiao@motorola.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* mpc8560ads board configuration file */
+/* please refer to doc/README.mpc85xx for more info */
+/* make sure you change the MAC address and other network params first,
+ * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE		1	/* BOOKE		*/
+#define CONFIG_E500		1	/* BOOKE e500 family	*/
+#define CONFIG_CPM2		1	/* has CPM2 */
+#define CONFIG_STXGP3		1	/* Silicon Tx GPPP board specific*/
+#define CONFIG_MPC8560		1
+
+#define	CONFIG_SYS_TEXT_BASE	0xfff80000
+
+#undef  CONFIG_PCI			/* pci ethernet support	*/
+#define CONFIG_TSEC_ENET		/* tsec ethernet support*/
+#undef  CONFIG_ETHER_ON_FCC             /* cpm FCC ethernet support */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_FSL_LAW		1	/* Use common FSL init code */
+
+/* sysclk for MPC85xx
+ */
+
+#define CONFIG_SYS_CLK_FREQ     33333333 /* most pci cards are 33Mhz */
+
+/* Blinkin' LEDs for Robert :-)
+*/
+#define CONFIG_SHOW_ACTIVITY 1
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE                     /* toggle L2 cache         */
+#define  CONFIG_BTB                          /* toggle branch predition */
+
+#define CONFIG_BOARD_EARLY_INIT_F   1        /* Call board_pre_init      */
+#define CONFIG_RESET_PHY_R	1	/* Call reset_phy()		*/
+
+#undef  CONFIG_SYS_DRAM_TEST                       /* memory test, takes time  */
+#define CONFIG_SYS_MEMTEST_START       0x00200000  /* memtest region */
+#define CONFIG_SYS_MEMTEST_END         0x00400000
+
+
+/* Localbus SDRAM is an option, not all boards have it.
+ * This address, however, is used to configure a 256M local bus
+ * window that includes the Config latch below.
+ */
+#define CONFIG_SYS_LBC_SDRAM_BASE      0xf0000000      /* Localbus SDRAM */
+#define CONFIG_SYS_LBC_SDRAM_SIZE	256		/* LBC SDRAM is 64MB	*/
+
+#define CONFIG_SYS_FLASH_BASE        0xff000000      /* start of FLASH 16M    */
+#define CONFIG_SYS_BR0_PRELIM        0xff001801      /* port size 32bit      */
+
+#define CONFIG_SYS_OR0_PRELIM          0xff000ff7      /* 16 MB Flash           */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	136		/* sectors per device   */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+/* The configuration latch is Chip Select 1.
+ * It's an 8-bit latch in the lower 8 bits of the word.
+ */
+#define CONFIG_SYS_BR1_PRELIM		0xfc001801	/* 32-bit port */
+#define CONFIG_SYS_OR1_PRELIM		0xffff0ff7      /* 64K is enough */
+#define CONFIG_SYS_LBC_LCLDEVS_BASE	0xfc000000	/* Base of localbus devices */
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor	*/
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef  CONFIG_SYS_RAMBOOT
+#endif
+
+#ifdef CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0x40000000	/* CCSRBAR by BDI cfg	*/
+#endif
+#define CONFIG_SYS_CCSRBAR		0xfdf00000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+
+/* DDR Setup */
+#define CONFIG_SYS_FSL_DDR1
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_SPD
+#undef CONFIG_FSL_DDR_INTERACTIVE
+
+#undef  CONFIG_DDR_ECC			/* only for ECC DDR module */
+#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN	/* possible DLL fix needed */
+#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
+
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x54	/* CTLR 0 DIMM 0 */
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+/* local bus definitions */
+#define CONFIG_SYS_BR2_PRELIM		0xf8001861	/* 64MB localbus SDRAM  */
+#define CONFIG_SYS_OR2_PRELIM		0xfc006901
+#define CONFIG_SYS_LBC_LCRR		0x00030004	/* local bus freq	*/
+#define CONFIG_SYS_LBC_LBCR		0x00000000
+#define CONFIG_SYS_LBC_LSRT		0x20000000
+#define CONFIG_SYS_LBC_MRTPR		0x20000000
+#define CONFIG_SYS_LBC_LSDMR_1		0x2861b723
+#define CONFIG_SYS_LBC_LSDMR_2		0x0861b723
+#define CONFIG_SYS_LBC_LSDMR_3		0x0861b723
+#define CONFIG_SYS_LBC_LSDMR_4		0x1861b723
+#define CONFIG_SYS_LBC_LSDMR_5		0x4061b723
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR       0x60000000      /* Initial RAM address  */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)    /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)    /* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_ON_SCC		/* define if console on SCC */
+#undef  CONFIG_CONS_NONE		/* define if console on something else */
+#define CONFIG_CONS_INDEX       2	/* which serial channel for console */
+
+#define CONFIG_BAUDRATE		38400
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef  CONFIG_SYS_HUSH_PARSER
+#endif
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+
+#if 0
+#define CONFIG_SYS_I2C_NOPROBES        {0x00}  /* Don't probe these addrs */
+#else
+/* I did the 'if 0' so we could keep the syntax above if ever needed. */
+#undef CONFIG_SYS_I2C_NOPROBES
+#endif
+
+/* RapdIO Map configuration, mapped 1:1.
+*/
+#define CONFIG_SYS_RIO_MEM_BASE	0xc0000000
+#define CONFIG_SYS_RIO_MEM_PHYS	CONFIG_SYS_RIO_MEM_BASE
+#define CONFIG_SYS_RIO_MEM_SIZE	0x200000000	/* 512 M */
+
+/* Standard 8560 PCI addressing, mapped 1:1.
+*/
+#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCI1_IO_BASE	0xe2000000
+#define CONFIG_SYS_PCI1_IO_PHYS	CONFIG_SYS_PCI1_IO_BASE
+#define CONFIG_SYS_PCI1_IO_SIZE	0x01000000	/* 16 M */
+
+#if defined(CONFIG_PCI)			/* PCI Ethernet card */
+
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+  #define PCI_ENET0_IOADDR	0xe0000000
+  #define PCI_ENET0_MEMADDR     0xe0000000
+  #define PCI_IDSEL_NUMBER      0x0c	/* slot0->3(IDSEL)=12->15 */
+#endif
+
+#undef CONFIG_PCI_SCAN_SHOW
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
+
+#endif /* CONFIG_PCI */
+
+#if defined(CONFIG_TSEC_ENET)
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"TSEC1"
+
+#define TSEC1_PHY_ADDR		2
+#define TSEC2_PHY_ADDR		4
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
+#define CONFIG_ETHPRIME		"TSEC0"
+
+#elif defined(CONFIG_ETHER_ON_FCC)	/* CPM FCC Ethernet */
+
+#define CONFIG_ETHER_ON_FCC2             /* define if ether on FCC   */
+#undef  CONFIG_ETHER_NONE               /* define if ether on something else */
+#define CONFIG_ETHER_INDEX      2       /* which channel for ether  */
+
+#if (CONFIG_ETHER_INDEX == 2)
+  /*
+   * - Rx-CLK is CLK13
+   * - Tx-CLK is CLK14
+   * - Select bus for bd/buffers
+   * - Full duplex
+   */
+  #define CONFIG_SYS_CMXFCR_MASK2      (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+  #define CONFIG_SYS_CMXFCR_VALUE2     (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
+  #define CONFIG_SYS_CPMFCR_RAMTYPE    0
+#if 0
+  #define CONFIG_SYS_FCC_PSMR          (FCC_PSMR_FDE)
+#else
+  #define CONFIG_SYS_FCC_PSMR          0
+#endif
+  #define FETH2_RST		0x01
+#elif (CONFIG_ETHER_INDEX == 3)
+  /* need more definitions here for FE3 */
+  #define FETH3_RST		0x80
+#endif	/* CONFIG_ETHER_INDEX */
+
+/* MDIO is done through the TSEC0 control.
+*/
+#define CONFIG_MII			/* MII PHY management */
+#undef CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
+
+#endif
+
+/* Environment */
+/* We use the top boot sector flash, so we have some 16K sectors for env
+ */
+#ifndef CONFIG_SYS_RAMBOOT
+  #define CONFIG_ENV_IS_IN_FLASH	1
+  #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x60000)
+  #define CONFIG_ENV_SECT_SIZE	0x4000	/* 16K (one top sector) for env */
+  #define CONFIG_ENV_SIZE		0x2000
+#else
+  #define CONFIG_SYS_NO_FLASH		1	/* Flash is not usable now	*/
+  #define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only	*/
+  #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
+  #define CONFIG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,38400"
+#define CONFIG_BOOTCOMMAND	"bootm 0xff000000 0xff100000"
+#define CONFIG_BOOTDELAY	3	/* -1 disable autoboot */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_REGINFO
+
+#if defined(CONFIG_SYS_RAMBOOT)
+    #undef CONFIG_CMD_SAVEENV
+    #undef CONFIG_CMD_LOADS
+#else
+    #define CONFIG_CMD_ELF
+#endif
+
+#if defined(CONFIG_PCI)
+    #define CONFIG_CMD_PCI
+#endif
+
+#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
+    #define CONFIG_CMD_MII
+#endif
+
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"GPPP=> "	/* Monitor Command Prompt	*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_LOAD_ADDR	0x1000000	/* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*Note: change below for your network setting!!! */
+#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
+#define CONFIG_HAS_ETH0
+#define CONFIG_ETHADDR		 00:e0:0c:07:9b:8a
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR		 00:e0:0c:07:9b:8b
+#define CONFIG_HAS_ETH2
+#define CONFIG_ETH2ADDR		 00:e0:0c:07:9b:8c
+#endif
+
+#define CONFIG_SERVERIP		192.168.85.1
+#define CONFIG_IPADDR		192.168.85.60
+#define CONFIG_GATEWAYIP	192.168.85.1
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_HOSTNAME		STX_GP3
+#define CONFIG_ROOTPATH		"/gppproot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_LOADADDR		0x1000000
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/stxssa.h b/qemu/roms/u-boot/include/configs/stxssa.h
new file mode 100644
index 000000000..914d82190
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/stxssa.h
@@ -0,0 +1,451 @@
+/*
+ * (C) Copyright 2005 Embedded Alley Solutions, Inc.
+ * Dan Malek <dan@embeddedalley.com>
+ * Copied from STx GP3.
+ * Updates for Silicon Tx GP3 SSA board.
+ *
+ * (C) Copyright 2002,2003 Motorola,Inc.
+ * Xianghua Xiao <X.Xiao@motorola.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* mpc8560ads board configuration file */
+/* please refer to doc/README.mpc85xx for more info */
+/* make sure you change the MAC address and other network params first,
+ * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE		1	/* BOOKE		*/
+#define CONFIG_E500		1	/* BOOKE e500 family	*/
+#define CONFIG_CPM2		1	/* has CPM2 */
+#define CONFIG_STXSSA		1	/* Silicon Tx GPPP SSA board specific*/
+#define CONFIG_MPC8560		1
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFF80000
+
+#define CONFIG_PCI			/* PCI ethernet support	*/
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_TSEC_ENET		/* tsec ethernet support*/
+#undef CONFIG_ETHER_ON_FCC		/* cpm FCC ethernet support */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_FSL_LAW		1	/* Use common FSL init code */
+
+/* sysclk for MPC85xx
+ */
+
+#define CONFIG_SYS_CLK_FREQ	33000000 /* most pci cards are 33Mhz */
+
+/* Blinkin' LEDs for Robert :-)
+*/
+#define CONFIG_SHOW_ACTIVITY 1
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE				/* toggle L2 cache	       */
+#define  CONFIG_BTB				/* toggle branch predition */
+
+#define CONFIG_BOARD_EARLY_INIT_F   1		/* Call board_pre_init	 */
+
+#undef	CONFIG_SYS_DRAM_TEST				/* memory test, takes time	*/
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+
+
+/* Localbus connector.	There are many options that can be
+ * connected here, including sdram or lots of flash.
+ * This address, however, is used to configure a 256M local bus
+ * window that includes the Config latch below.
+ */
+#define CONFIG_SYS_LBC_OPTION_BASE	0xF0000000	/* Localbus Extension */
+#define CONFIG_SYS_LBC_OPTION_SIZE	256		/* 256MB */
+
+/* There are various flash options used, we configure for the largest,
+ * which is 64Mbytes.  The CFI works fine and will discover the proper
+ * sizes.
+ */
+#ifdef CONFIG_STXSSA_4M
+#define CONFIG_SYS_FLASH_BASE		0xFFC00000	/* start of  4 MiB flash */
+#else
+#define CONFIG_SYS_FLASH_BASE		0xFC000000	/* start of 64 MiB flash */
+#endif
+#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE | 0x1801) /* port size 32bit	 */
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_FLASH_BASE | 0x0FF7)
+
+#define CONFIG_SYS_FLASH_CFI		1
+#define CONFIG_FLASH_CFI_DRIVER	1
+#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE	/* use buffered writes (20x faster) */
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks	*/
+
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+
+#define CONFIG_SYS_FLASH_PROTECTION
+
+/* The configuration latch is Chip Select 1.
+ * It's an 8-bit latch in the lower 8 bits of the word.
+ */
+#define CONFIG_SYS_LBC_CFGLATCH_BASE	0xFB000000	/* Base of config latch */
+#define CONFIG_SYS_BR1_PRELIM		0xFB001801	/* 32-bit port */
+#define CONFIG_SYS_OR1_PRELIM		0xFFFF0FF7	/* 64K is enough */
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor	*/
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef	CONFIG_SYS_RAMBOOT
+#endif
+
+#ifdef CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0x40000000	/* CCSRBAR by BDI cfg	*/
+#endif
+
+#define CONFIG_SYS_CCSRBAR		0xe0000000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+
+/* DDR Setup */
+#define CONFIG_SYS_FSL_DDR1
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_SPD
+#undef CONFIG_FSL_DDR_INTERACTIVE
+
+#undef	CONFIG_DDR_ECC			/* only for ECC DDR module */
+#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */
+
+#define CONFIG_MEM_INIT_VALUE		0xDeadBeef
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS	0x54	/* CTLR 0 DIMM 0 */
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+/* local bus definitions */
+#define CONFIG_SYS_BR2_PRELIM		0xf8001861	/* 64MB localbus SDRAM	*/
+#define CONFIG_SYS_OR2_PRELIM		0xfc006901
+#define CONFIG_SYS_LBC_LCRR		0x00030004	/* local bus freq	*/
+#define CONFIG_SYS_LBC_LBCR		0x00000000
+#define CONFIG_SYS_LBC_LSRT		0x20000000
+#define CONFIG_SYS_LBC_MRTPR		0x20000000
+#define CONFIG_SYS_LBC_LSDMR_1		0x2861b723
+#define CONFIG_SYS_LBC_LSDMR_2		0x0861b723
+#define CONFIG_SYS_LBC_LSDMR_3		0x0861b723
+#define CONFIG_SYS_LBC_LSDMR_4		0x1861b723
+#define CONFIG_SYS_LBC_LSDMR_5		0x4061b723
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0x60000000	/* Initial RAM address	*/
+#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(512 * 1024)	/* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX     2
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_AUTO_COMPLETE	1	/* add autocompletion support   */
+#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT		1
+#define CONFIG_OF_BOARD_SETUP		1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#undef CONFIG_SYS_I2C_NOPROBES
+
+/* I2C RTC */
+#define CONFIG_RTC_DS1337		/* This is really a DS1339 RTC	*/
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68	/* at address 0x68		*/
+
+/* I2C EEPROM.	AT24C32, we keep our environment in here.
+*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x51	/* 1010001x		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* =32 Bytes per write	*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	20
+
+/*
+ * Standard 8555 PCI mapping.
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCI1_IO_BASE	0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
+#define CONFIG_SYS_PCI1_IO_SIZE	0x01000000	/* 16M */
+
+#define CONFIG_SYS_PCI2_MEM_BASE	0xa0000000
+#define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BASE
+#define CONFIG_SYS_PCI2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCI2_IO_BASE	0x00000000
+#define CONFIG_SYS_PCI2_IO_PHYS	0xe3000000
+#define CONFIG_SYS_PCI2_IO_SIZE	0x01000000	/* 16M */
+
+#if defined(CONFIG_PCI)			/* PCI Ethernet card */
+#define CONFIG_MPC85XX_PCI2	1
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+
+#define CONFIG_EEPRO100
+#define CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+  #define PCI_ENET0_IOADDR	0xe0000000
+  #define PCI_ENET0_MEMADDR	0xe0000000
+  #define PCI_IDSEL_NUMBER	0x0c	/* slot0->3(IDSEL)=12->15 */
+#endif
+
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057	/* Motorola */
+
+#endif /* CONFIG_PCI */
+
+#if defined(CONFIG_TSEC_ENET)
+
+#define CONFIG_MII		1	/* MII PHY management		*/
+
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"TSEC1"
+
+#define TSEC1_PHY_ADDR		2
+#define TSEC2_PHY_ADDR		4
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
+#define CONFIG_ETHPRIME		"TSEC0"
+
+#elif defined(CONFIG_ETHER_ON_FCC)	/* CPM FCC Ethernet */
+
+#define CONFIG_ETHER_ON_FCC2		/* define if ether on FCC   */
+#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
+#define CONFIG_ETHER_INDEX	2	/* which channel for ether  */
+
+#if (CONFIG_ETHER_INDEX == 2)
+  /*
+   * - Rx-CLK is CLK13
+   * - Tx-CLK is CLK14
+   * - Select bus for bd/buffers
+   * - Full duplex
+   */
+  #define CONFIG_SYS_CMXFCR_MASK2	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+  #define CONFIG_SYS_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
+  #define CONFIG_SYS_CPMFCR_RAMTYPE	0
+#if 0
+  #define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE)
+#else
+  #define CONFIG_SYS_FCC_PSMR		0
+#endif
+  #define FETH2_RST		0x01
+#elif (CONFIG_ETHER_INDEX == 3)
+  /* need more definitions here for FE3 */
+  #define FETH3_RST		0x80
+#endif					/* CONFIG_ETHER_INDEX */
+
+/* MDIO is done through the TSEC0 control.
+*/
+#define CONFIG_MII			/* MII PHY management */
+#undef CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
+
+#endif
+
+/* Environment - default config is in flash, see below */
+#if 0	/* in EEPROM */
+# define CONFIG_ENV_IS_IN_EEPROM	1
+# define CONFIG_ENV_OFFSET		0
+# define CONFIG_ENV_SIZE		2048
+#else	/* in flash */
+# define CONFIG_ENV_IS_IN_FLASH	1
+# ifdef CONFIG_STXSSA_4M
+#  define CONFIG_ENV_SECT_SIZE	0x20000
+# else	/* default configuration - 64 MiB flash */
+#  define CONFIG_ENV_SECT_SIZE	0x40000
+# endif
+# define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+# define CONFIG_ENV_SIZE		0x4000
+# define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
+# define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+#endif
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define	CONFIG_TIMESTAMP		/* Print image info with ts	*/
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_REGINFO
+
+#if defined(CONFIG_PCI)
+    #define CONFIG_CMD_PCI
+#endif
+
+#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
+    #define CONFIG_CMD_MII
+#endif
+
+#if defined(CONFIG_SYS_RAMBOOT)
+    #undef CONFIG_CMD_SAVEENV
+    #undef CONFIG_CMD_LOADS
+#else
+    #define CONFIG_CMD_ELF
+#endif
+
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"SSA=> "	/* Monitor Command Prompt	*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_LOAD_ADDR	0x1000000	/* default load address */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*Note: change below for your network setting!!! */
+#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
+#define CONFIG_HAS_ETH0
+#define CONFIG_ETHADDR	 00:e0:0c:07:9b:8a
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR  00:e0:0c:07:9b:8b
+#define CONFIG_HAS_ETH2
+#define CONFIG_ETH2ADDR  00:e0:0c:07:9b:8c
+#endif
+
+/*
+ * Environment in EEPROM is compatible with different flash sector sizes,
+ * but only little space is available, so we use a very simple setup.
+ * With environment in flash, we use a more powerful default configuration.
+ */
+#ifdef CONFIG_ENV_IS_IN_EEPROM		/* use restricted "standard" environment */
+
+#define CONFIG_BAUDRATE		38400
+
+#define CONFIG_BOOTDELAY	3	/* -1 disable autoboot */
+#define CONFIG_BOOTCOMMAND	"bootm 0xffc00000 0xffd00000"
+#define CONFIG_BOOTARGS		"root=/dev/nfs rw ip=any console=ttyS1,$baudrate"
+#define CONFIG_SERVERIP		192.168.85.1
+#define CONFIG_IPADDR		192.168.85.60
+#define CONFIG_GATEWAYIP	192.168.85.1
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_HOSTNAME		STX_SSA
+#define CONFIG_ROOTPATH		"/gppproot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_LOADADDR		0x1000000
+
+#else /* ENV IS IN FLASH		-- use a full-blown envionment */
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_BOOTDELAY	5	/* -1 disable autoboot */
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS		/* the boot command will set bootargs	*/
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"hostname=gp3ssa\0"						\
+	"bootfile=/tftpboot/gp3ssa/uImage\0"				\
+	"loadaddr=400000\0"						\
+	"netdev=eth0\0"							\
+	"consdev=ttyS1\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=$serverip:$rootpath\0"				\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs $bootargs "				\
+		"ip=$ipaddr:$serverip:$gatewayip:$netmask"		\
+		":$hostname:$netdev:off panic=1\0"			\
+	"addcons=setenv bootargs $bootargs "				\
+		"console=$consdev,$baudrate\0"				\
+	"flash_nfs=run nfsargs addip addcons;"				\
+		"bootm $kernel_addr\0"					\
+	"flash_self=run ramargs addip addcons;"				\
+		"bootm $kernel_addr $ramdisk_addr\0"			\
+	"net_nfs=tftp $loadaddr $bootfile;"				\
+		"run nfsargs addip addcons;bootm\0"			\
+	"rootpath=/opt/eldk/ppc_85xx\0"					\
+	"kernel_addr=FC000000\0"					\
+	"ramdisk_addr=FC200000\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#endif	/* CONFIG_ENV_IS_IN_EEPROM */
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/stxxtc.h b/qemu/roms/u-boot/include/configs/stxxtc.h
new file mode 100644
index 000000000..4e3b7277f
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/stxxtc.h
@@ -0,0 +1,485 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Dan Malek, Embedded Edge, LLC, dan@embeddededge.com
+ * U-Boot port on STx XTc 8xx board
+ * Mostly copied from Panto's NETTA2 board.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC875		1	/* This is a MPC875 CPU		*/
+#define CONFIG_STXXTC		1	/* ...on a STx XTc  board	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0x40F00000
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115.2kbps	*/
+
+#define CONFIG_XIN		10000000	/* 10 MHz input xtal */
+
+/* Select one of few clock rates defined later in this file.
+*/
+/* #define MPC8XX_HZ		50000000 */
+#define MPC8XX_HZ		66666666
+
+#define CONFIG_8xx_GCLK_FREQ	MPC8XX_HZ
+
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+#endif
+
+#undef	CONFIG_CLOCKS_IN_MHZ	/* clocks NOT passsed to Linux in MHz */
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND							\
+	"tftpboot; "								\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
+	"bootm"
+
+#define CONFIG_SOURCE
+#define CONFIG_LOADS_ECHO	0	/* echo off for serial download	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+#define CONFIG_BOARD_SPECIFIC_LED	/* version has board specific leds */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_NISDOMAIN
+
+
+#undef CONFIG_MAC_PARTITION
+#undef CONFIG_DOS_PARTITION
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+#define	FEC_ENET		1	/* eth.c needs it that way... */
+#undef CONFIG_SYS_DISCOVER_PHY
+#define CONFIG_MII		1
+#define CONFIG_MII_INIT		1
+#undef CONFIG_RMII
+
+#define CONFIG_ETHER_ON_FEC1	1
+#define CONFIG_FEC1_PHY		1	/* phy address of FEC */
+#undef CONFIG_FEC1_PHY_NORXERR
+
+#define CONFIG_ETHER_ON_FEC2	1
+#define CONFIG_FEC2_PHY		3
+#undef CONFIG_FEC2_PHY_NORXERR
+
+#define CONFIG_ENV_OVERWRITE	1	/* allow modification of vendor params */
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+
+
+#define CONFIG_BOARD_EARLY_INIT_F	1
+#define CONFIG_MISC_INIT_R
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT	"xtc> "		/* Monitor Command Prompt	*/
+
+#define CONFIG_SYS_HUSH_PARSER	1
+
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0300000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0700000	/* 3 ... 7 MB in DRAM	*/
+
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xFF000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x3000	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#if defined(DEBUG)
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#else
+#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#endif
+
+/* yes this is weird, I know :) */
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE | 0x00F00000)
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+#define CONFIG_SYS_RESET_ADDRESS	0x80000000
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define	CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_SECT_SIZE	0x10000
+
+#define	CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00000000)
+#define CONFIG_ENV_OFFSET		0
+#define	CONFIG_ENV_SIZE		0x4000
+
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_SYS_FLASH_BASE + 0x00010000)
+#define CONFIG_ENV_OFFSET_REDUND	0
+#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+
+#define CONFIG_SYS_FLASH_CFI		1
+#define CONFIG_FLASH_CFI_DRIVER	1
+#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE	/* use buffered writes (20x faster) */
+#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks	*/
+
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x2000000 }
+
+#define CONFIG_SYS_FLASH_PROTECTION
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC | SIUMCR_GB5E)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ *
+ */
+
+#if CONFIG_XIN == 10000000
+
+#if MPC8XX_HZ == 50000000
+#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
+			 (1 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
+			 PLPRCR_TEXPS)
+#elif MPC8XX_HZ == 66666666
+#define CONFIG_SYS_PLPRCR	((1 << PLPRCR_MFN_SHIFT) | (2 << PLPRCR_MFD_SHIFT) | \
+			 (1 << PLPRCR_S_SHIFT) | (13 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
+			 PLPRCR_TEXPS)
+#else
+#error unsupported CPU freq for XIN = 10MHz
+#endif
+#else
+#error unsupported freq for XIN (must be 10MHz)
+#endif
+
+
+/*
+ *-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ *
+ * Note: When TBS == 0 the timebase is independent of current cpu clock.
+ */
+
+#define SCCR_MASK	SCCR_EBDF11
+#if MPC8XX_HZ > 66666666
+#define CONFIG_SYS_SCCR	(/* SCCR_TBS     | */ SCCR_CRQEN | \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00 | SCCR_EBDF01)
+#else
+#define CONFIG_SYS_SCCR	(/* SCCR_TBS     | */ SCCR_CRQEN | \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+#endif
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+/*#define	CONFIG_SYS_DER	0x2002000F*/
+#define CONFIG_SYS_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x42000000	/* FLASH bank #1	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+
+#define FLASH_BANK_MAX_SIZE	0x01000000	/* max size per chip */
+
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000
+#define CONFIG_SYS_PRELIM_OR_AM	(0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1))
+
+/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_BI | OR_SCY_5_CLK | OR_TRLX)
+
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+
+#define CONFIG_SYS_OR1_PRELIM	((0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
+
+/*
+ * BR4 and OR4 (SDRAM)
+ *
+ */
+#define SDRAM_BASE1_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define	SDRAM_MAX_SIZE		(256 << 20)	/* max 256MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CONFIG_SYS_OR_TIMING_SDRAM	(OR_CSNT_SAM | OR_G5LS)
+
+#define CONFIG_SYS_OR4_PRELIM	((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM)
+#define CONFIG_SYS_BR4_PRELIM	((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V)
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ *	gclk	  CPU clock (not bus clock!)
+ *	Trefresh  Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096  Rows from SDRAM example configuration
+ * 1000  factor s -> ms
+ *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
+ *    4  Number of refresh cycles per period
+ *   64  Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ * 50 MHz => 50.000.000 / Divider =  98
+ * 66 Mhz => 66.000.000 / Divider = 129
+ * 80 Mhz => 80.000.000 / Divider = 156
+ */
+
+#define CONFIG_SYS_MAMR_PTA		 234
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ */
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+/* 9 column SDRAM */
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+#define CONFIG_LAST_STAGE_INIT		/* needed to reset the damn phys */
+
+/****************************************************************/
+
+#define NAND_SIZE	0x00010000	/* 64K */
+#define NAND_BASE	0xF1000000
+
+/*****************************************************************************/
+
+#define CONFIG_SYS_DIRECT_FLASH_TFTP
+
+/*****************************************************************************/
+
+/* Status Leds are on the MODCK pins, which become the PCMCIA PGCRB,
+ * CxOE and CxRESET.  We use the CxOE.
+ */
+#define STATUS_LED_BIT		0x00000080		/* bit 24 */
+
+#define STATUS_LED_PERIOD	(CONFIG_SYS_HZ / 2)
+#define STATUS_LED_STATE	STATUS_LED_BLINKING
+
+#define STATUS_LED_ACTIVE	0		/* LED on for bit == 0	*/
+#define STATUS_LED_BOOT		0		/* LED 0 used for boot status */
+
+#ifndef __ASSEMBLY__
+
+/* LEDs */
+
+/* led_id_t is unsigned int mask */
+typedef unsigned int led_id_t;
+
+#define __led_toggle(_msk) \
+	do { \
+		((volatile immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb ^= (_msk); \
+	} while(0)
+
+#define __led_set(_msk, _st) \
+	do { \
+		if ((_st)) \
+			((volatile immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb |= (_msk); \
+		else \
+			((volatile immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb &= ~(_msk); \
+	} while(0)
+
+#define __led_init(msk, st) __led_set(msk, st)
+
+#endif
+
+/******************************************************************************/
+
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV		1
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE	1
+#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE	1
+
+/******************************************************************************/
+
+/* use board specific hardware */
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+#define CONFIG_HW_WATCHDOG
+
+/*****************************************************************************/
+
+#define CONFIG_AUTO_COMPLETE	1
+#define CONFIG_CRC32_VERIFY	1
+#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE	1
+
+/*****************************************************************************/
+
+/* pass open firmware flattened device tree */
+#define CONFIG_OF_LIBFDT	1
+
+#define OF_TBCLK		(MPC8XX_HZ / 16)
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/suvd3.h b/qemu/roms/u-boot/include/configs/suvd3.h
new file mode 100644
index 000000000..fddba9238
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/suvd3.h
@@ -0,0 +1,147 @@
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ *                    Dave Liu <daveliu@freescale.com>
+ *
+ * Copyright (C) 2007 Logic Product Development, Inc.
+ *                    Peter Barada <peterb@logicpd.com>
+ *
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ *                    Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * (C) Copyright 2010
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+
+/* This needs to be set prior to including km/km83xx-common.h */
+#define	CONFIG_SYS_TEXT_BASE	0xF0000000
+
+#if defined(CONFIG_SUVD3)	/* SUVD3 board specific */
+#define CONFIG_HOSTNAME		suvd3
+#define CONFIG_KM_BOARD_NAME   "suvd3"
+/* include common defines/options for all 8321 Keymile boards */
+#include "km/km8321-common.h"
+#elif defined(CONFIG_KMVECT1)   /* VECT1 board specific */
+#define CONFIG_HOSTNAME		kmvect1
+#define CONFIG_KM_BOARD_NAME   "kmvect1"
+/* include common defines/options for all 8309 Keymile boards */
+#include "km/km8309-common.h"
+#else
+#error Supported boards are: SUVD3, KMVECT1
+#endif
+
+#define CONFIG_SYS_APP1_BASE		0xA0000000
+#define CONFIG_SYS_APP1_SIZE		256 /* Megabytes */
+#define CONFIG_SYS_APP2_BASE		0xB0000000
+#define CONFIG_SYS_APP2_SIZE		256 /* Megabytes */
+
+/* EEprom support */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+
+/*
+ * Init Local Bus Memory Controller:
+ *
+ * Bank Bus     Machine PortSz  Size  Device
+ * ---- ---     ------- ------  -----  ------
+ *  2   Local   UPMA    16 bit  256MB APP1
+ *  3   Local   GPCM    16 bit  256MB APP2
+ *
+ */
+
+/*
+ * APP1 on the local bus CS2
+ */
+#define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_APP1_BASE
+#define CONFIG_SYS_LBLAWAR2_PRELIM	(LBLAWAR_EN | LBLAWAR_256MB)
+
+#define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_APP1_BASE | \
+				 BR_PS_16 | \
+				 BR_MS_UPMA | \
+				 BR_V)
+#define CONFIG_SYS_OR2_PRELIM	(MEG_TO_AM(CONFIG_SYS_APP1_SIZE))
+
+#define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_APP2_BASE | \
+				 BR_PS_16 | \
+				 BR_V)
+
+#define CONFIG_SYS_OR3_PRELIM	(MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
+				 OR_GPCM_CSNT | \
+				 OR_GPCM_ACS_DIV4 | \
+				 OR_GPCM_SCY_3 | \
+				 OR_GPCM_TRLX_SET)
+
+#define CONFIG_SYS_MAMR	(MxMR_GPL_x4DIS | \
+			 0x0000c000 | \
+			 MxMR_WLFx_2X)
+
+#define CONFIG_SYS_LBLAWBAR3_PRELIM	CONFIG_SYS_APP2_BASE
+#define CONFIG_SYS_LBLAWAR3_PRELIM	(LBLAWAR_EN | LBLAWAR_256MB)
+
+/*
+ * MMU Setup
+ */
+
+
+/* APP1:  icache cacheable, but dcache-inhibit and guarded */
+#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_APP1_BASE | BATL_PP_RW | \
+				 BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_APP1_BASE | BATU_BL_256M | \
+				 BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT5L	(CONFIG_SYS_APP1_BASE | BATL_PP_RW | \
+				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
+
+#define CONFIG_SYS_IBAT6L	(CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
+				 BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U	(CONFIG_SYS_APP2_BASE | BATU_BL_256M | \
+				 BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT6L	(CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
+				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
+
+/*
+ * QE UEC ethernet configuration
+ */
+#if defined(CONFIG_KMVECT1)
+#define CONFIG_MV88E6352_SWITCH
+#define CONFIG_KM_MVEXTSW_ADDR		0x10
+
+/* ethernet port connected to simple switch 88e6122 (UEC0) */
+#define CONFIG_UEC_ETH1
+#define CONFIG_SYS_UEC1_UCC_NUM		0	/* UCC1 */
+#define CONFIG_SYS_UEC1_RX_CLK		QE_CLK9
+#define CONFIG_SYS_UEC1_TX_CLK		QE_CLK10
+
+#define CONFIG_FIXED_PHY		0xFFFFFFFF
+#define CONFIG_SYS_FIXED_PHY_ADDR	0x1E	/* unused address */
+#define CONFIG_SYS_FIXED_PHY_PORT(devnum, speed, duplex) \
+		{devnum, speed, duplex}
+#define CONFIG_SYS_FIXED_PHY_PORTS \
+		CONFIG_SYS_FIXED_PHY_PORT("UEC0", SPEED_100, DUPLEX_FULL)
+
+#define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
+#define CONFIG_SYS_UEC1_PHY_ADDR	CONFIG_SYS_FIXED_PHY_ADDR
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE	PHY_INTERFACE_MODE_MII
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED	100
+
+/* ethernet port connected to piggy (UEC2) */
+#define CONFIG_HAS_ETH1
+#define CONFIG_UEC_ETH2
+#define CONFIG_SYS_UEC2_UCC_NUM		2       /* UCC3 */
+#define CONFIG_SYS_UEC2_RX_CLK		QE_CLK_NONE /* not used in RMII Mode */
+#define CONFIG_SYS_UEC2_TX_CLK		QE_CLK12
+#define CONFIG_SYS_UEC2_ETH_TYPE	FAST_ETH
+#define CONFIG_SYS_UEC2_PHY_ADDR	0
+#define CONFIG_SYS_UEC2_INTERFACE_TYPE	PHY_INTERFACE_MODE_RMII
+#define CONFIG_SYS_UEC2_INTERFACE_SPEED	100
+#endif /* CONFIG_KMVECT1 */
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/svm_sc8xx.h b/qemu/roms/u-boot/include/configs/svm_sc8xx.h
new file mode 100644
index 000000000..b4aa94856
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/svm_sc8xx.h
@@ -0,0 +1,450 @@
+/*
+ * (C) Copyright 2000, 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific,
+ *                  for SinoVee Microsystems SC8xx series SBC
+ *                  http://www.fel.com.cn (Chinese)
+ *                  http://www.sinovee.com (English)
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define	CONFIG_SYS_TEXT_BASE	0x40000000
+
+/* Custom configuration */
+/* SC823,SC850,SC860SAR, FEL8xx-AT(823/850/860) */
+/* SC85T,SC860T, FEL8xx-AT(855T/860T) */
+/*#define CONFIG_FEL8xx_AT */
+/*#define CONFIG_LCD */
+/*#define CONFIG_MPC8XX_LCD*/
+/* if core > 50MHz , un-comment CONFIG_BUS_DIV2 */
+/* #define CONFIG_50MHz */
+/* #define CONFIG_66MHz */
+/* #define CONFIG_75MHz */
+#define CONFIG_80MHz
+/*#define CONFIG_100MHz */
+/* #define CONFIG_BUS_DIV2	1 */
+/* for BOOT device port size */
+/* #define CONFIG_BOOT_8B */
+#define CONFIG_BOOT_16B
+/* #define CONFIG_BOOT_32B */
+/* #define CONFIG_CAN_DRIVER */
+/* #define DEBUG */
+#define CONFIG_FEC_ENET
+
+/* #define CONFIG_SDRAM_16M */
+#define CONFIG_SDRAM_32M
+/* #define CONFIG_SDRAM_64M */
+#define CONFIG_SYS_RESET_ADDRESS 0xffffffff
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+/* #define CONFIG_MPC823		1 */
+/* #define CONFIG_MPC850		1 */
+#define CONFIG_MPC855		1
+/* #define CONFIG_MPC860		1 */
+/* #define CONFIG_MPC860T		1 */
+
+#undef	CONFIG_WATCHDOG			/* watchdog */
+
+#define CONFIG_SVM_SC8xx		1	/* ...on SVM SC8xx series	*/
+
+#ifdef	CONFIG_LCD			/* with LCD controller ?	*/
+/* #define CONFIG_NEC_NL6448BC20 1 / * use NEC NL6448BC20 display	*/
+#endif
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		19200	/* console baudrate = 115kbps	*/
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	1	/* autoboot after 5 seconds	*/
+#endif
+
+#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+
+#define CONFIG_BOARD_TYPES      1       /* support board types          */
+
+#define CONFIG_PREBOOT	"echo;echo Welcome to U-Boot SVM port;echo;echo Type \"? or help\" to get on-line help;echo"
+
+#undef	CONFIG_BOOTARGS
+#define CONFIG_EXTRA_ENV_SETTINGS                                       \
+	"nfsargs=setenv bootargs root=/dev/nfs rw "                     \
+	 "nfsroot=${serverip}:${rootpath}\0"                     \
+	"ramargs=setenv bootargs root=/dev/ram rw\0"                    \
+	"addip=setenv bootargs ${bootargs} "                            \
+	       "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
+		":${hostname}:${netdev}:off panic=1\0"                  \
+		"flash_nfs=run nfsargs addip;"                                  \
+	     "bootm ${kernel_addr}\0"                                \
+	"flash_self=run ramargs addip;"                                 \
+	       "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
+	"net_nfs=tftp 0x210000 ${bootfile};run nfsargs addip;bootm\0"     \
+	"rootpath=/opt/sinovee/ppc8xx-linux-2.0/target\0"                                  \
+	"bootfile=pImage-sc855t\0"                           \
+	"kernel_addr=48000000\0"                                        \
+	"ramdisk_addr=48100000\0"                                       \
+	""
+#define CONFIG_BOOTCOMMAND							\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
+	"tftpboot 0x210000 pImage-sc855t;bootm 0x210000"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+
+#ifdef CONFIG_LCD
+# undef	 CONFIG_STATUS_LED		/* disturbs display		*/
+#else
+# define CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+#endif	/* CONFIG_LCD */
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DATE
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+
+#ifdef  CONFIG_SYS_HUSH_PARSER
+#endif
+
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xFF000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#define	CONFIG_SYS_MONITOR_LEN		(384 << 10)	/* Reserve 192 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CONFIG_ENV_IS_IN_FLASH	1
+
+#ifdef CONFIG_BOOT_8B
+#define	CONFIG_ENV_OFFSET		0x10000	/*   Offset   of Environment Sector	*/
+#define	CONFIG_ENV_SIZE		0x10000	/* Total Size of Environment Sector	*/
+#elif defined (CONFIG_BOOT_16B)
+#define	CONFIG_ENV_OFFSET		0x10000	/*   Offset   of Environment Sector	*/
+#define	CONFIG_ENV_SIZE		0x10000	/* Total Size of Environment Sector	*/
+#elif defined (CONFIG_BOOT_32B)
+#define	CONFIG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
+#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+#endif
+
+/* Address and size of Redundant Environment Sector     */
+#define CONFIG_ENV_OFFSET_REDUND   (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND     (CONFIG_ENV_SIZE)
+
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC	0x46454C38	/* 'SVM8' */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+/*#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+*/
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CONFIG_SYS_SYPCR 0xffffff88
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef	CONFIG_CAN_DRIVER
+/*#define CONFIG_SYS_SIUMCR 0x00610c00	*/
+#define CONFIG_SYS_SIUMCR 0x00000000
+#else	/* we must activate GPL5 in the SIUMCR for CAN */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CONFIG_SYS_TBSCR	0x0001
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RTCSC	0x00c3
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CONFIG_SYS_PISCR	0x0000
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ */
+#if defined (CONFIG_100MHz)
+#define CONFIG_SYS_PLPRCR 0x06301000
+#define CONFIG_8xx_GCLK_FREQ 100000000
+#elif defined (CONFIG_80MHz)
+#define CONFIG_SYS_PLPRCR 0x04f01000
+#define CONFIG_8xx_GCLK_FREQ 80000000
+#elif defined(CONFIG_75MHz)
+#define CONFIG_SYS_PLPRCR 0x04a00100
+#define CONFIG_8xx_GCLK_FREQ 75000000
+#elif defined(CONFIG_66MHz)
+#define CONFIG_SYS_PLPRCR 0x04101000
+#define CONFIG_8xx_GCLK_FREQ 66000000
+#elif defined(CONFIG_50MHz)
+#define CONFIG_SYS_PLPRCR 0x03101000
+#define CONFIG_8xx_GCLK_FREQ 50000000
+#endif
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#ifdef	CONFIG_BUS_DIV2
+#define CONFIG_SYS_SCCR	0x02020000 | SCCR_RTSEL
+#else			/* up to 50 MHz we use a 1:1 clock */
+#define CONFIG_SYS_SCCR    0x02000000 | SCCR_RTSEL
+#endif
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#undef	CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/
+
+#define CONFIG_IDE_PREINIT	1	/* Use preinit IDE hook */
+#define CONFIG_IDE_INIT_POSTRESET	1	/* Use postreset IDE hook */
+#define	CONFIG_IDE_8xx_DIRECT	1	/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CONFIG_SYS_ATA_BASE_ADDR       0xFE100010
+#define CONFIG_SYS_ATA_IDE0_OFFSET     0x0000
+/*#define CONFIG_SYS_ATA_IDE1_OFFSET     0x0C00 */
+#define CONFIG_SYS_ATA_DATA_OFFSET     0x0000  /* Offset for data I/O
+					   */
+#define CONFIG_SYS_ATA_REG_OFFSET      0x0200  /* Offset for normal register accesses
+					   */
+#define CONFIG_SYS_ATA_ALT_OFFSET      0x0210  /* Offset for alternate registers
+					   */
+#define CONFIG_ATAPI
+#define CONFIG_SYS_PIO_MODE 0
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+/*#define	CONFIG_SYS_DER	0x2002000F*/
+#define CONFIG_SYS_DER	0x0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+#if defined(CONFIG_100MHz)
+#define CONFIG_SYS_OR_TIMING_FLASH 0x000002f4
+#define CONFIG_SYS_OR_TIMING_DOC   0x000002f4
+#define CONFIG_SYS_MxMR_PTx 0x61000000
+#define CONFIG_SYS_MPTPR 0x400
+
+#elif  defined(CONFIG_80MHz)
+#define CONFIG_SYS_OR_TIMING_FLASH 0x00000ff4
+#define CONFIG_SYS_OR_TIMING_DOC   0x000001f4
+#define CONFIG_SYS_MxMR_PTx 0x4e000000
+#define CONFIG_SYS_MPTPR 0x400
+
+#elif defined(CONFIG_75MHz)
+#define CONFIG_SYS_OR_TIMING_FLASH 0x000008f4
+#define CONFIG_SYS_OR_TIMING_DOC   0x000002f4
+#define CONFIG_SYS_MxMR_PTx 0x49000000
+#define CONFIG_SYS_MPTPR 0x400
+
+#elif defined(CONFIG_66MHz)
+#define CONFIG_SYS_OR_TIMING_FLASH     (OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+	OR_SCY_3_CLK | OR_EHTR | OR_BI)
+/*#define CONFIG_SYS_OR_TIMING_FLASH 0x000001f4 */
+#define CONFIG_SYS_OR_TIMING_DOC   0x000003f4
+#define CONFIG_SYS_MxMR_PTx  0x40000000
+#define CONFIG_SYS_MPTPR 0x400
+
+#else		/*   50 MHz */
+#define CONFIG_SYS_OR_TIMING_FLASH 0x00000ff4
+#define CONFIG_SYS_OR_TIMING_DOC   0x000001f4
+#define CONFIG_SYS_MxMR_PTx  0x30000000
+#define CONFIG_SYS_MPTPR 0x400
+#endif	/*CONFIG_??MHz */
+
+
+#if  defined (CONFIG_BOOT_8B)   /* 512K X 8 ,29F040 , 2MB space */
+#define CONFIG_SYS_OR0_PRELIM	(0xffe00000 | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_8)
+#elif  defined (CONFIG_BOOT_16B)   /* 29lv160 X 16 , 4MB space */
+#define CONFIG_SYS_OR0_PRELIM	(0xffc00000 | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16)
+#elif defined( CONFIG_BOOT_32B )  /* 29lv160 X 2 X 32, 4/8/16MB , 64MB space */
+#define CONFIG_SYS_OR0_PRELIM	(0xfc000000 | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+#else
+#error Boot device port size missing.
+#endif
+
+/*
+ * Disk-On-Chip configuration
+ */
+
+#define CONFIG_SYS_DOC_SHORT_TIMEOUT
+#define CONFIG_SYS_MAX_DOC_DEVICE      1       /* Max number of DOC devices    */
+
+#define CONFIG_SYS_DOC_SUPPORT_2000
+#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
+#define CONFIG_SYS_DOC_BASE 0x80000000
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/t3corp.h b/qemu/roms/u-boot/include/configs/t3corp.h
new file mode 100644
index 000000000..502e79597
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/t3corp.h
@@ -0,0 +1,539 @@
+/*
+ * (C) Copyright 2010
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * t3corp.h - configuration for T3CORP (460GT)
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_460GT		1	/* Specific PPC460GT	*/
+#define CONFIG_440		1
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xFFFA0000
+#endif
+
+#define CONFIG_HOSTNAME		t3corp
+
+/*
+ * Include common defines/options for all AMCC/APM eval boards
+ */
+#include "amcc-common.h"
+
+#define CONFIG_SYS_CLK_FREQ	66666667	/* external freq to pll	*/
+
+#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_early_init_f */
+#define CONFIG_BOARD_EARLY_INIT_R	1	/* Call board_early_init_r */
+#define CONFIG_MISC_INIT_R		1	/* Call misc_init_r */
+#define CONFIG_BOARD_TYPES		1	/* support board types */
+#define CONFIG_FIT
+#define CFG_ALT_MEMTEST
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped PCI memory */
+#define CONFIG_SYS_PCI_BASE		0xd0000000	/* internal PCI regs */
+#define CONFIG_SYS_PCI_TARGBASE	CONFIG_SYS_PCI_MEMBASE
+
+#define CONFIG_SYS_PCIE_MEMBASE		0xb0000000	/* mapped PCIe mem */
+#define CONFIG_SYS_PCIE_MEMSIZE		0x08000000	/* incr for PCIe */
+#define CONFIG_SYS_PCIE_BASE		0xc4000000	/* PCIe UTL regs */
+
+#define CONFIG_SYS_PCIE0_CFGBASE	0xc0000000
+#define CONFIG_SYS_PCIE1_CFGBASE	0xc1000000
+#define CONFIG_SYS_PCIE0_XCFGBASE	0xc3000000
+#define CONFIG_SYS_PCIE1_XCFGBASE	0xc3001000
+
+#define	CONFIG_SYS_PCIE0_UTLBASE	0xc08010000ULL	/* 36bit phys addr */
+
+/* base address of inbound PCIe window */
+#define CONFIG_SYS_PCIE_INBOUND_BASE	0x000000000ULL	/* 36bit phys addr */
+
+/* EBC stuff */
+#define CONFIG_SYS_FLASH_BASE		0xFC000000	/* later mapped here */
+#define CONFIG_SYS_FLASH_SIZE		(64 << 20)
+
+#define CONFIG_SYS_FPGA1_BASE		0xe0000000
+#define CONFIG_SYS_FPGA2_BASE		0xe2000000
+#define CONFIG_SYS_FPGA3_BASE		0xe4000000
+
+#define CONFIG_SYS_BOOT_BASE_ADDR	0xFF000000	/* EBC Boot Space */
+#define CONFIG_SYS_FLASH_BASE_PHYS_H	0x4
+#define CONFIG_SYS_FLASH_BASE_PHYS_L	0xCC000000
+#define CONFIG_SYS_FLASH_BASE_PHYS \
+	(((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) \
+	| (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
+
+#define CONFIG_SYS_OCM_BASE		0xE7000000	/* OCM: 64k */
+#define CONFIG_SYS_SRAM_BASE		0xE8000000	/* SRAM: 256k */
+#define CONFIG_SYS_SRAM_SIZE		(256 << 10)
+#define CONFIG_SYS_LOCAL_CONF_REGS	0xEF000000
+
+/*
+ * Initial RAM & stack pointer (placed in OCM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_BASE	/* OCM */
+#define CONFIG_SYS_INIT_RAM_SIZE	(4 << 10)
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+
+/*
+ * Environment
+ */
+/*
+ * Define here the location of the environment variables (flash).
+ */
+#define	CONFIG_ENV_IS_IN_FLASH		/* use flash for environment vars */
+
+/*
+ * Flash related
+ */
+#define CONFIG_SYS_FLASH_CFI		/* The flash is CFI compatible	*/
+#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* use status poll method	*/
+#define CONFIG_SYS_FLASH_PROTECTION	/* use hardware flash protection */
+
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE, \
+			(CONFIG_SYS_FPGA1_BASE + 0x01000000) }
+#define CONFIG_SYS_CFI_FLASH_CONFIG_REGS { 0xffff,	/* don't set	*/ \
+			0xbddf }		/* set async read mode	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max num of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sectors p. chip*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase/ms*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write/ms*/
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	/* buff'd writes (20x faster)*/
+#define CONFIG_SYS_FLASH_EMPTY_INFO	/* 'E' for empty sector on flinfo */
+
+#define CONFIG_ENV_SECT_SIZE		0x20000	/* sector size */
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_MONITOR_BASE - \
+					 CONFIG_ENV_SECT_SIZE)
+#define	CONFIG_ENV_SIZE			0x4000	/* env sector size */
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+/*
+ * DDR2 SDRAM
+ */
+#define CONFIG_SYS_MBYTES_SDRAM		256
+#define CONFIG_DDR_ECC
+#define CONFIG_AUTOCALIB	"silent\0"	/* default is non-verbose    */
+#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION	/* IBM DDR autocalibration   */
+#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION	/* dynamic DDR autocal debug */
+#undef CONFIG_PPC4xx_DDR_METHOD_A
+#define CONFIG_DDR_RFDC_FIXED		0x000001D7 /* optimal value */
+
+/* DDR1/2 SDRAM Device Control Register Data Values */
+/* Memory Queue */
+#define CONFIG_SYS_SDRAM_R0BAS		(SDRAM_RXBAS_SDBA_ENCODE(0) | \
+					 SDRAM_RXBAS_SDSZ_256)
+#define CONFIG_SYS_SDRAM_R1BAS		0x00000000
+#define CONFIG_SYS_SDRAM_R2BAS		0x00000000
+#define CONFIG_SYS_SDRAM_R3BAS		0x00000000
+#define CONFIG_SYS_SDRAM_PLBADDULL	0x00000000
+#define CONFIG_SYS_SDRAM_PLBADDUHB	0x00000008
+#define CONFIG_SYS_SDRAM_CONF1LL	0x80001C00
+#define CONFIG_SYS_SDRAM_CONF1HB	0x80001C80
+#define CONFIG_SYS_SDRAM_CONFPATHB	0x10a68000
+
+#define CAS_LATENCY			JEDEC_MA_MR_CL_DDR2_5_0_CLK
+
+/* DDR1/2 SDRAM Device Control Register Data Values */
+#define CONFIG_SYS_SDRAM0_MB0CF		(SDRAM_RXBAS_SDAM_MODE7		| \
+					 SDRAM_RXBAS_SDBE_ENABLE)
+#define CONFIG_SYS_SDRAM0_MB1CF		SDRAM_RXBAS_SDBE_DISABLE
+#define CONFIG_SYS_SDRAM0_MB2CF		SDRAM_RXBAS_SDBE_DISABLE
+#define CONFIG_SYS_SDRAM0_MB3CF		SDRAM_RXBAS_SDBE_DISABLE
+#define CONFIG_SYS_SDRAM0_MCOPT1	(SDRAM_MCOPT1_MCHK_GEN		| \
+					 SDRAM_MCOPT1_PMU_OPEN		| \
+					 SDRAM_MCOPT1_DMWD_32		| \
+					 SDRAM_MCOPT1_8_BANKS		| \
+					 SDRAM_MCOPT1_DDR2_TYPE		| \
+					 SDRAM_MCOPT1_QDEP		| \
+					 SDRAM_MCOPT1_RWOO_DISABLED	| \
+					 SDRAM_MCOPT1_WOOO_DISABLED	| \
+					 SDRAM_MCOPT1_DREF_NORMAL)
+#define CONFIG_SYS_SDRAM0_MCOPT2	0x00000000
+#define CONFIG_SYS_SDRAM0_MODT0		SDRAM_MODT_EB0W_ENABLE
+#define CONFIG_SYS_SDRAM0_MODT1		0x00000000
+#define CONFIG_SYS_SDRAM0_MODT2		0x00000000
+#define CONFIG_SYS_SDRAM0_MODT3		0x00000000
+#define CONFIG_SYS_SDRAM0_CODT		(SDRAM_CODT_RK0R_ON		| \
+					 SDRAM_CODT_DQS_1_8_V_DDR2	| \
+					 SDRAM_CODT_IO_NMODE)
+#define CONFIG_SYS_SDRAM0_RTR		SDRAM_RTR_RINT_ENCODE(1560)
+#define CONFIG_SYS_SDRAM0_INITPLR0					\
+	(SDRAM_INITPLR_ENABLE						| \
+	 SDRAM_INITPLR_IMWT_ENCODE(80)					| \
+	 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP))
+#define CONFIG_SYS_SDRAM0_INITPLR1					\
+	(SDRAM_INITPLR_ENABLE						| \
+	 SDRAM_INITPLR_IMWT_ENCODE(3)					| \
+	 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE)			| \
+	 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)				| \
+	 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
+#define CONFIG_SYS_SDRAM0_INITPLR2					\
+	(SDRAM_INITPLR_ENABLE						| \
+	 SDRAM_INITPLR_IMWT_ENCODE(2)					| \
+	 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)			| \
+	 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2)			| \
+	 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL))
+#define CONFIG_SYS_SDRAM0_INITPLR3					\
+	(SDRAM_INITPLR_ENABLE						| \
+	 SDRAM_INITPLR_IMWT_ENCODE(2)					| \
+	 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)			| \
+	 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3)			| \
+	 SDRAM_INITPLR_IMA_ENCODE(0))
+#define CONFIG_SYS_SDRAM0_INITPLR4					\
+	(SDRAM_INITPLR_ENABLE						| \
+	 SDRAM_INITPLR_IMWT_ENCODE(2)					| \
+	 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)			| \
+	 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)				| \
+	 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_ENABLE		| \
+				  JEDEC_MA_EMR_RTT_150OHM))
+#define CONFIG_SYS_SDRAM0_INITPLR5					\
+	(SDRAM_INITPLR_ENABLE						| \
+	 SDRAM_INITPLR_IMWT_ENCODE(200)					| \
+	 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)			| \
+	 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)				| \
+	 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC		| \
+				  CAS_LATENCY				| \
+				  JEDEC_MA_MR_BLEN_4			| \
+				  JEDEC_MA_MR_DLL_RESET))
+#define CONFIG_SYS_SDRAM0_INITPLR6					\
+	(SDRAM_INITPLR_ENABLE						| \
+	 SDRAM_INITPLR_IMWT_ENCODE(3)					| \
+	 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE)			| \
+	 SDRAM_INITPLR_IBA_ENCODE(0x0)					| \
+	 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
+#define CONFIG_SYS_SDRAM0_INITPLR7					\
+	(SDRAM_INITPLR_ENABLE						| \
+	 SDRAM_INITPLR_IMWT_ENCODE(26)					| \
+	 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
+#define CONFIG_SYS_SDRAM0_INITPLR8					\
+	(SDRAM_INITPLR_ENABLE						| \
+	 SDRAM_INITPLR_IMWT_ENCODE(26)					| \
+	 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
+#define CONFIG_SYS_SDRAM0_INITPLR9					\
+	(SDRAM_INITPLR_ENABLE						| \
+	 SDRAM_INITPLR_IMWT_ENCODE(26)					| \
+	 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
+#define CONFIG_SYS_SDRAM0_INITPLR10					\
+	(SDRAM_INITPLR_ENABLE						| \
+	 SDRAM_INITPLR_IMWT_ENCODE(26)					| \
+	 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
+#define CONFIG_SYS_SDRAM0_INITPLR11					\
+	(SDRAM_INITPLR_ENABLE						| \
+	 SDRAM_INITPLR_IMWT_ENCODE(2)					| \
+	 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)			| \
+	 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)				| \
+	 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC		| \
+				  CAS_LATENCY				| \
+				  JEDEC_MA_MR_BLEN_4))
+#define CONFIG_SYS_SDRAM0_INITPLR12					\
+	(SDRAM_INITPLR_ENABLE						| \
+	 SDRAM_INITPLR_IMWT_ENCODE(2)					| \
+	 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)			| \
+	 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)				| \
+	 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER		| \
+				  JEDEC_MA_EMR_RDQS_DISABLE		| \
+				  JEDEC_MA_EMR_DQS_ENABLE		| \
+				  JEDEC_MA_EMR_RTT_150OHM		| \
+				  JEDEC_MA_EMR_ODS_NORMAL))
+#define CONFIG_SYS_SDRAM0_INITPLR13					\
+	(SDRAM_INITPLR_ENABLE						| \
+	 SDRAM_INITPLR_IMWT_ENCODE(2)					| \
+	 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)			| \
+	 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)				| \
+	 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT			| \
+				  JEDEC_MA_EMR_RDQS_DISABLE		| \
+				  JEDEC_MA_EMR_DQS_ENABLE		| \
+				  JEDEC_MA_EMR_RTT_150OHM		| \
+				  JEDEC_MA_EMR_ODS_NORMAL))
+#define CONFIG_SYS_SDRAM0_INITPLR14	SDRAM_INITPLR_DISABLE
+#define CONFIG_SYS_SDRAM0_INITPLR15	SDRAM_INITPLR_DISABLE
+#define CONFIG_SYS_SDRAM0_RQDC		(SDRAM_RQDC_RQDE_ENABLE		| \
+					 SDRAM_RQDC_RQFD_ENCODE(56))
+#define CONFIG_SYS_SDRAM0_RFDC		SDRAM_RFDC_RFFD_ENCODE(599)
+#define CONFIG_SYS_SDRAM0_RDCC		(SDRAM_RDCC_RDSS_T2)
+#define CONFIG_SYS_SDRAM0_DLCR		(SDRAM_DLCR_DCLM_AUTO		| \
+					 SDRAM_DLCR_DLCS_CONT_DONE	| \
+					 SDRAM_DLCR_DLCV_ENCODE(155))
+#define CONFIG_SYS_SDRAM0_CLKTR		SDRAM_CLKTR_CLKP_90_DEG_ADV
+#define CONFIG_SYS_SDRAM0_WRDTR		SDRAM_WRDTR_WTR_90_DEG_ADV
+#define CONFIG_SYS_SDRAM0_SDTR1		(SDRAM_SDTR1_LDOF_2_CLK		| \
+					 SDRAM_SDTR1_RTW_2_CLK		| \
+					 SDRAM_SDTR1_RTRO_1_CLK)
+#define CONFIG_SYS_SDRAM0_SDTR2		(SDRAM_SDTR2_RCD_3_CLK		| \
+					 SDRAM_SDTR2_WTR_2_CLK		| \
+					 SDRAM_SDTR2_XSNR_32_CLK	| \
+					 SDRAM_SDTR2_WPC_4_CLK		| \
+					 SDRAM_SDTR2_RPC_2_CLK		| \
+					 SDRAM_SDTR2_RP_3_CLK		| \
+					 SDRAM_SDTR2_RRD_2_CLK)
+#define CONFIG_SYS_SDRAM0_SDTR3		(SDRAM_SDTR3_RAS_ENCODE(8)	| \
+					 SDRAM_SDTR3_RC_ENCODE(11)	| \
+					 SDRAM_SDTR3_XCS		| \
+					 SDRAM_SDTR3_RFC_ENCODE(26))
+#define CONFIG_SYS_SDRAM0_MMODE		(SDRAM_MMODE_WR_DDR2_3_CYC	| \
+					 CAS_LATENCY			| \
+					 SDRAM_MMODE_BLEN_4)
+#define CONFIG_SYS_SDRAM0_MEMODE	(SDRAM_MEMODE_DQS_ENABLE	| \
+					 SDRAM_MEMODE_RTT_150OHM)
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0			400000
+
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR		(0xa8>>1)
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
+
+/* I2C bootstrap EEPROM */
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR	0x52
+#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET	0
+#define CONFIG_4xx_CONFIG_BLOCKSIZE		16
+
+/*
+ * Ethernet
+ */
+#define CONFIG_IBM_EMAC4_V4	1
+
+#define CONFIG_HAS_ETH0
+
+#define CONFIG_PHY_ADDR		1	/* PHY address, See schematics	*/
+#define CONFIG_M88E1111_PHY
+/* Disable fiber since fiber/copper auto-selection doesn't seem to work */
+#define CONFIG_M88E1111_DISABLE_FIBER
+
+#define CONFIG_PHY_RESET	1	/* reset phy upon startup	*/
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+#define CONFIG_PHY_DYNAMIC_ANEG	1
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_AMCC_DEF_ENV						\
+	CONFIG_AMCC_DEF_ENV_POWERPC					\
+	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
+	"kernel_addr=fc000000\0"					\
+	"fdt_addr=fc1e0000\0"						\
+	"ramdisk_addr=fc200000\0"					\
+	"pciconfighost=1\0"						\
+	"pcie_mode=RP:RP\0"						\
+	"unlock=yes\0"							\
+	""
+
+/*
+ * Commands additional to the ones defined in amcc-common.h
+ */
+#define CONFIG_CMD_CHIP_CONFIG
+#define CONFIG_CMD_ECCTEST
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_SDRAM
+
+/*
+ * PCI stuff
+ */
+/* General PCI */
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play   */
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup  */
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE
+
+/* Board-specific PCI, no PCI support, only PCIe */
+#undef CONFIG_SYS_PCI_TARGET_INIT
+#undef CONFIG_SYS_PCI_MASTER_INIT
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014	/* IBM */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
+
+
+/*
+ * External Bus Controller (EBC) Setup
+ */
+
+/*
+ * T3CORP has 64MBytes of NOR flash (Spansion 29GL512), but the
+ * boot EBC mapping only supports a maximum of 16MBytes
+ * (4.ff00.0000 - 4.ffff.ffff).
+ * To solve this problem, the flash has to get remapped to another
+ * EBC address which accepts bigger regions:
+ *
+ * 0xfc00.0000 -> 4.cc00.0000
+ */
+
+/* Memory Bank 0 (NOR-flash) */
+#define CONFIG_SYS_EBC_PB0AP	(EBC_BXAP_BME_DISABLED		|	\
+				 EBC_BXAP_TWT_ENCODE(16)	|	\
+				 EBC_BXAP_BCE_DISABLE		|	\
+				 EBC_BXAP_BCT_2TRANS		|	\
+				 EBC_BXAP_CSN_ENCODE(1)		|	\
+				 EBC_BXAP_OEN_ENCODE(1)		|	\
+				 EBC_BXAP_WBN_ENCODE(1)		|	\
+				 EBC_BXAP_WBF_ENCODE(1)		|	\
+				 EBC_BXAP_TH_ENCODE(7)		|	\
+				 EBC_BXAP_RE_DISABLED		|	\
+				 EBC_BXAP_SOR_DELAYED		|	\
+				 EBC_BXAP_BEM_WRITEONLY		|	\
+				 EBC_BXAP_PEN_DISABLED)
+#define CONFIG_SYS_EBC_PB0CR	(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_BOOT_BASE_ADDR) | \
+				 EBC_BXCR_BS_16MB		|	\
+				 EBC_BXCR_BU_RW			|	\
+				 EBC_BXCR_BW_16BIT)
+
+/* Memory Bank 1 (FPGA 1) */
+#define CONFIG_SYS_EBC_PB1AP	(EBC_BXAP_BME_DISABLED		|	\
+				 EBC_BXAP_TWT_ENCODE(5)		|	\
+				 EBC_BXAP_CSN_ENCODE(0)		|	\
+				 EBC_BXAP_OEN_ENCODE(3)		|	\
+				 EBC_BXAP_WBN_ENCODE(0)		|	\
+				 EBC_BXAP_WBF_ENCODE(0)		|	\
+				 EBC_BXAP_TH_ENCODE(1)		|	\
+				 EBC_BXAP_RE_ENABLED		|	\
+				 EBC_BXAP_SOR_DELAYED		|	\
+				 EBC_BXAP_BEM_RW		|	\
+				 EBC_BXAP_PEN_DISABLED)
+#define CONFIG_SYS_EBC_PB1CR	(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA1_BASE) | \
+				 EBC_BXCR_BS_32MB		|	\
+				 EBC_BXCR_BU_RW			|	\
+				 EBC_BXCR_BW_32BIT)
+
+/* Memory Bank 2 (FPGA 2) */
+#define CONFIG_SYS_EBC_PB2AP	(EBC_BXAP_BME_DISABLED		|	\
+				 EBC_BXAP_TWT_ENCODE(5)		|	\
+				 EBC_BXAP_CSN_ENCODE(0)		|	\
+				 EBC_BXAP_OEN_ENCODE(3)		|	\
+				 EBC_BXAP_WBN_ENCODE(0)		|	\
+				 EBC_BXAP_WBF_ENCODE(0)		|	\
+				 EBC_BXAP_TH_ENCODE(1)		|	\
+				 EBC_BXAP_RE_ENABLED		|	\
+				 EBC_BXAP_SOR_DELAYED		|	\
+				 EBC_BXAP_BEM_RW		|	\
+				 EBC_BXAP_PEN_DISABLED)
+#define CONFIG_SYS_EBC_PB2CR	(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA2_BASE) | \
+				 EBC_BXCR_BS_16MB		|	\
+				 EBC_BXCR_BU_RW			|	\
+				 EBC_BXCR_BW_32BIT)
+
+/* Memory Bank 3 (FPGA 3) */
+#define CONFIG_SYS_EBC_PB3AP	(EBC_BXAP_BME_DISABLED		|	\
+				 EBC_BXAP_TWT_ENCODE(5)		|	\
+				 EBC_BXAP_CSN_ENCODE(0)		|	\
+				 EBC_BXAP_OEN_ENCODE(3)		|	\
+				 EBC_BXAP_WBN_ENCODE(0)		|	\
+				 EBC_BXAP_WBF_ENCODE(0)		|	\
+				 EBC_BXAP_TH_ENCODE(1)		|	\
+				 EBC_BXAP_RE_ENABLED		|	\
+				 EBC_BXAP_SOR_DELAYED		|	\
+				 EBC_BXAP_BEM_RW		|	\
+				 EBC_BXAP_PEN_DISABLED)
+#define CONFIG_SYS_EBC_PB3CR	(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA3_BASE) | \
+				 EBC_BXCR_BS_16MB		|	\
+				 EBC_BXCR_BU_RW			|	\
+				 EBC_BXCR_BW_32BIT)
+
+/*
+ * PPC4xx GPIO Configuration
+ */
+
+#define CONFIG_SYS_4xx_GPIO_TABLE { /*		  GPIO	Alternate1	Alternate2	Alternate3 */ \
+{											\
+/* GPIO Core 0 */									\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0	GMC1TxD(0)	USB2HostD(0)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1	GMC1TxD(1)	USB2HostD(1)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2	GMC1TxD(2)	USB2HostD(2)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3	GMC1TxD(3)	USB2HostD(3)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4	GMC1TxD(4)	USB2HostD(4)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5	GMC1TxD(5)	USB2HostD(5)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6	GMC1TxD(6)	USB2HostD(6)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7	GMC1TxD(7)	USB2HostD(7)	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8	GMC1RxD(0)	USB2OTGD(0)	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9	GMC1RxD(1)	USB2OTGD(1)	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2)	USB2OTGD(2)	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3)	USB2OTGD(3)	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4)	USB2OTGD(4)	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5)	USB2OTGD(5)	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6)	USB2OTGD(6)	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7)	USB2OTGD(7)	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMC1TxER	USB2HostStop	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD		USB2HostNext	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER	USB2HostDir	*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMC1TxEN	USB2OTGStop	*/	\
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS	USB2OTGNext	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV	USB2OTGDir	*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0)				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1)				*/	\
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2)				*/	\
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0	DMAReq2		IRQ(7)*/ \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1	DMAAck2		IRQ(8)*/ \
+},											\
+{											\
+/* GPIO Core 1 */									\
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2	EOT2/TC2	IRQ(9)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3	DMAReq3		IRQ(4)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N	UART1_DSR_CTS_N	UART2_SOUT*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3	UART3_SIN*/ \
+{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N	EOT3/TC3	UART3_SOUT*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N	UART1_SOUT	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N	UART1_SIN	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3)				*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1)				*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2)				*/	\
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3)		DMAReq1		IRQ(10)*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4)		DMAAck1		IRQ(11)*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5)		EOT/TC1		IRQ(12)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5)	DMAReq0		IRQ(13)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6)	DMAAck0		IRQ(14)*/ \
+{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7)	EOT/TC0		IRQ(15)*/ \
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit	*/	\
+{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit	*/	\
+}											\
+}
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/t4qds.h b/qemu/roms/u-boot/include/configs/t4qds.h
new file mode 100644
index 000000000..75609b9f6
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/t4qds.h
@@ -0,0 +1,339 @@
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Corenet DS style board configuration file
+ */
+#ifndef __T4QDS_H
+#define __T4QDS_H
+
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_CMD_REGINFO
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE
+#define CONFIG_E500			/* BOOKE e500 family */
+#define CONFIG_E500MC			/* BOOKE e500mc family */
+#define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
+#define CONFIG_MP			/* support multiple processors */
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xeff40000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+#define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC		CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_FSL_IFC			/* Enable IFC Support */
+#define CONFIG_PCI			/* Enable PCI/PCIE */
+#define CONFIG_PCIE1			/* PCIE controler 1 */
+#define CONFIG_PCIE2			/* PCIE controler 2 */
+#define CONFIG_PCIE3			/* PCIE controler 3 */
+#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
+
+#define CONFIG_SYS_SRIO
+#define CONFIG_SRIO1			/* SRIO port 1 */
+#define CONFIG_SRIO2			/* SRIO port 2 */
+
+#define CONFIG_FSL_LAW			/* Use common FSL init code */
+
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BTB			/* toggle branch predition */
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#endif
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP		64	/* number of TLB1 entries */
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_PANIC_HANG	/* do not reset board on panic */
+
+/*
+ *  Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
+#define CONFIG_SYS_L3_SIZE		(512 << 10)
+#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_ENV_ADDR			(CONFIG_SPL_GD_ADDR + 4 * 1024)
+#endif
+#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SPL_GD_ADDR + 12 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(50 << 10)
+#define CONFIG_SPL_RELOC_STACK		(CONFIG_SPL_GD_ADDR + 64 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE	(22 << 10)
+
+#define CONFIG_SYS_DCSRBAR		0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
+#define CONFIG_DIMM_SLOTS_PER_CTLR	2
+#define CONFIG_CHIP_SELECTS_PER_CTRL	4
+#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
+
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_FSL_DDR3
+
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE	0xe0000000
+#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe0ec000
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x118100
+
+/*
+ * RapidIO
+ */
+#define CONFIG_SYS_SRIO1_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
+#define CONFIG_SYS_SRIO1_MEM_SIZE	0x10000000	/* 256M */
+
+#define CONFIG_SYS_SRIO2_MEM_VIRT	0xb0000000
+#define CONFIG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
+#define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000	/* 256M */
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 2, Slot 2, tgtid 2, Base address 201000 */
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 3, Slot 1, tgtid 1, Base address 202000 */
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0xc0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc40000000ull
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 4, Base address 203000 */
+#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_PHYS	0xc60000000ull
+#define CONFIG_SYS_PCIE4_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
+#define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+#define CONFIG_E1000
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif	/* CONFIG_PCI */
+
+/* SATA */
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+
+#define CONFIG_SYS_SATA_MAX_DEVICE	2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
+
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_MII		/* MII PHY management */
+#define CONFIG_ETHPRIME		"FM1@DTSEC1"
+#define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ERRATA
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	"u-boot.bin"	/* U-Boot image on TFTP server*/
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+
+#define CONFIG_BAUDRATE	115200
+
+#define CONFIG_HVBOOT				\
+ "setenv bootargs config-addr=0x60000000; "	\
+ "bootm 0x01000000 - 0x00f00000"
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/taihu.h b/qemu/roms/u-boot/include/configs/taihu.h
new file mode 100644
index 000000000..5c0ce7a2e
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/taihu.h
@@ -0,0 +1,307 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2005-2007
+ * Beijing UD Technology Co., Ltd., taihusupport@amcc.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+
+#define CONFIG_405EP		1	/* this is a PPC405 CPU */
+#define CONFIG_TAIHU	        1	/*  on a taihu board */
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
+
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME		taihu
+#include "amcc-common.h"
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f */
+
+#define CONFIG_SYS_CLK_FREQ     33000000 /* external frequency to pll   */
+
+#define CONFIG_NO_SERIAL_EEPROM
+
+/*----------------------------------------------------------------------------*/
+#ifdef CONFIG_NO_SERIAL_EEPROM
+
+/*
+!-------------------------------------------------------------------------------
+! PLL settings for 333MHz CPU, 111MHz PLB/SDRAM, 55MHz EBC, 33MHz PCI,
+! assuming a 33MHz input clock to the 405EP from the C9531.
+!-------------------------------------------------------------------------------
+*/
+#define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 |  \
+			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |  \
+			      PLL_MALDIV_1 | PLL_PCIDIV_3)
+#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10  |  \
+			      PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
+			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
+#define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 |  \
+			       PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |  \
+			       PLL_MALDIV_1 | PLL_PCIDIV_1)
+#define PLLMR1_333_111_55_111 (PLL_FBKDIV_10  |  \
+			       PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
+			       PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
+
+#define PLLMR0_DEFAULT		PLLMR0_333_111_55_37
+#define PLLMR1_DEFAULT		PLLMR1_333_111_55_37
+#define PLLMR0_DEFAULT_PCI66	PLLMR0_333_111_55_111
+#define PLLMR1_DEFAULT_PCI66	PLLMR1_333_111_55_111
+
+#endif
+/*----------------------------------------------------------------------------*/
+
+#define CONFIG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars */
+
+/*
+ * Default environment variables
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_AMCC_DEF_ENV						\
+	CONFIG_AMCC_DEF_ENV_PPC						\
+	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
+	"kernel_addr=FC000000\0"					\
+	"ramdisk_addr=FC180000\0"					\
+	""
+
+#define CONFIG_PHY_ADDR		0x14	/* PHY address			*/
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_PHY1_ADDR	0x10	/* EMAC1 PHY address		*/
+#define CONFIG_PHY_RESET	1
+
+/*
+ * Commands additional to the ones defined in amcc-common.h
+ */
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SPI
+
+#undef CONFIG_SPD_EEPROM		/* use SPD EEPROM for setup */
+#define CONFIG_SYS_SDRAM_SIZE_PER_BANK 0x04000000 /* 64MB */
+#define CONFIG_SYS_SDRAM_BANKS	        2
+
+/*
+ * SDRAM configuration (please see cpu/ppc/sdram.[ch])
+ */
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0 */
+#define CONFIG_SDRAM_BANK1	1	/* init onboard SDRAM bank 1 */
+
+/* SDRAM timings used in datasheet */
+#define CONFIG_SYS_SDRAM_CL            3	/* CAS latency */
+#define CONFIG_SYS_SDRAM_tRP           20	/* PRECHARGE command period */
+#define CONFIG_SYS_SDRAM_tRC           66	/* ACTIVE-to-ACTIVE command period */
+#define CONFIG_SYS_SDRAM_tRCD          20	/* ACTIVE-to-READ delay */
+#define CONFIG_SYS_SDRAM_tRFC		66	/* Auto refresh period */
+
+/*
+ * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
+ * The Linux BASE_BAUD define should match this configuration.
+ *    baseBaud = cpuClock/(uartDivisor*16)
+ * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * set Linux BASE_BAUD to 403200.
+ */
+#define CONFIG_CONS_INDEX	2	/* Use UART1			*/
+#undef  CONFIG_SYS_EXT_SERIAL_CLOCK           /* external serial clock */
+#undef  CONFIG_SYS_405_UART_ERRATA_59         /* 405GP/CR Rev. D silicon */
+#define CONFIG_SYS_BASE_BAUD		691200
+
+/*-----------------------------------------------------------------------
+ * I2C stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
+
+#define CONFIG_SYS_I2C_NOPROBES	{ {0, 0x69} } /* avoid i2c probe hangup (?) */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	6 /* 24C02 requires 5ms delay */
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* I2C boot EEPROM (24C02W)	*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/
+
+#define CONFIG_SOFT_SPI
+#define SPI_SCL  spi_scl
+#define SPI_SDA  spi_sda
+#define SPI_READ spi_read()
+#define SPI_DELAY udelay(2)
+#ifndef __ASSEMBLY__
+void spi_scl(int);
+void spi_sda(int);
+unsigned char spi_read(void);
+#endif
+
+/* standard dtt sensor configuration */
+#define CONFIG_DTT_DS1775	1
+#define CONFIG_DTT_SENSORS	{ 0 }
+#define CONFIG_SYS_I2C_DTT_ADDR	0x49
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0		/* configure ar pci adapter    */
+#define PCI_HOST_FORCE   1		/* configure as pci host       */
+#define PCI_HOST_AUTO    2		/* detected via arbiter enable */
+
+#define CONFIG_PCI			/* include pci support	       */
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_HOST	PCI_HOST_FORCE  /* select pci host function    */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play        */
+					/* resource configuration      */
+#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
+#define CONFIG_SYS_PCI_CLASSCODE       0x0600  /* PCI Class Code: bridge/host */
+#define CONFIG_SYS_PCI_PTM1LA	    0x00000000	/* point to sdram              */
+#define CONFIG_SYS_PCI_PTM1MS      0x80000001	/* 2GB, enable hard-wired to 1 */
+#define CONFIG_SYS_PCI_PTM1PCI     0x00000000	/* Host: use this pci address  */
+#define CONFIG_SYS_PCI_PTM2LA      0x00000000	/* disabled                    */
+#define CONFIG_SYS_PCI_PTM2MS	    0x00000000	/* disabled                    */
+#define CONFIG_SYS_PCI_PTM2PCI     0x04000000	/* Host: use this pci address  */
+#define CONFIG_EEPRO100		1
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ */
+#define CONFIG_SYS_FLASH_BASE		0xFFE00000
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CONFIG_SYS_FLASH_ADDR0         0x555
+#define CONFIG_SYS_FLASH_ADDR1         0x2aa
+#define CONFIG_SYS_FLASH_WORD_SIZE     unsigned short
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	0x10000	/* size of one complete sector	*/
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+#endif /* CONFIG_ENV_IS_IN_FLASH */
+
+/*-----------------------------------------------------------------------
+ * NVRAM organization
+ */
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xf0000000	/* NVRAM base address */
+#define CONFIG_SYS_NVRAM_SIZE		0x1ff8		/* NVRAM size */
+
+#ifdef CONFIG_ENV_IS_IN_NVRAM
+#define CONFIG_ENV_SIZE		0x0ff8		/* Size of Environment vars */
+#define CONFIG_ENV_ADDR		\
+	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE)	/* Env*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * PPC405 GPIO Configuration
+ */
+#define CONFIG_SYS_4xx_GPIO_TABLE { /*				GPIO	Alternate1		*/	\
+{												\
+/* GPIO Core 0 */										\
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO0	PerBLast    SPI CS	*/	\
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO1	TS1E			*/	\
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO2	TS2E			*/	\
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO3	TS1O			*/	\
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO4	TS2O			*/	\
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO5	TS3			*/	\
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO6	TS4			*/	\
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO7	TS5			*/	\
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO8	TS6			*/	\
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO9	TrcClk			*/	\
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10	PerCS1			*/	\
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11	PerCS2			*/	\
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12	PerCS3			*/	\
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13	PerCS4			*/	\
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO14	PerAddr03   SPI SCLK	*/	\
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO15	PerAddr04   SPI DI	*/	\
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO16	PerAddr05   SPI DO	*/	\
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17	IRQ0	    PCI INTA	*/	\
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18	IRQ1	    PCI INTB	*/	\
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19	IRQ2	    PCI INTC	*/	\
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO20	IRQ3	    PCI INTD	*/	\
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO21	IRQ4	    USB		*/	\
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO22	IRQ5	    EBC		*/	\
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO23	IRQ6	    unused	*/	\
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24	UART0_DCD   UART1	*/	\
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25	UART0_DSR		*/	\
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26	UART0_RI		*/	\
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27	UART0_DTR		*/	\
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28	UART1_Rx    UART0	*/	\
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29	UART1_Tx		*/	\
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO30	RejectPkt0  User LED1	*/	\
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO31	RejectPkt1  User LED2	*/	\
+}												\
+}
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
+#define FLASH_BASE1_PRELIM  0xFC000000	/* FLASH bank #1 */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory (OCM) for temperary stack until sdram is tested */
+#define CONFIG_SYS_TEMP_STACK_OCM        1
+
+/* On Chip Memory location */
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
+
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash/SRAM) initialization */
+#define CONFIG_SYS_EBC_PB0AP           0x03815600
+#define CONFIG_SYS_EBC_PB0CR           0xFFE3A000  /* BAS=0xFFE,BS=2MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (NVRAM/RTC) initialization */
+#define CONFIG_SYS_EBC_PB1AP           0x05815600
+#define CONFIG_SYS_EBC_PB1CR           0xFC0BA000  /* BAS=0xFc0,BS=32MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 2 (USB device) initialization */
+#define CONFIG_SYS_EBC_PB2AP           0x03016600
+#define CONFIG_SYS_EBC_PB2CR           0x50018000 /* BAS=0x500,BS=1MB,BU=R/W,BW=8bit */
+
+/* Memory Bank 3 (LCM and D-flip-flop) initialization */
+#define CONFIG_SYS_EBC_PB3AP           0x158FF600
+#define CONFIG_SYS_EBC_PB3CR           0x50118000 /* BAS=0x501,BS=1MB,BU=R/W,BW=8bit */
+
+/* Memory Bank 4 (not install) initialization */
+#define CONFIG_SYS_EBC_PB4AP           0x158FF600
+#define CONFIG_SYS_EBC_PB4CR           0x5021A000
+
+#define CPLD_REG0_ADDR	0x50100000
+#define CPLD_REG1_ADDR	0x50100001
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/taishan.h b/qemu/roms/u-boot/include/configs/taishan.h
new file mode 100644
index 000000000..3d5c351b1
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/taishan.h
@@ -0,0 +1,193 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/************************************************************************
+ * TAISHAN.h - configuration for AMCC 440GX Ref
+ ***********************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_TAISHAN		1	/* Board is taishan		*/
+#define CONFIG_440GX		1	/* Specifc GX support		*/
+#define CONFIG_440		1	/* ... PPC440 family		*/
+#define CONFIG_SYS_CLK_FREQ	33333333 /* external freq to pll	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
+
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME		taishan
+#define CONFIG_USE_TTY		ttyS1
+#include "amcc-common.h"
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_pre_init		*/
+#define CONFIG_MISC_INIT_R	1	/* Call misc_init_r		*/
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_FLASH_BASE		0xfc000000	/* start of FLASH	*/
+#define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped pci memory	*/
+#define CONFIG_SYS_ISRAM_BASE		0xc0000000	/* internal SRAM	*/
+#define CONFIG_SYS_PCI_BASE		0xd0000000	/* internal PCI regs	*/
+
+#define CONFIG_SYS_EBC0_FLASH_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_EBC1_FPGA_BASE	(CONFIG_SYS_PERIPHERAL_BASE + 0x01000000)
+#define CONFIG_SYS_EBC2_LCM_BASE	(CONFIG_SYS_PERIPHERAL_BASE + 0x02000000)
+#define CONFIG_SYS_EBC3_CONN_BASE	(CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
+
+#define CONFIG_SYS_GPIO_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in internal SRAM)
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_TEMP_STACK_OCM	1
+#define CONFIG_SYS_OCM_DATA_ADDR	CONFIG_SYS_ISRAM_BASE
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_ISRAM_BASE  /* Initial RAM address	*/
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000		/* Size of used area in RAM*/
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#define CONFIG_CONS_INDEX	2	/* Use UART1			*/
+#define CONFIG_SYS_EXT_SERIAL_CLOCK	(1843200 * 6)	/* Ext clk @ 11.059 MHz */
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+#define CONFIG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+
+#define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_MAX_FLASH_BANKS     1		    /* number of banks	    */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024		    /* sectors per device   */
+
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CONFIG_ENV_SECT_SIZE	0x40000 /* size of one complete sector	*/
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
+#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+/*-----------------------------------------------------------------------
+ * E2PROM bootstrap configure value
+ *----------------------------------------------------------------------*/
+
+/*
+ * 800/133/66
+ * IIC 0~15: 86 78 11 6a 61 A7 04 62 00 00 00 00 00 00 00 00
+ */
+
+/*
+ * 800/160/80
+ * IIC 0~15: 86 78 c1 a6 09 67 04 63 00 00 00 00 00 00 00 00
+ */
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#undef CONFIG_SPD_EEPROM		/* Don't use SPD EEPROM for setup	*/
+#define CONFIG_SDRAM_BANK0	1	/* init onboard DDR SDRAM bank 0	*/
+#define	CONFIG_SYS_SDRAM0_TR0		0xC10A401A
+#undef CONFIG_SDRAM_ECC			/* enable ECC support			*/
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
+
+#undef CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+#define CONFIG_SYS_BOOTSTRAP_IIC_ADDR	0x50
+
+/* I2C SYSMON (LM75, AD7414 is almost compatible)			*/
+#define CONFIG_DTT_LM75		1		/* ON Semi's LM75	*/
+#define CONFIG_DTT_SENSORS	{0}		/* Sensor addresses	*/
+#define CONFIG_SYS_DTT_MAX_TEMP	70
+#define CONFIG_SYS_DTT_LOW_TEMP	-30
+#define CONFIG_SYS_DTT_HYSTERESIS	3
+
+/*
+ * Default environment variables
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_AMCC_DEF_ENV						\
+	CONFIG_AMCC_DEF_ENV_POWERPC					\
+	CONFIG_AMCC_DEF_ENV_PPC_OLD					\
+	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
+	"kernel_addr=fc000000\0"					\
+	"ramdisk_addr=fc180000\0"					\
+	"kozio=bootm 0xffe00000\0"					\
+	""
+
+/*-----------------------------------------------------------------------
+ * Networking
+ *----------------------------------------------------------------------*/
+#define CONFIG_EMAC_NR_START	2	/* start with EMAC 2 (skip 0&1)	*/
+#define CONFIG_PHY_ADDR		0xff	     /* no phy on EMAC0		*/
+#define CONFIG_PHY1_ADDR	0xff	     /* no phy on EMAC1		*/
+#define CONFIG_PHY2_ADDR	0x1
+#define CONFIG_PHY3_ADDR	0x3
+#define CONFIG_ET1011C_PHY	1
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH2
+#define CONFIG_HAS_ETH3
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+#define CONFIG_PHY_RESET        1       /* reset phy upon startup         */
+#define CONFIG_PHY_RESET_DELAY	1000
+
+/*
+ * Commands additional to the ones defined in amcc-common.h
+ */
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_PCI
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+/* General PCI */
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+#define CONFIG_EEPRO100       1		/* include PCI EEPRO100		*/
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
+#define CONFIG_SYS_PCI_TARGBASE    0x80000000	/* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
+
+/* Board-specific PCI */
+#define CONFIG_SYS_PCI_TARGET_INIT		/* let board init pci target    */
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/tam3517-common.h b/qemu/roms/u-boot/include/configs/tam3517-common.h
new file mode 100644
index 000000000..3522c1a07
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/tam3517-common.h
@@ -0,0 +1,427 @@
+/*
+ * Copyright (C) 2011
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * Copyright (C) 2009 TechNexion Ltd.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __TAM3517_H
+#define __TAM3517_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_OMAP		/* in a TI OMAP core */
+#define CONFIG_OMAP34XX		/* which is a 34XX */
+#define CONFIG_OMAP_GPIO
+#define CONFIG_OMAP_COMMON
+
+#define CONFIG_SYS_TEXT_BASE 0x80008000
+
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
+#define CONFIG_EMIF4	/* The chip has EMIF4 controller */
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Clock Defines */
+#define V_OSCK			26000000	/* Clock output from T2 */
+#define V_SCLK			(V_OSCK >> 1)
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB sector */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10) + \
+					2 * 1024 * 1024)
+/*
+ * DDR related
+ */
+#define CONFIG_OMAP3_MICRON_DDR		/* Micron DDR */
+#define CONFIG_SYS_CS0_SIZE		(256 * 1024 * 1024)
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		48000000	/* 48MHz (APLL96/2) */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550_COM1		OMAP34XX_UART1
+#define CONFIG_SERIAL1			/* UART1 */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
+					115200}
+#define CONFIG_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DOS_PARTITION
+
+/* EHCI */
+#define CONFIG_OMAP3_GPIO_5
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_OMAP
+#define CONFIG_USB_ULPI
+#define CONFIG_USB_ULPI_VIEWPORT_OMAP
+#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO	25
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
+#define CONFIG_USB_STORAGE
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
+#define CONFIG_CMD_FAT		/* FAT support			*/
+#define CONFIG_CMD_GPIO
+#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MMC		/* MMC support			*/
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_NAND		/* NAND support			*/
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_EEPROM
+
+#undef CONFIG_CMD_FLASH		/* only NAND on the SOM */
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED	400000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
+#define CONFIG_SYS_I2C_OMAP34XX
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50		/* base address */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1		/* bytes of address */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
+							/* to access */
+							/* nand at CS0 */
+
+#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
+							/* NAND devices */
+
+#define CONFIG_AUTO_COMPLETE
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		32	/* max number of command */
+						/* args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
+#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
+					0x01F00000) /* 31MB */
+
+#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
+								/* address */
+
+/*
+ * AM3517 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
+#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
+#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
+
+/*
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+
+/* Configure the PISMO */
+#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
+
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_ENV_IS_IN_NAND
+#define SMNAND_ENV_OFFSET		0x180000 /* environment starts here */
+
+/* Redundant Environment */
+#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
+#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
+#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
+						2 * CONFIG_SYS_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE	0x800
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+
+/*
+ * ethernet support, EMAC
+ *
+ */
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_DRIVER_TI_EMAC_USE_RMII
+#define CONFIG_MII
+#define CONFIG_EMAC_MDIO_PHY_NUM	0
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT 10
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_CONSOLE
+#define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SPL_NAND_SOFTECC
+#define CONFIG_SPL_NAND_WORKSPACE	0x8f07f000 /* below BSS */
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
+
+#define CONFIG_SPL_TEXT_BASE		0x40200000 /*CONFIG_SYS_SRAM_START*/
+#define CONFIG_SPL_MAX_SIZE		(54 * 1024)	/* 8 KB for stack */
+#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
+
+#define CONFIG_SYS_SPL_MALLOC_START	0x8f000000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
+#define CONFIG_SPL_BSS_START_ADDR	0x8f080000 /* end of RAM */
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
+
+/* NAND boot config */
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
+#define CONFIG_SYS_NAND_ECCPOS		{40, 41, 42, 43, 44, 45, 46, 47,\
+					 48, 49, 50, 51, 52, 53, 54, 55,\
+					 56, 57, 58, 59, 60, 61, 62, 63}
+#define CONFIG_SYS_NAND_ECCSIZE		256
+#define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_SW
+
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x80000
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_FIT
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_CMD_MTDPARTS
+
+/* Setup MTD for NAND on the SOM */
+#define MTDIDS_DEFAULT		"nand0=omap2-nand.0"
+#define MTDPARTS_DEFAULT	"mtdparts=omap2-nand.0:512k(MLO)," \
+				"1m(u-boot),256k(env1)," \
+				"256k(env2),6m(kernel),-(rootfs)"
+
+#define	CONFIG_TAM3517_SETTINGS						\
+	"netdev=eth0\0"							\
+	"nandargs=setenv bootargs root=${nandroot} "			\
+		"rootfstype=${nandrootfstype}\0"			\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip_sta=setenv bootargs ${bootargs} "			\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0"		\
+	"addip=if test -n ${ipdyn};then run addip_dyn;"			\
+		"else run addip_sta;fi\0"				\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
+	"addtty=setenv bootargs ${bootargs}"				\
+		" console=ttyO0,${baudrate}\0"				\
+	"addmisc=setenv bootargs ${bootargs} ${misc}\0"			\
+	"loadaddr=82000000\0"						\
+	"kernel_addr_r=82000000\0"					\
+	"hostname=" __stringify(CONFIG_HOSTNAME) "\0"			\
+	"bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0"		\
+	"flash_self=run ramargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"flash_nfs=run nfsargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr}\0"				\
+	"nandboot=run nandargs addip addtty addmtd addmisc;"		\
+		"nand read ${kernel_addr_r} kernel\0"			\
+		"bootm ${kernel_addr_r}\0"				\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
+		"run nfsargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr_r}\0"				\
+	"net_self=if run net_self_load;then "				\
+		"run ramargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr_r} ${ramdisk_addr_r};"		\
+		"else echo Images not loades;fi\0"			\
+	"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0"		\
+	"load=tftp ${loadaddr} ${u-boot}\0"				\
+	"loadmlo=tftp ${loadaddr} ${mlo}\0"				\
+	"mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0"			\
+	"uboot_addr=0x80000\0"						\
+	"update=nandecc sw;nand erase ${uboot_addr} 100000;"		\
+		"nand write ${loadaddr} ${uboot_addr} 80000\0"		\
+	"updatemlo=nandecc hw;nand erase 0 20000;"			\
+		"nand write ${loadaddr} 0 20000\0"			\
+	"upd=if run load;then echo Updating u-boot;if run update;"	\
+		"then echo U-Boot updated;"				\
+			"else echo Error updating u-boot !;"		\
+			"echo Board without bootloader !!;"		\
+		"fi;"							\
+		"else echo U-Boot not downloaded..exiting;fi\0"		\
+
+
+/*
+ * this is common code for all TAM3517 boards.
+ * MAC address is stored from manufacturer in
+ * I2C EEPROM
+ */
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+/*
+ * The I2C EEPROM on the TAM3517 contains
+ * mac address and production data
+ */
+struct tam3517_module_info {
+	char customer[48];
+	char product[48];
+
+	/*
+	 * bit 0~47  : sequence number
+	 * bit 48~55 : week of year, from 0.
+	 * bit 56~63 : year
+	 */
+	unsigned long long sequence_number;
+
+	/*
+	 * bit 0~7   : revision fixed
+	 * bit 8~15  : revision major
+	 * bit 16~31 : TNxxx
+	 */
+	unsigned int revision;
+	unsigned char eth_addr[4][8];
+	unsigned char _rev[100];
+};
+
+#define TAM3517_READ_EEPROM(info, ret) \
+do {								\
+	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \
+	if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,		\
+		(void *)info, sizeof(*info)))			\
+		ret = 1;					\
+	else							\
+		ret = 0;					\
+} while (0)
+
+#define TAM3517_READ_MAC_FROM_EEPROM(info)			\
+do {								\
+	char buf[80], ethname[20];				\
+	int i;							\
+	memset(buf, 0, sizeof(buf));				\
+	for (i = 0 ; i < ARRAY_SIZE((info)->eth_addr); i++) {	\
+		sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X",	\
+			(info)->eth_addr[i][5],			\
+			(info)->eth_addr[i][4],			\
+			(info)->eth_addr[i][3],			\
+			(info)->eth_addr[i][2],			\
+			(info)->eth_addr[i][1],			\
+			(info)->eth_addr[i][0]);			\
+								\
+		if (i)						\
+			sprintf(ethname, "eth%daddr", i);	\
+		else						\
+			sprintf(ethname, "ethaddr");		\
+		printf("Setting %s from EEPROM with %s\n", ethname, buf);\
+		setenv(ethname, buf);				\
+	}							\
+} while (0)
+
+/* The following macros are taken from Technexion's documentation */
+#define TAM3517_sequence_number(info) \
+	((info)->sequence_number % 0x1000000000000LL)
+#define TAM3517_week_of_year(info) (((info)->sequence_number >> 48) % 0x100)
+#define TAM3517_year(info) ((info)->sequence_number >> 56)
+#define TAM3517_revision_fixed(info) ((info)->revision % 0x100)
+#define TAM3517_revision_major(info) (((info)->revision >> 8) % 0x100)
+#define TAM3517_revision_tn(info) ((info)->revision >> 16)
+
+#define TAM3517_PRINT_SOM_INFO(info)				\
+do {								\
+	printf("Vendor:%s\n", (info)->customer);		\
+	printf("SOM:   %s\n", (info)->product);			\
+	printf("SeqNr: %02llu%02llu%012llu\n",			\
+		TAM3517_year(info),				\
+		TAM3517_week_of_year(info),			\
+		TAM3517_sequence_number(info));			\
+	printf("Rev:   TN%u %u.%u\n",				\
+		TAM3517_revision_tn(info),			\
+		TAM3517_revision_major(info),			\
+		TAM3517_revision_fixed(info));			\
+} while (0)
+
+#endif
+
+#endif /* __TAM3517_H */
diff --git a/qemu/roms/u-boot/include/configs/tao3530.h b/qemu/roms/u-boot/include/configs/tao3530.h
new file mode 100644
index 000000000..9c04c23ab
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/tao3530.h
@@ -0,0 +1,370 @@
+/*
+ * Configuration settings for the TechNexion TAO-3530 SOM
+ * equipped on Thunder baseboard.
+ *
+ * Edward Lin <linuxfae@technexion.com>
+ * Tapani Utriainen <linuxfae@technexion.com>
+ *
+ * Copyright (C) 2013 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMV7			/* This is an ARM V7 CPU core */
+#define CONFIG_OMAP			/* in a TI OMAP core */
+#define CONFIG_OMAP34XX			/* which is a 34XX */
+
+#define CONFIG_OMAP_GPIO
+#define CONFIG_OMAP_COMMON
+
+#define MACH_TYPE_OMAP3_TAO3530		2836
+
+#define CONFIG_SDRC			/* Has an SDRC controller */
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Clock Defines */
+#define V_OSCK			26000000	/* Clock output from T2 */
+#define V_SCLK			(V_OSCK >> 1)
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(4 << 20)
+#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB sector */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX		3
+#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_DOS_PARTITION
+
+/* GPIO banks */
+#define CONFIG_OMAP3_GPIO_2		/* GPIO32 ..63  is in GPIO bank 2 */
+#define CONFIG_OMAP3_GPIO_3		/* GPIO64 ..95  is in GPIO bank 3 */
+#define CONFIG_OMAP3_GPIO_4		/* GPIO96 ..127 is in GPIO bank 4 */
+#define CONFIG_OMAP3_GPIO_5		/* GPIO128..159 is in GPIO bank 5 */
+#define CONFIG_OMAP3_GPIO_6		/* GPIO160..191 is in GPIO bank 6 */
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
+#define CONFIG_CMD_FAT		/* FAT support			*/
+#define CONFIG_CMD_MTDPARTS	/* Enable MTD parts commands */
+#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
+#define MTDIDS_DEFAULT			"nand0=nand"
+#define MTDPARTS_DEFAULT		"mtdparts=nand:512k(x-loader),"\
+					"1920k(u-boot),128k(u-boot-env),"\
+					"4m(kernel),-(fs)"
+
+#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
+#define CONFIG_CMD_MMC		/* MMC support			*/
+#define CONFIG_CMD_NAND		/* NAND support			*/
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+
+#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
+#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
+#undef CONFIG_CMD_IMI		/* iminfo			*/
+#undef CONFIG_CMD_IMLS		/* List all found images	*/
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_OMAP34XX
+#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
+#define CONFIG_I2C_MULTI_BUS
+
+/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER
+#define CONFIG_TWL4030_LED
+
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_SYS_NAND_QUIET_TEST
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
+							/* to access nand */
+#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
+							/* to access nand at */
+							/* CS0 */
+#define GPMC_NAND_ECC_LP_x16_LAYOUT
+
+#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
+							/* devices */
+/* Environment information */
+#define CONFIG_BOOTDELAY		3
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x82000000\0" \
+	"console=ttyO2,115200n8\0" \
+	"mpurate=600\0" \
+	"dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \
+	"tv_mode=omapfb.mode=tv:ntsc\0" \
+	"video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \
+	"lcd_mode=omapfb.mode=lcd:800x480@60 \0" \
+	"extra_options= \0" \
+	"mmcdev=0\0" \
+	"mmcroot=/dev/mmcblk0p2 rw\0" \
+	"mmcrootfstype=ext3 rootwait\0" \
+	"nandroot=ubi0:rootfs ubi.mtd=4\0" \
+	"nandrootfstype=ubifs\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"mpurate=${mpurate} " \
+		"${video_mode} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype} " \
+		"${extra_options}\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"mpurate=${mpurate} " \
+		"${video_mode} " \
+		"${network_setting} " \
+		"root=${nandroot} " \
+		"rootfstype=${nandrootfstype} "\
+		"${extra_options}\0" \
+	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source ${loadaddr}\0" \
+	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nand read ${loadaddr} 280000 400000; " \
+		"bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"if mmc rescan ${mmcdev}; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loaduimage; then " \
+				"run mmcboot; " \
+			"else run nandboot; " \
+			"fi; " \
+		"fi; " \
+	"else run nandboot; fi"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT		"TAO-3530 # "
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+
+/* turn on command-line edit/hist/auto */
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_COMMAND_HISTORY
+#define CONFIG_AUTO_COMPLETE
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
+
+#define CONFIG_SYS_ALT_MEMTEST		1
+#define CONFIG_SYS_MEMTEST_START	(0x82000000)		/* memtest */
+								/* defaults */
+#define CONFIG_SYS_MEMTEST_END		(0x83FFFFFF)		/* 64MB */
+#define CONFIG_SYS_MEMTEST_SCRATCH	(0x81000000)	/* dummy address */
+
+#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)	/* default */
+							/* load address */
+#define CONFIG_SYS_TEXT_BASE		0x80008000
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
+#define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
+#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 MiB */
+#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
+
+/*
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+
+/* Configure the PISMO */
+#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
+#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
+#define CONFIG_SYS_FLASH_BASE		PISMO1_NAND_BASE
+
+/* Monitor at start of flash */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
+
+#define CONFIG_ENV_IS_IN_NAND		1
+#define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
+#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
+
+#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)
+#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
+#define CONFIG_ENV_ADDR			CONFIG_ENV_OFFSET
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE	0x800
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_OMAP3_SPI
+
+/*
+ * USB
+ *
+ * Currently only EHCI is enabled, the MUSB OTG controller
+ * is not enabled.
+ */
+
+/* USB EHCI */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_OMAP
+#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO	162
+
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_SMSC95XX
+
+#define CONFIG_USB_ETHER
+#define CONFIG_USB_ETHER_RNDIS
+#define CONFIG_USB_STORAGE
+#define CONGIG_CMD_STORAGE
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_NAND_SIMPLE
+
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
+
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_OMAP3_ID_NAND
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
+
+/* NAND boot config */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+/*
+ * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
+ * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
+ */
+#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
+					 10, 11, 12, 13 }
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW
+
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+
+#define CONFIG_SPL_TEXT_BASE		0x40200800
+#define CONFIG_SPL_MAX_SIZE		(54 * 1024)	/* 8 KB for stack */
+#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
+
+/*
+ * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
+ * older x-loader implementations. And move the BSS area so that it
+ * doesn't overlap with TEXT_BASE.
+ */
+#define CONFIG_SYS_TEXT_BASE		0x80008000
+#define CONFIG_SPL_BSS_START_ADDR	0x80100000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
+
+#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/taurus.h b/qemu/roms/u-boot/include/configs/taurus.h
new file mode 100644
index 000000000..20d4cee01
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/taurus.h
@@ -0,0 +1,159 @@
+/*
+ * Common board functions for Siemens TAURUS (AT91SAM9G20) based boards
+ * (C) Copyright 2013 Siemens AG
+ *
+ * Based on:
+ * U-Boot file: include/configs/at91sam9260ek.h
+ *
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * SoC must be defined first, before hardware.h is included.
+ * In this case SoC is defined in boards.cfg.
+ */
+#include <asm/hardware.h>
+
+#define MACH_TYPE_TAURUS		2067
+#define MACH_TYPE_AXM			2068
+
+/*
+ * Warning: changing CONFIG_SYS_TEXT_BASE requires
+ * adapting the initial boot program.
+ * Since the linker has to swallow that define, we must use a pure
+ * hex number here!
+ */
+
+
+#define CONFIG_SYS_TEXT_BASE		0x23f00000
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000	/* main clock xtal */
+
+/* Misc CPU related */
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_OF_LIBFDT
+
+/* general purpose I/O */
+#define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
+#define CONFIG_AT91_GPIO
+#define CONFIG_AT91_GPIO_PULLUP	1	/* keep pullups on peripheral pins */
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
+#define CONFIG_USART_ID			ATMEL_ID_SYS
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_SOURCE
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NAND
+
+/*
+ * SDRAM: 1 bank, min 32, max 128 MB
+ * Initialized before u-boot gets started.
+ */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
+#define CONFIG_SYS_SDRAM_SIZE		(128 * 1024 * 1024)
+
+/*
+ * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
+ * leaving the correct space for initial global data structure above
+ * that address while providing maximum stack area below.
+ */
+# define CONFIG_SYS_INIT_SP_ADDR \
+	(ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
+#define CONFIG_SYS_NAND_DBW_8
+#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
+#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIN_PC14
+#define CONFIG_SYS_NAND_READY_PIN	AT91_PIN_PC13
+#endif
+
+/* NOR flash - no real flash on this board */
+#define CONFIG_SYS_NO_FLASH			1
+
+/* Ethernet */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_AT91_WANTS_COMMON_PHY
+
+/* USB */
+#if defined(CONFIG_BOARD_TAURUS)
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00500000
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9260"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+#define CONFIG_USB_STORAGE
+#endif
+
+/* load address */
+#define CONFIG_SYS_LOAD_ADDR			0x22000000
+
+/* bootstrap in spi flash , u-boot + env + linux in nandflash */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		0x100000
+#define CONFIG_ENV_OFFSET_REDUND	0x180000
+#define CONFIG_ENV_SIZE		0x20000		/* 1 sector = 128 kB */
+#define CONFIG_BOOTCOMMAND	"nand read 0x22000000 0x200000 0x300000; bootm"
+#define CONFIG_BOOTARGS							\
+	"console=ttyS0,115200 earlyprintk "				\
+	"mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,"		\
+	"256k(env),256k(env_redundant),256k(spare),"			\
+	"512k(dtb),6M(kernel)ro,-(rootfs) "				\
+	"root=/dev/mtdblock7 rw rootfstype=jffs2"
+
+#define CONFIG_SYS_PROMPT		"U-Boot> "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_PBSIZE \
+	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN \
+	ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/tcm-bf518.h b/qemu/roms/u-boot/include/configs/tcm-bf518.h
new file mode 100644
index 000000000..a77ba697d
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/tcm-bf518.h
@@ -0,0 +1,126 @@
+/*
+ * U-boot - Configuration file for Bluetechnix TCM-BF518 board
+ */
+
+#ifndef __CONFIG_TCM_BF518_H__
+#define __CONFIG_TCM_BF518_H__
+
+#include <asm/config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU             bf518-0.0
+#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
+
+
+/*
+ * Clock Settings
+ *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz					*/
+#define CONFIG_CLKIN_HZ			25000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
+/*                                                1 = CLKIN / 2		*/
+#define CONFIG_CLKIN_HALF		0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
+/*                                                1 = bypass PLL	*/
+#define CONFIG_PLL_BYPASS		0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
+/* Values can range from 0-63 (where 0 means 64)			*/
+#define CONFIG_VCO_MULT			16
+/* CCLK_DIV controls the core clock divider				*/
+/* Values can be 1, 2, 4, or 8 ONLY					*/
+#define CONFIG_CCLK_DIV			1
+/* SCLK_DIV controls the system clock divider				*/
+/* Values can range from 1-15						*/
+#define CONFIG_SCLK_DIV			4
+
+
+/*
+ * Memory Settings
+ */
+/* This board has a 32meg MT48H16M16 */
+#define CONFIG_MEM_ADD_WDTH	9
+#define CONFIG_MEM_SIZE		32
+
+#define CONFIG_EBIU_SDRRC_VAL	0x3f8
+#define CONFIG_EBIU_SDGCTL_VAL	0x9111cd
+
+#define CONFIG_EBIU_AMGCTL_VAL	(AMBEN_ALL)
+#define CONFIG_EBIU_AMBCTL0_VAL	(B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
+#define CONFIG_EBIU_AMBCTL1_VAL	(B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
+
+#define CONFIG_SYS_MONITOR_LEN	(512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN	(384 * 1024)
+
+
+/*
+ * Network Settings
+ */
+#if !defined(__ADSPBF512__) && !defined(__ADSPBF514__)
+#define ADI_CMDS_NETWORK	1
+#define CONFIG_BFIN_MAC
+#define CONFIG_NETCONSOLE	1
+#endif
+#define CONFIG_HOSTNAME		tcm-bf518
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR	02:80:ad:20:31:e8 */
+#define CONFIG_LIB_RAND
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_BASE		0x20000000
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	19
+
+
+/*
+ * SPI Settings
+ */
+#define CONFIG_BFIN_SPI
+#define CONFIG_ENV_SPI_MAX_HZ	30000000
+#define CONFIG_SF_DEFAULT_SPEED	30000000
+
+
+/*
+ * Env Storage Settings
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OFFSET	0x8000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x8000
+#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
+
+
+/*
+ * I2C Settings
+ */
+#define CONFIG_BFIN_TWI_I2C	1
+#define CONFIG_HARD_I2C		1
+
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_MISC_INIT_R
+#define CONFIG_RTC_BFIN
+#define CONFIG_UART_CONSOLE	0
+#define CONFIG_BOOTCOMMAND	"run flashboot"
+#define FLASHBOOT_ENV_SETTINGS	"flashboot=bootm 0x20040000\0"
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/tcm-bf537.h b/qemu/roms/u-boot/include/configs/tcm-bf537.h
new file mode 100644
index 000000000..c4c1c579b
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/tcm-bf537.h
@@ -0,0 +1,156 @@
+/*
+ * U-boot - Configuration file for TCM-BF537 board
+ */
+
+#ifndef __CONFIG_TCM_BF537_H__
+#define __CONFIG_TCM_BF537_H__
+
+#include <asm/config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU             bf537-0.2
+#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
+
+
+/*
+ * Clock Settings
+ *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz					*/
+#define CONFIG_CLKIN_HZ			25000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
+/*                                                1 = CLKIN / 2		*/
+#define CONFIG_CLKIN_HALF		0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
+/*                                                1 = bypass PLL	*/
+#define CONFIG_PLL_BYPASS		0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
+/* Values can range from 0-63 (where 0 means 64)			*/
+#define CONFIG_VCO_MULT			21
+/* CCLK_DIV controls the core clock divider				*/
+/* Values can be 1, 2, 4, or 8 ONLY					*/
+#define CONFIG_CCLK_DIV			1
+/* SCLK_DIV controls the system clock divider				*/
+/* Values can range from 1-15						*/
+#define CONFIG_SCLK_DIV			4
+
+/* Decrease core voltage */
+#define CONFIG_VR_CTL_VAL (VLEV_115 | CLKBUFOE | GAIN_20 | FREQ_1000)
+
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_ADD_WDTH	9
+#define CONFIG_MEM_SIZE		32
+
+#define CONFIG_EBIU_SDRRC_VAL	0x3f8
+#define CONFIG_EBIU_SDGCTL_VAL	0x9111cd
+
+#define CONFIG_EBIU_AMGCTL_VAL	(AMBEN_ALL)
+#define CONFIG_EBIU_AMBCTL0_VAL	(B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
+#define CONFIG_EBIU_AMBCTL1_VAL	(B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
+
+#define CONFIG_SYS_MONITOR_LEN	(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN	(128 * 1024)
+
+
+/*
+ * Network Settings
+ */
+#ifndef __ADSPBF534__
+#define ADI_CMDS_NETWORK	1
+#define CONFIG_BFIN_MAC
+#define CONFIG_SMC911X		1
+#define CONFIG_SMC911X_BASE	0x20308000
+#define CONFIG_SMC911X_16_BIT
+#define CONFIG_NETCONSOLE	1
+#endif
+#define CONFIG_HOSTNAME		tcm-bf537
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR	02:80:ad:20:31:e8 */
+#define CONFIG_LIB_RAND
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define CONFIG_SYS_FLASH_BASE		0x20000000
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	67
+
+
+/*
+ * SPI Settings
+ */
+#define CONFIG_BFIN_SPI
+#define CONFIG_ENV_SPI_MAX_HZ	30000000
+
+
+/*
+ * Env Storage Settings
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_OFFSET	0x8000
+#define CONFIG_ENV_SIZE		0x8000
+#define CONFIG_ENV_SECT_SIZE	0x8000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
+#define ENV_IS_EMBEDDED
+#endif
+#ifdef ENV_IS_EMBEDDED
+/* WARNING - the following is hand-optimized to fit within
+ * the sector before the environment sector. If it throws
+ * an error during compilation remove an object here to get
+ * it linked after the configuration sector.
+ */
+# define LDS_BOARD_TEXT \
+	arch/blackfin/lib/built-in.o (.text*); \
+	arch/blackfin/cpu/built-in.o (.text*); \
+	. = DEFINED(env_offset) ? env_offset : .; \
+	common/env_embedded.o (.text*);
+#endif
+
+
+/*
+ * I2C Settings
+ */
+#define CONFIG_BFIN_TWI_I2C	1
+#define CONFIG_HARD_I2C		1
+
+
+/*
+ * SPI_MMC Settings
+ */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC_SPI
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_MISC_INIT_R
+#define CONFIG_RTC_BFIN
+#define CONFIG_UART_CONSOLE	0
+#define CONFIG_BOOTCOMMAND	"run flashboot"
+#define FLASHBOOT_ENV_SETTINGS \
+	"flashboot=flread 20040000 1000000 300000;" \
+	"bootm 0x1000000\0"
+#define CONFIG_BOARD_SIZE_LIMIT $$((384 * 1024))
+#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/tec-ng.h b/qemu/roms/u-boot/include/configs/tec-ng.h
new file mode 100644
index 000000000..13baa76f9
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/tec-ng.h
@@ -0,0 +1,84 @@
+/*
+ * (C) Copyright 2013
+ * Avionic Design GmbH <www.avionic-design.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "tegra30-common.h"
+
+/* Enable fdt support for tec-ng. Flash the image in u-boot-dtb.bin */
+#define CONFIG_DEFAULT_DEVICE_TREE	tegra30-tec-ng
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
+/* High-level configuration options */
+#define V_PROMPT			"Tegra30 (TEC-NG) # "
+#define CONFIG_TEGRA_BOARD_STRING	"Avionic Design Tamontenâ„¢ NG Evaluation Carrier"
+
+/* Board-specific serial config */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_TEGRA_ENABLE_UARTD
+#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* I2C */
+#define CONFIG_SYS_I2C_TEGRA
+#define CONFIG_SYS_I2C_INIT_BOARD
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_MAX_I2C_BUS		TEGRA_I2C_NUM_CONTROLLERS
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_TEGRA_MMC
+#define CONFIG_CMD_MMC
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART		2
+
+/* SPI */
+#define CONFIG_TEGRA20_SLINK
+#define CONFIG_TEGRA_SLINK_CTRLS       6
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SF_DEFAULT_MODE         SPI_MODE_0
+#define CONFIG_SF_DEFAULT_SPEED        24000000
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH_SIZE          (4 << 20)
+
+/* USB Host support */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_TEGRA
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB
+
+/* USB networking support */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_SMSC95XX
+
+/* General networking support */
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+
+/* Tag support */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+/* support the new (FDT-based) image format */
+#define CONFIG_FIT
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/tec.h b/qemu/roms/u-boot/include/configs/tec.h
new file mode 100644
index 000000000..90e7b7ad9
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/tec.h
@@ -0,0 +1,72 @@
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *  (C) Copyright 2011-2012
+ *  Avionic Design GmbH <www.avionic-design.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "tegra20-common.h"
+
+/* Enable fdt support for TEC. Flash the image in u-boot-dtb.bin */
+#define CONFIG_DEFAULT_DEVICE_TREE	tegra20-tec
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
+/* High-level configuration options */
+#define V_PROMPT			"Tegra20 (TEC) # "
+#define CONFIG_TEGRA_BOARD_STRING	"Avionic Design Tamonten Evaluation Carrier"
+
+/* Board-specific serial config */
+#define CONFIG_TEGRA_ENABLE_UARTD	/* UARTD: debug UART */
+#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_TEGRA_MMC
+#define CONFIG_CMD_MMC
+
+/* NAND support */
+#define CONFIG_CMD_NAND
+#define CONFIG_TEGRA_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+
+/* Environment in NAND, aligned to start of last sector */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		(SZ_512M - SZ_128K) /* 128K sectors */
+
+/* USB host support */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_TEGRA
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB
+
+/* USB networking support */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_SMSC95XX
+
+/* General networking support */
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+
+/* LCD support */
+#define CONFIG_LCD
+#define CONFIG_PWM_TEGRA
+#define CONFIG_VIDEO_TEGRA
+#define LCD_BPP LCD_COLOR16
+#define CONFIG_SYS_WHITE_ON_BLACK
+
+/* support the new (FDT-based) image format */
+#define CONFIG_FIT
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/tegra-common-post.h b/qemu/roms/u-boot/include/configs/tegra-common-post.h
new file mode 100644
index 000000000..76dad4e88
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/tegra-common-post.h
@@ -0,0 +1,267 @@
+/*
+ * (C) Copyright 2010-2012
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __TEGRA_COMMON_POST_H
+#define __TEGRA_COMMON_POST_H
+
+#ifdef CONFIG_BOOTCOMMAND
+
+#define BOOTCMDS_COMMON ""
+
+#else
+
+#ifdef CONFIG_CMD_MMC
+#define BOOTCMDS_MMC \
+	"mmc_boot=" \
+		"setenv devtype mmc; " \
+		"if mmc dev ${devnum}; then " \
+			"run scan_boot; " \
+		"fi\0" \
+	"bootcmd_mmc0=setenv devnum 0; run mmc_boot;\0" \
+	"bootcmd_mmc1=setenv devnum 1; run mmc_boot;\0"
+#define BOOT_TARGETS_MMC "mmc1 mmc0"
+#else
+#define BOOTCMDS_MMC ""
+#define BOOT_TARGETS_MMC ""
+#endif
+
+#ifdef CONFIG_CMD_USB
+#define BOOTCMD_INIT_USB "run usb_init; "
+#define BOOTCMDS_USB \
+	"usb_init=" \
+		"if ${usb_need_init}; then " \
+			"set usb_need_init false; " \
+			"usb start 0; " \
+		"fi\0" \
+	\
+	"usb_boot=" \
+		"setenv devtype usb; " \
+		BOOTCMD_INIT_USB \
+		"if usb dev ${devnum}; then " \
+			"run scan_boot; " \
+		"fi\0" \
+	\
+	"bootcmd_usb0=setenv devnum 0; run usb_boot;\0"
+#define BOOT_TARGETS_USB "usb0"
+#else
+#define BOOTCMD_INIT_USB ""
+#define BOOTCMDS_USB ""
+#define BOOT_TARGETS_USB ""
+#endif
+
+#ifdef CONFIG_CMD_DHCP
+#define BOOTCMDS_DHCP \
+	"bootcmd_dhcp=" \
+		BOOTCMD_INIT_USB \
+		"if dhcp ${scriptaddr} boot.scr.uimg; then "\
+			"source ${scriptaddr}; " \
+		"fi\0"
+#define BOOT_TARGETS_DHCP "dhcp"
+#else
+#define BOOTCMDS_DHCP ""
+#define BOOT_TARGETS_DHCP ""
+#endif
+
+#if defined(CONFIG_CMD_DHCP) && defined(CONFIG_CMD_PXE)
+#define BOOTCMDS_PXE \
+	"bootcmd_pxe=" \
+		BOOTCMD_INIT_USB \
+		"dhcp; " \
+		"if pxe get; then " \
+			"pxe boot; " \
+		"fi\0"
+#define BOOT_TARGETS_PXE "pxe"
+#else
+#define BOOTCMDS_PXE ""
+#define BOOT_TARGETS_PXE ""
+#endif
+
+#define BOOTCMDS_COMMON \
+	"rootpart=1\0" \
+	\
+	"do_script_boot="                                                 \
+		"load ${devtype} ${devnum}:${rootpart} "                  \
+			"${scriptaddr} ${prefix}${script}; "              \
+		"source ${scriptaddr}\0"                                  \
+	\
+	"script_boot="                                                    \
+		"for script in ${boot_scripts}; do "                      \
+			"if test -e ${devtype} ${devnum}:${rootpart} "    \
+					"${prefix}${script}; then "       \
+				"echo Found U-Boot script "               \
+					"${prefix}${script}; "            \
+				"run do_script_boot; "                    \
+				"echo SCRIPT FAILED: continuing...; "     \
+			"fi; "                                            \
+		"done\0"                                                  \
+	\
+	"do_sysboot_boot="                                                \
+		"sysboot ${devtype} ${devnum}:${rootpart} any "           \
+			"${scriptaddr} ${prefix}extlinux.conf\0"          \
+	\
+	"sysboot_boot="                                                   \
+		"if test -e ${devtype} ${devnum}:${rootpart} "            \
+				"${prefix}extlinux.conf; then "           \
+			"echo Found extlinux config "                     \
+				"${prefix}extlinux.conf; "                \
+			"run do_sysboot_boot; "                           \
+			"echo SCRIPT FAILED: continuing...; "             \
+		"fi\0"                                                    \
+	\
+	"scan_boot="                                                      \
+		"echo Scanning ${devtype} ${devnum}...; "                 \
+		"for prefix in ${boot_prefixes}; do "                     \
+			"run sysboot_boot; "                              \
+			"run script_boot; "                               \
+		"done\0"                                                  \
+	\
+	"boot_targets=" \
+		BOOT_TARGETS_MMC " " \
+		BOOT_TARGETS_USB " " \
+		BOOT_TARGETS_PXE " " \
+		BOOT_TARGETS_DHCP " " \
+		"\0" \
+	\
+	"boot_prefixes=/ /boot/\0" \
+	\
+	"boot_scripts=boot.scr.uimg boot.scr\0" \
+	\
+	BOOTCMDS_MMC \
+	BOOTCMDS_USB \
+	BOOTCMDS_DHCP \
+	BOOTCMDS_PXE
+
+#define CONFIG_BOOTCOMMAND \
+	"set usb_need_init; " \
+	"for target in ${boot_targets}; do run bootcmd_${target}; done"
+
+#endif
+
+#ifdef CONFIG_TEGRA_KEYBOARD
+#define STDIN_KBD_KBC ",tegra-kbc"
+#else
+#define STDIN_KBD_KBC ""
+#endif
+
+#ifdef CONFIG_USB_KEYBOARD
+#define STDIN_KBD_USB ",usbkbd"
+#define CONFIG_SYS_USB_EVENT_POLL
+#define CONFIG_PREBOOT			"usb start"
+#else
+#define STDIN_KBD_USB ""
+#endif
+
+#ifdef CONFIG_VIDEO_TEGRA
+#define STDOUT_LCD ",lcd"
+#else
+#define STDOUT_LCD ""
+#endif
+
+#define TEGRA_DEVICE_SETTINGS \
+	"stdin=serial" STDIN_KBD_KBC STDIN_KBD_USB "\0" \
+	"stdout=serial" STDOUT_LCD "\0" \
+	"stderr=serial" STDOUT_LCD "\0" \
+	""
+
+#ifndef BOARD_EXTRA_ENV_SETTINGS
+#define BOARD_EXTRA_ENV_SETTINGS
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	TEGRA_DEVICE_SETTINGS \
+	MEM_LAYOUT_ENV_SETTINGS \
+	BOOTCMDS_COMMON \
+	BOARD_EXTRA_ENV_SETTINGS
+
+#if defined(CONFIG_TEGRA20_SFLASH) || defined(CONFIG_TEGRA20_SLINK) || defined(CONFIG_TEGRA114_SPI)
+#define CONFIG_FDT_SPI
+#endif
+
+/* overrides for SPL build here */
+#ifdef CONFIG_SPL_BUILD
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* remove devicetree support */
+#ifdef CONFIG_OF_CONTROL
+#undef CONFIG_OF_CONTROL
+#endif
+
+/* remove I2C support */
+#ifdef CONFIG_SYS_I2C_TEGRA
+#undef CONFIG_SYS_I2C_TEGRA
+#endif
+#ifdef CONFIG_CMD_I2C
+#undef CONFIG_CMD_I2C
+#endif
+
+/* remove MMC support */
+#ifdef CONFIG_MMC
+#undef CONFIG_MMC
+#endif
+#ifdef CONFIG_GENERIC_MMC
+#undef CONFIG_GENERIC_MMC
+#endif
+#ifdef CONFIG_TEGRA_MMC
+#undef CONFIG_TEGRA_MMC
+#endif
+#ifdef CONFIG_CMD_MMC
+#undef CONFIG_CMD_MMC
+#endif
+
+/* remove partitions/filesystems */
+#ifdef CONFIG_DOS_PARTITION
+#undef CONFIG_DOS_PARTITION
+#endif
+#ifdef CONFIG_EFI_PARTITION
+#undef CONFIG_EFI_PARTITION
+#endif
+#ifdef CONFIG_CMD_FS_GENERIC
+#undef CONFIG_CMD_FS_GENERIC
+#endif
+#ifdef CONFIG_CMD_EXT4
+#undef CONFIG_CMD_EXT4
+#endif
+#ifdef CONFIG_CMD_EXT2
+#undef CONFIG_CMD_EXT2
+#endif
+#ifdef CONFIG_CMD_FAT
+#undef CONFIG_CMD_FAT
+#endif
+#ifdef CONFIG_FS_EXT4
+#undef CONFIG_FS_EXT4
+#endif
+#ifdef CONFIG_FS_FAT
+#undef CONFIG_FS_FAT
+#endif
+
+/* remove USB */
+#ifdef CONFIG_USB_EHCI
+#undef CONFIG_USB_EHCI
+#endif
+#ifdef CONFIG_USB_EHCI_TEGRA
+#undef CONFIG_USB_EHCI_TEGRA
+#endif
+#ifdef CONFIG_USB_STORAGE
+#undef CONFIG_USB_STORAGE
+#endif
+#ifdef CONFIG_CMD_USB
+#undef CONFIG_CMD_USB
+#endif
+
+/* remove part command support */
+#ifdef CONFIG_PARTITION_UUIDS
+#undef CONFIG_PARTITION_UUIDS
+#endif
+
+#ifdef CONFIG_CMD_PART
+#undef CONFIG_CMD_PART
+#endif
+
+#endif /* CONFIG_SPL_BUILD */
+
+#endif /* __TEGRA_COMMON_POST_H */
diff --git a/qemu/roms/u-boot/include/configs/tegra-common.h b/qemu/roms/u-boot/include/configs/tegra-common.h
new file mode 100644
index 000000000..ae786cfd7
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/tegra-common.h
@@ -0,0 +1,152 @@
+/*
+ *  (C) Copyright 2010-2012
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _TEGRA_COMMON_H_
+#define _TEGRA_COMMON_H_
+#include <linux/sizes.h>
+#include <linux/stringify.h>
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMCORTEXA9		/* This is an ARM V7 CPU core */
+#define CONFIG_TEGRA			/* which is a Tegra generic machine */
+#define CONFIG_SYS_L2CACHE_OFF		/* No L2 cache */
+
+#include <asm/arch/tegra.h>		/* get chip and board defs */
+
+#define CONFIG_SYS_TIMER_RATE		1000000
+#define CONFIG_SYS_TIMER_COUNTER	NV_PA_TMRUS_BASE
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+
+/* Environment */
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_ENV_SIZE			0x2000	/* Total Size Environment */
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(4 << 20)	/* 4MB  */
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX	1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE			115200
+
+/* include default commands */
+#include <config_cmd_default.h>
+
+/* remove unused commands */
+#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect */
+#undef CONFIG_CMD_FPGA		/* FPGA configuration support */
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_NFS		/* NFS support */
+#undef CONFIG_CMD_NET		/* network support */
+
+/* turn on command-line edit/hist/auto */
+#define CONFIG_COMMAND_HISTORY
+
+/* turn on commonly used storage-related commands */
+#define CONFIG_PARTITION_UUIDS
+#define CONFIG_CMD_PART
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_PROMPT		V_PROMPT
+/*
+ * Increasing the size of the IO buffer as default nfsargs size is more
+ *  than 256 and so it is not possible to edit it
+ */
+#define CONFIG_SYS_CBSIZE		(256 * 2) /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
+
+#define CONFIG_SYS_MEMTEST_START	(NV_PA_SDRC_CS0 + 0x600000)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x100000)
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM_1		NV_PA_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE	0x20000000	/* 512M */
+
+#define CONFIG_SYS_UBOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_1
+
+#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)	/* 256M */
+
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_STACKBASE
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_MALLOC_LEN
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+						CONFIG_SYS_INIT_RAM_SIZE - \
+						GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_TEGRA_GPIO
+#define CONFIG_CMD_GPIO
+#define CONFIG_CMD_ENTERRCM
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_RAM_DEVICE
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SPL_MAX_FOOTPRINT	(CONFIG_SYS_TEXT_BASE - \
+						CONFIG_SPL_TEXT_BASE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00010000
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+
+#ifdef CONFIG_SPL_BUILD
+# define CONFIG_USE_PRIVATE_LIBGCC
+#endif
+
+#define CONFIG_SYS_GENERIC_BOARD
+
+/* Misc utility code */
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_CRC32_VERIFY
+
+#ifndef CONFIG_SPL_BUILD
+#include <config_distro_defaults.h>
+#endif
+
+#endif /* _TEGRA_COMMON_H_ */
diff --git a/qemu/roms/u-boot/include/configs/tegra114-common.h b/qemu/roms/u-boot/include/configs/tegra114-common.h
new file mode 100644
index 000000000..555c237cb
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/tegra114-common.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA114_COMMON_H_
+#define _TEGRA114_COMMON_H_
+#include "tegra-common.h"
+
+/* Cortex-A15 uses a cache line size of 64 bytes */
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK		408000000	/* 408MHz (pllp_out0) */
+
+/* Environment information, boards can override if required */
+#define CONFIG_LOADADDR		0x80408000	/* def. location for kernel */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x80A00800	/* default */
+#define CONFIG_STACKBASE	0x82800000	/* 40MB */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_SYS_TEXT_BASE	0x8010E000
+
+/*
+ * Memory layout for where various images get loaded by boot scripts:
+ *
+ * scriptaddr can be pretty much anywhere that doesn't conflict with something
+ *   else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
+ * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
+ *   something else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
+ * kernel_addr_r must be within the first 128M of RAM in order for the
+ *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
+ *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
+ *   should not overlap that area, or the kernel will have to copy itself
+ *   somewhere else before decompression. Similarly, the address of any other
+ *   data passed to the kernel shouldn't overlap the start of RAM. Pushing
+ *   this up to 16M allows for a sizable kernel to be decompressed below the
+ *   compressed load address.
+ *
+ * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
+ *   the compressed kernel to be up to 16M too.
+ *
+ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
+ *   for the FDT/DTB to be up to 1M, which is hopefully plenty.
+ */
+#define MEM_LAYOUT_ENV_SETTINGS \
+	"scriptaddr=0x90000000\0" \
+	"pxefile_addr_r=0x90100000\0" \
+	"kernel_addr_r=0x81000000\0" \
+	"fdt_addr_r=0x82000000\0" \
+	"ramdisk_addr_r=0x82100000\0"
+
+/* Defines for SPL */
+#define CONFIG_SPL_TEXT_BASE		0x80108000
+#define CONFIG_SYS_SPL_MALLOC_START	0x80090000
+#define CONFIG_SPL_STACK		0x800ffffc
+
+/* Total I2C ports on Tegra114 */
+#define TEGRA_I2C_NUM_CONTROLLERS	5
+
+/* For USB EHCI controller */
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_EHCI_TXFIFO_THRESH	0x10
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
+
+#endif /* _TEGRA114_COMMON_H_ */
diff --git a/qemu/roms/u-boot/include/configs/tegra124-common.h b/qemu/roms/u-boot/include/configs/tegra124-common.h
new file mode 100644
index 000000000..61e502657
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/tegra124-common.h
@@ -0,0 +1,79 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _TEGRA124_COMMON_H_
+#define _TEGRA124_COMMON_H_
+
+#include "tegra-common.h"
+
+/* Cortex-A15 uses a cache line size of 64 bytes */
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK		408000000	/* 408MHz (pllp_out0) */
+
+/* Environment information, boards can override if required */
+#define CONFIG_LOADADDR		0x80408000	/* def. location for kernel */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x80A00800	/* default */
+#define CONFIG_STACKBASE	0x82800000	/* 40MB */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_SYS_TEXT_BASE	0x8010E000
+
+/*
+ * Memory layout for where various images get loaded by boot scripts:
+ *
+ * scriptaddr can be pretty much anywhere that doesn't conflict with something
+ *   else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
+ * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
+ *   something else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
+ * kernel_addr_r must be within the first 128M of RAM in order for the
+ *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
+ *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
+ *   should not overlap that area, or the kernel will have to copy itself
+ *   somewhere else before decompression. Similarly, the address of any other
+ *   data passed to the kernel shouldn't overlap the start of RAM. Pushing
+ *   this up to 16M allows for a sizable kernel to be decompressed below the
+ *   compressed load address.
+ *
+ * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
+ *   the compressed kernel to be up to 16M too.
+ *
+ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
+ *   for the FDT/DTB to be up to 1M, which is hopefully plenty.
+ */
+#define MEM_LAYOUT_ENV_SETTINGS \
+	"scriptaddr=0x90000000\0" \
+	"pxefile_addr_r=0x90100000\0" \
+	"kernel_addr_r=0x81000000\0" \
+	"fdt_addr_r=0x82000000\0" \
+	"ramdisk_addr_r=0x82100000\0"
+
+/* Defines for SPL */
+#define CONFIG_SPL_TEXT_BASE		0x80108000
+#define CONFIG_SYS_SPL_MALLOC_START	0x80090000
+#define CONFIG_SPL_STACK		0x800ffffc
+
+/* Total I2C ports on Tegra124 */
+#define TEGRA_I2C_NUM_CONTROLLERS	5
+
+/* For USB EHCI controller */
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_EHCI_TXFIFO_THRESH	0x10
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
+
+#endif /* _TEGRA124_COMMON_H_ */
diff --git a/qemu/roms/u-boot/include/configs/tegra20-common.h b/qemu/roms/u-boot/include/configs/tegra20-common.h
new file mode 100644
index 000000000..21bf97717
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/tegra20-common.h
@@ -0,0 +1,106 @@
+/*
+ *  (C) Copyright 2010-2012
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _TEGRA20_COMMON_H_
+#define _TEGRA20_COMMON_H_
+#include "tegra-common.h"
+
+/* Cortex-A9 uses a cache line size of 32 bytes */
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
+/*
+ * Errata configuration
+ */
+#define CONFIG_ARM_ERRATA_716044
+#define CONFIG_ARM_ERRATA_742230
+#define CONFIG_ARM_ERRATA_751472
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK		216000000	/* 216MHz (pllp_out0) */
+
+/* Environment information, boards can override if required */
+#define CONFIG_LOADADDR		0x00408000	/* def. location for kernel */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x00A00800	/* default */
+#define CONFIG_STACKBASE	0x02800000	/* 40MB */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_SYS_TEXT_BASE	0x0010E000
+
+/*
+ * Memory layout for where various images get loaded by boot scripts:
+ *
+ * scriptaddr can be pretty much anywhere that doesn't conflict with something
+ *   else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
+ * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
+ *   something else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
+ * kernel_addr_r must be within the first 128M of RAM in order for the
+ *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
+ *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
+ *   should not overlap that area, or the kernel will have to copy itself
+ *   somewhere else before decompression. Similarly, the address of any other
+ *   data passed to the kernel shouldn't overlap the start of RAM. Pushing
+ *   this up to 16M allows for a sizable kernel to be decompressed below the
+ *   compressed load address.
+ *
+ * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
+ *   the compressed kernel to be up to 16M too.
+ *
+ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
+ *   for the FDT/DTB to be up to 1M, which is hopefully plenty.
+ */
+#define MEM_LAYOUT_ENV_SETTINGS \
+	"scriptaddr=0x10000000\0" \
+	"pxefile_addr_r=0x10100000\0" \
+	"kernel_addr_r=0x01000000\0" \
+	"fdt_addr_r=0x02000000\0" \
+	"ramdisk_addr_r=0x02100000\0"
+
+/* Defines for SPL */
+#define CONFIG_SPL_TEXT_BASE		0x00108000
+#define CONFIG_SYS_SPL_MALLOC_START	0x00090000
+#define CONFIG_SPL_STACK		0x000ffffc
+
+/* Align LCD to 1MB boundary */
+#define CONFIG_LCD_ALIGNMENT	MMU_SECTION_SIZE
+
+#ifdef CONFIG_TEGRA_LP0
+#define TEGRA_LP0_ADDR			0x1C406000
+#define TEGRA_LP0_SIZE			0x2000
+#define TEGRA_LP0_VEC \
+	"lp0_vec=" __stringify(TEGRA_LP0_SIZE)  \
+	"@" __stringify(TEGRA_LP0_ADDR) " "
+#else
+#define TEGRA_LP0_VEC
+#endif
+
+/*
+ * This parameter affects a TXFILLTUNING field that controls how much data is
+ * sent to the latency fifo before it is sent to the wire. Without this
+ * parameter, the default (2) causes occasional Data Buffer Errors in OUT
+ * packets depending on the buffer address and size.
+ */
+#define CONFIG_USB_EHCI_TXFIFO_THRESH	10
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
+
+/* Total I2C ports on Tegra20 */
+#define TEGRA_I2C_NUM_CONTROLLERS	4
+
+#define CONFIG_SYS_NAND_SELF_INIT
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+#endif /* _TEGRA20_COMMON_H_ */
diff --git a/qemu/roms/u-boot/include/configs/tegra30-common.h b/qemu/roms/u-boot/include/configs/tegra30-common.h
new file mode 100644
index 000000000..443c84224
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/tegra30-common.h
@@ -0,0 +1,84 @@
+/*
+ *  (C) Copyright 2010-2012
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _TEGRA30_COMMON_H_
+#define _TEGRA30_COMMON_H_
+#include "tegra-common.h"
+
+/* Cortex-A9 uses a cache line size of 32 bytes */
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
+/*
+ * Errata configuration
+ */
+#define CONFIG_ARM_ERRATA_743622
+#define CONFIG_ARM_ERRATA_751472
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK		408000000	/* 408MHz (pllp_out0) */
+
+/* Environment information, boards can override if required */
+#define CONFIG_LOADADDR		0x80408000	/* def. location for kernel */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR	0x80A00800	/* default */
+#define CONFIG_STACKBASE	0x82800000	/* 40MB */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_SYS_TEXT_BASE	0x8010E000
+
+/*
+ * Memory layout for where various images get loaded by boot scripts:
+ *
+ * scriptaddr can be pretty much anywhere that doesn't conflict with something
+ *   else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
+ * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
+ *   something else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
+ * kernel_addr_r must be within the first 128M of RAM in order for the
+ *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
+ *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
+ *   should not overlap that area, or the kernel will have to copy itself
+ *   somewhere else before decompression. Similarly, the address of any other
+ *   data passed to the kernel shouldn't overlap the start of RAM. Pushing
+ *   this up to 16M allows for a sizable kernel to be decompressed below the
+ *   compressed load address.
+ *
+ * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
+ *   the compressed kernel to be up to 16M too.
+ *
+ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
+ *   for the FDT/DTB to be up to 1M, which is hopefully plenty.
+ */
+#define MEM_LAYOUT_ENV_SETTINGS \
+	"scriptaddr=0x90000000\0" \
+	"pxefile_addr_r=0x90100000\0" \
+	"kernel_addr_r=0x81000000\0" \
+	"fdt_addr_r=0x82000000\0" \
+	"ramdisk_addr_r=0x82100000\0"
+
+/* Defines for SPL */
+#define CONFIG_SPL_TEXT_BASE		0x80108000
+#define CONFIG_SYS_SPL_MALLOC_START	0x80090000
+#define CONFIG_SPL_STACK		0x800ffffc
+
+/* Total I2C ports on Tegra30 */
+#define TEGRA_I2C_NUM_CONTROLLERS	5
+
+/* For USB EHCI controller */
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_EHCI_TXFIFO_THRESH	0x10
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
+
+#endif /* _TEGRA30_COMMON_H_ */
diff --git a/qemu/roms/u-boot/include/configs/ti814x_evm.h b/qemu/roms/u-boot/include/configs/ti814x_evm.h
new file mode 100644
index 000000000..b51400c46
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/ti814x_evm.h
@@ -0,0 +1,239 @@
+/*
+ * ti814x_evm.h
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __CONFIG_TI814X_EVM_H
+#define __CONFIG_TI814X_EVM_H
+
+#define CONFIG_TI81XX
+#define CONFIG_TI814X
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_OMAP
+#define CONFIG_OMAP_COMMON
+
+#include <asm/arch/omap.h>
+
+#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
+#define CONFIG_SYS_MALLOC_LEN		(1024 << 10)
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* Use HUSH for command parsing */
+#define CONFIG_SYS_PROMPT		"U-Boot# "
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_MACH_TYPE		MACH_TYPE_TI8148EVM
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs  */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG		/* for ramdisk support */
+
+/* commands to include */
+# include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_VERSION_VARIABLE
+
+#define CONFIG_BOOTDELAY		1	/* negative for no autoboot */
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x80200000\0" \
+	"fdtaddr=0x80F80000\0" \
+	"rdaddr=0x81000000\0" \
+	"bootfile=/boot/uImage\0" \
+	"fdtfile=\0" \
+	"console=ttyO0,115200n8\0" \
+	"optargs=\0" \
+	"mmcdev=0\0" \
+	"mmcroot=/dev/mmcblk0p2 ro\0" \
+	"mmcrootfstype=ext4 rootwait\0" \
+	"ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \
+	"ramrootfstype=ext2\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0" \
+	"bootenv=uEnv.txt\0" \
+	"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
+	"importbootenv=echo Importing environment from mmc ...; " \
+		"env import -t $loadaddr $filesize\0" \
+	"ramargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${ramroot} " \
+		"rootfstype=${ramrootfstype}\0" \
+	"loadramdisk=fatload mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
+	"loaduimagefat=fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \
+	"loaduimage=ext2load mmc ${mmcdev}:2 ${loadaddr} ${bootfile}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0" \
+	"ramboot=echo Booting from ramdisk ...; " \
+		"run ramargs; " \
+		"bootm ${loadaddr}\0" \
+	"fdtfile=ti814x-evm.dtb\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"echo SD/MMC found on device ${mmcdev};" \
+		"if run loadbootenv; then " \
+			"echo Loaded environment from ${bootenv};" \
+			"run importbootenv;" \
+		"fi;" \
+		"if test -n $uenvcmd; then " \
+			"echo Running uenvcmd ...;" \
+			"run uenvcmd;" \
+		"fi;" \
+		"if run loaduimage; then " \
+			"run mmcboot;" \
+		"fi;" \
+	"fi;" \
+
+/* Clock Defines */
+#define V_OSCK			24000000	/* Clock output from T2 */
+#define V_SCLK			(V_OSCK >> 1)
+
+#define CONFIG_CMD_ECHO
+
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS		16
+
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		512
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE \
+					+ sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START \
+					+ PHYS_DRAM_1_SIZE - (8 << 12))
+
+#define CONFIG_SYS_LOAD_ADDR		0x81000000	/* Default */
+
+#define CONFIG_OMAP_GPIO
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_CMD_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+
+/**
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS		1		/* 1 banks of DRAM */
+#define PHYS_DRAM_1_SIZE		0x20000000	/* 512MB */
+#define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 20)	/* 1024MB */
+
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CONFIG_SYS_INIT_SP_ADDR		(NON_SECURE_SRAM_END - \
+					 GENERATED_GBL_DATA_SIZE)
+
+/**
+ * Platform/Board specific defs
+ */
+#define CONFIG_SYS_TIMERBASE		0x4802E000
+#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		(48000000)
+#define CONFIG_SYS_NS16550_COM1		0x48020000	/* Base EVM has UART0 */
+
+#define CONFIG_BAUDRATE			115200
+
+/* CPU */
+#define CONFIG_ARCH_CPU_INIT
+
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+
+#define CONFIG_ENV_IS_NOWHERE
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE		0x40300000
+#define CONFIG_SPL_MAX_SIZE		((128 - 18) * 1024)
+#define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
+
+#define CONFIG_SPL_BSS_START_ADDR	0x80000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
+
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS      0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION    1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME        "u-boot.img"
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_YMODEM_SUPPORT
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x20000
+#define CONFIG_SYS_SPI_U_BOOT_SIZE	0x40000
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
+
+#define CONFIG_SPL_BOARD_INIT
+
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80800000 should not be used for any
+ * other needs.
+ */
+#define CONFIG_SYS_TEXT_BASE		0x80800000
+#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
+
+/*
+ * Since SPL did pll and ddr initialization for us,
+ * we don't need to do it twice.
+ */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+/* Unsupported features */
+#undef CONFIG_USE_IRQ
+
+/* Ethernet */
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MII
+#define CONFIG_DRIVER_TI_CPSW
+#define CONFIG_MII
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_NET_RETRY_COUNT         10
+#define CONFIG_NET_MULTI
+#define CONFIG_PHY_GIGE
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ET1011C
+#define CONFIG_PHY_ET1011C_TX_CLK_FIX
+
+#endif	/* ! __CONFIG_TI814X_EVM_H */
diff --git a/qemu/roms/u-boot/include/configs/ti816x_evm.h b/qemu/roms/u-boot/include/configs/ti816x_evm.h
new file mode 100644
index 000000000..b8c0d54ab
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/ti816x_evm.h
@@ -0,0 +1,179 @@
+/*
+ * ti816x_evm.h
+ *
+ * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
+ * Antoine Tenart, <atenart@adeneo-embedded.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_TI816X_EVM_H
+#define __CONFIG_TI816X_EVM_H
+
+#define CONFIG_TI81XX
+#define CONFIG_TI816X
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_OMAP
+#define CONFIG_OMAP_COMMON
+
+#define CONFIG_ARCH_CPU_INIT
+
+#include <asm/arch/omap.h>
+
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (32 * 1024))
+#define CONFIG_SYS_LONGHELP		/* undef save memory */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT		"u-boot/ti816x# "
+#define CONFIG_MACH_TYPE		MACH_TYPE_TI8168EVM
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG		/* required for ramdisk support */
+
+#include <config_cmd_default.h>		/* u-boot default commands */
+
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_BOOTDELAY		3 /* set negative for no autoboot */
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"loadaddr=0x81000000\0"		\
+
+#define CONFIG_BOOTCOMMAND			\
+	"mmc rescan;"				\
+	"fatload mmc 0 ${loadaddr} uImage;"	\
+	"bootm ${loadaddr}"			\
+
+#define CONFIG_BOOTARGS	"console=ttyO2,115200n8 noinitrd earlyprintk"
+
+/* Clock Defines */
+#define V_OSCK          24000000    /* Clock output from T2 */
+#define V_SCLK          (V_OSCK >> 1)
+
+#define CONFIG_SYS_MAXARGS	32
+#define CONFIG_SYS_CBSIZE	512 /* console I/O buffer size */
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE \
+		+ sizeof(CONFIG_SYS_PROMPT) + 16) /* print buffer size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* boot arg buffer size */
+
+#undef  CONFIG_SYS_CLKS_IN_HZ
+#define CONFIG_SYS_LOAD_ADDR		0x81000000 /* Default load address */
+
+#define CONFIG_CMD_ASKEN
+#define CONFIG_CMD_ECHO
+#define CONFIG_OMAP_GPIO
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_CMD_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+
+#define CONFIG_FS_FAT
+
+/*
+ * Only one of the following two options (DDR3/DDR2) should be enabled
+ * CONFIG_TI816X_EVM_DDR2
+ * CONFIG_TI816X_EVM_DDR3
+ */
+#define CONFIG_TI816X_EVM_DDR3
+
+/*
+ * Supported values: 400, 531, 675 or 796 MHz
+ */
+#define CONFIG_TI816X_DDR_PLL_796
+
+#define CONFIG_TI816X_USE_EMIF0	1
+#define CONFIG_TI816X_USE_EMIF1	1
+
+
+#define CONFIG_NR_DRAM_BANKS	2		/* we have 2 banks of DRAM */
+#define PHYS_DRAM_1		0x80000000	/* DRAM Bank #1 */
+#define PHYS_DRAM_1_SIZE        0x40000000	/* 1 GB */
+#define PHYS_DRAM_2		0xC0000000	/* DRAM Bank #2 */
+#define PHYS_DRAM_2_SIZE	0x40000000	/* 1 GB */
+
+#define CONFIG_MAX_RAM_BANK_SIZE	(2048 << 20)	/* 2048MB */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_DRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR		(NON_SECURE_SRAM_END - \
+		GENERATED_GBL_DATA_SIZE)
+
+/**
+ * Platform/Board specific defs
+ */
+#define CONFIG_SYS_CLK_FREQ     27000000
+#define CONFIG_SYS_TIMERBASE    0x4802E000
+#define CONFIG_SYS_PTV          2   /* Divisor: 2^(PTV+1) => 8 */
+
+#undef CONFIG_NAND_OMAP_GPMC
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK      (48000000)
+#define CONFIG_SYS_NS16550_COM1     0x48024000  /* Base EVM has UART2 */
+
+#define CONFIG_BAUDRATE     115200
+
+/* allow overwriting serial config and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_SERIAL1
+#define CONFIG_SERIAL2
+#define CONFIG_SERIAL3
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+
+#define CONFIG_ENV_IS_NOWHERE
+
+/* SPL */
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE    0x40400000
+#define CONFIG_SPL_MAX_SIZE     ((128 - 18) * 1024)
+#define CONFIG_SPL_STACK        CONFIG_SYS_INIT_SP_ADDR
+
+#define CONFIG_SPL_BSS_START_ADDR   0x80000000
+#define CONFIG_SPL_BSS_MAX_SIZE     0x80000     /* 512 KB */
+
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS      0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION    1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME        "u-boot.img"
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_YMODEM_SUPPORT
+#define CONFIG_SYS_SPI_U_BOOT_OFFS  0x20000
+#define CONFIG_SYS_SPI_U_BOOT_SIZE  0x40000
+#define CONFIG_SPL_LDSCRIPT     "$(CPUDIR)/omap-common/u-boot-spl.lds"
+
+#define CONFIG_SPL_BOARD_INIT
+
+#define CONFIG_SYS_TEXT_BASE        0x80800000
+#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE  0x100000
+
+/* Since SPL did pll and ddr initialization for us,
+ * we don't need to do it twice.
+ */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+/* Unsupported features */
+#undef CONFIG_USE_IRQ
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/ti_am335x_common.h b/qemu/roms/u-boot/include/configs/ti_am335x_common.h
new file mode 100644
index 000000000..128b66ede
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/ti_am335x_common.h
@@ -0,0 +1,85 @@
+/*
+ * ti_am335x_common.h
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * For more details, please see the technical documents listed at
+ * http://www.ti.com/product/am3359#technicaldocuments
+ */
+
+#ifndef __CONFIG_TI_AM335X_COMMON_H__
+#define __CONFIG_TI_AM335X_COMMON_H__
+
+#define CONFIG_AM33XX
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_SYS_CACHELINE_SIZE       64
+#define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 20)	/* 1GB */
+#define CONFIG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
+#define CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
+
+#include <asm/arch/omap.h>
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		48000000
+
+/* Network defines. */
+#define CONFIG_CMD_NET			/* 'bootp' and 'tftp' */
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_BOOTP_DNS		/* Configurable parts of CMD_DHCP */
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_NET_RETRY_COUNT         10
+#define CONFIG_CMD_PING
+#define CONFIG_DRIVER_TI_CPSW		/* Driver for IP block */
+#define CONFIG_MII			/* Required in net/eth.c */
+
+/*
+ * RTC related defines. To use bootcount you must set bootlimit in the
+ * environment to a non-zero value and enable CONFIG_BOOTCOUNT_LIMIT
+ * in the board config.
+ */
+#define CONFIG_SYS_BOOTCOUNT_ADDR	0x44E3E000
+
+/* Enable the HW watchdog, since we can use this with bootcount */
+#define CONFIG_HW_WATCHDOG
+#define CONFIG_OMAP_WATCHDOG
+
+/*
+ * SPL related defines.  The Public RAM memory map the ROM defines the
+ * area between 0x402F0400 and 0x4030B800 as a download area and
+ * 0x4030B800 to 0x4030CE00 as a public stack area.  The ROM also
+ * supports X-MODEM loading via UART, and we leverage this and then use
+ * Y-MODEM to load u-boot.img, when booted over UART.
+ */
+#define CONFIG_SPL_TEXT_BASE		0x402F0400
+#define CONFIG_SPL_MAX_SIZE		(0x4030B800 - CONFIG_SPL_TEXT_BASE)
+#define CONFIG_SYS_SPL_ARGS_ADDR	(CONFIG_SYS_SDRAM_BASE + \
+					 (128 << 20))
+
+/* Enable the watchdog inside of SPL */
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+
+/*
+ * Since SPL did pll and ddr initialization for us,
+ * we don't need to do it twice.
+ */
+#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+#ifdef CONFIG_NAND
+#define CONFIG_SPL_NAND_AM33XX_BCH	/* ELM support */
+#endif
+
+/* Now bring in the rest of the common code. */
+#include <configs/ti_armv7_common.h>
+
+#endif	/* __CONFIG_TI_AM335X_COMMON_H__ */
diff --git a/qemu/roms/u-boot/include/configs/ti_armv7_common.h b/qemu/roms/u-boot/include/configs/ti_armv7_common.h
new file mode 100644
index 000000000..485427276
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/ti_armv7_common.h
@@ -0,0 +1,281 @@
+/*
+ * ti_armv7_common.h
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * The various ARMv7 SoCs from TI all share a number of IP blocks when
+ * implementing a given feature.  Rather than define these in every
+ * board or even SoC common file, we define a common file to be re-used
+ * in all cases.  While technically true that some of these details are
+ * configurable at the board design, they are common throughout SoC
+ * reference platforms as well as custom designs and become de facto
+ * standards.
+ */
+
+#ifndef __CONFIG_TI_ARMV7_COMMON_H__
+#define __CONFIG_TI_ARMV7_COMMON_H__
+
+/* Common define for many platforms. */
+#define CONFIG_OMAP
+#define CONFIG_OMAP_COMMON
+#define CONFIG_SYS_GENERIC_BOARD
+
+/*
+ * We typically do not contain NOR flash.  In the cases where we do, we
+ * undefine this later.
+ */
+#define CONFIG_SYS_NO_FLASH
+
+/* Support both device trees and ATAGs. */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/*
+ * Our DDR memory always starts at 0x80000000 and U-Boot shall have
+ * relocated itself to higher in memory by the time this value is used.
+ * However, set this to a 32MB offset to allow for easier Linux kernel
+ * booting as the default is often used as the kernel load address.
+ */
+#define CONFIG_SYS_LOAD_ADDR		0x82000000
+
+/*
+ * We setup defaults based on constraints from the Linux kernel, which should
+ * also be safe elsewhere.  We have the default load at 32MB into DDR (for
+ * the kernel), FDT above 128MB (the maximum location for the end of the
+ * kernel), and the ramdisk 512KB above that (allowing for hopefully never
+ * seen large trees).  We say all of this must be within the first 256MB
+ * as that will normally be within the kernel lowmem and thus visible via
+ * bootm_size and we only run on platforms with 256MB or more of memory.
+ */
+#define DEFAULT_LINUX_BOOT_ENV \
+	"loadaddr=0x82000000\0" \
+	"kernel_addr_r=0x82000000\0" \
+	"fdtaddr=0x88000000\0" \
+	"fdt_addr_r=0x88000000\0" \
+	"rdaddr=0x88080000\0" \
+	"ramdisk_addr_r=0x88080000\0" \
+	"bootm_size=0x10000000\0"
+
+/*
+ * Default to a quick boot delay.
+ */
+#define CONFIG_BOOTDELAY		1
+
+/*
+ * DDR information.  If the CONFIG_NR_DRAM_BANKS is not defined,
+ * we say (for simplicity) that we have 1 bank, always, even when
+ * we have more.  We always start at 0x80000000, and we place the
+ * initial stack pointer in our SRAM. Otherwise, we can define
+ * CONFIG_NR_DRAM_BANKS before including this file.
+ */
+#ifndef CONFIG_NR_DRAM_BANKS
+#define CONFIG_NR_DRAM_BANKS		1
+#endif
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CONFIG_SYS_INIT_SP_ADDR         (NON_SECURE_SRAM_END - \
+						GENERATED_GBL_DATA_SIZE)
+
+/* Timer information. */
+#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
+
+/* I2C IP block */
+#define CONFIG_I2C
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
+#define CONFIG_SYS_I2C_OMAP24XX
+
+/* MMC/SD IP block */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_CMD_MMC
+
+/* McSPI IP block */
+#define CONFIG_SPI
+#define CONFIG_OMAP3_SPI
+#define CONFIG_CMD_SPI
+
+/* GPIO block */
+#define CONFIG_OMAP_GPIO
+#define CONFIG_CMD_GPIO
+
+/*
+ * GPMC NAND block.  We support 1 device and the physical address to
+ * access CS0 at is 0x8000000.
+ */
+#ifdef CONFIG_NAND
+#define CONFIG_NAND_OMAP_GPMC
+#ifndef CONFIG_SYS_NAND_BASE
+#define CONFIG_SYS_NAND_BASE		0x8000000
+#endif
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_CMD_NAND
+#endif
+
+/*
+ * The following are general good-enough settings for U-Boot.  We set a
+ * large malloc pool as we generally have a lot of DDR, and we opt for
+ * function over binary size in the main portion of U-Boot as this is
+ * generally easily constrained later if needed.  We enable the config
+ * options that give us information in the environment about what board
+ * we are on so we do not need to rely on the command prompt.  We set a
+ * console baudrate of 115200 and use the default baud rate table.
+ */
+#define CONFIG_SYS_MALLOC_LEN		(1024 << 10)
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT		"U-Boot# "
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_ENV_VARS_UBOOT_CONFIG	/* Strongly encouraged */
+#define CONFIG_ENV_OVERWRITE		/* Overwrite ethaddr / serial# */
+
+/* As stated above, the following choices are optional. */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_VERSION_VARIABLE
+
+/* We set the max number of command args high to avoid HUSH bugs. */
+#define CONFIG_SYS_MAXARGS		64
+
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		512
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE \
+					+ sizeof(CONFIG_SYS_PROMPT) + 16)
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+/*
+ * When we have SPI, NOR or NAND flash we expect to be making use of
+ * mtdparts, both for ease of use in U-Boot and for passing information
+ * on to the Linux kernel.
+ */
+#if defined(CONFIG_SPI_BOOT) || defined(CONFIG_NOR) || defined(CONFIG_NAND)
+#define CONFIG_MTD_DEVICE		/* Required for mtdparts */
+#define CONFIG_CMD_MTDPARTS
+#endif
+
+/*
+ * For commands to use, we take the default list and add a few other
+ * useful commands.  Note that we must have set CONFIG_SYS_NO_FLASH
+ * prior to this include, in order to skip a few commands.  When we do
+ * have flash, if we expect these commands they must be enabled in that
+ * config.  If desired, a specific list of desired commands can be used
+ * instead.
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_BOOTZ
+
+/*
+ * Common filesystems support.  When we have removable storage we
+ * enabled a number of useful commands and support.
+ */
+#if defined(CONFIG_MMC) || defined(CONFIG_USB_STORAGE)
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_FAT
+#define CONFIG_FAT_WRITE
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_FS_GENERIC
+#endif
+
+/*
+ * Our platforms make use of SPL to initalize the hardware (primarily
+ * memory) enough for full U-Boot to be loaded.  We also support Falcon
+ * Mode so that the Linux kernel can be booted directly from SPL
+ * instead, if desired.  We make use of the general SPL framework found
+ * under common/spl/.  Given our generally common memory map, we set a
+ * number of related defaults and sizes here.
+ */
+#ifndef CONFIG_NOR_BOOT
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_OS_BOOT
+
+/*
+ * Place the image at the start of the ROM defined image space.
+ * We limit our size to the ROM-defined downloaded image area, and use the
+ * rest of the space for stack.  We load U-Boot itself into memory at
+ * 0x80800000 for legacy reasons (to not conflict with older SPLs).  We
+ * have our BSS be placed 1MiB after this, to allow for the default
+ * Linux kernel address of 0x80008000 to work, in the Falcon Mode case.
+ * We have the SPL malloc pool at the end of the BSS area.
+ */
+#define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE		0x80800000
+#endif
+#ifndef CONFIG_SPL_BSS_START_ADDR
+#define CONFIG_SPL_BSS_START_ADDR	0x80a00000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
+#endif
+#ifndef CONFIG_SYS_SPL_MALLOC_START
+#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SPL_BSS_START_ADDR + \
+					 CONFIG_SPL_BSS_MAX_SIZE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE	CONFIG_SYS_MALLOC_LEN
+#endif
+
+/* RAW SD card / eMMC locations. */
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
+
+/* FAT sd card locations. */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
+
+#ifdef CONFIG_SPL_OS_BOOT
+/* FAT */
+#define CONFIG_SPL_FAT_LOAD_KERNEL_NAME		"uImage"
+#define CONFIG_SPL_FAT_LOAD_ARGS_NAME		"args"
+
+/* RAW SD card / eMMC */
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0x900	/* address 0x120000 */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0x80	/* address 0x10000 */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	0x80	/* 64KiB */
+
+/* NAND */
+#ifdef CONFIG_NAND
+#define CONFIG_CMD_SPL_NAND_OFS			0x240000 /* end of u-boot */
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS		0x280000
+#define CONFIG_CMD_SPL_WRITE_SIZE		0x2000
+#endif
+
+/* spl export command */
+#define CONFIG_CMD_SPL
+#endif
+
+#ifdef CONFIG_MMC
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#endif
+
+/* General parts of the framework, required. */
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_BOARD_INIT
+
+#ifdef CONFIG_NAND
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SPL_MTD_SUPPORT
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+#endif
+#endif /* !CONFIG_NOR_BOOT */
+
+#endif	/* __CONFIG_TI_ARMV7_COMMON_H__ */
diff --git a/qemu/roms/u-boot/include/configs/ti_omap3_common.h b/qemu/roms/u-boot/include/configs/ti_omap3_common.h
new file mode 100644
index 000000000..ade35d295
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/ti_omap3_common.h
@@ -0,0 +1,77 @@
+/*
+ * ti_omap3_common.h
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * For more details, please see the technical documents listed at
+ *   http://www.ti.com/product/omap3530
+ *   http://www.ti.com/product/omap3630
+ *   http://www.ti.com/product/dm3730
+ */
+
+#ifndef __CONFIG_TI_OMAP3_COMMON_H__
+#define __CONFIG_TI_OMAP3_COMMON_H__
+
+#define CONFIG_OMAP34XX
+
+#include <asm/arch/cpu.h>
+#include <asm/arch/omap3.h>
+
+/* The chip has SDRC controller */
+#define CONFIG_SDRC
+
+/* Clock Defines */
+#define V_OSCK			26000000	/* Clock output from T2 */
+#define V_SCLK			(V_OSCK >> 1)
+
+/* NS16550 Configuration */
+#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600, \
+					115200}
+
+/* Select serial console configuration */
+#define CONFIG_CONS_INDEX		3
+#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
+#define CONFIG_SERIAL3			3
+
+/* Physical Memory Map */
+#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)
+
+/* TWL4030 */
+#define CONFIG_TWL4030_POWER		1
+
+/* SPL */
+#define CONFIG_SPL_TEXT_BASE		0x40200800
+#define CONFIG_SPL_MAX_SIZE		(54 * 1024)
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SYS_SPL_ARGS_ADDR	(CONFIG_SYS_SDRAM_BASE + \
+					 (64 << 20))
+
+
+#ifdef CONFIG_NAND
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SYS_NAND_BASE		0x30000000
+#endif
+
+/* Now bring in the rest of the common code. */
+#include <configs/ti_armv7_common.h>
+
+#endif	/* __CONFIG_TI_OMAP3_COMMON_H__ */
diff --git a/qemu/roms/u-boot/include/configs/ti_omap4_common.h b/qemu/roms/u-boot/include/configs/ti_omap4_common.h
new file mode 100644
index 000000000..77fbfb641
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/ti_omap4_common.h
@@ -0,0 +1,172 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated.
+ * Aneesh V       <aneesh@ti.com>
+ * Steve Sakoman  <steve@sakoman.com>
+ *
+ * TI OMAP4 common configuration settings
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_TI_OMAP4_COMMON_H
+#define __CONFIG_TI_OMAP4_COMMON_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_OMAP44XX		1	/* which is a 44XX */
+#define CONFIG_OMAP4430		1	/* which is in a 4430 */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO		1
+#define CONFIG_DISPLAY_BOARDINFO	1
+
+#define CONFIG_SYS_THUMB_BUILD
+
+#ifndef CONFIG_SYS_L2CACHE_OFF
+#define CONFIG_SYS_L2_PL310		1
+#define CONFIG_SYS_PL310_BASE	0x48242000
+#endif
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
+/* Get CPU defs */
+#include <asm/arch/cpu.h>
+#include <asm/arch/omap.h>
+
+/* Use General purpose timer 1 */
+#define CONFIG_SYS_TIMERBASE		GPT2_BASE
+
+/*
+ * Total Size Environment - 128k
+ */
+#define CONFIG_ENV_SIZE			(128 << 10)
+
+/*
+ * For the DDR timing information we can either dynamically determine
+ * the timings to use or use pre-determined timings (based on using the
+ * dynamic method.  Default to the static timing infomation.
+ */
+#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
+#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
+#endif
+
+#include <configs/ti_armv7_common.h>
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		48000000
+#define CONFIG_CONS_INDEX		3
+#define CONFIG_SYS_NS16550_COM3		UART3_BASE
+
+/* TWL6030 */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_TWL6030_POWER		1
+#endif
+
+/* USB */
+#define CONFIG_MUSB_UDC			1
+#define CONFIG_USB_OMAP3		1
+
+/* USB device configuration */
+#define CONFIG_USB_DEVICE		1
+#define CONFIG_USB_TTY			1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
+
+/* Per-Soc commands */
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+
+/*
+ * Environment setup
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	DEFAULT_LINUX_BOOT_ENV \
+	"console=ttyO2,115200n8\0" \
+	"fdtfile=undefined\0" \
+	"bootpart=0:2\0" \
+	"bootdir=/boot\0" \
+	"bootfile=zImage\0" \
+	"usbtty=cdc_acm\0" \
+	"vram=16M\0" \
+	"mmcdev=0\0" \
+	"mmcroot=/dev/mmcblk0p2 rw\0" \
+	"mmcrootfstype=ext3 rootwait\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"vram=${vram} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0" \
+	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
+		"source ${loadaddr}\0" \
+	"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
+	"importbootenv=echo Importing environment from mmc${mmcdev} ...; " \
+		"env import -t ${loadaddr} ${filesize}\0" \
+	"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
+	"mmcboot=echo Booting from mmc${mmcdev} ...; " \
+		"run mmcargs; " \
+		"bootz ${loadaddr} - ${fdtaddr}\0" \
+	"findfdt="\
+		"if test $board_name = sdp4430; then " \
+			"setenv fdtfile omap4-sdp.dtb; fi; " \
+		"if test $board_name = panda; then " \
+			"setenv fdtfile omap4-panda.dtb; fi;" \
+		"if test $board_name = panda-a4; then " \
+			"setenv fdtfile omap4-panda-a4.dtb; fi;" \
+		"if test $board_name = panda-es; then " \
+			"setenv fdtfile omap4-panda-es.dtb; fi;" \
+		"if test $fdtfile = undefined; then " \
+			"echo WARNING: Could not determine device tree to use; fi; \0" \
+	"loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"run findfdt; " \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"echo SD/MMC found on device ${mmcdev};" \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loadbootenv; then " \
+				"run importbootenv; " \
+			"fi;" \
+			"if test -n ${uenvcmd}; then " \
+				"echo Running uenvcmd ...;" \
+				"run uenvcmd;" \
+			"fi;" \
+		"fi;" \
+		"if run loadimage; then " \
+			"run loadfdt;" \
+			"run mmcboot; " \
+		"fi; " \
+	"fi"
+
+/*
+ * Defines for SPL
+ * It is known that this will break HS devices. Since the current size of
+ * SPL is overlapped with public stack and breaking non HS devices to boot.
+ * So moving TEXT_BASE down to non-HS limit.
+ */
+#define CONFIG_SPL_TEXT_BASE		0x40300000
+#define CONFIG_SPL_MAX_SIZE		(0x4030C000 - CONFIG_SPL_TEXT_BASE)
+#define CONFIG_SPL_DISPLAY_PRINT
+#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
+#define CONFIG_SYS_SPL_ARGS_ADDR	(CONFIG_SYS_SDRAM_BASE + \
+					 (128 << 20))
+
+#ifdef CONFIG_NAND
+#define CONFIG_SPL_NAND_AM33XX_BCH	/* ELM support */
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+/* No need for i2c in SPL mode as we will use SRI2C for PMIC access on OMAP4 */
+#undef CONFIG_SYS_I2C
+#undef CONFIG_SYS_I2C_OMAP24XX
+#endif
+
+#endif /* __CONFIG_TI_OMAP4_COMMON_H */
diff --git a/qemu/roms/u-boot/include/configs/ti_omap5_common.h b/qemu/roms/u-boot/include/configs/ti_omap5_common.h
new file mode 100644
index 000000000..a582fa404
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/ti_omap5_common.h
@@ -0,0 +1,150 @@
+/*
+ * (C) Copyright 2013
+ * Texas Instruments Incorporated.
+ * Sricharan R	  <r.sricharan@ti.com>
+ *
+ * Derived from OMAP4 done by:
+ *	Aneesh V <aneesh@ti.com>
+ *
+ * TI OMAP5 AND DRA7XX common configuration settings
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * For more details, please see the technical documents listed at
+ * http://www.ti.com/product/omap5432
+ */
+
+#ifndef __CONFIG_TI_OMAP5_COMMON_H
+#define __CONFIG_TI_OMAP5_COMMON_H
+
+#define CONFIG_OMAP54XX
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_MISC_INIT_R
+#define CONFIG_ARCH_CPU_INIT
+
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
+/* Use General purpose timer 1 */
+#define CONFIG_SYS_TIMERBASE		GPT2_BASE
+
+/*
+ * For the DDR timing information we can either dynamically determine
+ * the timings to use or use pre-determined timings (based on using the
+ * dynamic method.  Default to the static timing infomation.
+ */
+#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
+#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
+#endif
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_PALMAS_POWER
+#endif
+
+#include <asm/arch/cpu.h>
+#include <asm/arch/omap.h>
+
+#include <configs/ti_armv7_common.h>
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		48000000
+
+/* Per-SoC commands */
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+
+/*
+ * Environment setup
+ */
+#ifndef PARTS_DEFAULT
+#define PARTS_DEFAULT
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	DEFAULT_LINUX_BOOT_ENV \
+	"console=" CONSOLEDEV ",115200n8\0" \
+	"fdtfile=undefined\0" \
+	"bootpart=0:2\0" \
+	"bootdir=/boot\0" \
+	"bootfile=zImage\0" \
+	"usbtty=cdc_acm\0" \
+	"vram=16M\0" \
+	"partitions=" PARTS_DEFAULT "\0" \
+	"optargs=\0" \
+	"mmcdev=0\0" \
+	"mmcroot=/dev/mmcblk1p2 rw\0" \
+	"mmcrootfstype=ext4 rootwait\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"vram=${vram} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0" \
+	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
+		"source ${loadaddr}\0" \
+	"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
+	"importbootenv=echo Importing environment from mmc${mmcdev} ...; " \
+		"env import -t ${loadaddr} ${filesize}\0" \
+	"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
+	"mmcboot=mmc dev ${mmcdev}; " \
+		"if mmc rescan; then " \
+			"echo SD/MMC found on device ${mmcdev};" \
+			"if run loadbootenv; then " \
+				"echo Loaded environment from ${bootenv};" \
+				"run importbootenv;" \
+			"fi;" \
+			"if test -n $uenvcmd; then " \
+				"echo Running uenvcmd ...;" \
+				"run uenvcmd;" \
+			"fi;" \
+			"if run loadimage; then " \
+				"run loadfdt; " \
+				"echo Booting from mmc${mmcdev} ...; " \
+				"run mmcargs; " \
+				"bootz ${loadaddr} - ${fdtaddr}; " \
+			"fi;" \
+		"fi;\0" \
+	"findfdt="\
+		"if test $board_name = omap5_uevm; then " \
+			"setenv fdtfile omap5-uevm.dtb; fi; " \
+		"if test $board_name = dra7xx; then " \
+			"setenv fdtfile dra7-evm.dtb; fi;" \
+		"if test $fdtfile = undefined; then " \
+			"echo WARNING: Could not determine device tree to use; fi; \0" \
+	"loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile};\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"run findfdt; " \
+	"run mmcboot;" \
+	"setenv mmcdev 1; " \
+	"setenv bootpart 1:2; " \
+	"setenv mmcroot /dev/mmcblk0p2 rw; " \
+	"run mmcboot;" \
+
+
+/*
+ * SPL related defines.  The Public RAM memory map the ROM defines the
+ * area between 0x40300000 and 0x4031E000 as a download area for OMAP5
+ * (dra7xx is larger, but we do not need to be larger at this time).  We
+ * set CONFIG_SPL_DISPLAY_PRINT to have omap_rev_string() called and
+ * print some information.
+ */
+#define CONFIG_SPL_TEXT_BASE		0x40300000
+#define CONFIG_SPL_MAX_SIZE		(0x4031E000 - CONFIG_SPL_TEXT_BASE)
+#define CONFIG_SPL_DISPLAY_PRINT
+#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
+#define CONFIG_SYS_SPL_ARGS_ADDR	(CONFIG_SYS_SDRAM_BASE + \
+					 (128 << 20))
+
+#ifdef CONFIG_NAND
+#define CONFIG_SPL_NAND_AM33XX_BCH	/* ELM support */
+#endif
+
+#endif /* __CONFIG_TI_OMAP5_COMMON_H */
diff --git a/qemu/roms/u-boot/include/configs/titanium.h b/qemu/roms/u-boot/include/configs/titanium.h
new file mode 100644
index 000000000..f9e00c5b8
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/titanium.h
@@ -0,0 +1,269 @@
+/*
+ * Copyright (C) 2013 Stefan Roese <sr@denx.de>
+ *
+ * Configuration settings for the ProjectionDesign / Barco
+ * Titanium board.
+ *
+ * Based on mx6qsabrelite.h which is:
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/gpio.h>
+
+#define CONFIG_MX6
+#define CONFIG_MX6Q
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define MACH_TYPE_TITANIUM		3769
+#define CONFIG_MACH_TYPE		MACH_TYPE_TITANIUM
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(2 * 1024 * 1024)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MISC_INIT_R
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART1_BASE
+
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_SPEED		100000
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_USDHC_NUM	1
+
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE		RGMII
+#define CONFIG_FEC_MXC_PHYADDR		4
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9021
+
+/* USB Configs */
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_FAT
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_MXC_USB_PORT	1
+#define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS	0
+
+/* Miscellaneous commands */
+#define CONFIG_CMD_BMODE
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+
+/* Command definition */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY		3
+
+#define CONFIG_LOADADDR			0x12000000
+#define CONFIG_SYS_TEXT_BASE		0x17800000
+
+#define CONFIG_SYS_MEMTEST_START	0x10000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (500 << 20))
+
+#define CONFIG_HOSTNAME			titanium
+#define CONFIG_UBI_PART			ubi
+#define CONFIG_UBIFS_VOLUME		rootfs0
+
+#define MTDIDS_DEFAULT		"nand0=gpmi-nand"
+#define MTDPARTS_DEFAULT	"mtdparts=gpmi-nand:16M(uboot),512k(env1)," \
+				"512k(env2),-(ubi)"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"kernel=" __stringify(CONFIG_HOSTNAME) "/uImage\0"		\
+	"kernel_fs=/boot/uImage\0"					\
+	"kernel_addr=11000000\0"					\
+	"dtb=" __stringify(CONFIG_HOSTNAME) "/"				\
+		__stringify(CONFIG_HOSTNAME) ".dtb\0"			\
+	"dtb_fs=/boot/" __stringify(CONFIG_HOSTNAME) ".dtb\0"		\
+	"dtb_addr=12800000\0"						\
+	"script=boot.scr\0" \
+	"uimage=uImage\0" \
+	"console=ttymxc0\0" \
+	"baudrate=115200\0" \
+	"fdt_high=0xffffffff\0"	  \
+	"initrd_high=0xffffffff\0" \
+	"mmcdev=0\0" \
+	"mmcpart=1\0" \
+	"uimage=uImage\0" \
+	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}" \
+		" ${script}\0" \
+	"bootscript=echo Running bootscript from mmc ...; source\0" \
+	"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+	"mmcroot=/dev/mmcblk0p2\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot} rootwait rw\0" \
+	"bootmmc=run mmcargs; fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}" \
+		" ${uimage}; bootm\0" \
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addcon=setenv bootargs ${bootargs} console=ttymxc0,"		\
+		"${baudrate}\0"						\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
+	"rootpath=/opt/eldk-5.3/armv7a/rootfs-minimal-mtdutils\0"	\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ubifs=" __stringify(CONFIG_HOSTNAME) "/ubifs.img\0"		\
+	"part=" __stringify(CONFIG_UBI_PART) "\0"			\
+	"boot_vol=0\0"							\
+	"vol=" __stringify(CONFIG_UBIFS_VOLUME) "\0"			\
+	"load_ubifs=tftp ${kernel_addr} ${ubifs}\0"			\
+	"update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}"	\
+		" ${filesize}\0"					\
+	"upd_ubifs=run load_ubifs update_ubifs\0"			\
+	"init_ubi=nand erase.part ubi;ubi part ${part};"		\
+		"ubi create ${vol} c800000\0"				\
+	"mtdids=" MTDIDS_DEFAULT "\0"					\
+	"mtdparts=" MTDPARTS_DEFAULT "\0"				\
+	"nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip"		\
+		" addcon addmtd;"					\
+		"bootm ${kernel_addr} - ${dtb_addr}\0"			\
+	"ubifsargs=set bootargs ubi.mtd=ubi "				\
+		"root=ubi:rootfs${boot_vol} rootfstype=ubifs\0"		\
+	"ubifs_mount=ubi part ubi;ubifsmount ubi:rootfs${boot_vol}\0"	\
+	"ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};"		\
+		"ubifsload ${dtb_addr} ${dtb_fs};\0"			\
+	"nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon "	\
+		"addmtd;bootm ${kernel_addr} - ${dtb_addr}\0"		\
+	"load_kernel=tftp ${kernel_addr} ${kernel}\0"			\
+	"load_dtb=tftp ${dtb_addr} ${dtb}\0"				\
+	"net_nfs=run load_dtb load_kernel; "				\
+		"run nfsargs addip addcon addmtd;"			\
+		"bootm ${kernel_addr} - ${dtb_addr}\0"			\
+	"delenv=env default -a -f; saveenv; reset\0"
+
+#define CONFIG_BOOTCOMMAND		"run nand_ubifs"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT		"Titanium > "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	/* don't print console @ startup */
+
+#define CONFIG_SYS_CBSIZE		256
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					 sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+#define PHYS_SDRAM_SIZE			(512 << 20)
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+/* Enable NAND support */
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NAND_TRIMFFS
+#define CONFIG_CMD_TIME
+
+#ifdef CONFIG_CMD_NAND
+
+/* NAND stuff */
+#define CONFIG_NAND_MXS
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* DMA stuff, needed for GPMI/MXS NAND support */
+#define CONFIG_APBH_DMA
+#define CONFIG_APBH_DMA_BURST
+#define CONFIG_APBH_DMA_BURST8
+
+/* Environment in NAND */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		(16 << 20)
+#define CONFIG_ENV_SECT_SIZE		(128 << 10)
+#define CONFIG_ENV_SIZE			CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + (512 << 10))
+#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
+
+#else /* CONFIG_CMD_NAND */
+
+/* Environment in MMC */
+#define CONFIG_ENV_SIZE			(8 << 10)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET		(6 * 64 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+
+#endif /* CONFIG_CMD_NAND */
+
+/* UBI/UBIFS config options */
+#define CONFIG_LZO
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_RBTREE
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+#endif
+
+#endif			       /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/tk71.h b/qemu/roms/u-boot/include/configs/tk71.h
new file mode 100644
index 000000000..16e8a7f2b
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/tk71.h
@@ -0,0 +1,114 @@
+/*
+ * Copyright (C) 2012 Marek Vasut <marex@denx.de>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_TK71_H__
+#define __CONFIG_TK71_H__
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING	"\nKa-Ro TK71"
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_FEROCEON_88FR131	1	/* CPU Core subversion */
+#define CONFIG_KIRKWOOD		1	/* SOC Family Name */
+#define CONFIG_KW88F6281	1	/* SOC Name */
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+#define CONFIG_NR_DRAM_BANKS	1
+
+#define MACH_TYPE_TK71		2399
+#define CONFIG_MACH_TYPE	MACH_TYPE_TK71
+
+/*
+ * Commands configuration
+ */
+#define	CONFIG_SYS_HUSH_PARSER
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SUPPORT_VFAT
+
+#include <config_cmd_default.h>
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/*
+ * NAND flash
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_JFFS2_NAND
+#define CONFIG_JFFS2_DEV		"nand0,3"
+#endif
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE_PORTS	{1, 0}
+#define CONFIG_PHY_BASE_ADR	0x08
+#endif
+
+/*
+ * USB/EHCI
+ */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_KIRKWOOD
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_STORAGE
+#endif
+
+/*
+ *  Environment variables configurations
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SECT_SIZE		0x20000
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+#define CONFIG_ENV_SIZE			0x20000
+#define CONFIG_ENV_ADDR			0x80000
+#define CONFIG_ENV_OFFSET		0x80000
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_BOOTCOMMAND "nand read 0x800000 kernel 0x300000; bootm;"
+#define CONFIG_MTDPARTS 	"512K(u-boot),512K(u-boot-env),3M(kernel),-(root)"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"update_uboot=dhcp u-boot.kwb; nand erase.part u-boot; nand write ${fileaddr} u-boot ${filesize}\0" \
+	"update_kernel=dhcp uImage-tk71; nand erase.part kernel; nand write ${fileaddr} kernel ${filesize} \0" \
+	"update_rootfs=dhcp rootfs-tk71; nand erase.part root; nand write ${fileaddr} root ${filesize}\0" \
+	"update_all=run update_uboot; run update_kernel; run update_rootfs; reset\0" \
+	"mtdids=nand0=orion_nand\0" \
+	"mtdparts=mtdparts=orion_nand:"CONFIG_MTDPARTS"\0" \
+	"bootargs=console=ttyS0,115200 mtdparts=orion_nand:"CONFIG_MTDPARTS" rootfstype=jffs2 root=/dev/mtdblock3 rw\0"
+#define MTDIDS_DEFAULT			"nand0=orion_nand"
+#define MTDPARTS_DEFAULT		"mtdparts=orion_nand:"CONFIG_MTDPARTS
+
+#define PHYS_SDRAM_1		0x00000000	/* Base address */
+#define PHYS_SDRAM_1_SIZE	0x20000000	/* Max 512 MB RAM */
+
+#endif	/* __CONFIG_TK71_H__ */
diff --git a/qemu/roms/u-boot/include/configs/tnetv107x_evm.h b/qemu/roms/u-boot/include/configs/tnetv107x_evm.h
new file mode 100644
index 000000000..162826f7d
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/tnetv107x_evm.h
@@ -0,0 +1,140 @@
+/*
+ * Copyright (C) 2008 Texas Instruments, Inc <www.ti.com>
+ *
+ * Based on davinci_dvevm.h. Original Copyrights follow:
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/clock.h>
+
+/* Architecture, CPU, etc */
+#define CONFIG_ARM1176
+#define CONFIG_TNETV107X
+#define CONFIG_TNETV107X_EVM
+#define CONFIG_TNETV107X_WATCHDOG
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_SYS_UBOOT_BASE		CONFIG_SYS_TEXT_BASE
+#define CONFIG_DISABLE_TCM
+#define CONFIG_PERIPORT_REMAP
+#define CONFIG_PERIPORT_BASE		0x2000000
+#define CONFIG_PERIPORT_SIZE		0x10
+#define CONFIG_SYS_CLK_FREQ		clk_get_rate(TNETV107X_LPSC_ARM)
+
+#define CONFIG_SYS_TIMERBASE		TNETV107X_TIMER0_BASE
+#define CONFIG_SYS_HZ_CLOCK		clk_get_rate(TNETV107X_LPSC_TIMER0)
+
+#define CONFIG_PLL_SYS_EXT_FREQ		25000000
+#define CONFIG_PLL_TDM_EXT_FREQ		19200000
+#define CONFIG_PLL_ETH_EXT_FREQ		25000000
+
+/* Memory Info */
+#define CONFIG_SYS_MALLOC_LEN		(0x10000 + 1*1024*1024)
+#define PHYS_SDRAM_1			TNETV107X_DDR_EMIF_DATA_BASE
+#define PHYS_SDRAM_1_SIZE		0x04000000
+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
+#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_1 + 16*1024*1024)
+#define CONFIG_NR_DRAM_BANKS		1
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+
+/* Serial Driver Info */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#define CONFIG_SYS_NS16550_COM1		TNETV107X_UART1_BASE
+#define CONFIG_SYS_NS16550_CLK		clk_get_rate(TNETV107X_LPSC_UART1)
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+
+/* Flash and environment info */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_NAND_DAVINCI
+#define CONFIG_ENV_SIZE			(SZ_128K)
+#define CONFIG_SYS_NAND_HW_ECC
+#define CONFIG_SYS_NAND_1BIT_ECC
+#define CONFIG_SYS_NAND_CS		2
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_BASE		TNETV107X_ASYNC_EMIF_DATA_CE0_BASE
+#define CONFIG_SYS_NAND_MASK_CLE		0x10
+#define CONFIG_SYS_NAND_MASK_ALE		0x8
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_JFFS2_NAND
+#define CONFIG_ENV_OFFSET		0x180000
+
+/*
+ * davinci_nand is a bit of a misnomer since this particular EMIF block is
+ * commonly used across multiple TI devices.  Unfortunately, this misnomer
+ * (amongst others) carries forward into the kernel too.  Consequently, if we
+ * use a different device name here, the mtdparts variable won't be usable as
+ * a kernel command-line argument.
+ */
+#define MTDIDS_DEFAULT			"nand0=davinci_nand.0"
+#define MTDPARTS_DEFAULT		"mtdparts=davinci_nand.0:"	\
+						"1536k(uboot)ro,"	\
+						"128k(params)ro,"	\
+						"4m(kernel),"		\
+						"-(filesystem)"
+
+/* General U-Boot configuration */
+#define CONFIG_BOOTFILE			"uImage"
+#define CONFIG_SYS_PROMPT		"U-Boot > "
+#define CONFIG_SYS_CBSIZE		1024
+#define CONFIG_SYS_MAXARGS		64
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE +		\
+					 sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_MEMTEST_START +	\
+					 0x700000)
+#define LINUX_BOOT_PARAM_ADDR		(CONFIG_SYS_MEMTEST_START + 0x100)
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_BOOTARGS			"mem=32M console=ttyS1,115200n8 " \
+					"root=/dev/mmcblk0p1 rw noinitrd"
+#define CONFIG_BOOTCOMMAND		""
+#define CONFIG_BOOTDELAY		1
+
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_CONSOLE
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_EDITENV
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_ITEST
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_SOURCE
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_JFFS2
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/tny_a9260.h b/qemu/roms/u-boot/include/configs/tny_a9260.h
new file mode 100644
index 000000000..32f6b00bb
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/tny_a9260.h
@@ -0,0 +1,151 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * Copyright (C) 2009
+ * Albin Tonnerre, Free Electrons <albin.tonnerre@free-electrons.com>
+ *
+ * Configuation settings for the Calao TNY-A9260 and TNY-A9G20 boards
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * SoC must be defined first, before hardware.h is included.
+ * In this case SoC is defined in boards.cfg.
+ */
+#include <asm/hardware.h>
+
+#if defined(CONFIG_TNY_A9260_NANDFLASH) || defined(CONFIG_TNY_A9G20_NANDFLASH)
+#define CONFIG_ENV_IS_IN_NAND
+#else
+#define CONFIG_ENV_IS_IN_EEPROM
+#endif
+
+/* Define actual evaluation board type from used processor type */
+#ifdef CONFIG_AT91SAM9G20
+# define CONFIG_TNY_A9G20
+# define MACH_TYPE_TNY_A9G20		2059
+# define CONFIG_MACH_TYPE		MACH_TYPE_TNY_A9G20
+#else
+# define CONFIG_TNY_A9260
+# define MACH_TYPE_TNY_A9260		2058
+# define CONFIG_MACH_TYPE		MACH_TYPE_TNY_A9260
+#endif
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	12000000	/* 12 MHz crystal */
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_CMDLINE_TAG	        /* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_ATMEL_LEGACY
+#define CONFIG_AT91_GPIO
+
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
+#define	CONFIG_USART_ID			ATMEL_ID_SYS
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_SOURCE
+#undef CONFIG_CMD_USB
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
+#define CONFIG_SYS_SDRAM_SIZE		0x04000000	/* 64 megs */
+# define CONFIG_SYS_INIT_SP_ADDR \
+	(ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+/* SPI EEPROM */
+#define CONFIG_SPI
+#define CONFIG_CMD_SPI
+#define CONFIG_ATMEL_SPI
+#define CONFIG_SYS_SPI_WRITE_TOUT		(5 * CONFIG_SYS_HZ)
+
+#define CONFIG_CMD_EEPROM
+#define CONFIG_SPI_M95XXX
+#define CONFIG_SYS_EEPROM_SIZE 0x10000
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
+
+/* NAND flash */
+#define CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE		1
+#define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3
+#define CONFIG_SYS_NAND_DBW_8
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PC14
+#define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PC13
+
+/* NOR flash - no real flash on this board */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_FAT
+
+#define CONFIG_SYS_LOAD_ADDR			0x22000000	/* load address */
+
+#define CONFIG_SYS_MEMTEST_START		CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END			0x23e00000
+
+/* Env in EEPROM, bootstrap + u-boot in NAND*/
+#ifdef CONFIG_ENV_IS_IN_EEPROM
+#define CONFIG_ENV_OFFSET		0x20
+#define CONFIG_ENV_SIZE		        0x1000
+#endif
+
+/* Env, bootstrap and u-boot in NAND */
+#ifdef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET               0x60000
+#define CONFIG_ENV_OFFSET_REDUND        0x80000
+#define CONFIG_ENV_SIZE                 0x20000
+#endif
+
+#define CONFIG_BOOTCOMMAND	"nboot 0x21000000 0 400000"
+#define CONFIG_BOOTARGS		"console=ttyS0,115200 " \
+				"root=/dev/mtdblock1 " \
+				"mtdparts=atmel_nand:16M(kernel)ro," \
+				"120M(rootfs),-(other) " \
+				"rw rootfstype=jffs2"
+
+#define CONFIG_SYS_PROMPT	"U-Boot> "
+#define CONFIG_SYS_CBSIZE	256
+#define CONFIG_SYS_MAXARGS	16
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN	ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/top9000.h b/qemu/roms/u-boot/include/configs/top9000.h
new file mode 100644
index 000000000..a96a9cb41
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/top9000.h
@@ -0,0 +1,290 @@
+/*
+ * (C) Copyright 2010
+ * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
+ *
+ * Configuation settings for the TOP9000 CPU module with AT91SAM9XE.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/*
+ * top9000 with at91sam9xe256 or at91sam9xe512
+ *
+ * Initial Bootloader is in embedded flash.
+ * Vital Product Data, U-Boot Environment are in I2C-EEPROM.
+ * U-Boot is in embedded flash, a backup U-Boot can be in NAND flash.
+ * kernel and file system are either in NAND flash or on a micro SD card.
+ * NAND flash is optional.
+ * I2C EEPROM is never optional.
+ * SPI FRAM is optional.
+ * SPI ENC28J60 is optional.
+ * 16 or 32 bit wide SDRAM.
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* SoC must be defined first, before hardware.h is included */
+#define CONFIG_AT91SAM9XE
+#include <asm/hardware.h>
+
+/*
+ * Warning: changing CONFIG_SYS_TEXT_BASE requires
+ * adapting the initial boot program.
+ */
+#define CONFIG_SYS_TEXT_BASE		0x20000000	/* start of SDRAM */
+
+/* Command line configuration */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
+#define CONFIG_CMD_ASKENV
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_PBSIZE \
+	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_PROMPT		"TOP9000> "
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_CACHE
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000	/* main clock xtal */
+
+/* Misc CPU related */
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_AT91RESET_EXTRST		/* assert external reset */
+
+/* general purpose I/O */
+#define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
+#define CONFIG_AT91_GPIO
+#define CONFIG_AT91_GPIO_PULLUP	1	/* keep pullups on peripheral pins */
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
+#define	CONFIG_USART_ID			ATMEL_ID_SYS
+#define CONFIG_BAUDRATE			115200
+
+/* SD/MMC card */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_GENERIC_ATMEL_MCI
+#define CONFIG_SYS_MMC_CD_PIN		AT91_PIN_PC9
+#define CONFIG_CMD_MMC
+
+/* Ethernet */
+#define CONFIG_MACB
+#define CONFIG_SYS_PHY_ID	1
+#define CONFIG_RMII
+#define CONFIG_NET_RETRY_COUNT	20
+
+/* real time clock */
+#define CONFIG_RTC_AT91SAM9_RTT
+#define CONFIG_CMD_DATE
+
+#if defined(CONFIG_AT91SAM9XE)
+/*
+ * NOR flash - use embedded flash of SAM9XE256/512
+ * U-Boot will not fit into 128K !
+ * 2010.09 will not fit into 256K with all options enabled !
+ *
+ * Layout:
+ * 16kB	1st Bootloader
+ * Rest U-Boot
+ * the first sector (16kB) of EFLASH cannot be unprotected
+ * with u-boot commands
+ */
+# define CONFIG_AT91_EFLASH
+# define CONFIG_SYS_FLASH_BASE		ATMEL_BASE_FLASH
+# define CONFIG_SYS_MAX_FLASH_SECT	32
+# define CONFIG_SYS_MAX_FLASH_BANKS	1
+# define CONFIG_SYS_FLASH_PROTECTION
+# define CONFIG_EFLASH_PROTSECTORS	1	/* protect first sector */
+#endif
+
+/* SPI */
+#define CONFIG_ATMEL_SPI
+#define CONFIG_CMD_SPI
+
+/* RAMTRON FRAM */
+#define CONFIG_CMD_SF
+#define CONFIG_ATMEL_SPI0		/* SPI used for FRAM is SPI0 */
+#define FRAM_SPI_BUS		0
+#define FRAM_CS_NUM		0
+#define CONFIG_SPI_FRAM_RAMTRON
+#define CONFIG_SF_DEFAULT_SPEED	1000000	/* be conservative here... */
+#define CONFIG_SF_DEFAULT_MODE	SPI_MODE_0
+#define CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC	"FM25H20"
+
+/* Microchip ENC28J60 (second LAN) */
+#if defined(CONFIG_EVAL9000)
+# define CONFIG_ENC28J60
+# define CONFIG_ATMEL_SPI1		/* SPI used for ENC28J60 is SPI1 */
+# define ENC_SPI_BUS		1
+# define ENC_CS_NUM		0
+# define ENC_SPI_CLOCK	1000000
+#endif /* CONFIG_EVAL9000 */
+
+/*
+ * SDRAM: 1 bank, min 32, max 128 MB
+ * Initialized before u-boot gets started.
+ */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
+#define CONFIG_SYS_SDRAM_SIZE		0x08000000
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x01e00000)
+#define CONFIG_SYS_LOAD_ADDR \
+	(CONFIG_SYS_SDRAM_BASE + 0x01000000)
+/*
+ * Initial stack pointer: 16k - GENERATED_GBL_DATA_SIZE in internal SRAM,
+ * leaving the correct space for initial global data structure above
+ * that address while providing maximum stack area below.
+ */
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(ATMEL_BASE_SRAM + 0x4000 - GENERATED_GBL_DATA_SIZE)
+
+/*
+ * NAND flash: 256 MB (optional)
+ *
+ * Layout:
+ * 640kB: u-boot (includes space for spare sectors, handled by
+ * initial loader)
+ * 2MB: kernel
+ * rest: file system
+ */
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
+#define CONFIG_SYS_NAND_DBW_8
+#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
+#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIN_PC14
+#define CONFIG_SYS_NAND_READY_PIN	AT91_PIN_PC13
+#define CONFIG_CMD_NAND
+
+/* USB */
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE	ATMEL_UHP_BASE
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"top9000"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB
+
+/* I2C support must always be enabled */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED	400000
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0x7F
+
+#define I2C0_PORT			AT91_PIO_PORTA
+#define SDA0_PIN			23
+#define SCL0_PIN			24
+#define I2C1_PORT			AT91_PIO_PORTB
+#define SDA1_PIN			12
+#define SCL1_PIN			13
+#define I2C_SOFT_DECLARATIONS		void iic_init(void);\
+					int iic_read(void);\
+					void iic_sda(int);\
+					void iic_scl(int);
+#define I2C_ACTIVE
+#define I2C_TRISTATE
+#define I2C_INIT			iic_init()
+#define I2C_READ			iic_read()
+#define I2C_SDA(bit)			iic_sda(bit)
+#define I2C_SCL(bit)			iic_scl(bit)
+#define I2C_DELAY			udelay(3)
+/* EEPROM configuration */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+#define CONFIG_SYS_EEPROM_SIZE		0x2000
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+/* later: #define CONFIG_I2C_ENV_EEPROM_BUS	0 */
+/* ENV is always in I2C-EEPROM */
+#define CONFIG_ENV_IS_IN_EEPROM
+#define CONFIG_ENV_OFFSET		0x1000
+#define CONFIG_ENV_SIZE			0x0f00
+/* VPD settings */
+#define CONFIG_SYS_I2C_FACT_ADDR	0x57
+#define CONFIG_SYS_FACT_OFFSET		0x1F00
+#define CONFIG_SYS_FACT_SIZE		0x0100
+/* later: #define CONFIG_MISC_INIT_R */
+/* define the next only if you want to allow users to enter VPD data */
+#define CONFIG_SYS_FACT_ENTRY
+#ifndef __ASSEMBLY__
+extern void read_factory_r(void);
+#endif
+
+/*
+ * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
+ * data on the serial line may interrupt the boot sequence.
+ */
+#define CONFIG_BOOTDELAY		1
+#define CONFIG_AUTOBOOT
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT \
+	"Press SPACE to abort autoboot in %d seconds\n", bootdelay
+#define CONFIG_AUTOBOOT_DELAY_STR	"d"
+#define CONFIG_AUTOBOOT_STOP_STR	" "
+
+/*
+ * add filesystem commands if we have at least 1 storage
+ * media with filesystem
+ */
+#if defined(CONFIG_NAND_ATMEL) \
+	|| defined(CONFIG_USB_ATMEL) \
+	|| defined(CONFIG_MMC)
+# define CONFIG_DOS_PARTITION
+# define CONFIG_CMD_FAT
+# define CONFIG_CMD_EXT2
+/* later: #define CONFIG_CMD_JFFS2 */
+#endif
+
+/* add NET commands if we have at least 1 LAN */
+#if defined(CONFIG_MACB) || defined(CONFIG_ENC28J60)
+# define CONFIG_CMD_PING
+# define CONFIG_CMD_DHCP
+# define CONFIG_CMD_MII
+/* is this really needed ? */
+# define CONFIG_RESET_PHY_R
+/* BOOTP options */
+# define CONFIG_BOOTP_BOOTFILESIZE
+# define CONFIG_BOOTP_BOOTPATH
+# define CONFIG_BOOTP_GATEWAY
+# define CONFIG_BOOTP_HOSTNAME
+#endif
+
+/* linux in NAND flash */
+#define CONFIG_BOOTCOUNT_LIMIT	1
+#define CONFIG_BOOTCOMMAND \
+	"nand read 0x21000000 0xA0000 0x200000; bootm"
+#define CONFIG_BOOTARGS \
+	"console=ttyS0,115200 " \
+	"root=/dev/mtdblock2 " \
+	"mtdparts=atmel_nand:" \
+		"640k(uboot)ro," \
+		"2M(linux)," \
+		"16M(root)," \
+		"-(rest) " \
+	"rw "\
+	"rootfstype=jffs2"
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN \
+	ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/trats.h b/qemu/roms/u-boot/include/configs/trats.h
new file mode 100644
index 000000000..c4afecf3d
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/trats.h
@@ -0,0 +1,270 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics
+ * Heungjun Kim <riverful.kim@samsung.com>
+ *
+ * Configuation settings for the SAMSUNG TRATS (EXYNOS4210) board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_TRATS_H
+#define __CONFIG_TRATS_H
+
+#include <configs/exynos4-dt.h>
+
+#define CONFIG_SYS_PROMPT	"Trats # "	/* Monitor Command Prompt */
+
+#define CONFIG_TRATS
+
+#undef CONFIG_DEFAULT_DEVICE_TREE
+#define CONFIG_DEFAULT_DEVICE_TREE	exynos4210-trats
+
+#define CONFIG_TIZEN			/* TIZEN lib */
+
+#define CONFIG_SYS_L2CACHE_OFF
+#ifndef CONFIG_SYS_L2CACHE_OFF
+#define CONFIG_SYS_L2_PL310
+#define CONFIG_SYS_PL310_BASE	0x10502000
+#endif
+
+/* TRATS has 4 banks of DRAM */
+#define CONFIG_NR_DRAM_BANKS		4
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define PHYS_SDRAM_1			CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_TEXT_BASE		0x63300000
+#define SDRAM_BANK_SIZE			(256 << 20)	/* 256 MB */
+
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5000000)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x4800000)
+
+#define CONFIG_SYS_TEXT_BASE		0x63300000
+
+#include <linux/sizes.h>
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (80 * SZ_1M))
+
+/* select serial console configuration */
+#define CONFIG_SERIAL2
+#define CONFIG_BAUDRATE			115200
+
+/* Console configuration */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+/* MACH_TYPE_TRATS macro will be removed once added to mach-types */
+#define MACH_TYPE_TRATS			3928
+#define CONFIG_MACH_TYPE		MACH_TYPE_TRATS
+
+#define CONFIG_BOOTARGS			"Please use defined boot"
+#define CONFIG_BOOTCOMMAND		"run mmcboot"
+#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC1,115200n8\0"
+
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_LOAD_ADDR \
+					- GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_MEM_TOP_HIDE	(1 << 20)	/* ram console */
+
+#define CONFIG_SYS_MONITOR_BASE	0x00000000
+
+#define CONFIG_BOOTBLOCK		"10"
+#define CONFIG_ENV_COMMON_BOOT		"${console} ${meminfo}"
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV		CONFIG_MMC_DEFAULT_DEV
+#define CONFIG_ENV_SIZE			4096
+#define CONFIG_ENV_OFFSET		((32 - 4) << 10) /* 32KiB - 4KiB */
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+/* Tizen - partitions definitions */
+#define PARTS_CSA		"csa-mmc"
+#define PARTS_BOOT		"boot"
+#define PARTS_QBOOT		"qboot"
+#define PARTS_CSC		"csc"
+#define PARTS_ROOT		"platform"
+#define PARTS_DATA		"data"
+#define PARTS_UMS		"ums"
+
+#define PARTS_DEFAULT \
+	"uuid_disk=${uuid_gpt_disk};" \
+	"name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
+	"name="PARTS_BOOT",size=60MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
+	"name="PARTS_QBOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_QBOOT"};" \
+	"name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \
+	"name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
+	"name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
+	"name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \
+
+#define CONFIG_DFU_ALT \
+	"u-boot raw 0x80 0x400;" \
+	"uImage ext4 0 2;" \
+	"modem.bin ext4 0 2;" \
+	"exynos4210-trats.dtb ext4 0 2;" \
+	""PARTS_CSA" part 0 1;" \
+	""PARTS_BOOT" part 0 2;" \
+	""PARTS_QBOOT" part 0 3;" \
+	""PARTS_CSC" part 0 4;" \
+	""PARTS_ROOT" part 0 5;" \
+	""PARTS_DATA" part 0 6;" \
+	""PARTS_UMS" part 0 7;" \
+	"params.bin raw 0x38 0x8\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"bootk=" \
+		"run loaduimage;" \
+		"if run loaddtb; then " \
+			"bootm 0x40007FC0 - ${fdtaddr};" \
+		"fi;" \
+		"bootm 0x40007FC0;\0" \
+	"updatemmc=" \
+		"mmc boot 0 1 1 1; mmc write 0 0x42008000 0 0x200;" \
+		"mmc boot 0 1 1 0\0" \
+	"updatebackup=" \
+		"mmc boot 0 1 1 2; mmc write 0 0x42100000 0 0x200;" \
+		"mmc boot 0 1 1 0\0" \
+	"updatebootb=" \
+		"mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \
+	"lpj=lpj=3981312\0" \
+	"nfsboot=" \
+		"setenv bootargs root=/dev/nfs rw " \
+		"nfsroot=${nfsroot},nolock,tcp " \
+		"ip=${ipaddr}:${serverip}:${gatewayip}:" \
+		"${netmask}:generic:usb0:off " CONFIG_ENV_COMMON_BOOT \
+		"; run bootk\0" \
+	"ramfsboot=" \
+		"setenv bootargs root=/dev/ram0 rw rootfstype=ext2 " \
+		"${console} ${meminfo} " \
+		"initrd=0x43000000,8M ramdisk=8192\0" \
+	"mmcboot=" \
+		"setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
+		"${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \
+		"run bootk\0" \
+	"bootchart=setenv opts init=/sbin/bootchartd; run bootcmd\0" \
+	"boottrace=setenv opts initcall_debug; run bootcmd\0" \
+	"mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \
+	"verify=n\0" \
+	"rootfstype=ext4\0" \
+	"console=" CONFIG_DEFAULT_CONSOLE \
+	"meminfo=crashkernel=32M@0x50000000\0" \
+	"nfsroot=/nfsroot/arm\0" \
+	"bootblock=" CONFIG_BOOTBLOCK "\0" \
+	"loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \
+	"loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \
+		"${fdtfile}\0" \
+	"mmcdev=0\0" \
+	"mmcbootpart=2\0" \
+	"mmcrootpart=5\0" \
+	"opts=always_resume=1\0" \
+	"partitions=" PARTS_DEFAULT \
+	"dfu_alt_info=" CONFIG_DFU_ALT \
+	"spladdr=0x40000100\0" \
+	"splsize=0x200\0" \
+	"splfile=falcon.bin\0" \
+	"spl_export=" \
+		   "setexpr spl_imgsize ${splsize} + 8 ;" \
+		   "setenv spl_imgsize 0x${spl_imgsize};" \
+		   "setexpr spl_imgaddr ${spladdr} - 8 ;" \
+		   "setexpr spl_addr_tmp ${spladdr} - 4 ;" \
+		   "mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \
+		   "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
+		   "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};" \
+		   "spl export atags 0x40007FC0;" \
+		   "crc32 ${spladdr} ${splsize} ${spl_imgaddr};" \
+		   "mw.l ${spl_addr_tmp} ${splsize};" \
+		   "ext4write mmc ${mmcdev}:${mmcbootpart}" \
+		   " /${splfile} ${spl_imgaddr} ${spl_imgsize};" \
+		   "setenv spl_imgsize;" \
+		   "setenv spl_imgaddr;" \
+		   "setenv spl_addr_tmp;\0" \
+	"fdtaddr=40800000\0" \
+
+/* Falcon mode definitions */
+#define CONFIG_CMD_SPL
+#define CONFIG_SYS_SPL_ARGS_ADDR        CONFIG_SYS_SDRAM_BASE + 0x100
+
+/* GPT */
+#define CONFIG_RANDOM_UUID
+
+/* I2C */
+#include <asm/arch/gpio.h>
+
+#define CONFIG_CMD_I2C
+
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_S3C24X0
+#define CONFIG_SYS_I2C_S3C24X0_SPEED	100000
+#define CONFIG_SYS_I2C_S3C24X0_SLAVE	0xFE
+#define CONFIG_MAX_I2C_NUM		8
+#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED	50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0x7F
+#define CONFIG_SOFT_I2C_READ_REPEATED_START
+#define CONFIG_SYS_I2C_INIT_BOARD
+
+/* I2C FG */
+#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_get(2, y4, 1)
+#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_get(2, y4, 0)
+
+/* POWER */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_MAX8997
+
+#define CONFIG_POWER_FG
+#define CONFIG_POWER_FG_MAX17042
+#define CONFIG_POWER_MUIC
+#define CONFIG_POWER_MUIC_MAX8997
+#define CONFIG_POWER_BATTERY
+#define CONFIG_POWER_BATTERY_TRATS
+
+/* Security subsystem - enable hw_rand() */
+#define CONFIG_EXYNOS_ACE_SHA
+#define CONFIG_LIB_HW_RAND
+
+/* Common misc for Samsung */
+#define CONFIG_MISC_COMMON
+
+#define CONFIG_MISC_INIT_R
+
+/* Download menu - Samsung common */
+#define CONFIG_LCD_MENU
+#define CONFIG_LCD_MENU_BOARD
+
+/* Download menu - definitions for check keys */
+#ifndef __ASSEMBLY__
+#include <power/max8997_pmic.h>
+
+#define KEY_PWR_PMIC_NAME		"MAX8997_PMIC"
+#define KEY_PWR_STATUS_REG		MAX8997_REG_STATUS1
+#define KEY_PWR_STATUS_MASK		(1 << 0)
+#define KEY_PWR_INTERRUPT_REG		MAX8997_REG_INT1
+#define KEY_PWR_INTERRUPT_MASK		(1 << 0)
+
+#define KEY_VOL_UP_GPIO			exynos4_gpio_get(2, x2, 0)
+#define KEY_VOL_DOWN_GPIO		exynos4_gpio_get(2, x2, 1)
+#endif /* __ASSEMBLY__ */
+
+/* LCD console */
+#define LCD_BPP			LCD_COLOR16
+#define CONFIG_SYS_WHITE_ON_BLACK
+
+/* LCD */
+#define CONFIG_EXYNOS_FB
+#define CONFIG_LCD
+#define CONFIG_CMD_BMP
+#define CONFIG_BMP_16BPP
+#define CONFIG_FB_ADDR		0x52504000
+#define CONFIG_S6E8AX0
+#define CONFIG_EXYNOS_MIPI_DSIM
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE  ((500 * 160 * 4) + 54)
+
+#define LCD_XRES	720
+#define LCD_YRES	1280
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/trats2.h b/qemu/roms/u-boot/include/configs/trats2.h
new file mode 100644
index 000000000..14def7d16
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/trats2.h
@@ -0,0 +1,252 @@
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ * Sanghee Kim <sh0130.kim@samsung.com>
+ * Piotr Wilczek <p.wilczek@samsung.com>
+ *
+ * Configuation settings for the SAMSUNG TRATS2 (EXYNOS4412) board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_TRATS2_H
+#define __CONFIG_TRATS2_H
+
+#include <configs/exynos4-dt.h>
+
+#define CONFIG_SYS_PROMPT	"Trats2 # "	/* Monitor Command Prompt */
+
+#undef CONFIG_DEFAULT_DEVICE_TREE
+#define CONFIG_DEFAULT_DEVICE_TREE	exynos4412-trats2
+
+#define CONFIG_TIZEN			/* TIZEN lib */
+
+#define CONFIG_SYS_L2CACHE_OFF
+#ifndef CONFIG_SYS_L2CACHE_OFF
+#define CONFIG_SYS_L2_PL310
+#define CONFIG_SYS_PL310_BASE	0x10502000
+#endif
+
+/* TRATS2 has 4 banks of DRAM */
+#define CONFIG_NR_DRAM_BANKS		4
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define PHYS_SDRAM_1			CONFIG_SYS_SDRAM_BASE
+#define SDRAM_BANK_SIZE			(256 << 20)	/* 256 MB */
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5E00000)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x3E00000)
+
+#define CONFIG_SYS_TEXT_BASE		0x43e00000
+
+#include <linux/sizes.h>
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (80 * SZ_1M))
+
+/* select serial console configuration */
+#define CONFIG_SERIAL2
+#define CONFIG_BAUDRATE			115200
+
+/* Console configuration */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+#define CONFIG_BOOTARGS			"Please use defined boot"
+#define CONFIG_BOOTCOMMAND		"run mmcboot"
+#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC1,115200n8\0"
+
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_LOAD_ADDR \
+					- GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_MEM_TOP_HIDE	(1 << 20)	/* ram console */
+
+#define CONFIG_SYS_MONITOR_BASE	0x00000000
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV		CONFIG_MMC_DEFAULT_DEV
+#define CONFIG_ENV_SIZE			4096
+#define CONFIG_ENV_OFFSET		((32 - 4) << 10) /* 32KiB - 4KiB */
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+/* Tizen - partitions definitions */
+#define PARTS_CSA		"csa-mmc"
+#define PARTS_BOOT		"boot"
+#define PARTS_QBOOT		"qboot"
+#define PARTS_CSC		"csc"
+#define PARTS_ROOT		"platform"
+#define PARTS_DATA		"data"
+#define PARTS_UMS		"ums"
+
+#define PARTS_DEFAULT \
+	"uuid_disk=${uuid_gpt_disk};" \
+	"name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
+	"name="PARTS_BOOT",size=60MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
+	"name="PARTS_QBOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_QBOOT"};" \
+	"name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \
+	"name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
+	"name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
+	"name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \
+
+#define CONFIG_DFU_ALT \
+	"u-boot raw 0x80 0x800;" \
+	"uImage ext4 0 2;" \
+	"modem.bin ext4 0 2;" \
+	"exynos4412-trats2.dtb ext4 0 2;" \
+	""PARTS_CSA" part 0 1;" \
+	""PARTS_BOOT" part 0 2;" \
+	""PARTS_QBOOT" part 0 3;" \
+	""PARTS_CSC" part 0 4;" \
+	""PARTS_ROOT" part 0 5;" \
+	""PARTS_DATA" part 0 6;" \
+	""PARTS_UMS" part 0 7;" \
+	"params.bin raw 0x38 0x8\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"bootk=" \
+		"run loaduimage;" \
+		"if run loaddtb; then " \
+			"bootm 0x40007FC0 - ${fdtaddr};" \
+		"fi;" \
+		"bootm 0x40007FC0;\0" \
+	"updatemmc=" \
+		"mmc boot 0 1 1 1; mmc write 0x42008000 0 0x200;" \
+		"mmc boot 0 1 1 0\0" \
+	"updatebackup=" \
+		"mmc boot 0 1 1 2; mmc write 0x42100000 0 0x200;" \
+		" mmc boot 0 1 1 0\0" \
+	"updatebootb=" \
+		"mmc read 0x51000000 0x80 0x200; run updatebackup\0" \
+	"updateuboot=" \
+		"mmc write 0x50000000 0x80 0x400\0" \
+	"mmcboot=" \
+		"setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
+		"${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \
+		"run bootk\0" \
+	"bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \
+	"boottrace=setenv opts initcall_debug; run bootcmd\0" \
+	"verify=n\0" \
+	"rootfstype=ext4\0" \
+	"console=" CONFIG_DEFAULT_CONSOLE \
+	"kernelname=uImage\0" \
+	"loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 " \
+		"${kernelname}\0" \
+	"loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \
+		"${fdtfile}\0" \
+	"mmcdev=" __stringify(CONFIG_MMC_DEFAULT_DEV) "\0" \
+	"mmcbootpart=2\0" \
+	"mmcrootpart=5\0" \
+	"opts=always_resume=1\0" \
+	"partitions=" PARTS_DEFAULT \
+	"dfu_alt_info=" CONFIG_DFU_ALT \
+	"uartpath=ap\0" \
+	"usbpath=ap\0" \
+	"consoleon=set console console=ttySAC2,115200n8; save; reset\0" \
+	"consoleoff=set console console=ram; save; reset\0" \
+	"spladdr=0x40000100\0" \
+	"splsize=0x200\0" \
+	"splfile=falcon.bin\0" \
+	"spl_export=" \
+		   "setexpr spl_imgsize ${splsize} + 8 ;" \
+		   "setenv spl_imgsize 0x${spl_imgsize};" \
+		   "setexpr spl_imgaddr ${spladdr} - 8 ;" \
+		   "setexpr spl_addr_tmp ${spladdr} - 4 ;" \
+		   "mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \
+		   "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
+		   "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};" \
+		   "spl export atags 0x40007FC0;" \
+		   "crc32 ${spladdr} ${splsize} ${spl_imgaddr};" \
+		   "mw.l ${spl_addr_tmp} ${splsize};" \
+		   "ext4write mmc ${mmcdev}:${mmcbootpart}" \
+		   " /${splfile} ${spl_imgaddr} ${spl_imgsize};" \
+		   "setenv spl_imgsize;" \
+		   "setenv spl_imgaddr;" \
+		   "setenv spl_addr_tmp;\0" \
+	"fdtaddr=40800000\0" \
+
+/* GPT */
+#define CONFIG_RANDOM_UUID
+
+/* I2C */
+#include <asm/arch/gpio.h>
+
+#define CONFIG_CMD_I2C
+
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_S3C24X0
+#define CONFIG_SYS_I2C_S3C24X0_SPEED	100000
+#define CONFIG_SYS_I2C_S3C24X0_SLAVE	0
+#define CONFIG_MAX_I2C_NUM		8
+#define CONFIG_SYS_I2C_SOFT
+#define CONFIG_SYS_I2C_SOFT_SPEED	50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0x00
+#define I2C_SOFT_DECLARATIONS2
+#define CONFIG_SYS_I2C_SOFT_SPEED_2     50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_2     0x00
+#define CONFIG_SOFT_I2C_READ_REPEATED_START
+#define CONFIG_SYS_I2C_INIT_BOARD
+
+#ifndef __ASSEMBLY__
+int get_soft_i2c_scl_pin(void);
+int get_soft_i2c_sda_pin(void);
+#endif
+#define CONFIG_SOFT_I2C_GPIO_SCL	get_soft_i2c_scl_pin()
+#define CONFIG_SOFT_I2C_GPIO_SDA	get_soft_i2c_sda_pin()
+
+/* POWER */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_MAX77686
+#define CONFIG_POWER_PMIC_MAX77693
+#define CONFIG_POWER_MUIC_MAX77693
+#define CONFIG_POWER_FG_MAX77693
+#define CONFIG_POWER_BATTERY_TRATS2
+
+/* Security subsystem - enable hw_rand() */
+#define CONFIG_EXYNOS_ACE_SHA
+#define CONFIG_LIB_HW_RAND
+
+/* Common misc for Samsung */
+#define CONFIG_MISC_COMMON
+
+#define CONFIG_MISC_INIT_R
+
+/* Download menu - Samsung common */
+#define CONFIG_LCD_MENU
+#define CONFIG_LCD_MENU_BOARD
+
+/* Download menu - definitions for check keys */
+#ifndef __ASSEMBLY__
+#include <power/max77686_pmic.h>
+
+#define KEY_PWR_PMIC_NAME		"MAX77686_PMIC"
+#define KEY_PWR_STATUS_REG		MAX77686_REG_PMIC_STATUS1
+#define KEY_PWR_STATUS_MASK		(1 << 0)
+#define KEY_PWR_INTERRUPT_REG		MAX77686_REG_PMIC_INT1
+#define KEY_PWR_INTERRUPT_MASK		(1 << 1)
+
+#define KEY_VOL_UP_GPIO			exynos4x12_gpio_get(2, x2, 2)
+#define KEY_VOL_DOWN_GPIO		exynos4x12_gpio_get(2, x3, 3)
+#endif /* __ASSEMBLY__ */
+
+/* LCD console */
+#define LCD_BPP                 LCD_COLOR16
+#define CONFIG_SYS_WHITE_ON_BLACK
+
+/* LCD */
+#define CONFIG_EXYNOS_FB
+#define CONFIG_LCD
+#define CONFIG_CMD_BMP
+#define CONFIG_BMP_16BPP
+#define CONFIG_FB_ADDR		0x52504000
+#define CONFIG_S6E8AX0
+#define CONFIG_EXYNOS_MIPI_DSIM
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)
+
+#define LCD_XRES	720
+#define LCD_YRES	1280
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/tricorder.h b/qemu/roms/u-boot/include/configs/tricorder.h
new file mode 100644
index 000000000..80985a265
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/tricorder.h
@@ -0,0 +1,392 @@
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * (C) Copyright 2012
+ * Corscience GmbH & Co. KG
+ * Thomas Weber <weber@corscience.de>
+ *
+ * Configuration settings for the Tricorder board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_OMAP			/* in a TI OMAP core */
+#define CONFIG_OMAP34XX			/* which is a 34XX */
+#define CONFIG_OMAP_COMMON
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_TRICORDER
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * other needs.
+ */
+#define CONFIG_SYS_TEXT_BASE		0x80100000
+
+#define CONFIG_SDRC			/* The chip has SDRC controller */
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/* Display CPU and Board information */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_SILENT_CONSOLE
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+/* Clock Defines */
+#define V_OSCK				26000000 /* Clock output from T2 */
+#define V_SCLK				(V_OSCK >> 1)
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+#define CONFIG_OF_LIBFDT
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(1024*1024)
+
+/* Hardware drivers */
+
+/* GPIO support */
+#define CONFIG_OMAP_GPIO
+
+/* GPIO banks */
+#define CONFIG_OMAP3_GPIO_2		/* GPIO32..63 are in GPIO bank 2 */
+
+/* LED support */
+#define CONFIG_STATUS_LED
+#define CONFIG_BOARD_SPECIFIC_LED
+#define CONFIG_CMD_LED			/* LED command */
+#define STATUS_LED_BIT			(1 << 0)
+#define STATUS_LED_STATE		STATUS_LED_ON
+#define STATUS_LED_PERIOD		(CONFIG_SYS_HZ / 2)
+#define STATUS_LED_BIT1			(1 << 1)
+#define STATUS_LED_STATE1		STATUS_LED_ON
+#define STATUS_LED_PERIOD1		(CONFIG_SYS_HZ / 2)
+#define STATUS_LED_BIT2			(1 << 2)
+#define STATUS_LED_STATE2		STATUS_LED_ON
+#define STATUS_LED_PERIOD2		(CONFIG_SYS_HZ / 2)
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		48000000 /* 48MHz (APLL96/2) */
+
+/* select serial console configuration */
+#define CONFIG_CONS_INDEX		3
+#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
+#define CONFIG_SERIAL3			3
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
+					115200}
+
+/* MMC */
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_DOS_PARTITION
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
+#define CONFIG_SYS_I2C_OMAP34XX
+ 
+
+/* EEPROM */
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+#define CONFIG_SYS_EEPROM_BUS_NUM	1
+
+/* TWL4030 */
+#define CONFIG_TWL4030_POWER
+#define CONFIG_TWL4030_LED
+
+/* Board NAND Info */
+#define CONFIG_SYS_NO_FLASH		/* no NOR flash */
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define MTDIDS_DEFAULT			"nand0=omap2-nand.0"
+#define MTDPARTS_DEFAULT		"mtdparts=omap2-nand.0:" \
+						"128k(SPL)," \
+						"1m(u-boot)," \
+						"384k(u-boot-env1)," \
+						"1152k(mtdoops)," \
+						"384k(u-boot-env2)," \
+						"5m(kernel)," \
+						"2m(fdt)," \
+						"-(ubi)"
+
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
+							/* to access nand */
+#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
+							/* to access nand at */
+							/* CS0 */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
+							/* devices */
+#define CONFIG_BCH
+#define CONFIG_SYS_NAND_MAX_OOBFREE	2
+#define CONFIG_SYS_NAND_MAX_ECCPOS	56
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_EXT2			/* EXT2 Support */
+#define CONFIG_CMD_FAT			/* FAT support */
+#define CONFIG_CMD_I2C			/* I2C serial bus support */
+#define CONFIG_CMD_MMC			/* MMC support */
+#define CONFIG_CMD_MTDPARTS		/* Enable MTD parts commands */
+#define CONFIG_CMD_NAND			/* NAND support */
+#define CONFIG_CMD_NAND_LOCK_UNLOCK	/* nand (un)lock commands */
+#define CONFIG_CMD_UBI			/* UBI commands */
+#define CONFIG_CMD_UBIFS		/* UBIFS commands */
+#define CONFIG_LZO			/* LZO is needed for UBIFS */
+
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_FPGA			/* FPGA configuration Support */
+#undef CONFIG_CMD_IMI			/* iminfo */
+#undef CONFIG_CMD_JFFS2			/* JFFS2 Support */
+
+/* needed for ubi */
+#define CONFIG_RBTREE
+#define CONFIG_MTD_DEVICE       /* needed for mtdparts commands */
+#define CONFIG_MTD_PARTITIONS
+
+/* Environment information (this is the common part) */
+
+#define CONFIG_BOOTDELAY		0
+
+/* hang() the board on panic() */
+#define CONFIG_PANIC_HANG
+
+/* environment placement (for NAND), is different for FLASHCARD but does not
+ * harm there */
+#define CONFIG_ENV_OFFSET		0x120000    /* env start */
+#define CONFIG_ENV_OFFSET_REDUND	0x2A0000    /* redundant env start */
+#define CONFIG_ENV_SIZE			(16 << 10)  /* use 16KiB for env */
+#define CONFIG_ENV_RANGE		(384 << 10) /* allow badblocks in env */
+
+/* the loadaddr is the same as CONFIG_SYS_LOAD_ADDR, unfortunately the defiend
+ * value can not be used here! */
+#define CONFIG_LOADADDR		0x82000000
+
+#define CONFIG_COMMON_ENV_SETTINGS \
+	"console=ttyO2,115200n8\0" \
+	"mmcdev=0\0" \
+	"vram=3M\0" \
+	"defaultdisplay=lcd\0" \
+	"kernelopts=mtdoops.mtddev=3\0" \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"mtdids=" MTDIDS_DEFAULT "\0" \
+	"commonargs=" \
+		"setenv bootargs console=${console} " \
+		"${mtdparts} " \
+		"${kernelopts} " \
+		"vt.global_cursor_default=0 " \
+		"vram=${vram} " \
+		"omapdss.def_disp=${defaultdisplay}\0"
+
+#define CONFIG_BOOTCOMMAND "run autoboot"
+
+/* specific environment settings for different use cases
+ * FLASHCARD: used to run a rdimage from sdcard to program the device
+ * 'NORMAL': used to boot kernel from sdcard, nand, ...
+ *
+ * The main aim for the FLASHCARD skin is to have an embedded environment
+ * which will not be influenced by any data already on the device.
+ */
+#ifdef CONFIG_FLASHCARD
+
+#define CONFIG_ENV_IS_NOWHERE
+
+/* the rdaddr is 16 MiB before the loadaddr */
+#define CONFIG_ENV_RDADDR	"rdaddr=0x81000000\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	CONFIG_COMMON_ENV_SETTINGS \
+	CONFIG_ENV_RDADDR \
+	"autoboot=" \
+	"run commonargs; " \
+	"setenv bootargs ${bootargs} " \
+		"flashy_updateimg=/dev/mmcblk0p1:corscience_update.img " \
+		"rdinit=/sbin/init; " \
+	"mmc dev ${mmcdev}; mmc rescan; " \
+	"fatload mmc ${mmcdev} ${loadaddr} uImage; " \
+	"fatload mmc ${mmcdev} ${rdaddr} uRamdisk; " \
+	"bootm ${loadaddr} ${rdaddr}\0"
+
+#else /* CONFIG_FLASHCARD */
+
+#define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */
+
+#define CONFIG_ENV_IS_IN_NAND
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	CONFIG_COMMON_ENV_SETTINGS \
+	"mmcargs=" \
+		"run commonargs; " \
+		"setenv bootargs ${bootargs} " \
+		"root=/dev/mmcblk0p2 " \
+		"rootwait " \
+		"rw\0" \
+	"nandargs=" \
+		"run commonargs; " \
+		"setenv bootargs ${bootargs} " \
+		"root=ubi0:root " \
+		"ubi.mtd=7 " \
+		"rootfstype=ubifs " \
+		"ro\0" \
+	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source ${loadaddr}\0" \
+	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0" \
+	"loaduimage_ubi=ubi part ubi; " \
+		"ubifsmount ubi:root; " \
+		"ubifsload ${loadaddr} /boot/uImage\0" \
+	"loaduimage_nand=nand read ${loadaddr} kernel 0x500000\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"run loaduimage_nand; " \
+		"bootm ${loadaddr}\0" \
+	"autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
+			"if run loadbootscript; then " \
+				"run bootscript; " \
+			"else " \
+				"if run loaduimage; then " \
+					"run mmcboot; " \
+				"else run nandboot; " \
+				"fi; " \
+			"fi; " \
+		"else run nandboot; fi\0"
+
+#endif /* CONFIG_FLASHCARD */
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_CMDLINE_EDITING		/* enable cmdline history */
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_PROMPT		"OMAP3 Tricorder # "
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
+
+#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0 + 0x00000000)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
+					0x07000000) /* 112 MB */
+
+#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0 + 0x02000000)
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
+#define CONFIG_SYS_PTV			2 /* Divisor: 2^(PTV+1) => 8 */
+
+/*  Physical Memory Map  */
+#define CONFIG_NR_DRAM_BANKS		2 /* CS1 may or may not be populated */
+#define PHYS_SDRAM_1			OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_2			OMAP34XX_SDRC_CS1
+
+/* NAND and environment organization  */
+#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE	0x800
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_INIT_RAM_ADDR + \
+						CONFIG_SYS_INIT_RAM_SIZE - \
+						GENERATED_GBL_DATA_SIZE)
+
+/* SRAM config */
+#define CONFIG_SYS_SRAM_START		0x40200000
+#define CONFIG_SYS_SRAM_SIZE		0x10000
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_NAND_SIMPLE
+
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME        "u-boot.img"
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION    1
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
+
+#define CONFIG_SPL_TEXT_BASE		0x40200000 /*CONFIG_SYS_SRAM_START*/
+#define CONFIG_SPL_MAX_SIZE		(57 * 1024)	/* 7 KB for stack */
+#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
+
+#define CONFIG_SPL_BSS_START_ADDR	0x80000000 /*CONFIG_SYS_SDRAM_BASE*/
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
+
+/* NAND boot config */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
+					 13, 14, 16, 17, 18, 19, 20, 21, 22, \
+					 23, 24, 25, 26, 27, 28, 30, 31, 32, \
+					 33, 34, 35, 36, 37, 38, 39, 40, 41, \
+					 42, 44, 45, 46, 47, 48, 49, 50, 51, \
+					 52, 53, 54, 55, 56}
+
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	13
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
+
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x20000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x100000
+
+#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000	/* 1 MB */
+
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_SYS_MEMTEST_SCRATCH	0x81000000
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/trimslice.h b/qemu/roms/u-boot/include/configs/trimslice.h
new file mode 100644
index 000000000..f81cfa2e3
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/trimslice.h
@@ -0,0 +1,77 @@
+/*
+ *  (C) Copyright 2010-2012
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+#include "tegra20-common.h"
+
+/* Enable fdt support for TrimSlice. Flash the image in u-boot-dtb.bin */
+#define CONFIG_DEFAULT_DEVICE_TREE	tegra20-trimslice
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
+/* High-level configuration options */
+#define V_PROMPT		"Tegra20 (TrimSlice) # "
+#define CONFIG_TEGRA_BOARD_STRING	"Compulab Trimslice"
+
+/* Board-specific serial config */
+#define CONFIG_TEGRA_ENABLE_UARTA
+#define CONFIG_TEGRA_UARTA_GPU
+#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_TRIMSLICE
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* SPI */
+#define CONFIG_TEGRA20_SFLASH
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+
+/* I2C */
+#define CONFIG_SYS_I2C_TEGRA
+#define CONFIG_SYS_I2C_INIT_BOARD
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_TEGRA_MMC
+#define CONFIG_CMD_MMC
+
+/* Environment in SPI */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_MAX_HZ		48000000
+#define CONFIG_ENV_SPI_MODE		SPI_MODE_0
+#define CONFIG_ENV_SECT_SIZE		CONFIG_ENV_SIZE
+#define CONFIG_ENV_OFFSET		(512 * 1024)
+
+/* USB Host support */
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_TEGRA
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB
+
+/* USB networking support */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+
+/* General networking support */
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/trizepsiv.h b/qemu/roms/u-boot/include/configs/trizepsiv.h
new file mode 100644
index 000000000..b7804d287
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/trizepsiv.h
@@ -0,0 +1,311 @@
+/*
+ * (C) Copyright 2007
+ * Stefano Babic, DENX Gmbh, sbabic@denx.de
+ *
+ * (C) Copyright 2004
+ * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Configuation settings for the LUBBOCK board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_CPU_PXA27X		1	/* This is an PXA27x CPU    */
+
+#define CONFIG_MMC		1
+#define CONFIG_BOARD_LATE_INIT
+#define	CONFIG_SYS_TEXT_BASE	0x0
+
+/* we will never enable dcache, because we have to setup MMU first */
+#define CONFIG_SYS_DCACHE_OFF
+
+#define RTC
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN	    (CONFIG_ENV_SIZE + 128*1024)
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_PXA_SERIAL
+#define CONFIG_FFUART	       1       /* we use FFUART on Conxs */
+#define CONFIG_BTUART	       1       /* we use BTUART on Conxs */
+#define CONFIG_STUART	       1       /* we use STUART on Conxs */
+#define CONFIG_CONS_INDEX	3
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE	       38400
+
+#define CONFIG_DOS_PARTITION   1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_IMLS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+
+#undef CONFIG_SHOW_BOOT_PROGRESS
+
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_SERVERIP		192.168.1.99
+#define CONFIG_BOOTCOMMAND	"run boot_flash"
+#define CONFIG_BOOTARGS		"console=ttyS0,38400 ramdisk_size=12288"\
+				" rw root=/dev/ram initrd=0xa0800000,5m"
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"program_boot_mmc="						\
+			"mw.b 0xa0010000 0xff 0x20000; "		\
+			"if	 mmcinit && "				\
+				"fatload mmc 0 0xa0010000 u-boot.bin; "	\
+			"then "						\
+				"protect off 0x0 0x1ffff; "		\
+				"erase 0x0 0x1ffff; "			\
+				"cp.b 0xa0010000 0x0 0x20000; "		\
+			"fi\0"						\
+	"program_uzImage_mmc="						\
+			"mw.b 0xa0010000 0xff 0x180000; "		\
+			"if	 mmcinit && "				\
+				"fatload mmc 0 0xa0010000 uzImage; "	\
+			"then "						\
+				"protect off 0x40000 0x1bffff; "	\
+				"erase 0x40000 0x1bffff; "		\
+				"cp.b 0xa0010000 0x40000 0x180000; "	\
+			"fi\0"						\
+	"program_ramdisk_mmc="						\
+			"mw.b 0xa0010000 0xff 0x500000; "		\
+			"if	 mmcinit && "				\
+				"fatload mmc 0 0xa0010000 ramdisk.gz; "	\
+			"then "						\
+				"protect off 0x1c0000 0x6bffff; "	\
+				"erase 0x1c0000 0x6bffff; "		\
+				"cp.b 0xa0010000 0x1c0000 0x500000; "	\
+			"fi\0"						\
+	"boot_mmc="							\
+			"if	 mmcinit && "				\
+				"fatload mmc 0 0xa0030000 uzImage && "	\
+				"fatload mmc 0 0xa0800000 ramdisk.gz; "	\
+			"then "						\
+				"bootm 0xa0030000; "			\
+			"fi\0"						\
+	"boot_flash="							\
+			"cp.b 0x1c0000 0xa0800000 0x500000; "		\
+			"bootm 0x40000\0"				\
+
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_CMDLINE_TAG	 1	/* enable passing of ATAGs	*/
+/* #define CONFIG_INITRD_TAG	 1 */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_HUSH_PARSER		1
+
+#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT		"$ "		/* Monitor Command Prompt */
+#else
+#endif
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_DEVICE_NULLDEV	1
+
+#define CONFIG_SYS_MEMTEST_START	0xa0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0xa1000000	/* default load address */
+
+#define CONFIG_SYS_CPUSPEED		0x207		/* need to look more closely, I think this is Turbo = 2x, L=91Mhz */
+
+#ifdef CONFIG_MMC
+#define	CONFIG_GENERIC_MMC
+#define	CONFIG_PXA_MMC_GENERIC
+#define CONFIG_CMD_MMC
+#define CONFIG_SYS_MMC_BASE		0xF0000000
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	4	   /* we have 2 banks of DRAM */
+#define PHYS_SDRAM_1		0xa0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x04000000 /* 64 MB */
+#define PHYS_SDRAM_2		0xa4000000 /* SDRAM Bank #2 */
+#define PHYS_SDRAM_2_SIZE	0x00000000 /* 0 MB */
+#define PHYS_SDRAM_3		0xa8000000 /* SDRAM Bank #3 */
+#define PHYS_SDRAM_3_SIZE	0x00000000 /* 0 MB */
+#define PHYS_SDRAM_4		0xac000000 /* SDRAM Bank #4 */
+#define PHYS_SDRAM_4_SIZE	0x00000000 /* 0 MB */
+
+#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
+
+#define CONFIG_SYS_DRAM_BASE		0xa0000000
+#define CONFIG_SYS_DRAM_SIZE		0x04000000
+
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
+/*
+ * GPIO settings
+ */
+#define CONFIG_SYS_GPSR0_VAL		0x00018000
+#define CONFIG_SYS_GPSR1_VAL		0x00000000
+#define CONFIG_SYS_GPSR2_VAL		0x400dc000
+#define CONFIG_SYS_GPSR3_VAL		0x00000000
+#define CONFIG_SYS_GPCR0_VAL		0x00000000
+#define CONFIG_SYS_GPCR1_VAL		0x00000000
+#define CONFIG_SYS_GPCR2_VAL		0x00000000
+#define CONFIG_SYS_GPCR3_VAL		0x00000000
+#define CONFIG_SYS_GPDR0_VAL		0x00018000
+#define CONFIG_SYS_GPDR1_VAL		0x00028801
+#define CONFIG_SYS_GPDR2_VAL		0x520dc000
+#define CONFIG_SYS_GPDR3_VAL		0x0001E000
+#define CONFIG_SYS_GAFR0_L_VAL		0x801c0000
+#define CONFIG_SYS_GAFR0_U_VAL		0x00000013
+#define CONFIG_SYS_GAFR1_L_VAL		0x6990100A
+#define CONFIG_SYS_GAFR1_U_VAL		0x00000008
+#define CONFIG_SYS_GAFR2_L_VAL		0xA0000000
+#define CONFIG_SYS_GAFR2_U_VAL		0x010900F2
+#define CONFIG_SYS_GAFR3_L_VAL		0x54000003
+#define CONFIG_SYS_GAFR3_U_VAL		0x00002401
+#define CONFIG_SYS_GRER0_VAL		0x00000000
+#define CONFIG_SYS_GRER1_VAL		0x00000000
+#define CONFIG_SYS_GRER2_VAL		0x00000000
+#define CONFIG_SYS_GRER3_VAL		0x00000000
+
+#define CONFIG_SYS_GFER1_VAL		0x00000000
+#define CONFIG_SYS_GFER3_VAL		0x00000020
+
+#if CONFIG_POLARIS
+#define CONFIG_SYS_GFER0_VAL		0x00000001
+#define CONFIG_SYS_GFER2_VAL		0x00200000
+#else
+#define CONFIG_SYS_GFER0_VAL		0x00000000
+#define CONFIG_SYS_GFER2_VAL		0x00000000
+#endif
+
+#define CONFIG_SYS_PSSR_VAL		0x20	/* CHECK */
+
+/*
+ * Clock settings
+ */
+#define CONFIG_SYS_CKEN		0x01FFFFFF	/* CHECK */
+#define CONFIG_SYS_CCCR		0x02000290 /*   520Mhz */
+
+/*
+ * Memory settings
+ */
+
+#define CONFIG_SYS_MSC0_VAL		0x4df84df0
+#define CONFIG_SYS_MSC1_VAL		0x7ff87ff4
+#if CONFIG_POLARIS
+#define CONFIG_SYS_MSC2_VAL		0xa2697ff8
+#else
+#define CONFIG_SYS_MSC2_VAL		0xa26936d4
+#endif
+#define CONFIG_SYS_MDCNFG_VAL		0x880009C9
+#define CONFIG_SYS_MDREFR_VAL		0x20ca201e
+#define CONFIG_SYS_MDMRS_VAL		0x00220022
+
+#define CONFIG_SYS_FLYCNFG_VAL		0x00000000
+#define CONFIG_SYS_SXCNFG_VAL		0x40044004
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define CONFIG_SYS_MECR_VAL		0x00000001
+#define CONFIG_SYS_MCMEM0_VAL		0x00004204
+#define CONFIG_SYS_MCMEM1_VAL		0x00010204
+#define CONFIG_SYS_MCATT0_VAL		0x00010504
+#define CONFIG_SYS_MCATT1_VAL		0x00010504
+#define CONFIG_SYS_MCIO0_VAL		0x00008407
+#define CONFIG_SYS_MCIO1_VAL		0x0000c108
+
+#define CONFIG_DRIVER_DM9000		1
+
+#if CONFIG_POLARIS
+#define CONFIG_DM9000_BASE		0x0C800000
+#else
+#define CONFIG_DM9000_BASE		0x08000000
+#endif
+
+#define DM9000_IO			CONFIG_DM9000_BASE
+#define DM9000_DATA			(CONFIG_DM9000_BASE+0x8004)
+
+#define CONFIG_USB_OHCI_NEW	1
+#define CONFIG_SYS_USB_OHCI_BOARD_INIT	1
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	3
+#define CONFIG_SYS_USB_OHCI_REGS_BASE	0x4C000000
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"trizepsiv"
+#define CONFIG_USB_STORAGE	1
+#define CONFIG_SYS_USB_OHCI_CPU_INIT	1
+
+/*
+ * FLASH and environment organization
+ */
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER	1
+
+#define CONFIG_SYS_MONITOR_BASE	0
+#define CONFIG_SYS_MONITOR_LEN		0x40000
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	4 + 255  /* max number of sectors on one chip   */
+
+/* timeout values are in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(25*CONFIG_SYS_HZ) /* Timeout for Flash Write */
+
+/* write flash less slowly */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
+
+/* Unlock to be used with Intel chips */
+#define CONFIG_SYS_FLASH_PROTECTION	1
+
+/* Flash environment locations */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_ADDR		(PHYS_FLASH_1 + CONFIG_SYS_MONITOR_LEN) /* Addr of Environment Sector	*/
+#define CONFIG_ENV_SIZE		0x40000	/* Total Size of Environment		*/
+#define CONFIG_ENV_SECT_SIZE	0x40000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/tseries.h b/qemu/roms/u-boot/include/configs/tseries.h
new file mode 100644
index 000000000..8fb87ac44
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/tseries.h
@@ -0,0 +1,265 @@
+/*
+ * tseries.h
+ *
+ * specific parts for B&R T-Series Motherboard
+ *
+ * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at> -
+ * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
+ *
+ * SPDX-License-Identifier:        GPL-2.0+
+ */
+
+#ifndef __CONFIG_TSERIES_H__
+#define __CONFIG_TSERIES_H__
+
+#include <configs/bur_am335x_common.h>
+/* ------------------------------------------------------------------------- */
+/* Clock Defines */
+#define V_OSCK				26000000  /* Clock output from T2 */
+#define V_SCLK				(V_OSCK)
+
+#define CONFIG_POWER_TPS65217
+
+/* Support both device trees and ATAGs. */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMD_BOOTZ
+/*#define CONFIG_MACH_TYPE		3589*/
+#define CONFIG_MACH_TYPE		0xFFFFFFFF /* TODO: check with kernel*/
+
+/* MMC/SD IP block */
+#if defined(CONFIG_EMMC_BOOT)
+ #define CONFIG_MMC
+ #define CONFIG_GENERIC_MMC
+ #define CONFIG_OMAP_HSMMC
+ #define CONFIG_CMD_MMC
+ #define CONFIG_SUPPORT_EMMC_BOOT
+/* RAW SD card / eMMC locations. */
+ #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /*addr. 0x60000 */
+ #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS		0x200 /* 256 KB */
+ #define CONFIG_SPL_MMC_SUPPORT
+#endif /* CONFIG_EMMC_BOOT */
+
+/*
+ * When we have SPI or NAND flash we expect to be making use of mtdparts,
+ * both for ease of use in U-Boot and for passing information on to
+ * the Linux kernel.
+ */
+#if defined(CONFIG_SPI_BOOT) || defined(CONFIG_NAND)
+#define CONFIG_MTD_DEVICE		/* Required for mtdparts */
+#define CONFIG_CMD_MTDPARTS
+#endif /* CONFIG_SPI_BOOT, ... */
+
+#undef CONFIG_SPL_OS_BOOT
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_SYS_SPL_ARGS_ADDR		0x80F80000
+
+/* RAW SD card / eMMC */
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0x900	/* address 0x120000 */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0x80	/* address 0x10000 */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	0x80	/* 64KiB */
+
+/* NAND */
+#ifdef CONFIG_NAND
+#define CONFIG_CMD_SPL_NAND_OFS			0x080000 /* end of u-boot */
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS		0x140000
+#define CONFIG_CMD_SPL_WRITE_SIZE		0x2000
+#endif /* CONFIG_NAND */
+#endif /* CONFIG_SPL_OS_BOOT */
+
+#ifdef CONFIG_NAND
+#define CONFIG_SPL_NAND_AM33XX_BCH	/* OMAP4 and later ELM support */
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+#endif /* CONFIG_NAND */
+
+/* Always 128 KiB env size */
+#define CONFIG_ENV_SIZE			(128 << 10)
+
+#ifdef CONFIG_NAND
+#define NANDARGS \
+	"mtdids=" MTDIDS_DEFAULT "\0" \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${nandroot} " \
+		"rootfstype=${nandrootfstype}\0" \
+	"nandroot=ubi0:rootfs rw ubi.mtd=8,2048\0" \
+	"nandrootfstype=ubifs rootwait=1\0" \
+	"nandimgsize=0x500000\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nand read ${loadaddr} kernel ${nandimgsize}; " \
+		"bootz ${loadaddr}\0"
+#else
+#define NANDARGS ""
+#endif /* CONFIG_NAND */
+
+#ifdef CONFIG_MMC
+#define MMCARGS \
+	"silent=1\0"
+#else
+#define MMCARGS ""
+#endif /* CONFIG_MMC */
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"autoload=0\0" \
+	"loadaddr=0x80200000\0" \
+	"bootfile=zImage\0" \
+	"console=ttyO0,115200n8\0" \
+	"optargs=\0" \
+	"rootpath=/tftpboot/tseries/rootfs-small\0" \
+	"nfsopts=nolock\0" \
+	"netargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=/dev/nfs " \
+		"nfsroot=${serverip}:${rootpath},${nfsopts} rw " \
+		"ip=dhcp\0" \
+	"netboot=echo Booting from network ...; " \
+		"setenv autoload no; " \
+		"dhcp; " \
+		"tftp ${loadaddr} ${bootfile}; " \
+		"run netargs; " \
+		"bootm ${loadaddr}\0" \
+	"usbupdate=echo Updating UBOOT from USB-Stick ...; " \
+		"usb start; " \
+		"fatload usb 0 0x80000000 updateubootusb.img; " \
+		"source;\0" \
+	"netupdate=echo Updating UBOOT from Network (TFTP) ...; " \
+		"setenv autoload 0; " \
+		"dhcp;" \
+		"tftp 0x80000000 updateUBOOT.img;" \
+		"source;\0" \
+	NANDARGS \
+	MMCARGS
+#endif /* !CONFIG_SPL_BUILD*/
+
+#define CONFIG_BOOTCOMMAND \
+	"run mmcboot1;"
+#define CONFIG_BOOTDELAY		1 /* TODO: für release auf 0 setzen */
+
+#ifdef CONFIG_NAND
+/*
+ * GPMC  block.  We support 1 device and the physical address to
+ * access CS0 at is 0x8000000.
+ */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x8000000
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_CMD_NAND
+/* don't change OMAP_ELM, ECCSCHEME. ROM code only supports this */
+#define CONFIG_NAND_OMAP_ELM
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW
+#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
+					CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9, \
+					10, 11, 12, 13, 14, 15, 16, 17, \
+					18, 19, 20, 21, 22, 23, 24, 25, \
+					26, 27, 28, 29, 30, 31, 32, 33, \
+					34, 35, 36, 37, 38, 39, 40, 41, \
+					42, 43, 44, 45, 46, 47, 48, 49, \
+					50, 51, 52, 53, 54, 55, 56, 57, }
+
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	14
+
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+
+#define MTDIDS_DEFAULT			"nand0=omap2-nand.0"
+#define MTDPARTS_DEFAULT		"mtdparts=omap2-nand.0:" \
+					"128k(SPL)," \
+					"128k(SPL.backup1)," \
+					"128k(SPL.backup2)," \
+					"128k(SPL.backup3)," \
+					"512k(u-boot)," \
+					"128k(u-boot-spl-os)," \
+					"128k(u-boot-env)," \
+					"5m(kernel),"\
+					"-(rootfs)"
+#endif /* CONFIG_NAND */
+
+/* USB configuration */
+#define CONFIG_USB_MUSB_DSPS
+#define CONFIG_ARCH_MISC_INIT
+#define CONFIG_MUSB_PIO_ONLY
+#define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT
+/* attention! not only for gadget, enables also highspeed in hostmode */
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_MUSB_HOST
+#define CONFIG_AM335X_USB0
+#define CONFIG_AM335X_USB0_MODE	MUSB_HOST
+#define CONFIG_AM335X_USB1
+#define CONFIG_AM335X_USB1_MODE MUSB_HOST
+
+#ifdef CONFIG_MUSB_HOST
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#endif /* CONFIG_MUSB_HOST */
+
+#if defined(CONFIG_SPI_BOOT)
+/* McSPI IP block */
+#define CONFIG_SPI
+#define CONFIG_OMAP3_SPI
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SF_DEFAULT_SPEED		24000000
+
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_BUS		0
+#define CONFIG_SPL_SPI_CS		0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x20000
+#undef CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
+#define CONFIG_ENV_SECT_SIZE		(4 << 10) /* 4 KB sectors */
+#define CONFIG_ENV_OFFSET		(768 << 10) /* 768 KiB in */
+#define CONFIG_ENV_OFFSET_REDUND	(896 << 10) /* 896 KiB in */
+
+#elif defined(CONFIG_EMMC_BOOT)
+#undef CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV		1
+#define CONFIG_SYS_MMC_ENV_PART		2
+#define CONFIG_ENV_OFFSET		0x40000	/* TODO: Adresse definieren */
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+
+#elif defined(CONFIG_NAND)
+#undef CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		0x120000 /* TODO: Adresse definieren */
+#define CONFIG_SYS_ENV_SECT_SIZE	CONFIG_ENV_SIZE
+#else
+#error "no storage for Environment defined!"
+#endif
+/*
+ * Common filesystems support.  When we have removable storage we
+ * enabled a number of useful commands and support.
+ */
+#if defined(CONFIG_MMC) || defined(CONFIG_USB_STORAGE)
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_FAT
+#define CONFIG_FAT_WRITE
+#define CONFIG_CMD_FS_GENERIC
+#endif /* CONFIG_MMC, ... */
+
+#endif	/* ! __CONFIG_TSERIES_H__ */
diff --git a/qemu/roms/u-boot/include/configs/tt01.h b/qemu/roms/u-boot/include/configs/tt01.h
new file mode 100644
index 000000000..0937653fc
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/tt01.h
@@ -0,0 +1,272 @@
+/*
+ * (C) Copyright 2011 HALE electronic <helmut.raiger@hale.at>
+ * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
+ *
+ * Configuration settings for the HALE TT-01 board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+
+/* High Level Configuration Options */
+#define CONFIG_ARM1136
+#define CONFIG_MX31
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#define CONFIG_MACH_TYPE	3726		/* not yet in mach-types.h */
+#define CONFIG_SYS_TEXT_BASE	0xA0000000
+
+
+/*
+ * Physical Memory Map:
+ *   CS settings are defined by i.MX31:
+ *     - CSD0 and CDS1 are 256MB each, starting at 0x80000000 and 0x9000000
+ *     - CS0 and CS1 are 128MB each, at A0000000 and A8000000
+ *     - CS2 to CS5 are 32MB each, at B0.., B2.., B4.., B6..
+ *
+ * HALE set-up of the bluetechnix board for now is:
+ *   - 128MB DDR (2x64MB, 2x16bit), connected to 32bit DDR ram interface
+ *   - NOR-Flash (Spansion 32MB MCP, Flash+16MB PSRAM), 16bit interface at CS0
+ *		- S71WS256ND0BFWYM (and CS1 for 64MB S71WS512ND0 without PSRAM)
+ *        the flash chip is a mirrorbit S29WS256N !
+ *   - the PSRAM is hooked to CS5 (0xB6000000)
+ *   - Intel Strata Flash PF48F2000P0ZB00, 16bit interface at (CS0 or) CS1
+ *     - 64Mbit = 8MByte (will go away in the production set-up)
+ *   - NAND-Flash NAND01GR3B2BZA6 at NAND-FC:
+ *		1Gbit=128MB, 2048+64 bytes/page, 64pages x 1024 blocks
+ *   - Ethernet controller SMC9118 at CS4 via FPGA, 16bit interface
+ *
+ * u-boot will support the 32MB nor flash and the 128MB NAND flash, the PSRAM
+ * is not used right now. We should be able to reduce the SOM to NAND flash
+ * only and boot from there.
+ */
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM_1		CSD0_BASE
+#define PHYS_SDRAM_1_SIZE	(128 * 1024 * 1024)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR	\
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)
+
+/* default load address, 1MB up the road */
+#define CONFIG_SYS_LOAD_ADDR		(PHYS_SDRAM_1+0x100000)
+
+/* Size of malloc() pool, make sure possible frame buffer fits */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 10*1024*1024)
+
+/* memtest works on all but the last 1MB (u-boot) and malloc area  */
+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
+#define CONFIG_SYS_MEMTEST_END \
+	(PHYS_SDRAM_1+(PHYS_SDRAM_1_SIZE-CONFIG_SYS_MALLOC_LEN-0x100000))
+
+/* CFI FLASH driver setup */
+#define CONFIG_SYS_FLASH_CFI		/* Flash memory is CFI compliant */
+#define CONFIG_FLASH_CFI_DRIVER		/* Use drivers/cfi_flash.c */
+#define CONFIG_FLASH_SPANSION_S29WS_N
+/*
+ * TODO: Bluetechnix (the supplier of the SOM) did define these values
+ * in their original version of u-boot (1.2 or so). This should be
+ * reviewed.
+ *
+ * #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+ * #define CONFIG_SYS_FLASH_PROTECTION
+ */
+#define CONFIG_SYS_FLASH_BASE		CS0_BASE
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT (254+8) /* max number of sectors per chip */
+
+/*
+ * FLASH and environment organization, only the Spansion chip is supported:
+ * - it has 254 * 128kB + 8 * 32kB blocks
+ * - this setup uses 4*32k+3*128k as monitor space = 0xA000 0000 to 0xA00F FFFF
+ *		and 2 sectors with 128k as environment =
+ *		A010 0000 to 0xA011 FFFF and 0xA012 0000 to 0xA013 FFFF
+ * - this could be less, but this is only for developer versions of the board
+ *   and no-one is going to use the NOR flash anyway.
+ *
+ * Monitor is at the beginning of the NOR-Flash, 1MB reserved. Again this is
+ * way to large, but it avoids ENV overwrite (when updating u-boot) in case
+ * size breaks the next boundary (as it has with 128k).
+ */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(1024 * 1024)
+
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	(128 * 1024)
+#define CONFIG_ENV_SIZE		(128 * 1024)
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
+
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+
+/* Hardware drivers */
+
+/*
+ * on TT-01 UART1 pins are used by Audio, so we use UART2
+ * TT-01 implements a hardware that turns off components depending on
+ * the power level. In PL=1 the RS232 transceiver is usually off,
+ * make sure that the transceiver is enabled during PL=1 for testing!
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	UART2_BASE
+
+#define CONFIG_MXC_SPI
+#define CONFIG_MXC_GPIO
+
+/* MC13783 connected to CSPI3 and SS0 */
+#define CONFIG_POWER
+#define CONFIG_POWER_SPI
+#define CONFIG_POWER_FSL
+
+#define CONFIG_FSL_PMIC_BUS		2
+#define CONFIG_FSL_PMIC_CS		0
+#define CONFIG_FSL_PMIC_CLK		1000000
+#define CONFIG_FSL_PMIC_MODE	(SPI_MODE_0 | SPI_CS_HIGH)
+#define CONFIG_FSL_PMIC_BITLEN	32
+
+#define CONFIG_RTC_MC13XXX
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+/* console is UART2 on TT-01 */
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+
+/* ethernet setup for the onboard smc9118 */
+#define CONFIG_MII
+#define CONFIG_SMC911X
+/* 16 bit, onboard ethernet, decoded via MACH-MX0 FPGA at 0x84200000 */
+#define CONFIG_SMC911X_BASE		(CS4_BASE+0x200000)
+#define CONFIG_SMC911X_16_BIT
+
+/* mmc driver */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MXC_MMC
+#define CONFIG_MXC_MCI_REGS_BASE       SDHC1_BASE_ADDR
+
+/* video support */
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_MX3
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_LOGO
+/* splash image won't work with NAND boot, use preboot script */
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_CONSOLE_EXTRA_INFO /* display additional board info */
+#define CONFIG_VGA_AS_SINGLE_DEVICE /* display is an output only device */
+
+/* allow stdin, stdout and stderr variables to redirect output */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SILENT_CONSOLE		/* UARTs used externally (release) */
+#define CONFIG_SYS_DEVICE_NULLDEV	/* allow console to be turned off */
+#define CONFIG_PREBOOT
+
+/* allow decompressing max. 4MB */
+#define CONFIG_VIDEO_BMP_GZIP
+/* this is not only used by cfb_console.c for the logo, but also in cmd_bmp.c */
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (4*1024*1024)
+
+/*
+ * Command definition
+ */
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_NAND
+/*
+ * #define CONFIG_CMD_NAND_LOCK_UNLOCK the NAND01... chip does not support
+ * the NAND_CMD_LOCK_STATUS command, however the NFC of i.MX31 supports
+ * a software locking scheme.
+ */
+#define CONFIG_CMD_BMP
+
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * currently a default setting for booting via script is implemented
+ *   set user to login name and serverip to tftp host, define your
+ *   boot behaviour in bootscript.loginname
+ *
+ * TT-01 board specific TFT setup (used by drivers/video/mx3fb.c)
+ *
+ *  This set-up is for the L5F30947T04 by Epson, which is
+ *   800x480, 33MHz pixel clock, 60Hz vsync, 31.6kHz hsync
+ *  sync must be set to: DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS \
+"videomode=epson\0" \
+"epson=video=ctfb:x:800,y:480,depth:16,mode:0,pclk:30076," \
+	"le:215,ri:1,up:32,lo:13,hs:7,vs:10,sync:100663296,vmode:0\0" \
+"bootcmd=dhcp bootscript.${user}; source\0"
+
+#define CONFIG_BOOTP_SERVERIP /* tftp serverip not overruled by dhcp server */
+#define CONFIG_BOOTP_SEND_HOSTNAME /* if env-var 'hostname' is set, send it */
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_HUSH_PARSER
+
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_PROMPT	"TT01> "
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
+				sizeof(CONFIG_SYS_PROMPT)+16)
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS	16
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+#define CONFIG_CMDLINE_EDITING
+
+/* MMC boot support */
+#define CONFIG_CMD_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+
+#define CONFIG_NAND_MXC
+#define CONFIG_SYS_MAX_NAND_DEVICE		1
+
+/*
+ * actually this is nothing someone wants to configure!
+ * CONFIG_SYS_NAND_BASE despite being passed to board_nand_init()
+ * is not used by the driver.
+ */
+#define CONFIG_MXC_NAND_REGS_BASE	NFC_BASE_ADDR
+#define CONFIG_SYS_NAND_BASE		NFC_BASE_ADDR
+#define CONFIG_MXC_NAND_HWECC
+
+/* the current u-boot driver does not use the nand flash setup! */
+#define CONFIG_SYS_NAND_LARGEPAGE
+/*
+ * it's not 16 bit:
+ * #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
+ *    the current u-boot mxc_nand.c tries to auto-detect, but this only
+ *    reads the boot settings during reset (which might be wrong)
+ */
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/tuxx1.h b/qemu/roms/u-boot/include/configs/tuxx1.h
new file mode 100644
index 000000000..08ead7fa4
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/tuxx1.h
@@ -0,0 +1,170 @@
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ *                    Dave Liu <daveliu@freescale.com>
+ *
+ * Copyright (C) 2007 Logic Product Development, Inc.
+ *                    Peter Barada <peterb@logicpd.com>
+ *
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ *                    Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * (C) Copyright 2008
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * (C) Copyright 2010-2013
+ * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
+ * Holger Brunck,  Keymile GmbH, holger.bruncl@keymile.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#if defined(CONFIG_KMSUPX5)
+#define CONFIG_KM_BOARD_NAME	"kmsupx5"
+#define CONFIG_HOSTNAME		kmsupx5
+#elif defined(CONFIG_TUGE1)
+#define CONFIG_KM_BOARD_NAME	"tuge1"
+#define CONFIG_HOSTNAME		tuge1
+#elif defined(CONFIG_TUXX1)	/* TUXX1 board (tuxa1/tuda1) specific */
+#define CONFIG_KM_BOARD_NAME	"tuxx1"
+#define CONFIG_HOSTNAME		tuxx1
+#elif defined(CONFIG_KMOPTI2)
+#define CONFIG_KM_BOARD_NAME	"kmopti2"
+#define CONFIG_HOSTNAME		kmopti2
+#else
+#error ("Board not supported")
+#endif
+
+#define	CONFIG_SYS_TEXT_BASE	0xF0000000
+
+/* include common defines/options for all 8321 Keymile boards */
+#include "km/km8321-common.h"
+
+#define CONFIG_SYS_APP1_BASE	0xA0000000    /* PAXG */
+#define	CONFIG_SYS_APP1_SIZE	256 /* Megabytes */
+#if defined(CONFIG_TUXX1) || defined(CONFIG_KMOPTI2)
+#define CONFIG_SYS_APP2_BASE	0xB0000000    /* PINC3 */
+#define	CONFIG_SYS_APP2_SIZE	256 /* Megabytes */
+#endif
+
+/*
+ * Init Local Bus Memory Controller:
+ *				      Device on
+ * Bank Bus     Machine PortSz  Size  TUDA1  TUXA1  TUGE1  KMSUPX4 KMOPTI2
+ * ---- ---     ------- ------  ----- ---------------------------------------
+ *  2   Local   GPCM    8 bit  256MB  PAXG  LPXF   PAXI     LPXF   PAXE
+ *  3   Local   GPCM    8 bit  256MB  PINC3 PINC2  unused  unused  OPI2(16 bit)
+ *
+ */
+
+/*
+ * Configuration for C2 on the local bus
+ */
+/* Window base at flash base */
+#define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_APP1_BASE
+/* Window size: 256 MB */
+#define CONFIG_SYS_LBLAWAR2_PRELIM	(LBLAWAR_EN | LBLAWAR_256MB)
+
+#define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_APP1_BASE | \
+				 BR_PS_8 | \
+				 BR_MS_GPCM | \
+				 BR_V)
+
+#define CONFIG_SYS_OR2_PRELIM	(MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \
+				 OR_GPCM_CSNT | \
+				 OR_GPCM_ACS_DIV4 | \
+				 OR_GPCM_SCY_2 | \
+				 OR_GPCM_TRLX_SET | \
+				 OR_GPCM_EHTR_CLEAR | \
+				 OR_GPCM_EAD)
+#if defined(CONFIG_TUXX1)
+/*
+ * Configuration for C3 on the local bus
+ */
+/* Access window base at PINC3 base */
+#define CONFIG_SYS_LBLAWBAR3_PRELIM	CONFIG_SYS_APP2_BASE
+/* Window size: 256 MB */
+#define CONFIG_SYS_LBLAWAR3_PRELIM	(LBLAWAR_EN | LBLAWAR_256MB)
+
+#define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_APP2_BASE | \
+				 BR_PS_8 |		\
+				 BR_MS_GPCM |		\
+				 BR_V)
+
+#define CONFIG_SYS_OR3_PRELIM	(MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
+				 OR_GPCM_CSNT |	\
+				 OR_GPCM_ACS_DIV2 | \
+				 OR_GPCM_SCY_2 | \
+				 OR_GPCM_TRLX_SET | \
+				 OR_GPCM_EHTR_CLEAR)
+
+#define CONFIG_SYS_MAMR		(MxMR_GPL_x4DIS | \
+				 0x0000c000 | \
+				 MxMR_WLFx_2X)
+#endif
+
+#if defined(CONFIG_KMOPTI2)
+/*
+ * Configuration for C3 on the local bus
+ */
+#define CONFIG_SYS_LBLAWBAR3_PRELIM	CONFIG_SYS_APP2_BASE
+#define CONFIG_SYS_LBLAWAR3_PRELIM	(LBLAWAR_EN | LBLAWAR_256MB)
+#define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_APP2_BASE | \
+				 BR_PS_16 |		\
+				 BR_MS_GPCM |		\
+				 BR_V)
+#define CONFIG_SYS_OR3_PRELIM	(MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
+				 OR_GPCM_SCY_4 | \
+				 OR_GPCM_TRLX_CLEAR | \
+				 OR_GPCM_EHTR_CLEAR)
+#endif
+
+/*
+ * MMU Setup
+ */
+/* APP1: icache cacheable, but dcache-inhibit and guarded */
+#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_APP1_BASE | \
+				 BATL_PP_RW | \
+				 BATL_MEMCOHERENCE)
+/* 512M should also include APP2... */
+#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_APP1_BASE | \
+				 BATU_BL_256M | \
+				 BATU_VS | \
+				 BATU_VP)
+#define CONFIG_SYS_DBAT5L	(CONFIG_SYS_APP1_BASE | \
+				 BATL_PP_RW | \
+				 BATL_CACHEINHIBIT | \
+				 BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
+
+#if defined(CONFIG_TUGE1) || defined(CONFIG_KMSUPX5)
+#define CONFIG_SYS_IBAT6L	(0)
+#define CONFIG_SYS_IBAT6U	(0)
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#else
+/* APP2:  icache cacheable, but dcache-inhibit and guarded */
+#define CONFIG_SYS_IBAT6L	(CONFIG_SYS_APP2_BASE | \
+				 BATL_PP_RW | \
+				 BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U	(CONFIG_SYS_APP2_BASE | \
+				 BATU_BL_256M | \
+				 BATU_VS | \
+				 BATU_VP)
+#define CONFIG_SYS_DBAT6L	(CONFIG_SYS_APP2_BASE | \
+				 BATL_PP_RW | \
+				 BATL_CACHEINHIBIT | \
+				 BATL_GUARDEDSTORAGE)
+#endif
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
+
+#define CONFIG_SYS_IBAT7L	(0)
+#define CONFIG_SYS_IBAT7U	(0)
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/twister.h b/qemu/roms/u-boot/include/configs/twister.h
new file mode 100644
index 000000000..f24dc136c
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/twister.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2011
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * Copyright (C) 2009 TechNexion Ltd.
+ *
+ * Configuration for the Technexion twister board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "tam3517-common.h"
+
+#define MACH_TYPE_TAM3517	2818
+#define CONFIG_MACH_TYPE	MACH_TYPE_TAM3517
+
+#define CONFIG_TAM3517_SW3_SETTINGS
+#define CONFIG_XR16L2751
+
+#define CONFIG_BOOTDELAY	10
+
+#define CONFIG_BOOTFILE		"uImage"
+
+#define CONFIG_HOSTNAME twister
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_PROMPT		"twister => "
+
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_16_BIT
+#define CONFIG_SMC911X_BASE		0x2C000000
+#define CONFIG_SMC911X_NO_EEPROM
+
+#define	CONFIG_EXTRA_ENV_SETTINGS	CONFIG_TAM3517_SETTINGS \
+	"bootcmd=run nandboot\0"
+
+/* SPL OS boot options */
+#define CONFIG_CMD_SPL
+#define CONFIG_CMD_SPL_WRITE_SIZE	0x400 /* 1024 byte */
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x00200000
+#define CONFIG_CMD_SPL_NAND_OFS	(CONFIG_SYS_NAND_SPL_KERNEL_OFFS+\
+						0x600000)
+#define CONFIG_SPL_OS_BOOT
+
+#define CONFIG_SYS_SPL_ARGS_ADDR	(PHYS_SDRAM_1 + 0x100)
+#define CONFIG_SPL_BOARD_INIT
+
+/* gpio 55 is used as SPL_OS_BOOT_KEY */
+#define CONFIG_OMAP3_GPIO_2
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/tx25.h b/qemu/roms/u-boot/include/configs/tx25.h
new file mode 100644
index 000000000..5ac6e6441
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/tx25.h
@@ -0,0 +1,174 @@
+/*
+ * (C) Copyright 2009 DENX Software Engineering
+ * Author: John Rigby <jrigby@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+
+/*
+ * KARO TX25 board - SoC Configuration
+ */
+#define CONFIG_MX25
+#define CONFIG_MX25_CLK32		32000	/* OSC32K frequency */
+#define CONFIG_SYS_TIMER_RATE		CONFIG_MX25_CLK32
+#define CONFIG_SYS_TIMER_COUNTER	\
+	(&((struct gpt_regs *)IMX_GPT1_BASE)->counter)
+
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* 256 kB for U-Boot */
+
+#define CONFIG_SPL
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SPL_LDSCRIPT		"arch/$(ARCH)/cpu/u-boot-spl.lds"
+#define CONFIG_SPL_MAX_SIZE		2048
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+
+#define CONFIG_SPL_TEXT_BASE		0x810c0000
+#define CONFIG_SYS_TEXT_BASE		0x81200000
+
+#ifndef MACH_TYPE_TX25
+#define MACH_TYPE_TX25	2177
+#endif
+
+#define CONFIG_MACH_TYPE MACH_TYPE_TX25
+
+#ifdef CONFIG_SPL_BUILD
+/* Start copying real U-boot from the second page */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	CONFIG_SPL_PAD_TO
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x30000
+
+#define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST
+
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_SIZE		(128 * 1024 * 1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
+#else
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/*
+ * Memory Info
+ */
+/* malloc() len */
+#define CONFIG_SYS_MALLOC_LEN		(1 << 20)	/* 1 MiB */
+/*
+ * Board has 2 32MB banks of DRAM but there is a bug when using
+ * both so only the first is configured
+ */
+#define CONFIG_NR_DRAM_BANKS	1
+
+#define PHYS_SDRAM_1		0x80000000
+#define PHYS_SDRAM_1_SIZE	0x02000000
+#if (CONFIG_NR_DRAM_BANKS == 2)
+#define PHYS_SDRAM_2		0x90000000
+#define PHYS_SDRAM_2_SIZE	0x02000000
+#endif
+/* 8MB DRAM test */
+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
+#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_1+0x0800000)
+
+/*
+ * Serial Info
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	UART1_BASE
+#define CONFIG_CONS_INDEX	1	/* use UART0 for console */
+#define CONFIG_BAUDRATE		115200	/* Default baud rate */
+
+#define CONFIG_MXC_GPIO
+
+/*
+ * Flash & Environment
+ */
+/* No NOR flash present */
+#define CONFIG_SYS_NO_FLASH
+#define	CONFIG_ENV_IS_IN_NAND
+#define	CONFIG_ENV_OFFSET	CONFIG_SYS_MONITOR_LEN
+#define CONFIG_ENV_SIZE		(128 * 1024)	/* 128 kB NAND block size */
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+
+/* NAND */
+#define CONFIG_NAND_MXC
+#define CONFIG_MXC_NAND_REGS_BASE	(0xBB000000)
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		(0xBB000000)
+#define CONFIG_JFFS2_NAND
+#define CONFIG_MXC_NAND_HWECC
+#define CONFIG_SYS_NAND_LARGEPAGE
+
+/* U-Boot general configuration */
+#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size  */
+/* Print buffer sz */
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
+		sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	32	/* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+
+/* U-Boot commands */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_CACHE
+
+/*
+ * Ethernet
+ */
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_MXC_PHYADDR		0x1f
+#define CONFIG_MII
+#define CONFIG_CMD_NET
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BOOTDELAY	5
+
+#define CONFIG_LOADADDR		0x81000000	/* loadaddr env var */
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs}"				\
+		" console=ttymxc0,${baudrate}\0"			\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
+	"addmisc=setenv bootargs ${bootargs}\0"				\
+	"u-boot=tx25/u-boot.bin\0"					\
+	"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0"		\
+	"hostname=tx25\0"						\
+	"bootfile=tx25/uImage\0"					\
+	"rootpath=/opt/eldk/arm\0"					\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
+		"run nfsargs addip addtty addmtd addmisc;"		\
+		"bootm\0"						\
+	"bootcmd=run net_nfs\0"						\
+	"load=tftp ${loadaddr} ${u-boot}\0"				\
+	"update=nand erase 0 40000;nand write ${loadaddr} 0 40000\0"	\
+	"upd=run load update\0"						\
+
+/* additions for new relocation code, must be added to all boards */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR		(IMX_RAM_BASE + IMX_RAM_SIZE)
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/u8500_href.h b/qemu/roms/u-boot/include/configs/u8500_href.h
new file mode 100644
index 000000000..8d7970a37
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/u8500_href.h
@@ -0,0 +1,212 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2009
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_U8500
+
+#define CONFIG_SYS_MEMTEST_START	0x00000000
+#define CONFIG_SYS_MEMTEST_END	0x1FFFFFFF
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+
+/*
+ * Size of malloc() pool
+ */
+#ifdef CONFIG_BOOT_SRAM
+#define CONFIG_ENV_SIZE		(32*1024)
+#define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + 64*1024)
+#else
+#define CONFIG_ENV_SIZE		(128*1024)
+#define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + 256*1024)
+#endif
+
+/*
+ * PL011 Configuration
+ */
+#define CONFIG_PL011_SERIAL
+#define CONFIG_PL011_SERIAL_RLCR
+#define CONFIG_PL011_SERIAL_FLUSH_ON_INIT
+
+/*
+ * U8500 UART registers base for 3 serial devices
+ */
+#define CFG_UART0_BASE		0x80120000
+#define CFG_UART1_BASE		0x80121000
+#define CFG_UART2_BASE		0x80007000
+#define CFG_SERIAL0		CFG_UART0_BASE
+#define CFG_SERIAL1		CFG_UART1_BASE
+#define CFG_SERIAL2		CFG_UART2_BASE
+#define CONFIG_PL011_CLOCK	38400000
+#define CONFIG_PL01x_PORTS	{ (void *)CFG_SERIAL0, (void *)CFG_SERIAL1, \
+				  (void *)CFG_SERIAL2 }
+#define CONFIG_CONS_INDEX	2
+#define CONFIG_BAUDRATE		115200
+
+/*
+ * Devices and file systems
+ */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DOS_PARTITION
+
+/*
+ * Commands
+ */
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_CONSOLE
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_SOURCE
+#define CONFIG_CMD_I2C
+
+#ifndef CONFIG_BOOTDELAY
+#define CONFIG_BOOTDELAY	1
+#endif
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+#undef CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND	"run emmcboot"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"verify=n\0"							\
+	"loadaddr=0x00100000\0"						\
+	"console=ttyAMA2,115200n8\0"					\
+	"memargs256=mem=96M@0 mem_modem=32M@96M mem=30M@128M "		\
+		"pmem=22M@158M pmem_hwb=44M@180M mem_mali=32@224M\0"	\
+	"memargs512=mem=96M@0 mem_modem=32M@96M mem=44M@128M "		\
+		"pmem=22M@172M mem=30M@194M mem_mali=32M@224M "		\
+		"pmem_hwb=54M@256M mem=202M@310M\0"			\
+	"commonargs=setenv bootargs cachepolicy=writealloc noinitrd "	\
+		"init=init "						\
+		"board_id=${board_id} "					\
+		"logo.${logo} "						\
+		"startup_graphics=${startup_graphics}\0"		\
+	"emmcargs=setenv bootargs ${bootargs} "				\
+		"root=/dev/mmcblk0p2 "					\
+		"rootdelay=1\0"						\
+	"addcons=setenv bootargs ${bootargs} "				\
+		"console=${console}\0"					\
+	"emmcboot=echo Booting from eMMC ...; "				\
+		"run commonargs emmcargs addcons memargs;"		\
+		"mmc read 0 ${loadaddr} 0xA0000 0x4000;"		\
+		"bootm ${loadaddr}\0"					\
+	"flash=mmc init 1;fatload mmc 1 ${loadaddr} flash.scr;"		\
+		"source ${loadaddr}\0"					\
+	"loaduimage=mmc init 1;fatload mmc 1 ${loadaddr} uImage\0"	\
+	"usbtty=cdc_acm\0"						\
+	"stdout=serial,usbtty\0"					\
+	"stdin=serial,usbtty\0"						\
+	"stderr=serial,usbtty\0"
+
+/*
+ * Miscellaneous configurable options
+ */
+
+#define CONFIG_SYS_LONGHELP			/* undef to save memory     */
+#define CONFIG_SYS_PROMPT	"U8500 $ "	/* Monitor Command Prompt   */
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size  */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE \
+					+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	32	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */
+
+#undef	CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+#define CONFIG_SYS_LOAD_ADDR		0x00100000 /* default load address */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE
+
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_CMDLINE_EDITING
+
+#define CONFIG_SETUP_MEMORY_TAGS	2
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs  */
+
+/*
+ * I2C
+ */
+#define CONFIG_U8500_I2C
+#undef	CONFIG_HARD_I2C			/* I2C with hardware support */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_I2C_SLAVE		0	/* slave addr of controller */
+#define CONFIG_SYS_U8500_I2C0_BASE		0x80004000
+#define CONFIG_SYS_U8500_I2C1_BASE		0x80122000
+#define CONFIG_SYS_U8500_I2C2_BASE		0x80128000
+#define CONFIG_SYS_U8500_I2C3_BASE		0x80110000
+#define CONFIG_SYS_U8500_I2C_BUS_MAX		4
+
+#define CONFIG_SYS_I2C_GPIOE_ADDR	0x42	/* GPIO expander chip addr */
+#define CONFIG_TC35892_GPIO
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM_1			0x00000000	/* DDR-SDRAM Bank #1 */
+#define PHYS_SDRAM_SIZE_1		0x20000000	/* 512 MB */
+
+/*
+ * additions for new relocation code
+ */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_SIZE	0x100000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_SDRAM_BASE + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SYS_GBL_DATA_OFFSET
+
+/* landing address before relocation */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE            0x0
+#endif
+
+/*
+ * MMC related configs
+ * NB Only externa SD slot is currently supported
+ */
+#define MMC_BLOCK_SIZE			512
+#define CONFIG_ARM_PL180_MMCI
+#define CONFIG_ARM_PL180_MMCI_BASE	0x80126000	/* MMC base for 8500  */
+#define CONFIG_ARM_PL180_MMCI_CLOCK_FREQ 6250000
+#define CONFIG_MMC_DEV_NUM		1
+
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SAVEENV	/* CMD_ENV is obsolete but used in env_emmc.c */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET		0x13F80000
+#define CONFIG_SYS_MMC_ENV_DEV          0               /* SLOT2: eMMC */
+
+/*
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * base register values for U8500
+ */
+#define CFG_PRCMU_BASE		0x80157000	/* Power, reset and clock
+						   management unit */
+#define CFG_FSMC_BASE		0x80000000	/* FSMC Controller */
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/uc100.h b/qemu/roms/u-boot/include/configs/uc100.h
new file mode 100644
index 000000000..cad897f70
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/uc100.h
@@ -0,0 +1,482 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC860		1
+#define CONFIG_MPC860T		1
+#define CONFIG_MPC862		1       /* enable 862 since the         */
+#define CONFIG_MPC857		1       /* 857 is a variant of the 862  */
+
+#define CONFIG_UC100		1	/* ...on a UC100 module	        */
+
+#define	CONFIG_SYS_TEXT_BASE	0x40700000
+
+#define MPC8XX_FACT		4		/* Multiply by 4	*/
+#define MPC8XX_XIN		25000000	/* 25.0 MHz in		*/
+#define CONFIG_8xx_GCLK_FREQ	(MPC8XX_FACT * MPC8XX_XIN)
+				    /* define if cant' use get_gclk_freq */
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
+
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+
+#define	CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
+		"bootm\0"						\
+	"rootpath=/opt/eldk/ppc_8xx\0"					\
+	"bootfile=/tftpboot/uc100/uImage\0"				\
+	"kernel_addr=40000000\0"					\
+	"ramdisk_addr=40100000\0"					\
+	"load=tftp 100000 /tftpboot/uc100/u-boot.bin\0"			\
+	"update=protect off 40700000 4073ffff;era 40700000 4073ffff;"	\
+		"cp.b 100000 40700000 ${filesize};"			\
+		"setenv filesize;saveenv\0"				\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#undef CONFIG_STATUS_LED                /* no status-led                */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#undef CONFIG_RTC_MPC8xx
+#define CONFIG_SYS_I2C_RTC_ADDR	0x51	/* PCF8563 RTC			*/
+#define CONFIG_RTC_PCF8563		/* use Philips PCF8563 RTC	*/
+
+/*
+ * Power On Self Test support
+ */
+#define CONFIG_POST	      ( CONFIG_SYS_POST_CACHE		| \
+				CONFIG_SYS_POST_MEMORY		| \
+				CONFIG_SYS_POST_CPU		| \
+				CONFIG_SYS_POST_UART		| \
+				CONFIG_SYS_POST_SPR )
+#undef  CONFIG_POST
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SNTP
+
+#ifdef CONFIG_POST
+#define CONFIG_CMD_DIAG
+#endif
+
+
+#define CONFIG_NETCONSOLE
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+
+#if 0
+#define	CONFIG_SYS_HUSH_PARSER		1	/* use "hush" command parser	*/
+#endif
+
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#else
+#define	CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
+#endif
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define CONFIG_AUTO_COMPLETE	1       /* add autocompletion support   */
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xF0000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE+0x00700000) /* resetvec fff00100*/
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*-----------------------------------------------------------------------
+ * Address accessed to reset the board - must not be mapped/assigned
+ */
+#define CONFIG_SYS_RESET_ADDRESS       0x90000000
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_FLASH_CFI				/* The flash is CFI compatible  */
+#define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver        */
+#define CONFIG_SYS_FLASH_CFI_AMD_RESET	1		/* AMD RESET for STM 29W320DB!  */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#define	CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector		*/
+#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_FRC | SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ */
+#define CONFIG_SYS_PLPRCR	(((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) |	\
+				PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	0x00000000
+#define CONFIG_SYS_SCCR        (SCCR_EBDF11)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_IDE_PREINIT	1	/* Use preinit IDE hook */
+#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xFF800000	/* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+#define CONFIG_SYS_OR_TIMING_FLASH	(0x00000d24)
+
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+#define CONFIG_SYS_BR1_PRELIM  0x00000081  /* Chip select for SDRAM (32 Bit, UPMA) */
+#define CONFIG_SYS_OR1_PRELIM  0xfc000a00
+#define CONFIG_SYS_BR2_PRELIM  0x80000001  /* Chip select for SRAM (32 Bit, GPCM) */
+#define CONFIG_SYS_OR2_PRELIM  0xfff00d24
+#define CONFIG_SYS_BR3_PRELIM  0x80600401  /* Chip select for Display (8 Bit, GPCM) */
+#define CONFIG_SYS_OR3_PRELIM  0xffff8f44
+#define CONFIG_SYS_BR4_PRELIM  0xc05108c1  /* Chip select for Interbus MPM (16 Bit, UPMB) */
+#define CONFIG_SYS_OR4_PRELIM  0xffff0300
+#define CONFIG_SYS_BR5_PRELIM  0xc0500401  /* Chip select for Interbus Status (8 Bit, GPCM) */
+#define CONFIG_SYS_OR5_PRELIM  0xffff8db0
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ *	gclk	  CPU clock (not bus clock!)
+ *	Trefresh  Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096  Rows from SDRAM example configuration
+ * 1000  factor s -> ms
+ *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
+ *    4  Number of refresh cycles per period
+ *   64  Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ *  50 MHz =>  50.000.000 / Divider =  98
+ *  66 Mhz =>  66.000.000 / Divider = 129
+ *  80 Mhz =>  80.000.000 / Divider = 156
+ * 100 Mhz => 100.000.000 / Divider = 195
+ */
+
+#define CONFIG_SYS_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CONFIG_SYS_MAMR_PTA	98
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ */
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+#define	CONFIG_SYS_MAMR_VAL	0x30904114	/* for SDRAM */
+#define	CONFIG_SYS_MBMR_VAL	0xff001111	/* for Interbus-MPM */
+
+/*-----------------------------------------------------------------------
+ * I2C stuff
+ */
+
+/* enable I2C and select the hardware/software driver */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED	93000 /* 93 kHz is supposed to work */
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PB_SCL		0x00000020	/* PB 26 */
+#define PB_SDA		0x00000010	/* PB 27 */
+
+#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
+#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
+#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
+#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
+#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
+#define I2C_DELAY	udelay(2)	/* 1/4 I2C clock duration */
+
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (24C164)
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x58	/* EEPROM AT24C164		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* takes up to 10 msec	*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+
+#define	CONFIG_FEC_ENET		1	/* use FEC ethernet  */
+#define FEC_ENET
+#define CONFIG_MII
+#define CONFIG_MII_INIT		1
+#define CONFIG_SYS_DISCOVER_PHY	1
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/uc101.h b/qemu/roms/u-boot/include/configs/uc101.h
new file mode 100644
index 000000000..f93dea7b3
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/uc101.h
@@ -0,0 +1,103 @@
+/*
+ * (C) Copyright 2003-2009
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_UC101		1	/* UC101 board		*/
+#define CONFIG_HOSTNAME		uc101
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xFFF00000
+#endif
+#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds"
+
+#include "manroland/common.h"
+#include "manroland/mpc5200-common.h"
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps	*/
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Flash configuration
+ */
+#define CONFIG_SYS_MAX_FLASH_SECT	140
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_SECT_SIZE	0x10000
+
+/*
+ * Memory map
+ */
+#define	CONFIG_SYS_IB_MASTER		0xc0510000	/* CS 6 */
+#define CONFIG_SYS_IB_EPLD		0xc0500000	/* CS 7 */
+
+/* SRAM */
+#define CONFIG_SYS_SRAM_SIZE	0x200000
+
+/*
+ * GPIO configuration
+ */
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x4d558044
+
+#define CONFIG_SYS_MEMTEST_START	0x00300000
+#define CONFIG_SYS_MEMTEST_END		0x00f00000
+
+#define CONFIG_SYS_LOAD_ADDR		0x300000
+
+#define CONFIG_SYS_BOOTCS_CFG		0x00045D00
+
+/* 8Mbit SRAM @0x80100000 */
+#define CONFIG_SYS_CS1_SIZE		0x00200000
+#define CONFIG_SYS_CS1_CFG		0x21D00
+
+/* Display H1, Status Inputs, EPLD @0x80600000 8 Bit */
+#define CONFIG_SYS_CS3_START		CONFIG_SYS_DISPLAY_BASE
+#define CONFIG_SYS_CS3_SIZE		0x00000100
+#define CONFIG_SYS_CS3_CFG		0x00081802
+
+/* Interbus Master 16 Bit */
+#define CONFIG_SYS_CS6_START		CONFIG_SYS_IB_MASTER
+#define CONFIG_SYS_CS6_SIZE		0x00010000
+#define CONFIG_SYS_CS6_CFG		0x00FF3500
+
+/* Interbus EPLD 8 Bit */
+#define CONFIG_SYS_CS7_START		CONFIG_SYS_IB_EPLD
+#define CONFIG_SYS_CS7_SIZE		0x00010000
+#define CONFIG_SYS_CS7_CFG		0x00081800
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 2 drives per IDE bus*/
+
+/*---------------------------------------------------------------------*/
+/* Display addresses						       */
+/*---------------------------------------------------------------------*/
+#define CONFIG_SYS_DISP_CHR_RAM	(CONFIG_SYS_DISPLAY_BASE + 0x38)
+#define CONFIG_SYS_DISP_CWORD		(CONFIG_SYS_DISPLAY_BASE + 0x30)
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/udoo.h b/qemu/roms/u-boot/include/configs/udoo.h
new file mode 100644
index 000000000..a0306de6a
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/udoo.h
@@ -0,0 +1,234 @@
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for Udoo board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/gpio.h>
+#include <linux/sizes.h>
+
+#define CONFIG_MX6
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define MACH_TYPE_UDOO		4800
+#define CONFIG_MACH_TYPE	MACH_TYPE_UDOO
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(2 * SZ_1M)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART2_BASE
+
+/* SATA Configs */
+
+#define CONFIG_CMD_SATA
+#ifdef CONFIG_CMD_SATA
+#define CONFIG_DWC_AHSATA
+#define CONFIG_SYS_SATA_MAX_DEVICE	1
+#define CONFIG_DWC_AHSATA_PORT_ID	0
+#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
+#define CONFIG_LBA48
+#define CONFIG_LIBATA
+#endif
+
+/* Network support */
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE                    ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE             RGMII
+#define CONFIG_ETHPRIME                 "FEC"
+#define CONFIG_FEC_MXC_PHYADDR          6
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9031
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+
+/* Command definition */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_CMD_BMODE
+#define CONFIG_CMD_SETEXPR
+
+#define CONFIG_BOOTDELAY		3
+
+#define CONFIG_SYS_MEMTEST_START	0x10000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 500 * SZ_1M)
+#define CONFIG_LOADADDR			0x12000000
+#define CONFIG_SYS_TEXT_BASE		0x17800000
+
+/* MMC Configuration */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_DEFAULT_FDT_FILE		"imx6q-udoo.dtb"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"image=zImage\0" \
+	"console=ttymxc1\0" \
+	"splashpos=m,m\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"fdt_addr=0x18000000\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"mmcdev=0\0" \
+	"mmcpart=1\0" \
+	"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
+	"update_sd_firmware_filename=u-boot.imx\0" \
+	"update_sd_firmware=" \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"if mmc dev ${mmcdev}; then "	\
+			"if ${get_cmd} ${update_sd_firmware_filename}; then " \
+				"setexpr fw_sz ${filesize} / 0x200; " \
+				"setexpr fw_sz ${fw_sz} + 1; "	\
+				"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
+			"fi; "	\
+		"fi\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs " \
+	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+		"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	   "mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "else run netboot; " \
+			   "fi; " \
+		   "fi; " \
+	   "else run netboot; fi"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT	       "=> "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE		256
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	       16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+#define CONFIG_CMDLINE_EDITING
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_SIZE			(8 * 1024)
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET		(6 * 64 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+#endif
+
+#endif			       /* __CONFIG_H * */
diff --git a/qemu/roms/u-boot/include/configs/usb_a9263.h b/qemu/roms/u-boot/include/configs/usb_a9263.h
new file mode 100644
index 000000000..3c5487078
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/usb_a9263.h
@@ -0,0 +1,168 @@
+/*
+ * (C) Copyright 2007-2013
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ * Thomas Petazzoni, Free Electrons, <thomas.petazzoni@free-electrons.com>
+ * Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+ *
+ * Settings for Calao USB-A9263 board
+ *
+ * U-Boot image has to be less than 200704 bytes, otherwise at91bootstrap
+ * installed on board will not be able to load it properly.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+#include <asm/hardware.h>
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	12000000	/* 12 MHz crystal */
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_USB_A9263
+
+#define CONFIG_ARCH_CPU_INIT
+
+#define CONFIG_CMDLINE_TAG	/* enable passing of ATAGs      */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_SYS_TEXT_BASE		0x23f00000
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_AT91_GPIO
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
+#define CONFIG_USART_ID			ATMEL_ID_SYS
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_BOOTDELAY 3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_ITEST
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NAND
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
+#define CONFIG_SYS_SDRAM_SIZE		0x04000000
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+/* DataFlash */
+#define CONFIG_ATMEL_DATAFLASH_SPI
+#define CONFIG_HAS_DATAFLASH
+#define CONFIG_SYS_SPI_WRITE_TOUT		(5*CONFIG_SYS_HZ)
+#define CONFIG_SYS_MAX_DATAFLASH_BANKS		1
+#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000
+#define AT91_SPI_CLK				8000000
+#define DATAFLASH_TCSS				(0x1a << 16)
+#define DATAFLASH_TCHS				(0x1 << 24)
+
+/* no NOR flash */
+#define CONFIG_SYS_NO_FLASH
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE		1
+#define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN		GPIO_PIN_PD(15)
+#define CONFIG_SYS_NAND_READY_PIN		GPIO_PIN_PA(22)
+#endif
+
+#define MTDPARTS_DEFAULT \
+	"mtdparts=atmel_nand:16m(kernel)ro,120m(root1),-(root2)"
+
+/* Ethernet */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_RETRY_COUNT			20
+#define CONFIG_AT91_WANTS_COMMON_PHY
+
+/* USB */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00a00000
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9263"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_FAT
+#endif
+
+#define CONFIG_SYS_LOAD_ADDR			0x22000000
+
+#define CONFIG_SYS_MEMTEST_START		CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END			0x23e00000
+
+/* bootstrap + u-boot + env in dataflash on CS0 */
+#define CONFIG_ENV_IS_IN_DATAFLASH
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x4000)
+#define CONFIG_ENV_OFFSET	0x2000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \
+				 CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_BOOTCOMMAND	"nboot 21000000 0"
+#define CONFIG_BOOTARGS		"console=ttyS0,115200 " \
+	"root=/dev/mtdblock1 " \
+	"mtdparts=" MTDPARTS_DEFAULT " " \
+	"rw rootfstype=jffs2"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+
+#define CONFIG_SYS_PROMPT		"U-Boot> "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					 sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_LONGHELP
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN	ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/utx8245.h b/qemu/roms/u-boot/include/configs/utx8245.h
new file mode 100644
index 000000000..5be62ecb2
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/utx8245.h
@@ -0,0 +1,408 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002
+ * Gregory E. Allen, gallen@arlut.utexas.edu
+ * Matthew E. Karger, karger@arlut.utexas.edu
+ * Applied Research Laboratories, The University of Texas at Austin
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ *
+ * Configuration settings for the utx8245 board.
+ *
+ */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC8245		1
+#define CONFIG_UTX8245		1
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
+
+#define DEBUG				1
+
+#define CONFIG_IDENT_STRING     " [UTX5] "
+
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		57600
+
+#define CONFIG_BOOTDELAY	2
+#define CONFIG_AUTOBOOT_PROMPT	"autoboot in %d seconds\n", bootdelay
+#define CONFIG_BOOTCOMMAND	"run nfsboot"	/* autoboot command	*/
+#define CONFIG_BOOTARGS		"root=/dev/ram console=ttyS0,57600" /* RAMdisk */
+#define CONFIG_ETHADDR		00:AA:00:14:00:05	/* UTX5 */
+#define CONFIG_SERVERIP		10.8.17.105	/* Spree */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"kernel_addr=FFA00000\0" \
+	"ramdisk_addr=FF800000\0" \
+	"u-boot_startaddr=FFB00000\0" \
+	"u-boot_endaddr=FFB2FFFF\0" \
+	"nfsargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/nfs rw \
+nfsroot=${nfsrootip}:${rootpath} ip=dhcp\0" \
+	"ramargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/ram0\0" \
+	"smargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/mtdblock1 ro\0" \
+	"fwargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/sda2 ro\0" \
+	"nfsboot=run nfsargs;bootm ${kernel_addr}\0" \
+	"ramboot=run ramargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \
+	"smboot=run smargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \
+	"fwboot=run fwargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \
+	"update_u-boot=tftp ${loadaddr} /bdi2000/u-boot.bin;protect off \
+${u-boot_startaddr} ${u-boot_endaddr};era ${u-boot_startaddr} \
+${u-boot_endaddr};cp.b ${loadaddr} ${u-boot_startaddr} ${filesize};\
+protect on ${u-boot_startaddr} ${u-boot_endaddr}"
+
+#define CONFIG_ENV_OVERWRITE
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_CONSOLE
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_DATE
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
+#define CONFIG_SYS_CBSIZE	256				/* Console I/O Buffer Size	*/
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_LOAD_ADDR	0x00100000	/* Default load address		*/
+
+
+/*-----------------------------------------------------------------------
+ * PCI configuration
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_PCI				/* include pci support		*/
+#define	CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
+#undef CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_EEPRO100
+#define CONFIG_SYS_RX_ETH_BUFFER	8               /* use 8 rx buffer on eepro100  */
+#define CONFIG_EEPRO100_SROM_WRITE
+
+#define PCI_ENET0_IOADDR	0xF0000000
+#define PCI_ENET0_MEMADDR	0xF0000000
+
+#define PCI_FIREWIRE_IOADDR		0xF1000000
+#define PCI_FIREWIRE_MEMADDR	0xF1000000
+/*
+#define PCI_ENET0_IOADDR	0xFE000000
+#define PCI_ENET0_MEMADDR	0x80000000
+
+#define PCI_FIREWIRE_IOADDR	0x81000000
+#define PCI_FIREWIRE_MEMADDR	0x81000000
+*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE	    0x00000000
+#define CONFIG_SYS_MAX_RAM_SIZE    0x10000000	/* 256MB  */
+/*#define CONFIG_SYS_VERY_BIG_RAM	1 */
+
+/* FLASH_BASE is FF800000, with 4MB on RCS0, but the reset vector
+ * is actually located at FFF00100.  Therefore, U-Boot is
+ * physically located at 0xFFB0_0000, but is also mirrored at
+ * 0xFFF0_0000.
+ */
+#define CONFIG_SYS_RESET_ADDRESS   0xFFF00100
+
+#define CONFIG_SYS_EUMB_ADDR	    0xFC000000
+
+#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_MONITOR_LEN	    (256 << 10) /* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN	    (128 << 10) /* Reserve 128 kB for malloc()	*/
+
+/*#define CONFIG_SYS_DRAM_TEST		1 */
+#define CONFIG_SYS_MEMTEST_START   0x00003000	/* memtest works on	0...256 MB	*/
+#define CONFIG_SYS_MEMTEST_END	    0x0ff8ffa7	/* in SDRAM, skips exception */
+										/* vectors and U-Boot */
+
+
+/*--------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area
+ *------------------------------------------------------------------*/
+#define CONFIG_SYS_INIT_DATA_SIZE    128	/* Size in bytes reserved for */
+									/* initial data */
+#define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE      0x1000
+#define CONFIG_SYS_INIT_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+/*--------------------------------------------------------------------
+ * NS16550 Configuration
+ *------------------------------------------------------------------*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+
+#if (CONFIG_CONS_INDEX == 1 || CONFIG_CONS_INDEX == 2)
+#	define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+#else
+#	define CONFIG_SYS_NS16550_CLK 33000000
+#endif
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_EUMB_ADDR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_EUMB_ADDR + 0x4600)
+#define CONFIG_SYS_NS16550_COM3	0xFF000000
+#define CONFIG_SYS_NS16550_COM4	0xFF000008
+
+/*--------------------------------------------------------------------
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ * For the detail description refer to the MPC8240 user's manual.
+ *------------------------------------------------------------------*/
+
+#define CONFIG_SYS_CLK_FREQ  33000000
+
+/*#define CONFIG_SYS_ETH_DEV_FN	     0x7800 */
+/*#define CONFIG_SYS_ETH_IOBASE	     0x00104000 */
+
+/*--------------------------------------------------------------------
+ * I2C Configuration
+ *------------------------------------------------------------------*/
+#if 1
+#define CONFIG_HARD_I2C		1		/* To enable I2C support	*/
+#define CONFIG_SYS_I2C_SPEED		400000
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#endif
+
+#define CONFIG_RTC_PCF8563	1		/* enable I2C support for */
+									/* Philips PCF8563 RTC */
+#define CONFIG_SYS_I2C_RTC_ADDR	0x51	/* Philips PCF8563 RTC address */
+
+/*--------------------------------------------------------------------
+ *	Memory Control Configuration Register values
+ *	- see sec. 4.12 of MPC8245 UM
+ *------------------------------------------------------------------*/
+
+/**** MCCR1 ****/
+#define CONFIG_SYS_ROMNAL	    0
+#define CONFIG_SYS_ROMFAL	    10		/* (tacc=70ns)*mem_freq - 2,
+									mem_freq = 100MHz */
+
+#define CONFIG_SYS_BANK7_ROW	0		/* SDRAM bank 7-0 row address */
+#define CONFIG_SYS_BANK6_ROW	0		/*	bit count */
+#define CONFIG_SYS_BANK5_ROW	0
+#define CONFIG_SYS_BANK4_ROW	0
+#define CONFIG_SYS_BANK3_ROW	0
+#define CONFIG_SYS_BANK2_ROW	0
+#define CONFIG_SYS_BANK1_ROW	2
+#define CONFIG_SYS_BANK0_ROW	2
+
+/**** MCCR2, refresh interval clock cycles ****/
+#define CONFIG_SYS_REFINT	    480	    /* 33 MHz SDRAM clock was 480 */
+
+/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */
+#define CONFIG_SYS_BSTOPRE	    1023	/* burst to precharge[0..9], */
+								/* sets open page interval */
+
+/**** MCCR3 ****/
+#define CONFIG_SYS_REFREC	    7	    /* Refresh to activate interval, trc */
+
+/**** MCCR4 ****/
+#define CONFIG_SYS_PRETOACT	    2	    /* trp */
+#define CONFIG_SYS_ACTTOPRE	    7	    /* trcd + (burst length - 1) + trdl */
+#define CONFIG_SYS_SDMODE_CAS_LAT  3	    /* SDMODE CAS latancy */
+#define CONFIG_SYS_SDMODE_WRAP	    0	    /* SDMODE wrap type, sequential */
+#define CONFIG_SYS_ACTORW		2		/* trcd min */
+#define CONFIG_SYS_DBUS_SIZE2		1		/* set for 8-bit RCS1, clear for 32,64 */
+#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
+#define CONFIG_SYS_EXTROM	    0			/* we don't need extended ROM space */
+#define CONFIG_SYS_REGDIMM	    0
+
+/* calculate according to formula in sec. 6-22 of 8245 UM */
+#define CONFIG_SYS_PGMAX           50		/* how long the 8245 retains the */
+									/* currently accessed page in memory */
+									/* was 45 */
+
+#define CONFIG_SYS_SDRAM_DSCD	0x20	/* SDRAM data in sample clock delay - note */
+								/* bits 7,6, and 3-0 MUST be 0 */
+
+#if 0
+#define CONFIG_SYS_DLL_MAX_DELAY	0x04
+#else
+#define CONFIG_SYS_DLL_MAX_DELAY	0
+#endif
+#if 0							/* need for 33MHz SDRAM */
+#define CONFIG_SYS_DLL_EXTEND	0x80
+#else
+#define CONFIG_SYS_DLL_EXTEND	0
+#endif
+#define CONFIG_SYS_PCI_HOLD_DEL 0x20
+
+
+/* Memory bank settings.
+ * Only bits 20-29 are actually used from these values to set the
+ * start/end addresses. The upper two bits will always be 0, and the lower
+ * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
+ * address. Refer to the MPC8245 user manual.
+ */
+
+#define CONFIG_SYS_BANK0_START	    0x00000000
+#define CONFIG_SYS_BANK0_END	    (CONFIG_SYS_MAX_RAM_SIZE/2 - 1)
+#define CONFIG_SYS_BANK0_ENABLE    1
+#define CONFIG_SYS_BANK1_START	    CONFIG_SYS_MAX_RAM_SIZE/2
+#define CONFIG_SYS_BANK1_END	    (CONFIG_SYS_MAX_RAM_SIZE - 1)
+#define CONFIG_SYS_BANK1_ENABLE    1
+#define CONFIG_SYS_BANK2_START	    0x3ff00000		/* not available in this design */
+#define CONFIG_SYS_BANK2_END	    0x3fffffff
+#define CONFIG_SYS_BANK2_ENABLE    0
+#define CONFIG_SYS_BANK3_START	    0x3ff00000
+#define CONFIG_SYS_BANK3_END	    0x3fffffff
+#define CONFIG_SYS_BANK3_ENABLE    0
+#define CONFIG_SYS_BANK4_START	    0x3ff00000
+#define CONFIG_SYS_BANK4_END	    0x3fffffff
+#define CONFIG_SYS_BANK4_ENABLE    0
+#define CONFIG_SYS_BANK5_START	    0x3ff00000
+#define CONFIG_SYS_BANK5_END	    0x3fffffff
+#define CONFIG_SYS_BANK5_ENABLE    0
+#define CONFIG_SYS_BANK6_START	    0x3ff00000
+#define CONFIG_SYS_BANK6_END	    0x3fffffff
+#define CONFIG_SYS_BANK6_ENABLE    0
+#define CONFIG_SYS_BANK7_START	    0x3ff00000
+#define CONFIG_SYS_BANK7_END	    0x3fffffff
+#define CONFIG_SYS_BANK7_ENABLE    0
+
+/*--------------------------------------------------------------------*/
+/* 4.4 - Output Driver Control Register */
+/*--------------------------------------------------------------------*/
+#define CONFIG_SYS_ODCR	    0xe5
+
+/*--------------------------------------------------------------------*/
+/* 4.8 - Error Handling Registers */
+/*-------------------------------CONFIG_SYS_SDMODE_BURSTLEN-------------------------------------*/
+#define CONFIG_SYS_ERRENR1	0x11	/* enable SDRAM refresh overflow error */
+
+/* SDRAM 0-256 MB */
+#define CONFIG_SYS_IBAT0L  (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+/*#define CONFIG_SYS_IBAT0L  (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_CACHEINHIBIT) */
+#define CONFIG_SYS_IBAT0U  (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* stack in dcache */
+#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+
+
+#define CONFIG_SYS_IBAT2L  (CONFIG_SYS_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT2U  (CONFIG_SYS_SDRAM_BASE + 0x10000000| BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* PCI memory */
+/*#define CONFIG_SYS_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) */
+/*#define CONFIG_SYS_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) */
+
+/*Flash, config addrs, etc. */
+#define CONFIG_SYS_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_DBAT0L  CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U  CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L  CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U  CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L  CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U  CONFIG_SYS_IBAT3U
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	    (8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_FLASH_BASE	    0xFF800000
+#define CONFIG_SYS_MAX_FLASH_BANKS	1			/* Max number of flash banks */
+
+/*	NOTE: environment is not EMBEDDED in the u-boot code.
+	It's stored in flash in its own separate sector.  */
+#define CONFIG_ENV_IS_IN_FLASH	    1
+
+#if 1	/* AMD AM29LV033C */
+#define CONFIG_SYS_MAX_FLASH_SECT	64		/* Max number of sectors in one bank */
+#define CONFIG_ENV_ADDR		0xFFBF0000	/* flash sector SA63 */
+#define CONFIG_ENV_SECT_SIZE	(64*1024)	/* Size of the Environment Sector */
+#else	/* AMD AM29LV116D */
+#define CONFIG_SYS_MAX_FLASH_SECT	35	/* Max number of sectors in one bank */
+#define CONFIG_ENV_ADDR		0xFF9FA000	/* flash sector SA33 */
+#define CONFIG_ENV_SECT_SIZE	(8*1024)	/* Size of the Environment Sector */
+#endif /* #if */
+
+#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE		/* Size of the Environment */
+#define CONFIG_ENV_OFFSET		0			/* starting right at the beginning */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Timeout for Flash Write (in ms)	*/
+
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+#undef CONFIG_SYS_RAMBOOT
+#else
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	32
+#if defined(CONFIG_CMD_KGDB)
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/v37.h b/qemu/roms/u-boot/include/configs/v37.h
new file mode 100644
index 000000000..0d01fe207
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/v37.h
@@ -0,0 +1,375 @@
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC823		1	/* This is a MPC823 CPU		*/
+#define CONFIG_V37		1	/* ...on a Marel V37 board	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0x40000000
+
+#define CONFIG_LCD
+#define CONFIG_MPC8XX_LCD
+#define CONFIG_SHARP_LQ084V1DG21
+#undef CONFIG_LCD_LOGO
+
+/*-----------------------------------------------------------------------------
+ * I2C Configuration
+ *-----------------------------------------------------------------------------
+ */
+#define CONFIG_I2C              1
+#define CONFIG_SYS_I2C_SLAVE           0x2
+
+#define	CONFIG_8xx_CONS_SMC1	1
+#undef	CONFIG_8xx_CONS_SMC2		/* Console is on SMC2		*/
+#undef	CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE		9600	/* console baudrate = 115kbps	*/
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
+#else
+#define CONFIG_BOOTDELAY	2	/* autoboot after 2 seconds	*/
+#endif
+
+#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
+#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define CONFIG_BOOTCOMMAND							\
+	"tftpboot; "								\
+	"setenv bootargs console=tty0 "                                   \
+	"root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "			\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
+	"bootm"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_CAN_DRIVER	1	/* CAN Driver support enabled	*/
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_DATE
+
+
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_CMD_MTDPARTS
+#define CONFIG_JFFS2_DEV		"nor1"
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET	0x00000000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_CMD_MTDPARTS
+#define MTDIDS_DEFAULT		"nor1=v37-1"
+#define MTDPARTS_DEFAULT	"mtdparts=v37-1:-(jffs2)"
+*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#else
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
+#endif
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xF0000000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE0		0x40000000
+#define CONFIG_SYS_FLASH_BASE1		0x60000000
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_FLASH_BASE1
+
+#if defined(DEBUG)
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#else
+#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#endif
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE0
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	35	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CONFIG_ENV_IS_IN_NVRAM	1
+#define	CONFIG_ENV_ADDR		0x80000000/* Address of Environment */
+#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+#define CONFIG_ENV_OFFSET		0
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CONFIG_SYS_SYPCR	0xFFFFFF88
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_FRC | SIUMCR_GB5E)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+/*%%%#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
+/*
+#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
+*/
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ *
+ * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
+ */
+/* up to 50 MHz we use a 1:1 clock */
+#define CONFIG_SYS_PLPRCR	( (1524 << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TMIST | PLPRCR_TEXPS )
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+/* up to 50 MHz we use a 1:1 clock */
+#define CONFIG_SYS_SCCR	(SCCR_COM00 | SCCR_TBS)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#undef	CONFIG_IDE_PCCARD		/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_PCMCIA		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0 and OR0 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #1	*/
+
+#define CONFIG_SYS_PRELIM_OR_AM	0xFE000000	/* OR addr mask */
+
+#define CONFIG_SYS_OR_TIMING_FLASH	0xF56
+
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V)
+
+#define CONFIG_SYS_OR5_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR5_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V)
+
+/*
+ * BR1 and OR1 (Battery backed SRAM)
+ */
+#define	CONFIG_SYS_BR1_PRELIM	0x80000401
+#define CONFIG_SYS_OR1_PRELIM	0xFFC00736
+
+/*
+ * BR2 and OR2 (SDRAM)
+ */
+#define SDRAM_BASE_PRELIM	0x00000000	/* SDRAM base	*/
+#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB */
+
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
+
+#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+/* Marel V37 mem setting */
+
+#define	CONFIG_SYS_BR3_CAN	0xC0000401
+#define CONFIG_SYS_OR3_CAN	0xFFFF0724
+
+/*
+#define	CONFIG_SYS_BR3_PRELIM	0xFA400001
+#define CONFIG_SYS_OR3_PRELIM	0xFFFF8910
+#define	CONFIG_SYS_BR4_PRELIM	0xFA000401
+#define CONFIG_SYS_OR4_PRELIM	0xFFFE0970
+*/
+
+/*
+ * Memory Periodic Timer Prescaler
+ */
+
+/* periodic timer for refresh */
+#define CONFIG_SYS_MAMR_PTA	97		/* start with divider for 100 MHz	*/
+
+/*
+ * Refresh clock Prescalar
+ */
+#define CONFIG_SYS_MPTPR	MPTPR_PTP_DIV16
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 10 column SDRAM */
+#define CONFIG_SYS_MAMR_10COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 |	\
+			 MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X)
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/v38b.h b/qemu/roms/u-boot/include/configs/v38b.h
new file mode 100644
index 000000000..7f6b0c7cb
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/v38b.h
@@ -0,0 +1,336 @@
+/*
+ * (C) Copyright 2003-2006 Wolfgang Denk, DENX Software Engineering,
+ * wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MPC5200			1	/* This is an MPC5200 CPU */
+#define CONFIG_V38B			1	/* ...on V38B board */
+
+#define	CONFIG_SYS_TEXT_BASE		0xFF000000
+
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000	/* ...running at 33.000000MHz */
+
+#define CONFIG_RTC_PCF8563		1	/* has PCF8563 RTC */
+#define CONFIG_MPC5200_DDR		1	/* has DDR SDRAM */
+
+#undef CONFIG_HW_WATCHDOG			/* don't use watchdog */
+
+#define CONFIG_NETCONSOLE		1
+
+#define CONFIG_BOARD_EARLY_INIT_R	1	/* do board-specific init */
+#define CONFIG_BOARD_EARLY_INIT_F	1	/* do board-specific init */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_SYS_XLB_PIPELINING		1	/* gives better performance */
+
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
+#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*
+ * DDR
+ */
+#define SDRAM_DDR		1	/* is DDR */
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE		0x018D0000
+#define SDRAM_EMODE		0x40090000
+#define SDRAM_CONTROL		0x704f0f00
+#define SDRAM_CONFIG1		0x73722930
+#define SDRAM_CONFIG2		0x47770000
+#define SDRAM_TAPDELAY		0x10000000
+
+/*
+ * PCI - no suport
+ */
+#undef CONFIG_PCI
+
+/*
+ * Partitions
+ */
+#define CONFIG_MAC_PARTITION	1
+#define CONFIG_DOS_PARTITION	1
+
+/*
+ * USB
+ */
+#define CONFIG_USB_OHCI
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_CLOCK	0x0001BBBB
+#define CONFIG_USB_CONFIG	0x00001000
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_FAT
+
+
+#define CONFIG_TIMESTAMP		/* Print image info with timestamp */
+
+/*
+ * Boot low with 16 MB Flash
+ */
+#define CONFIG_SYS_LOWBOOT		1
+#define CONFIG_SYS_LOWBOOT16		1
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds */
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"bootcmd=run net_nfs\0"						\
+	"bootdelay=3\0"							\
+	"baudrate=115200\0"						\
+	"preboot=echo;echo Type \"run flash_nfs\" to mount root "	\
+		"filesystem over NFS; echo\0"				\
+	"netdev=eth0\0"							\
+	"ramargs=setenv bootargs root=/dev/ram rw wdt=off \0"		\
+	"addip=setenv bootargs $(bootargs) "				\
+		"ip=$(ipaddr):$(serverip):$(gatewayip):"		\
+		"$(netmask):$(hostname):$(netdev):off panic=1\0"	\
+	"flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0"		\
+	"flash_self=run ramargs addip;bootm $(kernel_addr) "		\
+		"$(ramdisk_addr)\0"					\
+	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"	\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=$(serverip):$(rootpath) wdt=off\0"		\
+	"hostname=v38b\0"						\
+	"ethact=FEC\0"							\
+	"rootpath=/opt/eldk-3.1.1/ppc_6xx\0"				\
+	"update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; "	\
+		"cp.b 200000 ff000000 $(filesize);"			\
+		"prot on ff000000 ff03ffff\0"				\
+	"load=tftp 200000 $(u-boot)\0"					\
+	"netmask=255.255.0.0\0"						\
+	"ipaddr=192.168.160.18\0"					\
+	"serverip=192.168.1.1\0"					\
+	"ethaddr=00:e0:ee:00:05:2e\0"					\
+	"bootfile=/tftpboot/v38b/uImage\0"				\
+	"u-boot=/tftpboot/v38b/u-boot.bin\0"				\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run net_nfs"
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK			/* define for 133MHz speed */
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #1 or #2 */
+#define CONFIG_SYS_I2C_SPEED		100000	/* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	70
+
+/*
+ * RTC configuration
+ */
+#define CONFIG_SYS_I2C_RTC_ADDR		0x51
+
+/*
+ * Flash configuration - use CFI driver
+ */
+#define CONFIG_SYS_FLASH_CFI		1		/* Flash is CFI conformant */
+#define CONFIG_FLASH_CFI_DRIVER	1		/* Use the common driver */
+#define CONFIG_SYS_FLASH_CFI_AMD_RESET	1
+#define CONFIG_SYS_FLASH_BASE		0xFF000000
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* max num of flash banks */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_FLASH_SIZE		0x01000000	/* 16 MiB */
+#define CONFIG_SYS_MAX_FLASH_SECT	256		/* max num of sects on one chip */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1	/* flash write speed-up */
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00040000)
+#define CONFIG_ENV_SIZE		0x10000
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#define CONFIG_ENV_OVERWRITE	1
+
+/*
+ * Memory map
+ */
+#define CONFIG_SYS_MBAR		0xF0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
+
+/* Use SRAM until RAM will be available */
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* Size of used area in DPRAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128kB for malloc() */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Linux initial memory map */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC	1
+#define CONFIG_MPC5xxx_FEC_MII100
+#define CONFIG_PHY_ADDR		0x00
+#define CONFIG_MII		1
+
+/*
+ * GPIO configuration
+ */
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x90001404
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM */
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
+
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
+#if defined(CONFIG_CMD_KGDB)
+#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#endif
+
+/*
+ * Various low-level settings
+ */
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
+
+#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_CFG		0x00047801
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
+
+#define CONFIG_SYS_CS_BURST		0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE	0x33333333
+
+#define CONFIG_SYS_RESET_ADDRESS	0xff000000
+
+/*
+ * IDE/ATA (supports IDE harddisk)
+ */
+#undef CONFIG_IDE_8xx_PCCARD		/* Don't use IDE with PC Card Adapter */
+#undef CONFIG_IDE_8xx_DIRECT		/* Direct IDE not supported */
+#undef CONFIG_IDE_LED			/* LED for ide not supported */
+
+#define CONFIG_IDE_RESET		/* reset for ide supported */
+#define CONFIG_IDE_PREINIT
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus */
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus */
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
+
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)	/* data I/O offset */
+
+#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)	/* normal register accesses offset */
+
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)	/* alternate registers offset */
+
+#define CONFIG_SYS_ATA_STRIDE		4		/* Interval between registers */
+
+/*
+ * Status LED
+ */
+#define  CONFIG_STATUS_LED		/* Status LED enabled */
+#define  CONFIG_BOARD_SPECIFIC_LED	/* version has board specific leds */
+
+#define CONFIG_SYS_LED_BASE	MPC5XXX_GPT7_ENABLE	/* Timer 7 GPIO */
+#ifndef __ASSEMBLY__
+typedef unsigned int led_id_t;
+
+#define __led_toggle(_msk) \
+	do { \
+		*((volatile long *) (CONFIG_SYS_LED_BASE)) ^= (_msk); \
+	} while(0)
+
+#define __led_set(_msk, _st) \
+	do { \
+		if ((_st)) \
+			*((volatile long *) (CONFIG_SYS_LED_BASE)) &= ~(_msk); \
+		else \
+			*((volatile long *) (CONFIG_SYS_LED_BASE)) |= (_msk); \
+	} while(0)
+
+#define __led_init(_msk, st) \
+	do { \
+		*((volatile long *) (CONFIG_SYS_LED_BASE)) |= 0x34; \
+	} while(0)
+#endif /* __ASSEMBLY__ */
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/v5fx30teval.h b/qemu/roms/u-boot/include/configs/v5fx30teval.h
new file mode 100644
index 000000000..f30a0904a
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/v5fx30teval.h
@@ -0,0 +1,39 @@
+/*
+ * (C) Copyright 2008
+ *  Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ *  This work has been supported by: QTechnology  http://qtec.com/
+ * SPDX-License-Identifier:	GPL-2.0+
+*/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*CPU*/
+#define CONFIG_440		1
+#define CONFIG_XILINX_ML507	1
+#include "../board/avnet/v5fx30teval/xparameters.h"
+
+/*Mem Map*/
+#define CONFIG_SYS_SDRAM_SIZE_MB	64
+
+/*Env*/
+#define	CONFIG_ENV_IS_IN_FLASH	1
+#define	CONFIG_ENV_SIZE		0x20000
+#define	CONFIG_ENV_SECT_SIZE	0x20000
+#define CONFIG_ENV_OFFSET		0x1A0000
+#define CONFIG_ENV_ADDR		(XPAR_FLASH_MEM0_BASEADDR+CONFIG_ENV_OFFSET)
+
+/*Misc*/
+#define CONFIG_SYS_PROMPT		"v5fx30t:/# "	/* Monitor Command Prompt    */
+#define CONFIG_PREBOOT		"echo U-Boot is up and runnining;"
+
+/*Flash*/
+#define	CONFIG_SYS_FLASH_SIZE		(16*1024*1024)
+#define	CONFIG_SYS_MAX_FLASH_SECT	131
+#define MTDIDS_DEFAULT		"nor0=v5fx30t-flash"
+#define MTDPARTS_DEFAULT	"mtdparts=v5fx30t-flash:-(user)"
+
+/*Generic Configs*/
+#include <configs/xilinx-ppc440.h>
+
+#endif						/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/vct.h b/qemu/roms/u-boot/include/configs/vct.h
new file mode 100644
index 000000000..5ab4de327
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/vct.h
@@ -0,0 +1,330 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * This file contains the configuration parameters for the VCT board
+ * family:
+ *
+ * vct_premium
+ * vct_premium_small
+ * vct_premium_onenand
+ * vct_premium_onenand_small
+ * vct_platinum
+ * vct_platinum_small
+ * vct_platinum_onenand
+ * vct_platinum_onenand_small
+ * vct_platinumavc
+ * vct_platinumavc_small
+ * vct_platinumavc_onenand
+ * vct_platinumavc_onenand_small
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CPU_CLOCK_RATE			324000000 /* Clock for the MIPS core */
+#define CONFIG_SYS_MIPS_TIMER_FREQ	(CPU_CLOCK_RATE / 2)
+
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* SDRAM is initialized by the bootstrap code */
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)
+#define CONFIG_SYS_MALLOC_LEN		(1 << 20)
+#define CONFIG_SYS_BOOTPARAMS_LEN	(128 << 10)
+#define CONFIG_SYS_INIT_SP_OFFSET	0x400000
+
+#if !defined(CONFIG_VCT_NAND) && !defined(CONFIG_VCT_ONENAND)
+#define CONFIG_VCT_NOR
+#else
+#define CONFIG_SYS_NO_FLASH
+#endif
+
+/*
+ * UART
+ */
+#ifdef CONFIG_VCT_PLATINUMAVC
+#define UART_1_BASE		0xBDC30000
+#else
+#define UART_1_BASE		0xBF89C000
+#endif
+
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#define CONFIG_SYS_NS16550_COM1		UART_1_BASE
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550_CLK		921600
+#define CONFIG_BAUDRATE			115200
+
+/*
+ * SDRAM
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CONFIG_SYS_MBYTES_SDRAM		128
+#define CONFIG_SYS_MEMTEST_START	0x80200000
+#define CONFIG_SYS_MEMTEST_END		0x80400000
+#define CONFIG_SYS_LOAD_ADDR		0x80400000	/* default load address */
+
+#if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)
+/*
+ * SMSC91C11x Network Card
+ */
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_BASE	0x00000000
+#define CONFIG_SMC911X_32_BIT
+#define CONFIG_NET_RETRY_COUNT		20
+#endif
+
+/*
+ * Commands
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+
+/*
+ * Only Premium/Platinum have ethernet support right now
+ */
+#if (defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)) && \
+	!defined(CONFIG_VCT_SMALL_IMAGE)
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SNTP
+#else
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#endif
+
+/*
+ * Only Premium/Platinum have USB-EHCI support right now
+ */
+#if (defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)) && \
+	!defined(CONFIG_VCT_SMALL_IMAGE)
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_FAT
+#endif
+
+#if defined(CONFIG_CMD_USB)
+#define CONFIG_USB_STORAGE
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+#define CONFIG_SUPPORT_VFAT
+
+/*
+ * USB/EHCI
+ */
+#define CONFIG_USB_EHCI			/* Enable EHCI USB support	*/
+#define CONFIG_USB_EHCI_VCT		/* on VCT platform		*/
+#define CONFIG_EHCI_MMIO_BIG_ENDIAN
+#define CONFIG_EHCI_DESC_BIG_ENDIAN
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */
+#endif /* CONFIG_CMD_USB */
+
+#if !defined(CONFIG_VCT_NOR)
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#endif
+
+#if defined(CONFIG_VCT_NAND)
+#define CONFIG_CMD_NAND
+#endif
+
+#if defined(CONFIG_VCT_ONENAND)
+#define CONFIG_CMD_ONENAND
+#endif
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_SUBNETMASK
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define CONFIG_SYS_PROMPT	"VCT# "		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_CBSIZE	512		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
+				 sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_TIMESTAMP			/* Print image info with timestamp */
+#define CONFIG_CMDLINE_EDITING			/* add command line history	*/
+#define CONFIG_SYS_CONSOLE_INFO_QUIET		/* don't print console @ startup*/
+
+/*
+ * FLASH and environment organization
+ */
+#if defined(CONFIG_VCT_NOR)
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_FLASH_NOT_MEM_MAPPED
+
+/*
+ * We need special accessor functions for the CFI FLASH driver. This
+ * can be enabled via the CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS option.
+ */
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+
+/*
+ * For the non-memory-mapped NOR FLASH, we need to define the
+ * NOR FLASH area. This can't be detected via the addr2info()
+ * function, since we check for flash access in the very early
+ * U-Boot code, before the NOR FLASH is detected.
+ */
+#define CONFIG_FLASH_BASE		0xb0000000
+#define CONFIG_FLASH_END		0xbfffffff
+
+/*
+ * CFI driver settings
+ */
+#define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible	*/
+#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
+#define CONFIG_SYS_FLASH_CFI_AMD_RESET	1	/* Use AMD (Spansion) reset cmd */
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT	/* no byte writes on IXP4xx	*/
+
+#define CONFIG_SYS_FLASH_BASE		0xb0000000
+#define CONFIG_SYS_FLASH_BANKS_LIST    { CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	0x10000		/* size of one complete sector	*/
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
+#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+#endif /* CONFIG_ENV_IS_IN_FLASH */
+#endif /* CONFIG_VCT_NOR */
+
+#if defined(CONFIG_VCT_ONENAND)
+#define CONFIG_USE_ONENAND_BOARD_INIT
+#define	CONFIG_ENV_IS_IN_ONENAND
+#define	CONFIG_SYS_ONENAND_BASE		0x00000000	/* this is not real address */
+#define CONFIG_SYS_FLASH_BASE		0x00000000
+#define CONFIG_ENV_ADDR			(128 << 10)	/* after compr. U-Boot image */
+#define	CONFIG_ENV_SIZE			(128 << 10)	/* erase size */
+#endif /* CONFIG_VCT_ONENAND */
+
+/*
+ * Cache Configuration
+ */
+#define CONFIG_SYS_DCACHE_SIZE		16384
+#define CONFIG_SYS_ICACHE_SIZE		16384
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
+/*
+ * I2C/EEPROM
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED	83000	/* 83 kHz is supposed to work */
+#define CONFIG_SYS_I2C_SOFT_SLAVE	0x7f
+
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define CONFIG_SYS_GPIO_I2C_SCL		11
+#define CONFIG_SYS_GPIO_I2C_SDA		10
+
+#ifndef __ASSEMBLY__
+int vct_gpio_dir(int pin, int dir);
+void vct_gpio_set(int pin, int val);
+int vct_gpio_get(int pin);
+#endif
+
+#define I2C_INIT	vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SCL, 1)
+#define I2C_ACTIVE	vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SDA, 1)
+#define I2C_TRISTATE	vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SDA, 0)
+#define I2C_READ	vct_gpio_get(CONFIG_SYS_GPIO_I2C_SDA)
+#define I2C_SDA(bit)	vct_gpio_set(CONFIG_SYS_GPIO_I2C_SDA, bit)
+#define I2C_SCL(bit)	vct_gpio_set(CONFIG_SYS_GPIO_I2C_SCL, bit)
+#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+/* CAT24WC32 */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2	/* Bytes of address		*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5	/* The Catalyst CAT24WC32 has	*/
+					/* 32 byte page write mode using*/
+					/* last 5 bits of the address	*/
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
+
+#define CONFIG_BOOTCOMMAND	"run test3"
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+/*
+ * UBI configuration
+ */
+#if defined(CONFIG_VCT_ONENAND)
+#define CONFIG_SYS_USE_UBI
+#define	CONFIG_CMD_JFFS2
+#define	CONFIG_CMD_UBI
+#define	CONFIG_RBTREE
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+
+#define MTDIDS_DEFAULT		"onenand0=onenand"
+#define MTDPARTS_DEFAULT	"mtdparts=onenand:128k(u-boot),"	\
+					"128k(env),"		\
+					"20m(kernel),"		\
+					"-(rootfs)"
+#endif
+
+/*
+ * We need a small, stripped down image to fit into the first 128k OneNAND
+ * erase block (gzipped). This image only needs basic commands for FLASH
+ * (NOR/OneNAND) usage and Linux kernel booting.
+ */
+#if defined(CONFIG_VCT_SMALL_IMAGE)
+#undef CONFIG_CMD_ASKENV
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_BEDBUG
+#undef CONFIG_CMD_CACHE
+#undef CONFIG_CMD_CONSOLE
+#undef CONFIG_CMD_CRC32
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_ELF
+#undef CONFIG_CMD_FAT
+#undef CONFIG_CMD_I2C
+#undef CONFIG_CMD_I2C
+#undef CONFIG_CMD_IRQ
+#undef CONFIG_CMD_ITEST
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_LOADY
+#undef CONFIG_CMD_MII
+#undef CONFIG_CMD_MISC
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_PING
+#undef CONFIG_CMD_REGINFO
+#undef CONFIG_CMD_SNTP
+#undef CONFIG_CMD_SOURCE
+#undef CONFIG_CMD_STRINGS
+#undef CONFIG_CMD_TERMINAL
+#undef CONFIG_CMD_USB
+
+#undef CONFIG_SMC911X
+#undef CONFIG_SYS_I2C_SOFT
+#undef CONFIG_SOURCE
+#undef CONFIG_SYS_LONGHELP
+#undef CONFIG_TIMESTAMP
+#endif /* CONFIG_VCT_SMALL_IMAGE */
+
+#endif  /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/ve8313.h b/qemu/roms/u-boot/include/configs/ve8313.h
new file mode 100644
index 000000000..00787bbb2
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/ve8313.h
@@ -0,0 +1,498 @@
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006.
+ *
+ * (C) Copyright 2010
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/*
+ * ve8313 board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1
+#define CONFIG_MPC831x		1
+#define CONFIG_MPC8313		1
+#define CONFIG_VE8313		1
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xfe000000
+#endif
+
+#define CONFIG_PCI		1
+#define CONFIG_PCI_INDIRECT_BRIDGE 1
+#define CONFIG_FSL_ELBC		1
+
+#define CONFIG_BOARD_EARLY_INIT_F	1
+
+/*
+ * On-board devices
+ *
+ */
+#define CONFIG_83XX_CLKIN	32000000	/* in Hz */
+
+#define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN
+
+#define CONFIG_SYS_IMMR		0xE0000000
+
+#define CONFIG_SYS_MEMTEST_START	0x00001000
+#define CONFIG_SYS_MEMTEST_END		0x07000000
+
+#define CONFIG_SYS_ACR_PIPE_DEP		3	/* Arbiter pipeline depth */
+#define CONFIG_SYS_ACR_RPTCNT		3	/* Arbiter repeat count */
+
+/*
+ * Device configurations
+ */
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
+
+/*
+ * Manually set up DDR parameters, as this board does not
+ * have the SPD connected to I2C.
+ */
+#define CONFIG_SYS_DDR_SIZE	128	/* MB */
+#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
+				| CSCONFIG_AP \
+				| CSCONFIG_ODT_RD_NEVER \
+				| CSCONFIG_ODT_WR_ALL \
+				| CSCONFIG_ROW_BIT_13 \
+				| CSCONFIG_COL_BIT_10)
+				/* 0x80840102 */
+
+#define CONFIG_SYS_DDR_TIMING_3	0x00000000
+#define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
+				| (0 << TIMING_CFG0_WRT_SHIFT) \
+				| (3 << TIMING_CFG0_RRT_SHIFT) \
+				| (2 << TIMING_CFG0_WWT_SHIFT) \
+				| (7 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
+				| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
+				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
+				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
+				/* 0x0e720802 */
+#define CONFIG_SYS_DDR_TIMING_1	((2 << TIMING_CFG1_PRETOACT_SHIFT) \
+				| (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
+				| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
+				| (5 << TIMING_CFG1_CASLAT_SHIFT) \
+				| (6 << TIMING_CFG1_REFREC_SHIFT) \
+				| (2 << TIMING_CFG1_WRREC_SHIFT) \
+				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
+				| (2 << TIMING_CFG1_WRTORD_SHIFT))
+				/* 0x26256222 */
+#define CONFIG_SYS_DDR_TIMING_2	((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
+				| (5 << TIMING_CFG2_CPO_SHIFT) \
+				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
+				| (1 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
+				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
+				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
+				| (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
+				/* 0x029028c7 */
+#define CONFIG_SYS_DDR_INTERVAL	((0x320 << SDRAM_INTERVAL_REFINT_SHIFT) \
+				| (0x2000 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
+				/* 0x03202000 */
+#define CONFIG_SYS_SDRAM_CFG	(SDRAM_CFG_SREN \
+				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
+				| SDRAM_CFG_DBW_32)
+				/* 0x43080000 */
+#define CONFIG_SYS_SDRAM_CFG2	0x00401000
+#define CONFIG_SYS_DDR_MODE	((0x4440 << SDRAM_MODE_ESD_SHIFT) \
+				| (0x0232 << SDRAM_MODE_SD_SHIFT))
+				/* 0x44400232 */
+#define CONFIG_SYS_DDR_MODE_2	0x8000C000
+
+#define CONFIG_SYS_DDR_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+				/*0x02000000*/
+#define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN \
+				| DDRCDR_PZ_NOMZ \
+				| DDRCDR_NZ_NOMZ \
+				| DDRCDR_M_ODR)
+				/* 0x73000002 */
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
+#define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
+#define CONFIG_SYS_FLASH_BASE		0xFE000000
+#define CONFIG_SYS_FLASH_SIZE		32	/* size in MB */
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* display empty sectors */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	/* buffer up multiple bytes */
+
+#define CONFIG_SYS_NOR_BR_PRELIM	(CONFIG_SYS_FLASH_BASE \
+					| BR_PS_16	/* 16 bit */ \
+					| BR_MS_GPCM	/* MSEL = GPCM */ \
+					| BR_V)		/* valid */
+#define CONFIG_SYS_NOR_OR_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+					| OR_GPCM_CSNT \
+					| OR_GPCM_ACS_DIV4 \
+					| OR_GPCM_SCY_5 \
+					| OR_GPCM_TRLX_SET \
+					| OR_GPCM_EAD)
+					/* 0xfe000c55 */
+
+#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_32MB)
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	256		/* sectors per dev */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in RAM*/
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
+#define CONFIG_SYS_MONITOR_LEN		(384 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(512 * 1024)
+
+/*
+ * Local Bus LCRR and LBCR regs
+ */
+#define CONFIG_SYS_LCRR_EADC	LCRR_EADC_3
+#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_2
+
+#define CONFIG_SYS_LBC_LBCR	0x00040000
+
+#define CONFIG_SYS_LBC_MRTPR	0x20000000
+
+/*
+ * NAND settings
+ */
+#define CONFIG_SYS_NAND_BASE		0x61000000
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND 1
+#define CONFIG_NAND_FSL_ELBC 1
+#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
+
+#define CONFIG_SYS_NAND_BR_PRELIM	(CONFIG_SYS_NAND_BASE \
+					| BR_PS_8		\
+					| BR_DECC_CHK_GEN	\
+					| BR_MS_FCM		\
+					| BR_V)	/* valid */
+					/* 0x61000c21 */
+#define CONFIG_SYS_NAND_OR_PRELIM	(OR_AM_32KB \
+					| OR_FCM_BCTLD \
+					| OR_FCM_CHT \
+					| OR_FCM_SCY_2 \
+					| OR_FCM_RST \
+					| OR_FCM_TRLX)
+					/* 0xffff90ac */
+
+#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
+#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
+#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
+#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
+
+#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_NAND_BASE
+#define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)
+
+#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
+#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
+
+/* CS2 NvRAM */
+#define CONFIG_SYS_BR2_PRELIM	(0x60000000 \
+				| BR_PS_8 \
+				| BR_V)
+				/* 0x60000801 */
+#define CONFIG_SYS_OR2_PRELIM	(OR_AM_128KB \
+				| OR_GPCM_CSNT \
+				| OR_GPCM_XACS \
+				| OR_GPCM_SCY_3 \
+				| OR_GPCM_TRLX_SET \
+				| OR_GPCM_EHTR_SET \
+				| OR_GPCM_EAD)
+				/* 0xfffe0937 */
+/* local bus read write buffer mapping SRAM@0x64000000 */
+#define CONFIG_SYS_BR3_PRELIM	(0x62000000 \
+				| BR_PS_16 \
+				| BR_V)
+				/* 0x62001001 */
+
+#define CONFIG_SYS_OR3_PRELIM	(OR_AM_32MB \
+				| OR_GPCM_CSNT \
+				| OR_GPCM_XACS \
+				| OR_GPCM_SCY_15 \
+				| OR_GPCM_TRLX_SET \
+				| OR_GPCM_EHTR_SET \
+				| OR_GPCM_EAD)
+				/* 0xfe0009f7 */
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+#if defined(CONFIG_PCI)
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
+#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS		0xE2000000
+#define CONFIG_SYS_PCI1_IO_SIZE		0x00100000	/* 1M */
+
+#define CONFIG_PCI_PNP		/* do pci plug-and-play */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
+#endif
+
+/*
+ * TSEC
+ */
+#define CONFIG_TSEC_ENET		/* TSEC ethernet support */
+
+
+#define CONFIG_TSEC1
+#ifdef CONFIG_TSEC1
+#define CONFIG_HAS_ETH0
+#define CONFIG_TSEC1_NAME	"TSEC1"
+#define CONFIG_SYS_TSEC1_OFFSET	0x24000
+#define TSEC1_PHY_ADDR		0x01
+#define TSEC1_FLAGS		0
+#define TSEC1_PHYIDX		0
+#endif
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME			"TSEC1"
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_ADDR		\
+			(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SECT_SIZE	0x20000	/* 128K(one sector) for env */
+#define CONFIG_ENV_SIZE		0x4000
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_OFFSET_REDUND	\
+			(CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_PCI
+
+#define CONFIG_CMDLINE_EDITING 1
+#define CONFIG_AUTO_COMPLETE	/* add autocompletion support   */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16		/* max number of cmd args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot arg Buffer size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+				/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)
+
+/* 0x64050000 */
+#define CONFIG_SYS_HRCW_LOW (\
+	0x20000000 /* reserved, must be set */ |\
+	HRCWL_DDRCM |\
+	HRCWL_CSB_TO_CLKIN_4X1 | \
+	HRCWL_CORE_TO_CSB_2_5X1)
+
+/* 0xa0600004 */
+#define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST | \
+	HRCWH_PCI_ARBITER_ENABLE | \
+	HRCWH_CORE_ENABLE | \
+	HRCWH_FROM_0X00000100 | \
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT | \
+	HRCWH_TSEC1M_IN_MII | \
+	HRCWH_BIG_ENDIAN | \
+	HRCWH_LALE_EARLY)
+
+/* System IO Config */
+#define CONFIG_SYS_SICRH	(0x01000000 | \
+				SICRH_ETSEC2_B | \
+				SICRH_ETSEC2_C | \
+				SICRH_ETSEC2_D | \
+				SICRH_ETSEC2_E | \
+				SICRH_ETSEC2_F | \
+				SICRH_ETSEC2_G | \
+				SICRH_TSOBI1 | \
+				SICRH_TSOBI2)
+				/* 0x010fff03 */
+#define CONFIG_SYS_SICRL	(SICRL_LBC | \
+				SICRL_SPI_A | \
+				SICRL_SPI_B | \
+				SICRL_SPI_C | \
+				SICRL_SPI_D | \
+				SICRL_ETSEC2_A)
+				/* 0x33fc0003) */
+
+#define CONFIG_SYS_HID0_INIT	0x000000000
+#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
+				 HID0_ENABLE_INSTRUCTION_CACHE)
+
+#define CONFIG_SYS_HID2 HID2_HBE
+
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
+/* DDR @ 0x00000000 */
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+
+#if defined(CONFIG_PCI)
+/* PCI @ 0x80000000 */
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_PCI1_MEM_BASE \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_MMIO_BASE \
+				| BATL_PP_RW \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PCI1_MMIO_BASE \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+#else
+#define CONFIG_SYS_IBAT1L	(0)
+#define CONFIG_SYS_IBAT1U	(0)
+#define CONFIG_SYS_IBAT2L	(0)
+#define CONFIG_SYS_IBAT2U	(0)
+#endif
+
+/* PCI2 not supported on 8313 */
+#define CONFIG_SYS_IBAT3L	(0)
+#define CONFIG_SYS_IBAT3U	(0)
+#define CONFIG_SYS_IBAT4L	(0)
+#define CONFIG_SYS_IBAT4U	(0)
+
+/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
+#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_IMMR \
+				| BATL_PP_RW \
+				| BATL_CACHEINHIBIT \
+				| BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_IMMR \
+				| BATU_BL_256M \
+				| BATU_VS \
+				| BATU_VP)
+
+/* stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
+#define CONFIG_SYS_IBAT6L	(0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT6U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/*  FPGA, SRAM, NAND @ 0x60000000 */
+#define CONFIG_SYS_IBAT7L	(0x60000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT7U	(0x60000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
+#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
+#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
+#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
+#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
+
+#define CONFIG_NETDEV		eth0
+
+#define CONFIG_HOSTNAME		ve8313
+#define CONFIG_UBOOTPATH	ve8313/u-boot.bin
+
+#define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"netdev=" __stringify(CONFIG_NETDEV) "\0"			\
+	"ethprime=" __stringify(CONFIG_TSEC1_NAME) "\0"			\
+	"u-boot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
+	"u-boot_addr_r=100000\0"					\
+	"load=tftp ${u-boot_addr_r} ${u-boot}\0"			\
+	"update=protect off " __stringify(CONFIG_SYS_FLASH_BASE)	\
+		" +${filesize};"	\
+	"erase " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};"	\
+	"cp.b ${u-boot_addr_r} " __stringify(CONFIG_SYS_FLASH_BASE)	\
+	" ${filesize};"							\
+	"protect on " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize}\0" \
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/venice2.h b/qemu/roms/u-boot/include/configs/venice2.h
new file mode 100644
index 000000000..2d75f5013
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/venice2.h
@@ -0,0 +1,79 @@
+/*
+ * (C) Copyright 2013-2014
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+
+#include "tegra124-common.h"
+
+/* Enable fdt support for Venice2. Flash the image in u-boot-dtb.bin */
+#define CONFIG_DEFAULT_DEVICE_TREE	tegra124-venice2
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
+/* High-level configuration options */
+#define V_PROMPT			"Tegra124 (Venice2) # "
+#define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Venice2"
+
+/* Board-specific serial config */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_TEGRA_ENABLE_UARTA
+#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* I2C */
+#define CONFIG_SYS_I2C_TEGRA
+#define CONFIG_SYS_I2C_INIT_BOARD
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_MAX_I2C_BUS		TEGRA_I2C_NUM_CONTROLLERS
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_TEGRA_MMC
+#define CONFIG_CMD_MMC
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART		2
+#define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE)
+
+/* SPI */
+#define CONFIG_TEGRA114_SPI		/* Compatible w/ Tegra114 SPI */
+#define CONFIG_TEGRA114_SPI_CTRLS	6
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SF_DEFAULT_MODE         SPI_MODE_0
+#define CONFIG_SF_DEFAULT_SPEED        24000000
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH_SIZE          (4 << 20)
+
+/* USB Host support */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_TEGRA
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB
+
+/* USB networking support */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+
+/* General networking support */
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/ventana.h b/qemu/roms/u-boot/include/configs/ventana.h
new file mode 100644
index 000000000..edf3720b6
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/ventana.h
@@ -0,0 +1,71 @@
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+#include "tegra20-common.h"
+
+/* Enable fdt support for Ventana. Flash the image in u-boot-dtb.bin */
+#define CONFIG_DEFAULT_DEVICE_TREE	tegra20-ventana
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
+/* High-level configuration options */
+#define V_PROMPT		"Tegra20 (Ventana) # "
+#define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Ventana"
+
+/* Board-specific serial config */
+#define CONFIG_TEGRA_ENABLE_UARTD
+#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_VENTANA
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT		/* Make sure LCD init is complete */
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_TEGRA_MMC
+#define CONFIG_CMD_MMC
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_SYS_MMC_ENV_PART 2
+
+/* USB Host support */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_TEGRA
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB
+
+/* USB networking support */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+
+/* General networking support */
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+
+/* USB keyboard */
+#define CONFIG_USB_KEYBOARD
+
+/* LCD support */
+#define CONFIG_LCD
+#define CONFIG_PWM_TEGRA
+#define CONFIG_VIDEO_TEGRA
+#define LCD_BPP				LCD_COLOR16
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define CONFIG_CONSOLE_SCROLL_LINES	10
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/versatile.h b/qemu/roms/u-boot/include/configs/versatile.h
new file mode 100644
index 000000000..29c32fee5
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/versatile.h
@@ -0,0 +1,220 @@
+/*
+ * (C) Copyright 2003
+ * Texas Instruments.
+ * Kshitij Gupta <kshitij@ti.com>
+ * Configuation settings for the TI OMAP Innovator board.
+ *
+ * (C) Copyright 2004
+ * ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ * Configuration for Versatile PB.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARM926EJS	1	/* This is an arm926ejs CPU core */
+#define CONFIG_VERSATILE	1	/* in Versatile Platform Board	*/
+#define CONFIG_ARCH_VERSATILE	1	/* Specifically, a Versatile	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x100000
+#define CONFIG_SYS_MEMTEST_END		0x10000000
+
+#define CONFIG_SYS_TIMERBASE		0x101E2000	/* Timer 0 and 1 base */
+#define CONFIG_SYS_TIMER_RATE		(1000000 / 256)
+#define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMERBASE + 0x4)
+#define CONFIG_SYS_TIMER_COUNTS_DOWN
+
+/*
+ * control registers
+ */
+#define VERSATILE_SCTL_BASE		0x101E0000	/* System controller */
+
+/*
+ * System controller bit assignment
+ */
+#define VERSATILE_REFCLK	0
+#define VERSATILE_TIMCLK	1
+
+#define VERSATILE_TIMER1_EnSel	15
+#define VERSATILE_TIMER2_EnSel	17
+#define VERSATILE_TIMER3_EnSel	19
+#define VERSATILE_TIMER4_EnSel	21
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_MISC_INIT_R		1
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE			8192
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)
+
+/*
+ * Hardware drivers
+ */
+
+#define CONFIG_SMC91111
+#define CONFIG_SMC_USE_32_BIT
+#define CONFIG_SMC91111_BASE	0x10010000
+#undef CONFIG_SMC91111_EXT_PHY
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_PL011_SERIAL
+#define CONFIG_PL011_CLOCK	24000000
+#define CONFIG_PL01x_PORTS				\
+			{(void *)CONFIG_SYS_SERIAL0,	\
+			 (void *)CONFIG_SYS_SERIAL1 }
+#define CONFIG_CONS_INDEX	0
+
+#define CONFIG_BAUDRATE			38400
+#define CONFIG_SYS_SERIAL0		0x101F1000
+#define CONFIG_SYS_SERIAL1		0x101F2000
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVEENV
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_SUBNETMASK
+
+#define CONFIG_BOOTDELAY	2
+#define CONFIG_BOOTARGS		"root=/dev/nfs mem=128M ip=dhcp "\
+				"netdev=25,0,0xf1010000,0xf1010010,eth0 "\
+				"console=ttyAMA0,38400n1"
+
+/*
+ * Static configuration when assigning fixed address
+ */
+#define CONFIG_BOOTFILE		"/tftpboot/uImage" /* file to load */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP	/* undef to save memory */
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+/* Monitor Command Prompt	 */
+#ifdef CONFIG_ARCH_VERSATILE_AB
+# define CONFIG_SYS_PROMPT	"VersatileAB # "
+#else
+# define CONFIG_SYS_PROMPT	"VersatilePB # "
+#endif
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE	\
+			(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_LOAD_ADDR	0x7fc0	/* default load address */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1	/* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1		0x00000000	/* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x08000000	/* 128 MB */
+#define PHYS_FLASH_SIZE		0x04000000	/* 64MB */
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR	0x00800000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x000FFFFF
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+						GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_INIT_RAM_ADDR + \
+						CONFIG_SYS_GBL_DATA_OFFSET)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#ifdef CONFIG_ARCH_VERSATILE_QEMU
+#define CONFIG_SYS_TEXT_BASE		0x10000
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_SYS_MONITOR_LEN		0x80000
+#else
+#define CONFIG_SYS_TEXT_BASE		0x01000000
+/*
+ * Use the CFI flash driver for ease of use
+ */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_ENV_IS_IN_FLASH	1
+/*
+ *	System control register
+ */
+#define VERSATILE_SYS_BASE		0x10000000
+#define VERSATILE_SYS_FLASH_OFFSET	0x4C
+#define VERSATILE_FLASHCTRL		\
+		(VERSATILE_SYS_BASE + VERSATILE_SYS_FLASH_OFFSET)
+/* Enable writing to flash */
+#define VERSATILE_FLASHPROG_FLVPPEN	(1 << 0)
+
+/* timeout values are in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(2 * CONFIG_SYS_HZ) /* Erase Timeout */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(2 * CONFIG_SYS_HZ) /* Write Timeout */
+
+/*
+ * Note that CONFIG_SYS_MAX_FLASH_SECT allows for a parameter block
+ * i.e.
+ *	the bottom "sector" (bottom boot), or top "sector"
+ *	(top boot), is a seperate erase region divided into
+ *	4 (equal) smaller sectors. This, notionally, allows
+ *	quicker erase/rewrire of the most frequently changed
+ *	area......
+ *	CONFIG_SYS_MAX_FLASH_SECT is padded up to a multiple of 4
+ */
+
+#ifdef CONFIG_ARCH_VERSATILE_AB
+#define FLASH_SECTOR_SIZE		0x00020000	/* 128 KB sectors */
+#define CONFIG_ENV_SECT_SIZE		(2 * FLASH_SECTOR_SIZE)
+#define CONFIG_SYS_MAX_FLASH_SECT	(520)
+#endif
+
+#ifdef CONFIG_ARCH_VERSATILE_PB		/* Versatile PB is default	*/
+#define FLASH_SECTOR_SIZE		0x00040000	/* 256 KB sectors */
+#define CONFIG_ENV_SECT_SIZE		FLASH_SECTOR_SIZE
+#define CONFIG_SYS_MAX_FLASH_SECT	(260)
+#endif
+
+#define CONFIG_SYS_FLASH_BASE		0x34000000
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+
+#define CONFIG_SYS_MONITOR_LEN		(4 * CONFIG_ENV_SECT_SIZE)
+
+/* The ARM Boot Monitor is shipped in the lowest sector of flash */
+
+#define FLASH_TOP			(CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SIZE)
+#define CONFIG_ENV_ADDR			(FLASH_TOP - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_OFFSET		(CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_MONITOR_BASE		(CONFIG_ENV_ADDR - CONFIG_SYS_MONITOR_LEN)
+
+#define CONFIG_SYS_FLASH_PROTECTION	/* The devices have real protection */
+#define CONFIG_SYS_FLASH_EMPTY_INFO	/* flinfo indicates empty blocks */
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/vexpress_aemv8a.h b/qemu/roms/u-boot/include/configs/vexpress_aemv8a.h
new file mode 100644
index 000000000..dff6adcc7
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/vexpress_aemv8a.h
@@ -0,0 +1,196 @@
+/*
+ * Configuration for Versatile Express. Parts were derived from other ARM
+ *   configurations.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __VEXPRESS_AEMV8A_H
+#define __VEXPRESS_AEMV8A_H
+
+#define DEBUG
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_GICV3
+
+/*#define CONFIG_ARMV8_SWITCH_TO_EL1*/
+
+/*#define CONFIG_SYS_GENERIC_BOARD*/
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_SUPPORT_RAW_INITRD
+
+/* Cache Definitions */
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_SYS_ICACHE_OFF
+
+#define CONFIG_IDENT_STRING		" vexpress_aemv8a"
+#define CONFIG_BOOTP_VCI_STRING		"U-boot.armv8.vexpress_aemv8a"
+
+/* Link Definitions */
+#define CONFIG_SYS_TEXT_BASE		0x80000000
+#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
+
+/* Flat Device Tree Definitions */
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_DEFAULT_DEVICE_TREE	vexpress64
+
+/* SMP Spin Table Definitions */
+#define CPU_RELEASE_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x7fff0)
+
+/* CS register bases for the original memory map. */
+#define V2M_PA_CS0			0x00000000
+#define V2M_PA_CS1			0x14000000
+#define V2M_PA_CS2			0x18000000
+#define V2M_PA_CS3			0x1c000000
+#define V2M_PA_CS4			0x0c000000
+#define V2M_PA_CS5			0x10000000
+
+#define V2M_PERIPH_OFFSET(x)		(x << 16)
+#define V2M_SYSREGS			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(1))
+#define V2M_SYSCTL			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(2))
+#define V2M_SERIAL_BUS_PCI		(V2M_PA_CS3 + V2M_PERIPH_OFFSET(3))
+
+#define V2M_BASE			0x80000000
+
+/*
+ * Physical addresses, offset from V2M_PA_CS0-3
+ */
+#define V2M_NOR0			(V2M_PA_CS0)
+#define V2M_NOR1			(V2M_PA_CS4)
+#define V2M_SRAM			(V2M_PA_CS1)
+
+/* Common peripherals relative to CS7. */
+#define V2M_AACI			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(4))
+#define V2M_MMCI			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(5))
+#define V2M_KMI0			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(6))
+#define V2M_KMI1			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(7))
+
+#define V2M_UART0			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(9))
+#define V2M_UART1			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(10))
+#define V2M_UART2			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(11))
+#define V2M_UART3			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(12))
+
+#define V2M_WDT				(V2M_PA_CS3 + V2M_PERIPH_OFFSET(15))
+
+#define V2M_TIMER01			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(17))
+#define V2M_TIMER23			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(18))
+
+#define V2M_SERIAL_BUS_DVI		(V2M_PA_CS3 + V2M_PERIPH_OFFSET(22))
+#define V2M_RTC				(V2M_PA_CS3 + V2M_PERIPH_OFFSET(23))
+
+#define V2M_CF				(V2M_PA_CS3 + V2M_PERIPH_OFFSET(26))
+
+#define V2M_CLCD			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(31))
+
+/* System register offsets. */
+#define V2M_SYS_CFGDATA			(V2M_SYSREGS + 0x0a0)
+#define V2M_SYS_CFGCTRL			(V2M_SYSREGS + 0x0a4)
+#define V2M_SYS_CFGSTAT			(V2M_SYSREGS + 0x0a8)
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY		(0x1800000)	/* 24MHz */
+
+/* Generic Interrupt Controller Definitions */
+#ifdef CONFIG_GICV3
+#define GICD_BASE			(0x2f000000)
+#define GICR_BASE			(0x2f100000)
+#else
+#define GICD_BASE			(0x2C001000)
+#define GICC_BASE			(0x2C002000)
+#endif
+
+#define CONFIG_SYS_MEMTEST_START	V2M_BASE
+#define CONFIG_SYS_MEMTEST_END		(V2M_BASE + 0x80000000)
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)
+
+/* SMSC91C111 Ethernet Configuration */
+#define CONFIG_SMC91111			1
+#define CONFIG_SMC91111_BASE		(0x01A000000)
+
+/* PL011 Serial Configuration */
+#define CONFIG_PL011_SERIAL
+#define CONFIG_PL011_CLOCK		24000000
+#define CONFIG_PL01x_PORTS		{(void *)CONFIG_SYS_SERIAL0, \
+					 (void *)CONFIG_SYS_SERIAL1}
+#define CONFIG_CONS_INDEX		0
+
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_SERIAL0		V2M_UART0
+#define CONFIG_SYS_SERIAL1		V2M_UART1
+
+/* Command line configuration */
+#define CONFIG_MENU
+/*#define CONFIG_MENU_SHOW*/
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PXE
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_SOURCE
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+/* BOOTP options */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_PXE
+#define CONFIG_BOOTP_PXE_CLIENTARCH	0x100
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LOAD_ADDR		(V2M_BASE + 0x10000000)
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM_1			(V2M_BASE)	/* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE		0x80000000	/* 2048 MB */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+					"kernel_addr=0x200000\0"	\
+					"initrd_addr=0xa00000\0"	\
+					"initrd_size=0x2000000\0"	\
+					"fdt_addr=0x100000\0"		\
+					"fdt_high=0xa0000000\0"
+
+#define CONFIG_BOOTARGS			"console=ttyAMA0 root=/dev/ram0"
+#define CONFIG_BOOTCOMMAND		"bootm $kernel_addr " \
+					"$initrd_addr:$initrd_size $fdt_addr"
+#define CONFIG_BOOTDELAY		-1
+
+/* Do not preserve environment */
+#define CONFIG_ENV_IS_NOWHERE		1
+#define CONFIG_ENV_SIZE			0x1000
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PROMPT		"VExpress64# "
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING		1
+#define CONFIG_SYS_MAXARGS		64	/* max command args */
+
+#endif /* __VEXPRESS_AEMV8A_H */
diff --git a/qemu/roms/u-boot/include/configs/vexpress_ca15_tc2.h b/qemu/roms/u-boot/include/configs/vexpress_ca15_tc2.h
new file mode 100644
index 000000000..982f4a75e
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/vexpress_ca15_tc2.h
@@ -0,0 +1,23 @@
+/*
+ * (C) Copyright 2013 Linaro
+ * Andre Przywara, <andre.przywara@linaro.org>
+ *
+ * Configuration for Versatile Express. Parts were derived from other ARM
+ *   configurations.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __VEXPRESS_CA15X2_TC2_h
+#define __VEXPRESS_CA15X2_TC2_h
+
+#define CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP
+#include "vexpress_common.h"
+#define CONFIG_BOOTP_VCI_STRING     "U-boot.armv7.vexpress_ca15x2_tc2"
+
+#define CONFIG_SYSFLAGS_ADDR	0x1c010030
+#define CONFIG_SMP_PEN_ADDR	CONFIG_SYSFLAGS_ADDR
+
+#define CONFIG_ARMV7_VIRT
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/vexpress_ca5x2.h b/qemu/roms/u-boot/include/configs/vexpress_ca5x2.h
new file mode 100644
index 000000000..7719d59e1
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/vexpress_ca5x2.h
@@ -0,0 +1,18 @@
+/*
+ * (C) Copyright 2011 Linaro
+ * Ryan Harkin, <ryan.harkin@linaro.org>
+ *
+ * Configuration for Versatile Express. Parts were derived from other ARM
+ *   configurations.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __VEXPRESS_CA5X2_h
+#define __VEXPRESS_CA5X2_h
+
+#define CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP
+#include "vexpress_common.h"
+#define CONFIG_BOOTP_VCI_STRING     "U-boot.armv7.vexpress_ca5x2"
+
+#endif /* __VEXPRESS_CA5X2_h */
diff --git a/qemu/roms/u-boot/include/configs/vexpress_ca9x4.h b/qemu/roms/u-boot/include/configs/vexpress_ca9x4.h
new file mode 100644
index 000000000..38ac4ed38
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/vexpress_ca9x4.h
@@ -0,0 +1,18 @@
+/*
+ * (C) Copyright 2011 Linaro
+ * Ryan Harkin, <ryan.harkin@linaro.org>
+ *
+ * Configuration for Versatile Express. Parts were derived from other ARM
+ *   configurations.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __VEXPRESS_CA9X4_H
+#define __VEXPRESS_CA9X4_H
+
+#define CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP
+#include "vexpress_common.h"
+#define CONFIG_BOOTP_VCI_STRING     "U-boot.armv7.vexpress_ca9x4"
+
+#endif /* VEXPRESS_CA9X4_H */
diff --git a/qemu/roms/u-boot/include/configs/vexpress_common.h b/qemu/roms/u-boot/include/configs/vexpress_common.h
new file mode 100644
index 000000000..7e78f8ac8
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/vexpress_common.h
@@ -0,0 +1,302 @@
+/*
+ * (C) Copyright 2011 ARM Limited
+ * (C) Copyright 2010 Linaro
+ * Matt Waddel, <matt.waddel@linaro.org>
+ *
+ * Configuration for Versatile Express. Parts were derived from other ARM
+ *   configurations.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __VEXPRESS_COMMON_H
+#define __VEXPRESS_COMMON_H
+
+/*
+ * Definitions copied from linux kernel:
+ * arch/arm/mach-vexpress/include/mach/motherboard.h
+ */
+#ifdef CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP
+/* CS register bases for the original memory map. */
+#define V2M_PA_CS0		0x40000000
+#define V2M_PA_CS1		0x44000000
+#define V2M_PA_CS2		0x48000000
+#define V2M_PA_CS3		0x4c000000
+#define V2M_PA_CS7		0x10000000
+
+#define V2M_PERIPH_OFFSET(x)	(x << 12)
+#define V2M_SYSREGS		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(0))
+#define V2M_SYSCTL		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(1))
+#define V2M_SERIAL_BUS_PCI	(V2M_PA_CS7 + V2M_PERIPH_OFFSET(2))
+
+#define V2M_BASE		0x60000000
+#define CONFIG_SYS_TEXT_BASE	0x60800000
+#elif defined(CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP)
+/* CS register bases for the extended memory map. */
+#define V2M_PA_CS0		0x08000000
+#define V2M_PA_CS1		0x0c000000
+#define V2M_PA_CS2		0x14000000
+#define V2M_PA_CS3		0x18000000
+#define V2M_PA_CS7		0x1c000000
+
+#define V2M_PERIPH_OFFSET(x)	(x << 16)
+#define V2M_SYSREGS		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(1))
+#define V2M_SYSCTL		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(2))
+#define V2M_SERIAL_BUS_PCI	(V2M_PA_CS7 + V2M_PERIPH_OFFSET(3))
+
+#define V2M_BASE		0x80000000
+#define CONFIG_SYS_TEXT_BASE	0x80800000
+#endif
+
+/*
+ * Physical addresses, offset from V2M_PA_CS0-3
+ */
+#define V2M_NOR0		(V2M_PA_CS0)
+#define V2M_NOR1		(V2M_PA_CS1)
+#define V2M_SRAM		(V2M_PA_CS2)
+#define V2M_VIDEO_SRAM		(V2M_PA_CS3 + 0x00000000)
+#define V2M_LAN9118		(V2M_PA_CS3 + 0x02000000)
+#define V2M_ISP1761		(V2M_PA_CS3 + 0x03000000)
+
+/* Common peripherals relative to CS7. */
+#define V2M_AACI		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(4))
+#define V2M_MMCI		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(5))
+#define V2M_KMI0		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(6))
+#define V2M_KMI1		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(7))
+
+#define V2M_UART0		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(9))
+#define V2M_UART1		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(10))
+#define V2M_UART2		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(11))
+#define V2M_UART3		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(12))
+
+#define V2M_WDT			(V2M_PA_CS7 + V2M_PERIPH_OFFSET(15))
+
+#define V2M_TIMER01		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(17))
+#define V2M_TIMER23		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(18))
+
+#define V2M_SERIAL_BUS_DVI	(V2M_PA_CS7 + V2M_PERIPH_OFFSET(22))
+#define V2M_RTC			(V2M_PA_CS7 + V2M_PERIPH_OFFSET(23))
+
+#define V2M_CF			(V2M_PA_CS7 + V2M_PERIPH_OFFSET(26))
+
+#define V2M_CLCD		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(31))
+#define V2M_SIZE_CS7		V2M_PERIPH_OFFSET(32)
+
+/* System register offsets. */
+#define V2M_SYS_CFGDATA		(V2M_SYSREGS + 0x0a0)
+#define V2M_SYS_CFGCTRL		(V2M_SYSREGS + 0x0a4)
+#define V2M_SYS_CFGSTAT		(V2M_SYSREGS + 0x0a8)
+
+/*
+ * Configuration
+ */
+#define SYS_CFG_START		(1 << 31)
+#define SYS_CFG_WRITE		(1 << 30)
+#define SYS_CFG_OSC		(1 << 20)
+#define SYS_CFG_VOLT		(2 << 20)
+#define SYS_CFG_AMP		(3 << 20)
+#define SYS_CFG_TEMP		(4 << 20)
+#define SYS_CFG_RESET		(5 << 20)
+#define SYS_CFG_SCC		(6 << 20)
+#define SYS_CFG_MUXFPGA		(7 << 20)
+#define SYS_CFG_SHUTDOWN	(8 << 20)
+#define SYS_CFG_REBOOT		(9 << 20)
+#define SYS_CFG_DVIMODE		(11 << 20)
+#define SYS_CFG_POWER		(12 << 20)
+#define SYS_CFG_SITE_MB		(0 << 16)
+#define SYS_CFG_SITE_DB1	(1 << 16)
+#define SYS_CFG_SITE_DB2	(2 << 16)
+#define SYS_CFG_STACK(n)	((n) << 12)
+
+#define SYS_CFG_ERR		(1 << 1)
+#define SYS_CFG_COMPLETE	(1 << 0)
+
+/* Board info register */
+#define SYS_ID				V2M_SYSREGS
+#define CONFIG_REVISION_TAG		1
+
+#define CONFIG_SYS_MEMTEST_START	V2M_BASE
+#define CONFIG_SYS_MEMTEST_END		0x20000000
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_SYS_L2CACHE_OFF		1
+#define CONFIG_INITRD_TAG		1
+
+#define CONFIG_OF_LIBFDT		1
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)
+
+#define SCTL_BASE			V2M_SYSCTL
+#define VEXPRESS_FLASHPROG_FLVPPEN	(1 << 0)
+
+#define CONFIG_SYS_TIMER_RATE		1000000
+#define CONFIG_SYS_TIMER_COUNTER	(V2M_TIMER01 + 0x4)
+#define CONFIG_SYS_TIMER_COUNTS_DOWN
+
+/* SMSC9115 Ethernet from SMSC9118 family */
+#define CONFIG_SMC911X			1
+#define CONFIG_SMC911X_32_BIT		1
+#define CONFIG_SMC911X_BASE		V2M_LAN9118
+
+/* PL011 Serial Configuration */
+#define CONFIG_PL011_SERIAL
+#define CONFIG_PL011_CLOCK		24000000
+#define CONFIG_PL01x_PORTS		{(void *)CONFIG_SYS_SERIAL0, \
+					 (void *)CONFIG_SYS_SERIAL1}
+#define CONFIG_CONS_INDEX		0
+
+#define CONFIG_BAUDRATE			38400
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_SERIAL0		V2M_UART0
+#define CONFIG_SYS_SERIAL1		V2M_UART1
+
+/* Command line configuration */
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PXE
+#define CONFIG_MENU
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_SUPPORT_RAW_INITRD
+
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION		1
+#define CONFIG_MMC			1
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_ARM_PL180_MMCI
+#define CONFIG_ARM_PL180_MMCI_BASE	V2M_MMCI
+#define CONFIG_SYS_MMC_MAX_BLK_COUNT	127
+#define CONFIG_ARM_PL180_MMCI_CLOCK_FREQ 6250000
+
+/* BOOTP options */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_PXE
+#define CONFIG_BOOTP_PXE_CLIENTARCH	0x100
+
+/* Miscellaneous configurable options */
+#undef	CONFIG_SYS_CLKS_IN_HZ
+#define CONFIG_SYS_LOAD_ADDR		(V2M_BASE + 0x8000)
+#define LINUX_BOOT_PARAM_ADDR		(V2M_BASE + 0x2000)
+#define CONFIG_BOOTDELAY		2
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS		2
+#define PHYS_SDRAM_1			(V2M_BASE)	/* SDRAM Bank #1 */
+#define PHYS_SDRAM_2			(((unsigned int)V2M_BASE) + \
+					((unsigned int)0x20000000))
+#define PHYS_SDRAM_1_SIZE		0x20000000	/* 512 MB */
+#define PHYS_SDRAM_2_SIZE		0x20000000	/* 512 MB */
+
+/* additions for new relocation code */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_SIZE		0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_SDRAM_BASE + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SYS_GBL_DATA_OFFSET
+
+/* Basic environment settings */
+#define CONFIG_BOOTCOMMAND		"run bootflash;"
+#ifdef CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP
+#define CONFIG_PLATFORM_ENV_SETTINGS \
+		"loadaddr=0x80008000\0" \
+		"ramdisk_addr_r=0x61000000\0" \
+		"kernel_addr=0x44100000\0" \
+		"ramdisk_addr=0x44800000\0" \
+		"maxramdisk=0x1800000\0" \
+		"pxefile_addr_r=0x88000000\0" \
+		"kernel_addr_r=0x80008000\0"
+#elif defined(CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP)
+#define CONFIG_PLATFORM_ENV_SETTINGS \
+		"loadaddr=0xa0008000\0" \
+		"ramdisk_addr_r=0x81000000\0" \
+		"kernel_addr=0x0c100000\0" \
+		"ramdisk_addr=0x0c800000\0" \
+		"maxramdisk=0x1800000\0" \
+		"pxefile_addr_r=0xa8000000\0" \
+		"kernel_addr_r=0xa0008000\0"
+#endif
+#define CONFIG_EXTRA_ENV_SETTINGS \
+		CONFIG_PLATFORM_ENV_SETTINGS \
+		"console=ttyAMA0,38400n8\0" \
+		"dram=1024M\0" \
+		"root=/dev/sda1 rw\0" \
+		"mtd=armflash:1M@0x800000(uboot),7M@0x1000000(kernel)," \
+			"24M@0x2000000(initrd)\0" \
+		"flashargs=setenv bootargs root=${root} console=${console} " \
+			"mem=${dram} mtdparts=${mtd} mmci.fmax=190000 " \
+			"devtmpfs.mount=0  vmalloc=256M\0" \
+		"bootflash=run flashargs; " \
+			"cp ${ramdisk_addr} ${ramdisk_addr_r} ${maxramdisk}; " \
+			"bootm ${kernel_addr} ${ramdisk_addr_r}\0"
+
+/* FLASH and environment organization */
+#define PHYS_FLASH_SIZE			0x04000000	/* 64MB */
+#define CONFIG_SYS_FLASH_CFI		1
+#define CONFIG_FLASH_CFI_DRIVER		1
+#define CONFIG_SYS_FLASH_SIZE		0x04000000
+#define CONFIG_SYS_MAX_FLASH_BANKS	2
+#define CONFIG_SYS_FLASH_BASE0		V2M_NOR0
+#define CONFIG_SYS_FLASH_BASE1		V2M_NOR1
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE0
+
+/* Timeout values in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(2 * CONFIG_SYS_HZ) /* Erase Timeout */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(2 * CONFIG_SYS_HZ) /* Write Timeout */
+
+/* 255 0x40000 sectors + first or last sector may have 4 erase regions = 259 */
+#define CONFIG_SYS_MAX_FLASH_SECT	259		/* Max sectors */
+#define FLASH_MAX_SECTOR_SIZE		0x00040000	/* 256 KB sectors */
+
+/* Room required on the stack for the environment data */
+#define CONFIG_ENV_SIZE			FLASH_MAX_SECTOR_SIZE
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */
+
+/*
+ * Amount of flash used for environment:
+ * We don't know which end has the small erase blocks so we use the penultimate
+ * sector location for the environment
+ */
+#define CONFIG_ENV_SECT_SIZE		FLASH_MAX_SECTOR_SIZE
+#define CONFIG_ENV_OVERWRITE		1
+
+/* Store environment at top of flash */
+#define CONFIG_ENV_IS_IN_FLASH		1
+#define CONFIG_ENV_OFFSET		(PHYS_FLASH_SIZE - \
+					(2 * CONFIG_ENV_SECT_SIZE))
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE1 + \
+					 CONFIG_ENV_OFFSET)
+#define CONFIG_SYS_FLASH_PROTECTION	/* The devices have real protection */
+#define CONFIG_SYS_FLASH_EMPTY_INFO	/* flinfo indicates empty blocks */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE0, \
+					  CONFIG_SYS_FLASH_BASE1 }
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PROMPT		"VExpress# "
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_HUSH_PARSER
+
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot args buffer */
+#define CONFIG_CMD_SOURCE
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING		1
+#define CONFIG_SYS_MAXARGS		16	/* max command args */
+
+#endif /* VEXPRESS_COMMON_H */
diff --git a/qemu/roms/u-boot/include/configs/vf610twr.h b/qemu/roms/u-boot/include/configs/vf610twr.h
new file mode 100644
index 000000000..500fd2fd6
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/vf610twr.h
@@ -0,0 +1,218 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale Vybrid vf610twr board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+#include <config_cmd_default.h>
+
+#define CONFIG_VF610
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_MACH_TYPE		4146
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* Enable passing of ATAGs */
+#define CONFIG_CMDLINE_TAG
+
+#define CONFIG_CMD_FUSE
+#ifdef CONFIG_CMD_FUSE
+#define CONFIG_MXC_OCOTP
+#endif
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_FSL_LPUART
+#define LPUART_BASE			UART1_BASE
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SYS_UART_PORT		(1)
+#define CONFIG_BAUDRATE			115200
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_ESDHC_NUM	1
+
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE		RMII
+#define CONFIG_FEC_MXC_PHYADDR          0
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_SPD_BUS_NUM		0
+
+#define CONFIG_BOOTDELAY		3
+
+#define CONFIG_LOADADDR			0x82000000
+#define CONFIG_SYS_TEXT_BASE		0x3f008000
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"image=zImage\0" \
+	"console=ttyLP1\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_file=vf610-twr.dtb\0" \
+	"fdt_addr=0x81000000\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
+	"mmcpart=1\0" \
+	"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
+	"update_sd_firmware_filename=u-boot.imx\0" \
+	"update_sd_firmware=" \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"if mmc dev ${mmcdev}; then "	\
+			"if ${get_cmd} ${update_sd_firmware_filename}; then " \
+				"setexpr fw_sz ${filesize} / 0x200; " \
+				"setexpr fw_sz ${fw_sz} + 1; "	\
+				"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
+			"fi; "	\
+		"fi\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs " \
+	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+		"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	   "mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "else run netboot; " \
+			   "fi; " \
+		   "fi; " \
+	   "else run netboot; fi"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#undef CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE		\
+			(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START	0x80010000
+#define CONFIG_SYS_MEMTEST_END		0x87C00000
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+/*
+ * Stack sizes
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE		(128 * 1024)	/* regular stack */
+
+/* Physical memory map */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			(0x80000000)
+#define PHYS_SDRAM_SIZE			(128 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_SIZE			(8 * 1024)
+#define CONFIG_ENV_IS_IN_MMC
+
+#define CONFIG_ENV_OFFSET		(12 * 64 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/virtlab2.h b/qemu/roms/u-boot/include/configs/virtlab2.h
new file mode 100644
index 000000000..0457cdfcf
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/virtlab2.h
@@ -0,0 +1,469 @@
+/*
+ * (C) Copyright 2006-2008
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC823		1	/* This is a MPC823 CPU		*/
+#define CONFIG_VIRTLAB2		1	/* ...on a virtlab2 module	*/
+#define	CONFIG_TQM8xxL		1
+
+#define	CONFIG_SYS_TEXT_BASE	0x40000000
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#define CONFIG_SYS_SMC_RXBUFLEN	128
+#define CONFIG_SYS_MAXIDLE	10
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+
+#define	CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_8xx\0"					\
+	"hostname=virtlab2\0"						\
+	"bootfile=virtlab2/uImage\0"					\
+	"fdt_addr=40040000\0"						\
+	"kernel_addr=40060000\0"					\
+	"ramdisk_addr=40200000\0"					\
+	"u-boot=virtlab2/u-image.bin\0"					\
+	"load=tftp 200000 ${u-boot}\0"					\
+	"update=prot off 40000000 +${filesize};"			\
+		"era 40000000 +${filesize};"				\
+		"cp.b 200000 40000000 ${filesize};"			\
+		"sete filesize;save\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#if defined(CONFIG_LCD)
+# undef	 CONFIG_STATUS_LED		/* disturbs display		*/
+#else
+# define CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+#endif	/* CONFIG_LCD */
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+
+#if defined(CONFIG_SPLASH_SCREEN)
+    #define CONFIG_CMD_BMP
+#endif
+
+
+#define CONFIG_NETCONSOLE
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define	CONFIG_SYS_HUSH_PARSER		1	/* use "hush" command parser	*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#else
+#define	CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	*/
+#endif
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CONFIG_SYS_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0x40000000
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+
+/* use CFI flash driver */
+#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
+#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	71	/* max number of sectors on one chip */
+
+#define	CONFIG_ENV_IS_IN_FLASH	1
+#define	CONFIG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
+#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+
+#define CONFIG_MISC_INIT_R		/* Make sure to remap flashes correctly */
+
+/*-----------------------------------------------------------------------
+ * Dynamic MTD partition support
+ */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
+#define MTDIDS_DEFAULT		"nor0=TQM8xxL-0"
+
+#define MTDPARTS_DEFAULT	"mtdparts=TQM8xxL-0:256k(u-boot),"	\
+						"128k(dtb),"		\
+						"1664k(kernel),"	\
+						"2m(rootfs),"		\
+						"4m(data)"
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CONFIG_SYS_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef	CONFIG_CAN_DRIVER
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#else	/* we must activate GPL5 in the SIUMCR for CAN */
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ */
+#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#define CONFIG_SYS_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define CONFIG_IDE_PREINIT	1	/* Use preinit IDE hook */
+#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CONFIG_SYS_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
+
+#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
+#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
+#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00
+
+#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
+#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#ifndef	CONFIG_CAN_DRIVER
+#define	CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
+#define	CONFIG_SYS_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CONFIG_SYS_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CONFIG_SYS_OR3_CAN		(CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CONFIG_SYS_BR3_CAN		((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
+					BR_PS_8 | BR_MS_UPMB | BR_V )
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ *	gclk	  CPU clock (not bus clock!)
+ *	Trefresh  Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096  Rows from SDRAM example configuration
+ * 1000  factor s -> ms
+ *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
+ *    4  Number of refresh cycles per period
+ *   64  Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ * 50 MHz => 50.000.000 / Divider =  98
+ * 66 Mhz => 66.000.000 / Divider = 129
+ * 80 Mhz => 80.000.000 / Divider = 156
+ */
+
+#define CONFIG_SYS_PTA_PER_CLK	((4096 * 32 * 1000) / (4 * 64))
+#define CONFIG_SYS_MAMR_PTA	98
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ */
+#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+/* Map peripheral control registers on CS4 */
+#define CONFIG_SYS_PERIPHERAL_BASE 0xA0000000
+#define CONFIG_SYS_PERIPHERAL_OR_AM 0xFFFF8000 /* 32 kB address mask */
+#define CONFIG_SYS_OR4_PRELIM (CONFIG_SYS_PERIPHERAL_OR_AM | OR_TRLX | OR_CSNT_SAM | \
+						OR_SCY_2_CLK)
+#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_PERIPHERAL_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
+#define PCMCIA_CTRL (CONFIG_SYS_PERIPHERAL_BASE + 0xB00)
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_HWCONFIG		1
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/vision2.h b/qemu/roms/u-boot/include/configs/vision2.h
new file mode 100644
index 000000000..6891bf8b1
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/vision2.h
@@ -0,0 +1,205 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the MX51-3Stack Freescale board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+
+#define CONFIG_MX51	/* in a mx51 */
+#define CONFIG_SYS_TEXT_BASE	0x97800000
+
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_CMDLINE_TAG	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_BOARD_LATE_INIT
+
+#ifndef MACH_TYPE_TTC_VISION2
+#define MACH_TYPE_TTC_VISION2	2775
+#endif
+#define CONFIG_MACH_TYPE	MACH_TYPE_TTC_VISION2
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	UART3_BASE
+#define CONFIG_MXC_GPIO
+#define CONFIG_MXC_SPI
+#define CONFIG_HW_WATCHDOG
+
+ /*
+ * SPI Configs
+ * */
+#define CONFIG_FSL_SF
+#define CONFIG_CMD_SF
+
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+
+/*
+ * Use gpio 4 pin 25 as chip select for SPI flash
+ * This corresponds to gpio 121
+ */
+#define CONFIG_SF_DEFAULT_CS	(1 | (121 << 8))
+#define CONFIG_SF_DEFAULT_MODE   SPI_MODE_0
+#define CONFIG_SF_DEFAULT_SPEED  25000000
+
+#define CONFIG_ENV_SPI_CS	(1 | (121 << 8))
+#define CONFIG_ENV_SPI_BUS      0
+#define CONFIG_ENV_SPI_MAX_HZ	25000000
+#define CONFIG_ENV_SPI_MODE	SPI_MODE_0
+
+#define CONFIG_ENV_OFFSET       (6 * 64 * 1024)
+#define CONFIG_ENV_SECT_SIZE    (1 * 64 * 1024)
+#define CONFIG_ENV_SIZE		(4 * 1024)
+
+#define CONFIG_FSL_ENV_IN_SF
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+
+/* PMIC Controller */
+#define CONFIG_POWER
+#define CONFIG_POWER_SPI
+#define CONFIG_POWER_FSL
+#define CONFIG_FSL_PMIC_BUS	0
+#define CONFIG_FSL_PMIC_CS	0
+#define CONFIG_FSL_PMIC_CLK	2500000
+#define CONFIG_FSL_PMIC_MODE	SPI_MODE_0
+#define CONFIG_FSL_PMIC_BITLEN	32
+#define CONFIG_RTC_MC13XXX
+
+/*
+ * MMC Configs
+ */
+#define CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	(0x70004000)
+#define CONFIG_SYS_FSL_ESDHC_NUM	1
+
+#define CONFIG_MMC
+
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+#define CONFIG_CMD_DATE
+
+/*
+ * Eth Configs
+ */
+#define CONFIG_HAS_ETH1
+#define CONFIG_MII
+
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE				FEC_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR		0x1F
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX			3
+#define CONFIG_BAUDRATE				115200
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_SPI
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY        3
+
+#define CONFIG_LOADADDR	0x90800000	/* loadaddr env var */
+
+#define	CONFIG_EXTRA_ENV_SETTINGS	\
+		"netdev=eth0\0"		\
+		"loadaddr=0x90800000\0"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP
+#define	CONFIG_SYS_PROMPT		"Vision II U-boot > "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		64	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START	0x90000000
+#define CONFIG_SYS_MEMTEST_END		0x10000
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS		2
+#define PHYS_SDRAM_1			CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE		(256 * 1024 * 1024)
+#define PHYS_SDRAM_2			CSD1_BASE_ADDR
+#define PHYS_SDRAM_2_SIZE		(256 * 1024 * 1024)
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* 166 MHz DDR RAM */
+#define CONFIG_SYS_DDR_CLKSEL		0
+#define CONFIG_SYS_CLKTL_CBCDR		0x19239100
+#define CONFIG_SYS_MAIN_PWR_ON
+
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * Framebuffer and LCD
+ */
+#define CONFIG_PREBOOT
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_IPUV3
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_CMD_BMP
+#define CONFIG_BMP_16BPP
+#define CONFIG_IPUV3_CLK	133000000
+
+#endif				/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/vl_ma2sc.h b/qemu/roms/u-boot/include/configs/vl_ma2sc.h
new file mode 100644
index 000000000..14c6e675c
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/vl_ma2sc.h
@@ -0,0 +1,439 @@
+/*
+ * (C) Copyright 2009-2012
+ * Jens Scharsig  <esw@bus-elekronik.de>
+ * BuS Elektronik GmbH & Co. KG
+ *
+ * Configuation settings for the VL_MA2SC board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*--------------------------------------------------------------------------*/
+
+#define CONFIG_ARM926EJS		/* This is an ARM926EJS Core	*/
+#define CONFIG_AT91FAMILY
+#define CONFIG_AT91SAM9263		/* It's an Atmel AT91SAM9263 SoC*/
+#define CONFIG_VL_MA2SC			/* on an VL_MA2SC Board	*/
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_MISC_INIT_R
+
+#include <asm/hardware.h>
+
+#define MACH_TYPE_VL_MA2SC		2412
+#define CONFIG_MACH_TYPE		MACH_TYPE_VL_MA2SC
+
+#define CONFIG_SYS_DCACHE_OFF
+
+#ifdef CONFIG_RAMLOAD
+#define CONFIG_SYS_TEXT_BASE		0x21000000
+#else
+#define CONFIG_SYS_TEXT_BASE		0x00000000
+#endif
+#define CONFIG_SYS_LOAD_ADDR		0x21000000  /* default load address */
+
+#define CONFIG_IDENT_STRING		" on MiS Activ 2"
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AT91_GPIO
+
+#if !defined(CONFIG_SYS_USE_NANDFLASH) && !defined(CONFIG_RAMLOAD)
+#define CONFIG_SYS_USE_NORFLASH
+#define CONFIG_SYS_USE_BOOT_NORFLASH
+#endif
+
+#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#ifndef CONFIG_SYS_USE_BOOT_NORFLASH
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+/*
+ * Hardware drivers
+ */
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_WATCHDOG
+
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
+#define CONFIG_USART_ID			ATMEL_ID_SYS
+
+/* LCD */
+#define CONFIG_LCD
+#define CONFIG_ATMEL_LCD
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SYS_BLACK_ON_WHITE
+#define LCD_BPP				LCD_COLOR8
+#define CONFIG_ATMEL_LCD_BGR555
+
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_BOOTDELAY		3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_LOADS
+
+#define CONFIG_CMD_BMP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_MD5SUM
+#define CONFIG_CMD_SHA1SUM
+/*
+#define CONFIG_CMD_SPI
+*/
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_USB
+
+#define	CONFIG_SYS_LONGHELP
+#define CONFIG_MD5
+#define	CONFIG_SHA1
+
+/*----------------------------------------------------------------------------
+ * Hardware confuguration
+ *---------------------------------------------------------------------------*/
+
+/* USB */
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00a00000	/* UHP_BASE */
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9263"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+#define CONFIG_USB_STORAGE
+#define CONFIG_AT91C_PQFP_UHPBUG
+
+/* I2C-Bus */
+
+#define CONFIG_SYS_I2C_SPEED			50000
+#define CONFIG_SYS_I2C_SLAVE			0		/* not used */
+
+#ifndef CONFIG_HARD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SOFT			/* I2C bit-banged */
+#define CONFIG_SYS_I2C_SOFT_SPEED	CONFIG_SYS_I2C_SPEED
+#define CONFIG_SYS_I2C_SOFT_SLAVE	CONFIG_SYS_I2C_SLAVE
+
+/* Software  I2C driver configuration */
+#define I2C_DELAY	udelay(2500000/CONFIG_SYS_I2C_SPEED)
+
+#define AT91_PIN_SDA	(1<<4)		/* AT91C_PIO_PB4 */
+#define AT91_PIN_SCL	(1<<5)		/* AT91C_PIO_PB5 */
+
+#define I2C_INIT	i2c_init_board();
+#define I2C_ACTIVE	writel(AT91_PIN_SDA, &pio->piob.mddr);
+#define I2C_TRISTATE	writel(AT91_PIN_SDA, &pio->piob.mder);
+#define I2C_READ	((readl(&pio->piob.pdsr) & AT91_PIN_SDA) != 0)
+#define I2C_SDA(bit)						\
+	do {							\
+		if (bit)					\
+			writel(AT91_PIN_SDA, &pio->piob.sodr);	\
+		else						\
+			writel(AT91_PIN_SDA, &pio->piob.codr);	\
+	} while (0);
+#define I2C_SCL(bit)						\
+	do {							\
+		if (bit)					\
+			writel(AT91_PIN_SCL, &pio->piob.sodr);	\
+		else						\
+			writel(AT91_PIN_SCL, &pio->piob.codr);	\
+	} while (0);
+#endif
+
+/* I2C-RTC */
+
+#ifdef CONFIG_CMD_DATE
+#define CONFIG_RTC_DS1338
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68
+#endif
+
+/* EEPROM */
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+
+/* define PDC[31:16] as DATA[31:16] */
+#define CONFIG_SYS_PIOD_PDR_VAL1	0xFFFF0000
+#define CONFIG_SYS_PIOD_PPUDR_VAL	0xFFFF0000
+
+/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
+#define CONFIG_SYS_MATRIX_EBI0CSA_VAL					\
+	(AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V |	\
+	 AT91_MATRIX_CSA_EBI_CS1A)
+
+/* user reset enable */
+#define CONFIG_SYS_RSTC_RMR_VAL			\
+		(AT91_RSTC_KEY |		\
+		AT91_RSTC_MR_URSTEN |		\
+		AT91_RSTC_MR_ERSTL(15))
+
+/* Disable Watchdog */
+#define CONFIG_SYS_WDTC_WDMR_VAL				\
+		(AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT |	\
+		 AT91_WDT_MR_WDV(0xFFF) |			\
+		 AT91_WDT_MR_WDDIS |				\
+		 AT91_WDT_MR_WDD(0xFFF))
+
+/* clocks */
+
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock */
+
+#define MHZ180
+#if defined(MHZ199)
+/* 199,8994 MHZ */
+#define MASTER_PLL_MUL		911
+#define MASTER_PLL_DIV		56
+#define MASTER_PLL_OUT		2
+#elif defined(MHZ180)
+/* 180 MHZ */
+#define MASTER_PLL_MUL		1875
+#define MASTER_PLL_DIV		128
+#define MASTER_PLL_OUT		2
+#elif defined(MHZTEST)
+/* Test MHZ */
+#define CONFIG_DISPLAY_CPUINFO
+#define MASTER_PLL_MUL		8
+#define MASTER_PLL_DIV		1
+#define MASTER_PLL_OUT		2
+#else
+/* 176.9472 MHZ */
+#define MASTER_PLL_MUL		72
+#define MASTER_PLL_DIV		5
+#define MASTER_PLL_OUT		2
+#endif
+
+#define CONFIG_SYS_MOR_VAL					\
+	(AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255))
+
+#define CONFIG_SYS_PLLAR_VAL					\
+	(AT91_PMC_PLLAR_29 |					\
+	AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) |			\
+	AT91_PMC_PLLXR_PLLCOUNT(63) |				\
+	AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) |		\
+	AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))
+
+/* PCK/2 = MCK Master Clock from PLLA */
+#define	CONFIG_SYS_MCKR1_VAL		\
+	(AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 |	\
+	 AT91_PMC_MCKR_MDIV_2)
+
+/* PCK/2 = MCK Master Clock from PLLA */
+#define	CONFIG_SYS_MCKR2_VAL		\
+	(AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 |	\
+	AT91_PMC_MCKR_MDIV_2)
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE		0x20000000
+#define CONFIG_SYS_SDRAM_SIZE		0x04000000  /* 64 megs */
+#define CONFIG_SYS_INIT_SP_ADDR		0x00504000  /* use internal SRAM0 */
+
+#define CONFIG_SYS_SDRC_MR_VAL1		0
+#define CONFIG_SYS_SDRC_TR_VAL1		700
+#define CONFIG_SYS_SDRC_CR_VAL						\
+		(AT91_SDRAMC_NC_9 |					\
+		 AT91_SDRAMC_NR_13 |					\
+		 AT91_SDRAMC_NB_4 |					\
+		 AT91_SDRAMC_CAS_3 |					\
+		 AT91_SDRAMC_DBW_32 |					\
+		 (2 <<  8) |		/* Write Recovery Delay */	\
+		 (7 << 12) |		/* Row Cycle Delay */		\
+		 (2 << 16) |		/* Row Precharge Delay */	\
+		 (2 << 20) |		/* Row to Column Delay */	\
+		 (5 << 24) |		/* Active to Precharge Delay */	\
+		 (8 << 28))		/* Exit Self Refresh to Active Delay */
+
+#define CONFIG_SYS_SDRC_MDR_VAL		AT91_SDRAMC_MD_SDRAM
+#define CONFIG_SYS_SDRC_MR_VAL2		AT91_SDRAMC_MODE_PRECHARGE
+#define CONFIG_SYS_SDRAM_VAL1		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL3		AT91_SDRAMC_MODE_REFRESH
+#define CONFIG_SYS_SDRAM_VAL2		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL3		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL4		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL5		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL6		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL7		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL8		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRAM_VAL9		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL4		AT91_SDRAMC_MODE_LMR
+#define CONFIG_SYS_SDRAM_VAL10		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_MR_VAL5		AT91_SDRAMC_MODE_NORMAL
+#define CONFIG_SYS_SDRAM_VAL11		0		/* SDRAM_BASE */
+#define CONFIG_SYS_SDRC_TR_VAL2		1200		/* SDRAM_TR */
+#define CONFIG_SYS_SDRAM_VAL12		0		/* SDRAM_BASE */
+
+/* NOR flash */
+
+#define CONFIG_FLASH_SHOW_PROGRESS	45
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define PHYS_FLASH_1			0x10000000
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_MAX_FLASH_SECT	256
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x00060000)
+
+/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
+#define CONFIG_SYS_SMC0_SETUP0_VAL				\
+	(AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) |	\
+	 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
+#define CONFIG_SYS_SMC0_PULSE0_VAL				\
+	(AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) |	\
+	 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
+#define CONFIG_SYS_SMC0_CYCLE0_VAL	\
+	(AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
+#define CONFIG_SYS_SMC0_MODE0_VAL				\
+	(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |		\
+	 AT91_SMC_MODE_DBW_16 |					\
+	 AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6))
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CONFIG_SYS_NAND_DBW_8		1
+#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)	/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)	/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_ENABLE_PIN	GPIO_PIN_PD(15)
+#define CONFIG_SYS_NAND_READY_PIN	GPIO_PIN_PB(0)
+#endif
+
+/* Ethernet */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_MULTI
+#define CONFIG_NET_RETRY_COUNT		5
+#define CONFIG_AT91_WANTS_COMMON_PHY
+
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
+
+#define CONFIG_SYS_LOAD_ADDR		0x21000000  /* default load address */
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		0x21e00000
+
+/* Address and size of Primary Environment Sector */
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SIZE			0x20000
+#else
+#define CONFIG_ENV_SIZE			0x2000
+#endif
+
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{312500, 230400, 115200, 19200, \
+						38400, 57600, 9600 }
+
+#define CONFIG_SYS_PROMPT	"U-Boot> "
+#define CONFIG_SYS_CBSIZE	512		/* Console I/O Buffer Size */
+#define CONFIG_SYS_MAXARGS	32		/* max number of command args */
+#define CONFIG_SYS_PBSIZE	\
+	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		\
+	ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
+
+#ifndef CONFIG_RAMLOAD
+#define CONFIG_BOOTCOMMAND		"run nfsboot"
+#endif
+#define CONFIG_BOOT_RETRY_TIME		-1
+#define CONFIG_BOOT_RETRY_MIN		15
+
+#define CONFIG_NFSBOOTCOMMAND						\
+		"dhcp $(copy_addr) $(kernelname);"			\
+		"run bootargsdefaults;"					\
+		"set bootargs $(bootargs) boot=nfs "			\
+		";echo $(bootargs)"					\
+	";bootm"
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"ubootaddr=10000000\0"						\
+	"splashimage=10080000\0"					\
+	"kerneladdr=100A0000\0"						\
+	"kernelsize=00800000\0"						\
+	"minifsaddr=108A0000\0"						\
+	"minifssize=00060000\0"						\
+	"rootfsaddr=10900000\0"						\
+	"copy_addr=20200000\0"						\
+	"rootfssize=01700000\0"						\
+	"kernelname=uImage_vl_ma2sc\0"					\
+	"bootargsdefaults=set bootargs "				\
+		"console=ttyS0,115200 "					\
+		"video=atmel_lcdfb "					\
+		"mem=62M "						\
+		"panic=10 "						\
+		"boardrevison=\\\"${revision}\\\" "			\
+		"uboot=\\\"${ver}\\\" "					\
+		"\0"							\
+	"update_all=run update_kernel;run update_root;"			\
+		"run update_splash; run update_uboot\0"			\
+	"update_kernel=protect off $(kerneladdr) +$(kernelsize);"	\
+		"dhcp $(copy_addr) $(kernelname);"			\
+		"erase $(kerneladdr) +$(kernelsize);"			\
+		"cp.b $(fileaddr) $(kerneladdr) $(filesize);"		\
+		"protect on $(kerneladdr) +$(kernelsize)"		\
+		"\0"							\
+	"update_root=protect off $(rootfsaddr) +$(rootfssize);"		\
+		"dhcp $(copy_addr) vl_ma2sc.root;"			\
+		"erase $(rootfsaddr) +$(rootfssize);"			\
+		"cp.b $(fileaddr) $(rootfsaddr) $(filesize);"		\
+		"\0"							\
+	"update_splash=protect off $(splashimage) +20000;"		\
+		"dhcp $(copy_addr) splash_vl_ma2sc.bmp;"		\
+		"erase $(splashimage) +20000;"				\
+		"cp.b $(fileaddr) 10080000 $(filesize);"		\
+		"protect on $(splashimage) +20000\0"			\
+	"update_uboot=protect off 10000000 1005FFFF;"			\
+		"dhcp $(copy_addr) u-boot_vl_ma2sc;"			\
+		"erase 10000000 1005FFFF;"				\
+		"cp.b $(fileaddr) $(ubootaddr) $(filesize);"		\
+		"protect on 10000000 1005FFFF;reset\0"			\
+	"emergency=run bootargsdefaults;"				\
+		"set bootargs $(bootargs) root=initramfs boot=emergency " \
+		";bootm $(kerneladdr)\0"				\
+	"netemergency=run bootargsdefaults;"				\
+		"dhcp $(copy_addr) $(kernelname);"			\
+		"set bootargs $(bootargs) root=initramfs boot=emergency " \
+		";bootm $(copy_addr)\0"					\
+	"norboot=run bootargsdefaults;"					\
+		"set bootargs $(bootargs) root=initramfs boot=local quiet " \
+		";bootm $(kerneladdr)\0"				\
+	"nandboot=run bootargsdefaults;"				\
+		"set bootargs $(bootargs) root=initramfs boot=nand "	\
+		";bootm $(kerneladdr)\0"				\
+	"setnorboot=set bootcmd 'run norboot'; set bootdelay 1;save\0"	\
+	"clearenv=protect off 10060000 1007FFFF;"			\
+		"erase 10060000 1007FFFF;reset\0"			\
+	" "
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/vme8349.h b/qemu/roms/u-boot/include/configs/vme8349.h
new file mode 100644
index 000000000..175311cad
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/vme8349.h
@@ -0,0 +1,613 @@
+/*
+ * esd vme8349 U-Boot configuration file
+ * Copyright (c) 2008, 2009 esd gmbh Hannover Germany
+ *
+ * (C) Copyright 2006-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * reinhard.arlt@esd-electronics.de
+ * Based on the MPC8349EMDS config.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * vme8349 board configuration file.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Top level Makefile configuration choices
+ */
+#ifdef CONFIG_CADDY2
+#define VME_CADDY2
+#endif
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1	/* E300 Family */
+#define CONFIG_MPC834x		1	/* MPC834x family */
+#define CONFIG_MPC8349		1	/* MPC8349 specific */
+#define CONFIG_VME8349		1	/* ESD VME8349 board specific */
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFF00000
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_PCI
+/* Don't enable PCI2 on vme834x - it doesn't exist physically. */
+#undef CONFIG_MPC83XX_PCI2		/* support for 2nd PCI controller */
+
+#define CONFIG_PCI_66M
+#ifdef CONFIG_PCI_66M
+#define CONFIG_83XX_CLKIN	66000000	/* in Hz */
+#else
+#define CONFIG_83XX_CLKIN	33000000	/* in Hz */
+#endif
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#ifdef CONFIG_PCI_66M
+#define CONFIG_SYS_CLK_FREQ	66000000
+#define HRCWL_CSB_TO_CLKIN	HRCWL_CSB_TO_CLKIN_4X1
+#else
+#define CONFIG_SYS_CLK_FREQ	33000000
+#define HRCWL_CSB_TO_CLKIN	HRCWL_CSB_TO_CLKIN_8X1
+#endif
+#endif
+
+#define CONFIG_SYS_IMMR		0xE0000000
+
+#undef CONFIG_SYS_DRAM_TEST			/* memory test, takes time */
+#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00100000
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_DDR_ECC			/* only for ECC DDR module */
+#define CONFIG_DDR_ECC_CMD		/* use DDR ECC user commands */
+#define CONFIG_SPD_EEPROM
+#define SPD_EEPROM_ADDRESS		0x54
+#define CONFIG_SYS_READ_SPD		vme8349_read_spd
+#define CONFIG_SYS_83XX_DDR_USES_CS0	/* esd; Fsl board uses CS2/CS3 */
+
+/*
+ * 32-bit data path mode.
+ *
+ * Please note that using this mode for devices with the real density of 64-bit
+ * effectively reduces the amount of available memory due to the effect of
+ * wrapping around while translating address to row/columns, for example in the
+ * 256MB module the upper 128MB get aliased with contents of the lower
+ * 128MB); normally this define should be used for devices with real 32-bit
+ * data path.
+ */
+#undef CONFIG_DDR_32BIT
+
+#define CONFIG_SYS_DDR_BASE		0x00000000	/* DDR is sys memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN \
+					| DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
+#define CONFIG_DDR_2T_TIMING
+#define CONFIG_SYS_DDRCDR		(DDRCDR_DHC_EN \
+					| DDRCDR_ODT \
+					| DDRCDR_Q_DRN)
+					/* 0x80080001 */
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER			        /* use the CFI driver */
+#ifdef VME_CADDY2
+#define CONFIG_SYS_FLASH_BASE		0xffc00000	/* start of FLASH   */
+#define CONFIG_SYS_FLASH_SIZE		4		/* flash size in MB */
+#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | \
+					 BR_PS_16 |	/*  16bit */ \
+					 BR_MS_GPCM |	/*  MSEL = GPCM */ \
+					 BR_V)		/* valid */
+
+#define CONFIG_SYS_OR0_PRELIM		(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+					| OR_GPCM_XAM \
+					| OR_GPCM_CSNT \
+					| OR_GPCM_ACS_DIV2 \
+					| OR_GPCM_XACS \
+					| OR_GPCM_SCY_15 \
+					| OR_GPCM_TRLX_SET \
+					| OR_GPCM_EHTR_SET \
+					| OR_GPCM_EAD)
+					/* 0xffc06ff7 */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_4MB)
+#else
+#define CONFIG_SYS_FLASH_BASE		0xf8000000	/* start of FLASH   */
+#define CONFIG_SYS_FLASH_SIZE		128		/* flash size in MB */
+#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | \
+					 BR_PS_16 |	/*  16bit */ \
+					 BR_MS_GPCM |	/*  MSEL = GPCM */ \
+					 BR_V)		/* valid */
+
+#define CONFIG_SYS_OR0_PRELIM		(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+					| OR_GPCM_XAM \
+					| OR_GPCM_CSNT \
+					| OR_GPCM_ACS_DIV2 \
+					| OR_GPCM_XACS \
+					| OR_GPCM_SCY_15 \
+					| OR_GPCM_TRLX_SET \
+					| OR_GPCM_EHTR_SET \
+					| OR_GPCM_EAD)
+					/* 0xf8006ff7 */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_128MB)
+#endif
+/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
+
+#define CONFIG_SYS_WINDOW1_BASE		0xf0000000
+#define CONFIG_SYS_BR1_PRELIM		(CONFIG_SYS_WINDOW1_BASE \
+					| BR_PS_32 \
+					| BR_MS_GPCM \
+					| BR_V)
+					/* 0xF0001801 */
+#define CONFIG_SYS_OR1_PRELIM		(OR_AM_256KB \
+					| OR_GPCM_SETA)
+					/* 0xfffc0208 */
+#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_WINDOW1_BASE
+#define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_256KB)
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device*/
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase TO (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write TO (ms) */
+
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xF7000000	/* Initial RAM addr */
+#define CONFIG_SYS_INIT_RAM_SIZE		0x1000		/* size */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB */
+#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)	/* Malloc size */
+
+/*
+ * Local Bus LCRR and LBCR regs
+ *    LCRR:  no DLL bypass, Clock divider is 4
+ * External Local Bus rate is
+ *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
+ */
+#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_4
+#define CONFIG_SYS_LBC_LBCR	0x00000000
+
+#undef CONFIG_SYS_LB_SDRAM	/* if board has SDRAM on local bus */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1		(CONFIG_SYS_IMMR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2		(CONFIG_SYS_IMMR + 0x4600)
+
+#define CONFIG_CMDLINE_EDITING		/* add command line history	*/
+#define CONFIG_AUTO_COMPLETE		/* add autocompletion support */
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
+/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
+
+#define CONFIG_SYS_I2C_8574_ADDR2       0x20    /* I2C1, PCF8574 */
+
+/* TSEC */
+#define CONFIG_SYS_TSEC1_OFFSET	0x24000
+#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
+#define CONFIG_SYS_TSEC2_OFFSET 0x25000
+#define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
+#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS		0xE2000000
+#define CONFIG_SYS_PCI1_IO_SIZE		0x00100000	/* 1M */
+
+#define CONFIG_SYS_PCI2_MEM_BASE	0xA0000000
+#define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BASE
+#define CONFIG_SYS_PCI2_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI2_MMIO_BASE	0xB0000000
+#define CONFIG_SYS_PCI2_MMIO_PHYS	CONFIG_SYS_PCI2_MMIO_BASE
+#define CONFIG_SYS_PCI2_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI2_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI2_IO_PHYS		0xE2100000
+#define CONFIG_SYS_PCI2_IO_SIZE		0x00100000	/* 1M */
+
+#if defined(CONFIG_PCI)
+
+#define PCI_64BIT
+#define PCI_ONE_PCI1
+#if defined(PCI_64BIT)
+#undef PCI_ALL_PCI1
+#undef PCI_TWO_PCI1
+#undef PCI_ONE_PCI1
+#endif
+
+#ifndef VME_CADDY2
+#endif
+#define CONFIG_PCI_PNP		/* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+	#define PCI_ENET0_IOADDR	0xFIXME
+	#define PCI_ENET0_MEMADDR	0xFIXME
+	#define PCI_IDSEL_NUMBER	0xFIXME
+#endif
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID	0x1957	/* Freescale */
+
+#endif	/* CONFIG_PCI */
+
+/*
+ * TSEC configuration
+ */
+#ifdef VME_CADDY2
+#define CONFIG_E1000
+#else
+#define CONFIG_TSEC_ENET		/* TSEC ethernet support */
+#endif
+
+#if defined(CONFIG_TSEC_ENET)
+
+#define CONFIG_GMII			/* MII PHY management */
+#define CONFIG_TSEC1
+#define CONFIG_TSEC1_NAME	"TSEC0"
+#define CONFIG_TSEC2
+#define CONFIG_TSEC2_NAME	"TSEC1"
+#define CONFIG_PHY_M88E1111
+#define TSEC1_PHY_ADDR		0x08
+#define TSEC2_PHY_ADDR		0x10
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME		"TSEC0"
+
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#ifndef CONFIG_SYS_RAMBOOT
+	#define CONFIG_ENV_IS_IN_FLASH
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0xc0000)
+	#define CONFIG_ENV_SECT_SIZE	0x20000	/* 128K(one sector) for env */
+	#define CONFIG_ENV_SIZE		0x2000
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+#else
+	#define CONFIG_SYS_NO_FLASH		/* Flash is not usable now */
+	#define CONFIG_ENV_IS_NOWHERE		/* Store ENV in memory only */
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
+	#define CONFIG_ENV_SIZE		0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DATE
+#define CONFIG_SYS_RTC_BUS_NUM  0x01
+#define CONFIG_SYS_I2C_RTC_ADDR	0x32
+#define CONFIG_RTC_RX8025
+#define CONFIG_CMD_TSI148
+
+#if defined(CONFIG_PCI)
+    #define CONFIG_CMD_PCI
+#endif
+
+#if defined(CONFIG_SYS_RAMBOOT)
+    #undef CONFIG_CMD_ENV
+    #undef CONFIG_CMD_LOADS
+#endif
+
+#define CONFIG_CMD_ELF
+/* Pass Ethernet MAC to VxWorks */
+#define CONFIG_SYS_VXWORKS_MAC_PTR	0x000043f0
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+
+#if defined(CONFIG_CMD_KGDB)
+	#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
+#else
+	#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
+#endif
+
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	16		/* max num of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Argument Buf Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 256 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(256 << 20)	/* Init Memory map for Linux*/
+
+#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
+
+#define CONFIG_SYS_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_1X1 |\
+	HRCWL_CSB_TO_CLKIN |\
+	HRCWL_VCO_1X2 |\
+	HRCWL_CORE_TO_CSB_2X1)
+
+#if defined(PCI_64BIT)
+#define CONFIG_SYS_HRCW_HIGH (\
+	HRCWH_PCI_HOST |\
+	HRCWH_64_BIT_PCI |\
+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_PCI2_ARBITER_DISABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0X00000100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_TSEC1M_IN_GMII |\
+	HRCWH_TSEC2M_IN_GMII)
+#else
+#define CONFIG_SYS_HRCW_HIGH (\
+	HRCWH_PCI_HOST |\
+	HRCWH_32_BIT_PCI |\
+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_PCI2_ARBITER_ENABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0X00000100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_TSEC1M_IN_GMII |\
+	HRCWH_TSEC2M_IN_GMII)
+#endif
+
+/* System IO Config */
+#define CONFIG_SYS_SICRH 0
+#define CONFIG_SYS_SICRL SICRL_LDP_A
+
+#define CONFIG_SYS_HID0_INIT	0x000000000
+#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
+				 HID0_ENABLE_INSTRUCTION_CACHE)
+
+#define CONFIG_SYS_HID2		HID2_HBE
+
+#define CONFIG_SYS_GPIO1_PRELIM
+#define CONFIG_SYS_GPIO1_DIR	0x00100000
+#define CONFIG_SYS_GPIO1_DAT	0x00100000
+
+#define CONFIG_SYS_GPIO2_PRELIM
+#define CONFIG_SYS_GPIO2_DIR	0x78900000
+#define CONFIG_SYS_GPIO2_DAT	0x70100000
+
+#define CONFIG_HIGH_BATS		/* High BATs supported */
+
+/* DDR @ 0x00000000 */
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
+				 BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
+				 BATU_VS | BATU_VP)
+
+/* PCI @ 0x80000000 */
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | \
+				 BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \
+				 BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | \
+				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \
+				 BATU_VS | BATU_VP)
+#else
+#define CONFIG_SYS_IBAT1L	(0)
+#define CONFIG_SYS_IBAT1U	(0)
+#define CONFIG_SYS_IBAT2L	(0)
+#define CONFIG_SYS_IBAT2U	(0)
+#endif
+
+#ifdef CONFIG_MPC83XX_PCI2
+#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | \
+				 BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \
+				 BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | \
+				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \
+				 BATU_VS | BATU_VP)
+#else
+#define CONFIG_SYS_IBAT3L	(0)
+#define CONFIG_SYS_IBAT3U	(0)
+#define CONFIG_SYS_IBAT4L	(0)
+#define CONFIG_SYS_IBAT4U	(0)
+#endif
+
+/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
+#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_IMMR | BATL_PP_RW | \
+				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_IMMR | BATU_BL_256M | \
+				 BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_IBAT6L	(0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#if (CONFIG_SYS_DDR_SIZE == 512)
+#define CONFIG_SYS_IBAT7L	(CONFIG_SYS_SDRAM_BASE+0x10000000 | \
+				 BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT7U	(CONFIG_SYS_SDRAM_BASE+0x10000000 | \
+				 BATU_BL_256M | BATU_VS | BATU_VP)
+#else
+#define CONFIG_SYS_IBAT7L	(0)
+#define CONFIG_SYS_IBAT7U	(0)
+#endif
+
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
+#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
+#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
+#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
+#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#endif
+
+#define CONFIG_HOSTNAME		VME8349
+#define CONFIG_ROOTPATH		"/tftpboot/rootfs"
+#define CONFIG_BOOTFILE		"uImage"
+
+#define CONFIG_LOADADDR		800000	/* def location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS			/* boot command will set bootargs */
+
+#define CONFIG_BAUDRATE	 9600
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"hostname=vme8349\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr}\0"				\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"	\
+		"bootm\0"						\
+	"load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0"		\
+	"update=protect off fff00000 fff3ffff; "			\
+		"era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
+	"upd=run load update\0"						\
+	"fdtaddr=780000\0"						\
+	"fdtfile=vme8349.dtb\0"						\
+	""
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"setenv bootargs root=/dev/nfs rw "				\
+		"nfsroot=$serverip:$rootpath "				\
+		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"	\
+							"$netdev:off "	\
+		"console=$consoledev,$baudrate $othbootargs;"		\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+	"setenv bootargs root=/dev/ram rw "				\
+		"console=$consoledev,$baudrate $othbootargs;"		\
+	"tftp $ramdiskaddr $ramdiskfile;"				\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#ifndef __ASSEMBLY__
+int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen,
+		     unsigned char *buffer, int len);
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/vpac270.h b/qemu/roms/u-boot/include/configs/vpac270.h
new file mode 100644
index 000000000..c6d47635b
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/vpac270.h
@@ -0,0 +1,334 @@
+/*
+ * Voipac PXA270 configuration file
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef	__CONFIG_H
+#define	__CONFIG_H
+
+/*
+ * High Level Board Configuration Options
+ */
+#define	CONFIG_CPU_PXA27X		1	/* Marvell PXA270 CPU */
+#define	CONFIG_VPAC270		1	/* Voipac PXA270 board */
+#define	CONFIG_SYS_TEXT_BASE	0xa0000000
+
+#ifdef	CONFIG_ONENAND
+#define	CONFIG_SPL
+#define	CONFIG_SPL_ONENAND_SUPPORT
+#define	CONFIG_SPL_ONENAND_LOAD_ADDR	0x2000
+#define	CONFIG_SPL_ONENAND_LOAD_SIZE	\
+	(512 * 1024 - CONFIG_SPL_ONENAND_LOAD_ADDR)
+#define	CONFIG_SPL_TEXT_BASE	0x5c000000
+#define	CONFIG_SPL_LDSCRIPT	"board/vpac270/u-boot-spl.lds"
+#endif
+
+/*
+ * Environment settings
+ */
+#define	CONFIG_ENV_OVERWRITE
+#define	CONFIG_SYS_MALLOC_LEN		(128*1024)
+#define	CONFIG_ARCH_CPU_INIT
+#define	CONFIG_BOOTCOMMAND						\
+	"if mmc init && fatload mmc 0 0xa4000000 uImage; then "		\
+		"bootm 0xa4000000; "					\
+	"fi; "								\
+	"if usb reset && fatload usb 0 0xa4000000 uImage; then "	\
+		"bootm 0xa4000000; "					\
+	"fi; "								\
+	"if ide reset && fatload ide 0 0xa4000000 uImage; then "	\
+		"bootm 0xa4000000; "					\
+	"fi; "								\
+	"bootm 0x60000;"
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"update_onenand="						\
+		"onenand erase 0x0 0x80000 ; "				\
+		"onenand write 0xa0000000 0x0 0x80000"
+
+#define	CONFIG_BOOTARGS			"console=tty0 console=ttyS0,115200"
+#define	CONFIG_TIMESTAMP
+#define	CONFIG_BOOTDELAY		2	/* Autoboot delay */
+#define	CONFIG_CMDLINE_TAG
+#define	CONFIG_SETUP_MEMORY_TAGS
+#define	CONFIG_LZMA			/* LZMA compression support */
+#define	CONFIG_OF_LIBFDT
+
+/*
+ * Serial Console Configuration
+ */
+#define	CONFIG_PXA_SERIAL
+#define	CONFIG_FFUART			1
+#define CONFIG_CONS_INDEX		3
+#define	CONFIG_BAUDRATE			115200
+
+/*
+ * Bootloader Components Configuration
+ */
+#include <config_cmd_default.h>
+
+#define	CONFIG_CMD_NET
+#define	CONFIG_CMD_ENV
+#undef	CONFIG_CMD_IMLS
+#define	CONFIG_CMD_MMC
+#define	CONFIG_CMD_USB
+#undef	CONFIG_LCD
+#define	CONFIG_CMD_IDE
+
+#ifdef	CONFIG_ONENAND
+#undef	CONFIG_CMD_FLASH
+#define	CONFIG_CMD_ONENAND
+#else
+#define	CONFIG_CMD_FLASH
+#undef	CONFIG_CMD_ONENAND
+#endif
+
+/*
+ * Networking Configuration
+ *  chip on the Voipac PXA270 board
+ */
+#ifdef	CONFIG_CMD_NET
+#define	CONFIG_CMD_PING
+#define	CONFIG_CMD_DHCP
+
+#define	CONFIG_DRIVER_DM9000		1
+#define	CONFIG_DM9000_BASE		0x08000300	/* CS2 */
+#define	DM9000_IO			(CONFIG_DM9000_BASE)
+#define	DM9000_DATA			(CONFIG_DM9000_BASE + 4)
+#define	CONFIG_NET_RETRY_COUNT		10
+
+#define	CONFIG_BOOTP_BOOTFILESIZE
+#define	CONFIG_BOOTP_BOOTPATH
+#define	CONFIG_BOOTP_GATEWAY
+#define	CONFIG_BOOTP_HOSTNAME
+#endif
+
+/*
+ * MMC Card Configuration
+ */
+#ifdef	CONFIG_CMD_MMC
+#define	CONFIG_MMC
+#define	CONFIG_GENERIC_MMC
+#define	CONFIG_PXA_MMC_GENERIC
+#define	CONFIG_SYS_MMC_BASE		0xF0000000
+#define	CONFIG_CMD_FAT
+#define	CONFIG_CMD_EXT2
+#define	CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * KGDB
+ */
+#ifdef	CONFIG_CMD_KGDB
+#define	CONFIG_KGDB_BAUDRATE		230400	/* kgdb serial port speed */
+#endif
+
+/*
+ * HUSH Shell Configuration
+ */
+#define	CONFIG_SYS_HUSH_PARSER		1
+
+#define	CONFIG_SYS_LONGHELP
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define	CONFIG_SYS_PROMPT		"$ "
+#else
+#endif
+#define	CONFIG_SYS_CBSIZE		256
+#define	CONFIG_SYS_PBSIZE		\
+	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define	CONFIG_SYS_MAXARGS		16
+#define	CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+#define	CONFIG_SYS_DEVICE_NULLDEV	1
+#define	CONFIG_CMDLINE_EDITING		1
+#define	CONFIG_AUTO_COMPLETE		1
+
+/*
+ * Clock Configuration
+ */
+#define	CONFIG_SYS_CPUSPEED		0x190		/* 312MHz */
+
+
+/*
+ * DRAM Map
+ */
+#define	CONFIG_NR_DRAM_BANKS		2		/* 2 banks of DRAM */
+#define	PHYS_SDRAM_1			0xa0000000	/* SDRAM Bank #1 */
+#define	PHYS_SDRAM_1_SIZE		0x08000000	/* 128 MB */
+
+#ifdef	CONFIG_RAM_256M
+#define	PHYS_SDRAM_2			0x80000000	/* SDRAM Bank #2 */
+#define	PHYS_SDRAM_2_SIZE		0x08000000	/* 128 MB */
+#endif
+
+#define	CONFIG_SYS_DRAM_BASE		0xa0000000	/* CS0 */
+#ifdef	CONFIG_RAM_256M
+#define	CONFIG_SYS_DRAM_SIZE		0x10000000	/* 256 MB DRAM */
+#else
+#define	CONFIG_SYS_DRAM_SIZE		0x08000000	/* 128 MB DRAM */
+#endif
+
+#define	CONFIG_SYS_MEMTEST_START	0xa0400000	/* memtest works on */
+#define	CONFIG_SYS_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM */
+
+#define	CONFIG_SYS_LOAD_ADDR		PHYS_SDRAM_1
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define	CONFIG_SYS_INIT_SP_ADDR		0x5c010000
+
+/*
+ * NOR FLASH
+ */
+#define	CONFIG_SYS_MONITOR_BASE		0x0
+#define	CONFIG_SYS_MONITOR_LEN		0x80000
+#define	CONFIG_ENV_ADDR			\
+			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define	CONFIG_ENV_SIZE			0x20000
+#define	CONFIG_ENV_SECT_SIZE		0x20000
+
+#if	defined(CONFIG_CMD_FLASH)	/* NOR */
+#define	PHYS_FLASH_1			0x00000000	/* Flash Bank #1 */
+
+#ifdef	CONFIG_RAM_256M
+#define	PHYS_FLASH_2			0x02000000	/* Flash Bank #2 */
+#endif
+
+#define	CONFIG_SYS_FLASH_CFI
+#define	CONFIG_FLASH_CFI_DRIVER		1
+
+#define	CONFIG_SYS_MAX_FLASH_SECT	(4 + 255)
+#ifdef	CONFIG_RAM_256M
+#define	CONFIG_SYS_MAX_FLASH_BANKS	2
+#define	CONFIG_SYS_FLASH_BANKS_LIST	{ PHYS_FLASH_1, PHYS_FLASH_2 }
+#else
+#define	CONFIG_SYS_MAX_FLASH_BANKS	1
+#define	CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+#endif
+
+#define	CONFIG_SYS_FLASH_ERASE_TOUT	(25*CONFIG_SYS_HZ)
+#define	CONFIG_SYS_FLASH_WRITE_TOUT	(25*CONFIG_SYS_HZ)
+
+#define	CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+#define	CONFIG_SYS_FLASH_PROTECTION		1
+
+#define	CONFIG_ENV_IS_IN_FLASH		1
+
+#elif	defined(CONFIG_CMD_ONENAND)	/* OneNAND */
+#define	CONFIG_SYS_NO_FLASH
+#define	CONFIG_SYS_ONENAND_BASE		0x00000000
+
+#define	CONFIG_ENV_IS_IN_ONENAND	1
+
+#else	/* No flash */
+#define	CONFIG_SYS_NO_FLASH
+#define	CONFIG_SYS_ENV_IS_NOWHERE
+#endif
+
+/*
+ * IDE
+ */
+#ifdef	CONFIG_CMD_IDE
+#define	CONFIG_LBA48
+#undef	CONFIG_IDE_LED
+#undef	CONFIG_IDE_RESET
+
+#define	__io
+
+#define	CONFIG_SYS_IDE_MAXBUS		1
+#define	CONFIG_SYS_IDE_MAXDEVICE	1
+
+#define	CONFIG_SYS_ATA_BASE_ADDR	0x0c000000
+#define	CONFIG_SYS_ATA_IDE0_OFFSET	0x0
+
+#define	CONFIG_SYS_ATA_DATA_OFFSET	0x120
+#define	CONFIG_SYS_ATA_REG_OFFSET	0x120
+#define	CONFIG_SYS_ATA_ALT_OFFSET	0x120
+
+#define	CONFIG_SYS_ATA_STRIDE		2
+#endif
+
+/*
+ * GPIO settings
+ */
+#define	CONFIG_SYS_GPSR0_VAL	0x01308800
+#define	CONFIG_SYS_GPSR1_VAL	0x00cf0000
+#define	CONFIG_SYS_GPSR2_VAL	0x922ac000
+#define	CONFIG_SYS_GPSR3_VAL	0x0161e800
+
+#define	CONFIG_SYS_GPCR0_VAL	0x00010000
+#define	CONFIG_SYS_GPCR1_VAL	0x0
+#define	CONFIG_SYS_GPCR2_VAL	0x0
+#define	CONFIG_SYS_GPCR3_VAL	0x0
+
+#define	CONFIG_SYS_GPDR0_VAL	0xcbb18800
+#define	CONFIG_SYS_GPDR1_VAL	0xfccfa981
+#define	CONFIG_SYS_GPDR2_VAL	0x922affff
+#define	CONFIG_SYS_GPDR3_VAL	0x0161e904
+
+#define	CONFIG_SYS_GAFR0_L_VAL	0x00100000
+#define	CONFIG_SYS_GAFR0_U_VAL	0xa5da8510
+#define	CONFIG_SYS_GAFR1_L_VAL	0x6992901a
+#define	CONFIG_SYS_GAFR1_U_VAL	0xaaa5a0aa
+#define	CONFIG_SYS_GAFR2_L_VAL	0xaaaaaaaa
+#define	CONFIG_SYS_GAFR2_U_VAL	0x4109a401
+#define	CONFIG_SYS_GAFR3_L_VAL	0x54010310
+#define	CONFIG_SYS_GAFR3_U_VAL	0x00025401
+
+#define	CONFIG_SYS_PSSR_VAL	0x30
+
+/*
+ * Clock settings
+ */
+#define	CONFIG_SYS_CKEN		0x00500240
+#define	CONFIG_SYS_CCCR		0x02000290
+
+/*
+ * Memory settings
+ */
+#define	CONFIG_SYS_MSC0_VAL	0x3ffc95f9
+#define	CONFIG_SYS_MSC1_VAL	0x02ccf974
+#define	CONFIG_SYS_MSC2_VAL	0x00000000
+#ifdef	CONFIG_RAM_256M
+#define	CONFIG_SYS_MDCNFG_VAL	0x8ad30ad3
+#else
+#define	CONFIG_SYS_MDCNFG_VAL	0x88000ad3
+#endif
+#define	CONFIG_SYS_MDREFR_VAL	0x201fe01e
+#define	CONFIG_SYS_MDMRS_VAL	0x00000000
+#define	CONFIG_SYS_FLYCNFG_VAL	0x00000000
+#define	CONFIG_SYS_SXCNFG_VAL	0x40044004
+#define	CONFIG_SYS_MEM_BUF_IMP	0x0f
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define	CONFIG_SYS_MECR_VAL	0x00000001
+#define	CONFIG_SYS_MCMEM0_VAL	0x00014307
+#define	CONFIG_SYS_MCMEM1_VAL	0x00014307
+#define	CONFIG_SYS_MCATT0_VAL	0x0001c787
+#define	CONFIG_SYS_MCATT1_VAL	0x0001c787
+#define	CONFIG_SYS_MCIO0_VAL	0x0001430f
+#define	CONFIG_SYS_MCIO1_VAL	0x0001430f
+
+/*
+ * LCD
+ */
+#ifdef	CONFIG_LCD
+#define	CONFIG_VOIPAC_LCD
+#endif
+
+/*
+ * USB
+ */
+#ifdef	CONFIG_CMD_USB
+#define	CONFIG_USB_OHCI_NEW
+#define	CONFIG_SYS_USB_OHCI_CPU_INIT
+#define	CONFIG_SYS_USB_OHCI_BOARD_INIT
+#define	CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+#define	CONFIG_SYS_USB_OHCI_REGS_BASE	0x4C000000
+#define	CONFIG_SYS_USB_OHCI_SLOT_NAME	"vpac270"
+#define	CONFIG_USB_STORAGE
+#endif
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/walnut.h b/qemu/roms/u-boot/include/configs/walnut.h
new file mode 100644
index 000000000..8b803a2ee
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/walnut.h
@@ -0,0 +1,214 @@
+/*
+ * (C) Copyright 2000-2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
+#define CONFIG_WALNUT		1	/* ...on a WALNUT board		*/
+					/* ...or on a SYCAMORE board	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
+
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME		walnut
+#include "amcc-common.h"
+
+#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
+
+#define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll	*/
+
+/*
+ * Default environment variables
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_AMCC_DEF_ENV						\
+	CONFIG_AMCC_DEF_ENV_POWERPC					\
+	CONFIG_AMCC_DEF_ENV_PPC_OLD					\
+	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
+	"kernel_addr=fff80000\0"					\
+	"ramdisk_addr=fff80000\0"					\
+	""
+
+#define CONFIG_PHY_ADDR		1	/* PHY address			*/
+#define CONFIG_HAS_ETH0		1
+
+#define CONFIG_RTC_DS174x	1	/* use DS1743 RTC in Walnut	*/
+
+/*
+ * Commands additional to the ones defined in amcc-common.h
+ */
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
+
+#define CONFIG_SPD_EEPROM      1       /* use SPD EEPROM for setup    */
+
+/*
+ * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
+ * The Linux BASE_BAUD define should match this configuration.
+ *    baseBaud = cpuClock/(uartDivisor*16)
+ * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * set Linux BASE_BAUD to 403200.
+ */
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* external serial clock */
+#undef	CONFIG_SYS_405_UART_ERRATA_59	       /* 405GP/CR Rev. D silicon */
+#define CONFIG_SYS_BASE_BAUD	    691200
+
+/*-----------------------------------------------------------------------
+ * I2C stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
+
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR	(0xa8>>1)
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0		/* configure ar pci adapter	*/
+#define PCI_HOST_FORCE	1		/* configure as pci host	*/
+#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
+
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_HOST PCI_HOST_FORCE	/* select pci host function	*/
+#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
+					/* resource configuration	*/
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
+#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
+#define CONFIG_SYS_PCI_PTM1MS	0x80000001	/* 2GB, enable hard-wired to 1	*/
+#define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
+#define CONFIG_SYS_PCI_PTM2LA	0x00000000	/* disabled			*/
+#define CONFIG_SYS_PCI_PTM2MS	0x00000000	/* disabled			*/
+#define CONFIG_SYS_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ */
+#define CONFIG_SYS_FLASH_BASE		0xFFF80000
+
+/*
+ * Define here the location of the environment variables (FLASH or NVRAM).
+ * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
+ *	 supported for backward compatibility.
+ */
+#if 1
+#define CONFIG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars	*/
+#else
+#define CONFIG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define FLASH_BASE0_PRELIM	CONFIG_SYS_FLASH_BASE	/* FLASH bank #0		*/
+#define FLASH_BASE1_PRELIM	0		/* FLASH bank #1		*/
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#define CONFIG_SYS_FLASH_ADDR0		0x5555
+#define CONFIG_SYS_FLASH_ADDR1		0x2aaa
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned char
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	0x10000		/* size of one complete sector	*/
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+#endif /* CONFIG_ENV_IS_IN_FLASH */
+
+/*-----------------------------------------------------------------------
+ * NVRAM organization
+ */
+#define CONFIG_SYS_NVRAM_BASE_ADDR	0xf0000000	/* NVRAM base address	*/
+#define CONFIG_SYS_NVRAM_SIZE		0x1ff8		/* NVRAM size	*/
+
+#ifdef CONFIG_ENV_IS_IN_NVRAM
+#define CONFIG_ENV_SIZE		0x1000		/* Size of Environment vars	*/
+#define CONFIG_ENV_ADDR		\
+	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE)	/* Env	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash Bank 0) initialization					*/
+#define CONFIG_SYS_EBC_PB0AP		0x9B015480
+#define CONFIG_SYS_EBC_PB0CR		0xFFF18000  /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit	*/
+
+#define CONFIG_SYS_EBC_PB1AP		0x02815480
+#define CONFIG_SYS_EBC_PB1CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
+
+#define CONFIG_SYS_EBC_PB2AP		0x04815A80
+#define CONFIG_SYS_EBC_PB2CR		0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit	*/
+
+#define CONFIG_SYS_EBC_PB3AP		0x01815280
+#define CONFIG_SYS_EBC_PB3CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/
+
+#define CONFIG_SYS_EBC_PB7AP		0x01815280
+#define CONFIG_SYS_EBC_PB7CR		0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit	*/
+
+/*-----------------------------------------------------------------------
+ * External peripheral base address
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_SYS_KEY_REG_BASE_ADDR	0xF0100000
+#define CONFIG_SYS_IR_REG_BASE_ADDR	0xF0200000
+#define CONFIG_SYS_FPGA_REG_BASE_ADDR	0xF0300000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area
+ */
+#define CONFIG_SYS_INIT_DCACHE_CS	4	/* use cs # 4 for data cache memory    */
+
+#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000  /* inside of SDRAM			   */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000	/* Size of used area in RAM	       */
+#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Definitions for Serial Presence Detect EEPROM address
+ * (to get SDRAM settings)
+ */
+#define SPD_EEPROM_ADDRESS	0x50
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/wandboard.h b/qemu/roms/u-boot/include/configs/wandboard.h
new file mode 100644
index 000000000..6c74c7295
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/wandboard.h
@@ -0,0 +1,241 @@
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Wandboard.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/gpio.h>
+#include <linux/sizes.h>
+
+#define CONFIG_MX6
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define MACH_TYPE_WANDBOARD		4412
+#define CONFIG_MACH_TYPE		MACH_TYPE_WANDBOARD
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(10 * SZ_1M)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART1_BASE
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+
+/* Command definition */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_CMD_BMODE
+#define CONFIG_CMD_SETEXPR
+
+#define CONFIG_BOOTDELAY		5
+
+#define CONFIG_SYS_MEMTEST_START	0x10000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 500 * SZ_1M)
+#define CONFIG_LOADADDR			0x12000000
+#define CONFIG_SYS_TEXT_BASE		0x17800000
+
+/* MMC Configuration */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+/* Ethernet Configuration */
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE		RGMII
+#define CONFIG_ETHPRIME			"FEC"
+#define CONFIG_FEC_MXC_PHYADDR		1
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ATHEROS
+
+/* Framebuffer */
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_IPUV3
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_IPUV3_CLK 260000000
+#define CONFIG_IMX_HDMI
+
+#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
+#define CONFIG_DEFAULT_FDT_FILE		"imx6dl-wandboard.dtb"
+#elif defined(CONFIG_MX6Q)
+#define CONFIG_DEFAULT_FDT_FILE		"imx6q-wandboard.dtb"
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"image=zImage\0" \
+	"console=ttymxc0\0" \
+	"splashpos=m,m\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"fdt_addr=0x18000000\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
+	"mmcpart=1\0" \
+	"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
+	"update_sd_firmware_filename=u-boot.imx\0" \
+	"update_sd_firmware=" \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"if mmc dev ${mmcdev}; then "	\
+			"if ${get_cmd} ${update_sd_firmware_filename}; then " \
+				"setexpr fw_sz ${filesize} / 0x200; " \
+				"setexpr fw_sz ${fw_sz} + 1; "	\
+				"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
+			"fi; "	\
+		"fi\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs " \
+	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+		"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	   "mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "else run netboot; " \
+			   "fi; " \
+		   "fi; " \
+	   "else run netboot; fi"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE		256
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	       16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+#define CONFIG_CMDLINE_EDITING
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_SIZE			(8 * 1024)
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET		(6 * 64 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+#endif
+
+#endif			       /* __CONFIG_H * */
diff --git a/qemu/roms/u-boot/include/configs/whistler.h b/qemu/roms/u-boot/include/configs/whistler.h
new file mode 100644
index 000000000..9e09f03d5
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/whistler.h
@@ -0,0 +1,72 @@
+/*
+ *  (C) Copyright 2010-2012
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+#include "tegra20-common.h"
+
+/* Enable fdt support for Whistler. Flash the image in u-boot-dtb.bin */
+#define CONFIG_DEFAULT_DEVICE_TREE	tegra20-whistler
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
+/* High-level configuration options */
+#define V_PROMPT		"Tegra20 (Whistler) # "
+#define CONFIG_TEGRA_BOARD_STRING	"NVIDIA Whistler"
+
+/* Board-specific serial config */
+#define CONFIG_TEGRA_ENABLE_UARTA
+#define CONFIG_TEGRA_UARTA_UAA_UAB
+#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTA_BASE
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_WHISTLER
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* I2C */
+#define CONFIG_SYS_I2C_TEGRA
+#define CONFIG_SYS_I2C_INIT_BOARD
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_TEGRA_MMC
+#define CONFIG_CMD_MMC
+
+/*
+ * Environment in eMMC, at the end of 2nd "boot sector". Note: This assumes
+ * the user plugged the standard 8GB MoviNAND card into J29/HSMMC/POP. If
+ * they didn't, the boot sector layout may be different. However, use of that
+ * particular card is standard practice as far as I know.
+ */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_SYS_MMC_ENV_PART 2
+
+/* USB Host support */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_TEGRA
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB
+
+/* USB networking support */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+
+/* General networking support */
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/wireless_space.h b/qemu/roms/u-boot/include/configs/wireless_space.h
new file mode 100644
index 000000000..2070a9b1b
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/wireless_space.h
@@ -0,0 +1,183 @@
+/*
+ * Copyright (C) 2011 Albert ARIBAUD <albert.u.boot@aribaud.net>
+ *
+ * Based on the netspace_v2 code which is
+ * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CONFIG_WIRELESS_SPACE_H
+#define _CONFIG_WIRELESS_SPACE_H
+
+/*
+ * Machine number definition
+ */
+#define MACH_TYPE_WIRELESS_SPACE	2500 /* is missing in mach-types.h */
+#define CONFIG_MACH_TYPE		MACH_TYPE_WIRELESS_SPACE
+#define CONFIG_IDENT_STRING		" Wireless Space"
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_FEROCEON_88FR131		/* CPU Core subversion */
+#define CONFIG_KIRKWOOD			/* SoC Family Name */
+/* SoC name */
+#define CONFIG_KW88F6281
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH		/* no NOR or SPI flash */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_USB
+
+/*
+ * Core clock definition
+ */
+#define CONFIG_SYS_TCLK			166000000 /* 166MHz */
+
+/*
+ * SDRAM configuration
+ */
+#define CONFIG_NR_DRAM_BANKS		1
+
+/*
+ * Different SDRAM configuration and size for some of the boards derived
+ * from the Network Space v2
+ */
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/* Remove or override few declarations from mv-common.h */
+#undef CONFIG_RBTREE
+#undef CONFIG_SYS_IDE_MAXBUS
+#undef CONFIG_SYS_IDE_MAXDEVICE
+#define CONFIG_SYS_IDE_MAXBUS           1
+#define CONFIG_SYS_IDE_MAXDEVICE        1
+#undef CONFIG_SYS_PROMPT
+#define CONFIG_SYS_PROMPT		"ws> "
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MISC_INIT_R /* misc_init_r() initializes MAC address */
+#define CONFIG_MVGBE_PORTS	{1, 0}	/* enable only egiga0... */
+#define PORT_SERIAL_CONTROL_VALUE 0x00A4260E /* ... tied to the switch... */
+#define CONFIG_PHY_BASE_ADR 0xa		/* ... through a 'fake' PHY */
+#define CONFIG_MII
+#undef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#define CONFIG_NETCONSOLE
+#define CONFIG_MV88E61XX_SWITCH
+#define CONFIG_MV88E61XX_MULTICHIP_ADRMODE
+#define CONFIG_MV88E61XX_CMD
+#define CONFIG_CMD_TFTPPUT
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * SATA Driver configuration
+ */
+#ifdef CONFIG_MVSATA_IDE
+#define CONFIG_SYS_ATA_IDE0_OFFSET      MV_SATA_PORT0_OFFSET
+#endif /* CONFIG_MVSATA_IDE */
+
+/*
+ * Enable GPI0 support
+ */
+#define CONFIG_KIRKWOOD_GPIO
+
+/*
+ * Enable I2C support
+ */
+#ifdef CONFIG_CMD_I2C
+/* I2C EEPROM HT24LC04 (512B - 32 pages of 16 Bytes) */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4 /* 16-byte page size */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1 /* 8-bit device address */
+#endif /* CONFIG_CMD_I2C */
+
+/*
+ * Partition support
+ */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+
+/*
+ * File systems support
+ */
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+
+/*
+ * Use the HUSH parser
+ */
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Console configuration
+ */
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+/*
+ * Enable device tree support
+ */
+#define CONFIG_OF_LIBFDT
+
+/*
+ * Environment variables configurations
+ */
+
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SECT_SIZE		0x20000	/* 128KB */
+#define CONFIG_ENV_SIZE			0x20000	/* 128KB */
+#define CONFIG_ENV_OFFSET		0x80000	/* env starts here */
+
+/*
+ * Board-specific command to make using buttons etc easier
+ */
+
+#define CONFIG_WIRELESS_SPACE_CMD
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_PREBOOT
+
+#define CONFIG_BOOTARGS "console=ttyS0,115200"
+
+#define CONFIG_BOOTCOMMAND					\
+	"if run usbload || run diskload; then bootm; fi"
+
+#define CONFIG_EXTRA_ENV_SETTINGS				\
+	"stdin=serial\0"					\
+	"stdout=serial\0"					\
+	"stderr=serial\0"					\
+	"bootfile=uImage\0"					\
+	"loadaddr=0x800000\0"					\
+	"autoload=no\0"						\
+	"netconsole="						\
+		"set stdin $stdin,nc; "				\
+		"set stdout $stdout,nc; "			\
+		"set stderr $stderr,nc;\0"			\
+	"diskload=ide reset && "				\
+		"ext2load ide 0:1 $loadaddr /boot/$bootfile\0"	\
+	"usbload=usb start && "					\
+		"fatload usb 0:1 $loadaddr /boot/$bootfile\0"	\
+	"preboot="						\
+		"dhcp && run netconsole\0"
+
+#endif /* _CONFIG_WIRELESS_SPACE_H */
diff --git a/qemu/roms/u-boot/include/configs/woodburn.h b/qemu/roms/u-boot/include/configs/woodburn.h
new file mode 100644
index 000000000..c14f7d47d
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/woodburn.h
@@ -0,0 +1,21 @@
+/*
+ * (C) Copyright 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Configuration for the woodburn board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+#include "woodburn_common.h"
+
+/* Set TEXT at the beginning of the NOR flash */
+#define CONFIG_SYS_TEXT_BASE	0xA0000000
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#endif				/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/woodburn_common.h b/qemu/roms/u-boot/include/configs/woodburn_common.h
new file mode 100644
index 000000000..695bc230c
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/woodburn_common.h
@@ -0,0 +1,296 @@
+/*
+ * (C) Copyright 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Configuration for the woodburn board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __WOODBURN_COMMON_CONFIG_H
+#define __WOODBURN_COMMON_CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+
+ /* High Level Configuration Options */
+#define CONFIG_ARM1136	/* This is an arm1136 CPU core */
+#define CONFIG_MX35
+#define CONFIG_MX35_HCLK_FREQ	24000000
+
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
+#define CONFIG_DISPLAY_CPUINFO
+
+/* Only in case the value is not present in mach-types.h */
+#ifndef MACH_TYPE_FLEA3
+#define MACH_TYPE_FLEA3                3668
+#endif
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_FLEA3
+
+/* This is required to setup the ESDC controller */
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+#define CONFIG_REVISION_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 1024 * 1024)
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_SPD_BUS_NUM		0
+#define CONFIG_MXC_SPI
+#define CONFIG_MXC_GPIO
+
+/* PMIC Controller */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_FSL
+#define CONFIG_PMIC_FSL_MC13892
+#define CONFIG_SYS_FSL_PMIC_I2C_ADDR	0x8
+#define CONFIG_RTC_MC13XXX
+
+
+/* mmc driver */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_ESDHC_NUM	1
+
+/*
+ * UART (console)
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	UART1_BASE
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_BAUDRATE		115200
+
+/*
+ * Command definition
+ */
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_DNS
+
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_CACHE
+
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+
+#define CONFIG_CMD_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+
+#define CONFIG_CMD_GPIO
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_NET_RETRY_COUNT	100
+
+#define CONFIG_BOOTDELAY	3
+
+#define CONFIG_LOADADDR		0x80800000	/* loadaddr env var */
+
+
+/*
+ * Ethernet on SOC (FEC)
+ */
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE	FEC_BASE_ADDR
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_FEC_MXC_PHYADDR	0x1
+
+#define CONFIG_MII
+#define CONFIG_DISCOVER_PHY
+
+#define CONFIG_ARP_TIMEOUT	200UL
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP	/* undef to save memory */
+#define CONFIG_SYS_PROMPT	"woodburn U-Boot > "
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_HUSH_PARSER	/* Use the HUSH parser */
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START	0	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x10000
+
+#undef	CONFIG_SYS_CLKS_IN_HZ	/* everything, incl board info, in Hz */
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128 * 1024)	/* regular stack */
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM_1		CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE	(256 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE		CSD0_BASE_ADDR
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(LOW_LEVEL_SRAM_STACK - \
+						IRAM_BASE_ADDR - \
+						GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR		(IRAM_BASE_ADDR + \
+					CONFIG_SYS_GBL_DATA_OFFSET)
+
+/*
+ * MTD Command for mtdparts
+ */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_FLASH_CFI_MTD
+#define CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT		"nand0=mxc_nand,nor0=physmap-flash.0"
+#define MTDPARTS_DEFAULT	"mtdparts=mxc_nand:50m(root1)," \
+				"32m(rootfb)," \
+				"64m(pcache)," \
+				"64m(app1)," \
+				"10m(app2),-(spool);" \
+				"physmap-flash.0:512k(u-boot),64k(env1)," \
+				"64k(env2),3776k(kernel1),3776k(kernel2)"
+
+/*
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_FLASH_BASE		CS0_BASE_ADDR
+#define CONFIG_SYS_MAX_FLASH_BANKS 1	/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512	/* max number of sectors on one chip */
+/* Monitor at beginning of flash */
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+
+#define CONFIG_ENV_SECT_SIZE	(128 * 1024)
+#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + \
+				CONFIG_SYS_MONITOR_LEN)
+
+#define CONFIG_ENV_IS_IN_FLASH
+
+/*
+ * CFI FLASH driver setup
+ */
+#define CONFIG_SYS_FLASH_CFI		/* Flash memory is CFI compliant */
+#define CONFIG_FLASH_CFI_DRIVER
+
+/* A non-standard buffered write algorithm */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	/* faster */
+#define CONFIG_SYS_FLASH_PROTECTION	/* Use hardware sector protection */
+
+/*
+ * NAND FLASH driver setup
+ */
+#define CONFIG_NAND_MXC
+#define CONFIG_NAND_MXC_V1_1
+#define CONFIG_MXC_NAND_REGS_BASE	(NFC_BASE_ADDR)
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		(NFC_BASE_ADDR)
+#define CONFIG_MXC_NAND_HWECC
+#define CONFIG_SYS_NAND_LARGEPAGE
+
+#if 0
+#define CONFIG_MTD_DEBUG
+#define CONFIG_MTD_DEBUG_VERBOSE	7
+#endif
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/*
+ * Default environment and default scripts
+ * to update uboot and load kernel
+ */
+#define xstr(s)	str(s)
+#define str(s)	#s
+
+#define CONFIG_HOSTNAME woodburn
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip_sta=setenv bootargs ${bootargs} "			\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0"		\
+	"addip=if test -n ${ipdyn};then run addip_dyn;"			\
+		"else run addip_sta;fi\0"	\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
+	"addtty=setenv bootargs ${bootargs}"				\
+		" console=ttymxc0,${baudrate}\0"			\
+	"addmisc=setenv bootargs ${bootargs} ${misc}\0"			\
+	"loadaddr=80800000\0"						\
+	"kernel_addr_r=80800000\0"					\
+	"hostname=" xstr(CONFIG_HOSTNAME) "\0"				\
+	"bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0"			\
+	"ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0"		\
+	"flash_self=run ramargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"flash_nfs=run nfsargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr}\0"				\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
+		"run nfsargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr_r}\0"				\
+	"net_self_load=tftp ${kernel_addr_r} ${bootfile};"		\
+		"tftp ${ramdisk_addr_r} ${ramdisk_file};\0"		\
+	"net_self=if run net_self_load;then "				\
+		"run ramargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr_r} ${ramdisk_addr_r};"		\
+		"else echo Images not loades;fi\0"			\
+	"u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0"			\
+	"load=tftp ${loadaddr} ${u-boot}\0"				\
+	"uboot_addr=" xstr(CONFIG_SYS_MONITOR_BASE) "\0"		\
+	"update=protect off ${uboot_addr} +80000;"			\
+		"erase ${uboot_addr} +80000;"				\
+		"cp.b ${loadaddr} ${uboot_addr} ${filesize}\0"		\
+	"upd=if run load;then echo Updating u-boot;if run update;"	\
+		"then echo U-Boot updated;"				\
+			"else echo Error updating u-boot !;"		\
+			"echo Board without bootloader !!;"		\
+		"fi;"							\
+		"else echo U-Boot not downloaded..exiting;fi\0"		\
+	"bootcmd=run net_nfs\0"
+
+#endif				/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/woodburn_sd.h b/qemu/roms/u-boot/include/configs/woodburn_sd.h
new file mode 100644
index 000000000..437472f3e
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/woodburn_sd.h
@@ -0,0 +1,45 @@
+/*
+ * (C) Copyright 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Configuration for the woodburn board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+#include "woodburn_common.h"
+
+/* Set TEXT in RAM */
+#define CONFIG_SYS_TEXT_BASE	0x82000000
+
+/*
+ * SPL
+ */
+#define	CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define	CONFIG_SPL_LDSCRIPT	"arch/arm/cpu/arm1136/u-boot-spl.lds"
+#define	CONFIG_SPL_LIBCOMMON_SUPPORT
+#define	CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x100 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x400 /* 512 KB */
+#define	CONFIG_SPL_GPIO_SUPPORT
+
+#define CONFIG_SPL_TEXT_BASE		0x10002300
+#define CONFIG_SPL_MAX_SIZE		(64 * 1024)	/* 8 KB for stack */
+#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
+
+#define CONFIG_SYS_SPL_MALLOC_START	0x8f000000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
+#define CONFIG_SPL_BSS_START_ADDR	0x8f080000 /* end of RAM */
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
+
+#endif				/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/x600.h b/qemu/roms/u-boot/include/configs/x600.h
new file mode 100644
index 000000000..7405419f0
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/x600.h
@@ -0,0 +1,321 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
+ *
+ * Copyright (C) 2012 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_SPEAR600				/* SPEAr600 SoC */
+#define CONFIG_X600				/* on X600 board */
+
+#include <asm/arch/hardware.h>
+
+/* Timer, HZ specific defines */
+#define CONFIG_SYS_HZ_CLOCK			8300000
+
+#define	CONFIG_SYS_TEXT_BASE			0x00800040
+#define CONFIG_SYS_FLASH_BASE			0xf8000000
+/* Reserve 8KiB for SPL */
+#define CONFIG_SPL_PAD_TO			8192	/* decimal for 'dd' */
+#define CONFIG_SYS_SPL_LEN			CONFIG_SPL_PAD_TO
+#define CONFIG_SYS_UBOOT_BASE			(CONFIG_SYS_FLASH_BASE + \
+						 CONFIG_SYS_SPL_LEN)
+#define CONFIG_SYS_MONITOR_BASE			CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN			0x60000
+
+#define CONFIG_ENV_IS_IN_FLASH
+
+/* Serial Configuration (PL011) */
+#define CONFIG_SYS_SERIAL0			0xD0000000
+#define CONFIG_SYS_SERIAL1			0xD0080000
+#define CONFIG_PL01x_PORTS			{ (void *)CONFIG_SYS_SERIAL0, \
+						(void *)CONFIG_SYS_SERIAL1 }
+#define CONFIG_PL011_SERIAL
+#define CONFIG_PL011_CLOCK			(48 * 1000 * 1000)
+#define CONFIG_CONS_INDEX			0
+#define CONFIG_BAUDRATE				115200
+#define CONFIG_SYS_BAUDRATE_TABLE		{ 9600, 19200, 38400, \
+						  57600, 115200 }
+#define CONFIG_SYS_LOADS_BAUD_CHANGE
+
+/* NOR FLASH config options */
+#define CONFIG_ST_SMI
+#define CONFIG_SYS_MAX_FLASH_BANKS		1
+#define CONFIG_SYS_FLASH_BANK_SIZE		0x01000000
+#define CONFIG_SYS_FLASH_ADDR_BASE		{ CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_MAX_FLASH_SECT		128
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_ERASE_TOUT		(3 * CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT		(3 * CONFIG_SYS_HZ)
+
+/* NAND FLASH config options */
+#define CONFIG_NAND_FSMC
+#define CONFIG_SYS_NAND_SELF_INIT
+#define CONFIG_SYS_MAX_NAND_DEVICE		1
+#define CONFIG_SYS_NAND_BASE			CONFIG_FSMC_NAND_BASE
+#define CONFIG_MTD_ECC_SOFT
+#define CONFIG_SYS_FSMC_NAND_8BIT
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* UBI/UBI config options */
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_RBTREE
+
+/* Ethernet config options */
+#define CONFIG_MII
+#define CONFIG_DESIGNWARE_ETH
+#define CONFIG_NET_MULTI
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_RESET_DELAY			10000		/* in usec */
+#define CONFIG_PHY_ADDR		0	/* PHY address */
+#define CONFIG_PHY_GIGE			/* Include GbE speed/duplex detection */
+
+#define CONFIG_SPEAR_GPIO
+
+/* I2C config options */
+#define CONFIG_HARD_I2C
+#define CONFIG_DW_I2C
+#define CONFIG_SYS_I2C_BASE			0xD0200000
+#define CONFIG_SYS_I2C_SPEED			400000
+#define CONFIG_SYS_I2C_SLAVE			0x02
+#define CONFIG_I2C_CHIPADDRESS			0x50
+
+#define CONFIG_RTC_M41T62	1
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68
+
+/* FPGA config options */
+#define CONFIG_FPGA
+#define CONFIG_FPGA_XILINX
+#define CONFIG_FPGA_SPARTAN3
+#define CONFIG_FPGA_COUNT	1
+
+/*
+ * Command support defines
+ */
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FPGA
+#define CONFIG_CMD_GPIO
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_LZO
+
+/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <config_cmd_default.h>
+
+#define CONFIG_BOOTDELAY			3
+
+#define CONFIG_SYS_HUSH_PARSER			/* Use the HUSH parser	*/
+#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+
+/*
+ * U-Boot Environment placing definitions.
+ */
+#define CONFIG_ENV_SECT_SIZE			0x00010000
+#define CONFIG_ENV_ADDR				(CONFIG_SYS_MONITOR_BASE + \
+						 CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SIZE				0x02000
+#define CONFIG_ENV_ADDR_REDUND			(CONFIG_ENV_ADDR + \
+						 CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND			(CONFIG_ENV_SIZE)
+
+/* Miscellaneous configurable options */
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_BOOT_PARAMS_ADDR			0x00000100
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_OF_LIBFDT		/* enable passing of devicetree */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_MISC_INIT_R
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_LOOPW			/* enable loopw command         */
+#define CONFIG_MX_CYCLIC		/* enable mdc/mwc commands      */
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_STOP_STR		" "
+#define CONFIG_AUTOBOOT_PROMPT			\
+		"Hit SPACE in %d seconds to stop autoboot.\n", bootdelay
+
+#define CONFIG_SYS_MEMTEST_START		0x00800000
+#define CONFIG_SYS_MEMTEST_END			0x04000000
+#define CONFIG_SYS_MALLOC_LEN			(1024 * 1024)
+#define CONFIG_IDENT_STRING			"-SPEAr"
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT			"X600> "
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_CBSIZE			256
+#define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE + \
+						 sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS			16
+#define CONFIG_SYS_BARGSIZE			CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_LOAD_ADDR			0x00800000
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+
+/* Use last 2 lwords in internal SRAM for bootcounter */
+#define CONFIG_BOOTCOUNT_LIMIT
+#define CONFIG_SYS_BOOTCOUNT_ADDR	0xd2801ff8
+
+#define CONFIG_HOSTNAME				x600
+#define CONFIG_UBI_PART				ubi0
+#define CONFIG_UBIFS_VOLUME			rootfs
+
+#define xstr(s)	str(s)
+#define str(s)	#s
+
+#define MTDIDS_DEFAULT		"nand0=nand"
+#define MTDPARTS_DEFAULT	"mtdparts=nand:64M(ubi0),64M(ubi1)"
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"u-boot_addr=1000000\0"						\
+	"u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.spr\0"			\
+	"load=tftp ${u-boot_addr} ${u-boot}\0"				\
+	"update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) " +${filesize};"\
+		"erase " xstr(CONFIG_SYS_MONITOR_BASE) " +${filesize};"	\
+		"cp.b ${u-boot_addr} " xstr(CONFIG_SYS_MONITOR_BASE)	\
+		" ${filesize};"						\
+		"protect on " xstr(CONFIG_SYS_MONITOR_BASE)		\
+		" +${filesize}\0"					\
+	"upd=run load update\0"						\
+	"ubifs=" xstr(CONFIG_HOSTNAME) "/ubifs.img\0"			\
+	"part=" xstr(CONFIG_UBI_PART) "\0"				\
+	"vol=" xstr(CONFIG_UBIFS_VOLUME) "\0"				\
+	"load_ubifs=tftp ${kernel_addr} ${ubifs}\0"			\
+	"update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}"	\
+		" ${filesize}\0"					\
+	"upd_ubifs=run load_ubifs update_ubifs\0"			\
+	"init_ubifs=nand erase.part ubi0;ubi part ${part};"		\
+		"ubi create ${vol} 4000000\0"				\
+	"netdev=eth0\0"							\
+	"rootpath=/opt/eldk-4.2/arm\0"					\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"boot_part=0\0"							\
+	"altbootcmd=if test $boot_part -eq 0;then "			\
+			"echo Switching to partition 1!;"		\
+			"setenv boot_part 1;"				\
+		"else; "						\
+			"echo Switching to partition 0!;"		\
+			"setenv boot_part 0;"				\
+		"fi;"							\
+		"saveenv;boot\0"					\
+	"ubifsargs=set bootargs ubi.mtd=ubi${boot_part} "		\
+		"root=ubi0:rootfs rootfstype=ubifs\0"			\
+	"kernel=" xstr(CONFIG_HOSTNAME) "/uImage\0"			\
+	"kernel_fs=/boot/uImage \0"					\
+	"kernel_addr=1000000\0"						\
+	"dtb=" xstr(CONFIG_HOSTNAME) "/" xstr(CONFIG_HOSTNAME) ".dtb\0"	\
+	"dtb_fs=/boot/" xstr(CONFIG_HOSTNAME) ".dtb\0"			\
+	"dtb_addr=1800000\0"						\
+	"load_kernel=tftp ${kernel_addr} ${kernel}\0"			\
+	"load_dtb=tftp ${dtb_addr} ${dtb}\0"				\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addcon=setenv bootargs ${bootargs} console=ttyAMA0,"		\
+		"${baudrate}\0"						\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
+	"net_nfs=run load_dtb load_kernel; "				\
+		"run nfsargs addip addcon addmtd addmisc;"		\
+		"bootm ${kernel_addr} - ${dtb_addr}\0"			\
+	"mtdids=" MTDIDS_DEFAULT "\0"					\
+	"mtdparts=" MTDPARTS_DEFAULT "\0"				\
+	"nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip"		\
+		" addcon addmisc addmtd;"				\
+		"bootm ${kernel_addr} - ${dtb_addr}\0"			\
+	"ubifs_mount=ubi part ubi${boot_part};ubifsmount ubi:rootfs\0"	\
+	"ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};"		\
+		"ubifsload ${dtb_addr} ${dtb_fs};\0"			\
+	"nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon "	\
+		"addmtd addmisc;bootm ${kernel_addr} - ${dtb_addr}\0"	\
+	"bootcmd=run nand_ubifs\0"					\
+	"\0"
+
+/* Stack sizes */
+#define CONFIG_STACKSIZE			(512 * 1024)
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS			1
+#define PHYS_SDRAM_1				0x00000000
+#define PHYS_SDRAM_1_MAXSIZE			0x40000000
+
+#define CONFIG_SYS_SDRAM_BASE			PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR		0xD2800000
+#define CONFIG_SYS_INIT_RAM_SIZE		0x2000
+
+#define CONFIG_SYS_INIT_SP_OFFSET		\
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_INIT_SP_ADDR			\
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/*
+ * SPL related defines
+ */
+#define CONFIG_SPL
+#define CONFIG_SPL_TEXT_BASE	0xd2800b00
+#define	CONFIG_SPL_START_S_PATH	"arch/arm/cpu/arm926ejs/spear"
+#define CONFIG_SPL_LDSCRIPT	"arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds"
+
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT	/* image.c */
+#define CONFIG_SPL_LIBGENERIC_SUPPORT	/* string.c */
+#define CONFIG_SPL_NO_PRINTF
+
+/*
+ * Please select/define only one of the following
+ * Each definition corresponds to a supported DDR chip.
+ * DDR configuration is based on the following selection
+ */
+#define CONFIG_DDR_MT47H64M16		1
+#define CONFIG_DDR_MT47H32M16		0
+#define CONFIG_DDR_MT47H128M8		0
+
+/*
+ * Synchronous/Asynchronous operation of DDR
+ *
+ * Select CONFIG_DDR_2HCLK for DDR clk = 333MHz, synchronous operation
+ * Select CONFIG_DDR_HCLK for DDR clk = 166MHz, synchronous operation
+ * Select CONFIG_DDR_PLL2 for DDR clk = PLL2, asynchronous operation
+ */
+#define CONFIG_DDR_2HCLK		1
+#define CONFIG_DDR_HCLK			0
+#define CONFIG_DDR_PLL2			0
+
+/*
+ * xxx_BOOT_SUPPORTED macro defines whether a booting type is supported
+ * or not. Modify/Add to only these macros to define new boot types
+ */
+#define USB_BOOT_SUPPORTED		0
+#define PCIE_BOOT_SUPPORTED		0
+#define SNOR_BOOT_SUPPORTED		1
+#define NAND_BOOT_SUPPORTED		1
+#define PNOR_BOOT_SUPPORTED		0
+#define TFTP_BOOT_SUPPORTED		0
+#define UART_BOOT_SUPPORTED		0
+#define SPI_BOOT_SUPPORTED		0
+#define I2C_BOOT_SUPPORTED		0
+#define MMC_BOOT_SUPPORTED		0
+
+#endif  /* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/xaeniax.h b/qemu/roms/u-boot/include/configs/xaeniax.h
new file mode 100644
index 000000000..2999d1b0f
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/xaeniax.h
@@ -0,0 +1,543 @@
+/*
+ * (C) Copyright 2004-2005
+ * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+ *
+ * (C) Copyright 2004
+ * Vincent Dubey, Xa SA, vincent.dubey@xa-ch.com
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.ne
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Configuation settings for the xaeniax board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_CPU_PXA25X		1	/* This is an PXA255 CPU    */
+#define CONFIG_XAENIAX		1	/* on a xaeniax board	    */
+#define	CONFIG_SYS_TEXT_BASE	0x0
+
+#define CONFIG_BOARD_LATE_INIT
+
+/* we will never enable dcache, because we have to setup MMU first */
+#define CONFIG_SYS_DCACHE_OFF
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_PXA_SERIAL
+#define CONFIG_BTUART	       1       /* we use BTUART on XAENIAX */
+#define CONFIG_CONS_INDEX	4
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
+
+#define CONFIG_BAUDRATE		115200
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SNTP
+
+#undef CONFIG_CMD_DTT
+
+
+#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
+#define CONFIG_NETMASK		255.255.255.0
+#define CONFIG_IPADDR		192.168.68.201
+#define CONFIG_SERVERIP		192.168.68.62
+
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTCOMMAND	"bootm 0x00100000"
+#define CONFIG_BOOTARGS		"console=ttyS1,115200"
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	115200			/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Size of malloc() pool; this lives below the uppermost 128 KiB which are
+ * used for the RAM copy of the uboot code
+ */
+#define CONFIG_SYS_MALLOC_LEN	    (CONFIG_ENV_SIZE + 128*1024)
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP				/* undef to save memory	*/
+#define CONFIG_SYS_HUSH_PARSER		1
+
+
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT		"u-boot$ "	/* Monitor Command Prompt */
+#else
+#define CONFIG_SYS_PROMPT		"u-boot=> "	/* Monitor Command Prompt */
+#endif
+#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
+#define CONFIG_SYS_DEVICE_NULLDEV	1
+
+#define CONFIG_SYS_MEMTEST_START	0xa0400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0xa1000000	/* default load address */
+
+#define CONFIG_SYS_CPUSPEED		0x141		/* set core clock to 400/200/100 MHz */
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 banks (partition) of DRAM */
+#define PHYS_SDRAM_1		0xa0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x04000000 /* 64 MB */
+#define PHYS_SDRAM_2		0xa4000000 /* SDRAM Bank #2 */
+#define PHYS_SDRAM_2_SIZE	0x00000000 /* 0 MB */
+#define PHYS_SDRAM_3		0xa8000000 /* SDRAM Bank #3 */
+#define PHYS_SDRAM_3_SIZE	0x00000000 /* 0 MB */
+#define PHYS_SDRAM_4		0xac000000 /* SDRAM Bank #4 */
+#define PHYS_SDRAM_4_SIZE	0x00000000 /* 0 MB */
+
+#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
+#define PHYS_FLASH_2		0x04000000 /* Flash Bank #2 */
+#define PHYS_FLASH_SIZE		0x02000000 /* 32 MB */
+#define PHYS_FLASH_BANK_SIZE	0x02000000 /* 32 MB Banks */
+#define PHYS_FLASH_SECT_SIZE	0x00040000 /* 256 KB sectors (x2) */
+
+#define CONFIG_SYS_DRAM_BASE		0xa0000000
+#define CONFIG_SYS_DRAM_SIZE		0x04000000
+
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define	CONFIG_SYS_INIT_SP_ADDR		0xfffff800
+
+/*
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	1    /* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	128  /* max number of sectors on one chip    */
+
+/* timeout values are in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(25*CONFIG_SYS_HZ) /* Timeout for Flash Write */
+
+/* FIXME */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_ADDR		(PHYS_FLASH_1 + 0x40000)/* Addr of Environment Sector	*/
+#define CONFIG_ENV_SIZE		0x40000			/* Total Size of Environment Sector	*/
+
+/*
+ * SMSC91C111 Network Card
+ */
+#define CONFIG_SMC91111		1
+#define CONFIG_SMC91111_BASE		0x10000300  /* chip select 3         */
+#define CONFIG_SMC_USE_32_BIT		1          /* 32 bit bus  */
+#undef  CONFIG_SMC_91111_EXT_PHY		   /* we use internal phy   */
+#undef  CONFIG_SHOW_ACTIVITY
+#define CONFIG_NET_RETRY_COUNT		10	   /* # of retries          */
+
+/*
+ * GPIO settings
+ */
+
+/*
+ * GP05 == nUSBReset  is 1
+ * GP10 == CFReset   is 1
+ * GP13 == nCFDataEnable is 1
+ * GP14 == nCFAddrEnable is 1
+ * GP15 == nCS1      is 1
+ * GP21 == ComBrdReset is 1
+ * GP24 == SFRM      is 1
+ * GP25 == TXD       is 1
+ * GP31 == SYNC      is 1
+ * GP33 == nCS5      is 1
+ * GP39 == FFTXD     is 1
+ * GP41 == RTS       is 1
+ * GP43 == BTTXD     is 1
+ * GP45 == BTRTS     is 1
+ * GP47 == TXD       is 1
+ * GP48 == nPOE      is 1
+ * GP49 == nPWE      is 1
+ * GP50 == nPIOR     is 1
+ * GP51 == nPIOW     is 1
+ * GP52 == nPCE[1]   is 1
+ * GP53 == nPCE[2]   is 1
+ * GP54 == nPSKTSEL  is 1
+ * GP55 == nPREG     is 1
+ * GP78 == nCS2      is 1
+ * GP79 == nCS3      is 1
+ * GP80 == nCS4      is 1
+ * GP82 == NSSPSFRM  is 1
+ * GP83 == NSSPTXD   is 1
+ */
+#define CONFIG_SYS_GPSR0_VAL		0x8320E420
+#define CONFIG_SYS_GPSR1_VAL		0x00FFAA82
+#define CONFIG_SYS_GPSR2_VAL		0x000DC000
+
+/*
+ * GP03 == LANReset  is 0
+ * GP06 == USBWakeUp  is 0
+ * GP11 == USBControl is 0
+ * GP12 == Buzzer     is 0
+ * GP16 == PWM0       is 0
+ * GP17 == PWM1       is 0
+ * GP23 == SCLK      is 0
+ * GP30 == SDATA_OUT is 0
+ * GP81 == NSSPCLK   is 0
+ */
+#define CONFIG_SYS_GPCR0_VAL		0x40C31848
+#define CONFIG_SYS_GPCR1_VAL		0x00000000
+#define CONFIG_SYS_GPCR2_VAL		0x00020000
+
+/*
+ * GP00 == CPUWakeUpUSB is input
+ * GP01 == GP reset is input
+ * GP02 == LANInterrupt is input
+ * GP03 == LANReset     is output
+ * GP04 == USBInterrupt is input
+ * GP05 == nUSBReset    is output
+ * GP06 == USBWakeUp    is output
+ * GP07 == CFReady/nBusy is input
+ * GP08 == nCFCardDetect1 is input
+ * GP09 == nCFCardDetect2 is input
+ * GP10 == nCFReset   is output
+ * GP11 == USBControl is output
+ * GP12 == Buzzer     is output
+ * GP13 == CFDataEnable is output
+ * GP14 == CFAddressEnable is output
+ * GP15 == nCS1      is output
+ * GP16 == PWM0      is output
+ * GP17 == PWM1      is output
+ * GP18 == RDY       is input
+ * GP19 == ReaderReady is input
+ * GP20 == ReaderReset is input
+ * GP21 == ComBrdReset is output
+ * GP23 == SCLK      is output
+ * GP24 == SFRM      is output
+ * GP25 == TXD       is output
+ * GP26 == RXD       is input
+ * GP27 == EXTCLK    is input
+ * GP28 == BITCLK    is output
+ * GP29 == SDATA_IN0 is input
+ * GP30 == SDATA_OUT is output
+ * GP31 == SYNC      is output
+ * GP32 == SYSSCLK   is output
+ * GP33 == nCS5      is output
+ * GP34 == FFRXD     is input
+ * GP35 == CTS       is input
+ * GP36 == DCD       is input
+ * GP37 == DSR       is input
+ * GP38 == RI        is input
+ * GP39 == FFTXD     is output
+ * GP40 == DTR       is output
+ * GP41 == RTS       is output
+ * GP42 == BTRXD     is input
+ * GP43 == BTTXD     is output
+ * GP44 == BTCTS     is input
+ * GP45 == BTRTS     is output
+ * GP46 == RXD       is input
+ * GP47 == TXD       is output
+ * GP48 == nPOE      is output
+ * GP49 == nPWE      is output
+ * GP50 == nPIOR     is output
+ * GP51 == nPIOW     is output
+ * GP52 == nPCE[1]   is output
+ * GP53 == nPCE[2]   is output
+ * GP54 == nPSKTSEL  is output
+ * GP55 == nPREG     is output
+ * GP56 == nPWAIT    is input
+ * GP57 == nPIOS16   is input
+ * GP58 == LDD[0]    is output
+ * GP59 == LDD[1]    is output
+ * GP60 == LDD[2]    is output
+ * GP61 == LDD[3]    is output
+ * GP62 == LDD[4]    is output
+ * GP63 == LDD[5]    is output
+ * GP64 == LDD[6]    is output
+ * GP65 == LDD[7]    is output
+ * GP66 == LDD[8]    is output
+ * GP67 == LDD[9]    is output
+ * GP68 == LDD[10]   is output
+ * GP69 == LDD[11]   is output
+ * GP70 == LDD[12]   is output
+ * GP71 == LDD[13]   is output
+ * GP72 == LDD[14]   is output
+ * GP73 == LDD[15]   is output
+ * GP74 == LCD_FCLK  is output
+ * GP75 == LCD_LCLK  is output
+ * GP76 == LCD_PCLK  is output
+ * GP77 == LCD_ACBIAS is output
+ * GP78 == nCS2      is output
+ * GP79 == nCS3      is output
+ * GP80 == nCS4      is output
+ * GP81 == NSSPCLK   is output
+ * GP82 == NSSPSFRM  is output
+ * GP83 == NSSPTXD   is output
+ * GP84 == NSSPRXD   is input
+ */
+#define CONFIG_SYS_GPDR0_VAL		0xD3E3FC68
+#define CONFIG_SYS_GPDR1_VAL		0xFCFFAB83
+#define CONFIG_SYS_GPDR2_VAL		0x000FFFFF
+
+/*
+ * GP01 == GP reset is AF01
+ * GP15 == nCS1     is AF10
+ * GP16 == PWM0     is AF10
+ * GP17 == PWM1     is AF10
+ * GP18 == RDY      is AF01
+ * GP23 == SCLK     is AF10
+ * GP24 == SFRM     is AF10
+ * GP25 == TXD      is AF10
+ * GP26 == RXD      is AF01
+ * GP27 == EXTCLK   is AF01
+ * GP28 == BITCLK   is AF01
+ * GP29 == SDATA_IN0 is AF10
+ * GP30 == SDATA_OUT is AF01
+ * GP31 == SYNC     is AF01
+ * GP32 == SYSCLK   is AF01
+ * GP33 == nCS5  is AF10
+ * GP34 == FFRXD is AF01
+ * GP35 == CTS   is AF01
+ * GP36 == DCD   is AF01
+ * GP37 == DSR   is AF01
+ * GP38 == RI    is AF01
+ * GP39 == FFTXD is AF10
+ * GP40 == DTR   is AF10
+ * GP41 == RTS   is AF10
+ * GP42 == BTRXD is AF01
+ * GP43 == BTTXD is AF10
+ * GP44 == BTCTS is AF01
+ * GP45 == BTRTS is AF10
+ * GP46 == RXD   is AF10
+ * GP47 == TXD   is AF01
+ * GP48 == nPOE  is AF10
+ * GP49 == nPWE  is AF10
+ * GP50 == nPIOR is AF10
+ * GP51 == nPIOW is AF10
+ * GP52 == nPCE[1] is AF10
+ * GP53 == nPCE[2] is AF10
+ * GP54 == nPSKTSEL is AF10
+ * GP55 == nPREG   is AF10
+ * GP56 == nPWAIT  is AF01
+ * GP57 == nPIOS16 is AF01
+ * GP58 == LDD[0]  is AF10
+ * GP59 == LDD[1]  is AF10
+ * GP60 == LDD[2]  is AF10
+ * GP61 == LDD[3]  is AF10
+ * GP62 == LDD[4]  is AF10
+ * GP63 == LDD[5]  is AF10
+ * GP64 == LDD[6]  is AF10
+ * GP65 == LDD[7]  is AF10
+ * GP66 == LDD[8]  is AF10
+ * GP67 == LDD[9]  is AF10
+ * GP68 == LDD[10] is AF10
+ * GP69 == LDD[11] is AF10
+ * GP70 == LDD[12] is AF10
+ * GP71 == LDD[13] is AF10
+ * GP72 == LDD[14] is AF10
+ * GP73 == LDD[15] is AF10
+ * GP74 == LCD_FCLK is AF10
+ * GP75 == LCD_LCLK is AF10
+ * GP76 == LCD_PCLK is AF10
+ * GP77 == LCD_ACBIAS is AF10
+ * GP78 == nCS2     is AF10
+ * GP79 == nCS3     is AF10
+ * GP80 == nCS4     is AF10
+ * GP81 == NSSPCLK  is AF01
+ * GP82 == NSSPSFRM is AF01
+ * GP83 == NSSPTXD  is AF01
+ * GP84 == NSSPRXD  is AF10
+ */
+#define CONFIG_SYS_GAFR0_L_VAL		0x80000004
+#define CONFIG_SYS_GAFR0_U_VAL		0x595A801A
+#define CONFIG_SYS_GAFR1_L_VAL		0x699A9559
+#define CONFIG_SYS_GAFR1_U_VAL		0xAAA5AAAA
+#define CONFIG_SYS_GAFR2_L_VAL		0xAAAAAAAA
+#define CONFIG_SYS_GAFR2_U_VAL		0x00000256
+
+/*
+ * clock settings
+ */
+/* RDH = 1
+ * PH  = 0
+ * VFS = 0
+ * BFS = 0
+ * SSS = 0
+ */
+#define CONFIG_SYS_PSSR_VAL		0x00000030
+
+#define CONFIG_SYS_CKEN			0x00000080  /*  */
+#define CONFIG_SYS_ICMR			0x00000000  /* No interrupts enabled        */
+#define	CONFIG_SYS_CCCR			CCCR_L27|CCCR_M2|CCCR_N10
+
+
+/*
+ * Memory settings
+ *
+ * This is the configuration for nCS0/1 -> flash banks
+ * configuration for nCS1 :
+ * [31]    0    -
+ * [30:28] 000  -
+ * [27:24] 0000 -
+ * [23:20] 0000 -
+ * [19]    0    -
+ * [18:16] 000  -
+ * configuration for nCS0:
+ * [15]    0    - Slower Device
+ * [14:12] 010  - CS deselect to CS time: 2*(2*MemClk) = 40 ns
+ * [11:08] 0011 - Address to data valid in bursts: (3+1)*MemClk = 40 ns
+ * [07:04] 1111 - " for first access: (23+2)*MemClk = 250 ns (fixme 12+2?)
+ * [03]    0    - 32 Bit bus width
+ * [02:00] 010  - burst OF 4 ROM or FLASH
+*/
+#define CONFIG_SYS_MSC0_VAL		0x000023D2
+
+/* This is the configuration for nCS2/3 -> USB controller, LAN
+ * configuration for nCS3: LAN
+ * [31]    0    - Slower Device
+ * [30:28] 001  - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns
+ * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns
+ * [23:20] 0010 - RDF3: Address for first access: (2+1)*MemClk = 30 ns
+ * [19]    0    - 32 Bit bus width
+ * [18:16] 100  - variable latency I/O
+ * configuration for nCS2: USB
+ * [15]    1    - Faster Device
+ * [14:12] 010  - RRR2: CS deselect to CS time: 2*(2*MemClk) = 40 ns
+ * [11:08] 0010 - RDN2: Address to data valid in bursts: (2+1)*MemClk = 30 ns
+ * [07:04] 0110 - RDF2: Address for first access: (6+1)*MemClk = 70 ns
+ * [03]    1    - 16 Bit bus width
+ * [02:00] 100  - variable latency I/O
+ */
+#define CONFIG_SYS_MSC1_VAL		0x1224A26C
+
+/* This is the configuration for nCS4/5 -> LAN
+ * configuration for nCS5:
+ * [31]    0    -
+ * [30:28] 000  -
+ * [27:24] 0000 -
+ * [23:20] 0000 -
+ * [19]    0    -
+ * [18:16] 000  -
+ * configuration for nCS4: LAN
+ * [15]    1    - Faster Device
+ * [14:12] 010  - RRR2: CS deselect to CS time: 2*(2*MemClk) = 40 ns
+ * [11:08] 0010 - RDN2: Address to data valid in bursts: (2+1)*MemClk = 30 ns
+ * [07:04] 0110 - RDF2: Address for first access: (6+1)*MemClk = 70 ns
+ * [03]    0    - 32 Bit bus width
+ * [02:00] 100  - variable latency I/O
+ */
+#define CONFIG_SYS_MSC2_VAL		0x00001224
+
+/* MDCNFG: SDRAM Configuration Register
+ *
+ * [31:29]   000 - reserved
+ * [28]      0	 - no SA1111 compatiblity mode
+ * [27]      0   - latch return data with return clock
+ * [26]      0   - alternate addressing for pair 2/3
+ * [25:24]   00  - timings
+ * [23]      0   - internal banks in lower partition 2/3 (not used)
+ * [22:21]   00  - row address bits for partition 2/3 (not used)
+ * [20:19]   00  - column address bits for partition 2/3 (not used)
+ * [18]      0   - SDRAM partition 2/3 width is 32 bit
+ * [17]      0   - SDRAM partition 3 disabled
+ * [16]      0   - SDRAM partition 2 disabled
+ * [15:13]   000 - reserved
+ * [12]      0	 - no SA1111 compatiblity mode
+ * [11]      1   - latch return data with return clock
+ * [10]      0   - no alternate addressing for pair 0/1
+ * [09:08]   10  - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk
+ * [7]       1   - 4 internal banks in lower partition pair
+ * [06:05]   10  - 13 row address bits for partition 0/1
+ * [04:03]   01  - 9 column address bits for partition 0/1
+ * [02]      0   - SDRAM partition 0/1 width is 32 bit
+ * [01]      0   - disable SDRAM partition 1
+ * [00]      1   - enable  SDRAM partition 0
+ */
+/* use the configuration above but disable partition 0 */
+#define CONFIG_SYS_MDCNFG_VAL		0x00000AC9
+
+/* MDREFR: SDRAM Refresh Control Register
+ *
+ * [32:26] 0     - reserved
+ * [25]    0     - K2FREE: not free running
+ * [24]    0     - K1FREE: not free running
+ * [23]    0     - K0FREE: not free running
+ * [22]    0     - SLFRSH: self refresh disabled
+ * [21]    0     - reserved
+ * [20]    1     - APD: auto power down
+ * [19]    0     - K2DB2: SDCLK2 is MemClk
+ * [18]    0     - K2RUN: disable SDCLK2
+ * [17]    0     - K1DB2: SDCLK1 is MemClk
+ * [16]    1     - K1RUN: enable SDCLK1
+ * [15]    1     - E1PIN: SDRAM clock enable
+ * [14]    0     - K0DB2: SDCLK0 is MemClk
+ * [13]    0     - K0RUN: disable SDCLK0
+ * [12]    0     - E0PIN: disable SDCKE0
+ * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24
+ */
+#define CONFIG_SYS_MDREFR_VAL		0x00138018 /* mh: was 0x00118018 */
+
+/* MDMRS: Mode Register Set Configuration Register
+ *
+ * [31]      0       - reserved
+ * [30:23]   00000000- MDMRS2: SDRAM2/3 MRS Value. (not used)
+ * [22:20]   011     - MDCL2:  SDRAM2/3 Cas Latency.  (not used)
+ * [19]      0       - MDADD2: SDRAM2/3 burst Type. Fixed to sequential.  (not used)
+ * [18:16]   010     - MDBL2:  SDRAM2/3 burst Length. Fixed to 4.  (not used)
+ * [15]      0       - reserved
+ * [14:07]   00000000- MDMRS0: SDRAM0/1 MRS Value.
+ * [06:04]   011     - MDCL0:  SDRAM0/1 Cas Latency.
+ * [03]      0       - MDADD0: SDRAM0/1 burst Type. Fixed to sequential.
+ * [02:00]   010     - MDBL0:  SDRAM0/1 burst Length. Fixed to 4.
+ */
+#define CONFIG_SYS_MDMRS_VAL		0x00320032
+
+#define	CONFIG_SYS_FLYCNFG_VAL		0x00000000
+#define	CONFIG_SYS_SXCNFG_VAL		0x00000000
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define CONFIG_SYS_MECR_VAL		0x00000000
+#define CONFIG_SYS_MCMEM0_VAL		0x00010504
+#define CONFIG_SYS_MCMEM1_VAL		0x00010504
+#define CONFIG_SYS_MCATT0_VAL		0x00010504
+#define CONFIG_SYS_MCATT1_VAL		0x00010504
+#define CONFIG_SYS_MCIO0_VAL		0x00004715
+#define CONFIG_SYS_MCIO1_VAL		0x00004715
+
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/xfi3.h b/qemu/roms/u-boot/include/configs/xfi3.h
new file mode 100644
index 000000000..8e6b36536
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/xfi3.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __CONFIGS_XFI3_H__
+#define __CONFIGS_XFI3_H__
+
+/* System configurations */
+#define CONFIG_MX23				/* i.MX23 SoC */
+
+/* U-Boot Commands */
+#define CONFIG_SYS_NO_FLASH
+#include <config_cmd_default.h>
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_GPIO
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+#define CONFIG_VIDEO
+
+/* Memory configuration */
+#define CONFIG_NR_DRAM_BANKS		1		/* 1 bank of DRAM */
+#define PHYS_SDRAM_1			0x40000000	/* Base address */
+#define PHYS_SDRAM_1_SIZE		0x08000000	/* Max 128 MB RAM */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+
+/* Environment */
+#define CONFIG_ENV_SIZE			(16 * 1024)
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_OVERWRITE
+
+/* Booting Linux */
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_BOOTARGS		"console=ttyAMA0,115200n8 "
+#define CONFIG_LOADADDR		0x42000000
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+
+/* LCD */
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO_FONT_4X6
+#define CONFIG_VIDEO_MXS_MODE_SYSTEM
+#define CONFIG_SYS_BLACK_IN_WRITE
+#define LCD_BPP	LCD_COLOR16
+#endif
+
+/* USB */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_EHCI_MXS_PORT0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+
+#define CONFIG_CI_UDC		/* ChipIdea CI13xxx UDC */
+#define CONFIG_USB_GADGET_DUALSPEED
+
+#define CONFIG_USB_ETHER
+#define CONFIG_USB_ETH_CDC
+#define CONFIG_NETCONSOLE
+#endif
+
+/* The rest of the configuration is shared */
+#include <configs/mxs.h>
+
+#endif	/* __CONFIGS_XFI3_H__ */
diff --git a/qemu/roms/u-boot/include/configs/xilinx-ppc.h b/qemu/roms/u-boot/include/configs/xilinx-ppc.h
new file mode 100644
index 000000000..0ccd73a86
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/xilinx-ppc.h
@@ -0,0 +1,126 @@
+/*
+ * (C) Copyright 2008
+ *  Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ *  This work has been supported by: QTechnology  http://qtec.com/
+ *
+ *  (C) Copyright 2008
+ *  Georg Schardt <schardt@team-ctech.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+*/
+
+#ifndef __CONFIG_XLX_H
+#define __CONFIG_XLX_H
+/*
+#define DEBUG
+#define ET_DEBUG
+*/
+
+/*Mem Map*/
+#define CONFIG_SYS_SDRAM_BASE		0x0
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(192 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)
+
+/*Cmd*/
+#include <config_cmd_default.h>
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_REGINFO
+#undef CONFIG_CMD_JFFS2
+#undef CONFIG_CMD_MTDPARTS
+#undef CONFIG_CMD_SPI
+#undef CONFIG_CMD_I2C
+#undef CONFIG_CMD_DTT
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_PING
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_NFS
+
+/*Misc*/
+#define CONFIG_BOOTDELAY		5/* autoboot after 5 seconds     */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory         */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE		1024/* Console I/O Buffer Size      */
+#else
+#define CONFIG_SYS_CBSIZE		256/* Console I/O Buffer Size      */
+#endif
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE +\
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16
+					/* max number of command args   */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+					/* Boot Argument Buffer Size */
+#define CONFIG_SYS_MEMTEST_START	0x00400000
+					/* memtest works on           */
+#define CONFIG_SYS_MEMTEST_END		0x00C00000
+					/* 4 ... 12 MB in DRAM        */
+#define CONFIG_SYS_LOAD_ADDR		0x00400000
+					/* default load address       */
+#define CONFIG_SYS_EXTBDINFO		1
+					/* Extended board_into (bd_t) */
+					/* decrementer freq: 1 ms ticks */
+#define CONFIG_CMDLINE_EDITING		/* add command line history     */
+#define CONFIG_AUTO_COMPLETE		/* add autocompletion support   */
+#define CONFIG_LOOPW			/* enable loopw command         */
+#define CONFIG_MX_CYCLIC		/* enable mdc/mwc commands      */
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE		/* include version env variable */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	/* don't print console @ startup */
+#define CONFIG_SYS_HUSH_PARSER		/* Use the HUSH parser          */
+#define CONFIG_LOADS_ECHO		/* echo on for serial download  */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change        */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)
+				/* Initial Memory map for Linux */
+
+/*Stack*/
+#define CONFIG_SYS_INIT_RAM_ADDR	0x800000/* Initial RAM address    */
+#define CONFIG_SYS_INIT_RAM_SIZE		0x2000	/* Size of used area in RAM  */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE \
+				- GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+/*Speed*/
+#define CONFIG_SYS_CLK_FREQ	XPAR_CORE_CLOCK_FREQ_HZ
+
+/*Flash*/
+#ifdef XPAR_FLASH_MEM0_BASEADDR
+#define	CONFIG_SYS_FLASH_BASE		XPAR_FLASH_MEM0_BASEADDR
+#define	CONFIG_SYS_FLASH_CFI		1
+#define	CONFIG_FLASH_CFI_DRIVER	1
+#define	CONFIG_SYS_FLASH_EMPTY_INFO	1
+#define	CONFIG_SYS_MAX_FLASH_BANKS	1
+#define	CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_SYS_NO_FLASH
+#endif
+
+/* serial communication */
+#ifdef XPAR_UARTLITE_0_BASEADDR
+#define CONFIG_XILINX_UARTLITE
+#define XILINX_UARTLITE_BASEADDR	XPAR_UARTLITE_0_BASEADDR
+#define CONFIG_BAUDRATE			XPAR_UARTLITE_0_BAUDRATE
+#define CONFIG_SYS_BAUDRATE_TABLE	{ CONFIG_BAUDRATE }
+#else
+#ifdef XPAR_UARTNS550_0_BASEADDR
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	4
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550_COM1		XPAR_UARTNS550_0_BASEADDR
+#define CONFIG_SYS_NS16550_CLK		XPAR_UARTNS550_0_CLOCK_FREQ_HZ
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 115200 }
+#endif
+#endif
+
+#endif						/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/xilinx-ppc405-generic.h b/qemu/roms/u-boot/include/configs/xilinx-ppc405-generic.h
new file mode 100644
index 000000000..75b119f85
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/xilinx-ppc405-generic.h
@@ -0,0 +1,42 @@
+/*
+ *
+ * (C) Copyright 2008
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * This work has been supported by: QTechnology http://qtec.com/
+ *
+ * (C) Copyright 2008
+ * Georg Schardt <schardt@team-ctech.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __CONFIG_GEN_H
+#define __CONFIG_GEN_H
+
+#include "../board/xilinx/ppc405-generic/xparameters.h"
+
+/* sdram */
+#define CONFIG_SYS_SDRAM_SIZE_MB	256
+
+/* environment */
+#define CONFIG_ENV_IS_IN_FLASH		1
+#define CONFIG_ENV_SIZE			0x10000
+#define CONFIG_ENV_SECT_SIZE		0x10000
+#define CONFIG_SYS_ENV_OFFSET		0x3F0000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE+CONFIG_SYS_ENV_OFFSET)
+#define CONFIG_ENV_OVERWRITE		1
+
+/*Misc*/
+#define CONFIG_SYS_PROMPT	"xlx-ppc405:/# " /* Monitor Command Prompt */
+#define CONFIG_PREBOOT		"echo U-Boot is up and runnining;"
+
+/*Flash*/
+#define CONFIG_SYS_FLASH_BASE			XPAR_FLASH_MEM0_BASEADDR
+#define CONFIG_SYS_FLASH_SIZE		(32*1024*1024)
+#define CONFIG_SYS_MAX_FLASH_SECT	71
+#define CONFIG_SYS_FLASH_CFI		1
+#define CONFIG_FLASH_CFI_DRIVER		1
+#define MTDIDS_DEFAULT			"nor0=ppc405-flash"
+#define MTDPARTS_DEFAULT		"mtdpartsa=ppc405-flash:-(user)"
+
+#include <configs/xilinx-ppc405.h>
+#endif			/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/xilinx-ppc405.h b/qemu/roms/u-boot/include/configs/xilinx-ppc405.h
new file mode 100644
index 000000000..a0151fe8f
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/xilinx-ppc405.h
@@ -0,0 +1,22 @@
+/*
+ *
+ * (C) Copyright 2008
+ * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ * This work has been supported by: QTechnology http://qtec.com/
+ *
+ * (C) Copyright 2008
+ * Georg Schardt <schardt@team-ctech.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* cpu parameter */
+#define CONFIG_405		1
+#define CONFIG_XILINX_405	1
+
+#include <configs/xilinx-ppc.h>
+
+#endif
diff --git a/qemu/roms/u-boot/include/configs/xilinx-ppc440-generic.h b/qemu/roms/u-boot/include/configs/xilinx-ppc440-generic.h
new file mode 100644
index 000000000..8e684151e
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/xilinx-ppc440-generic.h
@@ -0,0 +1,39 @@
+/*
+ * (C) Copyright 2008
+ *  Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ *  This work has been supported by: QTechnology  http://qtec.com/
+ * SPDX-License-Identifier:	GPL-2.0+
+*/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*CPU*/
+#define CONFIG_440			1
+#define CONFIG_XILINX_PPC440_GENERIC	1
+#include "../board/xilinx/ppc440-generic/xparameters.h"
+
+/*Mem Map*/
+#define CONFIG_SYS_SDRAM_SIZE_MB	256
+
+/*Env*/
+#define	CONFIG_ENV_IS_IN_FLASH	1
+#define	CONFIG_ENV_SIZE		0x20000
+#define	CONFIG_ENV_SECT_SIZE	0x20000
+#define CONFIG_ENV_OFFSET		0x340000
+#define CONFIG_ENV_ADDR		(XPAR_FLASH_MEM0_BASEADDR+CONFIG_ENV_OFFSET)
+
+/*Misc*/
+#define CONFIG_SYS_PROMPT		"board:/# "	/* Monitor Command Prompt    */
+#define CONFIG_PREBOOT		"echo U-Boot is up and runnining;"
+
+/*Flash*/
+#define	CONFIG_SYS_FLASH_SIZE		(32*1024*1024)
+#define	CONFIG_SYS_MAX_FLASH_SECT	259
+#define MTDIDS_DEFAULT		"nor0=ml507-flash"
+#define MTDPARTS_DEFAULT	"mtdparts=ml507-flash:-(user)"
+
+/*Generic Configs*/
+#include <configs/xilinx-ppc440.h>
+
+#endif						/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/xilinx-ppc440.h b/qemu/roms/u-boot/include/configs/xilinx-ppc440.h
new file mode 100644
index 000000000..f45700878
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/xilinx-ppc440.h
@@ -0,0 +1,17 @@
+/*
+ * (C) Copyright 2008
+ *  Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
+ *  This work has been supported by: QTechnology  http://qtec.com/
+ * SPDX-License-Identifier:	GPL-2.0+
+*/
+
+#ifndef __CONFIG_GEN_H
+#define __CONFIG_GEN_H
+
+/*CPU*/
+#define CONFIG_440		1
+#define CONFIG_XILINX_440	1
+
+#include <configs/xilinx-ppc.h>
+
+#endif						/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/xpedite1000.h b/qemu/roms/u-boot/include/configs/xpedite1000.h
new file mode 100644
index 000000000..ca322b2e8
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/xpedite1000.h
@@ -0,0 +1,337 @@
+/*
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * config for XPedite1000 from XES Inc.
+ * Ported from EBONY config by Travis B. Sawyer <tsawyer@sandburst.com>
+ * (C) Copyright 2003 Sandburst Corporation
+ * board/config_EBONY.h - configuration for AMCC 440GP Ref (Ebony)
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_XPEDITE1000	1
+#define CONFIG_SYS_BOARD_NAME	"XPedite1000"
+#define CONFIG_SYS_FORM_PMC	1
+#define CONFIG_440		1
+#define CONFIG_440GX		1		/* 440 GX */
+#define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_pre_init	*/
+#define CONFIG_SYS_CLK_FREQ	33333333	/* external freq to pll */
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFF80000
+
+/*
+ * DDR config
+ */
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for setup */
+#define SPD_EEPROM_ADDRESS	{0x54}	/* SPD i2c spd addresses */
+#define CONFIG_VERY_BIG_RAM	1
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xff000000	/* start of FLASH */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped pci memory */
+#define CONFIG_SYS_ISRAM_BASE		0xc0000000	/* internal SRAM */
+#define CONFIG_SYS_PCI_BASE		0xd0000000	/* internal PCI regs */
+#define CONFIG_SYS_NVRAM_BASE_ADDR	(CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
+#define CONFIG_SYS_GPIO_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)
+
+/*
+ * Diagnostics
+ */
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_SYS_MEMTEST_START	0x0400000
+#define CONFIG_SYS_MEMTEST_END		0x0C00000
+
+/* POST support */
+#define CONFIG_POST		(CONFIG_SYS_POST_RTC	| \
+				 CONFIG_SYS_POST_I2C)
+
+/*
+ * LED support
+ */
+#define USR_LED0	0x00000080
+#define USR_LED1	0x00000100
+#define USR_LED2	0x00000200
+#define USR_LED3	0x00000400
+
+#ifndef __ASSEMBLY__
+extern unsigned long in32(unsigned int);
+extern void out32(unsigned int, unsigned long);
+
+#define LED0_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED0))
+#define LED1_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED1))
+#define LED2_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED2))
+#define LED3_ON() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) & ~USR_LED3))
+
+#define LED0_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED0))
+#define LED1_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED1))
+#define LED2_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED2))
+#define LED3_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED3))
+#endif
+
+/*
+ * Use internal SRAM for initial stack
+ */
+#define CONFIG_SYS_TEMP_STACK_OCM	1
+#define CONFIG_SYS_OCM_DATA_ADDR	CONFIG_SYS_ISRAM_BASE
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_ISRAM_BASE	/* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE		0x2000	/* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
+
+#define CONFIG_SYS_MONITOR_LEN	(512 * 1024)	/* Reserve 512 KB for Mon */
+#define CONFIG_SYS_MALLOC_LEN	(1024 * 1024)	/* Reserved for malloc */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400}
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_LOADS_ECHO		1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * Use the HUSH parser
+ */
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * NOR flash configuration
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS	3
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE, 0xf0000000, 0xf4000000 }
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* sectors per device */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_QUIET_TEST		/* MirrorBit flashes are optional */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7f
+
+/* I2C EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
+
+/* I2C RTC: STMicro M41T00 */
+#define CONFIG_RTC_M41T11		1
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR	2000
+
+/*
+ * PCI
+ */
+/* General PCI */
+#define CONFIG_PCI				/* include pci support */
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_PNP				/* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW			/* show pci devices on startup */
+#define CONFIG_SYS_PCI_TARGBASE	0x80000000	/* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
+
+/* Board-specific PCI */
+#define CONFIG_SYS_PCI_TARGET_INIT		/* let board init pci target */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014	/* IBM */
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
+#define CONFIG_SYS_PCI_FORCE_PCI_CONV		/* Force PCI Conventional Mode */
+
+/*
+ * Networking options
+ */
+#define CONFIG_PPC4xx_EMAC
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+#define CONFIG_MII		1	/* MII PHY management */
+#define CONFIG_PHY_RESET	1	/* reset phy upon startup */
+#define CONFIG_SYS_RX_ETH_BUFFER 32	/* Number of ethernet rx buffers & descriptors */
+#define CONFIG_ETHPRIME		"ppc_4xx_eth2"
+#define CONFIG_PHY_ADDR		4	/* PHY address phy0 not populated */
+#define CONFIG_PHY2_ADDR	4	/* PHY address phy2 */
+#define CONFIG_HAS_ETH2		1	/* add support for "eth2addr" */
+#define CONFIG_PHY3_ADDR	8	/* PHY address phy3 */
+#define CONFIG_HAS_ETH3		1	/* add support for "eth3addr" */
+
+/* BOOTP options */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command configuration
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_SNTP
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_CMDLINE_EDITING	1		/* Command-line editing */
+#define CONFIG_BOOTDELAY	3		/* -1 disables auto-boot */
+#define CONFIG_PANIC_HANG			/* do not reset board on panic */
+#define CONFIG_PREBOOT				/* enable preboot variable */
+#define CONFIG_FIT		1
+#define CONFIG_FIT_VERBOSE	1
+#define CONFIG_INTEGRITY			/* support booting INTEGRITY OS */
+#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128k (one sector) for env */
+#define CONFIG_ENV_SIZE		0x8000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - (256 * 1024))
+
+/*
+ * Flash memory map:
+ * fff80000 - ffffffff	U-Boot (512 KB)
+ * fff40000 - fff7ffff	U-Boot Environment (256 KB)
+ * fff00000 - fff3ffff	FDT (256KB)
+ * ffc00000 - ffefffff	OS image (3MB)
+ * ff000000 - ffbfffff	OS Use/Filesystem (12MB)
+ */
+
+#define CONFIG_UBOOT_ENV_ADDR	__stringify(CONFIG_SYS_TEXT_BASE)
+#define CONFIG_FDT_ENV_ADDR	__stringify(0xfff00000)
+#define CONFIG_OS_ENV_ADDR	__stringify(0xffc00000)
+
+#define CONFIG_PROG_UBOOT						\
+	"$download_cmd $loadaddr $ubootfile; "				\
+	"if test $? -eq 0; then "					\
+		"protect off "CONFIG_UBOOT_ENV_ADDR" +80000; "		\
+		"erase "CONFIG_UBOOT_ENV_ADDR" +80000; "		\
+		"cp.w $loadaddr "CONFIG_UBOOT_ENV_ADDR" 40000; "	\
+		"protect on "CONFIG_UBOOT_ENV_ADDR" +80000; "		\
+		"cmp.b $loadaddr "CONFIG_UBOOT_ENV_ADDR" 80000; "	\
+		"if test $? -ne 0; then "				\
+			"echo PROGRAM FAILED; "				\
+		"else; "						\
+			"echo PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_BOOT_OS_NET						\
+	"$download_cmd $osaddr $osfile; "				\
+	"if test $? -eq 0; then "					\
+		"if test -n $fdtaddr; then "				\
+			"$download_cmd $fdtaddr $fdtfile; "		\
+			"if test $? -eq 0; then "			\
+				"bootm $osaddr - $fdtaddr; "		\
+			"else; "					\
+				"echo FDT DOWNLOAD FAILED; "		\
+			"fi; "						\
+		"else; "						\
+			"bootm $osaddr; "				\
+		"fi; "							\
+	"else; "							\
+		"echo OS DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_OS							\
+	"$download_cmd $osaddr $osfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_OS_ENV_ADDR" +$filesize; "		\
+		"cp.b $osaddr "CONFIG_OS_ENV_ADDR" $filesize; "		\
+		"cmp.b $osaddr "CONFIG_OS_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo OS PROGRAM FAILED; "			\
+		"else; "						\
+			"echo OS PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo OS DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_FDT							\
+	"$download_cmd $fdtaddr $fdtfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_FDT_ENV_ADDR" +$filesize;"		\
+		"cp.b $fdtaddr "CONFIG_FDT_ENV_ADDR" $filesize; "	\
+		"cmp.b $fdtaddr "CONFIG_FDT_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo FDT PROGRAM FAILED; "			\
+		"else; "						\
+			"echo FDT PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo FDT DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"autoload=yes\0"						\
+	"download_cmd=tftp\0"						\
+	"console_args=console=ttyS0,115200\0"				\
+	"root_args=root=/dev/nfs rw\0"					\
+	"misc_args=ip=on\0"						\
+	"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
+	"bootfile=/home/user/file\0"					\
+	"osfile=/home/user/board.uImage\0"				\
+	"fdtfile=/home/user/board.dtb\0"				\
+	"ubootfile=/home/user/u-boot.bin\0"				\
+	"fdtaddr=c00000\0"						\
+	"osaddr=0x1000000\0"						\
+	"loadaddr=0x1000000\0"						\
+	"prog_uboot="CONFIG_PROG_UBOOT"\0"				\
+	"prog_os="CONFIG_PROG_OS"\0"					\
+	"prog_fdt="CONFIG_PROG_FDT"\0"					\
+	"bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0"		\
+	"bootcmd_flash=run set_bootargs; "				\
+		"bootm "CONFIG_OS_ENV_ADDR" - "CONFIG_FDT_ENV_ADDR"\0"	\
+	"bootcmd=run bootcmd_flash\0"
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/xpedite517x.h b/qemu/roms/u-boot/include/configs/xpedite517x.h
new file mode 100644
index 000000000..cbf4b8e0f
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/xpedite517x.h
@@ -0,0 +1,745 @@
+/*
+ * Copyright 2009 Extreme Engineering Solutions, Inc.
+ * Copyright 2007-2008 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * xpedite517x board configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_MPC8641		1	/* MPC8641 specific */
+#define CONFIG_XPEDITE5140	1	/* MPC8641HPCN board specific */
+#define CONFIG_SYS_BOARD_NAME	"XPedite5170"
+#define CONFIG_SYS_FORM_3U_VPX	1
+#define CONFIG_LINUX_RESET_VEC	0x100	/* Reset vector used by Linux */
+#define CONFIG_BOARD_EARLY_INIT_R	/* Call board_pre_init */
+#define CONFIG_BAT_RW		1	/* Use common BAT rw code */
+#define CONFIG_HIGH_BATS	1	/* High BATs supported and enabled */
+#define CONFIG_ALTIVEC		1
+
+#define	CONFIG_SYS_TEXT_BASE	0xfff00000
+
+#define CONFIG_PCI		1	/* Enable PCI/PCIE */
+#define CONFIG_PCI_PNP		1	/* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup */
+#define CONFIG_PCIE1		1	/* PCIE controler 1 */
+#define CONFIG_PCIE2		1	/* PCIE controler 2 */
+#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
+#define CONFIG_FSL_LAW		1	/* Use common FSL init code */
+
+/*
+ * DDR config
+ */
+#define CONFIG_SYS_FSL_DDR2
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
+#define CONFIG_DDR_SPD
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#define SPD_EEPROM_ADDRESS1		0x54	/* Both channels use the */
+#define SPD_EEPROM_ADDRESS2		0x54	/* same SPD data         */
+#define SPD_EEPROM_OFFSET		0x200	/* OFFSET of SPD in EEPROM */
+#define CONFIG_NUM_DDR_CONTROLLERS	2
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	1
+#define CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_MAX_DDR_BAT_SIZE	0x80000000	/* BAT mapping size */
+
+/*
+ * virtual address to be used for temporary mappings.  There
+ * should be 128k free at this VA.
+ */
+#define CONFIG_SYS_SCRATCH_VA	0xe0000000
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_board_sys_clk(unsigned long dummy);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0) /* sysclk for MPC86xx */
+
+/*
+ * L2CR setup
+ */
+#define CONFIG_SYS_L2
+#define L2_INIT		0
+#define L2_ENABLE	(L2CR_L2E)
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
+#define CONFIG_SYS_CCSRBAR		0xef000000	/* relocated CCSRBAR */
+#define CONFIG_SYS_CCSRBAR_PHYS		CONFIG_SYS_CCSRBAR
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0x0
+#define CONFIG_SYS_IMMR			CONFIG_SYS_CCSRBAR
+
+/*
+ * Diagnostics
+ */
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_SYS_MEMTEST_START	0x10000000
+#define CONFIG_SYS_MEMTEST_END		0x20000000
+#define CONFIG_POST			(CONFIG_SYS_POST_MEMORY |\
+					 CONFIG_SYS_POST_I2C)
+#define I2C_ADDR_LIST			{CONFIG_SYS_I2C_DS1621_ADDR,	\
+					 CONFIG_SYS_I2C_DS4510_ADDR,	\
+					 CONFIG_SYS_I2C_EEPROM_ADDR,	\
+					 CONFIG_SYS_I2C_LM90_ADDR,	\
+					 CONFIG_SYS_I2C_PCA9553_ADDR,	\
+					 CONFIG_SYS_I2C_PCA953X_ADDR0,	\
+					 CONFIG_SYS_I2C_PCA953X_ADDR1,	\
+					 CONFIG_SYS_I2C_PCA953X_ADDR2,	\
+					 CONFIG_SYS_I2C_PCA953X_ADDR3,	\
+					 CONFIG_SYS_I2C_PEX8518_ADDR,	\
+					 CONFIG_SYS_I2C_RTC_ADDR}
+/* The XPedite5170 can host an XMC which has an EEPROM at address 0x50 */
+#define I2C_ADDR_IGNORE_LIST		{0x50}
+
+/*
+ * Memory map
+ * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
+ * 0x8000_0000	0xbfff_ffff	PCIe1 Mem		1G non-cacheable
+ * 0xc000_0000	0xcfff_ffff	PCIe2 Mem		256M non-cacheable
+ * 0xe000_0000	0xe7ff_ffff	SRAM/SSRAM/L1 Cache	128M non-cacheable
+ * 0xe800_0000	0xe87f_ffff	PCIe1 IO		8M non-cacheable
+ * 0xe880_0000	0xe8ff_ffff	PCIe2 IO		8M non-cacheable
+ * 0xef00_0000	0xef0f_ffff	CCSR/IMMR		1M non-cacheable
+ * 0xef80_0000	0xef8f_ffff	NAND Flash		1M non-cacheable
+ * 0xf000_0000	0xf7ff_ffff	NOR Flash 2		128M non-cacheable
+ * 0xf800_0000	0xffff_ffff	NOR Flash 1		128M non-cacheable
+ */
+
+#define CONFIG_SYS_LBC_LCRR		(LCRR_CLKDIV_4 | LCRR_EADC_3)
+
+/*
+ * NAND flash configuration
+ */
+#define CONFIG_SYS_NAND_BASE		0xef800000
+#define CONFIG_SYS_NAND_BASE2		0xef840000	/* Unused at this time */
+#define CONFIG_SYS_NAND_BASE_LIST 	{CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE2}
+#define CONFIG_SYS_MAX_NAND_DEVICE	2
+#define CONFIG_NAND_ACTL
+#define CONFIG_SYS_NAND_ACTL_ALE 	(1 << 14)	/* C_LA14 */
+#define CONFIG_SYS_NAND_ACTL_CLE 	(1 << 15)	/* C_LA15 */
+#define CONFIG_SYS_NAND_ACTL_NCE	0		/* NCE not controlled by ADDR */
+#define CONFIG_SYS_NAND_ACTL_DELAY	25
+#define CONFIG_SYS_NAND_QUIET_TEST
+#define CONFIG_JFFS2_NAND
+
+/*
+ * NOR flash configuration
+ */
+#define CONFIG_SYS_FLASH_BASE		0xf8000000
+#define CONFIG_SYS_FLASH_BASE2		0xf0000000
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
+#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST	{ {0xfff00000, 0xc0000}, \
+						  {0xf7f00000, 0xc0000} }
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE_EARLY	0xfff00000	/* early monitor loc */
+
+/*
+ * Chip select configuration
+ */
+/* NOR Flash 0 on CS0 */
+#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE	|\
+				 BR_PS_16		|\
+				 BR_V)
+#define CONFIG_SYS_OR0_PRELIM	(OR_AM_128MB		|\
+				 OR_GPCM_CSNT		|\
+				 OR_GPCM_XACS		|\
+				 OR_GPCM_ACS_DIV2	|\
+				 OR_GPCM_SCY_8		|\
+				 OR_GPCM_TRLX		|\
+				 OR_GPCM_EHTR		|\
+				 OR_GPCM_EAD)
+
+/* NOR Flash 1 on CS1 */
+#define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_FLASH_BASE2	|\
+				 BR_PS_16		|\
+				 BR_V)
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+
+/* NAND flash on CS2 */
+#define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_NAND_BASE	|\
+				 BR_PS_8		|\
+				 BR_V)
+#define CONFIG_SYS_OR2_PRELIM	(OR_AM_256KB		|\
+				 OR_GPCM_BCTLD		|\
+				 OR_GPCM_CSNT		|\
+				 OR_GPCM_ACS_DIV4	|\
+				 OR_GPCM_SCY_4		|\
+				 OR_GPCM_TRLX		|\
+				 OR_GPCM_EHTR)
+
+/* Optional NAND flash on CS3 */
+#define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_NAND_BASE2	|\
+				 BR_PS_8		|\
+				 BR_V)
+#define CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+
+/*
+ * Use L1 as initial stack
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xe0000000
+#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 KB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_LOADS_ECHO		1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * Use the HUSH parser
+ */
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT		1
+#define CONFIG_OF_BOARD_SETUP		1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	100000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	100000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+
+/* PEX8518 slave I2C interface */
+#define CONFIG_SYS_I2C_PEX8518_ADDR	0x70
+
+/* I2C DS1631 temperature sensor */
+#define CONFIG_SYS_I2C_DS1621_ADDR	0x48
+#define CONFIG_DTT_DS1621
+#define CONFIG_DTT_SENSORS		{ 0 }
+#define CONFIG_SYS_I2C_LM90_ADDR	0x4c
+
+/* I2C EEPROM - AT24C128B */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x54
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6	/* 64 byte pages */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* take up to 10 msec */
+
+/* I2C RTC */
+#define CONFIG_RTC_M41T11		1
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR	2000
+
+/* GPIO/EEPROM/SRAM */
+#define CONFIG_DS4510
+#define CONFIG_SYS_I2C_DS4510_ADDR	0x51
+
+/* GPIO */
+#define CONFIG_PCA953X
+#define CONFIG_SYS_I2C_PCA953X_ADDR0	0x18
+#define CONFIG_SYS_I2C_PCA953X_ADDR1	0x1c
+#define CONFIG_SYS_I2C_PCA953X_ADDR2	0x1e
+#define CONFIG_SYS_I2C_PCA953X_ADDR3	0x1f
+#define CONFIG_SYS_I2C_PCA953X_ADDR	CONFIG_SYS_I2C_PCA953X_ADDR0
+#define CONFIG_SYS_I2C_PCA9553_ADDR	0x62
+
+/*
+ * PU = pulled high, PD = pulled low
+ * I = input, O = output, IO = input/output
+ */
+/* PCA9557 @ 0x18*/
+#define CONFIG_SYS_PCA953X_C0_SER0_EN		0x01 /* PU; UART0 enable (1: enabled) */
+#define CONFIG_SYS_PCA953X_C0_SER0_MODE		0x02 /* PU; UART0 serial mode select */
+#define CONFIG_SYS_PCA953X_C0_SER1_EN		0x04 /* PU; UART1 enable (1: enabled) */
+#define CONFIG_SYS_PCA953X_C0_SER1_MODE		0x08 /* PU; UART1 serial mode select */
+#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS	0x10 /* PU; Boot flash CS select */
+#define CONFIG_SYS_PCA953X_NVM_WP		0x20 /* PU; Set to 0 to enable NVM writing */
+
+/* PCA9557 @ 0x1c*/
+#define CONFIG_SYS_PCA953X_XMC0_ROOT0		0x01 /* PU; Low if XMC is RC */
+#define CONFIG_SYS_PCA953X_PLUG_GPIO0		0x02 /* Samtec connector GPIO */
+#define CONFIG_SYS_PCA953X_XMC0_WAKE		0x04 /* PU; XMC wake */
+#define CONFIG_SYS_PCA953X_XMC0_BIST		0x08 /* PU; XMC built in self test */
+#define CONFIG_SYS_PCA953X_XMC_PRESENT		0x10 /* PU; Low if XMC module installed */
+#define CONFIG_SYS_PCA953X_PMC_PRESENT		0x20 /* PU; Low if PMC module installed */
+#define CONFIG_SYS_PCA953X_PMC0_MONARCH		0x40 /* PMC monarch mode enable */
+#define CONFIG_SYS_PCA953X_PMC0_EREADY		0x80 /* PU; PMC PCI eready */
+
+/* PCA9557 @ 0x1e*/
+#define CONFIG_SYS_PCA953X_P0_GA0		0x01 /* PU; VPX Geographical address */
+#define CONFIG_SYS_PCA953X_P0_GA1		0x02 /* PU; VPX Geographical address */
+#define CONFIG_SYS_PCA953X_P0_GA2		0x04 /* PU; VPX Geographical address */
+#define CONFIG_SYS_PCA953X_P0_GA3		0x08 /* PU; VPX Geographical address */
+#define CONFIG_SYS_PCA953X_P0_GA4		0x10 /* PU; VPX Geographical address */
+#define CONFIG_SYS_PCA953X_P0_GAP		0x20 /* PU; VPX Geographical address parity */
+#define CONFIG_SYS_PCA953X_P1_SYSEN		0x80 /* PU; VPX P1 SYSCON */
+
+/* PCA9557 @ 0x1f */
+#define CONFIG_SYS_PCA953X_VPX_GPIO0		0x01 /* PU; VPX P15 GPIO */
+#define CONFIG_SYS_PCA953X_VPX_GPIO1		0x02 /* PU; VPX P15 GPIO */
+#define CONFIG_SYS_PCA953X_VPX_GPIO2		0x04 /* PU; VPX P15 GPIO */
+#define CONFIG_SYS_PCA953X_VPX_GPIO3		0x08 /* PU; VPX P15 GPIO */
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+/* PCIE1 - PEX8518 */
+#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BUS
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x40000000	/* 1G */
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xe8000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000	/* 8M */
+
+/* PCIE2 - VPX P1 */
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xc0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	CONFIG_SYS_PCIE2_MEM_BUS
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xe8800000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000	/* 8M */
+
+/*
+ * Networking options
+ */
+#define CONFIG_TSEC_ENET		/* tsec ethernet support */
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+#define CONFIG_MII		1	/* MII PHY management */
+#define CONFIG_ETHPRIME		"eTSEC1"
+
+#define CONFIG_TSEC1		1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC1_PHY_ADDR		1
+#define TSEC1_PHYIDX		0
+#define CONFIG_HAS_ETH0
+
+#define CONFIG_TSEC2		1
+#define CONFIG_TSEC2_NAME	"eTSEC2"
+#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_PHY_ADDR		2
+#define TSEC2_PHYIDX		0
+#define CONFIG_HAS_ETH1
+
+/*
+ * BAT mappings
+ */
+#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
+#define CONFIG_SYS_CCSR_DEFAULT_DBATL	(CONFIG_SYS_CCSRBAR_DEFAULT	|\
+					 BATL_PP_RW			|\
+					 BATL_CACHEINHIBIT		|\
+					 BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_CCSR_DEFAULT_DBATU	(CONFIG_SYS_CCSRBAR_DEFAULT	|\
+					 BATU_BL_1M			|\
+					 BATU_VS			|\
+					 BATU_VP)
+#define CONFIG_SYS_CCSR_DEFAULT_IBATL	(CONFIG_SYS_CCSRBAR_DEFAULT	|\
+					 BATL_PP_RW			|\
+					 BATL_CACHEINHIBIT)
+#define CONFIG_SYS_CCSR_DEFAULT_IBATU	CONFIG_SYS_CCSR_DEFAULT_DBATU
+#endif
+
+/*
+ * BAT0		2G	Cacheable, non-guarded
+ * 0x0000_0000	2G	DDR
+ */
+#define CONFIG_SYS_DBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_DBAT0U	(BATU_BL_2G | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0L	(BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	CONFIG_SYS_DBAT0U
+
+/*
+ * BAT1		1G	Cache-inhibited, guarded
+ * 0x8000_0000	1G	PCI-Express 1 Memory
+ */
+#define CONFIG_SYS_DBAT1L	(CONFIG_SYS_PCIE1_MEM_PHYS	|\
+				 BATL_PP_RW			|\
+				 BATL_CACHEINHIBIT		|\
+				 BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT1U	(CONFIG_SYS_PCIE1_MEM_PHYS	|\
+				 BATU_BL_1G			|\
+				 BATU_VS			|\
+				 BATU_VP)
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCIE1_MEM_PHYS	|\
+				 BATL_PP_RW			|\
+				 BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT1U	CONFIG_SYS_DBAT1U
+
+/*
+ * BAT2		512M	Cache-inhibited, guarded
+ * 0xc000_0000	512M	PCI-Express 2 Memory
+ */
+#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_PCIE2_MEM_PHYS	|\
+				 BATL_PP_RW			|\
+				 BATL_CACHEINHIBIT		|\
+				 BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U	(CONFIG_SYS_PCIE2_MEM_PHYS	|\
+				 BATU_BL_512M			|\
+				 BATU_VS			|\
+				 BATU_VP)
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCIE2_MEM_PHYS	|\
+				 BATL_PP_RW			|\
+				 BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U	CONFIG_SYS_DBAT2U
+
+/*
+ * BAT3		1M	Cache-inhibited, guarded
+ * 0xe000_0000	1M	CCSR
+ */
+#define CONFIG_SYS_DBAT3L	(CONFIG_SYS_CCSRBAR		|\
+				 BATL_PP_RW			|\
+				 BATL_CACHEINHIBIT		|\
+				 BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT3U	(CONFIG_SYS_CCSRBAR		|\
+				 BATU_BL_1M			|\
+				 BATU_VS			|\
+				 BATU_VP)
+#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_CCSRBAR		|\
+				 BATL_PP_RW			|\
+				 BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U	CONFIG_SYS_DBAT3U
+
+/*
+ * BAT4		32M	Cache-inhibited, guarded
+ * 0xe200_0000	16M	PCI-Express 1 I/O
+ * 0xe300_0000	16M	PCI-Express 2 I/0
+ */
+#define CONFIG_SYS_DBAT4L	(CONFIG_SYS_PCIE1_IO_PHYS	|\
+				 BATL_PP_RW			|\
+				 BATL_CACHEINHIBIT		|\
+				 BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT4U	(CONFIG_SYS_PCIE1_IO_PHYS	|\
+				 BATU_BL_32M			|\
+				 BATU_VS			|\
+				 BATU_VP)
+#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCIE1_IO_PHYS	|\
+				 BATL_PP_RW			|\
+				 BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT4U	CONFIG_SYS_DBAT4U
+
+/*
+ * BAT5		128K	Cacheable, non-guarded
+ * 0xe400_1000	128K	Init RAM for stack in the CPU DCache (no backing memory)
+ */
+#define CONFIG_SYS_DBAT5L	(CONFIG_SYS_INIT_RAM_ADDR	|\
+				 BATL_PP_RW			|\
+				 BATL_MEMCOHERENCE)
+#define CONFIG_SYS_DBAT5U	(CONFIG_SYS_INIT_RAM_ADDR	|\
+				 BATU_BL_128K			|\
+				 BATU_VS			|\
+				 BATU_VP)
+#define CONFIG_SYS_IBAT5L	CONFIG_SYS_DBAT5L
+#define CONFIG_SYS_IBAT5U	CONFIG_SYS_DBAT5U
+
+/*
+ * BAT6		256M	Cache-inhibited, guarded
+ * 0xf000_0000	256M	FLASH
+ */
+#define CONFIG_SYS_DBAT6L	(CONFIG_SYS_FLASH_BASE2		|\
+				 BATL_PP_RW			|\
+				 BATL_CACHEINHIBIT		|\
+				 BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6U	(CONFIG_SYS_FLASH_BASE		|\
+				 BATU_BL_256M			|\
+				 BATU_VS			|\
+				 BATU_VP)
+#define CONFIG_SYS_IBAT6L	(CONFIG_SYS_FLASH_BASE		|\
+				 BATL_PP_RW			|\
+				 BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U	CONFIG_SYS_DBAT6U
+
+/* Map the last 1M of flash where we're running from reset */
+#define CONFIG_SYS_DBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY	|\
+				 BATL_PP_RW			|\
+				 BATL_CACHEINHIBIT		|\
+				 BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT6U_EARLY	(CONFIG_SYS_TEXT_BASE			|\
+				 BATU_BL_1M			|\
+				 BATU_VS			|\
+				 BATU_VP)
+#define CONFIG_SYS_IBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY	|\
+				 BATL_PP_RW			|\
+				 BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U_EARLY	CONFIG_SYS_DBAT6U_EARLY
+
+/*
+ * BAT7		64M	Cache-inhibited, guarded
+ * 0xe800_0000	64K	NAND FLASH
+ * 0xe804_0000	128K	DUART Registers
+ */
+#define CONFIG_SYS_DBAT7L	(CONFIG_SYS_NAND_BASE		|\
+				 BATL_PP_RW			|\
+				 BATL_CACHEINHIBIT		|\
+				 BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT7U 	(CONFIG_SYS_NAND_BASE		|\
+				 BATU_BL_512K			|\
+				 BATU_VS			|\
+				 BATU_VP)
+#define CONFIG_SYS_IBAT7L	(CONFIG_SYS_NAND_BASE		|\
+				 BATL_PP_RW			|\
+				 BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT7U	CONFIG_SYS_DBAT7U
+
+/*
+ * Command configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DS4510
+#define CONFIG_CMD_DS4510_INFO
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCA953X
+#define CONFIG_CMD_PCA953X_INFO
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PCI_ENUM
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SNTP
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_CMDLINE_EDITING	1		/* Command-line editing */
+#define CONFIG_LOADADDR		0x1000000	/* default location for tftp and bootm */
+#define CONFIG_BOOTDELAY	3		/* -1 disables auto-boot */
+#define CONFIG_PANIC_HANG			/* do not reset board on panic */
+#define CONFIG_PREBOOT				/* enable preboot variable */
+#define CONFIG_FIT		1
+#define CONFIG_FIT_VERBOSE	1
+#define CONFIG_INTEGRITY			/* support booting INTEGRITY OS */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(16 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(16 << 20)	/* Increase max gunzip size */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_SECT_SIZE	0x20000		/* 128k (one sector) for env */
+#define CONFIG_ENV_SIZE		0x8000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+
+/*
+ * Flash memory map:
+ * fffc0000 - ffffffff	Pri FDT (256KB)
+ * fff80000 - fffbffff	Pri U-Boot Environment (256 KB)
+ * fff00000 - fff7ffff	Pri U-Boot (512 KB)
+ * fef00000 - ffefffff	Pri OS image (16MB)
+ * f8000000 - feefffff	Pri OS Use/Filesystem (111MB)
+ *
+ * f7fc0000 - f7ffffff	Sec FDT (256KB)
+ * f7f80000 - f7fbffff	Sec U-Boot Environment (256 KB)
+ * f7f00000 - f7f7ffff	Sec U-Boot (512 KB)
+ * f6f00000 - f7efffff	Sec OS image (16MB)
+ * f0000000 - f6efffff	Sec OS Use/Filesystem (111MB)
+ */
+#define CONFIG_UBOOT1_ENV_ADDR	__stringify(0xfff00000)
+#define CONFIG_UBOOT2_ENV_ADDR	__stringify(0xf7f00000)
+#define CONFIG_FDT1_ENV_ADDR	__stringify(0xfffc0000)
+#define CONFIG_FDT2_ENV_ADDR	__stringify(0xf7fc0000)
+#define CONFIG_OS1_ENV_ADDR	__stringify(0xfef00000)
+#define CONFIG_OS2_ENV_ADDR	__stringify(0xf6f00000)
+
+#define CONFIG_PROG_UBOOT1						\
+	"$download_cmd $loadaddr $ubootfile; "				\
+	"if test $? -eq 0; then "					\
+		"protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
+		"erase "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
+		"cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; "	\
+		"protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
+		"cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; "	\
+		"if test $? -ne 0; then "				\
+			"echo PROGRAM FAILED; "				\
+		"else; "						\
+			"echo PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_UBOOT2						\
+	"$download_cmd $loadaddr $ubootfile; "				\
+	"if test $? -eq 0; then "					\
+		"protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
+		"erase "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
+		"cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; "	\
+		"protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
+		"cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; "	\
+		"if test $? -ne 0; then "				\
+			"echo PROGRAM FAILED; "				\
+		"else; "						\
+			"echo PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_BOOT_OS_NET						\
+	"$download_cmd $osaddr $osfile; "				\
+	"if test $? -eq 0; then "					\
+		"if test -n $fdtaddr; then "				\
+			"$download_cmd $fdtaddr $fdtfile; "		\
+			"if test $? -eq 0; then "			\
+				"bootm $osaddr - $fdtaddr; "		\
+			"else; "					\
+				"echo FDT DOWNLOAD FAILED; "		\
+			"fi; "						\
+		"else; "						\
+			"bootm $osaddr; "				\
+		"fi; "							\
+	"else; "							\
+		"echo OS DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_OS1							\
+	"$download_cmd $osaddr $osfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_OS1_ENV_ADDR" +$filesize; "		\
+		"cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
+		"cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo OS PROGRAM FAILED; "			\
+		"else; "						\
+			"echo OS PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo OS DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_OS2							\
+	"$download_cmd $osaddr $osfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_OS2_ENV_ADDR" +$filesize; "		\
+		"cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
+		"cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo OS PROGRAM FAILED; "			\
+		"else; "						\
+			"echo OS PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo OS DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_FDT1						\
+	"$download_cmd $fdtaddr $fdtfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_FDT1_ENV_ADDR" +$filesize;"		\
+		"cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
+		"cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo FDT PROGRAM FAILED; "			\
+		"else; "						\
+			"echo FDT PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo FDT DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_FDT2						\
+	"$download_cmd $fdtaddr $fdtfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_FDT2_ENV_ADDR" +$filesize;"		\
+		"cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
+		"cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo FDT PROGRAM FAILED; "			\
+		"else; "						\
+			"echo FDT PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo FDT DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"autoload=yes\0"						\
+	"download_cmd=tftp\0"						\
+	"console_args=console=ttyS0,115200\0"				\
+	"root_args=root=/dev/nfs rw\0"					\
+	"misc_args=ip=on\0"						\
+	"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
+	"bootfile=/home/user/file\0"					\
+	"osfile=/home/user/board.uImage\0"				\
+	"fdtfile=/home/user/board.dtb\0"				\
+	"ubootfile=/home/user/u-boot.bin\0"				\
+	"fdtaddr=c00000\0"						\
+	"osaddr=0x1000000\0"						\
+	"loadaddr=0x1000000\0"						\
+	"prog_uboot1="CONFIG_PROG_UBOOT1"\0"				\
+	"prog_uboot2="CONFIG_PROG_UBOOT2"\0"				\
+	"prog_os1="CONFIG_PROG_OS1"\0"					\
+	"prog_os2="CONFIG_PROG_OS2"\0"					\
+	"prog_fdt1="CONFIG_PROG_FDT1"\0"				\
+	"prog_fdt2="CONFIG_PROG_FDT2"\0"				\
+	"bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0"		\
+	"bootcmd_flash1=run set_bootargs; "				\
+		"bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
+	"bootcmd_flash2=run set_bootargs; "				\
+		"bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
+	"bootcmd=run bootcmd_flash1\0"
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/xpedite520x.h b/qemu/roms/u-boot/include/configs/xpedite520x.h
new file mode 100644
index 000000000..baa30395a
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/xpedite520x.h
@@ -0,0 +1,528 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2004-2008 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * xpedite520x board configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_BOOKE		1	/* BOOKE */
+#define CONFIG_E500		1	/* BOOKE e500 family */
+#define CONFIG_MPC8548		1
+#define CONFIG_XPEDITE5200	1
+#define CONFIG_SYS_BOARD_NAME	"XPedite5200"
+#define CONFIG_SYS_FORM_PMC_XMC	1
+#define CONFIG_BOARD_EARLY_INIT_R	/* Call board_pre_init */
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xfff80000
+#endif
+
+#define CONFIG_PCI		1	/* Enable PCI/PCIE */
+#define CONFIG_PCI_PNP		1	/* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup */
+#define CONFIG_PCI1		1	/* PCI controller 1 */
+#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
+#define CONFIG_FSL_LAW		1	/* Use common FSL init code */
+
+/*
+ * DDR config
+ */
+#define CONFIG_SYS_FSL_DDR2
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
+#define CONFIG_DDR_SPD
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#define SPD_EEPROM_ADDRESS		0x54
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	2
+#define CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
+
+#define CONFIG_SYS_CLK_FREQ	66666666
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* toggle branch predition */
+#define CONFIG_ENABLE_36BIT_PHYS	1
+
+#define CONFIG_SYS_CCSRBAR		0xef000000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+
+/*
+ * Diagnostics
+ */
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_SYS_MEMTEST_START	0x10000000
+#define CONFIG_SYS_MEMTEST_END		0x20000000
+#define CONFIG_POST			(CONFIG_SYS_POST_MEMORY | \
+					 CONFIG_SYS_POST_I2C)
+#define I2C_ADDR_LIST			{CONFIG_SYS_I2C_MAX1237_ADDR,	\
+					 CONFIG_SYS_I2C_EEPROM_ADDR,	\
+					 CONFIG_SYS_I2C_PCA953X_ADDR0,	\
+					 CONFIG_SYS_I2C_PCA953X_ADDR1,	\
+					 CONFIG_SYS_I2C_RTC_ADDR}
+
+/*
+ * Memory map
+ * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
+ * 0x8000_0000	0xbfff_ffff	PCI1 Mem		1G non-cacheable
+ * 0xe000_0000	0xe7ff_ffff	SRAM/SSRAM/L1 Cache	128M non-cacheable
+ * 0xe800_0000	0xe87f_ffff	PCI1 IO			8M non-cacheable
+ * 0xef00_0000	0xef0f_ffff	CCSR/IMMR		1M non-cacheable
+ * 0xef80_0000	0xef8f_ffff	NAND Flash		1M non-cacheable
+ * 0xf800_0000	0xfbff_ffff	NOR Flash 2		64M non-cacheable
+ * 0xfc00_0000	0xffff_ffff	NOR Flash 1		64M non-cacheable
+ */
+
+#define CONFIG_SYS_LBC_LCRR	(LCRR_CLKDIV_8 | LCRR_EADC_3)
+
+/*
+ * NAND flash configuration
+ */
+#define CONFIG_SYS_NAND_BASE		0xef800000
+#define CONFIG_SYS_NAND_BASE2		0xef840000 /* Unused at this time */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_NAND_ACTL
+#define CONFIG_SYS_NAND_ACTL_CLE	(1 << 3)	/* ADDR3 is CLE */
+#define CONFIG_SYS_NAND_ACTL_ALE	(1 << 4)	/* ADDR4 is ALE */
+#define CONFIG_SYS_NAND_ACTL_NCE	(0)		/* NCE not controlled by ADDR */
+#define CONFIG_SYS_NAND_ACTL_DELAY	25
+
+/*
+ * NOR flash configuration
+ */
+#define CONFIG_SYS_FLASH_BASE		0xfc000000
+#define CONFIG_SYS_FLASH_BASE2		0xf8000000
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
+#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST	{ {0xfff40000, 0xc0000}, \
+						  {0xfbf40000, 0xc0000} }
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+
+/*
+ * Chip select configuration
+ */
+/* NOR Flash 0 on CS0 */
+#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE	| \
+				 BR_PS_16		| \
+				 BR_V)
+#define CONFIG_SYS_OR0_PRELIM	(OR_AM_64MB		| \
+				 OR_GPCM_ACS_DIV4	| \
+				 OR_GPCM_SCY_8)
+
+/* NOR Flash 1 on CS1 */
+#define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_FLASH_BASE2	| \
+				 BR_PS_16		| \
+				 BR_V)
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+
+/* NAND flash on CS2 */
+#define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_NAND_BASE	| \
+				 BR_PS_8		| \
+				 BR_V)
+
+/* NAND flash on CS2 */
+#define CONFIG_SYS_OR2_PRELIM	(OR_AM_256KB		| \
+				 OR_GPCM_BCTLD		| \
+				 OR_GPCM_CSNT		| \
+				 OR_GPCM_ACS_DIV4	| \
+				 OR_GPCM_SCY_4		| \
+				 OR_GPCM_TRLX		| \
+				 OR_GPCM_EHTR)
+
+/* NAND flash on CS3 */
+#define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_NAND_BASE2	| \
+				 BR_PS_8		| \
+				 BR_V)
+#define CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+
+/*
+ * Use L1 as initial stack
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xe0000000
+#define CONFIG_SYS_INIT_RAM_SIZE		0x4000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 KB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_LOADS_ECHO		1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * Use the HUSH parser
+ */
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT		1
+#define CONFIG_OF_BOARD_SETUP		1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+
+/* I2C EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6	/* 64 byte pages */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* take up to 10 msec */
+
+/* I2C RTC */
+#define CONFIG_RTC_M41T11			1
+#define CONFIG_SYS_I2C_RTC_ADDR			0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR		2000
+
+/* GPIO */
+#define CONFIG_PCA953X
+#define CONFIG_SYS_I2C_PCA953X_ADDR0		0x18
+#define CONFIG_SYS_I2C_PCA953X_ADDR1		0x19
+#define CONFIG_SYS_I2C_PCA953X_ADDR		CONFIG_SYS_I2C_PCA953X_ADDR0
+
+/* PCA957 @ 0x18 */
+#define CONFIG_SYS_PCA953X_BRD_CFG0		0x01
+#define CONFIG_SYS_PCA953X_BRD_CFG1		0x02
+#define CONFIG_SYS_PCA953X_BRD_CFG2		0x04
+#define CONFIG_SYS_PCA953X_XMC_ROOT0		0x08
+#define CONFIG_SYS_PCA953X_FLASH_PASS_CS	0x10
+#define CONFIG_SYS_PCA953X_NVM_WP		0x20
+#define CONFIG_SYS_PCA953X_MONARCH		0x40
+#define CONFIG_SYS_PCA953X_EREADY		0x80
+
+/* PCA957 @ 0x19 */
+#define CONFIG_SYS_PCA953X_P14_IO0		0x01
+#define CONFIG_SYS_PCA953X_P14_IO1		0x02
+#define CONFIG_SYS_PCA953X_P14_IO2		0x04
+#define CONFIG_SYS_PCA953X_P14_IO3		0x08
+#define CONFIG_SYS_PCA953X_P14_IO4		0x10
+#define CONFIG_SYS_PCA953X_P14_IO5		0x20
+#define CONFIG_SYS_PCA953X_P14_IO6		0x40
+#define CONFIG_SYS_PCA953X_P14_IO7		0x80
+
+/* 12-bit ADC used to measure CPU diode */
+#define CONFIG_SYS_I2C_MAX1237_ADDR		0x34
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+#define CONFIG_SYS_PCI1_MEM_BUS		0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BUS
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x40000000	/* 1G */
+#define CONFIG_SYS_PCI1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS		0xe8000000
+#define CONFIG_SYS_PCI1_IO_SIZE		0x00800000	/* 1M */
+
+/*
+ * Networking options
+ */
+#define CONFIG_TSEC_ENET		/* tsec ethernet support */
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+#define CONFIG_MII		1	/* MII PHY management */
+#define CONFIG_ETHPRIME		"eTSEC1"
+
+#define CONFIG_TSEC1		1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC1_PHY_ADDR		1
+#define TSEC1_PHYIDX		0
+#define CONFIG_HAS_ETH0
+
+#define CONFIG_TSEC2		1
+#define CONFIG_TSEC2_NAME	"eTSEC2"
+#define TSEC2_FLAGS		TSEC_GIGABIT
+#define TSEC2_PHY_ADDR		2
+#define TSEC2_PHYIDX		0
+#define CONFIG_HAS_ETH1
+
+#define CONFIG_TSEC3	1
+#define CONFIG_TSEC3_NAME	"eTSEC3"
+#define TSEC3_FLAGS		TSEC_GIGABIT
+#define TSEC3_PHY_ADDR		3
+#define TSEC3_PHYIDX		0
+#define CONFIG_HAS_ETH2
+
+#define CONFIG_TSEC4	1
+#define CONFIG_TSEC4_NAME	"eTSEC4"
+#define TSEC4_FLAGS		TSEC_GIGABIT
+#define TSEC4_PHY_ADDR		4
+#define TSEC4_PHYIDX		0
+#define CONFIG_HAS_ETH3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+
+/*
+ * Command configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCA953X
+#define CONFIG_CMD_PCA953X_INFO
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PCI_ENUM
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_REGINFO
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_CMDLINE_EDITING	1		/* add command line history	*/
+#define CONFIG_AUTO_COMPLETE	1		/* add autocompletion support */
+#define CONFIG_LOADADDR		0x1000000	/* default location for tftp and bootm */
+#define CONFIG_BOOTDELAY	3		/* -1 disables auto-boot */
+#define CONFIG_PANIC_HANG			/* do not reset board on panic */
+#define CONFIG_PREBOOT				/* enable preboot variable */
+#define CONFIG_FIT		1
+#define CONFIG_FIT_VERBOSE	1
+#define CONFIG_INTEGRITY			/* support booting INTEGRITY OS */
+#define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(16 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(16 << 20)	/* Increase max gunzip size */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_SECT_SIZE	0x20000		/* 128k (one sector) for env */
+#define CONFIG_ENV_SIZE		0x8000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - (256 * 1024))
+
+/*
+ * Flash memory map:
+ * fff80000 - ffffffff     Pri U-Boot (512 KB)
+ * fff40000 - fff7ffff     Pri U-Boot Environment (256 KB)
+ * fff00000 - fff3ffff     Pri FDT (256KB)
+ * fef00000 - ffefffff     Pri OS image (16MB)
+ * fc000000 - feefffff     Pri OS Use/Filesystem (47MB)
+ *
+ * fbf80000 - fbffffff     Sec U-Boot (512 KB)
+ * fbf40000 - fbf7ffff     Sec U-Boot Environment (256 KB)
+ * fbf00000 - fbf3ffff     Sec FDT (256KB)
+ * faf00000 - fbefffff     Sec OS image (16MB)
+ * f8000000 - faefffff     Sec OS Use/Filesystem (47MB)
+ */
+#define CONFIG_UBOOT1_ENV_ADDR	__stringify(0xfff80000)
+#define CONFIG_UBOOT2_ENV_ADDR	__stringify(0xfbf80000)
+#define CONFIG_FDT1_ENV_ADDR	__stringify(0xfff00000)
+#define CONFIG_FDT2_ENV_ADDR	__stringify(0xfbf00000)
+#define CONFIG_OS1_ENV_ADDR	__stringify(0xfef00000)
+#define CONFIG_OS2_ENV_ADDR	__stringify(0xfaf00000)
+
+#define CONFIG_PROG_UBOOT1						\
+	"$download_cmd $loadaddr $ubootfile; "				\
+	"if test $? -eq 0; then "					\
+		"protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
+		"erase "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
+		"cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; "	\
+		"protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
+		"cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; "	\
+		"if test $? -ne 0; then "				\
+			"echo PROGRAM FAILED; "				\
+		"else; "						\
+			"echo PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_UBOOT2						\
+	"$download_cmd $loadaddr $ubootfile; "				\
+	"if test $? -eq 0; then "					\
+		"protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
+		"erase "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
+		"cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; "	\
+		"protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
+		"cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; "	\
+		"if test $? -ne 0; then "				\
+			"echo PROGRAM FAILED; "				\
+		"else; "						\
+			"echo PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_BOOT_OS_NET						\
+	"$download_cmd $osaddr $osfile; "				\
+	"if test $? -eq 0; then "					\
+		"if test -n $fdtaddr; then "				\
+			"$download_cmd $fdtaddr $fdtfile; "		\
+			"if test $? -eq 0; then "			\
+				"bootm $osaddr - $fdtaddr; "		\
+			"else; "					\
+				"echo FDT DOWNLOAD FAILED; "		\
+			"fi; "						\
+		"else; "						\
+			"bootm $osaddr; "				\
+		"fi; "							\
+	"else; "							\
+		"echo OS DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_OS1							\
+	"$download_cmd $osaddr $osfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_OS1_ENV_ADDR" +$filesize; "		\
+		"cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
+		"cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo OS PROGRAM FAILED; "			\
+		"else; "						\
+			"echo OS PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo OS DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_OS2							\
+	"$download_cmd $osaddr $osfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_OS2_ENV_ADDR" +$filesize; "		\
+		"cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
+		"cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo OS PROGRAM FAILED; "			\
+		"else; "						\
+			"echo OS PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo OS DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_FDT1						\
+	"$download_cmd $fdtaddr $fdtfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_FDT1_ENV_ADDR" +$filesize;"		\
+		"cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
+		"cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo FDT PROGRAM FAILED; "			\
+		"else; "						\
+			"echo FDT PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo FDT DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_FDT2						\
+	"$download_cmd $fdtaddr $fdtfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_FDT2_ENV_ADDR" +$filesize;"		\
+		"cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
+		"cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo FDT PROGRAM FAILED; "			\
+		"else; "						\
+			"echo FDT PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo FDT DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"autoload=yes\0"						\
+	"download_cmd=tftp\0"						\
+	"console_args=console=ttyS0,115200\0"				\
+	"root_args=root=/dev/nfs rw\0"					\
+	"misc_args=ip=on\0"						\
+	"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
+	"bootfile=/home/user/file\0"					\
+	"osfile=/home/user/board.uImage\0"				\
+	"fdtfile=/home/user/board.dtb\0"				\
+	"ubootfile=/home/user/u-boot.bin\0"				\
+	"fdtaddr=c00000\0"						\
+	"osaddr=0x1000000\0"						\
+	"loadaddr=0x1000000\0"						\
+	"prog_uboot1="CONFIG_PROG_UBOOT1"\0"				\
+	"prog_uboot2="CONFIG_PROG_UBOOT2"\0"				\
+	"prog_os1="CONFIG_PROG_OS1"\0"					\
+	"prog_os2="CONFIG_PROG_OS2"\0"					\
+	"prog_fdt1="CONFIG_PROG_FDT1"\0"				\
+	"prog_fdt2="CONFIG_PROG_FDT2"\0"				\
+	"bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0"		\
+	"bootcmd_flash1=run set_bootargs; "				\
+		"bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
+	"bootcmd_flash2=run set_bootargs; "				\
+		"bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
+	"bootcmd=run bootcmd_flash1\0"
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/xpedite537x.h b/qemu/roms/u-boot/include/configs/xpedite537x.h
new file mode 100644
index 000000000..bdf55763d
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/xpedite537x.h
@@ -0,0 +1,601 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ * Copyright 2007-2008 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * xpedite537x board configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_BOOKE		1	/* BOOKE */
+#define CONFIG_E500		1	/* BOOKE e500 family */
+#define CONFIG_MPC8572		1
+#define CONFIG_XPEDITE5370	1
+#define CONFIG_SYS_BOARD_NAME	"XPedite5370"
+#define CONFIG_SYS_FORM_3U_VPX	1
+#define CONFIG_BOARD_EARLY_INIT_R	/* Call board_pre_init */
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xfff80000
+#endif
+
+#define CONFIG_PCI		1	/* Enable PCI/PCIE */
+#define CONFIG_PCI_PNP		1	/* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup */
+#define CONFIG_PCIE1		1	/* PCIE controler 1 */
+#define CONFIG_PCIE2		1	/* PCIE controler 2 */
+#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
+#define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
+#define CONFIG_FSL_LAW		1	/* Use common FSL init code */
+#define CONFIG_FSL_ELBC		1
+
+/*
+ * Multicore config
+ */
+#define CONFIG_MP
+#define CONFIG_BPTR_VIRT_ADDR	0xee000000	/* virt boot page address */
+#define CONFIG_MPC8xxx_DISABLE_BPTR		/* Don't leave BPTR enabled */
+
+/*
+ * DDR config
+ */
+#define CONFIG_SYS_FSL_DDR2
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
+#define CONFIG_DDR_SPD
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#define SPD_EEPROM_ADDRESS1		0x54	/* Both channels use the */
+#define SPD_EEPROM_ADDRESS2		0x54	/* same SPD data         */
+#define SPD_EEPROM_OFFSET		0x200	/* OFFSET of SPD in EEPROM */
+#define CONFIG_NUM_DDR_CONTROLLERS	2
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	1
+#define CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000 /* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_board_sys_clk(unsigned long dummy);
+extern unsigned long get_board_ddr_clk(unsigned long dummy);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0) /* sysclk for MPC85xx */
+#define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk(0) /* ddrclk for MPC85xx */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* toggle branch predition */
+#define CONFIG_ENABLE_36BIT_PHYS	1
+
+#define CONFIG_SYS_CCSRBAR		0xef000000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+
+/*
+ * Diagnostics
+ */
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_SYS_MEMTEST_START	0x10000000
+#define CONFIG_SYS_MEMTEST_END		0x20000000
+#define CONFIG_POST			(CONFIG_SYS_POST_MEMORY | \
+					 CONFIG_SYS_POST_I2C)
+#define I2C_ADDR_LIST			{CONFIG_SYS_I2C_DS1621_ADDR,	\
+					 CONFIG_SYS_I2C_DS4510_ADDR,	\
+					 CONFIG_SYS_I2C_EEPROM_ADDR,	\
+					 CONFIG_SYS_I2C_LM90_ADDR,	\
+					 CONFIG_SYS_I2C_PCA953X_ADDR0,	\
+					 CONFIG_SYS_I2C_PCA953X_ADDR1,	\
+					 CONFIG_SYS_I2C_PCA953X_ADDR2,	\
+					 CONFIG_SYS_I2C_PCA953X_ADDR3,	\
+					 CONFIG_SYS_I2C_PEX8518_ADDR,	\
+					 CONFIG_SYS_I2C_RTC_ADDR}
+/* The XPedite5370 can host an XMC which has an EEPROM at address 0x50 */
+#define I2C_ADDR_IGNORE_LIST		{0x50}
+
+/*
+ * Memory map
+ * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
+ * 0x8000_0000	0xbfff_ffff	PCIe1 Mem		1G non-cacheable
+ * 0xc000_0000	0xcfff_ffff	PCIe2 Mem		256M non-cacheable
+ * 0xe000_0000	0xe7ff_ffff	SRAM/SSRAM/L1 Cache	128M non-cacheable
+ * 0xe800_0000	0xe87f_ffff	PCIe1 IO		8M non-cacheable
+ * 0xe880_0000	0xe8ff_ffff	PCIe2 IO		8M non-cacheable
+ * 0xee00_0000	0xee00_ffff	Boot page translation	4K non-cacheable
+ * 0xef00_0000	0xef0f_ffff	CCSR/IMMR		1M non-cacheable
+ * 0xef80_0000	0xef8f_ffff	NAND Flash		1M non-cacheable
+ * 0xf000_0000	0xf7ff_ffff	NOR Flash 2		128M non-cacheable
+ * 0xf800_0000	0xffff_ffff	NOR Flash 1		128M non-cacheable
+ */
+
+#define CONFIG_SYS_LBC_LCRR	(LCRR_CLKDIV_8 | LCRR_EADC_3)
+
+/*
+ * NAND flash configuration
+ */
+#define CONFIG_SYS_NAND_BASE		0xef800000
+#define CONFIG_SYS_NAND_BASE2		0xef840000 /* Unused at this time */
+#define CONFIG_SYS_NAND_BASE_LIST	{CONFIG_SYS_NAND_BASE, \
+					 CONFIG_SYS_NAND_BASE2}
+#define CONFIG_SYS_MAX_NAND_DEVICE	2
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_SYS_NAND_QUIET_TEST	/* 2nd NAND flash not always populated */
+#define CONFIG_NAND_FSL_ELBC
+
+/*
+ * NOR flash configuration
+ */
+#define CONFIG_SYS_FLASH_BASE		0xf8000000
+#define CONFIG_SYS_FLASH_BASE2		0xf0000000
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
+#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST	{ {0xfff40000, 0xc0000}, \
+						  {0xf7f40000, 0xc0000} }
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+
+/*
+ * Chip select configuration
+ */
+/* NOR Flash 0 on CS0 */
+#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE	| \
+				 BR_PS_16		| \
+				 BR_V)
+#define CONFIG_SYS_OR0_PRELIM	(OR_AM_128MB		| \
+				 OR_GPCM_CSNT		| \
+				 OR_GPCM_XACS		| \
+				 OR_GPCM_ACS_DIV2	| \
+				 OR_GPCM_SCY_8		| \
+				 OR_GPCM_TRLX		| \
+				 OR_GPCM_EHTR		| \
+				 OR_GPCM_EAD)
+
+/* NOR Flash 1 on CS1 */
+#define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_FLASH_BASE2	| \
+				 BR_PS_16		| \
+				 BR_V)
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+
+/* NAND flash on CS2 */
+#define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_NAND_BASE	| \
+				 (2<<BR_DECC_SHIFT)	| \
+				 BR_PS_8		| \
+				 BR_MS_FCM		| \
+				 BR_V)
+
+/* NAND flash on CS2 */
+#define CONFIG_SYS_OR2_PRELIM	(OR_AM_256KB	| \
+				 OR_FCM_PGS	| \
+				 OR_FCM_CSCT	| \
+				 OR_FCM_CST	| \
+				 OR_FCM_CHT	| \
+				 OR_FCM_SCY_1	| \
+				 OR_FCM_TRLX	| \
+				 OR_FCM_EHTR)
+
+/* NAND flash on CS3 */
+#define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_NAND_BASE2	| \
+				 (2<<BR_DECC_SHIFT)	| \
+				 BR_PS_8		| \
+				 BR_MS_FCM		| \
+				 BR_V)
+#define CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+
+/*
+ * Use L1 as initial stack
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xe0000000
+#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 KB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_LOADS_ECHO		1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * Use the HUSH parser
+ */
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT		1
+#define CONFIG_OF_BOARD_SETUP		1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
+
+/* PEX8518 slave I2C interface */
+#define CONFIG_SYS_I2C_PEX8518_ADDR	0x70
+
+/* I2C DS1631 temperature sensor */
+#define CONFIG_SYS_I2C_DS1621_ADDR	0x48
+#define CONFIG_DTT_DS1621
+#define CONFIG_DTT_SENSORS		{ 0 }
+#define CONFIG_SYS_I2C_LM90_ADDR	0x4c
+
+/* I2C EEPROM - AT24C128B */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x54
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6	/* 64 byte pages */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* take up to 10 msec */
+
+/* I2C RTC */
+#define CONFIG_RTC_M41T11		1
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR	2000
+
+/* GPIO/EEPROM/SRAM */
+#define CONFIG_DS4510
+#define CONFIG_SYS_I2C_DS4510_ADDR	0x51
+
+/* GPIO */
+#define CONFIG_PCA953X
+#define CONFIG_SYS_I2C_PCA953X_ADDR0	0x18
+#define CONFIG_SYS_I2C_PCA953X_ADDR1	0x1c
+#define CONFIG_SYS_I2C_PCA953X_ADDR2	0x1e
+#define CONFIG_SYS_I2C_PCA953X_ADDR3	0x1f
+#define CONFIG_SYS_I2C_PCA953X_ADDR	CONFIG_SYS_I2C_PCA953X_ADDR0
+
+/*
+ * PU = pulled high, PD = pulled low
+ * I = input, O = output, IO = input/output
+ */
+/* PCA9557 @ 0x18*/
+#define CONFIG_SYS_PCA953X_C0_SER0_EN		0x01 /* PU; UART0 enable (1: enabled) */
+#define CONFIG_SYS_PCA953X_C0_SER0_MODE		0x02 /* PU; UART0 serial mode select */
+#define CONFIG_SYS_PCA953X_C0_SER1_EN		0x04 /* PU; UART1 enable (1: enabled) */
+#define CONFIG_SYS_PCA953X_C0_SER1_MODE		0x08 /* PU; UART1 serial mode select */
+#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS	0x10 /* PU; Boot flash CS select */
+#define CONFIG_SYS_PCA953X_NVM_WP		0x20 /* PU; Set to 0 to enable NVM writing */
+#define CONFIG_SYS_PCA953X_C0_VCORE_VID2	0x40 /* VID2 of ISL6262 */
+#define CONFIG_SYS_PCA953X_C0_VCORE_VID3	0x80 /* VID3 of ISL6262 */
+
+/* PCA9557 @ 0x1c*/
+#define CONFIG_SYS_PCA953X_XMC0_ROOT0		0x01 /* PU; Low if XMC is RC */
+#define CONFIG_SYS_PCA953X_XMC0_MVMR0		0x02 /* XMC EEPROM write protect */
+#define CONFIG_SYS_PCA953X_XMC0_WAKE		0x04 /* PU; XMC wake */
+#define CONFIG_SYS_PCA953X_XMC0_BIST		0x08 /* PU; XMC built in self test */
+#define CONFIG_SYS_PCA953X_XMC_PRESENT		0x10 /* PU; Low if XMC module installed */
+#define CONFIG_SYS_PCA953X_PMC_PRESENT		0x20 /* PU; Low if PMC module installed */
+#define CONFIG_SYS_PCA953X_PMC0_MONARCH		0x40 /* PMC monarch mode enable */
+#define CONFIG_SYS_PCA953X_PMC0_EREADY		0x80 /* PU; PMC PCI eready */
+
+/* PCA9557 @ 0x1e*/
+#define CONFIG_SYS_PCA953X_P0_GA0		0x01 /* PU; VPX Geographical address */
+#define CONFIG_SYS_PCA953X_P0_GA1		0x02 /* PU; VPX Geographical address */
+#define CONFIG_SYS_PCA953X_P0_GA2		0x04 /* PU; VPX Geographical address */
+#define CONFIG_SYS_PCA953X_P0_GA3		0x08 /* PU; VPX Geographical address */
+#define CONFIG_SYS_PCA953X_P0_GA4		0x10 /* PU; VPX Geographical address */
+#define CONFIG_SYS_PCA953X_P0_GAP		0x20 /* PU; tied to VPX P0.GAP */
+#define CONFIG_SYS_PCA953X_P1_SYSEN		0x80 /* PU; Pulled high; tied to VPX P1.SYSCON */
+
+/* PCA9557 @ 0x1f */
+#define CONFIG_SYS_PCA953X_GPIO_VPX0		0x01 /* PU */
+#define CONFIG_SYS_PCA953X_GPIO_VPX1		0x02 /* PU */
+#define CONFIG_SYS_PCA953X_GPIO_VPX2		0x04 /* PU */
+#define CONFIG_SYS_PCA953X_GPIO_VPX3		0x08 /* PU */
+#define CONFIG_SYS_PCA953X_VPX_FRU_WRCTL	0x10 /* PD; I2C master source for FRU SEEPROM */
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+/* PCIE1 - VPX P1 */
+#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BUS
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x40000000	/* 1G */
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xe8000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000	/* 8M */
+
+/* PCIE2 - PEX8518 */
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xc0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	CONFIG_SYS_PCIE2_MEM_BUS
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xe8800000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000	/* 8M */
+
+/*
+ * Networking options
+ */
+#define CONFIG_TSEC_ENET		/* tsec ethernet support */
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+#define CONFIG_TSEC_TBI
+#define CONFIG_MII		1	/* MII PHY management */
+#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
+#define CONFIG_ETHPRIME		"eTSEC2"
+
+/*
+ * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force
+ * 1000mbps SGMII link
+ */
+#define CONFIG_TSEC_TBICR_SETTINGS ( \
+		TBICR_PHY_RESET \
+		| TBICR_FULL_DUPLEX \
+		| TBICR_SPEED1_SET \
+		)
+
+#define CONFIG_TSEC1		1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC1_PHY_ADDR		1
+#define TSEC1_PHYIDX		0
+#define CONFIG_HAS_ETH0
+
+#define CONFIG_TSEC2		1
+#define CONFIG_TSEC2_NAME	"eTSEC2"
+#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_PHY_ADDR		2
+#define TSEC2_PHYIDX		0
+#define CONFIG_HAS_ETH1
+
+/*
+ * Command configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DS4510
+#define CONFIG_CMD_DS4510_INFO
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCA953X
+#define CONFIG_CMD_PCA953X_INFO
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PCI_ENUM
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_REGINFO
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_CMDLINE_EDITING	1		/* add command line history	*/
+#define CONFIG_AUTO_COMPLETE	1		/* add autocompletion support */
+#define CONFIG_LOADADDR		0x1000000	/* default location for tftp and bootm */
+#define CONFIG_BOOTDELAY	3		/* -1 disables auto-boot */
+#define CONFIG_PANIC_HANG			/* do not reset board on panic */
+#define CONFIG_PREBOOT				/* enable preboot variable */
+#define CONFIG_FIT		1
+#define CONFIG_FIT_VERBOSE	1
+#define CONFIG_INTEGRITY			/* support booting INTEGRITY OS */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(16 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(16 << 20)	/* Increase max gunzip size */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_SECT_SIZE	0x20000		/* 128k (one sector) for env */
+#define CONFIG_ENV_SIZE		0x8000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - (256 * 1024))
+
+/*
+ * Flash memory map:
+ * fff80000 - ffffffff     Pri U-Boot (512 KB)
+ * fff40000 - fff7ffff     Pri U-Boot Environment (256 KB)
+ * fff00000 - fff3ffff     Pri FDT (256KB)
+ * fef00000 - ffefffff     Pri OS image (16MB)
+ * f8000000 - feefffff     Pri OS Use/Filesystem (111MB)
+ *
+ * f7f80000 - f7ffffff     Sec U-Boot (512 KB)
+ * f7f40000 - f7f7ffff     Sec U-Boot Environment (256 KB)
+ * f7f00000 - f7f3ffff     Sec FDT (256KB)
+ * f6f00000 - f7efffff     Sec OS image (16MB)
+ * f0000000 - f6efffff     Sec OS Use/Filesystem (111MB)
+ */
+#define CONFIG_UBOOT1_ENV_ADDR	__stringify(0xfff80000)
+#define CONFIG_UBOOT2_ENV_ADDR	__stringify(0xf7f80000)
+#define CONFIG_FDT1_ENV_ADDR	__stringify(0xfff00000)
+#define CONFIG_FDT2_ENV_ADDR	__stringify(0xf7f00000)
+#define CONFIG_OS1_ENV_ADDR	__stringify(0xfef00000)
+#define CONFIG_OS2_ENV_ADDR	__stringify(0xf6f00000)
+
+#define CONFIG_PROG_UBOOT1						\
+	"$download_cmd $loadaddr $ubootfile; "				\
+	"if test $? -eq 0; then "					\
+		"protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
+		"erase "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
+		"cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; "	\
+		"protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
+		"cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; "	\
+		"if test $? -ne 0; then "				\
+			"echo PROGRAM FAILED; "				\
+		"else; "						\
+			"echo PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_UBOOT2						\
+	"$download_cmd $loadaddr $ubootfile; "				\
+	"if test $? -eq 0; then "					\
+		"protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
+		"erase "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
+		"cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; "	\
+		"protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
+		"cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; "	\
+		"if test $? -ne 0; then "				\
+			"echo PROGRAM FAILED; "				\
+		"else; "						\
+			"echo PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_BOOT_OS_NET						\
+	"$download_cmd $osaddr $osfile; "				\
+	"if test $? -eq 0; then "					\
+		"if test -n $fdtaddr; then "				\
+			"$download_cmd $fdtaddr $fdtfile; "		\
+			"if test $? -eq 0; then "			\
+				"bootm $osaddr - $fdtaddr; "		\
+			"else; "					\
+				"echo FDT DOWNLOAD FAILED; "		\
+			"fi; "						\
+		"else; "						\
+			"bootm $osaddr; "				\
+		"fi; "							\
+	"else; "							\
+		"echo OS DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_OS1							\
+	"$download_cmd $osaddr $osfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_OS1_ENV_ADDR" +$filesize; "		\
+		"cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
+		"cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo OS PROGRAM FAILED; "			\
+		"else; "						\
+			"echo OS PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo OS DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_OS2							\
+	"$download_cmd $osaddr $osfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_OS2_ENV_ADDR" +$filesize; "		\
+		"cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
+		"cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo OS PROGRAM FAILED; "			\
+		"else; "						\
+			"echo OS PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo OS DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_FDT1						\
+	"$download_cmd $fdtaddr $fdtfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_FDT1_ENV_ADDR" +$filesize;"		\
+		"cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
+		"cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo FDT PROGRAM FAILED; "			\
+		"else; "						\
+			"echo FDT PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo FDT DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_FDT2						\
+	"$download_cmd $fdtaddr $fdtfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_FDT2_ENV_ADDR" +$filesize;"		\
+		"cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
+		"cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo FDT PROGRAM FAILED; "			\
+		"else; "						\
+			"echo FDT PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo FDT DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"autoload=yes\0"						\
+	"download_cmd=tftp\0"						\
+	"console_args=console=ttyS0,115200\0"				\
+	"root_args=root=/dev/nfs rw\0"					\
+	"misc_args=ip=on\0"						\
+	"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
+	"bootfile=/home/user/file\0"					\
+	"osfile=/home/user/board.uImage\0"				\
+	"fdtfile=/home/user/board.dtb\0"				\
+	"ubootfile=/home/user/u-boot.bin\0"				\
+	"fdtaddr=c00000\0"						\
+	"osaddr=0x1000000\0"						\
+	"loadaddr=0x1000000\0"						\
+	"prog_uboot1="CONFIG_PROG_UBOOT1"\0"				\
+	"prog_uboot2="CONFIG_PROG_UBOOT2"\0"				\
+	"prog_os1="CONFIG_PROG_OS1"\0"					\
+	"prog_os2="CONFIG_PROG_OS2"\0"					\
+	"prog_fdt1="CONFIG_PROG_FDT1"\0"				\
+	"prog_fdt2="CONFIG_PROG_FDT2"\0"				\
+	"bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0"		\
+	"bootcmd_flash1=run set_bootargs; "				\
+		"bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
+	"bootcmd_flash2=run set_bootargs; "				\
+		"bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
+	"bootcmd=run bootcmd_flash1\0"
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/xpedite550x.h b/qemu/roms/u-boot/include/configs/xpedite550x.h
new file mode 100644
index 000000000..0b24f3e8d
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/xpedite550x.h
@@ -0,0 +1,586 @@
+/*
+ * Copyright 2010 Extreme Engineering Solutions, Inc.
+ * Copyright 2007-2008 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * xpedite550x board configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_BOOKE		1	/* BOOKE */
+#define CONFIG_E500		1	/* BOOKE e500 family */
+#define CONFIG_P2020		1
+#define CONFIG_XPEDITE550X	1
+#define CONFIG_SYS_BOARD_NAME	"XPedite5500"
+#define CONFIG_SYS_FORM_PMC_XMC	1
+#define CONFIG_PRPMC_PCI_ALIAS	"pci0"	/* Processor PMC interface on pci0 */
+#define CONFIG_BOARD_EARLY_INIT_R	/* Call board_pre_init */
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xfff80000
+#endif
+
+#define CONFIG_PCI		1	/* Enable PCI/PCIE */
+#define CONFIG_PCI_PNP		1	/* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup */
+#define CONFIG_PCIE1		1	/* PCIE controler 1 (PEX8112 or XMC) */
+#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
+#define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
+#define CONFIG_FSL_LAW		1	/* Use common FSL init code */
+#define CONFIG_FSL_ELBC		1
+
+/*
+ * Multicore config
+ */
+#define CONFIG_MP
+#define CONFIG_BPTR_VIRT_ADDR	0xee000000	/* virt boot page address */
+#define CONFIG_MPC8xxx_DISABLE_BPTR		/* Don't leave BPTR enabled */
+
+/*
+ * DDR config
+ */
+#define CONFIG_SYS_FSL_DDR3
+#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
+#define CONFIG_DDR_SPD
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#define SPD_EEPROM_ADDRESS			0x54
+#define SPD_EEPROM_OFFSET		0x200	/* OFFSET of SPD in EEPROM */
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL 2
+#define CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000 /* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_board_sys_clk(unsigned long dummy);
+extern unsigned long get_board_ddr_clk(unsigned long dummy);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0) /* sysclk for MPC85xx */
+#define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk(0) /* ddrclk for MPC85xx */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* toggle branch predition */
+#define CONFIG_ENABLE_36BIT_PHYS	1
+
+#define CONFIG_SYS_CCSRBAR		0xef000000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+
+/*
+ * Diagnostics
+ */
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_SYS_MEMTEST_START	0x10000000
+#define CONFIG_SYS_MEMTEST_END		0x20000000
+#define CONFIG_POST			(CONFIG_SYS_POST_MEMORY | \
+					 CONFIG_SYS_POST_I2C)
+#define I2C_ADDR_LIST			{CONFIG_SYS_I2C_EEPROM_ADDR,	\
+					 CONFIG_SYS_I2C_LM75_ADDR,	\
+					 CONFIG_SYS_I2C_LM90_ADDR,	\
+					 CONFIG_SYS_I2C_PCA953X_ADDR0,	\
+					 CONFIG_SYS_I2C_PCA953X_ADDR2,	\
+					 CONFIG_SYS_I2C_PCA953X_ADDR3,	\
+					 CONFIG_SYS_I2C_RTC_ADDR}
+
+/*
+ * Memory map
+ * 0x0000_0000 0x7fff_ffff	DDR			2G Cacheable
+ * 0x8000_0000 0xbfff_ffff	PCIe1 Mem		1G non-cacheable
+ * 0xe000_0000 0xe7ff_ffff	SRAM/SSRAM/L1 Cache	128M non-cacheable
+ * 0xe800_0000 0xe87f_ffff	PCIe1 IO		8M non-cacheable
+ * 0xee00_0000 0xee00_ffff	Boot page translation	4K non-cacheable
+ * 0xef00_0000 0xef0f_ffff	CCSR/IMMR		1M non-cacheable
+ * 0xef80_0000 0xef8f_ffff	NAND Flash		1M non-cacheable
+ * 0xf000_0000 0xf7ff_ffff	NOR Flash 2		128M non-cacheable
+ * 0xf800_0000 0xffff_ffff	NOR Flash 1		128M non-cacheable
+ */
+
+#define CONFIG_SYS_LBC_LCRR	(LCRR_CLKDIV_8 | LCRR_EADC_3)
+
+/*
+ * NAND flash configuration
+ */
+#define CONFIG_SYS_NAND_BASE		0xef800000
+#define CONFIG_SYS_NAND_BASE2		0xef840000 /* Unused at this time */
+#define CONFIG_SYS_NAND_BASE_LIST	{CONFIG_SYS_NAND_BASE, \
+					 CONFIG_SYS_NAND_BASE2}
+#define CONFIG_SYS_MAX_NAND_DEVICE	2
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_SYS_NAND_QUIET_TEST	/* 2nd NAND flash not always populated */
+#define CONFIG_NAND_FSL_ELBC
+
+/*
+ * NOR flash configuration
+ */
+#define CONFIG_SYS_FLASH_BASE		0xf8000000
+#define CONFIG_SYS_FLASH_BASE2		0xf0000000
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
+#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST	{ {0xfff40000, 0xc0000}, \
+						  {0xf7f40000, 0xc0000} }
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
+
+/*
+ * Chip select configuration
+ */
+/* NOR Flash 0 on CS0 */
+#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE	| \
+				 BR_PS_16		| \
+				 BR_V)
+#define CONFIG_SYS_OR0_PRELIM	(OR_AM_128MB		| \
+				 OR_GPCM_CSNT		| \
+				 OR_GPCM_XACS		| \
+				 OR_GPCM_ACS_DIV2	| \
+				 OR_GPCM_SCY_8		| \
+				 OR_GPCM_TRLX		| \
+				 OR_GPCM_EHTR		| \
+				 OR_GPCM_EAD)
+
+/* NOR Flash 1 on CS1 */
+#define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_FLASH_BASE2	| \
+				 BR_PS_16		| \
+				 BR_V)
+#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
+
+/* NAND flash on CS2 */
+#define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_NAND_BASE	| \
+				 (2<<BR_DECC_SHIFT)	| \
+				 BR_PS_8		| \
+				 BR_MS_FCM		| \
+				 BR_V)
+
+/* NAND flash on CS2 */
+#define CONFIG_SYS_OR2_PRELIM	(OR_AM_256KB	| \
+				 OR_FCM_PGS	| \
+				 OR_FCM_CSCT	| \
+				 OR_FCM_CST	| \
+				 OR_FCM_CHT	| \
+				 OR_FCM_SCY_1	| \
+				 OR_FCM_TRLX	| \
+				 OR_FCM_EHTR)
+
+/* NAND flash on CS3 */
+#define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_NAND_BASE2	| \
+				 (2<<BR_DECC_SHIFT)	| \
+				 BR_PS_8		| \
+				 BR_MS_FCM		| \
+				 BR_V)
+#define CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
+
+/*
+ * Use L1 as initial stack
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xe0000000
+#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 KB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_LOADS_ECHO		1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * Use the HUSH parser
+ */
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT		1
+#define CONFIG_OF_BOARD_SETUP		1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+#define CONFIG_FDT_FIXUP_PCI_IRQ	1
+
+/*
+ * I2C
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	400000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+
+/* I2C DS7505 temperature sensor */
+#define CONFIG_DTT_LM75
+#define CONFIG_DTT_SENSORS		{ 0 }
+#define CONFIG_SYS_I2C_LM75_ADDR	0x48
+
+/* I2C ADT7461 temperature sensor */
+#define CONFIG_SYS_I2C_LM90_ADDR	0x4C
+
+/* I2C EEPROM - AT24C128B */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x54
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6	/* 64 byte pages */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* take up to 10 msec */
+
+/* I2C RTC */
+#define CONFIG_RTC_M41T11		1
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR	2000
+
+/* GPIO */
+#define CONFIG_PCA953X
+#define CONFIG_SYS_I2C_PCA953X_ADDR0	0x18
+#define CONFIG_SYS_I2C_PCA953X_ADDR1	0x1c
+#define CONFIG_SYS_I2C_PCA953X_ADDR2	0x1e
+#define CONFIG_SYS_I2C_PCA953X_ADDR3	0x1f
+#define CONFIG_SYS_I2C_PCA953X_ADDR	CONFIG_SYS_I2C_PCA953X_ADDR0
+
+/*
+ * GPIO pin definitions, PU = pulled high, PD = pulled low
+ */
+/* PCA9557 @ 0x18*/
+#define CONFIG_SYS_PCA953X_C0_SER0_EN		0x01 /* PU; UART0 enable (1: enabled) */
+#define CONFIG_SYS_PCA953X_C0_SER0_MODE		0x02 /* PU; UART0 serial mode select (1: RS-485, 0: RS-232) */
+#define CONFIG_SYS_PCA953X_C0_SER1_EN		0x04 /* PU; UART1 enable (1: enabled) */
+#define CONFIG_SYS_PCA953X_C0_SER1_MODE		0x08 /* PU; UART1 serial mode select (1: RS-485, 0: RS-232) */
+#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS	0x10 /* PU; Boot flash CS select */
+#define CONFIG_SYS_PCA953X_NVM_WP		0x20 /* PU; Write protection (0: disabled, 1: enabled) */
+
+/* PCA9557 @ 0x1e*/
+#define CONFIG_SYS_PCA953X_XMC_GA0		0x01 /* PU; */
+#define CONFIG_SYS_PCA953X_XMC_GA1		0x02 /* PU; */
+#define CONFIG_SYS_PCA953X_XMC_GA2		0x04 /* PU; */
+#define CONFIG_SYS_PCA953X_XMC_WAKE		0x10 /* PU; */
+#define CONFIG_SYS_PCA953X_XMC_BIST		0x20 /* Enable XMC BIST */
+#define CONFIG_SYS_PCA953X_PMC_EREADY		0x40 /* PU; PMC PCI eready */
+#define CONFIG_SYS_PCA953X_PMC_MONARCH		0x80 /* PMC monarch mode enable */
+
+/* PCA9557 @ 0x1f */
+#define CONFIG_SYS_PCA953X_MC_GPIO0		0x01 /* PU; */
+#define CONFIG_SYS_PCA953X_MC_GPIO1		0x02 /* PU; */
+#define CONFIG_SYS_PCA953X_MC_GPIO2		0x04 /* PU; */
+#define CONFIG_SYS_PCA953X_MC_GPIO3		0x08 /* PU; */
+#define CONFIG_SYS_PCA953X_MC_GPIO4		0x10 /* PU; */
+#define CONFIG_SYS_PCA953X_MC_GPIO5		0x20 /* PU; */
+#define CONFIG_SYS_PCA953X_MC_GPIO6		0x40 /* PU; */
+#define CONFIG_SYS_PCA953X_MC_GPIO7		0x80 /* PU; */
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 1 - PEX8112 or XMC, depending on build option */
+#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BUS
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x40000000	/* 1G */
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xe8000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000	/* 8M */
+
+
+/*
+ * Networking options
+ */
+#define CONFIG_TSEC_ENET		/* tsec ethernet support */
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+#define CONFIG_TSEC_TBI
+#define CONFIG_MII		1	/* MII PHY management */
+#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
+#define CONFIG_ETHPRIME		"eTSEC2"
+
+/*
+ * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force
+ * 1000mbps SGMII link
+ */
+#define CONFIG_TSEC_TBICR_SETTINGS ( \
+		TBICR_PHY_RESET \
+		| TBICR_FULL_DUPLEX \
+		| TBICR_SPEED1_SET \
+		)
+
+#define CONFIG_TSEC1		1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC1_PHY_ADDR		1
+#define TSEC1_PHYIDX		0
+#define CONFIG_HAS_ETH0
+
+#define CONFIG_TSEC2		1
+#define CONFIG_TSEC2_NAME	"eTSEC2"
+#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_PHY_ADDR		2
+#define TSEC2_PHYIDX		0
+#define CONFIG_HAS_ETH1
+
+#define CONFIG_TSEC3		1
+#define CONFIG_TSEC3_NAME	"eTSEC3"
+#define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_PHY_ADDR		3
+#define TSEC3_PHYIDX		0
+#define CONFIG_HAS_ETH2
+
+/*
+ * USB
+ */
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_DOS_PARTITION
+
+/*
+ * Command configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCA953X
+#define CONFIG_CMD_PCA953X_INFO
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PCI_ENUM
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_USB
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_CMDLINE_EDITING	1		/* add command line history	*/
+#define CONFIG_AUTO_COMPLETE	1		/* add autocompletion support */
+#define CONFIG_LOADADDR		0x1000000	/* default location for tftp and bootm */
+#define CONFIG_BOOTDELAY	3		/* -1 disables auto-boot */
+#define CONFIG_PANIC_HANG			/* do not reset board on panic */
+#define CONFIG_PREBOOT				/* enable preboot variable */
+#define CONFIG_FIT		1
+#define CONFIG_FIT_VERBOSE	1
+#define CONFIG_INTEGRITY			/* support booting INTEGRITY OS */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(16 << 20)	/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(16 << 20)	/* Increase max gunzip size */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_SECT_SIZE	0x20000		/* 128k (one sector) for env */
+#define CONFIG_ENV_SIZE		0x8000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - (256 * 1024))
+
+/*
+ * Flash memory map:
+ * fff80000 - ffffffff     Pri U-Boot (512 KB)
+ * fff40000 - fff7ffff     Pri U-Boot Environment (256 KB)
+ * fff00000 - fff3ffff     Pri FDT (256KB)
+ * fef00000 - ffefffff     Pri OS image (16MB)
+ * f8000000 - feefffff     Pri OS Use/Filesystem (111MB)
+ *
+ * f7f80000 - f7ffffff     Sec U-Boot (512 KB)
+ * f7f40000 - f7f7ffff     Sec U-Boot Environment (256 KB)
+ * f7f00000 - f7f3ffff     Sec FDT (256KB)
+ * f6f00000 - f7efffff     Sec OS image (16MB)
+ * f0000000 - f6efffff     Sec OS Use/Filesystem (111MB)
+ */
+#define CONFIG_UBOOT1_ENV_ADDR	__stringify(0xfff80000)
+#define CONFIG_UBOOT2_ENV_ADDR	__stringify(0xf7f80000)
+#define CONFIG_FDT1_ENV_ADDR	__stringify(0xfff00000)
+#define CONFIG_FDT2_ENV_ADDR	__stringify(0xf7f00000)
+#define CONFIG_OS1_ENV_ADDR	__stringify(0xfef00000)
+#define CONFIG_OS2_ENV_ADDR	__stringify(0xf6f00000)
+
+#define CONFIG_PROG_UBOOT1						\
+	"$download_cmd $loadaddr $ubootfile; "				\
+	"if test $? -eq 0; then "					\
+		"protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
+		"erase "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
+		"cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; "	\
+		"protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; "		\
+		"cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; "	\
+		"if test $? -ne 0; then "				\
+			"echo PROGRAM FAILED; "				\
+		"else; "						\
+			"echo PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_UBOOT2						\
+	"$download_cmd $loadaddr $ubootfile; "				\
+	"if test $? -eq 0; then "					\
+		"protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
+		"erase "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
+		"cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; "	\
+		"protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; "		\
+		"cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; "	\
+		"if test $? -ne 0; then "				\
+			"echo PROGRAM FAILED; "				\
+		"else; "						\
+			"echo PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_BOOT_OS_NET						\
+	"$download_cmd $osaddr $osfile; "				\
+	"if test $? -eq 0; then "					\
+		"if test -n $fdtaddr; then "				\
+			"$download_cmd $fdtaddr $fdtfile; "		\
+			"if test $? -eq 0; then "			\
+				"bootm $osaddr - $fdtaddr; "		\
+			"else; "					\
+				"echo FDT DOWNLOAD FAILED; "		\
+			"fi; "						\
+		"else; "						\
+			"bootm $osaddr; "				\
+		"fi; "							\
+	"else; "							\
+		"echo OS DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_OS1							\
+	"$download_cmd $osaddr $osfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_OS1_ENV_ADDR" +$filesize; "		\
+		"cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
+		"cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo OS PROGRAM FAILED; "			\
+		"else; "						\
+			"echo OS PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo OS DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_OS2							\
+	"$download_cmd $osaddr $osfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_OS2_ENV_ADDR" +$filesize; "		\
+		"cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
+		"cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo OS PROGRAM FAILED; "			\
+		"else; "						\
+			"echo OS PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo OS DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_FDT1						\
+	"$download_cmd $fdtaddr $fdtfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_FDT1_ENV_ADDR" +$filesize;"		\
+		"cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
+		"cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo FDT PROGRAM FAILED; "			\
+		"else; "						\
+			"echo FDT PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo FDT DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_PROG_FDT2						\
+	"$download_cmd $fdtaddr $fdtfile; "				\
+	"if test $? -eq 0; then "					\
+		"erase "CONFIG_FDT2_ENV_ADDR" +$filesize;"		\
+		"cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
+		"cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "	\
+		"if test $? -ne 0; then "				\
+			"echo FDT PROGRAM FAILED; "			\
+		"else; "						\
+			"echo FDT PROGRAM SUCCEEDED; "			\
+		"fi; "							\
+	"else; "							\
+		"echo FDT DOWNLOAD FAILED; "				\
+	"fi;"
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"autoload=yes\0"						\
+	"download_cmd=tftp\0"						\
+	"console_args=console=ttyS0,115200\0"				\
+	"root_args=root=/dev/nfs rw\0"					\
+	"misc_args=ip=on\0"						\
+	"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
+	"bootfile=/home/user/file\0"					\
+	"osfile=/home/user/board.uImage\0"				\
+	"fdtfile=/home/user/board.dtb\0"				\
+	"ubootfile=/home/user/u-boot.bin\0"				\
+	"fdtaddr=c00000\0"						\
+	"osaddr=0x1000000\0"						\
+	"loadaddr=0x1000000\0"						\
+	"prog_uboot1="CONFIG_PROG_UBOOT1"\0"				\
+	"prog_uboot2="CONFIG_PROG_UBOOT2"\0"				\
+	"prog_os1="CONFIG_PROG_OS1"\0"					\
+	"prog_os2="CONFIG_PROG_OS2"\0"					\
+	"prog_fdt1="CONFIG_PROG_FDT1"\0"				\
+	"prog_fdt2="CONFIG_PROG_FDT2"\0"				\
+	"bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0"		\
+	"bootcmd_flash1=run set_bootargs; "				\
+		"bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
+	"bootcmd_flash2=run set_bootargs; "				\
+		"bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
+	"bootcmd=run bootcmd_flash1\0"
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/yosemite.h b/qemu/roms/u-boot/include/configs/yosemite.h
new file mode 100644
index 000000000..8508a8029
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/yosemite.h
@@ -0,0 +1,236 @@
+/*
+ * (C) Copyright 2005-2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/************************************************************************
+ * yosemite.h - configuration for Yosemite & Yellowstone boards
+ ***********************************************************************/
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+/* This config file is used for Yosemite (440EP) and Yellowstone (440GR)*/
+#ifndef CONFIG_YELLOWSTONE
+#define CONFIG_440EP		1	/* Specific PPC440EP support	*/
+#define CONFIG_HOSTNAME		yosemite
+#else
+#define CONFIG_440GR		1	/* Specific PPC440GR support	*/
+#define CONFIG_HOSTNAME		yellowstone
+#endif
+#define CONFIG_440		1	/* ... PPC440 family		*/
+#define CONFIG_SYS_CLK_FREQ	66666666    /* external freq to pll	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFF80000
+
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#include "amcc-common.h"
+
+#define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f	*/
+#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
+#define CONFIG_BOARD_RESET	1	/* call board_reset()		*/
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_FLASH_BASE	        0xfc000000	    /* start of FLASH	*/
+#define CONFIG_SYS_PCI_MEMBASE	        0xa0000000	    /* mapped pci memory*/
+#define CONFIG_SYS_PCI_MEMBASE1        CONFIG_SYS_PCI_MEMBASE  + 0x10000000
+#define CONFIG_SYS_PCI_MEMBASE2        CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
+#define CONFIG_SYS_PCI_MEMBASE3        CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
+
+/*Don't change either of these*/
+#define CONFIG_SYS_PCI_BASE	        0xe0000000	    /* internal PCI regs*/
+/*Don't change either of these*/
+
+#define CONFIG_SYS_USB_DEVICE          0x50000000
+#define CONFIG_SYS_NVRAM_BASE_ADDR     0x80000000
+#define CONFIG_SYS_BCSR_BASE	        (CONFIG_SYS_NVRAM_BASE_ADDR | 0x2000)
+#define CONFIG_SYS_BOOT_BASE_ADDR      0xf0000000
+
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in SDRAM)
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_INIT_RAM_DCACHE	1		/* d-cache as init ram	*/
+#define CONFIG_SYS_INIT_RAM_ADDR	0x70000000		/* DCache       */
+#define CONFIG_SYS_INIT_RAM_SIZE	(4 << 10)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#define CONFIG_SYS_EXT_SERIAL_CLOCK	11059200 /* use external 11.059MHz clk	*/
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+/*
+ * Define here the location of the environment variables (FLASH or EEPROM).
+ * Note: DENX encourages to use redundant environment in FLASH.
+ */
+#if 1
+#define CONFIG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
+#else
+#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_FLASH_CFI				/* The flash is CFI compatible	*/
+#define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/
+#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1		/* AMD RESET for STM 29W320DB!	*/
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector		*/
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
+#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+#endif /* CONFIG_ENV_IS_IN_FLASH */
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#undef CONFIG_SPD_EEPROM	       /* Don't use SPD EEPROM for setup    */
+#define CONFIG_SYS_KBYTES_SDRAM        (128 * 1024)    /* 128MB		    */
+#define CONFIG_SYS_SDRAM_BANKS	        (2)
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
+
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR	(0xa8>>1)
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+#ifdef CONFIG_ENV_IS_IN_EEPROM
+#define CONFIG_ENV_SIZE		0x200	    /* Size of Environment vars */
+#define CONFIG_ENV_OFFSET		0x0
+#endif /* CONFIG_ENV_IS_IN_EEPROM */
+
+/* I2C SYSMON (LM75, AD7414 is almost compatible)			*/
+#define CONFIG_DTT_LM75		1		/* ON Semi's LM75	*/
+#define CONFIG_DTT_AD7414	1		/* use AD7414		*/
+#define CONFIG_DTT_SENSORS	{0}		/* Sensor addresses	*/
+#define CONFIG_SYS_DTT_MAX_TEMP	70
+#define CONFIG_SYS_DTT_LOW_TEMP	-30
+#define CONFIG_SYS_DTT_HYSTERESIS	3
+
+/*
+ * Default environment variables
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_AMCC_DEF_ENV						\
+	CONFIG_AMCC_DEF_ENV_POWERPC					\
+	CONFIG_AMCC_DEF_ENV_PPC_OLD					\
+	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
+	"kernel_addr=fc000000\0"					\
+	"ramdisk_addr=fc180000\0"					\
+	""
+
+#define CONFIG_HAS_ETH0		1	/* add support for "ethaddr"	*/
+#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
+#define CONFIG_PHY_ADDR		1	/* PHY address, See schematics	*/
+#define CONFIG_PHY1_ADDR        3
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+#ifdef CONFIG_440EP
+/* USB */
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_USB_STORAGE
+#define CONFIG_SYS_OHCI_BE_CONTROLLER
+
+#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
+#define CONFIG_SYS_USB_OHCI_CPU_INIT	1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE	(CONFIG_SYS_PERIPHERAL_BASE | 0x1000)
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"ppc440"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
+
+/* Comment this out to enable USB 1.1 device */
+#define USB_2_0_DEVICE
+
+#define CONFIG_SUPPORT_VFAT
+#endif /* CONFIG_440EP */
+
+#ifdef DEBUG
+#define CONFIG_PANIC_HANG
+#else
+#define CONFIG_HW_WATCHDOG			/* watchdog */
+#endif
+
+/*
+ * Commands additional to the ones defined in amcc-common.h
+ */
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_PCI
+
+#ifdef CONFIG_440EP
+    #define CONFIG_CMD_USB
+    #define CONFIG_CMD_FAT
+    #define CONFIG_CMD_EXT2
+#endif
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+/* General PCI */
+#define CONFIG_PCI			/* include pci support	        */
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#undef  CONFIG_PCI_PNP			/* do (not) pci plug-and-play   */
+#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
+#define CONFIG_SYS_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
+
+/* Board-specific PCI */
+#define CONFIG_SYS_PCI_TARGET_INIT
+#define CONFIG_SYS_PCI_MASTER_INIT
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
+#define CONFIG_SYS_PCI_SUBSYS_ID       0xcafe	/* Whatever */
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_FLASH		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CPLD		0x80000000
+
+/* Memory Bank 0 (NOR-FLASH) initialization					*/
+#define CONFIG_SYS_EBC_PB0AP		0x03017300
+#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_FLASH | 0xda000)
+
+/* Memory Bank 2 (CPLD) initialization						*/
+#define CONFIG_SYS_EBC_PB2AP		0x04814500
+#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_CPLD | 0x18000)
+
+#define CONFIG_SYS_BCSR5_PCI66EN	0x80
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/yucca.h b/qemu/roms/u-boot/include/configs/yucca.h
new file mode 100644
index 000000000..76717e457
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/yucca.h
@@ -0,0 +1,413 @@
+/*
+ * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/************************************************************************
+ * 1 january 2005	Alain Saurel <asaurel@amcc.com>
+ * Adapted to current Das U-Boot source
+ ***********************************************************************/
+/************************************************************************
+ * yucca.h - configuration for AMCC 440SPe Ref (yucca)
+ ***********************************************************************/
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_440			1	/* ... PPC440 family	*/
+#define CONFIG_440SPE			1	/* Specifc SPe support	*/
+#define CONFIG_440SPE_REVA		1	/* Support old Rev A.	*/
+#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init	*/
+#define CONFIG_SYS_CLK_FREQ	33333333	/* external freq to pll	*/
+#define EXTCLK_33_33		33333333
+#define EXTCLK_66_66		66666666
+#define EXTCLK_50		50000000
+#define EXTCLK_83		83333333
+
+#define	CONFIG_SYS_TEXT_BASE	0xfffb0000
+
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME		yucca
+#include "amcc-common.h"
+
+#define	CONFIG_MISC_INIT_F	1	/* Use misc_init_f()		*/
+#undef  CONFIG_SHOW_BOOT_PROGRESS
+#undef  CONFIG_STRESS
+
+/*-----------------------------------------------------------------------
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_FLASH_BASE		0xfff00000	/* start of FLASH	*/
+#define CONFIG_SYS_ISRAM_BASE		0x90000000	/* internal SRAM	*/
+
+#define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped PCI memory	*/
+#define CONFIG_SYS_PCI_BASE		0xd0000000	/* internal PCI regs	*/
+#define CONFIG_SYS_PCI_TARGBASE	CONFIG_SYS_PCI_MEMBASE
+
+#define CONFIG_SYS_PCIE_MEMBASE	0xb0000000	/* mapped PCIe memory	*/
+#define CONFIG_SYS_PCIE_MEMSIZE	0x08000000	/* smallest incr for PCIe port */
+#define CONFIG_SYS_PCIE_BASE		0xe0000000	/* PCIe UTL regs */
+
+#define CONFIG_SYS_PCIE0_CFGBASE	0xc0000000
+#define CONFIG_SYS_PCIE1_CFGBASE	0xc1000000
+#define CONFIG_SYS_PCIE2_CFGBASE	0xc2000000
+#define CONFIG_SYS_PCIE0_XCFGBASE	0xc3000000
+#define CONFIG_SYS_PCIE1_XCFGBASE	0xc3001000
+#define CONFIG_SYS_PCIE2_XCFGBASE	0xc3002000
+
+/* base address of inbound PCIe window */
+#define CONFIG_SYS_PCIE_INBOUND_BASE	0x0000000400000000ULL
+
+/* System RAM mapped to PCI space */
+#define CONFIG_PCI_SYS_MEM_BUS	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_PHYS	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_SIZE	(1024 * 1024 * 1024)
+
+#define CONFIG_SYS_FPGA_BASE		0xe2000000	/* epld			*/
+#define CONFIG_SYS_OPER_FLASH		0xe7000000	/* SRAM - OPER Flash	*/
+
+/* #define CONFIG_SYS_NVRAM_BASE_ADDR 0x08000000 */
+/*-----------------------------------------------------------------------
+ * Initial RAM & stack pointer (placed in internal SRAM)
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_TEMP_STACK_OCM	1
+#define CONFIG_SYS_OCM_DATA_ADDR	CONFIG_SYS_ISRAM_BASE
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_ISRAM_BASE	/* Initial RAM address	*/
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000		/* Size of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+
+#undef CONFIG_SYS_EXT_SERIAL_CLOCK
+/* #define CONFIG_SYS_EXT_SERIAL_CLOCK	(1843200 * 6) */ /* Ext clk @ 11.059 MHz */
+
+/*-----------------------------------------------------------------------
+ * DDR SDRAM
+ *----------------------------------------------------------------------*/
+#define CONFIG_SPD_EEPROM	1	/* Use SPD EEPROM for setup	*/
+#define SPD_EEPROM_ADDRESS	{0x53, 0x52}	/* SPD i2c spd addresses*/
+#define CONFIG_DDR_ECC		1	/* with ECC support		*/
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
+
+#define IIC0_BOOTPROM_ADDR	0x50
+#define IIC0_ALT_BOOTPROM_ADDR	0x54
+
+/* Don't probe these addrs */
+#define CONFIG_SYS_I2C_NOPROBES	{ {0, 0x50}, {0, 0x52}, {0, 0x53}, {0, 0x54} }
+
+/* #if defined(CONFIG_CMD_EEPROM) */
+/* #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50 */	/* I2C boot EEPROM		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2	/* Bytes of address		*/
+/* #endif */
+
+/*-----------------------------------------------------------------------
+ * Environment
+ *----------------------------------------------------------------------*/
+/* #define CONFIG_SYS_NVRAM_SIZE	(0x2000 - 8) */	/* NVRAM size(8k)- RTC regs */
+
+#undef  CONFIG_ENV_IS_IN_NVRAM		/* ... not in NVRAM		*/
+#define	CONFIG_ENV_IS_IN_FLASH	1	/* Environment uses flash	*/
+#undef	CONFIG_ENV_IS_IN_EEPROM		/* ... not in EEPROM		*/
+#define CONFIG_ENV_OVERWRITE	1
+
+/*
+ * Default environment variables
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_AMCC_DEF_ENV						\
+	CONFIG_AMCC_DEF_ENV_PPC						\
+	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
+	"kernel_addr=E7F10000\0"					\
+	"ramdisk_addr=E7F20000\0"					\
+	"pciconfighost=1\0"						\
+	"pcie_mode=RP:EP:EP\0"						\
+	""
+
+/*
+ * Commands additional to the ones defined in amcc-common.h
+ */
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_SDRAM
+
+#define	CONFIG_IBM_EMAC4_V4	1
+#define CONFIG_PHY_ADDR		1	/* PHY address, See schematics	*/
+#define CONFIG_HAS_ETH0
+#define CONFIG_PHY_RESET        1	/* reset phy upon startup	*/
+#define CONFIG_PHY_RESET_DELAY	1000
+#define CONFIG_CIS8201_PHY	1	/* Enable 'special' RGMII mode for Cicada phy */
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+
+/*-----------------------------------------------------------------------
+ * FLASH related
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	3	/* number of banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* sectors per device		*/
+
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
+
+#define CONFIG_SYS_FLASH_ADDR0		0x5555
+#define CONFIG_SYS_FLASH_ADDR1		0x2aaa
+#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned char
+
+#define CONFIG_SYS_FLASH_2ND_16BIT_DEV	1	/* evb440SPe has 8 and 16bit device */
+#define CONFIG_SYS_FLASH_2ND_ADDR	0xe7c00000 /* evb440SPe has 8 and 16bit device*/
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	0x10000	/* size of one complete sector	*/
+#define CONFIG_ENV_ADDR		0xfffa0000
+/* #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) */
+#define CONFIG_ENV_SIZE		0x10000	/* Size of Environment vars	*/
+#endif /* CONFIG_ENV_IS_IN_FLASH */
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+/* General PCI */
+#define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
+#define CONFIG_PCI_PNP		1	/* do pci plug-and-play		*/
+#define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup	*/
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE
+
+/* Board-specific PCI */
+#define CONFIG_SYS_PCI_TARGET_INIT		/* let board init pci target    */
+#undef	CONFIG_SYS_PCI_MASTER_INIT
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014	/* IBM				*/
+#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever			*/
+/* #define CONFIG_SYS_PCI_SUBSYS_ID	CONFIG_SYS_PCI_SUBSYS_DEVICEID */
+
+/*
+ *  NETWORK Support (PCI):
+ */
+/* Support for Intel 82557/82559/82559ER chips. */
+#define CONFIG_EEPRO100
+
+/* FB Divisor selection */
+#define FPGA_FB_DIV_6		6
+#define FPGA_FB_DIV_10		10
+#define FPGA_FB_DIV_12		12
+#define FPGA_FB_DIV_20		20
+
+/* VCO Divisor selection */
+#define	FPGA_VCO_DIV_4		4
+#define	FPGA_VCO_DIV_6		6
+#define	FPGA_VCO_DIV_8		8
+#define	FPGA_VCO_DIV_10		10
+
+/*----------------------------------------------------------------------------+
+| FPGA registers and bit definitions
++----------------------------------------------------------------------------*/
+/* PowerPC 440SPe Board FPGA is reached with physical address 0x1 E2000000. */
+/* TLB initialization makes it correspond to logical address 0xE2000000. */
+/* => Done init_chip.s in bootlib */
+#define FPGA_REG_BASE_ADDR	0xE2000000
+#define FPGA_GPIO_BASE_ADDR	0xE2010000
+#define FPGA_INT_BASE_ADDR	0xE2020000
+
+/*----------------------------------------------------------------------------+
+| Display
++----------------------------------------------------------------------------*/
+#define PPC440SPE_DISPLAY	FPGA_REG_BASE_ADDR
+
+#define PPC440SPE_DISPLAY_D8	(FPGA_REG_BASE_ADDR+0x06)
+#define PPC440SPE_DISPLAY_D4	(FPGA_REG_BASE_ADDR+0x04)
+#define PPC440SPE_DISPLAY_D2	(FPGA_REG_BASE_ADDR+0x02)
+#define PPC440SPE_DISPLAY_D1	(FPGA_REG_BASE_ADDR+0x00)
+/*define   WRITE_DISPLAY_DIGIT(n) IOREG8(FPGA_REG_BASE_ADDR + (2*n))*/
+/*#define   IOREG8(addr) *((volatile unsigned char *)(addr))*/
+
+/*----------------------------------------------------------------------------+
+| ethernet/reset/boot Register 1
++----------------------------------------------------------------------------*/
+#define FPGA_REG10	(FPGA_REG_BASE_ADDR+0x10)
+
+#define FPGA_REG10_10MHZ_ENABLE		0x8000
+#define FPGA_REG10_100MHZ_ENABLE	0x4000
+#define FPGA_REG10_GIGABIT_ENABLE	0x2000
+#define FPGA_REG10_FULL_DUPLEX		0x1000	/* force Full Duplex*/
+#define FPGA_REG10_RESET_ETH		0x0800
+#define FPGA_REG10_AUTO_NEG_DIS		0x0400
+#define FPGA_REG10_INTP_ETH		0x0200
+
+#define FPGA_REG10_RESET_HISR		0x0080
+#define FPGA_REG10_ENABLE_DISPLAY	0x0040
+#define FPGA_REG10_RESET_SDRAM		0x0020
+#define FPGA_REG10_OPER_BOOT		0x0010
+#define FPGA_REG10_SRAM_BOOT		0x0008
+#define FPGA_REG10_SMALL_BOOT		0x0004
+#define FPGA_REG10_FORCE_COLA		0x0002
+#define FPGA_REG10_COLA_MANUAL		0x0001
+
+#define FPGA_REG10_SDRAM_ENABLE		0x0020
+
+#define FPGA_REG10_ENET_ENCODE2(n) ((((unsigned long)(n))&0x0F)<<4) /*from ocotea ?*/
+#define FPGA_REG10_ENET_DECODE2(n) ((((unsigned long)(n))>>4)&0x0F) /*from ocotea ?*/
+
+/*----------------------------------------------------------------------------+
+| MUX control
++----------------------------------------------------------------------------*/
+#define FPGA_REG12	(FPGA_REG_BASE_ADDR+0x12)
+
+#define FPGA_REG12_EBC_CTL		0x8000
+#define FPGA_REG12_UART1_CTS_RTS	0x4000
+#define FPGA_REG12_UART0_RX_ENABLE	0x2000
+#define FPGA_REG12_UART1_RX_ENABLE	0x1000
+#define FPGA_REG12_UART2_RX_ENABLE	0x0800
+#define FPGA_REG12_EBC_OUT_ENABLE	0x0400
+#define FPGA_REG12_GPIO0_OUT_ENABLE	0x0200
+#define FPGA_REG12_GPIO1_OUT_ENABLE	0x0100
+#define FPGA_REG12_GPIO_SELECT		0x0010
+#define FPGA_REG12_GPIO_CHREG		0x0008
+#define FPGA_REG12_GPIO_CLK_CHREG	0x0004
+#define FPGA_REG12_GPIO_OETRI		0x0002
+#define FPGA_REG12_EBC_ERROR		0x0001
+
+/*----------------------------------------------------------------------------+
+| PCI Clock control
++----------------------------------------------------------------------------*/
+#define FPGA_REG16	(FPGA_REG_BASE_ADDR+0x16)
+
+#define FPGA_REG16_PCI_CLK_CTL0		0x8000
+#define FPGA_REG16_PCI_CLK_CTL1		0x4000
+#define FPGA_REG16_PCI_CLK_CTL2		0x2000
+#define FPGA_REG16_PCI_CLK_CTL3		0x1000
+#define FPGA_REG16_PCI_CLK_CTL4		0x0800
+#define FPGA_REG16_PCI_CLK_CTL5		0x0400
+#define FPGA_REG16_PCI_CLK_CTL6		0x0200
+#define FPGA_REG16_PCI_CLK_CTL7		0x0100
+#define FPGA_REG16_PCI_CLK_CTL8		0x0080
+#define FPGA_REG16_PCI_CLK_CTL9		0x0040
+#define FPGA_REG16_PCI_EXT_ARB0		0x0020
+#define FPGA_REG16_PCI_MODE_1		0x0010
+#define FPGA_REG16_PCI_TARGET_MODE	0x0008
+#define FPGA_REG16_PCI_INTP_MODE	0x0004
+
+/* FB1 Divisor selection */
+#define FPGA_REG16_FB2_DIV_MASK		0x1000
+#define FPGA_REG16_FB2_DIV_LOW		0x0000
+#define FPGA_REG16_FB2_DIV_HIGH		0x1000
+/* FB2 Divisor selection */
+/* S3 switch on Board */
+#define FPGA_REG16_FB1_DIV_MASK		0x2000
+#define FPGA_REG16_FB1_DIV_LOW		0x0000
+#define FPGA_REG16_FB1_DIV_HIGH		0x2000
+/* PCI0 Clock Selection */
+/* S3 switch on Board */
+#define FPGA_REG16_PCI0_CLK_MASK	0x0c00
+#define FPGA_REG16_PCI0_CLK_33_33	0x0000
+#define FPGA_REG16_PCI0_CLK_66_66	0x0800
+#define FPGA_REG16_PCI0_CLK_100		0x0400
+#define FPGA_REG16_PCI0_CLK_133_33	0x0c00
+/* VCO Divisor selection */
+/* S3 switch on Board */
+#define FPGA_REG16_VCO_DIV_MASK		0xc000
+#define FPGA_REG16_VCO_DIV_4		0x0000
+#define FPGA_REG16_VCO_DIV_8		0x4000
+#define FPGA_REG16_VCO_DIV_6		0x8000
+#define FPGA_REG16_VCO_DIV_10		0xc000
+/* Master Clock Selection */
+/* S3, S4 switches on Board */
+#define FPGA_REG16_MASTER_CLK_MASK	0x01c0
+#define FPGA_REG16_MASTER_CLK_EXT	0x0000
+#define FPGA_REG16_MASTER_CLK_66_66	0x0040
+#define FPGA_REG16_MASTER_CLK_50	0x0080
+#define FPGA_REG16_MASTER_CLK_33_33	0x00c0
+#define FPGA_REG16_MASTER_CLK_25	0x0100
+
+/*----------------------------------------------------------------------------+
+| PCI Miscellaneous
++----------------------------------------------------------------------------*/
+#define FPGA_REG18	(FPGA_REG_BASE_ADDR+0x18)
+
+#define FPGA_REG18_PCI_PRSNT1		0x8000
+#define FPGA_REG18_PCI_PRSNT2		0x4000
+#define FPGA_REG18_PCI_INTA		0x2000
+#define FPGA_REG18_PCI_SLOT0_INTP	0x1000
+#define FPGA_REG18_PCI_SLOT1_INTP	0x0800
+#define FPGA_REG18_PCI_SLOT2_INTP	0x0400
+#define FPGA_REG18_PCI_SLOT3_INTP	0x0200
+#define FPGA_REG18_PCI_PCI0_VC		0x0100
+#define FPGA_REG18_PCI_PCI0_VTH1	0x0080
+#define FPGA_REG18_PCI_PCI0_VTH2	0x0040
+#define FPGA_REG18_PCI_PCI0_VTH3	0x0020
+
+/*----------------------------------------------------------------------------+
+| PCIe Miscellaneous
++----------------------------------------------------------------------------*/
+#define FPGA_REG1A	(FPGA_REG_BASE_ADDR+0x1A)
+
+#define FPGA_REG1A_PE0_GLED		0x8000
+#define FPGA_REG1A_PE1_GLED		0x4000
+#define FPGA_REG1A_PE2_GLED		0x2000
+#define FPGA_REG1A_PE0_YLED		0x1000
+#define FPGA_REG1A_PE1_YLED		0x0800
+#define FPGA_REG1A_PE2_YLED		0x0400
+#define FPGA_REG1A_PE0_PWRON		0x0200
+#define FPGA_REG1A_PE1_PWRON		0x0100
+#define FPGA_REG1A_PE2_PWRON		0x0080
+#define FPGA_REG1A_PE0_REFCLK_ENABLE	0x0040
+#define FPGA_REG1A_PE1_REFCLK_ENABLE	0x0020
+#define FPGA_REG1A_PE2_REFCLK_ENABLE	0x0010
+#define FPGA_REG1A_PE_SPREAD0		0x0008
+#define FPGA_REG1A_PE_SPREAD1		0x0004
+#define FPGA_REG1A_PE_SELSOURCE_0	0x0002
+#define FPGA_REG1A_PE_SELSOURCE_1	0x0001
+
+#define FPGA_REG1A_GLED_ENCODE(n)	(FPGA_REG1A_PE0_GLED >> (n))
+#define FPGA_REG1A_YLED_ENCODE(n)	(FPGA_REG1A_PE0_YLED >> (n))
+#define FPGA_REG1A_PWRON_ENCODE(n)	(FPGA_REG1A_PE0_PWRON >> (n))
+#define FPGA_REG1A_REFCLK_ENCODE(n)	(FPGA_REG1A_PE0_REFCLK_ENABLE >> (n))
+
+/*----------------------------------------------------------------------------+
+| PCIe Miscellaneous
++----------------------------------------------------------------------------*/
+#define FPGA_REG1C	(FPGA_REG_BASE_ADDR+0x1C)
+
+#define FPGA_REG1C_PE0_ROOTPOINT	0x8000
+#define FPGA_REG1C_PE1_ENDPOINT		0x4000
+#define FPGA_REG1C_PE2_ENDPOINT		0x2000
+#define FPGA_REG1C_PE0_PRSNT		0x1000
+#define FPGA_REG1C_PE1_PRSNT		0x0800
+#define FPGA_REG1C_PE2_PRSNT		0x0400
+#define FPGA_REG1C_PE0_WAKE		0x0080
+#define FPGA_REG1C_PE1_WAKE		0x0040
+#define FPGA_REG1C_PE2_WAKE		0x0020
+#define FPGA_REG1C_PE0_PERST		0x0010
+#define FPGA_REG1C_PE1_PERST		0x0008
+#define FPGA_REG1C_PE2_PERST		0x0004
+
+#define FPGA_REG1C_ROOTPOINT_ENCODE(n)	(FPGA_REG1C_PE0_ROOTPOINT >> (n))
+#define FPGA_REG1C_PERST_ENCODE(n)	(FPGA_REG1C_PE0_PERST >> (n))
+
+/*----------------------------------------------------------------------------+
+| Defines
++----------------------------------------------------------------------------*/
+#define PERIOD_133_33MHZ	7500	/* 7,5ns */
+#define PERIOD_100_00MHZ	10000	/* 10ns */
+#define PERIOD_83_33MHZ		12000	/* 12ns */
+#define PERIOD_75_00MHZ		13333	/* 13,333ns */
+#define PERIOD_66_66MHZ		15000	/* 15ns */
+#define PERIOD_50_00MHZ		20000	/* 20ns */
+#define PERIOD_33_33MHZ		30000	/* 30ns */
+#define PERIOD_25_00MHZ		40000	/* 40ns */
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/zeus.h b/qemu/roms/u-boot/include/configs/zeus.h
new file mode 100644
index 000000000..4d7a7fc75
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/zeus.h
@@ -0,0 +1,356 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/************************************************************************
+ * zeus.h - configuration for Zeus board
+ ***********************************************************************/
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*-----------------------------------------------------------------------
+ * High Level Configuration Options
+ *----------------------------------------------------------------------*/
+#define CONFIG_ZEUS		1		/* Board is Zeus	*/
+#define CONFIG_405EP		1		/* Specifc 405EP support*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
+
+#define CONFIG_SYS_CLK_FREQ     33000000 /* external frequency to pll   */
+
+#define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_early_init_f */
+#define CONFIG_MISC_INIT_R	1		/* Call misc_init_r	*/
+
+#define PLLMR0_DEFAULT		PLLMR0_333_111_55_111
+#define PLLMR1_DEFAULT		PLLMR1_333_111_55_111
+
+#define CONFIG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
+
+#define CONFIG_OVERWRITE_ETHADDR_ONCE	1
+
+#define CONFIG_PPC4xx_EMAC
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_PHY_ADDR		0x01	/* PHY address			*/
+#define CONFIG_HAS_ETH1		1
+#define CONFIG_PHY1_ADDR	0x11	/* EMAC1 PHY address		*/
+#define CONFIG_SYS_RX_ETH_BUFFER	16	/* Number of ethernet rx buffers & descriptors */
+#define CONFIG_PHY_RESET	1
+#define CONFIG_PHY_RESET_DELAY	300	/* PHY RESET recovery delay	*/
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+
+/* POST support */
+#define CONFIG_POST		(CONFIG_SYS_POST_MEMORY   | \
+				 CONFIG_SYS_POST_CPU	   | \
+				 CONFIG_SYS_POST_CACHE	   | \
+				 CONFIG_SYS_POST_UART	   | \
+				 CONFIG_SYS_POST_ETHER)
+
+#define CONFIG_SYS_POST_ETHER_EXT_LOOPBACK	/* eth POST using ext loopack connector	*/
+
+/* Define here the base-addresses of the UARTs to test in POST */
+#define CONFIG_SYS_POST_UART_TABLE	{ CONFIG_SYS_NS16550_COM1 }
+
+#define CONFIG_LOGBUFFER
+#define CONFIG_SYS_POST_CACHE_ADDR	0x00800000 /* free virtual address	*/
+
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+/*-----------------------------------------------------------------------
+ * SDRAM
+ *----------------------------------------------------------------------*/
+/*
+ * SDRAM configuration (please see cpu/ppc/sdram.[ch])
+ */
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0 */
+#define CONFIG_SDRAM_BANK1	1	/* init onboard SDRAM bank 1 */
+
+/* SDRAM timings used in datasheet */
+#define CONFIG_SYS_SDRAM_CL            3	/* CAS latency */
+#define CONFIG_SYS_SDRAM_tRP           20	/* PRECHARGE command period */
+#define CONFIG_SYS_SDRAM_tRC           66	/* ACTIVE-to-ACTIVE command period */
+#define CONFIG_SYS_SDRAM_tRCD          20	/* ACTIVE-to-READ delay */
+#define CONFIG_SYS_SDRAM_tRFC		66	/* Auto refresh period */
+
+/*-----------------------------------------------------------------------
+ * Serial Port
+ *----------------------------------------------------------------------*/
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+#undef	CONFIG_SYS_EXT_SERIAL_CLOCK			/* external serial clock */
+#define CONFIG_SYS_BASE_BAUD	691200
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+    {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+
+/*-----------------------------------------------------------------------
+ * Miscellaneous configurable options
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	        1024	/* Console I/O Buffer Size	*/
+#else
+#define CONFIG_SYS_CBSIZE	        256	/* Console I/O Buffer Size	*/
+#endif
+#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	        16	/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	        CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size	*/
+
+#define CONFIG_SYS_MEMTEST_START	0x0400000 /* memtest works on		*/
+#define CONFIG_SYS_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000  /* default load address	*/
+#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+#define CONFIG_LOOPW            1       /* enable loopw command         */
+#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
+
+/*-----------------------------------------------------------------------
+ * I2C
+ *----------------------------------------------------------------------*/
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
+
+/* these are for the ST M24C02 2kbit serial i2c eeprom */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50		/* base address */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1		/* bytes of address */
+/* mask of address bits that overflow into the "EEPROM chip address"    */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
+
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3	/* 8 byte write page size */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+
+/*
+ * The layout of the I2C EEPROM, used for bootstrap setup and for board-
+ * specific values, like ethaddr... that can be restored via the sw-reset
+ * button
+ */
+#define FACTORY_RESET_I2C_EEPROM	0x50
+#define FACTORY_RESET_ENV_OFFS		0x80
+#define FACTORY_RESET_ENV_SIZE		0x80
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xFF000000
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
+#define CONFIG_SYS_MONITOR_BASE	(-CONFIG_SYS_MONITOR_LEN)
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CONFIG_SYS_FLASH_CFI				/* The flash is CFI compatible	*/
+#define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/
+
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* use hardware flash protection	*/
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash	*/
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector		*/
+#define CONFIG_ENV_ADDR		((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
+#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+#endif
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory (OCM) for temperary stack until sdram is tested */
+#define CONFIG_SYS_TEMP_STACK_OCM	1
+
+/* On Chip Memory location */
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of OCM		*/
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+/* reserve some memory for POST and BOOT limit info */
+#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 16)
+
+/* extra data in OCM */
+#define CONFIG_SYS_POST_MAGIC		\
+		(CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_GBL_DATA_OFFSET - 8)
+#define CONFIG_SYS_POST_VAL		\
+		(CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_GBL_DATA_OFFSET - 12)
+
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash 16M) initialization					*/
+#define CONFIG_SYS_EBC_PB0AP		0x05815600
+#define CONFIG_SYS_EBC_PB0CR		0xFF09A000  /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit  */
+
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO setup (PPC405EP specific)
+ *
+ * GPIO0[0]     - External Bus Controller BLAST output
+ * GPIO0[1-9]   - Instruction trace outputs
+ * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
+ * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
+ * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
+ * GPIO0[24-27] - UART0 control signal inputs/outputs
+ * GPIO0[28-29] - UART1 data signal input/output
+ * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
+ */
+#define CONFIG_SYS_GPIO0_OSRL		0x15555550	/* Chip selects */
+#define CONFIG_SYS_GPIO0_OSRH		0x00000110	/* UART_DTR-pin 27 alt out */
+#define CONFIG_SYS_GPIO0_ISR1L		0x10000041	/* Pin 2, 12 is input */
+#define CONFIG_SYS_GPIO0_ISR1H		0x15505440	/* OUT: LEDs 22/23; IN: pin12,2, NVALID# */
+#define CONFIG_SYS_GPIO0_TSRL		0x00000000
+#define CONFIG_SYS_GPIO0_TSRH		0x00000000
+#define CONFIG_SYS_GPIO0_TCR		0xBFF68317	/* 3-state OUT: 22/23/29; 12,2 is not 3-state */
+#define CONFIG_SYS_GPIO0_ODR		0x00000000
+
+#define CONFIG_SYS_GPIO_SW_RESET	1
+#define CONFIG_SYS_GPIO_ZEUS_PE	12
+#define CONFIG_SYS_GPIO_LED_RED	22
+#define CONFIG_SYS_GPIO_LED_GREEN	23
+
+/* Time in milli-seconds */
+#define CONFIG_SYS_TIME_POST		5000
+#define CONFIG_SYS_TIME_FACTORY_RESET	10000
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
+#endif
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+
+/* ENVIRONMENT VARS */
+
+#define CONFIG_PREBOOT		"echo;echo Welcome to Bulletendpoints board v1.1;echo"
+#define CONFIG_IPADDR		192.168.1.10
+#define CONFIG_SERVERIP		192.168.1.100
+#define CONFIG_GATEWAYIP	192.168.1.100
+#define CONFIG_ETHADDR		50:00:00:00:06:00
+#define CONFIG_ETH1ADDR		50:00:00:00:06:01
+#if 0
+#define CONFIG_BOOTDELAY	-1	/* autoboot disabled        */
+#else
+#define CONFIG_BOOTDELAY	3	/* autoboot after 5 seconds */
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"logversion=2\0"                                                \
+	"hostname=zeus\0"						\
+	"netdev=eth0\0"							\
+	"ethact=ppc_4xx_eth0\0"						\
+	"netmask=255.255.255.0\0"					\
+	"ramdisk_size=50000\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw"			\
+		" nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw"			\
+		" ramdisk_size=${ramdisk_size}\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,"		\
+		"${baudrate}\0"						\
+	"net_nfs=tftp ${kernel_mem_addr} ${file_kernel};"		\
+		"run nfsargs addip addtty;bootm\0"			\
+	"net_ram=tftp ${kernel_mem_addr} ${file_kernel};"		\
+		"tftp ${ramdisk_mem_addr} ${file_fs};"			\
+		"run ramargs addip addtty;"				\
+		"bootm ${kernel_mem_addr} ${ramdisk_mem_addr}\0"	\
+	"rootpath=/target_fs/zeus\0"					\
+	"kernel_fl_addr=ff000000\0"					\
+	"kernel_mem_addr=200000\0"					\
+	"ramdisk_fl_addr=ff300000\0"					\
+	"ramdisk_mem_addr=4000000\0"					\
+	"uboot_fl_addr=fffc0000\0"					\
+	"uboot_mem_addr=100000\0"					\
+	"file_uboot=/zeus/u-boot.bin\0"					\
+	"tftp_uboot=tftp 100000 ${file_uboot}\0"			\
+	"update_uboot=protect off fffc0000 ffffffff;"			\
+		"era fffc0000 ffffffff;cp.b 100000 fffc0000 40000;"	\
+		"protect on fffc0000 ffffffff\0"			\
+	"upd_uboot=run tftp_uboot;run update_uboot\0"			\
+	"file_kernel=/zeus/uImage_ba\0"					\
+	"tftp_kernel=tftp 100000 ${file_kernel}\0"			\
+	"update_kernel=protect off ff000000 ff17ffff;"			\
+		"era ff000000 ff17ffff;cp.b 100000 ff000000 180000\0"	\
+	"upd_kernel=run tftp_kernel;run update_kernel\0"		\
+	"file_fs=/zeus/rootfs_ba.img\0"					\
+	"tftp_fs=tftp 100000 ${file_fs}\0"				\
+	"update_fs=protect off ff300000 ff87ffff;era ff300000 ff87ffff;"\
+		"cp.b 100000 ff300000 580000\0"				\
+	"upd_fs=run tftp_fs;run update_fs\0"				\
+	"bootcmd=chkreset;run ramargs addip addtty addmisc;"		\
+		"bootm ${kernel_fl_addr} ${ramdisk_fl_addr}\0"		\
+	""
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/zipitz2.h b/qemu/roms/u-boot/include/configs/zipitz2.h
new file mode 100644
index 000000000..41a7c99ed
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/zipitz2.h
@@ -0,0 +1,248 @@
+/*
+ * Aeronix Zipit Z2 configuration file
+ *
+ * Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Board Configuration Options
+ */
+#define	CONFIG_CPU_PXA27X		1	/* Marvell PXA270 CPU */
+#define	CONFIG_ZIPITZ2		1	/* Zipit Z2 board */
+#define	CONFIG_SYS_TEXT_BASE	0x0
+
+#undef	CONFIG_BOARD_LATE_INIT
+#undef	CONFIG_SKIP_LOWLEVEL_INIT
+#define	CONFIG_PREBOOT
+
+/*
+ * Environment settings
+ */
+#define	CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_IS_IN_FLASH		1
+#define CONFIG_ENV_ADDR			0x40000
+#define CONFIG_ENV_SIZE			0x20000
+
+/* we will never enable dcache, because we have to setup MMU first */
+#define CONFIG_SYS_DCACHE_OFF
+
+#define	CONFIG_SYS_MALLOC_LEN		(128*1024)
+#define	CONFIG_ARCH_CPU_INIT
+
+#define	CONFIG_BOOTCOMMAND						\
+	"if mmc rescan && ext2load mmc 0 0xa0000000 boot/uboot.script ;"\
+	"then "								\
+		"source 0xa0000000; "					\
+	"else "								\
+		"bootm 0x60000; "					\
+	"fi; "
+#define	CONFIG_BOOTARGS							\
+	"console=tty0 console=ttyS2,115200 fbcon=rotate:3"
+#define	CONFIG_TIMESTAMP
+#define	CONFIG_BOOTDELAY		2	/* Autoboot delay */
+#define	CONFIG_CMDLINE_TAG
+#define	CONFIG_SETUP_MEMORY_TAGS
+#define	CONFIG_SYS_TEXT_BASE		0x0
+#define	CONFIG_LZMA			/* LZMA compression support */
+
+/*
+ * Serial Console Configuration
+ * STUART - the lower serial port on Colibri board
+ */
+#define	CONFIG_PXA_SERIAL
+#define	CONFIG_STUART			1
+#define CONFIG_CONS_INDEX		2
+#define	CONFIG_BAUDRATE			115200
+
+/*
+ * Bootloader Components Configuration
+ */
+#include <config_cmd_default.h>
+
+#undef	CONFIG_CMD_NET
+#undef	CONFIG_CMD_NFS
+#define	CONFIG_CMD_ENV
+#undef	CONFIG_CMD_IMLS
+#define	CONFIG_CMD_MMC
+#define	CONFIG_CMD_SPI
+
+/*
+ * MMC Card Configuration
+ */
+#ifdef	CONFIG_CMD_MMC
+#define	CONFIG_MMC
+#define	CONFIG_GENERIC_MMC
+#define	CONFIG_PXA_MMC_GENERIC
+#define	CONFIG_SYS_MMC_BASE		0xF0000000
+#define	CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define	CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * SPI and LCD
+ */
+#ifdef	CONFIG_CMD_SPI
+#define	CONFIG_SOFT_SPI
+#define	CONFIG_LCD
+#define	CONFIG_PXA_LCD
+#define	CONFIG_LMS283GF05
+#define	CONFIG_VIDEO_LOGO
+#define	CONFIG_CMD_BMP
+#define	CONFIG_SPLASH_SCREEN
+#define	CONFIG_SPLASH_SCREEN_ALIGN
+#define	CONFIG_VIDEO_BMP_GZIP
+#define	CONFIG_VIDEO_BMP_RLE8
+#define	CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(2 << 20)
+#undef	SPI_INIT
+
+#define	SPI_DELAY	udelay(10)
+#define	SPI_SDA(val)	zipitz2_spi_sda(val)
+#define	SPI_SCL(val)	zipitz2_spi_scl(val)
+#define	SPI_READ	zipitz2_spi_read()
+#ifndef	__ASSEMBLY__
+void zipitz2_spi_sda(int);
+void zipitz2_spi_scl(int);
+unsigned char zipitz2_spi_read(void);
+#endif
+#endif
+
+/*
+ * KGDB
+ */
+#ifdef	CONFIG_CMD_KGDB
+#define	CONFIG_KGDB_BAUDRATE		230400		/* speed to run kgdb serial port */
+#endif
+
+/*
+ * HUSH Shell Configuration
+ */
+#define	CONFIG_SYS_HUSH_PARSER		1
+
+#define	CONFIG_SYS_LONGHELP				/* undef to save memory	*/
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define	CONFIG_SYS_PROMPT		"$ "		/* Monitor Command Prompt */
+#endif
+#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size */
+#define	CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS		16		/* max number of command args */
+#define	CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define	CONFIG_SYS_DEVICE_NULLDEV	1
+
+/*
+ * Clock Configuration
+ */
+#undef	CONFIG_SYS_CLKS_IN_HZ
+#define CONFIG_SYS_CPUSPEED		0x190		/* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */
+
+/*
+ * SRAM Map
+ */
+#define	PHYS_SRAM			0x5c000000	/* SRAM Bank #1 */
+#define	PHYS_SRAM_SIZE			0x00040000	/* 256k */
+
+/*
+ * DRAM Map
+ */
+#define	CONFIG_NR_DRAM_BANKS		1		/* We have 1 bank of DRAM */
+#define	PHYS_SDRAM_1			0xa0000000	/* SDRAM Bank #1 */
+#define	PHYS_SDRAM_1_SIZE		0x02000000	/* 32 MB */
+
+#define	CONFIG_SYS_DRAM_BASE		0xa0000000	/* CS0 */
+#define	CONFIG_SYS_DRAM_SIZE		0x02000000	/* 32 MB DRAM */
+
+#define CONFIG_SYS_MEMTEST_START	0xa0400000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM */
+
+#define	CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_DRAM_BASE
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SRAM + 2048)
+
+/*
+ * NOR FLASH
+ */
+#define PHYS_FLASH_1			0x00000000	/* Flash Bank #1 */
+#define PHYS_FLASH_SIZE			0x00800000	/* 8 MB */
+#define PHYS_FLASH_SECT_SIZE		0x00010000	/* 64 KB sectors */
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER		1
+#define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
+
+#define CONFIG_SYS_MONITOR_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_MONITOR_LEN		PHYS_FLASH_SECT_SIZE
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	256
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	240000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	240000
+#define CONFIG_SYS_FLASH_LOCK_TOUT	240000
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	240000
+#define CONFIG_SYS_FLASH_PROTECTION
+
+/*
+ * GPIO settings
+ */
+#define CONFIG_SYS_GAFR0_L_VAL	0x02000140
+#define CONFIG_SYS_GAFR0_U_VAL	0x59188000
+#define CONFIG_SYS_GAFR1_L_VAL	0x63900002
+#define CONFIG_SYS_GAFR1_U_VAL	0xaaa03950
+#define CONFIG_SYS_GAFR2_L_VAL	0x0aaaaaaa
+#define CONFIG_SYS_GAFR2_U_VAL	0x29000308
+#define CONFIG_SYS_GAFR3_L_VAL	0x54000000
+#define CONFIG_SYS_GAFR3_U_VAL	0x000000d5
+#define CONFIG_SYS_GPCR0_VAL	0x00000000
+#define CONFIG_SYS_GPCR1_VAL	0x00000020
+#define CONFIG_SYS_GPCR2_VAL	0x00000000
+#define CONFIG_SYS_GPCR3_VAL	0x00000000
+#define CONFIG_SYS_GPDR0_VAL	0xdafcee00
+#define CONFIG_SYS_GPDR1_VAL	0xffa3aaab
+#define CONFIG_SYS_GPDR2_VAL	0x8fe9ffff
+#define CONFIG_SYS_GPDR3_VAL	0x001b1f8a
+#define CONFIG_SYS_GPSR0_VAL	0x06080400
+#define CONFIG_SYS_GPSR1_VAL	0x007f0000
+#define CONFIG_SYS_GPSR2_VAL	0x032a0000
+#define CONFIG_SYS_GPSR3_VAL	0x00000180
+
+#define CONFIG_SYS_PSSR_VAL	0x30
+
+/*
+ * Clock settings
+ */
+#define CONFIG_SYS_CKEN		0x00511220
+#define CONFIG_SYS_CCCR		0x00000190
+
+/*
+ * Memory settings
+ */
+#define CONFIG_SYS_MSC0_VAL	0x2ffc38f8
+#define CONFIG_SYS_MSC1_VAL	0x0000ccd1
+#define CONFIG_SYS_MSC2_VAL	0x0000b884
+#define CONFIG_SYS_MDCNFG_VAL	0x08000ba9
+#define CONFIG_SYS_MDREFR_VAL	0x2011a01e
+#define CONFIG_SYS_MDMRS_VAL	0x00000000
+#define CONFIG_SYS_FLYCNFG_VAL	0x00010001
+#define CONFIG_SYS_SXCNFG_VAL	0x40044004
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+#define CONFIG_SYS_MECR_VAL	0x00000001
+#define CONFIG_SYS_MCMEM0_VAL	0x00014307
+#define CONFIG_SYS_MCMEM1_VAL	0x00014307
+#define CONFIG_SYS_MCATT0_VAL	0x0001c787
+#define CONFIG_SYS_MCATT1_VAL	0x0001c787
+#define CONFIG_SYS_MCIO0_VAL	0x0001430f
+#define CONFIG_SYS_MCIO1_VAL	0x0001430f
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/zmx25.h b/qemu/roms/u-boot/include/configs/zmx25.h
new file mode 100644
index 000000000..8ffe6f1e0
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/zmx25.h
@@ -0,0 +1,163 @@
+/*
+ * (c) 2011 Graf-Syteco, Matthias Weisser
+ * <weisserm@arcor.de>
+ *
+ * Configuation settings for the zmx25 board
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_ARM926EJS			/* arm926ejs CPU core */
+#define CONFIG_MX25
+#define CONFIG_SYS_TEXT_BASE		0xA0000000
+
+#define CONFIG_SYS_TIMER_RATE		32768
+#define CONFIG_SYS_TIMER_COUNTER	\
+	(&((struct gpt_regs *)IMX_GPT1_BASE)->counter)
+
+#define CONFIG_MACH_TYPE	MACH_TYPE_ZMX25
+/*
+ * Environment settings
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"gs_fast_boot=setenv bootdelay 5\0" \
+	"gs_slow_boot=setenv bootdelay 10\0" \
+	"bootcmd=dcache off; mw.l 0x81000000 0 1024; usb start;" \
+		"fatls usb 0; fatload usb 0 0x81000000 zmx25-init.bin;" \
+		"bootm 0x81000000; bootelf 0x81000000\0"
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_BOARD_LATE_INIT
+
+/*
+ * Compressions
+ */
+#define CONFIG_LZO
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * GPIO
+ */
+#define CONFIG_MXC_GPIO
+
+/*
+ * Serial
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE	UART2_BASE
+#define CONFIG_CONS_INDEX	1	/* use UART2 for console */
+#define CONFIG_BAUDRATE		115200	/* Default baud rate */
+
+/*
+ * Ethernet
+ */
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_MXC_PHYADDR		0x00
+#define CONFIG_MII
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_CACHE
+
+/*
+ * Additional command
+ */
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_USB
+
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * USB
+ */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI			/* Enable EHCI USB support */
+#define CONFIG_USB_EHCI_MXC
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORT	1
+#define CONFIG_MXC_USB_PORTSC	MXC_EHCI_MODE_SERIAL
+#define CONFIG_MXC_USB_FLAGS	(MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN)
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_STORAGE
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SUPPORT_VFAT
+#endif /* CONFIG_CMD_USB */
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM		0x80000000	/* start address of LPDDRRAM */
+#define PHYS_SDRAM_SIZE		0x04000000	/* 64 megs */
+
+#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM
+#define CONFIG_SYS_INIT_SP_ADDR	0x78020000	/* end of internal SRAM */
+
+/*
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_FLASH_BASE		0xA0000000
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	256
+
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x00040000)
+#define CONFIG_ENV_IS_IN_FLASH		1
+#define CONFIG_ENV_SECT_SIZE		(128 * 1024)
+#define CONFIG_ENV_SIZE			(128 * 1024)
+
+/*
+ * CFI FLASH driver setup
+ */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	/* ~10x faster */
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE
+
+#define CONFIG_SYS_MEMTEST_START	(PHYS_SDRAM + (512*1024))
+#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM + PHYS_SDRAM_SIZE)
+
+#define CONFIG_SYS_PROMPT	"zmx25> "
+#define CONFIG_SYS_CBSIZE	256
+#define CONFIG_SYS_MAXARGS	16
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
+				sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+
+#define CONFIG_PREBOOT  ""
+
+#define CONFIG_BOOTDELAY	5
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT "boot in %d s\n", bootdelay
+#define CONFIG_AUTOBOOT_DELAY_STR	"delaygs"
+#define CONFIG_AUTOBOOT_STOP_STR	"stopgs"
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(0x400000 - 0x8000)
+
+#endif	/* __CONFIG_H */
diff --git a/qemu/roms/u-boot/include/configs/zynq-common.h b/qemu/roms/u-boot/include/configs/zynq-common.h
new file mode 100644
index 000000000..731e69b5f
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/zynq-common.h
@@ -0,0 +1,309 @@
+/*
+ * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
+ * (C) Copyright 2013 Xilinx, Inc.
+ *
+ * Common configuration options for all Zynq boards.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQ_COMMON_H
+#define __CONFIG_ZYNQ_COMMON_H
+
+/* High Level configuration Options */
+#define CONFIG_ARMV7
+#define CONFIG_ZYNQ
+
+/* CPU clock */
+#ifndef CONFIG_CPU_FREQ_HZ
+# define CONFIG_CPU_FREQ_HZ	800000000
+#endif
+
+/* Cache options */
+#define CONFIG_CMD_CACHE
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
+#define CONFIG_SYS_L2CACHE_OFF
+#ifndef CONFIG_SYS_L2CACHE_OFF
+# define CONFIG_SYS_L2_PL310
+# define CONFIG_SYS_PL310_BASE		0xf8f02000
+#endif
+
+/* Serial drivers */
+#define CONFIG_BAUDRATE		115200
+/* The following table includes the supported baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
+
+/* DCC driver */
+#if defined(CONFIG_ZYNQ_DCC)
+# define CONFIG_ARM_DCC
+# define CONFIG_CPU_V6 /* Required by CONFIG_ARM_DCC */
+#else
+# define CONFIG_ZYNQ_SERIAL
+#endif
+
+/* Ethernet driver */
+#if defined(CONFIG_ZYNQ_GEM0) || defined(CONFIG_ZYNQ_GEM1)
+# define CONFIG_NET_MULTI
+# define CONFIG_ZYNQ_GEM
+# define CONFIG_MII
+# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+# define CONFIG_PHYLIB
+# define CONFIG_PHY_MARVELL
+#endif
+
+/* SPI */
+#ifdef CONFIG_ZYNQ_SPI
+# define CONFIG_SPI_FLASH
+# define CONFIG_SPI_FLASH_SST
+# define CONFIG_CMD_SF
+#endif
+
+/* NOR */
+#ifndef CONFIG_SYS_NO_FLASH
+# define CONFIG_SYS_FLASH_BASE		0xE2000000
+# define CONFIG_SYS_FLASH_SIZE		(16 * 1024 * 1024)
+# define CONFIG_SYS_MAX_FLASH_BANKS	1
+# define CONFIG_SYS_MAX_FLASH_SECT	512
+# define CONFIG_SYS_FLASH_ERASE_TOUT	1000
+# define CONFIG_SYS_FLASH_WRITE_TOUT	5000
+# define CONFIG_FLASH_SHOW_PROGRESS	10
+# define CONFIG_SYS_FLASH_CFI
+# undef CONFIG_SYS_FLASH_EMPTY_INFO
+# define CONFIG_FLASH_CFI_DRIVER
+# undef CONFIG_SYS_FLASH_PROTECTION
+# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#endif
+
+/* MMC */
+#if defined(CONFIG_ZYNQ_SDHCI0) || defined(CONFIG_ZYNQ_SDHCI1)
+# define CONFIG_MMC
+# define CONFIG_GENERIC_MMC
+# define CONFIG_SDHCI
+# define CONFIG_ZYNQ_SDHCI
+# define CONFIG_CMD_MMC
+# define CONFIG_CMD_FAT
+# define CONFIG_SUPPORT_VFAT
+# define CONFIG_CMD_EXT2
+# define CONFIG_DOS_PARTITION
+#endif
+
+#define CONFIG_SYS_I2C_ZYNQ
+/* I2C */
+#if defined(CONFIG_SYS_I2C_ZYNQ)
+# define CONFIG_CMD_I2C
+# define CONFIG_SYS_I2C
+# define CONFIG_SYS_I2C_ZYNQ_SPEED		100000
+# define CONFIG_SYS_I2C_ZYNQ_SLAVE		0
+#endif
+
+/* EEPROM */
+#ifdef CONFIG_ZYNQ_EEPROM
+# define CONFIG_CMD_EEPROM
+# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+# define CONFIG_SYS_I2C_EEPROM_ADDR		0x54
+# define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
+# define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
+# define CONFIG_SYS_EEPROM_SIZE			1024 /* Bytes */
+#endif
+
+#define CONFIG_BOOTP_SERVERIP
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_MAY_FAIL
+
+/* Total Size of Environment Sector */
+#define CONFIG_ENV_SIZE			(128 << 10)
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Environment */
+#ifndef CONFIG_ENV_IS_NOWHERE
+# ifndef CONFIG_SYS_NO_FLASH
+#  define CONFIG_ENV_IS_IN_FLASH
+# elif defined(CONFIG_SYS_NO_FLASH)
+#  define CONFIG_ENV_IS_NOWHERE
+# endif
+
+# define CONFIG_ENV_SECT_SIZE		CONFIG_ENV_SIZE
+# define CONFIG_ENV_OFFSET		0xE0000
+# define CONFIG_CMD_SAVEENV
+#endif
+
+/* Default environment */
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"fit_image=fit.itb\0"		\
+	"load_addr=0x2000000\0"		\
+	"fit_size=0x800000\0"		\
+	"flash_off=0x100000\0"		\
+	"nor_flash_off=0xE2100000\0"	\
+	"fdt_high=0x20000000\0"		\
+	"initrd_high=0x20000000\0"	\
+	"norboot=echo Copying FIT from NOR flash to RAM... && " \
+		"cp.b ${nor_flash_off} ${load_addr} ${fit_size} && " \
+		"bootm ${load_addr}\0" \
+	"sdboot=echo Copying FIT from SD to RAM... && " \
+		"fatload mmc 0 ${load_addr} ${fit_image} && " \
+		"bootm ${load_addr}\0" \
+	"jtagboot=echo TFTPing FIT to RAM... && " \
+		"tftpboot ${load_addr} ${fit_image} && " \
+		"bootm ${load_addr}\0"
+#define CONFIG_BOOTCOMMAND		"run $modeboot"
+#define CONFIG_BOOTDELAY		3 /* -1 to Disable autoboot */
+#define CONFIG_SYS_LOAD_ADDR		0 /* default? */
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_PROMPT		"zynq-uboot> "
+#define CONFIG_SYS_HUSH_PARSER
+
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CLOCKS
+#define CONFIG_CMD_CLK
+#define CONFIG_SYS_MAXARGS		15 /* max number of command args */
+#define CONFIG_SYS_CBSIZE		256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Physical Memory map */
+#define CONFIG_SYS_TEXT_BASE		0x4000000
+
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE		0
+
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x1000)
+
+#define CONFIG_SYS_MALLOC_LEN		0x400000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_MALLOC_LEN
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+
+/* Enable the PL to be downloaded */
+#define CONFIG_FPGA
+#define CONFIG_FPGA_XILINX
+#define CONFIG_FPGA_ZYNQPL
+#define CONFIG_CMD_FPGA
+
+/* Open Firmware flat tree */
+#define CONFIG_OF_LIBFDT
+
+/* FIT support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	1 /* enable fit_format_{error,warning}() */
+
+/* FDT support */
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+/* RSA support */
+#define CONFIG_FIT_SIGNATURE
+#define CONFIG_RSA
+
+/* Extend size of kernel image for uncompression */
+#define CONFIG_SYS_BOOTM_LEN	(20 * 1024 * 1024)
+
+/* Boot FreeBSD/vxWorks from an ELF image */
+#if defined(CONFIG_ZYNQ_BOOT_FREEBSD)
+# define CONFIG_API
+# define CONFIG_CMD_ELF
+# define CONFIG_SYS_MMC_MAX_DEVICE	1
+#endif
+
+#define CONFIG_SYS_LDSCRIPT  "arch/arm/cpu/armv7/zynq/u-boot.lds"
+
+/* Commands */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_TFTPPUT
+
+/* SPL part */
+#define CONFIG_SPL
+#define CONFIG_CMD_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+
+#define CONFIG_SPL_LDSCRIPT	"arch/arm/cpu/armv7/zynq/u-boot-spl.lds"
+
+/* Disable dcache for SPL just for sure */
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_DCACHE_OFF
+#undef CONFIG_FPGA
+#undef CONFIG_OF_CONTROL
+#endif
+
+/* MMC support */
+#ifdef CONFIG_ZYNQ_SDHCI0
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS      0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION    1
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME     "u-boot.img"
+#endif
+
+/* Address in RAM where the parameters must be copied by SPL. */
+#define CONFIG_SYS_SPL_ARGS_ADDR	0x10000000
+
+#define CONFIG_SPL_FAT_LOAD_ARGS_NAME		"system.dtb"
+#define CONFIG_SPL_FAT_LOAD_KERNEL_NAME		"uImage"
+
+/* Not using MMC raw mode - just for compilation purpose */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	0
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0
+
+/* qspi mode is working fine */
+#ifdef CONFIG_ZYNQ_QSPI
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_BUS	0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x100000
+#define CONFIG_SPL_SPI_CS	0
+#endif
+
+/* for booting directly linux */
+#define CONFIG_SPL_OS_BOOT
+
+/* SP location before relocation, must use scratch RAM */
+#define CONFIG_SPL_TEXT_BASE	0x0
+
+/* 3 * 64kB blocks of OCM - one is on the top because of bootrom */
+#define CONFIG_SPL_MAX_SIZE	0x30000
+
+/* The highest 64k OCM address */
+#define OCM_HIGH_ADDR	0xffff0000
+
+/* Just define any reasonable size */
+#define CONFIG_SPL_STACK_SIZE	0x1000
+
+/* SPL stack position - and stack goes down */
+#define CONFIG_SPL_STACK	(OCM_HIGH_ADDR + CONFIG_SPL_STACK_SIZE)
+
+/* On the top of OCM space */
+#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SPL_STACK + \
+					 GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x1000
+
+/* BSS setup */
+#define CONFIG_SPL_BSS_START_ADDR	0x100000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x100000
+
+#define CONFIG_SYS_UBOOT_START	CONFIG_SYS_TEXT_BASE
+
+#endif /* __CONFIG_ZYNQ_COMMON_H */
diff --git a/qemu/roms/u-boot/include/configs/zynq_microzed.h b/qemu/roms/u-boot/include/configs/zynq_microzed.h
new file mode 100644
index 000000000..b0328a2cc
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/zynq_microzed.h
@@ -0,0 +1,26 @@
+/*
+ * (C) Copyright 2013 Xilinx, Inc.
+ *
+ * Configuration for Micro Zynq Evaluation and Development Board - MicroZedBoard
+ * See zynq-common.h for Zynq common configs
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQ_MICROZED_H
+#define __CONFIG_ZYNQ_MICROZED_H
+
+#define CONFIG_SYS_SDRAM_SIZE		(1024 * 1024 * 1024)
+
+#define CONFIG_ZYNQ_SERIAL_UART1
+#define CONFIG_ZYNQ_GEM0
+#define CONFIG_ZYNQ_GEM_PHY_ADDR0	0
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ZYNQ_SDHCI0
+#define CONFIG_DEFAULT_DEVICE_TREE	zynq-microzed
+
+#include <configs/zynq-common.h>
+
+#endif /* __CONFIG_ZYNQ_MICROZED_H */
diff --git a/qemu/roms/u-boot/include/configs/zynq_zc70x.h b/qemu/roms/u-boot/include/configs/zynq_zc70x.h
new file mode 100644
index 000000000..de0e24129
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/zynq_zc70x.h
@@ -0,0 +1,29 @@
+/*
+ * (C) Copyright 2013 Xilinx, Inc.
+ *
+ * Configuration settings for the Xilinx Zynq ZC702 and ZC706 boards
+ * See zynq-common.h for Zynq common configs
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQ_ZC70X_H
+#define __CONFIG_ZYNQ_ZC70X_H
+
+#define CONFIG_SYS_SDRAM_SIZE		(1024 * 1024 * 1024)
+
+#define CONFIG_ZYNQ_SERIAL_UART1
+#define CONFIG_ZYNQ_GEM0
+#define CONFIG_ZYNQ_GEM_PHY_ADDR0	7
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ZYNQ_SDHCI0
+#define CONFIG_ZYNQ_I2C0
+#define CONFIG_ZYNQ_EEPROM
+#define CONFIG_ZYNQ_BOOT_FREEBSD
+#define CONFIG_DEFAULT_DEVICE_TREE	zynq-zc702
+
+#include <configs/zynq-common.h>
+
+#endif /* __CONFIG_ZYNQ_ZC70X_H */
diff --git a/qemu/roms/u-boot/include/configs/zynq_zc770.h b/qemu/roms/u-boot/include/configs/zynq_zc770.h
new file mode 100644
index 000000000..8aa96e712
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/zynq_zc770.h
@@ -0,0 +1,42 @@
+/*
+ * (C) Copyright 2013 Xilinx, Inc.
+ *
+ * Configuration settings for the Xilinx Zynq ZC770 board.
+ * See zynq-common.h for Zynq common configs
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQ_ZC770_H
+#define __CONFIG_ZYNQ_ZC770_H
+
+#define CONFIG_SYS_SDRAM_SIZE		(1024 * 1024 * 1024)
+
+#define CONFIG_SYS_NO_FLASH
+
+#if defined(CONFIG_ZC770_XM010)
+# define CONFIG_ZYNQ_SERIAL_UART1
+# define CONFIG_ZYNQ_GEM0
+# define CONFIG_ZYNQ_GEM_PHY_ADDR0	7
+# define CONFIG_ZYNQ_SDHCI0
+# define CONFIG_ZYNQ_SPI
+# define CONFIG_DEFAULT_DEVICE_TREE	zynq-zc770-xm010
+
+#elif defined(CONFIG_ZC770_XM012)
+# define CONFIG_ZYNQ_SERIAL_UART1
+# undef CONFIG_SYS_NO_FLASH
+# define CONFIG_DEFAULT_DEVICE_TREE	zynq-zc770-xm012
+
+#elif defined(CONFIG_ZC770_XM013)
+# define CONFIG_ZYNQ_SERIAL_UART0
+# define CONFIG_ZYNQ_GEM1
+# define CONFIG_ZYNQ_GEM_PHY_ADDR1	7
+# define CONFIG_DEFAULT_DEVICE_TREE	zynq-zc770-xm013
+
+#else
+# define CONFIG_ZYNQ_SERIAL_UART0
+#endif
+
+#include <configs/zynq-common.h>
+
+#endif /* __CONFIG_ZYNQ_ZC770_H */
diff --git a/qemu/roms/u-boot/include/configs/zynq_zed.h b/qemu/roms/u-boot/include/configs/zynq_zed.h
new file mode 100644
index 000000000..274140cb3
--- /dev/null
+++ b/qemu/roms/u-boot/include/configs/zynq_zed.h
@@ -0,0 +1,27 @@
+/*
+ * (C) Copyright 2013 Xilinx, Inc.
+ *
+ * Configuration for Zynq Evaluation and Development Board - ZedBoard
+ * See zynq-common.h for Zynq common configs
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQ_ZED_H
+#define __CONFIG_ZYNQ_ZED_H
+
+#define CONFIG_SYS_SDRAM_SIZE		(512 * 1024 * 1024)
+
+#define CONFIG_ZYNQ_SERIAL_UART1
+#define CONFIG_ZYNQ_GEM0
+#define CONFIG_ZYNQ_GEM_PHY_ADDR0	0
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ZYNQ_SDHCI0
+#define CONFIG_ZYNQ_BOOT_FREEBSD
+#define CONFIG_DEFAULT_DEVICE_TREE	zynq-zed
+
+#include <configs/zynq-common.h>
+
+#endif /* __CONFIG_ZYNQ_ZED_H */
diff --git a/qemu/roms/u-boot/include/cpsw.h b/qemu/roms/u-boot/include/cpsw.h
new file mode 100644
index 000000000..a73843d2f
--- /dev/null
+++ b/qemu/roms/u-boot/include/cpsw.h
@@ -0,0 +1,52 @@
+/*
+ * CPSW Ethernet Switch Driver
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _CPSW_H_
+#define _CPSW_H_
+
+struct cpsw_slave_data {
+	u32		slave_reg_ofs;
+	u32		sliver_reg_ofs;
+	int		phy_addr;
+	int		phy_if;
+};
+
+enum {
+	CPSW_CTRL_VERSION_1 = 0,
+	CPSW_CTRL_VERSION_2	/* am33xx like devices */
+};
+
+struct cpsw_platform_data {
+	u32	mdio_base;
+	u32	cpsw_base;
+	int	mdio_div;
+	int	channels;	/* number of cpdma channels (symmetric)	*/
+	u32	cpdma_reg_ofs;	/* cpdma register offset		*/
+	int	slaves;		/* number of slave cpgmac ports		*/
+	u32	ale_reg_ofs;	/* address lookup engine reg offset	*/
+	int	ale_entries;	/* ale table size			*/
+	u32	host_port_reg_ofs;	/* cpdma host port registers	*/
+	u32	hw_stats_reg_ofs;	/* cpsw hw stats counters	*/
+	u32	bd_ram_ofs;		/* Buffer Descriptor RAM offset */
+	u32	mac_control;
+	struct cpsw_slave_data	*slave_data;
+	void	(*control)(int enabled);
+	u32	host_port_num;
+	u8	version;
+};
+
+int cpsw_register(struct cpsw_platform_data *data);
+
+#endif /* _CPSW_H_  */
diff --git a/qemu/roms/u-boot/include/cramfs/cramfs_fs.h b/qemu/roms/u-boot/include/cramfs/cramfs_fs.h
new file mode 100644
index 000000000..e0c14f04a
--- /dev/null
+++ b/qemu/roms/u-boot/include/cramfs/cramfs_fs.h
@@ -0,0 +1,100 @@
+#ifndef __CRAMFS_H
+#define __CRAMFS_H
+
+#define CRAMFS_MAGIC		0x28cd3d45	/* some random number */
+#define CRAMFS_SIGNATURE	"Compressed ROMFS"
+
+/*
+ * Width of various bitfields in struct cramfs_inode.
+ * Primarily used to generate warnings in mkcramfs.
+ */
+#define CRAMFS_MODE_WIDTH	16
+#define CRAMFS_UID_WIDTH	16
+#define CRAMFS_SIZE_WIDTH	24
+#define CRAMFS_GID_WIDTH	8
+#define CRAMFS_NAMELEN_WIDTH	6
+#define CRAMFS_OFFSET_WIDTH	26
+
+/*
+ * Since inode.namelen is a unsigned 6-bit number, the maximum cramfs
+ * path length is 63 << 2 = 252.
+ */
+#define CRAMFS_MAXPATHLEN (((1 << CRAMFS_NAMELEN_WIDTH) - 1) << 2)
+
+/*
+ * Reasonably terse representation of the inode data.
+ */
+struct cramfs_inode {
+	u32 mode:CRAMFS_MODE_WIDTH, uid:CRAMFS_UID_WIDTH;
+
+	/* SIZE for device files is i_rdev */
+	u32 size:CRAMFS_SIZE_WIDTH, gid:CRAMFS_GID_WIDTH;
+
+	/* NAMELEN is the length of the file name, divided by 4 and
+	   rounded up.	(cramfs doesn't support hard links.) */
+	/* OFFSET: For symlinks and non-empty regular files, this
+	   contains the offset (divided by 4) of the file data in
+	   compressed form (starting with an array of block pointers;
+	   see README).	 For non-empty directories it is the offset
+	   (divided by 4) of the inode of the first file in that
+	   directory.  For anything else, offset is zero. */
+	u32 namelen:CRAMFS_NAMELEN_WIDTH, offset:CRAMFS_OFFSET_WIDTH;
+};
+
+struct cramfs_info {
+	u32 crc;
+	u32 edition;
+	u32 blocks;
+	u32 files;
+};
+
+/*
+ * Superblock information at the beginning of the FS.
+ */
+struct cramfs_super {
+	u32 magic;			/* 0x28cd3d45 - random number */
+	u32 size;			/* length in bytes */
+	u32 flags;			/* feature flags */
+	u32 future;			/* reserved for future use */
+	u8 signature[16];		/* "Compressed ROMFS" */
+	struct cramfs_info fsid;	/* unique filesystem info */
+	u8 name[16];			/* user-defined name */
+	struct cramfs_inode root;	/* root inode data */
+};
+
+/*
+ * Feature flags
+ *
+ * 0x00000000 - 0x000000ff: features that work for all past kernels
+ * 0x00000100 - 0xffffffff: features that don't work for past kernels
+ */
+#define CRAMFS_FLAG_FSID_VERSION_2	0x00000001	/* fsid version #2 */
+#define CRAMFS_FLAG_SORTED_DIRS		0x00000002	/* sorted dirs */
+#define CRAMFS_FLAG_HOLES		0x00000100	/* support for holes */
+#define CRAMFS_FLAG_WRONG_SIGNATURE	0x00000200	/* reserved */
+#define CRAMFS_FLAG_SHIFTED_ROOT_OFFSET 0x00000400	/* shifted root fs */
+
+/*
+ * Valid values in super.flags.	 Currently we refuse to mount
+ * if (flags & ~CRAMFS_SUPPORTED_FLAGS).  Maybe that should be
+ * changed to test super.future instead.
+ */
+#define CRAMFS_SUPPORTED_FLAGS	( 0x000000ff \
+				| CRAMFS_FLAG_HOLES \
+				| CRAMFS_FLAG_WRONG_SIGNATURE \
+				| CRAMFS_FLAG_SHIFTED_ROOT_OFFSET )
+
+#define CRAMFS_16(x)	(x)
+#define CRAMFS_24(x)	(x)
+#define CRAMFS_32(x)	(x)
+#define CRAMFS_GET_NAMELEN(x)	((x)->namelen)
+#define CRAMFS_GET_OFFSET(x)	((x)->offset)
+#define CRAMFS_SET_OFFSET(x,y)	((x)->offset = (y))
+#define CRAMFS_SET_NAMELEN(x,y) ((x)->namelen = (y))
+
+/* Uncompression interfaces to the underlying zlib */
+int cramfs_uncompress_block(void *dst, void *src, int srclen);
+int cramfs_uncompress_init(void);
+int cramfs_uncompress_exit(void);
+
+#endif	/* __CRAMFS_H */
diff --git a/qemu/roms/u-boot/include/crc.h b/qemu/roms/u-boot/include/crc.h
new file mode 100644
index 000000000..5085d4ed4
--- /dev/null
+++ b/qemu/roms/u-boot/include/crc.h
@@ -0,0 +1,69 @@
+/*
+ *==========================================================================
+ *
+ *      crc.h
+ *
+ *      Interface for the CRC algorithms.
+ *
+ *==========================================================================
+ * SPDX-License-Identifier:	eCos-2.0
+ *==========================================================================
+ *#####DESCRIPTIONBEGIN####
+ *
+ * Author(s):    Andrew Lunn
+ * Contributors: Andrew Lunn
+ * Date:         2002-08-06
+ * Purpose:
+ * Description:
+ *
+ * This code is part of eCos (tm).
+ *
+ *####DESCRIPTIONEND####
+ *
+ *==========================================================================
+ */
+
+#ifndef _SERVICES_CRC_CRC_H_
+#define _SERVICES_CRC_CRC_H_
+
+#include <linux/types.h>
+
+#ifndef __externC
+# ifdef __cplusplus
+#  define __externC extern "C"
+# else
+#  define __externC extern
+# endif
+#endif
+
+/* Compute a CRC, using the POSIX 1003 definition */
+extern uint32_t
+cyg_posix_crc32(unsigned char *s, int len);
+
+/* Gary S. Brown's 32 bit CRC */
+
+extern uint32_t
+cyg_crc32(unsigned char *s, int len);
+
+/* Gary S. Brown's 32 bit CRC, but accumulate the result from a */
+/* previous CRC calculation */
+
+extern uint32_t
+cyg_crc32_accumulate(uint32_t crc, unsigned char *s, int len);
+
+/* Ethernet FCS Algorithm */
+
+extern uint32_t
+cyg_ether_crc32(unsigned char *s, int len);
+
+/* Ethernet FCS algorithm, but accumulate the result from a previous */
+/* CRC calculation. */
+
+extern uint32_t
+cyg_ether_crc32_accumulate(uint32_t crc, unsigned char *s, int len);
+
+/* 16 bit CRC with polynomial x^16+x^12+x^5+1 */
+
+extern uint16_t cyg_crc16(unsigned char *s, int len);
+
+#endif /* _SERVICES_CRC_CRC_H_ */
diff --git a/qemu/roms/u-boot/include/cros_ec.h b/qemu/roms/u-boot/include/cros_ec.h
new file mode 100644
index 000000000..1e4d8db96
--- /dev/null
+++ b/qemu/roms/u-boot/include/cros_ec.h
@@ -0,0 +1,518 @@
+/*
+ * Chromium OS cros_ec driver
+ *
+ * Copyright (c) 2012 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CROS_EC_H
+#define _CROS_EC_H
+
+#include <linux/compiler.h>
+#include <ec_commands.h>
+#include <fdtdec.h>
+#include <cros_ec_message.h>
+
+/* Which interface is the device on? */
+enum cros_ec_interface_t {
+	CROS_EC_IF_NONE,
+	CROS_EC_IF_SPI,
+	CROS_EC_IF_I2C,
+	CROS_EC_IF_LPC,	/* Intel Low Pin Count interface */
+	CROS_EC_IF_SANDBOX,
+};
+
+/* Our configuration information */
+struct cros_ec_dev {
+	enum cros_ec_interface_t interface;
+	struct spi_slave *spi;		/* Our SPI slave, if using SPI */
+	int node;                       /* Our node */
+	int parent_node;		/* Our parent node (interface) */
+	unsigned int cs;		/* Our chip select */
+	unsigned int addr;		/* Device address (for I2C) */
+	unsigned int bus_num;		/* Bus number (for I2C) */
+	unsigned int max_frequency;	/* Maximum interface frequency */
+	struct fdt_gpio_state ec_int;	/* GPIO used as EC interrupt line */
+	int protocol_version;           /* Protocol version to use */
+	int optimise_flash_write;	/* Don't write erased flash blocks */
+
+	/*
+	 * These two buffers will always be dword-aligned and include enough
+	 * space for up to 7 word-alignment bytes also, so we can ensure that
+	 * the body of the message is always dword-aligned (64-bit).
+	 *
+	 * We use this alignment to keep ARM and x86 happy. Probably word
+	 * alignment would be OK, there might be a small performance advantage
+	 * to using dword.
+	 */
+	uint8_t din[ALIGN(MSG_BYTES + sizeof(int64_t), sizeof(int64_t))]
+		__aligned(sizeof(int64_t));
+	uint8_t dout[ALIGN(MSG_BYTES + sizeof(int64_t), sizeof(int64_t))]
+		__aligned(sizeof(int64_t));
+};
+
+/*
+ * Hard-code the number of columns we happen to know we have right now.  It
+ * would be more correct to call cros_ec_info() at startup and determine the
+ * actual number of keyboard cols from there.
+ */
+#define CROS_EC_KEYSCAN_COLS 13
+
+/* Information returned by a key scan */
+struct mbkp_keyscan {
+	uint8_t data[CROS_EC_KEYSCAN_COLS];
+};
+
+/* Holds information about the Chrome EC */
+struct fdt_cros_ec {
+	struct fmap_entry flash;	/* Address and size of EC flash */
+	/*
+	 * Byte value of erased flash, or -1 if not known. It is normally
+	 * 0xff but some flash devices use 0 (e.g. STM32Lxxx)
+	 */
+	int flash_erase_value;
+	struct fmap_entry region[EC_FLASH_REGION_COUNT];
+};
+
+/**
+ * Read the ID of the CROS-EC device
+ *
+ * The ID is a string identifying the CROS-EC device.
+ *
+ * @param dev		CROS-EC device
+ * @param id		Place to put the ID
+ * @param maxlen	Maximum length of the ID field
+ * @return 0 if ok, -1 on error
+ */
+int cros_ec_read_id(struct cros_ec_dev *dev, char *id, int maxlen);
+
+/**
+ * Read a keyboard scan from the CROS-EC device
+ *
+ * Send a message requesting a keyboard scan and return the result
+ *
+ * @param dev		CROS-EC device
+ * @param scan		Place to put the scan results
+ * @return 0 if ok, -1 on error
+ */
+int cros_ec_scan_keyboard(struct cros_ec_dev *dev, struct mbkp_keyscan *scan);
+
+/**
+ * Read which image is currently running on the CROS-EC device.
+ *
+ * @param dev		CROS-EC device
+ * @param image		Destination for image identifier
+ * @return 0 if ok, <0 on error
+ */
+int cros_ec_read_current_image(struct cros_ec_dev *dev,
+		enum ec_current_image *image);
+
+/**
+ * Read the hash of the CROS-EC device firmware.
+ *
+ * @param dev		CROS-EC device
+ * @param hash		Destination for hash information
+ * @return 0 if ok, <0 on error
+ */
+int cros_ec_read_hash(struct cros_ec_dev *dev,
+		struct ec_response_vboot_hash *hash);
+
+/**
+ * Send a reboot command to the CROS-EC device.
+ *
+ * Note that some reboot commands (such as EC_REBOOT_COLD) also reboot the AP.
+ *
+ * @param dev		CROS-EC device
+ * @param cmd		Reboot command
+ * @param flags         Flags for reboot command (EC_REBOOT_FLAG_*)
+ * @return 0 if ok, <0 on error
+ */
+int cros_ec_reboot(struct cros_ec_dev *dev, enum ec_reboot_cmd cmd,
+		uint8_t flags);
+
+/**
+ * Check if the CROS-EC device has an interrupt pending.
+ *
+ * Read the status of the external interrupt connected to the CROS-EC device.
+ * If no external interrupt is configured, this always returns 1.
+ *
+ * @param dev		CROS-EC device
+ * @return 0 if no interrupt is pending
+ */
+int cros_ec_interrupt_pending(struct cros_ec_dev *dev);
+
+enum {
+	CROS_EC_OK,
+	CROS_EC_ERR = 1,
+	CROS_EC_ERR_FDT_DECODE,
+	CROS_EC_ERR_CHECK_VERSION,
+	CROS_EC_ERR_READ_ID,
+	CROS_EC_ERR_DEV_INIT,
+};
+
+/**
+ * Initialise the Chromium OS EC driver
+ *
+ * @param blob		Device tree blob containing setup information
+ * @param cros_ecp        Returns pointer to the cros_ec device, or NULL if none
+ * @return 0 if we got an cros_ec device and all is well (or no cros_ec is
+ *	expected), -ve if we should have an cros_ec device but failed to find
+ *	one, or init failed (-CROS_EC_ERR_...).
+ */
+int cros_ec_init(const void *blob, struct cros_ec_dev **cros_ecp);
+
+/**
+ * Read information about the keyboard matrix
+ *
+ * @param dev		CROS-EC device
+ * @param info		Place to put the info structure
+ */
+int cros_ec_info(struct cros_ec_dev *dev,
+		struct ec_response_mkbp_info *info);
+
+/**
+ * Read the host event flags
+ *
+ * @param dev		CROS-EC device
+ * @param events_ptr	Destination for event flags.  Not changed on error.
+ * @return 0 if ok, <0 on error
+ */
+int cros_ec_get_host_events(struct cros_ec_dev *dev, uint32_t *events_ptr);
+
+/**
+ * Clear the specified host event flags
+ *
+ * @param dev		CROS-EC device
+ * @param events	Event flags to clear
+ * @return 0 if ok, <0 on error
+ */
+int cros_ec_clear_host_events(struct cros_ec_dev *dev, uint32_t events);
+
+/**
+ * Get/set flash protection
+ *
+ * @param dev		CROS-EC device
+ * @param set_mask	Mask of flags to set; if 0, just retrieves existing
+ *                      protection state without changing it.
+ * @param set_flags	New flag values; only bits in set_mask are applied;
+ *                      ignored if set_mask=0.
+ * @param prot          Destination for updated protection state from EC.
+ * @return 0 if ok, <0 on error
+ */
+int cros_ec_flash_protect(struct cros_ec_dev *dev,
+		       uint32_t set_mask, uint32_t set_flags,
+		       struct ec_response_flash_protect *resp);
+
+
+/**
+ * Run internal tests on the cros_ec interface.
+ *
+ * @param dev		CROS-EC device
+ * @return 0 if ok, <0 if the test failed
+ */
+int cros_ec_test(struct cros_ec_dev *dev);
+
+/**
+ * Update the EC RW copy.
+ *
+ * @param dev		CROS-EC device
+ * @param image		the content to write
+ * @param imafge_size	content length
+ * @return 0 if ok, <0 if the test failed
+ */
+int cros_ec_flash_update_rw(struct cros_ec_dev *dev,
+			 const uint8_t  *image, int image_size);
+
+/**
+ * Return a pointer to the board's CROS-EC device
+ *
+ * This should be implemented by board files.
+ *
+ * @return pointer to CROS-EC device, or NULL if none is available
+ */
+struct cros_ec_dev *board_get_cros_ec_dev(void);
+
+
+/* Internal interfaces */
+int cros_ec_i2c_init(struct cros_ec_dev *dev, const void *blob);
+int cros_ec_spi_init(struct cros_ec_dev *dev, const void *blob);
+int cros_ec_lpc_init(struct cros_ec_dev *dev, const void *blob);
+int cros_ec_sandbox_init(struct cros_ec_dev *dev, const void *blob);
+
+/**
+ * Read information from the fdt for the i2c cros_ec interface
+ *
+ * @param dev		CROS-EC device
+ * @param blob		Device tree blob
+ * @return 0 if ok, -1 if we failed to read all required information
+ */
+int cros_ec_i2c_decode_fdt(struct cros_ec_dev *dev, const void *blob);
+
+/**
+ * Read information from the fdt for the spi cros_ec interface
+ *
+ * @param dev		CROS-EC device
+ * @param blob		Device tree blob
+ * @return 0 if ok, -1 if we failed to read all required information
+ */
+int cros_ec_spi_decode_fdt(struct cros_ec_dev *dev, const void *blob);
+
+/**
+ * Read information from the fdt for the sandbox cros_ec interface
+ *
+ * @param dev		CROS-EC device
+ * @param blob		Device tree blob
+ * @return 0 if ok, -1 if we failed to read all required information
+ */
+int cros_ec_sandbox_decode_fdt(struct cros_ec_dev *dev, const void *blob);
+
+/**
+ * Check whether the LPC interface supports new-style commands.
+ *
+ * LPC has its own way of doing this, which involves checking LPC values
+ * visible to the host. Do this, and update dev->protocol_version accordingly.
+ *
+ * @param dev		CROS-EC device to check
+ */
+int cros_ec_lpc_check_version(struct cros_ec_dev *dev);
+
+/**
+ * Send a command to an I2C CROS-EC device and return the reply.
+ *
+ * This rather complicated function deals with sending both old-style and
+ * new-style commands. The old ones have just a command byte and arguments.
+ * The new ones have version, command, arg-len, [args], chksum so are 3 bytes
+ * longer.
+ *
+ * The device's internal input/output buffers are used.
+ *
+ * @param dev		CROS-EC device
+ * @param cmd		Command to send (EC_CMD_...)
+ * @param cmd_version	Version of command to send (EC_VER_...)
+ * @param dout          Output data (may be NULL If dout_len=0)
+ * @param dout_len      Size of output data in bytes
+ * @param dinp          Returns pointer to response data
+ * @param din_len       Maximum size of response in bytes
+ * @return number of bytes in response, or -1 on error
+ */
+int cros_ec_i2c_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version,
+		     const uint8_t *dout, int dout_len,
+		     uint8_t **dinp, int din_len);
+
+/**
+ * Send a command to a LPC CROS-EC device and return the reply.
+ *
+ * The device's internal input/output buffers are used.
+ *
+ * @param dev		CROS-EC device
+ * @param cmd		Command to send (EC_CMD_...)
+ * @param cmd_version	Version of command to send (EC_VER_...)
+ * @param dout          Output data (may be NULL If dout_len=0)
+ * @param dout_len      Size of output data in bytes
+ * @param dinp          Returns pointer to response data
+ * @param din_len       Maximum size of response in bytes
+ * @return number of bytes in response, or -1 on error
+ */
+int cros_ec_lpc_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version,
+		     const uint8_t *dout, int dout_len,
+		     uint8_t **dinp, int din_len);
+
+int cros_ec_spi_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version,
+		     const uint8_t *dout, int dout_len,
+		     uint8_t **dinp, int din_len);
+
+/**
+ * Send a packet to a CROS-EC device and return the response packet.
+ *
+ * Expects the request packet to be stored in dev->dout.  Stores the response
+ * packet in dev->din.
+ *
+ * @param dev		CROS-EC device
+ * @param out_bytes	Size of request packet to output
+ * @param in_bytes	Maximum size of response packet to receive
+ * @return number of bytes in response packet, or <0 on error
+ */
+int cros_ec_spi_packet(struct cros_ec_dev *dev, int out_bytes, int in_bytes);
+int cros_ec_sandbox_packet(struct cros_ec_dev *dev, int out_bytes,
+			   int in_bytes);
+
+/**
+ * Dump a block of data for a command.
+ *
+ * @param name	Name for data (e.g. 'in', 'out')
+ * @param cmd	Command number associated with data, or -1 for none
+ * @param data	Data block to dump
+ * @param len	Length of data block to dump
+ */
+void cros_ec_dump_data(const char *name, int cmd, const uint8_t *data, int len);
+
+/**
+ * Calculate a simple 8-bit checksum of a data block
+ *
+ * @param data	Data block to checksum
+ * @param size	Size of data block in bytes
+ * @return checksum value (0 to 255)
+ */
+int cros_ec_calc_checksum(const uint8_t *data, int size);
+
+/**
+ * Decode a flash region parameter
+ *
+ * @param argc	Number of params remaining
+ * @param argv	List of remaining parameters
+ * @return flash region (EC_FLASH_REGION_...) or -1 on error
+ */
+int cros_ec_decode_region(int argc, char * const argv[]);
+
+int cros_ec_flash_erase(struct cros_ec_dev *dev, uint32_t offset,
+		uint32_t size);
+
+/**
+ * Read data from the flash
+ *
+ * Read an arbitrary amount of data from the EC flash, by repeatedly reading
+ * small blocks.
+ *
+ * The offset starts at 0. You can obtain the region information from
+ * cros_ec_flash_offset() to find out where to read for a particular region.
+ *
+ * @param dev		CROS-EC device
+ * @param data		Pointer to data buffer to read into
+ * @param offset	Offset within flash to read from
+ * @param size		Number of bytes to read
+ * @return 0 if ok, -1 on error
+ */
+int cros_ec_flash_read(struct cros_ec_dev *dev, uint8_t *data, uint32_t offset,
+		    uint32_t size);
+
+/**
+ * Write data to the flash
+ *
+ * Write an arbitrary amount of data to the EC flash, by repeatedly writing
+ * small blocks.
+ *
+ * The offset starts at 0. You can obtain the region information from
+ * cros_ec_flash_offset() to find out where to write for a particular region.
+ *
+ * Attempting to write to the region where the EC is currently running from
+ * will result in an error.
+ *
+ * @param dev		CROS-EC device
+ * @param data		Pointer to data buffer to write
+ * @param offset	Offset within flash to write to.
+ * @param size		Number of bytes to write
+ * @return 0 if ok, -1 on error
+ */
+int cros_ec_flash_write(struct cros_ec_dev *dev, const uint8_t *data,
+		     uint32_t offset, uint32_t size);
+
+/**
+ * Obtain position and size of a flash region
+ *
+ * @param dev		CROS-EC device
+ * @param region	Flash region to query
+ * @param offset	Returns offset of flash region in EC flash
+ * @param size		Returns size of flash region
+ * @return 0 if ok, -1 on error
+ */
+int cros_ec_flash_offset(struct cros_ec_dev *dev, enum ec_flash_region region,
+		      uint32_t *offset, uint32_t *size);
+
+/**
+ * Read/write VbNvContext from/to a CROS-EC device.
+ *
+ * @param dev		CROS-EC device
+ * @param block		Buffer of VbNvContext to be read/write
+ * @return 0 if ok, -1 on error
+ */
+int cros_ec_read_vbnvcontext(struct cros_ec_dev *dev, uint8_t *block);
+int cros_ec_write_vbnvcontext(struct cros_ec_dev *dev, const uint8_t *block);
+
+/**
+ * Read the version information for the EC images
+ *
+ * @param dev		CROS-EC device
+ * @param versionp	This is set to point to the version information
+ * @return 0 if ok, -1 on error
+ */
+int cros_ec_read_version(struct cros_ec_dev *dev,
+		       struct ec_response_get_version **versionp);
+
+/**
+ * Read the build information for the EC
+ *
+ * @param dev		CROS-EC device
+ * @param versionp	This is set to point to the build string
+ * @return 0 if ok, -1 on error
+ */
+int cros_ec_read_build_info(struct cros_ec_dev *dev, char **strp);
+
+/**
+ * Switch on/off a LDO / FET.
+ *
+ * @param dev		CROS-EC device
+ * @param index		index of the LDO/FET to switch
+ * @param state		new state of the LDO/FET : EC_LDO_STATE_ON|OFF
+ * @return 0 if ok, -1 on error
+ */
+int cros_ec_set_ldo(struct cros_ec_dev *dev, uint8_t index, uint8_t state);
+
+/**
+ * Read back a LDO / FET current state.
+ *
+ * @param dev		CROS-EC device
+ * @param index		index of the LDO/FET to switch
+ * @param state		current state of the LDO/FET : EC_LDO_STATE_ON|OFF
+ * @return 0 if ok, -1 on error
+ */
+int cros_ec_get_ldo(struct cros_ec_dev *dev, uint8_t index, uint8_t *state);
+
+/**
+ * Initialize the Chrome OS EC at board initialization time.
+ *
+ * @return 0 if ok, -ve on error
+ */
+int cros_ec_board_init(void);
+
+/**
+ * Get access to the error reported when cros_ec_board_init() was called
+ *
+ * This permits delayed reporting of the EC error if it failed during
+ * early init.
+ *
+ * @return error (0 if there was no error, -ve if there was an error)
+ */
+int cros_ec_get_error(void);
+
+/**
+ * Returns information from the FDT about the Chrome EC flash
+ *
+ * @param blob		FDT blob to use
+ * @param config	Structure to use to return information
+ */
+int cros_ec_decode_ec_flash(const void *blob, struct fdt_cros_ec *config);
+
+/**
+ * Check the current keyboard state, in case recovery mode is requested.
+ * This function is for sandbox only.
+ *
+ * @param ec		CROS-EC device
+ */
+void cros_ec_check_keyboard(struct cros_ec_dev *dev);
+
+/*
+ * Tunnel an I2C transfer to the EC
+ *
+ * @param dev		CROS-EC device
+ * @param chip		Chip address (7-bit I2C address)
+ * @param addr		Register address to read/write
+ * @param alen		Length of register address in bytes
+ * @param buffer	Buffer containing data to read/write
+ * @param len		Length of buffer
+ * @param is_read	1 if this is a read, 0 if this is a write
+ */
+int cros_ec_i2c_xfer(struct cros_ec_dev *dev, uchar chip, uint addr,
+		     int alen, uchar *buffer, int len, int is_read);
+
+#endif
diff --git a/qemu/roms/u-boot/include/cros_ec_message.h b/qemu/roms/u-boot/include/cros_ec_message.h
new file mode 100644
index 000000000..36e2d83ce
--- /dev/null
+++ b/qemu/roms/u-boot/include/cros_ec_message.h
@@ -0,0 +1,29 @@
+/*
+ * Chromium OS Matrix Keyboard Message Protocol definitions
+ *
+ * Copyright (c) 2012 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CROS_MESSAGE_H
+#define _CROS_MESSAGE_H
+
+/*
+ * Command interface between EC and AP, for LPC, I2C and SPI interfaces.
+ *
+ * This is copied from the Chromium OS Open Source Embedded Controller code.
+ */
+enum {
+	/* The header byte, which follows the preamble */
+	MSG_HEADER	= 0xec,
+
+	MSG_HEADER_BYTES	= 3,
+	MSG_TRAILER_BYTES	= 2,
+	MSG_PROTO_BYTES		= MSG_HEADER_BYTES + MSG_TRAILER_BYTES,
+
+	/* Max length of messages */
+	MSG_BYTES		= EC_PROTO2_MAX_PARAM_SIZE + MSG_PROTO_BYTES,
+};
+
+#endif
diff --git a/qemu/roms/u-boot/include/dataflash.h b/qemu/roms/u-boot/include/dataflash.h
new file mode 100644
index 000000000..142b55546
--- /dev/null
+++ b/qemu/roms/u-boot/include/dataflash.h
@@ -0,0 +1,205 @@
+/*
+ * (C) Copyright 2003
+ * Data Flash Atmel Description File
+ * Author : Hamid Ikdoumi (Atmel)
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* File Name		: dataflash.h					*/
+/* Object		: Data Flash Atmel Description File		*/
+/* Translator		:						*/
+/*									*/
+/* 1.0 03/04/01 HI	: Creation					*/
+/* 1.2 20/10/02 FB	: Adapatation Service and Lib v3		*/
+/*----------------------------------------------------------------------*/
+
+#ifndef _DataFlash_h
+#define _DataFlash_h
+
+
+#include "config.h"
+
+/*number of protected area*/
+#define NB_DATAFLASH_AREA		5
+
+#ifdef CONFIG_SYS_NO_FLASH
+
+/*-----------------------------------------------------------------------
+ * return codes from flash_write():
+ */
+# define ERR_OK				0
+# define ERR_TIMOUT			1
+# define ERR_NOT_ERASED			2
+# define ERR_PROTECTED			4
+# define ERR_INVAL			8
+# define ERR_ALIGN			16
+# define ERR_UNKNOWN_FLASH_VENDOR	32
+# define ERR_UNKNOWN_FLASH_TYPE		64
+# define ERR_PROG_ERROR			128
+
+/*-----------------------------------------------------------------------
+ * Protection Flags for flash_protect():
+ */
+# define FLAG_PROTECT_SET		0x01
+# define FLAG_PROTECT_CLEAR		0x02
+# define FLAG_PROTECT_INVALID		0x03
+
+/*-----------------------------------------------------------------------
+ * Set Environment according to label:
+ */
+# define	FLAG_SETENV		0x80
+#endif /* CONFIG_SYS_NO_FLASH */
+
+/*define the area structure*/
+typedef struct {
+	unsigned long start;
+	unsigned long end;
+	unsigned char protected;
+	unsigned char setenv;
+	unsigned char label[20];
+} dataflash_protect_t;
+
+typedef unsigned int AT91S_DataFlashStatus;
+
+/*----------------------------------------------------------------------*/
+/* DataFlash Structures							*/
+/*----------------------------------------------------------------------*/
+
+/*---------------------------------------------*/
+/* DataFlash Descriptor Structure Definition   */
+/*---------------------------------------------*/
+typedef struct _AT91S_DataflashDesc {
+	unsigned char *tx_cmd_pt;
+	unsigned int tx_cmd_size;
+	unsigned char *rx_cmd_pt;
+	unsigned int rx_cmd_size;
+	unsigned char *tx_data_pt;
+	unsigned int tx_data_size;
+	unsigned char *rx_data_pt;
+	unsigned int rx_data_size;
+	volatile unsigned char state;
+	volatile unsigned char DataFlash_state;
+	unsigned char command[8];
+} AT91S_DataflashDesc, *AT91PS_DataflashDesc;
+
+/*---------------------------------------------*/
+/* DataFlash device definition structure       */
+/*---------------------------------------------*/
+typedef struct _AT91S_Dataflash {
+	int pages_number;			/* dataflash page number */
+	int pages_size;				/* dataflash page size */
+	int page_offset;			/* page offset in command */
+	int byte_mask;				/* byte mask in command */
+	int cs;
+	dataflash_protect_t area_list[NB_DATAFLASH_AREA]; /* area protection status */
+} AT91S_DataflashFeatures, *AT91PS_DataflashFeatures;
+
+/*---------------------------------------------*/
+/* DataFlash Structure Definition	       */
+/*---------------------------------------------*/
+typedef struct _AT91S_DataFlash {
+	AT91PS_DataflashDesc pDataFlashDesc;	/* dataflash descriptor */
+	AT91PS_DataflashFeatures pDevice;	/* Pointer on a dataflash features array */
+} AT91S_DataFlash, *AT91PS_DataFlash;
+
+
+typedef struct _AT91S_DATAFLASH_INFO {
+
+	AT91S_DataflashDesc Desc;
+	AT91S_DataflashFeatures Device; /* Pointer on a dataflash features array */
+	unsigned long logical_address;
+	unsigned long end_address;
+	unsigned int id;			/* device id */
+} AT91S_DATAFLASH_INFO, *AT91PS_DATAFLASH_INFO;
+
+struct dataflash_addr {
+	unsigned long addr;
+	int cs;
+};
+/*-------------------------------------------------------------------------------------------------*/
+#define AT45DB161	0x2c
+#define AT45DB021	0x14
+#define AT45DB081	0x24
+#define AT45DB321	0x34
+#define AT45DB642	0x3c
+#define AT45DB128	0x10
+#define	PAGES_PER_BLOCK	8
+
+#define AT91C_DATAFLASH_TIMEOUT		10000	/* For AT91F_DataFlashWaitReady */
+
+/* DataFlash return value */
+#define DATAFLASH_BUSY			0x00
+#define DATAFLASH_OK			0x01
+#define DATAFLASH_ERROR			0x02
+#define DATAFLASH_MEMORY_OVERFLOW	0x03
+#define DATAFLASH_BAD_COMMAND		0x04
+#define DATAFLASH_BAD_ADDRESS		0x05
+
+
+/* Driver State */
+#define IDLE		0x0
+#define BUSY		0x1
+#define ERROR		0x2
+
+/* DataFlash Driver State */
+#define GET_STATUS	0x0F
+
+/*-------------------------------------------------------------------------------------------------*/
+/* Command Definition										   */
+/*-------------------------------------------------------------------------------------------------*/
+
+/* READ COMMANDS */
+#define DB_CONTINUOUS_ARRAY_READ	0xE8	/* Continuous array read */
+#define DB_BURST_ARRAY_READ		0xE8	/* Burst array read */
+#define DB_PAGE_READ			0xD2	/* Main memory page read */
+#define DB_BUF1_READ			0xD4	/* Buffer 1 read */
+#define DB_BUF2_READ			0xD6	/* Buffer 2 read */
+#define DB_STATUS			0xD7	/* Status Register */
+
+/* PROGRAM and ERASE COMMANDS */
+#define DB_BUF1_WRITE			0x84	/* Buffer 1 write */
+#define DB_BUF2_WRITE			0x87	/* Buffer 2 write */
+#define DB_BUF1_PAGE_ERASE_PGM		0x83	/* Buffer 1 to main memory page program with built-In erase */
+#define DB_BUF1_PAGE_ERASE_FASTPGM	0x93	/* Buffer 1 to main memory page program with built-In erase, Fast program */
+#define DB_BUF2_PAGE_ERASE_PGM		0x86	/* Buffer 2 to main memory page program with built-In erase */
+#define DB_BUF2_PAGE_ERASE_FASTPGM	0x96	/* Buffer 1 to main memory page program with built-In erase, Fast program */
+#define DB_BUF1_PAGE_PGM		0x88	/* Buffer 1 to main memory page program without built-In erase */
+#define DB_BUF1_PAGE_FASTPGM		0x98	/* Buffer 1 to main memory page program without built-In erase, Fast program */
+#define DB_BUF2_PAGE_PGM		0x89	/* Buffer 2 to main memory page program without built-In erase */
+#define DB_BUF2_PAGE_FASTPGM		0x99	/* Buffer 1 to main memory page program without built-In erase, Fast program */
+#define DB_PAGE_ERASE			0x81	/* Page Erase */
+#define DB_BLOCK_ERASE			0x50	/* Block Erase */
+#define DB_PAGE_PGM_BUF1		0x82	/* Main memory page through buffer 1 */
+#define DB_PAGE_FASTPGM_BUF1		0x92	/* Main memory page through buffer 1, Fast program */
+#define DB_PAGE_PGM_BUF2		0x85	/* Main memory page through buffer 2 */
+#define DB_PAGE_FastPGM_BUF2		0x95	/* Main memory page through buffer 2, Fast program */
+
+/* ADDITIONAL COMMANDS */
+#define DB_PAGE_2_BUF1_TRF		0x53	/* Main memory page to buffer 1 transfert */
+#define DB_PAGE_2_BUF2_TRF		0x55	/* Main memory page to buffer 2 transfert */
+#define DB_PAGE_2_BUF1_CMP		0x60	/* Main memory page to buffer 1 compare */
+#define DB_PAGE_2_BUF2_CMP		0x61	/* Main memory page to buffer 2 compare */
+#define DB_AUTO_PAGE_PGM_BUF1		0x58	/* Auto page rewrite throught buffer 1 */
+#define DB_AUTO_PAGE_PGM_BUF2		0x59	/* Auto page rewrite throught buffer 2 */
+
+/*-------------------------------------------------------------------------------------------------*/
+
+extern int size_dataflash (AT91PS_DataFlash pdataFlash, unsigned long addr, unsigned long size);
+extern int prot_dataflash (AT91PS_DataFlash pdataFlash, unsigned long addr);
+extern int addr2ram(ulong addr);
+extern int dataflash_real_protect (int flag, unsigned long start_addr, unsigned long end_addr);
+extern int addr_dataflash (unsigned long addr);
+extern int read_dataflash (unsigned long addr, unsigned long size, char *result);
+extern int write_dataflash(unsigned long addr_dest, unsigned long addr_src,
+			unsigned long size);
+extern int AT91F_DataflashInit(void);
+
+extern void dataflash_print_info (void);
+extern void dataflash_perror (int err);
+extern void AT91F_DataflashSetEnv (void);
+
+extern struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS];
+extern dataflash_protect_t area_list[NB_DATAFLASH_AREA];
+extern AT91S_DATAFLASH_INFO dataflash_info[];
+#endif
diff --git a/qemu/roms/u-boot/include/ddr_spd.h b/qemu/roms/u-boot/include/ddr_spd.h
new file mode 100644
index 000000000..cf2aac6ae
--- /dev/null
+++ b/qemu/roms/u-boot/include/ddr_spd.h
@@ -0,0 +1,565 @@
+/*
+ * Copyright 2008-2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#ifndef _DDR_SPD_H_
+#define _DDR_SPD_H_
+
+/*
+ * Format from "JEDEC Standard No. 21-C,
+ * Appendix D: Rev 1.0: SPD's for DDR SDRAM
+ */
+typedef struct ddr1_spd_eeprom_s {
+	unsigned char info_size;   /*  0 # bytes written into serial memory */
+	unsigned char chip_size;   /*  1 Total # bytes of SPD memory device */
+	unsigned char mem_type;    /*  2 Fundamental memory type */
+	unsigned char nrow_addr;   /*  3 # of Row Addresses on this assembly */
+	unsigned char ncol_addr;   /*  4 # of Column Addrs on this assembly */
+	unsigned char nrows;       /*  5 Number of DIMM Banks */
+	unsigned char dataw_lsb;   /*  6 Data Width of this assembly */
+	unsigned char dataw_msb;   /*  7 ... Data Width continuation */
+	unsigned char voltage;     /*  8 Voltage intf std of this assembly */
+	unsigned char clk_cycle;   /*  9 SDRAM Cycle time @ CL=X */
+	unsigned char clk_access;  /* 10 SDRAM Access from Clk @ CL=X (tAC) */
+	unsigned char config;      /* 11 DIMM Configuration type */
+	unsigned char refresh;     /* 12 Refresh Rate/Type */
+	unsigned char primw;       /* 13 Primary SDRAM Width */
+	unsigned char ecw;         /* 14 Error Checking SDRAM width */
+	unsigned char min_delay;   /* 15 for Back to Back Random Address */
+	unsigned char burstl;      /* 16 Burst Lengths Supported */
+	unsigned char nbanks;      /* 17 # of Banks on SDRAM Device */
+	unsigned char cas_lat;     /* 18 CAS# Latencies Supported */
+	unsigned char cs_lat;      /* 19 CS# Latency */
+	unsigned char write_lat;   /* 20 Write Latency (aka Write Recovery) */
+	unsigned char mod_attr;    /* 21 SDRAM Module Attributes */
+	unsigned char dev_attr;    /* 22 SDRAM Device Attributes */
+	unsigned char clk_cycle2;  /* 23 Min SDRAM Cycle time @ CL=X-0.5 */
+	unsigned char clk_access2; /* 24 SDRAM Access from
+					 Clk @ CL=X-0.5 (tAC) */
+	unsigned char clk_cycle3;  /* 25 Min SDRAM Cycle time @ CL=X-1 */
+	unsigned char clk_access3; /* 26 Max Access from Clk @ CL=X-1 (tAC) */
+	unsigned char trp;         /* 27 Min Row Precharge Time (tRP)*/
+	unsigned char trrd;        /* 28 Min Row Active to Row Active (tRRD) */
+	unsigned char trcd;        /* 29 Min RAS to CAS Delay (tRCD) */
+	unsigned char tras;        /* 30 Minimum RAS Pulse Width (tRAS) */
+	unsigned char bank_dens;   /* 31 Density of each bank on module */
+	unsigned char ca_setup;    /* 32 Addr + Cmd Setup Time Before Clk */
+	unsigned char ca_hold;     /* 33 Addr + Cmd Hold Time After Clk */
+	unsigned char data_setup;  /* 34 Data Input Setup Time Before Strobe */
+	unsigned char data_hold;   /* 35 Data Input Hold Time After Strobe */
+	unsigned char res_36_40[5];/* 36-40 reserved for VCSDRAM */
+	unsigned char trc;         /* 41 Min Active to Auto refresh time tRC */
+	unsigned char trfc;        /* 42 Min Auto to Active period tRFC */
+	unsigned char tckmax;      /* 43 Max device cycle time tCKmax */
+	unsigned char tdqsq;       /* 44 Max DQS to DQ skew (tDQSQ max) */
+	unsigned char tqhs;        /* 45 Max Read DataHold skew (tQHS) */
+	unsigned char res_46;      /* 46 Reserved */
+	unsigned char dimm_height; /* 47 DDR SDRAM DIMM Height */
+	unsigned char res_48_61[14]; /* 48-61 Reserved */
+	unsigned char spd_rev;     /* 62 SPD Data Revision Code */
+	unsigned char cksum;       /* 63 Checksum for bytes 0-62 */
+	unsigned char mid[8];      /* 64-71 Mfr's JEDEC ID code per JEP-106 */
+	unsigned char mloc;        /* 72 Manufacturing Location */
+	unsigned char mpart[18];   /* 73 Manufacturer's Part Number */
+	unsigned char rev[2];      /* 91 Revision Code */
+	unsigned char mdate[2];    /* 93 Manufacturing Date */
+	unsigned char sernum[4];   /* 95 Assembly Serial Number */
+	unsigned char mspec[27];   /* 99-127 Manufacturer Specific Data */
+
+} ddr1_spd_eeprom_t;
+
+/*
+ * Format from "JEDEC Appendix X: Serial Presence Detects for DDR2 SDRAM",
+ * SPD Revision 1.2
+ */
+typedef struct ddr2_spd_eeprom_s {
+	unsigned char info_size;   /*  0 # bytes written into serial memory */
+	unsigned char chip_size;   /*  1 Total # bytes of SPD memory device */
+	unsigned char mem_type;    /*  2 Fundamental memory type */
+	unsigned char nrow_addr;   /*  3 # of Row Addresses on this assembly */
+	unsigned char ncol_addr;   /*  4 # of Column Addrs on this assembly */
+	unsigned char mod_ranks;   /*  5 Number of DIMM Ranks */
+	unsigned char dataw;       /*  6 Module Data Width */
+	unsigned char res_7;       /*  7 Reserved */
+	unsigned char voltage;     /*  8 Voltage intf std of this assembly */
+	unsigned char clk_cycle;   /*  9 SDRAM Cycle time @ CL=X */
+	unsigned char clk_access;  /* 10 SDRAM Access from Clk @ CL=X (tAC) */
+	unsigned char config;      /* 11 DIMM Configuration type */
+	unsigned char refresh;     /* 12 Refresh Rate/Type */
+	unsigned char primw;       /* 13 Primary SDRAM Width */
+	unsigned char ecw;         /* 14 Error Checking SDRAM width */
+	unsigned char res_15;      /* 15 Reserved */
+	unsigned char burstl;      /* 16 Burst Lengths Supported */
+	unsigned char nbanks;      /* 17 # of Banks on Each SDRAM Device */
+	unsigned char cas_lat;     /* 18 CAS# Latencies Supported */
+	unsigned char mech_char;   /* 19 DIMM Mechanical Characteristics */
+	unsigned char dimm_type;   /* 20 DIMM type information */
+	unsigned char mod_attr;    /* 21 SDRAM Module Attributes */
+	unsigned char dev_attr;    /* 22 SDRAM Device Attributes */
+	unsigned char clk_cycle2;  /* 23 Min SDRAM Cycle time @ CL=X-1 */
+	unsigned char clk_access2; /* 24 SDRAM Access from Clk @ CL=X-1 (tAC) */
+	unsigned char clk_cycle3;  /* 25 Min SDRAM Cycle time @ CL=X-2 */
+	unsigned char clk_access3; /* 26 Max Access from Clk @ CL=X-2 (tAC) */
+	unsigned char trp;         /* 27 Min Row Precharge Time (tRP)*/
+	unsigned char trrd;        /* 28 Min Row Active to Row Active (tRRD) */
+	unsigned char trcd;        /* 29 Min RAS to CAS Delay (tRCD) */
+	unsigned char tras;        /* 30 Minimum RAS Pulse Width (tRAS) */
+	unsigned char rank_dens;   /* 31 Density of each rank on module */
+	unsigned char ca_setup;    /* 32 Addr+Cmd Setup Time Before Clk (tIS) */
+	unsigned char ca_hold;     /* 33 Addr+Cmd Hold Time After Clk (tIH) */
+	unsigned char data_setup;  /* 34 Data Input Setup Time
+					 Before Strobe (tDS) */
+	unsigned char data_hold;   /* 35 Data Input Hold Time
+					 After Strobe (tDH) */
+	unsigned char twr;         /* 36 Write Recovery time tWR */
+	unsigned char twtr;        /* 37 Int write to read delay tWTR */
+	unsigned char trtp;        /* 38 Int read to precharge delay tRTP */
+	unsigned char mem_probe;   /* 39 Mem analysis probe characteristics */
+	unsigned char trctrfc_ext; /* 40 Extensions to trc and trfc */
+	unsigned char trc;         /* 41 Min Active to Auto refresh time tRC */
+	unsigned char trfc;        /* 42 Min Auto to Active period tRFC */
+	unsigned char tckmax;      /* 43 Max device cycle time tCKmax */
+	unsigned char tdqsq;       /* 44 Max DQS to DQ skew (tDQSQ max) */
+	unsigned char tqhs;        /* 45 Max Read DataHold skew (tQHS) */
+	unsigned char pll_relock;  /* 46 PLL Relock time */
+	unsigned char t_casemax;    /* 47 Tcasemax */
+	unsigned char psi_ta_dram;  /* 48 Thermal Resistance of DRAM Package from
+					 Top (Case) to Ambient (Psi T-A DRAM) */
+	unsigned char dt0_mode;    /* 49 DRAM Case Temperature Rise from Ambient
+					 due to Activate-Precharge/Mode Bits
+					 (DT0/Mode Bits) */
+	unsigned char dt2n_dt2q;   /* 50 DRAM Case Temperature Rise from Ambient
+					 due to Precharge/Quiet Standby
+					 (DT2N/DT2Q) */
+	unsigned char dt2p;        /* 51 DRAM Case Temperature Rise from Ambient
+					 due to Precharge Power-Down (DT2P) */
+	unsigned char dt3n;        /* 52 DRAM Case Temperature Rise from Ambient
+					 due to Active Standby (DT3N) */
+	unsigned char dt3pfast;    /* 53 DRAM Case Temperature Rise from Ambient
+					 due to Active Power-Down with
+					 Fast PDN Exit (DT3Pfast) */
+	unsigned char dt3pslow;    /* 54 DRAM Case Temperature Rise from Ambient
+					 due to Active Power-Down with Slow
+					 PDN Exit (DT3Pslow) */
+	unsigned char dt4r_dt4r4w; /* 55 DRAM Case Temperature Rise from Ambient
+					 due to Page Open Burst Read/DT4R4W
+					 Mode Bit (DT4R/DT4R4W Mode Bit) */
+	unsigned char dt5b;        /* 56 DRAM Case Temperature Rise from Ambient
+					 due to Burst Refresh (DT5B) */
+	unsigned char dt7;         /* 57 DRAM Case Temperature Rise from Ambient
+					 due to Bank Interleave Reads with
+					 Auto-Precharge (DT7) */
+	unsigned char psi_ta_pll;  /* 58 Thermal Resistance of PLL Package form
+					 Top (Case) to Ambient (Psi T-A PLL) */
+	unsigned char psi_ta_reg;    /* 59 Thermal Reisitance of Register Package
+					 from Top (Case) to Ambient
+					 (Psi T-A Register) */
+	unsigned char dtpllactive; /* 60 PLL Case Temperature Rise from Ambient
+					 due to PLL Active (DT PLL Active) */
+	unsigned char dtregact;    /* 61 Register Case Temperature Rise from
+					 Ambient due to Register Active/Mode Bit
+					 (DT Register Active/Mode Bit) */
+	unsigned char spd_rev;     /* 62 SPD Data Revision Code */
+	unsigned char cksum;       /* 63 Checksum for bytes 0-62 */
+	unsigned char mid[8];      /* 64 Mfr's JEDEC ID code per JEP-106 */
+	unsigned char mloc;        /* 72 Manufacturing Location */
+	unsigned char mpart[18];   /* 73 Manufacturer's Part Number */
+	unsigned char rev[2];      /* 91 Revision Code */
+	unsigned char mdate[2];    /* 93 Manufacturing Date */
+	unsigned char sernum[4];   /* 95 Assembly Serial Number */
+	unsigned char mspec[27];   /* 99-127 Manufacturer Specific Data */
+
+} ddr2_spd_eeprom_t;
+
+typedef struct ddr3_spd_eeprom_s {
+	/* General Section: Bytes 0-59 */
+	unsigned char info_size_crc;   /*  0 # bytes written into serial memory,
+					     CRC coverage */
+	unsigned char spd_rev;         /*  1 Total # bytes of SPD mem device */
+	unsigned char mem_type;        /*  2 Key Byte / Fundamental mem type */
+	unsigned char module_type;     /*  3 Key Byte / Module Type */
+	unsigned char density_banks;   /*  4 SDRAM Density and Banks */
+	unsigned char addressing;      /*  5 SDRAM Addressing */
+	unsigned char module_vdd;      /*  6 Module nominal voltage, VDD */
+	unsigned char organization;    /*  7 Module Organization */
+	unsigned char bus_width;       /*  8 Module Memory Bus Width */
+	unsigned char ftb_div;         /*  9 Fine Timebase (FTB)
+					     Dividend / Divisor */
+	unsigned char mtb_dividend;    /* 10 Medium Timebase (MTB) Dividend */
+	unsigned char mtb_divisor;     /* 11 Medium Timebase (MTB) Divisor */
+	unsigned char tck_min;         /* 12 SDRAM Minimum Cycle Time */
+	unsigned char res_13;          /* 13 Reserved */
+	unsigned char caslat_lsb;      /* 14 CAS Latencies Supported,
+					     Least Significant Byte */
+	unsigned char caslat_msb;      /* 15 CAS Latencies Supported,
+					     Most Significant Byte */
+	unsigned char taa_min;         /* 16 Min CAS Latency Time */
+	unsigned char twr_min;         /* 17 Min Write REcovery Time */
+	unsigned char trcd_min;        /* 18 Min RAS# to CAS# Delay Time */
+	unsigned char trrd_min;        /* 19 Min Row Active to
+					     Row Active Delay Time */
+	unsigned char trp_min;         /* 20 Min Row Precharge Delay Time */
+	unsigned char tras_trc_ext;    /* 21 Upper Nibbles for tRAS and tRC */
+	unsigned char tras_min_lsb;    /* 22 Min Active to Precharge
+					     Delay Time */
+	unsigned char trc_min_lsb;     /* 23 Min Active to Active/Refresh
+					     Delay Time, LSB */
+	unsigned char trfc_min_lsb;    /* 24 Min Refresh Recovery Delay Time */
+	unsigned char trfc_min_msb;    /* 25 Min Refresh Recovery Delay Time */
+	unsigned char twtr_min;        /* 26 Min Internal Write to
+					     Read Command Delay Time */
+	unsigned char trtp_min;        /* 27 Min Internal Read to Precharge
+					     Command Delay Time */
+	unsigned char tfaw_msb;        /* 28 Upper Nibble for tFAW */
+	unsigned char tfaw_min;        /* 29 Min Four Activate Window
+					     Delay Time*/
+	unsigned char opt_features;    /* 30 SDRAM Optional Features */
+	unsigned char therm_ref_opt;   /* 31 SDRAM Thermal and Refresh Opts */
+	unsigned char therm_sensor;    /* 32 Module Thermal Sensor */
+	unsigned char device_type;     /* 33 SDRAM device type */
+	int8_t fine_tck_min;	       /* 34 Fine offset for tCKmin */
+	int8_t fine_taa_min;	       /* 35 Fine offset for tAAmin */
+	int8_t fine_trcd_min;	       /* 36 Fine offset for tRCDmin */
+	int8_t fine_trp_min;	       /* 37 Fine offset for tRPmin */
+	int8_t fine_trc_min;	       /* 38 Fine offset for tRCmin */
+	unsigned char res_39_59[21];   /* 39-59 Reserved, General Section */
+
+	/* Module-Specific Section: Bytes 60-116 */
+	union {
+		struct {
+			/* 60 (Unbuffered) Module Nominal Height */
+			unsigned char mod_height;
+			/* 61 (Unbuffered) Module Maximum Thickness */
+			unsigned char mod_thickness;
+			/* 62 (Unbuffered) Reference Raw Card Used */
+			unsigned char ref_raw_card;
+			/* 63 (Unbuffered) Address Mapping from
+			      Edge Connector to DRAM */
+			unsigned char addr_mapping;
+			/* 64-116 (Unbuffered) Reserved */
+			unsigned char res_64_116[53];
+		} unbuffered;
+		struct {
+			/* 60 (Registered) Module Nominal Height */
+			unsigned char mod_height;
+			/* 61 (Registered) Module Maximum Thickness */
+			unsigned char mod_thickness;
+			/* 62 (Registered) Reference Raw Card Used */
+			unsigned char ref_raw_card;
+			/* 63 DIMM Module Attributes */
+			unsigned char modu_attr;
+			/* 64 RDIMM Thermal Heat Spreader Solution */
+			unsigned char thermal;
+			/* 65 Register Manufacturer ID Code, Least Significant Byte */
+			unsigned char reg_id_lo;
+			/* 66 Register Manufacturer ID Code, Most Significant Byte */
+			unsigned char reg_id_hi;
+			/* 67 Register Revision Number */
+			unsigned char reg_rev;
+			/* 68 Register Type */
+			unsigned char reg_type;
+			/* 69-76 RC1,3,5...15 (MS Nibble) / RC0,2,4...14 (LS Nibble) */
+			unsigned char rcw[8];
+		} registered;
+		unsigned char uc[57]; /* 60-116 Module-Specific Section */
+	} mod_section;
+
+	/* Unique Module ID: Bytes 117-125 */
+	unsigned char mmid_lsb;        /* 117 Module MfgID Code LSB - JEP-106 */
+	unsigned char mmid_msb;        /* 118 Module MfgID Code MSB - JEP-106 */
+	unsigned char mloc;            /* 119 Mfg Location */
+	unsigned char mdate[2];        /* 120-121 Mfg Date */
+	unsigned char sernum[4];       /* 122-125 Module Serial Number */
+
+	/* CRC: Bytes 126-127 */
+	unsigned char crc[2];          /* 126-127 SPD CRC */
+
+	/* Other Manufacturer Fields and User Space: Bytes 128-255 */
+	unsigned char mpart[18];       /* 128-145 Mfg's Module Part Number */
+	unsigned char mrev[2];         /* 146-147 Module Revision Code */
+
+	unsigned char dmid_lsb;        /* 148 DRAM MfgID Code LSB - JEP-106 */
+	unsigned char dmid_msb;        /* 149 DRAM MfgID Code MSB - JEP-106 */
+
+	unsigned char msd[26];         /* 150-175 Mfg's Specific Data */
+	unsigned char cust[80];        /* 176-255 Open for Customer Use */
+
+} ddr3_spd_eeprom_t;
+
+/* From JEEC Standard No. 21-C release 23A */
+struct ddr4_spd_eeprom_s {
+	/* General Section: Bytes 0-127 */
+	uint8_t info_size_crc;		/*  0 # bytes */
+	uint8_t spd_rev;		/*  1 Total # bytes of SPD */
+	uint8_t mem_type;		/*  2 Key Byte / mem type */
+	uint8_t module_type;		/*  3 Key Byte / Module Type */
+	uint8_t density_banks;		/*  4 Density and Banks	*/
+	uint8_t addressing;		/*  5 Addressing */
+	uint8_t package_type;		/*  6 Package type */
+	uint8_t opt_feature;		/*  7 Optional features */
+	uint8_t thermal_ref;		/*  8 Thermal and refresh */
+	uint8_t oth_opt_features;	/*  9 Other optional features */
+	uint8_t res_10;			/* 10 Reserved */
+	uint8_t module_vdd;		/* 11 Module nominal voltage */
+	uint8_t organization;		/* 12 Module Organization */
+	uint8_t bus_width;		/* 13 Module Memory Bus Width */
+	uint8_t therm_sensor;		/* 14 Module Thermal Sensor */
+	uint8_t ext_type;		/* 15 Extended module type */
+	uint8_t res_16;
+	uint8_t timebases;		/* 17 MTb and FTB */
+	uint8_t tck_min;		/* 18 tCKAVGmin */
+	uint8_t tck_max;		/* 19 TCKAVGmax */
+	uint8_t caslat_b1;		/* 20 CAS latencies, 1st byte */
+	uint8_t caslat_b2;		/* 21 CAS latencies, 2nd byte */
+	uint8_t caslat_b3;		/* 22 CAS latencies, 3rd byte */
+	uint8_t caslat_b4;		/* 23 CAS latencies, 4th byte */
+	uint8_t taa_min;		/* 24 Min CAS Latency Time */
+	uint8_t trcd_min;		/* 25 Min RAS# to CAS# Delay Time */
+	uint8_t trp_min;		/* 26 Min Row Precharge Delay Time */
+	uint8_t tras_trc_ext;		/* 27 Upper Nibbles for tRAS and tRC */
+	uint8_t tras_min_lsb;		/* 28 tRASmin, lsb */
+	uint8_t trc_min_lsb;		/* 29 tRCmin, lsb */
+	uint8_t trfc1_min_lsb;		/* 30 Min Refresh Recovery Delay Time */
+	uint8_t trfc1_min_msb;		/* 31 Min Refresh Recovery Delay Time */
+	uint8_t trfc2_min_lsb;		/* 32 Min Refresh Recovery Delay Time */
+	uint8_t trfc2_min_msb;		/* 33 Min Refresh Recovery Delay Time */
+	uint8_t trfc4_min_lsb;		/* 34 Min Refresh Recovery Delay Time */
+	uint8_t trfc4_min_msb;		/* 35 Min Refresh Recovery Delay Time */
+	uint8_t tfaw_msb;		/* 36 Upper Nibble for tFAW */
+	uint8_t tfaw_min;		/* 37 tFAW, lsb */
+	uint8_t trrds_min;		/* 38 tRRD_Smin, MTB */
+	uint8_t trrdl_min;		/* 39 tRRD_Lmin, MTB */
+	uint8_t tccdl_min;		/* 40 tCCS_Lmin, MTB */
+	uint8_t res_41[60-41];		/* 41 Rserved */
+	uint8_t mapping[78-60];		/* 60~77 Connector to SDRAM bit map */
+	uint8_t res_78[117-78];		/* 78~116, Reserved */
+	int8_t fine_tccdl_min;		/* 117 Fine offset for tCCD_Lmin */
+	int8_t fine_trrdl_min;		/* 118 Fine offset for tRRD_Lmin */
+	int8_t fine_trrds_min;		/* 119 Fine offset for tRRD_Smin */
+	int8_t fine_trc_min;		/* 120 Fine offset for tRCmin */
+	int8_t fine_trp_min;		/* 121 Fine offset for tRPmin */
+	int8_t fine_trcd_min;		/* 122 Fine offset for tRCDmin */
+	int8_t fine_taa_min;		/* 123 Fine offset for tAAmin */
+	int8_t fine_tck_max;		/* 124 Fine offset for tCKAVGmax */
+	int8_t fine_tck_min;		/* 125 Fine offset for tCKAVGmin */
+	/* CRC: Bytes 126-127 */
+	uint8_t crc[2];			/* 126-127 SPD CRC */
+
+	/* Module-Specific Section: Bytes 128-255 */
+	union {
+		struct {
+			/* 128 (Unbuffered) Module Nominal Height */
+			uint8_t mod_height;
+			/* 129 (Unbuffered) Module Maximum Thickness */
+			uint8_t mod_thickness;
+			/* 130 (Unbuffered) Reference Raw Card Used */
+			uint8_t ref_raw_card;
+			/* 131 (Unbuffered) Address Mapping from
+			      Edge Connector to DRAM */
+			uint8_t addr_mapping;
+			/* 132~253 (Unbuffered) Reserved */
+			uint8_t res_132[254-132];
+			/* 254~255 CRC */
+			uint8_t crc[2];
+		} unbuffered;
+		struct {
+			/* 128 (Registered) Module Nominal Height */
+			uint8_t mod_height;
+			/* 129 (Registered) Module Maximum Thickness */
+			uint8_t mod_thickness;
+			/* 130 (Registered) Reference Raw Card Used */
+			uint8_t ref_raw_card;
+			/* 131 DIMM Module Attributes */
+			uint8_t modu_attr;
+			/* 132 RDIMM Thermal Heat Spreader Solution */
+			uint8_t thermal;
+			/* 133 Register Manufacturer ID Code, LSB */
+			uint8_t reg_id_lo;
+			/* 134 Register Manufacturer ID Code, MSB */
+			uint8_t reg_id_hi;
+			/* 135 Register Revision Number */
+			uint8_t reg_rev;
+			/* 136 Address mapping from register to DRAM */
+			uint8_t reg_map;
+			/* 137~253 Reserved */
+			uint8_t res_137[254-137];
+			/* 254~255 CRC */
+			uint8_t crc[2];
+		} registered;
+		struct {
+			/* 128 (Loadreduced) Module Nominal Height */
+			uint8_t mod_height;
+			/* 129 (Loadreduced) Module Maximum Thickness */
+			uint8_t mod_thickness;
+			/* 130 (Loadreduced) Reference Raw Card Used */
+			uint8_t ref_raw_card;
+			/* 131 DIMM Module Attributes */
+			uint8_t modu_attr;
+			/* 132 RDIMM Thermal Heat Spreader Solution */
+			uint8_t thermal;
+			/* 133 Register Manufacturer ID Code, LSB */
+			uint8_t reg_id_lo;
+			/* 134 Register Manufacturer ID Code, MSB */
+			uint8_t reg_id_hi;
+			/* 135 Register Revision Number */
+			uint8_t reg_rev;
+			/* 136 Address mapping from register to DRAM */
+			uint8_t reg_map;
+			/* 137 Register Output Drive Strength for CMD/Add*/
+			uint8_t reg_drv;
+			/* 138 Register Output Drive Strength for CK */
+			uint8_t reg_drv_ck;
+			/* 139 Data Buffer Revision Number */
+			uint8_t data_buf_rev;
+			/* 140 DRAM VrefDQ for Package Rank 0 */
+			uint8_t vrefqe_r0;
+			/* 141 DRAM VrefDQ for Package Rank 1 */
+			uint8_t vrefqe_r1;
+			/* 142 DRAM VrefDQ for Package Rank 2 */
+			uint8_t vrefqe_r2;
+			/* 143 DRAM VrefDQ for Package Rank 3 */
+			uint8_t vrefqe_r3;
+			/* 144 Data Buffer VrefDQ for DRAM Interface */
+			uint8_t data_intf;
+			/*
+			 * 145 Data Buffer MDQ Drive Strength and RTT
+			 * for data rate <= 1866
+			 */
+			uint8_t data_drv_1866;
+			/*
+			 * 146 Data Buffer MDQ Drive Strength and RTT
+			 * for 1866 < data rate <= 2400
+			 */
+			uint8_t data_drv_2400;
+			/*
+			 * 147 Data Buffer MDQ Drive Strength and RTT
+			 * for 2400 < data rate <= 3200
+			 */
+			uint8_t data_drv_3200;
+			/* 148 DRAM Drive Strength */
+			uint8_t dram_drv;
+			/*
+			 * 149 DRAM ODT (RTT_WR, RTT_NOM)
+			 * for data rate <= 1866
+			 */
+			uint8_t dram_odt_1866;
+			/*
+			 * 150 DRAM ODT (RTT_WR, RTT_NOM)
+			 * for 1866 < data rate <= 2400
+			 */
+			uint8_t dram_odt_2400;
+			/*
+			 * 151 DRAM ODT (RTT_WR, RTT_NOM)
+			 * for 2400 < data rate <= 3200
+			 */
+			uint8_t dram_odt_3200;
+			/*
+			 * 152 DRAM ODT (RTT_PARK)
+			 * for data rate <= 1866
+			 */
+			uint8_t dram_odt_park_1866;
+			/*
+			 * 153 DRAM ODT (RTT_PARK)
+			 * for 1866 < data rate <= 2400
+			 */
+			uint8_t dram_odt_park_2400;
+			/*
+			 * 154 DRAM ODT (RTT_PARK)
+			 * for 2400 < data rate <= 3200
+			 */
+			uint8_t dram_odt_park_3200;
+			uint8_t res_155[254-155];	/* Reserved */
+			/* 254~255 CRC */
+			uint8_t crc[2];
+		} loadreduced;
+		uint8_t uc[128]; /* 128-255 Module-Specific Section */
+	} mod_section;
+
+	uint8_t res_256[320-256];	/* 256~319 Reserved */
+
+	/* Module supplier's data: Byte 320~383 */
+	uint8_t mmid_lsb;		/* 320 Module MfgID Code LSB */
+	uint8_t mmid_msb;		/* 321 Module MfgID Code MSB */
+	uint8_t mloc;			/* 322 Mfg Location */
+	uint8_t mdate[2];		/* 323~324 Mfg Date */
+	uint8_t sernum[4];		/* 325~328 Module Serial Number */
+	uint8_t mpart[20];		/* 329~348 Mfg's Module Part Number */
+	uint8_t mrev;			/* 349 Module Revision Code */
+	uint8_t dmid_lsb;		/* 350 DRAM MfgID Code LSB */
+	uint8_t dmid_msb;		/* 351 DRAM MfgID Code MSB */
+	uint8_t stepping;		/* 352 DRAM stepping */
+	uint8_t msd[29];		/* 353~381 Mfg's Specific Data */
+	uint8_t res_382[2];		/* 382~383 Reserved */
+
+	uint8_t user[512-384];		/* 384~511 End User Programmable */
+};
+
+extern unsigned int ddr1_spd_check(const ddr1_spd_eeprom_t *spd);
+extern void ddr1_spd_dump(const ddr1_spd_eeprom_t *spd);
+extern unsigned int ddr2_spd_check(const ddr2_spd_eeprom_t *spd);
+extern void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd);
+extern unsigned int ddr3_spd_check(const ddr3_spd_eeprom_t *spd);
+unsigned int ddr4_spd_check(const struct ddr4_spd_eeprom_s *spd);
+
+/*
+ * Byte 2 Fundamental Memory Types.
+ */
+#define SPD_MEMTYPE_FPM		(0x01)
+#define SPD_MEMTYPE_EDO		(0x02)
+#define SPD_MEMTYPE_PIPE_NIBBLE	(0x03)
+#define SPD_MEMTYPE_SDRAM	(0x04)
+#define SPD_MEMTYPE_ROM		(0x05)
+#define SPD_MEMTYPE_SGRAM	(0x06)
+#define SPD_MEMTYPE_DDR		(0x07)
+#define SPD_MEMTYPE_DDR2	(0x08)
+#define SPD_MEMTYPE_DDR2_FBDIMM	(0x09)
+#define SPD_MEMTYPE_DDR2_FBDIMM_PROBE	(0x0A)
+#define SPD_MEMTYPE_DDR3	(0x0B)
+#define SPD_MEMTYPE_DDR4	(0x0C)
+
+/* DIMM Type for DDR2 SPD (according to v1.3) */
+#define DDR2_SPD_DIMMTYPE_UNDEFINED	(0x00)
+#define DDR2_SPD_DIMMTYPE_RDIMM		(0x01)
+#define DDR2_SPD_DIMMTYPE_UDIMM		(0x02)
+#define DDR2_SPD_DIMMTYPE_SO_DIMM	(0x04)
+#define DDR2_SPD_DIMMTYPE_72B_SO_CDIMM	(0x06)
+#define DDR2_SPD_DIMMTYPE_72B_SO_RDIMM	(0x07)
+#define DDR2_SPD_DIMMTYPE_MICRO_DIMM	(0x08)
+#define DDR2_SPD_DIMMTYPE_MINI_RDIMM	(0x10)
+#define DDR2_SPD_DIMMTYPE_MINI_UDIMM	(0x20)
+
+/* Byte 3 Key Byte / Module Type for DDR3 SPD */
+#define DDR3_SPD_MODULETYPE_MASK	(0x0f)
+#define DDR3_SPD_MODULETYPE_RDIMM	(0x01)
+#define DDR3_SPD_MODULETYPE_UDIMM	(0x02)
+#define DDR3_SPD_MODULETYPE_SO_DIMM	(0x03)
+#define DDR3_SPD_MODULETYPE_MICRO_DIMM	(0x04)
+#define DDR3_SPD_MODULETYPE_MINI_RDIMM	(0x05)
+#define DDR3_SPD_MODULETYPE_MINI_UDIMM	(0x06)
+#define DDR3_SPD_MODULETYPE_MINI_CDIMM	(0x07)
+#define DDR3_SPD_MODULETYPE_72B_SO_UDIMM	(0x08)
+#define DDR3_SPD_MODULETYPE_72B_SO_RDIMM	(0x09)
+#define DDR3_SPD_MODULETYPE_72B_SO_CDIMM	(0x0A)
+#define DDR3_SPD_MODULETYPE_LRDIMM	(0x0B)
+#define DDR3_SPD_MODULETYPE_16B_SO_DIMM	(0x0C)
+#define DDR3_SPD_MODULETYPE_32B_SO_DIMM	(0x0D)
+
+/* DIMM Type for DDR4 SPD */
+#define DDR4_SPD_MODULETYPE_MASK	(0x0f)
+#define DDR4_SPD_MODULETYPE_EXT		(0x00)
+#define DDR4_SPD_MODULETYPE_RDIMM	(0x01)
+#define DDR4_SPD_MODULETYPE_UDIMM	(0x02)
+#define DDR4_SPD_MODULETYPE_SO_DIMM	(0x03)
+#define DDR4_SPD_MODULETYPE_LRDIMM	(0x04)
+#define DDR4_SPD_MODULETYPE_MINI_RDIMM	(0x05)
+#define DDR4_SPD_MODULETYPE_MINI_UDIMM	(0x06)
+#define DDR4_SPD_MODULETYPE_72B_SO_UDIMM	(0x08)
+#define DDR4_SPD_MODULETYPE_72B_SO_RDIMM	(0x09)
+#define DDR4_SPD_MODULETYPE_16B_SO_DIMM	(0x0C)
+#define DDR4_SPD_MODULETYPE_32B_SO_DIMM	(0x0D)
+
+#endif /* _DDR_SPD_H_ */
diff --git a/qemu/roms/u-boot/include/dfu.h b/qemu/roms/u-boot/include/dfu.h
new file mode 100644
index 000000000..240916854
--- /dev/null
+++ b/qemu/roms/u-boot/include/dfu.h
@@ -0,0 +1,172 @@
+/*
+ * dfu.h - DFU flashable area description
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ * authors: Andrzej Pietrasiewicz <andrzej.p@samsung.com>
+ *	    Lukasz Majewski <l.majewski@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DFU_ENTITY_H_
+#define __DFU_ENTITY_H_
+
+#include <common.h>
+#include <linux/list.h>
+#include <mmc.h>
+#include <linux/usb/composite.h>
+
+enum dfu_device_type {
+	DFU_DEV_MMC = 1,
+	DFU_DEV_ONENAND,
+	DFU_DEV_NAND,
+	DFU_DEV_RAM,
+};
+
+enum dfu_layout {
+	DFU_RAW_ADDR = 1,
+	DFU_FS_FAT,
+	DFU_FS_EXT2,
+	DFU_FS_EXT3,
+	DFU_FS_EXT4,
+	DFU_RAM_ADDR,
+};
+
+enum dfu_op {
+	DFU_OP_READ = 1,
+	DFU_OP_WRITE,
+};
+
+struct mmc_internal_data {
+	/* RAW programming */
+	unsigned int lba_start;
+	unsigned int lba_size;
+	unsigned int lba_blk_size;
+
+	/* FAT/EXT */
+	unsigned int dev;
+	unsigned int part;
+};
+
+struct nand_internal_data {
+	/* RAW programming */
+	u64 start;
+	u64 size;
+
+	unsigned int dev;
+	unsigned int part;
+	/* for nand/ubi use */
+	unsigned int ubi;
+};
+
+struct ram_internal_data {
+	void		*start;
+	unsigned int	size;
+};
+
+#define DFU_NAME_SIZE			32
+#define DFU_CMD_BUF_SIZE		128
+#ifndef CONFIG_SYS_DFU_DATA_BUF_SIZE
+#define CONFIG_SYS_DFU_DATA_BUF_SIZE		(1024*1024*8)	/* 8 MiB */
+#endif
+#ifndef CONFIG_SYS_DFU_MAX_FILE_SIZE
+#define CONFIG_SYS_DFU_MAX_FILE_SIZE CONFIG_SYS_DFU_DATA_BUF_SIZE
+#endif
+#ifndef DFU_DEFAULT_POLL_TIMEOUT
+#define DFU_DEFAULT_POLL_TIMEOUT 0
+#endif
+#ifndef DFU_MANIFEST_POLL_TIMEOUT
+#define DFU_MANIFEST_POLL_TIMEOUT	DFU_DEFAULT_POLL_TIMEOUT
+#endif
+
+struct dfu_entity {
+	char			name[DFU_NAME_SIZE];
+	int                     alt;
+	void                    *dev_private;
+	int                     dev_num;
+	enum dfu_device_type    dev_type;
+	enum dfu_layout         layout;
+
+	union {
+		struct mmc_internal_data mmc;
+		struct nand_internal_data nand;
+		struct ram_internal_data ram;
+	} data;
+
+	int (*read_medium)(struct dfu_entity *dfu,
+			u64 offset, void *buf, long *len);
+
+	int (*write_medium)(struct dfu_entity *dfu,
+			u64 offset, void *buf, long *len);
+
+	int (*flush_medium)(struct dfu_entity *dfu);
+
+	struct list_head list;
+
+	/* on the fly state */
+	u32 crc;
+	u64 offset;
+	int i_blk_seq_num;
+	u8 *i_buf;
+	u8 *i_buf_start;
+	u8 *i_buf_end;
+	long r_left;
+	long b_left;
+
+	u32 bad_skip;	/* for nand use */
+
+	unsigned int inited:1;
+};
+
+int dfu_config_entities(char *s, char *interface, int num);
+void dfu_free_entities(void);
+void dfu_show_entities(void);
+int dfu_get_alt_number(void);
+const char *dfu_get_dev_type(enum dfu_device_type t);
+const char *dfu_get_layout(enum dfu_layout l);
+struct dfu_entity *dfu_get_entity(int alt);
+char *dfu_extract_token(char** e, int *n);
+void dfu_trigger_reset(void);
+int dfu_get_alt(char *name);
+bool dfu_reset(void);
+int dfu_init_env_entities(char *interface, int dev);
+unsigned char *dfu_get_buf(void);
+unsigned char *dfu_free_buf(void);
+unsigned long dfu_get_buf_size(void);
+
+int dfu_read(struct dfu_entity *de, void *buf, int size, int blk_seq_num);
+int dfu_write(struct dfu_entity *de, void *buf, int size, int blk_seq_num);
+int dfu_flush(struct dfu_entity *de, void *buf, int size, int blk_seq_num);
+/* Device specific */
+#ifdef CONFIG_DFU_MMC
+extern int dfu_fill_entity_mmc(struct dfu_entity *dfu, char *s);
+#else
+static inline int dfu_fill_entity_mmc(struct dfu_entity *dfu, char *s)
+{
+	puts("MMC support not available!\n");
+	return -1;
+}
+#endif
+
+#ifdef CONFIG_DFU_NAND
+extern int dfu_fill_entity_nand(struct dfu_entity *dfu, char *s);
+#else
+static inline int dfu_fill_entity_nand(struct dfu_entity *dfu, char *s)
+{
+	puts("NAND support not available!\n");
+	return -1;
+}
+#endif
+
+#ifdef CONFIG_DFU_RAM
+extern int dfu_fill_entity_ram(struct dfu_entity *dfu, char *s);
+#else
+static inline int dfu_fill_entity_ram(struct dfu_entity *dfu, char *s)
+{
+	puts("RAM support not available!\n");
+	return -1;
+}
+#endif
+
+int dfu_add(struct usb_configuration *c);
+#endif /* __DFU_ENTITY_H_ */
diff --git a/qemu/roms/u-boot/include/dialog_pmic.h b/qemu/roms/u-boot/include/dialog_pmic.h
new file mode 100644
index 000000000..8f36bb63b
--- /dev/null
+++ b/qemu/roms/u-boot/include/dialog_pmic.h
@@ -0,0 +1,174 @@
+/*
+ * da9053 register declarations.
+ *
+ * Copyright(c) 2009 Dialog Semiconductor Ltd.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DIALOG_PMIC_H__
+#define __DIALOG_PMIC_H__
+
+enum {
+	DA9053_PAGECON0_REG = 0,
+	DA9053_STATUSA_REG,
+	DA9053_STATUSB_REG,
+	DA9053_STATUSC_REG,
+	DA9053_STATUSD_REG,
+	DA9053_EVENTA_REG,
+	DA9053_EVENTB_REG,
+	DA9053_EVENTC_REG,
+	DA9053_EVENTD_REG,
+	DA9053_FAULTLOG_REG,
+	DA9053_IRQMASKA_REG,
+	DA9053_IRQMASKB_REG,
+	DA9053_IRQMASKC_REG,
+	DA9053_IRQMASKD_REG,
+	DA9053_CONTROLA_REG,
+	DA9053_CONTROLB_REG,
+	DA9053_CONTROLC_REG,
+	DA9053_CONTROLD_REG,
+	DA9053_PDDIS_REG,
+	DA9053_INTERFACE_REG,
+	DA9053_RESET_REG,
+	DA9053_GPIO0001_REG,
+	DA9053_GPIO0203_REG,
+	DA9053_GPIO0405_REG,
+	DA9053_GPIO0607_REG,
+	DA9053_GPIO0809_REG,
+	DA9053_GPIO1011_REG,
+	DA9053_GPIO1213_REG,
+	DA9053_GPIO1415_REG,
+	DA9053_ID01_REG,
+	DA9053_ID23_REG,
+	DA9053_ID45_REG,
+	DA9053_ID67_REG,
+	DA9053_ID89_REG,
+	DA9053_ID1011_REG,
+	DA9053_ID1213_REG,
+	DA9053_ID1415_REG,
+	DA9053_ID1617_REG,
+	DA9053_ID1819_REG,
+	DA9053_ID2021_REG,
+	DA9053_SEQSTATUS_REG,
+	DA9053_SEQA_REG,
+	DA9053_SEQB_REG,
+	DA9053_SEQTIMER_REG,
+	DA9053_BUCKA_REG,
+	DA9053_BUCKB_REG,
+	DA9053_BUCKCORE_REG,
+	DA9053_BUCKPRO_REG,
+	DA9053_BUCKMEM_REG,
+	DA9053_BUCKPERI_REG,
+	DA9053_LDO1_REG,
+	DA9053_LDO2_REG,
+	DA9053_LDO3_REG,
+	DA9053_LDO4_REG,
+	DA9053_LDO5_REG,
+	DA9053_LDO6_REG,
+	DA9053_LDO7_REG,
+	DA9053_LDO8_REG,
+	DA9053_LDO9_REG,
+	DA9053_LDO10_REG,
+	DA9053_SUPPLY_REG,
+	DA9053_PULLDOWN_REG,
+	DA9053_CHGBUCK_REG,
+	DA9053_WAITCONT_REG,
+	DA9053_ISET_REG,
+	DA9053_BATCHG_REG,
+	DA9053_CHGCONT_REG,
+	DA9053_INPUTCONT_REG,
+	DA9053_CHGTIME_REG,
+	DA9053_BBATCONT_REG,
+	DA9053_BOOST_REG,
+	DA9053_LEDCONT_REG,
+	DA9053_LEDMIN123_REG,
+	DA9053_LED1CONF_REG,
+	DA9053_LED2CONF_REG,
+	DA9053_LED3CONF_REG,
+	DA9053_LED1CONT_REG,
+	DA9053_LED2CONT_REG,
+	DA9053_LED3CONT_REG,
+	DA9053_LED4CONT_REG,
+	DA9053_LED5CONT_REG,
+	DA9053_ADCMAN_REG,
+	DA9053_ADCCONT_REG,
+	DA9053_ADCRESL_REG,
+	DA9053_ADCRESH_REG,
+	DA9053_VDDRES_REG,
+	DA9053_VDDMON_REG,
+	DA9053_ICHGAV_REG,
+	DA9053_ICHGTHD_REG,
+	DA9053_ICHGEND_REG,
+	DA9053_TBATRES_REG,
+	DA9053_TBATHIGHP_REG,
+	DA9053_TBATHIGHIN_REG,
+	DA9053_TBATLOW_REG,
+	DA9053_TOFFSET_REG,
+	DA9053_ADCIN4RES_REG,
+	DA9053_AUTO4HIGH_REG,
+	DA9053_AUTO4LOW_REG,
+	DA9053_ADCIN5RES_REG,
+	DA9053_AUTO5HIGH_REG,
+	DA9053_AUTO5LOW_REG,
+	DA9053_ADCIN6RES_REG,
+	DA9053_AUTO6HIGH_REG,
+	DA9053_AUTO6LOW_REG,
+	DA9053_TJUNCRES_REG,
+	DA9053_TSICONTA_REG,
+	DA9053_TSICONTB_REG,
+	DA9053_TSIXMSB_REG,
+	DA9053_TSIYMSB_REG,
+	DA9053_TSILSB_REG,
+	DA9053_TSIZMSB_REG,
+	DA9053_COUNTS_REG,
+	DA9053_COUNTMI_REG,
+	DA9053_COUNTH_REG,
+	DA9053_COUNTD_REG,
+	DA9053_COUNTMO_REG,
+	DA9053_COUNTY_REG,
+	DA9053_ALARMMI_REG,
+	DA9053_ALARMH_REG,
+	DA9053_ALARMD_REG,
+	DA9053_ALARMMO_REG,
+	DA9053_ALARMY_REG,
+	DA9053_SECONDA_REG,
+	DA9053_SECONDB_REG,
+	DA9053_SECONDC_REG,
+	DA9053_SECONDD_REG,
+	DA9053_PAGECON128_REG,
+	DA9053_CHIPID_REG,
+	DA9053_CONFIGID_REG,
+	DA9053_OTPCONT_REG,
+	DA9053_OSCTRIM_REG,
+	DA9053_GPID0_REG,
+	DA9053_GPID1_REG,
+	DA9053_GPID2_REG,
+	DA9053_GPID3_REG,
+	DA9053_GPID4_REG,
+	DA9053_GPID5_REG,
+	DA9053_GPID6_REG,
+	DA9053_GPID7_REG,
+	DA9053_GPID8_REG,
+	DA9053_GPID9_REG,
+	DIALOG_NUM_OF_REGS,
+};
+
+#define DA_BUCKCORE_VBCORE_1_250V		0x1E
+
+/* BUCKCORE REGISTER */
+#define DA9052_BUCKCORE_BCORECONF               (1 << 7)
+#define DA9052_BUCKCORE_BCOREEN                 (1 << 6)
+#define DA9052_BUCKCORE_VBCORE                  63
+
+/* SUPPLY REGISTER */
+#define DA9052_SUPPLY_VLOCK                     (1 << 7)
+#define DA9052_SUPPLY_VMEMSWEN                  (1 << 6)
+#define DA9052_SUPPLY_VPERISWEN                 (1 << 5)
+#define DA9052_SUPPLY_VLDO3GO                   (1 << 4)
+#define DA9052_SUPPLY_VLDO2GO                   (1 << 3)
+#define DA9052_SUPPLY_VBMEMGO                   (1 << 2)
+#define DA9052_SUPPLY_VBPROGO                   (1 << 1)
+#define DA9052_SUPPLY_VBCOREGO                  (1 << 0)
+
+#endif /* __DIALOG_PMIC_H__ */
diff --git a/qemu/roms/u-boot/include/div64.h b/qemu/roms/u-boot/include/div64.h
new file mode 100644
index 000000000..d83314435
--- /dev/null
+++ b/qemu/roms/u-boot/include/div64.h
@@ -0,0 +1,49 @@
+#ifndef _ASM_GENERIC_DIV64_H
+#define _ASM_GENERIC_DIV64_H
+/*
+ * Copyright (C) 2003 Bernardo Innocenti <bernie@develer.com>
+ * Based on former asm-ppc/div64.h and asm-m68knommu/div64.h
+ *
+ * The semantics of do_div() are:
+ *
+ * uint32_t do_div(uint64_t *n, uint32_t base)
+ * {
+ *	uint32_t remainder = *n % base;
+ *	*n = *n / base;
+ *	return remainder;
+ * }
+ *
+ * NOTE: macro parameter n is evaluated multiple times,
+ *       beware of side effects!
+ */
+
+#include <linux/types.h>
+
+extern uint32_t __div64_32(uint64_t *dividend, uint32_t divisor);
+
+/* The unnecessary pointer compare is there
+ * to check for type safety (n must be 64bit)
+ */
+# define do_div(n,base) ({				\
+	uint32_t __base = (base);			\
+	uint32_t __rem;					\
+	(void)(((typeof((n)) *)0) == ((uint64_t *)0));	\
+	if (((n) >> 32) == 0) {			\
+		__rem = (uint32_t)(n) % __base;		\
+		(n) = (uint32_t)(n) / __base;		\
+	} else						\
+		__rem = __div64_32(&(n), __base);	\
+	__rem;						\
+ })
+
+/* Wrapper for do_div(). Doesn't modify dividend and returns
+ * the result, not reminder.
+ */
+static inline uint64_t lldiv(uint64_t dividend, uint32_t divisor)
+{
+	uint64_t __res = dividend;
+	do_div(__res, divisor);
+	return(__res);
+}
+
+#endif /* _ASM_GENERIC_DIV64_H */
diff --git a/qemu/roms/u-boot/include/dm-demo.h b/qemu/roms/u-boot/include/dm-demo.h
new file mode 100644
index 000000000..6e38d3c5b
--- /dev/null
+++ b/qemu/roms/u-boot/include/dm-demo.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DM_DEMO_H
+#define __DM_DEMO_H
+
+#include <dm.h>
+
+/**
+ * struct dm_demo_pdata - configuration data for demo instance
+ *
+ * @colour: Color of the demo
+ * @sides: Numbers of sides
+ * @default_char: Default ASCII character to output (65 = 'A')
+ */
+struct dm_demo_pdata {
+	const char *colour;
+	int sides;
+	int default_char;
+};
+
+struct demo_ops {
+	int (*hello)(struct device *dev, int ch);
+	int (*status)(struct device *dev, int *status);
+};
+
+int demo_hello(struct device *dev, int ch);
+int demo_status(struct device *dev, int *status);
+int demo_list(void);
+
+int demo_parse_dt(struct device *dev);
+
+#endif
diff --git a/qemu/roms/u-boot/include/dm.h b/qemu/roms/u-boot/include/dm.h
new file mode 100644
index 000000000..8bbb21b57
--- /dev/null
+++ b/qemu/roms/u-boot/include/dm.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _DM_H_
+#define _DM_H
+
+#include <dm/device.h>
+#include <dm/platdata.h>
+#include <dm/uclass.h>
+
+#endif
diff --git a/qemu/roms/u-boot/include/dm/device-internal.h b/qemu/roms/u-boot/include/dm/device-internal.h
new file mode 100644
index 000000000..c026e8e49
--- /dev/null
+++ b/qemu/roms/u-boot/include/dm/device-internal.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (C) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ * Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _DM_DEVICE_INTERNAL_H
+#define _DM_DEVICE_INTERNAL_H
+
+struct device;
+
+/**
+ * device_bind() - Create a device and bind it to a driver
+ *
+ * Called to set up a new device attached to a driver. The device will either
+ * have platdata, or a device tree node which can be used to create the
+ * platdata.
+ *
+ * Once bound a device exists but is not yet active until device_probe() is
+ * called.
+ *
+ * @parent: Pointer to device's parent, under which this driver will exist
+ * @drv: Device's driver
+ * @name: Name of device (e.g. device tree node name)
+ * @platdata: Pointer to data for this device - the structure is device-
+ * specific but may include the device's I/O address, etc.. This is NULL for
+ * devices which use device tree.
+ * @of_offset: Offset of device tree node for this device. This is -1 for
+ * devices which don't use device tree.
+ * @devp: Returns a pointer to the bound device
+ * @return 0 if OK, -ve on error
+ */
+int device_bind(struct device *parent, struct driver *drv,
+		const char *name, void *platdata, int of_offset,
+		struct device **devp);
+
+/**
+ * device_bind_by_name: Create a device and bind it to a driver
+ *
+ * This is a helper function used to bind devices which do not use device
+ * tree.
+ *
+ * @parent: Pointer to device's parent
+ * @info: Name and platdata for this device
+ * @devp: Returns a pointer to the bound device
+ * @return 0 if OK, -ve on error
+ */
+int device_bind_by_name(struct device *parent, const struct driver_info *info,
+			struct device **devp);
+
+/**
+ * device_probe() - Probe a device, activating it
+ *
+ * Activate a device so that it is ready for use. All its parents are probed
+ * first.
+ *
+ * @dev: Pointer to device to probe
+ * @return 0 if OK, -ve on error
+ */
+int device_probe(struct device *dev);
+
+/**
+ * device_remove() - Remove a device, de-activating it
+ *
+ * De-activate a device so that it is no longer ready for use. All its
+ * children are deactivated first.
+ *
+ * @dev: Pointer to device to remove
+ * @return 0 if OK, -ve on error (an error here is normally a very bad thing)
+ */
+int device_remove(struct device *dev);
+
+/**
+ * device_unbind() - Unbind a device, destroying it
+ *
+ * Unbind a device and remove all memory used by it
+ *
+ * @dev: Pointer to device to unbind
+ * @return 0 if OK, -ve on error
+ */
+int device_unbind(struct device *dev);
+
+#endif
diff --git a/qemu/roms/u-boot/include/dm/device.h b/qemu/roms/u-boot/include/dm/device.h
new file mode 100644
index 000000000..4cd38ed2d
--- /dev/null
+++ b/qemu/roms/u-boot/include/dm/device.h
@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ * Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _DM_DEVICE_H
+#define _DM_DEVICE_H
+
+#include <dm/uclass-id.h>
+#include <linker_lists.h>
+#include <linux/list.h>
+
+struct driver_info;
+
+/* Driver is active (probed). Cleared when it is removed */
+#define DM_FLAG_ACTIVATED	(1 << 0)
+
+/* DM is responsible for allocating and freeing platdata */
+#define DM_FLAG_ALLOC_PDATA	(2 << 0)
+
+/**
+ * struct device - An instance of a driver
+ *
+ * This holds information about a device, which is a driver bound to a
+ * particular port or peripheral (essentially a driver instance).
+ *
+ * A device will come into existence through a 'bind' call, either due to
+ * a U_BOOT_DEVICE() macro (in which case platdata is non-NULL) or a node
+ * in the device tree (in which case of_offset is >= 0). In the latter case
+ * we translate the device tree information into platdata in a function
+ * implemented by the driver ofdata_to_platdata method (called just before the
+ * probe method if the device has a device tree node.
+ *
+ * All three of platdata, priv and uclass_priv can be allocated by the
+ * driver, or you can use the auto_alloc_size members of struct driver and
+ * struct uclass_driver to have driver model do this automatically.
+ *
+ * @driver: The driver used by this device
+ * @name: Name of device, typically the FDT node name
+ * @platdata: Configuration data for this device
+ * @of_offset: Device tree node offset for this device (- for none)
+ * @parent: Parent of this device, or NULL for the top level device
+ * @priv: Private data for this device
+ * @uclass: Pointer to uclass for this device
+ * @uclass_priv: The uclass's private data for this device
+ * @uclass_node: Used by uclass to link its devices
+ * @child_head: List of children of this device
+ * @sibling_node: Next device in list of all devices
+ * @flags: Flags for this device DM_FLAG_...
+ */
+struct device {
+	struct driver *driver;
+	const char *name;
+	void *platdata;
+	int of_offset;
+	struct device *parent;
+	void *priv;
+	struct uclass *uclass;
+	void *uclass_priv;
+	struct list_head uclass_node;
+	struct list_head child_head;
+	struct list_head sibling_node;
+	uint32_t flags;
+};
+
+/* Returns the operations for a device */
+#define device_get_ops(dev)	(dev->driver->ops)
+
+/* Returns non-zero if the device is active (probed and not removed) */
+#define device_active(dev)	((dev)->flags & DM_FLAG_ACTIVATED)
+
+/**
+ * struct device_id - Lists the compatible strings supported by a driver
+ * @compatible: Compatible string
+ * @data: Data for this compatible string
+ */
+struct device_id {
+	const char *compatible;
+	ulong data;
+};
+
+/**
+ * struct driver - A driver for a feature or peripheral
+ *
+ * This holds methods for setting up a new device, and also removing it.
+ * The device needs information to set itself up - this is provided either
+ * by platdata or a device tree node (which we find by looking up
+ * matching compatible strings with of_match).
+ *
+ * Drivers all belong to a uclass, representing a class of devices of the
+ * same type. Common elements of the drivers can be implemented in the uclass,
+ * or the uclass can provide a consistent interface to the drivers within
+ * it.
+ *
+ * @name: Device name
+ * @id: Identiies the uclass we belong to
+ * @of_match: List of compatible strings to match, and any identifying data
+ * for each.
+ * @bind: Called to bind a device to its driver
+ * @probe: Called to probe a device, i.e. activate it
+ * @remove: Called to remove a device, i.e. de-activate it
+ * @unbind: Called to unbind a device from its driver
+ * @ofdata_to_platdata: Called before probe to decode device tree data
+ * @priv_auto_alloc_size: If non-zero this is the size of the private data
+ * to be allocated in the device's ->priv pointer. If zero, then the driver
+ * is responsible for allocating any data required.
+ * @platdata_auto_alloc_size: If non-zero this is the size of the
+ * platform data to be allocated in the device's ->platdata pointer.
+ * This is typically only useful for device-tree-aware drivers (those with
+ * an of_match), since drivers which use platdata will have the data
+ * provided in the U_BOOT_DEVICE() instantiation.
+ * ops: Driver-specific operations. This is typically a list of function
+ * pointers defined by the driver, to implement driver functions required by
+ * the uclass.
+ */
+struct driver {
+	char *name;
+	enum uclass_id id;
+	const struct device_id *of_match;
+	int (*bind)(struct device *dev);
+	int (*probe)(struct device *dev);
+	int (*remove)(struct device *dev);
+	int (*unbind)(struct device *dev);
+	int (*ofdata_to_platdata)(struct device *dev);
+	int priv_auto_alloc_size;
+	int platdata_auto_alloc_size;
+	const void *ops;	/* driver-specific operations */
+};
+
+/* Declare a new U-Boot driver */
+#define U_BOOT_DRIVER(__name)						\
+	ll_entry_declare(struct driver, __name, driver)
+
+/**
+ * dev_get_platdata() - Get the platform data for a device
+ *
+ * This checks that dev is not NULL, but no other checks for now
+ *
+ * @dev		Device to check
+ * @return platform data, or NULL if none
+ */
+void *dev_get_platdata(struct device *dev);
+
+/**
+ * dev_get_priv() - Get the private data for a device
+ *
+ * This checks that dev is not NULL, but no other checks for now
+ *
+ * @dev		Device to check
+ * @return private data, or NULL if none
+ */
+void *dev_get_priv(struct device *dev);
+
+#endif
diff --git a/qemu/roms/u-boot/include/dm/lists.h b/qemu/roms/u-boot/include/dm/lists.h
new file mode 100644
index 000000000..0d09f9a14
--- /dev/null
+++ b/qemu/roms/u-boot/include/dm/lists.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _DM_LISTS_H_
+#define _DM_LISTS_H_
+
+#include <dm/uclass-id.h>
+
+/**
+ * lists_driver_lookup_name() - Return u_boot_driver corresponding to name
+ *
+ * This function returns a pointer to a driver given its name. This is used
+ * for binding a driver given its name and platdata.
+ *
+ * @name: Name of driver to look up
+ * @return pointer to driver, or NULL if not found
+ */
+struct driver *lists_driver_lookup_name(const char *name);
+
+/**
+ * lists_uclass_lookup() - Return uclass_driver based on ID of the class
+ * id:		ID of the class
+ *
+ * This function returns the pointer to uclass_driver, which is the class's
+ * base structure based on the ID of the class. Returns NULL on error.
+ */
+struct uclass_driver *lists_uclass_lookup(enum uclass_id id);
+
+int lists_bind_drivers(struct device *parent);
+
+int lists_bind_fdt(struct device *parent, const void *blob, int offset);
+
+#endif
diff --git a/qemu/roms/u-boot/include/dm/platdata.h b/qemu/roms/u-boot/include/dm/platdata.h
new file mode 100644
index 000000000..0ef3353e7
--- /dev/null
+++ b/qemu/roms/u-boot/include/dm/platdata.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ * Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _DM_PLATDATA_H
+#define _DM_PLATDATA_H
+
+struct driver_info {
+	const char	*name;
+	const void	*platdata;
+};
+
+#define U_BOOT_DEVICE(__name)						\
+	ll_entry_declare(struct driver_info, __name, driver_info)
+
+#endif
diff --git a/qemu/roms/u-boot/include/dm/root.h b/qemu/roms/u-boot/include/dm/root.h
new file mode 100644
index 000000000..0ebccda35
--- /dev/null
+++ b/qemu/roms/u-boot/include/dm/root.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _DM_ROOT_H_
+#define _DM_ROOT_H_
+
+struct device;
+
+/**
+ * dm_root() - Return pointer to the top of the driver tree
+ *
+ * This function returns pointer to the root node of the driver tree,
+ *
+ * @return pointer to root device, or NULL if not inited yet
+ */
+struct device *dm_root(void);
+
+/**
+ * dm_scan_platdata() - Scan all platform data and bind drivers
+ *
+ * This scans all available platdata and creates drivers for each
+ *
+ * @return 0 if OK, -ve on error
+ */
+int dm_scan_platdata(void);
+
+/**
+ * dm_scan_fdt() - Scan the device tree and bind drivers
+ *
+ * This scans the device tree and creates a driver for each node
+ *
+ * @blob: Pointer to device tree blob
+ * @return 0 if OK, -ve on error
+ */
+int dm_scan_fdt(const void *blob);
+
+/**
+ * dm_init() - Initialize Driver Model structures
+ *
+ * This function will initialize roots of driver tree and class tree.
+ * This needs to be called before anything uses the DM
+ *
+ * @return 0 if OK, -ve on error
+ */
+int dm_init(void);
+
+#endif
diff --git a/qemu/roms/u-boot/include/dm/test.h b/qemu/roms/u-boot/include/dm/test.h
new file mode 100644
index 000000000..eeaa2eb2f
--- /dev/null
+++ b/qemu/roms/u-boot/include/dm/test.h
@@ -0,0 +1,167 @@
+/*
+ * Copyright (c) 2013 Google, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DM_TEST_H
+#define __DM_TEST_H
+
+#include <dm.h>
+
+/**
+ * struct dm_test_cdata - configuration data for test instance
+ *
+ * @ping_add: Amonut to add each time we get a ping
+ * @base: Base address of this device
+ */
+struct dm_test_pdata {
+	int ping_add;
+	uint32_t base;
+};
+
+/**
+ * struct test_ops - Operations supported by the test device
+ *
+ * @ping: Ping operation
+ *	@dev: Device to operate on
+ *	@pingval: Value to ping the device with
+ *	@pingret: Returns resulting value from driver
+ *	@return 0 if OK, -ve on error
+ */
+struct test_ops {
+	int (*ping)(struct device *dev, int pingval, int *pingret);
+};
+
+/* Operations that our test driver supports */
+enum {
+	DM_TEST_OP_BIND = 0,
+	DM_TEST_OP_UNBIND,
+	DM_TEST_OP_PROBE,
+	DM_TEST_OP_REMOVE,
+
+	/* For uclass */
+	DM_TEST_OP_POST_BIND,
+	DM_TEST_OP_PRE_UNBIND,
+	DM_TEST_OP_POST_PROBE,
+	DM_TEST_OP_PRE_REMOVE,
+	DM_TEST_OP_INIT,
+	DM_TEST_OP_DESTROY,
+
+	DM_TEST_OP_COUNT,
+};
+
+/* Test driver types */
+enum {
+	DM_TEST_TYPE_FIRST = 0,
+	DM_TEST_TYPE_SECOND,
+};
+
+/* The number added to the ping total on each probe */
+#define DM_TEST_START_TOTAL	5
+
+/**
+ * struct dm_test_priv - private data for the test devices
+ */
+struct dm_test_priv {
+	int ping_total;
+	int op_count[DM_TEST_OP_COUNT];
+};
+
+/**
+ * struct dm_test_perdev_class_priv - private per-device data for test uclass
+ */
+struct dm_test_uclass_perdev_priv {
+	int base_add;
+};
+
+/**
+ * struct dm_test_uclass_priv - private data for test uclass
+ */
+struct dm_test_uclass_priv {
+	int total_add;
+};
+
+/*
+ * Operation counts for the test driver, used to check that each method is
+ * called correctly
+ */
+extern int dm_testdrv_op_count[DM_TEST_OP_COUNT];
+
+extern struct dm_test_state global_test_state;
+
+/*
+ * struct dm_test_state - Entire state of dm test system
+ *
+ * This is often abreviated to dms.
+ *
+ * @root: Root device
+ * @testdev: Test device
+ * @fail_count: Number of tests that failed
+ * @force_fail_alloc: Force all memory allocs to fail
+ * @skip_post_probe: Skip uclass post-probe processing
+ */
+struct dm_test_state {
+	struct device *root;
+	struct device *testdev;
+	int fail_count;
+	int force_fail_alloc;
+	int skip_post_probe;
+};
+
+/* Test flags for each test */
+enum {
+	DM_TESTF_SCAN_PDATA	= 1 << 0,	/* test needs platform data */
+	DM_TESTF_PROBE_TEST	= 1 << 1,	/* probe test uclass */
+	DM_TESTF_SCAN_FDT	= 1 << 2,	/* scan device tree */
+};
+
+/**
+ * struct dm_test - Information about a driver model test
+ *
+ * @name: Name of test
+ * @func: Function to call to perform test
+ * @flags: Flags indicated pre-conditions for test
+ */
+struct dm_test {
+	const char *name;
+	int (*func)(struct dm_test_state *dms);
+	int flags;
+};
+
+/* Declare a new driver model test */
+#define DM_TEST(_name, _flags)						\
+	ll_entry_declare(struct dm_test, _name, dm_test) = {		\
+		.name = #_name,						\
+		.flags = _flags,					\
+		.func = _name,						\
+	}
+
+/* Declare ping methods for the drivers */
+int test_ping(struct device *dev, int pingval, int *pingret);
+int testfdt_ping(struct device *dev, int pingval, int *pingret);
+
+/**
+ * dm_check_operations() - Check that we can perform ping operations
+ *
+ * This checks that the ping operations work as expected for a device
+ *
+ * @dms: Overall test state
+ * @dev: Device to test
+ * @base: Base address, used to check ping return value
+ * @priv: Pointer to private test information
+ * @return 0 if OK, -ve on error
+ */
+int dm_check_operations(struct dm_test_state *dms, struct device *dev,
+			uint32_t base, struct dm_test_priv *priv);
+
+/**
+ * dm_test_main() - Run all the tests
+ *
+ * This runs all available driver model tests
+ *
+ * @return 0 if OK, -ve on error
+ */
+int dm_test_main(void);
+
+#endif
diff --git a/qemu/roms/u-boot/include/dm/uclass-id.h b/qemu/roms/u-boot/include/dm/uclass-id.h
new file mode 100644
index 000000000..f0e691c18
--- /dev/null
+++ b/qemu/roms/u-boot/include/dm/uclass-id.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _DM_UCLASS_ID_H
+#define _DM_UCLASS_ID_H
+
+/* TODO(sjg@chromium.org): this could be compile-time generated */
+enum uclass_id {
+	/* These are used internally by driver model */
+	UCLASS_ROOT = 0,
+	UCLASS_DEMO,
+	UCLASS_TEST,
+	UCLASS_TEST_FDT,
+
+	/* U-Boot uclasses start here */
+	UCLASS_GPIO,
+
+	UCLASS_COUNT,
+	UCLASS_INVALID = -1,
+};
+
+#endif
diff --git a/qemu/roms/u-boot/include/dm/uclass-internal.h b/qemu/roms/u-boot/include/dm/uclass-internal.h
new file mode 100644
index 000000000..cc65d5259
--- /dev/null
+++ b/qemu/roms/u-boot/include/dm/uclass-internal.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _DM_UCLASS_INTERNAL_H
+#define _DM_UCLASS_INTERNAL_H
+
+/**
+ * uclass_find_device() - Return n-th child of uclass
+ * @id:		Id number of the uclass
+ * @index:	Position of the child in uclass's list
+ * #devp:	Returns pointer to device, or NULL on error
+ *
+ * The device is not prepared for use - this is an internal function
+ *
+ * @return the uclass pointer of a child at the given index or
+ * return NULL on error.
+ */
+int uclass_find_device(enum uclass_id id, int index, struct device **devp);
+
+/**
+ * uclass_bind_device() - Associate device with a uclass
+ *
+ * Connect the device into uclass's list of devices.
+ *
+ * @dev:	Pointer to the device
+ * #return 0 on success, -ve on error
+ */
+int uclass_bind_device(struct device *dev);
+
+/**
+ * uclass_unbind_device() - Deassociate device with a uclass
+ *
+ * Disconnect the device from uclass's list of devices.
+ *
+ * @dev:	Pointer to the device
+ * #return 0 on success, -ve on error
+ */
+int uclass_unbind_device(struct device *dev);
+
+/**
+ * uclass_post_probe_device() - Deal with a device that has just been probed
+ *
+ * Perform any post-processing of a probed device that is needed by the
+ * uclass.
+ *
+ * @dev:	Pointer to the device
+ * #return 0 on success, -ve on error
+ */
+int uclass_post_probe_device(struct device *dev);
+
+/**
+ * uclass_pre_remove_device() - Handle a device which is about to be removed
+ *
+ * Perform any pre-processing of a device that is about to be removed.
+ *
+ * @dev:	Pointer to the device
+ * #return 0 on success, -ve on error
+ */
+int uclass_pre_remove_device(struct device *dev);
+
+/**
+ * uclass_find() - Find uclass by its id
+ *
+ * @id:		Id to serach for
+ * @return pointer to uclass, or NULL if not found
+ */
+struct uclass *uclass_find(enum uclass_id key);
+
+/**
+ * uclass_destroy() - Destroy a uclass
+ *
+ * Destroy a uclass and all its devices
+ *
+ * @uc: uclass to destroy
+ * @return 0 on success, -ve on error
+ */
+int uclass_destroy(struct uclass *uc);
+
+#endif
diff --git a/qemu/roms/u-boot/include/dm/uclass.h b/qemu/roms/u-boot/include/dm/uclass.h
new file mode 100644
index 000000000..cd23cfed1
--- /dev/null
+++ b/qemu/roms/u-boot/include/dm/uclass.h
@@ -0,0 +1,142 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _DM_UCLASS_H
+#define _DM_UCLASS_H
+
+#include <dm/uclass-id.h>
+#include <linux/list.h>
+
+/**
+ * struct uclass - a U-Boot drive class, collecting together similar drivers
+ *
+ * A uclass provides an interface to a particular function, which is
+ * implemented by one or more drivers. Every driver belongs to a uclass even
+ * if it is the only driver in that uclass. An example uclass is GPIO, which
+ * provides the ability to change read inputs, set and clear outputs, etc.
+ * There may be drivers for on-chip SoC GPIO banks, I2C GPIO expanders and
+ * PMIC IO lines, all made available in a unified way through the uclass.
+ *
+ * @priv: Private data for this uclass
+ * @uc_drv: The driver for the uclass itself, not to be confused with a
+ * 'struct driver'
+ * dev_head: List of devices in this uclass (devices are attached to their
+ * uclass when their bind method is called)
+ * @sibling_node: Next uclass in the linked list of uclasses
+ */
+struct uclass {
+	void *priv;
+	struct uclass_driver *uc_drv;
+	struct list_head dev_head;
+	struct list_head sibling_node;
+};
+
+struct device;
+
+/**
+ * struct uclass_driver - Driver for the uclass
+ *
+ * A uclass_driver provides a consistent interface to a set of related
+ * drivers.
+ *
+ * @name: Name of uclass driver
+ * @id: ID number of this uclass
+ * @post_bind: Called after a new device is bound to this uclass
+ * @pre_unbind: Called before a device is unbound from this uclass
+ * @post_probe: Called after a new device is probed
+ * @pre_remove: Called before a device is removed
+ * @init: Called to set up the uclass
+ * @destroy: Called to destroy the uclass
+ * @priv_auto_alloc_size: If non-zero this is the size of the private data
+ * to be allocated in the uclass's ->priv pointer. If zero, then the uclass
+ * driver is responsible for allocating any data required.
+ * @per_device_auto_alloc_size: Each device can hold private data owned
+ * by the uclass. If required this will be automatically allocated if this
+ * value is non-zero.
+ * @ops: Uclass operations, providing the consistent interface to devices
+ * within the uclass.
+ */
+struct uclass_driver {
+	const char *name;
+	enum uclass_id id;
+	int (*post_bind)(struct device *dev);
+	int (*pre_unbind)(struct device *dev);
+	int (*post_probe)(struct device *dev);
+	int (*pre_remove)(struct device *dev);
+	int (*init)(struct uclass *class);
+	int (*destroy)(struct uclass *class);
+	int priv_auto_alloc_size;
+	int per_device_auto_alloc_size;
+	const void *ops;
+};
+
+/* Declare a new uclass_driver */
+#define UCLASS_DRIVER(__name)						\
+	ll_entry_declare(struct uclass_driver, __name, uclass)
+
+/**
+ * uclass_get() - Get a uclass based on an ID, creating it if needed
+ *
+ * Every uclass is identified by an ID, a number from 0 to n-1 where n is
+ * the number of uclasses. This function allows looking up a uclass by its
+ * ID.
+ *
+ * @key: ID to look up
+ * @ucp: Returns pointer to uclass (there is only one per ID)
+ * @return 0 if OK, -ve on error
+ */
+int uclass_get(enum uclass_id key, struct uclass **ucp);
+
+/**
+ * uclass_get_device() - Get a uclass device based on an ID and index
+ *
+ * id: ID to look up
+ * @index: Device number within that uclass (0=first)
+ * @ucp: Returns pointer to uclass (there is only one per for each ID)
+ * @return 0 if OK, -ve on error
+ */
+int uclass_get_device(enum uclass_id id, int index, struct device **ucp);
+
+/**
+ * uclass_first_device() - Get the first device in a uclass
+ *
+ * @id: Uclass ID to look up
+ * @devp: Returns pointer to the first device in that uclass, or NULL if none
+ * @return 0 if OK (found or not found), -1 on error
+ */
+int uclass_first_device(enum uclass_id id, struct device **devp);
+
+/**
+ * uclass_next_device() - Get the next device in a uclass
+ *
+ * @devp: On entry, pointer to device to lookup. On exit, returns pointer
+ * to the next device in the same uclass, or NULL if none
+ * @return 0 if OK (found or not found), -1 on error
+ */
+int uclass_next_device(struct device **devp);
+
+/**
+ * uclass_foreach_dev() - Helper function to iteration through devices
+ *
+ * This creates a for() loop which works through the available devices in
+ * a uclass in order from start to end.
+ *
+ * @pos: struct device * to hold the current device. Set to NULL when there
+ * are no more devices.
+ * uc: uclass to scan
+ */
+#define uclass_foreach_dev(pos, uc)					\
+	for (pos = list_entry((&(uc)->dev_head)->next, typeof(*pos),	\
+			uclass_node);					\
+	     prefetch(pos->uclass_node.next),				\
+			&pos->uclass_node != (&(uc)->dev_head);		\
+	     pos = list_entry(pos->uclass_node.next, typeof(*pos),	\
+			uclass_node))
+
+#endif
diff --git a/qemu/roms/u-boot/include/dm/ut.h b/qemu/roms/u-boot/include/dm/ut.h
new file mode 100644
index 000000000..fa9eac022
--- /dev/null
+++ b/qemu/roms/u-boot/include/dm/ut.h
@@ -0,0 +1,95 @@
+/*
+ * Simple unit test library for driver model
+ *
+ * Copyright (c) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DM_UT_H
+#define __DM_UT_H
+
+struct dm_test_state;
+
+/**
+ * ut_fail() - Record failure of a unit test
+ *
+ * @dms: Test state
+ * @fname: Filename where the error occured
+ * @line: Line number where the error occured
+ * @func: Function name where the error occured
+ * @cond: The condition that failed
+ */
+void ut_fail(struct dm_test_state *dms, const char *fname, int line,
+	     const char *func, const char *cond);
+
+/**
+ * ut_failf() - Record failure of a unit test
+ *
+ * @dms: Test state
+ * @fname: Filename where the error occured
+ * @line: Line number where the error occured
+ * @func: Function name where the error occured
+ * @cond: The condition that failed
+ * @fmt: printf() format string for the error, followed by args
+ */
+void ut_failf(struct dm_test_state *dms, const char *fname, int line,
+	      const char *func, const char *cond, const char *fmt, ...)
+			__attribute__ ((format (__printf__, 6, 7)));
+
+
+/* Assert that a condition is non-zero */
+#define ut_assert(cond)							\
+	if (!(cond)) {							\
+		ut_fail(dms, __FILE__, __LINE__, __func__, #cond);	\
+		return -1;						\
+	}
+
+/* Assert that a condition is non-zero, with printf() string */
+#define ut_assertf(cond, fmt, args...)					\
+	if (!(cond)) {							\
+		ut_failf(dms, __FILE__, __LINE__, __func__, #cond,	\
+			 fmt, ##args);					\
+		return -1;						\
+	}
+
+/* Assert that two int expressions are equal */
+#define ut_asserteq(expr1, expr2) {					\
+	unsigned int val1 = (expr1), val2 = (expr2);			\
+									\
+	if (val1 != val2) {						\
+		ut_failf(dms, __FILE__, __LINE__, __func__,		\
+			 #expr1 " == " #expr2,				\
+			 "Expected %d, got %d", val1, val2);		\
+		return -1;						\
+	}								\
+}
+
+/* Assert that two string expressions are equal */
+#define ut_asserteq_str(expr1, expr2) {					\
+	const char *val1 = (expr1), *val2 = (expr2);			\
+									\
+	if (strcmp(val1, val2)) {					\
+		ut_failf(dms, __FILE__, __LINE__, __func__,		\
+			 #expr1 " = " #expr2,				\
+			 "Expected \"%s\", got \"%s\"", val1, val2);	\
+		return -1;						\
+	}								\
+}
+
+/* Assert that two pointers are equal */
+#define ut_asserteq_ptr(expr1, expr2) {					\
+	const void *val1 = (expr1), *val2 = (expr2);			\
+									\
+	if (val1 != val2) {						\
+		ut_failf(dms, __FILE__, __LINE__, __func__,		\
+			 #expr1 " = " #expr2,				\
+			 "Expected %p, got %p", val1, val2);		\
+		return -1;						\
+	}								\
+}
+
+/* Assert that an operation succeeds (returns 0) */
+#define ut_assertok(cond)	ut_asserteq(0, cond)
+
+#endif
diff --git a/qemu/roms/u-boot/include/dm/util.h b/qemu/roms/u-boot/include/dm/util.h
new file mode 100644
index 000000000..8be64a921
--- /dev/null
+++ b/qemu/roms/u-boot/include/dm/util.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DM_UTIL_H
+
+void dm_warn(const char *fmt, ...);
+
+#ifdef DEBUG
+void dm_dbg(const char *fmt, ...);
+#else
+static inline void dm_dbg(const char *fmt, ...)
+{
+}
+#endif
+
+struct list_head;
+
+/**
+ * list_count_items() - Count number of items in a list
+ *
+ * @param head:		Head of list
+ * @return number of items, or 0 if empty
+ */
+int list_count_items(struct list_head *head);
+
+#endif
diff --git a/qemu/roms/u-boot/include/dm9000.h b/qemu/roms/u-boot/include/dm9000.h
new file mode 100644
index 000000000..42b04fac3
--- /dev/null
+++ b/qemu/roms/u-boot/include/dm9000.h
@@ -0,0 +1,17 @@
+/*
+ * NOTE:        DAVICOM DM9000 ethernet driver interface
+ *
+ * Authors:     Remy Bohmer <linux@bohmer.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __DM9000_H__
+#define __DM9000_H__
+
+/******************  function prototypes **********************/
+#if !defined(CONFIG_DM9000_NO_SROM)
+void dm9000_write_srom_word(int offset, u16 val);
+void dm9000_read_srom_word(int offset, u8 *to);
+#endif
+
+#endif /* __DM9000_H__ */
diff --git a/qemu/roms/u-boot/include/dp83848.h b/qemu/roms/u-boot/include/dp83848.h
new file mode 100644
index 000000000..c74ce0efb
--- /dev/null
+++ b/qemu/roms/u-boot/include/dp83848.h
@@ -0,0 +1,85 @@
+/*
+ * DP83848 ethernet Physical layer
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+
+/* National Semiconductor PHYSICAL LAYER TRANSCEIVER DP83848 */
+
+#define DP83848_CTL_REG		0x0	/* Basic Mode Control Reg */
+#define DP83848_STAT_REG		0x1	/* Basic Mode Status Reg */
+#define DP83848_PHYID1_REG		0x2	/* PHY Idendifier Reg 1 */
+#define DP83848_PHYID2_REG		0x3	/* PHY Idendifier Reg 2 */
+#define DP83848_ANA_REG			0x4	/* Auto_Neg Advt Reg  */
+#define DP83848_ANLPA_REG		0x5	/* Auto_neg Link Partner Ability Reg */
+#define DP83848_ANE_REG			0x6	/* Auto-neg Expansion Reg  */
+#define DP83848_PHY_STAT_REG		0x10	/* PHY Status Register  */
+#define DP83848_PHY_INTR_CTRL_REG	0x11	/* PHY Interrupt Control Register */
+#define DP83848_PHY_CTRL_REG		0x19	/* PHY Status Register  */
+
+/*--Bit definitions: DP83848_CTL_REG */
+#define DP83848_RESET		(1 << 15)  /* 1= S/W Reset */
+#define DP83848_LOOPBACK	(1 << 14)  /* 1=loopback Enabled */
+#define DP83848_SPEED_SELECT	(1 << 13)
+#define DP83848_AUTONEG		(1 << 12)
+#define DP83848_POWER_DOWN	(1 << 11)
+#define DP83848_ISOLATE		(1 << 10)
+#define DP83848_RESTART_AUTONEG	(1 << 9)
+#define DP83848_DUPLEX_MODE	(1 << 8)
+#define DP83848_COLLISION_TEST	(1 << 7)
+
+/*--Bit definitions: DP83848_STAT_REG */
+#define DP83848_100BASE_T4	(1 << 15)
+#define DP83848_100BASE_TX_FD	(1 << 14)
+#define DP83848_100BASE_TX_HD	(1 << 13)
+#define DP83848_10BASE_T_FD	(1 << 12)
+#define DP83848_10BASE_T_HD	(1 << 11)
+#define DP83848_MF_PREAMB_SUPPR	(1 << 6)
+#define DP83848_AUTONEG_COMP	(1 << 5)
+#define DP83848_RMT_FAULT	(1 << 4)
+#define DP83848_AUTONEG_ABILITY	(1 << 3)
+#define DP83848_LINK_STATUS	(1 << 2)
+#define DP83848_JABBER_DETECT	(1 << 1)
+#define DP83848_EXTEND_CAPAB	(1 << 0)
+
+/*--definitions: DP83848_PHYID1 */
+#define DP83848_PHYID1_OUI	0x2000
+#define DP83848_PHYID2_OUI	0x5c90
+
+/*--Bit definitions: DP83848_ANAR, DP83848_ANLPAR */
+#define DP83848_NP		(1 << 15)
+#define DP83848_ACK		(1 << 14)
+#define DP83848_RF		(1 << 13)
+#define DP83848_PAUSE		(1 << 10)
+#define DP83848_T4		(1 << 9)
+#define DP83848_TX_FDX		(1 << 8)
+#define DP83848_TX_HDX		(1 << 7)
+#define DP83848_10_FDX		(1 << 6)
+#define DP83848_10_HDX		(1 << 5)
+#define DP83848_AN_IEEE_802_3	0x0001
+
+/*--Bit definitions: DP83848_ANER */
+#define DP83848_PDF		(1 << 4)
+#define DP83848_LP_NP_ABLE	(1 << 3)
+#define DP83848_NP_ABLE		(1 << 2)
+#define DP83848_PAGE_RX		(1 << 1)
+#define DP83848_LP_AN_ABLE	(1 << 0)
+
+/*--Bit definitions: DP83848_PHY_STAT */
+#define DP83848_RX_ERR_LATCH		(1 << 13)
+#define DP83848_POLARITY_STAT		(1 << 12)
+#define DP83848_FALSE_CAR_SENSE		(1 << 11)
+#define DP83848_SIG_DETECT		(1 << 10)
+#define DP83848_DESCRAM_LOCK		(1 << 9)
+#define DP83848_PAGE_RCV		(1 << 8)
+#define DP83848_PHY_RMT_FAULT		(1 << 6)
+#define DP83848_JABBER			(1 << 5)
+#define DP83848_AUTONEG_COMPLETE	(1 << 4)
+#define DP83848_LOOPBACK_STAT		(1 << 3)
+#define DP83848_DUPLEX			(1 << 2)
+#define DP83848_SPEED			(1 << 1)
+#define DP83848_LINK			(1 << 0)
diff --git a/qemu/roms/u-boot/include/ds1722.h b/qemu/roms/u-boot/include/ds1722.h
new file mode 100644
index 000000000..1b63e86b1
--- /dev/null
+++ b/qemu/roms/u-boot/include/ds1722.h
@@ -0,0 +1,16 @@
+/*
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _DS1722_H_
+#define _DS1722_H_
+
+#define DS1722_RESOLUTION_8BIT	0x0
+#define DS1722_RESOLUTION_9BIT	0x1
+#define DS1722_RESOLUTION_10BIT	0x2
+#define DS1722_RESOLUTION_11BIT	0x3
+#define DS1722_RESOLUTION_12BIT	0x4
+
+int ds1722_probe(int dev);
+
+#endif /* _DS1722_H_ */
diff --git a/qemu/roms/u-boot/include/ds4510.h b/qemu/roms/u-boot/include/ds4510.h
new file mode 100644
index 000000000..40480afc9
--- /dev/null
+++ b/qemu/roms/u-boot/include/ds4510.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __DS4510_H_
+#define __DS4510_H_
+
+/* General defines */
+#define DS4510_NUM_IO				0x04
+#define DS4510_IO_MASK				((1 << DS4510_NUM_IO) - 1)
+#define DS4510_EEPROM_PAGE_WRITE_DELAY_MS	20
+
+/* EEPROM from 0x00 - 0x39 */
+#define DS4510_EEPROM				0x00
+#define DS4510_EEPROM_SIZE			0x40
+#define DS4510_EEPROM_PAGE_SIZE			0x08
+#define DS4510_EEPROM_PAGE_OFFSET(x)	((x) & (DS4510_EEPROM_PAGE_SIZE - 1))
+
+/* SEEPROM from 0xf0 - 0xf7 */
+#define DS4510_SEEPROM				0xf0
+#define DS4510_SEEPROM_SIZE			0x08
+
+/* Registers overlapping SEEPROM from 0xf0 - 0xf7 */
+#define DS4510_PULLUP				0xF0
+#define DS4510_PULLUP_DIS			0x00
+#define DS4510_PULLUP_EN			0x01
+#define DS4510_RSTDELAY				0xF1
+#define DS4510_RSTDELAY_MASK			0x03
+#define DS4510_RSTDELAY_125			0x00
+#define DS4510_RSTDELAY_250			0x01
+#define DS4510_RSTDELAY_500			0x02
+#define DS4510_RSTDELAY_1000			0x03
+#define DS4510_IO3				0xF4
+#define DS4510_IO2				0xF5
+#define DS4510_IO1				0xF6
+#define DS4510_IO0				0xF7
+
+/* Status configuration registers from 0xf8 - 0xf9*/
+#define DS4510_IO_STATUS			0xF8
+#define DS4510_CFG				0xF9
+#define DS4510_CFG_READY			0x80
+#define DS4510_CFG_TRIP_POINT			0x40
+#define DS4510_CFG_RESET			0x20
+#define DS4510_CFG_SEE				0x10
+#define DS4510_CFG_SWRST			0x08
+
+/* SRAM from 0xfa - 0xff */
+#define DS4510_SRAM				0xfa
+#define DS4510_SRAM_SIZE			0x06
+
+int ds4510_mem_write(uint8_t chip, int offset, uint8_t *buf, int count);
+int ds4510_mem_read(uint8_t chip, int offset, uint8_t *buf, int count);
+int ds4510_see_write(uint8_t chip, uint8_t nv);
+int ds4510_rstdelay_write(uint8_t chip, uint8_t delay);
+int ds4510_pullup_write(uint8_t chip, uint8_t val);
+int ds4510_pullup_read(uint8_t chip);
+int ds4510_gpio_write(uint8_t chip, uint8_t val);
+int ds4510_gpio_read(uint8_t chip);
+int ds4510_gpio_read_val(uint8_t chip);
+
+#endif /* __DS4510_H_ */
diff --git a/qemu/roms/u-boot/include/dtt.h b/qemu/roms/u-boot/include/dtt.h
new file mode 100644
index 000000000..058bca4d5
--- /dev/null
+++ b/qemu/roms/u-boot/include/dtt.h
@@ -0,0 +1,46 @@
+/*
+ * (C) Copyright 2001
+ * Erik Theisen,  Wave 7 Optics, etheisen@mindspring.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Digital Thermometers and Thermostats.
+ */
+#ifndef _DTT_H_
+#define _DTT_H_
+
+#if defined(CONFIG_DTT_ADM1021)	|| \
+    defined(CONFIG_DTT_ADT7460)	|| \
+    defined(CONFIG_DTT_DS1621)	|| \
+    defined(CONFIG_DTT_DS1775)	|| \
+    defined(CONFIG_DTT_LM63)	|| \
+    defined(CONFIG_DTT_LM73)	|| \
+    defined(CONFIG_DTT_LM75)	|| \
+    defined(CONFIG_DTT_LM81)
+
+#define CONFIG_DTT				/* We have a DTT */
+
+#ifndef CONFIG_DTT_ADM1021
+#define DTT_COMMERCIAL_MAX_TEMP	70		/* 0 - +70 C */
+#define DTT_INDUSTRIAL_MAX_TEMP	85		/* -40 - +85 C */
+#define DTT_AUTOMOTIVE_MAX_TEMP	105		/* -40 - +105 C */
+
+#ifndef CONFIG_SYS_DTT_MAX_TEMP
+#define CONFIG_SYS_DTT_MAX_TEMP DTT_COMMERCIAL_MAX_TEMP
+#endif
+
+#ifndef CONFIG_SYS_DTT_HYSTERESIS
+#define CONFIG_SYS_DTT_HYSTERESIS	5		/* 5 C */
+#endif
+#endif /* CONFIG_DTT_ADM1021 */
+
+extern void dtt_init(void);
+extern int dtt_init_one(int);
+extern int dtt_read(int sensor, int reg);
+extern int dtt_write(int sensor, int reg, int val);
+extern int dtt_get_temp(int sensor);
+#endif
+
+#endif /* _DTT_H_ */
diff --git a/qemu/roms/u-boot/include/dwmmc.h b/qemu/roms/u-boot/include/dwmmc.h
new file mode 100644
index 000000000..c9bdf51a6
--- /dev/null
+++ b/qemu/roms/u-boot/include/dwmmc.h
@@ -0,0 +1,187 @@
+/*
+ * (C) Copyright 2012 SAMSUNG Electronics
+ * Jaehoon Chung <jh80.chung@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DWMMC_HW_H
+#define __DWMMC_HW_H
+
+#include <asm/io.h>
+#include <mmc.h>
+
+#define DWMCI_CTRL		0x000
+#define	DWMCI_PWREN		0x004
+#define DWMCI_CLKDIV		0x008
+#define DWMCI_CLKSRC		0x00C
+#define DWMCI_CLKENA		0x010
+#define DWMCI_TMOUT		0x014
+#define DWMCI_CTYPE		0x018
+#define DWMCI_BLKSIZ		0x01C
+#define DWMCI_BYTCNT		0x020
+#define DWMCI_INTMASK		0x024
+#define DWMCI_CMDARG		0x028
+#define DWMCI_CMD		0x02C
+#define DWMCI_RESP0		0x030
+#define DWMCI_RESP1		0x034
+#define DWMCI_RESP2		0x038
+#define DWMCI_RESP3		0x03C
+#define DWMCI_MINTSTS		0x040
+#define DWMCI_RINTSTS		0x044
+#define DWMCI_STATUS		0x048
+#define DWMCI_FIFOTH		0x04C
+#define DWMCI_CDETECT		0x050
+#define DWMCI_WRTPRT		0x054
+#define DWMCI_GPIO		0x058
+#define DWMCI_TCMCNT		0x05C
+#define DWMCI_TBBCNT		0x060
+#define DWMCI_DEBNCE		0x064
+#define DWMCI_USRID		0x068
+#define DWMCI_VERID		0x06C
+#define DWMCI_HCON		0x070
+#define DWMCI_UHS_REG		0x074
+#define DWMCI_BMOD		0x080
+#define DWMCI_PLDMND		0x084
+#define DWMCI_DBADDR		0x088
+#define DWMCI_IDSTS		0x08C
+#define DWMCI_IDINTEN		0x090
+#define DWMCI_DSCADDR		0x094
+#define DWMCI_BUFADDR		0x098
+#define DWMCI_DATA		0x200
+
+/* Interrupt Mask register */
+#define DWMCI_INTMSK_ALL	0xffffffff
+#define DWMCI_INTMSK_RE		(1 << 1)
+#define DWMCI_INTMSK_CDONE	(1 << 2)
+#define DWMCI_INTMSK_DTO	(1 << 3)
+#define DWMCI_INTMSK_TXDR	(1 << 4)
+#define DWMCI_INTMSK_RXDR	(1 << 5)
+#define DWMCI_INTMSK_DCRC	(1 << 7)
+#define DWMCI_INTMSK_RTO	(1 << 8)
+#define DWMCI_INTMSK_DRTO	(1 << 9)
+#define DWMCI_INTMSK_HTO	(1 << 10)
+#define DWMCI_INTMSK_FRUN	(1 << 11)
+#define DWMCI_INTMSK_HLE	(1 << 12)
+#define DWMCI_INTMSK_SBE	(1 << 13)
+#define DWMCI_INTMSK_ACD	(1 << 14)
+#define DWMCI_INTMSK_EBE	(1 << 15)
+
+/* Raw interrupt Regsiter */
+#define DWMCI_DATA_ERR	(DWMCI_INTMSK_EBE | DWMCI_INTMSK_SBE | DWMCI_INTMSK_HLE |\
+			DWMCI_INTMSK_FRUN | DWMCI_INTMSK_EBE | DWMCI_INTMSK_DCRC)
+#define DWMCI_DATA_TOUT	(DWMCI_INTMSK_HTO | DWMCI_INTMSK_DRTO)
+/* CTRL register */
+#define DWMCI_CTRL_RESET	(1 << 0)
+#define DWMCI_CTRL_FIFO_RESET	(1 << 1)
+#define DWMCI_CTRL_DMA_RESET	(1 << 2)
+#define DWMCI_DMA_EN		(1 << 5)
+#define DWMCI_CTRL_SEND_AS_CCSD	(1 << 10)
+#define DWMCI_IDMAC_EN		(1 << 25)
+#define DWMCI_RESET_ALL		(DWMCI_CTRL_RESET | DWMCI_CTRL_FIFO_RESET |\
+				DWMCI_CTRL_DMA_RESET)
+
+/* CMD register */
+#define DWMCI_CMD_RESP_EXP	(1 << 6)
+#define DWMCI_CMD_RESP_LENGTH	(1 << 7)
+#define DWMCI_CMD_CHECK_CRC	(1 << 8)
+#define DWMCI_CMD_DATA_EXP	(1 << 9)
+#define DWMCI_CMD_RW		(1 << 10)
+#define DWMCI_CMD_SEND_STOP	(1 << 12)
+#define DWMCI_CMD_ABORT_STOP	(1 << 14)
+#define DWMCI_CMD_PRV_DAT_WAIT	(1 << 13)
+#define DWMCI_CMD_UPD_CLK	(1 << 21)
+#define DWMCI_CMD_USE_HOLD_REG	(1 << 29)
+#define DWMCI_CMD_START		(1 << 31)
+
+/* CLKENA register */
+#define DWMCI_CLKEN_ENABLE	(1 << 0)
+#define DWMCI_CLKEN_LOW_PWR	(1 << 16)
+
+/* Card-type registe */
+#define DWMCI_CTYPE_1BIT	0
+#define DWMCI_CTYPE_4BIT	(1 << 0)
+#define DWMCI_CTYPE_8BIT	(1 << 16)
+
+/* Status Register */
+#define DWMCI_BUSY		(1 << 9)
+
+/* FIFOTH Register */
+#define MSIZE(x)		((x) << 28)
+#define RX_WMARK(x)		((x) << 16)
+#define TX_WMARK(x)		(x)
+#define RX_WMARK_SHIFT		16
+#define RX_WMARK_MASK		(0xfff << RX_WMARK_SHIFT)
+
+#define DWMCI_IDMAC_OWN		(1 << 31)
+#define DWMCI_IDMAC_CH		(1 << 4)
+#define DWMCI_IDMAC_FS		(1 << 3)
+#define DWMCI_IDMAC_LD		(1 << 2)
+
+/*  Bus Mode Register */
+#define DWMCI_BMOD_IDMAC_RESET	(1 << 0)
+#define DWMCI_BMOD_IDMAC_FB	(1 << 1)
+#define DWMCI_BMOD_IDMAC_EN	(1 << 7)
+
+/* quirks */
+#define DWMCI_QUIRK_DISABLE_SMU		(1 << 0)
+
+struct dwmci_host {
+	char *name;
+	void *ioaddr;
+	unsigned int quirks;
+	unsigned int caps;
+	unsigned int version;
+	unsigned int clock;
+	unsigned int bus_hz;
+	int dev_index;
+	int buswidth;
+	u32 clksel_val;
+	u32 fifoth_val;
+	struct mmc *mmc;
+
+	void (*clksel)(struct dwmci_host *host);
+	void (*board_init)(struct dwmci_host *host);
+	unsigned int (*get_mmc_clk)(struct dwmci_host *host);
+
+	struct mmc_config cfg;
+};
+
+struct dwmci_idmac {
+	u32 flags;
+	u32 cnt;
+	u32 addr;
+	u32 next_addr;
+};
+
+static inline void dwmci_writel(struct dwmci_host *host, int reg, u32 val)
+{
+	writel(val, host->ioaddr + reg);
+}
+
+static inline void dwmci_writew(struct dwmci_host *host, int reg, u16 val)
+{
+	writew(val, host->ioaddr + reg);
+}
+
+static inline void dwmci_writeb(struct dwmci_host *host, int reg, u8 val)
+{
+	writeb(val, host->ioaddr + reg);
+}
+static inline u32 dwmci_readl(struct dwmci_host *host, int reg)
+{
+	return readl(host->ioaddr + reg);
+}
+
+static inline u16 dwmci_readw(struct dwmci_host *host, int reg)
+{
+	return readw(host->ioaddr + reg);
+}
+
+static inline u8 dwmci_readb(struct dwmci_host *host, int reg)
+{
+	return readb(host->ioaddr + reg);
+}
+
+int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk);
+#endif	/* __DWMMC_HW_H */
diff --git a/qemu/roms/u-boot/include/e500.h b/qemu/roms/u-boot/include/e500.h
new file mode 100644
index 000000000..5884a224d
--- /dev/null
+++ b/qemu/roms/u-boot/include/e500.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright 2003 Motorola,Inc.
+ * Xianghua Xiao(x.xiao@motorola.com)
+ */
+
+#ifndef	__E500_H__
+#define __E500_H__
+
+#ifndef __ASSEMBLY__
+
+typedef struct
+{
+	unsigned long freq_processor[CONFIG_MAX_CPUS];
+	unsigned long freq_systembus;
+	unsigned long freq_ddrbus;
+	unsigned long freq_localbus;
+	unsigned long freq_qe;
+#ifdef CONFIG_SYS_DPAA_FMAN
+	unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
+#endif
+#ifdef CONFIG_SYS_DPAA_QBMAN
+	unsigned long freq_qman;
+#endif
+#ifdef CONFIG_SYS_DPAA_PME
+	unsigned long freq_pme;
+#endif
+#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+	unsigned char diff_sysclk;
+#endif
+} MPC85xx_SYS_INFO;
+
+#endif  /* _ASMLANGUAGE */
+
+#define RESET_VECTOR	0xfffffffc
+
+#endif	/* __E500_H__ */
diff --git a/qemu/roms/u-boot/include/ec_commands.h b/qemu/roms/u-boot/include/ec_commands.h
new file mode 100644
index 000000000..78baab164
--- /dev/null
+++ b/qemu/roms/u-boot/include/ec_commands.h
@@ -0,0 +1,1700 @@
+/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Host communication command constants for Chrome EC */
+
+#ifndef __CROS_EC_COMMANDS_H
+#define __CROS_EC_COMMANDS_H
+
+/*
+ * Protocol overview
+ *
+ * request:  CMD [ P0 P1 P2 ... Pn S ]
+ * response: ERR [ P0 P1 P2 ... Pn S ]
+ *
+ * where the bytes are defined as follow :
+ *      - CMD is the command code. (defined by EC_CMD_ constants)
+ *      - ERR is the error code. (defined by EC_RES_ constants)
+ *      - Px is the optional payload.
+ *        it is not sent if the error code is not success.
+ *        (defined by ec_params_ and ec_response_ structures)
+ *      - S is the checksum which is the sum of all payload bytes.
+ *
+ * On LPC, CMD and ERR are sent/received at EC_LPC_ADDR_KERNEL|USER_CMD
+ * and the payloads are sent/received at EC_LPC_ADDR_KERNEL|USER_PARAM.
+ * On I2C, all bytes are sent serially in the same message.
+ */
+
+/* Current version of this protocol */
+#define EC_PROTO_VERSION          0x00000002
+
+/* Command version mask */
+#define EC_VER_MASK(version) (1UL << (version))
+
+/* I/O addresses for ACPI commands */
+#define EC_LPC_ADDR_ACPI_DATA  0x62
+#define EC_LPC_ADDR_ACPI_CMD   0x66
+
+/* I/O addresses for host command */
+#define EC_LPC_ADDR_HOST_DATA  0x200
+#define EC_LPC_ADDR_HOST_CMD   0x204
+
+/* I/O addresses for host command args and params */
+/* Protocol version 2 */
+#define EC_LPC_ADDR_HOST_ARGS    0x800  /* And 0x801, 0x802, 0x803 */
+#define EC_LPC_ADDR_HOST_PARAM   0x804  /* For version 2 params; size is
+					 * EC_PROTO2_MAX_PARAM_SIZE */
+/* Protocol version 3 */
+#define EC_LPC_ADDR_HOST_PACKET  0x800  /* Offset of version 3 packet */
+#define EC_LPC_HOST_PACKET_SIZE  0x100  /* Max size of version 3 packet */
+
+/* The actual block is 0x800-0x8ff, but some BIOSes think it's 0x880-0x8ff
+ * and they tell the kernel that so we have to think of it as two parts. */
+#define EC_HOST_CMD_REGION0    0x800
+#define EC_HOST_CMD_REGION1    0x880
+#define EC_HOST_CMD_REGION_SIZE 0x80
+
+/* EC command register bit functions */
+#define EC_LPC_CMDR_DATA	(1 << 0)  /* Data ready for host to read */
+#define EC_LPC_CMDR_PENDING	(1 << 1)  /* Write pending to EC */
+#define EC_LPC_CMDR_BUSY	(1 << 2)  /* EC is busy processing a command */
+#define EC_LPC_CMDR_CMD		(1 << 3)  /* Last host write was a command */
+#define EC_LPC_CMDR_ACPI_BRST	(1 << 4)  /* Burst mode (not used) */
+#define EC_LPC_CMDR_SCI		(1 << 5)  /* SCI event is pending */
+#define EC_LPC_CMDR_SMI		(1 << 6)  /* SMI event is pending */
+
+#define EC_LPC_ADDR_MEMMAP       0x900
+#define EC_MEMMAP_SIZE         255 /* ACPI IO buffer max is 255 bytes */
+#define EC_MEMMAP_TEXT_MAX     8   /* Size of a string in the memory map */
+
+/* The offset address of each type of data in mapped memory. */
+#define EC_MEMMAP_TEMP_SENSOR      0x00 /* Temp sensors */
+#define EC_MEMMAP_FAN              0x10 /* Fan speeds */
+#define EC_MEMMAP_TEMP_SENSOR_B    0x18 /* Temp sensors (second set) */
+#define EC_MEMMAP_ID               0x20 /* 'E' 'C' */
+#define EC_MEMMAP_ID_VERSION       0x22 /* Version of data in 0x20 - 0x2f */
+#define EC_MEMMAP_THERMAL_VERSION  0x23 /* Version of data in 0x00 - 0x1f */
+#define EC_MEMMAP_BATTERY_VERSION  0x24 /* Version of data in 0x40 - 0x7f */
+#define EC_MEMMAP_SWITCHES_VERSION 0x25 /* Version of data in 0x30 - 0x33 */
+#define EC_MEMMAP_EVENTS_VERSION   0x26 /* Version of data in 0x34 - 0x3f */
+#define EC_MEMMAP_HOST_CMD_FLAGS   0x27 /* Host command interface flags */
+#define EC_MEMMAP_SWITCHES         0x30
+#define EC_MEMMAP_HOST_EVENTS      0x34
+#define EC_MEMMAP_BATT_VOLT        0x40 /* Battery Present Voltage */
+#define EC_MEMMAP_BATT_RATE        0x44 /* Battery Present Rate */
+#define EC_MEMMAP_BATT_CAP         0x48 /* Battery Remaining Capacity */
+#define EC_MEMMAP_BATT_FLAG        0x4c /* Battery State, defined below */
+#define EC_MEMMAP_BATT_DCAP        0x50 /* Battery Design Capacity */
+#define EC_MEMMAP_BATT_DVLT        0x54 /* Battery Design Voltage */
+#define EC_MEMMAP_BATT_LFCC        0x58 /* Battery Last Full Charge Capacity */
+#define EC_MEMMAP_BATT_CCNT        0x5c /* Battery Cycle Count */
+#define EC_MEMMAP_BATT_MFGR        0x60 /* Battery Manufacturer String */
+#define EC_MEMMAP_BATT_MODEL       0x68 /* Battery Model Number String */
+#define EC_MEMMAP_BATT_SERIAL      0x70 /* Battery Serial Number String */
+#define EC_MEMMAP_BATT_TYPE        0x78 /* Battery Type String */
+
+/* Number of temp sensors at EC_MEMMAP_TEMP_SENSOR */
+#define EC_TEMP_SENSOR_ENTRIES     16
+/*
+ * Number of temp sensors at EC_MEMMAP_TEMP_SENSOR_B.
+ *
+ * Valid only if EC_MEMMAP_THERMAL_VERSION returns >= 2.
+ */
+#define EC_TEMP_SENSOR_B_ENTRIES      8
+#define EC_TEMP_SENSOR_NOT_PRESENT    0xff
+#define EC_TEMP_SENSOR_ERROR          0xfe
+#define EC_TEMP_SENSOR_NOT_POWERED    0xfd
+#define EC_TEMP_SENSOR_NOT_CALIBRATED 0xfc
+/*
+ * The offset of temperature value stored in mapped memory.  This allows
+ * reporting a temperature range of 200K to 454K = -73C to 181C.
+ */
+#define EC_TEMP_SENSOR_OFFSET      200
+
+#define EC_FAN_SPEED_ENTRIES       4       /* Number of fans at EC_MEMMAP_FAN */
+#define EC_FAN_SPEED_NOT_PRESENT   0xffff  /* Entry not present */
+#define EC_FAN_SPEED_STALLED       0xfffe  /* Fan stalled */
+
+/* Battery bit flags at EC_MEMMAP_BATT_FLAG. */
+#define EC_BATT_FLAG_AC_PRESENT   0x01
+#define EC_BATT_FLAG_BATT_PRESENT 0x02
+#define EC_BATT_FLAG_DISCHARGING  0x04
+#define EC_BATT_FLAG_CHARGING     0x08
+#define EC_BATT_FLAG_LEVEL_CRITICAL 0x10
+
+/* Switch flags at EC_MEMMAP_SWITCHES */
+#define EC_SWITCH_LID_OPEN               0x01
+#define EC_SWITCH_POWER_BUTTON_PRESSED   0x02
+#define EC_SWITCH_WRITE_PROTECT_DISABLED 0x04
+/* Was recovery requested via keyboard; now unused. */
+#define EC_SWITCH_IGNORE1		 0x08
+/* Recovery requested via dedicated signal (from servo board) */
+#define EC_SWITCH_DEDICATED_RECOVERY     0x10
+/* Was fake developer mode switch; now unused.  Remove in next refactor. */
+#define EC_SWITCH_IGNORE0                0x20
+
+/* Host command interface flags */
+/* Host command interface supports LPC args (LPC interface only) */
+#define EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED  0x01
+/* Host command interface supports version 3 protocol */
+#define EC_HOST_CMD_FLAG_VERSION_3   0x02
+
+/* Wireless switch flags */
+#define EC_WIRELESS_SWITCH_WLAN      0x01
+#define EC_WIRELESS_SWITCH_BLUETOOTH 0x02
+#define EC_WIRELESS_SWITCH_WWAN      0x04
+
+/*
+ * This header file is used in coreboot both in C and ACPI code.  The ACPI code
+ * is pre-processed to handle constants but the ASL compiler is unable to
+ * handle actual C code so keep it separate.
+ */
+#ifndef __ACPI__
+
+/*
+ * Define __packed if someone hasn't beat us to it.  Linux kernel style
+ * checking prefers __packed over __attribute__((packed)).
+ */
+#ifndef __packed
+#define __packed __attribute__((packed))
+#endif
+
+/* LPC command status byte masks */
+/* EC has written a byte in the data register and host hasn't read it yet */
+#define EC_LPC_STATUS_TO_HOST     0x01
+/* Host has written a command/data byte and the EC hasn't read it yet */
+#define EC_LPC_STATUS_FROM_HOST   0x02
+/* EC is processing a command */
+#define EC_LPC_STATUS_PROCESSING  0x04
+/* Last write to EC was a command, not data */
+#define EC_LPC_STATUS_LAST_CMD    0x08
+/* EC is in burst mode.  Unsupported by Chrome EC, so this bit is never set */
+#define EC_LPC_STATUS_BURST_MODE  0x10
+/* SCI event is pending (requesting SCI query) */
+#define EC_LPC_STATUS_SCI_PENDING 0x20
+/* SMI event is pending (requesting SMI query) */
+#define EC_LPC_STATUS_SMI_PENDING 0x40
+/* (reserved) */
+#define EC_LPC_STATUS_RESERVED    0x80
+
+/*
+ * EC is busy.  This covers both the EC processing a command, and the host has
+ * written a new command but the EC hasn't picked it up yet.
+ */
+#define EC_LPC_STATUS_BUSY_MASK \
+	(EC_LPC_STATUS_FROM_HOST | EC_LPC_STATUS_PROCESSING)
+
+/* Host command response codes */
+enum ec_status {
+	EC_RES_SUCCESS = 0,
+	EC_RES_INVALID_COMMAND = 1,
+	EC_RES_ERROR = 2,
+	EC_RES_INVALID_PARAM = 3,
+	EC_RES_ACCESS_DENIED = 4,
+	EC_RES_INVALID_RESPONSE = 5,
+	EC_RES_INVALID_VERSION = 6,
+	EC_RES_INVALID_CHECKSUM = 7,
+	EC_RES_IN_PROGRESS = 8,		/* Accepted, command in progress */
+	EC_RES_UNAVAILABLE = 9,		/* No response available */
+	EC_RES_TIMEOUT = 10,		/* We got a timeout */
+	EC_RES_OVERFLOW = 11,		/* Table / data overflow */
+	EC_RES_INVALID_HEADER = 12,     /* Header contains invalid data */
+	EC_RES_REQUEST_TRUNCATED = 13,  /* Didn't get the entire request */
+	EC_RES_RESPONSE_TOO_BIG = 14    /* Response was too big to handle */
+};
+
+/*
+ * Host event codes.  Note these are 1-based, not 0-based, because ACPI query
+ * EC command uses code 0 to mean "no event pending".  We explicitly specify
+ * each value in the enum listing so they won't change if we delete/insert an
+ * item or rearrange the list (it needs to be stable across platforms, not
+ * just within a single compiled instance).
+ */
+enum host_event_code {
+	EC_HOST_EVENT_LID_CLOSED = 1,
+	EC_HOST_EVENT_LID_OPEN = 2,
+	EC_HOST_EVENT_POWER_BUTTON = 3,
+	EC_HOST_EVENT_AC_CONNECTED = 4,
+	EC_HOST_EVENT_AC_DISCONNECTED = 5,
+	EC_HOST_EVENT_BATTERY_LOW = 6,
+	EC_HOST_EVENT_BATTERY_CRITICAL = 7,
+	EC_HOST_EVENT_BATTERY = 8,
+	EC_HOST_EVENT_THERMAL_THRESHOLD = 9,
+	EC_HOST_EVENT_THERMAL_OVERLOAD = 10,
+	EC_HOST_EVENT_THERMAL = 11,
+	EC_HOST_EVENT_USB_CHARGER = 12,
+	EC_HOST_EVENT_KEY_PRESSED = 13,
+	/*
+	 * EC has finished initializing the host interface.  The host can check
+	 * for this event following sending a EC_CMD_REBOOT_EC command to
+	 * determine when the EC is ready to accept subsequent commands.
+	 */
+	EC_HOST_EVENT_INTERFACE_READY = 14,
+	/* Keyboard recovery combo has been pressed */
+	EC_HOST_EVENT_KEYBOARD_RECOVERY = 15,
+
+	/* Shutdown due to thermal overload */
+	EC_HOST_EVENT_THERMAL_SHUTDOWN = 16,
+	/* Shutdown due to battery level too low */
+	EC_HOST_EVENT_BATTERY_SHUTDOWN = 17,
+
+	/*
+	 * The high bit of the event mask is not used as a host event code.  If
+	 * it reads back as set, then the entire event mask should be
+	 * considered invalid by the host.  This can happen when reading the
+	 * raw event status via EC_MEMMAP_HOST_EVENTS but the LPC interface is
+	 * not initialized on the EC, or improperly configured on the host.
+	 */
+	EC_HOST_EVENT_INVALID = 32
+};
+/* Host event mask */
+#define EC_HOST_EVENT_MASK(event_code) (1UL << ((event_code) - 1))
+
+/* Arguments at EC_LPC_ADDR_HOST_ARGS */
+struct ec_lpc_host_args {
+	uint8_t flags;
+	uint8_t command_version;
+	uint8_t data_size;
+	/*
+	 * Checksum; sum of command + flags + command_version + data_size +
+	 * all params/response data bytes.
+	 */
+	uint8_t checksum;
+} __packed;
+
+/* Flags for ec_lpc_host_args.flags */
+/*
+ * Args are from host.  Data area at EC_LPC_ADDR_HOST_PARAM contains command
+ * params.
+ *
+ * If EC gets a command and this flag is not set, this is an old-style command.
+ * Command version is 0 and params from host are at EC_LPC_ADDR_OLD_PARAM with
+ * unknown length.  EC must respond with an old-style response (that is,
+ * withouth setting EC_HOST_ARGS_FLAG_TO_HOST).
+ */
+#define EC_HOST_ARGS_FLAG_FROM_HOST 0x01
+/*
+ * Args are from EC.  Data area at EC_LPC_ADDR_HOST_PARAM contains response.
+ *
+ * If EC responds to a command and this flag is not set, this is an old-style
+ * response.  Command version is 0 and response data from EC is at
+ * EC_LPC_ADDR_OLD_PARAM with unknown length.
+ */
+#define EC_HOST_ARGS_FLAG_TO_HOST   0x02
+
+/*****************************************************************************/
+
+/*
+ * Protocol version 2 for I2C and SPI send a request this way:
+ *
+ *	0	EC_CMD_VERSION0 + (command version)
+ *	1	Command number
+ *	2	Length of params = N
+ *	3..N+2	Params, if any
+ *	N+3	8-bit checksum of bytes 0..N+2
+ *
+ * The corresponding response is:
+ *
+ *	0	Result code (EC_RES_*)
+ *	1	Length of params = M
+ *	2..M+1	Params, if any
+ *	M+2	8-bit checksum of bytes 0..M+1
+ */
+#define EC_PROTO2_REQUEST_HEADER_BYTES 3
+#define EC_PROTO2_REQUEST_TRAILER_BYTES 1
+#define EC_PROTO2_REQUEST_OVERHEAD (EC_PROTO2_REQUEST_HEADER_BYTES +	\
+				    EC_PROTO2_REQUEST_TRAILER_BYTES)
+
+#define EC_PROTO2_RESPONSE_HEADER_BYTES 2
+#define EC_PROTO2_RESPONSE_TRAILER_BYTES 1
+#define EC_PROTO2_RESPONSE_OVERHEAD (EC_PROTO2_RESPONSE_HEADER_BYTES +	\
+				     EC_PROTO2_RESPONSE_TRAILER_BYTES)
+
+/* Parameter length was limited by the LPC interface */
+#define EC_PROTO2_MAX_PARAM_SIZE 0xfc
+
+/* Maximum request and response packet sizes for protocol version 2 */
+#define EC_PROTO2_MAX_REQUEST_SIZE (EC_PROTO2_REQUEST_OVERHEAD +	\
+				    EC_PROTO2_MAX_PARAM_SIZE)
+#define EC_PROTO2_MAX_RESPONSE_SIZE (EC_PROTO2_RESPONSE_OVERHEAD +	\
+				     EC_PROTO2_MAX_PARAM_SIZE)
+
+/*****************************************************************************/
+
+/*
+ * Value written to legacy command port / prefix byte to indicate protocol
+ * 3+ structs are being used.  Usage is bus-dependent.
+ */
+#define EC_COMMAND_PROTOCOL_3 0xda
+
+#define EC_HOST_REQUEST_VERSION 3
+
+/* Version 3 request from host */
+struct ec_host_request {
+	/* Struct version (=3)
+	 *
+	 * EC will return EC_RES_INVALID_HEADER if it receives a header with a
+	 * version it doesn't know how to parse.
+	 */
+	uint8_t struct_version;
+
+	/*
+	 * Checksum of request and data; sum of all bytes including checksum
+	 * should total to 0.
+	 */
+	uint8_t checksum;
+
+	/* Command code */
+	uint16_t command;
+
+	/* Command version */
+	uint8_t command_version;
+
+	/* Unused byte in current protocol version; set to 0 */
+	uint8_t reserved;
+
+	/* Length of data which follows this header */
+	uint16_t data_len;
+} __packed;
+
+#define EC_HOST_RESPONSE_VERSION 3
+
+/* Version 3 response from EC */
+struct ec_host_response {
+	/* Struct version (=3) */
+	uint8_t struct_version;
+
+	/*
+	 * Checksum of response and data; sum of all bytes including checksum
+	 * should total to 0.
+	 */
+	uint8_t checksum;
+
+	/* Result code (EC_RES_*) */
+	uint16_t result;
+
+	/* Length of data which follows this header */
+	uint16_t data_len;
+
+	/* Unused bytes in current protocol version; set to 0 */
+	uint16_t reserved;
+} __packed;
+
+/*****************************************************************************/
+/*
+ * Notes on commands:
+ *
+ * Each command is an 8-byte command value.  Commands which take params or
+ * return response data specify structs for that data.  If no struct is
+ * specified, the command does not input or output data, respectively.
+ * Parameter/response length is implicit in the structs.  Some underlying
+ * communication protocols (I2C, SPI) may add length or checksum headers, but
+ * those are implementation-dependent and not defined here.
+ */
+
+/*****************************************************************************/
+/* General / test commands */
+
+/*
+ * Get protocol version, used to deal with non-backward compatible protocol
+ * changes.
+ */
+#define EC_CMD_PROTO_VERSION 0x00
+
+struct ec_response_proto_version {
+	uint32_t version;
+} __packed;
+
+/*
+ * Hello.  This is a simple command to test the EC is responsive to
+ * commands.
+ */
+#define EC_CMD_HELLO 0x01
+
+struct ec_params_hello {
+	uint32_t in_data;  /* Pass anything here */
+} __packed;
+
+struct ec_response_hello {
+	uint32_t out_data;  /* Output will be in_data + 0x01020304 */
+} __packed;
+
+/* Get version number */
+#define EC_CMD_GET_VERSION 0x02
+
+enum ec_current_image {
+	EC_IMAGE_UNKNOWN = 0,
+	EC_IMAGE_RO,
+	EC_IMAGE_RW
+};
+
+struct ec_response_get_version {
+	/* Null-terminated version strings for RO, RW */
+	char version_string_ro[32];
+	char version_string_rw[32];
+	char reserved[32];       /* Was previously RW-B string */
+	uint32_t current_image;  /* One of ec_current_image */
+} __packed;
+
+/* Read test */
+#define EC_CMD_READ_TEST 0x03
+
+struct ec_params_read_test {
+	uint32_t offset;   /* Starting value for read buffer */
+	uint32_t size;     /* Size to read in bytes */
+} __packed;
+
+struct ec_response_read_test {
+	uint32_t data[32];
+} __packed;
+
+/*
+ * Get build information
+ *
+ * Response is null-terminated string.
+ */
+#define EC_CMD_GET_BUILD_INFO 0x04
+
+/* Get chip info */
+#define EC_CMD_GET_CHIP_INFO 0x05
+
+struct ec_response_get_chip_info {
+	/* Null-terminated strings */
+	char vendor[32];
+	char name[32];
+	char revision[32];  /* Mask version */
+} __packed;
+
+/* Get board HW version */
+#define EC_CMD_GET_BOARD_VERSION 0x06
+
+struct ec_response_board_version {
+	uint16_t board_version;  /* A monotonously incrementing number. */
+} __packed;
+
+/*
+ * Read memory-mapped data.
+ *
+ * This is an alternate interface to memory-mapped data for bus protocols
+ * which don't support direct-mapped memory - I2C, SPI, etc.
+ *
+ * Response is params.size bytes of data.
+ */
+#define EC_CMD_READ_MEMMAP 0x07
+
+struct ec_params_read_memmap {
+	uint8_t offset;   /* Offset in memmap (EC_MEMMAP_*) */
+	uint8_t size;     /* Size to read in bytes */
+} __packed;
+
+/* Read versions supported for a command */
+#define EC_CMD_GET_CMD_VERSIONS 0x08
+
+struct ec_params_get_cmd_versions {
+	uint8_t cmd;      /* Command to check */
+} __packed;
+
+struct ec_response_get_cmd_versions {
+	/*
+	 * Mask of supported versions; use EC_VER_MASK() to compare with a
+	 * desired version.
+	 */
+	uint32_t version_mask;
+} __packed;
+
+/*
+ * Check EC communcations status (busy). This is needed on i2c/spi but not
+ * on lpc since it has its own out-of-band busy indicator.
+ *
+ * lpc must read the status from the command register. Attempting this on
+ * lpc will overwrite the args/parameter space and corrupt its data.
+ */
+#define EC_CMD_GET_COMMS_STATUS		0x09
+
+/* Avoid using ec_status which is for return values */
+enum ec_comms_status {
+	EC_COMMS_STATUS_PROCESSING	= 1 << 0,	/* Processing cmd */
+};
+
+struct ec_response_get_comms_status {
+	uint32_t flags;		/* Mask of enum ec_comms_status */
+} __packed;
+
+/*
+ * Fake a variety of responses, purely for testing purposes.
+ * FIXME: Would be nice to force checksum errors.
+ */
+#define EC_CMD_TEST_PROTOCOL		0x0a
+
+/* Tell the EC what to send back to us. */
+struct ec_params_test_protocol {
+	uint32_t ec_result;
+	uint32_t ret_len;
+	uint8_t buf[32];
+} __packed;
+
+/* Here it comes... */
+struct ec_response_test_protocol {
+	uint8_t buf[32];
+} __packed;
+
+/* Get prococol information */
+#define EC_CMD_GET_PROTOCOL_INFO	0x0b
+
+/* Flags for ec_response_get_protocol_info.flags */
+/* EC_RES_IN_PROGRESS may be returned if a command is slow */
+#define EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED (1 << 0)
+
+struct ec_response_get_protocol_info {
+	/* Fields which exist if at least protocol version 3 supported */
+
+	/* Bitmask of protocol versions supported (1 << n means version n)*/
+	uint32_t protocol_versions;
+
+	/* Maximum request packet size, in bytes */
+	uint16_t max_request_packet_size;
+
+	/* Maximum response packet size, in bytes */
+	uint16_t max_response_packet_size;
+
+	/* Flags; see EC_PROTOCOL_INFO_* */
+	uint32_t flags;
+} __packed;
+
+/*****************************************************************************/
+/* Flash commands */
+
+/* Get flash info */
+#define EC_CMD_FLASH_INFO 0x10
+
+struct ec_response_flash_info {
+	/* Usable flash size, in bytes */
+	uint32_t flash_size;
+	/*
+	 * Write block size.  Write offset and size must be a multiple
+	 * of this.
+	 */
+	uint32_t write_block_size;
+	/*
+	 * Erase block size.  Erase offset and size must be a multiple
+	 * of this.
+	 */
+	uint32_t erase_block_size;
+	/*
+	 * Protection block size.  Protection offset and size must be a
+	 * multiple of this.
+	 */
+	uint32_t protect_block_size;
+} __packed;
+
+/*
+ * Read flash
+ *
+ * Response is params.size bytes of data.
+ */
+#define EC_CMD_FLASH_READ 0x11
+
+struct ec_params_flash_read {
+	uint32_t offset;   /* Byte offset to read */
+	uint32_t size;     /* Size to read in bytes */
+} __packed;
+
+/* Write flash */
+#define EC_CMD_FLASH_WRITE 0x12
+#define EC_VER_FLASH_WRITE 1
+
+/* Version 0 of the flash command supported only 64 bytes of data */
+#define EC_FLASH_WRITE_VER0_SIZE 64
+
+struct ec_params_flash_write {
+	uint32_t offset;   /* Byte offset to write */
+	uint32_t size;     /* Size to write in bytes */
+	/* Followed by data to write */
+} __packed;
+
+/* Erase flash */
+#define EC_CMD_FLASH_ERASE 0x13
+
+struct ec_params_flash_erase {
+	uint32_t offset;   /* Byte offset to erase */
+	uint32_t size;     /* Size to erase in bytes */
+} __packed;
+
+/*
+ * Get/set flash protection.
+ *
+ * If mask!=0, sets/clear the requested bits of flags.  Depending on the
+ * firmware write protect GPIO, not all flags will take effect immediately;
+ * some flags require a subsequent hard reset to take effect.  Check the
+ * returned flags bits to see what actually happened.
+ *
+ * If mask=0, simply returns the current flags state.
+ */
+#define EC_CMD_FLASH_PROTECT 0x15
+#define EC_VER_FLASH_PROTECT 1  /* Command version 1 */
+
+/* Flags for flash protection */
+/* RO flash code protected when the EC boots */
+#define EC_FLASH_PROTECT_RO_AT_BOOT         (1 << 0)
+/*
+ * RO flash code protected now.  If this bit is set, at-boot status cannot
+ * be changed.
+ */
+#define EC_FLASH_PROTECT_RO_NOW             (1 << 1)
+/* Entire flash code protected now, until reboot. */
+#define EC_FLASH_PROTECT_ALL_NOW            (1 << 2)
+/* Flash write protect GPIO is asserted now */
+#define EC_FLASH_PROTECT_GPIO_ASSERTED      (1 << 3)
+/* Error - at least one bank of flash is stuck locked, and cannot be unlocked */
+#define EC_FLASH_PROTECT_ERROR_STUCK        (1 << 4)
+/*
+ * Error - flash protection is in inconsistent state.  At least one bank of
+ * flash which should be protected is not protected.  Usually fixed by
+ * re-requesting the desired flags, or by a hard reset if that fails.
+ */
+#define EC_FLASH_PROTECT_ERROR_INCONSISTENT (1 << 5)
+/* Entile flash code protected when the EC boots */
+#define EC_FLASH_PROTECT_ALL_AT_BOOT        (1 << 6)
+
+struct ec_params_flash_protect {
+	uint32_t mask;   /* Bits in flags to apply */
+	uint32_t flags;  /* New flags to apply */
+} __packed;
+
+struct ec_response_flash_protect {
+	/* Current value of flash protect flags */
+	uint32_t flags;
+	/*
+	 * Flags which are valid on this platform.  This allows the caller
+	 * to distinguish between flags which aren't set vs. flags which can't
+	 * be set on this platform.
+	 */
+	uint32_t valid_flags;
+	/* Flags which can be changed given the current protection state */
+	uint32_t writable_flags;
+} __packed;
+
+/*
+ * Note: commands 0x14 - 0x19 version 0 were old commands to get/set flash
+ * write protect.  These commands may be reused with version > 0.
+ */
+
+/* Get the region offset/size */
+#define EC_CMD_FLASH_REGION_INFO 0x16
+#define EC_VER_FLASH_REGION_INFO 1
+
+enum ec_flash_region {
+	/* Region which holds read-only EC image */
+	EC_FLASH_REGION_RO = 0,
+	/* Region which holds rewritable EC image */
+	EC_FLASH_REGION_RW,
+	/*
+	 * Region which should be write-protected in the factory (a superset of
+	 * EC_FLASH_REGION_RO)
+	 */
+	EC_FLASH_REGION_WP_RO,
+	/* Number of regions */
+	EC_FLASH_REGION_COUNT,
+};
+
+struct ec_params_flash_region_info {
+	uint32_t region;  /* enum ec_flash_region */
+} __packed;
+
+struct ec_response_flash_region_info {
+	uint32_t offset;
+	uint32_t size;
+} __packed;
+
+/* Read/write VbNvContext */
+#define EC_CMD_VBNV_CONTEXT 0x17
+#define EC_VER_VBNV_CONTEXT 1
+#define EC_VBNV_BLOCK_SIZE 16
+
+enum ec_vbnvcontext_op {
+	EC_VBNV_CONTEXT_OP_READ,
+	EC_VBNV_CONTEXT_OP_WRITE,
+};
+
+struct ec_params_vbnvcontext {
+	uint32_t op;
+	uint8_t block[EC_VBNV_BLOCK_SIZE];
+} __packed;
+
+struct ec_response_vbnvcontext {
+	uint8_t block[EC_VBNV_BLOCK_SIZE];
+} __packed;
+
+/*****************************************************************************/
+/* PWM commands */
+
+/* Get fan target RPM */
+#define EC_CMD_PWM_GET_FAN_TARGET_RPM 0x20
+
+struct ec_response_pwm_get_fan_rpm {
+	uint32_t rpm;
+} __packed;
+
+/* Set target fan RPM */
+#define EC_CMD_PWM_SET_FAN_TARGET_RPM 0x21
+
+struct ec_params_pwm_set_fan_target_rpm {
+	uint32_t rpm;
+} __packed;
+
+/* Get keyboard backlight */
+#define EC_CMD_PWM_GET_KEYBOARD_BACKLIGHT 0x22
+
+struct ec_response_pwm_get_keyboard_backlight {
+	uint8_t percent;
+	uint8_t enabled;
+} __packed;
+
+/* Set keyboard backlight */
+#define EC_CMD_PWM_SET_KEYBOARD_BACKLIGHT 0x23
+
+struct ec_params_pwm_set_keyboard_backlight {
+	uint8_t percent;
+} __packed;
+
+/* Set target fan PWM duty cycle */
+#define EC_CMD_PWM_SET_FAN_DUTY 0x24
+
+struct ec_params_pwm_set_fan_duty {
+	uint32_t percent;
+} __packed;
+
+/*****************************************************************************/
+/*
+ * Lightbar commands. This looks worse than it is. Since we only use one HOST
+ * command to say "talk to the lightbar", we put the "and tell it to do X" part
+ * into a subcommand. We'll make separate structs for subcommands with
+ * different input args, so that we know how much to expect.
+ */
+#define EC_CMD_LIGHTBAR_CMD 0x28
+
+struct rgb_s {
+	uint8_t r, g, b;
+};
+
+#define LB_BATTERY_LEVELS 4
+/* List of tweakable parameters. NOTE: It's __packed so it can be sent in a
+ * host command, but the alignment is the same regardless. Keep it that way.
+ */
+struct lightbar_params {
+	/* Timing */
+	int google_ramp_up;
+	int google_ramp_down;
+	int s3s0_ramp_up;
+	int s0_tick_delay[2];			/* AC=0/1 */
+	int s0a_tick_delay[2];			/* AC=0/1 */
+	int s0s3_ramp_down;
+	int s3_sleep_for;
+	int s3_ramp_up;
+	int s3_ramp_down;
+
+	/* Oscillation */
+	uint8_t new_s0;
+	uint8_t osc_min[2];			/* AC=0/1 */
+	uint8_t osc_max[2];			/* AC=0/1 */
+	uint8_t w_ofs[2];			/* AC=0/1 */
+
+	/* Brightness limits based on the backlight and AC. */
+	uint8_t bright_bl_off_fixed[2];		/* AC=0/1 */
+	uint8_t bright_bl_on_min[2];		/* AC=0/1 */
+	uint8_t bright_bl_on_max[2];		/* AC=0/1 */
+
+	/* Battery level thresholds */
+	uint8_t battery_threshold[LB_BATTERY_LEVELS - 1];
+
+	/* Map [AC][battery_level] to color index */
+	uint8_t s0_idx[2][LB_BATTERY_LEVELS];	/* AP is running */
+	uint8_t s3_idx[2][LB_BATTERY_LEVELS];	/* AP is sleeping */
+
+	/* Color palette */
+	struct rgb_s color[8];			/* 0-3 are Google colors */
+} __packed;
+
+struct ec_params_lightbar {
+	uint8_t cmd;		      /* Command (see enum lightbar_command) */
+	union {
+		struct {
+			/* no args */
+		} dump, off, on, init, get_seq, get_params;
+
+		struct num {
+			uint8_t num;
+		} brightness, seq, demo;
+
+		struct reg {
+			uint8_t ctrl, reg, value;
+		} reg;
+
+		struct rgb {
+			uint8_t led, red, green, blue;
+		} rgb;
+
+		struct lightbar_params set_params;
+	};
+} __packed;
+
+struct ec_response_lightbar {
+	union {
+		struct dump {
+			struct {
+				uint8_t reg;
+				uint8_t ic0;
+				uint8_t ic1;
+			} vals[23];
+		} dump;
+
+		struct get_seq {
+			uint8_t num;
+		} get_seq;
+
+		struct lightbar_params get_params;
+
+		struct {
+			/* no return params */
+		} off, on, init, brightness, seq, reg, rgb, demo, set_params;
+	};
+} __packed;
+
+/* Lightbar commands */
+enum lightbar_command {
+	LIGHTBAR_CMD_DUMP = 0,
+	LIGHTBAR_CMD_OFF = 1,
+	LIGHTBAR_CMD_ON = 2,
+	LIGHTBAR_CMD_INIT = 3,
+	LIGHTBAR_CMD_BRIGHTNESS = 4,
+	LIGHTBAR_CMD_SEQ = 5,
+	LIGHTBAR_CMD_REG = 6,
+	LIGHTBAR_CMD_RGB = 7,
+	LIGHTBAR_CMD_GET_SEQ = 8,
+	LIGHTBAR_CMD_DEMO = 9,
+	LIGHTBAR_CMD_GET_PARAMS = 10,
+	LIGHTBAR_CMD_SET_PARAMS = 11,
+	LIGHTBAR_NUM_CMDS
+};
+
+/*****************************************************************************/
+/* LED control commands */
+
+#define EC_CMD_LED_CONTROL 0x29
+
+enum ec_led_id {
+	EC_LED_ID_BATTERY_LED = 0,
+	EC_LED_ID_POWER_BUTTON_LED,
+	EC_LED_ID_ADAPTER_LED,
+};
+
+/* LED control flags */
+#define EC_LED_FLAGS_QUERY (1 << 0) /* Query LED capability only */
+#define EC_LED_FLAGS_AUTO  (1 << 1) /* Switch LED back to automatic control */
+
+enum ec_led_colors {
+	EC_LED_COLOR_RED = 0,
+	EC_LED_COLOR_GREEN,
+	EC_LED_COLOR_BLUE,
+	EC_LED_COLOR_YELLOW,
+	EC_LED_COLOR_WHITE,
+
+	EC_LED_COLOR_COUNT
+};
+
+struct ec_params_led_control {
+	uint8_t led_id;     /* Which LED to control */
+	uint8_t flags;      /* Control flags */
+
+	uint8_t brightness[EC_LED_COLOR_COUNT];
+} __packed;
+
+struct ec_response_led_control {
+	/*
+	 * Available brightness value range.
+	 *
+	 * Range 0 means color channel not present.
+	 * Range 1 means on/off control.
+	 * Other values means the LED is control by PWM.
+	 */
+	uint8_t brightness_range[EC_LED_COLOR_COUNT];
+} __packed;
+
+/*****************************************************************************/
+/* Verified boot commands */
+
+/*
+ * Note: command code 0x29 version 0 was VBOOT_CMD in Link EVT; it may be
+ * reused for other purposes with version > 0.
+ */
+
+/* Verified boot hash command */
+#define EC_CMD_VBOOT_HASH 0x2A
+
+struct ec_params_vboot_hash {
+	uint8_t cmd;             /* enum ec_vboot_hash_cmd */
+	uint8_t hash_type;       /* enum ec_vboot_hash_type */
+	uint8_t nonce_size;      /* Nonce size; may be 0 */
+	uint8_t reserved0;       /* Reserved; set 0 */
+	uint32_t offset;         /* Offset in flash to hash */
+	uint32_t size;           /* Number of bytes to hash */
+	uint8_t nonce_data[64];  /* Nonce data; ignored if nonce_size=0 */
+} __packed;
+
+struct ec_response_vboot_hash {
+	uint8_t status;          /* enum ec_vboot_hash_status */
+	uint8_t hash_type;       /* enum ec_vboot_hash_type */
+	uint8_t digest_size;     /* Size of hash digest in bytes */
+	uint8_t reserved0;       /* Ignore; will be 0 */
+	uint32_t offset;         /* Offset in flash which was hashed */
+	uint32_t size;           /* Number of bytes hashed */
+	uint8_t hash_digest[64]; /* Hash digest data */
+} __packed;
+
+enum ec_vboot_hash_cmd {
+	EC_VBOOT_HASH_GET = 0,       /* Get current hash status */
+	EC_VBOOT_HASH_ABORT = 1,     /* Abort calculating current hash */
+	EC_VBOOT_HASH_START = 2,     /* Start computing a new hash */
+	EC_VBOOT_HASH_RECALC = 3,    /* Synchronously compute a new hash */
+};
+
+enum ec_vboot_hash_type {
+	EC_VBOOT_HASH_TYPE_SHA256 = 0, /* SHA-256 */
+};
+
+enum ec_vboot_hash_status {
+	EC_VBOOT_HASH_STATUS_NONE = 0, /* No hash (not started, or aborted) */
+	EC_VBOOT_HASH_STATUS_DONE = 1, /* Finished computing a hash */
+	EC_VBOOT_HASH_STATUS_BUSY = 2, /* Busy computing a hash */
+};
+
+/*
+ * Special values for offset for EC_VBOOT_HASH_START and EC_VBOOT_HASH_RECALC.
+ * If one of these is specified, the EC will automatically update offset and
+ * size to the correct values for the specified image (RO or RW).
+ */
+#define EC_VBOOT_HASH_OFFSET_RO 0xfffffffe
+#define EC_VBOOT_HASH_OFFSET_RW 0xfffffffd
+
+/*****************************************************************************/
+/* USB charging control commands */
+
+/* Set USB port charging mode */
+#define EC_CMD_USB_CHARGE_SET_MODE 0x30
+
+struct ec_params_usb_charge_set_mode {
+	uint8_t usb_port_id;
+	uint8_t mode;
+} __packed;
+
+/*****************************************************************************/
+/* Persistent storage for host */
+
+/* Maximum bytes that can be read/written in a single command */
+#define EC_PSTORE_SIZE_MAX 64
+
+/* Get persistent storage info */
+#define EC_CMD_PSTORE_INFO 0x40
+
+struct ec_response_pstore_info {
+	/* Persistent storage size, in bytes */
+	uint32_t pstore_size;
+	/* Access size; read/write offset and size must be a multiple of this */
+	uint32_t access_size;
+} __packed;
+
+/*
+ * Read persistent storage
+ *
+ * Response is params.size bytes of data.
+ */
+#define EC_CMD_PSTORE_READ 0x41
+
+struct ec_params_pstore_read {
+	uint32_t offset;   /* Byte offset to read */
+	uint32_t size;     /* Size to read in bytes */
+} __packed;
+
+/* Write persistent storage */
+#define EC_CMD_PSTORE_WRITE 0x42
+
+struct ec_params_pstore_write {
+	uint32_t offset;   /* Byte offset to write */
+	uint32_t size;     /* Size to write in bytes */
+	uint8_t data[EC_PSTORE_SIZE_MAX];
+} __packed;
+
+/*****************************************************************************/
+/* Real-time clock */
+
+/* RTC params and response structures */
+struct ec_params_rtc {
+	uint32_t time;
+} __packed;
+
+struct ec_response_rtc {
+	uint32_t time;
+} __packed;
+
+/* These use ec_response_rtc */
+#define EC_CMD_RTC_GET_VALUE 0x44
+#define EC_CMD_RTC_GET_ALARM 0x45
+
+/* These all use ec_params_rtc */
+#define EC_CMD_RTC_SET_VALUE 0x46
+#define EC_CMD_RTC_SET_ALARM 0x47
+
+/*****************************************************************************/
+/* Port80 log access */
+
+/* Get last port80 code from previous boot */
+#define EC_CMD_PORT80_LAST_BOOT 0x48
+
+struct ec_response_port80_last_boot {
+	uint16_t code;
+} __packed;
+
+/*****************************************************************************/
+/* Thermal engine commands */
+
+/* Set thershold value */
+#define EC_CMD_THERMAL_SET_THRESHOLD 0x50
+
+struct ec_params_thermal_set_threshold {
+	uint8_t sensor_type;
+	uint8_t threshold_id;
+	uint16_t value;
+} __packed;
+
+/* Get threshold value */
+#define EC_CMD_THERMAL_GET_THRESHOLD 0x51
+
+struct ec_params_thermal_get_threshold {
+	uint8_t sensor_type;
+	uint8_t threshold_id;
+} __packed;
+
+struct ec_response_thermal_get_threshold {
+	uint16_t value;
+} __packed;
+
+/* Toggle automatic fan control */
+#define EC_CMD_THERMAL_AUTO_FAN_CTRL 0x52
+
+/* Get TMP006 calibration data */
+#define EC_CMD_TMP006_GET_CALIBRATION 0x53
+
+struct ec_params_tmp006_get_calibration {
+	uint8_t index;
+} __packed;
+
+struct ec_response_tmp006_get_calibration {
+	float s0;
+	float b0;
+	float b1;
+	float b2;
+} __packed;
+
+/* Set TMP006 calibration data */
+#define EC_CMD_TMP006_SET_CALIBRATION 0x54
+
+struct ec_params_tmp006_set_calibration {
+	uint8_t index;
+	uint8_t reserved[3];  /* Reserved; set 0 */
+	float s0;
+	float b0;
+	float b1;
+	float b2;
+} __packed;
+
+/*****************************************************************************/
+/* MKBP - Matrix KeyBoard Protocol */
+
+/*
+ * Read key state
+ *
+ * Returns raw data for keyboard cols; see ec_response_mkbp_info.cols for
+ * expected response size.
+ */
+#define EC_CMD_MKBP_STATE 0x60
+
+/* Provide information about the matrix : number of rows and columns */
+#define EC_CMD_MKBP_INFO 0x61
+
+struct ec_response_mkbp_info {
+	uint32_t rows;
+	uint32_t cols;
+	uint8_t switches;
+} __packed;
+
+/* Simulate key press */
+#define EC_CMD_MKBP_SIMULATE_KEY 0x62
+
+struct ec_params_mkbp_simulate_key {
+	uint8_t col;
+	uint8_t row;
+	uint8_t pressed;
+} __packed;
+
+/* Configure keyboard scanning */
+#define EC_CMD_MKBP_SET_CONFIG 0x64
+#define EC_CMD_MKBP_GET_CONFIG 0x65
+
+/* flags */
+enum mkbp_config_flags {
+	EC_MKBP_FLAGS_ENABLE = 1,	/* Enable keyboard scanning */
+};
+
+enum mkbp_config_valid {
+	EC_MKBP_VALID_SCAN_PERIOD		= 1 << 0,
+	EC_MKBP_VALID_POLL_TIMEOUT		= 1 << 1,
+	EC_MKBP_VALID_MIN_POST_SCAN_DELAY	= 1 << 3,
+	EC_MKBP_VALID_OUTPUT_SETTLE		= 1 << 4,
+	EC_MKBP_VALID_DEBOUNCE_DOWN		= 1 << 5,
+	EC_MKBP_VALID_DEBOUNCE_UP		= 1 << 6,
+	EC_MKBP_VALID_FIFO_MAX_DEPTH		= 1 << 7,
+};
+
+/* Configuration for our key scanning algorithm */
+struct ec_mkbp_config {
+	uint32_t valid_mask;		/* valid fields */
+	uint8_t flags;		/* some flags (enum mkbp_config_flags) */
+	uint8_t valid_flags;		/* which flags are valid */
+	uint16_t scan_period_us;	/* period between start of scans */
+	/* revert to interrupt mode after no activity for this long */
+	uint32_t poll_timeout_us;
+	/*
+	 * minimum post-scan relax time. Once we finish a scan we check
+	 * the time until we are due to start the next one. If this time is
+	 * shorter this field, we use this instead.
+	 */
+	uint16_t min_post_scan_delay_us;
+	/* delay between setting up output and waiting for it to settle */
+	uint16_t output_settle_us;
+	uint16_t debounce_down_us;	/* time for debounce on key down */
+	uint16_t debounce_up_us;	/* time for debounce on key up */
+	/* maximum depth to allow for fifo (0 = no keyscan output) */
+	uint8_t fifo_max_depth;
+} __packed;
+
+struct ec_params_mkbp_set_config {
+	struct ec_mkbp_config config;
+} __packed;
+
+struct ec_response_mkbp_get_config {
+	struct ec_mkbp_config config;
+} __packed;
+
+/* Run the key scan emulation */
+#define EC_CMD_KEYSCAN_SEQ_CTRL 0x66
+
+enum ec_keyscan_seq_cmd {
+	EC_KEYSCAN_SEQ_STATUS = 0,	/* Get status information */
+	EC_KEYSCAN_SEQ_CLEAR = 1,	/* Clear sequence */
+	EC_KEYSCAN_SEQ_ADD = 2,		/* Add item to sequence */
+	EC_KEYSCAN_SEQ_START = 3,	/* Start running sequence */
+	EC_KEYSCAN_SEQ_COLLECT = 4,	/* Collect sequence summary data */
+};
+
+enum ec_collect_flags {
+	/*
+	 * Indicates this scan was processed by the EC. Due to timing, some
+	 * scans may be skipped.
+	 */
+	EC_KEYSCAN_SEQ_FLAG_DONE	= 1 << 0,
+};
+
+struct ec_collect_item {
+	uint8_t flags;		/* some flags (enum ec_collect_flags) */
+};
+
+struct ec_params_keyscan_seq_ctrl {
+	uint8_t cmd;	/* Command to send (enum ec_keyscan_seq_cmd) */
+	union {
+		struct {
+			uint8_t active;		/* still active */
+			uint8_t num_items;	/* number of items */
+			/* Current item being presented */
+			uint8_t cur_item;
+		} status;
+		struct {
+			/*
+			 * Absolute time for this scan, measured from the
+			 * start of the sequence.
+			 */
+			uint32_t time_us;
+			uint8_t scan[0];	/* keyscan data */
+		} add;
+		struct {
+			uint8_t start_item;	/* First item to return */
+			uint8_t num_items;	/* Number of items to return */
+		} collect;
+	};
+} __packed;
+
+struct ec_result_keyscan_seq_ctrl {
+	union {
+		struct {
+			uint8_t num_items;	/* Number of items */
+			/* Data for each item */
+			struct ec_collect_item item[0];
+		} collect;
+	};
+} __packed;
+
+/*****************************************************************************/
+/* Temperature sensor commands */
+
+/* Read temperature sensor info */
+#define EC_CMD_TEMP_SENSOR_GET_INFO 0x70
+
+struct ec_params_temp_sensor_get_info {
+	uint8_t id;
+} __packed;
+
+struct ec_response_temp_sensor_get_info {
+	char sensor_name[32];
+	uint8_t sensor_type;
+} __packed;
+
+/*****************************************************************************/
+
+/*
+ * Note: host commands 0x80 - 0x87 are reserved to avoid conflict with ACPI
+ * commands accidentally sent to the wrong interface.  See the ACPI section
+ * below.
+ */
+
+/*****************************************************************************/
+/* Host event commands */
+
+/*
+ * Host event mask params and response structures, shared by all of the host
+ * event commands below.
+ */
+struct ec_params_host_event_mask {
+	uint32_t mask;
+} __packed;
+
+struct ec_response_host_event_mask {
+	uint32_t mask;
+} __packed;
+
+/* These all use ec_response_host_event_mask */
+#define EC_CMD_HOST_EVENT_GET_B         0x87
+#define EC_CMD_HOST_EVENT_GET_SMI_MASK  0x88
+#define EC_CMD_HOST_EVENT_GET_SCI_MASK  0x89
+#define EC_CMD_HOST_EVENT_GET_WAKE_MASK 0x8d
+
+/* These all use ec_params_host_event_mask */
+#define EC_CMD_HOST_EVENT_SET_SMI_MASK  0x8a
+#define EC_CMD_HOST_EVENT_SET_SCI_MASK  0x8b
+#define EC_CMD_HOST_EVENT_CLEAR         0x8c
+#define EC_CMD_HOST_EVENT_SET_WAKE_MASK 0x8e
+#define EC_CMD_HOST_EVENT_CLEAR_B       0x8f
+
+/*****************************************************************************/
+/* Switch commands */
+
+/* Enable/disable LCD backlight */
+#define EC_CMD_SWITCH_ENABLE_BKLIGHT 0x90
+
+struct ec_params_switch_enable_backlight {
+	uint8_t enabled;
+} __packed;
+
+/* Enable/disable WLAN/Bluetooth */
+#define EC_CMD_SWITCH_ENABLE_WIRELESS 0x91
+
+struct ec_params_switch_enable_wireless {
+	uint8_t enabled;
+} __packed;
+
+/*****************************************************************************/
+/* GPIO commands. Only available on EC if write protect has been disabled. */
+
+/* Set GPIO output value */
+#define EC_CMD_GPIO_SET 0x92
+
+struct ec_params_gpio_set {
+	char name[32];
+	uint8_t val;
+} __packed;
+
+/* Get GPIO value */
+#define EC_CMD_GPIO_GET 0x93
+
+struct ec_params_gpio_get {
+	char name[32];
+} __packed;
+struct ec_response_gpio_get {
+	uint8_t val;
+} __packed;
+
+/*****************************************************************************/
+/* I2C commands. Only available when flash write protect is unlocked. */
+
+/* Read I2C bus */
+#define EC_CMD_I2C_READ 0x94
+
+struct ec_params_i2c_read {
+	uint16_t addr; /* 8-bit address (7-bit shifted << 1) */
+	uint8_t read_size; /* Either 8 or 16. */
+	uint8_t port;
+	uint8_t offset;
+} __packed;
+struct ec_response_i2c_read {
+	uint16_t data;
+} __packed;
+
+/* Write I2C bus */
+#define EC_CMD_I2C_WRITE 0x95
+
+struct ec_params_i2c_write {
+	uint16_t data;
+	uint16_t addr; /* 8-bit address (7-bit shifted << 1) */
+	uint8_t write_size; /* Either 8 or 16. */
+	uint8_t port;
+	uint8_t offset;
+} __packed;
+
+/*****************************************************************************/
+/* Charge state commands. Only available when flash write protect unlocked. */
+
+/* Force charge state machine to stop in idle mode */
+#define EC_CMD_CHARGE_FORCE_IDLE 0x96
+
+struct ec_params_force_idle {
+	uint8_t enabled;
+} __packed;
+
+/*****************************************************************************/
+/* Console commands. Only available when flash write protect is unlocked. */
+
+/* Snapshot console output buffer for use by EC_CMD_CONSOLE_READ. */
+#define EC_CMD_CONSOLE_SNAPSHOT 0x97
+
+/*
+ * Read next chunk of data from saved snapshot.
+ *
+ * Response is null-terminated string.  Empty string, if there is no more
+ * remaining output.
+ */
+#define EC_CMD_CONSOLE_READ 0x98
+
+/*****************************************************************************/
+
+/*
+ * Cut off battery power output if the battery supports.
+ *
+ * For unsupported battery, just don't implement this command and lets EC
+ * return EC_RES_INVALID_COMMAND.
+ */
+#define EC_CMD_BATTERY_CUT_OFF 0x99
+
+/*****************************************************************************/
+/* USB port mux control. */
+
+/*
+ * Switch USB mux or return to automatic switching.
+ */
+#define EC_CMD_USB_MUX 0x9a
+
+struct ec_params_usb_mux {
+	uint8_t mux;
+} __packed;
+
+/*****************************************************************************/
+/* LDOs / FETs control. */
+
+enum ec_ldo_state {
+	EC_LDO_STATE_OFF = 0,	/* the LDO / FET is shut down */
+	EC_LDO_STATE_ON = 1,	/* the LDO / FET is ON / providing power */
+};
+
+/*
+ * Switch on/off a LDO.
+ */
+#define EC_CMD_LDO_SET 0x9b
+
+struct ec_params_ldo_set {
+	uint8_t index;
+	uint8_t state;
+} __packed;
+
+/*
+ * Get LDO state.
+ */
+#define EC_CMD_LDO_GET 0x9c
+
+struct ec_params_ldo_get {
+	uint8_t index;
+} __packed;
+
+struct ec_response_ldo_get {
+	uint8_t state;
+} __packed;
+
+/*****************************************************************************/
+/* Power info. */
+
+/*
+ * Get power info.
+ */
+#define EC_CMD_POWER_INFO 0x9d
+
+struct ec_response_power_info {
+	uint32_t usb_dev_type;
+	uint16_t voltage_ac;
+	uint16_t voltage_system;
+	uint16_t current_system;
+	uint16_t usb_current_limit;
+} __packed;
+
+/*****************************************************************************/
+/* I2C passthru command */
+
+#define EC_CMD_I2C_PASSTHRU 0x9e
+
+/* Slave address is 10 (not 7) bit */
+#define EC_I2C_FLAG_10BIT	(1 << 16)
+
+/* Read data; if not present, message is a write */
+#define EC_I2C_FLAG_READ	(1 << 15)
+
+/* Mask for address */
+#define EC_I2C_ADDR_MASK	0x3ff
+
+#define EC_I2C_STATUS_NAK	(1 << 0) /* Transfer was not acknowledged */
+#define EC_I2C_STATUS_TIMEOUT	(1 << 1) /* Timeout during transfer */
+
+/* Any error */
+#define EC_I2C_STATUS_ERROR	(EC_I2C_STATUS_NAK | EC_I2C_STATUS_TIMEOUT)
+
+struct ec_params_i2c_passthru_msg {
+	uint16_t addr_flags;	/* I2C slave address (7 or 10 bits) and flags */
+	uint16_t len;		/* Number of bytes to read or write */
+} __packed;
+
+struct ec_params_i2c_passthru {
+	uint8_t port;		/* I2C port number */
+	uint8_t num_msgs;	/* Number of messages */
+	struct ec_params_i2c_passthru_msg msg[];
+	/* Data to write for all messages is concatenated here */
+} __packed;
+
+struct ec_response_i2c_passthru {
+	uint8_t i2c_status;	/* Status flags (EC_I2C_STATUS_...) */
+	uint8_t num_msgs;	/* Number of messages processed */
+	uint8_t data[];		/* Data read by messages concatenated here */
+} __packed;
+
+
+/*****************************************************************************/
+/* Temporary debug commands. TODO: remove this crosbug.com/p/13849 */
+
+/*
+ * Dump charge state machine context.
+ *
+ * Response is a binary dump of charge state machine context.
+ */
+#define EC_CMD_CHARGE_DUMP 0xa0
+
+/*
+ * Set maximum battery charging current.
+ */
+#define EC_CMD_CHARGE_CURRENT_LIMIT 0xa1
+
+struct ec_params_current_limit {
+	uint32_t limit; /* in mA */
+} __packed;
+
+/*
+ * Set maximum external power current.
+ */
+#define EC_CMD_EXT_POWER_CURRENT_LIMIT 0xa2
+
+struct ec_params_ext_power_current_limit {
+	uint32_t limit; /* in mA */
+} __packed;
+
+/*****************************************************************************/
+/* Smart battery pass-through */
+
+/* Get / Set 16-bit smart battery registers */
+#define EC_CMD_SB_READ_WORD   0xb0
+#define EC_CMD_SB_WRITE_WORD  0xb1
+
+/* Get / Set string smart battery parameters
+ * formatted as SMBUS "block".
+ */
+#define EC_CMD_SB_READ_BLOCK  0xb2
+#define EC_CMD_SB_WRITE_BLOCK 0xb3
+
+struct ec_params_sb_rd {
+	uint8_t reg;
+} __packed;
+
+struct ec_response_sb_rd_word {
+	uint16_t value;
+} __packed;
+
+struct ec_params_sb_wr_word {
+	uint8_t reg;
+	uint16_t value;
+} __packed;
+
+struct ec_response_sb_rd_block {
+	uint8_t data[32];
+} __packed;
+
+struct ec_params_sb_wr_block {
+	uint8_t reg;
+	uint16_t data[32];
+} __packed;
+
+/*****************************************************************************/
+/* System commands */
+
+/*
+ * TODO: this is a confusing name, since it doesn't necessarily reboot the EC.
+ * Rename to "set image" or something similar.
+ */
+#define EC_CMD_REBOOT_EC 0xd2
+
+/* Command */
+enum ec_reboot_cmd {
+	EC_REBOOT_CANCEL = 0,        /* Cancel a pending reboot */
+	EC_REBOOT_JUMP_RO = 1,       /* Jump to RO without rebooting */
+	EC_REBOOT_JUMP_RW = 2,       /* Jump to RW without rebooting */
+	/* (command 3 was jump to RW-B) */
+	EC_REBOOT_COLD = 4,          /* Cold-reboot */
+	EC_REBOOT_DISABLE_JUMP = 5,  /* Disable jump until next reboot */
+	EC_REBOOT_HIBERNATE = 6      /* Hibernate EC */
+};
+
+/* Flags for ec_params_reboot_ec.reboot_flags */
+#define EC_REBOOT_FLAG_RESERVED0      (1 << 0)  /* Was recovery request */
+#define EC_REBOOT_FLAG_ON_AP_SHUTDOWN (1 << 1)  /* Reboot after AP shutdown */
+
+struct ec_params_reboot_ec {
+	uint8_t cmd;           /* enum ec_reboot_cmd */
+	uint8_t flags;         /* See EC_REBOOT_FLAG_* */
+} __packed;
+
+/*
+ * Get information on last EC panic.
+ *
+ * Returns variable-length platform-dependent panic information.  See panic.h
+ * for details.
+ */
+#define EC_CMD_GET_PANIC_INFO 0xd3
+
+/*****************************************************************************/
+/*
+ * ACPI commands
+ *
+ * These are valid ONLY on the ACPI command/data port.
+ */
+
+/*
+ * ACPI Read Embedded Controller
+ *
+ * This reads from ACPI memory space on the EC (EC_ACPI_MEM_*).
+ *
+ * Use the following sequence:
+ *
+ *    - Write EC_CMD_ACPI_READ to EC_LPC_ADDR_ACPI_CMD
+ *    - Wait for EC_LPC_CMDR_PENDING bit to clear
+ *    - Write address to EC_LPC_ADDR_ACPI_DATA
+ *    - Wait for EC_LPC_CMDR_DATA bit to set
+ *    - Read value from EC_LPC_ADDR_ACPI_DATA
+ */
+#define EC_CMD_ACPI_READ 0x80
+
+/*
+ * ACPI Write Embedded Controller
+ *
+ * This reads from ACPI memory space on the EC (EC_ACPI_MEM_*).
+ *
+ * Use the following sequence:
+ *
+ *    - Write EC_CMD_ACPI_WRITE to EC_LPC_ADDR_ACPI_CMD
+ *    - Wait for EC_LPC_CMDR_PENDING bit to clear
+ *    - Write address to EC_LPC_ADDR_ACPI_DATA
+ *    - Wait for EC_LPC_CMDR_PENDING bit to clear
+ *    - Write value to EC_LPC_ADDR_ACPI_DATA
+ */
+#define EC_CMD_ACPI_WRITE 0x81
+
+/*
+ * ACPI Query Embedded Controller
+ *
+ * This clears the lowest-order bit in the currently pending host events, and
+ * sets the result code to the 1-based index of the bit (event 0x00000001 = 1,
+ * event 0x80000000 = 32), or 0 if no event was pending.
+ */
+#define EC_CMD_ACPI_QUERY_EVENT 0x84
+
+/* Valid addresses in ACPI memory space, for read/write commands */
+/* Memory space version; set to EC_ACPI_MEM_VERSION_CURRENT */
+#define EC_ACPI_MEM_VERSION            0x00
+/*
+ * Test location; writing value here updates test compliment byte to (0xff -
+ * value).
+ */
+#define EC_ACPI_MEM_TEST               0x01
+/* Test compliment; writes here are ignored. */
+#define EC_ACPI_MEM_TEST_COMPLIMENT    0x02
+/* Keyboard backlight brightness percent (0 - 100) */
+#define EC_ACPI_MEM_KEYBOARD_BACKLIGHT 0x03
+
+/* Current version of ACPI memory address space */
+#define EC_ACPI_MEM_VERSION_CURRENT 1
+
+
+/*****************************************************************************/
+/*
+ * Special commands
+ *
+ * These do not follow the normal rules for commands.  See each command for
+ * details.
+ */
+
+/*
+ * Reboot NOW
+ *
+ * This command will work even when the EC LPC interface is busy, because the
+ * reboot command is processed at interrupt level.  Note that when the EC
+ * reboots, the host will reboot too, so there is no response to this command.
+ *
+ * Use EC_CMD_REBOOT_EC to reboot the EC more politely.
+ */
+#define EC_CMD_REBOOT 0xd1  /* Think "die" */
+
+/*
+ * Resend last response (not supported on LPC).
+ *
+ * Returns EC_RES_UNAVAILABLE if there is no response available - for example,
+ * there was no previous command, or the previous command's response was too
+ * big to save.
+ */
+#define EC_CMD_RESEND_RESPONSE 0xdb
+
+/*
+ * This header byte on a command indicate version 0. Any header byte less
+ * than this means that we are talking to an old EC which doesn't support
+ * versioning. In that case, we assume version 0.
+ *
+ * Header bytes greater than this indicate a later version. For example,
+ * EC_CMD_VERSION0 + 1 means we are using version 1.
+ *
+ * The old EC interface must not use commands 0dc or higher.
+ */
+#define EC_CMD_VERSION0 0xdc
+
+#endif  /* !__ACPI__ */
+
+#endif  /* __CROS_EC_COMMANDS_H */
diff --git a/qemu/roms/u-boot/include/edid.h b/qemu/roms/u-boot/include/edid.h
new file mode 100644
index 000000000..480a773d0
--- /dev/null
+++ b/qemu/roms/u-boot/include/edid.h
@@ -0,0 +1,258 @@
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ *
+ * (C) Copyright 2010
+ * Petr Stetiar <ynezz@true.cz>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Contains stolen code from ddcprobe project which is:
+ * Copyright (C) Nalin Dahyabhai <bigfun@pobox.com>
+ */
+
+#ifndef __EDID_H_
+#define __EDID_H_
+
+#include <linux/types.h>
+
+#define GET_BIT(_x, _pos) \
+	(((_x) >> (_pos)) & 1)
+#define GET_BITS(_x, _pos_msb, _pos_lsb) \
+	(((_x) >> (_pos_lsb)) & ((1 << ((_pos_msb) - (_pos_lsb) + 1)) - 1))
+
+/* Aspect ratios used in EDID info. */
+enum edid_aspect {
+	ASPECT_625 = 0,
+	ASPECT_75,
+	ASPECT_8,
+	ASPECT_5625,
+};
+
+/* Detailed timing information used in EDID v1.x */
+struct edid_detailed_timing {
+	unsigned char pixel_clock[2];
+#define EDID_DETAILED_TIMING_PIXEL_CLOCK(_x) \
+	(((((uint32_t)(_x).pixel_clock[1]) << 8) + \
+	 (_x).pixel_clock[0]) * 10000)
+	unsigned char horizontal_active;
+	unsigned char horizontal_blanking;
+	unsigned char horizontal_active_blanking_hi;
+#define EDID_DETAILED_TIMING_HORIZONTAL_ACTIVE(_x) \
+	((GET_BITS((_x).horizontal_active_blanking_hi, 7, 4) << 8) + \
+	 (_x).horizontal_active)
+#define EDID_DETAILED_TIMING_HORIZONTAL_BLANKING(_x) \
+	((GET_BITS((_x).horizontal_active_blanking_hi, 3, 0) << 8) + \
+	 (_x).horizontal_blanking)
+	unsigned char vertical_active;
+	unsigned char vertical_blanking;
+	unsigned char vertical_active_blanking_hi;
+#define EDID_DETAILED_TIMING_VERTICAL_ACTIVE(_x) \
+	((GET_BITS((_x).vertical_active_blanking_hi, 7, 4) << 8) + \
+	 (_x).vertical_active)
+#define EDID_DETAILED_TIMING_VERTICAL_BLANKING(_x) \
+	((GET_BITS((_x).vertical_active_blanking_hi, 3, 0) << 8) + \
+	 (_x).vertical_blanking)
+	unsigned char hsync_offset;
+	unsigned char hsync_pulse_width;
+	unsigned char vsync_offset_pulse_width;
+	unsigned char hsync_vsync_offset_pulse_width_hi;
+#define EDID_DETAILED_TIMING_HSYNC_OFFSET(_x) \
+	((GET_BITS((_x).hsync_vsync_offset_pulse_width_hi, 7, 6) << 8) + \
+	 (_x).hsync_offset)
+#define EDID_DETAILED_TIMING_HSYNC_PULSE_WIDTH(_x) \
+	((GET_BITS((_x).hsync_vsync_offset_pulse_width_hi, 5, 4) << 8) + \
+	 (_x).hsync_pulse_width)
+#define EDID_DETAILED_TIMING_VSYNC_OFFSET(_x) \
+	((GET_BITS((_x).hsync_vsync_offset_pulse_width_hi, 3, 2) << 4) + \
+	 GET_BITS((_x).vsync_offset_pulse_width, 7, 4))
+#define EDID_DETAILED_TIMING_VSYNC_PULSE_WIDTH(_x) \
+	((GET_BITS((_x).hsync_vsync_offset_pulse_width_hi, 1, 0) << 4) + \
+	 GET_BITS((_x).vsync_offset_pulse_width, 3, 0))
+	unsigned char himage_size;
+	unsigned char vimage_size;
+	unsigned char himage_vimage_size_hi;
+#define EDID_DETAILED_TIMING_HIMAGE_SIZE(_x) \
+	((GET_BITS((_x).himage_vimage_size_hi, 7, 4) << 8) + (_x).himage_size)
+#define EDID_DETAILED_TIMING_VIMAGE_SIZE(_x) \
+	((GET_BITS((_x).himage_vimage_size_hi, 3, 0) << 8) + (_x).vimage_size)
+	unsigned char hborder;
+	unsigned char vborder;
+	unsigned char flags;
+#define EDID_DETAILED_TIMING_FLAG_INTERLACED(_x) \
+	GET_BIT((_x).flags, 7)
+#define EDID_DETAILED_TIMING_FLAG_STEREO(_x) \
+	GET_BITS((_x).flags, 6, 5)
+#define EDID_DETAILED_TIMING_FLAG_DIGITAL_COMPOSITE(_x) \
+	GET_BITS((_x).flags, 4, 3)
+#define EDID_DETAILED_TIMING_FLAG_POLARITY(_x) \
+	GET_BITS((_x).flags, 2, 1)
+#define EDID_DETAILED_TIMING_FLAG_INTERLEAVED(_x) \
+	GET_BIT((_x).flags, 0)
+} __attribute__ ((__packed__));
+
+enum edid_monitor_descriptor_types {
+	EDID_MONITOR_DESCRIPTOR_SERIAL = 0xff,
+	EDID_MONITOR_DESCRIPTOR_ASCII = 0xfe,
+	EDID_MONITOR_DESCRIPTOR_RANGE = 0xfd,
+	EDID_MONITOR_DESCRIPTOR_NAME = 0xfc,
+};
+
+struct edid_monitor_descriptor {
+	uint16_t zero_flag_1;
+	unsigned char zero_flag_2;
+	unsigned char type;
+	unsigned char zero_flag_3;
+	union {
+		char string[13];
+		struct {
+			unsigned char vertical_min;
+			unsigned char vertical_max;
+			unsigned char horizontal_min;
+			unsigned char horizontal_max;
+			unsigned char pixel_clock_max;
+			unsigned char gtf_data[8];
+		} range_data;
+	} data;
+} __attribute__ ((__packed__));
+
+struct edid1_info {
+	unsigned char header[8];
+	unsigned char manufacturer_name[2];
+#define EDID1_INFO_MANUFACTURER_NAME_ZERO(_x) \
+	GET_BIT(((_x).manufacturer_name[0]), 7)
+#define EDID1_INFO_MANUFACTURER_NAME_CHAR1(_x) \
+	GET_BITS(((_x).manufacturer_name[0]), 6, 2)
+#define EDID1_INFO_MANUFACTURER_NAME_CHAR2(_x) \
+	((GET_BITS(((_x).manufacturer_name[0]), 1, 0) << 3) + \
+	 GET_BITS(((_x).manufacturer_name[1]), 7, 5))
+#define EDID1_INFO_MANUFACTURER_NAME_CHAR3(_x) \
+	GET_BITS(((_x).manufacturer_name[1]), 4, 0)
+	unsigned char product_code[2];
+#define EDID1_INFO_PRODUCT_CODE(_x) \
+	(((uint16_t)(_x).product_code[1] << 8) + (_x).product_code[0])
+	unsigned char serial_number[4];
+#define EDID1_INFO_SERIAL_NUMBER(_x) \
+	(((uint32_t)(_x).serial_number[3] << 24) + \
+	 ((_x).serial_number[2] << 16) + ((_x).serial_number[1] << 8) + \
+	 (_x).serial_number[0])
+	unsigned char week;
+	unsigned char year;
+	unsigned char version;
+	unsigned char revision;
+	unsigned char video_input_definition;
+#define EDID1_INFO_VIDEO_INPUT_DIGITAL(_x) \
+	GET_BIT(((_x).video_input_definition), 7)
+#define EDID1_INFO_VIDEO_INPUT_VOLTAGE_LEVEL(_x) \
+	GET_BITS(((_x).video_input_definition), 6, 5)
+#define EDID1_INFO_VIDEO_INPUT_BLANK_TO_BLACK(_x) \
+	GET_BIT(((_x).video_input_definition), 4)
+#define EDID1_INFO_VIDEO_INPUT_SEPARATE_SYNC(_x) \
+	GET_BIT(((_x).video_input_definition), 3)
+#define EDID1_INFO_VIDEO_INPUT_COMPOSITE_SYNC(_x) \
+	GET_BIT(((_x).video_input_definition), 2)
+#define EDID1_INFO_VIDEO_INPUT_SYNC_ON_GREEN(_x) \
+	GET_BIT(((_x).video_input_definition), 1)
+#define EDID1_INFO_VIDEO_INPUT_SERRATION_V(_x) \
+	GET_BIT(((_x).video_input_definition), 0)
+	unsigned char max_size_horizontal;
+	unsigned char max_size_vertical;
+	unsigned char gamma;
+	unsigned char feature_support;
+#define EDID1_INFO_FEATURE_STANDBY(_x) \
+	GET_BIT(((_x).feature_support), 7)
+#define EDID1_INFO_FEATURE_SUSPEND(_x) \
+	GET_BIT(((_x).feature_support), 6)
+#define EDID1_INFO_FEATURE_ACTIVE_OFF(_x) \
+	GET_BIT(((_x).feature_support), 5)
+#define EDID1_INFO_FEATURE_DISPLAY_TYPE(_x) \
+	GET_BITS(((_x).feature_support), 4, 3)
+#define EDID1_INFO_FEATURE_RGB(_x) \
+	GET_BIT(((_x).feature_support), 2)
+#define EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(_x) \
+	GET_BIT(((_x).feature_support), 1)
+#define EDID1_INFO_FEATURE_DEFAULT_GTF_SUPPORT(_x) \
+	GET_BIT(((_x).feature_support), 0)
+	unsigned char color_characteristics[10];
+	unsigned char established_timings[3];
+#define EDID1_INFO_ESTABLISHED_TIMING_720X400_70(_x) \
+	GET_BIT(((_x).established_timings[0]), 7)
+#define EDID1_INFO_ESTABLISHED_TIMING_720X400_88(_x) \
+	GET_BIT(((_x).established_timings[0]), 6)
+#define EDID1_INFO_ESTABLISHED_TIMING_640X480_60(_x) \
+	GET_BIT(((_x).established_timings[0]), 5)
+#define EDID1_INFO_ESTABLISHED_TIMING_640X480_67(_x) \
+	GET_BIT(((_x).established_timings[0]), 4)
+#define EDID1_INFO_ESTABLISHED_TIMING_640X480_72(_x) \
+	GET_BIT(((_x).established_timings[0]), 3)
+#define EDID1_INFO_ESTABLISHED_TIMING_640X480_75(_x) \
+	GET_BIT(((_x).established_timings[0]), 2)
+#define EDID1_INFO_ESTABLISHED_TIMING_800X600_56(_x) \
+	GET_BIT(((_x).established_timings[0]), 1)
+#define EDID1_INFO_ESTABLISHED_TIMING_800X600_60(_x) \
+	GET_BIT(((_x).established_timings[0]), 0)
+#define EDID1_INFO_ESTABLISHED_TIMING_800X600_72(_x) \
+	GET_BIT(((_x).established_timings[1]), 7)
+#define EDID1_INFO_ESTABLISHED_TIMING_800X600_75(_x) \
+	GET_BIT(((_x).established_timings[1]), 6)
+#define EDID1_INFO_ESTABLISHED_TIMING_832X624_75(_x) \
+	GET_BIT(((_x).established_timings[1]), 5)
+#define EDID1_INFO_ESTABLISHED_TIMING_1024X768_87I(_x) \
+	GET_BIT(((_x).established_timings[1]), 4)
+#define EDID1_INFO_ESTABLISHED_TIMING_1024X768_60(_x) \
+	GET_BIT(((_x).established_timings[1]), 3)
+#define EDID1_INFO_ESTABLISHED_TIMING_1024X768_70(_x) \
+	GET_BIT(((_x).established_timings[1]), 2)
+#define EDID1_INFO_ESTABLISHED_TIMING_1024X768_75(_x) \
+	GET_BIT(((_x).established_timings[1]), 1)
+#define EDID1_INFO_ESTABLISHED_TIMING_1280X1024_75(_x) \
+	GET_BIT(((_x).established_timings[1]), 0)
+#define EDID1_INFO_ESTABLISHED_TIMING_1152X870_75(_x) \
+	GET_BIT(((_x).established_timings[2]), 7)
+	struct {
+		unsigned char xresolution;
+		unsigned char aspect_vfreq;
+	} __attribute__((__packed__)) standard_timings[8];
+#define EDID1_INFO_STANDARD_TIMING_XRESOLUTION(_x, _i) \
+	(((_x).standard_timings[_i]).xresolution)
+#define EDID1_INFO_STANDARD_TIMING_ASPECT(_x, _i) \
+	GET_BITS(((_x).standard_timings[_i].aspect_vfreq), 7, 6)
+#define EDID1_INFO_STANDARD_TIMING_VFREQ(_x, _i) \
+	GET_BITS(((_x).standard_timings[_i].aspect_vfreq), 5, 0)
+	union {
+		unsigned char timing[72];
+		struct edid_monitor_descriptor descriptor[4];
+	} monitor_details;
+	unsigned char extension_flag;
+	unsigned char checksum;
+} __attribute__ ((__packed__));
+
+/**
+ * Print the EDID info.
+ *
+ * @param edid_info	The EDID info to be printed
+ */
+void edid_print_info(struct edid1_info *edid_info);
+
+/**
+ * Check the EDID info.
+ *
+ * @param info  The EDID info to be checked
+ * @return 0 on valid, or -1 on invalid
+ */
+int edid_check_info(struct edid1_info *info);
+
+/**
+ * Get the horizontal and vertical rate ranges of the monitor.
+ *
+ * @param edid	The EDID info
+ * @param hmin	Returns the minimum horizontal rate
+ * @param hmax	Returns the maxium horizontal rate
+ * @param vmin	Returns the minimum vertical rate
+ * @param vmax	Returns the maxium vertical rate
+ * @return 0 on success, or -1 on error
+ */
+int edid_get_ranges(struct edid1_info *edid, unsigned int *hmin,
+		    unsigned int *hmax, unsigned int *vmin,
+		    unsigned int *vmax);
+
+#endif /* __EDID_H_ */
diff --git a/qemu/roms/u-boot/include/elf.h b/qemu/roms/u-boot/include/elf.h
new file mode 100644
index 000000000..b8ecc4106
--- /dev/null
+++ b/qemu/roms/u-boot/include/elf.h
@@ -0,0 +1,573 @@
+/*
+ * Copyright (c) 1995, 1996, 2001, 2002
+ * Erik Theisen.  All rights reserved.
+ *
+ * SPDX-License-Identifier:	BSD-3-Clause
+ */
+
+/*
+ * This is the ELF ABI header file
+ * formerly known as "elf_abi.h".
+ */
+
+#ifndef _ELF_H
+#define _ELF_H
+
+#include "compiler.h"
+
+/*
+ *  This version doesn't work for 64-bit ABIs - Erik.
+ */
+
+/*
+ * These typedefs need to be handled better.
+ */
+typedef uint32_t	Elf32_Addr;	/* Unsigned program address */
+typedef uint32_t	Elf32_Off;	/* Unsigned file offset */
+typedef int32_t		Elf32_Sword;	/* Signed large integer */
+typedef uint32_t	Elf32_Word;	/* Unsigned large integer */
+typedef uint16_t	Elf32_Half;	/* Unsigned medium integer */
+
+/* e_ident[] identification indexes */
+#define EI_MAG0		0		/* file ID */
+#define EI_MAG1		1		/* file ID */
+#define EI_MAG2		2		/* file ID */
+#define EI_MAG3		3		/* file ID */
+#define EI_CLASS	4		/* file class */
+#define EI_DATA		5		/* data encoding */
+#define EI_VERSION	6		/* ELF header version */
+#define EI_OSABI	7		/* OS/ABI specific ELF extensions */
+#define EI_ABIVERSION	8		/* ABI target version */
+#define EI_PAD		9		/* start of pad bytes */
+#define EI_NIDENT	16		/* Size of e_ident[] */
+
+/* e_ident[] magic number */
+#define	ELFMAG0		0x7f		/* e_ident[EI_MAG0] */
+#define	ELFMAG1		'E'		/* e_ident[EI_MAG1] */
+#define	ELFMAG2		'L'		/* e_ident[EI_MAG2] */
+#define	ELFMAG3		'F'		/* e_ident[EI_MAG3] */
+#define	ELFMAG		"\177ELF"	/* magic */
+#define	SELFMAG		4		/* size of magic */
+
+/* e_ident[] file class */
+#define	ELFCLASSNONE	0		/* invalid */
+#define	ELFCLASS32	1		/* 32-bit objs */
+#define	ELFCLASS64	2		/* 64-bit objs */
+#define	ELFCLASSNUM	3		/* number of classes */
+
+/* e_ident[] data encoding */
+#define ELFDATANONE	0		/* invalid */
+#define ELFDATA2LSB	1		/* Little-Endian */
+#define ELFDATA2MSB	2		/* Big-Endian */
+#define ELFDATANUM	3		/* number of data encode defines */
+
+/* e_ident[] OS/ABI specific ELF extensions */
+#define ELFOSABI_NONE		0	/* No extension specified */
+#define ELFOSABI_HPUX		1	/* Hewlett-Packard HP-UX */
+#define ELFOSABI_NETBSD		2	/* NetBSD */
+#define ELFOSABI_LINUX		3	/* Linux */
+#define ELFOSABI_SOLARIS	6	/* Sun Solaris */
+#define ELFOSABI_AIX		7	/* AIX */
+#define ELFOSABI_IRIX		8	/* IRIX */
+#define ELFOSABI_FREEBSD	9	/* FreeBSD */
+#define ELFOSABI_TRU64		10	/* Compaq TRU64 UNIX */
+#define ELFOSABI_MODESTO	11	/* Novell Modesto */
+#define ELFOSABI_OPENBSD	12	/* OpenBSD */
+/* 64-255 Architecture-specific value range */
+
+/* e_ident[] ABI Version */
+#define ELFABIVERSION		0
+
+/* e_ident */
+#define IS_ELF(ehdr) ((ehdr).e_ident[EI_MAG0] == ELFMAG0 && \
+		      (ehdr).e_ident[EI_MAG1] == ELFMAG1 && \
+		      (ehdr).e_ident[EI_MAG2] == ELFMAG2 && \
+		      (ehdr).e_ident[EI_MAG3] == ELFMAG3)
+
+/* ELF Header */
+typedef struct elfhdr{
+	unsigned char	e_ident[EI_NIDENT]; /* ELF Identification */
+	Elf32_Half	e_type;		/* object file type */
+	Elf32_Half	e_machine;	/* machine */
+	Elf32_Word	e_version;	/* object file version */
+	Elf32_Addr	e_entry;	/* virtual entry point */
+	Elf32_Off	e_phoff;	/* program header table offset */
+	Elf32_Off	e_shoff;	/* section header table offset */
+	Elf32_Word	e_flags;	/* processor-specific flags */
+	Elf32_Half	e_ehsize;	/* ELF header size */
+	Elf32_Half	e_phentsize;	/* program header entry size */
+	Elf32_Half	e_phnum;	/* number of program header entries */
+	Elf32_Half	e_shentsize;	/* section header entry size */
+	Elf32_Half	e_shnum;	/* number of section header entries */
+	Elf32_Half	e_shstrndx;	/* section header table's "section
+					   header string table" entry offset */
+} Elf32_Ehdr;
+
+/* e_type */
+#define ET_NONE		0		/* No file type */
+#define ET_REL		1		/* relocatable file */
+#define ET_EXEC		2		/* executable file */
+#define ET_DYN		3		/* shared object file */
+#define ET_CORE		4		/* core file */
+#define ET_NUM		5		/* number of types */
+#define ET_LOOS		0xfe00		/* reserved range for operating */
+#define ET_HIOS		0xfeff		/*  system specific e_type */
+#define ET_LOPROC	0xff00		/* reserved range for processor */
+#define ET_HIPROC	0xffff		/*  specific e_type */
+
+/* e_machine */
+#define EM_NONE		0		/* No Machine */
+#define EM_M32		1		/* AT&T WE 32100 */
+#define EM_SPARC	2		/* SPARC */
+#define EM_386		3		/* Intel 80386 */
+#define EM_68K		4		/* Motorola 68000 */
+#define EM_88K		5		/* Motorola 88000 */
+#if 0
+#define EM_486		6		/* RESERVED - was Intel 80486 */
+#endif
+#define EM_860		7		/* Intel 80860 */
+#define EM_MIPS		8		/* MIPS R3000 Big-Endian only */
+#define EM_S370		9		/* IBM System/370 Processor */
+#define EM_MIPS_RS4_BE	10		/* MIPS R4000 Big-Endian */
+#if 0
+#define EM_SPARC64	11		/* RESERVED - was SPARC v9
+					     64-bit unoffical */
+#endif
+/* RESERVED 11-14 for future use */
+#define EM_PARISC	15		/* HPPA */
+/* RESERVED 16 for future use */
+#define EM_VPP500	17		/* Fujitsu VPP500 */
+#define EM_SPARC32PLUS	18		/* Enhanced instruction set SPARC */
+#define EM_960		19		/* Intel 80960 */
+#define EM_PPC		20		/* PowerPC */
+#define EM_PPC64	21		/* 64-bit PowerPC */
+#define EM_S390		22		/* IBM System/390 Processor */
+/* RESERVED 23-35 for future use */
+#define EM_V800		36		/* NEC V800 */
+#define EM_FR20		37		/* Fujitsu FR20 */
+#define EM_RH32		38		/* TRW RH-32 */
+#define EM_RCE		39		/* Motorola RCE */
+#define EM_ARM		40		/* Advanced Risc Machines ARM */
+#define EM_ALPHA	41		/* Digital Alpha */
+#define EM_SH		42		/* Hitachi SH */
+#define EM_SPARCV9	43		/* SPARC Version 9 */
+#define EM_TRICORE	44		/* Siemens TriCore embedded processor */
+#define EM_ARC		45		/* Argonaut RISC Core */
+#define EM_H8_300	46		/* Hitachi H8/300 */
+#define EM_H8_300H	47		/* Hitachi H8/300H */
+#define EM_H8S		48		/* Hitachi H8S */
+#define EM_H8_500	49		/* Hitachi H8/500 */
+#define EM_IA_64	50		/* Intel Merced */
+#define EM_MIPS_X	51		/* Stanford MIPS-X */
+#define EM_COLDFIRE	52		/* Motorola Coldfire */
+#define EM_68HC12	53		/* Motorola M68HC12 */
+#define EM_MMA		54		/* Fujitsu MMA Multimedia Accelerator*/
+#define EM_PCP		55		/* Siemens PCP */
+#define EM_NCPU		56		/* Sony nCPU embeeded RISC */
+#define EM_NDR1		57		/* Denso NDR1 microprocessor */
+#define EM_STARCORE	58		/* Motorola Start*Core processor */
+#define EM_ME16		59		/* Toyota ME16 processor */
+#define EM_ST100	60		/* STMicroelectronic ST100 processor */
+#define EM_TINYJ	61		/* Advanced Logic Corp. Tinyj emb.fam*/
+#define EM_X86_64	62		/* AMD x86-64 */
+#define EM_PDSP		63		/* Sony DSP Processor */
+/* RESERVED 64,65 for future use */
+#define EM_FX66		66		/* Siemens FX66 microcontroller */
+#define EM_ST9PLUS	67		/* STMicroelectronics ST9+ 8/16 mc */
+#define EM_ST7		68		/* STmicroelectronics ST7 8 bit mc */
+#define EM_68HC16	69		/* Motorola MC68HC16 microcontroller */
+#define EM_68HC11	70		/* Motorola MC68HC11 microcontroller */
+#define EM_68HC08	71		/* Motorola MC68HC08 microcontroller */
+#define EM_68HC05	72		/* Motorola MC68HC05 microcontroller */
+#define EM_SVX		73		/* Silicon Graphics SVx */
+#define EM_ST19		74		/* STMicroelectronics ST19 8 bit mc */
+#define EM_VAX		75		/* Digital VAX */
+#define EM_CHRIS	76		/* Axis Communications embedded proc. */
+#define EM_JAVELIN	77		/* Infineon Technologies emb. proc. */
+#define EM_FIREPATH	78		/* Element 14 64-bit DSP Processor */
+#define EM_ZSP		79		/* LSI Logic 16-bit DSP Processor */
+#define EM_MMIX		80		/* Donald Knuth's edu 64-bit proc. */
+#define EM_HUANY	81		/* Harvard University mach-indep objs */
+#define EM_PRISM	82		/* SiTera Prism */
+#define EM_AVR		83		/* Atmel AVR 8-bit microcontroller */
+#define EM_FR30		84		/* Fujitsu FR30 */
+#define EM_D10V		85		/* Mitsubishi DV10V */
+#define EM_D30V		86		/* Mitsubishi DV30V */
+#define EM_V850		87		/* NEC v850 */
+#define EM_M32R		88		/* Mitsubishi M32R */
+#define EM_MN10300	89		/* Matsushita MN10200 */
+#define EM_MN10200	90		/* Matsushita MN10200 */
+#define EM_PJ		91		/* picoJava */
+#define EM_NUM		92		/* number of machine types */
+
+/* Version */
+#define EV_NONE		0		/* Invalid */
+#define EV_CURRENT	1		/* Current */
+#define EV_NUM		2		/* number of versions */
+
+/* Section Header */
+typedef struct {
+	Elf32_Word	sh_name;	/* name - index into section header
+					   string table section */
+	Elf32_Word	sh_type;	/* type */
+	Elf32_Word	sh_flags;	/* flags */
+	Elf32_Addr	sh_addr;	/* address */
+	Elf32_Off	sh_offset;	/* file offset */
+	Elf32_Word	sh_size;	/* section size */
+	Elf32_Word	sh_link;	/* section header table index link */
+	Elf32_Word	sh_info;	/* extra information */
+	Elf32_Word	sh_addralign;	/* address alignment */
+	Elf32_Word	sh_entsize;	/* section entry size */
+} Elf32_Shdr;
+
+/* Special Section Indexes */
+#define SHN_UNDEF	0		/* undefined */
+#define SHN_LORESERVE	0xff00		/* lower bounds of reserved indexes */
+#define SHN_LOPROC	0xff00		/* reserved range for processor */
+#define SHN_HIPROC	0xff1f		/*   specific section indexes */
+#define SHN_LOOS	0xff20		/* reserved range for operating */
+#define SHN_HIOS	0xff3f		/*   specific semantics */
+#define SHN_ABS		0xfff1		/* absolute value */
+#define SHN_COMMON	0xfff2		/* common symbol */
+#define SHN_XINDEX	0xffff		/* Index is an extra table */
+#define SHN_HIRESERVE	0xffff		/* upper bounds of reserved indexes */
+
+/* sh_type */
+#define SHT_NULL	0		/* inactive */
+#define SHT_PROGBITS	1		/* program defined information */
+#define SHT_SYMTAB	2		/* symbol table section */
+#define SHT_STRTAB	3		/* string table section */
+#define SHT_RELA	4		/* relocation section with addends*/
+#define SHT_HASH	5		/* symbol hash table section */
+#define SHT_DYNAMIC	6		/* dynamic section */
+#define SHT_NOTE	7		/* note section */
+#define SHT_NOBITS	8		/* no space section */
+#define SHT_REL		9		/* relation section without addends */
+#define SHT_SHLIB	10		/* reserved - purpose unknown */
+#define SHT_DYNSYM	11		/* dynamic symbol table section */
+#define SHT_INIT_ARRAY	14		/* Array of constructors */
+#define SHT_FINI_ARRAY	15		/* Array of destructors */
+#define SHT_PREINIT_ARRAY 16		/* Array of pre-constructors */
+#define SHT_GROUP	17		/* Section group */
+#define SHT_SYMTAB_SHNDX 18		/* Extended section indeces */
+#define SHT_NUM		19		/* number of section types */
+#define SHT_LOOS	0x60000000	/* Start OS-specific */
+#define SHT_HIOS	0x6fffffff	/* End OS-specific */
+#define SHT_LOPROC	0x70000000	/* reserved range for processor */
+#define SHT_HIPROC	0x7fffffff	/*  specific section header types */
+#define SHT_LOUSER	0x80000000	/* reserved range for application */
+#define SHT_HIUSER	0xffffffff	/*  specific indexes */
+
+/* Section names */
+#define ELF_BSS         ".bss"		/* uninitialized data */
+#define ELF_COMMENT	".comment"	/* version control information */
+#define ELF_DATA        ".data"		/* initialized data */
+#define ELF_DATA1       ".data1"	/* initialized data */
+#define ELF_DEBUG       ".debug"	/* debug */
+#define ELF_DYNAMIC     ".dynamic"	/* dynamic linking information */
+#define ELF_DYNSTR      ".dynstr"	/* dynamic string table */
+#define ELF_DYNSYM      ".dynsym"	/* dynamic symbol table */
+#define ELF_FINI        ".fini"		/* termination code */
+#define ELF_FINI_ARRAY	".fini_array"	/* Array of destructors */
+#define ELF_GOT         ".got"		/* global offset table */
+#define ELF_HASH        ".hash"		/* symbol hash table */
+#define ELF_INIT        ".init"		/* initialization code */
+#define ELF_INIT_ARRAY	".init_array"	/* Array of constuctors */
+#define ELF_INTERP	".interp"	/* Pathname of program interpreter */
+#define ELF_LINE	".line"		/* Symbolic line numnber information */
+#define ELF_NOTE	".note"		/* Contains note section */
+#define ELF_PLT		".plt"		/* Procedure linkage table */
+#define ELF_PREINIT_ARRAY ".preinit_array" /* Array of pre-constructors */
+#define ELF_REL_DATA    ".rel.data"	/* relocation data */
+#define ELF_REL_FINI    ".rel.fini"	/* relocation termination code */
+#define ELF_REL_INIT    ".rel.init"	/* relocation initialization code */
+#define ELF_REL_DYN     ".rel.dyn"	/* relocaltion dynamic link info */
+#define ELF_REL_RODATA  ".rel.rodata"	/* relocation read-only data */
+#define ELF_REL_TEXT    ".rel.text"	/* relocation code */
+#define ELF_RODATA      ".rodata"	/* read-only data */
+#define ELF_RODATA1     ".rodata1"	/* read-only data */
+#define ELF_SHSTRTAB    ".shstrtab"	/* section header string table */
+#define ELF_STRTAB      ".strtab"	/* string table */
+#define ELF_SYMTAB      ".symtab"	/* symbol table */
+#define ELF_SYMTAB_SHNDX ".symtab_shndx"/* symbol table section index */
+#define ELF_TBSS	".tbss"		/* thread local uninit data */
+#define ELF_TDATA	".tdata"	/* thread local init data */
+#define ELF_TDATA1	".tdata1"	/* thread local init data */
+#define ELF_TEXT        ".text"		/* code */
+
+/* Section Attribute Flags - sh_flags */
+#define SHF_WRITE	0x1		/* Writable */
+#define SHF_ALLOC	0x2		/* occupies memory */
+#define SHF_EXECINSTR	0x4		/* executable */
+#define SHF_MERGE	0x10		/* Might be merged */
+#define SHF_STRINGS	0x20		/* Contains NULL terminated strings */
+#define SHF_INFO_LINK	0x40		/* sh_info contains SHT index */
+#define SHF_LINK_ORDER	0x80		/* Preserve order after combining*/
+#define SHF_OS_NONCONFORMING 0x100	/* Non-standard OS specific handling */
+#define SHF_GROUP	0x200		/* Member of section group */
+#define SHF_TLS		0x400		/* Thread local storage */
+#define SHF_MASKOS	0x0ff00000	/* OS specific */
+#define SHF_MASKPROC	0xf0000000	/* reserved bits for processor */
+					/*  specific section attributes */
+
+/* Section Group Flags */
+#define GRP_COMDAT	0x1		/* COMDAT group */
+#define GRP_MASKOS	0x0ff00000	/* Mask OS specific flags */
+#define GRP_MASKPROC	0xf0000000	/* Mask processor specific flags */
+
+/* Symbol Table Entry */
+typedef struct elf32_sym {
+	Elf32_Word	st_name;	/* name - index into string table */
+	Elf32_Addr	st_value;	/* symbol value */
+	Elf32_Word	st_size;	/* symbol size */
+	unsigned char	st_info;	/* type and binding */
+	unsigned char	st_other;	/* 0 - no defined meaning */
+	Elf32_Half	st_shndx;	/* section header index */
+} Elf32_Sym;
+
+/* Symbol table index */
+#define STN_UNDEF	0		/* undefined */
+
+/* Extract symbol info - st_info */
+#define ELF32_ST_BIND(x)	((x) >> 4)
+#define ELF32_ST_TYPE(x)	(((unsigned int) x) & 0xf)
+#define ELF32_ST_INFO(b,t)	(((b) << 4) + ((t) & 0xf))
+#define ELF32_ST_VISIBILITY(x)	((x) & 0x3)
+
+/* Symbol Binding - ELF32_ST_BIND - st_info */
+#define STB_LOCAL	0		/* Local symbol */
+#define STB_GLOBAL	1		/* Global symbol */
+#define STB_WEAK	2		/* like global - lower precedence */
+#define STB_NUM		3		/* number of symbol bindings */
+#define STB_LOOS	10		/* reserved range for operating */
+#define STB_HIOS	12		/*   system specific symbol bindings */
+#define STB_LOPROC	13		/* reserved range for processor */
+#define STB_HIPROC	15		/*  specific symbol bindings */
+
+/* Symbol type - ELF32_ST_TYPE - st_info */
+#define STT_NOTYPE	0		/* not specified */
+#define STT_OBJECT	1		/* data object */
+#define STT_FUNC	2		/* function */
+#define STT_SECTION	3		/* section */
+#define STT_FILE	4		/* file */
+#define STT_NUM		5		/* number of symbol types */
+#define STT_TLS		6		/* Thread local storage symbol */
+#define STT_LOOS	10		/* reserved range for operating */
+#define STT_HIOS	12		/*  system specific symbol types */
+#define STT_LOPROC	13		/* reserved range for processor */
+#define STT_HIPROC	15		/*  specific symbol types */
+
+/* Symbol visibility - ELF32_ST_VISIBILITY - st_other */
+#define STV_DEFAULT	0		/* Normal visibility rules */
+#define STV_INTERNAL	1		/* Processor specific hidden class */
+#define STV_HIDDEN	2		/* Symbol unavailable in other mods */
+#define STV_PROTECTED	3		/* Not preemptible, not exported */
+
+
+/* Relocation entry with implicit addend */
+typedef struct
+{
+	Elf32_Addr	r_offset;	/* offset of relocation */
+	Elf32_Word	r_info;		/* symbol table index and type */
+} Elf32_Rel;
+
+/* Relocation entry with explicit addend */
+typedef struct
+{
+	Elf32_Addr	r_offset;	/* offset of relocation */
+	Elf32_Word	r_info;		/* symbol table index and type */
+	Elf32_Sword	r_addend;
+} Elf32_Rela;
+
+/* Extract relocation info - r_info */
+#define ELF32_R_SYM(i)		((i) >> 8)
+#define ELF32_R_TYPE(i)		((unsigned char) (i))
+#define ELF32_R_INFO(s,t)	(((s) << 8) + (unsigned char)(t))
+
+/* Program Header */
+typedef struct {
+	Elf32_Word	p_type;		/* segment type */
+	Elf32_Off	p_offset;	/* segment offset */
+	Elf32_Addr	p_vaddr;	/* virtual address of segment */
+	Elf32_Addr	p_paddr;	/* physical address - ignored? */
+	Elf32_Word	p_filesz;	/* number of bytes in file for seg. */
+	Elf32_Word	p_memsz;	/* number of bytes in mem. for seg. */
+	Elf32_Word	p_flags;	/* flags */
+	Elf32_Word	p_align;	/* memory alignment */
+} Elf32_Phdr;
+
+/* Segment types - p_type */
+#define PT_NULL		0		/* unused */
+#define PT_LOAD		1		/* loadable segment */
+#define PT_DYNAMIC	2		/* dynamic linking section */
+#define PT_INTERP	3		/* the RTLD */
+#define PT_NOTE		4		/* auxiliary information */
+#define PT_SHLIB	5		/* reserved - purpose undefined */
+#define PT_PHDR		6		/* program header */
+#define PT_TLS		7		/* Thread local storage template */
+#define PT_NUM		8		/* Number of segment types */
+#define PT_LOOS		0x60000000	/* reserved range for operating */
+#define PT_HIOS		0x6fffffff	/*   system specific segment types */
+#define PT_LOPROC	0x70000000	/* reserved range for processor */
+#define PT_HIPROC	0x7fffffff	/*  specific segment types */
+
+/* Segment flags - p_flags */
+#define PF_X		0x1		/* Executable */
+#define PF_W		0x2		/* Writable */
+#define PF_R		0x4		/* Readable */
+#define PF_MASKOS	0x0ff00000	/* OS specific segment flags */
+#define PF_MASKPROC	0xf0000000	/* reserved bits for processor */
+					/*  specific segment flags */
+/* Dynamic structure */
+typedef struct
+{
+	Elf32_Sword	d_tag;		/* controls meaning of d_val */
+	union
+	{
+		Elf32_Word	d_val;	/* Multiple meanings - see d_tag */
+		Elf32_Addr	d_ptr;	/* program virtual address */
+	} d_un;
+} Elf32_Dyn;
+
+extern Elf32_Dyn	_DYNAMIC[];
+
+/* Dynamic Array Tags - d_tag */
+#define DT_NULL		0		/* marks end of _DYNAMIC array */
+#define DT_NEEDED	1		/* string table offset of needed lib */
+#define DT_PLTRELSZ	2		/* size of relocation entries in PLT */
+#define DT_PLTGOT	3		/* address PLT/GOT */
+#define DT_HASH		4		/* address of symbol hash table */
+#define DT_STRTAB	5		/* address of string table */
+#define DT_SYMTAB	6		/* address of symbol table */
+#define DT_RELA		7		/* address of relocation table */
+#define DT_RELASZ	8		/* size of relocation table */
+#define DT_RELAENT	9		/* size of relocation entry */
+#define DT_STRSZ	10		/* size of string table */
+#define DT_SYMENT	11		/* size of symbol table entry */
+#define DT_INIT		12		/* address of initialization func. */
+#define DT_FINI		13		/* address of termination function */
+#define DT_SONAME	14		/* string table offset of shared obj */
+#define DT_RPATH	15		/* string table offset of library
+					   search path */
+#define DT_SYMBOLIC	16		/* start sym search in shared obj. */
+#define DT_REL		17		/* address of rel. tbl. w addends */
+#define DT_RELSZ	18		/* size of DT_REL relocation table */
+#define DT_RELENT	19		/* size of DT_REL relocation entry */
+#define DT_PLTREL	20		/* PLT referenced relocation entry */
+#define DT_DEBUG	21		/* bugger */
+#define DT_TEXTREL	22		/* Allow rel. mod. to unwritable seg */
+#define DT_JMPREL	23		/* add. of PLT's relocation entries */
+#define DT_BIND_NOW	24		/* Process relocations of object */
+#define DT_INIT_ARRAY	25		/* Array with addresses of init fct */
+#define DT_FINI_ARRAY	26		/* Array with addresses of fini fct */
+#define DT_INIT_ARRAYSZ	27		/* Size in bytes of DT_INIT_ARRAY */
+#define DT_FINI_ARRAYSZ	28		/* Size in bytes of DT_FINI_ARRAY */
+#define DT_RUNPATH	29		/* Library search path */
+#define DT_FLAGS	30		/* Flags for the object being loaded */
+#define DT_ENCODING	32		/* Start of encoded range */
+#define DT_PREINIT_ARRAY 32		/* Array with addresses of preinit fct*/
+#define DT_PREINIT_ARRAYSZ 33		/* size in bytes of DT_PREINIT_ARRAY */
+#define DT_NUM		34		/* Number used. */
+#define DT_LOOS		0x60000000	/* reserved range for OS */
+#define DT_HIOS		0x6fffffff	/*   specific dynamic array tags */
+#define DT_LOPROC	0x70000000	/* reserved range for processor */
+#define DT_HIPROC	0x7fffffff	/*  specific dynamic array tags */
+
+/* Dynamic Tag Flags - d_un.d_val */
+#define DF_ORIGIN	0x01		/* Object may use DF_ORIGIN */
+#define DF_SYMBOLIC	0x02		/* Symbol resolutions starts here */
+#define DF_TEXTREL	0x04		/* Object contains text relocations */
+#define DF_BIND_NOW	0x08		/* No lazy binding for this object */
+#define DF_STATIC_TLS	0x10		/* Static thread local storage */
+
+/* Standard ELF hashing function */
+unsigned long elf_hash(const unsigned char *name);
+
+#define ELF_TARG_VER	1	/* The ver for which this code is intended */
+
+/*
+ * XXX - PowerPC defines really don't belong in here,
+ * but we'll put them in for simplicity.
+ */
+
+/* Values for Elf32/64_Ehdr.e_flags.  */
+#define EF_PPC_EMB              0x80000000      /* PowerPC embedded flag */
+
+/* Cygnus local bits below */
+#define EF_PPC_RELOCATABLE      0x00010000      /* PowerPC -mrelocatable flag*/
+#define EF_PPC_RELOCATABLE_LIB  0x00008000      /* PowerPC -mrelocatable-lib
+						   flag */
+
+/* PowerPC relocations defined by the ABIs */
+#define R_PPC_NONE              0
+#define R_PPC_ADDR32            1       /* 32bit absolute address */
+#define R_PPC_ADDR24            2       /* 26bit address, 2 bits ignored.  */
+#define R_PPC_ADDR16            3       /* 16bit absolute address */
+#define R_PPC_ADDR16_LO         4       /* lower 16bit of absolute address */
+#define R_PPC_ADDR16_HI         5       /* high 16bit of absolute address */
+#define R_PPC_ADDR16_HA         6       /* adjusted high 16bit */
+#define R_PPC_ADDR14            7       /* 16bit address, 2 bits ignored */
+#define R_PPC_ADDR14_BRTAKEN    8
+#define R_PPC_ADDR14_BRNTAKEN   9
+#define R_PPC_REL24             10      /* PC relative 26 bit */
+#define R_PPC_REL14             11      /* PC relative 16 bit */
+#define R_PPC_REL14_BRTAKEN     12
+#define R_PPC_REL14_BRNTAKEN    13
+#define R_PPC_GOT16             14
+#define R_PPC_GOT16_LO          15
+#define R_PPC_GOT16_HI          16
+#define R_PPC_GOT16_HA          17
+#define R_PPC_PLTREL24          18
+#define R_PPC_COPY              19
+#define R_PPC_GLOB_DAT          20
+#define R_PPC_JMP_SLOT          21
+#define R_PPC_RELATIVE          22
+#define R_PPC_LOCAL24PC         23
+#define R_PPC_UADDR32           24
+#define R_PPC_UADDR16           25
+#define R_PPC_REL32             26
+#define R_PPC_PLT32             27
+#define R_PPC_PLTREL32          28
+#define R_PPC_PLT16_LO          29
+#define R_PPC_PLT16_HI          30
+#define R_PPC_PLT16_HA          31
+#define R_PPC_SDAREL16          32
+#define R_PPC_SECTOFF           33
+#define R_PPC_SECTOFF_LO        34
+#define R_PPC_SECTOFF_HI        35
+#define R_PPC_SECTOFF_HA        36
+/* Keep this the last entry.  */
+#define R_PPC_NUM               37
+
+/* The remaining relocs are from the Embedded ELF ABI, and are not
+   in the SVR4 ELF ABI.  */
+#define R_PPC_EMB_NADDR32       101
+#define R_PPC_EMB_NADDR16       102
+#define R_PPC_EMB_NADDR16_LO    103
+#define R_PPC_EMB_NADDR16_HI    104
+#define R_PPC_EMB_NADDR16_HA    105
+#define R_PPC_EMB_SDAI16        106
+#define R_PPC_EMB_SDA2I16       107
+#define R_PPC_EMB_SDA2REL       108
+#define R_PPC_EMB_SDA21         109     /* 16 bit offset in SDA */
+#define R_PPC_EMB_MRKREF        110
+#define R_PPC_EMB_RELSEC16      111
+#define R_PPC_EMB_RELST_LO      112
+#define R_PPC_EMB_RELST_HI      113
+#define R_PPC_EMB_RELST_HA      114
+#define R_PPC_EMB_BIT_FLD       115
+#define R_PPC_EMB_RELSDA        116     /* 16 bit relative offset in SDA */
+
+/* Diab tool relocations.  */
+#define R_PPC_DIAB_SDA21_LO     180     /* like EMB_SDA21, but lower 16 bit */
+#define R_PPC_DIAB_SDA21_HI     181     /* like EMB_SDA21, but high 16 bit */
+#define R_PPC_DIAB_SDA21_HA     182     /* like EMB_SDA21, adjusted high 16 */
+#define R_PPC_DIAB_RELSDA_LO    183     /* like EMB_RELSDA, but lower 16 bit */
+#define R_PPC_DIAB_RELSDA_HI    184     /* like EMB_RELSDA, but high 16 bit */
+#define R_PPC_DIAB_RELSDA_HA    185     /* like EMB_RELSDA, adjusted high 16 */
+
+/* This is a phony reloc to handle any old fashioned TOC16 references
+   that may still be in object files.  */
+#define R_PPC_TOC16             255
+
+#endif /* _ELF_H */
diff --git a/qemu/roms/u-boot/include/env_attr.h b/qemu/roms/u-boot/include/env_attr.h
new file mode 100644
index 000000000..b82fec91b
--- /dev/null
+++ b/qemu/roms/u-boot/include/env_attr.h
@@ -0,0 +1,39 @@
+/*
+ * (C) Copyright 2012
+ * Joe Hershberger, National Instruments, joe.hershberger@ni.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ENV_ATTR_H__
+#define __ENV_ATTR_H__
+
+#define ENV_ATTR_LIST_DELIM	','
+#define ENV_ATTR_SEP		':'
+
+/*
+ * env_attr_walk takes as input an "attr_list" that takes the form:
+ *	attributes = [^,:\s]*
+ *	entry = name[:attributes]
+ *	list = entry[,list]
+ * It will call the "callback" function with the "name" and attribute as "value"
+ * The callback may return a non-0 to abort the list walk.
+ * This return value will be passed through to the caller.
+ * 0 is returned on success.
+ */
+extern int env_attr_walk(const char *attr_list,
+	int (*callback)(const char *name, const char *value));
+
+/*
+ * env_attr_lookup takes as input an "attr_list" with the same form as above.
+ * It also takes as input a "name" to look for.
+ * If the name is found in the list, it's value is copied into "attributes".
+ * There is no protection on attributes being too small for the value.
+ * It returns -1 if attributes is NULL, 1 if "name" is not found, 2 if
+ * "attr_list" is NULL.
+ * Returns 0 on success.
+ */
+extern int env_attr_lookup(const char *attr_list, const char *name,
+	char *attributes);
+
+#endif /* __ENV_ATTR_H__ */
diff --git a/qemu/roms/u-boot/include/env_callback.h b/qemu/roms/u-boot/include/env_callback.h
new file mode 100644
index 000000000..f90a7fa3b
--- /dev/null
+++ b/qemu/roms/u-boot/include/env_callback.h
@@ -0,0 +1,73 @@
+/*
+ * (C) Copyright 2012
+ * Joe Hershberger, National Instruments, joe.hershberger@ni.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ENV_CALLBACK_H__
+#define __ENV_CALLBACK_H__
+
+#include <env_flags.h>
+#include <linker_lists.h>
+#include <search.h>
+
+#define ENV_CALLBACK_VAR ".callbacks"
+
+/* Board configs can define additional static callback bindings */
+#ifndef CONFIG_ENV_CALLBACK_LIST_STATIC
+#define CONFIG_ENV_CALLBACK_LIST_STATIC
+#endif
+
+#ifdef CONFIG_SILENT_CONSOLE
+#define SILENT_CALLBACK "silent:silent,"
+#else
+#define SILENT_CALLBACK
+#endif
+
+#ifdef CONFIG_SPLASHIMAGE_GUARD
+#define SPLASHIMAGE_CALLBACK "splashimage:splashimage,"
+#else
+#define SPLASHIMAGE_CALLBACK
+#endif
+
+/*
+ * This list of callback bindings is static, but may be overridden by defining
+ * a new association in the ".callbacks" environment variable.
+ */
+#define ENV_CALLBACK_LIST_STATIC ENV_CALLBACK_VAR ":callbacks," \
+	ENV_FLAGS_VAR ":flags," \
+	"baudrate:baudrate," \
+	"bootfile:bootfile," \
+	"loadaddr:loadaddr," \
+	SILENT_CALLBACK \
+	SPLASHIMAGE_CALLBACK \
+	"stdin:console,stdout:console,stderr:console," \
+	CONFIG_ENV_CALLBACK_LIST_STATIC
+
+struct env_clbk_tbl {
+	const char *name;		/* Callback name */
+	int (*callback)(const char *name, const char *value, enum env_op op,
+		int flags);
+};
+
+void env_callback_init(ENTRY *var_entry);
+
+/*
+ * Define a callback that can be associated with variables.
+ * when associated through the ".callbacks" environment variable, the callback
+ * will be executed any time the variable is inserted, overwritten, or deleted.
+ */
+#ifdef CONFIG_SPL_BUILD
+#define U_BOOT_ENV_CALLBACK(name, callback) \
+	static inline void _u_boot_env_noop_##name(void) \
+	{ \
+		(void)callback; \
+	}
+#else
+#define U_BOOT_ENV_CALLBACK(name, callback) \
+	ll_entry_declare(struct env_clbk_tbl, name, env_clbk) = \
+	{#name, callback}
+#endif
+
+#endif /* __ENV_CALLBACK_H__ */
diff --git a/qemu/roms/u-boot/include/env_default.h b/qemu/roms/u-boot/include/env_default.h
new file mode 100644
index 000000000..90431beb1
--- /dev/null
+++ b/qemu/roms/u-boot/include/env_default.h
@@ -0,0 +1,128 @@
+/*
+ * (C) Copyright 2000-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Andreas Heppel <aheppel@sysgo.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <env_callback.h>
+
+#ifdef DEFAULT_ENV_INSTANCE_EMBEDDED
+env_t environment __PPCENV__ = {
+	ENV_CRC,	/* CRC Sum */
+#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT
+	1,		/* Flags: valid */
+#endif
+	{
+#elif defined(DEFAULT_ENV_INSTANCE_STATIC)
+static char default_environment[] = {
+#else
+const uchar default_environment[] = {
+#endif
+#ifdef	CONFIG_ENV_CALLBACK_LIST_DEFAULT
+	ENV_CALLBACK_VAR "=" CONFIG_ENV_CALLBACK_LIST_DEFAULT "\0"
+#endif
+#ifdef	CONFIG_ENV_FLAGS_LIST_DEFAULT
+	ENV_FLAGS_VAR "=" CONFIG_ENV_FLAGS_LIST_DEFAULT "\0"
+#endif
+#ifdef	CONFIG_BOOTARGS
+	"bootargs="	CONFIG_BOOTARGS			"\0"
+#endif
+#ifdef	CONFIG_BOOTCOMMAND
+	"bootcmd="	CONFIG_BOOTCOMMAND		"\0"
+#endif
+#ifdef	CONFIG_RAMBOOTCOMMAND
+	"ramboot="	CONFIG_RAMBOOTCOMMAND		"\0"
+#endif
+#ifdef	CONFIG_NFSBOOTCOMMAND
+	"nfsboot="	CONFIG_NFSBOOTCOMMAND		"\0"
+#endif
+#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0)
+	"bootdelay="	__stringify(CONFIG_BOOTDELAY)	"\0"
+#endif
+#if defined(CONFIG_BAUDRATE) && (CONFIG_BAUDRATE >= 0)
+	"baudrate="	__stringify(CONFIG_BAUDRATE)	"\0"
+#endif
+#ifdef	CONFIG_LOADS_ECHO
+	"loads_echo="	__stringify(CONFIG_LOADS_ECHO)	"\0"
+#endif
+#ifdef	CONFIG_ETHADDR
+	"ethaddr="	__stringify(CONFIG_ETHADDR)	"\0"
+#endif
+#ifdef	CONFIG_ETH1ADDR
+	"eth1addr="	__stringify(CONFIG_ETH1ADDR)	"\0"
+#endif
+#ifdef	CONFIG_ETH2ADDR
+	"eth2addr="	__stringify(CONFIG_ETH2ADDR)	"\0"
+#endif
+#ifdef	CONFIG_ETH3ADDR
+	"eth3addr="	__stringify(CONFIG_ETH3ADDR)	"\0"
+#endif
+#ifdef	CONFIG_ETH4ADDR
+	"eth4addr="	__stringify(CONFIG_ETH4ADDR)	"\0"
+#endif
+#ifdef	CONFIG_ETH5ADDR
+	"eth5addr="	__stringify(CONFIG_ETH5ADDR)	"\0"
+#endif
+#ifdef	CONFIG_ETHPRIME
+	"ethprime="	CONFIG_ETHPRIME			"\0"
+#endif
+#ifdef	CONFIG_IPADDR
+	"ipaddr="	__stringify(CONFIG_IPADDR)	"\0"
+#endif
+#ifdef	CONFIG_SERVERIP
+	"serverip="	__stringify(CONFIG_SERVERIP)	"\0"
+#endif
+#ifdef	CONFIG_SYS_AUTOLOAD
+	"autoload="	CONFIG_SYS_AUTOLOAD		"\0"
+#endif
+#ifdef	CONFIG_PREBOOT
+	"preboot="	CONFIG_PREBOOT			"\0"
+#endif
+#ifdef	CONFIG_ROOTPATH
+	"rootpath="	CONFIG_ROOTPATH			"\0"
+#endif
+#ifdef	CONFIG_GATEWAYIP
+	"gatewayip="	__stringify(CONFIG_GATEWAYIP)	"\0"
+#endif
+#ifdef	CONFIG_NETMASK
+	"netmask="	__stringify(CONFIG_NETMASK)	"\0"
+#endif
+#ifdef	CONFIG_HOSTNAME
+	"hostname="	__stringify(CONFIG_HOSTNAME)	"\0"
+#endif
+#ifdef	CONFIG_BOOTFILE
+	"bootfile="	CONFIG_BOOTFILE			"\0"
+#endif
+#ifdef	CONFIG_LOADADDR
+	"loadaddr="	__stringify(CONFIG_LOADADDR)	"\0"
+#endif
+#ifdef	CONFIG_CLOCKS_IN_MHZ
+	"clocks_in_mhz=1\0"
+#endif
+#if defined(CONFIG_PCI_BOOTDELAY) && (CONFIG_PCI_BOOTDELAY > 0)
+	"pcidelay="	__stringify(CONFIG_PCI_BOOTDELAY)"\0"
+#endif
+#ifdef	CONFIG_ENV_VARS_UBOOT_CONFIG
+	"arch="		CONFIG_SYS_ARCH			"\0"
+	"cpu="		CONFIG_SYS_CPU			"\0"
+	"board="	CONFIG_SYS_BOARD		"\0"
+	"board_name="	CONFIG_SYS_BOARD		"\0"
+#ifdef CONFIG_SYS_VENDOR
+	"vendor="	CONFIG_SYS_VENDOR		"\0"
+#endif
+#ifdef CONFIG_SYS_SOC
+	"soc="		CONFIG_SYS_SOC			"\0"
+#endif
+#endif
+#ifdef	CONFIG_EXTRA_ENV_SETTINGS
+	CONFIG_EXTRA_ENV_SETTINGS
+#endif
+	"\0"
+#ifdef DEFAULT_ENV_INSTANCE_EMBEDDED
+	}
+#endif
+};
diff --git a/qemu/roms/u-boot/include/env_flags.h b/qemu/roms/u-boot/include/env_flags.h
new file mode 100644
index 000000000..3ef631105
--- /dev/null
+++ b/qemu/roms/u-boot/include/env_flags.h
@@ -0,0 +1,156 @@
+/*
+ * (C) Copyright 2012
+ * Joe Hershberger, National Instruments, joe.hershberger@ni.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ENV_FLAGS_H__
+#define __ENV_FLAGS_H__
+
+enum env_flags_vartype {
+	env_flags_vartype_string,
+	env_flags_vartype_decimal,
+	env_flags_vartype_hex,
+	env_flags_vartype_bool,
+#ifdef CONFIG_CMD_NET
+	env_flags_vartype_ipaddr,
+	env_flags_vartype_macaddr,
+#endif
+	env_flags_vartype_end
+};
+
+enum env_flags_varaccess {
+	env_flags_varaccess_any,
+	env_flags_varaccess_readonly,
+	env_flags_varaccess_writeonce,
+	env_flags_varaccess_changedefault,
+	env_flags_varaccess_end
+};
+
+#define ENV_FLAGS_VAR ".flags"
+#define ENV_FLAGS_ATTR_MAX_LEN 2
+#define ENV_FLAGS_VARTYPE_LOC 0
+#define ENV_FLAGS_VARACCESS_LOC 1
+
+#ifndef CONFIG_ENV_FLAGS_LIST_STATIC
+#define CONFIG_ENV_FLAGS_LIST_STATIC ""
+#endif
+
+#ifdef CONFIG_CMD_NET
+#ifdef CONFIG_ENV_OVERWRITE
+#define ETHADDR_FLAGS "ethaddr:ma,"
+#else
+#ifdef CONFIG_OVERWRITE_ETHADDR_ONCE
+#define ETHADDR_FLAGS "ethaddr:mc,"
+#else
+#define ETHADDR_FLAGS "ethaddr:mo,"
+#endif
+#endif
+#else
+#define ETHADDR_FLAGS ""
+#endif
+
+#ifndef CONFIG_ENV_OVERWRITE
+#define SERIAL_FLAGS "serial#:so,"
+#else
+#define SERIAL_FLAGS ""
+#endif
+
+#define ENV_FLAGS_LIST_STATIC \
+	ETHADDR_FLAGS \
+	SERIAL_FLAGS \
+	CONFIG_ENV_FLAGS_LIST_STATIC
+
+#ifdef CONFIG_CMD_ENV_FLAGS
+/*
+ * Print the whole list of available type flags.
+ */
+void env_flags_print_vartypes(void);
+/*
+ * Print the whole list of available access flags.
+ */
+void env_flags_print_varaccess(void);
+/*
+ * Return the name of the type.
+ */
+const char *env_flags_get_vartype_name(enum env_flags_vartype type);
+/*
+ * Return the name of the access.
+ */
+const char *env_flags_get_varaccess_name(enum env_flags_varaccess access);
+#endif
+
+/*
+ * Parse the flags string from a .flags attribute list into the vartype enum.
+ */
+enum env_flags_vartype env_flags_parse_vartype(const char *flags);
+/*
+ * Parse the flags string from a .flags attribute list into the varaccess enum.
+ */
+enum env_flags_varaccess env_flags_parse_varaccess(const char *flags);
+/*
+ * Parse the binary flags from a hash table entry into the varaccess enum.
+ */
+enum env_flags_varaccess env_flags_parse_varaccess_from_binflags(int binflags);
+
+#ifdef USE_HOSTCC
+/*
+ * Look up the type of a variable directly from the .flags var.
+ */
+enum env_flags_vartype env_flags_get_type(const char *name);
+/*
+ * Look up the access of a variable directly from the .flags var.
+ */
+enum env_flags_varaccess env_flags_get_access(const char *name);
+/*
+ * Validate the newval for its type to conform with the requirements defined by
+ * its flags (directly looked at the .flags var).
+ */
+int env_flags_validate_type(const char *name, const char *newval);
+/*
+ * Validate the newval for its access to conform with the requirements defined
+ * by its flags (directly looked at the .flags var).
+ */
+int env_flags_validate_access(const char *name, int check_mask);
+/*
+ * Validate that the proposed access to variable "name" is valid according to
+ * the defined flags for that variable, if any.
+ */
+int env_flags_validate_varaccess(const char *name, int check_mask);
+/*
+ * Validate the parameters passed to "env set" for type compliance
+ */
+int env_flags_validate_env_set_params(int argc, char * const argv[]);
+
+#else /* !USE_HOSTCC */
+
+#include <search.h>
+
+/*
+ * When adding a variable to the environment, initialize the flags for that
+ * variable.
+ */
+void env_flags_init(ENTRY *var_entry);
+
+/*
+ * Validate the newval for to conform with the requirements defined by its flags
+ */
+int env_flags_validate(const ENTRY *item, const char *newval, enum env_op op,
+	int flag);
+
+#endif /* USE_HOSTCC */
+
+/*
+ * These are the binary flags used in the environment entry->flags variable to
+ * decribe properties of veriables in the table
+ */
+#define ENV_FLAGS_VARTYPE_BIN_MASK			0x00000007
+/* The actual variable type values use the enum value (within the mask) */
+#define ENV_FLAGS_VARACCESS_PREVENT_DELETE		0x00000008
+#define ENV_FLAGS_VARACCESS_PREVENT_CREATE		0x00000010
+#define ENV_FLAGS_VARACCESS_PREVENT_OVERWR		0x00000020
+#define ENV_FLAGS_VARACCESS_PREVENT_NONDEF_OVERWR	0x00000040
+#define ENV_FLAGS_VARACCESS_BIN_MASK			0x00000078
+
+#endif /* __ENV_FLAGS_H__ */
diff --git a/qemu/roms/u-boot/include/environment.h b/qemu/roms/u-boot/include/environment.h
new file mode 100644
index 000000000..08679aead
--- /dev/null
+++ b/qemu/roms/u-boot/include/environment.h
@@ -0,0 +1,219 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ENVIRONMENT_H_
+#define _ENVIRONMENT_H_
+
+/**************************************************************************
+ *
+ * The "environment" is stored as a list of '\0' terminated
+ * "name=value" strings. The end of the list is marked by a double
+ * '\0'. New entries are always added at the end. Deleting an entry
+ * shifts the remaining entries to the front. Replacing an entry is a
+ * combination of deleting the old value and adding the new one.
+ *
+ * The environment is preceeded by a 32 bit CRC over the data part.
+ *
+ **************************************************************************
+ */
+
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+# ifndef	CONFIG_ENV_ADDR
+#  define	CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+# endif
+# ifndef	CONFIG_ENV_OFFSET
+#  define	CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
+# endif
+# if !defined(CONFIG_ENV_ADDR_REDUND) && defined(CONFIG_ENV_OFFSET_REDUND)
+#  define	CONFIG_ENV_ADDR_REDUND	\
+		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET_REDUND)
+# endif
+# if defined(CONFIG_ENV_SECT_SIZE) || defined(CONFIG_ENV_SIZE)
+#  ifndef	CONFIG_ENV_SECT_SIZE
+#   define	CONFIG_ENV_SECT_SIZE	CONFIG_ENV_SIZE
+#  endif
+#  ifndef	CONFIG_ENV_SIZE
+#   define	CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
+#  endif
+# else
+#  error "Both CONFIG_ENV_SECT_SIZE and CONFIG_ENV_SIZE undefined"
+# endif
+# if defined(CONFIG_ENV_ADDR_REDUND) && !defined(CONFIG_ENV_SIZE_REDUND)
+#  define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+# endif
+# if	(CONFIG_ENV_ADDR >= CONFIG_SYS_MONITOR_BASE) &&		\
+	(CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) <=			\
+	(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#  define ENV_IS_EMBEDDED
+# endif
+# if defined(CONFIG_ENV_ADDR_REDUND) || defined(CONFIG_ENV_OFFSET_REDUND)
+#  define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+# endif
+# ifdef CONFIG_ENV_IS_EMBEDDED
+#  error "do not define CONFIG_ENV_IS_EMBEDDED in your board config"
+#  error "it is calculated automatically for you"
+# endif
+#endif	/* CONFIG_ENV_IS_IN_FLASH */
+
+#if defined(CONFIG_ENV_IS_IN_MMC)
+# ifdef CONFIG_ENV_OFFSET_REDUND
+#  define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+# endif
+#endif
+
+#if defined(CONFIG_ENV_IS_IN_NAND)
+# if defined(CONFIG_ENV_OFFSET_OOB)
+#  ifdef CONFIG_ENV_OFFSET_REDUND
+#   error "CONFIG_ENV_OFFSET_REDUND is not supported when CONFIG_ENV_OFFSET_OOB"
+#   error "is set"
+#  endif
+extern unsigned long nand_env_oob_offset;
+#  define CONFIG_ENV_OFFSET nand_env_oob_offset
+# else
+#  ifndef CONFIG_ENV_OFFSET
+#   error "Need to define CONFIG_ENV_OFFSET when using CONFIG_ENV_IS_IN_NAND"
+#  endif
+#  ifdef CONFIG_ENV_OFFSET_REDUND
+#   define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#  endif
+# endif /* CONFIG_ENV_OFFSET_OOB */
+# ifndef CONFIG_ENV_SIZE
+#  error "Need to define CONFIG_ENV_SIZE when using CONFIG_ENV_IS_IN_NAND"
+# endif
+#endif /* CONFIG_ENV_IS_IN_NAND */
+
+#if defined(CONFIG_ENV_IS_IN_UBI)
+# ifndef CONFIG_ENV_UBI_PART
+#  error "Need to define CONFIG_ENV_UBI_PART when using CONFIG_ENV_IS_IN_UBI"
+# endif
+# ifndef CONFIG_ENV_UBI_VOLUME
+#  error "Need to define CONFIG_ENV_UBI_VOLUME when using CONFIG_ENV_IS_IN_UBI"
+# endif
+# if defined(CONFIG_ENV_UBI_VOLUME_REDUND)
+#  define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+# endif
+# ifndef CONFIG_ENV_SIZE
+#  error "Need to define CONFIG_ENV_SIZE when using CONFIG_ENV_IS_IN_UBI"
+# endif
+# ifndef CONFIG_CMD_UBI
+#  error "Need to define CONFIG_CMD_UBI when using CONFIG_ENV_IS_IN_UBI"
+# endif
+#endif /* CONFIG_ENV_IS_IN_UBI */
+
+/* Embedded env is only supported for some flash types */
+#ifdef CONFIG_ENV_IS_EMBEDDED
+# if	!defined(CONFIG_ENV_IS_IN_FLASH)	&& \
+	!defined(CONFIG_ENV_IS_IN_NAND)		&& \
+	!defined(CONFIG_ENV_IS_IN_ONENAND)	&& \
+	!defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+#  error "CONFIG_ENV_IS_EMBEDDED not supported for your flash type"
+# endif
+#endif
+
+/*
+ * For the flash types where embedded env is supported, but it cannot be
+ * calculated automatically (i.e. NAND), take the board opt-in.
+ */
+#if defined(CONFIG_ENV_IS_EMBEDDED) && !defined(ENV_IS_EMBEDDED)
+# define ENV_IS_EMBEDDED
+#endif
+
+/* The build system likes to know if the env is embedded */
+#ifdef DO_DEPS_ONLY
+# ifdef ENV_IS_EMBEDDED
+#  ifndef CONFIG_ENV_IS_EMBEDDED
+#   define CONFIG_ENV_IS_EMBEDDED
+#  endif
+# endif
+#endif
+
+#include "compiler.h"
+
+#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT
+# define ENV_HEADER_SIZE	(sizeof(uint32_t) + 1)
+
+# define ACTIVE_FLAG   1
+# define OBSOLETE_FLAG 0
+#else
+# define ENV_HEADER_SIZE	(sizeof(uint32_t))
+#endif
+
+#if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_ENV_IS_NOWHERE)
+extern char *env_name_spec;
+#endif
+
+#ifdef CONFIG_ENV_AES
+/* Make sure the payload is multiple of AES block size */
+#define ENV_SIZE ((CONFIG_ENV_SIZE - ENV_HEADER_SIZE) & ~(16 - 1))
+#else
+#define ENV_SIZE (CONFIG_ENV_SIZE - ENV_HEADER_SIZE)
+#endif
+
+typedef struct environment_s {
+	uint32_t	crc;		/* CRC32 over data bytes	*/
+#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT
+	unsigned char	flags;		/* active/obsolete flags	*/
+#endif
+	unsigned char	data[ENV_SIZE]; /* Environment data		*/
+} env_t
+#ifdef CONFIG_ENV_AES
+/* Make sure the env is aligned to block size. */
+__attribute__((aligned(16)))
+#endif
+;
+
+#ifdef ENV_IS_EMBEDDED
+extern env_t environment;
+#endif /* ENV_IS_EMBEDDED */
+
+extern const unsigned char default_environment[];
+extern env_t *env_ptr;
+
+extern void env_relocate_spec(void);
+extern unsigned char env_get_char_spec(int);
+
+#if defined(CONFIG_NEEDS_MANUAL_RELOC)
+extern void env_reloc(void);
+#endif
+
+#ifndef DO_DEPS_ONLY
+
+#include <env_attr.h>
+#include <env_callback.h>
+#include <env_flags.h>
+#include <search.h>
+
+extern struct hsearch_data env_htab;
+
+/* Function that returns a character from the environment */
+unsigned char env_get_char(int);
+
+/* Function that returns a pointer to a value from the environment */
+const unsigned char *env_get_addr(int);
+unsigned char env_get_char_memory(int index);
+
+/* Function that updates CRC of the enironment */
+void env_crc_update(void);
+
+/* Look up the variable from the default environment */
+char *getenv_default(const char *name);
+
+/* [re]set to the default environment */
+void set_default_env(const char *s);
+
+/* [re]set individual variables to their value in the default environment */
+int set_default_vars(int nvars, char * const vars[]);
+
+/* Import from binary representation into hash table */
+int env_import(const char *buf, int check);
+
+/* Export from hash table into binary representation */
+int env_export(env_t *env_out);
+
+#endif /* DO_DEPS_ONLY */
+
+#endif /* _ENVIRONMENT_H_ */
diff --git a/qemu/roms/u-boot/include/errno.h b/qemu/roms/u-boot/include/errno.h
new file mode 100644
index 000000000..e24a33b38
--- /dev/null
+++ b/qemu/roms/u-boot/include/errno.h
@@ -0,0 +1,9 @@
+#ifndef _ERRNO_H
+
+#include <asm-generic/errno.h>
+
+extern int errno;
+
+#define __set_errno(val) do { errno = val; } while (0)
+
+#endif /* _ERRNO_H */
diff --git a/qemu/roms/u-boot/include/exports.h b/qemu/roms/u-boot/include/exports.h
new file mode 100644
index 000000000..41d5085e1
--- /dev/null
+++ b/qemu/roms/u-boot/include/exports.h
@@ -0,0 +1,51 @@
+#ifndef __EXPORTS_H__
+#define __EXPORTS_H__
+
+#ifndef __ASSEMBLY__
+
+/* These are declarations of exported functions available in C code */
+unsigned long get_version(void);
+int  getc(void);
+int  tstc(void);
+void putc(const char);
+void puts(const char*);
+int printf(const char* fmt, ...);
+void install_hdlr(int, void (*interrupt_handler_t)(void *), void*);
+void free_hdlr(int);
+void *malloc(size_t);
+void free(void*);
+void __udelay(unsigned long);
+unsigned long get_timer(unsigned long);
+int vprintf(const char *, va_list);
+unsigned long simple_strtoul(const char *cp,char **endp,unsigned int base);
+int strict_strtoul(const char *cp, unsigned int base, unsigned long *res);
+char *getenv (const char *name);
+int setenv (const char *varname, const char *varvalue);
+long simple_strtol(const char *cp,char **endp,unsigned int base);
+int strcmp(const char * cs,const char * ct);
+unsigned long ustrtoul(const char *cp, char **endp, unsigned int base);
+unsigned long long ustrtoull(const char *cp, char **endp, unsigned int base);
+#if defined(CONFIG_CMD_I2C)
+int i2c_write (uchar, uint, int , uchar* , int);
+int i2c_read (uchar, uint, int , uchar* , int);
+#endif
+
+void app_startup(char * const *);
+
+#endif    /* ifndef __ASSEMBLY__ */
+
+enum {
+#define EXPORT_FUNC(x) XF_ ## x ,
+#include <_exports.h>
+#undef EXPORT_FUNC
+
+	XF_MAX
+};
+
+#define XF_VERSION	6
+
+#if defined(CONFIG_X86)
+extern gd_t *global_data;
+#endif
+
+#endif	/* __EXPORTS_H__ */
diff --git a/qemu/roms/u-boot/include/ext4fs.h b/qemu/roms/u-boot/include/ext4fs.h
new file mode 100644
index 000000000..fbbb002b1
--- /dev/null
+++ b/qemu/roms/u-boot/include/ext4fs.h
@@ -0,0 +1,147 @@
+/*
+ * (C) Copyright 2011 - 2012 Samsung Electronics
+ * EXT4 filesystem implementation in Uboot by
+ * Uma Shankar <uma.shankar@samsung.com>
+ * Manjunatha C Achar <a.manjunatha@samsung.com>
+ *
+ * Ext4 Extent data structures are taken from  original ext4 fs code
+ * as found in the linux kernel.
+ *
+ * Copyright (c) 2003-2006, Cluster File Systems, Inc, info@clusterfs.com
+ * Written by Alex Tomas <alex@clusterfs.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __EXT4__
+#define __EXT4__
+#include <ext_common.h>
+
+#define EXT4_EXTENTS_FL		0x00080000 /* Inode uses extents */
+#define EXT4_EXT_MAGIC			0xf30a
+#define EXT4_FEATURE_RO_COMPAT_GDT_CSUM	0x0010
+#define EXT4_FEATURE_INCOMPAT_EXTENTS	0x0040
+#define EXT4_INDIRECT_BLOCKS		12
+
+#define EXT4_BG_INODE_UNINIT		0x0001
+#define EXT4_BG_BLOCK_UNINIT		0x0002
+#define EXT4_BG_INODE_ZEROED		0x0004
+
+/*
+ * ext4_inode has i_block array (60 bytes total).
+ * The first 12 bytes store ext4_extent_header;
+ * the remainder stores an array of ext4_extent.
+ */
+
+/*
+ * This is the extent on-disk structure.
+ * It's used at the bottom of the tree.
+ */
+struct ext4_extent {
+	__le32	ee_block;	/* first logical block extent covers */
+	__le16	ee_len;		/* number of blocks covered by extent */
+	__le16	ee_start_hi;	/* high 16 bits of physical block */
+	__le32	ee_start_lo;	/* low 32 bits of physical block */
+};
+
+/*
+ * This is index on-disk structure.
+ * It's used at all the levels except the bottom.
+ */
+struct ext4_extent_idx {
+	__le32	ei_block;	/* index covers logical blocks from 'block' */
+	__le32	ei_leaf_lo;	/* pointer to the physical block of the next *
+				 * level. leaf or next index could be there */
+	__le16	ei_leaf_hi;	/* high 16 bits of physical block */
+	__u16	ei_unused;
+};
+
+/* Each block (leaves and indexes), even inode-stored has header. */
+struct ext4_extent_header {
+	__le16	eh_magic;	/* probably will support different formats */
+	__le16	eh_entries;	/* number of valid entries */
+	__le16	eh_max;		/* capacity of store in entries */
+	__le16	eh_depth;	/* has tree real underlying blocks? */
+	__le32	eh_generation;	/* generation of the tree */
+};
+
+struct ext_filesystem {
+	/* Total Sector of partition */
+	uint64_t total_sect;
+	/* Block size  of partition */
+	uint32_t blksz;
+	/* Inode size of partition */
+	uint32_t inodesz;
+	/* Sectors per Block */
+	uint32_t sect_perblk;
+	/* Group Descriptor Block Number */
+	uint32_t gdtable_blkno;
+	/* Total block groups of partition */
+	uint32_t no_blkgrp;
+	/* No of blocks required for bgdtable */
+	uint32_t no_blk_pergdt;
+	/* Superblock */
+	struct ext2_sblock *sb;
+	/* Block group descritpor table */
+	struct ext2_block_group *bgd;
+	char *gdtable;
+
+	/* Block Bitmap Related */
+	unsigned char **blk_bmaps;
+	long int curr_blkno;
+	uint16_t first_pass_bbmap;
+
+	/* Inode Bitmap Related */
+	unsigned char **inode_bmaps;
+	int curr_inode_no;
+	uint16_t first_pass_ibmap;
+
+	/* Journal Related */
+
+	/* Block Device Descriptor */
+	block_dev_desc_t *dev_desc;
+};
+
+extern struct ext2_data *ext4fs_root;
+extern struct ext2fs_node *ext4fs_file;
+
+#if defined(CONFIG_EXT4_WRITE)
+extern struct ext2_inode *g_parent_inode;
+extern int gd_index;
+extern int gindex;
+
+int ext4fs_init(void);
+void ext4fs_deinit(void);
+int ext4fs_filename_check(char *filename);
+int ext4fs_write(const char *fname, unsigned char *buffer,
+				unsigned long sizebytes);
+#endif
+
+struct ext_filesystem *get_fs(void);
+int ext4fs_open(const char *filename);
+int ext4fs_read(char *buf, unsigned len);
+int ext4fs_mount(unsigned part_length);
+void ext4fs_close(void);
+void ext4fs_reinit_global(void);
+int ext4fs_ls(const char *dirname);
+int ext4fs_exists(const char *filename);
+void ext4fs_free_node(struct ext2fs_node *node, struct ext2fs_node *currroot);
+int ext4fs_devread(lbaint_t sector, int byte_offset, int byte_len, char *buf);
+void ext4fs_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info);
+long int read_allocated_block(struct ext2_inode *inode, int fileblock);
+int ext4fs_probe(block_dev_desc_t *fs_dev_desc,
+		 disk_partition_t *fs_partition);
+int ext4_read_file(const char *filename, void *buf, int offset, int len);
+int ext4_read_superblock(char *buffer);
+#endif
diff --git a/qemu/roms/u-boot/include/ext_common.h b/qemu/roms/u-boot/include/ext_common.h
new file mode 100644
index 000000000..6cddf166d
--- /dev/null
+++ b/qemu/roms/u-boot/include/ext_common.h
@@ -0,0 +1,180 @@
+/*
+ * (C) Copyright 2011 - 2012 Samsung Electronics
+ * EXT4 filesystem implementation in Uboot by
+ * Uma Shankar <uma.shankar@samsung.com>
+ * Manjunatha C Achar <a.manjunatha@samsung.com>
+ *
+ * Data structures and headers for ext4 support have been taken from
+ * ext2 ls load support in Uboot
+ *
+ * (C) Copyright 2004
+ * esd gmbh <www.esd-electronics.com>
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ *
+ * based on code from grub2 fs/ext2.c and fs/fshelp.c by
+ * GRUB  --  GRand Unified Bootloader
+ * Copyright (C) 2003, 2004  Free Software Foundation, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __EXT_COMMON__
+#define __EXT_COMMON__
+#include <command.h>
+#define SECTOR_SIZE		0x200
+
+/* Magic value used to identify an ext2 filesystem.  */
+#define	EXT2_MAGIC			0xEF53
+/* Amount of indirect blocks in an inode.  */
+#define INDIRECT_BLOCKS			12
+/* Maximum lenght of a pathname.  */
+#define EXT2_PATH_MAX				4096
+/* Maximum nesting of symlinks, used to prevent a loop.  */
+#define	EXT2_MAX_SYMLINKCNT		8
+
+/* Filetype used in directory entry.  */
+#define	FILETYPE_UNKNOWN		0
+#define	FILETYPE_REG			1
+#define	FILETYPE_DIRECTORY		2
+#define	FILETYPE_SYMLINK		7
+
+/* Filetype information as used in inodes.  */
+#define FILETYPE_INO_MASK		0170000
+#define FILETYPE_INO_REG		0100000
+#define FILETYPE_INO_DIRECTORY		0040000
+#define FILETYPE_INO_SYMLINK		0120000
+#define EXT2_ROOT_INO			2 /* Root inode */
+
+/* The size of an ext2 block in bytes.  */
+#define EXT2_BLOCK_SIZE(data)	   (1 << LOG2_BLOCK_SIZE(data))
+
+/* Log2 size of ext2 block in bytes.  */
+#define LOG2_BLOCK_SIZE(data)	   (__le32_to_cpu		   \
+				    (data->sblock.log2_block_size) \
+				    + EXT2_MIN_BLOCK_LOG_SIZE)
+#define INODE_SIZE_FILESYSTEM(data)	(__le32_to_cpu \
+			(data->sblock.inode_size))
+
+#define EXT2_FT_DIR	2
+#define SUCCESS	1
+
+/* Macro-instructions used to manage several block sizes  */
+#define EXT2_MIN_BLOCK_LOG_SIZE	10 /* 1024 */
+#define EXT2_MAX_BLOCK_LOG_SIZE	16 /* 65536 */
+#define EXT2_MIN_BLOCK_SIZE		(1 << EXT2_MIN_BLOCK_LOG_SIZE)
+#define EXT2_MAX_BLOCK_SIZE		(1 << EXT2_MAX_BLOCK_LOG_SIZE)
+
+/* The ext2 superblock.  */
+struct ext2_sblock {
+	uint32_t total_inodes;
+	uint32_t total_blocks;
+	uint32_t reserved_blocks;
+	uint32_t free_blocks;
+	uint32_t free_inodes;
+	uint32_t first_data_block;
+	uint32_t log2_block_size;
+	uint32_t log2_fragment_size;
+	uint32_t blocks_per_group;
+	uint32_t fragments_per_group;
+	uint32_t inodes_per_group;
+	uint32_t mtime;
+	uint32_t utime;
+	uint16_t mnt_count;
+	uint16_t max_mnt_count;
+	uint16_t magic;
+	uint16_t fs_state;
+	uint16_t error_handling;
+	uint16_t minor_revision_level;
+	uint32_t lastcheck;
+	uint32_t checkinterval;
+	uint32_t creator_os;
+	uint32_t revision_level;
+	uint16_t uid_reserved;
+	uint16_t gid_reserved;
+	uint32_t first_inode;
+	uint16_t inode_size;
+	uint16_t block_group_number;
+	uint32_t feature_compatibility;
+	uint32_t feature_incompat;
+	uint32_t feature_ro_compat;
+	uint32_t unique_id[4];
+	char volume_name[16];
+	char last_mounted_on[64];
+	uint32_t compression_info;
+};
+
+struct ext2_block_group {
+	__u32 block_id;	/* Blocks bitmap block */
+	__u32 inode_id;	/* Inodes bitmap block */
+	__u32 inode_table_id;	/* Inodes table block */
+	__u16 free_blocks;	/* Free blocks count */
+	__u16 free_inodes;	/* Free inodes count */
+	__u16 used_dir_cnt;	/* Directories count */
+	__u16 bg_flags;
+	__u32 bg_reserved[2];
+	__u16 bg_itable_unused; /* Unused inodes count */
+	__u16 bg_checksum;	/* crc16(s_uuid+grouo_num+group_desc)*/
+};
+
+/* The ext2 inode. */
+struct ext2_inode {
+	uint16_t mode;
+	uint16_t uid;
+	uint32_t size;
+	uint32_t atime;
+	uint32_t ctime;
+	uint32_t mtime;
+	uint32_t dtime;
+	uint16_t gid;
+	uint16_t nlinks;
+	uint32_t blockcnt;	/* Blocks of 512 bytes!! */
+	uint32_t flags;
+	uint32_t osd1;
+	union {
+		struct datablocks {
+			uint32_t dir_blocks[INDIRECT_BLOCKS];
+			uint32_t indir_block;
+			uint32_t double_indir_block;
+			uint32_t triple_indir_block;
+		} blocks;
+		char symlink[60];
+	} b;
+	uint32_t version;
+	uint32_t acl;
+	uint32_t dir_acl;
+	uint32_t fragment_addr;
+	uint32_t osd2[3];
+};
+
+/* The header of an ext2 directory entry. */
+struct ext2_dirent {
+	uint32_t inode;
+	uint16_t direntlen;
+	uint8_t namelen;
+	uint8_t filetype;
+};
+
+struct ext2fs_node {
+	struct ext2_data *data;
+	struct ext2_inode inode;
+	int ino;
+	int inode_read;
+};
+
+/* Information about a "mounted" ext2 filesystem. */
+struct ext2_data {
+	struct ext2_sblock sblock;
+	struct ext2_inode *inode;
+	struct ext2fs_node diropen;
+};
+
+extern lbaint_t part_offset;
+
+int do_ext2ls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+int do_ext2load(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+int do_ext4_load(cmd_tbl_t *cmdtp, int flag, int argc,
+					char *const argv[]);
+int do_ext4_ls(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]);
+int do_ext4_write(cmd_tbl_t *cmdtp, int flag, int argc,
+				char *const argv[]);
+#endif
diff --git a/qemu/roms/u-boot/include/faraday/ftahbc020s.h b/qemu/roms/u-boot/include/faraday/ftahbc020s.h
new file mode 100644
index 000000000..ccae39095
--- /dev/null
+++ b/qemu/roms/u-boot/include/faraday/ftahbc020s.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* FTAHBC020S - AHB Controller (Arbiter/Decoder) definitions */
+#ifndef __FTAHBC020S_H
+#define __FTAHBC202S_H
+
+/* Registers Offsets */
+
+/*
+ * AHB Slave BSR, offset: n * 4, n=0~31
+ */
+#ifndef __ASSEMBLY__
+struct ftahbc02s {
+	unsigned int	s_bsr[32];	/* 0x00-0x7c - Slave n Base/Size Reg */
+	unsigned int	pcr;		/* 0x80	- Priority Ctrl Reg */
+	unsigned int	tcrg;		/* 0x84	- Transfer Ctrl Reg */
+	unsigned int	cr;		/* 0x88	- Ctrl Reg */
+};
+#endif /* __ASSEMBLY__ */
+
+/*
+ * FTAHBC020S_SLAVE_BSR - Slave n Base / Size Register
+ */
+#define FTAHBC020S_SLAVE_BSR_BASE(x)	(((x) & 0xfff) << 20)
+#define FTAHBC020S_SLAVE_BSR_SIZE(x)	(((x) & 0xf) << 16)
+/* The value of b(16:19)SLAVE_BSR_SIZE: 1M-2048M, must be power of 2 */
+#define FTAHBC020S_BSR_SIZE(x)		(ffs(x) - 1)	/* size of Addr Space */
+
+/*
+ * FTAHBC020S_PCR - Priority Control Register
+ */
+#define FTAHBC020S_PCR_PLEVEL_(x)	(1 << (x))	/* x: 1-15 */
+
+/*
+ * FTAHBC020S_CR - Interrupt Control Register
+ */
+#define FTAHBC020S_CR_INTSTS	(1 << 24)
+#define FTAHBC020S_CR_RESP(x)	(((x) & 0x3) << 20)
+#define FTAHBC020S_CR_INTSMASK	(1 << 16)
+#define FTAHBC020S_CR_REMAP	(1 << 0)
+
+#endif	/* __FTAHBC020S_H */
diff --git a/qemu/roms/u-boot/include/faraday/ftpci100.h b/qemu/roms/u-boot/include/faraday/ftpci100.h
new file mode 100644
index 000000000..43152aae2
--- /dev/null
+++ b/qemu/roms/u-boot/include/faraday/ftpci100.h
@@ -0,0 +1,84 @@
+/*
+ * Faraday FTPCI100 PCI Bridge Controller Device Driver Implementation
+ *
+ * Copyright (C) 2010 Andes Technology Corporation
+ * Gavin Guo, Andes Technology Corporation <gavinguo@andestech.com>
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __FTPCI100_H
+#define __FTPCI100_H
+
+/* AHB Control Registers */
+struct ftpci100_ahbc {
+	unsigned int iosize;		/* 0x00 - I/O Space Size Signal */
+	unsigned int prot;		/* 0x04 - AHB Protection */
+	unsigned int rsved[8];		/* 0x08-0x24 - Reserved */
+	unsigned int conf;		/* 0x28 - PCI Configuration */
+	unsigned int data;		/* 0x2c - PCI Configuration DATA */
+};
+
+/*
+ * FTPCI100_IOSIZE_REG's constant definitions
+ */
+#define FTPCI100_BASE_IO_SIZE(x)	(ffs(x) - 1)	/* 1M - 2048M */
+
+/*
+ * PCI Configuration Register
+ */
+#define PCI_INT_MASK			0x4c
+#define PCI_MEM_BASE_SIZE1		0x50
+#define PCI_MEM_BASE_SIZE2		0x54
+#define PCI_MEM_BASE_SIZE3		0x58
+
+/*
+ * PCI_INT_MASK's bit definitions
+ */
+#define PCI_INTA_ENABLE			(1 << 22)
+#define PCI_INTB_ENABLE			(1 << 23)
+#define PCI_INTC_ENABLE			(1 << 24)
+#define PCI_INTD_ENABLE			(1 << 25)
+
+/*
+ * PCI_MEM_BASE_SIZE1's constant definitions
+ */
+#define FTPCI100_BASE_ADR_SIZE(x)	((ffs(x) - 1) << 16)	/* 1M - 2048M */
+
+#define FTPCI100_MAX_FUNCTIONS		20
+#define PCI_IRQ_LINES			4
+
+#define MAX_BUS_NUM			256
+#define MAX_DEV_NUM			32
+#define MAX_FUN_NUM			8
+
+#define PCI_MAX_BAR_PER_FUNC		6
+
+/*
+ * PCI_MEM_SIZE
+ */
+#define FTPCI100_MEM_SIZE(x)		(ffs(x) << 24)
+
+/* This definition is used by pci_ftpci_init() */
+#define FTPCI100_BRIDGE_VENDORID		0x159b
+#define FTPCI100_BRIDGE_DEVICEID		0x4321
+
+void pci_ftpci_init(void);
+
+struct pcibar {
+	unsigned int size;
+	unsigned int addr;
+};
+
+struct pci_config {
+	unsigned int bus;
+	unsigned int dev;				/* device */
+	unsigned int func;
+	unsigned int pin;
+	unsigned short v_id;				/* vendor id */
+	unsigned short d_id;				/* device id */
+	struct pcibar bar[PCI_MAX_BAR_PER_FUNC + 1];
+};
+
+#endif
diff --git a/qemu/roms/u-boot/include/faraday/ftpmu010.h b/qemu/roms/u-boot/include/faraday/ftpmu010.h
new file mode 100644
index 000000000..b1131e5ae
--- /dev/null
+++ b/qemu/roms/u-boot/include/faraday/ftpmu010.h
@@ -0,0 +1,235 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Power Management Unit
+ */
+#ifndef __FTPMU010_H
+#define __FTPMU010_H
+
+#ifndef __ASSEMBLY__
+struct ftpmu010 {
+	unsigned int	IDNMBR0;	/* 0x00 */
+	unsigned int	reserved0;	/* 0x04 */
+	unsigned int	OSCC;		/* 0x08 */
+	unsigned int	PMODE;		/* 0x0C */
+	unsigned int	PMCR;		/* 0x10 */
+	unsigned int	PED;		/* 0x14 */
+	unsigned int	PEDSR;		/* 0x18 */
+	unsigned int	reserved1;	/* 0x1C */
+	unsigned int	PMSR;		/* 0x20 */
+	unsigned int	PGSR;		/* 0x24 */
+	unsigned int	MFPSR;		/* 0x28 */
+	unsigned int	MISC;		/* 0x2C */
+	unsigned int	PDLLCR0;	/* 0x30 */
+	unsigned int	PDLLCR1;	/* 0x34 */
+	unsigned int	AHBMCLKOFF;	/* 0x38 */
+	unsigned int	APBMCLKOFF;	/* 0x3C */
+	unsigned int	DCSRCR0;	/* 0x40 */
+	unsigned int	DCSRCR1;	/* 0x44 */
+	unsigned int	DCSRCR2;	/* 0x48 */
+	unsigned int	SDRAMHTC;	/* 0x4C */
+	unsigned int	PSPR0;		/* 0x50 */
+	unsigned int	PSPR1;		/* 0x54 */
+	unsigned int	PSPR2;		/* 0x58 */
+	unsigned int	PSPR3;		/* 0x5C */
+	unsigned int	PSPR4;		/* 0x60 */
+	unsigned int	PSPR5;		/* 0x64 */
+	unsigned int	PSPR6;		/* 0x68 */
+	unsigned int	PSPR7;		/* 0x6C */
+	unsigned int	PSPR8;		/* 0x70 */
+	unsigned int	PSPR9;		/* 0x74 */
+	unsigned int	PSPR10;		/* 0x78 */
+	unsigned int	PSPR11;		/* 0x7C */
+	unsigned int	PSPR12;		/* 0x80 */
+	unsigned int	PSPR13;		/* 0x84 */
+	unsigned int	PSPR14;		/* 0x88 */
+	unsigned int	PSPR15;		/* 0x8C */
+	unsigned int	AHBDMA_RACCS;	/* 0x90 */
+	unsigned int	reserved2;	/* 0x94 */
+	unsigned int	reserved3;	/* 0x98 */
+	unsigned int	JSS;		/* 0x9C */
+	unsigned int	CFC_RACC;	/* 0xA0 */
+	unsigned int	SSP1_RACC;	/* 0xA4 */
+	unsigned int	UART1TX_RACC;	/* 0xA8 */
+	unsigned int	UART1RX_RACC;	/* 0xAC */
+	unsigned int	UART2TX_RACC;	/* 0xB0 */
+	unsigned int	UART2RX_RACC;	/* 0xB4 */
+	unsigned int	SDC_RACC;	/* 0xB8 */
+	unsigned int	I2SAC97_RACC;	/* 0xBC */
+	unsigned int	IRDATX_RACC;	/* 0xC0 */
+	unsigned int	reserved4;	/* 0xC4 */
+	unsigned int	USBD_RACC;	/* 0xC8 */
+	unsigned int	IRDARX_RACC;	/* 0xCC */
+	unsigned int	IRDA_RACC;	/* 0xD0 */
+	unsigned int	ED0_RACC;	/* 0xD4 */
+	unsigned int	ED1_RACC;	/* 0xD8 */
+};
+#endif /* __ASSEMBLY__ */
+
+/*
+ * ID Number 0 Register
+ */
+#define FTPMU010_ID_A320A	0x03200000
+#define FTPMU010_ID_A320C	0x03200010
+#define FTPMU010_ID_A320D	0x03200030
+
+/*
+ * OSC Control Register
+ */
+#define FTPMU010_OSCC_OSCH_TRI		(1 << 11)
+#define FTPMU010_OSCC_OSCH_STABLE	(1 << 9)
+#define FTPMU010_OSCC_OSCH_OFF		(1 << 8)
+
+#define FTPMU010_OSCC_OSCL_TRI		(1 << 3)
+#define FTPMU010_OSCC_OSCL_RTCLSEL	(1 << 2)
+#define FTPMU010_OSCC_OSCL_STABLE	(1 << 1)
+#define FTPMU010_OSCC_OSCL_OFF		(1 << 0)
+
+/*
+ * Power Mode Register
+ */
+#define FTPMU010_PMODE_DIVAHBCLK_MASK	(0x7 << 4)
+#define FTPMU010_PMODE_DIVAHBCLK_2	(0x0 << 4)
+#define FTPMU010_PMODE_DIVAHBCLK_3	(0x1 << 4)
+#define FTPMU010_PMODE_DIVAHBCLK_4	(0x2 << 4)
+#define FTPMU010_PMODE_DIVAHBCLK_6	(0x3 << 4)
+#define FTPMU010_PMODE_DIVAHBCLK_8	(0x4 << 4)
+#define FTPMU010_PMODE_DIVAHBCLK(pmode)	(((pmode) >> 4) & 0x7)
+#define FTPMU010_PMODE_FCS		(1 << 2)
+#define FTPMU010_PMODE_TURBO		(1 << 1)
+#define FTPMU010_PMODE_SLEEP		(1 << 0)
+
+/*
+ * Power Manager Status Register
+ */
+#define FTPMU010_PMSR_SMR	(1 << 10)
+
+#define FTPMU010_PMSR_RDH	(1 << 2)
+#define FTPMU010_PMSR_PH	(1 << 1)
+#define FTPMU010_PMSR_CKEHLOW	(1 << 0)
+
+/*
+ * Multi-Function Port Setting Register
+ */
+#define FTPMU010_MFPSR_DEBUGSEL		(1 << 17)
+#define FTPMU010_MFPSR_DMA0PINSEL	(1 << 16)
+#define FTPMU010_MFPSR_DMA1PINSEL	(1 << 15)
+#define FTPMU010_MFPSR_MODEMPINSEL	(1 << 14)
+#define FTPMU010_MFPSR_AC97CLKOUTSEL	(1 << 13)
+#define FTPMU010_MFPSR_PWM1PINSEL	(1 << 11)
+#define FTPMU010_MFPSR_PWM0PINSEL	(1 << 10)
+#define FTPMU010_MFPSR_IRDACLKSEL	(1 << 9)
+#define FTPMU010_MFPSR_UARTCLKSEL	(1 << 8)
+#define FTPMU010_MFPSR_SSPCLKSEL	(1 << 6)
+#define FTPMU010_MFPSR_I2SCLKSEL	(1 << 5)
+#define FTPMU010_MFPSR_AC97CLKSEL	(1 << 4)
+#define FTPMU010_MFPSR_AC97PINSEL	(1 << 3)
+#define FTPMU010_MFPSR_TRIAHBDIS	(1 << 1)
+#define FTPMU010_MFPSR_TRIAHBDBG	(1 << 0)
+
+/*
+ * PLL/DLL Control Register 0
+ * Note:
+ *  1. FTPMU010_PDLLCR0_HCLKOUTDIS:
+ *	Datasheet indicated it starts at bit #21 which was wrong.
+ *  2. FTPMU010_PDLLCR0_DLLFRAG:
+ * 	Datasheet indicated it has 2 bit which was wrong.
+ */
+#define FTPMU010_PDLLCR0_HCLKOUTDIS(cr0)	(((cr0) & 0xf) << 20)
+#define FTPMU010_PDLLCR0_DLLFRAG(cr0)		(1 << 19)
+#define FTPMU010_PDLLCR0_DLLSTSEL		(1 << 18)
+#define FTPMU010_PDLLCR0_DLLSTABLE		(1 << 17)
+#define FTPMU010_PDLLCR0_DLLDIS			(1 << 16)
+#define FTPMU010_PDLLCR0_PLL1FRANG(cr0)		(((cr0) & 0x3) << 12)
+#define FTPMU010_PDLLCR0_PLL1NS(cr0)		(((cr0) & 0x1ff) << 3)
+#define FTPMU010_PDLLCR0_PLL1STSEL		(1 << 2)
+#define FTPMU010_PDLLCR0_PLL1STABLE		(1 << 1)
+#define FTPMU010_PDLLCR0_PLL1DIS		(1 << 0)
+
+/*
+ * SDRAM Signal Hold Time Control Register
+ */
+#define FTPMU010_SDRAMHTC_RCLK_DLY(x)		(((x) & 0xf) << 28)
+#define FTPMU010_SDRAMHTC_CTL_WCLK_DLY(x)	(((x) & 0xf) << 24)
+#define FTPMU010_SDRAMHTC_DAT_WCLK_DLY(x)	(((x) & 0xf) << 20)
+#define FTPMU010_SDRAMHTC_EBICTRL_DCSR		(1 << 18)
+#define FTPMU010_SDRAMHTC_EBIDATA_DCSR		(1 << 17)
+#define FTPMU010_SDRAMHTC_SDRAMCS_DCSR		(1 << 16)
+#define FTPMU010_SDRAMHTC_SDRAMCTL_DCSR		(1 << 15)
+#define FTPMU010_SDRAMHTC_CKE_DCSR		(1 << 14)
+#define FTPMU010_SDRAMHTC_DQM_DCSR		(1 << 13)
+#define FTPMU010_SDRAMHTC_SDCLK_DCSR		(1 << 12)
+
+#ifndef __ASSEMBLY__
+void ftpmu010_32768osc_enable(void);
+void ftpmu010_dlldis_disable(void);
+void ftpmu010_mfpsr_diselect_dev(unsigned int dev);
+void ftpmu010_mfpsr_select_dev(unsigned int dev);
+void ftpmu010_sdram_clk_disable(unsigned int cr0);
+void ftpmu010_sdramhtc_set(unsigned int val);
+#endif
+
+#ifdef __ASSEMBLY__
+#define FTPMU010_IDNMBR0	0x00
+#define FTPMU010_reserved0	0x04
+#define FTPMU010_OSCC		0x08
+#define FTPMU010_PMODE		0x0C
+#define FTPMU010_PMCR		0x10
+#define FTPMU010_PED		0x14
+#define FTPMU010_PEDSR		0x18
+#define FTPMU010_reserved1	0x1C
+#define FTPMU010_PMSR		0x20
+#define FTPMU010_PGSR		0x24
+#define FTPMU010_MFPSR		0x28
+#define FTPMU010_MISC		0x2C
+#define FTPMU010_PDLLCR0	0x30
+#define FTPMU010_PDLLCR1	0x34
+#define FTPMU010_AHBMCLKOFF	0x38
+#define FTPMU010_APBMCLKOFF	0x3C
+#define FTPMU010_DCSRCR0	0x40
+#define FTPMU010_DCSRCR1	0x44
+#define FTPMU010_DCSRCR2	0x48
+#define FTPMU010_SDRAMHTC	0x4C
+#define FTPMU010_PSPR0		0x50
+#define FTPMU010_PSPR1		0x54
+#define FTPMU010_PSPR2		0x58
+#define FTPMU010_PSPR3		0x5C
+#define FTPMU010_PSPR4		0x60
+#define FTPMU010_PSPR5		0x64
+#define FTPMU010_PSPR6		0x68
+#define FTPMU010_PSPR7		0x6C
+#define FTPMU010_PSPR8		0x70
+#define FTPMU010_PSPR9		0x74
+#define FTPMU010_PSPR10		0x78
+#define FTPMU010_PSPR11		0x7C
+#define FTPMU010_PSPR12		0x80
+#define FTPMU010_PSPR13		0x84
+#define FTPMU010_PSPR14		0x88
+#define FTPMU010_PSPR15		0x8C
+#define FTPMU010_AHBDMA_RACCS	0x90
+#define FTPMU010_reserved2	0x94
+#define FTPMU010_reserved3	0x98
+#define FTPMU010_JSS		0x9C
+#define FTPMU010_CFC_RACC	0xA0
+#define FTPMU010_SSP1_RACC	0xA4
+#define FTPMU010_UART1TX_RACC	0xA8
+#define FTPMU010_UART1RX_RACC	0xAC
+#define FTPMU010_UART2TX_RACC	0xB0
+#define FTPMU010_UART2RX_RACC	0xB4
+#define FTPMU010_SDC_RACC	0xB8
+#define FTPMU010_I2SAC97_RACC	0xBC
+#define FTPMU010_IRDATX_RACC	0xC0
+#define FTPMU010_reserved4	0xC4
+#define FTPMU010_USBD_RACC	0xC8
+#define FTPMU010_IRDARX_RACC	0xCC
+#define FTPMU010_IRDA_RACC	0xD0
+#define FTPMU010_ED0_RACC	0xD4
+#define FTPMU010_ED1_RACC	0xD8
+#endif /* __ASSEMBLY__ */
+
+#endif	/* __FTPMU010_H */
diff --git a/qemu/roms/u-boot/include/faraday/ftsdc010.h b/qemu/roms/u-boot/include/faraday/ftsdc010.h
new file mode 100644
index 000000000..9bfdef90e
--- /dev/null
+++ b/qemu/roms/u-boot/include/faraday/ftsdc010.h
@@ -0,0 +1,246 @@
+/*
+ * Faraday FTSDC010 Secure Digital Memory Card Host Controller
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __FTSDC010_H
+#define __FTSDC010_H
+
+#ifndef __ASSEMBLY__
+
+/* sd controller register */
+struct ftsdc010_mmc {
+	unsigned int	cmd;		/* 0x00 - command reg		*/
+	unsigned int	argu;		/* 0x04 - argument reg		*/
+	unsigned int	rsp0;		/* 0x08 - response reg0		*/
+	unsigned int	rsp1;		/* 0x0c - response reg1		*/
+	unsigned int	rsp2;		/* 0x10 - response reg2		*/
+	unsigned int	rsp3;		/* 0x14 - response reg3		*/
+	unsigned int	rsp_cmd;	/* 0x18 - responded cmd reg	*/
+	unsigned int	dcr;		/* 0x1c - data control reg	*/
+	unsigned int	dtr;		/* 0x20 - data timer reg	*/
+	unsigned int	dlr;		/* 0x24 - data length reg	*/
+	unsigned int	status;		/* 0x28 - status reg		*/
+	unsigned int	clr;		/* 0x2c - clear reg		*/
+	unsigned int	int_mask;	/* 0x30 - intrrupt mask reg	*/
+	unsigned int	pcr;		/* 0x34 - power control reg	*/
+	unsigned int	ccr;		/* 0x38 - clock contorl reg	*/
+	unsigned int	bwr;		/* 0x3c - bus width reg		*/
+	unsigned int	dwr;		/* 0x40 - data window reg	*/
+#ifndef CONFIG_FTSDC010_SDIO
+	unsigned int	feature;	/* 0x44 - feature reg		*/
+	unsigned int	rev;		/* 0x48 - revision reg		*/
+#else
+	unsigned int	mmc_intr_time;	/* 0x44 - MMC int resp time reg	*/
+	unsigned int	gpo;		/* 0x48 - gerenal purpose output */
+	unsigned int	reserved[8];	/* 0x50 - 0x68 reserved		*/
+	unsigned int	sdio_ctrl1;	/* 0x6c - SDIO control reg 1	*/
+	unsigned int	sdio_ctrl2;	/* 0x70 - SDIO control reg 2	*/
+	unsigned int	sdio_status;	/* 0x74 - SDIO status regi	*/
+	unsigned int	reserved1[9];	/* 0x78 - 0x98	reserved	*/
+	unsigned int	feature;	/* 0x9c - feature reg		*/
+	unsigned int	rev;		/* 0xa0 - revision reg		*/
+#endif /* CONFIG_FTSDC010_SDIO */
+};
+
+struct mmc_host {
+	struct ftsdc010_mmc *reg;
+	unsigned int version;		/* SDHCI spec. version */
+	unsigned int clock;		/* Current clock (MHz) */
+	unsigned int fifo_len;		/* bytes */
+	unsigned int last_opcode;	/* Last OP Code */
+	unsigned int card_type;		/* Card type */
+};
+
+/* functions */
+int ftsdc010_mmc_init(int dev_index);
+
+#endif	/* __ASSEMBLY__ */
+
+/* global defines */
+#define FTSDC010_CMD_RETRY			0x100000
+#define FTSDC010_PIO_RETRY			100	/* pio retry times */
+#define FTSDC010_DELAY_UNIT			100	/* 100 us */
+
+/* define from Linux kernel - include/linux/mmc/card.h */
+#define MMC_TYPE_SDIO				2	/* SDIO card */
+
+/* define for mmc layer */
+#define MMC_DATA_BOTH_DIR			(MMC_DATA_WRITE | MMC_DATA_READ)
+
+/* this part is strange */
+#define FTSDC010_SDIO_CTRL1_REG			0x0000006C
+#define FTSDC010_SDIO_CTRL2_REG			0x0000006C
+#define FTSDC010_SDIO_STATUS_REG		0x00000070
+
+/* 0x00 - command register */
+#define FTSDC010_CMD_IDX(x)			(((x) & 0x3f) << 0)
+#define FTSDC010_CMD_NEED_RSP			(1 << 6)
+#define FTSDC010_CMD_LONG_RSP			(1 << 7)
+#define FTSDC010_CMD_APP_CMD			(1 << 8)
+#define FTSDC010_CMD_CMD_EN			(1 << 9)
+#define FTSDC010_CMD_SDC_RST			(1 << 10)
+#define FTSDC010_CMD_MMC_INT_STOP		(1 << 11)
+
+/* 0x18 - responded command register */
+#define FTSDC010_RSP_CMD_IDX(x)			(((x) >> 0) & 0x3f)
+#define FTSDC010_RSP_CMD_APP			(1 << 6)
+
+/* 0x1c - data control register */
+#define FTSDC010_DCR_BLK_SIZE(x)		(((x) & 0xf) << 0)
+#define FTSDC010_DCR_DATA_WRITE			(1 << 4)
+#define FTSDC010_DCR_DMA_EN			(1 << 5)
+#define FTSDC010_DCR_DATA_EN			(1 << 6)
+#ifdef CONFIG_FTSDC010_SDIO
+#define FTSDC010_DCR_FIFOTH			(1 << 7)
+#define FTSDC010_DCR_DMA_TYPE(x)		(((x) & 0x3) << 8)
+#define FTSDC010_DCR_FIFO_RST			(1 << 10)
+#endif /* CONFIG_FTSDC010_SDIO */
+
+#define FTSDC010_DCR_DMA_TYPE_1			0x0	/* Single r/w	*/
+#define FTSDC010_DCR_DMA_TYPE_4			0x1	/* Burst 4 r/w	*/
+#define FTSDC010_DCR_DMA_TYPE_8			0x2	/* Burst 8 r/w	*/
+
+#define FTSDC010_DCR_BLK_BYTES(x)		(ffs(x) - 1)	/* 1B - 2048B */
+
+/* CPRM related define */
+#define FTSDC010_CPRM_DATA_CHANGE_ENDIAN_EN	0x000008
+#define FTSDC010_CPRM_DATA_SWAP_HL_EN		0x000010
+
+/* 0x28 - status register */
+#define FTSDC010_STATUS_RSP_CRC_FAIL		(1 << 0)
+#define FTSDC010_STATUS_DATA_CRC_FAIL		(1 << 1)
+#define FTSDC010_STATUS_RSP_TIMEOUT		(1 << 2)
+#define FTSDC010_STATUS_DATA_TIMEOUT		(1 << 3)
+#define FTSDC010_STATUS_RSP_CRC_OK		(1 << 4)
+#define FTSDC010_STATUS_DATA_CRC_OK		(1 << 5)
+#define FTSDC010_STATUS_CMD_SEND		(1 << 6)
+#define FTSDC010_STATUS_DATA_END		(1 << 7)
+#define FTSDC010_STATUS_FIFO_URUN		(1 << 8)
+#define FTSDC010_STATUS_FIFO_ORUN		(1 << 9)
+#define FTSDC010_STATUS_CARD_CHANGE		(1 << 10)
+#define FTSDC010_STATUS_CARD_DETECT		(1 << 11)
+#define FTSDC010_STATUS_WRITE_PROT		(1 << 12)
+#ifdef CONFIG_FTSDC010_SDIO
+#define FTSDC010_STATUS_CP_READY		(1 << 13) /* reserved ? */
+#define FTSDC010_STATUS_CP_BUF_READY		(1 << 14) /* reserved ? */
+#define FTSDC010_STATUS_PLAIN_TEXT_READY	(1 << 15) /* reserved ? */
+#define FTSDC010_STATUS_SDIO_IRPT		(1 << 16) /* SDIO card intr */
+#define FTSDC010_STATUS_DATA0_STATUS		(1 << 17)
+#endif /* CONFIG_FTSDC010_SDIO */
+#define FTSDC010_STATUS_RSP_ERROR	\
+	(FTSDC010_STATUS_RSP_CRC_FAIL | FTSDC010_STATUS_RSP_TIMEOUT)
+#define FTSDC010_STATUS_RSP_MASK	\
+	(FTSDC010_STATUS_RSP_ERROR | FTSDC010_STATUS_RSP_CRC_OK)
+#define FTSDC010_STATUS_DATA_ERROR	\
+	(FTSDC010_STATUS_DATA_CRC_FAIL | FTSDC010_STATUS_DATA_TIMEOUT)
+#define FTSDC010_STATUS_DATA_MASK	\
+	(FTSDC010_STATUS_DATA_ERROR | FTSDC010_STATUS_DATA_CRC_OK \
+	| FTSDC010_STATUS_DATA_END)
+
+/* 0x2c - clear register */
+#define FTSDC010_CLR_RSP_CRC_FAIL		(1 << 0)
+#define FTSDC010_CLR_DATA_CRC_FAIL		(1 << 1)
+#define FTSDC010_CLR_RSP_TIMEOUT		(1 << 2)
+#define FTSDC010_CLR_DATA_TIMEOUT		(1 << 3)
+#define FTSDC010_CLR_RSP_CRC_OK			(1 << 4)
+#define FTSDC010_CLR_DATA_CRC_OK		(1 << 5)
+#define FTSDC010_CLR_CMD_SEND			(1 << 6)
+#define FTSDC010_CLR_DATA_END			(1 << 7)
+#define FTSDC010_STATUS_FIFO_URUN		(1 << 8) /* reserved ? */
+#define FTSDC010_STATUS_FIFO_ORUN		(1 << 9) /* reserved ? */
+#define FTSDC010_CLR_CARD_CHANGE		(1 << 10)
+#ifdef CONFIG_FTSDC010_SDIO
+#define FTSDC010_CLR_SDIO_IRPT			(1 << 16)
+#endif /* CONFIG_FTSDC010_SDIO */
+
+/* 0x30 - interrupt mask register */
+#define FTSDC010_INT_MASK_RSP_CRC_FAIL		(1 << 0)
+#define FTSDC010_INT_MASK_DATA_CRC_FAIL		(1 << 1)
+#define FTSDC010_INT_MASK_RSP_TIMEOUT		(1 << 2)
+#define FTSDC010_INT_MASK_DATA_TIMEOUT		(1 << 3)
+#define FTSDC010_INT_MASK_RSP_CRC_OK		(1 << 4)
+#define FTSDC010_INT_MASK_DATA_CRC_OK		(1 << 5)
+#define FTSDC010_INT_MASK_CMD_SEND		(1 << 6)
+#define FTSDC010_INT_MASK_DATA_END		(1 << 7)
+#define FTSDC010_INT_MASK_FIFO_URUN		(1 << 8)
+#define FTSDC010_INT_MASK_FIFO_ORUN		(1 << 9)
+#define FTSDC010_INT_MASK_CARD_CHANGE		(1 << 10)
+#ifdef CONFIG_FTSDC010_SDIO
+#define FTSDC010_INT_MASK_CP_READY		(1 << 13)
+#define FTSDC010_INT_MASK_CP_BUF_READY		(1 << 14)
+#define FTSDC010_INT_MASK_PLAIN_TEXT_READY	(1 << 15)
+#define FTSDC010_INT_MASK_SDIO_IRPT		(1 << 16)
+#define FTSDC010_STATUS_DATA0_STATUS		(1 << 17)
+#endif /* CONFIG_FTSDC010_SDIO */
+
+/* ? */
+#define FTSDC010_CARD_INSERT			0x0
+#define FTSDC010_CARD_REMOVE			FTSDC010_STATUS_REG_CARD_DETECT
+
+/* 0x34 - power control register */
+#define FTSDC010_PCR_POWER(x)			(((x) & 0xf) << 0)
+#define FTSDC010_PCR_POWER_ON			(1 << 4)
+
+/* 0x38 - clock control register */
+#define FTSDC010_CCR_CLK_DIV(x)			(((x) & 0x7f) << 0)
+#define FTSDC010_CCR_CLK_SD			(1 << 7) /* 0: MMC, 1: SD */
+#define FTSDC010_CCR_CLK_DIS			(1 << 8)
+#define FTSDC010_CCR_CLK_HISPD			(1 << 9) /* high speed */
+
+/* card type */
+#define FTSDC010_CARD_TYPE_SD			FTSDC010_CLOCK_REG_CARD_TYPE
+#define FTSDC010_CARD_TYPE_MMC			0x0
+
+/* 0x3c - bus width register */
+#define FTSDC010_BWR_MODE_1BIT      (1 << 0) /* 1 bit mode enabled */
+#define FTSDC010_BWR_MODE_8BIT      (1 << 1) /* 8 bit mode enabled */
+#define FTSDC010_BWR_MODE_4BIT      (1 << 2) /* 4 bit mode enabled */
+#define FTSDC010_BWR_MODE_MASK      (7 << 0)
+#define FTSDC010_BWR_MODE_SHIFT     (0)
+#define FTSDC010_BWR_CAPS_1BIT      (0 << 3) /* 1 bits mode supported */
+#define FTSDC010_BWR_CAPS_4BIT      (1 << 3) /* 1,4 bits mode supported */
+#define FTSDC010_BWR_CAPS_8BIT      (2 << 3) /* 1,4,8 bits mode supported */
+#define FTSDC010_BWR_CAPS_MASK      (3 << 3)
+#define FTSDC010_BWR_CAPS_SHIFT     (3)
+#define FTSDC010_BWR_CARD_DETECT    (1 << 5)
+
+/* 0x44 or 0x9c - feature register */
+#define FTSDC010_FEATURE_FIFO_DEPTH(x)		(((x) >> 0) & 0xff)
+#define FTSDC010_FEATURE_CPRM_FUNCTION		(1 << 8)
+
+#define FTSDC010_FIFO_DEPTH_4			0x04
+#define FTSDC010_FIFO_DEPTH_8			0x08
+#define FTSDC010_FIFO_DEPTH_16			0x10
+
+/* 0x48 or 0xa0 - revision register */
+#define FTSDC010_REV_REVISION(x)		(((x) & 0xff) >> 0)
+#define FTSDC010_REV_MINOR(x)			(((x) & 0xff00) >> 8)
+#define FTSDC010_REV_MAJOR(x)			(((x) & 0xffff0000) >> 16)
+
+#ifdef CONFIG_FTSDC010_SDIO
+/* 0x44 - general purpose output */
+#define FTSDC010_GPO_PORT(x)			(((x) & 0xf) << 0)
+
+/* 0x6c - sdio control register 1 */
+#define FTSDC010_SDIO_CTRL1_SDIO_BLK_SIZE(x)	(((x) & 0xfff) << 0)
+#define FTSDC010_SDIO_CTRL1_SDIO_BLK_MODE	(1 << 12)
+#define FTSDC010_SDIO_CTRL1_READ_WAIT_EN	(1 << 13)
+#define FTSDC010_SDIO_CTRL1_SDIO_ENABLE		(1 << 14)
+#define FTSDC010_SDIO_CTRL1_SDIO_BLK_NO(x)	(((x) & 0x1ff) << 15)
+
+/* 0x70 - sdio control register 2 */
+#define FTSDC010_SDIO_CTRL2_SUSP_READ_WAIT	(1 << 0)
+#define FTSDC010_SDIO_CTRL2_SUSP_CMD_ABORT	(1 << 1)
+
+/* 0x74 - sdio status register */
+#define FTSDC010_SDIO_STATUS_SDIO_BLK_CNT(x)	(((x) >> 0) & 0x1ffff)
+#define FTSDC010_SDIO_STATUS_FIFO_REMAIN_NO(x)	(((x) >> 17) & 0xef)
+
+#endif /* CONFIG_FTSDC010_SDIO */
+
+#endif /* __FTSDC010_H */
diff --git a/qemu/roms/u-boot/include/faraday/ftsdmc020.h b/qemu/roms/u-boot/include/faraday/ftsdmc020.h
new file mode 100644
index 000000000..8e296c056
--- /dev/null
+++ b/qemu/roms/u-boot/include/faraday/ftsdmc020.h
@@ -0,0 +1,91 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * SDRAM Controller
+ */
+#ifndef __FTSDMC020_H
+#define __FTSDMC020_H
+
+#define FTSDMC020_OFFSET_TP0		0x00
+#define FTSDMC020_OFFSET_TP1		0x04
+#define FTSDMC020_OFFSET_CR		0x08
+#define FTSDMC020_OFFSET_BANK0_BSR	0x0C
+#define FTSDMC020_OFFSET_BANK1_BSR	0x10
+#define FTSDMC020_OFFSET_BANK2_BSR	0x14
+#define FTSDMC020_OFFSET_BANK3_BSR	0x18
+#define FTSDMC020_OFFSET_BANK4_BSR	0x1C
+#define FTSDMC020_OFFSET_BANK5_BSR	0x20
+#define FTSDMC020_OFFSET_BANK6_BSR	0x24
+#define FTSDMC020_OFFSET_BANK7_BSR	0x28
+#define FTSDMC020_OFFSET_ACR		0x34
+
+/*
+ * Timing Parametet 0 Register
+ */
+#define FTSDMC020_TP0_TCL(x)	((x) & 0x3)
+#define FTSDMC020_TP0_TWR(x)	(((x) & 0x3) << 4)
+#define FTSDMC020_TP0_TRF(x)	(((x) & 0xf) << 8)
+#define FTSDMC020_TP0_TRCD(x)	(((x) & 0x7) << 12)
+#define FTSDMC020_TP0_TRP(x)	(((x) & 0xf) << 16)
+#define FTSDMC020_TP0_TRAS(x)	(((x) & 0xf) << 20)
+
+/*
+ * Timing Parametet 1 Register
+ */
+#define FTSDMC020_TP1_REF_INTV(x)	((x) & 0xffff)
+#define FTSDMC020_TP1_INI_REFT(x)	(((x) & 0xf) << 16)
+#define FTSDMC020_TP1_INI_PREC(x)	(((x) & 0xf) << 20)
+
+/*
+ * Configuration Register
+ */
+#define FTSDMC020_CR_SREF	(1 << 0)
+#define FTSDMC020_CR_PWDN	(1 << 1)
+#define FTSDMC020_CR_ISMR	(1 << 2)
+#define FTSDMC020_CR_IREF	(1 << 3)
+#define FTSDMC020_CR_IPREC	(1 << 4)
+#define FTSDMC020_CR_REFTYPE	(1 << 5)
+
+/*
+ * SDRAM External Bank Base/Size Register
+ */
+#define FTSDMC020_BANK_ENABLE		(1 << 28)
+
+#define FTSDMC020_BANK_BASE(addr)	(((addr) >> 20) << 16)
+
+#define FTSDMC020_BANK_DDW_X4		(0 << 12)
+#define FTSDMC020_BANK_DDW_X8		(1 << 12)
+#define FTSDMC020_BANK_DDW_X16		(2 << 12)
+#define FTSDMC020_BANK_DDW_X32		(3 << 12)
+
+#define FTSDMC020_BANK_DSZ_16M		(0 << 8)
+#define FTSDMC020_BANK_DSZ_64M		(1 << 8)
+#define FTSDMC020_BANK_DSZ_128M		(2 << 8)
+#define FTSDMC020_BANK_DSZ_256M		(3 << 8)
+
+#define FTSDMC020_BANK_MBW_8		(0 << 4)
+#define FTSDMC020_BANK_MBW_16		(1 << 4)
+#define FTSDMC020_BANK_MBW_32		(2 << 4)
+
+#define FTSDMC020_BANK_SIZE_1M		0x0
+#define FTSDMC020_BANK_SIZE_2M		0x1
+#define FTSDMC020_BANK_SIZE_4M		0x2
+#define FTSDMC020_BANK_SIZE_8M		0x3
+#define FTSDMC020_BANK_SIZE_16M		0x4
+#define FTSDMC020_BANK_SIZE_32M		0x5
+#define FTSDMC020_BANK_SIZE_64M		0x6
+#define FTSDMC020_BANK_SIZE_128M	0x7
+#define FTSDMC020_BANK_SIZE_256M	0x8
+
+/*
+ * Arbiter Control Register
+ */
+#define FTSDMC020_ACR_TOC(x)	((x) & 0x1f)
+#define FTSDMC020_ACR_TOE	(1 << 8)
+
+#endif	/* __FTSDMC020_H */
diff --git a/qemu/roms/u-boot/include/faraday/ftsdmc021.h b/qemu/roms/u-boot/include/faraday/ftsdmc021.h
new file mode 100644
index 000000000..b893b5e3e
--- /dev/null
+++ b/qemu/roms/u-boot/include/faraday/ftsdmc021.h
@@ -0,0 +1,139 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * (C) Copyright 2011 Andes Technology Corp
+ * Macpaul Lin <macpaul@andestech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * FTSDMC021 - SDRAM Controller
+ */
+#ifndef __FTSDMC021_H
+#define __FTSDMC021_H
+
+#ifndef __ASSEMBLY__
+struct ftsdmc021 {
+	unsigned int	tp1;		/* 0x00 - SDRAM Timing Parameter 1 */
+	unsigned int	tp2;		/* 0x04 - SDRAM Timing Parameter 2 */
+	unsigned int	cr1;		/* 0x08 - SDRAM Configuration Reg 1 */
+	unsigned int	cr2;		/* 0x0c - SDRAM Configuration Reg 2 */
+	unsigned int	bank0_bsr;	/* 0x10 - Ext. Bank Base/Size Reg 0 */
+	unsigned int	bank1_bsr;	/* 0x14 - Ext. Bank Base/Size Reg 1 */
+	unsigned int	bank2_bsr;	/* 0x18 - Ext. Bank Base/Size Reg 2 */
+	unsigned int	bank3_bsr;	/* 0x1c - Ext. Bank Base/Size Reg 3 */
+	unsigned int	bank4_bsr;	/* 0x20 - Ext. Bank Base/Size Reg 4 */
+	unsigned int	bank5_bsr;	/* 0x24 - Ext. Bank Base/Size Reg 5 */
+	unsigned int	bank6_bsr;	/* 0x28 - Ext. Bank Base/Size Reg 6 */
+	unsigned int	bank7_bsr;	/* 0x2c - Ext. Bank Base/Size Reg 7 */
+	unsigned int	ragr;		/* 0x30 - Read Arbitration Group Reg */
+	unsigned int	frr;		/* 0x34 - Flush Request Register */
+	unsigned int	ebisr;		/* 0x38 - EBI Support Register	*/
+	unsigned int	rsved[25];	/* 0x3c-0x9c - Reserved		*/
+	unsigned int	crr;		/* 0x100 - Controller Revision Reg */
+	unsigned int	cfr;		/* 0x104 - Controller Feature Reg */
+};
+#endif /* __ASSEMBLY__ */
+
+/*
+ * Timing Parameter 1 Register
+ */
+#define FTSDMC021_TP1_TCL(x)	((x) & 0x3)		/* CAS Latency */
+#define FTSDMC021_TP1_TWR(x)	(((x) & 0x3) << 4)	/* W-Recovery Time */
+#define FTSDMC021_TP1_TRF(x)	(((x) & 0xf) << 8)	/* Auto-Refresh Cycle */
+#define FTSDMC021_TP1_TRCD(x)	(((x) & 0x7) << 12)	/* RAS-to-CAS Delay */
+#define FTSDMC021_TP1_TRP(x)	(((x) & 0xf) << 16)	/* Precharge Cycle */
+#define FTSDMC021_TP1_TRAS(x)	(((x) & 0xf) << 20)
+
+/*
+ * Timing Parameter 2 Register
+ */
+#define FTSDMC021_TP2_REF_INTV(x)	((x) & 0xffff)	/* Refresh interval */
+/* b(16:19) - Initial Refresh Times */
+#define FTSDMC021_TP2_INI_REFT(x)	(((x) & 0xf) << 16)
+/* b(20:23) - Initial Pre-Charge Times */
+#define FTSDMC021_TP2_INI_PREC(x)	(((x) & 0xf) << 20)
+
+/*
+ * SDRAM Configuration Register 1
+ */
+#define FTSDMC021_CR1_BNKSIZE(x)	((x) & 0xf)		/* Bank Size  */
+#define FTSDMC021_CR1_MBW(x)		(((x) & 0x3) << 4)	/* Bus Width  */
+#define FTSDMC021_CR1_DSZ(x)		(((x) & 0x7) << 8)	/* SDRAM Size */
+#define FTSDMC021_CR1_DDW(x)		(((x) & 0x3) << 12)	/* Data Width */
+/* b(16) MA2T: Double Memory Address Cycle Enable */
+#define FTSDMC021_CR1_MA2T(x)		(1 << 16)
+/* The value of b(0:3)CR1: 1M-512M, must be power of 2 */
+#define FTSDMC021_BANK_SIZE(x)		(ffs(x) - 1)
+
+/*
+ * Configuration Register 2
+ */
+#define FTSDMC021_CR2_SREF	(1 << 0)	/* Self-Refresh Mode */
+#define FTSDMC021_CR2_PWDN	(1 << 1)	/* Power Down Operation Mode */
+#define FTSDMC021_CR2_ISMR	(1 << 2)	/* Start Set-Mode-Register */
+#define FTSDMC021_CR2_IREF	(1 << 3)	/* Init Refresh Start Flag */
+#define FTSDMC021_CR2_IPREC	(1 << 4)	/* Init Pre-Charge Start Flag */
+#define FTSDMC021_CR2_REFTYPE	(1 << 5)
+
+/*
+ * SDRAM External Bank Base/Size Register
+ */
+#define FTSDMC021_BANK_ENABLE		(1 << 12)
+
+/* 12-bit base address of external bank.
+ * Default value is 0x800.
+ * The 12-bit equals to the haddr[31:20] of AHB address bus. */
+#define FTSDMC021_BANK_BASE(x)		((x) & 0xfff)
+
+/*
+ * Read Arbitration Grant Window Register
+ */
+#define FTSDMC021_RAGR_CH1GW(x)		(((x) & 0xff) << 0)
+#define FTSDMC021_RAGR_CH2GW(x)		(((x) & 0xff) << 4)
+#define FTSDMC021_RAGR_CH3GW(x)		(((x) & 0xff) << 8)
+#define FTSDMC021_RAGR_CH4GW(x)		(((x) & 0xff) << 12)
+#define FTSDMC021_RAGR_CH5GW(x)		(((x) & 0xff) << 16)
+#define FTSDMC021_RAGR_CH6GW(x)		(((x) & 0xff) << 20)
+#define FTSDMC021_RAGR_CH7GW(x)		(((x) & 0xff) << 24)
+#define FTSDMC021_RAGR_CH8GW(x)		(((x) & 0xff) << 28)
+
+/*
+ * Flush Request Register
+ */
+#define FTSDMC021_FRR_FLUSHCHN(x)	(((x) & 0x7) << 0)
+#define FTSDMC021_FRR_FLUSHCMPLT	(1 << 3)	/* Flush Req Flag */
+
+/*
+ * External Bus Interface Support Register (EBISR)
+ */
+#define FTSDMC021_EBISR_MR(x)		((x) & 0xfff)	/* Far-end mode	*/
+#define FTSDMC021_EBISR_PRSMR		(1 << 12)	/* Pre-SMR	*/
+#define FTSDMC021_EBISR_POPREC		(1 << 13)
+#define FTSDMC021_EBISR_POSMR		(1 << 14)	/* Post-SMR	*/
+
+/*
+ * Controller Revision Register (CRR, Read Only)
+ */
+#define FTSDMC021_CRR_REV_VER		(((x) >> 0) & 0xff)
+#define FTSDMC021_CRR_MINOR_VER		(((x) >> 8) & 0xff)
+#define FTSDMC021_CRR_MAJOR_VER		(((x) >> 16) & 0xff)
+
+/*
+ * Controller Feature Register (CFR, Read Only)
+ */
+#define FTSDMC021_CFR_EBNK		(((x) >> 0) & 0xf)
+#define FTSDMC021_CFR_CHN		(((x) >> 8) & 0xf)
+#define FTSDMC021_CFR_EBI		(((x) >> 16) & 0x1)
+#define FTSDMC021_CFR_CH1_FDEPTH	(((x) >> 24) & 0x1)
+#define FTSDMC021_CFR_CH2_FDEPTH	(((x) >> 25) & 0x1)
+#define FTSDMC021_CFR_CH3_FDEPTH	(((x) >> 26) & 0x1)
+#define FTSDMC021_CFR_CH4_FDEPTH	(((x) >> 27) & 0x1)
+#define FTSDMC021_CFR_CH5_FDEPTH	(((x) >> 28) & 0x1)
+#define FTSDMC021_CFR_CH6_FDEPTH	(((x) >> 29) & 0x1)
+#define FTSDMC021_CFR_CH7_FDEPTH	(((x) >> 30) & 0x1)
+#define FTSDMC021_CFR_CH8_FDEPTH	(((x) >> 31) & 0x1)
+
+#endif	/* __FTSDMC021_H */
diff --git a/qemu/roms/u-boot/include/faraday/ftsmc020.h b/qemu/roms/u-boot/include/faraday/ftsmc020.h
new file mode 100644
index 000000000..54120ab41
--- /dev/null
+++ b/qemu/roms/u-boot/include/faraday/ftsmc020.h
@@ -0,0 +1,74 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Static Memory Controller
+ */
+#ifndef __FTSMC020_H
+#define __FTSMC020_H
+
+#ifndef __ASSEMBLY__
+
+struct ftsmc020_bank {
+	unsigned int    cr;
+	unsigned int    tpr;
+};
+
+struct ftsmc020 {
+	struct ftsmc020_bank bank[4];	/* 0x00 - 0x1c */
+	unsigned int	pad[8];		/* 0x20 - 0x3c */
+	unsigned int	ssr;		/* 0x40 */
+};
+
+void ftsmc020_init(void);
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * Memory Bank Configuration Register
+ */
+#define FTSMC020_BANK_ENABLE	(1 << 28)
+#define FTSMC020_BANK_BASE(x)	((x) & 0x0fff1000)
+
+#define FTSMC020_BANK_WPROT	(1 << 11)
+
+#define FTSMC020_BANK_TYPE1	(1 << 10)
+#define FTSMC020_BANK_TYPE2	(1 << 9)
+#define FTSMC020_BANK_TYPE3	(1 << 8)
+
+#define FTSMC020_BANK_SIZE_32K	(0xb << 4)
+#define FTSMC020_BANK_SIZE_64K	(0xc << 4)
+#define FTSMC020_BANK_SIZE_128K	(0xd << 4)
+#define FTSMC020_BANK_SIZE_256K	(0xe << 4)
+#define FTSMC020_BANK_SIZE_512K	(0xf << 4)
+#define FTSMC020_BANK_SIZE_1M	(0x0 << 4)
+#define FTSMC020_BANK_SIZE_2M	(0x1 << 4)
+#define FTSMC020_BANK_SIZE_4M	(0x2 << 4)
+#define FTSMC020_BANK_SIZE_8M	(0x3 << 4)
+#define FTSMC020_BANK_SIZE_16M	(0x4 << 4)
+#define FTSMC020_BANK_SIZE_32M	(0x5 << 4)
+#define FTSMC020_BANK_SIZE_64M	(0x6 << 4)
+
+#define FTSMC020_BANK_MBW_8	(0x0 << 0)
+#define FTSMC020_BANK_MBW_16	(0x1 << 0)
+#define FTSMC020_BANK_MBW_32	(0x2 << 0)
+
+/*
+ * Memory Bank Timing Parameter Register
+ */
+#define FTSMC020_TPR_ETRNA(x)	(((x) & 0xf) << 28)
+#define FTSMC020_TPR_EATI(x)	(((x) & 0xf) << 24)
+#define FTSMC020_TPR_RBE	(1 << 20)
+#define FTSMC020_TPR_AST(x)	(((x) & 0x3) << 18)
+#define FTSMC020_TPR_CTW(x)	(((x) & 0x3) << 16)
+#define FTSMC020_TPR_ATI(x)	(((x) & 0xf) << 12)
+#define FTSMC020_TPR_AT2(x)	(((x) & 0x3) << 8)
+#define FTSMC020_TPR_WTC(x)	(((x) & 0x3) << 6)
+#define FTSMC020_TPR_AHT(x)	(((x) & 0x3) << 4)
+#define FTSMC020_TPR_TRNA(x)	(((x) & 0xf) << 0)
+
+#endif	/* __FTSMC020_H */
diff --git a/qemu/roms/u-boot/include/faraday/fttmr010.h b/qemu/roms/u-boot/include/faraday/fttmr010.h
new file mode 100644
index 000000000..2ab68d102
--- /dev/null
+++ b/qemu/roms/u-boot/include/faraday/fttmr010.h
@@ -0,0 +1,61 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <ratbert@faraday-tech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Timer
+ */
+#ifndef __FTTMR010_H
+#define __FTTMR010_H
+
+struct fttmr010 {
+	unsigned int	timer1_counter;		/* 0x00 */
+	unsigned int	timer1_load;		/* 0x04 */
+	unsigned int	timer1_match1;		/* 0x08 */
+	unsigned int	timer1_match2;		/* 0x0c */
+	unsigned int	timer2_counter;		/* 0x10 */
+	unsigned int	timer2_load;		/* 0x14 */
+	unsigned int	timer2_match1;		/* 0x18 */
+	unsigned int	timer2_match2;		/* 0x1c */
+	unsigned int	timer3_counter;		/* 0x20 */
+	unsigned int	timer3_load;		/* 0x24 */
+	unsigned int	timer3_match1;		/* 0x28 */
+	unsigned int	timer3_match2;		/* 0x2c */
+	unsigned int	cr;			/* 0x30 */
+	unsigned int	interrupt_state;	/* 0x34 */
+	unsigned int	interrupt_mask;		/* 0x38 */
+};
+
+/*
+ * Timer Control Register
+ */
+#define FTTMR010_TM3_UPDOWN	(1 << 11)
+#define FTTMR010_TM2_UPDOWN	(1 << 10)
+#define FTTMR010_TM1_UPDOWN	(1 << 9)
+#define FTTMR010_TM3_OFENABLE	(1 << 8)
+#define FTTMR010_TM3_CLOCK	(1 << 7)
+#define FTTMR010_TM3_ENABLE	(1 << 6)
+#define FTTMR010_TM2_OFENABLE	(1 << 5)
+#define FTTMR010_TM2_CLOCK	(1 << 4)
+#define FTTMR010_TM2_ENABLE	(1 << 3)
+#define FTTMR010_TM1_OFENABLE	(1 << 2)
+#define FTTMR010_TM1_CLOCK	(1 << 1)
+#define FTTMR010_TM1_ENABLE	(1 << 0)
+
+/*
+ * Timer Interrupt State & Mask Registers
+ */
+#define FTTMR010_TM3_OVERFLOW	(1 << 8)
+#define FTTMR010_TM3_MATCH2	(1 << 7)
+#define FTTMR010_TM3_MATCH1	(1 << 6)
+#define FTTMR010_TM2_OVERFLOW	(1 << 5)
+#define FTTMR010_TM2_MATCH2	(1 << 4)
+#define FTTMR010_TM2_MATCH1	(1 << 3)
+#define FTTMR010_TM1_OVERFLOW	(1 << 2)
+#define FTTMR010_TM1_MATCH2	(1 << 1)
+#define FTTMR010_TM1_MATCH1	(1 << 0)
+
+#endif	/* __FTTMR010_H */
diff --git a/qemu/roms/u-boot/include/faraday/ftwdt010_wdt.h b/qemu/roms/u-boot/include/faraday/ftwdt010_wdt.h
new file mode 100644
index 000000000..2c5a36628
--- /dev/null
+++ b/qemu/roms/u-boot/include/faraday/ftwdt010_wdt.h
@@ -0,0 +1,94 @@
+/*
+ * Watchdog driver for the FTWDT010 Watch Dog Driver
+ *
+ * (c) Copyright 2004 Faraday Technology Corp. (www.faraday-tech.com)
+ * Based on sa1100_wdt.c by Oleg Drokin <green@crimea.edu>
+ * Based on SoftDog driver by Alan Cox <alan@redhat.com>
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * 27/11/2004 Initial release, Faraday.
+ * 12/01/2011 Port to u-boot, Macpaul Lin.
+ */
+
+#ifndef __FTWDT010_H
+#define __FTWDT010_H
+
+struct ftwdt010_wdt {
+	unsigned int	wdcounter;	/* Counter Reg		- 0x00 */
+	unsigned int	wdload;		/* Counter Auto Reload Reg - 0x04 */
+	unsigned int	wdrestart;	/* Counter Restart Reg	- 0x08 */
+	unsigned int	wdcr;		/* Control Reg		- 0x0c */
+	unsigned int	wdstatus;	/* Status Reg		- 0x10 */
+	unsigned int	wdclear;	/* Timer Clear		- 0x14 */
+	unsigned int	wdintrlen;	/* Interrupt Length	- 0x18 */
+};
+
+/*
+ * WDLOAD - Counter Auto Reload Register
+ *   The Auto Reload Register is set to 0x03EF1480 (66Mhz) by default.
+ *   Which means in a 66MHz system, the period of Watch Dog timer reset is
+ *   one second.
+ */
+#define FTWDT010_WDLOAD(x)		((x) & 0xffffffff)
+
+/*
+ * WDRESTART - Watch Dog Timer Counter Restart Register
+ *   If writing 0x5AB9 to WDRESTART register, Watch Dog timer will
+ *   automatically reload WDLOAD to WDCOUNTER and restart counting.
+ */
+#define FTWDT010_WDRESTART_MAGIC	0x5AB9
+
+/* WDCR - Watch Dog Timer Control Register */
+#define FTWDT010_WDCR_ENABLE		(1 << 0)
+#define FTWDT010_WDCR_RST		(1 << 1)
+#define FTWDT010_WDCR_INTR		(1 << 2)
+/* FTWDT010_WDCR_EXT bit: Watch Dog Timer External Signal Enable */
+#define FTWDT010_WDCR_EXT		(1 << 3)
+/* FTWDT010_WDCR_CLOCK bit: Clock Source: 0: PCLK, 1: EXTCLK.
+ *  The clock source PCLK cannot be gated when system sleeps, even if
+ *  WDCLOCK bit is turned on.
+ *
+ *  Faraday's Watch Dog timer can be driven by an external clock. The
+ *  programmer just needs to write one to WdCR[WdClock] bit.
+ *
+ *  Note: There is a limitation between EXTCLK and PCLK:
+ *  EXTCLK cycle time / PCLK cycle time > 2.
+ *  If the system does not need an external clock,
+ *  just keep WdCR[WdClock] bit in its default value.
+ */
+#define FTWDT010_WDCR_CLOCK		(1 << 4)
+
+/*
+ * WDSTATUS - Watch Dog Timer Status Register
+ *   This bit is set when the counter reaches Zero
+ */
+#define FTWDT010_WDSTATUS(x)		((x) & 0x1)
+
+/*
+ * WDCLEAR - Watch Dog Timer Clear Register
+ *   Writing one to this register will clear WDSTATUS.
+ */
+#define FTWDT010_WDCLEAR		(1 << 0)
+
+/*
+ * WDINTRLEN - Watch Dog Timer Interrupt Length
+ *   This register controls the duration length of wd_rst, wd_intr and wd_ext.
+ *   The default value is 0xFF.
+ */
+#define FTWDT010_WDINTRLEN(x)		((x) & 0xff)
+
+/*
+ * Variable timeout should be set in ms.
+ * (CONFIG_SYS_CLK_FREQ/1000) equals 1 ms.
+ * WDLOAD = timeout * TIMEOUT_FACTOR.
+ */
+#define FTWDT010_TIMEOUT_FACTOR		(CONFIG_SYS_CLK_FREQ / 1000) /* 1 ms */
+
+void ftwdt010_wdt_reset(void);
+void ftwdt010_wdt_disable(void);
+
+#endif /* __FTWDT010_H */
diff --git a/qemu/roms/u-boot/include/fat.h b/qemu/roms/u-boot/include/fat.h
new file mode 100644
index 000000000..81d979042
--- /dev/null
+++ b/qemu/roms/u-boot/include/fat.h
@@ -0,0 +1,207 @@
+/*
+ * R/O (V)FAT 12/16/32 filesystem implementation by Marcus Sundberg
+ *
+ * 2002-07-28 - rjones@nexus-tech.net - ported to ppcboot v1.1.6
+ * 2003-03-10 - kharris@nexus-tech.net - ported to u-boot
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _FAT_H_
+#define _FAT_H_
+
+#include <asm/byteorder.h>
+
+#define CONFIG_SUPPORT_VFAT
+/* Maximum Long File Name length supported here is 128 UTF-16 code units */
+#define VFAT_MAXLEN_BYTES	256 /* Maximum LFN buffer in bytes */
+#define VFAT_MAXSEQ		9   /* Up to 9 of 13 2-byte UTF-16 entries */
+#define PREFETCH_BLOCKS		2
+
+#define MAX_CLUSTSIZE	65536
+#define DIRENTSPERBLOCK	(mydata->sect_size / sizeof(dir_entry))
+#define DIRENTSPERCLUST	((mydata->clust_size * mydata->sect_size) / \
+			 sizeof(dir_entry))
+
+#define FATBUFBLOCKS	6
+#define FATBUFSIZE	(mydata->sect_size * FATBUFBLOCKS)
+#define FAT12BUFSIZE	((FATBUFSIZE*2)/3)
+#define FAT16BUFSIZE	(FATBUFSIZE/2)
+#define FAT32BUFSIZE	(FATBUFSIZE/4)
+
+
+/* Filesystem identifiers */
+#define FAT12_SIGN	"FAT12   "
+#define FAT16_SIGN	"FAT16   "
+#define FAT32_SIGN	"FAT32   "
+#define SIGNLEN		8
+
+/* File attributes */
+#define ATTR_RO	1
+#define ATTR_HIDDEN	2
+#define ATTR_SYS	4
+#define ATTR_VOLUME	8
+#define ATTR_DIR	16
+#define ATTR_ARCH	32
+
+#define ATTR_VFAT	(ATTR_RO | ATTR_HIDDEN | ATTR_SYS | ATTR_VOLUME)
+
+#define DELETED_FLAG	((char)0xe5) /* Marks deleted files when in name[0] */
+#define aRING		0x05	     /* Used as special character in name[0] */
+
+/*
+ * Indicates that the entry is the last long entry in a set of long
+ * dir entries
+ */
+#define LAST_LONG_ENTRY_MASK	0x40
+
+/* Flags telling whether we should read a file or list a directory */
+#define LS_NO		0
+#define LS_YES		1
+#define LS_DIR		1
+#define LS_ROOT		2
+
+#define ISDIRDELIM(c)	((c) == '/' || (c) == '\\')
+
+#define FSTYPE_NONE	(-1)
+
+#if defined(__linux__) && defined(__KERNEL__)
+#define FAT2CPU16	le16_to_cpu
+#define FAT2CPU32	le32_to_cpu
+#else
+#if __LITTLE_ENDIAN
+#define FAT2CPU16(x)	(x)
+#define FAT2CPU32(x)	(x)
+#else
+#define FAT2CPU16(x)	((((x) & 0x00ff) << 8) | (((x) & 0xff00) >> 8))
+#define FAT2CPU32(x)	((((x) & 0x000000ff) << 24)  |	\
+			 (((x) & 0x0000ff00) << 8)  |	\
+			 (((x) & 0x00ff0000) >> 8)  |	\
+			 (((x) & 0xff000000) >> 24))
+#endif
+#endif
+
+#define START(dent)	(FAT2CPU16((dent)->start) \
+			+ (mydata->fatsize != 32 ? 0 : \
+			  (FAT2CPU16((dent)->starthi) << 16)))
+#define IS_LAST_CLUST(x, fatsize) ((x) >= ((fatsize) != 32 ? \
+					((fatsize) != 16 ? 0xff8 : 0xfff8) : \
+					0xffffff8))
+#define CHECK_CLUST(x, fatsize) ((x) <= 1 || \
+				(x) >= ((fatsize) != 32 ? \
+					((fatsize) != 16 ? 0xff0 : 0xfff0) : \
+					0xffffff0))
+
+typedef struct boot_sector {
+	__u8	ignored[3];	/* Bootstrap code */
+	char	system_id[8];	/* Name of fs */
+	__u8	sector_size[2];	/* Bytes/sector */
+	__u8	cluster_size;	/* Sectors/cluster */
+	__u16	reserved;	/* Number of reserved sectors */
+	__u8	fats;		/* Number of FATs */
+	__u8	dir_entries[2];	/* Number of root directory entries */
+	__u8	sectors[2];	/* Number of sectors */
+	__u8	media;		/* Media code */
+	__u16	fat_length;	/* Sectors/FAT */
+	__u16	secs_track;	/* Sectors/track */
+	__u16	heads;		/* Number of heads */
+	__u32	hidden;		/* Number of hidden sectors */
+	__u32	total_sect;	/* Number of sectors (if sectors == 0) */
+
+	/* FAT32 only */
+	__u32	fat32_length;	/* Sectors/FAT */
+	__u16	flags;		/* Bit 8: fat mirroring, low 4: active fat */
+	__u8	version[2];	/* Filesystem version */
+	__u32	root_cluster;	/* First cluster in root directory */
+	__u16	info_sector;	/* Filesystem info sector */
+	__u16	backup_boot;	/* Backup boot sector */
+	__u16	reserved2[6];	/* Unused */
+} boot_sector;
+
+typedef struct volume_info
+{
+	__u8 drive_number;	/* BIOS drive number */
+	__u8 reserved;		/* Unused */
+	__u8 ext_boot_sign;	/* 0x29 if fields below exist (DOS 3.3+) */
+	__u8 volume_id[4];	/* Volume ID number */
+	char volume_label[11];	/* Volume label */
+	char fs_type[8];	/* Typically FAT12, FAT16, or FAT32 */
+	/* Boot code comes next, all but 2 bytes to fill up sector */
+	/* Boot sign comes last, 2 bytes */
+} volume_info;
+
+typedef struct dir_entry {
+	char	name[8],ext[3];	/* Name and extension */
+	__u8	attr;		/* Attribute bits */
+	__u8	lcase;		/* Case for base and extension */
+	__u8	ctime_ms;	/* Creation time, milliseconds */
+	__u16	ctime;		/* Creation time */
+	__u16	cdate;		/* Creation date */
+	__u16	adate;		/* Last access date */
+	__u16	starthi;	/* High 16 bits of cluster in FAT32 */
+	__u16	time,date,start;/* Time, date and first cluster */
+	__u32	size;		/* File size in bytes */
+} dir_entry;
+
+typedef struct dir_slot {
+	__u8	id;		/* Sequence number for slot */
+	__u8	name0_4[10];	/* First 5 characters in name */
+	__u8	attr;		/* Attribute byte */
+	__u8	reserved;	/* Unused */
+	__u8	alias_checksum;/* Checksum for 8.3 alias */
+	__u8	name5_10[12];	/* 6 more characters in name */
+	__u16	start;		/* Unused */
+	__u8	name11_12[4];	/* Last 2 characters in name */
+} dir_slot;
+
+/*
+ * Private filesystem parameters
+ *
+ * Note: FAT buffer has to be 32 bit aligned
+ * (see FAT32 accesses)
+ */
+typedef struct {
+	__u8	*fatbuf;	/* Current FAT buffer */
+	int	fatsize;	/* Size of FAT in bits */
+	__u32	fatlength;	/* Length of FAT in sectors */
+	__u16	fat_sect;	/* Starting sector of the FAT */
+	__u32	rootdir_sect;	/* Start sector of root directory */
+	__u16	sect_size;	/* Size of sectors in bytes */
+	__u16	clust_size;	/* Size of clusters in sectors */
+	int	data_begin;	/* The sector of the first cluster, can be negative */
+	int	fatbufnum;	/* Used by get_fatent, init to -1 */
+} fsdata;
+
+typedef int	(file_detectfs_func)(void);
+typedef int	(file_ls_func)(const char *dir);
+typedef long	(file_read_func)(const char *filename, void *buffer,
+				 unsigned long maxsize);
+
+struct filesystem {
+	file_detectfs_func	*detect;
+	file_ls_func		*ls;
+	file_read_func		*read;
+	const char		name[12];
+};
+
+/* FAT tables */
+file_detectfs_func	file_fat_detectfs;
+file_ls_func		file_fat_ls;
+file_read_func		file_fat_read;
+
+/* Currently this doesn't check if the dir exists or is valid... */
+int file_cd(const char *path);
+int file_fat_detectfs(void);
+int file_fat_ls(const char *dir);
+int fat_exists(const char *filename);
+long file_fat_read_at(const char *filename, unsigned long pos, void *buffer,
+		      unsigned long maxsize);
+long file_fat_read(const char *filename, void *buffer, unsigned long maxsize);
+const char *file_getfsname(int idx);
+int fat_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info);
+int fat_register_device(block_dev_desc_t *dev_desc, int part_no);
+
+int file_fat_write(const char *filename, void *buffer, unsigned long maxsize);
+int fat_read_file(const char *filename, void *buf, int offset, int len);
+void fat_close(void);
+#endif /* _FAT_H_ */
diff --git a/qemu/roms/u-boot/include/fdt.h b/qemu/roms/u-boot/include/fdt.h
new file mode 100644
index 000000000..526aedb51
--- /dev/null
+++ b/qemu/roms/u-boot/include/fdt.h
@@ -0,0 +1,111 @@
+#ifndef _FDT_H
+#define _FDT_H
+/*
+ * libfdt - Flat Device Tree manipulation
+ * Copyright (C) 2006 David Gibson, IBM Corporation.
+ * Copyright 2012 Kim Phillips, Freescale Semiconductor.
+ *
+ * libfdt is dual licensed: you can use it either under the terms of
+ * the GPL, or the BSD license, at your option.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this library; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Alternatively,
+ *
+ *  b) Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *     1. Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *     2. Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ *     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ *     CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ *     INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ *     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ *     CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *     SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *     NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *     HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ *     OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ *     EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ASSEMBLY__
+
+struct fdt_header {
+	fdt32_t magic;			 /* magic word FDT_MAGIC */
+	fdt32_t totalsize;		 /* total size of DT block */
+	fdt32_t off_dt_struct;		 /* offset to structure */
+	fdt32_t off_dt_strings;		 /* offset to strings */
+	fdt32_t off_mem_rsvmap;		 /* offset to memory reserve map */
+	fdt32_t version;		 /* format version */
+	fdt32_t last_comp_version;	 /* last compatible version */
+
+	/* version 2 fields below */
+	fdt32_t boot_cpuid_phys;	 /* Which physical CPU id we're
+					    booting on */
+	/* version 3 fields below */
+	fdt32_t size_dt_strings;	 /* size of the strings block */
+
+	/* version 17 fields below */
+	fdt32_t size_dt_struct;		 /* size of the structure block */
+};
+
+struct fdt_reserve_entry {
+	fdt64_t address;
+	fdt64_t size;
+};
+
+struct fdt_node_header {
+	fdt32_t tag;
+	char name[0];
+};
+
+struct fdt_property {
+	fdt32_t tag;
+	fdt32_t len;
+	fdt32_t nameoff;
+	char data[0];
+};
+
+#endif /* !__ASSEMBLY */
+
+#define FDT_MAGIC	0xd00dfeed	/* 4: version, 4: total size */
+#define FDT_TAGSIZE	sizeof(fdt32_t)
+
+#define FDT_BEGIN_NODE	0x1		/* Start node: full name */
+#define FDT_END_NODE	0x2		/* End node */
+#define FDT_PROP	0x3		/* Property: name off,
+					   size, content */
+#define FDT_NOP		0x4		/* nop */
+#define FDT_END		0x9
+
+#define FDT_V1_SIZE	(7*sizeof(fdt32_t))
+#define FDT_V2_SIZE	(FDT_V1_SIZE + sizeof(fdt32_t))
+#define FDT_V3_SIZE	(FDT_V2_SIZE + sizeof(fdt32_t))
+#define FDT_V16_SIZE	FDT_V3_SIZE
+#define FDT_V17_SIZE	(FDT_V16_SIZE + sizeof(fdt32_t))
+
+#endif /* _FDT_H */
diff --git a/qemu/roms/u-boot/include/fdt_support.h b/qemu/roms/u-boot/include/fdt_support.h
new file mode 100644
index 000000000..ae010bb62
--- /dev/null
+++ b/qemu/roms/u-boot/include/fdt_support.h
@@ -0,0 +1,134 @@
+/*
+ * (C) Copyright 2007
+ * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __FDT_SUPPORT_H
+#define __FDT_SUPPORT_H
+
+#ifdef CONFIG_OF_LIBFDT
+
+#include <libfdt.h>
+
+u32 fdt_getprop_u32_default_node(const void *fdt, int off, int cell,
+				const char *prop, const u32 dflt);
+u32 fdt_getprop_u32_default(const void *fdt, const char *path,
+				const char *prop, const u32 dflt);
+int fdt_chosen(void *fdt, int force);
+int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end, int force);
+void do_fixup_by_path(void *fdt, const char *path, const char *prop,
+		      const void *val, int len, int create);
+void do_fixup_by_path_u32(void *fdt, const char *path, const char *prop,
+			  u32 val, int create);
+
+static inline void do_fixup_by_path_string(void *fdt, const char *path,
+					   const char *prop, const char *status)
+{
+	do_fixup_by_path(fdt, path, prop, status, strlen(status) + 1, 1);
+}
+
+void do_fixup_by_prop(void *fdt,
+		      const char *pname, const void *pval, int plen,
+		      const char *prop, const void *val, int len,
+		      int create);
+void do_fixup_by_prop_u32(void *fdt,
+			  const char *pname, const void *pval, int plen,
+			  const char *prop, u32 val, int create);
+void do_fixup_by_compat(void *fdt, const char *compat,
+			const char *prop, const void *val, int len, int create);
+void do_fixup_by_compat_u32(void *fdt, const char *compat,
+			    const char *prop, u32 val, int create);
+int fdt_fixup_memory(void *blob, u64 start, u64 size);
+int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[], int banks);
+void fdt_fixup_ethernet(void *fdt);
+int fdt_find_and_setprop(void *fdt, const char *node, const char *prop,
+			 const void *val, int len, int create);
+void fdt_fixup_qe_firmware(void *fdt);
+
+#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
+void fdt_fixup_dr_usb(void *blob, bd_t *bd);
+#else
+static inline void fdt_fixup_dr_usb(void *blob, bd_t *bd) {}
+#endif /* defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) */
+
+#if defined(CONFIG_SYS_FSL_SEC_COMPAT)
+void fdt_fixup_crypto_node(void *blob, int sec_rev);
+#else
+static inline void fdt_fixup_crypto_node(void *blob, int sec_rev) {}
+#endif
+
+#ifdef CONFIG_PCI
+#include <pci.h>
+int fdt_pci_dma_ranges(void *blob, int phb_off, struct pci_controller *hose);
+#endif
+
+void ft_board_setup(void *blob, bd_t *bd);
+/*
+ * The keystone2 SOC requires all 32 bit aliased addresses to be converted
+ * to their 36 physical format. This has to happen after all fdt nodes
+ * are added or modified by the image_setup_libfdt(). The ft_board_setup_ex()
+ * called at the end of the image_setup_libfdt() is to do that convertion.
+ */
+void ft_board_setup_ex(void *blob, bd_t *bd);
+void ft_cpu_setup(void *blob, bd_t *bd);
+void ft_pci_setup(void *blob, bd_t *bd);
+
+void set_working_fdt_addr(void *addr);
+int fdt_resize(void *blob);
+int fdt_increase_size(void *fdt, int add_len);
+
+int fdt_fixup_nor_flash_size(void *blob);
+
+void fdt_fixup_mtdparts(void *fdt, void *node_info, int node_info_size);
+void fdt_del_node_and_alias(void *blob, const char *alias);
+u64 fdt_translate_address(void *blob, int node_offset, const __be32 *in_addr);
+int fdt_node_offset_by_compat_reg(void *blob, const char *compat,
+					phys_addr_t compat_off);
+int fdt_alloc_phandle(void *blob);
+int fdt_set_phandle(void *fdt, int nodeoffset, uint32_t phandle);
+unsigned int fdt_create_phandle(void *fdt, int nodeoffset);
+int fdt_add_edid(void *blob, const char *compat, unsigned char *buf);
+
+int fdt_verify_alias_address(void *fdt, int anode, const char *alias,
+			      u64 addr);
+u64 fdt_get_base_address(void *fdt, int node);
+int fdt_read_range(void *fdt, int node, int n, uint64_t *child_addr,
+		   uint64_t *addr, uint64_t *len);
+
+enum fdt_status {
+	FDT_STATUS_OKAY,
+	FDT_STATUS_DISABLED,
+	FDT_STATUS_FAIL,
+	FDT_STATUS_FAIL_ERROR_CODE,
+};
+int fdt_set_node_status(void *fdt, int nodeoffset,
+			enum fdt_status status, unsigned int error_code);
+static inline int fdt_status_okay(void *fdt, int nodeoffset)
+{
+	return fdt_set_node_status(fdt, nodeoffset, FDT_STATUS_OKAY, 0);
+}
+static inline int fdt_status_disabled(void *fdt, int nodeoffset)
+{
+	return fdt_set_node_status(fdt, nodeoffset, FDT_STATUS_DISABLED, 0);
+}
+
+int fdt_set_status_by_alias(void *fdt, const char* alias,
+			    enum fdt_status status, unsigned int error_code);
+static inline int fdt_status_okay_by_alias(void *fdt, const char* alias)
+{
+	return fdt_set_status_by_alias(fdt, alias, FDT_STATUS_OKAY, 0);
+}
+static inline int fdt_status_disabled_by_alias(void *fdt, const char* alias)
+{
+	return fdt_set_status_by_alias(fdt, alias, FDT_STATUS_DISABLED, 0);
+}
+
+#endif /* ifdef CONFIG_OF_LIBFDT */
+
+#ifdef USE_HOSTCC
+int fdtdec_get_int(const void *blob, int node, const char *prop_name,
+		int default_val);
+#endif
+#endif /* ifndef __FDT_SUPPORT_H */
diff --git a/qemu/roms/u-boot/include/fdtdec.h b/qemu/roms/u-boot/include/fdtdec.h
new file mode 100644
index 000000000..3196cf668
--- /dev/null
+++ b/qemu/roms/u-boot/include/fdtdec.h
@@ -0,0 +1,555 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __fdtdec_h
+#define __fdtdec_h
+
+/*
+ * This file contains convenience functions for decoding useful and
+ * enlightening information from FDTs. It is intended to be used by device
+ * drivers and board-specific code within U-Boot. It aims to reduce the
+ * amount of FDT munging required within U-Boot itself, so that driver code
+ * changes to support FDT are minimized.
+ */
+
+#include <libfdt.h>
+
+/*
+ * A typedef for a physical address. Note that fdt data is always big
+ * endian even on a litle endian machine.
+ */
+#ifdef CONFIG_PHYS_64BIT
+typedef u64 fdt_addr_t;
+typedef u64 fdt_size_t;
+#define FDT_ADDR_T_NONE (-1ULL)
+#define fdt_addr_to_cpu(reg) be64_to_cpu(reg)
+#define fdt_size_to_cpu(reg) be64_to_cpu(reg)
+#else
+typedef u32 fdt_addr_t;
+typedef u32 fdt_size_t;
+#define FDT_ADDR_T_NONE (-1U)
+#define fdt_addr_to_cpu(reg) be32_to_cpu(reg)
+#define fdt_size_to_cpu(reg) be32_to_cpu(reg)
+#endif
+
+/* Information obtained about memory from the FDT */
+struct fdt_memory {
+	fdt_addr_t start;
+	fdt_addr_t end;
+};
+
+/**
+ * Compat types that we know about and for which we might have drivers.
+ * Each is named COMPAT_<dir>_<filename> where <dir> is the directory
+ * within drivers.
+ */
+enum fdt_compat_id {
+	COMPAT_UNKNOWN,
+	COMPAT_NVIDIA_TEGRA20_USB,	/* Tegra20 USB port */
+	COMPAT_NVIDIA_TEGRA30_USB,	/* Tegra30 USB port */
+	COMPAT_NVIDIA_TEGRA114_USB,	/* Tegra114 USB port */
+	COMPAT_NVIDIA_TEGRA114_I2C,	/* Tegra114 I2C w/single clock source */
+	COMPAT_NVIDIA_TEGRA20_I2C,	/* Tegra20 i2c */
+	COMPAT_NVIDIA_TEGRA20_DVC,	/* Tegra20 dvc (really just i2c) */
+	COMPAT_NVIDIA_TEGRA20_EMC,	/* Tegra20 memory controller */
+	COMPAT_NVIDIA_TEGRA20_EMC_TABLE, /* Tegra20 memory timing table */
+	COMPAT_NVIDIA_TEGRA20_KBC,	/* Tegra20 Keyboard */
+	COMPAT_NVIDIA_TEGRA20_NAND,	/* Tegra2 NAND controller */
+	COMPAT_NVIDIA_TEGRA20_PWM,	/* Tegra 2 PWM controller */
+	COMPAT_NVIDIA_TEGRA20_DC,	/* Tegra 2 Display controller */
+	COMPAT_NVIDIA_TEGRA124_SDMMC,	/* Tegra124 SDMMC controller */
+	COMPAT_NVIDIA_TEGRA30_SDMMC,	/* Tegra30 SDMMC controller */
+	COMPAT_NVIDIA_TEGRA20_SDMMC,	/* Tegra20 SDMMC controller */
+	COMPAT_NVIDIA_TEGRA20_SFLASH,	/* Tegra 2 SPI flash controller */
+	COMPAT_NVIDIA_TEGRA20_SLINK,	/* Tegra 2 SPI SLINK controller */
+	COMPAT_NVIDIA_TEGRA114_SPI,	/* Tegra 114 SPI controller */
+	COMPAT_SMSC_LAN9215,		/* SMSC 10/100 Ethernet LAN9215 */
+	COMPAT_SAMSUNG_EXYNOS5_SROMC,	/* Exynos5 SROMC */
+	COMPAT_SAMSUNG_S3C2440_I2C,	/* Exynos I2C Controller */
+	COMPAT_SAMSUNG_EXYNOS5_SOUND,	/* Exynos Sound */
+	COMPAT_WOLFSON_WM8994_CODEC,	/* Wolfson WM8994 Sound Codec */
+	COMPAT_SAMSUNG_EXYNOS_SPI,	/* Exynos SPI */
+	COMPAT_GOOGLE_CROS_EC,		/* Google CROS_EC Protocol */
+	COMPAT_GOOGLE_CROS_EC_KEYB,	/* Google CROS_EC Keyboard */
+	COMPAT_SAMSUNG_EXYNOS_EHCI,	/* Exynos EHCI controller */
+	COMPAT_SAMSUNG_EXYNOS5_XHCI,	/* Exynos5 XHCI controller */
+	COMPAT_SAMSUNG_EXYNOS_USB_PHY,	/* Exynos phy controller for usb2.0 */
+	COMPAT_SAMSUNG_EXYNOS5_USB3_PHY,/* Exynos phy controller for usb3.0 */
+	COMPAT_SAMSUNG_EXYNOS_TMU,	/* Exynos TMU */
+	COMPAT_SAMSUNG_EXYNOS_FIMD,	/* Exynos Display controller */
+	COMPAT_SAMSUNG_EXYNOS_MIPI_DSI,	/* Exynos mipi dsi */
+	COMPAT_SAMSUNG_EXYNOS5_DP,	/* Exynos Display port controller */
+	COMPAT_SAMSUNG_EXYNOS5_DWMMC,	/* Exynos5 DWMMC controller */
+	COMPAT_SAMSUNG_EXYNOS_MMC,	/* Exynos MMC controller */
+	COMPAT_SAMSUNG_EXYNOS_SERIAL,	/* Exynos UART */
+	COMPAT_MAXIM_MAX77686_PMIC,	/* MAX77686 PMIC */
+	COMPAT_GENERIC_SPI_FLASH,	/* Generic SPI Flash chip */
+	COMPAT_MAXIM_98095_CODEC,	/* MAX98095 Codec */
+	COMPAT_INFINEON_SLB9635_TPM,	/* Infineon SLB9635 TPM */
+	COMPAT_INFINEON_SLB9645_TPM,	/* Infineon SLB9645 TPM */
+	COMPAT_SAMSUNG_EXYNOS5_I2C,	/* Exynos5 High Speed I2C Controller */
+	COMPAT_SANDBOX_HOST_EMULATION,	/* Sandbox emulation of a function */
+	COMPAT_SANDBOX_LCD_SDL,		/* Sandbox LCD emulation with SDL */
+
+	COMPAT_COUNT,
+};
+
+/* GPIOs are numbered from 0 */
+enum {
+	FDT_GPIO_NONE = -1U,	/* an invalid GPIO used to end our list */
+
+	FDT_GPIO_ACTIVE_LOW = 1 << 0,	/* input is active low (else high) */
+};
+
+/* This is the state of a GPIO pin as defined by the fdt */
+struct fdt_gpio_state {
+	const char *name;	/* name of the fdt property defining this */
+	uint gpio;		/* GPIO number, or FDT_GPIO_NONE if none */
+	u8 flags;		/* FDT_GPIO_... flags */
+};
+
+/* This tells us whether a fdt_gpio_state record is valid or not */
+#define fdt_gpio_isvalid(x) ((x)->gpio != FDT_GPIO_NONE)
+
+/**
+ * Read the GPIO taking into account the polarity of the pin.
+ *
+ * @param gpio		pointer to the decoded gpio
+ * @return value of the gpio if successful, < 0 if unsuccessful
+ */
+int fdtdec_get_gpio(struct fdt_gpio_state *gpio);
+
+/**
+ * Write the GPIO taking into account the polarity of the pin.
+ *
+ * @param gpio		pointer to the decoded gpio
+ * @return 0 if successful
+ */
+int fdtdec_set_gpio(struct fdt_gpio_state *gpio, int val);
+
+/**
+ * Find the next numbered alias for a peripheral. This is used to enumerate
+ * all the peripherals of a certain type.
+ *
+ * Do the first call with *upto = 0. Assuming /aliases/<name>0 exists then
+ * this function will return a pointer to the node the alias points to, and
+ * then update *upto to 1. Next time you call this function, the next node
+ * will be returned.
+ *
+ * All nodes returned will match the compatible ID, as it is assumed that
+ * all peripherals use the same driver.
+ *
+ * @param blob		FDT blob to use
+ * @param name		Root name of alias to search for
+ * @param id		Compatible ID to look for
+ * @return offset of next compatible node, or -FDT_ERR_NOTFOUND if no more
+ */
+int fdtdec_next_alias(const void *blob, const char *name,
+		enum fdt_compat_id id, int *upto);
+
+/**
+ * Find the compatible ID for a given node.
+ *
+ * Generally each node has at least one compatible string attached to it.
+ * This function looks through our list of known compatible strings and
+ * returns the corresponding ID which matches the compatible string.
+ *
+ * @param blob		FDT blob to use
+ * @param node		Node containing compatible string to find
+ * @return compatible ID, or COMPAT_UNKNOWN if we cannot find a match
+ */
+enum fdt_compat_id fdtdec_lookup(const void *blob, int node);
+
+/**
+ * Find the next compatible node for a peripheral.
+ *
+ * Do the first call with node = 0. This function will return a pointer to
+ * the next compatible node. Next time you call this function, pass the
+ * value returned, and the next node will be provided.
+ *
+ * @param blob		FDT blob to use
+ * @param node		Start node for search
+ * @param id		Compatible ID to look for (enum fdt_compat_id)
+ * @return offset of next compatible node, or -FDT_ERR_NOTFOUND if no more
+ */
+int fdtdec_next_compatible(const void *blob, int node,
+		enum fdt_compat_id id);
+
+/**
+ * Find the next compatible subnode for a peripheral.
+ *
+ * Do the first call with node set to the parent and depth = 0. This
+ * function will return the offset of the next compatible node. Next time
+ * you call this function, pass the node value returned last time, with
+ * depth unchanged, and the next node will be provided.
+ *
+ * @param blob		FDT blob to use
+ * @param node		Start node for search
+ * @param id		Compatible ID to look for (enum fdt_compat_id)
+ * @param depthp	Current depth (set to 0 before first call)
+ * @return offset of next compatible node, or -FDT_ERR_NOTFOUND if no more
+ */
+int fdtdec_next_compatible_subnode(const void *blob, int node,
+		enum fdt_compat_id id, int *depthp);
+
+/**
+ * Look up an address property in a node and return it as an address.
+ * The property must hold either one address with no trailing data or
+ * one address with a length. This is only tested on 32-bit machines.
+ *
+ * @param blob	FDT blob
+ * @param node	node to examine
+ * @param prop_name	name of property to find
+ * @return address, if found, or FDT_ADDR_T_NONE if not
+ */
+fdt_addr_t fdtdec_get_addr(const void *blob, int node,
+		const char *prop_name);
+
+/**
+ * Look up an address property in a node and return it as an address.
+ * The property must hold one address with a length. This is only tested
+ * on 32-bit machines.
+ *
+ * @param blob	FDT blob
+ * @param node	node to examine
+ * @param prop_name	name of property to find
+ * @return address, if found, or FDT_ADDR_T_NONE if not
+ */
+fdt_addr_t fdtdec_get_addr_size(const void *blob, int node,
+		const char *prop_name, fdt_size_t *sizep);
+
+/**
+ * Look up a 32-bit integer property in a node and return it. The property
+ * must have at least 4 bytes of data. The value of the first cell is
+ * returned.
+ *
+ * @param blob	FDT blob
+ * @param node	node to examine
+ * @param prop_name	name of property to find
+ * @param default_val	default value to return if the property is not found
+ * @return integer value, if found, or default_val if not
+ */
+s32 fdtdec_get_int(const void *blob, int node, const char *prop_name,
+		s32 default_val);
+
+/**
+ * Look up a 64-bit integer property in a node and return it. The property
+ * must have at least 8 bytes of data (2 cells). The first two cells are
+ * concatenated to form a 8 bytes value, where the first cell is top half and
+ * the second cell is bottom half.
+ *
+ * @param blob	FDT blob
+ * @param node	node to examine
+ * @param prop_name	name of property to find
+ * @param default_val	default value to return if the property is not found
+ * @return integer value, if found, or default_val if not
+ */
+uint64_t fdtdec_get_uint64(const void *blob, int node, const char *prop_name,
+		uint64_t default_val);
+
+/**
+ * Checks whether a node is enabled.
+ * This looks for a 'status' property. If this exists, then returns 1 if
+ * the status is 'ok' and 0 otherwise. If there is no status property,
+ * it returns 1 on the assumption that anything mentioned should be enabled
+ * by default.
+ *
+ * @param blob	FDT blob
+ * @param node	node to examine
+ * @return integer value 0 (not enabled) or 1 (enabled)
+ */
+int fdtdec_get_is_enabled(const void *blob, int node);
+
+/**
+ * Make sure we have a valid fdt available to control U-Boot.
+ *
+ * If not, a message is printed to the console if the console is ready.
+ *
+ * @return 0 if all ok, -1 if not
+ */
+int fdtdec_prepare_fdt(void);
+
+/**
+ * Checks that we have a valid fdt available to control U-Boot.
+
+ * However, if not then for the moment nothing is done, since this function
+ * is called too early to panic().
+ *
+ * @returns 0
+ */
+int fdtdec_check_fdt(void);
+
+/**
+ * Find the nodes for a peripheral and return a list of them in the correct
+ * order. This is used to enumerate all the peripherals of a certain type.
+ *
+ * To use this, optionally set up a /aliases node with alias properties for
+ * a peripheral. For example, for usb you could have:
+ *
+ * aliases {
+ *		usb0 = "/ehci@c5008000";
+ *		usb1 = "/ehci@c5000000";
+ * };
+ *
+ * Pass "usb" as the name to this function and will return a list of two
+ * nodes offsets: /ehci@c5008000 and ehci@c5000000.
+ *
+ * All nodes returned will match the compatible ID, as it is assumed that
+ * all peripherals use the same driver.
+ *
+ * If no alias node is found, then the node list will be returned in the
+ * order found in the fdt. If the aliases mention a node which doesn't
+ * exist, then this will be ignored. If nodes are found with no aliases,
+ * they will be added in any order.
+ *
+ * If there is a gap in the aliases, then this function return a 0 node at
+ * that position. The return value will also count these gaps.
+ *
+ * This function checks node properties and will not return nodes which are
+ * marked disabled (status = "disabled").
+ *
+ * @param blob		FDT blob to use
+ * @param name		Root name of alias to search for
+ * @param id		Compatible ID to look for
+ * @param node_list	Place to put list of found nodes
+ * @param maxcount	Maximum number of nodes to find
+ * @return number of nodes found on success, FTD_ERR_... on error
+ */
+int fdtdec_find_aliases_for_id(const void *blob, const char *name,
+			enum fdt_compat_id id, int *node_list, int maxcount);
+
+/*
+ * This function is similar to fdtdec_find_aliases_for_id() except that it
+ * adds to the node_list that is passed in. Any 0 elements are considered
+ * available for allocation - others are considered already used and are
+ * skipped.
+ *
+ * You can use this by calling fdtdec_find_aliases_for_id() with an
+ * uninitialised array, then setting the elements that are returned to -1,
+ * say, then calling this function, perhaps with a different compat id.
+ * Any elements you get back that are >0 are new nodes added by the call
+ * to this function.
+ *
+ * Note that if you have some nodes with aliases and some without, you are
+ * sailing close to the wind. The call to fdtdec_find_aliases_for_id() with
+ * one compat_id may fill in positions for which you have aliases defined
+ * for another compat_id. When you later call *this* function with the second
+ * compat_id, the alias positions may already be used. A debug warning may
+ * be generated in this case, but it is safest to define aliases for all
+ * nodes when you care about the ordering.
+ */
+int fdtdec_add_aliases_for_id(const void *blob, const char *name,
+			enum fdt_compat_id id, int *node_list, int maxcount);
+
+/*
+ * Get the name for a compatible ID
+ *
+ * @param id		Compatible ID to look for
+ * @return compatible string for that id
+ */
+const char *fdtdec_get_compatible(enum fdt_compat_id id);
+
+/* Look up a phandle and follow it to its node. Then return the offset
+ * of that node.
+ *
+ * @param blob		FDT blob
+ * @param node		node to examine
+ * @param prop_name	name of property to find
+ * @return node offset if found, -ve error code on error
+ */
+int fdtdec_lookup_phandle(const void *blob, int node, const char *prop_name);
+
+/**
+ * Look up a property in a node and return its contents in an integer
+ * array of given length. The property must have at least enough data for
+ * the array (4*count bytes). It may have more, but this will be ignored.
+ *
+ * @param blob		FDT blob
+ * @param node		node to examine
+ * @param prop_name	name of property to find
+ * @param array		array to fill with data
+ * @param count		number of array elements
+ * @return 0 if ok, or -FDT_ERR_NOTFOUND if the property is not found,
+ *		or -FDT_ERR_BADLAYOUT if not enough data
+ */
+int fdtdec_get_int_array(const void *blob, int node, const char *prop_name,
+		u32 *array, int count);
+
+/**
+ * Look up a property in a node and return a pointer to its contents as a
+ * unsigned int array of given length. The property must have at least enough
+ * data for the array ('count' cells). It may have more, but this will be
+ * ignored. The data is not copied.
+ *
+ * Note that you must access elements of the array with fdt32_to_cpu(),
+ * since the elements will be big endian even on a little endian machine.
+ *
+ * @param blob		FDT blob
+ * @param node		node to examine
+ * @param prop_name	name of property to find
+ * @param count		number of array elements
+ * @return pointer to array if found, or NULL if the property is not
+ *		found or there is not enough data
+ */
+const u32 *fdtdec_locate_array(const void *blob, int node,
+			       const char *prop_name, int count);
+
+/**
+ * Look up a boolean property in a node and return it.
+ *
+ * A boolean properly is true if present in the device tree and false if not
+ * present, regardless of its value.
+ *
+ * @param blob	FDT blob
+ * @param node	node to examine
+ * @param prop_name	name of property to find
+ * @return 1 if the properly is present; 0 if it isn't present
+ */
+int fdtdec_get_bool(const void *blob, int node, const char *prop_name);
+
+/**
+ * Decode a single GPIOs from an FDT.
+ *
+ * If the property is not found, then the GPIO structure will still be
+ * initialised, with gpio set to FDT_GPIO_NONE. This makes it easy to
+ * provide optional GPIOs.
+ *
+ * @param blob		FDT blob to use
+ * @param node		Node to look at
+ * @param prop_name	Node property name
+ * @param gpio		gpio elements to fill from FDT
+ * @return 0 if ok, -FDT_ERR_NOTFOUND if the property is missing.
+ */
+int fdtdec_decode_gpio(const void *blob, int node, const char *prop_name,
+		struct fdt_gpio_state *gpio);
+
+/**
+ * Decode a list of GPIOs from an FDT. This creates a list of GPIOs with no
+ * terminating item.
+ *
+ * @param blob         FDT blob to use
+ * @param node         Node to look at
+ * @param prop_name    Node property name
+ * @param gpio         Array of gpio elements to fill from FDT. This will be
+ *                     untouched if either 0 or an error is returned
+ * @param max_count    Maximum number of elements allowed
+ * @return number of GPIOs read if ok, -FDT_ERR_BADLAYOUT if max_count would
+ * be exceeded, or -FDT_ERR_NOTFOUND if the property is missing.
+ */
+int fdtdec_decode_gpios(const void *blob, int node, const char *prop_name,
+		struct fdt_gpio_state *gpio, int max_count);
+
+/**
+ * Set up a GPIO pin according to the provided gpio information. At present this
+ * just requests the GPIO.
+ *
+ * If the gpio is FDT_GPIO_NONE, no action is taken. This makes it easy to
+ * deal with optional GPIOs.
+ *
+ * @param gpio		GPIO info to use for set up
+ * @return 0 if all ok or gpio was FDT_GPIO_NONE; -1 on error
+ */
+int fdtdec_setup_gpio(struct fdt_gpio_state *gpio);
+
+/**
+ * Look in the FDT for a config item with the given name and return its value
+ * as a 32-bit integer. The property must have at least 4 bytes of data. The
+ * value of the first cell is returned.
+ *
+ * @param blob		FDT blob to use
+ * @param prop_name	Node property name
+ * @param default_val	default value to return if the property is not found
+ * @return integer value, if found, or default_val if not
+ */
+int fdtdec_get_config_int(const void *blob, const char *prop_name,
+		int default_val);
+
+/**
+ * Look in the FDT for a config item with the given name
+ * and return whether it exists.
+ *
+ * @param blob		FDT blob
+ * @param prop_name	property name to look up
+ * @return 1, if it exists, or 0 if not
+ */
+int fdtdec_get_config_bool(const void *blob, const char *prop_name);
+
+/**
+ * Look in the FDT for a config item with the given name and return its value
+ * as a string.
+ *
+ * @param blob          FDT blob
+ * @param prop_name     property name to look up
+ * @returns property string, NULL on error.
+ */
+char *fdtdec_get_config_string(const void *blob, const char *prop_name);
+
+/*
+ * Look up a property in a node and return its contents in a byte
+ * array of given length. The property must have at least enough data for
+ * the array (count bytes). It may have more, but this will be ignored.
+ *
+ * @param blob		FDT blob
+ * @param node		node to examine
+ * @param prop_name	name of property to find
+ * @param array		array to fill with data
+ * @param count		number of array elements
+ * @return 0 if ok, or -FDT_ERR_MISSING if the property is not found,
+ *		or -FDT_ERR_BADLAYOUT if not enough data
+ */
+int fdtdec_get_byte_array(const void *blob, int node, const char *prop_name,
+		u8 *array, int count);
+
+/**
+ * Look up a property in a node and return a pointer to its contents as a
+ * byte array of given length. The property must have at least enough data
+ * for the array (count bytes). It may have more, but this will be ignored.
+ * The data is not copied.
+ *
+ * @param blob		FDT blob
+ * @param node		node to examine
+ * @param prop_name	name of property to find
+ * @param count		number of array elements
+ * @return pointer to byte array if found, or NULL if the property is not
+ *		found or there is not enough data
+ */
+const u8 *fdtdec_locate_byte_array(const void *blob, int node,
+			     const char *prop_name, int count);
+
+/**
+ * Look up a property in a node which contains a memory region address and
+ * size. Then return a pointer to this address.
+ *
+ * The property must hold one address with a length. This is only tested on
+ * 32-bit machines.
+ *
+ * @param blob		FDT blob
+ * @param node		node to examine
+ * @param prop_name	name of property to find
+ * @param ptrp		returns pointer to region, or NULL if no address
+ * @param size		returns size of region
+ * @return 0 if ok, -1 on error (propery not found)
+ */
+int fdtdec_decode_region(const void *blob, int node,
+		const char *prop_name, void **ptrp, size_t *size);
+
+/* A flash map entry, containing an offset and length */
+struct fmap_entry {
+	uint32_t offset;
+	uint32_t length;
+};
+
+/**
+ * Read a flash entry from the fdt
+ *
+ * @param blob		FDT blob
+ * @param node		Offset of node to read
+ * @param name		Name of node being read
+ * @param entry		Place to put offset and size of this node
+ * @return 0 if ok, -ve on error
+ */
+int fdtdec_read_fmap_entry(const void *blob, int node, const char *name,
+			   struct fmap_entry *entry);
+#endif
diff --git a/qemu/roms/u-boot/include/fis.h b/qemu/roms/u-boot/include/fis.h
new file mode 100644
index 000000000..0d80c1cb5
--- /dev/null
+++ b/qemu/roms/u-boot/include/fis.h
@@ -0,0 +1,142 @@
+/*
+ * Copyright (C) 2008 Freescale Semiconductor, Inc.
+ *		Dave Liu <daveliu@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __FIS_H__
+#define __FIS_H__
+/*
+* Register - Host to Device FIS
+*/
+typedef struct sata_fis_h2d {
+	u8 fis_type;
+	u8 pm_port_c;
+	u8 command;
+	u8 features;
+	u8 lba_low;
+	u8 lba_mid;
+	u8 lba_high;
+	u8 device;
+	u8 lba_low_exp;
+	u8 lba_mid_exp;
+	u8 lba_high_exp;
+	u8 features_exp;
+	u8 sector_count;
+	u8 sector_count_exp;
+	u8 res1;
+	u8 control;
+	u8 res2[4];
+} __attribute__ ((packed)) sata_fis_h2d_t;
+
+/*
+* Register - Host to Device FIS for read/write FPDMA queued
+*/
+typedef struct sata_fis_h2d_ncq {
+	u8 fis_type;
+	u8 pm_port_c;
+	u8 command;
+	u8 sector_count_low;
+	u8 lba_low;
+	u8 lba_mid;
+	u8 lba_high;
+	u8 device;
+	u8 lba_low_exp;
+	u8 lba_mid_exp;
+	u8 lba_high_exp;
+	u8 sector_count_high;
+	u8 tag;
+	u8 res1;
+	u8 res2;
+	u8 control;
+	u8 res3[4];
+} __attribute__ ((packed)) sata_fis_h2d_ncq_t;
+
+/*
+* Register - Device to Host FIS
+*/
+typedef struct sata_fis_d2h {
+	u8 fis_type;
+	u8 pm_port_i;
+	u8 status;
+	u8 error;
+	u8 lba_low;
+	u8 lba_mid;
+	u8 lba_high;
+	u8 device;
+	u8 lba_low_exp;
+	u8 lba_mid_exp;
+	u8 lba_high_exp;
+	u8 res1;
+	u8 sector_count;
+	u8 sector_count_exp;
+	u8 res2[2];
+	u8 res3[4];
+} __attribute__ ((packed)) sata_fis_d2h_t;
+
+/*
+* DMA Setup - Device to Host or Host to Device FIS
+*/
+typedef struct sata_fis_dma_setup {
+	u8 fis_type;
+	u8 pm_port_dir_int_act;
+	u8 res1;
+	u8 res2;
+	u32 dma_buffer_id_low;
+	u32 dma_buffer_id_high;
+	u32 res3;
+	u32 dma_buffer_offset;
+	u32 dma_transfer_count;
+	u32 res4;
+} __attribute__ ((packed)) sata_fis_dma_setup_t;
+
+/*
+* PIO Setup - Device to Host FIS
+*/
+typedef struct sata_fis_pio_setup {
+	u8 fis_type;
+	u8 pm_port_dir_int;
+	u8 status;
+	u8 error;
+	u8 lba_low;
+	u8 lba_mid;
+	u8 lba_high;
+	u8 res1;
+	u8 lba_low_exp;
+	u8 lba_mid_exp;
+	u8 lba_high_exp;
+	u8 res2;
+	u8 sector_count;
+	u8 sector_count_exp;
+	u8 res3;
+	u8 e_status;
+	u16 transfer_count;
+	u16 res4;
+} __attribute__ ((packed)) sata_fis_pio_setup_t;
+
+/*
+* Data - Host to Device or Device to Host FIS
+*/
+typedef struct sata_fis_data {
+	u8 fis_type;
+	u8 pm_port;
+	u8 res1;
+	u8 res2;
+	u32 data[2048];
+} __attribute__ ((packed)) sata_fis_data_t;
+
+/* fis_type - SATA FIS type
+ */
+enum sata_fis_type {
+	SATA_FIS_TYPE_REGISTER_H2D		= 0x27,
+	SATA_FIS_TYPE_REGISTER_D2H		= 0x34,
+	SATA_FIS_TYPE_DMA_ACT_D2H		= 0x39,
+	SATA_FIS_TYPE_DMA_SETUP_BI		= 0x41,
+	SATA_FIS_TYPE_DATA_BI			= 0x46,
+	SATA_FIS_TYPE_BIST_ACT_BI		= 0x58,
+	SATA_FIS_TYPE_PIO_SETUP_D2H		= 0x5F,
+	SATA_FIS_TYPE_SET_DEVICE_BITS_D2H	= 0xA1,
+};
+
+#endif	/* __FIS_H__ */
diff --git a/qemu/roms/u-boot/include/flash.h b/qemu/roms/u-boot/include/flash.h
new file mode 100644
index 000000000..5454c9ea2
--- /dev/null
+++ b/qemu/roms/u-boot/include/flash.h
@@ -0,0 +1,501 @@
+/*
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _FLASH_H_
+#define _FLASH_H_
+
+#ifndef CONFIG_SYS_NO_FLASH
+/*-----------------------------------------------------------------------
+ * FLASH Info: contains chip specific data, per FLASH bank
+ */
+
+typedef struct {
+	ulong	size;			/* total bank size in bytes		*/
+	ushort	sector_count;		/* number of erase units		*/
+	ulong	flash_id;		/* combined device & manufacturer code	*/
+	ulong	start[CONFIG_SYS_MAX_FLASH_SECT];   /* virtual sector start address */
+	uchar	protect[CONFIG_SYS_MAX_FLASH_SECT]; /* sector protection status	*/
+#ifdef CONFIG_SYS_FLASH_CFI
+	uchar	portwidth;		/* the width of the port		*/
+	uchar	chipwidth;		/* the width of the chip		*/
+	ushort	buffer_size;		/* # of bytes in write buffer		*/
+	ulong	erase_blk_tout;		/* maximum block erase timeout		*/
+	ulong	write_tout;		/* maximum write timeout		*/
+	ulong	buffer_write_tout;	/* maximum buffer write timeout		*/
+	ushort	vendor;			/* the primary vendor id		*/
+	ushort	cmd_reset;		/* vendor specific reset command	*/
+	uchar   cmd_erase_sector;	/* vendor specific erase sect. command	*/
+	ushort	interface;		/* used for x8/x16 adjustments		*/
+	ushort	legacy_unlock;		/* support Intel legacy (un)locking	*/
+	ushort	manufacturer_id;	/* manufacturer id			*/
+	ushort	device_id;		/* device id				*/
+	ushort	device_id2;		/* extended device id			*/
+	ushort	ext_addr;		/* extended query table address		*/
+	ushort	cfi_version;		/* cfi version				*/
+	ushort	cfi_offset;		/* offset for cfi query			*/
+	ulong   addr_unlock1;		/* unlock address 1 for AMD flash roms  */
+	ulong   addr_unlock2;		/* unlock address 2 for AMD flash roms  */
+	const char *name;		/* human-readable name	                */
+#endif
+} flash_info_t;
+
+extern flash_info_t flash_info[]; /* info for FLASH chips	*/
+
+typedef unsigned long flash_sect_t;
+
+/*
+ * Values for the width of the port
+ */
+#define FLASH_CFI_8BIT		0x01
+#define FLASH_CFI_16BIT		0x02
+#define FLASH_CFI_32BIT		0x04
+#define FLASH_CFI_64BIT		0x08
+/*
+ * Values for the width of the chip
+ */
+#define FLASH_CFI_BY8		0x01
+#define FLASH_CFI_BY16		0x02
+#define FLASH_CFI_BY32		0x04
+#define FLASH_CFI_BY64		0x08
+/* convert between bit value and numeric value */
+#define CFI_FLASH_SHIFT_WIDTH	3
+/*
+ * Values for the flash device interface
+ */
+#define FLASH_CFI_X8		0x00
+#define FLASH_CFI_X16		0x01
+#define FLASH_CFI_X8X16		0x02
+#define FLASH_CFI_X16X32	0x05
+
+/* convert between bit value and numeric value */
+#define CFI_FLASH_SHIFT_WIDTH	3
+
+/* Prototypes */
+
+extern unsigned long flash_init (void);
+extern void flash_protect_default(void);
+extern void flash_print_info (flash_info_t *);
+extern int flash_erase	(flash_info_t *, int, int);
+extern int flash_sect_erase (ulong addr_first, ulong addr_last);
+extern int flash_sect_protect (int flag, ulong addr_first, ulong addr_last);
+extern int flash_sect_roundb (ulong *addr);
+extern unsigned long flash_sector_size(flash_info_t *info, flash_sect_t sect);
+extern void flash_set_verbose(uint);
+
+/* common/flash.c */
+extern void flash_protect (int flag, ulong from, ulong to, flash_info_t *info);
+extern int flash_write (char *, ulong, ulong);
+extern flash_info_t *addr2info (ulong);
+extern int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt);
+
+/* drivers/mtd/cfi_mtd.c */
+#ifdef CONFIG_FLASH_CFI_MTD
+extern int cfi_mtd_init(void);
+#endif
+
+/* board/?/flash.c */
+#if defined(CONFIG_SYS_FLASH_PROTECTION)
+extern int flash_real_protect(flash_info_t *info, long sector, int prot);
+extern void flash_read_user_serial(flash_info_t * info, void * buffer, int offset, int len);
+extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int offset, int len);
+#endif	/* CONFIG_SYS_FLASH_PROTECTION */
+
+#ifdef CONFIG_FLASH_CFI_LEGACY
+extern ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info);
+extern int jedec_flash_match(flash_info_t *info, ulong base);
+#define CFI_CMDSET_AMD_LEGACY		0xFFF0
+#endif
+
+#if defined(CONFIG_SYS_FLASH_CFI)
+extern flash_info_t *flash_get_info(ulong base);
+#endif
+
+/*-----------------------------------------------------------------------
+ * return codes from flash_write():
+ */
+#define ERR_OK				0
+#define ERR_TIMOUT			1
+#define ERR_NOT_ERASED			2
+#define ERR_PROTECTED			4
+#define ERR_INVAL			8
+#define ERR_ALIGN			16
+#define ERR_UNKNOWN_FLASH_VENDOR	32
+#define ERR_UNKNOWN_FLASH_TYPE		64
+#define ERR_PROG_ERROR			128
+#define ERR_ABORTED			256
+
+/*-----------------------------------------------------------------------
+ * Protection Flags for flash_protect():
+ */
+#define FLAG_PROTECT_SET	0x01
+#define FLAG_PROTECT_CLEAR	0x02
+#define	FLAG_PROTECT_INVALID	0x03
+/*-----------------------------------------------------------------------
+ * Set Environment according to label:
+ */
+#define	FLAG_SETENV		0x80
+
+/*-----------------------------------------------------------------------
+ * Device IDs
+ */
+
+/* Manufacturers inside bank 0 have ids like 0x00xx00xx */
+#define AMD_MANUFACT	0x00010001	/* AMD	   manuf. ID in D23..D16, D7..D0 */
+#define FUJ_MANUFACT	0x00040004	/* FUJITSU manuf. ID in D23..D16, D7..D0 */
+#define ATM_MANUFACT	0x001F001F	/* ATMEL */
+#define STM_MANUFACT	0x00200020	/* STM (Thomson) manuf. ID in D23.. -"- */
+#define SST_MANUFACT	0x00BF00BF	/* SST	   manuf. ID in D23..D16, D7..D0 */
+#define MT_MANUFACT	0x00890089	/* MT	   manuf. ID in D23..D16, D7..D0 */
+#define INTEL_MANUFACT	0x00890089	/* INTEL   manuf. ID in D23..D16, D7..D0 */
+#define INTEL_ALT_MANU	0x00B000B0	/* alternate INTEL namufacturer ID	*/
+#define MX_MANUFACT	0x00C200C2	/* MXIC	   manuf. ID in D23..D16, D7..D0 */
+#define TOSH_MANUFACT	0x00980098	/* TOSHIBA manuf. ID in D23..D16, D7..D0 */
+#define MT2_MANUFACT	0x002C002C	/* alternate MICRON manufacturer ID*/
+#define EXCEL_MANUFACT	0x004A004A	/* Excel Semiconductor			*/
+#define AMIC_MANUFACT	0x00370037	/* AMIC    manuf. ID in D23..D16, D7..D0 */
+#define WINB_MANUFACT	0x00DA00DA	/* Winbond manuf. ID in D23..D16, D7..D0 */
+
+/* Manufacturers inside bank 1 have ids like 0x01xx01xx */
+#define EON_MANUFACT	0x011C011C	/* EON     manuf. ID in D23..D16, D7..D0 */
+
+/* Manufacturers inside bank 2 have ids like 0x02xx02xx */
+
+					/* Micron Technologies (INTEL compat.)	*/
+#define MT_ID_28F400_T	0x44704470	/* 28F400B3 ID ( 4 M, top boot sector)	*/
+#define MT_ID_28F400_B	0x44714471	/* 28F400B3 ID ( 4 M, bottom boot sect) */
+
+#define AMD_ID_LV040B	0x4F		/* 29LV040B ID				*/
+					/* 4 Mbit, 512K x 8,			*/
+					/* 8 64K x 8 uniform sectors		*/
+#define AMD_ID_F033C	0xA3		/* 29LV033C ID				*/
+					/* 32 Mbit, 4Mbits x 8,			*/
+					/* 64 64K x 8 uniform sectors		*/
+#define AMD_ID_F065D	0x93		/* 29LV065D ID				*/
+					/* 64 Mbit, 8Mbits x 8,			*/
+					/* 126 64K x 8 uniform sectors		*/
+#define ATM_ID_LV040	0x13		/* 29LV040B ID				*/
+					/* 4 Mbit, 512K x 8,			*/
+					/* 8 64K x 8 uniform sectors		*/
+#define AMD_ID_F040B	0xA4		/* 29F040B ID				*/
+					/* 4 Mbit, 512K x 8,			*/
+					/* 8 64K x 8 uniform sectors		*/
+#define STM_ID_M29W040B 0xE3		/* M29W040B ID				*/
+					/* 4 Mbit, 512K x 8,			*/
+					/* 8 64K x 8 uniform sectors		*/
+#define AMD_ID_F080B	0xD5		/* 29F080  ID  ( 1 M)			*/
+					/* 8 Mbit, 512K x 16,			*/
+					/* 8 64K x 16 uniform sectors		*/
+#define AMD_ID_F016D	0xAD		/* 29F016  ID  ( 2 M x 8)		*/
+#define AMD_ID_F032B	0x41		/* 29F032  ID  ( 4 M x 8)		*/
+#define AMD_ID_LV116DT	0xC7		/* 29LV116DT   ( 2 M x 8, top boot sect) */
+#define AMD_ID_LV116DB	0x4C		/* 29LV116DB   ( 2 M x 8, bottom boot sect) */
+#define AMD_ID_LV016B	0xc8		/* 29LV016 ID  ( 2 M x 8)		*/
+
+#define AMD_ID_PL160CB	0x22452245	/* 29PL160CB ID (16 M, bottom boot sect */
+
+#define AMD_ID_LV400T	0x22B922B9	/* 29LV400T ID ( 4 M, top boot sector)	*/
+#define AMD_ID_LV400B	0x22BA22BA	/* 29LV400B ID ( 4 M, bottom boot sect) */
+
+#define AMD_ID_LV033C	0xA3		/* 29LV033C ID ( 4 M x 8)		*/
+#define AMD_ID_LV065D	0x93		/* 29LV065D ID ( 8 M x 8)		*/
+
+#define AMD_ID_LV800T	0x22DA22DA	/* 29LV800T ID ( 8 M, top boot sector)	*/
+#define AMD_ID_LV800B	0x225B225B	/* 29LV800B ID ( 8 M, bottom boot sect) */
+
+#define AMD_ID_LV160T	0x22C422C4	/* 29LV160T ID (16 M, top boot sector)	*/
+#define AMD_ID_LV160B	0x22492249	/* 29LV160B ID (16 M, bottom boot sect) */
+
+#define AMD_ID_DL163T	0x22282228	/* 29DL163T ID (16 M, top boot sector)	*/
+#define AMD_ID_DL163B	0x222B222B	/* 29DL163B ID (16 M, bottom boot sect) */
+
+#define AMD_ID_LV320T	0x22F622F6	/* 29LV320T ID (32 M, top boot sector)	*/
+#define MX_ID_LV320T	0x22A722A7	/* 29LV320T by Macronix, AMD compatible */
+#define AMD_ID_LV320B	0x22F922F9	/* 29LV320B ID (32 M, bottom boot sect) */
+#define MX_ID_LV320B	0x22A822A8	/* 29LV320B by Macronix, AMD compatible */
+
+#define AMD_ID_DL322T	0x22552255	/* 29DL322T ID (32 M, top boot sector)	*/
+#define AMD_ID_DL322B	0x22562256	/* 29DL322B ID (32 M, bottom boot sect) */
+#define AMD_ID_DL323T	0x22502250	/* 29DL323T ID (32 M, top boot sector)	*/
+#define AMD_ID_DL323B	0x22532253	/* 29DL323B ID (32 M, bottom boot sect) */
+#define AMD_ID_DL324T	0x225C225C	/* 29DL324T ID (32 M, top boot sector)	*/
+#define AMD_ID_DL324B	0x225F225F	/* 29DL324B ID (32 M, bottom boot sect) */
+
+#define AMD_ID_DL640	0x227E227E	/* 29DL640D ID (64 M, dual boot sectors)*/
+#define AMD_ID_MIRROR	0x227E227E	/* 1st ID word for MirrorBit family */
+#define AMD_ID_DL640G_2 0x22022202	/* 2nd ID word for AM29DL640G  at 0x38 */
+#define AMD_ID_DL640G_3 0x22012201	/* 3rd ID word for AM29DL640G  at 0x3c */
+#define AMD_ID_LV640U_2 0x220C220C	/* 2nd ID word for AM29LV640M  at 0x38 */
+#define AMD_ID_LV640U_3 0x22012201	/* 3rd ID word for AM29LV640M  at 0x3c */
+#define AMD_ID_LV640MT_2 0x22102210	/* 2nd ID word for AM29LV640MT at 0x38 */
+#define AMD_ID_LV640MT_3 0x22012201	/* 3rd ID word for AM29LV640MT at 0x3c */
+#define AMD_ID_LV640MB_2 0x22102210	/* 2nd ID word for AM29LV640MB at 0x38 */
+#define AMD_ID_LV640MB_3 0x22002200	/* 3rd ID word for AM29LV640MB at 0x3c */
+#define AMD_ID_LV128U_2 0x22122212	/* 2nd ID word for AM29LV128M  at 0x38 */
+#define AMD_ID_LV128U_3 0x22002200	/* 3rd ID word for AM29LV128M  at 0x3c */
+#define AMD_ID_LV256U_2 0x22122212	/* 2nd ID word for AM29LV256M  at 0x38 */
+#define AMD_ID_LV256U_3 0x22012201	/* 3rd ID word for AM29LV256M  at 0x3c */
+#define AMD_ID_GL064M_2 0x22132213	/* 2nd ID word for S29GL064M-R6 */
+#define AMD_ID_GL064M_3 0x22012201	/* 3rd ID word for S29GL064M-R6 */
+#define AMD_ID_GL064MT_2 0x22102210	/* 2nd ID word for S29GL064M-R3 (top boot sector) */
+#define AMD_ID_GL064MT_3 0x22012201	/* 3rd ID word for S29GL064M-R3 (top boot sector) */
+#define AMD_ID_GL128N_2	0x22212221	/* 2nd ID word for S29GL128N */
+#define AMD_ID_GL128N_3	0x22012201	/* 3rd ID word for S29GL128N */
+
+
+#define AMD_ID_LV320B_2 0x221A221A	/* 2d ID word for AM29LV320MB at 0x38 */
+#define AMD_ID_LV320B_3 0x22002200	/* 3d ID word for AM29LV320MB at 0x3c */
+
+#define AMD_ID_LV640U	0x22D722D7	/* 29LV640U ID (64 M, uniform sectors)	*/
+#define AMD_ID_LV650U	0x22D722D7	/* 29LV650U ID (64 M, uniform sectors)	*/
+
+#define ATM_ID_BV1614	0x000000C0	/* 49BV1614  ID */
+#define ATM_ID_BV1614A	0x000000C8	/* 49BV1614A ID */
+#define ATM_ID_BV6416	0x000000D6	/* 49BV6416  ID */
+
+#define FUJI_ID_29F800BA  0x22582258	/* MBM29F800BA ID  (8M) */
+#define FUJI_ID_29F800TA  0x22D622D6	/* MBM29F800TA ID  (8M) */
+#define FUJI_ID_29LV650UE 0x22d722d7	/* MBM29LV650UE/651UE ID (8M = 128 x 32kWord) */
+
+#define SST_ID_xF200A	0x27892789	/* 39xF200A ID ( 2M = 128K x 16 )	*/
+#define SST_ID_xF400A	0x27802780	/* 39xF400A ID ( 4M = 256K x 16 )	*/
+#define SST_ID_xF800A	0x27812781	/* 39xF800A ID ( 8M = 512K x 16 )	*/
+#define SST_ID_xF160A	0x27822782	/* 39xF800A ID (16M =	1M x 16 )	*/
+#define SST_ID_xF1601	0x234B234B	/* 39xF1601 ID (16M =	1M x 16 )	*/
+#define SST_ID_xF1602	0x234A234A	/* 39xF1602 ID (16M =	1M x 16 )	*/
+#define SST_ID_xF3201	0x235B235B	/* 39xF3201 ID (32M =	2M x 16 )	*/
+#define SST_ID_xF3202	0x235A235A	/* 39xF3202 ID (32M =	2M x 16 )	*/
+#define SST_ID_xF6401	0x236B236B	/* 39xF6401 ID (64M =	4M x 16 )	*/
+#define SST_ID_xF6402	0x236A236A	/* 39xF6402 ID (64M =	4M x 16 )	*/
+#define SST_ID_xF020	0xBFD6BFD6	/* 39xF020 ID (256KB = 2Mbit x 8)	*/
+#define SST_ID_xF040	0xBFD7BFD7	/* 39xF040 ID (512KB = 4Mbit x 8)	*/
+
+#define STM_ID_F040B	0xE2		/* M29F040B ID ( 4M = 512K x 8	)	*/
+					/* 8 64K x 8 uniform sectors		*/
+
+#define STM_ID_x800AB	0x005B005B	/* M29W800AB ID (8M = 512K x 16 )	*/
+#define STM_ID_29W320DT 0x22CA22CA	/* M29W320DT ID (32 M, top boot sector) */
+#define STM_ID_29W320DB 0x22CB22CB	/* M29W320DB ID (32 M, bottom boot sect)	*/
+#define STM_ID_29W320ET 0x22562256	/* M29W320ET ID (32 M, top boot sector) */
+#define STM_ID_29W320EB 0x22572257	/* M29W320EB ID (32 M, bottom boot sect)*/
+#define STM_ID_29W040B	0x00E300E3	/* M29W040B ID (4M = 512K x 8)	*/
+#define FLASH_PSD4256GV 0x00E9		/* PSD4256 Flash and CPLD combination	*/
+
+#define INTEL_ID_28F016S    0x66a066a0	/* 28F016S[VS] ID (16M = 512k x 16)	*/
+#define INTEL_ID_28F800B3T  0x88928892	/*  8M = 512K x 16 top boot sector	*/
+#define INTEL_ID_28F800B3B  0x88938893	/*  8M = 512K x 16 bottom boot sector	*/
+#define INTEL_ID_28F160B3T  0x88908890	/*  16M = 1M x 16 top boot sector	*/
+#define INTEL_ID_28F160B3B  0x88918891	/*  16M = 1M x 16 bottom boot sector	*/
+#define INTEL_ID_28F320B3T  0x88968896	/*  32M = 2M x 16 top boot sector	*/
+#define INTEL_ID_28F320B3B  0x88978897	/*  32M = 2M x 16 bottom boot sector	*/
+#define INTEL_ID_28F640B3T  0x88988898	/*  64M = 4M x 16 top boot sector	*/
+#define INTEL_ID_28F640B3B  0x88998899	/*  64M = 4M x 16 bottom boot sector	*/
+#define INTEL_ID_28F160F3B  0x88F488F4	/*  16M = 1M x 16 bottom boot sector	*/
+
+#define INTEL_ID_28F800C3T  0x88C088C0	/*  8M = 512K x 16 top boot sector	*/
+#define INTEL_ID_28F800C3B  0x88C188C1	/*  8M = 512K x 16 bottom boot sector	*/
+#define INTEL_ID_28F160C3T  0x88C288C2	/*  16M = 1M x 16 top boot sector	*/
+#define INTEL_ID_28F160C3B  0x88C388C3	/*  16M = 1M x 16 bottom boot sector	*/
+#define INTEL_ID_28F320C3T  0x88C488C4	/*  32M = 2M x 16 top boot sector	*/
+#define INTEL_ID_28F320C3B  0x88C588C5	/*  32M = 2M x 16 bottom boot sector	*/
+#define INTEL_ID_28F640C3T  0x88CC88CC	/*  64M = 4M x 16 top boot sector	*/
+#define INTEL_ID_28F640C3B  0x88CD88CD	/*  64M = 4M x 16 bottom boot sector	*/
+
+#define INTEL_ID_28F128J3   0x89188918	/*  16M = 8M x 16 x 128 */
+#define INTEL_ID_28F320J5   0x00140014	/*  32M = 128K x  32	*/
+#define INTEL_ID_28F640J5   0x00150015	/*  64M = 128K x  64	*/
+#define INTEL_ID_28F320J3A  0x00160016	/*  32M = 128K x  32	*/
+#define INTEL_ID_28F640J3A  0x00170017	/*  64M = 128K x  64	*/
+#define INTEL_ID_28F128J3A  0x00180018	/* 128M = 128K x 128	*/
+#define INTEL_ID_28F256J3A  0x001D001D	/* 256M = 128K x 256	*/
+#define INTEL_ID_28F256L18T 0x880D880D	/* 256M = 128K x 255 + 32k x 4 */
+#define INTEL_ID_28F64K3    0x88018801	/*  64M =  32K x 255 + 32k x 4 */
+#define INTEL_ID_28F128K3   0x88028802	/* 128M =  64K x 255 + 32k x 4 */
+#define INTEL_ID_28F256K3   0x88038803	/* 256M = 128K x 255 + 32k x 4 */
+#define INTEL_ID_28F64P30T  0x88178817	/*  64M =  32K x 255 + 32k x 4 */
+#define INTEL_ID_28F64P30B  0x881A881A	/*  64M =  32K x 255 + 32k x 4 */
+#define INTEL_ID_28F128P30T 0x88188818	/* 128M =  64K x 255 + 32k x 4 */
+#define INTEL_ID_28F128P30B 0x881B881B	/* 128M =  64K x 255 + 32k x 4 */
+#define INTEL_ID_28F256P30T 0x88198819	/* 256M = 128K x 255 + 32k x 4 */
+#define INTEL_ID_28F256P30B 0x881C881C	/* 256M = 128K x 255 + 32k x 4 */
+
+#define INTEL_ID_28F160S3   0x00D000D0	/*  16M = 512K x  32 (64kB x 32)	*/
+#define INTEL_ID_28F320S3   0x00D400D4	/*  32M = 512K x  64 (64kB x 64)	*/
+
+/* Note that the Sharp 28F016SC is compatible with the Intel E28F016SC */
+#define SHARP_ID_28F016SCL  0xAAAAAAAA	/* LH28F016SCT-L95 2Mx8, 32 64k blocks	*/
+#define SHARP_ID_28F016SCZ  0xA0A0A0A0	/* LH28F016SCT-Z4  2Mx8, 32 64k blocks	*/
+#define SHARP_ID_28F008SC   0xA6A6A6A6	/* LH28F008SCT-L12 1Mx8, 16 64k blocks	*/
+					/* LH28F008SCR-L85 1Mx8, 16 64k blocks	*/
+
+#define TOSH_ID_FVT160	0xC2		/* TC58FVT160 ID (16 M, top )		*/
+#define TOSH_ID_FVB160	0x43		/* TC58FVT160 ID (16 M, bottom )	*/
+#define NUMONYX_256MBIT	0x8922		/* Numonyx P33/30 256MBit 65nm	*/
+
+/*-----------------------------------------------------------------------
+ * Internal FLASH identification codes
+ *
+ * Be careful when adding new type! Odd numbers are "bottom boot sector" types!
+ */
+
+#define FLASH_AM040	0x0001		/* AMD Am29F040B, Am29LV040B		*/
+					/* Bright Micro BM29F040		*/
+					/* Fujitsu MBM29F040A			*/
+					/* STM M29W040B				*/
+					/* SGS Thomson M29F040B			*/
+					/* 8 64K x 8 uniform sectors		*/
+#define FLASH_AM400T	0x0002		/* AMD AM29LV400			*/
+#define FLASH_AM400B	0x0003
+#define FLASH_AM800T	0x0004		/* AMD AM29LV800			*/
+#define FLASH_AM800B	0x0005
+#define FLASH_AM116DT	0x0026		/* AMD AM29LV116DT (2Mx8bit) */
+#define FLASH_AM116DB	0x0027		/* AMD AM29LV116DB (2Mx8bit) */
+#define FLASH_AM160T	0x0006		/* AMD AM29LV160			*/
+#define FLASH_AM160LV	0x0046		/* AMD29LV160DB (2M = 2Mx8bit ) */
+#define FLASH_AM160B	0x0007
+#define FLASH_AM320T	0x0008		/* AMD AM29LV320			*/
+#define FLASH_AM320B	0x0009
+
+#define FLASH_AM080	0x000A		/* AMD Am29F080B			*/
+					/* 16 64K x 8 uniform sectors		*/
+
+#define FLASH_AMDL322T	0x0010		/* AMD AM29DL322			*/
+#define FLASH_AMDL322B	0x0011
+#define FLASH_AMDL323T	0x0012		/* AMD AM29DL323			*/
+#define FLASH_AMDL323B	0x0013
+#define FLASH_AMDL324T	0x0014		/* AMD AM29DL324			*/
+#define FLASH_AMDL324B	0x0015
+
+#define FLASH_AMDLV033C 0x0018
+#define FLASH_AMDLV065D 0x001A
+
+#define FLASH_AMDL640	0x0016		/* AMD AM29DL640D			*/
+#define FLASH_AMD016	0x0018		/* AMD AM29F016D			*/
+#define FLASH_AMDL640MB 0x0019		/* AMD AM29LV640MB (64M, bottom boot sect)*/
+#define FLASH_AMDL640MT 0x001A		/* AMD AM29LV640MT (64M, top boot sect) */
+
+#define FLASH_SST200A	0x0040		/* SST 39xF200A ID (  2M = 128K x 16 )	*/
+#define FLASH_SST400A	0x0042		/* SST 39xF400A ID (  4M = 256K x 16 )	*/
+#define FLASH_SST800A	0x0044		/* SST 39xF800A ID (  8M = 512K x 16 )	*/
+#define FLASH_SST160A	0x0046		/* SST 39xF160A ID ( 16M =   1M x 16 )	*/
+#define FLASH_SST320	0x0048		/* SST 39xF160A ID ( 16M =   1M x 16 )	*/
+#define FLASH_SST640	0x004A		/* SST 39xF160A ID ( 16M =   1M x 16 )	*/
+#define FLASH_SST020	0x0024		/* SST 39xF020 ID (256KB = 2Mbit x 8 )	*/
+#define FLASH_SST040	0x000E		/* SST 39xF040 ID (512KB = 4Mbit x 8 )	*/
+
+#define FLASH_STM800AB	0x0051		/* STM M29WF800AB  (  8M = 512K x 16 )	*/
+#define FLASH_STMW320DT 0x0052		/* STM M29W320DT   (32 M, top boot sector)	*/
+#define FLASH_STMW320DB 0x0053		/* STM M29W320DB   (32 M, bottom boot sect)*/
+#define FLASH_STM320DB	0x00CB		/* STM M29W320DB (4M = 64K x 64, bottom)*/
+#define FLASH_STM800DT	0x00D7		/* STM M29W800DT (1M = 64K x 16, top)	*/
+#define FLASH_STM800DB	0x005B		/* STM M29W800DB (1M = 64K x 16, bottom)*/
+
+#define FLASH_28F400_T	0x0062		/* MT  28F400B3 ID (  4M = 256K x 16 )	*/
+#define FLASH_28F400_B	0x0063		/* MT  28F400B3 ID (  4M = 256K x 16 )	*/
+
+#define FLASH_INTEL800T 0x0074		/* INTEL 28F800B3T (  8M = 512K x 16 )	*/
+#define FLASH_INTEL800B 0x0075		/* INTEL 28F800B3B (  8M = 512K x 16 )	*/
+#define FLASH_INTEL160T 0x0076		/* INTEL 28F160B3T ( 16M =  1 M x 16 )	*/
+#define FLASH_INTEL160B 0x0077		/* INTEL 28F160B3B ( 16M =  1 M x 16 )	*/
+#define FLASH_INTEL320T 0x0078		/* INTEL 28F320B3T ( 32M =  2 M x 16 )	*/
+#define FLASH_INTEL320B 0x0079		/* INTEL 28F320B3B ( 32M =  2 M x 16 )	*/
+#define FLASH_INTEL640T 0x007A		/* INTEL 28F320B3T ( 64M =  4 M x 16 )	*/
+#define FLASH_INTEL640B 0x007B		/* INTEL 28F320B3B ( 64M =  4 M x 16 )	*/
+
+#define FLASH_28F008S5	0x0080		/* Intel 28F008S5  (  1M =  64K x 16 )	*/
+#define FLASH_28F016SV	0x0081		/* Intel 28F016SV  ( 16M = 512k x 32 )	*/
+#define FLASH_28F800_B	0x0083		/* Intel E28F800B  (  1M = ? )		*/
+#define FLASH_AM29F800B 0x0084		/* AMD Am29F800BB  (  1M = ? )		*/
+#define FLASH_28F320J5	0x0085		/* Intel 28F320J5  (  4M = 128K x 32 )	*/
+#define FLASH_28F160S3	0x0086		/* Intel 28F160S3  ( 16M = 512K x 32 )	*/
+#define FLASH_28F320S3	0x0088		/* Intel 28F320S3  ( 32M = 512K x 64 )	*/
+#define FLASH_AM640U	0x0090		/* AMD Am29LV640U  ( 64M = 4M x 16 )	*/
+#define FLASH_AM033C	0x0091		/* AMD AM29LV033   ( 32M = 4M x 8 )	*/
+#define FLASH_LH28F016SCT 0x0092	/* Sharp 28F016SCT ( 8 Meg Flash SIMM ) */
+#define FLASH_28F160F3B 0x0093		/* Intel 28F160F3B ( 16M = 1M x 16 )	*/
+#define FLASH_AM065D	0x0093
+
+#define FLASH_28F640J5	0x0099		/* INTEL 28F640J5  ( 64M = 128K x  64)	*/
+
+#define FLASH_28F800C3T 0x009A		/* Intel 28F800C3T (  8M = 512K x 16 )	*/
+#define FLASH_28F800C3B 0x009B		/* Intel 28F800C3B (  8M = 512K x 16 )	*/
+#define FLASH_28F160C3T 0x009C		/* Intel 28F160C3T ( 16M = 1M x 16 )	*/
+#define FLASH_28F160C3B 0x009D		/* Intel 28F160C3B ( 16M = 1M x 16 )	*/
+#define FLASH_28F320C3T 0x009E		/* Intel 28F320C3T ( 32M = 2M x 16 )	*/
+#define FLASH_28F320C3B 0x009F		/* Intel 28F320C3B ( 32M = 2M x 16 )	*/
+#define FLASH_28F640C3T 0x00A0		/* Intel 28F640C3T ( 64M = 4M x 16 )	*/
+#define FLASH_28F640C3B 0x00A1		/* Intel 28F640C3B ( 64M = 4M x 16 )	*/
+#define FLASH_AMLV320U	0x00A2		/* AMD 29LV320M	   ( 32M = 2M x 16 )	*/
+
+#define FLASH_AM033	0x00A3		/* AMD AmL033C90V1   (32M = 4M x 8)	*/
+#define FLASH_AM065	0x0093		/* AMD AmL065DU12RI  (64M = 8M x 8)	*/
+#define FLASH_AT040	0x00A5		/* Amtel AT49LV040   (4M = 512K x 8)	*/
+
+#define FLASH_AMLV640U	0x00A4		/* AMD 29LV640M	   ( 64M = 4M x 16 )	*/
+#define FLASH_AMLV128U	0x00A6		/* AMD 29LV128M	   ( 128M = 8M x 16 )	*/
+#define FLASH_AMLV320B	0x00A7		/* AMD 29LV320MB   ( 32M = 2M x 16 )	*/
+#define FLASH_AMLV320T	0x00A8		/* AMD 29LV320MT   ( 32M = 2M x 16 )	*/
+#define FLASH_AMLV256U	0x00AA		/* AMD 29LV256M	   ( 256M = 16M x 16 )	*/
+#define FLASH_MXLV320B	0x00AB		/* MX  29LV320MB   ( 32M = 2M x 16 )	*/
+#define FLASH_MXLV320T	0x00AC		/* MX  29LV320MT   ( 32M = 2M x 16 )	*/
+#define FLASH_28F256L18T 0x00B0		/* Intel 28F256L18T 256M = 128K x 255 + 32k x 4 */
+#define FLASH_AMDL163T	0x00B2		/* AMD AM29DL163T (2M x 16 )			*/
+#define FLASH_AMDL163B	0x00B3
+#define FLASH_28F64K3	0x00B4		/* Intel 28F64K3   (  64M)		*/
+#define FLASH_28F128K3	0x00B6		/* Intel 28F128K3  ( 128M = 8M x 16 )	*/
+#define FLASH_28F256K3	0x00B8		/* Intel 28F256K3  ( 256M = 16M x 16 )	*/
+
+#define FLASH_28F320J3A 0x00C0		/* INTEL 28F320J3A ( 32M = 128K x  32)	*/
+#define FLASH_28F640J3A 0x00C2		/* INTEL 28F640J3A ( 64M = 128K x  64)	*/
+#define FLASH_28F128J3A 0x00C4		/* INTEL 28F128J3A (128M = 128K x 128)	*/
+#define FLASH_28F256J3A 0x00C6		/* INTEL 28F256J3A (256M = 128K x 256)	*/
+
+#define FLASH_FUJLV650	0x00D0		/* Fujitsu MBM 29LV650UE/651UE		*/
+#define FLASH_MT28S4M16LC 0x00E1	/* Micron MT28S4M16LC			*/
+#define FLASH_S29GL064M 0x00F0		/* Spansion S29GL064M-R6		*/
+#define FLASH_S29GL128N 0x00F1		/* Spansion S29GL128N			*/
+
+#define FLASH_UNKNOWN	0xFFFF		/* unknown flash type			*/
+
+
+/* manufacturer offsets
+ */
+#define FLASH_MAN_AMD	0x00000000	/* AMD					*/
+#define FLASH_MAN_FUJ	0x00010000	/* Fujitsu				*/
+#define FLASH_MAN_BM	0x00020000	/* Bright Microelectronics		*/
+#define FLASH_MAN_MX	0x00030000	/* MXIC					*/
+#define FLASH_MAN_STM	0x00040000
+#define FLASH_MAN_TOSH	0x00050000	/* Toshiba				*/
+#define FLASH_MAN_EXCEL 0x00060000	/* Excel Semiconductor			*/
+#define FLASH_MAN_SST	0x00100000
+#define FLASH_MAN_INTEL 0x00300000
+#define FLASH_MAN_MT	0x00400000
+#define FLASH_MAN_SHARP 0x00500000
+#define FLASH_MAN_ATM	0x00600000
+#define FLASH_MAN_CFI	0x01000000
+
+
+#define FLASH_TYPEMASK	0x0000FFFF	/* extract FLASH type	information	*/
+#define FLASH_VENDMASK	0xFFFF0000	/* extract FLASH vendor information	*/
+
+#define FLASH_AMD_COMP	0x000FFFFF	/* Up to this ID, FLASH is compatible	*/
+					/* with AMD, Fujitsu and SST		*/
+					/* (JEDEC standard commands ?)		*/
+
+#define FLASH_BTYPE	0x0001		/* mask for bottom boot sector type	*/
+
+/*-----------------------------------------------------------------------
+ * Timeout constants:
+ *
+ * We can't find any specifications for maximum chip erase times,
+ * so these values are guestimates.
+ */
+#define FLASH_ERASE_TIMEOUT	120000	/* timeout for erasing in ms		*/
+#define FLASH_WRITE_TIMEOUT	500	/* timeout for writes  in ms		*/
+
+#endif /* !CONFIG_SYS_NO_FLASH */
+
+#endif /* _FLASH_H_ */
diff --git a/qemu/roms/u-boot/include/fm_eth.h b/qemu/roms/u-boot/include/fm_eth.h
new file mode 100644
index 000000000..98edfcf4a
--- /dev/null
+++ b/qemu/roms/u-boot/include/fm_eth.h
@@ -0,0 +1,176 @@
+/*
+ * Copyright 2009-2012 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __FM_ETH_H__
+#define __FM_ETH_H__
+
+#include <common.h>
+#include <asm/types.h>
+#include <asm/fsl_enet.h>
+
+enum fm_port {
+	FM1_DTSEC1,
+	FM1_DTSEC2,
+	FM1_DTSEC3,
+	FM1_DTSEC4,
+	FM1_DTSEC5,
+	FM1_DTSEC6,
+	FM1_DTSEC9,
+	FM1_DTSEC10,
+	FM1_10GEC1,
+	FM1_10GEC2,
+	FM1_10GEC3,
+	FM1_10GEC4,
+	FM2_DTSEC1,
+	FM2_DTSEC2,
+	FM2_DTSEC3,
+	FM2_DTSEC4,
+	FM2_DTSEC5,
+	FM2_DTSEC6,
+	FM2_DTSEC9,
+	FM2_DTSEC10,
+	FM2_10GEC1,
+	FM2_10GEC2,
+	NUM_FM_PORTS,
+};
+
+enum fm_eth_type {
+	FM_ETH_1G_E,
+	FM_ETH_10G_E,
+};
+
+#ifdef CONFIG_SYS_FMAN_V3
+#define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR	(CONFIG_SYS_FSL_FM1_ADDR + 0xfc000)
+#define CONFIG_SYS_FM1_TGEC_MDIO_ADDR	(CONFIG_SYS_FSL_FM1_ADDR + 0xfd000)
+#define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR	(CONFIG_SYS_FSL_FM2_ADDR + 0xfc000)
+#define CONFIG_SYS_FM2_TGEC_MDIO_ADDR	(CONFIG_SYS_FSL_FM2_ADDR + 0xfd000)
+#else
+#define CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR	(CONFIG_SYS_FSL_FM1_ADDR + 0xe1120)
+#define CONFIG_SYS_FM1_TGEC_MDIO_ADDR	(CONFIG_SYS_FSL_FM1_ADDR + 0xf1000)
+#endif
+
+#define DEFAULT_FM_MDIO_NAME "FSL_MDIO0"
+#define DEFAULT_FM_TGEC_MDIO_NAME "FM_TGEC_MDIO"
+
+/* Fman ethernet info struct */
+#define FM_ETH_INFO_INITIALIZER(idx, pregs) \
+	.fm		= idx,						\
+	.phy_regs	= (void *)pregs,				\
+	.enet_if	= PHY_INTERFACE_MODE_NONE,			\
+
+#ifdef CONFIG_SYS_FMAN_V3
+#define FM_DTSEC_INFO_INITIALIZER(idx, n) \
+{									\
+	FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_DTSEC_MDIO_ADDR)	\
+	.index		= idx,						\
+	.num		= n - 1,					\
+	.type		= FM_ETH_1G_E,					\
+	.port		= FM##idx##_DTSEC##n,				\
+	.rx_port_id	= RX_PORT_1G_BASE + n - 1,			\
+	.tx_port_id	= TX_PORT_1G_BASE + n - 1,			\
+	.compat_offset	= CONFIG_SYS_FSL_FM##idx##_OFFSET +		\
+				offsetof(struct ccsr_fman, memac[n-1]),\
+}
+
+#define FM_TGEC_INFO_INITIALIZER(idx, n) \
+{									\
+	FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM2_TGEC_MDIO_ADDR)	\
+	.index		= idx,						\
+	.num		= n - 1,					\
+	.type		= FM_ETH_10G_E,					\
+	.port		= FM##idx##_10GEC##n,				\
+	.rx_port_id	= RX_PORT_10G_BASE + n - 1,			\
+	.tx_port_id	= TX_PORT_10G_BASE + n - 1,			\
+	.compat_offset	= CONFIG_SYS_FSL_FM##idx##_OFFSET +		\
+				offsetof(struct ccsr_fman, memac[n-1+8]),\
+}
+
+#if (CONFIG_SYS_NUM_FM1_10GEC >= 3)
+#define FM_TGEC_INFO_INITIALIZER2(idx, n) \
+{									\
+	FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR)	\
+	.index		= idx,						\
+	.num		= n - 1,					\
+	.type		= FM_ETH_10G_E,					\
+	.port		= FM##idx##_10GEC##n,				\
+	.rx_port_id	= RX_PORT_10G_BASE2 + n - 3,			\
+	.tx_port_id	= TX_PORT_10G_BASE2 + n - 3,			\
+	.compat_offset	= CONFIG_SYS_FSL_FM##idx##_OFFSET +		\
+				offsetof(struct ccsr_fman, memac[n-1-2]),\
+}
+#endif
+
+#else
+#define FM_DTSEC_INFO_INITIALIZER(idx, n) \
+{									\
+	FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR)	\
+	.index		= idx,						\
+	.num		= n - 1,					\
+	.type		= FM_ETH_1G_E,					\
+	.port		= FM##idx##_DTSEC##n,				\
+	.rx_port_id	= RX_PORT_1G_BASE + n - 1,			\
+	.tx_port_id	= TX_PORT_1G_BASE + n - 1,			\
+	.compat_offset	= CONFIG_SYS_FSL_FM##idx##_OFFSET +		\
+				offsetof(struct ccsr_fman, mac_1g[n-1]),\
+}
+
+#define FM_TGEC_INFO_INITIALIZER(idx, n) \
+{									\
+	FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR)	\
+	.index		= idx,						\
+	.num		= n - 1,					\
+	.type		= FM_ETH_10G_E,					\
+	.port		= FM##idx##_10GEC##n,				\
+	.rx_port_id	= RX_PORT_10G_BASE + n - 1,			\
+	.tx_port_id	= TX_PORT_10G_BASE + n - 1,			\
+	.compat_offset	= CONFIG_SYS_FSL_FM##idx##_OFFSET +		\
+				offsetof(struct ccsr_fman, mac_10g[n-1]),\
+}
+#endif
+struct fm_eth_info {
+	u8 enabled;
+	u8 fm;
+	u8 num;
+	u8 phy_addr;
+	int index;
+	u16 rx_port_id;
+	u16 tx_port_id;
+	enum fm_port port;
+	enum fm_eth_type type;
+	void *phy_regs;
+	phy_interface_t enet_if;
+	u32 compat_offset;
+	struct mii_dev *bus;
+};
+
+struct tgec_mdio_info {
+	struct tgec_mdio_controller *regs;
+	char *name;
+};
+
+struct memac_mdio_info {
+	struct memac_mdio_controller *regs;
+	char *name;
+};
+
+int fm_tgec_mdio_init(bd_t *bis, struct tgec_mdio_info *info);
+int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info *info);
+
+int fm_standard_init(bd_t *bis);
+void fman_enet_init(void);
+void fdt_fixup_fman_ethernet(void *fdt);
+phy_interface_t fm_info_get_enet_if(enum fm_port port);
+void fm_info_set_phy_address(enum fm_port port, int address);
+int fm_info_get_phy_address(enum fm_port port);
+void fm_info_set_mdio(enum fm_port port, struct mii_dev *bus);
+void fm_disable_port(enum fm_port port);
+void fm_enable_port(enum fm_port port);
+void set_sgmii_phy(struct mii_dev *bus, enum fm_port base_port,
+		unsigned int port_num, int phy_base_addr);
+int is_qsgmii_riser_card(struct mii_dev *bus, int phy_base_addr,
+		unsigned int port_num, unsigned regnum);
+
+#endif
diff --git a/qemu/roms/u-boot/include/fpga.h b/qemu/roms/u-boot/include/fpga.h
new file mode 100644
index 000000000..15e603a16
--- /dev/null
+++ b/qemu/roms/u-boot/include/fpga.h
@@ -0,0 +1,50 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/types.h>	       /* for ulong typedef */
+
+#ifndef _FPGA_H_
+#define _FPGA_H_
+
+#ifndef CONFIG_MAX_FPGA_DEVICES
+#define CONFIG_MAX_FPGA_DEVICES		5
+#endif
+
+/* fpga_xxxx function return value definitions */
+#define FPGA_SUCCESS		0
+#define FPGA_FAIL		-1
+
+/* device numbers must be non-negative */
+#define FPGA_INVALID_DEVICE	-1
+
+/* root data type defintions */
+typedef enum {			/* typedef fpga_type */
+	fpga_min_type,		/* range check value */
+	fpga_xilinx,		/* Xilinx Family) */
+	fpga_altera,		/* unimplemented */
+	fpga_lattice,		/* Lattice family */
+	fpga_undefined		/* invalid range check value */
+} fpga_type;			/* end, typedef fpga_type */
+
+typedef struct {		/* typedef fpga_desc */
+	fpga_type devtype;	/* switch value to select sub-functions */
+	void *devdesc;		/* real device descriptor */
+} fpga_desc;			/* end, typedef fpga_desc */
+
+
+/* root function definitions */
+extern void fpga_init(void);
+extern int fpga_add(fpga_type devtype, void *desc);
+extern int fpga_count(void);
+extern int fpga_load(int devnum, const void *buf, size_t bsize);
+extern int fpga_loadbitstream(int devnum, char *fpgadata, size_t size);
+extern int fpga_dump(int devnum, const void *buf, size_t bsize);
+extern int fpga_info(int devnum);
+extern const fpga_desc *const fpga_validate(int devnum, const void *buf,
+					    size_t bsize, char *fn);
+
+#endif	/* _FPGA_H_ */
diff --git a/qemu/roms/u-boot/include/fs.h b/qemu/roms/u-boot/include/fs.h
new file mode 100644
index 000000000..26de0539f
--- /dev/null
+++ b/qemu/roms/u-boot/include/fs.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef _FS_H
+#define _FS_H
+
+#include <common.h>
+
+#define FS_TYPE_ANY	0
+#define FS_TYPE_FAT	1
+#define FS_TYPE_EXT	2
+#define FS_TYPE_SANDBOX	3
+
+/*
+ * Tell the fs layer which block device an partition to use for future
+ * commands. This also internally identifies the filesystem that is present
+ * within the partition. The identification process may be limited to a
+ * specific filesystem type by passing FS_* in the fstype parameter.
+ *
+ * Returns 0 on success.
+ * Returns non-zero if there is an error accessing the disk or partition, or
+ * no known filesystem type could be recognized on it.
+ */
+int fs_set_blk_dev(const char *ifname, const char *dev_part_str, int fstype);
+
+/*
+ * Print the list of files on the partition previously set by fs_set_blk_dev(),
+ * in directory "dirname".
+ *
+ * Returns 0 on success. Returns non-zero on error.
+ */
+int fs_ls(const char *dirname);
+
+/*
+ * Determine whether a file exists
+ *
+ * Returns 1 if the file exists, 0 if it doesn't exist.
+ */
+int fs_exists(const char *filename);
+
+/*
+ * Read file "filename" from the partition previously set by fs_set_blk_dev(),
+ * to address "addr", starting at byte offset "offset", and reading "len"
+ * bytes. "offset" may be 0 to read from the start of the file. "len" may be
+ * 0 to read the entire file. Note that not all filesystem types support
+ * either/both offset!=0 or len!=0.
+ *
+ * Returns number of bytes read on success. Returns <= 0 on error.
+ */
+int fs_read(const char *filename, ulong addr, int offset, int len);
+
+/*
+ * Write file "filename" to the partition previously set by fs_set_blk_dev(),
+ * from address "addr", starting at byte offset "offset", and writing "len"
+ * bytes. "offset" may be 0 to write to the start of the file. Note that not
+ * all filesystem types support offset!=0.
+ *
+ * Returns number of bytes read on success. Returns <= 0 on error.
+ */
+int fs_write(const char *filename, ulong addr, int offset, int len);
+
+/*
+ * Common implementation for various filesystem commands, optionally limited
+ * to a specific filesystem type via the fstype parameter.
+ */
+int do_load(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
+		int fstype);
+int do_ls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
+		int fstype);
+int file_exists(const char *dev_type, const char *dev_part, const char *file,
+		int fstype);
+int do_save(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
+		int fstype);
+
+#endif /* _FS_H */
diff --git a/qemu/roms/u-boot/include/fsl_ddr.h b/qemu/roms/u-boot/include/fsl_ddr.h
new file mode 100644
index 000000000..5c49b229d
--- /dev/null
+++ b/qemu/roms/u-boot/include/fsl_ddr.h
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2008-2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#ifndef FSL_DDR_MAIN_H
+#define FSL_DDR_MAIN_H
+
+#include <fsl_ddrc_version.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+
+#include <common_timing_params.h>
+
+#ifdef CONFIG_SYS_FSL_DDR_LE
+#define ddr_in32(a)	in_le32(a)
+#define ddr_out32(a, v)	out_le32(a, v)
+#else
+#define ddr_in32(a)	in_be32(a)
+#define ddr_out32(a, v)	out_be32(a, v)
+#endif
+
+#define _DDR_ADDR CONFIG_SYS_FSL_DDR_ADDR
+
+u32 fsl_ddr_get_version(void);
+
+#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
+/*
+ * Bind the main DDR setup driver's generic names
+ * to this specific DDR technology.
+ */
+static __inline__ int
+compute_dimm_parameters(const generic_spd_eeprom_t *spd,
+			dimm_params_t *pdimm,
+			unsigned int dimm_number)
+{
+	return ddr_compute_dimm_parameters(spd, pdimm, dimm_number);
+}
+#endif
+
+/*
+ * Data Structures
+ *
+ * All data structures have to be on the stack
+ */
+#define CONFIG_SYS_NUM_DDR_CTLRS CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_SYS_DIMM_SLOTS_PER_CTLR CONFIG_DIMM_SLOTS_PER_CTLR
+
+typedef struct {
+	generic_spd_eeprom_t
+	   spd_installed_dimms[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR];
+	struct dimm_params_s
+	   dimm_params[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR];
+	memctl_options_t memctl_opts[CONFIG_SYS_NUM_DDR_CTLRS];
+	common_timing_params_t common_timing_params[CONFIG_SYS_NUM_DDR_CTLRS];
+	fsl_ddr_cfg_regs_t fsl_ddr_config_reg[CONFIG_SYS_NUM_DDR_CTLRS];
+} fsl_ddr_info_t;
+
+/* Compute steps */
+#define STEP_GET_SPD                 (1 << 0)
+#define STEP_COMPUTE_DIMM_PARMS      (1 << 1)
+#define STEP_COMPUTE_COMMON_PARMS    (1 << 2)
+#define STEP_GATHER_OPTS             (1 << 3)
+#define STEP_ASSIGN_ADDRESSES        (1 << 4)
+#define STEP_COMPUTE_REGS            (1 << 5)
+#define STEP_PROGRAM_REGS            (1 << 6)
+#define STEP_ALL                     0xFFF
+
+unsigned long long
+fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
+				       unsigned int size_only);
+
+const char *step_to_string(unsigned int step);
+
+unsigned int compute_fsl_memctl_config_regs(const memctl_options_t *popts,
+			       fsl_ddr_cfg_regs_t *ddr,
+			       const common_timing_params_t *common_dimm,
+			       const dimm_params_t *dimm_parameters,
+			       unsigned int dbw_capacity_adjust,
+			       unsigned int size_only);
+unsigned int compute_lowest_common_dimm_parameters(
+				const dimm_params_t *dimm_params,
+				common_timing_params_t *outpdimm,
+				unsigned int number_of_dimms);
+unsigned int populate_memctl_options(int all_dimms_registered,
+				memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num);
+void check_interleaving_options(fsl_ddr_info_t *pinfo);
+
+unsigned int mclk_to_picos(unsigned int mclk);
+unsigned int get_memory_clk_period_ps(void);
+unsigned int picos_to_mclk(unsigned int picos);
+void fsl_ddr_set_lawbar(
+		const common_timing_params_t *memctl_common_params,
+		unsigned int memctl_interleaved,
+		unsigned int ctrl_num);
+
+int fsl_ddr_interactive_env_var_exists(void);
+unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set);
+void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
+			   unsigned int ctrl_num);
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr);
+void board_add_ram_info(int use_default);
+
+/* processor specific function */
+void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
+				   unsigned int ctrl_num, int step);
+
+/* board specific function */
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+			unsigned int controller_number,
+			unsigned int dimm_number);
+#endif
diff --git a/qemu/roms/u-boot/include/fsl_ddr_dimm_params.h b/qemu/roms/u-boot/include/fsl_ddr_dimm_params.h
new file mode 100644
index 000000000..09a67a680
--- /dev/null
+++ b/qemu/roms/u-boot/include/fsl_ddr_dimm_params.h
@@ -0,0 +1,120 @@
+/*
+ * Copyright 2008-2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#ifndef DDR2_DIMM_PARAMS_H
+#define DDR2_DIMM_PARAMS_H
+
+#define EDC_DATA_PARITY	1
+#define EDC_ECC		2
+#define EDC_AC_PARITY	4
+
+/* Parameters for a DDR dimm computed from the SPD */
+typedef struct dimm_params_s {
+
+	/* DIMM organization parameters */
+	char mpart[19];		/* guaranteed null terminated */
+
+	unsigned int n_ranks;
+	unsigned long long rank_density;
+	unsigned long long capacity;
+	unsigned int data_width;
+	unsigned int primary_sdram_width;
+	unsigned int ec_sdram_width;
+	unsigned int registered_dimm;
+	unsigned int device_width;	/* x4, x8, x16 components */
+
+	/* SDRAM device parameters */
+	unsigned int n_row_addr;
+	unsigned int n_col_addr;
+	unsigned int edc_config;	/* 0 = none, 1 = parity, 2 = ECC */
+#ifdef CONFIG_SYS_FSL_DDR4
+	unsigned int bank_addr_bits;
+	unsigned int bank_group_bits;
+#else
+	unsigned int n_banks_per_sdram_device;
+#endif
+	unsigned int burst_lengths_bitmask;	/* BL=4 bit 2, BL=8 = bit 3 */
+	unsigned int row_density;
+
+	/* used in computing base address of DIMMs */
+	unsigned long long base_address;
+	/* mirrored DIMMs */
+	unsigned int mirrored_dimm;	/* only for ddr3 */
+
+	/* DIMM timing parameters */
+
+	int mtb_ps;	/* medium timebase ps */
+	int ftb_10th_ps; /* fine timebase, in 1/10 ps */
+	int taa_ps;	/* minimum CAS latency time */
+	int tfaw_ps;	/* four active window delay */
+
+	/*
+	 * SDRAM clock periods
+	 * The range for these are 1000-10000 so a short should be sufficient
+	 */
+	int tckmin_x_ps;
+	int tckmin_x_minus_1_ps;
+	int tckmin_x_minus_2_ps;
+	int tckmax_ps;
+
+	/* SPD-defined CAS latencies */
+	unsigned int caslat_x;
+	unsigned int caslat_x_minus_1;
+	unsigned int caslat_x_minus_2;
+
+	unsigned int caslat_lowest_derated;	/* Derated CAS latency */
+
+	/* basic timing parameters */
+	int trcd_ps;
+	int trp_ps;
+	int tras_ps;
+
+#ifdef CONFIG_SYS_FSL_DDR4
+	int trfc1_ps;
+	int trfc2_ps;
+	int trfc4_ps;
+	int trrds_ps;
+	int trrdl_ps;
+	int tccdl_ps;
+#else
+	int twr_ps;	/* maximum = 63750 ps */
+	int trfc_ps;	/* max = 255 ns + 256 ns + .75 ns
+				       = 511750 ps */
+	int trrd_ps;	/* maximum = 63750 ps */
+	int twtr_ps;	/* maximum = 63750 ps */
+	int trtp_ps;	/* byte 38, spd->trtp */
+#endif
+
+	int trc_ps;	/* maximum = 254 ns + .75 ns = 254750 ps */
+
+	int refresh_rate_ps;
+	int extended_op_srt;
+
+#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
+	int tis_ps;	/* byte 32, spd->ca_setup */
+	int tih_ps;	/* byte 33, spd->ca_hold */
+	int tds_ps;	/* byte 34, spd->data_setup */
+	int tdh_ps;	/* byte 35, spd->data_hold */
+	int tdqsq_max_ps;	/* byte 44, spd->tdqsq */
+	int tqhs_ps;	/* byte 45, spd->tqhs */
+#endif
+
+	/* DDR3 RDIMM */
+	unsigned char rcw[16];	/* Register Control Word 0-15 */
+#ifdef CONFIG_SYS_FSL_DDR4
+	unsigned int dq_mapping[18];
+	unsigned int dq_mapping_ors;
+#endif
+} dimm_params_t;
+
+extern unsigned int ddr_compute_dimm_parameters(
+					 const generic_spd_eeprom_t *spd,
+					 dimm_params_t *pdimm,
+					 unsigned int dimm_number);
+
+#endif
diff --git a/qemu/roms/u-boot/include/fsl_ddr_sdram.h b/qemu/roms/u-boot/include/fsl_ddr_sdram.h
new file mode 100644
index 000000000..e8a2db91c
--- /dev/null
+++ b/qemu/roms/u-boot/include/fsl_ddr_sdram.h
@@ -0,0 +1,431 @@
+/*
+ * Copyright 2008-2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#ifndef FSL_DDR_MEMCTL_H
+#define FSL_DDR_MEMCTL_H
+
+/*
+ * Pick a basic DDR Technology.
+ */
+#include <ddr_spd.h>
+#include <fsl_ddrc_version.h>
+
+#define SDRAM_TYPE_DDR1		2
+#define SDRAM_TYPE_DDR2		3
+#define SDRAM_TYPE_LPDDR1	6
+#define SDRAM_TYPE_DDR3		7
+#define SDRAM_TYPE_DDR4		5
+
+#define DDR_BL4		4	/* burst length 4 */
+#define DDR_BC4		DDR_BL4	/* burst chop for ddr3 */
+#define DDR_OTF		6	/* on-the-fly BC4 and BL8 */
+#define DDR_BL8		8	/* burst length 8 */
+
+#define DDR3_RTT_OFF		0
+#define DDR3_RTT_60_OHM		1 /* RTT_Nom = RZQ/4 */
+#define DDR3_RTT_120_OHM	2 /* RTT_Nom = RZQ/2 */
+#define DDR3_RTT_40_OHM		3 /* RTT_Nom = RZQ/6 */
+#define DDR3_RTT_20_OHM		4 /* RTT_Nom = RZQ/12 */
+#define DDR3_RTT_30_OHM		5 /* RTT_Nom = RZQ/8 */
+
+#define DDR2_RTT_OFF		0
+#define DDR2_RTT_75_OHM		1
+#define DDR2_RTT_150_OHM	2
+#define DDR2_RTT_50_OHM		3
+
+#if defined(CONFIG_SYS_FSL_DDR1)
+#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR	(1)
+typedef ddr1_spd_eeprom_t generic_spd_eeprom_t;
+#ifndef CONFIG_FSL_SDRAM_TYPE
+#define CONFIG_FSL_SDRAM_TYPE	SDRAM_TYPE_DDR1
+#endif
+#elif defined(CONFIG_SYS_FSL_DDR2)
+#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR	(3)
+typedef ddr2_spd_eeprom_t generic_spd_eeprom_t;
+#ifndef CONFIG_FSL_SDRAM_TYPE
+#define CONFIG_FSL_SDRAM_TYPE	SDRAM_TYPE_DDR2
+#endif
+#elif defined(CONFIG_SYS_FSL_DDR3)
+#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR	(3)	/* FIXME */
+typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
+#ifndef CONFIG_FSL_SDRAM_TYPE
+#define CONFIG_FSL_SDRAM_TYPE	SDRAM_TYPE_DDR3
+#endif
+#elif defined(CONFIG_SYS_FSL_DDR4)
+#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR	(3)	/* FIXME */
+typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
+#ifndef CONFIG_FSL_SDRAM_TYPE
+#define CONFIG_FSL_SDRAM_TYPE	SDRAM_TYPE_DDR4
+#endif
+#endif	/* #if defined(CONFIG_SYS_FSL_DDR1) */
+
+#define FSL_DDR_ODT_NEVER		0x0
+#define FSL_DDR_ODT_CS			0x1
+#define FSL_DDR_ODT_ALL_OTHER_CS	0x2
+#define FSL_DDR_ODT_OTHER_DIMM		0x3
+#define FSL_DDR_ODT_ALL			0x4
+#define FSL_DDR_ODT_SAME_DIMM		0x5
+#define FSL_DDR_ODT_CS_AND_OTHER_DIMM	0x6
+#define FSL_DDR_ODT_OTHER_CS_ONSAMEDIMM	0x7
+
+/* define bank(chip select) interleaving mode */
+#define FSL_DDR_CS0_CS1			0x40
+#define FSL_DDR_CS2_CS3			0x20
+#define FSL_DDR_CS0_CS1_AND_CS2_CS3	(FSL_DDR_CS0_CS1 | FSL_DDR_CS2_CS3)
+#define FSL_DDR_CS0_CS1_CS2_CS3		(FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04)
+
+/* define memory controller interleaving mode */
+#define FSL_DDR_CACHE_LINE_INTERLEAVING	0x0
+#define FSL_DDR_PAGE_INTERLEAVING	0x1
+#define FSL_DDR_BANK_INTERLEAVING	0x2
+#define FSL_DDR_SUPERBANK_INTERLEAVING	0x3
+#define FSL_DDR_256B_INTERLEAVING	0x8
+#define FSL_DDR_3WAY_1KB_INTERLEAVING	0xA
+#define FSL_DDR_3WAY_4KB_INTERLEAVING	0xC
+#define FSL_DDR_3WAY_8KB_INTERLEAVING	0xD
+/* placeholder for 4-way interleaving */
+#define FSL_DDR_4WAY_1KB_INTERLEAVING	0x1A
+#define FSL_DDR_4WAY_4KB_INTERLEAVING	0x1C
+#define FSL_DDR_4WAY_8KB_INTERLEAVING	0x1D
+
+#define SDRAM_CS_CONFIG_EN		0x80000000
+
+/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
+ */
+#define SDRAM_CFG_MEM_EN		0x80000000
+#define SDRAM_CFG_SREN			0x40000000
+#define SDRAM_CFG_ECC_EN		0x20000000
+#define SDRAM_CFG_RD_EN			0x10000000
+#define SDRAM_CFG_SDRAM_TYPE_DDR1	0x02000000
+#define SDRAM_CFG_SDRAM_TYPE_DDR2	0x03000000
+#define SDRAM_CFG_SDRAM_TYPE_MASK	0x07000000
+#define SDRAM_CFG_SDRAM_TYPE_SHIFT	24
+#define SDRAM_CFG_DYN_PWR		0x00200000
+#define SDRAM_CFG_DBW_MASK		0x00180000
+#define SDRAM_CFG_DBW_SHIFT		19
+#define SDRAM_CFG_32_BE			0x00080000
+#define SDRAM_CFG_16_BE			0x00100000
+#define SDRAM_CFG_8_BE			0x00040000
+#define SDRAM_CFG_NCAP			0x00020000
+#define SDRAM_CFG_2T_EN			0x00008000
+#define SDRAM_CFG_BI			0x00000001
+
+#define SDRAM_CFG2_D_INIT		0x00000010
+#define SDRAM_CFG2_ODT_CFG_MASK		0x00600000
+#define SDRAM_CFG2_ODT_NEVER		0
+#define SDRAM_CFG2_ODT_ONLY_WRITE	1
+#define SDRAM_CFG2_ODT_ONLY_READ	2
+#define SDRAM_CFG2_ODT_ALWAYS		3
+
+#define TIMING_CFG_2_CPO_MASK	0x0F800000
+
+#if defined(CONFIG_SYS_FSL_DDR_VER) && \
+	(CONFIG_SYS_FSL_DDR_VER > FSL_DDR_VER_4_4)
+#define RD_TO_PRE_MASK		0xf
+#define RD_TO_PRE_SHIFT		13
+#define WR_DATA_DELAY_MASK	0xf
+#define WR_DATA_DELAY_SHIFT	9
+#else
+#define RD_TO_PRE_MASK		0x7
+#define RD_TO_PRE_SHIFT		13
+#define WR_DATA_DELAY_MASK	0x7
+#define WR_DATA_DELAY_SHIFT	10
+#endif
+
+/* DDR_MD_CNTL */
+#define MD_CNTL_MD_EN		0x80000000
+#define MD_CNTL_CS_SEL_CS0	0x00000000
+#define MD_CNTL_CS_SEL_CS1	0x10000000
+#define MD_CNTL_CS_SEL_CS2	0x20000000
+#define MD_CNTL_CS_SEL_CS3	0x30000000
+#define MD_CNTL_CS_SEL_CS0_CS1	0x40000000
+#define MD_CNTL_CS_SEL_CS2_CS3	0x50000000
+#define MD_CNTL_MD_SEL_MR	0x00000000
+#define MD_CNTL_MD_SEL_EMR	0x01000000
+#define MD_CNTL_MD_SEL_EMR2	0x02000000
+#define MD_CNTL_MD_SEL_EMR3	0x03000000
+#define MD_CNTL_SET_REF		0x00800000
+#define MD_CNTL_SET_PRE		0x00400000
+#define MD_CNTL_CKE_CNTL_LOW	0x00100000
+#define MD_CNTL_CKE_CNTL_HIGH	0x00200000
+#define MD_CNTL_WRCW		0x00080000
+#define MD_CNTL_MD_VALUE(x)	(x & 0x0000FFFF)
+
+/* DDR_CDR1 */
+#define DDR_CDR1_DHC_EN	0x80000000
+#define DDR_CDR1_ODT_SHIFT	17
+#define DDR_CDR1_ODT_MASK	0x6
+#define DDR_CDR2_ODT_MASK	0x1
+#define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT)
+#define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK)
+#define DDR_CDR2_VREF_OVRD(x)	(0x00008080 | ((((x) - 37) & 0x3F) << 8))
+
+#if (defined(CONFIG_SYS_FSL_DDR_VER) && \
+	(CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7))
+#ifdef CONFIG_SYS_FSL_DDR3L
+#define DDR_CDR_ODT_OFF		0x0
+#define DDR_CDR_ODT_120ohm	0x1
+#define DDR_CDR_ODT_200ohm	0x2
+#define DDR_CDR_ODT_75ohm	0x3
+#define DDR_CDR_ODT_60ohm	0x5
+#define DDR_CDR_ODT_46ohm	0x7
+#elif defined(CONFIG_SYS_FSL_DDR4)
+#define DDR_CDR_ODT_OFF		0x0
+#define DDR_CDR_ODT_100ohm	0x1
+#define DDR_CDR_ODT_120OHM	0x2
+#define DDR_CDR_ODT_80ohm	0x3
+#define DDR_CDR_ODT_60ohm	0x4
+#define DDR_CDR_ODT_40ohm	0x5
+#define DDR_CDR_ODT_50ohm	0x6
+#define DDR_CDR_ODT_30ohm	0x7
+#else
+#define DDR_CDR_ODT_OFF		0x0
+#define DDR_CDR_ODT_120ohm	0x1
+#define DDR_CDR_ODT_180ohm	0x2
+#define DDR_CDR_ODT_75ohm	0x3
+#define DDR_CDR_ODT_110ohm	0x4
+#define DDR_CDR_ODT_60hm	0x5
+#define DDR_CDR_ODT_70ohm	0x6
+#define DDR_CDR_ODT_47ohm	0x7
+#endif /* DDR3L */
+#else
+#define DDR_CDR_ODT_75ohm	0x0
+#define DDR_CDR_ODT_55ohm	0x1
+#define DDR_CDR_ODT_60ohm	0x2
+#define DDR_CDR_ODT_50ohm	0x3
+#define DDR_CDR_ODT_150ohm	0x4
+#define DDR_CDR_ODT_43ohm	0x5
+#define DDR_CDR_ODT_120ohm	0x6
+#endif
+
+/* Record of register values computed */
+typedef struct fsl_ddr_cfg_regs_s {
+	struct {
+		unsigned int bnds;
+		unsigned int config;
+		unsigned int config_2;
+	} cs[CONFIG_CHIP_SELECTS_PER_CTRL];
+	unsigned int timing_cfg_3;
+	unsigned int timing_cfg_0;
+	unsigned int timing_cfg_1;
+	unsigned int timing_cfg_2;
+	unsigned int ddr_sdram_cfg;
+	unsigned int ddr_sdram_cfg_2;
+	unsigned int ddr_sdram_cfg_3;
+	unsigned int ddr_sdram_mode;
+	unsigned int ddr_sdram_mode_2;
+	unsigned int ddr_sdram_mode_3;
+	unsigned int ddr_sdram_mode_4;
+	unsigned int ddr_sdram_mode_5;
+	unsigned int ddr_sdram_mode_6;
+	unsigned int ddr_sdram_mode_7;
+	unsigned int ddr_sdram_mode_8;
+	unsigned int ddr_sdram_mode_9;
+	unsigned int ddr_sdram_mode_10;
+	unsigned int ddr_sdram_mode_11;
+	unsigned int ddr_sdram_mode_12;
+	unsigned int ddr_sdram_mode_13;
+	unsigned int ddr_sdram_mode_14;
+	unsigned int ddr_sdram_mode_15;
+	unsigned int ddr_sdram_mode_16;
+	unsigned int ddr_sdram_md_cntl;
+	unsigned int ddr_sdram_interval;
+	unsigned int ddr_data_init;
+	unsigned int ddr_sdram_clk_cntl;
+	unsigned int ddr_init_addr;
+	unsigned int ddr_init_ext_addr;
+	unsigned int timing_cfg_4;
+	unsigned int timing_cfg_5;
+	unsigned int timing_cfg_6;
+	unsigned int timing_cfg_7;
+	unsigned int timing_cfg_8;
+	unsigned int timing_cfg_9;
+	unsigned int ddr_zq_cntl;
+	unsigned int ddr_wrlvl_cntl;
+	unsigned int ddr_wrlvl_cntl_2;
+	unsigned int ddr_wrlvl_cntl_3;
+	unsigned int ddr_sr_cntr;
+	unsigned int ddr_sdram_rcw_1;
+	unsigned int ddr_sdram_rcw_2;
+	unsigned int ddr_sdram_rcw_3;
+	unsigned int ddr_sdram_rcw_4;
+	unsigned int ddr_sdram_rcw_5;
+	unsigned int ddr_sdram_rcw_6;
+	unsigned int dq_map_0;
+	unsigned int dq_map_1;
+	unsigned int dq_map_2;
+	unsigned int dq_map_3;
+	unsigned int ddr_eor;
+	unsigned int ddr_cdr1;
+	unsigned int ddr_cdr2;
+	unsigned int err_disable;
+	unsigned int err_int_en;
+	unsigned int debug[32];
+} fsl_ddr_cfg_regs_t;
+
+typedef struct memctl_options_partial_s {
+	unsigned int all_dimms_ecc_capable;
+	unsigned int all_dimms_tckmax_ps;
+	unsigned int all_dimms_burst_lengths_bitmask;
+	unsigned int all_dimms_registered;
+	unsigned int all_dimms_unbuffered;
+	/*	unsigned int lowest_common_spd_caslat; */
+	unsigned int all_dimms_minimum_trcd_ps;
+} memctl_options_partial_t;
+
+#define DDR_DATA_BUS_WIDTH_64 0
+#define DDR_DATA_BUS_WIDTH_32 1
+#define DDR_DATA_BUS_WIDTH_16 2
+/*
+ * Generalized parameters for memory controller configuration,
+ * might be a little specific to the FSL memory controller
+ */
+typedef struct memctl_options_s {
+	/*
+	 * Memory organization parameters
+	 *
+	 * if DIMM is present in the system
+	 * where DIMMs are with respect to chip select
+	 * where chip selects are with respect to memory boundaries
+	 */
+	unsigned int registered_dimm_en;    /* use registered DIMM support */
+
+	/* Options local to a Chip Select */
+	struct cs_local_opts_s {
+		unsigned int auto_precharge;
+		unsigned int odt_rd_cfg;
+		unsigned int odt_wr_cfg;
+		unsigned int odt_rtt_norm;
+		unsigned int odt_rtt_wr;
+	} cs_local_opts[CONFIG_CHIP_SELECTS_PER_CTRL];
+
+	/* Special configurations for chip select */
+	unsigned int memctl_interleaving;
+	unsigned int memctl_interleaving_mode;
+	unsigned int ba_intlv_ctl;
+	unsigned int addr_hash;
+
+	/* Operational mode parameters */
+	unsigned int ecc_mode;	 /* Use ECC? */
+	/* Initialize ECC using memory controller? */
+	unsigned int ecc_init_using_memctl;
+	unsigned int dqs_config;	/* Use DQS? maybe only with DDR2? */
+	/* SREN - self-refresh during sleep */
+	unsigned int self_refresh_in_sleep;
+	unsigned int dynamic_power;	/* DYN_PWR */
+	/* memory data width to use (16-bit, 32-bit, 64-bit) */
+	unsigned int data_bus_width;
+	unsigned int burst_length;	/* BL4, OTF and BL8 */
+	/* On-The-Fly Burst Chop enable */
+	unsigned int otf_burst_chop_en;
+	/* mirrior DIMMs for DDR3 */
+	unsigned int mirrored_dimm;
+	unsigned int quad_rank_present;
+	unsigned int ap_en;	/* address parity enable for RDIMM */
+	unsigned int x4_en;	/* enable x4 devices */
+
+	/* Global Timing Parameters */
+	unsigned int cas_latency_override;
+	unsigned int cas_latency_override_value;
+	unsigned int use_derated_caslat;
+	unsigned int additive_latency_override;
+	unsigned int additive_latency_override_value;
+
+	unsigned int clk_adjust;		/* */
+	unsigned int cpo_override;
+	unsigned int write_data_delay;		/* DQS adjust */
+
+	unsigned int wrlvl_override;
+	unsigned int wrlvl_sample;		/* Write leveling */
+	unsigned int wrlvl_start;
+	unsigned int wrlvl_ctl_2;
+	unsigned int wrlvl_ctl_3;
+
+	unsigned int half_strength_driver_enable;
+	unsigned int twot_en;
+	unsigned int threet_en;
+	unsigned int bstopre;
+	unsigned int tcke_clock_pulse_width_ps;	/* tCKE */
+	unsigned int tfaw_window_four_activates_ps;	/* tFAW --  FOUR_ACT */
+
+	/* Rtt impedance */
+	unsigned int rtt_override;		/* rtt_override enable */
+	unsigned int rtt_override_value;	/* that is Rtt_Nom for DDR3 */
+	unsigned int rtt_wr_override_value;	/* this is Rtt_WR for DDR3 */
+
+	/* Automatic self refresh */
+	unsigned int auto_self_refresh_en;
+	unsigned int sr_it;
+	/* ZQ calibration */
+	unsigned int zq_en;
+	/* Write leveling */
+	unsigned int wrlvl_en;
+	/* RCW override for RDIMM */
+	unsigned int rcw_override;
+	unsigned int rcw_1;
+	unsigned int rcw_2;
+	/* control register 1 */
+	unsigned int ddr_cdr1;
+	unsigned int ddr_cdr2;
+
+	unsigned int trwt_override;
+	unsigned int trwt;			/* read-to-write turnaround */
+} memctl_options_t;
+
+extern phys_size_t fsl_ddr_sdram(void);
+extern phys_size_t fsl_ddr_sdram_size(void);
+extern int fsl_use_spd(void);
+extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
+					unsigned int ctrl_num, int step);
+u32 fsl_ddr_get_intl3r(void);
+
+static void __board_assert_mem_reset(void)
+{
+}
+
+static void __board_deassert_mem_reset(void)
+{
+}
+
+void board_assert_mem_reset(void)
+	__attribute__((weak, alias("__board_assert_mem_reset")));
+
+void board_deassert_mem_reset(void)
+	__attribute__((weak, alias("__board_deassert_mem_reset")));
+
+static int __board_need_mem_reset(void)
+{
+	return 0;
+}
+
+int board_need_mem_reset(void)
+	__attribute__((weak, alias("__board_need_mem_reset")));
+
+void __weak board_mem_sleep_setup(void)
+{
+}
+
+/*
+ * The 85xx boards have a common prototype for fixed_sdram so put the
+ * declaration here.
+ */
+#ifdef CONFIG_MPC85xx
+extern phys_size_t fixed_sdram(void);
+#endif
+
+#if defined(CONFIG_DDR_ECC)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+
+typedef struct fixed_ddr_parm{
+	int min_freq;
+	int max_freq;
+	fsl_ddr_cfg_regs_t *ddr_settings;
+} fixed_ddr_parm_t;
+#endif
diff --git a/qemu/roms/u-boot/include/fsl_ddrc_version.h b/qemu/roms/u-boot/include/fsl_ddrc_version.h
new file mode 100644
index 000000000..60ba98bf8
--- /dev/null
+++ b/qemu/roms/u-boot/include/fsl_ddrc_version.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __FSL_DDRC_VER_H
+#define __FSL_DDRC_VER_H
+
+/*
+ * Only the versions with distinct features or registers are listed here.
+ */
+#define FSL_DDR_VER_4_4 44
+#define FSL_DDR_VER_4_6 46
+#define FSL_DDR_VER_4_7	47
+#define FSL_DDR_VER_5_0	50
+
+#endif /* __FSL_DDRC_VER_H */
diff --git a/qemu/roms/u-boot/include/fsl_diu_fb.h b/qemu/roms/u-boot/include/fsl_diu_fb.h
new file mode 100644
index 000000000..7898b2bb2
--- /dev/null
+++ b/qemu/roms/u-boot/include/fsl_diu_fb.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright 2007, 2011 Freescale Semiconductor, Inc.
+ * Authors: York Sun <yorksun@freescale.com>
+ *          Timur Tabi <timur@freescale.com>
+ *
+ * FSL DIU Framebuffer driver
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+int fsl_diu_init(u16 xres, u16 yres, u32 pixel_format, int gamma_fix);
+
+/* Prototypes for external board-specific functions */
+int platform_diu_init(unsigned int xres, unsigned int yres, const char *port);
+void diu_set_pixel_clock(unsigned int pixclock);
diff --git a/qemu/roms/u-boot/include/fsl_esdhc.h b/qemu/roms/u-boot/include/fsl_esdhc.h
new file mode 100644
index 000000000..981496493
--- /dev/null
+++ b/qemu/roms/u-boot/include/fsl_esdhc.h
@@ -0,0 +1,192 @@
+/*
+ * FSL SD/MMC Defines
+ *-------------------------------------------------------------------
+ *
+ * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef  __FSL_ESDHC_H__
+#define	__FSL_ESDHC_H__
+
+#include <asm/errno.h>
+#include <asm/byteorder.h>
+
+/* needed for the mmc_cfg definition */
+#include <mmc.h>
+
+/* FSL eSDHC-specific constants */
+#define SYSCTL			0x0002e02c
+#define SYSCTL_INITA		0x08000000
+#define SYSCTL_TIMEOUT_MASK	0x000f0000
+#define SYSCTL_CLOCK_MASK	0x0000fff0
+#define SYSCTL_CKEN		0x00000008
+#define SYSCTL_PEREN		0x00000004
+#define SYSCTL_HCKEN		0x00000002
+#define SYSCTL_IPGEN		0x00000001
+#define SYSCTL_RSTA		0x01000000
+#define SYSCTL_RSTC		0x02000000
+#define SYSCTL_RSTD		0x04000000
+
+#define IRQSTAT			0x0002e030
+#define IRQSTAT_DMAE		(0x10000000)
+#define IRQSTAT_AC12E		(0x01000000)
+#define IRQSTAT_DEBE		(0x00400000)
+#define IRQSTAT_DCE		(0x00200000)
+#define IRQSTAT_DTOE		(0x00100000)
+#define IRQSTAT_CIE		(0x00080000)
+#define IRQSTAT_CEBE		(0x00040000)
+#define IRQSTAT_CCE		(0x00020000)
+#define IRQSTAT_CTOE		(0x00010000)
+#define IRQSTAT_CINT		(0x00000100)
+#define IRQSTAT_CRM		(0x00000080)
+#define IRQSTAT_CINS		(0x00000040)
+#define IRQSTAT_BRR		(0x00000020)
+#define IRQSTAT_BWR		(0x00000010)
+#define IRQSTAT_DINT		(0x00000008)
+#define IRQSTAT_BGE		(0x00000004)
+#define IRQSTAT_TC		(0x00000002)
+#define IRQSTAT_CC		(0x00000001)
+
+#define CMD_ERR		(IRQSTAT_CIE | IRQSTAT_CEBE | IRQSTAT_CCE)
+#define DATA_ERR	(IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE | \
+				IRQSTAT_DMAE)
+#define DATA_COMPLETE	(IRQSTAT_TC | IRQSTAT_DINT)
+
+#define IRQSTATEN		0x0002e034
+#define IRQSTATEN_DMAE		(0x10000000)
+#define IRQSTATEN_AC12E		(0x01000000)
+#define IRQSTATEN_DEBE		(0x00400000)
+#define IRQSTATEN_DCE		(0x00200000)
+#define IRQSTATEN_DTOE		(0x00100000)
+#define IRQSTATEN_CIE		(0x00080000)
+#define IRQSTATEN_CEBE		(0x00040000)
+#define IRQSTATEN_CCE		(0x00020000)
+#define IRQSTATEN_CTOE		(0x00010000)
+#define IRQSTATEN_CINT		(0x00000100)
+#define IRQSTATEN_CRM		(0x00000080)
+#define IRQSTATEN_CINS		(0x00000040)
+#define IRQSTATEN_BRR		(0x00000020)
+#define IRQSTATEN_BWR		(0x00000010)
+#define IRQSTATEN_DINT		(0x00000008)
+#define IRQSTATEN_BGE		(0x00000004)
+#define IRQSTATEN_TC		(0x00000002)
+#define IRQSTATEN_CC		(0x00000001)
+
+#define PRSSTAT			0x0002e024
+#define PRSSTAT_DAT0		(0x01000000)
+#define PRSSTAT_CLSL		(0x00800000)
+#define PRSSTAT_WPSPL		(0x00080000)
+#define PRSSTAT_CDPL		(0x00040000)
+#define PRSSTAT_CINS		(0x00010000)
+#define PRSSTAT_BREN		(0x00000800)
+#define PRSSTAT_BWEN		(0x00000400)
+#define PRSSTAT_DLA		(0x00000004)
+#define PRSSTAT_CICHB		(0x00000002)
+#define PRSSTAT_CIDHB		(0x00000001)
+
+#define PROCTL			0x0002e028
+#define PROCTL_INIT		0x00000020
+#define PROCTL_DTW_4		0x00000002
+#define PROCTL_DTW_8		0x00000004
+
+#define CMDARG			0x0002e008
+
+#define XFERTYP			0x0002e00c
+#define XFERTYP_CMD(x)		((x & 0x3f) << 24)
+#define XFERTYP_CMDTYP_NORMAL	0x0
+#define XFERTYP_CMDTYP_SUSPEND	0x00400000
+#define XFERTYP_CMDTYP_RESUME	0x00800000
+#define XFERTYP_CMDTYP_ABORT	0x00c00000
+#define XFERTYP_DPSEL		0x00200000
+#define XFERTYP_CICEN		0x00100000
+#define XFERTYP_CCCEN		0x00080000
+#define XFERTYP_RSPTYP_NONE	0
+#define XFERTYP_RSPTYP_136	0x00010000
+#define XFERTYP_RSPTYP_48	0x00020000
+#define XFERTYP_RSPTYP_48_BUSY	0x00030000
+#define XFERTYP_MSBSEL		0x00000020
+#define XFERTYP_DTDSEL		0x00000010
+#define XFERTYP_AC12EN		0x00000004
+#define XFERTYP_BCEN		0x00000002
+#define XFERTYP_DMAEN		0x00000001
+
+#define CINS_TIMEOUT		1000
+#define PIO_TIMEOUT		100000
+
+#define DSADDR		0x2e004
+
+#define CMDRSP0		0x2e010
+#define CMDRSP1		0x2e014
+#define CMDRSP2		0x2e018
+#define CMDRSP3		0x2e01c
+
+#define DATPORT		0x2e020
+
+#define WML		0x2e044
+#define WML_WRITE	0x00010000
+#ifdef CONFIG_FSL_SDHC_V2_3
+#define WML_RD_WML_MAX		0x80
+#define WML_WR_WML_MAX		0x80
+#define WML_RD_WML_MAX_VAL	0x0
+#define WML_WR_WML_MAX_VAL	0x0
+#define WML_RD_WML_MASK		0x7f
+#define WML_WR_WML_MASK		0x7f0000
+#else
+#define WML_RD_WML_MAX		0x10
+#define WML_WR_WML_MAX		0x80
+#define WML_RD_WML_MAX_VAL	0x10
+#define WML_WR_WML_MAX_VAL	0x80
+#define WML_RD_WML_MASK	0xff
+#define WML_WR_WML_MASK	0xff0000
+#endif
+
+#define BLKATTR		0x2e004
+#define BLKATTR_CNT(x)	((x & 0xffff) << 16)
+#define BLKATTR_SIZE(x)	(x & 0x1fff)
+#define MAX_BLK_CNT	0x7fff	/* so malloc will have enough room with 32M */
+
+#define ESDHC_HOSTCAPBLT_VS18	0x04000000
+#define ESDHC_HOSTCAPBLT_VS30	0x02000000
+#define ESDHC_HOSTCAPBLT_VS33	0x01000000
+#define ESDHC_HOSTCAPBLT_SRS	0x00800000
+#define ESDHC_HOSTCAPBLT_DMAS	0x00400000
+#define ESDHC_HOSTCAPBLT_HSS	0x00200000
+
+struct fsl_esdhc_cfg {
+	u32	esdhc_base;
+	u32	sdhc_clk;
+	u8	max_bus_width;
+	struct mmc_config cfg;
+};
+
+/* Select the correct accessors depending on endianess */
+#if __BYTE_ORDER == __LITTLE_ENDIAN
+#define esdhc_read32		in_le32
+#define esdhc_write32		out_le32
+#define esdhc_clrsetbits32	clrsetbits_le32
+#define esdhc_clrbits32		clrbits_le32
+#define esdhc_setbits32		setbits_le32
+#elif __BYTE_ORDER == __BIG_ENDIAN
+#define esdhc_read32		in_be32
+#define esdhc_write32		out_be32
+#define esdhc_clrsetbits32	clrsetbits_be32
+#define esdhc_clrbits32		clrbits_be32
+#define esdhc_setbits32		setbits_be32
+#else
+#error "Endianess is not defined: please fix to continue"
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+int fsl_esdhc_mmc_init(bd_t *bis);
+int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg);
+void fdt_fixup_esdhc(void *blob, bd_t *bd);
+#else
+static inline int fsl_esdhc_mmc_init(bd_t *bis) { return -ENOSYS; }
+static inline void fdt_fixup_esdhc(void *blob, bd_t *bd) {}
+#endif /* CONFIG_FSL_ESDHC */
+void __noreturn mmc_boot(void);
+void mmc_spl_load_image(uint32_t offs, unsigned int size, void *vdst);
+
+#endif  /* __FSL_ESDHC_H__ */
diff --git a/qemu/roms/u-boot/include/fsl_ifc.h b/qemu/roms/u-boot/include/fsl_ifc.h
new file mode 100644
index 000000000..630e4b499
--- /dev/null
+++ b/qemu/roms/u-boot/include/fsl_ifc.h
@@ -0,0 +1,1005 @@
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ * Author: Dipen Dudhat <dipen.dudhat@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __FSL_IFC_H
+#define __FSL_IFC_H
+
+#ifdef CONFIG_FSL_IFC
+#include <config.h>
+#include <common.h>
+
+
+#ifdef CONFIG_SYS_FSL_IFC_LE
+#define ifc_in32(a)       in_le32(a)
+#define ifc_out32(a, v)   out_le32(a, v)
+#define ifc_in16(a)       in_le16(a)
+#elif defined(CONFIG_SYS_FSL_IFC_BE)
+#define ifc_in32(a)       in_be32(a)
+#define ifc_out32(a, v)   out_be32(a, v)
+#define ifc_in16(a)       in_be16(a)
+#else
+#error Neither CONFIG_SYS_FSL_IFC_LE nor CONFIG_SYS_FSL_IFC_BE is defined
+#endif
+
+
+/*
+ * CSPR - Chip Select Property Register
+ */
+#define CSPR_BA				0xFFFF0000
+#define CSPR_BA_SHIFT			16
+#define CSPR_PORT_SIZE			0x00000180
+#define CSPR_PORT_SIZE_SHIFT		7
+/* Port Size 8 bit */
+#define CSPR_PORT_SIZE_8		0x00000080
+/* Port Size 16 bit */
+#define CSPR_PORT_SIZE_16		0x00000100
+/* Port Size 32 bit */
+#define CSPR_PORT_SIZE_32		0x00000180
+/* Write Protect */
+#define CSPR_WP				0x00000040
+#define CSPR_WP_SHIFT			6
+/* Machine Select */
+#define CSPR_MSEL			0x00000006
+#define CSPR_MSEL_SHIFT			1
+/* NOR */
+#define CSPR_MSEL_NOR			0x00000000
+/* NAND */
+#define CSPR_MSEL_NAND			0x00000002
+/* GPCM */
+#define CSPR_MSEL_GPCM			0x00000004
+/* Bank Valid */
+#define CSPR_V				0x00000001
+#define CSPR_V_SHIFT			0
+
+/* Convert an address into the right format for the CSPR Registers */
+#define CSPR_PHYS_ADDR(x)		(((uint64_t)x) & 0xffff0000)
+
+/*
+ * Address Mask Register
+ */
+#define IFC_AMASK_MASK			0xFFFF0000
+#define IFC_AMASK_SHIFT			16
+#define IFC_AMASK(n)			(IFC_AMASK_MASK << \
+					(__ilog2(n) - IFC_AMASK_SHIFT))
+
+/*
+ * Chip Select Option Register IFC_NAND Machine
+ */
+/* Enable ECC Encoder */
+#define CSOR_NAND_ECC_ENC_EN		0x80000000
+#define CSOR_NAND_ECC_MODE_MASK		0x30000000
+/* 4 bit correction per 520 Byte sector */
+#define CSOR_NAND_ECC_MODE_4		0x00000000
+/* 8 bit correction per 528 Byte sector */
+#define CSOR_NAND_ECC_MODE_8		0x10000000
+/* Enable ECC Decoder */
+#define CSOR_NAND_ECC_DEC_EN		0x04000000
+/* Row Address Length */
+#define CSOR_NAND_RAL_MASK		0x01800000
+#define CSOR_NAND_RAL_SHIFT		20
+#define CSOR_NAND_RAL_1			0x00000000
+#define CSOR_NAND_RAL_2			0x00800000
+#define CSOR_NAND_RAL_3			0x01000000
+#define CSOR_NAND_RAL_4			0x01800000
+/* Page Size 512b, 2k, 4k */
+#define CSOR_NAND_PGS_MASK		0x00180000
+#define CSOR_NAND_PGS_SHIFT		16
+#define CSOR_NAND_PGS_512		0x00000000
+#define CSOR_NAND_PGS_2K		0x00080000
+#define CSOR_NAND_PGS_4K		0x00100000
+#define CSOR_NAND_PGS_8K		0x00180000
+/* Spare region Size */
+#define CSOR_NAND_SPRZ_MASK		0x0000E000
+#define CSOR_NAND_SPRZ_SHIFT		13
+#define CSOR_NAND_SPRZ_16		0x00000000
+#define CSOR_NAND_SPRZ_64		0x00002000
+#define CSOR_NAND_SPRZ_128		0x00004000
+#define CSOR_NAND_SPRZ_210		0x00006000
+#define CSOR_NAND_SPRZ_218		0x00008000
+#define CSOR_NAND_SPRZ_224		0x0000A000
+#define CSOR_NAND_SPRZ_CSOR_EXT	0x0000C000
+/* Pages Per Block */
+#define CSOR_NAND_PB_MASK		0x00000700
+#define CSOR_NAND_PB_SHIFT		8
+#define CSOR_NAND_PB(n)		((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT)
+/* Time for Read Enable High to Output High Impedance */
+#define CSOR_NAND_TRHZ_MASK		0x0000001C
+#define CSOR_NAND_TRHZ_SHIFT		2
+#define CSOR_NAND_TRHZ_20		0x00000000
+#define CSOR_NAND_TRHZ_40		0x00000004
+#define CSOR_NAND_TRHZ_60		0x00000008
+#define CSOR_NAND_TRHZ_80		0x0000000C
+#define CSOR_NAND_TRHZ_100		0x00000010
+/* Buffer control disable */
+#define CSOR_NAND_BCTLD			0x00000001
+
+/*
+ * Chip Select Option Register - NOR Flash Mode
+ */
+/* Enable Address shift Mode */
+#define CSOR_NOR_ADM_SHFT_MODE_EN	0x80000000
+/* Page Read Enable from NOR device */
+#define CSOR_NOR_PGRD_EN		0x10000000
+/* AVD Toggle Enable during Burst Program */
+#define CSOR_NOR_AVD_TGL_PGM_EN		0x01000000
+/* Address Data Multiplexing Shift */
+#define CSOR_NOR_ADM_MASK		0x0003E000
+#define CSOR_NOR_ADM_SHIFT_SHIFT	13
+#define CSOR_NOR_ADM_SHIFT(n)	((n) << CSOR_NOR_ADM_SHIFT_SHIFT)
+/* Type of the NOR device hooked */
+#define CSOR_NOR_NOR_MODE_AYSNC_NOR	0x00000000
+#define CSOR_NOR_NOR_MODE_AVD_NOR	0x00000020
+/* Time for Read Enable High to Output High Impedance */
+#define CSOR_NOR_TRHZ_MASK		0x0000001C
+#define CSOR_NOR_TRHZ_SHIFT		2
+#define CSOR_NOR_TRHZ_20		0x00000000
+#define CSOR_NOR_TRHZ_40		0x00000004
+#define CSOR_NOR_TRHZ_60		0x00000008
+#define CSOR_NOR_TRHZ_80		0x0000000C
+#define CSOR_NOR_TRHZ_100		0x00000010
+/* Buffer control disable */
+#define CSOR_NOR_BCTLD			0x00000001
+
+/*
+ * Chip Select Option Register - GPCM Mode
+ */
+/* GPCM Mode - Normal */
+#define CSOR_GPCM_GPMODE_NORMAL		0x00000000
+/* GPCM Mode - GenericASIC */
+#define CSOR_GPCM_GPMODE_ASIC		0x80000000
+/* Parity Mode odd/even */
+#define CSOR_GPCM_PARITY_EVEN		0x40000000
+/* Parity Checking enable/disable */
+#define CSOR_GPCM_PAR_EN		0x20000000
+/* GPCM Timeout Count */
+#define CSOR_GPCM_GPTO_MASK		0x0F000000
+#define CSOR_GPCM_GPTO_SHIFT		24
+#define CSOR_GPCM_GPTO(n)	((__ilog2(n) - 8) << CSOR_GPCM_GPTO_SHIFT)
+/* GPCM External Access Termination mode for read access */
+#define CSOR_GPCM_RGETA_EXT		0x00080000
+/* GPCM External Access Termination mode for write access */
+#define CSOR_GPCM_WGETA_EXT		0x00040000
+/* Address Data Multiplexing Shift */
+#define CSOR_GPCM_ADM_MASK		0x0003E000
+#define CSOR_GPCM_ADM_SHIFT_SHIFT	13
+#define CSOR_GPCM_ADM_SHIFT(n)	((n) << CSOR_GPCM_ADM_SHIFT_SHIFT)
+/* Generic ASIC Parity error indication delay */
+#define CSOR_GPCM_GAPERRD_MASK		0x00000180
+#define CSOR_GPCM_GAPERRD_SHIFT		7
+#define CSOR_GPCM_GAPERRD(n)	(((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT)
+/* Time for Read Enable High to Output High Impedance */
+#define CSOR_GPCM_TRHZ_MASK		0x0000001C
+#define CSOR_GPCM_TRHZ_20		0x00000000
+#define CSOR_GPCM_TRHZ_40		0x00000004
+#define CSOR_GPCM_TRHZ_60		0x00000008
+#define CSOR_GPCM_TRHZ_80		0x0000000C
+#define CSOR_GPCM_TRHZ_100		0x00000010
+/* Buffer control disable */
+#define CSOR_GPCM_BCTLD			0x00000001
+
+/*
+ * Flash Timing Registers (FTIM0 - FTIM2_CSn)
+ */
+/*
+ * FTIM0 - NAND Flash Mode
+ */
+#define FTIM0_NAND			0x7EFF3F3F
+#define FTIM0_NAND_TCCST_SHIFT	25
+#define FTIM0_NAND_TCCST(n)	((n) << FTIM0_NAND_TCCST_SHIFT)
+#define FTIM0_NAND_TWP_SHIFT	16
+#define FTIM0_NAND_TWP(n)	((n) << FTIM0_NAND_TWP_SHIFT)
+#define FTIM0_NAND_TWCHT_SHIFT	8
+#define FTIM0_NAND_TWCHT(n)	((n) << FTIM0_NAND_TWCHT_SHIFT)
+#define FTIM0_NAND_TWH_SHIFT	0
+#define FTIM0_NAND_TWH(n)	((n) << FTIM0_NAND_TWH_SHIFT)
+/*
+ * FTIM1 - NAND Flash Mode
+ */
+#define FTIM1_NAND			0xFFFF3FFF
+#define FTIM1_NAND_TADLE_SHIFT	24
+#define FTIM1_NAND_TADLE(n)	((n) << FTIM1_NAND_TADLE_SHIFT)
+#define FTIM1_NAND_TWBE_SHIFT	16
+#define FTIM1_NAND_TWBE(n)	((n) << FTIM1_NAND_TWBE_SHIFT)
+#define FTIM1_NAND_TRR_SHIFT	8
+#define FTIM1_NAND_TRR(n)	((n) << FTIM1_NAND_TRR_SHIFT)
+#define FTIM1_NAND_TRP_SHIFT	0
+#define FTIM1_NAND_TRP(n)	((n) << FTIM1_NAND_TRP_SHIFT)
+/*
+ * FTIM2 - NAND Flash Mode
+ */
+#define FTIM2_NAND			0x1FE1F8FF
+#define FTIM2_NAND_TRAD_SHIFT	21
+#define FTIM2_NAND_TRAD(n)	((n) << FTIM2_NAND_TRAD_SHIFT)
+#define FTIM2_NAND_TREH_SHIFT	11
+#define FTIM2_NAND_TREH(n)	((n) << FTIM2_NAND_TREH_SHIFT)
+#define FTIM2_NAND_TWHRE_SHIFT	0
+#define FTIM2_NAND_TWHRE(n)	((n) << FTIM2_NAND_TWHRE_SHIFT)
+/*
+ * FTIM3 - NAND Flash Mode
+ */
+#define FTIM3_NAND			0xFF000000
+#define FTIM3_NAND_TWW_SHIFT	24
+#define FTIM3_NAND_TWW(n)	((n) << FTIM3_NAND_TWW_SHIFT)
+
+/*
+ * FTIM0 - NOR Flash Mode
+ */
+#define FTIM0_NOR			0xF03F3F3F
+#define FTIM0_NOR_TACSE_SHIFT	28
+#define FTIM0_NOR_TACSE(n)	((n) << FTIM0_NOR_TACSE_SHIFT)
+#define FTIM0_NOR_TEADC_SHIFT	16
+#define FTIM0_NOR_TEADC(n)	((n) << FTIM0_NOR_TEADC_SHIFT)
+#define FTIM0_NOR_TAVDS_SHIFT	8
+#define FTIM0_NOR_TAVDS(n)	((n) << FTIM0_NOR_TAVDS_SHIFT)
+#define FTIM0_NOR_TEAHC_SHIFT	0
+#define FTIM0_NOR_TEAHC(n)	((n) << FTIM0_NOR_TEAHC_SHIFT)
+/*
+ * FTIM1 - NOR Flash Mode
+ */
+#define FTIM1_NOR			0xFF003F3F
+#define FTIM1_NOR_TACO_SHIFT	24
+#define FTIM1_NOR_TACO(n)	((n) << FTIM1_NOR_TACO_SHIFT)
+#define FTIM1_NOR_TRAD_NOR_SHIFT	8
+#define FTIM1_NOR_TRAD_NOR(n)	((n) << FTIM1_NOR_TRAD_NOR_SHIFT)
+#define FTIM1_NOR_TSEQRAD_NOR_SHIFT	0
+#define FTIM1_NOR_TSEQRAD_NOR(n)	((n) << FTIM1_NOR_TSEQRAD_NOR_SHIFT)
+/*
+ * FTIM2 - NOR Flash Mode
+ */
+#define FTIM2_NOR			0x0F3CFCFF
+#define FTIM2_NOR_TCS_SHIFT		24
+#define FTIM2_NOR_TCS(n)	((n) << FTIM2_NOR_TCS_SHIFT)
+#define FTIM2_NOR_TCH_SHIFT		18
+#define FTIM2_NOR_TCH(n)	((n) << FTIM2_NOR_TCH_SHIFT)
+#define FTIM2_NOR_TWPH_SHIFT	10
+#define FTIM2_NOR_TWPH(n)	((n) << FTIM2_NOR_TWPH_SHIFT)
+#define FTIM2_NOR_TWP_SHIFT		0
+#define FTIM2_NOR_TWP(n)	((n) << FTIM2_NOR_TWP_SHIFT)
+
+/*
+ * FTIM0 - Normal GPCM Mode
+ */
+#define FTIM0_GPCM			0xF03F3F3F
+#define FTIM0_GPCM_TACSE_SHIFT	28
+#define FTIM0_GPCM_TACSE(n)	((n) << FTIM0_GPCM_TACSE_SHIFT)
+#define FTIM0_GPCM_TEADC_SHIFT	16
+#define FTIM0_GPCM_TEADC(n)	((n) << FTIM0_GPCM_TEADC_SHIFT)
+#define FTIM0_GPCM_TAVDS_SHIFT	8
+#define FTIM0_GPCM_TAVDS(n)	((n) << FTIM0_GPCM_TAVDS_SHIFT)
+#define FTIM0_GPCM_TEAHC_SHIFT	0
+#define FTIM0_GPCM_TEAHC(n)	((n) << FTIM0_GPCM_TEAHC_SHIFT)
+/*
+ * FTIM1 - Normal GPCM Mode
+ */
+#define FTIM1_GPCM			0xFF003F00
+#define FTIM1_GPCM_TACO_SHIFT	24
+#define FTIM1_GPCM_TACO(n)	((n) << FTIM1_GPCM_TACO_SHIFT)
+#define FTIM1_GPCM_TRAD_SHIFT	8
+#define FTIM1_GPCM_TRAD(n)	((n) << FTIM1_GPCM_TRAD_SHIFT)
+/*
+ * FTIM2 - Normal GPCM Mode
+ */
+#define FTIM2_GPCM			0x0F3C00FF
+#define FTIM2_GPCM_TCS_SHIFT	24
+#define FTIM2_GPCM_TCS(n)	((n) << FTIM2_GPCM_TCS_SHIFT)
+#define FTIM2_GPCM_TCH_SHIFT	18
+#define FTIM2_GPCM_TCH(n)	((n) << FTIM2_GPCM_TCH_SHIFT)
+#define FTIM2_GPCM_TWP_SHIFT	0
+#define FTIM2_GPCM_TWP(n)	((n) << FTIM2_GPCM_TWP_SHIFT)
+
+/*
+ * Ready Busy Status Register (RB_STAT)
+ */
+/* CSn is READY */
+#define IFC_RB_STAT_READY_CS0		0x80000000
+#define IFC_RB_STAT_READY_CS1		0x40000000
+#define IFC_RB_STAT_READY_CS2		0x20000000
+#define IFC_RB_STAT_READY_CS3		0x10000000
+
+/*
+ * General Control Register (GCR)
+ */
+#define IFC_GCR_MASK			0x8000F800
+/* reset all IFC hardware */
+#define IFC_GCR_SOFT_RST_ALL		0x80000000
+/* Turnaroud Time of external buffer */
+#define IFC_GCR_TBCTL_TRN_TIME		0x0000F800
+#define IFC_GCR_TBCTL_TRN_TIME_SHIFT	11
+
+/*
+ * Common Event and Error Status Register (CM_EVTER_STAT)
+ */
+/* Chip select error */
+#define IFC_CM_EVTER_STAT_CSER		0x80000000
+
+/*
+ * Common Event and Error Enable Register (CM_EVTER_EN)
+ */
+/* Chip select error checking enable */
+#define IFC_CM_EVTER_EN_CSEREN		0x80000000
+
+/*
+ * Common Event and Error Interrupt Enable Register (CM_EVTER_INTR_EN)
+ */
+/* Chip select error interrupt enable */
+#define IFC_CM_EVTER_INTR_EN_CSERIREN	0x80000000
+
+/*
+ * Common Transfer Error Attribute Register-0 (CM_ERATTR0)
+ */
+/* transaction type of error Read/Write */
+#define IFC_CM_ERATTR0_ERTYP_READ	0x80000000
+#define IFC_CM_ERATTR0_ERAID		0x0FF00000
+#define IFC_CM_ERATTR0_ESRCID		0x0000FF00
+
+/*
+ * Clock Control Register (CCR)
+ */
+#define IFC_CCR_MASK			0x0F0F8800
+/* Clock division ratio */
+#define IFC_CCR_CLK_DIV_MASK		0x0F000000
+#define IFC_CCR_CLK_DIV_SHIFT		24
+#define IFC_CCR_CLK_DIV(n)		((n-1) << IFC_CCR_CLK_DIV_SHIFT)
+/* IFC Clock Delay */
+#define IFC_CCR_CLK_DLY_MASK		0x000F0000
+#define IFC_CCR_CLK_DLY_SHIFT		16
+#define IFC_CCR_CLK_DLY(n)		((n) << IFC_CCR_CLK_DLY_SHIFT)
+/* Invert IFC clock before sending out */
+#define IFC_CCR_INV_CLK_EN		0x00008000
+/* Fedback IFC Clock */
+#define IFC_CCR_FB_IFC_CLK_SEL		0x00000800
+
+/*
+ * Clock Status Register (CSR)
+ */
+/* Clk is stable */
+#define IFC_CSR_CLK_STAT_STABLE		0x80000000
+
+/*
+ * IFC_NAND Machine Specific Registers
+ */
+/*
+ * NAND Configuration Register (NCFGR)
+ */
+/* Auto Boot Mode */
+#define IFC_NAND_NCFGR_BOOT		0x80000000
+/* Addressing Mode-ROW0+n/COL0 */
+#define IFC_NAND_NCFGR_ADDR_MODE_RC0	0x00000000
+/* Addressing Mode-ROW0+n/COL0+n */
+#define IFC_NAND_NCFGR_ADDR_MODE_RC1	0x00400000
+/* Number of loop iterations of FIR sequences for multi page operations */
+#define IFC_NAND_NCFGR_NUM_LOOP_MASK	0x0000F000
+#define IFC_NAND_NCFGR_NUM_LOOP_SHIFT	12
+#define IFC_NAND_NCFGR_NUM_LOOP(n)	((n) << IFC_NAND_NCFGR_NUM_LOOP_SHIFT)
+/* Number of wait cycles */
+#define IFC_NAND_NCFGR_NUM_WAIT_MASK	0x000000FF
+#define IFC_NAND_NCFGR_NUM_WAIT_SHIFT	0
+
+/*
+ * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1)
+ */
+/* General purpose FCM flash command bytes CMD0-CMD7 */
+#define IFC_NAND_FCR0_CMD0		0xFF000000
+#define IFC_NAND_FCR0_CMD0_SHIFT	24
+#define IFC_NAND_FCR0_CMD1		0x00FF0000
+#define IFC_NAND_FCR0_CMD1_SHIFT	16
+#define IFC_NAND_FCR0_CMD2		0x0000FF00
+#define IFC_NAND_FCR0_CMD2_SHIFT	8
+#define IFC_NAND_FCR0_CMD3		0x000000FF
+#define IFC_NAND_FCR0_CMD3_SHIFT	0
+#define IFC_NAND_FCR1_CMD4		0xFF000000
+#define IFC_NAND_FCR1_CMD4_SHIFT	24
+#define IFC_NAND_FCR1_CMD5		0x00FF0000
+#define IFC_NAND_FCR1_CMD5_SHIFT	16
+#define IFC_NAND_FCR1_CMD6		0x0000FF00
+#define IFC_NAND_FCR1_CMD6_SHIFT	8
+#define IFC_NAND_FCR1_CMD7		0x000000FF
+#define IFC_NAND_FCR1_CMD7_SHIFT	0
+
+/*
+ * Flash ROW and COL Address Register (ROWn, COLn)
+ */
+/* Main/spare region locator */
+#define IFC_NAND_COL_MS			0x80000000
+/* Column Address */
+#define IFC_NAND_COL_CA_MASK		0x00000FFF
+
+/*
+ * NAND Flash Byte Count Register (NAND_BC)
+ */
+/* Byte Count for read/Write */
+#define IFC_NAND_BC			0x000001FF
+
+/*
+ * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2)
+ */
+/* NAND Machine specific opcodes OP0-OP14*/
+#define IFC_NAND_FIR0_OP0		0xFC000000
+#define IFC_NAND_FIR0_OP0_SHIFT		26
+#define IFC_NAND_FIR0_OP1		0x03F00000
+#define IFC_NAND_FIR0_OP1_SHIFT		20
+#define IFC_NAND_FIR0_OP2		0x000FC000
+#define IFC_NAND_FIR0_OP2_SHIFT		14
+#define IFC_NAND_FIR0_OP3		0x00003F00
+#define IFC_NAND_FIR0_OP3_SHIFT		8
+#define IFC_NAND_FIR0_OP4		0x000000FC
+#define IFC_NAND_FIR0_OP4_SHIFT		2
+#define IFC_NAND_FIR1_OP5		0xFC000000
+#define IFC_NAND_FIR1_OP5_SHIFT		26
+#define IFC_NAND_FIR1_OP6		0x03F00000
+#define IFC_NAND_FIR1_OP6_SHIFT		20
+#define IFC_NAND_FIR1_OP7		0x000FC000
+#define IFC_NAND_FIR1_OP7_SHIFT		14
+#define IFC_NAND_FIR1_OP8		0x00003F00
+#define IFC_NAND_FIR1_OP8_SHIFT		8
+#define IFC_NAND_FIR1_OP9		0x000000FC
+#define IFC_NAND_FIR1_OP9_SHIFT		2
+#define IFC_NAND_FIR2_OP10		0xFC000000
+#define IFC_NAND_FIR2_OP10_SHIFT	26
+#define IFC_NAND_FIR2_OP11		0x03F00000
+#define IFC_NAND_FIR2_OP11_SHIFT	20
+#define IFC_NAND_FIR2_OP12		0x000FC000
+#define IFC_NAND_FIR2_OP12_SHIFT	14
+#define IFC_NAND_FIR2_OP13		0x00003F00
+#define IFC_NAND_FIR2_OP13_SHIFT	8
+#define IFC_NAND_FIR2_OP14		0x000000FC
+#define IFC_NAND_FIR2_OP14_SHIFT	2
+
+/*
+ * Instruction opcodes to be programmed
+ * in FIR registers- 6bits
+ */
+enum ifc_nand_fir_opcodes {
+	IFC_FIR_OP_NOP,
+	IFC_FIR_OP_CA0,
+	IFC_FIR_OP_CA1,
+	IFC_FIR_OP_CA2,
+	IFC_FIR_OP_CA3,
+	IFC_FIR_OP_RA0,
+	IFC_FIR_OP_RA1,
+	IFC_FIR_OP_RA2,
+	IFC_FIR_OP_RA3,
+	IFC_FIR_OP_CMD0,
+	IFC_FIR_OP_CMD1,
+	IFC_FIR_OP_CMD2,
+	IFC_FIR_OP_CMD3,
+	IFC_FIR_OP_CMD4,
+	IFC_FIR_OP_CMD5,
+	IFC_FIR_OP_CMD6,
+	IFC_FIR_OP_CMD7,
+	IFC_FIR_OP_CW0,
+	IFC_FIR_OP_CW1,
+	IFC_FIR_OP_CW2,
+	IFC_FIR_OP_CW3,
+	IFC_FIR_OP_CW4,
+	IFC_FIR_OP_CW5,
+	IFC_FIR_OP_CW6,
+	IFC_FIR_OP_CW7,
+	IFC_FIR_OP_WBCD,
+	IFC_FIR_OP_RBCD,
+	IFC_FIR_OP_BTRD,
+	IFC_FIR_OP_RDSTAT,
+	IFC_FIR_OP_NWAIT,
+	IFC_FIR_OP_WFR,
+	IFC_FIR_OP_SBRD,
+	IFC_FIR_OP_UA,
+	IFC_FIR_OP_RB,
+};
+
+/*
+ * NAND Chip Select Register (NAND_CSEL)
+ */
+#define IFC_NAND_CSEL			0x0C000000
+#define IFC_NAND_CSEL_SHIFT		26
+#define IFC_NAND_CSEL_CS0		0x00000000
+#define IFC_NAND_CSEL_CS1		0x04000000
+#define IFC_NAND_CSEL_CS2		0x08000000
+#define IFC_NAND_CSEL_CS3		0x0C000000
+
+/*
+ * NAND Operation Sequence Start (NANDSEQ_STRT)
+ */
+/* NAND Flash Operation Start */
+#define IFC_NAND_SEQ_STRT_FIR_STRT	0x80000000
+/* Automatic Erase */
+#define IFC_NAND_SEQ_STRT_AUTO_ERS	0x00800000
+/* Automatic Program */
+#define IFC_NAND_SEQ_STRT_AUTO_PGM	0x00100000
+/* Automatic Copyback */
+#define IFC_NAND_SEQ_STRT_AUTO_CPB	0x00020000
+/* Automatic Read Operation */
+#define IFC_NAND_SEQ_STRT_AUTO_RD	0x00004000
+/* Automatic Status Read */
+#define IFC_NAND_SEQ_STRT_AUTO_STAT_RD	0x00000800
+
+/*
+ * NAND Event and Error Status Register (NAND_EVTER_STAT)
+ */
+/* Operation Complete */
+#define IFC_NAND_EVTER_STAT_OPC		0x80000000
+/* Flash Timeout Error */
+#define IFC_NAND_EVTER_STAT_FTOER	0x08000000
+/* Write Protect Error */
+#define IFC_NAND_EVTER_STAT_WPER	0x04000000
+/* ECC Error */
+#define IFC_NAND_EVTER_STAT_ECCER	0x02000000
+/* RCW Load Done */
+#define IFC_NAND_EVTER_STAT_RCW_DN	0x00008000
+/* Boot Loadr Done */
+#define IFC_NAND_EVTER_STAT_BOOT_DN	0x00004000
+/* Bad Block Indicator search select */
+#define IFC_NAND_EVTER_STAT_BBI_SRCH_SE	0x00000800
+
+/*
+ * NAND Flash Page Read Completion Event Status Register
+ * (PGRDCMPL_EVT_STAT)
+ */
+#define PGRDCMPL_EVT_STAT_MASK		0xFFFF0000
+/* Small Page 0-15 Done */
+#define PGRDCMPL_EVT_STAT_SECTION_SP(n)	(1 << (31 - (n)))
+/* Large Page(2K) 0-3 Done */
+#define PGRDCMPL_EVT_STAT_LP_2K(n)	(0xF << (28 - (n)*4))
+/* Large Page(4K) 0-1 Done */
+#define PGRDCMPL_EVT_STAT_LP_4K(n)	(0xFF << (24 - (n)*8))
+
+/*
+ * NAND Event and Error Enable Register (NAND_EVTER_EN)
+ */
+/* Operation complete event enable */
+#define IFC_NAND_EVTER_EN_OPC_EN	0x80000000
+/* Page read complete event enable */
+#define IFC_NAND_EVTER_EN_PGRDCMPL_EN	0x20000000
+/* Flash Timeout error enable */
+#define IFC_NAND_EVTER_EN_FTOER_EN	0x08000000
+/* Write Protect error enable */
+#define IFC_NAND_EVTER_EN_WPER_EN	0x04000000
+/* ECC error logging enable */
+#define IFC_NAND_EVTER_EN_ECCER_EN	0x02000000
+
+/*
+ * NAND Event and Error Interrupt Enable Register (NAND_EVTER_INTR_EN)
+ */
+/* Enable interrupt for operation complete */
+#define IFC_NAND_EVTER_INTR_OPCIR_EN		0x80000000
+/* Enable interrupt for Page read complete */
+#define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN	0x20000000
+/* Enable interrupt for Flash timeout error */
+#define IFC_NAND_EVTER_INTR_FTOERIR_EN		0x08000000
+/* Enable interrupt for Write protect error */
+#define IFC_NAND_EVTER_INTR_WPERIR_EN		0x04000000
+/* Enable interrupt for ECC error*/
+#define IFC_NAND_EVTER_INTR_ECCERIR_EN		0x02000000
+
+/*
+ * NAND Transfer Error Attribute Register-0 (NAND_ERATTR0)
+ */
+#define IFC_NAND_ERATTR0_MASK		0x0C080000
+/* Error on CS0-3 for NAND */
+#define IFC_NAND_ERATTR0_ERCS_CS0	0x00000000
+#define IFC_NAND_ERATTR0_ERCS_CS1	0x04000000
+#define IFC_NAND_ERATTR0_ERCS_CS2	0x08000000
+#define IFC_NAND_ERATTR0_ERCS_CS3	0x0C000000
+/* Transaction type of error Read/Write */
+#define IFC_NAND_ERATTR0_ERTTYPE_READ	0x00080000
+
+/*
+ * NAND Flash Status Register (NAND_FSR)
+ */
+/* First byte of data read from read status op */
+#define IFC_NAND_NFSR_RS0		0xFF000000
+/* Second byte of data read from read status op */
+#define IFC_NAND_NFSR_RS1		0x00FF0000
+
+/*
+ * ECC Error Status Registers (ECCSTAT0-ECCSTAT3)
+ */
+/* Number of ECC errors on sector n (n = 0-15) */
+#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK	0x0F000000
+#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_SHIFT	24
+#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK	0x000F0000
+#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_SHIFT	16
+#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK	0x00000F00
+#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_SHIFT	8
+#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK	0x0000000F
+#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT	0
+#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK	0x0F000000
+#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_SHIFT	24
+#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK	0x000F0000
+#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_SHIFT	16
+#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK	0x00000F00
+#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_SHIFT	8
+#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK	0x0000000F
+#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT	0
+#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK	0x0F000000
+#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_SHIFT	24
+#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK	0x000F0000
+#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_SHIFT	16
+#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK	0x00000F00
+#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_SHIFT	8
+#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK	0x0000000F
+#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT	0
+#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK	0x0F000000
+#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_SHIFT	24
+#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK	0x000F0000
+#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_SHIFT	16
+#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK	0x00000F00
+#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_SHIFT	8
+#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK	0x0000000F
+#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT	0
+
+/*
+ * NAND Control Register (NANDCR)
+ */
+#define IFC_NAND_NCR_FTOCNT_MASK	0x1E000000
+#define IFC_NAND_NCR_FTOCNT_SHIFT	25
+#define IFC_NAND_NCR_FTOCNT(n)	((_ilog2(n) - 8)  << IFC_NAND_NCR_FTOCNT_SHIFT)
+
+/*
+ * NAND_AUTOBOOT_TRGR
+ */
+/* Trigger RCW load */
+#define IFC_NAND_AUTOBOOT_TRGR_RCW_LD	0x80000000
+/* Trigget Auto Boot */
+#define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD	0x20000000
+
+/*
+ * NAND_MDR
+ */
+/* 1st read data byte when opcode SBRD */
+#define IFC_NAND_MDR_RDATA0		0xFF000000
+/* 2nd read data byte when opcode SBRD */
+#define IFC_NAND_MDR_RDATA1		0x00FF0000
+
+/*
+ * NOR Machine Specific Registers
+ */
+/*
+ * NOR Event and Error Status Register (NOR_EVTER_STAT)
+ */
+/* NOR Command Sequence Operation Complete */
+#define IFC_NOR_EVTER_STAT_OPC_NOR	0x80000000
+/* Write Protect Error */
+#define IFC_NOR_EVTER_STAT_WPER		0x04000000
+/* Command Sequence Timeout Error */
+#define IFC_NOR_EVTER_STAT_STOER	0x01000000
+
+/*
+ * NOR Event and Error Enable Register (NOR_EVTER_EN)
+ */
+/* NOR Command Seq complete event enable */
+#define IFC_NOR_EVTER_EN_OPCEN_NOR	0x80000000
+/* Write Protect Error Checking Enable */
+#define IFC_NOR_EVTER_EN_WPEREN		0x04000000
+/* Timeout Error Enable */
+#define IFC_NOR_EVTER_EN_STOEREN	0x01000000
+
+/*
+ * NOR Event and Error Interrupt Enable Register (NOR_EVTER_INTR_EN)
+ */
+/* Enable interrupt for OPC complete */
+#define IFC_NOR_EVTER_INTR_OPCEN_NOR	0x80000000
+/* Enable interrupt for write protect error */
+#define IFC_NOR_EVTER_INTR_WPEREN	0x04000000
+/* Enable interrupt for timeout error */
+#define IFC_NOR_EVTER_INTR_STOEREN	0x01000000
+
+/*
+ * NOR Transfer Error Attribute Register-0 (NOR_ERATTR0)
+ */
+/* Source ID for error transaction */
+#define IFC_NOR_ERATTR0_ERSRCID		0xFF000000
+/* AXI ID for error transation */
+#define IFC_NOR_ERATTR0_ERAID		0x000FF000
+/* Chip select corresponds to NOR error */
+#define IFC_NOR_ERATTR0_ERCS_CS0	0x00000000
+#define IFC_NOR_ERATTR0_ERCS_CS1	0x00000010
+#define IFC_NOR_ERATTR0_ERCS_CS2	0x00000020
+#define IFC_NOR_ERATTR0_ERCS_CS3	0x00000030
+/* Type of transaction read/write */
+#define IFC_NOR_ERATTR0_ERTYPE_READ	0x00000001
+
+/*
+ * NOR Transfer Error Attribute Register-2 (NOR_ERATTR2)
+ */
+#define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP	0x000F0000
+#define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER	0x00000F00
+
+/*
+ * NOR Control Register (NORCR)
+ */
+#define IFC_NORCR_MASK			0x0F0F0000
+/* No. of Address/Data Phase */
+#define IFC_NORCR_NUM_PHASE_MASK	0x0F000000
+#define IFC_NORCR_NUM_PHASE_SHIFT	24
+#define IFC_NORCR_NUM_PHASE(n)	((n-1) << IFC_NORCR_NUM_PHASE_SHIFT)
+/* Sequence Timeout Count */
+#define IFC_NORCR_STOCNT_MASK		0x000F0000
+#define IFC_NORCR_STOCNT_SHIFT		16
+#define IFC_NORCR_STOCNT(n)	((__ilog2(n) - 8) << IFC_NORCR_STOCNT_SHIFT)
+
+/*
+ * GPCM Machine specific registers
+ */
+/*
+ * GPCM Event and Error Status Register (GPCM_EVTER_STAT)
+ */
+/* Timeout error */
+#define IFC_GPCM_EVTER_STAT_TOER	0x04000000
+/* Parity error */
+#define IFC_GPCM_EVTER_STAT_PER		0x01000000
+
+/*
+ * GPCM Event and Error Enable Register (GPCM_EVTER_EN)
+ */
+/* Timeout error enable */
+#define IFC_GPCM_EVTER_EN_TOER_EN	0x04000000
+/* Parity error enable */
+#define IFC_GPCM_EVTER_EN_PER_EN	0x01000000
+
+/*
+ * GPCM Event and Error Interrupt Enable Register (GPCM_EVTER_INTR_EN)
+ */
+/* Enable Interrupt for timeout error */
+#define IFC_GPCM_EEIER_TOERIR_EN	0x04000000
+/* Enable Interrupt for Parity error */
+#define IFC_GPCM_EEIER_PERIR_EN		0x01000000
+
+/*
+ * GPCM Transfer Error Attribute Register-0 (GPCM_ERATTR0)
+ */
+/* Source ID for error transaction */
+#define IFC_GPCM_ERATTR0_ERSRCID	0xFF000000
+/* AXI ID for error transaction */
+#define IFC_GPCM_ERATTR0_ERAID		0x000FF000
+/* Chip select corresponds to GPCM error */
+#define IFC_GPCM_ERATTR0_ERCS_CS0	0x00000000
+#define IFC_GPCM_ERATTR0_ERCS_CS1	0x00000040
+#define IFC_GPCM_ERATTR0_ERCS_CS2	0x00000080
+#define IFC_GPCM_ERATTR0_ERCS_CS3	0x000000C0
+/* Type of transaction read/Write */
+#define IFC_GPCM_ERATTR0_ERTYPE_READ	0x00000001
+
+/*
+ * GPCM Transfer Error Attribute Register-2 (GPCM_ERATTR2)
+ */
+/* On which beat of address/data parity error is observed */
+#define IFC_GPCM_ERATTR2_PERR_BEAT		0x00000C00
+/* Parity Error on byte */
+#define IFC_GPCM_ERATTR2_PERR_BYTE		0x000000F0
+/* Parity Error reported in addr or data phase */
+#define IFC_GPCM_ERATTR2_PERR_DATA_PHASE	0x00000001
+
+/*
+ * GPCM Status Register (GPCM_STAT)
+ */
+#define IFC_GPCM_STAT_BSY		0x80000000  /* GPCM is busy */
+
+
+#ifndef __ASSEMBLY__
+#include <asm/io.h>
+
+extern void print_ifc_regs(void);
+extern void init_early_memctl_regs(void);
+void init_final_memctl_regs(void);
+
+#define IFC_BASE_ADDR ((struct fsl_ifc *)CONFIG_SYS_IFC_ADDR)
+
+#define get_ifc_cspr_ext(i) (ifc_in32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext))
+#define get_ifc_cspr(i) (ifc_in32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr))
+#define get_ifc_csor_ext(i) (ifc_in32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext))
+#define get_ifc_csor(i) (ifc_in32(&(IFC_BASE_ADDR)->csor_cs[i].csor))
+#define get_ifc_amask(i) (ifc_in32(&(IFC_BASE_ADDR)->amask_cs[i].amask))
+#define get_ifc_ftim(i, j) (ifc_in32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j]))
+
+#define set_ifc_cspr_ext(i, v) \
+			(ifc_out32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext, v))
+#define set_ifc_cspr(i, v) (ifc_out32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr, v))
+#define set_ifc_csor_ext(i, v) \
+			(ifc_out32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext, v))
+#define set_ifc_csor(i, v) (ifc_out32(&(IFC_BASE_ADDR)->csor_cs[i].csor, v))
+#define set_ifc_amask(i, v) (ifc_out32(&(IFC_BASE_ADDR)->amask_cs[i].amask, v))
+#define set_ifc_ftim(i, j, v) \
+			(ifc_out32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j], v))
+
+enum ifc_chip_sel {
+	IFC_CS0,
+	IFC_CS1,
+	IFC_CS2,
+	IFC_CS3,
+	IFC_CS4,
+	IFC_CS5,
+	IFC_CS6,
+	IFC_CS7,
+};
+
+enum ifc_ftims {
+	IFC_FTIM0,
+	IFC_FTIM1,
+	IFC_FTIM2,
+	IFC_FTIM3,
+};
+
+/*
+ * IFC Controller NAND Machine registers
+ */
+struct fsl_ifc_nand {
+	u32 ncfgr;
+	u32 res1[0x4];
+	u32 nand_fcr0;
+	u32 nand_fcr1;
+	u32 res2[0x8];
+	u32 row0;
+	u32 res3;
+	u32 col0;
+	u32 res4;
+	u32 row1;
+	u32 res5;
+	u32 col1;
+	u32 res6;
+	u32 row2;
+	u32 res7;
+	u32 col2;
+	u32 res8;
+	u32 row3;
+	u32 res9;
+	u32 col3;
+	u32 res10[0x24];
+	u32 nand_fbcr;
+	u32 res11;
+	u32 nand_fir0;
+	u32 nand_fir1;
+	u32 nand_fir2;
+	u32 res12[0x10];
+	u32 nand_csel;
+	u32 res13;
+	u32 nandseq_strt;
+	u32 res14;
+	u32 nand_evter_stat;
+	u32 res15;
+	u32 pgrdcmpl_evt_stat;
+	u32 res16[0x2];
+	u32 nand_evter_en;
+	u32 res17[0x2];
+	u32 nand_evter_intr_en;
+	u32 res18[0x2];
+	u32 nand_erattr0;
+	u32 nand_erattr1;
+	u32 res19[0x10];
+	u32 nand_fsr;
+	u32 res20;
+	u32 nand_eccstat[4];
+	u32 res21[0x20];
+	u32 nanndcr;
+	u32 res22[0x2];
+	u32 nand_autoboot_trgr;
+	u32 res23;
+	u32 nand_mdr;
+	u32 res24[0x5C];
+};
+
+/*
+ * IFC controller NOR Machine registers
+ */
+struct fsl_ifc_nor {
+	u32 nor_evter_stat;
+	u32 res1[0x2];
+	u32 nor_evter_en;
+	u32 res2[0x2];
+	u32 nor_evter_intr_en;
+	u32 res3[0x2];
+	u32 nor_erattr0;
+	u32 nor_erattr1;
+	u32 nor_erattr2;
+	u32 res4[0x4];
+	u32 norcr;
+	u32 res5[0xEF];
+};
+
+/*
+ * IFC controller GPCM Machine registers
+ */
+struct fsl_ifc_gpcm {
+	u32 gpcm_evter_stat;
+	u32 res1[0x2];
+	u32 gpcm_evter_en;
+	u32 res2[0x2];
+	u32 gpcm_evter_intr_en;
+	u32 res3[0x2];
+	u32 gpcm_erattr0;
+	u32 gpcm_erattr1;
+	u32 gpcm_erattr2;
+	u32 gpcm_stat;
+	u32 res4[0x1F3];
+};
+
+#ifdef CONFIG_SYS_FSL_IFC_BANK_COUNT
+#if (CONFIG_SYS_FSL_IFC_BANK_COUNT <= 8)
+#define IFC_CSPR_REG_LEN	148
+#define IFC_AMASK_REG_LEN	144
+#define IFC_CSOR_REG_LEN	144
+#define IFC_FTIM_REG_LEN	576
+
+#define IFC_CSPR_USED_LEN	sizeof(struct fsl_ifc_cspr) * \
+					CONFIG_SYS_FSL_IFC_BANK_COUNT
+#define IFC_AMASK_USED_LEN	sizeof(struct fsl_ifc_amask) * \
+					CONFIG_SYS_FSL_IFC_BANK_COUNT
+#define IFC_CSOR_USED_LEN	sizeof(struct fsl_ifc_csor) * \
+					CONFIG_SYS_FSL_IFC_BANK_COUNT
+#define IFC_FTIM_USED_LEN	sizeof(struct fsl_ifc_ftim) * \
+					CONFIG_SYS_FSL_IFC_BANK_COUNT
+#else
+#error IFC BANK count not vaild
+#endif
+#else
+#error IFC BANK count not defined
+#endif
+
+struct fsl_ifc_cspr {
+	u32 cspr_ext;
+	u32 cspr;
+	u32 res;
+};
+
+struct fsl_ifc_amask {
+	u32 amask;
+	u32 res[0x2];
+};
+
+struct fsl_ifc_csor {
+	u32 csor;
+	u32 csor_ext;
+	u32 res;
+};
+
+struct fsl_ifc_ftim {
+	u32 ftim[4];
+	u32 res[0x8];
+};
+
+/*
+ * IFC Controller Registers
+ */
+struct fsl_ifc {
+	u32 ifc_rev;
+	u32 res1[0x2];
+	struct fsl_ifc_cspr cspr_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
+	u8 res2[IFC_CSPR_REG_LEN - IFC_CSPR_USED_LEN];
+	struct fsl_ifc_amask amask_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
+	u8 res3[IFC_AMASK_REG_LEN - IFC_AMASK_USED_LEN];
+	struct fsl_ifc_csor csor_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
+	u8 res4[IFC_CSOR_REG_LEN - IFC_CSOR_USED_LEN];
+	struct fsl_ifc_ftim ftim_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
+	u8 res5[IFC_FTIM_REG_LEN - IFC_FTIM_USED_LEN];
+	u32 rb_stat;
+	u32 res6[0x2];
+	u32 ifc_gcr;
+	u32 res7[0x2];
+	u32 cm_evter_stat;
+	u32 res8[0x2];
+	u32 cm_evter_en;
+	u32 res9[0x2];
+	u32 cm_evter_intr_en;
+	u32 res10[0x2];
+	u32 cm_erattr0;
+	u32 cm_erattr1;
+	u32 res11[0x2];
+	u32 ifc_ccr;
+	u32 ifc_csr;
+	u32 res12[0x2EB];
+	struct fsl_ifc_nand ifc_nand;
+	struct fsl_ifc_nor ifc_nor;
+	struct fsl_ifc_gpcm ifc_gpcm;
+};
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769
+#undef CSPR_MSEL_NOR
+#define CSPR_MSEL_NOR	CSPR_MSEL_GPCM
+#endif
+#endif /* CONFIG_FSL_IFC */
+
+#endif /* __ASSEMBLY__ */
+#endif /* __FSL_IFC_H */
diff --git a/qemu/roms/u-boot/include/fsl_immap.h b/qemu/roms/u-boot/include/fsl_immap.h
new file mode 100644
index 000000000..d63cc19fa
--- /dev/null
+++ b/qemu/roms/u-boot/include/fsl_immap.h
@@ -0,0 +1,139 @@
+/*
+ * Common internal memory map for some Freescale SoCs
+ *
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __FSL_IMMAP_H
+#define __FSL_IMMAP_H
+/*
+ * DDR memory controller registers
+ * This structure works for mpc83xx (DDR2 and DDR3), mpc85xx, mpc86xx.
+ */
+struct ccsr_ddr {
+	u32	cs0_bnds;		/* Chip Select 0 Memory Bounds */
+	u8	res_04[4];
+	u32	cs1_bnds;		/* Chip Select 1 Memory Bounds */
+	u8	res_0c[4];
+	u32	cs2_bnds;		/* Chip Select 2 Memory Bounds */
+	u8	res_14[4];
+	u32	cs3_bnds;		/* Chip Select 3 Memory Bounds */
+	u8	res_1c[100];
+	u32	cs0_config;		/* Chip Select Configuration */
+	u32	cs1_config;		/* Chip Select Configuration */
+	u32	cs2_config;		/* Chip Select Configuration */
+	u32	cs3_config;		/* Chip Select Configuration */
+	u8	res_90[48];
+	u32	cs0_config_2;		/* Chip Select Configuration 2 */
+	u32	cs1_config_2;		/* Chip Select Configuration 2 */
+	u32	cs2_config_2;		/* Chip Select Configuration 2 */
+	u32	cs3_config_2;		/* Chip Select Configuration 2 */
+	u8	res_d0[48];
+	u32	timing_cfg_3;		/* SDRAM Timing Configuration 3 */
+	u32	timing_cfg_0;		/* SDRAM Timing Configuration 0 */
+	u32	timing_cfg_1;		/* SDRAM Timing Configuration 1 */
+	u32	timing_cfg_2;		/* SDRAM Timing Configuration 2 */
+	u32	sdram_cfg;		/* SDRAM Control Configuration */
+	u32	sdram_cfg_2;		/* SDRAM Control Configuration 2 */
+	u32	sdram_mode;		/* SDRAM Mode Configuration */
+	u32	sdram_mode_2;		/* SDRAM Mode Configuration 2 */
+	u32	sdram_md_cntl;		/* SDRAM Mode Control */
+	u32	sdram_interval;		/* SDRAM Interval Configuration */
+	u32	sdram_data_init;	/* SDRAM Data initialization */
+	u8	res_12c[4];
+	u32	sdram_clk_cntl;		/* SDRAM Clock Control */
+	u8	res_134[20];
+	u32	init_addr;		/* training init addr */
+	u32	init_ext_addr;		/* training init extended addr */
+	u8	res_150[16];
+	u32	timing_cfg_4;		/* SDRAM Timing Configuration 4 */
+	u32	timing_cfg_5;		/* SDRAM Timing Configuration 5 */
+	u32	timing_cfg_6;		/* SDRAM Timing Configuration 6 */
+	u32	timing_cfg_7;		/* SDRAM Timing Configuration 7 */
+	u32	ddr_zq_cntl;		/* ZQ calibration control*/
+	u32	ddr_wrlvl_cntl;		/* write leveling control*/
+	u8	reg_178[4];
+	u32	ddr_sr_cntr;		/* self refresh counter */
+	u32	ddr_sdram_rcw_1;	/* Control Words 1 */
+	u32	ddr_sdram_rcw_2;	/* Control Words 2 */
+	u8	reg_188[8];
+	u32	ddr_wrlvl_cntl_2;	/* write leveling control 2 */
+	u32	ddr_wrlvl_cntl_3;	/* write leveling control 3 */
+	u8	res_198[0x1a0-0x198];
+	u32	ddr_sdram_rcw_3;
+	u32	ddr_sdram_rcw_4;
+	u32	ddr_sdram_rcw_5;
+	u32	ddr_sdram_rcw_6;
+	u8	res_1b0[0x200-0x1b0];
+	u32	sdram_mode_3;		/* SDRAM Mode Configuration 3 */
+	u32	sdram_mode_4;		/* SDRAM Mode Configuration 4 */
+	u32	sdram_mode_5;		/* SDRAM Mode Configuration 5 */
+	u32	sdram_mode_6;		/* SDRAM Mode Configuration 6 */
+	u32	sdram_mode_7;		/* SDRAM Mode Configuration 7 */
+	u32	sdram_mode_8;		/* SDRAM Mode Configuration 8 */
+	u8	res_218[0x220-0x218];
+	u32	sdram_mode_9;		/* SDRAM Mode Configuration 9 */
+	u32	sdram_mode_10;		/* SDRAM Mode Configuration 10 */
+	u32	sdram_mode_11;		/* SDRAM Mode Configuration 11 */
+	u32	sdram_mode_12;		/* SDRAM Mode Configuration 12 */
+	u32	sdram_mode_13;		/* SDRAM Mode Configuration 13 */
+	u32	sdram_mode_14;		/* SDRAM Mode Configuration 14 */
+	u32	sdram_mode_15;		/* SDRAM Mode Configuration 15 */
+	u32	sdram_mode_16;		/* SDRAM Mode Configuration 16 */
+	u8	res_240[0x250-0x240];
+	u32	timing_cfg_8;		/* SDRAM Timing Configuration 8 */
+	u32	timing_cfg_9;		/* SDRAM Timing Configuration 9 */
+	u8	res_258[0x260-0x258];
+	u32	sdram_cfg_3;
+	u8	res_264[0x2a0-0x264];
+	u32	deskew_cntl;
+	u8	res_2a4[0x400-0x2a4];
+	u32	dq_map_0;
+	u32	dq_map_1;
+	u32	dq_map_2;
+	u32	dq_map_3;
+	u8	res_410[0xb20-0x410];
+	u32	ddr_dsr1;		/* Debug Status 1 */
+	u32	ddr_dsr2;		/* Debug Status 2 */
+	u32	ddr_cdr1;		/* Control Driver 1 */
+	u32	ddr_cdr2;		/* Control Driver 2 */
+	u8	res_b30[200];
+	u32	ip_rev1;		/* IP Block Revision 1 */
+	u32	ip_rev2;		/* IP Block Revision 2 */
+	u32	eor;			/* Enhanced Optimization Register */
+	u8	res_c04[252];
+	u32	mtcr;			/* Memory Test Control Register */
+	u8	res_d04[28];
+	u32	mtp1;			/* Memory Test Pattern 1 */
+	u32	mtp2;			/* Memory Test Pattern 2 */
+	u32	mtp3;			/* Memory Test Pattern 3 */
+	u32	mtp4;			/* Memory Test Pattern 4 */
+	u32	mtp5;			/* Memory Test Pattern 5 */
+	u32	mtp6;			/* Memory Test Pattern 6 */
+	u32	mtp7;			/* Memory Test Pattern 7 */
+	u32	mtp8;			/* Memory Test Pattern 8 */
+	u32	mtp9;			/* Memory Test Pattern 9 */
+	u32	mtp10;			/* Memory Test Pattern 10 */
+	u8	res_d48[184];
+	u32	data_err_inject_hi;	/* Data Path Err Injection Mask High */
+	u32	data_err_inject_lo;	/* Data Path Err Injection Mask Low */
+	u32	ecc_err_inject;		/* Data Path Err Injection Mask ECC */
+	u8	res_e0c[20];
+	u32	capture_data_hi;	/* Data Path Read Capture High */
+	u32	capture_data_lo;	/* Data Path Read Capture Low */
+	u32	capture_ecc;		/* Data Path Read Capture ECC */
+	u8	res_e2c[20];
+	u32	err_detect;		/* Error Detect */
+	u32	err_disable;		/* Error Disable */
+	u32	err_int_en;
+	u32	capture_attributes;	/* Error Attrs Capture */
+	u32	capture_address;	/* Error Addr Capture */
+	u32	capture_ext_address;	/* Error Extended Addr Capture */
+	u32	err_sbe;		/* Single-Bit ECC Error Management */
+	u8	res_e5c[164];
+	u32	debug[32];		/* debug_1 to debug_32 */
+	u8	res_f80[128];
+};
+#endif /* __FSL_IMMAP_H */
diff --git a/qemu/roms/u-boot/include/fsl_mdio.h b/qemu/roms/u-boot/include/fsl_mdio.h
new file mode 100644
index 000000000..b58713d89
--- /dev/null
+++ b/qemu/roms/u-boot/include/fsl_mdio.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2009-2012, 2013 Freescale Semiconductor, Inc.
+ *	Jun-jie Zhang <b18070@freescale.com>
+ *	Mingkai Hu <Mingkai.hu@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __FSL_PHY_H__
+#define __FSL_PHY_H__
+
+#include <net.h>
+#include <miiphy.h>
+#include <asm/fsl_enet.h>
+
+/* PHY register offsets */
+#define PHY_EXT_PAGE_ACCESS	0x1f
+
+/* MII Management Configuration Register */
+#define MIIMCFG_RESET_MGMT          0x80000000
+#define MIIMCFG_MGMT_CLOCK_SELECT   0x00000007
+#define MIIMCFG_INIT_VALUE	    0x00000003
+
+/* MII Management Command Register */
+#define MIIMCOM_READ_CYCLE	0x00000001
+#define MIIMCOM_SCAN_CYCLE	0x00000002
+
+/* MII Management Address Register */
+#define MIIMADD_PHY_ADDR_SHIFT	8
+
+/* MII Management Indicator Register */
+#define MIIMIND_BUSY		0x00000001
+#define MIIMIND_NOTVALID	0x00000004
+
+void tsec_local_mdio_write(struct tsec_mii_mng __iomem *phyregs, int port_addr,
+		int dev_addr, int reg, int value);
+int tsec_local_mdio_read(struct tsec_mii_mng __iomem *phyregs, int port_addr,
+		int dev_addr, int regnum);
+int tsec_phy_read(struct mii_dev *bus, int addr, int dev_addr, int regnum);
+int tsec_phy_write(struct mii_dev *bus, int addr, int dev_addr, int regnum,
+		u16 value);
+int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
+		int regnum, u16 value);
+int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
+		int regnum);
+
+struct fsl_pq_mdio_info {
+	struct tsec_mii_mng __iomem *regs;
+	char *name;
+};
+int fsl_pq_mdio_init(bd_t *bis, struct fsl_pq_mdio_info *info);
+
+#endif /* __FSL_PHY_H__ */
diff --git a/qemu/roms/u-boot/include/fsl_pmic.h b/qemu/roms/u-boot/include/fsl_pmic.h
new file mode 100644
index 000000000..e8a67d552
--- /dev/null
+++ b/qemu/roms/u-boot/include/fsl_pmic.h
@@ -0,0 +1,120 @@
+/*
+ * (C) Copyright 2010
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __FSL_PMIC_H__
+#define __FSL_PMIC_H__
+
+/*
+ * The registers of different PMIC has the same meaning
+ * but the bit positions of the fields can differ or
+ * some fields has a meaning only on some devices.
+ * You have to check with the internal SPI bitmap
+ * (see Freescale Documentation) to set the registers
+ * for the device you are using
+ */
+enum {
+	REG_INT_STATUS0 = 0,
+	REG_INT_MASK0,
+	REG_INT_SENSE0,
+	REG_INT_STATUS1,
+	REG_INT_MASK1,
+	REG_INT_SENSE1,
+	REG_PU_MODE_S,
+	REG_IDENTIFICATION,
+	REG_UNUSED0,
+	REG_ACC0,
+	REG_ACC1,		/*10 */
+	REG_UNUSED1,
+	REG_UNUSED2,
+	REG_POWER_CTL0,
+	REG_POWER_CTL1,
+	REG_POWER_CTL2,
+	REG_REGEN_ASSIGN,
+	REG_UNUSED3,
+	REG_MEM_A,
+	REG_MEM_B,
+	REG_RTC_TIME,		/*20 */
+	REG_RTC_ALARM,
+	REG_RTC_DAY,
+	REG_RTC_DAY_ALARM,
+	REG_SW_0,
+	REG_SW_1,
+	REG_SW_2,
+	REG_SW_3,
+	REG_SW_4,
+	REG_SW_5,
+	REG_SETTING_0,		/*30 */
+	REG_SETTING_1,
+	REG_MODE_0,
+	REG_MODE_1,
+	REG_POWER_MISC,
+	REG_UNUSED4,
+	REG_UNUSED5,
+	REG_UNUSED6,
+	REG_UNUSED7,
+	REG_UNUSED8,
+	REG_UNUSED9,		/*40 */
+	REG_UNUSED10,
+	REG_UNUSED11,
+	REG_ADC0,
+	REG_ADC1,
+	REG_ADC2,
+	REG_ADC3,
+	REG_ADC4,
+	REG_CHARGE,
+	REG_USB0,
+	REG_USB1,		/*50 */
+	REG_LED_CTL0,
+	REG_LED_CTL1,
+	REG_LED_CTL2,
+	REG_LED_CTL3,
+	REG_UNUSED12,
+	REG_UNUSED13,
+	REG_TRIM0,
+	REG_TRIM1,
+	REG_TEST0,
+	REG_TEST1,		/*60 */
+	REG_TEST2,
+	REG_TEST3,
+	REG_TEST4,
+	PMIC_NUM_OF_REGS,
+};
+
+/* REG_POWER_MISC */
+#define GPO1EN		(1 << 6)
+#define GPO1STBY	(1 << 7)
+#define GPO2EN		(1 << 8)
+#define GPO2STBY	(1 << 9)
+#define GPO3EN		(1 << 10)
+#define GPO3STBY	(1 << 11)
+#define GPO4EN		(1 << 12)
+#define GPO4STBY	(1 << 13)
+#define PWGT1SPIEN	(1 << 15)
+#define PWGT2SPIEN	(1 << 16)
+#define PWUP		(1 << 21)
+
+/* Power Control 0 */
+#define COINCHEN	(1 << 23)
+#define BATTDETEN	(1 << 19)
+
+/* Interrupt status 1 */
+#define RTCRSTI		(1 << 7)
+
+/* MC34708 Definitions */
+#define SWx_VOLT_MASK_MC34708	0x3F
+#define SWx_1_250V_MC34708	0x30
+#define SWx_1_300V_MC34708	0x34
+#define TIMER_MASK_MC34708	0x300
+#define TIMER_4S_MC34708	0x100
+#define VUSBSEL_MC34708		(1 << 2)
+#define VUSBEN_MC34708		(1 << 3)
+#define SWBST_CTRL		31
+#define SWBST_AUTO		0x8
+
+#endif
diff --git a/qemu/roms/u-boot/include/fsl_usb.h b/qemu/roms/u-boot/include/fsl_usb.h
new file mode 100644
index 000000000..1a6c9c163
--- /dev/null
+++ b/qemu/roms/u-boot/include/fsl_usb.h
@@ -0,0 +1,88 @@
+/*
+ * Freescale USB Controller
+ *
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_FSL_USB_H_
+#define _ASM_FSL_USB_H_
+
+#ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
+struct ccsr_usb_port_ctrl {
+	u32	ctrl;
+	u32	drvvbuscfg;
+	u32	pwrfltcfg;
+	u32	sts;
+	u8	res_14[0xc];
+	u32	bistcfg;
+	u32	biststs;
+	u32	abistcfg;
+	u32	abiststs;
+	u8	res_30[0x10];
+	u32	xcvrprg;
+	u32	anaprg;
+	u32	anadrv;
+	u32	anasts;
+};
+
+struct ccsr_usb_phy {
+	u32	id;
+	struct ccsr_usb_port_ctrl port1;
+	u8	res_50[0xc];
+	u32	tvr;
+	u32	pllprg[4];
+	u8	res_70[0x4];
+	u32	anaccfg;
+	u32	dbg;
+	u8	res_7c[0x4];
+	struct ccsr_usb_port_ctrl port2;
+	u8	res_dc[0x334];
+};
+
+#define CONFIG_SYS_FSL_USB_CTRL_PHY_EN (1 << 0)
+#define CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN (1 << 1)
+#define CONFIG_SYS_FSL_USB_PWRFLT_CR_EN (1 << 1)
+#define CONFIG_SYS_FSL_USB_PLLPRG1_PHY_DIV (1 << 0)
+#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN (1 << 0)
+#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN (1 << 1)
+#define CONFIG_SYS_FSL_USB_PLLPRG2_FRAC_LPF_EN (1 << 13)
+#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+#define CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK (5 << 4)
+#define CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK (6 << 16)
+#define CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN (1 << 20)
+#endif
+#define CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV (1 << 4)
+#define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16)
+#define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21)
+#define CONFIG_SYS_FSL_USB_SYS_CLK_VALID (1 << 0)
+#define CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN (1 << 7)
+#define CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK (3 << 4)
+
+#define INC_DCNT_THRESHOLD_25MV        (0 << 4)
+#define INC_DCNT_THRESHOLD_50MV        (1 << 4)
+#define DEC_DCNT_THRESHOLD_25MV        (2 << 4)
+#define DEC_DCNT_THRESHOLD_50MV        (3 << 4)
+#else
+struct ccsr_usb_phy {
+	u32     config1;
+	u32     config2;
+	u32     config3;
+	u32     config4;
+	u32     config5;
+	u32     status1;
+	u32	usb_enable_override;
+	u8	res[0xe4];
+};
+#define CONFIG_SYS_FSL_USB_HS_DISCNCT_INC (3 << 22)
+#define CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL (1 << 20)
+#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0 13
+#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3 16
+#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0 0
+#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3 3
+#define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1
+#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK 0x07
+#endif
+
+#endif /*_ASM_FSL_USB_H_ */
diff --git a/qemu/roms/u-boot/include/fuse.h b/qemu/roms/u-boot/include/fuse.h
new file mode 100644
index 000000000..87ee17d34
--- /dev/null
+++ b/qemu/roms/u-boot/include/fuse.h
@@ -0,0 +1,28 @@
+/*
+ * (C) Copyright 2009-2013 ADVANSEE
+ * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
+ *
+ * Based on the mpc512x iim code:
+ * Copyright 2008 Silicon Turnkey Express, Inc.
+ * Martha Marx <mmarx@silicontkx.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _FUSE_H_
+#define _FUSE_H_
+
+/*
+ * Read/Sense/Program/Override interface:
+ *   bank:    Fuse bank
+ *   word:    Fuse word within the bank
+ *   val:     Value to read/write
+ *
+ *   Returns: 0 on success, not 0 on failure
+ */
+int fuse_read(u32 bank, u32 word, u32 *val);
+int fuse_sense(u32 bank, u32 word, u32 *val);
+int fuse_prog(u32 bank, u32 word, u32 val);
+int fuse_override(u32 bank, u32 word, u32 val);
+
+#endif	/* _FUSE_H_ */
diff --git a/qemu/roms/u-boot/include/g_dnl.h b/qemu/roms/u-boot/include/g_dnl.h
new file mode 100644
index 000000000..1b1b35e0e
--- /dev/null
+++ b/qemu/roms/u-boot/include/g_dnl.h
@@ -0,0 +1,42 @@
+/*
+ *  Copyright (C) 2012 Samsung Electronics
+ *  Lukasz Majewski <l.majewski@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __G_DOWNLOAD_H_
+#define __G_DOWNLOAD_H_
+
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <linux/usb/composite.h>
+#include <linker_lists.h>
+
+/*
+ * @usb_fname: unescaped USB function name
+ * @callback_ptr: bind callback, one per function name
+ */
+#define DECLARE_GADGET_BIND_CALLBACK(usb_fname, callback_ptr) \
+	ll_entry_declare(struct g_dnl_bind_callback, \
+			__usb_function_name_##usb_fname, \
+			g_dnl_bind_callbacks) = { \
+				.usb_function_name = #usb_fname, \
+				.fptr = callback_ptr \
+			}
+
+typedef int (*g_dnl_bind_callback_f)(struct usb_configuration *);
+
+/* used in Gadget downloader callback linker list */
+struct g_dnl_bind_callback {
+	const char *usb_function_name;
+	g_dnl_bind_callback_f fptr;
+};
+
+int g_dnl_bind_fixup(struct usb_device_descriptor *, const char *);
+int g_dnl_board_usb_cable_connected(void);
+int g_dnl_register(const char *s);
+void g_dnl_unregister(void);
+void g_dnl_set_serialnumber(char *);
+
+#endif /* __G_DOWNLOAD_H_ */
diff --git a/qemu/roms/u-boot/include/galileo/core.h b/qemu/roms/u-boot/include/galileo/core.h
new file mode 100644
index 000000000..95013fac2
--- /dev/null
+++ b/qemu/roms/u-boot/include/galileo/core.h
@@ -0,0 +1,217 @@
+/* Core.h - Basic core logic functions and definitions */
+
+/* Copyright Galileo Technology. */
+
+/*
+DESCRIPTION
+This header file contains simple read/write macros for addressing
+the SDRAM, devices, GT`s internal registers and PCI (using the PCI`s address
+space). The macros take care of Big/Little endian conversions.
+*/
+
+#ifndef __INCcoreh
+#define __INCcoreh
+
+/* includes */
+#include "gt64260R.h"
+#include <stdbool.h>
+
+extern unsigned int INTERNAL_REG_BASE_ADDR;
+
+/*
+ * GT-6426x variants
+ */
+#define GT_64260	0  /* includes both 64260A and 64260B */
+#define GT_64261	1
+
+#if (CONFIG_SYS_GT_6426x == GT_64260)
+#ifdef CONFIG_ETHER_PORT_MII
+#define GAL_ETH_DEVS 2
+#else
+#define GAL_ETH_DEVS 3
+#endif
+#elif (CONFIG_SYS_GT_6426x == GT_64261)
+#define GAL_ETH_DEVS 2
+#else
+#define GAL_ETH_DEVS 3	/* default to a 64260 */
+#endif
+
+/****************************************/
+/*          GENERAL Definitions			*/
+/****************************************/
+
+#define NO_BIT          0x00000000
+#define BIT0            0x00000001
+#define BIT1            0x00000002
+#define BIT2            0x00000004
+#define BIT3            0x00000008
+#define BIT4            0x00000010
+#define BIT5            0x00000020
+#define BIT6            0x00000040
+#define BIT7            0x00000080
+#define BIT8            0x00000100
+#define BIT9            0x00000200
+#define BIT10           0x00000400
+#define BIT11           0x00000800
+#define BIT12           0x00001000
+#define BIT13           0x00002000
+#define BIT14           0x00004000
+#define BIT15           0x00008000
+#define BIT16           0x00010000
+#define BIT17           0x00020000
+#define BIT18           0x00040000
+#define BIT19           0x00080000
+#define BIT20           0x00100000
+#define BIT21           0x00200000
+#define BIT22           0x00400000
+#define BIT23           0x00800000
+#define BIT24           0x01000000
+#define BIT25           0x02000000
+#define BIT26           0x04000000
+#define BIT27           0x08000000
+#define BIT28           0x10000000
+#define BIT29           0x20000000
+#define BIT30           0x40000000
+#define BIT31           0x80000000
+
+#define _1K             0x00000400
+#define _2K             0x00000800
+#define _4K             0x00001000
+#define _8K             0x00002000
+#define _16K            0x00004000
+#define _32K            0x00008000
+#define _64K            0x00010000
+#define _128K           0x00020000
+#define _256K           0x00040000
+#define _512K           0x00080000
+
+#define _1M             0x00100000
+#define _2M             0x00200000
+#define _3M             0x00300000
+#define _4M             0x00400000
+#define _5M             0x00500000
+#define _6M             0x00600000
+#define _7M             0x00700000
+#define _8M             0x00800000
+#define _9M             0x00900000
+#define _10M            0x00a00000
+#define _11M            0x00b00000
+#define _12M            0x00c00000
+#define _13M            0x00d00000
+#define _14M            0x00e00000
+#define _15M            0x00f00000
+#define _16M            0x01000000
+
+#define _32M            0x02000000
+#define _64M            0x04000000
+#define _128M           0x08000000
+#define _256M           0x10000000
+#define _512M           0x20000000
+
+#define _1G             0x40000000
+#define _2G             0x80000000
+
+/* Little to Big endian conversion macros */
+
+#ifdef LE /* Little Endian */
+#define SHORT_SWAP(X) (X)
+#define WORD_SWAP(X) (X)
+#define LONG_SWAP(X) ((l64)(X))
+
+#else    /* Big Endian */
+#define SHORT_SWAP(X) ((X <<8 ) | (X >> 8))
+
+#define WORD_SWAP(X) (((X)&0xff)<<24)+      \
+		    (((X)&0xff00)<<8)+      \
+		    (((X)&0xff0000)>>8)+    \
+		    (((X)&0xff000000)>>24)
+
+#define LONG_SWAP(X) ( (l64) (((X)&0xffULL)<<56)+               \
+			    (((X)&0xff00ULL)<<40)+              \
+			    (((X)&0xff0000ULL)<<24)+            \
+			    (((X)&0xff000000ULL)<<8)+           \
+			    (((X)&0xff00000000ULL)>>8)+         \
+			    (((X)&0xff0000000000ULL)>>24)+      \
+			    (((X)&0xff000000000000ULL)>>40)+    \
+			    (((X)&0xff00000000000000ULL)>>56))
+
+#endif
+
+#ifndef NULL
+#define NULL 0
+#endif
+
+/* Those two definitions were defined to be compatible with MIPS */
+#define NONE_CACHEABLE		0x00000000
+#define CACHEABLE			0x00000000
+
+/* 750 cache line */
+#define CACHE_LINE_SIZE 32
+#define CACHELINE_MASK_BITS (CACHE_LINE_SIZE - 1)
+#define CACHELINE_ROUNDUP(A) (((A)+CACHELINE_MASK_BITS) & ~CACHELINE_MASK_BITS)
+
+/* Read/Write to/from GT`s internal registers */
+#define GT_REG_READ(offset, pData)                                          \
+*pData = ( *((volatile unsigned int *)(NONE_CACHEABLE |                     \
+		INTERNAL_REG_BASE_ADDR | (offset))) ) ;                                              \
+*pData = WORD_SWAP(*pData)
+
+#define GTREGREAD(offset)                                                   \
+	 (WORD_SWAP( *((volatile unsigned int *)(NONE_CACHEABLE |            \
+		   INTERNAL_REG_BASE_ADDR | (offset))) ))
+
+#define GT_REG_WRITE(offset, data)                                          \
+*((unsigned int *)( INTERNAL_REG_BASE_ADDR | (offset))) =                   \
+		    WORD_SWAP(data)
+
+/* Write 32/16/8 bit */
+#define WRITE_CHAR(address, data)                                           \
+	*((unsigned char *)(address)) = data
+#define WRITE_SHORT(address, data)                                          \
+	*((unsigned short *)(address)) = data
+#define WRITE_WORD(address, data)                                           \
+	*((unsigned int *)(address)) = data
+
+/* Read 32/16/8 bits - returns data in variable. */
+#define READ_CHAR(address, pData)                                           \
+	*pData = *((volatile unsigned char *)(address))
+
+#define READ_SHORT(address, pData)                                          \
+	*pData = *((volatile unsigned short *)(address))
+
+#define READ_WORD(address, pData)                                           \
+	*pData = *((volatile unsigned int *)(address))
+
+/* Read 32/16/8 bit - returns data direct. */
+#define READCHAR(address)                                                   \
+	*((volatile unsigned char *)((address) | NONE_CACHEABLE))
+
+#define READSHORT(address)                                                  \
+	*((volatile unsigned short *)((address) | NONE_CACHEABLE))
+
+#define READWORD(address)                                                   \
+	*((volatile unsigned int *)((address) | NONE_CACHEABLE))
+
+/* Those two Macros were defined to be compatible with MIPS */
+#define VIRTUAL_TO_PHY(x)    (((unsigned int)x) & 0xffffffff)
+#define PHY_TO_VIRTUAL(x)    (((unsigned int)x) | NONE_CACHEABLE)
+
+/*  SET_REG_BITS(regOffset,bits) -
+   gets register offset and bits: a 32bit value. It set to logic '1' in the
+   internal register the bits which given as an input example:
+   SET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic
+   '1' in register 0x840 while the other bits stays as is. */
+#define SET_REG_BITS(regOffset,bits) \
+	*(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR |  \
+	regOffset) |= (unsigned int)WORD_SWAP(bits)
+
+/*  RESET_REG_BITS(regOffset,bits) -
+   gets register offset and bits: a 32bit value. It set to logic '0' in the
+   internal register the bits which given as an input example:
+   RESET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic
+   '0' in register 0x840 while the other bits stays as is. */
+#define RESET_REG_BITS(regOffset,bits) \
+	*(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR   \
+	| regOffset) &= ~( (unsigned int)WORD_SWAP(bits) )
+
+#endif /* __INCcoreh */
diff --git a/qemu/roms/u-boot/include/galileo/gt64260R.h b/qemu/roms/u-boot/include/galileo/gt64260R.h
new file mode 100644
index 000000000..b55da9d35
--- /dev/null
+++ b/qemu/roms/u-boot/include/galileo/gt64260R.h
@@ -0,0 +1,1194 @@
+/* gt64260R.h - GT64260 Internal registers definition file */
+
+/* Copyright - Galileo technology. */
+
+#ifndef __INCgt64260rh
+#define __INCgt64260rh
+
+#ifndef GT64260
+#define GT64260
+#endif
+
+/* CPU MASTER CONTROL REGISTER */
+#define	CPU_CONFIGURATION	0x0
+#define	CPU_MASTER_CONTROL	0x160
+
+/****************************************/
+/* Processor Address Space		*/
+/****************************************/
+
+/* Sdram's BAR'S */
+#define SCS_0_LOW_DECODE_ADDRESS			0x008
+#define SCS_0_HIGH_DECODE_ADDRESS			0x010
+#define SCS_1_LOW_DECODE_ADDRESS			0x208
+#define SCS_1_HIGH_DECODE_ADDRESS			0x210
+#define SCS_2_LOW_DECODE_ADDRESS			0x018
+#define SCS_2_HIGH_DECODE_ADDRESS			0x020
+#define SCS_3_LOW_DECODE_ADDRESS			0x218
+#define SCS_3_HIGH_DECODE_ADDRESS			0x220
+/* Devices BAR'S */
+#define CS_0_LOW_DECODE_ADDRESS				0x028
+#define CS_0_HIGH_DECODE_ADDRESS			0x030
+#define CS_1_LOW_DECODE_ADDRESS				0x228
+#define CS_1_HIGH_DECODE_ADDRESS			0x230
+#define CS_2_LOW_DECODE_ADDRESS				0x248
+#define CS_2_HIGH_DECODE_ADDRESS			0x250
+#define CS_3_LOW_DECODE_ADDRESS				0x038
+#define CS_3_HIGH_DECODE_ADDRESS			0x040
+#define BOOTCS_LOW_DECODE_ADDRESS			0x238
+#define BOOTCS_HIGH_DECODE_ADDRESS			0x240
+
+#define PCI_0I_O_LOW_DECODE_ADDRESS			0x048
+#define PCI_0I_O_HIGH_DECODE_ADDRESS			0x050
+#define PCI_0MEMORY0_LOW_DECODE_ADDRESS			0x058
+#define PCI_0MEMORY0_HIGH_DECODE_ADDRESS		0x060
+#define PCI_0MEMORY1_LOW_DECODE_ADDRESS			0x080
+#define PCI_0MEMORY1_HIGH_DECODE_ADDRESS		0x088
+#define PCI_0MEMORY2_LOW_DECODE_ADDRESS			0x258
+#define PCI_0MEMORY2_HIGH_DECODE_ADDRESS		0x260
+#define PCI_0MEMORY3_LOW_DECODE_ADDRESS			0x280
+#define PCI_0MEMORY3_HIGH_DECODE_ADDRESS		0x288
+
+#define PCI_1I_O_LOW_DECODE_ADDRESS			0x090
+#define PCI_1I_O_HIGH_DECODE_ADDRESS			0x098
+#define PCI_1MEMORY0_LOW_DECODE_ADDRESS			0x0a0
+#define PCI_1MEMORY0_HIGH_DECODE_ADDRESS		0x0a8
+#define PCI_1MEMORY1_LOW_DECODE_ADDRESS			0x0b0
+#define PCI_1MEMORY1_HIGH_DECODE_ADDRESS		0x0b8
+#define PCI_1MEMORY2_LOW_DECODE_ADDRESS			0x2a0
+#define PCI_1MEMORY2_HIGH_DECODE_ADDRESS		0x2a8
+#define PCI_1MEMORY3_LOW_DECODE_ADDRESS			0x2b0
+#define PCI_1MEMORY3_HIGH_DECODE_ADDRESS		0x2b8
+
+
+#define INTERNAL_SPACE_DECODE				0x068
+
+#define CPU_0_LOW_DECODE_ADDRESS			0x290
+#define CPU_0_HIGH_DECODE_ADDRESS			0x298
+#define CPU_1_LOW_DECODE_ADDRESS			0x2c0
+#define CPU_1_HIGH_DECODE_ADDRESS			0x2c8
+
+#define PCI_0I_O_ADDRESS_REMAP				0x0f0
+#define PCI_0MEMORY0_ADDRESS_REMAP			0x0f8
+#define PCI_0MEMORY0_HIGH_ADDRESS_REMAP			0x320
+#define PCI_0MEMORY1_ADDRESS_REMAP			0x100
+#define PCI_0MEMORY1_HIGH_ADDRESS_REMAP			0x328
+#define PCI_0MEMORY2_ADDRESS_REMAP			0x2f8
+#define PCI_0MEMORY2_HIGH_ADDRESS_REMAP			0x330
+#define PCI_0MEMORY3_ADDRESS_REMAP			0x300
+#define PCI_0MEMORY3_HIGH_ADDRESS_REMAP			0x338
+
+#define PCI_1I_O_ADDRESS_REMAP				0x108
+#define PCI_1MEMORY0_ADDRESS_REMAP			0x110
+#define PCI_1MEMORY0_HIGH_ADDRESS_REMAP			0x340
+#define PCI_1MEMORY1_ADDRESS_REMAP			0x118
+#define PCI_1MEMORY1_HIGH_ADDRESS_REMAP			0x348
+#define PCI_1MEMORY2_ADDRESS_REMAP			0x310
+#define PCI_1MEMORY2_HIGH_ADDRESS_REMAP			0x350
+#define PCI_1MEMORY3_ADDRESS_REMAP			0x318
+#define PCI_1MEMORY3_HIGH_ADDRESS_REMAP			0x358
+
+
+/****************************************/
+/* CPU Sync Barrier			*/
+/****************************************/
+
+#define PCI_0SYNC_BARIER_VIRTUAL_REGISTER		0x0c0
+#define PCI_1SYNC_BARIER_VIRTUAL_REGISTER		0x0c8
+
+
+/****************************************/
+/* CPU Access Protect			*/
+/****************************************/
+
+#define CPU_LOW_PROTECT_ADDRESS_0			0x180
+#define CPU_HIGH_PROTECT_ADDRESS_0			0x188
+#define CPU_LOW_PROTECT_ADDRESS_1			0x190
+#define CPU_HIGH_PROTECT_ADDRESS_1			0x198
+#define CPU_LOW_PROTECT_ADDRESS_2			0x1a0
+#define CPU_HIGH_PROTECT_ADDRESS_2			0x1a8
+#define CPU_LOW_PROTECT_ADDRESS_3			0x1b0
+#define CPU_HIGH_PROTECT_ADDRESS_3			0x1b8
+#define CPU_LOW_PROTECT_ADDRESS_4			0x1c0
+#define CPU_HIGH_PROTECT_ADDRESS_4			0x1c8
+#define CPU_LOW_PROTECT_ADDRESS_5			0x1d0
+#define CPU_HIGH_PROTECT_ADDRESS_5			0x1d8
+#define CPU_LOW_PROTECT_ADDRESS_6			0x1e0
+#define CPU_HIGH_PROTECT_ADDRESS_6			0x1e8
+#define CPU_LOW_PROTECT_ADDRESS_7			0x1f0
+#define CPU_HIGH_PROTECT_ADDRESS_7			0x1f8
+
+
+/****************************************/
+/*	    Snoop Control		*/
+/****************************************/
+
+#define SNOOP_BASE_ADDRESS_0				0x380
+#define SNOOP_TOP_ADDRESS_0				0x388
+#define SNOOP_BASE_ADDRESS_1				0x390
+#define SNOOP_TOP_ADDRESS_1				0x398
+#define SNOOP_BASE_ADDRESS_2				0x3a0
+#define SNOOP_TOP_ADDRESS_2				0x3a8
+#define SNOOP_BASE_ADDRESS_3				0x3b0
+#define SNOOP_TOP_ADDRESS_3				0x3b8
+
+/****************************************/
+/*	    CPU Error Report		*/
+/****************************************/
+
+#define CPU_ERROR_ADDRESS_LOW				0x070
+#define CPU_ERROR_ADDRESS_HIGH				0x078
+#define CPU_ERROR_DATA_LOW				0x128
+#define CPU_ERROR_DATA_HIGH				0x130
+#define CPU_ERROR_PARITY				0x138
+#define CPU_ERROR_CAUSE					0x140
+#define CPU_ERROR_MASK					0x148
+
+/****************************************/
+/*	    Pslave Debug		*/
+/****************************************/
+
+#define X_0_ADDRESS					0x360
+#define X_0_COMMAND_ID					0x368
+#define X_1_ADDRESS					0x370
+#define X_1_COMMAND_ID					0x378
+#define WRITE_DATA_LOW					0x3c0
+#define WRITE_DATA_HIGH					0x3c8
+#define WRITE_BYTE_ENABLE				0x3e0
+#define READ_DATA_LOW					0x3d0
+#define READ_DATA_HIGH					0x3d8
+#define READ_ID						0x3e8
+
+
+/****************************************/
+/* SDRAM and Device Address Space	*/
+/****************************************/
+
+
+/****************************************/
+/* SDRAM Configuration			*/
+/****************************************/
+
+
+#define SDRAM_CONFIGURATION				0x448
+#define SDRAM_OPERATION_MODE				0x474
+#define SDRAM_ADDRESS_DECODE				0x47c
+#define SDRAM_UMA_CONTROL				0x4a4
+#define SDRAM_CROSS_BAR_CONTROL_LOW			0x4a8
+#define SDRAM_CROSS_BAR_CONTROL_HIGH			0x4ac
+#define SDRAM_CROSS_BAR_TIMEOUT				0x4b0
+#define SDRAM_TIMING					0x4b4
+
+
+/****************************************/
+/* SDRAM Parameters			*/
+/****************************************/
+
+#define SDRAM_BANK0PARAMETERS				0x44C
+#define SDRAM_BANK1PARAMETERS				0x450
+#define SDRAM_BANK2PARAMETERS				0x454
+#define SDRAM_BANK3PARAMETERS				0x458
+
+
+/****************************************/
+/* SDRAM Error Report			*/
+/****************************************/
+
+#define SDRAM_ERROR_DATA_LOW				0x484
+#define SDRAM_ERROR_DATA_HIGH				0x480
+#define SDRAM_AND_DEVICE_ERROR_ADDRESS			0x490
+#define SDRAM_RECEIVED_ECC				0x488
+#define SDRAM_CALCULATED_ECC				0x48c
+#define SDRAM_ECC_CONTROL				0x494
+#define SDRAM_ECC_ERROR_COUNTER				0x498
+
+
+/****************************************/
+/* SDunit Debug (for internal use)	*/
+/****************************************/
+
+#define X0_ADDRESS					0x500
+#define X0_COMMAND_AND_ID				0x504
+#define X0_WRITE_DATA_LOW				0x508
+#define X0_WRITE_DATA_HIGH				0x50c
+#define X0_WRITE_BYTE_ENABLE				0x518
+#define X0_READ_DATA_LOW				0x510
+#define X0_READ_DATA_HIGH				0x514
+#define X0_READ_ID					0x51c
+#define X1_ADDRESS					0x520
+#define X1_COMMAND_AND_ID				0x524
+#define X1_WRITE_DATA_LOW				0x528
+#define X1_WRITE_DATA_HIGH				0x52c
+#define X1_WRITE_BYTE_ENABLE				0x538
+#define X1_READ_DATA_LOW				0x530
+#define X1_READ_DATA_HIGH				0x534
+#define X1_READ_ID					0x53c
+#define X0_SNOOP_ADDRESS				0x540
+#define X0_SNOOP_COMMAND				0x544
+#define X1_SNOOP_ADDRESS				0x548
+#define X1_SNOOP_COMMAND				0x54c
+
+
+/****************************************/
+/* Device Parameters			*/
+/****************************************/
+
+#define DEVICE_BANK0PARAMETERS				0x45c
+#define DEVICE_BANK1PARAMETERS				0x460
+#define DEVICE_BANK2PARAMETERS				0x464
+#define DEVICE_BANK3PARAMETERS				0x468
+#define DEVICE_BOOT_BANK_PARAMETERS			0x46c
+#define DEVICE_CONTROL					0x4c0
+#define DEVICE_CROSS_BAR_CONTROL_LOW			0x4c8
+#define DEVICE_CROSS_BAR_CONTROL_HIGH			0x4cc
+#define DEVICE_CROSS_BAR_TIMEOUT			0x4c4
+
+
+/****************************************/
+/* Device Interrupt			*/
+/****************************************/
+
+#define DEVICE_INTERRUPT_CAUSE				0x4d0
+#define DEVICE_INTERRUPT_MASK				0x4d4
+#define DEVICE_ERROR_ADDRESS				0x4d8
+
+/****************************************/
+/* DMA Record				*/
+/****************************************/
+
+#define CHANNEL0_DMA_BYTE_COUNT				0x800
+#define CHANNEL1_DMA_BYTE_COUNT				0x804
+#define CHANNEL2_DMA_BYTE_COUNT				0x808
+#define CHANNEL3_DMA_BYTE_COUNT				0x80C
+#define CHANNEL4_DMA_BYTE_COUNT				0x900
+#define CHANNEL5_DMA_BYTE_COUNT				0x904
+#define CHANNEL6_DMA_BYTE_COUNT				0x908
+#define CHANNEL7_DMA_BYTE_COUNT				0x90C
+#define CHANNEL0_DMA_SOURCE_ADDRESS			0x810
+#define CHANNEL1_DMA_SOURCE_ADDRESS			0x814
+#define CHANNEL2_DMA_SOURCE_ADDRESS			0x818
+#define CHANNEL3_DMA_SOURCE_ADDRESS			0x81C
+#define CHANNEL4_DMA_SOURCE_ADDRESS			0x910
+#define CHANNEL5_DMA_SOURCE_ADDRESS			0x914
+#define CHANNEL6_DMA_SOURCE_ADDRESS			0x918
+#define CHANNEL7_DMA_SOURCE_ADDRESS			0x91C
+#define CHANNEL0_DMA_DESTINATION_ADDRESS		0x820
+#define CHANNEL1_DMA_DESTINATION_ADDRESS		0x824
+#define CHANNEL2_DMA_DESTINATION_ADDRESS		0x828
+#define CHANNEL3_DMA_DESTINATION_ADDRESS		0x82C
+#define CHANNEL4_DMA_DESTINATION_ADDRESS		0x920
+#define CHANNEL5_DMA_DESTINATION_ADDRESS		0x924
+#define CHANNEL6_DMA_DESTINATION_ADDRESS		0x928
+#define CHANNEL7_DMA_DESTINATION_ADDRESS		0x92C
+#define CHANNEL0NEXT_RECORD_POINTER			0x830
+#define CHANNEL1NEXT_RECORD_POINTER			0x834
+#define CHANNEL2NEXT_RECORD_POINTER			0x838
+#define CHANNEL3NEXT_RECORD_POINTER			0x83C
+#define CHANNEL4NEXT_RECORD_POINTER			0x930
+#define CHANNEL5NEXT_RECORD_POINTER			0x934
+#define CHANNEL6NEXT_RECORD_POINTER			0x938
+#define CHANNEL7NEXT_RECORD_POINTER			0x93C
+#define CHANNEL0CURRENT_DESCRIPTOR_POINTER		0x870
+#define CHANNEL1CURRENT_DESCRIPTOR_POINTER		0x874
+#define CHANNEL2CURRENT_DESCRIPTOR_POINTER		0x878
+#define CHANNEL3CURRENT_DESCRIPTOR_POINTER		0x87C
+#define CHANNEL4CURRENT_DESCRIPTOR_POINTER		0x970
+#define CHANNEL5CURRENT_DESCRIPTOR_POINTER		0x974
+#define CHANNEL6CURRENT_DESCRIPTOR_POINTER		0x978
+#define CHANNEL7CURRENT_DESCRIPTOR_POINTER		0x97C
+#define CHANNEL0_DMA_SOURCE_HIGH_PCI_ADDRESS		0x890
+#define CHANNEL1_DMA_SOURCE_HIGH_PCI_ADDRESS		0x894
+#define CHANNEL2_DMA_SOURCE_HIGH_PCI_ADDRESS		0x898
+#define CHANNEL3_DMA_SOURCE_HIGH_PCI_ADDRESS		0x89c
+#define CHANNEL4_DMA_SOURCE_HIGH_PCI_ADDRESS		0x990
+#define CHANNEL5_DMA_SOURCE_HIGH_PCI_ADDRESS		0x994
+#define CHANNEL6_DMA_SOURCE_HIGH_PCI_ADDRESS		0x998
+#define CHANNEL7_DMA_SOURCE_HIGH_PCI_ADDRESS		0x99c
+#define CHANNEL0_DMA_DESTINATION_HIGH_PCI_ADDRESS	0x8a0
+#define CHANNEL1_DMA_DESTINATION_HIGH_PCI_ADDRESS	0x8a4
+#define CHANNEL2_DMA_DESTINATION_HIGH_PCI_ADDRESS	0x8a8
+#define CHANNEL3_DMA_DESTINATION_HIGH_PCI_ADDRESS	0x8ac
+#define CHANNEL4_DMA_DESTINATION_HIGH_PCI_ADDRESS	0x9a0
+#define CHANNEL5_DMA_DESTINATION_HIGH_PCI_ADDRESS	0x9a4
+#define CHANNEL6_DMA_DESTINATION_HIGH_PCI_ADDRESS	0x9a8
+#define CHANNEL7_DMA_DESTINATION_HIGH_PCI_ADDRESS	0x9ac
+#define CHANNEL0_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS  0x8b0
+#define CHANNEL1_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS  0x8b4
+#define CHANNEL2_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS  0x8b8
+#define CHANNEL3_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS  0x8bc
+#define CHANNEL4_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS  0x9b0
+#define CHANNEL5_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS  0x9b4
+#define CHANNEL6_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS  0x9b8
+#define CHANNEL7_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS  0x9bc
+
+/****************************************/
+/* DMA Channel Control			*/
+/****************************************/
+
+#define CHANNEL0CONTROL					0x840
+#define CHANNEL0CONTROL_HIGH				0x880
+#define CHANNEL1CONTROL					0x844
+#define CHANNEL1CONTROL_HIGH				0x884
+#define CHANNEL2CONTROL					0x848
+#define CHANNEL2CONTROL_HIGH				0x888
+#define CHANNEL3CONTROL					0x84C
+#define CHANNEL3CONTROL_HIGH				0x88C
+
+#define CHANNEL4CONTROL					0x940
+#define CHANNEL4CONTROL_HIGH				0x980
+#define CHANNEL5CONTROL					0x944
+#define CHANNEL5CONTROL_HIGH				0x984
+#define CHANNEL6CONTROL					0x948
+#define CHANNEL6CONTROL_HIGH				0x988
+#define CHANNEL7CONTROL					0x94C
+#define CHANNEL7CONTROL_HIGH				0x98C
+
+
+/****************************************/
+/* DMA Arbiter				*/
+/****************************************/
+
+#define ARBITER_CONTROL_0_3										0x860
+#define ARBITER_CONTROL_4_7										0x960
+
+
+/****************************************/
+/* DMA Interrupt			*/
+/****************************************/
+
+#define CHANELS0_3_INTERRUPT_CAUSE			0x8c0
+#define CHANELS0_3_INTERRUPT_MASK			0x8c4
+#define CHANELS0_3_ERROR_ADDRESS			0x8c8
+#define CHANELS0_3_ERROR_SELECT				0x8cc
+#define CHANELS4_7_INTERRUPT_CAUSE			0x9c0
+#define CHANELS4_7_INTERRUPT_MASK			0x9c4
+#define CHANELS4_7_ERROR_ADDRESS			0x9c8
+#define CHANELS4_7_ERROR_SELECT				0x9cc
+
+
+/****************************************/
+/* DMA Debug (for internal use)		*/
+/****************************************/
+
+#define DMA_X0_ADDRESS					0x8e0
+#define DMA_X0_COMMAND_AND_ID				0x8e4
+#define DMA_X0_WRITE_DATA_LOW				0x8e8
+#define DMA_X0_WRITE_DATA_HIGH				0x8ec
+#define DMA_X0_WRITE_BYTE_ENABLE			0x8f8
+#define DMA_X0_READ_DATA_LOW				0x8f0
+#define DMA_X0_READ_DATA_HIGH				0x8f4
+#define DMA_X0_READ_ID					0x8fc
+#define DMA_X1_ADDRESS					0x9e0
+#define DMA_X1_COMMAND_AND_ID				0x9e4
+#define DMA_X1_WRITE_DATA_LOW				0x9e8
+#define DMA_X1_WRITE_DATA_HIGH				0x9ec
+#define DMA_X1_WRITE_BYTE_ENABLE			0x9f8
+#define DMA_X1_READ_DATA_LOW				0x9f0
+#define DMA_X1_READ_DATA_HIGH				0x9f4
+#define DMA_X1_READ_ID					0x9fc
+
+/****************************************/
+/* Timer_Counter			*/
+/****************************************/
+
+#define TIMER_COUNTER0					0x850
+#define TIMER_COUNTER1					0x854
+#define TIMER_COUNTER2					0x858
+#define TIMER_COUNTER3					0x85C
+#define TIMER_COUNTER_0_3_CONTROL			0x864
+#define TIMER_COUNTER_0_3_INTERRUPT_CAUSE		0x868
+#define TIMER_COUNTER_0_3_INTERRUPT_MASK		0x86c
+#define TIMER_COUNTER4					0x950
+#define TIMER_COUNTER5					0x954
+#define TIMER_COUNTER6					0x958
+#define TIMER_COUNTER7					0x95C
+#define TIMER_COUNTER_4_7_CONTROL			0x964
+#define TIMER_COUNTER_4_7_INTERRUPT_CAUSE		0x968
+#define TIMER_COUNTER_4_7_INTERRUPT_MASK		0x96c
+
+/****************************************/
+/* PCI Slave Address Decoding		*/
+/****************************************/
+
+#define PCI_0SCS_0_BANK_SIZE				0xc08
+#define PCI_1SCS_0_BANK_SIZE				0xc88
+#define PCI_0SCS_1_BANK_SIZE				0xd08
+#define PCI_1SCS_1_BANK_SIZE				0xd88
+#define PCI_0SCS_2_BANK_SIZE				0xc0c
+#define PCI_1SCS_2_BANK_SIZE				0xc8c
+#define PCI_0SCS_3_BANK_SIZE				0xd0c
+#define PCI_1SCS_3_BANK_SIZE				0xd8c
+#define PCI_0CS_0_BANK_SIZE				0xc10
+#define PCI_1CS_0_BANK_SIZE				0xc90
+#define PCI_0CS_1_BANK_SIZE				0xd10
+#define PCI_1CS_1_BANK_SIZE				0xd90
+#define PCI_0CS_2_BANK_SIZE				0xd18
+#define PCI_1CS_2_BANK_SIZE				0xd98
+#define PCI_0CS_3_BANK_SIZE				0xc14
+#define PCI_1CS_3_BANK_SIZE				0xc94
+#define PCI_0CS_BOOT_BANK_SIZE				0xd14
+#define PCI_1CS_BOOT_BANK_SIZE				0xd94
+#define PCI_0P2P_MEM0_BAR_SIZE				0xd1c
+#define PCI_1P2P_MEM0_BAR_SIZE				0xd9c
+#define PCI_0P2P_MEM1_BAR_SIZE				0xd20
+#define PCI_1P2P_MEM1_BAR_SIZE				0xda0
+#define PCI_0P2P_I_O_BAR_SIZE				0xd24
+#define PCI_1P2P_I_O_BAR_SIZE				0xda4
+#define PCI_0CPU_BAR_SIZE				0xd28
+#define PCI_1CPU_BAR_SIZE				0xda8
+#define PCI_0DAC_SCS_0_BANK_SIZE			0xe00
+#define PCI_1DAC_SCS_0_BANK_SIZE			0xe80
+#define PCI_0DAC_SCS_1_BANK_SIZE			0xe04
+#define PCI_1DAC_SCS_1_BANK_SIZE			0xe84
+#define PCI_0DAC_SCS_2_BANK_SIZE			0xe08
+#define PCI_1DAC_SCS_2_BANK_SIZE			0xe88
+#define PCI_0DAC_SCS_3_BANK_SIZE			0xe0c
+#define PCI_1DAC_SCS_3_BANK_SIZE			0xe8c
+#define PCI_0DAC_CS_0_BANK_SIZE				0xe10
+#define PCI_1DAC_CS_0_BANK_SIZE				0xe90
+#define PCI_0DAC_CS_1_BANK_SIZE				0xe14
+#define PCI_1DAC_CS_1_BANK_SIZE				0xe94
+#define PCI_0DAC_CS_2_BANK_SIZE				0xe18
+#define PCI_1DAC_CS_2_BANK_SIZE				0xe98
+#define PCI_0DAC_CS_3_BANK_SIZE				0xe1c
+#define PCI_1DAC_CS_3_BANK_SIZE				0xe9c
+#define PCI_0DAC_BOOTCS_BANK_SIZE			0xe20
+#define PCI_1DAC_BOOTCS_BANK_SIZE			0xea0
+#define PCI_0DAC_P2P_MEM0_BAR_SIZE			0xe24
+#define PCI_1DAC_P2P_MEM0_BAR_SIZE			0xea4
+#define PCI_0DAC_P2P_MEM1_BAR_SIZE			0xe28
+#define PCI_1DAC_P2P_MEM1_BAR_SIZE			0xea8
+#define PCI_0DAC_CPU_BAR_SIZE				0xe2c
+#define PCI_1DAC_CPU_BAR_SIZE				0xeac
+#define PCI_0EXPANSION_ROM_BAR_SIZE			0xd2c
+#define PCI_1EXPANSION_ROM_BAR_SIZE			0xdac
+#define PCI_0BASE_ADDRESS_REGISTERS_ENABLE		0xc3c
+#define PCI_1BASE_ADDRESS_REGISTERS_ENABLE		0xcbc
+#define PCI_0SCS_0_BASE_ADDRESS_REMAP			0xc48
+#define PCI_1SCS_0_BASE_ADDRESS_REMAP			0xcc8
+#define PCI_0SCS_1_BASE_ADDRESS_REMAP			0xd48
+#define PCI_1SCS_1_BASE_ADDRESS_REMAP			0xdc8
+#define PCI_0SCS_2_BASE_ADDRESS_REMAP			0xc4c
+#define PCI_1SCS_2_BASE_ADDRESS_REMAP			0xccc
+#define PCI_0SCS_3_BASE_ADDRESS_REMAP			0xd4c
+#define PCI_1SCS_3_BASE_ADDRESS_REMAP			0xdcc
+#define PCI_0CS_0_BASE_ADDRESS_REMAP			0xc50
+#define PCI_1CS_0_BASE_ADDRESS_REMAP			0xcd0
+#define PCI_0CS_1_BASE_ADDRESS_REMAP			0xd50
+#define PCI_1CS_1_BASE_ADDRESS_REMAP			0xdd0
+#define PCI_0CS_2_BASE_ADDRESS_REMAP			0xd58
+#define PCI_1CS_2_BASE_ADDRESS_REMAP			0xdd8
+#define PCI_0CS_3_BASE_ADDRESS_REMAP			0xc54
+#define PCI_1CS_3_BASE_ADDRESS_REMAP			0xcd4
+#define PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP		0xd54
+#define PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP		0xdd4
+#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW		0xd5c
+#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW		0xddc
+#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH		0xd60
+#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH		0xde0
+#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW		0xd64
+#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW		0xde4
+#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH		0xd68
+#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH		0xde8
+#define PCI_0P2P_I_O_BASE_ADDRESS_REMAP			0xd6c
+#define PCI_1P2P_I_O_BASE_ADDRESS_REMAP			0xdec
+#define PCI_0CPU_BASE_ADDRESS_REMAP			0xd70
+#define PCI_1CPU_BASE_ADDRESS_REMAP			0xdf0
+#define PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP		0xf00
+#define PCI_1DAC_SCS_0_BASE_ADDRESS_REMAP		0xff0
+#define PCI_0DAC_SCS_1_BASE_ADDRESS_REMAP		0xf04
+#define PCI_1DAC_SCS_1_BASE_ADDRESS_REMAP		0xf84
+#define PCI_0DAC_SCS_2_BASE_ADDRESS_REMAP		0xf08
+#define PCI_1DAC_SCS_2_BASE_ADDRESS_REMAP		0xf88
+#define PCI_0DAC_SCS_3_BASE_ADDRESS_REMAP		0xf0c
+#define PCI_1DAC_SCS_3_BASE_ADDRESS_REMAP		0xf8c
+#define PCI_0DAC_CS_0_BASE_ADDRESS_REMAP		0xf10
+#define PCI_1DAC_CS_0_BASE_ADDRESS_REMAP		0xf90
+#define PCI_0DAC_CS_1_BASE_ADDRESS_REMAP		0xf14
+#define PCI_1DAC_CS_1_BASE_ADDRESS_REMAP		0xf94
+#define PCI_0DAC_CS_2_BASE_ADDRESS_REMAP		0xf18
+#define PCI_1DAC_CS_2_BASE_ADDRESS_REMAP		0xf98
+#define PCI_0DAC_CS_3_BASE_ADDRESS_REMAP		0xf1c
+#define PCI_1DAC_CS_3_BASE_ADDRESS_REMAP		0xf9c
+#define PCI_0DAC_BOOTCS_BASE_ADDRESS_REMAP		0xf20
+#define PCI_1DAC_BOOTCS_BASE_ADDRESS_REMAP		0xfa0
+#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW	0xf24
+#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW	0xfa4
+#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH	0xf28
+#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH	0xfa8
+#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW	0xf2c
+#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW	0xfac
+#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH	0xf30
+#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH	0xfb0
+#define PCI_0DAC_CPU_BASE_ADDRESS_REMAP			0xf34
+#define PCI_1DAC_CPU_BASE_ADDRESS_REMAP			0xfb4
+#define PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP		0xf38
+#define PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP		0xfb8
+#define PCI_0ADDRESS_DECODE_CONTROL			0xd3c
+#define PCI_1ADDRESS_DECODE_CONTROL			0xdbc
+
+/****************************************/
+/* PCI Control				*/
+/****************************************/
+
+#define PCI_0COMMAND					0xc00
+#define PCI_1COMMAND					0xc80
+#define PCI_0MODE					0xd00
+#define PCI_1MODE					0xd80
+#define PCI_0TIMEOUT_RETRY				0xc04
+#define PCI_1TIMEOUT_RETRY				0xc84
+#define PCI_0READ_BUFFER_DISCARD_TIMER			0xd04
+#define PCI_1READ_BUFFER_DISCARD_TIMER			0xd84
+#define MSI_0TRIGGER_TIMER				0xc38
+#define MSI_1TRIGGER_TIMER				0xcb8
+#define PCI_0ARBITER_CONTROL				0x1d00
+#define PCI_1ARBITER_CONTROL				0x1d80
+/* changing untill here */
+#define PCI_0CROSS_BAR_CONTROL_LOW			0x1d08
+#define PCI_0CROSS_BAR_CONTROL_HIGH			0x1d0c
+#define PCI_0CROSS_BAR_TIMEOUT				0x1d04
+#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_LOW	0x1d18
+#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_HIGH	0x1d1c
+#define PCI_0SYNC_BARRIER_VIRTUAL_REGISTER		0x1d10
+#define PCI_0P2P_CONFIGURATION				0x1d14
+#define PCI_0ACCESS_CONTROL_BASE_0_LOW			0x1e00
+#define PCI_0ACCESS_CONTROL_BASE_0_HIGH			0x1e04
+#define PCI_0ACCESS_CONTROL_TOP_0			0x1e08
+#define PCI_0ACCESS_CONTROL_BASE_1_LOW			0x1e10
+#define PCI_0ACCESS_CONTROL_BASE_1_HIGH			0x1e14
+#define PCI_0ACCESS_CONTROL_TOP_1			0x1e18
+#define PCI_0ACCESS_CONTROL_BASE_2_LOW			0x1e20
+#define PCI_0ACCESS_CONTROL_BASE_2_HIGH			0x1e24
+#define PCI_0ACCESS_CONTROL_TOP_2			0x1e28
+#define PCI_0ACCESS_CONTROL_BASE_3_LOW			0x1e30
+#define PCI_0ACCESS_CONTROL_BASE_3_HIGH			0x1e34
+#define PCI_0ACCESS_CONTROL_TOP_3			0x1e38
+#define PCI_0ACCESS_CONTROL_BASE_4_LOW			0x1e40
+#define PCI_0ACCESS_CONTROL_BASE_4_HIGH			0x1e44
+#define PCI_0ACCESS_CONTROL_TOP_4			0x1e48
+#define PCI_0ACCESS_CONTROL_BASE_5_LOW			0x1e50
+#define PCI_0ACCESS_CONTROL_BASE_5_HIGH			0x1e54
+#define PCI_0ACCESS_CONTROL_TOP_5			0x1e58
+#define PCI_0ACCESS_CONTROL_BASE_6_LOW			0x1e60
+#define PCI_0ACCESS_CONTROL_BASE_6_HIGH			0x1e64
+#define PCI_0ACCESS_CONTROL_TOP_6			0x1e68
+#define PCI_0ACCESS_CONTROL_BASE_7_LOW			0x1e70
+#define PCI_0ACCESS_CONTROL_BASE_7_HIGH			0x1e74
+#define PCI_0ACCESS_CONTROL_TOP_7			0x1e78
+#define PCI_1CROSS_BAR_CONTROL_LOW			0x1d88
+#define PCI_1CROSS_BAR_CONTROL_HIGH			0x1d8c
+#define PCI_1CROSS_BAR_TIMEOUT				0x1d84
+#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_LOW	0x1d98
+#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_HIGH	0x1d9c
+#define PCI_1SYNC_BARRIER_VIRTUAL_REGISTER		0x1d90
+#define PCI_1P2P_CONFIGURATION				0x1d94
+#define PCI_1ACCESS_CONTROL_BASE_0_LOW			0x1e80
+#define PCI_1ACCESS_CONTROL_BASE_0_HIGH			0x1e84
+#define PCI_1ACCESS_CONTROL_TOP_0			0x1e88
+#define PCI_1ACCESS_CONTROL_BASE_1_LOW			0x1e90
+#define PCI_1ACCESS_CONTROL_BASE_1_HIGH			0x1e94
+#define PCI_1ACCESS_CONTROL_TOP_1			0x1e98
+#define PCI_1ACCESS_CONTROL_BASE_2_LOW			0x1ea0
+#define PCI_1ACCESS_CONTROL_BASE_2_HIGH			0x1ea4
+#define PCI_1ACCESS_CONTROL_TOP_2			0x1ea8
+#define PCI_1ACCESS_CONTROL_BASE_3_LOW			0x1eb0
+#define PCI_1ACCESS_CONTROL_BASE_3_HIGH			0x1eb4
+#define PCI_1ACCESS_CONTROL_TOP_3			0x1eb8
+#define PCI_1ACCESS_CONTROL_BASE_4_LOW			0x1ec0
+#define PCI_1ACCESS_CONTROL_BASE_4_HIGH			0x1ec4
+#define PCI_1ACCESS_CONTROL_TOP_4			0x1ec8
+#define PCI_1ACCESS_CONTROL_BASE_5_LOW			0x1ed0
+#define PCI_1ACCESS_CONTROL_BASE_5_HIGH			0x1ed4
+#define PCI_1ACCESS_CONTROL_TOP_5			0x1ed8
+#define PCI_1ACCESS_CONTROL_BASE_6_LOW			0x1ee0
+#define PCI_1ACCESS_CONTROL_BASE_6_HIGH			0x1ee4
+#define PCI_1ACCESS_CONTROL_TOP_6			0x1ee8
+#define PCI_1ACCESS_CONTROL_BASE_7_LOW			0x1ef0
+#define PCI_1ACCESS_CONTROL_BASE_7_HIGH			0x1ef4
+#define PCI_1ACCESS_CONTROL_TOP_7			0x1ef8
+
+/****************************************/
+/* PCI Snoop Control			*/
+/****************************************/
+
+#define PCI_0SNOOP_CONTROL_BASE_0_LOW			0x1f00
+#define PCI_0SNOOP_CONTROL_BASE_0_HIGH			0x1f04
+#define PCI_0SNOOP_CONTROL_TOP_0			0x1f08
+#define PCI_0SNOOP_CONTROL_BASE_1_0_LOW			0x1f10
+#define PCI_0SNOOP_CONTROL_BASE_1_0_HIGH		0x1f14
+#define PCI_0SNOOP_CONTROL_TOP_1			0x1f18
+#define PCI_0SNOOP_CONTROL_BASE_2_0_LOW			0x1f20
+#define PCI_0SNOOP_CONTROL_BASE_2_0_HIGH		0x1f24
+#define PCI_0SNOOP_CONTROL_TOP_2			0x1f28
+#define PCI_0SNOOP_CONTROL_BASE_3_0_LOW			0x1f30
+#define PCI_0SNOOP_CONTROL_BASE_3_0_HIGH		0x1f34
+#define PCI_0SNOOP_CONTROL_TOP_3			0x1f38
+#define PCI_1SNOOP_CONTROL_BASE_0_LOW			0x1f80
+#define PCI_1SNOOP_CONTROL_BASE_0_HIGH			0x1f84
+#define PCI_1SNOOP_CONTROL_TOP_0			0x1f88
+#define PCI_1SNOOP_CONTROL_BASE_1_0_LOW			0x1f90
+#define PCI_1SNOOP_CONTROL_BASE_1_0_HIGH		0x1f94
+#define PCI_1SNOOP_CONTROL_TOP_1			0x1f98
+#define PCI_1SNOOP_CONTROL_BASE_2_0_LOW			0x1fa0
+#define PCI_1SNOOP_CONTROL_BASE_2_0_HIGH		0x1fa4
+#define PCI_1SNOOP_CONTROL_TOP_2			0x1fa8
+#define PCI_1SNOOP_CONTROL_BASE_3_0_LOW			0x1fb0
+#define PCI_1SNOOP_CONTROL_BASE_3_0_HIGH		0x1fb4
+#define PCI_1SNOOP_CONTROL_TOP_3			0x1fb8
+
+/****************************************/
+/* PCI Configuration Address		*/
+/****************************************/
+
+#define PCI_0CONFIGURATION_ADDRESS			0xcf8
+#define PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER	0xcfc
+#define PCI_1CONFIGURATION_ADDRESS			0xc78
+#define PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER	0xc7c
+#define PCI_0INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER	0xc34
+#define PCI_1INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER	0xcb4
+
+/****************************************/
+/* PCI Error Report			*/
+/****************************************/
+
+#define PCI_0SERR_MASK										 0xc28
+#define PCI_0ERROR_ADDRESS_LOW				0x1d40
+#define PCI_0ERROR_ADDRESS_HIGH				0x1d44
+#define PCI_0ERROR_DATA_LOW				0x1d48
+#define PCI_0ERROR_DATA_HIGH				0x1d4c
+#define PCI_0ERROR_COMMAND				0x1d50
+#define PCI_0ERROR_CAUSE				0x1d58
+#define PCI_0ERROR_MASK					0x1d5c
+#define PCI_1SERR_MASK										 0xca8
+#define PCI_1ERROR_ADDRESS_LOW				0x1dc0
+#define PCI_1ERROR_ADDRESS_HIGH				0x1dc4
+#define PCI_1ERROR_DATA_LOW				0x1dc8
+#define PCI_1ERROR_DATA_HIGH				0x1dcc
+#define PCI_1ERROR_COMMAND				0x1dd0
+#define PCI_1ERROR_CAUSE				0x1dd8
+#define PCI_1ERROR_MASK					0x1ddc
+
+
+/****************************************/
+/* Lslave Debug  (for internal use)	*/
+/****************************************/
+
+#define L_SLAVE_X0_ADDRESS				0x1d20
+#define L_SLAVE_X0_COMMAND_AND_ID			0x1d24
+#define L_SLAVE_X1_ADDRESS				0x1d28
+#define L_SLAVE_X1_COMMAND_AND_ID			0x1d2c
+#define L_SLAVE_WRITE_DATA_LOW				0x1d30
+#define L_SLAVE_WRITE_DATA_HIGH				0x1d34
+#define L_SLAVE_WRITE_BYTE_ENABLE			0x1d60
+#define L_SLAVE_READ_DATA_LOW				0x1d38
+#define L_SLAVE_READ_DATA_HIGH				0x1d3c
+#define L_SLAVE_READ_ID					0x1d64
+
+/****************************************/
+/* PCI Configuration Function 0		*/
+/****************************************/
+
+#define PCI_DEVICE_AND_VENDOR_ID			0x000
+#define PCI_STATUS_AND_COMMAND				0x004
+#define PCI_CLASS_CODE_AND_REVISION_ID			0x008
+#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE	0x00C
+#define PCI_SCS_0_BASE_ADDRESS				0x010
+#define PCI_SCS_1_BASE_ADDRESS				0x014
+#define PCI_SCS_2_BASE_ADDRESS				0x018
+#define PCI_SCS_3_BASE_ADDRESS				0x01C
+#define PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS  0x020
+#define PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS	0x024
+#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID	0x02C
+#define PCI_EXPANSION_ROM_BASE_ADDRESS_REGISTER		0x030
+#define PCI_CAPABILTY_LIST_POINTER			0x034
+#define PCI_INTERRUPT_PIN_AND_LINE			0x03C
+#define PCI_POWER_MANAGEMENT_CAPABILITY			0x040
+#define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL		0x044
+#define PCI_VPD_ADDRESS					0x048
+#define PCI_VPD_DATA					0x04c
+#define PCI_MSI_MESSAGE_CONTROL				0x050
+#define PCI_MSI_MESSAGE_ADDRESS				0x054
+#define PCI_MSI_MESSAGE_UPPER_ADDRESS			0x058
+#define PCI_MSI_MESSAGE_DATA				0x05c
+#define PCI_COMPACT_PCI_HOT_SWAP_CAPABILITY		0x058
+
+/****************************************/
+/* PCI Configuration Function 1		*/
+/****************************************/
+
+#define PCI_CS_0_BASE_ADDRESS				0x110
+#define PCI_CS_1_BASE_ADDRESS				0x114
+#define PCI_CS_2_BASE_ADDRESS				0x118
+#define PCI_CS_3_BASE_ADDRESS				0x11c
+#define PCI_BOOTCS_BASE_ADDRESS				0x120
+
+/****************************************/
+/* PCI Configuration Function 2		*/
+/****************************************/
+
+#define PCI_P2P_MEM0_BASE_ADDRESS			0x210
+#define PCI_P2P_MEM1_BASE_ADDRESS			0x214
+#define PCI_P2P_I_O_BASE_ADDRESS			0x218
+#define PCI_CPU_BASE_ADDRESS				0x21c
+
+/****************************************/
+/* PCI Configuration Function 4		*/
+/****************************************/
+
+#define PCI_DAC_SCS_0_BASE_ADDRESS_LOW			0x410
+#define PCI_DAC_SCS_0_BASE_ADDRESS_HIGH			0x414
+#define PCI_DAC_SCS_1_BASE_ADDRESS_LOW			0x418
+#define PCI_DAC_SCS_1_BASE_ADDRESS_HIGH			0x41c
+#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_LOW		0x420
+#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_HIGH		0x424
+
+
+/****************************************/
+/* PCI Configuration Function 5		*/
+/****************************************/
+
+#define PCI_DAC_SCS_2_BASE_ADDRESS_LOW			0x510
+#define PCI_DAC_SCS_2_BASE_ADDRESS_HIGH			0x514
+#define PCI_DAC_SCS_3_BASE_ADDRESS_LOW			0x518
+#define PCI_DAC_SCS_3_BASE_ADDRESS_HIGH			0x51c
+#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_LOW		0x520
+#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_HIGH		0x524
+
+
+/****************************************/
+/* PCI Configuration Function 6		*/
+/****************************************/
+
+#define PCI_DAC_CS_0_BASE_ADDRESS_LOW			0x610
+#define PCI_DAC_CS_0_BASE_ADDRESS_HIGH			0x614
+#define PCI_DAC_CS_1_BASE_ADDRESS_LOW			0x618
+#define PCI_DAC_CS_1_BASE_ADDRESS_HIGH			0x61c
+#define PCI_DAC_CS_2_BASE_ADDRESS_LOW			0x620
+#define PCI_DAC_CS_2_BASE_ADDRESS_HIGH			0x624
+
+/****************************************/
+/* PCI Configuration Function 7		*/
+/****************************************/
+
+#define PCI_DAC_CS_3_BASE_ADDRESS_LOW			0x710
+#define PCI_DAC_CS_3_BASE_ADDRESS_HIGH			0x714
+#define PCI_DAC_BOOTCS_BASE_ADDRESS_LOW			0x718
+#define PCI_DAC_BOOTCS_BASE_ADDRESS_HIGH		0x71c
+#define PCI_DAC_CPU_BASE_ADDRESS_LOW			0x720
+#define PCI_DAC_CPU_BASE_ADDRESS_HIGH			0x724
+
+/****************************************/
+/* Interrupts				*/
+/****************************************/
+
+#define LOW_INTERRUPT_CAUSE_REGISTER			0xc18
+#define HIGH_INTERRUPT_CAUSE_REGISTER			0xc68
+#define CPU_INTERRUPT_MASK_REGISTER_LOW			0xc1c
+#define CPU_INTERRUPT_MASK_REGISTER_HIGH		0xc6c
+#define CPU_SELECT_CAUSE_REGISTER			0xc70
+#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW		0xc24
+#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH		0xc64
+#define PCI_0SELECT_CAUSE				0xc74
+#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW		0xca4
+#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH		0xce4
+#define PCI_1SELECT_CAUSE				0xcf4
+#define CPU_INT_0_MASK					0xe60
+#define CPU_INT_1_MASK					0xe64
+#define CPU_INT_2_MASK					0xe68
+#define CPU_INT_3_MASK					0xe6c
+
+/****************************************/
+/* I20 Support registers		*/
+/****************************************/
+
+#define INBOUND_MESSAGE_REGISTER0_PCI_SIDE		0x010
+#define INBOUND_MESSAGE_REGISTER1_PCI_SIDE		0x014
+#define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE		0x018
+#define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE		0x01C
+#define INBOUND_DOORBELL_REGISTER_PCI_SIDE		0x020
+#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE	0x024
+#define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE	0x028
+#define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE		0x02C
+#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE	0x030
+#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE	0x034
+#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE	0x040
+#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE	0x044
+#define QUEUE_CONTROL_REGISTER_PCI_SIDE			0x050
+#define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE		0x054
+#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE	0x060
+#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE	0x064
+#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE	0x068
+#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE	0x06C
+#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE	0x070
+#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE	0x074
+#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE	0x078
+#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE	0x07C
+
+#define INBOUND_MESSAGE_REGISTER0_CPU_SIDE		0x1C10
+#define INBOUND_MESSAGE_REGISTER1_CPU_SIDE		0x1C14
+#define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE		0x1C18
+#define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE		0x1C1C
+#define INBOUND_DOORBELL_REGISTER_CPU_SIDE		0x1C20
+#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE	0x1C24
+#define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE	0x1C28
+#define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE		0x1C2C
+#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE	0x1C30
+#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE	0x1C34
+#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE	0x1C40
+#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE	0x1C44
+#define QUEUE_CONTROL_REGISTER_CPU_SIDE			0x1C50
+#define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE		0x1C54
+#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE	0x1C60
+#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE	0x1C64
+#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE	0x1C68
+#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE	0x1C6C
+#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE	0x1C70
+#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE	0x1C74
+#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE	0x1C78
+#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE	0x1C7C
+
+/****************************************/
+/* Communication Unit Registers		*/
+/****************************************/
+
+#define ETHERNET_0_ADDRESS_CONTROL_LOW			0xf200
+#define ETHERNET_0_ADDRESS_CONTROL_HIGH			0xf204
+#define ETHERNET_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS	0xf208
+#define ETHERNET_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS	0xf20c
+#define ETHERNET_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS	0xf210
+#define ETHERNET_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf214
+#define ETHERNET_0_HASH_TABLE_PCI_HIGH_ADDRESS		0xf218
+#define ETHERNET_1_ADDRESS_CONTROL_LOW			0xf220
+#define ETHERNET_1_ADDRESS_CONTROL_HIGH			0xf224
+#define ETHERNET_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS	0xf228
+#define ETHERNET_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS	0xf22c
+#define ETHERNET_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS	0xf230
+#define ETHERNET_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf234
+#define ETHERNET_1_HASH_TABLE_PCI_HIGH_ADDRESS		0xf238
+#define ETHERNET_2_ADDRESS_CONTROL_LOW			0xf240
+#define ETHERNET_2_ADDRESS_CONTROL_HIGH			0xf244
+#define ETHERNET_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS	0xf248
+#define ETHERNET_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS	0xf24c
+#define ETHERNET_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS	0xf250
+#define ETHERNET_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf254
+#define ETHERNET_2_HASH_TABLE_PCI_HIGH_ADDRESS		0xf258
+#define MPSC_0_ADDRESS_CONTROL_LOW			0xf280
+#define MPSC_0_ADDRESS_CONTROL_HIGH			0xf284
+#define MPSC_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS		0xf288
+#define MPSC_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS		0xf28c
+#define MPSC_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS	0xf290
+#define MPSC_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS	0xf294
+#define MPSC_1_ADDRESS_CONTROL_LOW			0xf2c0
+#define MPSC_1_ADDRESS_CONTROL_HIGH			0xf2c4
+#define MPSC_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS		0xf2c8
+#define MPSC_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS		0xf2cc
+#define MPSC_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS	0xf2d0
+#define MPSC_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS	0xf2d4
+#define SERIAL_INIT_PCI_HIGH_ADDRESS			0xf320
+#define SERIAL_INIT_LAST_DATA				0xf324
+#define SERIAL_INIT_STATUS_AND_CONTROL			0xf328
+#define COMM_UNIT_ARBITER_CONTROL			0xf300
+#define COMM_UNIT_CROSS_BAR_TIMEOUT			0xf304
+#define COMM_UNIT_INTERRUPT_CAUSE			0xf310
+#define COMM_UNIT_INTERRUPT_MASK			0xf314
+#define COMM_UNIT_ERROR_ADDRESS				0xf314
+
+/****************************************/
+/* Cunit Debug	(for internal use)     */
+/****************************************/
+
+#define CUNIT_ADDRESS					0xf340
+#define CUNIT_COMMAND_AND_ID				0xf344
+#define CUNIT_WRITE_DATA_LOW				0xf348
+#define CUNIT_WRITE_DATA_HIGH				0xf34c
+#define CUNIT_WRITE_BYTE_ENABLE				0xf358
+#define CUNIT_READ_DATA_LOW				0xf350
+#define CUNIT_READ_DATA_HIGH				0xf354
+#define CUNIT_READ_ID					0xf35c
+
+/****************************************/
+/* Fast Ethernet Unit Registers		*/
+/****************************************/
+
+/* Ethernet */
+
+#define ETHERNET_PHY_ADDRESS_REGISTER			0x2000
+#define ETHERNET_SMI_REGISTER				0x2010
+
+/* Ethernet 0 */
+
+#define ETHERNET0_PORT_CONFIGURATION_REGISTER		0x2400
+#define ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER	0x2408
+#define ETHERNET0_PORT_COMMAND_REGISTER			0x2410
+#define ETHERNET0_PORT_STATUS_REGISTER			0x2418
+#define ETHERNET0_SERIAL_PARAMETRS_REGISTER		0x2420
+#define ETHERNET0_HASH_TABLE_POINTER_REGISTER		0x2428
+#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_LOW	0x2430
+#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_HIGH	0x2438
+#define ETHERNET0_SDMA_CONFIGURATION_REGISTER		0x2440
+#define ETHERNET0_SDMA_COMMAND_REGISTER			0x2448
+#define ETHERNET0_INTERRUPT_CAUSE_REGISTER		0x2450
+#define ETHERNET0_INTERRUPT_MASK_REGISTER		0x2458
+#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0		0x2480
+#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER1		0x2484
+#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER2		0x2488
+#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER3		0x248c
+#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0	0x24a0
+#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER1	0x24a4
+#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER2	0x24a8
+#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER3	0x24ac
+#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0	0x24e0
+#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER1	0x24e4
+#define ETHERNET0_MIB_COUNTER_BASE			0x2500
+
+/* Ethernet 1 */
+
+#define ETHERNET1_PORT_CONFIGURATION_REGISTER		0x2800
+#define ETHERNET1_PORT_CONFIGURATION_EXTEND_REGISTER	0x2808
+#define ETHERNET1_PORT_COMMAND_REGISTER			0x2810
+#define ETHERNET1_PORT_STATUS_REGISTER			0x2818
+#define ETHERNET1_SERIAL_PARAMETRS_REGISTER		0x2820
+#define ETHERNET1_HASH_TABLE_POINTER_REGISTER		0x2828
+#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_LOW	0x2830
+#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_HIGH	0x2838
+#define ETHERNET1_SDMA_CONFIGURATION_REGISTER		0x2840
+#define ETHERNET1_SDMA_COMMAND_REGISTER			0x2848
+#define ETHERNET1_INTERRUPT_CAUSE_REGISTER		0x2850
+#define ETHERNET1_INTERRUPT_MASK_REGISTER		0x2858
+#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER0		0x2880
+#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER1		0x2884
+#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER2		0x2888
+#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER3		0x288c
+#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER0	0x28a0
+#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER1	0x28a4
+#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER2	0x28a8
+#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER3	0x28ac
+#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER0	0x28e0
+#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER1	0x28e4
+#define ETHERNET1_MIB_COUNTER_BASE			0x2900
+
+/* Ethernet 2 */
+
+#define ETHERNET2_PORT_CONFIGURATION_REGISTER		0x2c00
+#define ETHERNET2_PORT_CONFIGURATION_EXTEND_REGISTER	0x2c08
+#define ETHERNET2_PORT_COMMAND_REGISTER			0x2c10
+#define ETHERNET2_PORT_STATUS_REGISTER			0x2c18
+#define ETHERNET2_SERIAL_PARAMETRS_REGISTER		0x2c20
+#define ETHERNET2_HASH_TABLE_POINTER_REGISTER		0x2c28
+#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_LOW	0x2c30
+#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_HIGH	0x2c38
+#define ETHERNET2_SDMA_CONFIGURATION_REGISTER		0x2c40
+#define ETHERNET2_SDMA_COMMAND_REGISTER			0x2c48
+#define ETHERNET2_INTERRUPT_CAUSE_REGISTER		0x2c50
+#define ETHERNET2_INTERRUPT_MASK_REGISTER		0x2c58
+#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER0		0x2c80
+#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER1		0x2c84
+#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER2		0x2c88
+#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER3		0x2c8c
+#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER0	0x2ca0
+#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER1	0x2ca4
+#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER2	0x2ca8
+#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER3	0x2cac
+#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER0	0x2ce0
+#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER1	0x2ce4
+#define ETHERNET2_MIB_COUNTER_BASE			0x2d00
+
+/****************************************/
+/* SDMA Registers			*/
+/****************************************/
+
+#define SDMA_GROUP_CONFIGURATION_REGISTER		0xb1f0
+#define CHANNEL0_CONFIGURATION_REGISTER			0x4000
+#define CHANNEL0_COMMAND_REGISTER			0x4008
+#define CHANNEL0_RX_CMD_STATUS				0x4800
+#define CHANNEL0_RX_PACKET_AND_BUFFER_SIZES		0x4804
+#define CHANNEL0_RX_BUFFER_POINTER			0x4808
+#define CHANNEL0_RX_NEXT_POINTER			0x480c
+#define CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER		0x4810
+#define CHANNEL0_TX_CMD_STATUS				0x4C00
+#define CHANNEL0_TX_PACKET_SIZE				0x4C04
+#define CHANNEL0_TX_BUFFER_POINTER			0x4C08
+#define CHANNEL0_TX_NEXT_POINTER			0x4C0c
+#define CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER		0x4c10
+#define CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER		0x4c14
+#define CHANNEL1_CONFIGURATION_REGISTER			0x5000
+#define CHANNEL1_COMMAND_REGISTER			0x5008
+#define CHANNEL1_RX_CMD_STATUS				0x5800
+#define CHANNEL1_RX_PACKET_AND_BUFFER_SIZES		0x5804
+#define CHANNEL1_RX_BUFFER_POINTER			0x5808
+#define CHANNEL1_RX_NEXT_POINTER			0x580c
+#define CHANNEL1_TX_CMD_STATUS				0x5C00
+#define CHANNEL1_TX_PACKET_SIZE				0x5C04
+#define CHANNEL1_TX_BUFFER_POINTER			0x5C08
+#define CHANNEL1_TX_NEXT_POINTER			0x5C0c
+#define CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER		0x5810
+#define CHANNEL1_CURRENT_TX_DESCRIPTOR_POINTER		0x5c10
+#define CHANNEL1_FIRST_TX_DESCRIPTOR_POINTER		0x5c14
+#define CHANNEL2_CONFIGURATION_REGISTER			0x6000
+#define CHANNEL2_COMMAND_REGISTER			0x6008
+#define CHANNEL2_RX_CMD_STATUS				0x6800
+#define CHANNEL2_RX_PACKET_AND_BUFFER_SIZES		0x6804
+#define CHANNEL2_RX_BUFFER_POINTER			0x6808
+#define CHANNEL2_RX_NEXT_POINTER			0x680c
+#define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER		0x6810
+#define CHANNEL2_TX_CMD_STATUS				0x6C00
+#define CHANNEL2_TX_PACKET_SIZE				0x6C04
+#define CHANNEL2_TX_BUFFER_POINTER			0x6C08
+#define CHANNEL2_TX_NEXT_POINTER			0x6C0c
+#define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER		0x6810
+#define CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER		0x6c10
+#define CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER		0x6c14
+
+/* SDMA Interrupt */
+
+#define SDMA_CAUSE					0xb820
+#define SDMA_MASK					0xb8a0
+
+
+/****************************************/
+/* Baude Rate Generators Registers	*/
+/****************************************/
+
+/* BRG 0 */
+
+#define BRG0_CONFIGURATION_REGISTER			0xb200
+#define BRG0_BAUDE_TUNING_REGISTER			0xb204
+
+/* BRG 1 */
+
+#define BRG1_CONFIGURATION_REGISTER			0xb208
+#define BRG1_BAUDE_TUNING_REGISTER			0xb20c
+
+/* BRG 2 */
+
+#define BRG2_CONFIGURATION_REGISTER			0xb210
+#define BRG2_BAUDE_TUNING_REGISTER			0xb214
+
+/* BRG Interrupts */
+
+#define BRG_CAUSE_REGISTER				0xb834
+#define BRG_MASK_REGISTER				0xb8b4
+
+/* MISC */
+
+#define MAIN_ROUTING_REGISTER				0xb400
+#define RECEIVE_CLOCK_ROUTING_REGISTER			0xb404
+#define TRANSMIT_CLOCK_ROUTING_REGISTER			0xb408
+#define COMM_UNIT_ARBITER_CONFIGURATION_REGISTER	0xb40c
+#define WATCHDOG_CONFIGURATION_REGISTER			0xb410
+#define WATCHDOG_VALUE_REGISTER				0xb414
+
+
+/****************************************/
+/* Flex TDM Registers			*/
+/****************************************/
+
+/* FTDM Port */
+
+#define FLEXTDM_TRANSMIT_READ_POINTER			0xa800
+#define FLEXTDM_RECEIVE_READ_POINTER			0xa804
+#define FLEXTDM_CONFIGURATION_REGISTER			0xa808
+#define FLEXTDM_AUX_CHANNELA_TX_REGISTER		0xa80c
+#define FLEXTDM_AUX_CHANNELA_RX_REGISTER		0xa810
+#define FLEXTDM_AUX_CHANNELB_TX_REGISTER		0xa814
+#define FLEXTDM_AUX_CHANNELB_RX_REGISTER		0xa818
+
+/* FTDM Interrupts */
+
+#define FTDM_CAUSE_REGISTER				0xb830
+#define FTDM_MASK_REGISTER				0xb8b0
+
+
+/****************************************/
+/* GPP Interface Registers		*/
+/****************************************/
+
+#define GPP_IO_CONTROL					0xf100
+#define GPP_LEVEL_CONTROL				0xf110
+#define GPP_VALUE					0xf104
+#define GPP_INTERRUPT_CAUSE				0xf108
+#define GPP_INTERRUPT_MASK				0xf10c
+
+#define MPP_CONTROL0					0xf000
+#define MPP_CONTROL1					0xf004
+#define MPP_CONTROL2					0xf008
+#define MPP_CONTROL3					0xf00c
+#define DEBUG_PORT_MULTIPLEX				0xf014
+#define SERIAL_PORT_MULTIPLEX				0xf010
+
+/****************************************/
+/* I2C Registers			*/
+/****************************************/
+
+#define I2C_SLAVE_ADDRESS				0xc000
+#define I2C_EXTENDED_SLAVE_ADDRESS			0xc040
+#define I2C_DATA					0xc004
+#define I2C_CONTROL					0xc008
+#define I2C_STATUS_BAUDE_RATE				0xc00C
+#define I2C_SOFT_RESET					0xc01c
+
+/****************************************/
+/* MPSC Registers			*/
+/****************************************/
+
+/* MPSC0  */
+
+#define MPSC0_MAIN_CONFIGURATION_LOW			0x8000
+#define MPSC0_MAIN_CONFIGURATION_HIGH			0x8004
+#define MPSC0_PROTOCOL_CONFIGURATION			0x8008
+#define CHANNEL0_REGISTER1				0x800c
+#define CHANNEL0_REGISTER2				0x8010
+#define CHANNEL0_REGISTER3				0x8014
+#define CHANNEL0_REGISTER4				0x8018
+#define CHANNEL0_REGISTER5				0x801c
+#define CHANNEL0_REGISTER6				0x8020
+#define CHANNEL0_REGISTER7				0x8024
+#define CHANNEL0_REGISTER8				0x8028
+#define CHANNEL0_REGISTER9				0x802c
+#define CHANNEL0_REGISTER10				0x8030
+#define CHANNEL0_REGISTER11				0x8034
+
+/* MPSC1  */
+
+#define MPSC1_MAIN_CONFIGURATION_LOW			0x8840
+#define MPSC1_MAIN_CONFIGURATION_HIGH			0x8844
+#define MPSC1_PROTOCOL_CONFIGURATION			0x8848
+#define CHANNEL1_REGISTER1				0x884c
+#define CHANNEL1_REGISTER2				0x8850
+#define CHANNEL1_REGISTER3				0x8854
+#define CHANNEL1_REGISTER4				0x8858
+#define CHANNEL1_REGISTER5				0x885c
+#define CHANNEL1_REGISTER6				0x8860
+#define CHANNEL1_REGISTER7				0x8864
+#define CHANNEL1_REGISTER8				0x8868
+#define CHANNEL1_REGISTER9				0x886c
+#define CHANNEL1_REGISTER10				0x8870
+#define CHANNEL1_REGISTER11				0x8874
+
+/* MPSC2  */
+
+#define MPSC2_MAIN_CONFIGURATION_LOW			0x9040
+#define MPSC2_MAIN_CONFIGURATION_HIGH			0x9044
+#define MPSC2_PROTOCOL_CONFIGURATION			0x9048
+#define CHANNEL2_REGISTER1				0x904c
+#define CHANNEL2_REGISTER2				0x9050
+#define CHANNEL2_REGISTER3				0x9054
+#define CHANNEL2_REGISTER4				0x9058
+#define CHANNEL2_REGISTER5				0x905c
+#define CHANNEL2_REGISTER6				0x9060
+#define CHANNEL2_REGISTER7				0x9064
+#define CHANNEL2_REGISTER8				0x9068
+#define CHANNEL2_REGISTER9				0x906c
+#define CHANNEL2_REGISTER10				0x9070
+#define CHANNEL2_REGISTER11				0x9074
+
+/* MPSCs Interrupts  */
+
+#define MPSC0_CAUSE					0xb824
+#define MPSC0_MASK					0xb8a4
+#define MPSC1_CAUSE					0xb828
+#define MPSC1_MASK					0xb8a8
+#define MPSC2_CAUSE					0xb82c
+#define MPSC2_MASK					0xb8ac
+
+#endif /* __INCgt64260rh */
diff --git a/qemu/roms/u-boot/include/galileo/memory.h b/qemu/roms/u-boot/include/galileo/memory.h
new file mode 100644
index 000000000..0c46c24d0
--- /dev/null
+++ b/qemu/roms/u-boot/include/galileo/memory.h
@@ -0,0 +1,85 @@
+/* Memory.h - Memory mappings and remapping functions declarations */
+
+/* Copyright - Galileo technology. */
+
+#ifndef __INCmemoryh
+#define __INCmemoryh
+
+/* includes */
+
+#include "core.h"
+
+/* defines */
+
+#define DONT_MODIFY     0xffffffff
+#define PARITY_SUPPORT  0x40000000
+
+#define _8BIT           0x00000000
+#define _16BIT          0x00100000
+#define _32BIT          0x00200000
+#define _64BIT          0x00300000
+
+/* typedefs */
+
+ typedef struct deviceParam
+{                               /* boundary values  */
+    unsigned int    turnOff;    /* 0x0 - 0xf        */
+    unsigned int    acc2First;  /* 0x0 - 0x1f       */
+    unsigned int    acc2Next;   /* 0x0 - 0x1f       */
+    unsigned int    ale2Wr;     /* 0x0 - 0xf        */
+    unsigned int    wrLow;      /* 0x0 - 0xf        */
+    unsigned int    wrHigh;     /* 0x0 - 0xf        */
+    unsigned int    deviceWidth;    /* in Bytes  */
+} DEVICE_PARAM;
+
+typedef enum __memBank{BANK0,BANK1,BANK2,BANK3} MEMORY_BANK;
+typedef enum __memDevice{DEVICE0,DEVICE1,DEVICE2,DEVICE3,BOOT_DEVICE} DEVICE;
+
+typedef enum __memoryProtectRegion{MEM_REGION0,MEM_REGION1,MEM_REGION2,       \
+				   MEM_REGION3,MEM_REGION4,MEM_REGION5,       \
+				   MEM_REGION6,MEM_REGION7}                   \
+				   MEMORY_PROTECT_REGION;
+typedef enum __memoryAccess{MEM_ACCESS_ALLOWED,MEM_ACCESS_FORBIDEN}           \
+			    MEMORY_ACCESS;
+typedef enum __memoryWrite{MEM_WRITE_ALLOWED,MEM_WRITE_FORBIDEN}              \
+			   MEMORY_ACCESS_WRITE;
+typedef enum __memoryCacheProtect{MEM_CACHE_ALLOWED,MEM_CACHE_FORBIDEN}       \
+				  MEMORY_CACHE_PROTECT;
+typedef enum __memorySnoopType{MEM_NO_SNOOP,MEM_SNOOP_WT,MEM_SNOOP_WB}        \
+			       MEMORY_SNOOP_TYPE;
+typedef enum __memorySnoopRegion{MEM_SNOOP_REGION0,MEM_SNOOP_REGION1,         \
+				 MEM_SNOOP_REGION2,MEM_SNOOP_REGION3}         \
+				 MEMORY_SNOOP_REGION;
+
+/* functions */
+unsigned int memoryGetBankBaseAddress(MEMORY_BANK bank);
+unsigned int memoryGetDeviceBaseAddress(DEVICE device);
+unsigned int memoryGetBankSize(MEMORY_BANK bank);
+unsigned int memoryGetDeviceSize(DEVICE device);
+unsigned int memoryGetDeviceWidth(DEVICE device);
+
+/* when given base Address and size Set new WINDOW for SCS_X. (X = 0,1,2 or 3*/
+bool memoryMapBank(MEMORY_BANK bank, unsigned int bankBase,unsigned int bankLength);
+bool memoryMapDeviceSpace(DEVICE device, unsigned int deviceBase,unsigned int deviceLength);
+
+/* Change the Internal Register Base Address to a new given Address. */
+bool memoryMapInternalRegistersSpace(unsigned int internalRegBase);
+/* returns internal Register Space Base Address. */
+unsigned int memoryGetInternalRegistersSpace(void);
+/* Configurate the protection feature to a given space. */
+bool memorySetProtectRegion(MEMORY_PROTECT_REGION region,
+			    MEMORY_ACCESS memoryAccess,
+			    MEMORY_ACCESS_WRITE memoryWrite,
+			    MEMORY_CACHE_PROTECT cacheProtection,
+			    unsigned int baseAddress,
+			    unsigned int regionLength);
+/* Configurate the snoop feature to a given space. */
+bool memorySetRegionSnoopMode(MEMORY_SNOOP_REGION region,
+			      MEMORY_SNOOP_TYPE snoopType,
+			      unsigned int baseAddress,
+			      unsigned int regionLength);
+
+bool memoryRemapAddress(unsigned int remapReg, unsigned int remapValue);
+bool memoryGetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum);
+bool memorySetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum);
+#endif  /* __INCmemoryh */
diff --git a/qemu/roms/u-boot/include/galileo/pci.h b/qemu/roms/u-boot/include/galileo/pci.h
new file mode 100644
index 000000000..6ed8b95df
--- /dev/null
+++ b/qemu/roms/u-boot/include/galileo/pci.h
@@ -0,0 +1,113 @@
+/* PCI.h - PCI functions header file */
+
+/* Copyright - Galileo technology. */
+
+#ifndef __INCpcih
+#define __INCpcih
+
+/* includes */
+
+#include "core.h"
+#include "memory.h"
+
+/* According to PCI REV 2.1 MAX agents allowed on the bus are -21- */
+#define PCI_MAX_DEVICES 22
+
+
+/* Macros */
+#define     SELF                    32
+
+/* Defines for the access regions. */
+#define     PREFETCH_ENABLE                 BIT12
+#define     PREFETCH_DISABLE                NO_BIT
+#define     DELAYED_READ_ENABLE             BIT13
+/* #define     CACHING_ENABLE                  BIT14 */
+/* aggressive prefetch: PCI slave prefetch two burst in advance*/
+#define     AGGRESSIVE_PREFETCH              BIT16
+/* read line aggresive prefetch: PCI slave prefetch two burst in advance*/
+#define     READ_LINE_AGGRESSIVE_PREFETCH   BIT17
+/* read multiple aggresive prefetch: PCI slave prefetch two burst in advance*/
+#define     READ_MULTI_AGGRESSIVE_PREFETCH  BIT18
+#define     MAX_BURST_4                     NO_BIT
+#define     MAX_BURST_8                     BIT20  /* Bits[21:20] = 01 */
+#define     MAX_BURST_16                    BIT21  /* Bits[21:20] = 10 */
+#define     PCI_BYTE_SWAP                   NO_BIT /* Bits[25:24] = 00 */
+#define     PCI_NO_SWAP                     BIT24  /* Bits[25:24] = 01 */
+#define     PCI_BYTE_AND_WORD_SWAP          BIT25  /* Bits[25:24] = 10 */
+#define     PCI_WORD_SWAP                  (BIT24 | BIT25) /* Bits[25:24] = 11 */
+#define     PCI_ACCESS_PROTECT              BIT28
+#define     PCI_WRITE_PROTECT               BIT29
+
+/* typedefs */
+
+typedef enum __pciAccessRegions{REGION0,REGION1,REGION2,REGION3,REGION4,REGION5,
+				REGION6,REGION7} PCI_ACCESS_REGIONS;
+
+typedef enum __pciAgentPrio{LOW_AGENT_PRIO,HI_AGENT_PRIO} PCI_AGENT_PRIO;
+typedef enum __pciAgentPark{PARK_ON_AGENT,DONT_PARK_ON_AGENT} PCI_AGENT_PARK;
+
+typedef enum __pciSnoopType{PCI_NO_SNOOP,PCI_SNOOP_WT,PCI_SNOOP_WB}
+			    PCI_SNOOP_TYPE;
+typedef enum __pciSnoopRegion{PCI_SNOOP_REGION0,PCI_SNOOP_REGION1,
+			      PCI_SNOOP_REGION2,PCI_SNOOP_REGION3}
+			      PCI_SNOOP_REGION;
+
+typedef enum __memPciHost{PCI_HOST0,PCI_HOST1} PCI_HOST;
+typedef enum __memPciRegion{PCI_REGION0,PCI_REGION1,
+			 PCI_REGION2,PCI_REGION3,
+			 PCI_IO}
+			 PCI_REGION;
+
+/* read/write configuration registers on local PCI bus. */
+void pciWriteConfigReg(PCI_HOST host, unsigned int regOffset,
+		       unsigned int pciDevNum, unsigned int data);
+unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
+			       unsigned int pciDevNum);
+
+/* read/write configuration registers on another PCI bus. */
+void pciOverBridgeWriteConfigReg(PCI_HOST host,
+				 unsigned int regOffset,
+				 unsigned int pciDevNum,
+				 unsigned int busNum,unsigned int data);
+unsigned int pciOverBridgeReadConfigReg(PCI_HOST host,
+					unsigned int regOffset,
+					unsigned int pciDevNum,
+					unsigned int busNum);
+
+/*      Master`s memory space   */
+bool pciMapSpace(PCI_HOST host, PCI_REGION region,
+		unsigned int remapBase,
+		unsigned int deviceBase,
+		unsigned int deviceLength);
+unsigned int pciGetSpaceBase(PCI_HOST host, PCI_REGION region);
+unsigned int pciGetSpaceSize(PCI_HOST host, PCI_REGION region);
+
+/*      Slave`s memory space   */
+void pciMapMemoryBank(PCI_HOST host, MEMORY_BANK bank,
+		      unsigned int pci0Dram0Base, unsigned int pci0Dram0Size);
+
+/* PCI region options */
+
+bool  pciSetRegionFeatures(PCI_HOST host, PCI_ACCESS_REGIONS region,
+	unsigned int features, unsigned int baseAddress,
+	unsigned int regionLength);
+
+void  pciDisableAccessRegion(PCI_HOST host, PCI_ACCESS_REGIONS region);
+
+/* PCI arbiter */
+
+bool pciArbiterEnable(PCI_HOST host);
+bool pciArbiterDisable(PCI_HOST host);
+bool pciParkingDisable(PCI_HOST host, PCI_AGENT_PARK internalAgent,
+			PCI_AGENT_PARK externalAgent0,
+			PCI_AGENT_PARK externalAgent1,
+			PCI_AGENT_PARK externalAgent2,
+			PCI_AGENT_PARK externalAgent3,
+			PCI_AGENT_PARK externalAgent4,
+			PCI_AGENT_PARK externalAgent5);
+bool pciSetRegionSnoopMode(PCI_HOST host, PCI_SNOOP_REGION region,
+			    PCI_SNOOP_TYPE snoopType,
+			    unsigned int baseAddress,
+			    unsigned int regionLength);
+
+#endif /* __INCpcih */
diff --git a/qemu/roms/u-boot/include/gdsys_fpga.h b/qemu/roms/u-boot/include/gdsys_fpga.h
new file mode 100644
index 000000000..85ddbcb93
--- /dev/null
+++ b/qemu/roms/u-boot/include/gdsys_fpga.h
@@ -0,0 +1,166 @@
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __GDSYS_FPGA_H
+#define __GDSYS_FPGA_H
+
+int init_func_fpga(void);
+
+enum {
+	FPGA_STATE_DONE_FAILED = 1 << 0,
+	FPGA_STATE_REFLECTION_FAILED = 1 << 1,
+	FPGA_STATE_PLATFORM = 1 << 2,
+};
+
+int get_fpga_state(unsigned dev);
+void print_fpga_state(unsigned dev);
+
+int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data);
+int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data);
+
+extern struct ihs_fpga *fpga_ptr[];
+
+#define FPGA_SET_REG(ix, fld, val) \
+	fpga_set_reg((ix), \
+		     &fpga_ptr[ix]->fld, \
+		     offsetof(struct ihs_fpga, fld), \
+		     val)
+
+#define FPGA_GET_REG(ix, fld, val) \
+	fpga_get_reg((ix), \
+		     &fpga_ptr[ix]->fld, \
+		     offsetof(struct ihs_fpga, fld), \
+		     val)
+
+struct ihs_gpio {
+	u16 read;
+	u16 clear;
+	u16 set;
+};
+
+struct ihs_i2c {
+	u16 write_mailbox;
+	u16 write_mailbox_ext;
+	u16 read_mailbox;
+	u16 read_mailbox_ext;
+};
+
+struct ihs_osd {
+	u16 version;
+	u16 features;
+	u16 control;
+	u16 xy_size;
+	u16 xy_scale;
+	u16 x_pos;
+	u16 y_pos;
+};
+
+#ifdef CONFIG_NEO
+struct ihs_fpga {
+	u16 reflection_low;	/* 0x0000 */
+	u16 versions;		/* 0x0002 */
+	u16 fpga_features;	/* 0x0004 */
+	u16 fpga_version;	/* 0x0006 */
+	u16 reserved_0[8187];	/* 0x0008 */
+	u16 reflection_high;	/* 0x3ffe */
+};
+#endif
+
+#ifdef CONFIG_IO
+struct ihs_fpga {
+	u16 reflection_low;	/* 0x0000 */
+	u16 versions;		/* 0x0002 */
+	u16 fpga_features;	/* 0x0004 */
+	u16 fpga_version;	/* 0x0006 */
+	u16 reserved_0[5];	/* 0x0008 */
+	u16 quad_serdes_reset;	/* 0x0012 */
+	u16 reserved_1[8181];	/* 0x0014 */
+	u16 reflection_high;	/* 0x3ffe */
+};
+#endif
+
+#ifdef CONFIG_IO64
+
+struct ihs_fpga_channel {
+	u16 status_int;
+	u16 config_int;
+	u16 switch_connect_config;
+	u16 tx_destination;
+};
+
+struct ihs_fpga_hicb {
+	u16 status_int;
+	u16 config_int;
+};
+
+struct ihs_fpga {
+	u16 reflection_low;	/* 0x0000 */
+	u16 versions;		/* 0x0002 */
+	u16 fpga_features;	/* 0x0004 */
+	u16 fpga_version;	/* 0x0006 */
+	u16 reserved_0[5];	/* 0x0008 */
+	u16 quad_serdes_reset;	/* 0x0012 */
+	u16 reserved_1[502];	/* 0x0014 */
+	struct ihs_fpga_channel ch[32];		/* 0x0400 */
+	struct ihs_fpga_channel hicb_ch[32];	/* 0x0500 */
+	u16 reserved_2[7487];	/* 0x0580 */
+	u16 reflection_high;	/* 0x3ffe */
+};
+#endif
+
+#ifdef CONFIG_IOCON
+struct ihs_fpga {
+	u16 reflection_low;	/* 0x0000 */
+	u16 versions;		/* 0x0002 */
+	u16 fpga_version;	/* 0x0004 */
+	u16 fpga_features;	/* 0x0006 */
+	u16 reserved_0[6];	/* 0x0008 */
+	struct ihs_gpio gpio;	/* 0x0014 */
+	u16 mpc3w_control;	/* 0x001a */
+	u16 reserved_1[19];	/* 0x001c */
+	u16 videocontrol;	/* 0x0042 */
+	u16 reserved_2[14];	/* 0x0044 */
+	u16 mc_int;		/* 0x0060 */
+	u16 mc_int_en;		/* 0x0062 */
+	u16 mc_status;		/* 0x0064 */
+	u16 mc_control;		/* 0x0066 */
+	u16 mc_tx_data;		/* 0x0068 */
+	u16 mc_tx_address;	/* 0x006a */
+	u16 mc_tx_cmd;		/* 0x006c */
+	u16 mc_res;		/* 0x006e */
+	u16 mc_rx_cmd_status;	/* 0x0070 */
+	u16 mc_rx_data;		/* 0x0072 */
+	u16 reserved_3[69];	/* 0x0074 */
+	u16 reflection_high;	/* 0x00fe */
+	struct ihs_osd osd;	/* 0x0100 */
+	u16 reserved_4[889];	/* 0x010e */
+	u16 videomem[31736];	/* 0x0800 */
+};
+#endif
+
+#ifdef CONFIG_DLVISION_10G
+struct ihs_fpga {
+	u16 reflection_low;	/* 0x0000 */
+	u16 versions;		/* 0x0002 */
+	u16 fpga_version;	/* 0x0004 */
+	u16 fpga_features;	/* 0x0006 */
+	u16 reserved_0[10];	/* 0x0008 */
+	u16 extended_interrupt; /* 0x001c */
+	u16 reserved_1[9];	/* 0x001e */
+	struct ihs_i2c i2c;	/* 0x0030 */
+	u16 reserved_2[16];	/* 0x0038 */
+	u16 mpc3w_control;	/* 0x0058 */
+	u16 reserved_3[34];	/* 0x005a */
+	u16 videocontrol;	/* 0x009e */
+	u16 reserved_4[176];	/* 0x00a0 */
+	struct ihs_osd osd;	/* 0x0200 */
+	u16 reserved_5[761];	/* 0x020e */
+	u16 videomem[31736];	/* 0x0800 */
+};
+#endif
+
+#endif
diff --git a/qemu/roms/u-boot/include/gt64120.h b/qemu/roms/u-boot/include/gt64120.h
new file mode 100644
index 000000000..938966db5
--- /dev/null
+++ b/qemu/roms/u-boot/include/gt64120.h
@@ -0,0 +1,539 @@
+/*
+ * Copyright (C) 2000, 2004, 2005  MIPS Technologies, Inc.
+ *	All rights reserved.
+ *	Authors: Carsten Langgaard <carstenl@mips.com>
+ *		 Maciej W. Rozycki <macro@mips.com>
+ * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+#ifndef _ASM_GT64120_H
+#define _ASM_GT64120_H
+
+#define MSK(n)			((1 << (n)) - 1)
+
+/*
+ *  Register offset addresses
+ */
+/* CPU Configuration.  */
+#define GT_CPU_OFS		0x000
+
+#define GT_MULTI_OFS		0x120
+
+/* CPU Address Decode.	*/
+#define GT_SCS10LD_OFS		0x008
+#define GT_SCS10HD_OFS		0x010
+#define GT_SCS32LD_OFS		0x018
+#define GT_SCS32HD_OFS		0x020
+#define GT_CS20LD_OFS		0x028
+#define GT_CS20HD_OFS		0x030
+#define GT_CS3BOOTLD_OFS	0x038
+#define GT_CS3BOOTHD_OFS	0x040
+#define GT_PCI0IOLD_OFS		0x048
+#define GT_PCI0IOHD_OFS		0x050
+#define GT_PCI0M0LD_OFS		0x058
+#define GT_PCI0M0HD_OFS		0x060
+#define GT_ISD_OFS		0x068
+
+#define GT_PCI0M1LD_OFS		0x080
+#define GT_PCI0M1HD_OFS		0x088
+#define GT_PCI1IOLD_OFS		0x090
+#define GT_PCI1IOHD_OFS		0x098
+#define GT_PCI1M0LD_OFS		0x0a0
+#define GT_PCI1M0HD_OFS		0x0a8
+#define GT_PCI1M1LD_OFS		0x0b0
+#define GT_PCI1M1HD_OFS		0x0b8
+#define GT_PCI1M1LD_OFS		0x0b0
+#define GT_PCI1M1HD_OFS		0x0b8
+
+#define GT_SCS10AR_OFS		0x0d0
+#define GT_SCS32AR_OFS		0x0d8
+#define GT_CS20R_OFS		0x0e0
+#define GT_CS3BOOTR_OFS		0x0e8
+
+#define GT_PCI0IOREMAP_OFS	0x0f0
+#define GT_PCI0M0REMAP_OFS	0x0f8
+#define GT_PCI0M1REMAP_OFS	0x100
+#define GT_PCI1IOREMAP_OFS	0x108
+#define GT_PCI1M0REMAP_OFS	0x110
+#define GT_PCI1M1REMAP_OFS	0x118
+
+/* CPU Error Report.  */
+#define GT_CPUERR_ADDRLO_OFS	0x070
+#define GT_CPUERR_ADDRHI_OFS	0x078
+
+#define GT_CPUERR_DATALO_OFS	0x128			/* GT-64120A only  */
+#define GT_CPUERR_DATAHI_OFS	0x130			/* GT-64120A only  */
+#define GT_CPUERR_PARITY_OFS	0x138			/* GT-64120A only  */
+
+/* CPU Sync Barrier.  */
+#define GT_PCI0SYNC_OFS		0x0c0
+#define GT_PCI1SYNC_OFS		0x0c8
+
+/* SDRAM and Device Address Decode.  */
+#define GT_SCS0LD_OFS		0x400
+#define GT_SCS0HD_OFS		0x404
+#define GT_SCS1LD_OFS		0x408
+#define GT_SCS1HD_OFS		0x40c
+#define GT_SCS2LD_OFS		0x410
+#define GT_SCS2HD_OFS		0x414
+#define GT_SCS3LD_OFS		0x418
+#define GT_SCS3HD_OFS		0x41c
+#define GT_CS0LD_OFS		0x420
+#define GT_CS0HD_OFS		0x424
+#define GT_CS1LD_OFS		0x428
+#define GT_CS1HD_OFS		0x42c
+#define GT_CS2LD_OFS		0x430
+#define GT_CS2HD_OFS		0x434
+#define GT_CS3LD_OFS		0x438
+#define GT_CS3HD_OFS		0x43c
+#define GT_BOOTLD_OFS		0x440
+#define GT_BOOTHD_OFS		0x444
+
+#define GT_ADERR_OFS		0x470
+
+/* SDRAM Configuration.	 */
+#define GT_SDRAM_CFG_OFS	0x448
+
+#define GT_SDRAM_OPMODE_OFS	0x474
+#define GT_SDRAM_BM_OFS		0x478
+#define GT_SDRAM_ADDRDECODE_OFS 0x47c
+
+/* SDRAM Parameters.  */
+#define GT_SDRAM_B0_OFS		0x44c
+#define GT_SDRAM_B1_OFS		0x450
+#define GT_SDRAM_B2_OFS		0x454
+#define GT_SDRAM_B3_OFS		0x458
+
+/* Device Parameters.  */
+#define GT_DEV_B0_OFS		0x45c
+#define GT_DEV_B1_OFS		0x460
+#define GT_DEV_B2_OFS		0x464
+#define GT_DEV_B3_OFS		0x468
+#define GT_DEV_BOOT_OFS		0x46c
+
+/* ECC.	 */
+#define GT_ECC_ERRDATALO	0x480			/* GT-64120A only  */
+#define GT_ECC_ERRDATAHI	0x484			/* GT-64120A only  */
+#define GT_ECC_MEM		0x488			/* GT-64120A only  */
+#define GT_ECC_CALC		0x48c			/* GT-64120A only  */
+#define GT_ECC_ERRADDR		0x490			/* GT-64120A only  */
+
+/* DMA Record.	*/
+#define GT_DMA0_CNT_OFS		0x800
+#define GT_DMA1_CNT_OFS		0x804
+#define GT_DMA2_CNT_OFS		0x808
+#define GT_DMA3_CNT_OFS		0x80c
+#define GT_DMA0_SA_OFS		0x810
+#define GT_DMA1_SA_OFS		0x814
+#define GT_DMA2_SA_OFS		0x818
+#define GT_DMA3_SA_OFS		0x81c
+#define GT_DMA0_DA_OFS		0x820
+#define GT_DMA1_DA_OFS		0x824
+#define GT_DMA2_DA_OFS		0x828
+#define GT_DMA3_DA_OFS		0x82c
+#define GT_DMA0_NEXT_OFS	0x830
+#define GT_DMA1_NEXT_OFS	0x834
+#define GT_DMA2_NEXT_OFS	0x838
+#define GT_DMA3_NEXT_OFS	0x83c
+
+#define GT_DMA0_CUR_OFS		0x870
+#define GT_DMA1_CUR_OFS		0x874
+#define GT_DMA2_CUR_OFS		0x878
+#define GT_DMA3_CUR_OFS		0x87c
+
+/* DMA Channel Control.	 */
+#define GT_DMA0_CTRL_OFS	0x840
+#define GT_DMA1_CTRL_OFS	0x844
+#define GT_DMA2_CTRL_OFS	0x848
+#define GT_DMA3_CTRL_OFS	0x84c
+
+/* DMA Arbiter.	 */
+#define GT_DMA_ARB_OFS		0x860
+
+/* Timer/Counter.  */
+#define GT_TC0_OFS		0x850
+#define GT_TC1_OFS		0x854
+#define GT_TC2_OFS		0x858
+#define GT_TC3_OFS		0x85c
+
+#define GT_TC_CONTROL_OFS	0x864
+
+/* PCI Internal.  */
+#define GT_PCI0_CMD_OFS		0xc00
+#define GT_PCI0_TOR_OFS		0xc04
+#define GT_PCI0_BS_SCS10_OFS	0xc08
+#define GT_PCI0_BS_SCS32_OFS	0xc0c
+#define GT_PCI0_BS_CS20_OFS	0xc10
+#define GT_PCI0_BS_CS3BT_OFS	0xc14
+
+#define GT_PCI1_IACK_OFS	0xc30
+#define GT_PCI0_IACK_OFS	0xc34
+
+#define GT_PCI0_BARE_OFS	0xc3c
+#define GT_PCI0_PREFMBR_OFS	0xc40
+
+#define GT_PCI0_SCS10_BAR_OFS	0xc48
+#define GT_PCI0_SCS32_BAR_OFS	0xc4c
+#define GT_PCI0_CS20_BAR_OFS	0xc50
+#define GT_PCI0_CS3BT_BAR_OFS	0xc54
+#define GT_PCI0_SSCS10_BAR_OFS	0xc58
+#define GT_PCI0_SSCS32_BAR_OFS	0xc5c
+
+#define GT_PCI0_SCS3BT_BAR_OFS	0xc64
+
+#define GT_PCI1_CMD_OFS		0xc80
+#define GT_PCI1_TOR_OFS		0xc84
+#define GT_PCI1_BS_SCS10_OFS	0xc88
+#define GT_PCI1_BS_SCS32_OFS	0xc8c
+#define GT_PCI1_BS_CS20_OFS	0xc90
+#define GT_PCI1_BS_CS3BT_OFS	0xc94
+
+#define GT_PCI1_BARE_OFS	0xcbc
+#define GT_PCI1_PREFMBR_OFS	0xcc0
+
+#define GT_PCI1_SCS10_BAR_OFS	0xcc8
+#define GT_PCI1_SCS32_BAR_OFS	0xccc
+#define GT_PCI1_CS20_BAR_OFS	0xcd0
+#define GT_PCI1_CS3BT_BAR_OFS	0xcd4
+#define GT_PCI1_SSCS10_BAR_OFS	0xcd8
+#define GT_PCI1_SSCS32_BAR_OFS	0xcdc
+
+#define GT_PCI1_SCS3BT_BAR_OFS	0xce4
+
+#define GT_PCI1_CFGADDR_OFS	0xcf0
+#define GT_PCI1_CFGDATA_OFS	0xcf4
+#define GT_PCI0_CFGADDR_OFS	0xcf8
+#define GT_PCI0_CFGDATA_OFS	0xcfc
+
+/* Interrupts.	*/
+#define GT_INTRCAUSE_OFS	0xc18
+#define GT_INTRMASK_OFS		0xc1c
+
+#define GT_PCI0_ICMASK_OFS	0xc24
+#define GT_PCI0_SERR0MASK_OFS	0xc28
+
+#define GT_CPU_INTSEL_OFS	0xc70
+#define GT_PCI0_INTSEL_OFS	0xc74
+
+#define GT_HINTRCAUSE_OFS	0xc98
+#define GT_HINTRMASK_OFS	0xc9c
+
+#define GT_PCI0_HICMASK_OFS	0xca4
+#define GT_PCI1_SERR1MASK_OFS	0xca8
+
+
+/*
+ * I2O Support Registers
+ */
+#define INBOUND_MESSAGE_REGISTER0_PCI_SIDE		0x010
+#define INBOUND_MESSAGE_REGISTER1_PCI_SIDE		0x014
+#define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE		0x018
+#define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE		0x01c
+#define INBOUND_DOORBELL_REGISTER_PCI_SIDE		0x020
+#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE	0x024
+#define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE	0x028
+#define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE		0x02c
+#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE	0x030
+#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE	0x034
+#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE	0x040
+#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE	0x044
+#define QUEUE_CONTROL_REGISTER_PCI_SIDE			0x050
+#define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE		0x054
+#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE	0x060
+#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE	0x064
+#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE	0x068
+#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE	0x06c
+#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE	0x070
+#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE	0x074
+#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE	0x078
+#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE	0x07c
+
+#define INBOUND_MESSAGE_REGISTER0_CPU_SIDE		0x1c10
+#define INBOUND_MESSAGE_REGISTER1_CPU_SIDE		0x1c14
+#define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE		0x1c18
+#define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE		0x1c1c
+#define INBOUND_DOORBELL_REGISTER_CPU_SIDE		0x1c20
+#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE	0x1c24
+#define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE	0x1c28
+#define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE		0x1c2c
+#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE	0x1c30
+#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE	0x1c34
+#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE	0x1c40
+#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE	0x1c44
+#define QUEUE_CONTROL_REGISTER_CPU_SIDE			0x1c50
+#define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE		0x1c54
+#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE	0x1c60
+#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE	0x1c64
+#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE	0x1c68
+#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE	0x1c6c
+#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE	0x1c70
+#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE	0x1c74
+#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE	0x1c78
+#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE	0x1c7c
+
+/*
+ *  Register encodings
+ */
+#define GT_CPU_ENDIAN_SHF	12
+#define GT_CPU_ENDIAN_MSK	(MSK(1) << GT_CPU_ENDIAN_SHF)
+#define GT_CPU_ENDIAN_BIT	GT_CPU_ENDIAN_MSK
+#define GT_CPU_WR_SHF		16
+#define GT_CPU_WR_MSK		(MSK(1) << GT_CPU_WR_SHF)
+#define GT_CPU_WR_BIT		GT_CPU_WR_MSK
+#define GT_CPU_WR_DXDXDXDX	0
+#define GT_CPU_WR_DDDD		1
+
+
+#define GT_PCI_DCRM_SHF		21
+#define GT_PCI_LD_SHF		0
+#define GT_PCI_LD_MSK		(MSK(15) << GT_PCI_LD_SHF)
+#define GT_PCI_HD_SHF		0
+#define GT_PCI_HD_MSK		(MSK(7) << GT_PCI_HD_SHF)
+#define GT_PCI_REMAP_SHF	0
+#define GT_PCI_REMAP_MSK	(MSK(11) << GT_PCI_REMAP_SHF)
+
+
+#define GT_CFGADDR_CFGEN_SHF	31
+#define GT_CFGADDR_CFGEN_MSK	(MSK(1) << GT_CFGADDR_CFGEN_SHF)
+#define GT_CFGADDR_CFGEN_BIT	GT_CFGADDR_CFGEN_MSK
+
+#define GT_CFGADDR_BUSNUM_SHF	16
+#define GT_CFGADDR_BUSNUM_MSK	(MSK(8) << GT_CFGADDR_BUSNUM_SHF)
+
+#define GT_CFGADDR_DEVNUM_SHF	11
+#define GT_CFGADDR_DEVNUM_MSK	(MSK(5) << GT_CFGADDR_DEVNUM_SHF)
+
+#define GT_CFGADDR_FUNCNUM_SHF	8
+#define GT_CFGADDR_FUNCNUM_MSK	(MSK(3) << GT_CFGADDR_FUNCNUM_SHF)
+
+#define GT_CFGADDR_REGNUM_SHF	2
+#define GT_CFGADDR_REGNUM_MSK	(MSK(6) << GT_CFGADDR_REGNUM_SHF)
+
+
+#define GT_SDRAM_BM_ORDER_SHF	2
+#define GT_SDRAM_BM_ORDER_MSK	(MSK(1) << GT_SDRAM_BM_ORDER_SHF)
+#define GT_SDRAM_BM_ORDER_BIT	GT_SDRAM_BM_ORDER_MSK
+#define GT_SDRAM_BM_ORDER_SUB	1
+#define GT_SDRAM_BM_ORDER_LIN	0
+
+#define GT_SDRAM_BM_RSVD_ALL1	0xffb
+
+
+#define GT_SDRAM_ADDRDECODE_ADDR_SHF	0
+#define GT_SDRAM_ADDRDECODE_ADDR_MSK	(MSK(3) << GT_SDRAM_ADDRDECODE_ADDR_SHF)
+#define GT_SDRAM_ADDRDECODE_ADDR_0	0
+#define GT_SDRAM_ADDRDECODE_ADDR_1	1
+#define GT_SDRAM_ADDRDECODE_ADDR_2	2
+#define GT_SDRAM_ADDRDECODE_ADDR_3	3
+#define GT_SDRAM_ADDRDECODE_ADDR_4	4
+#define GT_SDRAM_ADDRDECODE_ADDR_5	5
+#define GT_SDRAM_ADDRDECODE_ADDR_6	6
+#define GT_SDRAM_ADDRDECODE_ADDR_7	7
+
+
+#define GT_SDRAM_B0_CASLAT_SHF		0
+#define GT_SDRAM_B0_CASLAT_MSK		(MSK(2) << GT_SDRAM_B0__SHF)
+#define GT_SDRAM_B0_CASLAT_2		1
+#define GT_SDRAM_B0_CASLAT_3		2
+
+#define GT_SDRAM_B0_FTDIS_SHF		2
+#define GT_SDRAM_B0_FTDIS_MSK		(MSK(1) << GT_SDRAM_B0_FTDIS_SHF)
+#define GT_SDRAM_B0_FTDIS_BIT		GT_SDRAM_B0_FTDIS_MSK
+
+#define GT_SDRAM_B0_SRASPRCHG_SHF	3
+#define GT_SDRAM_B0_SRASPRCHG_MSK	(MSK(1) << GT_SDRAM_B0_SRASPRCHG_SHF)
+#define GT_SDRAM_B0_SRASPRCHG_BIT	GT_SDRAM_B0_SRASPRCHG_MSK
+#define GT_SDRAM_B0_SRASPRCHG_2		0
+#define GT_SDRAM_B0_SRASPRCHG_3		1
+
+#define GT_SDRAM_B0_B0COMPAB_SHF	4
+#define GT_SDRAM_B0_B0COMPAB_MSK	(MSK(1) << GT_SDRAM_B0_B0COMPAB_SHF)
+#define GT_SDRAM_B0_B0COMPAB_BIT	GT_SDRAM_B0_B0COMPAB_MSK
+
+#define GT_SDRAM_B0_64BITINT_SHF	5
+#define GT_SDRAM_B0_64BITINT_MSK	(MSK(1) << GT_SDRAM_B0_64BITINT_SHF)
+#define GT_SDRAM_B0_64BITINT_BIT	GT_SDRAM_B0_64BITINT_MSK
+#define GT_SDRAM_B0_64BITINT_2		0
+#define GT_SDRAM_B0_64BITINT_4		1
+
+#define GT_SDRAM_B0_BW_SHF		6
+#define GT_SDRAM_B0_BW_MSK		(MSK(1) << GT_SDRAM_B0_BW_SHF)
+#define GT_SDRAM_B0_BW_BIT		GT_SDRAM_B0_BW_MSK
+#define GT_SDRAM_B0_BW_32		0
+#define GT_SDRAM_B0_BW_64		1
+
+#define GT_SDRAM_B0_BLODD_SHF		7
+#define GT_SDRAM_B0_BLODD_MSK		(MSK(1) << GT_SDRAM_B0_BLODD_SHF)
+#define GT_SDRAM_B0_BLODD_BIT		GT_SDRAM_B0_BLODD_MSK
+
+#define GT_SDRAM_B0_PAR_SHF		8
+#define GT_SDRAM_B0_PAR_MSK		(MSK(1) << GT_SDRAM_B0_PAR_SHF)
+#define GT_SDRAM_B0_PAR_BIT		GT_SDRAM_B0_PAR_MSK
+
+#define GT_SDRAM_B0_BYPASS_SHF		9
+#define GT_SDRAM_B0_BYPASS_MSK		(MSK(1) << GT_SDRAM_B0_BYPASS_SHF)
+#define GT_SDRAM_B0_BYPASS_BIT		GT_SDRAM_B0_BYPASS_MSK
+
+#define GT_SDRAM_B0_SRAS2SCAS_SHF	10
+#define GT_SDRAM_B0_SRAS2SCAS_MSK	(MSK(1) << GT_SDRAM_B0_SRAS2SCAS_SHF)
+#define GT_SDRAM_B0_SRAS2SCAS_BIT	GT_SDRAM_B0_SRAS2SCAS_MSK
+#define GT_SDRAM_B0_SRAS2SCAS_2		0
+#define GT_SDRAM_B0_SRAS2SCAS_3		1
+
+#define GT_SDRAM_B0_SIZE_SHF		11
+#define GT_SDRAM_B0_SIZE_MSK		(MSK(1) << GT_SDRAM_B0_SIZE_SHF)
+#define GT_SDRAM_B0_SIZE_BIT		GT_SDRAM_B0_SIZE_MSK
+#define GT_SDRAM_B0_SIZE_16M		0
+#define GT_SDRAM_B0_SIZE_64M		1
+
+#define GT_SDRAM_B0_EXTPAR_SHF		12
+#define GT_SDRAM_B0_EXTPAR_MSK		(MSK(1) << GT_SDRAM_B0_EXTPAR_SHF)
+#define GT_SDRAM_B0_EXTPAR_BIT		GT_SDRAM_B0_EXTPAR_MSK
+
+#define GT_SDRAM_B0_BLEN_SHF		13
+#define GT_SDRAM_B0_BLEN_MSK		(MSK(1) << GT_SDRAM_B0_BLEN_SHF)
+#define GT_SDRAM_B0_BLEN_BIT		GT_SDRAM_B0_BLEN_MSK
+#define GT_SDRAM_B0_BLEN_8		0
+#define GT_SDRAM_B0_BLEN_4		1
+
+
+#define GT_SDRAM_CFG_REFINT_SHF		0
+#define GT_SDRAM_CFG_REFINT_MSK		(MSK(14) << GT_SDRAM_CFG_REFINT_SHF)
+
+#define GT_SDRAM_CFG_NINTERLEAVE_SHF	14
+#define GT_SDRAM_CFG_NINTERLEAVE_MSK	(MSK(1) << GT_SDRAM_CFG_NINTERLEAVE_SHF)
+#define GT_SDRAM_CFG_NINTERLEAVE_BIT	GT_SDRAM_CFG_NINTERLEAVE_MSK
+
+#define GT_SDRAM_CFG_RMW_SHF		15
+#define GT_SDRAM_CFG_RMW_MSK		(MSK(1) << GT_SDRAM_CFG_RMW_SHF)
+#define GT_SDRAM_CFG_RMW_BIT		GT_SDRAM_CFG_RMW_MSK
+
+#define GT_SDRAM_CFG_NONSTAGREF_SHF	16
+#define GT_SDRAM_CFG_NONSTAGREF_MSK	(MSK(1) << GT_SDRAM_CFG_NONSTAGREF_SHF)
+#define GT_SDRAM_CFG_NONSTAGREF_BIT	GT_SDRAM_CFG_NONSTAGREF_MSK
+
+#define GT_SDRAM_CFG_DUPCNTL_SHF	19
+#define GT_SDRAM_CFG_DUPCNTL_MSK	(MSK(1) << GT_SDRAM_CFG_DUPCNTL_SHF)
+#define GT_SDRAM_CFG_DUPCNTL_BIT	GT_SDRAM_CFG_DUPCNTL_MSK
+
+#define GT_SDRAM_CFG_DUPBA_SHF		20
+#define GT_SDRAM_CFG_DUPBA_MSK		(MSK(1) << GT_SDRAM_CFG_DUPBA_SHF)
+#define GT_SDRAM_CFG_DUPBA_BIT		GT_SDRAM_CFG_DUPBA_MSK
+
+#define GT_SDRAM_CFG_DUPEOT0_SHF	21
+#define GT_SDRAM_CFG_DUPEOT0_MSK	(MSK(1) << GT_SDRAM_CFG_DUPEOT0_SHF)
+#define GT_SDRAM_CFG_DUPEOT0_BIT	GT_SDRAM_CFG_DUPEOT0_MSK
+
+#define GT_SDRAM_CFG_DUPEOT1_SHF	22
+#define GT_SDRAM_CFG_DUPEOT1_MSK	(MSK(1) << GT_SDRAM_CFG_DUPEOT1_SHF)
+#define GT_SDRAM_CFG_DUPEOT1_BIT	GT_SDRAM_CFG_DUPEOT1_MSK
+
+#define GT_SDRAM_OPMODE_OP_SHF		0
+#define GT_SDRAM_OPMODE_OP_MSK		(MSK(3) << GT_SDRAM_OPMODE_OP_SHF)
+#define GT_SDRAM_OPMODE_OP_NORMAL	0
+#define GT_SDRAM_OPMODE_OP_NOP		1
+#define GT_SDRAM_OPMODE_OP_PRCHG	2
+#define GT_SDRAM_OPMODE_OP_MODE		3
+#define GT_SDRAM_OPMODE_OP_CBR		4
+
+#define GT_TC_CONTROL_ENTC0_SHF		0
+#define GT_TC_CONTROL_ENTC0_MSK		(MSK(1) << GT_TC_CONTROL_ENTC0_SHF)
+#define GT_TC_CONTROL_ENTC0_BIT		GT_TC_CONTROL_ENTC0_MSK
+#define GT_TC_CONTROL_SELTC0_SHF	1
+#define GT_TC_CONTROL_SELTC0_MSK	(MSK(1) << GT_TC_CONTROL_SELTC0_SHF)
+#define GT_TC_CONTROL_SELTC0_BIT	GT_TC_CONTROL_SELTC0_MSK
+
+
+#define GT_PCI0_BARE_SWSCS3BOOTDIS_SHF	0
+#define GT_PCI0_BARE_SWSCS3BOOTDIS_MSK	\
+	(MSK(1) << GT_PCI0_BARE_SWSCS3BOOTDIS_SHF)
+#define GT_PCI0_BARE_SWSCS3BOOTDIS_BIT	GT_PCI0_BARE_SWSCS3BOOTDIS_MSK
+
+#define GT_PCI0_BARE_SWSCS32DIS_SHF	1
+#define GT_PCI0_BARE_SWSCS32DIS_MSK	(MSK(1) << GT_PCI0_BARE_SWSCS32DIS_SHF)
+#define GT_PCI0_BARE_SWSCS32DIS_BIT	GT_PCI0_BARE_SWSCS32DIS_MSK
+
+#define GT_PCI0_BARE_SWSCS10DIS_SHF	2
+#define GT_PCI0_BARE_SWSCS10DIS_MSK	(MSK(1) << GT_PCI0_BARE_SWSCS10DIS_SHF)
+#define GT_PCI0_BARE_SWSCS10DIS_BIT	GT_PCI0_BARE_SWSCS10DIS_MSK
+
+#define GT_PCI0_BARE_INTIODIS_SHF	3
+#define GT_PCI0_BARE_INTIODIS_MSK	(MSK(1) << GT_PCI0_BARE_INTIODIS_SHF)
+#define GT_PCI0_BARE_INTIODIS_BIT	GT_PCI0_BARE_INTIODIS_MSK
+
+#define GT_PCI0_BARE_INTMEMDIS_SHF	4
+#define GT_PCI0_BARE_INTMEMDIS_MSK	(MSK(1) << GT_PCI0_BARE_INTMEMDIS_SHF)
+#define GT_PCI0_BARE_INTMEMDIS_BIT	GT_PCI0_BARE_INTMEMDIS_MSK
+
+#define GT_PCI0_BARE_CS3BOOTDIS_SHF	5
+#define GT_PCI0_BARE_CS3BOOTDIS_MSK	(MSK(1) << GT_PCI0_BARE_CS3BOOTDIS_SHF)
+#define GT_PCI0_BARE_CS3BOOTDIS_BIT	GT_PCI0_BARE_CS3BOOTDIS_MSK
+
+#define GT_PCI0_BARE_CS20DIS_SHF	6
+#define GT_PCI0_BARE_CS20DIS_MSK	(MSK(1) << GT_PCI0_BARE_CS20DIS_SHF)
+#define GT_PCI0_BARE_CS20DIS_BIT	GT_PCI0_BARE_CS20DIS_MSK
+
+#define GT_PCI0_BARE_SCS32DIS_SHF	7
+#define GT_PCI0_BARE_SCS32DIS_MSK	(MSK(1) << GT_PCI0_BARE_SCS32DIS_SHF)
+#define GT_PCI0_BARE_SCS32DIS_BIT	GT_PCI0_BARE_SCS32DIS_MSK
+
+#define GT_PCI0_BARE_SCS10DIS_SHF	8
+#define GT_PCI0_BARE_SCS10DIS_MSK	(MSK(1) << GT_PCI0_BARE_SCS10DIS_SHF)
+#define GT_PCI0_BARE_SCS10DIS_BIT	GT_PCI0_BARE_SCS10DIS_MSK
+
+
+#define GT_INTRCAUSE_MASABORT0_SHF	18
+#define GT_INTRCAUSE_MASABORT0_MSK	(MSK(1) << GT_INTRCAUSE_MASABORT0_SHF)
+#define GT_INTRCAUSE_MASABORT0_BIT	GT_INTRCAUSE_MASABORT0_MSK
+
+#define GT_INTRCAUSE_TARABORT0_SHF	19
+#define GT_INTRCAUSE_TARABORT0_MSK	(MSK(1) << GT_INTRCAUSE_TARABORT0_SHF)
+#define GT_INTRCAUSE_TARABORT0_BIT	GT_INTRCAUSE_TARABORT0_MSK
+
+
+#define GT_PCI0_CFGADDR_REGNUM_SHF	2
+#define GT_PCI0_CFGADDR_REGNUM_MSK	(MSK(6) << GT_PCI0_CFGADDR_REGNUM_SHF)
+#define GT_PCI0_CFGADDR_FUNCTNUM_SHF	8
+#define GT_PCI0_CFGADDR_FUNCTNUM_MSK	(MSK(3) << GT_PCI0_CFGADDR_FUNCTNUM_SHF)
+#define GT_PCI0_CFGADDR_DEVNUM_SHF	11
+#define GT_PCI0_CFGADDR_DEVNUM_MSK	(MSK(5) << GT_PCI0_CFGADDR_DEVNUM_SHF)
+#define GT_PCI0_CFGADDR_BUSNUM_SHF	16
+#define GT_PCI0_CFGADDR_BUSNUM_MSK	(MSK(8) << GT_PCI0_CFGADDR_BUSNUM_SHF)
+#define GT_PCI0_CFGADDR_CONFIGEN_SHF	31
+#define GT_PCI0_CFGADDR_CONFIGEN_MSK	(MSK(1) << GT_PCI0_CFGADDR_CONFIGEN_SHF)
+#define GT_PCI0_CFGADDR_CONFIGEN_BIT	GT_PCI0_CFGADDR_CONFIGEN_MSK
+
+#define GT_PCI0_CMD_MBYTESWAP_SHF	0
+#define GT_PCI0_CMD_MBYTESWAP_MSK	(MSK(1) << GT_PCI0_CMD_MBYTESWAP_SHF)
+#define GT_PCI0_CMD_MBYTESWAP_BIT	GT_PCI0_CMD_MBYTESWAP_MSK
+#define GT_PCI0_CMD_MWORDSWAP_SHF	10
+#define GT_PCI0_CMD_MWORDSWAP_MSK	(MSK(1) << GT_PCI0_CMD_MWORDSWAP_SHF)
+#define GT_PCI0_CMD_MWORDSWAP_BIT	GT_PCI0_CMD_MWORDSWAP_MSK
+#define GT_PCI0_CMD_SBYTESWAP_SHF	16
+#define GT_PCI0_CMD_SBYTESWAP_MSK	(MSK(1) << GT_PCI0_CMD_SBYTESWAP_SHF)
+#define GT_PCI0_CMD_SBYTESWAP_BIT	GT_PCI0_CMD_SBYTESWAP_MSK
+#define GT_PCI0_CMD_SWORDSWAP_SHF	11
+#define GT_PCI0_CMD_SWORDSWAP_MSK	(MSK(1) << GT_PCI0_CMD_SWORDSWAP_SHF)
+#define GT_PCI0_CMD_SWORDSWAP_BIT	GT_PCI0_CMD_SWORDSWAP_MSK
+
+#define GT_INTR_T0EXP_SHF		8
+#define GT_INTR_T0EXP_MSK		(MSK(1) << GT_INTR_T0EXP_SHF)
+#define GT_INTR_T0EXP_BIT		GT_INTR_T0EXP_MSK
+#define GT_INTR_RETRYCTR0_SHF		20
+#define GT_INTR_RETRYCTR0_MSK		(MSK(1) << GT_INTR_RETRYCTR0_SHF)
+#define GT_INTR_RETRYCTR0_BIT		GT_INTR_RETRYCTR0_MSK
+
+/*
+ *  Misc
+ */
+#define GT_DEF_PCI0_IO_BASE	0x10000000
+#define GT_DEF_PCI0_IO_SIZE	0x02000000
+#define GT_DEF_PCI0_MEM0_BASE	0x12000000
+#define GT_DEF_PCI0_MEM0_SIZE	0x02000000
+#define GT_DEF_BASE		0x14000000
+
+#define GT_MAX_BANKSIZE		(256 * 1024 * 1024)	/* Max 256MB bank  */
+#define GT_LATTIM_MIN		6			/* Minimum lat	*/
+
+#endif /* _ASM_GT64120_H */
diff --git a/qemu/roms/u-boot/include/hash.h b/qemu/roms/u-boot/include/hash.h
new file mode 100644
index 000000000..dc2167804
--- /dev/null
+++ b/qemu/roms/u-boot/include/hash.h
@@ -0,0 +1,128 @@
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _HASH_H
+#define _HASH_H
+
+#if defined(CONFIG_SHA1SUM_VERIFY) || defined(CONFIG_CRC32_VERIFY)
+#define CONFIG_HASH_VERIFY
+#endif
+
+struct hash_algo {
+	const char *name;			/* Name of algorithm */
+	int digest_size;			/* Length of digest */
+	/**
+	 * hash_func_ws: Generic hashing function
+	 *
+	 * This is the generic prototype for a hashing function. We only
+	 * have the watchdog version at present.
+	 *
+	 * @input:	Input buffer
+	 * @ilen:	Input buffer length
+	 * @output:	Checksum result (length depends on algorithm)
+	 * @chunk_sz:	Trigger watchdog after processing this many bytes
+	 */
+	void (*hash_func_ws)(const unsigned char *input, unsigned int ilen,
+		unsigned char *output, unsigned int chunk_sz);
+	int chunk_size;				/* Watchdog chunk size */
+	/*
+	 * hash_init: Create the context for progressive hashing
+	 *
+	 * @algo: Pointer to the hash_algo struct
+	 * @ctxp: Pointer to the pointer of the context for hashing
+	 * @return 0 if ok, -1 on error
+	 */
+	int (*hash_init)(struct hash_algo *algo, void **ctxp);
+	/*
+	 * hash_update: Perform hashing on the given buffer
+	 *
+	 * The context is freed by this function if an error occurs.
+	 *
+	 * @algo: Pointer to the hash_algo struct
+	 * @ctx: Pointer to the context for hashing
+	 * @buf: Pointer to the buffer being hashed
+	 * @size: Size of the buffer being hashed
+	 * @is_last: 1 if this is the last update; 0 otherwise
+	 * @return 0 if ok, -1 on error
+	 */
+	int (*hash_update)(struct hash_algo *algo, void *ctx, const void *buf,
+			   unsigned int size, int is_last);
+	/*
+	 * hash_finish: Write the hash result to the given buffer
+	 *
+	 * The context is freed by this function.
+	 *
+	 * @algo: Pointer to the hash_algo struct
+	 * @ctx: Pointer to the context for hashing
+	 * @dest_buf: Pointer to the buffer for the result
+	 * @size: Size of the buffer for the result
+	 * @return 0 if ok, -ENOSPC if size of the result buffer is too small
+	 *   or -1 on other errors
+	 */
+	int (*hash_finish)(struct hash_algo *algo, void *ctx, void *dest_buf,
+			   int size);
+};
+
+/*
+ * Maximum digest size for all algorithms we support. Having this value
+ * avoids a malloc() or C99 local declaration in common/cmd_hash.c.
+ */
+#define HASH_MAX_DIGEST_SIZE	32
+
+enum {
+	HASH_FLAG_VERIFY	= 1 << 0,	/* Enable verify mode */
+	HASH_FLAG_ENV		= 1 << 1,	/* Allow env vars */
+};
+
+/**
+ * hash_command: Process a hash command for a particular algorithm
+ *
+ * This common function is used to implement specific hash commands.
+ *
+ * @algo_name:		Hash algorithm being used (lower case!)
+ * @flags:		Flags value (HASH_FLAG_...)
+ * @cmdtp:		Pointer to command table entry
+ * @flag:		Some flags normally 0 (see CMD_FLAG_.. above)
+ * @argc:		Number of arguments (arg 0 must be the command text)
+ * @argv:		Arguments
+ */
+int hash_command(const char *algo_name, int flags, cmd_tbl_t *cmdtp, int flag,
+		 int argc, char * const argv[]);
+
+/**
+ * hash_block() - Hash a block according to the requested algorithm
+ *
+ * The caller probably knows the hash length for the chosen algorithm, but
+ * in order to provide a general interface, and output_size parameter is
+ * provided.
+ *
+ * @algo_name:		Hash algorithm to use
+ * @data:		Data to hash
+ * @len:		Lengh of data to hash in bytes
+ * @output:		Place to put hash value
+ * @output_size:	On entry, pointer to the number of bytes available in
+ *			output. On exit, pointer to the number of bytes used.
+ *			If NULL, then it is assumed that the caller has
+ *			allocated enough space for the hash. This is possible
+ *			since the caller is selecting the algorithm.
+ * @return 0 if ok, -ve on error: -EPROTONOSUPPORT for an unknown algorithm,
+ * -ENOSPC if the output buffer is not large enough.
+ */
+int hash_block(const char *algo_name, const void *data, unsigned int len,
+	       uint8_t *output, int *output_size);
+
+/**
+ * hash_lookup_algo() - Look up the hash_algo struct for an algorithm
+ *
+ * The function returns the pointer to the struct or -EPROTONOSUPPORT if the
+ * algorithm is not available.
+ *
+ * @algo_name: Hash algorithm to look up
+ * @algop: Pointer to the hash_algo struct if found
+ *
+ * @return 0 if ok, -EPROTONOSUPPORT for an unknown algorithm.
+ */
+int hash_lookup_algo(const char *algo_name, struct hash_algo **algop);
+#endif
diff --git a/qemu/roms/u-boot/include/hush.h b/qemu/roms/u-boot/include/hush.h
new file mode 100644
index 000000000..595303a65
--- /dev/null
+++ b/qemu/roms/u-boot/include/hush.h
@@ -0,0 +1,26 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _HUSH_H_
+#define _HUSH_H_
+
+#define FLAG_EXIT_FROM_LOOP 1
+#define FLAG_PARSE_SEMICOLON (1 << 1)	  /* symbol ';' is special for parser */
+#define FLAG_REPARSING       (1 << 2)	  /* >=2nd pass */
+
+extern int u_boot_hush_start(void);
+extern int parse_string_outer(const char *, int);
+extern int parse_file_outer(void);
+
+int set_local_var(const char *s, int flg_export);
+void unset_local_var(const char *name);
+char *get_local_var(const char *s);
+
+#if defined(CONFIG_HUSH_INIT_VAR)
+extern int hush_init_var (void);
+#endif
+#endif
diff --git a/qemu/roms/u-boot/include/hw_sha.h b/qemu/roms/u-boot/include/hw_sha.h
new file mode 100644
index 000000000..783350d51
--- /dev/null
+++ b/qemu/roms/u-boot/include/hw_sha.h
@@ -0,0 +1,37 @@
+/*
+ * Header file for SHA hardware acceleration
+ *
+ * Copyright (c) 2012  Samsung Electronics
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __HW_SHA_H
+#define __HW_SHA_H
+
+
+/**
+ * Computes hash value of input pbuf using h/w acceleration
+ *
+ * @param in_addr	A pointer to the input buffer
+ * @param bufleni	Byte length of input buffer
+ * @param out_addr	A pointer to the output buffer. When complete
+ *			32 bytes are copied to pout[0]...pout[31]. Thus, a user
+ *			should allocate at least 32 bytes at pOut in advance.
+ * @param chunk_size	chunk size for sha256
+ */
+void hw_sha256(const uchar * in_addr, uint buflen,
+			uchar * out_addr, uint chunk_size);
+
+/**
+ * Computes hash value of input pbuf using h/w acceleration
+ *
+ * @param in_addr	A pointer to the input buffer
+ * @param bufleni	Byte length of input buffer
+ * @param out_addr	A pointer to the output buffer. When complete
+ *			32 bytes are copied to pout[0]...pout[31]. Thus, a user
+ *			should allocate at least 32 bytes at pOut in advance.
+ * @param chunk_size	chunk_size for sha1
+ */
+void hw_sha1(const uchar * in_addr, uint buflen,
+			uchar * out_addr, uint chunk_size);
+#endif
diff --git a/qemu/roms/u-boot/include/hwconfig.h b/qemu/roms/u-boot/include/hwconfig.h
new file mode 100644
index 000000000..def7ad03d
--- /dev/null
+++ b/qemu/roms/u-boot/include/hwconfig.h
@@ -0,0 +1,100 @@
+/*
+ * An inteface for configuring a hardware via u-boot environment.
+ *
+ * Copyright (c) 2009  MontaVista Software, Inc.
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _HWCONFIG_H
+#define _HWCONFIG_H
+
+#include <linux/types.h>
+#include <asm/errno.h>
+
+#ifdef CONFIG_HWCONFIG
+
+extern int hwconfig_f(const char *opt, char *buf);
+extern const char *hwconfig_arg_f(const char *opt, size_t *arglen, char *buf);
+extern int hwconfig_arg_cmp_f(const char *opt, const char *arg, char *buf);
+extern int hwconfig_sub_f(const char *opt, const char *subopt, char *buf);
+extern const char *hwconfig_subarg_f(const char *opt, const char *subopt,
+				     size_t *subarglen, char *buf);
+extern int hwconfig_subarg_cmp_f(const char *opt, const char *subopt,
+				 const char *subarg, char *buf);
+#else
+
+static inline int hwconfig_f(const char *opt, char *buf)
+{
+	return -ENOSYS;
+}
+
+static inline const char *hwconfig_arg_f(const char *opt, size_t *arglen,
+					 char *buf)
+{
+	*arglen = 0;
+	return "";
+}
+
+static inline int hwconfig_arg_cmp_f(const char *opt, const char *arg,
+				     char *buf)
+{
+	return -ENOSYS;
+}
+
+static inline int hwconfig_sub_f(const char *opt, const char *subopt, char *buf)
+{
+	return -ENOSYS;
+}
+
+static inline const char *hwconfig_subarg_f(const char *opt, const char *subopt,
+					    size_t *subarglen, char *buf)
+{
+	*subarglen = 0;
+	return "";
+}
+
+static inline int hwconfig_subarg_cmp_f(const char *opt, const char *subopt,
+					const char *subarg, char *buf)
+{
+	return -ENOSYS;
+}
+
+#endif /* CONFIG_HWCONFIG */
+
+static inline int hwconfig(const char *opt)
+{
+	return hwconfig_f(opt, NULL);
+}
+
+static inline const char *hwconfig_arg(const char *opt, size_t *arglen)
+{
+	return hwconfig_arg_f(opt, arglen, NULL);
+}
+
+static inline int hwconfig_arg_cmp(const char *opt, const char *arg)
+{
+	return hwconfig_arg_cmp_f(opt, arg, NULL);
+}
+
+static inline int hwconfig_sub(const char *opt, const char *subopt)
+{
+	return hwconfig_sub_f(opt, subopt, NULL);
+}
+
+static inline const char *hwconfig_subarg(const char *opt, const char *subopt,
+					  size_t *subarglen)
+{
+	return hwconfig_subarg_f(opt, subopt, subarglen, NULL);
+}
+
+static inline int hwconfig_subarg_cmp(const char *opt, const char *subopt,
+				      const char *subarg)
+{
+	return hwconfig_subarg_cmp_f(opt, subopt, subarg, NULL);
+}
+
+#endif /* _HWCONFIG_H */
diff --git a/qemu/roms/u-boot/include/i2c.h b/qemu/roms/u-boot/include/i2c.h
new file mode 100644
index 000000000..1b4078ed6
--- /dev/null
+++ b/qemu/roms/u-boot/include/i2c.h
@@ -0,0 +1,454 @@
+/*
+ * Copyright (C) 2009 Sergey Kubushyn <ksi@koi8.net>
+ * Copyright (C) 2009 - 2013 Heiko Schocher <hs@denx.de>
+ * Changes for multibus/multiadapter I2C support.
+ *
+ * (C) Copyright 2001
+ * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * The original I2C interface was
+ *   (C) 2000 by Paolo Scaffardi (arsenio@tin.it)
+ *   AIRVENT SAM s.p.a - RIMINI(ITALY)
+ * but has been changed substantially.
+ */
+
+#ifndef _I2C_H_
+#define _I2C_H_
+
+/*
+ * WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING
+ *
+ * The implementation MUST NOT use static or global variables if the
+ * I2C routines are used to read SDRAM configuration information
+ * because this is done before the memories are initialized. Limited
+ * use of stack-based variables are OK (the initial stack size is
+ * limited).
+ *
+ * WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING
+ */
+
+/*
+ * Configuration items.
+ */
+#define I2C_RXTX_LEN	128	/* maximum tx/rx buffer length */
+
+#if !defined(CONFIG_SYS_I2C_MAX_HOPS)
+/* no muxes used bus = i2c adapters */
+#define CONFIG_SYS_I2C_DIRECT_BUS	1
+#define CONFIG_SYS_I2C_MAX_HOPS		0
+#define CONFIG_SYS_NUM_I2C_BUSES	ll_entry_count(struct i2c_adapter, i2c)
+#else
+/* we use i2c muxes */
+#undef CONFIG_SYS_I2C_DIRECT_BUS
+#endif
+
+/* define the I2C bus number for RTC and DTT if not already done */
+#if !defined(CONFIG_SYS_RTC_BUS_NUM)
+#define CONFIG_SYS_RTC_BUS_NUM		0
+#endif
+#if !defined(CONFIG_SYS_DTT_BUS_NUM)
+#define CONFIG_SYS_DTT_BUS_NUM		0
+#endif
+#if !defined(CONFIG_SYS_SPD_BUS_NUM)
+#define CONFIG_SYS_SPD_BUS_NUM		0
+#endif
+
+struct i2c_adapter {
+	void		(*init)(struct i2c_adapter *adap, int speed,
+				int slaveaddr);
+	int		(*probe)(struct i2c_adapter *adap, uint8_t chip);
+	int		(*read)(struct i2c_adapter *adap, uint8_t chip,
+				uint addr, int alen, uint8_t *buffer,
+				int len);
+	int		(*write)(struct i2c_adapter *adap, uint8_t chip,
+				uint addr, int alen, uint8_t *buffer,
+				int len);
+	uint		(*set_bus_speed)(struct i2c_adapter *adap,
+				uint speed);
+	int		speed;
+	int		waitdelay;
+	int		slaveaddr;
+	int		init_done;
+	int		hwadapnr;
+	char		*name;
+};
+
+#define U_BOOT_I2C_MKENT_COMPLETE(_init, _probe, _read, _write, \
+		_set_speed, _speed, _slaveaddr, _hwadapnr, _name) \
+	{ \
+		.init		=	_init, \
+		.probe		=	_probe, \
+		.read		=	_read, \
+		.write		=	_write, \
+		.set_bus_speed	=	_set_speed, \
+		.speed		=	_speed, \
+		.slaveaddr	=	_slaveaddr, \
+		.init_done	=	0, \
+		.hwadapnr	=	_hwadapnr, \
+		.name		=	#_name \
+};
+
+#define U_BOOT_I2C_ADAP_COMPLETE(_name, _init, _probe, _read, _write, \
+			_set_speed, _speed, _slaveaddr, _hwadapnr) \
+	ll_entry_declare(struct i2c_adapter, _name, i2c) = \
+	U_BOOT_I2C_MKENT_COMPLETE(_init, _probe, _read, _write, \
+		 _set_speed, _speed, _slaveaddr, _hwadapnr, _name);
+
+struct i2c_adapter *i2c_get_adapter(int index);
+
+#ifndef CONFIG_SYS_I2C_DIRECT_BUS
+struct i2c_mux {
+	int	id;
+	char	name[16];
+};
+
+struct i2c_next_hop {
+	struct i2c_mux		mux;
+	uint8_t		chip;
+	uint8_t		channel;
+};
+
+struct i2c_bus_hose {
+	int	adapter;
+	struct i2c_next_hop	next_hop[CONFIG_SYS_I2C_MAX_HOPS];
+};
+#define I2C_NULL_HOP	{{-1, ""}, 0, 0}
+extern struct i2c_bus_hose	i2c_bus[];
+
+#define I2C_ADAPTER(bus)	i2c_bus[bus].adapter
+#else
+#define I2C_ADAPTER(bus)	bus
+#endif
+#define	I2C_BUS			gd->cur_i2c_bus
+
+#define	I2C_ADAP_NR(bus)	i2c_get_adapter(I2C_ADAPTER(bus))
+#define	I2C_ADAP		I2C_ADAP_NR(gd->cur_i2c_bus)
+#define I2C_ADAP_HWNR		(I2C_ADAP->hwadapnr)
+
+#ifndef CONFIG_SYS_I2C_DIRECT_BUS
+#define I2C_MUX_PCA9540_ID	1
+#define I2C_MUX_PCA9540		{I2C_MUX_PCA9540_ID, "PCA9540B"}
+#define I2C_MUX_PCA9542_ID	2
+#define I2C_MUX_PCA9542		{I2C_MUX_PCA9542_ID, "PCA9542A"}
+#define I2C_MUX_PCA9544_ID	3
+#define I2C_MUX_PCA9544		{I2C_MUX_PCA9544_ID, "PCA9544A"}
+#define I2C_MUX_PCA9547_ID	4
+#define I2C_MUX_PCA9547		{I2C_MUX_PCA9547_ID, "PCA9547A"}
+#define I2C_MUX_PCA9548_ID	5
+#define I2C_MUX_PCA9548		{I2C_MUX_PCA9548_ID, "PCA9548"}
+#endif
+
+#ifndef I2C_SOFT_DECLARATIONS
+# if defined(CONFIG_MPC8260)
+#  define I2C_SOFT_DECLARATIONS volatile ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, I2C_PORT);
+# elif defined(CONFIG_8xx)
+#  define I2C_SOFT_DECLARATIONS	volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+
+# elif (defined(CONFIG_AT91RM9200) || \
+	defined(CONFIG_AT91SAM9260) ||  defined(CONFIG_AT91SAM9261) || \
+	defined(CONFIG_AT91SAM9263))
+#  define I2C_SOFT_DECLARATIONS	at91_pio_t *pio	= (at91_pio_t *) ATMEL_BASE_PIOA;
+# else
+#  define I2C_SOFT_DECLARATIONS
+# endif
+#endif
+
+#ifdef CONFIG_8xx
+/* Set default value for the I2C bus speed on 8xx. In the
+ * future, we'll define these in all 8xx board config files.
+ */
+#ifndef	CONFIG_SYS_I2C_SPEED
+#define	CONFIG_SYS_I2C_SPEED	50000
+#endif
+#endif
+
+/*
+ * Many boards/controllers/drivers don't support an I2C slave interface so
+ * provide a default slave address for them for use in common code.  A real
+ * value for CONFIG_SYS_I2C_SLAVE should be defined for any board which does
+ * support a slave interface.
+ */
+#ifndef	CONFIG_SYS_I2C_SLAVE
+#define	CONFIG_SYS_I2C_SLAVE	0xfe
+#endif
+
+/*
+ * Initialization, must be called once on start up, may be called
+ * repeatedly to change the speed and slave addresses.
+ */
+void i2c_init(int speed, int slaveaddr);
+void i2c_init_board(void);
+#ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT
+void i2c_board_late_init(void);
+#endif
+
+#ifdef CONFIG_SYS_I2C
+/*
+ * i2c_get_bus_num:
+ *
+ *  Returns index of currently active I2C bus.  Zero-based.
+ */
+unsigned int i2c_get_bus_num(void);
+
+/*
+ * i2c_set_bus_num:
+ *
+ *  Change the active I2C bus.  Subsequent read/write calls will
+ *  go to this one.
+ *
+ *	bus - bus index, zero based
+ *
+ *	Returns: 0 on success, not 0 on failure
+ *
+ */
+int i2c_set_bus_num(unsigned int bus);
+
+/*
+ * i2c_init_all():
+ *
+ * Initializes all I2C adapters in the system. All i2c_adap structures must
+ * be initialized beforehead with function pointers and data, including
+ * speed and slaveaddr. Returns 0 on success, non-0 on failure.
+ */
+void i2c_init_all(void);
+
+/*
+ * Probe the given I2C chip address.  Returns 0 if a chip responded,
+ * not 0 on failure.
+ */
+int i2c_probe(uint8_t chip);
+
+/*
+ * Read/Write interface:
+ *   chip:    I2C chip address, range 0..127
+ *   addr:    Memory (register) address within the chip
+ *   alen:    Number of bytes to use for addr (typically 1, 2 for larger
+ *              memories, 0 for register type devices with only one
+ *              register)
+ *   buffer:  Where to read/write the data
+ *   len:     How many bytes to read/write
+ *
+ *   Returns: 0 on success, not 0 on failure
+ */
+int i2c_read(uint8_t chip, unsigned int addr, int alen,
+				uint8_t *buffer, int len);
+
+int i2c_write(uint8_t chip, unsigned int addr, int alen,
+				uint8_t *buffer, int len);
+
+/*
+ * Utility routines to read/write registers.
+ */
+uint8_t i2c_reg_read(uint8_t addr, uint8_t reg);
+
+void i2c_reg_write(uint8_t addr, uint8_t reg, uint8_t val);
+
+/*
+ * i2c_set_bus_speed:
+ *
+ *  Change the speed of the active I2C bus
+ *
+ *	speed - bus speed in Hz
+ *
+ *	Returns: new bus speed
+ *
+ */
+unsigned int i2c_set_bus_speed(unsigned int speed);
+
+/*
+ * i2c_get_bus_speed:
+ *
+ *  Returns speed of currently active I2C bus in Hz
+ */
+
+unsigned int i2c_get_bus_speed(void);
+
+/*
+ * i2c_reloc_fixup:
+ *
+ * Adjusts I2C pointers after U-Boot is relocated to DRAM
+ */
+void i2c_reloc_fixup(void);
+#if defined(CONFIG_SYS_I2C_SOFT)
+void i2c_soft_init(void);
+void i2c_soft_active(void);
+void i2c_soft_tristate(void);
+int i2c_soft_read(void);
+void i2c_soft_sda(int bit);
+void i2c_soft_scl(int bit);
+void i2c_soft_delay(void);
+#endif
+#else
+
+/*
+ * Probe the given I2C chip address.  Returns 0 if a chip responded,
+ * not 0 on failure.
+ */
+int i2c_probe(uchar chip);
+
+/*
+ * Read/Write interface:
+ *   chip:    I2C chip address, range 0..127
+ *   addr:    Memory (register) address within the chip
+ *   alen:    Number of bytes to use for addr (typically 1, 2 for larger
+ *              memories, 0 for register type devices with only one
+ *              register)
+ *   buffer:  Where to read/write the data
+ *   len:     How many bytes to read/write
+ *
+ *   Returns: 0 on success, not 0 on failure
+ */
+int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len);
+int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len);
+
+/*
+ * Utility routines to read/write registers.
+ */
+static inline u8 i2c_reg_read(u8 addr, u8 reg)
+{
+	u8 buf;
+
+#ifdef CONFIG_8xx
+	/* MPC8xx needs this.  Maybe one day we can get rid of it. */
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
+
+#ifdef DEBUG
+	printf("%s: addr=0x%02x, reg=0x%02x\n", __func__, addr, reg);
+#endif
+
+	i2c_read(addr, reg, 1, &buf, 1);
+
+	return buf;
+}
+
+static inline void i2c_reg_write(u8 addr, u8 reg, u8 val)
+{
+#ifdef CONFIG_8xx
+	/* MPC8xx needs this.  Maybe one day we can get rid of it. */
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
+
+#ifdef DEBUG
+	printf("%s: addr=0x%02x, reg=0x%02x, val=0x%02x\n",
+	       __func__, addr, reg, val);
+#endif
+
+	i2c_write(addr, reg, 1, &val, 1);
+}
+
+/*
+ * Functions for setting the current I2C bus and its speed
+ */
+
+/*
+ * i2c_set_bus_num:
+ *
+ *  Change the active I2C bus.  Subsequent read/write calls will
+ *  go to this one.
+ *
+ *	bus - bus index, zero based
+ *
+ *	Returns: 0 on success, not 0 on failure
+ *
+ */
+int i2c_set_bus_num(unsigned int bus);
+
+/*
+ * i2c_get_bus_num:
+ *
+ *  Returns index of currently active I2C bus.  Zero-based.
+ */
+
+unsigned int i2c_get_bus_num(void);
+
+/*
+ * i2c_set_bus_speed:
+ *
+ *  Change the speed of the active I2C bus
+ *
+ *	speed - bus speed in Hz
+ *
+ *	Returns: 0 on success, not 0 on failure
+ *
+ */
+int i2c_set_bus_speed(unsigned int);
+
+/*
+ * i2c_get_bus_speed:
+ *
+ *  Returns speed of currently active I2C bus in Hz
+ */
+
+unsigned int i2c_get_bus_speed(void);
+#endif /* CONFIG_SYS_I2C */
+
+/*
+ * only for backwardcompatibility, should go away if we switched
+ * completely to new multibus support.
+ */
+#if defined(CONFIG_SYS_I2C) || defined(CONFIG_I2C_MULTI_BUS)
+# if !defined(CONFIG_SYS_MAX_I2C_BUS)
+#  define CONFIG_SYS_MAX_I2C_BUS		2
+# endif
+# define I2C_MULTI_BUS				1
+#else
+# define CONFIG_SYS_MAX_I2C_BUS		1
+# define I2C_MULTI_BUS				0
+#endif
+
+/* NOTE: These two functions MUST be always_inline to avoid code growth! */
+static inline unsigned int I2C_GET_BUS(void) __attribute__((always_inline));
+static inline unsigned int I2C_GET_BUS(void)
+{
+	return I2C_MULTI_BUS ? i2c_get_bus_num() : 0;
+}
+
+static inline void I2C_SET_BUS(unsigned int bus) __attribute__((always_inline));
+static inline void I2C_SET_BUS(unsigned int bus)
+{
+	if (I2C_MULTI_BUS)
+		i2c_set_bus_num(bus);
+}
+
+/* Multi I2C definitions */
+enum {
+	I2C_0, I2C_1, I2C_2, I2C_3, I2C_4, I2C_5, I2C_6, I2C_7,
+	I2C_8, I2C_9, I2C_10,
+};
+
+/* Multi I2C busses handling */
+#ifdef CONFIG_SOFT_I2C_MULTI_BUS
+extern int get_multi_scl_pin(void);
+extern int get_multi_sda_pin(void);
+extern int multi_i2c_init(void);
+#endif
+
+/**
+ * Get FDT values for i2c bus.
+ *
+ * @param blob  Device tree blbo
+ * @return the number of I2C bus
+ */
+void board_i2c_init(const void *blob);
+
+/**
+ * Find the I2C bus number by given a FDT I2C node.
+ *
+ * @param blob  Device tree blbo
+ * @param node  FDT I2C node to find
+ * @return the number of I2C bus (zero based), or -1 on error
+ */
+int i2c_get_bus_num_fdt(int node);
+
+/**
+ * Reset the I2C bus represented by the given a FDT I2C node.
+ *
+ * @param blob  Device tree blbo
+ * @param node  FDT I2C node to find
+ * @return 0 if port was reset, -1 if not found
+ */
+int i2c_reset_port_fdt(const void *blob, int node);
+#endif	/* _I2C_H_ */
diff --git a/qemu/roms/u-boot/include/i2s.h b/qemu/roms/u-boot/include/i2s.h
new file mode 100644
index 000000000..8dd2cc388
--- /dev/null
+++ b/qemu/roms/u-boot/include/i2s.h
@@ -0,0 +1,112 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * R. Chandrasekar <rcsekar@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __I2S_H__
+#define __I2S_H__
+
+/*
+ * DAI hardware audio formats.
+ *
+ * Describes the physical PCM data formating and clocking. Add new formats
+ * to the end.
+ */
+#define SND_SOC_DAIFMT_I2S		1 /* I2S mode */
+#define SND_SOC_DAIFMT_RIGHT_J		2 /* Right Justified mode */
+#define SND_SOC_DAIFMT_LEFT_J		3 /* Left Justified mode */
+#define SND_SOC_DAIFMT_DSP_A		4 /* L data MSB after FRM LRC */
+#define SND_SOC_DAIFMT_DSP_B		5 /* L data MSB during FRM LRC */
+#define SND_SOC_DAIFMT_AC97		6 /* AC97 */
+#define SND_SOC_DAIFMT_PDM		7 /* Pulse density modulation */
+
+/* left and right justified also known as MSB and LSB respectively */
+#define SND_SOC_DAIFMT_MSB		SND_SOC_DAIFMT_LEFT_J
+#define SND_SOC_DAIFMT_LSB		SND_SOC_DAIFMT_RIGHT_J
+
+/*
+ * DAI hardware signal inversions.
+ *
+ * Specifies whether the DAI can also support inverted clocks for the specified
+ * format.
+ */
+#define SND_SOC_DAIFMT_NB_NF	(1 << 8) /* normal bit clock + frame */
+#define SND_SOC_DAIFMT_NB_IF	(2 << 8) /* normal BCLK + inv FRM */
+#define SND_SOC_DAIFMT_IB_NF	(3 << 8) /* invert BCLK + nor FRM */
+#define SND_SOC_DAIFMT_IB_IF	(4 << 8) /* invert BCLK + FRM */
+
+/*
+ * DAI hardware clock masters.
+ *
+ * This is wrt the codec, the inverse is true for the interface
+ * i.e. if the codec is clk and FRM master then the interface is
+ * clk and frame slave.
+ */
+#define SND_SOC_DAIFMT_CBM_CFM	(1 << 12) /* codec clk & FRM master */
+#define SND_SOC_DAIFMT_CBS_CFM	(2 << 12) /* codec clk slave & FRM master */
+#define SND_SOC_DAIFMT_CBM_CFS	(3 << 12) /* codec clk master & frame slave */
+#define SND_SOC_DAIFMT_CBS_CFS	(4 << 12) /* codec clk & FRM slave */
+
+#define SND_SOC_DAIFMT_FORMAT_MASK	0x000f
+#define SND_SOC_DAIFMT_CLOCK_MASK	0x00f0
+#define SND_SOC_DAIFMT_INV_MASK		0x0f00
+#define SND_SOC_DAIFMT_MASTER_MASK	0xf000
+
+/*
+ * Master Clock Directions
+ */
+#define SND_SOC_CLOCK_IN		0
+#define SND_SOC_CLOCK_OUT		1
+
+/* I2S Tx Control */
+#define I2S_TX_ON	1
+#define I2S_TX_OFF	0
+
+#define FIFO_LENGTH	64
+
+/* I2s Registers */
+struct i2s_reg {
+	unsigned int con;	/* base + 0 , Control register */
+	unsigned int mod;	/* Mode register */
+	unsigned int fic;	/* FIFO control register */
+	unsigned int psr;	/* Reserved */
+	unsigned int txd;	/* Transmit data register */
+	unsigned int rxd;	/* Receive Data Register */
+};
+
+/* This structure stores the i2s related information */
+struct i2stx_info {
+	unsigned int rfs;		/* LR clock frame size */
+	unsigned int bfs;		/* Bit slock frame size */
+	unsigned int audio_pll_clk;	/* Audio pll frequency in Hz */
+	unsigned int samplingrate;	/* sampling rate */
+	unsigned int bitspersample;	/* bits per sample */
+	unsigned int channels;		/* audio channels */
+	unsigned int base_address;	/* I2S Register Base */
+	unsigned int id;		/* I2S controller id */
+};
+
+/*
+ * Sends the given data through i2s tx
+ *
+ * @param pi2s_tx	pointer of i2s transmitter parameter structure.
+ * @param data		address of the data buffer
+ * @param data_size	array size of the int buffer (total size / size of int)
+ *
+ * @return		int value 0 for success, -1 in case of error
+ */
+int i2s_transfer_tx_data(struct i2stx_info *pi2s_tx, unsigned *data,
+				unsigned long data_size);
+
+/*
+ * Initialise i2s transmiter
+ *
+ * @param pi2s_tx	pointer of i2s transmitter parameter structure.
+ *
+ * @return		int value 0 for success, -1 in case of error
+ */
+int i2s_tx_init(struct i2stx_info *pi2s_tx);
+
+#endif /* __I2S_H__ */
diff --git a/qemu/roms/u-boot/include/i8042.h b/qemu/roms/u-boot/include/i8042.h
new file mode 100644
index 000000000..963061920
--- /dev/null
+++ b/qemu/roms/u-boot/include/i8042.h
@@ -0,0 +1,79 @@
+/*
+ * (C) Copyright 2002 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* i8042.h - Intel 8042 keyboard driver header */
+
+#ifndef _I8042_H_
+#define _I8042_H_
+
+#ifdef __I386__
+#include <common.h>
+#include <asm/io.h>
+#define in8(p) inb(p)
+#define out8(p,v) outb(v,p)
+#endif
+
+/* defines */
+
+#define I8042_DATA_REG      (CONFIG_SYS_ISA_IO + 0x0060)    /* keyboard i/o buffer */
+#define I8042_STATUS_REG    (CONFIG_SYS_ISA_IO + 0x0064)    /* keyboard status read */
+#define I8042_COMMAND_REG   (CONFIG_SYS_ISA_IO + 0x0064)    /* keyboard ctrl write */
+
+enum {
+	/* Output register (I8042_DATA_REG) has data for system */
+	I8042_STATUS_OUT_DATA	= 1 << 0,
+	I8042_STATUS_IN_DATA	= 1 << 1,
+};
+
+#define KBD_US              0        /* default US layout */
+#define KBD_GER             1        /* german layout */
+
+#define KBD_TIMEOUT         1000     /* 1 sec */
+#define KBD_RESET_TRIES     3
+
+#define AS                  0        /* normal character index */
+#define SH                  1        /* shift index */
+#define CN                  2        /* control index */
+#define NM                  3        /* numeric lock index */
+#define AK                  4        /* right alt key */
+#define CP                  5        /* capslock index */
+#define ST                  6        /* stop output index */
+#define EX                  7        /* extended code index */
+#define ES                  8        /* escape and extended code index */
+
+#define NORMAL              0x0000    /* normal key */
+#define STP                 0x0001    /* scroll lock stop output*/
+#define NUM                 0x0002    /* numeric lock */
+#define CAPS                0x0004    /* capslock */
+#define SHIFT               0x0008    /* shift */
+#define CTRL                0x0010    /* control*/
+#define EXT                 0x0020    /* extended scan code 0xe0 */
+#define ESC                 0x0040    /* escape key press */
+#define E1                  0x0080    /* extended scan code 0xe1 */
+#define BRK                 0x0100    /* make break flag for keyboard */
+#define ALT                 0x0200    /* right alt */
+
+/* exports */
+
+/**
+ * Flush all buffer from keyboard controller to host.
+ */
+void i8042_flush(void);
+
+/**
+ * Disables the keyboard so that key strokes no longer generate scancodes to
+ * the host.
+ *
+ * @return 0 if ok, -1 if keyboard input was found while disabling
+ */
+int i8042_disable(void);
+
+int i8042_kbd_init(void);
+int i8042_tstc(void);
+int i8042_getc(void);
+
+#endif /* _I8042_H_ */
diff --git a/qemu/roms/u-boot/include/ide.h b/qemu/roms/u-boot/include/ide.h
new file mode 100644
index 000000000..0424d045a
--- /dev/null
+++ b/qemu/roms/u-boot/include/ide.h
@@ -0,0 +1,82 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef	_IDE_H
+#define _IDE_H
+
+#define IDE_BUS(dev)	(dev / (CONFIG_SYS_IDE_MAXDEVICE / CONFIG_SYS_IDE_MAXBUS))
+
+#define	ATA_CURR_BASE(dev)	(CONFIG_SYS_ATA_BASE_ADDR+ide_bus_offset[IDE_BUS(dev)])
+extern ulong ide_bus_offset[];
+
+#ifdef CONFIG_IDE_LED
+
+/*
+ * LED Port
+ */
+#define	LED_PORT	((uchar *)(PER8_BASE + 0x3000))
+#define LED_IDE1	0x01
+#define LED_IDE2	0x02
+#define	DEVICE_LED(d)	((d & 2) | ((d & 2) == 0)) /* depends on bit positions! */
+
+#endif /* CONFIG_IDE_LED */
+
+#ifdef CONFIG_SYS_64BIT_LBA
+typedef uint64_t lbaint_t;
+#define LBAF "%llx"
+#define LBAFU "%llu"
+#else
+typedef ulong lbaint_t;
+#define LBAF "%lx"
+#define LBAFU "%lu"
+#endif
+
+/*
+ * Function Prototypes
+ */
+
+void ide_init(void);
+ulong ide_read(int device, lbaint_t blknr, lbaint_t blkcnt, void *buffer);
+ulong ide_write(int device, lbaint_t blknr, lbaint_t blkcnt,
+		const void *buffer);
+
+#ifdef CONFIG_IDE_PREINIT
+int ide_preinit(void);
+#endif
+
+#ifdef CONFIG_IDE_INIT_POSTRESET
+int ide_init_postreset(void);
+#endif
+
+#if defined(CONFIG_OF_IDE_FIXUP)
+int ide_device_present(int dev);
+#endif
+
+#if defined(CONFIG_IDE_AHB)
+unsigned char ide_read_register(int dev, unsigned int port);
+void ide_write_register(int dev, unsigned int port, unsigned char val);
+void ide_read_data(int dev, ulong *sect_buf, int words);
+void ide_write_data(int dev, const ulong *sect_buf, int words);
+#endif
+
+/*
+ * I/O function overrides
+ */
+void ide_input_swap_data(int dev, ulong *sect_buf, int words);
+void ide_input_data(int dev, ulong *sect_buf, int words);
+void ide_output_data(int dev, const ulong *sect_buf, int words);
+void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts);
+void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts);
+
+/**
+ * board_start_ide() - Start up the board IDE interfac
+ *
+ * @return 0 if ok
+ */
+int board_start_ide(void);
+
+#endif /* _IDE_H */
diff --git a/qemu/roms/u-boot/include/image.h b/qemu/roms/u-boot/include/image.h
new file mode 100644
index 000000000..b27877870
--- /dev/null
+++ b/qemu/roms/u-boot/include/image.h
@@ -0,0 +1,1034 @@
+/*
+ * (C) Copyright 2008 Semihalf
+ *
+ * (C) Copyright 2000-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ ********************************************************************
+ * NOTE: This header file defines an interface to U-Boot. Including
+ * this (unmodified) header file in another file is considered normal
+ * use of U-Boot, and does *not* fall under the heading of "derived
+ * work".
+ ********************************************************************
+ */
+
+#ifndef __IMAGE_H__
+#define __IMAGE_H__
+
+#include "compiler.h"
+#include <asm/byteorder.h>
+
+/* Define this to avoid #ifdefs later on */
+struct lmb;
+
+#ifdef USE_HOSTCC
+
+/* new uImage format support enabled on host */
+#define CONFIG_FIT		1
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_FIT_VERBOSE	1 /* enable fit_format_{error,warning}() */
+
+#define IMAGE_ENABLE_IGNORE	0
+#define IMAGE_INDENT_STRING	""
+
+#else
+
+#include <lmb.h>
+#include <asm/u-boot.h>
+#include <command.h>
+
+/* Take notice of the 'ignore' property for hashes */
+#define IMAGE_ENABLE_IGNORE	1
+#define IMAGE_INDENT_STRING	"   "
+
+#endif /* USE_HOSTCC */
+
+#if defined(CONFIG_FIT)
+#include <libfdt.h>
+#include <fdt_support.h>
+# ifdef CONFIG_SPL_BUILD
+#  ifdef CONFIG_SPL_CRC32_SUPPORT
+#   define IMAGE_ENABLE_CRC32	1
+#  endif
+#  ifdef CONFIG_SPL_MD5_SUPPORT
+#   define IMAGE_ENABLE_MD5	1
+#  endif
+#  ifdef CONFIG_SPL_SHA1_SUPPORT
+#   define IMAGE_ENABLE_SHA1	1
+#  endif
+#  ifdef CONFIG_SPL_SHA256_SUPPORT
+#   define IMAGE_ENABLE_SHA256	1
+#  endif
+# else
+#  define CONFIG_CRC32		/* FIT images need CRC32 support */
+#  define CONFIG_MD5		/* and MD5 */
+#  define CONFIG_SHA1		/* and SHA1 */
+#  define CONFIG_SHA256		/* and SHA256 */
+#  define IMAGE_ENABLE_CRC32	1
+#  define IMAGE_ENABLE_MD5	1
+#  define IMAGE_ENABLE_SHA1	1
+#  define IMAGE_ENABLE_SHA256	1
+# endif
+
+#ifndef IMAGE_ENABLE_CRC32
+#define IMAGE_ENABLE_CRC32	0
+#endif
+
+#ifndef IMAGE_ENABLE_MD5
+#define IMAGE_ENABLE_MD5	0
+#endif
+
+#ifndef IMAGE_ENABLE_SHA1
+#define IMAGE_ENABLE_SHA1	0
+#endif
+
+#ifndef IMAGE_ENABLE_SHA256
+#define IMAGE_ENABLE_SHA256	0
+#endif
+
+#endif /* CONFIG_FIT */
+
+#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH
+# define IMAGE_ENABLE_RAMDISK_HIGH	1
+#else
+# define IMAGE_ENABLE_RAMDISK_HIGH	0
+#endif
+
+#ifdef CONFIG_OF_LIBFDT
+# define IMAGE_ENABLE_OF_LIBFDT	1
+#else
+# define IMAGE_ENABLE_OF_LIBFDT	0
+#endif
+
+#ifdef CONFIG_SYS_BOOT_GET_CMDLINE
+# define IMAGE_BOOT_GET_CMDLINE		1
+#else
+# define IMAGE_BOOT_GET_CMDLINE		0
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+# define IMAGE_OF_BOARD_SETUP		1
+#else
+# define IMAGE_OF_BOARD_SETUP		0
+#endif
+
+/*
+ * Operating System Codes
+ */
+#define IH_OS_INVALID		0	/* Invalid OS	*/
+#define IH_OS_OPENBSD		1	/* OpenBSD	*/
+#define IH_OS_NETBSD		2	/* NetBSD	*/
+#define IH_OS_FREEBSD		3	/* FreeBSD	*/
+#define IH_OS_4_4BSD		4	/* 4.4BSD	*/
+#define IH_OS_LINUX		5	/* Linux	*/
+#define IH_OS_SVR4		6	/* SVR4		*/
+#define IH_OS_ESIX		7	/* Esix		*/
+#define IH_OS_SOLARIS		8	/* Solaris	*/
+#define IH_OS_IRIX		9	/* Irix		*/
+#define IH_OS_SCO		10	/* SCO		*/
+#define IH_OS_DELL		11	/* Dell		*/
+#define IH_OS_NCR		12	/* NCR		*/
+#define IH_OS_LYNXOS		13	/* LynxOS	*/
+#define IH_OS_VXWORKS		14	/* VxWorks	*/
+#define IH_OS_PSOS		15	/* pSOS		*/
+#define IH_OS_QNX		16	/* QNX		*/
+#define IH_OS_U_BOOT		17	/* Firmware	*/
+#define IH_OS_RTEMS		18	/* RTEMS	*/
+#define IH_OS_ARTOS		19	/* ARTOS	*/
+#define IH_OS_UNITY		20	/* Unity OS	*/
+#define IH_OS_INTEGRITY		21	/* INTEGRITY	*/
+#define IH_OS_OSE		22	/* OSE		*/
+#define IH_OS_PLAN9		23	/* Plan 9	*/
+
+/*
+ * CPU Architecture Codes (supported by Linux)
+ */
+#define IH_ARCH_INVALID		0	/* Invalid CPU	*/
+#define IH_ARCH_ALPHA		1	/* Alpha	*/
+#define IH_ARCH_ARM		2	/* ARM		*/
+#define IH_ARCH_I386		3	/* Intel x86	*/
+#define IH_ARCH_IA64		4	/* IA64		*/
+#define IH_ARCH_MIPS		5	/* MIPS		*/
+#define IH_ARCH_MIPS64		6	/* MIPS	 64 Bit */
+#define IH_ARCH_PPC		7	/* PowerPC	*/
+#define IH_ARCH_S390		8	/* IBM S390	*/
+#define IH_ARCH_SH		9	/* SuperH	*/
+#define IH_ARCH_SPARC		10	/* Sparc	*/
+#define IH_ARCH_SPARC64		11	/* Sparc 64 Bit */
+#define IH_ARCH_M68K		12	/* M68K		*/
+#define IH_ARCH_MICROBLAZE	14	/* MicroBlaze   */
+#define IH_ARCH_NIOS2		15	/* Nios-II	*/
+#define IH_ARCH_BLACKFIN	16	/* Blackfin	*/
+#define IH_ARCH_AVR32		17	/* AVR32	*/
+#define IH_ARCH_ST200	        18	/* STMicroelectronics ST200  */
+#define IH_ARCH_SANDBOX		19	/* Sandbox architecture (test only) */
+#define IH_ARCH_NDS32	        20	/* ANDES Technology - NDS32  */
+#define IH_ARCH_OPENRISC        21	/* OpenRISC 1000  */
+#define IH_ARCH_ARM64		22	/* ARM64	*/
+#define IH_ARCH_ARC		23	/* Synopsys DesignWare ARC */
+
+/*
+ * Image Types
+ *
+ * "Standalone Programs" are directly runnable in the environment
+ *	provided by U-Boot; it is expected that (if they behave
+ *	well) you can continue to work in U-Boot after return from
+ *	the Standalone Program.
+ * "OS Kernel Images" are usually images of some Embedded OS which
+ *	will take over control completely. Usually these programs
+ *	will install their own set of exception handlers, device
+ *	drivers, set up the MMU, etc. - this means, that you cannot
+ *	expect to re-enter U-Boot except by resetting the CPU.
+ * "RAMDisk Images" are more or less just data blocks, and their
+ *	parameters (address, size) are passed to an OS kernel that is
+ *	being started.
+ * "Multi-File Images" contain several images, typically an OS
+ *	(Linux) kernel image and one or more data images like
+ *	RAMDisks. This construct is useful for instance when you want
+ *	to boot over the network using BOOTP etc., where the boot
+ *	server provides just a single image file, but you want to get
+ *	for instance an OS kernel and a RAMDisk image.
+ *
+ *	"Multi-File Images" start with a list of image sizes, each
+ *	image size (in bytes) specified by an "uint32_t" in network
+ *	byte order. This list is terminated by an "(uint32_t)0".
+ *	Immediately after the terminating 0 follow the images, one by
+ *	one, all aligned on "uint32_t" boundaries (size rounded up to
+ *	a multiple of 4 bytes - except for the last file).
+ *
+ * "Firmware Images" are binary images containing firmware (like
+ *	U-Boot or FPGA images) which usually will be programmed to
+ *	flash memory.
+ *
+ * "Script files" are command sequences that will be executed by
+ *	U-Boot's command interpreter; this feature is especially
+ *	useful when you configure U-Boot to use a real shell (hush)
+ *	as command interpreter (=> Shell Scripts).
+ */
+
+#define IH_TYPE_INVALID		0	/* Invalid Image		*/
+#define IH_TYPE_STANDALONE	1	/* Standalone Program		*/
+#define IH_TYPE_KERNEL		2	/* OS Kernel Image		*/
+#define IH_TYPE_RAMDISK		3	/* RAMDisk Image		*/
+#define IH_TYPE_MULTI		4	/* Multi-File Image		*/
+#define IH_TYPE_FIRMWARE	5	/* Firmware Image		*/
+#define IH_TYPE_SCRIPT		6	/* Script file			*/
+#define IH_TYPE_FILESYSTEM	7	/* Filesystem Image (any type)	*/
+#define IH_TYPE_FLATDT		8	/* Binary Flat Device Tree Blob	*/
+#define IH_TYPE_KWBIMAGE	9	/* Kirkwood Boot Image		*/
+#define IH_TYPE_IMXIMAGE	10	/* Freescale IMXBoot Image	*/
+#define IH_TYPE_UBLIMAGE	11	/* Davinci UBL Image		*/
+#define IH_TYPE_OMAPIMAGE	12	/* TI OMAP Config Header Image	*/
+#define IH_TYPE_AISIMAGE	13	/* TI Davinci AIS Image		*/
+#define IH_TYPE_KERNEL_NOLOAD	14	/* OS Kernel Image, can run from any load address */
+#define IH_TYPE_PBLIMAGE	15	/* Freescale PBL Boot Image	*/
+#define IH_TYPE_MXSIMAGE	16	/* Freescale MXSBoot Image	*/
+#define IH_TYPE_GPIMAGE		17	/* TI Keystone GPHeader Image	*/
+
+/*
+ * Compression Types
+ */
+#define IH_COMP_NONE		0	/*  No	 Compression Used	*/
+#define IH_COMP_GZIP		1	/* gzip	 Compression Used	*/
+#define IH_COMP_BZIP2		2	/* bzip2 Compression Used	*/
+#define IH_COMP_LZMA		3	/* lzma  Compression Used	*/
+#define IH_COMP_LZO		4	/* lzo   Compression Used	*/
+
+#define IH_MAGIC	0x27051956	/* Image Magic Number		*/
+#define IH_NMLEN		32	/* Image Name Length		*/
+
+/* Reused from common.h */
+#define ROUND(a, b)		(((a) + (b) - 1) & ~((b) - 1))
+
+/*
+ * Legacy format image header,
+ * all data in network byte order (aka natural aka bigendian).
+ */
+typedef struct image_header {
+	__be32		ih_magic;	/* Image Header Magic Number	*/
+	__be32		ih_hcrc;	/* Image Header CRC Checksum	*/
+	__be32		ih_time;	/* Image Creation Timestamp	*/
+	__be32		ih_size;	/* Image Data Size		*/
+	__be32		ih_load;	/* Data	 Load  Address		*/
+	__be32		ih_ep;		/* Entry Point Address		*/
+	__be32		ih_dcrc;	/* Image Data CRC Checksum	*/
+	uint8_t		ih_os;		/* Operating System		*/
+	uint8_t		ih_arch;	/* CPU architecture		*/
+	uint8_t		ih_type;	/* Image Type			*/
+	uint8_t		ih_comp;	/* Compression Type		*/
+	uint8_t		ih_name[IH_NMLEN];	/* Image Name		*/
+} image_header_t;
+
+typedef struct image_info {
+	ulong		start, end;		/* start/end of blob */
+	ulong		image_start, image_len; /* start of image within blob, len of image */
+	ulong		load;			/* load addr for the image */
+	uint8_t		comp, type, os;		/* compression, type of image, os type */
+} image_info_t;
+
+/*
+ * Legacy and FIT format headers used by do_bootm() and do_bootm_<os>()
+ * routines.
+ */
+typedef struct bootm_headers {
+	/*
+	 * Legacy os image header, if it is a multi component image
+	 * then boot_get_ramdisk() and get_fdt() will attempt to get
+	 * data from second and third component accordingly.
+	 */
+	image_header_t	*legacy_hdr_os;		/* image header pointer */
+	image_header_t	legacy_hdr_os_copy;	/* header copy */
+	ulong		legacy_hdr_valid;
+
+#if defined(CONFIG_FIT)
+	const char	*fit_uname_cfg;	/* configuration node unit name */
+
+	void		*fit_hdr_os;	/* os FIT image header */
+	const char	*fit_uname_os;	/* os subimage node unit name */
+	int		fit_noffset_os;	/* os subimage node offset */
+
+	void		*fit_hdr_rd;	/* init ramdisk FIT image header */
+	const char	*fit_uname_rd;	/* init ramdisk subimage node unit name */
+	int		fit_noffset_rd;	/* init ramdisk subimage node offset */
+
+	void		*fit_hdr_fdt;	/* FDT blob FIT image header */
+	const char	*fit_uname_fdt;	/* FDT blob subimage node unit name */
+	int		fit_noffset_fdt;/* FDT blob subimage node offset */
+#endif
+
+#ifndef USE_HOSTCC
+	image_info_t	os;		/* os image info */
+	ulong		ep;		/* entry point of OS */
+
+	ulong		rd_start, rd_end;/* ramdisk start/end */
+
+	char		*ft_addr;	/* flat dev tree address */
+	ulong		ft_len;		/* length of flat device tree */
+
+	ulong		initrd_start;
+	ulong		initrd_end;
+	ulong		cmdline_start;
+	ulong		cmdline_end;
+	bd_t		*kbd;
+#endif
+
+	int		verify;		/* getenv("verify")[0] != 'n' */
+
+#define	BOOTM_STATE_START	(0x00000001)
+#define	BOOTM_STATE_FINDOS	(0x00000002)
+#define	BOOTM_STATE_FINDOTHER	(0x00000004)
+#define	BOOTM_STATE_LOADOS	(0x00000008)
+#define	BOOTM_STATE_RAMDISK	(0x00000010)
+#define	BOOTM_STATE_FDT		(0x00000020)
+#define	BOOTM_STATE_OS_CMDLINE	(0x00000040)
+#define	BOOTM_STATE_OS_BD_T	(0x00000080)
+#define	BOOTM_STATE_OS_PREP	(0x00000100)
+#define	BOOTM_STATE_OS_FAKE_GO	(0x00000200)	/* 'Almost' run the OS */
+#define	BOOTM_STATE_OS_GO	(0x00000400)
+	int		state;
+
+#ifdef CONFIG_LMB
+	struct lmb	lmb;		/* for memory mgmt */
+#endif
+} bootm_headers_t;
+
+extern bootm_headers_t images;
+
+/*
+ * Some systems (for example LWMON) have very short watchdog periods;
+ * we must make sure to split long operations like memmove() or
+ * checksum calculations into reasonable chunks.
+ */
+#ifndef CHUNKSZ
+#define CHUNKSZ (64 * 1024)
+#endif
+
+#ifndef CHUNKSZ_CRC32
+#define CHUNKSZ_CRC32 (64 * 1024)
+#endif
+
+#ifndef CHUNKSZ_MD5
+#define CHUNKSZ_MD5 (64 * 1024)
+#endif
+
+#ifndef CHUNKSZ_SHA1
+#define CHUNKSZ_SHA1 (64 * 1024)
+#endif
+
+#define uimage_to_cpu(x)		be32_to_cpu(x)
+#define cpu_to_uimage(x)		cpu_to_be32(x)
+
+/*
+ * Translation table for entries of a specific type; used by
+ * get_table_entry_id() and get_table_entry_name().
+ */
+typedef struct table_entry {
+	int	id;
+	char	*sname;		/* short (input) name to find table entry */
+	char	*lname;		/* long (output) name to print for messages */
+} table_entry_t;
+
+/*
+ * get_table_entry_id() scans the translation table trying to find an
+ * entry that matches the given short name. If a matching entry is
+ * found, it's id is returned to the caller.
+ */
+int get_table_entry_id(const table_entry_t *table,
+		const char *table_name, const char *name);
+/*
+ * get_table_entry_name() scans the translation table trying to find
+ * an entry that matches the given id. If a matching entry is found,
+ * its long name is returned to the caller.
+ */
+char *get_table_entry_name(const table_entry_t *table, char *msg, int id);
+
+const char *genimg_get_os_name(uint8_t os);
+const char *genimg_get_arch_name(uint8_t arch);
+const char *genimg_get_type_name(uint8_t type);
+const char *genimg_get_comp_name(uint8_t comp);
+int genimg_get_os_id(const char *name);
+int genimg_get_arch_id(const char *name);
+int genimg_get_type_id(const char *name);
+int genimg_get_comp_id(const char *name);
+void genimg_print_size(uint32_t size);
+
+#if defined(CONFIG_TIMESTAMP) || defined(CONFIG_CMD_DATE) || \
+	defined(USE_HOSTCC)
+#define IMAGE_ENABLE_TIMESTAMP 1
+#else
+#define IMAGE_ENABLE_TIMESTAMP 0
+#endif
+void genimg_print_time(time_t timestamp);
+
+/* What to do with a image load address ('load = <> 'in the FIT) */
+enum fit_load_op {
+	FIT_LOAD_IGNORED,	/* Ignore load address */
+	FIT_LOAD_OPTIONAL,	/* Can be provided, but optional */
+	FIT_LOAD_REQUIRED,	/* Must be provided */
+};
+
+#ifndef USE_HOSTCC
+/* Image format types, returned by _get_format() routine */
+#define IMAGE_FORMAT_INVALID	0x00
+#define IMAGE_FORMAT_LEGACY	0x01	/* legacy image_header based format */
+#define IMAGE_FORMAT_FIT	0x02	/* new, libfdt based format */
+
+int genimg_get_format(const void *img_addr);
+int genimg_has_config(bootm_headers_t *images);
+ulong genimg_get_image(ulong img_addr);
+
+int boot_get_ramdisk(int argc, char * const argv[], bootm_headers_t *images,
+		uint8_t arch, ulong *rd_start, ulong *rd_end);
+
+/**
+ * fit_image_load() - load an image from a FIT
+ *
+ * This deals with all aspects of loading an image from a FIT, including
+ * selecting the right image based on configuration, verifying it, printing
+ * out progress messages, checking the type/arch/os and optionally copying it
+ * to the right load address.
+ *
+ * @param images	Boot images structure
+ * @param prop_name	Property name to look up (FIT_..._PROP)
+ * @param addr		Address of FIT in memory
+ * @param fit_unamep	On entry this is the requested image name
+ *			(e.g. "kernel@1") or NULL to use the default. On exit
+ *			points to the selected image name
+ * @param fit_uname_configp	On entry this is the requested configuration
+ *			name (e.g. "conf@1") or NULL to use the default. On
+ *			exit points to the selected configuration name.
+ * @param arch		Expected architecture (IH_ARCH_...)
+ * @param image_type	Required image type (IH_TYPE_...). If this is
+ *			IH_TYPE_KERNEL then we allow IH_TYPE_KERNEL_NOLOAD
+ *			also.
+ * @param bootstage_id	ID of starting bootstage to use for progress updates.
+ *			This will be added to the BOOTSTAGE_SUB values when
+ *			calling bootstage_mark()
+ * @param load_op	Decribes what to do with the load address
+ * @param datap		Returns address of loaded image
+ * @param lenp		Returns length of loaded image
+ */
+int fit_image_load(bootm_headers_t *images, const char *prop_name, ulong addr,
+		   const char **fit_unamep, const char **fit_uname_configp,
+		   int arch, int image_type, int bootstage_id,
+		   enum fit_load_op load_op, ulong *datap, ulong *lenp);
+
+/**
+ * fit_get_node_from_config() - Look up an image a FIT by type
+ *
+ * This looks in the selected conf@ node (images->fit_uname_cfg) for a
+ * particular image type (e.g. "kernel") and then finds the image that is
+ * referred to.
+ *
+ * For example, for something like:
+ *
+ * images {
+ *	kernel@1 {
+ *		...
+ *	};
+ * };
+ * configurations {
+ *	conf@1 {
+ *		kernel = "kernel@1";
+ *	};
+ * };
+ *
+ * the function will return the node offset of the kernel@1 node, assuming
+ * that conf@1 is the chosen configuration.
+ *
+ * @param images	Boot images structure
+ * @param prop_name	Property name to look up (FIT_..._PROP)
+ * @param addr		Address of FIT in memory
+ */
+int fit_get_node_from_config(bootm_headers_t *images, const char *prop_name,
+			ulong addr);
+
+int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch,
+		 bootm_headers_t *images,
+		 char **of_flat_tree, ulong *of_size);
+void boot_fdt_add_mem_rsv_regions(struct lmb *lmb, void *fdt_blob);
+int boot_relocate_fdt(struct lmb *lmb, char **of_flat_tree, ulong *of_size);
+
+int boot_ramdisk_high(struct lmb *lmb, ulong rd_data, ulong rd_len,
+		  ulong *initrd_start, ulong *initrd_end);
+int boot_get_cmdline(struct lmb *lmb, ulong *cmd_start, ulong *cmd_end);
+#ifdef CONFIG_SYS_BOOT_GET_KBD
+int boot_get_kbd(struct lmb *lmb, bd_t **kbd);
+#endif /* CONFIG_SYS_BOOT_GET_KBD */
+#endif /* !USE_HOSTCC */
+
+/*******************************************************************/
+/* Legacy format specific code (prefixed with image_) */
+/*******************************************************************/
+static inline uint32_t image_get_header_size(void)
+{
+	return (sizeof(image_header_t));
+}
+
+#define image_get_hdr_l(f) \
+	static inline uint32_t image_get_##f(const image_header_t *hdr) \
+	{ \
+		return uimage_to_cpu(hdr->ih_##f); \
+	}
+image_get_hdr_l(magic)		/* image_get_magic */
+image_get_hdr_l(hcrc)		/* image_get_hcrc */
+image_get_hdr_l(time)		/* image_get_time */
+image_get_hdr_l(size)		/* image_get_size */
+image_get_hdr_l(load)		/* image_get_load */
+image_get_hdr_l(ep)		/* image_get_ep */
+image_get_hdr_l(dcrc)		/* image_get_dcrc */
+
+#define image_get_hdr_b(f) \
+	static inline uint8_t image_get_##f(const image_header_t *hdr) \
+	{ \
+		return hdr->ih_##f; \
+	}
+image_get_hdr_b(os)		/* image_get_os */
+image_get_hdr_b(arch)		/* image_get_arch */
+image_get_hdr_b(type)		/* image_get_type */
+image_get_hdr_b(comp)		/* image_get_comp */
+
+static inline char *image_get_name(const image_header_t *hdr)
+{
+	return (char *)hdr->ih_name;
+}
+
+static inline uint32_t image_get_data_size(const image_header_t *hdr)
+{
+	return image_get_size(hdr);
+}
+
+/**
+ * image_get_data - get image payload start address
+ * @hdr: image header
+ *
+ * image_get_data() returns address of the image payload. For single
+ * component images it is image data start. For multi component
+ * images it points to the null terminated table of sub-images sizes.
+ *
+ * returns:
+ *     image payload data start address
+ */
+static inline ulong image_get_data(const image_header_t *hdr)
+{
+	return ((ulong)hdr + image_get_header_size());
+}
+
+static inline uint32_t image_get_image_size(const image_header_t *hdr)
+{
+	return (image_get_size(hdr) + image_get_header_size());
+}
+static inline ulong image_get_image_end(const image_header_t *hdr)
+{
+	return ((ulong)hdr + image_get_image_size(hdr));
+}
+
+#define image_set_hdr_l(f) \
+	static inline void image_set_##f(image_header_t *hdr, uint32_t val) \
+	{ \
+		hdr->ih_##f = cpu_to_uimage(val); \
+	}
+image_set_hdr_l(magic)		/* image_set_magic */
+image_set_hdr_l(hcrc)		/* image_set_hcrc */
+image_set_hdr_l(time)		/* image_set_time */
+image_set_hdr_l(size)		/* image_set_size */
+image_set_hdr_l(load)		/* image_set_load */
+image_set_hdr_l(ep)		/* image_set_ep */
+image_set_hdr_l(dcrc)		/* image_set_dcrc */
+
+#define image_set_hdr_b(f) \
+	static inline void image_set_##f(image_header_t *hdr, uint8_t val) \
+	{ \
+		hdr->ih_##f = val; \
+	}
+image_set_hdr_b(os)		/* image_set_os */
+image_set_hdr_b(arch)		/* image_set_arch */
+image_set_hdr_b(type)		/* image_set_type */
+image_set_hdr_b(comp)		/* image_set_comp */
+
+static inline void image_set_name(image_header_t *hdr, const char *name)
+{
+	strncpy(image_get_name(hdr), name, IH_NMLEN);
+}
+
+int image_check_hcrc(const image_header_t *hdr);
+int image_check_dcrc(const image_header_t *hdr);
+#ifndef USE_HOSTCC
+ulong getenv_bootm_low(void);
+phys_size_t getenv_bootm_size(void);
+phys_size_t getenv_bootm_mapsize(void);
+void memmove_wd(void *to, void *from, size_t len, ulong chunksz);
+#endif
+
+static inline int image_check_magic(const image_header_t *hdr)
+{
+	return (image_get_magic(hdr) == IH_MAGIC);
+}
+static inline int image_check_type(const image_header_t *hdr, uint8_t type)
+{
+	return (image_get_type(hdr) == type);
+}
+static inline int image_check_arch(const image_header_t *hdr, uint8_t arch)
+{
+	return (image_get_arch(hdr) == arch);
+}
+static inline int image_check_os(const image_header_t *hdr, uint8_t os)
+{
+	return (image_get_os(hdr) == os);
+}
+
+ulong image_multi_count(const image_header_t *hdr);
+void image_multi_getimg(const image_header_t *hdr, ulong idx,
+			ulong *data, ulong *len);
+
+void image_print_contents(const void *hdr);
+
+#ifndef USE_HOSTCC
+static inline int image_check_target_arch(const image_header_t *hdr)
+{
+#ifndef IH_ARCH_DEFAULT
+# error "please define IH_ARCH_DEFAULT in your arch asm/u-boot.h"
+#endif
+	return image_check_arch(hdr, IH_ARCH_DEFAULT);
+}
+#endif /* USE_HOSTCC */
+
+/**
+ * Set up properties in the FDT
+ *
+ * This sets up properties in the FDT that is to be passed to linux.
+ *
+ * @images:	Images information
+ * @blob:	FDT to update
+ * @of_size:	Size of the FDT
+ * @lmb:	Points to logical memory block structure
+ * @return 0 if ok, <0 on failure
+ */
+int image_setup_libfdt(bootm_headers_t *images, void *blob,
+		       int of_size, struct lmb *lmb);
+
+/**
+ * Set up the FDT to use for booting a kernel
+ *
+ * This performs ramdisk setup, sets up the FDT if required, and adds
+ * paramters to the FDT if libfdt is available.
+ *
+ * @param images	Images information
+ * @return 0 if ok, <0 on failure
+ */
+int image_setup_linux(bootm_headers_t *images);
+
+/**
+ * bootz_setup() - Extract stat and size of a Linux xImage
+ *
+ * @image: Address of image
+ * @start: Returns start address of image
+ * @end : Returns end address of image
+ * @return 0 if OK, 1 if the image was not recognised
+ */
+int bootz_setup(ulong image, ulong *start, ulong *end);
+
+
+/*******************************************************************/
+/* New uImage format specific code (prefixed with fit_) */
+/*******************************************************************/
+#if defined(CONFIG_FIT)
+
+#define FIT_IMAGES_PATH		"/images"
+#define FIT_CONFS_PATH		"/configurations"
+
+/* hash/signature node */
+#define FIT_HASH_NODENAME	"hash"
+#define FIT_ALGO_PROP		"algo"
+#define FIT_VALUE_PROP		"value"
+#define FIT_IGNORE_PROP		"uboot-ignore"
+#define FIT_SIG_NODENAME	"signature"
+
+/* image node */
+#define FIT_DATA_PROP		"data"
+#define FIT_TIMESTAMP_PROP	"timestamp"
+#define FIT_DESC_PROP		"description"
+#define FIT_ARCH_PROP		"arch"
+#define FIT_TYPE_PROP		"type"
+#define FIT_OS_PROP		"os"
+#define FIT_COMP_PROP		"compression"
+#define FIT_ENTRY_PROP		"entry"
+#define FIT_LOAD_PROP		"load"
+
+/* configuration node */
+#define FIT_KERNEL_PROP		"kernel"
+#define FIT_RAMDISK_PROP	"ramdisk"
+#define FIT_FDT_PROP		"fdt"
+#define FIT_DEFAULT_PROP	"default"
+
+#define FIT_MAX_HASH_LEN	20	/* max(crc32_len(4), sha1_len(20)) */
+
+/* cmdline argument format parsing */
+int fit_parse_conf(const char *spec, ulong addr_curr,
+		ulong *addr, const char **conf_name);
+int fit_parse_subimage(const char *spec, ulong addr_curr,
+		ulong *addr, const char **image_name);
+
+void fit_print_contents(const void *fit);
+void fit_image_print(const void *fit, int noffset, const char *p);
+
+/**
+ * fit_get_end - get FIT image size
+ * @fit: pointer to the FIT format image header
+ *
+ * returns:
+ *     size of the FIT image (blob) in memory
+ */
+static inline ulong fit_get_size(const void *fit)
+{
+	return fdt_totalsize(fit);
+}
+
+/**
+ * fit_get_end - get FIT image end
+ * @fit: pointer to the FIT format image header
+ *
+ * returns:
+ *     end address of the FIT image (blob) in memory
+ */
+static inline ulong fit_get_end(const void *fit)
+{
+	return (ulong)fit + fdt_totalsize(fit);
+}
+
+/**
+ * fit_get_name - get FIT node name
+ * @fit: pointer to the FIT format image header
+ *
+ * returns:
+ *     NULL, on error
+ *     pointer to node name, on success
+ */
+static inline const char *fit_get_name(const void *fit_hdr,
+		int noffset, int *len)
+{
+	return fdt_get_name(fit_hdr, noffset, len);
+}
+
+int fit_get_desc(const void *fit, int noffset, char **desc);
+int fit_get_timestamp(const void *fit, int noffset, time_t *timestamp);
+
+int fit_image_get_node(const void *fit, const char *image_uname);
+int fit_image_get_os(const void *fit, int noffset, uint8_t *os);
+int fit_image_get_arch(const void *fit, int noffset, uint8_t *arch);
+int fit_image_get_type(const void *fit, int noffset, uint8_t *type);
+int fit_image_get_comp(const void *fit, int noffset, uint8_t *comp);
+int fit_image_get_load(const void *fit, int noffset, ulong *load);
+int fit_image_get_entry(const void *fit, int noffset, ulong *entry);
+int fit_image_get_data(const void *fit, int noffset,
+				const void **data, size_t *size);
+
+int fit_image_hash_get_algo(const void *fit, int noffset, char **algo);
+int fit_image_hash_get_value(const void *fit, int noffset, uint8_t **value,
+				int *value_len);
+
+int fit_set_timestamp(void *fit, int noffset, time_t timestamp);
+
+/**
+ * fit_add_verification_data() - add verification data to FIT image nodes
+ *
+ * @keydir:	Directory containing keys
+ * @kwydest:	FDT blob to write public key information to
+ * @fit:	Pointer to the FIT format image header
+ * @comment:	Comment to add to signature nodes
+ * @require_keys: Mark all keys as 'required'
+ *
+ * Adds hash values for all component images in the FIT blob.
+ * Hashes are calculated for all component images which have hash subnodes
+ * with algorithm property set to one of the supported hash algorithms.
+ *
+ * Also add signatures if signature nodes are present.
+ *
+ * returns
+ *     0, on success
+ *     libfdt error code, on failure
+ */
+int fit_add_verification_data(const char *keydir, void *keydest, void *fit,
+			      const char *comment, int require_keys);
+
+int fit_image_verify(const void *fit, int noffset);
+int fit_config_verify(const void *fit, int conf_noffset);
+int fit_all_image_verify(const void *fit);
+int fit_image_check_os(const void *fit, int noffset, uint8_t os);
+int fit_image_check_arch(const void *fit, int noffset, uint8_t arch);
+int fit_image_check_type(const void *fit, int noffset, uint8_t type);
+int fit_image_check_comp(const void *fit, int noffset, uint8_t comp);
+int fit_check_format(const void *fit);
+
+int fit_conf_find_compat(const void *fit, const void *fdt);
+int fit_conf_get_node(const void *fit, const char *conf_uname);
+
+/**
+ * fit_conf_get_prop_node() - Get node refered to by a configuration
+ * @fit:	FIT to check
+ * @noffset:	Offset of conf@xxx node to check
+ * @prop_name:	Property to read from the conf node
+ *
+ * The conf@ nodes contain references to other nodes, using properties
+ * like 'kernel = "kernel@1"'. Given such a property name (e.g. "kernel"),
+ * return the offset of the node referred to (e.g. offset of node
+ * "/images/kernel@1".
+ */
+int fit_conf_get_prop_node(const void *fit, int noffset,
+		const char *prop_name);
+
+void fit_conf_print(const void *fit, int noffset, const char *p);
+
+int fit_check_ramdisk(const void *fit, int os_noffset,
+		uint8_t arch, int verify);
+
+int calculate_hash(const void *data, int data_len, const char *algo,
+			uint8_t *value, int *value_len);
+
+/*
+ * At present we only support signing on the host, and verification on the
+ * device
+ */
+#if defined(CONFIG_FIT_SIGNATURE)
+# ifdef USE_HOSTCC
+#  define IMAGE_ENABLE_SIGN	1
+#  define IMAGE_ENABLE_VERIFY	1
+# include  <openssl/evp.h>
+#else
+#  define IMAGE_ENABLE_SIGN	0
+#  define IMAGE_ENABLE_VERIFY	1
+# endif
+#else
+# define IMAGE_ENABLE_SIGN	0
+# define IMAGE_ENABLE_VERIFY	0
+#endif
+
+#ifdef USE_HOSTCC
+void *image_get_host_blob(void);
+void image_set_host_blob(void *host_blob);
+# define gd_fdt_blob()		image_get_host_blob()
+#else
+# define gd_fdt_blob()		(gd->fdt_blob)
+#endif
+
+#ifdef CONFIG_FIT_BEST_MATCH
+#define IMAGE_ENABLE_BEST_MATCH	1
+#else
+#define IMAGE_ENABLE_BEST_MATCH	0
+#endif
+
+/* Information passed to the signing routines */
+struct image_sign_info {
+	const char *keydir;		/* Directory conaining keys */
+	const char *keyname;		/* Name of key to use */
+	void *fit;			/* Pointer to FIT blob */
+	int node_offset;		/* Offset of signature node */
+	struct image_sig_algo *algo;	/* Algorithm information */
+	const void *fdt_blob;		/* FDT containing public keys */
+	int required_keynode;		/* Node offset of key to use: -1=any */
+	const char *require_keys;	/* Value for 'required' property */
+};
+
+/* A part of an image, used for hashing */
+struct image_region {
+	const void *data;
+	int size;
+};
+
+#if IMAGE_ENABLE_VERIFY
+# include <rsa-checksum.h>
+#endif
+struct checksum_algo {
+	const char *name;
+	const int checksum_len;
+	const int pad_len;
+#if IMAGE_ENABLE_SIGN
+	const EVP_MD *(*calculate_sign)(void);
+#endif
+	void (*calculate)(const struct image_region region[],
+			  int region_count, uint8_t *checksum);
+	const uint8_t *rsa_padding;
+};
+
+struct image_sig_algo {
+	const char *name;		/* Name of algorithm */
+
+	/**
+	 * sign() - calculate and return signature for given input data
+	 *
+	 * @info:	Specifies key and FIT information
+	 * @data:	Pointer to the input data
+	 * @data_len:	Data length
+	 * @sigp:	Set to an allocated buffer holding the signature
+	 * @sig_len:	Set to length of the calculated hash
+	 *
+	 * This computes input data signature according to selected algorithm.
+	 * Resulting signature value is placed in an allocated buffer, the
+	 * pointer is returned as *sigp. The length of the calculated
+	 * signature is returned via the sig_len pointer argument. The caller
+	 * should free *sigp.
+	 *
+	 * @return: 0, on success, -ve on error
+	 */
+	int (*sign)(struct image_sign_info *info,
+		    const struct image_region region[],
+		    int region_count, uint8_t **sigp, uint *sig_len);
+
+	/**
+	 * add_verify_data() - Add verification information to FDT
+	 *
+	 * Add public key information to the FDT node, suitable for
+	 * verification at run-time. The information added depends on the
+	 * algorithm being used.
+	 *
+	 * @info:	Specifies key and FIT information
+	 * @keydest:	Destination FDT blob for public key data
+	 * @return: 0, on success, -ve on error
+	 */
+	int (*add_verify_data)(struct image_sign_info *info, void *keydest);
+
+	/**
+	 * verify() - Verify a signature against some data
+	 *
+	 * @info:	Specifies key and FIT information
+	 * @data:	Pointer to the input data
+	 * @data_len:	Data length
+	 * @sig:	Signature
+	 * @sig_len:	Number of bytes in signature
+	 * @return 0 if verified, -ve on error
+	 */
+	int (*verify)(struct image_sign_info *info,
+		      const struct image_region region[], int region_count,
+		      uint8_t *sig, uint sig_len);
+
+	/* pointer to checksum algorithm */
+	struct checksum_algo *checksum;
+};
+
+/**
+ * image_get_sig_algo() - Look up a signature algortihm
+ *
+ * @param name		Name of algorithm
+ * @return pointer to algorithm information, or NULL if not found
+ */
+struct image_sig_algo *image_get_sig_algo(const char *name);
+
+/**
+ * fit_image_verify_required_sigs() - Verify signatures marked as 'required'
+ *
+ * @fit:		FIT to check
+ * @image_noffset:	Offset of image node to check
+ * @data:		Image data to check
+ * @size:		Size of image data
+ * @sig_blob:		FDT containing public keys
+ * @no_sigsp:		Returns 1 if no signatures were required, and
+ *			therefore nothing was checked. The caller may wish
+ *			to fall back to other mechanisms, or refuse to
+ *			boot.
+ * @return 0 if all verified ok, <0 on error
+ */
+int fit_image_verify_required_sigs(const void *fit, int image_noffset,
+		const char *data, size_t size, const void *sig_blob,
+		int *no_sigsp);
+
+/**
+ * fit_image_check_sig() - Check a single image signature node
+ *
+ * @fit:		FIT to check
+ * @noffset:		Offset of signature node to check
+ * @data:		Image data to check
+ * @size:		Size of image data
+ * @required_keynode:	Offset in the control FDT of the required key node,
+ *			if any. If this is given, then the image wil not
+ *			pass verification unless that key is used. If this is
+ *			-1 then any signature will do.
+ * @err_msgp:		In the event of an error, this will be pointed to a
+ *			help error string to display to the user.
+ * @return 0 if all verified ok, <0 on error
+ */
+int fit_image_check_sig(const void *fit, int noffset, const void *data,
+		size_t size, int required_keynode, char **err_msgp);
+
+/**
+ * fit_region_make_list() - Make a list of regions to hash
+ *
+ * Given a list of FIT regions (offset, size) provided by libfdt, create
+ * a list of regions (void *, size) for use by the signature creationg
+ * and verification code.
+ *
+ * @fit:		FIT image to process
+ * @fdt_regions:	Regions as returned by libfdt
+ * @count:		Number of regions returned by libfdt
+ * @region:		Place to put list of regions (NULL to allocate it)
+ * @return pointer to list of regions, or NULL if out of memory
+ */
+struct image_region *fit_region_make_list(const void *fit,
+		struct fdt_region *fdt_regions, int count,
+		struct image_region *region);
+
+static inline int fit_image_check_target_arch(const void *fdt, int node)
+{
+#ifndef USE_HOSTCC
+	return fit_image_check_arch(fdt, node, IH_ARCH_DEFAULT);
+#else
+	return 0;
+#endif
+}
+
+#ifdef CONFIG_FIT_VERBOSE
+#define fit_unsupported(msg)	printf("! %s:%d " \
+				"FIT images not supported for '%s'\n", \
+				__FILE__, __LINE__, (msg))
+
+#define fit_unsupported_reset(msg)	printf("! %s:%d " \
+				"FIT images not supported for '%s' " \
+				"- must reset board to recover!\n", \
+				__FILE__, __LINE__, (msg))
+#else
+#define fit_unsupported(msg)
+#define fit_unsupported_reset(msg)
+#endif /* CONFIG_FIT_VERBOSE */
+#endif /* CONFIG_FIT */
+
+#endif	/* __IMAGE_H__ */
diff --git a/qemu/roms/u-boot/include/initcall.h b/qemu/roms/u-boot/include/initcall.h
new file mode 100644
index 000000000..237807736
--- /dev/null
+++ b/qemu/roms/u-boot/include/initcall.h
@@ -0,0 +1,9 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+typedef int (*init_fnc_t)(void);
+
+int initcall_run_list(init_fnc_t init_sequence[]);
diff --git a/qemu/roms/u-boot/include/input.h b/qemu/roms/u-boot/include/input.h
new file mode 100644
index 000000000..26e2ad700
--- /dev/null
+++ b/qemu/roms/u-boot/include/input.h
@@ -0,0 +1,140 @@
+/*
+ * Keyboard input helper functions (too small to be called a layer)
+ *
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _INPUT_H
+#define _INPUT_H
+
+enum {
+	INPUT_MAX_MODIFIERS	= 4,
+	INPUT_BUFFER_LEN	= 16,
+};
+
+enum {
+	/* Keyboard LEDs */
+	INPUT_LED_SCROLL	= 1 << 0,
+	INPUT_LED_CAPS		= 1 << 1,
+	INPUT_LED_NUM		= 1 << 2,
+};
+
+/*
+ * This table translates key codes to ASCII. Most of the entries are ASCII
+ * codes, but entries after KEY_FIRST_MOD indicate that this key is a
+ * modifier key, like shift, ctrl. KEY_FIRST_MOD + MOD_SHIFT is the shift
+ * key, for example.
+ */
+struct input_key_xlate {
+	/* keycode of the modifiers which select this table, -1 if none */
+	int left_keycode;
+	int right_keycode;
+	const uchar *xlate;	/* keycode to ASCII table */
+	int num_entries;	/* number of entries in this table */
+};
+
+struct input_config {
+	uchar fifo[INPUT_BUFFER_LEN];
+	int fifo_in, fifo_out;
+
+	/* Which modifiers are active (1 bit for each MOD_... value) */
+	uchar modifiers;
+	uchar flags;		/* active state keys (FLAGS_...) */
+	uchar leds;		/* active LEDS (INPUT_LED_...) */
+	uchar num_tables;	/* number of modifier tables */
+	int prev_keycodes[INPUT_BUFFER_LEN];	/* keys held last time */
+	int num_prev_keycodes;	/* number of prev keys */
+	struct input_key_xlate table[INPUT_MAX_MODIFIERS];
+
+	/**
+	 * Function the input helper calls to scan the keyboard
+	 *
+	 * @param config	Input state
+	 * @return 0 if no keys read, otherwise number of keys read, or 1 if
+	 *		unknown
+	 */
+	int (*read_keys)(struct input_config *config);
+	unsigned int next_repeat_ms;	/* Next time we repeat a key */
+	unsigned int repeat_delay_ms;	/* Time before autorepeat starts */
+	unsigned int repeat_rate_ms;	/* Autorepeat rate in ms */
+};
+
+struct stdio_dev;
+
+/**
+ * Convert a list of key codes into ASCII and send them
+ *
+ * @param config	Input state
+ * @param keycode	List of key codes to examine
+ * @param num_keycodes	Number of key codes
+ * @return number of ascii characters sent, or 0 if none, or -1 for an
+ *	internal error
+ */
+int input_send_keycodes(struct input_config *config, int keycode[], int count);
+
+/**
+ * Add a new key translation table to the input
+ *
+ * @param config	Input state
+ * @param left_keycode	Key to hold to get into this table
+ * @param right_keycode	Another key to hold to get into this table
+ * @param xlate		Conversion table from key codes to ASCII
+ * @param num_entries	Number of entries in xlate table
+ */
+int input_add_table(struct input_config *config, int left_keycode,
+		    int right_keycode, const uchar *xlate, int num_entries);
+
+/**
+ * Test if keys are available to be read
+ *
+ * @param config	Input state
+ * @return 0 if no keys available, 1 if keys are available
+ */
+int input_tstc(struct input_config *config);
+
+/**
+ * Read a key
+ *
+ * TODO: U-Boot wants 0 for no key, but Ctrl-@ is a valid key...
+ *
+ * @param config	Input state
+ * @return key, or 0 if no key, or -1 if error
+ */
+int input_getc(struct input_config *config);
+
+/**
+ * Register a new device with stdio and switch to it if wanted
+ *
+ * @param dev	Pointer to device
+ * @return 0 if ok, -1 on error
+ */
+int input_stdio_register(struct stdio_dev *dev);
+
+/**
+ * Set up the keyboard autorepeat delays
+ *
+ * @param repeat_delay_ms	Delay before key auto-repeat starts (in ms)
+ * @param repeat_rate_ms	Delay between successive key repeats (in ms)
+ */
+void input_set_delays(struct input_config *config, int repeat_delay_ms,
+	       int repeat_rate_ms);
+
+/**
+ * Set up the input handler with basic key maps.
+ *
+ * @param config	Input state
+ * @param leds		Initial LED value (INPUT_LED_ mask), 0 suggested
+ * @return 0 if ok, -1 on error
+ */
+int input_init(struct input_config *config, int leds);
+
+#ifdef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+extern int overwrite_console(void);
+#define OVERWRITE_CONSOLE overwrite_console()
+#else
+#define OVERWRITE_CONSOLE 0
+#endif /* CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE */
+
+#endif
diff --git a/qemu/roms/u-boot/include/iomux.h b/qemu/roms/u-boot/include/iomux.h
new file mode 100644
index 000000000..d104baf02
--- /dev/null
+++ b/qemu/roms/u-boot/include/iomux.h
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2008
+ * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _IO_MUX_H
+#define _IO_MUX_H
+
+#include <stdio_dev.h>
+
+/*
+ * Stuff required to support console multiplexing.
+ */
+
+/*
+ * Pointers to devices used for each file type.  Defined in console.c
+ * but storage is allocated in iomux.c.
+ */
+extern struct stdio_dev **console_devices[MAX_FILES];
+/*
+ * The count of devices assigned to each FILE.  Defined in console.c
+ * and populated in iomux.c.
+ */
+extern int cd_count[MAX_FILES];
+
+int iomux_doenv(const int, const char *);
+void iomux_printdevs(const int);
+struct stdio_dev *search_device(int, const char *);
+
+#endif /* _IO_MUX_H */
diff --git a/qemu/roms/u-boot/include/ioports.h b/qemu/roms/u-boot/include/ioports.h
new file mode 100644
index 000000000..1134ea520
--- /dev/null
+++ b/qemu/roms/u-boot/include/ioports.h
@@ -0,0 +1,65 @@
+/*
+ * definitions for MPC8260 I/O Ports
+ *
+ * (in addition to those provided in <asm/immap_8260.h>)
+ *
+ * Murray.Jensen@cmst.csiro.au, 20-Oct-00
+ */
+
+/*
+ * this structure mirrors the layout of the five port registers in
+ * the internal memory map - see iop8260_t in <asm/immap_8260.h>
+ */
+typedef struct {
+    unsigned int pdir;		/* Port Data Direction Register (35-3) */
+    unsigned int ppar;		/* Port Pin Assignment Register (35-4) */
+    unsigned int psor;		/* Port Special Options Register (35-5) */
+    unsigned int podr;		/* Port Open Drain Register (35-2) */
+    unsigned int pdat;		/* Port Data Register (35-3) */
+} ioport_t;
+
+/*
+ * this macro calculates the address within the internal
+ * memory map (im) of the set of registers for a port (idx)
+ *
+ * the internal memory map aligns the above structure on
+ * a 0x20 byte boundary
+ */
+#ifdef CONFIG_MPC85xx
+#define ioport_addr(im, idx) (ioport_t *)((uint)&(im->im_cpm_iop) + ((idx)*0x20))
+#else
+#define ioport_addr(im, idx) (ioport_t *)((uint)&(im)->im_ioport + ((idx)*0x20))
+#endif
+
+/*
+ * this structure provides configuration
+ * information for one port pin
+ */
+typedef struct {
+    unsigned char conf:1;	/* if 1, configure this port */
+    unsigned char ppar:1;	/* Port Pin Assignment Register (35-4) */
+    unsigned char psor:1;	/* Port Special Options Register (35-2) */
+    unsigned char pdir:1;	/* Port Data Direction Register (35-3) */
+    unsigned char podr:1;	/* Port Open Drain Register (35-2) */
+    unsigned char pdat:1;	/* Port Data Register (35-2) */
+} iop_conf_t;
+
+/*
+ * a table that contains configuration information for all 32 pins
+ * of all four MPC8260 I/O ports.
+ *
+ * NOTE: in the second dimension of this table, index 0 refers to pin 31
+ * and index 31 refers to pin 0. this made the code in the table look more
+ * like the table in the 8260UM (and in the hymod manuals).
+ */
+extern const iop_conf_t iop_conf_tab[4][32];
+
+typedef struct {
+	unsigned char	port;
+	unsigned char	pin;
+	int		dir;
+	int		open_drain;
+	int		assign;
+} qe_iop_conf_t;
+
+#define QE_IOP_TAB_END	(-1)
diff --git a/qemu/roms/u-boot/include/ipu_pixfmt.h b/qemu/roms/u-boot/include/ipu_pixfmt.h
new file mode 100644
index 000000000..f7a237c80
--- /dev/null
+++ b/qemu/roms/u-boot/include/ipu_pixfmt.h
@@ -0,0 +1,68 @@
+/*
+ * (C) Copyright 2011
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de
+ *
+ * Based on Linux IPU driver for MX51 (ipu.h):
+ *
+ * (C) Copyright 2005-2010 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __IPU_PIXFMT_H__
+#define __IPU_PIXFMT_H__
+
+#include <linux/list.h>
+#include <linux/fb.h>
+
+/*  IPU Pixel format definitions */
+#define fourcc(a, b, c, d)\
+	(((__u32)(a)<<0)|((__u32)(b)<<8)|((__u32)(c)<<16)|((__u32)(d)<<24))
+
+/*
+ * Pixel formats are defined with ASCII FOURCC code. The pixel format codes are
+ * the same used by V4L2 API.
+ */
+
+#define IPU_PIX_FMT_GENERIC fourcc('I', 'P', 'U', '0')
+#define IPU_PIX_FMT_GENERIC_32 fourcc('I', 'P', 'U', '1')
+#define IPU_PIX_FMT_LVDS666 fourcc('L', 'V', 'D', '6')
+#define IPU_PIX_FMT_LVDS888 fourcc('L', 'V', 'D', '8')
+
+#define IPU_PIX_FMT_RGB332  fourcc('R', 'G', 'B', '1')	/*<  8  RGB-3-3-2    */
+#define IPU_PIX_FMT_RGB555  fourcc('R', 'G', 'B', 'O')	/*< 16  RGB-5-5-5    */
+#define IPU_PIX_FMT_RGB565  fourcc('R', 'G', 'B', 'P')	/*< 1 6  RGB-5-6-5   */
+#define IPU_PIX_FMT_RGB666  fourcc('R', 'G', 'B', '6')	/*< 18  RGB-6-6-6    */
+#define IPU_PIX_FMT_BGR666  fourcc('B', 'G', 'R', '6')	/*< 18  BGR-6-6-6    */
+#define IPU_PIX_FMT_BGR24   fourcc('B', 'G', 'R', '3')	/*< 24  BGR-8-8-8    */
+#define IPU_PIX_FMT_RGB24   fourcc('R', 'G', 'B', '3')	/*< 24  RGB-8-8-8    */
+#define IPU_PIX_FMT_BGR32   fourcc('B', 'G', 'R', '4')	/*< 32  BGR-8-8-8-8  */
+#define IPU_PIX_FMT_BGRA32  fourcc('B', 'G', 'R', 'A')	/*< 32  BGR-8-8-8-8  */
+#define IPU_PIX_FMT_RGB32   fourcc('R', 'G', 'B', '4')	/*< 32  RGB-8-8-8-8  */
+#define IPU_PIX_FMT_RGBA32  fourcc('R', 'G', 'B', 'A')	/*< 32  RGB-8-8-8-8  */
+#define IPU_PIX_FMT_ABGR32  fourcc('A', 'B', 'G', 'R')	/*< 32  ABGR-8-8-8-8 */
+
+/* YUV Interleaved Formats */
+#define IPU_PIX_FMT_YUYV    fourcc('Y', 'U', 'Y', 'V')	/*< 16 YUV 4:2:2 */
+#define IPU_PIX_FMT_UYVY    fourcc('U', 'Y', 'V', 'Y')	/*< 16 YUV 4:2:2 */
+#define IPU_PIX_FMT_Y41P    fourcc('Y', '4', '1', 'P')	/*< 12 YUV 4:1:1 */
+#define IPU_PIX_FMT_YUV444  fourcc('Y', '4', '4', '4')	/*< 24 YUV 4:4:4 */
+
+/* two planes -- one Y, one Cb + Cr interleaved  */
+#define IPU_PIX_FMT_NV12    fourcc('N', 'V', '1', '2') /* 12  Y/CbCr 4:2:0  */
+
+#define IPU_PIX_FMT_GREY    fourcc('G', 'R', 'E', 'Y')	/*< 8  Greyscale */
+#define IPU_PIX_FMT_YVU410P fourcc('Y', 'V', 'U', '9')	/*< 9  YVU 4:1:0 */
+#define IPU_PIX_FMT_YUV410P fourcc('Y', 'U', 'V', '9')	/*< 9  YUV 4:1:0 */
+#define IPU_PIX_FMT_YVU420P fourcc('Y', 'V', '1', '2')	/*< 12 YVU 4:2:0 */
+#define IPU_PIX_FMT_YUV420P fourcc('I', '4', '2', '0')	/*< 12 YUV 4:2:0 */
+#define IPU_PIX_FMT_YUV420P2 fourcc('Y', 'U', '1', '2')	/*< 12 YUV 4:2:0 */
+#define IPU_PIX_FMT_YVU422P fourcc('Y', 'V', '1', '6')	/*< 16 YVU 4:2:2 */
+#define IPU_PIX_FMT_YUV422P fourcc('4', '2', '2', 'P')	/*< 16 YUV 4:2:2 */
+
+int ipuv3_fb_init(struct fb_videomode const *mode,
+		  uint8_t disp,
+		  uint32_t pixfmt);
+void ipuv3_fb_shutdown(void);
+
+#endif
diff --git a/qemu/roms/u-boot/include/jffs2/compr_rubin.h b/qemu/roms/u-boot/include/jffs2/compr_rubin.h
new file mode 100644
index 000000000..f26f476da
--- /dev/null
+++ b/qemu/roms/u-boot/include/jffs2/compr_rubin.h
@@ -0,0 +1,11 @@
+/* Rubin encoder/decoder header       */
+/* work started at   : aug   3, 1994  */
+/* last modification : aug  15, 1994  */
+/* $Id: compr_rubin.h,v 1.1 2002/01/16 23:34:32 nyet Exp $ */
+
+#define RUBIN_REG_SIZE   16
+#define UPPER_BIT_RUBIN    (((long) 1)<<(RUBIN_REG_SIZE-1))
+#define LOWER_BITS_RUBIN   ((((long) 1)<<(RUBIN_REG_SIZE-1))-1)
+
+void dynrubin_decompress(unsigned char *data_in, unsigned char *cpage_out,
+		   unsigned long sourcelen, unsigned long dstlen);
diff --git a/qemu/roms/u-boot/include/jffs2/jffs2.h b/qemu/roms/u-boot/include/jffs2/jffs2.h
new file mode 100644
index 000000000..651f94cf3
--- /dev/null
+++ b/qemu/roms/u-boot/include/jffs2/jffs2.h
@@ -0,0 +1,234 @@
+/*
+ * JFFS2 -- Journalling Flash File System, Version 2.
+ *
+ * Copyright (C) 2001 Red Hat, Inc.
+ *
+ * Created by David Woodhouse <dwmw2@cambridge.redhat.com>
+ *
+ * The original JFFS, from which the design for JFFS2 was derived,
+ * was designed and implemented by Axis Communications AB.
+ *
+ * The contents of this file are subject to the Red Hat eCos Public
+ * License Version 1.1 (the "Licence"); you may not use this file
+ * except in compliance with the Licence.  You may obtain a copy of
+ * the Licence at http://www.redhat.com/
+ *
+ * Software distributed under the Licence is distributed on an "AS IS"
+ * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.
+ * See the Licence for the specific language governing rights and
+ * limitations under the Licence.
+ *
+ * The Original Code is JFFS2 - Journalling Flash File System, version 2
+ *
+ * Alternatively, the contents of this file may be used under the
+ * terms of the GNU General Public License version 2 (the "GPL"), in
+ * which case the provisions of the GPL are applicable instead of the
+ * above.  If you wish to allow the use of your version of this file
+ * only under the terms of the GPL and not to allow others to use your
+ * version of this file under the RHEPL, indicate your decision by
+ * deleting the provisions above and replace them with the notice and
+ * other provisions required by the GPL.  If you do not delete the
+ * provisions above, a recipient may use your version of this file
+ * under either the RHEPL or the GPL.
+ *
+ * $Id: jffs2.h,v 1.2 2002/01/17 00:53:20 nyet Exp $
+ *
+ */
+
+#ifndef __LINUX_JFFS2_H__
+#define __LINUX_JFFS2_H__
+
+#include <asm/types.h>
+#include <jffs2/load_kernel.h>
+
+#define JFFS2_SUPER_MAGIC 0x72b6
+
+/* Values we may expect to find in the 'magic' field */
+#define JFFS2_OLD_MAGIC_BITMASK 0x1984
+#define JFFS2_MAGIC_BITMASK 0x1985
+#define KSAMTIB_CIGAM_2SFFJ 0x5981 /* For detecting wrong-endian fs */
+#define JFFS2_EMPTY_BITMASK 0xffff
+#define JFFS2_DIRTY_BITMASK 0x0000
+
+/* Summary node MAGIC marker */
+#define JFFS2_SUM_MAGIC	0x02851885
+
+/* We only allow a single char for length, and 0xFF is empty flash so
+   we don't want it confused with a real length. Hence max 254.
+*/
+#define JFFS2_MAX_NAME_LEN 254
+
+/* How small can we sensibly write nodes? */
+#define JFFS2_MIN_DATA_LEN 128
+
+#define JFFS2_COMPR_NONE	0x00
+#define JFFS2_COMPR_ZERO	0x01
+#define JFFS2_COMPR_RTIME	0x02
+#define JFFS2_COMPR_RUBINMIPS	0x03
+#define JFFS2_COMPR_COPY	0x04
+#define JFFS2_COMPR_DYNRUBIN	0x05
+#define JFFS2_COMPR_ZLIB	0x06
+#if defined(CONFIG_JFFS2_LZO)
+#define JFFS2_COMPR_LZO		0x07
+#define JFFS2_NUM_COMPR		8
+#else
+#define JFFS2_NUM_COMPR		7
+#endif
+
+/* Compatibility flags. */
+#define JFFS2_COMPAT_MASK 0xc000      /* What do to if an unknown nodetype is found */
+#define JFFS2_NODE_ACCURATE 0x2000
+/* INCOMPAT: Fail to mount the filesystem */
+#define JFFS2_FEATURE_INCOMPAT 0xc000
+/* ROCOMPAT: Mount read-only */
+#define JFFS2_FEATURE_ROCOMPAT 0x8000
+/* RWCOMPAT_COPY: Mount read/write, and copy the node when it's GC'd */
+#define JFFS2_FEATURE_RWCOMPAT_COPY 0x4000
+/* RWCOMPAT_DELETE: Mount read/write, and delete the node when it's GC'd */
+#define JFFS2_FEATURE_RWCOMPAT_DELETE 0x0000
+
+#define JFFS2_NODETYPE_DIRENT (JFFS2_FEATURE_INCOMPAT | JFFS2_NODE_ACCURATE | 1)
+#define JFFS2_NODETYPE_INODE (JFFS2_FEATURE_INCOMPAT | JFFS2_NODE_ACCURATE | 2)
+#define JFFS2_NODETYPE_CLEANMARKER (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 3)
+#define JFFS2_NODETYPE_PADDING (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 4)
+#define JFFS2_NODETYPE_SUMMARY (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 6)
+
+/* Maybe later... */
+/*#define JFFS2_NODETYPE_CHECKPOINT (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 3) */
+/*#define JFFS2_NODETYPE_OPTIONS (JFFS2_FEATURE_RWCOMPAT_COPY | JFFS2_NODE_ACCURATE | 4) */
+
+/* Same as the non_ECC versions, but with extra space for real
+ * ECC instead of just the checksum. For use on NAND flash
+ */
+/*#define JFFS2_NODETYPE_DIRENT_ECC (JFFS2_FEATURE_INCOMPAT | JFFS2_NODE_ACCURATE | 5) */
+/*#define JFFS2_NODETYPE_INODE_ECC (JFFS2_FEATURE_INCOMPAT | JFFS2_NODE_ACCURATE | 6) */
+
+#define JFFS2_INO_FLAG_PREREAD	  1	/* Do read_inode() for this one at
+					   mount time, don't wait for it to
+					   happen later */
+#define JFFS2_INO_FLAG_USERCOMPR  2	/* User has requested a specific
+					   compression type */
+
+
+struct jffs2_unknown_node
+{
+	/* All start like this */
+	__u16 magic;
+	__u16 nodetype;
+	__u32 totlen; /* So we can skip over nodes we don't grok */
+	__u32 hdr_crc;
+} __attribute__((packed));
+
+struct jffs2_raw_dirent
+{
+	__u16 magic;
+	__u16 nodetype;	/* == JFFS_NODETYPE_DIRENT */
+	__u32 totlen;
+	__u32 hdr_crc;
+	__u32 pino;
+	__u32 version;
+	__u32 ino; /* == zero for unlink */
+	__u32 mctime;
+	__u8 nsize;
+	__u8 type;
+	__u8 unused[2];
+	__u32 node_crc;
+	__u32 name_crc;
+	__u8 name[0];
+} __attribute__((packed));
+
+/* The JFFS2 raw inode structure: Used for storage on physical media.  */
+/* The uid, gid, atime, mtime and ctime members could be longer, but
+   are left like this for space efficiency. If and when people decide
+   they really need them extended, it's simple enough to add support for
+   a new type of raw node.
+*/
+struct jffs2_raw_inode
+{
+	__u16 magic;      /* A constant magic number.  */
+	__u16 nodetype;   /* == JFFS_NODETYPE_INODE */
+	__u32 totlen;     /* Total length of this node (inc data, etc.) */
+	__u32 hdr_crc;
+	__u32 ino;        /* Inode number.  */
+	__u32 version;    /* Version number.  */
+	__u32 mode;       /* The file's type or mode.  */
+	__u16 uid;        /* The file's owner.  */
+	__u16 gid;        /* The file's group.  */
+	__u32 isize;      /* Total resultant size of this inode (used for truncations)  */
+	__u32 atime;      /* Last access time.  */
+	__u32 mtime;      /* Last modification time.  */
+	__u32 ctime;      /* Change time.  */
+	__u32 offset;     /* Where to begin to write.  */
+	__u32 csize;      /* (Compressed) data size */
+	__u32 dsize;	  /* Size of the node's data. (after decompression) */
+	__u8 compr;       /* Compression algorithm used */
+	__u8 usercompr;	  /* Compression algorithm requested by the user */
+	__u16 flags;	  /* See JFFS2_INO_FLAG_* */
+	__u32 data_crc;   /* CRC for the (compressed) data.  */
+	__u32 node_crc;   /* CRC for the raw inode (excluding data)  */
+/*	__u8 data[dsize]; */
+} __attribute__((packed));
+
+struct jffs2_raw_summary
+{
+	__u16 magic;
+	__u16 nodetype; 	/* = JFFS2_NODETYPE_SUMMARY */
+	__u32 totlen;
+	__u32 hdr_crc;
+	__u32 sum_num;	/* number of sum entries*/
+	__u32 cln_mkr;	/* clean marker size, 0 = no cleanmarker */
+	__u32 padded;	/* sum of the size of padding nodes */
+	__u32 sum_crc;	/* summary information crc */
+	__u32 node_crc; 	/* node crc */
+	__u32 sum[0]; 	/* inode summary info */
+};
+
+union jffs2_node_union {
+	struct jffs2_raw_inode i;
+	struct jffs2_raw_dirent d;
+	struct jffs2_raw_summary s;
+	struct jffs2_unknown_node u;
+} __attribute__((packed));
+
+enum
+  {
+    DT_UNKNOWN = 0,
+# define DT_UNKNOWN     DT_UNKNOWN
+    DT_FIFO = 1,
+# define DT_FIFO        DT_FIFO
+    DT_CHR = 2,
+# define DT_CHR         DT_CHR
+    DT_DIR = 4,
+# define DT_DIR         DT_DIR
+    DT_BLK = 6,
+# define DT_BLK         DT_BLK
+    DT_REG = 8,
+# define DT_REG         DT_REG
+    DT_LNK = 10,
+# define DT_LNK         DT_LNK
+    DT_SOCK = 12,
+# define DT_SOCK        DT_SOCK
+    DT_WHT = 14
+# define DT_WHT         DT_WHT
+  };
+
+
+u32 jffs2_1pass_ls(struct part_info *part,const char *fname);
+u32 jffs2_1pass_load(char *dest, struct part_info *part,const char *fname);
+u32 jffs2_1pass_info(struct part_info *part);
+
+void rtime_decompress(unsigned char *data_in, unsigned char *cpage_out,
+		u32 srclen, u32 destlen);
+void rubin_do_decompress(unsigned char *bits, unsigned char *in,
+		unsigned char *page_out, __u32 destlen);
+void dynrubin_decompress(unsigned char *data_in, unsigned char *cpage_out,
+		unsigned long sourcelen, unsigned long dstlen);
+long zlib_decompress(unsigned char *data_in, unsigned char *cpage_out,
+		__u32 srclen, __u32 destlen);
+#if defined(CONFIG_JFFS2_LZO)
+int lzo_decompress(unsigned char *data_in, unsigned char *cpage_out,
+		u32 srclen, u32 destlen);
+#endif
+
+char *mkmodestr(unsigned long mode, char *str);
+#endif /* __LINUX_JFFS2_H__ */
diff --git a/qemu/roms/u-boot/include/jffs2/jffs2_1pass.h b/qemu/roms/u-boot/include/jffs2/jffs2_1pass.h
new file mode 100644
index 000000000..5bc3e66cd
--- /dev/null
+++ b/qemu/roms/u-boot/include/jffs2/jffs2_1pass.h
@@ -0,0 +1,3 @@
+u32 jffs2_1pass_ls(struct part_info *part,const char *fname);
+u32 jffs2_1pass_load(char *dest, struct part_info *part,const char *fname);
+u32 jffs2_1pass_info(struct part_info *part);
diff --git a/qemu/roms/u-boot/include/jffs2/load_kernel.h b/qemu/roms/u-boot/include/jffs2/load_kernel.h
new file mode 100644
index 000000000..dd0d23fa5
--- /dev/null
+++ b/qemu/roms/u-boot/include/jffs2/load_kernel.h
@@ -0,0 +1,69 @@
+#ifndef load_kernel_h
+#define load_kernel_h
+/*-------------------------------------------------------------------------
+ * Filename:      load_kernel.h
+ * Version:       $Id: load_kernel.h,v 1.3 2002/01/25 01:34:11 nyet Exp $
+ * Copyright:     Copyright (C) 2001, Russ Dill
+ * Author:        Russ Dill <Russ.Dill@asu.edu>
+ * Description:   header for load kernel modules
+ *-----------------------------------------------------------------------*/
+/*
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/list.h>
+
+/* mtd device types */
+#define MTD_DEV_TYPE_NOR	0x0001
+#define MTD_DEV_TYPE_NAND	0x0002
+#define MTD_DEV_TYPE_ONENAND	0x0004
+
+#define MTD_DEV_TYPE(type) ((type == MTD_DEV_TYPE_NAND) ? "nand" :	\
+			(type == MTD_DEV_TYPE_ONENAND) ? "onenand" : "nor")
+
+struct mtd_device {
+	struct list_head link;
+	struct mtdids *id;		/* parent mtd id entry */
+	u16 num_parts;			/* number of partitions on this device */
+	struct list_head parts;		/* partitions */
+};
+
+struct part_info {
+	struct list_head link;
+	char *name;			/* partition name */
+	u8 auto_name;			/* set to 1 for generated name */
+	u64 size;			/* total size of the partition */
+	u64 offset;			/* offset within device */
+	void *jffs2_priv;		/* used internaly by jffs2 */
+	u32 mask_flags;			/* kernel MTD mask flags */
+	u32 sector_size;		/* size of sector */
+	struct mtd_device *dev;		/* parent device */
+};
+
+struct mtdids {
+	struct list_head link;
+	u8 type;			/* device type */
+	u8 num;				/* device number */
+	u64 size;			/* device size */
+	char *mtd_id;			/* linux kernel device id */
+};
+
+#define ldr_strlen	strlen
+#define ldr_strncmp	strncmp
+#define ldr_memcpy	memcpy
+#define putstr(x)	printf("%s", x)
+#define mmalloc		malloc
+#define UDEBUG		printf
+
+#define putnstr(str, size)	printf("%*.*s", size, size, str)
+#define ldr_output_string(x)	puts(x)
+#define putLabeledWord(x, y)	printf("%s %08x\n", x, (unsigned int)y)
+#define led_blink(x, y, z, a)
+
+/* common/cmd_jffs2.c */
+extern int mtdparts_init(void);
+extern int find_dev_and_part(const char *id, struct mtd_device **dev,
+				u8 *part_num, struct part_info **part);
+extern struct mtd_device *device_find(u8 type, u8 num);
+
+#endif /* load_kernel_h */
diff --git a/qemu/roms/u-boot/include/jffs2/mini_inflate.h b/qemu/roms/u-boot/include/jffs2/mini_inflate.h
new file mode 100644
index 000000000..1cf129167
--- /dev/null
+++ b/qemu/roms/u-boot/include/jffs2/mini_inflate.h
@@ -0,0 +1,68 @@
+/*-------------------------------------------------------------------------
+ * Filename:      mini_inflate.h
+ * Version:       $Id: mini_inflate.h,v 1.2 2002/01/17 00:53:20 nyet Exp $
+ * Copyright:     Copyright (C) 2001, Russ Dill
+ * Author:        Russ Dill <Russ.Dill@asu.edu>
+ * Description:   Mini deflate implementation
+ *-----------------------------------------------------------------------*/
+/*
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+typedef __SIZE_TYPE__ size;
+
+#define NO_ERROR 0
+#define COMP_UNKNOWN 1	 /* The specififed bytype is invalid */
+#define CODE_NOT_FOUND 2 /* a huffman code in the stream could not be decoded */
+#define TOO_MANY_BITS 3	 /* pull_bits was passed an argument that is too
+			  * large */
+
+/* This struct represents an entire huffman code set. It has various lookup
+ * tables to speed decoding */
+struct huffman_set {
+	int bits;	 /* maximum bit length */
+	int num_symbols; /* Number of symbols this code can represent */
+	int *lengths;	 /* The bit length of symbols */
+	int *symbols;	 /* All of the symbols, sorted by the huffman code */
+	int *count;	 /* the number of codes of this bit length */
+	int *first;	 /* the first code of this bit length */
+	int *pos;	 /* the symbol that first represents (in the symbols
+			  * array) */
+};
+
+struct bitstream {
+	unsigned char *data; /* increments as we move from byte to byte */
+	unsigned char bit;   /* 0 to 7 */
+	void *(*memcpy)(void *, const void *, size);
+	unsigned long decoded; /* The number of bytes decoded */
+	int error;
+
+	int  distance_count[16];
+	int  distance_first[16];
+	int  distance_pos[16];
+	int  distance_lengths[32];
+	int  distance_symbols[32];
+
+	int  code_count[8];
+	int  code_first[8];
+	int  code_pos[8];
+	int  code_lengths[19];
+	int  code_symbols[19];
+
+	int  length_count[16];
+	int  length_first[16];
+	int  length_pos[16];
+	int  length_lengths[288];
+	int  length_symbols[288];
+
+	struct huffman_set codes;
+	struct huffman_set lengths;
+	struct huffman_set distance;
+};
+
+#define NO_COMP 0
+#define FIXED_COMP 1
+#define DYNAMIC_COMP 2
+
+long decompress_block(unsigned char *dest, unsigned char *source,
+		      void *(*inflate_memcpy)(void *dest, const void *src, size n));
diff --git a/qemu/roms/u-boot/include/key_matrix.h b/qemu/roms/u-boot/include/key_matrix.h
new file mode 100644
index 000000000..8db686040
--- /dev/null
+++ b/qemu/roms/u-boot/include/key_matrix.h
@@ -0,0 +1,87 @@
+/*
+ * Keyboard matrix helper functions
+ *
+ * Copyright (c) 2012 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _KEY_MATRIX_H
+#define _KEY_MATRIX_H
+
+#include <common.h>
+
+/* Information about a matrix keyboard */
+struct key_matrix {
+	/* Dimensions of the keyboard matrix, in rows and columns */
+	int num_rows;
+	int num_cols;
+	int key_count;	/* number of keys in the matrix (= rows * cols) */
+
+	/*
+	 * Information about keycode mappings. The plain_keycode array must
+	 * exist but fn may be NULL in which case it is not decoded.
+	 */
+	const u8 *plain_keycode;        /* key code for each row / column */
+	const u8 *fn_keycode;           /* ...when Fn held down */
+	int fn_pos;                     /* position of Fn key in key (or -1) */
+	int ghost_filter;		/* non-zero to enable ghost filter */
+};
+
+/* Information about a particular key (row, column pair) in the matrix */
+struct key_matrix_key {
+	uint8_t row;	/* row number (0 = first) */
+	uint8_t col;	/* column number (0 = first) */
+	uint8_t valid;	/* 1 if valid, 0 to ignore this */
+};
+
+/**
+ * Decode a set of pressed keys into key codes
+ *
+ * Given a list of keys that are pressed, this converts this list into
+ * a list of key codes. Each of the keys has a valid flag, which can be
+ * used to mark a particular key as invalid (so that it is ignored).
+ *
+ * The plain keymap is used, unless the Fn key is detected along the way,
+ * at which point we switch to the Fn key map.
+ *
+ * If key ghosting is detected, we simply ignore the keys and return 0.
+ *
+ * @param config        Keyboard matrix config
+ * @param keys		List of keys to process (each is row, col)
+ * @param num_keys	Number of keys to process
+ * @param keycode	Returns a list of key codes, decoded from input
+ * @param max_keycodes	Size of key codes array (suggest 8)
+ *
+ */
+int key_matrix_decode(struct key_matrix *config, struct key_matrix_key *keys,
+		      int num_keys, int keycode[], int max_keycodes);
+
+/**
+ * Read the keyboard configuration out of the fdt.
+ *
+ * Decode properties of named "linux,<type>keymap" where <type> is either
+ * empty, or "fn-". Then set up the plain key map (and the FN keymap if
+ * present).
+ *
+ * @param config        Keyboard matrix config
+ * @param blob          FDT blob
+ * @param node          Node containing compatible data
+ * @return 0 if ok, -1 on error
+ */
+int key_matrix_decode_fdt(struct key_matrix *config, const void *blob,
+			  int node);
+
+/**
+ * Set up a new key matrix.
+ *
+ * @param config	Keyboard matrix config
+ * @param rows		Number of rows in key matrix
+ * @param cols		Number of columns in key matrix
+ * @param ghost_filter	Non-zero to enable ghost filtering
+ * @return 0 if ok, -1 on error
+ */
+int key_matrix_init(struct key_matrix *config, int rows, int cols,
+		    int ghost_filter);
+
+#endif
diff --git a/qemu/roms/u-boot/include/keyboard.h b/qemu/roms/u-boot/include/keyboard.h
new file mode 100644
index 000000000..88ae12bc0
--- /dev/null
+++ b/qemu/roms/u-boot/include/keyboard.h
@@ -0,0 +1,22 @@
+#ifndef __KEYBOARD_H
+#define __KEYBOARD_H
+
+#ifdef CONFIG_PS2MULT
+#include <ps2mult.h>
+#endif
+
+#if !defined(kbd_request_region) || \
+    !defined(kbd_request_irq) || \
+    !defined(kbd_read_input) || \
+    !defined(kbd_read_status) || \
+    !defined(kbd_write_output) || \
+    !defined(kbd_write_command)
+#error PS/2 low level routines not defined
+#endif
+
+extern int kbd_init (void);
+extern void handle_scancode(unsigned char scancode);
+extern int kbd_init_hw(void);
+extern void pckbd_leds(unsigned char leds);
+
+#endif /* __KEYBOARD_H */
diff --git a/qemu/roms/u-boot/include/kgdb.h b/qemu/roms/u-boot/include/kgdb.h
new file mode 100644
index 000000000..b6ba742ad
--- /dev/null
+++ b/qemu/roms/u-boot/include/kgdb.h
@@ -0,0 +1,70 @@
+#ifndef __KGDB_H__
+#define __KGDB_H__
+
+#include <asm/ptrace.h>
+
+#define KGDBERR_BADPARAMS	1
+#define KGDBERR_NOTHEXDIG	2
+#define KGDBERR_MEMFAULT	3
+#define KGDBERR_NOSPACE		4
+#define KGDBERR_ALIGNFAULT	5
+
+#define KGDBDATA_MAXREGS	8
+#define KGDBDATA_MAXPRIV	8
+
+#define KGDBEXIT_TYPEMASK	0xff
+
+#define KGDBEXIT_KILL		0
+#define KGDBEXIT_CONTINUE	1
+#define KGDBEXIT_SINGLE		2
+
+#define KGDBEXIT_WITHADDR	0x100
+
+typedef
+	struct {
+		int num;
+		unsigned long val;
+	}
+kgdb_reg;
+
+typedef
+	struct {
+		int sigval;
+		int extype;
+		unsigned long exaddr;
+		int nregs;
+		kgdb_reg regs[KGDBDATA_MAXREGS];
+		unsigned long private[KGDBDATA_MAXPRIV];
+	}
+kgdb_data;
+
+/* these functions are provided by the generic kgdb support */
+extern void kgdb_init(void);
+extern void kgdb_error(int);
+extern int kgdb_output_string(const char *, unsigned int);
+extern void breakpoint(void);
+
+/* these functions are provided by the platform specific kgdb support */
+extern void kgdb_flush_cache_range(void *, void *);
+extern void kgdb_flush_cache_all(void);
+extern int kgdb_setjmp(long *);
+extern void kgdb_longjmp(long *, int);
+extern void kgdb_enter(struct pt_regs *, kgdb_data *);
+extern void kgdb_exit(struct pt_regs *, kgdb_data *);
+extern int kgdb_getregs(struct pt_regs *, char *, int);
+extern void kgdb_putreg(struct pt_regs *, int, char *, int);
+extern void kgdb_putregs(struct pt_regs *, char *, int);
+extern int kgdb_trap(struct pt_regs *);
+extern void kgdb_breakpoint(int argc, char * const argv[]);
+
+/* these functions are provided by the platform serial driver */
+extern void kgdb_serial_init(void);
+extern int getDebugChar(void);
+extern void putDebugChar(int);
+extern void putDebugStr(const char *);
+extern void kgdb_interruptible(int);
+
+/* this is referenced in the trap handler for the platform */
+extern int (*debugger_exception_handler)(struct pt_regs *);
+
+#endif /* __KGDB_H__ */
diff --git a/qemu/roms/u-boot/include/lattice.h b/qemu/roms/u-boot/include/lattice.h
new file mode 100644
index 000000000..ea4b5303a
--- /dev/null
+++ b/qemu/roms/u-boot/include/lattice.h
@@ -0,0 +1,299 @@
+/*
+ * Porting to U-Boot:
+ *
+ * (C) Copyright 2010
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * Lattice's ispVME Embedded Tool to load Lattice's FPGA:
+ *
+ * Lattice Semiconductor Corp. Copyright 2009
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _VME_OPCODE_H
+#define _VME_OPCODE_H
+
+#define VME_VERSION_NUMBER "12.1"
+
+/* Maximum declarations. */
+
+#define VMEHEXMAX	60000L	/* The hex file is split 60K per file. */
+#define SCANMAX		64000L	/* The maximum SDR/SIR burst. */
+
+/*
+ *
+ * Supported JTAG state transitions.
+ *
+ */
+
+#define RESET		0x00
+#define IDLE		0x01
+#define IRPAUSE		0x02
+#define DRPAUSE		0x03
+#define SHIFTIR		0x04
+#define SHIFTDR		0x05
+/* 11/15/05 Nguyen changed to support DRCAPTURE*/
+#define DRCAPTURE	0x06
+
+/*
+ * Flow control register bit definitions.  A set bit indicates
+ * that the register currently exhibits the corresponding mode.
+ */
+
+#define INTEL_PRGM	0x0001	/* Intelligent programming is in effect. */
+#define CASCADE		0x0002	/* Currently splitting large SDR. */
+#define REPEATLOOP	0x0008	/* Currently executing a repeat loop. */
+#define SHIFTRIGHT	0x0080	/* The next data stream needs a right shift. */
+#define SHIFTLEFT	0x0100	/* The next data stream needs a left shift. */
+#define VERIFYUES	0x0200	/* Continue if fail is in effect. */
+
+/*
+ * DataType register bit definitions.  A set bit indicates
+ * that the register currently holds the corresponding type of data.
+ */
+
+#define EXPRESS		0x0001    /* Simultaneous program and verify. */
+#define SIR_DATA	0x0002    /* SIR is the active SVF command. */
+#define SDR_DATA	0x0004    /* SDR is the active SVF command. */
+#define COMPRESS	0x0008    /* Data is compressed. */
+#define TDI_DATA	0x0010    /* TDI data is present. */
+#define TDO_DATA	0x0020    /* TDO data is present. */
+#define MASK_DATA	0x0040    /* MASK data is present. */
+#define HEAP_IN		0x0080    /* Data is from the heap. */
+#define LHEAP_IN	0x0200    /* Data is from intel data buffer. */
+#define VARIABLE	0x0400    /* Data is from a declared variable. */
+#define CRC_DATA	0x0800	 /* CRC data is pressent. */
+#define CMASK_DATA	0x1000    /* CMASK data is pressent. */
+#define RMASK_DATA	0x2000	 /* RMASK data is pressent. */
+#define READ_DATA	0x4000    /* READ data is pressent. */
+#define DMASK_DATA	0x8000	 /* DMASK data is pressent. */
+
+/*
+ *
+ * Pin opcodes.
+ *
+ */
+
+#define signalENABLE	0x1C    /* ispENABLE pin. */
+#define signalTMS	0x1D    /* TMS pin. */
+#define signalTCK	0x1E    /* TCK pin. */
+#define signalTDI	0x1F    /* TDI pin. */
+#define signalTRST	0x20    /* TRST pin. */
+
+/*
+ *
+ * Supported vendors.
+ *
+ */
+
+#define VENDOR		0x56
+#define LATTICE		0x01
+#define ALTERA		0x02
+#define XILINX		0x03
+
+/*
+ * Opcode definitions.
+ *
+ * Note: opcodes must be unique.
+ */
+
+#define ENDDATA		0x00	/* The end of the current SDR data stream. */
+#define RUNTEST		0x01	/* The duration to stay at the stable state. */
+#define ENDDR		0x02	/* The stable state after SDR. */
+#define ENDIR		0x03	/* The stable state after SIR. */
+#define ENDSTATE	0x04	/* The stable state after RUNTEST. */
+#define TRST		0x05	/* Assert the TRST pin. */
+#define HIR		0x06	/*
+				 * The sum of the IR bits of the
+				 * leading devices.
+				 */
+#define TIR		0x07	/*
+				 * The sum of the IR bits of the trailing
+				 * devices.
+				 */
+#define HDR		0x08	/* The number of leading devices. */
+#define TDR		0x09	/* The number of trailing devices. */
+#define ispEN		0x0A	/* Assert the ispEN pin. */
+#define FREQUENCY	0x0B	/*
+				 * The maximum clock rate to run the JTAG state
+				 * machine.
+				 */
+#define STATE		0x10	/* Move to the next stable state. */
+#define SIR		0x11	/* The instruction stream follows. */
+#define SDR		0x12	/* The data stream follows. */
+#define TDI		0x13	/* The following data stream feeds into
+					the device. */
+#define TDO		0x14	/*
+				 * The following data stream is compared against
+				 * the device.
+				 */
+#define MASK		0x15	/* The following data stream is used as mask. */
+#define XSDR		0x16	/*
+				 * The following data stream is for simultaneous
+				 * program and verify.
+				 */
+#define XTDI		0x17	/* The following data stream is for shift in
+				 * only. It must be stored for the next
+				 * XSDR.
+				 */
+#define XTDO		0x18	/*
+				 * There is not data stream.  The data stream
+				 * was stored from the previous XTDI.
+				 */
+#define MEM		0x19	/*
+				 * The maximum memory needed to allocate in
+				 * order hold one row of data.
+				 */
+#define WAIT		0x1A	/* The duration of delay to observe. */
+#define TCK		0x1B	/* The number of TCK pulses. */
+#define SHR		0x23	/*
+				 * Set the flow control register for
+				 * right shift
+				 */
+#define SHL		0x24	/*
+				 * Set the flow control register for left shift.
+				 */
+#define HEAP		0x32	/* The memory size needed to hold one loop. */
+#define REPEAT		0x33	/* The beginning of the loop. */
+#define LEFTPAREN	0x35	/* The beginning of data following the loop. */
+#define VAR		0x55	/* Plac holder for loop data. */
+#define SEC		0x1C	/*
+				 * The delay time in seconds that must be
+				 * observed.
+				 */
+#define SMASK		0x1D	/* The mask for TDI data. */
+#define MAX_WAIT	0x1E	/* The absolute maximum wait time. */
+#define ON		0x1F	/* Assert the targeted pin. */
+#define OFF		0x20	/* Dis-assert the targeted pin. */
+#define SETFLOW		0x30	/* Change the flow control register. */
+#define RESETFLOW	0x31	/* Clear the flow control register. */
+
+#define CRC		0x47	/*
+				 * The following data stream is used for CRC
+				 * calculation.
+				 */
+#define CMASK		0x48	/*
+				 * The following data stream is used as mask
+				 * for CRC calculation.
+				 */
+#define RMASK		0x49	/*
+				 * The following data stream is used as mask
+				 * for read and save.
+				 */
+#define READ		0x50	/*
+				 * The following data stream is used for read
+				 * and save.
+				 */
+#define ENDLOOP		0x59	/* The end of the repeat loop. */
+#define SECUREHEAP	0x60	/* Used to secure the HEAP opcode. */
+#define VUES		0x61	/* Support continue if fail. */
+#define DMASK		0x62	/*
+				 * The following data stream is used for dynamic
+				 * I/O.
+				 */
+#define COMMENT		0x63	/* Support SVF comments in the VME file. */
+#define HEADER		0x64	/* Support header in VME file. */
+#define FILE_CRC	0x65	/* Support crc-protected VME file. */
+#define LCOUNT		0x66	/* Support intelligent programming. */
+#define LDELAY		0x67	/* Support intelligent programming. */
+#define LSDR		0x68	/* Support intelligent programming. */
+#define LHEAP		0x69	/*
+				 * Memory needed to hold intelligent data
+				 * buffer
+				 */
+#define CONTINUE	0x70	/* Allow continuation. */
+#define LVDS		0x71	/* Support LVDS. */
+#define ENDVME		0x7F	/* End of the VME file. */
+#define ENDFILE		0xFF	/* End of file. */
+
+/*
+ *
+ * ispVM Embedded Return Codes.
+ *
+ */
+
+#define VME_VERIFICATION_FAILURE	-1
+#define VME_FILE_READ_FAILURE		-2
+#define VME_VERSION_FAILURE		-3
+#define VME_INVALID_FILE		-4
+#define VME_ARGUMENT_FAILURE		-5
+#define VME_CRC_FAILURE			-6
+
+#define g_ucPinTDI	0x01
+#define g_ucPinTCK	0x02
+#define g_ucPinTMS	0x04
+#define g_ucPinENABLE	0x08
+#define g_ucPinTRST	0x10
+
+/*
+ *
+ * Type definitions.
+ *
+ */
+
+/* Support LVDS */
+typedef struct {
+	unsigned short usPositiveIndex;
+	unsigned short usNegativeIndex;
+	unsigned char  ucUpdate;
+} LVDSPair;
+
+typedef enum {
+	min_lattice_iface_type,		/* insert all new types after this */
+	lattice_jtag_mode,		/* jtag/tap  */
+	max_lattice_iface_type		/* insert all new types before this */
+} Lattice_iface;
+
+typedef enum {
+	min_lattice_type,
+	Lattice_XP2,			/* Lattice XP2 Family */
+	max_lattice_type		/* insert all new types before this */
+} Lattice_Family;
+
+typedef struct {
+	Lattice_Family	family;	/* part type */
+	Lattice_iface	iface;	/* interface type */
+	size_t		size;	/* bytes of data part can accept */
+	void		*iface_fns; /* interface function table */
+	void		*base;	/* base interface address */
+	int		cookie;	/* implementation specific cookie */
+	char		*desc;	/* description string */
+} Lattice_desc;			/* end, typedef Altera_desc */
+
+/* Board specific implementation specific function types */
+typedef void (*Lattice_jtag_init)(void);
+typedef void (*Lattice_jtag_set_tdi)(int v);
+typedef void (*Lattice_jtag_set_tms)(int v);
+typedef void (*Lattice_jtag_set_tck)(int v);
+typedef int (*Lattice_jtag_get_tdo)(void);
+
+typedef struct {
+	Lattice_jtag_init	jtag_init;
+	Lattice_jtag_set_tdi	jtag_set_tdi;
+	Lattice_jtag_set_tms	jtag_set_tms;
+	Lattice_jtag_set_tck	jtag_set_tck;
+	Lattice_jtag_get_tdo	jtag_get_tdo;
+} lattice_board_specific_func;
+
+void writePort(unsigned char pins, unsigned char value);
+unsigned char readPort(void);
+void sclock(void);
+void ispVMDelay(unsigned short int a_usMicroSecondDelay);
+void calibration(void);
+
+int lattice_load(Lattice_desc *desc, const void *buf, size_t bsize);
+int lattice_dump(Lattice_desc *desc, const void *buf, size_t bsize);
+int lattice_info(Lattice_desc *desc);
+
+void ispVMStart(void);
+void ispVMEnd(void);
+extern void ispVMFreeMem(void);
+signed char ispVMCode(void);
+void ispVMDelay(unsigned short int a_usMicroSecondDelay);
+void ispVMCalculateCRC32(unsigned char a_ucData);
+unsigned char GetByte(void);
+void writePort(unsigned char pins, unsigned char value);
+unsigned char readPort(void);
+void sclock(void);
+#endif
diff --git a/qemu/roms/u-boot/include/lcd.h b/qemu/roms/u-boot/include/lcd.h
new file mode 100644
index 000000000..5f84cd3c5
--- /dev/null
+++ b/qemu/roms/u-boot/include/lcd.h
@@ -0,0 +1,408 @@
+/*
+ * MPC823 and PXA LCD Controller
+ *
+ * Modeled after video interface by Paolo Scaffardi
+ *
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _LCD_H_
+#define _LCD_H_
+
+extern char lcd_is_enabled;
+
+extern int lcd_line_length;
+
+extern struct vidinfo panel_info;
+
+void lcd_ctrl_init(void *lcdbase);
+void lcd_enable(void);
+
+/* setcolreg used in 8bpp/16bpp; initcolregs used in monochrome */
+void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue);
+void lcd_initcolregs(void);
+
+int lcd_getfgcolor(void);
+
+/* gunzip_bmp used if CONFIG_VIDEO_BMP_GZIP */
+struct bmp_image *gunzip_bmp(unsigned long addr, unsigned long *lenp,
+			     void **alloc_addr);
+int bmp_display(ulong addr, int x, int y);
+
+/**
+ * Set whether we need to flush the dcache when changing the LCD image. This
+ * defaults to off.
+ *
+ * @param flush		non-zero to flush cache after update, 0 to skip
+ */
+void lcd_set_flush_dcache(int flush);
+
+#if defined CONFIG_MPC823
+/*
+ * LCD controller stucture for MPC823 CPU
+ */
+typedef struct vidinfo {
+	ushort	vl_col;		/* Number of columns (i.e. 640) */
+	ushort	vl_row;		/* Number of rows (i.e. 480) */
+	ushort	vl_width;	/* Width of display area in millimeters */
+	ushort	vl_height;	/* Height of display area in millimeters */
+
+	/* LCD configuration register */
+	u_char	vl_clkp;	/* Clock polarity */
+	u_char	vl_oep;		/* Output Enable polarity */
+	u_char	vl_hsp;		/* Horizontal Sync polarity */
+	u_char	vl_vsp;		/* Vertical Sync polarity */
+	u_char	vl_dp;		/* Data polarity */
+	u_char	vl_bpix;	/* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8 */
+	u_char	vl_lbw;		/* LCD Bus width, 0 = 4, 1 = 8 */
+	u_char	vl_splt;	/* Split display, 0 = single-scan, 1 = dual-scan */
+	u_char	vl_clor;	/* Color, 0 = mono, 1 = color */
+	u_char	vl_tft;		/* 0 = passive, 1 = TFT */
+
+	/* Horizontal control register. Timing from data sheet */
+	ushort	vl_wbl;		/* Wait between lines */
+
+	/* Vertical control register */
+	u_char	vl_vpw;		/* Vertical sync pulse width */
+	u_char	vl_lcdac;	/* LCD AC timing */
+	u_char	vl_wbf;		/* Wait between frames */
+} vidinfo_t;
+
+#elif defined(CONFIG_CPU_PXA25X) || defined(CONFIG_CPU_PXA27X) || \
+	defined CONFIG_CPU_MONAHANS
+/*
+ * PXA LCD DMA descriptor
+ */
+struct pxafb_dma_descriptor {
+	u_long	fdadr;		/* Frame descriptor address register */
+	u_long	fsadr;		/* Frame source address register */
+	u_long	fidr;		/* Frame ID register */
+	u_long	ldcmd;		/* Command register */
+};
+
+/*
+ * PXA LCD info
+ */
+struct pxafb_info {
+
+	/* Misc registers */
+	u_long	reg_lccr3;
+	u_long	reg_lccr2;
+	u_long	reg_lccr1;
+	u_long	reg_lccr0;
+	u_long	fdadr0;
+	u_long	fdadr1;
+
+	/* DMA descriptors */
+	struct	pxafb_dma_descriptor *	dmadesc_fblow;
+	struct	pxafb_dma_descriptor *	dmadesc_fbhigh;
+	struct	pxafb_dma_descriptor *	dmadesc_palette;
+
+	u_long	screen;		/* physical address of frame buffer */
+	u_long	palette;	/* physical address of palette memory */
+	u_int	palette_size;
+};
+
+/*
+ * LCD controller stucture for PXA CPU
+ */
+typedef struct vidinfo {
+	ushort	vl_col;		/* Number of columns (i.e. 640) */
+	ushort	vl_row;		/* Number of rows (i.e. 480) */
+	ushort	vl_width;	/* Width of display area in millimeters */
+	ushort	vl_height;	/* Height of display area in millimeters */
+
+	/* LCD configuration register */
+	u_char	vl_clkp;	/* Clock polarity */
+	u_char	vl_oep;		/* Output Enable polarity */
+	u_char	vl_hsp;		/* Horizontal Sync polarity */
+	u_char	vl_vsp;		/* Vertical Sync polarity */
+	u_char	vl_dp;		/* Data polarity */
+	u_char	vl_bpix;	/* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */
+	u_char	vl_lbw;		/* LCD Bus width, 0 = 4, 1 = 8 */
+	u_char	vl_splt;	/* Split display, 0 = single-scan, 1 = dual-scan */
+	u_char	vl_clor;	/* Color, 0 = mono, 1 = color */
+	u_char	vl_tft;		/* 0 = passive, 1 = TFT */
+
+	/* Horizontal control register. Timing from data sheet */
+	ushort	vl_hpw;		/* Horz sync pulse width */
+	u_char	vl_blw;		/* Wait before of line */
+	u_char	vl_elw;		/* Wait end of line */
+
+	/* Vertical control register. */
+	u_char	vl_vpw;		/* Vertical sync pulse width */
+	u_char	vl_bfw;		/* Wait before of frame */
+	u_char	vl_efw;		/* Wait end of frame */
+
+	/* PXA LCD controller params */
+	struct	pxafb_info pxa;
+} vidinfo_t;
+
+#elif defined(CONFIG_ATMEL_LCD) || defined(CONFIG_ATMEL_HLCD)
+
+typedef struct vidinfo {
+	ushort vl_col;		/* Number of columns (i.e. 640) */
+	ushort vl_row;		/* Number of rows (i.e. 480) */
+	u_long vl_clk;	/* pixel clock in ps    */
+
+	/* LCD configuration register */
+	u_long vl_sync;		/* Horizontal / vertical sync */
+	u_long vl_bpix;		/* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */
+	u_long vl_tft;		/* 0 = passive, 1 = TFT */
+	u_long vl_cont_pol_low;	/* contrast polarity is low */
+	u_long vl_clk_pol;	/* clock polarity */
+
+	/* Horizontal control register. */
+	u_long vl_hsync_len;	/* Length of horizontal sync */
+	u_long vl_left_margin;	/* Time from sync to picture */
+	u_long vl_right_margin;	/* Time from picture to sync */
+
+	/* Vertical control register. */
+	u_long vl_vsync_len;	/* Length of vertical sync */
+	u_long vl_upper_margin;	/* Time from sync to picture */
+	u_long vl_lower_margin;	/* Time from picture to sync */
+
+	u_long	mmio;		/* Memory mapped registers */
+} vidinfo_t;
+
+#elif defined(CONFIG_EXYNOS_FB)
+
+enum {
+	FIMD_RGB_INTERFACE = 1,
+	FIMD_CPU_INTERFACE = 2,
+};
+
+enum exynos_fb_rgb_mode_t {
+	MODE_RGB_P = 0,
+	MODE_BGR_P = 1,
+	MODE_RGB_S = 2,
+	MODE_BGR_S = 3,
+};
+
+typedef struct vidinfo {
+	ushort vl_col;		/* Number of columns (i.e. 640) */
+	ushort vl_row;		/* Number of rows (i.e. 480) */
+	ushort vl_width;	/* Width of display area in millimeters */
+	ushort vl_height;	/* Height of display area in millimeters */
+
+	/* LCD configuration register */
+	u_char vl_freq;		/* Frequency */
+	u_char vl_clkp;		/* Clock polarity */
+	u_char vl_oep;		/* Output Enable polarity */
+	u_char vl_hsp;		/* Horizontal Sync polarity */
+	u_char vl_vsp;		/* Vertical Sync polarity */
+	u_char vl_dp;		/* Data polarity */
+	u_char vl_bpix;		/* Bits per pixel */
+
+	/* Horizontal control register. Timing from data sheet */
+	u_char vl_hspw;		/* Horz sync pulse width */
+	u_char vl_hfpd;		/* Wait before of line */
+	u_char vl_hbpd;		/* Wait end of line */
+
+	/* Vertical control register. */
+	u_char	vl_vspw;	/* Vertical sync pulse width */
+	u_char	vl_vfpd;	/* Wait before of frame */
+	u_char	vl_vbpd;	/* Wait end of frame */
+	u_char  vl_cmd_allow_len; /* Wait end of frame */
+
+	unsigned int win_id;
+	unsigned int init_delay;
+	unsigned int power_on_delay;
+	unsigned int reset_delay;
+	unsigned int interface_mode;
+	unsigned int mipi_enabled;
+	unsigned int dp_enabled;
+	unsigned int cs_setup;
+	unsigned int wr_setup;
+	unsigned int wr_act;
+	unsigned int wr_hold;
+	unsigned int logo_on;
+	unsigned int logo_width;
+	unsigned int logo_height;
+	int logo_x_offset;
+	int logo_y_offset;
+	unsigned long logo_addr;
+	unsigned int rgb_mode;
+	unsigned int resolution;
+
+	/* parent clock name(MPLL, EPLL or VPLL) */
+	unsigned int pclk_name;
+	/* ratio value for source clock from parent clock. */
+	unsigned int sclk_div;
+
+	unsigned int dual_lcd_enabled;
+} vidinfo_t;
+
+void init_panel_info(vidinfo_t *vid);
+
+#else
+
+typedef struct vidinfo {
+	ushort	vl_col;		/* Number of columns (i.e. 160) */
+	ushort	vl_row;		/* Number of rows (i.e. 100) */
+
+	u_char	vl_bpix;	/* Bits per pixel, 0 = 1 */
+
+	ushort	*cmap;		/* Pointer to the colormap */
+
+	void	*priv;		/* Pointer to driver-specific data */
+} vidinfo_t;
+
+#endif /* CONFIG_MPC823, CONFIG_CPU_PXA25X, CONFIG_MCC200, CONFIG_ATMEL_LCD */
+
+extern vidinfo_t panel_info;
+
+/* Video functions */
+
+#if defined(CONFIG_RBC823)
+void	lcd_disable(void);
+#endif
+
+void	lcd_putc(const char c);
+void	lcd_puts(const char *s);
+void	lcd_printf(const char *fmt, ...);
+void	lcd_clear(void);
+int	lcd_display_bitmap(ulong bmp_image, int x, int y);
+
+/**
+ * Get the width of the LCD in pixels
+ *
+ * @return width of LCD in pixels
+ */
+int lcd_get_pixel_width(void);
+
+/**
+ * Get the height of the LCD in pixels
+ *
+ * @return height of LCD in pixels
+ */
+int lcd_get_pixel_height(void);
+
+/**
+ * Get the number of text lines/rows on the LCD
+ *
+ * @return number of rows
+ */
+int lcd_get_screen_rows(void);
+
+/**
+ * Get the number of text columns on the LCD
+ *
+ * @return number of columns
+ */
+int lcd_get_screen_columns(void);
+
+/**
+ * Set the position of the text cursor
+ *
+ * @param col	Column to place cursor (0 = left side)
+ * @param row	Row to place cursor (0 = top line)
+ */
+void lcd_position_cursor(unsigned col, unsigned row);
+
+/* Allow boards to customize the information displayed */
+void lcd_show_board_info(void);
+
+/* Return the size of the LCD frame buffer, and the line length */
+int lcd_get_size(int *line_length);
+
+int lcd_dt_simplefb_add_node(void *blob);
+int lcd_dt_simplefb_enable_existing_node(void *blob);
+
+/* Update the LCD / flush the cache */
+void lcd_sync(void);
+
+/************************************************************************/
+/* ** BITMAP DISPLAY SUPPORT						*/
+/************************************************************************/
+#if defined(CONFIG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN)
+# include <bmp_layout.h>
+# include <asm/byteorder.h>
+#endif
+
+/*
+ *  Information about displays we are using. This is for configuring
+ *  the LCD controller and memory allocation. Someone has to know what
+ *  is connected, as we can't autodetect anything.
+ */
+#define CONFIG_SYS_HIGH	0	/* Pins are active high			*/
+#define CONFIG_SYS_LOW	1	/* Pins are active low			*/
+
+#define LCD_MONOCHROME	0
+#define LCD_COLOR2	1
+#define LCD_COLOR4	2
+#define LCD_COLOR8	3
+#define LCD_COLOR16	4
+
+/*----------------------------------------------------------------------*/
+#if defined(CONFIG_LCD_INFO_BELOW_LOGO)
+# define LCD_INFO_X		0
+# define LCD_INFO_Y		(BMP_LOGO_HEIGHT + VIDEO_FONT_HEIGHT)
+#elif defined(CONFIG_LCD_LOGO)
+# define LCD_INFO_X		(BMP_LOGO_WIDTH + 4 * VIDEO_FONT_WIDTH)
+# define LCD_INFO_Y		VIDEO_FONT_HEIGHT
+#else
+# define LCD_INFO_X		VIDEO_FONT_WIDTH
+# define LCD_INFO_Y		VIDEO_FONT_HEIGHT
+#endif
+
+/* Default to 8bpp if bit depth not specified */
+#ifndef LCD_BPP
+# define LCD_BPP			LCD_COLOR8
+#endif
+#ifndef LCD_DF
+# define LCD_DF			1
+#endif
+
+/* Calculate nr. of bits per pixel  and nr. of colors */
+#define NBITS(bit_code)		(1 << (bit_code))
+#define NCOLORS(bit_code)	(1 << NBITS(bit_code))
+
+/************************************************************************/
+/* ** CONSOLE CONSTANTS							*/
+/************************************************************************/
+#if LCD_BPP == LCD_MONOCHROME
+
+/*
+ * Simple black/white definitions
+ */
+# define CONSOLE_COLOR_BLACK	0
+# define CONSOLE_COLOR_WHITE	1	/* Must remain last / highest	*/
+
+#elif LCD_BPP == LCD_COLOR8
+
+/*
+ * 8bpp color definitions
+ */
+# define CONSOLE_COLOR_BLACK	0
+# define CONSOLE_COLOR_RED	1
+# define CONSOLE_COLOR_GREEN	2
+# define CONSOLE_COLOR_YELLOW	3
+# define CONSOLE_COLOR_BLUE	4
+# define CONSOLE_COLOR_MAGENTA	5
+# define CONSOLE_COLOR_CYAN	6
+# define CONSOLE_COLOR_GREY	14
+# define CONSOLE_COLOR_WHITE	15	/* Must remain last / highest	*/
+
+#else
+
+/*
+ * 16bpp color definitions
+ */
+# define CONSOLE_COLOR_BLACK	0x0000
+# define CONSOLE_COLOR_WHITE	0xffff	/* Must remain last / highest	*/
+
+#endif /* color definitions */
+
+/************************************************************************/
+#ifndef PAGE_SIZE
+# define PAGE_SIZE	4096
+#endif
+
+/************************************************************************/
+
+#endif	/* _LCD_H_ */
diff --git a/qemu/roms/u-boot/include/lcdvideo.h b/qemu/roms/u-boot/include/lcdvideo.h
new file mode 100644
index 000000000..f0640a538
--- /dev/null
+++ b/qemu/roms/u-boot/include/lcdvideo.h
@@ -0,0 +1,69 @@
+/*
+ * MPC823 LCD and Video Controller
+ * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
+ */
+#ifndef __LCDVIDEO_H__
+#define __LCDVIDEO_H__
+
+
+/* LCD Controller Configuration Register.
+*/
+#define LCCR_BNUM	((uint)0xfffe0000)
+#define LCCR_EIEN	((uint)0x00010000)
+#define LCCR_IEN	((uint)0x00008000)
+#define LCCR_IRQL	((uint)0x00007000)
+#define LCCR_CLKP	((uint)0x00000800)
+#define LCCR_OEP	((uint)0x00000400)
+#define LCCR_HSP	((uint)0x00000200)
+#define LCCR_VSP	((uint)0x00000100)
+#define LCCR_DP		((uint)0x00000080)
+#define LCCR_BPIX	((uint)0x00000060)
+#define LCCR_LBW	((uint)0x00000010)
+#define LCCR_SPLT	((uint)0x00000008)
+#define LCCR_CLOR	((uint)0x00000004)
+#define LCCR_TFT	((uint)0x00000002)
+#define LCCR_PON	((uint)0x00000001)
+
+/* Define the bit shifts to load values into the register.
+*/
+#define LCDBIT(BIT, VAL)	((VAL) << (31 - BIT))
+
+#define LCCR_BNUM_BIT	((uint)14)
+#define LCCR_EIEN_BIT	((uint)15)
+#define LCCR_IEN_BIT	((uint)16)
+#define LCCR_IROL_BIT	((uint)19)
+#define LCCR_CLKP_BIT	((uint)20)
+#define LCCR_OEP_BIT	((uint)21)
+#define LCCR_HSP_BIT	((uint)22)
+#define LCCR_VSP_BIT	((uint)23)
+#define LCCR_DP_BIT	((uint)24)
+#define LCCR_BPIX_BIT	((uint)26)
+#define LCCR_LBW_BIT	((uint)27)
+#define LCCR_SPLT_BIT	((uint)28)
+#define LCCR_CLOR_BIT	((uint)29)
+#define LCCR_TFT_BIT	((uint)30)
+#define LCCR_PON_BIT	((uint)31)
+
+/* LCD Horizontal control register.
+*/
+#define LCHCR_BO	((uint)0x01000000)
+#define LCHCR_AT	((uint)0x00e00000)
+#define LCHCR_HPC	((uint)0x001ffc00)
+#define LCHCR_WBL	((uint)0x000003ff)
+
+#define LCHCR_AT_BIT	((uint)10)
+#define LCHCR_HPC_BIT	((uint)21)
+#define LCHCR_WBL_BIT	((uint)31)
+
+/* LCD Vertical control register.
+*/
+#define LCVCR_VPW	((uint)0xf0000000)
+#define LCVCR_LCD_AC	((uint)0x01e00000)
+#define LCVCR_VPC	((uint)0x001ff800)
+#define LCVCR_WBF	((uint)0x000003ff)
+
+#define LCVCR_VPW_BIT	((uint)3)
+#define LCVCR_LCD_AC_BIT ((uint)10)
+#define LCVCR_VPC_BIT	((uint)20)
+
+#endif /* __LCDVIDEO_H__ */
diff --git a/qemu/roms/u-boot/include/ld9040.h b/qemu/roms/u-boot/include/ld9040.h
new file mode 100644
index 000000000..9d527e2de
--- /dev/null
+++ b/qemu/roms/u-boot/include/ld9040.h
@@ -0,0 +1,16 @@
+/*
+ * ld9040 AMOLED LCD panel driver.
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ * Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __LD9040_H_
+#define __LD9040_H_
+
+void ld9040_cfg_ldo(void);
+void ld9040_enable_ldo(unsigned int onoff);
+
+#endif /* __LD9040_H_ */
diff --git a/qemu/roms/u-boot/include/led-display.h b/qemu/roms/u-boot/include/led-display.h
new file mode 100644
index 000000000..ffc262dc9
--- /dev/null
+++ b/qemu/roms/u-boot/include/led-display.h
@@ -0,0 +1,19 @@
+/*
+ * (C) Copyright 2005-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2010
+ * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _led_display_h_
+#define _led_display_h_
+
+/* Display Commands */
+#define DISPLAY_CLEAR	0x1 /* Clear the display */
+#define DISPLAY_HOME	0x2 /* Set cursor at home position */
+
+void display_set(int cmd);
+int display_putc(char c);
+#endif
diff --git a/qemu/roms/u-boot/include/libata.h b/qemu/roms/u-boot/include/libata.h
new file mode 100644
index 000000000..5b7d7b302
--- /dev/null
+++ b/qemu/roms/u-boot/include/libata.h
@@ -0,0 +1,655 @@
+/*
+ * Copyright 2003-2004 Red Hat, Inc.  All rights reserved.
+ * Copyright 2003-2004 Jeff Garzik
+ * Copyright (C) 2008 Freescale Semiconductor, Inc.
+ *		Dave Liu <daveliu@freescale.com>
+ *		port from libata of linux kernel
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __LIBATA_H__
+#define __LIBATA_H__
+
+#include <common.h>
+
+enum {
+	/* various global constants */
+	ATA_MAX_DEVICES		= 2,	/* per bus/port */
+	ATA_MAX_PRD		= 256,	/* we could make these 256/256 */
+	ATA_SECT_SIZE		= 512,
+	ATA_MAX_SECTORS_128	= 128,
+	ATA_MAX_SECTORS		= 256,
+	ATA_MAX_SECTORS_LBA48	= 65535,
+	ATA_MAX_SECTORS_TAPE	= 65535,
+
+	ATA_ID_WORDS		= 256,
+	ATA_ID_SERNO		= 10,
+	ATA_ID_FW_REV		= 23,
+	ATA_ID_PROD		= 27,
+	ATA_ID_OLD_PIO_MODES	= 51,
+	ATA_ID_FIELD_VALID	= 53,
+	ATA_ID_LBA_SECTORS	= 60,
+	ATA_ID_MWDMA_MODES	= 63,
+	ATA_ID_PIO_MODES	= 64,
+	ATA_ID_EIDE_DMA_MIN	= 65,
+	ATA_ID_EIDE_PIO		= 67,
+	ATA_ID_EIDE_PIO_IORDY	= 68,
+	ATA_ID_PIO4		= (1 << 1),
+	ATA_ID_QUEUE_DEPTH	= 75,
+	ATA_ID_SATA_CAP		= 76,
+	ATA_ID_SATA_FEATURES	= 78,
+	ATA_ID_SATA_FEATURES_EN	= 79,
+	ATA_ID_MAJOR_VER	= 80,
+	ATA_ID_MINOR_VER	= 81,
+	ATA_ID_UDMA_MODES	= 88,
+	ATA_ID_LBA48_SECTORS	= 100,
+
+	ATA_ID_SERNO_LEN	= 20,
+	ATA_ID_FW_REV_LEN	= 8,
+	ATA_ID_PROD_LEN		= 40,
+
+	ATA_PCI_CTL_OFS		= 2,
+
+	ATA_PIO0		= (1 << 0),
+	ATA_PIO1		= ATA_PIO0 | (1 << 1),
+	ATA_PIO2		= ATA_PIO1 | (1 << 2),
+	ATA_PIO3		= ATA_PIO2 | (1 << 3),
+	ATA_PIO4		= ATA_PIO3 | (1 << 4),
+	ATA_PIO5		= ATA_PIO4 | (1 << 5),
+	ATA_PIO6		= ATA_PIO5 | (1 << 6),
+
+	ATA_SWDMA0		= (1 << 0),
+	ATA_SWDMA1		= ATA_SWDMA0 | (1 << 1),
+	ATA_SWDMA2		= ATA_SWDMA1 | (1 << 2),
+
+	ATA_SWDMA2_ONLY		= (1 << 2),
+
+	ATA_MWDMA0		= (1 << 0),
+	ATA_MWDMA1		= ATA_MWDMA0 | (1 << 1),
+	ATA_MWDMA2		= ATA_MWDMA1 | (1 << 2),
+
+	ATA_MWDMA12_ONLY	= (1 << 1) | (1 << 2),
+	ATA_MWDMA2_ONLY		= (1 << 2),
+
+	ATA_UDMA0		= (1 << 0),
+	ATA_UDMA1		= ATA_UDMA0 | (1 << 1),
+	ATA_UDMA2		= ATA_UDMA1 | (1 << 2),
+	ATA_UDMA3		= ATA_UDMA2 | (1 << 3),
+	ATA_UDMA4		= ATA_UDMA3 | (1 << 4),
+	ATA_UDMA5		= ATA_UDMA4 | (1 << 5),
+	ATA_UDMA6		= ATA_UDMA5 | (1 << 6),
+	ATA_UDMA7		= ATA_UDMA6 | (1 << 7),
+	/* ATA_UDMA7 is just for completeness... doesn't exist (yet?).  */
+
+	ATA_UDMA_MASK_40C	= ATA_UDMA2,	/* udma0-2 */
+
+	/* DMA-related */
+	ATA_PRD_SZ		= 8,
+	ATA_PRD_TBL_SZ		= (ATA_MAX_PRD * ATA_PRD_SZ),
+	ATA_PRD_EOT		= (1 << 31),	/* end-of-table flag */
+
+	ATA_DMA_TABLE_OFS	= 4,
+	ATA_DMA_STATUS		= 2,
+	ATA_DMA_CMD		= 0,
+	ATA_DMA_WR		= (1 << 3),
+	ATA_DMA_START		= (1 << 0),
+	ATA_DMA_INTR		= (1 << 2),
+	ATA_DMA_ERR		= (1 << 1),
+	ATA_DMA_ACTIVE		= (1 << 0),
+
+	/* bits in ATA command block registers */
+	ATA_HOB			= (1 << 7),	/* LBA48 selector */
+	ATA_NIEN		= (1 << 1),	/* disable-irq flag */
+	ATA_LBA			= (1 << 6),	/* LBA28 selector */
+	ATA_DEV1		= (1 << 4),	/* Select Device 1 (slave) */
+	ATA_DEVICE_OBS		= (1 << 7) | (1 << 5), /* obs bits in dev reg */
+	ATA_DEVCTL_OBS		= (1 << 3),	/* obsolete bit in devctl reg */
+	ATA_BUSY		= (1 << 7),	/* BSY status bit */
+	ATA_DRDY		= (1 << 6),	/* device ready */
+	ATA_DF			= (1 << 5),	/* device fault */
+	ATA_DRQ			= (1 << 3),	/* data request i/o */
+	ATA_ERR			= (1 << 0),	/* have an error */
+	ATA_SRST		= (1 << 2),	/* software reset */
+	ATA_ICRC		= (1 << 7),	/* interface CRC error */
+	ATA_UNC			= (1 << 6),	/* uncorrectable media error */
+	ATA_IDNF		= (1 << 4),	/* ID not found */
+	ATA_ABORTED		= (1 << 2),	/* command aborted */
+
+	/* ATA command block registers */
+	ATA_REG_DATA		= 0x00,
+	ATA_REG_ERR		= 0x01,
+	ATA_REG_NSECT		= 0x02,
+	ATA_REG_LBAL		= 0x03,
+	ATA_REG_LBAM		= 0x04,
+	ATA_REG_LBAH		= 0x05,
+	ATA_REG_DEVICE		= 0x06,
+	ATA_REG_STATUS		= 0x07,
+
+	ATA_REG_FEATURE		= ATA_REG_ERR, /* and their aliases */
+	ATA_REG_CMD		= ATA_REG_STATUS,
+	ATA_REG_BYTEL		= ATA_REG_LBAM,
+	ATA_REG_BYTEH		= ATA_REG_LBAH,
+	ATA_REG_DEVSEL		= ATA_REG_DEVICE,
+	ATA_REG_IRQ		= ATA_REG_NSECT,
+
+	/* ATA device commands */
+	ATA_CMD_DEV_RESET	= 0x08, /* ATAPI device reset */
+	ATA_CMD_CHK_POWER	= 0xE5, /* check power mode */
+	ATA_CMD_STANDBY		= 0xE2, /* place in standby power mode */
+	ATA_CMD_IDLE		= 0xE3, /* place in idle power mode */
+	ATA_CMD_EDD		= 0x90,	/* execute device diagnostic */
+	ATA_CMD_FLUSH		= 0xE7,
+	ATA_CMD_FLUSH_EXT	= 0xEA,
+	ATA_CMD_ID_ATA		= 0xEC,
+	ATA_CMD_ID_ATAPI	= 0xA1,
+	ATA_CMD_READ		= 0xC8,
+	ATA_CMD_READ_EXT	= 0x25,
+	ATA_CMD_WRITE		= 0xCA,
+	ATA_CMD_WRITE_EXT	= 0x35,
+	ATA_CMD_WRITE_FUA_EXT	= 0x3D,
+	ATA_CMD_FPDMA_READ	= 0x60,
+	ATA_CMD_FPDMA_WRITE	= 0x61,
+	ATA_CMD_PIO_READ	= 0x20,
+	ATA_CMD_PIO_READ_EXT	= 0x24,
+	ATA_CMD_PIO_WRITE	= 0x30,
+	ATA_CMD_PIO_WRITE_EXT	= 0x34,
+	ATA_CMD_READ_MULTI	= 0xC4,
+	ATA_CMD_READ_MULTI_EXT	= 0x29,
+	ATA_CMD_WRITE_MULTI	= 0xC5,
+	ATA_CMD_WRITE_MULTI_EXT	= 0x39,
+	ATA_CMD_WRITE_MULTI_FUA_EXT = 0xCE,
+	ATA_CMD_SET_FEATURES	= 0xEF,
+	ATA_CMD_SET_MULTI	= 0xC6,
+	ATA_CMD_PACKET		= 0xA0,
+	ATA_CMD_VERIFY		= 0x40,
+	ATA_CMD_VERIFY_EXT	= 0x42,
+	ATA_CMD_STANDBYNOW1	= 0xE0,
+	ATA_CMD_IDLEIMMEDIATE	= 0xE1,
+	ATA_CMD_SLEEP		= 0xE6,
+	ATA_CMD_INIT_DEV_PARAMS	= 0x91,
+	ATA_CMD_READ_NATIVE_MAX	= 0xF8,
+	ATA_CMD_READ_NATIVE_MAX_EXT = 0x27,
+	ATA_CMD_SET_MAX		= 0xF9,
+	ATA_CMD_SET_MAX_EXT	= 0x37,
+	ATA_CMD_READ_LOG_EXT	= 0x2f,
+	ATA_CMD_PMP_READ	= 0xE4,
+	ATA_CMD_PMP_WRITE	= 0xE8,
+	ATA_CMD_CONF_OVERLAY	= 0xB1,
+	ATA_CMD_SEC_FREEZE_LOCK	= 0xF5,
+
+	/* READ_LOG_EXT pages */
+	ATA_LOG_SATA_NCQ	= 0x10,
+
+	/* READ/WRITE LONG (obsolete) */
+	ATA_CMD_READ_LONG	= 0x22,
+	ATA_CMD_READ_LONG_ONCE	= 0x23,
+	ATA_CMD_WRITE_LONG	= 0x32,
+	ATA_CMD_WRITE_LONG_ONCE	= 0x33,
+
+	/* SETFEATURES stuff */
+	SETFEATURES_XFER	= 0x03,
+	XFER_UDMA_7		= 0x47,
+	XFER_UDMA_6		= 0x46,
+	XFER_UDMA_5		= 0x45,
+	XFER_UDMA_4		= 0x44,
+	XFER_UDMA_3		= 0x43,
+	XFER_UDMA_2		= 0x42,
+	XFER_UDMA_1		= 0x41,
+	XFER_UDMA_0		= 0x40,
+	XFER_MW_DMA_4		= 0x24,	/* CFA only */
+	XFER_MW_DMA_3		= 0x23,	/* CFA only */
+	XFER_MW_DMA_2		= 0x22,
+	XFER_MW_DMA_1		= 0x21,
+	XFER_MW_DMA_0		= 0x20,
+	XFER_SW_DMA_2		= 0x12,
+	XFER_SW_DMA_1		= 0x11,
+	XFER_SW_DMA_0		= 0x10,
+	XFER_PIO_6		= 0x0E,	/* CFA only */
+	XFER_PIO_5		= 0x0D,	/* CFA only */
+	XFER_PIO_4		= 0x0C,
+	XFER_PIO_3		= 0x0B,
+	XFER_PIO_2		= 0x0A,
+	XFER_PIO_1		= 0x09,
+	XFER_PIO_0		= 0x08,
+	XFER_PIO_SLOW		= 0x00,
+
+	SETFEATURES_WC_ON	= 0x02, /* Enable write cache */
+	SETFEATURES_WC_OFF	= 0x82, /* Disable write cache */
+
+	SETFEATURES_SPINUP	= 0x07, /* Spin-up drive */
+
+	SETFEATURES_SATA_ENABLE = 0x10, /* Enable use of SATA feature */
+	SETFEATURES_SATA_DISABLE = 0x90, /* Disable use of SATA feature */
+
+	/* SETFEATURE Sector counts for SATA features */
+	SATA_AN			= 0x05,  /* Asynchronous Notification */
+	SATA_DIPM		= 0x03,  /* Device Initiated Power Management */
+
+	/* feature values for SET_MAX */
+	ATA_SET_MAX_ADDR	= 0x00,
+	ATA_SET_MAX_PASSWD	= 0x01,
+	ATA_SET_MAX_LOCK	= 0x02,
+	ATA_SET_MAX_UNLOCK	= 0x03,
+	ATA_SET_MAX_FREEZE_LOCK	= 0x04,
+
+	/* feature values for DEVICE CONFIGURATION OVERLAY */
+	ATA_DCO_RESTORE		= 0xC0,
+	ATA_DCO_FREEZE_LOCK	= 0xC1,
+	ATA_DCO_IDENTIFY	= 0xC2,
+	ATA_DCO_SET		= 0xC3,
+
+	/* ATAPI stuff */
+	ATAPI_PKT_DMA		= (1 << 0),
+	ATAPI_DMADIR		= (1 << 2),	/* ATAPI data dir:
+						   0=to device, 1=to host */
+	ATAPI_CDB_LEN		= 16,
+
+	/* PMP stuff */
+	SATA_PMP_MAX_PORTS	= 15,
+	SATA_PMP_CTRL_PORT	= 15,
+
+	SATA_PMP_GSCR_DWORDS	= 128,
+	SATA_PMP_GSCR_PROD_ID	= 0,
+	SATA_PMP_GSCR_REV	= 1,
+	SATA_PMP_GSCR_PORT_INFO	= 2,
+	SATA_PMP_GSCR_ERROR	= 32,
+	SATA_PMP_GSCR_ERROR_EN	= 33,
+	SATA_PMP_GSCR_FEAT	= 64,
+	SATA_PMP_GSCR_FEAT_EN	= 96,
+
+	SATA_PMP_PSCR_STATUS	= 0,
+	SATA_PMP_PSCR_ERROR	= 1,
+	SATA_PMP_PSCR_CONTROL	= 2,
+
+	SATA_PMP_FEAT_BIST	= (1 << 0),
+	SATA_PMP_FEAT_PMREQ	= (1 << 1),
+	SATA_PMP_FEAT_DYNSSC	= (1 << 2),
+	SATA_PMP_FEAT_NOTIFY	= (1 << 3),
+
+	/* cable types */
+	ATA_CBL_NONE		= 0,
+	ATA_CBL_PATA40		= 1,
+	ATA_CBL_PATA80		= 2,
+	ATA_CBL_PATA40_SHORT	= 3,	/* 40 wire cable to high UDMA spec */
+	ATA_CBL_PATA_UNK	= 4,	/* don't know, maybe 80c? */
+	ATA_CBL_PATA_IGN	= 5,	/* don't know, ignore cable handling */
+	ATA_CBL_SATA		= 6,
+
+	/* SATA Status and Control Registers */
+	SCR_STATUS		= 0,
+	SCR_ERROR		= 1,
+	SCR_CONTROL		= 2,
+	SCR_ACTIVE		= 3,
+	SCR_NOTIFICATION	= 4,
+
+	/* SError bits */
+	SERR_DATA_RECOVERED	= (1 << 0), /* recovered data error */
+	SERR_COMM_RECOVERED	= (1 << 1), /* recovered comm failure */
+	SERR_DATA		= (1 << 8), /* unrecovered data error */
+	SERR_PERSISTENT		= (1 << 9), /* persistent data/comm error */
+	SERR_PROTOCOL		= (1 << 10), /* protocol violation */
+	SERR_INTERNAL		= (1 << 11), /* host internal error */
+	SERR_PHYRDY_CHG		= (1 << 16), /* PHY RDY changed */
+	SERR_PHY_INT_ERR	= (1 << 17), /* PHY internal error */
+	SERR_COMM_WAKE		= (1 << 18), /* Comm wake */
+	SERR_10B_8B_ERR		= (1 << 19), /* 10b to 8b decode error */
+	SERR_DISPARITY		= (1 << 20), /* Disparity */
+	SERR_CRC		= (1 << 21), /* CRC error */
+	SERR_HANDSHAKE		= (1 << 22), /* Handshake error */
+	SERR_LINK_SEQ_ERR	= (1 << 23), /* Link sequence error */
+	SERR_TRANS_ST_ERROR	= (1 << 24), /* Transport state trans. error */
+	SERR_UNRECOG_FIS	= (1 << 25), /* Unrecognized FIS */
+	SERR_DEV_XCHG		= (1 << 26), /* device exchanged */
+
+	/* struct ata_taskfile flags */
+	ATA_TFLAG_LBA48		= (1 << 0), /* enable 48-bit LBA and "HOB" */
+	ATA_TFLAG_ISADDR	= (1 << 1), /* enable r/w to nsect/lba regs */
+	ATA_TFLAG_DEVICE	= (1 << 2), /* enable r/w to device reg */
+	ATA_TFLAG_WRITE		= (1 << 3), /* data dir: host->dev==1 (write) */
+	ATA_TFLAG_LBA		= (1 << 4), /* enable LBA */
+	ATA_TFLAG_FUA		= (1 << 5), /* enable FUA */
+	ATA_TFLAG_POLLING	= (1 << 6), /* set nIEN to 1 and use polling */
+
+	/* protocol flags */
+	ATA_PROT_FLAG_PIO	= (1 << 0), /* is PIO */
+	ATA_PROT_FLAG_DMA	= (1 << 1), /* is DMA */
+	ATA_PROT_FLAG_DATA	= ATA_PROT_FLAG_PIO | ATA_PROT_FLAG_DMA,
+	ATA_PROT_FLAG_NCQ	= (1 << 2), /* is NCQ */
+	ATA_PROT_FLAG_ATAPI	= (1 << 3), /* is ATAPI */
+};
+
+enum ata_tf_protocols {
+	/* ATA taskfile protocols */
+	ATA_PROT_UNKNOWN,	/* unknown/invalid */
+	ATA_PROT_NODATA,	/* no data */
+	ATA_PROT_PIO,		/* PIO data xfer */
+	ATA_PROT_DMA,		/* DMA */
+	ATA_PROT_NCQ,		/* NCQ */
+	ATAPI_PROT_NODATA,	/* packet command, no data */
+	ATAPI_PROT_PIO,		/* packet command, PIO data xfer*/
+	ATAPI_PROT_DMA,		/* packet command with special DMA sauce */
+};
+
+enum ata_ioctls {
+	ATA_IOC_GET_IO32	= 0x309,
+	ATA_IOC_SET_IO32	= 0x324,
+};
+
+enum ata_dev_typed {
+	ATA_DEV_ATA,		/* ATA device */
+	ATA_DEV_ATAPI,		/* ATAPI device */
+	ATA_DEV_PMP,		/* Port Multiplier Port */
+	ATA_DEV_UNKNOWN,	/* unknown */
+};
+
+struct ata_taskfile {
+	unsigned long		flags;		/* ATA_TFLAG_xxx */
+	u8			protocol;	/* ATA_PROT_xxx */
+
+	u8			ctl;		/* control reg */
+
+	u8			hob_feature;	/* additional data */
+	u8			hob_nsect;	/* to support LBA48 */
+	u8			hob_lbal;
+	u8			hob_lbam;
+	u8			hob_lbah;
+
+	u8			feature;
+	u8			nsect;
+	u8			lbal;
+	u8			lbam;
+	u8			lbah;
+
+	u8			device;
+
+	u8			command;	/* IO operation */
+};
+
+/*
+ * protocol tests
+ */
+static inline unsigned int ata_prot_flags(u8 prot)
+{
+	switch (prot) {
+	case ATA_PROT_NODATA:
+		return 0;
+	case ATA_PROT_PIO:
+		return ATA_PROT_FLAG_PIO;
+	case ATA_PROT_DMA:
+		return ATA_PROT_FLAG_DMA;
+	case ATA_PROT_NCQ:
+		return ATA_PROT_FLAG_DMA | ATA_PROT_FLAG_NCQ;
+	case ATAPI_PROT_NODATA:
+		return ATA_PROT_FLAG_ATAPI;
+	case ATAPI_PROT_PIO:
+		return ATA_PROT_FLAG_ATAPI | ATA_PROT_FLAG_PIO;
+	case ATAPI_PROT_DMA:
+		return ATA_PROT_FLAG_ATAPI | ATA_PROT_FLAG_DMA;
+	}
+	return 0;
+}
+
+static inline int ata_is_atapi(u8 prot)
+{
+	return ata_prot_flags(prot) & ATA_PROT_FLAG_ATAPI;
+}
+
+static inline int ata_is_nodata(u8 prot)
+{
+	return !(ata_prot_flags(prot) & ATA_PROT_FLAG_DATA);
+}
+
+static inline int ata_is_pio(u8 prot)
+{
+	return ata_prot_flags(prot) & ATA_PROT_FLAG_PIO;
+}
+
+static inline int ata_is_dma(u8 prot)
+{
+	return ata_prot_flags(prot) & ATA_PROT_FLAG_DMA;
+}
+
+static inline int ata_is_ncq(u8 prot)
+{
+	return ata_prot_flags(prot) & ATA_PROT_FLAG_NCQ;
+}
+
+static inline int ata_is_data(u8 prot)
+{
+	return ata_prot_flags(prot) & ATA_PROT_FLAG_DATA;
+}
+
+/*
+ * id tests
+ */
+#define ata_id_is_ata(id)		(((id)[0] & (1 << 15)) == 0)
+#define ata_id_has_lba(id)		((id)[49] & (1 << 9))
+#define ata_id_has_dma(id)		((id)[49] & (1 << 8))
+#define ata_id_has_ncq(id)		((id)[76] & (1 << 8))
+#define ata_id_queue_depth(id)		(((id)[75] & 0x1f) + 1)
+#define ata_id_removeable(id)		((id)[0] & (1 << 7))
+#define ata_id_iordy_disable(id)	((id)[49] & (1 << 10))
+#define ata_id_has_iordy(id)		((id)[49] & (1 << 11))
+
+#define ata_id_u32(id,n)	\
+	(((u32) (id)[(n) + 1] << 16) | ((u32) (id)[(n)]))
+#define ata_id_u64(id,n)	\
+	( ((u64) (id)[(n) + 3] << 48) | \
+	  ((u64) (id)[(n) + 2] << 32) | \
+	  ((u64) (id)[(n) + 1] << 16) | \
+	  ((u64) (id)[(n) + 0]) )
+
+#define ata_id_cdb_intr(id)		(((id)[0] & 0x60) == 0x20)
+
+static inline int ata_id_has_fua(const u16 *id)
+{
+	if ((id[84] & 0xC000) != 0x4000)
+		return 0;
+	return id[84] & (1 << 6);
+}
+
+static inline int ata_id_has_flush(const u16 *id)
+{
+	if ((id[83] & 0xC000) != 0x4000)
+		return 0;
+	return id[83] & (1 << 12);
+}
+
+static inline int ata_id_has_flush_ext(const u16 *id)
+{
+	if ((id[83] & 0xC000) != 0x4000)
+		return 0;
+	return id[83] & (1 << 13);
+}
+
+static inline int ata_id_has_lba48(const u16 *id)
+{
+	if ((id[83] & 0xC000) != 0x4000)
+		return 0;
+	if (!ata_id_u64(id, 100))
+		return 0;
+	return id[83] & (1 << 10);
+}
+
+static inline int ata_id_hpa_enabled(const u16 *id)
+{
+	/* Yes children, word 83 valid bits cover word 82 data */
+	if ((id[83] & 0xC000) != 0x4000)
+		return 0;
+	/* And 87 covers 85-87 */
+	if ((id[87] & 0xC000) != 0x4000)
+		return 0;
+	/* Check command sets enabled as well as supported */
+	if ((id[85] & ( 1 << 10)) == 0)
+		return 0;
+	return id[82] & (1 << 10);
+}
+
+static inline int ata_id_has_wcache(const u16 *id)
+{
+	/* Yes children, word 83 valid bits cover word 82 data */
+	if ((id[83] & 0xC000) != 0x4000)
+		return 0;
+	return id[82] & (1 << 5);
+}
+
+static inline int ata_id_has_pm(const u16 *id)
+{
+	if ((id[83] & 0xC000) != 0x4000)
+		return 0;
+	return id[82] & (1 << 3);
+}
+
+static inline int ata_id_rahead_enabled(const u16 *id)
+{
+	if ((id[87] & 0xC000) != 0x4000)
+		return 0;
+	return id[85] & (1 << 6);
+}
+
+static inline int ata_id_wcache_enabled(const u16 *id)
+{
+	if ((id[87] & 0xC000) != 0x4000)
+		return 0;
+	return id[85] & (1 << 5);
+}
+
+static inline unsigned int ata_id_major_version(const u16 *id)
+{
+	unsigned int mver;
+
+	if (id[ATA_ID_MAJOR_VER] == 0xFFFF)
+		return 0;
+
+	for (mver = 14; mver >= 1; mver--)
+		if (id[ATA_ID_MAJOR_VER] & (1 << mver))
+			break;
+	return mver;
+}
+
+static inline int ata_id_is_sata(const u16 *id)
+{
+	return ata_id_major_version(id) >= 5 && id[93] == 0;
+}
+
+static inline int ata_id_has_tpm(const u16 *id)
+{
+	/* The TPM bits are only valid on ATA8 */
+	if (ata_id_major_version(id) < 8)
+		return 0;
+	if ((id[48] & 0xC000) != 0x4000)
+		return 0;
+	return id[48] & (1 << 0);
+}
+
+static inline int ata_id_has_dword_io(const u16 *id)
+{
+	/* ATA 8 reuses this flag for "trusted" computing */
+	if (ata_id_major_version(id) > 7)
+		return 0;
+	if (id[48] & (1 << 0))
+		return 1;
+	return 0;
+}
+
+static inline int ata_id_current_chs_valid(const u16 *id)
+{
+	/* For ATA-1 devices, if the INITIALIZE DEVICE PARAMETERS command
+	   has not been issued to the device then the values of
+	   id[54] to id[56] are vendor specific. */
+	return (id[53] & 0x01) && /* Current translation valid */
+		id[54] &&  /* cylinders in current translation */
+		id[55] &&  /* heads in current translation */
+		id[55] <= 16 &&
+		id[56];    /* sectors in current translation */
+}
+
+static inline int ata_id_is_cfa(const u16 *id)
+{
+	u16 v = id[0];
+	if (v == 0x848A)	/* Standard CF */
+		return 1;
+	/* Could be CF hiding as standard ATA */
+	if (ata_id_major_version(id) >= 3 &&  id[82] != 0xFFFF &&
+			(id[82] & ( 1 << 2)))
+		return 1;
+	return 0;
+}
+
+static inline int ata_drive_40wire(const u16 *dev_id)
+{
+	if (ata_id_is_sata(dev_id))
+		return 0;	/* SATA */
+	if ((dev_id[93] & 0xE000) == 0x6000)
+		return 0;	/* 80 wire */
+	return 1;
+}
+
+static inline int ata_drive_40wire_relaxed(const u16 *dev_id)
+{
+	if ((dev_id[93] & 0x2000) == 0x2000)
+		return 0;	/* 80 wire */
+	return 1;
+}
+
+static inline int atapi_cdb_len(const u16 *dev_id)
+{
+	u16 tmp = dev_id[0] & 0x3;
+	switch (tmp) {
+	case 0:		return 12;
+	case 1:		return 16;
+	default:	return -1;
+	}
+}
+
+static inline int atapi_command_packet_set(const u16 *dev_id)
+{
+	return (dev_id[0] >> 8) & 0x1f;
+}
+
+static inline int atapi_id_dmadir(const u16 *dev_id)
+{
+	return ata_id_major_version(dev_id) >= 7 && (dev_id[62] & 0x8000);
+}
+
+static inline int is_multi_taskfile(struct ata_taskfile *tf)
+{
+	return (tf->command == ATA_CMD_READ_MULTI) ||
+	       (tf->command == ATA_CMD_WRITE_MULTI) ||
+	       (tf->command == ATA_CMD_READ_MULTI_EXT) ||
+	       (tf->command == ATA_CMD_WRITE_MULTI_EXT) ||
+	       (tf->command == ATA_CMD_WRITE_MULTI_FUA_EXT);
+}
+
+static inline int ata_ok(u8 status)
+{
+	return ((status & (ATA_BUSY | ATA_DRDY | ATA_DF | ATA_DRQ | ATA_ERR))
+			== ATA_DRDY);
+}
+
+static inline int lba_28_ok(u64 block, u32 n_block)
+{
+	/* check the ending block number */
+	return ((block + n_block - 1) < ((u64)1 << 28)) && (n_block <= 256);
+}
+
+static inline int lba_48_ok(u64 block, u32 n_block)
+{
+	/* check the ending block number */
+	return ((block + n_block - 1) < ((u64)1 << 48)) && (n_block <= 65536);
+}
+
+#define sata_pmp_gscr_vendor(gscr)	((gscr)[SATA_PMP_GSCR_PROD_ID] & 0xffff)
+#define sata_pmp_gscr_devid(gscr)	((gscr)[SATA_PMP_GSCR_PROD_ID] >> 16)
+#define sata_pmp_gscr_rev(gscr)		(((gscr)[SATA_PMP_GSCR_REV] >> 8) & 0xff)
+#define sata_pmp_gscr_ports(gscr)	((gscr)[SATA_PMP_GSCR_PORT_INFO] & 0xf)
+
+u64 ata_id_n_sectors(u16 *id);
+u32 ata_dev_classify(u32 sig);
+void ata_id_c_string(const u16 *id, unsigned char *s,
+			 unsigned int ofs, unsigned int len);
+void ata_dump_id(u16 *id);
+void ata_swap_buf_le16(u16 *buf, unsigned int buf_words);
+
+#endif /* __LIBATA_H__ */
diff --git a/qemu/roms/u-boot/include/libfdt.h b/qemu/roms/u-boot/include/libfdt.h
new file mode 100644
index 000000000..9eefaaf5f
--- /dev/null
+++ b/qemu/roms/u-boot/include/libfdt.h
@@ -0,0 +1,1578 @@
+#ifndef _LIBFDT_H
+#define _LIBFDT_H
+/*
+ * libfdt - Flat Device Tree manipulation
+ * Copyright (C) 2006 David Gibson, IBM Corporation.
+ *
+ * libfdt is dual licensed: you can use it either under the terms of
+ * the GPL, or the BSD license, at your option.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this library; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Alternatively,
+ *
+ *  b) Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *     1. Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *     2. Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ *     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ *     CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ *     INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ *     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ *     CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *     SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *     NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *     HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ *     OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ *     EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <libfdt_env.h>
+#include <fdt.h>
+
+#define FDT_FIRST_SUPPORTED_VERSION	0x10
+#define FDT_LAST_SUPPORTED_VERSION	0x11
+
+/* Error codes: informative error codes */
+#define FDT_ERR_NOTFOUND	1
+	/* FDT_ERR_NOTFOUND: The requested node or property does not exist */
+#define FDT_ERR_EXISTS		2
+	/* FDT_ERR_EXISTS: Attemped to create a node or property which
+	 * already exists */
+#define FDT_ERR_NOSPACE		3
+	/* FDT_ERR_NOSPACE: Operation needed to expand the device
+	 * tree, but its buffer did not have sufficient space to
+	 * contain the expanded tree. Use fdt_open_into() to move the
+	 * device tree to a buffer with more space. */
+
+/* Error codes: codes for bad parameters */
+#define FDT_ERR_BADOFFSET	4
+	/* FDT_ERR_BADOFFSET: Function was passed a structure block
+	 * offset which is out-of-bounds, or which points to an
+	 * unsuitable part of the structure for the operation. */
+#define FDT_ERR_BADPATH		5
+	/* FDT_ERR_BADPATH: Function was passed a badly formatted path
+	 * (e.g. missing a leading / for a function which requires an
+	 * absolute path) */
+#define FDT_ERR_BADPHANDLE	6
+	/* FDT_ERR_BADPHANDLE: Function was passed an invalid phandle
+	 * value.  phandle values of 0 and -1 are not permitted. */
+#define FDT_ERR_BADSTATE	7
+	/* FDT_ERR_BADSTATE: Function was passed an incomplete device
+	 * tree created by the sequential-write functions, which is
+	 * not sufficiently complete for the requested operation. */
+
+/* Error codes: codes for bad device tree blobs */
+#define FDT_ERR_TRUNCATED	8
+	/* FDT_ERR_TRUNCATED: Structure block of the given device tree
+	 * ends without an FDT_END tag. */
+#define FDT_ERR_BADMAGIC	9
+	/* FDT_ERR_BADMAGIC: Given "device tree" appears not to be a
+	 * device tree at all - it is missing the flattened device
+	 * tree magic number. */
+#define FDT_ERR_BADVERSION	10
+	/* FDT_ERR_BADVERSION: Given device tree has a version which
+	 * can't be handled by the requested operation.  For
+	 * read-write functions, this may mean that fdt_open_into() is
+	 * required to convert the tree to the expected version. */
+#define FDT_ERR_BADSTRUCTURE	11
+	/* FDT_ERR_BADSTRUCTURE: Given device tree has a corrupt
+	 * structure block or other serious error (e.g. misnested
+	 * nodes, or subnodes preceding properties). */
+#define FDT_ERR_BADLAYOUT	12
+	/* FDT_ERR_BADLAYOUT: For read-write functions, the given
+	 * device tree has it's sub-blocks in an order that the
+	 * function can't handle (memory reserve map, then structure,
+	 * then strings).  Use fdt_open_into() to reorganize the tree
+	 * into a form suitable for the read-write operations. */
+
+/* "Can't happen" error indicating a bug in libfdt */
+#define FDT_ERR_INTERNAL	13
+	/* FDT_ERR_INTERNAL: libfdt has failed an internal assertion.
+	 * Should never be returned, if it is, it indicates a bug in
+	 * libfdt itself. */
+
+#define FDT_ERR_MAX		13
+
+/**********************************************************************/
+/* Low-level functions (you probably don't need these)                */
+/**********************************************************************/
+
+const void *fdt_offset_ptr(const void *fdt, int offset, unsigned int checklen);
+static inline void *fdt_offset_ptr_w(void *fdt, int offset, int checklen)
+{
+	return (void *)(uintptr_t)fdt_offset_ptr(fdt, offset, checklen);
+}
+
+uint32_t fdt_next_tag(const void *fdt, int offset, int *nextoffset);
+
+/**********************************************************************/
+/* Traversal functions                                                */
+/**********************************************************************/
+
+int fdt_next_node(const void *fdt, int offset, int *depth);
+
+/**
+ * fdt_first_subnode() - get offset of first direct subnode
+ *
+ * @fdt:	FDT blob
+ * @offset:	Offset of node to check
+ * @return offset of first subnode, or -FDT_ERR_NOTFOUND if there is none
+ */
+int fdt_first_subnode(const void *fdt, int offset);
+
+/**
+ * fdt_next_subnode() - get offset of next direct subnode
+ *
+ * After first calling fdt_first_subnode(), call this function repeatedly to
+ * get direct subnodes of a parent node.
+ *
+ * @fdt:	FDT blob
+ * @offset:	Offset of previous subnode
+ * @return offset of next subnode, or -FDT_ERR_NOTFOUND if there are no more
+ * subnodes
+ */
+int fdt_next_subnode(const void *fdt, int offset);
+
+/**********************************************************************/
+/* General functions                                                  */
+/**********************************************************************/
+
+#define fdt_get_header(fdt, field) \
+	(fdt32_to_cpu(((const struct fdt_header *)(fdt))->field))
+#define fdt_magic(fdt)			(fdt_get_header(fdt, magic))
+#define fdt_totalsize(fdt)		(fdt_get_header(fdt, totalsize))
+#define fdt_off_dt_struct(fdt)		(fdt_get_header(fdt, off_dt_struct))
+#define fdt_off_dt_strings(fdt)		(fdt_get_header(fdt, off_dt_strings))
+#define fdt_off_mem_rsvmap(fdt)		(fdt_get_header(fdt, off_mem_rsvmap))
+#define fdt_version(fdt)		(fdt_get_header(fdt, version))
+#define fdt_last_comp_version(fdt)	(fdt_get_header(fdt, last_comp_version))
+#define fdt_boot_cpuid_phys(fdt)	(fdt_get_header(fdt, boot_cpuid_phys))
+#define fdt_size_dt_strings(fdt)	(fdt_get_header(fdt, size_dt_strings))
+#define fdt_size_dt_struct(fdt)		(fdt_get_header(fdt, size_dt_struct))
+
+#define __fdt_set_hdr(name) \
+	static inline void fdt_set_##name(void *fdt, uint32_t val) \
+	{ \
+		struct fdt_header *fdth = (struct fdt_header*)fdt; \
+		fdth->name = cpu_to_fdt32(val); \
+	}
+__fdt_set_hdr(magic);
+__fdt_set_hdr(totalsize);
+__fdt_set_hdr(off_dt_struct);
+__fdt_set_hdr(off_dt_strings);
+__fdt_set_hdr(off_mem_rsvmap);
+__fdt_set_hdr(version);
+__fdt_set_hdr(last_comp_version);
+__fdt_set_hdr(boot_cpuid_phys);
+__fdt_set_hdr(size_dt_strings);
+__fdt_set_hdr(size_dt_struct);
+#undef __fdt_set_hdr
+
+/**
+ * fdt_check_header - sanity check a device tree or possible device tree
+ * @fdt: pointer to data which might be a flattened device tree
+ *
+ * fdt_check_header() checks that the given buffer contains what
+ * appears to be a flattened device tree with sane information in its
+ * header.
+ *
+ * returns:
+ *     0, if the buffer appears to contain a valid device tree
+ *     -FDT_ERR_BADMAGIC,
+ *     -FDT_ERR_BADVERSION,
+ *     -FDT_ERR_BADSTATE, standard meanings, as above
+ */
+int fdt_check_header(const void *fdt);
+
+/**
+ * fdt_move - move a device tree around in memory
+ * @fdt: pointer to the device tree to move
+ * @buf: pointer to memory where the device is to be moved
+ * @bufsize: size of the memory space at buf
+ *
+ * fdt_move() relocates, if possible, the device tree blob located at
+ * fdt to the buffer at buf of size bufsize.  The buffer may overlap
+ * with the existing device tree blob at fdt.  Therefore,
+ *     fdt_move(fdt, fdt, fdt_totalsize(fdt))
+ * should always succeed.
+ *
+ * returns:
+ *     0, on success
+ *     -FDT_ERR_NOSPACE, bufsize is insufficient to contain the device tree
+ *     -FDT_ERR_BADMAGIC,
+ *     -FDT_ERR_BADVERSION,
+ *     -FDT_ERR_BADSTATE, standard meanings
+ */
+int fdt_move(const void *fdt, void *buf, int bufsize);
+
+/**********************************************************************/
+/* Read-only functions                                                */
+/**********************************************************************/
+
+/**
+ * fdt_string - retrieve a string from the strings block of a device tree
+ * @fdt: pointer to the device tree blob
+ * @stroffset: offset of the string within the strings block (native endian)
+ *
+ * fdt_string() retrieves a pointer to a single string from the
+ * strings block of the device tree blob at fdt.
+ *
+ * returns:
+ *     a pointer to the string, on success
+ *     NULL, if stroffset is out of bounds
+ */
+const char *fdt_string(const void *fdt, int stroffset);
+
+/**
+ * fdt_num_mem_rsv - retrieve the number of memory reserve map entries
+ * @fdt: pointer to the device tree blob
+ *
+ * Returns the number of entries in the device tree blob's memory
+ * reservation map.  This does not include the terminating 0,0 entry
+ * or any other (0,0) entries reserved for expansion.
+ *
+ * returns:
+ *     the number of entries
+ */
+int fdt_num_mem_rsv(const void *fdt);
+
+/**
+ * fdt_get_mem_rsv - retrieve one memory reserve map entry
+ * @fdt: pointer to the device tree blob
+ * @address, @size: pointers to 64-bit variables
+ *
+ * On success, *address and *size will contain the address and size of
+ * the n-th reserve map entry from the device tree blob, in
+ * native-endian format.
+ *
+ * returns:
+ *     0, on success
+ *     -FDT_ERR_BADMAGIC,
+ *     -FDT_ERR_BADVERSION,
+ *     -FDT_ERR_BADSTATE, standard meanings
+ */
+int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size);
+
+/**
+ * fdt_subnode_offset_namelen - find a subnode based on substring
+ * @fdt: pointer to the device tree blob
+ * @parentoffset: structure block offset of a node
+ * @name: name of the subnode to locate
+ * @namelen: number of characters of name to consider
+ *
+ * Identical to fdt_subnode_offset(), but only examine the first
+ * namelen characters of name for matching the subnode name.  This is
+ * useful for finding subnodes based on a portion of a larger string,
+ * such as a full path.
+ */
+int fdt_subnode_offset_namelen(const void *fdt, int parentoffset,
+			       const char *name, int namelen);
+/**
+ * fdt_subnode_offset - find a subnode of a given node
+ * @fdt: pointer to the device tree blob
+ * @parentoffset: structure block offset of a node
+ * @name: name of the subnode to locate
+ *
+ * fdt_subnode_offset() finds a subnode of the node at structure block
+ * offset parentoffset with the given name.  name may include a unit
+ * address, in which case fdt_subnode_offset() will find the subnode
+ * with that unit address, or the unit address may be omitted, in
+ * which case fdt_subnode_offset() will find an arbitrary subnode
+ * whose name excluding unit address matches the given name.
+ *
+ * returns:
+ *	structure block offset of the requested subnode (>=0), on success
+ *	-FDT_ERR_NOTFOUND, if the requested subnode does not exist
+ *	-FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE tag
+ *      -FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings.
+ */
+int fdt_subnode_offset(const void *fdt, int parentoffset, const char *name);
+
+/**
+ * fdt_path_offset - find a tree node by its full path
+ * @fdt: pointer to the device tree blob
+ * @path: full path of the node to locate
+ *
+ * fdt_path_offset() finds a node of a given path in the device tree.
+ * Each path component may omit the unit address portion, but the
+ * results of this are undefined if any such path component is
+ * ambiguous (that is if there are multiple nodes at the relevant
+ * level matching the given component, differentiated only by unit
+ * address).
+ *
+ * returns:
+ *	structure block offset of the node with the requested path (>=0), on success
+ *	-FDT_ERR_BADPATH, given path does not begin with '/' or is invalid
+ *	-FDT_ERR_NOTFOUND, if the requested node does not exist
+ *      -FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings.
+ */
+int fdt_path_offset(const void *fdt, const char *path);
+
+/**
+ * fdt_get_name - retrieve the name of a given node
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: structure block offset of the starting node
+ * @lenp: pointer to an integer variable (will be overwritten) or NULL
+ *
+ * fdt_get_name() retrieves the name (including unit address) of the
+ * device tree node at structure block offset nodeoffset.  If lenp is
+ * non-NULL, the length of this name is also returned, in the integer
+ * pointed to by lenp.
+ *
+ * returns:
+ *	pointer to the node's name, on success
+ *		If lenp is non-NULL, *lenp contains the length of that name (>=0)
+ *	NULL, on error
+ *		if lenp is non-NULL *lenp contains an error code (<0):
+ *		-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *		-FDT_ERR_BADMAGIC,
+ *		-FDT_ERR_BADVERSION,
+ *		-FDT_ERR_BADSTATE, standard meanings
+ */
+const char *fdt_get_name(const void *fdt, int nodeoffset, int *lenp);
+
+/**
+ * fdt_first_property_offset - find the offset of a node's first property
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: structure block offset of a node
+ *
+ * fdt_first_property_offset() finds the first property of the node at
+ * the given structure block offset.
+ *
+ * returns:
+ *	structure block offset of the property (>=0), on success
+ *	-FDT_ERR_NOTFOUND, if the requested node has no properties
+ *	-FDT_ERR_BADOFFSET, if nodeoffset did not point to an FDT_BEGIN_NODE tag
+ *      -FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings.
+ */
+int fdt_first_property_offset(const void *fdt, int nodeoffset);
+
+/**
+ * fdt_next_property_offset - step through a node's properties
+ * @fdt: pointer to the device tree blob
+ * @offset: structure block offset of a property
+ *
+ * fdt_next_property_offset() finds the property immediately after the
+ * one at the given structure block offset.  This will be a property
+ * of the same node as the given property.
+ *
+ * returns:
+ *	structure block offset of the next property (>=0), on success
+ *	-FDT_ERR_NOTFOUND, if the given property is the last in its node
+ *	-FDT_ERR_BADOFFSET, if nodeoffset did not point to an FDT_PROP tag
+ *      -FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings.
+ */
+int fdt_next_property_offset(const void *fdt, int offset);
+
+/**
+ * fdt_get_property_by_offset - retrieve the property at a given offset
+ * @fdt: pointer to the device tree blob
+ * @offset: offset of the property to retrieve
+ * @lenp: pointer to an integer variable (will be overwritten) or NULL
+ *
+ * fdt_get_property_by_offset() retrieves a pointer to the
+ * fdt_property structure within the device tree blob at the given
+ * offset.  If lenp is non-NULL, the length of the property value is
+ * also returned, in the integer pointed to by lenp.
+ *
+ * returns:
+ *	pointer to the structure representing the property
+ *		if lenp is non-NULL, *lenp contains the length of the property
+ *		value (>=0)
+ *	NULL, on error
+ *		if lenp is non-NULL, *lenp contains an error code (<0):
+ *		-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_PROP tag
+ *		-FDT_ERR_BADMAGIC,
+ *		-FDT_ERR_BADVERSION,
+ *		-FDT_ERR_BADSTATE,
+ *		-FDT_ERR_BADSTRUCTURE,
+ *		-FDT_ERR_TRUNCATED, standard meanings
+ */
+const struct fdt_property *fdt_get_property_by_offset(const void *fdt,
+						      int offset,
+						      int *lenp);
+
+/**
+ * fdt_get_property_namelen - find a property based on substring
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to find
+ * @name: name of the property to find
+ * @namelen: number of characters of name to consider
+ * @lenp: pointer to an integer variable (will be overwritten) or NULL
+ *
+ * Identical to fdt_get_property_namelen(), but only examine the first
+ * namelen characters of name for matching the property name.
+ */
+const struct fdt_property *fdt_get_property_namelen(const void *fdt,
+						    int nodeoffset,
+						    const char *name,
+						    int namelen, int *lenp);
+
+/**
+ * fdt_get_property - find a given property in a given node
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to find
+ * @name: name of the property to find
+ * @lenp: pointer to an integer variable (will be overwritten) or NULL
+ *
+ * fdt_get_property() retrieves a pointer to the fdt_property
+ * structure within the device tree blob corresponding to the property
+ * named 'name' of the node at offset nodeoffset.  If lenp is
+ * non-NULL, the length of the property value is also returned, in the
+ * integer pointed to by lenp.
+ *
+ * returns:
+ *	pointer to the structure representing the property
+ *		if lenp is non-NULL, *lenp contains the length of the property
+ *		value (>=0)
+ *	NULL, on error
+ *		if lenp is non-NULL, *lenp contains an error code (<0):
+ *		-FDT_ERR_NOTFOUND, node does not have named property
+ *		-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *		-FDT_ERR_BADMAGIC,
+ *		-FDT_ERR_BADVERSION,
+ *		-FDT_ERR_BADSTATE,
+ *		-FDT_ERR_BADSTRUCTURE,
+ *		-FDT_ERR_TRUNCATED, standard meanings
+ */
+const struct fdt_property *fdt_get_property(const void *fdt, int nodeoffset,
+					    const char *name, int *lenp);
+static inline struct fdt_property *fdt_get_property_w(void *fdt, int nodeoffset,
+						      const char *name,
+						      int *lenp)
+{
+	return (struct fdt_property *)(uintptr_t)
+		fdt_get_property(fdt, nodeoffset, name, lenp);
+}
+
+/**
+ * fdt_getprop_by_offset - retrieve the value of a property at a given offset
+ * @fdt: pointer to the device tree blob
+ * @ffset: offset of the property to read
+ * @namep: pointer to a string variable (will be overwritten) or NULL
+ * @lenp: pointer to an integer variable (will be overwritten) or NULL
+ *
+ * fdt_getprop_by_offset() retrieves a pointer to the value of the
+ * property at structure block offset 'offset' (this will be a pointer
+ * to within the device blob itself, not a copy of the value).  If
+ * lenp is non-NULL, the length of the property value is also
+ * returned, in the integer pointed to by lenp.  If namep is non-NULL,
+ * the property's namne will also be returned in the char * pointed to
+ * by namep (this will be a pointer to within the device tree's string
+ * block, not a new copy of the name).
+ *
+ * returns:
+ *	pointer to the property's value
+ *		if lenp is non-NULL, *lenp contains the length of the property
+ *		value (>=0)
+ *		if namep is non-NULL *namep contiains a pointer to the property
+ *		name.
+ *	NULL, on error
+ *		if lenp is non-NULL, *lenp contains an error code (<0):
+ *		-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_PROP tag
+ *		-FDT_ERR_BADMAGIC,
+ *		-FDT_ERR_BADVERSION,
+ *		-FDT_ERR_BADSTATE,
+ *		-FDT_ERR_BADSTRUCTURE,
+ *		-FDT_ERR_TRUNCATED, standard meanings
+ */
+const void *fdt_getprop_by_offset(const void *fdt, int offset,
+				  const char **namep, int *lenp);
+
+/**
+ * fdt_getprop_namelen - get property value based on substring
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to find
+ * @name: name of the property to find
+ * @namelen: number of characters of name to consider
+ * @lenp: pointer to an integer variable (will be overwritten) or NULL
+ *
+ * Identical to fdt_getprop(), but only examine the first namelen
+ * characters of name for matching the property name.
+ */
+const void *fdt_getprop_namelen(const void *fdt, int nodeoffset,
+				const char *name, int namelen, int *lenp);
+
+/**
+ * fdt_getprop - retrieve the value of a given property
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to find
+ * @name: name of the property to find
+ * @lenp: pointer to an integer variable (will be overwritten) or NULL
+ *
+ * fdt_getprop() retrieves a pointer to the value of the property
+ * named 'name' of the node at offset nodeoffset (this will be a
+ * pointer to within the device blob itself, not a copy of the value).
+ * If lenp is non-NULL, the length of the property value is also
+ * returned, in the integer pointed to by lenp.
+ *
+ * returns:
+ *	pointer to the property's value
+ *		if lenp is non-NULL, *lenp contains the length of the property
+ *		value (>=0)
+ *	NULL, on error
+ *		if lenp is non-NULL, *lenp contains an error code (<0):
+ *		-FDT_ERR_NOTFOUND, node does not have named property
+ *		-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *		-FDT_ERR_BADMAGIC,
+ *		-FDT_ERR_BADVERSION,
+ *		-FDT_ERR_BADSTATE,
+ *		-FDT_ERR_BADSTRUCTURE,
+ *		-FDT_ERR_TRUNCATED, standard meanings
+ */
+const void *fdt_getprop(const void *fdt, int nodeoffset,
+			const char *name, int *lenp);
+static inline void *fdt_getprop_w(void *fdt, int nodeoffset,
+				  const char *name, int *lenp)
+{
+	return (void *)(uintptr_t)fdt_getprop(fdt, nodeoffset, name, lenp);
+}
+
+/**
+ * fdt_get_phandle - retrieve the phandle of a given node
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: structure block offset of the node
+ *
+ * fdt_get_phandle() retrieves the phandle of the device tree node at
+ * structure block offset nodeoffset.
+ *
+ * returns:
+ *	the phandle of the node at nodeoffset, on success (!= 0, != -1)
+ *	0, if the node has no phandle, or another error occurs
+ */
+uint32_t fdt_get_phandle(const void *fdt, int nodeoffset);
+
+/**
+ * fdt_get_alias_namelen - get alias based on substring
+ * @fdt: pointer to the device tree blob
+ * @name: name of the alias th look up
+ * @namelen: number of characters of name to consider
+ *
+ * Identical to fdt_get_alias(), but only examine the first namelen
+ * characters of name for matching the alias name.
+ */
+const char *fdt_get_alias_namelen(const void *fdt,
+				  const char *name, int namelen);
+
+/**
+ * fdt_get_alias - retrieve the path referenced by a given alias
+ * @fdt: pointer to the device tree blob
+ * @name: name of the alias to look up
+ *
+ * fdt_get_alias() retrieves the value of a given alias.  That is, the
+ * value of the property named 'name' in the node /aliases.
+ *
+ * returns:
+ *	a pointer to the expansion of the alias named 'name', if it exists
+ *	NULL, if the given alias or the /aliases node does not exist
+ */
+const char *fdt_get_alias(const void *fdt, const char *name);
+
+/**
+ * fdt_get_path - determine the full path of a node
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose path to find
+ * @buf: character buffer to contain the returned path (will be overwritten)
+ * @buflen: size of the character buffer at buf
+ *
+ * fdt_get_path() computes the full path of the node at offset
+ * nodeoffset, and records that path in the buffer at buf.
+ *
+ * NOTE: This function is expensive, as it must scan the device tree
+ * structure from the start to nodeoffset.
+ *
+ * returns:
+ *	0, on success
+ *		buf contains the absolute path of the node at
+ *		nodeoffset, as a NUL-terminated string.
+ *	-FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
+ *	-FDT_ERR_NOSPACE, the path of the given node is longer than (bufsize-1)
+ *		characters and will not fit in the given buffer.
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE, standard meanings
+ */
+int fdt_get_path(const void *fdt, int nodeoffset, char *buf, int buflen);
+
+/**
+ * fdt_supernode_atdepth_offset - find a specific ancestor of a node
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose parent to find
+ * @supernodedepth: depth of the ancestor to find
+ * @nodedepth: pointer to an integer variable (will be overwritten) or NULL
+ *
+ * fdt_supernode_atdepth_offset() finds an ancestor of the given node
+ * at a specific depth from the root (where the root itself has depth
+ * 0, its immediate subnodes depth 1 and so forth).  So
+ *	fdt_supernode_atdepth_offset(fdt, nodeoffset, 0, NULL);
+ * will always return 0, the offset of the root node.  If the node at
+ * nodeoffset has depth D, then:
+ *	fdt_supernode_atdepth_offset(fdt, nodeoffset, D, NULL);
+ * will return nodeoffset itself.
+ *
+ * NOTE: This function is expensive, as it must scan the device tree
+ * structure from the start to nodeoffset.
+ *
+ * returns:
+
+ *	structure block offset of the node at node offset's ancestor
+ *		of depth supernodedepth (>=0), on success
+ *	-FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
+*	-FDT_ERR_NOTFOUND, supernodedepth was greater than the depth of nodeoffset
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE, standard meanings
+ */
+int fdt_supernode_atdepth_offset(const void *fdt, int nodeoffset,
+				 int supernodedepth, int *nodedepth);
+
+/**
+ * fdt_node_depth - find the depth of a given node
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose parent to find
+ *
+ * fdt_node_depth() finds the depth of a given node.  The root node
+ * has depth 0, its immediate subnodes depth 1 and so forth.
+ *
+ * NOTE: This function is expensive, as it must scan the device tree
+ * structure from the start to nodeoffset.
+ *
+ * returns:
+ *	depth of the node at nodeoffset (>=0), on success
+ *	-FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE, standard meanings
+ */
+int fdt_node_depth(const void *fdt, int nodeoffset);
+
+/**
+ * fdt_parent_offset - find the parent of a given node
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose parent to find
+ *
+ * fdt_parent_offset() locates the parent node of a given node (that
+ * is, it finds the offset of the node which contains the node at
+ * nodeoffset as a subnode).
+ *
+ * NOTE: This function is expensive, as it must scan the device tree
+ * structure from the start to nodeoffset, *twice*.
+ *
+ * returns:
+ *	structure block offset of the parent of the node at nodeoffset
+ *		(>=0), on success
+ *	-FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE, standard meanings
+ */
+int fdt_parent_offset(const void *fdt, int nodeoffset);
+
+/**
+ * fdt_node_offset_by_prop_value - find nodes with a given property value
+ * @fdt: pointer to the device tree blob
+ * @startoffset: only find nodes after this offset
+ * @propname: property name to check
+ * @propval: property value to search for
+ * @proplen: length of the value in propval
+ *
+ * fdt_node_offset_by_prop_value() returns the offset of the first
+ * node after startoffset, which has a property named propname whose
+ * value is of length proplen and has value equal to propval; or if
+ * startoffset is -1, the very first such node in the tree.
+ *
+ * To iterate through all nodes matching the criterion, the following
+ * idiom can be used:
+ *	offset = fdt_node_offset_by_prop_value(fdt, -1, propname,
+ *					       propval, proplen);
+ *	while (offset != -FDT_ERR_NOTFOUND) {
+ *		... other code here ...
+ *		offset = fdt_node_offset_by_prop_value(fdt, offset, propname,
+ *						       propval, proplen);
+ *	}
+ *
+ * Note the -1 in the first call to the function, if 0 is used here
+ * instead, the function will never locate the root node, even if it
+ * matches the criterion.
+ *
+ * returns:
+ *	structure block offset of the located node (>= 0, >startoffset),
+ *		 on success
+ *	-FDT_ERR_NOTFOUND, no node matching the criterion exists in the
+ *		tree after startoffset
+ *	-FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE, standard meanings
+ */
+int fdt_node_offset_by_prop_value(const void *fdt, int startoffset,
+				  const char *propname,
+				  const void *propval, int proplen);
+
+/**
+ * fdt_node_offset_by_phandle - find the node with a given phandle
+ * @fdt: pointer to the device tree blob
+ * @phandle: phandle value
+ *
+ * fdt_node_offset_by_phandle() returns the offset of the node
+ * which has the given phandle value.  If there is more than one node
+ * in the tree with the given phandle (an invalid tree), results are
+ * undefined.
+ *
+ * returns:
+ *	structure block offset of the located node (>= 0), on success
+ *	-FDT_ERR_NOTFOUND, no node with that phandle exists
+ *	-FDT_ERR_BADPHANDLE, given phandle value was invalid (0 or -1)
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE, standard meanings
+ */
+int fdt_node_offset_by_phandle(const void *fdt, uint32_t phandle);
+
+/**
+ * fdt_node_check_compatible: check a node's compatible property
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of a tree node
+ * @compatible: string to match against
+ *
+ *
+ * fdt_node_check_compatible() returns 0 if the given node contains a
+ * 'compatible' property with the given string as one of its elements,
+ * it returns non-zero otherwise, or on error.
+ *
+ * returns:
+ *	0, if the node has a 'compatible' property listing the given string
+ *	1, if the node has a 'compatible' property, but it does not list
+ *		the given string
+ *	-FDT_ERR_NOTFOUND, if the given node has no 'compatible' property
+ *	-FDT_ERR_BADOFFSET, if nodeoffset does not refer to a BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE, standard meanings
+ */
+int fdt_node_check_compatible(const void *fdt, int nodeoffset,
+			      const char *compatible);
+
+/**
+ * fdt_node_offset_by_compatible - find nodes with a given 'compatible' value
+ * @fdt: pointer to the device tree blob
+ * @startoffset: only find nodes after this offset
+ * @compatible: 'compatible' string to match against
+ *
+ * fdt_node_offset_by_compatible() returns the offset of the first
+ * node after startoffset, which has a 'compatible' property which
+ * lists the given compatible string; or if startoffset is -1, the
+ * very first such node in the tree.
+ *
+ * To iterate through all nodes matching the criterion, the following
+ * idiom can be used:
+ *	offset = fdt_node_offset_by_compatible(fdt, -1, compatible);
+ *	while (offset != -FDT_ERR_NOTFOUND) {
+ *		... other code here ...
+ *		offset = fdt_node_offset_by_compatible(fdt, offset, compatible);
+ *	}
+ *
+ * Note the -1 in the first call to the function, if 0 is used here
+ * instead, the function will never locate the root node, even if it
+ * matches the criterion.
+ *
+ * returns:
+ *	structure block offset of the located node (>= 0, >startoffset),
+ *		 on success
+ *	-FDT_ERR_NOTFOUND, no node matching the criterion exists in the
+ *		tree after startoffset
+ *	-FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE, standard meanings
+ */
+int fdt_node_offset_by_compatible(const void *fdt, int startoffset,
+				  const char *compatible);
+
+/**
+ * fdt_stringlist_contains - check a string list property for a string
+ * @strlist: Property containing a list of strings to check
+ * @listlen: Length of property
+ * @str: String to search for
+ *
+ * This is a utility function provided for convenience. The list contains
+ * one or more strings, each terminated by \0, as is found in a device tree
+ * "compatible" property.
+ *
+ * @return: 1 if the string is found in the list, 0 not found, or invalid list
+ */
+int fdt_stringlist_contains(const char *strlist, int listlen, const char *str);
+
+/**********************************************************************/
+/* Write-in-place functions                                           */
+/**********************************************************************/
+
+/**
+ * fdt_setprop_inplace - change a property's value, but not its size
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to change
+ * @name: name of the property to change
+ * @val: pointer to data to replace the property value with
+ * @len: length of the property value
+ *
+ * fdt_setprop_inplace() replaces the value of a given property with
+ * the data in val, of length len.  This function cannot change the
+ * size of a property, and so will only work if len is equal to the
+ * current length of the property.
+ *
+ * This function will alter only the bytes in the blob which contain
+ * the given property value, and will not alter or move any other part
+ * of the tree.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOSPACE, if len is not equal to the property's current length
+ *	-FDT_ERR_NOTFOUND, node does not have the named property
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name,
+			const void *val, int len);
+
+/**
+ * fdt_setprop_inplace_u32 - change the value of a 32-bit integer property
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to change
+ * @name: name of the property to change
+ * @val: 32-bit integer value to replace the property with
+ *
+ * fdt_setprop_inplace_u32() replaces the value of a given property
+ * with the 32-bit integer value in val, converting val to big-endian
+ * if necessary.  This function cannot change the size of a property,
+ * and so will only work if the property already exists and has length
+ * 4.
+ *
+ * This function will alter only the bytes in the blob which contain
+ * the given property value, and will not alter or move any other part
+ * of the tree.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOSPACE, if the property's length is not equal to 4
+ *	-FDT_ERR_NOTFOUND, node does not have the named property
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+static inline int fdt_setprop_inplace_u32(void *fdt, int nodeoffset,
+					  const char *name, uint32_t val)
+{
+	fdt32_t tmp = cpu_to_fdt32(val);
+	return fdt_setprop_inplace(fdt, nodeoffset, name, &tmp, sizeof(tmp));
+}
+
+/**
+ * fdt_setprop_inplace_u64 - change the value of a 64-bit integer property
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to change
+ * @name: name of the property to change
+ * @val: 64-bit integer value to replace the property with
+ *
+ * fdt_setprop_inplace_u64() replaces the value of a given property
+ * with the 64-bit integer value in val, converting val to big-endian
+ * if necessary.  This function cannot change the size of a property,
+ * and so will only work if the property already exists and has length
+ * 8.
+ *
+ * This function will alter only the bytes in the blob which contain
+ * the given property value, and will not alter or move any other part
+ * of the tree.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOSPACE, if the property's length is not equal to 8
+ *	-FDT_ERR_NOTFOUND, node does not have the named property
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+static inline int fdt_setprop_inplace_u64(void *fdt, int nodeoffset,
+					  const char *name, uint64_t val)
+{
+	fdt64_t tmp = cpu_to_fdt64(val);
+	return fdt_setprop_inplace(fdt, nodeoffset, name, &tmp, sizeof(tmp));
+}
+
+/**
+ * fdt_setprop_inplace_cell - change the value of a single-cell property
+ *
+ * This is an alternative name for fdt_setprop_inplace_u32()
+ */
+static inline int fdt_setprop_inplace_cell(void *fdt, int nodeoffset,
+					   const char *name, uint32_t val)
+{
+	return fdt_setprop_inplace_u32(fdt, nodeoffset, name, val);
+}
+
+/**
+ * fdt_nop_property - replace a property with nop tags
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to nop
+ * @name: name of the property to nop
+ *
+ * fdt_nop_property() will replace a given property's representation
+ * in the blob with FDT_NOP tags, effectively removing it from the
+ * tree.
+ *
+ * This function will alter only the bytes in the blob which contain
+ * the property, and will not alter or move any other part of the
+ * tree.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOTFOUND, node does not have the named property
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+int fdt_nop_property(void *fdt, int nodeoffset, const char *name);
+
+/**
+ * fdt_nop_node - replace a node (subtree) with nop tags
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node to nop
+ *
+ * fdt_nop_node() will replace a given node's representation in the
+ * blob, including all its subnodes, if any, with FDT_NOP tags,
+ * effectively removing it from the tree.
+ *
+ * This function will alter only the bytes in the blob which contain
+ * the node and its properties and subnodes, and will not alter or
+ * move any other part of the tree.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+int fdt_nop_node(void *fdt, int nodeoffset);
+
+/**********************************************************************/
+/* Sequential write functions                                         */
+/**********************************************************************/
+
+int fdt_create(void *buf, int bufsize);
+int fdt_add_reservemap_entry(void *fdt, uint64_t addr, uint64_t size);
+int fdt_finish_reservemap(void *fdt);
+int fdt_begin_node(void *fdt, const char *name);
+int fdt_property(void *fdt, const char *name, const void *val, int len);
+static inline int fdt_property_u32(void *fdt, const char *name, uint32_t val)
+{
+	fdt32_t tmp = cpu_to_fdt32(val);
+	return fdt_property(fdt, name, &tmp, sizeof(tmp));
+}
+static inline int fdt_property_u64(void *fdt, const char *name, uint64_t val)
+{
+	fdt64_t tmp = cpu_to_fdt64(val);
+	return fdt_property(fdt, name, &tmp, sizeof(tmp));
+}
+static inline int fdt_property_cell(void *fdt, const char *name, uint32_t val)
+{
+	return fdt_property_u32(fdt, name, val);
+}
+#define fdt_property_string(fdt, name, str) \
+	fdt_property(fdt, name, str, strlen(str)+1)
+int fdt_end_node(void *fdt);
+int fdt_finish(void *fdt);
+
+/**********************************************************************/
+/* Read-write functions                                               */
+/**********************************************************************/
+
+int fdt_create_empty_tree(void *buf, int bufsize);
+int fdt_open_into(const void *fdt, void *buf, int bufsize);
+int fdt_pack(void *fdt);
+
+/**
+ * fdt_add_mem_rsv - add one memory reserve map entry
+ * @fdt: pointer to the device tree blob
+ * @address, @size: 64-bit values (native endian)
+ *
+ * Adds a reserve map entry to the given blob reserving a region at
+ * address address of length size.
+ *
+ * This function will insert data into the reserve map and will
+ * therefore change the indexes of some entries in the table.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOSPACE, there is insufficient free space in the blob to
+ *		contain the new reservation entry
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+int fdt_add_mem_rsv(void *fdt, uint64_t address, uint64_t size);
+
+/**
+ * fdt_del_mem_rsv - remove a memory reserve map entry
+ * @fdt: pointer to the device tree blob
+ * @n: entry to remove
+ *
+ * fdt_del_mem_rsv() removes the n-th memory reserve map entry from
+ * the blob.
+ *
+ * This function will delete data from the reservation table and will
+ * therefore change the indexes of some entries in the table.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOTFOUND, there is no entry of the given index (i.e. there
+ *		are less than n+1 reserve map entries)
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+int fdt_del_mem_rsv(void *fdt, int n);
+
+/**
+ * fdt_set_name - change the name of a given node
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: structure block offset of a node
+ * @name: name to give the node
+ *
+ * fdt_set_name() replaces the name (including unit address, if any)
+ * of the given node with the given string.  NOTE: this function can't
+ * efficiently check if the new name is unique amongst the given
+ * node's siblings; results are undefined if this function is invoked
+ * with a name equal to one of the given node's siblings.
+ *
+ * This function may insert or delete data from the blob, and will
+ * therefore change the offsets of some existing nodes.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOSPACE, there is insufficient free space in the blob
+ *		to contain the new name
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE, standard meanings
+ */
+int fdt_set_name(void *fdt, int nodeoffset, const char *name);
+
+/**
+ * fdt_setprop - create or change a property
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to change
+ * @name: name of the property to change
+ * @val: pointer to data to set the property value to
+ * @len: length of the property value
+ *
+ * fdt_setprop() sets the value of the named property in the given
+ * node to the given value and length, creating the property if it
+ * does not already exist.
+ *
+ * This function may insert or delete data from the blob, and will
+ * therefore change the offsets of some existing nodes.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOSPACE, there is insufficient free space in the blob to
+ *		contain the new property value
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+int fdt_setprop(void *fdt, int nodeoffset, const char *name,
+		const void *val, int len);
+
+/**
+ * fdt_setprop_u32 - set a property to a 32-bit integer
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to change
+ * @name: name of the property to change
+ * @val: 32-bit integer value for the property (native endian)
+ *
+ * fdt_setprop_u32() sets the value of the named property in the given
+ * node to the given 32-bit integer value (converting to big-endian if
+ * necessary), or creates a new property with that value if it does
+ * not already exist.
+ *
+ * This function may insert or delete data from the blob, and will
+ * therefore change the offsets of some existing nodes.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOSPACE, there is insufficient free space in the blob to
+ *		contain the new property value
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+static inline int fdt_setprop_u32(void *fdt, int nodeoffset, const char *name,
+				  uint32_t val)
+{
+	fdt32_t tmp = cpu_to_fdt32(val);
+	return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp));
+}
+
+/**
+ * fdt_setprop_u64 - set a property to a 64-bit integer
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to change
+ * @name: name of the property to change
+ * @val: 64-bit integer value for the property (native endian)
+ *
+ * fdt_setprop_u64() sets the value of the named property in the given
+ * node to the given 64-bit integer value (converting to big-endian if
+ * necessary), or creates a new property with that value if it does
+ * not already exist.
+ *
+ * This function may insert or delete data from the blob, and will
+ * therefore change the offsets of some existing nodes.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOSPACE, there is insufficient free space in the blob to
+ *		contain the new property value
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+static inline int fdt_setprop_u64(void *fdt, int nodeoffset, const char *name,
+				  uint64_t val)
+{
+	fdt64_t tmp = cpu_to_fdt64(val);
+	return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp));
+}
+
+/**
+ * fdt_setprop_cell - set a property to a single cell value
+ *
+ * This is an alternative name for fdt_setprop_u32()
+ */
+static inline int fdt_setprop_cell(void *fdt, int nodeoffset, const char *name,
+				   uint32_t val)
+{
+	return fdt_setprop_u32(fdt, nodeoffset, name, val);
+}
+
+/**
+ * fdt_setprop_string - set a property to a string value
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to change
+ * @name: name of the property to change
+ * @str: string value for the property
+ *
+ * fdt_setprop_string() sets the value of the named property in the
+ * given node to the given string value (using the length of the
+ * string to determine the new length of the property), or creates a
+ * new property with that value if it does not already exist.
+ *
+ * This function may insert or delete data from the blob, and will
+ * therefore change the offsets of some existing nodes.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOSPACE, there is insufficient free space in the blob to
+ *		contain the new property value
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+#define fdt_setprop_string(fdt, nodeoffset, name, str) \
+	fdt_setprop((fdt), (nodeoffset), (name), (str), strlen(str)+1)
+
+/**
+ * fdt_appendprop - append to or create a property
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to change
+ * @name: name of the property to append to
+ * @val: pointer to data to append to the property value
+ * @len: length of the data to append to the property value
+ *
+ * fdt_appendprop() appends the value to the named property in the
+ * given node, creating the property if it does not already exist.
+ *
+ * This function may insert data into the blob, and will therefore
+ * change the offsets of some existing nodes.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOSPACE, there is insufficient free space in the blob to
+ *		contain the new property value
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+int fdt_appendprop(void *fdt, int nodeoffset, const char *name,
+		   const void *val, int len);
+
+/**
+ * fdt_appendprop_u32 - append a 32-bit integer value to a property
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to change
+ * @name: name of the property to change
+ * @val: 32-bit integer value to append to the property (native endian)
+ *
+ * fdt_appendprop_u32() appends the given 32-bit integer value
+ * (converting to big-endian if necessary) to the value of the named
+ * property in the given node, or creates a new property with that
+ * value if it does not already exist.
+ *
+ * This function may insert data into the blob, and will therefore
+ * change the offsets of some existing nodes.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOSPACE, there is insufficient free space in the blob to
+ *		contain the new property value
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+static inline int fdt_appendprop_u32(void *fdt, int nodeoffset,
+				     const char *name, uint32_t val)
+{
+	fdt32_t tmp = cpu_to_fdt32(val);
+	return fdt_appendprop(fdt, nodeoffset, name, &tmp, sizeof(tmp));
+}
+
+/**
+ * fdt_appendprop_u64 - append a 64-bit integer value to a property
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to change
+ * @name: name of the property to change
+ * @val: 64-bit integer value to append to the property (native endian)
+ *
+ * fdt_appendprop_u64() appends the given 64-bit integer value
+ * (converting to big-endian if necessary) to the value of the named
+ * property in the given node, or creates a new property with that
+ * value if it does not already exist.
+ *
+ * This function may insert data into the blob, and will therefore
+ * change the offsets of some existing nodes.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOSPACE, there is insufficient free space in the blob to
+ *		contain the new property value
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+static inline int fdt_appendprop_u64(void *fdt, int nodeoffset,
+				     const char *name, uint64_t val)
+{
+	fdt64_t tmp = cpu_to_fdt64(val);
+	return fdt_appendprop(fdt, nodeoffset, name, &tmp, sizeof(tmp));
+}
+
+/**
+ * fdt_appendprop_cell - append a single cell value to a property
+ *
+ * This is an alternative name for fdt_appendprop_u32()
+ */
+static inline int fdt_appendprop_cell(void *fdt, int nodeoffset,
+				      const char *name, uint32_t val)
+{
+	return fdt_appendprop_u32(fdt, nodeoffset, name, val);
+}
+
+/**
+ * fdt_appendprop_string - append a string to a property
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to change
+ * @name: name of the property to change
+ * @str: string value to append to the property
+ *
+ * fdt_appendprop_string() appends the given string to the value of
+ * the named property in the given node, or creates a new property
+ * with that value if it does not already exist.
+ *
+ * This function may insert data into the blob, and will therefore
+ * change the offsets of some existing nodes.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOSPACE, there is insufficient free space in the blob to
+ *		contain the new property value
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+#define fdt_appendprop_string(fdt, nodeoffset, name, str) \
+	fdt_appendprop((fdt), (nodeoffset), (name), (str), strlen(str)+1)
+
+/**
+ * fdt_delprop - delete a property
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to nop
+ * @name: name of the property to nop
+ *
+ * fdt_del_property() will delete the given property.
+ *
+ * This function will delete data from the blob, and will therefore
+ * change the offsets of some existing nodes.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOTFOUND, node does not have the named property
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+int fdt_delprop(void *fdt, int nodeoffset, const char *name);
+
+/**
+ * fdt_add_subnode_namelen - creates a new node based on substring
+ * @fdt: pointer to the device tree blob
+ * @parentoffset: structure block offset of a node
+ * @name: name of the subnode to locate
+ * @namelen: number of characters of name to consider
+ *
+ * Identical to fdt_add_subnode(), but use only the first namelen
+ * characters of name as the name of the new node.  This is useful for
+ * creating subnodes based on a portion of a larger string, such as a
+ * full path.
+ */
+int fdt_add_subnode_namelen(void *fdt, int parentoffset,
+			    const char *name, int namelen);
+
+/**
+ * fdt_add_subnode - creates a new node
+ * @fdt: pointer to the device tree blob
+ * @parentoffset: structure block offset of a node
+ * @name: name of the subnode to locate
+ *
+ * fdt_add_subnode() creates a new node as a subnode of the node at
+ * structure block offset parentoffset, with the given name (which
+ * should include the unit address, if any).
+ *
+ * This function will insert data into the blob, and will therefore
+ * change the offsets of some existing nodes.
+
+ * returns:
+ *	structure block offset of the created nodeequested subnode (>=0), on success
+ *	-FDT_ERR_NOTFOUND, if the requested subnode does not exist
+ *	-FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE tag
+ *	-FDT_ERR_EXISTS, if the node at parentoffset already has a subnode of
+ *		the given name
+ *	-FDT_ERR_NOSPACE, if there is insufficient free space in the
+ *		blob to contain the new node
+ *	-FDT_ERR_NOSPACE
+ *	-FDT_ERR_BADLAYOUT
+ *      -FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings.
+ */
+int fdt_add_subnode(void *fdt, int parentoffset, const char *name);
+
+/**
+ * fdt_del_node - delete a node (subtree)
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node to nop
+ *
+ * fdt_del_node() will remove the given node, including all its
+ * subnodes if any, from the blob.
+ *
+ * This function will delete data from the blob, and will therefore
+ * change the offsets of some existing nodes.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+int fdt_del_node(void *fdt, int nodeoffset);
+
+/**********************************************************************/
+/* Debugging / informational functions                                */
+/**********************************************************************/
+
+const char *fdt_strerror(int errval);
+
+struct fdt_region {
+	int offset;
+	int size;
+};
+
+/**
+ * fdt_find_regions() - find regions in device tree
+ *
+ * Given a list of nodes to include and properties to exclude, find
+ * the regions of the device tree which describe those included parts.
+ *
+ * The intent is to get a list of regions which will be invariant provided
+ * those parts are invariant. For example, if you request a list of regions
+ * for all nodes but exclude the property "data", then you will get the
+ * same region contents regardless of any change to "data" properties.
+ *
+ * This function can be used to produce a byte-stream to send to a hashing
+ * function to verify that critical parts of the FDT have not changed.
+ *
+ * Nodes which are given in 'inc' are included in the region list, as
+ * are the names of the immediate subnodes nodes (but not the properties
+ * or subnodes of those subnodes).
+ *
+ * For eaxample "/" means to include the root node, all root properties
+ * and the FDT_BEGIN_NODE and FDT_END_NODE of all subnodes of /. The latter
+ * ensures that we capture the names of the subnodes. In a hashing situation
+ * it prevents the root node from changing at all Any change to non-excluded
+ * properties, names of subnodes or number of subnodes would be detected.
+ *
+ * When used with FITs this provides the ability to hash and sign parts of
+ * the FIT based on different configurations in the FIT. Then it is
+ * impossible to change anything about that configuration (include images
+ * attached to the configuration), but it may be possible to add new
+ * configurations, new images or new signatures within the existing
+ * framework.
+ *
+ * Adding new properties to a device tree may result in the string table
+ * being extended (if the new property names are different from those
+ * already added). This function can optionally include a region for
+ * the string table so that this can be part of the hash too.
+ *
+ * The device tree header is not included in the list.
+ *
+ * @fdt:	Device tree to check
+ * @inc:	List of node paths to included
+ * @inc_count:	Number of node paths in list
+ * @exc_prop:	List of properties names to exclude
+ * @exc_prop_count:	Number of properties in exclude list
+ * @region:	Returns list of regions
+ * @max_region:	Maximum length of region list
+ * @path:	Pointer to a temporary string for the function to use for
+ *		building path names
+ * @path_len:	Length of path, must be large enough to hold the longest
+ *		path in the tree
+ * @add_string_tab:	1 to add a region for the string table
+ * @return number of regions in list. If this is >max_regions then the
+ * region array was exhausted. You should increase max_regions and try
+ * the call again.
+ */
+int fdt_find_regions(const void *fdt, char * const inc[], int inc_count,
+		     char * const exc_prop[], int exc_prop_count,
+		     struct fdt_region region[], int max_regions,
+		     char *path, int path_len, int add_string_tab);
+
+#endif /* _LIBFDT_H */
diff --git a/qemu/roms/u-boot/include/libfdt_env.h b/qemu/roms/u-boot/include/libfdt_env.h
new file mode 100644
index 000000000..273b5d30f
--- /dev/null
+++ b/qemu/roms/u-boot/include/libfdt_env.h
@@ -0,0 +1,29 @@
+/*
+ * libfdt - Flat Device Tree manipulation (build/run environment adaptation)
+ * Copyright (C) 2007 Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com
+ * Original version written by David Gibson, IBM Corporation.
+ *
+ * SPDX-License-Identifier:	LGPL-2.1+
+ */
+
+#ifndef _LIBFDT_ENV_H
+#define _LIBFDT_ENV_H
+
+#include "compiler.h"
+#include "linux/types.h"
+
+extern struct fdt_header *working_fdt;  /* Pointer to the working fdt */
+
+typedef __be16 fdt16_t;
+typedef __be32 fdt32_t;
+typedef __be64 fdt64_t;
+
+#define fdt32_to_cpu(x)		be32_to_cpu(x)
+#define cpu_to_fdt32(x)		cpu_to_be32(x)
+#define fdt64_to_cpu(x)		be64_to_cpu(x)
+#define cpu_to_fdt64(x)		cpu_to_be64(x)
+
+/* adding a ramdisk needs 0x44 bytes in version 2008.10 */
+#define FDT_RAMDISK_OVERHEAD	0x80
+
+#endif /* _LIBFDT_ENV_H */
diff --git a/qemu/roms/u-boot/include/libtizen.h b/qemu/roms/u-boot/include/libtizen.h
new file mode 100644
index 000000000..6490fb52b
--- /dev/null
+++ b/qemu/roms/u-boot/include/libtizen.h
@@ -0,0 +1,15 @@
+/*
+ * (C) Copyright 2012 Samsung Electronics
+ * Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _LIBTIZEN_H_
+#define _LIBTIZEN_H_
+
+#define HD_RESOLUTION	0
+
+void get_tizen_logo_info(vidinfo_t *vid);
+
+#endif	/* _LIBTIZEN_H_ */
diff --git a/qemu/roms/u-boot/include/linker_lists.h b/qemu/roms/u-boot/include/linker_lists.h
new file mode 100644
index 000000000..557e6273a
--- /dev/null
+++ b/qemu/roms/u-boot/include/linker_lists.h
@@ -0,0 +1,288 @@
+/*
+ * include/linker_lists.h
+ *
+ * Implementation of linker-generated arrays
+ *
+ * Copyright (C) 2012 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __LINKER_LISTS_H__
+#define __LINKER_LISTS_H__
+
+/*
+ * There is no use in including this from ASM files, but that happens
+ * anyway, e.g. PPC kgdb.S includes command.h which incluse us.
+ * So just don't define anything when included from ASM.
+ */
+
+#if !defined(__ASSEMBLY__)
+
+/**
+ * A linker list is constructed by grouping together linker input
+ * sections, each containning one entry of the list. Each input section
+ * contains a constant initialized variable which holds the entry's
+ * content. Linker list input sections are constructed from the list
+ * and entry names, plus a prefix which allows grouping all lists
+ * together. Assuming _list and _entry are the list and entry names,
+ * then the corresponding input section name is
+ *
+ *   _u_boot_list + _2_ + @_list + _2_ + @_entry
+ *
+ * and the C variable name is
+ *
+ *   .u_boot_list_ + 2_ + @_list + _2_ + @_entry
+ *
+ * This ensures uniqueness for both input section and C variable name.
+ *
+ * Note that the names differ only in the first character, "." for the
+ * setion and "_" for the variable, so that the linker cannot confuse
+ * section and symbol names. From now on, both names will be referred
+ * to as
+ *
+ *   %u_boot_list_ + 2_ + @_list + _2_ + @_entry
+ *
+ * Entry variables need never be referred to directly.
+ *
+ * The naming scheme for input sections allows grouping all linker lists
+ * into a single linker output section and grouping all entries for a
+ * single list.
+ *
+ * Note the two '_2_' constant components in the names: their presence
+ * allows putting a start and end symbols around a list, by mapping
+ * these symbols to sections names with components "1" (before) and
+ * "3" (after) instead of "2" (within).
+ * Start and end symbols for a list can generally be defined as
+ *
+ *   %u_boot_list_2_ + @_list + _1_...
+ *   %u_boot_list_2_ + @_list + _3_...
+ *
+ * Start and end symbols for the whole of the linker lists area can be
+ * defined as
+ *
+ *   %u_boot_list_1_...
+ *   %u_boot_list_3_...
+ *
+ * Here is an example of the sorted sections which result from a list
+ * "array" made up of three entries : "first", "second" and "third",
+ * iterated at least once.
+ *
+ *   .u_boot_list_2_array_1
+ *   .u_boot_list_2_array_2_first
+ *   .u_boot_list_2_array_2_second
+ *   .u_boot_list_2_array_2_third
+ *   .u_boot_list_2_array_3
+ *
+ * If lists must be divided into sublists (e.g. for iterating only on
+ * part of a list), one can simply give the list a name of the form
+ * 'outer_2_inner', where 'outer' is the global list name and 'inner'
+ * is the sub-list name. Iterators for the whole list should use the
+ * global list name ("outer"); iterators for only a sub-list should use
+ * the full sub-list name ("outer_2_inner").
+ *
+ *  Here is an example of the sections generated from a global list
+ * named "drivers", two sub-lists named "i2c" and "pci", and iterators
+ * defined for the whole list and each sub-list:
+ *
+ *   %u_boot_list_2_drivers_1
+ *   %u_boot_list_2_drivers_2_i2c_1
+ *   %u_boot_list_2_drivers_2_i2c_2_first
+ *   %u_boot_list_2_drivers_2_i2c_2_first
+ *   %u_boot_list_2_drivers_2_i2c_2_second
+ *   %u_boot_list_2_drivers_2_i2c_2_third
+ *   %u_boot_list_2_drivers_2_i2c_3
+ *   %u_boot_list_2_drivers_2_pci_1
+ *   %u_boot_list_2_drivers_2_pci_2_first
+ *   %u_boot_list_2_drivers_2_pci_2_second
+ *   %u_boot_list_2_drivers_2_pci_2_third
+ *   %u_boot_list_2_drivers_2_pci_3
+ *   %u_boot_list_2_drivers_3
+ */
+
+/**
+ * ll_entry_declare() - Declare linker-generated array entry
+ * @_type:	Data type of the entry
+ * @_name:	Name of the entry
+ * @_list:	name of the list. Should contain only characters allowed
+ *		in a C variable name!
+ *
+ * This macro declares a variable that is placed into a linker-generated
+ * array. This is a basic building block for more advanced use of linker-
+ * generated arrays. The user is expected to build their own macro wrapper
+ * around this one.
+ *
+ * A variable declared using this macro must be compile-time initialized.
+ *
+ * Special precaution must be made when using this macro:
+ *
+ * 1) The _type must not contain the "static" keyword, otherwise the
+ *    entry is generated and can be iterated but is listed in the map
+ *    file and cannot be retrieved by name.
+ *
+ * 2) In case a section is declared that contains some array elements AND
+ *    a subsection of this section is declared and contains some elements,
+ *    it is imperative that the elements are of the same type.
+ *
+ * 4) In case an outer section is declared that contains some array elements
+ *    AND an inner subsection of this section is declared and contains some
+ *    elements, then when traversing the outer section, even the elements of
+ *    the inner sections are present in the array.
+ *
+ * Example:
+ * ll_entry_declare(struct my_sub_cmd, my_sub_cmd, cmd_sub, cmd.sub) = {
+ *         .x = 3,
+ *         .y = 4,
+ * };
+ */
+#define ll_entry_declare(_type, _name, _list)				\
+	_type _u_boot_list_2_##_list##_2_##_name __aligned(4)		\
+			__attribute__((unused,				\
+			section(".u_boot_list_2_"#_list"_2_"#_name)))
+
+/**
+ * We need a 0-byte-size type for iterator symbols, and the compiler
+ * does not allow defining objects of C type 'void'. Using an empty
+ * struct is allowed by the compiler, but causes gcc versions 4.4 and
+ * below to complain about aliasing. Therefore we use the next best
+ * thing: zero-sized arrays, which are both 0-byte-size and exempt from
+ * aliasing warnings.
+ */
+
+/**
+ * ll_entry_start() - Point to first entry of linker-generated array
+ * @_type:	Data type of the entry
+ * @_list:	Name of the list in which this entry is placed
+ *
+ * This function returns (_type *) pointer to the very first entry of a
+ * linker-generated array placed into subsection of .u_boot_list section
+ * specified by _list argument.
+ *
+ * Since this macro defines an array start symbol, its leftmost index
+ * must be 2 and its rightmost index must be 1.
+ *
+ * Example:
+ * struct my_sub_cmd *msc = ll_entry_start(struct my_sub_cmd, cmd_sub);
+ */
+#define ll_entry_start(_type, _list)					\
+({									\
+	static char start[0] __aligned(4) __attribute__((unused,	\
+		section(".u_boot_list_2_"#_list"_1")));			\
+	(_type *)&start;						\
+})
+
+/**
+ * ll_entry_end() - Point after last entry of linker-generated array
+ * @_type:	Data type of the entry
+ * @_list:	Name of the list in which this entry is placed
+ *		(with underscores instead of dots)
+ *
+ * This function returns (_type *) pointer after the very last entry of
+ * a linker-generated array placed into subsection of .u_boot_list
+ * section specified by _list argument.
+ *
+ * Since this macro defines an array end symbol, its leftmost index
+ * must be 2 and its rightmost index must be 3.
+ *
+ * Example:
+ * struct my_sub_cmd *msc = ll_entry_end(struct my_sub_cmd, cmd_sub);
+ */
+#define ll_entry_end(_type, _list)					\
+({									\
+	static char end[0] __aligned(4) __attribute__((unused,	\
+		section(".u_boot_list_2_"#_list"_3")));			\
+	(_type *)&end;							\
+})
+/**
+ * ll_entry_count() - Return the number of elements in linker-generated array
+ * @_type:	Data type of the entry
+ * @_list:	Name of the list of which the number of elements is computed
+ *
+ * This function returns the number of elements of a linker-generated array
+ * placed into subsection of .u_boot_list section specified by _list
+ * argument. The result is of an unsigned int type.
+ *
+ * Example:
+ * int i;
+ * const unsigned int count = ll_entry_count(struct my_sub_cmd, cmd_sub);
+ * struct my_sub_cmd *msc = ll_entry_start(struct my_sub_cmd, cmd_sub);
+ * for (i = 0; i < count; i++, msc++)
+ *         printf("Entry %i, x=%i y=%i\n", i, msc->x, msc->y);
+ */
+#define ll_entry_count(_type, _list)					\
+	({								\
+		_type *start = ll_entry_start(_type, _list);		\
+		_type *end = ll_entry_end(_type, _list);		\
+		unsigned int _ll_result = end - start;			\
+		_ll_result;						\
+	})
+
+/**
+ * ll_entry_get() - Retrieve entry from linker-generated array by name
+ * @_type:	Data type of the entry
+ * @_name:	Name of the entry
+ * @_list:	Name of the list in which this entry is placed
+ *
+ * This function returns a pointer to a particular entry in LG-array
+ * identified by the subsection of u_boot_list where the entry resides
+ * and it's name.
+ *
+ * Example:
+ * ll_entry_declare(struct my_sub_cmd, my_sub_cmd, cmd_sub) = {
+ *         .x = 3,
+ *         .y = 4,
+ * };
+ * ...
+ * struct my_sub_cmd *c = ll_entry_get(struct my_sub_cmd, my_sub_cmd, cmd_sub);
+ */
+#define ll_entry_get(_type, _name, _list)				\
+	({								\
+		extern _type _u_boot_list_2_##_list##_2_##_name;	\
+		_type *_ll_result =					\
+			&_u_boot_list_2_##_list##_2_##_name;	\
+		_ll_result;						\
+	})
+
+/**
+ * ll_start() - Point to first entry of first linker-generated array
+ * @_type:	Data type of the entry
+ *
+ * This function returns (_type *) pointer to the very first entry of
+ * the very first linker-generated array.
+ *
+ * Since this macro defines the start of the linker-generated arrays,
+ * its leftmost index must be 1.
+ *
+ * Example:
+ * struct my_sub_cmd *msc = ll_start(struct my_sub_cmd);
+ */
+#define ll_start(_type)							\
+({									\
+	static char start[0] __aligned(4) __attribute__((unused,	\
+		section(".u_boot_list_1")));				\
+	(_type *)&start;						\
+})
+
+/**
+ * ll_entry_end() - Point after last entry of last linker-generated array
+ * @_type:	Data type of the entry
+ *
+ * This function returns (_type *) pointer after the very last entry of
+ * the very last linker-generated array.
+ *
+ * Since this macro defines the end of the linker-generated arrays,
+ * its leftmost index must be 3.
+ *
+ * Example:
+ * struct my_sub_cmd *msc = ll_end(struct my_sub_cmd);
+ */
+#define ll_end(_type)							\
+({									\
+	static char end[0] __aligned(4) __attribute__((unused,	\
+		section(".u_boot_list_3")));				\
+	(_type *)&end;							\
+})
+
+#endif /* __ASSEMBLY__ */
+
+#endif	/* __LINKER_LISTS_H__ */
diff --git a/qemu/roms/u-boot/include/linux/apm_bios.h b/qemu/roms/u-boot/include/linux/apm_bios.h
new file mode 100644
index 000000000..d18ca719f
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/apm_bios.h
@@ -0,0 +1,212 @@
+#ifndef _LINUX_APM_H
+#define _LINUX_APM_H
+
+/*
+ * Include file for the interface to an APM BIOS
+ * Copyright 1994-2001 Stephen Rothwell (sfr@canb.auug.org.au)
+ *
+  * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/types.h>
+
+typedef unsigned short	apm_event_t;
+typedef unsigned short	apm_eventinfo_t;
+
+struct apm_bios_info {
+	__u16	version;
+	__u16	cseg;
+	__u32	offset;
+	__u16	cseg_16;
+	__u16	dseg;
+	__u16	flags;
+	__u16	cseg_len;
+	__u16	cseg_16_len;
+	__u16	dseg_len;
+};
+
+#ifdef __KERNEL__
+
+#define APM_CS		(GDT_ENTRY_APMBIOS_BASE * 8)
+#define APM_CS_16	(APM_CS + 8)
+#define APM_DS		(APM_CS_16 + 8)
+
+/* Results of APM Installation Check */
+#define APM_16_BIT_SUPPORT	0x0001
+#define APM_32_BIT_SUPPORT	0x0002
+#define APM_IDLE_SLOWS_CLOCK	0x0004
+#define APM_BIOS_DISABLED      	0x0008
+#define APM_BIOS_DISENGAGED     0x0010
+
+/*
+ * Data for APM that is persistent across module unload/load
+ */
+struct apm_info {
+	struct apm_bios_info	bios;
+	unsigned short		connection_version;
+	int			get_power_status_broken;
+	int			get_power_status_swabinminutes;
+	int			allow_ints;
+	int			forbid_idle;
+	int			realmode_power_off;
+	int			disabled;
+};
+
+/*
+ * The APM function codes
+ */
+#define	APM_FUNC_INST_CHECK	0x5300
+#define	APM_FUNC_REAL_CONN	0x5301
+#define	APM_FUNC_16BIT_CONN	0x5302
+#define	APM_FUNC_32BIT_CONN	0x5303
+#define	APM_FUNC_DISCONN	0x5304
+#define	APM_FUNC_IDLE		0x5305
+#define	APM_FUNC_BUSY		0x5306
+#define	APM_FUNC_SET_STATE	0x5307
+#define	APM_FUNC_ENABLE_PM	0x5308
+#define	APM_FUNC_RESTORE_BIOS	0x5309
+#define	APM_FUNC_GET_STATUS	0x530a
+#define	APM_FUNC_GET_EVENT	0x530b
+#define	APM_FUNC_GET_STATE	0x530c
+#define	APM_FUNC_ENABLE_DEV_PM	0x530d
+#define	APM_FUNC_VERSION	0x530e
+#define	APM_FUNC_ENGAGE_PM	0x530f
+#define	APM_FUNC_GET_CAP	0x5310
+#define	APM_FUNC_RESUME_TIMER	0x5311
+#define	APM_FUNC_RESUME_ON_RING	0x5312
+#define	APM_FUNC_TIMER		0x5313
+
+/*
+ * Function code for APM_FUNC_RESUME_TIMER
+ */
+#define	APM_FUNC_DISABLE_TIMER	0
+#define	APM_FUNC_GET_TIMER	1
+#define	APM_FUNC_SET_TIMER	2
+
+/*
+ * Function code for APM_FUNC_RESUME_ON_RING
+ */
+#define	APM_FUNC_DISABLE_RING	0
+#define	APM_FUNC_ENABLE_RING	1
+#define	APM_FUNC_GET_RING	2
+
+/*
+ * Function code for APM_FUNC_TIMER_STATUS
+ */
+#define	APM_FUNC_TIMER_DISABLE	0
+#define	APM_FUNC_TIMER_ENABLE	1
+#define	APM_FUNC_TIMER_GET	2
+
+/*
+ * in arch/i386/kernel/setup.c
+ */
+extern struct apm_info	apm_info;
+
+#endif	/* __KERNEL__ */
+
+/*
+ * Power states
+ */
+#define APM_STATE_READY		0x0000
+#define APM_STATE_STANDBY	0x0001
+#define APM_STATE_SUSPEND	0x0002
+#define APM_STATE_OFF		0x0003
+#define APM_STATE_BUSY		0x0004
+#define APM_STATE_REJECT	0x0005
+#define APM_STATE_OEM_SYS	0x0020
+#define APM_STATE_OEM_DEV	0x0040
+
+#define APM_STATE_DISABLE	0x0000
+#define APM_STATE_ENABLE	0x0001
+
+#define APM_STATE_DISENGAGE	0x0000
+#define APM_STATE_ENGAGE	0x0001
+
+/*
+ * Events (results of Get PM Event)
+ */
+#define APM_SYS_STANDBY		0x0001
+#define APM_SYS_SUSPEND		0x0002
+#define APM_NORMAL_RESUME	0x0003
+#define APM_CRITICAL_RESUME	0x0004
+#define APM_LOW_BATTERY		0x0005
+#define APM_POWER_STATUS_CHANGE	0x0006
+#define APM_UPDATE_TIME		0x0007
+#define APM_CRITICAL_SUSPEND	0x0008
+#define APM_USER_STANDBY	0x0009
+#define APM_USER_SUSPEND	0x000a
+#define APM_STANDBY_RESUME	0x000b
+#define APM_CAPABILITY_CHANGE	0x000c
+
+/*
+ * Error codes
+ */
+#define APM_SUCCESS		0x00
+#define APM_DISABLED		0x01
+#define APM_CONNECTED		0x02
+#define APM_NOT_CONNECTED	0x03
+#define APM_16_CONNECTED	0x05
+#define APM_16_UNSUPPORTED	0x06
+#define APM_32_CONNECTED	0x07
+#define APM_32_UNSUPPORTED	0x08
+#define APM_BAD_DEVICE		0x09
+#define APM_BAD_PARAM		0x0a
+#define APM_NOT_ENGAGED		0x0b
+#define APM_BAD_FUNCTION	0x0c
+#define APM_RESUME_DISABLED	0x0d
+#define APM_NO_ERROR		0x53
+#define APM_BAD_STATE		0x60
+#define APM_NO_EVENTS		0x80
+#define APM_NOT_PRESENT		0x86
+
+/*
+ * APM Device IDs
+ */
+#define APM_DEVICE_BIOS		0x0000
+#define APM_DEVICE_ALL		0x0001
+#define APM_DEVICE_DISPLAY	0x0100
+#define APM_DEVICE_STORAGE	0x0200
+#define APM_DEVICE_PARALLEL	0x0300
+#define APM_DEVICE_SERIAL	0x0400
+#define APM_DEVICE_NETWORK	0x0500
+#define APM_DEVICE_PCMCIA	0x0600
+#define APM_DEVICE_BATTERY	0x8000
+#define APM_DEVICE_OEM		0xe000
+#define APM_DEVICE_OLD_ALL	0xffff
+#define APM_DEVICE_CLASS	0x00ff
+#define APM_DEVICE_MASK		0xff00
+
+#ifdef __KERNEL__
+/*
+ * This is the "All Devices" ID communicated to the BIOS
+ */
+#define APM_DEVICE_BALL		((apm_info.connection_version > 0x0100) ? \
+				 APM_DEVICE_ALL : APM_DEVICE_OLD_ALL)
+#endif
+
+/*
+ * Battery status
+ */
+#define APM_MAX_BATTERIES	2
+
+/*
+ * APM defined capability bit flags
+ */
+#define APM_CAP_GLOBAL_STANDBY		0x0001
+#define APM_CAP_GLOBAL_SUSPEND		0x0002
+#define APM_CAP_RESUME_STANDBY_TIMER	0x0004 /* Timer resume from standby */
+#define APM_CAP_RESUME_SUSPEND_TIMER	0x0008 /* Timer resume from suspend */
+#define APM_CAP_RESUME_STANDBY_RING	0x0010 /* Resume on Ring fr standby */
+#define APM_CAP_RESUME_SUSPEND_RING	0x0020 /* Resume on Ring fr suspend */
+#define APM_CAP_RESUME_STANDBY_PCMCIA	0x0040 /* Resume on PCMCIA Ring	*/
+#define APM_CAP_RESUME_SUSPEND_PCMCIA	0x0080 /* Resume on PCMCIA Ring	*/
+
+/*
+ * ioctl operations
+ */
+#include <linux/ioctl.h>
+
+#define APM_IOC_STANDBY		_IO('A', 1)
+#define APM_IOC_SUSPEND		_IO('A', 2)
+
+#endif	/* LINUX_APM_H */
diff --git a/qemu/roms/u-boot/include/linux/bch.h b/qemu/roms/u-boot/include/linux/bch.h
new file mode 100644
index 000000000..295b4ef15
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/bch.h
@@ -0,0 +1,79 @@
+/*
+ * Generic binary BCH encoding/decoding library
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 51
+ * Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Copyright © 2011 Parrot S.A.
+ *
+ * Author: Ivan Djelic <ivan.djelic@parrot.com>
+ *
+ * Description:
+ *
+ * This library provides runtime configurable encoding/decoding of binary
+ * Bose-Chaudhuri-Hocquenghem (BCH) codes.
+*/
+#ifndef _BCH_H
+#define _BCH_H
+
+#include <linux/types.h>
+
+/**
+ * struct bch_control - BCH control structure
+ * @m:          Galois field order
+ * @n:          maximum codeword size in bits (= 2^m-1)
+ * @t:          error correction capability in bits
+ * @ecc_bits:   ecc exact size in bits, i.e. generator polynomial degree (<=m*t)
+ * @ecc_bytes:  ecc max size (m*t bits) in bytes
+ * @a_pow_tab:  Galois field GF(2^m) exponentiation lookup table
+ * @a_log_tab:  Galois field GF(2^m) log lookup table
+ * @mod8_tab:   remainder generator polynomial lookup tables
+ * @ecc_buf:    ecc parity words buffer
+ * @ecc_buf2:   ecc parity words buffer
+ * @xi_tab:     GF(2^m) base for solving degree 2 polynomial roots
+ * @syn:        syndrome buffer
+ * @cache:      log-based polynomial representation buffer
+ * @elp:        error locator polynomial
+ * @poly_2t:    temporary polynomials of degree 2t
+ */
+struct bch_control {
+	unsigned int    m;
+	unsigned int    n;
+	unsigned int    t;
+	unsigned int    ecc_bits;
+	unsigned int    ecc_bytes;
+/* private: */
+	uint16_t       *a_pow_tab;
+	uint16_t       *a_log_tab;
+	uint32_t       *mod8_tab;
+	uint32_t       *ecc_buf;
+	uint32_t       *ecc_buf2;
+	unsigned int   *xi_tab;
+	unsigned int   *syn;
+	int            *cache;
+	struct gf_poly *elp;
+	struct gf_poly *poly_2t[4];
+};
+
+struct bch_control *init_bch(int m, int t, unsigned int prim_poly);
+
+void free_bch(struct bch_control *bch);
+
+void encode_bch(struct bch_control *bch, const uint8_t *data,
+		unsigned int len, uint8_t *ecc);
+
+int decode_bch(struct bch_control *bch, const uint8_t *data, unsigned int len,
+	       const uint8_t *recv_ecc, const uint8_t *calc_ecc,
+	       const unsigned int *syn, unsigned int *errloc);
+
+#endif /* _BCH_H */
diff --git a/qemu/roms/u-boot/include/linux/bitops.h b/qemu/roms/u-boot/include/linux/bitops.h
new file mode 100644
index 000000000..e72431029
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/bitops.h
@@ -0,0 +1,155 @@
+#ifndef _LINUX_BITOPS_H
+#define _LINUX_BITOPS_H
+
+#include <asm/types.h>
+
+/*
+ * ffs: find first bit set. This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ */
+
+static inline int generic_ffs(int x)
+{
+	int r = 1;
+
+	if (!x)
+		return 0;
+	if (!(x & 0xffff)) {
+		x >>= 16;
+		r += 16;
+	}
+	if (!(x & 0xff)) {
+		x >>= 8;
+		r += 8;
+	}
+	if (!(x & 0xf)) {
+		x >>= 4;
+		r += 4;
+	}
+	if (!(x & 3)) {
+		x >>= 2;
+		r += 2;
+	}
+	if (!(x & 1)) {
+		x >>= 1;
+		r += 1;
+	}
+	return r;
+}
+
+/**
+ * fls - find last (most-significant) bit set
+ * @x: the word to search
+ *
+ * This is defined the same way as ffs.
+ * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
+ */
+static inline int generic_fls(int x)
+{
+	int r = 32;
+
+	if (!x)
+		return 0;
+	if (!(x & 0xffff0000u)) {
+		x <<= 16;
+		r -= 16;
+	}
+	if (!(x & 0xff000000u)) {
+		x <<= 8;
+		r -= 8;
+	}
+	if (!(x & 0xf0000000u)) {
+		x <<= 4;
+		r -= 4;
+	}
+	if (!(x & 0xc0000000u)) {
+		x <<= 2;
+		r -= 2;
+	}
+	if (!(x & 0x80000000u)) {
+		x <<= 1;
+		r -= 1;
+	}
+	return r;
+}
+
+
+/*
+ * hweightN: returns the hamming weight (i.e. the number
+ * of bits set) of a N-bit word
+ */
+
+static inline unsigned int generic_hweight32(unsigned int w)
+{
+	unsigned int res = (w & 0x55555555) + ((w >> 1) & 0x55555555);
+	res = (res & 0x33333333) + ((res >> 2) & 0x33333333);
+	res = (res & 0x0F0F0F0F) + ((res >> 4) & 0x0F0F0F0F);
+	res = (res & 0x00FF00FF) + ((res >> 8) & 0x00FF00FF);
+	return (res & 0x0000FFFF) + ((res >> 16) & 0x0000FFFF);
+}
+
+static inline unsigned int generic_hweight16(unsigned int w)
+{
+	unsigned int res = (w & 0x5555) + ((w >> 1) & 0x5555);
+	res = (res & 0x3333) + ((res >> 2) & 0x3333);
+	res = (res & 0x0F0F) + ((res >> 4) & 0x0F0F);
+	return (res & 0x00FF) + ((res >> 8) & 0x00FF);
+}
+
+static inline unsigned int generic_hweight8(unsigned int w)
+{
+	unsigned int res = (w & 0x55) + ((w >> 1) & 0x55);
+	res = (res & 0x33) + ((res >> 2) & 0x33);
+	return (res & 0x0F) + ((res >> 4) & 0x0F);
+}
+
+#define BIT_MASK(nr)		(1UL << ((nr) % BITS_PER_LONG))
+#define BIT_WORD(nr)		((nr) / BITS_PER_LONG)
+
+#include <asm/bitops.h>
+
+/* linux/include/asm-generic/bitops/non-atomic.h */
+
+#ifndef PLATFORM__SET_BIT
+# define __set_bit generic_set_bit
+#endif
+
+#ifndef PLATFORM__CLEAR_BIT
+# define __clear_bit generic_clear_bit
+#endif
+
+#ifndef PLATFORM_FFS
+# define ffs generic_ffs
+#endif
+
+#ifndef PLATFORM_FLS
+# define fls generic_fls
+#endif
+
+/**
+ * __set_bit - Set a bit in memory
+ * @nr: the bit to set
+ * @addr: the address to start counting from
+ *
+ * Unlike set_bit(), this function is non-atomic and may be reordered.
+ * If it's called on the same region of memory simultaneously, the effect
+ * may be that only one operation succeeds.
+ */
+static inline void generic_set_bit(int nr, volatile unsigned long *addr)
+{
+	unsigned long mask = BIT_MASK(nr);
+	unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+
+	*p  |= mask;
+}
+
+static inline void generic_clear_bit(int nr, volatile unsigned long *addr)
+{
+	unsigned long mask = BIT_MASK(nr);
+	unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+
+	*p &= ~mask;
+}
+
+#endif
diff --git a/qemu/roms/u-boot/include/linux/bitrev.h b/qemu/roms/u-boot/include/linux/bitrev.h
new file mode 100644
index 000000000..6876e1b2e
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/bitrev.h
@@ -0,0 +1,22 @@
+/*
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Based on bitrev from the Linux kernel, by Akinobu Mita
+ */
+
+#ifndef _LINUX_BITREV_H
+#define _LINUX_BITREV_H
+
+#include <linux/types.h>
+
+extern u8 const byte_rev_table[256];
+
+static inline u8 bitrev8(u8 byte)
+{
+	return byte_rev_table[byte];
+}
+
+u16 bitrev16(u16 in);
+u32 bitrev32(u32 in);
+
+#endif /* _LINUX_BITREV_H */
diff --git a/qemu/roms/u-boot/include/linux/byteorder/big_endian.h b/qemu/roms/u-boot/include/linux/byteorder/big_endian.h
new file mode 100644
index 000000000..aaf77577c
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/byteorder/big_endian.h
@@ -0,0 +1,110 @@
+#ifndef _LINUX_BYTEORDER_BIG_ENDIAN_H
+#define _LINUX_BYTEORDER_BIG_ENDIAN_H
+
+#ifndef __BIG_ENDIAN
+#define __BIG_ENDIAN 4321
+#endif
+#ifndef __BIG_ENDIAN_BITFIELD
+#define __BIG_ENDIAN_BITFIELD
+#endif
+#define __BYTE_ORDER	__BIG_ENDIAN
+
+#include <linux/compiler.h>
+#include <linux/types.h>
+#include <linux/byteorder/swab.h>
+
+#define __constant_htonl(x) ((__force __be32)(__u32)(x))
+#define __constant_ntohl(x) ((__force __u32)(__be32)(x))
+#define __constant_htons(x) ((__force __be16)(__u16)(x))
+#define __constant_ntohs(x) ((__force __u16)(__be16)(x))
+#define __constant_cpu_to_le64(x) ((__force __le64)___constant_swab64((x)))
+#define __constant_le64_to_cpu(x) ___constant_swab64((__force __u64)(__le64)(x))
+#define __constant_cpu_to_le32(x) ((__force __le32)___constant_swab32((x)))
+#define __constant_le32_to_cpu(x) ___constant_swab32((__force __u32)(__le32)(x))
+#define __constant_cpu_to_le16(x) ((__force __le16)___constant_swab16((x)))
+#define __constant_le16_to_cpu(x) ___constant_swab16((__force __u16)(__le16)(x))
+#define __constant_cpu_to_be64(x) ((__force __be64)(__u64)(x))
+#define __constant_be64_to_cpu(x) ((__force __u64)(__be64)(x))
+#define __constant_cpu_to_be32(x) ((__force __be32)(__u32)(x))
+#define __constant_be32_to_cpu(x) ((__force __u32)(__be32)(x))
+#define __constant_cpu_to_be16(x) ((__force __be16)(__u16)(x))
+#define __constant_be16_to_cpu(x) ((__force __u16)(__be16)(x))
+#define __cpu_to_le64(x) ((__force __le64)__swab64((x)))
+#define __le64_to_cpu(x) __swab64((__force __u64)(__le64)(x))
+#define __cpu_to_le32(x) ((__force __le32)__swab32((x)))
+#define __le32_to_cpu(x) __swab32((__force __u32)(__le32)(x))
+#define __cpu_to_le16(x) ((__force __le16)__swab16((x)))
+#define __le16_to_cpu(x) __swab16((__force __u16)(__le16)(x))
+#define __cpu_to_be64(x) ((__force __be64)(__u64)(x))
+#define __be64_to_cpu(x) ((__force __u64)(__be64)(x))
+#define __cpu_to_be32(x) ((__force __be32)(__u32)(x))
+#define __be32_to_cpu(x) ((__force __u32)(__be32)(x))
+#define __cpu_to_be16(x) ((__force __be16)(__u16)(x))
+#define __be16_to_cpu(x) ((__force __u16)(__be16)(x))
+
+static inline __le64 __cpu_to_le64p(const __u64 *p)
+{
+	return (__force __le64)__swab64p(p);
+}
+static inline __u64 __le64_to_cpup(const __le64 *p)
+{
+	return __swab64p((__u64 *)p);
+}
+static inline __le32 __cpu_to_le32p(const __u32 *p)
+{
+	return (__force __le32)__swab32p(p);
+}
+static inline __u32 __le32_to_cpup(const __le32 *p)
+{
+	return __swab32p((__u32 *)p);
+}
+static inline __le16 __cpu_to_le16p(const __u16 *p)
+{
+	return (__force __le16)__swab16p(p);
+}
+static inline __u16 __le16_to_cpup(const __le16 *p)
+{
+	return __swab16p((__u16 *)p);
+}
+static inline __be64 __cpu_to_be64p(const __u64 *p)
+{
+	return (__force __be64)*p;
+}
+static inline __u64 __be64_to_cpup(const __be64 *p)
+{
+	return (__force __u64)*p;
+}
+static inline __be32 __cpu_to_be32p(const __u32 *p)
+{
+	return (__force __be32)*p;
+}
+static inline __u32 __be32_to_cpup(const __be32 *p)
+{
+	return (__force __u32)*p;
+}
+static inline __be16 __cpu_to_be16p(const __u16 *p)
+{
+	return (__force __be16)*p;
+}
+static inline __u16 __be16_to_cpup(const __be16 *p)
+{
+	return (__force __u16)*p;
+}
+#define __cpu_to_le64s(x) __swab64s((x))
+#define __le64_to_cpus(x) __swab64s((x))
+#define __cpu_to_le32s(x) __swab32s((x))
+#define __le32_to_cpus(x) __swab32s((x))
+#define __cpu_to_le16s(x) __swab16s((x))
+#define __le16_to_cpus(x) __swab16s((x))
+#define __cpu_to_be64s(x) do { (void)(x); } while (0)
+#define __be64_to_cpus(x) do { (void)(x); } while (0)
+#define __cpu_to_be32s(x) do { (void)(x); } while (0)
+#define __be32_to_cpus(x) do { (void)(x); } while (0)
+#define __cpu_to_be16s(x) do { (void)(x); } while (0)
+#define __be16_to_cpus(x) do { (void)(x); } while (0)
+
+#ifdef __KERNEL__
+#include <linux/byteorder/generic.h>
+#endif
+
+#endif /* _LINUX_BYTEORDER_BIG_ENDIAN_H */
diff --git a/qemu/roms/u-boot/include/linux/byteorder/generic.h b/qemu/roms/u-boot/include/linux/byteorder/generic.h
new file mode 100644
index 000000000..cff850f85
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/byteorder/generic.h
@@ -0,0 +1,180 @@
+#ifndef _LINUX_BYTEORDER_GENERIC_H
+#define _LINUX_BYTEORDER_GENERIC_H
+
+/*
+ * linux/byteorder_generic.h
+ * Generic Byte-reordering support
+ *
+ * Francois-Rene Rideau <fare@tunes.org> 19970707
+ *    gathered all the good ideas from all asm-foo/byteorder.h into one file,
+ *    cleaned them up.
+ *    I hope it is compliant with non-GCC compilers.
+ *    I decided to put __BYTEORDER_HAS_U64__ in byteorder.h,
+ *    because I wasn't sure it would be ok to put it in types.h
+ *    Upgraded it to 2.1.43
+ * Francois-Rene Rideau <fare@tunes.org> 19971012
+ *    Upgraded it to 2.1.57
+ *    to please Linus T., replaced huge #ifdef's between little/big endian
+ *    by nestedly #include'd files.
+ * Francois-Rene Rideau <fare@tunes.org> 19971205
+ *    Made it to 2.1.71; now a facelift:
+ *    Put files under include/linux/byteorder/
+ *    Split swab from generic support.
+ *
+ * TODO:
+ *   = Regular kernel maintainers could also replace all these manual
+ *    byteswap macros that remain, disseminated among drivers,
+ *    after some grep or the sources...
+ *   = Linus might want to rename all these macros and files to fit his taste,
+ *    to fit his personal naming scheme.
+ *   = it seems that a few drivers would also appreciate
+ *    nybble swapping support...
+ *   = every architecture could add their byteswap macro in asm/byteorder.h
+ *    see how some architectures already do (i386, alpha, ppc, etc)
+ *   = cpu_to_beXX and beXX_to_cpu might some day need to be well
+ *    distinguished throughout the kernel. This is not the case currently,
+ *    since little endian, big endian, and pdp endian machines needn't it.
+ *    But this might be the case for, say, a port of Linux to 20/21 bit
+ *    architectures (and F21 Linux addict around?).
+ */
+
+/*
+ * The following macros are to be defined by <asm/byteorder.h>:
+ *
+ * Conversion of long and short int between network and host format
+ *	ntohl(__u32 x)
+ *	ntohs(__u16 x)
+ *	htonl(__u32 x)
+ *	htons(__u16 x)
+ * It seems that some programs (which? where? or perhaps a standard? POSIX?)
+ * might like the above to be functions, not macros (why?).
+ * if that's true, then detect them, and take measures.
+ * Anyway, the measure is: define only ___ntohl as a macro instead,
+ * and in a separate file, have
+ * unsigned long inline ntohl(x){return ___ntohl(x);}
+ *
+ * The same for constant arguments
+ *	__constant_ntohl(__u32 x)
+ *	__constant_ntohs(__u16 x)
+ *	__constant_htonl(__u32 x)
+ *	__constant_htons(__u16 x)
+ *
+ * Conversion of XX-bit integers (16- 32- or 64-)
+ * between native CPU format and little/big endian format
+ * 64-bit stuff only defined for proper architectures
+ *	cpu_to_[bl]eXX(__uXX x)
+ *	[bl]eXX_to_cpu(__uXX x)
+ *
+ * The same, but takes a pointer to the value to convert
+ *	cpu_to_[bl]eXXp(__uXX x)
+ *	[bl]eXX_to_cpup(__uXX x)
+ *
+ * The same, but change in situ
+ *	cpu_to_[bl]eXXs(__uXX x)
+ *	[bl]eXX_to_cpus(__uXX x)
+ *
+ * See asm-foo/byteorder.h for examples of how to provide
+ * architecture-optimized versions
+ *
+ */
+
+
+#if defined(__KERNEL__)
+/*
+ * inside the kernel, we can use nicknames;
+ * outside of it, we must avoid POSIX namespace pollution...
+ */
+#define cpu_to_le64 __cpu_to_le64
+#define le64_to_cpu __le64_to_cpu
+#define cpu_to_le32 __cpu_to_le32
+#define le32_to_cpu __le32_to_cpu
+#define cpu_to_le16 __cpu_to_le16
+#define le16_to_cpu __le16_to_cpu
+#define cpu_to_be64 __cpu_to_be64
+#define be64_to_cpu __be64_to_cpu
+#define cpu_to_be32 __cpu_to_be32
+#define be32_to_cpu __be32_to_cpu
+#define cpu_to_be16 __cpu_to_be16
+#define be16_to_cpu __be16_to_cpu
+#define cpu_to_le64p __cpu_to_le64p
+#define le64_to_cpup __le64_to_cpup
+#define cpu_to_le32p __cpu_to_le32p
+#define le32_to_cpup __le32_to_cpup
+#define cpu_to_le16p __cpu_to_le16p
+#define le16_to_cpup __le16_to_cpup
+#define cpu_to_be64p __cpu_to_be64p
+#define be64_to_cpup __be64_to_cpup
+#define cpu_to_be32p __cpu_to_be32p
+#define be32_to_cpup __be32_to_cpup
+#define cpu_to_be16p __cpu_to_be16p
+#define be16_to_cpup __be16_to_cpup
+#define cpu_to_le64s __cpu_to_le64s
+#define le64_to_cpus __le64_to_cpus
+#define cpu_to_le32s __cpu_to_le32s
+#define le32_to_cpus __le32_to_cpus
+#define cpu_to_le16s __cpu_to_le16s
+#define le16_to_cpus __le16_to_cpus
+#define cpu_to_be64s __cpu_to_be64s
+#define be64_to_cpus __be64_to_cpus
+#define cpu_to_be32s __cpu_to_be32s
+#define be32_to_cpus __be32_to_cpus
+#define cpu_to_be16s __cpu_to_be16s
+#define be16_to_cpus __be16_to_cpus
+#endif
+
+
+/*
+ * Handle ntohl and suches. These have various compatibility
+ * issues - like we want to give the prototype even though we
+ * also have a macro for them in case some strange program
+ * wants to take the address of the thing or something..
+ *
+ * Note that these used to return a "long" in libc5, even though
+ * long is often 64-bit these days.. Thus the casts.
+ *
+ * They have to be macros in order to do the constant folding
+ * correctly - if the argument passed into a inline function
+ * it is no longer constant according to gcc..
+ */
+
+#undef ntohl
+#undef ntohs
+#undef htonl
+#undef htons
+
+/*
+ * Do the prototypes. Somebody might want to take the
+ * address or some such sick thing..
+ */
+#if defined(__KERNEL__) || (defined (__GLIBC__) && __GLIBC__ >= 2)
+extern __u32			ntohl(__u32);
+extern __u32			htonl(__u32);
+#else
+extern unsigned long int	ntohl(unsigned long int);
+extern unsigned long int	htonl(unsigned long int);
+#endif
+extern unsigned short int	ntohs(unsigned short int);
+extern unsigned short int	htons(unsigned short int);
+
+
+#if defined(__GNUC__) && (__GNUC__ >= 2)
+
+#define ___htonl(x) __cpu_to_be32(x)
+#define ___htons(x) __cpu_to_be16(x)
+#define ___ntohl(x) __be32_to_cpu(x)
+#define ___ntohs(x) __be16_to_cpu(x)
+
+#if defined(__KERNEL__) || (defined (__GLIBC__) && __GLIBC__ >= 2)
+#define htonl(x) ___htonl(x)
+#define ntohl(x) ___ntohl(x)
+#else
+#define htonl(x) ((unsigned long)___htonl(x))
+#define ntohl(x) ((unsigned long)___ntohl(x))
+#endif
+#define htons(x) ___htons(x)
+#define ntohs(x) ___ntohs(x)
+
+#endif /* OPTIMIZE */
+
+
+#endif /* _LINUX_BYTEORDER_GENERIC_H */
diff --git a/qemu/roms/u-boot/include/linux/byteorder/little_endian.h b/qemu/roms/u-boot/include/linux/byteorder/little_endian.h
new file mode 100644
index 000000000..a4cb3bfde
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/byteorder/little_endian.h
@@ -0,0 +1,110 @@
+#ifndef _LINUX_BYTEORDER_LITTLE_ENDIAN_H
+#define _LINUX_BYTEORDER_LITTLE_ENDIAN_H
+
+#ifndef __LITTLE_ENDIAN
+#define __LITTLE_ENDIAN 1234
+#endif
+#ifndef __LITTLE_ENDIAN_BITFIELD
+#define __LITTLE_ENDIAN_BITFIELD
+#endif
+#define	__BYTE_ORDER	__LITTLE_ENDIAN
+
+#include <linux/compiler.h>
+#include <linux/types.h>
+#include <linux/byteorder/swab.h>
+
+#define __constant_htonl(x) ((__force __be32)___constant_swab32((x)))
+#define __constant_ntohl(x) ___constant_swab32((__force __be32)(x))
+#define __constant_htons(x) ((__force __be16)___constant_swab16((x)))
+#define __constant_ntohs(x) ___constant_swab16((__force __be16)(x))
+#define __constant_cpu_to_le64(x) ((__force __le64)(__u64)(x))
+#define __constant_le64_to_cpu(x) ((__force __u64)(__le64)(x))
+#define __constant_cpu_to_le32(x) ((__force __le32)(__u32)(x))
+#define __constant_le32_to_cpu(x) ((__force __u32)(__le32)(x))
+#define __constant_cpu_to_le16(x) ((__force __le16)(__u16)(x))
+#define __constant_le16_to_cpu(x) ((__force __u16)(__le16)(x))
+#define __constant_cpu_to_be64(x) ((__force __be64)___constant_swab64((x)))
+#define __constant_be64_to_cpu(x) ___constant_swab64((__force __u64)(__be64)(x))
+#define __constant_cpu_to_be32(x) ((__force __be32)___constant_swab32((x)))
+#define __constant_be32_to_cpu(x) ___constant_swab32((__force __u32)(__be32)(x))
+#define __constant_cpu_to_be16(x) ((__force __be16)___constant_swab16((x)))
+#define __constant_be16_to_cpu(x) ___constant_swab16((__force __u16)(__be16)(x))
+#define __cpu_to_le64(x) ((__force __le64)(__u64)(x))
+#define __le64_to_cpu(x) ((__force __u64)(__le64)(x))
+#define __cpu_to_le32(x) ((__force __le32)(__u32)(x))
+#define __le32_to_cpu(x) ((__force __u32)(__le32)(x))
+#define __cpu_to_le16(x) ((__force __le16)(__u16)(x))
+#define __le16_to_cpu(x) ((__force __u16)(__le16)(x))
+#define __cpu_to_be64(x) ((__force __be64)__swab64((x)))
+#define __be64_to_cpu(x) __swab64((__force __u64)(__be64)(x))
+#define __cpu_to_be32(x) ((__force __be32)__swab32((x)))
+#define __be32_to_cpu(x) __swab32((__force __u32)(__be32)(x))
+#define __cpu_to_be16(x) ((__force __be16)__swab16((x)))
+#define __be16_to_cpu(x) __swab16((__force __u16)(__be16)(x))
+
+static inline __le64 __cpu_to_le64p(const __u64 *p)
+{
+	return (__force __le64)*p;
+}
+static inline __u64 __le64_to_cpup(const __le64 *p)
+{
+	return (__force __u64)*p;
+}
+static inline __le32 __cpu_to_le32p(const __u32 *p)
+{
+	return (__force __le32)*p;
+}
+static inline __u32 __le32_to_cpup(const __le32 *p)
+{
+	return (__force __u32)*p;
+}
+static inline __le16 __cpu_to_le16p(const __u16 *p)
+{
+	return (__force __le16)*p;
+}
+static inline __u16 __le16_to_cpup(const __le16 *p)
+{
+	return (__force __u16)*p;
+}
+static inline __be64 __cpu_to_be64p(const __u64 *p)
+{
+	return (__force __be64)__swab64p(p);
+}
+static inline __u64 __be64_to_cpup(const __be64 *p)
+{
+	return __swab64p((__u64 *)p);
+}
+static inline __be32 __cpu_to_be32p(const __u32 *p)
+{
+	return (__force __be32)__swab32p(p);
+}
+static inline __u32 __be32_to_cpup(const __be32 *p)
+{
+	return __swab32p((__u32 *)p);
+}
+static inline __be16 __cpu_to_be16p(const __u16 *p)
+{
+	return (__force __be16)__swab16p(p);
+}
+static inline __u16 __be16_to_cpup(const __be16 *p)
+{
+	return __swab16p((__u16 *)p);
+}
+#define __cpu_to_le64s(x) do { (void)(x); } while (0)
+#define __le64_to_cpus(x) do { (void)(x); } while (0)
+#define __cpu_to_le32s(x) do { (void)(x); } while (0)
+#define __le32_to_cpus(x) do { (void)(x); } while (0)
+#define __cpu_to_le16s(x) do { (void)(x); } while (0)
+#define __le16_to_cpus(x) do { (void)(x); } while (0)
+#define __cpu_to_be64s(x) __swab64s((x))
+#define __be64_to_cpus(x) __swab64s((x))
+#define __cpu_to_be32s(x) __swab32s((x))
+#define __be32_to_cpus(x) __swab32s((x))
+#define __cpu_to_be16s(x) __swab16s((x))
+#define __be16_to_cpus(x) __swab16s((x))
+
+#ifdef __KERNEL__
+#include <linux/byteorder/generic.h>
+#endif
+
+#endif /* _LINUX_BYTEORDER_LITTLE_ENDIAN_H */
diff --git a/qemu/roms/u-boot/include/linux/byteorder/swab.h b/qemu/roms/u-boot/include/linux/byteorder/swab.h
new file mode 100644
index 000000000..4334fa77e
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/byteorder/swab.h
@@ -0,0 +1,156 @@
+#ifndef _LINUX_BYTEORDER_SWAB_H
+#define _LINUX_BYTEORDER_SWAB_H
+
+/*
+ * linux/byteorder/swab.h
+ * Byte-swapping, independently from CPU endianness
+ *	swabXX[ps]?(foo)
+ *
+ * Francois-Rene Rideau <fare@tunes.org> 19971205
+ *    separated swab functions from cpu_to_XX,
+ *    to clean up support for bizarre-endian architectures.
+ *
+ * See asm-i386/byteorder.h and suches for examples of how to provide
+ * architecture-dependent optimized versions
+ *
+ */
+
+/* casts are necessary for constants, because we never know how for sure
+ * how U/UL/ULL map to __u16, __u32, __u64. At least not in a portable way.
+ */
+#define ___swab16(x) \
+	((__u16)( \
+		(((__u16)(x) & (__u16)0x00ffU) << 8) | \
+		(((__u16)(x) & (__u16)0xff00U) >> 8) ))
+#define ___swab32(x) \
+	((__u32)( \
+		(((__u32)(x) & (__u32)0x000000ffUL) << 24) | \
+		(((__u32)(x) & (__u32)0x0000ff00UL) <<  8) | \
+		(((__u32)(x) & (__u32)0x00ff0000UL) >>  8) | \
+		(((__u32)(x) & (__u32)0xff000000UL) >> 24) ))
+#define ___swab64(x) \
+	((__u64)( \
+		(__u64)(((__u64)(x) & (__u64)0x00000000000000ffULL) << 56) | \
+		(__u64)(((__u64)(x) & (__u64)0x000000000000ff00ULL) << 40) | \
+		(__u64)(((__u64)(x) & (__u64)0x0000000000ff0000ULL) << 24) | \
+		(__u64)(((__u64)(x) & (__u64)0x00000000ff000000ULL) <<  8) | \
+		(__u64)(((__u64)(x) & (__u64)0x000000ff00000000ULL) >>  8) | \
+		(__u64)(((__u64)(x) & (__u64)0x0000ff0000000000ULL) >> 24) | \
+		(__u64)(((__u64)(x) & (__u64)0x00ff000000000000ULL) >> 40) | \
+		(__u64)(((__u64)(x) & (__u64)0xff00000000000000ULL) >> 56) ))
+
+/*
+ * provide defaults when no architecture-specific optimization is detected
+ */
+#ifndef __arch__swab16
+#  define __arch__swab16(x) ___swab16(x)
+#endif
+#ifndef __arch__swab32
+#  define __arch__swab32(x) ___swab32(x)
+#endif
+#ifndef __arch__swab64
+#  define __arch__swab64(x) ___swab64(x)
+#endif
+
+#ifndef __arch__swab16p
+#  define __arch__swab16p(x) __swab16(*(x))
+#endif
+#ifndef __arch__swab32p
+#  define __arch__swab32p(x) __swab32(*(x))
+#endif
+#ifndef __arch__swab64p
+#  define __arch__swab64p(x) __swab64(*(x))
+#endif
+
+#ifndef __arch__swab16s
+#  define __arch__swab16s(x) do { *(x) = __swab16p((x)); } while (0)
+#endif
+#ifndef __arch__swab32s
+#  define __arch__swab32s(x) do { *(x) = __swab32p((x)); } while (0)
+#endif
+#ifndef __arch__swab64s
+#  define __arch__swab64s(x) do { *(x) = __swab64p((x)); } while (0)
+#endif
+
+
+/*
+ * Allow constant folding
+ */
+#if defined(__GNUC__) && (__GNUC__ >= 2) && defined(__OPTIMIZE__)
+#  define __swab16(x) \
+(__builtin_constant_p((__u16)(x)) ? \
+ ___swab16((x)) : \
+ __fswab16((x)))
+#  define __swab32(x) \
+(__builtin_constant_p((__u32)(x)) ? \
+ ___swab32((x)) : \
+ __fswab32((x)))
+#  define __swab64(x) \
+(__builtin_constant_p((__u64)(x)) ? \
+ ___swab64((x)) : \
+ __fswab64((x)))
+#else
+#  define __swab16(x) __fswab16(x)
+#  define __swab32(x) __fswab32(x)
+#  define __swab64(x) __fswab64(x)
+#endif /* OPTIMIZE */
+
+
+static __inline__ __attribute__((const)) __u16 __fswab16(__u16 x)
+{
+	return __arch__swab16(x);
+}
+static __inline__ __u16 __swab16p(const __u16 *x)
+{
+	return __arch__swab16p(x);
+}
+static __inline__ void __swab16s(__u16 *addr)
+{
+	__arch__swab16s(addr);
+}
+
+static __inline__ __attribute__((const)) __u32 __fswab32(__u32 x)
+{
+	return __arch__swab32(x);
+}
+static __inline__ __u32 __swab32p(const __u32 *x)
+{
+	return __arch__swab32p(x);
+}
+static __inline__ void __swab32s(__u32 *addr)
+{
+	__arch__swab32s(addr);
+}
+
+static __inline__ __attribute__((const)) __u64 __fswab64(__u64 x)
+{
+#  ifdef __SWAB_64_THRU_32__
+	__u32 h = x >> 32;
+	__u32 l = x & ((1ULL<<32)-1);
+	return (((__u64)__swab32(l)) << 32) | ((__u64)(__swab32(h)));
+#  else
+	return __arch__swab64(x);
+#  endif
+}
+static __inline__ __u64 __swab64p(const __u64 *x)
+{
+	return __arch__swab64p(x);
+}
+static __inline__ void __swab64s(__u64 *addr)
+{
+	__arch__swab64s(addr);
+}
+
+#if defined(__KERNEL__)
+#define swab16 __swab16
+#define swab32 __swab32
+#define swab64 __swab64
+#define swab16p __swab16p
+#define swab32p __swab32p
+#define swab64p __swab64p
+#define swab16s __swab16s
+#define swab32s __swab32s
+#define swab64s __swab64s
+#endif
+
+#endif /* _LINUX_BYTEORDER_SWAB_H */
diff --git a/qemu/roms/u-boot/include/linux/compat.h b/qemu/roms/u-boot/include/linux/compat.h
new file mode 100644
index 000000000..3fdfb399b
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/compat.h
@@ -0,0 +1,60 @@
+#ifndef _LINUX_COMPAT_H_
+#define _LINUX_COMPAT_H_
+
+#define ndelay(x)	udelay(1)
+
+#define dev_dbg(dev, fmt, args...)		\
+	debug(fmt, ##args)
+#define dev_vdbg(dev, fmt, args...)		\
+	debug(fmt, ##args)
+#define dev_info(dev, fmt, args...)		\
+	printf(fmt, ##args)
+#define dev_err(dev, fmt, args...)		\
+	printf(fmt, ##args)
+#define printk	printf
+
+#define KERN_EMERG
+#define KERN_ALERT
+#define KERN_CRIT
+#define KERN_ERR
+#define KERN_WARNING
+#define KERN_NOTICE
+#define KERN_INFO
+#define KERN_DEBUG
+
+#define kmalloc(size, flags)	malloc(size)
+#define kzalloc(size, flags)	calloc(size, 1)
+#define vmalloc(size)		malloc(size)
+#define kfree(ptr)		free(ptr)
+#define vfree(ptr)		free(ptr)
+
+#define DECLARE_WAITQUEUE(...)	do { } while (0)
+#define add_wait_queue(...)	do { } while (0)
+#define remove_wait_queue(...)	do { } while (0)
+
+#define KERNEL_VERSION(a,b,c)	(((a) << 16) + ((b) << 8) + (c))
+
+/*
+ * ..and if you can't take the strict
+ * types, you can specify one yourself.
+ *
+ * Or not use min/max at all, of course.
+ */
+#define min_t(type,x,y) \
+	({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
+#define max_t(type,x,y) \
+	({ type __x = (x); type __y = (y); __x > __y ? __x: __y; })
+
+#ifndef BUG
+#define BUG() do { \
+	printf("U-Boot BUG at %s:%d!\n", __FILE__, __LINE__); \
+} while (0)
+
+#define BUG_ON(condition) do { if (condition) BUG(); } while(0)
+#endif /* BUG */
+
+#define WARN_ON(x) if (x) {printf("WARNING in %s line %d\n" \
+				  , __FILE__, __LINE__); }
+
+#define PAGE_SIZE	4096
+#endif
diff --git a/qemu/roms/u-boot/include/linux/compiler-gcc.h b/qemu/roms/u-boot/include/linux/compiler-gcc.h
new file mode 100644
index 000000000..9896e547b
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/compiler-gcc.h
@@ -0,0 +1,93 @@
+#ifndef __LINUX_COMPILER_H
+#error "Please don't include <linux/compiler-gcc.h> directly, include <linux/compiler.h> instead."
+#endif
+
+/*
+ * Common definitions for all gcc versions go here.
+ */
+
+
+/* Optimization barrier */
+/* The "volatile" is due to gcc bugs */
+#define barrier() __asm__ __volatile__("": : :"memory")
+
+/*
+ * This macro obfuscates arithmetic on a variable address so that gcc
+ * shouldn't recognize the original var, and make assumptions about it.
+ *
+ * This is needed because the C standard makes it undefined to do
+ * pointer arithmetic on "objects" outside their boundaries and the
+ * gcc optimizers assume this is the case. In particular they
+ * assume such arithmetic does not wrap.
+ *
+ * A miscompilation has been observed because of this on PPC.
+ * To work around it we hide the relationship of the pointer and the object
+ * using this macro.
+ *
+ * Versions of the ppc64 compiler before 4.1 had a bug where use of
+ * RELOC_HIDE could trash r30. The bug can be worked around by changing
+ * the inline assembly constraint from =g to =r, in this particular
+ * case either is valid.
+ */
+#define RELOC_HIDE(ptr, off)					\
+  ({ unsigned long __ptr;					\
+    __asm__ ("" : "=r"(__ptr) : "0"(ptr));		\
+    (typeof(ptr)) (__ptr + (off)); })
+
+/* &a[0] degrades to a pointer: a different type from an array */
+#define __must_be_array(a) \
+  BUILD_BUG_ON_ZERO(__builtin_types_compatible_p(typeof(a), typeof(&a[0])))
+
+/*
+ * Force always-inline if the user requests it so via the .config,
+ * or if gcc is too old:
+ */
+#if !defined(CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING) || \
+    !defined(CONFIG_OPTIMIZE_INLINING) || (__GNUC__ < 4)
+# define inline		inline		__attribute__((always_inline))
+# define __inline__	__inline__	__attribute__((always_inline))
+# define __inline	__inline	__attribute__((always_inline))
+#endif
+
+#define __deprecated			__attribute__((deprecated))
+#ifndef __packed
+# define __packed			__attribute__((packed))
+#endif
+#define __weak				__attribute__((weak))
+
+/*
+ * it doesn't make sense on ARM (currently the only user of __naked) to trace
+ * naked functions because then mcount is called without stack and frame pointer
+ * being set up and there is no chance to restore the lr register to the value
+ * before mcount was called.
+ */
+#define __naked				__attribute__((naked)) notrace
+
+#define __noreturn			__attribute__((noreturn))
+
+/*
+ * From the GCC manual:
+ *
+ * Many functions have no effects except the return value and their
+ * return value depends only on the parameters and/or global
+ * variables.  Such a function can be subject to common subexpression
+ * elimination and loop optimization just as an arithmetic operator
+ * would be.
+ * [...]
+ */
+#ifndef __pure
+# define __pure				__attribute__((pure))
+#endif
+#ifndef __aligned
+# define __aligned(x)			__attribute__((aligned(x)))
+#endif
+#define __printf(a,b)			__attribute__((format(printf,a,b)))
+#define  noinline			__attribute__((noinline))
+#define __attribute_const__		__attribute__((__const__))
+#define __maybe_unused			__attribute__((unused))
+#define __always_unused			__attribute__((unused))
+
+#define __gcc_header(x) #x
+#define _gcc_header(x) __gcc_header(linux/compiler-gcc##x.h)
+#define gcc_header(x) _gcc_header(x)
+#include gcc_header(__GNUC__)
diff --git a/qemu/roms/u-boot/include/linux/compiler-gcc3.h b/qemu/roms/u-boot/include/linux/compiler-gcc3.h
new file mode 100644
index 000000000..2befe6513
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/compiler-gcc3.h
@@ -0,0 +1,21 @@
+#ifndef __LINUX_COMPILER_H
+#error "Please don't include <linux/compiler-gcc3.h> directly, include <linux/compiler.h> instead."
+#endif
+
+#if __GNUC_MINOR__ >= 3
+# define __used			__attribute__((__used__))
+#else
+# define __used			__attribute__((__unused__))
+#endif
+
+#if __GNUC_MINOR__ >= 4
+#define __must_check		__attribute__((warn_unused_result))
+#endif
+
+/*
+ * A trick to suppress uninitialized variable warning without generating any
+ * code
+ */
+#define uninitialized_var(x) x = x
+
+#define __always_inline		inline __attribute__((always_inline))
diff --git a/qemu/roms/u-boot/include/linux/compiler-gcc4.h b/qemu/roms/u-boot/include/linux/compiler-gcc4.h
new file mode 100644
index 000000000..27d11ca7b
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/compiler-gcc4.h
@@ -0,0 +1,63 @@
+#ifndef __LINUX_COMPILER_H
+#error "Please don't include <linux/compiler-gcc4.h> directly, include <linux/compiler.h> instead."
+#endif
+
+/* GCC 4.1.[01] miscompiles __weak */
+#ifdef __KERNEL__
+# if __GNUC_MINOR__ == 1 && __GNUC_PATCHLEVEL__ <= 1
+#  error Your version of gcc miscompiles the __weak directive
+# endif
+#endif
+
+#define __used			__attribute__((__used__))
+#define __must_check 		__attribute__((warn_unused_result))
+#define __compiler_offsetof(a,b) __builtin_offsetof(a,b)
+#ifndef __always_inline
+# define __always_inline		inline __attribute__((always_inline))
+#endif
+
+/*
+ * A trick to suppress uninitialized variable warning without generating any
+ * code
+ */
+#define uninitialized_var(x) x = x
+
+#if __GNUC_MINOR__ >= 3
+/* Mark functions as cold. gcc will assume any path leading to a call
+   to them will be unlikely.  This means a lot of manual unlikely()s
+   are unnecessary now for any paths leading to the usual suspects
+   like BUG(), printk(), panic() etc. [but let's keep them for now for
+   older compilers]
+
+   Early snapshots of gcc 4.3 don't support this and we can't detect this
+   in the preprocessor, but we can live with this because they're unreleased.
+   Maketime probing would be overkill here.
+
+   gcc also has a __attribute__((__hot__)) to move hot functions into
+   a special section, but I don't see any sense in this right now in
+   the kernel context */
+#define __cold			__attribute__((__cold__))
+
+
+#if __GNUC_MINOR__ >= 5
+/*
+ * Mark a position in code as unreachable.  This can be used to
+ * suppress control flow warnings after asm blocks that transfer
+ * control elsewhere.
+ *
+ * Early snapshots of gcc 4.5 don't support this and we can't detect
+ * this in the preprocessor, but we can live with this because they're
+ * unreleased.  Really, we need to have autoconf for the kernel.
+ */
+#define unreachable() __builtin_unreachable()
+#endif
+
+#endif
+
+#if __GNUC_MINOR__ > 0
+#define __compiletime_object_size(obj) __builtin_object_size(obj, 0)
+#endif
+#if __GNUC_MINOR__ >= 4
+#define __compiletime_warning(message) __attribute__((warning(message)))
+#define __compiletime_error(message) __attribute__((error(message)))
+#endif
diff --git a/qemu/roms/u-boot/include/linux/compiler.h b/qemu/roms/u-boot/include/linux/compiler.h
new file mode 100644
index 000000000..5be3dab4a
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/compiler.h
@@ -0,0 +1,303 @@
+#ifndef __LINUX_COMPILER_H
+#define __LINUX_COMPILER_H
+
+#ifndef __ASSEMBLY__
+
+#ifdef __CHECKER__
+# define __user		__attribute__((noderef, address_space(1)))
+# define __kernel	/* default address space */
+# define __safe		__attribute__((safe))
+# define __force	__attribute__((force))
+# define __nocast	__attribute__((nocast))
+# define __iomem	__attribute__((noderef, address_space(2)))
+# define __acquires(x)	__attribute__((context(x,0,1)))
+# define __releases(x)	__attribute__((context(x,1,0)))
+# define __acquire(x)	__context__(x,1)
+# define __release(x)	__context__(x,-1)
+# define __cond_lock(x,c)	((c) ? ({ __acquire(x); 1; }) : 0)
+extern void __chk_user_ptr(const volatile void __user *);
+extern void __chk_io_ptr(const volatile void __iomem *);
+#else
+# define __user
+# define __kernel
+# define __safe
+# define __force
+# define __nocast
+# define __iomem
+# define __chk_user_ptr(x) (void)0
+# define __chk_io_ptr(x) (void)0
+# define __builtin_warning(x, y...) (1)
+# define __acquires(x)
+# define __releases(x)
+# define __acquire(x) (void)0
+# define __release(x) (void)0
+# define __cond_lock(x,c) (c)
+#endif
+
+#ifdef __KERNEL__
+
+#ifdef __GNUC__
+#include <linux/compiler-gcc.h>
+#endif
+
+#define notrace __attribute__((no_instrument_function))
+
+/* Intel compiler defines __GNUC__. So we will overwrite implementations
+ * coming from above header files here
+ */
+#ifdef __INTEL_COMPILER
+# include <linux/compiler-intel.h>
+#endif
+
+/*
+ * Generic compiler-dependent macros required for kernel
+ * build go below this comment. Actual compiler/compiler version
+ * specific implementations come from the above header files
+ */
+
+struct ftrace_branch_data {
+	const char *func;
+	const char *file;
+	unsigned line;
+	union {
+		struct {
+			unsigned long correct;
+			unsigned long incorrect;
+		};
+		struct {
+			unsigned long miss;
+			unsigned long hit;
+		};
+		unsigned long miss_hit[2];
+	};
+};
+
+/*
+ * Note: DISABLE_BRANCH_PROFILING can be used by special lowlevel code
+ * to disable branch tracing on a per file basis.
+ */
+#if defined(CONFIG_TRACE_BRANCH_PROFILING) \
+    && !defined(DISABLE_BRANCH_PROFILING) && !defined(__CHECKER__)
+void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect);
+
+#define likely_notrace(x)	__builtin_expect(!!(x), 1)
+#define unlikely_notrace(x)	__builtin_expect(!!(x), 0)
+
+#define __branch_check__(x, expect) ({					\
+			int ______r;					\
+			static struct ftrace_branch_data		\
+				__attribute__((__aligned__(4)))		\
+				__attribute__((section("_ftrace_annotated_branch"))) \
+				______f = {				\
+				.func = __func__,			\
+				.file = __FILE__,			\
+				.line = __LINE__,			\
+			};						\
+			______r = likely_notrace(x);			\
+			ftrace_likely_update(&______f, ______r, expect); \
+			______r;					\
+		})
+
+/*
+ * Using __builtin_constant_p(x) to ignore cases where the return
+ * value is always the same.  This idea is taken from a similar patch
+ * written by Daniel Walker.
+ */
+# ifndef likely
+#  define likely(x)	(__builtin_constant_p(x) ? !!(x) : __branch_check__(x, 1))
+# endif
+# ifndef unlikely
+#  define unlikely(x)	(__builtin_constant_p(x) ? !!(x) : __branch_check__(x, 0))
+# endif
+
+#ifdef CONFIG_PROFILE_ALL_BRANCHES
+/*
+ * "Define 'is'", Bill Clinton
+ * "Define 'if'", Steven Rostedt
+ */
+#define if(cond, ...) __trace_if( (cond , ## __VA_ARGS__) )
+#define __trace_if(cond) \
+	if (__builtin_constant_p((cond)) ? !!(cond) :			\
+	({								\
+		int ______r;						\
+		static struct ftrace_branch_data			\
+			__attribute__((__aligned__(4)))			\
+			__attribute__((section("_ftrace_branch")))	\
+			______f = {					\
+				.func = __func__,			\
+				.file = __FILE__,			\
+				.line = __LINE__,			\
+			};						\
+		______r = !!(cond);					\
+		______f.miss_hit[______r]++;					\
+		______r;						\
+	}))
+#endif /* CONFIG_PROFILE_ALL_BRANCHES */
+
+#else
+# define likely(x)	__builtin_expect(!!(x), 1)
+# define unlikely(x)	__builtin_expect(!!(x), 0)
+#endif
+
+/* Optimization barrier */
+#ifndef barrier
+# define barrier() __memory_barrier()
+#endif
+
+/* Unreachable code */
+#ifndef unreachable
+# define unreachable() do { } while (1)
+#endif
+
+#ifndef RELOC_HIDE
+# define RELOC_HIDE(ptr, off)					\
+  ({ unsigned long __ptr;					\
+     __ptr = (unsigned long) (ptr);				\
+    (typeof(ptr)) (__ptr + (off)); })
+#endif
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASSEMBLY__ */
+
+#ifdef __KERNEL__
+/*
+ * Allow us to mark functions as 'deprecated' and have gcc emit a nice
+ * warning for each use, in hopes of speeding the functions removal.
+ * Usage is:
+ * 		int __deprecated foo(void)
+ */
+#ifndef __deprecated
+# define __deprecated		/* unimplemented */
+#endif
+
+#ifdef MODULE
+#define __deprecated_for_modules __deprecated
+#else
+#define __deprecated_for_modules
+#endif
+
+#ifndef __must_check
+#define __must_check
+#endif
+
+#ifndef CONFIG_ENABLE_MUST_CHECK
+#undef __must_check
+#define __must_check
+#endif
+#ifndef CONFIG_ENABLE_WARN_DEPRECATED
+#undef __deprecated
+#undef __deprecated_for_modules
+#define __deprecated
+#define __deprecated_for_modules
+#endif
+
+/*
+ * Allow us to avoid 'defined but not used' warnings on functions and data,
+ * as well as force them to be emitted to the assembly file.
+ *
+ * As of gcc 3.4, static functions that are not marked with attribute((used))
+ * may be elided from the assembly file.  As of gcc 3.4, static data not so
+ * marked will not be elided, but this may change in a future gcc version.
+ *
+ * NOTE: Because distributions shipped with a backported unit-at-a-time
+ * compiler in gcc 3.3, we must define __used to be __attribute__((used))
+ * for gcc >=3.3 instead of 3.4.
+ *
+ * In prior versions of gcc, such functions and data would be emitted, but
+ * would be warned about except with attribute((unused)).
+ *
+ * Mark functions that are referenced only in inline assembly as __used so
+ * the code is emitted even though it appears to be unreferenced.
+ */
+#ifndef __used
+# define __used			/* unimplemented */
+#endif
+
+#ifndef __maybe_unused
+# define __maybe_unused		/* unimplemented */
+#endif
+
+#ifndef __always_unused
+# define __always_unused	/* unimplemented */
+#endif
+
+#ifndef noinline
+#define noinline
+#endif
+
+/*
+ * Rather then using noinline to prevent stack consumption, use
+ * noinline_for_stack instead.  For documentaiton reasons.
+ */
+#define noinline_for_stack noinline
+
+#ifndef __always_inline
+#define __always_inline inline
+#endif
+
+#endif /* __KERNEL__ */
+
+/*
+ * From the GCC manual:
+ *
+ * Many functions do not examine any values except their arguments,
+ * and have no effects except the return value.  Basically this is
+ * just slightly more strict class than the `pure' attribute above,
+ * since function is not allowed to read global memory.
+ *
+ * Note that a function that has pointer arguments and examines the
+ * data pointed to must _not_ be declared `const'.  Likewise, a
+ * function that calls a non-`const' function usually must not be
+ * `const'.  It does not make sense for a `const' function to return
+ * `void'.
+ */
+#ifndef __attribute_const__
+# define __attribute_const__	/* unimplemented */
+#endif
+
+/*
+ * Tell gcc if a function is cold. The compiler will assume any path
+ * directly leading to the call is unlikely.
+ */
+
+#ifndef __cold
+#define __cold
+#endif
+
+/* Simple shorthand for a section definition */
+#ifndef __section
+# define __section(S) __attribute__ ((__section__(#S)))
+#endif
+
+/* Are two types/vars the same type (ignoring qualifiers)? */
+#ifndef __same_type
+# define __same_type(a, b) __builtin_types_compatible_p(typeof(a), typeof(b))
+#endif
+
+/* Compile time object size, -1 for unknown */
+#ifndef __compiletime_object_size
+# define __compiletime_object_size(obj) -1
+#endif
+#ifndef __compiletime_warning
+# define __compiletime_warning(message)
+#endif
+#ifndef __compiletime_error
+# define __compiletime_error(message)
+#endif
+
+/*
+ * Prevent the compiler from merging or refetching accesses.  The compiler
+ * is also forbidden from reordering successive instances of ACCESS_ONCE(),
+ * but only when the compiler is aware of some particular ordering.  One way
+ * to make the compiler aware of ordering is to put the two invocations of
+ * ACCESS_ONCE() in different C statements.
+ *
+ * This macro does absolutely -nothing- to prevent the CPU from reordering,
+ * merging, or refetching absolutely anything at any time.  Its main intended
+ * use is to mediate communication between process-level code and irq/NMI
+ * handlers, all running on the same CPU.
+ */
+#define ACCESS_ONCE(x) (*(volatile typeof(x) *)&(x))
+
+#endif /* __LINUX_COMPILER_H */
diff --git a/qemu/roms/u-boot/include/linux/crc32.h b/qemu/roms/u-boot/include/linux/crc32.h
new file mode 100644
index 000000000..ac4aed1c7
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/crc32.h
@@ -0,0 +1,27 @@
+/*
+ * crc32.h
+ * See linux/lib/crc32.c for license and changes
+ */
+#ifndef _LINUX_CRC32_H
+#define _LINUX_CRC32_H
+
+#include <linux/types.h>
+/* #include <linux/bitrev.h> */
+
+extern u32  crc32_le(u32 crc, unsigned char const *p, size_t len);
+/* extern u32  crc32_be(u32 crc, unsigned char const *p, size_t len); */
+
+#define crc32(seed, data, length)  crc32_le(seed, (unsigned char const *)data, length)
+
+/*
+ * Helpers for hash table generation of ethernet nics:
+ *
+ * Ethernet sends the least significant bit of a byte first, thus crc32_le
+ * is used. The output of crc32_le is bit reversed [most significant bit
+ * is in bit nr 0], thus it must be reversed before use. Except for
+ * nics that bit swap the result internally...
+ */
+/* #define ether_crc(length, data)    bitrev32(crc32_le(~0, data, length)) */
+/* #define ether_crc_le(length, data) crc32_le(~0, data, length) */
+
+#endif /* _LINUX_CRC32_H */
diff --git a/qemu/roms/u-boot/include/linux/crc7.h b/qemu/roms/u-boot/include/linux/crc7.h
new file mode 100644
index 000000000..1786e772d
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/crc7.h
@@ -0,0 +1,14 @@
+#ifndef _LINUX_CRC7_H
+#define _LINUX_CRC7_H
+#include <linux/types.h>
+
+extern const u8 crc7_syndrome_table[256];
+
+static inline u8 crc7_byte(u8 crc, u8 data)
+{
+	return crc7_syndrome_table[(crc << 1) ^ data];
+}
+
+extern u8 crc7(u8 crc, const u8 *buffer, size_t len);
+
+#endif
diff --git a/qemu/roms/u-boot/include/linux/crc8.h b/qemu/roms/u-boot/include/linux/crc8.h
new file mode 100644
index 000000000..b5fd2ac9d
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/crc8.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+
+#ifndef __linux_crc8_h
+#define __linux_crc8_h
+
+/**
+ * crc8() - Calculate and return CRC-8 of the data
+ *
+ * This uses an x^8 + x^2 + x + 1 polynomial.  A table-based algorithm would
+ * be faster, but for only a few bytes it isn't worth the code size
+ *
+ * @vptr: Buffer to checksum
+ * @len: Length of buffer in bytes
+ * @return CRC8 checksum
+ */
+unsigned int crc8(const unsigned char *vptr, int len);
+
+#endif
diff --git a/qemu/roms/u-boot/include/linux/ctype.h b/qemu/roms/u-boot/include/linux/ctype.h
new file mode 100644
index 000000000..42f9305a0
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/ctype.h
@@ -0,0 +1,60 @@
+#ifndef _LINUX_CTYPE_H
+#define _LINUX_CTYPE_H
+
+/*
+ * NOTE! This ctype does not handle EOF like the standard C
+ * library is required to.
+ */
+
+#define _U	0x01	/* upper */
+#define _L	0x02	/* lower */
+#define _D	0x04	/* digit */
+#define _C	0x08	/* cntrl */
+#define _P	0x10	/* punct */
+#define _S	0x20	/* white space (space/lf/tab) */
+#define _X	0x40	/* hex digit */
+#define _SP	0x80	/* hard space (0x20) */
+
+extern const unsigned char _ctype[];
+
+#define __ismask(x) (_ctype[(int)(unsigned char)(x)])
+
+#define isalnum(c)	((__ismask(c)&(_U|_L|_D)) != 0)
+#define isalpha(c)	((__ismask(c)&(_U|_L)) != 0)
+#define iscntrl(c)	((__ismask(c)&(_C)) != 0)
+#define isdigit(c)	((__ismask(c)&(_D)) != 0)
+#define isgraph(c)	((__ismask(c)&(_P|_U|_L|_D)) != 0)
+#define islower(c)	((__ismask(c)&(_L)) != 0)
+#define isprint(c)	((__ismask(c)&(_P|_U|_L|_D|_SP)) != 0)
+#define ispunct(c)	((__ismask(c)&(_P)) != 0)
+#define isspace(c)	((__ismask(c)&(_S)) != 0)
+#define isupper(c)	((__ismask(c)&(_U)) != 0)
+#define isxdigit(c)	((__ismask(c)&(_D|_X)) != 0)
+
+/*
+ * Rather than doubling the size of the _ctype lookup table to hold a 'blank'
+ * flag, just check for space or tab.
+ */
+#define isblank(c)	(c == ' ' || c == '\t')
+
+#define isascii(c) (((unsigned char)(c))<=0x7f)
+#define toascii(c) (((unsigned char)(c))&0x7f)
+
+static inline unsigned char __tolower(unsigned char c)
+{
+	if (isupper(c))
+		c -= 'A'-'a';
+	return c;
+}
+
+static inline unsigned char __toupper(unsigned char c)
+{
+	if (islower(c))
+		c -= 'a'-'A';
+	return c;
+}
+
+#define tolower(c) __tolower(c)
+#define toupper(c) __toupper(c)
+
+#endif
diff --git a/qemu/roms/u-boot/include/linux/edd.h b/qemu/roms/u-boot/include/linux/edd.h
new file mode 100644
index 000000000..4cbd0fe9d
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/edd.h
@@ -0,0 +1,194 @@
+/*
+ * linux/include/linux/edd.h
+ *  Copyright (C) 2002, 2003, 2004 Dell Inc.
+ *  by Matt Domsch <Matt_Domsch@dell.com>
+ *
+ * structures and definitions for the int 13h, ax={41,48}h
+ * BIOS Enhanced Disk Drive Services
+ * This is based on the T13 group document D1572 Revision 0 (August 14 2002)
+ * available at http://www.t13.org/docs2002/d1572r0.pdf.  It is
+ * very similar to D1484 Revision 3 http://www.t13.org/docs2002/d1484r3.pdf
+ *
+ * In a nutshell, arch/{i386,x86_64}/boot/setup.S populates a scratch
+ * table in the boot_params that contains a list of BIOS-enumerated
+ * boot devices.
+ * In arch/{i386,x86_64}/kernel/setup.c, this information is
+ * transferred into the edd structure, and in drivers/firmware/edd.c, that
+ * information is used to identify BIOS boot disk.  The code in setup.S
+ * is very sensitive to the size of these structures.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License v2.0 as published by
+ * the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef _LINUX_EDD_H
+#define _LINUX_EDD_H
+
+#include <linux/types.h>
+
+#define EDDNR 0x1e9		/* addr of number of edd_info structs at EDDBUF
+				   in boot_params - treat this as 1 byte  */
+#define EDDBUF	0xd00		/* addr of edd_info structs in boot_params */
+#define EDDMAXNR 6		/* number of edd_info structs starting at EDDBUF  */
+#define EDDEXTSIZE 8		/* change these if you muck with the structures */
+#define EDDPARMSIZE 74
+#define CHECKEXTENSIONSPRESENT 0x41
+#define GETDEVICEPARAMETERS 0x48
+#define LEGACYGETDEVICEPARAMETERS 0x08
+#define EDDMAGIC1 0x55AA
+#define EDDMAGIC2 0xAA55
+
+
+#define READ_SECTORS 0x02         /* int13 AH=0x02 is READ_SECTORS command */
+#define EDD_MBR_SIG_OFFSET 0x1B8  /* offset of signature in the MBR */
+#define EDD_MBR_SIG_BUF    0x290  /* addr in boot params */
+#define EDD_MBR_SIG_MAX 16        /* max number of signatures to store */
+#define EDD_MBR_SIG_NR_BUF 0x1ea  /* addr of number of MBR signtaures at EDD_MBR_SIG_BUF
+				     in boot_params - treat this as 1 byte  */
+
+#ifndef __ASSEMBLY__
+
+#define EDD_EXT_FIXED_DISK_ACCESS           (1 << 0)
+#define EDD_EXT_DEVICE_LOCKING_AND_EJECTING (1 << 1)
+#define EDD_EXT_ENHANCED_DISK_DRIVE_SUPPORT (1 << 2)
+#define EDD_EXT_64BIT_EXTENSIONS            (1 << 3)
+
+#define EDD_INFO_DMA_BOUNDARY_ERROR_TRANSPARENT (1 << 0)
+#define EDD_INFO_GEOMETRY_VALID                (1 << 1)
+#define EDD_INFO_REMOVABLE                     (1 << 2)
+#define EDD_INFO_WRITE_VERIFY                  (1 << 3)
+#define EDD_INFO_MEDIA_CHANGE_NOTIFICATION     (1 << 4)
+#define EDD_INFO_LOCKABLE                      (1 << 5)
+#define EDD_INFO_NO_MEDIA_PRESENT              (1 << 6)
+#define EDD_INFO_USE_INT13_FN50                (1 << 7)
+
+struct edd_device_params {
+	__u16 length;
+	__u16 info_flags;
+	__u32 num_default_cylinders;
+	__u32 num_default_heads;
+	__u32 sectors_per_track;
+	__u64 number_of_sectors;
+	__u16 bytes_per_sector;
+	__u32 dpte_ptr;		/* 0xFFFFFFFF for our purposes */
+	__u16 key;		/* = 0xBEDD */
+	__u8 device_path_info_length;	/* = 44 */
+	__u8 reserved2;
+	__u16 reserved3;
+	__u8 host_bus_type[4];
+	__u8 interface_type[8];
+	union {
+		struct {
+			__u16 base_address;
+			__u16 reserved1;
+			__u32 reserved2;
+		} __attribute__ ((packed)) isa;
+		struct {
+			__u8 bus;
+			__u8 slot;
+			__u8 function;
+			__u8 channel;
+			__u32 reserved;
+		} __attribute__ ((packed)) pci;
+		/* pcix is same as pci */
+		struct {
+			__u64 reserved;
+		} __attribute__ ((packed)) ibnd;
+		struct {
+			__u64 reserved;
+		} __attribute__ ((packed)) xprs;
+		struct {
+			__u64 reserved;
+		} __attribute__ ((packed)) htpt;
+		struct {
+			__u64 reserved;
+		} __attribute__ ((packed)) unknown;
+	} interface_path;
+	union {
+		struct {
+			__u8 device;
+			__u8 reserved1;
+			__u16 reserved2;
+			__u32 reserved3;
+			__u64 reserved4;
+		} __attribute__ ((packed)) ata;
+		struct {
+			__u8 device;
+			__u8 lun;
+			__u8 reserved1;
+			__u8 reserved2;
+			__u32 reserved3;
+			__u64 reserved4;
+		} __attribute__ ((packed)) atapi;
+		struct {
+			__u16 id;
+			__u64 lun;
+			__u16 reserved1;
+			__u32 reserved2;
+		} __attribute__ ((packed)) scsi;
+		struct {
+			__u64 serial_number;
+			__u64 reserved;
+		} __attribute__ ((packed)) usb;
+		struct {
+			__u64 eui;
+			__u64 reserved;
+		} __attribute__ ((packed)) i1394;
+		struct {
+			__u64 wwid;
+			__u64 lun;
+		} __attribute__ ((packed)) fibre;
+		struct {
+			__u64 identity_tag;
+			__u64 reserved;
+		} __attribute__ ((packed)) i2o;
+		struct {
+			__u32 array_number;
+			__u32 reserved1;
+			__u64 reserved2;
+		} __attribute__ ((packed)) raid;
+		struct {
+			__u8 device;
+			__u8 reserved1;
+			__u16 reserved2;
+			__u32 reserved3;
+			__u64 reserved4;
+		} __attribute__ ((packed)) sata;
+		struct {
+			__u64 reserved1;
+			__u64 reserved2;
+		} __attribute__ ((packed)) unknown;
+	} device_path;
+	__u8 reserved4;
+	__u8 checksum;
+} __attribute__ ((packed));
+
+struct edd_info {
+	__u8 device;
+	__u8 version;
+	__u16 interface_support;
+	__u16 legacy_max_cylinder;
+	__u8 legacy_max_head;
+	__u8 legacy_sectors_per_track;
+	struct edd_device_params params;
+} __attribute__ ((packed));
+
+struct edd {
+	unsigned int mbr_signature[EDD_MBR_SIG_MAX];
+	struct edd_info edd_info[EDDMAXNR];
+	unsigned char mbr_signature_nr;
+	unsigned char edd_info_nr;
+};
+
+#ifdef __KERNEL__
+extern struct edd edd;
+#endif /* __KERNEL__ */
+#endif				/*!__ASSEMBLY__ */
+
+#endif				/* _LINUX_EDD_H */
diff --git a/qemu/roms/u-boot/include/linux/err.h b/qemu/roms/u-boot/include/linux/err.h
new file mode 100644
index 000000000..96c0c72ba
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/err.h
@@ -0,0 +1,45 @@
+#ifndef _LINUX_ERR_H
+#define _LINUX_ERR_H
+
+/* XXX U-BOOT XXX */
+#if 0
+#include <linux/compiler.h>
+#else
+#include <linux/compat.h>
+#endif
+
+#include <asm/errno.h>
+
+
+/*
+ * Kernel pointers have redundant information, so we can use a
+ * scheme where we can return either an error code or a dentry
+ * pointer with the same return value.
+ *
+ * This should be a per-architecture thing, to allow different
+ * error and pointer decisions.
+ */
+#define MAX_ERRNO	4095
+
+#ifndef __ASSEMBLY__
+
+#define IS_ERR_VALUE(x) unlikely((x) >= (unsigned long)-MAX_ERRNO)
+
+static inline void *ERR_PTR(long error)
+{
+	return (void *) error;
+}
+
+static inline long PTR_ERR(const void *ptr)
+{
+	return (long) ptr;
+}
+
+static inline long IS_ERR(const void *ptr)
+{
+	return IS_ERR_VALUE((unsigned long)ptr);
+}
+
+#endif
+
+#endif /* _LINUX_ERR_H */
diff --git a/qemu/roms/u-boot/include/linux/ethtool.h b/qemu/roms/u-boot/include/linux/ethtool.h
new file mode 100644
index 000000000..f6dbdb096
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/ethtool.h
@@ -0,0 +1,725 @@
+/*
+ * ethtool.h: Defines for Linux ethtool.
+ *
+ * Copyright (C) 1998 David S. Miller (davem@redhat.com)
+ * Copyright 2001 Jeff Garzik <jgarzik@pobox.com>
+ * Portions Copyright 2001 Sun Microsystems (thockin@sun.com)
+ * Portions Copyright 2002 Intel (eli.kupermann@intel.com,
+ *                                christopher.leech@intel.com,
+ *                                scott.feldman@intel.com)
+ * Portions Copyright (C) Sun Microsystems 2008
+ */
+
+#ifndef _LINUX_ETHTOOL_H
+#define _LINUX_ETHTOOL_H
+
+#include <linux/types.h>
+
+/* This should work for both 32 and 64 bit userland. */
+struct ethtool_cmd {
+	__u32	cmd;
+	__u32	supported;	/* Features this interface supports */
+	__u32	advertising;	/* Features this interface advertises */
+	__u16	speed;		/* The forced speed, 10Mb, 100Mb, gigabit */
+	__u8	duplex;		/* Duplex, half or full */
+	__u8	port;		/* Which connector port */
+	__u8	phy_address;
+	__u8	transceiver;	/* Which transceiver to use */
+	__u8	autoneg;	/* Enable or disable autonegotiation */
+	__u8	mdio_support;
+	__u32	maxtxpkt;	/* Tx pkts before generating tx int */
+	__u32	maxrxpkt;	/* Rx pkts before generating rx int */
+	__u16	speed_hi;
+	__u8	eth_tp_mdix;
+	__u8	reserved2;
+	__u32	lp_advertising;	/* Features the link partner advertises */
+	__u32	reserved[2];
+};
+
+static inline void ethtool_cmd_speed_set(struct ethtool_cmd *ep,
+						__u32 speed)
+{
+
+	ep->speed = (__u16)speed;
+	ep->speed_hi = (__u16)(speed >> 16);
+}
+
+static inline __u32 ethtool_cmd_speed(struct ethtool_cmd *ep)
+{
+	return (ep->speed_hi << 16) | ep->speed;
+}
+
+#define ETHTOOL_FWVERS_LEN	32
+#define ETHTOOL_BUSINFO_LEN	32
+/* these strings are set to whatever the driver author decides... */
+struct ethtool_drvinfo {
+	__u32	cmd;
+	char	driver[32];	/* driver short name, "tulip", "eepro100" */
+	char	version[32];	/* driver version string */
+	char	fw_version[ETHTOOL_FWVERS_LEN];	/* firmware version string */
+	char	bus_info[ETHTOOL_BUSINFO_LEN];	/* Bus info for this IF. */
+				/* For PCI devices, use pci_name(pci_dev). */
+	char	reserved1[32];
+	char	reserved2[12];
+				/*
+				 * Some struct members below are filled in
+				 * using ops->get_sset_count().  Obtaining
+				 * this info from ethtool_drvinfo is now
+				 * deprecated; Use ETHTOOL_GSSET_INFO
+				 * instead.
+				 */
+	__u32	n_priv_flags;	/* number of flags valid in ETHTOOL_GPFLAGS */
+	__u32	n_stats;	/* number of u64's from ETHTOOL_GSTATS */
+	__u32	testinfo_len;
+	__u32	eedump_len;	/* Size of data from ETHTOOL_GEEPROM (bytes) */
+	__u32	regdump_len;	/* Size of data from ETHTOOL_GREGS (bytes) */
+};
+
+#define SOPASS_MAX	6
+/* wake-on-lan settings */
+struct ethtool_wolinfo {
+	__u32	cmd;
+	__u32	supported;
+	__u32	wolopts;
+	__u8	sopass[SOPASS_MAX]; /* SecureOn(tm) password */
+};
+
+/* for passing single values */
+struct ethtool_value {
+	__u32	cmd;
+	__u32	data;
+};
+
+/* for passing big chunks of data */
+struct ethtool_regs {
+	__u32	cmd;
+	__u32	version; /* driver-specific, indicates different chips/revs */
+	__u32	len; /* bytes */
+	__u8	data[0];
+};
+
+/* for passing EEPROM chunks */
+struct ethtool_eeprom {
+	__u32	cmd;
+	__u32	magic;
+	__u32	offset; /* in bytes */
+	__u32	len; /* in bytes */
+	__u8	data[0];
+};
+
+/* for configuring coalescing parameters of chip */
+struct ethtool_coalesce {
+	__u32	cmd;	/* ETHTOOL_{G,S}COALESCE */
+
+	/* How many usecs to delay an RX interrupt after
+	 * a packet arrives.  If 0, only rx_max_coalesced_frames
+	 * is used.
+	 */
+	__u32	rx_coalesce_usecs;
+
+	/* How many packets to delay an RX interrupt after
+	 * a packet arrives.  If 0, only rx_coalesce_usecs is
+	 * used.  It is illegal to set both usecs and max frames
+	 * to zero as this would cause RX interrupts to never be
+	 * generated.
+	 */
+	__u32	rx_max_coalesced_frames;
+
+	/* Same as above two parameters, except that these values
+	 * apply while an IRQ is being serviced by the host.  Not
+	 * all cards support this feature and the values are ignored
+	 * in that case.
+	 */
+	__u32	rx_coalesce_usecs_irq;
+	__u32	rx_max_coalesced_frames_irq;
+
+	/* How many usecs to delay a TX interrupt after
+	 * a packet is sent.  If 0, only tx_max_coalesced_frames
+	 * is used.
+	 */
+	__u32	tx_coalesce_usecs;
+
+	/* How many packets to delay a TX interrupt after
+	 * a packet is sent.  If 0, only tx_coalesce_usecs is
+	 * used.  It is illegal to set both usecs and max frames
+	 * to zero as this would cause TX interrupts to never be
+	 * generated.
+	 */
+	__u32	tx_max_coalesced_frames;
+
+	/* Same as above two parameters, except that these values
+	 * apply while an IRQ is being serviced by the host.  Not
+	 * all cards support this feature and the values are ignored
+	 * in that case.
+	 */
+	__u32	tx_coalesce_usecs_irq;
+	__u32	tx_max_coalesced_frames_irq;
+
+	/* How many usecs to delay in-memory statistics
+	 * block updates.  Some drivers do not have an in-memory
+	 * statistic block, and in such cases this value is ignored.
+	 * This value must not be zero.
+	 */
+	__u32	stats_block_coalesce_usecs;
+
+	/* Adaptive RX/TX coalescing is an algorithm implemented by
+	 * some drivers to improve latency under low packet rates and
+	 * improve throughput under high packet rates.  Some drivers
+	 * only implement one of RX or TX adaptive coalescing.  Anything
+	 * not implemented by the driver causes these values to be
+	 * silently ignored.
+	 */
+	__u32	use_adaptive_rx_coalesce;
+	__u32	use_adaptive_tx_coalesce;
+
+	/* When the packet rate (measured in packets per second)
+	 * is below pkt_rate_low, the {rx,tx}_*_low parameters are
+	 * used.
+	 */
+	__u32	pkt_rate_low;
+	__u32	rx_coalesce_usecs_low;
+	__u32	rx_max_coalesced_frames_low;
+	__u32	tx_coalesce_usecs_low;
+	__u32	tx_max_coalesced_frames_low;
+
+	/* When the packet rate is below pkt_rate_high but above
+	 * pkt_rate_low (both measured in packets per second) the
+	 * normal {rx,tx}_* coalescing parameters are used.
+	 */
+
+	/* When the packet rate is (measured in packets per second)
+	 * is above pkt_rate_high, the {rx,tx}_*_high parameters are
+	 * used.
+	 */
+	__u32	pkt_rate_high;
+	__u32	rx_coalesce_usecs_high;
+	__u32	rx_max_coalesced_frames_high;
+	__u32	tx_coalesce_usecs_high;
+	__u32	tx_max_coalesced_frames_high;
+
+	/* How often to do adaptive coalescing packet rate sampling,
+	 * measured in seconds.  Must not be zero.
+	 */
+	__u32	rate_sample_interval;
+};
+
+/* for configuring RX/TX ring parameters */
+struct ethtool_ringparam {
+	__u32	cmd;	/* ETHTOOL_{G,S}RINGPARAM */
+
+	/* Read only attributes.  These indicate the maximum number
+	 * of pending RX/TX ring entries the driver will allow the
+	 * user to set.
+	 */
+	__u32	rx_max_pending;
+	__u32	rx_mini_max_pending;
+	__u32	rx_jumbo_max_pending;
+	__u32	tx_max_pending;
+
+	/* Values changeable by the user.  The valid values are
+	 * in the range 1 to the "*_max_pending" counterpart above.
+	 */
+	__u32	rx_pending;
+	__u32	rx_mini_pending;
+	__u32	rx_jumbo_pending;
+	__u32	tx_pending;
+};
+
+/* for configuring link flow control parameters */
+struct ethtool_pauseparam {
+	__u32	cmd;	/* ETHTOOL_{G,S}PAUSEPARAM */
+
+	/* If the link is being auto-negotiated (via ethtool_cmd.autoneg
+	 * being true) the user may set 'autonet' here non-zero to have the
+	 * pause parameters be auto-negotiated too.  In such a case, the
+	 * {rx,tx}_pause values below determine what capabilities are
+	 * advertised.
+	 *
+	 * If 'autoneg' is zero or the link is not being auto-negotiated,
+	 * then {rx,tx}_pause force the driver to use/not-use pause
+	 * flow control.
+	 */
+	__u32	autoneg;
+	__u32	rx_pause;
+	__u32	tx_pause;
+};
+
+#define ETH_GSTRING_LEN		32
+enum ethtool_stringset {
+	ETH_SS_TEST		= 0,
+	ETH_SS_STATS,
+	ETH_SS_PRIV_FLAGS,
+	ETH_SS_NTUPLE_FILTERS,
+	ETH_SS_FEATURES,
+};
+
+/* for passing string sets for data tagging */
+struct ethtool_gstrings {
+	__u32	cmd;		/* ETHTOOL_GSTRINGS */
+	__u32	string_set;	/* string set id e.c. ETH_SS_TEST, etc*/
+	__u32	len;		/* number of strings in the string set */
+	__u8	data[0];
+};
+
+struct ethtool_sset_info {
+	__u32	cmd;		/* ETHTOOL_GSSET_INFO */
+	__u32	reserved;
+	__u64	sset_mask;	/* input: each bit selects an sset to query */
+				/* output: each bit a returned sset */
+	__u32	data[0];	/* ETH_SS_xxx count, in order, based on bits
+				   in sset_mask.  One bit implies one
+				   __u32, two bits implies two
+				   __u32's, etc. */
+};
+
+enum ethtool_test_flags {
+	ETH_TEST_FL_OFFLINE	= (1 << 0),	/* online / offline */
+	ETH_TEST_FL_FAILED	= (1 << 1),	/* test passed / failed */
+};
+
+/* for requesting NIC test and getting results*/
+struct ethtool_test {
+	__u32	cmd;		/* ETHTOOL_TEST */
+	__u32	flags;		/* ETH_TEST_FL_xxx */
+	__u32	reserved;
+	__u32	len;		/* result length, in number of u64 elements */
+	__u64	data[0];
+};
+
+/* for dumping NIC-specific statistics */
+struct ethtool_stats {
+	__u32	cmd;		/* ETHTOOL_GSTATS */
+	__u32	n_stats;	/* number of u64's being returned */
+	__u64	data[0];
+};
+
+struct ethtool_perm_addr {
+	__u32	cmd;		/* ETHTOOL_GPERMADDR */
+	__u32	size;
+	__u8	data[0];
+};
+
+/* boolean flags controlling per-interface behavior characteristics.
+ * When reading, the flag indicates whether or not a certain behavior
+ * is enabled/present.  When writing, the flag indicates whether
+ * or not the driver should turn on (set) or off (clear) a behavior.
+ *
+ * Some behaviors may read-only (unconditionally absent or present).
+ * If such is the case, return EINVAL in the set-flags operation if the
+ * flag differs from the read-only value.
+ */
+enum ethtool_flags {
+	ETH_FLAG_TXVLAN		= (1 << 7),	/* TX VLAN offload enabled */
+	ETH_FLAG_RXVLAN		= (1 << 8),	/* RX VLAN offload enabled */
+	ETH_FLAG_LRO		= (1 << 15),	/* LRO is enabled */
+	ETH_FLAG_NTUPLE		= (1 << 27),	/* N-tuple filters enabled */
+	ETH_FLAG_RXHASH		= (1 << 28),
+};
+
+/* The following structures are for supporting RX network flow
+ * classification and RX n-tuple configuration. Note, all multibyte
+ * fields, e.g., ip4src, ip4dst, psrc, pdst, spi, etc. are expected to
+ * be in network byte order.
+ */
+
+/**
+ * struct ethtool_tcpip4_spec - flow specification for TCP/IPv4 etc.
+ * @ip4src: Source host
+ * @ip4dst: Destination host
+ * @psrc: Source port
+ * @pdst: Destination port
+ * @tos: Type-of-service
+ *
+ * This can be used to specify a TCP/IPv4, UDP/IPv4 or SCTP/IPv4 flow.
+ */
+struct ethtool_tcpip4_spec {
+	__be32	ip4src;
+	__be32	ip4dst;
+	__be16	psrc;
+	__be16	pdst;
+	__u8    tos;
+};
+
+/**
+ * struct ethtool_ah_espip4_spec - flow specification for IPsec/IPv4
+ * @ip4src: Source host
+ * @ip4dst: Destination host
+ * @spi: Security parameters index
+ * @tos: Type-of-service
+ *
+ * This can be used to specify an IPsec transport or tunnel over IPv4.
+ */
+struct ethtool_ah_espip4_spec {
+	__be32	ip4src;
+	__be32	ip4dst;
+	__be32	spi;
+	__u8    tos;
+};
+
+#define	ETH_RX_NFC_IP4	1
+
+/**
+ * struct ethtool_usrip4_spec - general flow specification for IPv4
+ * @ip4src: Source host
+ * @ip4dst: Destination host
+ * @l4_4_bytes: First 4 bytes of transport (layer 4) header
+ * @tos: Type-of-service
+ * @ip_ver: Value must be %ETH_RX_NFC_IP4; mask must be 0
+ * @proto: Transport protocol number; mask must be 0
+ */
+struct ethtool_usrip4_spec {
+	__be32	ip4src;
+	__be32	ip4dst;
+	__be32	l4_4_bytes;
+	__u8    tos;
+	__u8    ip_ver;
+	__u8    proto;
+};
+
+
+/**
+ * struct ethtool_rxfh_indir - command to get or set RX flow hash indirection
+ * @cmd: Specific command number - %ETHTOOL_GRXFHINDIR or %ETHTOOL_SRXFHINDIR
+ * @size: On entry, the array size of the user buffer.  On return from
+ *	%ETHTOOL_GRXFHINDIR, the array size of the hardware indirection table.
+ * @ring_index: RX ring/queue index for each hash value
+ */
+struct ethtool_rxfh_indir {
+	__u32	cmd;
+	__u32	size;
+	__u32	ring_index[0];
+};
+
+#define ETHTOOL_FLASH_MAX_FILENAME	128
+enum ethtool_flash_op_type {
+	ETHTOOL_FLASH_ALL_REGIONS	= 0,
+};
+
+/* for passing firmware flashing related parameters */
+struct ethtool_flash {
+	__u32	cmd;
+	__u32	region;
+	char	data[ETHTOOL_FLASH_MAX_FILENAME];
+};
+
+/* for returning and changing feature sets */
+
+/**
+ * struct ethtool_get_features_block - block with state of 32 features
+ * @available: mask of changeable features
+ * @requested: mask of features requested to be enabled if possible
+ * @active: mask of currently enabled features
+ * @never_changed: mask of features not changeable for any device
+ */
+struct ethtool_get_features_block {
+	__u32	available;
+	__u32	requested;
+	__u32	active;
+	__u32	never_changed;
+};
+
+/**
+ * struct ethtool_gfeatures - command to get state of device's features
+ * @cmd: command number = %ETHTOOL_GFEATURES
+ * @size: in: number of elements in the features[] array;
+ *       out: number of elements in features[] needed to hold all features
+ * @features: state of features
+ */
+struct ethtool_gfeatures {
+	__u32	cmd;
+	__u32	size;
+	struct ethtool_get_features_block features[0];
+};
+
+/**
+ * struct ethtool_set_features_block - block with request for 32 features
+ * @valid: mask of features to be changed
+ * @requested: values of features to be changed
+ */
+struct ethtool_set_features_block {
+	__u32	valid;
+	__u32	requested;
+};
+
+/**
+ * struct ethtool_sfeatures - command to request change in device's features
+ * @cmd: command number = %ETHTOOL_SFEATURES
+ * @size: array size of the features[] array
+ * @features: feature change masks
+ */
+struct ethtool_sfeatures {
+	__u32	cmd;
+	__u32	size;
+	struct ethtool_set_features_block features[0];
+};
+
+/*
+ * %ETHTOOL_SFEATURES changes features present in features[].valid to the
+ * values of corresponding bits in features[].requested. Bits in .requested
+ * not set in .valid or not changeable are ignored.
+ *
+ * Returns %EINVAL when .valid contains undefined or never-changable bits
+ * or size is not equal to required number of features words (32-bit blocks).
+ * Returns >= 0 if request was completed; bits set in the value mean:
+ *   %ETHTOOL_F_UNSUPPORTED - there were bits set in .valid that are not
+ *	changeable (not present in %ETHTOOL_GFEATURES' features[].available)
+ *	those bits were ignored.
+ *   %ETHTOOL_F_WISH - some or all changes requested were recorded but the
+ *      resulting state of bits masked by .valid is not equal to .requested.
+ *      Probably there are other device-specific constraints on some features
+ *      in the set. When %ETHTOOL_F_UNSUPPORTED is set, .valid is considered
+ *      here as though ignored bits were cleared.
+ *   %ETHTOOL_F_COMPAT - some or all changes requested were made by calling
+ *      compatibility functions. Requested offload state cannot be properly
+ *      managed by kernel.
+ *
+ * Meaning of bits in the masks are obtained by %ETHTOOL_GSSET_INFO (number of
+ * bits in the arrays - always multiple of 32) and %ETHTOOL_GSTRINGS commands
+ * for ETH_SS_FEATURES string set. First entry in the table corresponds to least
+ * significant bit in features[0] fields. Empty strings mark undefined features.
+ */
+enum ethtool_sfeatures_retval_bits {
+	ETHTOOL_F_UNSUPPORTED__BIT,
+	ETHTOOL_F_WISH__BIT,
+	ETHTOOL_F_COMPAT__BIT,
+};
+
+#define ETHTOOL_F_UNSUPPORTED   (1 << ETHTOOL_F_UNSUPPORTED__BIT)
+#define ETHTOOL_F_WISH          (1 << ETHTOOL_F_WISH__BIT)
+#define ETHTOOL_F_COMPAT        (1 << ETHTOOL_F_COMPAT__BIT)
+
+/* CMDs currently supported */
+#define ETHTOOL_GSET		0x00000001 /* Get settings. */
+#define ETHTOOL_SSET		0x00000002 /* Set settings. */
+#define ETHTOOL_GDRVINFO	0x00000003 /* Get driver info. */
+#define ETHTOOL_GREGS		0x00000004 /* Get NIC registers. */
+#define ETHTOOL_GWOL		0x00000005 /* Get wake-on-lan options. */
+#define ETHTOOL_SWOL		0x00000006 /* Set wake-on-lan options. */
+#define ETHTOOL_GMSGLVL		0x00000007 /* Get driver message level */
+#define ETHTOOL_SMSGLVL		0x00000008 /* Set driver msg level. */
+#define ETHTOOL_NWAY_RST	0x00000009 /* Restart autonegotiation. */
+/* Get link status for host, i.e. whether the interface *and* the
+ * physical port (if there is one) are up (ethtool_value). */
+#define ETHTOOL_GLINK		0x0000000a
+#define ETHTOOL_GEEPROM		0x0000000b /* Get EEPROM data */
+#define ETHTOOL_SEEPROM		0x0000000c /* Set EEPROM data. */
+#define ETHTOOL_GCOALESCE	0x0000000e /* Get coalesce config */
+#define ETHTOOL_SCOALESCE	0x0000000f /* Set coalesce config. */
+#define ETHTOOL_GRINGPARAM	0x00000010 /* Get ring parameters */
+#define ETHTOOL_SRINGPARAM	0x00000011 /* Set ring parameters. */
+#define ETHTOOL_GPAUSEPARAM	0x00000012 /* Get pause parameters */
+#define ETHTOOL_SPAUSEPARAM	0x00000013 /* Set pause parameters. */
+#define ETHTOOL_GRXCSUM		0x00000014 /* Get RX hw csum enable (ethtool_value) */
+#define ETHTOOL_SRXCSUM		0x00000015 /* Set RX hw csum enable (ethtool_value) */
+#define ETHTOOL_GTXCSUM		0x00000016 /* Get TX hw csum enable (ethtool_value) */
+#define ETHTOOL_STXCSUM		0x00000017 /* Set TX hw csum enable (ethtool_value) */
+#define ETHTOOL_GSG		0x00000018 /* Get scatter-gather enable
+					    * (ethtool_value) */
+#define ETHTOOL_SSG		0x00000019 /* Set scatter-gather enable
+					    * (ethtool_value). */
+#define ETHTOOL_TEST		0x0000001a /* execute NIC self-test. */
+#define ETHTOOL_GSTRINGS	0x0000001b /* get specified string set */
+#define ETHTOOL_PHYS_ID		0x0000001c /* identify the NIC */
+#define ETHTOOL_GSTATS		0x0000001d /* get NIC-specific statistics */
+#define ETHTOOL_GTSO		0x0000001e /* Get TSO enable (ethtool_value) */
+#define ETHTOOL_STSO		0x0000001f /* Set TSO enable (ethtool_value) */
+#define ETHTOOL_GPERMADDR	0x00000020 /* Get permanent hardware address */
+#define ETHTOOL_GUFO		0x00000021 /* Get UFO enable (ethtool_value) */
+#define ETHTOOL_SUFO		0x00000022 /* Set UFO enable (ethtool_value) */
+#define ETHTOOL_GGSO		0x00000023 /* Get GSO enable (ethtool_value) */
+#define ETHTOOL_SGSO		0x00000024 /* Set GSO enable (ethtool_value) */
+#define ETHTOOL_GFLAGS		0x00000025 /* Get flags bitmap(ethtool_value) */
+#define ETHTOOL_SFLAGS		0x00000026 /* Set flags bitmap(ethtool_value) */
+#define ETHTOOL_GPFLAGS		0x00000027 /* Get driver-private flags bitmap */
+#define ETHTOOL_SPFLAGS		0x00000028 /* Set driver-private flags bitmap */
+
+#define ETHTOOL_GRXFH		0x00000029 /* Get RX flow hash configuration */
+#define ETHTOOL_SRXFH		0x0000002a /* Set RX flow hash configuration */
+#define ETHTOOL_GGRO		0x0000002b /* Get GRO enable (ethtool_value) */
+#define ETHTOOL_SGRO		0x0000002c /* Set GRO enable (ethtool_value) */
+#define ETHTOOL_GRXRINGS	0x0000002d /* Get RX rings available for LB */
+#define ETHTOOL_GRXCLSRLCNT	0x0000002e /* Get RX class rule count */
+#define ETHTOOL_GRXCLSRULE	0x0000002f /* Get RX classification rule */
+#define ETHTOOL_GRXCLSRLALL	0x00000030 /* Get all RX classification rule */
+#define ETHTOOL_SRXCLSRLDEL	0x00000031 /* Delete RX classification rule */
+#define ETHTOOL_SRXCLSRLINS	0x00000032 /* Insert RX classification rule */
+#define ETHTOOL_FLASHDEV	0x00000033 /* Flash firmware to device */
+#define ETHTOOL_RESET		0x00000034 /* Reset hardware */
+#define ETHTOOL_SRXNTUPLE	0x00000035 /* Add an n-tuple filter to device */
+#define ETHTOOL_GRXNTUPLE	0x00000036 /* Get n-tuple filters from device */
+#define ETHTOOL_GSSET_INFO	0x00000037 /* Get string set info */
+#define ETHTOOL_GRXFHINDIR	0x00000038 /* Get RX flow hash indir'n table */
+#define ETHTOOL_SRXFHINDIR	0x00000039 /* Set RX flow hash indir'n table */
+
+#define ETHTOOL_GFEATURES	0x0000003a /* Get device offload settings */
+#define ETHTOOL_SFEATURES	0x0000003b /* Change device offload settings */
+
+/* compatibility with older code */
+#define SPARC_ETH_GSET		ETHTOOL_GSET
+#define SPARC_ETH_SSET		ETHTOOL_SSET
+
+/* Indicates what features are supported by the interface. */
+#define SUPPORTED_10baseT_Half		(1 << 0)
+#define SUPPORTED_10baseT_Full		(1 << 1)
+#define SUPPORTED_100baseT_Half		(1 << 2)
+#define SUPPORTED_100baseT_Full		(1 << 3)
+#define SUPPORTED_1000baseT_Half	(1 << 4)
+#define SUPPORTED_1000baseT_Full	(1 << 5)
+#define SUPPORTED_Autoneg		(1 << 6)
+#define SUPPORTED_TP			(1 << 7)
+#define SUPPORTED_AUI			(1 << 8)
+#define SUPPORTED_MII			(1 << 9)
+#define SUPPORTED_FIBRE			(1 << 10)
+#define SUPPORTED_BNC			(1 << 11)
+#define SUPPORTED_10000baseT_Full	(1 << 12)
+#define SUPPORTED_Pause			(1 << 13)
+#define SUPPORTED_Asym_Pause		(1 << 14)
+#define SUPPORTED_2500baseX_Full	(1 << 15)
+#define SUPPORTED_Backplane		(1 << 16)
+#define SUPPORTED_1000baseKX_Full	(1 << 17)
+#define SUPPORTED_10000baseKX4_Full	(1 << 18)
+#define SUPPORTED_10000baseKR_Full	(1 << 19)
+#define SUPPORTED_10000baseR_FEC	(1 << 20)
+#define SUPPORTED_1000baseX_Half	(1 << 21)
+#define SUPPORTED_1000baseX_Full	(1 << 22)
+
+/* Indicates what features are advertised by the interface. */
+#define ADVERTISED_10baseT_Half		(1 << 0)
+#define ADVERTISED_10baseT_Full		(1 << 1)
+#define ADVERTISED_100baseT_Half	(1 << 2)
+#define ADVERTISED_100baseT_Full	(1 << 3)
+#define ADVERTISED_1000baseT_Half	(1 << 4)
+#define ADVERTISED_1000baseT_Full	(1 << 5)
+#define ADVERTISED_Autoneg		(1 << 6)
+#define ADVERTISED_TP			(1 << 7)
+#define ADVERTISED_AUI			(1 << 8)
+#define ADVERTISED_MII			(1 << 9)
+#define ADVERTISED_FIBRE		(1 << 10)
+#define ADVERTISED_BNC			(1 << 11)
+#define ADVERTISED_10000baseT_Full	(1 << 12)
+#define ADVERTISED_Pause		(1 << 13)
+#define ADVERTISED_Asym_Pause		(1 << 14)
+#define ADVERTISED_2500baseX_Full	(1 << 15)
+#define ADVERTISED_Backplane		(1 << 16)
+#define ADVERTISED_1000baseKX_Full	(1 << 17)
+#define ADVERTISED_10000baseKX4_Full	(1 << 18)
+#define ADVERTISED_10000baseKR_Full	(1 << 19)
+#define ADVERTISED_10000baseR_FEC	(1 << 20)
+#define ADVERTISED_1000baseX_Half	(1 << 21)
+#define ADVERTISED_1000baseX_Full	(1 << 22)
+
+/* The following are all involved in forcing a particular link
+ * mode for the device for setting things.  When getting the
+ * devices settings, these indicate the current mode and whether
+ * it was foced up into this mode or autonegotiated.
+ */
+
+/* The forced speed, 10Mb, 100Mb, gigabit, 2.5Gb, 10GbE. */
+#define SPEED_10		10
+#define SPEED_100		100
+#define SPEED_1000		1000
+#define SPEED_2500		2500
+#define SPEED_10000		10000
+
+/* Duplex, half or full. */
+#define DUPLEX_HALF		0x00
+#define DUPLEX_FULL		0x01
+
+/* Which connector port. */
+#define PORT_TP			0x00
+#define PORT_AUI		0x01
+#define PORT_MII		0x02
+#define PORT_FIBRE		0x03
+#define PORT_BNC		0x04
+#define PORT_DA			0x05
+#define PORT_NONE		0xef
+#define PORT_OTHER		0xff
+
+/* Which transceiver to use. */
+#define XCVR_INTERNAL		0x00
+#define XCVR_EXTERNAL		0x01
+#define XCVR_DUMMY1		0x02
+#define XCVR_DUMMY2		0x03
+#define XCVR_DUMMY3		0x04
+
+/* Enable or disable autonegotiation.  If this is set to enable,
+ * the forced link modes above are completely ignored.
+ */
+#define AUTONEG_DISABLE		0x00
+#define AUTONEG_ENABLE		0x01
+
+/* Mode MDI or MDI-X */
+#define ETH_TP_MDI_INVALID	0x00
+#define ETH_TP_MDI		0x01
+#define ETH_TP_MDI_X		0x02
+
+/* Wake-On-Lan options. */
+#define WAKE_PHY		(1 << 0)
+#define WAKE_UCAST		(1 << 1)
+#define WAKE_MCAST		(1 << 2)
+#define WAKE_BCAST		(1 << 3)
+#define WAKE_ARP		(1 << 4)
+#define WAKE_MAGIC		(1 << 5)
+#define WAKE_MAGICSECURE	(1 << 6) /* only meaningful if WAKE_MAGIC */
+
+/* L2-L4 network traffic flow types */
+#define	TCP_V4_FLOW	0x01	/* hash or spec (tcp_ip4_spec) */
+#define	UDP_V4_FLOW	0x02	/* hash or spec (udp_ip4_spec) */
+#define	SCTP_V4_FLOW	0x03	/* hash or spec (sctp_ip4_spec) */
+#define	AH_ESP_V4_FLOW	0x04	/* hash only */
+#define	TCP_V6_FLOW	0x05	/* hash only */
+#define	UDP_V6_FLOW	0x06	/* hash only */
+#define	SCTP_V6_FLOW	0x07	/* hash only */
+#define	AH_ESP_V6_FLOW	0x08	/* hash only */
+#define	AH_V4_FLOW	0x09	/* hash or spec (ah_ip4_spec) */
+#define	ESP_V4_FLOW	0x0a	/* hash or spec (esp_ip4_spec) */
+#define	AH_V6_FLOW	0x0b	/* hash only */
+#define	ESP_V6_FLOW	0x0c	/* hash only */
+#define	IP_USER_FLOW	0x0d	/* spec only (usr_ip4_spec) */
+#define	IPV4_FLOW	0x10	/* hash only */
+#define	IPV6_FLOW	0x11	/* hash only */
+#define	ETHER_FLOW	0x12	/* spec only (ether_spec) */
+
+/* L3-L4 network traffic flow hash options */
+#define	RXH_L2DA	(1 << 1)
+#define	RXH_VLAN	(1 << 2)
+#define	RXH_L3_PROTO	(1 << 3)
+#define	RXH_IP_SRC	(1 << 4)
+#define	RXH_IP_DST	(1 << 5)
+#define	RXH_L4_B_0_1	(1 << 6) /* src port in case of TCP/UDP/SCTP */
+#define	RXH_L4_B_2_3	(1 << 7) /* dst port in case of TCP/UDP/SCTP */
+#define	RXH_DISCARD	(1 << 31)
+
+#define	RX_CLS_FLOW_DISC	0xffffffffffffffffULL
+
+/* Reset flags */
+/* The reset() operation must clear the flags for the components which
+ * were actually reset.  On successful return, the flags indicate the
+ * components which were not reset, either because they do not exist
+ * in the hardware or because they cannot be reset independently.  The
+ * driver must never reset any components that were not requested.
+ */
+enum ethtool_reset_flags {
+	/* These flags represent components dedicated to the interface
+	 * the command is addressed to.  Shift any flag left by
+	 * ETH_RESET_SHARED_SHIFT to reset a shared component of the
+	 * same type.
+	 */
+	ETH_RESET_MGMT		= 1 << 0,	/* Management processor */
+	ETH_RESET_IRQ		= 1 << 1,	/* Interrupt requester */
+	ETH_RESET_DMA		= 1 << 2,	/* DMA engine */
+	ETH_RESET_FILTER	= 1 << 3,	/* Filtering/flow direction */
+	ETH_RESET_OFFLOAD	= 1 << 4,	/* Protocol offload */
+	ETH_RESET_MAC		= 1 << 5,	/* Media access controller */
+	ETH_RESET_PHY		= 1 << 6,	/* Transceiver/PHY */
+	ETH_RESET_RAM		= 1 << 7,	/* RAM shared between
+						 * multiple components */
+
+	ETH_RESET_DEDICATED	= 0x0000ffff,	/* All components dedicated to
+						 * this interface */
+	ETH_RESET_ALL		= 0xffffffff,	/* All components used by this
+						 * interface, even if shared */
+};
+#define ETH_RESET_SHARED_SHIFT	16
+
+#endif /* _LINUX_ETHTOOL_H */
diff --git a/qemu/roms/u-boot/include/linux/fb.h b/qemu/roms/u-boot/include/linux/fb.h
new file mode 100644
index 000000000..652cf3bab
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/fb.h
@@ -0,0 +1,619 @@
+#ifndef _LINUX_FB_H
+#define _LINUX_FB_H
+
+#include <linux/types.h>
+#include <linux/list.h>
+
+/* Definitions of frame buffers						*/
+
+#define FB_MAX			32	/* sufficient for now */
+
+#define FB_TYPE_PACKED_PIXELS		0	/* Packed Pixels	*/
+
+#define FB_VISUAL_MONO01		0	/* Monochr. 1=Black 0=White */
+#define FB_VISUAL_MONO10		1	/* Monochr. 1=White 0=Black */
+#define FB_VISUAL_TRUECOLOR		2	/* True color	*/
+#define FB_VISUAL_PSEUDOCOLOR		3	/* Pseudo color (like atari) */
+#define FB_VISUAL_DIRECTCOLOR		4	/* Direct color */
+#define FB_VISUAL_STATIC_PSEUDOCOLOR	5	/* Pseudo color readonly */
+
+#define FB_ACCEL_NONE		0	/* no hardware accelerator	*/
+
+struct fb_fix_screeninfo {
+	char id[16];			/* identification string eg "TT Builtin" */
+	unsigned long smem_start;	/* Start of frame buffer mem */
+					/* (physical address) */
+	__u32 smem_len;			/* Length of frame buffer mem */
+	__u32 type;			/* see FB_TYPE_*		*/
+	__u32 type_aux;			/* Interleave for interleaved Planes */
+	__u32 visual;			/* see FB_VISUAL_*		*/
+	__u16 xpanstep;			/* zero if no hardware panning	*/
+	__u16 ypanstep;			/* zero if no hardware panning	*/
+	__u16 ywrapstep;		/* zero if no hardware ywrap	*/
+	__u32 line_length;		/* length of a line in bytes	*/
+	unsigned long mmio_start;	/* Start of Memory Mapped I/O	*/
+					/* (physical address) */
+	__u32 mmio_len;			/* Length of Memory Mapped I/O	*/
+	__u32 accel;			/* Indicate to driver which	*/
+					/*  specific chip/card we have	*/
+	__u16 reserved[3];		/* Reserved for future compatibility */
+};
+
+/*
+ * Interpretation of offset for color fields: All offsets are from the right,
+ * inside a "pixel" value, which is exactly 'bits_per_pixel' wide (means: you
+ * can use the offset as right argument to <<). A pixel afterwards is a bit
+ * stream and is written to video memory as that unmodified.
+ *
+ * For pseudocolor: offset and length should be the same for all color
+ * components. Offset specifies the position of the least significant bit
+ * of the pallette index in a pixel value. Length indicates the number
+ * of available palette entries (i.e. # of entries = 1 << length).
+ */
+struct fb_bitfield {
+	__u32 offset;			/* beginning of bitfield	*/
+	__u32 length;			/* length of bitfield		*/
+	__u32 msb_right;
+
+};
+
+#define FB_NONSTD_HAM		1	/* Hold-And-Modify (HAM)	*/
+#define FB_NONSTD_REV_PIX_IN_B	2	/* order of pixels in each byte is reversed */
+
+#define FB_ACTIVATE_NOW		0	/* set values immediately (or vbl)*/
+#define FB_ACTIVATE_NXTOPEN	1	/* activate on next open	*/
+#define FB_ACTIVATE_TEST	2	/* don't set, round up impossible */
+#define FB_ACTIVATE_MASK       15
+					/* values			*/
+#define FB_ACTIVATE_VBL	       16	/* activate values on next vbl	*/
+#define FB_CHANGE_CMAP_VBL     32	/* change colormap on vbl	*/
+#define FB_ACTIVATE_ALL	       64	/* change all VCs on this fb	*/
+#define FB_ACTIVATE_FORCE     128	/* force apply even when no change*/
+#define FB_ACTIVATE_INV_MODE  256	/* invalidate videomode */
+
+#define FB_SYNC_HOR_HIGH_ACT	1	/* horizontal sync high active	*/
+#define FB_SYNC_VERT_HIGH_ACT	2	/* vertical sync high active	*/
+#define FB_SYNC_EXT		4	/* external sync		*/
+#define FB_SYNC_COMP_HIGH_ACT	8	/* composite sync high active	*/
+#define FB_SYNC_BROADCAST	16	/* broadcast video timings	*/
+					/* vtotal = 144d/288n/576i => PAL  */
+					/* vtotal = 121d/242n/484i => NTSC */
+#define FB_SYNC_ON_GREEN	32	/* sync on green */
+
+#define FB_VMODE_NONINTERLACED	0	/* non interlaced */
+#define FB_VMODE_INTERLACED	1	/* interlaced	*/
+#define FB_VMODE_DOUBLE		2	/* double scan */
+#define FB_VMODE_ODD_FLD_FIRST	4	/* interlaced: top line first */
+#define FB_VMODE_MASK		255
+
+#define FB_VMODE_YWRAP		256	/* ywrap instead of panning	*/
+#define FB_VMODE_SMOOTH_XPAN	512	/* smooth xpan possible (internally used) */
+#define FB_VMODE_CONUPDATE	512	/* don't update x/yoffset	*/
+
+/*
+ * Display rotation support
+ */
+#define FB_ROTATE_UR	  0
+#define FB_ROTATE_CW	  1
+#define FB_ROTATE_UD	  2
+#define FB_ROTATE_CCW	  3
+
+#define PICOS2KHZ(a) (1000000000UL/(a))
+#define KHZ2PICOS(a) (1000000000UL/(a))
+
+struct fb_var_screeninfo {
+	__u32 xres;			/* visible resolution		*/
+	__u32 yres;
+	__u32 xres_virtual;		/* virtual resolution		*/
+	__u32 yres_virtual;
+	__u32 xoffset;			/* offset from virtual to visible */
+	__u32 yoffset;			/* resolution			*/
+
+	__u32 bits_per_pixel;		/* guess what			*/
+	__u32 grayscale;		/* != 0 Graylevels instead of colors */
+
+	struct fb_bitfield red;		/* bitfield in fb mem if true color, */
+	struct fb_bitfield green;	/* else only length is significant */
+	struct fb_bitfield blue;
+	struct fb_bitfield transp;	/* transparency			*/
+
+	__u32 nonstd;			/* != 0 Non standard pixel format */
+
+	__u32 activate;			/* see FB_ACTIVATE_*		*/
+
+	__u32 height;			/* height of picture in mm    */
+	__u32 width;			/* width of picture in mm     */
+
+	__u32 accel_flags;		/* (OBSOLETE) see fb_info.flags */
+
+	/* Timing: All values in pixclocks, except pixclock (of course) */
+	__u32 pixclock;			/* pixel clock in ps (pico seconds) */
+	__u32 left_margin;		/* time from sync to picture	*/
+	__u32 right_margin;		/* time from picture to sync	*/
+	__u32 upper_margin;		/* time from sync to picture	*/
+	__u32 lower_margin;
+	__u32 hsync_len;		/* length of horizontal sync	*/
+	__u32 vsync_len;		/* length of vertical sync	*/
+	__u32 sync;			/* see FB_SYNC_*		*/
+	__u32 vmode;			/* see FB_VMODE_*		*/
+	__u32 rotate;			/* angle we rotate counter clockwise */
+	__u32 reserved[5];		/* Reserved for future compatibility */
+};
+
+struct fb_cmap {
+	__u32 start;			/* First entry	*/
+	__u32 len;			/* Number of entries */
+	__u16 *red;			/* Red values	*/
+	__u16 *green;
+	__u16 *blue;
+	__u16 *transp;			/* transparency, can be NULL */
+};
+
+struct fb_con2fbmap {
+	__u32 console;
+	__u32 framebuffer;
+};
+
+/* VESA Blanking Levels */
+#define VESA_NO_BLANKING	0
+#define VESA_VSYNC_SUSPEND	1
+#define VESA_HSYNC_SUSPEND	2
+#define VESA_POWERDOWN		3
+
+
+enum {
+	/* screen: unblanked, hsync: on,  vsync: on */
+	FB_BLANK_UNBLANK       = VESA_NO_BLANKING,
+
+	/* screen: blanked,   hsync: on,  vsync: on */
+	FB_BLANK_NORMAL        = VESA_NO_BLANKING + 1,
+
+	/* screen: blanked,   hsync: on,  vsync: off */
+	FB_BLANK_VSYNC_SUSPEND = VESA_VSYNC_SUSPEND + 1,
+
+	/* screen: blanked,   hsync: off, vsync: on */
+	FB_BLANK_HSYNC_SUSPEND = VESA_HSYNC_SUSPEND + 1,
+
+	/* screen: blanked,   hsync: off, vsync: off */
+	FB_BLANK_POWERDOWN     = VESA_POWERDOWN + 1
+};
+
+#define FB_VBLANK_VBLANKING	0x001	/* currently in a vertical blank */
+#define FB_VBLANK_HBLANKING	0x002	/* currently in a horizontal blank */
+#define FB_VBLANK_HAVE_VBLANK	0x004	/* vertical blanks can be detected */
+#define FB_VBLANK_HAVE_HBLANK	0x008	/* horizontal blanks can be detected */
+#define FB_VBLANK_HAVE_COUNT	0x010	/* global retrace counter is available */
+#define FB_VBLANK_HAVE_VCOUNT	0x020	/* the vcount field is valid */
+#define FB_VBLANK_HAVE_HCOUNT	0x040	/* the hcount field is valid */
+#define FB_VBLANK_VSYNCING	0x080	/* currently in a vsync */
+#define FB_VBLANK_HAVE_VSYNC	0x100	/* verical syncs can be detected */
+
+struct fb_vblank {
+	__u32 flags;			/* FB_VBLANK flags */
+	__u32 count;			/* counter of retraces since boot */
+	__u32 vcount;			/* current scanline position */
+	__u32 hcount;			/* current scandot position */
+	__u32 reserved[4];		/* reserved for future compatibility */
+};
+
+/* Internal HW accel */
+#define ROP_COPY 0
+#define ROP_XOR  1
+
+struct fb_copyarea {
+	__u32 dx;
+	__u32 dy;
+	__u32 width;
+	__u32 height;
+	__u32 sx;
+	__u32 sy;
+};
+
+struct fb_fillrect {
+	__u32 dx;	/* screen-relative */
+	__u32 dy;
+	__u32 width;
+	__u32 height;
+	__u32 color;
+	__u32 rop;
+};
+
+struct fb_image {
+	__u32 dx;		/* Where to place image */
+	__u32 dy;
+	__u32 width;		/* Size of image */
+	__u32 height;
+	__u32 fg_color;		/* Only used when a mono bitmap */
+	__u32 bg_color;
+	__u8  depth;		/* Depth of the image */
+	const char *data;	/* Pointer to image data */
+	struct fb_cmap cmap;	/* color map info */
+};
+
+/*
+ * hardware cursor control
+ */
+
+#define FB_CUR_SETIMAGE 0x01
+#define FB_CUR_SETPOS	0x02
+#define FB_CUR_SETHOT	0x04
+#define FB_CUR_SETCMAP	0x08
+#define FB_CUR_SETSHAPE 0x10
+#define FB_CUR_SETSIZE	0x20
+#define FB_CUR_SETALL	0xFF
+
+struct fbcurpos {
+	__u16 x, y;
+};
+
+struct fb_cursor {
+	__u16 set;		/* what to set */
+	__u16 enable;		/* cursor on/off */
+	__u16 rop;		/* bitop operation */
+	const char *mask;	/* cursor mask bits */
+	struct fbcurpos hot;	/* cursor hot spot */
+	struct fb_image	image;	/* Cursor image */
+};
+
+#ifdef CONFIG_FB_BACKLIGHT
+/* Settings for the generic backlight code */
+#define FB_BACKLIGHT_LEVELS	128
+#define FB_BACKLIGHT_MAX	0xFF
+#endif
+
+#ifdef __KERNEL__
+
+struct vm_area_struct;
+struct fb_info;
+struct device;
+struct file;
+
+/* Definitions below are used in the parsed monitor specs */
+#define FB_DPMS_ACTIVE_OFF	1
+#define FB_DPMS_SUSPEND		2
+#define FB_DPMS_STANDBY		4
+
+#define FB_DISP_DDI		1
+#define FB_DISP_ANA_700_300	2
+#define FB_DISP_ANA_714_286	4
+#define FB_DISP_ANA_1000_400	8
+#define FB_DISP_ANA_700_000	16
+
+#define FB_DISP_MONO		32
+#define FB_DISP_RGB		64
+#define FB_DISP_MULTI		128
+#define FB_DISP_UNKNOWN		256
+
+#define FB_SIGNAL_NONE		0
+#define FB_SIGNAL_BLANK_BLANK	1
+#define FB_SIGNAL_SEPARATE	2
+#define FB_SIGNAL_COMPOSITE	4
+#define FB_SIGNAL_SYNC_ON_GREEN	8
+#define FB_SIGNAL_SERRATION_ON	16
+
+#define FB_MISC_PRIM_COLOR	1
+#define FB_MISC_1ST_DETAIL	2	/* First Detailed Timing is preferred */
+struct fb_chroma {
+	__u32 redx;	/* in fraction of 1024 */
+	__u32 greenx;
+	__u32 bluex;
+	__u32 whitex;
+	__u32 redy;
+	__u32 greeny;
+	__u32 bluey;
+	__u32 whitey;
+};
+
+struct fb_monspecs {
+	struct fb_chroma chroma;
+	struct fb_videomode *modedb;	/* mode database */
+	__u8  manufacturer[4];		/* Manufacturer */
+	__u8  monitor[14];		/* Monitor String */
+	__u8  serial_no[14];		/* Serial Number */
+	__u8  ascii[14];		/* ? */
+	__u32 modedb_len;		/* mode database length */
+	__u32 model;			/* Monitor Model */
+	__u32 serial;			/* Serial Number - Integer */
+	__u32 year;			/* Year manufactured */
+	__u32 week;			/* Week Manufactured */
+	__u32 hfmin;			/* hfreq lower limit (Hz) */
+	__u32 hfmax;			/* hfreq upper limit (Hz) */
+	__u32 dclkmin;			/* pixelclock lower limit (Hz) */
+	__u32 dclkmax;			/* pixelclock upper limit (Hz) */
+	__u16 input;			/* display type - see FB_DISP_* */
+	__u16 dpms;			/* DPMS support - see FB_DPMS_ */
+	__u16 signal;			/* Signal Type - see FB_SIGNAL_* */
+	__u16 vfmin;			/* vfreq lower limit (Hz) */
+	__u16 vfmax;			/* vfreq upper limit (Hz) */
+	__u16 gamma;			/* Gamma - in fractions of 100 */
+	__u16 gtf	: 1;		/* supports GTF */
+	__u16 misc;			/* Misc flags - see FB_MISC_* */
+	__u8  version;			/* EDID version... */
+	__u8  revision;			/* ...and revision */
+	__u8  max_x;			/* Maximum horizontal size (cm) */
+	__u8  max_y;			/* Maximum vertical size (cm) */
+};
+
+struct fb_cmap_user {
+	__u32 start;			/* First entry	*/
+	__u32 len;			/* Number of entries */
+	__u16 *red;		/* Red values	*/
+	__u16 *green;
+	__u16 *blue;
+	__u16 *transp;		/* transparency, can be NULL */
+};
+
+struct fb_image_user {
+	__u32 dx;			/* Where to place image */
+	__u32 dy;
+	__u32 width;			/* Size of image */
+	__u32 height;
+	__u32 fg_color;			/* Only used when a mono bitmap */
+	__u32 bg_color;
+	__u8  depth;			/* Depth of the image */
+	const char *data;	/* Pointer to image data */
+	struct fb_cmap_user cmap;	/* color map info */
+};
+
+struct fb_cursor_user {
+	__u16 set;			/* what to set */
+	__u16 enable;			/* cursor on/off */
+	__u16 rop;			/* bitop operation */
+	const char *mask;	/* cursor mask bits */
+	struct fbcurpos hot;		/* cursor hot spot */
+	struct fb_image_user image;	/* Cursor image */
+};
+
+/*
+ * Register/unregister for framebuffer events
+ */
+
+/*	The resolution of the passed in fb_info about to change */
+#define FB_EVENT_MODE_CHANGE		0x01
+/*	The display on this fb_info is beeing suspended, no access to the
+ *	framebuffer is allowed any more after that call returns
+ */
+#define FB_EVENT_SUSPEND		0x02
+/*	The display on this fb_info was resumed, you can restore the display
+ *	if you own it
+ */
+#define FB_EVENT_RESUME			0x03
+/*	An entry from the modelist was removed */
+#define FB_EVENT_MODE_DELETE		0x04
+/*	A driver registered itself */
+#define FB_EVENT_FB_REGISTERED		0x05
+/*	A driver unregistered itself */
+#define FB_EVENT_FB_UNREGISTERED	0x06
+/*	CONSOLE-SPECIFIC: get console to framebuffer mapping */
+#define FB_EVENT_GET_CONSOLE_MAP	0x07
+/*	CONSOLE-SPECIFIC: set console to framebuffer mapping */
+#define FB_EVENT_SET_CONSOLE_MAP	0x08
+/*	A hardware display blank change occured */
+#define FB_EVENT_BLANK			0x09
+/*	Private modelist is to be replaced */
+#define FB_EVENT_NEW_MODELIST		0x0A
+/*	The resolution of the passed in fb_info about to change and
+	all vc's should be changed	   */
+#define FB_EVENT_MODE_CHANGE_ALL	0x0B
+/*	A software display blank change occured */
+#define FB_EVENT_CONBLANK		0x0C
+/*	Get drawing requirements	*/
+#define FB_EVENT_GET_REQ		0x0D
+/*	Unbind from the console if possible */
+#define FB_EVENT_FB_UNBIND		0x0E
+
+struct fb_event {
+	struct fb_info *info;
+	void *data;
+};
+
+struct fb_blit_caps {
+	u32 x;
+	u32 y;
+	u32 len;
+	u32 flags;
+};
+
+/*
+ * Pixmap structure definition
+ *
+ * The purpose of this structure is to translate data
+ * from the hardware independent format of fbdev to what
+ * format the hardware needs.
+ */
+
+#define FB_PIXMAP_DEFAULT 1	/* used internally by fbcon */
+#define FB_PIXMAP_SYSTEM  2	/* memory is in system RAM  */
+#define FB_PIXMAP_IO	  4	/* memory is iomapped	    */
+#define FB_PIXMAP_SYNC	  256	/* set if GPU can DMA	    */
+
+struct fb_pixmap {
+	u8  *addr;		/* pointer to memory			*/
+	u32 size;		/* size of buffer in bytes		*/
+	u32 offset;		/* current offset to buffer		*/
+	u32 buf_align;		/* byte alignment of each bitmap	*/
+	u32 scan_align;		/* alignment per scanline		*/
+	u32 access_align;	/* alignment per read/write (bits)	*/
+	u32 flags;		/* see FB_PIXMAP_*			*/
+	u32 blit_x;		/* supported bit block dimensions (1-32)*/
+	u32 blit_y;		/* Format: blit_x = 1 << (width - 1)	*/
+				/*	   blit_y = 1 << (height - 1)	*/
+				/* if 0, will be set to 0xffffffff (all)*/
+	/* access methods */
+	void (*writeio)(struct fb_info *info, void *dst, void *src, unsigned int size);
+	void (*readio) (struct fb_info *info, void *dst, void *src, unsigned int size);
+};
+
+#ifdef CONFIG_FB_DEFERRED_IO
+struct fb_deferred_io {
+	/* delay between mkwrite and deferred handler */
+	unsigned long delay;
+	struct mutex lock; /* mutex that protects the page list */
+	struct list_head pagelist; /* list of touched pages */
+	/* callback */
+	void (*deferred_io)(struct fb_info *info, struct list_head *pagelist);
+};
+#endif
+
+/* FBINFO_* = fb_info.flags bit flags */
+#define FBINFO_MODULE		0x0001	/* Low-level driver is a module */
+#define FBINFO_HWACCEL_DISABLED	0x0002
+	/* When FBINFO_HWACCEL_DISABLED is set:
+	 *  Hardware acceleration is turned off.  Software implementations
+	 *  of required functions (copyarea(), fillrect(), and imageblit())
+	 *  takes over; acceleration engine should be in a quiescent state */
+
+/* hints */
+#define FBINFO_PARTIAL_PAN_OK	0x0040 /* otw use pan only for double-buffering */
+#define FBINFO_READS_FAST	0x0080 /* soft-copy faster than rendering */
+
+/*
+ * A driver may set this flag to indicate that it does want a set_par to be
+ * called every time when fbcon_switch is executed. The advantage is that with
+ * this flag set you can really be sure that set_par is always called before
+ * any of the functions dependant on the correct hardware state or altering
+ * that state, even if you are using some broken X releases. The disadvantage
+ * is that it introduces unwanted delays to every console switch if set_par
+ * is slow. It is a good idea to try this flag in the drivers initialization
+ * code whenever there is a bug report related to switching between X and the
+ * framebuffer console.
+ */
+#define FBINFO_MISC_ALWAYS_SETPAR   0x40000
+
+/*
+ * Host and GPU endianness differ.
+ */
+#define FBINFO_FOREIGN_ENDIAN	0x100000
+/*
+ * Big endian math. This is the same flags as above, but with different
+ * meaning, it is set by the fb subsystem depending FOREIGN_ENDIAN flag
+ * and host endianness. Drivers should not use this flag.
+ */
+#define FBINFO_BE_MATH	0x100000
+
+struct fb_info {
+	int node;
+	int flags;
+	struct fb_var_screeninfo var;	/* Current var */
+	struct fb_fix_screeninfo fix;	/* Current fix */
+	struct fb_monspecs monspecs;	/* Current Monitor specs */
+	struct fb_pixmap pixmap;	/* Image hardware mapper */
+	struct fb_pixmap sprite;	/* Cursor hardware mapper */
+	struct fb_cmap cmap;		/* Current cmap */
+	struct list_head modelist;	/* mode list */
+	struct fb_videomode *mode;	/* current mode */
+
+	char *screen_base;	/* Virtual address */
+	unsigned long screen_size;	/* Amount of ioremapped VRAM or 0 */
+	void *pseudo_palette;		/* Fake palette of 16 colors */
+#define FBINFO_STATE_RUNNING	0
+#define FBINFO_STATE_SUSPENDED	1
+	u32 state;			/* Hardware state i.e suspend */
+	void *fbcon_par;		/* fbcon use-only private area */
+	/* From here on everything is device dependent */
+	void *par;
+};
+
+#define FBINFO_DEFAULT	0
+
+#define FBINFO_FLAG_MODULE	FBINFO_MODULE
+#define FBINFO_FLAG_DEFAULT	FBINFO_DEFAULT
+
+/* This will go away */
+#if defined(__sparc__)
+
+/* We map all of our framebuffers such that big-endian accesses
+ * are what we want, so the following is sufficient.
+ */
+
+/* This will go away */
+#define fb_readb sbus_readb
+#define fb_readw sbus_readw
+#define fb_readl sbus_readl
+#define fb_readq sbus_readq
+#define fb_writeb sbus_writeb
+#define fb_writew sbus_writew
+#define fb_writel sbus_writel
+#define fb_writeq sbus_writeq
+#define fb_memset sbus_memset_io
+
+#elif defined(__i386__) || defined(__alpha__) || defined(__x86_64__) || defined(__hppa__) || defined(__sh__) || defined(__powerpc__) || defined(__avr32__) || defined(__bfin__)
+
+#define fb_readb __raw_readb
+#define fb_readw __raw_readw
+#define fb_readl __raw_readl
+#define fb_readq __raw_readq
+#define fb_writeb __raw_writeb
+#define fb_writew __raw_writew
+#define fb_writel __raw_writel
+#define fb_writeq __raw_writeq
+#define fb_memset memset_io
+
+#else
+
+#define fb_readb(addr) (*(volatile u8 *) (addr))
+#define fb_readw(addr) (*(volatile u16 *) (addr))
+#define fb_readl(addr) (*(volatile u32 *) (addr))
+#define fb_readq(addr) (*(volatile u64 *) (addr))
+#define fb_writeb(b,addr) (*(volatile u8 *) (addr) = (b))
+#define fb_writew(b,addr) (*(volatile u16 *) (addr) = (b))
+#define fb_writel(b,addr) (*(volatile u32 *) (addr) = (b))
+#define fb_writeq(b,addr) (*(volatile u64 *) (addr) = (b))
+#define fb_memset memset
+
+#endif
+
+#define FB_LEFT_POS(p, bpp)	     (fb_be_math(p) ? (32 - (bpp)) : 0)
+#define FB_SHIFT_HIGH(p, val, bits)  (fb_be_math(p) ? (val) >> (bits) : \
+						      (val) << (bits))
+#define FB_SHIFT_LOW(p, val, bits)   (fb_be_math(p) ? (val) << (bits) : \
+						      (val) >> (bits))
+/* drivers/video/fbmon.c */
+#define FB_MAXTIMINGS		0
+#define FB_VSYNCTIMINGS		1
+#define FB_HSYNCTIMINGS		2
+#define FB_DCLKTIMINGS		3
+#define FB_IGNOREMON		0x100
+
+#define FB_MODE_IS_UNKNOWN	0
+#define FB_MODE_IS_DETAILED	1
+#define FB_MODE_IS_STANDARD	2
+#define FB_MODE_IS_VESA		4
+#define FB_MODE_IS_CALCULATED	8
+#define FB_MODE_IS_FIRST	16
+#define FB_MODE_IS_FROM_VAR	32
+
+
+/* drivers/video/fbcmap.c */
+
+extern int fb_alloc_cmap(struct fb_cmap *cmap, int len, int transp);
+extern void fb_dealloc_cmap(struct fb_cmap *cmap);
+extern int fb_copy_cmap(const struct fb_cmap *from, struct fb_cmap *to);
+extern int fb_cmap_to_user(const struct fb_cmap *from, struct fb_cmap_user *to);
+extern int fb_set_cmap(struct fb_cmap *cmap, struct fb_info *fb_info);
+extern int fb_set_user_cmap(struct fb_cmap_user *cmap, struct fb_info *fb_info);
+extern const struct fb_cmap *fb_default_cmap(int len);
+extern void fb_invert_cmaps(void);
+
+struct fb_videomode {
+	const char *name;	/* optional */
+	u32 refresh;		/* optional */
+	u32 xres;
+	u32 yres;
+	u32 pixclock;
+	u32 left_margin;
+	u32 right_margin;
+	u32 upper_margin;
+	u32 lower_margin;
+	u32 hsync_len;
+	u32 vsync_len;
+	u32 sync;
+	u32 vmode;
+	u32 flag;
+};
+
+int board_video_skip(void);
+
+#endif /* __KERNEL__ */
+
+#endif /* _LINUX_FB_H */
diff --git a/qemu/roms/u-boot/include/linux/input.h b/qemu/roms/u-boot/include/linux/input.h
new file mode 100644
index 000000000..44aec763d
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/input.h
@@ -0,0 +1,155 @@
+/*
+ * Copyright (c) 1999-2002 Vojtech Pavlik
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+
+#ifndef _LINUX_INPUT_H
+#define _LINUX_INPUT_H
+
+/*
+ * Keys and buttons
+ *
+ * Most of the keys/buttons are modeled after USB HUT 1.12
+ * (see http://www.usb.org/developers/hidpage).
+ * Abbreviations in the comments:
+ * AC - Application Control
+ * AL - Application Launch Button
+ * SC - System Control
+ */
+
+#define KEY_RESERVED		0
+#define KEY_ESC			1
+#define KEY_1			2
+#define KEY_2			3
+#define KEY_3			4
+#define KEY_4			5
+#define KEY_5			6
+#define KEY_6			7
+#define KEY_7			8
+#define KEY_8			9
+#define KEY_9			10
+#define KEY_0			11
+#define KEY_MINUS		12
+#define KEY_EQUAL		13
+#define KEY_BACKSPACE		14
+#define KEY_TAB			15
+#define KEY_Q			16
+#define KEY_W			17
+#define KEY_E			18
+#define KEY_R			19
+#define KEY_T			20
+#define KEY_Y			21
+#define KEY_U			22
+#define KEY_I			23
+#define KEY_O			24
+#define KEY_P			25
+#define KEY_LEFTBRACE		26
+#define KEY_RIGHTBRACE		27
+#define KEY_ENTER		28
+#define KEY_LEFTCTRL		29
+#define KEY_A			30
+#define KEY_S			31
+#define KEY_D			32
+#define KEY_F			33
+#define KEY_G			34
+#define KEY_H			35
+#define KEY_J			36
+#define KEY_K			37
+#define KEY_L			38
+#define KEY_SEMICOLON		39
+#define KEY_APOSTROPHE		40
+#define KEY_GRAVE		41
+#define KEY_LEFTSHIFT		42
+#define KEY_BACKSLASH		43
+#define KEY_Z			44
+#define KEY_X			45
+#define KEY_C			46
+#define KEY_V			47
+#define KEY_B			48
+#define KEY_N			49
+#define KEY_M			50
+#define KEY_COMMA		51
+#define KEY_DOT			52
+#define KEY_SLASH		53
+#define KEY_RIGHTSHIFT		54
+#define KEY_KPASTERISK		55
+#define KEY_LEFTALT		56
+#define KEY_SPACE		57
+#define KEY_CAPSLOCK		58
+#define KEY_F1			59
+#define KEY_F2			60
+#define KEY_F3			61
+#define KEY_F4			62
+#define KEY_F5			63
+#define KEY_F6			64
+#define KEY_F7			65
+#define KEY_F8			66
+#define KEY_F9			67
+#define KEY_F10			68
+#define KEY_NUMLOCK		69
+#define KEY_SCROLLLOCK		70
+#define KEY_KP7			71
+#define KEY_KP8			72
+#define KEY_KP9			73
+#define KEY_KPMINUS		74
+#define KEY_KP4			75
+#define KEY_KP5			76
+#define KEY_KP6			77
+#define KEY_KPPLUS		78
+#define KEY_KP1			79
+#define KEY_KP2			80
+#define KEY_KP3			81
+#define KEY_KP0			82
+#define KEY_KPDOT		83
+
+#define KEY_ZENKAKUHANKAKU	85
+#define KEY_102ND		86
+#define KEY_F11			87
+#define KEY_F12			88
+#define KEY_RO			89
+#define KEY_KATAKANA		90
+#define KEY_HIRAGANA		91
+#define KEY_HENKAN		92
+#define KEY_KATAKANAHIRAGANA	93
+#define KEY_MUHENKAN		94
+#define KEY_KPJPCOMMA		95
+#define KEY_KPENTER		96
+#define KEY_RIGHTCTRL		97
+#define KEY_KPSLASH		98
+#define KEY_SYSRQ		99
+#define KEY_RIGHTALT		100
+#define KEY_LINEFEED		101
+#define KEY_HOME		102
+#define KEY_UP			103
+#define KEY_PAGEUP		104
+#define KEY_LEFT		105
+#define KEY_RIGHT		106
+#define KEY_END			107
+#define KEY_DOWN		108
+#define KEY_PAGEDOWN		109
+#define KEY_INSERT		110
+#define KEY_DELETE		111
+#define KEY_MACRO		112
+#define KEY_MUTE		113
+#define KEY_VOLUMEDOWN		114
+#define KEY_VOLUMEUP		115
+#define KEY_POWER		116	/* SC System Power Down */
+#define KEY_KPEQUAL		117
+#define KEY_KPPLUSMINUS		118
+#define KEY_PAUSE		119
+#define KEY_SCALE		120	/* AL Compiz Scale (Expose) */
+
+#define KEY_KPCOMMA		121
+#define KEY_HANGEUL		122
+#define KEY_HANGUEL		KEY_HANGEUL
+#define KEY_HANJA		123
+#define KEY_YEN			124
+#define KEY_LEFTMETA		125
+#define KEY_RIGHTMETA		126
+#define KEY_COMPOSE		127
+#define KEY_FN			0x1d0
+
+#endif
diff --git a/qemu/roms/u-boot/include/linux/ioctl.h b/qemu/roms/u-boot/include/linux/ioctl.h
new file mode 100644
index 000000000..7e55c3614
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/ioctl.h
@@ -0,0 +1,6 @@
+#ifndef _LINUX_IOCTL_H
+#define _LINUX_IOCTL_H
+
+#include <asm/ioctl.h>
+
+#endif /* _LINUX_IOCTL_H */
diff --git a/qemu/roms/u-boot/include/linux/ioport.h b/qemu/roms/u-boot/include/linux/ioport.h
new file mode 100644
index 000000000..7129504e0
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/ioport.h
@@ -0,0 +1,192 @@
+/*
+ * ioport.h	Definitions of routines for detecting, reserving and
+ *		allocating system resources.
+ *
+ * Authors:	Linus Torvalds
+ */
+
+#ifndef _LINUX_IOPORT_H
+#define _LINUX_IOPORT_H
+
+#ifndef __ASSEMBLY__
+#include <linux/compiler.h>
+#include <linux/types.h>
+/*
+ * Resources are tree-like, allowing
+ * nesting etc..
+ */
+struct resource {
+	resource_size_t start;
+	resource_size_t end;
+	const char *name;
+	unsigned long flags;
+	struct resource *parent, *sibling, *child;
+};
+
+struct resource_list {
+	struct resource_list *next;
+	struct resource *res;
+	struct pci_dev *dev;
+};
+
+/*
+ * IO resources have these defined flags.
+ */
+#define IORESOURCE_BITS		0x000000ff	/* Bus-specific bits */
+
+#define IORESOURCE_TYPE_BITS	0x00000f00	/* Resource type */
+#define IORESOURCE_IO		0x00000100
+#define IORESOURCE_MEM		0x00000200
+#define IORESOURCE_IRQ		0x00000400
+#define IORESOURCE_DMA		0x00000800
+
+#define IORESOURCE_PREFETCH	0x00001000	/* No side effects */
+#define IORESOURCE_READONLY	0x00002000
+#define IORESOURCE_CACHEABLE	0x00004000
+#define IORESOURCE_RANGELENGTH	0x00008000
+#define IORESOURCE_SHADOWABLE	0x00010000
+
+#define IORESOURCE_SIZEALIGN	0x00020000	/* size indicates alignment */
+#define IORESOURCE_STARTALIGN	0x00040000	/* start field is alignment */
+
+#define IORESOURCE_MEM_64	0x00100000
+
+#define IORESOURCE_EXCLUSIVE	0x08000000	/* Userland may not map this resource */
+#define IORESOURCE_DISABLED	0x10000000
+#define IORESOURCE_UNSET	0x20000000
+#define IORESOURCE_AUTO		0x40000000
+#define IORESOURCE_BUSY		0x80000000	/* Driver has marked this resource busy */
+
+/* PnP IRQ specific bits (IORESOURCE_BITS) */
+#define IORESOURCE_IRQ_HIGHEDGE		(1<<0)
+#define IORESOURCE_IRQ_LOWEDGE		(1<<1)
+#define IORESOURCE_IRQ_HIGHLEVEL	(1<<2)
+#define IORESOURCE_IRQ_LOWLEVEL		(1<<3)
+#define IORESOURCE_IRQ_SHAREABLE	(1<<4)
+#define IORESOURCE_IRQ_OPTIONAL 	(1<<5)
+
+/* PnP DMA specific bits (IORESOURCE_BITS) */
+#define IORESOURCE_DMA_TYPE_MASK	(3<<0)
+#define IORESOURCE_DMA_8BIT		(0<<0)
+#define IORESOURCE_DMA_8AND16BIT	(1<<0)
+#define IORESOURCE_DMA_16BIT		(2<<0)
+
+#define IORESOURCE_DMA_MASTER		(1<<2)
+#define IORESOURCE_DMA_BYTE		(1<<3)
+#define IORESOURCE_DMA_WORD		(1<<4)
+
+#define IORESOURCE_DMA_SPEED_MASK	(3<<6)
+#define IORESOURCE_DMA_COMPATIBLE	(0<<6)
+#define IORESOURCE_DMA_TYPEA		(1<<6)
+#define IORESOURCE_DMA_TYPEB		(2<<6)
+#define IORESOURCE_DMA_TYPEF		(3<<6)
+
+/* PnP memory I/O specific bits (IORESOURCE_BITS) */
+#define IORESOURCE_MEM_WRITEABLE	(1<<0)	/* dup: IORESOURCE_READONLY */
+#define IORESOURCE_MEM_CACHEABLE	(1<<1)	/* dup: IORESOURCE_CACHEABLE */
+#define IORESOURCE_MEM_RANGELENGTH	(1<<2)	/* dup: IORESOURCE_RANGELENGTH */
+#define IORESOURCE_MEM_TYPE_MASK	(3<<3)
+#define IORESOURCE_MEM_8BIT		(0<<3)
+#define IORESOURCE_MEM_16BIT		(1<<3)
+#define IORESOURCE_MEM_8AND16BIT	(2<<3)
+#define IORESOURCE_MEM_32BIT		(3<<3)
+#define IORESOURCE_MEM_SHADOWABLE	(1<<5)	/* dup: IORESOURCE_SHADOWABLE */
+#define IORESOURCE_MEM_EXPANSIONROM	(1<<6)
+
+/* PnP I/O specific bits (IORESOURCE_BITS) */
+#define IORESOURCE_IO_16BIT_ADDR	(1<<0)
+#define IORESOURCE_IO_FIXED		(1<<1)
+
+/* PCI ROM control bits (IORESOURCE_BITS) */
+#define IORESOURCE_ROM_ENABLE		(1<<0)	/* ROM is enabled, same as PCI_ROM_ADDRESS_ENABLE */
+#define IORESOURCE_ROM_SHADOW		(1<<1)	/* ROM is copy at C000:0 */
+#define IORESOURCE_ROM_COPY		(1<<2)	/* ROM is alloc'd copy, resource field overlaid */
+#define IORESOURCE_ROM_BIOS_COPY	(1<<3)	/* ROM is BIOS copy, resource field overlaid */
+
+/* PCI control bits.  Shares IORESOURCE_BITS with above PCI ROM.  */
+#define IORESOURCE_PCI_FIXED		(1<<4)	/* Do not move resource */
+
+/* PC/ISA/whatever - the normal PC address spaces: IO and memory */
+extern struct resource ioport_resource;
+extern struct resource iomem_resource;
+
+extern int request_resource(struct resource *root, struct resource *new);
+extern int release_resource(struct resource *new);
+extern void reserve_region_with_split(struct resource *root,
+			     resource_size_t start, resource_size_t end,
+			     const char *name);
+extern int insert_resource(struct resource *parent, struct resource *new);
+extern void insert_resource_expand_to_fit(struct resource *root, struct resource *new);
+extern int allocate_resource(struct resource *root, struct resource *new,
+			     resource_size_t size, resource_size_t min,
+			     resource_size_t max, resource_size_t align,
+			     void (*alignf)(void *, struct resource *,
+					    resource_size_t, resource_size_t),
+			     void *alignf_data);
+int adjust_resource(struct resource *res, resource_size_t start,
+		    resource_size_t size);
+resource_size_t resource_alignment(struct resource *res);
+static inline resource_size_t resource_size(const struct resource *res)
+{
+	return res->end - res->start + 1;
+}
+static inline unsigned long resource_type(const struct resource *res)
+{
+	return res->flags & IORESOURCE_TYPE_BITS;
+}
+
+/* Convenience shorthand with allocation */
+#define request_region(start,n,name)	__request_region(&ioport_resource, (start), (n), (name), 0)
+#define __request_mem_region(start,n,name, excl) __request_region(&iomem_resource, (start), (n), (name), excl)
+#define request_mem_region(start,n,name) __request_region(&iomem_resource, (start), (n), (name), 0)
+#define request_mem_region_exclusive(start,n,name) \
+	__request_region(&iomem_resource, (start), (n), (name), IORESOURCE_EXCLUSIVE)
+#define rename_region(region, newname) do { (region)->name = (newname); } while (0)
+
+extern struct resource * __request_region(struct resource *,
+					resource_size_t start,
+					resource_size_t n,
+					const char *name, int flags);
+
+/* Compatibility cruft */
+#define release_region(start,n)	__release_region(&ioport_resource, (start), (n))
+#define check_mem_region(start,n)	__check_region(&iomem_resource, (start), (n))
+#define release_mem_region(start,n)	__release_region(&iomem_resource, (start), (n))
+
+extern int __check_region(struct resource *, resource_size_t, resource_size_t);
+extern void __release_region(struct resource *, resource_size_t,
+				resource_size_t);
+
+static inline int __deprecated check_region(resource_size_t s,
+						resource_size_t n)
+{
+	return __check_region(&ioport_resource, s, n);
+}
+
+/* Wrappers for managed devices */
+struct device;
+#define devm_request_region(dev,start,n,name) \
+	__devm_request_region(dev, &ioport_resource, (start), (n), (name))
+#define devm_request_mem_region(dev,start,n,name) \
+	__devm_request_region(dev, &iomem_resource, (start), (n), (name))
+
+extern struct resource * __devm_request_region(struct device *dev,
+				struct resource *parent, resource_size_t start,
+				resource_size_t n, const char *name);
+
+#define devm_release_region(dev, start, n) \
+	__devm_release_region(dev, &ioport_resource, (start), (n))
+#define devm_release_mem_region(dev, start, n) \
+	__devm_release_region(dev, &iomem_resource, (start), (n))
+
+extern void __devm_release_region(struct device *dev, struct resource *parent,
+				  resource_size_t start, resource_size_t n);
+extern int iomem_map_sanity_check(resource_size_t addr, unsigned long size);
+extern int iomem_is_exclusive(u64 addr);
+
+extern int
+walk_system_ram_range(unsigned long start_pfn, unsigned long nr_pages,
+		void *arg, int (*func)(unsigned long, unsigned long, void *));
+
+#endif /* __ASSEMBLY__ */
+#endif	/* _LINUX_IOPORT_H */
diff --git a/qemu/roms/u-boot/include/linux/kbuild.h b/qemu/roms/u-boot/include/linux/kbuild.h
new file mode 100644
index 000000000..ab7805a3b
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/kbuild.h
@@ -0,0 +1,20 @@
+/*
+ * Copied from Linux:
+ * commit 37487a56523d402e25650da16c337acf4cecd13d
+ * Author: Christoph Lameter <clameter@sgi.com>
+ */
+#ifndef __LINUX_KBUILD_H
+#define __LINUX_KBUILD_H
+
+#define DEFINE(sym, val) \
+	asm volatile("\n->" #sym " %0 " #val : : "i" (val))
+
+#define BLANK() asm volatile("\n->" : : )
+
+#define OFFSET(sym, str, mem) \
+	DEFINE(sym, offsetof(struct str, mem))
+
+#define COMMENT(x) \
+	asm volatile("\n->#" x)
+
+#endif
diff --git a/qemu/roms/u-boot/include/linux/linkage.h b/qemu/roms/u-boot/include/linux/linkage.h
new file mode 100644
index 000000000..7435fcd02
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/linkage.h
@@ -0,0 +1,68 @@
+/*
+ * U-boot - linkage.h
+ *
+ * Copyright (c) 2005-2007 Analog Devices Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _LINUX_LINKAGE_H
+#define _LINUX_LINKAGE_H
+
+#include <asm/linkage.h>
+
+#ifdef __cplusplus
+#define CPP_ASMLINKAGE		extern "C"
+#else
+#define CPP_ASMLINKAGE
+#endif
+
+#define asmlinkage CPP_ASMLINKAGE
+
+#define SYMBOL_NAME_STR(X)	#X
+#define SYMBOL_NAME(X)		X
+#ifdef __STDC__
+#define SYMBOL_NAME_LABEL(X)	X##:
+#else
+#define SYMBOL_NAME_LABEL(X)	X:
+#endif
+
+#ifndef __ALIGN
+#define __ALIGN .align		4
+#endif
+
+#ifndef __ALIGN_STR
+#define __ALIGN_STR		".align 4"
+#endif
+
+#ifdef __ASSEMBLY__
+
+#define ALIGN			__ALIGN
+#define ALIGN_STR		__ALIGN_STR
+
+#define LENTRY(name) \
+	ALIGN; \
+	SYMBOL_NAME_LABEL(name)
+
+#define ENTRY(name) \
+	.globl SYMBOL_NAME(name); \
+	LENTRY(name)
+
+#define WEAK(name) \
+	.weak SYMBOL_NAME(name); \
+	LENTRY(name)
+
+#ifndef END
+#define END(name) \
+	.size name, .-name
+#endif
+
+#ifndef ENDPROC
+#define ENDPROC(name) \
+	.type name STT_FUNC; \
+	END(name)
+#endif
+
+#endif
+
+#endif
diff --git a/qemu/roms/u-boot/include/linux/linux_string.h b/qemu/roms/u-boot/include/linux/linux_string.h
new file mode 100644
index 000000000..192b4c9be
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/linux_string.h
@@ -0,0 +1,8 @@
+#ifndef _LINUX_LINUX_STRING_H_
+#define _LINUX_LINUX_STRING_H_
+
+extern char * skip_spaces(const char *);
+
+extern char *strim(char *);
+
+#endif
diff --git a/qemu/roms/u-boot/include/linux/list.h b/qemu/roms/u-boot/include/linux/list.h
new file mode 100644
index 000000000..b78851c3d
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/list.h
@@ -0,0 +1,674 @@
+#ifndef _LINUX_LIST_H
+#define _LINUX_LIST_H
+
+#include <linux/stddef.h>
+#include <linux/poison.h>
+
+#ifndef ARCH_HAS_PREFETCH
+#define ARCH_HAS_PREFETCH
+static inline void prefetch(const void *x) {;}
+#endif
+
+/*
+ * Simple doubly linked list implementation.
+ *
+ * Some of the internal functions ("__xxx") are useful when
+ * manipulating whole lists rather than single entries, as
+ * sometimes we already know the next/prev entries and we can
+ * generate better code by using them directly rather than
+ * using the generic single-entry routines.
+ */
+
+struct list_head {
+	struct list_head *next, *prev;
+};
+
+#define LIST_HEAD_INIT(name) { &(name), &(name) }
+
+#define LIST_HEAD(name) \
+	struct list_head name = LIST_HEAD_INIT(name)
+
+static inline void INIT_LIST_HEAD(struct list_head *list)
+{
+	list->next = list;
+	list->prev = list;
+}
+
+/*
+ * Insert a new entry between two known consecutive entries.
+ *
+ * This is only for internal list manipulation where we know
+ * the prev/next entries already!
+ */
+static inline void __list_add(struct list_head *new,
+			      struct list_head *prev,
+			      struct list_head *next)
+{
+	next->prev = new;
+	new->next = next;
+	new->prev = prev;
+	prev->next = new;
+}
+
+/**
+ * list_add - add a new entry
+ * @new: new entry to be added
+ * @head: list head to add it after
+ *
+ * Insert a new entry after the specified head.
+ * This is good for implementing stacks.
+ */
+static inline void list_add(struct list_head *new, struct list_head *head)
+{
+	__list_add(new, head, head->next);
+}
+
+/**
+ * list_add_tail - add a new entry
+ * @new: new entry to be added
+ * @head: list head to add it before
+ *
+ * Insert a new entry before the specified head.
+ * This is useful for implementing queues.
+ */
+static inline void list_add_tail(struct list_head *new, struct list_head *head)
+{
+	__list_add(new, head->prev, head);
+}
+
+/*
+ * Delete a list entry by making the prev/next entries
+ * point to each other.
+ *
+ * This is only for internal list manipulation where we know
+ * the prev/next entries already!
+ */
+static inline void __list_del(struct list_head *prev, struct list_head *next)
+{
+	next->prev = prev;
+	prev->next = next;
+}
+
+/**
+ * list_del - deletes entry from list.
+ * @entry: the element to delete from the list.
+ * Note: list_empty() on entry does not return true after this, the entry is
+ * in an undefined state.
+ */
+static inline void list_del(struct list_head *entry)
+{
+	__list_del(entry->prev, entry->next);
+	entry->next = LIST_POISON1;
+	entry->prev = LIST_POISON2;
+}
+
+/**
+ * list_replace - replace old entry by new one
+ * @old : the element to be replaced
+ * @new : the new element to insert
+ *
+ * If @old was empty, it will be overwritten.
+ */
+static inline void list_replace(struct list_head *old,
+				struct list_head *new)
+{
+	new->next = old->next;
+	new->next->prev = new;
+	new->prev = old->prev;
+	new->prev->next = new;
+}
+
+static inline void list_replace_init(struct list_head *old,
+					struct list_head *new)
+{
+	list_replace(old, new);
+	INIT_LIST_HEAD(old);
+}
+
+/**
+ * list_del_init - deletes entry from list and reinitialize it.
+ * @entry: the element to delete from the list.
+ */
+static inline void list_del_init(struct list_head *entry)
+{
+	__list_del(entry->prev, entry->next);
+	INIT_LIST_HEAD(entry);
+}
+
+/**
+ * list_move - delete from one list and add as another's head
+ * @list: the entry to move
+ * @head: the head that will precede our entry
+ */
+static inline void list_move(struct list_head *list, struct list_head *head)
+{
+	__list_del(list->prev, list->next);
+	list_add(list, head);
+}
+
+/**
+ * list_move_tail - delete from one list and add as another's tail
+ * @list: the entry to move
+ * @head: the head that will follow our entry
+ */
+static inline void list_move_tail(struct list_head *list,
+				  struct list_head *head)
+{
+	__list_del(list->prev, list->next);
+	list_add_tail(list, head);
+}
+
+/**
+ * list_is_last - tests whether @list is the last entry in list @head
+ * @list: the entry to test
+ * @head: the head of the list
+ */
+static inline int list_is_last(const struct list_head *list,
+				const struct list_head *head)
+{
+	return list->next == head;
+}
+
+/**
+ * list_empty - tests whether a list is empty
+ * @head: the list to test.
+ */
+static inline int list_empty(const struct list_head *head)
+{
+	return head->next == head;
+}
+
+/**
+ * list_empty_careful - tests whether a list is empty and not being modified
+ * @head: the list to test
+ *
+ * Description:
+ * tests whether a list is empty _and_ checks that no other CPU might be
+ * in the process of modifying either member (next or prev)
+ *
+ * NOTE: using list_empty_careful() without synchronization
+ * can only be safe if the only activity that can happen
+ * to the list entry is list_del_init(). Eg. it cannot be used
+ * if another CPU could re-list_add() it.
+ */
+static inline int list_empty_careful(const struct list_head *head)
+{
+	struct list_head *next = head->next;
+	return (next == head) && (next == head->prev);
+}
+
+/**
+ * list_is_singular - tests whether a list has just one entry.
+ * @head: the list to test.
+ */
+static inline int list_is_singular(const struct list_head *head)
+{
+	return !list_empty(head) && (head->next == head->prev);
+}
+
+static inline void __list_cut_position(struct list_head *list,
+		struct list_head *head, struct list_head *entry)
+{
+	struct list_head *new_first = entry->next;
+	list->next = head->next;
+	list->next->prev = list;
+	list->prev = entry;
+	entry->next = list;
+	head->next = new_first;
+	new_first->prev = head;
+}
+
+/**
+ * list_cut_position - cut a list into two
+ * @list: a new list to add all removed entries
+ * @head: a list with entries
+ * @entry: an entry within head, could be the head itself
+ *	and if so we won't cut the list
+ *
+ * This helper moves the initial part of @head, up to and
+ * including @entry, from @head to @list. You should
+ * pass on @entry an element you know is on @head. @list
+ * should be an empty list or a list you do not care about
+ * losing its data.
+ *
+ */
+static inline void list_cut_position(struct list_head *list,
+		struct list_head *head, struct list_head *entry)
+{
+	if (list_empty(head))
+		return;
+	if (list_is_singular(head) &&
+		(head->next != entry && head != entry))
+		return;
+	if (entry == head)
+		INIT_LIST_HEAD(list);
+	else
+		__list_cut_position(list, head, entry);
+}
+
+static inline void __list_splice(const struct list_head *list,
+				 struct list_head *prev,
+				 struct list_head *next)
+{
+	struct list_head *first = list->next;
+	struct list_head *last = list->prev;
+
+	first->prev = prev;
+	prev->next = first;
+
+	last->next = next;
+	next->prev = last;
+}
+
+/**
+ * list_splice - join two lists, this is designed for stacks
+ * @list: the new list to add.
+ * @head: the place to add it in the first list.
+ */
+static inline void list_splice(const struct list_head *list,
+				struct list_head *head)
+{
+	if (!list_empty(list))
+		__list_splice(list, head, head->next);
+}
+
+/**
+ * list_splice_tail - join two lists, each list being a queue
+ * @list: the new list to add.
+ * @head: the place to add it in the first list.
+ */
+static inline void list_splice_tail(struct list_head *list,
+				struct list_head *head)
+{
+	if (!list_empty(list))
+		__list_splice(list, head->prev, head);
+}
+
+/**
+ * list_splice_init - join two lists and reinitialise the emptied list.
+ * @list: the new list to add.
+ * @head: the place to add it in the first list.
+ *
+ * The list at @list is reinitialised
+ */
+static inline void list_splice_init(struct list_head *list,
+				    struct list_head *head)
+{
+	if (!list_empty(list)) {
+		__list_splice(list, head, head->next);
+		INIT_LIST_HEAD(list);
+	}
+}
+
+/**
+ * list_splice_tail_init - join two lists and reinitialise the emptied list
+ * @list: the new list to add.
+ * @head: the place to add it in the first list.
+ *
+ * Each of the lists is a queue.
+ * The list at @list is reinitialised
+ */
+static inline void list_splice_tail_init(struct list_head *list,
+					 struct list_head *head)
+{
+	if (!list_empty(list)) {
+		__list_splice(list, head->prev, head);
+		INIT_LIST_HEAD(list);
+	}
+}
+
+/**
+ * list_entry - get the struct for this entry
+ * @ptr:	the &struct list_head pointer.
+ * @type:	the type of the struct this is embedded in.
+ * @member:	the name of the list_struct within the struct.
+ */
+#define list_entry(ptr, type, member) \
+	container_of(ptr, type, member)
+
+/**
+ * list_first_entry - get the first element from a list
+ * @ptr:	the list head to take the element from.
+ * @type:	the type of the struct this is embedded in.
+ * @member:	the name of the list_struct within the struct.
+ *
+ * Note, that list is expected to be not empty.
+ */
+#define list_first_entry(ptr, type, member) \
+	list_entry((ptr)->next, type, member)
+
+/**
+ * list_for_each	-	iterate over a list
+ * @pos:	the &struct list_head to use as a loop cursor.
+ * @head:	the head for your list.
+ */
+#define list_for_each(pos, head) \
+	for (pos = (head)->next; prefetch(pos->next), pos != (head); \
+		pos = pos->next)
+
+/**
+ * __list_for_each	-	iterate over a list
+ * @pos:	the &struct list_head to use as a loop cursor.
+ * @head:	the head for your list.
+ *
+ * This variant differs from list_for_each() in that it's the
+ * simplest possible list iteration code, no prefetching is done.
+ * Use this for code that knows the list to be very short (empty
+ * or 1 entry) most of the time.
+ */
+#define __list_for_each(pos, head) \
+	for (pos = (head)->next; pos != (head); pos = pos->next)
+
+/**
+ * list_for_each_prev	-	iterate over a list backwards
+ * @pos:	the &struct list_head to use as a loop cursor.
+ * @head:	the head for your list.
+ */
+#define list_for_each_prev(pos, head) \
+	for (pos = (head)->prev; prefetch(pos->prev), pos != (head); \
+		pos = pos->prev)
+
+/**
+ * list_for_each_safe - iterate over a list safe against removal of list entry
+ * @pos:	the &struct list_head to use as a loop cursor.
+ * @n:		another &struct list_head to use as temporary storage
+ * @head:	the head for your list.
+ */
+#define list_for_each_safe(pos, n, head) \
+	for (pos = (head)->next, n = pos->next; pos != (head); \
+		pos = n, n = pos->next)
+
+/**
+ * list_for_each_prev_safe - iterate over a list backwards safe against removal of list entry
+ * @pos:	the &struct list_head to use as a loop cursor.
+ * @n:		another &struct list_head to use as temporary storage
+ * @head:	the head for your list.
+ */
+#define list_for_each_prev_safe(pos, n, head) \
+	for (pos = (head)->prev, n = pos->prev; \
+	     prefetch(pos->prev), pos != (head); \
+	     pos = n, n = pos->prev)
+
+/**
+ * list_for_each_entry	-	iterate over list of given type
+ * @pos:	the type * to use as a loop cursor.
+ * @head:	the head for your list.
+ * @member:	the name of the list_struct within the struct.
+ */
+#define list_for_each_entry(pos, head, member)				\
+	for (pos = list_entry((head)->next, typeof(*pos), member);	\
+	     prefetch(pos->member.next), &pos->member != (head);	\
+	     pos = list_entry(pos->member.next, typeof(*pos), member))
+
+/**
+ * list_for_each_entry_reverse - iterate backwards over list of given type.
+ * @pos:	the type * to use as a loop cursor.
+ * @head:	the head for your list.
+ * @member:	the name of the list_struct within the struct.
+ */
+#define list_for_each_entry_reverse(pos, head, member)			\
+	for (pos = list_entry((head)->prev, typeof(*pos), member);	\
+	     prefetch(pos->member.prev), &pos->member != (head);	\
+	     pos = list_entry(pos->member.prev, typeof(*pos), member))
+
+/**
+ * list_prepare_entry - prepare a pos entry for use in list_for_each_entry_continue()
+ * @pos:	the type * to use as a start point
+ * @head:	the head of the list
+ * @member:	the name of the list_struct within the struct.
+ *
+ * Prepares a pos entry for use as a start point in list_for_each_entry_continue().
+ */
+#define list_prepare_entry(pos, head, member) \
+	((pos) ? : list_entry(head, typeof(*pos), member))
+
+/**
+ * list_for_each_entry_continue - continue iteration over list of given type
+ * @pos:	the type * to use as a loop cursor.
+ * @head:	the head for your list.
+ * @member:	the name of the list_struct within the struct.
+ *
+ * Continue to iterate over list of given type, continuing after
+ * the current position.
+ */
+#define list_for_each_entry_continue(pos, head, member) 		\
+	for (pos = list_entry(pos->member.next, typeof(*pos), member);	\
+	     prefetch(pos->member.next), &pos->member != (head);	\
+	     pos = list_entry(pos->member.next, typeof(*pos), member))
+
+/**
+ * list_for_each_entry_continue_reverse - iterate backwards from the given point
+ * @pos:	the type * to use as a loop cursor.
+ * @head:	the head for your list.
+ * @member:	the name of the list_struct within the struct.
+ *
+ * Start to iterate over list of given type backwards, continuing after
+ * the current position.
+ */
+#define list_for_each_entry_continue_reverse(pos, head, member)		\
+	for (pos = list_entry(pos->member.prev, typeof(*pos), member);	\
+	     prefetch(pos->member.prev), &pos->member != (head);	\
+	     pos = list_entry(pos->member.prev, typeof(*pos), member))
+
+/**
+ * list_for_each_entry_from - iterate over list of given type from the current point
+ * @pos:	the type * to use as a loop cursor.
+ * @head:	the head for your list.
+ * @member:	the name of the list_struct within the struct.
+ *
+ * Iterate over list of given type, continuing from current position.
+ */
+#define list_for_each_entry_from(pos, head, member)			\
+	for (; prefetch(pos->member.next), &pos->member != (head);	\
+	     pos = list_entry(pos->member.next, typeof(*pos), member))
+
+/**
+ * list_for_each_entry_safe - iterate over list of given type safe against removal of list entry
+ * @pos:	the type * to use as a loop cursor.
+ * @n:		another type * to use as temporary storage
+ * @head:	the head for your list.
+ * @member:	the name of the list_struct within the struct.
+ */
+#define list_for_each_entry_safe(pos, n, head, member)			\
+	for (pos = list_entry((head)->next, typeof(*pos), member),	\
+		n = list_entry(pos->member.next, typeof(*pos), member);	\
+	     &pos->member != (head);					\
+	     pos = n, n = list_entry(n->member.next, typeof(*n), member))
+
+/**
+ * list_for_each_entry_safe_continue
+ * @pos:	the type * to use as a loop cursor.
+ * @n:		another type * to use as temporary storage
+ * @head:	the head for your list.
+ * @member:	the name of the list_struct within the struct.
+ *
+ * Iterate over list of given type, continuing after current point,
+ * safe against removal of list entry.
+ */
+#define list_for_each_entry_safe_continue(pos, n, head, member) 		\
+	for (pos = list_entry(pos->member.next, typeof(*pos), member),		\
+		n = list_entry(pos->member.next, typeof(*pos), member);		\
+	     &pos->member != (head);						\
+	     pos = n, n = list_entry(n->member.next, typeof(*n), member))
+
+/**
+ * list_for_each_entry_safe_from
+ * @pos:	the type * to use as a loop cursor.
+ * @n:		another type * to use as temporary storage
+ * @head:	the head for your list.
+ * @member:	the name of the list_struct within the struct.
+ *
+ * Iterate over list of given type from current point, safe against
+ * removal of list entry.
+ */
+#define list_for_each_entry_safe_from(pos, n, head, member)			\
+	for (n = list_entry(pos->member.next, typeof(*pos), member);		\
+	     &pos->member != (head);						\
+	     pos = n, n = list_entry(n->member.next, typeof(*n), member))
+
+/**
+ * list_for_each_entry_safe_reverse
+ * @pos:	the type * to use as a loop cursor.
+ * @n:		another type * to use as temporary storage
+ * @head:	the head for your list.
+ * @member:	the name of the list_struct within the struct.
+ *
+ * Iterate backwards over list of given type, safe against removal
+ * of list entry.
+ */
+#define list_for_each_entry_safe_reverse(pos, n, head, member)		\
+	for (pos = list_entry((head)->prev, typeof(*pos), member),	\
+		n = list_entry(pos->member.prev, typeof(*pos), member);	\
+	     &pos->member != (head);					\
+	     pos = n, n = list_entry(n->member.prev, typeof(*n), member))
+
+/*
+ * Double linked lists with a single pointer list head.
+ * Mostly useful for hash tables where the two pointer list head is
+ * too wasteful.
+ * You lose the ability to access the tail in O(1).
+ */
+
+struct hlist_head {
+	struct hlist_node *first;
+};
+
+struct hlist_node {
+	struct hlist_node *next, **pprev;
+};
+
+#define HLIST_HEAD_INIT { .first = NULL }
+#define HLIST_HEAD(name) struct hlist_head name = {  .first = NULL }
+#define INIT_HLIST_HEAD(ptr) ((ptr)->first = NULL)
+static inline void INIT_HLIST_NODE(struct hlist_node *h)
+{
+	h->next = NULL;
+	h->pprev = NULL;
+}
+
+static inline int hlist_unhashed(const struct hlist_node *h)
+{
+	return !h->pprev;
+}
+
+static inline int hlist_empty(const struct hlist_head *h)
+{
+	return !h->first;
+}
+
+static inline void __hlist_del(struct hlist_node *n)
+{
+	struct hlist_node *next = n->next;
+	struct hlist_node **pprev = n->pprev;
+	*pprev = next;
+	if (next)
+		next->pprev = pprev;
+}
+
+static inline void hlist_del(struct hlist_node *n)
+{
+	__hlist_del(n);
+	n->next = LIST_POISON1;
+	n->pprev = LIST_POISON2;
+}
+
+static inline void hlist_del_init(struct hlist_node *n)
+{
+	if (!hlist_unhashed(n)) {
+		__hlist_del(n);
+		INIT_HLIST_NODE(n);
+	}
+}
+
+static inline void hlist_add_head(struct hlist_node *n, struct hlist_head *h)
+{
+	struct hlist_node *first = h->first;
+	n->next = first;
+	if (first)
+		first->pprev = &n->next;
+	h->first = n;
+	n->pprev = &h->first;
+}
+
+/* next must be != NULL */
+static inline void hlist_add_before(struct hlist_node *n,
+					struct hlist_node *next)
+{
+	n->pprev = next->pprev;
+	n->next = next;
+	next->pprev = &n->next;
+	*(n->pprev) = n;
+}
+
+static inline void hlist_add_after(struct hlist_node *n,
+					struct hlist_node *next)
+{
+	next->next = n->next;
+	n->next = next;
+	next->pprev = &n->next;
+
+	if(next->next)
+		next->next->pprev  = &next->next;
+}
+
+#define hlist_entry(ptr, type, member) container_of(ptr,type,member)
+
+#define hlist_for_each(pos, head) \
+	for (pos = (head)->first; pos && ({ prefetch(pos->next); 1; }); \
+	     pos = pos->next)
+
+#define hlist_for_each_safe(pos, n, head) \
+	for (pos = (head)->first; pos && ({ n = pos->next; 1; }); \
+	     pos = n)
+
+/**
+ * hlist_for_each_entry	- iterate over list of given type
+ * @tpos:	the type * to use as a loop cursor.
+ * @pos:	the &struct hlist_node to use as a loop cursor.
+ * @head:	the head for your list.
+ * @member:	the name of the hlist_node within the struct.
+ */
+#define hlist_for_each_entry(tpos, pos, head, member)			 \
+	for (pos = (head)->first;					 \
+	     pos && ({ prefetch(pos->next); 1;}) &&			 \
+		({ tpos = hlist_entry(pos, typeof(*tpos), member); 1;}); \
+	     pos = pos->next)
+
+/**
+ * hlist_for_each_entry_continue - iterate over a hlist continuing after current point
+ * @tpos:	the type * to use as a loop cursor.
+ * @pos:	the &struct hlist_node to use as a loop cursor.
+ * @member:	the name of the hlist_node within the struct.
+ */
+#define hlist_for_each_entry_continue(tpos, pos, member)		 \
+	for (pos = (pos)->next;						 \
+	     pos && ({ prefetch(pos->next); 1;}) &&			 \
+		({ tpos = hlist_entry(pos, typeof(*tpos), member); 1;}); \
+	     pos = pos->next)
+
+/**
+ * hlist_for_each_entry_from - iterate over a hlist continuing from current point
+ * @tpos:	the type * to use as a loop cursor.
+ * @pos:	the &struct hlist_node to use as a loop cursor.
+ * @member:	the name of the hlist_node within the struct.
+ */
+#define hlist_for_each_entry_from(tpos, pos, member)			 \
+	for (; pos && ({ prefetch(pos->next); 1;}) &&			 \
+		({ tpos = hlist_entry(pos, typeof(*tpos), member); 1;}); \
+	     pos = pos->next)
+
+/**
+ * hlist_for_each_entry_safe - iterate over list of given type safe against removal of list entry
+ * @tpos:	the type * to use as a loop cursor.
+ * @pos:	the &struct hlist_node to use as a loop cursor.
+ * @n:		another &struct hlist_node to use as temporary storage
+ * @head:	the head for your list.
+ * @member:	the name of the hlist_node within the struct.
+ */
+#define hlist_for_each_entry_safe(tpos, pos, n, head, member)		 \
+	for (pos = (head)->first;					 \
+	     pos && ({ n = pos->next; 1; }) &&				 \
+		({ tpos = hlist_entry(pos, typeof(*tpos), member); 1;}); \
+	     pos = n)
+
+#endif
diff --git a/qemu/roms/u-boot/include/linux/lzo.h b/qemu/roms/u-boot/include/linux/lzo.h
new file mode 100644
index 000000000..88687faba
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/lzo.h
@@ -0,0 +1,48 @@
+#ifndef __LZO_H__
+#define __LZO_H__
+/*
+ *  LZO Public Kernel Interface
+ *  A mini subset of the LZO real-time data compression library
+ *
+ *  Copyright (C) 1996-2005 Markus F.X.J. Oberhumer <markus@oberhumer.com>
+ *
+ *  The full LZO package can be found at:
+ *  http://www.oberhumer.com/opensource/lzo/
+ *
+ *  Changed for kernel use by:
+ *  Nitin Gupta <nitingupta910@gmail.com>
+ *  Richard Purdie <rpurdie@openedhand.com>
+ */
+
+#define LZO1X_MEM_COMPRESS	(16384 * sizeof(unsigned char *))
+#define LZO1X_1_MEM_COMPRESS	LZO1X_MEM_COMPRESS
+
+#define lzo1x_worst_compress(x) ((x) + ((x) / 16) + 64 + 3)
+
+/* This requires 'workmem' of size LZO1X_1_MEM_COMPRESS */
+int lzo1x_1_compress(const unsigned char *src, size_t src_len,
+			unsigned char *dst, size_t *dst_len, void *wrkmem);
+
+/* safe decompression with overrun testing */
+int lzo1x_decompress_safe(const unsigned char *src, size_t src_len,
+			unsigned char *dst, size_t *dst_len);
+
+/* decompress lzop format */
+int lzop_decompress(const unsigned char *src, size_t src_len,
+		    unsigned char *dst, size_t *dst_len);
+
+/*
+ * Return values (< 0 = Error)
+ */
+#define LZO_E_OK			0
+#define LZO_E_ERROR			(-1)
+#define LZO_E_OUT_OF_MEMORY		(-2)
+#define LZO_E_NOT_COMPRESSIBLE		(-3)
+#define LZO_E_INPUT_OVERRUN		(-4)
+#define LZO_E_OUTPUT_OVERRUN		(-5)
+#define LZO_E_LOOKBEHIND_OVERRUN	(-6)
+#define LZO_E_EOF_NOT_FOUND		(-7)
+#define LZO_E_INPUT_NOT_CONSUMED	(-8)
+#define LZO_E_NOT_YET_IMPLEMENTED	(-9)
+
+#endif
diff --git a/qemu/roms/u-boot/include/linux/math64.h b/qemu/roms/u-boot/include/linux/math64.h
new file mode 100644
index 000000000..6d760d75c
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/math64.h
@@ -0,0 +1,85 @@
+#ifndef _LINUX_MATH64_H
+#define _LINUX_MATH64_H
+
+#include <linux/types.h>
+
+#if BITS_PER_LONG == 64
+
+/**
+ * div_u64_rem - unsigned 64bit divide with 32bit divisor with remainder
+ *
+ * This is commonly provided by 32bit archs to provide an optimized 64bit
+ * divide.
+ */
+static inline u64 div_u64_rem(u64 dividend, u32 divisor, u32 *remainder)
+{
+	*remainder = dividend % divisor;
+	return dividend / divisor;
+}
+
+/**
+ * div_s64_rem - signed 64bit divide with 32bit divisor with remainder
+ */
+static inline s64 div_s64_rem(s64 dividend, s32 divisor, s32 *remainder)
+{
+	*remainder = dividend % divisor;
+	return dividend / divisor;
+}
+
+/**
+ * div64_u64 - unsigned 64bit divide with 64bit divisor
+ */
+static inline u64 div64_u64(u64 dividend, u64 divisor)
+{
+	return dividend / divisor;
+}
+
+#elif BITS_PER_LONG == 32
+
+#ifndef div_u64_rem
+static inline u64 div_u64_rem(u64 dividend, u32 divisor, u32 *remainder)
+{
+	*remainder = do_div(dividend, divisor);
+	return dividend;
+}
+#endif
+
+#ifndef div_s64_rem
+extern s64 div_s64_rem(s64 dividend, s32 divisor, s32 *remainder);
+#endif
+
+#ifndef div64_u64
+extern u64 div64_u64(u64 dividend, u64 divisor);
+#endif
+
+#endif /* BITS_PER_LONG */
+
+/**
+ * div_u64 - unsigned 64bit divide with 32bit divisor
+ *
+ * This is the most common 64bit divide and should be used if possible,
+ * as many 32bit archs can optimize this variant better than a full 64bit
+ * divide.
+ */
+#ifndef div_u64
+static inline u64 div_u64(u64 dividend, u32 divisor)
+{
+	u32 remainder;
+	return div_u64_rem(dividend, divisor, &remainder);
+}
+#endif
+
+/**
+ * div_s64 - signed 64bit divide with 32bit divisor
+ */
+#ifndef div_s64
+static inline s64 div_s64(s64 dividend, s32 divisor)
+{
+	s32 remainder;
+	return div_s64_rem(dividend, divisor, &remainder);
+}
+#endif
+
+u32 iter_div_u64_rem(u64 dividend, u32 divisor, u64 *remainder);
+
+#endif /* _LINUX_MATH64_H */
diff --git a/qemu/roms/u-boot/include/linux/mc146818rtc.h b/qemu/roms/u-boot/include/linux/mc146818rtc.h
new file mode 100644
index 000000000..0644d92b3
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/mc146818rtc.h
@@ -0,0 +1,86 @@
+/* mc146818rtc.h - register definitions for the Real-Time-Clock / CMOS RAM
+ * Copyright Torsten Duwe <duwe@informatik.uni-erlangen.de> 1993
+ * derived from Data Sheet, Copyright Motorola 1984 (!).
+ * It was written to be part of the Linux operating system.
+ */
+/* permission is hereby granted to copy, modify and redistribute this code
+ * in terms of the GNU Library General Public License, Version 2 or later,
+ * at your option.
+ */
+
+#ifndef _MC146818RTC_H
+#define _MC146818RTC_H
+
+#include <asm/io.h>
+#include <linux/rtc.h>          /* get the user-level API */
+#include <asm/mc146818rtc.h>        /* register access macros */
+
+/**********************************************************************
+ * register summary
+ **********************************************************************/
+#define RTC_SECONDS     0
+#define RTC_SECONDS_ALARM   1
+#define RTC_MINUTES     2
+#define RTC_MINUTES_ALARM   3
+#define RTC_HOURS       4
+#define RTC_HOURS_ALARM     5
+/* RTC_*_alarm is always true if 2 MSBs are set */
+# define RTC_ALARM_DONT_CARE    0xC0
+
+#define RTC_DAY_OF_WEEK     6
+#define RTC_DAY_OF_MONTH    7
+#define RTC_MONTH       8
+#define RTC_YEAR        9
+
+/* control registers - Moto names
+ */
+#define RTC_REG_A       10
+#define RTC_REG_B       11
+#define RTC_REG_C       12
+#define RTC_REG_D       13
+
+/**********************************************************************
+ * register details
+ **********************************************************************/
+#define RTC_FREQ_SELECT RTC_REG_A
+
+/* update-in-progress  - set to "1" 244 microsecs before RTC goes off the bus,
+ * reset after update (may take 1.984ms @ 32768Hz RefClock) is complete,
+ * totalling to a max high interval of 2.228 ms.
+ */
+# define RTC_UIP        0x80
+# define RTC_DIV_CTL        0x70
+   /* divider control: refclock values 4.194 / 1.049 MHz / 32.768 kHz */
+#  define RTC_REF_CLCK_4MHZ 0x00
+#  define RTC_REF_CLCK_1MHZ 0x10
+#  define RTC_REF_CLCK_32KHZ    0x20
+   /* 2 values for divider stage reset, others for "testing purposes only" */
+#  define RTC_DIV_RESET1    0x60
+#  define RTC_DIV_RESET2    0x70
+  /* Periodic intr. / Square wave rate select. 0=none, 1=32.8kHz,... 15=2Hz */
+# define RTC_RATE_SELECT    0x0F
+
+/**********************************************************************/
+#define RTC_CONTROL RTC_REG_B
+# define RTC_SET 0x80       /* disable updates for clock setting */
+# define RTC_PIE 0x40       /* periodic interrupt enable */
+# define RTC_AIE 0x20       /* alarm interrupt enable */
+# define RTC_UIE 0x10       /* update-finished interrupt enable */
+# define RTC_SQWE 0x08      /* enable square-wave output */
+# define RTC_DM_BINARY 0x04 /* all time/date values are BCD if clear */
+# define RTC_24H 0x02       /* 24 hour mode - else hours bit 7 means pm */
+# define RTC_DST_EN 0x01    /* auto switch DST - works f. USA only */
+
+/**********************************************************************/
+#define RTC_INTR_FLAGS  RTC_REG_C
+/* caution - cleared by read */
+# define RTC_IRQF 0x80      /* any of the following 3 is active */
+# define RTC_PF 0x40
+# define RTC_AF 0x20
+# define RTC_UF 0x10
+
+/**********************************************************************/
+#define RTC_VALID   RTC_REG_D
+# define RTC_VRT 0x80       /* valid RAM and time */
+/**********************************************************************/
+#endif /* _MC146818RTC_H */
diff --git a/qemu/roms/u-boot/include/linux/mdio.h b/qemu/roms/u-boot/include/linux/mdio.h
new file mode 100644
index 000000000..ea2060846
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/mdio.h
@@ -0,0 +1,284 @@
+/*
+ * linux/mdio.h: definitions for MDIO (clause 45) transceivers
+ * Copyright 2006-2009 Solarflare Communications Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation, incorporated herein by reference.
+ */
+
+#ifndef __LINUX_MDIO_H__
+#define __LINUX_MDIO_H__
+
+#include <linux/mii.h>
+
+/* MDIO Manageable Devices (MMDs). */
+#define MDIO_MMD_PMAPMD		1	/* Physical Medium Attachment/
+					 * Physical Medium Dependent */
+#define MDIO_MMD_WIS		2	/* WAN Interface Sublayer */
+#define MDIO_MMD_PCS		3	/* Physical Coding Sublayer */
+#define MDIO_MMD_PHYXS		4	/* PHY Extender Sublayer */
+#define MDIO_MMD_DTEXS		5	/* DTE Extender Sublayer */
+#define MDIO_MMD_TC		6	/* Transmission Convergence */
+#define MDIO_MMD_AN		7	/* Auto-Negotiation */
+#define MDIO_MMD_C22EXT		29	/* Clause 22 extension */
+#define MDIO_MMD_VEND1		30	/* Vendor specific 1 */
+#define MDIO_MMD_VEND2		31	/* Vendor specific 2 */
+
+/* Generic MDIO registers. */
+#define MDIO_CTRL1		MII_BMCR
+#define MDIO_STAT1		MII_BMSR
+#define MDIO_DEVID1		MII_PHYSID1
+#define MDIO_DEVID2		MII_PHYSID2
+#define MDIO_SPEED		4	/* Speed ability */
+#define MDIO_DEVS1		5	/* Devices in package */
+#define MDIO_DEVS2		6
+#define MDIO_CTRL2		7	/* 10G control 2 */
+#define MDIO_STAT2		8	/* 10G status 2 */
+#define MDIO_PMA_TXDIS		9	/* 10G PMA/PMD transmit disable */
+#define MDIO_PMA_RXDET		10	/* 10G PMA/PMD receive signal detect */
+#define MDIO_PMA_EXTABLE	11	/* 10G PMA/PMD extended ability */
+#define MDIO_PKGID1		14	/* Package identifier */
+#define MDIO_PKGID2		15
+#define MDIO_AN_ADVERTISE	16	/* AN advertising (base page) */
+#define MDIO_AN_LPA		19	/* AN LP abilities (base page) */
+#define MDIO_PHYXS_LNSTAT	24	/* PHY XGXS lane state */
+
+/* Media-dependent registers. */
+#define MDIO_PMA_10GBT_SWAPPOL	130	/* 10GBASE-T pair swap & polarity */
+#define MDIO_PMA_10GBT_TXPWR	131	/* 10GBASE-T TX power control */
+#define MDIO_PMA_10GBT_SNR	133	/* 10GBASE-T SNR margin, lane A.
+					 * Lanes B-D are numbered 134-136. */
+#define MDIO_PMA_10GBR_FECABLE	170	/* 10GBASE-R FEC ability */
+#define MDIO_PCS_10GBX_STAT1	24	/* 10GBASE-X PCS status 1 */
+#define MDIO_PCS_10GBRT_STAT1	32	/* 10GBASE-R/-T PCS status 1 */
+#define MDIO_PCS_10GBRT_STAT2	33	/* 10GBASE-R/-T PCS status 2 */
+#define MDIO_AN_10GBT_CTRL	32	/* 10GBASE-T auto-negotiation control */
+#define MDIO_AN_10GBT_STAT	33	/* 10GBASE-T auto-negotiation status */
+#define MDIO_AN_EEE_ADV		60	/* EEE advertisement */
+
+/* LASI (Link Alarm Status Interrupt) registers, defined by XENPAK MSA. */
+#define MDIO_PMA_LASI_RXCTRL	0x9000	/* RX_ALARM control */
+#define MDIO_PMA_LASI_TXCTRL	0x9001	/* TX_ALARM control */
+#define MDIO_PMA_LASI_CTRL	0x9002	/* LASI control */
+#define MDIO_PMA_LASI_RXSTAT	0x9003	/* RX_ALARM status */
+#define MDIO_PMA_LASI_TXSTAT	0x9004	/* TX_ALARM status */
+#define MDIO_PMA_LASI_STAT	0x9005	/* LASI status */
+
+/* Control register 1. */
+/* Enable extended speed selection */
+#define MDIO_CTRL1_SPEEDSELEXT		(BMCR_SPEED1000 | BMCR_SPEED100)
+/* All speed selection bits */
+#define MDIO_CTRL1_SPEEDSEL		(MDIO_CTRL1_SPEEDSELEXT | 0x003c)
+#define MDIO_CTRL1_FULLDPLX		BMCR_FULLDPLX
+#define MDIO_CTRL1_LPOWER		BMCR_PDOWN
+#define MDIO_CTRL1_RESET		BMCR_RESET
+#define MDIO_PMA_CTRL1_LOOPBACK		0x0001
+#define MDIO_PMA_CTRL1_SPEED1000	BMCR_SPEED1000
+#define MDIO_PMA_CTRL1_SPEED100		BMCR_SPEED100
+#define MDIO_PCS_CTRL1_LOOPBACK		BMCR_LOOPBACK
+#define MDIO_PHYXS_CTRL1_LOOPBACK	BMCR_LOOPBACK
+#define MDIO_AN_CTRL1_RESTART		BMCR_ANRESTART
+#define MDIO_AN_CTRL1_ENABLE		BMCR_ANENABLE
+#define MDIO_AN_CTRL1_XNP		0x2000	/* Enable extended next page */
+
+/* 10 Gb/s */
+#define MDIO_CTRL1_SPEED10G		(MDIO_CTRL1_SPEEDSELEXT | 0x00)
+/* 10PASS-TS/2BASE-TL */
+#define MDIO_CTRL1_SPEED10P2B		(MDIO_CTRL1_SPEEDSELEXT | 0x04)
+
+/* Status register 1. */
+#define MDIO_STAT1_LPOWERABLE		0x0002	/* Low-power ability */
+#define MDIO_STAT1_LSTATUS		BMSR_LSTATUS
+#define MDIO_STAT1_FAULT		0x0080	/* Fault */
+#define MDIO_AN_STAT1_LPABLE		0x0001	/* Link partner AN ability */
+#define MDIO_AN_STAT1_ABLE		BMSR_ANEGCAPABLE
+#define MDIO_AN_STAT1_RFAULT		BMSR_RFAULT
+#define MDIO_AN_STAT1_COMPLETE		BMSR_ANEGCOMPLETE
+#define MDIO_AN_STAT1_PAGE		0x0040	/* Page received */
+#define MDIO_AN_STAT1_XNP		0x0080	/* Extended next page status */
+
+/* Speed register. */
+#define MDIO_SPEED_10G			0x0001	/* 10G capable */
+#define MDIO_PMA_SPEED_2B		0x0002	/* 2BASE-TL capable */
+#define MDIO_PMA_SPEED_10P		0x0004	/* 10PASS-TS capable */
+#define MDIO_PMA_SPEED_1000		0x0010	/* 1000M capable */
+#define MDIO_PMA_SPEED_100		0x0020	/* 100M capable */
+#define MDIO_PMA_SPEED_10		0x0040	/* 10M capable */
+#define MDIO_PCS_SPEED_10P2B		0x0002	/* 10PASS-TS/2BASE-TL capable */
+
+/* Device present registers. */
+#define MDIO_DEVS_PRESENT(devad)	(1 << (devad))
+#define MDIO_DEVS_PMAPMD		MDIO_DEVS_PRESENT(MDIO_MMD_PMAPMD)
+#define MDIO_DEVS_WIS			MDIO_DEVS_PRESENT(MDIO_MMD_WIS)
+#define MDIO_DEVS_PCS			MDIO_DEVS_PRESENT(MDIO_MMD_PCS)
+#define MDIO_DEVS_PHYXS			MDIO_DEVS_PRESENT(MDIO_MMD_PHYXS)
+#define MDIO_DEVS_DTEXS			MDIO_DEVS_PRESENT(MDIO_MMD_DTEXS)
+#define MDIO_DEVS_TC			MDIO_DEVS_PRESENT(MDIO_MMD_TC)
+#define MDIO_DEVS_AN			MDIO_DEVS_PRESENT(MDIO_MMD_AN)
+#define MDIO_DEVS_C22EXT		MDIO_DEVS_PRESENT(MDIO_MMD_C22EXT)
+#define MDIO_DEVS_VEND1			MDIO_DEVS_PRESENT(MDIO_MMD_VEND1)
+#define MDIO_DEVS_VEND2			MDIO_DEVS_PRESENT(MDIO_MMD_VEND2)
+
+#define MDIO_DEVS_LINK			(MDIO_DEVS_PMAPMD | \
+					MDIO_DEVS_WIS | \
+					MDIO_DEVS_PCS | \
+					MDIO_DEVS_PHYXS | \
+					MDIO_DEVS_DTEXS | \
+					MDIO_DEVS_AN)
+
+/* Control register 2. */
+#define MDIO_PMA_CTRL2_TYPE		0x000f	/* PMA/PMD type selection */
+#define MDIO_PMA_CTRL2_10GBCX4		0x0000	/* 10GBASE-CX4 type */
+#define MDIO_PMA_CTRL2_10GBEW		0x0001	/* 10GBASE-EW type */
+#define MDIO_PMA_CTRL2_10GBLW		0x0002	/* 10GBASE-LW type */
+#define MDIO_PMA_CTRL2_10GBSW		0x0003	/* 10GBASE-SW type */
+#define MDIO_PMA_CTRL2_10GBLX4		0x0004	/* 10GBASE-LX4 type */
+#define MDIO_PMA_CTRL2_10GBER		0x0005	/* 10GBASE-ER type */
+#define MDIO_PMA_CTRL2_10GBLR		0x0006	/* 10GBASE-LR type */
+#define MDIO_PMA_CTRL2_10GBSR		0x0007	/* 10GBASE-SR type */
+#define MDIO_PMA_CTRL2_10GBLRM		0x0008	/* 10GBASE-LRM type */
+#define MDIO_PMA_CTRL2_10GBT		0x0009	/* 10GBASE-T type */
+#define MDIO_PMA_CTRL2_10GBKX4		0x000a	/* 10GBASE-KX4 type */
+#define MDIO_PMA_CTRL2_10GBKR		0x000b	/* 10GBASE-KR type */
+#define MDIO_PMA_CTRL2_1000BT		0x000c	/* 1000BASE-T type */
+#define MDIO_PMA_CTRL2_1000BKX		0x000d	/* 1000BASE-KX type */
+#define MDIO_PMA_CTRL2_100BTX		0x000e	/* 100BASE-TX type */
+#define MDIO_PMA_CTRL2_10BT		0x000f	/* 10BASE-T type */
+#define MDIO_PCS_CTRL2_TYPE		0x0003	/* PCS type selection */
+#define MDIO_PCS_CTRL2_10GBR		0x0000	/* 10GBASE-R type */
+#define MDIO_PCS_CTRL2_10GBX		0x0001	/* 10GBASE-X type */
+#define MDIO_PCS_CTRL2_10GBW		0x0002	/* 10GBASE-W type */
+#define MDIO_PCS_CTRL2_10GBT		0x0003	/* 10GBASE-T type */
+
+/* Status register 2. */
+#define MDIO_STAT2_RXFAULT		0x0400	/* Receive fault */
+#define MDIO_STAT2_TXFAULT		0x0800	/* Transmit fault */
+#define MDIO_STAT2_DEVPRST		0xc000	/* Device present */
+#define MDIO_STAT2_DEVPRST_VAL		0x8000	/* Device present value */
+#define MDIO_PMA_STAT2_LBABLE		0x0001	/* PMA loopback ability */
+#define MDIO_PMA_STAT2_10GBEW		0x0002	/* 10GBASE-EW ability */
+#define MDIO_PMA_STAT2_10GBLW		0x0004	/* 10GBASE-LW ability */
+#define MDIO_PMA_STAT2_10GBSW		0x0008	/* 10GBASE-SW ability */
+#define MDIO_PMA_STAT2_10GBLX4		0x0010	/* 10GBASE-LX4 ability */
+#define MDIO_PMA_STAT2_10GBER		0x0020	/* 10GBASE-ER ability */
+#define MDIO_PMA_STAT2_10GBLR		0x0040	/* 10GBASE-LR ability */
+#define MDIO_PMA_STAT2_10GBSR		0x0080	/* 10GBASE-SR ability */
+#define MDIO_PMD_STAT2_TXDISAB		0x0100	/* PMD TX disable ability */
+#define MDIO_PMA_STAT2_EXTABLE		0x0200	/* Extended abilities */
+#define MDIO_PMA_STAT2_RXFLTABLE	0x1000	/* Receive fault ability */
+#define MDIO_PMA_STAT2_TXFLTABLE	0x2000	/* Transmit fault ability */
+#define MDIO_PCS_STAT2_10GBR		0x0001	/* 10GBASE-R capable */
+#define MDIO_PCS_STAT2_10GBX		0x0002	/* 10GBASE-X capable */
+#define MDIO_PCS_STAT2_10GBW		0x0004	/* 10GBASE-W capable */
+#define MDIO_PCS_STAT2_RXFLTABLE	0x1000	/* Receive fault ability */
+#define MDIO_PCS_STAT2_TXFLTABLE	0x2000	/* Transmit fault ability */
+
+/* Transmit disable register. */
+#define MDIO_PMD_TXDIS_GLOBAL		0x0001	/* Global PMD TX disable */
+#define MDIO_PMD_TXDIS_0		0x0002	/* PMD TX disable 0 */
+#define MDIO_PMD_TXDIS_1		0x0004	/* PMD TX disable 1 */
+#define MDIO_PMD_TXDIS_2		0x0008	/* PMD TX disable 2 */
+#define MDIO_PMD_TXDIS_3		0x0010	/* PMD TX disable 3 */
+
+/* Receive signal detect register. */
+#define MDIO_PMD_RXDET_GLOBAL		0x0001	/* Global PMD RX signal detect */
+#define MDIO_PMD_RXDET_0		0x0002	/* PMD RX signal detect 0 */
+#define MDIO_PMD_RXDET_1		0x0004	/* PMD RX signal detect 1 */
+#define MDIO_PMD_RXDET_2		0x0008	/* PMD RX signal detect 2 */
+#define MDIO_PMD_RXDET_3		0x0010	/* PMD RX signal detect 3 */
+
+/* Extended abilities register. */
+#define MDIO_PMA_EXTABLE_10GCX4		0x0001	/* 10GBASE-CX4 ability */
+#define MDIO_PMA_EXTABLE_10GBLRM	0x0002	/* 10GBASE-LRM ability */
+#define MDIO_PMA_EXTABLE_10GBT		0x0004	/* 10GBASE-T ability */
+#define MDIO_PMA_EXTABLE_10GBKX4	0x0008	/* 10GBASE-KX4 ability */
+#define MDIO_PMA_EXTABLE_10GBKR		0x0010	/* 10GBASE-KR ability */
+#define MDIO_PMA_EXTABLE_1000BT		0x0020	/* 1000BASE-T ability */
+#define MDIO_PMA_EXTABLE_1000BKX	0x0040	/* 1000BASE-KX ability */
+#define MDIO_PMA_EXTABLE_100BTX		0x0080	/* 100BASE-TX ability */
+#define MDIO_PMA_EXTABLE_10BT		0x0100	/* 10BASE-T ability */
+
+/* PHY XGXS lane state register. */
+#define MDIO_PHYXS_LNSTAT_SYNC0		0x0001
+#define MDIO_PHYXS_LNSTAT_SYNC1		0x0002
+#define MDIO_PHYXS_LNSTAT_SYNC2		0x0004
+#define MDIO_PHYXS_LNSTAT_SYNC3		0x0008
+#define MDIO_PHYXS_LNSTAT_ALIGN		0x1000
+
+/* PMA 10GBASE-T pair swap & polarity */
+#define MDIO_PMA_10GBT_SWAPPOL_ABNX	0x0001	/* Pair A/B uncrossed */
+#define MDIO_PMA_10GBT_SWAPPOL_CDNX	0x0002	/* Pair C/D uncrossed */
+#define MDIO_PMA_10GBT_SWAPPOL_AREV	0x0100	/* Pair A polarity reversed */
+#define MDIO_PMA_10GBT_SWAPPOL_BREV	0x0200	/* Pair B polarity reversed */
+#define MDIO_PMA_10GBT_SWAPPOL_CREV	0x0400	/* Pair C polarity reversed */
+#define MDIO_PMA_10GBT_SWAPPOL_DREV	0x0800	/* Pair D polarity reversed */
+
+/* PMA 10GBASE-T TX power register. */
+#define MDIO_PMA_10GBT_TXPWR_SHORT	0x0001	/* Short-reach mode */
+
+/* PMA 10GBASE-T SNR registers. */
+/* Value is SNR margin in dB, clamped to range [-127, 127], plus 0x8000. */
+#define MDIO_PMA_10GBT_SNR_BIAS		0x8000
+#define MDIO_PMA_10GBT_SNR_MAX		127
+
+/* PMA 10GBASE-R FEC ability register. */
+#define MDIO_PMA_10GBR_FECABLE_ABLE	0x0001	/* FEC ability */
+#define MDIO_PMA_10GBR_FECABLE_ERRABLE	0x0002	/* FEC error indic. ability */
+
+/* PCS 10GBASE-R/-T status register 1. */
+#define MDIO_PCS_10GBRT_STAT1_BLKLK	0x0001	/* Block lock attained */
+
+/* PCS 10GBASE-R/-T status register 2. */
+#define MDIO_PCS_10GBRT_STAT2_ERR	0x00ff
+#define MDIO_PCS_10GBRT_STAT2_BER	0x3f00
+
+/* AN 10GBASE-T control register. */
+#define MDIO_AN_10GBT_CTRL_ADV10G	0x1000	/* Advertise 10GBASE-T */
+
+/* AN 10GBASE-T status register. */
+#define MDIO_AN_10GBT_STAT_LPTRR	0x0200	/* LP training reset req. */
+#define MDIO_AN_10GBT_STAT_LPLTABLE	0x0400	/* LP loop timing ability */
+#define MDIO_AN_10GBT_STAT_LP10G	0x0800	/* LP is 10GBT capable */
+#define MDIO_AN_10GBT_STAT_REMOK	0x1000	/* Remote OK */
+#define MDIO_AN_10GBT_STAT_LOCOK	0x2000	/* Local OK */
+#define MDIO_AN_10GBT_STAT_MS		0x4000	/* Master/slave config */
+#define MDIO_AN_10GBT_STAT_MSFLT	0x8000	/* Master/slave config fault */
+
+/* AN EEE Advertisement register. */
+#define MDIO_AN_EEE_ADV_100TX		0x0002	/* Advertise 100TX EEE cap */
+#define MDIO_AN_EEE_ADV_1000T		0x0004	/* Advertise 1000T EEE cap */
+
+/* LASI RX_ALARM control/status registers. */
+#define MDIO_PMA_LASI_RX_PHYXSLFLT	0x0001	/* PHY XS RX local fault */
+#define MDIO_PMA_LASI_RX_PCSLFLT	0x0008	/* PCS RX local fault */
+#define MDIO_PMA_LASI_RX_PMALFLT	0x0010	/* PMA/PMD RX local fault */
+#define MDIO_PMA_LASI_RX_OPTICPOWERFLT	0x0020	/* RX optical power fault */
+#define MDIO_PMA_LASI_RX_WISLFLT	0x0200	/* WIS local fault */
+
+/* LASI TX_ALARM control/status registers. */
+#define MDIO_PMA_LASI_TX_PHYXSLFLT	0x0001	/* PHY XS TX local fault */
+#define MDIO_PMA_LASI_TX_PCSLFLT	0x0008	/* PCS TX local fault */
+#define MDIO_PMA_LASI_TX_PMALFLT	0x0010	/* PMA/PMD TX local fault */
+#define MDIO_PMA_LASI_TX_LASERPOWERFLT	0x0080	/* Laser output power fault */
+#define MDIO_PMA_LASI_TX_LASERTEMPFLT	0x0100	/* Laser temperature fault */
+#define MDIO_PMA_LASI_TX_LASERBICURRFLT	0x0200	/* Laser bias current fault */
+
+/* LASI control/status registers. */
+#define MDIO_PMA_LASI_LSALARM		0x0001	/* LS_ALARM enable/status */
+#define MDIO_PMA_LASI_TXALARM		0x0002	/* TX_ALARM enable/status */
+#define MDIO_PMA_LASI_RXALARM		0x0004	/* RX_ALARM enable/status */
+
+/* Mapping between MDIO PRTAD/DEVAD and mii_ioctl_data::phy_id */
+
+#define MDIO_PHY_ID_C45			0x8000
+#define MDIO_PHY_ID_PRTAD		0x03e0
+#define MDIO_PHY_ID_DEVAD		0x001f
+#define MDIO_PHY_ID_C45_MASK						\
+	(MDIO_PHY_ID_C45 | MDIO_PHY_ID_PRTAD | MDIO_PHY_ID_DEVAD)
+
+#define MDIO_PRTAD_NONE			(-1)
+#define MDIO_DEVAD_NONE			(-1)
+#define MDIO_EMULATE_C22		4
+
+#endif /* __LINUX_MDIO_H__ */
diff --git a/qemu/roms/u-boot/include/linux/mii.h b/qemu/roms/u-boot/include/linux/mii.h
new file mode 100644
index 000000000..66b83d83d
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/mii.h
@@ -0,0 +1,193 @@
+/*
+ * linux/mii.h: definitions for MII-compatible transceivers
+ * Originally drivers/net/sunhme.h.
+ *
+ * Copyright (C) 1996, 1999, 2001 David S. Miller (davem@redhat.com)
+ */
+
+#ifndef __LINUX_MII_H__
+#define __LINUX_MII_H__
+
+/* Generic MII registers. */
+
+#define MII_BMCR	    0x00	/* Basic mode control register */
+#define MII_BMSR	    0x01	/* Basic mode status register  */
+#define MII_PHYSID1	    0x02	/* PHYS ID 1		       */
+#define MII_PHYSID2	    0x03	/* PHYS ID 2		       */
+#define MII_ADVERTISE	    0x04	/* Advertisement control reg   */
+#define MII_LPA		    0x05	/* Link partner ability reg    */
+#define MII_EXPANSION	    0x06	/* Expansion register	       */
+#define MII_CTRL1000	    0x09	/* 1000BASE-T control	       */
+#define MII_STAT1000	    0x0a	/* 1000BASE-T status	       */
+#define MII_ESTATUS	    0x0f	/* Extended Status */
+#define MII_DCOUNTER	    0x12	/* Disconnect counter	       */
+#define MII_FCSCOUNTER	    0x13	/* False carrier counter       */
+#define MII_NWAYTEST	    0x14	/* N-way auto-neg test reg     */
+#define MII_RERRCOUNTER     0x15	/* Receive error counter       */
+#define MII_SREVISION	    0x16	/* Silicon revision	       */
+#define MII_RESV1	    0x17	/* Reserved...		       */
+#define MII_LBRERROR	    0x18	/* Lpback, rx, bypass error    */
+#define MII_PHYADDR	    0x19	/* PHY address		       */
+#define MII_RESV2	    0x1a	/* Reserved...		       */
+#define MII_TPISTATUS	    0x1b	/* TPI status for 10mbps       */
+#define MII_NCONFIG	    0x1c	/* Network interface config    */
+
+/* Basic mode control register. */
+#define BMCR_RESV		0x003f	/* Unused...		       */
+#define BMCR_SPEED1000		0x0040	/* MSB of Speed (1000)	       */
+#define BMCR_CTST		0x0080	/* Collision test	       */
+#define BMCR_FULLDPLX		0x0100	/* Full duplex		       */
+#define BMCR_ANRESTART		0x0200	/* Auto negotiation restart    */
+#define BMCR_ISOLATE		0x0400	/* Disconnect DP83840 from MII */
+#define BMCR_PDOWN		0x0800	/* Powerdown the DP83840       */
+#define BMCR_ANENABLE		0x1000	/* Enable auto negotiation     */
+#define BMCR_SPEED100		0x2000	/* Select 100Mbps	       */
+#define BMCR_LOOPBACK		0x4000	/* TXD loopback bits	       */
+#define BMCR_RESET		0x8000	/* Reset the DP83840	       */
+
+/* Basic mode status register. */
+#define BMSR_ERCAP		0x0001	/* Ext-reg capability	       */
+#define BMSR_JCD		0x0002	/* Jabber detected	       */
+#define BMSR_LSTATUS		0x0004	/* Link status		       */
+#define BMSR_ANEGCAPABLE	0x0008	/* Able to do auto-negotiation */
+#define BMSR_RFAULT		0x0010	/* Remote fault detected       */
+#define BMSR_ANEGCOMPLETE	0x0020	/* Auto-negotiation complete   */
+#define BMSR_RESV		0x00c0	/* Unused...		       */
+#define BMSR_ESTATEN		0x0100	/* Extended Status in R15 */
+#define BMSR_100HALF2		0x0200	/* Can do 100BASE-T2 HDX */
+#define BMSR_100FULL2		0x0400	/* Can do 100BASE-T2 FDX */
+#define BMSR_10HALF		0x0800	/* Can do 10mbps, half-duplex  */
+#define BMSR_10FULL		0x1000	/* Can do 10mbps, full-duplex  */
+#define BMSR_100HALF		0x2000	/* Can do 100mbps, half-duplex */
+#define BMSR_100FULL		0x4000	/* Can do 100mbps, full-duplex */
+#define BMSR_100BASE4		0x8000	/* Can do 100mbps, 4k packets  */
+
+/* Advertisement control register. */
+#define ADVERTISE_SLCT		0x001f	/* Selector bits	       */
+#define ADVERTISE_CSMA		0x0001	/* Only selector supported     */
+#define ADVERTISE_10HALF	0x0020	/* Try for 10mbps half-duplex  */
+#define ADVERTISE_1000XFULL	0x0020	/* Try for 1000BASE-X full-duplex */
+#define ADVERTISE_10FULL	0x0040	/* Try for 10mbps full-duplex  */
+#define ADVERTISE_1000XHALF	0x0040	/* Try for 1000BASE-X half-duplex */
+#define ADVERTISE_100HALF	0x0080	/* Try for 100mbps half-duplex */
+#define ADVERTISE_1000XPAUSE	0x0080	/* Try for 1000BASE-X pause    */
+#define ADVERTISE_100FULL	0x0100	/* Try for 100mbps full-duplex */
+#define ADVERTISE_1000XPSE_ASYM 0x0100	/* Try for 1000BASE-X asym pause */
+#define ADVERTISE_100BASE4	0x0200	/* Try for 100mbps 4k packets  */
+#define ADVERTISE_PAUSE_CAP	0x0400	/* Try for pause	       */
+#define ADVERTISE_PAUSE_ASYM	0x0800	/* Try for asymetric pause     */
+#define ADVERTISE_RESV		0x1000	/* Unused...		       */
+#define ADVERTISE_RFAULT	0x2000	/* Say we can detect faults    */
+#define ADVERTISE_LPACK		0x4000	/* Ack link partners response  */
+#define ADVERTISE_NPAGE		0x8000	/* Next page bit	       */
+
+#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
+			ADVERTISE_CSMA)
+#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
+		       ADVERTISE_100HALF | ADVERTISE_100FULL)
+
+/* Link partner ability register. */
+#define LPA_SLCT		0x001f	/* Same as advertise selector  */
+#define LPA_10HALF		0x0020	/* Can do 10mbps half-duplex   */
+#define LPA_1000XFULL		0x0020	/* Can do 1000BASE-X full-duplex */
+#define LPA_10FULL		0x0040	/* Can do 10mbps full-duplex   */
+#define LPA_1000XHALF		0x0040	/* Can do 1000BASE-X half-duplex */
+#define LPA_100HALF		0x0080	/* Can do 100mbps half-duplex  */
+#define LPA_1000XPAUSE		0x0080	/* Can do 1000BASE-X pause     */
+#define LPA_100FULL		0x0100	/* Can do 100mbps full-duplex  */
+#define LPA_1000XPAUSE_ASYM	0x0100	/* Can do 1000BASE-X pause asym*/
+#define LPA_100BASE4		0x0200	/* Can do 100mbps 4k packets   */
+#define LPA_PAUSE_CAP		0x0400	/* Can pause		       */
+#define LPA_PAUSE_ASYM		0x0800	/* Can pause asymetrically     */
+#define LPA_RESV		0x1000	/* Unused...		       */
+#define LPA_RFAULT		0x2000	/* Link partner faulted        */
+#define LPA_LPACK		0x4000	/* Link partner acked us       */
+#define LPA_NPAGE		0x8000	/* Next page bit	       */
+
+#define LPA_DUPLEX		(LPA_10FULL | LPA_100FULL)
+#define LPA_100			(LPA_100FULL | LPA_100HALF | LPA_100BASE4)
+
+/* Expansion register for auto-negotiation. */
+#define EXPANSION_NWAY		0x0001	/* Can do N-way auto-nego      */
+#define EXPANSION_LCWP		0x0002	/* Got new RX page code word   */
+#define EXPANSION_ENABLENPAGE	0x0004	/* This enables npage words    */
+#define EXPANSION_NPCAPABLE	0x0008	/* Link partner supports npage */
+#define EXPANSION_MFAULTS	0x0010	/* Multiple faults detected    */
+#define EXPANSION_RESV		0xffe0	/* Unused...		       */
+
+#define ESTATUS_1000_XFULL	0x8000	/* Can do 1000BX Full */
+#define ESTATUS_1000_XHALF	0x4000	/* Can do 1000BX Half */
+#define ESTATUS_1000_TFULL	0x2000	/* Can do 1000BT Full */
+#define ESTATUS_1000_THALF	0x1000	/* Can do 1000BT Half */
+
+/* N-way test register. */
+#define NWAYTEST_RESV1		0x00ff	/* Unused...		       */
+#define NWAYTEST_LOOPBACK	0x0100	/* Enable loopback for N-way   */
+#define NWAYTEST_RESV2		0xfe00	/* Unused...		       */
+
+/* 1000BASE-T Control register */
+#define ADVERTISE_1000FULL	0x0200	/* Advertise 1000BASE-T full duplex */
+#define ADVERTISE_1000HALF	0x0100	/* Advertise 1000BASE-T half duplex */
+
+/* 1000BASE-T Status register */
+#define LPA_1000LOCALRXOK	0x2000	/* Link partner local receiver status */
+#define LPA_1000REMRXOK		0x1000	/* Link partner remote receiver status */
+#define LPA_1000FULL		0x0800	/* Link partner 1000BASE-T full duplex */
+#define LPA_1000HALF		0x0400	/* Link partner 1000BASE-T half duplex */
+
+/* Flow control flags */
+#define FLOW_CTRL_TX		0x01
+#define FLOW_CTRL_RX		0x02
+
+/**
+ * mii_nway_result
+ * @negotiated: value of MII ANAR and'd with ANLPAR
+ *
+ * Given a set of MII abilities, check each bit and returns the
+ * currently supported media, in the priority order defined by
+ * IEEE 802.3u.  We use LPA_xxx constants but note this is not the
+ * value of LPA solely, as described above.
+ *
+ * The one exception to IEEE 802.3u is that 100baseT4 is placed
+ * between 100T-full and 100T-half.  If your phy does not support
+ * 100T4 this is fine. If your phy places 100T4 elsewhere in the
+ * priority order, you will need to roll your own function.
+ */
+static inline unsigned int mii_nway_result (unsigned int negotiated)
+{
+	unsigned int ret;
+
+	if (negotiated & LPA_100FULL)
+		ret = LPA_100FULL;
+	else if (negotiated & LPA_100BASE4)
+		ret = LPA_100BASE4;
+	else if (negotiated & LPA_100HALF)
+		ret = LPA_100HALF;
+	else if (negotiated & LPA_10FULL)
+		ret = LPA_10FULL;
+	else
+		ret = LPA_10HALF;
+
+	return ret;
+}
+
+/**
+ * mii_duplex
+ * @duplex_lock: Non-zero if duplex is locked at full
+ * @negotiated: value of MII ANAR and'd with ANLPAR
+ *
+ * A small helper function for a common case.  Returns one
+ * if the media is operating or locked at full duplex, and
+ * returns zero otherwise.
+ */
+static inline unsigned int mii_duplex (unsigned int duplex_lock,
+				       unsigned int negotiated)
+{
+	if (duplex_lock)
+		return 1;
+	if (mii_nway_result(negotiated) & LPA_DUPLEX)
+		return 1;
+	return 0;
+}
+
+#endif /* __LINUX_MII_H__ */
diff --git a/qemu/roms/u-boot/include/linux/mtd/bbm.h b/qemu/roms/u-boot/include/linux/mtd/bbm.h
new file mode 100644
index 000000000..25a3d3a3d
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/mtd/bbm.h
@@ -0,0 +1,161 @@
+/*
+ *  linux/include/linux/mtd/bbm.h
+ *
+ *  NAND family Bad Block Management (BBM) header file
+ *    - Bad Block Table (BBT) implementation
+ *
+ *  Copyright (c) 2005-2007 Samsung Electronics
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ *  Copyright (c) 2000-2005
+ *  Thomas Gleixner <tglx@linuxtronix.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __LINUX_MTD_BBM_H
+#define __LINUX_MTD_BBM_H
+
+/* The maximum number of NAND chips in an array */
+#ifndef CONFIG_SYS_NAND_MAX_CHIPS
+#define CONFIG_SYS_NAND_MAX_CHIPS	1
+#endif
+
+/**
+ * struct nand_bbt_descr - bad block table descriptor
+ * @param options	options for this descriptor
+ * @param pages		the page(s) where we find the bbt, used with
+ *			option BBT_ABSPAGE when bbt is searched,
+ *			then we store the found bbts pages here.
+ *			Its an array and supports up to 8 chips now
+ * @param offs		offset of the pattern in the oob area of the page
+ * @param veroffs	offset of the bbt version counter in the oob are of the page
+ * @param version	version read from the bbt page during scan
+ * @param len		length of the pattern, if 0 no pattern check is performed
+ * @param maxblocks	maximum number of blocks to search for a bbt. This number of
+ *			blocks is reserved at the end of the device
+ *			where the tables are written.
+ * @param reserved_block_code	if non-0, this pattern denotes a reserved
+ *			(rather than bad) block in the stored bbt
+ * @param pattern	pattern to identify bad block table or factory marked
+ *			good / bad blocks, can be NULL, if len = 0
+ *
+ * Descriptor for the bad block table marker and the descriptor for the
+ * pattern which identifies good and bad blocks. The assumption is made
+ * that the pattern and the version count are always located in the oob area
+ * of the first block.
+ */
+struct nand_bbt_descr {
+	int options;
+	int pages[CONFIG_SYS_NAND_MAX_CHIPS];
+	int offs;
+	int veroffs;
+	uint8_t version[CONFIG_SYS_NAND_MAX_CHIPS];
+	int len;
+	int maxblocks;
+	int reserved_block_code;
+	uint8_t *pattern;
+};
+
+/* Options for the bad block table descriptors */
+
+/* The number of bits used per block in the bbt on the device */
+#define NAND_BBT_NRBITS_MSK	0x0000000F
+#define NAND_BBT_1BIT		0x00000001
+#define NAND_BBT_2BIT		0x00000002
+#define NAND_BBT_4BIT		0x00000004
+#define NAND_BBT_8BIT		0x00000008
+/* The bad block table is in the last good block of the device */
+#define NAND_BBT_LASTBLOCK	0x00000010
+/* The bbt is at the given page, else we must scan for the bbt */
+#define NAND_BBT_ABSPAGE	0x00000020
+/* bbt is stored per chip on multichip devices */
+#define NAND_BBT_PERCHIP	0x00000080
+/* bbt has a version counter at offset veroffs */
+#define NAND_BBT_VERSION	0x00000100
+/* Create a bbt if none exists */
+#define NAND_BBT_CREATE		0x00000200
+/*
+ * Create an empty BBT with no vendor information. Vendor's information may be
+ * unavailable, for example, if the NAND controller has a different data and OOB
+ * layout or if this information is already purged. Must be used in conjunction
+ * with NAND_BBT_CREATE.
+ */
+#define NAND_BBT_CREATE_EMPTY	0x00000400
+/* Search good / bad pattern through all pages of a block */
+#define NAND_BBT_SCANALLPAGES	0x00000800
+/* Scan block empty during good / bad block scan */
+#define NAND_BBT_SCANEMPTY	0x00001000
+/* Write bbt if neccecary */
+#define NAND_BBT_WRITE		0x00002000
+/* Read and write back block contents when writing bbt */
+#define NAND_BBT_SAVECONTENT	0x00004000
+/* Search good / bad pattern on the first and the second page */
+#define NAND_BBT_SCAN2NDPAGE	0x00008000
+/* Search good / bad pattern on the last page of the eraseblock */
+#define NAND_BBT_SCANLASTPAGE	0x00010000
+/*
+ * Use a flash based bad block table. By default, OOB identifier is saved in
+ * OOB area. This option is passed to the default bad block table function.
+ */
+#define NAND_BBT_USE_FLASH	0x00020000
+/*
+ * Do not store flash based bad block table marker in the OOB area; store it
+ * in-band.
+ */
+#define NAND_BBT_NO_OOB		0x00040000
+/*
+ * Do not write new bad block markers to OOB; useful, e.g., when ECC covers
+ * entire spare area. Must be used with NAND_BBT_USE_FLASH.
+ */
+#define NAND_BBT_NO_OOB_BBM	0x00080000
+
+/*
+ * Flag set by nand_create_default_bbt_descr(), marking that the nand_bbt_descr
+ * was allocated dynamicaly and must be freed in nand_release(). Has no meaning
+ * in nand_chip.bbt_options.
+ */
+#define NAND_BBT_DYNAMICSTRUCT	0x80000000
+
+/* The maximum number of blocks to scan for a bbt */
+#define NAND_BBT_SCAN_MAXBLOCKS	4
+
+/*
+ * Constants for oob configuration
+ */
+#define ONENAND_BADBLOCK_POS	0
+
+/*
+ * Bad block scanning errors
+ */
+#define ONENAND_BBT_READ_ERROR          1
+#define ONENAND_BBT_READ_ECC_ERROR      2
+#define ONENAND_BBT_READ_FATAL_ERROR    4
+
+/**
+ * struct bbt_info - [GENERIC] Bad Block Table data structure
+ * @param bbt_erase_shift	[INTERN] number of address bits in a bbt entry
+ * @param badblockpos		[INTERN] position of the bad block marker in the oob area
+ * @param bbt			[INTERN] bad block table pointer
+ * @param badblock_pattern	[REPLACEABLE] bad block scan pattern used for initial bad block scan
+ * @param priv			[OPTIONAL] pointer to private bbm date
+ */
+struct bbm_info {
+	int bbt_erase_shift;
+	int badblockpos;
+	int options;
+
+	uint8_t *bbt;
+
+	int (*isbad_bbt) (struct mtd_info * mtd, loff_t ofs, int allowbbt);
+
+	/* TODO Add more NAND specific fileds */
+	struct nand_bbt_descr *badblock_pattern;
+
+	void *priv;
+};
+
+/* OneNAND BBT interface */
+extern int onenand_scan_bbt (struct mtd_info *mtd, struct nand_bbt_descr *bd);
+extern int onenand_default_bbt (struct mtd_info *mtd);
+
+#endif				/* __LINUX_MTD_BBM_H */
diff --git a/qemu/roms/u-boot/include/linux/mtd/concat.h b/qemu/roms/u-boot/include/linux/mtd/concat.h
new file mode 100644
index 000000000..c92b4ddc9
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/mtd/concat.h
@@ -0,0 +1,19 @@
+/*
+ * MTD device concatenation layer definitions
+ *
+ * (C) 2002 Robert Kaiser <rkaiser@sysgo.de>
+ *
+ * This code is GPL
+ */
+
+#ifndef MTD_CONCAT_H
+#define MTD_CONCAT_H
+
+struct mtd_info *mtd_concat_create(
+    struct mtd_info *subdev[],  /* subdevices to concatenate */
+    int num_devs,               /* number of subdevices      */
+    const char *name);          /* name for the new device   */
+
+void mtd_concat_destroy(struct mtd_info *mtd);
+
+#endif
diff --git a/qemu/roms/u-boot/include/linux/mtd/doc2000.h b/qemu/roms/u-boot/include/linux/mtd/doc2000.h
new file mode 100644
index 000000000..ba29d53ec
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/mtd/doc2000.h
@@ -0,0 +1,207 @@
+/*
+ * Linux driver for Disk-On-Chip devices
+ *
+ * Copyright (C) 1999 Machine Vision Holdings, Inc.
+ * Copyright (C) 2001-2003 David Woodhouse <dwmw2@infradead.org>
+ * Copyright (C) 2002-2003 Greg Ungerer <gerg@snapgear.com>
+ * Copyright (C) 2002-2003 SnapGear Inc
+ *
+ * Released under GPL
+ */
+
+#ifndef __MTD_DOC2000_H__
+#define __MTD_DOC2000_H__
+
+#include <linux/mtd/mtd.h>
+#if 0
+#include <linux/mutex.h>
+#endif
+
+#define DoC_Sig1 0
+#define DoC_Sig2 1
+
+#define DoC_ChipID		0x1000
+#define DoC_DOCStatus		0x1001
+#define DoC_DOCControl		0x1002
+#define DoC_FloorSelect		0x1003
+#define DoC_CDSNControl		0x1004
+#define DoC_CDSNDeviceSelect	0x1005
+#define DoC_ECCConf		0x1006
+#define DoC_2k_ECCStatus	0x1007
+
+#define DoC_CDSNSlowIO		0x100d
+#define DoC_ECCSyndrome0	0x1010
+#define DoC_ECCSyndrome1	0x1011
+#define DoC_ECCSyndrome2	0x1012
+#define DoC_ECCSyndrome3	0x1013
+#define DoC_ECCSyndrome4	0x1014
+#define DoC_ECCSyndrome5	0x1015
+#define DoC_AliasResolution	0x101b
+#define DoC_ConfigInput		0x101c
+#define DoC_ReadPipeInit	0x101d
+#define DoC_WritePipeTerm	0x101e
+#define DoC_LastDataRead	0x101f
+#define DoC_NOP			0x1020
+
+#define DoC_Mil_CDSN_IO		0x0800
+#define DoC_2k_CDSN_IO		0x1800
+
+#define DoC_Mplus_NOP			0x1002
+#define DoC_Mplus_AliasResolution	0x1004
+#define DoC_Mplus_DOCControl		0x1006
+#define DoC_Mplus_AccessStatus		0x1008
+#define DoC_Mplus_DeviceSelect		0x1008
+#define DoC_Mplus_Configuration		0x100a
+#define DoC_Mplus_OutputControl		0x100c
+#define DoC_Mplus_FlashControl		0x1020
+#define DoC_Mplus_FlashSelect 		0x1022
+#define DoC_Mplus_FlashCmd		0x1024
+#define DoC_Mplus_FlashAddress		0x1026
+#define DoC_Mplus_FlashData0		0x1028
+#define DoC_Mplus_FlashData1		0x1029
+#define DoC_Mplus_ReadPipeInit		0x102a
+#define DoC_Mplus_LastDataRead		0x102c
+#define DoC_Mplus_LastDataRead1		0x102d
+#define DoC_Mplus_WritePipeTerm 	0x102e
+#define DoC_Mplus_ECCSyndrome0		0x1040
+#define DoC_Mplus_ECCSyndrome1		0x1041
+#define DoC_Mplus_ECCSyndrome2		0x1042
+#define DoC_Mplus_ECCSyndrome3		0x1043
+#define DoC_Mplus_ECCSyndrome4		0x1044
+#define DoC_Mplus_ECCSyndrome5		0x1045
+#define DoC_Mplus_ECCConf 		0x1046
+#define DoC_Mplus_Toggle		0x1046
+#define DoC_Mplus_DownloadStatus	0x1074
+#define DoC_Mplus_CtrlConfirm		0x1076
+#define DoC_Mplus_Power			0x1fff
+
+/* How to access the device?
+ * On ARM, it'll be mmap'd directly with 32-bit wide accesses.
+ * On PPC, it's mmap'd and 16-bit wide.
+ * Others use readb/writeb
+ */
+#if defined(__arm__)
+#define ReadDOC_(adr, reg)      ((unsigned char)(*(volatile __u32 *)(((unsigned long)adr)+((reg)<<2))))
+#define WriteDOC_(d, adr, reg)  do{ *(volatile __u32 *)(((unsigned long)adr)+((reg)<<2)) = (__u32)d; wmb();} while(0)
+#define DOC_IOREMAP_LEN 0x8000
+#elif defined(__ppc__)
+#define ReadDOC_(adr, reg)      ((unsigned char)(*(volatile __u16 *)(((unsigned long)adr)+((reg)<<1))))
+#define WriteDOC_(d, adr, reg)  do{ *(volatile __u16 *)(((unsigned long)adr)+((reg)<<1)) = (__u16)d; wmb();} while(0)
+#define DOC_IOREMAP_LEN 0x4000
+#else
+#define ReadDOC_(adr, reg)      readb((void __iomem *)(adr) + (reg))
+#define WriteDOC_(d, adr, reg)  writeb(d, (void __iomem *)(adr) + (reg))
+#define DOC_IOREMAP_LEN 0x2000
+
+#endif
+
+#if defined(__i386__) || defined(__x86_64__)
+#define USE_MEMCPY
+#endif
+
+/* These are provided to directly use the DoC_xxx defines */
+#define ReadDOC(adr, reg)      ReadDOC_(adr,DoC_##reg)
+#define WriteDOC(d, adr, reg)  WriteDOC_(d,adr,DoC_##reg)
+
+#define DOC_MODE_RESET		0
+#define DOC_MODE_NORMAL		1
+#define DOC_MODE_RESERVED1	2
+#define DOC_MODE_RESERVED2	3
+
+#define DOC_MODE_CLR_ERR	0x80
+#define	DOC_MODE_RST_LAT	0x10
+#define	DOC_MODE_BDECT		0x08
+#define DOC_MODE_MDWREN	0x04
+
+#define DOC_ChipID_Doc2k	0x20
+#define DOC_ChipID_Doc2kTSOP	0x21	/* internal number for MTD */
+#define DOC_ChipID_DocMil	0x30
+#define DOC_ChipID_DocMilPlus32	0x40
+#define DOC_ChipID_DocMilPlus16	0x41
+
+#define CDSN_CTRL_FR_B		0x80
+#define CDSN_CTRL_FR_B0		0x40
+#define CDSN_CTRL_FR_B1		0x80
+
+#define CDSN_CTRL_ECC_IO	0x20
+#define CDSN_CTRL_FLASH_IO	0x10
+#define CDSN_CTRL_WP		0x08
+#define CDSN_CTRL_ALE		0x04
+#define CDSN_CTRL_CLE		0x02
+#define CDSN_CTRL_CE		0x01
+
+#define DOC_ECC_RESET		0
+#define DOC_ECC_ERROR		0x80
+#define DOC_ECC_RW		0x20
+#define DOC_ECC__EN		0x08
+#define DOC_TOGGLE_BIT		0x04
+#define DOC_ECC_RESV		0x02
+#define DOC_ECC_IGNORE		0x01
+
+#define DOC_FLASH_CE		0x80
+#define DOC_FLASH_WP		0x40
+#define DOC_FLASH_BANK		0x02
+
+/* We have to also set the reserved bit 1 for enable */
+#define DOC_ECC_EN (DOC_ECC__EN | DOC_ECC_RESV)
+#define DOC_ECC_DIS (DOC_ECC_RESV)
+
+struct Nand {
+	char floor, chip;
+	unsigned long curadr;
+	unsigned char curmode;
+	/* Also some erase/write/pipeline info when we get that far */
+};
+
+#define MAX_FLOORS 4
+#define MAX_CHIPS 4
+
+#define MAX_FLOORS_MIL 1
+#define MAX_CHIPS_MIL 1
+
+#define MAX_FLOORS_MPLUS 2
+#define MAX_CHIPS_MPLUS 1
+
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+
+struct DiskOnChip {
+	unsigned long physadr;
+	void __iomem *virtadr;
+	unsigned long totlen;
+	unsigned char ChipID; /* Type of DiskOnChip */
+	int ioreg;
+
+	unsigned long mfr; /* Flash IDs - only one type of flash per device */
+	unsigned long id;
+	int chipshift;
+	char page256;
+	char pageadrlen;
+	char interleave; /* Internal interleaving - Millennium Plus style */
+	unsigned long erasesize;
+
+	int curfloor;
+	int curchip;
+
+	int numchips;
+	struct Nand *chips;
+	struct mtd_info *nextdoc;
+/* XXX U-BOOT XXX */
+#if 0
+	struct mutex lock;
+#endif
+};
+
+int doc_decode_ecc(unsigned char sector[512], unsigned char ecc1[6]);
+
+/* XXX U-BOOT XXX */
+#if 1
+/*
+ * NAND Flash Manufacturer ID Codes
+ */
+#define NAND_MFR_TOSHIBA   0x98
+#define NAND_MFR_SAMSUNG   0xec
+#endif
+
+#endif /* __MTD_DOC2000_H__ */
diff --git a/qemu/roms/u-boot/include/linux/mtd/docg4.h b/qemu/roms/u-boot/include/linux/mtd/docg4.h
new file mode 100644
index 000000000..741fc0db4
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/mtd/docg4.h
@@ -0,0 +1,132 @@
+/*
+ * Copyright (C) 2013 Mike Dunn <mikedunn@newsguy.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DOCG4_H__
+#define __DOCG4_H__
+
+#include <common.h>
+#include <linux/mtd/nand.h>
+
+extern int docg4_nand_init(struct mtd_info *mtd,
+			   struct nand_chip *nand, int devnum);
+
+/* SPL-related definitions */
+#define DOCG4_IPL_LOAD_BLOCK_COUNT 2  /* number of blocks that IPL loads */
+#define DOCG4_BLOCK_CAPACITY_SPL 0x10000 /* reliable mode; redundant pages */
+
+#define DOC_IOSPACE_DATA		0x0800
+
+/* register offsets */
+#define DOC_CHIPID			0x1000
+#define DOC_DEVICESELECT		0x100a
+#define DOC_ASICMODE			0x100c
+#define DOC_DATAEND			0x101e
+#define DOC_NOP				0x103e
+
+#define DOC_FLASHSEQUENCE		0x1032
+#define DOC_FLASHCOMMAND		0x1034
+#define DOC_FLASHADDRESS		0x1036
+#define DOC_FLASHCONTROL		0x1038
+#define DOC_ECCCONF0			0x1040
+#define DOC_ECCCONF1			0x1042
+#define DOC_HAMMINGPARITY		0x1046
+#define DOC_BCH_SYNDROM(idx)		(0x1048 + idx)
+
+#define DOC_ASICMODECONFIRM		0x1072
+#define DOC_CHIPID_INV			0x1074
+#define DOC_POWERMODE			0x107c
+
+#define DOCG4_MYSTERY_REG		0x1050
+
+/* apparently used only to write oob bytes 6 and 7 */
+#define DOCG4_OOB_6_7			0x1052
+
+/* DOC_FLASHSEQUENCE register commands */
+#define DOC_SEQ_RESET			0x00
+#define DOCG4_SEQ_PAGE_READ		0x03
+#define DOCG4_SEQ_FLUSH			0x29
+#define DOCG4_SEQ_PAGEWRITE		0x16
+#define DOCG4_SEQ_PAGEPROG		0x1e
+#define DOCG4_SEQ_BLOCKERASE		0x24
+
+/* DOC_FLASHCOMMAND register commands */
+#define DOCG4_CMD_PAGE_READ             0x00
+#define DOC_CMD_ERASECYCLE2		0xd0
+#define DOCG4_CMD_FLUSH                 0x70
+#define DOCG4_CMD_READ2                 0x30
+#define DOC_CMD_PROG_BLOCK_ADDR		0x60
+#define DOCG4_CMD_PAGEWRITE		0x80
+#define DOC_CMD_PROG_CYCLE2		0x10
+#define DOC_CMD_RESET			0xff
+
+/* DOC_POWERMODE register bits */
+#define DOC_POWERDOWN_READY		0x80
+
+/* DOC_FLASHCONTROL register bits */
+#define DOC_CTRL_CE			0x10
+#define DOC_CTRL_UNKNOWN		0x40
+#define DOC_CTRL_FLASHREADY		0x01
+
+/* DOC_ECCCONF0 register bits */
+#define DOC_ECCCONF0_READ_MODE		0x8000
+#define DOC_ECCCONF0_UNKNOWN		0x2000
+#define DOC_ECCCONF0_ECC_ENABLE	        0x1000
+#define DOC_ECCCONF0_DATA_BYTES_MASK	0x07ff
+
+/* DOC_ECCCONF1 register bits */
+#define DOC_ECCCONF1_BCH_SYNDROM_ERR	0x80
+#define DOC_ECCCONF1_ECC_ENABLE         0x07
+#define DOC_ECCCONF1_PAGE_IS_WRITTEN	0x20
+
+/* DOC_ASICMODE register bits */
+#define DOC_ASICMODE_RESET		0x00
+#define DOC_ASICMODE_NORMAL		0x01
+#define DOC_ASICMODE_POWERDOWN		0x02
+#define DOC_ASICMODE_MDWREN		0x04
+#define DOC_ASICMODE_BDETCT_RESET	0x08
+#define DOC_ASICMODE_RSTIN_RESET	0x10
+#define DOC_ASICMODE_RAM_WE		0x20
+
+/* good status values read after read/write/erase operations */
+#define DOCG4_PROGSTATUS_GOOD          0x51
+#define DOCG4_PROGSTATUS_GOOD_2        0xe0
+
+/*
+ * On read operations (page and oob-only), the first byte read from I/O reg is a
+ * status.  On error, it reads 0x73; otherwise, it reads either 0x71 (first read
+ * after reset only) or 0x51, so bit 1 is presumed to be an error indicator.
+ */
+#define DOCG4_READ_ERROR           0x02 /* bit 1 indicates read error */
+
+/* anatomy of the device */
+#define DOCG4_CHIP_SIZE        0x8000000
+#define DOCG4_PAGE_SIZE        0x200
+#define DOCG4_PAGES_PER_BLOCK  0x200
+#define DOCG4_BLOCK_SIZE       (DOCG4_PAGES_PER_BLOCK * DOCG4_PAGE_SIZE)
+#define DOCG4_NUMBLOCKS        (DOCG4_CHIP_SIZE / DOCG4_BLOCK_SIZE)
+#define DOCG4_OOB_SIZE         0x10
+#define DOCG4_CHIP_SHIFT       27    /* log_2(DOCG4_CHIP_SIZE) */
+#define DOCG4_PAGE_SHIFT       9     /* log_2(DOCG4_PAGE_SIZE) */
+#define DOCG4_ERASE_SHIFT      18    /* log_2(DOCG4_BLOCK_SIZE) */
+
+/* all but the last byte is included in ecc calculation */
+#define DOCG4_BCH_SIZE         (DOCG4_PAGE_SIZE + DOCG4_OOB_SIZE - 1)
+
+#define DOCG4_USERDATA_LEN     520 /* 512 byte page plus 8 oob avail to user */
+
+/* expected values from the ID registers */
+#define DOCG4_IDREG1_VALUE     0x0400
+#define DOCG4_IDREG2_VALUE     0xfbff
+
+/* primitive polynomial used to build the Galois field used by hw ecc gen */
+#define DOCG4_PRIMITIVE_POLY   0x4443
+
+#define DOCG4_M                14  /* Galois field is of order 2^14 */
+#define DOCG4_T                4   /* BCH alg corrects up to 4 bit errors */
+
+#define DOCG4_FACTORY_BBT_PAGE 16 /* page where read-only factory bbt lives */
+
+#endif	/* __DOCG4_H__ */
diff --git a/qemu/roms/u-boot/include/linux/mtd/fsl_upm.h b/qemu/roms/u-boot/include/linux/mtd/fsl_upm.h
new file mode 100644
index 000000000..0a949bca0
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/mtd/fsl_upm.h
@@ -0,0 +1,45 @@
+/*
+ * FSL UPM NAND driver
+ *
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ *                    Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __LINUX_MTD_NAND_FSL_UPM
+#define __LINUX_MTD_NAND_FSL_UPM
+
+#include <linux/mtd/nand.h>
+
+#define FSL_UPM_WAIT_RUN_PATTERN  0x1
+#define FSL_UPM_WAIT_WRITE_BYTE   0x2
+#define FSL_UPM_WAIT_WRITE_BUFFER 0x4
+
+struct fsl_upm {
+	void __iomem *mdr;
+	void __iomem *mxmr;
+	void __iomem *mar;
+	void __iomem *io_addr;
+};
+
+struct fsl_upm_nand {
+	struct fsl_upm upm;
+
+	int width;
+	int upm_cmd_offset;
+	int upm_addr_offset;
+	int upm_mar_chip_offset;
+	int wait_flags;
+	int (*dev_ready)(int chip_nr);
+	int chip_delay;
+	int chip_offset;
+	int chip_nr;
+
+	/* no need to fill */
+	int last_ctrl;
+};
+
+extern int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun);
+
+#endif
diff --git a/qemu/roms/u-boot/include/linux/mtd/fsmc_nand.h b/qemu/roms/u-boot/include/linux/mtd/fsmc_nand.h
new file mode 100644
index 000000000..f0f77270a
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/mtd/fsmc_nand.h
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2010
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __FSMC_NAND_H__
+#define __FSMC_NAND_H__
+
+#include <linux/mtd/nand.h>
+
+struct fsmc_regs {
+	u32 ctrl;			/* 0x00 */
+	u8 reserved_1[0x40 - 0x04];
+	u32 pc;				/* 0x40 */
+	u32 sts;			/* 0x44 */
+	u32 comm;			/* 0x48 */
+	u32 attrib;			/* 0x4c */
+	u32 ioata;			/* 0x50 */
+	u32 ecc1;			/* 0x54 */
+	u32 ecc2;			/* 0x58 */
+	u32 ecc3;			/* 0x5c */
+	u8 reserved_2[0xfe0 - 0x60];
+	u32 peripid0;			/* 0xfe0 */
+	u32 peripid1;			/* 0xfe4 */
+	u32 peripid2;			/* 0xfe8 */
+	u32 peripid3;			/* 0xfec */
+	u32 pcellid0;			/* 0xff0 */
+	u32 pcellid1;			/* 0xff4 */
+	u32 pcellid2;			/* 0xff8 */
+	u32 pcellid3;			/* 0xffc */
+};
+
+/* ctrl register definitions */
+#define FSMC_WP			(1 << 7)
+
+/* pc register definitions */
+#define FSMC_RESET		(1 << 0)
+#define FSMC_WAITON		(1 << 1)
+#define FSMC_ENABLE		(1 << 2)
+#define FSMC_DEVTYPE_NAND	(1 << 3)
+#define FSMC_DEVWID_8		(0 << 4)
+#define FSMC_DEVWID_16		(1 << 4)
+#define FSMC_ECCEN		(1 << 6)
+#define FSMC_ECCPLEN_512	(0 << 7)
+#define FSMC_ECCPLEN_256	(1 << 7)
+#define FSMC_TCLR_1		(1 << 9)
+#define FSMC_TAR_1		(1 << 13)
+
+/* sts register definitions */
+#define FSMC_CODE_RDY		(1 << 15)
+
+/* comm register definitions */
+#define FSMC_TSET_0		(0 << 0)
+#define FSMC_TWAIT_6		(6 << 8)
+#define FSMC_THOLD_4		(4 << 16)
+#define FSMC_THIZ_1		(1 << 24)
+
+/* peripid2 register definitions */
+#define FSMC_REVISION_MSK	(0xf)
+#define FSMC_REVISION_SHFT	(0x4)
+
+#define FSMC_VER8		0x8
+
+/*
+ * There are 13 bytes of ecc for every 512 byte block and it has to be read
+ * consecutively and immediately after the 512 byte data block for hardware to
+ * generate the error bit offsets
+ * Managing the ecc bytes in the following way is easier. This way is similar to
+ * oobfree structure maintained already in u-boot nand driver
+ */
+#define FSMC_MAX_ECCPLACE_ENTRIES	32
+
+struct fsmc_nand_eccplace {
+	u32 offset;
+	u32 length;
+};
+
+struct fsmc_eccplace {
+	struct fsmc_nand_eccplace eccplace[FSMC_MAX_ECCPLACE_ENTRIES];
+};
+
+extern int fsmc_nand_init(struct nand_chip *nand);
+#endif
diff --git a/qemu/roms/u-boot/include/linux/mtd/mtd.h b/qemu/roms/u-boot/include/linux/mtd/mtd.h
new file mode 100644
index 000000000..a65b68155
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/mtd/mtd.h
@@ -0,0 +1,388 @@
+/*
+ * Copyright (C) 1999-2003 David Woodhouse <dwmw2@infradead.org> et al.
+ *
+ * Released under GPL
+ */
+
+#ifndef __MTD_MTD_H__
+#define __MTD_MTD_H__
+
+#include <linux/types.h>
+#include <div64.h>
+#include <mtd/mtd-abi.h>
+#include <asm/errno.h>
+
+#define MTD_CHAR_MAJOR 90
+#define MTD_BLOCK_MAJOR 31
+#define MAX_MTD_DEVICES 32
+
+#define MTD_ERASE_PENDING	0x01
+#define MTD_ERASING		0x02
+#define MTD_ERASE_SUSPEND	0x04
+#define MTD_ERASE_DONE          0x08
+#define MTD_ERASE_FAILED        0x10
+
+#define MTD_FAIL_ADDR_UNKNOWN	-1LL
+
+/*
+ * Enumeration for NAND/OneNAND flash chip state
+ */
+enum {
+	FL_READY,
+	FL_READING,
+	FL_WRITING,
+	FL_ERASING,
+	FL_SYNCING,
+	FL_CACHEDPRG,
+	FL_RESETING,
+	FL_UNLOCKING,
+	FL_LOCKING,
+	FL_PM_SUSPENDED,
+};
+
+/* If the erase fails, fail_addr might indicate exactly which block failed.  If
+   fail_addr = MTD_FAIL_ADDR_UNKNOWN, the failure was not at the device level or was not
+   specific to any particular block. */
+struct erase_info {
+	struct mtd_info *mtd;
+	uint64_t addr;
+	uint64_t len;
+	uint64_t fail_addr;
+	u_long time;
+	u_long retries;
+	u_int dev;
+	u_int cell;
+	void (*callback) (struct erase_info *self);
+	u_long priv;
+	u_char state;
+	struct erase_info *next;
+	int scrub;
+};
+
+struct mtd_erase_region_info {
+	uint64_t offset;			/* At which this region starts, from the beginning of the MTD */
+	u_int32_t erasesize;		/* For this region */
+	u_int32_t numblocks;		/* Number of blocks of erasesize in this region */
+	unsigned long *lockmap;		/* If keeping bitmap of locks */
+};
+
+/**
+ * struct mtd_oob_ops - oob operation operands
+ * @mode:	operation mode
+ *
+ * @len:	number of data bytes to write/read
+ *
+ * @retlen:	number of data bytes written/read
+ *
+ * @ooblen:	number of oob bytes to write/read
+ * @oobretlen:	number of oob bytes written/read
+ * @ooboffs:	offset of oob data in the oob area (only relevant when
+ *		mode = MTD_OPS_PLACE_OOB or MTD_OPS_RAW)
+ * @datbuf:	data buffer - if NULL only oob data are read/written
+ * @oobbuf:	oob data buffer
+ *
+ * Note, it is allowed to read more then one OOB area at one go, but not write.
+ * The interface assumes that the OOB write requests program only one page's
+ * OOB area.
+ */
+struct mtd_oob_ops {
+	unsigned int	mode;
+	size_t		len;
+	size_t		retlen;
+	size_t		ooblen;
+	size_t		oobretlen;
+	uint32_t	ooboffs;
+	uint8_t		*datbuf;
+	uint8_t		*oobbuf;
+};
+
+#ifdef CONFIG_SYS_NAND_MAX_OOBFREE
+#define MTD_MAX_OOBFREE_ENTRIES_LARGE	CONFIG_SYS_NAND_MAX_OOBFREE
+#else
+#define MTD_MAX_OOBFREE_ENTRIES_LARGE	32
+#endif
+
+#ifdef CONFIG_SYS_NAND_MAX_ECCPOS
+#define MTD_MAX_ECCPOS_ENTRIES_LARGE	CONFIG_SYS_NAND_MAX_ECCPOS
+#else
+#define MTD_MAX_ECCPOS_ENTRIES_LARGE	640
+#endif
+
+/*
+ * ECC layout control structure. Exported to userspace for
+ * diagnosis and to allow creation of raw images
+ */
+struct nand_ecclayout {
+	uint32_t eccbytes;
+	uint32_t eccpos[MTD_MAX_ECCPOS_ENTRIES_LARGE];
+	uint32_t oobavail;
+	struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES_LARGE];
+};
+
+struct mtd_info {
+	u_char type;
+	u_int32_t flags;
+	uint64_t size;	 /* Total size of the MTD */
+
+	/* "Major" erase size for the device. Naïve users may take this
+	 * to be the only erase size available, or may use the more detailed
+	 * information below if they desire
+	 */
+	u_int32_t erasesize;
+	/* Minimal writable flash unit size. In case of NOR flash it is 1 (even
+	 * though individual bits can be cleared), in case of NAND flash it is
+	 * one NAND page (or half, or one-fourths of it), in case of ECC-ed NOR
+	 * it is of ECC block size, etc. It is illegal to have writesize = 0.
+	 * Any driver registering a struct mtd_info must ensure a writesize of
+	 * 1 or larger.
+	 */
+	u_int32_t writesize;
+
+	u_int32_t oobsize;   /* Amount of OOB data per block (e.g. 16) */
+	u_int32_t oobavail;  /* Available OOB bytes per block */
+
+	/*
+	 * read ops return -EUCLEAN if max number of bitflips corrected on any
+	 * one region comprising an ecc step equals or exceeds this value.
+	 * Settable by driver, else defaults to ecc_strength.  User can override
+	 * in sysfs.  N.B. The meaning of the -EUCLEAN return code has changed;
+	 * see Documentation/ABI/testing/sysfs-class-mtd for more detail.
+	 */
+	unsigned int bitflip_threshold;
+
+	/* Kernel-only stuff starts here. */
+	const char *name;
+	int index;
+
+	/* ECC layout structure pointer - read only! */
+	struct nand_ecclayout *ecclayout;
+
+	/* max number of correctible bit errors per ecc step */
+	unsigned int ecc_strength;
+
+	/* Data for variable erase regions. If numeraseregions is zero,
+	 * it means that the whole device has erasesize as given above.
+	 */
+	int numeraseregions;
+	struct mtd_erase_region_info *eraseregions;
+
+	/*
+	 * Do not call via these pointers, use corresponding mtd_*()
+	 * wrappers instead.
+	 */
+	int (*_erase) (struct mtd_info *mtd, struct erase_info *instr);
+	int (*_point) (struct mtd_info *mtd, loff_t from, size_t len,
+			size_t *retlen, void **virt, phys_addr_t *phys);
+	void (*_unpoint) (struct mtd_info *mtd, loff_t from, size_t len);
+	int (*_read) (struct mtd_info *mtd, loff_t from, size_t len,
+		     size_t *retlen, u_char *buf);
+	int (*_write) (struct mtd_info *mtd, loff_t to, size_t len,
+		      size_t *retlen, const u_char *buf);
+
+	/* In blackbox flight recorder like scenarios we want to make successful
+	   writes in interrupt context. panic_write() is only intended to be
+	   called when its known the kernel is about to panic and we need the
+	   write to succeed. Since the kernel is not going to be running for much
+	   longer, this function can break locks and delay to ensure the write
+	   succeeds (but not sleep). */
+
+	int (*_panic_write) (struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf);
+
+	int (*_read_oob) (struct mtd_info *mtd, loff_t from,
+			 struct mtd_oob_ops *ops);
+	int (*_write_oob) (struct mtd_info *mtd, loff_t to,
+			 struct mtd_oob_ops *ops);
+	int (*_get_fact_prot_info) (struct mtd_info *mtd, struct otp_info *buf,
+				   size_t len);
+	int (*_read_fact_prot_reg) (struct mtd_info *mtd, loff_t from,
+				   size_t len, size_t *retlen, u_char *buf);
+	int (*_get_user_prot_info) (struct mtd_info *mtd, struct otp_info *buf,
+				   size_t len);
+	int (*_read_user_prot_reg) (struct mtd_info *mtd, loff_t from,
+				   size_t len, size_t *retlen, u_char *buf);
+	int (*_write_user_prot_reg) (struct mtd_info *mtd, loff_t to, size_t len,
+				    size_t *retlen, u_char *buf);
+	int (*_lock_user_prot_reg) (struct mtd_info *mtd, loff_t from,
+				   size_t len);
+	void (*_sync) (struct mtd_info *mtd);
+	int (*_lock) (struct mtd_info *mtd, loff_t ofs, uint64_t len);
+	int (*_unlock) (struct mtd_info *mtd, loff_t ofs, uint64_t len);
+	int (*_block_isbad) (struct mtd_info *mtd, loff_t ofs);
+	int (*_block_markbad) (struct mtd_info *mtd, loff_t ofs);
+	/*
+	 * If the driver is something smart, like UBI, it may need to maintain
+	 * its own reference counting. The below functions are only for driver.
+	 */
+	int (*_get_device) (struct mtd_info *mtd);
+	void (*_put_device) (struct mtd_info *mtd);
+
+/* XXX U-BOOT XXX */
+#if 0
+	/* kvec-based read/write methods.
+	   NB: The 'count' parameter is the number of _vectors_, each of
+	   which contains an (ofs, len) tuple.
+	*/
+	int (*writev) (struct mtd_info *mtd, const struct kvec *vecs, unsigned long count, loff_t to, size_t *retlen);
+#endif
+/* XXX U-BOOT XXX */
+#if 0
+	struct notifier_block reboot_notifier;  /* default mode before reboot */
+#endif
+
+	/* ECC status information */
+	struct mtd_ecc_stats ecc_stats;
+	/* Subpage shift (NAND) */
+	int subpage_sft;
+
+	void *priv;
+
+	struct module *owner;
+	int usecount;
+};
+
+int mtd_erase(struct mtd_info *mtd, struct erase_info *instr);
+int mtd_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen,
+	     u_char *buf);
+int mtd_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen,
+	      const u_char *buf);
+int mtd_panic_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen,
+		    const u_char *buf);
+
+int mtd_read_oob(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops);
+
+static inline int mtd_write_oob(struct mtd_info *mtd, loff_t to,
+				struct mtd_oob_ops *ops)
+{
+	ops->retlen = ops->oobretlen = 0;
+	if (!mtd->_write_oob)
+		return -EOPNOTSUPP;
+	if (!(mtd->flags & MTD_WRITEABLE))
+		return -EROFS;
+	return mtd->_write_oob(mtd, to, ops);
+}
+
+int mtd_get_fact_prot_info(struct mtd_info *mtd, struct otp_info *buf,
+			   size_t len);
+int mtd_read_fact_prot_reg(struct mtd_info *mtd, loff_t from, size_t len,
+			   size_t *retlen, u_char *buf);
+int mtd_get_user_prot_info(struct mtd_info *mtd, struct otp_info *buf,
+			   size_t len);
+int mtd_read_user_prot_reg(struct mtd_info *mtd, loff_t from, size_t len,
+			   size_t *retlen, u_char *buf);
+int mtd_write_user_prot_reg(struct mtd_info *mtd, loff_t to, size_t len,
+			    size_t *retlen, u_char *buf);
+int mtd_lock_user_prot_reg(struct mtd_info *mtd, loff_t from, size_t len);
+
+/* XXX U-BOOT XXX */
+#if 0
+int mtd_writev(struct mtd_info *mtd, const struct kvec *vecs,
+	       unsigned long count, loff_t to, size_t *retlen);
+#endif
+
+static inline void mtd_sync(struct mtd_info *mtd)
+{
+	if (mtd->_sync)
+		mtd->_sync(mtd);
+}
+
+int mtd_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
+int mtd_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
+int mtd_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len);
+int mtd_block_isbad(struct mtd_info *mtd, loff_t ofs);
+int mtd_block_markbad(struct mtd_info *mtd, loff_t ofs);
+
+static inline uint32_t mtd_div_by_eb(uint64_t sz, struct mtd_info *mtd)
+{
+	do_div(sz, mtd->erasesize);
+	return sz;
+}
+
+static inline uint32_t mtd_mod_by_eb(uint64_t sz, struct mtd_info *mtd)
+{
+	return do_div(sz, mtd->erasesize);
+}
+
+static inline int mtd_has_oob(const struct mtd_info *mtd)
+{
+	return mtd->_read_oob && mtd->_write_oob;
+}
+
+static inline int mtd_can_have_bb(const struct mtd_info *mtd)
+{
+	return !!mtd->_block_isbad;
+}
+
+	/* Kernel-side ioctl definitions */
+
+extern int add_mtd_device(struct mtd_info *mtd);
+extern int del_mtd_device (struct mtd_info *mtd);
+
+extern struct mtd_info *get_mtd_device(struct mtd_info *mtd, int num);
+extern struct mtd_info *get_mtd_device_nm(const char *name);
+
+extern void put_mtd_device(struct mtd_info *mtd);
+extern void mtd_get_len_incl_bad(struct mtd_info *mtd, uint64_t offset,
+				 const uint64_t length, uint64_t *len_incl_bad,
+				 int *truncated);
+/* XXX U-BOOT XXX */
+#if 0
+struct mtd_notifier {
+	void (*add)(struct mtd_info *mtd);
+	void (*remove)(struct mtd_info *mtd);
+	struct list_head list;
+};
+
+extern void register_mtd_user (struct mtd_notifier *new);
+extern int unregister_mtd_user (struct mtd_notifier *old);
+#endif
+
+#ifdef CONFIG_MTD_PARTITIONS
+void mtd_erase_callback(struct erase_info *instr);
+#else
+static inline void mtd_erase_callback(struct erase_info *instr)
+{
+	if (instr->callback)
+		instr->callback(instr);
+}
+#endif
+
+/*
+ * Debugging macro and defines
+ */
+#define MTD_DEBUG_LEVEL0	(0)	/* Quiet   */
+#define MTD_DEBUG_LEVEL1	(1)	/* Audible */
+#define MTD_DEBUG_LEVEL2	(2)	/* Loud    */
+#define MTD_DEBUG_LEVEL3	(3)	/* Noisy   */
+
+#ifdef CONFIG_MTD_DEBUG
+#define pr_debug(args...)	MTDDEBUG(MTD_DEBUG_LEVEL0, args)
+#define MTDDEBUG(n, args...)				\
+	do {						\
+		if (n <= CONFIG_MTD_DEBUG_VERBOSE)	\
+			printk(KERN_INFO args);		\
+	} while(0)
+#else /* CONFIG_MTD_DEBUG */
+#define pr_debug(args...)
+#define MTDDEBUG(n, args...)				\
+	do {						\
+		if (0)					\
+			printk(KERN_INFO args);		\
+	} while(0)
+#endif /* CONFIG_MTD_DEBUG */
+#define pr_info(args...)	MTDDEBUG(MTD_DEBUG_LEVEL0, args)
+#define pr_warn(args...)	MTDDEBUG(MTD_DEBUG_LEVEL0, args)
+#define pr_err(args...)		MTDDEBUG(MTD_DEBUG_LEVEL0, args)
+
+static inline int mtd_is_bitflip(int err) {
+	return err == -EUCLEAN;
+}
+
+static inline int mtd_is_eccerr(int err) {
+	return err == -EBADMSG;
+}
+
+static inline int mtd_is_bitflip_or_eccerr(int err) {
+	return mtd_is_bitflip(err) || mtd_is_eccerr(err);
+}
+
+#endif /* __MTD_MTD_H__ */
diff --git a/qemu/roms/u-boot/include/linux/mtd/nand.h b/qemu/roms/u-boot/include/linux/mtd/nand.h
new file mode 100644
index 000000000..054656559
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/mtd/nand.h
@@ -0,0 +1,722 @@
+/*
+ *  linux/include/linux/mtd/nand.h
+ *
+ *  Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
+ *                        Steven J. Hill <sjhill@realitydiluted.com>
+ *		          Thomas Gleixner <tglx@linutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Info:
+ *	Contains standard defines and IDs for NAND flash devices
+ *
+ * Changelog:
+ *	See git changelog.
+ */
+#ifndef __LINUX_MTD_NAND_H
+#define __LINUX_MTD_NAND_H
+
+#include "config.h"
+
+#include "linux/compat.h"
+#include "linux/mtd/mtd.h"
+#include "linux/mtd/bbm.h"
+
+
+struct mtd_info;
+struct nand_flash_dev;
+/* Scan and identify a NAND device */
+extern int nand_scan (struct mtd_info *mtd, int max_chips);
+/* Separate phases of nand_scan(), allowing board driver to intervene
+ * and override command or ECC setup according to flash type */
+extern int nand_scan_ident(struct mtd_info *mtd, int max_chips,
+			   const struct nand_flash_dev *table);
+extern int nand_scan_tail(struct mtd_info *mtd);
+
+/* Free resources held by the NAND device */
+extern void nand_release(struct mtd_info *mtd);
+
+/* Internal helper for board drivers which need to override command function */
+extern void nand_wait_ready(struct mtd_info *mtd);
+
+/*
+ * This constant declares the max. oobsize / page, which
+ * is supported now. If you add a chip with bigger oobsize/page
+ * adjust this accordingly.
+ */
+#define NAND_MAX_OOBSIZE	640
+#define NAND_MAX_PAGESIZE	8192
+
+/*
+ * Constants for hardware specific CLE/ALE/NCE function
+ *
+ * These are bits which can be or'ed to set/clear multiple
+ * bits in one go.
+ */
+/* Select the chip by setting nCE to low */
+#define NAND_NCE		0x01
+/* Select the command latch by setting CLE to high */
+#define NAND_CLE		0x02
+/* Select the address latch by setting ALE to high */
+#define NAND_ALE		0x04
+
+#define NAND_CTRL_CLE		(NAND_NCE | NAND_CLE)
+#define NAND_CTRL_ALE		(NAND_NCE | NAND_ALE)
+#define NAND_CTRL_CHANGE	0x80
+
+/*
+ * Standard NAND flash commands
+ */
+#define NAND_CMD_READ0		0
+#define NAND_CMD_READ1		1
+#define NAND_CMD_RNDOUT		5
+#define NAND_CMD_PAGEPROG	0x10
+#define NAND_CMD_READOOB	0x50
+#define NAND_CMD_ERASE1		0x60
+#define NAND_CMD_STATUS		0x70
+#define NAND_CMD_STATUS_MULTI	0x71
+#define NAND_CMD_SEQIN		0x80
+#define NAND_CMD_RNDIN		0x85
+#define NAND_CMD_READID		0x90
+#define NAND_CMD_ERASE2		0xd0
+#define NAND_CMD_PARAM		0xec
+#define NAND_CMD_GET_FEATURES	0xee
+#define NAND_CMD_SET_FEATURES	0xef
+#define NAND_CMD_RESET		0xff
+
+#define NAND_CMD_LOCK		0x2a
+#define NAND_CMD_LOCK_TIGHT	0x2c
+#define NAND_CMD_UNLOCK1	0x23
+#define NAND_CMD_UNLOCK2	0x24
+#define NAND_CMD_LOCK_STATUS	0x7a
+
+/* Extended commands for large page devices */
+#define NAND_CMD_READSTART	0x30
+#define NAND_CMD_RNDOUTSTART	0xE0
+#define NAND_CMD_CACHEDPROG	0x15
+
+/* Extended commands for AG-AND device */
+/*
+ * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
+ *       there is no way to distinguish that from NAND_CMD_READ0
+ *       until the remaining sequence of commands has been completed
+ *       so add a high order bit and mask it off in the command.
+ */
+#define NAND_CMD_DEPLETE1	0x100
+#define NAND_CMD_DEPLETE2	0x38
+#define NAND_CMD_STATUS_MULTI	0x71
+#define NAND_CMD_STATUS_ERROR	0x72
+/* multi-bank error status (banks 0-3) */
+#define NAND_CMD_STATUS_ERROR0	0x73
+#define NAND_CMD_STATUS_ERROR1	0x74
+#define NAND_CMD_STATUS_ERROR2	0x75
+#define NAND_CMD_STATUS_ERROR3	0x76
+#define NAND_CMD_STATUS_RESET	0x7f
+#define NAND_CMD_STATUS_CLEAR	0xff
+
+#define NAND_CMD_NONE		-1
+
+/* Status bits */
+#define NAND_STATUS_FAIL	0x01
+#define NAND_STATUS_FAIL_N1	0x02
+#define NAND_STATUS_TRUE_READY	0x20
+#define NAND_STATUS_READY	0x40
+#define NAND_STATUS_WP		0x80
+
+/*
+ * Constants for ECC_MODES
+ */
+typedef enum {
+	NAND_ECC_NONE,
+	NAND_ECC_SOFT,
+	NAND_ECC_HW,
+	NAND_ECC_HW_SYNDROME,
+	NAND_ECC_HW_OOB_FIRST,
+	NAND_ECC_SOFT_BCH,
+} nand_ecc_modes_t;
+
+/*
+ * Constants for Hardware ECC
+ */
+/* Reset Hardware ECC for read */
+#define NAND_ECC_READ		0
+/* Reset Hardware ECC for write */
+#define NAND_ECC_WRITE		1
+/* Enable Hardware ECC before syndrome is read back from flash */
+#define NAND_ECC_READSYN	2
+
+/* Bit mask for flags passed to do_nand_read_ecc */
+#define NAND_GET_DEVICE		0x80
+
+
+/*
+ * Option constants for bizarre disfunctionality and real
+ * features.
+ */
+/* Buswidth is 16 bit */
+#define NAND_BUSWIDTH_16	0x00000002
+/* Device supports partial programming without padding */
+#define NAND_NO_PADDING		0x00000004
+/* Chip has cache program function */
+#define NAND_CACHEPRG		0x00000008
+/* Chip has copy back function */
+#define NAND_COPYBACK		0x00000010
+/*
+ * AND Chip which has 4 banks and a confusing page / block
+ * assignment. See Renesas datasheet for further information.
+ */
+#define NAND_IS_AND		0x00000020
+/*
+ * Chip has a array of 4 pages which can be read without
+ * additional ready /busy waits.
+ */
+#define NAND_4PAGE_ARRAY	0x00000040
+/*
+ * Chip requires that BBT is periodically rewritten to prevent
+ * bits from adjacent blocks from 'leaking' in altering data.
+ * This happens with the Renesas AG-AND chips, possibly others.
+ */
+#define BBT_AUTO_REFRESH	0x00000080
+/* Chip does not allow subpage writes */
+#define NAND_NO_SUBPAGE_WRITE	0x00000200
+
+/* Device is one of 'new' xD cards that expose fake nand command set */
+#define NAND_BROKEN_XD		0x00000400
+
+/* Device behaves just like nand, but is readonly */
+#define NAND_ROM		0x00000800
+
+/* Device supports subpage reads */
+#define NAND_SUBPAGE_READ       0x00001000
+
+/* Options valid for Samsung large page devices */
+#define NAND_SAMSUNG_LP_OPTIONS \
+	(NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
+
+/* Macros to identify the above */
+#define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
+#define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
+#define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
+#define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
+
+/* Non chip related options */
+/* This option skips the bbt scan during initialization. */
+#define NAND_SKIP_BBTSCAN	0x00010000
+/*
+ * This option is defined if the board driver allocates its own buffers
+ * (e.g. because it needs them DMA-coherent).
+ */
+#define NAND_OWN_BUFFERS	0x00020000
+/* Chip may not exist, so silence any errors in scan */
+#define NAND_SCAN_SILENT_NODEV	0x00040000
+
+/* Options set by nand scan */
+/* bbt has already been read */
+#define NAND_BBT_SCANNED	0x40000000
+/* Nand scan has allocated controller struct */
+#define NAND_CONTROLLER_ALLOC	0x80000000
+
+/* Cell info constants */
+#define NAND_CI_CHIPNR_MSK	0x03
+#define NAND_CI_CELLTYPE_MSK	0x0C
+
+/* Keep gcc happy */
+struct nand_chip;
+
+/* ONFI timing mode, used in both asynchronous and synchronous mode */
+#define ONFI_TIMING_MODE_0		(1 << 0)
+#define ONFI_TIMING_MODE_1		(1 << 1)
+#define ONFI_TIMING_MODE_2		(1 << 2)
+#define ONFI_TIMING_MODE_3		(1 << 3)
+#define ONFI_TIMING_MODE_4		(1 << 4)
+#define ONFI_TIMING_MODE_5		(1 << 5)
+#define ONFI_TIMING_MODE_UNKNOWN	(1 << 6)
+
+/* ONFI feature address */
+#define ONFI_FEATURE_ADDR_TIMING_MODE	0x1
+
+/* ONFI subfeature parameters length */
+#define ONFI_SUBFEATURE_PARAM_LEN	4
+
+struct nand_onfi_params {
+	/* rev info and features block */
+	/* 'O' 'N' 'F' 'I'  */
+	u8 sig[4];
+	__le16 revision;
+	__le16 features;
+	__le16 opt_cmd;
+	u8 reserved[22];
+
+	/* manufacturer information block */
+	char manufacturer[12];
+	char model[20];
+	u8 jedec_id;
+	__le16 date_code;
+	u8 reserved2[13];
+
+	/* memory organization block */
+	__le32 byte_per_page;
+	__le16 spare_bytes_per_page;
+	__le32 data_bytes_per_ppage;
+	__le16 spare_bytes_per_ppage;
+	__le32 pages_per_block;
+	__le32 blocks_per_lun;
+	u8 lun_count;
+	u8 addr_cycles;
+	u8 bits_per_cell;
+	__le16 bb_per_lun;
+	__le16 block_endurance;
+	u8 guaranteed_good_blocks;
+	__le16 guaranteed_block_endurance;
+	u8 programs_per_page;
+	u8 ppage_attr;
+	u8 ecc_bits;
+	u8 interleaved_bits;
+	u8 interleaved_ops;
+	u8 reserved3[13];
+
+	/* electrical parameter block */
+	u8 io_pin_capacitance_max;
+	__le16 async_timing_mode;
+	__le16 program_cache_timing_mode;
+	__le16 t_prog;
+	__le16 t_bers;
+	__le16 t_r;
+	__le16 t_ccs;
+	__le16 src_sync_timing_mode;
+	__le16 src_ssync_features;
+	__le16 clk_pin_capacitance_typ;
+	__le16 io_pin_capacitance_typ;
+	__le16 input_pin_capacitance_typ;
+	u8 input_pin_capacitance_max;
+	u8 driver_strenght_support;
+	__le16 t_int_r;
+	__le16 t_ald;
+	u8 reserved4[7];
+
+	/* vendor */
+	u8 reserved5[90];
+
+	__le16 crc;
+} __attribute__((packed));
+
+#define ONFI_CRC_BASE	0x4F4E
+
+/**
+ * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
+ * @lock:               protection lock
+ * @active:		the mtd device which holds the controller currently
+ * @wq:			wait queue to sleep on if a NAND operation is in
+ *			progress used instead of the per chip wait queue
+ *			when a hw controller is available.
+ */
+struct nand_hw_control {
+/* XXX U-BOOT XXX */
+#if 0
+	spinlock_t	 lock;
+	wait_queue_head_t wq;
+#endif
+	struct nand_chip *active;
+};
+
+/**
+ * struct nand_ecc_ctrl - Control structure for ECC
+ * @mode:	ECC mode
+ * @steps:	number of ECC steps per page
+ * @size:	data bytes per ECC step
+ * @bytes:	ECC bytes per step
+ * @strength:	max number of correctible bits per ECC step
+ * @total:	total number of ECC bytes per page
+ * @prepad:	padding information for syndrome based ECC generators
+ * @postpad:	padding information for syndrome based ECC generators
+ * @layout:	ECC layout control struct pointer
+ * @priv:	pointer to private ECC control data
+ * @hwctl:	function to control hardware ECC generator. Must only
+ *		be provided if an hardware ECC is available
+ * @calculate:	function for ECC calculation or readback from ECC hardware
+ * @correct:	function for ECC correction, matching to ECC generator (sw/hw)
+ * @read_page_raw:	function to read a raw page without ECC
+ * @write_page_raw:	function to write a raw page without ECC
+ * @read_page:	function to read a page according to the ECC generator
+ *		requirements; returns maximum number of bitflips corrected in
+ *		any single ECC step, 0 if bitflips uncorrectable, -EIO hw error
+ * @read_subpage:	function to read parts of the page covered by ECC;
+ *			returns same as read_page()
+ * @write_page:	function to write a page according to the ECC generator
+ *		requirements.
+ * @write_oob_raw:	function to write chip OOB data without ECC
+ * @read_oob_raw:	function to read chip OOB data without ECC
+ * @read_oob:	function to read chip OOB data
+ * @write_oob:	function to write chip OOB data
+ */
+struct nand_ecc_ctrl {
+	nand_ecc_modes_t mode;
+	int steps;
+	int size;
+	int bytes;
+	int total;
+	int strength;
+	int prepad;
+	int postpad;
+	struct nand_ecclayout	*layout;
+	void *priv;
+	void (*hwctl)(struct mtd_info *mtd, int mode);
+	int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
+			uint8_t *ecc_code);
+	int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
+			uint8_t *calc_ecc);
+	int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
+			uint8_t *buf, int oob_required, int page);
+	int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
+			const uint8_t *buf, int oob_required);
+	int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
+			uint8_t *buf, int oob_required, int page);
+	int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
+			uint32_t offs, uint32_t len, uint8_t *buf);
+	int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
+			const uint8_t *buf, int oob_required);
+	int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
+			int page);
+	int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
+			int page);
+	int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);
+	int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
+			int page);
+};
+
+/**
+ * struct nand_buffers - buffer structure for read/write
+ * @ecccalc:	buffer for calculated ECC
+ * @ecccode:	buffer for ECC read from flash
+ * @databuf:	buffer for data - dynamically sized
+ *
+ * Do not change the order of buffers. databuf and oobrbuf must be in
+ * consecutive order.
+ */
+struct nand_buffers {
+	uint8_t	ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
+	uint8_t	ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
+	uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE,
+			      ARCH_DMA_MINALIGN)];
+};
+
+/**
+ * struct nand_chip - NAND Private Flash Chip Data
+ * @IO_ADDR_R:		[BOARDSPECIFIC] address to read the 8 I/O lines of the
+ *			flash device
+ * @IO_ADDR_W:		[BOARDSPECIFIC] address to write the 8 I/O lines of the
+ *			flash device.
+ * @read_byte:		[REPLACEABLE] read one byte from the chip
+ * @read_word:		[REPLACEABLE] read one word from the chip
+ * @write_buf:		[REPLACEABLE] write data from the buffer to the chip
+ * @read_buf:		[REPLACEABLE] read data from the chip into the buffer
+ * @verify_buf:		[REPLACEABLE] verify buffer contents against the chip
+ *			data.
+ * @select_chip:	[REPLACEABLE] select chip nr
+ * @block_bad:		[REPLACEABLE] check, if the block is bad
+ * @block_markbad:	[REPLACEABLE] mark the block bad
+ * @cmd_ctrl:		[BOARDSPECIFIC] hardwarespecific function for controlling
+ *			ALE/CLE/nCE. Also used to write command and address
+ * @init_size:		[BOARDSPECIFIC] hardwarespecific function for setting
+ *			mtd->oobsize, mtd->writesize and so on.
+ *			@id_data contains the 8 bytes values of NAND_CMD_READID.
+ *			Return with the bus width.
+ * @dev_ready:		[BOARDSPECIFIC] hardwarespecific function for accessing
+ *			device ready/busy line. If set to NULL no access to
+ *			ready/busy is available and the ready/busy information
+ *			is read from the chip status register.
+ * @cmdfunc:		[REPLACEABLE] hardwarespecific function for writing
+ *			commands to the chip.
+ * @waitfunc:		[REPLACEABLE] hardwarespecific function for wait on
+ *			ready.
+ * @ecc:		[BOARDSPECIFIC] ECC control structure
+ * @buffers:		buffer structure for read/write
+ * @hwcontrol:		platform-specific hardware control structure
+ * @erase_cmd:		[INTERN] erase command write function, selectable due
+ *			to AND support.
+ * @scan_bbt:		[REPLACEABLE] function to scan bad block table
+ * @chip_delay:		[BOARDSPECIFIC] chip dependent delay for transferring
+ *			data from array to read regs (tR).
+ * @state:		[INTERN] the current state of the NAND device
+ * @oob_poi:		"poison value buffer," used for laying out OOB data
+ *			before writing
+ * @page_shift:		[INTERN] number of address bits in a page (column
+ *			address bits).
+ * @phys_erase_shift:	[INTERN] number of address bits in a physical eraseblock
+ * @bbt_erase_shift:	[INTERN] number of address bits in a bbt entry
+ * @chip_shift:		[INTERN] number of address bits in one chip
+ * @options:		[BOARDSPECIFIC] various chip options. They can partly
+ *			be set to inform nand_scan about special functionality.
+ *			See the defines for further explanation.
+ * @bbt_options:	[INTERN] bad block specific options. All options used
+ *			here must come from bbm.h. By default, these options
+ *			will be copied to the appropriate nand_bbt_descr's.
+ * @badblockpos:	[INTERN] position of the bad block marker in the oob
+ *			area.
+ * @badblockbits:	[INTERN] minimum number of set bits in a good block's
+ *			bad block marker position; i.e., BBM == 11110111b is
+ *			not bad when badblockbits == 7
+ * @cellinfo:		[INTERN] MLC/multichip data from chip ident
+ * @numchips:		[INTERN] number of physical chips
+ * @chipsize:		[INTERN] the size of one chip for multichip arrays
+ * @pagemask:		[INTERN] page number mask = number of (pages / chip) - 1
+ * @pagebuf:		[INTERN] holds the pagenumber which is currently in
+ *			data_buf.
+ * @pagebuf_bitflips:	[INTERN] holds the bitflip count for the page which is
+ *			currently in data_buf.
+ * @subpagesize:	[INTERN] holds the subpagesize
+ * @onfi_version:	[INTERN] holds the chip ONFI version (BCD encoded),
+ *			non 0 if ONFI supported.
+ * @onfi_params:	[INTERN] holds the ONFI page parameter when ONFI is
+ *			supported, 0 otherwise.
+ * @onfi_set_features	[REPLACEABLE] set the features for ONFI nand
+ * @onfi_get_features	[REPLACEABLE] get the features for ONFI nand
+ * @ecclayout:		[REPLACEABLE] the default ECC placement scheme
+ * @bbt:		[INTERN] bad block table pointer
+ * @bbt_td:		[REPLACEABLE] bad block table descriptor for flash
+ *			lookup.
+ * @bbt_md:		[REPLACEABLE] bad block table mirror descriptor
+ * @badblock_pattern:	[REPLACEABLE] bad block scan pattern used for initial
+ *			bad block scan.
+ * @controller:		[REPLACEABLE] a pointer to a hardware controller
+ *			structure which is shared among multiple independent
+ *			devices.
+ * @priv:		[OPTIONAL] pointer to private chip data
+ * @errstat:		[OPTIONAL] hardware specific function to perform
+ *			additional error status checks (determine if errors are
+ *			correctable).
+ * @write_page:		[REPLACEABLE] High-level page write function
+ */
+
+struct nand_chip {
+	void __iomem *IO_ADDR_R;
+	void __iomem *IO_ADDR_W;
+
+	uint8_t (*read_byte)(struct mtd_info *mtd);
+	u16 (*read_word)(struct mtd_info *mtd);
+	void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
+	void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
+	int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
+	void (*select_chip)(struct mtd_info *mtd, int chip);
+	int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
+	int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
+	void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
+	int (*init_size)(struct mtd_info *mtd, struct nand_chip *this,
+			u8 *id_data);
+	int (*dev_ready)(struct mtd_info *mtd);
+	void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
+			int page_addr);
+	int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
+	void (*erase_cmd)(struct mtd_info *mtd, int page);
+	int (*scan_bbt)(struct mtd_info *mtd);
+	int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state,
+			int status, int page);
+	int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
+			const uint8_t *buf, int oob_required, int page,
+			int cached, int raw);
+	int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
+			int feature_addr, uint8_t *subfeature_para);
+	int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
+			int feature_addr, uint8_t *subfeature_para);
+
+	int chip_delay;
+	unsigned int options;
+	unsigned int bbt_options;
+
+	int page_shift;
+	int phys_erase_shift;
+	int bbt_erase_shift;
+	int chip_shift;
+	int numchips;
+	uint64_t chipsize;
+	int pagemask;
+	int pagebuf;
+	unsigned int pagebuf_bitflips;
+	int subpagesize;
+	uint8_t cellinfo;
+	int badblockpos;
+	int badblockbits;
+
+	int onfi_version;
+#ifdef CONFIG_SYS_NAND_ONFI_DETECTION
+	struct nand_onfi_params onfi_params;
+#endif
+
+	int state;
+
+	uint8_t *oob_poi;
+	struct nand_hw_control *controller;
+	struct nand_ecclayout *ecclayout;
+
+	struct nand_ecc_ctrl ecc;
+	struct nand_buffers *buffers;
+	struct nand_hw_control hwcontrol;
+
+	uint8_t *bbt;
+	struct nand_bbt_descr *bbt_td;
+	struct nand_bbt_descr *bbt_md;
+
+	struct nand_bbt_descr *badblock_pattern;
+
+	void *priv;
+};
+
+/*
+ * NAND Flash Manufacturer ID Codes
+ */
+#define NAND_MFR_TOSHIBA	0x98
+#define NAND_MFR_SAMSUNG	0xec
+#define NAND_MFR_FUJITSU	0x04
+#define NAND_MFR_NATIONAL	0x8f
+#define NAND_MFR_RENESAS	0x07
+#define NAND_MFR_STMICRO	0x20
+#define NAND_MFR_HYNIX		0xad
+#define NAND_MFR_MICRON		0x2c
+#define NAND_MFR_AMD		0x01
+#define NAND_MFR_MACRONIX	0xc2
+#define NAND_MFR_EON		0x92
+
+/**
+ * struct nand_flash_dev - NAND Flash Device ID Structure
+ * @name:	Identify the device type
+ * @id:		device ID code
+ * @pagesize:	Pagesize in bytes. Either 256 or 512 or 0
+ *		If the pagesize is 0, then the real pagesize
+ *		and the eraseize are determined from the
+ *		extended id bytes in the chip
+ * @erasesize:	Size of an erase block in the flash device.
+ * @chipsize:	Total chipsize in Mega Bytes
+ * @options:	Bitfield to store chip relevant options
+ */
+struct nand_flash_dev {
+	char *name;
+	int id;
+	unsigned long pagesize;
+	unsigned long chipsize;
+	unsigned long erasesize;
+	unsigned long options;
+};
+
+/**
+ * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
+ * @name:	Manufacturer name
+ * @id:		manufacturer ID code of device.
+*/
+struct nand_manufacturers {
+	int id;
+	char *name;
+};
+
+extern const struct nand_flash_dev nand_flash_ids[];
+extern const struct nand_manufacturers nand_manuf_ids[];
+
+extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
+extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs);
+extern int nand_default_bbt(struct mtd_info *mtd);
+extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
+extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
+			   int allowbbt);
+extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
+			size_t *retlen, uint8_t *buf);
+
+/*
+* Constants for oob configuration
+*/
+#define NAND_SMALL_BADBLOCK_POS		5
+#define NAND_LARGE_BADBLOCK_POS		0
+
+/**
+ * struct platform_nand_chip - chip level device structure
+ * @nr_chips:		max. number of chips to scan for
+ * @chip_offset:	chip number offset
+ * @nr_partitions:	number of partitions pointed to by partitions (or zero)
+ * @partitions:		mtd partition list
+ * @chip_delay:		R/B delay value in us
+ * @options:		Option flags, e.g. 16bit buswidth
+ * @bbt_options:	BBT option flags, e.g. NAND_BBT_USE_FLASH
+ * @ecclayout:		ECC layout info structure
+ * @part_probe_types:	NULL-terminated array of probe types
+ */
+struct platform_nand_chip {
+	int nr_chips;
+	int chip_offset;
+	int nr_partitions;
+	struct mtd_partition *partitions;
+	struct nand_ecclayout *ecclayout;
+	int chip_delay;
+	unsigned int options;
+	unsigned int bbt_options;
+	const char **part_probe_types;
+};
+
+/* Keep gcc happy */
+struct platform_device;
+
+/**
+ * struct platform_nand_ctrl - controller level device structure
+ * @hwcontrol:		platform specific hardware control structure
+ * @dev_ready:		platform specific function to read ready/busy pin
+ * @select_chip:	platform specific chip select function
+ * @cmd_ctrl:		platform specific function for controlling
+ *			ALE/CLE/nCE. Also used to write command and address
+ * @priv:		private data to transport driver specific settings
+ *
+ * All fields are optional and depend on the hardware driver requirements
+ */
+struct platform_nand_ctrl {
+	void (*hwcontrol)(struct mtd_info *mtd, int cmd);
+	int (*dev_ready)(struct mtd_info *mtd);
+	void (*select_chip)(struct mtd_info *mtd, int chip);
+	void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
+	unsigned char (*read_byte)(struct mtd_info *mtd);
+	void *priv;
+};
+
+/**
+ * struct platform_nand_data - container structure for platform-specific data
+ * @chip:		chip level chip structure
+ * @ctrl:		controller level device structure
+ */
+struct platform_nand_data {
+	struct platform_nand_chip chip;
+	struct platform_nand_ctrl ctrl;
+};
+
+/* Some helpers to access the data structures */
+static inline
+struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
+{
+	struct nand_chip *chip = mtd->priv;
+
+	return chip->priv;
+}
+
+/* Standard NAND functions from nand_base.c */
+void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len);
+void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len);
+void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len);
+void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len);
+uint8_t nand_read_byte(struct mtd_info *mtd);
+
+/* return the supported asynchronous timing mode. */
+
+#ifdef CONFIG_SYS_NAND_ONFI_DETECTION
+static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
+{
+	if (!chip->onfi_version)
+		return ONFI_TIMING_MODE_UNKNOWN;
+	return le16_to_cpu(chip->onfi_params.async_timing_mode);
+}
+
+/* return the supported synchronous timing mode. */
+static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
+{
+	if (!chip->onfi_version)
+		return ONFI_TIMING_MODE_UNKNOWN;
+	return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
+}
+#endif
+
+#endif /* __LINUX_MTD_NAND_H */
diff --git a/qemu/roms/u-boot/include/linux/mtd/nand_bch.h b/qemu/roms/u-boot/include/linux/mtd/nand_bch.h
new file mode 100644
index 000000000..d8754dd8c
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/mtd/nand_bch.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright © 2011 Ivan Djelic <ivan.djelic@parrot.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file is the header for the NAND BCH ECC implementation.
+ */
+
+#ifndef __MTD_NAND_BCH_H__
+#define __MTD_NAND_BCH_H__
+
+struct mtd_info;
+struct nand_bch_control;
+
+#if defined(CONFIG_NAND_ECC_BCH)
+
+static inline int mtd_nand_has_bch(void) { return 1; }
+
+/*
+ * Calculate BCH ecc code
+ */
+int nand_bch_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
+			   u_char *ecc_code);
+
+/*
+ * Detect and correct bit errors
+ */
+int nand_bch_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc,
+			  u_char *calc_ecc);
+/*
+ * Initialize BCH encoder/decoder
+ */
+struct nand_bch_control *
+nand_bch_init(struct mtd_info *mtd, unsigned int eccsize,
+	      unsigned int eccbytes, struct nand_ecclayout **ecclayout);
+/*
+ * Release BCH encoder/decoder resources
+ */
+void nand_bch_free(struct nand_bch_control *nbc);
+
+#else /* !CONFIG_NAND_ECC_BCH */
+
+static inline int mtd_nand_has_bch(void) { return 0; }
+
+static inline int
+nand_bch_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
+		       u_char *ecc_code)
+{
+	return -1;
+}
+
+static inline int
+nand_bch_correct_data(struct mtd_info *mtd, unsigned char *buf,
+		      unsigned char *read_ecc, unsigned char *calc_ecc)
+{
+	return -1;
+}
+
+static inline struct nand_bch_control *
+nand_bch_init(struct mtd_info *mtd, unsigned int eccsize,
+	      unsigned int eccbytes, struct nand_ecclayout **ecclayout)
+{
+	return NULL;
+}
+
+static inline void nand_bch_free(struct nand_bch_control *nbc) {}
+
+#endif /* CONFIG_NAND_ECC_BCH */
+
+#endif /* __MTD_NAND_BCH_H__ */
diff --git a/qemu/roms/u-boot/include/linux/mtd/nand_ecc.h b/qemu/roms/u-boot/include/linux/mtd/nand_ecc.h
new file mode 100644
index 000000000..090da5054
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/mtd/nand_ecc.h
@@ -0,0 +1,28 @@
+/*
+ *  drivers/mtd/nand_ecc.h
+ *
+ *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file is the header for the ECC algorithm.
+ */
+
+#ifndef __MTD_NAND_ECC_H__
+#define __MTD_NAND_ECC_H__
+
+struct mtd_info;
+
+/*
+ * Calculate 3 byte ECC code for 256 byte block
+ */
+int nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code);
+
+/*
+ * Detect and correct a 1 bit error for 256 byte block
+ */
+int nand_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc);
+
+#endif /* __MTD_NAND_ECC_H__ */
diff --git a/qemu/roms/u-boot/include/linux/mtd/ndfc.h b/qemu/roms/u-boot/include/linux/mtd/ndfc.h
new file mode 100644
index 000000000..d0558a982
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/mtd/ndfc.h
@@ -0,0 +1,67 @@
+/*
+ *  linux/include/linux/mtd/ndfc.h
+ *
+ *  Copyright (c) 2006 Thomas Gleixner <tglx@linutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Info:
+ *   Contains defines, datastructures for ndfc nand controller
+ *
+ */
+#ifndef __LINUX_MTD_NDFC_H
+#define __LINUX_MTD_NDFC_H
+
+/* NDFC Register definitions */
+#define NDFC_CMD		0x00
+#define NDFC_ALE		0x04
+#define NDFC_DATA		0x08
+#define NDFC_ECC		0x10
+#define NDFC_BCFG0		0x30
+#define NDFC_BCFG1		0x34
+#define NDFC_BCFG2		0x38
+#define NDFC_BCFG3		0x3c
+#define NDFC_CCR		0x40
+#define NDFC_STAT		0x44
+#define NDFC_HWCTL		0x48
+#define NDFC_REVID		0x50
+
+#define NDFC_STAT_IS_READY	0x01000000
+
+#define NDFC_CCR_RESET_CE	0x80000000 /* CE Reset */
+#define NDFC_CCR_RESET_ECC	0x40000000 /* ECC Reset */
+#define NDFC_CCR_RIE		0x20000000 /* Interrupt Enable on Device Rdy */
+#define NDFC_CCR_REN		0x10000000 /* Enable wait for Rdy in LinearR */
+#define NDFC_CCR_ROMEN		0x08000000 /* Enable ROM In LinearR */
+#define NDFC_CCR_ARE		0x04000000 /* Auto-Read Enable */
+#define NDFC_CCR_BS(x)		(((x) & 0x3) << 24) /* Select Bank on CE[x] */
+#define NDFC_CCR_BS_MASK	0x03000000 /* Select Bank */
+#define NDFC_CCR_ARAC0		0x00000000 /* 3 Addr, 1 Col 2 Row 512b page */
+#define NDFC_CCR_ARAC1		0x00001000 /* 4 Addr, 1 Col 3 Row 512b page */
+#define NDFC_CCR_ARAC2		0x00002000 /* 4 Addr, 2 Col 2 Row 2K page */
+#define NDFC_CCR_ARAC3		0x00003000 /* 5 Addr, 2 Col 3 Row 2K page */
+#define NDFC_CCR_ARAC_MASK	0x00003000 /* Auto-Read mode Addr Cycles */
+#define NDFC_CCR_RPG		0x0000C000 /* Auto-Read Page */
+#define NDFC_CCR_EBCC		0x00000004 /* EBC Configuration Completed */
+#define NDFC_CCR_DHC		0x00000002 /* Direct Hardware Control Enable */
+
+#define NDFC_BxCFG_EN		0x80000000 /* Bank Enable */
+#define NDFC_BxCFG_CED		0x40000000 /* nCE Style */
+#define NDFC_BxCFG_SZ_MASK	0x08000000 /* Bank Size */
+#define NDFC_BxCFG_SZ_8BIT	0x00000000 /* 8bit */
+#define NDFC_BxCFG_SZ_16BIT	0x08000000 /* 16bit */
+
+#define NDFC_MAX_BANKS		4
+
+struct ndfc_controller_settings {
+	uint32_t	ccr_settings;
+	uint64_t	ndfc_erpn;
+};
+
+struct ndfc_chip_settings {
+	uint32_t	bank_settings;
+};
+
+#endif
diff --git a/qemu/roms/u-boot/include/linux/mtd/omap_elm.h b/qemu/roms/u-boot/include/linux/mtd/omap_elm.h
new file mode 100644
index 000000000..45454eaf0
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/mtd/omap_elm.h
@@ -0,0 +1,77 @@
+/*
+ * (C) Copyright 2010-2011 Texas Instruments, <www.ti.com>
+ * Mansoor Ahamed <mansoor.ahamed@ti.com>
+ *
+ * Derived from work done by Rohit Choraria <rohitkc@ti.com> for omap3
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __ASM_ARCH_ELM_H
+#define __ASM_ARCH_ELM_H
+/*
+ * ELM Module Registers
+ */
+
+/* ELM registers bit fields */
+#define ELM_SYSCONFIG_SOFTRESET_MASK			(0x2)
+#define ELM_SYSCONFIG_SOFTRESET			(0x2)
+#define ELM_SYSSTATUS_RESETDONE_MASK			(0x1)
+#define ELM_SYSSTATUS_RESETDONE			(0x1)
+#define ELM_LOCATION_CONFIG_ECC_BCH_LEVEL_MASK		(0x3)
+#define ELM_LOCATION_CONFIG_ECC_SIZE_MASK		(0x7FF0000)
+#define ELM_LOCATION_CONFIG_ECC_SIZE_POS		(16)
+#define ELM_SYNDROME_FRAGMENT_6_SYNDROME_VALID		(0x00010000)
+#define ELM_LOCATION_STATUS_ECC_CORRECTABLE_MASK	(0x100)
+#define ELM_LOCATION_STATUS_ECC_NB_ERRORS_MASK		(0x1F)
+
+#ifndef __ASSEMBLY__
+
+enum bch_level {
+	BCH_4_BIT = 0,
+	BCH_8_BIT,
+	BCH_16_BIT
+};
+
+
+/* BCH syndrome registers */
+struct syndrome {
+	u32 syndrome_fragment_x[7];	/* 0x400, 0x404.... 0x418 */
+	u8 res1[36];			/* 0x41c */
+};
+
+/* BCH error status & location register */
+struct location {
+	u32 location_status;		/* 0x800 */
+	u8 res1[124];			/* 0x804 */
+	u32 error_location_x[16];	/* 0x880.... */
+	u8 res2[64];			/* 0x8c0 */
+};
+
+/* BCH ELM register map - do not try to allocate memmory for this structure.
+ * We have used plenty of reserved variables to fill the slots in the ELM
+ * register memory map.
+ * Directly initialize the struct pointer to ELM base address.
+ */
+struct elm {
+	u32 rev;				/* 0x000 */
+	u8 res1[12];				/* 0x004 */
+	u32 sysconfig;				/* 0x010 */
+	u32 sysstatus;				/* 0x014 */
+	u32 irqstatus;				/* 0x018 */
+	u32 irqenable;				/* 0x01c */
+	u32 location_config;			/* 0x020 */
+	u8 res2[92];				/* 0x024 */
+	u32 page_ctrl;				/* 0x080 */
+	u8 res3[892];				/* 0x084 */
+	struct  syndrome syndrome_fragments[8]; /* 0x400 */
+	u8 res4[512];				/* 0x600 */
+	struct location  error_location[8];	/* 0x800 */
+};
+
+int elm_check_error(u8 *syndrome, u32 nibbles, u32 *error_count,
+		u32 *error_locations);
+int elm_config(enum bch_level level);
+void elm_reset(void);
+void elm_init(void);
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_ARCH_ELM_H */
diff --git a/qemu/roms/u-boot/include/linux/mtd/omap_gpmc.h b/qemu/roms/u-boot/include/linux/mtd/omap_gpmc.h
new file mode 100644
index 000000000..22f657396
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/mtd/omap_gpmc.h
@@ -0,0 +1,84 @@
+/*
+ * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
+ * Rohit Choraria <rohitkc@ti.com>
+ *
+ * (C) Copyright 2013 Andreas Bießmann <andreas.devel@googlemail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __ASM_OMAP_GPMC_H
+#define __ASM_OMAP_GPMC_H
+
+#define GPMC_BUF_EMPTY	0
+#define GPMC_BUF_FULL	1
+
+enum omap_ecc {
+	/* 1-bit  ECC calculation by Software, Error detection by Software */
+	OMAP_ECC_HAM1_CODE_SW = 1, /* avoid un-initialized int can be 0x0 */
+	/* 1-bit  ECC calculation by GPMC, Error detection by Software */
+	/* ECC layout compatible to legacy ROMCODE. */
+	OMAP_ECC_HAM1_CODE_HW,
+	/* 4-bit  ECC calculation by GPMC, Error detection by Software */
+	OMAP_ECC_BCH4_CODE_HW_DETECTION_SW,
+	/* 4-bit  ECC calculation by GPMC, Error detection by ELM */
+	OMAP_ECC_BCH4_CODE_HW,
+	/* 8-bit  ECC calculation by GPMC, Error detection by Software */
+	OMAP_ECC_BCH8_CODE_HW_DETECTION_SW,
+	/* 8-bit  ECC calculation by GPMC, Error detection by ELM */
+	OMAP_ECC_BCH8_CODE_HW,
+};
+
+struct gpmc_cs {
+	u32 config1;		/* 0x00 */
+	u32 config2;		/* 0x04 */
+	u32 config3;		/* 0x08 */
+	u32 config4;		/* 0x0C */
+	u32 config5;		/* 0x10 */
+	u32 config6;		/* 0x14 */
+	u32 config7;		/* 0x18 */
+	u32 nand_cmd;		/* 0x1C */
+	u32 nand_adr;		/* 0x20 */
+	u32 nand_dat;		/* 0x24 */
+	u8 res[8];		/* blow up to 0x30 byte */
+};
+
+struct bch_res_0_3 {
+	u32 bch_result_x[4];
+};
+
+struct gpmc {
+	u8 res1[0x10];
+	u32 sysconfig;		/* 0x10 */
+	u8 res2[0x4];
+	u32 irqstatus;		/* 0x18 */
+	u32 irqenable;		/* 0x1C */
+	u8 res3[0x20];
+	u32 timeout_control;	/* 0x40 */
+	u8 res4[0xC];
+	u32 config;		/* 0x50 */
+	u32 status;		/* 0x54 */
+	u8 res5[0x8];		/* 0x58 */
+	struct gpmc_cs cs[8];	/* 0x60, 0x90, .. */
+	u8 res6[0x14];		/* 0x1E0 */
+	u32 ecc_config;		/* 0x1F4 */
+	u32 ecc_control;	/* 0x1F8 */
+	u32 ecc_size_config;	/* 0x1FC */
+	u32 ecc1_result;	/* 0x200 */
+	u32 ecc2_result;	/* 0x204 */
+	u32 ecc3_result;	/* 0x208 */
+	u32 ecc4_result;	/* 0x20C */
+	u32 ecc5_result;	/* 0x210 */
+	u32 ecc6_result;	/* 0x214 */
+	u32 ecc7_result;	/* 0x218 */
+	u32 ecc8_result;	/* 0x21C */
+	u32 ecc9_result;	/* 0x220 */
+	u8 res7[12];		/* 0x224 */
+	u32 testmomde_ctrl;	/* 0x230 */
+	u8 res8[12];		/* 0x234 */
+	struct bch_res_0_3 bch_result_0_3[2];	/* 0x240 */
+};
+
+/* Used for board specific gpmc initialization */
+extern struct gpmc *gpmc_cfg;
+
+#endif /* __ASM_OMAP_GPMC_H */
diff --git a/qemu/roms/u-boot/include/linux/mtd/onenand.h b/qemu/roms/u-boot/include/linux/mtd/onenand.h
new file mode 100644
index 000000000..e7b63ddd1
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/mtd/onenand.h
@@ -0,0 +1,180 @@
+/*
+ *  linux/include/linux/mtd/onenand.h
+ *
+ *  Copyright (C) 2005-2007 Samsung Electronics
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __LINUX_MTD_ONENAND_H
+#define __LINUX_MTD_ONENAND_H
+
+#include <linux/mtd/onenand_regs.h>
+
+/* Note: The header order is impoertant */
+#include <onenand_uboot.h>
+
+#include <linux/compat.h>
+#include <linux/mtd/bbm.h>
+
+#define MAX_DIES		2
+#define MAX_BUFFERRAM		2
+#define MAX_ONENAND_PAGESIZE	(4096 + 128)
+
+/* Scan and identify a OneNAND device */
+extern int onenand_scan (struct mtd_info *mtd, int max_chips);
+/* Free resources held by the OneNAND device */
+extern void onenand_release (struct mtd_info *mtd);
+
+/**
+ * struct onenand_bufferram - OneNAND BufferRAM Data
+ * @param blockpage	block & page address in BufferRAM
+ */
+struct onenand_bufferram {
+	int blockpage;
+};
+
+/**
+ * struct onenand_chip - OneNAND Private Flash Chip Data
+ * @param base		[BOARDSPECIFIC] address to access OneNAND
+ * @dies:               [INTERN][FLEXONENAND] number of dies on chip
+ * @boundary:           [INTERN][FLEXONENAND] Boundary of the dies
+ * @diesize:            [INTERN][FLEXONENAND] Size of the dies
+ * @param chipsize	[INTERN] the size of one chip for multichip arrays
+ * @param device_id	[INTERN] device ID
+ * @param verstion_id	[INTERN] version ID
+ * @technology		[INTERN] describes the internal NAND array technology such as SLC or MLC.
+ * @density_mask:	[INTERN] chip density, used for DDP devices
+ * @param options	[BOARDSPECIFIC] various chip options. They can partly be set to inform onenand_scan about
+ * @param erase_shift	[INTERN] number of address bits in a block
+ * @param page_shift	[INTERN] number of address bits in a page
+ * @param ppb_shift	[INTERN] number of address bits in a pages per block
+ * @param page_mask	[INTERN] a page per block mask
+ * @param writesize	[INTERN] a real page size
+ * @param bufferam_index	[INTERN] BufferRAM index
+ * @param bufferam	[INTERN] BufferRAM info
+ * @param readw		[REPLACEABLE] hardware specific function for read short
+ * @param writew	[REPLACEABLE] hardware specific function for write short
+ * @param command	[REPLACEABLE] hardware specific function for writing commands to the chip
+ * @param wait		[REPLACEABLE] hardware specific function for wait on ready
+ * @param read_bufferram	[REPLACEABLE] hardware specific function for BufferRAM Area
+ * @param write_bufferram	[REPLACEABLE] hardware specific function for BufferRAM Area
+ * @param chip_lock	[INTERN] spinlock used to protect access to this structure and the chip
+ * @param wq		[INTERN] wait queue to sleep on if a OneNAND operation is in progress
+ * @param state		[INTERN] the current state of the OneNAND device
+ * @param autooob	[REPLACEABLE] the default (auto)placement scheme
+ * @param priv		[OPTIONAL] pointer to private chip date
+ */
+struct onenand_chip {
+	void __iomem *base;
+	unsigned int dies;
+	unsigned int boundary[MAX_DIES];
+	unsigned int diesize[MAX_DIES];
+	unsigned int chipsize;
+	unsigned int device_id;
+	unsigned int version_id;
+	unsigned int technology;
+	unsigned int density_mask;
+	unsigned int options;
+
+	unsigned int erase_shift;
+	unsigned int page_shift;
+	unsigned int ppb_shift;	/* Pages per block shift */
+	unsigned int page_mask;
+	unsigned int writesize;
+
+	unsigned int bufferram_index;
+	struct onenand_bufferram bufferram[MAX_BUFFERRAM];
+
+	int (*command) (struct mtd_info *mtd, int cmd, loff_t address,
+			size_t len);
+	int (*wait) (struct mtd_info *mtd, int state);
+	int (*bbt_wait) (struct mtd_info *mtd, int state);
+	void (*unlock_all)(struct mtd_info *mtd);
+	int (*read_bufferram) (struct mtd_info *mtd, loff_t addr, int area,
+			       unsigned char *buffer, int offset, size_t count);
+	int (*write_bufferram) (struct mtd_info *mtd, loff_t addr, int area,
+				const unsigned char *buffer, int offset,
+				size_t count);
+	unsigned short (*read_word) (void __iomem *addr);
+	void (*write_word) (unsigned short value, void __iomem *addr);
+	int (*chip_probe)(struct mtd_info *mtd);
+	void (*mmcontrol) (struct mtd_info *mtd, int sync_read);
+	int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
+	int (*scan_bbt)(struct mtd_info *mtd);
+
+	unsigned char		*main_buf;
+	unsigned char		*spare_buf;
+#ifdef DONT_USE_UBOOT
+	spinlock_t chip_lock;
+	wait_queue_head_t wq;
+#endif
+	int state;
+	unsigned char		*page_buf;
+	unsigned char		*oob_buf;
+
+	struct nand_oobinfo *autooob;
+	int			subpagesize;
+	struct nand_ecclayout	*ecclayout;
+
+	void *bbm;
+
+	void *priv;
+};
+
+/*
+ * Helper macros
+ */
+#define ONENAND_CURRENT_BUFFERRAM(this)		(this->bufferram_index)
+#define ONENAND_NEXT_BUFFERRAM(this)		(this->bufferram_index ^ 1)
+#define ONENAND_SET_NEXT_BUFFERRAM(this)	(this->bufferram_index ^= 1)
+#define ONENAND_SET_PREV_BUFFERRAM(this)	(this->bufferram_index ^= 1)
+#define ONENAND_SET_BUFFERRAM0(this)		(this->bufferram_index = 0)
+#define ONENAND_SET_BUFFERRAM1(this)		(this->bufferram_index = 1)
+
+#define FLEXONENAND(this)	(this->device_id & DEVICE_IS_FLEXONENAND)
+#define ONENAND_IS_MLC(this)	(this->technology & ONENAND_TECHNOLOGY_IS_MLC)
+#define ONENAND_IS_DDP(this)						\
+	(this->device_id & ONENAND_DEVICE_IS_DDP)
+
+#define ONENAND_IS_4KB_PAGE(this)					\
+	(this->options & ONENAND_HAS_4KB_PAGE)
+
+#define ONENAND_IS_2PLANE(this)			(0)
+
+/*
+ * Options bits
+ */
+#define ONENAND_HAS_CONT_LOCK		(0x0001)
+#define ONENAND_HAS_UNLOCK_ALL		(0x0002)
+#define ONENAND_HAS_2PLANE		(0x0004)
+#define ONENAND_HAS_4KB_PAGE            (0x0008)
+#define ONENAND_RUNTIME_BADBLOCK_CHECK	(0x0200)
+#define ONENAND_PAGEBUF_ALLOC		(0x1000)
+#define ONENAND_OOBBUF_ALLOC		(0x2000)
+
+/*
+ * OneNAND Flash Manufacturer ID Codes
+ */
+#define ONENAND_MFR_NUMONYX	0x20
+#define ONENAND_MFR_SAMSUNG	0xec
+
+/**
+ * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
+ * @param name:		Manufacturer name
+ * @param id:		manufacturer ID code of device.
+*/
+struct onenand_manufacturers {
+	int id;
+	char *name;
+};
+
+int onenand_bbt_read_oob(struct mtd_info *mtd, loff_t from,
+			struct mtd_oob_ops *ops);
+
+unsigned int onenand_block(struct onenand_chip *this, loff_t addr);
+int flexonenand_region(struct mtd_info *mtd, loff_t addr);
+#endif				/* __LINUX_MTD_ONENAND_H */
diff --git a/qemu/roms/u-boot/include/linux/mtd/onenand_regs.h b/qemu/roms/u-boot/include/linux/mtd/onenand_regs.h
new file mode 100644
index 000000000..8449a3cdc
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/mtd/onenand_regs.h
@@ -0,0 +1,208 @@
+/*
+ *  linux/include/linux/mtd/onenand_regs.h
+ *
+ *  OneNAND Register header file
+ *
+ *  Copyright (C) 2005-2007 Samsung Electronics
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ONENAND_REG_H
+#define __ONENAND_REG_H
+
+/* Memory Address Map Translation (Word order) */
+#define ONENAND_MEMORY_MAP(x)		((x) << 1)
+
+/*
+ * External BufferRAM area
+ */
+#define	ONENAND_BOOTRAM			ONENAND_MEMORY_MAP(0x0000)
+#define	ONENAND_DATARAM			ONENAND_MEMORY_MAP(0x0200)
+#define	ONENAND_SPARERAM		ONENAND_MEMORY_MAP(0x8010)
+
+/*
+ * OneNAND Registers
+ */
+#define ONENAND_REG_MANUFACTURER_ID	ONENAND_MEMORY_MAP(0xF000)
+#define ONENAND_REG_DEVICE_ID		ONENAND_MEMORY_MAP(0xF001)
+#define ONENAND_REG_VERSION_ID		ONENAND_MEMORY_MAP(0xF002)
+#define ONENAND_REG_DATA_BUFFER_SIZE	ONENAND_MEMORY_MAP(0xF003)
+#define ONENAND_REG_BOOT_BUFFER_SIZE	ONENAND_MEMORY_MAP(0xF004)
+#define ONENAND_REG_NUM_BUFFERS		ONENAND_MEMORY_MAP(0xF005)
+#define ONENAND_REG_TECHNOLOGY		ONENAND_MEMORY_MAP(0xF006)
+
+#define ONENAND_REG_START_ADDRESS1	ONENAND_MEMORY_MAP(0xF100)
+#define ONENAND_REG_START_ADDRESS2	ONENAND_MEMORY_MAP(0xF101)
+#define ONENAND_REG_START_ADDRESS3	ONENAND_MEMORY_MAP(0xF102)
+#define ONENAND_REG_START_ADDRESS4	ONENAND_MEMORY_MAP(0xF103)
+#define ONENAND_REG_START_ADDRESS5	ONENAND_MEMORY_MAP(0xF104)
+#define ONENAND_REG_START_ADDRESS6	ONENAND_MEMORY_MAP(0xF105)
+#define ONENAND_REG_START_ADDRESS7	ONENAND_MEMORY_MAP(0xF106)
+#define ONENAND_REG_START_ADDRESS8	ONENAND_MEMORY_MAP(0xF107)
+
+#define ONENAND_REG_START_BUFFER	ONENAND_MEMORY_MAP(0xF200)
+#define ONENAND_REG_COMMAND		ONENAND_MEMORY_MAP(0xF220)
+#define ONENAND_REG_SYS_CFG1		ONENAND_MEMORY_MAP(0xF221)
+#define ONENAND_REG_SYS_CFG2		ONENAND_MEMORY_MAP(0xF222)
+#define ONENAND_REG_CTRL_STATUS		ONENAND_MEMORY_MAP(0xF240)
+#define ONENAND_REG_INTERRUPT		ONENAND_MEMORY_MAP(0xF241)
+#define ONENAND_REG_START_BLOCK_ADDRESS	ONENAND_MEMORY_MAP(0xF24C)
+#define ONENAND_REG_END_BLOCK_ADDRESS	ONENAND_MEMORY_MAP(0xF24D)
+#define ONENAND_REG_WP_STATUS		ONENAND_MEMORY_MAP(0xF24E)
+
+#define ONENAND_REG_ECC_STATUS		ONENAND_MEMORY_MAP(0xFF00)
+#define ONENAND_REG_ECC_M0		ONENAND_MEMORY_MAP(0xFF01)
+#define ONENAND_REG_ECC_S0		ONENAND_MEMORY_MAP(0xFF02)
+#define ONENAND_REG_ECC_M1		ONENAND_MEMORY_MAP(0xFF03)
+#define ONENAND_REG_ECC_S1		ONENAND_MEMORY_MAP(0xFF04)
+#define ONENAND_REG_ECC_M2		ONENAND_MEMORY_MAP(0xFF05)
+#define ONENAND_REG_ECC_S2		ONENAND_MEMORY_MAP(0xFF06)
+#define ONENAND_REG_ECC_M3		ONENAND_MEMORY_MAP(0xFF07)
+#define ONENAND_REG_ECC_S3		ONENAND_MEMORY_MAP(0xFF08)
+
+/*
+ * Device ID Register F001h (R)
+ */
+#define DEVICE_IS_FLEXONENAND		(1 << 9)
+#define FLEXONENAND_PI_MASK		(0x3ff)
+#define FLEXONENAND_PI_UNLOCK_SHIFT	(14)
+#define ONENAND_DEVICE_DENSITY_MASK	(0xf)
+#define ONENAND_DEVICE_DENSITY_SHIFT	(4)
+#define ONENAND_DEVICE_IS_DDP		(1 << 3)
+#define ONENAND_DEVICE_IS_DEMUX		(1 << 2)
+#define ONENAND_DEVICE_VCC_MASK		(0x3)
+
+#define ONENAND_DEVICE_DENSITY_512Mb	(0x002)
+#define ONENAND_DEVICE_DENSITY_1Gb	(0x003)
+#define ONENAND_DEVICE_DENSITY_2Gb	(0x004)
+#define ONENAND_DEVICE_DENSITY_4Gb	(0x005)
+
+/*
+ * Version ID Register F002h (R)
+ */
+#define ONENAND_VERSION_PROCESS_SHIFT	(8)
+
+/*
+ * Technology Register F006h (R)
+ */
+#define ONENAND_TECHNOLOGY_IS_MLC	(1 << 0)
+
+/*
+ * Start Address 1 F100h (R/W)
+ */
+#define ONENAND_DDP_SHIFT		(15)
+#define ONENAND_DDP_CHIP0		(0)
+#define ONENAND_DDP_CHIP1		(1 << ONENAND_DDP_SHIFT)
+
+/*
+ * Start Address 8 F107h (R/W)
+ */
+#define ONENAND_FPA_MASK		(0x7f)
+#define ONENAND_FPA_SHIFT		(2)
+#define ONENAND_FSA_MASK		(0x03)
+
+/*
+ * Start Buffer Register F200h (R/W)
+ */
+#define ONENAND_BSA_MASK		(0x03)
+#define ONENAND_BSA_SHIFT		(8)
+#define ONENAND_BSA_BOOTRAM		(0 << 2)
+#define ONENAND_BSA_DATARAM0		(2 << 2)
+#define ONENAND_BSA_DATARAM1		(3 << 2)
+#define ONENAND_BSC_MASK		(0x07)
+
+/*
+ * Command Register F220h (R/W)
+ */
+#define ONENAND_CMD_READ		(0x00)
+#define ONENAND_CMD_READOOB		(0x13)
+#define ONENAND_CMD_PROG		(0x80)
+#define ONENAND_CMD_PROGOOB		(0x1A)
+#define ONENAND_CMD_2X_PROG		(0x7D)
+#define ONENAND_CMD_2X_CACHE_PROG	(0x7F)
+#define ONENAND_CMD_UNLOCK		(0x23)
+#define ONENAND_CMD_LOCK		(0x2A)
+#define ONENAND_CMD_LOCK_TIGHT		(0x2C)
+#define ONENAND_CMD_UNLOCK_ALL		(0x27)
+#define ONENAND_CMD_ERASE		(0x94)
+#define ONENAND_CMD_MULTIBLOCK_ERASE	(0x95)
+#define ONENAND_CMD_ERASE_VERIFY	(0x71)
+#define ONENAND_CMD_RESET		(0xF0)
+#define ONENAND_CMD_READID		(0x90)
+#define FLEXONENAND_CMD_RESET		(0xF3)
+#define FLEXONENAND_CMD_PI_UPDATE	(0x05)
+#define FLEXONENAND_CMD_PI_ACCESS	(0x66)
+#define FLEXONENAND_CMD_RECOVER_LSB	(0x05)
+
+/* NOTE: Those are not *REAL* commands */
+#define ONENAND_CMD_BUFFERRAM		(0x1978)
+#define FLEXONENAND_CMD_READ_PI		(0x1985)
+
+/*
+ * System Configuration 1 Register F221h (R, R/W)
+ */
+#define ONENAND_SYS_CFG1_SYNC_READ	(1 << 15)
+#define ONENAND_SYS_CFG1_BRL_7		(7 << 12)
+#define ONENAND_SYS_CFG1_BRL_6		(6 << 12)
+#define ONENAND_SYS_CFG1_BRL_5		(5 << 12)
+#define ONENAND_SYS_CFG1_BRL_4		(4 << 12)
+#define ONENAND_SYS_CFG1_BRL_3		(3 << 12)
+#define ONENAND_SYS_CFG1_BRL_10		(2 << 12)
+#define ONENAND_SYS_CFG1_BRL_9		(1 << 12)
+#define ONENAND_SYS_CFG1_BRL_8		(0 << 12)
+#define ONENAND_SYS_CFG1_BRL_SHIFT	(12)
+#define ONENAND_SYS_CFG1_BL_32		(4 << 9)
+#define ONENAND_SYS_CFG1_BL_16		(3 << 9)
+#define ONENAND_SYS_CFG1_BL_8		(2 << 9)
+#define ONENAND_SYS_CFG1_BL_4		(1 << 9)
+#define ONENAND_SYS_CFG1_BL_CONT	(0 << 9)
+#define ONENAND_SYS_CFG1_BL_SHIFT	(9)
+#define ONENAND_SYS_CFG1_NO_ECC		(1 << 8)
+#define ONENAND_SYS_CFG1_RDY		(1 << 7)
+#define ONENAND_SYS_CFG1_INT		(1 << 6)
+#define ONENAND_SYS_CFG1_IOBE		(1 << 5)
+#define ONENAND_SYS_CFG1_RDY_CONF	(1 << 4)
+
+/*
+ * Controller Status Register F240h (R)
+ */
+#define ONENAND_CTRL_ONGO		(1 << 15)
+#define ONENAND_CTRL_LOCK		(1 << 14)
+#define ONENAND_CTRL_LOAD		(1 << 13)
+#define ONENAND_CTRL_PROGRAM		(1 << 12)
+#define ONENAND_CTRL_ERASE		(1 << 11)
+#define ONENAND_CTRL_ERROR		(1 << 10)
+#define ONENAND_CTRL_RSTB		(1 << 7)
+
+/*
+ * Interrupt Status Register F241h (R)
+ */
+#define ONENAND_INT_MASTER		(1 << 15)
+#define ONENAND_INT_READ		(1 << 7)
+#define ONENAND_INT_WRITE		(1 << 6)
+#define ONENAND_INT_ERASE		(1 << 5)
+#define ONENAND_INT_RESET		(1 << 4)
+#define ONENAND_INT_CLEAR		(0 << 0)
+
+/*
+ * NAND Flash Write Protection Status Register F24Eh (R)
+ */
+#define ONENAND_WP_US			(1 << 2)
+#define ONENAND_WP_LS			(1 << 1)
+#define ONENAND_WP_LTS			(1 << 0)
+
+/*
+ * ECC Status Reigser FF00h (R)
+ */
+#define ONENAND_ECC_1BIT		(1 << 0)
+#define ONENAND_ECC_1BIT_ALL		(0x5555)
+#define ONENAND_ECC_2BIT		(1 << 1)
+#define ONENAND_ECC_2BIT_ALL		(0xAAAA)
+#define ONENAND_ECC_4BIT_UNCORRECTABLE	(0x1010)
+#define FLEXONENAND_UNCORRECTABLE_ERROR (0x1010)
+
+#endif				/* __ONENAND_REG_H */
diff --git a/qemu/roms/u-boot/include/linux/mtd/partitions.h b/qemu/roms/u-boot/include/linux/mtd/partitions.h
new file mode 100644
index 000000000..d1d9a96d5
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/mtd/partitions.h
@@ -0,0 +1,84 @@
+/*
+ * MTD partitioning layer definitions
+ *
+ * (C) 2000 Nicolas Pitre <nico@cam.org>
+ *
+ * This code is GPL
+ *
+ * $Id: partitions.h,v 1.17 2005/11/07 11:14:55 gleixner Exp $
+ */
+
+#ifndef MTD_PARTITIONS_H
+#define MTD_PARTITIONS_H
+
+#include <linux/types.h>
+
+
+/*
+ * Partition definition structure:
+ *
+ * An array of struct partition is passed along with a MTD object to
+ * add_mtd_partitions() to create them.
+ *
+ * For each partition, these fields are available:
+ * name: string that will be used to label the partition's MTD device.
+ * size: the partition size; if defined as MTDPART_SIZ_FULL, the partition
+ * 	will extend to the end of the master MTD device.
+ * offset: absolute starting position within the master MTD device; if
+ * 	defined as MTDPART_OFS_APPEND, the partition will start where the
+ * 	previous one ended; if MTDPART_OFS_NXTBLK, at the next erase block.
+ * mask_flags: contains flags that have to be masked (removed) from the
+ * 	master MTD flag set for the corresponding MTD partition.
+ * 	For example, to force a read-only partition, simply adding
+ * 	MTD_WRITEABLE to the mask_flags will do the trick.
+ *
+ * Note: writeable partitions require their size and offset be
+ * erasesize aligned (e.g. use MTDPART_OFS_NEXTBLK).
+ */
+
+struct mtd_partition {
+	char *name;			/* identifier string */
+	uint64_t size;			/* partition size */
+	uint64_t offset;		/* offset within the master MTD space */
+	u_int32_t mask_flags;		/* master MTD flags to mask out for this partition */
+	struct nand_ecclayout *ecclayout;	/* out of band layout for this partition (NAND only)*/
+	struct mtd_info **mtdp;		/* pointer to store the MTD object */
+};
+
+#define MTDPART_OFS_NXTBLK	(-2)
+#define MTDPART_OFS_APPEND	(-1)
+#define MTDPART_SIZ_FULL	(0)
+
+
+int add_mtd_partitions(struct mtd_info *, const struct mtd_partition *, int);
+int del_mtd_partitions(struct mtd_info *);
+
+#if 0
+/*
+ * Functions dealing with the various ways of partitioning the space
+ */
+
+struct mtd_part_parser {
+	struct list_head list;
+	struct module *owner;
+	const char *name;
+	int (*parse_fn)(struct mtd_info *, struct mtd_partition **, unsigned long);
+};
+
+extern int register_mtd_parser(struct mtd_part_parser *parser);
+extern int deregister_mtd_parser(struct mtd_part_parser *parser);
+extern int parse_mtd_partitions(struct mtd_info *master, const char **types,
+				struct mtd_partition **pparts, unsigned long origin);
+
+#define put_partition_parser(p) do { module_put((p)->owner); } while(0)
+
+struct device;
+struct device_node;
+
+int __devinit of_mtd_parse_partitions(struct device *dev,
+				      struct mtd_info *mtd,
+				      struct device_node *node,
+				      struct mtd_partition **pparts);
+#endif
+
+#endif
diff --git a/qemu/roms/u-boot/include/linux/mtd/samsung_onenand.h b/qemu/roms/u-boot/include/linux/mtd/samsung_onenand.h
new file mode 100644
index 000000000..246bcf8f3
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/mtd/samsung_onenand.h
@@ -0,0 +1,117 @@
+/*
+ *  Copyright (C) 2005-2009 Samsung Electronics
+ *  Minkyu Kang <mk7.kang@samsung.com>
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __SAMSUNG_ONENAND_H__
+#define __SAMSUNG_ONENAND_H__
+
+/*
+ * OneNAND Controller
+ */
+
+#ifndef __ASSEMBLY__
+struct samsung_onenand {
+	unsigned int	mem_cfg;	/* 0x0000 */
+	unsigned char	res1[0xc];
+	unsigned int	burst_len;	/* 0x0010 */
+	unsigned char	res2[0xc];
+	unsigned int	mem_reset;	/* 0x0020 */
+	unsigned char	res3[0xc];
+	unsigned int	int_err_stat;	/* 0x0030 */
+	unsigned char	res4[0xc];
+	unsigned int	int_err_mask;	/* 0x0040 */
+	unsigned char	res5[0xc];
+	unsigned int	int_err_ack;	/* 0x0050 */
+	unsigned char	res6[0xc];
+	unsigned int	ecc_err_stat;	/* 0x0060 */
+	unsigned char	res7[0xc];
+	unsigned int	manufact_id;	/* 0x0070 */
+	unsigned char	res8[0xc];
+	unsigned int	device_id;	/* 0x0080 */
+	unsigned char	res9[0xc];
+	unsigned int	data_buf_size;	/* 0x0090 */
+	unsigned char	res10[0xc];
+	unsigned int	boot_buf_size;	/* 0x00A0 */
+	unsigned char	res11[0xc];
+	unsigned int	buf_amount;	/* 0x00B0 */
+	unsigned char	res12[0xc];
+	unsigned int	tech;		/* 0x00C0 */
+	unsigned char	res13[0xc];
+	unsigned int	fba;		/* 0x00D0 */
+	unsigned char	res14[0xc];
+	unsigned int	fpa;		/* 0x00E0 */
+	unsigned char	res15[0xc];
+	unsigned int	fsa;		/* 0x00F0 */
+	unsigned char	res16[0x3c];
+	unsigned int	sync_mode;	/* 0x0130 */
+	unsigned char	res17[0xc];
+	unsigned int	trans_spare;	/* 0x0140 */
+	unsigned char	res18[0x3c];
+	unsigned int	err_page_addr;	/* 0x0180 */
+	unsigned char	res19[0x1c];
+	unsigned int	int_pin_en;	/* 0x01A0 */
+	unsigned char	res20[0x1c];
+	unsigned int	acc_clock;	/* 0x01C0 */
+	unsigned char	res21[0x1c];
+	unsigned int	err_blk_addr;	/* 0x01E0 */
+	unsigned char	res22[0xc];
+	unsigned int	flash_ver_id;	/* 0x01F0 */
+	unsigned char	res23[0x6c];
+	unsigned int	watchdog_cnt_low;	/* 0x0260 */
+	unsigned char	res24[0xc];
+	unsigned int	watchdog_cnt_hi;	/* 0x0270 */
+	unsigned char	res25[0xc];
+	unsigned int	sync_write;	/* 0x0280 */
+	unsigned char	res26[0x1c];
+	unsigned int	cold_reset;	/* 0x02A0 */
+	unsigned char	res27[0xc];
+	unsigned int	ddp_device;	/* 0x02B0 */
+	unsigned char	res28[0xc];
+	unsigned int	multi_plane;	/* 0x02C0 */
+	unsigned char	res29[0x1c];
+	unsigned int	trans_mode;	/* 0x02E0 */
+	unsigned char	res30[0x1c];
+	unsigned int	ecc_err_stat2;	/* 0x0300 */
+	unsigned char	res31[0xc];
+	unsigned int	ecc_err_stat3;	/* 0x0310 */
+	unsigned char	res32[0xc];
+	unsigned int	ecc_err_stat4;	/* 0x0320 */
+	unsigned char	res33[0x1c];
+	unsigned int	dev_page_size;	/* 0x0340 */
+	unsigned char	res34[0x4c];
+	unsigned int	int_mon_status;	/* 0x0390 */
+};
+#endif
+
+#define ONENAND_MEM_RESET_HOT	0x3
+#define ONENAND_MEM_RESET_COLD	0x2
+#define ONENAND_MEM_RESET_WARM	0x1
+
+#define INT_ERR_ALL	0x3fff
+#define CACHE_OP_ERR    (1 << 13)
+#define RST_CMP         (1 << 12)
+#define RDY_ACT         (1 << 11)
+#define INT_ACT         (1 << 10)
+#define UNSUP_CMD       (1 << 9)
+#define LOCKED_BLK      (1 << 8)
+#define BLK_RW_CMP      (1 << 7)
+#define ERS_CMP         (1 << 6)
+#define PGM_CMP         (1 << 5)
+#define LOAD_CMP        (1 << 4)
+#define ERS_FAIL        (1 << 3)
+#define PGM_FAIL        (1 << 2)
+#define INT_TO          (1 << 1)
+#define LD_FAIL_ECC_ERR (1 << 0)
+
+#define TSRF		(1 << 0)
+
+/* common initialize function */
+extern void s3c_onenand_init(struct mtd_info *);
+extern int s5pc110_chip_probe(struct mtd_info *);
+extern int s5pc210_chip_probe(struct mtd_info *);
+
+#endif
diff --git a/qemu/roms/u-boot/include/linux/mtd/st_smi.h b/qemu/roms/u-boot/include/linux/mtd/st_smi.h
new file mode 100644
index 000000000..645c6a31e
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/mtd/st_smi.h
@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef ST_SMI_H
+#define ST_SMI_H
+
+/* 0xF800.0000 . 0xFBFF.FFFF	64MB	SMI (Serial Flash Mem) */
+/* 0xFC00.0000 . 0xFC1F.FFFF	2MB	SMI (Serial Flash Reg.) */
+
+#define FLASH_START_ADDRESS	CONFIG_SYS_FLASH_BASE
+#define FLASH_BANK_SIZE		CONFIG_SYS_FLASH_BANK_SIZE
+
+#define SMIBANK0_BASE		(FLASH_START_ADDRESS)
+#define SMIBANK1_BASE		(SMIBANK0_BASE + FLASH_BANK_SIZE)
+#define SMIBANK2_BASE		(SMIBANK1_BASE + FLASH_BANK_SIZE)
+#define SMIBANK3_BASE		(SMIBANK2_BASE + FLASH_BANK_SIZE)
+
+#define BANK0			0
+#define BANK1			1
+#define BANK2			2
+#define BANK3			3
+
+struct smi_regs {
+	u32 smi_cr1;
+	u32 smi_cr2;
+	u32 smi_sr;
+	u32 smi_tr;
+	u32 smi_rr;
+};
+
+/* CONTROL REG 1 */
+#define BANK_EN			0x0000000F	/* enables all banks */
+#define DSEL_TIME		0x00000060	/* Deselect time */
+#define PRESCAL5		0x00000500	/* AHB_CK prescaling value */
+#define PRESCALA		0x00000A00	/* AHB_CK prescaling value */
+#define PRESCAL3		0x00000300	/* AHB_CK prescaling value */
+#define PRESCAL4		0x00000400	/* AHB_CK prescaling value */
+#define SW_MODE			0x10000000	/* enables SW Mode */
+#define WB_MODE			0x20000000	/* Write Burst Mode */
+#define FAST_MODE		0x00008000	/* Fast Mode */
+#define HOLD1			0x00010000
+
+/* CONTROL REG 2 */
+#define RD_STATUS_REG		0x00000400	/* reads status reg */
+#define WE			0x00000800	/* Write Enable */
+#define BANK0_SEL		0x00000000	/* Select Banck0 */
+#define BANK1_SEL		0x00001000	/* Select Banck1 */
+#define BANK2_SEL		0x00002000	/* Select Banck2 */
+#define BANK3_SEL		0x00003000	/* Select Banck3 */
+#define BANKSEL_SHIFT		12
+#define SEND			0x00000080	/* Send data */
+#define TX_LEN_1		0x00000001	/* data length = 1 byte */
+#define TX_LEN_2		0x00000002	/* data length = 2 byte */
+#define TX_LEN_3		0x00000003	/* data length = 3 byte */
+#define TX_LEN_4		0x00000004	/* data length = 4 byte */
+#define RX_LEN_1		0x00000010	/* data length = 1 byte */
+#define RX_LEN_2		0x00000020	/* data length = 2 byte */
+#define RX_LEN_3		0x00000030	/* data length = 3 byte */
+#define RX_LEN_4		0x00000040	/* data length = 4 byte */
+#define TFIE			0x00000100	/* Tx Flag Interrupt Enable */
+#define WCIE			0x00000200	/* WCF Interrupt Enable */
+
+/* STATUS_REG */
+#define INT_WCF_CLR		0xFFFFFDFF	/* clear: WCF clear */
+#define INT_TFF_CLR		0xFFFFFEFF	/* clear: TFF clear */
+#define WIP_BIT			0x00000001	/* WIP Bit of SPI SR */
+#define WEL_BIT			0x00000002	/* WEL Bit of SPI SR */
+#define RSR			0x00000005	/* Read Status regiser */
+#define TFF			0x00000100	/* Transfer Finished FLag */
+#define WCF			0x00000200	/* Transfer Finished FLag */
+#define ERF1			0x00000400	/* Error Flag 1 */
+#define ERF2			0x00000800	/* Error Flag 2 */
+#define WM0			0x00001000	/* WM Bank 0 */
+#define WM1			0x00002000	/* WM Bank 1 */
+#define WM2			0x00004000	/* WM Bank 2 */
+#define WM3			0x00008000	/* WM Bank 3 */
+#define WM_SHIFT		12
+
+/* TR REG */
+#define READ_ID			0x0000009F	/* Read Identification */
+#define BULK_ERASE		0x000000C7	/* BULK erase */
+#define SECTOR_ERASE		0x000000D8	/* SECTOR erase */
+#define WRITE_ENABLE		0x00000006	/* Wenable command to FLASH */
+
+struct flash_dev {
+	u32 density;
+	ulong size;
+	ushort sector_count;
+};
+
+#define SFLASH_PAGE_SIZE	0x100	/* flash page size */
+#define XFER_FINISH_TOUT	15	/* xfer finish timeout(in ms) */
+#define WMODE_TOUT		15	/* write enable timeout(in ms) */
+
+extern void smi_init(void);
+
+#endif
diff --git a/qemu/roms/u-boot/include/linux/mtd/ubi.h b/qemu/roms/u-boot/include/linux/mtd/ubi.h
new file mode 100644
index 000000000..4755770c5
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/mtd/ubi.h
@@ -0,0 +1,174 @@
+/*
+ * Copyright (c) International Business Machines Corp., 2006
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Author: Artem Bityutskiy (Битюцкий �ртём)
+ */
+
+#ifndef __LINUX_UBI_H__
+#define __LINUX_UBI_H__
+
+/* #include <asm/ioctl.h> */
+#include <linux/types.h>
+#include <mtd/ubi-user.h>
+
+/*
+ * enum ubi_open_mode - UBI volume open mode constants.
+ *
+ * UBI_READONLY: read-only mode
+ * UBI_READWRITE: read-write mode
+ * UBI_EXCLUSIVE: exclusive mode
+ */
+enum {
+	UBI_READONLY = 1,
+	UBI_READWRITE,
+	UBI_EXCLUSIVE
+};
+
+/**
+ * struct ubi_volume_info - UBI volume description data structure.
+ * @vol_id: volume ID
+ * @ubi_num: UBI device number this volume belongs to
+ * @size: how many physical eraseblocks are reserved for this volume
+ * @used_bytes: how many bytes of data this volume contains
+ * @used_ebs: how many physical eraseblocks of this volume actually contain any
+ * data
+ * @vol_type: volume type (%UBI_DYNAMIC_VOLUME or %UBI_STATIC_VOLUME)
+ * @corrupted: non-zero if the volume is corrupted (static volumes only)
+ * @upd_marker: non-zero if the volume has update marker set
+ * @alignment: volume alignment
+ * @usable_leb_size: how many bytes are available in logical eraseblocks of
+ * this volume
+ * @name_len: volume name length
+ * @name: volume name
+ * @cdev: UBI volume character device major and minor numbers
+ *
+ * The @corrupted flag is only relevant to static volumes and is always zero
+ * for dynamic ones. This is because UBI does not care about dynamic volume
+ * data protection and only cares about protecting static volume data.
+ *
+ * The @upd_marker flag is set if the volume update operation was interrupted.
+ * Before touching the volume data during the update operation, UBI first sets
+ * the update marker flag for this volume. If the volume update operation was
+ * further interrupted, the update marker indicates this. If the update marker
+ * is set, the contents of the volume is certainly damaged and a new volume
+ * update operation has to be started.
+ *
+ * To put it differently, @corrupted and @upd_marker fields have different
+ * semantics:
+ *     o the @corrupted flag means that this static volume is corrupted for some
+ *       reasons, but not because an interrupted volume update
+ *     o the @upd_marker field means that the volume is damaged because of an
+ *       interrupted update operation.
+ *
+ * I.e., the @corrupted flag is never set if the @upd_marker flag is set.
+ *
+ * The @used_bytes and @used_ebs fields are only really needed for static
+ * volumes and contain the number of bytes stored in this static volume and how
+ * many eraseblock this data occupies. In case of dynamic volumes, the
+ * @used_bytes field is equivalent to @size*@usable_leb_size, and the @used_ebs
+ * field is equivalent to @size.
+ *
+ * In general, logical eraseblock size is a property of the UBI device, not
+ * of the UBI volume. Indeed, the logical eraseblock size depends on the
+ * physical eraseblock size and on how much bytes UBI headers consume. But
+ * because of the volume alignment (@alignment), the usable size of logical
+ * eraseblocks if a volume may be less. The following equation is true:
+ * 	@usable_leb_size = LEB size - (LEB size mod @alignment),
+ * where LEB size is the logical eraseblock size defined by the UBI device.
+ *
+ * The alignment is multiple to the minimal flash input/output unit size or %1
+ * if all the available space is used.
+ *
+ * To put this differently, alignment may be considered is a way to change
+ * volume logical eraseblock sizes.
+ */
+struct ubi_volume_info {
+	int ubi_num;
+	int vol_id;
+	int size;
+	long long used_bytes;
+	int used_ebs;
+	int vol_type;
+	int corrupted;
+	int upd_marker;
+	int alignment;
+	int usable_leb_size;
+	int name_len;
+	const char *name;
+	dev_t cdev;
+};
+
+/**
+ * struct ubi_device_info - UBI device description data structure.
+ * @ubi_num: ubi device number
+ * @leb_size: logical eraseblock size on this UBI device
+ * @min_io_size: minimal I/O unit size
+ * @ro_mode: if this device is in read-only mode
+ * @cdev: UBI character device major and minor numbers
+ *
+ * Note, @leb_size is the logical eraseblock size offered by the UBI device.
+ * Volumes of this UBI device may have smaller logical eraseblock size if their
+ * alignment is not equivalent to %1.
+ */
+struct ubi_device_info {
+	int ubi_num;
+	int leb_size;
+	int min_io_size;
+	int ro_mode;
+	dev_t cdev;
+};
+
+/* UBI descriptor given to users when they open UBI volumes */
+struct ubi_volume_desc;
+
+int ubi_get_device_info(int ubi_num, struct ubi_device_info *di);
+void ubi_get_volume_info(struct ubi_volume_desc *desc,
+			 struct ubi_volume_info *vi);
+struct ubi_volume_desc *ubi_open_volume(int ubi_num, int vol_id, int mode);
+struct ubi_volume_desc *ubi_open_volume_nm(int ubi_num, const char *name,
+					   int mode);
+void ubi_close_volume(struct ubi_volume_desc *desc);
+int ubi_leb_read(struct ubi_volume_desc *desc, int lnum, char *buf, int offset,
+		 int len, int check);
+int ubi_leb_write(struct ubi_volume_desc *desc, int lnum, const void *buf,
+		  int offset, int len, int dtype);
+int ubi_leb_change(struct ubi_volume_desc *desc, int lnum, const void *buf,
+		   int len, int dtype);
+int ubi_leb_erase(struct ubi_volume_desc *desc, int lnum);
+int ubi_leb_unmap(struct ubi_volume_desc *desc, int lnum);
+int ubi_leb_map(struct ubi_volume_desc *desc, int lnum, int dtype);
+int ubi_is_mapped(struct ubi_volume_desc *desc, int lnum);
+
+/*
+ * This function is the same as the 'ubi_leb_read()' function, but it does not
+ * provide the checking capability.
+ */
+static inline int ubi_read(struct ubi_volume_desc *desc, int lnum, char *buf,
+			   int offset, int len)
+{
+	return ubi_leb_read(desc, lnum, buf, offset, len, 0);
+}
+
+/*
+ * This function is the same as the 'ubi_leb_write()' functions, but it does
+ * not have the data type argument.
+ */
+static inline int ubi_write(struct ubi_volume_desc *desc, int lnum,
+			    const void *buf, int offset, int len)
+{
+	return ubi_leb_write(desc, lnum, buf, offset, len, UBI_UNKNOWN);
+}
+
+/*
+ * This function is the same as the 'ubi_leb_change()' functions, but it does
+ * not have the data type argument.
+ */
+static inline int ubi_change(struct ubi_volume_desc *desc, int lnum,
+				    const void *buf, int len)
+{
+	return ubi_leb_change(desc, lnum, buf, len, UBI_UNKNOWN);
+}
+
+#endif /* !__LINUX_UBI_H__ */
diff --git a/qemu/roms/u-boot/include/linux/netdevice.h b/qemu/roms/u-boot/include/linux/netdevice.h
new file mode 100644
index 000000000..12e8cc19b
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/netdevice.h
@@ -0,0 +1,62 @@
+/*
+ * INET		An implementation of the TCP/IP protocol suite for the LINUX
+ *		operating system.  INET is implemented using the  BSD Socket
+ *		interface as the means of communication with the user level.
+ *
+ *		Definitions for the Interfaces handler.
+ *
+ * Version:	@(#)dev.h	1.0.10	08/12/93
+ *
+ * Authors:	Ross Biro
+ *		Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG>
+ *		Corey Minyard <wf-rch!minyard@relay.EU.net>
+ *		Donald J. Becker, <becker@cesdis.gsfc.nasa.gov>
+ *		Alan Cox, <Alan.Cox@linux.org>
+ *		Bjorn Ekwall. <bj0rn@blox.se>
+ *              Pekka Riikonen <priikone@poseidon.pspt.fi>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ *		Moved to /usr/include/linux for NET3
+ */
+#ifndef _LINUX_NETDEVICE_H
+#define _LINUX_NETDEVICE_H
+
+/*
+ *	Network device statistics. Akin to the 2.0 ether stats but
+ *	with byte counters.
+ */
+
+struct net_device_stats {
+	unsigned long	rx_packets;		/* total packets received	*/
+	unsigned long	tx_packets;		/* total packets transmitted	*/
+	unsigned long	rx_bytes;		/* total bytes received		*/
+	unsigned long	tx_bytes;		/* total bytes transmitted	*/
+	unsigned long	rx_errors;		/* bad packets received		*/
+	unsigned long	tx_errors;		/* packet transmit problems	*/
+	unsigned long	rx_dropped;		/* no space in linux buffers	*/
+	unsigned long	tx_dropped;		/* no space available in linux	*/
+	unsigned long	multicast;		/* multicast packets received	*/
+	unsigned long	collisions;
+
+	/* detailed rx_errors: */
+	unsigned long	rx_length_errors;
+	unsigned long	rx_over_errors;		/* receiver ring buff overflow	*/
+	unsigned long	rx_crc_errors;		/* recved pkt with crc error	*/
+	unsigned long	rx_frame_errors;	/* recv'd frame alignment error	*/
+	unsigned long	rx_fifo_errors;		/* recv'r fifo overrun		*/
+	unsigned long	rx_missed_errors;	/* receiver missed packet	*/
+
+	/* detailed tx_errors */
+	unsigned long	tx_aborted_errors;
+	unsigned long	tx_carrier_errors;
+	unsigned long	tx_fifo_errors;
+	unsigned long	tx_heartbeat_errors;
+	unsigned long	tx_window_errors;
+
+	/* for cslip etc */
+	unsigned long	rx_compressed;
+	unsigned long	tx_compressed;
+};
+
+#endif	/* _LINUX_NETDEVICE_H */
diff --git a/qemu/roms/u-boot/include/linux/poison.h b/qemu/roms/u-boot/include/linux/poison.h
new file mode 100644
index 000000000..b3d873b45
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/poison.h
@@ -0,0 +1,11 @@
+#ifndef _LINUX_POISON_H
+#define _LINUX_POISON_H
+
+/********** include/linux/list.h **********/
+/*
+ * used to verify that nobody uses non-initialized list entries.
+ */
+#define LIST_POISON1  ((void *) 0x0)
+#define LIST_POISON2  ((void *) 0x0)
+
+#endif
diff --git a/qemu/roms/u-boot/include/linux/posix_types.h b/qemu/roms/u-boot/include/linux/posix_types.h
new file mode 100644
index 000000000..bd37e1faf
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/posix_types.h
@@ -0,0 +1,48 @@
+#ifndef _LINUX_POSIX_TYPES_H
+#define _LINUX_POSIX_TYPES_H
+
+#include <linux/stddef.h>
+
+/*
+ * This allows for 1024 file descriptors: if NR_OPEN is ever grown
+ * beyond that you'll have to change this too. But 1024 fd's seem to be
+ * enough even for such "real" unices like OSF/1, so hopefully this is
+ * one limit that doesn't have to be changed [again].
+ *
+ * Note that POSIX wants the FD_CLEAR(fd,fdsetp) defines to be in
+ * <sys/time.h> (and thus <linux/time.h>) - but this is a more logical
+ * place for them. Solved by having dummy defines in <sys/time.h>.
+ */
+
+/*
+ * Those macros may have been defined in <gnu/types.h>. But we always
+ * use the ones here.
+ */
+#undef __NFDBITS
+#define __NFDBITS	(8 * sizeof(unsigned long))
+
+#undef __FD_SETSIZE
+#define __FD_SETSIZE	1024
+
+#undef __FDSET_LONGS
+#define __FDSET_LONGS	(__FD_SETSIZE/__NFDBITS)
+
+#undef __FDELT
+#define	__FDELT(d)	((d) / __NFDBITS)
+
+#undef __FDMASK
+#define	__FDMASK(d)	(1UL << ((d) % __NFDBITS))
+
+typedef struct {
+	unsigned long fds_bits [__FDSET_LONGS];
+} __kernel_fd_set;
+
+/* Type of a signal handler.  */
+typedef void (*__kernel_sighandler_t)(int);
+
+/* Type of a SYSV IPC key.  */
+typedef int __kernel_key_t;
+
+#include <asm/posix_types.h>
+
+#endif /* _LINUX_POSIX_TYPES_H */
diff --git a/qemu/roms/u-boot/include/linux/rbtree.h b/qemu/roms/u-boot/include/linux/rbtree.h
new file mode 100644
index 000000000..ad892d1cb
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/rbtree.h
@@ -0,0 +1,148 @@
+/*
+  Red Black Trees
+  (C) 1999  Andrea Arcangeli <andrea@suse.de>
+
+ * SPDX-License-Identifier:	GPL-2.0+
+
+  linux/include/linux/rbtree.h
+
+  To use rbtrees you'll have to implement your own insert and search cores.
+  This will avoid us to use callbacks and to drop drammatically performances.
+  I know it's not the cleaner way,  but in C (not in C++) to get
+  performances and genericity...
+
+  Some example of insert and search follows here. The search is a plain
+  normal search over an ordered tree. The insert instead must be implemented
+  int two steps: as first thing the code must insert the element in
+  order as a red leaf in the tree, then the support library function
+  rb_insert_color() must be called. Such function will do the
+  not trivial work to rebalance the rbtree if necessary.
+
+-----------------------------------------------------------------------
+static inline struct page * rb_search_page_cache(struct inode * inode,
+						 unsigned long offset)
+{
+	struct rb_node * n = inode->i_rb_page_cache.rb_node;
+	struct page * page;
+
+	while (n)
+	{
+		page = rb_entry(n, struct page, rb_page_cache);
+
+		if (offset < page->offset)
+			n = n->rb_left;
+		else if (offset > page->offset)
+			n = n->rb_right;
+		else
+			return page;
+	}
+	return NULL;
+}
+
+static inline struct page * __rb_insert_page_cache(struct inode * inode,
+						   unsigned long offset,
+						   struct rb_node * node)
+{
+	struct rb_node ** p = &inode->i_rb_page_cache.rb_node;
+	struct rb_node * parent = NULL;
+	struct page * page;
+
+	while (*p)
+	{
+		parent = *p;
+		page = rb_entry(parent, struct page, rb_page_cache);
+
+		if (offset < page->offset)
+			p = &(*p)->rb_left;
+		else if (offset > page->offset)
+			p = &(*p)->rb_right;
+		else
+			return page;
+	}
+
+	rb_link_node(node, parent, p);
+
+	return NULL;
+}
+
+static inline struct page * rb_insert_page_cache(struct inode * inode,
+						 unsigned long offset,
+						 struct rb_node * node)
+{
+	struct page * ret;
+	if ((ret = __rb_insert_page_cache(inode, offset, node)))
+		goto out;
+	rb_insert_color(node, &inode->i_rb_page_cache);
+ out:
+	return ret;
+}
+-----------------------------------------------------------------------
+*/
+
+#ifndef	_LINUX_RBTREE_H
+#define	_LINUX_RBTREE_H
+
+#include <linux/stddef.h>
+
+struct rb_node
+{
+	unsigned long  rb_parent_color;
+#define	RB_RED		0
+#define	RB_BLACK	1
+	struct rb_node *rb_right;
+	struct rb_node *rb_left;
+} __attribute__((aligned(sizeof(long))));
+    /* The alignment might seem pointless, but allegedly CRIS needs it */
+
+struct rb_root
+{
+	struct rb_node *rb_node;
+};
+
+
+#define rb_parent(r)   ((struct rb_node *)((r)->rb_parent_color & ~3))
+#define rb_color(r)   ((r)->rb_parent_color & 1)
+#define rb_is_red(r)   (!rb_color(r))
+#define rb_is_black(r) rb_color(r)
+#define rb_set_red(r)  do { (r)->rb_parent_color &= ~1; } while (0)
+#define rb_set_black(r)  do { (r)->rb_parent_color |= 1; } while (0)
+
+static inline void rb_set_parent(struct rb_node *rb, struct rb_node *p)
+{
+	rb->rb_parent_color = (rb->rb_parent_color & 3) | (unsigned long)p;
+}
+static inline void rb_set_color(struct rb_node *rb, int color)
+{
+	rb->rb_parent_color = (rb->rb_parent_color & ~1) | color;
+}
+
+#define RB_ROOT	(struct rb_root) { NULL, }
+#define	rb_entry(ptr, type, member) container_of(ptr, type, member)
+
+#define RB_EMPTY_ROOT(root)	((root)->rb_node == NULL)
+#define RB_EMPTY_NODE(node)	(rb_parent(node) == node)
+#define RB_CLEAR_NODE(node)	(rb_set_parent(node, node))
+
+extern void rb_insert_color(struct rb_node *, struct rb_root *);
+extern void rb_erase(struct rb_node *, struct rb_root *);
+
+/* Find logical next and previous nodes in a tree */
+extern struct rb_node *rb_next(struct rb_node *);
+extern struct rb_node *rb_prev(struct rb_node *);
+extern struct rb_node *rb_first(struct rb_root *);
+extern struct rb_node *rb_last(struct rb_root *);
+
+/* Fast replacement of a single node without remove/rebalance/add/rebalance */
+extern void rb_replace_node(struct rb_node *victim, struct rb_node *new,
+			    struct rb_root *root);
+
+static inline void rb_link_node(struct rb_node * node, struct rb_node * parent,
+				struct rb_node ** rb_link)
+{
+	node->rb_parent_color = (unsigned long )parent;
+	node->rb_left = node->rb_right = NULL;
+
+	*rb_link = node;
+}
+
+#endif	/* _LINUX_RBTREE_H */
diff --git a/qemu/roms/u-boot/include/linux/screen_info.h b/qemu/roms/u-boot/include/linux/screen_info.h
new file mode 100644
index 000000000..899fbb487
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/screen_info.h
@@ -0,0 +1,84 @@
+#ifndef _SCREEN_INFO_H
+#define _SCREEN_INFO_H
+
+#include <linux/types.h>
+
+/*
+ * These are set up by the setup-routine at boot-time:
+ */
+
+struct screen_info {
+	__u8  orig_x;		/* 0x00 */
+	__u8  orig_y;		/* 0x01 */
+	__u16 ext_mem_k;	/* 0x02 */
+	__u16 orig_video_page;	/* 0x04 */
+	__u8  orig_video_mode;	/* 0x06 */
+	__u8  orig_video_cols;	/* 0x07 */
+	__u8  flags;		/* 0x08 */
+	__u8  unused2;		/* 0x09 */
+	__u16 orig_video_ega_bx;/* 0x0a */
+	__u16 unused3;		/* 0x0c */
+	__u8  orig_video_lines;	/* 0x0e */
+	__u8  orig_video_isVGA;	/* 0x0f */
+	__u16 orig_video_points;/* 0x10 */
+
+	/* VESA graphic mode -- linear frame buffer */
+	__u16 lfb_width;	/* 0x12 */
+	__u16 lfb_height;	/* 0x14 */
+	__u16 lfb_depth;	/* 0x16 */
+	__u32 lfb_base;		/* 0x18 */
+	__u32 lfb_size;		/* 0x1c */
+	__u16 cl_magic, cl_offset; /* 0x20 */
+	__u16 lfb_linelength;	/* 0x24 */
+	__u8  red_size;		/* 0x26 */
+	__u8  red_pos;		/* 0x27 */
+	__u8  green_size;	/* 0x28 */
+	__u8  green_pos;	/* 0x29 */
+	__u8  blue_size;	/* 0x2a */
+	__u8  blue_pos;		/* 0x2b */
+	__u8  rsvd_size;	/* 0x2c */
+	__u8  rsvd_pos;		/* 0x2d */
+	__u16 vesapm_seg;	/* 0x2e */
+	__u16 vesapm_off;	/* 0x30 */
+	__u16 pages;		/* 0x32 */
+	__u16 vesa_attributes;	/* 0x34 */
+	__u32 capabilities;     /* 0x36 */
+	__u8  _reserved[6];	/* 0x3a */
+} __attribute__((packed));
+
+#define VIDEO_TYPE_MDA		0x10	/* Monochrome Text Display	*/
+#define VIDEO_TYPE_CGA		0x11	/* CGA Display 			*/
+#define VIDEO_TYPE_EGAM		0x20	/* EGA/VGA in Monochrome Mode	*/
+#define VIDEO_TYPE_EGAC		0x21	/* EGA in Color Mode		*/
+#define VIDEO_TYPE_VGAC		0x22	/* VGA+ in Color Mode		*/
+#define VIDEO_TYPE_VLFB		0x23	/* VESA VGA in graphic mode	*/
+
+#define VIDEO_TYPE_PICA_S3	0x30	/* ACER PICA-61 local S3 video	*/
+#define VIDEO_TYPE_MIPS_G364	0x31    /* MIPS Magnum 4000 G364 video  */
+#define VIDEO_TYPE_SGI          0x33    /* Various SGI graphics hardware */
+
+#define VIDEO_TYPE_TGAC		0x40	/* DEC TGA */
+
+#define VIDEO_TYPE_SUN          0x50    /* Sun frame buffer. */
+#define VIDEO_TYPE_SUNPCI       0x51    /* Sun PCI based frame buffer. */
+
+#define VIDEO_TYPE_PMAC		0x60	/* PowerMacintosh frame buffer. */
+
+#define VIDEO_TYPE_EFI		0x70	/* EFI graphic mode		*/
+
+#define VIDEO_FLAGS_NOCURSOR	(1 << 0) /* The video mode has no cursor set */
+
+#ifdef __KERNEL__
+extern struct screen_info screen_info;
+
+#define ORIG_X			(screen_info.orig_x)
+#define ORIG_Y			(screen_info.orig_y)
+#define ORIG_VIDEO_MODE		(screen_info.orig_video_mode)
+#define ORIG_VIDEO_COLS 	(screen_info.orig_video_cols)
+#define ORIG_VIDEO_EGA_BX	(screen_info.orig_video_ega_bx)
+#define ORIG_VIDEO_LINES	(screen_info.orig_video_lines)
+#define ORIG_VIDEO_ISVGA	(screen_info.orig_video_isVGA)
+#define ORIG_VIDEO_POINTS       (screen_info.orig_video_points)
+#endif /* __KERNEL__ */
+
+#endif /* _SCREEN_INFO_H */
diff --git a/qemu/roms/u-boot/include/linux/sizes.h b/qemu/roms/u-boot/include/linux/sizes.h
new file mode 100644
index 000000000..ce3e8150c
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/sizes.h
@@ -0,0 +1,47 @@
+/*
+ * include/linux/sizes.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __LINUX_SIZES_H__
+#define __LINUX_SIZES_H__
+
+#define SZ_1				0x00000001
+#define SZ_2				0x00000002
+#define SZ_4				0x00000004
+#define SZ_8				0x00000008
+#define SZ_16				0x00000010
+#define SZ_32				0x00000020
+#define SZ_64				0x00000040
+#define SZ_128				0x00000080
+#define SZ_256				0x00000100
+#define SZ_512				0x00000200
+
+#define SZ_1K				0x00000400
+#define SZ_2K				0x00000800
+#define SZ_4K				0x00001000
+#define SZ_8K				0x00002000
+#define SZ_16K				0x00004000
+#define SZ_32K				0x00008000
+#define SZ_64K				0x00010000
+#define SZ_128K				0x00020000
+#define SZ_256K				0x00040000
+#define SZ_512K				0x00080000
+
+#define SZ_1M				0x00100000
+#define SZ_2M				0x00200000
+#define SZ_4M				0x00400000
+#define SZ_8M				0x00800000
+#define SZ_16M				0x01000000
+#define SZ_32M				0x02000000
+#define SZ_64M				0x04000000
+#define SZ_128M				0x08000000
+#define SZ_256M				0x10000000
+#define SZ_512M				0x20000000
+
+#define SZ_1G				0x40000000
+#define SZ_2G				0x80000000
+
+#endif /* __LINUX_SIZES_H__ */
diff --git a/qemu/roms/u-boot/include/linux/stat.h b/qemu/roms/u-boot/include/linux/stat.h
new file mode 100644
index 000000000..cef636959
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/stat.h
@@ -0,0 +1,158 @@
+#ifndef _LINUX_STAT_H
+#define _LINUX_STAT_H
+
+#include <linux/types.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define S_IFMT	00170000	/* type of file */
+#define S_IFSOCK 0140000	/* named socket */
+#define S_IFLNK	 0120000	/* symbolic link */
+#define S_IFREG  0100000	/* regular */
+#define S_IFBLK  0060000	/* block special */
+#define S_IFDIR  0040000	/* directory */
+#define S_IFCHR  0020000	/* character special */
+#define S_IFIFO  0010000	/* fifo */
+#define S_ISUID  0004000	/* set user id on execution */
+#define S_ISGID  0002000	/* set group id on execution */
+#define S_ISVTX  0001000	/* save swapped text even after use */
+
+#define S_ISLNK(m)	(((m) & S_IFMT) == S_IFLNK)
+#define S_ISREG(m)	(((m) & S_IFMT) == S_IFREG)
+#define S_ISDIR(m)	(((m) & S_IFMT) == S_IFDIR)
+#define S_ISCHR(m)	(((m) & S_IFMT) == S_IFCHR)
+#define S_ISBLK(m)	(((m) & S_IFMT) == S_IFBLK)
+#define S_ISFIFO(m)	(((m) & S_IFMT) == S_IFIFO)
+#define S_ISSOCK(m)	(((m) & S_IFMT) == S_IFSOCK)
+
+#define S_IRWXU 00700		/* rwx for owner */
+#define S_IRUSR 00400		/* read permission for owner */
+#define S_IWUSR 00200		/* write permission for owner */
+#define S_IXUSR 00100		/* execute/search permission for owner */
+
+#define S_IRWXG 00070		/* rwx for group */
+#define S_IRGRP 00040		/* read permission for group */
+#define S_IWGRP 00020		/* write permission for group */
+#define S_IXGRP 00010		/* execute/search permission for group */
+
+#define S_IRWXO 00007		/* rwx for other */
+#define S_IROTH 00004		/* read permission for other */
+#define S_IWOTH 00002		/* read permission for other */
+#define S_IXOTH 00001		/* execute/search permission for other */
+
+#ifdef	__PPC__
+
+struct stat {
+	dev_t		st_dev;		/* file system id */
+	ino_t		st_ino;		/* file id */
+	mode_t		st_mode;	/* ownership/protection */
+	nlink_t		st_nlink;	/* number of links */
+	uid_t		st_uid;		/* user id */
+	gid_t		st_gid;		/* group id */
+	dev_t		st_rdev;
+	off_t		st_size;	/* file size in # of bytes */
+	unsigned long	st_blksize;	/* block size */
+	unsigned long	st_blocks;	/* file size in # of blocks */
+	unsigned long	st_atime;	/* time file was last accessed */
+	unsigned long	__unused1;
+	unsigned long	st_mtime;	/* time file was last modified */
+	unsigned long	__unused2;
+	unsigned long	st_ctime;	/* time file status was last changed */
+	unsigned long	__unused3;
+	unsigned long	__unused4;
+	unsigned long	__unused5;
+};
+
+#endif	/* __PPC__ */
+
+#if defined (__ARM__) || defined (__I386__) || defined (__M68K__) || defined (__bfin__) ||\
+	defined (__microblaze__) || defined (__nios2__)
+
+struct stat {
+	unsigned short st_dev;
+	unsigned short __pad1;
+	unsigned long st_ino;
+	unsigned short st_mode;
+	unsigned short st_nlink;
+	unsigned short st_uid;
+	unsigned short st_gid;
+	unsigned short st_rdev;
+	unsigned short __pad2;
+	unsigned long  st_size;
+	unsigned long  st_blksize;
+	unsigned long  st_blocks;
+	unsigned long  st_atime;
+	unsigned long  __unused1;
+	unsigned long  st_mtime;
+	unsigned long  __unused2;
+	unsigned long  st_ctime;
+	unsigned long  __unused3;
+	unsigned long  __unused4;
+	unsigned long  __unused5;
+};
+
+#endif	/* __ARM__ */
+
+#if defined (__MIPS__)
+
+struct stat {
+	dev_t		st_dev;
+	long		st_pad1[3];
+	ino_t		st_ino;
+	mode_t		st_mode;
+	nlink_t		st_nlink;
+	uid_t		st_uid;
+	gid_t		st_gid;
+	dev_t		st_rdev;
+	long		st_pad2[2];
+	off_t		st_size;
+	long		st_pad3;
+	/*
+	 * Actually this should be timestruc_t st_atime, st_mtime and st_ctime
+	 * but we don't have it under Linux.
+	 */
+	time_t		st_atime;
+	long		reserved0;
+	time_t		st_mtime;
+	long		reserved1;
+	time_t		st_ctime;
+	long		reserved2;
+	long		st_blksize;
+	long		st_blocks;
+	long		st_pad4[14];
+};
+
+#endif	/* __MIPS__ */
+
+#if defined(__AVR32__) || defined(__SH__)
+
+struct stat {
+	unsigned long st_dev;
+	unsigned long st_ino;
+	unsigned short st_mode;
+	unsigned short st_nlink;
+	unsigned short st_uid;
+	unsigned short st_gid;
+	unsigned long  st_rdev;
+	unsigned long  st_size;
+	unsigned long  st_blksize;
+	unsigned long  st_blocks;
+	unsigned long  st_atime;
+	unsigned long  st_atime_nsec;
+	unsigned long  st_mtime;
+	unsigned long  st_mtime_nsec;
+	unsigned long  st_ctime;
+	unsigned long  st_ctime_nsec;
+	unsigned long  __unused4;
+	unsigned long  __unused5;
+};
+
+#endif /* __AVR32__ || __SH__ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/qemu/roms/u-boot/include/linux/stddef.h b/qemu/roms/u-boot/include/linux/stddef.h
new file mode 100644
index 000000000..c540f6100
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/stddef.h
@@ -0,0 +1,20 @@
+#ifndef _LINUX_STDDEF_H
+#define _LINUX_STDDEF_H
+
+#undef NULL
+#if defined(__cplusplus)
+#define NULL 0
+#else
+#define NULL ((void *)0)
+#endif
+
+#ifndef _SIZE_T
+#include <linux/types.h>
+#endif
+
+#ifndef __CHECKER__
+#undef offsetof
+#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
+#endif
+
+#endif
diff --git a/qemu/roms/u-boot/include/linux/string.h b/qemu/roms/u-boot/include/linux/string.h
new file mode 100644
index 000000000..8e4485571
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/string.h
@@ -0,0 +1,96 @@
+#ifndef _LINUX_STRING_H_
+#define _LINUX_STRING_H_
+
+#include <linux/types.h>	/* for size_t */
+#include <linux/stddef.h>	/* for NULL */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern char * ___strtok;
+extern char * strpbrk(const char *,const char *);
+extern char * strtok(char *,const char *);
+extern char * strsep(char **,const char *);
+extern __kernel_size_t strspn(const char *,const char *);
+
+
+/*
+ * Include machine specific inline routines
+ */
+#include <asm/string.h>
+
+#ifndef __HAVE_ARCH_STRCPY
+extern char * strcpy(char *,const char *);
+#endif
+#ifndef __HAVE_ARCH_STRNCPY
+extern char * strncpy(char *,const char *, __kernel_size_t);
+#endif
+#ifndef __HAVE_ARCH_STRCAT
+extern char * strcat(char *, const char *);
+#endif
+#ifndef __HAVE_ARCH_STRNCAT
+extern char * strncat(char *, const char *, __kernel_size_t);
+#endif
+#ifndef __HAVE_ARCH_STRCMP
+extern int strcmp(const char *,const char *);
+#endif
+#ifndef __HAVE_ARCH_STRNCMP
+extern int strncmp(const char *,const char *,__kernel_size_t);
+#endif
+#ifndef __HAVE_ARCH_STRCASECMP
+int strcasecmp(const char *s1, const char *s2);
+#endif
+#ifndef __HAVE_ARCH_STRNCASECMP
+extern int strncasecmp(const char *s1, const char *s2, __kernel_size_t len);
+#endif
+#ifndef __HAVE_ARCH_STRCHR
+extern char * strchr(const char *,int);
+#endif
+#ifndef __HAVE_ARCH_STRRCHR
+extern char * strrchr(const char *,int);
+#endif
+#include <linux/linux_string.h>
+#ifndef __HAVE_ARCH_STRSTR
+extern char * strstr(const char *,const char *);
+#endif
+#ifndef __HAVE_ARCH_STRLEN
+extern __kernel_size_t strlen(const char *);
+#endif
+#ifndef __HAVE_ARCH_STRNLEN
+extern __kernel_size_t strnlen(const char *,__kernel_size_t);
+#endif
+#ifndef __HAVE_ARCH_STRDUP
+extern char * strdup(const char *);
+#endif
+#ifndef __HAVE_ARCH_STRSWAB
+extern char * strswab(const char *);
+#endif
+
+#ifndef __HAVE_ARCH_MEMSET
+extern void * memset(void *,int,__kernel_size_t);
+#endif
+#ifndef __HAVE_ARCH_MEMCPY
+extern void * memcpy(void *,const void *,__kernel_size_t);
+#endif
+#ifndef __HAVE_ARCH_MEMMOVE
+extern void * memmove(void *,const void *,__kernel_size_t);
+#endif
+#ifndef __HAVE_ARCH_MEMSCAN
+extern void * memscan(void *,int,__kernel_size_t);
+#endif
+#ifndef __HAVE_ARCH_MEMCMP
+extern int memcmp(const void *,const void *,__kernel_size_t);
+#endif
+#ifndef __HAVE_ARCH_MEMCHR
+extern void * memchr(const void *,int,__kernel_size_t);
+#endif
+#ifndef __HAVE_ARCH_MEMCHR_INV
+void *memchr_inv(const void *, int, size_t);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _LINUX_STRING_H_ */
diff --git a/qemu/roms/u-boot/include/linux/stringify.h b/qemu/roms/u-boot/include/linux/stringify.h
new file mode 100644
index 000000000..841cec8ed
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/stringify.h
@@ -0,0 +1,12 @@
+#ifndef __LINUX_STRINGIFY_H
+#define __LINUX_STRINGIFY_H
+
+/* Indirect stringification.  Doing two levels allows the parameter to be a
+ * macro itself.  For example, compile with -DFOO=bar, __stringify(FOO)
+ * converts to "bar".
+ */
+
+#define __stringify_1(x...)	#x
+#define __stringify(x...)	__stringify_1(x)
+
+#endif	/* !__LINUX_STRINGIFY_H */
diff --git a/qemu/roms/u-boot/include/linux/time.h b/qemu/roms/u-boot/include/linux/time.h
new file mode 100644
index 000000000..bf12b99d3
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/time.h
@@ -0,0 +1,158 @@
+#ifndef _LINUX_TIME_H
+#define _LINUX_TIME_H
+
+#include <linux/types.h>
+
+#define _DEFUN(a,b,c) a(c)
+#define _CONST const
+#define _AND ,
+
+#define _REENT_ONLY
+
+#define SECSPERMIN	60L
+#define MINSPERHOUR	60L
+#define HOURSPERDAY	24L
+#define SECSPERHOUR	(SECSPERMIN * MINSPERHOUR)
+#define SECSPERDAY	(SECSPERHOUR * HOURSPERDAY)
+#define DAYSPERWEEK	7
+#define MONSPERYEAR	12
+
+#define YEAR_BASE	1900
+#define EPOCH_YEAR      1970
+#define EPOCH_WDAY      4
+
+#define isleap(y) ((((y) % 4) == 0 && ((y) % 100) != 0) || ((y) % 400) == 0)
+
+
+/* Used by other time functions.  */
+struct tm {
+    int tm_sec;                   /* Seconds.     [0-60] (1 leap second) */
+    int tm_min;                   /* Minutes.     [0-59] */
+    int tm_hour;                  /* Hours.       [0-23] */
+    int tm_mday;                  /* Day.         [1-31] */
+    int tm_mon;                   /* Month.       [0-11] */
+    int tm_year;                  /* Year - 1900.  */
+    int tm_wday;                  /* Day of week. [0-6] */
+    int tm_yday;                  /* Days in year.[0-365] */
+    int tm_isdst;                 /* DST.         [-1/0/1]*/
+
+# ifdef __USE_BSD
+    long int tm_gmtoff;           /* Seconds east of UTC.  */
+    __const char *tm_zone;        /* Timezone abbreviation.  */
+# else
+    long int __tm_gmtoff;         /* Seconds east of UTC.  */
+    __const char *__tm_zone;      /* Timezone abbreviation.  */
+# endif
+};
+
+static inline char *
+_DEFUN (asctime_r, (tim_p, result),
+	_CONST struct tm *tim_p _AND
+	char *result)
+{
+    static _CONST char day_name[7][3] = {
+	"Sun", "Mon", "Tue", "Wed", "Thu", "Fri", "Sat"
+    };
+    static _CONST char mon_name[12][3] = {
+	"Jan", "Feb", "Mar", "Apr", "May", "Jun",
+	"Jul", "Aug", "Sep", "Oct", "Nov", "Dec"
+    };
+
+    sprintf (result, "%.3s %.3s %.2d %.2d:%.2d:%.2d %d\n",
+	    day_name[tim_p->tm_wday],
+	    mon_name[tim_p->tm_mon],
+	    tim_p->tm_mday, tim_p->tm_hour, tim_p->tm_min,
+	    tim_p->tm_sec, 1900 + tim_p->tm_year);
+    return result;
+}
+
+static inline struct tm *
+_DEFUN (localtime_r, (tim_p, res),
+	_CONST time_t * tim_p _AND
+	struct tm *res)
+{
+    static _CONST int mon_lengths[2][MONSPERYEAR] = {
+      {31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31},
+      {31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}
+    } ;
+
+    static _CONST int year_lengths[2] = {
+      365,
+      366
+    } ;
+
+    long days, rem;
+    int y;
+    int yleap;
+    _CONST int *ip;
+
+    days = ((long) *tim_p) / SECSPERDAY;
+    rem = ((long) *tim_p) % SECSPERDAY;
+    while (rem < 0)
+    {
+	rem += SECSPERDAY;
+	--days;
+    }
+    while (rem >= SECSPERDAY)
+    {
+	rem -= SECSPERDAY;
+	++days;
+    }
+
+    /* compute hour, min, and sec */
+    res->tm_hour = (int) (rem / SECSPERHOUR);
+    rem %= SECSPERHOUR;
+    res->tm_min = (int) (rem / SECSPERMIN);
+    res->tm_sec = (int) (rem % SECSPERMIN);
+
+    /* compute day of week */
+    if ((res->tm_wday = ((EPOCH_WDAY + days) % DAYSPERWEEK)) < 0)
+	res->tm_wday += DAYSPERWEEK;
+
+    /* compute year & day of year */
+    y = EPOCH_YEAR;
+    if (days >= 0)
+    {
+	for (;;)
+	{
+	    yleap = isleap(y);
+	    if (days < year_lengths[yleap])
+		break;
+	    y++;
+	    days -= year_lengths[yleap];
+	}
+    }
+    else
+    {
+	do
+	{
+	    --y;
+	    yleap = isleap(y);
+	    days += year_lengths[yleap];
+	} while (days < 0);
+    }
+
+    res->tm_year = y - YEAR_BASE;
+    res->tm_yday = days;
+    ip = mon_lengths[yleap];
+    for (res->tm_mon = 0; days >= ip[res->tm_mon]; ++res->tm_mon)
+	days -= ip[res->tm_mon];
+    res->tm_mday = days + 1;
+
+    /* set daylight saving time flag */
+    res->tm_isdst = -1;
+
+    return (res);
+}
+
+static inline char *
+_DEFUN (ctime_r, (tim_p, result),
+	_CONST time_t * tim_p _AND
+	char * result)
+
+{
+    struct tm tm;
+    return asctime_r (localtime_r (tim_p, &tm), result);
+}
+
+#endif
diff --git a/qemu/roms/u-boot/include/linux/types.h b/qemu/roms/u-boot/include/linux/types.h
new file mode 100644
index 000000000..9aebc4e8c
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/types.h
@@ -0,0 +1,151 @@
+#ifndef _LINUX_TYPES_H
+#define _LINUX_TYPES_H
+
+#include <linux/posix_types.h>
+#include <asm/types.h>
+#include <stdbool.h>
+
+#ifndef __KERNEL_STRICT_NAMES
+
+typedef __kernel_fd_set		fd_set;
+typedef __kernel_dev_t		dev_t;
+typedef __kernel_ino_t		ino_t;
+typedef __kernel_mode_t		mode_t;
+typedef __kernel_nlink_t	nlink_t;
+typedef __kernel_off_t		off_t;
+typedef __kernel_pid_t		pid_t;
+typedef __kernel_daddr_t	daddr_t;
+typedef __kernel_key_t		key_t;
+typedef __kernel_suseconds_t	suseconds_t;
+
+#ifdef __KERNEL__
+typedef __kernel_uid32_t	uid_t;
+typedef __kernel_gid32_t	gid_t;
+typedef __kernel_uid16_t        uid16_t;
+typedef __kernel_gid16_t        gid16_t;
+
+#ifdef CONFIG_UID16
+/* This is defined by include/asm-{arch}/posix_types.h */
+typedef __kernel_old_uid_t	old_uid_t;
+typedef __kernel_old_gid_t	old_gid_t;
+#endif /* CONFIG_UID16 */
+
+/* libc5 includes this file to define uid_t, thus uid_t can never change
+ * when it is included by non-kernel code
+ */
+#else
+typedef __kernel_uid_t		uid_t;
+typedef __kernel_gid_t		gid_t;
+#endif /* __KERNEL__ */
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __kernel_loff_t		loff_t;
+#endif
+
+/*
+ * The following typedefs are also protected by individual ifdefs for
+ * historical reasons:
+ */
+#ifndef _SIZE_T
+#define _SIZE_T
+typedef __kernel_size_t		size_t;
+#endif
+
+#ifndef _SSIZE_T
+#define _SSIZE_T
+typedef __kernel_ssize_t	ssize_t;
+#endif
+
+#ifndef _PTRDIFF_T
+#define _PTRDIFF_T
+typedef __kernel_ptrdiff_t	ptrdiff_t;
+#endif
+
+#ifndef _TIME_T
+#define _TIME_T
+typedef __kernel_time_t		time_t;
+#endif
+
+#ifndef _CLOCK_T
+#define _CLOCK_T
+typedef __kernel_clock_t	clock_t;
+#endif
+
+#ifndef _CADDR_T
+#define _CADDR_T
+typedef __kernel_caddr_t	caddr_t;
+#endif
+
+/* bsd */
+typedef unsigned char		u_char;
+typedef unsigned short		u_short;
+typedef unsigned int		u_int;
+typedef unsigned long		u_long;
+
+/* sysv */
+typedef unsigned char		unchar;
+typedef unsigned short		ushort;
+typedef unsigned int		uint;
+typedef unsigned long		ulong;
+
+#ifndef __BIT_TYPES_DEFINED__
+#define __BIT_TYPES_DEFINED__
+
+typedef		__u8		u_int8_t;
+typedef		__s8		int8_t;
+typedef		__u16		u_int16_t;
+typedef		__s16		int16_t;
+typedef		__u32		u_int32_t;
+typedef		__s32		int32_t;
+
+#endif /* !(__BIT_TYPES_DEFINED__) */
+
+typedef		__u8		uint8_t;
+typedef		__u16		uint16_t;
+typedef		__u32		uint32_t;
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef		__u64		uint64_t;
+typedef		__u64		u_int64_t;
+typedef		__s64		int64_t;
+#endif
+
+#endif /* __KERNEL_STRICT_NAMES */
+
+/*
+ * Below are truly Linux-specific types that should never collide with
+ * any application/library that wants linux/types.h.
+ */
+#ifdef __CHECKER__
+#define __bitwise__ __attribute__((bitwise))
+#else
+#define __bitwise__
+#endif
+#ifdef __CHECK_ENDIAN__
+#define __bitwise __bitwise__
+#else
+#define __bitwise
+#endif
+
+typedef __u16 __bitwise __le16;
+typedef __u16 __bitwise __be16;
+typedef __u32 __bitwise __le32;
+typedef __u32 __bitwise __be32;
+#if defined(__GNUC__)
+typedef __u64 __bitwise __le64;
+typedef __u64 __bitwise __be64;
+#endif
+typedef __u16 __bitwise __sum16;
+typedef __u32 __bitwise __wsum;
+
+
+typedef unsigned __bitwise__	gfp_t;
+
+struct ustat {
+	__kernel_daddr_t	f_tfree;
+	__kernel_ino_t		f_tinode;
+	char			f_fname[6];
+	char			f_fpack[6];
+};
+
+#endif /* _LINUX_TYPES_H */
diff --git a/qemu/roms/u-boot/include/linux/unaligned/access_ok.h b/qemu/roms/u-boot/include/linux/unaligned/access_ok.h
new file mode 100644
index 000000000..5f46eee23
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/unaligned/access_ok.h
@@ -0,0 +1,66 @@
+#ifndef _LINUX_UNALIGNED_ACCESS_OK_H
+#define _LINUX_UNALIGNED_ACCESS_OK_H
+
+#include <asm/byteorder.h>
+
+static inline u16 get_unaligned_le16(const void *p)
+{
+	return le16_to_cpup((__le16 *)p);
+}
+
+static inline u32 get_unaligned_le32(const void *p)
+{
+	return le32_to_cpup((__le32 *)p);
+}
+
+static inline u64 get_unaligned_le64(const void *p)
+{
+	return le64_to_cpup((__le64 *)p);
+}
+
+static inline u16 get_unaligned_be16(const void *p)
+{
+	return be16_to_cpup((__be16 *)p);
+}
+
+static inline u32 get_unaligned_be32(const void *p)
+{
+	return be32_to_cpup((__be32 *)p);
+}
+
+static inline u64 get_unaligned_be64(const void *p)
+{
+	return be64_to_cpup((__be64 *)p);
+}
+
+static inline void put_unaligned_le16(u16 val, void *p)
+{
+	*((__le16 *)p) = cpu_to_le16(val);
+}
+
+static inline void put_unaligned_le32(u32 val, void *p)
+{
+	*((__le32 *)p) = cpu_to_le32(val);
+}
+
+static inline void put_unaligned_le64(u64 val, void *p)
+{
+	*((__le64 *)p) = cpu_to_le64(val);
+}
+
+static inline void put_unaligned_be16(u16 val, void *p)
+{
+	*((__be16 *)p) = cpu_to_be16(val);
+}
+
+static inline void put_unaligned_be32(u32 val, void *p)
+{
+	*((__be32 *)p) = cpu_to_be32(val);
+}
+
+static inline void put_unaligned_be64(u64 val, void *p)
+{
+	*((__be64 *)p) = cpu_to_be64(val);
+}
+
+#endif /* _LINUX_UNALIGNED_ACCESS_OK_H */
diff --git a/qemu/roms/u-boot/include/linux/unaligned/be_byteshift.h b/qemu/roms/u-boot/include/linux/unaligned/be_byteshift.h
new file mode 100644
index 000000000..9356b2422
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/unaligned/be_byteshift.h
@@ -0,0 +1,70 @@
+#ifndef _LINUX_UNALIGNED_BE_BYTESHIFT_H
+#define _LINUX_UNALIGNED_BE_BYTESHIFT_H
+
+#include <linux/types.h>
+
+static inline u16 __get_unaligned_be16(const u8 *p)
+{
+	return p[0] << 8 | p[1];
+}
+
+static inline u32 __get_unaligned_be32(const u8 *p)
+{
+	return p[0] << 24 | p[1] << 16 | p[2] << 8 | p[3];
+}
+
+static inline u64 __get_unaligned_be64(const u8 *p)
+{
+	return (u64)__get_unaligned_be32(p) << 32 |
+	       __get_unaligned_be32(p + 4);
+}
+
+static inline void __put_unaligned_be16(u16 val, u8 *p)
+{
+	*p++ = val >> 8;
+	*p++ = val;
+}
+
+static inline void __put_unaligned_be32(u32 val, u8 *p)
+{
+	__put_unaligned_be16(val >> 16, p);
+	__put_unaligned_be16(val, p + 2);
+}
+
+static inline void __put_unaligned_be64(u64 val, u8 *p)
+{
+	__put_unaligned_be32(val >> 32, p);
+	__put_unaligned_be32(val, p + 4);
+}
+
+static inline u16 get_unaligned_be16(const void *p)
+{
+	return __get_unaligned_be16((const u8 *)p);
+}
+
+static inline u32 get_unaligned_be32(const void *p)
+{
+	return __get_unaligned_be32((const u8 *)p);
+}
+
+static inline u64 get_unaligned_be64(const void *p)
+{
+	return __get_unaligned_be64((const u8 *)p);
+}
+
+static inline void put_unaligned_be16(u16 val, void *p)
+{
+	__put_unaligned_be16(val, p);
+}
+
+static inline void put_unaligned_be32(u32 val, void *p)
+{
+	__put_unaligned_be32(val, p);
+}
+
+static inline void put_unaligned_be64(u64 val, void *p)
+{
+	__put_unaligned_be64(val, p);
+}
+
+#endif /* _LINUX_UNALIGNED_BE_BYTESHIFT_H */
diff --git a/qemu/roms/u-boot/include/linux/unaligned/generic.h b/qemu/roms/u-boot/include/linux/unaligned/generic.h
new file mode 100644
index 000000000..02d97ff3d
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/unaligned/generic.h
@@ -0,0 +1,68 @@
+#ifndef _LINUX_UNALIGNED_GENERIC_H
+#define _LINUX_UNALIGNED_GENERIC_H
+
+/*
+ * Cause a link-time error if we try an unaligned access other than
+ * 1,2,4 or 8 bytes long
+ */
+extern void __bad_unaligned_access_size(void);
+
+#define __get_unaligned_le(ptr) ((__force typeof(*(ptr)))({			\
+	__builtin_choose_expr(sizeof(*(ptr)) == 1, *(ptr),			\
+	__builtin_choose_expr(sizeof(*(ptr)) == 2, get_unaligned_le16((ptr)),	\
+	__builtin_choose_expr(sizeof(*(ptr)) == 4, get_unaligned_le32((ptr)),	\
+	__builtin_choose_expr(sizeof(*(ptr)) == 8, get_unaligned_le64((ptr)),	\
+	__bad_unaligned_access_size()))));					\
+	}))
+
+#define __get_unaligned_be(ptr) ((__force typeof(*(ptr)))({			\
+	__builtin_choose_expr(sizeof(*(ptr)) == 1, *(ptr),			\
+	__builtin_choose_expr(sizeof(*(ptr)) == 2, get_unaligned_be16((ptr)),	\
+	__builtin_choose_expr(sizeof(*(ptr)) == 4, get_unaligned_be32((ptr)),	\
+	__builtin_choose_expr(sizeof(*(ptr)) == 8, get_unaligned_be64((ptr)),	\
+	__bad_unaligned_access_size()))));					\
+	}))
+
+#define __put_unaligned_le(val, ptr) ({					\
+	void *__gu_p = (ptr);						\
+	switch (sizeof(*(ptr))) {					\
+	case 1:								\
+		*(u8 *)__gu_p = (__force u8)(val);			\
+		break;							\
+	case 2:								\
+		put_unaligned_le16((__force u16)(val), __gu_p);		\
+		break;							\
+	case 4:								\
+		put_unaligned_le32((__force u32)(val), __gu_p);		\
+		break;							\
+	case 8:								\
+		put_unaligned_le64((__force u64)(val), __gu_p);		\
+		break;							\
+	default:							\
+		__bad_unaligned_access_size();				\
+		break;							\
+	}								\
+	(void)0; })
+
+#define __put_unaligned_be(val, ptr) ({					\
+	void *__gu_p = (ptr);						\
+	switch (sizeof(*(ptr))) {					\
+	case 1:								\
+		*(u8 *)__gu_p = (__force u8)(val);			\
+		break;							\
+	case 2:								\
+		put_unaligned_be16((__force u16)(val), __gu_p);		\
+		break;							\
+	case 4:								\
+		put_unaligned_be32((__force u32)(val), __gu_p);		\
+		break;							\
+	case 8:								\
+		put_unaligned_be64((__force u64)(val), __gu_p);		\
+		break;							\
+	default:							\
+		__bad_unaligned_access_size();				\
+		break;							\
+	}								\
+	(void)0; })
+
+#endif /* _LINUX_UNALIGNED_GENERIC_H */
diff --git a/qemu/roms/u-boot/include/linux/unaligned/le_byteshift.h b/qemu/roms/u-boot/include/linux/unaligned/le_byteshift.h
new file mode 100644
index 000000000..be376fb79
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/unaligned/le_byteshift.h
@@ -0,0 +1,70 @@
+#ifndef _LINUX_UNALIGNED_LE_BYTESHIFT_H
+#define _LINUX_UNALIGNED_LE_BYTESHIFT_H
+
+#include <linux/types.h>
+
+static inline u16 __get_unaligned_le16(const u8 *p)
+{
+	return p[0] | p[1] << 8;
+}
+
+static inline u32 __get_unaligned_le32(const u8 *p)
+{
+	return p[0] | p[1] << 8 | p[2] << 16 | p[3] << 24;
+}
+
+static inline u64 __get_unaligned_le64(const u8 *p)
+{
+	return (u64)__get_unaligned_le32(p + 4) << 32 |
+	       __get_unaligned_le32(p);
+}
+
+static inline void __put_unaligned_le16(u16 val, u8 *p)
+{
+	*p++ = val;
+	*p++ = val >> 8;
+}
+
+static inline void __put_unaligned_le32(u32 val, u8 *p)
+{
+	__put_unaligned_le16(val >> 16, p + 2);
+	__put_unaligned_le16(val, p);
+}
+
+static inline void __put_unaligned_le64(u64 val, u8 *p)
+{
+	__put_unaligned_le32(val >> 32, p + 4);
+	__put_unaligned_le32(val, p);
+}
+
+static inline u16 get_unaligned_le16(const void *p)
+{
+	return __get_unaligned_le16((const u8 *)p);
+}
+
+static inline u32 get_unaligned_le32(const void *p)
+{
+	return __get_unaligned_le32((const u8 *)p);
+}
+
+static inline u64 get_unaligned_le64(const void *p)
+{
+	return __get_unaligned_le64((const u8 *)p);
+}
+
+static inline void put_unaligned_le16(u16 val, void *p)
+{
+	__put_unaligned_le16(val, p);
+}
+
+static inline void put_unaligned_le32(u32 val, void *p)
+{
+	__put_unaligned_le32(val, p);
+}
+
+static inline void put_unaligned_le64(u64 val, void *p)
+{
+	__put_unaligned_le64(val, p);
+}
+
+#endif /* _LINUX_UNALIGNED_LE_BYTESHIFT_H */
diff --git a/qemu/roms/u-boot/include/linux/usb/atmel_usba_udc.h b/qemu/roms/u-boot/include/linux/usb/atmel_usba_udc.h
new file mode 100644
index 000000000..be29ef0c5
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/usb/atmel_usba_udc.h
@@ -0,0 +1,26 @@
+/*
+ * Platform data definitions for Atmel USBA gadget driver
+ * [Original from Linux kernel: include/linux/usb/atmel_usba_udc.h]
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+#ifndef __LINUX_USB_USBA_H__
+#define __LINUX_USB_USBA_H__
+
+struct usba_ep_data {
+	char *name;
+	int index;
+	int fifo_size;
+	int nr_banks;
+	int can_dma;
+	int can_isoc;
+};
+
+struct usba_platform_data {
+	int			num_ep;
+	struct usba_ep_data	*ep;
+};
+
+extern int usba_udc_probe(struct usba_platform_data *pdata);
+
+#endif /* __LINUX_USB_USBA_H */
diff --git a/qemu/roms/u-boot/include/linux/usb/cdc.h b/qemu/roms/u-boot/include/linux/usb/cdc.h
new file mode 100644
index 000000000..c1d039cb8
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/usb/cdc.h
@@ -0,0 +1,224 @@
+/*
+ * USB Communications Device Class (CDC) definitions
+ *
+ * CDC says how to talk to lots of different types of network adapters,
+ * notably ethernet adapters and various modems.  It's used mostly with
+ * firmware based USB peripherals.
+ *
+ * Ported to U-boot by: Thomas Smits <ts.smits@gmail.com> and
+ *                      Remy Bohmer <linux@bohmer.net>
+ */
+
+#define USB_CDC_SUBCLASS_ACM			0x02
+#define USB_CDC_SUBCLASS_ETHERNET		0x06
+#define USB_CDC_SUBCLASS_WHCM			0x08
+#define USB_CDC_SUBCLASS_DMM			0x09
+#define USB_CDC_SUBCLASS_MDLM			0x0a
+#define USB_CDC_SUBCLASS_OBEX			0x0b
+
+#define USB_CDC_PROTO_NONE			0
+
+#define USB_CDC_ACM_PROTO_AT_V25TER		1
+#define USB_CDC_ACM_PROTO_AT_PCCA101		2
+#define USB_CDC_ACM_PROTO_AT_PCCA101_WAKE	3
+#define USB_CDC_ACM_PROTO_AT_GSM		4
+#define USB_CDC_ACM_PROTO_AT_3G			5
+#define USB_CDC_ACM_PROTO_AT_CDMA		6
+#define USB_CDC_ACM_PROTO_VENDOR		0xff
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * Class-Specific descriptors ... there are a couple dozen of them
+ */
+
+#define USB_CDC_HEADER_TYPE		0x00	/* header_desc */
+#define USB_CDC_CALL_MANAGEMENT_TYPE	0x01	/* call_mgmt_descriptor */
+#define USB_CDC_ACM_TYPE		0x02	/* acm_descriptor */
+#define USB_CDC_UNION_TYPE		0x06	/* union_desc */
+#define USB_CDC_COUNTRY_TYPE		0x07
+#define USB_CDC_NETWORK_TERMINAL_TYPE	0x0a	/* network_terminal_desc */
+#define USB_CDC_ETHERNET_TYPE		0x0f	/* ether_desc */
+#define USB_CDC_WHCM_TYPE		0x11
+#define USB_CDC_MDLM_TYPE		0x12	/* mdlm_desc */
+#define USB_CDC_MDLM_DETAIL_TYPE	0x13	/* mdlm_detail_desc */
+#define USB_CDC_DMM_TYPE		0x14
+#define USB_CDC_OBEX_TYPE		0x15
+
+/* "Header Functional Descriptor" from CDC spec  5.2.3.1 */
+struct usb_cdc_header_desc {
+	__u8	bLength;
+	__u8	bDescriptorType;
+	__u8	bDescriptorSubType;
+
+	__le16	bcdCDC;
+} __attribute__ ((packed));
+
+/* "Call Management Descriptor" from CDC spec  5.2.3.2 */
+struct usb_cdc_call_mgmt_descriptor {
+	__u8	bLength;
+	__u8	bDescriptorType;
+	__u8	bDescriptorSubType;
+
+	__u8	bmCapabilities;
+#define USB_CDC_CALL_MGMT_CAP_CALL_MGMT		0x01
+#define USB_CDC_CALL_MGMT_CAP_DATA_INTF		0x02
+
+	__u8	bDataInterface;
+} __attribute__ ((packed));
+
+/* "Abstract Control Management Descriptor" from CDC spec  5.2.3.3 */
+struct usb_cdc_acm_descriptor {
+	__u8	bLength;
+	__u8	bDescriptorType;
+	__u8	bDescriptorSubType;
+
+	__u8	bmCapabilities;
+} __attribute__ ((packed));
+
+/* capabilities from 5.2.3.3 */
+
+#define USB_CDC_COMM_FEATURE	0x01
+#define USB_CDC_CAP_LINE	0x02
+#define USB_CDC_CAP_BRK	0x04
+#define USB_CDC_CAP_NOTIFY	0x08
+
+/* "Union Functional Descriptor" from CDC spec 5.2.3.8 */
+struct usb_cdc_union_desc {
+	__u8	bLength;
+	__u8	bDescriptorType;
+	__u8	bDescriptorSubType;
+
+	__u8	bMasterInterface0;
+	__u8	bSlaveInterface0;
+	/* ... and there could be other slave interfaces */
+} __attribute__ ((packed));
+
+/* "Country Selection Functional Descriptor" from CDC spec 5.2.3.9 */
+struct usb_cdc_country_functional_desc {
+	__u8	bLength;
+	__u8	bDescriptorType;
+	__u8	bDescriptorSubType;
+
+	__u8	iCountryCodeRelDate;
+	__le16	wCountyCode0;
+	/* ... and there can be a lot of country codes */
+} __attribute__ ((packed));
+
+/* "Network Channel Terminal Functional Descriptor" from CDC spec 5.2.3.11 */
+struct usb_cdc_network_terminal_desc {
+	__u8	bLength;
+	__u8	bDescriptorType;
+	__u8	bDescriptorSubType;
+
+	__u8	bEntityId;
+	__u8	iName;
+	__u8	bChannelIndex;
+	__u8	bPhysicalInterface;
+} __attribute__ ((packed));
+
+/* "Ethernet Networking Functional Descriptor" from CDC spec 5.2.3.16 */
+struct usb_cdc_ether_desc {
+	__u8	bLength;
+	__u8	bDescriptorType;
+	__u8	bDescriptorSubType;
+
+	__u8	iMACAddress;
+	__le32	bmEthernetStatistics;
+	__le16	wMaxSegmentSize;
+	__le16	wNumberMCFilters;
+	__u8	bNumberPowerFilters;
+} __attribute__ ((packed));
+
+/* "MDLM Functional Descriptor" from CDC WMC spec 6.7.2.3 */
+struct usb_cdc_mdlm_desc {
+	__u8	bLength;
+	__u8	bDescriptorType;
+	__u8	bDescriptorSubType;
+
+	__le16	bcdVersion;
+	__u8	bGUID[16];
+} __attribute__ ((packed));
+
+/* "MDLM Detail Functional Descriptor" from CDC WMC spec 6.7.2.4 */
+struct usb_cdc_mdlm_detail_desc {
+	__u8	bLength;
+	__u8	bDescriptorType;
+	__u8	bDescriptorSubType;
+
+	/* type is associated with mdlm_desc.bGUID */
+	__u8	bGuidDescriptorType;
+	__u8	bDetailData[0];
+} __attribute__ ((packed));
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * Class-Specific Control Requests (6.2)
+ *
+ * section 3.6.2.1 table 4 has the ACM profile, for modems.
+ * section 3.8.2 table 10 has the ethernet profile.
+ *
+ * Microsoft's RNDIS stack for Ethernet is a vendor-specific CDC ACM variant,
+ * heavily dependent on the encapsulated (proprietary) command mechanism.
+ */
+
+#define USB_CDC_SEND_ENCAPSULATED_COMMAND	0x00
+#define USB_CDC_GET_ENCAPSULATED_RESPONSE	0x01
+#define USB_CDC_REQ_SET_LINE_CODING		0x20
+#define USB_CDC_REQ_GET_LINE_CODING		0x21
+#define USB_CDC_REQ_SET_CONTROL_LINE_STATE	0x22
+#define USB_CDC_REQ_SEND_BREAK			0x23
+#define USB_CDC_SET_ETHERNET_MULTICAST_FILTERS	0x40
+#define USB_CDC_SET_ETHERNET_PM_PATTERN_FILTER	0x41
+#define USB_CDC_GET_ETHERNET_PM_PATTERN_FILTER	0x42
+#define USB_CDC_SET_ETHERNET_PACKET_FILTER	0x43
+#define USB_CDC_GET_ETHERNET_STATISTIC		0x44
+
+/* Line Coding Structure from CDC spec 6.2.13 */
+struct usb_cdc_line_coding {
+	__le32	dwDTERate;
+	__u8	bCharFormat;
+#define USB_CDC_1_STOP_BITS			0
+#define USB_CDC_1_5_STOP_BITS			1
+#define USB_CDC_2_STOP_BITS			2
+
+	__u8	bParityType;
+#define USB_CDC_NO_PARITY			0
+#define USB_CDC_ODD_PARITY			1
+#define USB_CDC_EVEN_PARITY			2
+#define USB_CDC_MARK_PARITY			3
+#define USB_CDC_SPACE_PARITY			4
+
+	__u8	bDataBits;
+} __attribute__ ((packed));
+
+/* table 62; bits in multicast filter */
+#define	USB_CDC_PACKET_TYPE_PROMISCUOUS		(1 << 0)
+#define	USB_CDC_PACKET_TYPE_ALL_MULTICAST	(1 << 1) /* no filter */
+#define	USB_CDC_PACKET_TYPE_DIRECTED		(1 << 2)
+#define	USB_CDC_PACKET_TYPE_BROADCAST		(1 << 3)
+#define	USB_CDC_PACKET_TYPE_MULTICAST		(1 << 4) /* filtered */
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * Class-Specific Notifications (6.3) sent by interrupt transfers
+ *
+ * section 3.8.2 table 11 of the CDC spec lists Ethernet notifications
+ * section 3.6.2.1 table 5 specifies ACM notifications, accepted by RNDIS
+ * RNDIS also defines its own bit-incompatible notifications
+ */
+
+#define USB_CDC_NOTIFY_NETWORK_CONNECTION	0x00
+#define USB_CDC_NOTIFY_RESPONSE_AVAILABLE	0x01
+#define USB_CDC_NOTIFY_SERIAL_STATE		0x20
+#define USB_CDC_NOTIFY_SPEED_CHANGE		0x2a
+
+struct usb_cdc_notification {
+	__u8	bmRequestType;
+	__u8	bNotificationType;
+	__le16	wValue;
+	__le16	wIndex;
+	__le16	wLength;
+} __attribute__ ((packed));
diff --git a/qemu/roms/u-boot/include/linux/usb/ch9.h b/qemu/roms/u-boot/include/linux/usb/ch9.h
new file mode 100644
index 000000000..bd48704c8
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/usb/ch9.h
@@ -0,0 +1,1005 @@
+/*
+ * This file holds USB constants and structures that are needed for
+ * USB device APIs.  These are used by the USB device model, which is
+ * defined in chapter 9 of the USB 2.0 specification and in the
+ * Wireless USB 1.0 (spread around).  Linux has several APIs in C that
+ * need these:
+ *
+ * - the master/host side Linux-USB kernel driver API;
+ * - the "usbfs" user space API; and
+ * - the Linux "gadget" slave/device/peripheral side driver API.
+ *
+ * USB 2.0 adds an additional "On The Go" (OTG) mode, which lets systems
+ * act either as a USB master/host or as a USB slave/device.  That means
+ * the master and slave side APIs benefit from working well together.
+ *
+ * There's also "Wireless USB", using low power short range radios for
+ * peripheral interconnection but otherwise building on the USB framework.
+ *
+ * Note all descriptors are declared '__attribute__((packed))' so that:
+ *
+ * [a] they never get padded, either internally (USB spec writers
+ *     probably handled that) or externally;
+ *
+ * [b] so that accessing bigger-than-a-bytes fields will never
+ *     generate bus errors on any platform, even when the location of
+ *     its descriptor inside a bundle isn't "naturally aligned", and
+ *
+ * [c] for consistency, removing all doubt even when it appears to
+ *     someone that the two other points are non-issues for that
+ *     particular descriptor type.
+ */
+
+#ifndef __LINUX_USB_CH9_H
+#define __LINUX_USB_CH9_H
+
+#include <linux/types.h>	/* __u8 etc */
+#include <asm/byteorder.h>	/* le16_to_cpu */
+#include <asm/unaligned.h>	/* get_unaligned() */
+
+/*-------------------------------------------------------------------------*/
+
+/* CONTROL REQUEST SUPPORT */
+
+/*
+ * USB directions
+ *
+ * This bit flag is used in endpoint descriptors' bEndpointAddress field.
+ * It's also one of three fields in control requests bRequestType.
+ */
+#define USB_DIR_OUT			0		/* to device */
+#define USB_DIR_IN			0x80		/* to host */
+
+/*
+ * USB types, the second of three bRequestType fields
+ */
+#define USB_TYPE_MASK			(0x03 << 5)
+#define USB_TYPE_STANDARD		(0x00 << 5)
+#define USB_TYPE_CLASS			(0x01 << 5)
+#define USB_TYPE_VENDOR			(0x02 << 5)
+#define USB_TYPE_RESERVED		(0x03 << 5)
+
+/*
+ * USB recipients, the third of three bRequestType fields
+ */
+#define USB_RECIP_MASK			0x1f
+#define USB_RECIP_DEVICE		0x00
+#define USB_RECIP_INTERFACE		0x01
+#define USB_RECIP_ENDPOINT		0x02
+#define USB_RECIP_OTHER			0x03
+/* From Wireless USB 1.0 */
+#define USB_RECIP_PORT			0x04
+#define USB_RECIP_RPIPE		0x05
+
+/*
+ * Standard requests, for the bRequest field of a SETUP packet.
+ *
+ * These are qualified by the bRequestType field, so that for example
+ * TYPE_CLASS or TYPE_VENDOR specific feature flags could be retrieved
+ * by a GET_STATUS request.
+ */
+#define USB_REQ_GET_STATUS		0x00
+#define USB_REQ_CLEAR_FEATURE		0x01
+#define USB_REQ_SET_FEATURE		0x03
+#define USB_REQ_SET_ADDRESS		0x05
+#define USB_REQ_GET_DESCRIPTOR		0x06
+#define USB_REQ_SET_DESCRIPTOR		0x07
+#define USB_REQ_GET_CONFIGURATION	0x08
+#define USB_REQ_SET_CONFIGURATION	0x09
+#define USB_REQ_GET_INTERFACE		0x0A
+#define USB_REQ_SET_INTERFACE		0x0B
+#define USB_REQ_SYNCH_FRAME		0x0C
+#define USB_REQ_SET_SEL			0x30
+#define USB_REQ_SET_ISOCH_DELAY		0x31
+
+#define USB_REQ_SET_ENCRYPTION		0x0D	/* Wireless USB */
+#define USB_REQ_GET_ENCRYPTION		0x0E
+#define USB_REQ_RPIPE_ABORT		0x0E
+#define USB_REQ_SET_HANDSHAKE		0x0F
+#define USB_REQ_RPIPE_RESET		0x0F
+#define USB_REQ_GET_HANDSHAKE		0x10
+#define USB_REQ_SET_CONNECTION		0x11
+#define USB_REQ_SET_SECURITY_DATA	0x12
+#define USB_REQ_GET_SECURITY_DATA	0x13
+#define USB_REQ_SET_WUSB_DATA		0x14
+#define USB_REQ_LOOPBACK_DATA_WRITE	0x15
+#define USB_REQ_LOOPBACK_DATA_READ	0x16
+#define USB_REQ_SET_INTERFACE_DS	0x17
+
+/* The Link Power Management (LPM) ECN defines USB_REQ_TEST_AND_SET command,
+ * used by hubs to put ports into a new L1 suspend state, except that it
+ * forgot to define its number ...
+ */
+
+/*
+ * USB feature flags are written using USB_REQ_{CLEAR,SET}_FEATURE, and
+ * are read as a bit array returned by USB_REQ_GET_STATUS.  (So there
+ * are at most sixteen features of each type.)  Hubs may also support a
+ * new USB_REQ_TEST_AND_SET_FEATURE to put ports into L1 suspend.
+ */
+#define USB_DEVICE_SELF_POWERED		0	/* (read only) */
+#define USB_DEVICE_REMOTE_WAKEUP	1	/* dev may initiate wakeup */
+#define USB_DEVICE_TEST_MODE		2	/* (wired high speed only) */
+#define USB_DEVICE_BATTERY		2	/* (wireless) */
+#define USB_DEVICE_B_HNP_ENABLE		3	/* (otg) dev may initiate HNP */
+#define USB_DEVICE_WUSB_DEVICE		3	/* (wireless)*/
+#define USB_DEVICE_A_HNP_SUPPORT	4	/* (otg) RH port supports HNP */
+#define USB_DEVICE_A_ALT_HNP_SUPPORT	5	/* (otg) other RH port does */
+#define USB_DEVICE_DEBUG_MODE		6	/* (special devices only) */
+
+/*
+ * Test Mode Selectors
+ * See USB 2.0 spec Table 9-7
+ */
+#define	TEST_J		1
+#define	TEST_K		2
+#define	TEST_SE0_NAK	3
+#define	TEST_PACKET	4
+#define	TEST_FORCE_EN	5
+
+/*
+ * New Feature Selectors as added by USB 3.0
+ * See USB 3.0 spec Table 9-6
+ */
+#define USB_DEVICE_U1_ENABLE	48	/* dev may initiate U1 transition */
+#define USB_DEVICE_U2_ENABLE	49	/* dev may initiate U2 transition */
+#define USB_DEVICE_LTM_ENABLE	50	/* dev may send LTM */
+#define USB_INTRF_FUNC_SUSPEND	0	/* function suspend */
+
+#define USB_INTR_FUNC_SUSPEND_OPT_MASK	0xFF00
+/*
+ * Suspend Options, Table 9-7 USB 3.0 spec
+ */
+#define USB_INTRF_FUNC_SUSPEND_LP	(1 << (8 + 0))
+#define USB_INTRF_FUNC_SUSPEND_RW	(1 << (8 + 1))
+
+#define USB_ENDPOINT_HALT		0	/* IN/OUT will STALL */
+
+/* Bit array elements as returned by the USB_REQ_GET_STATUS request. */
+#define USB_DEV_STAT_U1_ENABLED		2	/* transition into U1 state */
+#define USB_DEV_STAT_U2_ENABLED		3	/* transition into U2 state */
+#define USB_DEV_STAT_LTM_ENABLED	4	/* Latency tolerance messages */
+
+/**
+ * struct usb_ctrlrequest - SETUP data for a USB device control request
+ * @bRequestType: matches the USB bmRequestType field
+ * @bRequest: matches the USB bRequest field
+ * @wValue: matches the USB wValue field (le16 byte order)
+ * @wIndex: matches the USB wIndex field (le16 byte order)
+ * @wLength: matches the USB wLength field (le16 byte order)
+ *
+ * This structure is used to send control requests to a USB device.  It matches
+ * the different fields of the USB 2.0 Spec section 9.3, table 9-2.  See the
+ * USB spec for a fuller description of the different fields, and what they are
+ * used for.
+ *
+ * Note that the driver for any interface can issue control requests.
+ * For most devices, interfaces don't coordinate with each other, so
+ * such requests may be made at any time.
+ */
+struct usb_ctrlrequest {
+	__u8 bRequestType;
+	__u8 bRequest;
+	__le16 wValue;
+	__le16 wIndex;
+	__le16 wLength;
+} __attribute__ ((packed));
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * STANDARD DESCRIPTORS ... as returned by GET_DESCRIPTOR, or
+ * (rarely) accepted by SET_DESCRIPTOR.
+ *
+ * Note that all multi-byte values here are encoded in little endian
+ * byte order "on the wire".  Within the kernel and when exposed
+ * through the Linux-USB APIs, they are not converted to cpu byte
+ * order; it is the responsibility of the client code to do this.
+ * The single exception is when device and configuration descriptors (but
+ * not other descriptors) are read from usbfs (i.e. /proc/bus/usb/BBB/DDD);
+ * in this case the fields are converted to host endianness by the kernel.
+ */
+
+/*
+ * Descriptor types ... USB 2.0 spec table 9.5
+ */
+#define USB_DT_DEVICE			0x01
+#define USB_DT_CONFIG			0x02
+#define USB_DT_STRING			0x03
+#define USB_DT_INTERFACE		0x04
+#define USB_DT_ENDPOINT			0x05
+#define USB_DT_DEVICE_QUALIFIER		0x06
+#define USB_DT_OTHER_SPEED_CONFIG	0x07
+#define USB_DT_INTERFACE_POWER		0x08
+/* these are from a minor usb 2.0 revision (ECN) */
+#define USB_DT_OTG			0x09
+#define USB_DT_DEBUG			0x0a
+#define USB_DT_INTERFACE_ASSOCIATION	0x0b
+/* these are from the Wireless USB spec */
+#define USB_DT_SECURITY			0x0c
+#define USB_DT_KEY			0x0d
+#define USB_DT_ENCRYPTION_TYPE		0x0e
+#define USB_DT_BOS			0x0f
+#define USB_DT_DEVICE_CAPABILITY	0x10
+#define USB_DT_WIRELESS_ENDPOINT_COMP	0x11
+#define USB_DT_WIRE_ADAPTER		0x21
+#define USB_DT_RPIPE			0x22
+#define USB_DT_CS_RADIO_CONTROL		0x23
+/* From the T10 UAS specification */
+#define USB_DT_PIPE_USAGE		0x24
+/* From the USB 3.0 spec */
+#define	USB_DT_SS_ENDPOINT_COMP		0x30
+
+/* Conventional codes for class-specific descriptors.  The convention is
+ * defined in the USB "Common Class" Spec (3.11).  Individual class specs
+ * are authoritative for their usage, not the "common class" writeup.
+ */
+#define USB_DT_CS_DEVICE		(USB_TYPE_CLASS | USB_DT_DEVICE)
+#define USB_DT_CS_CONFIG		(USB_TYPE_CLASS | USB_DT_CONFIG)
+#define USB_DT_CS_STRING		(USB_TYPE_CLASS | USB_DT_STRING)
+#define USB_DT_CS_INTERFACE		(USB_TYPE_CLASS | USB_DT_INTERFACE)
+#define USB_DT_CS_ENDPOINT		(USB_TYPE_CLASS | USB_DT_ENDPOINT)
+
+/* All standard descriptors have these 2 fields at the beginning */
+struct usb_descriptor_header {
+	__u8  bLength;
+	__u8  bDescriptorType;
+} __attribute__ ((packed));
+
+
+/*-------------------------------------------------------------------------*/
+
+/* USB_DT_DEVICE: Device descriptor */
+struct usb_device_descriptor {
+	__u8  bLength;
+	__u8  bDescriptorType;
+
+	__le16 bcdUSB;
+	__u8  bDeviceClass;
+	__u8  bDeviceSubClass;
+	__u8  bDeviceProtocol;
+	__u8  bMaxPacketSize0;
+	__le16 idVendor;
+	__le16 idProduct;
+	__le16 bcdDevice;
+	__u8  iManufacturer;
+	__u8  iProduct;
+	__u8  iSerialNumber;
+	__u8  bNumConfigurations;
+} __attribute__ ((packed));
+
+#define USB_DT_DEVICE_SIZE		18
+
+
+/*
+ * Device and/or Interface Class codes
+ * as found in bDeviceClass or bInterfaceClass
+ * and defined by www.usb.org documents
+ */
+#define USB_CLASS_PER_INTERFACE		0	/* for DeviceClass */
+#define USB_CLASS_AUDIO			1
+#define USB_CLASS_COMM			2
+#define USB_CLASS_HID			3
+#define USB_CLASS_PHYSICAL		5
+#define USB_CLASS_STILL_IMAGE		6
+#define USB_CLASS_PRINTER		7
+#define USB_CLASS_MASS_STORAGE		8
+#define USB_CLASS_HUB			9
+#define USB_CLASS_CDC_DATA		0x0a
+#define USB_CLASS_CSCID			0x0b	/* chip+ smart card */
+#define USB_CLASS_CONTENT_SEC		0x0d	/* content security */
+#define USB_CLASS_VIDEO			0x0e
+#define USB_CLASS_WIRELESS_CONTROLLER	0xe0
+#define USB_CLASS_MISC			0xef
+#define USB_CLASS_APP_SPEC		0xfe
+#define USB_CLASS_VENDOR_SPEC		0xff
+
+#define USB_SUBCLASS_VENDOR_SPEC	0xff
+
+/*-------------------------------------------------------------------------*/
+
+/* USB_DT_CONFIG: Configuration descriptor information.
+ *
+ * USB_DT_OTHER_SPEED_CONFIG is the same descriptor, except that the
+ * descriptor type is different.  Highspeed-capable devices can look
+ * different depending on what speed they're currently running.  Only
+ * devices with a USB_DT_DEVICE_QUALIFIER have any OTHER_SPEED_CONFIG
+ * descriptors.
+ */
+struct usb_config_descriptor {
+	__u8  bLength;
+	__u8  bDescriptorType;
+
+	__le16 wTotalLength;
+	__u8  bNumInterfaces;
+	__u8  bConfigurationValue;
+	__u8  iConfiguration;
+	__u8  bmAttributes;
+	__u8  bMaxPower;
+} __attribute__ ((packed));
+
+#define USB_DT_CONFIG_SIZE		9
+
+/* from config descriptor bmAttributes */
+#define USB_CONFIG_ATT_ONE		(1 << 7)	/* must be set */
+#define USB_CONFIG_ATT_SELFPOWER	(1 << 6)	/* self powered */
+#define USB_CONFIG_ATT_WAKEUP		(1 << 5)	/* can wakeup */
+#define USB_CONFIG_ATT_BATTERY		(1 << 4)	/* battery powered */
+
+/*-------------------------------------------------------------------------*/
+
+/* USB_DT_STRING: String descriptor */
+struct usb_string_descriptor {
+	__u8  bLength;
+	__u8  bDescriptorType;
+
+	__le16 wData[1];		/* UTF-16LE encoded */
+} __attribute__ ((packed));
+
+/* note that "string" zero is special, it holds language codes that
+ * the device supports, not Unicode characters.
+ */
+
+/*-------------------------------------------------------------------------*/
+
+/* USB_DT_INTERFACE: Interface descriptor */
+struct usb_interface_descriptor {
+	__u8  bLength;
+	__u8  bDescriptorType;
+
+	__u8  bInterfaceNumber;
+	__u8  bAlternateSetting;
+	__u8  bNumEndpoints;
+	__u8  bInterfaceClass;
+	__u8  bInterfaceSubClass;
+	__u8  bInterfaceProtocol;
+	__u8  iInterface;
+} __attribute__ ((packed));
+
+#define USB_DT_INTERFACE_SIZE		9
+
+/*-------------------------------------------------------------------------*/
+
+/* USB_DT_ENDPOINT: Endpoint descriptor */
+struct usb_endpoint_descriptor {
+	__u8  bLength;
+	__u8  bDescriptorType;
+
+	__u8  bEndpointAddress;
+	__u8  bmAttributes;
+	__le16 wMaxPacketSize;
+	__u8  bInterval;
+
+	/* NOTE:  these two are _only_ in audio endpoints. */
+	/* use USB_DT_ENDPOINT*_SIZE in bLength, not sizeof. */
+	__u8  bRefresh;
+	__u8  bSynchAddress;
+} __attribute__ ((packed));
+
+#define USB_DT_ENDPOINT_SIZE		7
+#define USB_DT_ENDPOINT_AUDIO_SIZE	9	/* Audio extension */
+
+
+/*
+ * Endpoints
+ */
+#define USB_ENDPOINT_NUMBER_MASK	0x0f	/* in bEndpointAddress */
+#define USB_ENDPOINT_DIR_MASK		0x80
+
+#define USB_ENDPOINT_XFERTYPE_MASK	0x03	/* in bmAttributes */
+#define USB_ENDPOINT_XFER_CONTROL	0
+#define USB_ENDPOINT_XFER_ISOC		1
+#define USB_ENDPOINT_XFER_BULK		2
+#define USB_ENDPOINT_XFER_INT		3
+#define USB_ENDPOINT_MAX_ADJUSTABLE	0x80
+
+/* The USB 3.0 spec redefines bits 5:4 of bmAttributes as interrupt ep type. */
+#define USB_ENDPOINT_INTRTYPE		0x30
+#define USB_ENDPOINT_INTR_PERIODIC	(0 << 4)
+#define USB_ENDPOINT_INTR_NOTIFICATION	(1 << 4)
+
+#define USB_ENDPOINT_SYNCTYPE		0x0c
+#define USB_ENDPOINT_SYNC_NONE		(0 << 2)
+#define USB_ENDPOINT_SYNC_ASYNC		(1 << 2)
+#define USB_ENDPOINT_SYNC_ADAPTIVE	(2 << 2)
+#define USB_ENDPOINT_SYNC_SYNC		(3 << 2)
+
+#define USB_ENDPOINT_USAGE_MASK		0x30
+#define USB_ENDPOINT_USAGE_DATA		0x00
+#define USB_ENDPOINT_USAGE_FEEDBACK	0x10
+#define USB_ENDPOINT_USAGE_IMPLICIT_FB	0x20	/* Implicit feedback Data endpoint */
+
+/*-------------------------------------------------------------------------*/
+
+/**
+ * usb_endpoint_num - get the endpoint's number
+ * @epd: endpoint to be checked
+ *
+ * Returns @epd's number: 0 to 15.
+ */
+static inline int usb_endpoint_num(const struct usb_endpoint_descriptor *epd)
+{
+	return epd->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
+}
+
+/**
+ * usb_endpoint_type - get the endpoint's transfer type
+ * @epd: endpoint to be checked
+ *
+ * Returns one of USB_ENDPOINT_XFER_{CONTROL, ISOC, BULK, INT} according
+ * to @epd's transfer type.
+ */
+static inline int usb_endpoint_type(const struct usb_endpoint_descriptor *epd)
+{
+	return epd->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
+}
+
+/**
+ * usb_endpoint_dir_in - check if the endpoint has IN direction
+ * @epd: endpoint to be checked
+ *
+ * Returns true if the endpoint is of type IN, otherwise it returns false.
+ */
+static inline int usb_endpoint_dir_in(const struct usb_endpoint_descriptor *epd)
+{
+	return ((epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN);
+}
+
+/**
+ * usb_endpoint_dir_out - check if the endpoint has OUT direction
+ * @epd: endpoint to be checked
+ *
+ * Returns true if the endpoint is of type OUT, otherwise it returns false.
+ */
+static inline int usb_endpoint_dir_out(
+				const struct usb_endpoint_descriptor *epd)
+{
+	return ((epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK) == USB_DIR_OUT);
+}
+
+/**
+ * usb_endpoint_xfer_bulk - check if the endpoint has bulk transfer type
+ * @epd: endpoint to be checked
+ *
+ * Returns true if the endpoint is of type bulk, otherwise it returns false.
+ */
+static inline int usb_endpoint_xfer_bulk(
+				const struct usb_endpoint_descriptor *epd)
+{
+	return ((epd->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) ==
+		USB_ENDPOINT_XFER_BULK);
+}
+
+/**
+ * usb_endpoint_xfer_control - check if the endpoint has control transfer type
+ * @epd: endpoint to be checked
+ *
+ * Returns true if the endpoint is of type control, otherwise it returns false.
+ */
+static inline int usb_endpoint_xfer_control(
+				const struct usb_endpoint_descriptor *epd)
+{
+	return ((epd->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) ==
+		USB_ENDPOINT_XFER_CONTROL);
+}
+
+/**
+ * usb_endpoint_xfer_int - check if the endpoint has interrupt transfer type
+ * @epd: endpoint to be checked
+ *
+ * Returns true if the endpoint is of type interrupt, otherwise it returns
+ * false.
+ */
+static inline int usb_endpoint_xfer_int(
+				const struct usb_endpoint_descriptor *epd)
+{
+	return ((epd->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) ==
+		USB_ENDPOINT_XFER_INT);
+}
+
+/**
+ * usb_endpoint_xfer_isoc - check if the endpoint has isochronous transfer type
+ * @epd: endpoint to be checked
+ *
+ * Returns true if the endpoint is of type isochronous, otherwise it returns
+ * false.
+ */
+static inline int usb_endpoint_xfer_isoc(
+				const struct usb_endpoint_descriptor *epd)
+{
+	return ((epd->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) ==
+		USB_ENDPOINT_XFER_ISOC);
+}
+
+/**
+ * usb_endpoint_is_bulk_in - check if the endpoint is bulk IN
+ * @epd: endpoint to be checked
+ *
+ * Returns true if the endpoint has bulk transfer type and IN direction,
+ * otherwise it returns false.
+ */
+static inline int usb_endpoint_is_bulk_in(
+				const struct usb_endpoint_descriptor *epd)
+{
+	return usb_endpoint_xfer_bulk(epd) && usb_endpoint_dir_in(epd);
+}
+
+/**
+ * usb_endpoint_is_bulk_out - check if the endpoint is bulk OUT
+ * @epd: endpoint to be checked
+ *
+ * Returns true if the endpoint has bulk transfer type and OUT direction,
+ * otherwise it returns false.
+ */
+static inline int usb_endpoint_is_bulk_out(
+				const struct usb_endpoint_descriptor *epd)
+{
+	return usb_endpoint_xfer_bulk(epd) && usb_endpoint_dir_out(epd);
+}
+
+/**
+ * usb_endpoint_is_int_in - check if the endpoint is interrupt IN
+ * @epd: endpoint to be checked
+ *
+ * Returns true if the endpoint has interrupt transfer type and IN direction,
+ * otherwise it returns false.
+ */
+static inline int usb_endpoint_is_int_in(
+				const struct usb_endpoint_descriptor *epd)
+{
+	return usb_endpoint_xfer_int(epd) && usb_endpoint_dir_in(epd);
+}
+
+/**
+ * usb_endpoint_is_int_out - check if the endpoint is interrupt OUT
+ * @epd: endpoint to be checked
+ *
+ * Returns true if the endpoint has interrupt transfer type and OUT direction,
+ * otherwise it returns false.
+ */
+static inline int usb_endpoint_is_int_out(
+				const struct usb_endpoint_descriptor *epd)
+{
+	return usb_endpoint_xfer_int(epd) && usb_endpoint_dir_out(epd);
+}
+
+/**
+ * usb_endpoint_is_isoc_in - check if the endpoint is isochronous IN
+ * @epd: endpoint to be checked
+ *
+ * Returns true if the endpoint has isochronous transfer type and IN direction,
+ * otherwise it returns false.
+ */
+static inline int usb_endpoint_is_isoc_in(
+				const struct usb_endpoint_descriptor *epd)
+{
+	return usb_endpoint_xfer_isoc(epd) && usb_endpoint_dir_in(epd);
+}
+
+/**
+ * usb_endpoint_is_isoc_out - check if the endpoint is isochronous OUT
+ * @epd: endpoint to be checked
+ *
+ * Returns true if the endpoint has isochronous transfer type and OUT direction,
+ * otherwise it returns false.
+ */
+static inline int usb_endpoint_is_isoc_out(
+				const struct usb_endpoint_descriptor *epd)
+{
+	return usb_endpoint_xfer_isoc(epd) && usb_endpoint_dir_out(epd);
+}
+
+/**
+ * usb_endpoint_maxp - get endpoint's max packet size
+ * @epd: endpoint to be checked
+ *
+ * Returns @epd's max packet
+ */
+static inline int usb_endpoint_maxp(const struct usb_endpoint_descriptor *epd)
+{
+	return __le16_to_cpu(get_unaligned(&epd->wMaxPacketSize));
+}
+
+static inline int usb_endpoint_interrupt_type(
+		const struct usb_endpoint_descriptor *epd)
+{
+	return epd->bmAttributes & USB_ENDPOINT_INTRTYPE;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* USB_DT_SS_ENDPOINT_COMP: SuperSpeed Endpoint Companion descriptor */
+struct usb_ss_ep_comp_descriptor {
+	__u8  bLength;
+	__u8  bDescriptorType;
+
+	__u8  bMaxBurst;
+	__u8  bmAttributes;
+	__le16 wBytesPerInterval;
+} __attribute__ ((packed));
+
+#define USB_DT_SS_EP_COMP_SIZE		6
+
+/* Bits 4:0 of bmAttributes if this is a bulk endpoint */
+static inline int
+usb_ss_max_streams(const struct usb_ss_ep_comp_descriptor *comp)
+{
+	int		max_streams;
+
+	if (!comp)
+		return 0;
+
+	max_streams = comp->bmAttributes & 0x1f;
+
+	if (!max_streams)
+		return 0;
+
+	max_streams = 1 << max_streams;
+
+	return max_streams;
+}
+
+/* Bits 1:0 of bmAttributes if this is an isoc endpoint */
+#define USB_SS_MULT(p)			(1 + ((p) & 0x3))
+
+/*-------------------------------------------------------------------------*/
+
+/* USB_DT_DEVICE_QUALIFIER: Device Qualifier descriptor */
+struct usb_qualifier_descriptor {
+	__u8  bLength;
+	__u8  bDescriptorType;
+
+	__le16 bcdUSB;
+	__u8  bDeviceClass;
+	__u8  bDeviceSubClass;
+	__u8  bDeviceProtocol;
+	__u8  bMaxPacketSize0;
+	__u8  bNumConfigurations;
+	__u8  bRESERVED;
+} __attribute__ ((packed));
+
+
+/*-------------------------------------------------------------------------*/
+
+/* USB_DT_OTG (from OTG 1.0a supplement) */
+struct usb_otg_descriptor {
+	__u8  bLength;
+	__u8  bDescriptorType;
+
+	__u8  bmAttributes;	/* support for HNP, SRP, etc */
+} __attribute__ ((packed));
+
+/* from usb_otg_descriptor.bmAttributes */
+#define USB_OTG_SRP		(1 << 0)
+#define USB_OTG_HNP		(1 << 1)	/* swap host/device roles */
+
+/*-------------------------------------------------------------------------*/
+
+/* USB_DT_DEBUG:  for special highspeed devices, replacing serial console */
+struct usb_debug_descriptor {
+	__u8  bLength;
+	__u8  bDescriptorType;
+
+	/* bulk endpoints with 8 byte maxpacket */
+	__u8  bDebugInEndpoint;
+	__u8  bDebugOutEndpoint;
+} __attribute__((packed));
+
+/*-------------------------------------------------------------------------*/
+
+/* USB_DT_INTERFACE_ASSOCIATION: groups interfaces */
+struct usb_interface_assoc_descriptor {
+	__u8  bLength;
+	__u8  bDescriptorType;
+
+	__u8  bFirstInterface;
+	__u8  bInterfaceCount;
+	__u8  bFunctionClass;
+	__u8  bFunctionSubClass;
+	__u8  bFunctionProtocol;
+	__u8  iFunction;
+} __attribute__ ((packed));
+
+
+/*-------------------------------------------------------------------------*/
+
+/* USB_DT_SECURITY:  group of wireless security descriptors, including
+ * encryption types available for setting up a CC/association.
+ */
+struct usb_security_descriptor {
+	__u8  bLength;
+	__u8  bDescriptorType;
+
+	__le16 wTotalLength;
+	__u8  bNumEncryptionTypes;
+} __attribute__((packed));
+
+/*-------------------------------------------------------------------------*/
+
+/* USB_DT_KEY:  used with {GET,SET}_SECURITY_DATA; only public keys
+ * may be retrieved.
+ */
+struct usb_key_descriptor {
+	__u8  bLength;
+	__u8  bDescriptorType;
+
+	__u8  tTKID[3];
+	__u8  bReserved;
+	__u8  bKeyData[0];
+} __attribute__((packed));
+
+/*-------------------------------------------------------------------------*/
+
+/* USB_DT_ENCRYPTION_TYPE:  bundled in DT_SECURITY groups */
+struct usb_encryption_descriptor {
+	__u8  bLength;
+	__u8  bDescriptorType;
+
+	__u8  bEncryptionType;
+#define	USB_ENC_TYPE_UNSECURE		0
+#define	USB_ENC_TYPE_WIRED		1	/* non-wireless mode */
+#define	USB_ENC_TYPE_CCM_1		2	/* aes128/cbc session */
+#define	USB_ENC_TYPE_RSA_1		3	/* rsa3072/sha1 auth */
+	__u8  bEncryptionValue;		/* use in SET_ENCRYPTION */
+	__u8  bAuthKeyIndex;
+} __attribute__((packed));
+
+
+/*-------------------------------------------------------------------------*/
+
+/* USB_DT_BOS:  group of device-level capabilities */
+struct usb_bos_descriptor {
+	__u8  bLength;
+	__u8  bDescriptorType;
+
+	__le16 wTotalLength;
+	__u8  bNumDeviceCaps;
+} __attribute__((packed));
+
+#define USB_DT_BOS_SIZE		5
+/*-------------------------------------------------------------------------*/
+
+/* USB_DT_DEVICE_CAPABILITY:  grouped with BOS */
+struct usb_dev_cap_header {
+	__u8  bLength;
+	__u8  bDescriptorType;
+	__u8  bDevCapabilityType;
+} __attribute__((packed));
+
+#define	USB_CAP_TYPE_WIRELESS_USB	1
+
+struct usb_wireless_cap_descriptor {	/* Ultra Wide Band */
+	__u8  bLength;
+	__u8  bDescriptorType;
+	__u8  bDevCapabilityType;
+
+	__u8  bmAttributes;
+#define	USB_WIRELESS_P2P_DRD		(1 << 1)
+#define	USB_WIRELESS_BEACON_MASK	(3 << 2)
+#define	USB_WIRELESS_BEACON_SELF	(1 << 2)
+#define	USB_WIRELESS_BEACON_DIRECTED	(2 << 2)
+#define	USB_WIRELESS_BEACON_NONE	(3 << 2)
+	__le16 wPHYRates;	/* bit rates, Mbps */
+#define	USB_WIRELESS_PHY_53		(1 << 0)	/* always set */
+#define	USB_WIRELESS_PHY_80		(1 << 1)
+#define	USB_WIRELESS_PHY_107		(1 << 2)	/* always set */
+#define	USB_WIRELESS_PHY_160		(1 << 3)
+#define	USB_WIRELESS_PHY_200		(1 << 4)	/* always set */
+#define	USB_WIRELESS_PHY_320		(1 << 5)
+#define	USB_WIRELESS_PHY_400		(1 << 6)
+#define	USB_WIRELESS_PHY_480		(1 << 7)
+	__u8  bmTFITXPowerInfo;	/* TFI power levels */
+	__u8  bmFFITXPowerInfo;	/* FFI power levels */
+	__le16 bmBandGroup;
+	__u8  bReserved;
+} __attribute__((packed));
+
+/* USB 2.0 Extension descriptor */
+#define	USB_CAP_TYPE_EXT		2
+
+struct usb_ext_cap_descriptor {		/* Link Power Management */
+	__u8  bLength;
+	__u8  bDescriptorType;
+	__u8  bDevCapabilityType;
+	__le32 bmAttributes;
+#define USB_LPM_SUPPORT			(1 << 1)	/* supports LPM */
+#define USB_BESL_SUPPORT		(1 << 2)	/* supports BESL */
+#define USB_BESL_BASELINE_VALID		(1 << 3)	/* Baseline BESL valid*/
+#define USB_BESL_DEEP_VALID		(1 << 4)	/* Deep BESL valid */
+#define USB_GET_BESL_BASELINE(p)	(((p) & (0xf << 8)) >> 8)
+#define USB_GET_BESL_DEEP(p)		(((p) & (0xf << 12)) >> 12)
+} __attribute__((packed));
+
+#define USB_DT_USB_EXT_CAP_SIZE	7
+
+/*
+ * SuperSpeed USB Capability descriptor: Defines the set of SuperSpeed USB
+ * specific device level capabilities
+ */
+#define		USB_SS_CAP_TYPE		3
+struct usb_ss_cap_descriptor {		/* Link Power Management */
+	__u8  bLength;
+	__u8  bDescriptorType;
+	__u8  bDevCapabilityType;
+	__u8  bmAttributes;
+#define USB_LTM_SUPPORT			(1 << 1) /* supports LTM */
+	__le16 wSpeedSupported;
+#define USB_LOW_SPEED_OPERATION		(1)	 /* Low speed operation */
+#define USB_FULL_SPEED_OPERATION	(1 << 1) /* Full speed operation */
+#define USB_HIGH_SPEED_OPERATION	(1 << 2) /* High speed operation */
+#define USB_5GBPS_OPERATION		(1 << 3) /* Operation at 5Gbps */
+	__u8  bFunctionalitySupport;
+	__u8  bU1devExitLat;
+	__le16 bU2DevExitLat;
+} __attribute__((packed));
+
+#define USB_DT_USB_SS_CAP_SIZE	10
+
+/*
+ * Container ID Capability descriptor: Defines the instance unique ID used to
+ * identify the instance across all operating modes
+ */
+#define	CONTAINER_ID_TYPE	4
+struct usb_ss_container_id_descriptor {
+	__u8  bLength;
+	__u8  bDescriptorType;
+	__u8  bDevCapabilityType;
+	__u8  bReserved;
+	__u8  ContainerID[16]; /* 128-bit number */
+} __attribute__((packed));
+
+#define USB_DT_USB_SS_CONTN_ID_SIZE	20
+/*-------------------------------------------------------------------------*/
+
+/* USB_DT_WIRELESS_ENDPOINT_COMP:  companion descriptor associated with
+ * each endpoint descriptor for a wireless device
+ */
+struct usb_wireless_ep_comp_descriptor {
+	__u8  bLength;
+	__u8  bDescriptorType;
+
+	__u8  bMaxBurst;
+	__u8  bMaxSequence;
+	__le16 wMaxStreamDelay;
+	__le16 wOverTheAirPacketSize;
+	__u8  bOverTheAirInterval;
+	__u8  bmCompAttributes;
+#define USB_ENDPOINT_SWITCH_MASK	0x03	/* in bmCompAttributes */
+#define USB_ENDPOINT_SWITCH_NO		0
+#define USB_ENDPOINT_SWITCH_SWITCH	1
+#define USB_ENDPOINT_SWITCH_SCALE	2
+} __attribute__((packed));
+
+/*-------------------------------------------------------------------------*/
+
+/* USB_REQ_SET_HANDSHAKE is a four-way handshake used between a wireless
+ * host and a device for connection set up, mutual authentication, and
+ * exchanging short lived session keys.  The handshake depends on a CC.
+ */
+struct usb_handshake {
+	__u8 bMessageNumber;
+	__u8 bStatus;
+	__u8 tTKID[3];
+	__u8 bReserved;
+	__u8 CDID[16];
+	__u8 nonce[16];
+	__u8 MIC[8];
+} __attribute__((packed));
+
+/*-------------------------------------------------------------------------*/
+
+/* USB_REQ_SET_CONNECTION modifies or revokes a connection context (CC).
+ * A CC may also be set up using non-wireless secure channels (including
+ * wired USB!), and some devices may support CCs with multiple hosts.
+ */
+struct usb_connection_context {
+	__u8 CHID[16];		/* persistent host id */
+	__u8 CDID[16];		/* device id (unique w/in host context) */
+	__u8 CK[16];		/* connection key */
+} __attribute__((packed));
+
+/*-------------------------------------------------------------------------*/
+
+/* USB 2.0 defines three speeds, here's how Linux identifies them */
+
+enum usb_device_speed {
+	USB_SPEED_UNKNOWN = 0,			/* enumerating */
+	USB_SPEED_LOW, USB_SPEED_FULL,		/* usb 1.1 */
+	USB_SPEED_HIGH,				/* usb 2.0 */
+	USB_SPEED_WIRELESS,			/* wireless (usb 2.5) */
+	USB_SPEED_SUPER,			/* usb 3.0 */
+};
+
+#ifdef __KERNEL__
+
+/**
+ * usb_speed_string() - Returns human readable-name of the speed.
+ * @speed: The speed to return human-readable name for.  If it's not
+ *   any of the speeds defined in usb_device_speed enum, string for
+ *   USB_SPEED_UNKNOWN will be returned.
+ */
+extern const char *usb_speed_string(enum usb_device_speed speed);
+
+#endif
+
+enum usb_device_state {
+	/* NOTATTACHED isn't in the USB spec, and this state acts
+	 * the same as ATTACHED ... but it's clearer this way.
+	 */
+	USB_STATE_NOTATTACHED = 0,
+
+	/* chapter 9 and authentication (wireless) device states */
+	USB_STATE_ATTACHED,
+	USB_STATE_POWERED,			/* wired */
+	USB_STATE_RECONNECTING,			/* auth */
+	USB_STATE_UNAUTHENTICATED,		/* auth */
+	USB_STATE_DEFAULT,			/* limited function */
+	USB_STATE_ADDRESS,
+	USB_STATE_CONFIGURED,			/* most functions */
+
+	USB_STATE_SUSPENDED
+
+	/* NOTE:  there are actually four different SUSPENDED
+	 * states, returning to POWERED, DEFAULT, ADDRESS, or
+	 * CONFIGURED respectively when SOF tokens flow again.
+	 * At this level there's no difference between L1 and L2
+	 * suspend states.  (L2 being original USB 1.1 suspend.)
+	 */
+};
+
+enum usb3_link_state {
+	USB3_LPM_U0 = 0,
+	USB3_LPM_U1,
+	USB3_LPM_U2,
+	USB3_LPM_U3
+};
+
+/*
+ * A U1 timeout of 0x0 means the parent hub will reject any transitions to U1.
+ * 0xff means the parent hub will accept transitions to U1, but will not
+ * initiate a transition.
+ *
+ * A U1 timeout of 0x1 to 0x7F also causes the hub to initiate a transition to
+ * U1 after that many microseconds.  Timeouts of 0x80 to 0xFE are reserved
+ * values.
+ *
+ * A U2 timeout of 0x0 means the parent hub will reject any transitions to U2.
+ * 0xff means the parent hub will accept transitions to U2, but will not
+ * initiate a transition.
+ *
+ * A U2 timeout of 0x1 to 0xFE also causes the hub to initiate a transition to
+ * U2 after N*256 microseconds.  Therefore a U2 timeout value of 0x1 means a U2
+ * idle timer of 256 microseconds, 0x2 means 512 microseconds, 0xFE means
+ * 65.024ms.
+ */
+#define USB3_LPM_DISABLED		0x0
+#define USB3_LPM_U1_MAX_TIMEOUT		0x7F
+#define USB3_LPM_U2_MAX_TIMEOUT		0xFE
+#define USB3_LPM_DEVICE_INITIATED	0xFF
+
+struct usb_set_sel_req {
+	__u8	u1_sel;
+	__u8	u1_pel;
+	__le16	u2_sel;
+	__le16	u2_pel;
+} __attribute__ ((packed));
+
+/*
+ * The Set System Exit Latency control transfer provides one byte each for
+ * U1 SEL and U1 PEL, so the max exit latency is 0xFF.  U2 SEL and U2 PEL each
+ * are two bytes long.
+ */
+#define USB3_LPM_MAX_U1_SEL_PEL		0xFF
+#define USB3_LPM_MAX_U2_SEL_PEL		0xFFFF
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * As per USB compliance update, a device that is actively drawing
+ * more than 100mA from USB must report itself as bus-powered in
+ * the GetStatus(DEVICE) call.
+ * http://compliance.usb.org/index.asp?UpdateFile=Electrical&Format=Standard#34
+ */
+#define USB_SELF_POWER_VBUS_MAX_DRAW		100
+
+#endif /* __LINUX_USB_CH9_H */
diff --git a/qemu/roms/u-boot/include/linux/usb/composite.h b/qemu/roms/u-boot/include/linux/usb/composite.h
new file mode 100644
index 000000000..f833d1006
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/usb/composite.h
@@ -0,0 +1,338 @@
+/*
+ * composite.h -- framework for usb gadgets which are composite devices
+ *
+ * Copyright (C) 2006-2008 David Brownell
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef	__LINUX_USB_COMPOSITE_H
+#define	__LINUX_USB_COMPOSITE_H
+
+/*
+ * This framework is an optional layer on top of the USB Gadget interface,
+ * making it easier to build (a) Composite devices, supporting multiple
+ * functions within any single configuration, and (b) Multi-configuration
+ * devices, also supporting multiple functions but without necessarily
+ * having more than one function per configuration.
+ *
+ * Example:  a device with a single configuration supporting both network
+ * link and mass storage functions is a composite device.  Those functions
+ * might alternatively be packaged in individual configurations, but in
+ * the composite model the host can use both functions at the same time.
+ */
+
+#include <common.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <usb/lin_gadget_compat.h>
+
+struct usb_configuration;
+
+/**
+ * struct usb_function - describes one function of a configuration
+ * @name: For diagnostics, identifies the function.
+ * @strings: tables of strings, keyed by identifiers assigned during bind()
+ *	and by language IDs provided in control requests
+ * @descriptors: Table of full (or low) speed descriptors, using interface and
+ *	string identifiers assigned during @bind().  If this pointer is null,
+ *	the function will not be available at full speed (or at low speed).
+ * @hs_descriptors: Table of high speed descriptors, using interface and
+ *	string identifiers assigned during @bind().  If this pointer is null,
+ *	the function will not be available at high speed.
+ * @config: assigned when @usb_add_function() is called; this is the
+ *	configuration with which this function is associated.
+ * @bind: Before the gadget can register, all of its functions bind() to the
+ *	available resources including string and interface identifiers used
+ *	in interface or class descriptors; endpoints; I/O buffers; and so on.
+ * @unbind: Reverses @bind; called as a side effect of unregistering the
+ *	driver which added this function.
+ * @set_alt: (REQUIRED) Reconfigures altsettings; function drivers may
+ *	initialize usb_ep.driver data at this time (when it is used).
+ *	Note that setting an interface to its current altsetting resets
+ *	interface state, and that all interfaces have a disabled state.
+ * @get_alt: Returns the active altsetting.  If this is not provided,
+ *	then only altsetting zero is supported.
+ * @disable: (REQUIRED) Indicates the function should be disabled.  Reasons
+ *	include host resetting or reconfiguring the gadget, and disconnection.
+ * @setup: Used for interface-specific control requests.
+ * @suspend: Notifies functions when the host stops sending USB traffic.
+ * @resume: Notifies functions when the host restarts USB traffic.
+ *
+ * A single USB function uses one or more interfaces, and should in most
+ * cases support operation at both full and high speeds.  Each function is
+ * associated by @usb_add_function() with a one configuration; that function
+ * causes @bind() to be called so resources can be allocated as part of
+ * setting up a gadget driver.  Those resources include endpoints, which
+ * should be allocated using @usb_ep_autoconfig().
+ *
+ * To support dual speed operation, a function driver provides descriptors
+ * for both high and full speed operation.  Except in rare cases that don't
+ * involve bulk endpoints, each speed needs different endpoint descriptors.
+ *
+ * Function drivers choose their own strategies for managing instance data.
+ * The simplest strategy just declares it "static', which means the function
+ * can only be activated once.  If the function needs to be exposed in more
+ * than one configuration at a given speed, it needs to support multiple
+ * usb_function structures (one for each configuration).
+ *
+ * A more complex strategy might encapsulate a @usb_function structure inside
+ * a driver-specific instance structure to allows multiple activations.  An
+ * example of multiple activations might be a CDC ACM function that supports
+ * two or more distinct instances within the same configuration, providing
+ * several independent logical data links to a USB host.
+ */
+struct usb_function {
+	const char			*name;
+	struct usb_gadget_strings	**strings;
+	struct usb_descriptor_header	**descriptors;
+	struct usb_descriptor_header	**hs_descriptors;
+
+	struct usb_configuration	*config;
+
+	/* REVISIT:  bind() functions can be marked __init, which
+	 * makes trouble for section mismatch analysis.  See if
+	 * we can't restructure things to avoid mismatching.
+	 * Related:  unbind() may kfree() but bind() won't...
+	 */
+
+	/* configuration management:  bind/unbind */
+	int			(*bind)(struct usb_configuration *,
+					struct usb_function *);
+	void			(*unbind)(struct usb_configuration *,
+					struct usb_function *);
+
+	/* runtime state management */
+	int			(*set_alt)(struct usb_function *,
+					unsigned interface, unsigned alt);
+	int			(*get_alt)(struct usb_function *,
+					unsigned interface);
+	void			(*disable)(struct usb_function *);
+	int			(*setup)(struct usb_function *,
+					const struct usb_ctrlrequest *);
+	void			(*suspend)(struct usb_function *);
+	void			(*resume)(struct usb_function *);
+
+	/* private: */
+	/* internals */
+	struct list_head		list;
+	DECLARE_BITMAP(endpoints, 32);
+};
+
+int usb_add_function(struct usb_configuration *, struct usb_function *);
+
+int usb_function_deactivate(struct usb_function *);
+int usb_function_activate(struct usb_function *);
+
+int usb_interface_id(struct usb_configuration *, struct usb_function *);
+
+/**
+ * ep_choose - select descriptor endpoint at current device speed
+ * @g: gadget, connected and running at some speed
+ * @hs: descriptor to use for high speed operation
+ * @fs: descriptor to use for full or low speed operation
+ */
+static inline struct usb_endpoint_descriptor *
+ep_choose(struct usb_gadget *g, struct usb_endpoint_descriptor *hs,
+		struct usb_endpoint_descriptor *fs)
+{
+	if (gadget_is_dualspeed(g) && g->speed == USB_SPEED_HIGH)
+		return hs;
+	return fs;
+}
+
+#define	MAX_CONFIG_INTERFACES		16	/* arbitrary; max 255 */
+
+/**
+ * struct usb_configuration - represents one gadget configuration
+ * @label: For diagnostics, describes the configuration.
+ * @strings: Tables of strings, keyed by identifiers assigned during @bind()
+ *	and by language IDs provided in control requests.
+ * @descriptors: Table of descriptors preceding all function descriptors.
+ *	Examples include OTG and vendor-specific descriptors.
+ * @bind: Called from @usb_add_config() to allocate resources unique to this
+ *	configuration and to call @usb_add_function() for each function used.
+ * @unbind: Reverses @bind; called as a side effect of unregistering the
+ *	driver which added this configuration.
+ * @setup: Used to delegate control requests that aren't handled by standard
+ *	device infrastructure or directed at a specific interface.
+ * @bConfigurationValue: Copied into configuration descriptor.
+ * @iConfiguration: Copied into configuration descriptor.
+ * @bmAttributes: Copied into configuration descriptor.
+ * @bMaxPower: Copied into configuration descriptor.
+ * @cdev: assigned by @usb_add_config() before calling @bind(); this is
+ *	the device associated with this configuration.
+ *
+ * Configurations are building blocks for gadget drivers structured around
+ * function drivers.  Simple USB gadgets require only one function and one
+ * configuration, and handle dual-speed hardware by always providing the same
+ * functionality.  Slightly more complex gadgets may have more than one
+ * single-function configuration at a given speed; or have configurations
+ * that only work at one speed.
+ *
+ * Composite devices are, by definition, ones with configurations which
+ * include more than one function.
+ *
+ * The lifecycle of a usb_configuration includes allocation, initialization
+ * of the fields described above, and calling @usb_add_config() to set up
+ * internal data and bind it to a specific device.  The configuration's
+ * @bind() method is then used to initialize all the functions and then
+ * call @usb_add_function() for them.
+ *
+ * Those functions would normally be independant of each other, but that's
+ * not mandatory.  CDC WMC devices are an example where functions often
+ * depend on other functions, with some functions subsidiary to others.
+ * Such interdependency may be managed in any way, so long as all of the
+ * descriptors complete by the time the composite driver returns from
+ * its bind() routine.
+ */
+struct usb_configuration {
+	const char			*label;
+	struct usb_gadget_strings	**strings;
+	const struct usb_descriptor_header **descriptors;
+
+	/* REVISIT:  bind() functions can be marked __init, which
+	 * makes trouble for section mismatch analysis.  See if
+	 * we can't restructure things to avoid mismatching...
+	 */
+
+	/* configuration management:  bind/unbind */
+	int			(*bind)(struct usb_configuration *);
+	void			(*unbind)(struct usb_configuration *);
+	int			(*setup)(struct usb_configuration *,
+					const struct usb_ctrlrequest *);
+
+	/* fields in the config descriptor */
+	u8			bConfigurationValue;
+	u8			iConfiguration;
+	u8			bmAttributes;
+	u8			bMaxPower;
+
+	struct usb_composite_dev	*cdev;
+
+	/* private: */
+	/* internals */
+	struct list_head	list;
+	struct list_head	functions;
+	u8			next_interface_id;
+	unsigned		highspeed:1;
+	unsigned		fullspeed:1;
+	struct usb_function	*interface[MAX_CONFIG_INTERFACES];
+};
+
+int usb_add_config(struct usb_composite_dev *,
+		struct usb_configuration *);
+
+/**
+ * struct usb_composite_driver - groups configurations into a gadget
+ * @name: For diagnostics, identifies the driver.
+ * @dev: Template descriptor for the device, including default device
+ *	identifiers.
+ * @strings: tables of strings, keyed by identifiers assigned during bind()
+ *	and language IDs provided in control requests
+ * @bind: (REQUIRED) Used to allocate resources that are shared across the
+ *	whole device, such as string IDs, and add its configurations using
+ *	@usb_add_config().  This may fail by returning a negative errno
+ *	value; it should return zero on successful initialization.
+ * @unbind: Reverses @bind(); called as a side effect of unregistering
+ *	this driver.
+ * @disconnect: optional driver disconnect method
+ * @suspend: Notifies when the host stops sending USB traffic,
+ *	after function notifications
+ * @resume: Notifies configuration when the host restarts USB traffic,
+ *	before function notifications
+ *
+ * Devices default to reporting self powered operation.  Devices which rely
+ * on bus powered operation should report this in their @bind() method.
+ *
+ * Before returning from @bind, various fields in the template descriptor
+ * may be overridden.  These include the idVendor/idProduct/bcdDevice values
+ * normally to bind the appropriate host side driver, and the three strings
+ * (iManufacturer, iProduct, iSerialNumber) normally used to provide user
+ * meaningful device identifiers.  (The strings will not be defined unless
+ * they are defined in @dev and @strings.)  The correct ep0 maxpacket size
+ * is also reported, as defined by the underlying controller driver.
+ */
+struct usb_composite_driver {
+	const char				*name;
+	const struct usb_device_descriptor	*dev;
+	struct usb_gadget_strings		**strings;
+
+	/* REVISIT:  bind() functions can be marked __init, which
+	 * makes trouble for section mismatch analysis.  See if
+	 * we can't restructure things to avoid mismatching...
+	 */
+
+	int			(*bind)(struct usb_composite_dev *);
+	int			(*unbind)(struct usb_composite_dev *);
+
+	void			(*disconnect)(struct usb_composite_dev *);
+
+	/* global suspend hooks */
+	void			(*suspend)(struct usb_composite_dev *);
+	void			(*resume)(struct usb_composite_dev *);
+};
+
+extern int usb_composite_register(struct usb_composite_driver *);
+extern void usb_composite_unregister(struct usb_composite_driver *);
+
+
+/**
+ * struct usb_composite_device - represents one composite usb gadget
+ * @gadget: read-only, abstracts the gadget's usb peripheral controller
+ * @req: used for control responses; buffer is pre-allocated
+ * @bufsiz: size of buffer pre-allocated in @req
+ * @config: the currently active configuration
+ *
+ * One of these devices is allocated and initialized before the
+ * associated device driver's bind() is called.
+ *
+ * OPEN ISSUE:  it appears that some WUSB devices will need to be
+ * built by combining a normal (wired) gadget with a wireless one.
+ * This revision of the gadget framework should probably try to make
+ * sure doing that won't hurt too much.
+ *
+ * One notion for how to handle Wireless USB devices involves:
+ * (a) a second gadget here, discovery mechanism TBD, but likely
+ *     needing separate "register/unregister WUSB gadget" calls;
+ * (b) updates to usb_gadget to include flags "is it wireless",
+ *     "is it wired", plus (presumably in a wrapper structure)
+ *     bandgroup and PHY info;
+ * (c) presumably a wireless_ep wrapping a usb_ep, and reporting
+ *     wireless-specific parameters like maxburst and maxsequence;
+ * (d) configurations that are specific to wireless links;
+ * (e) function drivers that understand wireless configs and will
+ *     support wireless for (additional) function instances;
+ * (f) a function to support association setup (like CBAF), not
+ *     necessarily requiring a wireless adapter;
+ * (g) composite device setup that can create one or more wireless
+ *     configs, including appropriate association setup support;
+ * (h) more, TBD.
+ */
+struct usb_composite_dev {
+	struct usb_gadget		*gadget;
+	struct usb_request		*req;
+	unsigned			bufsiz;
+
+	struct usb_configuration	*config;
+
+	/* private: */
+	/* internals */
+	unsigned int			suspended:1;
+	struct usb_device_descriptor __aligned(CONFIG_SYS_CACHELINE_SIZE) desc;
+	struct list_head		configs;
+	struct usb_composite_driver	*driver;
+	u8				next_string_id;
+
+	/* the gadget driver won't enable the data pullup
+	 * while the deactivation count is nonzero.
+	 */
+	unsigned			deactivations;
+};
+
+extern int usb_string_id(struct usb_composite_dev *c);
+extern int usb_string_ids_tab(struct usb_composite_dev *c,
+			      struct usb_string *str);
+extern int usb_string_ids_n(struct usb_composite_dev *c, unsigned n);
+
+#endif	/* __LINUX_USB_COMPOSITE_H */
diff --git a/qemu/roms/u-boot/include/linux/usb/dwc3.h b/qemu/roms/u-boot/include/linux/usb/dwc3.h
new file mode 100644
index 000000000..97d179a6e
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/usb/dwc3.h
@@ -0,0 +1,188 @@
+/* include/linux/usb/dwc3.h
+ *
+ * Copyright (c) 2012 Samsung Electronics Co. Ltd
+ *
+ * Designware SuperSpeed USB 3.0 DRD Controller global and OTG registers
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DWC3_H_
+#define __DWC3_H_
+
+/* Global constants */
+#define DWC3_ENDPOINTS_NUM			32
+
+#define DWC3_EVENT_BUFFERS_SIZE			PAGE_SIZE
+#define DWC3_EVENT_TYPE_MASK			0xfe
+
+#define DWC3_EVENT_TYPE_DEV			0
+#define DWC3_EVENT_TYPE_CARKIT			3
+#define DWC3_EVENT_TYPE_I2C			4
+
+#define DWC3_DEVICE_EVENT_DISCONNECT		0
+#define DWC3_DEVICE_EVENT_RESET			1
+#define DWC3_DEVICE_EVENT_CONNECT_DONE		2
+#define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE	3
+#define DWC3_DEVICE_EVENT_WAKEUP		4
+#define DWC3_DEVICE_EVENT_EOPF			6
+#define DWC3_DEVICE_EVENT_SOF			7
+#define DWC3_DEVICE_EVENT_ERRATIC_ERROR		9
+#define DWC3_DEVICE_EVENT_CMD_CMPL		10
+#define DWC3_DEVICE_EVENT_OVERFLOW		11
+
+#define DWC3_GEVNTCOUNT_MASK			0xfffc
+#define DWC3_GSNPSID_MASK			0xffff0000
+#define DWC3_GSNPSID_SHIFT			16
+#define DWC3_GSNPSREV_MASK			0xffff
+
+#define DWC3_REVISION_MASK			0xffff
+
+#define DWC3_REG_OFFSET				0xC100
+
+struct g_event_buffer {
+	u64 g_evntadr;
+	u32 g_evntsiz;
+	u32 g_evntcount;
+};
+
+struct d_physical_endpoint {
+	u32 d_depcmdpar2;
+	u32 d_depcmdpar1;
+	u32 d_depcmdpar0;
+	u32 d_depcmd;
+};
+
+struct dwc3 {					/* offset: 0xC100 */
+	u32 g_sbuscfg0;
+	u32 g_sbuscfg1;
+	u32 g_txthrcfg;
+	u32 g_rxthrcfg;
+	u32 g_ctl;
+
+	u32 reserved1;
+
+	u32 g_sts;
+
+	u32 reserved2;
+
+	u32 g_snpsid;
+	u32 g_gpio;
+	u32 g_uid;
+	u32 g_uctl;
+	u64 g_buserraddr;
+	u64 g_prtbimap;
+
+	u32 g_hwparams0;
+	u32 g_hwparams1;
+	u32 g_hwparams2;
+	u32 g_hwparams3;
+	u32 g_hwparams4;
+	u32 g_hwparams5;
+	u32 g_hwparams6;
+	u32 g_hwparams7;
+
+	u32 g_dbgfifospace;
+	u32 g_dbgltssm;
+	u32 g_dbglnmcc;
+	u32 g_dbgbmu;
+	u32 g_dbglspmux;
+	u32 g_dbglsp;
+	u32 g_dbgepinfo0;
+	u32 g_dbgepinfo1;
+
+	u64 g_prtbimap_hs;
+	u64 g_prtbimap_fs;
+
+	u32 reserved3[28];
+
+	u32 g_usb2phycfg[16];
+	u32 g_usb2i2cctl[16];
+	u32 g_usb2phyacc[16];
+	u32 g_usb3pipectl[16];
+
+	u32 g_txfifosiz[32];
+	u32 g_rxfifosiz[32];
+
+	struct g_event_buffer g_evnt_buf[32];
+
+	u32 g_hwparams8;
+
+	u32 reserved4[63];
+
+	u32 d_cfg;
+	u32 d_ctl;
+	u32 d_evten;
+	u32 d_sts;
+	u32 d_gcmdpar;
+	u32 d_gcmd;
+
+	u32 reserved5[2];
+
+	u32 d_alepena;
+
+	u32 reserved6[55];
+
+	struct d_physical_endpoint d_phy_ep_cmd[32];
+
+	u32 reserved7[128];
+
+	u32 o_cfg;
+	u32 o_ctl;
+	u32 o_evt;
+	u32 o_evten;
+	u32 o_sts;
+
+	u32 reserved8[3];
+
+	u32 adp_cfg;
+	u32 adp_ctl;
+	u32 adp_evt;
+	u32 adp_evten;
+
+	u32 bc_cfg;
+
+	u32 reserved9;
+
+	u32 bc_evt;
+	u32 bc_evten;
+};
+
+/* Global Configuration Register */
+#define DWC3_GCTL_PWRDNSCALE(n)			((n) << 19)
+#define DWC3_GCTL_U2RSTECN			(1 << 16)
+#define DWC3_GCTL_RAMCLKSEL(x)			\
+		(((x) & DWC3_GCTL_CLK_MASK) << 6)
+#define DWC3_GCTL_CLK_BUS			(0)
+#define DWC3_GCTL_CLK_PIPE			(1)
+#define DWC3_GCTL_CLK_PIPEHALF			(2)
+#define DWC3_GCTL_CLK_MASK			(3)
+#define DWC3_GCTL_PRTCAP(n)			(((n) & (3 << 12)) >> 12)
+#define DWC3_GCTL_PRTCAPDIR(n)			((n) << 12)
+#define DWC3_GCTL_PRTCAP_HOST			1
+#define DWC3_GCTL_PRTCAP_DEVICE			2
+#define DWC3_GCTL_PRTCAP_OTG			3
+#define DWC3_GCTL_CORESOFTRESET			(1 << 11)
+#define DWC3_GCTL_SCALEDOWN(n)			((n) << 4)
+#define DWC3_GCTL_SCALEDOWN_MASK		DWC3_GCTL_SCALEDOWN(3)
+#define DWC3_GCTL_DISSCRAMBLE			(1 << 3)
+#define DWC3_GCTL_DSBLCLKGTNG			(1 << 0)
+
+/* Global HWPARAMS1 Register */
+#define DWC3_GHWPARAMS1_EN_PWROPT(n)		(((n) & (3 << 24)) >> 24)
+#define DWC3_GHWPARAMS1_EN_PWROPT_NO		0
+#define DWC3_GHWPARAMS1_EN_PWROPT_CLK		1
+
+/* Global USB2 PHY Configuration Register */
+#define DWC3_GUSB2PHYCFG_PHYSOFTRST		(1 << 31)
+#define DWC3_GUSB2PHYCFG_SUSPHY			(1 << 6)
+
+/* Global USB3 PIPE Control Register */
+#define DWC3_GUSB3PIPECTL_PHYSOFTRST		(1 << 31)
+#define DWC3_GUSB3PIPECTL_SUSPHY		(1 << 17)
+
+/* Global TX Fifo Size Register */
+#define DWC3_GTXFIFOSIZ_TXFDEF(n)		((n) & 0xffff)
+#define DWC3_GTXFIFOSIZ_TXFSTADDR(n)		((n) & 0xffff0000)
+
+#endif /* __DWC3_H_ */
diff --git a/qemu/roms/u-boot/include/linux/usb/gadget.h b/qemu/roms/u-boot/include/linux/usb/gadget.h
new file mode 100644
index 000000000..a8a576316
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/usb/gadget.h
@@ -0,0 +1,864 @@
+/*
+ * <linux/usb/gadget.h>
+ *
+ * We call the USB code inside a Linux-based peripheral device a "gadget"
+ * driver, except for the hardware-specific bus glue.  One USB host can
+ * master many USB gadgets, but the gadgets are only slaved to one host.
+ *
+ *
+ * (C) Copyright 2002-2004 by David Brownell
+ * All Rights Reserved.
+ *
+ * This software is licensed under the GNU GPL version 2.
+ *
+ * Ported to U-boot by: Thomas Smits <ts.smits@gmail.com> and
+ *                      Remy Bohmer <linux@bohmer.net>
+ */
+
+#ifndef __LINUX_USB_GADGET_H
+#define __LINUX_USB_GADGET_H
+
+#include <errno.h>
+#include <linux/list.h>
+
+struct usb_ep;
+
+/**
+ * struct usb_request - describes one i/o request
+ * @buf: Buffer used for data.  Always provide this; some controllers
+ *	only use PIO, or don't use DMA for some endpoints.
+ * @dma: DMA address corresponding to 'buf'.  If you don't set this
+ *	field, and the usb controller needs one, it is responsible
+ *	for mapping and unmapping the buffer.
+ * @length: Length of that data
+ * @no_interrupt: If true, hints that no completion irq is needed.
+ *	Helpful sometimes with deep request queues that are handled
+ *	directly by DMA controllers.
+ * @zero: If true, when writing data, makes the last packet be "short"
+ *     by adding a zero length packet as needed;
+ * @short_not_ok: When reading data, makes short packets be
+ *     treated as errors (queue stops advancing till cleanup).
+ * @complete: Function called when request completes, so this request and
+ *	its buffer may be re-used.
+ *	Reads terminate with a short packet, or when the buffer fills,
+ *	whichever comes first.  When writes terminate, some data bytes
+ *	will usually still be in flight (often in a hardware fifo).
+ *	Errors (for reads or writes) stop the queue from advancing
+ *	until the completion function returns, so that any transfers
+ *	invalidated by the error may first be dequeued.
+ * @context: For use by the completion callback
+ * @list: For use by the gadget driver.
+ * @status: Reports completion code, zero or a negative errno.
+ *	Normally, faults block the transfer queue from advancing until
+ *	the completion callback returns.
+ *	Code "-ESHUTDOWN" indicates completion caused by device disconnect,
+ *	or when the driver disabled the endpoint.
+ * @actual: Reports bytes transferred to/from the buffer.  For reads (OUT
+ *	transfers) this may be less than the requested length.  If the
+ *	short_not_ok flag is set, short reads are treated as errors
+ *	even when status otherwise indicates successful completion.
+ *	Note that for writes (IN transfers) some data bytes may still
+ *	reside in a device-side FIFO when the request is reported as
+ *	complete.
+ *
+ * These are allocated/freed through the endpoint they're used with.  The
+ * hardware's driver can add extra per-request data to the memory it returns,
+ * which often avoids separate memory allocations (potential failures),
+ * later when the request is queued.
+ *
+ * Request flags affect request handling, such as whether a zero length
+ * packet is written (the "zero" flag), whether a short read should be
+ * treated as an error (blocking request queue advance, the "short_not_ok"
+ * flag), or hinting that an interrupt is not required (the "no_interrupt"
+ * flag, for use with deep request queues).
+ *
+ * Bulk endpoints can use any size buffers, and can also be used for interrupt
+ * transfers. interrupt-only endpoints can be much less functional.
+ *
+ * NOTE:  this is analagous to 'struct urb' on the host side, except that
+ * it's thinner and promotes more pre-allocation.
+ */
+
+struct usb_request {
+	void			*buf;
+	unsigned		length;
+	dma_addr_t		dma;
+
+	unsigned		no_interrupt:1;
+	unsigned		zero:1;
+	unsigned		short_not_ok:1;
+
+	void			(*complete)(struct usb_ep *ep,
+					struct usb_request *req);
+	void			*context;
+	struct list_head	list;
+
+	int			status;
+	unsigned		actual;
+};
+
+/*-------------------------------------------------------------------------*/
+
+/* endpoint-specific parts of the api to the usb controller hardware.
+ * unlike the urb model, (de)multiplexing layers are not required.
+ * (so this api could slash overhead if used on the host side...)
+ *
+ * note that device side usb controllers commonly differ in how many
+ * endpoints they support, as well as their capabilities.
+ */
+struct usb_ep_ops {
+	int (*enable) (struct usb_ep *ep,
+		const struct usb_endpoint_descriptor *desc);
+	int (*disable) (struct usb_ep *ep);
+
+	struct usb_request *(*alloc_request) (struct usb_ep *ep,
+		gfp_t gfp_flags);
+	void (*free_request) (struct usb_ep *ep, struct usb_request *req);
+
+	int (*queue) (struct usb_ep *ep, struct usb_request *req,
+		gfp_t gfp_flags);
+	int (*dequeue) (struct usb_ep *ep, struct usb_request *req);
+
+	int (*set_halt) (struct usb_ep *ep, int value);
+	int (*fifo_status) (struct usb_ep *ep);
+	void (*fifo_flush) (struct usb_ep *ep);
+};
+
+/**
+ * struct usb_ep - device side representation of USB endpoint
+ * @name:identifier for the endpoint, such as "ep-a" or "ep9in-bulk"
+ * @ops: Function pointers used to access hardware-specific operations.
+ * @ep_list:the gadget's ep_list holds all of its endpoints
+ * @maxpacket:The maximum packet size used on this endpoint.  The initial
+ *	value can sometimes be reduced (hardware allowing), according to
+ *      the endpoint descriptor used to configure the endpoint.
+ * @driver_data:for use by the gadget driver.  all other fields are
+ *	read-only to gadget drivers.
+ *
+ * the bus controller driver lists all the general purpose endpoints in
+ * gadget->ep_list.  the control endpoint (gadget->ep0) is not in that list,
+ * and is accessed only in response to a driver setup() callback.
+ */
+struct usb_ep {
+	void			*driver_data;
+	const char		*name;
+	const struct usb_ep_ops	*ops;
+	struct list_head	ep_list;
+	unsigned		maxpacket:16;
+};
+
+/*-------------------------------------------------------------------------*/
+
+/**
+ * usb_ep_enable - configure endpoint, making it usable
+ * @ep:the endpoint being configured.  may not be the endpoint named "ep0".
+ *	drivers discover endpoints through the ep_list of a usb_gadget.
+ * @desc:descriptor for desired behavior.  caller guarantees this pointer
+ *	remains valid until the endpoint is disabled; the data byte order
+ *	is little-endian (usb-standard).
+ *
+ * when configurations are set, or when interface settings change, the driver
+ * will enable or disable the relevant endpoints.  while it is enabled, an
+ * endpoint may be used for i/o until the driver receives a disconnect() from
+ * the host or until the endpoint is disabled.
+ *
+ * the ep0 implementation (which calls this routine) must ensure that the
+ * hardware capabilities of each endpoint match the descriptor provided
+ * for it.  for example, an endpoint named "ep2in-bulk" would be usable
+ * for interrupt transfers as well as bulk, but it likely couldn't be used
+ * for iso transfers or for endpoint 14.  some endpoints are fully
+ * configurable, with more generic names like "ep-a".  (remember that for
+ * USB, "in" means "towards the USB master".)
+ *
+ * returns zero, or a negative error code.
+ */
+static inline int usb_ep_enable(struct usb_ep *ep,
+				const struct usb_endpoint_descriptor *desc)
+{
+	return ep->ops->enable(ep, desc);
+}
+
+/**
+ * usb_ep_disable - endpoint is no longer usable
+ * @ep:the endpoint being unconfigured.  may not be the endpoint named "ep0".
+ *
+ * no other task may be using this endpoint when this is called.
+ * any pending and uncompleted requests will complete with status
+ * indicating disconnect (-ESHUTDOWN) before this call returns.
+ * gadget drivers must call usb_ep_enable() again before queueing
+ * requests to the endpoint.
+ *
+ * returns zero, or a negative error code.
+ */
+static inline int usb_ep_disable(struct usb_ep *ep)
+{
+	return ep->ops->disable(ep);
+}
+
+/**
+ * usb_ep_alloc_request - allocate a request object to use with this endpoint
+ * @ep:the endpoint to be used with with the request
+ * @gfp_flags:GFP_* flags to use
+ *
+ * Request objects must be allocated with this call, since they normally
+ * need controller-specific setup and may even need endpoint-specific
+ * resources such as allocation of DMA descriptors.
+ * Requests may be submitted with usb_ep_queue(), and receive a single
+ * completion callback.  Free requests with usb_ep_free_request(), when
+ * they are no longer needed.
+ *
+ * Returns the request, or null if one could not be allocated.
+ */
+static inline struct usb_request *usb_ep_alloc_request(struct usb_ep *ep,
+						       gfp_t gfp_flags)
+{
+	return ep->ops->alloc_request(ep, gfp_flags);
+}
+
+/**
+ * usb_ep_free_request - frees a request object
+ * @ep:the endpoint associated with the request
+ * @req:the request being freed
+ *
+ * Reverses the effect of usb_ep_alloc_request().
+ * Caller guarantees the request is not queued, and that it will
+ * no longer be requeued (or otherwise used).
+ */
+static inline void usb_ep_free_request(struct usb_ep *ep,
+				       struct usb_request *req)
+{
+	ep->ops->free_request(ep, req);
+}
+
+/**
+ * usb_ep_queue - queues (submits) an I/O request to an endpoint.
+ * @ep:the endpoint associated with the request
+ * @req:the request being submitted
+ * @gfp_flags: GFP_* flags to use in case the lower level driver couldn't
+ *	pre-allocate all necessary memory with the request.
+ *
+ * This tells the device controller to perform the specified request through
+ * that endpoint (reading or writing a buffer).  When the request completes,
+ * including being canceled by usb_ep_dequeue(), the request's completion
+ * routine is called to return the request to the driver.  Any endpoint
+ * (except control endpoints like ep0) may have more than one transfer
+ * request queued; they complete in FIFO order.  Once a gadget driver
+ * submits a request, that request may not be examined or modified until it
+ * is given back to that driver through the completion callback.
+ *
+ * Each request is turned into one or more packets.  The controller driver
+ * never merges adjacent requests into the same packet.  OUT transfers
+ * will sometimes use data that's already buffered in the hardware.
+ * Drivers can rely on the fact that the first byte of the request's buffer
+ * always corresponds to the first byte of some USB packet, for both
+ * IN and OUT transfers.
+ *
+ * Bulk endpoints can queue any amount of data; the transfer is packetized
+ * automatically.  The last packet will be short if the request doesn't fill it
+ * out completely.  Zero length packets (ZLPs) should be avoided in portable
+ * protocols since not all usb hardware can successfully handle zero length
+ * packets.  (ZLPs may be explicitly written, and may be implicitly written if
+ * the request 'zero' flag is set.)  Bulk endpoints may also be used
+ * for interrupt transfers; but the reverse is not true, and some endpoints
+ * won't support every interrupt transfer.  (Such as 768 byte packets.)
+ *
+ * Interrupt-only endpoints are less functional than bulk endpoints, for
+ * example by not supporting queueing or not handling buffers that are
+ * larger than the endpoint's maxpacket size.  They may also treat data
+ * toggle differently.
+ *
+ * Control endpoints ... after getting a setup() callback, the driver queues
+ * one response (even if it would be zero length).  That enables the
+ * status ack, after transfering data as specified in the response.  Setup
+ * functions may return negative error codes to generate protocol stalls.
+ * (Note that some USB device controllers disallow protocol stall responses
+ * in some cases.)  When control responses are deferred (the response is
+ * written after the setup callback returns), then usb_ep_set_halt() may be
+ * used on ep0 to trigger protocol stalls.
+ *
+ * For periodic endpoints, like interrupt or isochronous ones, the usb host
+ * arranges to poll once per interval, and the gadget driver usually will
+ * have queued some data to transfer at that time.
+ *
+ * Returns zero, or a negative error code.  Endpoints that are not enabled
+ * report errors; errors will also be
+ * reported when the usb peripheral is disconnected.
+ */
+static inline int usb_ep_queue(struct usb_ep *ep,
+			       struct usb_request *req, gfp_t gfp_flags)
+{
+	return ep->ops->queue(ep, req, gfp_flags);
+}
+
+/**
+ * usb_ep_dequeue - dequeues (cancels, unlinks) an I/O request from an endpoint
+ * @ep:the endpoint associated with the request
+ * @req:the request being canceled
+ *
+ * if the request is still active on the endpoint, it is dequeued and its
+ * completion routine is called (with status -ECONNRESET); else a negative
+ * error code is returned.
+ *
+ * note that some hardware can't clear out write fifos (to unlink the request
+ * at the head of the queue) except as part of disconnecting from usb.  such
+ * restrictions prevent drivers from supporting configuration changes,
+ * even to configuration zero (a "chapter 9" requirement).
+ */
+static inline int usb_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
+{
+	return ep->ops->dequeue(ep, req);
+}
+
+/**
+ * usb_ep_set_halt - sets the endpoint halt feature.
+ * @ep: the non-isochronous endpoint being stalled
+ *
+ * Use this to stall an endpoint, perhaps as an error report.
+ * Except for control endpoints,
+ * the endpoint stays halted (will not stream any data) until the host
+ * clears this feature; drivers may need to empty the endpoint's request
+ * queue first, to make sure no inappropriate transfers happen.
+ *
+ * Note that while an endpoint CLEAR_FEATURE will be invisible to the
+ * gadget driver, a SET_INTERFACE will not be.  To reset endpoints for the
+ * current altsetting, see usb_ep_clear_halt().  When switching altsettings,
+ * it's simplest to use usb_ep_enable() or usb_ep_disable() for the endpoints.
+ *
+ * Returns zero, or a negative error code.  On success, this call sets
+ * underlying hardware state that blocks data transfers.
+ * Attempts to halt IN endpoints will fail (returning -EAGAIN) if any
+ * transfer requests are still queued, or if the controller hardware
+ * (usually a FIFO) still holds bytes that the host hasn't collected.
+ */
+static inline int usb_ep_set_halt(struct usb_ep *ep)
+{
+	return ep->ops->set_halt(ep, 1);
+}
+
+/**
+ * usb_ep_clear_halt - clears endpoint halt, and resets toggle
+ * @ep:the bulk or interrupt endpoint being reset
+ *
+ * Use this when responding to the standard usb "set interface" request,
+ * for endpoints that aren't reconfigured, after clearing any other state
+ * in the endpoint's i/o queue.
+ *
+ * Returns zero, or a negative error code.  On success, this call clears
+ * the underlying hardware state reflecting endpoint halt and data toggle.
+ * Note that some hardware can't support this request (like pxa2xx_udc),
+ * and accordingly can't correctly implement interface altsettings.
+ */
+static inline int usb_ep_clear_halt(struct usb_ep *ep)
+{
+	return ep->ops->set_halt(ep, 0);
+}
+
+/**
+ * usb_ep_fifo_status - returns number of bytes in fifo, or error
+ * @ep: the endpoint whose fifo status is being checked.
+ *
+ * FIFO endpoints may have "unclaimed data" in them in certain cases,
+ * such as after aborted transfers.  Hosts may not have collected all
+ * the IN data written by the gadget driver (and reported by a request
+ * completion).  The gadget driver may not have collected all the data
+ * written OUT to it by the host.  Drivers that need precise handling for
+ * fault reporting or recovery may need to use this call.
+ *
+ * This returns the number of such bytes in the fifo, or a negative
+ * errno if the endpoint doesn't use a FIFO or doesn't support such
+ * precise handling.
+ */
+static inline int usb_ep_fifo_status(struct usb_ep *ep)
+{
+	if (ep->ops->fifo_status)
+		return ep->ops->fifo_status(ep);
+	else
+		return -EOPNOTSUPP;
+}
+
+/**
+ * usb_ep_fifo_flush - flushes contents of a fifo
+ * @ep: the endpoint whose fifo is being flushed.
+ *
+ * This call may be used to flush the "unclaimed data" that may exist in
+ * an endpoint fifo after abnormal transaction terminations.  The call
+ * must never be used except when endpoint is not being used for any
+ * protocol translation.
+ */
+static inline void usb_ep_fifo_flush(struct usb_ep *ep)
+{
+	if (ep->ops->fifo_flush)
+		ep->ops->fifo_flush(ep);
+}
+
+
+/*-------------------------------------------------------------------------*/
+
+struct usb_gadget;
+
+/* the rest of the api to the controller hardware: device operations,
+ * which don't involve endpoints (or i/o).
+ */
+struct usb_gadget_ops {
+	int	(*get_frame)(struct usb_gadget *);
+	int	(*wakeup)(struct usb_gadget *);
+	int	(*set_selfpowered) (struct usb_gadget *, int is_selfpowered);
+	int	(*vbus_session) (struct usb_gadget *, int is_active);
+	int	(*vbus_draw) (struct usb_gadget *, unsigned mA);
+	int	(*pullup) (struct usb_gadget *, int is_on);
+	int	(*ioctl)(struct usb_gadget *,
+				unsigned code, unsigned long param);
+};
+
+struct device {
+	void		*driver_data;	/* data private to the driver */
+	void            *device_data;   /* data private to the device */
+};
+
+/**
+ * struct usb_gadget - represents a usb slave device
+ * @ops: Function pointers used to access hardware-specific operations.
+ * @ep0: Endpoint zero, used when reading or writing responses to
+ *	driver setup() requests
+ * @ep_list: List of other endpoints supported by the device.
+ * @speed: Speed of current connection to USB host.
+ * @is_dualspeed: true if the controller supports both high and full speed
+ *	operation.  If it does, the gadget driver must also support both.
+ * @is_otg: true if the USB device port uses a Mini-AB jack, so that the
+ *	gadget driver must provide a USB OTG descriptor.
+ * @is_a_peripheral: false unless is_otg, the "A" end of a USB cable
+ *	is in the Mini-AB jack, and HNP has been used to switch roles
+ *	so that the "A" device currently acts as A-Peripheral, not A-Host.
+ * @a_hnp_support: OTG device feature flag, indicating that the A-Host
+ *	supports HNP at this port.
+ * @a_alt_hnp_support: OTG device feature flag, indicating that the A-Host
+ *	only supports HNP on a different root port.
+ * @b_hnp_enable: OTG device feature flag, indicating that the A-Host
+ *	enabled HNP support.
+ * @name: Identifies the controller hardware type.  Used in diagnostics
+ *	and sometimes configuration.
+ * @dev: Driver model state for this abstract device.
+ *
+ * Gadgets have a mostly-portable "gadget driver" implementing device
+ * functions, handling all usb configurations and interfaces.  Gadget
+ * drivers talk to hardware-specific code indirectly, through ops vectors.
+ * That insulates the gadget driver from hardware details, and packages
+ * the hardware endpoints through generic i/o queues.  The "usb_gadget"
+ * and "usb_ep" interfaces provide that insulation from the hardware.
+ *
+ * Except for the driver data, all fields in this structure are
+ * read-only to the gadget driver.  That driver data is part of the
+ * "driver model" infrastructure in 2.6 (and later) kernels, and for
+ * earlier systems is grouped in a similar structure that's not known
+ * to the rest of the kernel.
+ *
+ * Values of the three OTG device feature flags are updated before the
+ * setup() call corresponding to USB_REQ_SET_CONFIGURATION, and before
+ * driver suspend() calls.  They are valid only when is_otg, and when the
+ * device is acting as a B-Peripheral (so is_a_peripheral is false).
+ */
+struct usb_gadget {
+	/* readonly to gadget driver */
+	const struct usb_gadget_ops	*ops;
+	struct usb_ep			*ep0;
+	struct list_head		ep_list;	/* of usb_ep */
+	enum usb_device_speed		speed;
+	unsigned			is_dualspeed:1;
+	unsigned			is_otg:1;
+	unsigned			is_a_peripheral:1;
+	unsigned			b_hnp_enable:1;
+	unsigned			a_hnp_support:1;
+	unsigned			a_alt_hnp_support:1;
+	const char			*name;
+	struct device			dev;
+};
+
+static inline void set_gadget_data(struct usb_gadget *gadget, void *data)
+{
+	gadget->dev.driver_data = data;
+}
+
+static inline void *get_gadget_data(struct usb_gadget *gadget)
+{
+	return gadget->dev.driver_data;
+}
+
+static inline struct usb_gadget *dev_to_usb_gadget(struct device *dev)
+{
+	return container_of(dev, struct usb_gadget, dev);
+}
+
+/* iterates the non-control endpoints; 'tmp' is a struct usb_ep pointer */
+#define gadget_for_each_ep(tmp, gadget) \
+	list_for_each_entry(tmp, &(gadget)->ep_list, ep_list)
+
+
+/**
+ * gadget_is_dualspeed - return true iff the hardware handles high speed
+ * @g: controller that might support both high and full speeds
+ */
+static inline int gadget_is_dualspeed(struct usb_gadget *g)
+{
+#ifdef CONFIG_USB_GADGET_DUALSPEED
+	/* runtime test would check "g->is_dualspeed" ... that might be
+	 * useful to work around hardware bugs, but is mostly pointless
+	 */
+	return 1;
+#else
+	return 0;
+#endif
+}
+
+/**
+ * gadget_is_otg - return true iff the hardware is OTG-ready
+ * @g: controller that might have a Mini-AB connector
+ *
+ * This is a runtime test, since kernels with a USB-OTG stack sometimes
+ * run on boards which only have a Mini-B (or Mini-A) connector.
+ */
+static inline int gadget_is_otg(struct usb_gadget *g)
+{
+#ifdef CONFIG_USB_OTG
+	return g->is_otg;
+#else
+	return 0;
+#endif
+}
+
+/**
+ * usb_gadget_frame_number - returns the current frame number
+ * @gadget: controller that reports the frame number
+ *
+ * Returns the usb frame number, normally eleven bits from a SOF packet,
+ * or negative errno if this device doesn't support this capability.
+ */
+static inline int usb_gadget_frame_number(struct usb_gadget *gadget)
+{
+	return gadget->ops->get_frame(gadget);
+}
+
+/**
+ * usb_gadget_wakeup - tries to wake up the host connected to this gadget
+ * @gadget: controller used to wake up the host
+ *
+ * Returns zero on success, else negative error code if the hardware
+ * doesn't support such attempts, or its support has not been enabled
+ * by the usb host.  Drivers must return device descriptors that report
+ * their ability to support this, or hosts won't enable it.
+ *
+ * This may also try to use SRP to wake the host and start enumeration,
+ * even if OTG isn't otherwise in use.  OTG devices may also start
+ * remote wakeup even when hosts don't explicitly enable it.
+ */
+static inline int usb_gadget_wakeup(struct usb_gadget *gadget)
+{
+	if (!gadget->ops->wakeup)
+		return -EOPNOTSUPP;
+	return gadget->ops->wakeup(gadget);
+}
+
+/**
+ * usb_gadget_set_selfpowered - sets the device selfpowered feature.
+ * @gadget:the device being declared as self-powered
+ *
+ * this affects the device status reported by the hardware driver
+ * to reflect that it now has a local power supply.
+ *
+ * returns zero on success, else negative errno.
+ */
+static inline int usb_gadget_set_selfpowered(struct usb_gadget *gadget)
+{
+	if (!gadget->ops->set_selfpowered)
+		return -EOPNOTSUPP;
+	return gadget->ops->set_selfpowered(gadget, 1);
+}
+
+/**
+ * usb_gadget_clear_selfpowered - clear the device selfpowered feature.
+ * @gadget:the device being declared as bus-powered
+ *
+ * this affects the device status reported by the hardware driver.
+ * some hardware may not support bus-powered operation, in which
+ * case this feature's value can never change.
+ *
+ * returns zero on success, else negative errno.
+ */
+static inline int usb_gadget_clear_selfpowered(struct usb_gadget *gadget)
+{
+	if (!gadget->ops->set_selfpowered)
+		return -EOPNOTSUPP;
+	return gadget->ops->set_selfpowered(gadget, 0);
+}
+
+/**
+ * usb_gadget_vbus_connect - Notify controller that VBUS is powered
+ * @gadget:The device which now has VBUS power.
+ *
+ * This call is used by a driver for an external transceiver (or GPIO)
+ * that detects a VBUS power session starting.  Common responses include
+ * resuming the controller, activating the D+ (or D-) pullup to let the
+ * host detect that a USB device is attached, and starting to draw power
+ * (8mA or possibly more, especially after SET_CONFIGURATION).
+ *
+ * Returns zero on success, else negative errno.
+ */
+static inline int usb_gadget_vbus_connect(struct usb_gadget *gadget)
+{
+	if (!gadget->ops->vbus_session)
+		return -EOPNOTSUPP;
+	return gadget->ops->vbus_session(gadget, 1);
+}
+
+/**
+ * usb_gadget_vbus_draw - constrain controller's VBUS power usage
+ * @gadget:The device whose VBUS usage is being described
+ * @mA:How much current to draw, in milliAmperes.  This should be twice
+ *	the value listed in the configuration descriptor bMaxPower field.
+ *
+ * This call is used by gadget drivers during SET_CONFIGURATION calls,
+ * reporting how much power the device may consume.  For example, this
+ * could affect how quickly batteries are recharged.
+ *
+ * Returns zero on success, else negative errno.
+ */
+static inline int usb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA)
+{
+	if (!gadget->ops->vbus_draw)
+		return -EOPNOTSUPP;
+	return gadget->ops->vbus_draw(gadget, mA);
+}
+
+/**
+ * usb_gadget_vbus_disconnect - notify controller about VBUS session end
+ * @gadget:the device whose VBUS supply is being described
+ *
+ * This call is used by a driver for an external transceiver (or GPIO)
+ * that detects a VBUS power session ending.  Common responses include
+ * reversing everything done in usb_gadget_vbus_connect().
+ *
+ * Returns zero on success, else negative errno.
+ */
+static inline int usb_gadget_vbus_disconnect(struct usb_gadget *gadget)
+{
+	if (!gadget->ops->vbus_session)
+		return -EOPNOTSUPP;
+	return gadget->ops->vbus_session(gadget, 0);
+}
+
+/**
+ * usb_gadget_connect - software-controlled connect to USB host
+ * @gadget:the peripheral being connected
+ *
+ * Enables the D+ (or potentially D-) pullup.  The host will start
+ * enumerating this gadget when the pullup is active and a VBUS session
+ * is active (the link is powered).  This pullup is always enabled unless
+ * usb_gadget_disconnect() has been used to disable it.
+ *
+ * Returns zero on success, else negative errno.
+ */
+static inline int usb_gadget_connect(struct usb_gadget *gadget)
+{
+	if (!gadget->ops->pullup)
+		return -EOPNOTSUPP;
+	return gadget->ops->pullup(gadget, 1);
+}
+
+/**
+ * usb_gadget_disconnect - software-controlled disconnect from USB host
+ * @gadget:the peripheral being disconnected
+ *
+ * Disables the D+ (or potentially D-) pullup, which the host may see
+ * as a disconnect (when a VBUS session is active).  Not all systems
+ * support software pullup controls.
+ *
+ * This routine may be used during the gadget driver bind() call to prevent
+ * the peripheral from ever being visible to the USB host, unless later
+ * usb_gadget_connect() is called.  For example, user mode components may
+ * need to be activated before the system can talk to hosts.
+ *
+ * Returns zero on success, else negative errno.
+ */
+static inline int usb_gadget_disconnect(struct usb_gadget *gadget)
+{
+	if (!gadget->ops->pullup)
+		return -EOPNOTSUPP;
+	return gadget->ops->pullup(gadget, 0);
+}
+
+
+/*-------------------------------------------------------------------------*/
+
+/**
+ * struct usb_gadget_driver - driver for usb 'slave' devices
+ * @speed: Highest speed the driver handles.
+ * @bind: Invoked when the driver is bound to a gadget, usually
+ *	after registering the driver.
+ *	At that point, ep0 is fully initialized, and ep_list holds
+ *	the currently-available endpoints.
+ *	Called in a context that permits sleeping.
+ * @setup: Invoked for ep0 control requests that aren't handled by
+ *	the hardware level driver. Most calls must be handled by
+ *	the gadget driver, including descriptor and configuration
+ *	management.  The 16 bit members of the setup data are in
+ *	USB byte order. Called in_interrupt; this may not sleep.  Driver
+ *	queues a response to ep0, or returns negative to stall.
+ * @disconnect: Invoked after all transfers have been stopped,
+ *	when the host is disconnected.  May be called in_interrupt; this
+ *	may not sleep.  Some devices can't detect disconnect, so this might
+ *	not be called except as part of controller shutdown.
+ * @unbind: Invoked when the driver is unbound from a gadget,
+ *	usually from rmmod (after a disconnect is reported).
+ *	Called in a context that permits sleeping.
+ * @suspend: Invoked on USB suspend.  May be called in_interrupt.
+ * @resume: Invoked on USB resume.  May be called in_interrupt.
+ *
+ * Devices are disabled till a gadget driver successfully bind()s, which
+ * means the driver will handle setup() requests needed to enumerate (and
+ * meet "chapter 9" requirements) then do some useful work.
+ *
+ * If gadget->is_otg is true, the gadget driver must provide an OTG
+ * descriptor during enumeration, or else fail the bind() call.  In such
+ * cases, no USB traffic may flow until both bind() returns without
+ * having called usb_gadget_disconnect(), and the USB host stack has
+ * initialized.
+ *
+ * Drivers use hardware-specific knowledge to configure the usb hardware.
+ * endpoint addressing is only one of several hardware characteristics that
+ * are in descriptors the ep0 implementation returns from setup() calls.
+ *
+ * Except for ep0 implementation, most driver code shouldn't need change to
+ * run on top of different usb controllers.  It'll use endpoints set up by
+ * that ep0 implementation.
+ *
+ * The usb controller driver handles a few standard usb requests.  Those
+ * include set_address, and feature flags for devices, interfaces, and
+ * endpoints (the get_status, set_feature, and clear_feature requests).
+ *
+ * Accordingly, the driver's setup() callback must always implement all
+ * get_descriptor requests, returning at least a device descriptor and
+ * a configuration descriptor.  Drivers must make sure the endpoint
+ * descriptors match any hardware constraints. Some hardware also constrains
+ * other descriptors. (The pxa250 allows only configurations 1, 2, or 3).
+ *
+ * The driver's setup() callback must also implement set_configuration,
+ * and should also implement set_interface, get_configuration, and
+ * get_interface.  Setting a configuration (or interface) is where
+ * endpoints should be activated or (config 0) shut down.
+ *
+ * (Note that only the default control endpoint is supported.  Neither
+ * hosts nor devices generally support control traffic except to ep0.)
+ *
+ * Most devices will ignore USB suspend/resume operations, and so will
+ * not provide those callbacks.  However, some may need to change modes
+ * when the host is not longer directing those activities.  For example,
+ * local controls (buttons, dials, etc) may need to be re-enabled since
+ * the (remote) host can't do that any longer; or an error state might
+ * be cleared, to make the device behave identically whether or not
+ * power is maintained.
+ */
+struct usb_gadget_driver {
+	enum usb_device_speed	speed;
+	int			(*bind)(struct usb_gadget *);
+	void			(*unbind)(struct usb_gadget *);
+	int			(*setup)(struct usb_gadget *,
+					const struct usb_ctrlrequest *);
+	void			(*disconnect)(struct usb_gadget *);
+	void			(*suspend)(struct usb_gadget *);
+	void			(*resume)(struct usb_gadget *);
+};
+
+
+/*-------------------------------------------------------------------------*/
+
+/* driver modules register and unregister, as usual.
+ * these calls must be made in a context that can sleep.
+ *
+ * these will usually be implemented directly by the hardware-dependent
+ * usb bus interface driver, which will only support a single driver.
+ */
+
+/**
+ * usb_gadget_register_driver - register a gadget driver
+ * @driver:the driver being registered
+ *
+ * Call this in your gadget driver's module initialization function,
+ * to tell the underlying usb controller driver about your driver.
+ * The driver's bind() function will be called to bind it to a
+ * gadget before this registration call returns.  It's expected that
+ * the bind() functions will be in init sections.
+ * This function must be called in a context that can sleep.
+ */
+int usb_gadget_register_driver(struct usb_gadget_driver *driver);
+
+/**
+ * usb_gadget_unregister_driver - unregister a gadget driver
+ * @driver:the driver being unregistered
+ *
+ * Call this in your gadget driver's module cleanup function,
+ * to tell the underlying usb controller that your driver is
+ * going away.  If the controller is connected to a USB host,
+ * it will first disconnect().  The driver is also requested
+ * to unbind() and clean up any device state, before this procedure
+ * finally returns.  It's expected that the unbind() functions
+ * will in in exit sections, so may not be linked in some kernels.
+ * This function must be called in a context that can sleep.
+ */
+int usb_gadget_unregister_driver(struct usb_gadget_driver *driver);
+
+/*-------------------------------------------------------------------------*/
+
+/* utility to simplify dealing with string descriptors */
+
+/**
+ * struct usb_string - wraps a C string and its USB id
+ * @id:the (nonzero) ID for this string
+ * @s:the string, in UTF-8 encoding
+ *
+ * If you're using usb_gadget_get_string(), use this to wrap a string
+ * together with its ID.
+ */
+struct usb_string {
+	u8			id;
+	const char		*s;
+};
+
+/**
+ * struct usb_gadget_strings - a set of USB strings in a given language
+ * @language:identifies the strings' language (0x0409 for en-us)
+ * @strings:array of strings with their ids
+ *
+ * If you're using usb_gadget_get_string(), use this to wrap all the
+ * strings for a given language.
+ */
+struct usb_gadget_strings {
+	u16			language;	/* 0x0409 for en-us */
+	struct usb_string	*strings;
+};
+
+/* put descriptor for string with that id into buf (buflen >= 256) */
+int usb_gadget_get_string(struct usb_gadget_strings *table, int id, u8 *buf);
+
+/*-------------------------------------------------------------------------*/
+
+/* utility to simplify managing config descriptors */
+
+/* write vector of descriptors into buffer */
+int usb_descriptor_fillbuf(void *, unsigned,
+		const struct usb_descriptor_header **);
+
+/* build config descriptor from single descriptor vector */
+int usb_gadget_config_buf(const struct usb_config_descriptor *config,
+	void *buf, unsigned buflen, const struct usb_descriptor_header **desc);
+
+/*-------------------------------------------------------------------------*/
+
+/* utility wrapping a simple endpoint selection policy */
+
+extern struct usb_ep *usb_ep_autoconfig(struct usb_gadget *,
+			struct usb_endpoint_descriptor *);
+
+extern void usb_ep_autoconfig_reset(struct usb_gadget *);
+
+extern int usb_gadget_handle_interrupts(void);
+
+#endif	/* __LINUX_USB_GADGET_H */
diff --git a/qemu/roms/u-boot/include/linux/usb/musb.h b/qemu/roms/u-boot/include/linux/usb/musb.h
new file mode 100644
index 000000000..9f65ef96a
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/usb/musb.h
@@ -0,0 +1,162 @@
+/*
+ * This is used to for host and peripheral modes of the driver for
+ * Inventra (Multidrop) Highspeed Dual-Role Controllers:  (M)HDRC.
+ *
+ * Board initialization should put one of these into dev->platform_data,
+ * probably on some platform_device named "musb-hdrc".  It encapsulates
+ * key configuration differences between boards.
+ */
+
+#ifndef __LINUX_USB_MUSB_H
+#define __LINUX_USB_MUSB_H
+
+#ifndef __deprecated
+#define __deprecated
+#endif
+
+/* The USB role is defined by the connector used on the board, so long as
+ * standards are being followed.  (Developer boards sometimes won't.)
+ */
+enum musb_mode {
+	MUSB_UNDEFINED = 0,
+	MUSB_HOST,		/* A or Mini-A connector */
+	MUSB_PERIPHERAL,	/* B or Mini-B connector */
+	MUSB_OTG		/* Mini-AB connector */
+};
+
+struct clk;
+
+enum musb_fifo_style {
+	FIFO_RXTX,
+	FIFO_TX,
+	FIFO_RX
+} __attribute__ ((packed));
+
+enum musb_buf_mode {
+	BUF_SINGLE,
+	BUF_DOUBLE
+} __attribute__ ((packed));
+
+struct musb_fifo_cfg {
+	u8			hw_ep_num;
+	enum musb_fifo_style	style;
+	enum musb_buf_mode	mode;
+	u16			maxpacket;
+};
+
+#define MUSB_EP_FIFO(ep, st, m, pkt)		\
+{						\
+	.hw_ep_num	= ep,			\
+	.style		= st,			\
+	.mode		= m,			\
+	.maxpacket	= pkt,			\
+}
+
+#define MUSB_EP_FIFO_SINGLE(ep, st, pkt)	\
+	MUSB_EP_FIFO(ep, st, BUF_SINGLE, pkt)
+
+#define MUSB_EP_FIFO_DOUBLE(ep, st, pkt)	\
+	MUSB_EP_FIFO(ep, st, BUF_DOUBLE, pkt)
+
+struct musb_hdrc_eps_bits {
+	const char	name[16];
+	u8		bits;
+};
+
+struct musb_hdrc_config {
+	struct musb_fifo_cfg	*fifo_cfg;	/* board fifo configuration */
+	unsigned		fifo_cfg_size;	/* size of the fifo configuration */
+
+	/* MUSB configuration-specific details */
+	unsigned	multipoint:1;	/* multipoint device */
+	unsigned	dyn_fifo:1 __deprecated; /* supports dynamic fifo sizing */
+	unsigned	soft_con:1 __deprecated; /* soft connect required */
+	unsigned	utm_16:1 __deprecated; /* utm data witdh is 16 bits */
+	unsigned	big_endian:1;	/* true if CPU uses big-endian */
+	unsigned	mult_bulk_tx:1;	/* Tx ep required for multbulk pkts */
+	unsigned	mult_bulk_rx:1;	/* Rx ep required for multbulk pkts */
+	unsigned	high_iso_tx:1;	/* Tx ep required for HB iso */
+	unsigned	high_iso_rx:1;	/* Rx ep required for HD iso */
+	unsigned	dma:1 __deprecated; /* supports DMA */
+	unsigned	vendor_req:1 __deprecated; /* vendor registers required */
+
+	u8		num_eps;	/* number of endpoints _with_ ep0 */
+	u8		dma_channels __deprecated; /* number of dma channels */
+	u8		dyn_fifo_size;	/* dynamic size in bytes */
+	u8		vendor_ctrl __deprecated; /* vendor control reg width */
+	u8		vendor_stat __deprecated; /* vendor status reg witdh */
+	u8		dma_req_chan __deprecated; /* bitmask for required dma channels */
+	u8		ram_bits;	/* ram address size */
+
+	struct musb_hdrc_eps_bits *eps_bits __deprecated;
+#ifdef CONFIG_BLACKFIN
+	/* A GPIO controlling VRSEL in Blackfin */
+	unsigned int	gpio_vrsel;
+	unsigned int	gpio_vrsel_active;
+	/* musb CLKIN in Blackfin in MHZ */
+	unsigned char   clkin;
+#endif
+
+};
+
+struct musb_hdrc_platform_data {
+	/* MUSB_HOST, MUSB_PERIPHERAL, or MUSB_OTG */
+	u8		mode;
+
+	/* for clk_get() */
+	const char	*clock;
+
+	/* (HOST or OTG) switch VBUS on/off */
+	int		(*set_vbus)(struct device *dev, int is_on);
+
+	/* (HOST or OTG) mA/2 power supplied on (default = 8mA) */
+	u8		power;
+
+	/* (PERIPHERAL) mA/2 max power consumed (default = 100mA) */
+	u8		min_power;
+
+	/* (HOST or OTG) msec/2 after VBUS on till power good */
+	u8		potpgt;
+
+	/* (HOST or OTG) program PHY for external Vbus */
+	unsigned	extvbus:1;
+
+	/* Power the device on or off */
+	int		(*set_power)(int state);
+
+	/* MUSB configuration-specific details */
+	struct musb_hdrc_config	*config;
+
+	/* Architecture specific board data	*/
+	void		*board_data;
+
+	/* Platform specific struct musb_ops pointer */
+	const void	*platform_ops;
+};
+
+
+/* TUSB 6010 support */
+
+#define	TUSB6010_OSCCLK_60	16667	/* psec/clk @ 60.0 MHz */
+#define	TUSB6010_REFCLK_24	41667	/* psec/clk @ 24.0 MHz XI */
+#define	TUSB6010_REFCLK_19	52083	/* psec/clk @ 19.2 MHz CLKIN */
+
+#ifdef	CONFIG_ARCH_OMAP2
+
+extern int __init tusb6010_setup_interface(
+		struct musb_hdrc_platform_data *data,
+		unsigned ps_refclk, unsigned waitpin,
+		unsigned async_cs, unsigned sync_cs,
+		unsigned irq, unsigned dmachan);
+
+extern int tusb6010_platform_retime(unsigned is_refclk);
+
+#endif	/* OMAP2 */
+
+/*
+ * U-Boot specfic stuff
+ */
+int musb_register(struct musb_hdrc_platform_data *plat, void *bdata,
+			void *ctl_regs);
+
+#endif /* __LINUX_USB_MUSB_H */
diff --git a/qemu/roms/u-boot/include/linux/usb/xhci-omap.h b/qemu/roms/u-boot/include/linux/usb/xhci-omap.h
new file mode 100644
index 000000000..82630adc7
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux/usb/xhci-omap.h
@@ -0,0 +1,140 @@
+/*
+ * (C) Copyright 2013
+ * Texas Instruments Inc, <www.ti.com>
+ *
+ * Author: Dan Murphy <dmurphy@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_XHCI_OMAP_H_
+#define _ASM_ARCH_XHCI_OMAP_H_
+
+#ifdef CONFIG_DRA7XX
+#define OMAP_XHCI_BASE 0x488d0000
+#define OMAP_OCP1_SCP_BASE 0x4A081000
+#define OMAP_OTG_WRAPPER_BASE 0x488c0000
+#elif defined CONFIG_AM43XX
+#define OMAP_XHCI_BASE 0x483d0000
+#define OMAP_OCP1_SCP_BASE 0x483E8000
+#define OMAP_OTG_WRAPPER_BASE 0x483dc100
+#else
+/* Default to the OMAP5 XHCI defines */
+#define OMAP_XHCI_BASE 0x4a030000
+#define OMAP_OCP1_SCP_BASE 0x4a084c00
+#define OMAP_OTG_WRAPPER_BASE 0x4A020000
+#endif
+
+/* Phy register MACRO definitions */
+#define	PLL_REGM_MASK		0x001FFE00
+#define	PLL_REGM_SHIFT		0x9
+#define	PLL_REGM_F_MASK		0x0003FFFF
+#define	PLL_REGM_F_SHIFT	0x0
+#define	PLL_REGN_MASK		0x000001FE
+#define	PLL_REGN_SHIFT		0x1
+#define	PLL_SELFREQDCO_MASK	0x0000000E
+#define	PLL_SELFREQDCO_SHIFT	0x1
+#define	PLL_SD_MASK		0x0003FC00
+#define	PLL_SD_SHIFT		0x9
+#define	SET_PLL_GO		0x1
+#define	PLL_TICOPWDN		0x10000
+#define	PLL_LOCK		0x2
+#define	PLL_IDLE		0x1
+
+#define USB3_PWRCTL_CLK_CMD_MASK	0x3FE000
+#define USB3_PWRCTL_CLK_FREQ_MASK	0xFFC
+#define USB3_PHY_PARTIAL_RX_POWERON     (1 << 6)
+#define USB3_PHY_RX_POWERON		(1 << 14)
+#define USB3_PHY_TX_POWERON		(1 << 15)
+#define USB3_PHY_TX_RX_POWERON	(USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON)
+#define USB3_PWRCTL_CLK_CMD_SHIFT   14
+#define USB3_PWRCTL_CLK_FREQ_SHIFT	22
+
+/* USBOTGSS_WRAPPER definitions */
+#define USBOTGSS_WRAPRESET	(1 << 17)
+#define USBOTGSS_DMADISABLE (1 << 16)
+#define USBOTGSS_STANDBYMODE_NO_STANDBY (1 << 4)
+#define USBOTGSS_STANDBYMODE_SMRT		(1 << 5)
+#define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 << 4)
+#define USBOTGSS_IDLEMODE_NOIDLE (1 << 2)
+#define USBOTGSS_IDLEMODE_SMRT (1 << 3)
+#define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 << 2)
+
+/* USBOTGSS_IRQENABLE_SET_0 bit */
+#define USBOTGSS_COREIRQ_EN	(1 << 0)
+
+/* USBOTGSS_IRQENABLE_SET_1 bits */
+#define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN	(1 << 0)
+#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN	(1 << 3)
+#define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN	(1 << 4)
+#define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN	(1 << 5)
+#define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN	(1 << 8)
+#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN	(1 << 11)
+#define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN	(1 << 12)
+#define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN	(1 << 13)
+#define USBOTGSS_IRQ_SET_1_OEVT_EN	(1 << 16)
+#define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN	(1 << 17)
+
+/*
+ * USBOTGSS_WRAPPER registers
+ */
+struct omap_dwc_wrapper {
+	u32 revision;
+
+	u32 reserve_1[3];
+
+	u32 sysconfig; /* offset of 0x10 */
+
+	u32 reserve_2[3];
+	u16 reserve_3;
+
+	u32 irqstatus_raw_0; /* offset of 0x24 */
+	u32 irqstatus_0;
+	u32 irqenable_set_0;
+	u32 irqenable_clr_0;
+
+	u32 irqstatus_raw_1; /* offset of 0x34 */
+	u32 irqstatus_1;
+	u32 irqenable_set_1;
+	u32 irqenable_clr_1;
+
+	u32 reserve_4[15];
+
+	u32 utmi_otg_ctrl; /* offset of 0x80 */
+	u32 utmi_otg_status;
+
+	u32 reserve_5[30];
+
+	u32 mram_offset; /* offset of 0x100 */
+	u32 fladj;
+	u32 dbg_config;
+	u32 dbg_data;
+	u32 dev_ebc_en;
+};
+
+/* XHCI PHY register structure */
+struct omap_usb3_phy {
+	u32 reserve1;
+	u32 pll_status;
+	u32 pll_go;
+	u32 pll_config_1;
+	u32 pll_config_2;
+	u32 pll_config_3;
+	u32 pll_ssc_config_1;
+	u32 pll_ssc_config_2;
+	u32 pll_config_4;
+};
+
+struct omap_xhci {
+	struct omap_dwc_wrapper *otg_wrapper;
+	struct omap_usb3_phy *usb3_phy;
+	struct xhci_hccr *hcd;
+	struct dwc3 *dwc3_reg;
+};
+
+/* USB PHY functions */
+void omap_enable_phy(struct omap_xhci *omap);
+void omap_reset_usb_phy(struct dwc3 *dwc3_reg);
+void usb_phy_power(int on);
+
+#endif /* _ASM_ARCH_XHCI_OMAP_H_ */
diff --git a/qemu/roms/u-boot/include/linux_logo.h b/qemu/roms/u-boot/include/linux_logo.h
new file mode 100644
index 000000000..9aa712eb4
--- /dev/null
+++ b/qemu/roms/u-boot/include/linux_logo.h
@@ -0,0 +1,1445 @@
+/* $Id: linux_logo.h,v 1.5 1998/07/30 16:30:58 jj Exp $
+ * include/linux/linux_logo.h: This is a linux logo
+ *                             to be displayed on boot.
+ *
+ * Copyright (C) 1996 Larry Ewing (lewing@isc.tamu.edu)
+ * Copyright (C) 1996,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
+ *
+ * You can put anything here, but:
+ * LINUX_LOGO_COLORS has to be less than 224
+ * image size has to be 80x80
+ * values have to start from 0x20
+ * (i.e. RGB(linux_logo_red[0],
+ *           linux_logo_green[0],
+ *           linux_logo_blue[0]) is color 0x20)
+ * BW image has to be 80x80 as well, with MS bit
+ * on the left
+ * Serial_console ascii image can be any size,
+ * but should contain %s to display the version
+ */
+
+#if LINUX_LOGO_COLORS == 214
+
+unsigned char linux_logo_red[] __initdata = {
+  0x02, 0x9E, 0xE9, 0xC4, 0x50, 0xC9, 0xC4, 0xE9,
+  0x65, 0xE3, 0xC2, 0x25, 0xA4, 0xEC, 0x90, 0xA6,
+  0xC4, 0x6A, 0xD1, 0xF3, 0x12, 0xED, 0xA0, 0xC2,
+  0xB8, 0xD5, 0xDB, 0xD2, 0x3E, 0x16, 0xEB, 0x54,
+  0xA9, 0xCD, 0xF5, 0x0A, 0xBA, 0xB3, 0xDC, 0x74,
+  0xCE, 0xF6, 0xD3, 0xC5, 0xEA, 0xB8, 0xED, 0x5E,
+  0xE5, 0x26, 0xF4, 0xA9, 0x82, 0x94, 0xE6, 0x38,
+  0xF2, 0x0F, 0x7F, 0x49, 0xE5, 0xF4, 0xD3, 0xC3,
+  0xC2, 0x1E, 0xD5, 0xC6, 0xA4, 0xFA, 0x0A, 0xBA,
+  0xD4, 0xEB, 0xEA, 0xEC, 0xA8, 0xBC, 0xB4, 0xDC,
+  0x84, 0xE4, 0xCE, 0xEC, 0x92, 0xCD, 0xDC, 0x8B,
+  0xCC, 0x1E, 0xF6, 0xB2, 0x60, 0x2A, 0x96, 0x52,
+  0x0F, 0xBD, 0xFA, 0xCC, 0xB8, 0x7A, 0x4C, 0xD2,
+  0x06, 0xEF, 0x44, 0x64, 0xF4, 0xBA, 0xCE, 0xE6,
+  0x8A, 0x6F, 0x3C, 0x70, 0x7C, 0x9C, 0xBA, 0xDF,
+  0x2C, 0x4D, 0x3B, 0xCA, 0xDE, 0xCE, 0xEE, 0x46,
+  0x6A, 0xAC, 0x96, 0xE5, 0x96, 0x7A, 0xBA, 0xB6,
+  0xE2, 0x7E, 0xAA, 0xC5, 0x96, 0x9E, 0xC2, 0xAA,
+  0xDA, 0x35, 0xB6, 0x82, 0x88, 0xBE, 0xC2, 0x9E,
+  0xB4, 0xD5, 0xDA, 0x9C, 0xA0, 0xD0, 0xA8, 0xC7,
+  0x72, 0xF2, 0xDB, 0x76, 0xDC, 0xBE, 0xAA, 0xF4,
+  0x87, 0x2F, 0x53, 0x8E, 0x36, 0xCE, 0xE6, 0xCA,
+  0xCB, 0xE4, 0xD6, 0xAA, 0x42, 0x5D, 0xB4, 0x59,
+  0x1C, 0xC8, 0x96, 0x6C, 0xDA, 0xCE, 0xE6, 0xCB,
+  0x96, 0x16, 0xFA, 0xBE, 0xAE, 0xFE, 0x6E, 0xD6,
+  0xCE, 0xB6, 0xE5, 0xED, 0xDB, 0xDC, 0xF4, 0x72,
+  0x1F, 0xAE, 0xE6, 0xC2, 0xCA, 0xC4
+};
+
+unsigned char linux_logo_green[] __initdata = {
+  0x02, 0x88, 0xC4, 0x85, 0x44, 0xA2, 0xA8, 0xE5,
+  0x65, 0xA6, 0xC2, 0x24, 0xA4, 0xB4, 0x62, 0x86,
+  0x94, 0x44, 0xD2, 0xB6, 0x12, 0xD4, 0x73, 0x96,
+  0x92, 0x95, 0xB2, 0xC2, 0x36, 0x0E, 0xBC, 0x54,
+  0x75, 0xA5, 0xF5, 0x0A, 0xB2, 0x83, 0xC2, 0x74,
+  0x9B, 0xBD, 0xA2, 0xCA, 0xDA, 0x8C, 0xCB, 0x42,
+  0xAC, 0x12, 0xDA, 0x7B, 0x54, 0x94, 0xD2, 0x24,
+  0xBE, 0x06, 0x65, 0x33, 0xBB, 0xBC, 0xAB, 0x8C,
+  0x92, 0x1E, 0x9B, 0xB6, 0x6E, 0xFB, 0x04, 0xA2,
+  0xC8, 0xBD, 0xAD, 0xEC, 0x92, 0xBC, 0x7B, 0x9D,
+  0x84, 0xC4, 0xC4, 0xB4, 0x6C, 0x93, 0xA3, 0x5E,
+  0x8D, 0x13, 0xD6, 0x82, 0x4C, 0x2A, 0x7A, 0x5A,
+  0x0D, 0x82, 0xBB, 0xCC, 0x8B, 0x6A, 0x3C, 0xBE,
+  0x06, 0xC4, 0x44, 0x45, 0xDB, 0x96, 0xB6, 0xDE,
+  0x8A, 0x4D, 0x3C, 0x5A, 0x7C, 0x9C, 0xAA, 0xCB,
+  0x1C, 0x4D, 0x2E, 0xB2, 0xBE, 0xAA, 0xDE, 0x3E,
+  0x6A, 0xAC, 0x82, 0xE5, 0x72, 0x62, 0x92, 0x9E,
+  0xCA, 0x4A, 0x8E, 0xBE, 0x86, 0x6B, 0xAA, 0x9A,
+  0xBE, 0x34, 0xAB, 0x76, 0x6E, 0x9A, 0x9E, 0x62,
+  0x76, 0xCE, 0xD3, 0x92, 0x7C, 0xB8, 0x7E, 0xC6,
+  0x5E, 0xE2, 0xC3, 0x54, 0xAA, 0x9E, 0x8A, 0xCA,
+  0x63, 0x2D, 0x3B, 0x8E, 0x1A, 0x9E, 0xC2, 0xA6,
+  0xCB, 0xDC, 0xD6, 0x8E, 0x26, 0x5C, 0xB4, 0x45,
+  0x1C, 0xB8, 0x6E, 0x4C, 0xBC, 0xAE, 0xD6, 0x92,
+  0x63, 0x16, 0xF6, 0x8C, 0x7A, 0xFE, 0x6E, 0xBA,
+  0xC6, 0x86, 0xAA, 0xAE, 0xDB, 0xA4, 0xD4, 0x56,
+  0x0E, 0x6E, 0xB6, 0xB2, 0xBE, 0xBE
+};
+
+unsigned char linux_logo_blue[] __initdata = {
+  0x04, 0x28, 0x10, 0x0B, 0x14, 0x14, 0x74, 0xC7,
+  0x64, 0x0E, 0xC3, 0x24, 0xA4, 0x0C, 0x10, 0x20,
+  0x0D, 0x04, 0xD1, 0x0D, 0x13, 0x22, 0x0A, 0x40,
+  0x14, 0x0C, 0x11, 0x94, 0x0C, 0x08, 0x0B, 0x56,
+  0x09, 0x47, 0xF4, 0x0B, 0x9C, 0x07, 0x54, 0x74,
+  0x0F, 0x0C, 0x0F, 0xC7, 0x6C, 0x14, 0x14, 0x11,
+  0x0B, 0x04, 0x12, 0x0C, 0x05, 0x94, 0x94, 0x0A,
+  0x34, 0x09, 0x14, 0x08, 0x2F, 0x15, 0x19, 0x11,
+  0x28, 0x0C, 0x0B, 0x94, 0x08, 0xFA, 0x08, 0x7C,
+  0xBC, 0x15, 0x0A, 0xEC, 0x64, 0xBB, 0x0A, 0x0C,
+  0x84, 0x2C, 0xA0, 0x15, 0x10, 0x0D, 0x0B, 0x0E,
+  0x0A, 0x07, 0x10, 0x3C, 0x24, 0x2C, 0x28, 0x5C,
+  0x0A, 0x0D, 0x0A, 0xC1, 0x22, 0x4C, 0x10, 0x94,
+  0x04, 0x0F, 0x45, 0x08, 0x31, 0x54, 0x3C, 0xBC,
+  0x8C, 0x09, 0x3C, 0x18, 0x7C, 0x9C, 0x7C, 0x91,
+  0x0C, 0x4D, 0x17, 0x74, 0x0C, 0x48, 0x9C, 0x3C,
+  0x6A, 0xAC, 0x5C, 0xE3, 0x29, 0x3C, 0x2C, 0x7C,
+  0x6C, 0x04, 0x14, 0xA9, 0x74, 0x07, 0x2C, 0x74,
+  0x4C, 0x34, 0x97, 0x5C, 0x38, 0x0C, 0x5C, 0x04,
+  0x0C, 0xBA, 0xBC, 0x78, 0x18, 0x88, 0x24, 0xC2,
+  0x3C, 0xB4, 0x87, 0x0C, 0x14, 0x4C, 0x3C, 0x10,
+  0x17, 0x2C, 0x0A, 0x8C, 0x04, 0x1C, 0x44, 0x2C,
+  0xCD, 0xD8, 0xD4, 0x34, 0x0C, 0x5B, 0xB4, 0x1E,
+  0x1D, 0xAC, 0x24, 0x18, 0x20, 0x5C, 0xB4, 0x1C,
+  0x09, 0x14, 0xFC, 0x0C, 0x10, 0xFC, 0x6C, 0x7C,
+  0xB4, 0x1C, 0x15, 0x17, 0xDB, 0x18, 0x21, 0x24,
+  0x04, 0x04, 0x44, 0x8C, 0x8C, 0xB7
+};
+
+unsigned char linux_logo[] __initdata = {
+  0xBF, 0x95, 0x90, 0xCB, 0x95, 0xA1, 0x2C, 0x2C,
+  0x95, 0x55, 0xCB, 0x90, 0xCB, 0x95, 0x2C, 0x95,
+  0xCB, 0x47, 0x94, 0x95, 0xA1, 0xD6, 0xD6, 0x2C,
+  0x90, 0x47, 0x70, 0x2C, 0x6D, 0x2A, 0x6D, 0xD6,
+  0xA1, 0x2C, 0x55, 0x95, 0x2C, 0x2C, 0x55, 0x55,
+  0x95, 0xA1, 0xA1, 0xA1, 0x6D, 0xBF, 0x2A, 0x2A,
+  0xBF, 0x83, 0xBF, 0x95, 0x90, 0xCB, 0x95, 0xA1,
+  0x2C, 0x2C, 0x95, 0x55, 0xCB, 0x90, 0xCB, 0x95,
+  0x2C, 0x95, 0xCB, 0x47, 0x94, 0x95, 0xA1, 0xD6,
+  0xD6, 0x2C, 0x90, 0x47, 0x70, 0x2C, 0x6D, 0x2A,
+  0x95, 0x47, 0x47, 0x90, 0x2C, 0x2C, 0x2C, 0x95,
+  0x55, 0x55, 0xCB, 0x90, 0xCB, 0x55, 0x55, 0xCB,
+  0x47, 0xE6, 0x70, 0x95, 0xD6, 0xD6, 0xA1, 0x2C,
+  0x55, 0x55, 0x95, 0xD6, 0x6D, 0xD6, 0xA1, 0x2C,
+  0x2C, 0x95, 0x55, 0x95, 0x95, 0x95, 0x2C, 0x2C,
+  0xA1, 0xA1, 0x2C, 0x2C, 0xA1, 0xD6, 0xD6, 0xD6,
+  0xD6, 0xD6, 0x95, 0x47, 0x47, 0x90, 0x2C, 0x2C,
+  0x2C, 0x95, 0x55, 0x55, 0xCB, 0x90, 0xCB, 0x55,
+  0x55, 0xCB, 0x47, 0xE6, 0x70, 0x95, 0xD6, 0xD6,
+  0xA1, 0x2C, 0x55, 0x55, 0x95, 0xD6, 0x6D, 0xD6,
+  0x90, 0x47, 0x47, 0x70, 0x2C, 0xA1, 0x2C, 0x95,
+  0x55, 0x55, 0x90, 0xCB, 0x55, 0x55, 0x55, 0x70,
+  0x94, 0x70, 0x95, 0xA1, 0xD6, 0xD6, 0xA1, 0x2C,
+  0x95, 0x95, 0x2C, 0xA1, 0xD6, 0xA1, 0x2C, 0x2C,
+  0x95, 0x55, 0xCB, 0x95, 0xD6, 0xA1, 0x2C, 0x95,
+  0xA1, 0xD6, 0xD6, 0xA1, 0xA1, 0xD6, 0xA1, 0xA1,
+  0xA1, 0x2C, 0x90, 0x47, 0x47, 0x70, 0x2C, 0xA1,
+  0x2C, 0x95, 0x55, 0x55, 0x90, 0xCB, 0x55, 0x55,
+  0x55, 0x70, 0x94, 0x70, 0x95, 0xA1, 0xD6, 0xD6,
+  0xA1, 0x2C, 0x95, 0x95, 0x2C, 0xD6, 0xD6, 0xA1,
+  0x94, 0xA0, 0x47, 0x55, 0x2C, 0xD6, 0xA1, 0x95,
+  0x55, 0x55, 0xCB, 0xCB, 0x55, 0x55, 0xCB, 0xCB,
+  0x55, 0x95, 0x2C, 0xA1, 0xD6, 0xD6, 0xA1, 0x2C,
+  0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0x95,
+  0x55, 0x55, 0x2C, 0x3F, 0x80, 0x20, 0x88, 0x88,
+  0x88, 0x20, 0x88, 0xB1, 0x2C, 0xA1, 0x2C, 0x2C,
+  0x95, 0xCB, 0x94, 0xA0, 0x47, 0x55, 0x2C, 0xD6,
+  0xA1, 0x95, 0x55, 0x55, 0xCB, 0xCB, 0x55, 0x55,
+  0xCB, 0xCB, 0x55, 0x95, 0x2C, 0xA1, 0xD6, 0xD6,
+  0xA1, 0x2C, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C,
+  0x94, 0x94, 0x70, 0x2C, 0xA1, 0xD6, 0xA1, 0x2C,
+  0x55, 0x55, 0xCB, 0x55, 0x55, 0x55, 0x55, 0x55,
+  0x95, 0x2C, 0xD6, 0xD6, 0xD6, 0xA1, 0x2C, 0x95,
+  0x55, 0x55, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
+  0x2C, 0x94, 0x80, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x88, 0x92, 0xA1, 0x95,
+  0x55, 0x90, 0x94, 0x94, 0x70, 0x2C, 0xA1, 0xD6,
+  0xA1, 0x2C, 0x55, 0x55, 0xCB, 0x55, 0x55, 0x55,
+  0x55, 0x55, 0x95, 0x2C, 0xD6, 0xD6, 0xD6, 0xA1,
+  0x2C, 0x95, 0x55, 0x55, 0x55, 0x95, 0x95, 0x95,
+  0x70, 0x70, 0x55, 0x2C, 0xD6, 0xD6, 0xA1, 0x95,
+  0x55, 0x90, 0xCB, 0xCB, 0x55, 0x55, 0x2C, 0x2C,
+  0xA1, 0xD6, 0xA1, 0xA1, 0x2C, 0x2C, 0x95, 0x55,
+  0x55, 0x55, 0x95, 0x95, 0x2C, 0x95, 0x95, 0xD6,
+  0xB1, 0x88, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x80, 0x34, 0x88, 0x43, 0x47,
+  0x95, 0xCB, 0x70, 0x70, 0x55, 0x2C, 0xD6, 0xD6,
+  0xA1, 0x95, 0x55, 0x90, 0xCB, 0xCB, 0x55, 0x55,
+  0x2C, 0x2C, 0xA1, 0xD6, 0xA1, 0xA1, 0xA1, 0x2C,
+  0x55, 0x55, 0x55, 0x55, 0x2C, 0x95, 0x2C, 0x2C,
+  0x55, 0x55, 0x95, 0x2C, 0xA1, 0xA1, 0x2C, 0x55,
+  0x90, 0x70, 0x90, 0x55, 0x95, 0x95, 0xA1, 0xA1,
+  0xA1, 0xA1, 0xA1, 0xA1, 0x2C, 0x95, 0x95, 0x95,
+  0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0xD5,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x88, 0x7D, 0x3F, 0xB1, 0x80, 0x20,
+  0x99, 0x2C, 0x55, 0x55, 0x95, 0x2C, 0xA1, 0xA1,
+  0x2C, 0x55, 0x90, 0x70, 0x90, 0x55, 0x95, 0x95,
+  0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0x2C, 0x2C, 0x2C,
+  0x95, 0x55, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C,
+  0x95, 0x90, 0x55, 0x2C, 0xA1, 0xA1, 0x95, 0xCB,
+  0x70, 0x94, 0x90, 0x55, 0x95, 0xA1, 0xA1, 0xA1,
+  0x2C, 0x2C, 0x2C, 0x2C, 0x95, 0x95, 0x95, 0x95,
+  0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0xA1, 0x88,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0xB1, 0x47, 0xD5, 0x7D, 0x43,
+  0x20, 0x70, 0x95, 0x90, 0x55, 0x2C, 0xA1, 0xA1,
+  0x95, 0xCB, 0x70, 0x94, 0x90, 0x55, 0x95, 0xA1,
+  0xA1, 0xA1, 0x2C, 0x95, 0x2C, 0x2C, 0x95, 0x95,
+  0x95, 0x95, 0x95, 0x2C, 0x95, 0x95, 0x95, 0x95,
+  0x95, 0x90, 0x55, 0x2C, 0xD6, 0xD6, 0x2C, 0x90,
+  0x94, 0x70, 0x55, 0x95, 0x2C, 0xD6, 0xD6, 0xA1,
+  0x95, 0x95, 0x95, 0x2C, 0x2C, 0x95, 0x55, 0x55,
+  0xCB, 0xCB, 0xCB, 0x55, 0xCB, 0x55, 0x47, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x88, 0xB1, 0x3F, 0x92, 0x2B, 0x80,
+  0x20, 0x80, 0xD6, 0x70, 0x55, 0x2C, 0xD6, 0xD6,
+  0x2C, 0x90, 0x94, 0x70, 0x55, 0x95, 0x2C, 0xD6,
+  0xD6, 0xA1, 0x2C, 0x95, 0x95, 0x2C, 0x2C, 0x95,
+  0x95, 0x55, 0x90, 0xCB, 0xCB, 0xCB, 0xCB, 0x55,
+  0xD6, 0x55, 0x95, 0xA1, 0xD6, 0xA1, 0x55, 0x70,
+  0x94, 0x55, 0x95, 0xA1, 0xA1, 0xA1, 0xA1, 0x95,
+  0x55, 0x55, 0x55, 0x95, 0x55, 0x55, 0xCB, 0x90,
+  0x70, 0x90, 0xCB, 0x55, 0x55, 0xA1, 0xD8, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x88, 0xD8, 0xE1, 0x88, 0x20, 0x20,
+  0x88, 0x88, 0xE6, 0x55, 0x2C, 0xA1, 0xD6, 0xA1,
+  0x55, 0x70, 0x94, 0x55, 0x95, 0xA1, 0xA1, 0xA1,
+  0xA1, 0x95, 0x55, 0x55, 0x95, 0x95, 0x55, 0x55,
+  0x90, 0x90, 0x90, 0x90, 0xCB, 0x55, 0x55, 0x55,
+  0xD6, 0x2C, 0xA1, 0xD6, 0xD6, 0xA1, 0xCB, 0x70,
+  0x70, 0x95, 0x2C, 0xA1, 0xA1, 0x2C, 0x2C, 0x55,
+  0xCB, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55,
+  0x55, 0x95, 0x2C, 0x95, 0x2C, 0xD6, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x80, 0xD6, 0xA1, 0xD6, 0xD6, 0xA1,
+  0xCB, 0x70, 0x70, 0x95, 0x2C, 0xA1, 0xA1, 0x2C,
+  0x2C, 0x55, 0xCB, 0xCB, 0x55, 0x55, 0x55, 0x55,
+  0x55, 0x55, 0x55, 0x95, 0x2C, 0x2C, 0x2C, 0x2C,
+  0xD6, 0xA1, 0xA1, 0xA1, 0xA1, 0x55, 0x70, 0x94,
+  0xCB, 0x95, 0xA1, 0xA1, 0x2C, 0x95, 0xCB, 0x55,
+  0x90, 0xCB, 0x55, 0x55, 0x55, 0x55, 0x95, 0xA1,
+  0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0x95, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x88, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x88, 0x95, 0xA1, 0xA1, 0xA1, 0x55,
+  0x70, 0x94, 0xCB, 0x95, 0xA1, 0xA1, 0x2C, 0x95,
+  0xCB, 0xCB, 0x90, 0xCB, 0x55, 0x55, 0x55, 0x55,
+  0x95, 0x2C, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1,
+  0x2C, 0x2C, 0x2C, 0x95, 0x95, 0xCB, 0x70, 0x70,
+  0x95, 0x2C, 0x2C, 0x95, 0xCB, 0x70, 0x90, 0xCB,
+  0xCB, 0x55, 0x55, 0xCB, 0x55, 0x55, 0x2C, 0xD6,
+  0xD6, 0xD6, 0xD6, 0xA1, 0x2C, 0x70, 0x20, 0x20,
+  0x88, 0x43, 0xD8, 0x43, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x88, 0x88, 0x43, 0x2B, 0xD8, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x3F, 0x2C, 0x95, 0x95, 0xCB,
+  0x70, 0x70, 0x95, 0x2C, 0x2C, 0x95, 0xCB, 0x90,
+  0x90, 0xCB, 0x55, 0xCB, 0x55, 0xCB, 0x55, 0x95,
+  0x2C, 0xD6, 0xD6, 0xD6, 0xD6, 0xA1, 0x2C, 0x2C,
+  0xA1, 0x95, 0x95, 0x55, 0xCB, 0x70, 0x90, 0x55,
+  0x2C, 0x2C, 0x2C, 0x55, 0x70, 0x70, 0x55, 0x95,
+  0x95, 0xCB, 0x90, 0x90, 0x90, 0x95, 0x2C, 0xA1,
+  0xD6, 0xD6, 0x2C, 0x2C, 0x95, 0x70, 0x20, 0x20,
+  0x80, 0x2B, 0x34, 0x2B, 0x88, 0x20, 0x20, 0x20,
+  0x88, 0xB1, 0x28, 0x28, 0x2B, 0x7D, 0x80, 0x20,
+  0x20, 0x20, 0x20, 0x92, 0x95, 0x55, 0xCB, 0x70,
+  0x90, 0x55, 0x2C, 0x2C, 0x2C, 0x55, 0x70, 0x70,
+  0x55, 0x95, 0x55, 0x55, 0x90, 0x90, 0x90, 0x55,
+  0x2C, 0xA1, 0xD6, 0xA1, 0x2C, 0x2C, 0x95, 0x95,
+  0xA1, 0x95, 0x55, 0xCB, 0x90, 0x70, 0xCB, 0x95,
+  0xA1, 0x95, 0x95, 0xCB, 0x90, 0xCB, 0x95, 0x2C,
+  0x95, 0x70, 0x70, 0x90, 0x55, 0x2C, 0xA1, 0xA1,
+  0x2C, 0x2C, 0x55, 0xCB, 0x55, 0x90, 0x20, 0x34,
+  0x90, 0x6D, 0x70, 0xD8, 0x43, 0x20, 0x20, 0x88,
+  0x3F, 0x55, 0xA1, 0x2A, 0xD6, 0x7D, 0x43, 0x20,
+  0x20, 0x20, 0x88, 0x7D, 0x55, 0xCB, 0x90, 0x70,
+  0xCB, 0x95, 0xA1, 0x95, 0x95, 0xCB, 0x70, 0xCB,
+  0x95, 0xA1, 0x95, 0x70, 0x70, 0xCB, 0x55, 0x2C,
+  0xA1, 0xA1, 0xA1, 0x95, 0x55, 0x55, 0x55, 0x95,
+  0x2C, 0x55, 0x90, 0x70, 0x94, 0x90, 0x95, 0x2C,
+  0x2C, 0x95, 0xCB, 0x90, 0x55, 0x95, 0xA1, 0xA1,
+  0x95, 0x90, 0x90, 0x95, 0xA1, 0xD6, 0xD6, 0x6D,
+  0xA1, 0x95, 0x55, 0xCB, 0x55, 0xCB, 0x20, 0x99,
+  0xBF, 0xA3, 0xA3, 0x90, 0x20, 0x20, 0x20, 0x92,
+  0x83, 0x6B, 0x6B, 0x6B, 0xA3, 0x70, 0x88, 0x20,
+  0x20, 0x20, 0x20, 0x2B, 0x90, 0x70, 0x94, 0x90,
+  0x95, 0x2C, 0x2C, 0x95, 0xCB, 0x90, 0x55, 0x95,
+  0xA1, 0x2C, 0x55, 0x90, 0x90, 0x95, 0xA1, 0xD6,
+  0xD6, 0x6D, 0xA1, 0x95, 0x55, 0xCB, 0x55, 0x55,
+  0x2C, 0x55, 0x70, 0x70, 0x94, 0x90, 0x95, 0x2C,
+  0x2C, 0x55, 0xCB, 0xCB, 0x95, 0x2C, 0x2C, 0x2C,
+  0x55, 0x55, 0x95, 0xA1, 0x6D, 0xBF, 0x6D, 0xD6,
+  0x95, 0x55, 0x90, 0xCB, 0x55, 0x95, 0x88, 0x95,
+  0x2C, 0x3F, 0x6D, 0x6B, 0x34, 0x20, 0x20, 0x47,
+  0x65, 0xD6, 0xE1, 0x3F, 0x2A, 0x6B, 0x2B, 0x20,
+  0x20, 0x20, 0x20, 0x43, 0x70, 0x70, 0x94, 0x90,
+  0x95, 0x2C, 0x2C, 0x55, 0x55, 0x55, 0x95, 0x2C,
+  0xA1, 0x2C, 0x55, 0xCB, 0x95, 0xA1, 0x6D, 0xBF,
+  0x6D, 0xD6, 0x2C, 0x55, 0x90, 0xCB, 0x95, 0x95,
+  0x95, 0x55, 0x70, 0x94, 0x70, 0x55, 0x2C, 0xA1,
+  0x2C, 0x55, 0xCB, 0x55, 0x2C, 0x95, 0x2C, 0x95,
+  0x95, 0x95, 0xA1, 0x6D, 0xBF, 0x2A, 0xD6, 0x95,
+  0x70, 0x94, 0x94, 0x70, 0x55, 0x55, 0x20, 0xBF,
+  0xC9, 0xB1, 0x99, 0x42, 0xB1, 0x61, 0x7D, 0x94,
+  0x65, 0xB1, 0x88, 0x99, 0xD5, 0xE5, 0x7F, 0x20,
+  0x20, 0x20, 0x20, 0x43, 0x70, 0x94, 0x70, 0x55,
+  0x2C, 0xA1, 0x2C, 0x55, 0x90, 0x55, 0x2C, 0x95,
+  0x2C, 0x95, 0x95, 0x2C, 0xA1, 0x6D, 0xBF, 0xBF,
+  0xD6, 0x55, 0x70, 0x94, 0x94, 0x70, 0xCB, 0x55,
+  0x55, 0xCB, 0x70, 0x94, 0x70, 0x95, 0xA1, 0xA1,
+  0x95, 0x55, 0x55, 0x95, 0x2C, 0x95, 0x95, 0x95,
+  0x95, 0xA1, 0x6D, 0x2A, 0x2A, 0xD6, 0x55, 0x94,
+  0xE6, 0xE6, 0x47, 0x70, 0x55, 0x95, 0x20, 0x2A,
+  0xD8, 0x43, 0xC9, 0x83, 0x98, 0x79, 0x34, 0x9F,
+  0x6B, 0x43, 0x20, 0x88, 0x2B, 0x65, 0xA0, 0x20,
+  0x20, 0x20, 0x20, 0xE1, 0x70, 0x94, 0x70, 0x95,
+  0xA1, 0xA1, 0x95, 0x55, 0x55, 0x95, 0x2C, 0x95,
+  0x95, 0x95, 0x95, 0xA1, 0x6D, 0xBF, 0x2A, 0xD6,
+  0x55, 0x94, 0xE6, 0xE6, 0x47, 0x70, 0x55, 0x55,
+  0x94, 0x70, 0x94, 0x47, 0x70, 0x95, 0x2C, 0x2C,
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+  0x80, 0xD2, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0x65, 0xD0, 0x63, 0x5F, 0x29, 0x2D, 0x2D, 0xEA,
+  0x29, 0x29, 0x76, 0x50, 0x2D, 0x82, 0x49, 0x49,
+  0x3E, 0x49, 0x5C, 0xB0, 0xBA, 0x95, 0x55, 0x55,
+  0x2C, 0xA1, 0xD6, 0xD6, 0xD6, 0xA1, 0x2C, 0x2C,
+  0xA1, 0x95, 0x95, 0x55, 0xCB, 0x70, 0x70, 0x55,
+  0x2C, 0x83, 0x60, 0x76, 0x5D, 0x49, 0x49, 0x49,
+  0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
+  0x49, 0x5D, 0x89, 0xDC, 0x8B, 0x20, 0x20, 0x20,
+  0x20, 0x95, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE2, 0x32, 0x85, 0xE3, 0x29, 0x2D, 0x33, 0x2D,
+  0x2D, 0x2D, 0x6A, 0x2D, 0x33, 0x5D, 0x49, 0x82,
+  0x49, 0x49, 0x82, 0x73, 0x5C, 0x9E, 0x2C, 0x55,
+  0x2C, 0xA1, 0xD6, 0xA1, 0x2C, 0x2C, 0x95, 0x95,
+  0x2C, 0x95, 0x55, 0xCB, 0x90, 0x90, 0xCB, 0x95,
+  0x2C, 0x6D, 0x41, 0x6F, 0x3E, 0x49, 0x49, 0x49,
+  0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
+  0x49, 0x82, 0x3E, 0x4E, 0x38, 0xCA, 0x20, 0x20,
+  0x20, 0x55, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0x65,
+  0x42, 0xA0, 0xD4, 0xE3, 0x29, 0x2D, 0x82, 0x5D,
+  0x5D, 0x82, 0x82, 0x49, 0x49, 0x49, 0x49, 0x49,
+  0x49, 0x3E, 0x49, 0x49, 0x49, 0x5C, 0x56, 0xD6,
+  0xA1, 0xA1, 0xA1, 0x95, 0x55, 0x55, 0x55, 0x95,
+  0xA1, 0x55, 0x90, 0x70, 0x94, 0x70, 0x95, 0x2C,
+  0x2C, 0xD6, 0xDD, 0x6F, 0x33, 0x49, 0x49, 0x49,
+  0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
+  0x5D, 0x5D, 0x82, 0x69, 0x22, 0x62, 0x80, 0x34,
+  0x94, 0x6B, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0x65, 0xE5, 0x65, 0x6B,
+  0xD5, 0x88, 0x5B, 0xE3, 0x29, 0x5D, 0x5D, 0x5D,
+  0x5D, 0x5D, 0x5D, 0x5D, 0x49, 0x49, 0x49, 0x82,
+  0x49, 0x49, 0x89, 0x49, 0x82, 0x49, 0x71, 0xBA,
+  0x6D, 0x6D, 0xA1, 0x95, 0x55, 0xCB, 0x55, 0x55,
+  0x2C, 0x55, 0x70, 0x70, 0x70, 0x90, 0x95, 0xA1,
+  0x2C, 0xA1, 0x41, 0x76, 0x5D, 0x5D, 0x49, 0x49,
+  0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
+  0x49, 0x5D, 0x82, 0x5D, 0x89, 0x5E, 0x96, 0x65,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0xE5, 0xE5, 0xE5, 0xE5, 0x65, 0x65, 0xEC, 0xB1,
+  0x20, 0x20, 0xCA, 0x23, 0x29, 0x33, 0x49, 0x5D,
+  0x49, 0x82, 0x49, 0x49, 0x49, 0x49, 0x49, 0x82,
+  0x49, 0x82, 0x5D, 0x5D, 0x5D, 0x2D, 0x5C, 0x8F,
+  0x6D, 0xD6, 0x2C, 0x55, 0x90, 0xCB, 0x95, 0x95,
+  0x95, 0x55, 0x70, 0x94, 0x70, 0x55, 0x2C, 0xA1,
+  0x95, 0xE8, 0x5F, 0x76, 0x33, 0x5D, 0x49, 0x49,
+  0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
+  0x49, 0x49, 0x49, 0x49, 0x3E, 0x9C, 0x2F, 0x68,
+  0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
+  0x65, 0xE5, 0x65, 0xE5, 0x6B, 0x90, 0x80, 0x20,
+  0x20, 0x20, 0x4F, 0x81, 0x50, 0x3E, 0x49, 0x49,
+  0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
+  0x69, 0x69, 0x49, 0x5D, 0x2D, 0xC4, 0x46, 0xA3,
+  0xD6, 0x55, 0x70, 0x94, 0x94, 0x70, 0xCB, 0x55,
+  0x55, 0xCB, 0x70, 0x47, 0x70, 0x95, 0xA1, 0xA1,
+  0x95, 0xBD, 0x75, 0x2D, 0x33, 0x49, 0x49, 0x49,
+  0x49, 0x49, 0x5D, 0x49, 0x49, 0x49, 0x49, 0x49,
+  0x49, 0x49, 0x49, 0x49, 0x5D, 0x2D, 0xB5, 0xDB,
+  0xD6, 0x65, 0xE5, 0x65, 0xE5, 0xE5, 0x65, 0xE5,
+  0x65, 0x65, 0x6B, 0x95, 0x2B, 0x88, 0x20, 0x20,
+  0x20, 0x20, 0x8B, 0x81, 0x29, 0x33, 0x49, 0x49,
+  0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
+  0x49, 0x3E, 0x3E, 0x5E, 0x41, 0x97, 0x27, 0xD6,
+  0x55, 0x94, 0xE6, 0xE6, 0x47, 0x70, 0x55, 0x55,
+  0x94, 0x70, 0x94, 0x94, 0x70, 0x55, 0xA1, 0x2C,
+  0x6D, 0xC5, 0x39, 0x6A, 0x5D, 0x5D, 0x49, 0x49,
+  0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
+  0x49, 0x49, 0x49, 0x49, 0x3E, 0xEA, 0x30, 0x77,
+  0xE1, 0xC9, 0x94, 0x2C, 0xD6, 0xD6, 0xA1, 0x55,
+  0x47, 0x9F, 0x43, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x80, 0x91, 0x81, 0x6A, 0x2D, 0x49, 0x49,
+  0x49, 0x5D, 0x5D, 0x49, 0x49, 0x5D, 0x5D, 0x82,
+  0xEB, 0x4A, 0x41, 0xC2, 0x8F, 0xF5, 0xA1, 0x55,
+  0x94, 0x28, 0xA0, 0x47, 0x70, 0x55, 0x95, 0x95,
+  0x47, 0x70, 0x70, 0x94, 0x90, 0x95, 0xA1, 0x2C,
+  0xE8, 0xA6, 0x39, 0x76, 0x50, 0x50, 0x2D, 0x2D,
+  0x3E, 0x3E, 0x5D, 0x3E, 0x5D, 0x5D, 0x49, 0x82,
+  0x49, 0x49, 0x49, 0x82, 0x82, 0x50, 0x75, 0xE0,
+  0x57, 0x20, 0x88, 0x88, 0x20, 0x20, 0x88, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x79, 0x91, 0x81, 0x76, 0x33, 0x49, 0x49,
+  0x5D, 0x82, 0x49, 0x49, 0x3E, 0x6A, 0xEA, 0x29,
+  0xDF, 0x97, 0xBF, 0x6D, 0x6D, 0xD6, 0x55, 0x47,
+  0x28, 0x28, 0x47, 0x70, 0x55, 0x95, 0x2C, 0x2C,
+  0x95, 0x95, 0x55, 0x90, 0x90, 0x95, 0xA1, 0xA1,
+  0xD6, 0x26, 0x45, 0x81, 0x5F, 0x30, 0x48, 0x6F,
+  0x6F, 0x29, 0x29, 0x6A, 0x2D, 0x2D, 0x5D, 0x49,
+  0x49, 0x49, 0x49, 0x49, 0x2D, 0x76, 0x6E, 0x77,
+  0x5B, 0x66, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x20, 0x79, 0xA9, 0xB8, 0x39, 0x50, 0x5D, 0x5D,
+  0x5D, 0x5D, 0x3E, 0x2D, 0x29, 0x76, 0xCD, 0x37,
+  0xB9, 0xA1, 0xA1, 0x6D, 0x6D, 0x2C, 0x94, 0x28,
+  0xD5, 0xE6, 0x70, 0x55, 0x95, 0xA1, 0x2C, 0xA1,
+  0xBF, 0xA1, 0x95, 0xCB, 0x55, 0x95, 0xA1, 0x2C,
+  0x95, 0x83, 0xDE, 0x87, 0xB6, 0xBE, 0x40, 0x6E,
+  0x81, 0x81, 0x78, 0x78, 0x39, 0x6F, 0xEA, 0x2D,
+  0x2D, 0x33, 0x33, 0x33, 0x76, 0x30, 0x64, 0x54,
+  0x5B, 0x66, 0x20, 0x20, 0x66, 0x20, 0x88, 0x20,
+  0x20, 0x20, 0x88, 0x20, 0x20, 0x20, 0x20, 0x20,
+  0x88, 0x34, 0x8B, 0xF1, 0x23, 0x6F, 0x50, 0x2D,
+  0x2D, 0x6A, 0x29, 0x6F, 0x78, 0x84, 0x9B, 0xD2,
+  0x2C, 0x2C, 0xD6, 0x6D, 0x6D, 0x2C, 0x47, 0xA0,
+  0xE6, 0x70, 0x55, 0x95, 0x2C, 0xA1, 0xA1, 0xA1,
+  0xD2, 0x95, 0x55, 0xCB, 0x55, 0x2C, 0xD6, 0xA1,
+  0x95, 0x95, 0xA1, 0xD6, 0x6D, 0x6D, 0xBA, 0xF3,
+  0x8D, 0x36, 0x74, 0x36, 0xF1, 0xB8, 0x23, 0x78,
+  0x62, 0x4A, 0x29, 0x62, 0x23, 0xF1, 0x54, 0x31,
+  0x57, 0x2B, 0x90, 0x95, 0x2C, 0x2C, 0x2C, 0x2C,
+  0xA1, 0xA1, 0xA1, 0xA1, 0x2C, 0x2C, 0x2C, 0xCB,
+  0xE6, 0x7D, 0xCA, 0xB7, 0xB8, 0x75, 0x6F, 0x6F,
+  0x76, 0x6F, 0x78, 0x81, 0x53, 0xBD, 0x6D, 0x2C,
+  0x95, 0x95, 0xA1, 0x6D, 0xA1, 0x55, 0x94, 0xE6,
+  0x70, 0xCB, 0x55, 0x95, 0xA1, 0xD6, 0xD6, 0xA1,
+  0xD0, 0x94, 0x94, 0x90, 0x95, 0x2C, 0xD6, 0xA1,
+  0x95, 0x55, 0x2C, 0xA1, 0xD6, 0xA1, 0x95, 0x2C,
+  0xD6, 0x68, 0xAB, 0x6C, 0xA4, 0x77, 0x77, 0xAD,
+  0x40, 0x53, 0x6E, 0x40, 0xB7, 0x54, 0x31, 0xD7,
+  0xAC, 0xD6, 0x55, 0x55, 0x95, 0x95, 0x95, 0x55,
+  0x95, 0x2C, 0x2C, 0xA1, 0x95, 0x95, 0x2C, 0xA1,
+  0x6D, 0xD2, 0x7C, 0x54, 0xAD, 0x40, 0x6E, 0x81,
+  0x81, 0x6E, 0x36, 0xDA, 0xE8, 0xD6, 0xD6, 0x2C,
+  0x2C, 0x2C, 0xA1, 0xD6, 0x95, 0x90, 0x94, 0x47,
+  0x94, 0x94, 0x70, 0x55, 0x2C, 0xD6, 0xA1, 0x95,
+  0x95, 0x28, 0x47, 0x90, 0x95, 0x2C, 0xA1, 0x2C,
+  0x55, 0x95, 0x2C, 0xA1, 0xA1, 0x2C, 0x2C, 0x2C,
+  0x2C, 0xA1, 0x55, 0x70, 0x95, 0x2C, 0xB2, 0xB4,
+  0xC3, 0xC3, 0x54, 0x54, 0xA9, 0x31, 0xCA, 0x2A,
+  0x95, 0x90, 0x55, 0x95, 0x2C, 0xA1, 0x2C, 0x95,
+  0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0xD6,
+  0x6D, 0x2A, 0xB2, 0x4F, 0x31, 0x2E, 0xE0, 0xAD,
+  0xB7, 0xC8, 0xB4, 0xF5, 0x2C, 0xA1, 0xA1, 0xA1,
+  0x95, 0x2C, 0xA1, 0x2C, 0x95, 0x70, 0x94, 0x94,
+  0x94, 0x94, 0x70, 0x95, 0xD6, 0xD6, 0x2C, 0x95,
+  0x94, 0x28, 0x47, 0xCB, 0x95, 0x2C, 0xA1, 0xA1,
+  0x95, 0x55, 0x2C, 0xA1, 0xD6, 0xA1, 0x95, 0x95,
+  0x95, 0x2C, 0x55, 0x70, 0x70, 0x70, 0x94, 0x2C,
+  0x63, 0xBB, 0xA5, 0xD7, 0xCA, 0xB3, 0x6D, 0x2C,
+  0x55, 0x55, 0x95, 0x2C, 0x2C, 0x2C, 0x95, 0x95,
+  0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0xA1,
+  0xD6, 0x2C, 0x70, 0x95, 0xAC, 0xC0, 0xDB, 0xEF,
+  0xEF, 0xA2, 0xE8, 0x95, 0x95, 0xA1, 0xD6, 0xA1,
+  0x95, 0x55, 0x2C, 0x95, 0x55, 0x70, 0x70, 0x70,
+  0x94, 0x70, 0x55, 0xD6, 0x6D, 0x6D, 0x95, 0x55,
+  0x70, 0x47, 0x70, 0x95, 0x2C, 0x2C, 0x2C, 0xA1,
+  0x2C, 0x95, 0x2C, 0xA1, 0xD6, 0xA1, 0x95, 0x55,
+  0x55, 0x95, 0x55, 0x55, 0x55, 0x55, 0x55, 0x95,
+  0xA1, 0xF5, 0xBF, 0xBF, 0xA1, 0x95, 0x95, 0x95,
+  0x95, 0x55, 0x2C, 0x2C, 0x95, 0x55, 0x55, 0x95,
+  0x95, 0x95, 0xA1, 0xA1, 0xA1, 0xA1, 0x2C, 0xA1,
+  0x2C, 0x55, 0x70, 0x94, 0x90, 0x2C, 0x6D, 0x6D,
+  0x6D, 0xA1, 0x2C, 0x95, 0x2C, 0xA1, 0xD6, 0xA1,
+  0x2C, 0x55, 0x55, 0x95, 0x55, 0x55, 0x55, 0x55,
+  0x55, 0x95, 0xD6, 0x6D, 0xBF, 0xD6, 0x55, 0xCB,
+  0x55, 0x55, 0x55, 0x2C, 0x2C, 0x2C, 0x2C, 0xA1,
+  0xA1, 0x95, 0x2C, 0xA1, 0xA1, 0xA1, 0x2C, 0x95,
+  0x55, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0xA1,
+  0x6D, 0xBF, 0x6D, 0x2C, 0x55, 0x55, 0x95, 0x95,
+  0xCB, 0xCB, 0x55, 0x55, 0xCB, 0x55, 0x55, 0x95,
+  0x95, 0x2C, 0x2C, 0xA1, 0xA1, 0xA1, 0x2C, 0x2C,
+  0xA1, 0x95, 0xCB, 0xCB, 0x95, 0x95, 0x2C, 0x2C,
+  0x2C, 0xA1, 0x2C, 0x2C, 0x2C, 0xA1, 0xA1, 0x2C,
+  0x2C, 0x95, 0x55, 0x95, 0x95, 0x2C, 0x2C, 0x2C,
+  0x2C, 0xA1, 0x6D, 0xBF, 0x6D, 0xA1, 0x55, 0x55,
+  0x95, 0x95, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C,
+  0x2C, 0x95, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x95,
+  0x55, 0x95, 0x2C, 0x2C, 0xA1, 0xA1, 0xD6, 0xD6,
+  0x6D, 0x6D, 0xA1, 0x95, 0xCB, 0x55, 0x95, 0x55,
+  0x90, 0x70, 0xCB, 0xCB, 0x90, 0xCB, 0x95, 0x95,
+  0x2C, 0x2C, 0xA1, 0xD6, 0xA1, 0xA1, 0xA1, 0xA1,
+  0xA1, 0xA1, 0x2C, 0x95, 0x95, 0x2C, 0x2C, 0x2C,
+  0x2C, 0xA1, 0x2C, 0x95, 0x95, 0x95, 0x2C, 0x2C,
+  0x2C, 0x95, 0x55, 0x55, 0x2C, 0x2C, 0xA1, 0xA1,
+  0xD6, 0xD6, 0x6D, 0x6D, 0xA1, 0x55, 0xCB, 0x55
+};
+
+#endif
+
+#ifdef INCLUDE_LINUX_LOGOBW
+
+unsigned char linux_logo_bw[] __initdata = {
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x80, 0x00, 0x3F,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x1F,
+  0xFE, 0x1F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFE, 0x3F, 0xFF, 0x0F, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xFE, 0x7F, 0xFF, 0xC7, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF, 0xFF, 0xC3,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF,
+  0xFB, 0xE3, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFD, 0xFF, 0xFF, 0xE1, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xF9, 0xFF, 0xFF, 0xF1, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xFF, 0xFF, 0xF1,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xFF,
+  0xFF, 0xF8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xF9, 0xFF, 0xFF, 0xF8, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xF9, 0xCF, 0xC3, 0xF8, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x87, 0x81, 0xF9,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xA7,
+  0x99, 0xF9, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xF9, 0xF3, 0xBC, 0xF9, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xF9, 0xE3, 0xBC, 0xF9, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xB0, 0x3C, 0xF9,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xB0,
+  0x19, 0xF0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xF9, 0xC0, 0x03, 0xF0, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xF9, 0x80, 0x01, 0xF8, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x80, 0x01, 0xF8,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x80,
+  0x01, 0xF8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xF9, 0xC0, 0x21, 0xD8, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xF9, 0xB1, 0x80, 0xEC, 0xC0, 0x1F,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xF1, 0x90, 0x00, 0xE4,
+  0x00, 0x01, 0xFF, 0xFF, 0xFF, 0xFF, 0xF1, 0x8C,
+  0xC0, 0x7C, 0x04, 0x81, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xE3, 0x80, 0x00, 0x7C, 0x40, 0x11, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xE3, 0x80, 0x00, 0x7F, 0xD2, 0x29,
+  0xFF, 0xFF, 0xFF, 0xFF, 0x87, 0x00, 0x00, 0x3F,
+  0x80, 0x19, 0xFF, 0xFF, 0xFF, 0xFF, 0x0E, 0x00,
+  0x00, 0x3F, 0x80, 0x19, 0xFF, 0xFF, 0xFF, 0xFF,
+  0x1E, 0x00, 0x00, 0x1F, 0x80, 0x19, 0xFF, 0xFF,
+  0xFF, 0xFE, 0x1C, 0x00, 0x00, 0x1E, 0x80, 0x19,
+  0xFF, 0xFF, 0xFF, 0xFE, 0x3C, 0x00, 0x00, 0x1E,
+  0x80, 0x11, 0xFF, 0xFF, 0xFF, 0xFC, 0x7C, 0x00,
+  0x00, 0x0F, 0x80, 0x11, 0xFF, 0xFF, 0xFF, 0xFC,
+  0xF8, 0x00, 0x00, 0x0E, 0x80, 0x11, 0xFF, 0xFF,
+  0xFF, 0xFC, 0xF8, 0x00, 0x00, 0x06, 0x00, 0x11,
+  0xFF, 0xFF, 0xFF, 0xF8, 0xF8, 0x00, 0x00, 0x06,
+  0x00, 0x01, 0xFF, 0xFF, 0xFF, 0xF9, 0xF0, 0x00,
+  0x00, 0x02, 0x00, 0x09, 0xFF, 0xFF, 0xFF, 0xF1,
+  0xF0, 0x00, 0x00, 0x02, 0x80, 0x10, 0xFF, 0xFF,
+  0xFF, 0xF1, 0xE0, 0x00, 0x00, 0x00, 0x97, 0x10,
+  0xFF, 0xFF, 0xFF, 0xE3, 0xE0, 0x00, 0x00, 0x00,
+  0xDF, 0xF0, 0xFF, 0xFF, 0xFF, 0xE3, 0xC0, 0x00,
+  0x00, 0x00, 0xFF, 0xF8, 0xFF, 0xFF, 0xFF, 0xC7,
+  0xC0, 0x00, 0x00, 0x01, 0xFF, 0xF8, 0xFF, 0xFF,
+  0xFF, 0xC7, 0x80, 0x00, 0x00, 0x01, 0xFF, 0xF8,
+  0xFF, 0xFF, 0xFF, 0x8F, 0x80, 0x00, 0x00, 0x01,
+  0xFF, 0xF8, 0xFF, 0xFF, 0xFF, 0x8F, 0x80, 0x00,
+  0x00, 0x01, 0xFF, 0xF8, 0xFF, 0xFF, 0xFF, 0x9F,
+  0x80, 0x00, 0x00, 0x01, 0xFF, 0xF8, 0xFF, 0xFF,
+  0xFF, 0x9F, 0x80, 0x00, 0x00, 0x01, 0x80, 0x18,
+  0xFF, 0xFF, 0xFF, 0x9E, 0x80, 0x00, 0x00, 0x03,
+  0xA8, 0x11, 0xFF, 0xFF, 0xFF, 0x9F, 0x80, 0x00,
+  0x00, 0x02, 0x00, 0x01, 0xFF, 0xFF, 0xFF, 0x99,
+  0x80, 0x00, 0x00, 0x00, 0x00, 0x09, 0xFF, 0xFF,
+  0xFF, 0x00, 0x80, 0x00, 0x00, 0x01, 0xC0, 0x01,
+  0xFF, 0xFF, 0xFE, 0x20, 0x60, 0x00, 0x00, 0x00,
+  0xFF, 0xC3, 0xFF, 0xFF, 0xF8, 0x00, 0x30, 0x00,
+  0x00, 0x00, 0xFF, 0x0F, 0xFF, 0xFF, 0xC0, 0x40,
+  0x38, 0x00, 0x00, 0x00, 0xFE, 0x47, 0xFF, 0xFF,
+  0x81, 0x00, 0x1C, 0x00, 0x00, 0x00, 0xFC, 0x23,
+  0xFF, 0xFF, 0x90, 0x00, 0x1E, 0x00, 0x00, 0x00,
+  0x78, 0x11, 0xFF, 0xFF, 0x80, 0x00, 0x0F, 0x80,
+  0x00, 0x00, 0x00, 0x01, 0xFF, 0xFF, 0x80, 0x00,
+  0x07, 0xC0, 0x00, 0x00, 0x00, 0x08, 0xFF, 0xFF,
+  0xC0, 0x00, 0x07, 0xC0, 0x00, 0x00, 0x00, 0x04,
+  0x7F, 0xFF, 0x80, 0x00, 0x03, 0xC0, 0x00, 0x10,
+  0x00, 0x00, 0x1F, 0xFF, 0x80, 0x00, 0x01, 0x80,
+  0x00, 0x30, 0x00, 0x00, 0x0F, 0xFF, 0x80, 0x00,
+  0x00, 0x00, 0x00, 0x70, 0x00, 0x01, 0x4F, 0xFF,
+  0x80, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00,
+  0x0F, 0xFF, 0xC0, 0x00, 0x00, 0x80, 0x03, 0xF0,
+  0x00, 0x00, 0x8F, 0xFF, 0x80, 0x00, 0x00, 0x40,
+  0x0F, 0xF0, 0x00, 0x04, 0x1F, 0xFF, 0x80, 0x00,
+  0x00, 0x7F, 0xFF, 0xF0, 0x00, 0x10, 0x1F, 0xFF,
+  0xC0, 0x00, 0x00, 0x7F, 0xFF, 0xF0, 0x00, 0x40,
+  0xFF, 0xFF, 0x98, 0x00, 0x00, 0xFF, 0xFF, 0xF0,
+  0x00, 0x83, 0xFF, 0xFF, 0x81, 0xE0, 0x01, 0xFF,
+  0xFF, 0xF8, 0x02, 0x07, 0xFF, 0xFF, 0x80, 0x3F,
+  0x07, 0xE0, 0x00, 0x1C, 0x0C, 0x1F, 0xFF, 0xFF,
+  0xF8, 0x03, 0xFF, 0x80, 0x00, 0x1F, 0x78, 0x1F,
+  0xFF, 0xFF, 0xFF, 0x80, 0x7F, 0x00, 0x07, 0x0F,
+  0xF0, 0x7F, 0xFF, 0xFF, 0xFF, 0xFE, 0x0C, 0x07,
+  0xFF, 0x83, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0x00, 0x1F, 0xFF, 0xC0, 0x03, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF8, 0x07, 0xFF,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+};
+
+#endif
+
+#ifdef INCLUDE_LINUX_LOGO16
+
+unsigned char linux_logo16_red[] __initdata = {
+    0x00, 0x90, 0xb0, 0x9c, 0xf7, 0x35, 0x83, 0xa5,
+    0x65, 0x8f, 0x98, 0xc9, 0xdb, 0xe1, 0xe7, 0xf8
+};
+
+unsigned char linux_logo16_green[] __initdata = {
+    0x00, 0x90, 0xb0, 0x9c, 0xf7, 0x2e, 0x83, 0xa5,
+    0x65, 0x6e, 0x98, 0x89, 0xbf, 0xac, 0xda, 0xf8
+};
+
+unsigned char linux_logo16_blue[] __initdata = {
+    0x00, 0x90, 0xaf, 0x9c, 0xf7, 0x2b, 0x82, 0xa5,
+    0x65, 0x41, 0x97, 0x1e, 0x60, 0x29, 0xa5, 0xf8
+};
+
+unsigned char linux_logo16[] __initdata = {
+    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
+    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa1, 0x11, 0x11,
+    0x61, 0x16, 0x66, 0x66, 0x11, 0x11, 0x11, 0x11,
+    0x11, 0x11, 0x1a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
+    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
+    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
+    0xaa, 0xaa, 0xaa, 0xaa, 0x33, 0xa8, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x87, 0x77, 0x77, 0x77, 0x77,
+    0x77, 0x77, 0x73, 0x33, 0x33, 0x3a, 0xaa, 0xaa,
+    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
+    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
+    0xaa, 0xaa, 0xa3, 0x33, 0x33, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x77, 0x77, 0x77, 0x77,
+    0x77, 0x27, 0x77, 0x77, 0x77, 0x33, 0x3a, 0xaa,
+    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
+    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
+    0xaa, 0xa3, 0x33, 0x33, 0x30, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x55, 0x50, 0x08, 0x33, 0x77, 0x77,
+    0x77, 0x72, 0x72, 0x27, 0x77, 0x77, 0x33, 0x33,
+    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
+    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
+    0xa3, 0x33, 0x33, 0x77, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x58, 0x85, 0x00, 0x11, 0x11, 0xaa,
+    0xa3, 0x37, 0x77, 0x72, 0x22, 0x22, 0x77, 0x73,
+    0x33, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
+    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa3,
+    0x33, 0x37, 0x77, 0x33, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x56, 0x85, 0x00, 0x06, 0x66, 0x11,
+    0x11, 0x1a, 0xa3, 0x37, 0x77, 0x72, 0x22, 0x77,
+    0x73, 0x33, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
+    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x33,
+    0x33, 0x33, 0x33, 0x30, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x55, 0x00, 0x00, 0x06, 0x66, 0x66,
+    0x66, 0x66, 0x11, 0x1a, 0xa3, 0x77, 0x72, 0x22,
+    0x77, 0x73, 0x3a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
+    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x33, 0x33,
+    0x33, 0x33, 0x33, 0xa0, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x11,
+    0x66, 0x66, 0x66, 0x66, 0x11, 0xa3, 0x77, 0x22,
+    0x22, 0x77, 0x33, 0x33, 0xaa, 0xaa, 0xaa, 0xaa,
+    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x33, 0x33, 0x33,
+    0x33, 0x3a, 0xa1, 0x10, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x33,
+    0xaa, 0x11, 0x16, 0x66, 0x66, 0x61, 0x1a, 0x37,
+    0x22, 0x22, 0x77, 0x33, 0x3a, 0xaa, 0xaa, 0xaa,
+    0xaa, 0xaa, 0xaa, 0xaa, 0xa3, 0x33, 0x33, 0x33,
+    0x3a, 0xa1, 0x11, 0x10, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x02, 0x22,
+    0x22, 0x77, 0x3a, 0x11, 0x66, 0x66, 0x66, 0x1a,
+    0x37, 0x22, 0x22, 0x77, 0x33, 0x3a, 0xaa, 0xaa,
+    0xaa, 0xaa, 0xaa, 0xaa, 0x33, 0x33, 0x33, 0x3a,
+    0xa1, 0x11, 0x11, 0x10, 0x00, 0x00, 0x50, 0x00,
+    0x00, 0x05, 0x80, 0x50, 0x00, 0x00, 0x07, 0x72,
+    0x22, 0x22, 0x22, 0x73, 0xa1, 0x66, 0x66, 0x61,
+    0x1a, 0x77, 0x22, 0x27, 0x73, 0x33, 0xaa, 0xaa,
+    0xaa, 0xaa, 0xaa, 0xaa, 0x33, 0x33, 0x3a, 0xaa,
+    0x11, 0x11, 0x1a, 0xa0, 0x08, 0x71, 0x05, 0x00,
+    0x00, 0x12, 0x22, 0x50, 0x00, 0x00, 0x07, 0x77,
+    0x77, 0x72, 0x22, 0x22, 0x27, 0x31, 0x16, 0x66,
+    0x61, 0x13, 0x77, 0x22, 0x77, 0x33, 0x3a, 0xaa,
+    0xaa, 0xaa, 0xaa, 0xa3, 0x33, 0x33, 0xaa, 0xa1,
+    0x11, 0x1a, 0x33, 0x70, 0x07, 0x2e, 0x70, 0x00,
+    0x01, 0x44, 0x42, 0x60, 0x00, 0x00, 0x02, 0x22,
+    0x22, 0x22, 0x22, 0x22, 0x22, 0x27, 0x31, 0x66,
+    0x66, 0x61, 0xa3, 0x72, 0x22, 0x77, 0x33, 0xaa,
+    0xaa, 0xaa, 0xa3, 0x33, 0x33, 0xaa, 0xaa, 0x11,
+    0x1a, 0x33, 0x77, 0x30, 0x04, 0x82, 0x40, 0x00,
+    0x54, 0x48, 0x54, 0x40, 0x00, 0x00, 0x01, 0xaa,
+    0x32, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x31,
+    0x66, 0x66, 0x11, 0x37, 0x22, 0x27, 0x73, 0x3a,
+    0xaa, 0xaa, 0xa3, 0x33, 0x3a, 0xaa, 0xaa, 0xaa,
+    0xa3, 0x77, 0xaa, 0x10, 0x50, 0x08, 0x46, 0x05,
+    0x54, 0x80, 0x50, 0x42, 0x00, 0x00, 0x08, 0x66,
+    0x66, 0x1a, 0x32, 0x22, 0x22, 0x22, 0x22, 0x27,
+    0x31, 0x66, 0x66, 0x13, 0x72, 0x22, 0x77, 0x33,
+    0xaa, 0xaa, 0xaa, 0x33, 0xaa, 0xa1, 0xaa, 0xa3,
+    0x37, 0xa1, 0x1a, 0x30, 0x50, 0x06, 0x26, 0x00,
+    0x54, 0x00, 0x00, 0x44, 0x00, 0x00, 0x08, 0xe2,
+    0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0x22, 0x22,
+    0x27, 0xa6, 0x66, 0x61, 0xa7, 0x72, 0x27, 0x73,
+    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x33,
+    0x31, 0x11, 0x37, 0x70, 0x02, 0x00, 0xab, 0xbb,
+    0xb6, 0x00, 0x00, 0xf4, 0x00, 0x00, 0xee, 0xee,
+    0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0x22,
+    0x22, 0x23, 0x16, 0x66, 0x1a, 0x37, 0x22, 0x77,
+    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa3, 0x3a,
+    0x11, 0xa7, 0x33, 0x10, 0x04, 0x09, 0xbd, 0xdd,
+    0xbd, 0xd0, 0x04, 0x45, 0x00, 0x0e, 0xee, 0xee,
+    0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0x22,
+    0x22, 0x22, 0x71, 0x66, 0x66, 0x13, 0x72, 0x27,
+    0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x33, 0x11,
+    0xa3, 0x73, 0xa1, 0x60, 0x08, 0xbd, 0xdd, 0xdd,
+    0xdd, 0xdd, 0xdb, 0x90, 0x00, 0x02, 0xec, 0xee,
+    0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xce, 0x22,
+    0x22, 0x22, 0x27, 0xa6, 0x66, 0x61, 0x37, 0x27,
+    0x1a, 0xaa, 0xaa, 0xaa, 0xaa, 0xa3, 0xa1, 0x1a,
+    0x33, 0xa1, 0x16, 0x60, 0x0b, 0xbd, 0xdd, 0xdd,
+    0xcd, 0xdd, 0xdd, 0xd9, 0x00, 0x00, 0xec, 0xcc,
+    0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xce, 0xa2,
+    0x22, 0x22, 0x22, 0x7a, 0x66, 0x66, 0x13, 0x77,
+    0x1a, 0xaa, 0xaa, 0xaa, 0xaa, 0x3a, 0x11, 0x33,
+    0xaa, 0x11, 0x66, 0x60, 0x9b, 0xdd, 0xdd, 0xdd,
+    0xcd, 0xdd, 0xdb, 0xb9, 0x00, 0x00, 0xec, 0xcc,
+    0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xee, 0x61,
+    0x72, 0x22, 0x22, 0x22, 0xa1, 0x66, 0x61, 0x37,
+    0x1a, 0xaa, 0xaa, 0xaa, 0xa3, 0xa1, 0x13, 0x3a,
+    0x11, 0x11, 0x11, 0x10, 0x5b, 0xdd, 0xdd, 0xdc,
+    0xdd, 0xdd, 0xbd, 0xd9, 0x00, 0x00, 0xec, 0xcc,
+    0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xee, 0x86,
+    0x17, 0x22, 0x22, 0x22, 0x23, 0x16, 0x66, 0xaa,
+    0xaa, 0xa3, 0x3a, 0xaa, 0xaa, 0x1a, 0x3a, 0xa1,
+    0x11, 0x11, 0x1a, 0x70, 0x05, 0xbd, 0xdd, 0xdd,
+    0xdb, 0x5b, 0xdd, 0xb0, 0x00, 0x60, 0x2e, 0xcc,
+    0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xe6, 0x88,
+    0x66, 0x32, 0x22, 0x22, 0x22, 0x36, 0x66, 0x11,
+    0x33, 0x33, 0x3a, 0xaa, 0x11, 0xaa, 0xaa, 0xa1,
+    0x11, 0x1a, 0x3a, 0x60, 0x02, 0x99, 0xbb, 0xb9,
+    0x9b, 0xbb, 0xbc, 0x22, 0x00, 0x86, 0x5e, 0xcc,
+    0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xe1, 0x68,
+    0x86, 0x63, 0x22, 0x22, 0x22, 0x2a, 0x66, 0x66,
+    0x33, 0x33, 0xaa, 0xaa, 0x1a, 0xaa, 0xaa, 0x11,
+    0x1a, 0xa7, 0x68, 0x80, 0x02, 0x2b, 0xbd, 0xbb,
+    0xbb, 0xb9, 0x22, 0x22, 0x00, 0x06, 0x6e, 0xcc,
+    0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xc7, 0xa6,
+    0x88, 0x86, 0x32, 0x22, 0x22, 0x27, 0xa6, 0x66,
+    0x33, 0x3a, 0xaa, 0xa1, 0xaa, 0xaa, 0xa1, 0x11,
+    0xa3, 0xa6, 0x88, 0x80, 0x02, 0x22, 0x9b, 0xbb,
+    0xbb, 0x22, 0x24, 0xf4, 0x60, 0x00, 0x0c, 0xcc,
+    0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xc2, 0x21,
+    0x68, 0x88, 0x63, 0x22, 0x22, 0x22, 0x71, 0x66,
+    0x33, 0x3a, 0x11, 0x11, 0xaa, 0xaa, 0x11, 0xaa,
+    0x71, 0x88, 0x88, 0x00, 0x02, 0xe2, 0x26, 0x99,
+    0x22, 0x22, 0x4f, 0xf4, 0x40, 0x00, 0x0c, 0xcc,
+    0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0x22, 0x22,
+    0x16, 0x88, 0x86, 0xa2, 0x22, 0x22, 0x27, 0x11,
+    0x33, 0xa1, 0x11, 0x11, 0xaa, 0x31, 0x1a, 0xa3,
+    0x68, 0x88, 0x81, 0x00, 0x54, 0x42, 0x22, 0x22,
+    0x22, 0x44, 0xff, 0xff, 0x48, 0x00, 0x00, 0x99,
+    0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0x99, 0x22, 0x22,
+    0x21, 0x88, 0x88, 0x6a, 0x22, 0x22, 0x22, 0x31,
+    0x3a, 0xa1, 0x11, 0x1a, 0xa3, 0x11, 0x33, 0x36,
+    0x88, 0x86, 0x30, 0x00, 0x4f, 0x44, 0x22, 0x22,
+    0x24, 0xff, 0xff, 0xff, 0x44, 0x00, 0x00, 0x99,
+    0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0x95, 0x22, 0x72,
+    0x22, 0x18, 0x88, 0x86, 0x32, 0x22, 0x22, 0x27,
+    0xaa, 0x11, 0x11, 0x1a, 0x31, 0x13, 0x33, 0x68,
+    0x88, 0x6a, 0x00, 0x02, 0x4f, 0x4f, 0x42, 0x24,
+    0x4f, 0xff, 0xff, 0xff, 0xf4, 0x50, 0x00, 0x99,
+    0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0x99, 0x22, 0x73,
+    0x72, 0x26, 0x88, 0x88, 0x63, 0x22, 0x22, 0x22,
+    0x11, 0x11, 0x11, 0xa3, 0xa1, 0x73, 0xa6, 0x88,
+    0x81, 0xa5, 0x00, 0x04, 0x4f, 0x4f, 0x44, 0x4f,
+    0xff, 0xff, 0xff, 0xff, 0xf4, 0x40, 0x00, 0x99,
+    0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0x99, 0x12, 0x27,
+    0xaa, 0x22, 0x68, 0x55, 0x86, 0x72, 0x22, 0x22,
+    0x11, 0x11, 0x1a, 0x33, 0x13, 0x3a, 0x18, 0x88,
+    0x1a, 0x10, 0x00, 0x44, 0x4f, 0x4f, 0xff, 0x4f,
+    0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, 0x00, 0x99,
+    0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0x99, 0x61, 0x22,
+    0x3a, 0xa2, 0x26, 0x85, 0x58, 0x67, 0x22, 0x22,
+    0x61, 0x61, 0x1a, 0x7a, 0x37, 0x31, 0x88, 0x81,
+    0x11, 0x00, 0x05, 0xe4, 0x44, 0xff, 0xff, 0xff,
+    0x4f, 0xf4, 0x44, 0xff, 0xff, 0xf5, 0x00, 0x99,
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+    0x88, 0x88, 0x88, 0x66, 0x36, 0x63, 0x26, 0x86,
+    0x86, 0x36, 0x86, 0x11, 0x66, 0x66, 0x76, 0x61,
+    0x88, 0x88, 0x81, 0x22, 0x22, 0x38, 0x85, 0x58,
+    0x37, 0x22, 0x21, 0x68, 0xa2, 0x31, 0x68, 0x55,
+    0x55, 0x81, 0x22, 0x22, 0xa8, 0x88, 0x88, 0x68,
+    0x86, 0x88, 0x68, 0x81, 0x36, 0x17, 0x21, 0x68,
+    0x86, 0x16, 0x66, 0x26, 0x66, 0x61, 0x36, 0x66,
+    0x68, 0x88, 0x86, 0x27, 0x22, 0x28, 0x88, 0x88,
+    0x17, 0x72, 0x2a, 0x66, 0xa2, 0x22, 0x36, 0x55,
+    0x55, 0x58, 0x37, 0x3a, 0x16, 0x66, 0x66, 0x66,
+    0x66, 0x18, 0x88, 0x67, 0x16, 0x12, 0x71, 0x68,
+    0x81, 0x68, 0x61, 0x76, 0x66, 0x6a, 0x16, 0x66,
+    0x88, 0x88, 0x86, 0x77, 0x22, 0x26, 0x88, 0x88,
+    0x13, 0x37, 0x71, 0x66, 0xa2, 0x33, 0x2a, 0x85,
+    0x55, 0x55, 0x17, 0x73, 0x16, 0x66, 0x66, 0x68,
+    0x63, 0x88, 0x88, 0xa2, 0x66, 0xa2, 0xa6, 0x88,
+    0x61, 0x68, 0x6a, 0x76, 0x66, 0x6a, 0x66, 0x6a
+};
+
+#endif
diff --git a/qemu/roms/u-boot/include/lmb.h b/qemu/roms/u-boot/include/lmb.h
new file mode 100644
index 000000000..6b6959fd8
--- /dev/null
+++ b/qemu/roms/u-boot/include/lmb.h
@@ -0,0 +1,58 @@
+#ifndef _LINUX_LMB_H
+#define _LINUX_LMB_H
+#ifdef __KERNEL__
+
+#include <asm/types.h>
+/*
+ * Logical memory blocks.
+ *
+ * Copyright (C) 2001 Peter Bergner, IBM Corp.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#define MAX_LMB_REGIONS 8
+
+struct lmb_property {
+	phys_addr_t base;
+	phys_size_t size;
+};
+
+struct lmb_region {
+	unsigned long cnt;
+	phys_size_t size;
+	struct lmb_property region[MAX_LMB_REGIONS+1];
+};
+
+struct lmb {
+	struct lmb_region memory;
+	struct lmb_region reserved;
+};
+
+extern struct lmb lmb;
+
+extern void lmb_init(struct lmb *lmb);
+extern long lmb_add(struct lmb *lmb, phys_addr_t base, phys_size_t size);
+extern long lmb_reserve(struct lmb *lmb, phys_addr_t base, phys_size_t size);
+extern phys_addr_t lmb_alloc(struct lmb *lmb, phys_size_t size, ulong align);
+extern phys_addr_t lmb_alloc_base(struct lmb *lmb, phys_size_t size, ulong align,
+			    phys_addr_t max_addr);
+extern phys_addr_t __lmb_alloc_base(struct lmb *lmb, phys_size_t size, ulong align,
+			      phys_addr_t max_addr);
+extern int lmb_is_reserved(struct lmb *lmb, phys_addr_t addr);
+extern long lmb_free(struct lmb *lmb, phys_addr_t base, phys_size_t size);
+
+extern void lmb_dump_all(struct lmb *lmb);
+
+static inline phys_size_t
+lmb_size_bytes(struct lmb_region *type, unsigned long region_nr)
+{
+	return type->region[region_nr].size;
+}
+
+void board_lmb_reserve(struct lmb *lmb);
+void arch_lmb_reserve(struct lmb *lmb);
+
+#endif /* __KERNEL__ */
+
+#endif /* _LINUX_LMB_H */
diff --git a/qemu/roms/u-boot/include/logbuff.h b/qemu/roms/u-boot/include/logbuff.h
new file mode 100644
index 000000000..625feb9f9
--- /dev/null
+++ b/qemu/roms/u-boot/include/logbuff.h
@@ -0,0 +1,49 @@
+/*
+ * (C) Copyright 2002-2007
+ * Detlev Zundel, dzu@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _LOGBUFF_H
+#define _LOGBUFF_H
+
+#ifdef CONFIG_LOGBUFFER
+
+#define LOGBUFF_MAGIC	0xc0de4ced	/* Forced by code, eh!	*/
+#define LOGBUFF_LEN	(16384)	/* Must be 16k right now */
+#define LOGBUFF_MASK	(LOGBUFF_LEN-1)
+#define LOGBUFF_OVERHEAD (4096) /* Logbuffer overhead for extra info */
+#define LOGBUFF_RESERVE (LOGBUFF_LEN+LOGBUFF_OVERHEAD)
+
+/* The mapping used here has to be the same as in setup_ext_logbuff ()
+   in linux/kernel/printk */
+
+typedef struct {
+	union {
+		struct {
+			unsigned long	tag;
+			unsigned long	start;
+			unsigned long	con;
+			unsigned long	end;
+			unsigned long	chars;
+		} v2;
+		struct {
+			unsigned long	dummy;
+			unsigned long	tag;
+			unsigned long	start;
+			unsigned long	size;
+			unsigned long	chars;
+		} v1;
+	};
+	unsigned char	buf[0];
+} logbuff_t;
+
+int drv_logbuff_init (void);
+void logbuff_init_ptrs (void);
+void logbuff_log(char *msg);
+void logbuff_reset (void);
+unsigned long logbuffer_base (void);
+
+#endif /* CONFIG_LOGBUFFER */
+
+#endif /* _LOGBUFF_H */
diff --git a/qemu/roms/u-boot/include/lxt971a.h b/qemu/roms/u-boot/include/lxt971a.h
new file mode 100644
index 000000000..2a3f66041
--- /dev/null
+++ b/qemu/roms/u-boot/include/lxt971a.h
@@ -0,0 +1,132 @@
+/***********************************************************************
+ *
+ * Copyright (C) 2004 by FS Forth-Systeme GmbH.
+ * All rights reserved.
+ *
+ * $Id: ns9750_eth.h,v 1.2 2004/02/24 13:25:39 mpietrek Exp $
+ * @Author: Markus Pietrek
+ * @References: [1] NS9750 Hardware Reference, December 2003
+ *              [2] Intel LXT971 Datasheet #249414 Rev. 02
+ *              [3] NS7520 Linux Ethernet Driver
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __LXT971A_H__
+#define __LXT971A_H__
+
+/* PHY definitions (LXT971A) [2] */
+#define PHY_LXT971_PORT_CFG		(0x10)
+#define PHY_LXT971_STAT2		(0x11)
+#define PHY_LXT971_INT_ENABLE		(0x12)
+#define PHY_LXT971_INT_STATUS		(0x13)
+#define PHY_LXT971_LED_CFG		(0x14)
+#define PHY_LXT971_DIG_CFG		(0x1A)
+#define PHY_LXT971_TX_CTRL		(0x1E)
+
+/* PORT_CFG Port Configuration Register Bit Fields */
+#define PHY_LXT971_PORT_CFG_RES1        (0x8000)
+#define PHY_LXT971_PORT_CFG_FORCE_LNK   (0x4000)
+#define PHY_LXT971_PORT_CFG_TX_DISABLE  (0x2000)
+#define PHY_LXT971_PORT_CFG_BYPASS_SCR  (0x1000)
+#define PHY_LXT971_PORT_CFG_RES2        (0x0800)
+#define PHY_LXT971_PORT_CFG_JABBER      (0x0400)
+#define PHY_LXT971_PORT_CFG_SQE	        (0x0200)
+#define PHY_LXT971_PORT_CFG_TP_LOOPBACK (0x0100)
+#define PHY_LXT971_PORT_CFG_CRS_SEL     (0x0080)
+#define PHY_LXT971_PORT_CFG_SLEEP_MODE  (0x0040)
+#define PHY_LXT971_PORT_CFG_PRE_EN      (0x0020)
+#define PHY_LXT971_PORT_CFG_SLEEP_T_MA  (0x0018)
+#define PHY_LXT971_PORT_CFG_SLEEP_T_104 (0x0010)
+#define PHY_LXT971_PORT_CFG_SLEEP_T_200 (0x0001)
+#define PHY_LXT971_PORT_CFG_SLEEP_T_304 (0x0000)
+#define PHY_LXT971_PORT_CFG_FLT_CODE_EN (0x0004)
+#define PHY_LXT971_PORT_CFG_ALT_NP      (0x0002)
+#define PHY_LXT971_PORT_CFG_FIBER_SEL   (0x0001)
+
+/* STAT2 Status Register #2 Bit Fields */
+#define PHY_LXT971_STAT2_RES1		(0x8000)
+#define PHY_LXT971_STAT2_100BTX		(0x4000)
+#define PHY_LXT971_STAT2_TX_STATUS	(0x2000)
+#define PHY_LXT971_STAT2_RX_STATUS	(0x1000)
+#define PHY_LXT971_STAT2_COL_STATUS	(0x0800)
+#define PHY_LXT971_STAT2_LINK		(0x0400)
+#define PHY_LXT971_STAT2_DUPLEX_MODE	(0x0200)
+#define PHY_LXT971_STAT2_AUTO_NEG	(0x0100)
+#define PHY_LXT971_STAT2_AUTO_NEG_COMP	(0x0080)
+#define PHY_LXT971_STAT2_RES2		(0x0040)
+#define PHY_LXT971_STAT2_POLARITY	(0x0020)
+#define PHY_LXT971_STAT2_PAUSE		(0x0010)
+#define PHY_LXT971_STAT2_ERROR		(0x0008)
+#define PHY_LXT971_STAT2_RES3		(0x0007)
+
+/* INT_ENABLE Interrupt Enable Register Bit Fields */
+#define PHY_LXT971_INT_ENABLE_RES1      (0xFF00)
+#define PHY_LXT971_INT_ENABLE_ANMSK     (0x0080)
+#define PHY_LXT971_INT_ENABLE_SPEEDMSK  (0x0040)
+#define PHY_LXT971_INT_ENABLE_DUPLEXMSK (0x0020)
+#define PHY_LXT971_INT_ENABLE_LINKMSK   (0x0010)
+#define PHY_LXT971_INT_ENABLE_RES2      (0x000C)
+#define PHY_LXT971_INT_ENABLE_INTEN     (0x0002)
+#define PHY_LXT971_INT_ENABLE_TINT      (0x0001)
+
+/* INT_STATUS Interrupt Status Register Bit Fields */
+#define PHY_LXT971_INT_STATUS_RES1      (0xFF00)
+#define PHY_LXT971_INT_STATUS_ANDONE    (0x0080)
+#define PHY_LXT971_INT_STATUS_SPEEDCHG  (0x0040)
+#define PHY_LXT971_INT_STATUS_DUPLEXCHG (0x0020)
+#define PHY_LXT971_INT_STATUS_LINKCHG   (0x0010)
+#define PHY_LXT971_INT_STATUS_RES2      (0x0008)
+#define PHY_LXT971_INT_STATUS_MDINT     (0x0004)
+#define PHY_LXT971_INT_STATUS_RES3      (0x0003)
+
+/* LED_CFG Interrupt LED Configuration Register Bit Fields */
+#define PHY_LXT971_LED_CFG_SHIFT_LED1   (0x000C)
+#define PHY_LXT971_LED_CFG_SHIFT_LED2   (0x0008)
+#define PHY_LXT971_LED_CFG_SHIFT_LED3   (0x0004)
+#define PHY_LXT971_LED_CFG_LEDFREQ_MA	(0x000C)
+#define PHY_LXT971_LED_CFG_LEDFREQ_RES	(0x000C)
+#define PHY_LXT971_LED_CFG_LEDFREQ_100	(0x0008)
+#define PHY_LXT971_LED_CFG_LEDFREQ_60	(0x0004)
+#define PHY_LXT971_LED_CFG_LEDFREQ_30	(0x0000)
+#define PHY_LXT971_LED_CFG_PULSE_STR    (0x0002)
+#define PHY_LXT971_LED_CFG_RES1         (0x0001)
+
+/* only one of these values must be shifted for each SHIFT_LED?  */
+#define PHY_LXT971_LED_CFG_UNUSED1      (0x000F)
+#define PHY_LXT971_LED_CFG_DUPLEX_COL   (0x000E)
+#define PHY_LXT971_LED_CFG_LINK_ACT     (0x000D)
+#define PHY_LXT971_LED_CFG_LINK_RX      (0x000C)
+#define PHY_LXT971_LED_CFG_TEST_BLK_SLW (0x000B)
+#define PHY_LXT971_LED_CFG_TEST_BLK_FST (0x000A)
+#define PHY_LXT971_LED_CFG_TEST_OFF     (0x0009)
+#define PHY_LXT971_LED_CFG_TEST_ON      (0x0008)
+#define PHY_LXT971_LED_CFG_RX_OR_TX     (0x0007)
+#define PHY_LXT971_LED_CFG_UNUSED2      (0x0006)
+#define PHY_LXT971_LED_CFG_DUPLEX       (0x0005)
+#define PHY_LXT971_LED_CFG_LINK	        (0x0004)
+#define PHY_LXT971_LED_CFG_COLLISION    (0x0003)
+#define PHY_LXT971_LED_CFG_RECEIVE      (0x0002)
+#define PHY_LXT971_LED_CFG_TRANSMIT     (0x0001)
+#define PHY_LXT971_LED_CFG_SPEED        (0x0000)
+
+/* DIG_CFG Digitial Configuration Register Bit Fields */
+#define PHY_LXT971_DIG_CFG_RES1		(0xF000)
+#define PHY_LXT971_DIG_CFG_MII_DRIVE	(0x0800)
+#define PHY_LXT971_DIG_CFG_RES2		(0x0400)
+#define PHY_LXT971_DIG_CFG_SHOW_SYMBOL	(0x0200)
+#define PHY_LXT971_DIG_CFG_RES3		(0x01FF)
+
+#define PHY_LXT971_MDIO_MAX_CLK		(8000000)
+#define PHY_MDIO_MAX_CLK		(2500000)
+
+/* TX_CTRL Transmit Control Register Bit Fields
+   documentation is buggy for this register, therefore setting not included */
+
+typedef enum
+{
+	PHY_NONE    = 0x0000, /* no PHY detected yet */
+	PHY_LXT971A = 0x0013
+} PhyType;
+
+#endif /* __LXT971A_H__ */
diff --git a/qemu/roms/u-boot/include/lynxkdi.h b/qemu/roms/u-boot/include/lynxkdi.h
new file mode 100644
index 000000000..8e45a81f9
--- /dev/null
+++ b/qemu/roms/u-boot/include/lynxkdi.h
@@ -0,0 +1,25 @@
+/*
+ * (C) Copyright 2003
+ * Orbacom Systems, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __LYNXKDI_H__
+#define __LYNXKDI_H__
+
+
+/* Boot parameter struct passed to kernel
+ */
+typedef struct lynxos_bootparms_t {
+	uint8_t		rsvd1[2];	/* Reserved			*/
+	uint8_t		ethaddr[6];	/* Ethernet address		*/
+	uint16_t	flags;		/* Boot flags			*/
+	uint32_t	rate;		/* System frequency		*/
+	uint32_t	clock_ref;	/* Time reference		*/
+	uint32_t	dramsz;		/* DRAM size			*/
+	uint32_t	rsvd2;		/* Reserved			*/
+} lynxos_bootparms_t;
+
+
+#endif	/* __LYNXKDI_H__ */
diff --git a/qemu/roms/u-boot/include/lzma/LzmaDec.h b/qemu/roms/u-boot/include/lzma/LzmaDec.h
new file mode 100644
index 000000000..c41804b34
--- /dev/null
+++ b/qemu/roms/u-boot/include/lzma/LzmaDec.h
@@ -0,0 +1,15 @@
+/*
+ * Fake include for LzmaDec.h
+ *
+ * Copyright (C) 2007-2009 Industrie Dial Face S.p.A.
+ * Luigi 'Comio' Mantellini (luigi.mantellini@idf-hit.com)
+ *
+ * SPDX-License-Identifier:	GPL-2.0+ 
+ */
+
+#ifndef __LZMADEC_H__FAKE__
+#define __LZMADEC_H__FAKE__
+
+#include "../../lib/lzma/LzmaDec.h"
+
+#endif
diff --git a/qemu/roms/u-boot/include/lzma/LzmaTools.h b/qemu/roms/u-boot/include/lzma/LzmaTools.h
new file mode 100644
index 000000000..994e412ee
--- /dev/null
+++ b/qemu/roms/u-boot/include/lzma/LzmaTools.h
@@ -0,0 +1,15 @@
+/*
+ * Fake include for LzmaTools.h
+ *
+ * Copyright (C) 2007-2009 Industrie Dial Face S.p.A.
+ * Luigi 'Comio' Mantellini (luigi.mantellini@idf-hit.com)
+ *
+ * SPDX-License-Identifier:	GPL-2.0+ 
+ */
+
+#ifndef __LZMATOOLS_H__FAKE__
+#define __LZMATOOLS_H__FAKE__
+
+#include "../../lib/lzma/LzmaTools.h"
+
+#endif
diff --git a/qemu/roms/u-boot/include/lzma/LzmaTypes.h b/qemu/roms/u-boot/include/lzma/LzmaTypes.h
new file mode 100644
index 000000000..31ef31c83
--- /dev/null
+++ b/qemu/roms/u-boot/include/lzma/LzmaTypes.h
@@ -0,0 +1,20 @@
+/*
+ * Fake include for Types.h
+ *
+ * Copyright (C) 2007-2009 Industrie Dial Face S.p.A.
+ * Luigi 'Comio' Mantellini (luigi.mantellini@idf-hit.com)
+ *
+ * SPDX-License-Identifier:	GPL-2.0+ 
+ */
+
+#ifndef __TYPES_H__FAKE__
+#define __TYPES_H__FAKE__
+
+/*
+ *This avoids the collition with zlib.h Byte definition
+ */
+#define Byte LZByte
+
+#include "../../lib/lzma/Types.h"
+
+#endif
diff --git a/qemu/roms/u-boot/include/malloc.h b/qemu/roms/u-boot/include/malloc.h
new file mode 100644
index 000000000..c33f3b494
--- /dev/null
+++ b/qemu/roms/u-boot/include/malloc.h
@@ -0,0 +1,945 @@
+/*
+  A version of malloc/free/realloc written by Doug Lea and released to the
+  public domain.  Send questions/comments/complaints/performance data
+  to dl@cs.oswego.edu
+
+* VERSION 2.6.6  Sun Mar  5 19:10:03 2000  Doug Lea  (dl at gee)
+
+   Note: There may be an updated version of this malloc obtainable at
+	   ftp://g.oswego.edu/pub/misc/malloc.c
+	 Check before installing!
+
+* Why use this malloc?
+
+  This is not the fastest, most space-conserving, most portable, or
+  most tunable malloc ever written. However it is among the fastest
+  while also being among the most space-conserving, portable and tunable.
+  Consistent balance across these factors results in a good general-purpose
+  allocator. For a high-level description, see
+     http://g.oswego.edu/dl/html/malloc.html
+
+* Synopsis of public routines
+
+  (Much fuller descriptions are contained in the program documentation below.)
+
+  malloc(size_t n);
+     Return a pointer to a newly allocated chunk of at least n bytes, or null
+     if no space is available.
+  free(Void_t* p);
+     Release the chunk of memory pointed to by p, or no effect if p is null.
+  realloc(Void_t* p, size_t n);
+     Return a pointer to a chunk of size n that contains the same data
+     as does chunk p up to the minimum of (n, p's size) bytes, or null
+     if no space is available. The returned pointer may or may not be
+     the same as p. If p is null, equivalent to malloc.  Unless the
+     #define REALLOC_ZERO_BYTES_FREES below is set, realloc with a
+     size argument of zero (re)allocates a minimum-sized chunk.
+  memalign(size_t alignment, size_t n);
+     Return a pointer to a newly allocated chunk of n bytes, aligned
+     in accord with the alignment argument, which must be a power of
+     two.
+  valloc(size_t n);
+     Equivalent to memalign(pagesize, n), where pagesize is the page
+     size of the system (or as near to this as can be figured out from
+     all the includes/defines below.)
+  pvalloc(size_t n);
+     Equivalent to valloc(minimum-page-that-holds(n)), that is,
+     round up n to nearest pagesize.
+  calloc(size_t unit, size_t quantity);
+     Returns a pointer to quantity * unit bytes, with all locations
+     set to zero.
+  cfree(Void_t* p);
+     Equivalent to free(p).
+  malloc_trim(size_t pad);
+     Release all but pad bytes of freed top-most memory back
+     to the system. Return 1 if successful, else 0.
+  malloc_usable_size(Void_t* p);
+     Report the number usable allocated bytes associated with allocated
+     chunk p. This may or may not report more bytes than were requested,
+     due to alignment and minimum size constraints.
+  malloc_stats();
+     Prints brief summary statistics on stderr.
+  mallinfo()
+     Returns (by copy) a struct containing various summary statistics.
+  mallopt(int parameter_number, int parameter_value)
+     Changes one of the tunable parameters described below. Returns
+     1 if successful in changing the parameter, else 0.
+
+* Vital statistics:
+
+  Alignment:                            8-byte
+       8 byte alignment is currently hardwired into the design.  This
+       seems to suffice for all current machines and C compilers.
+
+  Assumed pointer representation:       4 or 8 bytes
+       Code for 8-byte pointers is untested by me but has worked
+       reliably by Wolfram Gloger, who contributed most of the
+       changes supporting this.
+
+  Assumed size_t  representation:       4 or 8 bytes
+       Note that size_t is allowed to be 4 bytes even if pointers are 8.
+
+  Minimum overhead per allocated chunk: 4 or 8 bytes
+       Each malloced chunk has a hidden overhead of 4 bytes holding size
+       and status information.
+
+  Minimum allocated size: 4-byte ptrs:  16 bytes    (including 4 overhead)
+			  8-byte ptrs:  24/32 bytes (including, 4/8 overhead)
+
+       When a chunk is freed, 12 (for 4byte ptrs) or 20 (for 8 byte
+       ptrs but 4 byte size) or 24 (for 8/8) additional bytes are
+       needed; 4 (8) for a trailing size field
+       and 8 (16) bytes for free list pointers. Thus, the minimum
+       allocatable size is 16/24/32 bytes.
+
+       Even a request for zero bytes (i.e., malloc(0)) returns a
+       pointer to something of the minimum allocatable size.
+
+  Maximum allocated size: 4-byte size_t: 2^31 -  8 bytes
+			  8-byte size_t: 2^63 - 16 bytes
+
+       It is assumed that (possibly signed) size_t bit values suffice to
+       represent chunk sizes. `Possibly signed' is due to the fact
+       that `size_t' may be defined on a system as either a signed or
+       an unsigned type. To be conservative, values that would appear
+       as negative numbers are avoided.
+       Requests for sizes with a negative sign bit when the request
+       size is treaded as a long will return null.
+
+  Maximum overhead wastage per allocated chunk: normally 15 bytes
+
+       Alignnment demands, plus the minimum allocatable size restriction
+       make the normal worst-case wastage 15 bytes (i.e., up to 15
+       more bytes will be allocated than were requested in malloc), with
+       two exceptions:
+	 1. Because requests for zero bytes allocate non-zero space,
+	    the worst case wastage for a request of zero bytes is 24 bytes.
+	 2. For requests >= mmap_threshold that are serviced via
+	    mmap(), the worst case wastage is 8 bytes plus the remainder
+	    from a system page (the minimal mmap unit); typically 4096 bytes.
+
+* Limitations
+
+    Here are some features that are NOT currently supported
+
+    * No user-definable hooks for callbacks and the like.
+    * No automated mechanism for fully checking that all accesses
+      to malloced memory stay within their bounds.
+    * No support for compaction.
+
+* Synopsis of compile-time options:
+
+    People have reported using previous versions of this malloc on all
+    versions of Unix, sometimes by tweaking some of the defines
+    below. It has been tested most extensively on Solaris and
+    Linux. It is also reported to work on WIN32 platforms.
+    People have also reported adapting this malloc for use in
+    stand-alone embedded systems.
+
+    The implementation is in straight, hand-tuned ANSI C.  Among other
+    consequences, it uses a lot of macros.  Because of this, to be at
+    all usable, this code should be compiled using an optimizing compiler
+    (for example gcc -O2) that can simplify expressions and control
+    paths.
+
+  __STD_C                  (default: derived from C compiler defines)
+     Nonzero if using ANSI-standard C compiler, a C++ compiler, or
+     a C compiler sufficiently close to ANSI to get away with it.
+  DEBUG                    (default: NOT defined)
+     Define to enable debugging. Adds fairly extensive assertion-based
+     checking to help track down memory errors, but noticeably slows down
+     execution.
+  REALLOC_ZERO_BYTES_FREES (default: NOT defined)
+     Define this if you think that realloc(p, 0) should be equivalent
+     to free(p). Otherwise, since malloc returns a unique pointer for
+     malloc(0), so does realloc(p, 0).
+  HAVE_MEMCPY               (default: defined)
+     Define if you are not otherwise using ANSI STD C, but still
+     have memcpy and memset in your C library and want to use them.
+     Otherwise, simple internal versions are supplied.
+  USE_MEMCPY               (default: 1 if HAVE_MEMCPY is defined, 0 otherwise)
+     Define as 1 if you want the C library versions of memset and
+     memcpy called in realloc and calloc (otherwise macro versions are used).
+     At least on some platforms, the simple macro versions usually
+     outperform libc versions.
+  HAVE_MMAP                 (default: defined as 1)
+     Define to non-zero to optionally make malloc() use mmap() to
+     allocate very large blocks.
+  HAVE_MREMAP                 (default: defined as 0 unless Linux libc set)
+     Define to non-zero to optionally make realloc() use mremap() to
+     reallocate very large blocks.
+  malloc_getpagesize        (default: derived from system #includes)
+     Either a constant or routine call returning the system page size.
+  HAVE_USR_INCLUDE_MALLOC_H (default: NOT defined)
+     Optionally define if you are on a system with a /usr/include/malloc.h
+     that declares struct mallinfo. It is not at all necessary to
+     define this even if you do, but will ensure consistency.
+  INTERNAL_SIZE_T           (default: size_t)
+     Define to a 32-bit type (probably `unsigned int') if you are on a
+     64-bit machine, yet do not want or need to allow malloc requests of
+     greater than 2^31 to be handled. This saves space, especially for
+     very small chunks.
+  INTERNAL_LINUX_C_LIB      (default: NOT defined)
+     Defined only when compiled as part of Linux libc.
+     Also note that there is some odd internal name-mangling via defines
+     (for example, internally, `malloc' is named `mALLOc') needed
+     when compiling in this case. These look funny but don't otherwise
+     affect anything.
+  WIN32                     (default: undefined)
+     Define this on MS win (95, nt) platforms to compile in sbrk emulation.
+  LACKS_UNISTD_H            (default: undefined if not WIN32)
+     Define this if your system does not have a <unistd.h>.
+  LACKS_SYS_PARAM_H         (default: undefined if not WIN32)
+     Define this if your system does not have a <sys/param.h>.
+  MORECORE                  (default: sbrk)
+     The name of the routine to call to obtain more memory from the system.
+  MORECORE_FAILURE          (default: -1)
+     The value returned upon failure of MORECORE.
+  MORECORE_CLEARS           (default 1)
+     true (1) if the routine mapped to MORECORE zeroes out memory (which
+     holds for sbrk).
+  DEFAULT_TRIM_THRESHOLD
+  DEFAULT_TOP_PAD
+  DEFAULT_MMAP_THRESHOLD
+  DEFAULT_MMAP_MAX
+     Default values of tunable parameters (described in detail below)
+     controlling interaction with host system routines (sbrk, mmap, etc).
+     These values may also be changed dynamically via mallopt(). The
+     preset defaults are those that give best performance for typical
+     programs/systems.
+  USE_DL_PREFIX             (default: undefined)
+     Prefix all public routines with the string 'dl'.  Useful to
+     quickly avoid procedure declaration conflicts and linker symbol
+     conflicts with existing memory allocation routines.
+
+
+*/
+
+
+#ifndef __MALLOC_H__
+#define __MALLOC_H__
+
+/* Preliminaries */
+
+#ifndef __STD_C
+#ifdef __STDC__
+#define __STD_C     1
+#else
+#if __cplusplus
+#define __STD_C     1
+#else
+#define __STD_C     0
+#endif /*__cplusplus*/
+#endif /*__STDC__*/
+#endif /*__STD_C*/
+
+#ifndef Void_t
+#if (__STD_C || defined(WIN32))
+#define Void_t      void
+#else
+#define Void_t      char
+#endif
+#endif /*Void_t*/
+
+#if __STD_C
+#include <linux/stddef.h>	/* for size_t */
+#else
+#include <sys/types.h>
+#endif	/* __STD_C */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if 0	/* not for U-Boot */
+#include <stdio.h>	/* needed for malloc_stats */
+#endif
+
+
+/*
+  Compile-time options
+*/
+
+
+/*
+    Debugging:
+
+    Because freed chunks may be overwritten with link fields, this
+    malloc will often die when freed memory is overwritten by user
+    programs.  This can be very effective (albeit in an annoying way)
+    in helping track down dangling pointers.
+
+    If you compile with -DDEBUG, a number of assertion checks are
+    enabled that will catch more memory errors. You probably won't be
+    able to make much sense of the actual assertion errors, but they
+    should help you locate incorrectly overwritten memory.  The
+    checking is fairly extensive, and will slow down execution
+    noticeably. Calling malloc_stats or mallinfo with DEBUG set will
+    attempt to check every non-mmapped allocated and free chunk in the
+    course of computing the summmaries. (By nature, mmapped regions
+    cannot be checked very much automatically.)
+
+    Setting DEBUG may also be helpful if you are trying to modify
+    this code. The assertions in the check routines spell out in more
+    detail the assumptions and invariants underlying the algorithms.
+
+*/
+
+/*
+  INTERNAL_SIZE_T is the word-size used for internal bookkeeping
+  of chunk sizes. On a 64-bit machine, you can reduce malloc
+  overhead by defining INTERNAL_SIZE_T to be a 32 bit `unsigned int'
+  at the expense of not being able to handle requests greater than
+  2^31. This limitation is hardly ever a concern; you are encouraged
+  to set this. However, the default version is the same as size_t.
+*/
+
+#ifndef INTERNAL_SIZE_T
+#define INTERNAL_SIZE_T size_t
+#endif
+
+/*
+  REALLOC_ZERO_BYTES_FREES should be set if a call to
+  realloc with zero bytes should be the same as a call to free.
+  Some people think it should. Otherwise, since this malloc
+  returns a unique pointer for malloc(0), so does realloc(p, 0).
+*/
+
+
+/*   #define REALLOC_ZERO_BYTES_FREES */
+
+
+/*
+  WIN32 causes an emulation of sbrk to be compiled in
+  mmap-based options are not currently supported in WIN32.
+*/
+
+/* #define WIN32 */
+#ifdef WIN32
+#define MORECORE wsbrk
+#define HAVE_MMAP 0
+
+#define LACKS_UNISTD_H
+#define LACKS_SYS_PARAM_H
+
+/*
+  Include 'windows.h' to get the necessary declarations for the
+  Microsoft Visual C++ data structures and routines used in the 'sbrk'
+  emulation.
+
+  Define WIN32_LEAN_AND_MEAN so that only the essential Microsoft
+  Visual C++ header files are included.
+*/
+#define WIN32_LEAN_AND_MEAN
+#include <windows.h>
+#endif
+
+
+/*
+  HAVE_MEMCPY should be defined if you are not otherwise using
+  ANSI STD C, but still have memcpy and memset in your C library
+  and want to use them in calloc and realloc. Otherwise simple
+  macro versions are defined here.
+
+  USE_MEMCPY should be defined as 1 if you actually want to
+  have memset and memcpy called. People report that the macro
+  versions are often enough faster than libc versions on many
+  systems that it is better to use them.
+
+*/
+
+#define HAVE_MEMCPY
+
+#ifndef USE_MEMCPY
+#ifdef HAVE_MEMCPY
+#define USE_MEMCPY 1
+#else
+#define USE_MEMCPY 0
+#endif
+#endif
+
+#if (__STD_C || defined(HAVE_MEMCPY))
+
+#if __STD_C
+void* memset(void*, int, size_t);
+void* memcpy(void*, const void*, size_t);
+#else
+#ifdef WIN32
+/* On Win32 platforms, 'memset()' and 'memcpy()' are already declared in */
+/* 'windows.h' */
+#else
+Void_t* memset();
+Void_t* memcpy();
+#endif
+#endif
+#endif
+
+#if USE_MEMCPY
+
+/* The following macros are only invoked with (2n+1)-multiples of
+   INTERNAL_SIZE_T units, with a positive integer n. This is exploited
+   for fast inline execution when n is small. */
+
+#define MALLOC_ZERO(charp, nbytes)                                            \
+do {                                                                          \
+  INTERNAL_SIZE_T mzsz = (nbytes);                                            \
+  if(mzsz <= 9*sizeof(mzsz)) {                                                \
+    INTERNAL_SIZE_T* mz = (INTERNAL_SIZE_T*) (charp);                         \
+    if(mzsz >= 5*sizeof(mzsz)) {     *mz++ = 0;                               \
+				     *mz++ = 0;                               \
+      if(mzsz >= 7*sizeof(mzsz)) {   *mz++ = 0;                               \
+				     *mz++ = 0;                               \
+	if(mzsz >= 9*sizeof(mzsz)) { *mz++ = 0;                               \
+				     *mz++ = 0; }}}                           \
+				     *mz++ = 0;                               \
+				     *mz++ = 0;                               \
+				     *mz   = 0;                               \
+  } else memset((charp), 0, mzsz);                                            \
+} while(0)
+
+#define MALLOC_COPY(dest,src,nbytes)                                          \
+do {                                                                          \
+  INTERNAL_SIZE_T mcsz = (nbytes);                                            \
+  if(mcsz <= 9*sizeof(mcsz)) {                                                \
+    INTERNAL_SIZE_T* mcsrc = (INTERNAL_SIZE_T*) (src);                        \
+    INTERNAL_SIZE_T* mcdst = (INTERNAL_SIZE_T*) (dest);                       \
+    if(mcsz >= 5*sizeof(mcsz)) {     *mcdst++ = *mcsrc++;                     \
+				     *mcdst++ = *mcsrc++;                     \
+      if(mcsz >= 7*sizeof(mcsz)) {   *mcdst++ = *mcsrc++;                     \
+				     *mcdst++ = *mcsrc++;                     \
+	if(mcsz >= 9*sizeof(mcsz)) { *mcdst++ = *mcsrc++;                     \
+				     *mcdst++ = *mcsrc++; }}}                 \
+				     *mcdst++ = *mcsrc++;                     \
+				     *mcdst++ = *mcsrc++;                     \
+				     *mcdst   = *mcsrc  ;                     \
+  } else memcpy(dest, src, mcsz);                                             \
+} while(0)
+
+#else /* !USE_MEMCPY */
+
+/* Use Duff's device for good zeroing/copying performance. */
+
+#define MALLOC_ZERO(charp, nbytes)                                            \
+do {                                                                          \
+  INTERNAL_SIZE_T* mzp = (INTERNAL_SIZE_T*)(charp);                           \
+  long mctmp = (nbytes)/sizeof(INTERNAL_SIZE_T), mcn;                         \
+  if (mctmp < 8) mcn = 0; else { mcn = (mctmp-1)/8; mctmp %= 8; }             \
+  switch (mctmp) {                                                            \
+    case 0: for(;;) { *mzp++ = 0;                                             \
+    case 7:           *mzp++ = 0;                                             \
+    case 6:           *mzp++ = 0;                                             \
+    case 5:           *mzp++ = 0;                                             \
+    case 4:           *mzp++ = 0;                                             \
+    case 3:           *mzp++ = 0;                                             \
+    case 2:           *mzp++ = 0;                                             \
+    case 1:           *mzp++ = 0; if(mcn <= 0) break; mcn--; }                \
+  }                                                                           \
+} while(0)
+
+#define MALLOC_COPY(dest,src,nbytes)                                          \
+do {                                                                          \
+  INTERNAL_SIZE_T* mcsrc = (INTERNAL_SIZE_T*) src;                            \
+  INTERNAL_SIZE_T* mcdst = (INTERNAL_SIZE_T*) dest;                           \
+  long mctmp = (nbytes)/sizeof(INTERNAL_SIZE_T), mcn;                         \
+  if (mctmp < 8) mcn = 0; else { mcn = (mctmp-1)/8; mctmp %= 8; }             \
+  switch (mctmp) {                                                            \
+    case 0: for(;;) { *mcdst++ = *mcsrc++;                                    \
+    case 7:           *mcdst++ = *mcsrc++;                                    \
+    case 6:           *mcdst++ = *mcsrc++;                                    \
+    case 5:           *mcdst++ = *mcsrc++;                                    \
+    case 4:           *mcdst++ = *mcsrc++;                                    \
+    case 3:           *mcdst++ = *mcsrc++;                                    \
+    case 2:           *mcdst++ = *mcsrc++;                                    \
+    case 1:           *mcdst++ = *mcsrc++; if(mcn <= 0) break; mcn--; }       \
+  }                                                                           \
+} while(0)
+
+#endif
+
+
+/*
+  Define HAVE_MMAP to optionally make malloc() use mmap() to
+  allocate very large blocks.  These will be returned to the
+  operating system immediately after a free().
+*/
+
+/***
+#ifndef HAVE_MMAP
+#define HAVE_MMAP 1
+#endif
+***/
+#undef	HAVE_MMAP	/* Not available for U-Boot */
+
+/*
+  Define HAVE_MREMAP to make realloc() use mremap() to re-allocate
+  large blocks.  This is currently only possible on Linux with
+  kernel versions newer than 1.3.77.
+*/
+
+/***
+#ifndef HAVE_MREMAP
+#ifdef INTERNAL_LINUX_C_LIB
+#define HAVE_MREMAP 1
+#else
+#define HAVE_MREMAP 0
+#endif
+#endif
+***/
+#undef	HAVE_MREMAP	/* Not available for U-Boot */
+
+#ifdef HAVE_MMAP
+
+#include <unistd.h>
+#include <fcntl.h>
+#include <sys/mman.h>
+
+#if !defined(MAP_ANONYMOUS) && defined(MAP_ANON)
+#define MAP_ANONYMOUS MAP_ANON
+#endif
+
+#endif /* HAVE_MMAP */
+
+/*
+  Access to system page size. To the extent possible, this malloc
+  manages memory from the system in page-size units.
+
+  The following mechanics for getpagesize were adapted from
+  bsd/gnu getpagesize.h
+*/
+
+#define	LACKS_UNISTD_H	/* Shortcut for U-Boot */
+#define	malloc_getpagesize	4096
+
+#ifndef LACKS_UNISTD_H
+#  include <unistd.h>
+#endif
+
+#ifndef malloc_getpagesize
+#  ifdef _SC_PAGESIZE         /* some SVR4 systems omit an underscore */
+#    ifndef _SC_PAGE_SIZE
+#      define _SC_PAGE_SIZE _SC_PAGESIZE
+#    endif
+#  endif
+#  ifdef _SC_PAGE_SIZE
+#    define malloc_getpagesize sysconf(_SC_PAGE_SIZE)
+#  else
+#    if defined(BSD) || defined(DGUX) || defined(HAVE_GETPAGESIZE)
+       extern size_t getpagesize();
+#      define malloc_getpagesize getpagesize()
+#    else
+#      ifdef WIN32
+#        define malloc_getpagesize (4096) /* TBD: Use 'GetSystemInfo' instead */
+#      else
+#        ifndef LACKS_SYS_PARAM_H
+#          include <sys/param.h>
+#        endif
+#        ifdef EXEC_PAGESIZE
+#          define malloc_getpagesize EXEC_PAGESIZE
+#        else
+#          ifdef NBPG
+#            ifndef CLSIZE
+#              define malloc_getpagesize NBPG
+#            else
+#              define malloc_getpagesize (NBPG * CLSIZE)
+#            endif
+#          else
+#            ifdef NBPC
+#              define malloc_getpagesize NBPC
+#            else
+#              ifdef PAGESIZE
+#                define malloc_getpagesize PAGESIZE
+#              else
+#                define malloc_getpagesize (4096) /* just guess */
+#              endif
+#            endif
+#          endif
+#        endif
+#      endif
+#    endif
+#  endif
+#endif
+
+
+/*
+
+  This version of malloc supports the standard SVID/XPG mallinfo
+  routine that returns a struct containing the same kind of
+  information you can get from malloc_stats. It should work on
+  any SVID/XPG compliant system that has a /usr/include/malloc.h
+  defining struct mallinfo. (If you'd like to install such a thing
+  yourself, cut out the preliminary declarations as described above
+  and below and save them in a malloc.h file. But there's no
+  compelling reason to bother to do this.)
+
+  The main declaration needed is the mallinfo struct that is returned
+  (by-copy) by mallinfo().  The SVID/XPG malloinfo struct contains a
+  bunch of fields, most of which are not even meaningful in this
+  version of malloc. Some of these fields are are instead filled by
+  mallinfo() with other numbers that might possibly be of interest.
+
+  HAVE_USR_INCLUDE_MALLOC_H should be set if you have a
+  /usr/include/malloc.h file that includes a declaration of struct
+  mallinfo.  If so, it is included; else an SVID2/XPG2 compliant
+  version is declared below.  These must be precisely the same for
+  mallinfo() to work.
+
+*/
+
+/* #define HAVE_USR_INCLUDE_MALLOC_H */
+
+#ifdef HAVE_USR_INCLUDE_MALLOC_H
+#include "/usr/include/malloc.h"
+#else
+
+/* SVID2/XPG mallinfo structure */
+
+struct mallinfo {
+  int arena;    /* total space allocated from system */
+  int ordblks;  /* number of non-inuse chunks */
+  int smblks;   /* unused -- always zero */
+  int hblks;    /* number of mmapped regions */
+  int hblkhd;   /* total space in mmapped regions */
+  int usmblks;  /* unused -- always zero */
+  int fsmblks;  /* unused -- always zero */
+  int uordblks; /* total allocated space */
+  int fordblks; /* total non-inuse space */
+  int keepcost; /* top-most, releasable (via malloc_trim) space */
+};
+
+/* SVID2/XPG mallopt options */
+
+#define M_MXFAST  1    /* UNUSED in this malloc */
+#define M_NLBLKS  2    /* UNUSED in this malloc */
+#define M_GRAIN   3    /* UNUSED in this malloc */
+#define M_KEEP    4    /* UNUSED in this malloc */
+
+#endif
+
+/* mallopt options that actually do something */
+
+#define M_TRIM_THRESHOLD    -1
+#define M_TOP_PAD           -2
+#define M_MMAP_THRESHOLD    -3
+#define M_MMAP_MAX          -4
+
+
+#ifndef DEFAULT_TRIM_THRESHOLD
+#define DEFAULT_TRIM_THRESHOLD (128 * 1024)
+#endif
+
+/*
+    M_TRIM_THRESHOLD is the maximum amount of unused top-most memory
+      to keep before releasing via malloc_trim in free().
+
+      Automatic trimming is mainly useful in long-lived programs.
+      Because trimming via sbrk can be slow on some systems, and can
+      sometimes be wasteful (in cases where programs immediately
+      afterward allocate more large chunks) the value should be high
+      enough so that your overall system performance would improve by
+      releasing.
+
+      The trim threshold and the mmap control parameters (see below)
+      can be traded off with one another. Trimming and mmapping are
+      two different ways of releasing unused memory back to the
+      system. Between these two, it is often possible to keep
+      system-level demands of a long-lived program down to a bare
+      minimum. For example, in one test suite of sessions measuring
+      the XF86 X server on Linux, using a trim threshold of 128K and a
+      mmap threshold of 192K led to near-minimal long term resource
+      consumption.
+
+      If you are using this malloc in a long-lived program, it should
+      pay to experiment with these values.  As a rough guide, you
+      might set to a value close to the average size of a process
+      (program) running on your system.  Releasing this much memory
+      would allow such a process to run in memory.  Generally, it's
+      worth it to tune for trimming rather tham memory mapping when a
+      program undergoes phases where several large chunks are
+      allocated and released in ways that can reuse each other's
+      storage, perhaps mixed with phases where there are no such
+      chunks at all.  And in well-behaved long-lived programs,
+      controlling release of large blocks via trimming versus mapping
+      is usually faster.
+
+      However, in most programs, these parameters serve mainly as
+      protection against the system-level effects of carrying around
+      massive amounts of unneeded memory. Since frequent calls to
+      sbrk, mmap, and munmap otherwise degrade performance, the default
+      parameters are set to relatively high values that serve only as
+      safeguards.
+
+      The default trim value is high enough to cause trimming only in
+      fairly extreme (by current memory consumption standards) cases.
+      It must be greater than page size to have any useful effect.  To
+      disable trimming completely, you can set to (unsigned long)(-1);
+
+
+*/
+
+
+#ifndef DEFAULT_TOP_PAD
+#define DEFAULT_TOP_PAD        (0)
+#endif
+
+/*
+    M_TOP_PAD is the amount of extra `padding' space to allocate or
+      retain whenever sbrk is called. It is used in two ways internally:
+
+      * When sbrk is called to extend the top of the arena to satisfy
+	a new malloc request, this much padding is added to the sbrk
+	request.
+
+      * When malloc_trim is called automatically from free(),
+	it is used as the `pad' argument.
+
+      In both cases, the actual amount of padding is rounded
+      so that the end of the arena is always a system page boundary.
+
+      The main reason for using padding is to avoid calling sbrk so
+      often. Having even a small pad greatly reduces the likelihood
+      that nearly every malloc request during program start-up (or
+      after trimming) will invoke sbrk, which needlessly wastes
+      time.
+
+      Automatic rounding-up to page-size units is normally sufficient
+      to avoid measurable overhead, so the default is 0.  However, in
+      systems where sbrk is relatively slow, it can pay to increase
+      this value, at the expense of carrying around more memory than
+      the program needs.
+
+*/
+
+
+#ifndef DEFAULT_MMAP_THRESHOLD
+#define DEFAULT_MMAP_THRESHOLD (128 * 1024)
+#endif
+
+/*
+
+    M_MMAP_THRESHOLD is the request size threshold for using mmap()
+      to service a request. Requests of at least this size that cannot
+      be allocated using already-existing space will be serviced via mmap.
+      (If enough normal freed space already exists it is used instead.)
+
+      Using mmap segregates relatively large chunks of memory so that
+      they can be individually obtained and released from the host
+      system. A request serviced through mmap is never reused by any
+      other request (at least not directly; the system may just so
+      happen to remap successive requests to the same locations).
+
+      Segregating space in this way has the benefit that mmapped space
+      can ALWAYS be individually released back to the system, which
+      helps keep the system level memory demands of a long-lived
+      program low. Mapped memory can never become `locked' between
+      other chunks, as can happen with normally allocated chunks, which
+      menas that even trimming via malloc_trim would not release them.
+
+      However, it has the disadvantages that:
+
+	 1. The space cannot be reclaimed, consolidated, and then
+	    used to service later requests, as happens with normal chunks.
+	 2. It can lead to more wastage because of mmap page alignment
+	    requirements
+	 3. It causes malloc performance to be more dependent on host
+	    system memory management support routines which may vary in
+	    implementation quality and may impose arbitrary
+	    limitations. Generally, servicing a request via normal
+	    malloc steps is faster than going through a system's mmap.
+
+      All together, these considerations should lead you to use mmap
+      only for relatively large requests.
+
+
+*/
+
+
+#ifndef DEFAULT_MMAP_MAX
+#ifdef HAVE_MMAP
+#define DEFAULT_MMAP_MAX       (64)
+#else
+#define DEFAULT_MMAP_MAX       (0)
+#endif
+#endif
+
+/*
+    M_MMAP_MAX is the maximum number of requests to simultaneously
+      service using mmap. This parameter exists because:
+
+	 1. Some systems have a limited number of internal tables for
+	    use by mmap.
+	 2. In most systems, overreliance on mmap can degrade overall
+	    performance.
+	 3. If a program allocates many large regions, it is probably
+	    better off using normal sbrk-based allocation routines that
+	    can reclaim and reallocate normal heap memory. Using a
+	    small value allows transition into this mode after the
+	    first few allocations.
+
+      Setting to 0 disables all use of mmap.  If HAVE_MMAP is not set,
+      the default value is 0, and attempts to set it to non-zero values
+      in mallopt will fail.
+*/
+
+
+/*
+    USE_DL_PREFIX will prefix all public routines with the string 'dl'.
+      Useful to quickly avoid procedure declaration conflicts and linker
+      symbol conflicts with existing memory allocation routines.
+
+*/
+
+/* #define USE_DL_PREFIX */
+
+
+/*
+
+  Special defines for linux libc
+
+  Except when compiled using these special defines for Linux libc
+  using weak aliases, this malloc is NOT designed to work in
+  multithreaded applications.  No semaphores or other concurrency
+  control are provided to ensure that multiple malloc or free calls
+  don't run at the same time, which could be disasterous. A single
+  semaphore could be used across malloc, realloc, and free (which is
+  essentially the effect of the linux weak alias approach). It would
+  be hard to obtain finer granularity.
+
+*/
+
+
+#ifdef INTERNAL_LINUX_C_LIB
+
+#if __STD_C
+
+Void_t * __default_morecore_init (ptrdiff_t);
+Void_t *(*__morecore)(ptrdiff_t) = __default_morecore_init;
+
+#else
+
+Void_t * __default_morecore_init ();
+Void_t *(*__morecore)() = __default_morecore_init;
+
+#endif
+
+#define MORECORE (*__morecore)
+#define MORECORE_FAILURE 0
+#define MORECORE_CLEARS 1
+
+#else /* INTERNAL_LINUX_C_LIB */
+
+#if __STD_C
+extern Void_t*     sbrk(ptrdiff_t);
+#else
+extern Void_t*     sbrk();
+#endif
+
+#ifndef MORECORE
+#define MORECORE sbrk
+#endif
+
+#ifndef MORECORE_FAILURE
+#define MORECORE_FAILURE -1
+#endif
+
+#ifndef MORECORE_CLEARS
+#define MORECORE_CLEARS 1
+#endif
+
+#endif /* INTERNAL_LINUX_C_LIB */
+
+#if defined(INTERNAL_LINUX_C_LIB) && defined(__ELF__)
+
+#define cALLOc		__libc_calloc
+#define fREe		__libc_free
+#define mALLOc		__libc_malloc
+#define mEMALIGn	__libc_memalign
+#define rEALLOc		__libc_realloc
+#define vALLOc		__libc_valloc
+#define pvALLOc		__libc_pvalloc
+#define mALLINFo	__libc_mallinfo
+#define mALLOPt		__libc_mallopt
+
+#pragma weak calloc = __libc_calloc
+#pragma weak free = __libc_free
+#pragma weak cfree = __libc_free
+#pragma weak malloc = __libc_malloc
+#pragma weak memalign = __libc_memalign
+#pragma weak realloc = __libc_realloc
+#pragma weak valloc = __libc_valloc
+#pragma weak pvalloc = __libc_pvalloc
+#pragma weak mallinfo = __libc_mallinfo
+#pragma weak mallopt = __libc_mallopt
+
+#else
+
+#ifdef USE_DL_PREFIX
+#define cALLOc		dlcalloc
+#define fREe		dlfree
+#define mALLOc		dlmalloc
+#define mEMALIGn	dlmemalign
+#define rEALLOc		dlrealloc
+#define vALLOc		dlvalloc
+#define pvALLOc		dlpvalloc
+#define mALLINFo	dlmallinfo
+#define mALLOPt		dlmallopt
+#else /* USE_DL_PREFIX */
+#define cALLOc		calloc
+#define fREe		free
+#define mALLOc		malloc
+#define mEMALIGn	memalign
+#define rEALLOc		realloc
+#define vALLOc		valloc
+#define pvALLOc		pvalloc
+#define mALLINFo	mallinfo
+#define mALLOPt		mallopt
+#endif /* USE_DL_PREFIX */
+
+#endif
+
+/* Public routines */
+
+#if __STD_C
+
+Void_t* mALLOc(size_t);
+void    fREe(Void_t*);
+Void_t* rEALLOc(Void_t*, size_t);
+Void_t* mEMALIGn(size_t, size_t);
+Void_t* vALLOc(size_t);
+Void_t* pvALLOc(size_t);
+Void_t* cALLOc(size_t, size_t);
+void    cfree(Void_t*);
+int     malloc_trim(size_t);
+size_t  malloc_usable_size(Void_t*);
+void    malloc_stats(void);
+int     mALLOPt(int, int);
+struct mallinfo mALLINFo(void);
+#else
+Void_t* mALLOc();
+void    fREe();
+Void_t* rEALLOc();
+Void_t* mEMALIGn();
+Void_t* vALLOc();
+Void_t* pvALLOc();
+Void_t* cALLOc();
+void    cfree();
+int     malloc_trim();
+size_t  malloc_usable_size();
+void    malloc_stats();
+int     mALLOPt();
+struct mallinfo mALLINFo();
+#endif
+
+/*
+ * Begin and End of memory area for malloc(), and current "brk"
+ */
+extern ulong mem_malloc_start;
+extern ulong mem_malloc_end;
+extern ulong mem_malloc_brk;
+
+void mem_malloc_init(ulong start, ulong size);
+
+#ifdef __cplusplus
+};  /* end of extern "C" */
+#endif
+
+#endif /* __MALLOC_H__ */
diff --git a/qemu/roms/u-boot/include/mb862xx.h b/qemu/roms/u-boot/include/mb862xx.h
new file mode 100644
index 000000000..3521f044b
--- /dev/null
+++ b/qemu/roms/u-boot/include/mb862xx.h
@@ -0,0 +1,102 @@
+/*
+ * (C) Copyright 2007
+ * DENX Software Engineering, Anatolij Gustschin, agust@denx.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * mb862xx.h - Graphic interface for Fujitsu CoralP/Lime
+ */
+
+#ifndef _MB862XX_H_
+#define _MB862XX_H_
+
+#define PCI_VENDOR_ID_FUJITSU	0x10CF
+#define PCI_DEVICE_ID_CORAL_P	0x2019
+#define PCI_DEVICE_ID_CORAL_PA	0x201E
+
+#define MB862XX_TYPE_LIME	0x1
+
+#define GC_HOST_BASE		0x01fc0000
+#define GC_DISP_BASE		0x01fd0000
+#define GC_DRAW_BASE		0x01ff0000
+
+/* Host interface registers */
+#define GC_SRST			0x0000002c
+#define GC_CCF			0x00000038
+#define GC_CID			0x000000f0
+#define GC_MMR			0x0000fffc
+
+/*
+ * Display Controller registers
+ * _A means the offset is aligned, we use these for boards
+ * with 8-/16-bit GDC access not working or buggy.
+ */
+#define GC_DCM0			0x00000000
+#define GC_HTP_A		0x00000004
+#define GC_HTP			0x00000006
+#define GC_HDB_HDP_A		0x00000008
+#define GC_HDP			0x00000008
+#define GC_HDB			0x0000000a
+#define GC_VSW_HSW_HSP_A	0x0000000c
+#define GC_HSP			0x0000000c
+#define GC_HSW			0x0000000e
+#define GC_VSW			0x0000000f
+#define GC_VTR_A		0x00000010
+#define GC_VTR			0x00000012
+#define GC_VDP_VSP_A		0x00000014
+#define GC_VSP			0x00000014
+#define GC_VDP			0x00000016
+#define GC_WY_WX		0x00000018
+#define GC_WH_WW		0x0000001c
+#define GC_L0M			0x00000020
+#define GC_L0OA0		0x00000024
+#define GC_L0DA0		0x00000028
+#define GC_L0DY_L0DX		0x0000002c
+#define GC_L2M			0x00000040
+#define GC_L2OA0		0x00000044
+#define GC_L2DA0		0x00000048
+#define GC_L2OA1		0x0000004c
+#define GC_L2DA1		0x00000050
+#define GC_L2DX			0x00000054
+#define GC_L2DY			0x00000056
+#define GC_DCM1			0x00000100
+#define GC_DCM2			0x00000104
+#define GC_DCM3			0x00000108
+#define GC_L0EM			0x00000110
+#define GC_L0WY_L0WX		0x00000114
+#define GC_L0WH_L0WW		0x00000118
+#define GC_L2EM			0x00000130
+#define GC_L2WX			0x00000134
+#define GC_L2WY			0x00000136
+#define GC_L2WW			0x00000138
+#define GC_L2WH			0x0000013a
+#define GC_L0PAL0		0x00000400
+
+/* Drawing registers */
+#define GC_CTR			0x00000400
+#define GC_IFCNT		0x00000408
+#define GC_FBR			0x00000440
+#define GC_XRES			0x00000444
+#define GC_CXMIN		0x00000454
+#define GC_CXMAX		0x00000458
+#define GC_CYMIN		0x0000045c
+#define GC_CYMAX		0x00000460
+#define GC_FC			0x00000480
+#define GC_BC			0x00000484
+#define GC_FIFO			0x000004a0
+#define GC_REV			0x00008084
+#define GC_GEO_FIFO		0x00008400
+
+typedef struct {
+	unsigned int index;
+	unsigned int value;
+} gdc_regs;
+
+int mb862xx_probe(unsigned int addr);
+const gdc_regs *board_get_regs (void);
+unsigned int board_video_init (void);
+void board_backlight_switch(int);
+
+#endif /* _MB862XX_H_ */
diff --git a/qemu/roms/u-boot/include/mc13783.h b/qemu/roms/u-boot/include/mc13783.h
new file mode 100644
index 000000000..3b20591a8
--- /dev/null
+++ b/qemu/roms/u-boot/include/mc13783.h
@@ -0,0 +1,64 @@
+/*
+ * (C) Copyright 2011
+ * Helmut Raiger, HALE electronic GmbH, helmut.raiger@hale.at
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+
+#ifndef __MC13783_H__
+#define __MC13783_H__
+
+/* REG_MODE_0 */
+#define VAUDIOEN	(1 << 0)
+#define VAUDIOSTBY	(1 << 1)
+#define VAUDIOMODE	(1 << 2)
+#define VIOHIEN		(1 << 3)
+#define VIOHISTBY	(1 << 4)
+#define VIOHIMODE	(1 << 5)
+#define VIOLOEN		(1 << 6)
+#define VIOLOSTBY	(1 << 7)
+#define VIOLOMODE	(1 << 8)
+#define VDIGEN 		(1 << 9)
+#define VDIGSTBY	(1 << 10)
+#define VDIGMODE	(1 << 11)
+#define VGENEN		(1 << 12)
+#define VGENSTBY	(1 << 13)
+#define VGENMODE	(1 << 14)
+#define VRFDIGEN	(1 << 15)
+#define VRFDIGSTBY	(1 << 16)
+#define VRFDIGMODE	(1 << 17)
+#define VRFREFEN	(1 << 18)
+#define VRFREFSTBY	(1 << 19)
+#define VRFREFMODE	(1 << 20)
+#define VRFCPEN		(1 << 21)
+#define VRFCPSTBY	(1 << 22)
+#define VRFCPMODE	(1 << 23)
+
+/* REG_MODE_1 */
+#define VSIMEN		(1 << 0)
+#define VSIMSTBY	(1 << 1)
+#define VSIMMODE	(1 << 2)
+#define VESIMEN		(1 << 3)
+#define VESIMSTBY	(1 << 4)
+#define VESIMMODE	(1 << 5)
+#define VCAMEN		(1 << 6)
+#define VCAMSTBY	(1 << 7)
+#define VCAMMODE	(1 << 8)
+#define VRFBGEN		(1 << 9)
+#define VRFBGSTBY	(1 << 10)
+#define VVIBEN		(1 << 11)
+#define VRF1EN		(1 << 12)
+#define VRF1STBY	(1 << 13)
+#define VRF1MODE	(1 << 14)
+#define VRF2EN		(1 << 15)
+#define VRF2STBY	(1 << 16)
+#define VRF2MODE	(1 << 17)
+#define VMMC1EN		(1 << 18)
+#define VMMC1STBY	(1 << 19)
+#define VMMC1MODE	(1 << 20)
+#define VMMC2EN		(1 << 21)
+#define VMMC2STBY	(1 << 22)
+#define VMMC2MODE	(1 << 23)
+
+#endif
diff --git a/qemu/roms/u-boot/include/mc13892.h b/qemu/roms/u-boot/include/mc13892.h
new file mode 100644
index 000000000..218f36f08
--- /dev/null
+++ b/qemu/roms/u-boot/include/mc13892.h
@@ -0,0 +1,207 @@
+/*
+ * (C) Copyright 2010
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+
+#ifndef __MC13892_H__
+#define __MC13892_H__
+
+/* REG_CHARGE */
+
+#define VCHRG0		(1 << 0)
+#define VCHRG1		(1 << 1)
+#define VCHRG2		(1 << 2)
+#define ICHRG0		(1 << 3)
+#define ICHRG1		(1 << 4)
+#define ICHRG2		(1 << 5)
+#define ICHRG3		(1 << 6)
+#define TREN		(1 << 7)
+#define ACKLPB		(1 << 8)
+#define THCHKB		(1 << 9)
+#define FETOVRD		(1 << 10)
+#define FETCTRL		(1 << 11)
+#define RVRSMODE	(1 << 13)
+#define PLIM0		(1 << 15)
+#define PLIM1		(1 << 16)
+#define PLIMDIS		(1 << 17)
+#define CHRGLEDEN	(1 << 18)
+#define CHGTMRRST	(1 << 19)
+#define CHGRESTART	(1 << 20)
+#define CHGAUTOB	(1 << 21)
+#define CYCLB		(1 << 22)
+#define CHGAUTOVIB	(1 << 23)
+
+/* REG_SETTING_0/1 */
+#define VO_1_20V	0
+#define VO_1_30V	1
+#define VO_1_50V	2
+#define VO_1_80V	3
+#define VO_1_10V	4
+#define VO_2_00V	5
+#define VO_2_77V	6
+#define VO_2_40V	7
+
+#define VIOL		2
+#define VDIG		4
+#define VGEN		6
+
+/* SWxMode for Normal/Standby Mode */
+#define SWMODE_OFF_OFF		0
+#define SWMODE_PWM_OFF		1
+#define SWMODE_PWMPS_OFF	2
+#define SWMODE_PFM_OFF		3
+#define SWMODE_AUTO_OFF		4
+#define SWMODE_PWM_PWM		5
+#define SWMODE_PWM_AUTO		6
+#define SWMODE_AUTO_AUTO	8
+#define SWMODE_PWM_PWMPS	9
+#define SWMODE_PWMS_PWMPS	10
+#define SWMODE_PWMS_AUTO	11
+#define SWMODE_AUTO_PFM		12
+#define SWMODE_PWM_PFM		13
+#define SWMODE_PWMS_PFM		14
+#define SWMODE_PFM_PFM		15
+#define SWMODE_MASK		0x0F
+
+#define SWMODE1_SHIFT		0
+#define SWMODE2_SHIFT		10
+#define SWMODE3_SHIFT		0
+#define SWMODE4_SHIFT		8
+
+/* Fields in REG_SETTING_1 */
+#define VVIDEO_2_7	(0 << 2)
+#define VVIDEO_2_775	(1 << 2)
+#define VVIDEO_2_5	(2 << 2)
+#define VVIDEO_2_6	(3 << 2)
+#define VVIDEO_MASK	(3 << 2)
+#define VAUDIO_2_3	(0 << 4)
+#define VAUDIO_2_5	(1 << 4)
+#define VAUDIO_2_775	(2 << 4)
+#define VAUDIO_3_0	(3 << 4)
+#define VAUDIO_MASK	(3 << 4)
+#define VSD_1_8		(0 << 6)
+#define VSD_2_0		(1 << 6)
+#define VSD_2_6		(2 << 6)
+#define VSD_2_7		(3 << 6)
+#define VSD_2_8		(4 << 6)
+#define VSD_2_9		(5 << 6)
+#define VSD_3_0		(6 << 6)
+#define VSD_3_15	(7 << 6)
+#define VSD_MASK	(7 << 6)
+#define VGEN1_1_2	0
+#define VGEN1_1_5	1
+#define VGEN1_2_775	2
+#define VGEN1_3_15	3
+#define VGEN1_MASK	3
+#define VGEN2_1_2	(0 << 6)
+#define VGEN2_1_5	(1 << 6)
+#define VGEN2_1_6	(2 << 6)
+#define VGEN2_1_8	(3 << 6)
+#define VGEN2_2_7	(4 << 6)
+#define VGEN2_2_8	(5 << 6)
+#define VGEN2_3_0	(6 << 6)
+#define VGEN2_3_15	(7 << 6)
+#define VGEN2_MASK	(7 << 6)
+
+/* Fields in REG_SETTING_1 */
+#define VGEN3_1_8	(0 << 14)
+#define VGEN3_2_9	(1 << 14)
+#define VGEN3_MASK	(1 << 14)
+#define VDIG_1_05	(0 << 4)
+#define VDIG_1_25	(1 << 4)
+#define VDIG_1_65	(2 << 4)
+#define VDIG_1_8	(3 << 4)
+#define VDIG_MASK	(3 << 4)
+#define VCAM_2_5	(0 << 16)
+#define VCAM_2_6	(1 << 16)
+#define VCAM_2_75	(2 << 16)
+#define VCAM_3_0	(3 << 16)
+#define VCAM_MASK	(3 << 16)
+
+/* Reg Mode 0 */
+#define VGEN1EN		(1 << 0)
+#define VGEN1STBY	(1 << 1)
+#define VGEN1MODE	(1 << 2)
+#define VIOHIEN		(1 << 3)
+#define VIOHISTBY	(1 << 4)
+#define VDIGEN		(1 << 9)
+#define VDIGSTBY	(1 << 10)
+#define VGEN2EN		(1 << 12)
+#define VGEN2STBY	(1 << 13)
+#define VGEN2MODE	(1 << 14)
+#define VPLLEN		(1 << 15)
+#define VPLLSTBY	(1 << 16)
+#define VUSBEN		(1 << 18)
+#define VUSBSTBY	(1 << 19)
+
+/* Reg Mode 1 */
+#define VGEN3EN		(1 << 0)
+#define VGEN3STBY	(1 << 1)
+#define VGEN3MODE	(1 << 2)
+#define VGEN3CONFIG	(1 << 3)
+#define VCAMEN		(1 << 6)
+#define VCAMSTBY	(1 << 7)
+#define VCAMMODE	(1 << 8)
+#define VCAMCONFIG	(1 << 9)
+#define VVIDEOEN	(1 << 12)
+#define VIDEOSTBY	(1 << 13)
+#define VVIDEOMODE	(1 << 14)
+#define VAUDIOEN	(1 << 15)
+#define VAUDIOSTBY	(1 << 16)
+#define VSDEN		(1 << 18)
+#define VSDSTBY		(1 << 19)
+#define VSDMODE		(1 << 20)
+
+/* Reg Power Control 2*/
+#define WDIRESET	(1 << 12)
+
+/* SWx Output Volts */
+#define SWX_OUT_MASK	0x1F
+#define SWX_OUT_1_25	0x1A
+#define SWX_OUT_1_30    0X1C
+
+/* Buck Switchers (SW1,2,3,4) Output Voltage */
+/*
+ * NOTE: These values are for SWxHI = 0,
+ * SWxHI = 1 adds 0.5V to the desired voltage
+ */
+#define SWx_0_600V	0
+#define SWx_0_625V	1
+#define SWx_0_650V	2
+#define SWx_0_675V	3
+#define SWx_0_700V	4
+#define SWx_0_725V	5
+#define SWx_0_750V	6
+#define SWx_0_775V	7
+#define SWx_0_800V	8
+#define SWx_0_825V	9
+#define SWx_0_850V	10
+#define SWx_0_875V	11
+#define SWx_0_900V	12
+#define SWx_0_925V	13
+#define SWx_0_950V	14
+#define SWx_0_975V	15
+#define SWx_1_000V	16
+#define SWx_1_025V	17
+#define SWx_1_050V	18
+#define SWx_1_075V	19
+#define SWx_1_100V	20
+#define SWx_1_125V	21
+#define SWx_1_150V	22
+#define SWx_1_175V	23
+#define SWx_1_200V	24
+#define SWx_1_225V	25
+#define SWx_1_250V	26
+#define SWx_1_275V	27
+#define SWx_1_300V	28
+#define SWx_1_325V	29
+#define SWx_1_350V	30
+#define SWx_1_375V	31
+#define SWx_VOLT_MASK	0x1F
+
+#endif
diff --git a/qemu/roms/u-boot/include/mc34704.h b/qemu/roms/u-boot/include/mc34704.h
new file mode 100644
index 000000000..53716e039
--- /dev/null
+++ b/qemu/roms/u-boot/include/mc34704.h
@@ -0,0 +1,45 @@
+/*
+ * (C) Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MC34704_H__
+#define __MC34704_H__
+
+enum {
+	MC34704_RESERVED0_REG = 0,	/* 0x00 */
+	MC34704_GENERAL1_REG,		/* 0x01 */
+	MC34704_GENERAL2_REG,		/* 0x02 */
+	MC34704_GENERAL3_REG,		/* 0x03 */
+	MC34704_RESERVED4_REG,		/* 0x04 */
+	MC34704_VGSET2_REG,		/* 0x05 */
+	MC34704_REG2SET1_REG,		/* 0x06 */
+	MC34704_REG2SET2_REG,		/* 0x07 */
+	MC34704_REG3SET1_REG,		/* 0x08 */
+	MC34704_REG3SET2_REG,		/* 0x09 */
+	MC34704_REG4SET1_REG,		/* 0x0a */
+	MC34704_REG4SET2_REG,		/* 0x0b */
+	MC34704_REG5SET1_REG,		/* 0x0c */
+	MC34704_REG5SET2_REG,		/* 0x0d */
+	MC34704_REG5SET3_REG,		/* 0x0e */
+	MC34704_RESERVEDF_REG,		/* 0x0f */
+	MC34704_RESERVED10_REG,		/* 0x10 */
+	MC34704_RESERVED11_REG,		/* 0x11 */
+	MC34704_RESERVED12_REG,		/* 0x12 */
+	MC34704_FSW2SET_REG,		/* 0x13 */
+	MC34704_RESERVED14_REG,		/* 0x14 */
+	MC34704_REG8SET1_REG,		/* 0x15 */
+	MC34704_REG8SET2_REG,		/* 0x16 */
+	MC34704_REG8SET3_REG,		/* 0x17 */
+	MC34704_FAULTS_REG,		/* 0x18 */
+	MC34704_I2CSET1,		/* 0x19 */
+	MC34704_NUM_OF_REGS,
+};
+
+/* GENERAL2 register fields */
+#define ONOFFE		(1 << 0)
+#define ONOFFD		(1 << 1)
+#define ALLOFF		(1 << 4)
+
+#endif /* __MC34704_H__ */
diff --git a/qemu/roms/u-boot/include/mc9sdz60.h b/qemu/roms/u-boot/include/mc9sdz60.h
new file mode 100644
index 000000000..7b1118138
--- /dev/null
+++ b/qemu/roms/u-boot/include/mc9sdz60.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright (C) 2009 Marc Kleine-Budde <mkl@pengutronix.de>
+ *
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_MC9SDZ60_H
+#define __ASM_ARCH_MC9SDZ60_H
+
+/**
+ * Register addresses for the MC9SDZ60
+ *
+ * @note: these match those in the kernel drivers/mxc/mcu_pmic/mc9s08dz60.h
+ * but not include/linux/mfd/mc9s08dz60/pmic.h
+ *
+ */
+enum mc9sdz60_reg {
+	MC9SDZ60_REG_VERSION		= 0x00,
+	/* reserved                       0x01 */
+	MC9SDZ60_REG_SECS		= 0x02,
+	MC9SDZ60_REG_MINS		= 0x03,
+	MC9SDZ60_REG_HRS		= 0x04,
+	MC9SDZ60_REG_DAY		= 0x05,
+	MC9SDZ60_REG_DATE		= 0x06,
+	MC9SDZ60_REG_MONTH		= 0x07,
+	MC9SDZ60_REG_YEAR		= 0x08,
+	MC9SDZ60_REG_ALARM_SECS		= 0x09,
+	MC9SDZ60_REG_ALARM_MINS		= 0x0a,
+	MC9SDZ60_REG_ALARM_HRS		= 0x0b,
+	/* reserved                       0x0c */
+	/* reserved                       0x0d */
+	MC9SDZ60_REG_TS_CONTROL		= 0x0e,
+	MC9SDZ60_REG_X_LOW		= 0x0f,
+	MC9SDZ60_REG_Y_LOW		= 0x10,
+	MC9SDZ60_REG_XY_HIGH		= 0x11,
+	MC9SDZ60_REG_X_LEFT_LOW		= 0x12,
+	MC9SDZ60_REG_X_LEFT_HIGH	= 0x13,
+	MC9SDZ60_REG_X_RIGHT		= 0x14,
+	MC9SDZ60_REG_Y_TOP_LOW		= 0x15,
+	MC9SDZ60_REG_Y_TOP_HIGH		= 0x16,
+	MC9SDZ60_REG_Y_BOTTOM		= 0x17,
+	/* reserved                       0x18 */
+	/* reserved                       0x19 */
+	MC9SDZ60_REG_RESET_1		= 0x1a,
+	MC9SDZ60_REG_RESET_2		= 0x1b,
+	MC9SDZ60_REG_POWER_CTL		= 0x1c,
+	MC9SDZ60_REG_DELAY_CONFIG	= 0x1d,
+	/* reserved                       0x1e */
+	/* reserved                       0x1f */
+	MC9SDZ60_REG_GPIO_1		= 0x20,
+	MC9SDZ60_REG_GPIO_2		= 0x21,
+	MC9SDZ60_REG_KPD_1		= 0x22,
+	MC9SDZ60_REG_KPD_2		= 0x23,
+	MC9SDZ60_REG_KPD_CONTROL	= 0x24,
+	MC9SDZ60_REG_INT_ENABLE_1	= 0x25,
+	MC9SDZ60_REG_INT_ENABLE_2	= 0x26,
+	MC9SDZ60_REG_INT_FLAG_1		= 0x27,
+	MC9SDZ60_REG_INT_FLAG_2		= 0x28,
+	MC9SDZ60_REG_DES_FLAG		= 0x29,
+};
+
+extern u8 mc9sdz60_reg_read(enum mc9sdz60_reg reg);
+extern void mc9sdz60_reg_write(enum mc9sdz60_reg reg, u8 val);
+
+#endif /* __ASM_ARCH_MC9SDZ60_H */
diff --git a/qemu/roms/u-boot/include/menu.h b/qemu/roms/u-boot/include/menu.h
new file mode 100644
index 000000000..063cd196b
--- /dev/null
+++ b/qemu/roms/u-boot/include/menu.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright 2010-2011 Calxeda, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MENU_H__
+#define __MENU_H__
+
+struct menu;
+
+struct menu *menu_create(char *title, int timeout, int prompt,
+				void (*item_data_print)(void *),
+				char *(*item_choice)(void *),
+				void *item_choice_data);
+int menu_default_set(struct menu *m, char *item_key);
+int menu_get_choice(struct menu *m, void **choice);
+int menu_item_add(struct menu *m, char *item_key, void *item_data);
+int menu_destroy(struct menu *m);
+void menu_display_statusline(struct menu *m);
+int menu_default_choice(struct menu *m, void **choice);
+
+#if defined(CONFIG_MENU_SHOW)
+int menu_show(int bootdelay);
+#endif
+#endif /* __MENU_H__ */
diff --git a/qemu/roms/u-boot/include/micrel.h b/qemu/roms/u-boot/include/micrel.h
new file mode 100644
index 000000000..04c9ecf3b
--- /dev/null
+++ b/qemu/roms/u-boot/include/micrel.h
@@ -0,0 +1,32 @@
+#ifndef _MICREL_H
+
+#define MII_KSZ9021_EXT_COMMON_CTRL		0x100
+#define MII_KSZ9021_EXT_STRAP_STATUS		0x101
+#define MII_KSZ9021_EXT_OP_STRAP_OVERRIDE	0x102
+#define MII_KSZ9021_EXT_OP_STRAP_STATUS		0x103
+#define MII_KSZ9021_EXT_RGMII_CLOCK_SKEW	0x104
+#define MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW	0x105
+#define MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW	0x106
+#define MII_KSZ9021_EXT_ANALOG_TEST		0x107
+/* Register operations */
+#define MII_KSZ9031_MOD_REG			0x0000
+/* Data operations */
+#define MII_KSZ9031_MOD_DATA_NO_POST_INC	0x4000
+#define MII_KSZ9031_MOD_DATA_POST_INC_RW	0x8000
+#define MII_KSZ9031_MOD_DATA_POST_INC_W		0xC000
+
+#define MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW	0x4
+#define MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW	0x5
+#define MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW	0x6
+#define MII_KSZ9031_EXT_RGMII_CLOCK_SKEW	0x8
+
+struct phy_device;
+int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val);
+int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum);
+
+int ksz9031_phy_extended_write(struct phy_device *phydev, int devaddr,
+			       int regnum, u16 mode, u16 val);
+int ksz9031_phy_extended_read(struct phy_device *phydev, int devaddr,
+			      int regnum, u16 mode);
+
+#endif
diff --git a/qemu/roms/u-boot/include/mii_phy.h b/qemu/roms/u-boot/include/mii_phy.h
new file mode 100644
index 000000000..f0d3e6282
--- /dev/null
+++ b/qemu/roms/u-boot/include/mii_phy.h
@@ -0,0 +1,8 @@
+#ifndef _MII_PHY_H_
+#define _MII_PHY_H_
+
+void mii_discover_phy(void);
+unsigned short mii_phy_read(unsigned short reg);
+void mii_phy_write(unsigned short reg, unsigned short val);
+
+#endif
diff --git a/qemu/roms/u-boot/include/miiphy.h b/qemu/roms/u-boot/include/miiphy.h
new file mode 100644
index 000000000..088797e4c
--- /dev/null
+++ b/qemu/roms/u-boot/include/miiphy.h
@@ -0,0 +1,124 @@
+/*
+ * SPDX-License-Identifier:	GPL-2.0	IBM-pibs
+ *
+ * Additions (C) Copyright 2009 Industrie Dial Face S.p.A.
+ */
+/*----------------------------------------------------------------------------+
+|
+|  File Name:	miiphy.h
+|
+|  Function:	Include file defining PHY registers.
+|
+|  Author:	Mark Wisner
+|
++----------------------------------------------------------------------------*/
+#ifndef _miiphy_h_
+#define _miiphy_h_
+
+#include <common.h>
+#include <linux/mii.h>
+#include <linux/list.h>
+#include <net.h>
+#include <phy.h>
+
+struct legacy_mii_dev {
+	int (*read)(const char *devname, unsigned char addr,
+		     unsigned char reg, unsigned short *value);
+	int (*write)(const char *devname, unsigned char addr,
+		      unsigned char reg, unsigned short value);
+};
+
+int miiphy_read(const char *devname, unsigned char addr, unsigned char reg,
+		 unsigned short *value);
+int miiphy_write(const char *devname, unsigned char addr, unsigned char reg,
+		  unsigned short value);
+int miiphy_info(const char *devname, unsigned char addr, unsigned int *oui,
+		 unsigned char *model, unsigned char *rev);
+int miiphy_reset(const char *devname, unsigned char addr);
+int miiphy_speed(const char *devname, unsigned char addr);
+int miiphy_duplex(const char *devname, unsigned char addr);
+int miiphy_is_1000base_x(const char *devname, unsigned char addr);
+#ifdef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+int miiphy_link(const char *devname, unsigned char addr);
+#endif
+
+void miiphy_init(void);
+
+void miiphy_register(const char *devname,
+		      int (*read)(const char *devname, unsigned char addr,
+				   unsigned char reg, unsigned short *value),
+		      int (*write)(const char *devname, unsigned char addr,
+				    unsigned char reg, unsigned short value));
+
+int miiphy_set_current_dev(const char *devname);
+const char *miiphy_get_current_dev(void);
+struct mii_dev *mdio_get_current_dev(void);
+struct mii_dev *miiphy_get_dev_by_name(const char *devname);
+struct phy_device *mdio_phydev_for_ethname(const char *devname);
+
+void miiphy_listdev(void);
+
+struct mii_dev *mdio_alloc(void);
+int mdio_register(struct mii_dev *bus);
+void mdio_list_devices(void);
+
+#ifdef CONFIG_BITBANGMII
+
+#define BB_MII_DEVNAME	"bb_miiphy"
+
+struct bb_miiphy_bus {
+	char name[16];
+	int (*init)(struct bb_miiphy_bus *bus);
+	int (*mdio_active)(struct bb_miiphy_bus *bus);
+	int (*mdio_tristate)(struct bb_miiphy_bus *bus);
+	int (*set_mdio)(struct bb_miiphy_bus *bus, int v);
+	int (*get_mdio)(struct bb_miiphy_bus *bus, int *v);
+	int (*set_mdc)(struct bb_miiphy_bus *bus, int v);
+	int (*delay)(struct bb_miiphy_bus *bus);
+#ifdef CONFIG_BITBANGMII_MULTI
+	void *priv;
+#endif
+};
+
+extern struct bb_miiphy_bus bb_miiphy_buses[];
+extern int bb_miiphy_buses_num;
+
+void bb_miiphy_init(void);
+int bb_miiphy_read(const char *devname, unsigned char addr,
+		    unsigned char reg, unsigned short *value);
+int bb_miiphy_write(const char *devname, unsigned char addr,
+		     unsigned char reg, unsigned short value);
+#endif
+
+/* phy seed setup */
+#define AUTO			99
+#define _1000BASET		1000
+#define _100BASET		100
+#define _10BASET		10
+#define HALF			22
+#define FULL			44
+
+/* phy register offsets */
+#define MII_MIPSCR		0x11
+
+/* MII_LPA */
+#define PHY_ANLPAR_PSB_802_3	0x0001
+#define PHY_ANLPAR_PSB_802_9	0x0002
+
+/* MII_CTRL1000 masks */
+#define PHY_1000BTCR_1000FD	0x0200
+#define PHY_1000BTCR_1000HD	0x0100
+
+/* MII_STAT1000 masks */
+#define PHY_1000BTSR_MSCF	0x8000
+#define PHY_1000BTSR_MSCR	0x4000
+#define PHY_1000BTSR_LRS	0x2000
+#define PHY_1000BTSR_RRS	0x1000
+#define PHY_1000BTSR_1000FD	0x0800
+#define PHY_1000BTSR_1000HD	0x0400
+
+/* phy EXSR */
+#define ESTATUS_1000XF		0x8000
+#define ESTATUS_1000XH		0x4000
+
+#endif
diff --git a/qemu/roms/u-boot/include/mk48t59.h b/qemu/roms/u-boot/include/mk48t59.h
new file mode 100644
index 000000000..3ddc034c9
--- /dev/null
+++ b/qemu/roms/u-boot/include/mk48t59.h
@@ -0,0 +1,48 @@
+/*
+ * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Andreas Heppel <aheppel@sysgo.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Date & Time support for the MK48T59 RTC
+ */
+
+
+#if defined(CONFIG_RTC_MK48T59) && defined(CONFIG_CMD_DATE)
+
+#define RTC_PORT_ADDR0		CONFIG_SYS_ISA_IO +  0x70
+#define RTC_PORT_ADDR1		RTC_PORT_ADDR0 +  0x1
+#define RTC_PORT_DATA		CONFIG_SYS_ISA_IO +  0x76
+
+/* RTC Offsets */
+#define RTC_SECONDS             0x1FF9
+#define RTC_MINUTES             0x1FFA
+#define RTC_HOURS               0x1FFB
+#define RTC_DAY_OF_WEEK         0x1FFC
+#define RTC_DAY_OF_MONTH        0x1FFD
+#define RTC_MONTH               0x1FFE
+#define RTC_YEAR                0x1FFF
+
+#define RTC_CONTROLA            0x1FF8
+#define RTC_CA_WRITE            0x80
+#define RTC_CA_READ             0x40
+#define RTC_CA_CALIB_SIGN       0x20
+#define RTC_CA_CALIB_MASK       0x1f
+
+#define RTC_CONTROLB            0x1FF9
+#define RTC_CB_STOP             0x80
+
+#define RTC_WATCHDOG			0x1FF7
+#define RTC_WDS					0x80
+#define RTC_WD_RB_16TH			0x0
+#define RTC_WD_RB_4TH			0x1
+#define RTC_WD_RB_1				0x2
+#define RTC_WD_RB_4				0x3
+
+void rtc_set_watchdog(short multi, short res);
+void *nvram_read(void *dest, const short src, size_t count);
+void nvram_write(short dest, const void *src, size_t count);
+
+#endif
diff --git a/qemu/roms/u-boot/include/mmc.h b/qemu/roms/u-boot/include/mmc.h
new file mode 100644
index 000000000..bc11f45a6
--- /dev/null
+++ b/qemu/roms/u-boot/include/mmc.h
@@ -0,0 +1,383 @@
+/*
+ * Copyright 2008,2010 Freescale Semiconductor, Inc
+ * Andy Fleming
+ *
+ * Based (loosely) on the Linux code
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _MMC_H_
+#define _MMC_H_
+
+#include <linux/list.h>
+#include <linux/compiler.h>
+#include <part.h>
+
+#define SD_VERSION_SD	0x20000
+#define SD_VERSION_3	(SD_VERSION_SD | 0x300)
+#define SD_VERSION_2	(SD_VERSION_SD | 0x200)
+#define SD_VERSION_1_0	(SD_VERSION_SD | 0x100)
+#define SD_VERSION_1_10	(SD_VERSION_SD | 0x10a)
+#define MMC_VERSION_MMC		0x10000
+#define MMC_VERSION_UNKNOWN	(MMC_VERSION_MMC)
+#define MMC_VERSION_1_2		(MMC_VERSION_MMC | 0x102)
+#define MMC_VERSION_1_4		(MMC_VERSION_MMC | 0x104)
+#define MMC_VERSION_2_2		(MMC_VERSION_MMC | 0x202)
+#define MMC_VERSION_3		(MMC_VERSION_MMC | 0x300)
+#define MMC_VERSION_4		(MMC_VERSION_MMC | 0x400)
+#define MMC_VERSION_4_1		(MMC_VERSION_MMC | 0x401)
+#define MMC_VERSION_4_2		(MMC_VERSION_MMC | 0x402)
+#define MMC_VERSION_4_3		(MMC_VERSION_MMC | 0x403)
+#define MMC_VERSION_4_41	(MMC_VERSION_MMC | 0x429)
+#define MMC_VERSION_4_5		(MMC_VERSION_MMC | 0x405)
+
+#define MMC_MODE_HS		0x001
+#define MMC_MODE_HS_52MHz	0x010
+#define MMC_MODE_4BIT		0x100
+#define MMC_MODE_8BIT		0x200
+#define MMC_MODE_SPI		0x400
+#define MMC_MODE_HC		0x800
+
+#define MMC_MODE_MASK_WIDTH_BITS (MMC_MODE_4BIT | MMC_MODE_8BIT)
+#define MMC_MODE_WIDTH_BITS_SHIFT 8
+
+#define SD_DATA_4BIT	0x00040000
+
+#define IS_SD(x) (x->version & SD_VERSION_SD)
+
+#define MMC_DATA_READ		1
+#define MMC_DATA_WRITE		2
+
+#define NO_CARD_ERR		-16 /* No SD/MMC card inserted */
+#define UNUSABLE_ERR		-17 /* Unusable Card */
+#define COMM_ERR		-18 /* Communications Error */
+#define TIMEOUT			-19
+#define IN_PROGRESS		-20 /* operation is in progress */
+
+#define MMC_CMD_GO_IDLE_STATE		0
+#define MMC_CMD_SEND_OP_COND		1
+#define MMC_CMD_ALL_SEND_CID		2
+#define MMC_CMD_SET_RELATIVE_ADDR	3
+#define MMC_CMD_SET_DSR			4
+#define MMC_CMD_SWITCH			6
+#define MMC_CMD_SELECT_CARD		7
+#define MMC_CMD_SEND_EXT_CSD		8
+#define MMC_CMD_SEND_CSD		9
+#define MMC_CMD_SEND_CID		10
+#define MMC_CMD_STOP_TRANSMISSION	12
+#define MMC_CMD_SEND_STATUS		13
+#define MMC_CMD_SET_BLOCKLEN		16
+#define MMC_CMD_READ_SINGLE_BLOCK	17
+#define MMC_CMD_READ_MULTIPLE_BLOCK	18
+#define MMC_CMD_WRITE_SINGLE_BLOCK	24
+#define MMC_CMD_WRITE_MULTIPLE_BLOCK	25
+#define MMC_CMD_ERASE_GROUP_START	35
+#define MMC_CMD_ERASE_GROUP_END		36
+#define MMC_CMD_ERASE			38
+#define MMC_CMD_APP_CMD			55
+#define MMC_CMD_SPI_READ_OCR		58
+#define MMC_CMD_SPI_CRC_ON_OFF		59
+#define MMC_CMD_RES_MAN			62
+
+#define MMC_CMD62_ARG1			0xefac62ec
+#define MMC_CMD62_ARG2			0xcbaea7
+
+
+#define SD_CMD_SEND_RELATIVE_ADDR	3
+#define SD_CMD_SWITCH_FUNC		6
+#define SD_CMD_SEND_IF_COND		8
+
+#define SD_CMD_APP_SET_BUS_WIDTH	6
+#define SD_CMD_ERASE_WR_BLK_START	32
+#define SD_CMD_ERASE_WR_BLK_END		33
+#define SD_CMD_APP_SEND_OP_COND		41
+#define SD_CMD_APP_SEND_SCR		51
+
+/* SCR definitions in different words */
+#define SD_HIGHSPEED_BUSY	0x00020000
+#define SD_HIGHSPEED_SUPPORTED	0x00020000
+
+#define MMC_HS_TIMING		0x00000100
+#define MMC_HS_52MHZ		0x2
+
+#define OCR_BUSY		0x80000000
+#define OCR_HCS			0x40000000
+#define OCR_VOLTAGE_MASK	0x007FFF80
+#define OCR_ACCESS_MODE		0x60000000
+
+#define SECURE_ERASE		0x80000000
+
+#define MMC_STATUS_MASK		(~0x0206BF7F)
+#define MMC_STATUS_RDY_FOR_DATA (1 << 8)
+#define MMC_STATUS_CURR_STATE	(0xf << 9)
+#define MMC_STATUS_ERROR	(1 << 19)
+
+#define MMC_STATE_PRG		(7 << 9)
+
+#define MMC_VDD_165_195		0x00000080	/* VDD voltage 1.65 - 1.95 */
+#define MMC_VDD_20_21		0x00000100	/* VDD voltage 2.0 ~ 2.1 */
+#define MMC_VDD_21_22		0x00000200	/* VDD voltage 2.1 ~ 2.2 */
+#define MMC_VDD_22_23		0x00000400	/* VDD voltage 2.2 ~ 2.3 */
+#define MMC_VDD_23_24		0x00000800	/* VDD voltage 2.3 ~ 2.4 */
+#define MMC_VDD_24_25		0x00001000	/* VDD voltage 2.4 ~ 2.5 */
+#define MMC_VDD_25_26		0x00002000	/* VDD voltage 2.5 ~ 2.6 */
+#define MMC_VDD_26_27		0x00004000	/* VDD voltage 2.6 ~ 2.7 */
+#define MMC_VDD_27_28		0x00008000	/* VDD voltage 2.7 ~ 2.8 */
+#define MMC_VDD_28_29		0x00010000	/* VDD voltage 2.8 ~ 2.9 */
+#define MMC_VDD_29_30		0x00020000	/* VDD voltage 2.9 ~ 3.0 */
+#define MMC_VDD_30_31		0x00040000	/* VDD voltage 3.0 ~ 3.1 */
+#define MMC_VDD_31_32		0x00080000	/* VDD voltage 3.1 ~ 3.2 */
+#define MMC_VDD_32_33		0x00100000	/* VDD voltage 3.2 ~ 3.3 */
+#define MMC_VDD_33_34		0x00200000	/* VDD voltage 3.3 ~ 3.4 */
+#define MMC_VDD_34_35		0x00400000	/* VDD voltage 3.4 ~ 3.5 */
+#define MMC_VDD_35_36		0x00800000	/* VDD voltage 3.5 ~ 3.6 */
+
+#define MMC_SWITCH_MODE_CMD_SET		0x00 /* Change the command set */
+#define MMC_SWITCH_MODE_SET_BITS	0x01 /* Set bits in EXT_CSD byte
+						addressed by index which are
+						1 in value field */
+#define MMC_SWITCH_MODE_CLEAR_BITS	0x02 /* Clear bits in EXT_CSD byte
+						addressed by index, which are
+						1 in value field */
+#define MMC_SWITCH_MODE_WRITE_BYTE	0x03 /* Set target byte to value */
+
+#define SD_SWITCH_CHECK		0
+#define SD_SWITCH_SWITCH	1
+
+/*
+ * EXT_CSD fields
+ */
+#define EXT_CSD_GP_SIZE_MULT		143	/* R/W */
+#define EXT_CSD_PARTITIONS_ATTRIBUTE	156	/* R/W */
+#define EXT_CSD_PARTITIONING_SUPPORT	160	/* RO */
+#define EXT_CSD_RST_N_FUNCTION		162	/* R/W */
+#define EXT_CSD_RPMB_MULT		168	/* RO */
+#define EXT_CSD_ERASE_GROUP_DEF		175	/* R/W */
+#define EXT_CSD_BOOT_BUS_WIDTH		177
+#define EXT_CSD_PART_CONF		179	/* R/W */
+#define EXT_CSD_BUS_WIDTH		183	/* R/W */
+#define EXT_CSD_HS_TIMING		185	/* R/W */
+#define EXT_CSD_REV			192	/* RO */
+#define EXT_CSD_CARD_TYPE		196	/* RO */
+#define EXT_CSD_SEC_CNT			212	/* RO, 4 bytes */
+#define EXT_CSD_HC_WP_GRP_SIZE		221	/* RO */
+#define EXT_CSD_HC_ERASE_GRP_SIZE	224	/* RO */
+#define EXT_CSD_BOOT_MULT		226	/* RO */
+
+/*
+ * EXT_CSD field definitions
+ */
+
+#define EXT_CSD_CMD_SET_NORMAL		(1 << 0)
+#define EXT_CSD_CMD_SET_SECURE		(1 << 1)
+#define EXT_CSD_CMD_SET_CPSECURE	(1 << 2)
+
+#define EXT_CSD_CARD_TYPE_26	(1 << 0)	/* Card can run at 26MHz */
+#define EXT_CSD_CARD_TYPE_52	(1 << 1)	/* Card can run at 52MHz */
+
+#define EXT_CSD_BUS_WIDTH_1	0	/* Card is in 1 bit mode */
+#define EXT_CSD_BUS_WIDTH_4	1	/* Card is in 4 bit mode */
+#define EXT_CSD_BUS_WIDTH_8	2	/* Card is in 8 bit mode */
+
+#define EXT_CSD_BOOT_ACK_ENABLE			(1 << 6)
+#define EXT_CSD_BOOT_PARTITION_ENABLE		(1 << 3)
+#define EXT_CSD_PARTITION_ACCESS_ENABLE		(1 << 0)
+#define EXT_CSD_PARTITION_ACCESS_DISABLE	(0 << 0)
+
+#define EXT_CSD_BOOT_ACK(x)		(x << 6)
+#define EXT_CSD_BOOT_PART_NUM(x)	(x << 3)
+#define EXT_CSD_PARTITION_ACCESS(x)	(x << 0)
+
+#define EXT_CSD_BOOT_BUS_WIDTH_MODE(x)	(x << 3)
+#define EXT_CSD_BOOT_BUS_WIDTH_RESET(x)	(x << 2)
+#define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x)	(x)
+
+#define R1_ILLEGAL_COMMAND		(1 << 22)
+#define R1_APP_CMD			(1 << 5)
+
+#define MMC_RSP_PRESENT (1 << 0)
+#define MMC_RSP_136	(1 << 1)		/* 136 bit response */
+#define MMC_RSP_CRC	(1 << 2)		/* expect valid crc */
+#define MMC_RSP_BUSY	(1 << 3)		/* card may send busy */
+#define MMC_RSP_OPCODE	(1 << 4)		/* response contains opcode */
+
+#define MMC_RSP_NONE	(0)
+#define MMC_RSP_R1	(MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
+#define MMC_RSP_R1b	(MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
+			MMC_RSP_BUSY)
+#define MMC_RSP_R2	(MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
+#define MMC_RSP_R3	(MMC_RSP_PRESENT)
+#define MMC_RSP_R4	(MMC_RSP_PRESENT)
+#define MMC_RSP_R5	(MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
+#define MMC_RSP_R6	(MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
+#define MMC_RSP_R7	(MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
+
+#define MMCPART_NOAVAILABLE	(0xff)
+#define PART_ACCESS_MASK	(0x7)
+#define PART_SUPPORT		(0x1)
+#define PART_ENH_ATTRIB		(0x1f)
+
+/* Maximum block size for MMC */
+#define MMC_MAX_BLOCK_LEN	512
+
+/* The number of MMC physical partitions.  These consist of:
+ * boot partitions (2), general purpose partitions (4) in MMC v4.4.
+ */
+#define MMC_NUM_BOOT_PARTITION	2
+
+struct mmc_cid {
+	unsigned long psn;
+	unsigned short oid;
+	unsigned char mid;
+	unsigned char prv;
+	unsigned char mdt;
+	char pnm[7];
+};
+
+struct mmc_cmd {
+	ushort cmdidx;
+	uint resp_type;
+	uint cmdarg;
+	uint response[4];
+};
+
+struct mmc_data {
+	union {
+		char *dest;
+		const char *src; /* src buffers don't get written to */
+	};
+	uint flags;
+	uint blocks;
+	uint blocksize;
+};
+
+/* forward decl. */
+struct mmc;
+
+struct mmc_ops {
+	int (*send_cmd)(struct mmc *mmc,
+			struct mmc_cmd *cmd, struct mmc_data *data);
+	void (*set_ios)(struct mmc *mmc);
+	int (*init)(struct mmc *mmc);
+	int (*getcd)(struct mmc *mmc);
+	int (*getwp)(struct mmc *mmc);
+};
+
+struct mmc_config {
+	const char *name;
+	const struct mmc_ops *ops;
+	uint host_caps;
+	uint voltages;
+	uint f_min;
+	uint f_max;
+	uint b_max;
+	unsigned char part_type;
+};
+
+/* TODO struct mmc should be in mmc_private but it's hard to fix right now */
+struct mmc {
+	struct list_head link;
+	const struct mmc_config *cfg;	/* provided configuration */
+	uint version;
+	void *priv;
+	uint has_init;
+	int high_capacity;
+	uint bus_width;
+	uint clock;
+	uint card_caps;
+	uint ocr;
+	uint dsr;
+	uint dsr_imp;
+	uint scr[2];
+	uint csd[4];
+	uint cid[4];
+	ushort rca;
+	char part_config;
+	char part_num;
+	uint tran_speed;
+	uint read_bl_len;
+	uint write_bl_len;
+	uint erase_grp_size;
+	u64 capacity;
+	u64 capacity_user;
+	u64 capacity_boot;
+	u64 capacity_rpmb;
+	u64 capacity_gp[4];
+	block_dev_desc_t block_dev;
+	char op_cond_pending;	/* 1 if we are waiting on an op_cond command */
+	char init_in_progress;	/* 1 if we have done mmc_start_init() */
+	char preinit;		/* start init as early as possible */
+	uint op_cond_response;	/* the response byte from the last op_cond */
+};
+
+int mmc_register(struct mmc *mmc);
+struct mmc *mmc_create(const struct mmc_config *cfg, void *priv);
+void mmc_destroy(struct mmc *mmc);
+int mmc_initialize(bd_t *bis);
+int mmc_init(struct mmc *mmc);
+int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
+void mmc_set_clock(struct mmc *mmc, uint clock);
+struct mmc *find_mmc_device(int dev_num);
+int mmc_set_dev(int dev_num);
+void print_mmc_devices(char separator);
+int get_mmc_num(void);
+int board_mmc_getcd(struct mmc *mmc);
+int mmc_switch_part(int dev_num, unsigned int part_num);
+int mmc_getcd(struct mmc *mmc);
+int mmc_getwp(struct mmc *mmc);
+int mmc_set_dsr(struct mmc *mmc, u16 val);
+/* Function to change the size of boot partition and rpmb partitions */
+int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
+					unsigned long rpmbsize);
+/* Function to modify the PARTITION_CONFIG field of EXT_CSD */
+int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access);
+/* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */
+int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode);
+/* Function to modify the RST_n_FUNCTION field of EXT_CSD */
+int mmc_set_rst_n_function(struct mmc *mmc, u8 enable);
+
+/**
+ * Start device initialization and return immediately; it does not block on
+ * polling OCR (operation condition register) status.  Then you should call
+ * mmc_init, which would block on polling OCR status and complete the device
+ * initializatin.
+ *
+ * @param mmc	Pointer to a MMC device struct
+ * @return 0 on success, IN_PROGRESS on waiting for OCR status, <0 on error.
+ */
+int mmc_start_init(struct mmc *mmc);
+
+/**
+ * Set preinit flag of mmc device.
+ *
+ * This will cause the device to be pre-inited during mmc_initialize(),
+ * which may save boot time if the device is not accessed until later.
+ * Some eMMC devices take 200-300ms to init, but unfortunately they
+ * must be sent a series of commands to even get them to start preparing
+ * for operation.
+ *
+ * @param mmc		Pointer to a MMC device struct
+ * @param preinit	preinit flag value
+ */
+void mmc_set_preinit(struct mmc *mmc, int preinit);
+
+#ifdef CONFIG_GENERIC_MMC
+#ifdef CONFIG_MMC_SPI
+#define mmc_host_is_spi(mmc)	((mmc)->cfg->host_caps & MMC_MODE_SPI)
+#else
+#define mmc_host_is_spi(mmc)	0
+#endif
+struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode);
+#else
+int mmc_legacy_init(int verbose);
+#endif
+
+int board_mmc_init(bd_t *bis);
+
+/* Set block count limit because of 16 bit register limit on some hardware*/
+#ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
+#define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
+#endif
+
+#endif /* _MMC_H_ */
diff --git a/qemu/roms/u-boot/include/mpc106.h b/qemu/roms/u-boot/include/mpc106.h
new file mode 100644
index 000000000..32f5350f1
--- /dev/null
+++ b/qemu/roms/u-boot/include/mpc106.h
@@ -0,0 +1,141 @@
+/*
+ * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Andreas Heppel <aheppel@sysgo.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _MPC106_PCI_H
+#define _MPC106_PCI_H
+
+/*
+ * Defines for the MPC106 PCI Config address and data registers followed by
+ * defines for the standard PCI device configuration header.
+ */
+#define PCIDEVID_MPC106			0x0
+
+/*
+ * MPC106 Registers
+ */
+#define	MPC106_REG			0x80000000
+
+#ifdef CONFIG_SYS_ADDRESS_MAP_A
+#define MPC106_REG_ADDR			0x80000cf8
+#define	MPC106_REG_DATA			0x80000cfc
+#define MPC106_ISA_IO_PHYS		0x80000000
+#define MPC106_ISA_IO_BUS		0x00000000
+#define MPC106_ISA_IO_SIZE		0x00800000
+#define MPC106_PCI_IO_PHYS		0x81000000
+#define MPC106_PCI_IO_BUS		0x01000000
+#define MPC106_PCI_IO_SIZE		0x3e800000
+#define MPC106_PCI_MEM_PHYS		0xc0000000
+#define MPC106_PCI_MEM_BUS		0x00000000
+#define MPC106_PCI_MEM_SIZE		0x3f000000
+#define	MPC106_PCI_MEMORY_PHYS		0x00000000
+#define	MPC106_PCI_MEMORY_BUS		0x80000000
+#define	MPC106_PCI_MEMORY_SIZE		0x80000000
+#else
+#define MPC106_REG_ADDR			0xfec00cf8
+#define	MPC106_REG_DATA			0xfee00cfc
+#define MPC106_ISA_MEM_PHYS		0xfd000000
+#define MPC106_ISA_MEM_BUS		0x00000000
+#define MPC106_ISA_MEM_SIZE		0x01000000
+#define MPC106_ISA_IO_PHYS		0xfe000000
+#define MPC106_ISA_IO_BUS		0x00000000
+#define MPC106_ISA_IO_SIZE		0x00800000
+#define MPC106_PCI_IO_PHYS		0xfe800000
+#define MPC106_PCI_IO_BUS		0x00800000
+#define MPC106_PCI_IO_SIZE		0x00400000
+#define MPC106_PCI_MEM_PHYS		0x80000000
+#define MPC106_PCI_MEM_BUS		0x80000000
+#define MPC106_PCI_MEM_SIZE		0x7d000000
+#define	MPC106_PCI_MEMORY_PHYS		0x00000000
+#define	MPC106_PCI_MEMORY_BUS		0x00000000
+#define MPC106_PCI_MEMORY_SIZE		0x40000000
+#endif
+
+#define CMD_SERR			0x0100
+#define PCI_CMD_MASTER			0x0004
+#define PCI_CMD_MEMEN			0x0002
+#define PCI_CMD_IOEN			0x0001
+
+#define PCI_STAT_NO_RSV_BITS		0xffff
+
+#define PCI_BUSNUM			0x40
+#define PCI_SUBBUSNUM			0x41
+#define PCI_DISCOUNT			0x42
+
+#define PCI_PICR1			0xA8
+#define PICR1_CF_CBA(value)		((value & 0xff) << 24)
+#define PICR1_CF_BREAD_WS(value)	((value & 0x3) << 22)
+#define PICR1_PROC_TYPE_603		0x40000
+#define PICR1_PROC_TYPE_604		0x60000
+#define PICR1_MCP_EN			0x800
+#define PICR1_CF_DPARK			0x200
+#define PICR1_CF_LOOP_SNOOP		0x10
+#define PICR1_CF_L2_COPY_BACK		0x2
+#define PICR1_CF_L2_CACHE_MASK		0x3
+#define PICR1_CF_APARK			0x8
+#define PICR1_ADDRESS_MAP		0x10000
+#define PICR1_XIO_MODE			0x80000
+#define PICR1_CF_CACHE_1G		0x200000
+
+#define PCI_PICR2			0xAC
+#define PICR2_CF_SNOOP_WS(value)	((value & 0x3) << 18)
+#define PICR2_CF_FLUSH_L2		0x10000000
+#define PICR2_CF_L2_HIT_DELAY(value)	((value & 0x3) << 9)
+#define PICR2_CF_APHASE_WS(value)	((value & 0x3) << 2)
+#define PICR2_CF_INV_MODE		0x00001000
+#define PICR2_CF_MOD_HIGH		0x00020000
+#define PICR2_CF_HIT_HIGH		0x00010000
+#define PICR2_L2_SIZE_256K		0x00000000
+#define PICR2_L2_SIZE_512K		0x00000010
+#define PICR2_L2_SIZE_1MB		0x00000020
+#define PICR2_L2_EN			0x40000000
+#define PICR2_L2_UPDATE_EN		0x80000000
+#define PICR2_CF_ADDR_ONLY_DISABLE	0x00004000
+#define PICR2_CF_FAST_CASTOUT		0x00000080
+#define PICR2_CF_WDATA			0x00000001
+#define PICR2_CF_DATA_RAM_PBURST	0x00400000
+
+/*
+ * Memory controller
+ */
+#define MPC106_MCCR1			0xF0
+#define MCCR1_TYPE_EDO			0x00020000
+#define MCCR1_BK0_9BITS			0x0
+#define MCCR1_BK0_10BITS		0x1
+#define MCCR1_BK0_11BITS		0x2
+#define MCCR1_BK0_12BITS		0x3
+#define MCCR1_BK1_9BITS			0x0
+#define MCCR1_BK1_10BITS		0x4
+#define MCCR1_BK1_11BITS		0x8
+#define MCCR1_BK1_12BITS		0xC
+#define MCCR1_BK2_9BITS			0x00
+#define MCCR1_BK2_10BITS		0x10
+#define MCCR1_BK2_11BITS		0x20
+#define MCCR1_BK2_12BITS		0x30
+#define MCCR1_BK3_9BITS			0x00
+#define MCCR1_BK3_10BITS		0x40
+#define MCCR1_BK3_11BITS		0x80
+#define MCCR1_BK3_12BITS		0xC0
+#define MCCR1_MEMGO			0x00080000
+
+#define MPC106_MCCR2			0xF4
+#define MPC106_MCCR3			0xF8
+#define MPC106_MCCR4			0xFC
+
+#define MPC106_MSAR1			0x80
+#define MPC106_EMSAR1			0x88
+#define MPC106_EMSAR2			0x8C
+#define MPC106_MEAR1			0x90
+#define MPC106_EMEAR1			0x98
+#define MPC106_EMEAR2			0x9C
+
+#define MPC106_MBER			0xA0
+#define MBER_BANK0			0x1
+#define MBER_BANK1			0x2
+#define MBER_BANK2			0x4
+#define MBER_BANK3			0x8
+
+#endif
diff --git a/qemu/roms/u-boot/include/mpc5xx.h b/qemu/roms/u-boot/include/mpc5xx.h
new file mode 100644
index 000000000..6c170dcb0
--- /dev/null
+++ b/qemu/roms/u-boot/include/mpc5xx.h
@@ -0,0 +1,173 @@
+/*
+ * (C) Copyright 2003
+ * Martin Winistoerfer, martinwinistoerfer@gmx.ch.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * File:		mpc5xx.h
+ *
+ * Discription:		mpc5xx specific definitions
+ *
+ */
+
+#ifndef __MPC5XX_H__
+#define __MPC5XX_H__
+
+
+/*-----------------------------------------------------------------------
+ * Exception offsets (PowerPC standard)
+ */
+#define EXC_OFF_SYS_RESET	0x0100	/* System reset				*/
+#define _START_OFFSET		EXC_OFF_SYS_RESET
+
+/*-----------------------------------------------------------------------
+ * ISB bit in IMMR to set internal memory map
+ */
+
+#define CONFIG_SYS_ISB			((CONFIG_SYS_IMMR / 0x00400000) << 1)
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control Register
+ */
+#define SYPCR_SWTC	0xffff0000	/* Software Watchdog Timer Count	*/
+#define SYPCR_BMT	0x0000ff00	/* Bus Monitor Timing			*/
+#define SYPCR_BME	0x00000080	/* Bus Monitor Enable			*/
+#define SYPCR_SWF	0x00000008	/* Software Watchdog Freeze		*/
+#define SYPCR_SWE	0x00000004	/* Software Watchdog Enable		*/
+#define SYPCR_SWRI	0x00000002	/* Software Watchdog Reset/Int Select	*/
+#define SYPCR_SWP	0x00000001	/* Software Watchdog Prescale		*/
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration Register
+ */
+#define SIUMCR_EARB	0x80000000	/* External Arbitration			*/
+#define SIUMCR_EARP0	0x00000000	/* External Arbi. Request priority 0	*/
+#define SIUMCR_EARP1	0x10000000	/* External Arbi. Request priority 1	*/
+#define SIUMCR_EARP2	0x20000000	/* External Arbi. Request priority 2	*/
+#define SIUMCR_EARP3	0x30000000	/* External Arbi. Request priority 3	*/
+#define SIUMCR_EARP4	0x40000000	/* External Arbi. Request priority 4	*/
+#define SIUMCR_EARP5	0x50000000	/* External Arbi. Request priority 5	*/
+#define SIUMCR_EARP6	0x60000000	/* External Arbi. Request priority 6	*/
+#define SIUMCR_EARP7	0x70000000	/* External Arbi. Request priority 7	*/
+#define SIUMCR_DSHW	0x00800000	/* Data Showcycles			*/
+#define SIUMCR_DBGC00	0x00000000	/* Debug pins configuration		*/
+#define SIUMCR_DBGC01	0x00200000	/* - " -				*/
+#define SIUMCR_DBGC10	0x00400000	/* - " -				*/
+#define SIUMCR_DBGC11	0x00600000	/* - " -				*/
+#define SIUMCR_DBPC00	0x00000000	/* Debug Port pins Config.		*/
+#define SIUMCR_DBPC01	0x00080000	/* - " -				*/
+#define SIUMCR_DBPC10	0x00100000	/* - " -				*/
+#define SIUMCR_DBPC11	0x00180000	/* - " -				*/
+#define SIUMCR_GPC00	0x00000000	/* General Pins Config			*/
+#define SIUMCR_GPC01	0x00020000	/* General Pins Config			*/
+#define SIUMCR_GPC10	0x00040000	/* General Pins Config			*/
+#define SIUMCR_GPC11	0x00060000	/* General Pins Config			*/
+#define SIUMCR_DLK	0x00010000	/* Debug Register Lock			*/
+#define SIUMCR_SC00	0x00000000	/* Multi Chip 32 bit			*/
+#define SIUMCR_SC01	0x00004000	/* Muilt Chip 16 bit			*/
+#define SIUMCR_SC10	0x00004000	/* Single adress show			*/
+#define SIUMCR_SC11	0x00006000	/* Single adress			*/
+#define SIUMCR_RCTX	0x00001000	/* Data Parity pins Config.		*/
+#define SIUMCR_MLRC00	0x00000000	/* Multi Level Reserva. Ctrl		*/
+#define SIUMCR_MLRC01	0x00000400	/* - " -				*/
+#define SIUMCR_MLRC10	0x00000800	/* - " -				*/
+#define SIUMCR_MLRC11	0x00000c00	/* - " -				*/
+#define SIUMCR_MTSC	0x00000100	/* Memory transfer			*/
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control Register
+ */
+#define TBSCR_REFA	((ushort)0x0080)	/* Reference Interrupt Status A	*/
+#define TBSCR_REFB	((ushort)0x0040)	/* Reference Interrupt Status B */
+#define TBSCR_TBF	((ushort)0x0002)	/* Time Base stops while FREEZE */
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control Register
+ */
+#define PISCR_PITF	((ushort)0x0002)	/* PIT stops when FREEZE	*/
+#define PISCR_PS	0x0080			/* Periodic Interrupt Status	*/
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register
+ */
+#define PLPRCR_MF_MSK	0xfff00000	/* MF mask				*/
+#define PLPRCR_DIVF_MSK	0x0000001f	/* DIVF mask				*/
+#define PLPRCR_CSRC_MSK 0x00000400	/* CSRC mask				*/
+#define PLPRCR_MF_SHIFT 0x00000014	/* Multiplication factor shift value	*/
+#define PLPRCR_DIVF_0   0x00000000	/* Division factor 0			*/
+#define PLPRCR_MF_9     0x00900000	/* Mulitipliaction factor 9		*/
+#define PLPRCR_TEXPS	0x00004000	/* TEXP Status				*/
+#define PLPRCR_TMIST	0x00001000	/* Timers Interrupt Status		*/
+#define PLPRCR_CSR	0x00000080	/* CheskStop Reset value		*/
+#define PLPRCR_SPLSS	0x00008000	/* SPLL Lock Status Sticky bit		*/
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register
+ */
+#define SCCR_DFNL_MSK	0x00000070	/* DFNL mask				*/
+#define SCCR_DFNH_MSK	0x00000007	/* DFNH mask				*/
+#define SCCR_DFNL_SHIFT 0x0000004	/* DFNL shift value			*/
+#define SCCR_RTSEL	0x00100000	/* RTC circuit input source select	*/
+#define SCCR_EBDF00	0x00000000	/* Division factor 1. CLKOUT is GCLK2   */
+#define SCCR_EBDF11	0x00060000	/* reserved				*/
+#define SCCR_TBS	0x02000000	/* Time Base Source			*/
+#define SCCR_RTDIV	0x01000000	/* RTC Clock Divide			*/
+#define SCCR_COM00	0x00000000	/* full strength CLKOUT output buffer	*/
+#define SCCR_COM01	0x20000000	/* half strength CLKOUT output buffer	*/
+#define SCCR_DFNL000	0x00000000	/* Division by 2 (default = minimum)	*/
+#define SCCR_DFNH000	0x00000000	/* Division by 1 (default = minimum)	*/
+
+/*-----------------------------------------------------------------------
+ * MC - Memory Controller
+ */
+#define BR_V		0x00000001	/* Bank valid				*/
+#define BR_BI		0x00000002	/* Burst inhibit			*/
+#define BR_PS_8		0x00000400	/* 8 bit port size			*/
+#define BR_PS_16	0x00000800	/* 16 bit port size			*/
+#define BR_PS_32	0x00000000	/* 32 bit port size			*/
+#define BR_LBDIR	0x00000008	/* Late burst data in progess		*/
+#define BR_SETA		0x00000004	/* External Data Acknowledge		*/
+#define OR_SCY_3	0x00000030	/* 3 clock cycles wait states		*/
+#define OR_SCY_1	0x00000000	/* 1 clock cycle wait state		*/
+#define OR_SCY_8	0x00000080	/* 8 clock cycles wait states		*/
+#define OR_TRLX		0x00000001	/* Timing relaxed			*/
+#define OR_BSCY		0x00000060	/* Burst beats length in clocks		*/
+#define OR_ACS_10	0x00000600	/* Adress to chip-select setup		*/
+#define OR_CSNT		0x00000800	/* Chip-select negotation time		*/
+#define OR_ETHR		0x00000100	/* Extended hold time on read		*/
+#define OR_ADDR_MK_FF	0xFF000000
+#define OR_ADDR_MK_FFFF	0xFFFF0000
+
+/*-----------------------------------------------------------------------
+ * UMCR - UIMB Module Configuration Register
+ */
+#define UMCR_FSPEED	0x00000000	/* Full speed. Opposit of UMCR_HSPEED	*/
+#define UMCR_HSPEED	0x10000000	/* Half speed				*/
+
+/*-----------------------------------------------------------------------
+ * ICTRL - I-Bus Support Control Register
+ */
+#define ICTRL_ISCT_SER_7 0x00000007	/* All indirect change of flow		*/
+
+
+#define NR_IRQS		0		/* Place this later in a separate file */
+
+/*-----------------------------------------------------------------------
+ * SCI - Serial communication interface
+ */
+
+#define SCI_TDRE	0x0100		/* Transmit data register empty		*/
+#define SCI_TE		0x0008		/* Transmitter enabled			*/
+#define SCI_RE		0x0004		/* Receiver enabled			*/
+#define SCI_RDRF	0x0040		/* Receive data register full		*/
+#define SCI_PE		0x0400		/* Parity enable			*/
+#define SCI_SCXBR_MK	0x1fff		/* Baudrate mask			*/
+#define SCI_SCXDR_MK	0x00ff		/* Data register mask			*/
+#define SCI_M_11	0x0200		/* Frame size is 11 bit			*/
+#define SCI_M_10	0x0000		/* Frame size is 10 bit			*/
+#define SCI_PORT_1	((int)1)	/* Place this later somewhere better	*/
+#define SCI_PORT_2	((int)2)
+
+#endif	/* __MPC5XX_H__ */
diff --git a/qemu/roms/u-boot/include/mpc5xxx.h b/qemu/roms/u-boot/include/mpc5xxx.h
new file mode 100644
index 000000000..10daf0944
--- /dev/null
+++ b/qemu/roms/u-boot/include/mpc5xxx.h
@@ -0,0 +1,893 @@
+/*
+ * include/asm-ppc/mpc5xxx.h
+ *
+ * Prototypes, etc. for the Motorola MPC5xxx
+ * embedded cpu chips
+ *
+ * 2003 (c) MontaVista, Software, Inc.
+ * Author: Dale Farnsworth <dfarnsworth@mvista.com>
+ *
+ * 2003 (C) Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __ASMPPC_MPC5XXX_H
+#define __ASMPPC_MPC5XXX_H
+
+#include <asm/types.h>
+
+/* Processor name */
+#define CPU_ID_STR	"MPC5200"
+
+/* Exception offsets (PowerPC standard) */
+#define EXC_OFF_SYS_RESET	0x0100
+#define _START_OFFSET		EXC_OFF_SYS_RESET
+
+/* useful macros for manipulating CSx_START/STOP */
+#define START_REG(start)	((start) >> 16)
+#define STOP_REG(start, size)	(((start) + (size) - 1) >> 16)
+
+/* Internal memory map */
+
+#define MPC5XXX_CS0_START	(CONFIG_SYS_MBAR + 0x0004)
+#define MPC5XXX_CS0_STOP	(CONFIG_SYS_MBAR + 0x0008)
+#define MPC5XXX_CS1_START	(CONFIG_SYS_MBAR + 0x000c)
+#define MPC5XXX_CS1_STOP	(CONFIG_SYS_MBAR + 0x0010)
+#define MPC5XXX_CS2_START	(CONFIG_SYS_MBAR + 0x0014)
+#define MPC5XXX_CS2_STOP	(CONFIG_SYS_MBAR + 0x0018)
+#define MPC5XXX_CS3_START	(CONFIG_SYS_MBAR + 0x001c)
+#define MPC5XXX_CS3_STOP	(CONFIG_SYS_MBAR + 0x0020)
+#define MPC5XXX_CS4_START	(CONFIG_SYS_MBAR + 0x0024)
+#define MPC5XXX_CS4_STOP	(CONFIG_SYS_MBAR + 0x0028)
+#define MPC5XXX_CS5_START	(CONFIG_SYS_MBAR + 0x002c)
+#define MPC5XXX_CS5_STOP	(CONFIG_SYS_MBAR + 0x0030)
+#define MPC5XXX_BOOTCS_START	(CONFIG_SYS_MBAR + 0x004c)
+#define MPC5XXX_BOOTCS_STOP	(CONFIG_SYS_MBAR + 0x0050)
+#define MPC5XXX_ADDECR		(CONFIG_SYS_MBAR + 0x0054)
+
+#define MPC5XXX_CS6_START	(CONFIG_SYS_MBAR + 0x0058)
+#define MPC5XXX_CS6_STOP	(CONFIG_SYS_MBAR + 0x005c)
+#define MPC5XXX_CS7_START	(CONFIG_SYS_MBAR + 0x0060)
+#define MPC5XXX_CS7_STOP	(CONFIG_SYS_MBAR + 0x0064)
+#define MPC5XXX_SDRAM_CS0CFG	(CONFIG_SYS_MBAR + 0x0034)
+#define MPC5XXX_SDRAM_CS1CFG	(CONFIG_SYS_MBAR + 0x0038)
+
+#define MPC5XXX_SDRAM		(CONFIG_SYS_MBAR + 0x0100)
+#define MPC5XXX_CDM		(CONFIG_SYS_MBAR + 0x0200)
+#define MPC5XXX_LPB		(CONFIG_SYS_MBAR + 0x0300)
+#define MPC5XXX_ICTL		(CONFIG_SYS_MBAR + 0x0500)
+#define MPC5XXX_GPT		(CONFIG_SYS_MBAR + 0x0600)
+#define MPC5XXX_GPIO		(CONFIG_SYS_MBAR + 0x0b00)
+#define MPC5XXX_WU_GPIO         (CONFIG_SYS_MBAR + 0x0c00)
+#define MPC5XXX_PCI		(CONFIG_SYS_MBAR + 0x0d00)
+#define MPC5XXX_SPI		(CONFIG_SYS_MBAR + 0x0f00)
+#define MPC5XXX_USB		(CONFIG_SYS_MBAR + 0x1000)
+#define MPC5XXX_SDMA		(CONFIG_SYS_MBAR + 0x1200)
+#define MPC5XXX_XLBARB		(CONFIG_SYS_MBAR + 0x1f00)
+
+#define	MPC5XXX_PSC1		(CONFIG_SYS_MBAR + 0x2000)
+#define	MPC5XXX_PSC2		(CONFIG_SYS_MBAR + 0x2200)
+#define	MPC5XXX_PSC3		(CONFIG_SYS_MBAR + 0x2400)
+#define	MPC5XXX_PSC4		(CONFIG_SYS_MBAR + 0x2600)
+#define	MPC5XXX_PSC5		(CONFIG_SYS_MBAR + 0x2800)
+#define	MPC5XXX_PSC6		(CONFIG_SYS_MBAR + 0x2c00)
+
+#define	MPC5XXX_FEC		(CONFIG_SYS_MBAR + 0x3000)
+#define MPC5XXX_ATA             (CONFIG_SYS_MBAR + 0x3A00)
+
+#define MPC5XXX_I2C1		(CONFIG_SYS_MBAR + 0x3D00)
+#define MPC5XXX_I2C2		(CONFIG_SYS_MBAR + 0x3D40)
+
+#define MPC5XXX_SRAM		(CONFIG_SYS_MBAR + 0x8000)
+#define MPC5XXX_SRAM_SIZE	(16*1024)
+
+/* SDRAM Controller */
+#define MPC5XXX_SDRAM_MODE	(MPC5XXX_SDRAM + 0x0000)
+#define MPC5XXX_SDRAM_CTRL	(MPC5XXX_SDRAM + 0x0004)
+#define MPC5XXX_SDRAM_CONFIG1	(MPC5XXX_SDRAM + 0x0008)
+#define MPC5XXX_SDRAM_CONFIG2	(MPC5XXX_SDRAM + 0x000c)
+#define MPC5XXX_SDRAM_SDELAY	(MPC5XXX_SDRAM + 0x0090)
+
+/* Clock Distribution Module */
+#define MPC5XXX_CDM_JTAGID	(MPC5XXX_CDM + 0x0000)
+#define MPC5XXX_CDM_PORCFG	(MPC5XXX_CDM + 0x0004)
+#define MPC5XXX_CDM_BRDCRMB  	(MPC5XXX_CDM + 0x0008)
+#define MPC5XXX_CDM_CFG		(MPC5XXX_CDM + 0x000c)
+#define MPC5XXX_CDM_48_FDC	(MPC5XXX_CDM + 0x0010)
+#define MPC5XXX_CDM_CLK_ENA	(MPC5XXX_CDM + 0x0014)
+#define MPC5XXX_CDM_SRESET	(MPC5XXX_CDM + 0x0020)
+
+/* Local Plus Bus interface */
+#define MPC5XXX_CS0_CFG		(MPC5XXX_LPB + 0x0000)
+#define MPC5XXX_CS1_CFG		(MPC5XXX_LPB + 0x0004)
+#define MPC5XXX_CS2_CFG		(MPC5XXX_LPB + 0x0008)
+#define MPC5XXX_CS3_CFG		(MPC5XXX_LPB + 0x000c)
+#define MPC5XXX_CS4_CFG		(MPC5XXX_LPB + 0x0010)
+#define MPC5XXX_CS5_CFG		(MPC5XXX_LPB + 0x0014)
+#define MPC5XXX_BOOTCS_CFG	MPC5XXX_CS0_CFG
+#define MPC5XXX_CS_CTRL		(MPC5XXX_LPB + 0x0018)
+#define MPC5XXX_CS_STATUS	(MPC5XXX_LPB + 0x001c)
+#define MPC5XXX_CS6_CFG		(MPC5XXX_LPB + 0x0020)
+#define MPC5XXX_CS7_CFG		(MPC5XXX_LPB + 0x0024)
+#define MPC5XXX_CS_BURST	(MPC5XXX_LPB + 0x0028)
+#define MPC5XXX_CS_DEADCYCLE	(MPC5XXX_LPB + 0x002c)
+
+/* XLB Arbiter registers */
+#define MPC5XXX_XLBARB_CFG		(MPC5XXX_XLBARB + 0x40)
+#define MPC5XXX_XLBARB_MPRIEN	(MPC5XXX_XLBARB + 0x64)
+#define MPC5XXX_XLBARB_MPRIVAL	(MPC5XXX_XLBARB + 0x68)
+
+/* GPIO registers */
+#define MPC5XXX_GPS_PORT_CONFIG	(MPC5XXX_GPIO + 0x0000)
+
+/* Standard GPIO registers (simple, output only and simple interrupt */
+#define MPC5XXX_GPIO_ENABLE     (MPC5XXX_GPIO + 0x0004)
+#define MPC5XXX_GPIO_ODE        (MPC5XXX_GPIO + 0x0008)
+#define MPC5XXX_GPIO_DIR        (MPC5XXX_GPIO + 0x000c)
+#define MPC5XXX_GPIO_DATA_O     (MPC5XXX_GPIO + 0x0010)
+#define MPC5XXX_GPIO_DATA_I     (MPC5XXX_GPIO + 0x0014)
+#define MPC5XXX_GPIO_OO_ENABLE  (MPC5XXX_GPIO + 0x0018)
+#define MPC5XXX_GPIO_OO_DATA    (MPC5XXX_GPIO + 0x001C)
+#define MPC5XXX_GPIO_SI_ENABLE  (MPC5XXX_GPIO + 0x0020)
+#define MPC5XXX_GPIO_SI_ODE     (MPC5XXX_GPIO + 0x0024)
+#define MPC5XXX_GPIO_SI_DIR     (MPC5XXX_GPIO + 0x0028)
+#define MPC5XXX_GPIO_SI_DATA    (MPC5XXX_GPIO + 0x002C)
+#define MPC5XXX_GPIO_SI_IEN     (MPC5XXX_GPIO + 0x0030)
+#define MPC5XXX_GPIO_SI_ITYPE   (MPC5XXX_GPIO + 0x0034)
+#define MPC5XXX_GPIO_SI_MEN     (MPC5XXX_GPIO + 0x0038)
+#define MPC5XXX_GPIO_SI_STATUS  (MPC5XXX_GPIO + 0x003C)
+
+/* WakeUp GPIO registers */
+#define MPC5XXX_WU_GPIO_ENABLE  (MPC5XXX_WU_GPIO + 0x0000)
+#define MPC5XXX_WU_GPIO_ODE     (MPC5XXX_WU_GPIO + 0x0004)
+#define MPC5XXX_WU_GPIO_DIR     (MPC5XXX_WU_GPIO + 0x0008)
+#define MPC5XXX_WU_GPIO_DATA_O  (MPC5XXX_WU_GPIO + 0x000c)
+#define MPC5XXX_WU_GPIO_DATA_I  (MPC5XXX_WU_GPIO + 0x0020)
+
+/* GPIO pins, for Rev.B chip */
+#define GPIO_WKUP_7		0x80000000UL
+#define GPIO_PSC6_0		0x10000000UL
+#define GPIO_PSC3_9		0x04000000UL
+#define GPIO_PSC1_4		0x01000000UL
+#define GPIO_PSC2_4		0x02000000UL
+
+#define MPC5XXX_GPIO_SIMPLE_PSC6_3   0x20000000UL
+#define MPC5XXX_GPIO_SIMPLE_PSC6_2   0x10000000UL
+#define MPC5XXX_GPIO_SIMPLE_PSC3_7   0x00002000UL
+#define MPC5XXX_GPIO_SIMPLE_PSC3_6   0x00001000UL
+#define MPC5XXX_GPIO_SIMPLE_PSC3_3   0x00000800UL
+#define MPC5XXX_GPIO_SIMPLE_PSC3_2   0x00000400UL
+#define MPC5XXX_GPIO_SIMPLE_PSC3_1   0x00000200UL
+#define MPC5XXX_GPIO_SIMPLE_PSC3_0   0x00000100UL
+#define MPC5XXX_GPIO_SIMPLE_PSC2_3   0x00000080UL
+#define MPC5XXX_GPIO_SIMPLE_PSC2_2   0x00000040UL
+#define MPC5XXX_GPIO_SIMPLE_PSC2_1   0x00000020UL
+#define MPC5XXX_GPIO_SIMPLE_PSC2_0   0x00000010UL
+#define MPC5XXX_GPIO_SIMPLE_PSC1_3   0x00000008UL
+#define MPC5XXX_GPIO_SIMPLE_PSC1_2   0x00000004UL
+#define MPC5XXX_GPIO_SIMPLE_PSC1_1   0x00000002UL
+#define MPC5XXX_GPIO_SIMPLE_PSC1_0   0x00000001UL
+
+#define MPC5XXX_GPIO_SINT_ETH_16     0x80
+#define MPC5XXX_GPIO_SINT_ETH_15     0x40
+#define MPC5XXX_GPIO_SINT_ETH_14     0x20
+#define MPC5XXX_GPIO_SINT_ETH_13     0x10
+#define MPC5XXX_GPIO_SINT_USB1_9     0x08
+#define MPC5XXX_GPIO_SINT_PSC3_8     0x04
+#define MPC5XXX_GPIO_SINT_PSC3_5     0x02
+#define MPC5XXX_GPIO_SINT_PSC3_4     0x01
+
+#define MPC5XXX_GPIO_WKUP_7          0x80
+#define MPC5XXX_GPIO_WKUP_6          0x40
+#define MPC5XXX_GPIO_WKUP_PSC6_1     0x20
+#define MPC5XXX_GPIO_WKUP_PSC6_0     0x10
+#define MPC5XXX_GPIO_WKUP_ETH17      0x08
+#define MPC5XXX_GPIO_WKUP_PSC3_9     0x04
+#define MPC5XXX_GPIO_WKUP_PSC2_4     0x02
+#define MPC5XXX_GPIO_WKUP_PSC1_4     0x01
+
+/* PCI registers */
+#define MPC5XXX_PCI_CMD		(MPC5XXX_PCI + 0x04)
+#define MPC5XXX_PCI_CFG		(MPC5XXX_PCI + 0x0c)
+#define MPC5XXX_PCI_BAR0	(MPC5XXX_PCI + 0x10)
+#define MPC5XXX_PCI_BAR1	(MPC5XXX_PCI + 0x14)
+#define MPC5XXX_PCI_GSCR	(MPC5XXX_PCI + 0x60)
+#define MPC5XXX_PCI_TBATR0	(MPC5XXX_PCI + 0x64)
+#define MPC5XXX_PCI_TBATR1	(MPC5XXX_PCI + 0x68)
+#define MPC5XXX_PCI_TCR		(MPC5XXX_PCI + 0x6c)
+#define MPC5XXX_PCI_IW0BTAR	(MPC5XXX_PCI + 0x70)
+#define MPC5XXX_PCI_IW1BTAR	(MPC5XXX_PCI + 0x74)
+#define MPC5XXX_PCI_IW2BTAR	(MPC5XXX_PCI + 0x78)
+#define MPC5XXX_PCI_IWCR	(MPC5XXX_PCI + 0x80)
+#define MPC5XXX_PCI_ICR		(MPC5XXX_PCI + 0x84)
+#define MPC5XXX_PCI_ISR		(MPC5XXX_PCI + 0x88)
+#define MPC5XXX_PCI_ARB		(MPC5XXX_PCI + 0x8c)
+#define MPC5XXX_PCI_CAR		(MPC5XXX_PCI + 0xf8)
+
+/* Interrupt Controller registers */
+#define MPC5XXX_ICTL_PER_MASK	(MPC5XXX_ICTL + 0x0000)
+#define MPC5XXX_ICTL_PER_PRIO1	(MPC5XXX_ICTL + 0x0004)
+#define MPC5XXX_ICTL_PER_PRIO2	(MPC5XXX_ICTL + 0x0008)
+#define MPC5XXX_ICTL_PER_PRIO3	(MPC5XXX_ICTL + 0x000c)
+#define MPC5XXX_ICTL_EXT	(MPC5XXX_ICTL + 0x0010)
+#define MPC5XXX_ICTL_CRIT	(MPC5XXX_ICTL + 0x0014)
+#define MPC5XXX_ICTL_MAIN_PRIO1	(MPC5XXX_ICTL + 0x0018)
+#define MPC5XXX_ICTL_MAIN_PRIO2	(MPC5XXX_ICTL + 0x001c)
+#define MPC5XXX_ICTL_STS	(MPC5XXX_ICTL + 0x0024)
+#define MPC5XXX_ICTL_CRIT_STS	(MPC5XXX_ICTL + 0x0028)
+#define MPC5XXX_ICTL_MAIN_STS	(MPC5XXX_ICTL + 0x002c)
+#define MPC5XXX_ICTL_PER_STS	(MPC5XXX_ICTL + 0x0030)
+#define MPC5XXX_ICTL_BUS_STS	(MPC5XXX_ICTL + 0x0038)
+
+#define NR_IRQS			64
+
+/* IRQ mapping - these are our logical IRQ numbers */
+#define MPC5XXX_CRIT_IRQ_NUM	4
+#define MPC5XXX_MAIN_IRQ_NUM	17
+#define MPC5XXX_SDMA_IRQ_NUM	17
+#define MPC5XXX_PERP_IRQ_NUM	23
+
+#define MPC5XXX_CRIT_IRQ_BASE	1
+#define MPC5XXX_MAIN_IRQ_BASE	(MPC5XXX_CRIT_IRQ_BASE + MPC5XXX_CRIT_IRQ_NUM)
+#define MPC5XXX_SDMA_IRQ_BASE	(MPC5XXX_MAIN_IRQ_BASE + MPC5XXX_MAIN_IRQ_NUM)
+#define MPC5XXX_PERP_IRQ_BASE	(MPC5XXX_SDMA_IRQ_BASE + MPC5XXX_SDMA_IRQ_NUM)
+
+#define MPC5XXX_IRQ0			(MPC5XXX_CRIT_IRQ_BASE + 0)
+#define MPC5XXX_SLICE_TIMER_0_IRQ	(MPC5XXX_CRIT_IRQ_BASE + 1)
+#define MPC5XXX_HI_INT_IRQ		(MPC5XXX_CRIT_IRQ_BASE + 2)
+#define MPC5XXX_CCS_IRQ			(MPC5XXX_CRIT_IRQ_BASE + 3)
+
+#define MPC5XXX_IRQ1			(MPC5XXX_MAIN_IRQ_BASE + 1)
+#define MPC5XXX_IRQ2			(MPC5XXX_MAIN_IRQ_BASE + 2)
+#define MPC5XXX_IRQ3			(MPC5XXX_MAIN_IRQ_BASE + 3)
+#define MPC5XXX_RTC_PINT_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 5)
+#define MPC5XXX_RTC_SINT_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 6)
+#define MPC5XXX_RTC_GPIO_STD_IRQ	(MPC5XXX_MAIN_IRQ_BASE + 7)
+#define MPC5XXX_RTC_GPIO_WKUP_IRQ	(MPC5XXX_MAIN_IRQ_BASE + 8)
+#define MPC5XXX_TMR0_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 9)
+#define MPC5XXX_TMR1_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 10)
+#define MPC5XXX_TMR2_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 11)
+#define MPC5XXX_TMR3_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 12)
+#define MPC5XXX_TMR4_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 13)
+#define MPC5XXX_TMR5_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 14)
+#define MPC5XXX_TMR6_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 15)
+#define MPC5XXX_TMR7_IRQ		(MPC5XXX_MAIN_IRQ_BASE + 16)
+
+#define MPC5XXX_SDMA_IRQ		(MPC5XXX_PERP_IRQ_BASE + 0)
+#define MPC5XXX_PSC1_IRQ		(MPC5XXX_PERP_IRQ_BASE + 1)
+#define MPC5XXX_PSC2_IRQ		(MPC5XXX_PERP_IRQ_BASE + 2)
+#define MPC5XXX_PSC3_IRQ		(MPC5XXX_PERP_IRQ_BASE + 3)
+#define MPC5XXX_PSC6_IRQ		(MPC5XXX_PERP_IRQ_BASE + 4)
+#define MPC5XXX_IRDA_IRQ		(MPC5XXX_PERP_IRQ_BASE + 4)
+#define MPC5XXX_FEC_IRQ			(MPC5XXX_PERP_IRQ_BASE + 5)
+#define MPC5XXX_USB_IRQ			(MPC5XXX_PERP_IRQ_BASE + 6)
+#define MPC5XXX_ATA_IRQ			(MPC5XXX_PERP_IRQ_BASE + 7)
+#define MPC5XXX_PCI_CNTRL_IRQ		(MPC5XXX_PERP_IRQ_BASE + 8)
+#define MPC5XXX_PCI_SCIRX_IRQ		(MPC5XXX_PERP_IRQ_BASE + 9)
+#define MPC5XXX_PCI_SCITX_IRQ		(MPC5XXX_PERP_IRQ_BASE + 10)
+#define MPC5XXX_PSC4_IRQ		(MPC5XXX_PERP_IRQ_BASE + 11)
+#define MPC5XXX_PSC5_IRQ		(MPC5XXX_PERP_IRQ_BASE + 12)
+#define MPC5XXX_SPI_MODF_IRQ		(MPC5XXX_PERP_IRQ_BASE + 13)
+#define MPC5XXX_SPI_SPIF_IRQ		(MPC5XXX_PERP_IRQ_BASE + 14)
+#define MPC5XXX_I2C1_IRQ		(MPC5XXX_PERP_IRQ_BASE + 15)
+#define MPC5XXX_I2C2_IRQ		(MPC5XXX_PERP_IRQ_BASE + 16)
+#define MPC5XXX_MSCAN1_IRQ		(MPC5XXX_PERP_IRQ_BASE + 17)
+#define MPC5XXX_MSCAN2_IRQ		(MPC5XXX_PERP_IRQ_BASE + 18)
+#define MPC5XXX_IR_RX_IRQ		(MPC5XXX_PERP_IRQ_BASE + 19)
+#define MPC5XXX_IR_TX_IRQ		(MPC5XXX_PERP_IRQ_BASE + 20)
+#define MPC5XXX_XLB_ARB_IRQ		(MPC5XXX_PERP_IRQ_BASE + 21)
+#define MPC5XXX_BDLC_IRQ		(MPC5XXX_PERP_IRQ_BASE + 22)
+
+/* General Purpose Timers registers */
+#define MPC5XXX_GPT0_ENABLE		(MPC5XXX_GPT + 0x0)
+#define MPC5XXX_GPT0_COUNTER		(MPC5XXX_GPT + 0x4)
+#define MPC5XXX_GPT0_STATUS		(MPC5XXX_GPT + 0x0C)
+#define MPC5XXX_GPT1_ENABLE		(MPC5XXX_GPT + 0x10)
+#define MPC5XXX_GPT1_COUNTER		(MPC5XXX_GPT + 0x14)
+#define MPC5XXX_GPT1_STATUS		(MPC5XXX_GPT + 0x1C)
+#define MPC5XXX_GPT2_ENABLE		(MPC5XXX_GPT + 0x20)
+#define MPC5XXX_GPT2_COUNTER		(MPC5XXX_GPT + 0x24)
+#define MPC5XXX_GPT2_STATUS		(MPC5XXX_GPT + 0x2C)
+#define MPC5XXX_GPT3_ENABLE		(MPC5XXX_GPT + 0x30)
+#define MPC5XXX_GPT3_COUNTER		(MPC5XXX_GPT + 0x34)
+#define MPC5XXX_GPT3_STATUS		(MPC5XXX_GPT + 0x3C)
+#define MPC5XXX_GPT4_ENABLE		(MPC5XXX_GPT + 0x40)
+#define MPC5XXX_GPT4_COUNTER		(MPC5XXX_GPT + 0x44)
+#define MPC5XXX_GPT4_STATUS		(MPC5XXX_GPT + 0x4C)
+#define MPC5XXX_GPT5_ENABLE		(MPC5XXX_GPT + 0x50)
+#define MPC5XXX_GPT5_STATUS		(MPC5XXX_GPT + 0x5C)
+#define MPC5XXX_GPT5_COUNTER		(MPC5XXX_GPT + 0x54)
+#define MPC5XXX_GPT6_ENABLE		(MPC5XXX_GPT + 0x60)
+#define MPC5XXX_GPT6_COUNTER		(MPC5XXX_GPT + 0x64)
+#define MPC5XXX_GPT6_STATUS		(MPC5XXX_GPT + 0x6C)
+#define MPC5XXX_GPT7_ENABLE		(MPC5XXX_GPT + 0x70)
+#define MPC5XXX_GPT7_COUNTER		(MPC5XXX_GPT + 0x74)
+#define MPC5XXX_GPT7_STATUS		(MPC5XXX_GPT + 0x7C)
+
+#define MPC5XXX_GPT_GPIO_PIN(status)	((0x00000100 & (status)) >> 8)
+
+#define MPC5XXX_GPT7_PWMCFG		(MPC5XXX_GPT + 0x78)
+
+/* ATA registers */
+#define MPC5XXX_ATA_HOST_CONFIG         (MPC5XXX_ATA + 0x0000)
+#define MPC5XXX_ATA_PIO1                (MPC5XXX_ATA + 0x0008)
+#define MPC5XXX_ATA_PIO2                (MPC5XXX_ATA + 0x000C)
+#define MPC5XXX_ATA_SHARE_COUNT         (MPC5XXX_ATA + 0x002C)
+
+/* I2Cn control register bits */
+#define I2C_EN		0x80
+#define I2C_IEN		0x40
+#define I2C_STA		0x20
+#define I2C_TX		0x10
+#define I2C_TXAK	0x08
+#define I2C_RSTA	0x04
+#define I2C_INIT_MASK	(I2C_EN | I2C_STA | I2C_TX | I2C_RSTA)
+
+/* I2Cn status register bits */
+#define I2C_CF		0x80
+#define I2C_AAS		0x40
+#define I2C_BB		0x20
+#define I2C_AL		0x10
+#define I2C_SRW		0x04
+#define I2C_IF		0x02
+#define I2C_RXAK	0x01
+
+/* SPI control register 1 bits */
+#define SPI_CR_LSBFE	0x01
+#define SPI_CR_SSOE	0x02
+#define SPI_CR_CPHA	0x04
+#define SPI_CR_CPOL	0x08
+#define SPI_CR_MSTR	0x10
+#define SPI_CR_SWOM	0x20
+#define SPI_CR_SPE	0x40
+#define SPI_CR_SPIE	0x80
+
+/* SPI status register bits */
+#define SPI_SR_MODF	0x10
+#define SPI_SR_WCOL	0x40
+#define SPI_SR_SPIF	0x80
+
+/* SPI port data register bits */
+#define SPI_PDR_SS	0x08
+
+/* Programmable Serial Controller (PSC) status register bits */
+#define PSC_SR_CDE		0x0080
+#define PSC_SR_RXRDY		0x0100
+#define PSC_SR_RXFULL		0x0200
+#define PSC_SR_TXRDY		0x0400
+#define PSC_SR_TXEMP		0x0800
+#define PSC_SR_OE		0x1000
+#define PSC_SR_PE		0x2000
+#define PSC_SR_FE		0x4000
+#define PSC_SR_RB		0x8000
+
+/* PSC Command values */
+#define PSC_RX_ENABLE		0x0001
+#define PSC_RX_DISABLE		0x0002
+#define PSC_TX_ENABLE		0x0004
+#define PSC_TX_DISABLE		0x0008
+#define PSC_SEL_MODE_REG_1	0x0010
+#define PSC_RST_RX		0x0020
+#define PSC_RST_TX		0x0030
+#define PSC_RST_ERR_STAT	0x0040
+#define PSC_RST_BRK_CHG_INT	0x0050
+#define PSC_START_BRK		0x0060
+#define PSC_STOP_BRK		0x0070
+
+/* PSC Rx FIFO status bits */
+#define PSC_RX_FIFO_ERR		0x0040
+#define PSC_RX_FIFO_UF		0x0020
+#define PSC_RX_FIFO_OF		0x0010
+#define PSC_RX_FIFO_FR		0x0008
+#define PSC_RX_FIFO_FULL	0x0004
+#define PSC_RX_FIFO_ALARM	0x0002
+#define PSC_RX_FIFO_EMPTY	0x0001
+
+/* PSC interrupt mask bits */
+#define PSC_IMR_TXRDY		0x0100
+#define PSC_IMR_RXRDY		0x0200
+#define PSC_IMR_DB		0x0400
+#define PSC_IMR_IPC		0x8000
+
+/* PSC input port change bits */
+#define PSC_IPCR_CTS		0x01
+#define PSC_IPCR_DCD		0x02
+
+/* PSC mode fields */
+#define PSC_MODE_5_BITS		0x00
+#define PSC_MODE_6_BITS		0x01
+#define PSC_MODE_7_BITS		0x02
+#define PSC_MODE_8_BITS		0x03
+#define PSC_MODE_PAREVEN	0x00
+#define PSC_MODE_PARODD		0x04
+#define PSC_MODE_PARFORCE	0x08
+#define PSC_MODE_PARNONE	0x10
+#define PSC_MODE_ERR		0x20
+#define PSC_MODE_FFULL		0x40
+#define PSC_MODE_RXRTS		0x80
+
+#define PSC_MODE_ONE_STOP_5_BITS	0x00
+#define PSC_MODE_ONE_STOP		0x07
+#define PSC_MODE_TWO_STOP		0x0f
+
+/* ATA config fields */
+#define MPC5xxx_ATA_HOSTCONF_SMR	0x80000000UL	/* State machine
+							   reset */
+#define MPC5xxx_ATA_HOSTCONF_FR		0x40000000UL	/* FIFO Reset */
+#define MPC5xxx_ATA_HOSTCONF_IE		0x02000000UL	/* Enable interrupt
+							   in PIO */
+#define MPC5xxx_ATA_HOSTCONF_IORDY	0x01000000UL	/* Drive supports
+							   IORDY protocol */
+
+#ifndef __ASSEMBLY__
+/* Memory map registers */
+struct mpc5xxx_mmap_ctl {
+	volatile u32	mbar;
+	volatile u32	cs0_start;	/* 0x0004 */
+	volatile u32	cs0_stop;
+	volatile u32	cs1_start;	/* 0x000c */
+	volatile u32	cs1_stop;
+	volatile u32	cs2_start;	/* 0x0014 */
+	volatile u32	cs2_stop;
+	volatile u32	cs3_start;	/* 0x001c */
+	volatile u32	cs3_stop;
+	volatile u32	cs4_start;	/* 0x0024 */
+	volatile u32	cs4_stop;
+	volatile u32	cs5_start;	/* 0x002c */
+	volatile u32	cs5_stop;
+	volatile u32	sdram0;		/* 0x0034 */
+	volatile u32	sdram1;		/* 0x0038 */
+	volatile u32	dummy1[4];	/* 0x003c */
+	volatile u32	boot_start;	/* 0x004c */
+	volatile u32	boot_stop;
+	volatile u32	ipbi_ws_ctrl;	/* 0x0054 */
+	volatile u32	cs6_start;	/* 0x0058 */
+	volatile u32	cs6_stop;
+	volatile u32	cs7_start;	/* 0x0060 */
+	volatile u32	cs7_stop;
+};
+
+/* Clock distribution module */
+struct mpc5xxx_cdm {
+	volatile u32	jtagid;		/* 0x0000 */
+	volatile u32	porcfg;
+	volatile u32	brdcrmb;	/* 0x0008 */
+	volatile u32	cfg;
+	volatile u32	fourtyeight_fdc;/* 0x0010 */
+	volatile u32	clock_enable;
+	volatile u32	system_osc;	/* 0x0018 */
+	volatile u32	ccscr;
+	volatile u32	sreset;		/* 0x0020 */
+	volatile u32	pll_status;
+	volatile u32	psc1_mccr;	/* 0x0028 */
+	volatile u32	psc2_mccr;
+	volatile u32	psc3_mccr;	/* 0x0030 */
+	volatile u32	psc6_mccr;
+};
+
+/* SDRAM controller */
+struct mpc5xxx_sdram {
+	volatile u32	mode;
+	volatile u32	ctrl;
+	volatile u32	config1;
+	volatile u32	config2;
+	volatile u32	dummy[32];
+	volatile u32	sdelay;
+};
+
+struct mpc5xxx_lpb {
+	volatile u32	cs0_cfg;
+	volatile u32	cs1_cfg;
+	volatile u32	cs2_cfg;
+	volatile u32	cs3_cfg;
+	volatile u32	cs4_cfg;
+	volatile u32	cs5_cfg;
+	volatile u32	cs_ctrl;
+	volatile u32	cs_status;
+	volatile u32	cs6_cfg;
+	volatile u32	cs7_cfg;
+	volatile u32	cs_burst;
+	volatile u32	cs_deadcycle;
+};
+
+
+struct mpc5xxx_psc {
+	volatile u8	mode;		/* PSC + 0x00 */
+	volatile u8	reserved0[3];
+	union {				/* PSC + 0x04 */
+		volatile u16	status;
+		volatile u16	clock_select;
+	} sr_csr;
+#define psc_status	sr_csr.status
+#define psc_clock_select sr_csr.clock_select
+	volatile u16	reserved1;
+	volatile u8	command;	/* PSC + 0x08 */
+	volatile u8	reserved2[3];
+	union {				/* PSC + 0x0c */
+		volatile u8	buffer_8;
+		volatile u16	buffer_16;
+		volatile u32	buffer_32;
+	} buffer;
+#define psc_buffer_8	buffer.buffer_8
+#define psc_buffer_16	buffer.buffer_16
+#define psc_buffer_32	buffer.buffer_32
+	union {				/* PSC + 0x10 */
+		volatile u8	ipcr;
+		volatile u8	acr;
+	} ipcr_acr;
+#define psc_ipcr	ipcr_acr.ipcr
+#define psc_acr		ipcr_acr.acr
+	volatile u8	reserved3[3];
+	union {				/* PSC + 0x14 */
+		volatile u16	isr;
+		volatile u16	imr;
+	} isr_imr;
+#define psc_isr		isr_imr.isr
+#define psc_imr		isr_imr.imr
+	volatile u16	reserved4;
+	volatile u8	ctur;		/* PSC + 0x18 */
+	volatile u8	reserved5[3];
+	volatile u8	ctlr;		/* PSC + 0x1c */
+	volatile u8	reserved6[3];
+	volatile u16	ccr;		/* PSC + 0x20 */
+	volatile u8	reserved7[14];
+	volatile u8	ivr;		/* PSC + 0x30 */
+	volatile u8	reserved8[3];
+	volatile u8	ip;		/* PSC + 0x34 */
+	volatile u8	reserved9[3];
+	volatile u8	op1;		/* PSC + 0x38 */
+	volatile u8	reserved10[3];
+	volatile u8	op0;		/* PSC + 0x3c */
+	volatile u8	reserved11[3];
+	volatile u32	sicr;		/* PSC + 0x40 */
+	volatile u8	ircr1;		/* PSC + 0x44 */
+	volatile u8	reserved12[3];
+	volatile u8	ircr2;		/* PSC + 0x44 */
+	volatile u8	reserved13[3];
+	volatile u8	irsdr;		/* PSC + 0x4c */
+	volatile u8	reserved14[3];
+	volatile u8	irmdr;		/* PSC + 0x50 */
+	volatile u8	reserved15[3];
+	volatile u8	irfdr;		/* PSC + 0x54 */
+	volatile u8	reserved16[3];
+	volatile u16	rfnum;		/* PSC + 0x58 */
+	volatile u16	reserved17;
+	volatile u16	tfnum;		/* PSC + 0x5c */
+	volatile u16	reserved18;
+	volatile u32	rfdata;		/* PSC + 0x60 */
+	volatile u16	rfstat;		/* PSC + 0x64 */
+	volatile u16	reserved20;
+	volatile u8	rfcntl;		/* PSC + 0x68 */
+	volatile u8	reserved21[5];
+	volatile u16	rfalarm;	/* PSC + 0x6e */
+	volatile u16	reserved22;
+	volatile u16	rfrptr;		/* PSC + 0x72 */
+	volatile u16	reserved23;
+	volatile u16	rfwptr;		/* PSC + 0x76 */
+	volatile u16	reserved24;
+	volatile u16	rflrfptr;	/* PSC + 0x7a */
+	volatile u16	reserved25;
+	volatile u16	rflwfptr;	/* PSC + 0x7e */
+	volatile u32	tfdata;		/* PSC + 0x80 */
+	volatile u16	tfstat;		/* PSC + 0x84 */
+	volatile u16	reserved26;
+	volatile u8	tfcntl;		/* PSC + 0x88 */
+	volatile u8	reserved27[5];
+	volatile u16	tfalarm;	/* PSC + 0x8e */
+	volatile u16	reserved28;
+	volatile u16	tfrptr;		/* PSC + 0x92 */
+	volatile u16	reserved29;
+	volatile u16	tfwptr;		/* PSC + 0x96 */
+	volatile u16	reserved30;
+	volatile u16	tflrfptr;	/* PSC + 0x9a */
+	volatile u16	reserved31;
+	volatile u16	tflwfptr;	/* PSC + 0x9e */
+};
+
+struct mpc5xxx_intr {
+	volatile u32	per_mask;	/* INTR + 0x00 */
+	volatile u32	per_pri1;	/* INTR + 0x04 */
+	volatile u32	per_pri2;	/* INTR + 0x08 */
+	volatile u32	per_pri3;	/* INTR + 0x0c */
+	volatile u32	ctrl;		/* INTR + 0x10 */
+	volatile u32	main_mask;	/* INTR + 0x14 */
+	volatile u32	main_pri1;	/* INTR + 0x18 */
+	volatile u32	main_pri2;	/* INTR + 0x1c */
+	volatile u32	reserved1;	/* INTR + 0x20 */
+	volatile u32	enc_status;	/* INTR + 0x24 */
+	volatile u32	crit_status;	/* INTR + 0x28 */
+	volatile u32	main_status;	/* INTR + 0x2c */
+	volatile u32	per_status;	/* INTR + 0x30 */
+	volatile u32	reserved2;	/* INTR + 0x34 */
+	volatile u32	per_error;	/* INTR + 0x38 */
+};
+
+struct mpc5xxx_gpio {
+	volatile u32 port_config;	/* GPIO + 0x00 */
+	volatile u32 simple_gpioe;	/* GPIO + 0x04 */
+	volatile u32 simple_ode;	/* GPIO + 0x08 */
+	volatile u32 simple_ddr;	/* GPIO + 0x0c */
+	volatile u32 simple_dvo;	/* GPIO + 0x10 */
+	volatile u32 simple_ival;	/* GPIO + 0x14 */
+	volatile u8 outo_gpioe;		/* GPIO + 0x18 */
+	volatile u8 reserved1[3];	/* GPIO + 0x19 */
+	volatile u8 outo_dvo;		/* GPIO + 0x1c */
+	volatile u8 reserved2[3];	/* GPIO + 0x1d */
+	volatile u8 sint_gpioe;		/* GPIO + 0x20 */
+	volatile u8 reserved3[3];	/* GPIO + 0x21 */
+	volatile u8 sint_ode;		/* GPIO + 0x24 */
+	volatile u8 reserved4[3];	/* GPIO + 0x25 */
+	volatile u8 sint_ddr;		/* GPIO + 0x28 */
+	volatile u8 reserved5[3];	/* GPIO + 0x29 */
+	volatile u8 sint_dvo;		/* GPIO + 0x2c */
+	volatile u8 reserved6[3];	/* GPIO + 0x2d */
+	volatile u8 sint_inten;		/* GPIO + 0x30 */
+	volatile u8 reserved7[3];	/* GPIO + 0x31 */
+	volatile u16 sint_itype;	/* GPIO + 0x34 */
+	volatile u16 reserved8;		/* GPIO + 0x36 */
+	volatile u8 gpio_control;	/* GPIO + 0x38 */
+	volatile u8 reserved9[3];	/* GPIO + 0x39 */
+	volatile u8 sint_istat;		/* GPIO + 0x3c */
+	volatile u8 sint_ival;		/* GPIO + 0x3d */
+	volatile u8 bus_errs;		/* GPIO + 0x3e */
+	volatile u8 reserved10;		/* GPIO + 0x3f */
+};
+
+struct mpc5xxx_wu_gpio {
+	volatile u8 enable;		/* WU_GPIO + 0x00 */
+	volatile u8 reserved1[3];	/* WU_GPIO + 0x01 */
+	volatile u8 ode;		/* WU_GPIO + 0x04 */
+	volatile u8 reserved2[3];	/* WU_GPIO + 0x05 */
+	volatile u8 ddr;		/* WU_GPIO + 0x08 */
+	volatile u8 reserved3[3];	/* WU_GPIO + 0x09 */
+	volatile u8 dvo;		/* WU_GPIO + 0x0c */
+	volatile u8 reserved4[3];	/* WU_GPIO + 0x0d */
+	volatile u8 inten;		/* WU_GPIO + 0x10 */
+	volatile u8 reserved5[3];	/* WU_GPIO + 0x11 */
+	volatile u8 iinten;		/* WU_GPIO + 0x14 */
+	volatile u8 reserved6[3];	/* WU_GPIO + 0x15 */
+	volatile u16 itype;		/* WU_GPIO + 0x18 */
+	volatile u8 reserved7[2];	/* WU_GPIO + 0x1a */
+	volatile u8 master_enable;	/* WU_GPIO + 0x1c */
+	volatile u8 reserved8[3];	/* WU_GPIO + 0x1d */
+	volatile u8 ival;		/* WU_GPIO + 0x20 */
+	volatile u8 reserved9[3];	/* WU_GPIO + 0x21 */
+	volatile u8 status;		/* WU_GPIO + 0x24 */
+	volatile u8 reserved10[3];	/* WU_GPIO + 0x25 */
+};
+
+struct mpc5xxx_sdma {
+	volatile u32 taskBar;		/* SDMA + 0x00 */
+	volatile u32 currentPointer;	/* SDMA + 0x04 */
+	volatile u32 endPointer;	/* SDMA + 0x08 */
+	volatile u32 variablePointer;	/* SDMA + 0x0c */
+
+	volatile u8 IntVect1;		/* SDMA + 0x10 */
+	volatile u8 IntVect2;		/* SDMA + 0x11 */
+	volatile u16 PtdCntrl;		/* SDMA + 0x12 */
+
+	volatile u32 IntPend;		/* SDMA + 0x14 */
+	volatile u32 IntMask;		/* SDMA + 0x18 */
+
+	volatile u16 tcr_0;		/* SDMA + 0x1c */
+	volatile u16 tcr_1;		/* SDMA + 0x1e */
+	volatile u16 tcr_2;		/* SDMA + 0x20 */
+	volatile u16 tcr_3;		/* SDMA + 0x22 */
+	volatile u16 tcr_4;		/* SDMA + 0x24 */
+	volatile u16 tcr_5;		/* SDMA + 0x26 */
+	volatile u16 tcr_6;		/* SDMA + 0x28 */
+	volatile u16 tcr_7;		/* SDMA + 0x2a */
+	volatile u16 tcr_8;		/* SDMA + 0x2c */
+	volatile u16 tcr_9;		/* SDMA + 0x2e */
+	volatile u16 tcr_a;		/* SDMA + 0x30 */
+	volatile u16 tcr_b;		/* SDMA + 0x32 */
+	volatile u16 tcr_c;		/* SDMA + 0x34 */
+	volatile u16 tcr_d;		/* SDMA + 0x36 */
+	volatile u16 tcr_e;		/* SDMA + 0x38 */
+	volatile u16 tcr_f;		/* SDMA + 0x3a */
+
+	volatile u8 IPR0;		/* SDMA + 0x3c */
+	volatile u8 IPR1;		/* SDMA + 0x3d */
+	volatile u8 IPR2;		/* SDMA + 0x3e */
+	volatile u8 IPR3;		/* SDMA + 0x3f */
+	volatile u8 IPR4;		/* SDMA + 0x40 */
+	volatile u8 IPR5;		/* SDMA + 0x41 */
+	volatile u8 IPR6;		/* SDMA + 0x42 */
+	volatile u8 IPR7;		/* SDMA + 0x43 */
+	volatile u8 IPR8;		/* SDMA + 0x44 */
+	volatile u8 IPR9;		/* SDMA + 0x45 */
+	volatile u8 IPR10;		/* SDMA + 0x46 */
+	volatile u8 IPR11;		/* SDMA + 0x47 */
+	volatile u8 IPR12;		/* SDMA + 0x48 */
+	volatile u8 IPR13;		/* SDMA + 0x49 */
+	volatile u8 IPR14;		/* SDMA + 0x4a */
+	volatile u8 IPR15;		/* SDMA + 0x4b */
+	volatile u8 IPR16;		/* SDMA + 0x4c */
+	volatile u8 IPR17;		/* SDMA + 0x4d */
+	volatile u8 IPR18;		/* SDMA + 0x4e */
+	volatile u8 IPR19;		/* SDMA + 0x4f */
+	volatile u8 IPR20;		/* SDMA + 0x50 */
+	volatile u8 IPR21;		/* SDMA + 0x51 */
+	volatile u8 IPR22;		/* SDMA + 0x52 */
+	volatile u8 IPR23;		/* SDMA + 0x53 */
+	volatile u8 IPR24;		/* SDMA + 0x54 */
+	volatile u8 IPR25;		/* SDMA + 0x55 */
+	volatile u8 IPR26;		/* SDMA + 0x56 */
+	volatile u8 IPR27;		/* SDMA + 0x57 */
+	volatile u8 IPR28;		/* SDMA + 0x58 */
+	volatile u8 IPR29;		/* SDMA + 0x59 */
+	volatile u8 IPR30;		/* SDMA + 0x5a */
+	volatile u8 IPR31;		/* SDMA + 0x5b */
+
+	volatile u32 res1;		/* SDMA + 0x5c */
+	volatile u32 res2;		/* SDMA + 0x60 */
+	volatile u32 res3;		/* SDMA + 0x64 */
+	volatile u32 MDEDebug;		/* SDMA + 0x68 */
+	volatile u32 ADSDebug;		/* SDMA + 0x6c */
+	volatile u32 Value1;		/* SDMA + 0x70 */
+	volatile u32 Value2;		/* SDMA + 0x74 */
+	volatile u32 Control;		/* SDMA + 0x78 */
+	volatile u32 Status;		/* SDMA + 0x7c */
+	volatile u32 EU00;		/* SDMA + 0x80 */
+	volatile u32 EU01;		/* SDMA + 0x84 */
+	volatile u32 EU02;		/* SDMA + 0x88 */
+	volatile u32 EU03;		/* SDMA + 0x8c */
+	volatile u32 EU04;		/* SDMA + 0x90 */
+	volatile u32 EU05;		/* SDMA + 0x94 */
+	volatile u32 EU06;		/* SDMA + 0x98 */
+	volatile u32 EU07;		/* SDMA + 0x9c */
+	volatile u32 EU10;		/* SDMA + 0xa0 */
+	volatile u32 EU11;		/* SDMA + 0xa4 */
+	volatile u32 EU12;		/* SDMA + 0xa8 */
+	volatile u32 EU13;		/* SDMA + 0xac */
+	volatile u32 EU14;		/* SDMA + 0xb0 */
+	volatile u32 EU15;		/* SDMA + 0xb4 */
+	volatile u32 EU16;		/* SDMA + 0xb8 */
+	volatile u32 EU17;		/* SDMA + 0xbc */
+	volatile u32 EU20;		/* SDMA + 0xc0 */
+	volatile u32 EU21;		/* SDMA + 0xc4 */
+	volatile u32 EU22;		/* SDMA + 0xc8 */
+	volatile u32 EU23;		/* SDMA + 0xcc */
+	volatile u32 EU24;		/* SDMA + 0xd0 */
+	volatile u32 EU25;		/* SDMA + 0xd4 */
+	volatile u32 EU26;		/* SDMA + 0xd8 */
+	volatile u32 EU27;		/* SDMA + 0xdc */
+	volatile u32 EU30;		/* SDMA + 0xe0 */
+	volatile u32 EU31;		/* SDMA + 0xe4 */
+	volatile u32 EU32;		/* SDMA + 0xe8 */
+	volatile u32 EU33;		/* SDMA + 0xec */
+	volatile u32 EU34;		/* SDMA + 0xf0 */
+	volatile u32 EU35;		/* SDMA + 0xf4 */
+	volatile u32 EU36;		/* SDMA + 0xf8 */
+	volatile u32 EU37;		/* SDMA + 0xfc */
+};
+
+struct mpc5xxx_i2c {
+	volatile u32 madr;		/* I2Cn + 0x00 */
+	volatile u32 mfdr;		/* I2Cn + 0x04 */
+	volatile u32 mcr;		/* I2Cn + 0x08 */
+	volatile u32 msr;		/* I2Cn + 0x0C */
+	volatile u32 mdr;		/* I2Cn + 0x10 */
+};
+
+struct mpc5xxx_spi {
+	volatile u8 cr1;		/* SPI + 0x0F00 */
+	volatile u8 cr2;		/* SPI + 0x0F01 */
+	volatile u8 reserved1[2];
+	volatile u8 brr;		/* SPI + 0x0F04 */
+	volatile u8 sr;			/* SPI + 0x0F05 */
+	volatile u8 reserved2[3];
+	volatile u8 dr;			/* SPI + 0x0F09 */
+	volatile u8 reserved3[3];
+	volatile u8 pdr;		/* SPI + 0x0F0D */
+	volatile u8 reserved4[2];
+	volatile u8 ddr;		/* SPI + 0x0F10 */
+};
+
+
+struct mpc5xxx_gpt {
+	volatile u32 emsr;		/* GPT + Timer# * 0x10 + 0x00 */
+	volatile u32 cir;		/* GPT + Timer# * 0x10 + 0x04 */
+	volatile u32 pwmcr;		/* GPT + Timer# * 0x10 + 0x08 */
+	volatile u32 sr;		/* GPT + Timer# * 0x10 + 0x0c */
+};
+
+struct mpc5xxx_gpt_0_7 {
+	struct mpc5xxx_gpt gpt0;
+	struct mpc5xxx_gpt gpt1;
+	struct mpc5xxx_gpt gpt2;
+	struct mpc5xxx_gpt gpt3;
+	struct mpc5xxx_gpt gpt4;
+	struct mpc5xxx_gpt gpt5;
+	struct mpc5xxx_gpt gpt6;
+	struct mpc5xxx_gpt gpt7;
+};
+
+struct mscan_buffer {
+	volatile u8  idr[0x8];          /* 0x00 */
+	volatile u8  dsr[0x10];         /* 0x08 */
+	volatile u8  dlr;               /* 0x18 */
+	volatile u8  tbpr;              /* 0x19 */      /* This register is not applicable for receive buffers */
+	volatile u16 rsrv1;             /* 0x1A */
+	volatile u8  tsrh;              /* 0x1C */
+	volatile u8  tsrl;              /* 0x1D */
+	volatile u16 rsrv2;             /* 0x1E */
+};
+
+struct mpc5xxx_mscan {
+	volatile u8  canctl0;           /* MSCAN + 0x00 */
+	volatile u8  canctl1;           /* MSCAN + 0x01 */
+	volatile u16 rsrv1;             /* MSCAN + 0x02 */
+	volatile u8  canbtr0;           /* MSCAN + 0x04 */
+	volatile u8  canbtr1;           /* MSCAN + 0x05 */
+	volatile u16 rsrv2;             /* MSCAN + 0x06 */
+	volatile u8  canrflg;           /* MSCAN + 0x08 */
+	volatile u8  canrier;           /* MSCAN + 0x09 */
+	volatile u16 rsrv3;             /* MSCAN + 0x0A */
+	volatile u8  cantflg;           /* MSCAN + 0x0C */
+	volatile u8  cantier;           /* MSCAN + 0x0D */
+	volatile u16 rsrv4;             /* MSCAN + 0x0E */
+	volatile u8  cantarq;           /* MSCAN + 0x10 */
+	volatile u8  cantaak;           /* MSCAN + 0x11 */
+	volatile u16 rsrv5;             /* MSCAN + 0x12 */
+	volatile u8  cantbsel;          /* MSCAN + 0x14 */
+	volatile u8  canidac;           /* MSCAN + 0x15 */
+	volatile u16 rsrv6[3];          /* MSCAN + 0x16 */
+	volatile u8  canrxerr;          /* MSCAN + 0x1C */
+	volatile u8  cantxerr;          /* MSCAN + 0x1D */
+	volatile u16 rsrv7;             /* MSCAN + 0x1E */
+	volatile u8  canidar0;          /* MSCAN + 0x20 */
+	volatile u8  canidar1;          /* MSCAN + 0x21 */
+	volatile u16 rsrv8;             /* MSCAN + 0x22 */
+	volatile u8  canidar2;          /* MSCAN + 0x24 */
+	volatile u8  canidar3;          /* MSCAN + 0x25 */
+	volatile u16 rsrv9;             /* MSCAN + 0x26 */
+	volatile u8  canidmr0;          /* MSCAN + 0x28 */
+	volatile u8  canidmr1;          /* MSCAN + 0x29 */
+	volatile u16 rsrv10;            /* MSCAN + 0x2A */
+	volatile u8  canidmr2;          /* MSCAN + 0x2C */
+	volatile u8  canidmr3;          /* MSCAN + 0x2D */
+	volatile u16 rsrv11;            /* MSCAN + 0x2E */
+	volatile u8  canidar4;          /* MSCAN + 0x30 */
+	volatile u8  canidar5;          /* MSCAN + 0x31 */
+	volatile u16 rsrv12;            /* MSCAN + 0x32 */
+	volatile u8  canidar6;          /* MSCAN + 0x34 */
+	volatile u8  canidar7;          /* MSCAN + 0x35 */
+	volatile u16 rsrv13;            /* MSCAN + 0x36 */
+	volatile u8  canidmr4;          /* MSCAN + 0x38 */
+	volatile u8  canidmr5;          /* MSCAN + 0x39 */
+	volatile u16 rsrv14;            /* MSCAN + 0x3A */
+	volatile u8  canidmr6;          /* MSCAN + 0x3C */
+	volatile u8  canidmr7;          /* MSCAN + 0x3D */
+	volatile u16 rsrv15;            /* MSCAN + 0x3E */
+
+	struct mscan_buffer canrxfg;    /* MSCAN + 0x40 */    /* Foreground receive buffer */
+	struct mscan_buffer cantxfg;    /* MSCAN + 0x60 */    /* Foreground transmit buffer */
+	};
+
+struct mpc5xxx_xlb {
+	volatile u8 reserved[0x40];	/* XLB + 0x00 */
+	volatile u32 config;		/* XLB + 0x40 */
+	volatile u32 version;		/* XLB + 0x44 */
+	volatile u32 status;		/* XLB + 0x48 */
+	volatile u32 int_enable;	/* XLB + 0x4c */
+	volatile u32 addr_capture;	/* XLB + 0x50 */
+	volatile u32 bus_sig_capture;	/* XLB + 0x54 */
+	volatile u32 addr_timeout;	/* XLB + 0x58 */
+	volatile u32 data_timeout;	/* XLB + 0x5c */
+	volatile u32 bus_act_timeout;	/* XLB + 0x60 */
+	volatile u32 master_pri_enable; /* XLB + 0x64 */
+	volatile u32 master_priority;	/* XLB + 0x68 */
+	volatile u32 base_address;	/* XLB + 0x6c */
+	volatile u32 snoop_window;	/* XLB + 0x70 */
+};
+
+struct pci_controller;
+
+/* function prototypes */
+void loadtask(int basetask, int tasks);
+void pci_mpc5xxx_init(struct pci_controller *);
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASMPPC_MPC5XXX_H */
diff --git a/qemu/roms/u-boot/include/mpc5xxx_sdma.h b/qemu/roms/u-boot/include/mpc5xxx_sdma.h
new file mode 100644
index 000000000..821ac0ac6
--- /dev/null
+++ b/qemu/roms/u-boot/include/mpc5xxx_sdma.h
@@ -0,0 +1,93 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * This file is based on code
+ * (C) Copyright Motorola, Inc., 2000
+ *
+ * odin smartdma header file
+ */
+
+#ifndef __MPC5XXX_SDMA_H
+#define __MPC5XXX_SDMA_H
+
+#include <common.h>
+#include <mpc5xxx.h>
+
+/* Task number assignment */
+#define FEC_RECV_TASK_NO            0
+#define FEC_XMIT_TASK_NO            1
+
+/*---------------------------------------------------------------------*/
+
+/* Stuff for Ethernet Tx/Rx tasks                                      */
+
+/*---------------------------------------------------------------------*/
+
+/* Layout of Ethernet controller Parameter SRAM area:
+----------------------------------------------------------------
+0x00: TBD_BASE, base address of TX BD ring
+0x04: TBD_NEXT, address of next TX BD to be processed
+0x08: RBD_BASE, base address of RX BD ring
+0x0C: RBD_NEXT, address of next RX BD to be processed
+---------------------------------------------------------------
+ALL PARAMETERS ARE ALL LONGWORDS (FOUR BYTES EACH).
+*/
+
+/* base address of SRAM area to store parameters used by Ethernet tasks */
+#define FEC_PARAM_BASE		(MPC5XXX_SRAM + 0x0800)
+
+/* base address of SRAM area for buffer descriptors */
+#define FEC_BD_BASE		(MPC5XXX_SRAM + 0x0820)
+
+/*---------------------------------------------------------------------*/
+
+/* common shortcuts  used  by driver C code                            */
+
+/*---------------------------------------------------------------------*/
+
+/* Disable SmartDMA task */
+#define SDMA_TASK_DISABLE(tasknum)                     \
+{                                                      \
+    volatile ushort *tcr = (ushort *)(MPC5XXX_SDMA + 0x0000001c + 2 * tasknum); \
+    *tcr = (*tcr) & (~0x8000);                         \
+}
+
+/* Enable SmartDMA task */
+#define SDMA_TASK_ENABLE(tasknum)                      \
+{                                                      \
+    volatile ushort *tcr = (ushort *) (MPC5XXX_SDMA + 0x0000001c + 2 * tasknum); \
+    *tcr = (*tcr)  | 0x8000;                           \
+}
+
+/* Enable interrupt */
+#define SDMA_INT_ENABLE(tasknum)                       \
+{                                                      \
+    struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA; \
+    sdma->IntMask &= ~(1 << tasknum);                  \
+}
+
+/* Disable interrupt */
+#define SDMA_INT_DISABLE(tasknum)   \
+{                                                      \
+    struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA; \
+    sdma->IntMask |= (1 << tasknum);                   \
+}
+
+
+/* Clear interrupt pending bits */
+#define SDMA_CLEAR_IEVENT(tasknum)  \
+{                                                      \
+    struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA; \
+    sdma->IntPend = (1 << tasknum);                    \
+}
+
+/* get interrupt pending bit of a task */
+#define SDMA_GET_PENDINGBIT(tasknum)                   \
+	((*(vu_long *)(MPC5XXX_SDMA + 0x14)) & (1<<(tasknum)))
+
+/* get interrupt mask bit of a task */
+#define SDMA_GET_MASKBIT(tasknum)                      \
+	((*(vu_long *)(MPC5XXX_SDMA + 0x18)) & (1<<(tasknum)))
+
+#endif	/* __MPC5XXX_SDMA_H */
diff --git a/qemu/roms/u-boot/include/mpc824x.h b/qemu/roms/u-boot/include/mpc824x.h
new file mode 100644
index 000000000..31d6f693d
--- /dev/null
+++ b/qemu/roms/u-boot/include/mpc824x.h
@@ -0,0 +1,523 @@
+/*
+ * Copyright Rob Taylor, Flying Pig Systems Ltd. 2000.
+ * Copyright (C) 2001, James Dougherty, jfd@cs.stanford.edu
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MPC824X_H__
+#define __MPC824X_H__
+
+#include <config.h>
+
+/* CPU Types */
+#define CPU_TYPE_601		0x01		/* PPC 601	 CPU */
+#define CPU_TYPE_602		0x02		/* PPC 602	 CPU */
+#define CPU_TYPE_603		0x03		/* PPC 603	 CPU */
+#define CPU_TYPE_603E		0x06		/* PPC 603e	 CPU */
+#define CPU_TYPE_603P		0x07		/* PPC 603p	 CPU */
+#define CPU_TYPE_604		0x04		/* PPC 604	 CPU */
+#define CPU_TYPE_604E		0x09		/* PPC 604e	 CPU */
+#define CPU_TYPE_604R		0x0a		/* PPC 604r	 CPU */
+#define CPU_TYPE_750		0x08		/* PPC 750	 CPU */
+#define CPU_TYPE_8240		0x81		/* PPC 8240	 CPU */
+#define CPU_TYPE_8245		0x8081		/* PPC 8245/8241 CPU */
+#define _CACHE_ALIGN_SIZE	32		/* cache line size */
+
+/* spr976 - DMISS data tlb miss address register
+ * spr977 - DCMP data tlb miss compare register
+ * spr978 - HASH1 PTEG1 address register
+ * spr980 - HASH2 PTEG2 address register
+ * IMISS  - instruction tlb miss address register
+ * ICMP	  - instruction TLB mis compare register
+ * RPA	  - real page address register
+ * HID0	  - hardware implemntation register
+ * HID2	  - instruction address breakpoint register
+ */
+
+/* Kahlua/MPC8240 defines */
+#define VEN_DEV_ID		0x00021057	/* Vendor and Dev. ID for MPC106 */
+#define KAHLUA_ID		0x00031057	/* Vendor & Dev Id for Kahlua's PCI */
+#define KAHLUA2_ID	        0x00061057      /* 8245 is aka Kahlua-2 */
+#define BMC_BASE		0x80000000	/* Kahlua ID in PCI Memory space */
+#define CHRP_REG_ADDR		0xfec00000	/* MPC107 Config, Map B */
+#define CHRP_REG_DATA		0xfee00000	/* MPC107 Config, Map B */
+#define CHRP_ISA_MEM_PHYS	0xfd000000
+#define CHRP_ISA_MEM_BUS	0x00000000
+#define CHRP_ISA_MEM_SIZE	0x01000000
+#define CHRP_ISA_IO_PHYS	0xfe000000
+#define CHRP_ISA_IO_BUS		0x00000000
+#define CHRP_ISA_IO_SIZE	0x00800000
+#define CHRP_PCI_IO_PHYS	0xfe800000
+#define CHRP_PCI_IO_BUS		0x00800000
+#define CHRP_PCI_IO_SIZE	0x00400000
+#define CHRP_PCI_MEM_PHYS	0x80000000
+#define CHRP_PCI_MEM_BUS	0x80000000
+#define CHRP_PCI_MEM_SIZE	0x7d000000
+#define	CHRP_PCI_MEMORY_PHYS	0x00000000
+#define	CHRP_PCI_MEMORY_BUS	0x00000000
+#define CHRP_PCI_MEMORY_SIZE	0x40000000
+#define PREP_REG_ADDR		0x80000cf8	/* MPC107 Config, Map A */
+#define PREP_REG_DATA		0x80000cfc	/* MPC107 Config, Map A */
+#define PREP_ISA_IO_PHYS	0x80000000
+#define PREP_ISA_IO_BUS		0x00000000
+#define PREP_ISA_IO_SIZE	0x00800000
+#define PREP_PCI_IO_PHYS	0x81000000
+#define PREP_PCI_IO_BUS		0x01000000
+#define PREP_PCI_IO_SIZE	0x3e800000
+#define PREP_PCI_MEM_PHYS	0xc0000000
+#define PREP_PCI_MEM_BUS	0x00000000
+#define PREP_PCI_MEM_SIZE	0x3f000000
+#define	PREP_PCI_MEMORY_PHYS	0x00000000
+#define	PREP_PCI_MEMORY_BUS	0x80000000
+#define	PREP_PCI_MEMORY_SIZE	0x80000000
+#define MPC107_PCI_CMD		0x80000004	/* MPC107 PCI cmd reg */
+#define MPC107_PCI_STAT		0x80000006	/* MPC107 PCI status reg */
+#define PROC_INT1_ADR		0x800000a8	/* MPC107 Processor i/f cfg1 */
+#define PROC_INT2_ADR		0x800000ac	/* MPC107 Processor i/f cfg2 */
+#define MEM_CONT1_ADR		0x800000f0	/* MPC107 Memory control config. 1 */
+#define MEM_CONT2_ADR		0x800000f4	/* MPC107 Memory control config. 2 */
+#define MEM_CONT3_ADR		0x800000f8	/* MPC107 Memory control config. 3 */
+#define MEM_CONT4_ADR		0x800000fc	/* MPC107 Memory control config. 4 */
+#define MEM_ERREN1_ADR		0x800000c0	/* MPC107 Memory error enable 1 */
+#define MEM_START1_ADR		0x80000080	/* MPC107 Memory starting addr */
+#define MEM_START2_ADR		0x80000084	/* MPC107 Memory starting addr-lo */
+#define XMEM_START1_ADR		0x80000088	/* MPC107 Extended mem. start addr-hi*/
+#define XMEM_START2_ADR		0x8000008c	/* MPC107 Extended mem. start addr-lo*/
+#define MEM_END1_ADR		0x80000090	/* MPC107 Memory ending address */
+#define MEM_END2_ADR		0x80000094	/* MPC107 Memory ending addr-lo */
+#define XMEM_END1_ADR		0x80000098	/* MPC107 Extended mem. end addrs-hi */
+#define XMEM_END2_ADR		0x8000009c	/* MPC107 Extended mem. end addrs-lo*/
+#define OUT_DRV_CONT		0x80000073	/* MPC107 Output Driver Control reg */
+#define MEM_EN_ADR		0x800000a0	/* Memory bank enable */
+#define PAGE_MODE		0x800000a3	/* MPC107 Page Mode Counter/Timer */
+
+/*-----------------------------------------------------------------------
+ * Exception offsets (PowerPC standard)
+ */
+#define EXC_OFF_RESERVED0	0x0000	/* Reserved */
+#define EXC_OFF_SYS_RESET	0x0100	/* System reset */
+#define EXC_OFF_MACH_CHCK	0x0200	/* Machine Check */
+#define EXC_OFF_DATA_STOR	0x0300	/* Data Storage */
+#define EXC_OFF_INS_STOR	0x0400	/* Instruction Storage */
+#define EXC_OFF_EXTERNAL	0x0500	/* External */
+#define EXC_OFF_ALIGN		0x0600	/* Alignment */
+#define EXC_OFF_PROGRAM		0x0700	/* Program */
+#define EXC_OFF_FPUNAVAIL	0x0800	/* Floating-point Unavailable */
+#define EXC_OFF_DECR		0x0900	/* Decrementer */
+#define EXC_OFF_RESERVED1	0x0A00	/* Reserved */
+#define EXC_OFF_RESERVED2	0x0B00	/* Reserved */
+#define EXC_OFF_SYS_CALL	0x0C00	/* System Call */
+#define EXC_OFF_TRACE		0x0D00	/* Trace */
+#define EXC_OFF_FPUNASSIST	0x0E00	/* Floating-point Assist */
+
+	/* 0x0E10 - 0x0FFF are marked reserved in The PowerPC Architecture book */
+	/* these found in DINK code  - may not apply to 8240*/
+#define EXC_OFF_PMI		0x0F00	/* Performance Monitoring Interrupt */
+#define EXC_OFF_VMXUI		0x0F20	/* VMX (AltiVec) Unavailable Interrupt */
+
+	/* 0x1000 - 0x2FFF are implementation specific */
+	/* these found in DINK code  - may not apply to 8240 */
+#define EXC_OFF_ITME		0x1000	/* Instruction Translation Miss Exception */
+#define EXC_OFF_DLTME		0x1100	/* Data Load Translation Miss Exception */
+#define EXC_OFF_DSTME		0x1200	/* Data Store Translation Miss Exception */
+#define EXC_OFF_IABE		0x1300	/* Instruction Addr Breakpoint Exception */
+#define EXC_OFF_SMIE		0x1400	/* System Management Interrupt Exception */
+#define EXC_OFF_JMDDI		0x1600	/* Java Mode denorm detect Interr -- WTF??*/
+#define EXC_OFF_RMTE		0x2000	/* Run Mode or Trace Exception */
+
+#define _START_OFFSET		EXC_OFF_SYS_RESET
+
+#define MAP_A_CONFIG_ADDR_HIGH	0x8000	/* Upper half of CONFIG_ADDR for Map A */
+#define MAP_A_CONFIG_ADDR_LOW	0x0CF8	/* Lower half of CONFIG_ADDR for Map A */
+#define MAP_A_CONFIG_DATA_HIGH	0x8000	/* Upper half of CONFIG_DAT for Map A */
+#define MAP_A_CONFIG_DATA_LOW	0x0CFC	/* Lower half of CONFIG_DAT for Map A */
+#define MAP_B_CONFIG_ADDR_HIGH	0xfec0	/* Upper half of CONFIG_ADDR for Map B */
+#define MAP_B_CONFIG_ADDR_LOW	0x0000	/* Lower half of CONFIG_ADDR for Map B */
+#define MAP_B_CONFIG_DATA_HIGH	0xfee0	/* Upper half of CONFIG_DAT for Map B */
+#define MAP_B_CONFIG_DATA_LOW	0x0000	/* Lower half of CONFIG_DAT for Map B */
+
+
+#if defined(CONFIG_SYS_ADDR_MAP_A)
+#define CONFIG_ADDR_HIGH    MAP_A_CONFIG_ADDR_HIGH  /* Upper half of CONFIG_ADDR */
+#define CONFIG_ADDR_LOW	    MAP_A_CONFIG_ADDR_LOW   /* Lower half of CONFIG_ADDR */
+#define CONFIG_DATA_HIGH    MAP_A_CONFIG_DATA_HIGH  /* Upper half of CONFIG_DAT */
+#define CONFIG_DATA_LOW	    MAP_A_CONFIG_DATA_LOW   /* Lower half of CONFIG_DAT */
+#else /* Assume Map B, default */
+#define CONFIG_ADDR_HIGH    MAP_B_CONFIG_ADDR_HIGH  /* Upper half of CONFIG_ADDR */
+#define CONFIG_ADDR_LOW	    MAP_B_CONFIG_ADDR_LOW   /* Lower half of CONFIG_ADDR */
+#define CONFIG_DATA_HIGH    MAP_B_CONFIG_DATA_HIGH  /* Upper half of CONFIG_DAT */
+#define CONFIG_DATA_LOW	    MAP_B_CONFIG_DATA_LOW   /* Lower half of CONFIG_DAT */
+#endif
+
+#define CONFIG_ADDR	(CONFIG_ADDR_HIGH << 16 | CONFIG_ADDR_LOW)
+
+#define CONFIG_DATA	(CONFIG_DATA_HIGH << 16 | CONFIG_DATA_LOW)
+
+/* Macros to write to config registers. addr should be a constant in all cases */
+
+#define CONFIG_WRITE_BYTE( addr, data ) \
+  __asm__ __volatile__( \
+  " stwbrx %1, 0, %0\n \
+    sync\n \
+    stb %3, %4(%2)\n \
+    sync " \
+  : /* no output */ \
+  : "r" (CONFIG_ADDR), "r" ((addr) & ~3), \
+    "b" (CONFIG_DATA), "r" (data), \
+    "n" ((addr) & 3));
+
+#define CONFIG_WRITE_HALFWORD( addr, data ) \
+  __asm__ __volatile__( \
+  " stwbrx %1, 0, %0\n \
+    sync\n \
+    sthbrx %3, %4, %2\n \
+    sync " \
+  : /* no output */ \
+  : "r" (CONFIG_ADDR), "r" ((addr) & ~3), \
+    "r" (CONFIG_DATA), "r" (data), \
+    "b" ((addr) & 3));
+
+/* this assumes it's writeing on word boundaries*/
+#define CONFIG_WRITE_WORD( addr, data ) \
+  __asm__ __volatile__( \
+  " stwbrx %1, 0, %0\n \
+    sync\n \
+    stwbrx %3, 0, %2\n \
+    sync " \
+  : /* no output */ \
+  : "r" (CONFIG_ADDR), "r" (addr), \
+    "r" (CONFIG_DATA), "r" (data));
+
+/* Configuration register reads*/
+
+#define CONFIG_READ_BYTE( addr, reg ) \
+  __asm__ ( \
+  " stwbrx %1, 0, %2\n \
+    sync\n \
+    lbz	  %0, %4(%3)\n \
+    sync " \
+  : "=r" (reg) \
+  : "r" ((addr) & ~3), "r" (CONFIG_ADDR), \
+    "b" (CONFIG_DATA), "n" ((addr) & 3));
+
+
+#define CONFIG_READ_HALFWORD( addr, reg ) \
+  __asm__ ( \
+  " stwbrx %1, 0, %2\n \
+    sync\n \
+    lhbrx %0, %4, %3\n \
+    sync " \
+  : "=r" (reg) \
+  : "r" ((addr) & ~3), "r" (CONFIG_ADDR), \
+    "r" (CONFIG_DATA), \
+    "b" ((addr) & 3));
+
+/* this assumes it's reading on word boundaries*/
+#define CONFIG_READ_WORD( addr, reg ) \
+  __asm__ ( \
+  " stwbrx %1, 0, %2\n \
+    sync\n \
+    lwbrx %0, 0, %3\n \
+    sync " \
+  : "=r" (reg) \
+  : "r" (addr), "r" (CONFIG_ADDR),\
+    "r" (CONFIG_DATA));
+
+/*
+ *  configuration register 'addresses'.
+ *  These are described in chaper 5 of the 8240 users manual.
+ *  Where the register has an abreviation in the manual, this has
+ *  been usaed here, otherwise a name in keeping with the norm has
+ *  been invented.
+ *  Note that some of these registers aren't documented in the manual.
+ */
+
+#define PCICR		0x80000004  /* PCI Command Register */
+#define PCISR		0x80000006  /* PCI Status Register */
+#define REVID		0x80000008  /* CPU revision id */
+#define PIR		0x80000009  /* PCI Programming Interface Register */
+#define PBCCR		0x8000000b  /* PCI Base Class Code Register */
+#define PCLSR		0x8000000c  /* Processor Cache Line Size Register */
+#define PLTR		0x8000000d  /* PCI Latancy Timer Register */
+#define PHTR		0x8000000e  /* PCI Header Type Register */
+#define BISTCTRL	0x8000000f  /* BIST Control */
+#define LMBAR		0x80000010  /* Local Base Address Register */
+#define PCSRBAR		0x80000014  /* PCSR Base Address Register */
+#define ILR		0x8000003c  /* PCI Interrupt Line Register */
+#define IPR		0x8000003d  /* Interrupt Pin Register */
+#define MINGNT		0x8000003e  /* MIN GNI */
+#define MAXLAT		0x8000003f  /* MAX LAT */
+#define PCIACR		0x80000046  /* PCI Arbiter Control Register */
+#define PMCR1		0x80000070  /* Power management config. 1 */
+#define PMCR2		0x80000072  /* Power management config. 2 */
+#define ODCR		0x80000073  /* Output Driver Control Register */
+#define CLKDCR		0x80000074  /* CLK Driver Control Register */
+#if defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241)
+#define MIOCR1		0x80000076  /* Miscellaneous I/O Control Register 1 */
+#define MIOCR2		0x80000077  /* Miscellaneous I/O Control Register 2 */
+#endif
+#define EUMBBAR		0x80000078  /* Embedded Utilities Memory Block Base Address Register */
+#define EUMBBAR_VAL	0x80500000  /* PCI Relocation offset for EUMB region */
+#define EUMBSIZE	0x00100000  /* Size of EUMB region */
+
+#define MSAR1		0x80000080  /* Memory Starting Address Register 1 */
+#define MSAR2		0x80000084  /* Memory Starting Address Register 2 */
+#define EMSAR1		0x80000088  /* Extended Memory Starting Address Register 1*/
+#define EMSAR2		0x8000008c  /* Extended Memory Starting Address Register 2*/
+#define MEAR1		0x80000090  /* Memory Ending Address Register 1 */
+#define MEAR2		0x80000094  /* Memory Ending Address Register 2 */
+#define EMEAR1		0x80000098  /* Extended Memory Ending Address Register 1 */
+#define EMEAR2		0x8000009c  /* Extended Memory Ending Address Register 2 */
+#define MBER		0x800000a0  /* Memory bank Enable Register*/
+#define MPMR		0x800000a3  /* Memory Page Mode Register (stores PGMAX) */
+#define PICR1		0x800000a8  /* Processor Interface Configuration Register 1 */
+#define PICR2		0x800000ac  /* Processor Interface Configuration Register 2 */
+#define ECCSBECR	0x800000b8  /* ECC Single-Bit Error Counter Register */
+#define ECCSBETR	0x800000b8  /* ECC Single-Bit Error Trigger Register */
+#define ERRENR1		0x800000c0  /* Error Enableing Register 1 */
+#define ERRENR2		0x800000c4  /* Error Enableing Register 2 */
+#define ERRDR1		0x800000c1  /* Error Detection Register 1 */
+#define IPBESR		0x800000c3  /* Internal Processor Error Status Register */
+#define ERRDR2		0x800000c5  /* Error Detection Register 2 */
+#define PBESR		0x800000c7  /* PCI Bus Error Status Register */
+#define PBEAR		0x800000c8  /* Processor/PCI Bus Error Status Register */
+#define AMBOR		0x800000e0  /* Address Map B Options Register */
+#define PCMBCR		0x800000e1  /* PCI/Memory Buffer Configuration */
+#define MCCR1		0x800000f0  /* Memory Control Configuration Register 1 */
+#define MCCR2		0x800000f4  /* Memory Control Configuration Register 2 */
+#define MCCR3		0x800000f8  /* Memory Control Configuration Register 3 */
+#define MCCR4		0x800000fc  /* Memory Control Configuration Register 4 */
+
+/* some values for some of the above */
+
+#define PICR1_CF_APARK		0x00000008
+#define PICR1_LE_MODE		0x00000020
+#define PICR1_ST_GATH_EN	0x00000040
+#if defined(CONFIG_MPC8240)
+#define PICR1_EN_PCS		0x00000080 /* according to dink code, sets the 8240 to handle pci config space */
+#elif defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241)
+#define PICR1_NO_BUSW_CK	0x00000080 /* no bus width check for flash writes */
+#define PICR1_DEC		0x00000100 /* Time Base enable on 8245/8241 */
+#define ERCR1		        0x800000d0  /* Extended ROM Configuration Register 1 */
+#define ERCR2		        0x800000d4  /* Extended ROM Configuration Register 2 */
+#define ERCR3		        0x800000d8  /* Extended ROM Configuration Register 3 */
+#define ERCR4		        0x800000dc  /* Extended ROM Configuration Register 4 */
+#define MIOCR1		        0x80000076  /* Miscellaneous I/O Control Register 1 */
+#define MIOCR1_ADR_X	        0x80000074  /* Miscellaneous I/O Control Register 1 */
+#define MIOCR1_SHIFT	        2
+#define MIOCR2		        0x80000077  /* Miscellaneous I/O Control Register 2 */
+#define MIOCR2_ADR_X	        0x80000074  /* Miscellaneous I/O Control Register 1 */
+#define MIOCR2_SHIFT	        3
+#define ODCR_ADR_X	        0x80000070	/* Output Driver Control register */
+#define ODCR_SHIFT              3
+#define PMCR2_ADR	        0x80000072	/* Power Mgmnt Cfg 2 register */
+#define PMCR2_ADR_X	        0x80000070
+#define PMCR2_SHIFT             3
+#define PMCR1_ADR	        0x80000070	/* Power Mgmnt Cfg 1 reister */
+#else
+#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
+#endif
+#define PICR1_CF_DPARK		0x00000200
+#define PICR1_MCP_EN		0x00000800
+#define PICR1_FLASH_WR_EN	0x00001000
+#ifdef CONFIG_MPC8240
+#define PICR1_ADDRESS_MAP	0x00010000
+#define PIRC1_MSK		0xff000000
+#endif
+#define PICR1_PROC_TYPE_MSK	0x00060000
+#define PICR1_PROC_TYPE_603E	0x00040000
+#define PICR1_RCS0		0x00100000
+
+#define PICR2_CF_SNOOP_WS_MASK	0x000c0000
+#define PICR2_CF_SNOOP_WS_0WS	0x00000000
+#define PICR2_CF_SNOOP_WS_1WS	0x00040000
+#define PICR2_CF_SNOOP_WS_2WS	0x00080000
+#define PICR2_CF_SNOOP_WS_3WS	0x000c0000
+#define PICR2_CF_APHASE_WS_MASK 0x0000000c
+#define PICR2_CF_APHASE_WS_0WS	0x00000000
+#define PICR2_CF_APHASE_WS_1WS	0x00000004
+#define PICR2_CF_APHASE_WS_2WS	0x00000008
+#define PICR2_CF_APHASE_WS_3WS	0x0000000c
+
+#define MCCR1_ROMNAL_SHIFT	28
+#define MCCR1_ROMNAL_MSK	0xf0000000
+#define MCCR1_ROMFAL_SHIFT	23
+#define MCCR1_ROMFAL_MSK	0x0f800000
+#define MCCR1_DBUS_SIZE0        0x00400000
+#define MCCR1_BURST		0x00100000
+#define MCCR1_MEMGO		0x00080000
+#define MCCR1_SREN		0x00040000
+#if defined(CONFIG_MPC8240)
+#define MCCR1_RAM_TYPE		0x00020000
+#elif defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241)
+#define MCCR1_SDRAM_EN		0x00020000
+#else
+#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
+#endif
+#define MCCR1_PCKEN		0x00010000
+#define MCCR1_BANK1ROW_SHIFT	2
+#define MCCR1_BANK2ROW_SHIFT	4
+#define MCCR1_BANK3ROW_SHIFT	6
+#define MCCR1_BANK4ROW_SHIFT	8
+#define MCCR1_BANK5ROW_SHIFT	10
+#define MCCR1_BANK6ROW_SHIFT	12
+#define MCCR1_BANK7ROW_SHIFT	14
+
+#define MCCR2_TS_WAIT_TIMER_MSK 0xe0000000
+#define MCCR2_TS_WAIT_TIMER_SHIFT 29
+#define MCCR2_ASRISE_MSK	0x1e000000
+#define MCCR2_ASRISE_SHIFT	25
+#define MCCR2_ASFALL_MSK	0x01e00000
+#define MCCR2_ASFALL_SHIFT	21
+
+#define MCCR2_INLINE_PAR_NOT_ECC    0x00100000
+#define MCCR2_WRITE_PARITY_CHK	0x00080000
+#define MCCR2_INLFRD_PARECC_CHK_EN  0x00040000
+#ifdef CONFIG_MPC8240
+#define MCCR2_ECC_EN		0x00020000
+#define MCCR2_EDO		0x00010000
+#endif
+#define MCCR2_REFINT_MSK	0x0000fffc
+#define MCCR2_REFINT_SHIFT	2
+#define MCCR2_RSV_PG		0x00000002
+#define MCCR2_PMW_PAR		0x00000001
+
+#define MCCR3_BSTOPRE2TO5_MSK	0xf0000000 /*BSTOPRE[2-5]*/
+#define MCCR3_BSTOPRE2TO5_SHIFT 28
+#define MCCR3_REFREC_MSK	0x0f000000
+#define MCCR3_REFREC_SHIFT	24
+#ifdef CONFIG_MPC8240
+#define MCCR3_RDLAT_MSK		0x00f00000
+#define MCCR3_RDLAT_SHIFT	20
+#define MCCR3_CPX		0x00010000
+#define MCCR3_RAS6P_MSK		0x00078000
+#define MCCR3_RAS6P_SHIFT	15
+#define MCCR3_CAS5_MSK		0x00007000
+#define MCCR3_CAS5_SHIFT	12
+#define MCCR3_CP4_MSK		0x00000e00
+#define MCCR3_CP4_SHIFT		9
+#define MCCR3_CAS3_MSK		0x000001c0
+#define MCCR3_CAS3_SHIFT	6
+#define MCCR3_RCD2_MSK		0x00000038
+#define MCCR3_RCD2_SHIFT	3
+#define MCCR3_RP1_MSK		0x00000007
+#define MCCR3_RP1_SHIFT		0
+#endif
+
+#define MCCR4_PRETOACT_MSK	0xf0000000
+#define MCCR4_PRETOACT_SHIFT	28
+#define MCCR4_ACTTOPRE_MSK	0x0f000000
+#define MCCR4_ACTTOPRE_SHIFT	24
+#define MCCR4_WMODE		0x00800000
+#define MCCR4_INLINE		0x00400000
+#if defined(CONFIG_MPC8240)
+#define MCCR4_BIT21		0x00200000 /* this include cos DINK code sets it- unknown function*/
+#elif defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241)
+#define MCCR4_EXTROM		0x00200000 /* enables Extended ROM space */
+#else
+#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
+#endif
+#define MCCR4_REGISTERED	0x00100000
+#define MCCR4_BSTOPRE0TO1_MSK	0x000c0000 /*BSTOPRE[0-1]*/
+#define MCCR4_BSTOPRE0TO1_SHIFT 18
+#define MCCR4_REGDIMM		0x00008000
+#define MCCR4_SDMODE_MSK	0x00007f00
+#define MCCR4_SDMODE_SHIFT	8
+#define MCCR4_ACTTORW_MSK	0x000000f0
+#define MCCR4_ACTTORW_SHIFT	4
+#define MCCR4_BSTOPRE6TO9_MSK	0x0000000f /*BSTOPRE[6-9]*/
+#define MCCR4_BSTOPRE6TO9_SHIFT 0
+#define MCCR4_DBUS_SIZE2_SHIFT	17
+
+#define MICR_ADDR_MASK		0x0ff00000
+#define MICR_ADDR_SHIFT		20
+#define MICR_EADDR_MASK		0x30000000
+#define MICR_EADDR_SHIFT	28
+
+/*eumb and epic config*/
+
+#define EPIC_FPR		0x00041000
+#define EPIC_GCR		0x00041020
+#define EPIC_EICR		0x00041030
+#define EPIC_EVI		0x00041080
+#define EPIC_PI			0x00041090
+#define EPIC_SVR		0x000410E0
+#define EPIC_TFRR		0x000410F0
+
+/*
+ * Note the information for these is rather mangled in the 8240 manual.
+ * These are guesses.
+ */
+
+#define EPIC_GTCCR0		0x00041100
+#define EPIC_GTCCR1		0x00041140
+#define EPIC_GTCCR2		0x00041180
+#define EPIC_GTCCR3		0x000411C0
+#define EPIC_GTBCR0		0x00041110
+#define EPIC_GTBCR1		0x00041150
+#define EPIC_GTBCR2		0x00041190
+#define EPIC_GTBCR3		0x000411D0
+#define EPIC_GTVPR0		0x00041120
+#define EPIC_GTVPR1		0x00041160
+#define EPIC_GTVPR2		0x000411a0
+#define EPIC_GTVPR3		0x000411e0
+#define EPIC_GTDR0		0x00041130
+#define EPIC_GTDR1		0x00041170
+#define EPIC_GTDR2		0x000411b0
+#define EPIC_GTDR3		0x000411f0
+
+#define EPIC_IVPR0		0x00050200
+#define EPIC_IVPR1		0x00050220
+#define EPIC_IVPR2		0x00050240
+#define EPIC_IVPR3		0x00050260
+#define EPIC_IVPR4		0x00050280
+
+#define EPIC_SVPR0		0x00050200
+#define EPIC_SVPR1		0x00050220
+#define EPIC_SVPR2		0x00050240
+#define EPIC_SVPR3		0x00050260
+#define EPIC_SVPR4		0x00050280
+#define EPIC_SVPR5		0x000502A0
+#define EPIC_SVPR6		0x000502C0
+#define EPIC_SVPR7		0x000502E0
+#define EPIC_SVPR8		0x00050300
+#define EPIC_SVPR9		0x00050320
+#define EPIC_SVPRa		0x00050340
+#define EPIC_SVPRb		0x00050360
+#define EPIC_SVPRc		0x00050380
+#define EPIC_SVPRd		0x000503A0
+#define EPIC_SVPRe		0x000503C0
+#define EPIC_SVPRf		0x000503E0
+
+/* MPC8240 Byte Swap/PCI Support Macros */
+#define BYTE_SWAP_16_BIT(x)    ( (((x) & 0x00ff) << 8) | ( (x) >> 8) )
+#define LONGSWAP(x) ((((x) & 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8)|\
+		     (((x) & 0x00ff0000) >>  8) | (((x) & 0xff000000) >> 24) )
+#define PCISWAP(x)   LONGSWAP(x)
+
+#ifndef __ASSEMBLY__
+
+/*
+ * MPC107 Support
+ *
+ */
+unsigned int mpc824x_mpc107_getreg(unsigned int regNum);
+void mpc824x_mpc107_setreg(unsigned int regNum, unsigned int regVal);
+void mpc824x_mpc107_write8(unsigned int address, unsigned char data);
+void mpc824x_mpc107_write16(unsigned int address, unsigned short data);
+void mpc824x_mpc107_write32(unsigned int address, unsigned int data);
+unsigned char mpc824x_mpc107_read8(unsigned int address);
+unsigned short mpc824x_mpc107_read16(unsigned int address);
+unsigned int mpc824x_mpc107_read32(unsigned int address);
+unsigned int mpc824x_eummbar_read(unsigned int regNum);
+void mpc824x_eummbar_write(unsigned int regNum, unsigned int regVal);
+
+#ifdef CONFIG_PCI
+struct pci_controller;
+void pci_cpm824x_init(struct pci_controller* hose);
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __MPC824X_H__ */
diff --git a/qemu/roms/u-boot/include/mpc8260.h b/qemu/roms/u-boot/include/mpc8260.h
new file mode 100644
index 000000000..a8ae27879
--- /dev/null
+++ b/qemu/roms/u-boot/include/mpc8260.h
@@ -0,0 +1,907 @@
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * mpc8260.h
+ *
+ * MPC8255 / MPC8260 specific definitions
+ */
+
+#ifndef __MPC8260_H__
+#define __MPC8260_H__
+
+#ifdef CONFIG_MPC8255
+#define CPU_ID_STR	"MPC8255"
+#endif
+#ifndef CPU_ID_STR
+#if defined(CONFIG_MPC8272_FAMILY)
+#ifdef CONFIG_MPC8247
+#define CPU_ID_STR	"MPC8247"
+#elif defined CONFIG_MPC8248
+#define CPU_ID_STR	"MPC8248"
+#elif defined CONFIG_MPC8271
+#define CPU_ID_STR	"MPC8271"
+#else
+#define CPU_ID_STR	"MPC8272"
+#endif
+#else
+#define CPU_ID_STR	"MPC8260"
+#endif
+#endif /* !CPU_ID_STR */
+
+/*-----------------------------------------------------------------------
+ * Exception offsets (PowerPC standard)
+ */
+#define EXC_OFF_SYS_RESET	0x0100	/* System reset			*/
+#define _START_OFFSET		EXC_OFF_SYS_RESET
+
+/*-----------------------------------------------------------------------
+ * BCR - Bus Configuration Register					 4-25
+ */
+#define BCR_EBM		0x80000000	/* External Bus Mode		*/
+#define BCR_APD_MSK	0x70000000	/* Address Phase Delay Mask	*/
+#define BCR_L2C		0x08000000	/* Secondary Cache Controller	*/
+#define BCR_L2D_MSK	0x07000000	/* L2 Cache Hit Delay Mask	*/
+#define BCR_PLDP	0x00800000	/* Pipeline Maximum Depth	*/
+#define BCR_EAV		0x00400000	/* Enable Address Visibility	*/
+#define BCR_ETM		0x00080000	/* Compatibility Mode Enable	*/
+#define BCR_LETM	0x00040000	/* LocalBus Compatibility Mode Enable*/
+#define BCR_EPAR	0x00020000	/* Even Parity			*/
+#define BCR_LEPAR	0x00010000	/* Local Bus Even Parity	*/
+#define BCR_NPQM0	0x00008000	/* Non PowerQUICC-II Master 0	*/
+#define BCR_NPQM1	0x00004000	/* Non PowerQUICC-II Master 1	*/
+#define BCR_NPQM2	0x00002000	/* Non PowerQUICC-II Master 2	*/
+#define BCR_EXDD	0x00000400	/* External Master Delay Disable*/
+#define BCR_ISPS	0x00000010	/* Internal Space Port Size	*/
+
+
+/*-----------------------------------------------------------------------
+ * PPC_ACR - 60x Bus Arbiter Configuration Register			 4-28
+ */
+#define PPC_ACR_DBGD	0x20		/* Data Bus Grant Delay		*/
+#define PPC_ACR_EARB	0x10		/* External Arbitration		*/
+#define PPC_ACR_PRKM_MSK 0x0f		/* Parking Master		*/
+
+#define PPC_ACR_PRKM_CPMH 0x00		/* CPM high request level	*/
+#define PPC_ACR_PRKM_CPMM 0x01		/* CPM middle request level	*/
+#define PPC_ACR_PRKM_CPML 0x02		/* CPM low request level	*/
+#define PPC_ACR_PRKM_CORE 0x06		/* Internal Core		*/
+#define PPC_ACR_PRKM_EXT1 0x07		/* External Master 1		*/
+#define PPC_ACR_PRKM_EXT2 0x08		/* External Master 2		*/
+#define PPC_ACR_PRKM_EXT3 0x09		/* External Master 3		*/
+
+/*-----------------------------------------------------------------------
+ * PPC_ALRH/PPC_ALRL - 60x Bus Arbitration-Level Registers		 4-28
+ */
+#define PPC_ALRH_PF0_MSK  0xf0000000	/* Priority Field  0 Mask	*/
+#define PPC_ALRH_PF1_MSK  0x0f000000	/* Priority Field  1 Mask	*/
+#define PPC_ALRH_PF2_MSK  0x00f00000	/* Priority Field  2 Mask	*/
+#define PPC_ALRH_PF3_MSK  0x000f0000	/* Priority Field  3 Mask	*/
+#define PPC_ALRH_PF4_MSK  0x0000f000	/* Priority Field  4 Mask	*/
+#define PPC_ALRH_PF5_MSK  0x00000f00	/* Priority Field  5 Mask	*/
+#define PPC_ALRH_PF6_MSK  0x000000f0	/* Priority Field  6 Mask	*/
+#define PPC_ALRH_PF7_MSK  0x0000000f	/* Priority Field  7 Mask	*/
+#define PPC_ALRL_PF8_MSK  0xf0000000	/* Priority Field  8 Mask	*/
+#define PPC_ALRL_PF9_MSK  0x0f000000	/* Priority Field  9 Mask	*/
+#define PPC_ALRL_PF10_MSK 0x00f00000	/* Priority Field 10 Mask	*/
+#define PPC_ALRL_PF11_MSK 0x000f0000	/* Priority Field 11 Mask	*/
+#define PPC_ALRL_PF12_MSK 0x0000f000	/* Priority Field 12 Mask	*/
+#define PPC_ALRL_PF13_MSK 0x00000f00	/* Priority Field 13 Mask	*/
+#define PPC_ALRL_PF14_MSK 0x000000f0	/* Priority Field 14 Mask	*/
+#define PPC_ALRL_PF15_MSK 0x0000000f	/* Priority Field 15 Mask	*/
+
+/*-----------------------------------------------------------------------
+ * LCL_ACR - Local Bus Arbiter Configuration Register			 4-29
+ */
+#define LCL_ACR_DBGD	0x20		/* Data Bus Grant Delay		*/
+#define LCL_ACR_PRKM_MSK 0x0f		/* Parking Master		*/
+
+#define LCL_ACR_PRKM_CPMH 0x00		/* CPM high request level	*/
+#define LCL_ACR_PRKM_CPMM 0x01		/* CPM middle request level	*/
+#define LCL_ACR_PRKM_CPML 0x02		/* CPM low request level	*/
+#define LCL_ACR_PRKM_HOST 0x03		/* Host Bridge			*/
+
+/*-----------------------------------------------------------------------
+ * LCL_ALRH/LCL_ALRL - Local Bus Arbitration Level Registers		 4-30
+ */
+#define LCL_ALRH_PF0_MSK  0xf0000000	/* Priority Field  0 Mask	*/
+#define LCL_ALRH_PF1_MSK  0x0f000000	/* Priority Field  1 Mask	*/
+#define LCL_ALRH_PF2_MSK  0x00f00000	/* Priority Field  2 Mask	*/
+#define LCL_ALRH_PF3_MSK  0x000f0000	/* Priority Field  3 Mask	*/
+#define LCL_ALRH_PF4_MSK  0x0000f000	/* Priority Field  4 Mask	*/
+#define LCL_ALRH_PF5_MSK  0x00000f00	/* Priority Field  5 Mask	*/
+#define LCL_ALRH_PF6_MSK  0x000000f0	/* Priority Field  6 Mask	*/
+#define LCL_ALRH_PF7_MSK  0x0000000f	/* Priority Field  7 Mask	*/
+#define LCL_ALRL_PF8_MSK  0xf0000000	/* Priority Field  8 Mask	*/
+#define LCL_ALRL_PF9_MSK  0x0f000000	/* Priority Field  9 Mask	*/
+#define LCL_ALRL_PF10_MSK 0x00f00000	/* Priority Field 10 Mask	*/
+#define LCL_ALRL_PF11_MSK 0x000f0000	/* Priority Field 11 Mask	*/
+#define LCL_ALRL_PF12_MSK 0x0000f000	/* Priority Field 12 Mask	*/
+#define LCL_ALRL_PF13_MSK 0x00000f00	/* Priority Field 13 Mask	*/
+#define LCL_ALRL_PF14_MSK 0x000000f0	/* Priority Field 14 Mask	*/
+#define LCL_ALRL_PF15_MSK 0x0000000f	/* Priority Field 15 Mask	*/
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration Register				 4-31
+ */
+#define SIUMCR_BBD	0x80000000	/* Bus Busy Disable		*/
+#define SIUMCR_ESE	0x40000000	/* External Snoop Enable	*/
+#define SIUMCR_PBSE	0x20000000	/* Parity Byte Select Enable	*/
+#define SIUMCR_CDIS	0x10000000	/* Core Disable			*/
+#define SIUMCR_DPPC00	0x00000000	/* Data Parity Pins Configuration*/
+#define SIUMCR_DPPC01	0x04000000	/* - " -			*/
+#define SIUMCR_DPPC10	0x08000000	/* - " -			*/
+#define SIUMCR_DPPC11	0x0c000000	/* - " -			*/
+#define SIUMCR_L2CPC00	0x00000000	/* L2 Cache Pins Configuration	*/
+#define SIUMCR_L2CPC01	0x01000000	/* - " -			*/
+#define SIUMCR_L2CPC10	0x02000000	/* - " -			*/
+#define SIUMCR_L2CPC11	0x03000000	/* - " -			*/
+#define SIUMCR_LBPC00	0x00000000	/* Local Bus Pins Configuration	*/
+#define SIUMCR_LBPC01	0x00400000	/* - " -			*/
+#define SIUMCR_LBPC10	0x00800000	/* - " -			*/
+#define SIUMCR_LBPC11	0x00c00000	/* - " -			*/
+#define SIUMCR_APPC00	0x00000000	/* Address Parity Pins Configuration*/
+#define SIUMCR_APPC01	0x00100000	/* - " -			*/
+#define SIUMCR_APPC10	0x00200000	/* - " -			*/
+#define SIUMCR_APPC11	0x00300000	/* - " -			*/
+#define SIUMCR_CS10PC00	0x00000000	/* CS10 Pin Configuration	*/
+#define SIUMCR_CS10PC01	0x00040000	/* - " -			*/
+#define SIUMCR_CS10PC10	0x00080000	/* - " -			*/
+#define SIUMCR_CS10PC11	0x000c0000	/* - " -			*/
+#define SIUMCR_BCTLC00	0x00000000	/* Buffer Control Configuration	*/
+#define SIUMCR_BCTLC01	0x00010000	/* - " -			*/
+#define SIUMCR_BCTLC10	0x00020000	/* - " -			*/
+#define SIUMCR_BCTLC11	0x00030000	/* - " -			*/
+#define SIUMCR_MMR00	0x00000000	/* Mask Masters Requests	*/
+#define SIUMCR_MMR01	0x00004000	/* - " -			*/
+#define SIUMCR_MMR10	0x00008000	/* - " -			*/
+#define SIUMCR_MMR11	0x0000c000	/* - " -			*/
+#define SIUMCR_LPBSE	0x00002000	/* LocalBus Parity Byte Select Enable*/
+#define SIUMCR_ABE	0x00000400	/* Address output buffer impedance*/
+
+/*-----------------------------------------------------------------------
+ * IMMR - Internal Memory Map Register					 4-34
+ */
+#define IMMR_ISB_MSK	 0xfffe0000	/* Internal Space base		*/
+#define IMMR_PARTNUM_MSK 0x0000ff00	/* Part number			*/
+#define IMMR_MASKNUM_MSK 0x000000ff	/* Mask number			*/
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control Register				 4-35
+ */
+#define SYPCR_SWTC	0xffff0000	/* Software Watchdog Timer Count*/
+#define SYPCR_BMT	0x0000ff00	/* Bus Monitor Timing		*/
+#define SYPCR_PBME	0x00000080	/* 60x Bus Monitor Enable	*/
+#define SYPCR_LBME	0x00000040	/* Local Bus Monitor Enable	*/
+#define SYPCR_SWE	0x00000004	/* Software Watchdog Enable	*/
+#define SYPCR_SWRI	0x00000002	/* Software Watchdog Reset/Int Select*/
+#define SYPCR_SWP	0x00000001	/* Software Watchdog Prescale	*/
+
+/*-----------------------------------------------------------------------
+ * TMCNTSC - Time Counter Status and Control Register			 4-40
+ */
+#define TMCNTSC_SEC	0x0080		/* Once Per Second Interrupt	*/
+#define TMCNTSC_ALR	0x0040		/* Alarm Interrupt		*/
+#define TMCNTSC_SIE	0x0008		/* Second Interrupt Enable	*/
+#define TMCNTSC_ALE	0x0004		/* Alarm Interrupt Enable	*/
+#define TMCNTSC_TCF	0x0002		/* Time Counter Frequency	*/
+#define TMCNTSC_TCE	0x0001		/* Time Counter Enable		*/
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control Register		 4-42
+ */
+#if 0	/* already defined in asm/immap_8260.h */
+#define PISCR_PS	0x0080		/* Periodic Interrupt Status	*/
+#define PISCR_PIE	0x0004		/* Periodic Interrupt Enable	*/
+#define PISCR_PTF	0x0002		/* Periodic Timer Frequency	*/
+#define PISCR_PTE	0x0001		/* Periodic Timer Enable	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * RSR - Reset Status Register						 5-4
+ */
+#define RSR_JTRS	0x00000020	/* JTAG Reset Status		*/
+#define RSR_CSRS	0x00000010	/* Check Stop Reset Status	*/
+#define RSR_SWRS	0x00000008	/* Software Watchdog Reset Status*/
+#define RSR_BMRS	0x00000004	/* Bus Monitor Reset Status	*/
+#define RSR_ESRS	0x00000002	/* External Soft Reset Status	*/
+#define RSR_EHRS	0x00000001	/* External Hard Reset Status	*/
+
+#define RSR_ALLBITS	(RSR_JTRS|RSR_CSRS|RSR_SWRS|RSR_BMRS|RSR_ESRS|RSR_EHRS)
+
+/*-----------------------------------------------------------------------
+ * RMR - Reset Mode Register						 5-5
+ */
+#define RMR_CSRE	0x00000001	/* Checkstop Reset Enable	*/
+
+/*-----------------------------------------------------------------------
+ * Hard Reset Configuration Word					 5-8
+ */
+#define HRCW_EARB	0x80000000	/* External Arbitration		*/
+#define HRCW_EXMC	0x40000000	/* External Memory Controller	*/
+#define HRCW_CDIS	0x20000000	/* Core Disable			*/
+#define HRCW_EBM	0x10000000	/* External Bus Mode		*/
+#define HRCW_BPS00	0x00000000	/* Boot Port Size		*/
+#define HRCW_BPS01	0x04000000	/* - " -			*/
+#define HRCW_BPS10	0x08000000	/* - " -			*/
+#define HRCW_BPS11	0x0c000000	/* - " -			*/
+#define HRCW_CIP	0x02000000	/* Core Initial Prefix		*/
+#define HRCW_ISPS	0x01000000	/* Internal Space Port Size	*/
+#define HRCW_L2CPC00	0x00000000	/* L2 Cache Pins Configuration	*/
+#define HRCW_L2CPC01	0x00400000	/* - " -			*/
+#define HRCW_L2CPC10	0x00800000	/* - " -			*/
+#define HRCW_L2CPC11	0x00c00000	/* - " -			*/
+#define HRCW_DPPC00	0x00000000	/* Data Parity Pin Configuration*/
+#define HRCW_DPPC01	0x00100000	/* - " -			*/
+#define HRCW_DPPC10	0x00200000	/* - " -			*/
+#define HRCW_DPPC11	0x00300000	/* - " -			*/
+#define HRCW_reserved1	0x00080000	/* reserved			*/
+#define HRCW_ISB000	0x00000000	/* Initial Internal Space Base	*/
+#define HRCW_ISB001	0x00010000	/* - " -			*/
+#define HRCW_ISB010	0x00020000	/* - " -			*/
+#define HRCW_ISB011	0x00030000	/* - " -			*/
+#define HRCW_ISB100	0x00040000	/* - " -			*/
+#define HRCW_ISB101	0x00050000	/* - " -			*/
+#define HRCW_ISB110	0x00060000	/* - " -			*/
+#define HRCW_ISB111	0x00070000	/* - " -			*/
+#define HRCW_BMS	0x00008000	/* Boot Memory Space		*/
+#define HRCW_BBD	0x00004000	/* Bus Busy Disable		*/
+#define HRCW_MMR00	0x00000000	/* Mask Masters Requests	*/
+#define HRCW_MMR01	0x00001000	/* - " -			*/
+#define HRCW_MMR10	0x00002000	/* - " -			*/
+#define HRCW_MMR11	0x00003000	/* - " -			*/
+#define HRCW_LBPC00	0x00000000	/* Local Bus Pin Configuration	*/
+#define HRCW_LBPC01	0x00000400	/* - " -			*/
+#define HRCW_LBPC10	0x00000800	/* - " -			*/
+#define HRCW_LBPC11	0x00000c00	/* - " -			*/
+#define HRCW_APPC00	0x00000000	/* Address Parity Pin Configuration*/
+#define HRCW_APPC01	0x00000100	/* - " -			*/
+#define HRCW_APPC10	0x00000200	/* - " -			*/
+#define HRCW_APPC11	0x00000300	/* - " -			*/
+#define HRCW_CS10PC00	0x00000000	/* CS10 Pin Configuration	*/
+#define HRCW_CS10PC01	0x00000040	/* - " -			*/
+#define HRCW_CS10PC10	0x00000080	/* - " -			*/
+#define HRCW_CS10PC11	0x000000c0	/* - " -			*/
+#define HRCW_MODCK_H0000 0x00000000	/* High-order bits of MODCK Bus	*/
+#define HRCW_MODCK_H0001 0x00000001	/* - " -			*/
+#define HRCW_MODCK_H0010 0x00000002	/* - " -			*/
+#define HRCW_MODCK_H0011 0x00000003	/* - " -			*/
+#define HRCW_MODCK_H0100 0x00000004	/* - " -			*/
+#define HRCW_MODCK_H0101 0x00000005	/* - " -			*/
+#define HRCW_MODCK_H0110 0x00000006	/* - " -			*/
+#define HRCW_MODCK_H0111 0x00000007	/* - " -			*/
+#define HRCW_MODCK_H1000 0x00000008	/* - " -			*/
+#define HRCW_MODCK_H1001 0x00000009	/* - " -			*/
+#define HRCW_MODCK_H1010 0x0000000a	/* - " -			*/
+#define HRCW_MODCK_H1011 0x0000000b	/* - " -			*/
+#define HRCW_MODCK_H1100 0x0000000c	/* - " -			*/
+#define HRCW_MODCK_H1101 0x0000000d	/* - " -			*/
+#define HRCW_MODCK_H1110 0x0000000e	/* - " -			*/
+#define HRCW_MODCK_H1111 0x0000000f	/* - " -			*/
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control Register					 9-8
+ */
+#define SCCR_PCI_MODE	0x00000100	/* PCI Mode	*/
+#define SCCR_PCI_MODCK	0x00000080	/* Value of PCI_MODCK pin	*/
+#define SCCR_PCIDF_MSK	0x00000078	/* PCI division factor	*/
+#define SCCR_PCIDF_SHIFT 3
+#define SCCR_CLPD	0x00000004	/* CPM Low Power Disable	*/
+#define SCCR_DFBRG_MSK	0x00000003	/* Division factor of BRGCLK Mask */
+#define SCCR_DFBRG_SHIFT 0
+
+#define SCCR_DFBRG00	0x00000000	/* BRGCLK division by 4		*/
+#define SCCR_DFBRG01	0x00000001	/* BRGCLK division by 16 (normal op.)*/
+#define SCCR_DFBRG10	0x00000002	/* BRGCLK division by 64	*/
+#define SCCR_DFBRG11	0x00000003	/* BRGCLK division by 128	*/
+
+/*-----------------------------------------------------------------------
+ * SCMR - System Clock Mode Register					 9-9
+ */
+#define SCMR_CORECNF_MSK   0x1f000000	/* Core Configuration Mask	*/
+#define SCMR_CORECNF_SHIFT 24
+#define SCMR_BUSDF_MSK	   0x00f00000	/* 60x Bus Division Factor Mask	*/
+#define SCMR_BUSDF_SHIFT   20
+#define SCMR_CPMDF_MSK	   0x000f0000	/* CPM Division Factor Mask	*/
+#define SCMR_CPMDF_SHIFT   16
+#define SCMR_PLLDF	   0x00001000	/* PLL Pre-divider Value	*/
+#define SCMR_PLLMF_MSK	   0x00000fff	/* PLL Multiplication Factor Mask*/
+#define SCMR_PLLMF_MSKH7   0x0000000f	/* for HiP7 processors */
+#define SCMR_PLLMF_SHIFT 0
+
+
+/*-----------------------------------------------------------------------
+ * MxMR - Machine A/B/C Mode Registers					10-13
+ */
+#define MxMR_BSEL	0x80000000	/* Bus Select			*/
+#define MxMR_RFEN	0x40000000	/* Refresh Enable		*/
+#define MxMR_OP_MSK	0x30000000	/* Command Opcode Mask		*/
+#define MxMR_AMx_MSK	0x07000000	/* Addess Multiplex Size Mask	*/
+#define MxMR_DSx_MSK	0x00c00000	/* Disable Timer Period Mask	*/
+#define MxMR_G0CLx_MSK	0x00380000	/* General Line 0 Control Mask	*/
+#define MxMR_GPL_x4DIS	0x00040000	/* GPL_A4 Ouput Line Disable	*/
+#define MxMR_RLFx_MSK	0x0003c000	/* Read Loop Field Mask		*/
+#define MxMR_WLFx_MSK	0x00003c00	/* Write Loop Field Mask	*/
+#define MxMR_TLFx_MSK	0x000003c0	/* Refresh Loop Field Mask	*/
+#define MxMR_MAD_MSK	0x0000003f	/* Machine Address Mask		*/
+
+#define MxMR_OP_NORM	0x00000000	/* Normal Operation		*/
+#define MxMR_OP_WARR	0x10000000	/* Write to Array		*/
+#define MxMR_OP_RARR	0x20000000	/* Read from Array		*/
+#define MxMR_OP_RUNP	0x30000000	/* Run Pattern			*/
+
+#define MxMR_AMx_TYPE_0 0x00000000	/* Addess Multiplexing Type 0	*/
+#define MxMR_AMx_TYPE_1 0x01000000	/* Addess Multiplexing Type 1	*/
+#define MxMR_AMx_TYPE_2 0x02000000	/* Addess Multiplexing Type 2	*/
+#define MxMR_AMx_TYPE_3 0x03000000	/* Addess Multiplexing Type 3	*/
+#define MxMR_AMx_TYPE_4 0x04000000	/* Addess Multiplexing Type 4	*/
+#define MxMR_AMx_TYPE_5 0x05000000	/* Addess Multiplexing Type 5	*/
+
+#define MxMR_DSx_1_CYCL 0x00000000	/* 1 cycle Disable Period	*/
+#define MxMR_DSx_2_CYCL 0x00400000	/* 2 cycle Disable Period	*/
+#define MxMR_DSx_3_CYCL 0x00800000	/* 3 cycle Disable Period	*/
+#define MxMR_DSx_4_CYCL 0x00c00000	/* 4 cycle Disable Period	*/
+
+#define MxMR_G0CLx_A12	0x00000000	/* General Line 0 : A12		*/
+#define MxMR_G0CLx_A11	0x00080000	/* General Line 0 : A11		*/
+#define MxMR_G0CLx_A10	0x00100000	/* General Line 0 : A10		*/
+#define MxMR_G0CLx_A9	0x00180000	/* General Line 0 : A9		*/
+#define MxMR_G0CLx_A8	0x00200000	/* General Line 0 : A8		*/
+#define MxMR_G0CLx_A7	0x00280000	/* General Line 0 : A7		*/
+#define MxMR_G0CLx_A6	0x00300000	/* General Line 0 : A6		*/
+#define MxMR_G0CLx_A5	0x00380000	/* General Line 0 : A5		*/
+
+#define MxMR_RLFx_1X	0x00004000	/* Read Loop is executed 1 time	*/
+#define MxMR_RLFx_2X	0x00008000	/* Read Loop is executed 2 times*/
+#define MxMR_RLFx_3X	0x0000c000	/* Read Loop is executed 3 times*/
+#define MxMR_RLFx_4X	0x00010000	/* Read Loop is executed 4 times*/
+#define MxMR_RLFx_5X	0x00014000	/* Read Loop is executed 5 times*/
+#define MxMR_RLFx_6X	0x00018000	/* Read Loop is executed 6 times*/
+#define MxMR_RLFx_7X	0x0001c000	/* Read Loop is executed 7 times*/
+#define MxMR_RLFx_8X	0x00020000	/* Read Loop is executed 8 times*/
+#define MxMR_RLFx_9X	0x00024000	/* Read Loop is executed 9 times*/
+#define MxMR_RLFx_10X	0x00028000	/* Read Loop is executed 10 times*/
+#define MxMR_RLFx_11X	0x0002c000	/* Read Loop is executed 11 times*/
+#define MxMR_RLFx_12X	0x00030000	/* Read Loop is executed 12 times*/
+#define MxMR_RLFx_13X	0x00034000	/* Read Loop is executed 13 times*/
+#define MxMR_RLFx_14X	0x00038000	/* Read Loop is executed 14 times*/
+#define MxMR_RLFx_15X	0x0003c000	/* Read Loop is executed 15 times*/
+#define MxMR_RLFx_16X	0x00000000	/* Read Loop is executed 16 times*/
+
+#define MxMR_WLFx_1X	0x00000400	/* Write Loop is executed 1 time*/
+#define MxMR_WLFx_2X	0x00000800	/* Write Loop is executed 2 times*/
+#define MxMR_WLFx_3X	0x00000c00	/* Write Loop is executed 3 times*/
+#define MxMR_WLFx_4X	0x00001000	/* Write Loop is executed 4 times*/
+#define MxMR_WLFx_5X	0x00001400	/* Write Loop is executed 5 times*/
+#define MxMR_WLFx_6X	0x00001800	/* Write Loop is executed 6 times*/
+#define MxMR_WLFx_7X	0x00001c00	/* Write Loop is executed 7 times*/
+#define MxMR_WLFx_8X	0x00002000	/* Write Loop is executed 8 times*/
+#define MxMR_WLFx_9X	0x00002400	/* Write Loop is executed 9 times*/
+#define MxMR_WLFx_10X	0x00002800	/* Write Loop is executed 10 times*/
+#define MxMR_WLFx_11X	0x00002c00	/* Write Loop is executed 11 times*/
+#define MxMR_WLFx_12X	0x00003000	/* Write Loop is executed 12 times*/
+#define MxMR_WLFx_13X	0x00003400	/* Write Loop is executed 13 times*/
+#define MxMR_WLFx_14X	0x00003800	/* Write Loop is executed 14 times*/
+#define MxMR_WLFx_15X	0x00003c00	/* Write Loop is executed 15 times*/
+#define MxMR_WLFx_16X	0x00000000	/* Write Loop is executed 16 times*/
+
+#define MxMR_TLFx_1X	0x00000040	/* Timer Loop is executed 1 time*/
+#define MxMR_TLFx_2X	0x00000080	/* Timer Loop is executed 2 times*/
+#define MxMR_TLFx_3X	0x000000c0	/* Timer Loop is executed 3 times*/
+#define MxMR_TLFx_4X	0x00000100	/* Timer Loop is executed 4 times*/
+#define MxMR_TLFx_5X	0x00000140	/* Timer Loop is executed 5 times*/
+#define MxMR_TLFx_6X	0x00000180	/* Timer Loop is executed 6 times*/
+#define MxMR_TLFx_7X	0x000001c0	/* Timer Loop is executed 7 times*/
+#define MxMR_TLFx_8X	0x00000200	/* Timer Loop is executed 8 times*/
+#define MxMR_TLFx_9X	0x00000240	/* Timer Loop is executed 9 times*/
+#define MxMR_TLFx_10X	0x00000280	/* Timer Loop is executed 10 times*/
+#define MxMR_TLFx_11X	0x000002c0	/* Timer Loop is executed 11 times*/
+#define MxMR_TLFx_12X	0x00000300	/* Timer Loop is executed 12 times*/
+#define MxMR_TLFx_13X	0x00000340	/* Timer Loop is executed 13 times*/
+#define MxMR_TLFx_14X	0x00000380	/* Timer Loop is executed 14 times*/
+#define MxMR_TLFx_15X	0x000003c0	/* Timer Loop is executed 15 times*/
+#define MxMR_TLFx_16X	0x00000000	/* Timer Loop is executed 16 times*/
+
+
+/*-----------------------------------------------------------------------
+ * BRx - Memory Controller: Base Register				10-14
+ */
+#define BRx_BA_MSK	0xffff8000	/* Base Address Mask		*/
+#define BRx_PS_MSK	0x00001800	/* Port Size Mask		*/
+#define BRx_DECC_MSK	0x00000600	/* Data Error Correct+Check Mask*/
+#define BRx_WP		0x00000100	/* Write Protect		*/
+#define BRx_MS_MSK	0x000000e0	/* Machine Select Mask		*/
+#define BRx_EMEMC	0x00000010	/* External MEMC Enable		*/
+#define BRx_ATOM_MSK	0x0000000c	/* Atomic Operation Mask	*/
+#define BRx_DR		0x00000002	/* Data Pipelining		*/
+#define BRx_V		0x00000001	/* Bank Valid			*/
+
+#define BRx_PS_64	0x00000000	/* 64 bit port size (60x bus only)*/
+#define BRx_PS_8	0x00000800	/*  8 bit port size		*/
+#define BRx_PS_16	0x00001000	/* 16 bit port size		*/
+#define BRx_PS_32	0x00001800	/* 32 bit port size		*/
+
+#define BRx_DECC_NONE	0x00000000	/* Data Errors Checking Disabled*/
+#define BRx_DECC_NORMAL	0x00000200	/* Normal Parity Checking	*/
+#define BRx_DECC_RMWPC	0x00000400	/* Read-Modify-Write Parity Checking*/
+#define BRx_DECC_ECC	0x00000600	/* ECC Correction and Checking	*/
+
+#define BRx_MS_GPCM_P	0x00000000	/* G.P.C.M. 60x Bus Machine Select*/
+#define BRx_MS_GPCM_L	0x00000020	/* G.P.C.M. Local Bus Machine Select*/
+#define BRx_MS_SDRAM_P	0x00000040	/* SDRAM 60x Bus Machine Select	*/
+#define BRx_MS_SDRAM_L	0x00000060	/* SDRAM Local Bus Machine Select*/
+#define BRx_MS_UPMA	0x00000080	/* U.P.M.A Machine Select	*/
+#define BRx_MS_UPMB	0x000000a0	/* U.P.M.B Machine Select	*/
+#define BRx_MS_UPMC	0x000000c0	/* U.P.M.C Machine Select	*/
+
+#define BRx_ATOM_RAWA	0x00000004	/* Read-After-Write-Atomic	*/
+#define BRx_ATOM_WARA	0x00000008	/* Write-After-Read-Atomic	*/
+
+/*-----------------------------------------------------------------------
+ * ORx - Memory Controller: Option Register - SDRAM Mode		10-16
+ */
+#define ORxS_SDAM_MSK	0xfff00000	/* SDRAM Address Mask Mask	*/
+#define ORxS_LSDAM_MSK	0x000f8000	/* Lower SDRAM Address Mask Mask*/
+#define ORxS_BPD_MSK	0x00006000	/* Banks Per Device Mask	*/
+#define ORxS_ROWST_MSK	0x00001e00	/* Row Start Address Bit Mask	*/
+#define ORxS_NUMR_MSK	0x000001c0	/* Number of Row Addr Lines Mask*/
+#define ORxS_PMSEL	0x00000020	/* Page Mode Select		*/
+#define ORxS_IBID	0x00000010	/* Internal Bank Interleaving Disable*/
+
+#define ORxS_BPD_2	0x00000000	/* 2 Banks Per Device		*/
+#define ORxS_BPD_4	0x00002000	/* 4 Banks Per Device		*/
+#define ORxS_BPD_8	0x00004000	/* 8 Banks Per Device		*/
+
+/* ROWST values for xSDMR[PBI] = 0 */
+#define ORxS_ROWST_PBI0_A7  0x00000400	/* Row Start Address Bit is A7	*/
+#define ORxS_ROWST_PBI0_A8  0x00000800	/* Row Start Address Bit is A8	*/
+#define ORxS_ROWST_PBI0_A9  0x00000c00	/* Row Start Address Bit is A9	*/
+#define ORxS_ROWST_PBI0_A10 0x00001000	/* Row Start Address Bit is A10	*/
+#define ORxS_ROWST_PBI0_A11 0x00001400	/* Row Start Address Bit is A11	*/
+#define ORxS_ROWST_PBI0_A12 0x00001800	/* Row Start Address Bit is A12	*/
+#define ORxS_ROWST_PBI0_A13 0x00001c00	/* Row Start Address Bit is A13	*/
+
+/* ROWST values for xSDMR[PBI] = 1 */
+#define ORxS_ROWST_PBI1_A0  0x00000000	/* Row Start Address Bit is A0	*/
+#define ORxS_ROWST_PBI1_A1  0x00000200	/* Row Start Address Bit is A1	*/
+#define ORxS_ROWST_PBI1_A2  0x00000400	/* Row Start Address Bit is A2	*/
+#define ORxS_ROWST_PBI1_A3  0x00000600	/* Row Start Address Bit is A3	*/
+#define ORxS_ROWST_PBI1_A4  0x00000800	/* Row Start Address Bit is A4	*/
+#define ORxS_ROWST_PBI1_A5  0x00000a00	/* Row Start Address Bit is A5	*/
+#define ORxS_ROWST_PBI1_A6  0x00000c00	/* Row Start Address Bit is A6	*/
+#define ORxS_ROWST_PBI1_A7  0x00000e00	/* Row Start Address Bit is A7	*/
+#define ORxS_ROWST_PBI1_A8  0x00001000	/* Row Start Address Bit is A8	*/
+#define ORxS_ROWST_PBI1_A9  0x00001200	/* Row Start Address Bit is A9	*/
+#define ORxS_ROWST_PBI1_A10 0x00001400	/* Row Start Address Bit is A10	*/
+#define ORxS_ROWST_PBI1_A11 0x00001600	/* Row Start Address Bit is A11	*/
+#define ORxS_ROWST_PBI1_A12 0x00001800	/* Row Start Address Bit is A12	*/
+
+#define ORxS_NUMR_9	0x00000000	/*  9 Row Address Lines		*/
+#define ORxS_NUMR_10	0x00000040	/* 10 Row Address Lines		*/
+#define ORxS_NUMR_11	0x00000080	/* 11 Row Address Lines		*/
+#define ORxS_NUMR_12	0x000000c0	/* 12 Row Address Lines		*/
+#define ORxS_NUMR_13	0x00000100	/* 13 Row Address Lines		*/
+#define ORxS_NUMR_14	0x00000140	/* 14 Row Address Lines		*/
+#define ORxS_NUMR_15	0x00000180	/* 15 Row Address Lines		*/
+#define ORxS_NUMR_16	0x000001c0	/* 16 Row Address Lines		*/
+
+/* helper to determine the AM for a given size (SDRAM mode) */
+#define ORxS_SIZE_TO_AM(s) ((~((s) - 1)) & 0xffff8000)	/* must be pow of 2 */
+
+/*-----------------------------------------------------------------------
+ * ORx - Memory Controller: Option Register - GPCM Mode			10-18
+ */
+#define ORxG_AM_MSK	0xffff8000	/* Address Mask Mask		*/
+#define ORxG_BCTLD	0x00001000	/* Data Buffer Control Disable	*/
+#define ORxG_CSNT	0x00000800	/* Chip Select Negation Time	*/
+#define ORxG_ACS_MSK	0x00000600	/* Address to Chip Select Setup mask*/
+#define ORxG_SCY_MSK	0x000000f0	/* Cycle Lenght in Clocks	*/
+#define ORxG_SETA	0x00000008	/* External Access Termination	*/
+#define ORxG_TRLX	0x00000004	/* Timing Relaxed		*/
+#define ORxG_EHTR	0x00000002	/* Extended Hold Time on Read	*/
+
+#define ORxG_ACS_DIV1	0x00000000	/* CS is output at the same time*/
+#define ORxG_ACS_DIV4	0x00000400	/* CS is output 1/4 a clock later*/
+#define ORxG_ACS_DIV2	0x00000600	/* CS is output 1/2 a clock later*/
+
+#define ORxG_SCY_0_CLK	0x00000000	/*  0 clock cycles wait states	*/
+#define ORxG_SCY_1_CLK	0x00000010	/*  1 clock cycles wait states	*/
+#define ORxG_SCY_2_CLK	0x00000020	/*  2 clock cycles wait states	*/
+#define ORxG_SCY_3_CLK	0x00000030	/*  3 clock cycles wait states	*/
+#define ORxG_SCY_4_CLK	0x00000040	/*  4 clock cycles wait states	*/
+#define ORxG_SCY_5_CLK	0x00000050	/*  5 clock cycles wait states	*/
+#define ORxG_SCY_6_CLK	0x00000060	/*  6 clock cycles wait states	*/
+#define ORxG_SCY_7_CLK	0x00000070	/*  7 clock cycles wait states	*/
+#define ORxG_SCY_8_CLK	0x00000080	/*  8 clock cycles wait states	*/
+#define ORxG_SCY_9_CLK	0x00000090	/*  9 clock cycles wait states	*/
+#define ORxG_SCY_10_CLK	0x000000a0	/* 10 clock cycles wait states	*/
+#define ORxG_SCY_11_CLK	0x000000b0	/* 11 clock cycles wait states	*/
+#define ORxG_SCY_12_CLK	0x000000c0	/* 12 clock cycles wait states	*/
+#define ORxG_SCY_13_CLK	0x000000d0	/* 13 clock cycles wait states	*/
+#define ORxG_SCY_14_CLK	0x000000e0	/* 14 clock cycles wait states	*/
+#define ORxG_SCY_15_CLK	0x000000f0	/* 15 clock cycles wait states	*/
+
+/*-----------------------------------------------------------------------
+ * ORx - Memory Controller: Option Register - UPM Mode			10-20
+ */
+#define ORxU_AM_MSK	0xffff8000	/* Address Mask Mask		*/
+#define ORxU_BCTLD	0x00001000	/* Data Buffer Control Disable	*/
+#define ORxU_BI		0x00000100	/* Burst Inhibit		*/
+#define ORxU_EHTR_MSK	0x00000006	/* Extended Hold Time on Read Mask*/
+
+#define ORxU_EHTR_NORM	0x00000000	/* Normal Timing		*/
+#define ORxU_EHTR_1IDLE	0x00000002	/* One Idle Clock Cycle Inserted*/
+#define ORxU_EHTR_4IDLE	0x00000004	/* Four Idle Clock Cycles Inserted*/
+#define ORxU_EHTR_8IDLE	0x00000006	/* Eight Idle Clock Cycles Inserted*/
+
+
+/* helpers to convert values into an OR address mask (GPCM mode) */
+#define P2SZ_TO_AM(s)	((~((s) - 1)) & 0xffff8000)	/* must be pow of 2 */
+#define MEG_TO_AM(m)	P2SZ_TO_AM((m) << 20)
+
+
+/*-----------------------------------------------------------------------
+ * PSDMR - 60x SDRAM Mode Register					10-21
+ */
+#define PSDMR_PBI	     0x80000000	/* Page-based Interleaving	*/
+#define PSDMR_RFEN	     0x40000000	/* Refresh Enable		*/
+#define PSDMR_OP_MSK	     0x38000000	/* SDRAM Operation Mask		*/
+#define PSDMR_SDAM_MSK	     0x07000000	/* SDRAM Address Multiplex Mask	*/
+#define PSDMR_BSMA_MSK	     0x00e00000	/* Bank Select Muxd Addr Line Mask*/
+#define PSDMR_SDA10_MSK	     0x001c0000	/* A10 Control Mask		*/
+#define PSDMR_RFRC_MSK	     0x00038000	/* Refresh Recovery Mask	*/
+#define PSDMR_PRETOACT_MSK   0x00007000	/* Precharge to Activate Intvl Mask*/
+#define PSDMR_ACTTORW_MSK    0x00000e00	/* Activate to Read/Write Intvl Mask*/
+#define PSDMR_BL	     0x00000100	/* Burst Length			*/
+#define PSDMR_LDOTOPRE_MSK   0x000000c0	/* Last Data Out to Precharge Mask*/
+#define PSDMR_WRC_MSK	     0x00000030	/* Write Recovery Time Mask	*/
+#define PSDMR_EAMUX	     0x00000008	/* External Address Multiplexing*/
+#define PSDMR_BUFCMD	     0x00000004	/* SDRAM ctl lines asrtd for 2 cycles*/
+#define PSDMR_CL_MSK	     0x00000003	/* CAS Latency Mask		*/
+
+#define PSDMR_OP_NORM	     0x00000000	/* Normal Operation		*/
+#define PSDMR_OP_CBRR	     0x08000000	/* CBR Refresh			*/
+#define PSDMR_OP_SELFR	     0x10000000	/* Self Refresh			*/
+#define PSDMR_OP_MRW	     0x18000000	/* Mode Register Write		*/
+#define PSDMR_OP_PREB	     0x20000000	/* Precharge Bank		*/
+#define PSDMR_OP_PREA	     0x28000000	/* Precharge All Banks		*/
+#define PSDMR_OP_ACTB	     0x30000000	/* Activate Bank		*/
+#define PSDMR_OP_RW	     0x38000000	/* Read/Write			*/
+
+#define PSDMR_SDAM_A13_IS_A5 0x00000000	/* SDRAM Address Multiplex A13 is A5 */
+#define PSDMR_SDAM_A14_IS_A5 0x01000000	/* SDRAM Address Multiplex A14 is A5 */
+#define PSDMR_SDAM_A15_IS_A5 0x02000000	/* SDRAM Address Multiplex A15 is A5 */
+#define PSDMR_SDAM_A16_IS_A5 0x03000000	/* SDRAM Address Multiplex A16 is A5 */
+#define PSDMR_SDAM_A17_IS_A5 0x04000000	/* SDRAM Address Multiplex A17 is A5 */
+#define PSDMR_SDAM_A18_IS_A5 0x05000000	/* SDRAM Address Multiplex A18 is A5 */
+
+#define PSDMR_BSMA_A12_A14   0x00000000	/* A12 - A14			*/
+#define PSDMR_BSMA_A13_A15   0x00200000	/* A13 - A15			*/
+#define PSDMR_BSMA_A14_A16   0x00400000	/* A14 - A16			*/
+#define PSDMR_BSMA_A15_A17   0x00600000	/* A15 - A17			*/
+#define PSDMR_BSMA_A16_A18   0x00800000	/* A16 - A18			*/
+#define PSDMR_BSMA_A17_A19   0x00a00000	/* A17 - A19			*/
+#define PSDMR_BSMA_A18_A20   0x00c00000	/* A18 - A20			*/
+#define PSDMR_BSMA_A19_A21   0x00e00000	/* A19 - A21			*/
+
+/* SDA10 values for xSDMR[PBI] = 0 */
+#define PSDMR_SDA10_PBI0_A12 0x00000000	/* "A10" Control is A12		*/
+#define PSDMR_SDA10_PBI0_A11 0x00040000	/* "A10" Control is A11		*/
+#define PSDMR_SDA10_PBI0_A10 0x00080000	/* "A10" Control is A10		*/
+#define PSDMR_SDA10_PBI0_A9  0x000c0000	/* "A10" Control is A9		*/
+#define PSDMR_SDA10_PBI0_A8  0x00100000	/* "A10" Control is A8		*/
+#define PSDMR_SDA10_PBI0_A7  0x00140000	/* "A10" Control is A7		*/
+#define PSDMR_SDA10_PBI0_A6  0x00180000	/* "A10" Control is A6		*/
+#define PSDMR_SDA10_PBI0_A5  0x001c0000	/* "A10" Control is A5		*/
+
+/* SDA10 values for xSDMR[PBI] = 1 */
+#define PSDMR_SDA10_PBI1_A10 0x00000000	/* "A10" Control is A10		*/
+#define PSDMR_SDA10_PBI1_A9  0x00040000	/* "A10" Control is A9		*/
+#define PSDMR_SDA10_PBI1_A8  0x00080000	/* "A10" Control is A8		*/
+#define PSDMR_SDA10_PBI1_A7  0x000c0000	/* "A10" Control is A7		*/
+#define PSDMR_SDA10_PBI1_A6  0x00100000	/* "A10" Control is A6		*/
+#define PSDMR_SDA10_PBI1_A5  0x00140000	/* "A10" Control is A5		*/
+#define PSDMR_SDA10_PBI1_A4  0x00180000	/* "A10" Control is A4		*/
+#define PSDMR_SDA10_PBI1_A3  0x001c0000	/* "A10" Control is A3		*/
+
+#define PSDMR_RFRC_3_CLK     0x00008000	/*  3 Clocks			*/
+#define PSDMR_RFRC_4_CLK     0x00010000	/*  4 Clocks			*/
+#define PSDMR_RFRC_5_CLK     0x00018000	/*  5 Clocks			*/
+#define PSDMR_RFRC_6_CLK     0x00020000	/*  6 Clocks			*/
+#define PSDMR_RFRC_7_CLK     0x00028000	/*  7 Clocks			*/
+#define PSDMR_RFRC_8_CLK     0x00030000	/*  8 Clocks			*/
+#define PSDMR_RFRC_16_CLK    0x00038000	/* 16 Clocks			*/
+
+#define PSDMR_PRETOACT_8W    0x00000000	/* 8 Clock-cycle Wait States	*/
+#define PSDMR_PRETOACT_1W    0x00001000	/* 1 Clock-cycle Wait States	*/
+#define PSDMR_PRETOACT_2W    0x00002000	/* 2 Clock-cycle Wait States	*/
+#define PSDMR_PRETOACT_3W    0x00003000	/* 3 Clock-cycle Wait States	*/
+#define PSDMR_PRETOACT_4W    0x00004000	/* 4 Clock-cycle Wait States	*/
+#define PSDMR_PRETOACT_5W    0x00005000	/* 5 Clock-cycle Wait States	*/
+#define PSDMR_PRETOACT_6W    0x00006000	/* 6 Clock-cycle Wait States	*/
+#define PSDMR_PRETOACT_7W    0x00007000	/* 7 Clock-cycle Wait States	*/
+
+#define PSDMR_ACTTORW_8W     0x00000000	/* 8 Clock-cycle Wait States	*/
+#define PSDMR_ACTTORW_1W     0x00000200	/* 1 Clock-cycle Wait States	*/
+#define PSDMR_ACTTORW_2W     0x00000400	/* 2 Clock-cycle Wait States	*/
+#define PSDMR_ACTTORW_3W     0x00000600	/* 3 Clock-cycle Wait States	*/
+#define PSDMR_ACTTORW_4W     0x00000800	/* 4 Clock-cycle Wait States	*/
+#define PSDMR_ACTTORW_5W     0x00000a00	/* 5 Clock-cycle Wait States	*/
+#define PSDMR_ACTTORW_6W     0x00000c00	/* 6 Clock-cycle Wait States	*/
+#define PSDMR_ACTTORW_7W     0x00000e00	/* 7 Clock-cycle Wait States	*/
+
+#define PSDMR_LDOTOPRE_0C    0x00000000	/* 0 Clock Cycles		*/
+#define PSDMR_LDOTOPRE_1C    0x00000040	/* 1 Clock Cycles		*/
+#define PSDMR_LDOTOPRE_2C    0x00000080	/* 2 Clock Cycles		*/
+
+#define PSDMR_WRC_4C	     0x00000000	/* 4 Clock Cycles		*/
+#define PSDMR_WRC_1C	     0x00000010	/* 1 Clock Cycles		*/
+#define PSDMR_WRC_2C	     0x00000020	/* 2 Clock Cycles		*/
+#define PSDMR_WRC_3C	     0x00000030	/* 3 Clock Cycles		*/
+
+#define PSDMR_CL_1	     0x00000001	/* CAS Latency = 1		*/
+#define PSDMR_CL_2	     0x00000002	/* CAS Latency = 2		*/
+#define PSDMR_CL_3	     0x00000003	/* CAS Latency = 3		*/
+
+/*-----------------------------------------------------------------------
+ * LSDMR - Local Bus SDRAM Mode Register				10-24
+ */
+
+/*
+ * No definitions here - the LSDMR has the same fields as the PSDMR.
+ */
+
+/*-----------------------------------------------------------------------
+ * MPTPR - Memory Refresh Timer Prescaler Register			10-32
+ * See User's Manual Errata for the changed definition (matches the
+ * 8xx now).  The wrong prescaler definition causes excessive refreshes
+ * (typically "divide by 2" when "divide by 32" is intended) which will
+ * cause unnecessary memory subsystem slowdown.
+ */
+#define MPTPR_PTP_MSK	0xff00		/* Periodic Timers Prescaler Mask */
+#define MPTPR_PTP_DIV2	0x2000		/* BRGCLK divided by 2		*/
+#define MPTPR_PTP_DIV4	0x1000		/* BRGCLK divided by 4		*/
+#define MPTPR_PTP_DIV8	0x0800		/* BRGCLK divided by 8		*/
+#define MPTPR_PTP_DIV16	0x0400		/* BRGCLK divided by 16		*/
+#define MPTPR_PTP_DIV32	0x0200		/* BRGCLK divided by 32		*/
+#define MPTPR_PTP_DIV64	0x0100		/* BRGCLK divided by 64		*/
+
+
+/*-----------------------------------------------------------------------
+ * TGCR1/TGCR2 - Timer Global Configuration Registers			17-4
+ */
+#define TGCR1_CAS2	0x80		/* Cascade Timer 1 and 2	*/
+#define TGCR1_STP2	0x20		/* Stop timer   2		*/
+#define TGCR1_RST2	0x10		/* Reset timer  2		*/
+#define TGCR1_GM1	0x08		/* Gate Mode for Pin 1		*/
+#define TGCR1_STP1	0x02		/* Stop timer   1		*/
+#define TGCR1_RST1	0x01		/* Reset timer  1		*/
+#define TGCR2_CAS4	0x80		/* Cascade Timer 3 and 4	*/
+#define TGCR2_STP4	0x20		/* Stop timer   4		*/
+#define TGCR2_RST4	0x10		/* Reset timer  4		*/
+#define TGCR2_GM2	0x08		/* Gate Mode for Pin 2		*/
+#define TGCR2_STP3	0x02		/* Stop timer   3		*/
+#define TGCR2_RST3	0x01		/* Reset timer  3		*/
+
+
+/*-----------------------------------------------------------------------
+ * TMR1-TMR4 - Timer Mode Registers					17-6
+ */
+#define TMRx_PS_MSK		0xff00	/* Prescaler Value		*/
+#define TMRx_CE_MSK		0x00c0	/* Capture Edge and Enable Interrupt*/
+#define TMRx_OM			0x0020	/* Output Mode			*/
+#define TMRx_ORI		0x0010	/* Output Reference Interrupt Enable*/
+#define TMRx_FRR		0x0008	/* Free Run/Restart		*/
+#define TMRx_ICLK_MSK		0x0006	/* Timer Input Clock Source mask */
+#define TMRx_GE			0x0001	/* Gate Enable			*/
+
+#define TMRx_CE_INTR_DIS	0x0000	/* Disable Interrupt on capture event*/
+#define TMRx_CE_RISING		0x0040	/* Capture on Rising TINx edge only */
+#define TMRx_CE_FALLING		0x0080	/* Capture on Falling TINx edge only */
+#define TMRx_CE_ANY		0x00c0	/* Capture on any TINx edge	*/
+
+#define TMRx_ICLK_IN_CAS	0x0000	/* Internally cascaded input	*/
+#define TMRx_ICLK_IN_GEN	0x0002	/* Internal General system clock*/
+#define TMRx_ICLK_IN_GEN_DIV16	0x0004	/* Internal General system clk div 16*/
+#define TMRx_ICLK_TIN_PIN	0x0006	/* TINx pin			*/
+
+
+/*-----------------------------------------------------------------------
+ * CMXFCR - CMX FCC Clock Route Register				15-12
+ */
+#define CMXFCR_FC1	   0x40000000	/* FCC1 connection		*/
+#define CMXFCR_RF1CS_MSK   0x38000000	/* Receive FCC1 Clock Source Mask */
+#define CMXFCR_TF1CS_MSK   0x07000000	/* Transmit FCC1 Clock Source Mask */
+#define CMXFCR_FC2	   0x00400000	/* FCC2 connection		*/
+#define CMXFCR_RF2CS_MSK   0x00380000	/* Receive FCC2 Clock Source Mask */
+#define CMXFCR_TF2CS_MSK   0x00070000	/* Transmit FCC2 Clock Source Mask */
+#define CMXFCR_FC3	   0x00004000	/* FCC3 connection		*/
+#define CMXFCR_RF3CS_MSK   0x00003800	/* Receive FCC3 Clock Source Mask */
+#define CMXFCR_TF3CS_MSK   0x00000700	/* Transmit FCC3 Clock Source Mask */
+
+#define CMXFCR_RF1CS_BRG5  0x00000000	/* Receive FCC1 Clock Source is BRG5 */
+#define CMXFCR_RF1CS_BRG6  0x08000000	/* Receive FCC1 Clock Source is BRG6 */
+#define CMXFCR_RF1CS_BRG7  0x10000000	/* Receive FCC1 Clock Source is BRG7 */
+#define CMXFCR_RF1CS_BRG8  0x18000000	/* Receive FCC1 Clock Source is BRG8 */
+#define CMXFCR_RF1CS_CLK9  0x20000000	/* Receive FCC1 Clock Source is CLK9 */
+#define CMXFCR_RF1CS_CLK10 0x28000000	/* Receive FCC1 Clock Source is CLK10 */
+#define CMXFCR_RF1CS_CLK11 0x30000000	/* Receive FCC1 Clock Source is CLK11 */
+#define CMXFCR_RF1CS_CLK12 0x38000000	/* Receive FCC1 Clock Source is CLK12 */
+
+#define CMXFCR_TF1CS_BRG5  0x00000000	/* Transmit FCC1 Clock Source is BRG5 */
+#define CMXFCR_TF1CS_BRG6  0x01000000	/* Transmit FCC1 Clock Source is BRG6 */
+#define CMXFCR_TF1CS_BRG7  0x02000000	/* Transmit FCC1 Clock Source is BRG7 */
+#define CMXFCR_TF1CS_BRG8  0x03000000	/* Transmit FCC1 Clock Source is BRG8 */
+#define CMXFCR_TF1CS_CLK9  0x04000000	/* Transmit FCC1 Clock Source is CLK9 */
+#define CMXFCR_TF1CS_CLK10 0x05000000	/* Transmit FCC1 Clock Source is CLK10 */
+#define CMXFCR_TF1CS_CLK11 0x06000000	/* Transmit FCC1 Clock Source is CLK11 */
+#define CMXFCR_TF1CS_CLK12 0x07000000	/* Transmit FCC1 Clock Source is CLK12 */
+
+#define CMXFCR_RF2CS_BRG5  0x00000000	/* Receive FCC2 Clock Source is BRG5 */
+#define CMXFCR_RF2CS_BRG6  0x00080000	/* Receive FCC2 Clock Source is BRG6 */
+#define CMXFCR_RF2CS_BRG7  0x00100000	/* Receive FCC2 Clock Source is BRG7 */
+#define CMXFCR_RF2CS_BRG8  0x00180000	/* Receive FCC2 Clock Source is BRG8 */
+#define CMXFCR_RF2CS_CLK13 0x00200000	/* Receive FCC2 Clock Source is CLK13 */
+#define CMXFCR_RF2CS_CLK14 0x00280000	/* Receive FCC2 Clock Source is CLK14 */
+#define CMXFCR_RF2CS_CLK15 0x00300000	/* Receive FCC2 Clock Source is CLK15 */
+#define CMXFCR_RF2CS_CLK16 0x00380000	/* Receive FCC2 Clock Source is CLK16 */
+
+#define CMXFCR_TF2CS_BRG5  0x00000000	/* Transmit FCC2 Clock Source is BRG5 */
+#define CMXFCR_TF2CS_BRG6  0x00010000	/* Transmit FCC2 Clock Source is BRG6 */
+#define CMXFCR_TF2CS_BRG7  0x00020000	/* Transmit FCC2 Clock Source is BRG7 */
+#define CMXFCR_TF2CS_BRG8  0x00030000	/* Transmit FCC2 Clock Source is BRG8 */
+#define CMXFCR_TF2CS_CLK13 0x00040000	/* Transmit FCC2 Clock Source is CLK13 */
+#define CMXFCR_TF2CS_CLK14 0x00050000	/* Transmit FCC2 Clock Source is CLK14 */
+#define CMXFCR_TF2CS_CLK15 0x00060000	/* Transmit FCC2 Clock Source is CLK15 */
+#define CMXFCR_TF2CS_CLK16 0x00070000	/* Transmit FCC2 Clock Source is CLK16 */
+
+#define CMXFCR_RF3CS_BRG5  0x00000000	/* Receive FCC3 Clock Source is BRG5 */
+#define CMXFCR_RF3CS_BRG6  0x00000800	/* Receive FCC3 Clock Source is BRG6 */
+#define CMXFCR_RF3CS_BRG7  0x00001000	/* Receive FCC3 Clock Source is BRG7 */
+#define CMXFCR_RF3CS_BRG8  0x00001800	/* Receive FCC3 Clock Source is BRG8 */
+#define CMXFCR_RF3CS_CLK13 0x00002000	/* Receive FCC3 Clock Source is CLK13 */
+#define CMXFCR_RF3CS_CLK14 0x00002800	/* Receive FCC3 Clock Source is CLK14 */
+#define CMXFCR_RF3CS_CLK15 0x00003000	/* Receive FCC3 Clock Source is CLK15 */
+#define CMXFCR_RF3CS_CLK16 0x00003800	/* Receive FCC3 Clock Source is CLK16 */
+
+#define CMXFCR_TF3CS_BRG5  0x00000000	/* Transmit FCC3 Clock Source is BRG5 */
+#define CMXFCR_TF3CS_BRG6  0x00000100	/* Transmit FCC3 Clock Source is BRG6 */
+#define CMXFCR_TF3CS_BRG7  0x00000200	/* Transmit FCC3 Clock Source is BRG7 */
+#define CMXFCR_TF3CS_BRG8  0x00000300	/* Transmit FCC3 Clock Source is BRG8 */
+#define CMXFCR_TF3CS_CLK13 0x00000400	/* Transmit FCC3 Clock Source is CLK13 */
+#define CMXFCR_TF3CS_CLK14 0x00000500	/* Transmit FCC3 Clock Source is CLK14 */
+#define CMXFCR_TF3CS_CLK15 0x00000600	/* Transmit FCC3 Clock Source is CLK15 */
+#define CMXFCR_TF3CS_CLK16 0x00000700	/* Transmit FCC3 Clock Source is CLK16 */
+
+/*-----------------------------------------------------------------------
+ * CMXSCR - CMX SCC Clock Route Register				15-14
+ */
+#define CMXSCR_GR1	   0x80000000	/* Grant Support of SCC1	*/
+#define CMXSCR_SC1	   0x40000000	/* SCC1 connection		*/
+#define CMXSCR_RS1CS_MSK   0x38000000	/* Receive SCC1 Clock Source Mask */
+#define CMXSCR_TS1CS_MSK   0x07000000	/* Transmit SCC1 Clock Source Mask */
+#define CMXSCR_GR2	   0x00800000	/* Grant Support of SCC2	*/
+#define CMXSCR_SC2	   0x00400000	/* SCC2 connection		*/
+#define CMXSCR_RS2CS_MSK   0x00380000	/* Receive SCC2 Clock Source Mask */
+#define CMXSCR_TS2CS_MSK   0x00070000	/* Transmit SCC2 Clock Source Mask */
+#define CMXSCR_GR3	   0x00008000	/* Grant Support of SCC3	*/
+#define CMXSCR_SC3	   0x00004000	/* SCC3 connection		*/
+#define CMXSCR_RS3CS_MSK   0x00003800	/* Receive SCC3 Clock Source Mask */
+#define CMXSCR_TS3CS_MSK   0x00000700	/* Transmit SCC3 Clock Source Mask */
+#define CMXSCR_GR4	   0x00000080	/* Grant Support of SCC4	*/
+#define CMXSCR_SC4	   0x00000040	/* SCC4 connection		*/
+#define CMXSCR_RS4CS_MSK   0x00000038	/* Receive SCC4 Clock Source Mask */
+#define CMXSCR_TS4CS_MSK   0x00000007	/* Transmit SCC4 Clock Source Mask */
+
+#define CMXSCR_RS1CS_BRG1  0x00000000	/* SCC1 Rx Clock Source is BRG1 */
+#define CMXSCR_RS1CS_BRG2  0x08000000	/* SCC1 Rx Clock Source is BRG2 */
+#define CMXSCR_RS1CS_BRG3  0x10000000	/* SCC1 Rx Clock Source is BRG3 */
+#define CMXSCR_RS1CS_BRG4  0x18000000	/* SCC1 Rx Clock Source is BRG4 */
+#define CMXSCR_RS1CS_CLK11 0x20000000	/* SCC1 Rx Clock Source is CLK11 */
+#define CMXSCR_RS1CS_CLK12 0x28000000	/* SCC1 Rx Clock Source is CLK12 */
+#define CMXSCR_RS1CS_CLK3  0x30000000	/* SCC1 Rx Clock Source is CLK3 */
+#define CMXSCR_RS1CS_CLK4  0x38000000	/* SCC1 Rx Clock Source is CLK4 */
+
+#define CMXSCR_TS1CS_BRG1  0x00000000	/* SCC1 Tx Clock Source is BRG1 */
+#define CMXSCR_TS1CS_BRG2  0x01000000	/* SCC1 Tx Clock Source is BRG2 */
+#define CMXSCR_TS1CS_BRG3  0x02000000	/* SCC1 Tx Clock Source is BRG3 */
+#define CMXSCR_TS1CS_BRG4  0x03000000	/* SCC1 Tx Clock Source is BRG4 */
+#define CMXSCR_TS1CS_CLK11 0x04000000	/* SCC1 Tx Clock Source is CLK11 */
+#define CMXSCR_TS1CS_CLK12 0x05000000	/* SCC1 Tx Clock Source is CLK12 */
+#define CMXSCR_TS1CS_CLK3  0x06000000	/* SCC1 Tx Clock Source is CLK3 */
+#define CMXSCR_TS1CS_CLK4  0x07000000	/* SCC1 Tx Clock Source is CLK4 */
+
+#define CMXSCR_RS2CS_BRG1  0x00000000	/* SCC2 Rx Clock Source is BRG1 */
+#define CMXSCR_RS2CS_BRG2  0x00080000	/* SCC2 Rx Clock Source is BRG2 */
+#define CMXSCR_RS2CS_BRG3  0x00100000	/* SCC2 Rx Clock Source is BRG3 */
+#define CMXSCR_RS2CS_BRG4  0x00180000	/* SCC2 Rx Clock Source is BRG4 */
+#define CMXSCR_RS2CS_CLK11 0x00200000	/* SCC2 Rx Clock Source is CLK11 */
+#define CMXSCR_RS2CS_CLK12 0x00280000	/* SCC2 Rx Clock Source is CLK12 */
+#define CMXSCR_RS2CS_CLK3  0x00300000	/* SCC2 Rx Clock Source is CLK3 */
+#define CMXSCR_RS2CS_CLK4  0x00380000	/* SCC2 Rx Clock Source is CLK4 */
+
+#define CMXSCR_TS2CS_BRG1  0x00000000	/* SCC2 Tx Clock Source is BRG1 */
+#define CMXSCR_TS2CS_BRG2  0x00010000	/* SCC2 Tx Clock Source is BRG2 */
+#define CMXSCR_TS2CS_BRG3  0x00020000	/* SCC2 Tx Clock Source is BRG3 */
+#define CMXSCR_TS2CS_BRG4  0x00030000	/* SCC2 Tx Clock Source is BRG4 */
+#define CMXSCR_TS2CS_CLK11 0x00040000	/* SCC2 Tx Clock Source is CLK11 */
+#define CMXSCR_TS2CS_CLK12 0x00050000	/* SCC2 Tx Clock Source is CLK12 */
+#define CMXSCR_TS2CS_CLK3  0x00060000	/* SCC2 Tx Clock Source is CLK3 */
+#define CMXSCR_TS2CS_CLK4  0x00070000	/* SCC2 Tx Clock Source is CLK4 */
+
+#define CMXSCR_RS3CS_BRG1  0x00000000	/* SCC3 Rx Clock Source is BRG1 */
+#define CMXSCR_RS3CS_BRG2  0x00000800	/* SCC3 Rx Clock Source is BRG2 */
+#define CMXSCR_RS3CS_BRG3  0x00001000	/* SCC3 Rx Clock Source is BRG3 */
+#define CMXSCR_RS3CS_BRG4  0x00001800	/* SCC3 Rx Clock Source is BRG4 */
+#define CMXSCR_RS3CS_CLK5  0x00002000	/* SCC3 Rx Clock Source is CLK5 */
+#define CMXSCR_RS3CS_CLK6  0x00002800	/* SCC3 Rx Clock Source is CLK6 */
+#define CMXSCR_RS3CS_CLK7  0x00003000	/* SCC3 Rx Clock Source is CLK7 */
+#define CMXSCR_RS3CS_CLK8  0x00003800	/* SCC3 Rx Clock Source is CLK8 */
+
+#define CMXSCR_TS3CS_BRG1  0x00000000	/* SCC3 Tx Clock Source is BRG1 */
+#define CMXSCR_TS3CS_BRG2  0x00000100	/* SCC3 Tx Clock Source is BRG2 */
+#define CMXSCR_TS3CS_BRG3  0x00000200	/* SCC3 Tx Clock Source is BRG3 */
+#define CMXSCR_TS3CS_BRG4  0x00000300	/* SCC3 Tx Clock Source is BRG4 */
+#define CMXSCR_TS3CS_CLK5  0x00000400	/* SCC3 Tx Clock Source is CLK5 */
+#define CMXSCR_TS3CS_CLK6  0x00000500	/* SCC3 Tx Clock Source is CLK6 */
+#define CMXSCR_TS3CS_CLK7  0x00000600	/* SCC3 Tx Clock Source is CLK7 */
+#define CMXSCR_TS3CS_CLK8  0x00000700	/* SCC3 Tx Clock Source is CLK8 */
+
+#define CMXSCR_RS4CS_BRG1  0x00000000	/* SCC4 Rx Clock Source is BRG1 */
+#define CMXSCR_RS4CS_BRG2  0x00000008	/* SCC4 Rx Clock Source is BRG2 */
+#define CMXSCR_RS4CS_BRG3  0x00000010	/* SCC4 Rx Clock Source is BRG3 */
+#define CMXSCR_RS4CS_BRG4  0x00000018	/* SCC4 Rx Clock Source is BRG4 */
+#define CMXSCR_RS4CS_CLK5  0x00000020	/* SCC4 Rx Clock Source is CLK5 */
+#define CMXSCR_RS4CS_CLK6  0x00000028	/* SCC4 Rx Clock Source is CLK6 */
+#define CMXSCR_RS4CS_CLK7  0x00000030	/* SCC4 Rx Clock Source is CLK7 */
+#define CMXSCR_RS4CS_CLK8  0x00000038	/* SCC4 Rx Clock Source is CLK8 */
+
+#define CMXSCR_TS4CS_BRG1  0x00000000	/* SCC4 Tx Clock Source is BRG1 */
+#define CMXSCR_TS4CS_BRG2  0x00000001	/* SCC4 Tx Clock Source is BRG2 */
+#define CMXSCR_TS4CS_BRG3  0x00000002	/* SCC4 Tx Clock Source is BRG3 */
+#define CMXSCR_TS4CS_BRG4  0x00000003	/* SCC4 Tx Clock Source is BRG4 */
+#define CMXSCR_TS4CS_CLK5  0x00000004	/* SCC4 Tx Clock Source is CLK5 */
+#define CMXSCR_TS4CS_CLK6  0x00000005	/* SCC4 Tx Clock Source is CLK6 */
+#define CMXSCR_TS4CS_CLK7  0x00000006	/* SCC4 Tx Clock Source is CLK7 */
+#define CMXSCR_TS4CS_CLK8  0x00000007	/* SCC4 Tx Clock Source is CLK8 */
+
+/*-----------------------------------------------------------------------
+ * CMXSMR - CMX SMC Clock Route Register				15-17
+ */
+#define CMXSMR_SMC1	    0x80	/* SMC1 Connection		*/
+#define CMXSMR_SMC1CS_MSK   0x30	/* SMC1 Clock Source		*/
+#define CMXSMR_SMC2	    0x08	/* SMC2 Connection		*/
+#define CMXSMR_SMC2CS_MSK   0x03	/* SMC2 Clock Source		*/
+
+#define CMXSMR_SMC1CS_BRG1  0x00	/* SMC1 Tx and Rx Clocks are BRG1 */
+#define CMXSMR_SMC1CS_BRG7  0x10	/* SMC1 Tx and Rx Clocks are BRG7 */
+#define CMXSMR_SMC1CS_CLK7  0x20	/* SMC1 Tx and Rx Clocks are CLK7 */
+#define CMXSMR_SMC1CS_CLK9  0x30	/* SMC1 Tx and Rx Clocks are CLK9 */
+
+#define CMXSMR_SMC2CS_BRG2  0x00	/* SMC2 Tx and Rx Clocks are BRG2 */
+#define CMXSMR_SMC2CS_BRG8  0x01	/* SMC2 Tx and Rx Clocks are BRG8 */
+#define CMXSMR_SMC2CS_CLK19 0x02	/* SMC2 Tx and Rx Clocks are CLK19 */
+#define CMXSMR_SMC2CS_CLK20 0x03	/* SMC2 Tx and Rx Clocks are CLK20 */
+
+/*-----------------------------------------------------------------------
+ * miscellaneous
+ */
+
+#define UPMA			1
+#define UPMB			2
+#define UPMC			3
+
+#if !defined(__ASSEMBLY__) && defined(CONFIG_WATCHDOG)
+extern __inline__ void
+reset_8260_watchdog(volatile immap_t *immr)
+{
+    immr->im_siu_conf.sc_swsr = 0x556c;
+    immr->im_siu_conf.sc_swsr = 0xaa39;
+}
+#endif /* !__ASSEMBLY && CONFIG_WATCHDOG */
+
+#endif	/* __MPC8260_H__ */
diff --git a/qemu/roms/u-boot/include/mpc8260_irq.h b/qemu/roms/u-boot/include/mpc8260_irq.h
new file mode 100644
index 000000000..9bee9a335
--- /dev/null
+++ b/qemu/roms/u-boot/include/mpc8260_irq.h
@@ -0,0 +1,48 @@
+#ifndef _MPC8260_IRQ_H
+#define _MPC8260_IRQ_H
+
+/****************************************************************************/
+/* most of this was ripped out of include/asm-ppc/irq.h from the Linux/PPC  */
+/* source. There was no copyright information in the file.		    */
+
+/*
+ * this is the # irq's for all ppc arch's (pmac/chrp/prep)
+ * so it is the max of them all
+ *
+ * [let's just worry about 8260 for now - mjj]
+ */
+#define NR_IRQS			64
+
+/* The 8260 has an internal interrupt controller with a maximum of
+ * 64 IRQs.  We will use NR_IRQs from above since it is large enough.
+ * Don't be confused by the 8260 documentation where they list an
+ * "interrupt number" and "interrupt vector".  We are only interested
+ * in the interrupt vector.  There are "reserved" holes where the
+ * vector number increases, but the interrupt number in the table does not.
+ * (Document errata updates have fixed this...make sure you have up to
+ * date processor documentation -- Dan).
+ */
+#define NR_SIU_INTS	64
+
+/* There are many more than these, we will add them as we need them.
+*/
+#define	SIU_INT_SMC1		((uint)0x04)
+#define	SIU_INT_SMC2		((uint)0x05)
+#define	SIU_INT_IRQ1		((uint)0x13)
+#define	SIU_INT_IRQ2		((uint)0x14)
+#define	SIU_INT_IRQ3		((uint)0x15)
+#define	SIU_INT_IRQ4		((uint)0x16)
+#define	SIU_INT_IRQ5		((uint)0x17)
+#define	SIU_INT_IRQ6		((uint)0x18)
+#define	SIU_INT_IRQ7		((uint)0x19)
+#define	SIU_INT_FCC1		((uint)0x20)
+#define	SIU_INT_FCC2		((uint)0x21)
+#define	SIU_INT_FCC3		((uint)0x22)
+#define	SIU_INT_SCC1		((uint)0x28)
+#define	SIU_INT_SCC2		((uint)0x29)
+#define	SIU_INT_SCC3		((uint)0x2a)
+#define	SIU_INT_SCC4		((uint)0x2b)
+
+#define NR_MASK_WORDS	((NR_IRQS + 31) / 32)
+
+#endif /* _MPC8260_IRQ_H */
diff --git a/qemu/roms/u-boot/include/mpc83xx.h b/qemu/roms/u-boot/include/mpc83xx.h
new file mode 100644
index 000000000..a6d721a89
--- /dev/null
+++ b/qemu/roms/u-boot/include/mpc83xx.h
@@ -0,0 +1,1586 @@
+/*
+ * Copyright (C) 2004-2007, 2010 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MPC83XX_H__
+#define __MPC83XX_H__
+
+#include <config.h>
+#include <asm/fsl_lbc.h>
+#if defined(CONFIG_E300)
+#include <asm/e300.h>
+#endif
+
+/*
+ * MPC83xx cpu provide RCR register to do reset thing specially
+ */
+#define MPC83xx_RESET
+
+/*
+ * System reset offset (PowerPC standard)
+ */
+#define EXC_OFF_SYS_RESET		0x0100
+#define	_START_OFFSET			EXC_OFF_SYS_RESET
+
+/*
+ * IMMRBAR - Internal Memory Register Base Address
+ */
+#ifndef CONFIG_DEFAULT_IMMR
+/* Default IMMR base address */
+#define CONFIG_DEFAULT_IMMR		0xFF400000
+#endif
+/* Register offset to immr */
+#define IMMRBAR				0x0000
+#define IMMRBAR_BASE_ADDR		0xFFF00000	/* Base addr. mask */
+#define IMMRBAR_RES			~(IMMRBAR_BASE_ADDR)
+
+/*
+ * LAWBAR - Local Access Window Base Address Register
+ */
+/* Register offset to immr */
+#define LBLAWBAR0			0x0020
+#define LBLAWAR0			0x0024
+#define LBLAWBAR1			0x0028
+#define LBLAWAR1			0x002C
+#define LBLAWBAR2			0x0030
+#define LBLAWAR2			0x0034
+#define LBLAWBAR3			0x0038
+#define LBLAWAR3			0x003C
+#define LAWBAR_BAR			0xFFFFF000	/* Base addr. mask */
+
+/*
+ * SPRIDR - System Part and Revision ID Register
+ */
+#define SPRIDR_PARTID			0xFFFF0000	/* Part Id */
+#define SPRIDR_REVID			0x0000FFFF	/* Revision Id */
+
+#if defined(CONFIG_MPC834x)
+#define REVID_MAJOR(spridr)		((spridr & 0x0000FF00) >> 8)
+#define REVID_MINOR(spridr)		(spridr & 0x000000FF)
+#else
+#define REVID_MAJOR(spridr)		((spridr & 0x000000F0) >> 4)
+#define REVID_MINOR(spridr)		(spridr & 0x0000000F)
+#endif
+
+#define PARTID_NO_E(spridr)		((spridr & 0xFFFE0000) >> 16)
+#define SPR_FAMILY(spridr)		((spridr & 0xFFF00000) >> 20)
+
+#define SPR_8308			0x8100
+#define SPR_8309			0x8110
+#define SPR_831X_FAMILY			0x80B
+#define SPR_8311			0x80B2
+#define SPR_8313			0x80B0
+#define SPR_8314			0x80B6
+#define SPR_8315			0x80B4
+#define SPR_832X_FAMILY			0x806
+#define SPR_8321			0x8066
+#define SPR_8323			0x8062
+#define SPR_834X_FAMILY			0x803
+#define SPR_8343			0x8036
+#define SPR_8347_TBGA_			0x8032
+#define SPR_8347_PBGA_			0x8034
+#define SPR_8349			0x8030
+#define SPR_836X_FAMILY			0x804
+#define SPR_8358_TBGA_			0x804A
+#define SPR_8358_PBGA_			0x804E
+#define SPR_8360			0x8048
+#define SPR_837X_FAMILY			0x80C
+#define SPR_8377			0x80C6
+#define SPR_8378			0x80C4
+#define SPR_8379			0x80C2
+
+/*
+ * SPCR - System Priority Configuration Register
+ */
+/* PCI Highest Priority Enable */
+#define SPCR_PCIHPE			0x10000000
+#define SPCR_PCIHPE_SHIFT		(31-3)
+/* PCI bridge system bus request priority */
+#define SPCR_PCIPR			0x03000000
+#define SPCR_PCIPR_SHIFT		(31-7)
+#define SPCR_OPT			0x00800000	/* Optimize */
+#define SPCR_OPT_SHIFT			(31-8)
+/* E300 PowerPC core time base unit enable */
+#define SPCR_TBEN			0x00400000
+#define SPCR_TBEN_SHIFT			(31-9)
+/* E300 PowerPC Core system bus request priority */
+#define SPCR_COREPR			0x00300000
+#define SPCR_COREPR_SHIFT		(31-11)
+
+#if defined(CONFIG_MPC834x)
+/* SPCR bits - MPC8349 specific */
+/* TSEC1 data priority */
+#define SPCR_TSEC1DP			0x00003000
+#define SPCR_TSEC1DP_SHIFT		(31-19)
+/* TSEC1 buffer descriptor priority */
+#define SPCR_TSEC1BDP			0x00000C00
+#define SPCR_TSEC1BDP_SHIFT		(31-21)
+/* TSEC1 emergency priority */
+#define SPCR_TSEC1EP			0x00000300
+#define SPCR_TSEC1EP_SHIFT		(31-23)
+/* TSEC2 data priority */
+#define SPCR_TSEC2DP			0x00000030
+#define SPCR_TSEC2DP_SHIFT		(31-27)
+/* TSEC2 buffer descriptor priority */
+#define SPCR_TSEC2BDP			0x0000000C
+#define SPCR_TSEC2BDP_SHIFT		(31-29)
+/* TSEC2 emergency priority */
+#define SPCR_TSEC2EP			0x00000003
+#define SPCR_TSEC2EP_SHIFT		(31-31)
+
+#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+	defined(CONFIG_MPC837x)
+/* SPCR bits - MPC8308, MPC831x and MPC837x specific */
+/* TSEC data priority */
+#define SPCR_TSECDP			0x00003000
+#define SPCR_TSECDP_SHIFT		(31-19)
+/* TSEC buffer descriptor priority */
+#define SPCR_TSECBDP			0x00000C00
+#define SPCR_TSECBDP_SHIFT		(31-21)
+/* TSEC emergency priority */
+#define SPCR_TSECEP			0x00000300
+#define SPCR_TSECEP_SHIFT		(31-23)
+#endif
+
+/* SICRL/H - System I/O Configuration Register Low/High
+ */
+#if defined(CONFIG_MPC834x)
+/* SICRL bits - MPC8349 specific */
+#define SICRL_LDP_A			0x80000000
+#define SICRL_USB1			0x40000000
+#define SICRL_USB0			0x20000000
+#define SICRL_UART			0x0C000000
+#define SICRL_GPIO1_A			0x02000000
+#define SICRL_GPIO1_B			0x01000000
+#define SICRL_GPIO1_C			0x00800000
+#define SICRL_GPIO1_D			0x00400000
+#define SICRL_GPIO1_E			0x00200000
+#define SICRL_GPIO1_F			0x00180000
+#define SICRL_GPIO1_G			0x00040000
+#define SICRL_GPIO1_H			0x00020000
+#define SICRL_GPIO1_I			0x00010000
+#define SICRL_GPIO1_J			0x00008000
+#define SICRL_GPIO1_K			0x00004000
+#define SICRL_GPIO1_L			0x00003000
+
+/* SICRH bits - MPC8349 specific */
+#define SICRH_DDR			0x80000000
+#define SICRH_TSEC1_A			0x10000000
+#define SICRH_TSEC1_B			0x08000000
+#define SICRH_TSEC1_C			0x04000000
+#define SICRH_TSEC1_D			0x02000000
+#define SICRH_TSEC1_E			0x01000000
+#define SICRH_TSEC1_F			0x00800000
+#define SICRH_TSEC2_A			0x00400000
+#define SICRH_TSEC2_B			0x00200000
+#define SICRH_TSEC2_C			0x00100000
+#define SICRH_TSEC2_D			0x00080000
+#define SICRH_TSEC2_E			0x00040000
+#define SICRH_TSEC2_F			0x00020000
+#define SICRH_TSEC2_G			0x00010000
+#define SICRH_TSEC2_H			0x00008000
+#define SICRH_GPIO2_A			0x00004000
+#define SICRH_GPIO2_B			0x00002000
+#define SICRH_GPIO2_C			0x00001000
+#define SICRH_GPIO2_D			0x00000800
+#define SICRH_GPIO2_E			0x00000400
+#define SICRH_GPIO2_F			0x00000200
+#define SICRH_GPIO2_G			0x00000180
+#define SICRH_GPIO2_H			0x00000060
+#define SICRH_TSOBI1			0x00000002
+#define SICRH_TSOBI2			0x00000001
+
+#elif defined(CONFIG_MPC8360)
+/* SICRL bits - MPC8360 specific */
+#define SICRL_LDP_A			0xC0000000
+#define SICRL_LCLK_1			0x10000000
+#define SICRL_LCLK_2			0x08000000
+#define SICRL_SRCID_A			0x03000000
+#define SICRL_IRQ_CKSTP_A		0x00C00000
+
+/* SICRH bits - MPC8360 specific */
+#define SICRH_DDR			0x80000000
+#define SICRH_SECONDARY_DDR		0x40000000
+#define SICRH_SDDROE			0x20000000
+#define SICRH_IRQ3			0x10000000
+#define SICRH_UC1EOBI			0x00000004
+#define SICRH_UC2E1OBI			0x00000002
+#define SICRH_UC2E2OBI			0x00000001
+
+#elif defined(CONFIG_MPC832x)
+/* SICRL bits - MPC832x specific */
+#define SICRL_LDP_LCS_A			0x80000000
+#define SICRL_IRQ_CKS			0x20000000
+#define SICRL_PCI_MSRC			0x10000000
+#define SICRL_URT_CTPR			0x06000000
+#define SICRL_IRQ_CTPR			0x00C00000
+
+#elif defined(CONFIG_MPC8313)
+/* SICRL bits - MPC8313 specific */
+#define SICRL_LBC			0x30000000
+#define SICRL_UART			0x0C000000
+#define SICRL_SPI_A			0x03000000
+#define SICRL_SPI_B			0x00C00000
+#define SICRL_SPI_C			0x00300000
+#define SICRL_SPI_D			0x000C0000
+#define SICRL_USBDR_11			0x00000C00
+#define SICRL_USBDR_10			0x00000800
+#define SICRL_USBDR_01			0x00000400
+#define SICRL_USBDR_00			0x00000000
+#define SICRL_ETSEC1_A			0x0000000C
+#define SICRL_ETSEC2_A			0x00000003
+
+/* SICRH bits - MPC8313 specific */
+#define SICRH_INTR_A			0x02000000
+#define SICRH_INTR_B			0x00C00000
+#define SICRH_IIC			0x00300000
+#define SICRH_ETSEC2_B			0x000C0000
+#define SICRH_ETSEC2_C			0x00030000
+#define SICRH_ETSEC2_D			0x0000C000
+#define SICRH_ETSEC2_E			0x00003000
+#define SICRH_ETSEC2_F			0x00000C00
+#define SICRH_ETSEC2_G			0x00000300
+#define SICRH_ETSEC1_B			0x00000080
+#define SICRH_ETSEC1_C			0x00000060
+#define SICRH_GTX1_DLY			0x00000008
+#define SICRH_GTX2_DLY			0x00000004
+#define SICRH_TSOBI1			0x00000002
+#define SICRH_TSOBI2			0x00000001
+
+#elif defined(CONFIG_MPC8315)
+/* SICRL bits - MPC8315 specific */
+#define SICRL_DMA_CH0			0xc0000000
+#define SICRL_DMA_SPI			0x30000000
+#define SICRL_UART			0x0c000000
+#define SICRL_IRQ4			0x02000000
+#define SICRL_IRQ5			0x01800000
+#define SICRL_IRQ6_7			0x00400000
+#define SICRL_IIC1			0x00300000
+#define SICRL_TDM			0x000c0000
+#define SICRL_TDM_SHARED		0x00030000
+#define SICRL_PCI_A			0x0000c000
+#define SICRL_ELBC_A			0x00003000
+#define SICRL_ETSEC1_A			0x000000c0
+#define SICRL_ETSEC1_B			0x00000030
+#define SICRL_ETSEC1_C			0x0000000c
+#define SICRL_TSEXPOBI			0x00000001
+
+/* SICRH bits - MPC8315 specific */
+#define SICRH_GPIO_0			0xc0000000
+#define SICRH_GPIO_1			0x30000000
+#define SICRH_GPIO_2			0x0c000000
+#define SICRH_GPIO_3			0x03000000
+#define SICRH_GPIO_4			0x00c00000
+#define SICRH_GPIO_5			0x00300000
+#define SICRH_GPIO_6			0x000c0000
+#define SICRH_GPIO_7			0x00030000
+#define SICRH_GPIO_8			0x0000c000
+#define SICRH_GPIO_9			0x00003000
+#define SICRH_GPIO_10			0x00000c00
+#define SICRH_GPIO_11			0x00000300
+#define SICRH_ETSEC2_A			0x000000c0
+#define SICRH_TSOBI1			0x00000002
+#define SICRH_TSOBI2			0x00000001
+
+#elif defined(CONFIG_MPC837x)
+/* SICRL bits - MPC837x specific */
+#define SICRL_USB_A			0xC0000000
+#define SICRL_USB_B			0x30000000
+#define SICRL_USB_B_SD			0x20000000
+#define SICRL_UART			0x0C000000
+#define SICRL_GPIO_A			0x02000000
+#define SICRL_GPIO_B			0x01000000
+#define SICRL_GPIO_C			0x00800000
+#define SICRL_GPIO_D			0x00400000
+#define SICRL_GPIO_E			0x00200000
+#define SICRL_GPIO_F			0x00180000
+#define SICRL_GPIO_G			0x00040000
+#define SICRL_GPIO_H			0x00020000
+#define SICRL_GPIO_I			0x00010000
+#define SICRL_GPIO_J			0x00008000
+#define SICRL_GPIO_K			0x00004000
+#define SICRL_GPIO_L			0x00003000
+#define SICRL_DMA_A			0x00000800
+#define SICRL_DMA_B			0x00000400
+#define SICRL_DMA_C			0x00000200
+#define SICRL_DMA_D			0x00000100
+#define SICRL_DMA_E			0x00000080
+#define SICRL_DMA_F			0x00000040
+#define SICRL_DMA_G			0x00000020
+#define SICRL_DMA_H			0x00000010
+#define SICRL_DMA_I			0x00000008
+#define SICRL_DMA_J			0x00000004
+#define SICRL_LDP_A			0x00000002
+#define SICRL_LDP_B			0x00000001
+
+/* SICRH bits - MPC837x specific */
+#define SICRH_DDR			0x80000000
+#define SICRH_TSEC1_A			0x10000000
+#define SICRH_TSEC1_B			0x08000000
+#define SICRH_TSEC2_A			0x00400000
+#define SICRH_TSEC2_B			0x00200000
+#define SICRH_TSEC2_C			0x00100000
+#define SICRH_TSEC2_D			0x00080000
+#define SICRH_TSEC2_E			0x00040000
+#define SICRH_TMR			0x00010000
+#define SICRH_GPIO2_A			0x00008000
+#define SICRH_GPIO2_B			0x00004000
+#define SICRH_GPIO2_C			0x00002000
+#define SICRH_GPIO2_D			0x00001000
+#define SICRH_GPIO2_E			0x00000C00
+#define SICRH_GPIO2_E_SD		0x00000800
+#define SICRH_GPIO2_F			0x00000300
+#define SICRH_GPIO2_G			0x000000C0
+#define SICRH_GPIO2_H			0x00000030
+#define SICRH_SPI			0x00000003
+#define SICRH_SPI_SD			0x00000001
+
+#elif defined(CONFIG_MPC8308)
+/* SICRL bits - MPC8308 specific */
+#define SICRL_SPI_PF0			(0 << 28)
+#define SICRL_SPI_PF1			(1 << 28)
+#define SICRL_SPI_PF3			(3 << 28)
+#define SICRL_UART_PF0			(0 << 26)
+#define SICRL_UART_PF1			(1 << 26)
+#define SICRL_UART_PF3			(3 << 26)
+#define SICRL_IRQ_PF0			(0 << 24)
+#define SICRL_IRQ_PF1			(1 << 24)
+#define SICRL_I2C2_PF0			(0 << 20)
+#define SICRL_I2C2_PF1			(1 << 20)
+#define SICRL_ETSEC1_TX_CLK		(0 << 6)
+#define SICRL_ETSEC1_GTX_CLK125		(1 << 6)
+
+/* SICRH bits - MPC8308 specific */
+#define SICRH_ESDHC_A_SD		(0 << 30)
+#define SICRH_ESDHC_A_GTM		(1 << 30)
+#define SICRH_ESDHC_A_GPIO		(3 << 30)
+#define SICRH_ESDHC_B_SD		(0 << 28)
+#define SICRH_ESDHC_B_GTM		(1 << 28)
+#define SICRH_ESDHC_B_GPIO		(3 << 28)
+#define SICRH_ESDHC_C_SD		(0 << 26)
+#define SICRH_ESDHC_C_GTM		(1 << 26)
+#define SICRH_ESDHC_C_GPIO		(3 << 26)
+#define SICRH_GPIO_A_GPIO		(0 << 24)
+#define SICRH_GPIO_A_TSEC2		(1 << 24)
+#define SICRH_GPIO_B_GPIO		(0 << 22)
+#define SICRH_GPIO_B_TSEC2_TX_CLK	(1 << 22)
+#define SICRH_GPIO_B_TSEC2_GTX_CLK125	(2 << 22)
+#define SICRH_IEEE1588_A_TMR		(1 << 20)
+#define SICRH_IEEE1588_A_GPIO		(3 << 20)
+#define SICRH_USB			(1 << 18)
+#define SICRH_GTM_GTM			(1 << 16)
+#define SICRH_GTM_GPIO			(3 << 16)
+#define SICRH_IEEE1588_B_TMR		(1 << 14)
+#define SICRH_IEEE1588_B_GPIO		(3 << 14)
+#define SICRH_ETSEC2_CRS		(1 << 12)
+#define SICRH_ETSEC2_GPIO		(3 << 12)
+#define SICRH_GPIOSEL_0			(0 << 8)
+#define SICRH_GPIOSEL_1			(1 << 8)
+#define SICRH_TMROBI_V3P3		(0 << 4)
+#define SICRH_TMROBI_V2P5		(1 << 4)
+#define SICRH_TSOBI1_V3P3		(0 << 1)
+#define SICRH_TSOBI1_V2P5		(1 << 1)
+#define SICRH_TSOBI2_V3P3		(0 << 0)
+#define SICRH_TSOBI2_V2P5		(1 << 0)
+
+#elif defined(CONFIG_MPC8309)
+/* SICR_1 */
+#define SICR_1_UART1_UART1S		(0 << (30-2))
+#define SICR_1_UART1_UART1RTS		(1 << (30-2))
+#define SICR_1_I2C_I2C			(0 << (30-4))
+#define SICR_1_I2C_CKSTOP		(1 << (30-4))
+#define SICR_1_IRQ_A_IRQ		(0 << (30-6))
+#define SICR_1_IRQ_A_MCP		(1 << (30-6))
+#define SICR_1_IRQ_B_IRQ		(0 << (30-8))
+#define SICR_1_IRQ_B_CKSTOP		(1 << (30-8))
+#define SICR_1_GPIO_A_GPIO		(0 << (30-10))
+#define SICR_1_GPIO_A_SD		(2 << (30-10))
+#define SICR_1_GPIO_A_DDR		(3 << (30-10))
+#define SICR_1_GPIO_B_GPIO		(0 << (30-12))
+#define SICR_1_GPIO_B_SD		(2 << (30-12))
+#define SICR_1_GPIO_B_QE		(3 << (30-12))
+#define SICR_1_GPIO_C_GPIO		(0 << (30-14))
+#define SICR_1_GPIO_C_CAN		(1 << (30-14))
+#define SICR_1_GPIO_C_DDR		(2 << (30-14))
+#define SICR_1_GPIO_C_LCS		(3 << (30-14))
+#define SICR_1_GPIO_D_GPIO		(0 << (30-16))
+#define SICR_1_GPIO_D_CAN		(1 << (30-16))
+#define SICR_1_GPIO_D_DDR		(2 << (30-16))
+#define SICR_1_GPIO_D_LCS		(3 << (30-16))
+#define SICR_1_GPIO_E_GPIO		(0 << (30-18))
+#define SICR_1_GPIO_E_CAN		(1 << (30-18))
+#define SICR_1_GPIO_E_DDR		(2 << (30-18))
+#define SICR_1_GPIO_E_LCS		(3 << (30-18))
+#define SICR_1_GPIO_F_GPIO		(0 << (30-20))
+#define SICR_1_GPIO_F_CAN		(1 << (30-20))
+#define SICR_1_GPIO_F_CK		(2 << (30-20))
+#define SICR_1_USB_A_USBDR		(0 << (30-22))
+#define SICR_1_USB_A_UART2S		(1 << (30-22))
+#define SICR_1_USB_B_USBDR		(0 << (30-24))
+#define SICR_1_USB_B_UART2S		(1 << (30-24))
+#define SICR_1_USB_B_UART2RTS		(2 << (30-24))
+#define SICR_1_USB_C_USBDR		(0 << (30-26))
+#define SICR_1_USB_C_QE_EXT		(3 << (30-26))
+#define SICR_1_FEC1_FEC1		(0 << (30-28))
+#define SICR_1_FEC1_GTM			(1 << (30-28))
+#define SICR_1_FEC1_GPIO		(2 << (30-28))
+#define SICR_1_FEC2_FEC2		(0 << (30-30))
+#define SICR_1_FEC2_GTM			(1 << (30-30))
+#define SICR_1_FEC2_GPIO		(2 << (30-30))
+/* SICR_2 */
+#define SICR_2_FEC3_FEC3		(0 << (30-0))
+#define SICR_2_FEC3_TMR			(1 << (30-0))
+#define SICR_2_FEC3_GPIO		(2 << (30-0))
+#define SICR_2_HDLC1_A_HDLC1		(0 << (30-2))
+#define SICR_2_HDLC1_A_GPIO		(1 << (30-2))
+#define SICR_2_HDLC1_A_TDM1		(2 << (30-2))
+#define SICR_2_ELBC_A_LA		(0 << (30-4))
+#define SICR_2_ELBC_B_LCLK		(0 << (30-6))
+#define SICR_2_HDLC2_A_HDLC2		(0 << (30-8))
+#define SICR_2_HDLC2_A_GPIO		(0 << (30-8))
+#define SICR_2_HDLC2_A_TDM2		(0 << (30-8))
+/* bits 10-11 unused */
+#define SICR_2_USB_D_USBDR		(0 << (30-12))
+#define SICR_2_USB_D_GPIO		(2 << (30-12))
+#define SICR_2_USB_D_QE_BRG		(3 << (30-12))
+#define SICR_2_PCI_PCI			(0 << (30-14))
+#define SICR_2_PCI_CPCI_HS		(2 << (30-14))
+#define SICR_2_HDLC1_B_HDLC1		(0 << (30-16))
+#define SICR_2_HDLC1_B_GPIO		(1 << (30-16))
+#define SICR_2_HDLC1_B_QE_BRG		(2 << (30-16))
+#define SICR_2_HDLC1_B_TDM1		(3 << (30-16))
+#define SICR_2_HDLC1_C_HDLC1		(0 << (30-18))
+#define SICR_2_HDLC1_C_GPIO		(1 << (30-18))
+#define SICR_2_HDLC1_C_TDM1		(2 << (30-18))
+#define SICR_2_HDLC2_B_HDLC2		(0 << (30-20))
+#define SICR_2_HDLC2_B_GPIO		(1 << (30-20))
+#define SICR_2_HDLC2_B_QE_BRG		(2 << (30-20))
+#define SICR_2_HDLC2_B_TDM2		(3 << (30-20))
+#define SICR_2_HDLC2_C_HDLC2		(0 << (30-22))
+#define SICR_2_HDLC2_C_GPIO		(1 << (30-22))
+#define SICR_2_HDLC2_C_TDM2		(2 << (30-22))
+#define SICR_2_HDLC2_C_QE_BRG		(3 << (30-22))
+#define SICR_2_QUIESCE_B		(0 << (30-24))
+
+#endif
+
+/*
+ * SWCRR - System Watchdog Control Register
+ */
+/* Register offset to immr */
+#define SWCRR				0x0204
+/* Software Watchdog Time Count */
+#define SWCRR_SWTC			0xFFFF0000
+/* Watchdog Enable bit */
+#define SWCRR_SWEN			0x00000004
+/* Software Watchdog Reset/Interrupt Select bit */
+#define SWCRR_SWRI			0x00000002
+/* Software Watchdog Counter Prescale bit */
+#define SWCRR_SWPR			0x00000001
+#define SWCRR_RES			(~(SWCRR_SWTC | SWCRR_SWEN | \
+						SWCRR_SWRI | SWCRR_SWPR))
+
+/*
+ * SWCNR - System Watchdog Counter Register
+ */
+/* Register offset to immr */
+#define SWCNR				0x0208
+/* Software Watchdog Count mask */
+#define SWCNR_SWCN			0x0000FFFF
+#define SWCNR_RES			~(SWCNR_SWCN)
+
+/*
+ * SWSRR - System Watchdog Service Register
+ */
+/* Register offset to immr */
+#define SWSRR				0x020E
+
+/*
+ * ACR - Arbiter Configuration Register
+ */
+#define ACR_COREDIS			0x10000000	/* Core disable */
+#define ACR_COREDIS_SHIFT		(31-7)
+#define ACR_PIPE_DEP			0x00070000	/* Pipeline depth */
+#define ACR_PIPE_DEP_SHIFT		(31-15)
+#define ACR_PCI_RPTCNT			0x00007000	/* PCI repeat count */
+#define ACR_PCI_RPTCNT_SHIFT		(31-19)
+#define ACR_RPTCNT			0x00000700	/* Repeat count */
+#define ACR_RPTCNT_SHIFT		(31-23)
+#define ACR_APARK			0x00000030	/* Address parking */
+#define ACR_APARK_SHIFT			(31-27)
+#define ACR_PARKM			0x0000000F	/* Parking master */
+#define ACR_PARKM_SHIFT			(31-31)
+
+/*
+ * ATR - Arbiter Timers Register
+ */
+#define ATR_DTO				0x00FF0000	/* Data time out */
+#define ATR_DTO_SHIFT			16
+#define ATR_ATO				0x000000FF	/* Address time out */
+#define ATR_ATO_SHIFT			0
+
+/*
+ * AER - Arbiter Event Register
+ */
+#define AER_ETEA			0x00000020	/* Transfer error */
+/* Reserved transfer type */
+#define AER_RES				0x00000010
+/* External control word transfer type */
+#define AER_ECW				0x00000008
+/* Address Only transfer type */
+#define AER_AO				0x00000004
+#define AER_DTO				0x00000002	/* Data time out */
+#define AER_ATO				0x00000001	/* Address time out */
+
+/*
+ * AEATR - Arbiter Event Address Register
+ */
+#define AEATR_EVENT			0x07000000	/* Event type */
+#define AEATR_EVENT_SHIFT		24
+#define AEATR_MSTR_ID			0x001F0000	/* Master Id */
+#define AEATR_MSTR_ID_SHIFT		16
+#define AEATR_TBST			0x00000800	/* Transfer burst */
+#define AEATR_TBST_SHIFT		11
+#define AEATR_TSIZE			0x00000700	/* Transfer Size */
+#define AEATR_TSIZE_SHIFT		8
+#define AEATR_TTYPE			0x0000001F	/* Transfer Type */
+#define AEATR_TTYPE_SHIFT		0
+
+/*
+ * HRCWL - Hard Reset Configuration Word Low
+ */
+#define HRCWL_LBIUCM			0x80000000
+#define HRCWL_LBIUCM_SHIFT		31
+#define HRCWL_LCL_BUS_TO_SCB_CLK_1X1	0x00000000
+#define HRCWL_LCL_BUS_TO_SCB_CLK_2X1	0x80000000
+
+#define HRCWL_DDRCM			0x40000000
+#define HRCWL_DDRCM_SHIFT		30
+#define HRCWL_DDR_TO_SCB_CLK_1X1	0x00000000
+#define HRCWL_DDR_TO_SCB_CLK_2X1	0x40000000
+
+#define HRCWL_SPMF			0x0f000000
+#define HRCWL_SPMF_SHIFT		24
+#define HRCWL_CSB_TO_CLKIN_16X1		0x00000000
+#define HRCWL_CSB_TO_CLKIN_1X1		0x01000000
+#define HRCWL_CSB_TO_CLKIN_2X1		0x02000000
+#define HRCWL_CSB_TO_CLKIN_3X1		0x03000000
+#define HRCWL_CSB_TO_CLKIN_4X1		0x04000000
+#define HRCWL_CSB_TO_CLKIN_5X1		0x05000000
+#define HRCWL_CSB_TO_CLKIN_6X1		0x06000000
+#define HRCWL_CSB_TO_CLKIN_7X1		0x07000000
+#define HRCWL_CSB_TO_CLKIN_8X1		0x08000000
+#define HRCWL_CSB_TO_CLKIN_9X1		0x09000000
+#define HRCWL_CSB_TO_CLKIN_10X1		0x0A000000
+#define HRCWL_CSB_TO_CLKIN_11X1		0x0B000000
+#define HRCWL_CSB_TO_CLKIN_12X1		0x0C000000
+#define HRCWL_CSB_TO_CLKIN_13X1		0x0D000000
+#define HRCWL_CSB_TO_CLKIN_14X1		0x0E000000
+#define HRCWL_CSB_TO_CLKIN_15X1		0x0F000000
+
+#define HRCWL_VCO_BYPASS		0x00000000
+#define HRCWL_VCO_1X2			0x00000000
+#define HRCWL_VCO_1X4			0x00200000
+#define HRCWL_VCO_1X8			0x00400000
+
+#define HRCWL_COREPLL			0x007F0000
+#define HRCWL_COREPLL_SHIFT		16
+#define HRCWL_CORE_TO_CSB_BYPASS	0x00000000
+#define HRCWL_CORE_TO_CSB_1X1		0x00020000
+#define HRCWL_CORE_TO_CSB_1_5X1		0x00030000
+#define HRCWL_CORE_TO_CSB_2X1		0x00040000
+#define HRCWL_CORE_TO_CSB_2_5X1		0x00050000
+#define HRCWL_CORE_TO_CSB_3X1		0x00060000
+
+#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
+#define HRCWL_CEVCOD			0x000000C0
+#define HRCWL_CEVCOD_SHIFT		6
+#define HRCWL_CE_PLL_VCO_DIV_4		0x00000000
+#define HRCWL_CE_PLL_VCO_DIV_8		0x00000040
+#define HRCWL_CE_PLL_VCO_DIV_2		0x00000080
+
+#define HRCWL_CEPDF			0x00000020
+#define HRCWL_CEPDF_SHIFT		5
+#define HRCWL_CE_PLL_DIV_1X1		0x00000000
+#define HRCWL_CE_PLL_DIV_2X1		0x00000020
+
+#define HRCWL_CEPMF			0x0000001F
+#define HRCWL_CEPMF_SHIFT		0
+#define HRCWL_CE_TO_PLL_1X16_		0x00000000
+#define HRCWL_CE_TO_PLL_1X2		0x00000002
+#define HRCWL_CE_TO_PLL_1X3		0x00000003
+#define HRCWL_CE_TO_PLL_1X4		0x00000004
+#define HRCWL_CE_TO_PLL_1X5		0x00000005
+#define HRCWL_CE_TO_PLL_1X6		0x00000006
+#define HRCWL_CE_TO_PLL_1X7		0x00000007
+#define HRCWL_CE_TO_PLL_1X8		0x00000008
+#define HRCWL_CE_TO_PLL_1X9		0x00000009
+#define HRCWL_CE_TO_PLL_1X10		0x0000000A
+#define HRCWL_CE_TO_PLL_1X11		0x0000000B
+#define HRCWL_CE_TO_PLL_1X12		0x0000000C
+#define HRCWL_CE_TO_PLL_1X13		0x0000000D
+#define HRCWL_CE_TO_PLL_1X14		0x0000000E
+#define HRCWL_CE_TO_PLL_1X15		0x0000000F
+#define HRCWL_CE_TO_PLL_1X16		0x00000010
+#define HRCWL_CE_TO_PLL_1X17		0x00000011
+#define HRCWL_CE_TO_PLL_1X18		0x00000012
+#define HRCWL_CE_TO_PLL_1X19		0x00000013
+#define HRCWL_CE_TO_PLL_1X20		0x00000014
+#define HRCWL_CE_TO_PLL_1X21		0x00000015
+#define HRCWL_CE_TO_PLL_1X22		0x00000016
+#define HRCWL_CE_TO_PLL_1X23		0x00000017
+#define HRCWL_CE_TO_PLL_1X24		0x00000018
+#define HRCWL_CE_TO_PLL_1X25		0x00000019
+#define HRCWL_CE_TO_PLL_1X26		0x0000001A
+#define HRCWL_CE_TO_PLL_1X27		0x0000001B
+#define HRCWL_CE_TO_PLL_1X28		0x0000001C
+#define HRCWL_CE_TO_PLL_1X29		0x0000001D
+#define HRCWL_CE_TO_PLL_1X30		0x0000001E
+#define HRCWL_CE_TO_PLL_1X31		0x0000001F
+
+#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315)
+#define HRCWL_SVCOD			0x30000000
+#define HRCWL_SVCOD_SHIFT		28
+#define HRCWL_SVCOD_DIV_2		0x00000000
+#define HRCWL_SVCOD_DIV_4		0x10000000
+#define HRCWL_SVCOD_DIV_8		0x20000000
+#define HRCWL_SVCOD_DIV_1		0x30000000
+
+#elif defined(CONFIG_MPC837x)
+#define HRCWL_SVCOD			0x30000000
+#define HRCWL_SVCOD_SHIFT		28
+#define HRCWL_SVCOD_DIV_4		0x00000000
+#define HRCWL_SVCOD_DIV_8		0x10000000
+#define HRCWL_SVCOD_DIV_2		0x20000000
+#define HRCWL_SVCOD_DIV_1		0x30000000
+#elif defined(CONFIG_MPC8309)
+
+#define HRCWL_CEVCOD			0x000000C0
+#define HRCWL_CEVCOD_SHIFT		6
+/*
+ * According to Errata MPC8309RMAD, Rev. 0.2, 9/2012
+ * these are different than with 8360, 832x
+ */
+#define HRCWL_CE_PLL_VCO_DIV_2		0x00000000
+#define HRCWL_CE_PLL_VCO_DIV_4		0x00000040
+#define HRCWL_CE_PLL_VCO_DIV_8		0x00000080
+
+#define HRCWL_CEPDF			0x00000020
+#define HRCWL_CEPDF_SHIFT		5
+#define HRCWL_CE_PLL_DIV_1X1		0x00000000
+#define HRCWL_CE_PLL_DIV_2X1		0x00000020
+
+#define HRCWL_CEPMF			0x0000001F
+#define HRCWL_CEPMF_SHIFT		0
+#define HRCWL_CE_TO_PLL_1X16_		0x00000000
+#define HRCWL_CE_TO_PLL_1X2		0x00000002
+#define HRCWL_CE_TO_PLL_1X3		0x00000003
+#define HRCWL_CE_TO_PLL_1X4		0x00000004
+#define HRCWL_CE_TO_PLL_1X5		0x00000005
+#define HRCWL_CE_TO_PLL_1X6		0x00000006
+#define HRCWL_CE_TO_PLL_1X7		0x00000007
+#define HRCWL_CE_TO_PLL_1X8		0x00000008
+#define HRCWL_CE_TO_PLL_1X9		0x00000009
+#define HRCWL_CE_TO_PLL_1X10		0x0000000A
+#define HRCWL_CE_TO_PLL_1X11		0x0000000B
+#define HRCWL_CE_TO_PLL_1X12		0x0000000C
+#define HRCWL_CE_TO_PLL_1X13		0x0000000D
+#define HRCWL_CE_TO_PLL_1X14		0x0000000E
+#define HRCWL_CE_TO_PLL_1X15		0x0000000F
+#define HRCWL_CE_TO_PLL_1X16		0x00000010
+#define HRCWL_CE_TO_PLL_1X17		0x00000011
+#define HRCWL_CE_TO_PLL_1X18		0x00000012
+#define HRCWL_CE_TO_PLL_1X19		0x00000013
+#define HRCWL_CE_TO_PLL_1X20		0x00000014
+#define HRCWL_CE_TO_PLL_1X21		0x00000015
+#define HRCWL_CE_TO_PLL_1X22		0x00000016
+#define HRCWL_CE_TO_PLL_1X23		0x00000017
+#define HRCWL_CE_TO_PLL_1X24		0x00000018
+#define HRCWL_CE_TO_PLL_1X25		0x00000019
+#define HRCWL_CE_TO_PLL_1X26		0x0000001A
+#define HRCWL_CE_TO_PLL_1X27		0x0000001B
+#define HRCWL_CE_TO_PLL_1X28		0x0000001C
+#define HRCWL_CE_TO_PLL_1X29		0x0000001D
+#define HRCWL_CE_TO_PLL_1X30		0x0000001E
+#define HRCWL_CE_TO_PLL_1X31		0x0000001F
+
+#define HRCWL_SVCOD			0x30000000
+#define HRCWL_SVCOD_SHIFT		28
+#define HRCWL_SVCOD_DIV_2		0x00000000
+#define HRCWL_SVCOD_DIV_4		0x10000000
+#define HRCWL_SVCOD_DIV_8		0x20000000
+#define HRCWL_SVCOD_DIV_1		0x30000000
+#endif
+
+/*
+ * HRCWH - Hardware Reset Configuration Word High
+ */
+#define HRCWH_PCI_HOST			0x80000000
+#define HRCWH_PCI_HOST_SHIFT		31
+#define HRCWH_PCI_AGENT			0x00000000
+
+#if defined(CONFIG_MPC834x)
+#define HRCWH_32_BIT_PCI		0x00000000
+#define HRCWH_64_BIT_PCI		0x40000000
+#endif
+
+#define HRCWH_PCI1_ARBITER_DISABLE	0x00000000
+#define HRCWH_PCI1_ARBITER_ENABLE	0x20000000
+
+#define HRCWH_PCI_ARBITER_DISABLE	0x00000000
+#define HRCWH_PCI_ARBITER_ENABLE	0x20000000
+
+#if defined(CONFIG_MPC834x)
+#define HRCWH_PCI2_ARBITER_DISABLE	0x00000000
+#define HRCWH_PCI2_ARBITER_ENABLE	0x10000000
+
+#elif defined(CONFIG_MPC8360)
+#define HRCWH_PCICKDRV_DISABLE		0x00000000
+#define HRCWH_PCICKDRV_ENABLE		0x10000000
+#endif
+
+#define HRCWH_CORE_DISABLE		0x08000000
+#define HRCWH_CORE_ENABLE		0x00000000
+
+#define HRCWH_FROM_0X00000100		0x00000000
+#define HRCWH_FROM_0XFFF00100		0x04000000
+
+#define HRCWH_BOOTSEQ_DISABLE		0x00000000
+#define HRCWH_BOOTSEQ_NORMAL		0x01000000
+#define HRCWH_BOOTSEQ_EXTENDED		0x02000000
+
+#define HRCWH_SW_WATCHDOG_DISABLE	0x00000000
+#define HRCWH_SW_WATCHDOG_ENABLE	0x00800000
+
+#define HRCWH_ROM_LOC_DDR_SDRAM		0x00000000
+#define HRCWH_ROM_LOC_PCI1		0x00100000
+#if defined(CONFIG_MPC834x)
+#define HRCWH_ROM_LOC_PCI2		0x00200000
+#endif
+#if defined(CONFIG_MPC837x)
+#define HRCWH_ROM_LOC_ON_CHIP_ROM	0x00300000
+#endif
+#define HRCWH_ROM_LOC_LOCAL_8BIT	0x00500000
+#define HRCWH_ROM_LOC_LOCAL_16BIT	0x00600000
+#define HRCWH_ROM_LOC_LOCAL_32BIT	0x00700000
+
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+	defined(CONFIG_MPC837x)
+#define HRCWH_ROM_LOC_NAND_SP_8BIT	0x00100000
+#define HRCWH_ROM_LOC_NAND_SP_16BIT	0x00200000
+#define HRCWH_ROM_LOC_NAND_LP_8BIT	0x00500000
+#define HRCWH_ROM_LOC_NAND_LP_16BIT	0x00600000
+
+#define HRCWH_RL_EXT_LEGACY		0x00000000
+#define HRCWH_RL_EXT_NAND		0x00040000
+
+#define HRCWH_TSEC1M_MASK		0x0000E000
+#define HRCWH_TSEC1M_IN_MII		0x00000000
+#define HRCWH_TSEC1M_IN_RMII		0x00002000
+#define HRCWH_TSEC1M_IN_RGMII		0x00006000
+#define HRCWH_TSEC1M_IN_RTBI		0x0000A000
+#define HRCWH_TSEC1M_IN_SGMII		0x0000C000
+
+#define HRCWH_TSEC2M_MASK		0x00001C00
+#define HRCWH_TSEC2M_IN_MII		0x00000000
+#define HRCWH_TSEC2M_IN_RMII		0x00000400
+#define HRCWH_TSEC2M_IN_RGMII		0x00000C00
+#define HRCWH_TSEC2M_IN_RTBI		0x00001400
+#define HRCWH_TSEC2M_IN_SGMII		0x00001800
+#endif
+
+#if defined(CONFIG_MPC834x)
+#define HRCWH_TSEC1M_IN_RGMII		0x00000000
+#define HRCWH_TSEC1M_IN_RTBI		0x00004000
+#define HRCWH_TSEC1M_IN_GMII		0x00008000
+#define HRCWH_TSEC1M_IN_TBI		0x0000C000
+#define HRCWH_TSEC2M_IN_RGMII		0x00000000
+#define HRCWH_TSEC2M_IN_RTBI		0x00001000
+#define HRCWH_TSEC2M_IN_GMII		0x00002000
+#define HRCWH_TSEC2M_IN_TBI		0x00003000
+#endif
+
+#if defined(CONFIG_MPC8360)
+#define HRCWH_SECONDARY_DDR_DISABLE	0x00000000
+#define HRCWH_SECONDARY_DDR_ENABLE	0x00000010
+#endif
+
+#define HRCWH_BIG_ENDIAN		0x00000000
+#define HRCWH_LITTLE_ENDIAN		0x00000008
+
+#define HRCWH_LALE_NORMAL		0x00000000
+#define HRCWH_LALE_EARLY		0x00000004
+
+#define HRCWH_LDP_SET			0x00000000
+#define HRCWH_LDP_CLEAR			0x00000002
+
+/*
+ * RSR - Reset Status Register
+ */
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+	defined(CONFIG_MPC837x)
+#define RSR_RSTSRC			0xF0000000	/* Reset source */
+#define RSR_RSTSRC_SHIFT		28
+#else
+#define RSR_RSTSRC			0xE0000000	/* Reset source */
+#define RSR_RSTSRC_SHIFT		29
+#endif
+#define RSR_BSF				0x00010000	/* Boot seq. fail */
+#define RSR_BSF_SHIFT			16
+/* software soft reset */
+#define RSR_SWSR			0x00002000
+#define RSR_SWSR_SHIFT			13
+/* software hard reset */
+#define RSR_SWHR			0x00001000
+#define RSR_SWHR_SHIFT			12
+#define RSR_JHRS			0x00000200	/* jtag hreset */
+#define RSR_JHRS_SHIFT			9
+/* jtag sreset status */
+#define RSR_JSRS			0x00000100
+#define RSR_JSRS_SHIFT			8
+/* checkstop reset status */
+#define RSR_CSHR			0x00000010
+#define RSR_CSHR_SHIFT			4
+/* software watchdog reset status */
+#define RSR_SWRS			0x00000008
+#define RSR_SWRS_SHIFT			3
+/* bus monitop reset status */
+#define RSR_BMRS			0x00000004
+#define RSR_BMRS_SHIFT			2
+#define RSR_SRS				0x00000002	/* soft reset status */
+#define RSR_SRS_SHIFT			1
+#define RSR_HRS				0x00000001	/* hard reset status */
+#define RSR_HRS_SHIFT			0
+#define RSR_RES				(~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | \
+						RSR_SWHR | RSR_JHRS | \
+						RSR_JSRS | RSR_CSHR | \
+						RSR_SWRS | RSR_BMRS | \
+						RSR_SRS | RSR_HRS))
+/*
+ * RMR - Reset Mode Register
+ */
+/* checkstop reset enable */
+#define RMR_CSRE			0x00000001
+#define RMR_CSRE_SHIFT			0
+#define RMR_RES				~(RMR_CSRE)
+
+/*
+ * RCR - Reset Control Register
+ */
+/* software hard reset */
+#define RCR_SWHR			0x00000002
+/* software soft reset */
+#define RCR_SWSR			0x00000001
+#define RCR_RES				~(RCR_SWHR | RCR_SWSR)
+
+/*
+ * RCER - Reset Control Enable Register
+ */
+/* software hard reset */
+#define RCER_CRE			0x00000001
+#define RCER_RES			~(RCER_CRE)
+
+/*
+ * SPMR - System PLL Mode Register
+ */
+#define SPMR_LBIUCM			0x80000000
+#define SPMR_LBIUCM_SHIFT		31
+#define SPMR_DDRCM			0x40000000
+#define SPMR_DDRCM_SHIFT		30
+#define SPMR_SPMF			0x0F000000
+#define SPMR_SPMF_SHIFT		24
+#define SPMR_CKID			0x00800000
+#define SPMR_CKID_SHIFT			23
+#define SPMR_COREPLL			0x007F0000
+#define SPMR_COREPLL_SHIFT		16
+#define SPMR_CEVCOD			0x000000C0
+#define SPMR_CEVCOD_SHIFT		6
+#define SPMR_CEPDF			0x00000020
+#define SPMR_CEPDF_SHIFT		5
+#define SPMR_CEPMF			0x0000001F
+#define SPMR_CEPMF_SHIFT		0
+
+/*
+ * OCCR - Output Clock Control Register
+ */
+#define OCCR_PCICOE0			0x80000000
+#define OCCR_PCICOE1			0x40000000
+#define OCCR_PCICOE2			0x20000000
+#define OCCR_PCICOE3			0x10000000
+#define OCCR_PCICOE4			0x08000000
+#define OCCR_PCICOE5			0x04000000
+#define OCCR_PCICOE6			0x02000000
+#define OCCR_PCICOE7			0x01000000
+#define OCCR_PCICD0			0x00800000
+#define OCCR_PCICD1			0x00400000
+#define OCCR_PCICD2			0x00200000
+#define OCCR_PCICD3			0x00100000
+#define OCCR_PCICD4			0x00080000
+#define OCCR_PCICD5			0x00040000
+#define OCCR_PCICD6			0x00020000
+#define OCCR_PCICD7			0x00010000
+#define OCCR_PCI1CR			0x00000002
+#define OCCR_PCI2CR			0x00000001
+#define OCCR_PCICR			OCCR_PCI1CR
+
+/*
+ * SCCR - System Clock Control Register
+ */
+#define SCCR_ENCCM			0x03000000
+#define SCCR_ENCCM_SHIFT		24
+#define SCCR_ENCCM_0			0x00000000
+#define SCCR_ENCCM_1			0x01000000
+#define SCCR_ENCCM_2			0x02000000
+#define SCCR_ENCCM_3			0x03000000
+
+#define SCCR_PCICM			0x00010000
+#define SCCR_PCICM_SHIFT		16
+
+#if defined(CONFIG_MPC834x)
+/* SCCR bits - MPC834x specific */
+#define SCCR_TSEC1CM			0xc0000000
+#define SCCR_TSEC1CM_SHIFT		30
+#define SCCR_TSEC1CM_0			0x00000000
+#define SCCR_TSEC1CM_1			0x40000000
+#define SCCR_TSEC1CM_2			0x80000000
+#define SCCR_TSEC1CM_3			0xC0000000
+
+#define SCCR_TSEC2CM			0x30000000
+#define SCCR_TSEC2CM_SHIFT		28
+#define SCCR_TSEC2CM_0			0x00000000
+#define SCCR_TSEC2CM_1			0x10000000
+#define SCCR_TSEC2CM_2			0x20000000
+#define SCCR_TSEC2CM_3			0x30000000
+
+/* The MPH must have the same clock ratio as DR, unless its clock disabled */
+#define SCCR_USBMPHCM			0x00c00000
+#define SCCR_USBMPHCM_SHIFT		22
+#define SCCR_USBDRCM			0x00300000
+#define SCCR_USBDRCM_SHIFT		20
+#define SCCR_USBCM			0x00f00000
+#define SCCR_USBCM_SHIFT		20
+#define SCCR_USBCM_0			0x00000000
+#define SCCR_USBCM_1			0x00500000
+#define SCCR_USBCM_2			0x00A00000
+#define SCCR_USBCM_3			0x00F00000
+
+#elif defined(CONFIG_MPC8313)
+/* TSEC1 bits are for TSEC2 as well */
+#define SCCR_TSEC1CM			0xc0000000
+#define SCCR_TSEC1CM_SHIFT		30
+#define SCCR_TSEC1CM_0			0x00000000
+#define SCCR_TSEC1CM_1			0x40000000
+#define SCCR_TSEC1CM_2			0x80000000
+#define SCCR_TSEC1CM_3			0xC0000000
+
+#define SCCR_TSEC1ON			0x20000000
+#define SCCR_TSEC1ON_SHIFT		29
+#define SCCR_TSEC2ON			0x10000000
+#define SCCR_TSEC2ON_SHIFT		28
+
+#define SCCR_USBDRCM			0x00300000
+#define SCCR_USBDRCM_SHIFT		20
+#define SCCR_USBDRCM_0			0x00000000
+#define SCCR_USBDRCM_1			0x00100000
+#define SCCR_USBDRCM_2			0x00200000
+#define SCCR_USBDRCM_3			0x00300000
+
+#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315)
+/* SCCR bits - MPC8315/MPC8308 specific */
+#define SCCR_TSEC1CM			0xc0000000
+#define SCCR_TSEC1CM_SHIFT		30
+#define SCCR_TSEC1CM_0			0x00000000
+#define SCCR_TSEC1CM_1			0x40000000
+#define SCCR_TSEC1CM_2			0x80000000
+#define SCCR_TSEC1CM_3			0xC0000000
+
+#define SCCR_TSEC2CM			0x30000000
+#define SCCR_TSEC2CM_SHIFT		28
+#define SCCR_TSEC2CM_0			0x00000000
+#define SCCR_TSEC2CM_1			0x10000000
+#define SCCR_TSEC2CM_2			0x20000000
+#define SCCR_TSEC2CM_3			0x30000000
+
+#define SCCR_SDHCCM			0x0c000000
+#define SCCR_SDHCCM_SHIFT		26
+#define SCCR_SDHCCM_0			0x00000000
+#define SCCR_SDHCCM_1			0x04000000
+#define SCCR_SDHCCM_2			0x08000000
+#define SCCR_SDHCCM_3			0x0c000000
+
+#define SCCR_USBDRCM			0x00c00000
+#define SCCR_USBDRCM_SHIFT		22
+#define SCCR_USBDRCM_0			0x00000000
+#define SCCR_USBDRCM_1			0x00400000
+#define SCCR_USBDRCM_2			0x00800000
+#define SCCR_USBDRCM_3			0x00c00000
+
+#define SCCR_SATA1CM			0x00003000
+#define SCCR_SATA1CM_SHIFT		12
+#define SCCR_SATACM			0x00003c00
+#define SCCR_SATACM_SHIFT		10
+#define SCCR_SATACM_0			0x00000000
+#define SCCR_SATACM_1			0x00001400
+#define SCCR_SATACM_2			0x00002800
+#define SCCR_SATACM_3			0x00003c00
+
+#define SCCR_TDMCM			0x00000030
+#define SCCR_TDMCM_SHIFT		4
+#define SCCR_TDMCM_0			0x00000000
+#define SCCR_TDMCM_1			0x00000010
+#define SCCR_TDMCM_2			0x00000020
+#define SCCR_TDMCM_3			0x00000030
+
+#elif defined(CONFIG_MPC837x)
+/* SCCR bits - MPC837x specific */
+#define SCCR_TSEC1CM			0xc0000000
+#define SCCR_TSEC1CM_SHIFT		30
+#define SCCR_TSEC1CM_0			0x00000000
+#define SCCR_TSEC1CM_1			0x40000000
+#define SCCR_TSEC1CM_2			0x80000000
+#define SCCR_TSEC1CM_3			0xC0000000
+
+#define SCCR_TSEC2CM			0x30000000
+#define SCCR_TSEC2CM_SHIFT		28
+#define SCCR_TSEC2CM_0			0x00000000
+#define SCCR_TSEC2CM_1			0x10000000
+#define SCCR_TSEC2CM_2			0x20000000
+#define SCCR_TSEC2CM_3			0x30000000
+
+#define SCCR_SDHCCM			0x0c000000
+#define SCCR_SDHCCM_SHIFT		26
+#define SCCR_SDHCCM_0			0x00000000
+#define SCCR_SDHCCM_1			0x04000000
+#define SCCR_SDHCCM_2			0x08000000
+#define SCCR_SDHCCM_3			0x0c000000
+
+#define SCCR_USBDRCM			0x00c00000
+#define SCCR_USBDRCM_SHIFT		22
+#define SCCR_USBDRCM_0			0x00000000
+#define SCCR_USBDRCM_1			0x00400000
+#define SCCR_USBDRCM_2			0x00800000
+#define SCCR_USBDRCM_3			0x00c00000
+
+/* All of the four SATA controllers must have the same clock ratio */
+#define SCCR_SATA1CM			0x000000c0
+#define SCCR_SATA1CM_SHIFT		6
+#define SCCR_SATACM			0x000000ff
+#define SCCR_SATACM_SHIFT		0
+#define SCCR_SATACM_0			0x00000000
+#define SCCR_SATACM_1			0x00000055
+#define SCCR_SATACM_2			0x000000aa
+#define SCCR_SATACM_3			0x000000ff
+#elif defined(CONFIG_MPC8309)
+/* SCCR bits - MPC8309 specific */
+#define SCCR_SDHCCM			0x0c000000
+#define SCCR_SDHCCM_SHIFT		26
+#define SCCR_SDHCCM_0			0x00000000
+#define SCCR_SDHCCM_1			0x04000000
+#define SCCR_SDHCCM_2			0x08000000
+#define SCCR_SDHCCM_3			0x0c000000
+
+#define SCCR_USBDRCM			0x00c00000
+#define SCCR_USBDRCM_SHIFT		22
+#define SCCR_USBDRCM_0			0x00000000
+#define SCCR_USBDRCM_1			0x00400000
+#define SCCR_USBDRCM_2			0x00800000
+#define SCCR_USBDRCM_3			0x00c00000
+#endif
+
+#define SCCR_PCIEXP1CM			0x00300000
+#define SCCR_PCIEXP1CM_SHIFT		20
+#define SCCR_PCIEXP1CM_0		0x00000000
+#define SCCR_PCIEXP1CM_1		0x00100000
+#define SCCR_PCIEXP1CM_2		0x00200000
+#define SCCR_PCIEXP1CM_3		0x00300000
+
+#define SCCR_PCIEXP2CM			0x000c0000
+#define SCCR_PCIEXP2CM_SHIFT		18
+#define SCCR_PCIEXP2CM_0		0x00000000
+#define SCCR_PCIEXP2CM_1		0x00040000
+#define SCCR_PCIEXP2CM_2		0x00080000
+#define SCCR_PCIEXP2CM_3		0x000c0000
+
+/*
+ * CSn_BDNS - Chip Select memory Bounds Register
+ */
+#define CSBNDS_SA			0x00FF0000
+#define CSBNDS_SA_SHIFT			8
+#define CSBNDS_EA			0x000000FF
+#define CSBNDS_EA_SHIFT			24
+
+/*
+ * CSn_CONFIG - Chip Select Configuration Register
+ */
+#define CSCONFIG_EN			0x80000000
+#define CSCONFIG_AP			0x00800000
+#if defined(CONFIG_MPC830x) || defined(CONFIG_MPC831x)
+#define CSCONFIG_ODT_RD_NEVER		0x00000000
+#define CSCONFIG_ODT_RD_ONLY_CURRENT	0x00100000
+#define CSCONFIG_ODT_RD_ONLY_OTHER_CS	0x00200000
+#define CSCONFIG_ODT_RD_ALL		0x00400000
+#define CSCONFIG_ODT_WR_NEVER		0x00000000
+#define CSCONFIG_ODT_WR_ONLY_CURRENT	0x00010000
+#define CSCONFIG_ODT_WR_ONLY_OTHER_CS	0x00020000
+#define CSCONFIG_ODT_WR_ALL		0x00040000
+#elif defined(CONFIG_MPC832x)
+#define CSCONFIG_ODT_RD_CFG		0x00400000
+#define CSCONFIG_ODT_WR_CFG		0x00040000
+#elif defined(CONFIG_MPC8360) || defined(CONFIG_MPC837x)
+#define CSCONFIG_ODT_RD_NEVER		0x00000000
+#define CSCONFIG_ODT_RD_ONLY_CURRENT	0x00100000
+#define CSCONFIG_ODT_RD_ONLY_OTHER_CS	0x00200000
+#define CSCONFIG_ODT_RD_ONLY_OTHER_DIMM	0x00300000
+#define CSCONFIG_ODT_RD_ALL		0x00400000
+#define CSCONFIG_ODT_WR_NEVER		0x00000000
+#define CSCONFIG_ODT_WR_ONLY_CURRENT	0x00010000
+#define CSCONFIG_ODT_WR_ONLY_OTHER_CS	0x00020000
+#define CSCONFIG_ODT_WR_ONLY_OTHER_DIMM	0x00030000
+#define CSCONFIG_ODT_WR_ALL		0x00040000
+#endif
+#define CSCONFIG_BANK_BIT_3		0x00004000
+#define CSCONFIG_ROW_BIT		0x00000700
+#define CSCONFIG_ROW_BIT_12		0x00000000
+#define CSCONFIG_ROW_BIT_13		0x00000100
+#define CSCONFIG_ROW_BIT_14		0x00000200
+#define CSCONFIG_COL_BIT		0x00000007
+#define CSCONFIG_COL_BIT_8		0x00000000
+#define CSCONFIG_COL_BIT_9		0x00000001
+#define CSCONFIG_COL_BIT_10		0x00000002
+#define CSCONFIG_COL_BIT_11		0x00000003
+
+/*
+ * TIMING_CFG_0 - DDR SDRAM Timing Configuration 0
+ */
+#define TIMING_CFG0_RWT			0xC0000000
+#define TIMING_CFG0_RWT_SHIFT		30
+#define TIMING_CFG0_WRT			0x30000000
+#define TIMING_CFG0_WRT_SHIFT		28
+#define TIMING_CFG0_RRT			0x0C000000
+#define TIMING_CFG0_RRT_SHIFT		26
+#define TIMING_CFG0_WWT			0x03000000
+#define TIMING_CFG0_WWT_SHIFT		24
+#define TIMING_CFG0_ACT_PD_EXIT		0x00700000
+#define TIMING_CFG0_ACT_PD_EXIT_SHIFT	20
+#define TIMING_CFG0_PRE_PD_EXIT		0x00070000
+#define TIMING_CFG0_PRE_PD_EXIT_SHIFT	16
+#define TIMING_CFG0_ODT_PD_EXIT		0x00000F00
+#define TIMING_CFG0_ODT_PD_EXIT_SHIFT	8
+#define TIMING_CFG0_MRS_CYC		0x0000000F
+#define TIMING_CFG0_MRS_CYC_SHIFT	0
+
+/*
+ * TIMING_CFG_1 - DDR SDRAM Timing Configuration 1
+ */
+#define TIMING_CFG1_PRETOACT		0x70000000
+#define TIMING_CFG1_PRETOACT_SHIFT	28
+#define TIMING_CFG1_ACTTOPRE		0x0F000000
+#define TIMING_CFG1_ACTTOPRE_SHIFT	24
+#define TIMING_CFG1_ACTTORW		0x00700000
+#define TIMING_CFG1_ACTTORW_SHIFT	20
+#define TIMING_CFG1_CASLAT		0x00070000
+#define TIMING_CFG1_CASLAT_SHIFT	16
+#define TIMING_CFG1_REFREC		0x0000F000
+#define TIMING_CFG1_REFREC_SHIFT	12
+#define TIMING_CFG1_WRREC		0x00000700
+#define TIMING_CFG1_WRREC_SHIFT		8
+#define TIMING_CFG1_ACTTOACT		0x00000070
+#define TIMING_CFG1_ACTTOACT_SHIFT	4
+#define TIMING_CFG1_WRTORD		0x00000007
+#define TIMING_CFG1_WRTORD_SHIFT	0
+#define TIMING_CFG1_CASLAT_20		0x00030000	/* CAS latency = 2.0 */
+#define TIMING_CFG1_CASLAT_25		0x00040000	/* CAS latency = 2.5 */
+#define TIMING_CFG1_CASLAT_30		0x00050000	/* CAS latency = 3.0 */
+#define TIMING_CFG1_CASLAT_35		0x00060000	/* CAS latency = 3.5 */
+#define TIMING_CFG1_CASLAT_40		0x00070000	/* CAS latency = 4.0 */
+#define TIMING_CFG1_CASLAT_45		0x00080000	/* CAS latency = 4.5 */
+#define TIMING_CFG1_CASLAT_50		0x00090000	/* CAS latency = 5.0 */
+
+/*
+ * TIMING_CFG_2 - DDR SDRAM Timing Configuration 2
+ */
+#define TIMING_CFG2_CPO			0x0F800000
+#define TIMING_CFG2_CPO_SHIFT		23
+#define TIMING_CFG2_ACSM		0x00080000
+#define TIMING_CFG2_WR_DATA_DELAY	0x00001C00
+#define TIMING_CFG2_WR_DATA_DELAY_SHIFT	10
+/* default (= CASLAT + 1) */
+#define TIMING_CFG2_CPO_DEF		0x00000000
+
+#define TIMING_CFG2_ADD_LAT		0x70000000
+#define TIMING_CFG2_ADD_LAT_SHIFT	28
+#define TIMING_CFG2_WR_LAT_DELAY	0x00380000
+#define TIMING_CFG2_WR_LAT_DELAY_SHIFT	19
+#define TIMING_CFG2_RD_TO_PRE		0x0000E000
+#define TIMING_CFG2_RD_TO_PRE_SHIFT	13
+#define TIMING_CFG2_CKE_PLS		0x000001C0
+#define TIMING_CFG2_CKE_PLS_SHIFT	6
+#define TIMING_CFG2_FOUR_ACT		0x0000003F
+#define TIMING_CFG2_FOUR_ACT_SHIFT	0
+
+/*
+ * TIMING_CFG_3 - DDR SDRAM Timing Configuration 3
+ */
+#define TIMING_CFG3_EXT_REFREC		0x00070000
+#define TIMING_CFG3_EXT_REFREC_SHIFT	16
+
+/*
+ * DDR_SDRAM_CFG - DDR SDRAM Control Configuration
+ */
+#define SDRAM_CFG_MEM_EN		0x80000000
+#define SDRAM_CFG_SREN			0x40000000
+#define SDRAM_CFG_ECC_EN		0x20000000
+#define SDRAM_CFG_RD_EN			0x10000000
+#define SDRAM_CFG_SDRAM_TYPE_DDR1	0x02000000
+#define SDRAM_CFG_SDRAM_TYPE_DDR2	0x03000000
+#define SDRAM_CFG_SDRAM_TYPE_MASK	0x07000000
+#define SDRAM_CFG_SDRAM_TYPE_SHIFT	24
+#define SDRAM_CFG_DYN_PWR		0x00200000
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x)
+#define SDRAM_CFG_DBW_MASK		0x00180000
+#define SDRAM_CFG_DBW_16		0x00100000
+#define SDRAM_CFG_DBW_32		0x00080000
+#else
+#define SDRAM_CFG_32_BE			0x00080000
+#endif
+#if !defined(CONFIG_MPC8308)
+#define SDRAM_CFG_8_BE			0x00040000
+#endif
+#define SDRAM_CFG_NCAP			0x00020000
+#define SDRAM_CFG_2T_EN			0x00008000
+#define SDRAM_CFG_HSE			0x00000008
+#define SDRAM_CFG_BI			0x00000001
+
+/*
+ * DDR_SDRAM_MODE - DDR SDRAM Mode Register
+ */
+#define SDRAM_MODE_ESD			0xFFFF0000
+#define SDRAM_MODE_ESD_SHIFT		16
+#define SDRAM_MODE_SD			0x0000FFFF
+#define SDRAM_MODE_SD_SHIFT		0
+/* select extended mode reg */
+#define DDR_MODE_EXT_MODEREG		0x4000
+/* operating mode, mask */
+#define DDR_MODE_EXT_OPMODE		0x3FF8
+#define DDR_MODE_EXT_OP_NORMAL		0x0000		/* normal operation */
+/* QFC / compatibility, mask */
+#define DDR_MODE_QFC			0x0004
+/* compatible to older SDRAMs */
+#define DDR_MODE_QFC_COMP		0x0000
+/* weak drivers */
+#define DDR_MODE_WEAK			0x0002
+/* disable DLL */
+#define DDR_MODE_DLL_DIS		0x0001
+/* CAS latency, mask */
+#define DDR_MODE_CASLAT			0x0070
+#define DDR_MODE_CASLAT_15		0x0010		/* CAS latency 1.5 */
+#define DDR_MODE_CASLAT_20		0x0020		/* CAS latency 2 */
+#define DDR_MODE_CASLAT_25		0x0060		/* CAS latency 2.5 */
+#define DDR_MODE_CASLAT_30		0x0030		/* CAS latency 3 */
+/* sequential burst */
+#define DDR_MODE_BTYPE_SEQ		0x0000
+/* interleaved burst */
+#define DDR_MODE_BTYPE_ILVD		0x0008
+#define DDR_MODE_BLEN_2			0x0001		/* burst length 2 */
+#define DDR_MODE_BLEN_4			0x0002		/* burst length 4 */
+/* exact value for 7.8125us */
+#define DDR_REFINT_166MHZ_7US		1302
+/* use 256 cycles as a starting point */
+#define DDR_BSTOPRE			256
+/* select mode register */
+#define DDR_MODE_MODEREG		0x0000
+
+/*
+ * DDR_SDRAM_INTERVAL - DDR SDRAM Interval Register
+ */
+#define SDRAM_INTERVAL_REFINT		0x3FFF0000
+#define SDRAM_INTERVAL_REFINT_SHIFT	16
+#define SDRAM_INTERVAL_BSTOPRE		0x00003FFF
+#define SDRAM_INTERVAL_BSTOPRE_SHIFT	0
+
+/*
+ * DDR_SDRAM_CLK_CNTL - DDR SDRAM Clock Control Register
+ */
+#define DDR_SDRAM_CLK_CNTL_SS_EN		0x80000000
+#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025	0x01000000
+#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05	0x02000000
+#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075	0x03000000
+#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1		0x04000000
+
+/*
+ * ECC_ERR_INJECT - Memory data path error injection mask ECC
+ */
+/* ECC Mirror Byte */
+#define ECC_ERR_INJECT_EMB		(0x80000000 >> 22)
+/* Error Injection Enable */
+#define ECC_ERR_INJECT_EIEN		(0x80000000 >> 23)
+/* ECC Erroe Injection Enable */
+#define ECC_ERR_INJECT_EEIM		(0xff000000 >> 24)
+#define ECC_ERR_INJECT_EEIM_SHIFT	0
+
+/*
+ * CAPTURE_ECC - Memory data path read capture ECC
+ */
+#define CAPTURE_ECC_ECE			(0xff000000 >> 24)
+#define CAPTURE_ECC_ECE_SHIFT		0
+
+/*
+ * ERR_DETECT - Memory error detect
+ */
+/* Multiple Memory Errors */
+#define ECC_ERROR_DETECT_MME		(0x80000000 >> 0)
+/* Multiple-Bit Error */
+#define ECC_ERROR_DETECT_MBE		(0x80000000 >> 28)
+/* Single-Bit ECC Error Pickup */
+#define ECC_ERROR_DETECT_SBE		(0x80000000 >> 29)
+/* Memory Select Error */
+#define ECC_ERROR_DETECT_MSE		(0x80000000 >> 31)
+
+/*
+ * ERR_DISABLE - Memory error disable
+ */
+/* Multiple-Bit ECC Error Disable */
+#define ECC_ERROR_DISABLE_MBED		(0x80000000 >> 28)
+/* Sinle-Bit ECC Error disable */
+#define ECC_ERROR_DISABLE_SBED		(0x80000000 >> 29)
+/* Memory Select Error Disable */
+#define ECC_ERROR_DISABLE_MSED		(0x80000000 >> 31)
+#define ECC_ERROR_ENABLE		(~(ECC_ERROR_DISABLE_MSED | \
+						ECC_ERROR_DISABLE_SBED | \
+						ECC_ERROR_DISABLE_MBED))
+
+/*
+ * ERR_INT_EN - Memory error interrupt enable
+ */
+/* Multiple-Bit ECC Error Interrupt Enable */
+#define ECC_ERR_INT_EN_MBEE		(0x80000000 >> 28)
+/* Single-Bit ECC Error Interrupt Enable */
+#define ECC_ERR_INT_EN_SBEE		(0x80000000 >> 29)
+/* Memory Select Error Interrupt Enable */
+#define ECC_ERR_INT_EN_MSEE		(0x80000000 >> 31)
+#define ECC_ERR_INT_DISABLE		(~(ECC_ERR_INT_EN_MBEE | \
+						ECC_ERR_INT_EN_SBEE | \
+						ECC_ERR_INT_EN_MSEE))
+
+/*
+ * CAPTURE_ATTRIBUTES - Memory error attributes capture
+ */
+/* Data Beat Num */
+#define ECC_CAPT_ATTR_BNUM		(0xe0000000 >> 1)
+#define ECC_CAPT_ATTR_BNUM_SHIFT	28
+/* Transaction Size */
+#define ECC_CAPT_ATTR_TSIZ		(0xc0000000 >> 6)
+#define ECC_CAPT_ATTR_TSIZ_FOUR_DW	0
+#define ECC_CAPT_ATTR_TSIZ_ONE_DW	1
+#define ECC_CAPT_ATTR_TSIZ_TWO_DW	2
+#define ECC_CAPT_ATTR_TSIZ_THREE_DW	3
+#define ECC_CAPT_ATTR_TSIZ_SHIFT	24
+/* Transaction Source */
+#define ECC_CAPT_ATTR_TSRC		(0xf8000000 >> 11)
+#define ECC_CAPT_ATTR_TSRC_E300_CORE_DT	0x0
+#define ECC_CAPT_ATTR_TSRC_E300_CORE_IF	0x2
+#define ECC_CAPT_ATTR_TSRC_TSEC1	0x4
+#define ECC_CAPT_ATTR_TSRC_TSEC2	0x5
+#define ECC_CAPT_ATTR_TSRC_USB		(0x06|0x07)
+#define ECC_CAPT_ATTR_TSRC_ENCRYPT	0x8
+#define ECC_CAPT_ATTR_TSRC_I2C		0x9
+#define ECC_CAPT_ATTR_TSRC_JTAG		0xA
+#define ECC_CAPT_ATTR_TSRC_PCI1		0xD
+#define ECC_CAPT_ATTR_TSRC_PCI2		0xE
+#define ECC_CAPT_ATTR_TSRC_DMA		0xF
+#define ECC_CAPT_ATTR_TSRC_SHIFT	16
+/* Transaction Type */
+#define ECC_CAPT_ATTR_TTYP		(0xe0000000 >> 18)
+#define ECC_CAPT_ATTR_TTYP_WRITE	0x1
+#define ECC_CAPT_ATTR_TTYP_READ		0x2
+#define ECC_CAPT_ATTR_TTYP_R_M_W	0x3
+#define ECC_CAPT_ATTR_TTYP_SHIFT	12
+#define ECC_CAPT_ATTR_VLD		(0x80000000 >> 31)	/* Valid */
+
+/*
+ * ERR_SBE - Single bit ECC memory error management
+ */
+/* Single-Bit Error Threshold 0..255 */
+#define ECC_ERROR_MAN_SBET		(0xff000000 >> 8)
+#define ECC_ERROR_MAN_SBET_SHIFT	16
+/* Single Bit Error Counter 0..255 */
+#define ECC_ERROR_MAN_SBEC		(0xff000000 >> 24)
+#define ECC_ERROR_MAN_SBEC_SHIFT	0
+
+/*
+ * CONFIG_ADDRESS - PCI Config Address Register
+ */
+#define PCI_CONFIG_ADDRESS_EN		0x80000000
+#define PCI_CONFIG_ADDRESS_BN_SHIFT	16
+#define PCI_CONFIG_ADDRESS_BN_MASK	0x00ff0000
+#define PCI_CONFIG_ADDRESS_DN_SHIFT	11
+#define PCI_CONFIG_ADDRESS_DN_MASK	0x0000f800
+#define PCI_CONFIG_ADDRESS_FN_SHIFT	8
+#define PCI_CONFIG_ADDRESS_FN_MASK	0x00000700
+#define PCI_CONFIG_ADDRESS_RN_SHIFT	0
+#define PCI_CONFIG_ADDRESS_RN_MASK	0x000000fc
+
+/*
+ * POTAR - PCI Outbound Translation Address Register
+ */
+#define POTAR_TA_MASK			0x000fffff
+
+/*
+ * POBAR - PCI Outbound Base Address Register
+ */
+#define POBAR_BA_MASK			0x000fffff
+
+/*
+ * POCMR - PCI Outbound Comparision Mask Register
+ */
+#define POCMR_EN			0x80000000
+/* 0-memory space 1-I/O space */
+#define POCMR_IO			0x40000000
+#define POCMR_SE			0x20000000	/* streaming enable */
+#define POCMR_DST			0x10000000	/* 0-PCI1 1-PCI2 */
+#define POCMR_CM_MASK			0x000fffff
+#define POCMR_CM_4G			0x00000000
+#define POCMR_CM_2G			0x00080000
+#define POCMR_CM_1G			0x000C0000
+#define POCMR_CM_512M			0x000E0000
+#define POCMR_CM_256M			0x000F0000
+#define POCMR_CM_128M			0x000F8000
+#define POCMR_CM_64M			0x000FC000
+#define POCMR_CM_32M			0x000FE000
+#define POCMR_CM_16M			0x000FF000
+#define POCMR_CM_8M			0x000FF800
+#define POCMR_CM_4M			0x000FFC00
+#define POCMR_CM_2M			0x000FFE00
+#define POCMR_CM_1M			0x000FFF00
+#define POCMR_CM_512K			0x000FFF80
+#define POCMR_CM_256K			0x000FFFC0
+#define POCMR_CM_128K			0x000FFFE0
+#define POCMR_CM_64K			0x000FFFF0
+#define POCMR_CM_32K			0x000FFFF8
+#define POCMR_CM_16K			0x000FFFFC
+#define POCMR_CM_8K			0x000FFFFE
+#define POCMR_CM_4K			0x000FFFFF
+
+/*
+ * PITAR - PCI Inbound Translation Address Register
+ */
+#define PITAR_TA_MASK			0x000fffff
+
+/*
+ * PIBAR - PCI Inbound Base/Extended Address Register
+ */
+#define PIBAR_MASK			0xffffffff
+#define PIEBAR_EBA_MASK			0x000fffff
+
+/*
+ * PIWAR - PCI Inbound Windows Attributes Register
+ */
+#define PIWAR_EN			0x80000000
+#define PIWAR_PF			0x20000000
+#define PIWAR_RTT_MASK			0x000f0000
+#define PIWAR_RTT_NO_SNOOP		0x00040000
+#define PIWAR_RTT_SNOOP			0x00050000
+#define PIWAR_WTT_MASK			0x0000f000
+#define PIWAR_WTT_NO_SNOOP		0x00004000
+#define PIWAR_WTT_SNOOP			0x00005000
+#define PIWAR_IWS_MASK			0x0000003F
+#define PIWAR_IWS_4K			0x0000000B
+#define PIWAR_IWS_8K			0x0000000C
+#define PIWAR_IWS_16K			0x0000000D
+#define PIWAR_IWS_32K			0x0000000E
+#define PIWAR_IWS_64K			0x0000000F
+#define PIWAR_IWS_128K			0x00000010
+#define PIWAR_IWS_256K			0x00000011
+#define PIWAR_IWS_512K			0x00000012
+#define PIWAR_IWS_1M			0x00000013
+#define PIWAR_IWS_2M			0x00000014
+#define PIWAR_IWS_4M			0x00000015
+#define PIWAR_IWS_8M			0x00000016
+#define PIWAR_IWS_16M			0x00000017
+#define PIWAR_IWS_32M			0x00000018
+#define PIWAR_IWS_64M			0x00000019
+#define PIWAR_IWS_128M			0x0000001A
+#define PIWAR_IWS_256M			0x0000001B
+#define PIWAR_IWS_512M			0x0000001C
+#define PIWAR_IWS_1G			0x0000001D
+#define PIWAR_IWS_2G			0x0000001E
+
+/*
+ * PMCCR1 - PCI Configuration Register 1
+ */
+#define PMCCR1_POWER_OFF		0x00000020
+
+/*
+ * DDRCDR - DDR Control Driver Register
+ */
+#define DDRCDR_DHC_EN		0x80000000
+#define DDRCDR_EN		0x40000000
+#define DDRCDR_PZ		0x3C000000
+#define DDRCDR_PZ_MAXZ		0x00000000
+#define DDRCDR_PZ_HIZ		0x20000000
+#define DDRCDR_PZ_NOMZ		0x30000000
+#define DDRCDR_PZ_LOZ		0x38000000
+#define DDRCDR_PZ_MINZ		0x3C000000
+#define DDRCDR_NZ		0x3C000000
+#define DDRCDR_NZ_MAXZ		0x00000000
+#define DDRCDR_NZ_HIZ		0x02000000
+#define DDRCDR_NZ_NOMZ		0x03000000
+#define DDRCDR_NZ_LOZ		0x03800000
+#define DDRCDR_NZ_MINZ		0x03C00000
+#define DDRCDR_ODT		0x00080000
+#define DDRCDR_DDR_CFG		0x00040000
+#define DDRCDR_M_ODR		0x00000002
+#define DDRCDR_Q_DRN		0x00000001
+
+/*
+ * PCIE Bridge Register
+ */
+#define PEX_CSB_CTRL_OBPIOE	0x00000001
+#define PEX_CSB_CTRL_IBPIOE	0x00000002
+#define PEX_CSB_CTRL_WDMAE	0x00000004
+#define PEX_CSB_CTRL_RDMAE	0x00000008
+
+#define PEX_CSB_OBCTRL_PIOE	0x00000001
+#define PEX_CSB_OBCTRL_MEMWE	0x00000002
+#define PEX_CSB_OBCTRL_IOWE	0x00000004
+#define PEX_CSB_OBCTRL_CFGWE	0x00000008
+
+#define PEX_CSB_IBCTRL_PIOE	0x00000001
+
+#define PEX_OWAR_EN		0x00000001
+#define PEX_OWAR_TYPE_CFG	0x00000000
+#define PEX_OWAR_TYPE_IO	0x00000002
+#define PEX_OWAR_TYPE_MEM	0x00000004
+#define PEX_OWAR_RLXO		0x00000008
+#define PEX_OWAR_NANP		0x00000010
+#define PEX_OWAR_SIZE		0xFFFFF000
+
+#define PEX_IWAR_EN		0x00000001
+#define PEX_IWAR_TYPE_INT	0x00000000
+#define PEX_IWAR_TYPE_PF	0x00000004
+#define PEX_IWAR_TYPE_NO_PF	0x00000006
+#define PEX_IWAR_NSOV		0x00000008
+#define PEX_IWAR_NSNP		0x00000010
+#define PEX_IWAR_SIZE		0xFFFFF000
+#define PEX_IWAR_SIZE_1M	0x000FF000
+#define PEX_IWAR_SIZE_2M	0x001FF000
+#define PEX_IWAR_SIZE_4M	0x003FF000
+#define PEX_IWAR_SIZE_8M	0x007FF000
+#define PEX_IWAR_SIZE_16M	0x00FFF000
+#define PEX_IWAR_SIZE_32M	0x01FFF000
+#define PEX_IWAR_SIZE_64M	0x03FFF000
+#define PEX_IWAR_SIZE_128M	0x07FFF000
+#define PEX_IWAR_SIZE_256M	0x0FFFF000
+
+#define PEX_GCLK_RATIO		0x440
+
+#ifndef __ASSEMBLY__
+struct pci_region;
+void mpc83xx_pci_init(int num_buses, struct pci_region **reg);
+void mpc83xx_pcislave_unlock(int bus);
+void mpc83xx_pcie_init(int num_buses, struct pci_region **reg);
+#endif
+
+#endif	/* __MPC83XX_H__ */
diff --git a/qemu/roms/u-boot/include/mpc85xx.h b/qemu/roms/u-boot/include/mpc85xx.h
new file mode 100644
index 000000000..11d898527
--- /dev/null
+++ b/qemu/roms/u-boot/include/mpc85xx.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright 2004, 2007 Freescale Semiconductor.
+ * Copyright(c) 2003 Motorola Inc.
+ */
+
+#ifndef	__MPC85xx_H__
+#define __MPC85xx_H__
+
+/* define for common ppc_asm.tmpl */
+#define EXC_OFF_SYS_RESET	0x100	/* System reset */
+#define _START_OFFSET		0
+
+#if defined(CONFIG_E500)
+#include <e500.h>
+#endif
+
+/*
+ * SCCR - System Clock Control Register, 9-8
+ */
+#define SCCR_CLPD       0x00000004      /* CPM Low Power Disable */
+#define SCCR_DFBRG_MSK  0x00000003      /* Division by BRGCLK Mask */
+#define SCCR_DFBRG_SHIFT 0
+
+#define SCCR_DFBRG00    0x00000000      /* BRGCLK division by 4 */
+#define SCCR_DFBRG01    0x00000001      /* BRGCLK div by 16 (normal) */
+#define SCCR_DFBRG10    0x00000002      /* BRGCLK division by 64 */
+#define SCCR_DFBRG11    0x00000003      /* BRGCLK division by 256 */
+
+/*
+ * Define default values for some CCSR macros to make header files cleaner*
+ *
+ * To completely disable CCSR relocation in a board header file, define
+ * CONFIG_SYS_CCSR_DO_NOT_RELOCATE.  This will force CONFIG_SYS_CCSRBAR_PHYS
+ * to a value that is the same as CONFIG_SYS_CCSRBAR.
+ */
+
+#ifdef CONFIG_SYS_CCSRBAR_PHYS
+#error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly.  Use \
+CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead."
+#endif
+
+#ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#undef CONFIG_SYS_CCSRBAR_PHYS_HIGH
+#undef CONFIG_SYS_CCSRBAR_PHYS_LOW
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0
+#endif
+
+#ifndef CONFIG_SYS_CCSRBAR
+#define CONFIG_SYS_CCSRBAR 		CONFIG_SYS_CCSRBAR_DEFAULT
+#endif
+
+#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0xf
+#else
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0
+#endif
+#endif
+
+#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW 	CONFIG_SYS_CCSRBAR_DEFAULT
+#endif
+
+#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
+				 CONFIG_SYS_CCSRBAR_PHYS_LOW)
+
+#ifndef CONFIG_SYS_IMMR
+#define CONFIG_SYS_IMMR 		CONFIG_SYS_CCSRBAR
+#endif
+
+#endif	/* __MPC85xx_H__ */
diff --git a/qemu/roms/u-boot/include/mpc86xx.h b/qemu/roms/u-boot/include/mpc86xx.h
new file mode 100644
index 000000000..9fe474803
--- /dev/null
+++ b/qemu/roms/u-boot/include/mpc86xx.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright 2006 Freescale Semiconductor.
+ * Jeffrey Brown
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ */
+
+#ifndef	__MPC86xx_H__
+#define __MPC86xx_H__
+
+#include <asm/fsl_lbc.h>
+
+#define EXC_OFF_SYS_RESET	0x0100	/* System reset	offset */
+#define _START_OFFSET		EXC_OFF_SYS_RESET
+
+/*
+ * platform register addresses
+ */
+
+#define GUTS_SVR	(CONFIG_SYS_CCSRBAR + 0xE00A4)
+#define MCM_ABCR	(CONFIG_SYS_CCSRBAR + 0x01000)
+#define MCM_DBCR	(CONFIG_SYS_CCSRBAR + 0x01008)
+
+/*
+ * l2cr values.  Look in config_<BOARD>.h for the actual setup
+ */
+#define l2cr		 1017
+
+#define L2CR_L2E         0x80000000 /* bit 0 - enable */
+#define L2CR_L2PE        0x40000000 /* bit 1 - data parity */
+#define L2CR_L2I         0x00200000 /* bit 10 - global invalidate bit */
+#define L2CR_L2CTL       0x00100000 /* bit 11 - l2 ram control */
+#define L2CR_L2DO        0x00010000 /* bit 15 - data-only mode */
+#define L2CR_REP         0x00001000 /* bit 19 - l2 replacement alg */
+#define L2CR_HWF         0x00000800 /* bit 20 - hardware flush */
+#define L2CR_L2IP        0x00000001 /* global invalidate in progress */
+
+#define HID0_XBSEN              0x00000100
+#define HID0_HIGH_BAT_EN        0x00800000
+#define HID0_XAEN               0x00020000
+
+#ifndef __ASSEMBLY__
+
+typedef struct {
+	unsigned long freq_processor;
+	unsigned long freq_systembus;
+	unsigned long freq_localbus;
+} MPC86xx_SYS_INFO;
+
+#define l1icache_enable	icache_enable
+
+void l2cache_enable(void);
+void l1dcache_enable(void);
+
+static __inline__ unsigned long get_hid0 (void)
+{
+	unsigned long hid0;
+	asm volatile("mfspr %0, 1008" : "=r" (hid0) :);
+	return hid0;
+}
+
+static __inline__ unsigned long get_hid1 (void)
+{
+	unsigned long hid1;
+	asm volatile("mfspr %0, 1009" : "=r" (hid1) :);
+	return hid1;
+}
+
+static __inline__ void set_hid0 (unsigned long hid0)
+{
+	asm volatile("mtspr 1008, %0" : : "r" (hid0));
+}
+
+static __inline__ void set_hid1 (unsigned long hid1)
+{
+	asm volatile("mtspr 1009, %0" : : "r" (hid1));
+}
+
+
+static __inline__ unsigned long get_l2cr (void)
+{
+   unsigned long l2cr_val;
+   asm volatile("mfspr %0, 1017" : "=r" (l2cr_val) :);
+   return l2cr_val;
+}
+
+void setup_ddr_bat(phys_addr_t dram_size);
+extern void setup_bats(void);
+
+#endif  /* _ASMLANGUAGE */
+#endif	/* __MPC86xx_H__ */
diff --git a/qemu/roms/u-boot/include/mpc8xx.h b/qemu/roms/u-boot/include/mpc8xx.h
new file mode 100644
index 000000000..33a2cd805
--- /dev/null
+++ b/qemu/roms/u-boot/include/mpc8xx.h
@@ -0,0 +1,618 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * mpc8xx.h
+ *
+ * MPC8xx specific definitions
+ */
+
+#ifndef __MPCXX_H__
+#define __MPCXX_H__
+
+
+/*-----------------------------------------------------------------------
+ * Exception offsets (PowerPC standard)
+ */
+#define EXC_OFF_SYS_RESET	0x0100	/* System reset				*/
+#define _START_OFFSET		EXC_OFF_SYS_RESET
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control Register				11-9
+ */
+#define SYPCR_SWTC	0xFFFF0000	/* Software Watchdog Timer Count	*/
+#define SYPCR_BMT	0x0000FF00	/* Bus Monitor Timing			*/
+#define SYPCR_BME	0x00000080	/* Bus Monitor Enable			*/
+#define SYPCR_SWF	0x00000008	/* Software Watchdog Freeze		*/
+#define SYPCR_SWE	0x00000004	/* Software Watchdog Enable		*/
+#define SYPCR_SWRI	0x00000002	/* Software Watchdog Reset/Int Select	*/
+#define SYPCR_SWP	0x00000001	/* Software Watchdog Prescale		*/
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration Register				11-6
+ */
+#define SIUMCR_EARB	0x80000000	/* External Arbitration			*/
+#define SIUMCR_EARP0	0x00000000	/* External Arbi. Request priority 0	*/
+#define SIUMCR_EARP1	0x10000000	/* External Arbi. Request priority 1	*/
+#define SIUMCR_EARP2	0x20000000	/* External Arbi. Request priority 2	*/
+#define SIUMCR_EARP3	0x30000000	/* External Arbi. Request priority 3	*/
+#define SIUMCR_EARP4	0x40000000	/* External Arbi. Request priority 4	*/
+#define SIUMCR_EARP5	0x50000000	/* External Arbi. Request priority 5	*/
+#define SIUMCR_EARP6	0x60000000	/* External Arbi. Request priority 6	*/
+#define SIUMCR_EARP7	0x70000000	/* External Arbi. Request priority 7	*/
+#define SIUMCR_DSHW	0x00800000	/* Data Showcycles			*/
+#define SIUMCR_DBGC00	0x00000000	/* Debug pins configuration		*/
+#define SIUMCR_DBGC01	0x00200000	/* - " -				*/
+#define SIUMCR_DBGC10	0x00400000	/* - " -				*/
+#define SIUMCR_DBGC11	0x00600000	/* - " -				*/
+#define SIUMCR_DBPC00	0x00000000	/* Debug Port pins Config.		*/
+#define SIUMCR_DBPC01	0x00080000	/* - " -				*/
+#define SIUMCR_DBPC10	0x00100000	/* - " -				*/
+#define SIUMCR_DBPC11	0x00180000	/* - " -				*/
+#define SIUMCR_FRC	0x00020000	/* FRZ pin Configuration		*/
+#define SIUMCR_DLK	0x00010000	/* Debug Register Lock			*/
+#define SIUMCR_PNCS	0x00008000	/* Parity Non-mem Crtl reg		*/
+#define SIUMCR_OPAR	0x00004000	/* Odd Parity				*/
+#define SIUMCR_DPC	0x00002000	/* Data Parity pins Config.		*/
+#define SIUMCR_MPRE	0x00001000	/* Multi CPU Reserva. Enable		*/
+#define SIUMCR_MLRC00	0x00000000	/* Multi Level Reserva. Ctrl		*/
+#define SIUMCR_MLRC01	0x00000400	/* - " -				*/
+#define SIUMCR_MLRC10	0x00000800	/* - " -				*/
+#define SIUMCR_MLRC11	0x00000C00	/* - " -				*/
+#define SIUMCR_AEME	0x00000200	/* Asynchro External Master		*/
+#define SIUMCR_SEME	0x00000100	/* Synchro External Master		*/
+#define SIUMCR_BSC	0x00000080	/* Byte Select Configuration		*/
+#define SIUMCR_GB5E	0x00000040	/* GPL_B(5) Enable			*/
+#define SIUMCR_B2DD	0x00000020	/* Bank 2 Double Drive			*/
+#define SIUMCR_B3DD	0x00000010	/* Bank 3 Double Drive			*/
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control Register			11-26
+ */
+#define TBSCR_TBIRQ7	0x8000		/* Time Base Interrupt Request 7	*/
+#define TBSCR_TBIRQ6	0x4000		/* Time Base Interrupt Request 6	*/
+#define TBSCR_TBIRQ5	0x2000		/* Time Base Interrupt Request 5	*/
+#define TBSCR_TBIRQ4	0x1000		/* Time Base Interrupt Request 4	*/
+#define TBSCR_TBIRQ3	0x0800		/* Time Base Interrupt Request 3	*/
+#define TBSCR_TBIRQ2	0x0400		/* Time Base Interrupt Request 2	*/
+#define TBSCR_TBIRQ1	0x0200		/* Time Base Interrupt Request 1	*/
+#define TBSCR_TBIRQ0	0x0100		/* Time Base Interrupt Request 0	*/
+#if 0	/* already in asm/8xx_immap.h */
+#define TBSCR_REFA	0x0080		/* Reference Interrupt Status A		*/
+#define TBSCR_REFB	0x0040		/* Reference Interrupt Status B		*/
+#define TBSCR_REFAE	0x0008		/* Second Interrupt Enable A		*/
+#define TBSCR_REFBE	0x0004		/* Second Interrupt Enable B		*/
+#define TBSCR_TBF	0x0002		/* Time Base Freeze			*/
+#define TBSCR_TBE	0x0001		/* Time Base Enable			*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control Register		11-31
+ */
+#undef	PISCR_PIRQ			/* TBD					*/
+#define PISCR_PITF	0x0002		/* Periodic Interrupt Timer Freeze	*/
+#if 0	/* already in asm/8xx_immap.h */
+#define PISCR_PS	0x0080		/* Periodic interrupt Status		*/
+#define PISCR_PIE	0x0004		/* Periodic Interrupt Enable		*/
+#define PISCR_PTE	0x0001		/* Periodic Timer Enable		*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * RSR - Reset Status Register						 5-4
+ */
+#define RSR_JTRS	0x01000000	/* JTAG Reset Status		*/
+#define RSR_DBSRS	0x02000000	/* Debug Port Soft Reset Status */
+#define RSR_DBHRS	0x04000000	/* Debug Port Hard Reset Status */
+#define RSR_CSRS	0x08000000	/* Check Stop Reset Status	*/
+#define RSR_SWRS	0x10000000	/* Software Watchdog Reset Status*/
+#define RSR_LLRS	0x20000000	/* Loss-of-Lock Reset Status	*/
+#define RSR_ESRS	0x40000000	/* External Soft Reset Status	*/
+#define RSR_EHRS	0x80000000	/* External Hard Reset Status	*/
+
+#define RSR_ALLBITS	(RSR_JTRS|RSR_DBSRS|RSR_DBHRS|RSR_CSRS|RSR_SWRS|RSR_LLRS|RSR_ESRS|RSR_EHRS)
+
+/*-----------------------------------------------------------------------
+ * Newer chips (MPC866 family and MPC87x/88x family) have different
+ * clock distribution system. Their IMMR lower half is >= 0x0800
+ */
+#define MPC8xx_NEW_CLK 0x0800
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register			15-30
+ */
+/* Newer chips (MPC866/87x/88x et al) defines */
+#define PLPRCR_MFN_MSK	0xF8000000	/* Multiplication factor numerator bits */
+#define PLPRCR_MFN_SHIFT	27	/* Multiplication factor numerator shift*/
+#define PLPRCR_MFD_MSK	0x07C00000	/* Multiplication factor denominator bits */
+#define PLPRCR_MFD_SHIFT	22	/* Multiplication factor denominator shift*/
+#define PLPRCR_S_MSK	0x00300000	/* Multiplication factor integer bits	*/
+#define PLPRCR_S_SHIFT		20	/* Multiplication factor integer shift	*/
+#define PLPRCR_MFI_MSK	0x000F0000	/* Multiplication factor integer bits	*/
+#define PLPRCR_MFI_SHIFT	16	/* Multiplication factor integer shift	*/
+
+#define PLPRCR_PDF_MSK	0x0000001E	/* Predivision Factor bits		*/
+#define PLPRCR_PDF_SHIFT	 1	/* Predivision Factor shift value	*/
+#define PLPRCR_DBRMO	0x00000001	/* DPLL BRM Order bit			*/
+
+/* Multiplication factor + PDF bits */
+#define PLPRCR_MFACT_MSK (PLPRCR_MFN_MSK | \
+			  PLPRCR_MFD_MSK | \
+			  PLPRCR_S_MSK	 | \
+			  PLPRCR_MFI_MSK | \
+			  PLPRCR_PDF_MSK)
+
+/* Older chips (MPC860/862 et al) defines */
+#define PLPRCR_MF_MSK	0xFFF00000	/* Multiplication factor bits		*/
+#define PLPRCR_MF_SHIFT		20	/* Multiplication factor shift value	*/
+
+#define PLPRCR_SPLSS	0x00008000	/* SPLL Lock Status Sticky bit		*/
+#define PLPRCR_TMIST	0x00001000	/* Timers Interrupt Status		*/
+
+#define PLPRCR_LPM_MSK	0x00000300	/* Low Power Mode mask			*/
+#define PLPRCR_LPM_NORMAL 0x00000000	/* normal power management mode		*/
+#define PLPRCR_LPM_DOZE	  0x00000100	/* doze power management mode		*/
+#define PLPRCR_LPM_SLEEP  0x00000200	/* sleep power management mode		*/
+#define PLPRCR_LPM_DEEP_SLEEP 0x00000300 /* deep sleep power mgt mode		*/
+#define PLPRCR_LPM_DOWN	  0x00000300	/* down power management mode		*/
+
+/* Common defines */
+#define PLPRCR_TEXPS	0x00004000	/* TEXP Status				*/
+#define PLPRCR_CSRC	0x00000400	/* Clock Source				*/
+
+#define PLPRCR_CSR	0x00000080	/* CheskStop Reset value		*/
+#define PLPRCR_LOLRE	0x00000040	/* Loss Of Lock Reset Enable		*/
+#define PLPRCR_FIOPD	0x00000020	/* Force I/O Pull Down			*/
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register			15-27
+ */
+#define SCCR_COM00	0x00000000	/* full strength CLKOUT output buffer	*/
+#define SCCR_COM01	0x20000000	/* half strength CLKOUT output buffer	*/
+#define SCCR_COM10	0x40000000	/* reserved				*/
+#define SCCR_COM11	0x60000000	/* CLKOUT output buffer disabled	*/
+#define SCCR_TBS	0x02000000	/* Time Base Source			*/
+#define SCCR_RTDIV	0x01000000	/* RTC Clock Divide			*/
+#define SCCR_RTSEL	0x00800000	/* RTC circuit input source select	*/
+#define SCCR_CRQEN	0x00400000	/* CPM Request Enable			*/
+#define SCCR_PRQEN	0x00200000	/* Power Management Request Enable	*/
+#define SCCR_EBDF00	0x00000000	/* CLKOUT is GCLK2 / 1 (normal op.)	*/
+#define SCCR_EBDF01	0x00020000	/* CLKOUT is GCLK2 / 2			*/
+#define SCCR_EBDF10	0x00040000	/* reserved				*/
+#define SCCR_EBDF11	0x00060000	/* reserved				*/
+#define SCCR_DFSYNC00	0x00000000	/* SyncCLK division by 1 (normal op.)	*/
+#define SCCR_DFSYNC01	0x00002000	/* SyncCLK division by 4		*/
+#define SCCR_DFSYNC10	0x00004000	/* SyncCLK division by 16		*/
+#define SCCR_DFSYNC11	0x00006000	/* SyncCLK division by 64		*/
+#define SCCR_DFBRG00	0x00000000	/* BRGCLK division by 1 (normal op.)	*/
+#define SCCR_DFBRG01	0x00000800	/* BRGCLK division by 4			*/
+#define SCCR_DFBRG10	0x00001000	/* BRGCLK division by 16		*/
+#define SCCR_DFBRG11	0x00001800	/* BRGCLK division by 64		*/
+#define SCCR_DFNL000	0x00000000	/* Division by 2 (default = minimum)	*/
+#define SCCR_DFNL001	0x00000100	/* Division by 4	                */
+#define SCCR_DFNL010	0x00000200	/* Division by 8	                */
+#define SCCR_DFNL011	0x00000300	/* Division by 16	                */
+#define SCCR_DFNL100	0x00000400	/* Division by 32	                */
+#define SCCR_DFNL101	0x00000500	/* Division by 64	                */
+#define SCCR_DFNL110	0x00000600	/* Division by 128	                */
+#define SCCR_DFNL111	0x00000700	/* Division by 256 (maximum)		*/
+#define SCCR_DFNH000	0x00000000	/* Division by 1 (default = minimum)	*/
+#define SCCR_DFNH110	0x000000D0	/* Division by 64 (maximum)		*/
+#define SCCR_DFNH111	0x000000E0	/* reserved				*/
+#define SCCR_DFLCD000	0x00000000	/* Division by 1 (default = minimum)	*/
+#define SCCR_DFLCD001	0x00000004	/* Division by 2			*/
+#define SCCR_DFLCD010	0x00000008	/* Division by 4			*/
+#define SCCR_DFLCD011	0x0000000C	/* Division by 8			*/
+#define SCCR_DFLCD100	0x00000010	/* Division by 16			*/
+#define SCCR_DFLCD101	0x00000014	/* Division by 32			*/
+#define SCCR_DFLCD110	0x00000018	/* Division by 64 (maximum)		*/
+#define SCCR_DFLCD111	0x0000001C	/* reserved				*/
+#define SCCR_DFALCD00	0x00000000	/* Division by 1 (default = minimum)	*/
+#define SCCR_DFALCD01	0x00000001	/* Division by 3			*/
+#define SCCR_DFALCD10	0x00000002	/* Division by 5			*/
+#define SCCR_DFALCD11	0x00000003	/* Division by 7 (maximum)		*/
+
+
+/*-----------------------------------------------------------------------
+ * BR - Memory Controler: Base Register					16-9
+ */
+#define BR_BA_MSK	0xFFFF8000	/* Base Address Mask			*/
+#define BR_AT_MSK	0x00007000	/* Address Type Mask			*/
+#define BR_PS_MSK	0x00000C00	/* Port Size Mask			*/
+#define BR_PS_32	0x00000000	/* 32 bit port size			*/
+#define BR_PS_16	0x00000800	/* 16 bit port size			*/
+#define BR_PS_8		0x00000400	/*  8 bit port size			*/
+#define BR_PARE		0x00000200	/* Parity Enable			*/
+#define BR_WP		0x00000100	/* Write Protect			*/
+#define BR_MS_MSK	0x000000C0	/* Machine Select Mask			*/
+#define BR_MS_GPCM	0x00000000	/* G.P.C.M. Machine Select		*/
+#define BR_MS_UPMA	0x00000080	/* U.P.M.A Machine Select		*/
+#define BR_MS_UPMB	0x000000C0	/* U.P.M.B Machine Select		*/
+#define BR_V		0x00000001	/* Bank Valid				*/
+
+/*-----------------------------------------------------------------------
+ * OR - Memory Controler: Option Register				16-11
+ */
+#define OR_AM_MSK	0xFFFF8000	/* Address Mask Mask			*/
+#define OR_ATM_MSK	0x00007000	/* Address Type Mask Mask		*/
+#define OR_CSNT_SAM	0x00000800	/* Chip Select Negation Time/ Start	*/
+					/* Address Multiplex			*/
+#define OR_ACS_MSK	0x00000600	/* Address to Chip Select Setup mask	*/
+#define OR_ACS_DIV1	0x00000000	/* CS is output at the same time	*/
+#define OR_ACS_DIV4	0x00000400	/* CS is output 1/4 a clock later	*/
+#define OR_ACS_DIV2	0x00000600	/* CS is output 1/2 a clock later	*/
+#define OR_G5LA		0x00000400	/* Output #GPL5 on #GPL_A5		*/
+#define OR_G5LS		0x00000200	/* Drive #GPL high on falling edge of...*/
+#define OR_BI		0x00000100	/* Burst inhibit			*/
+#define OR_SCY_MSK	0x000000F0	/* Cycle Lenght in Clocks		*/
+#define OR_SCY_0_CLK	0x00000000	/* 0 clock cycles wait states		*/
+#define OR_SCY_1_CLK	0x00000010	/* 1 clock cycles wait states		*/
+#define OR_SCY_2_CLK	0x00000020	/* 2 clock cycles wait states		*/
+#define OR_SCY_3_CLK	0x00000030	/* 3 clock cycles wait states		*/
+#define OR_SCY_4_CLK	0x00000040	/* 4 clock cycles wait states		*/
+#define OR_SCY_5_CLK	0x00000050	/* 5 clock cycles wait states		*/
+#define OR_SCY_6_CLK	0x00000060	/* 6 clock cycles wait states		*/
+#define OR_SCY_7_CLK	0x00000070	/* 7 clock cycles wait states		*/
+#define OR_SCY_8_CLK	0x00000080	/* 8 clock cycles wait states		*/
+#define OR_SCY_9_CLK	0x00000090	/* 9 clock cycles wait states		*/
+#define OR_SCY_10_CLK	0x000000A0	/* 10 clock cycles wait states		*/
+#define OR_SCY_11_CLK	0x000000B0	/* 11 clock cycles wait states		*/
+#define OR_SCY_12_CLK	0x000000C0	/* 12 clock cycles wait states		*/
+#define OR_SCY_13_CLK	0x000000D0	/* 13 clock cycles wait states		*/
+#define OR_SCY_14_CLK	0x000000E0	/* 14 clock cycles wait states		*/
+#define OR_SCY_15_CLK	0x000000F0	/* 15 clock cycles wait states		*/
+#define OR_SETA		0x00000008	/* External Transfer Acknowledge	*/
+#define OR_TRLX		0x00000004	/* Timing Relaxed			*/
+#define OR_EHTR		0x00000002	/* Extended Hold Time on Read		*/
+
+
+/*-----------------------------------------------------------------------
+ * MPTPR - Memory Periodic Timer Prescaler Register			16-17
+ */
+#define MPTPR_PTP_MSK	0xFF00		/* Periodic Timers Prescaler Mask	*/
+#define MPTPR_PTP_DIV2	0x2000		/* BRGCLK divided by 2			*/
+#define MPTPR_PTP_DIV4	0x1000		/* BRGCLK divided by 4			*/
+#define MPTPR_PTP_DIV8	0x0800		/* BRGCLK divided by 8			*/
+#define MPTPR_PTP_DIV16 0x0400		/* BRGCLK divided by 16			*/
+#define MPTPR_PTP_DIV32 0x0200		/* BRGCLK divided by 32			*/
+#define MPTPR_PTP_DIV64 0x0100		/* BRGCLK divided by 64			*/
+
+/*-----------------------------------------------------------------------
+ * MCR - Memory Command Register
+ */
+#define MCR_OP_WRITE	0x00000000	/* WRITE command			*/
+#define MCR_OP_READ	0x40000000	/* READ	 command			*/
+#define MCR_OP_RUN	0x80000000	/* RUN	 command			*/
+#define MCR_UPM_A	0x00000000	/* Select UPM A				*/
+#define MCR_UPM_B	0x00800000	/* Select UPM B				*/
+#define MCR_MB_CS0	0x00000000	/* Use Chip Select /CS0			*/
+#define MCR_MB_CS1	0x00002000	/* Use Chip Select /CS1			*/
+#define MCR_MB_CS2	0x00004000	/* Use Chip Select /CS2			*/
+#define MCR_MB_CS3	0x00006000	/* Use Chip Select /CS3			*/
+#define MCR_MB_CS4	0x00008000	/* Use Chip Select /CS4			*/
+#define MCR_MB_CS5	0x0000A000	/* Use Chip Select /CS5			*/
+#define MCR_MB_CS6	0x0000C000	/* Use Chip Select /CS6			*/
+#define MCR_MB_CS7	0x0000E000	/* Use Chip Select /CS7			*/
+#define MCR_MLCF(n)	(((n)&0xF)<<8)	/* Memory Command Loop Count Field	*/
+#define MCR_MAD(addr)	((addr)&0x3F)	/* Memory Array Index			*/
+
+/*-----------------------------------------------------------------------
+ * Machine A Mode Register						16-13
+ */
+#define MAMR_PTA_MSK	0xFF000000	/* Periodic Timer A period mask		*/
+#define MAMR_PTA_SHIFT	0x00000018	/* Periodic Timer A period shift	*/
+#define MAMR_PTAE	0x00800000	/* Periodic Timer A Enable		*/
+#define MAMR_AMA_MSK	0x00700000	/* Addess Multiplexing size A		*/
+#define MAMR_AMA_TYPE_0 0x00000000	/* Addess Multiplexing Type 0		*/
+#define MAMR_AMA_TYPE_1 0x00100000	/* Addess Multiplexing Type 1		*/
+#define MAMR_AMA_TYPE_2 0x00200000	/* Addess Multiplexing Type 2		*/
+#define MAMR_AMA_TYPE_3 0x00300000	/* Addess Multiplexing Type 3		*/
+#define MAMR_AMA_TYPE_4 0x00400000	/* Addess Multiplexing Type 4		*/
+#define MAMR_AMA_TYPE_5 0x00500000	/* Addess Multiplexing Type 5		*/
+#define MAMR_DSA_MSK	0x00060000	/* Disable Timer period mask		*/
+#define MAMR_DSA_1_CYCL 0x00000000	/* 1 cycle Disable Period		*/
+#define MAMR_DSA_2_CYCL 0x00020000	/* 2 cycle Disable Period		*/
+#define MAMR_DSA_3_CYCL 0x00040000	/* 3 cycle Disable Period		*/
+#define MAMR_DSA_4_CYCL 0x00060000	/* 4 cycle Disable Period		*/
+#define MAMR_G0CLA_MSK	0x0000E000	/* General Line 0 Control A		*/
+#define MAMR_G0CLA_A12	0x00000000	/* General Line 0 : A12			*/
+#define MAMR_G0CLA_A11	0x00002000	/* General Line 0 : A11			*/
+#define MAMR_G0CLA_A10	0x00004000	/* General Line 0 : A10			*/
+#define MAMR_G0CLA_A9	0x00006000	/* General Line 0 : A9			*/
+#define MAMR_G0CLA_A8	0x00008000	/* General Line 0 : A8			*/
+#define MAMR_G0CLA_A7	0x0000A000	/* General Line 0 : A7			*/
+#define MAMR_G0CLA_A6	0x0000C000	/* General Line 0 : A6			*/
+#define MAMR_G0CLA_A5	0x0000E000	/* General Line 0 : A5			*/
+#define MAMR_GPL_A4DIS	0x00001000	/* GPL_A4 ouput line Disable		*/
+#define MAMR_RLFA_MSK	0x00000F00	/* Read Loop Field A mask		*/
+#define MAMR_RLFA_1X	0x00000100	/* The Read Loop is executed 1 time	*/
+#define MAMR_RLFA_2X	0x00000200	/* The Read Loop is executed 2 times	*/
+#define MAMR_RLFA_3X	0x00000300	/* The Read Loop is executed 3 times	*/
+#define MAMR_RLFA_4X	0x00000400	/* The Read Loop is executed 4 times	*/
+#define MAMR_RLFA_5X	0x00000500	/* The Read Loop is executed 5 times	*/
+#define MAMR_RLFA_6X	0x00000600	/* The Read Loop is executed 6 times	*/
+#define MAMR_RLFA_7X	0x00000700	/* The Read Loop is executed 7 times	*/
+#define MAMR_RLFA_8X	0x00000800	/* The Read Loop is executed 8 times	*/
+#define MAMR_RLFA_9X	0x00000900	/* The Read Loop is executed 9 times	*/
+#define MAMR_RLFA_10X	0x00000A00	/* The Read Loop is executed 10 times	*/
+#define MAMR_RLFA_11X	0x00000B00	/* The Read Loop is executed 11 times	*/
+#define MAMR_RLFA_12X	0x00000C00	/* The Read Loop is executed 12 times	*/
+#define MAMR_RLFA_13X	0x00000D00	/* The Read Loop is executed 13 times	*/
+#define MAMR_RLFA_14X	0x00000E00	/* The Read Loop is executed 14 times	*/
+#define MAMR_RLFA_15X	0x00000F00	/* The Read Loop is executed 15 times	*/
+#define MAMR_RLFA_16X	0x00000000	/* The Read Loop is executed 16 times	*/
+#define MAMR_WLFA_MSK	0x000000F0	/* Write Loop Field A mask		*/
+#define MAMR_WLFA_1X	0x00000010	/* The Write Loop is executed 1 time	*/
+#define MAMR_WLFA_2X	0x00000020	/* The Write Loop is executed 2 times	*/
+#define MAMR_WLFA_3X	0x00000030	/* The Write Loop is executed 3 times	*/
+#define MAMR_WLFA_4X	0x00000040	/* The Write Loop is executed 4 times	*/
+#define MAMR_WLFA_5X	0x00000050	/* The Write Loop is executed 5 times	*/
+#define MAMR_WLFA_6X	0x00000060	/* The Write Loop is executed 6 times	*/
+#define MAMR_WLFA_7X	0x00000070	/* The Write Loop is executed 7 times	*/
+#define MAMR_WLFA_8X	0x00000080	/* The Write Loop is executed 8 times	*/
+#define MAMR_WLFA_9X	0x00000090	/* The Write Loop is executed 9 times	*/
+#define MAMR_WLFA_10X	0x000000A0	/* The Write Loop is executed 10 times	*/
+#define MAMR_WLFA_11X	0x000000B0	/* The Write Loop is executed 11 times	*/
+#define MAMR_WLFA_12X	0x000000C0	/* The Write Loop is executed 12 times	*/
+#define MAMR_WLFA_13X	0x000000D0	/* The Write Loop is executed 13 times	*/
+#define MAMR_WLFA_14X	0x000000E0	/* The Write Loop is executed 14 times	*/
+#define MAMR_WLFA_15X	0x000000F0	/* The Write Loop is executed 15 times	*/
+#define MAMR_WLFA_16X	0x00000000	/* The Write Loop is executed 16 times	*/
+#define MAMR_TLFA_MSK	0x0000000F	/* Timer Loop Field A mask		*/
+#define MAMR_TLFA_1X	0x00000001	/* The Timer Loop is executed 1 time	*/
+#define MAMR_TLFA_2X	0x00000002	/* The Timer Loop is executed 2 times	*/
+#define MAMR_TLFA_3X	0x00000003	/* The Timer Loop is executed 3 times	*/
+#define MAMR_TLFA_4X	0x00000004	/* The Timer Loop is executed 4 times	*/
+#define MAMR_TLFA_5X	0x00000005	/* The Timer Loop is executed 5 times	*/
+#define MAMR_TLFA_6X	0x00000006	/* The Timer Loop is executed 6 times	*/
+#define MAMR_TLFA_7X	0x00000007	/* The Timer Loop is executed 7 times	*/
+#define MAMR_TLFA_8X	0x00000008	/* The Timer Loop is executed 8 times	*/
+#define MAMR_TLFA_9X	0x00000009	/* The Timer Loop is executed 9 times	*/
+#define MAMR_TLFA_10X	0x0000000A	/* The Timer Loop is executed 10 times	*/
+#define MAMR_TLFA_11X	0x0000000B	/* The Timer Loop is executed 11 times	*/
+#define MAMR_TLFA_12X	0x0000000C	/* The Timer Loop is executed 12 times	*/
+#define MAMR_TLFA_13X	0x0000000D	/* The Timer Loop is executed 13 times	*/
+#define MAMR_TLFA_14X	0x0000000E	/* The Timer Loop is executed 14 times	*/
+#define MAMR_TLFA_15X	0x0000000F	/* The Timer Loop is executed 15 times	*/
+#define MAMR_TLFA_16X	0x00000000	/* The Timer Loop is executed 16 times	*/
+
+/*-----------------------------------------------------------------------
+ * Machine B Mode Register						16-13
+ */
+#define MBMR_PTB_MSK	0xFF000000	/* Periodic Timer B period mask		*/
+#define MBMR_PTB_SHIFT	0x00000018	/* Periodic Timer B period shift	*/
+#define MBMR_PTBE	0x00800000	/* Periodic Timer B Enable		*/
+#define MBMR_AMB_MSK	0x00700000	/* Addess Multiplex size B		*/
+#define MBMR_AMB_TYPE_0 0x00000000	/* Addess Multiplexing Type 0		*/
+#define MBMR_AMB_TYPE_1 0x00100000	/* Addess Multiplexing Type 1		*/
+#define MBMR_AMB_TYPE_2 0x00200000	/* Addess Multiplexing Type 2		*/
+#define MBMR_AMB_TYPE_3 0x00300000	/* Addess Multiplexing Type 3		*/
+#define MBMR_AMB_TYPE_4 0x00400000	/* Addess Multiplexing Type 4		*/
+#define MBMR_AMB_TYPE_5 0x00500000	/* Addess Multiplexing Type 5		*/
+#define MBMR_DSB_MSK	0x00060000	/* Disable Timer period mask		*/
+#define MBMR_DSB_1_CYCL 0x00000000	/* 1 cycle Disable Period		*/
+#define MBMR_DSB_2_CYCL 0x00020000	/* 2 cycle Disable Period		*/
+#define MBMR_DSB_3_CYCL 0x00040000	/* 3 cycle Disable Period		*/
+#define MBMR_DSB_4_CYCL 0x00060000	/* 4 cycle Disable Period		*/
+#define MBMR_G0CLB_MSK	0x0000E000	/* General Line 0 Control B		*/
+#define MBMR_G0CLB_A12	0x00000000	/* General Line 0 : A12			*/
+#define MBMR_G0CLB_A11	0x00002000	/* General Line 0 : A11			*/
+#define MBMR_G0CLB_A10	0x00004000	/* General Line 0 : A10			*/
+#define MBMR_G0CLB_A9	0x00006000	/* General Line 0 : A9			*/
+#define MBMR_G0CLB_A8	0x00008000	/* General Line 0 : A8			*/
+#define MBMR_G0CLB_A7	0x0000A000	/* General Line 0 : A7			*/
+#define MBMR_G0CLB_A6	0x0000C000	/* General Line 0 : A6			*/
+#define MBMR_G0CLB_A5	0x0000E000	/* General Line 0 : A5			*/
+#define MBMR_GPL_B4DIS	0x00001000	/* GPL_B4 ouput line Disable		*/
+#define MBMR_RLFB_MSK	0x00000F00	/* Read Loop Field B mask		*/
+#define MBMR_RLFB_1X	0x00000100	/* The Read Loop is executed 1 time	*/
+#define MBMR_RLFB_2X	0x00000200	/* The Read Loop is executed 2 times	*/
+#define MBMR_RLFB_3X	0x00000300	/* The Read Loop is executed 3 times	*/
+#define MBMR_RLFB_4X	0x00000400	/* The Read Loop is executed 4 times	*/
+#define MBMR_RLFB_5X	0x00000500	/* The Read Loop is executed 5 times	*/
+#define MBMR_RLFB_6X	0x00000600	/* The Read Loop is executed 6 times	*/
+#define MBMR_RLFB_7X	0x00000700	/* The Read Loop is executed 7 times	*/
+#define MBMR_RLFB_8X	0x00000800	/* The Read Loop is executed 8 times	*/
+#define MBMR_RLFB_9X	0x00000900	/* The Read Loop is executed 9 times	*/
+#define MBMR_RLFB_10X	0x00000A00	/* The Read Loop is executed 10 times	*/
+#define MBMR_RLFB_11X	0x00000B00	/* The Read Loop is executed 11 times	*/
+#define MBMR_RLFB_12X	0x00000C00	/* The Read Loop is executed 12 times	*/
+#define MBMR_RLFB_13X	0x00000D00	/* The Read Loop is executed 13 times	*/
+#define MBMR_RLFB_14X	0x00000E00	/* The Read Loop is executed 14 times	*/
+#define MBMR_RLFB_15X	0x00000f00	/* The Read Loop is executed 15 times	*/
+#define MBMR_RLFB_16X	0x00000000	/* The Read Loop is executed 16 times	*/
+#define MBMR_WLFB_MSK	0x000000F0	/* Write Loop Field B mask		*/
+#define MBMR_WLFB_1X	0x00000010	/* The Write Loop is executed 1 time	*/
+#define MBMR_WLFB_2X	0x00000020	/* The Write Loop is executed 2 times	*/
+#define MBMR_WLFB_3X	0x00000030	/* The Write Loop is executed 3 times	*/
+#define MBMR_WLFB_4X	0x00000040	/* The Write Loop is executed 4 times	*/
+#define MBMR_WLFB_5X	0x00000050	/* The Write Loop is executed 5 times	*/
+#define MBMR_WLFB_6X	0x00000060	/* The Write Loop is executed 6 times	*/
+#define MBMR_WLFB_7X	0x00000070	/* The Write Loop is executed 7 times	*/
+#define MBMR_WLFB_8X	0x00000080	/* The Write Loop is executed 8 times	*/
+#define MBMR_WLFB_9X	0x00000090	/* The Write Loop is executed 9 times	*/
+#define MBMR_WLFB_10X	0x000000A0	/* The Write Loop is executed 10 times	*/
+#define MBMR_WLFB_11X	0x000000B0	/* The Write Loop is executed 11 times	*/
+#define MBMR_WLFB_12X	0x000000C0	/* The Write Loop is executed 12 times	*/
+#define MBMR_WLFB_13X	0x000000D0	/* The Write Loop is executed 13 times	*/
+#define MBMR_WLFB_14X	0x000000E0	/* The Write Loop is executed 14 times	*/
+#define MBMR_WLFB_15X	0x000000F0	/* The Write Loop is executed 15 times	*/
+#define MBMR_WLFB_16X	0x00000000	/* The Write Loop is executed 16 times	*/
+#define MBMR_TLFB_MSK	0x0000000F	/* Timer Loop Field B mask		*/
+#define MBMR_TLFB_1X	0x00000001	/* The Timer Loop is executed 1 time	*/
+#define MBMR_TLFB_2X	0x00000002	/* The Timer Loop is executed 2 times	*/
+#define MBMR_TLFB_3X	0x00000003	/* The Timer Loop is executed 3 times	*/
+#define MBMR_TLFB_4X	0x00000004	/* The Timer Loop is executed 4 times	*/
+#define MBMR_TLFB_5X	0x00000005	/* The Timer Loop is executed 5 times	*/
+#define MBMR_TLFB_6X	0x00000006	/* The Timer Loop is executed 6 times	*/
+#define MBMR_TLFB_7X	0x00000007	/* The Timer Loop is executed 7 times	*/
+#define MBMR_TLFB_8X	0x00000008	/* The Timer Loop is executed 8 times	*/
+#define MBMR_TLFB_9X	0x00000009	/* The Timer Loop is executed 9 times	*/
+#define MBMR_TLFB_10X	0x0000000A	/* The Timer Loop is executed 10 times	*/
+#define MBMR_TLFB_11X	0x0000000B	/* The Timer Loop is executed 11 times	*/
+#define MBMR_TLFB_12X	0x0000000C	/* The Timer Loop is executed 12 times	*/
+#define MBMR_TLFB_13X	0x0000000D	/* The Timer Loop is executed 13 times	*/
+#define MBMR_TLFB_14X	0x0000000E	/* The Timer Loop is executed 14 times	*/
+#define MBMR_TLFB_15X	0x0000000F	/* The Timer Loop is executed 15 times	*/
+#define MBMR_TLFB_16X	0x00000000	/* The Timer Loop is executed 16 times	*/
+
+/*-----------------------------------------------------------------------
+ * Timer Global Configuration Register					18-8
+ */
+#define TGCR_CAS4	0x8000		/* Cascade Timer 3 and 4	*/
+#define TGCR_FRZ4	0x4000		/* Freeze timer 4		*/
+#define TGCR_STP4	0x2000		/* Stop timer	4		*/
+#define TGCR_RST4	0x1000		/* Reset timer	4		*/
+#define TGCR_GM2	0x0800		/* Gate Mode for Pin 2		*/
+#define TGCR_FRZ3	0x0400		/* Freeze timer 3		*/
+#define TGCR_STP3	0x0200		/* Stop timer	3		*/
+#define TGCR_RST3	0x0100		/* Reset timer	3		*/
+#define TGCR_CAS2	0x0080		/* Cascade Timer 1 and 2	*/
+#define TGCR_FRZ2	0x0040		/* Freeze timer 2		*/
+#define TGCR_STP2	0x0020		/* Stop timer	2		*/
+#define TGCR_RST2	0x0010		/* Reset timer	2		*/
+#define TGCR_GM1	0x0008		/* Gate Mode for Pin 1		*/
+#define TGCR_FRZ1	0x0004		/* Freeze timer 1		*/
+#define TGCR_STP1	0x0002		/* Stop timer	1		*/
+#define TGCR_RST1	0x0001		/* Reset timer	1		*/
+
+
+/*-----------------------------------------------------------------------
+ * Timer Mode Register							18-9
+ */
+#define TMR_PS_MSK		0xFF00	/* Prescaler Value			*/
+#define TMR_PS_SHIFT		     8	/* Prescaler position			*/
+#define TMR_CE_MSK		0x00C0	/* Capture Edge and Enable Interrupt	*/
+#define TMR_CE_INTR_DIS		0x0000	/* Disable Interrupt on capture event	*/
+#define TMR_CE_RISING		0x0040	/* Capture on Rising TINx edge only	*/
+#define TMR_CE_FALLING		0x0080	/* Capture on Falling TINx edge only	*/
+#define TMR_CE_ANY		0x00C0	/* Capture on any TINx edge		*/
+#define TMR_OM			0x0020	/* Output Mode				*/
+#define TMR_ORI			0x0010	/* Output Reference Interrupt Enable	*/
+#define TMR_FRR			0x0008	/* Free Run/Restart			*/
+#define TMR_ICLK_MSK		0x0006	/* Timer Input Clock Source mask	*/
+#define TMR_ICLK_IN_CAS		0x0000	/* Internally cascaded input		*/
+#define TMR_ICLK_IN_GEN		0x0002	/* Internal General system clock	*/
+#define TMR_ICLK_IN_GEN_DIV16	0x0004	/* Internal General system clk div 16	*/
+#define TMR_ICLK_TIN_PIN	0x0006	/* TINx pin				*/
+#define TMR_GE			0x0001	/* Gate Enable				*/
+
+
+/*-----------------------------------------------------------------------
+ * I2C Controller Registers
+ */
+#define I2MOD_REVD		0x20	/* Reverese Data			*/
+#define I2MOD_GCD		0x10	/* General Call Disable			*/
+#define I2MOD_FLT		0x08	/* Clock Filter				*/
+#define I2MOD_PDIV32		0x00	/* Pre-Divider 32			*/
+#define I2MOD_PDIV16		0x02	/* Pre-Divider 16			*/
+#define I2MOD_PDIV8		0x04	/* Pre-Divider	8			*/
+#define I2MOD_PDIV4		0x06	/* Pre-Divider	4			*/
+#define I2MOD_EN		0x01	/* Enable				*/
+
+#define I2CER_TXE		0x10	/* Tx Error				*/
+#define I2CER_BSY		0x04	/* Busy Condition			*/
+#define I2CER_TXB		0x02	/* Tx Buffer Transmitted		*/
+#define I2CER_RXB		0x01	/* Rx Buffer Received			*/
+#define I2CER_ALL		(I2CER_TXE | I2CER_BSY | I2CER_TXB | I2CER_RXB)
+
+#define I2COM_STR		0x80	/* Start Transmit			*/
+#define I2COM_MASTER		0x01	/* Master mode				*/
+
+/*-----------------------------------------------------------------------
+ * SPI Controller Registers						31-10
+ */
+#define SPI_EMASK		0x37	/* Event Mask				*/
+#define SPI_MME			0x20	/* Multi-Master Error			*/
+#define SPI_TXE			0x10	/* Transmit Error			*/
+#define SPI_BSY			0x04	/* Busy					*/
+#define SPI_TXB			0x02	/* Tx Buffer Empty			*/
+#define SPI_RXB			0x01	/* RX Buffer full/closed		*/
+
+#define SPI_STR			0x80	/* SPCOM: Start transmit		*/
+
+/*-----------------------------------------------------------------------
+ * PCMCIA Interface General Control Register				17-12
+ */
+#define PCMCIA_GCRX_CXRESET	0x00000040
+#define PCMCIA_GCRX_CXOE	0x00000080
+
+#define PCMCIA_VS1(slot)	(0x80000000 >> (slot << 4))
+#define PCMCIA_VS2(slot)	(0x40000000 >> (slot << 4))
+#define PCMCIA_VS_MASK(slot)	(0xC0000000 >> (slot << 4))
+#define PCMCIA_VS_SHIFT(slot)	(30 - (slot << 4))
+
+#define PCMCIA_WP(slot)		(0x20000000 >> (slot << 4))
+#define PCMCIA_CD2(slot)	(0x10000000 >> (slot << 4))
+#define PCMCIA_CD1(slot)	(0x08000000 >> (slot << 4))
+#define PCMCIA_BVD2(slot)	(0x04000000 >> (slot << 4))
+#define PCMCIA_BVD1(slot)	(0x02000000 >> (slot << 4))
+#define PCMCIA_RDY(slot)	(0x01000000 >> (slot << 4))
+#define PCMCIA_RDY_L(slot)	(0x00800000 >> (slot << 4))
+#define PCMCIA_RDY_H(slot)	(0x00400000 >> (slot << 4))
+#define PCMCIA_RDY_R(slot)	(0x00200000 >> (slot << 4))
+#define PCMCIA_RDY_F(slot)	(0x00100000 >> (slot << 4))
+#define PCMCIA_MASK(slot)	(0xFFFF0000 >> (slot << 4))
+
+/*-----------------------------------------------------------------------
+ * PCMCIA Option Register Definitions
+ *
+ * Bank Sizes:
+ */
+#define PCMCIA_BSIZE_1		0x00000000	/* Bank size:	1 Bytes */
+#define PCMCIA_BSIZE_2		0x08000000	/* Bank size:	2 Bytes */
+#define PCMCIA_BSIZE_4		0x18000000	/* Bank size:	4 Bytes */
+#define PCMCIA_BSIZE_8		0x10000000	/* Bank size:	8 Bytes */
+#define PCMCIA_BSIZE_16		0x30000000	/* Bank size:  16 Bytes */
+#define PCMCIA_BSIZE_32		0x38000000	/* Bank size:  32 Bytes */
+#define PCMCIA_BSIZE_64		0x28000000	/* Bank size:  64 Bytes */
+#define PCMCIA_BSIZE_128	0x20000000	/* Bank size: 128 Bytes */
+#define PCMCIA_BSIZE_256	0x60000000	/* Bank size: 256 Bytes */
+#define PCMCIA_BSIZE_512	0x68000000	/* Bank size: 512 Bytes */
+#define PCMCIA_BSIZE_1K		0x78000000	/* Bank size:	1 kB	*/
+#define PCMCIA_BSIZE_2K		0x70000000	/* Bank size:	2 kB	*/
+#define PCMCIA_BSIZE_4K		0x50000000	/* Bank size:	4 kB	*/
+#define PCMCIA_BSIZE_8K		0x58000000	/* Bank size:	8 kB	*/
+#define PCMCIA_BSIZE_16K	0x48000000	/* Bank size:  16 kB	*/
+#define PCMCIA_BSIZE_32K	0x40000000	/* Bank size:  32 kB	*/
+#define PCMCIA_BSIZE_64K	0xC0000000	/* Bank size:  64 kB	*/
+#define PCMCIA_BSIZE_128K	0xC8000000	/* Bank size: 128 kB	*/
+#define PCMCIA_BSIZE_256K	0xD8000000	/* Bank size: 256 kB	*/
+#define PCMCIA_BSIZE_512K	0xD0000000	/* Bank size: 512 kB	*/
+#define PCMCIA_BSIZE_1M		0xF0000000	/* Bank size:	1 MB	*/
+#define PCMCIA_BSIZE_2M		0xF8000000	/* Bank size:	2 MB	*/
+#define PCMCIA_BSIZE_4M		0xE8000000	/* Bank size:	4 MB	*/
+#define PCMCIA_BSIZE_8M		0xE0000000	/* Bank size:	8 MB	*/
+#define PCMCIA_BSIZE_16M	0xA0000000	/* Bank size:  16 MB	*/
+#define PCMCIA_BSIZE_32M	0xA8000000	/* Bank size:  32 MB	*/
+#define PCMCIA_BSIZE_64M	0xB8000000	/* Bank size:  64 MB	*/
+
+/* PCMCIA Timing */
+#define PCMCIA_SHT(t)	((t & 0x0F)<<16)	/* Strobe Hold	Time	*/
+#define PCMCIA_SST(t)	((t & 0x0F)<<12)	/* Strobe Setup Time	*/
+#define PCMCIA_SL(t) ((t==32) ? 0 : ((t & 0x1F)<<7)) /* Strobe Length	*/
+
+/* PCMCIA Port Sizes */
+#define PCMCIA_PPS_8		0x00000000	/*  8 bit port size	*/
+#define PCMCIA_PPS_16		0x00000040	/* 16 bit port size	*/
+
+/* PCMCIA Region Select */
+#define PCMCIA_PRS_MEM		0x00000000	/* Common Memory Space	*/
+#define PCMCIA_PRS_ATTR		0x00000010	/*     Attribute Space	*/
+#define PCMCIA_PRS_IO		0x00000018	/*	     I/O Space	*/
+#define PCMCIA_PRS_DMA		0x00000020	/* DMA, normal transfer */
+#define PCMCIA_PRS_DMA_LAST	0x00000028	/* DMA, last transactn	*/
+#define PCMCIA_PRS_CEx		0x00000030	/* A[22:23] ==> CE1,CE2 */
+
+#define PCMCIA_PSLOT_A		0x00000000	/* Slot A		*/
+#define PCMCIA_PSLOT_B		0x00000004	/* Slot B		*/
+#define PCMCIA_WPROT		0x00000002	/* Write Protect	*/
+#define PCMCIA_PV		0x00000001	/* Valid Bit		*/
+
+#define UPMA	0x00000000
+#define UPMB	0x00800000
+
+#endif	/* __MPCXX_H__ */
diff --git a/qemu/roms/u-boot/include/mpc8xx_irq.h b/qemu/roms/u-boot/include/mpc8xx_irq.h
new file mode 100644
index 000000000..15cf693fa
--- /dev/null
+++ b/qemu/roms/u-boot/include/mpc8xx_irq.h
@@ -0,0 +1,59 @@
+#ifndef _MPC8XX_IRQ_H
+#define _MPC8XX_IRQ_H
+
+/* The MPC8xx cores have 16 possible interrupts.  There are eight
+ * possible level sensitive interrupts assigned and generated internally
+ * from such devices as CPM, PCMCIA, RTC, PIT, TimeBase and Decrementer.
+ * There are eight external interrupts (IRQs) that can be configured
+ * as either level or edge sensitive.
+ *
+ * On some implementations, there is also the possibility of an 8259
+ * through the PCI and PCI-ISA bridges.
+ *
+ * We don't support the 8259 (yet).
+ */
+#define NR_SIU_INTS	16
+#define	NR_8259_INTS	0
+
+#define NR_IRQS	(NR_SIU_INTS + NR_8259_INTS)
+
+/* These values must be zero-based and map 1:1 with the SIU configuration.
+ * They are used throughout the 8xx I/O subsystem to generate
+ * interrupt masks, flags, and other control patterns.  This is why the
+ * current kernel assumption of the 8259 as the base controller is such
+ * a pain in the butt.
+ */
+#define	SIU_IRQ0	(0)	/* Highest priority */
+#define	SIU_LEVEL0	(1)
+#define	SIU_IRQ1	(2)
+#define	SIU_LEVEL1	(3)
+#define	SIU_IRQ2	(4)
+#define	SIU_LEVEL2	(5)
+#define	SIU_IRQ3	(6)
+#define	SIU_LEVEL3	(7)
+#define	SIU_IRQ4	(8)
+#define	SIU_LEVEL4	(9)
+#define	SIU_IRQ5	(10)
+#define	SIU_LEVEL5	(11)
+#define	SIU_IRQ6	(12)
+#define	SIU_LEVEL6	(13)
+#define	SIU_IRQ7	(14)
+#define	SIU_LEVEL7	(15)
+
+/* The internal interrupts we can configure as we see fit.
+ * My personal preference is CPM at level 2, which puts it above the
+ * MBX PCI/ISA/IDE interrupts.
+ */
+
+#ifdef CONFIG_SYS_CPM_INTERRUPT
+# define CPM_INTERRUPT		CONFIG_SYS_CPM_INTERRUPT
+#else
+# define CPM_INTERRUPT		SIU_LEVEL2
+#endif
+
+/* Some internal interrupt registers use an 8-bit mask for the interrupt
+ * level instead of a number.
+ */
+#define	mk_int_int_mask(IL) (1 << (7 - (IL/2)))
+
+#endif /* _MPC8XX_IRQ_H */
diff --git a/qemu/roms/u-boot/include/msc01.h b/qemu/roms/u-boot/include/msc01.h
new file mode 100644
index 000000000..37cf963f1
--- /dev/null
+++ b/qemu/roms/u-boot/include/msc01.h
@@ -0,0 +1,135 @@
+/*
+ * Copyright (C) 2013 Imagination Technologies
+ * Author: Paul Burton <paul.burton@imgtec.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MSC01_H__
+#define __MSC01_H__
+
+/*
+ * Bus Interface Unit
+ */
+
+#define MSC01_BIU_IP1BAS1L_OFS		0x0208
+#define MSC01_BIU_IP1MSK1L_OFS		0x0218
+#define MSC01_BIU_IP1BAS2L_OFS		0x0248
+#define MSC01_BIU_IP1MSK2L_OFS		0x0258
+#define MSC01_BIU_IP2BAS1L_OFS		0x0288
+#define MSC01_BIU_IP2MSK1L_OFS		0x0298
+#define MSC01_BIU_IP2BAS2L_OFS		0x02c8
+#define MSC01_BIU_IP2MSK2L_OFS		0x02d8
+#define MSC01_BIU_IP3BAS1L_OFS		0x0308
+#define MSC01_BIU_IP3MSK1L_OFS		0x0318
+#define MSC01_BIU_IP3BAS2L_OFS		0x0348
+#define MSC01_BIU_IP3MSK2L_OFS		0x0358
+#define MSC01_BIU_MCBAS1L_OFS		0x0388
+#define MSC01_BIU_MCMSK1L_OFS		0x0398
+#define MSC01_BIU_MCBAS2L_OFS		0x03c8
+#define MSC01_BIU_MCMSK2L_OFS		0x03d8
+
+/*
+ * PCI Bridge
+ */
+
+#define MSC01_PCI_SC2PMBASL_OFS		0x0208
+#define MSC01_PCI_SC2PMMSKL_OFS		0x0218
+#define MSC01_PCI_SC2PMMAPL_OFS		0x0228
+#define MSC01_PCI_SC2PIOBASL_OFS	0x0248
+#define MSC01_PCI_SC2PIOMSKL_OFS	0x0258
+#define MSC01_PCI_SC2PIOMAPL_OFS	0x0268
+#define MSC01_PCI_P2SCMSKL_OFS		0x0308
+#define MSC01_PCI_P2SCMAPL_OFS		0x0318
+#define MSC01_PCI_INTSTAT_OFS		0x0608
+#define MSC01_PCI_CFGADDR_OFS		0x0610
+#define MSC01_PCI_CFGDATA_OFS		0x0618
+#define MSC01_PCI_HEAD0_OFS		0x2000
+#define MSC01_PCI_HEAD1_OFS		0x2008
+#define MSC01_PCI_HEAD2_OFS		0x2010
+#define MSC01_PCI_HEAD3_OFS		0x2018
+#define MSC01_PCI_HEAD4_OFS		0x2020
+#define MSC01_PCI_HEAD5_OFS		0x2028
+#define MSC01_PCI_HEAD6_OFS		0x2030
+#define MSC01_PCI_HEAD7_OFS		0x2038
+#define MSC01_PCI_HEAD8_OFS		0x2040
+#define MSC01_PCI_HEAD9_OFS		0x2048
+#define MSC01_PCI_HEAD10_OFS		0x2050
+#define MSC01_PCI_HEAD11_OFS		0x2058
+#define MSC01_PCI_HEAD12_OFS		0x2060
+#define MSC01_PCI_HEAD13_OFS		0x2068
+#define MSC01_PCI_HEAD14_OFS		0x2070
+#define MSC01_PCI_HEAD15_OFS		0x2078
+#define MSC01_PCI_BAR0_OFS		0x2220
+#define MSC01_PCI_CFG_OFS		0x2380
+#define MSC01_PCI_SWAP_OFS		0x2388
+
+#define MSC01_PCI_SC2PMMSKL_MSK_MSK	0xff000000
+#define MSC01_PCI_SC2PIOMSKL_MSK_MSK	0xff000000
+
+#define MSC01_PCI_INTSTAT_TA_SHF	6
+#define MSC01_PCI_INTSTAT_TA_MSK	(0x1 << MSC01_PCI_INTSTAT_TA_SHF)
+#define MSC01_PCI_INTSTAT_MA_SHF	7
+#define MSC01_PCI_INTSTAT_MA_MSK	(0x1 << MSC01_PCI_INTSTAT_MA_SHF)
+
+#define MSC01_PCI_CFGADDR_BNUM_SHF	16
+#define MSC01_PCI_CFGADDR_BNUM_MSK	(0xff << MSC01_PCI_CFGADDR_BNUM_SHF)
+#define MSC01_PCI_CFGADDR_DNUM_SHF	11
+#define MSC01_PCI_CFGADDR_DNUM_MSK	(0x1f << MSC01_PCI_CFGADDR_DNUM_SHF)
+#define MSC01_PCI_CFGADDR_FNUM_SHF	8
+#define MSC01_PCI_CFGADDR_FNUM_MSK	(0x3 << MSC01_PCI_CFGADDR_FNUM_SHF)
+#define MSC01_PCI_CFGADDR_RNUM_SHF	2
+#define MSC01_PCI_CFGADDR_RNUM_MSK	(0x3f << MSC01_PCI_CFGADDR_RNUM_SHF)
+
+#define MSC01_PCI_HEAD0_VENDORID_SHF	0
+#define MSC01_PCI_HEAD0_DEVICEID_SHF	16
+
+#define MSC01_PCI_HEAD2_REV_SHF		0
+#define MSC01_PCI_HEAD2_CLASS_SHF	16
+
+#define MSC01_PCI_CFG_EN_SHF		15
+#define MSC01_PCI_CFG_EN_MSK		(0x1 << MSC01_PCI_CFG_EN_SHF)
+#define MSC01_PCI_CFG_G_SHF		16
+#define MSC01_PCI_CFG_G_MSK		(0x1 << MSC01_PCI_CFG_G_SHF)
+#define MSC01_PCI_CFG_RA_SHF		17
+#define MSC01_PCI_CFG_RA_MSK		(0x1 << MSC01_PCI_CFG_RA_SHF)
+
+#define MSC01_PCI_SWAP_BAR0_BSWAP_SHF	0
+#define MSC01_PCI_SWAP_IO_BSWAP_SHF	18
+
+/*
+ * Peripheral Bus Controller
+ */
+
+#define MSC01_PBC_CLKCFG_OFS		0x0100
+#define MSC01_PBC_CS0CFG_OFS		0x0400
+#define MSC01_PBC_CS0TIM_OFS		0x0500
+#define MSC01_PBC_CS0RW_OFS		0x0600
+
+#define MSC01_PBC_CLKCFG_SHF		0
+#define MSC01_PBC_CLKCFG_MSK		(0x1f << MSC01_PBC_CLKCFG_SHF)
+
+#define MSC01_PBC_CS0CFG_WS_SHF		0
+#define MSC01_PBC_CS0CFG_WS_MSK		(0x1f << MSC01_PBC_CS0CFG_WS_SHF)
+#define MSC01_PBC_CS0CFG_WSIDLE_SHF	8
+#define MSC01_PBC_CS0CFG_WSIDLE_MSK	(0x1f << MSC01_PBC_CS0CFG_WSIDLE_SHF)
+#define MSC01_PBC_CS0CFG_DTYP_SHF	16
+#define MSC01_PBC_CS0CFG_DTYP_MSK	(0x3 << MSC01_PBC_CS0CFG_DTYP_SHF)
+#define MSC01_PBC_CS0CFG_ADM_SHF	20
+#define MSC01_PBC_CS0CFG_ADM_MSK	(0x1 << MSC01_PBC_CS0CFG_ADM_SHF)
+
+#define MSC01_PBC_CS0TIM_CAT_SHF	0
+#define MSC01_PBC_CS0TIM_CAT_MSK	(0x1f << MSC01_PBC_CS0TIM_CAT_SHF)
+#define MSC01_PBC_CS0TIM_CDT_SHF	8
+#define MSC01_PBC_CS0TIM_CDT_MSK	(0x1f << MSC01_PBC_CS0TIM_CDT_SHF)
+
+#define MSC01_PBC_CS0RW_WAT_SHF		0
+#define MSC01_PBC_CS0RW_WAT_MSK		(0x1f << MSC01_PBC_CS0RW_WAT_SHF)
+#define MSC01_PBC_CS0RW_WDT_SHF		8
+#define MSC01_PBC_CS0RW_WDT_MSK		(0x1f << MSC01_PBC_CS0RW_WDT_SHF)
+#define MSC01_PBC_CS0RW_RAT_SHF		16
+#define MSC01_PBC_CS0RW_RAT_MSK		(0x1f << MSC01_PBC_CS0RW_RAT_SHF)
+#define MSC01_PBC_CS0RW_RDT_SHF		24
+#define MSC01_PBC_CS0RW_RDT_MSK		(0x1f << MSC01_PBC_CS0RW_RDT_SHF)
+
+#endif /* __MSC01_H__ */
diff --git a/qemu/roms/u-boot/include/mtd/cfi_flash.h b/qemu/roms/u-boot/include/mtd/cfi_flash.h
new file mode 100644
index 000000000..048b4773f
--- /dev/null
+++ b/qemu/roms/u-boot/include/mtd/cfi_flash.h
@@ -0,0 +1,185 @@
+/*
+ * (C) Copyright 2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CFI_FLASH_H__
+#define __CFI_FLASH_H__
+
+#define FLASH_CMD_CFI			0x98
+#define FLASH_CMD_READ_ID		0x90
+#define FLASH_CMD_RESET			0xff
+#define FLASH_CMD_BLOCK_ERASE		0x20
+#define FLASH_CMD_ERASE_CONFIRM		0xD0
+#define FLASH_CMD_WRITE			0x40
+#define FLASH_CMD_PROTECT		0x60
+#define FLASH_CMD_SETUP			0x60
+#define FLASH_CMD_SET_CR_CONFIRM	0x03
+#define FLASH_CMD_PROTECT_SET		0x01
+#define FLASH_CMD_PROTECT_CLEAR		0xD0
+#define FLASH_CMD_CLEAR_STATUS		0x50
+#define FLASH_CMD_READ_STATUS		0x70
+#define FLASH_CMD_WRITE_TO_BUFFER	0xE8
+#define FLASH_CMD_WRITE_BUFFER_PROG	0xE9
+#define FLASH_CMD_WRITE_BUFFER_CONFIRM	0xD0
+
+#define FLASH_STATUS_DONE		0x80
+#define FLASH_STATUS_ESS		0x40
+#define FLASH_STATUS_ECLBS		0x20
+#define FLASH_STATUS_PSLBS		0x10
+#define FLASH_STATUS_VPENS		0x08
+#define FLASH_STATUS_PSS		0x04
+#define FLASH_STATUS_DPS		0x02
+#define FLASH_STATUS_R			0x01
+#define FLASH_STATUS_PROTECT		0x01
+
+#define AMD_CMD_RESET			0xF0
+#define AMD_CMD_WRITE			0xA0
+#define AMD_CMD_ERASE_START		0x80
+#define AMD_CMD_ERASE_SECTOR		0x30
+#define AMD_CMD_UNLOCK_START		0xAA
+#define AMD_CMD_UNLOCK_ACK		0x55
+#define AMD_CMD_WRITE_TO_BUFFER		0x25
+#define AMD_CMD_WRITE_BUFFER_CONFIRM	0x29
+#define AMD_CMD_SET_PPB_ENTRY		0xC0
+#define AMD_CMD_SET_PPB_EXIT_BC1	0x90
+#define AMD_CMD_SET_PPB_EXIT_BC2	0x00
+#define AMD_CMD_PPB_UNLOCK_BC1		0x80
+#define AMD_CMD_PPB_UNLOCK_BC2		0x30
+#define AMD_CMD_PPB_LOCK_BC1		0xA0
+#define AMD_CMD_PPB_LOCK_BC2		0x00
+
+#define AMD_STATUS_TOGGLE		0x40
+#define AMD_STATUS_ERROR		0x20
+
+#define ATM_CMD_UNLOCK_SECT		0x70
+#define ATM_CMD_SOFTLOCK_START		0x80
+#define ATM_CMD_LOCK_SECT		0x40
+
+#define FLASH_CONTINUATION_CODE		0x7F
+
+#define FLASH_OFFSET_MANUFACTURER_ID	0x00
+#define FLASH_OFFSET_DEVICE_ID		0x01
+#define FLASH_OFFSET_DEVICE_ID2		0x0E
+#define FLASH_OFFSET_DEVICE_ID3		0x0F
+#define FLASH_OFFSET_CFI		0x55
+#define FLASH_OFFSET_CFI_ALT		0x555
+#define FLASH_OFFSET_CFI_RESP		0x10
+#define FLASH_OFFSET_PRIMARY_VENDOR	0x13
+/* extended query table primary address */
+#define FLASH_OFFSET_EXT_QUERY_T_P_ADDR	0x15
+#define FLASH_OFFSET_WTOUT		0x1F
+#define FLASH_OFFSET_WBTOUT		0x20
+#define FLASH_OFFSET_ETOUT		0x21
+#define FLASH_OFFSET_CETOUT		0x22
+#define FLASH_OFFSET_WMAX_TOUT		0x23
+#define FLASH_OFFSET_WBMAX_TOUT		0x24
+#define FLASH_OFFSET_EMAX_TOUT		0x25
+#define FLASH_OFFSET_CEMAX_TOUT		0x26
+#define FLASH_OFFSET_SIZE		0x27
+#define FLASH_OFFSET_INTERFACE		0x28
+#define FLASH_OFFSET_BUFFER_SIZE	0x2A
+#define FLASH_OFFSET_NUM_ERASE_REGIONS	0x2C
+#define FLASH_OFFSET_ERASE_REGIONS	0x2D
+#define FLASH_OFFSET_PROTECT		0x02
+#define FLASH_OFFSET_USER_PROTECTION	0x85
+#define FLASH_OFFSET_INTEL_PROTECTION	0x81
+
+#define CFI_CMDSET_NONE			0
+#define CFI_CMDSET_INTEL_EXTENDED	1
+#define CFI_CMDSET_AMD_STANDARD		2
+#define CFI_CMDSET_INTEL_STANDARD	3
+#define CFI_CMDSET_AMD_EXTENDED		4
+#define CFI_CMDSET_MITSU_STANDARD	256
+#define CFI_CMDSET_MITSU_EXTENDED	257
+#define CFI_CMDSET_SST			258
+#define CFI_CMDSET_INTEL_PROG_REGIONS	512
+
+#ifdef CONFIG_SYS_FLASH_CFI_AMD_RESET /* needed for STM_ID_29W320DB on UC100 */
+# undef  FLASH_CMD_RESET
+# define FLASH_CMD_RESET	AMD_CMD_RESET /* use AMD-Reset instead */
+#endif
+
+#define NUM_ERASE_REGIONS	4 /* max. number of erase regions */
+
+typedef union {
+	unsigned char c;
+	unsigned short w;
+	unsigned long l;
+	unsigned long long ll;
+} cfiword_t;
+
+/* CFI standard query structure */
+/* The offsets and sizes of this packed structure members correspond
+ * to the actual layout in CFI Flash chips. Some 16- and 32-bit members
+ * are unaligned and must be accessed with explicit unaligned access macros.
+ */
+struct cfi_qry {
+	u8	qry[3];
+	u16	p_id;			/* unaligned */
+	u16	p_adr;			/* unaligned */
+	u16	a_id;			/* unaligned */
+	u16	a_adr;			/* unaligned */
+	u8	vcc_min;
+	u8	vcc_max;
+	u8	vpp_min;
+	u8	vpp_max;
+	u8	word_write_timeout_typ;
+	u8	buf_write_timeout_typ;
+	u8	block_erase_timeout_typ;
+	u8	chip_erase_timeout_typ;
+	u8	word_write_timeout_max;
+	u8	buf_write_timeout_max;
+	u8	block_erase_timeout_max;
+	u8	chip_erase_timeout_max;
+	u8	dev_size;
+	u16	interface_desc;		/* aligned */
+	u16	max_buf_write_size;	/* aligned */
+	u8	num_erase_regions;
+	u32	erase_region_info[NUM_ERASE_REGIONS];	/* unaligned */
+} __attribute__((packed));
+
+struct cfi_pri_hdr {
+	u8	pri[3];
+	u8	major_version;
+	u8	minor_version;
+} __attribute__((packed));
+
+#ifndef CONFIG_SYS_FLASH_BANKS_LIST
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+#endif
+
+/*
+ * CFI_MAX_FLASH_BANKS only used for flash_info struct declaration.
+ *
+ * Use CONFIG_SYS_MAX_FLASH_BANKS_DETECT if defined
+ */
+#if defined(CONFIG_SYS_MAX_FLASH_BANKS_DETECT)
+#define CONFIG_SYS_MAX_FLASH_BANKS	(cfi_flash_num_flash_banks)
+#define CFI_MAX_FLASH_BANKS	CONFIG_SYS_MAX_FLASH_BANKS_DETECT
+/* board code can update this variable before CFI detection */
+extern int cfi_flash_num_flash_banks;
+#else
+#define CFI_MAX_FLASH_BANKS	CONFIG_SYS_MAX_FLASH_BANKS
+#endif
+
+void flash_write_cmd(flash_info_t * info, flash_sect_t sect,
+		     uint offset, u32 cmd);
+phys_addr_t cfi_flash_bank_addr(int i);
+unsigned long cfi_flash_bank_size(int i);
+void flash_cmd_reset(flash_info_t *info);
+
+#ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+void flash_write8(u8 value, void *addr);
+void flash_write16(u16 value, void *addr);
+void flash_write32(u32 value, void *addr);
+void flash_write64(u64 value, void *addr);
+u8 flash_read8(void *addr);
+u16 flash_read16(void *addr);
+u32 flash_read32(void *addr);
+u64 flash_read64(void *addr);
+#endif
+
+#endif /* __CFI_FLASH_H__ */
diff --git a/qemu/roms/u-boot/include/mtd/mtd-abi.h b/qemu/roms/u-boot/include/mtd/mtd-abi.h
new file mode 100644
index 000000000..ac3c29876
--- /dev/null
+++ b/qemu/roms/u-boot/include/mtd/mtd-abi.h
@@ -0,0 +1,197 @@
+/*
+ * $Id: mtd-abi.h,v 1.13 2005/11/07 11:14:56 gleixner Exp $
+ *
+ * Portions of MTD ABI definition which are shared by kernel and user space
+ */
+
+#ifndef __MTD_ABI_H__
+#define __MTD_ABI_H__
+
+#if 1
+#include <linux/compat.h>
+#endif
+
+#include <linux/compiler.h>
+
+struct erase_info_user {
+	uint32_t start;
+	uint32_t length;
+};
+
+struct mtd_oob_buf {
+	uint32_t start;
+	uint32_t length;
+	unsigned char __user *ptr;
+};
+
+/*
+ * MTD operation modes
+ *
+ * @MTD_OPS_PLACE_OOB:	OOB data are placed at the given offset (default)
+ * @MTD_OPS_AUTO_OOB:	OOB data are automatically placed at the free areas
+ *			which are defined by the internal ecclayout
+ * @MTD_OPS_RAW:	data are transferred as-is, with no error correction;
+ *			this mode implies %MTD_OPS_PLACE_OOB
+ *
+ * These modes can be passed to ioctl(MEMWRITE) and are also used internally.
+ * See notes on "MTD file modes" for discussion on %MTD_OPS_RAW vs.
+ * %MTD_FILE_MODE_RAW.
+ */
+enum {
+	MTD_OPS_PLACE_OOB = 0,
+	MTD_OPS_AUTO_OOB = 1,
+	MTD_OPS_RAW = 2,
+};
+
+#define MTD_ABSENT		0
+#define MTD_RAM			1
+#define MTD_ROM			2
+#define MTD_NORFLASH		3
+#define MTD_NANDFLASH		4
+#define MTD_DATAFLASH		6
+#define MTD_UBIVOLUME		7
+
+#define MTD_WRITEABLE		0x400	/* Device is writeable */
+#define MTD_BIT_WRITEABLE	0x800	/* Single bits can be flipped */
+#define MTD_NO_ERASE		0x1000	/* No erase necessary */
+#define MTD_STUPID_LOCK		0x2000	/* Always locked after reset */
+
+/* Some common devices / combinations of capabilities */
+#define MTD_CAP_ROM		0
+#define MTD_CAP_RAM		(MTD_WRITEABLE | MTD_BIT_WRITEABLE | MTD_NO_ERASE)
+#define MTD_CAP_NORFLASH	(MTD_WRITEABLE | MTD_BIT_WRITEABLE)
+#define MTD_CAP_NANDFLASH	(MTD_WRITEABLE)
+
+/* ECC byte placement */
+#define MTD_NANDECC_OFF		0	/* Switch off ECC (Not recommended) */
+#define MTD_NANDECC_PLACE	1	/* Use the given placement in the structure (YAFFS1 legacy mode) */
+#define MTD_NANDECC_AUTOPLACE	2	/* Use the default placement scheme */
+#define MTD_NANDECC_PLACEONLY	3	/* Use the given placement in the structure (Do not store ecc result on read) */
+#define MTD_NANDECC_AUTOPL_USR	4	/* Use the given autoplacement scheme rather than using the default */
+
+/* OTP mode selection */
+#define MTD_OTP_OFF		0
+#define MTD_OTP_FACTORY		1
+#define MTD_OTP_USER		2
+
+struct mtd_info_user {
+	uint8_t type;
+	uint32_t flags;
+	uint32_t size;			/* Total size of the MTD */
+	uint32_t erasesize;
+	uint32_t writesize;
+	uint32_t oobsize;		/* Amount of OOB data per block (e.g. 16) */
+	/* The below two fields are obsolete and broken, do not use them
+	 * (TODO: remove at some point) */
+	uint32_t ecctype;
+	uint32_t eccsize;
+};
+
+struct region_info_user {
+	uint32_t offset;		/* At which this region starts,
+					 * from the beginning of the MTD */
+	uint32_t erasesize;		/* For this region */
+	uint32_t numblocks;		/* Number of blocks in this region */
+	uint32_t regionindex;
+};
+
+struct otp_info {
+	uint32_t start;
+	uint32_t length;
+	uint32_t locked;
+};
+
+/* Get basic MTD characteristics info (better to use sysfs) */
+#define MEMGETINFO		_IOR('M', 1, struct mtd_info_user)
+/* Erase segment of MTD */
+#define MEMERASE		_IOW('M', 2, struct erase_info_user)
+/* Write out-of-band data from MTD */
+#define MEMWRITEOOB		_IOWR('M', 3, struct mtd_oob_buf)
+/* Read out-of-band data from MTD */
+#define MEMREADOOB		_IOWR('M', 4, struct mtd_oob_buf)
+/* Lock a chip (for MTD that supports it) */
+#define MEMLOCK			_IOW('M', 5, struct erase_info_user)
+/* Unlock a chip (for MTD that supports it) */
+#define MEMUNLOCK		_IOW('M', 6, struct erase_info_user)
+/* Get the number of different erase regions */
+#define MEMGETREGIONCOUNT	_IOR('M', 7, int)
+/* Get information about the erase region for a specific index */
+#define MEMGETREGIONINFO	_IOWR('M', 8, struct region_info_user)
+/* Get info about OOB modes (e.g., RAW, PLACE, AUTO) - legacy interface */
+#define MEMSETOOBSEL		_IOW('M', 9, struct nand_oobinfo)
+#define MEMGETOOBSEL		_IOR('M', 10, struct nand_oobinfo)
+/* Check if an eraseblock is bad */
+#define MEMGETBADBLOCK		_IOW('M', 11, loff_t)
+/* Mark an eraseblock as bad */
+#define MEMSETBADBLOCK		_IOW('M', 12, loff_t)
+/* Set OTP (One-Time Programmable) mode (factory vs. user) */
+#define OTPSELECT		_IOR('M', 13, int)
+/* Get number of OTP (One-Time Programmable) regions */
+#define OTPGETREGIONCOUNT	_IOW('M', 14, int)
+/* Get all OTP (One-Time Programmable) info about MTD */
+#define OTPGETREGIONINFO	_IOW('M', 15, struct otp_info)
+/* Lock a given range of user data (must be in mode %MTD_FILE_MODE_OTP_USER) */
+#define OTPLOCK			_IOR('M', 16, struct otp_info)
+/* Get ECC layout (deprecated) */
+#define ECCGETLAYOUT		_IOR('M', 17, struct nand_ecclayout)
+/* Get statistics about corrected/uncorrected errors */
+#define ECCGETSTATS		_IOR('M', 18, struct mtd_ecc_stats)
+/* Set MTD mode on a per-file-descriptor basis (see "MTD file modes") */
+#define MTDFILEMODE		_IO('M', 19)
+
+/*
+ * Obsolete legacy interface. Keep it in order not to break userspace
+ * interfaces
+ */
+struct nand_oobinfo {
+	uint32_t useecc;
+	uint32_t eccbytes;
+	uint32_t oobfree[8][2];
+	uint32_t eccpos[48];
+};
+
+struct nand_oobfree {
+	uint32_t offset;
+	uint32_t length;
+};
+
+/**
+ * struct mtd_ecc_stats - error correction stats
+ *
+ * @corrected:	number of corrected bits
+ * @failed:	number of uncorrectable errors
+ * @badblocks:	number of bad blocks in this partition
+ * @bbtblocks:	number of blocks reserved for bad block tables
+ */
+struct mtd_ecc_stats {
+	uint32_t corrected;
+	uint32_t failed;
+	uint32_t badblocks;
+	uint32_t bbtblocks;
+};
+
+/*
+ * MTD file modes - for read/write access to MTD
+ *
+ * @MTD_FILE_MODE_NORMAL:	OTP disabled, ECC enabled
+ * @MTD_FILE_MODE_OTP_FACTORY:	OTP enabled in factory mode
+ * @MTD_FILE_MODE_OTP_USER:	OTP enabled in user mode
+ * @MTD_FILE_MODE_RAW:		OTP disabled, ECC disabled
+ *
+ * These modes can be set via ioctl(MTDFILEMODE). The mode mode will be retained
+ * separately for each open file descriptor.
+ *
+ * Note: %MTD_FILE_MODE_RAW provides the same functionality as %MTD_OPS_RAW -
+ * raw access to the flash, without error correction or autoplacement schemes.
+ * Wherever possible, the MTD_OPS_* mode will override the MTD_FILE_MODE_* mode
+ * (e.g., when using ioctl(MEMWRITE)), but in some cases, the MTD_FILE_MODE is
+ * used out of necessity (e.g., `write()', ioctl(MEMWRITEOOB64)).
+ */
+enum mtd_file_modes {
+	MTD_MODE_NORMAL = MTD_OTP_OFF,
+	MTD_MODE_OTP_FACTORY = MTD_OTP_FACTORY,
+	MTD_MODE_OTP_USER = MTD_OTP_USER,
+	MTD_MODE_RAW,
+};
+
+#endif /* __MTD_ABI_H__ */
diff --git a/qemu/roms/u-boot/include/mtd/ubi-user.h b/qemu/roms/u-boot/include/mtd/ubi-user.h
new file mode 100644
index 000000000..1ccc06ea6
--- /dev/null
+++ b/qemu/roms/u-boot/include/mtd/ubi-user.h
@@ -0,0 +1,256 @@
+/*
+ * Copyright (c) International Business Machines Corp., 2006
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Author: Artem Bityutskiy (Битюцкий �ртём)
+ */
+
+#ifndef __UBI_USER_H__
+#define __UBI_USER_H__
+
+/*
+ * UBI device creation (the same as MTD device attachment)
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ * MTD devices may be attached using %UBI_IOCATT ioctl command of the UBI
+ * control device. The caller has to properly fill and pass
+ * &struct ubi_attach_req object - UBI will attach the MTD device specified in
+ * the request and return the newly created UBI device number as the ioctl
+ * return value.
+ *
+ * UBI device deletion (the same as MTD device detachment)
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ * An UBI device maybe deleted with %UBI_IOCDET ioctl command of the UBI
+ * control device.
+ *
+ * UBI volume creation
+ * ~~~~~~~~~~~~~~~~~~~
+ *
+ * UBI volumes are created via the %UBI_IOCMKVOL IOCTL command of UBI character
+ * device. A &struct ubi_mkvol_req object has to be properly filled and a
+ * pointer to it has to be passed to the IOCTL.
+ *
+ * UBI volume deletion
+ * ~~~~~~~~~~~~~~~~~~~
+ *
+ * To delete a volume, the %UBI_IOCRMVOL IOCTL command of the UBI character
+ * device should be used. A pointer to the 32-bit volume ID hast to be passed
+ * to the IOCTL.
+ *
+ * UBI volume re-size
+ * ~~~~~~~~~~~~~~~~~~
+ *
+ * To re-size a volume, the %UBI_IOCRSVOL IOCTL command of the UBI character
+ * device should be used. A &struct ubi_rsvol_req object has to be properly
+ * filled and a pointer to it has to be passed to the IOCTL.
+ *
+ * UBI volume update
+ * ~~~~~~~~~~~~~~~~~
+ *
+ * Volume update should be done via the %UBI_IOCVOLUP IOCTL command of the
+ * corresponding UBI volume character device. A pointer to a 64-bit update
+ * size should be passed to the IOCTL. After this, UBI expects user to write
+ * this number of bytes to the volume character device. The update is finished
+ * when the claimed number of bytes is passed. So, the volume update sequence
+ * is something like:
+ *
+ * fd = open("/dev/my_volume");
+ * ioctl(fd, UBI_IOCVOLUP, &image_size);
+ * write(fd, buf, image_size);
+ * close(fd);
+ *
+ * Atomic eraseblock change
+ * ~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ * Atomic eraseblock change operation is done via the %UBI_IOCEBCH IOCTL
+ * command of the corresponding UBI volume character device. A pointer to
+ * &struct ubi_leb_change_req has to be passed to the IOCTL. Then the user is
+ * expected to write the requested amount of bytes. This is similar to the
+ * "volume update" IOCTL.
+ */
+
+/*
+ * When a new UBI volume or UBI device is created, users may either specify the
+ * volume/device number they want to create or to let UBI automatically assign
+ * the number using these constants.
+ */
+#define UBI_VOL_NUM_AUTO (-1)
+#define UBI_DEV_NUM_AUTO (-1)
+
+/* Maximum volume name length */
+#define UBI_MAX_VOLUME_NAME 127
+
+/* IOCTL commands of UBI character devices */
+
+#define UBI_IOC_MAGIC 'o'
+
+/* Create an UBI volume */
+#define UBI_IOCMKVOL _IOW(UBI_IOC_MAGIC, 0, struct ubi_mkvol_req)
+/* Remove an UBI volume */
+#define UBI_IOCRMVOL _IOW(UBI_IOC_MAGIC, 1, int32_t)
+/* Re-size an UBI volume */
+#define UBI_IOCRSVOL _IOW(UBI_IOC_MAGIC, 2, struct ubi_rsvol_req)
+
+/* IOCTL commands of the UBI control character device */
+
+#define UBI_CTRL_IOC_MAGIC 'o'
+
+/* Attach an MTD device */
+#define UBI_IOCATT _IOW(UBI_CTRL_IOC_MAGIC, 64, struct ubi_attach_req)
+/* Detach an MTD device */
+#define UBI_IOCDET _IOW(UBI_CTRL_IOC_MAGIC, 65, int32_t)
+
+/* IOCTL commands of UBI volume character devices */
+
+#define UBI_VOL_IOC_MAGIC 'O'
+
+/* Start UBI volume update */
+#define UBI_IOCVOLUP _IOW(UBI_VOL_IOC_MAGIC, 0, int64_t)
+/* An eraseblock erasure command, used for debugging, disabled by default */
+#define UBI_IOCEBER _IOW(UBI_VOL_IOC_MAGIC, 1, int32_t)
+/* An atomic eraseblock change command */
+#define UBI_IOCEBCH _IOW(UBI_VOL_IOC_MAGIC, 2, int32_t)
+
+/* Maximum MTD device name length supported by UBI */
+#define MAX_UBI_MTD_NAME_LEN 127
+
+/*
+ * UBI data type hint constants.
+ *
+ * UBI_LONGTERM: long-term data
+ * UBI_SHORTTERM: short-term data
+ * UBI_UNKNOWN: data persistence is unknown
+ *
+ * These constants are used when data is written to UBI volumes in order to
+ * help the UBI wear-leveling unit to find more appropriate physical
+ * eraseblocks.
+ */
+enum {
+	UBI_LONGTERM  = 1,
+	UBI_SHORTTERM = 2,
+	UBI_UNKNOWN   = 3,
+};
+
+/*
+ * UBI volume type constants.
+ *
+ * @UBI_DYNAMIC_VOLUME: dynamic volume
+ * @UBI_STATIC_VOLUME:  static volume
+ */
+enum {
+	UBI_DYNAMIC_VOLUME = 3,
+	UBI_STATIC_VOLUME  = 4,
+};
+
+/**
+ * struct ubi_attach_req - attach MTD device request.
+ * @ubi_num: UBI device number to create
+ * @mtd_num: MTD device number to attach
+ * @vid_hdr_offset: VID header offset (use defaults if %0)
+ * @padding: reserved for future, not used, has to be zeroed
+ *
+ * This data structure is used to specify MTD device UBI has to attach and the
+ * parameters it has to use. The number which should be assigned to the new UBI
+ * device is passed in @ubi_num. UBI may automatically assign the number if
+ * @UBI_DEV_NUM_AUTO is passed. In this case, the device number is returned in
+ * @ubi_num.
+ *
+ * Most applications should pass %0 in @vid_hdr_offset to make UBI use default
+ * offset of the VID header within physical eraseblocks. The default offset is
+ * the next min. I/O unit after the EC header. For example, it will be offset
+ * 512 in case of a 512 bytes page NAND flash with no sub-page support. Or
+ * it will be 512 in case of a 2KiB page NAND flash with 4 512-byte sub-pages.
+ *
+ * But in rare cases, if this optimizes things, the VID header may be placed to
+ * a different offset. For example, the boot-loader might do things faster if the
+ * VID header sits at the end of the first 2KiB NAND page with 4 sub-pages. As
+ * the boot-loader would not normally need to read EC headers (unless it needs
+ * UBI in RW mode), it might be faster to calculate ECC. This is weird example,
+ * but it real-life example. So, in this example, @vid_hdr_offer would be
+ * 2KiB-64 bytes = 1984. Note, that this position is not even 512-bytes
+ * aligned, which is OK, as UBI is clever enough to realize this is 4th sub-page
+ * of the first page and add needed padding.
+ */
+struct ubi_attach_req {
+	int32_t ubi_num;
+	int32_t mtd_num;
+	int32_t vid_hdr_offset;
+	uint8_t padding[12];
+};
+
+/**
+ * struct ubi_mkvol_req - volume description data structure used in
+ *                        volume creation requests.
+ * @vol_id: volume number
+ * @alignment: volume alignment
+ * @bytes: volume size in bytes
+ * @vol_type: volume type (%UBI_DYNAMIC_VOLUME or %UBI_STATIC_VOLUME)
+ * @padding1: reserved for future, not used, has to be zeroed
+ * @name_len: volume name length
+ * @padding2: reserved for future, not used, has to be zeroed
+ * @name: volume name
+ *
+ * This structure is used by user-space programs when creating new volumes. The
+ * @used_bytes field is only necessary when creating static volumes.
+ *
+ * The @alignment field specifies the required alignment of the volume logical
+ * eraseblock. This means, that the size of logical eraseblocks will be aligned
+ * to this number, i.e.,
+ *	(UBI device logical eraseblock size) mod (@alignment) = 0.
+ *
+ * To put it differently, the logical eraseblock of this volume may be slightly
+ * shortened in order to make it properly aligned. The alignment has to be
+ * multiple of the flash minimal input/output unit, or %1 to utilize the entire
+ * available space of logical eraseblocks.
+ *
+ * The @alignment field may be useful, for example, when one wants to maintain
+ * a block device on top of an UBI volume. In this case, it is desirable to fit
+ * an integer number of blocks in logical eraseblocks of this UBI volume. With
+ * alignment it is possible to update this volume using plane UBI volume image
+ * BLOBs, without caring about how to properly align them.
+ */
+struct ubi_mkvol_req {
+	int32_t vol_id;
+	int32_t alignment;
+	int64_t bytes;
+	int8_t vol_type;
+	int8_t padding1;
+	int16_t name_len;
+	int8_t padding2[4];
+	char name[UBI_MAX_VOLUME_NAME + 1];
+} __attribute__ ((packed));
+
+/**
+ * struct ubi_rsvol_req - a data structure used in volume re-size requests.
+ * @vol_id: ID of the volume to re-size
+ * @bytes: new size of the volume in bytes
+ *
+ * Re-sizing is possible for both dynamic and static volumes. But while dynamic
+ * volumes may be re-sized arbitrarily, static volumes cannot be made to be
+ * smaller then the number of bytes they bear. To arbitrarily shrink a static
+ * volume, it must be wiped out first (by means of volume update operation with
+ * zero number of bytes).
+ */
+struct ubi_rsvol_req {
+	int64_t bytes;
+	int32_t vol_id;
+} __attribute__ ((packed));
+
+/**
+ * struct ubi_leb_change_req - a data structure used in atomic logical
+ *                             eraseblock change requests.
+ * @lnum: logical eraseblock number to change
+ * @bytes: how many bytes will be written to the logical eraseblock
+ * @dtype: data type (%UBI_LONGTERM, %UBI_SHORTTERM, %UBI_UNKNOWN)
+ * @padding: reserved for future, not used, has to be zeroed
+ */
+struct ubi_leb_change_req {
+	int32_t lnum;
+	int32_t bytes;
+	uint8_t dtype;
+	uint8_t padding[7];
+} __attribute__ ((packed));
+
+#endif /* __UBI_USER_H__ */
diff --git a/qemu/roms/u-boot/include/mtd_node.h b/qemu/roms/u-boot/include/mtd_node.h
new file mode 100644
index 000000000..5aae0859d
--- /dev/null
+++ b/qemu/roms/u-boot/include/mtd_node.h
@@ -0,0 +1,11 @@
+#ifndef _NODE_INFO
+#define _NODE_INFO
+
+/*
+ * Info we use to search for a flash node in DTB.
+ */
+struct node_info {
+	const char *compat;	/* compatible string */
+	int type;		/* mtd flash type */
+};
+#endif
diff --git a/qemu/roms/u-boot/include/mv88e6352.h b/qemu/roms/u-boot/include/mv88e6352.h
new file mode 100644
index 000000000..a34b43466
--- /dev/null
+++ b/qemu/roms/u-boot/include/mv88e6352.h
@@ -0,0 +1,76 @@
+/*
+ * (C) Copyright 2012
+ * Valentin Lontgchamp, Keymile AG, valentin.longchamp@keymile.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MV886352_H
+#define __MV886352_H
+
+#include <common.h>
+
+/* PHY registers */
+#define PHY(itf)	(itf)
+
+#define PHY_CTRL	0x00
+#define PHY_100_MBPS	0x2000
+#define PHY_1_GBPS	0x0040
+#define AUTONEG_EN	0x1000
+#define AUTONEG_RST	0x0200
+#define FULL_DUPLEX	0x0100
+#define PHY_PWR_DOWN	0x0800
+
+#define PHY_STATUS	0x01
+#define AN1000FIX	0x0001
+
+#define PHY_SPEC_CTRL	0x10
+#define SPEC_PWR_DOWN	0x0004
+#define AUTO_MDIX_EN	0x0060
+
+#define PHY_1000_CTRL	0x9
+
+#define NO_ADV		0x0000
+#define ADV_1000_FDPX	0x0200
+#define ADV_1000_HDPX	0x0100
+
+#define PHY_PAGE	0x16
+
+#define AN1000FIX_PAGE	0x00fc
+
+/* PORT or MAC registers */
+#define PORT(itf)	(itf+0x10)
+
+#define PORT_STATUS	0x00
+#define NO_PHY_DETECT	0x0000
+
+#define PORT_PHY	0x01
+#define RX_RGMII_TIM	0x8000
+#define TX_RGMII_TIM	0x4000
+#define FLOW_CTRL_EN	0x0080
+#define FLOW_CTRL_FOR	0x0040
+#define LINK_VAL	0x0020
+#define LINK_FOR	0x0010
+#define FULL_DPX	0x0008
+#define FULL_DPX_FOR	0x0004
+#define NO_SPEED_FOR	0x0003
+#define SPEED_1000_FOR	0x0002
+#define SPEED_100_FOR	0x0001
+#define SPEED_10_FOR	0x0000
+
+#define PORT_CTRL	0x04
+#define FORWARDING	0x0003
+#define EGRS_FLD_ALL	0x000c
+#define PORT_DIS	0x0000
+
+struct mv88e_sw_reg {
+	u8 port;
+	u8 reg;
+	u16 value;
+};
+
+int mv88e_sw_reset(const char *devname, u8 phy_addr);
+int mv88e_sw_program(const char *devname, u8 phy_addr,
+	struct mv88e_sw_reg *regs, int regs_nb);
+
+#endif
diff --git a/qemu/roms/u-boot/include/mvmfp.h b/qemu/roms/u-boot/include/mvmfp.h
new file mode 100644
index 000000000..961d79995
--- /dev/null
+++ b/qemu/roms/u-boot/include/mvmfp.h
@@ -0,0 +1,84 @@
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MVMFP_H
+#define __MVMFP_H
+
+/*
+ * Header file for MultiFunctionPin (MFP) Configururation framework
+ *
+ * Processors Supported:
+ * 1. Marvell ARMADA100 Processors
+ *
+ * processor to be supported should be added here
+ */
+
+/*
+ * MFP configuration is represented by a 32-bit unsigned integer
+ */
+#define MFP(_off, _pull, _pF, _drv, _dF, _edge, _eF, _afn, _aF) ( \
+	/* bits 31..16 - MFP Register Offset */	(((_off) & 0xffff) << 16) | \
+	/* bits 15..13 - Run Mode Pull State */	(((_pull) & 0x7) << 13) | \
+	/* bit  12     - Unused */ \
+	/* bits 11..10 - Driver Strength */	(((_drv) & 0x3) << 10) | \
+	/* bit  09     - Pull State flag */	(((_pF) & 0x1) << 9) | \
+	/* bit  08     - Drv-strength flag */	(((_dF) & 0x1) << 8) | \
+	/* bit  07     - Edge-det flag */	(((_eF) & 0x1) << 7) | \
+	/* bits 06..04 - Edge Detection */	(((_edge) & 0x7) << 4) | \
+	/* bits 03..00 - Alt-fun flag */	(((_aF) & 0x1) << 3) | \
+	/* bits Alternate-fun select */		((_afn) & 0x7))
+
+/*
+ * to facilitate the definition, the following macros are provided
+ *
+ * 				    offset, pull,pF, drv,dF, edge,eF ,afn,aF
+ */
+#define MFP_OFFSET_MASK		MFP(0xffff,    0,0,    0,0,     0,0,   0,0)
+#define MFP_REG(x)		MFP(x,         0,0,    0,0,     0,0,   0,0)
+#define MFP_REG_GET_OFFSET(x)	((x & MFP_OFFSET_MASK) >> 16)
+
+#define MFP_AF_FLAG		MFP(0x0000,    0,0,    0,0,     0,0,   0,1)
+#define MFP_DRIVE_FLAG		MFP(0x0000,    0,0,    0,1,     0,0,   0,0)
+#define MFP_EDGE_FLAG		MFP(0x0000,    0,0,    0,0,     0,1,   0,0)
+#define MFP_PULL_FLAG		MFP(0x0000,    0,1,    0,0,     0,0,   0,0)
+
+#define MFP_AF0			MFP(0x0000,    0,0,    0,0,     0,0,   0,1)
+#define MFP_AF1			MFP(0x0000,    0,0,    0,0,     0,0,   1,1)
+#define MFP_AF2			MFP(0x0000,    0,0,    0,0,     0,0,   2,1)
+#define MFP_AF3			MFP(0x0000,    0,0,    0,0,     0,0,   3,1)
+#define MFP_AF4			MFP(0x0000,    0,0,    0,0,     0,0,   4,1)
+#define MFP_AF5			MFP(0x0000,    0,0,    0,0,     0,0,   5,1)
+#define MFP_AF6			MFP(0x0000,    0,0,    0,0,     0,0,   6,1)
+#define MFP_AF7			MFP(0x0000,    0,0,    0,0,     0,0,   7,1)
+#define MFP_AF_MASK		MFP(0x0000,    0,0,    0,0,     0,0,   7,0)
+
+#define MFP_LPM_EDGE_NONE	MFP(0x0000,    0,0,    0,0,     0,1,   0,0)
+#define MFP_LPM_EDGE_RISE	MFP(0x0000,    0,0,    0,0,     1,1,   0,0)
+#define MFP_LPM_EDGE_FALL	MFP(0x0000,    0,0,    0,0,     2,1,   0,0)
+#define MFP_LPM_EDGE_BOTH	MFP(0x0000,    0,0,    0,0,     3,1,   0,0)
+#define MFP_LPM_EDGE_MASK	MFP(0x0000,    0,0,    0,0,     3,0,   0,0)
+
+#define MFP_DRIVE_VERY_SLOW	MFP(0x0000,    0,0,    0,1,     0,0,   0,0)
+#define MFP_DRIVE_SLOW		MFP(0x0000,    0,0,    1,1,     0,0,   0,0)
+#define MFP_DRIVE_MEDIUM	MFP(0x0000,    0,0,    2,1,     0,0,   0,0)
+#define MFP_DRIVE_FAST		MFP(0x0000,    0,0,    3,1,     0,0,   0,0)
+#define MFP_DRIVE_MASK		MFP(0x0000,    0,0,    3,0,     0,0,   0,0)
+
+#define MFP_PULL_NONE		MFP(0x0000,    0,1,    0,0,     0,0,   0,0)
+#define MFP_PULL_LOW		MFP(0x0000,    1,1,    0,0,     0,0,   0,0)
+#define MFP_PULL_HIGH		MFP(0x0000,    2,1,    0,0,     0,0,   0,0)
+#define MFP_PULL_BOTH		MFP(0x0000,    3,1,    0,0,     0,0,   0,0)
+#define MFP_PULL_FLOAT		MFP(0x0000,    4,1,    0,0,     0,0,   0,0)
+#define MFP_PULL_MASK		MFP(0x0000,    7,0,    0,0,     0,0,   0,0)
+
+#define MFP_EOC			0xffffffff	/* indicates end-of-conf */
+
+/* Functions */
+void mfp_config(u32 *mfp_cfgs);
+
+#endif /* __MVMFP_H */
diff --git a/qemu/roms/u-boot/include/nand.h b/qemu/roms/u-boot/include/nand.h
new file mode 100644
index 000000000..fc735d1ec
--- /dev/null
+++ b/qemu/roms/u-boot/include/nand.h
@@ -0,0 +1,169 @@
+/*
+ * (C) Copyright 2005
+ * 2N Telekomunikace, a.s. <www.2n.cz>
+ * Ladislav Michl <michl@2n.cz>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ */
+
+#ifndef _NAND_H_
+#define _NAND_H_
+
+#include <config.h>
+
+/*
+ * All boards using a given driver must convert to self-init
+ * at the same time, so do it here.  When all drivers are
+ * converted, this will go away.
+ */
+#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_NAND_FSL_ELBC) || defined(CONFIG_NAND_FSL_IFC)
+#define CONFIG_SYS_NAND_SELF_INIT
+#endif
+#else
+#if defined(CONFIG_NAND_FSL_ELBC) || defined(CONFIG_NAND_ATMEL)\
+	|| defined(CONFIG_NAND_FSL_IFC)
+#define CONFIG_SYS_NAND_SELF_INIT
+#endif
+#endif
+
+extern void nand_init(void);
+
+#include <linux/compat.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+
+#ifdef CONFIG_SYS_NAND_SELF_INIT
+void board_nand_init(void);
+int nand_register(int devnum);
+#else
+extern int board_nand_init(struct nand_chip *nand);
+#endif
+
+typedef struct mtd_info nand_info_t;
+
+extern int nand_curr_device;
+extern nand_info_t nand_info[];
+
+static inline int nand_read(nand_info_t *info, loff_t ofs, size_t *len, u_char *buf)
+{
+	return mtd_read(info, ofs, *len, (size_t *)len, buf);
+}
+
+static inline int nand_write(nand_info_t *info, loff_t ofs, size_t *len, u_char *buf)
+{
+	return mtd_write(info, ofs, *len, (size_t *)len, buf);
+}
+
+static inline int nand_block_isbad(nand_info_t *info, loff_t ofs)
+{
+	return mtd_block_isbad(info, ofs);
+}
+
+static inline int nand_erase(nand_info_t *info, loff_t off, size_t size)
+{
+	struct erase_info instr;
+
+	instr.mtd = info;
+	instr.addr = off;
+	instr.len = size;
+	instr.callback = 0;
+
+	return mtd_erase(info, &instr);
+}
+
+
+/*****************************************************************************
+ * declarations from nand_util.c
+ ****************************************************************************/
+
+struct nand_write_options {
+	u_char *buffer;		/* memory block containing image to write */
+	ulong length;		/* number of bytes to write */
+	ulong offset;		/* start address in NAND */
+	int quiet;		/* don't display progress messages */
+	int autoplace;		/* if true use auto oob layout */
+	int forcejffs2;		/* force jffs2 oob layout */
+	int forceyaffs;		/* force yaffs oob layout */
+	int noecc;		/* write without ecc */
+	int writeoob;		/* image contains oob data */
+	int pad;		/* pad to page size */
+	int blockalign;		/* 1|2|4 set multiple of eraseblocks
+				 * to align to */
+};
+
+typedef struct nand_write_options nand_write_options_t;
+typedef struct mtd_oob_ops mtd_oob_ops_t;
+
+struct nand_read_options {
+	u_char *buffer;		/* memory block in which read image is written*/
+	ulong length;		/* number of bytes to read */
+	ulong offset;		/* start address in NAND */
+	int quiet;		/* don't display progress messages */
+	int readoob;		/* put oob data in image */
+};
+
+typedef struct nand_read_options nand_read_options_t;
+
+struct nand_erase_options {
+	loff_t length;		/* number of bytes to erase */
+	loff_t offset;		/* first address in NAND to erase */
+	int quiet;		/* don't display progress messages */
+	int jffs2;		/* if true: format for jffs2 usage
+				 * (write appropriate cleanmarker blocks) */
+	int scrub;		/* if true, really clean NAND by erasing
+				 * bad blocks (UNSAFE) */
+
+	/* Don't include skipped bad blocks in size to be erased */
+	int spread;
+	/* maximum size that actual may be in order to not exceed the buf */
+	loff_t lim;
+};
+
+typedef struct nand_erase_options nand_erase_options_t;
+
+int nand_read_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
+		       size_t *actual, loff_t lim, u_char *buffer);
+
+#define WITH_YAFFS_OOB	(1 << 0) /* whether write with yaffs format. This flag
+				  * is a 'mode' meaning it cannot be mixed with
+				  * other flags */
+#define WITH_DROP_FFS	(1 << 1) /* drop trailing all-0xff pages */
+
+int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
+			size_t *actual, loff_t lim, u_char *buffer, int flags);
+int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts);
+int nand_torture(nand_info_t *nand, loff_t offset);
+
+#define NAND_LOCK_STATUS_TIGHT	0x01
+#define NAND_LOCK_STATUS_UNLOCK 0x04
+
+int nand_lock(nand_info_t *meminfo, int tight);
+int nand_unlock(nand_info_t *meminfo, loff_t start, size_t length,
+	int allexcept);
+int nand_get_lock_status(nand_info_t *meminfo, loff_t offset);
+
+int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst);
+void nand_deselect(void);
+
+#ifdef CONFIG_SYS_NAND_SELECT_DEVICE
+void board_nand_select_device(struct nand_chip *nand, int chip);
+#endif
+
+__attribute__((noreturn)) void nand_boot(void);
+
+#endif
+
+#ifdef CONFIG_ENV_OFFSET_OOB
+#define ENV_OOB_MARKER 0x30425645 /*"EVB0" in little-endian -- offset is stored
+				    as block number*/
+#define ENV_OOB_MARKER_OLD 0x30564e45 /*"ENV0" in little-endian -- offset is
+					stored as byte number */
+#define ENV_OFFSET_SIZE 8
+int get_nand_env_oob(nand_info_t *nand, unsigned long *result);
+#endif
diff --git a/qemu/roms/u-boot/include/net.h b/qemu/roms/u-boot/include/net.h
new file mode 100644
index 000000000..735b0b9d2
--- /dev/null
+++ b/qemu/roms/u-boot/include/net.h
@@ -0,0 +1,705 @@
+/*
+ *	LiMon Monitor (LiMon) - Network.
+ *
+ *	Copyright 1994 - 2000 Neil Russell.
+ *	(See License)
+ *
+ *
+ * History
+ *	9/16/00	  bor  adapted to TQM823L/STK8xxL board, RARP/TFTP boot added
+ */
+
+#ifndef __NET_H__
+#define __NET_H__
+
+#if defined(CONFIG_8xx)
+#include <commproc.h>
+#endif	/* CONFIG_8xx */
+
+#include <asm/cache.h>
+#include <asm/byteorder.h>	/* for nton* / ntoh* stuff */
+
+#define DEBUG_LL_STATE 0	/* Link local state machine changes */
+#define DEBUG_DEV_PKT 0		/* Packets or info directed to the device */
+#define DEBUG_NET_PKT 0		/* Packets on info on the network at large */
+#define DEBUG_INT_STATE 0	/* Internal network state changes */
+
+/*
+ *	The number of receive packet buffers, and the required packet buffer
+ *	alignment in memory.
+ *
+ */
+
+#ifdef CONFIG_SYS_RX_ETH_BUFFER
+# define PKTBUFSRX	CONFIG_SYS_RX_ETH_BUFFER
+#else
+# define PKTBUFSRX	4
+#endif
+
+#define PKTALIGN	ARCH_DMA_MINALIGN
+
+/* IPv4 addresses are always 32 bits in size */
+typedef __be32		IPaddr_t;
+
+
+/**
+ * An incoming packet handler.
+ * @param pkt    pointer to the application packet
+ * @param dport  destination UDP port
+ * @param sip    source IP address
+ * @param sport  source UDP port
+ * @param len    packet length
+ */
+typedef void rxhand_f(uchar *pkt, unsigned dport,
+		      IPaddr_t sip, unsigned sport,
+		      unsigned len);
+
+/**
+ * An incoming ICMP packet handler.
+ * @param type	ICMP type
+ * @param code	ICMP code
+ * @param dport	destination UDP port
+ * @param sip	source IP address
+ * @param sport	source UDP port
+ * @param pkt	pointer to the ICMP packet data
+ * @param len	packet length
+ */
+typedef void rxhand_icmp_f(unsigned type, unsigned code, unsigned dport,
+		IPaddr_t sip, unsigned sport, uchar *pkt, unsigned len);
+
+/*
+ *	A timeout handler.  Called after time interval has expired.
+ */
+typedef void	thand_f(void);
+
+enum eth_state_t {
+	ETH_STATE_INIT,
+	ETH_STATE_PASSIVE,
+	ETH_STATE_ACTIVE
+};
+
+struct eth_device {
+	char name[16];
+	unsigned char enetaddr[6];
+	int iobase;
+	int state;
+
+	int  (*init) (struct eth_device *, bd_t *);
+	int  (*send) (struct eth_device *, void *packet, int length);
+	int  (*recv) (struct eth_device *);
+	void (*halt) (struct eth_device *);
+#ifdef CONFIG_MCAST_TFTP
+	int (*mcast) (struct eth_device *, const u8 *enetaddr, u8 set);
+#endif
+	int  (*write_hwaddr) (struct eth_device *);
+	struct eth_device *next;
+	int index;
+	void *priv;
+};
+
+extern int eth_initialize(bd_t *bis);	/* Initialize network subsystem */
+extern int eth_register(struct eth_device* dev);/* Register network device */
+extern int eth_unregister(struct eth_device *dev);/* Remove network device */
+extern void eth_try_another(int first_restart);	/* Change the device */
+extern void eth_set_current(void);		/* set nterface to ethcur var */
+
+/* get the current device MAC */
+extern struct eth_device *eth_current;
+
+static inline __attribute__((always_inline))
+struct eth_device *eth_get_dev(void)
+{
+	return eth_current;
+}
+extern struct eth_device *eth_get_dev_by_name(const char *devname);
+extern struct eth_device *eth_get_dev_by_index(int index); /* get dev @ index */
+extern int eth_get_dev_index(void);		/* get the device index */
+extern void eth_parse_enetaddr(const char *addr, uchar *enetaddr);
+extern int eth_getenv_enetaddr(char *name, uchar *enetaddr);
+extern int eth_setenv_enetaddr(char *name, const uchar *enetaddr);
+
+/*
+ * Get the hardware address for an ethernet interface .
+ * Args:
+ *	base_name - base name for device (normally "eth")
+ *	index - device index number (0 for first)
+ *	enetaddr - returns 6 byte hardware address
+ * Returns:
+ *	Return true if the address is valid.
+ */
+extern int eth_getenv_enetaddr_by_index(const char *base_name, int index,
+					uchar *enetaddr);
+
+extern int usb_eth_initialize(bd_t *bi);
+extern int eth_init(bd_t *bis);			/* Initialize the device */
+extern int eth_send(void *packet, int length);	   /* Send a packet */
+
+#ifdef CONFIG_API
+extern int eth_receive(void *packet, int length); /* Receive a packet*/
+extern void (*push_packet)(void *packet, int length);
+#endif
+extern int eth_rx(void);			/* Check for received packets */
+extern void eth_halt(void);			/* stop SCC */
+extern char *eth_get_name(void);		/* get name of current device */
+
+/* Set active state */
+static inline __attribute__((always_inline)) int eth_init_state_only(bd_t *bis)
+{
+	eth_get_dev()->state = ETH_STATE_ACTIVE;
+
+	return 0;
+}
+/* Set passive state */
+static inline __attribute__((always_inline)) void eth_halt_state_only(void)
+{
+	eth_get_dev()->state = ETH_STATE_PASSIVE;
+}
+
+/*
+ * Set the hardware address for an ethernet interface based on 'eth%daddr'
+ * environment variable (or just 'ethaddr' if eth_number is 0).
+ * Args:
+ *	base_name - base name for device (normally "eth")
+ *	eth_number - value of %d (0 for first device of this type)
+ * Returns:
+ *	0 is success, non-zero is error status from driver.
+ */
+int eth_write_hwaddr(struct eth_device *dev, const char *base_name,
+		     int eth_number);
+
+#ifdef CONFIG_MCAST_TFTP
+int eth_mcast_join(IPaddr_t mcast_addr, u8 join);
+u32 ether_crc(size_t len, unsigned char const *p);
+#endif
+
+
+/**********************************************************************/
+/*
+ *	Protocol headers.
+ */
+
+/*
+ *	Ethernet header
+ */
+
+struct ethernet_hdr {
+	uchar		et_dest[6];	/* Destination node		*/
+	uchar		et_src[6];	/* Source node			*/
+	ushort		et_protlen;	/* Protocol or length		*/
+};
+
+/* Ethernet header size */
+#define ETHER_HDR_SIZE	(sizeof(struct ethernet_hdr))
+
+struct e802_hdr {
+	uchar		et_dest[6];	/* Destination node		*/
+	uchar		et_src[6];	/* Source node			*/
+	ushort		et_protlen;	/* Protocol or length		*/
+	uchar		et_dsap;	/* 802 DSAP			*/
+	uchar		et_ssap;	/* 802 SSAP			*/
+	uchar		et_ctl;		/* 802 control			*/
+	uchar		et_snap1;	/* SNAP				*/
+	uchar		et_snap2;
+	uchar		et_snap3;
+	ushort		et_prot;	/* 802 protocol			*/
+};
+
+/* 802 + SNAP + ethernet header size */
+#define E802_HDR_SIZE	(sizeof(struct e802_hdr))
+
+/*
+ *	Virtual LAN Ethernet header
+ */
+struct vlan_ethernet_hdr {
+	uchar		vet_dest[6];	/* Destination node		*/
+	uchar		vet_src[6];	/* Source node			*/
+	ushort		vet_vlan_type;	/* PROT_VLAN			*/
+	ushort		vet_tag;	/* TAG of VLAN			*/
+	ushort		vet_type;	/* protocol type		*/
+};
+
+/* VLAN Ethernet header size */
+#define VLAN_ETHER_HDR_SIZE	(sizeof(struct vlan_ethernet_hdr))
+
+#define PROT_IP		0x0800		/* IP protocol			*/
+#define PROT_ARP	0x0806		/* IP ARP protocol		*/
+#define PROT_RARP	0x8035		/* IP ARP protocol		*/
+#define PROT_VLAN	0x8100		/* IEEE 802.1q protocol		*/
+
+#define IPPROTO_ICMP	 1	/* Internet Control Message Protocol	*/
+#define IPPROTO_UDP	17	/* User Datagram Protocol		*/
+
+/*
+ *	Internet Protocol (IP) header.
+ */
+struct ip_hdr {
+	uchar		ip_hl_v;	/* header length and version	*/
+	uchar		ip_tos;		/* type of service		*/
+	ushort		ip_len;		/* total length			*/
+	ushort		ip_id;		/* identification		*/
+	ushort		ip_off;		/* fragment offset field	*/
+	uchar		ip_ttl;		/* time to live			*/
+	uchar		ip_p;		/* protocol			*/
+	ushort		ip_sum;		/* checksum			*/
+	IPaddr_t	ip_src;		/* Source IP address		*/
+	IPaddr_t	ip_dst;		/* Destination IP address	*/
+};
+
+#define IP_OFFS		0x1fff /* ip offset *= 8 */
+#define IP_FLAGS	0xe000 /* first 3 bits */
+#define IP_FLAGS_RES	0x8000 /* reserved */
+#define IP_FLAGS_DFRAG	0x4000 /* don't fragments */
+#define IP_FLAGS_MFRAG	0x2000 /* more fragments */
+
+#define IP_HDR_SIZE		(sizeof(struct ip_hdr))
+
+/*
+ *	Internet Protocol (IP) + UDP header.
+ */
+struct ip_udp_hdr {
+	uchar		ip_hl_v;	/* header length and version	*/
+	uchar		ip_tos;		/* type of service		*/
+	ushort		ip_len;		/* total length			*/
+	ushort		ip_id;		/* identification		*/
+	ushort		ip_off;		/* fragment offset field	*/
+	uchar		ip_ttl;		/* time to live			*/
+	uchar		ip_p;		/* protocol			*/
+	ushort		ip_sum;		/* checksum			*/
+	IPaddr_t	ip_src;		/* Source IP address		*/
+	IPaddr_t	ip_dst;		/* Destination IP address	*/
+	ushort		udp_src;	/* UDP source port		*/
+	ushort		udp_dst;	/* UDP destination port		*/
+	ushort		udp_len;	/* Length of UDP packet		*/
+	ushort		udp_xsum;	/* Checksum			*/
+};
+
+#define IP_UDP_HDR_SIZE		(sizeof(struct ip_udp_hdr))
+#define UDP_HDR_SIZE		(IP_UDP_HDR_SIZE - IP_HDR_SIZE)
+
+/*
+ *	Address Resolution Protocol (ARP) header.
+ */
+struct arp_hdr {
+	ushort		ar_hrd;		/* Format of hardware address	*/
+#   define ARP_ETHER	    1		/* Ethernet  hardware address	*/
+	ushort		ar_pro;		/* Format of protocol address	*/
+	uchar		ar_hln;		/* Length of hardware address	*/
+#   define ARP_HLEN	6
+	uchar		ar_pln;		/* Length of protocol address	*/
+#   define ARP_PLEN	4
+	ushort		ar_op;		/* Operation			*/
+#   define ARPOP_REQUEST    1		/* Request  to resolve  address	*/
+#   define ARPOP_REPLY	    2		/* Response to previous request	*/
+
+#   define RARPOP_REQUEST   3		/* Request  to resolve  address	*/
+#   define RARPOP_REPLY	    4		/* Response to previous request */
+
+	/*
+	 * The remaining fields are variable in size, according to
+	 * the sizes above, and are defined as appropriate for
+	 * specific hardware/protocol combinations.
+	 */
+	uchar		ar_data[0];
+#define ar_sha		ar_data[0]
+#define ar_spa		ar_data[ARP_HLEN]
+#define ar_tha		ar_data[ARP_HLEN + ARP_PLEN]
+#define ar_tpa		ar_data[ARP_HLEN + ARP_PLEN + ARP_HLEN]
+#if 0
+	uchar		ar_sha[];	/* Sender hardware address	*/
+	uchar		ar_spa[];	/* Sender protocol address	*/
+	uchar		ar_tha[];	/* Target hardware address	*/
+	uchar		ar_tpa[];	/* Target protocol address	*/
+#endif /* 0 */
+};
+
+#define ARP_HDR_SIZE	(8+20)		/* Size assuming ethernet	*/
+
+/*
+ * ICMP stuff (just enough to handle (host) redirect messages)
+ */
+#define ICMP_ECHO_REPLY		0	/* Echo reply			*/
+#define ICMP_NOT_REACH		3	/* Detination unreachable	*/
+#define ICMP_REDIRECT		5	/* Redirect (change route)	*/
+#define ICMP_ECHO_REQUEST	8	/* Echo request			*/
+
+/* Codes for REDIRECT. */
+#define ICMP_REDIR_NET		0	/* Redirect Net			*/
+#define ICMP_REDIR_HOST		1	/* Redirect Host		*/
+
+/* Codes for NOT_REACH */
+#define ICMP_NOT_REACH_PORT	3	/* Port unreachable		*/
+
+struct icmp_hdr {
+	uchar		type;
+	uchar		code;
+	ushort		checksum;
+	union {
+		struct {
+			ushort	id;
+			ushort	sequence;
+		} echo;
+		ulong	gateway;
+		struct {
+			ushort	unused;
+			ushort	mtu;
+		} frag;
+		uchar data[0];
+	} un;
+};
+
+#define ICMP_HDR_SIZE		(sizeof(struct icmp_hdr))
+#define IP_ICMP_HDR_SIZE	(IP_HDR_SIZE + ICMP_HDR_SIZE)
+
+/*
+ * Maximum packet size; used to allocate packet storage.
+ * TFTP packets can be 524 bytes + IP header + ethernet header.
+ * Lets be conservative, and go for 38 * 16.  (Must also be
+ * a multiple of 32 bytes).
+ */
+/*
+ * AS.HARNOIS : Better to set PKTSIZE to maximum size because
+ * traffic type is not always controlled
+ * maximum packet size =  1518
+ * maximum packet size and multiple of 32 bytes =  1536
+ */
+#define PKTSIZE			1518
+#define PKTSIZE_ALIGN		1536
+/*#define PKTSIZE		608*/
+
+/*
+ * Maximum receive ring size; that is, the number of packets
+ * we can buffer before overflow happens. Basically, this just
+ * needs to be enough to prevent a packet being discarded while
+ * we are processing the previous one.
+ */
+#define RINGSZ		4
+#define RINGSZ_LOG2	2
+
+/**********************************************************************/
+/*
+ *	Globals.
+ *
+ * Note:
+ *
+ * All variables of type IPaddr_t are stored in NETWORK byte order
+ * (big endian).
+ */
+
+/* net.c */
+/** BOOTP EXTENTIONS **/
+extern IPaddr_t NetOurGatewayIP;	/* Our gateway IP address */
+extern IPaddr_t NetOurSubnetMask;	/* Our subnet mask (0 = unknown) */
+extern IPaddr_t NetOurDNSIP;	/* Our Domain Name Server (0 = unknown) */
+#if defined(CONFIG_BOOTP_DNS2)
+extern IPaddr_t NetOurDNS2IP;	/* Our 2nd Domain Name Server (0 = unknown) */
+#endif
+extern char	NetOurNISDomain[32];	/* Our NIS domain */
+extern char	NetOurHostName[32];	/* Our hostname */
+extern char	NetOurRootPath[64];	/* Our root path */
+extern ushort	NetBootFileSize;	/* Our boot file size in blocks */
+/** END OF BOOTP EXTENTIONS **/
+extern ulong		NetBootFileXferSize;	/* size of bootfile in bytes */
+extern uchar		NetOurEther[6];		/* Our ethernet address */
+extern uchar		NetServerEther[6];	/* Boot server enet address */
+extern IPaddr_t		NetOurIP;	/* Our    IP addr (0 = unknown) */
+extern IPaddr_t		NetServerIP;	/* Server IP addr (0 = unknown) */
+extern uchar		*NetTxPacket;		/* THE transmit packet */
+extern uchar		*NetRxPackets[PKTBUFSRX]; /* Receive packets */
+extern uchar		*NetRxPacket;		/* Current receive packet */
+extern int		NetRxPacketLen;		/* Current rx packet length */
+extern unsigned		NetIPID;		/* IP ID (counting) */
+extern uchar		NetBcastAddr[6];	/* Ethernet boardcast address */
+extern uchar		NetEtherNullAddr[6];
+
+#define VLAN_NONE	4095			/* untagged */
+#define VLAN_IDMASK	0x0fff			/* mask of valid vlan id */
+extern ushort		NetOurVLAN;		/* Our VLAN */
+extern ushort		NetOurNativeVLAN;	/* Our Native VLAN */
+
+extern int		NetRestartWrap;		/* Tried all network devices */
+
+enum proto_t {
+	BOOTP, RARP, ARP, TFTPGET, DHCP, PING, DNS, NFS, CDP, NETCONS, SNTP,
+	TFTPSRV, TFTPPUT, LINKLOCAL
+};
+
+/* from net/net.c */
+extern char	BootFile[128];			/* Boot File name */
+
+#if defined(CONFIG_CMD_DNS)
+extern char *NetDNSResolve;		/* The host to resolve  */
+extern char *NetDNSenvvar;		/* the env var to put the ip into */
+#endif
+
+#if defined(CONFIG_CMD_PING)
+extern IPaddr_t	NetPingIP;			/* the ip address to ping */
+#endif
+
+#if defined(CONFIG_CMD_CDP)
+/* when CDP completes these hold the return values */
+extern ushort CDPNativeVLAN;		/* CDP returned native VLAN */
+extern ushort CDPApplianceVLAN;		/* CDP returned appliance VLAN */
+
+/*
+ * Check for a CDP packet by examining the received MAC address field
+ */
+static inline int is_cdp_packet(const uchar *et_addr)
+{
+	extern const uchar NetCDPAddr[6];
+
+	return memcmp(et_addr, NetCDPAddr, 6) == 0;
+}
+#endif
+
+#if defined(CONFIG_CMD_SNTP)
+extern IPaddr_t	NetNtpServerIP;			/* the ip address to NTP */
+extern int NetTimeOffset;			/* offset time from UTC */
+#endif
+
+#if defined(CONFIG_MCAST_TFTP)
+extern IPaddr_t Mcast_addr;
+#endif
+
+/* Initialize the network adapter */
+extern void net_init(void);
+extern int NetLoop(enum proto_t);
+
+/* Shutdown adapters and cleanup */
+extern void	NetStop(void);
+
+/* Load failed.	 Start again. */
+extern void	NetStartAgain(void);
+
+/* Get size of the ethernet header when we send */
+extern int	NetEthHdrSize(void);
+
+/* Set ethernet header; returns the size of the header */
+extern int NetSetEther(uchar *, uchar *, uint);
+extern int net_update_ether(struct ethernet_hdr *et, uchar *addr, uint prot);
+
+/* Set IP header */
+extern void net_set_ip_header(uchar *pkt, IPaddr_t dest, IPaddr_t source);
+extern void net_set_udp_header(uchar *pkt, IPaddr_t dest, int dport,
+				int sport, int len);
+
+/* Checksum */
+extern int	NetCksumOk(uchar *, int);	/* Return true if cksum OK */
+extern uint	NetCksum(uchar *, int);		/* Calculate the checksum */
+
+/* Callbacks */
+extern rxhand_f *net_get_udp_handler(void);	/* Get UDP RX packet handler */
+extern void net_set_udp_handler(rxhand_f *);	/* Set UDP RX packet handler */
+extern rxhand_f *net_get_arp_handler(void);	/* Get ARP RX packet handler */
+extern void net_set_arp_handler(rxhand_f *);	/* Set ARP RX packet handler */
+extern void net_set_icmp_handler(rxhand_icmp_f *f); /* Set ICMP RX handler */
+extern void	NetSetTimeout(ulong, thand_f *);/* Set timeout handler */
+
+/* Network loop state */
+enum net_loop_state {
+	NETLOOP_CONTINUE,
+	NETLOOP_RESTART,
+	NETLOOP_SUCCESS,
+	NETLOOP_FAIL
+};
+extern enum net_loop_state net_state;
+
+static inline void net_set_state(enum net_loop_state state)
+{
+	debug_cond(DEBUG_INT_STATE, "--- NetState set to %d\n", state);
+	net_state = state;
+}
+
+/* Transmit a packet */
+static inline void NetSendPacket(uchar *pkt, int len)
+{
+	(void) eth_send(pkt, len);
+}
+
+/*
+ * Transmit "NetTxPacket" as UDP packet, performing ARP request if needed
+ *  (ether will be populated)
+ *
+ * @param ether Raw packet buffer
+ * @param dest IP address to send the datagram to
+ * @param dport Destination UDP port
+ * @param sport Source UDP port
+ * @param payload_len Length of data after the UDP header
+ */
+extern int NetSendUDPPacket(uchar *ether, IPaddr_t dest, int dport,
+			int sport, int payload_len);
+
+/* Processes a received packet */
+extern void NetReceive(uchar *, int);
+
+#ifdef CONFIG_NETCONSOLE
+void NcStart(void);
+int nc_input_packet(uchar *pkt, IPaddr_t src_ip, unsigned dest_port,
+	unsigned src_port, unsigned len);
+#endif
+
+static inline __attribute__((always_inline)) int eth_is_on_demand_init(void)
+{
+#ifdef CONFIG_NETCONSOLE
+	extern enum proto_t net_loop_last_protocol;
+
+	return net_loop_last_protocol != NETCONS;
+#else
+	return 1;
+#endif
+}
+
+static inline void eth_set_last_protocol(int protocol)
+{
+#ifdef CONFIG_NETCONSOLE
+	extern enum proto_t net_loop_last_protocol;
+
+	net_loop_last_protocol = protocol;
+#endif
+}
+
+/*
+ * Check if autoload is enabled. If so, use either NFS or TFTP to download
+ * the boot file.
+ */
+void net_auto_load(void);
+
+/*
+ * The following functions are a bit ugly, but necessary to deal with
+ * alignment restrictions on ARM.
+ *
+ * We're using inline functions, which had the smallest memory
+ * footprint in our tests.
+ */
+/* return IP *in network byteorder* */
+static inline IPaddr_t NetReadIP(void *from)
+{
+	IPaddr_t ip;
+
+	memcpy((void *)&ip, (void *)from, sizeof(ip));
+	return ip;
+}
+
+/* return ulong *in network byteorder* */
+static inline ulong NetReadLong(ulong *from)
+{
+	ulong l;
+
+	memcpy((void *)&l, (void *)from, sizeof(l));
+	return l;
+}
+
+/* write IP *in network byteorder* */
+static inline void NetWriteIP(void *to, IPaddr_t ip)
+{
+	memcpy(to, (void *)&ip, sizeof(ip));
+}
+
+/* copy IP */
+static inline void NetCopyIP(void *to, void *from)
+{
+	memcpy((void *)to, from, sizeof(IPaddr_t));
+}
+
+/* copy ulong */
+static inline void NetCopyLong(ulong *to, ulong *from)
+{
+	memcpy((void *)to, (void *)from, sizeof(ulong));
+}
+
+/**
+ * is_zero_ether_addr - Determine if give Ethernet address is all zeros.
+ * @addr: Pointer to a six-byte array containing the Ethernet address
+ *
+ * Return true if the address is all zeroes.
+ */
+static inline int is_zero_ether_addr(const u8 *addr)
+{
+	return !(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5]);
+}
+
+/**
+ * is_multicast_ether_addr - Determine if the Ethernet address is a multicast.
+ * @addr: Pointer to a six-byte array containing the Ethernet address
+ *
+ * Return true if the address is a multicast address.
+ * By definition the broadcast address is also a multicast address.
+ */
+static inline int is_multicast_ether_addr(const u8 *addr)
+{
+	return 0x01 & addr[0];
+}
+
+/*
+ * is_broadcast_ether_addr - Determine if the Ethernet address is broadcast
+ * @addr: Pointer to a six-byte array containing the Ethernet address
+ *
+ * Return true if the address is the broadcast address.
+ */
+static inline int is_broadcast_ether_addr(const u8 *addr)
+{
+	return (addr[0] & addr[1] & addr[2] & addr[3] & addr[4] & addr[5]) ==
+		0xff;
+}
+
+/*
+ * is_valid_ether_addr - Determine if the given Ethernet address is valid
+ * @addr: Pointer to a six-byte array containing the Ethernet address
+ *
+ * Check that the Ethernet address (MAC) is not 00:00:00:00:00:00, is not
+ * a multicast address, and is not FF:FF:FF:FF:FF:FF.
+ *
+ * Return true if the address is valid.
+ */
+static inline int is_valid_ether_addr(const u8 *addr)
+{
+	/* FF:FF:FF:FF:FF:FF is a multicast address so we don't need to
+	 * explicitly check for it here. */
+	return !is_multicast_ether_addr(addr) && !is_zero_ether_addr(addr);
+}
+
+/**
+ * eth_random_addr - Generate software assigned random Ethernet address
+ * @addr: Pointer to a six-byte array containing the Ethernet address
+ *
+ * Generate a random Ethernet address (MAC) that is not multicast
+ * and has the local assigned bit set.
+ */
+static inline void eth_random_addr(uchar *addr)
+{
+	int i;
+	unsigned int seed = get_timer(0);
+
+	for (i = 0; i < 6; i++)
+		addr[i] = rand_r(&seed);
+
+	addr[0] &= 0xfe;	/* clear multicast bit */
+	addr[0] |= 0x02;	/* set local assignment bit (IEEE802) */
+}
+
+/* Convert an IP address to a string */
+extern void ip_to_string(IPaddr_t x, char *s);
+
+/* Convert a string to ip address */
+extern IPaddr_t string_to_ip(const char *s);
+
+/* Convert a VLAN id to a string */
+extern void VLAN_to_string(ushort x, char *s);
+
+/* Convert a string to a vlan id */
+extern ushort string_to_VLAN(const char *s);
+
+/* read a VLAN id from an environment variable */
+extern ushort getenv_VLAN(char *);
+
+/* copy a filename (allow for "..." notation, limit length) */
+extern void copy_filename(char *dst, const char *src, int size);
+
+/* get a random source port */
+extern unsigned int random_port(void);
+
+/* Update U-Boot over TFTP */
+extern int update_tftp(ulong addr);
+
+/**********************************************************************/
+
+#endif /* __NET_H__ */
diff --git a/qemu/roms/u-boot/include/netdev.h b/qemu/roms/u-boot/include/netdev.h
new file mode 100644
index 000000000..e211f1841
--- /dev/null
+++ b/qemu/roms/u-boot/include/netdev.h
@@ -0,0 +1,217 @@
+/*
+ * (C) Copyright 2008
+ * Benjamin Warren, biggerbadderben@gmail.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * netdev.h - definitions an prototypes for network devices
+ */
+
+#ifndef _NETDEV_H_
+#define _NETDEV_H_
+
+/*
+ * Board and CPU-specific initialization functions
+ * board_eth_init() has highest priority.  cpu_eth_init() only
+ * gets called if board_eth_init() isn't instantiated or fails.
+ * Return values:
+ *      0: success
+ *     -1: failure
+ */
+
+int board_eth_init(bd_t *bis);
+int cpu_eth_init(bd_t *bis);
+
+/* Driver initialization prototypes */
+int altera_tse_initialize(u8 dev_num, int mac_base,
+			  int sgdma_rx_base, int sgdma_tx_base,
+			  u32 sgdma_desc_base, u32 sgdma_desc_size);
+int at91emac_register(bd_t *bis, unsigned long iobase);
+int au1x00_enet_initialize(bd_t*);
+int ax88180_initialize(bd_t *bis);
+int bfin_EMAC_initialize(bd_t *bis);
+int calxedaxgmac_initialize(u32 id, ulong base_addr);
+int cs8900_initialize(u8 dev_num, int base_addr);
+int davinci_emac_initialize(void);
+int dc21x4x_initialize(bd_t *bis);
+int designware_initialize(ulong base_addr, u32 interface);
+int dm9000_initialize(bd_t *bis);
+int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr);
+int e1000_initialize(bd_t *bis);
+int eepro100_initialize(bd_t *bis);
+int enc28j60_initialize(unsigned int bus, unsigned int cs,
+	unsigned int max_hz, unsigned int mode);
+int ep93xx_eth_initialize(u8 dev_num, int base_addr);
+int eth_3com_initialize (bd_t * bis);
+int ethoc_initialize(u8 dev_num, int base_addr);
+int fec_initialize (bd_t *bis);
+int fecmxc_initialize(bd_t *bis);
+int fecmxc_initialize_multi(bd_t *bis, int dev_id, int phy_id, uint32_t addr);
+int ftgmac100_initialize(bd_t *bits);
+int ftmac100_initialize(bd_t *bits);
+int ftmac110_initialize(bd_t *bits);
+int greth_initialize(bd_t *bis);
+void gt6426x_eth_initialize(bd_t *bis);
+int ks8695_eth_initialize(void);
+int ks8851_mll_initialize(u8 dev_num, int base_addr);
+int lan91c96_initialize(u8 dev_num, int base_addr);
+int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
+int mcdmafec_initialize(bd_t *bis);
+int mcffec_initialize(bd_t *bis);
+int mpc512x_fec_initialize(bd_t *bis);
+int mpc5xxx_fec_initialize(bd_t *bis);
+int mpc82xx_scc_enet_initialize(bd_t *bis);
+int mvgbe_initialize(bd_t *bis);
+int natsemi_initialize(bd_t *bis);
+int ne2k_register(void);
+int npe_initialize(bd_t *bis);
+int ns8382x_initialize(bd_t *bis);
+int pcnet_initialize(bd_t *bis);
+int plb2800_eth_initialize(bd_t *bis);
+int ppc_4xx_eth_initialize (bd_t *bis);
+int rtl8139_initialize(bd_t *bis);
+int rtl8169_initialize(bd_t *bis);
+int scc_initialize(bd_t *bis);
+int sh_eth_initialize(bd_t *bis);
+int skge_initialize(bd_t *bis);
+int smc91111_initialize(u8 dev_num, int base_addr);
+int smc911x_initialize(u8 dev_num, int base_addr);
+int sunxi_wemac_initialize(bd_t *bis);
+int tsi108_eth_initialize(bd_t *bis);
+int uec_standard_init(bd_t *bis);
+int uli526x_initialize(bd_t *bis);
+int armada100_fec_register(unsigned long base_addr);
+int xilinx_axiemac_initialize(bd_t *bis, unsigned long base_addr,
+							unsigned long dma_addr);
+int xilinx_emaclite_of_init(const void *blob);
+int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr,
+							int txpp, int rxpp);
+int xilinx_ll_temac_eth_init(bd_t *bis, unsigned long base_addr, int flags,
+						unsigned long ctrl_addr);
+int zynq_gem_of_init(const void *blob);
+int zynq_gem_initialize(bd_t *bis, int base_addr, int phy_addr, u32 emio);
+/*
+ * As long as the Xilinx xps_ll_temac ethernet driver has not its own interface
+ * exported by a public hader file, we need a global definition at this point.
+ */
+#if defined(CONFIG_XILINX_LL_TEMAC)
+#define XILINX_LL_TEMAC_M_FIFO		0	/* use FIFO Ctrl */
+#define XILINX_LL_TEMAC_M_SDMA_PLB	(1 << 0)/* use SDMA Ctrl via PLB */
+#define XILINX_LL_TEMAC_M_SDMA_DCR	(1 << 1)/* use SDMA Ctrl via DCR */
+#endif
+
+/* Boards with PCI network controllers can call this from their board_eth_init()
+ * function to initialize whatever's on board.
+ * Return value is total # of devices found */
+
+static inline int pci_eth_init(bd_t *bis)
+{
+	int num = 0;
+
+#ifdef CONFIG_PCI
+
+#ifdef CONFIG_EEPRO100
+	num += eepro100_initialize(bis);
+#endif
+#ifdef CONFIG_TULIP
+	num += dc21x4x_initialize(bis);
+#endif
+#ifdef CONFIG_E1000
+	num += e1000_initialize(bis);
+#endif
+#ifdef CONFIG_PCNET
+	num += pcnet_initialize(bis);
+#endif
+#ifdef CONFIG_NATSEMI
+	num += natsemi_initialize(bis);
+#endif
+#ifdef CONFIG_NS8382X
+	num += ns8382x_initialize(bis);
+#endif
+#if defined(CONFIG_RTL8139)
+	num += rtl8139_initialize(bis);
+#endif
+#if defined(CONFIG_RTL8169)
+	num += rtl8169_initialize(bis);
+#endif
+#if defined(CONFIG_ULI526X)
+	num += uli526x_initialize(bis);
+#endif
+
+#endif  /* CONFIG_PCI */
+	return num;
+}
+
+/*
+ * Boards with mv88e61xx switch can use this by defining
+ * CONFIG_MV88E61XX_SWITCH in respective board configheader file
+ * the stuct and enums here are used to specify switch configuration params
+ */
+#if defined(CONFIG_MV88E61XX_SWITCH)
+
+/* constants for any 88E61xx switch */
+#define MV88E61XX_MAX_PORTS_NUM	6
+
+enum mv88e61xx_cfg_mdip {
+	MV88E61XX_MDIP_NOCHANGE,
+	MV88E61XX_MDIP_REVERSE
+};
+
+enum mv88e61xx_cfg_ledinit {
+	MV88E61XX_LED_INIT_DIS,
+	MV88E61XX_LED_INIT_EN
+};
+
+enum mv88e61xx_cfg_rgmiid {
+	MV88E61XX_RGMII_DELAY_DIS,
+	MV88E61XX_RGMII_DELAY_EN
+};
+
+enum mv88e61xx_cfg_prtstt {
+	MV88E61XX_PORTSTT_DISABLED,
+	MV88E61XX_PORTSTT_BLOCKING,
+	MV88E61XX_PORTSTT_LEARNING,
+	MV88E61XX_PORTSTT_FORWARDING
+};
+
+struct mv88e61xx_config {
+	char *name;
+	u8 vlancfg[MV88E61XX_MAX_PORTS_NUM];
+	enum mv88e61xx_cfg_rgmiid rgmii_delay;
+	enum mv88e61xx_cfg_prtstt portstate;
+	enum mv88e61xx_cfg_ledinit led_init;
+	enum mv88e61xx_cfg_mdip mdip;
+	u32 ports_enabled;
+	u8 cpuport;
+};
+
+/*
+ * Common mappings for Internal VLANs
+ * These mappings consider that all ports are useable; the driver
+ * will mask inexistent/unused ports.
+ */
+
+/* Switch mode : routes any port to any port */
+#define MV88E61XX_VLANCFG_SWITCH { 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F }
+
+/* Router mode: routes only CPU port 5 to/from non-CPU ports 0-4 */
+#define MV88E61XX_VLANCFG_ROUTER { 0x20, 0x20, 0x20, 0x20, 0x20, 0x1F }
+
+int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig);
+#endif /* CONFIG_MV88E61XX_SWITCH */
+
+struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id);
+#ifdef CONFIG_PHYLIB
+struct phy_device;
+int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
+		struct mii_dev *bus, struct phy_device *phydev);
+#else
+/*
+ * Allow FEC to fine-tune MII configuration on boards which require this.
+ */
+int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int));
+#endif
+
+#endif /* _NETDEV_H_ */
diff --git a/qemu/roms/u-boot/include/nios2-epcs.h b/qemu/roms/u-boot/include/nios2-epcs.h
new file mode 100644
index 000000000..8c8f2385e
--- /dev/null
+++ b/qemu/roms/u-boot/include/nios2-epcs.h
@@ -0,0 +1,60 @@
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*************************************************************************
+ * Altera Nios-II EPCS Controller Core interfaces
+ ************************************************************************/
+
+#ifndef __NIOS2_EPCS_H__
+#define __NIOS2_EPCS_H__
+
+typedef struct epcs_devinfo_t {
+	const char	*name;		/* Device name */
+	unsigned char	id;		/* Device silicon id */
+	unsigned char	size;		/* Total size log2(bytes)*/
+	unsigned char	num_sects;	/* Number of sectors */
+	unsigned char	sz_sect;	/* Sector size log2(bytes) */
+	unsigned char	sz_page;	/* Page size log2(bytes) */
+	unsigned char   prot_mask;	/* Protection mask */
+}epcs_devinfo_t;
+
+/* Resets the epcs controller -- to prevent (potential) soft-reset
+ * problems when booting from the epcs controller
+ */
+extern int epcs_reset (void);
+
+/* Returns the devinfo struct if EPCS device is found;
+ * NULL otherwise.
+ */
+extern epcs_devinfo_t *epcs_dev_find (void);
+
+/* Returns the number of bytes used by config data.
+ * Negative on error.
+ */
+extern int epcs_cfgsz (void);
+
+/* Erase sectors 'start' to 'end' - return zero on success
+ */
+extern int epcs_erase (unsigned start, unsigned end);
+
+/* Read 'cnt' bytes from device offset 'off' into buf at 'addr'
+ * Zero return on success
+ */
+extern int epcs_read (ulong addr, ulong off, ulong cnt);
+
+/* Write 'cnt' bytes to device offset 'off' from buf at 'addr'.
+ * Zero return on success
+ */
+extern int epcs_write (ulong addr, ulong off, ulong cnt);
+
+/* Verify 'cnt' bytes at device offset 'off' comparing with buf
+ * at 'addr'. On failure, write first invalid offset to *err.
+ * Zero return on success
+ */
+extern int epcs_verify (ulong addr, ulong off, ulong cnt, ulong *err);
+
+#endif /* __NIOS2_EPCS_H__ */
diff --git a/qemu/roms/u-boot/include/nios2-io.h b/qemu/roms/u-boot/include/nios2-io.h
new file mode 100644
index 000000000..6f1ae5031
--- /dev/null
+++ b/qemu/roms/u-boot/include/nios2-io.h
@@ -0,0 +1,153 @@
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*************************************************************************
+ * Altera Nios2 Standard Peripherals
+ ************************************************************************/
+
+#ifndef __NIOS2IO_H__
+#define __NIOS2IO_H__
+
+/*------------------------------------------------------------------------
+ * UART (http://www.altera.com/literature/ds/ds_nios_uart.pdf)
+ *----------------------------------------------------------------------*/
+typedef volatile struct nios_uart_t {
+	unsigned	rxdata;		/* Rx data reg */
+	unsigned	txdata;		/* Tx data reg */
+	unsigned	status;		/* Status reg */
+	unsigned	control;	/* Control reg */
+	unsigned	divisor;	/* Baud rate divisor reg */
+	unsigned	endofpacket;	/* End-of-packet reg */
+}nios_uart_t;
+
+/* status register */
+#define NIOS_UART_PE		(1 << 0)	/* parity error */
+#define NIOS_UART_FE		(1 << 1)	/* frame error */
+#define NIOS_UART_BRK		(1 << 2)	/* break detect */
+#define NIOS_UART_ROE		(1 << 3)	/* rx overrun */
+#define NIOS_UART_TOE		(1 << 4)	/* tx overrun */
+#define NIOS_UART_TMT		(1 << 5)	/* tx empty */
+#define NIOS_UART_TRDY		(1 << 6)	/* tx ready */
+#define NIOS_UART_RRDY		(1 << 7)	/* rx ready */
+#define NIOS_UART_E		(1 << 8)	/* exception */
+#define NIOS_UART_DCTS		(1 << 10)	/* cts change */
+#define NIOS_UART_CTS		(1 << 11)	/* cts */
+#define NIOS_UART_EOP		(1 << 12)	/* eop detected */
+
+/* control register */
+#define NIOS_UART_IPE		(1 << 0)	/* parity error int ena*/
+#define NIOS_UART_IFE		(1 << 1)	/* frame error int ena */
+#define NIOS_UART_IBRK		(1 << 2)	/* break detect int ena */
+#define NIOS_UART_IROE		(1 << 3)	/* rx overrun int ena */
+#define NIOS_UART_ITOE		(1 << 4)	/* tx overrun int ena */
+#define NIOS_UART_ITMT		(1 << 5)	/* tx empty int ena */
+#define NIOS_UART_ITRDY		(1 << 6)	/* tx ready int ena */
+#define NIOS_UART_IRRDY		(1 << 7)	/* rx ready int ena */
+#define NIOS_UART_IE		(1 << 8)	/* exception int ena */
+#define NIOS_UART_TBRK		(1 << 9)	/* transmit break */
+#define NIOS_UART_IDCTS		(1 << 10)	/* cts change int ena */
+#define NIOS_UART_RTS		(1 << 11)	/* rts */
+#define NIOS_UART_IEOP		(1 << 12)	/* eop detected int ena */
+
+
+/*------------------------------------------------------------------------
+ * TIMER (http://www.altera.com/literature/ds/ds_nios_timer.pdf)
+ *----------------------------------------------------------------------*/
+typedef volatile struct nios_timer_t {
+	unsigned	status;			/* Timer status reg */
+	unsigned	control;		/* Timer control reg */
+	unsigned	periodl;		/* Timeout period low */
+	unsigned	periodh;		/* Timeout period high */
+	unsigned	snapl;			/* Snapshot low */
+	unsigned	snaph;			/* Snapshot high */
+}nios_timer_t;
+
+/* status register */
+#define NIOS_TIMER_TO		(1 << 0)	/* Timeout */
+#define NIOS_TIMER_RUN		(1 << 1)	/* Timer running */
+
+/* control register */
+#define NIOS_TIMER_ITO		(1 << 0)	/* Timeout int ena */
+#define NIOS_TIMER_CONT		(1 << 1)	/* Continuous mode */
+#define NIOS_TIMER_START	(1 << 2)	/* Start timer */
+#define NIOS_TIMER_STOP		(1 << 3)	/* Stop timer */
+
+
+/*------------------------------------------------------------------------
+ * PIO (http://www.altera.com/literature/ds/ds_nios_pio.pdf)
+ *----------------------------------------------------------------------*/
+typedef volatile struct nios_pio_t {
+	unsigned int	data;		/* Data value at each PIO in/out */
+	unsigned int	direction;	/* Data direct. for each PIO bit */
+	unsigned int	interruptmask;	/* Per-bit IRQ enable/disable */
+	unsigned int	edgecapture;	/* Per-bit sync. edge detect & hold */
+}nios_pio_t;
+
+/* direction register */
+#define NIOS_PIO_OUT		(1)		/* PIO bit is output */
+#define NIOS_PIO_IN		(0)		/* PIO bit is input */
+
+
+/*------------------------------------------------------------------------
+ * SPI (http://www.altera.com/literature/ds/ds_nios_spi.pdf)
+ *----------------------------------------------------------------------*/
+typedef volatile struct nios_spi_t {
+	unsigned	rxdata;		/* Rx data reg */
+	unsigned	txdata;		/* Tx data reg */
+	unsigned	status;		/* Status reg */
+	unsigned	control;	/* Control reg */
+	unsigned	reserved;	/* (master only) */
+	unsigned	slaveselect;	/* SPI slave select mask (master only) */
+}nios_spi_t;
+
+/* status register */
+#define NIOS_SPI_ROE		(1 << 3)	/* rx overrun */
+#define NIOS_SPI_TOE		(1 << 4)	/* tx overrun */
+#define NIOS_SPI_TMT		(1 << 5)	/* tx empty */
+#define NIOS_SPI_TRDY		(1 << 6)	/* tx ready */
+#define NIOS_SPI_RRDY		(1 << 7)	/* rx ready */
+#define NIOS_SPI_E		(1 << 8)	/* exception */
+
+/* control register */
+#define NIOS_SPI_IROE		(1 << 3)	/* rx overrun int ena */
+#define NIOS_SPI_ITOE		(1 << 4)	/* tx overrun int ena */
+#define NIOS_SPI_ITRDY		(1 << 6)	/* tx ready int ena */
+#define NIOS_SPI_IRRDY		(1 << 7)	/* rx ready int ena */
+#define NIOS_SPI_IE		(1 << 8)	/* exception int ena */
+#define NIOS_SPI_SSO		(1 << 10)	/* override SS_n output */
+
+/*------------------------------------------------------------------------
+ * JTAG UART
+ *----------------------------------------------------------------------*/
+typedef volatile struct nios_jtag_t {
+	unsigned	data;			/* Data register */
+	unsigned	control;		/* Control register */
+}nios_jtag_t;
+
+/* data register */
+#define NIOS_JTAG_RVALID	(1<<15)		/* Read valid */
+#define NIOS_JTAG_DATA(d)	((d)&0x0ff)	/* Read data */
+#define NIOS_JTAG_RAVAIL(d)	((d)>>16)	/* Read space avail */
+
+/* control register */
+#define NIOS_JTAG_RE		(1 << 0)	/* read intr enable */
+#define NIOS_JTAG_WE		(1 << 1)	/* write intr enable */
+#define NIOS_JTAG_RI		(1 << 8)	/* read intr pending */
+#define NIOS_JTAG_WI		(1 << 9)	/* write intr pending*/
+#define NIOS_JTAG_AC		(1 << 10)	/* activity indicator */
+#define NIOS_JTAG_RRDY		(1 << 12)	/* read available */
+#define NIOS_JTAG_WSPACE(d)	((d)>>16)	/* Write space avail */
+
+/*------------------------------------------------------------------------
+ * SYSTEM ID
+ *----------------------------------------------------------------------*/
+typedef volatile struct nios_sysid_t {
+	unsigned	id;			/* The system build id*/
+	unsigned	timestamp;		/* Timestamp */
+}nios_sysid_t;
+
+#endif /* __NIOS2IO_H__ */
diff --git a/qemu/roms/u-boot/include/nios2-yanu.h b/qemu/roms/u-boot/include/nios2-yanu.h
new file mode 100644
index 000000000..6c16f5b45
--- /dev/null
+++ b/qemu/roms/u-boot/include/nios2-yanu.h
@@ -0,0 +1,99 @@
+/*
+ * (C) Copyright 2006, Imagos S.a.s <www.imagos.it>
+ * Renato Andreola <renato.andreola@imagos.it>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*************************************************************************
+ * Altera NiosII YANU serial interface by Imagos
+ * please see  http://www.opencores.org/project,yanu for
+ * information/downloads
+ ************************************************************************/
+
+#ifndef __NIOS2_YANU_H__
+#define __NIOS2_YANU_H__
+
+#define YANU_MAX_PRESCALER_N   ((1 << 4) - 1)	/* 15 */
+#define YANU_MAX_PRESCALER_M   ((1 << 11) -1)	/* 2047 */
+#define YANU_FIFO_SIZE         (16)
+#define YANU_RXFIFO_SIZE       (YANU_FIFO_SIZE)
+#define YANU_TXFIFO_SIZE       (YANU_FIFO_SIZE)
+
+#define YANU_RXFIFO_DLY        (10*11)
+#define YANU_TXFIFO_THR        (10)
+#define YANU_DATA_CHAR_MASK    (0xFF)
+
+/* data register */
+#define YANU_DATA_OFFSET       (0)	/* data register offset */
+
+#define YANU_CONTROL_OFFSET    (4)	/* control register offset */
+/* interrupt enable */
+#define YANU_CONTROL_IE_RRDY   (1<<0)	/* ie on received character ready */
+#define YANU_CONTROL_IE_OE     (1<<1)	/* ie on rx overrun    */
+#define YANU_CONTROL_IE_BRK    (1<<2)	/* ie on break detect  */
+#define YANU_CONTROL_IE_FE     (1<<3)	/* ie on framing error */
+#define YANU_CONTROL_IE_PE     (1<<4)	/* ie on parity error  */
+#define YANU_CONTROL_IE_TRDY   (1<<5)	/* ie interrupt on tranmitter ready */
+/* control bits */
+#define YANU_CONTROL_BITS_POS  (6)	/* bits number pos */
+#define YANU_CONTROL_BITS      (1<<YANU_CONTROL_BITS_POS)	/* number of rx/tx bits per word. 3 bit unsigned integer */
+#define YANU_CONTROL_BITS_N    (3)	/* ... its bit filed length */
+#define YANU_CONTROL_PARENA    (1<<9)	/*  enable parity bit transmission/reception */
+#define YANU_CONTROL_PAREVEN   (1<<10)	/* parity even */
+#define YANU_CONTROL_STOPS     (1<<11)	/* number of stop bits */
+#define YANU_CONTROL_HHENA     (1<<12)	/* Harware Handshake enable... */
+#define YANU_CONTROL_FORCEBRK  (1<<13)	/* if set than txd = active (0) */
+/* tuning part */
+#define YANU_CONTROL_RDYDLY    (1<<14)	/* delay from "first" before setting rrdy (in bit) */
+#define YANU_CONTROL_RDYDLY_N  (8)	/* ... its bit filed length */
+#define YANU_CONTROL_TXTHR     (1<<22)	/* tx interrupt threshold: the trdy set if txfifo_chars<= txthr (chars) */
+#define YANU_CONTROL_TXTHR_N   (4)	/* ... its bit field length */
+
+#define YANU_BAUD_OFFSET  (8)	/* baud register offset */
+#define YANU_BAUDM        (1<<0)	/* baud mantissa lsb */
+#define YANU_BAUDM_N      (12)	/* ...its bit filed length */
+#define YANU_BAUDE        (1<<12)	/* baud exponent lsb */
+#define YANU_BAUDE_N      (4)	/* ...its bit field length */
+
+#define YANU_ACTION_OFFSET   (12)	/* action register... write only */
+#define YANU_ACTION_RRRDY    (1<<0)	/* reset rrdy */
+#define YANU_ACTION_ROE      (1<<1)	/* reset oe */
+#define YANU_ACTION_RBRK     (1<<2)	/* reset brk */
+#define YANU_ACTION_RFE      (1<<3)	/* reset fe  */
+#define YANU_ACTION_RPE      (1<<4)	/* reset pe  */
+#define YANU_ACTION_SRRDY    (1<<5)	/* set rrdy  */
+#define YANU_ACTION_SOE      (1<<6)	/* set oe    */
+#define YANU_ACTION_SBRK     (1<<7)	/* set brk   */
+#define YANU_ACTION_SFE      (1<<8)	/* set fe    */
+#define YANU_ACTION_SPE      (1<<9)	/* set pe    */
+#define YANU_ACTION_RFIFO_PULL  (1<<10)	/* pull a char from rx fifo we MUST do it before taking a char */
+#define YANU_ACTION_RFIFO_CLEAR (1<<11)	/* clear rx fifo */
+#define YANU_ACTION_TFIFO_CLEAR (1<<12)	/* clear tx fifo */
+#define YANU_ACTION_RTRDY       (1<<13)	/* clear trdy    */
+#define YANU_ACTION_STRDY       (1<<14)	/* set trdy      */
+
+#define YANU_STATUS_OFFSET   (16)
+#define YANU_STATUS_RRDY     (1<<0)	/* rxrdy flag */
+#define YANU_STATUS_TRDY     (1<<1)	/* txrdy flag */
+#define YANU_STATUS_OE       (1<<2)	/* rx overrun error */
+#define YANU_STATUS_BRK      (1<<3)	/* rx break detect flag */
+#define YANU_STATUS_FE       (1<<4)	/* rx framing error flag */
+#define YANU_STATUS_PE       (1<<5)	/* rx parity erro flag */
+#define YANU_RFIFO_CHARS_POS (6)
+#define YANU_RFIFO_CHARS     (1<<RFIFO_CHAR_POS)	/* number of chars into rx fifo */
+#define YANU_RFIFO_CHARS_N   (5)	/* ...its bit field length: 32 chars */
+#define YANU_TFIFO_CHARS_POS (11)
+#define YANU_TFIFO_CHARS     (1<<TFIFO_CHAR_POS)	/* number of chars into tx fifo */
+#define YANU_TFIFO_CHARS_N   (5)	/* ...its bit field length: 32 chars */
+
+typedef volatile struct yanu_uart_t {
+	volatile unsigned data;
+	volatile unsigned control;	/* control register (RW) 32-bit   */
+	volatile unsigned baud;	/* baud/prescaler register (RW) 32-bit */
+	volatile unsigned action;	/* action register (W) 32-bit */
+	volatile unsigned status;	/* status register (R) 32-bit */
+	volatile unsigned magic;	/* magic register (R) 32-bit */
+} yanu_uart_t;
+
+#endif
diff --git a/qemu/roms/u-boot/include/nios2.h b/qemu/roms/u-boot/include/nios2.h
new file mode 100644
index 000000000..0539ec345
--- /dev/null
+++ b/qemu/roms/u-boot/include/nios2.h
@@ -0,0 +1,40 @@
+/*
+ * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __NIOS2_H__
+#define __NIOS2_H__
+
+/*------------------------------------------------------------------------
+ * Control registers -- use with wrctl() & rdctl()
+ *----------------------------------------------------------------------*/
+#define CTL_STATUS	0		/* Processor status reg		*/
+#define CTL_ESTATUS	1		/* Exception status reg		*/
+#define CTL_BSTATUS	2		/* Break status reg		*/
+#define CTL_IENABLE	3		/* Interrut enable reg		*/
+#define CTL_IPENDING	4		/* Interrut pending reg		*/
+
+/*------------------------------------------------------------------------
+ * Access to control regs
+ *----------------------------------------------------------------------*/
+
+#define rdctl(reg) __builtin_rdctl(reg)
+#define wrctl(reg, val) __builtin_wrctl(reg, val)
+
+/*------------------------------------------------------------------------
+ * Control reg bit masks
+ *----------------------------------------------------------------------*/
+#define STATUS_IE	(1<<0)		/* Interrupt enable		*/
+#define STATUS_U	(1<<1)		/* User-mode			*/
+
+/*------------------------------------------------------------------------
+ * Bit-31 Cache bypass -- only valid for data access. When data cache
+ * is not implemented, bit 31 is ignored for compatibility.
+ *----------------------------------------------------------------------*/
+#define CACHE_BYPASS(a) ((a) | 0x80000000)
+#define CACHE_NO_BYPASS(a) ((a) & ~0x80000000)
+
+#endif /* __NIOS2_H__ */
diff --git a/qemu/roms/u-boot/include/nomadik.h b/qemu/roms/u-boot/include/nomadik.h
new file mode 100644
index 000000000..ea65b2d82
--- /dev/null
+++ b/qemu/roms/u-boot/include/nomadik.h
@@ -0,0 +1,40 @@
+/* Collection of constants used to access Nomadik registers */
+
+#ifndef __NOMADIK_H__
+#define __NOMADIK_H__
+
+/* Base addresses of our peripherals */
+#define NOMADIK_CLCDC_BASE	0x10120000	/* CLCD Controller */
+#define NOMADIK_SRC_BASE	0x101E0000	/* System and Reset Cnt */
+#define NOMADIK_PMU_BASE	0x101E9000	/* Power Management Unit */
+#define NOMADIK_MPMC_BASE	0x10110000	/* SDRAM Controller */
+#define NOMADIK_FSMC_BASE	0x10100000	/* FSMC Controller */
+#define NOMADIK_1NAND_BASE	0x30000000
+#define NOMADIK_GPIO0_BASE	0x101E4000
+#define NOMADIK_GPIO1_BASE	0x101E5000
+#define NOMADIK_GPIO2_BASE	0x101E6000
+#define NOMADIK_GPIO3_BASE	0x101E7000
+#define NOMADIK_CPLD_BASE	0x36000000
+#define NOMADIK_UART0_BASE	0x101FD000
+#define NOMADIK_UART1_BASE	0x101FB000
+#define NOMADIK_UART2_BASE	0x101F2000
+
+#define NOMADIK_I2C1_BASE	0x101F7000	/* I2C1 interface */
+#define NOMADIK_I2C0_BASE	0x101F8000	/* I2C0 interface */
+
+#define NOMADIK_RTC_BASE	0x101E8000
+#define NOMADIK_ETH0_BASE	0x36800300
+#define NOMADIK_CPLD_UART_BASE	0x36480000
+
+/* Chip select registers ("Flexible Static Memory Controller") */
+
+#define REG_FSMC_BCR0	(NOMADIK_FSMC_BASE + 0x00)
+#define REG_FSMC_BTR0	(NOMADIK_FSMC_BASE + 0x04)
+#define REG_FSMC_BCR1	(NOMADIK_FSMC_BASE + 0x08)
+#define REG_FSMC_BTR1	(NOMADIK_FSMC_BASE + 0x0c)
+#define REG_FSMC_PCR0	(NOMADIK_FSMC_BASE + 0x40)
+#define REG_FSMC_PMEM0	(NOMADIK_FSMC_BASE + 0x48)
+#define REG_FSMC_PATT0	(NOMADIK_FSMC_BASE + 0x4c)
+#define REG_FSMC_ECCR0	(NOMADIK_FSMC_BASE + 0x54)
+
+#endif /* __NOMADIK_H__ */
diff --git a/qemu/roms/u-boot/include/ns16550.h b/qemu/roms/u-boot/include/ns16550.h
new file mode 100644
index 000000000..17f829f6f
--- /dev/null
+++ b/qemu/roms/u-boot/include/ns16550.h
@@ -0,0 +1,179 @@
+/*
+ * NS16550 Serial Port
+ * originally from linux source (arch/powerpc/boot/ns16550.h)
+ *
+ * Cleanup and unification
+ * (C) 2009 by Detlev Zundel, DENX Software Engineering GmbH
+ *
+ * modified slightly to
+ * have addresses as offsets from CONFIG_SYS_ISA_BASE
+ * added a few more definitions
+ * added prototypes for ns16550.c
+ * reduced no of com ports to 2
+ * modifications (c) Rob Taylor, Flying Pig Systems. 2000.
+ *
+ * added support for port on 64-bit bus
+ * by Richard Danter (richard.danter@windriver.com), (C) 2005 Wind River Systems
+ */
+
+/*
+ * Note that the following macro magic uses the fact that the compiler
+ * will not allocate storage for arrays of size 0
+ */
+
+#include <linux/types.h>
+
+#if !defined(CONFIG_SYS_NS16550_REG_SIZE) || (CONFIG_SYS_NS16550_REG_SIZE == 0)
+#error "Please define NS16550 registers size."
+#elif defined(CONFIG_SYS_NS16550_MEM32)
+#define UART_REG(x) u32 x
+#elif (CONFIG_SYS_NS16550_REG_SIZE > 0)
+#define UART_REG(x)						   \
+	unsigned char prepad_##x[CONFIG_SYS_NS16550_REG_SIZE - 1]; \
+	unsigned char x;
+#elif (CONFIG_SYS_NS16550_REG_SIZE < 0)
+#define UART_REG(x)							\
+	unsigned char x;						\
+	unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1];
+#endif
+
+struct NS16550 {
+	UART_REG(rbr);		/* 0 */
+	UART_REG(ier);		/* 1 */
+	UART_REG(fcr);		/* 2 */
+	UART_REG(lcr);		/* 3 */
+	UART_REG(mcr);		/* 4 */
+	UART_REG(lsr);		/* 5 */
+	UART_REG(msr);		/* 6 */
+	UART_REG(spr);		/* 7 */
+#ifdef CONFIG_SOC_DA8XX
+	UART_REG(reg8);		/* 8 */
+	UART_REG(reg9);		/* 9 */
+	UART_REG(revid1);	/* A */
+	UART_REG(revid2);	/* B */
+	UART_REG(pwr_mgmt);	/* C */
+	UART_REG(mdr1);		/* D */
+#else
+	UART_REG(mdr1);		/* 8 */
+	UART_REG(reg9);		/* 9 */
+	UART_REG(regA);		/* A */
+	UART_REG(regB);		/* B */
+	UART_REG(regC);		/* C */
+	UART_REG(regD);		/* D */
+	UART_REG(regE);		/* E */
+	UART_REG(uasr);		/* F */
+	UART_REG(scr);		/* 10*/
+	UART_REG(ssr);		/* 11*/
+	UART_REG(reg12);	/* 12*/
+	UART_REG(osc_12m_sel);	/* 13*/
+#endif
+};
+
+#define thr rbr
+#define iir fcr
+#define dll rbr
+#define dlm ier
+
+typedef struct NS16550 *NS16550_t;
+
+/*
+ * These are the definitions for the FIFO Control Register
+ */
+#define UART_FCR_FIFO_EN	0x01 /* Fifo enable */
+#define UART_FCR_CLEAR_RCVR	0x02 /* Clear the RCVR FIFO */
+#define UART_FCR_CLEAR_XMIT	0x04 /* Clear the XMIT FIFO */
+#define UART_FCR_DMA_SELECT	0x08 /* For DMA applications */
+#define UART_FCR_TRIGGER_MASK	0xC0 /* Mask for the FIFO trigger range */
+#define UART_FCR_TRIGGER_1	0x00 /* Mask for trigger set at 1 */
+#define UART_FCR_TRIGGER_4	0x40 /* Mask for trigger set at 4 */
+#define UART_FCR_TRIGGER_8	0x80 /* Mask for trigger set at 8 */
+#define UART_FCR_TRIGGER_14	0xC0 /* Mask for trigger set at 14 */
+
+#define UART_FCR_RXSR		0x02 /* Receiver soft reset */
+#define UART_FCR_TXSR		0x04 /* Transmitter soft reset */
+
+/*
+ * These are the definitions for the Modem Control Register
+ */
+#define UART_MCR_DTR	0x01		/* DTR   */
+#define UART_MCR_RTS	0x02		/* RTS   */
+#define UART_MCR_OUT1	0x04		/* Out 1 */
+#define UART_MCR_OUT2	0x08		/* Out 2 */
+#define UART_MCR_LOOP	0x10		/* Enable loopback test mode */
+#define UART_MCR_AFE	0x20		/* Enable auto-RTS/CTS */
+
+#define UART_MCR_DMA_EN	0x04
+#define UART_MCR_TX_DFR	0x08
+
+/*
+ * These are the definitions for the Line Control Register
+ *
+ * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
+ * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
+ */
+#define UART_LCR_WLS_MSK 0x03		/* character length select mask */
+#define UART_LCR_WLS_5	0x00		/* 5 bit character length */
+#define UART_LCR_WLS_6	0x01		/* 6 bit character length */
+#define UART_LCR_WLS_7	0x02		/* 7 bit character length */
+#define UART_LCR_WLS_8	0x03		/* 8 bit character length */
+#define UART_LCR_STB	0x04		/* # stop Bits, off=1, on=1.5 or 2) */
+#define UART_LCR_PEN	0x08		/* Parity eneble */
+#define UART_LCR_EPS	0x10		/* Even Parity Select */
+#define UART_LCR_STKP	0x20		/* Stick Parity */
+#define UART_LCR_SBRK	0x40		/* Set Break */
+#define UART_LCR_BKSE	0x80		/* Bank select enable */
+#define UART_LCR_DLAB	0x80		/* Divisor latch access bit */
+
+/*
+ * These are the definitions for the Line Status Register
+ */
+#define UART_LSR_DR	0x01		/* Data ready */
+#define UART_LSR_OE	0x02		/* Overrun */
+#define UART_LSR_PE	0x04		/* Parity error */
+#define UART_LSR_FE	0x08		/* Framing error */
+#define UART_LSR_BI	0x10		/* Break */
+#define UART_LSR_THRE	0x20		/* Xmit holding register empty */
+#define UART_LSR_TEMT	0x40		/* Xmitter empty */
+#define UART_LSR_ERR	0x80		/* Error */
+
+#define UART_MSR_DCD	0x80		/* Data Carrier Detect */
+#define UART_MSR_RI	0x40		/* Ring Indicator */
+#define UART_MSR_DSR	0x20		/* Data Set Ready */
+#define UART_MSR_CTS	0x10		/* Clear to Send */
+#define UART_MSR_DDCD	0x08		/* Delta DCD */
+#define UART_MSR_TERI	0x04		/* Trailing edge ring indicator */
+#define UART_MSR_DDSR	0x02		/* Delta DSR */
+#define UART_MSR_DCTS	0x01		/* Delta CTS */
+
+/*
+ * These are the definitions for the Interrupt Identification Register
+ */
+#define UART_IIR_NO_INT	0x01	/* No interrupts pending */
+#define UART_IIR_ID	0x06	/* Mask for the interrupt ID */
+
+#define UART_IIR_MSI	0x00	/* Modem status interrupt */
+#define UART_IIR_THRI	0x02	/* Transmitter holding register empty */
+#define UART_IIR_RDI	0x04	/* Receiver data interrupt */
+#define UART_IIR_RLSI	0x06	/* Receiver line status interrupt */
+
+/*
+ * These are the definitions for the Interrupt Enable Register
+ */
+#define UART_IER_MSI	0x08	/* Enable Modem status interrupt */
+#define UART_IER_RLSI	0x04	/* Enable receiver line status interrupt */
+#define UART_IER_THRI	0x02	/* Enable Transmitter holding register int. */
+#define UART_IER_RDI	0x01	/* Enable receiver data interrupt */
+
+
+#ifdef CONFIG_OMAP1510
+#define OSC_12M_SEL	0x01	/* selects 6.5 * current clk div */
+#endif
+
+/* useful defaults for LCR */
+#define UART_LCR_8N1	0x03
+
+void NS16550_init(NS16550_t com_port, int baud_divisor);
+void NS16550_putc(NS16550_t com_port, char c);
+char NS16550_getc(NS16550_t com_port);
+int NS16550_tstc(NS16550_t com_port);
+void NS16550_reinit(NS16550_t com_port, int baud_divisor);
diff --git a/qemu/roms/u-boot/include/ns87308.h b/qemu/roms/u-boot/include/ns87308.h
new file mode 100644
index 000000000..00b191639
--- /dev/null
+++ b/qemu/roms/u-boot/include/ns87308.h
@@ -0,0 +1,234 @@
+/*
+ * (C) Copyright 2000
+ * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _NS87308_H_
+#define _NS87308_H_
+
+#include <asm/pci_io.h>
+
+/* Note: I couldn't find a full data sheet for the ns87308, but the ns87307 seems to be pretty
+   functionally- (and pin-) equivalent to the 87308, but the 308 has better ir support. */
+
+void initialise_ns87308(void);
+
+/*
+ * The following struct represents the GPIO registers on the NS87308/NS97307
+ */
+struct GPIO
+{
+  unsigned char dta1;  /* 0 data port 1 */
+  unsigned char dir1;  /* 1 direction port 1 */
+  unsigned char out1;  /* 2 output type port 1 */
+  unsigned char puc1;  /* 3 pull-up control port 1 */
+  unsigned char dta2;  /* 4 data port 2 */
+  unsigned char dir2;  /* 5 direction port 2 */
+  unsigned char out2;  /* 6 output type port 2 */
+  unsigned char puc2;  /* 7 pull-up control port 2  */
+};
+
+/*
+ * The following represents the power management registers on the NS87308/NS97307
+ */
+#define PWM_FER1 0  /* 0 function enable reg. 1 */
+#define PWM_FER2 1  /* 1 function enable reg. 2 */
+#define PWM_PMC1 2  /* 2 power mgmt. control 1 */
+#define PWM_PMC2 3  /* 3 power mgmt. control 2 */
+#define PWM_PMC3 4  /* 4 power mgmt. control 3 */
+#define PWM_WDTO 5  /* 5 watchdog time-out */
+#define PWM_WDCF 6  /* 6 watchdog config. */
+#define PWM_WDST 7  /* 7 watchdog status  */
+
+/*PNP config registers:
+ * these depend on the stated of BADDR1 and BADDR0 on startup
+ * so there's three versions here with the last two digits indicating
+ * for which configuration their valid
+ * the 1st of the two digits indicates the state of BADDR1
+ * the 2st of the two digits indicates the state of BADDR0
+ */
+
+
+#define IO_INDEX_OFFSET_0x 0x0279  /* full PnP isa Mode */
+#define IO_INDEX_OFFSET_10 0x015C  /* PnP motherboard mode */
+#define IO_INDEX_OFFSET_11 0x002E  /* PnP motherboard mode */
+#define IO_DATA_OFFSET_0x  0x0A79  /* full PnP isa Mode */
+#define IO_DATA_OFFSET_10  0x015D  /* PnP motherboard mode */
+#define IO_DATA_OFFSET_11  0x002F  /* PnP motherboard mode */
+
+#if defined(CONFIG_SYS_NS87308_BADDR_0x)
+#define IO_INDEX (CONFIG_SYS_ISA_IO + IO_INDEX_OFFSET_0x)
+#define IO_DATA  (CONFIG_SYS_ISA_IO + IO_DATA_OFFSET_0x)
+#elif defined(CONFIG_SYS_NS87308_BADDR_10)
+#define IO_INDEX (CONFIG_SYS_ISA_IO + IO_INDEX_OFFSET_10)
+#define IO_DATA  (CONFIG_SYS_ISA_IO + IO_DATA_OFFSET_10)
+#elif defined(CONFIG_SYS_NS87308_BADDR_11)
+#define IO_INDEX (CONFIG_SYS_ISA_IO + IO_INDEX_OFFSET_11)
+#define IO_DATA  (CONFIG_SYS_ISA_IO + IO_DATA_OFFSET_11)
+#endif
+
+/* PnP register definitions */
+
+#define SET_RD_DATA_PORT    0x00
+#define SERIAL_ISOLATION    0x01
+#define CONFIG_CONTROL      0x02
+#define WAKE_CSN            0x03
+#define RES_DATA            0x04
+#define STATUS              0x05
+#define SET_CSN             0x06
+#define LOGICAL_DEVICE      0x07
+
+/*vendor defined values */
+#define SID_REG             0x20
+#define SUPOERIO_CONF1      0x21
+#define SUPOERIO_CONF2      0x22
+#define PGCS_INDEX          0x23
+#define PGCS_DATA           0x24
+
+/* values above 30 are different for each logical device
+   but I can't be arsed to enter them all. the ones here
+   are pretty consistent between all logical devices
+   feel free to correct the situation if you want.. ;)
+   */
+#define ACTIVATE            0x30
+#define ACTIVATE_OFF        0x00
+#define ACTIVATE_ON         0x01
+
+#define BASE_ADDR_HIGH      0x60
+#define BASE_ADDR_LOW       0x61
+#define LUN_CONFIG_REG		0xF0
+#define DBASE_HIGH			0x60	/* SIO KBC data base address, 15:8 */
+#define DBASE_LOW			0x61	/* SIO KBC data base address,  7:0 */
+#define CBASE_HIGH			0x62	/* SIO KBC command base addr, 15:8 */
+#define CBASE_LOW			0x63	/* SIO KBC command base addr,  7:0 */
+
+/* the logical devices*/
+#define LDEV_KBC1           0x00	/* 2 devices for keyboard and mouse controller*/
+#define LDEV_KBC2           0x01
+#define LDEV_MOUSE          0x01
+#define LDEV_RTC_APC        0x02	/*Real Time Clock and Advanced Power Control*/
+#define LDEV_FDC            0x03	/*floppy disk controller*/
+#define LDEV_PARP           0x04	/*Parallel port*/
+#define LDEV_UART2          0x05
+#define LDEV_UART1          0x06
+#define LDEV_GPIO           0x07    /*General Purpose IO and chip select output signals*/
+#define LDEV_POWRMAN        0x08    /*Power Managment*/
+
+#define CONFIG_SYS_NS87308_KBC1	(1 << LDEV_KBC1)
+#define CONFIG_SYS_NS87308_KBC2	(1 << LDEV_KBC2)
+#define CONFIG_SYS_NS87308_MOUSE	(1 << LDEV_MOUSE)
+#define CONFIG_SYS_NS87308_RTC_APC	(1 << LDEV_RTC_APC)
+#define CONFIG_SYS_NS87308_FDC		(1 << LDEV_FDC)
+#define CONFIG_SYS_NS87308_PARP	(1 << LDEV_PARP)
+#define CONFIG_SYS_NS87308_UART2	(1 << LDEV_UART2)
+#define CONFIG_SYS_NS87308_UART1	(1 << LDEV_UART1)
+#define CONFIG_SYS_NS87308_GPIO	(1 << LDEV_GPIO)
+#define CONFIG_SYS_NS87308_POWRMAN	(1 << LDEV_POWRMAN)
+
+/*some functions and macro's for doing configuration */
+
+static inline void read_pnp_config(unsigned char index, unsigned char *data)
+{
+    pci_writeb(index,IO_INDEX);
+    pci_readb(IO_DATA, *data);
+}
+
+static inline void write_pnp_config(unsigned char index, unsigned char data)
+{
+    pci_writeb(index,IO_INDEX);
+    pci_writeb(data, IO_DATA);
+}
+
+static inline void pnp_set_device(unsigned char dev)
+{
+    write_pnp_config(LOGICAL_DEVICE, dev);
+}
+
+static inline void write_pm_reg(unsigned short base, unsigned char index, unsigned char data)
+{
+    pci_writeb(index, CONFIG_SYS_ISA_IO + base);
+    eieio();
+    pci_writeb(data, CONFIG_SYS_ISA_IO + base + 1);
+}
+
+/*void write_pnp_config(unsigned char index, unsigned char data);
+void pnp_set_device(unsigned char dev);
+*/
+
+#define PNP_SET_DEVICE_BASE(dev,base) \
+   pnp_set_device(dev); \
+   write_pnp_config(ACTIVATE, ACTIVATE_OFF); \
+   write_pnp_config(BASE_ADDR_HIGH, ((base) >> 8) & 0xff ); \
+   write_pnp_config(BASE_ADDR_LOW, (base) &0xff); \
+   write_pnp_config(ACTIVATE, ACTIVATE_ON);
+
+#define PNP_ACTIVATE_DEVICE(dev) \
+   pnp_set_device(dev); \
+   write_pnp_config(ACTIVATE, ACTIVATE_ON);
+
+#define PNP_DEACTIVATE_DEVICE(dev) \
+   pnp_set_device(dev); \
+   write_pnp_config(ACTIVATE, ACTIVATE_OFF);
+
+
+static inline void write_pgcs_config(unsigned char index, unsigned char data)
+{
+    write_pnp_config(PGCS_INDEX, index);
+    write_pnp_config(PGCS_DATA, data);
+}
+
+/* these macrose configure the 3 CS lines
+   on the sandpoint board these controll NVRAM
+   CS0 is connected to NVRAMCS
+   CS1 is connected to NVRAMAS0
+   CS2 is connected to NVRAMAS1
+   */
+#define PGCS_CS_ASSERT_ON_WRITE 0x10
+#define PGCS_CS_ASSERT_ON_READ  0x20
+
+#define PNP_PGCS_CSLINE_BASE(cs, base) \
+  write_pgcs_config((cs) << 2, ((base) >> 8) & 0xff ); \
+  write_pgcs_config(((cs) << 2) + 1, (base) & 0xff );
+
+#define PNP_PGCS_CSLINE_CONF(cs, conf) \
+  write_pgcs_config(((cs) << 2) + 2, (conf) );
+
+
+/* The following sections are for 87308 extensions to the standard compoents it emulates */
+
+/* extensions to 16550*/
+
+#define MCR_MDSL_MSK    0xe0 /*mode select mask*/
+#define MCR_MDSL_UART   0x00 /*uart, default*/
+#define MCR_MDSL_SHRPIR 0x02 /*Sharp IR*/
+#define MCR_MDSL_SIR    0x03 /*SIR*/
+#define MCR_MDSL_CIR    0x06 /*Consumer IR*/
+
+#define FCR_TXFTH0      0x10    /* these bits control threshod of data level in fifo */
+#define FCR_TXFTH1      0x20    /* for interrupt trigger */
+
+/*
+ * Default NS87308 configuration
+ */
+#ifndef CONFIG_SYS_NS87308_KBC1_BASE
+#define CONFIG_SYS_NS87308_KBC1_BASE	0x0060
+#endif
+#ifndef CONFIG_SYS_NS87308_RTC_BASE
+#define CONFIG_SYS_NS87308_RTC_BASE	0x0070
+#endif
+#ifndef CONFIG_SYS_NS87308_FDC_BASE
+#define CONFIG_SYS_NS87308_FDC_BASE	0x03F0
+#endif
+#ifndef CONFIG_SYS_NS87308_LPT_BASE
+#define CONFIG_SYS_NS87308_LPT_BASE	0x0278
+#endif
+#ifndef CONFIG_SYS_NS87308_UART1_BASE
+#define CONFIG_SYS_NS87308_UART1_BASE	0x03F8
+#endif
+#ifndef CONFIG_SYS_NS87308_UART2_BASE
+#define CONFIG_SYS_NS87308_UART2_BASE	0x02F8
+#endif
+
+#endif /*_NS87308_H_*/
diff --git a/qemu/roms/u-boot/include/onenand_uboot.h b/qemu/roms/u-boot/include/onenand_uboot.h
new file mode 100644
index 000000000..fd0104081
--- /dev/null
+++ b/qemu/roms/u-boot/include/onenand_uboot.h
@@ -0,0 +1,54 @@
+/*
+ *  Header file for OneNAND support for U-Boot
+ *
+ *  Adaptation from kernel to U-Boot
+ *
+ *  Copyright (C) 2005-2007 Samsung Electronics
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __UBOOT_ONENAND_H
+#define __UBOOT_ONENAND_H
+
+#include <linux/types.h>
+
+/* Forward declarations */
+struct mtd_info;
+struct mtd_oob_ops;
+struct erase_info;
+struct onenand_chip;
+
+extern struct mtd_info onenand_mtd;
+extern struct onenand_chip onenand_chip;
+
+/* board */
+extern void onenand_board_init(struct mtd_info *);
+
+/* Functions */
+extern void onenand_init(void);
+extern int onenand_read(struct mtd_info *mtd, loff_t from, size_t len,
+			size_t * retlen, u_char * buf);
+extern int onenand_read_oob(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops);
+extern int onenand_write(struct mtd_info *mtd, loff_t from, size_t len,
+			 size_t * retlen, const u_char * buf);
+extern int onenand_erase(struct mtd_info *mtd, struct erase_info *instr);
+
+extern char *onenand_print_device_info(int device, int version);
+
+extern unsigned onenand_block(struct onenand_chip *this, loff_t addr);
+
+extern loff_t onenand_addr(struct onenand_chip *this, int block);
+
+extern int flexonenand_region(struct mtd_info *mtd, loff_t addr);
+
+extern int flexonenand_set_boundary(struct mtd_info *mtd, int die,
+					int boundary, int lock);
+
+/* SPL */
+void onenand_spl_load_image(uint32_t offs, uint32_t size, void *dst);
+
+#endif /* __UBOOT_ONENAND_H */
diff --git a/qemu/roms/u-boot/include/os.h b/qemu/roms/u-boot/include/os.h
new file mode 100644
index 000000000..0230a7f40
--- /dev/null
+++ b/qemu/roms/u-boot/include/os.h
@@ -0,0 +1,279 @@
+/*
+ * Operating System Interface
+ *
+ * This provides access to useful OS routines for the sandbox architecture.
+ * They are kept in a separate file so we can include system headers.
+ *
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __OS_H__
+#define __OS_H__
+
+#include <linux/types.h>
+
+struct sandbox_state;
+
+/**
+ * Access to the OS read() system call
+ *
+ * \param fd	File descriptor as returned by os_open()
+ * \param buf	Buffer to place data
+ * \param count	Number of bytes to read
+ * \return number of bytes read, or -1 on error
+ */
+ssize_t os_read(int fd, void *buf, size_t count);
+
+/**
+ * Access to the OS read() system call with non-blocking access
+ *
+ * \param fd	File descriptor as returned by os_open()
+ * \param buf	Buffer to place data
+ * \param count	Number of bytes to read
+ * \return number of bytes read, or -1 on error
+ */
+ssize_t os_read_no_block(int fd, void *buf, size_t count);
+
+/**
+ * Access to the OS write() system call
+ *
+ * \param fd	File descriptor as returned by os_open()
+ * \param buf	Buffer containing data to write
+ * \param count	Number of bytes to write
+ * \return number of bytes written, or -1 on error
+ */
+ssize_t os_write(int fd, const void *buf, size_t count);
+
+/**
+ * Access to the OS lseek() system call
+ *
+ * \param fd	File descriptor as returned by os_open()
+ * \param offset	File offset (based on whence)
+ * \param whence	Position offset is relative to (see below)
+ * \return new file offset
+ */
+off_t os_lseek(int fd, off_t offset, int whence);
+
+/* Defines for "whence" in os_lseek() */
+#define OS_SEEK_SET	0
+#define OS_SEEK_CUR	1
+#define OS_SEEK_END	2
+
+/**
+ * Access to the OS open() system call
+ *
+ * \param pathname	Pathname of file to open
+ * \param flags		Flags, like O_RDONLY, O_RDWR
+ * \return file descriptor, or -1 on error
+ */
+int os_open(const char *pathname, int flags);
+
+#define OS_O_RDONLY	0
+#define OS_O_WRONLY	1
+#define OS_O_RDWR	2
+#define OS_O_MASK	3	/* Mask for read/write flags */
+#define OS_O_CREAT	0100
+
+/**
+ * Access to the OS close() system call
+ *
+ * \param fd	File descriptor to close
+ * \return 0 on success, -1 on error
+ */
+int os_close(int fd);
+
+/**
+ * Access to the OS unlink() system call
+ *
+ * \param pathname Path of file to delete
+ * \return 0 for success, other for error
+ */
+int os_unlink(const char *pathname);
+
+/**
+ * Access to the OS exit() system call
+ *
+ * This exits with the supplied return code, which should be 0 to indicate
+ * success.
+ *
+ * @param exit_code	exit code for U-Boot
+ */
+void os_exit(int exit_code) __attribute__((noreturn));
+
+/**
+ * Put tty into raw mode to mimic serial console better
+ *
+ * @param fd		File descriptor of stdin (normally 0)
+ * @param allow_sigs	Allow Ctrl-C, Ctrl-Z to generate signals rather than
+ *			be handled by U-Boot
+ */
+void os_tty_raw(int fd, bool allow_sigs);
+
+/**
+ * Acquires some memory from the underlying os.
+ *
+ * \param length	Number of bytes to be allocated
+ * \return Pointer to length bytes or NULL on error
+ */
+void *os_malloc(size_t length);
+
+/**
+ * Free memory previous allocated with os_malloc()/os_realloc()
+ *
+ * This returns the memory to the OS.
+ *
+ * \param ptr		Pointer to memory block to free
+ */
+void os_free(void *ptr);
+
+/**
+ * Reallocate previously-allocated memory to increase/decrease space
+ *
+ * This works in a similar way to the C library realloc() function. If
+ * length is 0, then ptr is freed. Otherwise the space used by ptr is
+ * expanded or reduced depending on whether length is larger or smaller
+ * than before.
+ *
+ * If ptr is NULL, then this is similar to calling os_malloc().
+ *
+ * This function may need to move the memory block to make room for any
+ * extra space, in which case the new pointer is returned.
+ *
+ * \param ptr		Pointer to memory block to reallocate
+ * \param length	New length for memory block
+ * \return pointer to new memory block, or NULL on failure or if length
+ *	is 0.
+ */
+void *os_realloc(void *ptr, size_t length);
+
+/**
+ * Access to the usleep function of the os
+ *
+ * \param usec Time to sleep in micro seconds
+ */
+void os_usleep(unsigned long usec);
+
+/**
+ * Gets a monotonic increasing number of nano seconds from the OS
+ *
+ * \return A monotonic increasing time scaled in nano seconds
+ */
+uint64_t os_get_nsec(void);
+
+/**
+ * Parse arguments and update sandbox state.
+ *
+ * @param state		Sandbox state to update
+ * @param argc		Argument count
+ * @param argv		Argument vector
+ * @return 0 if ok, and program should continue;
+ *	1 if ok, but program should stop;
+ *	-1 on error: program should terminate.
+ */
+int os_parse_args(struct sandbox_state *state, int argc, char *argv[]);
+
+/*
+ * Types of directory entry that we support. See also os_dirent_typename in
+ * the C file.
+ */
+enum os_dirent_t {
+	OS_FILET_REG,		/* Regular file */
+	OS_FILET_LNK,		/* Symbolic link */
+	OS_FILET_DIR,		/* Directory */
+	OS_FILET_UNKNOWN,	/* Something else */
+
+	OS_FILET_COUNT,
+};
+
+/** A directory entry node, containing information about a single dirent */
+struct os_dirent_node {
+	struct os_dirent_node *next;	/* Pointer to next node, or NULL */
+	ulong size;			/* Size of file in bytes */
+	enum os_dirent_t type;		/* Type of entry */
+	char name[0];			/* Name of entry */
+};
+
+/**
+ * Get a directionry listing
+ *
+ * This allocates and returns a linked list containing the directory listing.
+ *
+ * @param dirname	Directory to examine
+ * @param headp		Returns pointer to head of linked list, or NULL if none
+ * @return 0 if ok, -ve on error
+ */
+int os_dirent_ls(const char *dirname, struct os_dirent_node **headp);
+
+/**
+ * Get the name of a directory entry type
+ *
+ * @param type		Type to cehck
+ * @return string containing the name of that type, or "???" if none/invalid
+ */
+const char *os_dirent_get_typename(enum os_dirent_t type);
+
+/**
+ * Get the size of a file
+ *
+ * @param fname		Filename to check
+ * @return size of file, or -1 if an error ocurred
+ */
+ssize_t os_get_filesize(const char *fname);
+
+/**
+ * Write a character to the controlling OS terminal
+ *
+ * This bypasses the U-Boot console support and writes directly to the OS
+ * stdout file descriptor.
+ *
+ * @param ch	Character to write
+ */
+void os_putc(int ch);
+
+/**
+ * Write a string to the controlling OS terminal
+ *
+ * This bypasses the U-Boot console support and writes directly to the OS
+ * stdout file descriptor.
+ *
+ * @param str	String to write (note that \n is not appended)
+ */
+void os_puts(const char *str);
+
+/**
+ * Write the sandbox RAM buffer to a existing file
+ *
+ * @param fname		Filename to write memory to (simple binary format)
+ * @return 0 if OK, -ve on error
+ */
+int os_write_ram_buf(const char *fname);
+
+/**
+ * Read the sandbox RAM buffer from an existing file
+ *
+ * @param fname		Filename containing memory (simple binary format)
+ * @return 0 if OK, -ve on error
+ */
+int os_read_ram_buf(const char *fname);
+
+/**
+ * Jump to a new executable image
+ *
+ * This uses exec() to run a new executable image, after putting it in a
+ * temporary file. The same arguments and environment are passed to this
+ * new image, with the addition of:
+ *
+ *	-j <filename>	Specifies the filename the image was written to. The
+ *			calling image may want to delete this at some point.
+ *	-m <filename>	Specifies the file containing the sandbox memory
+ *			(ram_buf) from this image, so that the new image can
+ *			have access to this. It also means that the original
+ *			memory filename passed to U-Boot will be left intact.
+ *
+ * @param dest		Buffer containing executable image
+ * @param size		Size of buffer
+ */
+int os_jump_to_image(const void *dest, int size);
+
+#endif
diff --git a/qemu/roms/u-boot/include/palmas.h b/qemu/roms/u-boot/include/palmas.h
new file mode 100644
index 000000000..eaf367086
--- /dev/null
+++ b/qemu/roms/u-boot/include/palmas.h
@@ -0,0 +1,124 @@
+/*
+ * (C) Copyright 2012-2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef PALMAS_H
+#define PALMAS_H
+
+#include <common.h>
+#include <i2c.h>
+
+/* I2C chip addresses, TW6035/37 */
+#define TWL603X_CHIP_P1		0x48	/* Page 1 */
+#define TWL603X_CHIP_P2		0x49	/* Page 2 */
+#define TWL603X_CHIP_P3		0x4a	/* Page 3 */
+
+/* TPS659038/39 */
+#define TPS65903X_CHIP_P1	0x58	/* Page 1 */
+
+/* Page 1 registers (0x1XY translates to page 1, reg addr 0xXY): */
+
+/* LDO1 control/voltage */
+#define LDO1_CTRL		0x50
+#define LDO1_VOLTAGE		0x51
+
+/* LDO9 control/voltage */
+#define LDO9_CTRL		0x60
+#define LDO9_VOLTAGE		0x61
+
+/* LDOUSB control/voltage */
+#define LDOUSB_CTRL		0x64
+#define LDOUSB_VOLTAGE		0x65
+#define LDO_CTRL		0x6a
+
+/* Control of 32 kHz audio clock */
+#define CLK32KGAUDIO_CTRL	0xd5
+
+/* SYSEN2_CTRL for VCC_3v3_AUX supply on the sEVM */
+#define SYSEN2_CTRL		0xd9
+
+/*
+ * Bit field definitions for LDOx_CTRL, SYSENx_CTRL
+ * and some other xxx_CTRL resources:
+ */
+#define LDO9_BYP_EN		(1 << 6)	/* LDO9 only! */
+#define RSC_STAT_ON		(1 << 4)	/* RO status bit! */
+#define RSC_MODE_SLEEP		(1 << 2)
+#define RSC_MODE_ACTIVE		(1 << 0)
+
+/* Some LDO voltage values */
+#define LDO_VOLT_OFF		0
+#define LDO_VOLT_1V8		0x13
+#define LDO_VOLT_3V0		0x2b
+#define LDO_VOLT_3V3		0x31
+/* Request bypass, LDO9 only */
+#define LDO9_BYPASS		0x3f
+
+/* SMPS7_CTRL */
+#define SMPS7_CTRL		0x30
+
+/* SMPS9_CTRL */
+#define SMPS9_CTRL		0x38
+#define SMPS9_VOLTAGE		0x3b
+
+/* SMPS10_CTRL */
+#define SMPS10_CTRL		0x3c
+#define SMPS10_MODE_ACTIVE_D	0x0d
+
+/* Bit field definitions for SMPSx_CTRL */
+#define SMPS_MODE_ACT_AUTO	1
+#define SMPS_MODE_ACT_ECO	2
+#define SMPS_MODE_ACT_FPWM	3
+#define SMPS_MODE_SLP_AUTO	(1 << 2)
+#define SMPS_MODE_SLP_ECO	(2 << 2)
+#define SMPS_MODE_SLP_FPWM	(3 << 2)
+
+/*
+ * Some popular SMPS voltages, all with RANGE=1; note
+ * that RANGE cannot be changed on the fly
+ */
+#define SMPS_VOLT_OFF		0
+#define SMPS_VOLT_1V2		0x90
+#define SMPS_VOLT_1V8		0xae
+#define SMPS_VOLT_2V1		0xbd
+#define SMPS_VOLT_3V0		0xea
+#define SMPS_VOLT_3V3		0xf9
+
+/* Backup Battery & VRTC Control */
+#define BB_VRTC_CTRL		0xa8
+/* Bit definitions for BB_VRTC_CTRL */
+#define VRTC_EN_SLP		(1 << 6)
+#define VRTC_EN_OFF		(1 << 5)
+#define VRTC_PWEN		(1 << 4)
+#define BB_LOW_ICHRG		(1 << 3)
+#define BB_HIGH_ICHRG		(0 << 3)
+#define BB_VSEL_3V0		(0 << 1)
+#define BB_VSEL_2V5		(1 << 1)
+#define BB_VSEL_3V15		(2 << 1)
+#define BB_VSEL_VBAT		(3 << 1)
+#define BB_CHRG_EN		(1 << 0)
+
+/*
+ * Functions to read and write from TPS659038/TWL6035/TWL6037
+ * or other Palmas family of TI PMICs
+ */
+static inline int palmas_i2c_write_u8(u8 chip_no, u8 reg, u8 val)
+{
+	return i2c_write(chip_no, reg, 1, &val, 1);
+}
+
+static inline int palmas_i2c_read_u8(u8 chip_no, u8 reg, u8 *val)
+{
+	return i2c_read(chip_no, reg, 1, val, 1);
+}
+
+void palmas_init_settings(void);
+int palmas_mmc1_poweron_ldo(void);
+int twl603x_mmc1_set_ldo9(u8 vsel);
+int twl603x_audio_power(u8 on);
+int twl603x_enable_bb_charge(u8 bb_fields);
+int palmas_enable_ss_ldo(void);
+
+#endif /* PALMAS_H */
diff --git a/qemu/roms/u-boot/include/part.h b/qemu/roms/u-boot/include/part.h
new file mode 100644
index 000000000..53532dcd6
--- /dev/null
+++ b/qemu/roms/u-boot/include/part.h
@@ -0,0 +1,236 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _PART_H
+#define _PART_H
+
+#include <ide.h>
+#include <common.h>
+
+typedef struct block_dev_desc {
+	int		if_type;	/* type of the interface */
+	int		dev;		/* device number */
+	unsigned char	part_type;	/* partition type */
+	unsigned char	target;		/* target SCSI ID */
+	unsigned char	lun;		/* target LUN */
+	unsigned char	type;		/* device type */
+	unsigned char	removable;	/* removable device */
+#ifdef CONFIG_LBA48
+	unsigned char	lba48;		/* device can use 48bit addr (ATA/ATAPI v7) */
+#endif
+	lbaint_t	lba;		/* number of blocks */
+	unsigned long	blksz;		/* block size */
+	int		log2blksz;	/* for convenience: log2(blksz) */
+	char		vendor [40+1];	/* IDE model, SCSI Vendor */
+	char		product[20+1];	/* IDE Serial no, SCSI product */
+	char		revision[8+1];	/* firmware revision */
+	unsigned long	(*block_read)(int dev,
+				      lbaint_t start,
+				      lbaint_t blkcnt,
+				      void *buffer);
+	unsigned long	(*block_write)(int dev,
+				       lbaint_t start,
+				       lbaint_t blkcnt,
+				       const void *buffer);
+	unsigned long   (*block_erase)(int dev,
+				       lbaint_t start,
+				       lbaint_t blkcnt);
+	void		*priv;		/* driver private struct pointer */
+}block_dev_desc_t;
+
+#define BLOCK_CNT(size, block_dev_desc) (PAD_COUNT(size, block_dev_desc->blksz))
+#define PAD_TO_BLOCKSIZE(size, block_dev_desc) \
+	(PAD_SIZE(size, block_dev_desc->blksz))
+#define LOG2(x) (((x & 0xaaaaaaaa) ? 1 : 0) + ((x & 0xcccccccc) ? 2 : 0) + \
+		 ((x & 0xf0f0f0f0) ? 4 : 0) + ((x & 0xff00ff00) ? 8 : 0) + \
+		 ((x & 0xffff0000) ? 16 : 0))
+#define LOG2_INVALID(type) ((type)((sizeof(type)<<3)-1))
+
+/* Interface types: */
+#define IF_TYPE_UNKNOWN		0
+#define IF_TYPE_IDE		1
+#define IF_TYPE_SCSI		2
+#define IF_TYPE_ATAPI		3
+#define IF_TYPE_USB		4
+#define IF_TYPE_DOC		5
+#define IF_TYPE_MMC		6
+#define IF_TYPE_SD		7
+#define IF_TYPE_SATA		8
+#define IF_TYPE_HOST		9
+#define IF_TYPE_MAX		10	/* Max number of IF_TYPE_* supported */
+
+/* Part types */
+#define PART_TYPE_UNKNOWN	0x00
+#define PART_TYPE_MAC		0x01
+#define PART_TYPE_DOS		0x02
+#define PART_TYPE_ISO		0x03
+#define PART_TYPE_AMIGA		0x04
+#define PART_TYPE_EFI		0x05
+
+/*
+ * Type string for U-Boot bootable partitions
+ */
+#define BOOT_PART_TYPE	"U-Boot"	/* primary boot partition type	*/
+#define BOOT_PART_COMP	"PPCBoot"	/* PPCBoot compatibility type	*/
+
+/* device types */
+#define DEV_TYPE_UNKNOWN	0xff	/* not connected */
+#define DEV_TYPE_HARDDISK	0x00	/* harddisk */
+#define DEV_TYPE_TAPE		0x01	/* Tape */
+#define DEV_TYPE_CDROM		0x05	/* CD-ROM */
+#define DEV_TYPE_OPDISK		0x07	/* optical disk */
+
+typedef struct disk_partition {
+	lbaint_t	start;	/* # of first block in partition	*/
+	lbaint_t	size;	/* number of blocks in partition	*/
+	ulong	blksz;		/* block size in bytes			*/
+	uchar	name[32];	/* partition name			*/
+	uchar	type[32];	/* string type description		*/
+	int	bootable;	/* Active/Bootable flag is set		*/
+#ifdef CONFIG_PARTITION_UUIDS
+	char	uuid[37];	/* filesystem UUID as string, if exists	*/
+#endif
+} disk_partition_t;
+
+/* Misc _get_dev functions */
+#ifdef CONFIG_PARTITIONS
+block_dev_desc_t *get_dev(const char *ifname, int dev);
+block_dev_desc_t* ide_get_dev(int dev);
+block_dev_desc_t* sata_get_dev(int dev);
+block_dev_desc_t* scsi_get_dev(int dev);
+block_dev_desc_t* usb_stor_get_dev(int dev);
+block_dev_desc_t* mmc_get_dev(int dev);
+block_dev_desc_t* systemace_get_dev(int dev);
+block_dev_desc_t* mg_disk_get_dev(int dev);
+block_dev_desc_t *host_get_dev(int dev);
+int host_get_dev_err(int dev, block_dev_desc_t **blk_devp);
+
+/* disk/part.c */
+int get_partition_info (block_dev_desc_t * dev_desc, int part, disk_partition_t *info);
+void print_part (block_dev_desc_t *dev_desc);
+void  init_part (block_dev_desc_t *dev_desc);
+void dev_print(block_dev_desc_t *dev_desc);
+int get_device(const char *ifname, const char *dev_str,
+	       block_dev_desc_t **dev_desc);
+int get_device_and_partition(const char *ifname, const char *dev_part_str,
+			     block_dev_desc_t **dev_desc,
+			     disk_partition_t *info, int allow_whole_dev);
+#else
+static inline block_dev_desc_t *get_dev(const char *ifname, int dev)
+{ return NULL; }
+static inline block_dev_desc_t* ide_get_dev(int dev) { return NULL; }
+static inline block_dev_desc_t* sata_get_dev(int dev) { return NULL; }
+static inline block_dev_desc_t* scsi_get_dev(int dev) { return NULL; }
+static inline block_dev_desc_t* usb_stor_get_dev(int dev) { return NULL; }
+static inline block_dev_desc_t* mmc_get_dev(int dev) { return NULL; }
+static inline block_dev_desc_t* systemace_get_dev(int dev) { return NULL; }
+static inline block_dev_desc_t* mg_disk_get_dev(int dev) { return NULL; }
+static inline block_dev_desc_t *host_get_dev(int dev) { return NULL; }
+
+static inline int get_partition_info (block_dev_desc_t * dev_desc, int part,
+	disk_partition_t *info) { return -1; }
+static inline void print_part (block_dev_desc_t *dev_desc) {}
+static inline void  init_part (block_dev_desc_t *dev_desc) {}
+static inline void dev_print(block_dev_desc_t *dev_desc) {}
+static inline int get_device(const char *ifname, const char *dev_str,
+	       block_dev_desc_t **dev_desc)
+{ return -1; }
+static inline int get_device_and_partition(const char *ifname,
+					   const char *dev_part_str,
+					   block_dev_desc_t **dev_desc,
+					   disk_partition_t *info,
+					   int allow_whole_dev)
+{ *dev_desc = NULL; return -1; }
+#endif
+
+#ifdef CONFIG_MAC_PARTITION
+/* disk/part_mac.c */
+int get_partition_info_mac (block_dev_desc_t * dev_desc, int part, disk_partition_t *info);
+void print_part_mac (block_dev_desc_t *dev_desc);
+int   test_part_mac (block_dev_desc_t *dev_desc);
+#endif
+
+#ifdef CONFIG_DOS_PARTITION
+/* disk/part_dos.c */
+int get_partition_info_dos (block_dev_desc_t * dev_desc, int part, disk_partition_t *info);
+void print_part_dos (block_dev_desc_t *dev_desc);
+int   test_part_dos (block_dev_desc_t *dev_desc);
+#endif
+
+#ifdef CONFIG_ISO_PARTITION
+/* disk/part_iso.c */
+int get_partition_info_iso (block_dev_desc_t * dev_desc, int part, disk_partition_t *info);
+void print_part_iso (block_dev_desc_t *dev_desc);
+int   test_part_iso (block_dev_desc_t *dev_desc);
+#endif
+
+#ifdef CONFIG_AMIGA_PARTITION
+/* disk/part_amiga.c */
+int get_partition_info_amiga (block_dev_desc_t * dev_desc, int part, disk_partition_t *info);
+void print_part_amiga (block_dev_desc_t *dev_desc);
+int   test_part_amiga (block_dev_desc_t *dev_desc);
+#endif
+
+#ifdef CONFIG_EFI_PARTITION
+#include <part_efi.h>
+/* disk/part_efi.c */
+int get_partition_info_efi (block_dev_desc_t * dev_desc, int part, disk_partition_t *info);
+void print_part_efi (block_dev_desc_t *dev_desc);
+int   test_part_efi (block_dev_desc_t *dev_desc);
+
+/**
+ * write_gpt_table() - Write the GUID Partition Table to disk
+ *
+ * @param dev_desc - block device descriptor
+ * @param gpt_h - pointer to GPT header representation
+ * @param gpt_e - pointer to GPT partition table entries
+ *
+ * @return - zero on success, otherwise error
+ */
+int write_gpt_table(block_dev_desc_t *dev_desc,
+		  gpt_header *gpt_h, gpt_entry *gpt_e);
+
+/**
+ * gpt_fill_pte(): Fill the GPT partition table entry
+ *
+ * @param gpt_h - GPT header representation
+ * @param gpt_e - GPT partition table entries
+ * @param partitions - list of partitions
+ * @param parts - number of partitions
+ *
+ * @return zero on success
+ */
+int gpt_fill_pte(gpt_header *gpt_h, gpt_entry *gpt_e,
+		disk_partition_t *partitions, int parts);
+
+/**
+ * gpt_fill_header(): Fill the GPT header
+ *
+ * @param dev_desc - block device descriptor
+ * @param gpt_h - GPT header representation
+ * @param str_guid - disk guid string representation
+ * @param parts_count - number of partitions
+ *
+ * @return - error on str_guid conversion error
+ */
+int gpt_fill_header(block_dev_desc_t *dev_desc, gpt_header *gpt_h,
+		char *str_guid, int parts_count);
+
+/**
+ * gpt_restore(): Restore GPT partition table
+ *
+ * @param dev_desc - block device descriptor
+ * @param str_disk_guid - disk GUID
+ * @param partitions - list of partitions
+ * @param parts - number of partitions
+ *
+ * @return zero on success
+ */
+int gpt_restore(block_dev_desc_t *dev_desc, char *str_disk_guid,
+		disk_partition_t *partitions, const int parts_count);
+#endif
+
+#endif /* _PART_H */
diff --git a/qemu/roms/u-boot/include/part_efi.h b/qemu/roms/u-boot/include/part_efi.h
new file mode 100644
index 000000000..d68ef3bb3
--- /dev/null
+++ b/qemu/roms/u-boot/include/part_efi.h
@@ -0,0 +1,129 @@
+/*
+ * Copyright (C) 2008 RuggedCom, Inc.
+ * Richard Retanubun <RichardRetanubun@RuggedCom.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * See also linux/fs/partitions/efi.h
+ *
+ * EFI GUID Partition Table
+ * Per Intel EFI Specification v1.02
+ * http://developer.intel.com/technology/efi/efi.htm
+*/
+
+#include <linux/compiler.h>
+
+#ifndef _DISK_PART_EFI_H
+#define _DISK_PART_EFI_H
+
+#define MSDOS_MBR_SIGNATURE 0xAA55
+#define EFI_PMBR_OSTYPE_EFI 0xEF
+#define EFI_PMBR_OSTYPE_EFI_GPT 0xEE
+
+#define GPT_HEADER_SIGNATURE 0x5452415020494645ULL
+#define GPT_HEADER_REVISION_V1 0x00010000
+#define GPT_PRIMARY_PARTITION_TABLE_LBA 1ULL
+#define GPT_ENTRY_NAME "gpt"
+#define GPT_ENTRY_NUMBERS		128
+#define GPT_ENTRY_SIZE			128
+
+#define EFI_GUID(a,b,c,d0,d1,d2,d3,d4,d5,d6,d7) \
+	((efi_guid_t) \
+	{{ (a) & 0xff, ((a) >> 8) & 0xff, ((a) >> 16) & 0xff, ((a) >> 24) & 0xff, \
+		(b) & 0xff, ((b) >> 8) & 0xff, \
+		(c) & 0xff, ((c) >> 8) & 0xff, \
+		(d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) }})
+
+#define PARTITION_SYSTEM_GUID \
+	EFI_GUID( 0xC12A7328, 0xF81F, 0x11d2, \
+		0xBA, 0x4B, 0x00, 0xA0, 0xC9, 0x3E, 0xC9, 0x3B)
+#define LEGACY_MBR_PARTITION_GUID \
+	EFI_GUID( 0x024DEE41, 0x33E7, 0x11d3, \
+		0x9D, 0x69, 0x00, 0x08, 0xC7, 0x81, 0xF3, 0x9F)
+#define PARTITION_MSFT_RESERVED_GUID \
+	EFI_GUID( 0xE3C9E316, 0x0B5C, 0x4DB8, \
+		0x81, 0x7D, 0xF9, 0x2D, 0xF0, 0x02, 0x15, 0xAE)
+#define PARTITION_BASIC_DATA_GUID \
+	EFI_GUID( 0xEBD0A0A2, 0xB9E5, 0x4433, \
+		0x87, 0xC0, 0x68, 0xB6, 0xB7, 0x26, 0x99, 0xC7)
+#define PARTITION_LINUX_RAID_GUID \
+	EFI_GUID( 0xa19d880f, 0x05fc, 0x4d3b, \
+		0xa0, 0x06, 0x74, 0x3f, 0x0f, 0x84, 0x91, 0x1e)
+#define PARTITION_LINUX_SWAP_GUID \
+	EFI_GUID( 0x0657fd6d, 0xa4ab, 0x43c4, \
+		0x84, 0xe5, 0x09, 0x33, 0xc8, 0x4b, 0x4f, 0x4f)
+#define PARTITION_LINUX_LVM_GUID \
+	EFI_GUID( 0xe6d6d379, 0xf507, 0x44c2, \
+		0xa2, 0x3c, 0x23, 0x8f, 0x2a, 0x3d, 0xf9, 0x28)
+
+/* linux/include/efi.h */
+typedef u16 efi_char16_t;
+
+typedef struct {
+	u8 b[16];
+} efi_guid_t;
+
+/* based on linux/include/genhd.h */
+struct partition {
+	u8 boot_ind;		/* 0x80 - active */
+	u8 head;		/* starting head */
+	u8 sector;		/* starting sector */
+	u8 cyl;			/* starting cylinder */
+	u8 sys_ind;		/* What partition type */
+	u8 end_head;		/* end head */
+	u8 end_sector;		/* end sector */
+	u8 end_cyl;		/* end cylinder */
+	__le32 start_sect;	/* starting sector counting from 0 */
+	__le32 nr_sects;	/* nr of sectors in partition */
+} __packed;
+
+/* based on linux/fs/partitions/efi.h */
+typedef struct _gpt_header {
+	__le64 signature;
+	__le32 revision;
+	__le32 header_size;
+	__le32 header_crc32;
+	__le32 reserved1;
+	__le64 my_lba;
+	__le64 alternate_lba;
+	__le64 first_usable_lba;
+	__le64 last_usable_lba;
+	efi_guid_t disk_guid;
+	__le64 partition_entry_lba;
+	__le32 num_partition_entries;
+	__le32 sizeof_partition_entry;
+	__le32 partition_entry_array_crc32;
+} __packed gpt_header;
+
+typedef union _gpt_entry_attributes {
+	struct {
+		u64 required_to_function:1;
+		u64 no_block_io_protocol:1;
+		u64 legacy_bios_bootable:1;
+		u64 reserved:45;
+		u64 type_guid_specific:16;
+	} fields;
+	unsigned long long raw;
+} __packed gpt_entry_attributes;
+
+#define PARTNAME_SZ	(72 / sizeof(efi_char16_t))
+typedef struct _gpt_entry {
+	efi_guid_t partition_type_guid;
+	efi_guid_t unique_partition_guid;
+	__le64 starting_lba;
+	__le64 ending_lba;
+	gpt_entry_attributes attributes;
+	efi_char16_t partition_name[PARTNAME_SZ];
+} __packed gpt_entry;
+
+typedef struct _legacy_mbr {
+	u8 boot_code[440];
+	__le32 unique_mbr_signature;
+	__le16 unknown;
+	struct partition partition_record[4];
+	__le16 signature;
+} __packed legacy_mbr;
+
+#endif	/* _DISK_PART_EFI_H */
diff --git a/qemu/roms/u-boot/include/pc_keyb.h b/qemu/roms/u-boot/include/pc_keyb.h
new file mode 100644
index 000000000..5ba99e35a
--- /dev/null
+++ b/qemu/roms/u-boot/include/pc_keyb.h
@@ -0,0 +1,121 @@
+/*
+ *	include/linux/pc_keyb.h
+ *
+ *	PC Keyboard And Keyboard Controller
+ *
+ *	(c) 1997 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
+ */
+
+/*
+ *	Configuration Switches
+ */
+#undef KBD_REPORT_ERR			/* Report keyboard errors */
+#define KBD_REPORT_UNKN			/* Report unknown scan codes */
+#define KBD_REPORT_TIMEOUTS		/* Report keyboard timeouts */
+#undef KBD_IS_FOCUS_9000		/* We have the brain-damaged FOCUS-9000 keyboard */
+#undef INITIALIZE_MOUSE			/* Define if your PS/2 mouse needs initialization. */
+
+#define KBD_INIT_TIMEOUT 1000		/* Timeout in ms for initializing the keyboard */
+#define KBC_TIMEOUT 250			/* Timeout in ms for sending to keyboard controller */
+#define KBD_TIMEOUT 1000		/* Timeout in ms for keyboard command acknowledge */
+
+/*
+ *	Internal variables of the driver
+ */
+extern unsigned char pckbd_read_mask;
+extern unsigned char aux_device_present;
+
+/*
+ *	Keyboard Controller Registers on normal PCs.
+ */
+#define KBD_STATUS_REG		0x64	/* Status register (R) */
+#define KBD_CNTL_REG		0x64	/* Controller command register (W) */
+#define KBD_DATA_REG		0x60	/* Keyboard data register (R/W) */
+
+/*
+ *	Keyboard Controller Commands
+ */
+#define KBD_CCMD_READ_MODE	0x20	/* Read mode bits */
+#define KBD_CCMD_WRITE_MODE	0x60	/* Write mode bits */
+#define KBD_CCMD_GET_VERSION	0xA1	/* Get controller version */
+#define KBD_CCMD_MOUSE_DISABLE	0xA7	/* Disable mouse interface */
+#define KBD_CCMD_MOUSE_ENABLE	0xA8	/* Enable mouse interface */
+#define KBD_CCMD_TEST_MOUSE	0xA9	/* Mouse interface test */
+#define KBD_CCMD_SELF_TEST	0xAA	/* Controller self test */
+#define KBD_CCMD_KBD_TEST	0xAB	/* Keyboard interface test */
+#define KBD_CCMD_KBD_DISABLE	0xAD	/* Keyboard interface disable */
+#define KBD_CCMD_KBD_ENABLE	0xAE	/* Keyboard interface enable */
+#define KBD_CCMD_WRITE_AUX_OBUF	0xD3    /* Write to output buffer as if
+					   initiated by the auxiliary device */
+#define KBD_CCMD_WRITE_MOUSE	0xD4	/* Write the following byte to the mouse */
+
+/*
+ *	Keyboard Commands
+ */
+#define KBD_CMD_SET_LEDS	0xED	/* Set keyboard leds */
+#define KBD_CMD_SET_RATE	0xF3	/* Set typematic rate */
+#define KBD_CMD_ENABLE		0xF4	/* Enable scanning */
+#define KBD_CMD_DISABLE		0xF5	/* Disable scanning */
+#define KBD_CMD_RESET		0xFF	/* Reset */
+
+/*
+ *	Keyboard Replies
+ */
+#define KBD_REPLY_POR		0xAA	/* Power on reset */
+#define KBD_REPLY_ACK		0xFA	/* Command ACK */
+#define KBD_REPLY_RESEND	0xFE	/* Command NACK, send the cmd again */
+
+/*
+ *	Status Register Bits
+ */
+#define KBD_STAT_OBF		0x01	/* Keyboard output buffer full */
+#define KBD_STAT_IBF		0x02	/* Keyboard input buffer full */
+#define KBD_STAT_SELFTEST	0x04	/* Self test successful */
+#define KBD_STAT_CMD		0x08	/* Last write was a command write (0=data) */
+#define KBD_STAT_UNLOCKED	0x10	/* Zero if keyboard locked */
+#define KBD_STAT_MOUSE_OBF	0x20	/* Mouse output buffer full */
+#define KBD_STAT_GTO		0x40	/* General receive/xmit timeout */
+#define KBD_STAT_PERR		0x80	/* Parity error */
+
+#define AUX_STAT_OBF (KBD_STAT_OBF | KBD_STAT_MOUSE_OBF)
+
+/*
+ *	Controller Mode Register Bits
+ */
+#define KBD_MODE_KBD_INT	0x01	/* Keyboard data generate IRQ1 */
+#define KBD_MODE_MOUSE_INT	0x02	/* Mouse data generate IRQ12 */
+#define KBD_MODE_SYS		0x04	/* The system flag (?) */
+#define KBD_MODE_NO_KEYLOCK	0x08	/* The keylock doesn't affect the keyboard if set */
+#define KBD_MODE_DISABLE_KBD	0x10	/* Disable keyboard interface */
+#define KBD_MODE_DISABLE_MOUSE	0x20	/* Disable mouse interface */
+#define KBD_MODE_KCC		0x40	/* Scan code conversion to PC format */
+#define KBD_MODE_RFU		0x80
+
+/*
+ *	Mouse Commands
+ */
+#define AUX_SET_RES		0xE8	/* Set resolution */
+#define AUX_SET_SCALE11		0xE6	/* Set 1:1 scaling */
+#define AUX_SET_SCALE21		0xE7	/* Set 2:1 scaling */
+#define AUX_GET_SCALE		0xE9	/* Get scaling factor */
+#define AUX_SET_STREAM		0xEA	/* Set stream mode */
+#define AUX_SET_SAMPLE		0xF3	/* Set sample rate */
+#define AUX_ENABLE_DEV		0xF4	/* Enable aux device */
+#define AUX_DISABLE_DEV		0xF5	/* Disable aux device */
+#define AUX_RESET		0xFF	/* Reset aux device */
+#define AUX_ACK			0xFA	/* Command byte ACK. */
+
+#define AUX_BUF_SIZE		2048	/* This might be better divisible by
+					   three to make overruns stay in sync
+					   but then the read function would need
+					   a lock etc - ick */
+
+#if 0
+struct aux_queue {
+	unsigned long head;
+	unsigned long tail;
+	wait_queue_head_t proc_list;
+	struct fasync_struct *fasync;
+	unsigned char buf[AUX_BUF_SIZE];
+};
+#endif
diff --git a/qemu/roms/u-boot/include/pca953x.h b/qemu/roms/u-boot/include/pca953x.h
new file mode 100644
index 000000000..6c2b58c56
--- /dev/null
+++ b/qemu/roms/u-boot/include/pca953x.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __PCA953X_H_
+#define __PCA953X_H_
+
+#define PCA953X_IN		0x00
+#define PCA953X_OUT		0x01
+#define PCA953X_POL		0x02
+#define PCA953X_CONF		0x03
+
+#define PCA953X_OUT_LOW		0
+#define PCA953X_OUT_HIGH	1
+#define PCA953X_POL_NORMAL	0
+#define PCA953X_POL_INVERT	1
+#define PCA953X_DIR_OUT		0
+#define PCA953X_DIR_IN		1
+
+int pca953x_set_val(u8 chip, uint mask, uint data);
+int pca953x_set_pol(u8 chip, uint mask, uint data);
+int pca953x_set_dir(u8 chip, uint mask, uint data);
+int pca953x_get_val(u8 chip);
+
+#endif /* __PCA953X_H_ */
diff --git a/qemu/roms/u-boot/include/pca9564.h b/qemu/roms/u-boot/include/pca9564.h
new file mode 100644
index 000000000..4b4b695c4
--- /dev/null
+++ b/qemu/roms/u-boot/include/pca9564.h
@@ -0,0 +1,36 @@
+/*
+ * File:         include/pca9564.h
+ * Author:
+ *
+ * Created:      2009-06-23
+ * Description:  PCA9564 i2c bridge driver
+ *
+ * Modified:
+ *               Copyright 2009 CJSC "NII STT", http://www.niistt.ru/
+ *
+ * Bugs:
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _PCA9564_H
+#define _PCA9564_H
+
+/* Clock speeds for the bus */
+#define PCA_CON_330kHz      0x00
+#define PCA_CON_288kHz      0x01
+#define PCA_CON_217kHz      0x02
+#define PCA_CON_146kHz      0x03
+#define PCA_CON_88kHz       0x04
+#define PCA_CON_59kHz       0x05
+#define PCA_CON_44kHz       0x06
+#define PCA_CON_36kHz       0x07
+
+#define PCA_CON_AA          0x80 /* Assert Acknowledge */
+#define PCA_CON_ENSIO       0x40 /* Enable */
+#define PCA_CON_STA         0x20 /* Start */
+#define PCA_CON_STO         0x10 /* Stop */
+#define PCA_CON_SI          0x08 /* Serial Interrupt */
+#define PCA_CON_CR          0x07 /* Clock Rate (MASK) */
+
+#endif
diff --git a/qemu/roms/u-boot/include/pca9698.h b/qemu/roms/u-boot/include/pca9698.h
new file mode 100644
index 000000000..9732be661
--- /dev/null
+++ b/qemu/roms/u-boot/include/pca9698.h
@@ -0,0 +1,18 @@
+/*
+ * (C) Copyright 2011
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __PCA9698_H_
+#define __PCA9698_H_
+
+int pca9698_request(unsigned gpio, const char *label);
+void pca9698_free(unsigned gpio);
+int pca9698_direction_input(u8 addr, unsigned gpio);
+int pca9698_direction_output(u8 addr, unsigned gpio, int value);
+int pca9698_get_value(u8 addr, unsigned gpio);
+int pca9698_set_value(u8 addr, unsigned gpio, int value);
+
+#endif /* __PCA9698_H_ */
diff --git a/qemu/roms/u-boot/include/pci.h b/qemu/roms/u-boot/include/pci.h
new file mode 100644
index 000000000..461f17c05
--- /dev/null
+++ b/qemu/roms/u-boot/include/pci.h
@@ -0,0 +1,674 @@
+/*
+ * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Andreas Heppel <aheppel@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _PCI_H
+#define _PCI_H
+
+/*
+ * Under PCI, each device has 256 bytes of configuration address space,
+ * of which the first 64 bytes are standardized as follows:
+ */
+#define PCI_VENDOR_ID		0x00	/* 16 bits */
+#define PCI_DEVICE_ID		0x02	/* 16 bits */
+#define PCI_COMMAND		0x04	/* 16 bits */
+#define  PCI_COMMAND_IO		0x1	/* Enable response in I/O space */
+#define  PCI_COMMAND_MEMORY	0x2	/* Enable response in Memory space */
+#define  PCI_COMMAND_MASTER	0x4	/* Enable bus mastering */
+#define  PCI_COMMAND_SPECIAL	0x8	/* Enable response to special cycles */
+#define  PCI_COMMAND_INVALIDATE 0x10	/* Use memory write and invalidate */
+#define  PCI_COMMAND_VGA_PALETTE 0x20	/* Enable palette snooping */
+#define  PCI_COMMAND_PARITY	0x40	/* Enable parity checking */
+#define  PCI_COMMAND_WAIT	0x80	/* Enable address/data stepping */
+#define  PCI_COMMAND_SERR	0x100	/* Enable SERR */
+#define  PCI_COMMAND_FAST_BACK	0x200	/* Enable back-to-back writes */
+
+#define PCI_STATUS		0x06	/* 16 bits */
+#define  PCI_STATUS_CAP_LIST	0x10	/* Support Capability List */
+#define  PCI_STATUS_66MHZ	0x20	/* Support 66 Mhz PCI 2.1 bus */
+#define  PCI_STATUS_UDF		0x40	/* Support User Definable Features [obsolete] */
+#define  PCI_STATUS_FAST_BACK	0x80	/* Accept fast-back to back */
+#define  PCI_STATUS_PARITY	0x100	/* Detected parity error */
+#define  PCI_STATUS_DEVSEL_MASK 0x600	/* DEVSEL timing */
+#define  PCI_STATUS_DEVSEL_FAST 0x000
+#define  PCI_STATUS_DEVSEL_MEDIUM 0x200
+#define  PCI_STATUS_DEVSEL_SLOW 0x400
+#define  PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
+#define  PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
+#define  PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
+#define  PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
+#define  PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
+
+#define PCI_CLASS_REVISION	0x08	/* High 24 bits are class, low 8
+					   revision */
+#define PCI_REVISION_ID		0x08	/* Revision ID */
+#define PCI_CLASS_PROG		0x09	/* Reg. Level Programming Interface */
+#define PCI_CLASS_DEVICE	0x0a	/* Device class */
+#define PCI_CLASS_CODE		0x0b	/* Device class code */
+#define  PCI_CLASS_CODE_TOO_OLD	0x00
+#define  PCI_CLASS_CODE_STORAGE 0x01
+#define  PCI_CLASS_CODE_NETWORK 0x02
+#define  PCI_CLASS_CODE_DISPLAY	0x03
+#define  PCI_CLASS_CODE_MULTIMEDIA 0x04
+#define  PCI_CLASS_CODE_MEMORY	0x05
+#define  PCI_CLASS_CODE_BRIDGE	0x06
+#define  PCI_CLASS_CODE_COMM	0x07
+#define  PCI_CLASS_CODE_PERIPHERAL 0x08
+#define  PCI_CLASS_CODE_INPUT	0x09
+#define  PCI_CLASS_CODE_DOCKING	0x0A
+#define  PCI_CLASS_CODE_PROCESSOR 0x0B
+#define  PCI_CLASS_CODE_SERIAL	0x0C
+#define  PCI_CLASS_CODE_WIRELESS 0x0D
+#define  PCI_CLASS_CODE_I2O	0x0E
+#define  PCI_CLASS_CODE_SATELLITE 0x0F
+#define  PCI_CLASS_CODE_CRYPTO	0x10
+#define  PCI_CLASS_CODE_DATA	0x11
+/* Base Class 0x12 - 0xFE is reserved */
+#define  PCI_CLASS_CODE_OTHER	0xFF
+
+#define PCI_CLASS_SUB_CODE	0x0a	/* Device sub-class code */
+#define  PCI_CLASS_SUB_CODE_TOO_OLD_NOTVGA	0x00
+#define  PCI_CLASS_SUB_CODE_TOO_OLD_VGA		0x01
+#define  PCI_CLASS_SUB_CODE_STORAGE_SCSI	0x00
+#define  PCI_CLASS_SUB_CODE_STORAGE_IDE		0x01
+#define  PCI_CLASS_SUB_CODE_STORAGE_FLOPPY	0x02
+#define  PCI_CLASS_SUB_CODE_STORAGE_IPIBUS	0x03
+#define  PCI_CLASS_SUB_CODE_STORAGE_RAID	0x04
+#define  PCI_CLASS_SUB_CODE_STORAGE_ATA		0x05
+#define  PCI_CLASS_SUB_CODE_STORAGE_SATA	0x06
+#define  PCI_CLASS_SUB_CODE_STORAGE_SAS		0x07
+#define  PCI_CLASS_SUB_CODE_STORAGE_OTHER	0x80
+#define  PCI_CLASS_SUB_CODE_NETWORK_ETHERNET	0x00
+#define  PCI_CLASS_SUB_CODE_NETWORK_TOKENRING	0x01
+#define  PCI_CLASS_SUB_CODE_NETWORK_FDDI	0x02
+#define  PCI_CLASS_SUB_CODE_NETWORK_ATM		0x03
+#define  PCI_CLASS_SUB_CODE_NETWORK_ISDN	0x04
+#define  PCI_CLASS_SUB_CODE_NETWORK_WORLDFIP	0x05
+#define  PCI_CLASS_SUB_CODE_NETWORK_PICMG	0x06
+#define  PCI_CLASS_SUB_CODE_NETWORK_OTHER	0x80
+#define  PCI_CLASS_SUB_CODE_DISPLAY_VGA		0x00
+#define  PCI_CLASS_SUB_CODE_DISPLAY_XGA		0x01
+#define  PCI_CLASS_SUB_CODE_DISPLAY_3D		0x02
+#define  PCI_CLASS_SUB_CODE_DISPLAY_OTHER	0x80
+#define  PCI_CLASS_SUB_CODE_MULTIMEDIA_VIDEO	0x00
+#define  PCI_CLASS_SUB_CODE_MULTIMEDIA_AUDIO	0x01
+#define  PCI_CLASS_SUB_CODE_MULTIMEDIA_PHONE	0x02
+#define  PCI_CLASS_SUB_CODE_MULTIMEDIA_OTHER	0x80
+#define  PCI_CLASS_SUB_CODE_MEMORY_RAM		0x00
+#define  PCI_CLASS_SUB_CODE_MEMORY_FLASH	0x01
+#define  PCI_CLASS_SUB_CODE_MEMORY_OTHER	0x80
+#define  PCI_CLASS_SUB_CODE_BRIDGE_HOST		0x00
+#define  PCI_CLASS_SUB_CODE_BRIDGE_ISA		0x01
+#define  PCI_CLASS_SUB_CODE_BRIDGE_EISA		0x02
+#define  PCI_CLASS_SUB_CODE_BRIDGE_MCA		0x03
+#define  PCI_CLASS_SUB_CODE_BRIDGE_PCI		0x04
+#define  PCI_CLASS_SUB_CODE_BRIDGE_PCMCIA	0x05
+#define  PCI_CLASS_SUB_CODE_BRIDGE_NUBUS	0x06
+#define  PCI_CLASS_SUB_CODE_BRIDGE_CARDBUS	0x07
+#define  PCI_CLASS_SUB_CODE_BRIDGE_RACEWAY	0x08
+#define  PCI_CLASS_SUB_CODE_BRIDGE_SEMI_PCI	0x09
+#define  PCI_CLASS_SUB_CODE_BRIDGE_INFINIBAND	0x0A
+#define  PCI_CLASS_SUB_CODE_BRIDGE_OTHER	0x80
+#define  PCI_CLASS_SUB_CODE_COMM_SERIAL		0x00
+#define  PCI_CLASS_SUB_CODE_COMM_PARALLEL	0x01
+#define  PCI_CLASS_SUB_CODE_COMM_MULTIPORT	0x02
+#define  PCI_CLASS_SUB_CODE_COMM_MODEM		0x03
+#define  PCI_CLASS_SUB_CODE_COMM_GPIB		0x04
+#define  PCI_CLASS_SUB_CODE_COMM_SMARTCARD	0x05
+#define  PCI_CLASS_SUB_CODE_COMM_OTHER		0x80
+#define  PCI_CLASS_SUB_CODE_PERIPHERAL_PIC	0x00
+#define  PCI_CLASS_SUB_CODE_PERIPHERAL_DMA	0x01
+#define  PCI_CLASS_SUB_CODE_PERIPHERAL_TIMER	0x02
+#define  PCI_CLASS_SUB_CODE_PERIPHERAL_RTC	0x03
+#define  PCI_CLASS_SUB_CODE_PERIPHERAL_HOTPLUG	0x04
+#define  PCI_CLASS_SUB_CODE_PERIPHERAL_SD	0x05
+#define  PCI_CLASS_SUB_CODE_PERIPHERAL_OTHER	0x80
+#define  PCI_CLASS_SUB_CODE_INPUT_KEYBOARD	0x00
+#define  PCI_CLASS_SUB_CODE_INPUT_DIGITIZER	0x01
+#define  PCI_CLASS_SUB_CODE_INPUT_MOUSE		0x02
+#define  PCI_CLASS_SUB_CODE_INPUT_SCANNER	0x03
+#define  PCI_CLASS_SUB_CODE_INPUT_GAMEPORT	0x04
+#define  PCI_CLASS_SUB_CODE_INPUT_OTHER		0x80
+#define  PCI_CLASS_SUB_CODE_DOCKING_GENERIC	0x00
+#define  PCI_CLASS_SUB_CODE_DOCKING_OTHER	0x80
+#define  PCI_CLASS_SUB_CODE_PROCESSOR_386	0x00
+#define  PCI_CLASS_SUB_CODE_PROCESSOR_486	0x01
+#define  PCI_CLASS_SUB_CODE_PROCESSOR_PENTIUM	0x02
+#define  PCI_CLASS_SUB_CODE_PROCESSOR_ALPHA	0x10
+#define  PCI_CLASS_SUB_CODE_PROCESSOR_POWERPC	0x20
+#define  PCI_CLASS_SUB_CODE_PROCESSOR_MIPS	0x30
+#define  PCI_CLASS_SUB_CODE_PROCESSOR_COPROC	0x40
+#define  PCI_CLASS_SUB_CODE_SERIAL_1394		0x00
+#define  PCI_CLASS_SUB_CODE_SERIAL_ACCESSBUS	0x01
+#define  PCI_CLASS_SUB_CODE_SERIAL_SSA		0x02
+#define  PCI_CLASS_SUB_CODE_SERIAL_USB		0x03
+#define  PCI_CLASS_SUB_CODE_SERIAL_FIBRECHAN	0x04
+#define  PCI_CLASS_SUB_CODE_SERIAL_SMBUS	0x05
+#define  PCI_CLASS_SUB_CODE_SERIAL_INFINIBAND	0x06
+#define  PCI_CLASS_SUB_CODE_SERIAL_IPMI		0x07
+#define  PCI_CLASS_SUB_CODE_SERIAL_SERCOS	0x08
+#define  PCI_CLASS_SUB_CODE_SERIAL_CANBUS	0x09
+#define  PCI_CLASS_SUB_CODE_WIRELESS_IRDA	0x00
+#define  PCI_CLASS_SUB_CODE_WIRELESS_IR		0x01
+#define  PCI_CLASS_SUB_CODE_WIRELESS_RF		0x10
+#define  PCI_CLASS_SUB_CODE_WIRELESS_BLUETOOTH	0x11
+#define  PCI_CLASS_SUB_CODE_WIRELESS_BROADBAND	0x12
+#define  PCI_CLASS_SUB_CODE_WIRELESS_80211A	0x20
+#define  PCI_CLASS_SUB_CODE_WIRELESS_80211B	0x21
+#define  PCI_CLASS_SUB_CODE_WIRELESS_OTHER	0x80
+#define  PCI_CLASS_SUB_CODE_I2O_V1_0		0x00
+#define  PCI_CLASS_SUB_CODE_SATELLITE_TV	0x01
+#define  PCI_CLASS_SUB_CODE_SATELLITE_AUDIO	0x02
+#define  PCI_CLASS_SUB_CODE_SATELLITE_VOICE	0x03
+#define  PCI_CLASS_SUB_CODE_SATELLITE_DATA	0x04
+#define  PCI_CLASS_SUB_CODE_CRYPTO_NETWORK	0x00
+#define  PCI_CLASS_SUB_CODE_CRYPTO_ENTERTAINMENT 0x10
+#define  PCI_CLASS_SUB_CODE_CRYPTO_OTHER	0x80
+#define  PCI_CLASS_SUB_CODE_DATA_DPIO		0x00
+#define  PCI_CLASS_SUB_CODE_DATA_PERFCNTR	0x01
+#define  PCI_CLASS_SUB_CODE_DATA_COMMSYNC	0x10
+#define  PCI_CLASS_SUB_CODE_DATA_MGMT		0x20
+#define  PCI_CLASS_SUB_CODE_DATA_OTHER		0x80
+
+#define PCI_CACHE_LINE_SIZE	0x0c	/* 8 bits */
+#define PCI_LATENCY_TIMER	0x0d	/* 8 bits */
+#define PCI_HEADER_TYPE		0x0e	/* 8 bits */
+#define  PCI_HEADER_TYPE_NORMAL 0
+#define  PCI_HEADER_TYPE_BRIDGE 1
+#define  PCI_HEADER_TYPE_CARDBUS 2
+
+#define PCI_BIST		0x0f	/* 8 bits */
+#define PCI_BIST_CODE_MASK	0x0f	/* Return result */
+#define PCI_BIST_START		0x40	/* 1 to start BIST, 2 secs or less */
+#define PCI_BIST_CAPABLE	0x80	/* 1 if BIST capable */
+
+/*
+ * Base addresses specify locations in memory or I/O space.
+ * Decoded size can be determined by writing a value of
+ * 0xffffffff to the register, and reading it back.  Only
+ * 1 bits are decoded.
+ */
+#define PCI_BASE_ADDRESS_0	0x10	/* 32 bits */
+#define PCI_BASE_ADDRESS_1	0x14	/* 32 bits [htype 0,1 only] */
+#define PCI_BASE_ADDRESS_2	0x18	/* 32 bits [htype 0 only] */
+#define PCI_BASE_ADDRESS_3	0x1c	/* 32 bits */
+#define PCI_BASE_ADDRESS_4	0x20	/* 32 bits */
+#define PCI_BASE_ADDRESS_5	0x24	/* 32 bits */
+#define  PCI_BASE_ADDRESS_SPACE 0x01	/* 0 = memory, 1 = I/O */
+#define  PCI_BASE_ADDRESS_SPACE_IO 0x01
+#define  PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
+#define  PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
+#define  PCI_BASE_ADDRESS_MEM_TYPE_32	0x00	/* 32 bit address */
+#define  PCI_BASE_ADDRESS_MEM_TYPE_1M	0x02	/* Below 1M [obsolete] */
+#define  PCI_BASE_ADDRESS_MEM_TYPE_64	0x04	/* 64 bit address */
+#define  PCI_BASE_ADDRESS_MEM_PREFETCH	0x08	/* prefetchable? */
+#define  PCI_BASE_ADDRESS_MEM_MASK	(~0x0fULL)
+#define  PCI_BASE_ADDRESS_IO_MASK	(~0x03ULL)
+/* bit 1 is reserved if address_space = 1 */
+
+/* Header type 0 (normal devices) */
+#define PCI_CARDBUS_CIS		0x28
+#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
+#define PCI_SUBSYSTEM_ID	0x2e
+#define PCI_ROM_ADDRESS		0x30	/* Bits 31..11 are address, 10..1 reserved */
+#define  PCI_ROM_ADDRESS_ENABLE 0x01
+#define PCI_ROM_ADDRESS_MASK	(~0x7ffULL)
+
+#define PCI_CAPABILITY_LIST	0x34	/* Offset of first capability list entry */
+
+/* 0x35-0x3b are reserved */
+#define PCI_INTERRUPT_LINE	0x3c	/* 8 bits */
+#define PCI_INTERRUPT_PIN	0x3d	/* 8 bits */
+#define PCI_MIN_GNT		0x3e	/* 8 bits */
+#define PCI_MAX_LAT		0x3f	/* 8 bits */
+
+/* Header type 1 (PCI-to-PCI bridges) */
+#define PCI_PRIMARY_BUS		0x18	/* Primary bus number */
+#define PCI_SECONDARY_BUS	0x19	/* Secondary bus number */
+#define PCI_SUBORDINATE_BUS	0x1a	/* Highest bus number behind the bridge */
+#define PCI_SEC_LATENCY_TIMER	0x1b	/* Latency timer for secondary interface */
+#define PCI_IO_BASE		0x1c	/* I/O range behind the bridge */
+#define PCI_IO_LIMIT		0x1d
+#define  PCI_IO_RANGE_TYPE_MASK 0x0f	/* I/O bridging type */
+#define  PCI_IO_RANGE_TYPE_16	0x00
+#define  PCI_IO_RANGE_TYPE_32	0x01
+#define  PCI_IO_RANGE_MASK	~0x0f
+#define PCI_SEC_STATUS		0x1e	/* Secondary status register, only bit 14 used */
+#define PCI_MEMORY_BASE		0x20	/* Memory range behind */
+#define PCI_MEMORY_LIMIT	0x22
+#define  PCI_MEMORY_RANGE_TYPE_MASK 0x0f
+#define  PCI_MEMORY_RANGE_MASK	~0x0f
+#define PCI_PREF_MEMORY_BASE	0x24	/* Prefetchable memory range behind */
+#define PCI_PREF_MEMORY_LIMIT	0x26
+#define  PCI_PREF_RANGE_TYPE_MASK 0x0f
+#define  PCI_PREF_RANGE_TYPE_32 0x00
+#define  PCI_PREF_RANGE_TYPE_64 0x01
+#define  PCI_PREF_RANGE_MASK	~0x0f
+#define PCI_PREF_BASE_UPPER32	0x28	/* Upper half of prefetchable memory range */
+#define PCI_PREF_LIMIT_UPPER32	0x2c
+#define PCI_IO_BASE_UPPER16	0x30	/* Upper half of I/O addresses */
+#define PCI_IO_LIMIT_UPPER16	0x32
+/* 0x34 same as for htype 0 */
+/* 0x35-0x3b is reserved */
+#define PCI_ROM_ADDRESS1	0x38	/* Same as PCI_ROM_ADDRESS, but for htype 1 */
+/* 0x3c-0x3d are same as for htype 0 */
+#define PCI_BRIDGE_CONTROL	0x3e
+#define  PCI_BRIDGE_CTL_PARITY	0x01	/* Enable parity detection on secondary interface */
+#define  PCI_BRIDGE_CTL_SERR	0x02	/* The same for SERR forwarding */
+#define  PCI_BRIDGE_CTL_NO_ISA	0x04	/* Disable bridging of ISA ports */
+#define  PCI_BRIDGE_CTL_VGA	0x08	/* Forward VGA addresses */
+#define  PCI_BRIDGE_CTL_MASTER_ABORT 0x20  /* Report master aborts */
+#define  PCI_BRIDGE_CTL_BUS_RESET 0x40	/* Secondary bus reset */
+#define  PCI_BRIDGE_CTL_FAST_BACK 0x80	/* Fast Back2Back enabled on secondary interface */
+
+/* From 440ep */
+#define PCI_ERREN       0x48     /* Error Enable */
+#define PCI_ERRSTS      0x49     /* Error Status */
+#define PCI_BRDGOPT1    0x4A     /* PCI Bridge Options 1 */
+#define PCI_PLBSESR0    0x4C     /* PCI PLB Slave Error Syndrome 0 */
+#define PCI_PLBSESR1    0x50     /* PCI PLB Slave Error Syndrome 1 */
+#define PCI_PLBSEAR     0x54     /* PCI PLB Slave Error Address */
+#define PCI_CAPID       0x58     /* Capability Identifier */
+#define PCI_NEXTITEMPTR 0x59     /* Next Item Pointer */
+#define PCI_PMC         0x5A     /* Power Management Capabilities */
+#define PCI_PMCSR       0x5C     /* Power Management Control Status */
+#define PCI_PMCSRBSE    0x5E     /* PMCSR PCI to PCI Bridge Support Extensions */
+#define PCI_BRDGOPT2    0x60     /* PCI Bridge Options 2 */
+#define PCI_PMSCRR      0x64     /* Power Management State Change Request Re. */
+
+/* Header type 2 (CardBus bridges) */
+#define PCI_CB_CAPABILITY_LIST	0x14
+/* 0x15 reserved */
+#define PCI_CB_SEC_STATUS	0x16	/* Secondary status */
+#define PCI_CB_PRIMARY_BUS	0x18	/* PCI bus number */
+#define PCI_CB_CARD_BUS		0x19	/* CardBus bus number */
+#define PCI_CB_SUBORDINATE_BUS	0x1a	/* Subordinate bus number */
+#define PCI_CB_LATENCY_TIMER	0x1b	/* CardBus latency timer */
+#define PCI_CB_MEMORY_BASE_0	0x1c
+#define PCI_CB_MEMORY_LIMIT_0	0x20
+#define PCI_CB_MEMORY_BASE_1	0x24
+#define PCI_CB_MEMORY_LIMIT_1	0x28
+#define PCI_CB_IO_BASE_0	0x2c
+#define PCI_CB_IO_BASE_0_HI	0x2e
+#define PCI_CB_IO_LIMIT_0	0x30
+#define PCI_CB_IO_LIMIT_0_HI	0x32
+#define PCI_CB_IO_BASE_1	0x34
+#define PCI_CB_IO_BASE_1_HI	0x36
+#define PCI_CB_IO_LIMIT_1	0x38
+#define PCI_CB_IO_LIMIT_1_HI	0x3a
+#define  PCI_CB_IO_RANGE_MASK	~0x03
+/* 0x3c-0x3d are same as for htype 0 */
+#define PCI_CB_BRIDGE_CONTROL	0x3e
+#define  PCI_CB_BRIDGE_CTL_PARITY	0x01	/* Similar to standard bridge control register */
+#define  PCI_CB_BRIDGE_CTL_SERR		0x02
+#define  PCI_CB_BRIDGE_CTL_ISA		0x04
+#define  PCI_CB_BRIDGE_CTL_VGA		0x08
+#define  PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
+#define  PCI_CB_BRIDGE_CTL_CB_RESET	0x40	/* CardBus reset */
+#define  PCI_CB_BRIDGE_CTL_16BIT_INT	0x80	/* Enable interrupt for 16-bit cards */
+#define  PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100	/* Prefetch enable for both memory regions */
+#define  PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
+#define  PCI_CB_BRIDGE_CTL_POST_WRITES	0x400
+#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
+#define PCI_CB_SUBSYSTEM_ID	0x42
+#define PCI_CB_LEGACY_MODE_BASE 0x44	/* 16-bit PC Card legacy mode base address (ExCa) */
+/* 0x48-0x7f reserved */
+
+/* Capability lists */
+
+#define PCI_CAP_LIST_ID		0	/* Capability ID */
+#define  PCI_CAP_ID_PM		0x01	/* Power Management */
+#define  PCI_CAP_ID_AGP		0x02	/* Accelerated Graphics Port */
+#define  PCI_CAP_ID_VPD		0x03	/* Vital Product Data */
+#define  PCI_CAP_ID_SLOTID	0x04	/* Slot Identification */
+#define  PCI_CAP_ID_MSI		0x05	/* Message Signalled Interrupts */
+#define  PCI_CAP_ID_CHSWP	0x06	/* CompactPCI HotSwap */
+#define  PCI_CAP_ID_EXP 	0x10	/* PCI Express */
+#define PCI_CAP_LIST_NEXT	1	/* Next capability in the list */
+#define PCI_CAP_FLAGS		2	/* Capability defined flags (16 bits) */
+#define PCI_CAP_SIZEOF		4
+
+/* Power Management Registers */
+
+#define  PCI_PM_CAP_VER_MASK	0x0007	/* Version */
+#define  PCI_PM_CAP_PME_CLOCK	0x0008	/* PME clock required */
+#define  PCI_PM_CAP_AUX_POWER	0x0010	/* Auxilliary power support */
+#define  PCI_PM_CAP_DSI		0x0020	/* Device specific initialization */
+#define  PCI_PM_CAP_D1		0x0200	/* D1 power state support */
+#define  PCI_PM_CAP_D2		0x0400	/* D2 power state support */
+#define  PCI_PM_CAP_PME		0x0800	/* PME pin supported */
+#define PCI_PM_CTRL		4	/* PM control and status register */
+#define  PCI_PM_CTRL_STATE_MASK 0x0003	/* Current power state (D0 to D3) */
+#define  PCI_PM_CTRL_PME_ENABLE 0x0100	/* PME pin enable */
+#define  PCI_PM_CTRL_DATA_SEL_MASK	0x1e00	/* Data select (??) */
+#define  PCI_PM_CTRL_DATA_SCALE_MASK	0x6000	/* Data scale (??) */
+#define  PCI_PM_CTRL_PME_STATUS 0x8000	/* PME pin status */
+#define PCI_PM_PPB_EXTENSIONS	6	/* PPB support extensions (??) */
+#define  PCI_PM_PPB_B2_B3	0x40	/* Stop clock when in D3hot (??) */
+#define  PCI_PM_BPCC_ENABLE	0x80	/* Bus power/clock control enable (??) */
+#define PCI_PM_DATA_REGISTER	7	/* (??) */
+#define PCI_PM_SIZEOF		8
+
+/* AGP registers */
+
+#define PCI_AGP_VERSION		2	/* BCD version number */
+#define PCI_AGP_RFU		3	/* Rest of capability flags */
+#define PCI_AGP_STATUS		4	/* Status register */
+#define  PCI_AGP_STATUS_RQ_MASK 0xff000000	/* Maximum number of requests - 1 */
+#define  PCI_AGP_STATUS_SBA	0x0200	/* Sideband addressing supported */
+#define  PCI_AGP_STATUS_64BIT	0x0020	/* 64-bit addressing supported */
+#define  PCI_AGP_STATUS_FW	0x0010	/* FW transfers supported */
+#define  PCI_AGP_STATUS_RATE4	0x0004	/* 4x transfer rate supported */
+#define  PCI_AGP_STATUS_RATE2	0x0002	/* 2x transfer rate supported */
+#define  PCI_AGP_STATUS_RATE1	0x0001	/* 1x transfer rate supported */
+#define PCI_AGP_COMMAND		8	/* Control register */
+#define  PCI_AGP_COMMAND_RQ_MASK 0xff000000  /* Master: Maximum number of requests */
+#define  PCI_AGP_COMMAND_SBA	0x0200	/* Sideband addressing enabled */
+#define  PCI_AGP_COMMAND_AGP	0x0100	/* Allow processing of AGP transactions */
+#define  PCI_AGP_COMMAND_64BIT	0x0020	/* Allow processing of 64-bit addresses */
+#define  PCI_AGP_COMMAND_FW	0x0010	/* Force FW transfers */
+#define  PCI_AGP_COMMAND_RATE4	0x0004	/* Use 4x rate */
+#define  PCI_AGP_COMMAND_RATE2	0x0002	/* Use 4x rate */
+#define  PCI_AGP_COMMAND_RATE1	0x0001	/* Use 4x rate */
+#define PCI_AGP_SIZEOF		12
+
+/* PCI-X registers */
+
+#define  PCI_X_CMD_DPERR_E      0x0001  /* Data Parity Error Recovery Enable */
+#define  PCI_X_CMD_ERO          0x0002  /* Enable Relaxed Ordering */
+#define  PCI_X_CMD_MAX_READ     0x0000  /* Max Memory Read Byte Count */
+#define  PCI_X_CMD_MAX_SPLIT    0x0030  /* Max Outstanding Split Transactions */
+#define  PCI_X_CMD_VERSION(x)   (((x) >> 12) & 3) /* Version */
+
+
+/* Slot Identification */
+
+#define PCI_SID_ESR		2	/* Expansion Slot Register */
+#define  PCI_SID_ESR_NSLOTS	0x1f	/* Number of expansion slots available */
+#define  PCI_SID_ESR_FIC	0x20	/* First In Chassis Flag */
+#define PCI_SID_CHASSIS_NR	3	/* Chassis Number */
+
+/* Message Signalled Interrupts registers */
+
+#define PCI_MSI_FLAGS		2	/* Various flags */
+#define  PCI_MSI_FLAGS_64BIT	0x80	/* 64-bit addresses allowed */
+#define  PCI_MSI_FLAGS_QSIZE	0x70	/* Message queue size configured */
+#define  PCI_MSI_FLAGS_QMASK	0x0e	/* Maximum queue size available */
+#define  PCI_MSI_FLAGS_ENABLE	0x01	/* MSI feature enabled */
+#define PCI_MSI_RFU		3	/* Rest of capability flags */
+#define PCI_MSI_ADDRESS_LO	4	/* Lower 32 bits */
+#define PCI_MSI_ADDRESS_HI	8	/* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
+#define PCI_MSI_DATA_32		8	/* 16 bits of data for 32-bit devices */
+#define PCI_MSI_DATA_64		12	/* 16 bits of data for 64-bit devices */
+
+#define PCI_MAX_PCI_DEVICES	32
+#define PCI_MAX_PCI_FUNCTIONS	8
+
+#define PCI_FIND_CAP_TTL 0x48
+#define CAP_START_POS 0x40
+
+/* Include the ID list */
+
+#include <pci_ids.h>
+
+#ifndef __ASSEMBLY__
+
+#ifdef CONFIG_SYS_PCI_64BIT
+typedef u64 pci_addr_t;
+typedef u64 pci_size_t;
+#else
+typedef u32 pci_addr_t;
+typedef u32 pci_size_t;
+#endif
+
+struct pci_region {
+	pci_addr_t bus_start;	/* Start on the bus */
+	phys_addr_t phys_start;	/* Start in physical address space */
+	pci_size_t size;	/* Size */
+	unsigned long flags;	/* Resource flags */
+
+	pci_addr_t bus_lower;
+};
+
+#define PCI_REGION_MEM		0x00000000	/* PCI memory space */
+#define PCI_REGION_IO		0x00000001	/* PCI IO space */
+#define PCI_REGION_TYPE		0x00000001
+#define PCI_REGION_PREFETCH	0x00000008	/* prefetchable PCI memory */
+
+#define PCI_REGION_SYS_MEMORY	0x00000100	/* System memory */
+#define PCI_REGION_RO		0x00000200	/* Read-only memory */
+
+static inline void pci_set_region(struct pci_region *reg,
+				      pci_addr_t bus_start,
+				      phys_addr_t phys_start,
+				      pci_size_t size,
+				      unsigned long flags) {
+	reg->bus_start	= bus_start;
+	reg->phys_start = phys_start;
+	reg->size	= size;
+	reg->flags	= flags;
+}
+
+typedef int pci_dev_t;
+
+#define PCI_BUS(d)	(((d) >> 16) & 0xff)
+#define PCI_DEV(d)	(((d) >> 11) & 0x1f)
+#define PCI_FUNC(d)	(((d) >> 8) & 0x7)
+#define PCI_BDF(b,d,f)	((b) << 16 | (d) << 11 | (f) << 8)
+
+#define PCI_ANY_ID (~0)
+
+struct pci_device_id {
+	unsigned int vendor, device;		/* Vendor and device ID or PCI_ANY_ID */
+};
+
+struct pci_controller;
+
+struct pci_config_table {
+	unsigned int vendor, device;		/* Vendor and device ID or PCI_ANY_ID */
+	unsigned int class;			/* Class ID, or  PCI_ANY_ID */
+	unsigned int bus;			/* Bus number, or PCI_ANY_ID */
+	unsigned int dev;			/* Device number, or PCI_ANY_ID */
+	unsigned int func;			/* Function number, or PCI_ANY_ID */
+
+	void (*config_device)(struct pci_controller* hose, pci_dev_t dev,
+			      struct pci_config_table *);
+	unsigned long priv[3];
+};
+
+extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev,
+				   struct pci_config_table *);
+extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev,
+				      struct pci_config_table *);
+
+#define MAX_PCI_REGIONS		7
+
+#define INDIRECT_TYPE_NO_PCIE_LINK	1
+
+/*
+ * Structure of a PCI controller (host bridge)
+ */
+struct pci_controller {
+	struct pci_controller *next;
+
+	int first_busno;
+	int last_busno;
+
+	volatile unsigned int *cfg_addr;
+	volatile unsigned char *cfg_data;
+
+	int indirect_type;
+
+	struct pci_region regions[MAX_PCI_REGIONS];
+	int region_count;
+
+	struct pci_config_table *config_table;
+
+	void (*fixup_irq)(struct pci_controller *, pci_dev_t);
+
+	/* Low-level architecture-dependent routines */
+	int (*read_byte)(struct pci_controller*, pci_dev_t, int where, u8 *);
+	int (*read_word)(struct pci_controller*, pci_dev_t, int where, u16 *);
+	int (*read_dword)(struct pci_controller*, pci_dev_t, int where, u32 *);
+	int (*write_byte)(struct pci_controller*, pci_dev_t, int where, u8);
+	int (*write_word)(struct pci_controller*, pci_dev_t, int where, u16);
+	int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32);
+
+	/* Used by auto config */
+	struct pci_region *pci_mem, *pci_io, *pci_prefetch;
+
+	/* Used by ppc405 autoconfig*/
+	struct pci_region *pci_fb;
+	int current_busno;
+
+	void *priv_data;
+};
+
+static inline void pci_set_ops(struct pci_controller *hose,
+				   int (*read_byte)(struct pci_controller*,
+						    pci_dev_t, int where, u8 *),
+				   int (*read_word)(struct pci_controller*,
+						    pci_dev_t, int where, u16 *),
+				   int (*read_dword)(struct pci_controller*,
+						     pci_dev_t, int where, u32 *),
+				   int (*write_byte)(struct pci_controller*,
+						     pci_dev_t, int where, u8),
+				   int (*write_word)(struct pci_controller*,
+						     pci_dev_t, int where, u16),
+				   int (*write_dword)(struct pci_controller*,
+						      pci_dev_t, int where, u32)) {
+	hose->read_byte   = read_byte;
+	hose->read_word   = read_word;
+	hose->read_dword  = read_dword;
+	hose->write_byte  = write_byte;
+	hose->write_word  = write_word;
+	hose->write_dword = write_dword;
+}
+
+#ifdef CONFIG_PCI_INDIRECT_BRIDGE
+extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data);
+#endif
+
+extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
+					pci_addr_t addr, unsigned long flags);
+extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose,
+					phys_addr_t addr, unsigned long flags);
+
+#define pci_phys_to_bus(dev, addr, flags) \
+	pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
+#define pci_bus_to_phys(dev, addr, flags) \
+	pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
+
+#define pci_virt_to_bus(dev, addr, flags) \
+	pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), \
+			     (virt_to_phys(addr)), (flags))
+#define pci_bus_to_virt(dev, addr, flags, len, map_flags) \
+	map_physmem(pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), \
+					 (addr), (flags)), \
+		    (len), (map_flags))
+
+#define pci_phys_to_mem(dev, addr) \
+	pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)
+#define pci_mem_to_phys(dev, addr) \
+	pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)
+#define pci_phys_to_io(dev, addr)  pci_phys_to_bus((dev), (addr), PCI_REGION_IO)
+#define pci_io_to_phys(dev, addr)  pci_bus_to_phys((dev), (addr), PCI_REGION_IO)
+
+#define pci_virt_to_mem(dev, addr) \
+	pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)
+#define pci_mem_to_virt(dev, addr, len, map_flags) \
+	pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags))
+#define pci_virt_to_io(dev, addr) \
+	pci_virt_to_bus((dev), (addr), PCI_REGION_IO)
+#define pci_io_to_virt(dev, addr, len, map_flags) \
+	pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
+
+extern int pci_hose_read_config_byte(struct pci_controller *hose,
+				     pci_dev_t dev, int where, u8 *val);
+extern int pci_hose_read_config_word(struct pci_controller *hose,
+				     pci_dev_t dev, int where, u16 *val);
+extern int pci_hose_read_config_dword(struct pci_controller *hose,
+				      pci_dev_t dev, int where, u32 *val);
+extern int pci_hose_write_config_byte(struct pci_controller *hose,
+				      pci_dev_t dev, int where, u8 val);
+extern int pci_hose_write_config_word(struct pci_controller *hose,
+				      pci_dev_t dev, int where, u16 val);
+extern int pci_hose_write_config_dword(struct pci_controller *hose,
+				       pci_dev_t dev, int where, u32 val);
+
+extern int pci_read_config_byte(pci_dev_t dev, int where, u8 *val);
+extern int pci_read_config_word(pci_dev_t dev, int where, u16 *val);
+extern int pci_read_config_dword(pci_dev_t dev, int where, u32 *val);
+extern int pci_write_config_byte(pci_dev_t dev, int where, u8 val);
+extern int pci_write_config_word(pci_dev_t dev, int where, u16 val);
+extern int pci_write_config_dword(pci_dev_t dev, int where, u32 val);
+
+extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose,
+					       pci_dev_t dev, int where, u8 *val);
+extern int pci_hose_read_config_word_via_dword(struct pci_controller *hose,
+					       pci_dev_t dev, int where, u16 *val);
+extern int pci_hose_write_config_byte_via_dword(struct pci_controller *hose,
+						pci_dev_t dev, int where, u8 val);
+extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose,
+						pci_dev_t dev, int where, u16 val);
+
+extern void *pci_map_bar(pci_dev_t pdev, int bar, int flags);
+extern void pci_register_hose(struct pci_controller* hose);
+extern struct pci_controller* pci_bus_to_hose(int bus);
+extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr);
+
+extern int pci_hose_scan(struct pci_controller *hose);
+extern int pci_hose_scan_bus(struct pci_controller *hose, int bus);
+
+extern void pciauto_region_init(struct pci_region* res);
+extern void pciauto_region_align(struct pci_region *res, pci_size_t size);
+extern int pciauto_region_allocate(struct pci_region* res, pci_size_t size, pci_addr_t *bar);
+extern void pciauto_setup_device(struct pci_controller *hose,
+				 pci_dev_t dev, int bars_num,
+				 struct pci_region *mem,
+				 struct pci_region *prefetch,
+				 struct pci_region *io);
+extern void pciauto_prescan_setup_bridge(struct pci_controller *hose,
+				 pci_dev_t dev, int sub_bus);
+extern void pciauto_postscan_setup_bridge(struct pci_controller *hose,
+				 pci_dev_t dev, int sub_bus);
+extern void pciauto_config_init(struct pci_controller *hose);
+extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
+
+extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index);
+extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index);
+extern pci_dev_t pci_find_class(int wanted_class, int wanted_sub_code,
+				int wanted_prog_if, int index);
+
+extern int pci_hose_config_device(struct pci_controller *hose,
+				  pci_dev_t dev,
+				  unsigned long io,
+				  pci_addr_t mem,
+				  unsigned long command);
+
+extern int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
+				    int cap);
+extern int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
+				   u8 hdr_type);
+extern int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos,
+			int cap);
+
+const char * pci_class_str(u8 class);
+int pci_last_busno(void);
+
+#ifdef CONFIG_MPC824X
+extern void pci_mpc824x_init (struct pci_controller *hose);
+#endif
+
+#ifdef CONFIG_MPC85xx
+extern void pci_mpc85xx_init (struct pci_controller *hose);
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* _PCI_H */
diff --git a/qemu/roms/u-boot/include/pci_gt64120.h b/qemu/roms/u-boot/include/pci_gt64120.h
new file mode 100644
index 000000000..b086024f0
--- /dev/null
+++ b/qemu/roms/u-boot/include/pci_gt64120.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef _PCI_GT64120_H
+#define _PCI_GT64120_H
+
+void gt64120_pci_init(void *regs, unsigned long sys_bus, unsigned long sys_phys,
+		     unsigned long sys_size, unsigned long mem_bus,
+		     unsigned long mem_phys, unsigned long mem_size,
+		     unsigned long io_bus, unsigned long io_phys,
+		     unsigned long io_size);
+
+
+#endif /* _PCI_GT64120_H */
diff --git a/qemu/roms/u-boot/include/pci_ids.h b/qemu/roms/u-boot/include/pci_ids.h
new file mode 100644
index 000000000..6bab67744
--- /dev/null
+++ b/qemu/roms/u-boot/include/pci_ids.h
@@ -0,0 +1,2920 @@
+/*
+ *	PCI Class, Vendor and Device IDs
+ *
+ *	Please keep sorted.
+ *
+ *	Do not add new entries to this file unless the definitions
+ *	are shared between multiple drivers.
+ */
+
+/* Device classes and subclasses */
+
+#define PCI_CLASS_NOT_DEFINED		0x0000
+#define PCI_CLASS_NOT_DEFINED_VGA	0x0001
+
+#define PCI_BASE_CLASS_STORAGE		0x01
+#define PCI_CLASS_STORAGE_SCSI		0x0100
+#define PCI_CLASS_STORAGE_IDE		0x0101
+#define PCI_CLASS_STORAGE_FLOPPY	0x0102
+#define PCI_CLASS_STORAGE_IPI		0x0103
+#define PCI_CLASS_STORAGE_RAID		0x0104
+#define PCI_CLASS_STORAGE_SATA		0x0106
+#define PCI_CLASS_STORAGE_SATA_AHCI	0x010601
+#define PCI_CLASS_STORAGE_SAS		0x0107
+#define PCI_CLASS_STORAGE_OTHER		0x0180
+
+#define PCI_BASE_CLASS_NETWORK		0x02
+#define PCI_CLASS_NETWORK_ETHERNET	0x0200
+#define PCI_CLASS_NETWORK_TOKEN_RING	0x0201
+#define PCI_CLASS_NETWORK_FDDI		0x0202
+#define PCI_CLASS_NETWORK_ATM		0x0203
+#define PCI_CLASS_NETWORK_OTHER		0x0280
+
+#define PCI_BASE_CLASS_DISPLAY		0x03
+#define PCI_CLASS_DISPLAY_VGA		0x0300
+#define PCI_CLASS_DISPLAY_XGA		0x0301
+#define PCI_CLASS_DISPLAY_3D		0x0302
+#define PCI_CLASS_DISPLAY_OTHER		0x0380
+
+#define PCI_BASE_CLASS_MULTIMEDIA	0x04
+#define PCI_CLASS_MULTIMEDIA_VIDEO	0x0400
+#define PCI_CLASS_MULTIMEDIA_AUDIO	0x0401
+#define PCI_CLASS_MULTIMEDIA_PHONE	0x0402
+#define PCI_CLASS_MULTIMEDIA_OTHER	0x0480
+
+#define PCI_BASE_CLASS_MEMORY		0x05
+#define PCI_CLASS_MEMORY_RAM		0x0500
+#define PCI_CLASS_MEMORY_FLASH		0x0501
+#define PCI_CLASS_MEMORY_OTHER		0x0580
+
+#define PCI_BASE_CLASS_BRIDGE		0x06
+#define PCI_CLASS_BRIDGE_HOST		0x0600
+#define PCI_CLASS_BRIDGE_ISA		0x0601
+#define PCI_CLASS_BRIDGE_EISA		0x0602
+#define PCI_CLASS_BRIDGE_MC		0x0603
+#define PCI_CLASS_BRIDGE_PCI		0x0604
+#define PCI_CLASS_BRIDGE_PCMCIA		0x0605
+#define PCI_CLASS_BRIDGE_NUBUS		0x0606
+#define PCI_CLASS_BRIDGE_CARDBUS	0x0607
+#define PCI_CLASS_BRIDGE_RACEWAY	0x0608
+#define PCI_CLASS_BRIDGE_OTHER		0x0680
+
+#define PCI_BASE_CLASS_COMMUNICATION	0x07
+#define PCI_CLASS_COMMUNICATION_SERIAL	0x0700
+#define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701
+#define PCI_CLASS_COMMUNICATION_MULTISERIAL 0x0702
+#define PCI_CLASS_COMMUNICATION_MODEM	0x0703
+#define PCI_CLASS_COMMUNICATION_OTHER	0x0780
+
+#define PCI_BASE_CLASS_SYSTEM		0x08
+#define PCI_CLASS_SYSTEM_PIC		0x0800
+#define PCI_CLASS_SYSTEM_PIC_IOAPIC	0x080010
+#define PCI_CLASS_SYSTEM_PIC_IOXAPIC	0x080020
+#define PCI_CLASS_SYSTEM_DMA		0x0801
+#define PCI_CLASS_SYSTEM_TIMER		0x0802
+#define PCI_CLASS_SYSTEM_RTC		0x0803
+#define PCI_CLASS_SYSTEM_PCI_HOTPLUG	0x0804
+#define PCI_CLASS_SYSTEM_SDHCI		0x0805
+#define PCI_CLASS_SYSTEM_OTHER		0x0880
+
+#define PCI_BASE_CLASS_INPUT		0x09
+#define PCI_CLASS_INPUT_KEYBOARD	0x0900
+#define PCI_CLASS_INPUT_PEN		0x0901
+#define PCI_CLASS_INPUT_MOUSE		0x0902
+#define PCI_CLASS_INPUT_SCANNER		0x0903
+#define PCI_CLASS_INPUT_GAMEPORT	0x0904
+#define PCI_CLASS_INPUT_OTHER		0x0980
+
+#define PCI_BASE_CLASS_DOCKING		0x0a
+#define PCI_CLASS_DOCKING_GENERIC	0x0a00
+#define PCI_CLASS_DOCKING_OTHER		0x0a80
+
+#define PCI_BASE_CLASS_PROCESSOR	0x0b
+#define PCI_CLASS_PROCESSOR_386		0x0b00
+#define PCI_CLASS_PROCESSOR_486		0x0b01
+#define PCI_CLASS_PROCESSOR_PENTIUM	0x0b02
+#define PCI_CLASS_PROCESSOR_ALPHA	0x0b10
+#define PCI_CLASS_PROCESSOR_POWERPC	0x0b20
+#define PCI_CLASS_PROCESSOR_MIPS	0x0b30
+#define PCI_CLASS_PROCESSOR_CO		0x0b40
+
+#define PCI_BASE_CLASS_SERIAL		0x0c
+#define PCI_CLASS_SERIAL_FIREWIRE	0x0c00
+#define PCI_CLASS_SERIAL_FIREWIRE_OHCI	0x0c0010
+#define PCI_CLASS_SERIAL_ACCESS		0x0c01
+#define PCI_CLASS_SERIAL_SSA		0x0c02
+#define PCI_CLASS_SERIAL_USB		0x0c03
+#define PCI_CLASS_SERIAL_USB_UHCI	0x0c0300
+#define PCI_CLASS_SERIAL_USB_OHCI	0x0c0310
+#define PCI_CLASS_SERIAL_USB_EHCI	0x0c0320
+#define PCI_CLASS_SERIAL_USB_XHCI	0x0c0330
+#define PCI_CLASS_SERIAL_FIBER		0x0c04
+#define PCI_CLASS_SERIAL_SMBUS		0x0c05
+
+#define PCI_BASE_CLASS_WIRELESS			0x0d
+#define PCI_CLASS_WIRELESS_RF_CONTROLLER	0x0d10
+#define PCI_CLASS_WIRELESS_WHCI			0x0d1010
+
+#define PCI_BASE_CLASS_INTELLIGENT	0x0e
+#define PCI_CLASS_INTELLIGENT_I2O	0x0e00
+
+#define PCI_BASE_CLASS_SATELLITE	0x0f
+#define PCI_CLASS_SATELLITE_TV		0x0f00
+#define PCI_CLASS_SATELLITE_AUDIO	0x0f01
+#define PCI_CLASS_SATELLITE_VOICE	0x0f03
+#define PCI_CLASS_SATELLITE_DATA	0x0f04
+
+#define PCI_BASE_CLASS_CRYPT		0x10
+#define PCI_CLASS_CRYPT_NETWORK		0x1000
+#define PCI_CLASS_CRYPT_ENTERTAINMENT	0x1001
+#define PCI_CLASS_CRYPT_OTHER		0x1080
+
+#define PCI_BASE_CLASS_SIGNAL_PROCESSING 0x11
+#define PCI_CLASS_SP_DPIO		0x1100
+#define PCI_CLASS_SP_OTHER		0x1180
+
+#define PCI_CLASS_OTHERS		0xff
+
+/* Vendors and devices.  Sort key: vendor first, device next. */
+
+#define PCI_VENDOR_ID_TTTECH		0x0357
+#define PCI_DEVICE_ID_TTTECH_MC322	0x000a
+
+#define PCI_VENDOR_ID_DYNALINK		0x0675
+#define PCI_DEVICE_ID_DYNALINK_IS64PH	0x1702
+
+#define PCI_VENDOR_ID_BERKOM			0x0871
+#define PCI_DEVICE_ID_BERKOM_A1T		0xffa1
+#define PCI_DEVICE_ID_BERKOM_T_CONCEPT		0xffa2
+#define PCI_DEVICE_ID_BERKOM_A4T		0xffa4
+#define PCI_DEVICE_ID_BERKOM_SCITEL_QUADRO	0xffa8
+
+#define PCI_VENDOR_ID_COMPAQ		0x0e11
+#define PCI_DEVICE_ID_COMPAQ_TOKENRING	0x0508
+#define PCI_DEVICE_ID_COMPAQ_TACHYON	0xa0fc
+#define PCI_DEVICE_ID_COMPAQ_SMART2P	0xae10
+#define PCI_DEVICE_ID_COMPAQ_NETEL100	0xae32
+#define PCI_DEVICE_ID_COMPAQ_NETEL10	0xae34
+#define PCI_DEVICE_ID_COMPAQ_TRIFLEX_IDE 0xae33
+#define PCI_DEVICE_ID_COMPAQ_NETFLEX3I	0xae35
+#define PCI_DEVICE_ID_COMPAQ_NETEL100D	0xae40
+#define PCI_DEVICE_ID_COMPAQ_NETEL100PI	0xae43
+#define PCI_DEVICE_ID_COMPAQ_NETEL100I	0xb011
+#define PCI_DEVICE_ID_COMPAQ_CISS	0xb060
+#define PCI_DEVICE_ID_COMPAQ_CISSB	0xb178
+#define PCI_DEVICE_ID_COMPAQ_CISSC	0x46
+#define PCI_DEVICE_ID_COMPAQ_THUNDER	0xf130
+#define PCI_DEVICE_ID_COMPAQ_NETFLEX3B	0xf150
+
+#define PCI_VENDOR_ID_NCR		0x1000
+#define PCI_VENDOR_ID_LSI_LOGIC		0x1000
+#define PCI_DEVICE_ID_NCR_53C810	0x0001
+#define PCI_DEVICE_ID_NCR_53C820	0x0002
+#define PCI_DEVICE_ID_NCR_53C825	0x0003
+#define PCI_DEVICE_ID_NCR_53C815	0x0004
+#define PCI_DEVICE_ID_LSI_53C810AP	0x0005
+#define PCI_DEVICE_ID_NCR_53C860	0x0006
+#define PCI_DEVICE_ID_LSI_53C1510	0x000a
+#define PCI_DEVICE_ID_NCR_53C896	0x000b
+#define PCI_DEVICE_ID_NCR_53C895	0x000c
+#define PCI_DEVICE_ID_NCR_53C885	0x000d
+#define PCI_DEVICE_ID_NCR_53C875	0x000f
+#define PCI_DEVICE_ID_NCR_53C1510	0x0010
+#define PCI_DEVICE_ID_LSI_53C895A	0x0012
+#define PCI_DEVICE_ID_LSI_53C875A	0x0013
+#define PCI_DEVICE_ID_LSI_53C1010_33	0x0020
+#define PCI_DEVICE_ID_LSI_53C1010_66	0x0021
+#define PCI_DEVICE_ID_LSI_53C1030	0x0030
+#define PCI_DEVICE_ID_LSI_1030_53C1035	0x0032
+#define PCI_DEVICE_ID_LSI_53C1035	0x0040
+#define PCI_DEVICE_ID_NCR_53C875J	0x008f
+#define PCI_DEVICE_ID_LSI_FC909		0x0621
+#define PCI_DEVICE_ID_LSI_FC929		0x0622
+#define PCI_DEVICE_ID_LSI_FC929_LAN	0x0623
+#define PCI_DEVICE_ID_LSI_FC919		0x0624
+#define PCI_DEVICE_ID_LSI_FC919_LAN	0x0625
+#define PCI_DEVICE_ID_LSI_FC929X	0x0626
+#define PCI_DEVICE_ID_LSI_FC939X	0x0642
+#define PCI_DEVICE_ID_LSI_FC949X	0x0640
+#define PCI_DEVICE_ID_LSI_FC949ES	0x0646
+#define PCI_DEVICE_ID_LSI_FC919X	0x0628
+#define PCI_DEVICE_ID_NCR_YELLOWFIN	0x0701
+#define PCI_DEVICE_ID_LSI_61C102	0x0901
+#define PCI_DEVICE_ID_LSI_63C815	0x1000
+#define PCI_DEVICE_ID_LSI_SAS1064	0x0050
+#define PCI_DEVICE_ID_LSI_SAS1064R	0x0411
+#define PCI_DEVICE_ID_LSI_SAS1066	0x005E
+#define PCI_DEVICE_ID_LSI_SAS1068	0x0054
+#define PCI_DEVICE_ID_LSI_SAS1064A	0x005C
+#define PCI_DEVICE_ID_LSI_SAS1064E	0x0056
+#define PCI_DEVICE_ID_LSI_SAS1066E	0x005A
+#define PCI_DEVICE_ID_LSI_SAS1068E	0x0058
+#define PCI_DEVICE_ID_LSI_SAS1078	0x0060
+
+#define PCI_VENDOR_ID_ATI		0x1002
+/* Mach64 */
+#define PCI_DEVICE_ID_ATI_68800		0x4158
+#define PCI_DEVICE_ID_ATI_215CT222	0x4354
+#define PCI_DEVICE_ID_ATI_210888CX	0x4358
+#define PCI_DEVICE_ID_ATI_215ET222	0x4554
+/* Mach64 / Rage */
+#define PCI_DEVICE_ID_ATI_215GB		0x4742
+#define PCI_DEVICE_ID_ATI_215GD		0x4744
+#define PCI_DEVICE_ID_ATI_215GI		0x4749
+#define PCI_DEVICE_ID_ATI_215GP		0x4750
+#define PCI_DEVICE_ID_ATI_215GQ		0x4751
+#define PCI_DEVICE_ID_ATI_215XL		0x4752
+#define PCI_DEVICE_ID_ATI_215GT		0x4754
+#define PCI_DEVICE_ID_ATI_215GTB	0x4755
+#define PCI_DEVICE_ID_ATI_215_IV	0x4756
+#define PCI_DEVICE_ID_ATI_215_IW	0x4757
+#define PCI_DEVICE_ID_ATI_215_IZ	0x475A
+#define PCI_DEVICE_ID_ATI_210888GX	0x4758
+#define PCI_DEVICE_ID_ATI_215_LB	0x4c42
+#define PCI_DEVICE_ID_ATI_215_LD	0x4c44
+#define PCI_DEVICE_ID_ATI_215_LG	0x4c47
+#define PCI_DEVICE_ID_ATI_215_LI	0x4c49
+#define PCI_DEVICE_ID_ATI_215_LM	0x4c4D
+#define PCI_DEVICE_ID_ATI_215_LN	0x4c4E
+#define PCI_DEVICE_ID_ATI_215_LR	0x4c52
+#define PCI_DEVICE_ID_ATI_215_LS	0x4c53
+#define PCI_DEVICE_ID_ATI_264_LT	0x4c54
+/* Mach64 VT */
+#define PCI_DEVICE_ID_ATI_264VT		0x5654
+#define PCI_DEVICE_ID_ATI_264VU		0x5655
+#define PCI_DEVICE_ID_ATI_264VV		0x5656
+/* Rage128 GL */
+#define PCI_DEVICE_ID_ATI_RAGE128_RE	0x5245
+#define PCI_DEVICE_ID_ATI_RAGE128_RF	0x5246
+#define PCI_DEVICE_ID_ATI_RAGE128_RG	0x5247
+/* Rage128 VR */
+#define PCI_DEVICE_ID_ATI_RAGE128_RK	0x524b
+#define PCI_DEVICE_ID_ATI_RAGE128_RL	0x524c
+#define PCI_DEVICE_ID_ATI_RAGE128_SE	0x5345
+#define PCI_DEVICE_ID_ATI_RAGE128_SF	0x5346
+#define PCI_DEVICE_ID_ATI_RAGE128_SG	0x5347
+#define PCI_DEVICE_ID_ATI_RAGE128_SH	0x5348
+#define PCI_DEVICE_ID_ATI_RAGE128_SK	0x534b
+#define PCI_DEVICE_ID_ATI_RAGE128_SL	0x534c
+#define PCI_DEVICE_ID_ATI_RAGE128_SM	0x534d
+#define PCI_DEVICE_ID_ATI_RAGE128_SN	0x534e
+/* Rage128 Ultra */
+#define PCI_DEVICE_ID_ATI_RAGE128_TF	0x5446
+#define PCI_DEVICE_ID_ATI_RAGE128_TL	0x544c
+#define PCI_DEVICE_ID_ATI_RAGE128_TR	0x5452
+#define PCI_DEVICE_ID_ATI_RAGE128_TS	0x5453
+#define PCI_DEVICE_ID_ATI_RAGE128_TT	0x5454
+#define PCI_DEVICE_ID_ATI_RAGE128_TU	0x5455
+/* Rage128 M3 */
+#define PCI_DEVICE_ID_ATI_RAGE128_LE	0x4c45
+#define PCI_DEVICE_ID_ATI_RAGE128_LF	0x4c46
+/* Rage128 M4 */
+#define PCI_DEVICE_ID_ATI_RAGE128_MF    0x4d46
+#define PCI_DEVICE_ID_ATI_RAGE128_ML    0x4d4c
+/* Rage128 Pro GL */
+#define PCI_DEVICE_ID_ATI_RAGE128_PA	0x5041
+#define PCI_DEVICE_ID_ATI_RAGE128_PB	0x5042
+#define PCI_DEVICE_ID_ATI_RAGE128_PC	0x5043
+#define PCI_DEVICE_ID_ATI_RAGE128_PD	0x5044
+#define PCI_DEVICE_ID_ATI_RAGE128_PE	0x5045
+#define PCI_DEVICE_ID_ATI_RAGE128_PF	0x5046
+/* Rage128 Pro VR */
+#define PCI_DEVICE_ID_ATI_RAGE128_PG	0x5047
+#define PCI_DEVICE_ID_ATI_RAGE128_PH	0x5048
+#define PCI_DEVICE_ID_ATI_RAGE128_PI	0x5049
+#define PCI_DEVICE_ID_ATI_RAGE128_PJ	0x504A
+#define PCI_DEVICE_ID_ATI_RAGE128_PK	0x504B
+#define PCI_DEVICE_ID_ATI_RAGE128_PL	0x504C
+#define PCI_DEVICE_ID_ATI_RAGE128_PM	0x504D
+#define PCI_DEVICE_ID_ATI_RAGE128_PN	0x504E
+#define PCI_DEVICE_ID_ATI_RAGE128_PO	0x504F
+#define PCI_DEVICE_ID_ATI_RAGE128_PP	0x5050
+#define PCI_DEVICE_ID_ATI_RAGE128_PQ	0x5051
+#define PCI_DEVICE_ID_ATI_RAGE128_PR	0x5052
+#define PCI_DEVICE_ID_ATI_RAGE128_PS	0x5053
+#define PCI_DEVICE_ID_ATI_RAGE128_PT	0x5054
+#define PCI_DEVICE_ID_ATI_RAGE128_PU	0x5055
+#define PCI_DEVICE_ID_ATI_RAGE128_PV	0x5056
+#define PCI_DEVICE_ID_ATI_RAGE128_PW	0x5057
+#define PCI_DEVICE_ID_ATI_RAGE128_PX	0x5058
+/* Rage128 M4 */
+/* Radeon R100 */
+#define PCI_DEVICE_ID_ATI_RADEON_QD	0x5144
+#define PCI_DEVICE_ID_ATI_RADEON_QE	0x5145
+#define PCI_DEVICE_ID_ATI_RADEON_QF	0x5146
+#define PCI_DEVICE_ID_ATI_RADEON_QG	0x5147
+/* Radeon RV100 (VE) */
+#define PCI_DEVICE_ID_ATI_RADEON_QY	0x5159
+#define PCI_DEVICE_ID_ATI_RADEON_QZ	0x515a
+/* Radeon R200 (8500) */
+#define PCI_DEVICE_ID_ATI_RADEON_QL	0x514c
+#define PCI_DEVICE_ID_ATI_RADEON_QN	0x514e
+#define PCI_DEVICE_ID_ATI_RADEON_QO	0x514f
+#define PCI_DEVICE_ID_ATI_RADEON_Ql	0x516c
+#define PCI_DEVICE_ID_ATI_RADEON_BB	0x4242
+/* Radeon R200 (9100) */
+#define PCI_DEVICE_ID_ATI_RADEON_QM	0x514d
+/* Radeon RV200 (7500) */
+#define PCI_DEVICE_ID_ATI_RADEON_QW	0x5157
+#define PCI_DEVICE_ID_ATI_RADEON_QX	0x5158
+/* Radeon NV-100 */
+/* Radeon RV250 (9000) */
+#define PCI_DEVICE_ID_ATI_RADEON_Id	0x4964
+#define PCI_DEVICE_ID_ATI_RADEON_Ie	0x4965
+#define PCI_DEVICE_ID_ATI_RADEON_If	0x4966
+#define PCI_DEVICE_ID_ATI_RADEON_Ig	0x4967
+/* Radeon RV280 (9200) */
+#define PCI_DEVICE_ID_ATI_RADEON_Ya	0x5961
+#define PCI_DEVICE_ID_ATI_RADEON_Yd	0x5964
+/* Radeon R300 (9500) */
+/* Radeon R300 (9700) */
+#define PCI_DEVICE_ID_ATI_RADEON_ND	0x4e44
+#define PCI_DEVICE_ID_ATI_RADEON_NE	0x4e45
+#define PCI_DEVICE_ID_ATI_RADEON_NF	0x4e46
+#define PCI_DEVICE_ID_ATI_RADEON_NG	0x4e47
+/* Radeon R350 (9800) */
+/* Radeon RV350 (9600) */
+/* Radeon M6 */
+#define PCI_DEVICE_ID_ATI_RADEON_LY	0x4c59
+#define PCI_DEVICE_ID_ATI_RADEON_LZ	0x4c5a
+/* Radeon M7 */
+#define PCI_DEVICE_ID_ATI_RADEON_LW	0x4c57
+#define PCI_DEVICE_ID_ATI_RADEON_LX	0x4c58
+/* Radeon M9 */
+#define PCI_DEVICE_ID_ATI_RADEON_Ld	0x4c64
+#define PCI_DEVICE_ID_ATI_RADEON_Le	0x4c65
+#define PCI_DEVICE_ID_ATI_RADEON_Lf	0x4c66
+#define PCI_DEVICE_ID_ATI_RADEON_Lg	0x4c67
+/* Radeon */
+/* RadeonIGP */
+#define PCI_DEVICE_ID_ATI_RS100		0xcab0
+#define PCI_DEVICE_ID_ATI_RS200		0xcab2
+#define PCI_DEVICE_ID_ATI_RS200_B	0xcbb2
+#define PCI_DEVICE_ID_ATI_RS250		0xcab3
+#define PCI_DEVICE_ID_ATI_RS300_100	0x5830
+#define PCI_DEVICE_ID_ATI_RS300_133	0x5831
+#define PCI_DEVICE_ID_ATI_RS300_166	0x5832
+#define PCI_DEVICE_ID_ATI_RS300_200	0x5833
+#define PCI_DEVICE_ID_ATI_RS350_100     0x7830
+#define PCI_DEVICE_ID_ATI_RS350_133     0x7831
+#define PCI_DEVICE_ID_ATI_RS350_166     0x7832
+#define PCI_DEVICE_ID_ATI_RS350_200     0x7833
+#define PCI_DEVICE_ID_ATI_RS400_100     0x5a30
+#define PCI_DEVICE_ID_ATI_RS400_133     0x5a31
+#define PCI_DEVICE_ID_ATI_RS400_166     0x5a32
+#define PCI_DEVICE_ID_ATI_RS400_200     0x5a33
+#define PCI_DEVICE_ID_ATI_RS480         0x5950
+/* additional Radeon families */
+#define PCI_DEVICE_ID_ATI_EVERGREEN     0x9802
+#define PCI_DEVICE_ID_ATI_EVERGREEN2    0x9804
+#define PCI_DEVICE_ID_ATI_WRESTLER      0x9806
+/* ATI IXP Chipset */
+#define PCI_DEVICE_ID_ATI_IXP200_IDE	0x4349
+#define PCI_DEVICE_ID_ATI_IXP200_SMBUS	0x4353
+#define PCI_DEVICE_ID_ATI_IXP300_SMBUS	0x4363
+#define PCI_DEVICE_ID_ATI_IXP300_IDE	0x4369
+#define PCI_DEVICE_ID_ATI_IXP300_SATA   0x436e
+#define PCI_DEVICE_ID_ATI_IXP400_SMBUS	0x4372
+#define PCI_DEVICE_ID_ATI_IXP400_IDE	0x4376
+#define PCI_DEVICE_ID_ATI_IXP400_SATA   0x4379
+#define PCI_DEVICE_ID_ATI_IXP400_SATA2	0x437a
+#define PCI_DEVICE_ID_ATI_IXP600_SATA	0x4380
+#define PCI_DEVICE_ID_ATI_SBX00_PCI_BRIDGE	0x4384
+#define PCI_DEVICE_ID_ATI_SBX00_SMBUS	0x4385
+#define PCI_DEVICE_ID_ATI_IXP600_IDE	0x438c
+#define PCI_DEVICE_ID_ATI_IXP700_SATA	0x4390
+#define PCI_DEVICE_ID_ATI_SBX00_SATA_AHCI	0x4391
+#define PCI_DEVICE_ID_ATI_SBX00_EHCI	0x4396
+#define PCI_DEVICE_ID_ATI_SBX00_OHCI	0x4397
+#define PCI_DEVICE_ID_ATI_IXP700_IDE	0x439c
+
+#define PCI_VENDOR_ID_VLSI		0x1004
+#define PCI_DEVICE_ID_VLSI_82C592	0x0005
+#define PCI_DEVICE_ID_VLSI_82C593	0x0006
+#define PCI_DEVICE_ID_VLSI_82C594	0x0007
+#define PCI_DEVICE_ID_VLSI_82C597	0x0009
+#define PCI_DEVICE_ID_VLSI_82C541	0x000c
+#define PCI_DEVICE_ID_VLSI_82C543	0x000d
+#define PCI_DEVICE_ID_VLSI_82C532	0x0101
+#define PCI_DEVICE_ID_VLSI_82C534	0x0102
+#define PCI_DEVICE_ID_VLSI_82C535	0x0104
+#define PCI_DEVICE_ID_VLSI_82C147	0x0105
+#define PCI_DEVICE_ID_VLSI_VAS96011	0x0702
+
+/* AMD RD890 Chipset */
+#define PCI_DEVICE_ID_RD890_IOMMU	0x5a23
+
+#define PCI_VENDOR_ID_ADL		0x1005
+#define PCI_DEVICE_ID_ADL_2301		0x2301
+
+#define PCI_VENDOR_ID_NS		0x100b
+#define PCI_DEVICE_ID_NS_87415		0x0002
+#define PCI_DEVICE_ID_NS_87560_LIO	0x000e
+#define PCI_DEVICE_ID_NS_87560_USB	0x0012
+#define PCI_DEVICE_ID_NS_83815		0x0020
+#define PCI_DEVICE_ID_NS_83820		0x0022
+#define PCI_DEVICE_ID_NS_CS5535_ISA	0x002b
+#define PCI_DEVICE_ID_NS_CS5535_IDE	0x002d
+#define PCI_DEVICE_ID_NS_CS5535_AUDIO	0x002e
+#define PCI_DEVICE_ID_NS_CS5535_USB	0x002f
+#define PCI_DEVICE_ID_NS_GX_VIDEO	0x0030
+#define PCI_DEVICE_ID_NS_SATURN		0x0035
+#define PCI_DEVICE_ID_NS_SCx200_BRIDGE	0x0500
+#define PCI_DEVICE_ID_NS_SCx200_SMI	0x0501
+#define PCI_DEVICE_ID_NS_SCx200_IDE	0x0502
+#define PCI_DEVICE_ID_NS_SCx200_AUDIO	0x0503
+#define PCI_DEVICE_ID_NS_SCx200_VIDEO	0x0504
+#define PCI_DEVICE_ID_NS_SCx200_XBUS	0x0505
+#define PCI_DEVICE_ID_NS_SC1100_BRIDGE	0x0510
+#define PCI_DEVICE_ID_NS_SC1100_SMI	0x0511
+#define PCI_DEVICE_ID_NS_SC1100_XBUS	0x0515
+#define PCI_DEVICE_ID_NS_87410		0xd001
+
+#define PCI_DEVICE_ID_NS_GX_HOST_BRIDGE  0x0028
+
+#define PCI_VENDOR_ID_TSENG		0x100c
+#define PCI_DEVICE_ID_TSENG_W32P_2	0x3202
+#define PCI_DEVICE_ID_TSENG_W32P_b	0x3205
+#define PCI_DEVICE_ID_TSENG_W32P_c	0x3206
+#define PCI_DEVICE_ID_TSENG_W32P_d	0x3207
+#define PCI_DEVICE_ID_TSENG_ET6000	0x3208
+
+#define PCI_VENDOR_ID_WEITEK		0x100e
+#define PCI_DEVICE_ID_WEITEK_P9000	0x9001
+#define PCI_DEVICE_ID_WEITEK_P9100	0x9100
+
+#define PCI_VENDOR_ID_DEC		0x1011
+#define PCI_DEVICE_ID_DEC_BRD		0x0001
+#define PCI_DEVICE_ID_DEC_TULIP		0x0002
+#define PCI_DEVICE_ID_DEC_TGA		0x0004
+#define PCI_DEVICE_ID_DEC_TULIP_FAST	0x0009
+#define PCI_DEVICE_ID_DEC_TGA2		0x000D
+#define PCI_DEVICE_ID_DEC_FDDI		0x000F
+#define PCI_DEVICE_ID_DEC_TULIP_PLUS	0x0014
+#define PCI_DEVICE_ID_DEC_21142		0x0019
+#define PCI_DEVICE_ID_DEC_21052		0x0021
+#define PCI_DEVICE_ID_DEC_21150		0x0022
+#define PCI_DEVICE_ID_DEC_21152		0x0024
+#define PCI_DEVICE_ID_DEC_21153		0x0025
+#define PCI_DEVICE_ID_DEC_21154		0x0026
+#define PCI_DEVICE_ID_DEC_21285		0x1065
+#define PCI_DEVICE_ID_COMPAQ_42XX	0x0046
+
+#define PCI_VENDOR_ID_CIRRUS		0x1013
+#define PCI_DEVICE_ID_CIRRUS_7548	0x0038
+#define PCI_DEVICE_ID_CIRRUS_5430	0x00a0
+#define PCI_DEVICE_ID_CIRRUS_5434_4	0x00a4
+#define PCI_DEVICE_ID_CIRRUS_5434_8	0x00a8
+#define PCI_DEVICE_ID_CIRRUS_5436	0x00ac
+#define PCI_DEVICE_ID_CIRRUS_5446	0x00b8
+#define PCI_DEVICE_ID_CIRRUS_5480	0x00bc
+#define PCI_DEVICE_ID_CIRRUS_5462	0x00d0
+#define PCI_DEVICE_ID_CIRRUS_5464	0x00d4
+#define PCI_DEVICE_ID_CIRRUS_5465	0x00d6
+#define PCI_DEVICE_ID_CIRRUS_6729	0x1100
+#define PCI_DEVICE_ID_CIRRUS_6832	0x1110
+#define PCI_DEVICE_ID_CIRRUS_7543	0x1202
+#define PCI_DEVICE_ID_CIRRUS_4610	0x6001
+#define PCI_DEVICE_ID_CIRRUS_4612	0x6003
+#define PCI_DEVICE_ID_CIRRUS_4615	0x6004
+
+#define PCI_VENDOR_ID_IBM		0x1014
+#define PCI_DEVICE_ID_IBM_TR		0x0018
+#define PCI_DEVICE_ID_IBM_TR_WAKE	0x003e
+#define PCI_DEVICE_ID_IBM_CPC710_PCI64	0x00fc
+#define PCI_DEVICE_ID_IBM_405GP		0x0156
+#define PCI_DEVICE_ID_IBM_SNIPE		0x0180
+#define PCI_DEVICE_ID_IBM_CITRINE		0x028C
+#define PCI_DEVICE_ID_IBM_GEMSTONE		0xB166
+#define PCI_DEVICE_ID_IBM_OBSIDIAN		0x02BD
+#define PCI_DEVICE_ID_IBM_ICOM_DEV_ID_1	0x0031
+#define PCI_DEVICE_ID_IBM_ICOM_DEV_ID_2	0x0219
+#define PCI_DEVICE_ID_IBM_ICOM_V2_TWO_PORTS_RVX		0x021A
+#define PCI_DEVICE_ID_IBM_ICOM_V2_ONE_PORT_RVX_ONE_PORT_MDM	0x0251
+#define PCI_DEVICE_ID_IBM_ICOM_V2_ONE_PORT_RVX_ONE_PORT_MDM_PCIE 0x0361
+#define PCI_DEVICE_ID_IBM_ICOM_FOUR_PORT_MODEL	0x252
+
+#define PCI_SUBVENDOR_ID_IBM		0x1014
+#define PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT	0x03d4
+
+#define PCI_VENDOR_ID_UNISYS		0x1018
+#define PCI_DEVICE_ID_UNISYS_DMA_DIRECTOR 0x001C
+
+#define PCI_VENDOR_ID_COMPEX2		0x101a /* pci.ids says "AT&T GIS (NCR)" */
+#define PCI_DEVICE_ID_COMPEX2_100VG	0x0005
+
+#define PCI_VENDOR_ID_WD		0x101c
+#define PCI_DEVICE_ID_WD_90C		0xc24a
+
+#define PCI_VENDOR_ID_AMI		0x101e
+#define PCI_DEVICE_ID_AMI_MEGARAID3	0x1960
+#define PCI_DEVICE_ID_AMI_MEGARAID	0x9010
+#define PCI_DEVICE_ID_AMI_MEGARAID2	0x9060
+
+#define PCI_VENDOR_ID_AMD		0x1022
+#define PCI_DEVICE_ID_AMD_K8_NB		0x1100
+#define PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP	0x1101
+#define PCI_DEVICE_ID_AMD_K8_NB_MEMCTL	0x1102
+#define PCI_DEVICE_ID_AMD_K8_NB_MISC	0x1103
+#define PCI_DEVICE_ID_AMD_10H_NB_HT	0x1200
+#define PCI_DEVICE_ID_AMD_10H_NB_MAP	0x1201
+#define PCI_DEVICE_ID_AMD_10H_NB_DRAM	0x1202
+#define PCI_DEVICE_ID_AMD_10H_NB_MISC	0x1203
+#define PCI_DEVICE_ID_AMD_10H_NB_LINK	0x1204
+#define PCI_DEVICE_ID_AMD_11H_NB_HT	0x1300
+#define PCI_DEVICE_ID_AMD_11H_NB_MAP	0x1301
+#define PCI_DEVICE_ID_AMD_11H_NB_DRAM	0x1302
+#define PCI_DEVICE_ID_AMD_11H_NB_MISC	0x1303
+#define PCI_DEVICE_ID_AMD_11H_NB_LINK	0x1304
+#define PCI_DEVICE_ID_AMD_15H_NB_MISC	0x1603
+#define PCI_DEVICE_ID_AMD_CNB17H_F3	0x1703
+#define PCI_DEVICE_ID_AMD_LANCE		0x2000
+#define PCI_DEVICE_ID_AMD_LANCE_HOME	0x2001
+#define PCI_DEVICE_ID_AMD_SCSI		0x2020
+#define PCI_DEVICE_ID_AMD_SERENADE	0x36c0
+#define PCI_DEVICE_ID_AMD_FE_GATE_7006	0x7006
+#define PCI_DEVICE_ID_AMD_FE_GATE_7007	0x7007
+#define PCI_DEVICE_ID_AMD_FE_GATE_700C	0x700C
+#define PCI_DEVICE_ID_AMD_FE_GATE_700E	0x700E
+#define PCI_DEVICE_ID_AMD_COBRA_7401	0x7401
+#define PCI_DEVICE_ID_AMD_VIPER_7409	0x7409
+#define PCI_DEVICE_ID_AMD_VIPER_740B	0x740B
+#define PCI_DEVICE_ID_AMD_VIPER_7410	0x7410
+#define PCI_DEVICE_ID_AMD_VIPER_7411	0x7411
+#define PCI_DEVICE_ID_AMD_VIPER_7413	0x7413
+#define PCI_DEVICE_ID_AMD_VIPER_7440	0x7440
+#define PCI_DEVICE_ID_AMD_OPUS_7441	0x7441
+#define PCI_DEVICE_ID_AMD_OPUS_7443	0x7443
+#define PCI_DEVICE_ID_AMD_VIPER_7443	0x7443
+#define PCI_DEVICE_ID_AMD_OPUS_7445	0x7445
+#define PCI_DEVICE_ID_AMD_8111_PCI	0x7460
+#define PCI_DEVICE_ID_AMD_8111_LPC	0x7468
+#define PCI_DEVICE_ID_AMD_8111_IDE	0x7469
+#define PCI_DEVICE_ID_AMD_8111_SMBUS2	0x746a
+#define PCI_DEVICE_ID_AMD_8111_SMBUS	0x746b
+#define PCI_DEVICE_ID_AMD_8111_AUDIO	0x746d
+#define PCI_DEVICE_ID_AMD_8151_0	0x7454
+#define PCI_DEVICE_ID_AMD_8131_BRIDGE	0x7450
+#define PCI_DEVICE_ID_AMD_8131_APIC	0x7451
+#define PCI_DEVICE_ID_AMD_8132_BRIDGE	0x7458
+#define PCI_DEVICE_ID_AMD_HUDSON2_SMBUS	0x780b
+#define PCI_DEVICE_ID_AMD_CS5535_IDE    0x208F
+#define PCI_DEVICE_ID_AMD_CS5536_ISA    0x2090
+#define PCI_DEVICE_ID_AMD_CS5536_FLASH  0x2091
+#define PCI_DEVICE_ID_AMD_CS5536_AUDIO  0x2093
+#define PCI_DEVICE_ID_AMD_CS5536_OHC    0x2094
+#define PCI_DEVICE_ID_AMD_CS5536_EHC    0x2095
+#define PCI_DEVICE_ID_AMD_CS5536_UDC    0x2096
+#define PCI_DEVICE_ID_AMD_CS5536_UOC    0x2097
+#define PCI_DEVICE_ID_AMD_CS5536_IDE    0x209A
+#define PCI_DEVICE_ID_AMD_LX_VIDEO  0x2081
+#define PCI_DEVICE_ID_AMD_LX_AES    0x2082
+#define PCI_DEVICE_ID_AMD_HUDSON2_IDE		0x780c
+#define PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE	0x7800
+
+#define PCI_VENDOR_ID_TRIDENT		0x1023
+#define PCI_DEVICE_ID_TRIDENT_4DWAVE_DX	0x2000
+#define PCI_DEVICE_ID_TRIDENT_4DWAVE_NX	0x2001
+#define PCI_DEVICE_ID_TRIDENT_9320	0x9320
+#define PCI_DEVICE_ID_TRIDENT_9388	0x9388
+#define PCI_DEVICE_ID_TRIDENT_9397	0x9397
+#define PCI_DEVICE_ID_TRIDENT_939A	0x939A
+#define PCI_DEVICE_ID_TRIDENT_9520	0x9520
+#define PCI_DEVICE_ID_TRIDENT_9525	0x9525
+#define PCI_DEVICE_ID_TRIDENT_9420	0x9420
+#define PCI_DEVICE_ID_TRIDENT_9440	0x9440
+#define PCI_DEVICE_ID_TRIDENT_9660	0x9660
+#define PCI_DEVICE_ID_TRIDENT_9750	0x9750
+#define PCI_DEVICE_ID_TRIDENT_9850	0x9850
+#define PCI_DEVICE_ID_TRIDENT_9880	0x9880
+#define PCI_DEVICE_ID_TRIDENT_8400	0x8400
+#define PCI_DEVICE_ID_TRIDENT_8420	0x8420
+#define PCI_DEVICE_ID_TRIDENT_8500	0x8500
+
+#define PCI_VENDOR_ID_AI		0x1025
+#define PCI_DEVICE_ID_AI_M1435		0x1435
+
+#define PCI_VENDOR_ID_DELL		0x1028
+#define PCI_DEVICE_ID_DELL_RACIII	0x0008
+#define PCI_DEVICE_ID_DELL_RAC4		0x0012
+#define PCI_DEVICE_ID_DELL_PERC5	0x0015
+
+#define PCI_VENDOR_ID_MATROX		0x102B
+#define PCI_DEVICE_ID_MATROX_MGA_2	0x0518
+#define PCI_DEVICE_ID_MATROX_MIL	0x0519
+#define PCI_DEVICE_ID_MATROX_MYS	0x051A
+#define PCI_DEVICE_ID_MATROX_MIL_2	0x051b
+#define PCI_DEVICE_ID_MATROX_MYS_AGP	0x051e
+#define PCI_DEVICE_ID_MATROX_MIL_2_AGP	0x051f
+#define PCI_DEVICE_ID_MATROX_MGA_IMP	0x0d10
+#define PCI_DEVICE_ID_MATROX_G100_MM	0x1000
+#define PCI_DEVICE_ID_MATROX_G100_AGP	0x1001
+#define PCI_DEVICE_ID_MATROX_G200_PCI	0x0520
+#define PCI_DEVICE_ID_MATROX_G200_AGP	0x0521
+#define	PCI_DEVICE_ID_MATROX_G400	0x0525
+#define	PCI_DEVICE_ID_MATROX_G200EV_PCI	0x0530
+#define PCI_DEVICE_ID_MATROX_G550	0x2527
+#define PCI_DEVICE_ID_MATROX_VIA	0x4536
+
+#define PCI_VENDOR_ID_CT		0x102c
+#define PCI_DEVICE_ID_CT_69000		0x00c0
+#define PCI_DEVICE_ID_CT_65545		0x00d8
+#define PCI_DEVICE_ID_CT_65548		0x00dc
+#define PCI_DEVICE_ID_CT_65550		0x00e0
+#define PCI_DEVICE_ID_CT_65554		0x00e4
+#define PCI_DEVICE_ID_CT_65555		0x00e5
+#define PCI_DEVICE_ID_CT_69030		0x0c30
+
+#define PCI_VENDOR_ID_MIRO		0x1031
+#define PCI_DEVICE_ID_MIRO_36050	0x5601
+#define PCI_DEVICE_ID_MIRO_DC10PLUS	0x7efe
+#define PCI_DEVICE_ID_MIRO_DC30PLUS	0xd801
+
+#define PCI_VENDOR_ID_NEC		0x1033
+#define PCI_DEVICE_ID_NEC_CBUS_1	0x0001 /* PCI-Cbus Bridge */
+#define PCI_DEVICE_ID_NEC_LOCAL		0x0002 /* Local Bridge */
+#define PCI_DEVICE_ID_NEC_ATM		0x0003 /* ATM LAN Controller */
+#define PCI_DEVICE_ID_NEC_R4000		0x0004 /* R4000 Bridge */
+#define PCI_DEVICE_ID_NEC_486		0x0005 /* 486 Like Peripheral Bus Bridge */
+#define PCI_DEVICE_ID_NEC_ACCEL_1	0x0006 /* Graphic Accelerator */
+#define PCI_DEVICE_ID_NEC_UXBUS		0x0007 /* UX-Bus Bridge */
+#define PCI_DEVICE_ID_NEC_ACCEL_2	0x0008 /* Graphic Accelerator */
+#define PCI_DEVICE_ID_NEC_GRAPH		0x0009 /* PCI-CoreGraph Bridge */
+#define PCI_DEVICE_ID_NEC_VL		0x0016 /* PCI-VL Bridge */
+#define PCI_DEVICE_ID_NEC_STARALPHA2	0x002c /* STAR ALPHA2 */
+#define PCI_DEVICE_ID_NEC_CBUS_2	0x002d /* PCI-Cbus Bridge */
+#define PCI_DEVICE_ID_NEC_USB		0x0035 /* PCI-USB Host */
+#define PCI_DEVICE_ID_NEC_CBUS_3	0x003b
+#define PCI_DEVICE_ID_NEC_NAPCCARD	0x003e
+#define PCI_DEVICE_ID_NEC_PCX2		0x0046 /* PowerVR */
+#define PCI_DEVICE_ID_NEC_VRC5476       0x009b
+#define PCI_DEVICE_ID_NEC_VRC4173	0x00a5
+#define PCI_DEVICE_ID_NEC_VRC5477_AC97  0x00a6
+#define PCI_DEVICE_ID_NEC_PC9821CS01    0x800c /* PC-9821-CS01 */
+#define PCI_DEVICE_ID_NEC_PC9821NRB06   0x800d /* PC-9821NR-B06 */
+
+#define PCI_VENDOR_ID_FD		0x1036
+#define PCI_DEVICE_ID_FD_36C70		0x0000
+
+#define PCI_VENDOR_ID_SI		0x1039
+#define PCI_DEVICE_ID_SI_5591_AGP	0x0001
+#define PCI_DEVICE_ID_SI_6202		0x0002
+#define PCI_DEVICE_ID_SI_503		0x0008
+#define PCI_DEVICE_ID_SI_ACPI		0x0009
+#define PCI_DEVICE_ID_SI_SMBUS		0x0016
+#define PCI_DEVICE_ID_SI_LPC		0x0018
+#define PCI_DEVICE_ID_SI_5597_VGA	0x0200
+#define PCI_DEVICE_ID_SI_6205		0x0205
+#define PCI_DEVICE_ID_SI_501		0x0406
+#define PCI_DEVICE_ID_SI_496		0x0496
+#define PCI_DEVICE_ID_SI_300		0x0300
+#define PCI_DEVICE_ID_SI_315H		0x0310
+#define PCI_DEVICE_ID_SI_315		0x0315
+#define PCI_DEVICE_ID_SI_315PRO		0x0325
+#define PCI_DEVICE_ID_SI_530		0x0530
+#define PCI_DEVICE_ID_SI_540		0x0540
+#define PCI_DEVICE_ID_SI_550		0x0550
+#define PCI_DEVICE_ID_SI_540_VGA	0x5300
+#define PCI_DEVICE_ID_SI_550_VGA	0x5315
+#define PCI_DEVICE_ID_SI_620		0x0620
+#define PCI_DEVICE_ID_SI_630		0x0630
+#define PCI_DEVICE_ID_SI_633		0x0633
+#define PCI_DEVICE_ID_SI_635		0x0635
+#define PCI_DEVICE_ID_SI_640		0x0640
+#define PCI_DEVICE_ID_SI_645		0x0645
+#define PCI_DEVICE_ID_SI_646		0x0646
+#define PCI_DEVICE_ID_SI_648		0x0648
+#define PCI_DEVICE_ID_SI_650		0x0650
+#define PCI_DEVICE_ID_SI_651		0x0651
+#define PCI_DEVICE_ID_SI_655		0x0655
+#define PCI_DEVICE_ID_SI_661		0x0661
+#define PCI_DEVICE_ID_SI_730		0x0730
+#define PCI_DEVICE_ID_SI_733		0x0733
+#define PCI_DEVICE_ID_SI_630_VGA	0x6300
+#define PCI_DEVICE_ID_SI_735		0x0735
+#define PCI_DEVICE_ID_SI_740		0x0740
+#define PCI_DEVICE_ID_SI_741		0x0741
+#define PCI_DEVICE_ID_SI_745		0x0745
+#define PCI_DEVICE_ID_SI_746		0x0746
+#define PCI_DEVICE_ID_SI_755		0x0755
+#define PCI_DEVICE_ID_SI_760		0x0760
+#define PCI_DEVICE_ID_SI_900		0x0900
+#define PCI_DEVICE_ID_SI_961		0x0961
+#define PCI_DEVICE_ID_SI_962		0x0962
+#define PCI_DEVICE_ID_SI_963		0x0963
+#define PCI_DEVICE_ID_SI_965		0x0965
+#define PCI_DEVICE_ID_SI_966		0x0966
+#define PCI_DEVICE_ID_SI_968		0x0968
+#define PCI_DEVICE_ID_SI_1180		0x1180
+#define PCI_DEVICE_ID_SI_5511		0x5511
+#define PCI_DEVICE_ID_SI_5513		0x5513
+#define PCI_DEVICE_ID_SI_5517		0x5517
+#define PCI_DEVICE_ID_SI_5518		0x5518
+#define PCI_DEVICE_ID_SI_5571		0x5571
+#define PCI_DEVICE_ID_SI_5581		0x5581
+#define PCI_DEVICE_ID_SI_5582		0x5582
+#define PCI_DEVICE_ID_SI_5591		0x5591
+#define PCI_DEVICE_ID_SI_5596		0x5596
+#define PCI_DEVICE_ID_SI_5597		0x5597
+#define PCI_DEVICE_ID_SI_5598		0x5598
+#define PCI_DEVICE_ID_SI_5600		0x5600
+#define PCI_DEVICE_ID_SI_7012		0x7012
+#define PCI_DEVICE_ID_SI_7013		0x7013
+#define PCI_DEVICE_ID_SI_7016		0x7016
+#define PCI_DEVICE_ID_SI_7018		0x7018
+
+#define PCI_VENDOR_ID_HP		0x103c
+#define PCI_DEVICE_ID_HP_VISUALIZE_EG	0x1005
+#define PCI_DEVICE_ID_HP_VISUALIZE_FX6	0x1006
+#define PCI_DEVICE_ID_HP_VISUALIZE_FX4	0x1008
+#define PCI_DEVICE_ID_HP_VISUALIZE_FX2	0x100a
+#define PCI_DEVICE_ID_HP_TACHYON	0x1028
+#define PCI_DEVICE_ID_HP_TACHLITE	0x1029
+#define PCI_DEVICE_ID_HP_J2585A		0x1030
+#define PCI_DEVICE_ID_HP_J2585B		0x1031
+#define PCI_DEVICE_ID_HP_J2973A		0x1040
+#define PCI_DEVICE_ID_HP_J2970A		0x1042
+#define PCI_DEVICE_ID_HP_DIVA		0x1048
+#define PCI_DEVICE_ID_HP_DIVA_TOSCA1	0x1049
+#define PCI_DEVICE_ID_HP_DIVA_TOSCA2	0x104A
+#define PCI_DEVICE_ID_HP_DIVA_MAESTRO	0x104B
+#define PCI_DEVICE_ID_HP_REO_IOC	0x10f1
+#define PCI_DEVICE_ID_HP_VISUALIZE_FXE	0x108b
+#define PCI_DEVICE_ID_HP_DIVA_HALFDOME	0x1223
+#define PCI_DEVICE_ID_HP_DIVA_KEYSTONE	0x1226
+#define PCI_DEVICE_ID_HP_DIVA_POWERBAR	0x1227
+#define PCI_DEVICE_ID_HP_ZX1_IOC	0x122a
+#define PCI_DEVICE_ID_HP_PCIX_LBA	0x122e
+#define PCI_DEVICE_ID_HP_SX1000_IOC	0x127c
+#define PCI_DEVICE_ID_HP_DIVA_EVEREST	0x1282
+#define PCI_DEVICE_ID_HP_DIVA_AUX	0x1290
+#define PCI_DEVICE_ID_HP_DIVA_RMP3	0x1301
+#define PCI_DEVICE_ID_HP_DIVA_HURRICANE	0x132a
+#define PCI_DEVICE_ID_HP_CISSA		0x3220
+#define PCI_DEVICE_ID_HP_CISSC		0x3230
+#define PCI_DEVICE_ID_HP_CISSD		0x3238
+#define PCI_DEVICE_ID_HP_CISSE		0x323a
+#define PCI_DEVICE_ID_HP_CISSF		0x323b
+#define PCI_DEVICE_ID_HP_ZX2_IOC	0x4031
+
+#define PCI_VENDOR_ID_PCTECH		0x1042
+#define PCI_DEVICE_ID_PCTECH_RZ1000	0x1000
+#define PCI_DEVICE_ID_PCTECH_RZ1001	0x1001
+#define PCI_DEVICE_ID_PCTECH_SAMURAI_IDE 0x3020
+
+#define PCI_VENDOR_ID_ASUSTEK		0x1043
+#define PCI_DEVICE_ID_ASUSTEK_0675	0x0675
+
+#define PCI_VENDOR_ID_DPT		0x1044
+#define PCI_DEVICE_ID_DPT		0xa400
+
+#define PCI_VENDOR_ID_OPTI		0x1045
+#define PCI_DEVICE_ID_OPTI_82C558	0xc558
+#define PCI_DEVICE_ID_OPTI_82C621	0xc621
+#define PCI_DEVICE_ID_OPTI_82C700	0xc700
+#define PCI_DEVICE_ID_OPTI_82C825	0xd568
+
+#define PCI_VENDOR_ID_ELSA		0x1048
+#define PCI_DEVICE_ID_ELSA_MICROLINK	0x1000
+#define PCI_DEVICE_ID_ELSA_QS3000	0x3000
+
+#define PCI_VENDOR_ID_STMICRO		0x104A
+
+#define PCI_VENDOR_ID_BUSLOGIC		      0x104B
+#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER_NC 0x0140
+#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER    0x1040
+#define PCI_DEVICE_ID_BUSLOGIC_FLASHPOINT     0x8130
+
+#define PCI_VENDOR_ID_TI		0x104c
+#define PCI_DEVICE_ID_TI_TVP4020	0x3d07
+#define PCI_DEVICE_ID_TI_4450		0x8011
+#define PCI_DEVICE_ID_TI_XX21_XX11	0x8031
+#define PCI_DEVICE_ID_TI_XX21_XX11_FM	0x8033
+#define PCI_DEVICE_ID_TI_XX21_XX11_SD	0x8034
+#define PCI_DEVICE_ID_TI_X515		0x8036
+#define PCI_DEVICE_ID_TI_XX12		0x8039
+#define PCI_DEVICE_ID_TI_XX12_FM	0x803b
+#define PCI_DEVICE_ID_TI_XIO2000A	0x8231
+#define PCI_DEVICE_ID_TI_1130		0xac12
+#define PCI_DEVICE_ID_TI_1031		0xac13
+#define PCI_DEVICE_ID_TI_1131		0xac15
+#define PCI_DEVICE_ID_TI_1250		0xac16
+#define PCI_DEVICE_ID_TI_1220		0xac17
+#define PCI_DEVICE_ID_TI_1221		0xac19
+#define PCI_DEVICE_ID_TI_1210		0xac1a
+#define PCI_DEVICE_ID_TI_1450		0xac1b
+#define PCI_DEVICE_ID_TI_1225		0xac1c
+#define PCI_DEVICE_ID_TI_1251A		0xac1d
+#define PCI_DEVICE_ID_TI_1211		0xac1e
+#define PCI_DEVICE_ID_TI_1251B		0xac1f
+#define PCI_DEVICE_ID_TI_4410		0xac41
+#define PCI_DEVICE_ID_TI_4451		0xac42
+#define PCI_DEVICE_ID_TI_4510		0xac44
+#define PCI_DEVICE_ID_TI_4520		0xac46
+#define PCI_DEVICE_ID_TI_7510		0xac47
+#define PCI_DEVICE_ID_TI_7610		0xac48
+#define PCI_DEVICE_ID_TI_7410		0xac49
+#define PCI_DEVICE_ID_TI_1410		0xac50
+#define PCI_DEVICE_ID_TI_1420		0xac51
+#define PCI_DEVICE_ID_TI_1451A		0xac52
+#define PCI_DEVICE_ID_TI_1620		0xac54
+#define PCI_DEVICE_ID_TI_1520		0xac55
+#define PCI_DEVICE_ID_TI_1510		0xac56
+#define PCI_DEVICE_ID_TI_X620		0xac8d
+#define PCI_DEVICE_ID_TI_X420		0xac8e
+#define PCI_DEVICE_ID_TI_XX20_FM	0xac8f
+
+#define PCI_VENDOR_ID_SONY		0x104d
+
+/* Winbond have two vendor IDs! See 0x10ad as well */
+#define PCI_VENDOR_ID_WINBOND2		0x1050
+#define PCI_DEVICE_ID_WINBOND2_89C940F	0x5a5a
+#define PCI_DEVICE_ID_WINBOND2_6692	0x6692
+
+#define PCI_VENDOR_ID_ANIGMA		0x1051
+#define PCI_DEVICE_ID_ANIGMA_MC145575	0x0100
+
+#define PCI_VENDOR_ID_EFAR		0x1055
+#define PCI_DEVICE_ID_EFAR_SLC90E66_1	0x9130
+#define PCI_DEVICE_ID_EFAR_SLC90E66_3	0x9463
+
+#define PCI_VENDOR_ID_MOTOROLA		0x1057
+#define PCI_DEVICE_ID_MOTOROLA_MPC105	0x0001
+#define PCI_DEVICE_ID_MOTOROLA_MPC106	0x0002
+#define PCI_DEVICE_ID_MOTOROLA_MPC107	0x0004
+#define PCI_DEVICE_ID_MOTOROLA_RAVEN	0x4801
+#define PCI_DEVICE_ID_MOTOROLA_FALCON	0x4802
+#define PCI_DEVICE_ID_MOTOROLA_HAWK	0x4803
+#define PCI_DEVICE_ID_MOTOROLA_HARRIER	0x480b
+#define PCI_DEVICE_ID_MOTOROLA_MPC5200	0x5803
+#define PCI_DEVICE_ID_MOTOROLA_MPC5200B	0x5809
+
+#define PCI_VENDOR_ID_PROMISE		0x105a
+#define PCI_DEVICE_ID_PROMISE_20265	0x0d30
+#define PCI_DEVICE_ID_PROMISE_20267	0x4d30
+#define PCI_DEVICE_ID_PROMISE_20246	0x4d33
+#define PCI_DEVICE_ID_PROMISE_20262	0x4d38
+#define PCI_DEVICE_ID_PROMISE_20263	0x0D38
+#define PCI_DEVICE_ID_PROMISE_20268	0x4d68
+#define PCI_DEVICE_ID_PROMISE_20269	0x4d69
+#define PCI_DEVICE_ID_PROMISE_20270	0x6268
+#define PCI_DEVICE_ID_PROMISE_20271	0x6269
+#define PCI_DEVICE_ID_PROMISE_20275	0x1275
+#define PCI_DEVICE_ID_PROMISE_20276	0x5275
+#define PCI_DEVICE_ID_PROMISE_20277	0x7275
+
+#define PCI_VENDOR_ID_FOXCONN		0x105b
+
+#define PCI_VENDOR_ID_UMC		0x1060
+#define PCI_DEVICE_ID_UMC_UM8673F	0x0101
+#define PCI_DEVICE_ID_UMC_UM8886BF	0x673a
+#define PCI_DEVICE_ID_UMC_UM8886A	0x886a
+
+#define PCI_VENDOR_ID_PICOPOWER		0x1066
+#define PCI_DEVICE_ID_PICOPOWER_PT86C523	0x0002
+#define PCI_DEVICE_ID_PICOPOWER_PT86C523BBP	0x8002
+
+#define PCI_VENDOR_ID_MYLEX		0x1069
+#define PCI_DEVICE_ID_MYLEX_DAC960_P	0x0001
+#define PCI_DEVICE_ID_MYLEX_DAC960_PD	0x0002
+#define PCI_DEVICE_ID_MYLEX_DAC960_PG	0x0010
+#define PCI_DEVICE_ID_MYLEX_DAC960_LA	0x0020
+#define PCI_DEVICE_ID_MYLEX_DAC960_LP	0x0050
+#define PCI_DEVICE_ID_MYLEX_DAC960_BA	0xBA56
+#define PCI_DEVICE_ID_MYLEX_DAC960_GEM	0xB166
+
+#define PCI_VENDOR_ID_APPLE		0x106b
+#define PCI_DEVICE_ID_APPLE_BANDIT	0x0001
+#define PCI_DEVICE_ID_APPLE_HYDRA	0x000e
+#define PCI_DEVICE_ID_APPLE_UNI_N_FW	0x0018
+#define PCI_DEVICE_ID_APPLE_UNI_N_AGP	0x0020
+#define PCI_DEVICE_ID_APPLE_UNI_N_GMAC	0x0021
+#define PCI_DEVICE_ID_APPLE_UNI_N_GMACP	0x0024
+#define PCI_DEVICE_ID_APPLE_UNI_N_AGP_P	0x0027
+#define PCI_DEVICE_ID_APPLE_UNI_N_AGP15	0x002d
+#define PCI_DEVICE_ID_APPLE_UNI_N_PCI15	0x002e
+#define PCI_DEVICE_ID_APPLE_UNI_N_GMAC2	0x0032
+#define PCI_DEVICE_ID_APPLE_UNI_N_ATA	0x0033
+#define PCI_DEVICE_ID_APPLE_UNI_N_AGP2	0x0034
+#define PCI_DEVICE_ID_APPLE_IPID_ATA100	0x003b
+#define PCI_DEVICE_ID_APPLE_K2_ATA100	0x0043
+#define PCI_DEVICE_ID_APPLE_U3_AGP	0x004b
+#define PCI_DEVICE_ID_APPLE_K2_GMAC	0x004c
+#define PCI_DEVICE_ID_APPLE_SH_ATA      0x0050
+#define PCI_DEVICE_ID_APPLE_SH_SUNGEM   0x0051
+#define PCI_DEVICE_ID_APPLE_U3L_AGP	0x0058
+#define PCI_DEVICE_ID_APPLE_U3H_AGP	0x0059
+#define PCI_DEVICE_ID_APPLE_U4_PCIE	0x005b
+#define PCI_DEVICE_ID_APPLE_IPID2_AGP	0x0066
+#define PCI_DEVICE_ID_APPLE_IPID2_ATA	0x0069
+#define PCI_DEVICE_ID_APPLE_IPID2_FW	0x006a
+#define PCI_DEVICE_ID_APPLE_IPID2_GMAC	0x006b
+#define PCI_DEVICE_ID_APPLE_TIGON3	0x1645
+
+#define PCI_VENDOR_ID_YAMAHA		0x1073
+#define PCI_DEVICE_ID_YAMAHA_724	0x0004
+#define PCI_DEVICE_ID_YAMAHA_724F	0x000d
+#define PCI_DEVICE_ID_YAMAHA_740	0x000a
+#define PCI_DEVICE_ID_YAMAHA_740C	0x000c
+#define PCI_DEVICE_ID_YAMAHA_744	0x0010
+#define PCI_DEVICE_ID_YAMAHA_754	0x0012
+
+#define PCI_VENDOR_ID_QLOGIC		0x1077
+#define PCI_DEVICE_ID_QLOGIC_ISP10160	0x1016
+#define PCI_DEVICE_ID_QLOGIC_ISP1020	0x1020
+#define PCI_DEVICE_ID_QLOGIC_ISP1080	0x1080
+#define PCI_DEVICE_ID_QLOGIC_ISP12160	0x1216
+#define PCI_DEVICE_ID_QLOGIC_ISP1240	0x1240
+#define PCI_DEVICE_ID_QLOGIC_ISP1280	0x1280
+#define PCI_DEVICE_ID_QLOGIC_ISP2100	0x2100
+#define PCI_DEVICE_ID_QLOGIC_ISP2200	0x2200
+#define PCI_DEVICE_ID_QLOGIC_ISP2300	0x2300
+#define PCI_DEVICE_ID_QLOGIC_ISP2312	0x2312
+#define PCI_DEVICE_ID_QLOGIC_ISP2322	0x2322
+#define PCI_DEVICE_ID_QLOGIC_ISP6312	0x6312
+#define PCI_DEVICE_ID_QLOGIC_ISP6322	0x6322
+#define PCI_DEVICE_ID_QLOGIC_ISP2422	0x2422
+#define PCI_DEVICE_ID_QLOGIC_ISP2432	0x2432
+#define PCI_DEVICE_ID_QLOGIC_ISP2512	0x2512
+#define PCI_DEVICE_ID_QLOGIC_ISP2522	0x2522
+#define PCI_DEVICE_ID_QLOGIC_ISP5422	0x5422
+#define PCI_DEVICE_ID_QLOGIC_ISP5432	0x5432
+
+#define PCI_VENDOR_ID_CYRIX		0x1078
+#define PCI_DEVICE_ID_CYRIX_5510	0x0000
+#define PCI_DEVICE_ID_CYRIX_PCI_MASTER	0x0001
+#define PCI_DEVICE_ID_CYRIX_5520	0x0002
+#define PCI_DEVICE_ID_CYRIX_5530_LEGACY	0x0100
+#define PCI_DEVICE_ID_CYRIX_5530_IDE	0x0102
+#define PCI_DEVICE_ID_CYRIX_5530_AUDIO	0x0103
+#define PCI_DEVICE_ID_CYRIX_5530_VIDEO	0x0104
+
+#define PCI_VENDOR_ID_CONTAQ		0x1080
+#define PCI_DEVICE_ID_CONTAQ_82C693	0xc693
+
+#define PCI_VENDOR_ID_OLICOM		0x108d
+#define PCI_DEVICE_ID_OLICOM_OC2325	0x0012
+#define PCI_DEVICE_ID_OLICOM_OC2183	0x0013
+#define PCI_DEVICE_ID_OLICOM_OC2326	0x0014
+
+#define PCI_VENDOR_ID_SUN		0x108e
+#define PCI_DEVICE_ID_SUN_EBUS		0x1000
+#define PCI_DEVICE_ID_SUN_HAPPYMEAL	0x1001
+#define PCI_DEVICE_ID_SUN_RIO_EBUS	0x1100
+#define PCI_DEVICE_ID_SUN_RIO_GEM	0x1101
+#define PCI_DEVICE_ID_SUN_RIO_1394	0x1102
+#define PCI_DEVICE_ID_SUN_RIO_USB	0x1103
+#define PCI_DEVICE_ID_SUN_GEM		0x2bad
+#define PCI_DEVICE_ID_SUN_SIMBA		0x5000
+#define PCI_DEVICE_ID_SUN_PBM		0x8000
+#define PCI_DEVICE_ID_SUN_SCHIZO	0x8001
+#define PCI_DEVICE_ID_SUN_SABRE		0xa000
+#define PCI_DEVICE_ID_SUN_HUMMINGBIRD	0xa001
+#define PCI_DEVICE_ID_SUN_TOMATILLO	0xa801
+#define PCI_DEVICE_ID_SUN_CASSINI	0xabba
+
+#define PCI_VENDOR_ID_NI		0x1093
+#define PCI_DEVICE_ID_NI_PCI2322	0xd130
+#define PCI_DEVICE_ID_NI_PCI2324	0xd140
+#define PCI_DEVICE_ID_NI_PCI2328	0xd150
+#define PCI_DEVICE_ID_NI_PXI8422_2322	0xd190
+#define PCI_DEVICE_ID_NI_PXI8422_2324	0xd1a0
+#define PCI_DEVICE_ID_NI_PXI8420_2322	0xd1d0
+#define PCI_DEVICE_ID_NI_PXI8420_2324	0xd1e0
+#define PCI_DEVICE_ID_NI_PXI8420_2328	0xd1f0
+#define PCI_DEVICE_ID_NI_PXI8420_23216	0xd1f1
+#define PCI_DEVICE_ID_NI_PCI2322I	0xd250
+#define PCI_DEVICE_ID_NI_PCI2324I	0xd270
+#define PCI_DEVICE_ID_NI_PCI23216	0xd2b0
+#define PCI_DEVICE_ID_NI_PXI8430_2322	0x7080
+#define PCI_DEVICE_ID_NI_PCI8430_2322	0x70db
+#define PCI_DEVICE_ID_NI_PXI8430_2324	0x70dd
+#define PCI_DEVICE_ID_NI_PCI8430_2324	0x70df
+#define PCI_DEVICE_ID_NI_PXI8430_2328	0x70e2
+#define PCI_DEVICE_ID_NI_PCI8430_2328	0x70e4
+#define PCI_DEVICE_ID_NI_PXI8430_23216	0x70e6
+#define PCI_DEVICE_ID_NI_PCI8430_23216	0x70e7
+#define PCI_DEVICE_ID_NI_PXI8432_2322	0x70e8
+#define PCI_DEVICE_ID_NI_PCI8432_2322	0x70ea
+#define PCI_DEVICE_ID_NI_PXI8432_2324	0x70ec
+#define PCI_DEVICE_ID_NI_PCI8432_2324	0x70ee
+
+#define PCI_VENDOR_ID_CMD		0x1095
+#define PCI_DEVICE_ID_CMD_643		0x0643
+#define PCI_DEVICE_ID_CMD_646		0x0646
+#define PCI_DEVICE_ID_CMD_648		0x0648
+#define PCI_DEVICE_ID_CMD_649		0x0649
+
+#define PCI_VENDOR_ID_SILICONIMAGE	0x1095
+#define PCI_DEVICE_ID_SII_1210SA	0x0240
+#define PCI_DEVICE_ID_SII_680		0x0680
+#define PCI_DEVICE_ID_SII_3112		0x3112
+#define PCI_DEVICE_ID_SIL3124		0x3124
+#define PCI_DEVICE_ID_SIL3131		0x3131
+#define PCI_DEVICE_ID_SIL3132		0x3132
+
+#define PCI_VENDOR_ID_BROOKTREE		0x109e
+#define PCI_DEVICE_ID_BROOKTREE_878	0x0878
+#define PCI_DEVICE_ID_BROOKTREE_879	0x0879
+
+#define PCI_VENDOR_ID_SGI		0x10a9
+#define PCI_DEVICE_ID_SGI_IOC3		0x0003
+#define PCI_DEVICE_ID_SGI_LITHIUM	0x1002
+#define PCI_DEVICE_ID_SGI_IOC4		0x100a
+
+#define PCI_VENDOR_ID_WINBOND		0x10ad
+#define PCI_DEVICE_ID_WINBOND_82C105	0x0105
+#define PCI_DEVICE_ID_WINBOND_83C553	0x0565
+
+#define PCI_VENDOR_ID_PLX		0x10b5
+#define PCI_DEVICE_ID_PLX_R685		0x1030
+#define PCI_DEVICE_ID_PLX_ROMULUS	0x106a
+#define PCI_DEVICE_ID_PLX_SPCOM800	0x1076
+#define PCI_DEVICE_ID_PLX_1077		0x1077
+#define PCI_DEVICE_ID_PLX_SPCOM200	0x1103
+#define PCI_DEVICE_ID_PLX_DJINN_ITOO	0x1151
+#define PCI_DEVICE_ID_PLX_R753		0x1152
+#define PCI_DEVICE_ID_PLX_OLITEC	0x1187
+#define PCI_DEVICE_ID_PLX_PCI200SYN	0x3196
+#define PCI_DEVICE_ID_PLX_9030          0x9030
+#define PCI_DEVICE_ID_PLX_9050		0x9050
+#define PCI_DEVICE_ID_PLX_9056		0x9056
+#define PCI_DEVICE_ID_PLX_9080		0x9080
+#define PCI_DEVICE_ID_PLX_GTEK_SERIAL2	0xa001
+
+#define PCI_VENDOR_ID_MADGE		0x10b6
+#define PCI_DEVICE_ID_MADGE_MK2		0x0002
+
+#define PCI_VENDOR_ID_3COM		0x10b7
+#define PCI_DEVICE_ID_3COM_3C985	0x0001
+#define PCI_DEVICE_ID_3COM_3C940	0x1700
+#define PCI_DEVICE_ID_3COM_3C339	0x3390
+#define PCI_DEVICE_ID_3COM_3C359	0x3590
+#define PCI_DEVICE_ID_3COM_3C940B	0x80eb
+#define PCI_DEVICE_ID_3COM_3CR990	0x9900
+#define PCI_DEVICE_ID_3COM_3CR990_TX_95	0x9902
+#define PCI_DEVICE_ID_3COM_3CR990_TX_97	0x9903
+#define PCI_DEVICE_ID_3COM_3CR990B	0x9904
+#define PCI_DEVICE_ID_3COM_3CR990_FX	0x9905
+#define PCI_DEVICE_ID_3COM_3CR990SVR95	0x9908
+#define PCI_DEVICE_ID_3COM_3CR990SVR97	0x9909
+#define PCI_DEVICE_ID_3COM_3CR990SVR	0x990a
+
+#define PCI_VENDOR_ID_AL		0x10b9
+#define PCI_DEVICE_ID_AL_M1533		0x1533
+#define PCI_DEVICE_ID_AL_M1535		0x1535
+#define PCI_DEVICE_ID_AL_M1541		0x1541
+#define PCI_DEVICE_ID_AL_M1563		0x1563
+#define PCI_DEVICE_ID_AL_M1621		0x1621
+#define PCI_DEVICE_ID_AL_M1631		0x1631
+#define PCI_DEVICE_ID_AL_M1632		0x1632
+#define PCI_DEVICE_ID_AL_M1641		0x1641
+#define PCI_DEVICE_ID_AL_M1644		0x1644
+#define PCI_DEVICE_ID_AL_M1647		0x1647
+#define PCI_DEVICE_ID_AL_M1651		0x1651
+#define PCI_DEVICE_ID_AL_M1671		0x1671
+#define PCI_DEVICE_ID_AL_M1681		0x1681
+#define PCI_DEVICE_ID_AL_M1683		0x1683
+#define PCI_DEVICE_ID_AL_M1689		0x1689
+#define PCI_DEVICE_ID_AL_M5219		0x5219
+#define PCI_DEVICE_ID_AL_M5228		0x5228
+#define PCI_DEVICE_ID_AL_M5229		0x5229
+#define PCI_DEVICE_ID_AL_M5451		0x5451
+#define PCI_DEVICE_ID_AL_M7101		0x7101
+
+#define PCI_VENDOR_ID_NEOMAGIC		0x10c8
+#define PCI_DEVICE_ID_NEOMAGIC_NM256AV_AUDIO 0x8005
+#define PCI_DEVICE_ID_NEOMAGIC_NM256ZX_AUDIO 0x8006
+#define PCI_DEVICE_ID_NEOMAGIC_NM256XL_PLUS_AUDIO 0x8016
+
+#define PCI_VENDOR_ID_TCONRAD		0x10da
+#define PCI_DEVICE_ID_TCONRAD_TOKENRING	0x0508
+
+#define PCI_VENDOR_ID_NVIDIA			0x10de
+#define PCI_DEVICE_ID_NVIDIA_TNT		0x0020
+#define PCI_DEVICE_ID_NVIDIA_TNT2		0x0028
+#define PCI_DEVICE_ID_NVIDIA_UTNT2		0x0029
+#define PCI_DEVICE_ID_NVIDIA_TNT_UNKNOWN        0x002a
+#define PCI_DEVICE_ID_NVIDIA_VTNT2		0x002C
+#define PCI_DEVICE_ID_NVIDIA_UVTNT2		0x002D
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SMBUS	0x0034
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE	0x0035
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA	0x0036
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2	0x003e
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_ULTRA 0x0040
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800       0x0041
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_LE    0x0042
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_GT    0x0045
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_4000     0x004E
+#define PCI_DEVICE_ID_NVIDIA_NFORCE4_SMBUS	0x0052
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE	0x0053
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA	0x0054
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2	0x0055
+#define PCI_DEVICE_ID_NVIDIA_CK804_AUDIO	0x0059
+#define PCI_DEVICE_ID_NVIDIA_CK804_PCIE		0x005d
+#define PCI_DEVICE_ID_NVIDIA_NFORCE2_SMBUS	0x0064
+#define PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE	0x0065
+#define PCI_DEVICE_ID_NVIDIA_MCP2_MODEM		0x0069
+#define PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO		0x006a
+#define PCI_DEVICE_ID_NVIDIA_NFORCE2S_SMBUS	0x0084
+#define PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE	0x0085
+#define PCI_DEVICE_ID_NVIDIA_MCP2S_MODEM	0x0089
+#define PCI_DEVICE_ID_NVIDIA_CK8_AUDIO		0x008a
+#define PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA	0x008e
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_7800_GT   0x0090
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_7800_GTX	0x0091
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_7800   0x0098
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_7800_GTX 0x0099
+#define PCI_DEVICE_ID_NVIDIA_ITNT2		0x00A0
+#define PCI_DEVICE_ID_GEFORCE_6800A             0x00c1
+#define PCI_DEVICE_ID_GEFORCE_6800A_LE          0x00c2
+#define PCI_DEVICE_ID_GEFORCE_GO_6800           0x00c8
+#define PCI_DEVICE_ID_GEFORCE_GO_6800_ULTRA     0x00c9
+#define PCI_DEVICE_ID_QUADRO_FX_GO1400          0x00cc
+#define PCI_DEVICE_ID_QUADRO_FX_1400            0x00ce
+#define PCI_DEVICE_ID_NVIDIA_NFORCE3		0x00d1
+#define PCI_DEVICE_ID_NVIDIA_NFORCE3_SMBUS	0x00d4
+#define PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE	0x00d5
+#define PCI_DEVICE_ID_NVIDIA_MCP3_MODEM		0x00d9
+#define PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO		0x00da
+#define PCI_DEVICE_ID_NVIDIA_NFORCE3S		0x00e1
+#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA	0x00e3
+#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_SMBUS	0x00e4
+#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE	0x00e5
+#define PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO		0x00ea
+#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2	0x00ee
+#define PCIE_DEVICE_ID_NVIDIA_GEFORCE_6800_ALT1 0x00f0
+#define PCIE_DEVICE_ID_NVIDIA_GEFORCE_6600_ALT1 0x00f1
+#define PCIE_DEVICE_ID_NVIDIA_GEFORCE_6600_ALT2 0x00f2
+#define PCIE_DEVICE_ID_NVIDIA_GEFORCE_6200_ALT1 0x00f3
+#define PCIE_DEVICE_ID_NVIDIA_GEFORCE_6800_GT   0x00f9
+#define PCIE_DEVICE_ID_NVIDIA_QUADRO_NVS280	0x00fd
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR	0x0100
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR	0x0101
+#define PCI_DEVICE_ID_NVIDIA_QUADRO		0x0103
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX	0x0110
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2	0x0111
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO	0x0112
+#define PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR	0x0113
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6600_GT	0x0140
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6600	0x0141
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6610_XL	0x0145
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_540	0x014E
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6200	0x014F
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS	0x0150
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2	0x0151
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA	0x0152
+#define PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO	0x0153
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6200_TURBOCACHE 0x0161
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6200    0x0164
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6250    0x0166
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6200_1  0x0167
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6250_1  0x0168
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460	0x0170
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440	0x0171
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420	0x0172
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440_SE	0x0173
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO	0x0174
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO	0x0175
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32 0x0176
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_460_GO    0x0177
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL	0x0178
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64 0x0179
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_200	0x017A
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL	0x017B
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL	0x017C
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_410_GO_M16 0x017D
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440_8X 0x0181
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440SE_8X 0x0182
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420_8X 0x0183
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_4000   0x0185
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_448_GO    0x0186
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_488_GO    0x0187
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_580_XGL    0x0188
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_MAC    0x0189
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_280_NVS    0x018A
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_380_XGL    0x018B
+#define PCI_DEVICE_ID_NVIDIA_IGEFORCE2		0x01a0
+#define PCI_DEVICE_ID_NVIDIA_NFORCE		0x01a4
+#define PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO		0x01b1
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_SMBUS	0x01b4
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_IDE		0x01bc
+#define PCI_DEVICE_ID_NVIDIA_MCP1_MODEM		0x01c1
+#define PCI_DEVICE_ID_NVIDIA_NFORCE2		0x01e0
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE3		0x0200
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE3_1		0x0201
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE3_2		0x0202
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_DDC		0x0203
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B      0x0211
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B_LE   0x0212
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B_GT   0x0215
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600	0x0250
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400	0x0251
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200	0x0253
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL	0x0258
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL	0x0259
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL	0x025B
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SMBUS	0x0264
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE	0x0265
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA	0x0266
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2	0x0267
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SMBUS	0x0368
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE	0x036E
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA	0x037E
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2	0x037F
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800	0x0280
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800_8X    0x0281
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800SE     0x0282
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_4200_GO       0x0286
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_980_XGL        0x0288
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_780_XGL        0x0289
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_700_GOGL       0x028C
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800_ULTRA  0x0301
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800        0x0302
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_2000         0x0308
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1000         0x0309
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600_ULTRA  0x0311
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600        0x0312
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600SE      0x0314
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5600      0x031A
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5650      0x031B
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO700        0x031C
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200        0x0320
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200_ULTRA  0x0321
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200_1      0x0322
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200SE      0x0323
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5200      0x0324
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5250      0x0325
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5500        0x0326
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5100        0x0327
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5250_32   0x0328
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200	    0x0329
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_NVS_280_PCI     0x032A
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_500          0x032B
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5300      0x032C
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5100      0x032D
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900_ULTRA  0x0330
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900        0x0331
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900XT      0x0332
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5950_ULTRA  0x0333
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900ZT      0x0334
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_3000         0x0338
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_700          0x033F
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700_ULTRA  0x0341
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700        0x0342
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700LE      0x0343
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700VE      0x0344
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_1    0x0347
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_2    0x0348
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO1000       0x034C
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1100         0x034E
+#define PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0	    0x0360
+#define PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4	    0x0364
+#define PCI_DEVICE_ID_NVIDIA_NVENET_15              0x0373
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA      0x03E7
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SMBUS	    0x03EB
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE       0x03EC
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA2     0x03F6
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA3     0x03F7
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_SMBUS	    0x0446
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE	    0x0448
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_SMBUS     0x0542
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE       0x0560
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE       0x056C
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP78S_SMBUS    0x0752
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE       0x0759
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_SMBUS     0x07D8
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP79_SMBUS     0x0AA2
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA	    0x0D85
+
+#define PCI_VENDOR_ID_IMS		0x10e0
+#define PCI_DEVICE_ID_IMS_TT128		0x9128
+#define PCI_DEVICE_ID_IMS_TT3D		0x9135
+
+#define PCI_VENDOR_ID_TUNDRA		0x10e3
+#define PCI_DEVICE_ID_TUNDRA_CA91C042	0x0000
+
+#define PCI_VENDOR_ID_INTERG		0x10ea
+#define PCI_DEVICE_ID_INTERG_1682	0x1682
+#define PCI_DEVICE_ID_INTERG_2000	0x2000
+#define PCI_DEVICE_ID_INTERG_2010	0x2010
+#define PCI_DEVICE_ID_INTERG_5000	0x5000
+#define PCI_DEVICE_ID_INTERG_5050	0x5050
+
+#define PCI_VENDOR_ID_REALTEK		0x10ec
+#define PCI_DEVICE_ID_REALTEK_8139	0x8139
+
+#define PCI_VENDOR_ID_XILINX		0x10ee
+#define PCI_DEVICE_ID_RME_DIGI96	0x3fc0
+#define PCI_DEVICE_ID_RME_DIGI96_8	0x3fc1
+#define PCI_DEVICE_ID_RME_DIGI96_8_PRO	0x3fc2
+#define PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST 0x3fc3
+#define PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP 0x3fc5
+#define PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI 0x3fc6
+
+#define PCI_VENDOR_ID_INIT		0x1101
+
+#define PCI_VENDOR_ID_CREATIVE		0x1102 /* duplicate: ECTIVA */
+#define PCI_DEVICE_ID_CREATIVE_EMU10K1	0x0002
+#define PCI_DEVICE_ID_CREATIVE_20K1	0x0005
+#define PCI_DEVICE_ID_CREATIVE_20K2	0x000b
+#define PCI_SUBDEVICE_ID_CREATIVE_SB0760	0x0024
+#define PCI_SUBDEVICE_ID_CREATIVE_SB08801	0x0041
+#define PCI_SUBDEVICE_ID_CREATIVE_SB08802	0x0042
+#define PCI_SUBDEVICE_ID_CREATIVE_SB08803	0x0043
+#define PCI_SUBDEVICE_ID_CREATIVE_HENDRIX	0x6000
+
+#define PCI_VENDOR_ID_ECTIVA		0x1102 /* duplicate: CREATIVE */
+#define PCI_DEVICE_ID_ECTIVA_EV1938	0x8938
+
+#define PCI_VENDOR_ID_TTI		0x1103
+#define PCI_DEVICE_ID_TTI_HPT343	0x0003
+#define PCI_DEVICE_ID_TTI_HPT366	0x0004
+#define PCI_DEVICE_ID_TTI_HPT372	0x0005
+#define PCI_DEVICE_ID_TTI_HPT302	0x0006
+#define PCI_DEVICE_ID_TTI_HPT371	0x0007
+#define PCI_DEVICE_ID_TTI_HPT374	0x0008
+#define PCI_DEVICE_ID_TTI_HPT372N	0x0009	/* apparently a 372N variant? */
+
+#define PCI_VENDOR_ID_VIA		0x1106
+#define PCI_DEVICE_ID_VIA_8763_0	0x0198
+#define PCI_DEVICE_ID_VIA_8380_0	0x0204
+#define PCI_DEVICE_ID_VIA_3238_0	0x0238
+#define PCI_DEVICE_ID_VIA_PT880		0x0258
+#define PCI_DEVICE_ID_VIA_PT880ULTRA	0x0308
+#define PCI_DEVICE_ID_VIA_PX8X0_0	0x0259
+#define PCI_DEVICE_ID_VIA_3269_0	0x0269
+#define PCI_DEVICE_ID_VIA_K8T800PRO_0	0x0282
+#define PCI_DEVICE_ID_VIA_3296_0	0x0296
+#define PCI_DEVICE_ID_VIA_8363_0	0x0305
+#define PCI_DEVICE_ID_VIA_P4M800CE	0x0314
+#define PCI_DEVICE_ID_VIA_P4M890	0x0327
+#define PCI_DEVICE_ID_VIA_VT3324	0x0324
+#define PCI_DEVICE_ID_VIA_VT3336	0x0336
+#define PCI_DEVICE_ID_VIA_VT3351	0x0351
+#define PCI_DEVICE_ID_VIA_VT3364	0x0364
+#define PCI_DEVICE_ID_VIA_8371_0	0x0391
+#define PCI_DEVICE_ID_VIA_6415		0x0415
+#define PCI_DEVICE_ID_VIA_8501_0	0x0501
+#define PCI_DEVICE_ID_VIA_82C561	0x0561
+#define PCI_DEVICE_ID_VIA_82C586_1	0x0571
+#define PCI_DEVICE_ID_VIA_82C576	0x0576
+#define PCI_DEVICE_ID_VIA_82C586_0	0x0586
+#define PCI_DEVICE_ID_VIA_82C596	0x0596
+#define PCI_DEVICE_ID_VIA_82C597_0	0x0597
+#define PCI_DEVICE_ID_VIA_82C598_0	0x0598
+#define PCI_DEVICE_ID_VIA_8601_0	0x0601
+#define PCI_DEVICE_ID_VIA_8605_0	0x0605
+#define PCI_DEVICE_ID_VIA_82C686	0x0686
+#define PCI_DEVICE_ID_VIA_82C691_0	0x0691
+#define PCI_DEVICE_ID_VIA_82C576_1	0x1571
+#define PCI_DEVICE_ID_VIA_82C586_2	0x3038
+#define PCI_DEVICE_ID_VIA_82C586_3	0x3040
+#define PCI_DEVICE_ID_VIA_82C596_3	0x3050
+#define PCI_DEVICE_ID_VIA_82C596B_3	0x3051
+#define PCI_DEVICE_ID_VIA_82C686_4	0x3057
+#define PCI_DEVICE_ID_VIA_82C686_5	0x3058
+#define PCI_DEVICE_ID_VIA_8233_5	0x3059
+#define PCI_DEVICE_ID_VIA_8233_0	0x3074
+#define PCI_DEVICE_ID_VIA_8633_0	0x3091
+#define PCI_DEVICE_ID_VIA_8367_0	0x3099
+#define PCI_DEVICE_ID_VIA_8653_0	0x3101
+#define PCI_DEVICE_ID_VIA_8622		0x3102
+#define PCI_DEVICE_ID_VIA_8235_USB_2	0x3104
+#define PCI_DEVICE_ID_VIA_8233C_0	0x3109
+#define PCI_DEVICE_ID_VIA_8361		0x3112
+#define PCI_DEVICE_ID_VIA_XM266		0x3116
+#define PCI_DEVICE_ID_VIA_612X		0x3119
+#define PCI_DEVICE_ID_VIA_862X_0	0x3123
+#define PCI_DEVICE_ID_VIA_8753_0	0x3128
+#define PCI_DEVICE_ID_VIA_8233A		0x3147
+#define PCI_DEVICE_ID_VIA_8703_51_0	0x3148
+#define PCI_DEVICE_ID_VIA_8237_SATA	0x3149
+#define PCI_DEVICE_ID_VIA_XN266		0x3156
+#define PCI_DEVICE_ID_VIA_6410		0x3164
+#define PCI_DEVICE_ID_VIA_8754C_0	0x3168
+#define PCI_DEVICE_ID_VIA_8235		0x3177
+#define PCI_DEVICE_ID_VIA_8385_0	0x3188
+#define PCI_DEVICE_ID_VIA_8377_0	0x3189
+#define PCI_DEVICE_ID_VIA_8378_0	0x3205
+#define PCI_DEVICE_ID_VIA_8783_0	0x3208
+#define PCI_DEVICE_ID_VIA_8237		0x3227
+#define PCI_DEVICE_ID_VIA_8251		0x3287
+#define PCI_DEVICE_ID_VIA_8261		0x3402
+#define PCI_DEVICE_ID_VIA_8237A		0x3337
+#define PCI_DEVICE_ID_VIA_8237S		0x3372
+#define PCI_DEVICE_ID_VIA_SATA_EIDE	0x5324
+#define PCI_DEVICE_ID_VIA_8231		0x8231
+#define PCI_DEVICE_ID_VIA_8231_4	0x8235
+#define PCI_DEVICE_ID_VIA_8365_1	0x8305
+#define PCI_DEVICE_ID_VIA_CX700		0x8324
+#define PCI_DEVICE_ID_VIA_CX700_IDE	0x0581
+#define PCI_DEVICE_ID_VIA_VX800		0x8353
+#define PCI_DEVICE_ID_VIA_VX855		0x8409
+#define PCI_DEVICE_ID_VIA_8371_1	0x8391
+#define PCI_DEVICE_ID_VIA_82C598_1	0x8598
+#define PCI_DEVICE_ID_VIA_838X_1	0xB188
+#define PCI_DEVICE_ID_VIA_83_87XX_1	0xB198
+#define PCI_DEVICE_ID_VIA_VX855_IDE	0xC409
+#define PCI_DEVICE_ID_VIA_ANON		0xFFFF
+
+#define PCI_VENDOR_ID_SIEMENS           0x110A
+#define PCI_DEVICE_ID_SIEMENS_DSCC4     0x2102
+
+#define PCI_VENDOR_ID_VORTEX		0x1119
+#define PCI_DEVICE_ID_VORTEX_GDT60x0	0x0000
+#define PCI_DEVICE_ID_VORTEX_GDT6000B	0x0001
+#define PCI_DEVICE_ID_VORTEX_GDT6x10	0x0002
+#define PCI_DEVICE_ID_VORTEX_GDT6x20	0x0003
+#define PCI_DEVICE_ID_VORTEX_GDT6530	0x0004
+#define PCI_DEVICE_ID_VORTEX_GDT6550	0x0005
+#define PCI_DEVICE_ID_VORTEX_GDT6x17	0x0006
+#define PCI_DEVICE_ID_VORTEX_GDT6x27	0x0007
+#define PCI_DEVICE_ID_VORTEX_GDT6537	0x0008
+#define PCI_DEVICE_ID_VORTEX_GDT6557	0x0009
+#define PCI_DEVICE_ID_VORTEX_GDT6x15	0x000a
+#define PCI_DEVICE_ID_VORTEX_GDT6x25	0x000b
+#define PCI_DEVICE_ID_VORTEX_GDT6535	0x000c
+#define PCI_DEVICE_ID_VORTEX_GDT6555	0x000d
+#define PCI_DEVICE_ID_VORTEX_GDT6x17RP	0x0100
+#define PCI_DEVICE_ID_VORTEX_GDT6x27RP	0x0101
+#define PCI_DEVICE_ID_VORTEX_GDT6537RP	0x0102
+#define PCI_DEVICE_ID_VORTEX_GDT6557RP	0x0103
+#define PCI_DEVICE_ID_VORTEX_GDT6x11RP	0x0104
+#define PCI_DEVICE_ID_VORTEX_GDT6x21RP	0x0105
+
+#define PCI_VENDOR_ID_EF		0x111a
+#define PCI_DEVICE_ID_EF_ATM_FPGA	0x0000
+#define PCI_DEVICE_ID_EF_ATM_ASIC	0x0002
+#define PCI_DEVICE_ID_EF_ATM_LANAI2	0x0003
+#define PCI_DEVICE_ID_EF_ATM_LANAIHB	0x0005
+
+#define PCI_VENDOR_ID_IDT		0x111d
+#define PCI_DEVICE_ID_IDT_IDT77201	0x0001
+
+#define PCI_VENDOR_ID_FORE		0x1127
+#define PCI_DEVICE_ID_FORE_PCA200E	0x0300
+
+#define PCI_VENDOR_ID_PHILIPS		0x1131
+#define PCI_DEVICE_ID_PHILIPS_SAA7146	0x7146
+#define PCI_DEVICE_ID_PHILIPS_SAA9730	0x9730
+
+#define PCI_VENDOR_ID_EICON		0x1133
+#define PCI_DEVICE_ID_EICON_DIVA20	0xe002
+#define PCI_DEVICE_ID_EICON_DIVA20_U	0xe004
+#define PCI_DEVICE_ID_EICON_DIVA201	0xe005
+#define PCI_DEVICE_ID_EICON_DIVA202	0xe00b
+#define PCI_DEVICE_ID_EICON_MAESTRA	0xe010
+#define PCI_DEVICE_ID_EICON_MAESTRAQ	0xe012
+#define PCI_DEVICE_ID_EICON_MAESTRAQ_U	0xe013
+#define PCI_DEVICE_ID_EICON_MAESTRAP	0xe014
+
+#define PCI_VENDOR_ID_CISCO		0x1137
+
+#define PCI_VENDOR_ID_ZIATECH		0x1138
+#define PCI_DEVICE_ID_ZIATECH_5550_HC	0x5550
+
+
+#define PCI_VENDOR_ID_SYSKONNECT	0x1148
+#define PCI_DEVICE_ID_SYSKONNECT_TR	0x4200
+#define PCI_DEVICE_ID_SYSKONNECT_GE	0x4300
+#define PCI_DEVICE_ID_SYSKONNECT_YU	0x4320
+#define PCI_DEVICE_ID_SYSKONNECT_9DXX	0x4400
+#define PCI_DEVICE_ID_SYSKONNECT_9MXX	0x4500
+
+#define PCI_VENDOR_ID_DIGI		0x114f
+#define PCI_DEVICE_ID_DIGI_DF_M_IOM2_E	0x0070
+#define PCI_DEVICE_ID_DIGI_DF_M_E	0x0071
+#define PCI_DEVICE_ID_DIGI_DF_M_IOM2_A	0x0072
+#define PCI_DEVICE_ID_DIGI_DF_M_A	0x0073
+#define PCI_DEVICE_ID_DIGI_NEO_8	0x00B1
+#define PCI_DEVICE_ID_NEO_2DB9          0x00C8
+#define PCI_DEVICE_ID_NEO_2DB9PRI       0x00C9
+#define PCI_DEVICE_ID_NEO_2RJ45         0x00CA
+#define PCI_DEVICE_ID_NEO_2RJ45PRI      0x00CB
+#define PCIE_DEVICE_ID_NEO_4_IBM        0x00F4
+
+#define PCI_VENDOR_ID_XIRCOM		0x115d
+#define PCI_DEVICE_ID_XIRCOM_RBM56G	0x0101
+#define PCI_DEVICE_ID_XIRCOM_X3201_MDM	0x0103
+
+#define PCI_VENDOR_ID_SERVERWORKS	  0x1166
+#define PCI_DEVICE_ID_SERVERWORKS_HE	  0x0008
+#define PCI_DEVICE_ID_SERVERWORKS_LE	  0x0009
+#define PCI_DEVICE_ID_SERVERWORKS_GCNB_LE 0x0017
+#define PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB	0x0036
+#define PCI_DEVICE_ID_SERVERWORKS_EPB	  0x0103
+#define PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE	0x0132
+#define PCI_DEVICE_ID_SERVERWORKS_OSB4	  0x0200
+#define PCI_DEVICE_ID_SERVERWORKS_CSB5	  0x0201
+#define PCI_DEVICE_ID_SERVERWORKS_CSB6    0x0203
+#define PCI_DEVICE_ID_SERVERWORKS_HT1000SB 0x0205
+#define PCI_DEVICE_ID_SERVERWORKS_OSB4IDE 0x0211
+#define PCI_DEVICE_ID_SERVERWORKS_CSB5IDE 0x0212
+#define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE 0x0213
+#define PCI_DEVICE_ID_SERVERWORKS_HT1000IDE 0x0214
+#define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2 0x0217
+#define PCI_DEVICE_ID_SERVERWORKS_CSB6LPC 0x0227
+#define PCI_DEVICE_ID_SERVERWORKS_HT1100LD 0x0408
+
+#define PCI_VENDOR_ID_SBE		0x1176
+#define PCI_DEVICE_ID_SBE_WANXL100	0x0301
+#define PCI_DEVICE_ID_SBE_WANXL200	0x0302
+#define PCI_DEVICE_ID_SBE_WANXL400	0x0104
+#define PCI_SUBDEVICE_ID_SBE_T3E3	0x0009
+#define PCI_SUBDEVICE_ID_SBE_2T3E3_P0	0x0901
+#define PCI_SUBDEVICE_ID_SBE_2T3E3_P1	0x0902
+
+#define PCI_VENDOR_ID_TOSHIBA		0x1179
+#define PCI_DEVICE_ID_TOSHIBA_PICCOLO_1	0x0101
+#define PCI_DEVICE_ID_TOSHIBA_PICCOLO_2	0x0102
+#define PCI_DEVICE_ID_TOSHIBA_PICCOLO_3	0x0103
+#define PCI_DEVICE_ID_TOSHIBA_PICCOLO_5	0x0105
+#define PCI_DEVICE_ID_TOSHIBA_TOPIC95	0x060a
+#define PCI_DEVICE_ID_TOSHIBA_TOPIC97	0x060f
+#define PCI_DEVICE_ID_TOSHIBA_TOPIC100	0x0617
+
+#define PCI_VENDOR_ID_TOSHIBA_2		0x102f
+#define PCI_DEVICE_ID_TOSHIBA_TC35815CF	0x0030
+#define PCI_DEVICE_ID_TOSHIBA_TC35815_NWU	0x0031
+#define PCI_DEVICE_ID_TOSHIBA_TC35815_TX4939	0x0032
+#define PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE	0x0105
+#define PCI_DEVICE_ID_TOSHIBA_TC86C001_MISC	0x0108
+#define PCI_DEVICE_ID_TOSHIBA_SPIDER_NET 0x01b3
+
+#define PCI_VENDOR_ID_ATTO		0x117c
+
+#define PCI_VENDOR_ID_RICOH		0x1180
+#define PCI_DEVICE_ID_RICOH_RL5C465	0x0465
+#define PCI_DEVICE_ID_RICOH_RL5C466	0x0466
+#define PCI_DEVICE_ID_RICOH_RL5C475	0x0475
+#define PCI_DEVICE_ID_RICOH_RL5C476	0x0476
+#define PCI_DEVICE_ID_RICOH_RL5C478	0x0478
+#define PCI_DEVICE_ID_RICOH_R5C822	0x0822
+#define PCI_DEVICE_ID_RICOH_R5C832	0x0832
+#define PCI_DEVICE_ID_RICOH_R5C843	0x0843
+
+#define PCI_VENDOR_ID_DLINK		0x1186
+#define PCI_DEVICE_ID_DLINK_8139	0x1300
+#define PCI_DEVICE_ID_DLINK_DGE510T	0x4c00
+
+#define PCI_VENDOR_ID_ARTOP		0x1191
+#define PCI_DEVICE_ID_ARTOP_ATP850UF	0x0005
+#define PCI_DEVICE_ID_ARTOP_ATP860	0x0006
+#define PCI_DEVICE_ID_ARTOP_ATP860R	0x0007
+#define PCI_DEVICE_ID_ARTOP_ATP865	0x0008
+#define PCI_DEVICE_ID_ARTOP_ATP865R	0x0009
+#define PCI_DEVICE_ID_ARTOP_ATP867A	0x000A
+#define PCI_DEVICE_ID_ARTOP_ATP867B	0x000B
+#define PCI_DEVICE_ID_ARTOP_AEC7610	0x8002
+#define PCI_DEVICE_ID_ARTOP_AEC7612UW	0x8010
+#define PCI_DEVICE_ID_ARTOP_AEC7612U	0x8020
+#define PCI_DEVICE_ID_ARTOP_AEC7612S	0x8030
+#define PCI_DEVICE_ID_ARTOP_AEC7612D	0x8040
+#define PCI_DEVICE_ID_ARTOP_AEC7612SUW	0x8050
+#define PCI_DEVICE_ID_ARTOP_8060	0x8060
+
+#define PCI_VENDOR_ID_ZEITNET		0x1193
+#define PCI_DEVICE_ID_ZEITNET_1221	0x0001
+#define PCI_DEVICE_ID_ZEITNET_1225	0x0002
+
+#define PCI_VENDOR_ID_FUJITSU_ME	0x119e
+#define PCI_DEVICE_ID_FUJITSU_FS155	0x0001
+#define PCI_DEVICE_ID_FUJITSU_FS50	0x0003
+
+#define PCI_SUBVENDOR_ID_KEYSPAN	0x11a9
+#define PCI_SUBDEVICE_ID_KEYSPAN_SX2	0x5334
+
+#define PCI_VENDOR_ID_MARVELL		0x11ab
+#define PCI_DEVICE_ID_MARVELL_GT64111	0x4146
+#define PCI_DEVICE_ID_MARVELL_GT64260	0x6430
+#define PCI_DEVICE_ID_MARVELL_MV64360	0x6460
+#define PCI_DEVICE_ID_MARVELL_MV64460	0x6480
+#define PCI_DEVICE_ID_MARVELL_88ALP01_NAND	0x4100
+#define PCI_DEVICE_ID_MARVELL_88ALP01_SD	0x4101
+#define PCI_DEVICE_ID_MARVELL_88ALP01_CCIC	0x4102
+
+#define PCI_VENDOR_ID_V3		0x11b0
+#define PCI_DEVICE_ID_V3_V960		0x0001
+#define PCI_DEVICE_ID_V3_V351		0x0002
+
+#define PCI_VENDOR_ID_ATT		0x11c1
+#define PCI_DEVICE_ID_ATT_VENUS_MODEM	0x480
+
+#define PCI_VENDOR_ID_SPECIALIX		0x11cb
+#define PCI_DEVICE_ID_SPECIALIX_IO8	0x2000
+#define PCI_DEVICE_ID_SPECIALIX_RIO	0x8000
+#define PCI_SUBDEVICE_ID_SPECIALIX_SPEED4 0xa004
+
+#define PCI_VENDOR_ID_ANALOG_DEVICES	0x11d4
+#define PCI_DEVICE_ID_AD1889JS		0x1889
+
+#define PCI_DEVICE_ID_SEGA_BBA		0x1234
+
+#define PCI_VENDOR_ID_ZORAN		0x11de
+#define PCI_DEVICE_ID_ZORAN_36057	0x6057
+#define PCI_DEVICE_ID_ZORAN_36120	0x6120
+
+#define PCI_VENDOR_ID_COMPEX		0x11f6
+#define PCI_DEVICE_ID_COMPEX_ENET100VG4	0x0112
+
+#define PCI_VENDOR_ID_PMC_Sierra	0x11f8
+
+#define PCI_VENDOR_ID_RP		0x11fe
+#define PCI_DEVICE_ID_RP32INTF		0x0001
+#define PCI_DEVICE_ID_RP8INTF		0x0002
+#define PCI_DEVICE_ID_RP16INTF		0x0003
+#define PCI_DEVICE_ID_RP4QUAD		0x0004
+#define PCI_DEVICE_ID_RP8OCTA		0x0005
+#define PCI_DEVICE_ID_RP8J		0x0006
+#define PCI_DEVICE_ID_RP4J		0x0007
+#define PCI_DEVICE_ID_RP8SNI		0x0008
+#define PCI_DEVICE_ID_RP16SNI		0x0009
+#define PCI_DEVICE_ID_RPP4		0x000A
+#define PCI_DEVICE_ID_RPP8		0x000B
+#define PCI_DEVICE_ID_RP4M		0x000D
+#define PCI_DEVICE_ID_RP2_232		0x000E
+#define PCI_DEVICE_ID_RP2_422		0x000F
+#define PCI_DEVICE_ID_URP32INTF		0x0801
+#define PCI_DEVICE_ID_URP8INTF		0x0802
+#define PCI_DEVICE_ID_URP16INTF		0x0803
+#define PCI_DEVICE_ID_URP8OCTA		0x0805
+#define PCI_DEVICE_ID_UPCI_RM3_8PORT	0x080C
+#define PCI_DEVICE_ID_UPCI_RM3_4PORT	0x080D
+#define PCI_DEVICE_ID_CRP16INTF		0x0903
+
+#define PCI_VENDOR_ID_CYCLADES		0x120e
+#define PCI_DEVICE_ID_CYCLOM_Y_Lo	0x0100
+#define PCI_DEVICE_ID_CYCLOM_Y_Hi	0x0101
+#define PCI_DEVICE_ID_CYCLOM_4Y_Lo	0x0102
+#define PCI_DEVICE_ID_CYCLOM_4Y_Hi	0x0103
+#define PCI_DEVICE_ID_CYCLOM_8Y_Lo	0x0104
+#define PCI_DEVICE_ID_CYCLOM_8Y_Hi	0x0105
+#define PCI_DEVICE_ID_CYCLOM_Z_Lo	0x0200
+#define PCI_DEVICE_ID_CYCLOM_Z_Hi	0x0201
+#define PCI_DEVICE_ID_PC300_RX_2	0x0300
+#define PCI_DEVICE_ID_PC300_RX_1	0x0301
+#define PCI_DEVICE_ID_PC300_TE_2	0x0310
+#define PCI_DEVICE_ID_PC300_TE_1	0x0311
+#define PCI_DEVICE_ID_PC300_TE_M_2	0x0320
+#define PCI_DEVICE_ID_PC300_TE_M_1	0x0321
+
+#define PCI_VENDOR_ID_ESSENTIAL		0x120f
+#define PCI_DEVICE_ID_ESSENTIAL_ROADRUNNER	0x0001
+
+#define PCI_VENDOR_ID_O2		0x1217
+#define PCI_DEVICE_ID_O2_6729		0x6729
+#define PCI_DEVICE_ID_O2_6730		0x673a
+#define PCI_DEVICE_ID_O2_6832		0x6832
+#define PCI_DEVICE_ID_O2_6836		0x6836
+#define PCI_DEVICE_ID_O2_6812		0x6872
+#define PCI_DEVICE_ID_O2_6933		0x6933
+#define PCI_DEVICE_ID_O2_8120		0x8120
+#define PCI_DEVICE_ID_O2_8220		0x8220
+#define PCI_DEVICE_ID_O2_8221		0x8221
+#define PCI_DEVICE_ID_O2_8320		0x8320
+#define PCI_DEVICE_ID_O2_8321		0x8321
+
+#define PCI_VENDOR_ID_3DFX		0x121a
+#define PCI_DEVICE_ID_3DFX_VOODOO	0x0001
+#define PCI_DEVICE_ID_3DFX_VOODOO2	0x0002
+#define PCI_DEVICE_ID_3DFX_BANSHEE	0x0003
+#define PCI_DEVICE_ID_3DFX_VOODOO3	0x0005
+#define PCI_DEVICE_ID_3DFX_VOODOO5	0x0009
+
+#define PCI_VENDOR_ID_AVM		0x1244
+#define PCI_DEVICE_ID_AVM_B1		0x0700
+#define PCI_DEVICE_ID_AVM_C4		0x0800
+#define PCI_DEVICE_ID_AVM_A1		0x0a00
+#define PCI_DEVICE_ID_AVM_A1_V2		0x0e00
+#define PCI_DEVICE_ID_AVM_C2		0x1100
+#define PCI_DEVICE_ID_AVM_T1		0x1200
+
+#define PCI_VENDOR_ID_STALLION		0x124d
+
+/* Allied Telesyn */
+#define PCI_VENDOR_ID_AT		0x1259
+#define PCI_SUBDEVICE_ID_AT_2700FX	0x2701
+#define PCI_SUBDEVICE_ID_AT_2701FX	0x2703
+
+#define PCI_VENDOR_ID_ESS		0x125d
+#define PCI_DEVICE_ID_ESS_ESS1968	0x1968
+#define PCI_DEVICE_ID_ESS_ESS1978	0x1978
+#define PCI_DEVICE_ID_ESS_ALLEGRO_1	0x1988
+#define PCI_DEVICE_ID_ESS_ALLEGRO	0x1989
+#define PCI_DEVICE_ID_ESS_CANYON3D_2LE	0x1990
+#define PCI_DEVICE_ID_ESS_CANYON3D_2	0x1992
+#define PCI_DEVICE_ID_ESS_MAESTRO3	0x1998
+#define PCI_DEVICE_ID_ESS_MAESTRO3_1	0x1999
+#define PCI_DEVICE_ID_ESS_MAESTRO3_HW	0x199a
+#define PCI_DEVICE_ID_ESS_MAESTRO3_2	0x199b
+
+#define PCI_VENDOR_ID_SATSAGEM		0x1267
+#define PCI_DEVICE_ID_SATSAGEM_NICCY	0x1016
+
+#define PCI_VENDOR_ID_SMI		0x126f
+#define PCI_DEVICE_ID_SMI_710		0x0710
+#define PCI_DEVICE_ID_SMI_712		0x0712
+#define PCI_DEVICE_ID_SMI_810		0x0810
+#define PCI_DEVICE_ID_SMI_501		0x0501
+
+#define PCI_VENDOR_ID_ENSONIQ		0x1274
+#define PCI_DEVICE_ID_ENSONIQ_CT5880	0x5880
+#define PCI_DEVICE_ID_ENSONIQ_ES1370	0x5000
+#define PCI_DEVICE_ID_ENSONIQ_ES1371	0x1371
+
+#define PCI_VENDOR_ID_TRANSMETA		0x1279
+#define PCI_DEVICE_ID_EFFICEON		0x0060
+
+#define PCI_VENDOR_ID_ROCKWELL		0x127A
+
+#define PCI_VENDOR_ID_DAVICOM		0x1282
+#define PCI_DEVICE_ID_DAVICOM_DM9102A	0x9102
+
+#define PCI_VENDOR_ID_ITE		0x1283
+#define PCI_DEVICE_ID_ITE_8172		0x8172
+#define PCI_DEVICE_ID_ITE_8211		0x8211
+#define PCI_DEVICE_ID_ITE_8212		0x8212
+#define PCI_DEVICE_ID_ITE_8213		0x8213
+#define PCI_DEVICE_ID_ITE_8152		0x8152
+#define PCI_DEVICE_ID_ITE_8872		0x8872
+#define PCI_DEVICE_ID_ITE_IT8330G_0	0xe886
+
+/* formerly Platform Tech */
+#define PCI_DEVICE_ID_ESS_ESS0100	0x0100
+
+#define PCI_VENDOR_ID_ALTEON		0x12ae
+
+#define PCI_SUBVENDOR_ID_CONNECT_TECH			0x12c4
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232		0x0001
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232		0x0002
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232		0x0003
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485		0x0004
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4	0x0005
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485		0x0006
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2	0x0007
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485		0x0008
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6	0x0009
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1	0x000A
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1	0x000B
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ		0x000C
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_PTM		0x000D
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_NT960PCI		0x0100
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2		0x0201
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4		0x0202
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232	0x0300
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232	0x0301
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232	0x0302
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1	0x0310
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2	0x0311
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4	0x0312
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2	0x0320
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4	0x0321
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8	0x0322
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485	0x0330
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485	0x0331
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485	0x0332
+
+#define PCI_VENDOR_ID_NVIDIA_SGS	0x12d2
+#define PCI_DEVICE_ID_NVIDIA_SGS_RIVA128 0x0018
+
+#define PCI_SUBVENDOR_ID_CHASE_PCIFAST		0x12E0
+#define PCI_SUBDEVICE_ID_CHASE_PCIFAST4		0x0031
+#define PCI_SUBDEVICE_ID_CHASE_PCIFAST8		0x0021
+#define PCI_SUBDEVICE_ID_CHASE_PCIFAST16	0x0011
+#define PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC	0x0041
+#define PCI_SUBVENDOR_ID_CHASE_PCIRAS		0x124D
+#define PCI_SUBDEVICE_ID_CHASE_PCIRAS4		0xF001
+#define PCI_SUBDEVICE_ID_CHASE_PCIRAS8		0xF010
+
+#define PCI_VENDOR_ID_AUREAL		0x12eb
+#define PCI_DEVICE_ID_AUREAL_VORTEX_1	0x0001
+#define PCI_DEVICE_ID_AUREAL_VORTEX_2	0x0002
+#define PCI_DEVICE_ID_AUREAL_ADVANTAGE	0x0003
+
+#define PCI_VENDOR_ID_ELECTRONICDESIGNGMBH 0x12f8
+#define PCI_DEVICE_ID_LML_33R10		0x8a02
+
+#define PCI_VENDOR_ID_ESDGMBH		0x12fe
+#define PCI_DEVICE_ID_ESDGMBH_CPCIASIO4 0x0111
+
+#define PCI_VENDOR_ID_SIIG		0x131f
+#define PCI_SUBVENDOR_ID_SIIG		0x131f
+#define PCI_DEVICE_ID_SIIG_1S_10x_550	0x1000
+#define PCI_DEVICE_ID_SIIG_1S_10x_650	0x1001
+#define PCI_DEVICE_ID_SIIG_1S_10x_850	0x1002
+#define PCI_DEVICE_ID_SIIG_1S1P_10x_550	0x1010
+#define PCI_DEVICE_ID_SIIG_1S1P_10x_650	0x1011
+#define PCI_DEVICE_ID_SIIG_1S1P_10x_850	0x1012
+#define PCI_DEVICE_ID_SIIG_1P_10x	0x1020
+#define PCI_DEVICE_ID_SIIG_2P_10x	0x1021
+#define PCI_DEVICE_ID_SIIG_2S_10x_550	0x1030
+#define PCI_DEVICE_ID_SIIG_2S_10x_650	0x1031
+#define PCI_DEVICE_ID_SIIG_2S_10x_850	0x1032
+#define PCI_DEVICE_ID_SIIG_2S1P_10x_550	0x1034
+#define PCI_DEVICE_ID_SIIG_2S1P_10x_650	0x1035
+#define PCI_DEVICE_ID_SIIG_2S1P_10x_850	0x1036
+#define PCI_DEVICE_ID_SIIG_4S_10x_550	0x1050
+#define PCI_DEVICE_ID_SIIG_4S_10x_650	0x1051
+#define PCI_DEVICE_ID_SIIG_4S_10x_850	0x1052
+#define PCI_DEVICE_ID_SIIG_1S_20x_550	0x2000
+#define PCI_DEVICE_ID_SIIG_1S_20x_650	0x2001
+#define PCI_DEVICE_ID_SIIG_1S_20x_850	0x2002
+#define PCI_DEVICE_ID_SIIG_1P_20x	0x2020
+#define PCI_DEVICE_ID_SIIG_2P_20x	0x2021
+#define PCI_DEVICE_ID_SIIG_2S_20x_550	0x2030
+#define PCI_DEVICE_ID_SIIG_2S_20x_650	0x2031
+#define PCI_DEVICE_ID_SIIG_2S_20x_850	0x2032
+#define PCI_DEVICE_ID_SIIG_2P1S_20x_550	0x2040
+#define PCI_DEVICE_ID_SIIG_2P1S_20x_650	0x2041
+#define PCI_DEVICE_ID_SIIG_2P1S_20x_850	0x2042
+#define PCI_DEVICE_ID_SIIG_1S1P_20x_550	0x2010
+#define PCI_DEVICE_ID_SIIG_1S1P_20x_650	0x2011
+#define PCI_DEVICE_ID_SIIG_1S1P_20x_850	0x2012
+#define PCI_DEVICE_ID_SIIG_4S_20x_550	0x2050
+#define PCI_DEVICE_ID_SIIG_4S_20x_650	0x2051
+#define PCI_DEVICE_ID_SIIG_4S_20x_850	0x2052
+#define PCI_DEVICE_ID_SIIG_2S1P_20x_550	0x2060
+#define PCI_DEVICE_ID_SIIG_2S1P_20x_650	0x2061
+#define PCI_DEVICE_ID_SIIG_2S1P_20x_850	0x2062
+#define PCI_DEVICE_ID_SIIG_8S_20x_550	0x2080
+#define PCI_DEVICE_ID_SIIG_8S_20x_650	0x2081
+#define PCI_DEVICE_ID_SIIG_8S_20x_850	0x2082
+#define PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL	0x2050
+#define PCI_SUBDEVICE_ID_SIIG_DUAL_SERIAL	0x2530
+
+#define PCI_VENDOR_ID_RADISYS		0x1331
+
+#define PCI_VENDOR_ID_MICRO_MEMORY		0x1332
+#define PCI_DEVICE_ID_MICRO_MEMORY_5415CN	0x5415
+#define PCI_DEVICE_ID_MICRO_MEMORY_5425CN	0x5425
+#define PCI_DEVICE_ID_MICRO_MEMORY_6155		0x6155
+
+#define PCI_VENDOR_ID_DOMEX		0x134a
+#define PCI_DEVICE_ID_DOMEX_DMX3191D	0x0001
+
+#define PCI_VENDOR_ID_INTASHIELD	0x135a
+#define PCI_DEVICE_ID_INTASHIELD_IS200	0x0d80
+#define PCI_DEVICE_ID_INTASHIELD_IS400	0x0dc0
+
+#define PCI_VENDOR_ID_QUATECH		0x135C
+#define PCI_DEVICE_ID_QUATECH_QSC100	0x0010
+#define PCI_DEVICE_ID_QUATECH_DSC100	0x0020
+#define PCI_DEVICE_ID_QUATECH_ESC100D	0x0050
+#define PCI_DEVICE_ID_QUATECH_ESC100M	0x0060
+#define PCI_DEVICE_ID_QUATECH_SPPXP_100 0x0278
+
+#define PCI_VENDOR_ID_SEALEVEL		0x135e
+#define PCI_DEVICE_ID_SEALEVEL_U530	0x7101
+#define PCI_DEVICE_ID_SEALEVEL_UCOMM2	0x7201
+#define PCI_DEVICE_ID_SEALEVEL_UCOMM422	0x7402
+#define PCI_DEVICE_ID_SEALEVEL_UCOMM232	0x7202
+#define PCI_DEVICE_ID_SEALEVEL_COMM4	0x7401
+#define PCI_DEVICE_ID_SEALEVEL_COMM8	0x7801
+#define PCI_DEVICE_ID_SEALEVEL_7803	0x7803
+#define PCI_DEVICE_ID_SEALEVEL_UCOMM8	0x7804
+
+#define PCI_VENDOR_ID_HYPERCOPE		0x1365
+#define PCI_DEVICE_ID_HYPERCOPE_PLX	0x9050
+#define PCI_SUBDEVICE_ID_HYPERCOPE_OLD_ERGO	0x0104
+#define PCI_SUBDEVICE_ID_HYPERCOPE_ERGO		0x0106
+#define PCI_SUBDEVICE_ID_HYPERCOPE_METRO	0x0107
+#define PCI_SUBDEVICE_ID_HYPERCOPE_CHAMP2	0x0108
+
+#define PCI_VENDOR_ID_DIGIGRAM		0x1369
+#define PCI_SUBDEVICE_ID_DIGIGRAM_LX6464ES_SERIAL_SUBSYSTEM	0xc001
+#define PCI_SUBDEVICE_ID_DIGIGRAM_LX6464ES_CAE_SERIAL_SUBSYSTEM	0xc002
+
+#define PCI_VENDOR_ID_KAWASAKI		0x136b
+#define PCI_DEVICE_ID_MCHIP_KL5A72002	0xff01
+
+#define PCI_VENDOR_ID_CNET		0x1371
+#define PCI_DEVICE_ID_CNET_GIGACARD	0x434e
+
+#define PCI_VENDOR_ID_LMC		0x1376
+#define PCI_DEVICE_ID_LMC_HSSI		0x0003
+#define PCI_DEVICE_ID_LMC_DS3		0x0004
+#define PCI_DEVICE_ID_LMC_SSI		0x0005
+#define PCI_DEVICE_ID_LMC_T1		0x0006
+
+#define PCI_VENDOR_ID_NETGEAR		0x1385
+#define PCI_DEVICE_ID_NETGEAR_GA620	0x620a
+
+#define PCI_VENDOR_ID_APPLICOM		0x1389
+#define PCI_DEVICE_ID_APPLICOM_PCIGENERIC 0x0001
+#define PCI_DEVICE_ID_APPLICOM_PCI2000IBS_CAN 0x0002
+#define PCI_DEVICE_ID_APPLICOM_PCI2000PFB 0x0003
+
+#define PCI_VENDOR_ID_MOXA		0x1393
+#define PCI_DEVICE_ID_MOXA_RC7000	0x0001
+#define PCI_DEVICE_ID_MOXA_CP102	0x1020
+#define PCI_DEVICE_ID_MOXA_CP102UL	0x1021
+#define PCI_DEVICE_ID_MOXA_CP102U	0x1022
+#define PCI_DEVICE_ID_MOXA_C104		0x1040
+#define PCI_DEVICE_ID_MOXA_CP104U	0x1041
+#define PCI_DEVICE_ID_MOXA_CP104JU	0x1042
+#define PCI_DEVICE_ID_MOXA_CP104EL	0x1043
+#define PCI_DEVICE_ID_MOXA_CT114	0x1140
+#define PCI_DEVICE_ID_MOXA_CP114	0x1141
+#define PCI_DEVICE_ID_MOXA_CP118U	0x1180
+#define PCI_DEVICE_ID_MOXA_CP118EL	0x1181
+#define PCI_DEVICE_ID_MOXA_CP132	0x1320
+#define PCI_DEVICE_ID_MOXA_CP132U	0x1321
+#define PCI_DEVICE_ID_MOXA_CP134U	0x1340
+#define PCI_DEVICE_ID_MOXA_C168		0x1680
+#define PCI_DEVICE_ID_MOXA_CP168U	0x1681
+#define PCI_DEVICE_ID_MOXA_CP168EL	0x1682
+#define PCI_DEVICE_ID_MOXA_CP204J	0x2040
+#define PCI_DEVICE_ID_MOXA_C218		0x2180
+#define PCI_DEVICE_ID_MOXA_C320		0x3200
+
+#define PCI_VENDOR_ID_CCD		0x1397
+#define PCI_DEVICE_ID_CCD_HFC4S		0x08B4
+#define PCI_SUBDEVICE_ID_CCD_PMX2S	0x1234
+#define PCI_DEVICE_ID_CCD_HFC8S		0x16B8
+#define PCI_DEVICE_ID_CCD_2BD0		0x2bd0
+#define PCI_DEVICE_ID_CCD_HFCE1		0x30B1
+#define PCI_SUBDEVICE_ID_CCD_SPD4S	0x3136
+#define PCI_SUBDEVICE_ID_CCD_SPDE1	0x3137
+#define PCI_DEVICE_ID_CCD_B000		0xb000
+#define PCI_DEVICE_ID_CCD_B006		0xb006
+#define PCI_DEVICE_ID_CCD_B007		0xb007
+#define PCI_DEVICE_ID_CCD_B008		0xb008
+#define PCI_DEVICE_ID_CCD_B009		0xb009
+#define PCI_DEVICE_ID_CCD_B00A		0xb00a
+#define PCI_DEVICE_ID_CCD_B00B		0xb00b
+#define PCI_DEVICE_ID_CCD_B00C		0xb00c
+#define PCI_DEVICE_ID_CCD_B100		0xb100
+#define PCI_SUBDEVICE_ID_CCD_IOB4ST	0xB520
+#define PCI_SUBDEVICE_ID_CCD_IOB8STR	0xB521
+#define PCI_SUBDEVICE_ID_CCD_IOB8ST	0xB522
+#define PCI_SUBDEVICE_ID_CCD_IOB1E1	0xB523
+#define PCI_SUBDEVICE_ID_CCD_SWYX4S	0xB540
+#define PCI_SUBDEVICE_ID_CCD_JH4S20	0xB550
+#define PCI_SUBDEVICE_ID_CCD_IOB8ST_1	0xB552
+#define PCI_SUBDEVICE_ID_CCD_JHSE1	0xB553
+#define PCI_SUBDEVICE_ID_CCD_JH8S	0xB55B
+#define PCI_SUBDEVICE_ID_CCD_BN4S	0xB560
+#define PCI_SUBDEVICE_ID_CCD_BN8S	0xB562
+#define PCI_SUBDEVICE_ID_CCD_BNE1	0xB563
+#define PCI_SUBDEVICE_ID_CCD_BNE1D	0xB564
+#define PCI_SUBDEVICE_ID_CCD_BNE1DP	0xB565
+#define PCI_SUBDEVICE_ID_CCD_BN2S	0xB566
+#define PCI_SUBDEVICE_ID_CCD_BN1SM	0xB567
+#define PCI_SUBDEVICE_ID_CCD_BN4SM	0xB568
+#define PCI_SUBDEVICE_ID_CCD_BN2SM	0xB569
+#define PCI_SUBDEVICE_ID_CCD_BNE1M	0xB56A
+#define PCI_SUBDEVICE_ID_CCD_BN8SP	0xB56B
+#define PCI_SUBDEVICE_ID_CCD_HFC4S	0xB620
+#define PCI_SUBDEVICE_ID_CCD_HFC8S	0xB622
+#define PCI_DEVICE_ID_CCD_B700		0xb700
+#define PCI_DEVICE_ID_CCD_B701		0xb701
+#define PCI_SUBDEVICE_ID_CCD_HFCE1	0xC523
+#define PCI_SUBDEVICE_ID_CCD_OV2S	0xE884
+#define PCI_SUBDEVICE_ID_CCD_OV4S	0xE888
+#define PCI_SUBDEVICE_ID_CCD_OV8S	0xE998
+
+#define PCI_VENDOR_ID_EXAR		0x13a8
+#define PCI_DEVICE_ID_EXAR_XR17C152	0x0152
+#define PCI_DEVICE_ID_EXAR_XR17C154	0x0154
+#define PCI_DEVICE_ID_EXAR_XR17C158	0x0158
+
+#define PCI_VENDOR_ID_MICROGATE		0x13c0
+#define PCI_DEVICE_ID_MICROGATE_USC	0x0010
+#define PCI_DEVICE_ID_MICROGATE_SCA	0x0030
+
+#define PCI_VENDOR_ID_3WARE		0x13C1
+#define PCI_DEVICE_ID_3WARE_1000	0x1000
+#define PCI_DEVICE_ID_3WARE_7000	0x1001
+#define PCI_DEVICE_ID_3WARE_9000	0x1002
+
+#define PCI_VENDOR_ID_IOMEGA		0x13ca
+#define PCI_DEVICE_ID_IOMEGA_BUZ	0x4231
+
+#define PCI_VENDOR_ID_ABOCOM		0x13D1
+#define PCI_DEVICE_ID_ABOCOM_2BD1       0x2BD1
+
+#define PCI_VENDOR_ID_SUNDANCE		0x13f0
+
+#define PCI_VENDOR_ID_CMEDIA		0x13f6
+#define PCI_DEVICE_ID_CMEDIA_CM8338A	0x0100
+#define PCI_DEVICE_ID_CMEDIA_CM8338B	0x0101
+#define PCI_DEVICE_ID_CMEDIA_CM8738	0x0111
+#define PCI_DEVICE_ID_CMEDIA_CM8738B	0x0112
+
+#define PCI_VENDOR_ID_LAVA		0x1407
+#define PCI_DEVICE_ID_LAVA_DSERIAL	0x0100 /* 2x 16550 */
+#define PCI_DEVICE_ID_LAVA_QUATRO_A	0x0101 /* 2x 16550, half of 4 port */
+#define PCI_DEVICE_ID_LAVA_QUATRO_B	0x0102 /* 2x 16550, half of 4 port */
+#define PCI_DEVICE_ID_LAVA_QUATTRO_A	0x0120 /* 2x 16550A, half of 4 port */
+#define PCI_DEVICE_ID_LAVA_QUATTRO_B	0x0121 /* 2x 16550A, half of 4 port */
+#define PCI_DEVICE_ID_LAVA_OCTO_A	0x0180 /* 4x 16550A, half of 8 port */
+#define PCI_DEVICE_ID_LAVA_OCTO_B	0x0181 /* 4x 16550A, half of 8 port */
+#define PCI_DEVICE_ID_LAVA_PORT_PLUS	0x0200 /* 2x 16650 */
+#define PCI_DEVICE_ID_LAVA_QUAD_A	0x0201 /* 2x 16650, half of 4 port */
+#define PCI_DEVICE_ID_LAVA_QUAD_B	0x0202 /* 2x 16650, half of 4 port */
+#define PCI_DEVICE_ID_LAVA_SSERIAL	0x0500 /* 1x 16550 */
+#define PCI_DEVICE_ID_LAVA_PORT_650	0x0600 /* 1x 16650 */
+#define PCI_DEVICE_ID_LAVA_PARALLEL	0x8000
+#define PCI_DEVICE_ID_LAVA_DUAL_PAR_A	0x8002 /* The Lava Dual Parallel is */
+#define PCI_DEVICE_ID_LAVA_DUAL_PAR_B	0x8003 /* two PCI devices on a card */
+#define PCI_DEVICE_ID_LAVA_BOCA_IOPPAR	0x8800
+
+#define PCI_VENDOR_ID_TIMEDIA		0x1409
+#define PCI_DEVICE_ID_TIMEDIA_1889	0x7168
+
+#define PCI_VENDOR_ID_ICE		0x1412
+#define PCI_DEVICE_ID_ICE_1712		0x1712
+#define PCI_DEVICE_ID_VT1724		0x1724
+
+#define PCI_VENDOR_ID_OXSEMI		0x1415
+#define PCI_DEVICE_ID_OXSEMI_12PCI840	0x8403
+#define PCI_DEVICE_ID_OXSEMI_PCIe840		0xC000
+#define PCI_DEVICE_ID_OXSEMI_PCIe840_G		0xC004
+#define PCI_DEVICE_ID_OXSEMI_PCIe952_0		0xC100
+#define PCI_DEVICE_ID_OXSEMI_PCIe952_0_G	0xC104
+#define PCI_DEVICE_ID_OXSEMI_PCIe952_1		0xC110
+#define PCI_DEVICE_ID_OXSEMI_PCIe952_1_G	0xC114
+#define PCI_DEVICE_ID_OXSEMI_PCIe952_1_U	0xC118
+#define PCI_DEVICE_ID_OXSEMI_PCIe952_1_GU	0xC11C
+#define PCI_DEVICE_ID_OXSEMI_16PCI954	0x9501
+#define PCI_DEVICE_ID_OXSEMI_C950	0x950B
+#define PCI_DEVICE_ID_OXSEMI_16PCI95N	0x9511
+#define PCI_DEVICE_ID_OXSEMI_16PCI954PP	0x9513
+#define PCI_DEVICE_ID_OXSEMI_16PCI952	0x9521
+#define PCI_DEVICE_ID_OXSEMI_16PCI952PP	0x9523
+#define PCI_SUBDEVICE_ID_OXSEMI_C950	0x0001
+
+#define PCI_VENDOR_ID_CHELSIO		0x1425
+
+#define PCI_VENDOR_ID_SAMSUNG		0x144d
+
+#define PCI_VENDOR_ID_GIGABYTE		0x1458
+
+#define PCI_VENDOR_ID_AMBIT		0x1468
+
+#define PCI_VENDOR_ID_MYRICOM		0x14c1
+
+#define PCI_VENDOR_ID_TITAN		0x14D2
+#define PCI_DEVICE_ID_TITAN_010L	0x8001
+#define PCI_DEVICE_ID_TITAN_100L	0x8010
+#define PCI_DEVICE_ID_TITAN_110L	0x8011
+#define PCI_DEVICE_ID_TITAN_200L	0x8020
+#define PCI_DEVICE_ID_TITAN_210L	0x8021
+#define PCI_DEVICE_ID_TITAN_400L	0x8040
+#define PCI_DEVICE_ID_TITAN_800L	0x8080
+#define PCI_DEVICE_ID_TITAN_100		0xA001
+#define PCI_DEVICE_ID_TITAN_200		0xA005
+#define PCI_DEVICE_ID_TITAN_400		0xA003
+#define PCI_DEVICE_ID_TITAN_800B	0xA004
+
+#define PCI_VENDOR_ID_PANACOM		0x14d4
+#define PCI_DEVICE_ID_PANACOM_QUADMODEM	0x0400
+#define PCI_DEVICE_ID_PANACOM_DUALMODEM	0x0402
+
+#define PCI_VENDOR_ID_SIPACKETS		0x14d9
+#define PCI_DEVICE_ID_SP1011		0x0010
+
+#define PCI_VENDOR_ID_AFAVLAB		0x14db
+#define PCI_DEVICE_ID_AFAVLAB_P028	0x2180
+#define PCI_DEVICE_ID_AFAVLAB_P030	0x2182
+#define PCI_SUBDEVICE_ID_AFAVLAB_P061		0x2150
+
+#define PCI_VENDOR_ID_BCM_GVC          0x14a4
+#define PCI_VENDOR_ID_BROADCOM		0x14e4
+#define PCI_DEVICE_ID_TIGON3_5752	0x1600
+#define PCI_DEVICE_ID_TIGON3_5752M	0x1601
+#define PCI_DEVICE_ID_NX2_5709		0x1639
+#define PCI_DEVICE_ID_NX2_5709S		0x163a
+#define PCI_DEVICE_ID_TIGON3_5700	0x1644
+#define PCI_DEVICE_ID_TIGON3_5701	0x1645
+#define PCI_DEVICE_ID_TIGON3_5702	0x1646
+#define PCI_DEVICE_ID_TIGON3_5703	0x1647
+#define PCI_DEVICE_ID_TIGON3_5704	0x1648
+#define PCI_DEVICE_ID_TIGON3_5704S_2	0x1649
+#define PCI_DEVICE_ID_NX2_5706		0x164a
+#define PCI_DEVICE_ID_NX2_5708		0x164c
+#define PCI_DEVICE_ID_TIGON3_5702FE	0x164d
+#define PCI_DEVICE_ID_NX2_57710		0x164e
+#define PCI_DEVICE_ID_NX2_57711		0x164f
+#define PCI_DEVICE_ID_NX2_57711E	0x1650
+#define PCI_DEVICE_ID_TIGON3_5705	0x1653
+#define PCI_DEVICE_ID_TIGON3_5705_2	0x1654
+#define PCI_DEVICE_ID_TIGON3_5721	0x1659
+#define PCI_DEVICE_ID_TIGON3_5722	0x165a
+#define PCI_DEVICE_ID_TIGON3_5723	0x165b
+#define PCI_DEVICE_ID_TIGON3_5705M	0x165d
+#define PCI_DEVICE_ID_TIGON3_5705M_2	0x165e
+#define PCI_DEVICE_ID_TIGON3_5714	0x1668
+#define PCI_DEVICE_ID_TIGON3_5714S	0x1669
+#define PCI_DEVICE_ID_TIGON3_5780	0x166a
+#define PCI_DEVICE_ID_TIGON3_5780S	0x166b
+#define PCI_DEVICE_ID_TIGON3_5705F	0x166e
+#define PCI_DEVICE_ID_TIGON3_5754M	0x1672
+#define PCI_DEVICE_ID_TIGON3_5755M	0x1673
+#define PCI_DEVICE_ID_TIGON3_5756	0x1674
+#define PCI_DEVICE_ID_TIGON3_5751	0x1677
+#define PCI_DEVICE_ID_TIGON3_5715	0x1678
+#define PCI_DEVICE_ID_TIGON3_5715S	0x1679
+#define PCI_DEVICE_ID_TIGON3_5754	0x167a
+#define PCI_DEVICE_ID_TIGON3_5755	0x167b
+#define PCI_DEVICE_ID_TIGON3_5751M	0x167d
+#define PCI_DEVICE_ID_TIGON3_5751F	0x167e
+#define PCI_DEVICE_ID_TIGON3_5787F	0x167f
+#define PCI_DEVICE_ID_TIGON3_5761E	0x1680
+#define PCI_DEVICE_ID_TIGON3_5761	0x1681
+#define PCI_DEVICE_ID_TIGON3_5764	0x1684
+#define PCI_DEVICE_ID_TIGON3_5787M	0x1693
+#define PCI_DEVICE_ID_TIGON3_5782	0x1696
+#define PCI_DEVICE_ID_TIGON3_5784	0x1698
+#define PCI_DEVICE_ID_TIGON3_5786	0x169a
+#define PCI_DEVICE_ID_TIGON3_5787	0x169b
+#define PCI_DEVICE_ID_TIGON3_5788	0x169c
+#define PCI_DEVICE_ID_TIGON3_5789	0x169d
+#define PCI_DEVICE_ID_TIGON3_5702X	0x16a6
+#define PCI_DEVICE_ID_TIGON3_5703X	0x16a7
+#define PCI_DEVICE_ID_TIGON3_5704S	0x16a8
+#define PCI_DEVICE_ID_NX2_5706S		0x16aa
+#define PCI_DEVICE_ID_NX2_5708S		0x16ac
+#define PCI_DEVICE_ID_TIGON3_5702A3	0x16c6
+#define PCI_DEVICE_ID_TIGON3_5703A3	0x16c7
+#define PCI_DEVICE_ID_TIGON3_5781	0x16dd
+#define PCI_DEVICE_ID_TIGON3_5753	0x16f7
+#define PCI_DEVICE_ID_TIGON3_5753M	0x16fd
+#define PCI_DEVICE_ID_TIGON3_5753F	0x16fe
+#define PCI_DEVICE_ID_TIGON3_5901	0x170d
+#define PCI_DEVICE_ID_BCM4401B1		0x170c
+#define PCI_DEVICE_ID_TIGON3_5901_2	0x170e
+#define PCI_DEVICE_ID_TIGON3_5906	0x1712
+#define PCI_DEVICE_ID_TIGON3_5906M	0x1713
+#define PCI_DEVICE_ID_BCM4401		0x4401
+#define PCI_DEVICE_ID_BCM4401B0		0x4402
+
+#define PCI_VENDOR_ID_TOPIC		0x151f
+#define PCI_DEVICE_ID_TOPIC_TP560	0x0000
+
+#define PCI_VENDOR_ID_MAINPINE		0x1522
+#define PCI_DEVICE_ID_MAINPINE_PBRIDGE	0x0100
+#define PCI_VENDOR_ID_ENE		0x1524
+#define PCI_DEVICE_ID_ENE_CB710_FLASH	0x0510
+#define PCI_DEVICE_ID_ENE_CB712_SD	0x0550
+#define PCI_DEVICE_ID_ENE_CB712_SD_2	0x0551
+#define PCI_DEVICE_ID_ENE_CB714_SD	0x0750
+#define PCI_DEVICE_ID_ENE_CB714_SD_2	0x0751
+#define PCI_DEVICE_ID_ENE_1211		0x1211
+#define PCI_DEVICE_ID_ENE_1225		0x1225
+#define PCI_DEVICE_ID_ENE_1410		0x1410
+#define PCI_DEVICE_ID_ENE_710		0x1411
+#define PCI_DEVICE_ID_ENE_712		0x1412
+#define PCI_DEVICE_ID_ENE_1420		0x1420
+#define PCI_DEVICE_ID_ENE_720		0x1421
+#define PCI_DEVICE_ID_ENE_722		0x1422
+
+#define PCI_VENDOR_ID_MIPS		0x153f
+#define PCI_DEVICE_ID_MIPS_MSC01	0x0001
+
+#define PCI_SUBVENDOR_ID_PERLE          0x155f
+#define PCI_SUBDEVICE_ID_PCI_RAS4       0xf001
+#define PCI_SUBDEVICE_ID_PCI_RAS8       0xf010
+
+#define PCI_VENDOR_ID_SYBA		0x1592
+#define PCI_DEVICE_ID_SYBA_2P_EPP	0x0782
+#define PCI_DEVICE_ID_SYBA_1P_ECP	0x0783
+
+#define PCI_VENDOR_ID_MORETON		0x15aa
+#define PCI_DEVICE_ID_RASTEL_2PORT	0x2000
+
+#define PCI_VENDOR_ID_ZOLTRIX		0x15b0
+#define PCI_DEVICE_ID_ZOLTRIX_2BD0	0x2bd0
+
+#define PCI_VENDOR_ID_MELLANOX		0x15b3
+#define PCI_DEVICE_ID_MELLANOX_TAVOR	0x5a44
+#define PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE	0x5a46
+#define PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT 0x6278
+#define PCI_DEVICE_ID_MELLANOX_ARBEL	0x6282
+#define PCI_DEVICE_ID_MELLANOX_SINAI_OLD 0x5e8c
+#define PCI_DEVICE_ID_MELLANOX_SINAI	0x6274
+
+#define PCI_VENDOR_ID_DFI		0x15bd
+
+#define PCI_VENDOR_ID_QUICKNET		0x15e2
+#define PCI_DEVICE_ID_QUICKNET_XJ	0x0500
+
+/*
+ * ADDI-DATA GmbH communication cards <info@addi-data.com>
+ */
+#define PCI_VENDOR_ID_ADDIDATA_OLD             0x10E8
+#define PCI_VENDOR_ID_ADDIDATA                 0x15B8
+#define PCI_DEVICE_ID_ADDIDATA_APCI7500        0x7000
+#define PCI_DEVICE_ID_ADDIDATA_APCI7420        0x7001
+#define PCI_DEVICE_ID_ADDIDATA_APCI7300        0x7002
+#define PCI_DEVICE_ID_ADDIDATA_APCI7800        0x818E
+#define PCI_DEVICE_ID_ADDIDATA_APCI7500_2      0x7009
+#define PCI_DEVICE_ID_ADDIDATA_APCI7420_2      0x700A
+#define PCI_DEVICE_ID_ADDIDATA_APCI7300_2      0x700B
+#define PCI_DEVICE_ID_ADDIDATA_APCI7500_3      0x700C
+#define PCI_DEVICE_ID_ADDIDATA_APCI7420_3      0x700D
+#define PCI_DEVICE_ID_ADDIDATA_APCI7300_3      0x700E
+#define PCI_DEVICE_ID_ADDIDATA_APCI7800_3      0x700F
+#define PCI_DEVICE_ID_ADDIDATA_APCIe7300       0x7010
+#define PCI_DEVICE_ID_ADDIDATA_APCIe7420       0x7011
+#define PCI_DEVICE_ID_ADDIDATA_APCIe7500       0x7012
+#define PCI_DEVICE_ID_ADDIDATA_APCIe7800       0x7013
+
+#define PCI_VENDOR_ID_PDC		0x15e9
+
+#define PCI_VENDOR_ID_FARSITE           0x1619
+#define PCI_DEVICE_ID_FARSITE_T2P       0x0400
+#define PCI_DEVICE_ID_FARSITE_T4P       0x0440
+#define PCI_DEVICE_ID_FARSITE_T1U       0x0610
+#define PCI_DEVICE_ID_FARSITE_T2U       0x0620
+#define PCI_DEVICE_ID_FARSITE_T4U       0x0640
+#define PCI_DEVICE_ID_FARSITE_TE1       0x1610
+#define PCI_DEVICE_ID_FARSITE_TE1C      0x1612
+
+#define PCI_VENDOR_ID_ARIMA		0x161f
+
+#define PCI_VENDOR_ID_BROCADE		0x1657
+#define PCI_DEVICE_ID_BROCADE_CT	0x0014
+#define PCI_DEVICE_ID_BROCADE_FC_8G1P	0x0017
+#define PCI_DEVICE_ID_BROCADE_CT_FC	0x0021
+
+#define PCI_VENDOR_ID_SIBYTE		0x166d
+#define PCI_DEVICE_ID_BCM1250_PCI	0x0001
+#define PCI_DEVICE_ID_BCM1250_HT	0x0002
+
+#define PCI_VENDOR_ID_ATHEROS		0x168c
+
+#define PCI_VENDOR_ID_NETCELL		0x169c
+#define PCI_DEVICE_ID_REVOLUTION	0x0044
+
+#define PCI_VENDOR_ID_CENATEK		0x16CA
+#define PCI_DEVICE_ID_CENATEK_IDE	0x0001
+
+#define PCI_VENDOR_ID_VITESSE		0x1725
+#define PCI_DEVICE_ID_VITESSE_VSC7174	0x7174
+
+#define PCI_VENDOR_ID_LINKSYS		0x1737
+#define PCI_DEVICE_ID_LINKSYS_EG1064	0x1064
+
+#define PCI_VENDOR_ID_ALTIMA		0x173b
+#define PCI_DEVICE_ID_ALTIMA_AC1000	0x03e8
+#define PCI_DEVICE_ID_ALTIMA_AC1001	0x03e9
+#define PCI_DEVICE_ID_ALTIMA_AC9100	0x03ea
+#define PCI_DEVICE_ID_ALTIMA_AC1003	0x03eb
+
+#define PCI_VENDOR_ID_BELKIN		0x1799
+#define PCI_DEVICE_ID_BELKIN_F5D7010V7	0x701f
+
+#define PCI_VENDOR_ID_RDC		0x17f3
+#define PCI_DEVICE_ID_RDC_R6020		0x6020
+#define PCI_DEVICE_ID_RDC_R6030		0x6030
+#define PCI_DEVICE_ID_RDC_R6040		0x6040
+#define PCI_DEVICE_ID_RDC_R6060		0x6060
+#define PCI_DEVICE_ID_RDC_R6061		0x6061
+#define PCI_DEVICE_ID_RDC_D1010		0x1010
+
+#define PCI_VENDOR_ID_LENOVO		0x17aa
+
+#define PCI_VENDOR_ID_ARECA		0x17d3
+#define PCI_DEVICE_ID_ARECA_1110	0x1110
+#define PCI_DEVICE_ID_ARECA_1120	0x1120
+#define PCI_DEVICE_ID_ARECA_1130	0x1130
+#define PCI_DEVICE_ID_ARECA_1160	0x1160
+#define PCI_DEVICE_ID_ARECA_1170	0x1170
+#define PCI_DEVICE_ID_ARECA_1200	0x1200
+#define PCI_DEVICE_ID_ARECA_1201	0x1201
+#define PCI_DEVICE_ID_ARECA_1202	0x1202
+#define PCI_DEVICE_ID_ARECA_1210	0x1210
+#define PCI_DEVICE_ID_ARECA_1220	0x1220
+#define PCI_DEVICE_ID_ARECA_1230	0x1230
+#define PCI_DEVICE_ID_ARECA_1260	0x1260
+#define PCI_DEVICE_ID_ARECA_1270	0x1270
+#define PCI_DEVICE_ID_ARECA_1280	0x1280
+#define PCI_DEVICE_ID_ARECA_1380	0x1380
+#define PCI_DEVICE_ID_ARECA_1381	0x1381
+#define PCI_DEVICE_ID_ARECA_1680	0x1680
+#define PCI_DEVICE_ID_ARECA_1681	0x1681
+
+#define PCI_VENDOR_ID_S2IO		0x17d5
+#define	PCI_DEVICE_ID_S2IO_WIN		0x5731
+#define	PCI_DEVICE_ID_S2IO_UNI		0x5831
+#define PCI_DEVICE_ID_HERC_WIN		0x5732
+#define PCI_DEVICE_ID_HERC_UNI		0x5832
+
+#define PCI_VENDOR_ID_SITECOM		0x182d
+#define PCI_DEVICE_ID_SITECOM_DC105V2	0x3069
+
+#define PCI_VENDOR_ID_TOPSPIN		0x1867
+
+#define PCI_VENDOR_ID_SILAN		0x1904
+
+#define PCI_VENDOR_ID_RENESAS		0x1912
+#define PCI_DEVICE_ID_RENESAS_SH7781	0x0001
+#define PCI_DEVICE_ID_RENESAS_SH7780	0x0002
+#define PCI_DEVICE_ID_RENESAS_SH7763	0x0004
+#define PCI_DEVICE_ID_RENESAS_SH7785	0x0007
+#define PCI_DEVICE_ID_RENESAS_SH7786	0x0010
+
+#define PCI_VENDOR_ID_TDI               0x192E
+#define PCI_DEVICE_ID_TDI_EHCI          0x0101
+
+#define PCI_VENDOR_ID_FREESCALE		0x1957
+#define PCI_DEVICE_ID_MPC8308		0xc006
+#define PCI_DEVICE_ID_MPC8315E		0x00b4
+#define PCI_DEVICE_ID_MPC8315		0x00b5
+#define PCI_DEVICE_ID_MPC8314E		0x00b6
+#define PCI_DEVICE_ID_MPC8314		0x00b7
+#define PCI_DEVICE_ID_MPC8378E		0x00c4
+#define PCI_DEVICE_ID_MPC8378		0x00c5
+#define PCI_DEVICE_ID_MPC8377E		0x00c6
+#define PCI_DEVICE_ID_MPC8377		0x00c7
+#define PCI_DEVICE_ID_MPC8548E		0x0012
+#define PCI_DEVICE_ID_MPC8548		0x0013
+#define PCI_DEVICE_ID_MPC8543E		0x0014
+#define PCI_DEVICE_ID_MPC8543		0x0015
+#define PCI_DEVICE_ID_MPC8547E		0x0018
+#define PCI_DEVICE_ID_MPC8545E		0x0019
+#define PCI_DEVICE_ID_MPC8545		0x001a
+#define PCI_DEVICE_ID_MPC8569E		0x0061
+#define PCI_DEVICE_ID_MPC8569		0x0060
+#define PCI_DEVICE_ID_MPC8568E		0x0020
+#define PCI_DEVICE_ID_MPC8568		0x0021
+#define PCI_DEVICE_ID_MPC8567E		0x0022
+#define PCI_DEVICE_ID_MPC8567		0x0023
+#define PCI_DEVICE_ID_MPC8533E		0x0030
+#define PCI_DEVICE_ID_MPC8533		0x0031
+#define PCI_DEVICE_ID_MPC8544E		0x0032
+#define PCI_DEVICE_ID_MPC8544		0x0033
+#define PCI_DEVICE_ID_MPC8572E		0x0040
+#define PCI_DEVICE_ID_MPC8572		0x0041
+#define PCI_DEVICE_ID_MPC8536E		0x0050
+#define PCI_DEVICE_ID_MPC8536		0x0051
+#define PCI_DEVICE_ID_P2020E		0x0070
+#define PCI_DEVICE_ID_P2020		0x0071
+#define PCI_DEVICE_ID_P2010E		0x0078
+#define PCI_DEVICE_ID_P2010		0x0079
+#define PCI_DEVICE_ID_P1020E		0x0100
+#define PCI_DEVICE_ID_P1020		0x0101
+#define PCI_DEVICE_ID_P1021E		0x0102
+#define PCI_DEVICE_ID_P1021		0x0103
+#define PCI_DEVICE_ID_P1011E		0x0108
+#define PCI_DEVICE_ID_P1011		0x0109
+#define PCI_DEVICE_ID_P1022E		0x0110
+#define PCI_DEVICE_ID_P1022		0x0111
+#define PCI_DEVICE_ID_P1013E		0x0118
+#define PCI_DEVICE_ID_P1013		0x0119
+#define PCI_DEVICE_ID_P4080E		0x0400
+#define PCI_DEVICE_ID_P4080		0x0401
+#define PCI_DEVICE_ID_P4040E		0x0408
+#define PCI_DEVICE_ID_P4040		0x0409
+#define PCI_DEVICE_ID_P2040E		0x0410
+#define PCI_DEVICE_ID_P2040		0x0411
+#define PCI_DEVICE_ID_P3041E		0x041E
+#define PCI_DEVICE_ID_P3041		0x041F
+#define PCI_DEVICE_ID_P5020E		0x0420
+#define PCI_DEVICE_ID_P5020		0x0421
+#define PCI_DEVICE_ID_P5010E		0x0428
+#define PCI_DEVICE_ID_P5010		0x0429
+#define PCI_DEVICE_ID_MPC8641		0x7010
+#define PCI_DEVICE_ID_MPC8641D		0x7011
+#define PCI_DEVICE_ID_MPC8610		0x7018
+
+#define PCI_VENDOR_ID_PASEMI		0x1959
+
+#define PCI_VENDOR_ID_ATTANSIC		0x1969
+#define PCI_DEVICE_ID_ATTANSIC_L1	0x1048
+#define PCI_DEVICE_ID_ATTANSIC_L2	0x2048
+
+#define PCI_VENDOR_ID_JMICRON		0x197B
+#define PCI_DEVICE_ID_JMICRON_JMB360	0x2360
+#define PCI_DEVICE_ID_JMICRON_JMB361	0x2361
+#define PCI_DEVICE_ID_JMICRON_JMB362	0x2362
+#define PCI_DEVICE_ID_JMICRON_JMB363	0x2363
+#define PCI_DEVICE_ID_JMICRON_JMB364	0x2364
+#define PCI_DEVICE_ID_JMICRON_JMB365	0x2365
+#define PCI_DEVICE_ID_JMICRON_JMB366	0x2366
+#define PCI_DEVICE_ID_JMICRON_JMB368	0x2368
+#define PCI_DEVICE_ID_JMICRON_JMB369	0x2369
+#define PCI_DEVICE_ID_JMICRON_JMB38X_SD	0x2381
+#define PCI_DEVICE_ID_JMICRON_JMB38X_MMC 0x2382
+#define PCI_DEVICE_ID_JMICRON_JMB38X_MS	0x2383
+#define PCI_DEVICE_ID_JMICRON_JMB385_MS	0x2388
+#define PCI_DEVICE_ID_JMICRON_JMB388_SD	0x2391
+#define PCI_DEVICE_ID_JMICRON_JMB388_ESD 0x2392
+#define PCI_DEVICE_ID_JMICRON_JMB390_MS	0x2393
+
+#define PCI_VENDOR_ID_KORENIX		0x1982
+#define PCI_DEVICE_ID_KORENIX_JETCARDF0	0x1600
+#define PCI_DEVICE_ID_KORENIX_JETCARDF1	0x16ff
+#define PCI_DEVICE_ID_KORENIX_JETCARDF2	0x1700
+#define PCI_DEVICE_ID_KORENIX_JETCARDF3	0x17ff
+
+#define PCI_VENDOR_ID_QMI		0x1a32
+
+#define PCI_VENDOR_ID_AZWAVE		0x1a3b
+
+#define PCI_VENDOR_ID_TEKRAM		0x1de1
+#define PCI_DEVICE_ID_TEKRAM_DC290	0xdc29
+
+#define PCI_VENDOR_ID_TEHUTI		0x1fc9
+#define PCI_DEVICE_ID_TEHUTI_3009	0x3009
+#define PCI_DEVICE_ID_TEHUTI_3010	0x3010
+#define PCI_DEVICE_ID_TEHUTI_3014	0x3014
+
+#define PCI_VENDOR_ID_HINT             0x3388
+#define PCI_DEVICE_ID_HINT_VXPROII_IDE 0x8013
+
+#define PCI_VENDOR_ID_3DLABS		0x3d3d
+#define PCI_DEVICE_ID_3DLABS_PERMEDIA2	0x0007
+#define PCI_DEVICE_ID_3DLABS_PERMEDIA2V	0x0009
+
+#define PCI_VENDOR_ID_NETXEN		0x4040
+#define PCI_DEVICE_ID_NX2031_10GXSR	0x0001
+#define PCI_DEVICE_ID_NX2031_10GCX4	0x0002
+#define PCI_DEVICE_ID_NX2031_4GCU	0x0003
+#define PCI_DEVICE_ID_NX2031_IMEZ	0x0004
+#define PCI_DEVICE_ID_NX2031_HMEZ	0x0005
+#define PCI_DEVICE_ID_NX2031_XG_MGMT	0x0024
+#define PCI_DEVICE_ID_NX2031_XG_MGMT2	0x0025
+#define PCI_DEVICE_ID_NX3031		0x0100
+
+#define PCI_VENDOR_ID_AKS		0x416c
+#define PCI_DEVICE_ID_AKS_ALADDINCARD	0x0100
+
+#define PCI_VENDOR_ID_ACCESSIO		0x494f
+#define PCI_DEVICE_ID_ACCESSIO_WDG_CSM	0x22c0
+
+#define PCI_VENDOR_ID_S3		0x5333
+#define PCI_DEVICE_ID_S3_TRIO		0x8811
+#define PCI_DEVICE_ID_S3_868		0x8880
+#define PCI_DEVICE_ID_S3_968		0x88f0
+#define PCI_DEVICE_ID_S3_SAVAGE4	0x8a25
+#define PCI_DEVICE_ID_S3_PROSAVAGE8	0x8d04
+#define PCI_DEVICE_ID_S3_SONICVIBES	0xca00
+
+#define PCI_VENDOR_ID_DUNORD		0x5544
+#define PCI_DEVICE_ID_DUNORD_I3000	0x0001
+
+#define PCI_VENDOR_ID_DCI		0x6666
+#define PCI_DEVICE_ID_DCI_PCCOM4	0x0001
+#define PCI_DEVICE_ID_DCI_PCCOM8	0x0002
+#define PCI_DEVICE_ID_DCI_PCCOM2	0x0004
+
+#define PCI_VENDOR_ID_INTEL		0x8086
+#define PCI_DEVICE_ID_INTEL_EESSC	0x0008
+#define PCI_DEVICE_ID_INTEL_PXHD_0	0x0320
+#define PCI_DEVICE_ID_INTEL_PXHD_1	0x0321
+#define PCI_DEVICE_ID_INTEL_PXH_0	0x0329
+#define PCI_DEVICE_ID_INTEL_PXH_1	0x032A
+#define PCI_DEVICE_ID_INTEL_PXHV	0x032C
+#define PCI_DEVICE_ID_INTEL_80332_0	0x0330
+#define PCI_DEVICE_ID_INTEL_80332_1	0x0332
+#define PCI_DEVICE_ID_INTEL_80333_0	0x0370
+#define PCI_DEVICE_ID_INTEL_80333_1	0x0372
+#define PCI_DEVICE_ID_INTEL_82375	0x0482
+#define PCI_DEVICE_ID_INTEL_82424	0x0483
+#define PCI_DEVICE_ID_INTEL_82378	0x0484
+#define PCI_DEVICE_ID_INTEL_MRST_SD0	0x0807
+#define PCI_DEVICE_ID_INTEL_MRST_SD1	0x0808
+#define PCI_DEVICE_ID_INTEL_MFD_SD	0x0820
+#define PCI_DEVICE_ID_INTEL_MFD_SDIO1	0x0821
+#define PCI_DEVICE_ID_INTEL_MFD_SDIO2	0x0822
+#define PCI_DEVICE_ID_INTEL_MFD_EMMC0	0x0823
+#define PCI_DEVICE_ID_INTEL_MFD_EMMC1	0x0824
+#define PCI_DEVICE_ID_INTEL_MRST_SD2	0x084F
+#define PCI_DEVICE_ID_INTEL_I960	0x0960
+#define PCI_DEVICE_ID_INTEL_I960RM	0x0962
+#define PCI_DEVICE_ID_INTEL_82541ER	0x1078
+#define PCI_DEVICE_ID_INTEL_82541GI_LF	0x107c
+#define PCI_DEVICE_ID_INTEL_82542	0x1000
+#define PCI_DEVICE_ID_INTEL_82543GC_FIBER	0x1001
+#define PCI_DEVICE_ID_INTEL_82543GC_COPPER	0x1004
+#define PCI_DEVICE_ID_INTEL_82544EI_COPPER	0x1008
+#define PCI_DEVICE_ID_INTEL_82544EI_FIBER	0x1009
+#define PCI_DEVICE_ID_INTEL_82544GC_COPPER	0x100C
+#define PCI_DEVICE_ID_INTEL_82544GC_LOM		0x100D
+#define PCI_DEVICE_ID_INTEL_82540EM		0x100E
+#define PCI_DEVICE_ID_INTEL_82545EM_COPPER	0x100F
+#define PCI_DEVICE_ID_INTEL_82546EB_COPPER	0x1010
+#define PCI_DEVICE_ID_INTEL_82545EM_FIBER	0x1011
+#define PCI_DEVICE_ID_INTEL_82546EB_FIBER	0x1012
+#define PCI_DEVICE_ID_INTEL_82546GB_COPPER	0x1079
+#define PCI_DEVICE_ID_INTEL_82540EM_LOM		0x1015
+#define PCI_DEVICE_ID_INTEL_82545GM_COPPER	0x1026
+#define PCI_DEVICE_ID_INTEL_82559		0x1030
+#define PCI_DEVICE_ID_INTEL_82559ER		0x1209
+#define PCI_DEVICE_ID_INTEL_82557		0x1229
+
+#define PCI_DEVICE_ID_INTEL_82562ET	0x1031
+
+#define PCI_DEVICE_ID_INTEL_82571EB_COPPER      0x105E
+#define PCI_DEVICE_ID_INTEL_82571EB_FIBER       0x105F
+#define PCI_DEVICE_ID_INTEL_82571EB_SERDES      0x1060
+#define PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER 0x10A4
+#define PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER 0x10D5
+#define PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER  0x10A5
+#define PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE  0x10BC
+#define PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL 0x10D9
+#define PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD 0x10DA
+#define PCI_DEVICE_ID_INTEL_82572EI_COPPER      0x107D
+#define PCI_DEVICE_ID_INTEL_82572EI_FIBER       0x107E
+#define PCI_DEVICE_ID_INTEL_82572EI_SERDES      0x107F
+#define PCI_DEVICE_ID_INTEL_82572EI             0x10B9
+#define PCI_DEVICE_ID_INTEL_82573E              0x108B
+#define PCI_DEVICE_ID_INTEL_82573E_IAMT         0x108C
+#define PCI_DEVICE_ID_INTEL_82573L              0x109A
+#define PCI_DEVICE_ID_INTEL_82574L              0x10D3
+#define PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3 0x10B5
+#define PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT     0x1096
+#define PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT     0x1098
+#define PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT     0x10BA
+#define PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT     0x10BB
+
+#define PCI_DEVICE_ID_INTEL_8257X_SOL	0x1062
+#define PCI_DEVICE_ID_INTEL_82573E_SOL	0x1085
+#define PCI_DEVICE_ID_INTEL_82573L_SOL	0x108F
+#define PCI_DEVICE_ID_INTEL_82815_MC	0x1130
+#define PCI_DEVICE_ID_INTEL_82815_CGC	0x1132
+#define PCI_DEVICE_ID_INTEL_82092AA_0	0x1221
+#define PCI_DEVICE_ID_INTEL_7505_0	0x2550
+#define PCI_DEVICE_ID_INTEL_7205_0	0x255d
+#define PCI_DEVICE_ID_INTEL_82437	0x122d
+#define PCI_DEVICE_ID_INTEL_82371FB_0	0x122e
+#define PCI_DEVICE_ID_INTEL_82371FB_1	0x1230
+#define PCI_DEVICE_ID_INTEL_82371MX	0x1234
+#define PCI_DEVICE_ID_INTEL_82441	0x1237
+#define PCI_DEVICE_ID_INTEL_82380FB	0x124b
+#define PCI_DEVICE_ID_INTEL_82439	0x1250
+#define PCI_DEVICE_ID_INTEL_80960_RP	0x1960
+#define PCI_DEVICE_ID_INTEL_82840_HB	0x1a21
+#define PCI_DEVICE_ID_INTEL_82845_HB	0x1a30
+#define PCI_DEVICE_ID_INTEL_IOAT	0x1a38
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE	0x1c03
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6	0x1c02
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_HDA	0x1c20
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS	0x1c22
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN	0x1c41
+#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX	0x1c5f
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE	0x1e03
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_HDA	0x1e20
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN 0x1e41
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX 0x1e5f
+#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS	0x1d22
+#define PCI_DEVICE_ID_INTEL_PATSBURG_LPC	0x1d40
+#define PCI_DEVICE_ID_INTEL_82801AA_0	0x2410
+#define PCI_DEVICE_ID_INTEL_82801AA_1	0x2411
+#define PCI_DEVICE_ID_INTEL_82801AA_3	0x2413
+#define PCI_DEVICE_ID_INTEL_82801AA_5	0x2415
+#define PCI_DEVICE_ID_INTEL_82801AA_6	0x2416
+#define PCI_DEVICE_ID_INTEL_82801AA_8	0x2418
+#define PCI_DEVICE_ID_INTEL_82801AB_0	0x2420
+#define PCI_DEVICE_ID_INTEL_82801AB_1	0x2421
+#define PCI_DEVICE_ID_INTEL_82801AB_3	0x2423
+#define PCI_DEVICE_ID_INTEL_82801AB_5	0x2425
+#define PCI_DEVICE_ID_INTEL_82801AB_6	0x2426
+#define PCI_DEVICE_ID_INTEL_82801AB_8	0x2428
+#define PCI_DEVICE_ID_INTEL_82801BA_0	0x2440
+#define PCI_DEVICE_ID_INTEL_82801BA_2	0x2443
+#define PCI_DEVICE_ID_INTEL_82801BA_4	0x2445
+#define PCI_DEVICE_ID_INTEL_82801BA_6	0x2448
+#define PCI_DEVICE_ID_INTEL_82801BA_8	0x244a
+#define PCI_DEVICE_ID_INTEL_82801BA_9	0x244b
+#define PCI_DEVICE_ID_INTEL_82801BA_10	0x244c
+#define PCI_DEVICE_ID_INTEL_82801BA_11	0x244e
+#define PCI_DEVICE_ID_INTEL_82801E_0	0x2450
+#define PCI_DEVICE_ID_INTEL_82801E_11	0x245b
+#define PCI_DEVICE_ID_INTEL_82801CA_0	0x2480
+#define PCI_DEVICE_ID_INTEL_82801CA_3	0x2483
+#define PCI_DEVICE_ID_INTEL_82801CA_5	0x2485
+#define PCI_DEVICE_ID_INTEL_82801CA_6	0x2486
+#define PCI_DEVICE_ID_INTEL_82801CA_10	0x248a
+#define PCI_DEVICE_ID_INTEL_82801CA_11	0x248b
+#define PCI_DEVICE_ID_INTEL_82801CA_12	0x248c
+#define PCI_DEVICE_ID_INTEL_82801DB_0	0x24c0
+#define PCI_DEVICE_ID_INTEL_82801DB_1	0x24c1
+#define PCI_DEVICE_ID_INTEL_82801DB_2	0x24c2
+#define PCI_DEVICE_ID_INTEL_82801DB_3	0x24c3
+#define PCI_DEVICE_ID_INTEL_82801DB_5	0x24c5
+#define PCI_DEVICE_ID_INTEL_82801DB_6	0x24c6
+#define PCI_DEVICE_ID_INTEL_82801DB_9	0x24c9
+#define PCI_DEVICE_ID_INTEL_82801DB_10	0x24ca
+#define PCI_DEVICE_ID_INTEL_82801DB_11	0x24cb
+#define PCI_DEVICE_ID_INTEL_82801DB_12  0x24cc
+#define PCI_DEVICE_ID_INTEL_82801EB_0	0x24d0
+#define PCI_DEVICE_ID_INTEL_82801EB_1	0x24d1
+#define PCI_DEVICE_ID_INTEL_82801EB_3	0x24d3
+#define PCI_DEVICE_ID_INTEL_82801EB_5	0x24d5
+#define PCI_DEVICE_ID_INTEL_82801EB_6	0x24d6
+#define PCI_DEVICE_ID_INTEL_82801EB_11	0x24db
+#define PCI_DEVICE_ID_INTEL_82801EB_12	0x24dc
+#define PCI_DEVICE_ID_INTEL_82801EB_13	0x24dd
+#define PCI_DEVICE_ID_INTEL_ESB_1	0x25a1
+#define PCI_DEVICE_ID_INTEL_ESB_2	0x25a2
+#define PCI_DEVICE_ID_INTEL_ESB_4	0x25a4
+#define PCI_DEVICE_ID_INTEL_ESB_5	0x25a6
+#define PCI_DEVICE_ID_INTEL_ESB_9	0x25ab
+#define PCI_DEVICE_ID_INTEL_ESB_10	0x25ac
+#define PCI_DEVICE_ID_INTEL_82820_HB	0x2500
+#define PCI_DEVICE_ID_INTEL_82820_UP_HB	0x2501
+#define PCI_DEVICE_ID_INTEL_82850_HB	0x2530
+#define PCI_DEVICE_ID_INTEL_82860_HB	0x2531
+#define PCI_DEVICE_ID_INTEL_E7501_MCH	0x254c
+#define PCI_DEVICE_ID_INTEL_82845G_HB	0x2560
+#define PCI_DEVICE_ID_INTEL_82845G_IG	0x2562
+#define PCI_DEVICE_ID_INTEL_82865_HB	0x2570
+#define PCI_DEVICE_ID_INTEL_82865_IG	0x2572
+#define PCI_DEVICE_ID_INTEL_82875_HB	0x2578
+#define PCI_DEVICE_ID_INTEL_82915G_HB	0x2580
+#define PCI_DEVICE_ID_INTEL_82915G_IG	0x2582
+#define PCI_DEVICE_ID_INTEL_82915GM_HB	0x2590
+#define PCI_DEVICE_ID_INTEL_82915GM_IG	0x2592
+#define PCI_DEVICE_ID_INTEL_5000_ERR	0x25F0
+#define PCI_DEVICE_ID_INTEL_5000_FBD0	0x25F5
+#define PCI_DEVICE_ID_INTEL_5000_FBD1	0x25F6
+#define PCI_DEVICE_ID_INTEL_82945G_HB	0x2770
+#define PCI_DEVICE_ID_INTEL_82945G_IG	0x2772
+#define PCI_DEVICE_ID_INTEL_3000_HB	0x2778
+#define PCI_DEVICE_ID_INTEL_82945GM_HB	0x27A0
+#define PCI_DEVICE_ID_INTEL_82945GM_IG	0x27A2
+#define PCI_DEVICE_ID_INTEL_ICH6_0	0x2640
+#define PCI_DEVICE_ID_INTEL_ICH6_1	0x2641
+#define PCI_DEVICE_ID_INTEL_ICH6_2	0x2642
+#define PCI_DEVICE_ID_INTEL_ICH6_16	0x266a
+#define PCI_DEVICE_ID_INTEL_ICH6_17	0x266d
+#define PCI_DEVICE_ID_INTEL_ICH6_18	0x266e
+#define PCI_DEVICE_ID_INTEL_ICH6_19	0x266f
+#define PCI_DEVICE_ID_INTEL_ESB2_0	0x2670
+#define PCI_DEVICE_ID_INTEL_ESB2_14	0x2698
+#define PCI_DEVICE_ID_INTEL_ESB2_17	0x269b
+#define PCI_DEVICE_ID_INTEL_ESB2_18	0x269e
+#define PCI_DEVICE_ID_INTEL_ICH7_0	0x27b8
+#define PCI_DEVICE_ID_INTEL_ICH7_1	0x27b9
+#define PCI_DEVICE_ID_INTEL_ICH7_30	0x27b0
+#define PCI_DEVICE_ID_INTEL_TGP_LPC	0x27bc
+#define PCI_DEVICE_ID_INTEL_ICH7_31	0x27bd
+#define PCI_DEVICE_ID_INTEL_NM10_AHCI	0x27c1
+#define PCI_DEVICE_ID_INTEL_ICH7_17	0x27da
+#define PCI_DEVICE_ID_INTEL_ICH7_19	0x27dd
+#define PCI_DEVICE_ID_INTEL_ICH7_20	0x27de
+#define PCI_DEVICE_ID_INTEL_ICH7_21	0x27df
+#define PCI_DEVICE_ID_INTEL_ICH8_0	0x2810
+#define PCI_DEVICE_ID_INTEL_ICH8_1	0x2811
+#define PCI_DEVICE_ID_INTEL_ICH8_2	0x2812
+#define PCI_DEVICE_ID_INTEL_ICH8_3	0x2814
+#define PCI_DEVICE_ID_INTEL_ICH8_4	0x2815
+#define PCI_DEVICE_ID_INTEL_ICH8_5	0x283e
+#define PCI_DEVICE_ID_INTEL_ICH8_6	0x2850
+#define PCI_DEVICE_ID_INTEL_ICH9_0	0x2910
+#define PCI_DEVICE_ID_INTEL_ICH9_1	0x2917
+#define PCI_DEVICE_ID_INTEL_ICH9_2	0x2912
+#define PCI_DEVICE_ID_INTEL_ICH9_3	0x2913
+#define PCI_DEVICE_ID_INTEL_ICH9_4	0x2914
+#define PCI_DEVICE_ID_INTEL_ICH9_5	0x2919
+#define PCI_DEVICE_ID_INTEL_ICH9_6	0x2930
+#define PCI_DEVICE_ID_INTEL_ICH9_7	0x2916
+#define PCI_DEVICE_ID_INTEL_ICH9_8	0x2918
+#define PCI_DEVICE_ID_INTEL_I7_MCR	0x2c18
+#define PCI_DEVICE_ID_INTEL_I7_MC_TAD	0x2c19
+#define PCI_DEVICE_ID_INTEL_I7_MC_RAS	0x2c1a
+#define PCI_DEVICE_ID_INTEL_I7_MC_TEST	0x2c1c
+#define PCI_DEVICE_ID_INTEL_I7_MC_CH0_CTRL  0x2c20
+#define PCI_DEVICE_ID_INTEL_I7_MC_CH0_ADDR  0x2c21
+#define PCI_DEVICE_ID_INTEL_I7_MC_CH0_RANK  0x2c22
+#define PCI_DEVICE_ID_INTEL_I7_MC_CH0_TC    0x2c23
+#define PCI_DEVICE_ID_INTEL_I7_MC_CH1_CTRL  0x2c28
+#define PCI_DEVICE_ID_INTEL_I7_MC_CH1_ADDR  0x2c29
+#define PCI_DEVICE_ID_INTEL_I7_MC_CH1_RANK  0x2c2a
+#define PCI_DEVICE_ID_INTEL_I7_MC_CH1_TC    0x2c2b
+#define PCI_DEVICE_ID_INTEL_I7_MC_CH2_CTRL  0x2c30
+#define PCI_DEVICE_ID_INTEL_I7_MC_CH2_ADDR  0x2c31
+#define PCI_DEVICE_ID_INTEL_I7_MC_CH2_RANK  0x2c32
+#define PCI_DEVICE_ID_INTEL_I7_MC_CH2_TC    0x2c33
+#define PCI_DEVICE_ID_INTEL_I7_NONCORE	0x2c41
+#define PCI_DEVICE_ID_INTEL_I7_NONCORE_ALT 0x2c40
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE     0x2c50
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_ALT 0x2c51
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_REV2 0x2c70
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_SAD         0x2c81
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_QPI_LINK0   0x2c90
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_QPI_PHY0    0x2c91
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR         0x2c98
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD      0x2c99
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST     0x2c9C
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL 0x2ca0
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR 0x2ca1
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK 0x2ca2
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC   0x2ca3
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL 0x2ca8
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR 0x2ca9
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK 0x2caa
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC   0x2cab
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR_REV2          0x2d98
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD_REV2       0x2d99
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_RAS_REV2       0x2d9a
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST_REV2      0x2d9c
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL_REV2  0x2da0
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR_REV2  0x2da1
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK_REV2  0x2da2
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC_REV2    0x2da3
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL_REV2  0x2da8
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR_REV2  0x2da9
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK_REV2  0x2daa
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC_REV2    0x2dab
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_CTRL_REV2  0x2db0
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_ADDR_REV2  0x2db1
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_RANK_REV2  0x2db2
+#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_TC_REV2    0x2db3
+#define PCI_DEVICE_ID_INTEL_82855PM_HB	0x3340
+#define PCI_DEVICE_ID_INTEL_IOAT_TBG4	0x3429
+#define PCI_DEVICE_ID_INTEL_IOAT_TBG5	0x342a
+#define PCI_DEVICE_ID_INTEL_IOAT_TBG6	0x342b
+#define PCI_DEVICE_ID_INTEL_IOAT_TBG7	0x342c
+#define PCI_DEVICE_ID_INTEL_X58_HUB_MGMT 0x342e
+#define PCI_DEVICE_ID_INTEL_IOAT_TBG0	0x3430
+#define PCI_DEVICE_ID_INTEL_IOAT_TBG1	0x3431
+#define PCI_DEVICE_ID_INTEL_IOAT_TBG2	0x3432
+#define PCI_DEVICE_ID_INTEL_IOAT_TBG3	0x3433
+#define PCI_DEVICE_ID_INTEL_82830_HB	0x3575
+#define PCI_DEVICE_ID_INTEL_82830_CGC	0x3577
+#define PCI_DEVICE_ID_INTEL_82854_HB	0x358c
+#define PCI_DEVICE_ID_INTEL_82854_IG	0x358e
+#define PCI_DEVICE_ID_INTEL_82855GM_HB	0x3580
+#define PCI_DEVICE_ID_INTEL_82855GM_IG	0x3582
+#define PCI_DEVICE_ID_INTEL_E7520_MCH	0x3590
+#define PCI_DEVICE_ID_INTEL_E7320_MCH	0x3592
+#define PCI_DEVICE_ID_INTEL_MCH_PA	0x3595
+#define PCI_DEVICE_ID_INTEL_MCH_PA1	0x3596
+#define PCI_DEVICE_ID_INTEL_MCH_PB	0x3597
+#define PCI_DEVICE_ID_INTEL_MCH_PB1	0x3598
+#define PCI_DEVICE_ID_INTEL_MCH_PC	0x3599
+#define PCI_DEVICE_ID_INTEL_MCH_PC1	0x359a
+#define PCI_DEVICE_ID_INTEL_E7525_MCH	0x359e
+#define PCI_DEVICE_ID_INTEL_I7300_MCH_ERR 0x360c
+#define PCI_DEVICE_ID_INTEL_I7300_MCH_FB0 0x360f
+#define PCI_DEVICE_ID_INTEL_I7300_MCH_FB1 0x3610
+#define PCI_DEVICE_ID_INTEL_IOAT_CNB	0x360b
+#define PCI_DEVICE_ID_INTEL_FBD_CNB	0x360c
+#define PCI_DEVICE_ID_INTEL_IOAT_JSF0	0x3710
+#define PCI_DEVICE_ID_INTEL_IOAT_JSF1	0x3711
+#define PCI_DEVICE_ID_INTEL_IOAT_JSF2	0x3712
+#define PCI_DEVICE_ID_INTEL_IOAT_JSF3	0x3713
+#define PCI_DEVICE_ID_INTEL_IOAT_JSF4	0x3714
+#define PCI_DEVICE_ID_INTEL_IOAT_JSF5	0x3715
+#define PCI_DEVICE_ID_INTEL_IOAT_JSF6	0x3716
+#define PCI_DEVICE_ID_INTEL_IOAT_JSF7	0x3717
+#define PCI_DEVICE_ID_INTEL_IOAT_JSF8	0x3718
+#define PCI_DEVICE_ID_INTEL_IOAT_JSF9	0x3719
+#define PCI_DEVICE_ID_INTEL_ICH10_0	0x3a14
+#define PCI_DEVICE_ID_INTEL_ICH10_1	0x3a16
+#define PCI_DEVICE_ID_INTEL_ICH10_2	0x3a18
+#define PCI_DEVICE_ID_INTEL_ICH10_3	0x3a1a
+#define PCI_DEVICE_ID_INTEL_ICH10_4	0x3a30
+#define PCI_DEVICE_ID_INTEL_ICH10_5	0x3a60
+#define PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MIN	0x3b00
+#define PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MAX	0x3b1f
+#define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS	0x3b30
+#define PCI_DEVICE_ID_INTEL_IOAT_SNB	0x402f
+#define PCI_DEVICE_ID_INTEL_5100_16	0x65f0
+#define PCI_DEVICE_ID_INTEL_5100_21	0x65f5
+#define PCI_DEVICE_ID_INTEL_5100_22	0x65f6
+#define PCI_DEVICE_ID_INTEL_5400_ERR	0x4030
+#define PCI_DEVICE_ID_INTEL_5400_FBD0	0x4035
+#define PCI_DEVICE_ID_INTEL_5400_FBD1	0x4036
+#define PCI_DEVICE_ID_INTEL_IOAT_SCNB	0x65ff
+#define PCI_DEVICE_ID_INTEL_EP80579_0	0x5031
+#define PCI_DEVICE_ID_INTEL_EP80579_1	0x5032
+#define PCI_DEVICE_ID_INTEL_82371SB_0	0x7000
+#define PCI_DEVICE_ID_INTEL_82371SB_1	0x7010
+#define PCI_DEVICE_ID_INTEL_82371SB_2	0x7020
+#define PCI_DEVICE_ID_INTEL_82437VX	0x7030
+#define PCI_DEVICE_ID_INTEL_82439TX	0x7100
+#define PCI_DEVICE_ID_INTEL_82371AB_0	0x7110
+#define PCI_DEVICE_ID_INTEL_82371AB	0x7111
+#define PCI_DEVICE_ID_INTEL_82371AB_2	0x7112
+#define PCI_DEVICE_ID_INTEL_82371AB_3	0x7113
+#define PCI_DEVICE_ID_INTEL_82810_MC1	0x7120
+#define PCI_DEVICE_ID_INTEL_82810_IG1	0x7121
+#define PCI_DEVICE_ID_INTEL_82810_MC3	0x7122
+#define PCI_DEVICE_ID_INTEL_82810_IG3	0x7123
+#define PCI_DEVICE_ID_INTEL_82810E_MC	0x7124
+#define PCI_DEVICE_ID_INTEL_82810E_IG	0x7125
+#define PCI_DEVICE_ID_INTEL_82443LX_0	0x7180
+#define PCI_DEVICE_ID_INTEL_82443LX_1	0x7181
+#define PCI_DEVICE_ID_INTEL_82443BX_0	0x7190
+#define PCI_DEVICE_ID_INTEL_82443BX_1	0x7191
+#define PCI_DEVICE_ID_INTEL_82443BX_2	0x7192
+#define PCI_DEVICE_ID_INTEL_440MX	0x7195
+#define PCI_DEVICE_ID_INTEL_440MX_6	0x7196
+#define PCI_DEVICE_ID_INTEL_82443MX_0	0x7198
+#define PCI_DEVICE_ID_INTEL_82443MX_1	0x7199
+#define PCI_DEVICE_ID_INTEL_82443MX_3	0x719b
+#define PCI_DEVICE_ID_INTEL_82443GX_0	0x71a0
+#define PCI_DEVICE_ID_INTEL_82443GX_2	0x71a2
+#define PCI_DEVICE_ID_INTEL_82372FB_1	0x7601
+#define PCI_DEVICE_ID_INTEL_SCH_LPC	0x8119
+#define PCI_DEVICE_ID_INTEL_SCH_IDE	0x811a
+#define PCI_DEVICE_ID_INTEL_82454GX	0x84c4
+#define PCI_DEVICE_ID_INTEL_82450GX	0x84c5
+#define PCI_DEVICE_ID_INTEL_82451NX	0x84ca
+#define PCI_DEVICE_ID_INTEL_82454NX     0x84cb
+#define PCI_DEVICE_ID_INTEL_84460GX	0x84ea
+#define PCI_DEVICE_ID_INTEL_IXP4XX	0x8500
+#define PCI_DEVICE_ID_INTEL_IXP2800	0x9004
+#define PCI_DEVICE_ID_INTEL_S21152BB	0xb152
+
+#define PCI_VENDOR_ID_SCALEMP		0x8686
+#define PCI_DEVICE_ID_SCALEMP_VSMP_CTL	0x1010
+
+#define PCI_VENDOR_ID_COMPUTONE		0x8e0e
+#define PCI_DEVICE_ID_COMPUTONE_IP2EX	0x0291
+#define PCI_DEVICE_ID_COMPUTONE_PG	0x0302
+#define PCI_SUBVENDOR_ID_COMPUTONE	0x8e0e
+#define PCI_SUBDEVICE_ID_COMPUTONE_PG4	0x0001
+#define PCI_SUBDEVICE_ID_COMPUTONE_PG8	0x0002
+#define PCI_SUBDEVICE_ID_COMPUTONE_PG6	0x0003
+
+#define PCI_VENDOR_ID_KTI		0x8e2e
+
+#define PCI_VENDOR_ID_ADAPTEC		0x9004
+#define PCI_DEVICE_ID_ADAPTEC_7810	0x1078
+#define PCI_DEVICE_ID_ADAPTEC_7821	0x2178
+#define PCI_DEVICE_ID_ADAPTEC_38602	0x3860
+#define PCI_DEVICE_ID_ADAPTEC_7850	0x5078
+#define PCI_DEVICE_ID_ADAPTEC_7855	0x5578
+#define PCI_DEVICE_ID_ADAPTEC_3860	0x6038
+#define PCI_DEVICE_ID_ADAPTEC_1480A	0x6075
+#define PCI_DEVICE_ID_ADAPTEC_7860	0x6078
+#define PCI_DEVICE_ID_ADAPTEC_7861	0x6178
+#define PCI_DEVICE_ID_ADAPTEC_7870	0x7078
+#define PCI_DEVICE_ID_ADAPTEC_7871	0x7178
+#define PCI_DEVICE_ID_ADAPTEC_7872	0x7278
+#define PCI_DEVICE_ID_ADAPTEC_7873	0x7378
+#define PCI_DEVICE_ID_ADAPTEC_7874	0x7478
+#define PCI_DEVICE_ID_ADAPTEC_7895	0x7895
+#define PCI_DEVICE_ID_ADAPTEC_7880	0x8078
+#define PCI_DEVICE_ID_ADAPTEC_7881	0x8178
+#define PCI_DEVICE_ID_ADAPTEC_7882	0x8278
+#define PCI_DEVICE_ID_ADAPTEC_7883	0x8378
+#define PCI_DEVICE_ID_ADAPTEC_7884	0x8478
+#define PCI_DEVICE_ID_ADAPTEC_7885	0x8578
+#define PCI_DEVICE_ID_ADAPTEC_7886	0x8678
+#define PCI_DEVICE_ID_ADAPTEC_7887	0x8778
+#define PCI_DEVICE_ID_ADAPTEC_7888	0x8878
+
+#define PCI_VENDOR_ID_ADAPTEC2		0x9005
+#define PCI_DEVICE_ID_ADAPTEC2_2940U2	0x0010
+#define PCI_DEVICE_ID_ADAPTEC2_2930U2	0x0011
+#define PCI_DEVICE_ID_ADAPTEC2_7890B	0x0013
+#define PCI_DEVICE_ID_ADAPTEC2_7890	0x001f
+#define PCI_DEVICE_ID_ADAPTEC2_3940U2	0x0050
+#define PCI_DEVICE_ID_ADAPTEC2_3950U2D	0x0051
+#define PCI_DEVICE_ID_ADAPTEC2_7896	0x005f
+#define PCI_DEVICE_ID_ADAPTEC2_7892A	0x0080
+#define PCI_DEVICE_ID_ADAPTEC2_7892B	0x0081
+#define PCI_DEVICE_ID_ADAPTEC2_7892D	0x0083
+#define PCI_DEVICE_ID_ADAPTEC2_7892P	0x008f
+#define PCI_DEVICE_ID_ADAPTEC2_7899A	0x00c0
+#define PCI_DEVICE_ID_ADAPTEC2_7899B	0x00c1
+#define PCI_DEVICE_ID_ADAPTEC2_7899D	0x00c3
+#define PCI_DEVICE_ID_ADAPTEC2_7899P	0x00cf
+#define PCI_DEVICE_ID_ADAPTEC2_OBSIDIAN   0x0500
+#define PCI_DEVICE_ID_ADAPTEC2_SCAMP	0x0503
+
+#define PCI_VENDOR_ID_HOLTEK		0x9412
+#define PCI_DEVICE_ID_HOLTEK_6565	0x6565
+
+#define PCI_VENDOR_ID_NETMOS		0x9710
+#define PCI_DEVICE_ID_NETMOS_9705	0x9705
+#define PCI_DEVICE_ID_NETMOS_9715	0x9715
+#define PCI_DEVICE_ID_NETMOS_9735	0x9735
+#define PCI_DEVICE_ID_NETMOS_9745	0x9745
+#define PCI_DEVICE_ID_NETMOS_9755	0x9755
+#define PCI_DEVICE_ID_NETMOS_9805	0x9805
+#define PCI_DEVICE_ID_NETMOS_9815	0x9815
+#define PCI_DEVICE_ID_NETMOS_9835	0x9835
+#define PCI_DEVICE_ID_NETMOS_9845	0x9845
+#define PCI_DEVICE_ID_NETMOS_9855	0x9855
+#define PCI_DEVICE_ID_NETMOS_9865	0x9865
+#define PCI_DEVICE_ID_NETMOS_9901	0x9901
+
+#define PCI_VENDOR_ID_3COM_2		0xa727
+
+#define PCI_VENDOR_ID_DIGIUM		0xd161
+#define PCI_DEVICE_ID_DIGIUM_HFC4S	0xb410
+
+#define PCI_SUBVENDOR_ID_EXSYS		0xd84d
+#define PCI_SUBDEVICE_ID_EXSYS_4014	0x4014
+#define PCI_SUBDEVICE_ID_EXSYS_4055	0x4055
+
+#define PCI_VENDOR_ID_TIGERJET		0xe159
+#define PCI_DEVICE_ID_TIGERJET_300	0x0001
+#define PCI_DEVICE_ID_TIGERJET_100	0x0002
+
+#define PCI_VENDOR_ID_XILINX_RME	0xea60
+#define PCI_DEVICE_ID_RME_DIGI32	0x9896
+#define PCI_DEVICE_ID_RME_DIGI32_PRO	0x9897
+#define PCI_DEVICE_ID_RME_DIGI32_8	0x9898
+
+#define PCI_VENDOR_ID_XEN		0x5853
+#define PCI_DEVICE_ID_XEN_PLATFORM	0x0001
diff --git a/qemu/roms/u-boot/include/pci_msc01.h b/qemu/roms/u-boot/include/pci_msc01.h
new file mode 100644
index 000000000..54945a7a8
--- /dev/null
+++ b/qemu/roms/u-boot/include/pci_msc01.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2013 Imagination Technologies
+ * Author: Paul Burton <paul.burton@imgtec.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __PCI_MSC01_H__
+#define __PCI_MSC01_H__
+
+extern void msc01_pci_init(void *base, unsigned long sys_bus,
+			   unsigned long sys_phys, unsigned long sys_size,
+			   unsigned long mem_bus, unsigned long mem_phys,
+			   unsigned long mem_size, unsigned long io_bus,
+			   unsigned long io_phys, unsigned long io_size);
+
+#endif /* __PCI_MSC01_H__ */
diff --git a/qemu/roms/u-boot/include/pcmcia.h b/qemu/roms/u-boot/include/pcmcia.h
new file mode 100644
index 000000000..952a67c17
--- /dev/null
+++ b/qemu/roms/u-boot/include/pcmcia.h
@@ -0,0 +1,300 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _PCMCIA_H
+#define _PCMCIA_H
+
+#include <common.h>
+#include <config.h>
+
+/*
+ * Allow configuration to select PCMCIA slot,
+ * or try to generate a useful default
+ */
+#if defined(CONFIG_CMD_PCMCIA) || \
+    (defined(CONFIG_CMD_IDE) && \
+	(defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_DIRECT) ) )
+
+#if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
+
+					/* The RPX series use SLOT_B	*/
+#if defined(CONFIG_RPXLITE)
+# define CONFIG_PCMCIA_SLOT_B
+#elif defined(CONFIG_FADS)		/* The FADS series are a mess	*/
+# if defined(CONFIG_MPC86x) || defined(CONFIG_MPC821)
+#  define CONFIG_PCMCIA_SLOT_A
+# else
+#  define CONFIG_PCMCIA_SLOT_B
+# endif
+#elif defined(CONFIG_TQM8xxL) || defined(CONFIG_SVM_SC8xx)
+# define	CONFIG_PCMCIA_SLOT_B	/* The TQM8xxL use SLOT_B	*/
+#elif defined(CONFIG_SPD823TS)		/* The SPD8xx  use SLOT_B	*/
+# define CONFIG_PCMCIA_SLOT_B
+#elif defined(CONFIG_IVMS8) || defined(CONFIG_IVML24)	/* The IVM* use SLOT_A	*/
+# define CONFIG_PCMCIA_SLOT_A
+#elif defined(CONFIG_LWMON)		/* The LWMON  use SLOT_B	*/
+# define CONFIG_PCMCIA_SLOT_B
+#elif defined(CONFIG_ICU862)		/* The ICU862 use SLOT_B	*/
+# define CONFIG_PCMCIA_SLOT_B
+#elif defined(CONFIG_R360MPI)		/* The R360MPI use SLOT_B	*/
+# define CONFIG_PCMCIA_SLOT_B
+#elif defined(CONFIG_ATC)		/* The ATC use SLOT_A	*/
+# define CONFIG_PCMCIA_SLOT_A
+#elif defined(CONFIG_NETTA)
+# define CONFIG_PCMCIA_SLOT_A
+#elif defined(CONFIG_UC100)		/* The UC100 use SLOT_B	        */
+# define CONFIG_PCMCIA_SLOT_B
+#else
+# error "PCMCIA Slot not configured"
+#endif
+
+#endif /* !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) */
+
+/* Make sure exactly one slot is defined - we support only one for now */
+#if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
+#error Neither CONFIG_PCMCIA_SLOT_A nor CONFIG_PCMCIA_SLOT_B configured
+#endif
+#if defined(CONFIG_PCMCIA_SLOT_A) && defined(CONFIG_PCMCIA_SLOT_B)
+#error Both CONFIG_PCMCIA_SLOT_A and CONFIG_PCMCIA_SLOT_B configured
+#endif
+
+#ifndef PCMCIA_SOCKETS_NO
+#define PCMCIA_SOCKETS_NO	1
+#endif
+#ifndef PCMCIA_MEM_WIN_NO
+#define PCMCIA_MEM_WIN_NO	4
+#endif
+#define PCMCIA_IO_WIN_NO	2
+
+/* define _slot_ to be able to optimize macros */
+#ifdef CONFIG_PCMCIA_SLOT_A
+# define _slot_			0
+# define PCMCIA_SLOT_MSG	"slot A"
+# define PCMCIA_SLOT_x		PCMCIA_PSLOT_A
+#else
+# define _slot_			1
+# define PCMCIA_SLOT_MSG	"slot B"
+# define PCMCIA_SLOT_x		PCMCIA_PSLOT_B
+#endif
+
+/*
+ * The TQM850L hardware has two pins swapped! Grrrrgh!
+ */
+#ifdef	CONFIG_TQM850L
+#define __MY_PCMCIA_GCRX_CXRESET	PCMCIA_GCRX_CXOE
+#define __MY_PCMCIA_GCRX_CXOE		PCMCIA_GCRX_CXRESET
+#else
+#define __MY_PCMCIA_GCRX_CXRESET	PCMCIA_GCRX_CXRESET
+#define __MY_PCMCIA_GCRX_CXOE		PCMCIA_GCRX_CXOE
+#endif
+
+/*
+ * This structure is used to address each window in the PCMCIA controller.
+ *
+ * Keep in mind that we assume that pcmcia_win_t[n+1] is mapped directly
+ * after pcmcia_win_t[n]...
+ */
+
+typedef struct {
+	ulong	br;
+	ulong	or;
+} pcmcia_win_t;
+
+/*
+ * Definitions for PCMCIA control registers to operate in IDE mode
+ *
+ * All timing related setup (PCMCIA_SHT, PCMCIA_SST, PCMCIA_SL)
+ * to be done later (depending on CPU clock)
+ */
+
+/* Window 0:
+ *	Base: 0xFE100000	CS1
+ *	Port Size:     2 Bytes
+ *	Port Size:    16 Bit
+ *	Common Memory Space
+ */
+
+#define CONFIG_SYS_PCMCIA_PBR0		0xFE100000
+#define CONFIG_SYS_PCMCIA_POR0	    (	PCMCIA_BSIZE_2	\
+			    |	PCMCIA_PPS_16	\
+			    |	PCMCIA_PRS_MEM	\
+			    |	PCMCIA_SLOT_x	\
+			    |	PCMCIA_PV	\
+			    )
+
+/* Window 1:
+ *	Base: 0xFE100080	CS1
+ *	Port Size:     8 Bytes
+ *	Port Size:     8 Bit
+ *	Common Memory Space
+ */
+
+#define CONFIG_SYS_PCMCIA_PBR1		0xFE100080
+#define CONFIG_SYS_PCMCIA_POR1	    (	PCMCIA_BSIZE_8	\
+			    |	PCMCIA_PPS_8	\
+			    |	PCMCIA_PRS_MEM	\
+			    |	PCMCIA_SLOT_x	\
+			    |	PCMCIA_PV	\
+			    )
+
+/* Window 2:
+ *	Base: 0xFE100100	CS2
+ *	Port Size:     8 Bytes
+ *	Port Size:     8 Bit
+ *	Common Memory Space
+ */
+
+#define CONFIG_SYS_PCMCIA_PBR2		0xFE100100
+#define CONFIG_SYS_PCMCIA_POR2	    (	PCMCIA_BSIZE_8	\
+			    |	PCMCIA_PPS_8	\
+			    |	PCMCIA_PRS_MEM	\
+			    |	PCMCIA_SLOT_x	\
+			    |	PCMCIA_PV	\
+			    )
+
+/* Window 3:
+ *	not used
+ */
+#define CONFIG_SYS_PCMCIA_PBR3		0
+#define CONFIG_SYS_PCMCIA_POR3		0
+
+/* Window 4:
+ *	Base: 0xFE100C00	CS1
+ *	Port Size:     2 Bytes
+ *	Port Size:    16 Bit
+ *	Common Memory Space
+ */
+
+#define CONFIG_SYS_PCMCIA_PBR4		0xFE100C00
+#define CONFIG_SYS_PCMCIA_POR4	    (	PCMCIA_BSIZE_2	\
+			    |	PCMCIA_PPS_16	\
+			    |	PCMCIA_PRS_MEM	\
+			    |	PCMCIA_SLOT_x	\
+			    |	PCMCIA_PV	\
+			    )
+
+/* Window 5:
+ *	Base: 0xFE100C80	CS1
+ *	Port Size:     8 Bytes
+ *	Port Size:     8 Bit
+ *	Common Memory Space
+ */
+
+#define CONFIG_SYS_PCMCIA_PBR5		0xFE100C80
+#define CONFIG_SYS_PCMCIA_POR5	    (	PCMCIA_BSIZE_8	\
+			    |	PCMCIA_PPS_8	\
+			    |	PCMCIA_PRS_MEM	\
+			    |	PCMCIA_SLOT_x	\
+			    |	PCMCIA_PV	\
+			    )
+
+/* Window 6:
+ *	Base: 0xFE100D00	CS2
+ *	Port Size:     8 Bytes
+ *	Port Size:     8 Bit
+ *	Common Memory Space
+ */
+
+#define CONFIG_SYS_PCMCIA_PBR6		0xFE100D00
+#define CONFIG_SYS_PCMCIA_POR6	    (	PCMCIA_BSIZE_8	\
+			    |	PCMCIA_PPS_8	\
+			    |	PCMCIA_PRS_MEM	\
+			    |	PCMCIA_SLOT_x	\
+			    |	PCMCIA_PV	\
+			    )
+
+/* Window 7:
+ *	not used
+ */
+#define CONFIG_SYS_PCMCIA_PBR7		0
+#define CONFIG_SYS_PCMCIA_POR7		0
+
+/**********************************************************************/
+
+/*
+ * CIS Tupel codes
+ */
+#define CISTPL_NULL		0x00
+#define CISTPL_DEVICE		0x01
+#define CISTPL_LONGLINK_CB	0x02
+#define CISTPL_INDIRECT		0x03
+#define CISTPL_CONFIG_CB	0x04
+#define CISTPL_CFTABLE_ENTRY_CB 0x05
+#define CISTPL_LONGLINK_MFC	0x06
+#define CISTPL_BAR		0x07
+#define CISTPL_PWR_MGMNT	0x08
+#define CISTPL_EXTDEVICE	0x09
+#define CISTPL_CHECKSUM		0x10
+#define CISTPL_LONGLINK_A	0x11
+#define CISTPL_LONGLINK_C	0x12
+#define CISTPL_LINKTARGET	0x13
+#define CISTPL_NO_LINK		0x14
+#define CISTPL_VERS_1		0x15
+#define CISTPL_ALTSTR		0x16
+#define CISTPL_DEVICE_A		0x17
+#define CISTPL_JEDEC_C		0x18
+#define CISTPL_JEDEC_A		0x19
+#define CISTPL_CONFIG		0x1a
+#define CISTPL_CFTABLE_ENTRY	0x1b
+#define CISTPL_DEVICE_OC	0x1c
+#define CISTPL_DEVICE_OA	0x1d
+#define CISTPL_DEVICE_GEO	0x1e
+#define CISTPL_DEVICE_GEO_A	0x1f
+#define CISTPL_MANFID		0x20
+#define CISTPL_FUNCID		0x21
+#define CISTPL_FUNCE		0x22
+#define CISTPL_SWIL		0x23
+#define CISTPL_END		0xff
+
+/*
+ * CIS Function ID codes
+ */
+#define CISTPL_FUNCID_MULTI	0x00
+#define CISTPL_FUNCID_MEMORY	0x01
+#define CISTPL_FUNCID_SERIAL	0x02
+#define CISTPL_FUNCID_PARALLEL	0x03
+#define CISTPL_FUNCID_FIXED	0x04
+#define CISTPL_FUNCID_VIDEO	0x05
+#define CISTPL_FUNCID_NETWORK	0x06
+#define CISTPL_FUNCID_AIMS	0x07
+#define CISTPL_FUNCID_SCSI	0x08
+
+/*
+ * Fixed Disk FUNCE codes
+ */
+#define CISTPL_IDE_INTERFACE	0x01
+
+#define CISTPL_FUNCE_IDE_IFACE	0x01
+#define CISTPL_FUNCE_IDE_MASTER	0x02
+#define CISTPL_FUNCE_IDE_SLAVE	0x03
+
+/* First feature byte */
+#define CISTPL_IDE_SILICON	0x04
+#define CISTPL_IDE_UNIQUE	0x08
+#define CISTPL_IDE_DUAL		0x10
+
+/* Second feature byte */
+#define CISTPL_IDE_HAS_SLEEP	0x01
+#define CISTPL_IDE_HAS_STANDBY	0x02
+#define CISTPL_IDE_HAS_IDLE	0x04
+#define CISTPL_IDE_LOW_POWER	0x08
+#define CISTPL_IDE_REG_INHIBIT	0x10
+#define CISTPL_IDE_HAS_INDEX	0x20
+#define CISTPL_IDE_IOIS16	0x40
+
+#endif
+
+#ifdef	CONFIG_8xx
+extern u_int *pcmcia_pgcrx[];
+#define	PCMCIA_PGCRX(slot)	(*pcmcia_pgcrx[slot])
+#endif
+
+#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
+extern int check_ide_device(int slot);
+#endif
+
+#endif /* _PCMCIA_H */
diff --git a/qemu/roms/u-boot/include/pcmcia/cirrus.h b/qemu/roms/u-boot/include/pcmcia/cirrus.h
new file mode 100644
index 000000000..cd34dd856
--- /dev/null
+++ b/qemu/roms/u-boot/include/pcmcia/cirrus.h
@@ -0,0 +1,180 @@
+/*
+ * cirrus.h 1.4 1999/10/25 20:03:34
+ *
+ * The contents of this file are subject to the Mozilla Public License
+ * Version 1.1 (the "License"); you may not use this file except in
+ * compliance with the License. You may obtain a copy of the License
+ * at http://www.mozilla.org/MPL/
+ *
+ * Software distributed under the License is distributed on an "AS IS"
+ * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
+ * the License for the specific language governing rights and
+ * limitations under the License.
+ *
+ * The initial developer of the original code is David A. Hinds
+ * <dahinds@users.sourceforge.net>.  Portions created by David A. Hinds
+ * are Copyright (C) 1999 David A. Hinds.  All Rights Reserved.
+ *
+ * Alternatively, the contents of this file may be used under the
+ * terms of the GNU General Public License version 2 (the "GPL"), in which
+ * case the provisions of the GPL are applicable instead of the
+ * above.  If you wish to allow the use of your version of this file
+ * only under the terms of the GPL and not to allow others to use
+ * your version of this file under the MPL, indicate your decision by
+ * deleting the provisions above and replace them with the notice and
+ * other provisions required by the GPL.  If you do not delete the
+ * provisions above, a recipient may use your version of this file
+ * under either the MPL or the GPL.
+ */
+
+#ifndef _LINUX_CIRRUS_H
+#define _LINUX_CIRRUS_H
+
+#ifndef PCI_VENDOR_ID_CIRRUS
+#define PCI_VENDOR_ID_CIRRUS		0x1013
+#endif
+#ifndef PCI_DEVICE_ID_CIRRUS_6729
+#define PCI_DEVICE_ID_CIRRUS_6729	0x1100
+#endif
+#ifndef PCI_DEVICE_ID_CIRRUS_6832
+#define PCI_DEVICE_ID_CIRRUS_6832	0x1110
+#endif
+
+#define PD67_MISC_CTL_1		0x16	/* Misc control 1 */
+#define PD67_FIFO_CTL		0x17	/* FIFO control */
+#define PD67_MISC_CTL_2		0x1E	/* Misc control 2 */
+#define PD67_CHIP_INFO		0x1f	/* Chip information */
+#define PD67_ATA_CTL		0x026	/* 6730: ATA control */
+#define PD67_EXT_INDEX		0x2e	/* Extension index */
+#define PD67_EXT_DATA		0x2f	/* Extension data */
+
+/* PD6722 extension registers -- indexed in PD67_EXT_INDEX */
+#define PD67_DATA_MASK0		0x01	/* Data mask 0 */
+#define PD67_DATA_MASK1		0x02	/* Data mask 1 */
+#define PD67_DMA_CTL		0x03	/* DMA control */
+
+/* PD6730 extension registers -- indexed in PD67_EXT_INDEX */
+#define PD67_EXT_CTL_1		0x03	/* Extension control 1 */
+#define PD67_MEM_PAGE(n)	((n)+5)	/* PCI window bits 31:24 */
+#define PD67_EXTERN_DATA	0x0a
+#define PD67_MISC_CTL_3		0x25
+#define PD67_SMB_PWR_CTL	0x26
+
+/* I/O window address offset */
+#define PD67_IO_OFF(w)		(0x36+((w)<<1))
+
+/* Timing register sets */
+#define PD67_TIME_SETUP(n)	(0x3a + 3*(n))
+#define PD67_TIME_CMD(n)	(0x3b + 3*(n))
+#define PD67_TIME_RECOV(n)	(0x3c + 3*(n))
+
+/* Flags for PD67_MISC_CTL_1 */
+#define PD67_MC1_5V_DET		0x01	/* 5v detect */
+#define PD67_MC1_MEDIA_ENA	0x01	/* 6730: Multimedia enable */
+#define PD67_MC1_VCC_3V		0x02	/* 3.3v Vcc */
+#define PD67_MC1_PULSE_MGMT	0x04
+#define PD67_MC1_PULSE_IRQ	0x08
+#define PD67_MC1_SPKR_ENA	0x10
+#define PD67_MC1_INPACK_ENA	0x80
+
+/* Flags for PD67_FIFO_CTL */
+#define PD67_FIFO_EMPTY		0x80
+
+/* Flags for PD67_MISC_CTL_2 */
+#define PD67_MC2_FREQ_BYPASS	0x01
+#define PD67_MC2_DYNAMIC_MODE	0x02
+#define PD67_MC2_SUSPEND	0x04
+#define PD67_MC2_5V_CORE	0x08
+#define PD67_MC2_LED_ENA	0x10	/* IRQ 12 is LED enable */
+#define PD67_MC2_FAST_PCI	0x10	/* 6729: PCI bus > 25 MHz */
+#define PD67_MC2_3STATE_BIT7	0x20	/* Floppy change bit */
+#define PD67_MC2_DMA_MODE	0x40
+#define PD67_MC2_IRQ15_RI	0x80	/* IRQ 15 is ring enable */
+
+/* Flags for PD67_CHIP_INFO */
+#define PD67_INFO_SLOTS		0x20	/* 0 = 1 slot, 1 = 2 slots */
+#define PD67_INFO_CHIP_ID	0xc0
+#define PD67_INFO_REV		0x1c
+
+/* Fields in PD67_TIME_* registers */
+#define PD67_TIME_SCALE		0xc0
+#define PD67_TIME_SCALE_1	0x00
+#define PD67_TIME_SCALE_16	0x40
+#define PD67_TIME_SCALE_256	0x80
+#define PD67_TIME_SCALE_4096	0xc0
+#define PD67_TIME_MULT		0x3f
+
+/* Fields in PD67_DMA_CTL */
+#define PD67_DMA_MODE		0xc0
+#define PD67_DMA_OFF		0x00
+#define PD67_DMA_DREQ_INPACK	0x40
+#define PD67_DMA_DREQ_WP	0x80
+#define PD67_DMA_DREQ_BVD2	0xc0
+#define PD67_DMA_PULLUP		0x20	/* Disable socket pullups? */
+
+/* Fields in PD67_EXT_CTL_1 */
+#define PD67_EC1_VCC_PWR_LOCK	0x01
+#define PD67_EC1_AUTO_PWR_CLEAR	0x02
+#define PD67_EC1_LED_ENA	0x04
+#define PD67_EC1_INV_CARD_IRQ	0x08
+#define PD67_EC1_INV_MGMT_IRQ	0x10
+#define PD67_EC1_PULLUP_CTL	0x20
+
+/* Fields in PD67_MISC_CTL_3 */
+#define PD67_MC3_IRQ_MASK	0x03
+#define PD67_MC3_IRQ_PCPCI	0x00
+#define PD67_MC3_IRQ_EXTERN	0x01
+#define PD67_MC3_IRQ_PCIWAY	0x02
+#define PD67_MC3_IRQ_PCI	0x03
+#define PD67_MC3_PWR_MASK	0x0c
+#define PD67_MC3_PWR_SERIAL	0x00
+#define PD67_MC3_PWR_TI2202	0x08
+#define PD67_MC3_PWR_SMB	0x0c
+
+/* Register definitions for Cirrus PD6832 PCI-to-CardBus bridge */
+
+/* PD6832 extension registers -- indexed in PD67_EXT_INDEX */
+#define PD68_EXT_CTL_2			0x0b
+#define PD68_PCI_SPACE			0x22
+#define PD68_PCCARD_SPACE		0x23
+#define PD68_WINDOW_TYPE		0x24
+#define PD68_EXT_CSC			0x2e
+#define PD68_MISC_CTL_4			0x2f
+#define PD68_MISC_CTL_5			0x30
+#define PD68_MISC_CTL_6			0x31
+
+/* Extra flags in PD67_MISC_CTL_3 */
+#define PD68_MC3_HW_SUSP		0x10
+#define PD68_MC3_MM_EXPAND		0x40
+#define PD68_MC3_MM_ARM			0x80
+
+/* Bridge Control Register */
+#define  PD6832_BCR_MGMT_IRQ_ENA	0x0800
+
+/* Socket Number Register */
+#define PD6832_SOCKET_NUMBER		0x004c	/* 8 bit */
+
+
+typedef struct cirrus_state_t {
+    u_char		misc1, misc2;
+    u_char		timer[6];
+} cirrus_state_t;
+
+/* Cirrus options */
+static int has_dma = -1;
+static int has_led = -1;
+static int has_ring = -1;
+static int dynamic_mode = 0;
+static int freq_bypass = -1;
+#ifdef CONFIG_CPC45
+static int setup_time = 2;
+static int cmd_time = 6;
+static int recov_time = 1;
+#else
+static int setup_time = -1;
+static int cmd_time = -1;
+static int recov_time = -1;
+#endif
+
+
+#endif /* _LINUX_CIRRUS_H */
diff --git a/qemu/roms/u-boot/include/pcmcia/i82365.h b/qemu/roms/u-boot/include/pcmcia/i82365.h
new file mode 100644
index 000000000..0b432a80b
--- /dev/null
+++ b/qemu/roms/u-boot/include/pcmcia/i82365.h
@@ -0,0 +1,154 @@
+/*
+ * i82365.h 1.21 2001/08/24 12:15:33
+ *
+ * The contents of this file are subject to the Mozilla Public License
+ * Version 1.1 (the "License"); you may not use this file except in
+ * compliance with the License. You may obtain a copy of the License
+ * at http://www.mozilla.org/MPL/
+ *
+ * Software distributed under the License is distributed on an "AS IS"
+ * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
+ * the License for the specific language governing rights and
+ * limitations under the License.
+ *
+ * The initial developer of the original code is David A. Hinds
+ * <dahinds@users.sourceforge.net>.  Portions created by David A. Hinds
+ * are Copyright (C) 1999 David A. Hinds.  All Rights Reserved.
+ *
+ * Alternatively, the contents of this file may be used under the
+ * terms of the GNU General Public License version 2 (the "GPL"), in
+ * which case the provisions of the GPL are applicable instead of the
+ * above.  If you wish to allow the use of your version of this file
+ * only under the terms of the GPL and not to allow others to use
+ * your version of this file under the MPL, indicate your decision by
+ * deleting the provisions above and replace them with the notice and
+ * other provisions required by the GPL.  If you do not delete the
+ * provisions above, a recipient may use your version of this file
+ * under either the MPL or the GPL.
+ */
+
+#ifndef _LINUX_I82365_H
+#define _LINUX_I82365_H
+
+/* register definitions for the Intel 82365SL PCMCIA controller */
+
+/* Offsets for PCIC registers */
+#define I365_IDENT	0x00	/* Identification and revision */
+#define I365_STATUS	0x01	/* Interface status */
+#define I365_POWER	0x02	/* Power and RESETDRV control */
+#define I365_INTCTL	0x03	/* Interrupt and general control */
+#define I365_CSC	0x04	/* Card status change */
+#define I365_CSCINT	0x05	/* Card status change interrupt control */
+#define I365_ADDRWIN	0x06	/* Address window enable */
+#define I365_IOCTL	0x07	/* I/O control */
+#define I365_GENCTL	0x16	/* Card detect and general control */
+#define I365_GBLCTL	0x1E	/* Global control register */
+
+/* Offsets for I/O and memory window registers */
+#define I365_IO(map)	(0x08+((map)<<2))
+#define I365_MEM(map)	(0x10+((map)<<3))
+#define I365_W_START	0
+#define I365_W_STOP	2
+#define I365_W_OFF	4
+
+/* Flags for I365_STATUS */
+#define I365_CS_BVD1	0x01
+#define I365_CS_STSCHG	0x01
+#define I365_CS_BVD2	0x02
+#define I365_CS_SPKR	0x02
+#define I365_CS_DETECT	0x0C
+#define I365_CS_WRPROT	0x10
+#define I365_CS_READY	0x20	/* Inverted */
+#define I365_CS_POWERON	0x40
+#define I365_CS_GPI	0x80
+
+/* Flags for I365_POWER */
+#define I365_PWR_OFF	0x00	/* Turn off the socket */
+#define I365_PWR_OUT	0x80	/* Output enable */
+#define I365_PWR_NORESET 0x40	/* Disable RESETDRV on resume */
+#define I365_PWR_AUTO	0x20	/* Auto pwr switch enable */
+#define I365_VCC_MASK	0x18	/* Mask for turning off Vcc */
+/* There are different layouts for B-step and DF-step chips: the B
+   step has independent Vpp1/Vpp2 control, and the DF step has only
+   Vpp1 control, plus 3V control */
+#define I365_VCC_5V	0x10	/* Vcc = 5.0v */
+#define I365_VCC_3V	0x18	/* Vcc = 3.3v */
+#define I365_VPP2_MASK	0x0c	/* Mask for turning off Vpp2 */
+#define I365_VPP2_5V	0x04	/* Vpp2 = 5.0v */
+#define I365_VPP2_12V	0x08	/* Vpp2 = 12.0v */
+#define I365_VPP1_MASK	0x03	/* Mask for turning off Vpp1 */
+#define I365_VPP1_5V	0x01	/* Vpp2 = 5.0v */
+#define I365_VPP1_12V	0x02	/* Vpp2 = 12.0v */
+
+/* Flags for I365_INTCTL */
+#define I365_RING_ENA	0x80
+#define I365_PC_RESET	0x40
+#define I365_PC_IOCARD	0x20
+#define I365_INTR_ENA	0x10
+#define I365_IRQ_MASK	0x0F
+
+/* Flags for I365_CSC and I365_CSCINT*/
+#define I365_CSC_BVD1	0x01
+#define I365_CSC_STSCHG	0x01
+#define I365_CSC_BVD2	0x02
+#define I365_CSC_READY	0x04
+#define I365_CSC_DETECT	0x08
+#define I365_CSC_ANY	0x0F
+#define I365_CSC_GPI	0x10
+
+/* Flags for I365_ADDRWIN */
+#define I365_ADDR_MEMCS16	0x20
+#define I365_ENA_IO(map)	(0x40 << (map))
+#define I365_ENA_MEM(map)	(0x01 << (map))
+
+/* Flags for I365_IOCTL */
+#define I365_IOCTL_MASK(map)	(0x0F << (map<<2))
+#define I365_IOCTL_WAIT(map)	(0x08 << (map<<2))
+#define I365_IOCTL_0WS(map)	(0x04 << (map<<2))
+#define I365_IOCTL_IOCS16(map)	(0x02 << (map<<2))
+#define I365_IOCTL_16BIT(map)	(0x01 << (map<<2))
+
+/* Flags for I365_GENCTL */
+#define I365_CTL_16DELAY	0x01
+#define I365_CTL_RESET		0x02
+#define I365_CTL_GPI_ENA	0x04
+#define I365_CTL_GPI_CTL	0x08
+#define I365_CTL_RESUME		0x10
+#define I365_CTL_SW_IRQ		0x20
+
+/* Flags for I365_GBLCTL */
+#define I365_GBL_PWRDOWN	0x01
+#define I365_GBL_CSC_LEV	0x02
+#define I365_GBL_WRBACK		0x04
+#define I365_GBL_IRQ_0_LEV	0x08
+#define I365_GBL_IRQ_1_LEV	0x10
+
+/* Flags for memory window registers */
+#define I365_MEM_16BIT	0x8000	/* In memory start high byte */
+#define I365_MEM_0WS	0x4000
+#define I365_MEM_WS1	0x8000	/* In memory stop high byte */
+#define I365_MEM_WS0	0x4000
+#define I365_MEM_WRPROT	0x8000	/* In offset high byte */
+#define I365_MEM_REG	0x4000
+
+#define I365_REG(slot, reg)	(((slot) << 6) | (reg))
+
+/* Default ISA interrupt mask */
+#define I365_ISA_IRQ_MASK	0xdeb8	/* irq's 3-5,7,9-12,14,15 */
+
+/* Device ID's for PCI-to-PCMCIA bridges */
+
+#ifndef PCI_VENDOR_ID_INTEL
+#define PCI_VENDOR_ID_INTEL		0x8086
+#endif
+#ifndef PCI_DEVICE_ID_INTEL_82092AA_0
+#define PCI_DEVICE_ID_INTEL_82092AA_0	0x1221
+#endif
+#ifndef PCI_VENDOR_ID_OMEGA
+#define PCI_VENDOR_ID_OMEGA		0x119b
+#endif
+#ifndef PCI_DEVICE_ID_OMEGA_82C092G
+#define PCI_DEVICE_ID_OMEGA_82C092G	0x1221
+#endif
+
+#endif /* _LINUX_I82365_H */
diff --git a/qemu/roms/u-boot/include/pcmcia/ss.h b/qemu/roms/u-boot/include/pcmcia/ss.h
new file mode 100644
index 000000000..aafae8a54
--- /dev/null
+++ b/qemu/roms/u-boot/include/pcmcia/ss.h
@@ -0,0 +1,133 @@
+/*
+ * ss.h 1.31 2001/08/24 12:16:13
+ *
+ * The contents of this file are subject to the Mozilla Public License
+ * Version 1.1 (the "License"); you may not use this file except in
+ * compliance with the License. You may obtain a copy of the License
+ * at http://www.mozilla.org/MPL/
+ *
+ * Software distributed under the License is distributed on an "AS IS"
+ * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
+ * the License for the specific language governing rights and
+ * limitations under the License.
+ *
+ * The initial developer of the original code is David A. Hinds
+ * <dahinds@users.sourceforge.net>.  Portions created by David A. Hinds
+ * are Copyright (C) 1999 David A. Hinds.  All Rights Reserved.
+ *
+ * Alternatively, the contents of this file may be used under the
+ * terms of the GNU General Public License version 2 (the "GPL"), in
+ * which case the provisions of the GPL are applicable instead of the
+ * above.  If you wish to allow the use of your version of this file
+ * only under the terms of the GPL and not to allow others to use
+ * your version of this file under the MPL, indicate your decision by
+ * deleting the provisions above and replace them with the notice and
+ * other provisions required by the GPL.  If you do not delete the
+ * provisions above, a recipient may use your version of this file
+ * under either the MPL or the GPL.
+ */
+
+#ifndef _LINUX_SS_H
+#define _LINUX_SS_H
+
+/* For RegisterCallback */
+typedef struct ss_callback_t {
+    void	(*handler)(void *info, u_int events);
+    void	*info;
+} ss_callback_t;
+
+/* Definitions for card status flags for GetStatus */
+#define SS_WRPROT	0x0001
+#define SS_CARDLOCK	0x0002
+#define SS_EJECTION	0x0004
+#define SS_INSERTION	0x0008
+#define SS_BATDEAD	0x0010
+#define SS_BATWARN	0x0020
+#define SS_READY	0x0040
+#define SS_DETECT	0x0080
+#define SS_POWERON	0x0100
+#define SS_GPI		0x0200
+#define SS_STSCHG	0x0400
+#define SS_CARDBUS	0x0800
+#define SS_3VCARD	0x1000
+#define SS_XVCARD	0x2000
+#define SS_PENDING	0x4000
+
+/* for InquireSocket */
+typedef struct socket_cap_t {
+    u_int	features;
+    u_int	irq_mask;
+    u_int	map_size;
+    u_char	pci_irq;
+    u_char	cardbus;
+    struct pci_bus *cb_bus;
+    struct bus_operations *bus;
+} socket_cap_t;
+
+/* InquireSocket capabilities */
+#define SS_CAP_PAGE_REGS	0x0001
+#define SS_CAP_VIRTUAL_BUS	0x0002
+#define SS_CAP_MEM_ALIGN	0x0004
+#define SS_CAP_STATIC_MAP	0x0008
+#define SS_CAP_PCCARD		0x4000
+#define SS_CAP_CARDBUS		0x8000
+
+/* for GetSocket, SetSocket */
+typedef struct socket_state_t {
+    u_int	flags;
+    u_int	csc_mask;
+    u_char	Vcc, Vpp;
+    u_char	io_irq;
+} socket_state_t;
+
+/* Socket configuration flags */
+#define SS_PWR_AUTO	0x0010
+#define SS_IOCARD	0x0020
+#define SS_RESET	0x0040
+#define SS_DMA_MODE	0x0080
+#define SS_SPKR_ENA	0x0100
+#define SS_OUTPUT_ENA	0x0200
+#define SS_ZVCARD	0x0400
+
+/* Flags for I/O port and memory windows */
+#define MAP_ACTIVE	0x01
+#define MAP_16BIT	0x02
+#define MAP_AUTOSZ	0x04
+#define MAP_0WS		0x08
+#define MAP_WRPROT	0x10
+#define MAP_ATTRIB	0x20
+#define MAP_USE_WAIT	0x40
+#define MAP_PREFETCH	0x80
+
+/* Use this just for bridge windows */
+#define MAP_IOSPACE	0x20
+
+typedef struct pccard_io_map {
+    u_char	map;
+    u_char	flags;
+    u_short	speed;
+    u_short	start, stop;
+} pccard_io_map;
+
+typedef struct pccard_mem_map {
+    u_char	map;
+    u_char	flags;
+    u_short	speed;
+    u_long	sys_start, sys_stop;
+    u_int	card_start;
+} pccard_mem_map;
+
+typedef struct cb_bridge_map {
+    u_char	map;
+    u_char	flags;
+    u_int	start, stop;
+} cb_bridge_map;
+
+enum ss_service {
+    SS_RegisterCallback, SS_InquireSocket,
+    SS_GetStatus, SS_GetSocket, SS_SetSocket,
+    SS_GetIOMap, SS_SetIOMap, SS_GetMemMap, SS_SetMemMap,
+    SS_GetBridge, SS_SetBridge, SS_ProcSetup
+};
+
+#endif /* _LINUX_SS_H */
diff --git a/qemu/roms/u-boot/include/pcmcia/ti113x.h b/qemu/roms/u-boot/include/pcmcia/ti113x.h
new file mode 100644
index 000000000..5453588d0
--- /dev/null
+++ b/qemu/roms/u-boot/include/pcmcia/ti113x.h
@@ -0,0 +1,234 @@
+/*
+ * ti113x.h 1.31 2002/05/12 18:19:47
+ *
+ * The contents of this file are subject to the Mozilla Public License
+ * Version 1.1 (the "License"); you may not use this file except in
+ * compliance with the License. You may obtain a copy of the License
+ * at http://www.mozilla.org/MPL/
+ *
+ * Software distributed under the License is distributed on an "AS IS"
+ * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
+ * the License for the specific language governing rights and
+ * limitations under the License.
+ *
+ * The initial developer of the original code is David A. Hinds
+ * <dahinds@users.sourceforge.net>.  Portions created by David A. Hinds
+ * are Copyright (C) 1999 David A. Hinds.  All Rights Reserved.
+ *
+ * Alternatively, the contents of this file may be used under the
+ * terms of the GNU General Public License version 2 (the "GPL"), in
+ * which case the provisions of the GPL are applicable instead of the
+ * above.  If you wish to allow the use of your version of this file
+ * only under the terms of the GPL and not to allow others to use
+ * your version of this file under the MPL, indicate your decision by
+ * deleting the provisions above and replace them with the notice and
+ * other provisions required by the GPL.  If you do not delete the
+ * provisions above, a recipient may use your version of this file
+ * under either the MPL or the GPL.
+ */
+
+#ifndef _LINUX_TI113X_H
+#define _LINUX_TI113X_H
+
+#ifndef PCI_VENDOR_ID_TI
+#define PCI_VENDOR_ID_TI		0x104c
+#endif
+
+#ifndef PCI_DEVICE_ID_TI_1130
+#define PCI_DEVICE_ID_TI_1130		0xac12
+#endif
+#ifndef PCI_DEVICE_ID_TI_1031
+#define PCI_DEVICE_ID_TI_1031		0xac13
+#endif
+#ifndef PCI_DEVICE_ID_TI_1131
+#define PCI_DEVICE_ID_TI_1131		0xac15
+#endif
+#ifndef PCI_DEVICE_ID_TI_1210
+#define PCI_DEVICE_ID_TI_1210		0xac1a
+#endif
+#ifndef PCI_DEVICE_ID_TI_1211
+#define PCI_DEVICE_ID_TI_1211		0xac1e
+#endif
+#ifndef PCI_DEVICE_ID_TI_1220
+#define PCI_DEVICE_ID_TI_1220		0xac17
+#endif
+#ifndef PCI_DEVICE_ID_TI_1221
+#define PCI_DEVICE_ID_TI_1221		0xac19
+#endif
+#ifndef PCI_DEVICE_ID_TI_1250A
+#define PCI_DEVICE_ID_TI_1250A		0xac16
+#endif
+#ifndef PCI_DEVICE_ID_TI_1225
+#define PCI_DEVICE_ID_TI_1225		0xac1c
+#endif
+#ifndef PCI_DEVICE_ID_TI_1251A
+#define PCI_DEVICE_ID_TI_1251A		0xac1d
+#endif
+#ifndef PCI_DEVICE_ID_TI_1251B
+#define PCI_DEVICE_ID_TI_1251B		0xac1f
+#endif
+#ifndef PCI_DEVICE_ID_TI_1410
+#define PCI_DEVICE_ID_TI_1410		0xac50
+#endif
+#ifndef PCI_DEVICE_ID_TI_1420
+#define PCI_DEVICE_ID_TI_1420		0xac51
+#endif
+#ifndef PCI_DEVICE_ID_TI_1450
+#define PCI_DEVICE_ID_TI_1450		0xac1b
+#endif
+#ifndef PCI_DEVICE_ID_TI_1451
+#define PCI_DEVICE_ID_TI_1451		0xac52
+#endif
+#ifndef PCI_DEVICE_ID_TI_1510
+#define PCI_DEVICE_ID_TI_1510		0xac56
+#endif
+#ifndef PCI_DEVICE_ID_TI_4410
+#define PCI_DEVICE_ID_TI_4410		0xac41
+#endif
+#ifndef PCI_DEVICE_ID_TI_4450
+#define PCI_DEVICE_ID_TI_4450		0xac40
+#endif
+#ifndef PCI_DEVICE_ID_TI_4451
+#define PCI_DEVICE_ID_TI_4451		0xac42
+#endif
+
+/* Register definitions for TI 113X PCI-to-CardBus bridges */
+
+/* System Control Register */
+#define TI113X_SYSTEM_CONTROL		0x80	/* 32 bit */
+#define  TI113X_SCR_SMIROUTE		0x04000000
+#define  TI113X_SCR_SMISTATUS		0x02000000
+#define  TI113X_SCR_SMIENB		0x01000000
+#define  TI113X_SCR_VCCPROT		0x00200000
+#define  TI113X_SCR_REDUCEZV		0x00100000
+#define  TI113X_SCR_CDREQEN		0x00080000
+#define  TI113X_SCR_CDMACHAN		0x00070000
+#define  TI113X_SCR_SOCACTIVE		0x00002000
+#define  TI113X_SCR_PWRSTREAM		0x00000800
+#define  TI113X_SCR_DELAYUP		0x00000400
+#define  TI113X_SCR_DELAYDOWN		0x00000200
+#define  TI113X_SCR_INTERROGATE		0x00000100
+#define  TI113X_SCR_CLKRUN_SEL		0x00000080
+#define  TI113X_SCR_PWRSAVINGS		0x00000040
+#define  TI113X_SCR_SUBSYSRW		0x00000020
+#define  TI113X_SCR_CB_DPAR		0x00000010
+#define  TI113X_SCR_CDMA_EN		0x00000008
+#define  TI113X_SCR_ASYNC_IRQ		0x00000004
+#define  TI113X_SCR_KEEPCLK		0x00000002
+#define  TI113X_SCR_CLKRUN_ENA		0x00000001
+
+#define  TI122X_SCR_SER_STEP		0xc0000000
+#define  TI122X_SCR_INTRTIE		0x20000000
+#define  TI122X_SCR_P2CCLK		0x08000000
+#define  TI122X_SCR_CBRSVD		0x00400000
+#define  TI122X_SCR_MRBURSTDN		0x00008000
+#define  TI122X_SCR_MRBURSTUP		0x00004000
+#define  TI122X_SCR_RIMUX		0x00000001
+
+/* Multimedia Control Register */
+#define TI1250_MULTIMEDIA_CTL		0x84	/* 8 bit */
+#define  TI1250_MMC_ZVOUTEN		0x80
+#define  TI1250_MMC_PORTSEL		0x40
+#define  TI1250_MMC_ZVEN1		0x02
+#define  TI1250_MMC_ZVEN0		0x01
+
+#define TI1250_GENERAL_STATUS		0x85	/* 8 bit */
+#define TI1250_GPIO0_CONTROL		0x88	/* 8 bit */
+#define TI1250_GPIO1_CONTROL		0x89	/* 8 bit */
+#define TI1250_GPIO2_CONTROL		0x8a	/* 8 bit */
+#define TI1250_GPIO3_CONTROL		0x8b	/* 8 bit */
+#define TI12XX_IRQMUX			0x8c	/* 32 bit */
+
+/* Retry Status Register */
+#define TI113X_RETRY_STATUS		0x90	/* 8 bit */
+#define  TI113X_RSR_PCIRETRY		0x80
+#define  TI113X_RSR_CBRETRY		0x40
+#define  TI113X_RSR_TEXP_CBB		0x20
+#define  TI113X_RSR_MEXP_CBB		0x10
+#define  TI113X_RSR_TEXP_CBA		0x08
+#define  TI113X_RSR_MEXP_CBA		0x04
+#define  TI113X_RSR_TEXP_PCI		0x02
+#define  TI113X_RSR_MEXP_PCI		0x01
+
+/* Card Control Register */
+#define TI113X_CARD_CONTROL		0x91	/* 8 bit */
+#define  TI113X_CCR_RIENB		0x80
+#define  TI113X_CCR_ZVENABLE		0x40
+#define  TI113X_CCR_PCI_IRQ_ENA		0x20
+#define  TI113X_CCR_PCI_IREQ		0x10
+#define  TI113X_CCR_PCI_CSC		0x08
+#define  TI113X_CCR_SPKROUTEN		0x02
+#define  TI113X_CCR_IFG			0x01
+
+#define  TI1220_CCR_PORT_SEL		0x20
+#define  TI122X_CCR_AUD2MUX		0x04
+
+/* Device Control Register */
+#define TI113X_DEVICE_CONTROL		0x92	/* 8 bit */
+#define  TI113X_DCR_5V_FORCE		0x40
+#define  TI113X_DCR_3V_FORCE		0x20
+#define  TI113X_DCR_IMODE_MASK		0x06
+#define  TI113X_DCR_IMODE_ISA		0x02
+#define  TI113X_DCR_IMODE_SERIAL	0x04
+
+#define  TI12XX_DCR_IMODE_PCI_ONLY	0x00
+#define  TI12XX_DCR_IMODE_ALL_SERIAL	0x06
+
+/* Buffer Control Register */
+#define TI113X_BUFFER_CONTROL		0x93	/* 8 bit */
+#define  TI113X_BCR_CB_READ_DEPTH	0x08
+#define  TI113X_BCR_CB_WRITE_DEPTH	0x04
+#define  TI113X_BCR_PCI_READ_DEPTH	0x02
+#define  TI113X_BCR_PCI_WRITE_DEPTH	0x01
+
+/* Diagnostic Register */
+#define TI1250_DIAGNOSTIC		0x93	/* 8 bit */
+#define  TI1250_DIAG_TRUE_VALUE		0x80
+#define  TI1250_DIAG_PCI_IREQ		0x40
+#define  TI1250_DIAG_PCI_CSC		0x20
+#define  TI1250_DIAG_ASYNC_CSC		0x01
+
+/* DMA Registers */
+#define TI113X_DMA_0			0x94	/* 32 bit */
+#define TI113X_DMA_1			0x98	/* 32 bit */
+
+/* ExCA IO offset registers */
+#define TI113X_IO_OFFSET(map)		(0x36+((map)<<1))
+
+/* Data structure for tracking vendor-specific state */
+typedef struct ti113x_state_t {
+    u32			sysctl;		/* TI113X_SYSTEM_CONTROL */
+    u8			cardctl;	/* TI113X_CARD_CONTROL */
+    u8			devctl;		/* TI113X_DEVICE_CONTROL */
+    u8			diag;		/* TI1250_DIAGNOSTIC */
+    u32			irqmux;		/* TI12XX_IRQMUX */
+} ti113x_state_t;
+
+#define TI_PCIC_ID \
+    IS_TI1130, IS_TI1131, IS_TI1031, IS_TI1210, IS_TI1211,	\
+    IS_TI1220, IS_TI1221, IS_TI1225, IS_TI1250A, IS_TI1251A,	\
+    IS_TI1251B, IS_TI1410, IS_TI1420, IS_TI1450, IS_TI1451,	\
+    IS_TI1510, IS_TI4410, IS_TI4450, IS_TI4451
+
+#define TI_PCIC_INFO \
+    { "TI 1130",  IS_TI|IS_CARDBUS, ID(TI, 1130) }, \
+    { "TI 1131",  IS_TI|IS_CARDBUS, ID(TI, 1131) }, \
+    { "TI 1031",  IS_TI|IS_CARDBUS, ID(TI, 1031) }, \
+    { "TI 1210",  IS_TI|IS_CARDBUS, ID(TI, 1210) }, \
+    { "TI 1211",  IS_TI|IS_CARDBUS, ID(TI, 1211) }, \
+    { "TI 1220",  IS_TI|IS_CARDBUS, ID(TI, 1220) }, \
+    { "TI 1221",  IS_TI|IS_CARDBUS, ID(TI, 1221) }, \
+    { "TI 1225",  IS_TI|IS_CARDBUS, ID(TI, 1225) }, \
+    { "TI 1250A", IS_TI|IS_CARDBUS, ID(TI, 1250A) }, \
+    { "TI 1251A", IS_TI|IS_CARDBUS, ID(TI, 1251A) }, \
+    { "TI 1251B", IS_TI|IS_CARDBUS, ID(TI, 1251B) }, \
+    { "TI 1410",  IS_TI|IS_CARDBUS, ID(TI, 1410) }, \
+    { "TI 1420",  IS_TI|IS_CARDBUS, ID(TI, 1420) }, \
+    { "TI 1450",  IS_TI|IS_CARDBUS, ID(TI, 1450) }, \
+    { "TI 1451",  IS_TI|IS_CARDBUS, ID(TI, 1451) }, \
+    { "TI 1510",  IS_TI|IS_CARDBUS, ID(TI, 1510) }, \
+    { "TI 4410",  IS_TI|IS_CARDBUS, ID(TI, 4410) }, \
+    { "TI 4450",  IS_TI|IS_CARDBUS, ID(TI, 4450) }, \
+    { "TI 4451",  IS_TI|IS_CARDBUS, ID(TI, 4451) }
+
+#endif /* _LINUX_TI113X_H */
diff --git a/qemu/roms/u-boot/include/pcmcia/yenta.h b/qemu/roms/u-boot/include/pcmcia/yenta.h
new file mode 100644
index 000000000..5cd58a7da
--- /dev/null
+++ b/qemu/roms/u-boot/include/pcmcia/yenta.h
@@ -0,0 +1,156 @@
+/*
+ * yenta.h 1.20 2001/08/24 12:15:34
+ *
+ * The contents of this file are subject to the Mozilla Public License
+ * Version 1.1 (the "License"); you may not use this file except in
+ * compliance with the License. You may obtain a copy of the License
+ * at http://www.mozilla.org/MPL/
+ *
+ * Software distributed under the License is distributed on an "AS IS"
+ * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
+ * the License for the specific language governing rights and
+ * limitations under the License.
+ *
+ * The initial developer of the original code is David A. Hinds
+ * <dahinds@users.sourceforge.net>.  Portions created by David A. Hinds
+ * are Copyright (C) 1999 David A. Hinds.  All Rights Reserved.
+ *
+ * Alternatively, the contents of this file may be used under the
+ * terms of the GNU General Public License version 2 (the "GPL"), in
+ * which case the provisions of the GPL are applicable instead of the
+ * above.  If you wish to allow the use of your version of this file
+ * only under the terms of the GPL and not to allow others to use
+ * your version of this file under the MPL, indicate your decision by
+ * deleting the provisions above and replace them with the notice and
+ * other provisions required by the GPL.  If you do not delete the
+ * provisions above, a recipient may use your version of this file
+ * under either the MPL or the GPL.
+ */
+
+#ifndef _LINUX_YENTA_H
+#define _LINUX_YENTA_H
+
+/* PCI Configuration Registers */
+
+#define PCI_STATUS_CAPLIST		0x10
+#define PCI_CB_CAPABILITY_POINTER	0x14	/* 8 bit */
+#define PCI_CAPABILITY_ID		0x00	/* 8 bit */
+#define  PCI_CAPABILITY_PM		0x01
+#define PCI_NEXT_CAPABILITY		0x01	/* 8 bit */
+#define PCI_PM_CAPABILITIES		0x02	/* 16 bit */
+#define  PCI_PMCAP_PME_D3COLD		0x8000
+#define  PCI_PMCAP_PME_D3HOT		0x4000
+#define  PCI_PMCAP_PME_D2		0x2000
+#define  PCI_PMCAP_PME_D1		0x1000
+#define  PCI_PMCAP_PME_D0		0x0800
+#define  PCI_PMCAP_D2_CAP		0x0400
+#define  PCI_PMCAP_D1_CAP		0x0200
+#define  PCI_PMCAP_DYN_DATA		0x0100
+#define  PCI_PMCAP_DSI			0x0020
+#define  PCI_PMCAP_AUX_PWR		0x0010
+#define  PCI_PMCAP_PMECLK		0x0008
+#define  PCI_PMCAP_VERSION_MASK		0x0007
+#define PCI_PM_CONTROL_STATUS		0x04	/* 16 bit */
+#define  PCI_PMCS_PME_STATUS		0x8000
+#define  PCI_PMCS_DATASCALE_MASK	0x6000
+#define  PCI_PMCS_DATASCALE_SHIFT	13
+#define  PCI_PMCS_DATASEL_MASK		0x1e00
+#define  PCI_PMCS_DATASEL_SHIFT		9
+#define  PCI_PMCS_PME_ENABLE		0x0100
+#define  PCI_PMCS_PWR_STATE_MASK	0x0003
+#define  PCI_PMCS_PWR_STATE_D0		0x0000
+#define  PCI_PMCS_PWR_STATE_D1		0x0001
+#define  PCI_PMCS_PWR_STATE_D2		0x0002
+#define  PCI_PMCS_PWR_STATE_D3		0x0003
+#define PCI_PM_BRIDGE_EXT		0x06	/* 8 bit */
+#define PCI_PM_DATA			0x07	/* 8 bit */
+
+#define CB_PRIMARY_BUS			0x18	/* 8 bit */
+#define CB_CARDBUS_BUS			0x19	/* 8 bit */
+#define CB_SUBORD_BUS			0x1a	/* 8 bit */
+#define CB_LATENCY_TIMER		0x1b	/* 8 bit */
+
+#define CB_MEM_BASE(m)			(0x1c + 8*(m))
+#define CB_MEM_LIMIT(m)			(0x20 + 8*(m))
+#define CB_IO_BASE(m)			(0x2c + 8*(m))
+#define CB_IO_LIMIT(m)			(0x30 + 8*(m))
+
+#define CB_BRIDGE_CONTROL		0x3e	/* 16 bit */
+#define  CB_BCR_PARITY_ENA		0x0001
+#define  CB_BCR_SERR_ENA		0x0002
+#define  CB_BCR_ISA_ENA			0x0004
+#define  CB_BCR_VGA_ENA			0x0008
+#define  CB_BCR_MABORT			0x0020
+#define  CB_BCR_CB_RESET		0x0040
+#define  CB_BCR_ISA_IRQ			0x0080
+#define  CB_BCR_PREFETCH(m)		(0x0100 << (m))
+#define  CB_BCR_WRITE_POST		0x0400
+
+#define CB_LEGACY_MODE_BASE		0x44
+
+/* Memory mapped registers */
+
+#define CB_SOCKET_EVENT			0x0000
+#define  CB_SE_CSTSCHG			0x00000001
+#define  CB_SE_CCD			0x00000006
+#define  CB_SE_CCD1			0x00000002
+#define  CB_SE_CCD2			0x00000004
+#define  CB_SE_PWRCYCLE			0x00000008
+
+#define CB_SOCKET_MASK			0x0004
+#define  CB_SM_CSTSCHG			0x00000001
+#define  CB_SM_CCD			0x00000006
+#define  CB_SM_PWRCYCLE			0x00000008
+
+#define CB_SOCKET_STATE			0x0008
+#define  CB_SS_CSTSCHG			0x00000001
+#define  CB_SS_CCD			0x00000006
+#define  CB_SS_CCD1			0x00000002
+#define  CB_SS_CCD2			0x00000004
+#define  CB_SS_PWRCYCLE			0x00000008
+#define  CB_SS_16BIT			0x00000010
+#define  CB_SS_32BIT			0x00000020
+#define  CB_SS_CINT			0x00000040
+#define  CB_SS_BADCARD			0x00000080
+#define  CB_SS_DATALOST			0x00000100
+#define  CB_SS_BADVCC			0x00000200
+#define  CB_SS_5VCARD			0x00000400
+#define  CB_SS_3VCARD			0x00000800
+#define  CB_SS_XVCARD			0x00001000
+#define  CB_SS_YVCARD			0x00002000
+#define  CB_SS_VSENSE			0x00003c86
+#define  CB_SS_5VSOCKET			0x10000000
+#define  CB_SS_3VSOCKET			0x20000000
+#define  CB_SS_XVSOCKET			0x40000000
+#define  CB_SS_YVSOCKET			0x80000000
+
+#define CB_SOCKET_FORCE			0x000c
+#define  CB_SF_CVSTEST			0x00004000
+
+#define CB_SOCKET_CONTROL		0x0010
+#define  CB_SC_VPP_MASK			0x00000007
+#define   CB_SC_VPP_OFF			0x00000000
+#define   CB_SC_VPP_12V			0x00000001
+#define   CB_SC_VPP_5V			0x00000002
+#define   CB_SC_VPP_3V			0x00000003
+#define   CB_SC_VPP_XV			0x00000004
+#define   CB_SC_VPP_YV			0x00000005
+#define  CB_SC_VCC_MASK			0x00000070
+#define   CB_SC_VCC_OFF			0x00000000
+#define   CB_SC_VCC_5V			0x00000020
+#define   CB_SC_VCC_3V			0x00000030
+#define   CB_SC_VCC_XV			0x00000040
+#define   CB_SC_VCC_YV			0x00000050
+#define  CB_SC_CCLK_STOP		0x00000080
+
+#define CB_SOCKET_POWER			0x0020
+#define  CB_SP_CLK_CTRL			0x00000001
+#define  CB_SP_CLK_CTRL_ENA		0x00010000
+#define  CB_SP_CLK_MODE			0x01000000
+#define  CB_SP_ACCESS			0x02000000
+
+/* Address bits 31..24 for memory windows for 16-bit cards,
+   accessable only by memory mapping the 16-bit register set */
+#define CB_MEM_PAGE(map)		(0x40 + (map))
+
+#endif /* _LINUX_YENTA_H */
diff --git a/qemu/roms/u-boot/include/phy.h b/qemu/roms/u-boot/include/phy.h
new file mode 100644
index 000000000..d3ecd6378
--- /dev/null
+++ b/qemu/roms/u-boot/include/phy.h
@@ -0,0 +1,242 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *	Andy Fleming <afleming@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h
+ */
+
+#ifndef _PHY_H
+#define _PHY_H
+
+#include <linux/list.h>
+#include <linux/mii.h>
+#include <linux/ethtool.h>
+#include <linux/mdio.h>
+
+#define PHY_MAX_ADDR 32
+
+#define PHY_BASIC_FEATURES	(SUPPORTED_10baseT_Half | \
+				 SUPPORTED_10baseT_Full | \
+				 SUPPORTED_100baseT_Half | \
+				 SUPPORTED_100baseT_Full | \
+				 SUPPORTED_Autoneg | \
+				 SUPPORTED_TP | \
+				 SUPPORTED_MII)
+
+#define PHY_GBIT_FEATURES	(PHY_BASIC_FEATURES | \
+				 SUPPORTED_1000baseT_Half | \
+				 SUPPORTED_1000baseT_Full)
+
+#define PHY_10G_FEATURES	(PHY_GBIT_FEATURES | \
+				SUPPORTED_10000baseT_Full)
+
+#define PHY_ANEG_TIMEOUT	4000
+
+
+typedef enum {
+	PHY_INTERFACE_MODE_MII,
+	PHY_INTERFACE_MODE_GMII,
+	PHY_INTERFACE_MODE_SGMII,
+	PHY_INTERFACE_MODE_QSGMII,
+	PHY_INTERFACE_MODE_TBI,
+	PHY_INTERFACE_MODE_RMII,
+	PHY_INTERFACE_MODE_RGMII,
+	PHY_INTERFACE_MODE_RGMII_ID,
+	PHY_INTERFACE_MODE_RGMII_RXID,
+	PHY_INTERFACE_MODE_RGMII_TXID,
+	PHY_INTERFACE_MODE_RTBI,
+	PHY_INTERFACE_MODE_XGMII,
+	PHY_INTERFACE_MODE_NONE	/* Must be last */
+} phy_interface_t;
+
+static const char *phy_interface_strings[] = {
+	[PHY_INTERFACE_MODE_MII]		= "mii",
+	[PHY_INTERFACE_MODE_GMII]		= "gmii",
+	[PHY_INTERFACE_MODE_SGMII]		= "sgmii",
+	[PHY_INTERFACE_MODE_QSGMII]		= "qsgmii",
+	[PHY_INTERFACE_MODE_TBI]		= "tbi",
+	[PHY_INTERFACE_MODE_RMII]		= "rmii",
+	[PHY_INTERFACE_MODE_RGMII]		= "rgmii",
+	[PHY_INTERFACE_MODE_RGMII_ID]		= "rgmii-id",
+	[PHY_INTERFACE_MODE_RGMII_RXID]		= "rgmii-rxid",
+	[PHY_INTERFACE_MODE_RGMII_TXID]		= "rgmii-txid",
+	[PHY_INTERFACE_MODE_RTBI]		= "rtbi",
+	[PHY_INTERFACE_MODE_XGMII]		= "xgmii",
+	[PHY_INTERFACE_MODE_NONE]		= "",
+};
+
+static inline const char *phy_string_for_interface(phy_interface_t i)
+{
+	/* Default to unknown */
+	if (i > PHY_INTERFACE_MODE_NONE)
+		i = PHY_INTERFACE_MODE_NONE;
+
+	return phy_interface_strings[i];
+}
+
+
+struct phy_device;
+
+#define MDIO_NAME_LEN 32
+
+struct mii_dev {
+	struct list_head link;
+	char name[MDIO_NAME_LEN];
+	void *priv;
+	int (*read)(struct mii_dev *bus, int addr, int devad, int reg);
+	int (*write)(struct mii_dev *bus, int addr, int devad, int reg,
+			u16 val);
+	int (*reset)(struct mii_dev *bus);
+	struct phy_device *phymap[PHY_MAX_ADDR];
+	u32 phy_mask;
+};
+
+/* struct phy_driver: a structure which defines PHY behavior
+ *
+ * uid will contain a number which represents the PHY.  During
+ * startup, the driver will poll the PHY to find out what its
+ * UID--as defined by registers 2 and 3--is.  The 32-bit result
+ * gotten from the PHY will be masked to
+ * discard any bits which may change based on revision numbers
+ * unimportant to functionality
+ *
+ */
+struct phy_driver {
+	char *name;
+	unsigned int uid;
+	unsigned int mask;
+	unsigned int mmds;
+
+	u32 features;
+
+	/* Called to do any driver startup necessities */
+	/* Will be called during phy_connect */
+	int (*probe)(struct phy_device *phydev);
+
+	/* Called to configure the PHY, and modify the controller
+	 * based on the results.  Should be called after phy_connect */
+	int (*config)(struct phy_device *phydev);
+
+	/* Called when starting up the controller */
+	int (*startup)(struct phy_device *phydev);
+
+	/* Called when bringing down the controller */
+	int (*shutdown)(struct phy_device *phydev);
+
+	int (*readext)(struct phy_device *phydev, int addr, int devad, int reg);
+	int (*writeext)(struct phy_device *phydev, int addr, int devad, int reg,
+			u16 val);
+	struct list_head list;
+};
+
+struct phy_device {
+	/* Information about the PHY type */
+	/* And management functions */
+	struct mii_dev *bus;
+	struct phy_driver *drv;
+	void *priv;
+
+	struct eth_device *dev;
+
+	/* forced speed & duplex (no autoneg)
+	 * partner speed & duplex & pause (autoneg)
+	 */
+	int speed;
+	int duplex;
+
+	/* The most recently read link state */
+	int link;
+	int port;
+	phy_interface_t interface;
+
+	u32 advertising;
+	u32 supported;
+	u32 mmds;
+
+	int autoneg;
+	int addr;
+	int pause;
+	int asym_pause;
+	u32 phy_id;
+	u32 flags;
+};
+
+struct fixed_link {
+	int phy_id;
+	int duplex;
+	int link_speed;
+	int pause;
+	int asym_pause;
+};
+
+static inline int phy_read(struct phy_device *phydev, int devad, int regnum)
+{
+	struct mii_dev *bus = phydev->bus;
+
+	return bus->read(bus, phydev->addr, devad, regnum);
+}
+
+static inline int phy_write(struct phy_device *phydev, int devad, int regnum,
+			u16 val)
+{
+	struct mii_dev *bus = phydev->bus;
+
+	return bus->write(bus, phydev->addr, devad, regnum, val);
+}
+
+#ifdef CONFIG_PHYLIB_10G
+extern struct phy_driver gen10g_driver;
+
+/* For now, XGMII is the only 10G interface */
+static inline int is_10g_interface(phy_interface_t interface)
+{
+	return interface == PHY_INTERFACE_MODE_XGMII;
+}
+
+#endif
+
+int phy_init(void);
+int phy_reset(struct phy_device *phydev);
+struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask,
+		phy_interface_t interface);
+void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev);
+struct phy_device *phy_connect(struct mii_dev *bus, int addr,
+				struct eth_device *dev,
+				phy_interface_t interface);
+int phy_startup(struct phy_device *phydev);
+int phy_config(struct phy_device *phydev);
+int phy_shutdown(struct phy_device *phydev);
+int phy_register(struct phy_driver *drv);
+int genphy_config_aneg(struct phy_device *phydev);
+int genphy_restart_aneg(struct phy_device *phydev);
+int genphy_update_link(struct phy_device *phydev);
+int genphy_parse_link(struct phy_device *phydev);
+int genphy_config(struct phy_device *phydev);
+int genphy_startup(struct phy_device *phydev);
+int genphy_shutdown(struct phy_device *phydev);
+int gen10g_config(struct phy_device *phydev);
+int gen10g_startup(struct phy_device *phydev);
+int gen10g_shutdown(struct phy_device *phydev);
+int gen10g_discover_mmds(struct phy_device *phydev);
+
+int phy_atheros_init(void);
+int phy_broadcom_init(void);
+int phy_davicom_init(void);
+int phy_et1011c_init(void);
+int phy_lxt_init(void);
+int phy_marvell_init(void);
+int phy_micrel_init(void);
+int phy_natsemi_init(void);
+int phy_realtek_init(void);
+int phy_smsc_init(void);
+int phy_teranetics_init(void);
+int phy_vitesse_init(void);
+
+int board_phy_config(struct phy_device *phydev);
+
+/* PHY UIDs for various PHYs that are referenced in external code */
+#define PHY_UID_TN2020	0x00a19410
+
+#endif
diff --git a/qemu/roms/u-boot/include/physmem.h b/qemu/roms/u-boot/include/physmem.h
new file mode 100644
index 000000000..03d3a78b7
--- /dev/null
+++ b/qemu/roms/u-boot/include/physmem.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Alternatively, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
+ */
+
+/*
+ * These functions work like memset but operate on physical memory which may
+ * not be accessible directly.
+ *
+ * @param s	The physical address to start setting memory at.
+ * @param c	The character to set each byte of the region to.
+ * @param n	The number of bytes to set.
+ *
+ * @return	The physical address of the memory which was set.
+ */
+phys_addr_t arch_phys_memset(phys_addr_t s, int c, phys_size_t n);
diff --git a/qemu/roms/u-boot/include/post.h b/qemu/roms/u-boot/include/post.h
new file mode 100644
index 000000000..24ca728b4
--- /dev/null
+++ b/qemu/roms/u-boot/include/post.h
@@ -0,0 +1,187 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2010
+ * Michael Zaidman, Kodak, michael.zaidman@kodak.com
+ * post_word_{load|store} cleanup.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _POST_H
+#define _POST_H
+
+#ifndef	__ASSEMBLY__
+#include <common.h>
+#include <asm/io.h>
+
+#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
+
+#ifndef CONFIG_POST_EXTERNAL_WORD_FUNCS
+#ifdef CONFIG_SYS_POST_WORD_ADDR
+#define _POST_WORD_ADDR	CONFIG_SYS_POST_WORD_ADDR
+#else
+
+#ifdef CONFIG_MPC5xxx
+#define _POST_WORD_ADDR	(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE)
+
+#elif defined(CONFIG_MPC512X)
+#define _POST_WORD_ADDR \
+	(CONFIG_SYS_SRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
+
+#elif defined(CONFIG_8xx)
+#define _POST_WORD_ADDR \
+	(((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_dpmem + CPM_POST_WORD_ADDR)
+
+#elif defined(CONFIG_MPC8260)
+#include <asm/cpm_8260.h>
+#define _POST_WORD_ADDR	(CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR)
+
+#elif defined(CONFIG_MPC8360)
+#include <asm/immap_qe.h>
+#define _POST_WORD_ADDR	(CONFIG_SYS_IMMR + CPM_POST_WORD_ADDR)
+
+#elif defined (CONFIG_MPC85xx)
+#include <asm/immap_85xx.h>
+#define _POST_WORD_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET + \
+				offsetof(ccsr_pic_t, tfrr))
+
+#elif defined (CONFIG_MPC86xx)
+#include <asm/immap_86xx.h>
+#define _POST_WORD_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PIC_OFFSET + \
+				offsetof(ccsr_pic_t, tfrr))
+
+#elif defined (CONFIG_4xx)
+#define _POST_WORD_ADDR \
+	(CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
+#endif
+
+#ifndef _POST_WORD_ADDR
+#error "_POST_WORD_ADDR currently not implemented for this platform!"
+#endif
+#endif /* CONFIG_SYS_POST_WORD_ADDR */
+
+static inline ulong post_word_load (void)
+{
+	return in_le32((volatile void *)(_POST_WORD_ADDR));
+}
+
+static inline void post_word_store (ulong value)
+{
+	out_le32((volatile void *)(_POST_WORD_ADDR), value);
+}
+
+#else
+
+extern ulong post_word_load(void);
+extern void post_word_store(ulong value);
+
+#endif /* CONFIG_POST_EXTERNAL_WORD_FUNCS */
+#endif /* defined (CONFIG_POST) || defined(CONFIG_LOGBUFFER) */
+#endif /* __ASSEMBLY__ */
+
+#ifdef CONFIG_POST
+
+#define POST_POWERON		0x01	/* test runs on power-on booting */
+#define POST_NORMAL		0x02	/* test runs on normal booting */
+#define POST_SLOWTEST		0x04	/* test is slow, enabled by key press */
+#define POST_POWERTEST		0x08	/* test runs after watchdog reset */
+
+#define POST_COLDBOOT		0x80	/* first boot after power-on */
+
+#define POST_ROM		0x0100	/* test runs in ROM */
+#define POST_RAM		0x0200	/* test runs in RAM */
+#define POST_MANUAL		0x0400	/* test runs on diag command */
+#define POST_REBOOT		0x0800	/* test may cause rebooting */
+#define POST_PREREL		0x1000  /* test runs before relocation */
+
+#define POST_CRITICAL		0x2000	/* Use failbootcmd if test failed */
+#define POST_STOP		0x4000	/* Interrupt POST sequence on fail */
+
+#define POST_MEM		(POST_RAM | POST_ROM)
+#define POST_ALWAYS		(POST_NORMAL	| \
+				 POST_SLOWTEST	| \
+				 POST_MANUAL	| \
+				 POST_POWERON	)
+
+#define POST_FAIL_SAVE		0x80
+
+#define POST_BEFORE		1
+#define POST_AFTER		0
+#define POST_PASSED		1
+#define POST_FAILED		0
+
+#ifndef	__ASSEMBLY__
+
+struct post_test {
+	char *name;
+	char *cmd;
+	char *desc;
+	int flags;
+	int (*test) (int flags);
+	int (*init_f) (void);
+	void (*reloc) (void);
+	unsigned long testid;
+};
+int post_init_f (void);
+void post_bootmode_init (void);
+int post_bootmode_get (unsigned int * last_test);
+void post_bootmode_clear (void);
+void post_output_backlog ( void );
+int post_run (char *name, int flags);
+int post_info (char *name);
+int post_log (char *format, ...);
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
+void post_reloc (void);
+#endif
+unsigned long post_time_ms (unsigned long base);
+
+extern struct post_test post_list[];
+extern unsigned int post_list_size;
+extern int post_hotkeys_pressed(void);
+extern int memory_post_test(int flags);
+
+/*
+ *  If GCC is configured to use a version of GAS that supports
+ * the .gnu_attribute directive, it will use that directive to
+ * record certain properties of the output code.
+ *  This feature is new to GCC 4.3.0.
+ *  .gnu_attribute is new to GAS 2.18.
+ */
+#if (__GNUC__ >= 4 && __GNUC_MINOR__ >= 3)
+/* Tag_GNU_Power_ABI_FP/soft-float */
+#define GNU_FPOST_ATTR	asm(".gnu_attribute	4, 2");
+#else
+#define GNU_FPOST_ATTR
+#endif /* __GNUC__ */
+#endif /* __ASSEMBLY__ */
+
+#define CONFIG_SYS_POST_RTC		0x00000001
+#define CONFIG_SYS_POST_WATCHDOG	0x00000002
+#define CONFIG_SYS_POST_MEMORY		0x00000004
+#define CONFIG_SYS_POST_CPU		0x00000008
+#define CONFIG_SYS_POST_I2C		0x00000010
+#define CONFIG_SYS_POST_CACHE		0x00000020
+#define CONFIG_SYS_POST_UART		0x00000040
+#define CONFIG_SYS_POST_ETHER		0x00000080
+#define CONFIG_SYS_POST_SPI		0x00000100
+#define CONFIG_SYS_POST_USB		0x00000200
+#define CONFIG_SYS_POST_SPR		0x00000400
+#define CONFIG_SYS_POST_SYSMON		0x00000800
+#define CONFIG_SYS_POST_DSP		0x00001000
+#define CONFIG_SYS_POST_OCM		0x00002000
+#define CONFIG_SYS_POST_FPU		0x00004000
+#define CONFIG_SYS_POST_ECC		0x00008000
+#define CONFIG_SYS_POST_BSPEC1		0x00010000
+#define CONFIG_SYS_POST_BSPEC2		0x00020000
+#define CONFIG_SYS_POST_BSPEC3		0x00040000
+#define CONFIG_SYS_POST_BSPEC4		0x00080000
+#define CONFIG_SYS_POST_BSPEC5		0x00100000
+#define CONFIG_SYS_POST_CODEC		0x00200000
+#define CONFIG_SYS_POST_COPROC		0x00400000
+#define CONFIG_SYS_POST_FLASH		0x00800000
+#define CONFIG_SYS_POST_MEM_REGIONS	0x01000000
+
+#endif /* CONFIG_POST */
+
+#endif /* _POST_H */
diff --git a/qemu/roms/u-boot/include/power/battery.h b/qemu/roms/u-boot/include/power/battery.h
new file mode 100644
index 000000000..dc8d153c1
--- /dev/null
+++ b/qemu/roms/u-boot/include/power/battery.h
@@ -0,0 +1,22 @@
+/*
+ *  Copyright (C) 2012 Samsung Electronics
+ *  Lukasz Majewski <l.majewski@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __POWER_BATTERY_H_
+#define __POWER_BATTERY_H_
+
+struct battery {
+	unsigned int version;
+	unsigned int state_of_chrg;
+	unsigned int time_to_empty;
+	unsigned int capacity;
+	unsigned int voltage_uV;
+
+	unsigned int state;
+};
+
+int power_bat_init(unsigned char bus);
+#endif /* __POWER_BATTERY_H_ */
diff --git a/qemu/roms/u-boot/include/power/fg_battery_cell_params.h b/qemu/roms/u-boot/include/power/fg_battery_cell_params.h
new file mode 100644
index 000000000..d18e2d673
--- /dev/null
+++ b/qemu/roms/u-boot/include/power/fg_battery_cell_params.h
@@ -0,0 +1,74 @@
+/*
+ *  Copyright (C) 2012 Samsung Electronics
+ *  Lukasz Majewski <l.majewski@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __FG_BATTERY_CELL_PARAMS_H_
+#define __FG_BATTERY_CELL_PARAMS_H_
+
+#if  defined(CONFIG_POWER_FG_MAX17042) && defined(CONFIG_TRATS)
+
+/* Cell characteristics - Exynos4 TRATS development board */
+/* Shall be written to addr 0x80h */
+u16 cell_character0[16] = {
+	0xA2A0,
+	0xB6E0,
+	0xB850,
+	0xBAD0,
+	0xBB20,
+	0xBB70,
+	0xBBC0,
+	0xBC20,
+	0xBC80,
+	0xBCE0,
+	0xBD80,
+	0xBE20,
+	0xC090,
+	0xC420,
+	0xC910,
+	0xD070
+};
+
+/* Shall be written to addr 0x90h */
+u16 cell_character1[16] = {
+	0x0090,
+	0x1A50,
+	0x02F0,
+	0x2060,
+	0x2060,
+	0x2E60,
+	0x26A0,
+	0x2DB0,
+	0x2DB0,
+	0x1870,
+	0x2A20,
+	0x16F0,
+	0x08F0,
+	0x0D40,
+	0x08C0,
+	0x08C0
+};
+
+/* Shall be written to addr 0xA0h */
+u16 cell_character2[16] = {
+	0x0100,
+	0x0100,
+	0x0100,
+	0x0100,
+	0x0100,
+	0x0100,
+	0x0100,
+	0x0100,
+	0x0100,
+	0x0100,
+	0x0100,
+	0x0100,
+	0x0100,
+	0x0100,
+	0x0100,
+	0x0100
+};
+#endif
+#endif /* __FG_BATTERY_CELL_PARAMS_H_ */
diff --git a/qemu/roms/u-boot/include/power/max17042_fg.h b/qemu/roms/u-boot/include/power/max17042_fg.h
new file mode 100644
index 000000000..ce9605336
--- /dev/null
+++ b/qemu/roms/u-boot/include/power/max17042_fg.h
@@ -0,0 +1,58 @@
+/*
+ *  Copyright (C) 2012 Samsung Electronics
+ *  Lukasz Majewski <l.majewski@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MAX17042_FG_H_
+#define __MAX17042_FG_H_
+
+/* MAX 17042 registers */
+enum {
+	MAX17042_STATUS         = 0x00,
+	MAX17042_SOCREP         = 0x06,
+	MAX17042_VCELL          = 0x09,
+	MAX17042_CURRENT        = 0x0A,
+	MAX17042_AVG_CURRENT	= 0x0B,
+	MAX17042_SOCMIX	= 0x0D,
+	MAX17042_SOCAV		= 0x0E,
+	MAX17042_DESIGN_CAP	= 0x18,
+	MAX17042_AVG_VCELL	= 0x19,
+	MAX17042_CONFIG	= 0x1D,
+	MAX17042_VERSION	= 0x21,
+	MAX17042_LEARNCFG       = 0x28,
+	MAX17042_FILTERCFG	= 0x29,
+	MAX17042_RELAXCFG	= 0x2A,
+	MAX17042_MISCCFG	= 0x2B,
+	MAX17042_CGAIN		= 0x2E,
+	MAX17042_COFF		= 0x2F,
+	MAX17042_RCOMP0	= 0x38,
+	MAX17042_TEMPCO	= 0x39,
+	MAX17042_FSTAT		= 0x3D,
+	MAX17042_MLOCKReg1	= 0x62,
+	MAX17042_MLOCKReg2	= 0x63,
+	MAX17042_MODEL1         = 0x80,
+	MAX17042_MODEL2         = 0x90,
+	MAX17042_MODEL3         = 0xA0,
+	MAX17042_VFOCV		= 0xFB,
+	MAX17042_VFSOC		= 0xFF,
+
+	FG_NUM_OF_REGS = 0x100,
+};
+
+#define RCOMP0			0x0060
+#define TempCo			0x1015
+
+
+#define MAX17042_POR (1 << 1)
+
+#define MODEL_UNLOCK1		0x0059
+#define MODEL_UNLOCK2		0x00c4
+#define MODEL_LOCK1		0x0000
+#define MODEL_LOCK2		0x0000
+
+#define MAX17042_I2C_ADDR	(0x6C >> 1)
+
+int power_fg_init(unsigned char bus);
+#endif /* __MAX17042_FG_H_ */
diff --git a/qemu/roms/u-boot/include/power/max77686_pmic.h b/qemu/roms/u-boot/include/power/max77686_pmic.h
new file mode 100644
index 000000000..c2a772a89
--- /dev/null
+++ b/qemu/roms/u-boot/include/power/max77686_pmic.h
@@ -0,0 +1,204 @@
+/*
+ *  Copyright (C) 2012 Samsung Electronics
+ *  Rajeshwari Shinde <rajeshwari.s@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MAX77686_H_
+#define __MAX77686_H_
+
+#include <power/pmic.h>
+
+enum {
+	MAX77686_REG_PMIC_ID		= 0x0,
+	MAX77686_REG_PMIC_INTSRC,
+	MAX77686_REG_PMIC_INT1,
+	MAX77686_REG_PMIC_INT2,
+	MAX77686_REG_PMIC_INT1MSK,
+	MAX77686_REG_PMIC_INT2MSK,
+
+	MAX77686_REG_PMIC_STATUS1,
+	MAX77686_REG_PMIC_STATUS2,
+
+	MAX77686_REG_PMIC_PWRON,
+	MAX77686_REG_PMIC_ONOFFDELAY,
+	MAX77686_REG_PMIC_MRSTB,
+
+	MAX77686_REG_PMIC_BUCK1CRTL	= 0x10,
+	MAX77686_REG_PMIC_BUCK1OUT,
+	MAX77686_REG_PMIC_BUCK2CTRL1,
+	MAX77686_REG_PMIC_BUCK234FREQ,
+	MAX77686_REG_PMIC_BUCK2DVS1,
+	MAX77686_REG_PMIC_BUCK2DVS2,
+	MAX77686_REG_PMIC_BUCK2DVS3,
+	MAX77686_REG_PMIC_BUCK2DVS4,
+	MAX77686_REG_PMIC_BUCK2DVS5,
+	MAX77686_REG_PMIC_BUCK2DVS6,
+	MAX77686_REG_PMIC_BUCK2DVS7,
+	MAX77686_REG_PMIC_BUCK2DVS8,
+	MAX77686_REG_PMIC_BUCK3CTRL,
+	MAX77686_REG_PMIC_BUCK3DVS1	= 0x1e,
+	MAX77686_REG_PMIC_BUCK3DVS2,
+	MAX77686_REG_PMIC_BUCK3DVS3,
+	MAX77686_REG_PMIC_BUCK3DVS4,
+	MAX77686_REG_PMIC_BUCK3DVS5,
+	MAX77686_REG_PMIC_BUCK3DVS6,
+	MAX77686_REG_PMIC_BUCK3DVS7,
+	MAX77686_REG_PMIC_BUCK3DVS8,
+	MAX77686_REG_PMIC_BUCK4CTRL1,
+	MAX77686_REG_PMIC_BUCK4DVS1	= 0x28,
+	MAX77686_REG_PMIC_BUCK4DVS2,
+	MAX77686_REG_PMIC_BUCK4DVS3,
+	MAX77686_REG_PMIC_BUCK4DVS4,
+	MAX77686_REG_PMIC_BUCK4DVS5,
+	MAX77686_REG_PMIC_BUCK4DVS6,
+	MAX77686_REG_PMIC_BUCK4DVS7,
+	MAX77686_REG_PMIC_BUCK4DVS8,
+	MAX77686_REG_PMIC_BUCK5CTRL,
+	MAX77686_REG_PMIC_BUCK5OUT,
+	MAX77686_REG_PMIC_BUCK6CRTL,
+	MAX77686_REG_PMIC_BUCK6OUT,
+	MAX77686_REG_PMIC_BUCK7CRTL,
+	MAX77686_REG_PMIC_BUCK7OUT,
+	MAX77686_REG_PMIC_BUCK8CRTL,
+	MAX77686_REG_PMIC_BUCK8OUT,
+	MAX77686_REG_PMIC_BUCK9CRTL,
+	MAX77686_REG_PMIC_BUCK9OUT,
+
+	MAX77686_REG_PMIC_LDO1CTRL1	= 0x40,
+	MAX77686_REG_PMIC_LDO2CTRL1,
+	MAX77686_REG_PMIC_LDO3CTRL1,
+	MAX77686_REG_PMIC_LDO4CTRL1,
+	MAX77686_REG_PMIC_LDO5CTRL1,
+	MAX77686_REG_PMIC_LDO6CTRL1,
+	MAX77686_REG_PMIC_LDO7CTRL1,
+	MAX77686_REG_PMIC_LDO8CTRL1,
+	MAX77686_REG_PMIC_LDO9CTRL1,
+	MAX77686_REG_PMIC_LDO10CTRL1,
+	MAX77686_REG_PMIC_LDO11CTRL1,
+	MAX77686_REG_PMIC_LDO12CTRL1,
+	MAX77686_REG_PMIC_LDO13CTRL1,
+	MAX77686_REG_PMIC_LDO14CTRL1,
+	MAX77686_REG_PMIC_LDO15CTRL1,
+	MAX77686_REG_PMIC_LDO16CTRL1,
+	MAX77686_REG_PMIC_LDO17CTRL1,
+	MAX77686_REG_PMIC_LDO18CTRL1,
+	MAX77686_REG_PMIC_LDO19CTRL1,
+	MAX77686_REG_PMIC_LDO20CTRL1,
+	MAX77686_REG_PMIC_LDO21CTRL1,
+	MAX77686_REG_PMIC_LDO22CTRL1,
+	MAX77686_REG_PMIC_LDO23CTRL1,
+	MAX77686_REG_PMIC_LDO24CTRL1,
+	MAX77686_REG_PMIC_LDO25CTRL1,
+	MAX77686_REG_PMIC_LDO26CTRL1,
+	MAX77686_REG_PMIC_LDO1CTRL2,
+	MAX77686_REG_PMIC_LDO2CTRL2,
+	MAX77686_REG_PMIC_LDO3CTRL2,
+	MAX77686_REG_PMIC_LDO4CTRL2,
+	MAX77686_REG_PMIC_LDO5CTRL2,
+	MAX77686_REG_PMIC_LDO6CTRL2,
+	MAX77686_REG_PMIC_LDO7CTRL2,
+	MAX77686_REG_PMIC_LDO8CTRL2,
+	MAX77686_REG_PMIC_LDO9CTRL2,
+	MAX77686_REG_PMIC_LDO10CTRL2,
+	MAX77686_REG_PMIC_LDO11CTRL2,
+	MAX77686_REG_PMIC_LDO12CTRL2,
+	MAX77686_REG_PMIC_LDO13CTRL2,
+	MAX77686_REG_PMIC_LDO14CTRL2,
+	MAX77686_REG_PMIC_LDO15CTRL2,
+	MAX77686_REG_PMIC_LDO16CTRL2,
+	MAX77686_REG_PMIC_LDO17CTRL2,
+	MAX77686_REG_PMIC_LDO18CTRL2,
+	MAX77686_REG_PMIC_LDO19CTRL2,
+	MAX77686_REG_PMIC_LDO20CTRL2,
+	MAX77686_REG_PMIC_LDO21CTRL2,
+	MAX77686_REG_PMIC_LDO22CTRL2,
+	MAX77686_REG_PMIC_LDO23CTRL2,
+	MAX77686_REG_PMIC_LDO24CTRL2,
+	MAX77686_REG_PMIC_LDO25CTRL2,
+	MAX77686_REG_PMIC_LDO26CTRL2,
+
+	MAX77686_REG_PMIC_BBAT		= 0x7e,
+	MAX77686_REG_PMIC_32KHZ,
+
+	PMIC_NUM_OF_REGS,
+};
+
+/* I2C device address for pmic max77686 */
+#define MAX77686_I2C_ADDR (0x12 >> 1)
+
+enum {
+	REG_DISABLE = 0,
+	REG_ENABLE
+};
+
+enum {
+	LDO_OFF = 0,
+	LDO_ON,
+
+	DIS_LDO = (0x00 << 6),
+	EN_LDO = (0x3 << 6),
+};
+
+enum {
+	OPMODE_OFF = 0,
+	OPMODE_STANDBY,
+	OPMODE_LPM,
+	OPMODE_ON,
+};
+
+int max77686_set_ldo_voltage(struct pmic *p, int ldo, ulong uV);
+int max77686_set_ldo_mode(struct pmic *p, int ldo, char opmode);
+int max77686_set_buck_mode(struct pmic *p, int buck, char opmode);
+
+#define MAX77686_LDO_VOLT_MAX_HEX	0x3f
+#define MAX77686_LDO_VOLT_MASK		0x3f
+#define MAX77686_LDO_MODE_MASK		0xc0
+#define MAX77686_LDO_MODE_OFF		(0x00 << 0x06)
+#define MAX77686_LDO_MODE_STANDBY	(0x01 << 0x06)
+#define MAX77686_LDO_MODE_LPM		(0x02 << 0x06)
+#define MAX77686_LDO_MODE_ON		(0x03 << 0x06)
+#define MAX77686_BUCK_MODE_MASK		0x03
+#define MAX77686_BUCK_MODE_SHIFT_1	0x00
+#define MAX77686_BUCK_MODE_SHIFT_2	0x04
+#define MAX77686_BUCK_MODE_OFF		0x00
+#define MAX77686_BUCK_MODE_STANDBY	0x01
+#define MAX77686_BUCK_MODE_LPM		0x02
+#define MAX77686_BUCK_MODE_ON		0x03
+
+/* Buck1 1 volt value */
+#define MAX77686_BUCK1OUT_1V	0x5
+/* Buck1 1.05 volt value */
+#define MAX77686_BUCK1OUT_1_05V    0x6
+#define MAX77686_BUCK1CTRL_EN	(3 << 0)
+/* Buck2 1.3 volt value */
+#define MAX77686_BUCK2DVS1_1_3V	0x38
+#define MAX77686_BUCK2CTRL_ON	(1 << 4)
+/* Buck3 1.0125 volt value */
+#define MAX77686_BUCK3DVS1_1_0125V	0x21
+#define MAX77686_BUCK3CTRL_ON	(1 << 4)
+/* Buck4 1.2 volt value */
+#define MAX77686_BUCK4DVS1_1_2V	0x30
+#define MAX77686_BUCK4CTRL_ON	(1 << 4)
+/* LDO2 1.5 volt value */
+#define MAX77686_LD02CTRL1_1_5V	0x1c
+/* LDO3 1.8 volt value */
+#define MAX77686_LD03CTRL1_1_8V	0x14
+/* LDO5 1.8 volt value */
+#define MAX77686_LD05CTRL1_1_8V	0x14
+/* LDO10 1.8 volt value */
+#define MAX77686_LD10CTRL1_1_8V	0x14
+/*
+ * MAX77686_REG_PMIC_32KHZ set to 32KH CP
+ * output is activated
+ */
+#define MAX77686_32KHCP_EN	(1 << 1)
+/*
+ * MAX77686_REG_PMIC_BBAT set to
+ * Back up batery charger on and
+ * limit voltage setting to 3.5v
+ */
+#define MAX77686_BBCHOSTEN	(1 << 0)
+#define MAX77686_BBCVS_3_5V	(3 << 3)
+#endif /* __MAX77686_PMIC_H_ */
diff --git a/qemu/roms/u-boot/include/power/max77693_fg.h b/qemu/roms/u-boot/include/power/max77693_fg.h
new file mode 100644
index 000000000..42626ed83
--- /dev/null
+++ b/qemu/roms/u-boot/include/power/max77693_fg.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ * Piotr Wilczek <p.wilczek@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MAX77693_FG_H_
+#define __MAX77693_FG_H_
+
+/* MAX 77693 registers */
+enum {
+	MAX77693_STATUS		= 0x00,
+	MAX77693_SOCREP		= 0x06,
+	MAX77693_VCELL		= 0x09,
+	MAX77693_CURRENT	= 0x0A,
+	MAX77693_AVG_CURRENT	= 0x0B,
+	MAX77693_SOCMIX		= 0x0D,
+	MAX77693_SOCAV		= 0x0E,
+	MAX77693_DESIGN_CAP	= 0x18,
+	MAX77693_AVG_VCELL	= 0x19,
+	MAX77693_CONFIG		= 0x1D,
+	MAX77693_VERSION	= 0x21,
+	MAX77693_LEARNCFG	= 0x28,
+	MAX77693_FILTERCFG	= 0x29,
+	MAX77693_RELAXCFG	= 0x2A,
+	MAX77693_MISCCFG	= 0x2B,
+	MAX77693_CGAIN		= 0x2E,
+	MAX77693_COFF		= 0x2F,
+	MAX77693_RCOMP0		= 0x38,
+	MAX77693_TEMPCO		= 0x39,
+	MAX77693_FSTAT		= 0x3D,
+	MAX77693_VFOCV		= 0xEE,
+	MAX77693_VFSOC		= 0xFF,
+
+	FG_NUM_OF_REGS		= 0x100,
+};
+
+#define MAX77693_POR (1 << 1)
+
+#define MODEL_UNLOCK1		0x0059
+#define MODEL_UNLOCK2		0x00c4
+#define MODEL_LOCK1		0x0000
+#define MODEL_LOCK2		0x0000
+
+#define MAX77693_FUEL_I2C_ADDR	(0x6C >> 1)
+
+int power_fg_init(unsigned char bus);
+#endif /* __MAX77693_FG_H_ */
diff --git a/qemu/roms/u-boot/include/power/max77693_muic.h b/qemu/roms/u-boot/include/power/max77693_muic.h
new file mode 100644
index 000000000..a2c29eb6c
--- /dev/null
+++ b/qemu/roms/u-boot/include/power/max77693_muic.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ * Piotr Wilczek <p.wilczek@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MAX77693_MUIC_H_
+#define __MAX77693_MUIC_H_
+
+#include <power/power_chrg.h>
+
+/*
+ * MUIC REGISTER
+ */
+
+#define MAX77693_MUIC_PREFIX	"max77693-muic:"
+
+/* MAX77693_MUIC_STATUS1 */
+#define MAX77693_MUIC_ADC_MASK	0x1F
+
+/* MAX77693_MUIC_STATUS2 */
+#define MAX77693_MUIC_CHG_NO		0x00
+#define MAX77693_MUIC_CHG_USB		0x01
+#define MAX77693_MUIC_CHG_USB_D		0x02
+#define MAX77693_MUIC_CHG_TA		0x03
+#define MAX77693_MUIC_CHG_TA_500	0x04
+#define MAX77693_MUIC_CHG_TA_1A		0x05
+#define MAX77693_MUIC_CHG_MASK		0x07
+
+/* MAX77693_MUIC_CONTROL1 */
+#define MAX77693_MUIC_CTRL1_DN1DP2	((0x1 << 3) | 0x1)
+#define MAX77693_MUIC_CTRL1_UT1UR2	((0x3 << 3) | 0x3)
+#define MAX77693_MUIC_CTRL1_ADN1ADP2	((0x4 << 3) | 0x4)
+#define MAX77693_MUIC_CTRL1_AUT1AUR2	((0x5 << 3) | 0x5)
+#define MAX77693_MUIC_CTRL1_MASK	0xC0
+
+#define MUIC_PATH_USB	0
+#define MUIC_PATH_UART	1
+
+#define MUIC_PATH_CP	0
+#define MUIC_PATH_AP	1
+
+enum muic_path {
+	MUIC_PATH_USB_CP,
+	MUIC_PATH_USB_AP,
+	MUIC_PATH_UART_CP,
+	MUIC_PATH_UART_AP,
+};
+
+/* MAX 777693 MUIC registers */
+enum {
+	MAX77693_MUIC_ID	= 0x00,
+	MAX77693_MUIC_INT1	= 0x01,
+	MAX77693_MUIC_INT2	= 0x02,
+	MAX77693_MUIC_INT3	= 0x03,
+	MAX77693_MUIC_STATUS1	= 0x04,
+	MAX77693_MUIC_STATUS2	= 0x05,
+	MAX77693_MUIC_STATUS3	= 0x06,
+	MAX77693_MUIC_INTMASK1	= 0x07,
+	MAX77693_MUIC_INTMASK2	= 0x08,
+	MAX77693_MUIC_INTMASK3	= 0x09,
+	MAX77693_MUIC_CDETCTRL	= 0x0A,
+	MAX77693_MUIC_CONTROL1	= 0x0C,
+	MAX77693_MUIC_CONTROL2	= 0x0D,
+	MAX77693_MUIC_CONTROL3	= 0x0E,
+
+	MUIC_NUM_OF_REGS	= 0x0F,
+};
+
+#define MAX77693_MUIC_I2C_ADDR	(0x4A >> 1)
+
+int power_muic_init(unsigned int bus);
+#endif /* __MAX77693_MUIC_H_ */
diff --git a/qemu/roms/u-boot/include/power/max77693_pmic.h b/qemu/roms/u-boot/include/power/max77693_pmic.h
new file mode 100644
index 000000000..616d051f1
--- /dev/null
+++ b/qemu/roms/u-boot/include/power/max77693_pmic.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ * Piotr Wilczek <p.wilczek@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MAX77693_PMIC_H_
+#define __MAX77693_PMIC_H_
+
+#include <power/power_chrg.h>
+
+enum {CHARGER_ENABLE, CHARGER_DISABLE};
+
+#define CHARGER_MIN_CURRENT 200
+#define CHARGER_MAX_CURRENT 2000
+
+#define MAX77693_CHG_PREFIX	"max77693-chg:"
+
+/* Registers */
+
+#define MAX77693_CHG_BASE	0xB0
+#define MAX77693_CHG_INT_OK	0xB2
+#define MAX77693_CHG_CNFG_00	0xB7
+#define MAX77693_CHG_CNFG_02	0xB9
+#define MAX77693_CHG_CNFG_06	0xBD
+#define MAX77693_SAFEOUT	0xC6
+
+#define PMIC_NUM_OF_REGS	0xC7
+
+#define MAX77693_CHG_DETBAT	(0x1 << 7)	/* MAX77693_CHG_INT_OK */
+#define MAX77693_CHG_MODE_ON	0x05		/* MAX77693_CHG_CNFG_00 */
+#define MAX77693_CHG_CC		0x3F		/* MAX77693_CHG_CNFG_02	*/
+#define MAX77693_CHG_LOCK	(0x0 << 2)	/* MAX77693_CHG_CNFG_06	*/
+#define MAX77693_CHG_UNLOCK	(0x3 << 2)	/* MAX77693_CHG_CNFG_06	*/
+
+#define MAX77693_ENSAFEOUT1	(1 << 6)
+#define MAX77693_ENSAFEOUT2	(1 << 7)
+
+#define MAX77693_PMIC_I2C_ADDR	(0xCC >> 1)
+
+int pmic_init_max77693(unsigned char bus);
+#endif /* __MAX77693_PMIC_H_ */
diff --git a/qemu/roms/u-boot/include/power/max8997_muic.h b/qemu/roms/u-boot/include/power/max8997_muic.h
new file mode 100644
index 000000000..e20854998
--- /dev/null
+++ b/qemu/roms/u-boot/include/power/max8997_muic.h
@@ -0,0 +1,45 @@
+/*
+ *  Copyright (C) 2012 Samsung Electronics
+ *  Lukasz Majewski <l.majewski@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MAX8997_MUIC_H_
+#define __MAX8997_MUIC_H_
+
+#include <power/power_chrg.h>
+
+/* MAX8997_MUIC_STATUS2 */
+#define MAX8997_MUIC_CHG_NO	0x00
+#define MAX8997_MUIC_CHG_USB	0x01
+#define MAX8997_MUIC_CHG_USB_D	0x02
+#define MAX8997_MUIC_CHG_TA	0x03
+#define MAX8997_MUIC_CHG_TA_500 0x04
+#define MAX8997_MUIC_CHG_TA_1A	0x05
+#define MAX8997_MUIC_CHG_MASK	0x07
+
+/* MAX 8997 MUIC registers */
+enum {
+	MAX8997_MUIC_ID         = 0x00,
+	MAX8997_MUIC_INT1	= 0x01,
+	MAX8997_MUIC_INT2	= 0x02,
+	MAX8997_MUIC_INT3	= 0x03,
+	MAX8997_MUIC_STATUS1	= 0x04,
+	MAX8997_MUIC_STATUS2	= 0x05,
+	MAX8997_MUIC_STATUS3	= 0x06,
+	MAX8997_MUIC_INTMASK1	= 0x07,
+	MAX8997_MUIC_INTMASK2	= 0x08,
+	MAX8997_MUIC_INTMASK3	= 0x09,
+	MAX8997_MUIC_CDETCTRL	= 0x0A,
+	MAX8997_MUIC_CONTROL1	= 0x0C,
+	MAX8997_MUIC_CONTROL2	= 0x0D,
+	MAX8997_MUIC_CONTROL3	= 0x0E,
+
+	MUIC_NUM_OF_REGS = 0x0F,
+};
+
+#define MAX8997_MUIC_I2C_ADDR	(0x4A >> 1)
+
+int power_muic_init(unsigned int bus);
+#endif /* __MAX8997_MUIC_H_ */
diff --git a/qemu/roms/u-boot/include/power/max8997_pmic.h b/qemu/roms/u-boot/include/power/max8997_pmic.h
new file mode 100644
index 000000000..74c5d5438
--- /dev/null
+++ b/qemu/roms/u-boot/include/power/max8997_pmic.h
@@ -0,0 +1,198 @@
+/*
+ *  Copyright (C) 2011 Samsung Electronics
+ *  Lukasz Majewski <l.majewski@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MAX8997_PMIC_H_
+#define __MAX8997_PMIC_H_
+
+/* MAX 8997 registers */
+enum {
+	MAX8997_REG_PMIC_ID0	= 0x00,
+	MAX8997_REG_PMIC_ID1	= 0x01,
+	MAX8997_REG_INTSRC	= 0x02,
+	MAX8997_REG_INT1	= 0x03,
+	MAX8997_REG_INT2	= 0x04,
+	MAX8997_REG_INT3	= 0x05,
+	MAX8997_REG_INT4	= 0x06,
+
+	MAX8997_REG_INT1MSK	= 0x08,
+	MAX8997_REG_INT2MSK	= 0x09,
+	MAX8997_REG_INT3MSK	= 0x0a,
+	MAX8997_REG_INT4MSK	= 0x0b,
+
+	MAX8997_REG_STATUS1	= 0x0d,
+	MAX8997_REG_STATUS2	= 0x0e,
+	MAX8997_REG_STATUS3	= 0x0f,
+	MAX8997_REG_STATUS4	= 0x10,
+
+	MAX8997_REG_MAINCON1	= 0x13,
+	MAX8997_REG_MAINCON2	= 0x14,
+	MAX8997_REG_BUCKRAMP	= 0x15,
+
+	MAX8997_REG_BUCK1CTRL	= 0x18,
+	MAX8997_REG_BUCK1DVS1	= 0x19,
+	MAX8997_REG_BUCK1DVS2	= 0x1a,
+	MAX8997_REG_BUCK1DVS3	= 0x1b,
+	MAX8997_REG_BUCK1DVS4	= 0x1c,
+	MAX8997_REG_BUCK1DVS5	= 0x1d,
+	MAX8997_REG_BUCK1DVS6	= 0x1e,
+	MAX8997_REG_BUCK1DVS7	= 0x1f,
+	MAX8997_REG_BUCK1DVS8	= 0x20,
+	MAX8997_REG_BUCK2CTRL	= 0x21,
+	MAX8997_REG_BUCK2DVS1	= 0x22,
+	MAX8997_REG_BUCK2DVS2	= 0x23,
+	MAX8997_REG_BUCK2DVS3	= 0x24,
+	MAX8997_REG_BUCK2DVS4	= 0x25,
+	MAX8997_REG_BUCK2DVS5	= 0x26,
+	MAX8997_REG_BUCK2DVS6	= 0x27,
+	MAX8997_REG_BUCK2DVS7	= 0x28,
+	MAX8997_REG_BUCK2DVS8	= 0x29,
+	MAX8997_REG_BUCK3CTRL	= 0x2a,
+	MAX8997_REG_BUCK3DVS	= 0x2b,
+	MAX8997_REG_BUCK4CTRL	= 0x2c,
+	MAX8997_REG_BUCK4DVS	= 0x2d,
+	MAX8997_REG_BUCK5CTRL	= 0x2e,
+	MAX8997_REG_BUCK5DVS1	= 0x2f,
+	MAX8997_REG_BUCK5DVS2	= 0x30,
+	MAX8997_REG_BUCK5DVS3	= 0x31,
+	MAX8997_REG_BUCK5DVS4	= 0x32,
+	MAX8997_REG_BUCK5DVS5	= 0x33,
+	MAX8997_REG_BUCK5DVS6	= 0x34,
+	MAX8997_REG_BUCK5DVS7	= 0x35,
+	MAX8997_REG_BUCK5DVS8	= 0x36,
+	MAX8997_REG_BUCK6CTRL	= 0x37,
+	MAX8997_REG_BUCK6BPSKIPCTRL	= 0x38,
+	MAX8997_REG_BUCK7CTRL	= 0x39,
+	MAX8997_REG_BUCK7DVS	= 0x3a,
+	MAX8997_REG_LDO1CTRL	= 0x3b,
+	MAX8997_REG_LDO2CTRL	= 0x3c,
+	MAX8997_REG_LDO3CTRL	= 0x3d,
+	MAX8997_REG_LDO4CTRL	= 0x3e,
+	MAX8997_REG_LDO5CTRL	= 0x3f,
+	MAX8997_REG_LDO6CTRL	= 0x40,
+	MAX8997_REG_LDO7CTRL	= 0x41,
+	MAX8997_REG_LDO8CTRL	= 0x42,
+	MAX8997_REG_LDO9CTRL	= 0x43,
+	MAX8997_REG_LDO10CTRL	= 0x44,
+	MAX8997_REG_LDO11CTRL	= 0x45,
+	MAX8997_REG_LDO12CTRL	= 0x46,
+	MAX8997_REG_LDO13CTRL	= 0x47,
+	MAX8997_REG_LDO14CTRL	= 0x48,
+	MAX8997_REG_LDO15CTRL	= 0x49,
+	MAX8997_REG_LDO16CTRL	= 0x4a,
+	MAX8997_REG_LDO17CTRL	= 0x4b,
+	MAX8997_REG_LDO18CTRL	= 0x4c,
+	MAX8997_REG_LDO21CTRL	= 0x4d,
+
+	MAX8997_REG_MBCCTRL1	= 0x50,
+	MAX8997_REG_MBCCTRL2	= 0x51,
+	MAX8997_REG_MBCCTRL3	= 0x52,
+	MAX8997_REG_MBCCTRL4	= 0x53,
+	MAX8997_REG_MBCCTRL5	= 0x54,
+	MAX8997_REG_MBCCTRL6	= 0x55,
+	MAX8997_REG_OTPCGHCVS	= 0x56,
+
+	MAX8997_REG_SAFEOUTCTRL = 0x5a,
+
+	MAX8997_REG_LBCNFG1	= 0x5e,
+	MAX8997_REG_LBCNFG2	= 0x5f,
+	MAX8997_REG_BBCCTRL	= 0x60,
+
+	MAX8997_REG_FLASH1_CUR	= 0x63, /* 0x63 ~ 0x6e for FLASH */
+	MAX8997_REG_FLASH2_CUR	= 0x64,
+	MAX8997_REG_MOVIE_CUR	= 0x65,
+	MAX8997_REG_GSMB_CUR	= 0x66,
+	MAX8997_REG_BOOST_CNTL	= 0x67,
+	MAX8997_REG_LEN_CNTL	= 0x68,
+	MAX8997_REG_FLASH_CNTL	= 0x69,
+	MAX8997_REG_WDT_CNTL	= 0x6a,
+	MAX8997_REG_MAXFLASH1	= 0x6b,
+	MAX8997_REG_MAXFLASH2	= 0x6c,
+	MAX8997_REG_FLASHSTATUS	= 0x6d,
+	MAX8997_REG_FLASHSTATUSMASK	= 0x6e,
+
+	MAX8997_REG_GPIOCNTL1	= 0x70,
+	MAX8997_REG_GPIOCNTL2	= 0x71,
+	MAX8997_REG_GPIOCNTL3	= 0x72,
+	MAX8997_REG_GPIOCNTL4	= 0x73,
+	MAX8997_REG_GPIOCNTL5	= 0x74,
+	MAX8997_REG_GPIOCNTL6	= 0x75,
+	MAX8997_REG_GPIOCNTL7	= 0x76,
+	MAX8997_REG_GPIOCNTL8	= 0x77,
+	MAX8997_REG_GPIOCNTL9	= 0x78,
+	MAX8997_REG_GPIOCNTL10	= 0x79,
+	MAX8997_REG_GPIOCNTL11	= 0x7a,
+	MAX8997_REG_GPIOCNTL12	= 0x7b,
+
+	MAX8997_REG_LDO1CONFIG	= 0x80,
+	MAX8997_REG_LDO2CONFIG	= 0x81,
+	MAX8997_REG_LDO3CONFIG	= 0x82,
+	MAX8997_REG_LDO4CONFIG	= 0x83,
+	MAX8997_REG_LDO5CONFIG	= 0x84,
+	MAX8997_REG_LDO6CONFIG	= 0x85,
+	MAX8997_REG_LDO7CONFIG	= 0x86,
+	MAX8997_REG_LDO8CONFIG	= 0x87,
+	MAX8997_REG_LDO9CONFIG	= 0x88,
+	MAX8997_REG_LDO10CONFIG	= 0x89,
+	MAX8997_REG_LDO11CONFIG	= 0x8a,
+	MAX8997_REG_LDO12CONFIG	= 0x8b,
+	MAX8997_REG_LDO13CONFIG	= 0x8c,
+	MAX8997_REG_LDO14CONFIG	= 0x8d,
+	MAX8997_REG_LDO15CONFIG	= 0x8e,
+	MAX8997_REG_LDO16CONFIG	= 0x8f,
+	MAX8997_REG_LDO17CONFIG	= 0x90,
+	MAX8997_REG_LDO18CONFIG	= 0x91,
+	MAX8997_REG_LDO21CONFIG	= 0x92,
+
+	MAX8997_REG_DVSOKTIMER1	= 0x97,
+	MAX8997_REG_DVSOKTIMER2	= 0x98,
+	MAX8997_REG_DVSOKTIMER4	= 0x99,
+	MAX8997_REG_DVSOKTIMER5	= 0x9a,
+
+	PMIC_NUM_OF_REGS = 0x9b,
+};
+
+#define ACTDISSAFEO1 (1 << 4)
+#define ACTDISSAFEO2 (1 << 5)
+#define ENSAFEOUT1 (1 << 6)
+#define ENSAFEOUT2 (1 << 7)
+
+#define ENBUCK (1 << 0)
+#define ACTIVE_DISCHARGE (1 << 3)
+#define GNSLCT (1 << 2)
+#define LDO_ADE (1 << 1)
+#define SAFEOUT_4_85V 0x00
+#define SAFEOUT_4_90V 0x01
+#define SAFEOUT_4_95V 0x02
+#define SAFEOUT_3_30V 0x03
+
+/* Charger */
+enum {CHARGER_ENABLE, CHARGER_DISABLE};
+#define DETBAT                  (1 << 2)
+#define MBCICHFCSET             (1 << 4)
+#define MBCHOSTEN               (1 << 6)
+#define VCHGR_FC                (1 << 7)
+
+#define CHARGER_MIN_CURRENT 200
+#define CHARGER_MAX_CURRENT 950
+#define CHARGER_CURRENT_RESOLUTION 50
+
+#define MAX8997_I2C_ADDR        (0xCC >> 1)
+#define MAX8997_RTC_ADDR	(0x0C >> 1)
+#define MAX8997_MUIC_ADDR	(0x4A >> 1)
+#define MAX8997_FG_ADDR	(0x6C >> 1)
+
+enum {
+	LDO_OFF = 0,
+	LDO_ON = 1,
+
+	DIS_LDO = (0x00 << 6),
+	EN_LDO = (0x3 << 6),
+};
+
+#define MAX8997_LDO_MAX_VAL 0x3F
+unsigned char max8997_reg_ldo(int uV);
+#endif /* __MAX8997_PMIC_H_ */
diff --git a/qemu/roms/u-boot/include/power/max8998_pmic.h b/qemu/roms/u-boot/include/power/max8998_pmic.h
new file mode 100644
index 000000000..03d06e8a5
--- /dev/null
+++ b/qemu/roms/u-boot/include/power/max8998_pmic.h
@@ -0,0 +1,72 @@
+/*
+ *  Copyright (C) 2011 Samsung Electronics
+ *  Lukasz Majewski <l.majewski@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MAX8998_PMIC_H_
+#define __MAX8998_PMIC_H_
+
+/* MAX 8998 registers */
+enum {
+	MAX8998_REG_IRQ1,
+	MAX8998_REG_IRQ2,
+	MAX8998_REG_IRQ3,
+	MAX8998_REG_IRQ4,
+	MAX8998_REG_IRQM1,
+	MAX8998_REG_IRQM2,
+	MAX8998_REG_IRQM3,
+	MAX8998_REG_IRQM4,
+	MAX8998_REG_STATUS1,
+	MAX8998_REG_STATUS2,
+	MAX8998_REG_STATUSM1,
+	MAX8998_REG_STATUSM2,
+	MAX8998_REG_CHGR1,
+	MAX8998_REG_CHGR2,
+	MAX8998_REG_LDO_ACTIVE_DISCHARGE1,
+	MAX8998_REG_LDO_ACTIVE_DISCHARGE2,
+	MAX8998_REG_BUCK_ACTIVE_DISCHARGE3,
+	MAX8998_REG_ONOFF1,
+	MAX8998_REG_ONOFF2,
+	MAX8998_REG_ONOFF3,
+	MAX8998_REG_ONOFF4,
+	MAX8998_REG_BUCK1_VOLTAGE1,
+	MAX8998_REG_BUCK1_VOLTAGE2,
+	MAX8998_REG_BUCK1_VOLTAGE3,
+	MAX8998_REG_BUCK1_VOLTAGE4,
+	MAX8998_REG_BUCK2_VOLTAGE1,
+	MAX8998_REG_BUCK2_VOLTAGE2,
+	MAX8998_REG_BUCK3,
+	MAX8998_REG_BUCK4,
+	MAX8998_REG_LDO2_LDO3,
+	MAX8998_REG_LDO4,
+	MAX8998_REG_LDO5,
+	MAX8998_REG_LDO6,
+	MAX8998_REG_LDO7,
+	MAX8998_REG_LDO8_LDO9,
+	MAX8998_REG_LDO10_LDO11,
+	MAX8998_REG_LDO12,
+	MAX8998_REG_LDO13,
+	MAX8998_REG_LDO14,
+	MAX8998_REG_LDO15,
+	MAX8998_REG_LDO16,
+	MAX8998_REG_LDO17,
+	MAX8998_REG_BKCHR,
+	MAX8998_REG_LBCNFG1,
+	MAX8998_REG_LBCNFG2,
+	PMIC_NUM_OF_REGS,
+};
+
+#define MAX8998_LDO3		(1 << 2)
+#define MAX8998_LDO4		(1 << 1)
+#define MAX8998_LDO7		(1 << 6)
+#define MAX8998_LDO8		(1 << 5)
+#define MAX8998_LDO17		(1 << 4)
+#define MAX8998_SAFEOUT1	(1 << 4)
+
+#define MAX8998_I2C_ADDR        (0xCC >> 1)
+
+enum { LDO_OFF, LDO_ON };
+
+#endif /* __MAX8998_PMIC_H_ */
diff --git a/qemu/roms/u-boot/include/power/pfuze100_pmic.h b/qemu/roms/u-boot/include/power/pfuze100_pmic.h
new file mode 100644
index 000000000..2a9032a1f
--- /dev/null
+++ b/qemu/roms/u-boot/include/power/pfuze100_pmic.h
@@ -0,0 +1,96 @@
+/*
+ *  Copyright (C) 2014 Gateworks Corporation
+ *  Tim Harvey <tharvey@gateworks.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __PFUZE100_PMIC_H_
+#define __PFUZE100_PMIC_H_
+
+/* PFUZE100 registers */
+enum {
+	PFUZE100_DEVICEID	= 0x00,
+	PFUZE100_REVID		= 0x03,
+	PFUZE100_FABID		= 0x04,
+
+	PFUZE100_SW1ABVOL	= 0x20,
+	PFUZE100_SW1CVOL	= 0x2e,
+	PFUZE100_SW2VOL		= 0x35,
+	PFUZE100_SW3AVOL	= 0x3c,
+	PFUZE100_SW3BVOL	= 0x43,
+	PFUZE100_SW4VOL		= 0x4a,
+	PFUZE100_SWBSTCON1	= 0x66,
+	PFUZE100_VREFDDRCON	= 0x6a,
+	PFUZE100_VSNVSVOL	= 0x6b,
+	PFUZE100_VGEN1VOL	= 0x6c,
+	PFUZE100_VGEN2VOL	= 0x6d,
+	PFUZE100_VGEN3VOL	= 0x6e,
+	PFUZE100_VGEN4VOL	= 0x6f,
+	PFUZE100_VGEN5VOL	= 0x70,
+	PFUZE100_VGEN6VOL	= 0x71,
+
+	PMIC_NUM_OF_REGS	= 0x7f,
+};
+
+/*
+ * LDO Configuration
+ */
+
+/* VGEN1/2 Voltage Configuration */
+#define LDOA_0_80V	0
+#define LDOA_0_85V	1
+#define LDOA_0_90V	2
+#define LDOA_0_95V	3
+#define LDOA_1_00V	4
+#define LDOA_1_05V	5
+#define LDOA_1_10V	6
+#define LDOA_1_15V	7
+#define LDOA_1_20V	8
+#define LDOA_1_25V	9
+#define LDOA_1_30V	10
+#define LDOA_1_35V	11
+#define LDOA_1_40V	12
+#define LDOA_1_45V	13
+#define LDOA_1_50V	14
+#define LDOA_1_55V	15
+
+/* VGEN3/4/5/6 Voltage Configuration */
+#define LDOB_1_80V	0
+#define LDOB_1_90V	1
+#define LDOB_2_00V	2
+#define LDOB_2_10V	3
+#define LDOB_2_20V	4
+#define LDOB_2_30V	5
+#define LDOB_2_40V	6
+#define LDOB_2_50V	7
+#define LDOB_2_60V	8
+#define LDOB_2_70V	9
+#define LDOB_2_80V	10
+#define LDOB_2_90V	11
+#define LDOB_3_00V	12
+#define LDOB_3_10V	13
+#define LDOB_3_20V	14
+#define LDOB_3_30V	15
+
+#define LDO_VOL_MASK	0xf
+#define LDO_EN		4
+
+/*
+ * Boost Regulator
+ */
+
+/* SWBST Output Voltage */
+#define SWBST_5_00V	0
+#define SWBST_5_05V	1
+#define SWBST_5_10V	2
+#define SWBST_5_15V	3
+
+#define SWBST_VOL_MASK	0x3
+#define SWBST_MODE_MASK	0x6
+#define SWBST_MODE_OFF	(2 << 0)
+#define SWBST_MODE_PFM	(2 << 1)
+#define SWBST_MODE_AUTO	(2 << 2)
+#define SWBST_MODE_APS	(2 << 3)
+
+#endif
diff --git a/qemu/roms/u-boot/include/power/pmic.h b/qemu/roms/u-boot/include/power/pmic.h
new file mode 100644
index 000000000..8f282dd2f
--- /dev/null
+++ b/qemu/roms/u-boot/include/power/pmic.h
@@ -0,0 +1,92 @@
+/*
+ *  Copyright (C) 2011-2012 Samsung Electronics
+ *  Lukasz Majewski <l.majewski@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CORE_PMIC_H_
+#define __CORE_PMIC_H_
+
+#include <linux/list.h>
+#include <i2c.h>
+#include <power/power_chrg.h>
+
+enum { PMIC_I2C, PMIC_SPI, PMIC_NONE};
+enum { I2C_PMIC, I2C_NUM, };
+enum { PMIC_READ, PMIC_WRITE, };
+enum { PMIC_SENSOR_BYTE_ORDER_LITTLE, PMIC_SENSOR_BYTE_ORDER_BIG, };
+
+struct p_i2c {
+	unsigned char addr;
+	unsigned char *buf;
+	unsigned char tx_num;
+};
+
+struct p_spi {
+	unsigned int cs;
+	unsigned int mode;
+	unsigned int bitlen;
+	unsigned int clk;
+	unsigned int flags;
+	u32 (*prepare_tx)(u32 reg, u32 *val, u32 write);
+};
+
+struct pmic;
+struct power_fg {
+	int (*fg_battery_check) (struct pmic *p, struct pmic *bat);
+	int (*fg_battery_update) (struct pmic *p, struct pmic *bat);
+};
+
+struct power_chrg {
+	int (*chrg_type) (struct pmic *p);
+	int (*chrg_bat_present) (struct pmic *p);
+	int (*chrg_state) (struct pmic *p, int state, int current);
+};
+
+struct power_battery {
+	struct battery *bat;
+	int (*battery_init) (struct pmic *bat, struct pmic *p1,
+			     struct pmic *p2, struct pmic *p3);
+	int (*battery_charge) (struct pmic *bat);
+	/* Keep info about power devices involved with battery operation */
+	struct pmic *chrg, *fg, *muic;
+};
+
+struct pmic {
+	const char *name;
+	unsigned char bus;
+	unsigned char interface;
+	unsigned char sensor_byte_order;
+	unsigned int number_of_regs;
+	union hw {
+		struct p_i2c i2c;
+		struct p_spi spi;
+	} hw;
+
+	void (*low_power_mode) (void);
+	struct power_battery *pbat;
+	struct power_chrg *chrg;
+	struct power_fg *fg;
+
+	struct pmic *parent;
+	struct list_head list;
+};
+
+int pmic_init(unsigned char bus);
+int pmic_dialog_init(unsigned char bus);
+int check_reg(struct pmic *p, u32 reg);
+struct pmic *pmic_alloc(void);
+struct pmic *pmic_get(const char *s);
+int pmic_probe(struct pmic *p);
+int pmic_reg_read(struct pmic *p, u32 reg, u32 *val);
+int pmic_reg_write(struct pmic *p, u32 reg, u32 val);
+int pmic_set_output(struct pmic *p, u32 reg, int ldo, int on);
+
+#define pmic_i2c_addr (p->hw.i2c.addr)
+#define pmic_i2c_tx_num (p->hw.i2c.tx_num)
+
+#define pmic_spi_bitlen (p->hw.spi.bitlen)
+#define pmic_spi_flags (p->hw.spi.flags)
+
+#endif /* __CORE_PMIC_H_ */
diff --git a/qemu/roms/u-boot/include/power/power_chrg.h b/qemu/roms/u-boot/include/power/power_chrg.h
new file mode 100644
index 000000000..8fa5c66ad
--- /dev/null
+++ b/qemu/roms/u-boot/include/power/power_chrg.h
@@ -0,0 +1,27 @@
+/*
+ *  Copyright (C) 2012 Samsung Electronics
+ *  Lukasz Majewski <l.majewski@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __POWER_CHARGER_H_
+#define __POWER_CHARGER_H_
+
+/* Type of available chargers */
+enum {
+	CHARGER_NO = 0,
+	CHARGER_TA,
+	CHARGER_USB,
+	CHARGER_TA_500,
+	CHARGER_UNKNOWN,
+};
+
+enum {
+	UNKNOWN,
+	EXT_SOURCE,
+	CHARGE,
+	NORMAL,
+};
+
+#endif /* __POWER_CHARGER_H_ */
diff --git a/qemu/roms/u-boot/include/power/tps65217.h b/qemu/roms/u-boot/include/power/tps65217.h
new file mode 100644
index 000000000..297c4cbd9
--- /dev/null
+++ b/qemu/roms/u-boot/include/power/tps65217.h
@@ -0,0 +1,83 @@
+/*
+ * (C) Copyright 2011-2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * For more details, please see the TRM at http://www.ti.com/product/tps65217a
+ */
+
+#ifndef __POWER_TPS65217_H__
+#define __POWER_TPS65217_H__
+
+/* I2C chip address */
+#define TPS65217_CHIP_PM			0x24
+
+/* Registers */
+enum {
+	TPS65217_CHIPID				= 0x00,
+	TPS65217_POWER_PATH,
+	TPS65217_INTERRUPT,
+	TPS65217_CHGCONFIG0,
+	TPS65217_CHGCONFIG1,
+	TPS65217_CHGCONFIG2,
+	TPS65217_CHGCONFIG3,
+	TPS65217_WLEDCTRL1,
+	TPS65217_WLEDCTRL2,
+	TPS65217_MUXCTRL,
+	TPS65217_STATUS,
+	TPS65217_PASSWORD,
+	TPS65217_PGOOD,
+	TPS65217_DEFPG,
+	TPS65217_DEFDCDC1,
+	TPS65217_DEFDCDC2,
+	TPS65217_DEFDCDC3,
+	TPS65217_DEFSLEW,
+	TPS65217_DEFLDO1,
+	TPS65217_DEFLDO2,
+	TPS65217_DEFLS1,
+	TPS65217_DEFLS2,
+	TPS65217_ENABLE,
+	TPS65217_DEFUVLO,
+	TPS65217_SEQ1,
+	TPS65217_SEQ2,
+	TPS65217_SEQ3,
+	TPS65217_SEQ4,
+	TPS65217_SEQ5,
+	TPS65217_SEQ6,
+	TPS65217_PMIC_NUM_OF_REGS,
+};
+
+#define TPS65217_PROT_LEVEL_NONE		0x00
+#define TPS65217_PROT_LEVEL_1			0x01
+#define TPS65217_PROT_LEVEL_2			0x02
+
+#define TPS65217_PASSWORD_LOCK_FOR_WRITE	0x00
+#define TPS65217_PASSWORD_UNLOCK		0x7D
+
+#define TPS65217_DCDC_GO			0x80
+
+#define TPS65217_MASK_ALL_BITS			0xFF
+
+#define TPS65217_USB_INPUT_CUR_LIMIT_MASK	0x03
+#define TPS65217_USB_INPUT_CUR_LIMIT_100MA	0x00
+#define TPS65217_USB_INPUT_CUR_LIMIT_500MA	0x01
+#define TPS65217_USB_INPUT_CUR_LIMIT_1300MA	0x02
+#define TPS65217_USB_INPUT_CUR_LIMIT_1800MA	0x03
+
+#define TPS65217_DCDC_VOLT_SEL_1125MV		0x09
+#define TPS65217_DCDC_VOLT_SEL_1275MV		0x0F
+#define TPS65217_DCDC_VOLT_SEL_1325MV		0x11
+
+#define TPS65217_LDO_MASK			0x1F
+#define TPS65217_LDO_VOLTAGE_OUT_1_8		0x06
+#define TPS65217_LDO_VOLTAGE_OUT_3_3		0x1F
+
+#define TPS65217_PWR_SRC_USB_BITMASK		0x4
+#define TPS65217_PWR_SRC_AC_BITMASK		0x8
+
+int tps65217_reg_read(uchar src_reg, uchar *src_val);
+int tps65217_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val,
+		       uchar mask);
+int tps65217_voltage_update(uchar dc_cntrl_reg, uchar volt_sel);
+#endif	/* __POWER_TPS65217_H__ */
diff --git a/qemu/roms/u-boot/include/power/tps65910.h b/qemu/roms/u-boot/include/power/tps65910.h
new file mode 100644
index 000000000..ca8430145
--- /dev/null
+++ b/qemu/roms/u-boot/include/power/tps65910.h
@@ -0,0 +1,77 @@
+/*
+ * (C) Copyright 2011-2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * For more details, please see the TRM at http://www.ti.com/product/tps65910
+ */
+#ifndef __POWER_TPS65910_H__
+#define __POWER_TPS65910_H__
+
+#define MPU     0
+#define CORE    1
+
+#define TPS65910_SR_I2C_ADDR				0x12
+#define TPS65910_CTRL_I2C_ADDR				0x2D
+
+/* PMIC Register offsets */
+enum {
+	TPS65910_VDD1_REG				= 0x21,
+	TPS65910_VDD1_OP_REG				= 0x22,
+	TPS65910_VDD2_REG				= 0x24,
+	TPS65910_VDD2_OP_REG				= 0x25,
+	TPS65910_DEVCTRL_REG				= 0x3F,
+};
+
+/* VDD2 & VDD1 control register (VDD2_REG & VDD1_REG) */
+#define TPS65910_VGAIN_SEL_MASK				(0x3 << 6)
+#define TPS65910_ILMAX_MASK				(0x1 << 5)
+#define TPS65910_TSTEP_MASK				(0x7 << 2)
+#define TPS65910_ST_MASK				(0x3)
+
+#define TPS65910_REG_VGAIN_SEL_X1			(0x0 << 6)
+#define TPS65910_REG_VGAIN_SEL_X1_0			(0x1 << 6)
+#define TPS65910_REG_VGAIN_SEL_X3			(0x2 << 6)
+#define TPS65910_REG_VGAIN_SEL_X4			(0x3 << 6)
+
+#define TPS65910_REG_ILMAX_1_0_A			(0x0 << 5)
+#define TPS65910_REG_ILMAX_1_5_A			(0x1 << 5)
+
+#define TPS65910_REG_TSTEP_				(0x0 << 2)
+#define TPS65910_REG_TSTEP_12_5				(0x1 << 2)
+#define TPS65910_REG_TSTEP_9_4				(0x2 << 2)
+#define TPS65910_REG_TSTEP_7_5				(0x3 << 2)
+#define TPS65910_REG_TSTEP_6_25				(0x4 << 2)
+#define TPS65910_REG_TSTEP_4_7				(0x5 << 2)
+#define TPS65910_REG_TSTEP_3_12				(0x6 << 2)
+#define TPS65910_REG_TSTEP_2_5				(0x7 << 2)
+
+#define TPS65910_REG_ST_OFF				(0x0)
+#define TPS65910_REG_ST_ON_HI_POW			(0x1)
+#define TPS65910_REG_ST_OFF_1				(0x2)
+#define TPS65910_REG_ST_ON_LOW_POW			(0x3)
+
+
+/* VDD2 & VDD1 voltage selection register. (VDD2_OP_REG & VDD1_OP_REG) */
+#define TPS65910_OP_REG_SEL				(0x7F)
+
+#define TPS65910_OP_REG_CMD_MASK			(0x1 << 7)
+#define TPS65910_OP_REG_CMD_OP				(0x0 << 7)
+#define TPS65910_OP_REG_CMD_SR				(0x1 << 7)
+
+#define TPS65910_OP_REG_SEL_MASK			(0x7F)
+#define TPS65910_OP_REG_SEL_0_9_5			(0x1F)	/* 0.9500 V */
+#define TPS65910_OP_REG_SEL_1_1_3			(0x2E)	/* 1.1375 V */
+#define TPS65910_OP_REG_SEL_1_2_0			(0x33)	/* 1.2000 V */
+#define TPS65910_OP_REG_SEL_1_2_6			(0x38)	/* 1.2625 V */
+#define TPS65910_OP_REG_SEL_1_3_2_5			(0x3D)	/* 1.3250 V */
+
+/* Device control register . (DEVCTRL_REG) */
+#define TPS65910_DEVCTRL_REG_SR_CTL_I2C_MASK		(0x1 << 4)
+#define TPS65910_DEVCTRL_REG_SR_CTL_I2C_SEL_SR_I2C	(0x0 << 4)
+#define TPS65910_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C	(0x1 << 4)
+
+int tps65910_set_i2c_control(void);
+int tps65910_voltage_update(unsigned int module, unsigned char vddx_op_vol_sel);
+#endif	/* __POWER_TPS65910_H__ */
diff --git a/qemu/roms/u-boot/include/ppc_asm.tmpl b/qemu/roms/u-boot/include/ppc_asm.tmpl
new file mode 100644
index 000000000..5fcef9ceb
--- /dev/null
+++ b/qemu/roms/u-boot/include/ppc_asm.tmpl
@@ -0,0 +1,283 @@
+/*
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * This file contains all the macros and symbols which define
+ * a PowerPC assembly language environment.
+ */
+#ifndef	__PPC_ASM_TMPL__
+#define __PPC_ASM_TMPL__
+
+/***************************************************************************
+ *
+ * These definitions simplify the ugly declarations necessary for GOT
+ * definitions.
+ *
+ * Stolen from prepboot/bootldr.h, (C) 1998 Gabriel Paubert, paubert@iram.es
+ *
+ * Uses r12 to access the GOT
+ */
+
+#define START_GOT			\
+	.section	".got2","aw";	\
+.LCTOC1 = .+32768
+
+#define END_GOT				\
+	.text
+
+#define GET_GOT				\
+	bl	1f		;	\
+	.text	2		;	\
+0:	.long	.LCTOC1-1f	;	\
+	.text			;	\
+1:	mflr	r12		;	\
+	lwz	r0,0b-1b(r12)	;	\
+	add	r12,r0,r12	;
+
+#define GOT_ENTRY(NAME)		.L_ ## NAME = . - .LCTOC1 ; .long NAME
+
+#define GOT(NAME)		.L_ ## NAME (r12)
+
+
+/***************************************************************************
+ * Register names
+ */
+#define	r0	0
+#define	r1	1
+#define	r2	2
+#define	r3	3
+#define	r4	4
+#define	r5	5
+#define	r6	6
+#define	r7	7
+#define	r8	8
+#define	r9	9
+#define	r10	10
+#define	r11	11
+#define	r12	12
+#define	r13	13
+#define	r14	14
+#define	r15	15
+#define	r16	16
+#define	r17	17
+#define	r18	18
+#define	r19	19
+#define	r20	20
+#define	r21	21
+#define	r22	22
+#define	r23	23
+#define	r24	24
+#define	r25	25
+#define	r26	26
+#define	r27	27
+#define	r28	28
+#define	r29	29
+#define	r30	30
+#define	r31	31
+
+
+#if defined(CONFIG_8xx) || defined(CONFIG_MPC824X)
+
+/* Some special registers */
+
+#define ICR	148	/* Interrupt Cause Register (37-44) */
+#define DER	149
+#define COUNTA	150	/* Breakpoint Counter	    (37-44) */
+#define COUNTB	151	/* Breakpoint Counter	    (37-44) */
+#define LCTRL1	156	/* Load/Store Support	    (37-40) */
+#define LCTRL2	157	/* Load/Store Support	    (37-41) */
+#define ICTRL	158
+
+#endif	/* CONFIG_8xx, CONFIG_MPC824X */
+
+
+#if  defined(CONFIG_5xx)
+/* Some special purpose registers */
+#define DER	149		/* Debug Enable Register		*/
+#define COUNTA	150		/* Breakpoint Counter			*/
+#define COUNTB	151		/* Breakpoint Counter			*/
+#define LCTRL1	156		/* Load/Store Support			*/
+#define LCTRL2	157		/* Load/Store Support			*/
+#define ICTRL	158		/* I-Bus Support Control Register	*/
+#define EID	81
+#endif	/* CONFIG_5xx */
+
+#if defined(CONFIG_8xx)
+
+/* Registers in the processor's internal memory map that we use.
+*/
+#define SYPCR	0x00000004
+#define BR0	0x00000100
+#define OR0	0x00000104
+#define BR1	0x00000108
+#define OR1	0x0000010c
+#define BR2	0x00000110
+#define OR2	0x00000114
+#define BR3	0x00000118
+#define OR3	0x0000011c
+#define BR4	0x00000120
+#define OR4	0x00000124
+
+#define MAR	0x00000164
+#define MCR	0x00000168
+#define MAMR	0x00000170
+#define MBMR	0x00000174
+#define MSTAT	0x00000178
+#define MPTPR	0x0000017a
+#define MDR	0x0000017c
+
+#define TBSCR	0x00000200
+#define TBREFF0	0x00000204
+
+#define PLPRCR	0x00000284
+
+#elif defined(CONFIG_MPC8260)
+
+#define HID2		1011
+
+#define HID0_IFEM	(1<<7)
+
+#define HID0_ICE_BITPOS	16
+#define HID0_DCE_BITPOS	17
+
+#define IM_REGBASE	0x10000
+#define IM_SYPCR	(IM_REGBASE+0x0004)
+#define IM_SWSR		(IM_REGBASE+0x000e)
+#define IM_BR0		(IM_REGBASE+0x0100)
+#define IM_OR0		(IM_REGBASE+0x0104)
+#define IM_BR1		(IM_REGBASE+0x0108)
+#define IM_OR1		(IM_REGBASE+0x010c)
+#define IM_BR2		(IM_REGBASE+0x0110)
+#define IM_OR2		(IM_REGBASE+0x0114)
+#define IM_MPTPR	(IM_REGBASE+0x0184)
+#define IM_PSDMR	(IM_REGBASE+0x0190)
+#define IM_PSRT		(IM_REGBASE+0x019c)
+#define IM_IMMR		(IM_REGBASE+0x01a8)
+#define IM_SCCR		(IM_REGBASE+0x0c80)
+
+#elif defined(CONFIG_MPC5xxx)
+
+#define HID0_ICE_BITPOS	16
+#define HID0_DCE_BITPOS	17
+
+#endif
+
+#define curptr r2
+
+#define SYNC \
+	sync; \
+	isync
+
+/*
+ * Macros for storing registers into and loading registers from
+ * exception frames.
+ */
+#define SAVE_GPR(n, base)	stw	n,GPR0+4*(n)(base)
+#define SAVE_2GPRS(n, base)	SAVE_GPR(n, base); SAVE_GPR(n+1, base)
+#define SAVE_4GPRS(n, base)	SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
+#define SAVE_8GPRS(n, base)	SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
+#define SAVE_10GPRS(n, base)	SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
+#define REST_GPR(n, base)	lwz	n,GPR0+4*(n)(base)
+#define REST_2GPRS(n, base)	REST_GPR(n, base); REST_GPR(n+1, base)
+#define REST_4GPRS(n, base)	REST_2GPRS(n, base); REST_2GPRS(n+2, base)
+#define REST_8GPRS(n, base)	REST_4GPRS(n, base); REST_4GPRS(n+4, base)
+#define REST_10GPRS(n, base)	REST_8GPRS(n, base); REST_2GPRS(n+8, base)
+
+/*
+ * GCC sometimes accesses words at negative offsets from the stack
+ * pointer, although the SysV ABI says it shouldn't.  To cope with
+ * this, we leave this much untouched space on the stack on exception
+ * entry.
+ */
+#define STACK_UNDERHEAD	64
+
+/*
+ * Exception entry code.  This code runs with address translation
+ * turned off, i.e. using physical addresses.
+ * We assume sprg3 has the physical address of the current
+ * task's thread_struct.
+ */
+#define EXCEPTION_PROLOG(reg1, reg2)	\
+	mtspr	SPRG0,r20;	\
+	mtspr	SPRG1,r21;	\
+	mfcr	r20;		\
+	subi	r21,r1,INT_FRAME_SIZE+STACK_UNDERHEAD;	/* alloc exc. frame */\
+	stw	r20,_CCR(r21);		/* save registers */ \
+	stw	r22,GPR22(r21);	\
+	stw	r23,GPR23(r21);	\
+	mfspr	r20,SPRG0;	\
+	stw	r20,GPR20(r21);	\
+	mfspr	r22,SPRG1;	\
+	stw	r22,GPR21(r21);	\
+	mflr	r20;		\
+	stw	r20,_LINK(r21);	\
+	mfctr	r22;		\
+	stw	r22,_CTR(r21);	\
+	mfspr	r20,XER;	\
+	stw	r20,_XER(r21);	\
+	mfspr	r20, DAR_DEAR;	\
+	stw	r20,_DAR(r21);	\
+	mfspr	r22,reg1;	\
+	mfspr	r23,reg2;	\
+	stw	r0,GPR0(r21);	\
+	stw	r1,GPR1(r21);	\
+	stw	r2,GPR2(r21);	\
+	stw	r1,0(r21);	\
+	mr	r1,r21;			/* set new kernel sp */	\
+	SAVE_4GPRS(3, r21);
+/*
+ * Note: code which follows this uses cr0.eq (set if from kernel),
+ * r21, r22 (SRR0), and r23 (SRR1).
+ */
+
+/*
+ * Exception vectors.
+ *
+ * The data words for `hdlr' and `int_return' are initialized with
+ * OFFSET values only; they must be relocated first before they can
+ * be used!
+ */
+#define COPY_EE(d, s)		rlwimi d,s,0,16,16
+#define NOCOPY(d, s)
+#define EXC_XFER_TEMPLATE(label, hdlr, msr, copyee)	\
+	bl	1f;					\
+1:	mflr    r20;					\
+	lwz	r20,(.L_ ## label)-1b+8(r20);		\
+	mtlr	r20;					\
+	li	r20,msr;				\
+	copyee(r20,r23);				\
+	rlwimi	r20,r23,0,25,25;			\
+	blrl;						\
+.L_ ## label :						\
+	.long	hdlr - _start + _START_OFFSET;		\
+	.long	int_return - _start + _START_OFFSET;	\
+	.long	transfer_to_handler - _start + _START_OFFSET
+
+#define STD_EXCEPTION(n, label, hdlr)				\
+	. = n;							\
+label:								\
+	EXCEPTION_PROLOG(SRR0, SRR1);				\
+	addi	r3,r1,STACK_FRAME_OVERHEAD;			\
+	EXC_XFER_TEMPLATE(label, hdlr, MSR_KERNEL, NOCOPY)	\
+
+#define CRIT_EXCEPTION(n, label, hdlr)				\
+	. = n;							\
+label:								\
+	EXCEPTION_PROLOG(CSRR0, CSRR1);				\
+	addi	r3,r1,STACK_FRAME_OVERHEAD;			\
+	EXC_XFER_TEMPLATE(label, hdlr,				\
+	MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE), NOCOPY)		\
+
+#define MCK_EXCEPTION(n, label, hdlr)				\
+	. = n;							\
+label:								\
+	EXCEPTION_PROLOG(MCSRR0, MCSRR1);			\
+	addi	r3,r1,STACK_FRAME_OVERHEAD;			\
+	EXC_XFER_TEMPLATE(label, hdlr,				\
+	MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE), NOCOPY)		\
+
+#endif	/* __PPC_ASM_TMPL__ */
diff --git a/qemu/roms/u-boot/include/ppc_defs.h b/qemu/roms/u-boot/include/ppc_defs.h
new file mode 100644
index 000000000..f406c33ee
--- /dev/null
+++ b/qemu/roms/u-boot/include/ppc_defs.h
@@ -0,0 +1,75 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * WARNING! This file is automatically generated - DO NOT EDIT!
+ */
+#define	KERNELBASE	-1073741824
+#define	STATE	0
+#define	NEXT_TASK	64
+#define	COUNTER	52
+#define	PROCESSOR	916
+#define	SIGPENDING	8
+#define	TSS	576
+#define	MM	880
+#define	TASK_STRUCT_SIZE	928
+#define	KSP	0
+#define	PG_TABLES	4
+#define	PGD	8
+#define	LAST_SYSCALL	20
+#define	PT_REGS	12
+#define	PF_TRACESYS	32
+#define	TASK_FLAGS	4
+#define	TSS_FPR0	24
+#define	TSS_FPSCR	284
+#define	TSS_SMP_FORK_RET	288
+#define	TASK_UNION_SIZE	8192
+#define	STACK_FRAME_OVERHEAD	16
+#define	INT_FRAME_SIZE	192
+#define	GPR0	16
+#define	GPR1	20
+#define	GPR2	24
+#define	GPR3	28
+#define	GPR4	32
+#define	GPR5	36
+#define	GPR6	40
+#define	GPR7	44
+#define	GPR8	48
+#define	GPR9	52
+#define	GPR10	56
+#define	GPR11	60
+#define	GPR12	64
+#define	GPR13	68
+#define	GPR14	72
+#define	GPR15	76
+#define	GPR16	80
+#define	GPR17	84
+#define	GPR18	88
+#define	GPR19	92
+#define	GPR20	96
+#define	GPR21	100
+#define	GPR22	104
+#define	GPR23	108
+#define	GPR24	112
+#define	GPR25	116
+#define	GPR26	120
+#define	GPR27	124
+#define	GPR28	128
+#define	GPR29	132
+#define	GPR30	136
+#define	GPR31	140
+#define	_NIP	144
+#define	_MSR	148
+#define	_CTR	156
+#define	_LINK	160
+#define	_CCR	168
+#define	_XER	164
+#define	_DAR	180
+#define	_DSISR	184
+#define	ORIG_GPR3	152
+#define	RESULT	188
+#define	TRAP	176
diff --git a/qemu/roms/u-boot/include/ps2mult.h b/qemu/roms/u-boot/include/ps2mult.h
new file mode 100644
index 000000000..1a38733b7
--- /dev/null
+++ b/qemu/roms/u-boot/include/ps2mult.h
@@ -0,0 +1,56 @@
+#ifndef __LINUX_PS2MULT_H
+#define __LINUX_PS2MULT_H
+
+#define kbd_request_region()		ps2mult_init()
+#define kbd_request_irq(handler)	ps2mult_request_irq(handler)
+
+#define kbd_read_input()		ps2mult_read_input()
+#define kbd_read_status()		ps2mult_read_status()
+#define kbd_write_output(val)		ps2mult_write_output(val)
+#define kbd_write_command(val)		ps2mult_write_command(val)
+
+#define aux_request_irq(hand, dev_id)	0
+#define aux_free_irq(dev_id)
+
+#define PS2MULT_KB_SELECTOR		0xA0
+#define PS2MULT_MS_SELECTOR		0xA1
+#define PS2MULT_ESCAPE			0x7D
+#define PS2MULT_BSYNC			0x7E
+#define PS2MULT_SESSION_START		0x55
+#define PS2MULT_SESSION_END		0x56
+
+#define	PS2BUF_SIZE			512	/* power of 2, please */
+
+#ifndef CONFIG_PS2MULT_DELAY
+#define CONFIG_PS2MULT_DELAY	(CONFIG_SYS_HZ/2)	/* Initial delay	*/
+#endif
+
+  /* PS/2 controller interface (include/asm/keyboard.h)
+   */
+extern int ps2mult_init (void);
+extern int ps2mult_request_irq(void (*handler)(void *));
+extern u_char ps2mult_read_input(void);
+extern u_char ps2mult_read_status(void);
+extern void ps2mult_write_output(u_char val);
+extern void ps2mult_write_command(u_char val);
+
+extern void ps2mult_early_init (void);
+extern void ps2mult_callback (int in_cnt);
+
+  /* Simple serial interface
+   */
+extern int ps2ser_init(void);
+extern void ps2ser_putc(int chr);
+extern int ps2ser_getc(void);
+extern int ps2ser_check(void);
+
+
+  /* Serial related stuff
+   */
+struct serial_state {
+	int	baud_base;
+	int	irq;
+	u8	*iomem_base;
+};
+
+#endif /* __LINUX_PS2MULT_H */
diff --git a/qemu/roms/u-boot/include/pwm.h b/qemu/roms/u-boot/include/pwm.h
new file mode 100644
index 000000000..f24f2202f
--- /dev/null
+++ b/qemu/roms/u-boot/include/pwm.h
@@ -0,0 +1,18 @@
+/*
+ * header file for pwm driver.
+ *
+ * Copyright (c) 2011 samsung electronics
+ * Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _pwm_h_
+#define _pwm_h_
+
+int	pwm_init		(int pwm_id, int div, int invert);
+int	pwm_config		(int pwm_id, int duty_ns, int period_ns);
+int	pwm_enable		(int pwm_id);
+void	pwm_disable		(int pwm_id);
+
+#endif /* _pwm_h_ */
diff --git a/qemu/roms/u-boot/include/radeon.h b/qemu/roms/u-boot/include/radeon.h
new file mode 100644
index 000000000..da6c26bbe
--- /dev/null
+++ b/qemu/roms/u-boot/include/radeon.h
@@ -0,0 +1,1988 @@
+#ifndef _RADEON_H
+#define _RADEON_H
+
+
+#define RADEON_REGSIZE			0x4000
+
+
+#define MM_INDEX			0x0000
+#define MM_DATA				0x0004
+#define BUS_CNTL			0x0030
+#define HI_STAT				0x004C
+#define BUS_CNTL1			0x0034
+#define I2C_CNTL_1			0x0094
+#define CONFIG_CNTL			0x00E0
+#define CONFIG_MEMSIZE			0x00F8
+#define CONFIG_APER_0_BASE		0x0100
+#define CONFIG_APER_1_BASE		0x0104
+#define CONFIG_APER_SIZE		0x0108
+#define CONFIG_REG_1_BASE		0x010C
+#define CONFIG_REG_APER_SIZE		0x0110
+#define PAD_AGPINPUT_DELAY		0x0164
+#define PAD_CTLR_STRENGTH		0x0168
+#define PAD_CTLR_UPDATE			0x016C
+#define PAD_CTLR_MISC			0x0aa0
+#define AGP_CNTL			0x0174
+#define BM_STATUS			0x0160
+#define CAP0_TRIG_CNTL			0x0950
+#define CAP1_TRIG_CNTL			0x09c0
+#define VIPH_CONTROL			0x0C40
+#define VENDOR_ID			0x0F00
+#define DEVICE_ID			0x0F02
+#define COMMAND				0x0F04
+#define STATUS				0x0F06
+#define REVISION_ID			0x0F08
+#define REGPROG_INF			0x0F09
+#define SUB_CLASS			0x0F0A
+#define BASE_CODE			0x0F0B
+#define CACHE_LINE			0x0F0C
+#define LATENCY				0x0F0D
+#define HEADER				0x0F0E
+#define BIST				0x0F0F
+#define REG_MEM_BASE			0x0F10
+#define REG_IO_BASE			0x0F14
+#define REG_REG_BASE			0x0F18
+#define ADAPTER_ID			0x0F2C
+#define BIOS_ROM			0x0F30
+#define CAPABILITIES_PTR		0x0F34
+#define INTERRUPT_LINE			0x0F3C
+#define INTERRUPT_PIN			0x0F3D
+#define MIN_GRANT			0x0F3E
+#define MAX_LATENCY			0x0F3F
+#define ADAPTER_ID_W			0x0F4C
+#define PMI_CAP_ID			0x0F50
+#define PMI_NXT_CAP_PTR			0x0F51
+#define PMI_PMC_REG			0x0F52
+#define PM_STATUS			0x0F54
+#define PMI_DATA			0x0F57
+#define AGP_CAP_ID			0x0F58
+#define AGP_STATUS			0x0F5C
+#define AGP_COMMAND			0x0F60
+#define AIC_CTRL			0x01D0
+#define AIC_STAT			0x01D4
+#define AIC_PT_BASE			0x01D8
+#define AIC_LO_ADDR			0x01DC
+#define AIC_HI_ADDR			0x01E0
+#define AIC_TLB_ADDR			0x01E4
+#define AIC_TLB_DATA			0x01E8
+#define DAC_CNTL			0x0058
+#define DAC_CNTL2			0x007c
+#define CRTC_GEN_CNTL			0x0050
+#define MEM_CNTL			0x0140
+#define MC_CNTL				0x0140
+#define EXT_MEM_CNTL			0x0144
+#define MC_TIMING_CNTL			0x0144
+#define MC_AGP_LOCATION			0x014C
+#define MEM_IO_CNTL_A0			0x0178
+#define MEM_REFRESH_CNTL		0x0178
+#define MEM_INIT_LATENCY_TIMER		0x0154
+#define MC_INIT_GFX_LAT_TIMER		0x0154
+#define MEM_SDRAM_MODE_REG		0x0158
+#define AGP_BASE			0x0170
+#define MEM_IO_CNTL_A1			0x017C
+#define MC_READ_CNTL_AB			0x017C
+#define MEM_IO_CNTL_B0			0x0180
+#define MC_INIT_MISC_LAT_TIMER		0x0180
+#define MEM_IO_CNTL_B1			0x0184
+#define MC_IOPAD_CNTL			0x0184
+#define MC_DEBUG			0x0188
+#define MC_STATUS			0x0150
+#define MEM_IO_OE_CNTL			0x018C
+#define MC_CHIP_IO_OE_CNTL_AB		0x018C
+#define MC_FB_LOCATION			0x0148
+/* #define MC_FB_LOCATION		0x0188 */
+#define HOST_PATH_CNTL			0x0130
+#define MEM_VGA_WP_SEL			0x0038
+#define MEM_VGA_RP_SEL			0x003C
+#define HDP_DEBUG			0x0138
+#define SW_SEMAPHORE			0x013C
+#define CRTC2_GEN_CNTL			0x03f8
+#define CRTC2_DISPLAY_BASE_ADDR		0x033c
+#define SURFACE_CNTL			0x0B00
+#define SURFACE0_LOWER_BOUND		0x0B04
+#define SURFACE1_LOWER_BOUND		0x0B14
+#define SURFACE2_LOWER_BOUND		0x0B24
+#define SURFACE3_LOWER_BOUND		0x0B34
+#define SURFACE4_LOWER_BOUND		0x0B44
+#define SURFACE5_LOWER_BOUND		0x0B54
+#define SURFACE6_LOWER_BOUND		0x0B64
+#define SURFACE7_LOWER_BOUND		0x0B74
+#define SURFACE0_UPPER_BOUND		0x0B08
+#define SURFACE1_UPPER_BOUND		0x0B18
+#define SURFACE2_UPPER_BOUND		0x0B28
+#define SURFACE3_UPPER_BOUND		0x0B38
+#define SURFACE4_UPPER_BOUND		0x0B48
+#define SURFACE5_UPPER_BOUND		0x0B58
+#define SURFACE6_UPPER_BOUND		0x0B68
+#define SURFACE7_UPPER_BOUND		0x0B78
+#define SURFACE0_INFO			0x0B0C
+#define SURFACE1_INFO			0x0B1C
+#define SURFACE2_INFO			0x0B2C
+#define SURFACE3_INFO			0x0B3C
+#define SURFACE4_INFO			0x0B4C
+#define SURFACE5_INFO			0x0B5C
+#define SURFACE6_INFO			0x0B6C
+#define SURFACE7_INFO			0x0B7C
+#define SURFACE_ACCESS_FLAGS		0x0BF8
+#define SURFACE_ACCESS_CLR		0x0BFC
+#define GEN_INT_CNTL			0x0040
+#define GEN_INT_STATUS			0x0044
+#define CRTC_EXT_CNTL			0x0054
+#define RB3D_CNTL			0x1C3C
+#define WAIT_UNTIL			0x1720
+#define ISYNC_CNTL			0x1724
+#define RBBM_GUICNTL			0x172C
+#define RBBM_STATUS			0x0E40
+#define RBBM_STATUS_alt_1		0x1740
+#define RBBM_CNTL			0x00EC
+#define RBBM_CNTL_alt_1			0x0E44
+#define RBBM_SOFT_RESET			0x00F0
+#define RBBM_SOFT_RESET_alt_1		0x0E48
+#define NQWAIT_UNTIL			0x0E50
+#define RBBM_DEBUG			0x0E6C
+#define RBBM_CMDFIFO_ADDR		0x0E70
+#define RBBM_CMDFIFO_DATAL		0x0E74
+#define RBBM_CMDFIFO_DATAH		0x0E78
+#define RBBM_CMDFIFO_STAT		0x0E7C
+#define CRTC_STATUS			0x005C
+#define GPIO_VGA_DDC			0x0060
+#define GPIO_DVI_DDC			0x0064
+#define GPIO_MONID			0x0068
+#define GPIO_CRT2_DDC			0x006c
+#define PALETTE_INDEX			0x00B0
+#define PALETTE_DATA			0x00B4
+#define PALETTE_30_DATA			0x00B8
+#define CRTC_H_TOTAL_DISP		0x0200
+#define CRTC_H_SYNC_STRT_WID		0x0204
+#define CRTC_H_SYNC_POL			(1 << 23)
+#define CRTC_V_TOTAL_DISP		0x0208
+#define CRTC_V_SYNC_STRT_WID		0x020C
+#define CRTC_V_SYNC_POL			(1 << 23)
+#define CRTC_VLINE_CRNT_VLINE		0x0210
+#define CRTC_CRNT_FRAME			0x0214
+#define CRTC_GUI_TRIG_VLINE		0x0218
+#define CRTC_DEBUG			0x021C
+#define CRTC_OFFSET_RIGHT		0x0220
+#define CRTC_OFFSET			0x0224
+#define CRTC_OFFSET_CNTL		0x0228
+#define CRTC_PITCH			0x022C
+#define OVR_CLR				0x0230
+#define OVR_WID_LEFT_RIGHT		0x0234
+#define OVR_WID_TOP_BOTTOM		0x0238
+#define DISPLAY_BASE_ADDR		0x023C
+#define SNAPSHOT_VH_COUNTS		0x0240
+#define SNAPSHOT_F_COUNT		0x0244
+#define N_VIF_COUNT			0x0248
+#define SNAPSHOT_VIF_COUNT		0x024C
+#define FP_CRTC_H_TOTAL_DISP		0x0250
+#define FP_CRTC_V_TOTAL_DISP		0x0254
+#define CRT_CRTC_H_SYNC_STRT_WID	0x0258
+#define CRT_CRTC_V_SYNC_STRT_WID	0x025C
+#define CUR_OFFSET			0x0260
+#define CUR_HORZ_VERT_POSN		0x0264
+#define CUR_HORZ_VERT_OFF		0x0268
+#define CUR_CLR0			0x026C
+#define CUR_CLR1			0x0270
+#define FP_HORZ_VERT_ACTIVE		0x0278
+#define CRTC_MORE_CNTL			0x027C
+#define CRTC_H_CUTOFF_ACTIVE_EN		(1<<4)
+#define CRTC_V_CUTOFF_ACTIVE_EN		(1<<5)
+#define DAC_EXT_CNTL			0x0280
+#define FP_GEN_CNTL			0x0284
+#define FP_HORZ_STRETCH			0x028C
+#define FP_VERT_STRETCH			0x0290
+#define FP_H_SYNC_STRT_WID		0x02C4
+#define FP_V_SYNC_STRT_WID		0x02C8
+#define AUX_WINDOW_HORZ_CNTL		0x02D8
+#define AUX_WINDOW_VERT_CNTL		0x02DC
+/* #define DDA_CONFIG			0x02e0 */
+/* #define DDA_ON_OFF			0x02e4 */
+#define DVI_I2C_CNTL_1			0x02e4
+#define GRPH_BUFFER_CNTL		0x02F0
+#define GRPH2_BUFFER_CNTL		0x03F0
+#define VGA_BUFFER_CNTL			0x02F4
+#define OV0_Y_X_START			0x0400
+#define OV0_Y_X_END			0x0404
+#define OV0_PIPELINE_CNTL		0x0408
+#define OV0_REG_LOAD_CNTL		0x0410
+#define OV0_SCALE_CNTL			0x0420
+#define OV0_V_INC			0x0424
+#define OV0_P1_V_ACCUM_INIT		0x0428
+#define OV0_P23_V_ACCUM_INIT		0x042C
+#define OV0_P1_BLANK_LINES_AT_TOP	0x0430
+#define OV0_P23_BLANK_LINES_AT_TOP	0x0434
+#define OV0_BASE_ADDR			0x043C
+#define OV0_VID_BUF0_BASE_ADRS		0x0440
+#define OV0_VID_BUF1_BASE_ADRS		0x0444
+#define OV0_VID_BUF2_BASE_ADRS		0x0448
+#define OV0_VID_BUF3_BASE_ADRS		0x044C
+#define OV0_VID_BUF4_BASE_ADRS		0x0450
+#define OV0_VID_BUF5_BASE_ADRS		0x0454
+#define OV0_VID_BUF_PITCH0_VALUE	0x0460
+#define OV0_VID_BUF_PITCH1_VALUE	0x0464
+#define OV0_AUTO_FLIP_CNTRL		0x0470
+#define OV0_DEINTERLACE_PATTERN		0x0474
+#define OV0_SUBMIT_HISTORY		0x0478
+#define OV0_H_INC			0x0480
+#define OV0_STEP_BY			0x0484
+#define OV0_P1_H_ACCUM_INIT		0x0488
+#define OV0_P23_H_ACCUM_INIT		0x048C
+#define OV0_P1_X_START_END		0x0494
+#define OV0_P2_X_START_END		0x0498
+#define OV0_P3_X_START_END		0x049C
+#define OV0_FILTER_CNTL			0x04A0
+#define OV0_FOUR_TAP_COEF_0		0x04B0
+#define OV0_FOUR_TAP_COEF_1		0x04B4
+#define OV0_FOUR_TAP_COEF_2		0x04B8
+#define OV0_FOUR_TAP_COEF_3		0x04BC
+#define OV0_FOUR_TAP_COEF_4		0x04C0
+#define OV0_FLAG_CNTRL			0x04DC
+#define OV0_SLICE_CNTL			0x04E0
+#define OV0_VID_KEY_CLR_LOW		0x04E4
+#define OV0_VID_KEY_CLR_HIGH		0x04E8
+#define OV0_GRPH_KEY_CLR_LOW		0x04EC
+#define OV0_GRPH_KEY_CLR_HIGH		0x04F0
+#define OV0_KEY_CNTL			0x04F4
+#define OV0_TEST			0x04F8
+#define SUBPIC_CNTL			0x0540
+#define SUBPIC_DEFCOLCON		0x0544
+#define SUBPIC_Y_X_START		0x054C
+#define SUBPIC_Y_X_END			0x0550
+#define SUBPIC_V_INC			0x0554
+#define SUBPIC_H_INC			0x0558
+#define SUBPIC_BUF0_OFFSET		0x055C
+#define SUBPIC_BUF1_OFFSET		0x0560
+#define SUBPIC_LC0_OFFSET		0x0564
+#define SUBPIC_LC1_OFFSET		0x0568
+#define SUBPIC_PITCH			0x056C
+#define SUBPIC_BTN_HLI_COLCON		0x0570
+#define SUBPIC_BTN_HLI_Y_X_START	0x0574
+#define SUBPIC_BTN_HLI_Y_X_END		0x0578
+#define SUBPIC_PALETTE_INDEX		0x057C
+#define SUBPIC_PALETTE_DATA		0x0580
+#define SUBPIC_H_ACCUM_INIT		0x0584
+#define SUBPIC_V_ACCUM_INIT		0x0588
+#define DISP_MISC_CNTL			0x0D00
+#define DAC_MACRO_CNTL			0x0D04
+#define DISP_PWR_MAN			0x0D08
+#define DISP_TEST_DEBUG_CNTL		0x0D10
+#define DISP_HW_DEBUG			0x0D14
+#define DAC_CRC_SIG1			0x0D18
+#define DAC_CRC_SIG2			0x0D1C
+#define OV0_LIN_TRANS_A			0x0D20
+#define OV0_LIN_TRANS_B			0x0D24
+#define OV0_LIN_TRANS_C			0x0D28
+#define OV0_LIN_TRANS_D			0x0D2C
+#define OV0_LIN_TRANS_E			0x0D30
+#define OV0_LIN_TRANS_F			0x0D34
+#define OV0_GAMMA_0_F			0x0D40
+#define OV0_GAMMA_10_1F			0x0D44
+#define OV0_GAMMA_20_3F			0x0D48
+#define OV0_GAMMA_40_7F			0x0D4C
+#define OV0_GAMMA_380_3BF		0x0D50
+#define OV0_GAMMA_3C0_3FF		0x0D54
+#define DISP_MERGE_CNTL			0x0D60
+#define DISP_OUTPUT_CNTL		0x0D64
+#define DISP_LIN_TRANS_GRPH_A		0x0D80
+#define DISP_LIN_TRANS_GRPH_B		0x0D84
+#define DISP_LIN_TRANS_GRPH_C		0x0D88
+#define DISP_LIN_TRANS_GRPH_D		0x0D8C
+#define DISP_LIN_TRANS_GRPH_E		0x0D90
+#define DISP_LIN_TRANS_GRPH_F		0x0D94
+#define DISP_LIN_TRANS_VID_A		0x0D98
+#define DISP_LIN_TRANS_VID_B		0x0D9C
+#define DISP_LIN_TRANS_VID_C		0x0DA0
+#define DISP_LIN_TRANS_VID_D		0x0DA4
+#define DISP_LIN_TRANS_VID_E		0x0DA8
+#define DISP_LIN_TRANS_VID_F		0x0DAC
+#define RMX_HORZ_FILTER_0TAP_COEF	0x0DB0
+#define RMX_HORZ_FILTER_1TAP_COEF	0x0DB4
+#define RMX_HORZ_FILTER_2TAP_COEF	0x0DB8
+#define RMX_HORZ_PHASE			0x0DBC
+#define DAC_EMBEDDED_SYNC_CNTL		0x0DC0
+#define DAC_BROAD_PULSE			0x0DC4
+#define DAC_SKEW_CLKS			0x0DC8
+#define DAC_INCR			0x0DCC
+#define DAC_NEG_SYNC_LEVEL		0x0DD0
+#define DAC_POS_SYNC_LEVEL		0x0DD4
+#define DAC_BLANK_LEVEL			0x0DD8
+#define CLOCK_CNTL_INDEX		0x0008
+#define CLOCK_CNTL_DATA			0x000C
+#define CP_RB_CNTL			0x0704
+#define CP_RB_BASE			0x0700
+#define CP_RB_RPTR_ADDR			0x070C
+#define CP_RB_RPTR			0x0710
+#define CP_RB_WPTR			0x0714
+#define CP_RB_WPTR_DELAY		0x0718
+#define CP_IB_BASE			0x0738
+#define CP_IB_BUFSZ			0x073C
+#define SCRATCH_REG0			0x15E0
+#define GUI_SCRATCH_REG0		0x15E0
+#define SCRATCH_REG1			0x15E4
+#define GUI_SCRATCH_REG1		0x15E4
+#define SCRATCH_REG2			0x15E8
+#define GUI_SCRATCH_REG2		0x15E8
+#define SCRATCH_REG3			0x15EC
+#define GUI_SCRATCH_REG3		0x15EC
+#define SCRATCH_REG4			0x15F0
+#define GUI_SCRATCH_REG4		0x15F0
+#define SCRATCH_REG5			0x15F4
+#define GUI_SCRATCH_REG5		0x15F4
+#define SCRATCH_UMSK			0x0770
+#define SCRATCH_ADDR			0x0774
+#define DP_BRUSH_FRGD_CLR		0x147C
+#define DP_BRUSH_BKGD_CLR		0x1478
+#define DST_LINE_START			0x1600
+#define DST_LINE_END			0x1604
+#define SRC_OFFSET			0x15AC
+#define SRC_PITCH			0x15B0
+#define SRC_TILE			0x1704
+#define SRC_PITCH_OFFSET		0x1428
+#define SRC_X				0x1414
+#define SRC_Y				0x1418
+#define SRC_X_Y				0x1590
+#define SRC_Y_X				0x1434
+#define DST_Y_X				0x1438
+#define DST_WIDTH_HEIGHT		0x1598
+#define DST_HEIGHT_WIDTH		0x143c
+#define DST_OFFSET			0x1404
+#define SRC_CLUT_ADDRESS		0x1780
+#define SRC_CLUT_DATA			0x1784
+#define SRC_CLUT_DATA_RD		0x1788
+#define HOST_DATA0			0x17C0
+#define HOST_DATA1			0x17C4
+#define HOST_DATA2			0x17C8
+#define HOST_DATA3			0x17CC
+#define HOST_DATA4			0x17D0
+#define HOST_DATA5			0x17D4
+#define HOST_DATA6			0x17D8
+#define HOST_DATA7			0x17DC
+#define HOST_DATA_LAST			0x17E0
+#define DP_SRC_ENDIAN			0x15D4
+#define DP_SRC_FRGD_CLR			0x15D8
+#define DP_SRC_BKGD_CLR			0x15DC
+#define SC_LEFT				0x1640
+#define SC_RIGHT			0x1644
+#define SC_TOP				0x1648
+#define SC_BOTTOM			0x164C
+#define SRC_SC_RIGHT			0x1654
+#define SRC_SC_BOTTOM			0x165C
+#define DP_CNTL				0x16C0
+#define DP_CNTL_XDIR_YDIR_YMAJOR	0x16D0
+#define DP_DATATYPE			0x16C4
+#define DP_MIX				0x16C8
+#define DP_WRITE_MSK			0x16CC
+#define DP_XOP				0x17F8
+#define CLR_CMP_CLR_SRC			0x15C4
+#define CLR_CMP_CLR_DST			0x15C8
+#define CLR_CMP_CNTL			0x15C0
+#define CLR_CMP_MSK			0x15CC
+#define DSTCACHE_MODE			0x1710
+#define DSTCACHE_CTLSTAT		0x1714
+#define DEFAULT_PITCH_OFFSET		0x16E0
+#define DEFAULT_SC_BOTTOM_RIGHT		0x16E8
+#define DEFAULT_SC_TOP_LEFT		0x16EC
+#define SRC_PITCH_OFFSET		0x1428
+#define DST_PITCH_OFFSET		0x142C
+#define DP_GUI_MASTER_CNTL		0x146C
+#define SC_TOP_LEFT			0x16EC
+#define SC_BOTTOM_RIGHT			0x16F0
+#define SRC_SC_BOTTOM_RIGHT		0x16F4
+#define RB2D_DSTCACHE_MODE		0x3428
+#define RB2D_DSTCACHE_CTLSTAT		0x342C
+#define LVDS_GEN_CNTL			0x02d0
+#define LVDS_PLL_CNTL			0x02d4
+#define FP2_GEN_CNTL			0x0288
+#define TMDS_CNTL			0x0294
+#define TMDS_CRC			0x02a0
+#define TMDS_TRANSMITTER_CNTL		0x02a4
+#define MPP_TB_CONFIG			0x01c0
+#define PAMAC0_DLY_CNTL			0x0a94
+#define PAMAC1_DLY_CNTL			0x0a98
+#define PAMAC2_DLY_CNTL			0x0a9c
+#define FW_CNTL				0x0118
+#define FCP_CNTL			0x0910
+#define VGA_DDA_ON_OFF			0x02ec
+#define TV_MASTER_CNTL			0x0800
+
+/* #define BASE_CODE			0x0f0b */
+#define BIOS_0_SCRATCH			0x0010
+#define BIOS_1_SCRATCH			0x0014
+#define BIOS_2_SCRATCH			0x0018
+#define BIOS_3_SCRATCH			0x001c
+#define BIOS_4_SCRATCH			0x0020
+#define BIOS_5_SCRATCH			0x0024
+#define BIOS_6_SCRATCH			0x0028
+#define BIOS_7_SCRATCH			0x002c
+
+#define HDP_SOFT_RESET			(1 << 26)
+
+#define TV_DAC_CNTL			0x088c
+#define GPIOPAD_MASK			0x0198
+#define GPIOPAD_A			0x019c
+#define GPIOPAD_EN			0x01a0
+#define GPIOPAD_Y			0x01a4
+#define ZV_LCDPAD_MASK			0x01a8
+#define ZV_LCDPAD_A			0x01ac
+#define ZV_LCDPAD_EN			0x01b0
+#define ZV_LCDPAD_Y			0x01b4
+
+/* PLL Registers */
+#define CLK_PIN_CNTL			0x0001
+#define PPLL_CNTL			0x0002
+#define PPLL_REF_DIV			0x0003
+#define PPLL_DIV_0			0x0004
+#define PPLL_DIV_1			0x0005
+#define PPLL_DIV_2			0x0006
+#define PPLL_DIV_3			0x0007
+#define VCLK_ECP_CNTL			0x0008
+#define HTOTAL_CNTL			0x0009
+#define M_SPLL_REF_FB_DIV		0x000a
+#define AGP_PLL_CNTL			0x000b
+#define SPLL_CNTL			0x000c
+#define SCLK_CNTL			0x000d
+#define MPLL_CNTL			0x000e
+#define MDLL_CKO			0x000f
+#define MDLL_RDCKA			0x0010
+#define MCLK_CNTL			0x0012
+#define AGP_PLL_CNTL			0x000b
+#define PLL_TEST_CNTL			0x0013
+#define CLK_PWRMGT_CNTL			0x0014
+#define PLL_PWRMGT_CNTL			0x0015
+#define MCLK_MISC			0x001f
+#define P2PLL_CNTL			0x002a
+#define P2PLL_REF_DIV			0x002b
+#define PIXCLKS_CNTL			0x002d
+#define SCLK_MORE_CNTL			0x0035
+
+/* MCLK_CNTL bit constants */
+#define FORCEON_MCLKA			(1 << 16)
+#define FORCEON_MCLKB			(1 << 17)
+#define FORCEON_YCLKA			(1 << 18)
+#define FORCEON_YCLKB			(1 << 19)
+#define FORCEON_MC			(1 << 20)
+#define FORCEON_AIC			(1 << 21)
+
+/* SCLK_CNTL bit constants */
+#define DYN_STOP_LAT_MASK		0x00007ff8
+#define CP_MAX_DYN_STOP_LAT		0x0008
+#define SCLK_FORCEON_MASK		0xffff8000
+
+/* SCLK_MORE_CNTL bit constants */
+#define SCLK_MORE_FORCEON		0x0700
+
+/* BUS_CNTL bit constants */
+#define BUS_DBL_RESYNC			0x00000001
+#define BUS_MSTR_RESET			0x00000002
+#define BUS_FLUSH_BUF			0x00000004
+#define BUS_STOP_REQ_DIS		0x00000008
+#define BUS_ROTATION_DIS		0x00000010
+#define BUS_MASTER_DIS			0x00000040
+#define BUS_ROM_WRT_EN			0x00000080
+#define BUS_DIS_ROM			0x00001000
+#define BUS_PCI_READ_RETRY_EN		0x00002000
+#define BUS_AGP_AD_STEPPING_EN		0x00004000
+#define BUS_PCI_WRT_RETRY_EN		0x00008000
+#define BUS_MSTR_RD_MULT		0x00100000
+#define BUS_MSTR_RD_LINE		0x00200000
+#define BUS_SUSPEND			0x00400000
+#define LAT_16X				0x00800000
+#define BUS_RD_DISCARD_EN		0x01000000
+#define BUS_RD_ABORT_EN			0x02000000
+#define BUS_MSTR_WS			0x04000000
+#define BUS_PARKING_DIS			0x08000000
+#define BUS_MSTR_DISCONNECT_EN		0x10000000
+#define BUS_WRT_BURST			0x20000000
+#define BUS_READ_BURST			0x40000000
+#define BUS_RDY_READ_DLY		0x80000000
+
+/* PIXCLKS_CNTL */
+#define PIX2CLK_SRC_SEL_MASK		0x03
+#define PIX2CLK_SRC_SEL_CPUCLK		0x00
+#define PIX2CLK_SRC_SEL_PSCANCLK	0x01
+#define PIX2CLK_SRC_SEL_BYTECLK		0x02
+#define PIX2CLK_SRC_SEL_P2PLLCLK	0x03
+#define PIX2CLK_ALWAYS_ONb		(1<<6)
+#define PIX2CLK_DAC_ALWAYS_ONb		(1<<7)
+#define PIXCLK_TV_SRC_SEL		(1 << 8)
+#define PIXCLK_LVDS_ALWAYS_ONb		(1 << 14)
+#define PIXCLK_TMDS_ALWAYS_ONb		(1 << 15)
+
+
+/* CLOCK_CNTL_INDEX bit constants */
+#define PLL_WR_EN			0x00000080
+
+/* CONFIG_CNTL bit constants */
+#define CONFIG_SYS_VGA_RAM_EN			0x00000100
+#define CONFIG_SYS_ATI_REV_ID_MASK		(0xf << 16)
+#define CONFIG_SYS_ATI_REV_A11			(0 << 16)
+#define CONFIG_SYS_ATI_REV_A12			(1 << 16)
+#define CONFIG_SYS_ATI_REV_A13			(2 << 16)
+
+/* CRTC_EXT_CNTL bit constants */
+#define VGA_ATI_LINEAR			0x00000008
+#define VGA_128KAP_PAGING		0x00000010
+#define XCRT_CNT_EN			(1 << 6)
+#define CRTC_HSYNC_DIS			(1 << 8)
+#define CRTC_VSYNC_DIS			(1 << 9)
+#define CRTC_DISPLAY_DIS		(1 << 10)
+#define CRTC_CRT_ON			(1 << 15)
+
+
+/* DSTCACHE_CTLSTAT bit constants */
+#define RB2D_DC_FLUSH			(3 << 0)
+#define RB2D_DC_FLUSH_ALL		0xf
+#define RB2D_DC_BUSY			(1 << 31)
+
+
+/* CRTC_GEN_CNTL bit constants */
+#define CRTC_DBL_SCAN_EN		0x00000001
+#define CRTC_CUR_EN			0x00010000
+#define CRTC_INTERLACE_EN		(1 << 1)
+#define CRTC_BYPASS_LUT_EN		(1 << 14)
+#define CRTC_EXT_DISP_EN		(1 << 24)
+#define CRTC_EN				(1 << 25)
+#define CRTC_DISP_REQ_EN_B		(1 << 26)
+
+/* CRTC_STATUS bit constants */
+#define CRTC_VBLANK			0x00000001
+
+/* CRTC2_GEN_CNTL bit constants */
+#define CRT2_ON				(1 << 7)
+#define CRTC2_DISPLAY_DIS		(1 << 23)
+#define CRTC2_EN			(1 << 25)
+#define CRTC2_DISP_REQ_EN_B		(1 << 26)
+
+/* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */
+#define CUR_LOCK			0x80000000
+
+/* GPIO bit constants */
+#define GPIO_A_0			(1 <<  0)
+#define GPIO_A_1			(1 <<  1)
+#define GPIO_Y_0			(1 <<  8)
+#define GPIO_Y_1			(1 <<  9)
+#define GPIO_EN_0			(1 << 16)
+#define GPIO_EN_1			(1 << 17)
+#define GPIO_MASK_0			(1 << 24)
+#define GPIO_MASK_1			(1 << 25)
+#define VGA_DDC_DATA_OUTPUT		GPIO_A_0
+#define VGA_DDC_CLK_OUTPUT		GPIO_A_1
+#define VGA_DDC_DATA_INPUT		GPIO_Y_0
+#define VGA_DDC_CLK_INPUT		GPIO_Y_1
+#define VGA_DDC_DATA_OUT_EN		GPIO_EN_0
+#define VGA_DDC_CLK_OUT_EN		GPIO_EN_1
+
+
+/* FP bit constants */
+#define FP_CRTC_H_TOTAL_MASK		000003ff
+#define FP_CRTC_H_DISP_MASK		0x01ff0000
+#define FP_CRTC_V_TOTAL_MASK		0x00000fff
+#define FP_CRTC_V_DISP_MASK		0x0fff0000
+#define FP_H_SYNC_STRT_CHAR_MASK	0x00001ff8
+#define FP_H_SYNC_WID_MASK		0x003f0000
+#define FP_V_SYNC_STRT_MASK		0x00000fff
+#define FP_V_SYNC_WID_MASK		0x001f0000
+#define FP_CRTC_H_TOTAL_SHIFT		0x00000000
+#define FP_CRTC_H_DISP_SHIFT		0x00000010
+#define FP_CRTC_V_TOTAL_SHIFT		0x00000000
+#define FP_CRTC_V_DISP_SHIFT		0x00000010
+#define FP_H_SYNC_STRT_CHAR_SHIFT	0x00000003
+#define FP_H_SYNC_WID_SHIFT		0x00000010
+#define FP_V_SYNC_STRT_SHIFT		0x00000000
+#define FP_V_SYNC_WID_SHIFT		0x00000010
+
+/* FP_GEN_CNTL bit constants */
+#define FP_FPON				(1 << 0)
+#define FP_TMDS_EN			(1 << 2)
+#define FP_PANEL_FORMAT			(1 << 3)
+#define FP_EN_TMDS			(1 << 7)
+#define FP_DETECT_SENSE			(1 << 8)
+#define R200_FP_SOURCE_SEL_MASK		(3 << 10)
+#define R200_FP_SOURCE_SEL_CRTC1	(0 << 10)
+#define R200_FP_SOURCE_SEL_CRTC2	(1 << 10)
+#define R200_FP_SOURCE_SEL_RMX		(2 << 10)
+#define R200_FP_SOURCE_SEL_TRANS	(3 << 10)
+#define FP_SEL_CRTC1			(0 << 13)
+#define FP_SEL_CRTC2			(1 << 13)
+#define FP_USE_VGA_HSYNC		(1 << 14)
+#define FP_CRTC_DONT_SHADOW_HPAR	(1 << 15)
+#define FP_CRTC_DONT_SHADOW_VPAR	(1 << 16)
+#define FP_CRTC_DONT_SHADOW_HEND	(1 << 17)
+#define FP_CRTC_USE_SHADOW_VEND		(1 << 18)
+#define FP_RMX_HVSYNC_CONTROL_EN	(1 << 20)
+#define FP_DFP_SYNC_SEL			(1 << 21)
+#define FP_CRTC_LOCK_8DOT		(1 << 22)
+#define FP_CRT_SYNC_SEL			(1 << 23)
+#define FP_USE_SHADOW_EN		(1 << 24)
+#define FP_CRT_SYNC_ALT			(1 << 26)
+
+/* FP2_GEN_CNTL bit constants */
+#define FP2_BLANK_EN			(1 <<	1)
+#define FP2_ON				(1 <<	2)
+#define FP2_PANEL_FORMAT		(1 <<	3)
+#define FP2_SOURCE_SEL_MASK		(3 << 10)
+#define FP2_SOURCE_SEL_CRTC2		(1 << 10)
+#define FP2_SRC_SEL_MASK		(3 << 13)
+#define FP2_SRC_SEL_CRTC2		(1 << 13)
+#define FP2_FP_POL			(1 << 16)
+#define FP2_LP_POL			(1 << 17)
+#define FP2_SCK_POL			(1 << 18)
+#define FP2_LCD_CNTL_MASK		(7 << 19)
+#define FP2_PAD_FLOP_EN			(1 << 22)
+#define FP2_CRC_EN			(1 << 23)
+#define FP2_CRC_READ_EN			(1 << 24)
+#define FP2_DV0_EN			(1 << 25)
+#define FP2_DV0_RATE_SEL_SDR		(1 << 26)
+
+
+/* LVDS_GEN_CNTL bit constants */
+#define LVDS_ON				(1 << 0)
+#define LVDS_DISPLAY_DIS		(1 << 1)
+#define LVDS_PANEL_TYPE			(1 << 2)
+#define LVDS_PANEL_FORMAT		(1 << 3)
+#define LVDS_EN				(1 << 7)
+#define LVDS_BL_MOD_LEVEL_MASK		0x0000ff00
+#define LVDS_BL_MOD_LEVEL_SHIFT		8
+#define LVDS_BL_MOD_EN			(1 << 16)
+#define LVDS_DIGON			(1 << 18)
+#define LVDS_BLON			(1 << 19)
+#define LVDS_SEL_CRTC2			(1 << 23)
+#define LVDS_STATE_MASK \
+	(LVDS_ON | LVDS_DISPLAY_DIS | LVDS_BL_MOD_LEVEL_MASK | LVDS_BLON)
+
+/* LVDS_PLL_CNTL bit constatns */
+#define HSYNC_DELAY_SHIFT		0x1c
+#define HSYNC_DELAY_MASK		(0xf << 0x1c)
+
+/* TMDS_TRANSMITTER_CNTL bit constants */
+#define TMDS_PLL_EN			(1 << 0)
+#define TMDS_PLLRST			(1 << 1)
+#define TMDS_RAN_PAT_RST		(1 << 7)
+#define TMDS_ICHCSEL			(1 << 28)
+
+/* FP_HORZ_STRETCH bit constants */
+#define HORZ_STRETCH_RATIO_MASK		0xffff
+#define HORZ_STRETCH_RATIO_MAX		4096
+#define HORZ_PANEL_SIZE			(0x1ff << 16)
+#define HORZ_PANEL_SHIFT		16
+#define HORZ_STRETCH_PIXREP		(0 << 25)
+#define HORZ_STRETCH_BLEND		(1 << 26)
+#define HORZ_STRETCH_ENABLE		(1 << 25)
+#define HORZ_AUTO_RATIO			(1 << 27)
+#define HORZ_FP_LOOP_STRETCH		(0x7 << 28)
+#define HORZ_AUTO_RATIO_INC		(1 << 31)
+
+
+/* FP_VERT_STRETCH bit constants */
+#define VERT_STRETCH_RATIO_MASK		0xfff
+#define VERT_STRETCH_RATIO_MAX		4096
+#define VERT_PANEL_SIZE			(0xfff << 12)
+#define VERT_PANEL_SHIFT		12
+#define VERT_STRETCH_LINREP		(0 << 26)
+#define VERT_STRETCH_BLEND		(1 << 26)
+#define VERT_STRETCH_ENABLE		(1 << 25)
+#define VERT_AUTO_RATIO_EN		(1 << 27)
+#define VERT_FP_LOOP_STRETCH		(0x7 << 28)
+#define VERT_STRETCH_RESERVED		0xf1000000
+
+/* DAC_CNTL bit constants */
+#define DAC_8BIT_EN			0x00000100
+#define DAC_4BPP_PIX_ORDER		0x00000200
+#define DAC_CRC_EN			0x00080000
+#define DAC_MASK_ALL			(0xff << 24)
+#define DAC_PDWN			(1 << 15)
+#define DAC_EXPAND_MODE			(1 << 14)
+#define DAC_VGA_ADR_EN			(1 << 13)
+#define DAC_RANGE_CNTL			(3 <<  0)
+#define DAC_RANGE_CNTL_MASK		0x03
+#define DAC_BLANKING			(1 <<  2)
+#define DAC_CMP_EN			(1 <<  3)
+#define DAC_CMP_OUTPUT			(1 <<  7)
+
+/* DAC_CNTL2 bit constants */
+#define DAC2_EXPAND_MODE		(1 << 14)
+#define DAC2_CMP_EN			(1 << 7)
+#define DAC2_PALETTE_ACCESS_CNTL	(1 << 5)
+
+/* DAC_EXT_CNTL bit constants */
+#define DAC_FORCE_BLANK_OFF_EN		(1 << 4)
+#define DAC_FORCE_DATA_EN		(1 << 5)
+#define DAC_FORCE_DATA_SEL_MASK		(3 << 6)
+#define DAC_FORCE_DATA_MASK		0x0003ff00
+#define DAC_FORCE_DATA_SHIFT		8
+
+/* GEN_RESET_CNTL bit constants */
+#define SOFT_RESET_GUI			0x00000001
+#define SOFT_RESET_VCLK			0x00000100
+#define SOFT_RESET_PCLK			0x00000200
+#define SOFT_RESET_ECP			0x00000400
+#define SOFT_RESET_DISPENG_XCLK		0x00000800
+
+/* MEM_CNTL bit constants */
+#define MEM_CTLR_STATUS_IDLE		0x00000000
+#define MEM_CTLR_STATUS_BUSY		0x00100000
+#define MEM_SEQNCR_STATUS_IDLE		0x00000000
+#define MEM_SEQNCR_STATUS_BUSY		0x00200000
+#define MEM_ARBITER_STATUS_IDLE		0x00000000
+#define MEM_ARBITER_STATUS_BUSY		0x00400000
+#define MEM_REQ_UNLOCK			0x00000000
+#define MEM_REQ_LOCK			0x00800000
+#define MEM_NUM_CHANNELS_MASK		0x00000001
+#define MEM_USE_B_CH_ONLY		0x00000002
+#define RV100_MEM_HALF_MODE		0x00000008
+#define R300_MEM_NUM_CHANNELS_MASK	0x00000003
+#define R300_MEM_USE_CD_CH_ONLY		0x00000004
+
+
+/* RBBM_SOFT_RESET bit constants */
+#define SOFT_RESET_CP			(1 <<  0)
+#define SOFT_RESET_HI			(1 <<  1)
+#define SOFT_RESET_SE			(1 <<  2)
+#define SOFT_RESET_RE			(1 <<  3)
+#define SOFT_RESET_PP			(1 <<  4)
+#define SOFT_RESET_E2			(1 <<  5)
+#define SOFT_RESET_RB			(1 <<  6)
+#define SOFT_RESET_HDP			(1 <<  7)
+
+/* SURFACE_CNTL bit consants */
+#define SURF_TRANSLATION_DIS		(1 << 8)
+#define NONSURF_AP0_SWP_16BPP		(1 << 20)
+#define NONSURF_AP0_SWP_32BPP		(1 << 21)
+#define NONSURF_AP1_SWP_16BPP		(1 << 22)
+#define NONSURF_AP1_SWP_32BPP		(1 << 23)
+
+#define R200_SURF_TILE_COLOR_MACRO	(1 << 16)
+
+/* DEFAULT_SC_BOTTOM_RIGHT bit constants */
+#define DEFAULT_SC_RIGHT_MAX		(0x1fff << 0)
+#define DEFAULT_SC_BOTTOM_MAX		(0x1fff << 16)
+
+/* MM_INDEX bit constants */
+#define MM_APER				0x80000000
+
+/* CLR_CMP_CNTL bit constants */
+#define COMPARE_SRC_FALSE		0x00000000
+#define COMPARE_SRC_TRUE		0x00000001
+#define COMPARE_SRC_NOT_EQUAL		0x00000004
+#define COMPARE_SRC_EQUAL		0x00000005
+#define COMPARE_SRC_EQUAL_FLIP		0x00000007
+#define COMPARE_DST_FALSE		0x00000000
+#define COMPARE_DST_TRUE		0x00000100
+#define COMPARE_DST_NOT_EQUAL		0x00000400
+#define COMPARE_DST_EQUAL		0x00000500
+#define COMPARE_DESTINATION		0x00000000
+#define COMPARE_SOURCE			0x01000000
+#define COMPARE_SRC_AND_DST		0x02000000
+
+
+/* DP_CNTL bit constants */
+#define DST_X_RIGHT_TO_LEFT		0x00000000
+#define DST_X_LEFT_TO_RIGHT		0x00000001
+#define DST_Y_BOTTOM_TO_TOP		0x00000000
+#define DST_Y_TOP_TO_BOTTOM		0x00000002
+#define DST_X_MAJOR			0x00000000
+#define DST_Y_MAJOR			0x00000004
+#define DST_X_TILE			0x00000008
+#define DST_Y_TILE			0x00000010
+#define DST_LAST_PEL			0x00000020
+#define DST_TRAIL_X_RIGHT_TO_LEFT	0x00000000
+#define DST_TRAIL_X_LEFT_TO_RIGHT	0x00000040
+#define DST_TRAP_FILL_RIGHT_TO_LEFT	0x00000000
+#define DST_TRAP_FILL_LEFT_TO_RIGHT	0x00000080
+#define DST_BRES_SIGN			0x00000100
+#define DST_HOST_BIG_ENDIAN_EN		0x00000200
+#define DST_POLYLINE_NONLAST		0x00008000
+#define DST_RASTER_STALL		0x00010000
+#define DST_POLY_EDGE			0x00040000
+
+
+/* DP_CNTL_YDIR_XDIR_YMAJOR bit constants (short version of DP_CNTL) */
+#define DST_X_MAJOR_S			0x00000000
+#define DST_Y_MAJOR_S			0x00000001
+#define DST_Y_BOTTOM_TO_TOP_S		0x00000000
+#define DST_Y_TOP_TO_BOTTOM_S		0x00008000
+#define DST_X_RIGHT_TO_LEFT_S		0x00000000
+#define DST_X_LEFT_TO_RIGHT_S		0x80000000
+
+
+/* DP_DATATYPE bit constants */
+#define DST_8BPP			0x00000002
+#define DST_15BPP			0x00000003
+#define DST_16BPP			0x00000004
+#define DST_24BPP			0x00000005
+#define DST_32BPP			0x00000006
+#define DST_8BPP_RGB332			0x00000007
+#define DST_8BPP_Y8			0x00000008
+#define DST_8BPP_RGB8			0x00000009
+#define DST_16BPP_VYUY422		0x0000000b
+#define DST_16BPP_YVYU422		0x0000000c
+#define DST_32BPP_AYUV444		0x0000000e
+#define DST_16BPP_ARGB4444		0x0000000f
+#define BRUSH_SOLIDCOLOR		0x00000d00
+#define SRC_MONO			0x00000000
+#define SRC_MONO_LBKGD			0x00010000
+#define SRC_DSTCOLOR			0x00030000
+#define BYTE_ORDER_MSB_TO_LSB		0x00000000
+#define BYTE_ORDER_LSB_TO_MSB		0x40000000
+#define DP_CONVERSION_TEMP		0x80000000
+#define HOST_BIG_ENDIAN_EN		(1 << 29)
+
+
+/* DP_GUI_MASTER_CNTL bit constants */
+#define GMC_SRC_PITCH_OFFSET_DEFAULT	0x00000000
+#define GMC_SRC_PITCH_OFFSET_LEAVE	0x00000001
+#define GMC_DST_PITCH_OFFSET_DEFAULT	0x00000000
+#define GMC_DST_PITCH_OFFSET_LEAVE	0x00000002
+#define GMC_SRC_CLIP_DEFAULT		0x00000000
+#define GMC_SRC_CLIP_LEAVE		0x00000004
+#define GMC_DST_CLIP_DEFAULT		0x00000000
+#define GMC_DST_CLIP_LEAVE		0x00000008
+#define GMC_BRUSH_8x8MONO		0x00000000
+#define GMC_BRUSH_8x8MONO_LBKGD		0x00000010
+#define GMC_BRUSH_8x1MONO		0x00000020
+#define GMC_BRUSH_8x1MONO_LBKGD		0x00000030
+#define GMC_BRUSH_1x8MONO		0x00000040
+#define GMC_BRUSH_1x8MONO_LBKGD		0x00000050
+#define GMC_BRUSH_32x1MONO		0x00000060
+#define GMC_BRUSH_32x1MONO_LBKGD	0x00000070
+#define GMC_BRUSH_32x32MONO		0x00000080
+#define GMC_BRUSH_32x32MONO_LBKGD	0x00000090
+#define GMC_BRUSH_8x8COLOR		0x000000a0
+#define GMC_BRUSH_8x1COLOR		0x000000b0
+#define GMC_BRUSH_1x8COLOR		0x000000c0
+#define GMC_BRUSH_SOLID_COLOR		0x000000d0
+#define GMC_DST_8BPP			0x00000200
+#define GMC_DST_15BPP			0x00000300
+#define GMC_DST_16BPP			0x00000400
+#define GMC_DST_24BPP			0x00000500
+#define GMC_DST_32BPP			0x00000600
+#define GMC_DST_8BPP_RGB332		0x00000700
+#define GMC_DST_8BPP_Y8			0x00000800
+#define GMC_DST_8BPP_RGB8		0x00000900
+#define GMC_DST_16BPP_VYUY422		0x00000b00
+#define GMC_DST_16BPP_YVYU422		0x00000c00
+#define GMC_DST_32BPP_AYUV444		0x00000e00
+#define GMC_DST_16BPP_ARGB4444		0x00000f00
+#define GMC_SRC_MONO			0x00000000
+#define GMC_SRC_MONO_LBKGD		0x00001000
+#define GMC_SRC_DSTCOLOR		0x00003000
+#define GMC_BYTE_ORDER_MSB_TO_LSB	0x00000000
+#define GMC_BYTE_ORDER_LSB_TO_MSB	0x00004000
+#define GMC_DP_CONVERSION_TEMP_9300	0x00008000
+#define GMC_DP_CONVERSION_TEMP_6500	0x00000000
+#define GMC_DP_SRC_RECT			0x02000000
+#define GMC_DP_SRC_HOST			0x03000000
+#define GMC_DP_SRC_HOST_BYTEALIGN	0x04000000
+#define GMC_3D_FCN_EN_CLR		0x00000000
+#define GMC_3D_FCN_EN_SET		0x08000000
+#define GMC_DST_CLR_CMP_FCN_LEAVE	0x00000000
+#define GMC_DST_CLR_CMP_FCN_CLEAR	0x10000000
+#define GMC_AUX_CLIP_LEAVE		0x00000000
+#define GMC_AUX_CLIP_CLEAR		0x20000000
+#define GMC_WRITE_MASK_LEAVE		0x00000000
+#define GMC_WRITE_MASK_SET		0x40000000
+#define GMC_CLR_CMP_CNTL_DIS		(1 << 28)
+#define GMC_SRC_DATATYPE_COLOR		(3 << 12)
+#define ROP3_S				0x00cc0000
+#define ROP3_SRCCOPY			0x00cc0000
+#define ROP3_P				0x00f00000
+#define ROP3_PATCOPY			0x00f00000
+#define DP_SRC_SOURCE_MASK		(7  << 24)
+#define GMC_BRUSH_NONE			(15 <<  4)
+#define DP_SRC_SOURCE_MEMORY		(2  << 24)
+#define GMC_BRUSH_SOLIDCOLOR		0x000000d0
+
+/* DP_MIX bit constants */
+#define DP_SRC_RECT			0x00000200
+#define DP_SRC_HOST			0x00000300
+#define DP_SRC_HOST_BYTEALIGN		0x00000400
+
+/* MPLL_CNTL bit constants */
+#define MPLL_RESET			0x00000001
+
+/* MDLL_CKO bit constants */
+#define MCKOA_SLEEP			0x00000001
+#define MCKOA_RESET			0x00000002
+#define MCKOA_REF_SKEW_MASK		0x00000700
+#define MCKOA_FB_SKEW_MASK		0x00007000
+
+/* MDLL_RDCKA bit constants */
+#define MRDCKA0_SLEEP			0x00000001
+#define MRDCKA0_RESET			0x00000002
+#define MRDCKA1_SLEEP			0x00010000
+#define MRDCKA1_RESET			0x00020000
+
+/* VCLK_ECP_CNTL constants */
+#define VCLK_SRC_SEL_MASK		0x03
+#define VCLK_SRC_SEL_CPUCLK		0x00
+#define VCLK_SRC_SEL_PSCANCLK		0x01
+#define VCLK_SRC_SEL_BYTECLK		0x02
+#define VCLK_SRC_SEL_PPLLCLK		0x03
+#define PIXCLK_ALWAYS_ONb		0x00000040
+#define PIXCLK_DAC_ALWAYS_ONb		0x00000080
+
+/* BUS_CNTL1 constants */
+#define BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK	0x0c000000
+#define BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT	26
+#define BUS_CNTL1_AGPCLK_VALID			0x80000000
+
+/* PLL_PWRMGT_CNTL constants */
+#define PLL_PWRMGT_CNTL_SPLL_TURNOFF		0x00000002
+#define PLL_PWRMGT_CNTL_PPLL_TURNOFF		0x00000004
+#define PLL_PWRMGT_CNTL_P2PLL_TURNOFF		0x00000008
+#define PLL_PWRMGT_CNTL_TVPLL_TURNOFF		0x00000010
+#define PLL_PWRMGT_CNTL_MOBILE_SU		0x00010000
+#define PLL_PWRMGT_CNTL_SU_SCLK_USE_BCLK	0x00020000
+#define PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK	0x00040000
+
+/* TV_DAC_CNTL constants */
+#define TV_DAC_CNTL_BGSLEEP			0x00000040
+#define TV_DAC_CNTL_DETECT			0x00000010
+#define TV_DAC_CNTL_BGADJ_MASK			0x000f0000
+#define TV_DAC_CNTL_DACADJ_MASK			0x00f00000
+#define TV_DAC_CNTL_BGADJ__SHIFT		16
+#define TV_DAC_CNTL_DACADJ__SHIFT		20
+#define TV_DAC_CNTL_RDACPD			0x01000000
+#define TV_DAC_CNTL_GDACPD			0x02000000
+#define TV_DAC_CNTL_BDACPD			0x04000000
+
+/* DISP_MISC_CNTL constants */
+#define DISP_MISC_CNTL_SOFT_RESET_GRPH_PP	(1 << 0)
+#define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_PP	(1 << 1)
+#define DISP_MISC_CNTL_SOFT_RESET_OV0_PP	(1 << 2)
+#define DISP_MISC_CNTL_SOFT_RESET_GRPH_SCLK	(1 << 4)
+#define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_SCLK	(1 << 5)
+#define DISP_MISC_CNTL_SOFT_RESET_OV0_SCLK	(1 << 6)
+#define DISP_MISC_CNTL_SOFT_RESET_GRPH2_PP	(1 << 12)
+#define DISP_MISC_CNTL_SOFT_RESET_GRPH2_SCLK	(1 << 15)
+#define DISP_MISC_CNTL_SOFT_RESET_LVDS		(1 << 16)
+#define DISP_MISC_CNTL_SOFT_RESET_TMDS		(1 << 17)
+#define DISP_MISC_CNTL_SOFT_RESET_DIG_TMDS	(1 << 18)
+#define DISP_MISC_CNTL_SOFT_RESET_TV		(1 << 19)
+
+/* DISP_PWR_MAN constants */
+#define DISP_PWR_MAN_DISP_PWR_MAN_D3_CRTC_EN	(1 << 0)
+#define DISP_PWR_MAN_DISP2_PWR_MAN_D3_CRTC2_EN	(1 << 4)
+#define DISP_PWR_MAN_DISP_D3_RST		(1 << 16)
+#define DISP_PWR_MAN_DISP_D3_REG_RST		(1 << 17)
+#define DISP_PWR_MAN_DISP_D3_GRPH_RST		(1 << 18)
+#define DISP_PWR_MAN_DISP_D3_SUBPIC_RST		(1 << 19)
+#define DISP_PWR_MAN_DISP_D3_OV0_RST		(1 << 20)
+#define DISP_PWR_MAN_DISP_D1D2_GRPH_RST		(1 << 21)
+#define DISP_PWR_MAN_DISP_D1D2_SUBPIC_RST	(1 << 22)
+#define DISP_PWR_MAN_DISP_D1D2_OV0_RST		(1 << 23)
+#define DISP_PWR_MAN_DIG_TMDS_ENABLE_RST	(1 << 24)
+#define DISP_PWR_MAN_TV_ENABLE_RST		(1 << 25)
+#define DISP_PWR_MAN_AUTO_PWRUP_EN		(1 << 26)
+
+/* masks */
+
+#define CONFIG_MEMSIZE_MASK		0x1f000000
+#define MEM_CFG_TYPE			0x40000000
+#define DST_OFFSET_MASK			0x003fffff
+#define DST_PITCH_MASK			0x3fc00000
+#define DEFAULT_TILE_MASK		0xc0000000
+#define PPLL_DIV_SEL_MASK		0x00000300
+#define PPLL_RESET			0x00000001
+#define PPLL_SLEEP			0x00000002
+#define PPLL_ATOMIC_UPDATE_EN		0x00010000
+#define PPLL_REF_DIV_MASK		0x000003ff
+#define PPLL_FB3_DIV_MASK		0x000007ff
+#define PPLL_POST3_DIV_MASK		0x00070000
+#define PPLL_ATOMIC_UPDATE_R		0x00008000
+#define PPLL_ATOMIC_UPDATE_W		0x00008000
+#define PPLL_VGA_ATOMIC_UPDATE_EN	0x00020000
+#define R300_PPLL_REF_DIV_ACC_MASK	(0x3ff << 18)
+#define R300_PPLL_REF_DIV_ACC_SHIFT	18
+
+#define GUI_ACTIVE			0x80000000
+
+
+#define MC_IND_INDEX			0x01F8
+#define MC_IND_DATA			0x01FC
+
+/* PAD_CTLR_STRENGTH */
+#define PAD_MANUAL_OVERRIDE		0x80000000
+
+/* pllCLK_PIN_CNTL */
+#define CLK_PIN_CNTL__OSC_EN_MASK			0x00000001L
+#define CLK_PIN_CNTL__OSC_EN				0x00000001L
+#define CLK_PIN_CNTL__XTL_LOW_GAIN_MASK			0x00000004L
+#define CLK_PIN_CNTL__XTL_LOW_GAIN			0x00000004L
+#define CLK_PIN_CNTL__DONT_USE_XTALIN_MASK		0x00000010L
+#define CLK_PIN_CNTL__DONT_USE_XTALIN			0x00000010L
+#define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE_MASK		0x00000020L
+#define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE			0x00000020L
+#define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN_MASK		0x00000800L
+#define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN			0x00000800L
+#define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN_MASK	0x00001000L
+#define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN		0x00001000L
+#define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND_MASK	0x00002000L
+#define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND		0x00002000L
+#define CLK_PIN_CNTL__CG_SPARE_MASK			0x00004000L
+#define CLK_PIN_CNTL__CG_SPARE				0x00004000L
+#define CLK_PIN_CNTL__SCLK_DYN_START_CNTL_MASK		0x00008000L
+#define CLK_PIN_CNTL__SCLK_DYN_START_CNTL		0x00008000L
+#define CLK_PIN_CNTL__CP_CLK_RUNNING_MASK		0x00010000L
+#define CLK_PIN_CNTL__CP_CLK_RUNNING			0x00010000L
+#define CLK_PIN_CNTL__CG_SPARE_RD_MASK			0x00060000L
+#define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb_MASK		0x00080000L
+#define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb			0x00080000L
+#define CLK_PIN_CNTL__PWRSEQ_DELAY_MASK			0xff000000L
+
+/* pllCLK_PWRMGT_CNTL */
+#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF__SHIFT		0x00000000
+#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF__SHIFT		0x00000001
+#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF__SHIFT		0x00000002
+#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF__SHIFT	0x00000003
+#define CLK_PWRMGT_CNTL__MCLK_TURNOFF__SHIFT		0x00000004
+#define CLK_PWRMGT_CNTL__SCLK_TURNOFF__SHIFT		0x00000005
+#define CLK_PWRMGT_CNTL__PCLK_TURNOFF__SHIFT		0x00000006
+#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF__SHIFT		0x00000007
+#define CLK_PWRMGT_CNTL__MC_CH_MODE__SHIFT		0x00000008
+#define CLK_PWRMGT_CNTL__TEST_MODE__SHIFT		0x00000009
+#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN__SHIFT		0x0000000a
+#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE__SHIFT	0x0000000c
+#define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT__SHIFT		0x0000000d
+#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT__SHIFT	0x0000000f
+#define CLK_PWRMGT_CNTL__MC_BUSY__SHIFT			0x00000010
+#define CLK_PWRMGT_CNTL__MC_INT_CNTL__SHIFT		0x00000011
+#define CLK_PWRMGT_CNTL__MC_SWITCH__SHIFT		0x00000012
+#define CLK_PWRMGT_CNTL__DLL_READY__SHIFT		0x00000013
+#define CLK_PWRMGT_CNTL__DISP_PM__SHIFT			0x00000014
+#define CLK_PWRMGT_CNTL__DYN_STOP_MODE__SHIFT		0x00000015
+#define CLK_PWRMGT_CNTL__CG_NO1_DEBUG__SHIFT		0x00000018
+#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF__SHIFT	0x0000001e
+#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF__SHIFT		0x0000001f
+
+/* pllP2PLL_CNTL */
+#define P2PLL_CNTL__P2PLL_RESET_MASK			0x00000001L
+#define P2PLL_CNTL__P2PLL_RESET				0x00000001L
+#define P2PLL_CNTL__P2PLL_SLEEP_MASK			0x00000002L
+#define P2PLL_CNTL__P2PLL_SLEEP				0x00000002L
+#define P2PLL_CNTL__P2PLL_TST_EN_MASK			0x00000004L
+#define P2PLL_CNTL__P2PLL_TST_EN			0x00000004L
+#define P2PLL_CNTL__P2PLL_REFCLK_SEL_MASK		0x00000010L
+#define P2PLL_CNTL__P2PLL_REFCLK_SEL			0x00000010L
+#define P2PLL_CNTL__P2PLL_FBCLK_SEL_MASK		0x00000020L
+#define P2PLL_CNTL__P2PLL_FBCLK_SEL			0x00000020L
+#define P2PLL_CNTL__P2PLL_TCPOFF_MASK			0x00000040L
+#define P2PLL_CNTL__P2PLL_TCPOFF			0x00000040L
+#define P2PLL_CNTL__P2PLL_TVCOMAX_MASK			0x00000080L
+#define P2PLL_CNTL__P2PLL_TVCOMAX			0x00000080L
+#define P2PLL_CNTL__P2PLL_PCP_MASK			0x00000700L
+#define P2PLL_CNTL__P2PLL_PVG_MASK			0x00003800L
+#define P2PLL_CNTL__P2PLL_PDC_MASK			0x0000c000L
+#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN_MASK		0x00010000L
+#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN		0x00010000L
+#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC_MASK	0x00040000L
+#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC		0x00040000L
+#define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET_MASK	0x00080000L
+#define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET		0x00080000L
+
+/* pllPIXCLKS_CNTL */
+#define PIXCLKS_CNTL__PIX2CLK_SRC_SEL__SHIFT		0x00000000
+#define PIXCLKS_CNTL__PIX2CLK_INVERT__SHIFT		0x00000004
+#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT__SHIFT		0x00000005
+#define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb__SHIFT		0x00000006
+#define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb__SHIFT	0x00000007
+#define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL__SHIFT		0x00000008
+#define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb__SHIFT	0x0000000b
+#define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb__SHIFT	0x0000000c
+#define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb__SHIFT	0x0000000d
+#define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb__SHIFT	0x0000000e
+#define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb__SHIFT	0x0000000f
+
+
+/* pllPIXCLKS_CNTL */
+#define PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK		0x00000003L
+#define PIXCLKS_CNTL__PIX2CLK_INVERT			0x00000010L
+#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT		0x00000020L
+#define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb		0x00000040L
+#define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb		0x00000080L
+#define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL			0x00000100L
+#define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb		0x00000800L
+#define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb		0x00001000L
+#define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb	0x00002000L
+#define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb		0x00004000L
+#define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb		0x00008000L
+#define PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb	(1 << 9)
+#define PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb		(1 << 10)
+#define PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb	(1 << 13)
+#define PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb	(1 << 16)
+#define PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb	(1 << 17)
+#define PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb		(1 << 18)
+#define PIXCLKS_CNTL__R300_P2G2CLK_DAC_ALWAYS_ONb	(1 << 19)
+#define PIXCLKS_CNTL__R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23)
+
+
+/* pllP2PLL_DIV_0 */
+#define P2PLL_DIV_0__P2PLL_FB_DIV_MASK			0x000007ffL
+#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W_MASK		0x00008000L
+#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W		0x00008000L
+#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R_MASK		0x00008000L
+#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R		0x00008000L
+#define P2PLL_DIV_0__P2PLL_POST_DIV_MASK		0x00070000L
+
+/* pllSCLK_CNTL */
+#define SCLK_CNTL__SCLK_SRC_SEL_MASK			0x00000007L
+#define SCLK_CNTL__CP_MAX_DYN_STOP_LAT			0x00000008L
+#define SCLK_CNTL__HDP_MAX_DYN_STOP_LAT			0x00000010L
+#define SCLK_CNTL__TV_MAX_DYN_STOP_LAT			0x00000020L
+#define SCLK_CNTL__E2_MAX_DYN_STOP_LAT			0x00000040L
+#define SCLK_CNTL__SE_MAX_DYN_STOP_LAT			0x00000080L
+#define SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT		0x00000100L
+#define SCLK_CNTL__VIP_MAX_DYN_STOP_LAT			0x00000200L
+#define SCLK_CNTL__RE_MAX_DYN_STOP_LAT			0x00000400L
+#define SCLK_CNTL__PB_MAX_DYN_STOP_LAT			0x00000800L
+#define SCLK_CNTL__TAM_MAX_DYN_STOP_LAT			0x00001000L
+#define SCLK_CNTL__TDM_MAX_DYN_STOP_LAT			0x00002000L
+#define SCLK_CNTL__RB_MAX_DYN_STOP_LAT			0x00004000L
+#define SCLK_CNTL__DYN_STOP_LAT_MASK			0x00007ff8
+#define SCLK_CNTL__FORCE_DISP2				0x00008000L
+#define SCLK_CNTL__FORCE_CP				0x00010000L
+#define SCLK_CNTL__FORCE_HDP				0x00020000L
+#define SCLK_CNTL__FORCE_DISP1				0x00040000L
+#define SCLK_CNTL__FORCE_TOP				0x00080000L
+#define SCLK_CNTL__FORCE_E2				0x00100000L
+#define SCLK_CNTL__FORCE_SE				0x00200000L
+#define SCLK_CNTL__FORCE_IDCT				0x00400000L
+#define SCLK_CNTL__FORCE_VIP				0x00800000L
+#define SCLK_CNTL__FORCE_RE				0x01000000L
+#define SCLK_CNTL__FORCE_PB				0x02000000L
+#define SCLK_CNTL__FORCE_TAM				0x04000000L
+#define SCLK_CNTL__FORCE_TDM				0x08000000L
+#define SCLK_CNTL__FORCE_RB				0x10000000L
+#define SCLK_CNTL__FORCE_TV_SCLK			0x20000000L
+#define SCLK_CNTL__FORCE_SUBPIC				0x40000000L
+#define SCLK_CNTL__FORCE_OV0				0x80000000L
+#define SCLK_CNTL__R300_FORCE_VAP			(1<<21)
+#define SCLK_CNTL__R300_FORCE_SR			(1<<25)
+#define SCLK_CNTL__R300_FORCE_PX			(1<<26)
+#define SCLK_CNTL__R300_FORCE_TX			(1<<27)
+#define SCLK_CNTL__R300_FORCE_US			(1<<28)
+#define SCLK_CNTL__R300_FORCE_SU			(1<<30)
+#define SCLK_CNTL__FORCEON_MASK				0xffff8000L
+
+/* pllSCLK_CNTL2 */
+#define SCLK_CNTL2__R300_TCL_MAX_DYN_STOP_LAT		(1<<10)
+#define SCLK_CNTL2__R300_GA_MAX_DYN_STOP_LAT		(1<<11)
+#define SCLK_CNTL2__R300_CBA_MAX_DYN_STOP_LAT		(1<<12)
+#define SCLK_CNTL2__R300_FORCE_TCL			(1<<13)
+#define SCLK_CNTL2__R300_FORCE_CBA			(1<<14)
+#define SCLK_CNTL2__R300_FORCE_GA			(1<<15)
+
+/* SCLK_MORE_CNTL */
+#define SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT	0x00000001L
+#define SCLK_MORE_CNTL__MC_GUI_MAX_DYN_STOP_LAT		0x00000002L
+#define SCLK_MORE_CNTL__MC_HOST_MAX_DYN_STOP_LAT	0x00000004L
+#define SCLK_MORE_CNTL__FORCE_DISPREGS			0x00000100L
+#define SCLK_MORE_CNTL__FORCE_MC_GUI			0x00000200L
+#define SCLK_MORE_CNTL__FORCE_MC_HOST			0x00000400L
+#define SCLK_MORE_CNTL__STOP_SCLK_EN			0x00001000L
+#define SCLK_MORE_CNTL__STOP_SCLK_A			0x00002000L
+#define SCLK_MORE_CNTL__STOP_SCLK_B			0x00004000L
+#define SCLK_MORE_CNTL__STOP_SCLK_C			0x00008000L
+#define SCLK_MORE_CNTL__HALF_SPEED_SCLK			0x00010000L
+#define SCLK_MORE_CNTL__IO_CG_VOLTAGE_DROP		0x00020000L
+#define SCLK_MORE_CNTL__TVFB_SOFT_RESET			0x00040000L
+#define SCLK_MORE_CNTL__VOLTAGE_DROP_SYNC		0x00080000L
+#define SCLK_MORE_CNTL__IDLE_DELAY_HALF_SCLK		0x00400000L
+#define SCLK_MORE_CNTL__AGP_BUSY_HALF_SCLK		0x00800000L
+#define SCLK_MORE_CNTL__CG_SPARE_RD_C_MASK		0xff000000L
+#define SCLK_MORE_CNTL__FORCEON				0x00000700L
+
+/* MCLK_CNTL */
+#define MCLK_CNTL__MCLKA_SRC_SEL_MASK			0x00000007L
+#define MCLK_CNTL__YCLKA_SRC_SEL_MASK			0x00000070L
+#define MCLK_CNTL__MCLKB_SRC_SEL_MASK			0x00000700L
+#define MCLK_CNTL__YCLKB_SRC_SEL_MASK			0x00007000L
+#define MCLK_CNTL__FORCE_MCLKA_MASK			0x00010000L
+#define MCLK_CNTL__FORCE_MCLKA				0x00010000L
+#define MCLK_CNTL__FORCE_MCLKB_MASK			0x00020000L
+#define MCLK_CNTL__FORCE_MCLKB				0x00020000L
+#define MCLK_CNTL__FORCE_YCLKA_MASK			0x00040000L
+#define MCLK_CNTL__FORCE_YCLKA				0x00040000L
+#define MCLK_CNTL__FORCE_YCLKB_MASK			0x00080000L
+#define MCLK_CNTL__FORCE_YCLKB				0x00080000L
+#define MCLK_CNTL__FORCE_MC_MASK			0x00100000L
+#define MCLK_CNTL__FORCE_MC				0x00100000L
+#define MCLK_CNTL__FORCE_AIC_MASK			0x00200000L
+#define MCLK_CNTL__FORCE_AIC				0x00200000L
+#define MCLK_CNTL__MRDCKA0_SOUTSEL_MASK			0x03000000L
+#define MCLK_CNTL__MRDCKA1_SOUTSEL_MASK			0x0c000000L
+#define MCLK_CNTL__MRDCKB0_SOUTSEL_MASK			0x30000000L
+#define MCLK_CNTL__MRDCKB1_SOUTSEL_MASK			0xc0000000L
+#define MCLK_CNTL__R300_DISABLE_MC_MCLKA		(1 << 21)
+#define MCLK_CNTL__R300_DISABLE_MC_MCLKB		(1 << 21)
+
+/* MCLK_MISC */
+#define MCLK_MISC__SCLK_SOURCED_FROM_MPLL_SEL_MASK	0x00000003L
+#define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL_MASK		0x00000004L
+#define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL		0x00000004L
+#define MCLK_MISC__ENABLE_SCLK_FROM_MPLL_MASK		0x00000008L
+#define MCLK_MISC__ENABLE_SCLK_FROM_MPLL		0x00000008L
+#define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN_MASK	0x00000010L
+#define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN		0x00000010L
+#define MCLK_MISC__DLL_READY_LAT_MASK			0x00000100L
+#define MCLK_MISC__DLL_READY_LAT			0x00000100L
+#define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT_MASK	0x00001000L
+#define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT		0x00001000L
+#define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT_MASK	0x00002000L
+#define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT		0x00002000L
+#define MCLK_MISC__MC_MCLK_DYN_ENABLE_MASK		0x00004000L
+#define MCLK_MISC__MC_MCLK_DYN_ENABLE			0x00004000L
+#define MCLK_MISC__IO_MCLK_DYN_ENABLE_MASK		0x00008000L
+#define MCLK_MISC__IO_MCLK_DYN_ENABLE			0x00008000L
+#define MCLK_MISC__CGM_CLK_TO_OUTPIN_MASK		0x00010000L
+#define MCLK_MISC__CGM_CLK_TO_OUTPIN			0x00010000L
+#define MCLK_MISC__CLK_OR_COUNT_SEL_MASK		0x00020000L
+#define MCLK_MISC__CLK_OR_COUNT_SEL			0x00020000L
+#define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND_MASK	0x00040000L
+#define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND		0x00040000L
+#define MCLK_MISC__CGM_SPARE_RD_MASK			0x00300000L
+#define MCLK_MISC__CGM_SPARE_A_RD_MASK			0x00c00000L
+#define MCLK_MISC__TCLK_TO_YCLKB_EN_MASK		0x01000000L
+#define MCLK_MISC__TCLK_TO_YCLKB_EN			0x01000000L
+#define MCLK_MISC__CGM_SPARE_A_MASK			0x0e000000L
+
+/* VCLK_ECP_CNTL */
+#define VCLK_ECP_CNTL__VCLK_SRC_SEL_MASK		0x00000003L
+#define VCLK_ECP_CNTL__VCLK_INVERT			0x00000010L
+#define VCLK_ECP_CNTL__PIXCLK_SRC_INVERT		0x00000020L
+#define VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb		0x00000040L
+#define VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb		0x00000080L
+#define VCLK_ECP_CNTL__ECP_DIV_MASK			0x00000300L
+#define VCLK_ECP_CNTL__ECP_FORCE_ON			0x00040000L
+#define VCLK_ECP_CNTL__SUBCLK_FORCE_ON			0x00080000L
+#define VCLK_ECP_CNTL__R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF  (1<<23)
+
+/* PLL_PWRMGT_CNTL */
+#define PLL_PWRMGT_CNTL__MPLL_TURNOFF_MASK		0x00000001L
+#define PLL_PWRMGT_CNTL__MPLL_TURNOFF			0x00000001L
+#define PLL_PWRMGT_CNTL__SPLL_TURNOFF_MASK		0x00000002L
+#define PLL_PWRMGT_CNTL__SPLL_TURNOFF			0x00000002L
+#define PLL_PWRMGT_CNTL__PPLL_TURNOFF_MASK		0x00000004L
+#define PLL_PWRMGT_CNTL__PPLL_TURNOFF			0x00000004L
+#define PLL_PWRMGT_CNTL__P2PLL_TURNOFF_MASK		0x00000008L
+#define PLL_PWRMGT_CNTL__P2PLL_TURNOFF			0x00000008L
+#define PLL_PWRMGT_CNTL__TVPLL_TURNOFF_MASK		0x00000010L
+#define PLL_PWRMGT_CNTL__TVPLL_TURNOFF			0x00000010L
+#define PLL_PWRMGT_CNTL__AGPCLK_DYN_STOP_LAT_MASK	0x000001e0L
+#define PLL_PWRMGT_CNTL__APM_POWER_STATE_MASK		0x00000600L
+#define PLL_PWRMGT_CNTL__APM_PWRSTATE_RD_MASK		0x00001800L
+#define PLL_PWRMGT_CNTL__PM_MODE_SEL_MASK		0x00002000L
+#define PLL_PWRMGT_CNTL__PM_MODE_SEL			0x00002000L
+#define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND_MASK	0x00004000L
+#define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND		0x00004000L
+#define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND_MASK	0x00008000L
+#define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND		0x00008000L
+#define PLL_PWRMGT_CNTL__MOBILE_SU_MASK			0x00010000L
+#define PLL_PWRMGT_CNTL__MOBILE_SU			0x00010000L
+#define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK_MASK		0x00020000L
+#define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK		0x00020000L
+#define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK_MASK		0x00040000L
+#define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK		0x00040000L
+#define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE_MASK	0x00080000L
+#define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE		0x00080000L
+#define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE_MASK	0x00100000L
+#define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE		0x00100000L
+#define PLL_PWRMGT_CNTL__TCL_CLOCK_CTIVE_RD_MASK	0x00200000L
+#define PLL_PWRMGT_CNTL__TCL_CLOCK_ACTIVE_RD		0x00200000L
+#define PLL_PWRMGT_CNTL__CG_NO2_DEBUG_MASK		0xff000000L
+
+/* CLK_PWRMGT_CNTL */
+#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF_MASK		0x00000001L
+#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF		0x00000001L
+#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF_MASK		0x00000002L
+#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF		0x00000002L
+#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF_MASK		0x00000004L
+#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF		0x00000004L
+#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF_MASK		0x00000008L
+#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF		0x00000008L
+#define CLK_PWRMGT_CNTL__MCLK_TURNOFF_MASK		0x00000010L
+#define CLK_PWRMGT_CNTL__MCLK_TURNOFF			0x00000010L
+#define CLK_PWRMGT_CNTL__SCLK_TURNOFF_MASK		0x00000020L
+#define CLK_PWRMGT_CNTL__SCLK_TURNOFF			0x00000020L
+#define CLK_PWRMGT_CNTL__PCLK_TURNOFF_MASK		0x00000040L
+#define CLK_PWRMGT_CNTL__PCLK_TURNOFF			0x00000040L
+#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF_MASK		0x00000080L
+#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF			0x00000080L
+#define CLK_PWRMGT_CNTL__MC_CH_MODE_MASK		0x00000100L
+#define CLK_PWRMGT_CNTL__MC_CH_MODE			0x00000100L
+#define CLK_PWRMGT_CNTL__TEST_MODE_MASK			0x00000200L
+#define CLK_PWRMGT_CNTL__TEST_MODE			0x00000200L
+#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN_MASK		0x00000400L
+#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN			0x00000400L
+#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE_MASK	0x00001000L
+#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE		0x00001000L
+#define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK		0x00006000L
+#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT_MASK		0x00008000L
+#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT		0x00008000L
+#define CLK_PWRMGT_CNTL__MC_BUSY_MASK			0x00010000L
+#define CLK_PWRMGT_CNTL__MC_BUSY			0x00010000L
+#define CLK_PWRMGT_CNTL__MC_INT_CNTL_MASK		0x00020000L
+#define CLK_PWRMGT_CNTL__MC_INT_CNTL			0x00020000L
+#define CLK_PWRMGT_CNTL__MC_SWITCH_MASK			0x00040000L
+#define CLK_PWRMGT_CNTL__MC_SWITCH			0x00040000L
+#define CLK_PWRMGT_CNTL__DLL_READY_MASK			0x00080000L
+#define CLK_PWRMGT_CNTL__DLL_READY			0x00080000L
+#define CLK_PWRMGT_CNTL__DISP_PM_MASK			0x00100000L
+#define CLK_PWRMGT_CNTL__DISP_PM			0x00100000L
+#define CLK_PWRMGT_CNTL__DYN_STOP_MODE_MASK		0x00e00000L
+#define CLK_PWRMGT_CNTL__CG_NO1_DEBUG_MASK		0x3f000000L
+#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF_MASK		0x40000000L
+#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF		0x40000000L
+#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF_MASK		0x80000000L
+#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF			0x80000000L
+
+/* BUS_CNTL1 */
+#define BUS_CNTL1__PMI_IO_DISABLE_MASK			0x00000001L
+#define BUS_CNTL1__PMI_IO_DISABLE			0x00000001L
+#define BUS_CNTL1__PMI_MEM_DISABLE_MASK			0x00000002L
+#define BUS_CNTL1__PMI_MEM_DISABLE			0x00000002L
+#define BUS_CNTL1__PMI_BM_DISABLE_MASK			0x00000004L
+#define BUS_CNTL1__PMI_BM_DISABLE			0x00000004L
+#define BUS_CNTL1__PMI_INT_DISABLE_MASK			0x00000008L
+#define BUS_CNTL1__PMI_INT_DISABLE			0x00000008L
+#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE_MASK	0x00000020L
+#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE		0x00000020L
+#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS_MASK	0x00000100L
+#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS		0x00000100L
+#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS_MASK	0x00000200L
+#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS		0x00000200L
+#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS_MASK	0x00000400L
+#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS		0x00000400L
+#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS_MASK 0x00000800L
+#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS	0x00000800L
+#define BUS_CNTL1__MOBILE_PLATFORM_SEL_MASK		0x0c000000L
+#define BUS_CNTL1__SEND_SBA_LATENCY_MASK		0x70000000L
+#define BUS_CNTL1__AGPCLK_VALID_MASK			0x80000000L
+#define BUS_CNTL1__AGPCLK_VALID				0x80000000L
+
+/* BUS_CNTL1 */
+#define BUS_CNTL1__PMI_IO_DISABLE__SHIFT		0x00000000
+#define BUS_CNTL1__PMI_MEM_DISABLE__SHIFT		0x00000001
+#define BUS_CNTL1__PMI_BM_DISABLE__SHIFT		0x00000002
+#define BUS_CNTL1__PMI_INT_DISABLE__SHIFT		0x00000003
+#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE__SHIFT	0x00000005
+#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS__SHIFT	0x00000008
+#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS__SHIFT	0x00000009
+#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS__SHIFT	0x0000000a
+#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS__SHIFT 0x0000000b
+#define BUS_CNTL1__MOBILE_PLATFORM_SEL__SHIFT		0x0000001a
+#define BUS_CNTL1__SEND_SBA_LATENCY__SHIFT		0x0000001c
+#define BUS_CNTL1__AGPCLK_VALID__SHIFT			0x0000001f
+
+/* CRTC_OFFSET_CNTL */
+#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_MASK		0x0000000fL
+#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_RIGHT_MASK	0x000000f0L
+#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT_MASK	0x00004000L
+#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT		0x00004000L
+#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_MASK		0x00008000L
+#define CRTC_OFFSET_CNTL__CRTC_TILE_EN			0x00008000L
+#define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL_MASK	0x00010000L
+#define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL		0x00010000L
+#define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN_MASK	0x00020000L
+#define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN		0x00020000L
+#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_EN_MASK	0x000c0000L
+#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN_MASK	0x00100000L
+#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN	0x00100000L
+#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_MASK		0x00200000L
+#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC		0x00200000L
+#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN_MASK 0x10000000L
+#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN	0x10000000L
+#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN_MASK 0x20000000L
+#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN	0x20000000L
+#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_MASK	0x40000000L
+#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET		0x40000000L
+#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK_MASK		0x80000000L
+#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK		0x80000000L
+
+/* CRTC_GEN_CNTL */
+#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN_MASK		0x00000001L
+#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN			0x00000001L
+#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN_MASK		0x00000002L
+#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN		0x00000002L
+#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN_MASK		0x00000010L
+#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN			0x00000010L
+#define CRTC_GEN_CNTL__CRTC_PIX_WIDTH_MASK		0x00000f00L
+#define CRTC_GEN_CNTL__CRTC_ICON_EN_MASK		0x00008000L
+#define CRTC_GEN_CNTL__CRTC_ICON_EN			0x00008000L
+#define CRTC_GEN_CNTL__CRTC_CUR_EN_MASK			0x00010000L
+#define CRTC_GEN_CNTL__CRTC_CUR_EN			0x00010000L
+#define CRTC_GEN_CNTL__CRTC_VSTAT_MODE_MASK		0x00060000L
+#define CRTC_GEN_CNTL__CRTC_CUR_MODE_MASK		0x00700000L
+#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN_MASK		0x01000000L
+#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN			0x01000000L
+#define CRTC_GEN_CNTL__CRTC_EN_MASK			0x02000000L
+#define CRTC_GEN_CNTL__CRTC_EN				0x02000000L
+#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B_MASK		0x04000000L
+#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B		0x04000000L
+
+/* CRTC2_GEN_CNTL */
+#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN_MASK		0x00000001L
+#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN		0x00000001L
+#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN_MASK		0x00000002L
+#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN		0x00000002L
+#define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE_MASK	0x00000010L
+#define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE		0x00000010L
+#define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE_MASK	0x00000020L
+#define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE		0x00000020L
+#define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE_MASK	0x00000040L
+#define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE		0x00000040L
+#define CRTC2_GEN_CNTL__CRT2_ON_MASK			0x00000080L
+#define CRTC2_GEN_CNTL__CRT2_ON				0x00000080L
+#define CRTC2_GEN_CNTL__CRTC2_PIX_WIDTH_MASK		0x00000f00L
+#define CRTC2_GEN_CNTL__CRTC2_ICON_EN_MASK		0x00008000L
+#define CRTC2_GEN_CNTL__CRTC2_ICON_EN			0x00008000L
+#define CRTC2_GEN_CNTL__CRTC2_CUR_EN_MASK		0x00010000L
+#define CRTC2_GEN_CNTL__CRTC2_CUR_EN			0x00010000L
+#define CRTC2_GEN_CNTL__CRTC2_CUR_MODE_MASK		0x00700000L
+#define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS_MASK		0x00800000L
+#define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS		0x00800000L
+#define CRTC2_GEN_CNTL__CRTC2_EN_MASK			0x02000000L
+#define CRTC2_GEN_CNTL__CRTC2_EN			0x02000000L
+#define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B_MASK	0x04000000L
+#define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B		0x04000000L
+#define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN_MASK		0x08000000L
+#define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN			0x08000000L
+#define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS_MASK		0x10000000L
+#define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS			0x10000000L
+#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS_MASK		0x20000000L
+#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS			0x20000000L
+
+/* AGP_CNTL */
+#define AGP_CNTL__MAX_IDLE_CLK_MASK			0x000000ffL
+#define AGP_CNTL__HOLD_RD_FIFO_MASK			0x00000100L
+#define AGP_CNTL__HOLD_RD_FIFO				0x00000100L
+#define AGP_CNTL__HOLD_RQ_FIFO_MASK			0x00000200L
+#define AGP_CNTL__HOLD_RQ_FIFO				0x00000200L
+#define AGP_CNTL__EN_2X_STBB_MASK			0x00000400L
+#define AGP_CNTL__EN_2X_STBB				0x00000400L
+#define AGP_CNTL__FORCE_FULL_SBA_MASK			0x00000800L
+#define AGP_CNTL__FORCE_FULL_SBA			0x00000800L
+#define AGP_CNTL__SBA_DIS_MASK				0x00001000L
+#define AGP_CNTL__SBA_DIS				0x00001000L
+#define AGP_CNTL__AGP_REV_ID_MASK			0x00002000L
+#define AGP_CNTL__AGP_REV_ID				0x00002000L
+#define AGP_CNTL__REG_CRIPPLE_AGP4X_MASK		0x00004000L
+#define AGP_CNTL__REG_CRIPPLE_AGP4X			0x00004000L
+#define AGP_CNTL__REG_CRIPPLE_AGP2X4X_MASK		0x00008000L
+#define AGP_CNTL__REG_CRIPPLE_AGP2X4X			0x00008000L
+#define AGP_CNTL__FORCE_INT_VREF_MASK			0x00010000L
+#define AGP_CNTL__FORCE_INT_VREF			0x00010000L
+#define AGP_CNTL__PENDING_SLOTS_VAL_MASK		0x00060000L
+#define AGP_CNTL__PENDING_SLOTS_SEL_MASK		0x00080000L
+#define AGP_CNTL__PENDING_SLOTS_SEL			0x00080000L
+#define AGP_CNTL__EN_EXTENDED_AD_STB_2X_MASK		0x00100000L
+#define AGP_CNTL__EN_EXTENDED_AD_STB_2X			0x00100000L
+#define AGP_CNTL__DIS_QUEUED_GNT_FIX_MASK		0x00200000L
+#define AGP_CNTL__DIS_QUEUED_GNT_FIX			0x00200000L
+#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET_MASK		0x00400000L
+#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET		0x00400000L
+#define AGP_CNTL__EN_RBFCALM_MASK			0x00800000L
+#define AGP_CNTL__EN_RBFCALM				0x00800000L
+#define AGP_CNTL__FORCE_EXT_VREF_MASK			0x01000000L
+#define AGP_CNTL__FORCE_EXT_VREF			0x01000000L
+#define AGP_CNTL__DIS_RBF_MASK				0x02000000L
+#define AGP_CNTL__DIS_RBF				0x02000000L
+#define AGP_CNTL__DELAY_FIRST_SBA_EN_MASK		0x04000000L
+#define AGP_CNTL__DELAY_FIRST_SBA_EN			0x04000000L
+#define AGP_CNTL__DELAY_FIRST_SBA_VAL_MASK		0x38000000L
+#define AGP_CNTL__AGP_MISC_MASK				0xc0000000L
+
+/* AGP_CNTL */
+#define AGP_CNTL__MAX_IDLE_CLK__SHIFT			0x00000000
+#define AGP_CNTL__HOLD_RD_FIFO__SHIFT			0x00000008
+#define AGP_CNTL__HOLD_RQ_FIFO__SHIFT			0x00000009
+#define AGP_CNTL__EN_2X_STBB__SHIFT			0x0000000a
+#define AGP_CNTL__FORCE_FULL_SBA__SHIFT			0x0000000b
+#define AGP_CNTL__SBA_DIS__SHIFT			0x0000000c
+#define AGP_CNTL__AGP_REV_ID__SHIFT			0x0000000d
+#define AGP_CNTL__REG_CRIPPLE_AGP4X__SHIFT		0x0000000e
+#define AGP_CNTL__REG_CRIPPLE_AGP2X4X__SHIFT		0x0000000f
+#define AGP_CNTL__FORCE_INT_VREF__SHIFT			0x00000010
+#define AGP_CNTL__PENDING_SLOTS_VAL__SHIFT		0x00000011
+#define AGP_CNTL__PENDING_SLOTS_SEL__SHIFT		0x00000013
+#define AGP_CNTL__EN_EXTENDED_AD_STB_2X__SHIFT		0x00000014
+#define AGP_CNTL__DIS_QUEUED_GNT_FIX__SHIFT		0x00000015
+#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET__SHIFT	0x00000016
+#define AGP_CNTL__EN_RBFCALM__SHIFT			0x00000017
+#define AGP_CNTL__FORCE_EXT_VREF__SHIFT			0x00000018
+#define AGP_CNTL__DIS_RBF__SHIFT			0x00000019
+#define AGP_CNTL__DELAY_FIRST_SBA_EN__SHIFT		0x0000001a
+#define AGP_CNTL__DELAY_FIRST_SBA_VAL__SHIFT		0x0000001b
+#define AGP_CNTL__AGP_MISC__SHIFT			0x0000001e
+
+/* DISP_MISC_CNTL */
+#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP_MASK		0x00000001L
+#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP		0x00000001L
+#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP_MASK	0x00000002L
+#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP		0x00000002L
+#define DISP_MISC_CNTL__SOFT_RESET_OV0_PP_MASK		0x00000004L
+#define DISP_MISC_CNTL__SOFT_RESET_OV0_PP		0x00000004L
+#define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK_MASK	0x00000010L
+#define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK		0x00000010L
+#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK_MASK	0x00000020L
+#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK		0x00000020L
+#define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK_MASK	0x00000040L
+#define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK		0x00000040L
+#define DISP_MISC_CNTL__SYNC_STRENGTH_MASK		0x00000300L
+#define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN_MASK		0x00000400L
+#define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN		0x00000400L
+#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP_MASK	0x00001000L
+#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP		0x00001000L
+#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK_MASK	0x00008000L
+#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK		0x00008000L
+#define DISP_MISC_CNTL__SOFT_RESET_LVDS_MASK		0x00010000L
+#define DISP_MISC_CNTL__SOFT_RESET_LVDS			0x00010000L
+#define DISP_MISC_CNTL__SOFT_RESET_TMDS_MASK		0x00020000L
+#define DISP_MISC_CNTL__SOFT_RESET_TMDS			0x00020000L
+#define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS_MASK	0x00040000L
+#define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS		0x00040000L
+#define DISP_MISC_CNTL__SOFT_RESET_TV_MASK		0x00080000L
+#define DISP_MISC_CNTL__SOFT_RESET_TV			0x00080000L
+#define DISP_MISC_CNTL__PALETTE2_MEM_RD_MARGIN_MASK	0x00f00000L
+#define DISP_MISC_CNTL__PALETTE_MEM_RD_MARGIN_MASK	0x0f000000L
+#define DISP_MISC_CNTL__RMX_BUF_MEM_RD_MARGIN_MASK	0xf0000000L
+
+/* DISP_PWR_MAN */
+#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN_MASK	0x00000001L
+#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN		0x00000001L
+#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN_MASK	0x00000010L
+#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN		0x00000010L
+#define DISP_PWR_MAN__DISP_PWR_MAN_DPMS_MASK		0x00000300L
+#define DISP_PWR_MAN__DISP_D3_RST_MASK			0x00010000L
+#define DISP_PWR_MAN__DISP_D3_RST			0x00010000L
+#define DISP_PWR_MAN__DISP_D3_REG_RST_MASK		0x00020000L
+#define DISP_PWR_MAN__DISP_D3_REG_RST			0x00020000L
+#define DISP_PWR_MAN__DISP_D3_GRPH_RST_MASK		0x00040000L
+#define DISP_PWR_MAN__DISP_D3_GRPH_RST			0x00040000L
+#define DISP_PWR_MAN__DISP_D3_SUBPIC_RST_MASK		0x00080000L
+#define DISP_PWR_MAN__DISP_D3_SUBPIC_RST		0x00080000L
+#define DISP_PWR_MAN__DISP_D3_OV0_RST_MASK		0x00100000L
+#define DISP_PWR_MAN__DISP_D3_OV0_RST			0x00100000L
+#define DISP_PWR_MAN__DISP_D1D2_GRPH_RST_MASK		0x00200000L
+#define DISP_PWR_MAN__DISP_D1D2_GRPH_RST		0x00200000L
+#define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST_MASK		0x00400000L
+#define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST		0x00400000L
+#define DISP_PWR_MAN__DISP_D1D2_OV0_RST_MASK		0x00800000L
+#define DISP_PWR_MAN__DISP_D1D2_OV0_RST			0x00800000L
+#define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST_MASK		0x01000000L
+#define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST		0x01000000L
+#define DISP_PWR_MAN__TV_ENABLE_RST_MASK		0x02000000L
+#define DISP_PWR_MAN__TV_ENABLE_RST			0x02000000L
+#define DISP_PWR_MAN__AUTO_PWRUP_EN_MASK		0x04000000L
+#define DISP_PWR_MAN__AUTO_PWRUP_EN			0x04000000L
+
+/* MC_IND_INDEX */
+#define MC_IND_INDEX__MC_IND_ADDR_MASK			0x0000001fL
+#define MC_IND_INDEX__MC_IND_WR_EN_MASK			0x00000100L
+#define MC_IND_INDEX__MC_IND_WR_EN			0x00000100L
+
+/* MC_IND_DATA */
+#define MC_IND_DATA__MC_IND_DATA_MASK			0xffffffffL
+
+/* MC_CHP_IO_CNTL_A1 */
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA__SHIFT		0x00000000
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA__SHIFT		0x00000001
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA__SHIFT	0x00000002
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA__SHIFT	0x00000003
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA__SHIFT		0x00000004
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA__SHIFT		0x00000005
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA__SHIFT	0x00000006
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA__SHIFT	0x00000007
+#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA__SHIFT		0x00000008
+#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA__SHIFT	0x00000009
+#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA__SHIFT	0x0000000a
+#define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA__SHIFT		0x0000000c
+#define MC_CHP_IO_CNTL_A1__MEM_REC_CKA__SHIFT		0x0000000e
+#define MC_CHP_IO_CNTL_A1__MEM_REC_AA__SHIFT		0x00000010
+#define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA__SHIFT		0x00000012
+#define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA__SHIFT		0x00000014
+#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA__SHIFT	0x00000016
+#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA__SHIFT	0x00000017
+#define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT		0x00000018
+#define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA__SHIFT		0x0000001a
+#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA__SHIFT		0x0000001c
+#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A__SHIFT	0x0000001e
+#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A__SHIFT	0x0000001f
+
+/* MC_CHP_IO_CNTL_B1 */
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB__SHIFT		0x00000000
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB__SHIFT		0x00000001
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB__SHIFT	0x00000002
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB__SHIFT	0x00000003
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB__SHIFT		0x00000004
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB__SHIFT		0x00000005
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB__SHIFT	0x00000006
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB__SHIFT	0x00000007
+#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB__SHIFT		0x00000008
+#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB__SHIFT	0x00000009
+#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB__SHIFT	0x0000000a
+#define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB__SHIFT		0x0000000c
+#define MC_CHP_IO_CNTL_B1__MEM_REC_CKB__SHIFT		0x0000000e
+#define MC_CHP_IO_CNTL_B1__MEM_REC_AB__SHIFT		0x00000010
+#define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB__SHIFT		0x00000012
+#define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB__SHIFT		0x00000014
+#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB__SHIFT	0x00000016
+#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB__SHIFT	0x00000017
+#define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT		0x00000018
+#define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB__SHIFT		0x0000001a
+#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB__SHIFT		0x0000001c
+#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B__SHIFT	0x0000001e
+#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B__SHIFT	0x0000001f
+
+/* MC_CHP_IO_CNTL_A1 */
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA_MASK		0x00000001L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA		0x00000001L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA_MASK		0x00000002L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA			0x00000002L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA_MASK		0x00000004L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA		0x00000004L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA_MASK		0x00000008L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA		0x00000008L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA_MASK		0x00000010L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA		0x00000010L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA_MASK		0x00000020L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA			0x00000020L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA_MASK		0x00000040L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA		0x00000040L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA_MASK		0x00000080L
+#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA		0x00000080L
+#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA_MASK		0x00000100L
+#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA		0x00000100L
+#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA_MASK		0x00000200L
+#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA		0x00000200L
+#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA_MASK		0x00000400L
+#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA		0x00000400L
+#define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA_MASK		0x00003000L
+#define MC_CHP_IO_CNTL_A1__MEM_REC_CKA_MASK		0x0000c000L
+#define MC_CHP_IO_CNTL_A1__MEM_REC_AA_MASK		0x00030000L
+#define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA_MASK		0x000c0000L
+#define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA_MASK		0x00300000L
+#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA_MASK		0x00400000L
+#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA		0x00400000L
+#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA_MASK	0x00800000L
+#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA		0x00800000L
+#define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK		0x03000000L
+#define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA_MASK		0x0c000000L
+#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA_MASK		0x10000000L
+#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA			0x10000000L
+#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A_MASK	0x40000000L
+#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A		0x40000000L
+#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A_MASK	0x80000000L
+#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A		0x80000000L
+
+/* MC_CHP_IO_CNTL_B1 */
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB_MASK		0x00000001L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB		0x00000001L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB_MASK		0x00000002L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB			0x00000002L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB_MASK		0x00000004L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB		0x00000004L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB_MASK		0x00000008L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB		0x00000008L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB_MASK		0x00000010L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB		0x00000010L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB_MASK		0x00000020L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB			0x00000020L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB_MASK		0x00000040L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB		0x00000040L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB_MASK		0x00000080L
+#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB		0x00000080L
+#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB_MASK		0x00000100L
+#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB		0x00000100L
+#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB_MASK		0x00000200L
+#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB		0x00000200L
+#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB_MASK		0x00000400L
+#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB		0x00000400L
+#define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB_MASK		0x00003000L
+#define MC_CHP_IO_CNTL_B1__MEM_REC_CKB_MASK		0x0000c000L
+#define MC_CHP_IO_CNTL_B1__MEM_REC_AB_MASK		0x00030000L
+#define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB_MASK		0x000c0000L
+#define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB_MASK		0x00300000L
+#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB_MASK		0x00400000L
+#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB		0x00400000L
+#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB_MASK	0x00800000L
+#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB		0x00800000L
+#define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK		0x03000000L
+#define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB_MASK		0x0c000000L
+#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB_MASK		0x10000000L
+#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB			0x10000000L
+#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B_MASK	0x40000000L
+#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B		0x40000000L
+#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B_MASK	0x80000000L
+#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B		0x80000000L
+
+/* MEM_SDRAM_MODE_REG */
+#define MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK		0x00007fffL
+#define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY_MASK		0x000f0000L
+#define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY_MASK	0x00700000L
+#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY_MASK	0x00800000L
+#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY		0x00800000L
+#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY_MASK	0x01000000L
+#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY		0x01000000L
+#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD_MASK	0x02000000L
+#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD		0x02000000L
+#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA_MASK	0x04000000L
+#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA		0x04000000L
+#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR_MASK	0x08000000L
+#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR		0x08000000L
+#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE_MASK	0x10000000L
+#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE		0x10000000L
+#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL_MASK		0x20000000L
+#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL			0x20000000L
+#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE_MASK		0x40000000L
+#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE		0x40000000L
+#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET_MASK	0x80000000L
+#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET		0x80000000L
+
+/* MEM_SDRAM_MODE_REG */
+#define MEM_SDRAM_MODE_REG__MEM_MODE_REG__SHIFT		0x00000000
+#define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY__SHIFT	0x00000010
+#define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY__SHIFT	0x00000014
+#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY__SHIFT	0x00000017
+#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY__SHIFT	0x00000018
+#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD__SHIFT	0x00000019
+#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA__SHIFT	0x0000001a
+#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR__SHIFT	0x0000001b
+#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE__SHIFT	0x0000001c
+#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL__SHIFT		0x0000001d
+#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE__SHIFT		0x0000001e
+#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET__SHIFT	0x0000001f
+
+/* MEM_REFRESH_CNTL */
+#define MEM_REFRESH_CNTL__MEM_REFRESH_RATE_MASK		0x000000ffL
+#define MEM_REFRESH_CNTL__MEM_REFRESH_DIS_MASK		0x00000100L
+#define MEM_REFRESH_CNTL__MEM_REFRESH_DIS		0x00000100L
+#define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE_MASK		0x00000200L
+#define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE		0x00000200L
+#define MEM_REFRESH_CNTL__MEM_TRFC_MASK			0x0000f000L
+#define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE_MASK		0x00010000L
+#define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE		0x00010000L
+#define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE_MASK	0x00020000L
+#define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE		0x00020000L
+#define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE_MASK		0x00040000L
+#define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE		0x00040000L
+#define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE_MASK	0x00080000L
+#define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE		0x00080000L
+#define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE_MASK	0x00100000L
+#define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE		0x00100000L
+#define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKA_MASK		0x00c00000L
+#define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE_MASK		0x01000000L
+#define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE		0x01000000L
+#define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE_MASK	0x02000000L
+#define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE		0x02000000L
+#define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE_MASK		0x04000000L
+#define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE		0x04000000L
+#define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE_MASK	0x08000000L
+#define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE		0x08000000L
+#define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE_MASK	0x10000000L
+#define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE		0x10000000L
+#define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKB_MASK		0xc0000000L
+
+/* MC_STATUS */
+#define MC_STATUS__MEM_PWRUP_COMPL_A_MASK		0x00000001L
+#define MC_STATUS__MEM_PWRUP_COMPL_A			0x00000001L
+#define MC_STATUS__MEM_PWRUP_COMPL_B_MASK		0x00000002L
+#define MC_STATUS__MEM_PWRUP_COMPL_B			0x00000002L
+#define MC_STATUS__MC_IDLE_MASK				0x00000004L
+#define MC_STATUS__MC_IDLE				0x00000004L
+#define MC_STATUS__IMP_N_VALUE_R_BACK_MASK		0x00000078L
+#define MC_STATUS__IMP_P_VALUE_R_BACK_MASK		0x00000780L
+#define MC_STATUS__TEST_OUT_R_BACK_MASK			0x00000800L
+#define MC_STATUS__TEST_OUT_R_BACK			0x00000800L
+#define MC_STATUS__DUMMY_OUT_R_BACK_MASK		0x00001000L
+#define MC_STATUS__DUMMY_OUT_R_BACK			0x00001000L
+#define MC_STATUS__IMP_N_VALUE_A_R_BACK_MASK		0x0001e000L
+#define MC_STATUS__IMP_P_VALUE_A_R_BACK_MASK		0x001e0000L
+#define MC_STATUS__IMP_N_VALUE_CK_R_BACK_MASK		0x01e00000L
+#define MC_STATUS__IMP_P_VALUE_CK_R_BACK_MASK		0x1e000000L
+
+/* MDLL_CKO */
+#define MDLL_CKO__MCKOA_SLEEP_MASK			0x00000001L
+#define MDLL_CKO__MCKOA_SLEEP				0x00000001L
+#define MDLL_CKO__MCKOA_RESET_MASK			0x00000002L
+#define MDLL_CKO__MCKOA_RESET				0x00000002L
+#define MDLL_CKO__MCKOA_RANGE_MASK			0x0000000cL
+#define MDLL_CKO__ERSTA_SOUTSEL_MASK			0x00000030L
+#define MDLL_CKO__MCKOA_FB_SEL_MASK			0x000000c0L
+#define MDLL_CKO__MCKOA_REF_SKEW_MASK			0x00000700L
+#define MDLL_CKO__MCKOA_FB_SKEW_MASK			0x00007000L
+#define MDLL_CKO__MCKOA_BP_SEL_MASK			0x00008000L
+#define MDLL_CKO__MCKOA_BP_SEL				0x00008000L
+#define MDLL_CKO__MCKOB_SLEEP_MASK			0x00010000L
+#define MDLL_CKO__MCKOB_SLEEP				0x00010000L
+#define MDLL_CKO__MCKOB_RESET_MASK			0x00020000L
+#define MDLL_CKO__MCKOB_RESET				0x00020000L
+#define MDLL_CKO__MCKOB_RANGE_MASK			0x000c0000L
+#define MDLL_CKO__ERSTB_SOUTSEL_MASK			0x00300000L
+#define MDLL_CKO__MCKOB_FB_SEL_MASK			0x00c00000L
+#define MDLL_CKO__MCKOB_REF_SKEW_MASK			0x07000000L
+#define MDLL_CKO__MCKOB_FB_SKEW_MASK			0x70000000L
+#define MDLL_CKO__MCKOB_BP_SEL_MASK			0x80000000L
+#define MDLL_CKO__MCKOB_BP_SEL				0x80000000L
+
+/* MDLL_RDCKA */
+#define MDLL_RDCKA__MRDCKA0_SLEEP_MASK			0x00000001L
+#define MDLL_RDCKA__MRDCKA0_SLEEP			0x00000001L
+#define MDLL_RDCKA__MRDCKA0_RESET_MASK			0x00000002L
+#define MDLL_RDCKA__MRDCKA0_RESET			0x00000002L
+#define MDLL_RDCKA__MRDCKA0_RANGE_MASK			0x0000000cL
+#define MDLL_RDCKA__MRDCKA0_REF_SEL_MASK		0x00000030L
+#define MDLL_RDCKA__MRDCKA0_FB_SEL_MASK			0x000000c0L
+#define MDLL_RDCKA__MRDCKA0_REF_SKEW_MASK		0x00000700L
+#define MDLL_RDCKA__MRDCKA0_SINSEL_MASK			0x00000800L
+#define MDLL_RDCKA__MRDCKA0_SINSEL			0x00000800L
+#define MDLL_RDCKA__MRDCKA0_FB_SKEW_MASK		0x00007000L
+#define MDLL_RDCKA__MRDCKA0_BP_SEL_MASK			0x00008000L
+#define MDLL_RDCKA__MRDCKA0_BP_SEL			0x00008000L
+#define MDLL_RDCKA__MRDCKA1_SLEEP_MASK			0x00010000L
+#define MDLL_RDCKA__MRDCKA1_SLEEP			0x00010000L
+#define MDLL_RDCKA__MRDCKA1_RESET_MASK			0x00020000L
+#define MDLL_RDCKA__MRDCKA1_RESET			0x00020000L
+#define MDLL_RDCKA__MRDCKA1_RANGE_MASK			0x000c0000L
+#define MDLL_RDCKA__MRDCKA1_REF_SEL_MASK		0x00300000L
+#define MDLL_RDCKA__MRDCKA1_FB_SEL_MASK			0x00c00000L
+#define MDLL_RDCKA__MRDCKA1_REF_SKEW_MASK		0x07000000L
+#define MDLL_RDCKA__MRDCKA1_SINSEL_MASK			0x08000000L
+#define MDLL_RDCKA__MRDCKA1_SINSEL			0x08000000L
+#define MDLL_RDCKA__MRDCKA1_FB_SKEW_MASK		0x70000000L
+#define MDLL_RDCKA__MRDCKA1_BP_SEL_MASK			0x80000000L
+#define MDLL_RDCKA__MRDCKA1_BP_SEL			0x80000000L
+
+/* MDLL_RDCKB */
+#define MDLL_RDCKB__MRDCKB0_SLEEP_MASK			0x00000001L
+#define MDLL_RDCKB__MRDCKB0_SLEEP			0x00000001L
+#define MDLL_RDCKB__MRDCKB0_RESET_MASK			0x00000002L
+#define MDLL_RDCKB__MRDCKB0_RESET			0x00000002L
+#define MDLL_RDCKB__MRDCKB0_RANGE_MASK			0x0000000cL
+#define MDLL_RDCKB__MRDCKB0_REF_SEL_MASK		0x00000030L
+#define MDLL_RDCKB__MRDCKB0_FB_SEL_MASK			0x000000c0L
+#define MDLL_RDCKB__MRDCKB0_REF_SKEW_MASK		0x00000700L
+#define MDLL_RDCKB__MRDCKB0_SINSEL_MASK			0x00000800L
+#define MDLL_RDCKB__MRDCKB0_SINSEL			0x00000800L
+#define MDLL_RDCKB__MRDCKB0_FB_SKEW_MASK		0x00007000L
+#define MDLL_RDCKB__MRDCKB0_BP_SEL_MASK			0x00008000L
+#define MDLL_RDCKB__MRDCKB0_BP_SEL			0x00008000L
+#define MDLL_RDCKB__MRDCKB1_SLEEP_MASK			0x00010000L
+#define MDLL_RDCKB__MRDCKB1_SLEEP			0x00010000L
+#define MDLL_RDCKB__MRDCKB1_RESET_MASK			0x00020000L
+#define MDLL_RDCKB__MRDCKB1_RESET			0x00020000L
+#define MDLL_RDCKB__MRDCKB1_RANGE_MASK			0x000c0000L
+#define MDLL_RDCKB__MRDCKB1_REF_SEL_MASK		0x00300000L
+#define MDLL_RDCKB__MRDCKB1_FB_SEL_MASK			0x00c00000L
+#define MDLL_RDCKB__MRDCKB1_REF_SKEW_MASK		0x07000000L
+#define MDLL_RDCKB__MRDCKB1_SINSEL_MASK			0x08000000L
+#define MDLL_RDCKB__MRDCKB1_SINSEL			0x08000000L
+#define MDLL_RDCKB__MRDCKB1_FB_SKEW_MASK		0x70000000L
+#define MDLL_RDCKB__MRDCKB1_BP_SEL_MASK			0x80000000L
+#define MDLL_RDCKB__MRDCKB1_BP_SEL			0x80000000L
+
+#define MDLL_R300_RDCK__MRDCKA_SLEEP			0x00000001L
+#define MDLL_R300_RDCK__MRDCKA_RESET			0x00000002L
+#define MDLL_R300_RDCK__MRDCKB_SLEEP			0x00000004L
+#define MDLL_R300_RDCK__MRDCKB_RESET			0x00000008L
+#define MDLL_R300_RDCK__MRDCKC_SLEEP			0x00000010L
+#define MDLL_R300_RDCK__MRDCKC_RESET			0x00000020L
+#define MDLL_R300_RDCK__MRDCKD_SLEEP			0x00000040L
+#define MDLL_R300_RDCK__MRDCKD_RESET			0x00000080L
+
+#define pllCLK_PIN_CNTL				0x0001
+#define pllPPLL_CNTL				0x0002
+#define pllPPLL_REF_DIV				0x0003
+#define pllPPLL_DIV_0				0x0004
+#define pllPPLL_DIV_1				0x0005
+#define pllPPLL_DIV_2				0x0006
+#define pllPPLL_DIV_3				0x0007
+#define pllVCLK_ECP_CNTL			0x0008
+#define pllHTOTAL_CNTL				0x0009
+#define pllM_SPLL_REF_FB_DIV			0x000A
+#define pllAGP_PLL_CNTL				0x000B
+#define pllSPLL_CNTL				0x000C
+#define pllSCLK_CNTL				0x000D
+#define pllMPLL_CNTL				0x000E
+#define pllMDLL_CKO				0x000F
+#define pllMDLL_RDCKA				0x0010
+#define pllMDLL_RDCKB				0x0011
+#define pllMCLK_CNTL				0x0012
+#define pllPLL_TEST_CNTL			0x0013
+#define pllCLK_PWRMGT_CNTL			0x0014
+#define pllPLL_PWRMGT_CNTL			0x0015
+#define pllCG_TEST_MACRO_RW_WRITE		0x0016
+#define pllCG_TEST_MACRO_RW_READ		0x0017
+#define pllCG_TEST_MACRO_RW_DATA		0x0018
+#define pllCG_TEST_MACRO_RW_CNTL		0x0019
+#define pllDISP_TEST_MACRO_RW_WRITE		0x001A
+#define pllDISP_TEST_MACRO_RW_READ		0x001B
+#define pllDISP_TEST_MACRO_RW_DATA		0x001C
+#define pllDISP_TEST_MACRO_RW_CNTL		0x001D
+#define pllSCLK_CNTL2				0x001E
+#define pllMCLK_MISC				0x001F
+#define pllTV_PLL_FINE_CNTL			0x0020
+#define pllTV_PLL_CNTL				0x0021
+#define pllTV_PLL_CNTL1				0x0022
+#define pllTV_DTO_INCREMENTS			0x0023
+#define pllSPLL_AUX_CNTL			0x0024
+#define pllMPLL_AUX_CNTL			0x0025
+#define pllP2PLL_CNTL				0x002A
+#define pllP2PLL_REF_DIV			0x002B
+#define pllP2PLL_DIV_0				0x002C
+#define pllPIXCLKS_CNTL				0x002D
+#define pllHTOTAL2_CNTL				0x002E
+#define pllSSPLL_CNTL				0x0030
+#define pllSSPLL_REF_DIV			0x0031
+#define pllSSPLL_DIV_0				0x0032
+#define pllSS_INT_CNTL				0x0033
+#define pllSS_TST_CNTL				0x0034
+#define pllSCLK_MORE_CNTL			0x0035
+
+#define ixMC_PERF_CNTL				0x0000
+#define ixMC_PERF_SEL				0x0001
+#define ixMC_PERF_REGION_0			0x0002
+#define ixMC_PERF_REGION_1			0x0003
+#define ixMC_PERF_COUNT_0			0x0004
+#define ixMC_PERF_COUNT_1			0x0005
+#define ixMC_PERF_COUNT_2			0x0006
+#define ixMC_PERF_COUNT_3			0x0007
+#define ixMC_PERF_COUNT_MEMCH_A			0x0008
+#define ixMC_PERF_COUNT_MEMCH_B			0x0009
+#define ixMC_IMP_CNTL				0x000A
+#define ixMC_CHP_IO_CNTL_A0			0x000B
+#define ixMC_CHP_IO_CNTL_A1			0x000C
+#define ixMC_CHP_IO_CNTL_B0			0x000D
+#define ixMC_CHP_IO_CNTL_B1			0x000E
+#define ixMC_IMP_CNTL_0				0x000F
+#define ixTC_MISMATCH_1				0x0010
+#define ixTC_MISMATCH_2				0x0011
+#define ixMC_BIST_CTRL				0x0012
+#define ixREG_COLLAR_WRITE			0x0013
+#define ixREG_COLLAR_READ			0x0014
+#define ixR300_MC_IMP_CNTL			0x0018
+#define ixR300_MC_CHP_IO_CNTL_A0		0x0019
+#define ixR300_MC_CHP_IO_CNTL_A1		0x001a
+#define ixR300_MC_CHP_IO_CNTL_B0		0x001b
+#define ixR300_MC_CHP_IO_CNTL_B1		0x001c
+#define ixR300_MC_CHP_IO_CNTL_C0		0x001d
+#define ixR300_MC_CHP_IO_CNTL_C1		0x001e
+#define ixR300_MC_CHP_IO_CNTL_D0		0x001f
+#define ixR300_MC_CHP_IO_CNTL_D1		0x0020
+#define ixR300_MC_IMP_CNTL_0			0x0021
+#define ixR300_MC_ELPIDA_CNTL			0x0022
+#define ixR300_MC_CHP_IO_OE_CNTL_CD		0x0023
+#define ixR300_MC_READ_CNTL_CD			0x0024
+#define ixR300_MC_MC_INIT_WR_LAT_TIMER		0x0025
+#define ixR300_MC_DEBUG_CNTL			0x0026
+#define ixR300_MC_BIST_CNTL_0			0x0028
+#define ixR300_MC_BIST_CNTL_1			0x0029
+#define ixR300_MC_BIST_CNTL_2			0x002a
+#define ixR300_MC_BIST_CNTL_3			0x002b
+#define ixR300_MC_BIST_CNTL_4			0x002c
+#define ixR300_MC_BIST_CNTL_5			0x002d
+#define ixR300_MC_IMP_STATUS			0x002e
+#define ixR300_MC_DLL_CNTL			0x002f
+#define NB_TOM					0x15C
+
+#endif	/* _RADEON_H */
diff --git a/qemu/roms/u-boot/include/reiserfs.h b/qemu/roms/u-boot/include/reiserfs.h
new file mode 100644
index 000000000..2d14d48fe
--- /dev/null
+++ b/qemu/roms/u-boot/include/reiserfs.h
@@ -0,0 +1,70 @@
+/*
+ *  Copyright 2000-2002 by Hans Reiser, licensing governed by reiserfs/README
+ *
+ *  GRUB  --  GRand Unified Bootloader
+ *  Copyright (C) 2000, 2001  Free Software Foundation, Inc.
+ *
+ *  (C) Copyright 2003 Sysgo Real-Time Solutions, AG <www.elinos.com>
+ *  Pavel Bartusek <pba@sysgo.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* An implementation for the ReiserFS filesystem ported from GRUB.
+ * Some parts of this code (mainly the structures and defines) are
+ * from the original reiser fs code, as found in the linux kernel.
+ */
+
+
+#define SECTOR_SIZE		0x200
+#define SECTOR_BITS		9
+
+/* Error codes */
+typedef enum
+{
+  ERR_NONE = 0,
+  ERR_BAD_FILENAME,
+  ERR_BAD_FILETYPE,
+  ERR_BAD_GZIP_DATA,
+  ERR_BAD_GZIP_HEADER,
+  ERR_BAD_PART_TABLE,
+  ERR_BAD_VERSION,
+  ERR_BELOW_1MB,
+  ERR_BOOT_COMMAND,
+  ERR_BOOT_FAILURE,
+  ERR_BOOT_FEATURES,
+  ERR_DEV_FORMAT,
+  ERR_DEV_VALUES,
+  ERR_EXEC_FORMAT,
+  ERR_FILELENGTH,
+  ERR_FILE_NOT_FOUND,
+  ERR_FSYS_CORRUPT,
+  ERR_FSYS_MOUNT,
+  ERR_GEOM,
+  ERR_NEED_LX_KERNEL,
+  ERR_NEED_MB_KERNEL,
+  ERR_NO_DISK,
+  ERR_NO_PART,
+  ERR_NUMBER_PARSING,
+  ERR_OUTSIDE_PART,
+  ERR_READ,
+  ERR_SYMLINK_LOOP,
+  ERR_UNRECOGNIZED,
+  ERR_WONT_FIT,
+  ERR_WRITE,
+  ERR_BAD_ARGUMENT,
+  ERR_UNALIGNED,
+  ERR_PRIVILEGED,
+  ERR_DEV_NEED_INIT,
+  ERR_NO_DISK_SPACE,
+  ERR_NUMBER_OVERFLOW,
+
+  MAX_ERR_NUM
+} reiserfs_error_t;
+
+
+extern void reiserfs_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info);
+extern int reiserfs_ls (char *dirname);
+extern int reiserfs_open (char *filename);
+extern int reiserfs_read (char *buf, unsigned len);
+extern int reiserfs_mount (unsigned part_length);
diff --git a/qemu/roms/u-boot/include/rsa-checksum.h b/qemu/roms/u-boot/include/rsa-checksum.h
new file mode 100644
index 000000000..612db85fe
--- /dev/null
+++ b/qemu/roms/u-boot/include/rsa-checksum.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2013, Andreas Oetken.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+*/
+
+#ifndef _RSA_CHECKSUM_H
+#define _RSA_CHECKSUM_H
+
+#include <errno.h>
+#include <image.h>
+#include <sha1.h>
+#include <sha256.h>
+
+extern const uint8_t padding_sha256_rsa4096[];
+extern const uint8_t padding_sha256_rsa2048[];
+extern const uint8_t padding_sha1_rsa2048[];
+
+void sha256_calculate(const struct image_region region[], int region_count,
+		      uint8_t *checksum);
+void sha1_calculate(const struct image_region region[], int region_count,
+		    uint8_t *checksum);
+
+#endif
diff --git a/qemu/roms/u-boot/include/rsa.h b/qemu/roms/u-boot/include/rsa.h
new file mode 100644
index 000000000..a5680ab88
--- /dev/null
+++ b/qemu/roms/u-boot/include/rsa.h
@@ -0,0 +1,116 @@
+/*
+ * Copyright (c) 2013, Google Inc.
+ *
+ * (C) Copyright 2008 Semihalf
+ *
+ * (C) Copyright 2000-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _RSA_H
+#define _RSA_H
+
+#include <errno.h>
+#include <image.h>
+
+/**
+ * struct rsa_public_key - holder for a public key
+ *
+ * An RSA public key consists of a modulus (typically called N), the inverse
+ * and R^2, where R is 2^(# key bits).
+ */
+
+struct rsa_public_key {
+	uint len;		/* len of modulus[] in number of uint32_t */
+	uint32_t n0inv;		/* -1 / modulus[0] mod 2^32 */
+	uint32_t *modulus;	/* modulus as little endian array */
+	uint32_t *rr;		/* R^2 as little endian array */
+};
+
+#if IMAGE_ENABLE_SIGN
+/**
+ * sign() - calculate and return signature for given input data
+ *
+ * @info:	Specifies key and FIT information
+ * @data:	Pointer to the input data
+ * @data_len:	Data length
+ * @sigp:	Set to an allocated buffer holding the signature
+ * @sig_len:	Set to length of the calculated hash
+ *
+ * This computes input data signature according to selected algorithm.
+ * Resulting signature value is placed in an allocated buffer, the
+ * pointer is returned as *sigp. The length of the calculated
+ * signature is returned via the sig_len pointer argument. The caller
+ * should free *sigp.
+ *
+ * @return: 0, on success, -ve on error
+ */
+int rsa_sign(struct image_sign_info *info,
+	     const struct image_region region[],
+	     int region_count, uint8_t **sigp, uint *sig_len);
+
+/**
+ * add_verify_data() - Add verification information to FDT
+ *
+ * Add public key information to the FDT node, suitable for
+ * verification at run-time. The information added depends on the
+ * algorithm being used.
+ *
+ * @info:	Specifies key and FIT information
+ * @keydest:	Destination FDT blob for public key data
+ * @return: 0, on success, -ve on error
+*/
+int rsa_add_verify_data(struct image_sign_info *info, void *keydest);
+#else
+static inline int rsa_sign(struct image_sign_info *info,
+		const struct image_region region[], int region_count,
+		uint8_t **sigp, uint *sig_len)
+{
+	return -ENXIO;
+}
+
+static inline int rsa_add_verify_data(struct image_sign_info *info,
+				      void *keydest)
+{
+	return -ENXIO;
+}
+#endif
+
+#if IMAGE_ENABLE_VERIFY
+/**
+ * rsa_verify() - Verify a signature against some data
+ *
+ * Verify a RSA PKCS1.5 signature against an expected hash.
+ *
+ * @info:	Specifies key and FIT information
+ * @data:	Pointer to the input data
+ * @data_len:	Data length
+ * @sig:	Signature
+ * @sig_len:	Number of bytes in signature
+ * @return 0 if verified, -ve on error
+ */
+int rsa_verify(struct image_sign_info *info,
+	       const struct image_region region[], int region_count,
+	       uint8_t *sig, uint sig_len);
+#else
+static inline int rsa_verify(struct image_sign_info *info,
+		const struct image_region region[], int region_count,
+		uint8_t *sig, uint sig_len)
+{
+	return -ENXIO;
+}
+#endif
+
+#define RSA2048_BYTES	(2048 / 8)
+#define RSA4096_BYTES	(4096 / 8)
+
+/* This is the minimum/maximum key size we support, in bits */
+#define RSA_MIN_KEY_BITS	2048
+#define RSA_MAX_KEY_BITS	4096
+
+/* This is the maximum signature length that we support, in bits */
+#define RSA_MAX_SIG_BITS	4096
+
+#endif
diff --git a/qemu/roms/u-boot/include/rtc.h b/qemu/roms/u-boot/include/rtc.h
new file mode 100644
index 000000000..c0349668b
--- /dev/null
+++ b/qemu/roms/u-boot/include/rtc.h
@@ -0,0 +1,53 @@
+/*
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Generic RTC interface.
+ */
+#ifndef _RTC_H_
+#define _RTC_H_
+
+/* bcd<->bin functions are needed by almost all the RTC drivers, let's include
+ * it there instead of in evey single driver */
+
+#include <bcd.h>
+
+/*
+ * The struct used to pass data from the generic interface code to
+ * the hardware dependend low-level code ande vice versa. Identical
+ * to struct rtc_time used by the Linux kernel.
+ *
+ * Note that there are small but significant differences to the
+ * common "struct time":
+ *
+ *		struct time:		struct rtc_time:
+ * tm_mon	0 ... 11		1 ... 12
+ * tm_year	years since 1900	years since 0
+ */
+
+struct rtc_time {
+	int tm_sec;
+	int tm_min;
+	int tm_hour;
+	int tm_mday;
+	int tm_mon;
+	int tm_year;
+	int tm_wday;
+	int tm_yday;
+	int tm_isdst;
+};
+
+int rtc_get (struct rtc_time *);
+int rtc_set (struct rtc_time *);
+void rtc_reset (void);
+
+void GregorianDay (struct rtc_time *);
+void to_tm (int, struct rtc_time *);
+unsigned long mktime (unsigned int, unsigned int, unsigned int,
+		      unsigned int, unsigned int, unsigned int);
+
+#endif	/* _RTC_H_ */
diff --git a/qemu/roms/u-boot/include/s6e63d6.h b/qemu/roms/u-boot/include/s6e63d6.h
new file mode 100644
index 000000000..aa583eed1
--- /dev/null
+++ b/qemu/roms/u-boot/include/s6e63d6.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2009
+ * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _S6E63D6_H_
+#define _S6E63D6_H_
+
+struct s6e63d6 {
+	unsigned int bus;
+	unsigned int cs;
+	unsigned int id;
+	struct spi_slave *slave;
+};
+
+extern int s6e63d6_init(struct s6e63d6 *data);
+extern int s6e63d6_index(struct s6e63d6 *data, u8 idx);
+extern int s6e63d6_param(struct s6e63d6 *data, u16 param);
+
+#endif
diff --git a/qemu/roms/u-boot/include/s_record.h b/qemu/roms/u-boot/include/s_record.h
new file mode 100644
index 000000000..6db717464
--- /dev/null
+++ b/qemu/roms/u-boot/include/s_record.h
@@ -0,0 +1,98 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*--------------------------------------------------------------------------
+ *
+ * Motorola S-Record Format:
+ *
+ * Motorola S-Records are an industry-standard format for
+ * transmitting binary files to target systems and PROM
+ * programmers. LSI Logic have extended this standard to include
+ * an S4-record containing an address and a symbol.
+ *
+ * The extended S-record standard is as follows:
+ *
+ * S<type><length><address><data....><checksum>
+ * S4<length><address><name>,<checksum>
+ *
+ * Where:
+ *
+ * type
+ *     is the record type. Where:
+ *
+ *     0  starting record (optional)
+ *     1  data record with 16-bit address
+ *     2  data record with 24-bit address
+ *     3  data record with 32-bit address
+ *     4  symbol record (LSI extension)
+ *     5  number of data records in preceeding block
+ *     6  unused
+ *     7  ending record for S3 records
+ *     8  ending record for S2 records
+ *     9  ending record for S1 records
+ *
+ * length
+ *     is two hex characters. This defines the length of the
+ *     record in bytes (not characters). It includes the address
+ *     field, the data field, and the checksum field.
+ *
+ * address
+ *     is 4, 6, or 8 characters. Corresponding to a 16-, 24-, or
+ *     32-bit address. The address field for S4 records is
+ *     always 32 bits.
+ *
+ * data
+ *
+ *     Are the data bytes. Each pair of hex characters represent
+ *     one byte in memory.
+ *
+ * name
+ *     Is the symbol name. The symbol is terminated by a ','.
+ *
+ * checksum
+ *     Is the one's complement of the 8-bit checksum.
+ *
+ * Example
+ *
+ * S0030000FC
+ * .
+ * .
+ * S325000004403C0880018D08DD900000000011000026000000003C0880012508DC50C50000B401
+ * S32500000460C50100B8C50200BCC50300C0C50400C4C50500C8C50600CCC50700D0C50800D4FA
+ * S32500000480C50900D8C50A00DCC50B00E0C50C00E4C50D00E8C50E00ECC50F00F0C51000F49A
+ * S325000004A0C51100F8C51200FCC5130100C5140104C5150108C516010CC5170110C518011434
+ * .
+ * .
+ * S70500000000FA
+ *
+ * The S0 record starts the file. The S3 records contain the
+ * data. The S7 record contains the entry address and terminates
+ * the download.
+ *
+ *--------------------------------------------------------------------------
+ */
+
+#define SREC_START	0	/* Start Record (module name)		    */
+#define SREC_DATA2	1	/* Data  Record with 2 byte address	    */
+#define SREC_DATA3	2	/* Data  Record with 3 byte address	    */
+#define SREC_DATA4	3	/* Data  Record with 4 byte address	    */
+#define SREC_COUNT	5	/* Count Record (previously transmitted)    */
+#define SREC_END4	7	/* End   Record with 4 byte start address   */
+#define SREC_END3	8	/* End   Record with 3 byte start address   */
+#define SREC_END2	9	/* End   Record with 2 byte start address   */
+#define SREC_EMPTY	10	/* Empty Record without any data	    */
+
+#define SREC_REC_OK  SREC_EMPTY /* last code without error condition	    */
+
+#define SREC_E_BADTYPE	-1	/* no valid S-Record		            */
+#define SREC_E_NOSREC	-2	/* line format differs from s-record	    */
+#define SREC_E_BADCHKS	-3	/* checksum error in an s-record line	    */
+
+#define SREC_MAXRECLEN	(512 + 4)   /* max ASCII record length		    */
+#define SREC_MAXBINLEN	255	    /* resulting binary length		    */
+
+int srec_decode (char *input, int *count, ulong *addr, char *data);
diff --git a/qemu/roms/u-boot/include/samsung/misc.h b/qemu/roms/u-boot/include/samsung/misc.h
new file mode 100644
index 000000000..ede6c1583
--- /dev/null
+++ b/qemu/roms/u-boot/include/samsung/misc.h
@@ -0,0 +1,29 @@
+#ifndef __SAMSUNG_MISC_COMMON_H__
+#define __SAMSUNG_MISC_COMMON_H__
+
+#ifdef CONFIG_REVISION_TAG
+u32 get_board_rev(void);
+#endif
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+void set_board_info(void);
+#endif
+
+#ifdef CONFIG_LCD_MENU
+enum {
+	BOOT_MODE_INFO,
+	BOOT_MODE_THOR,
+	BOOT_MODE_UMS,
+	BOOT_MODE_DFU,
+	BOOT_MODE_EXIT,
+};
+
+void keys_init(void);
+void check_boot_mode(void);
+#endif /* CONFIG_LCD_MENU */
+
+#ifdef CONFIG_CMD_BMP
+void draw_logo(void);
+#endif
+
+#endif /* __SAMSUNG_MISC_COMMON_H__ */
diff --git a/qemu/roms/u-boot/include/sandboxblockdev.h b/qemu/roms/u-boot/include/sandboxblockdev.h
new file mode 100644
index 000000000..627787aa3
--- /dev/null
+++ b/qemu/roms/u-boot/include/sandboxblockdev.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2013, Henrik Nordstrom <henrik@henriknordstrom.net>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __SANDBOX_BLOCK_DEV__
+#define __SANDBOX_BLOCK_DEV__
+
+struct host_block_dev {
+	block_dev_desc_t blk_dev;
+	char *filename;
+	int fd;
+};
+
+int host_dev_bind(int dev, char *filename);
+
+#endif
diff --git a/qemu/roms/u-boot/include/sandboxfs.h b/qemu/roms/u-boot/include/sandboxfs.h
new file mode 100644
index 000000000..a51ad1304
--- /dev/null
+++ b/qemu/roms/u-boot/include/sandboxfs.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2012, Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __SANDBOX_FS__
+#define __SANDBOX_FS__
+
+int sandbox_fs_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info);
+
+long sandbox_fs_read_at(const char *filename, unsigned long pos,
+			     void *buffer, unsigned long maxsize);
+
+void sandbox_fs_close(void);
+int sandbox_fs_ls(const char *dirname);
+int sandbox_fs_exists(const char *filename);
+int fs_read_sandbox(const char *filename, void *buf, int offset, int len);
+int fs_write_sandbox(const char *filename, void *buf, int offset, int len);
+
+#endif
diff --git a/qemu/roms/u-boot/include/sata.h b/qemu/roms/u-boot/include/sata.h
new file mode 100644
index 000000000..c95dc56e9
--- /dev/null
+++ b/qemu/roms/u-boot/include/sata.h
@@ -0,0 +1,15 @@
+#ifndef __SATA_H__
+#define __SATA_H__
+#include <part.h>
+
+int init_sata(int dev);
+int scan_sata(int dev);
+ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer);
+ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer);
+
+int sata_initialize(void);
+int __sata_initialize(void);
+
+extern block_dev_desc_t sata_dev_desc[];
+
+#endif
diff --git a/qemu/roms/u-boot/include/scf0403_lcd.h b/qemu/roms/u-boot/include/scf0403_lcd.h
new file mode 100644
index 000000000..d71896bbd
--- /dev/null
+++ b/qemu/roms/u-boot/include/scf0403_lcd.h
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2013, Compulab Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef SCF0403_LCD_H_
+#define SCF0403_LCD_H_
+
+int scf0403_init(int reset_gpio);
+
+#endif
diff --git a/qemu/roms/u-boot/include/scsi.h b/qemu/roms/u-boot/include/scsi.h
new file mode 100644
index 000000000..73de7b746
--- /dev/null
+++ b/qemu/roms/u-boot/include/scsi.h
@@ -0,0 +1,190 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+ #ifndef _SCSI_H
+ #define _SCSI_H
+
+typedef struct SCSI_cmd_block{
+	unsigned char		cmd[16];					/* command				   */
+	/* for request sense */
+	unsigned char		sense_buf[64]
+		__attribute__((aligned(ARCH_DMA_MINALIGN)));
+	unsigned char		status;						/* SCSI Status			 */
+	unsigned char		target;						/* Target ID				 */
+	unsigned char		lun;							/* Target LUN        */
+	unsigned char		cmdlen;						/* command len				*/
+	unsigned long		datalen;					/* Total data length	*/
+	unsigned char	*	pdata;						/* pointer to data		*/
+	unsigned char		msgout[12];				/* Messge out buffer (NOT USED) */
+	unsigned char		msgin[12];				/* Message in buffer	*/
+	unsigned char		sensecmdlen;			/* Sense command len	*/
+	unsigned long		sensedatalen;			/* Sense data len			*/
+	unsigned char		sensecmd[6];			/* Sense command			*/
+	unsigned long		contr_stat;				/* Controller Status	*/
+	unsigned long		trans_bytes;			/* tranfered bytes		*/
+
+	unsigned int		priv;
+}ccb;
+
+/*-----------------------------------------------------------
+**
+**	SCSI  constants.
+**
+**-----------------------------------------------------------
+*/
+
+/*
+**	Messages
+*/
+
+#define	M_COMPLETE	(0x00)
+#define	M_EXTENDED	(0x01)
+#define	M_SAVE_DP	(0x02)
+#define	M_RESTORE_DP	(0x03)
+#define	M_DISCONNECT	(0x04)
+#define	M_ID_ERROR	(0x05)
+#define	M_ABORT		(0x06)
+#define	M_REJECT	(0x07)
+#define	M_NOOP		(0x08)
+#define	M_PARITY	(0x09)
+#define	M_LCOMPLETE	(0x0a)
+#define	M_FCOMPLETE	(0x0b)
+#define	M_RESET		(0x0c)
+#define	M_ABORT_TAG	(0x0d)
+#define	M_CLEAR_QUEUE	(0x0e)
+#define	M_INIT_REC	(0x0f)
+#define	M_REL_REC	(0x10)
+#define	M_TERMINATE	(0x11)
+#define	M_SIMPLE_TAG	(0x20)
+#define	M_HEAD_TAG	(0x21)
+#define	M_ORDERED_TAG	(0x22)
+#define	M_IGN_RESIDUE	(0x23)
+#define	M_IDENTIFY	(0x80)
+
+#define	M_X_MODIFY_DP	(0x00)
+#define	M_X_SYNC_REQ	(0x01)
+#define	M_X_WIDE_REQ	(0x03)
+#define	M_X_PPR_REQ	(0x04)
+
+
+/*
+**	Status
+*/
+
+#define	S_GOOD		(0x00)
+#define	S_CHECK_COND	(0x02)
+#define	S_COND_MET	(0x04)
+#define	S_BUSY		(0x08)
+#define	S_INT		(0x10)
+#define	S_INT_COND_MET	(0x14)
+#define	S_CONFLICT	(0x18)
+#define	S_TERMINATED	(0x20)
+#define	S_QUEUE_FULL	(0x28)
+#define	S_ILLEGAL	(0xff)
+#define	S_SENSE		(0x80)
+
+/*
+ * Sense_keys
+ */
+
+#define SENSE_NO_SENSE				0x0
+#define SENSE_RECOVERED_ERROR	0x1
+#define SENSE_NOT_READY				0x2
+#define SENSE_MEDIUM_ERROR		0x3
+#define SENSE_HARDWARE_ERROR	0x4
+#define SENSE_ILLEGAL_REQUEST	0x5
+#define SENSE_UNIT_ATTENTION	0x6
+#define SENSE_DATA_PROTECT		0x7
+#define SENSE_BLANK_CHECK			0x8
+#define SENSE_VENDOR_SPECIFIC	0x9
+#define SENSE_COPY_ABORTED		0xA
+#define SENSE_ABORTED_COMMAND	0xB
+#define SENSE_VOLUME_OVERFLOW	0xD
+#define SENSE_MISCOMPARE			0xE
+
+
+#define SCSI_CHANGE_DEF	0x40		/* Change Definition (Optional) */
+#define SCSI_COMPARE		0x39		/* Compare (O) */
+#define SCSI_COPY			0x18		/* Copy (O) */
+#define SCSI_COP_VERIFY	0x3A		/* Copy and Verify (O) */
+#define SCSI_INQUIRY		0x12		/* Inquiry (MANDATORY) */
+#define SCSI_LOG_SELECT	0x4C		/* Log Select (O) */
+#define SCSI_LOG_SENSE	0x4D		/* Log Sense (O) */
+#define SCSI_MODE_SEL6	0x15		/* Mode Select 6-byte (Device Specific) */
+#define SCSI_MODE_SEL10	0x55		/* Mode Select 10-byte (Device Specific) */
+#define SCSI_MODE_SEN6	0x1A		/* Mode Sense 6-byte (Device Specific) */
+#define SCSI_MODE_SEN10	0x5A		/* Mode Sense 10-byte (Device Specific) */
+#define SCSI_READ_BUFF	0x3C		/* Read Buffer (O) */
+#define SCSI_REQ_SENSE	0x03		/* Request Sense (MANDATORY) */
+#define SCSI_SEND_DIAG	0x1D		/* Send Diagnostic (O) */
+#define SCSI_TST_U_RDY	0x00		/* Test Unit Ready (MANDATORY) */
+#define SCSI_WRITE_BUFF	0x3B		/* Write Buffer (O) */
+/***************************************************************************
+ *			  %%% Commands Unique to Direct Access Devices %%%
+ ***************************************************************************/
+#define SCSI_COMPARE		0x39		/* Compare (O) */
+#define SCSI_FORMAT		0x04		/* Format Unit (MANDATORY) */
+#define SCSI_LCK_UN_CAC	0x36		/* Lock Unlock Cache (O) */
+#define SCSI_PREFETCH	0x34		/* Prefetch (O) */
+#define SCSI_MED_REMOVL	0x1E		/* Prevent/Allow medium Removal (O) */
+#define SCSI_READ6		0x08		/* Read 6-byte (MANDATORY) */
+#define SCSI_READ10		0x28		/* Read 10-byte (MANDATORY) */
+#define SCSI_RD_CAPAC	0x25		/* Read Capacity (MANDATORY) */
+#define SCSI_RD_CAPAC10	SCSI_RD_CAPAC	/* Read Capacity (10) */
+#define SCSI_RD_CAPAC16	0x9e		/* Read Capacity (16) */
+#define SCSI_RD_DEFECT	0x37		/* Read Defect Data (O) */
+#define SCSI_READ_LONG	0x3E		/* Read Long (O) */
+#define SCSI_REASS_BLK	0x07		/* Reassign Blocks (O) */
+#define SCSI_RCV_DIAG	0x1C		/* Receive Diagnostic Results (O) */
+#define SCSI_RELEASE	0x17		/* Release Unit (MANDATORY) */
+#define SCSI_REZERO		0x01		/* Rezero Unit (O) */
+#define SCSI_SRCH_DAT_E	0x31		/* Search Data Equal (O) */
+#define SCSI_SRCH_DAT_H	0x30		/* Search Data High (O) */
+#define SCSI_SRCH_DAT_L	0x32		/* Search Data Low (O) */
+#define SCSI_SEEK6		0x0B		/* Seek 6-Byte (O) */
+#define SCSI_SEEK10		0x2B		/* Seek 10-Byte (O) */
+#define SCSI_SEND_DIAG	0x1D		/* Send Diagnostics (MANDATORY) */
+#define SCSI_SET_LIMIT	0x33		/* Set Limits (O) */
+#define SCSI_START_STP	0x1B		/* Start/Stop Unit (O) */
+#define SCSI_SYNC_CACHE	0x35		/* Synchronize Cache (O) */
+#define SCSI_VERIFY		0x2F		/* Verify (O) */
+#define SCSI_WRITE6		0x0A		/* Write 6-Byte (MANDATORY) */
+#define SCSI_WRITE10	0x2A		/* Write 10-Byte (MANDATORY) */
+#define SCSI_WRT_VERIFY	0x2E		/* Write and Verify (O) */
+#define SCSI_WRITE_LONG	0x3F		/* Write Long (O) */
+#define SCSI_WRITE_SAME	0x41		/* Write Same (O) */
+
+
+/****************************************************************************
+ * decleration of functions which have to reside in the LowLevel Part Driver
+ */
+
+void scsi_print_error(ccb *pccb);
+int scsi_exec(ccb *pccb);
+void scsi_bus_reset(void);
+void scsi_low_level_init(int busdevfunc);
+
+
+/***************************************************************************
+ * functions residing inside cmd_scsi.c
+ */
+void scsi_init(void);
+void scsi_scan(int mode);
+
+/** @return the number of scsi disks */
+int scsi_get_disk_count(void);
+
+#define SCSI_IDENTIFY					0xC0  /* not used */
+
+/* Hardware errors  */
+#define SCSI_SEL_TIME_OUT			 0x00000101	 /* Selection time out */
+#define SCSI_HNS_TIME_OUT			 0x00000102  /* Handshake */
+#define SCSI_MA_TIME_OUT			 0x00000103  /* Phase error */
+#define SCSI_UNEXP_DIS				 0x00000104  /* unexpected disconnect */
+
+#define SCSI_INT_STATE				 0x00010000  /* unknown Interrupt number is stored in 16 LSB */
+
+#endif /* _SCSI_H */
diff --git a/qemu/roms/u-boot/include/sdhci.h b/qemu/roms/u-boot/include/sdhci.h
new file mode 100644
index 000000000..aa4a0e965
--- /dev/null
+++ b/qemu/roms/u-boot/include/sdhci.h
@@ -0,0 +1,342 @@
+/*
+ * Copyright 2011, Marvell Semiconductor Inc.
+ * Lei Wen <leiwen@marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Back ported to the 8xx platform (from the 8260 platform) by
+ * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
+ */
+#ifndef __SDHCI_HW_H
+#define __SDHCI_HW_H
+
+#include <asm/io.h>
+#include <mmc.h>
+#include <fdtdec.h>
+
+/*
+ * Controller registers
+ */
+
+#define SDHCI_DMA_ADDRESS	0x00
+
+#define SDHCI_BLOCK_SIZE	0x04
+#define  SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
+
+#define SDHCI_BLOCK_COUNT	0x06
+
+#define SDHCI_ARGUMENT		0x08
+
+#define SDHCI_TRANSFER_MODE	0x0C
+#define  SDHCI_TRNS_DMA		0x01
+#define  SDHCI_TRNS_BLK_CNT_EN	0x02
+#define  SDHCI_TRNS_ACMD12	0x04
+#define  SDHCI_TRNS_READ	0x10
+#define  SDHCI_TRNS_MULTI	0x20
+
+#define SDHCI_COMMAND		0x0E
+#define  SDHCI_CMD_RESP_MASK	0x03
+#define  SDHCI_CMD_CRC		0x08
+#define  SDHCI_CMD_INDEX	0x10
+#define  SDHCI_CMD_DATA		0x20
+#define  SDHCI_CMD_ABORTCMD	0xC0
+
+#define  SDHCI_CMD_RESP_NONE	0x00
+#define  SDHCI_CMD_RESP_LONG	0x01
+#define  SDHCI_CMD_RESP_SHORT	0x02
+#define  SDHCI_CMD_RESP_SHORT_BUSY 0x03
+
+#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
+#define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
+
+#define SDHCI_RESPONSE		0x10
+
+#define SDHCI_BUFFER		0x20
+
+#define SDHCI_PRESENT_STATE	0x24
+#define  SDHCI_CMD_INHIBIT	0x00000001
+#define  SDHCI_DATA_INHIBIT	0x00000002
+#define  SDHCI_DOING_WRITE	0x00000100
+#define  SDHCI_DOING_READ	0x00000200
+#define  SDHCI_SPACE_AVAILABLE	0x00000400
+#define  SDHCI_DATA_AVAILABLE	0x00000800
+#define  SDHCI_CARD_PRESENT	0x00010000
+#define  SDHCI_CARD_STATE_STABLE	0x00020000
+#define  SDHCI_CARD_DETECT_PIN_LEVEL	0x00040000
+#define  SDHCI_WRITE_PROTECT	0x00080000
+
+#define SDHCI_HOST_CONTROL	0x28
+#define  SDHCI_CTRL_LED		0x01
+#define  SDHCI_CTRL_4BITBUS	0x02
+#define  SDHCI_CTRL_HISPD	0x04
+#define  SDHCI_CTRL_DMA_MASK	0x18
+#define   SDHCI_CTRL_SDMA	0x00
+#define   SDHCI_CTRL_ADMA1	0x08
+#define   SDHCI_CTRL_ADMA32	0x10
+#define   SDHCI_CTRL_ADMA64	0x18
+#define  SDHCI_CTRL_8BITBUS	0x20
+#define  SDHCI_CTRL_CD_TEST_INS	0x40
+#define  SDHCI_CTRL_CD_TEST	0x80
+
+#define SDHCI_POWER_CONTROL	0x29
+#define  SDHCI_POWER_ON		0x01
+#define  SDHCI_POWER_180	0x0A
+#define  SDHCI_POWER_300	0x0C
+#define  SDHCI_POWER_330	0x0E
+
+#define SDHCI_BLOCK_GAP_CONTROL	0x2A
+
+#define SDHCI_WAKE_UP_CONTROL	0x2B
+#define  SDHCI_WAKE_ON_INT	0x01
+#define  SDHCI_WAKE_ON_INSERT	0x02
+#define  SDHCI_WAKE_ON_REMOVE	0x04
+
+#define SDHCI_CLOCK_CONTROL	0x2C
+#define  SDHCI_DIVIDER_SHIFT	8
+#define  SDHCI_DIVIDER_HI_SHIFT	6
+#define  SDHCI_DIV_MASK	0xFF
+#define  SDHCI_DIV_MASK_LEN	8
+#define  SDHCI_DIV_HI_MASK	0x300
+#define  SDHCI_CLOCK_CARD_EN	0x0004
+#define  SDHCI_CLOCK_INT_STABLE	0x0002
+#define  SDHCI_CLOCK_INT_EN	0x0001
+
+#define SDHCI_TIMEOUT_CONTROL	0x2E
+
+#define SDHCI_SOFTWARE_RESET	0x2F
+#define  SDHCI_RESET_ALL	0x01
+#define  SDHCI_RESET_CMD	0x02
+#define  SDHCI_RESET_DATA	0x04
+
+#define SDHCI_INT_STATUS	0x30
+#define SDHCI_INT_ENABLE	0x34
+#define SDHCI_SIGNAL_ENABLE	0x38
+#define  SDHCI_INT_RESPONSE	0x00000001
+#define  SDHCI_INT_DATA_END	0x00000002
+#define  SDHCI_INT_DMA_END	0x00000008
+#define  SDHCI_INT_SPACE_AVAIL	0x00000010
+#define  SDHCI_INT_DATA_AVAIL	0x00000020
+#define  SDHCI_INT_CARD_INSERT	0x00000040
+#define  SDHCI_INT_CARD_REMOVE	0x00000080
+#define  SDHCI_INT_CARD_INT	0x00000100
+#define  SDHCI_INT_ERROR	0x00008000
+#define  SDHCI_INT_TIMEOUT	0x00010000
+#define  SDHCI_INT_CRC		0x00020000
+#define  SDHCI_INT_END_BIT	0x00040000
+#define  SDHCI_INT_INDEX	0x00080000
+#define  SDHCI_INT_DATA_TIMEOUT	0x00100000
+#define  SDHCI_INT_DATA_CRC	0x00200000
+#define  SDHCI_INT_DATA_END_BIT	0x00400000
+#define  SDHCI_INT_BUS_POWER	0x00800000
+#define  SDHCI_INT_ACMD12ERR	0x01000000
+#define  SDHCI_INT_ADMA_ERROR	0x02000000
+
+#define  SDHCI_INT_NORMAL_MASK	0x00007FFF
+#define  SDHCI_INT_ERROR_MASK	0xFFFF8000
+
+#define  SDHCI_INT_CMD_MASK	(SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
+		SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
+#define  SDHCI_INT_DATA_MASK	(SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
+		SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
+		SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
+		SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR)
+#define SDHCI_INT_ALL_MASK	((unsigned int)-1)
+
+#define SDHCI_ACMD12_ERR	0x3C
+
+/* 3E-3F reserved */
+
+#define SDHCI_CAPABILITIES	0x40
+#define  SDHCI_TIMEOUT_CLK_MASK	0x0000003F
+#define  SDHCI_TIMEOUT_CLK_SHIFT 0
+#define  SDHCI_TIMEOUT_CLK_UNIT	0x00000080
+#define  SDHCI_CLOCK_BASE_MASK	0x00003F00
+#define  SDHCI_CLOCK_V3_BASE_MASK	0x0000FF00
+#define  SDHCI_CLOCK_BASE_SHIFT	8
+#define  SDHCI_MAX_BLOCK_MASK	0x00030000
+#define  SDHCI_MAX_BLOCK_SHIFT  16
+#define  SDHCI_CAN_DO_8BIT	0x00040000
+#define  SDHCI_CAN_DO_ADMA2	0x00080000
+#define  SDHCI_CAN_DO_ADMA1	0x00100000
+#define  SDHCI_CAN_DO_HISPD	0x00200000
+#define  SDHCI_CAN_DO_SDMA	0x00400000
+#define  SDHCI_CAN_VDD_330	0x01000000
+#define  SDHCI_CAN_VDD_300	0x02000000
+#define  SDHCI_CAN_VDD_180	0x04000000
+#define  SDHCI_CAN_64BIT	0x10000000
+
+#define SDHCI_CAPABILITIES_1	0x44
+
+#define SDHCI_MAX_CURRENT	0x48
+
+/* 4C-4F reserved for more max current */
+
+#define SDHCI_SET_ACMD12_ERROR	0x50
+#define SDHCI_SET_INT_ERROR	0x52
+
+#define SDHCI_ADMA_ERROR	0x54
+
+/* 55-57 reserved */
+
+#define SDHCI_ADMA_ADDRESS	0x58
+
+/* 60-FB reserved */
+
+#define SDHCI_SLOT_INT_STATUS	0xFC
+
+#define SDHCI_HOST_VERSION	0xFE
+#define  SDHCI_VENDOR_VER_MASK	0xFF00
+#define  SDHCI_VENDOR_VER_SHIFT	8
+#define  SDHCI_SPEC_VER_MASK	0x00FF
+#define  SDHCI_SPEC_VER_SHIFT	0
+#define   SDHCI_SPEC_100	0
+#define   SDHCI_SPEC_200	1
+#define   SDHCI_SPEC_300	2
+
+#define SDHCI_GET_VERSION(x) (x->version & SDHCI_SPEC_VER_MASK)
+
+/*
+ * End of controller registers.
+ */
+
+#define SDHCI_MAX_DIV_SPEC_200	256
+#define SDHCI_MAX_DIV_SPEC_300	2046
+
+/*
+ * quirks
+ */
+#define SDHCI_QUIRK_32BIT_DMA_ADDR	(1 << 0)
+#define SDHCI_QUIRK_REG32_RW		(1 << 1)
+#define SDHCI_QUIRK_BROKEN_R1B		(1 << 2)
+#define SDHCI_QUIRK_NO_HISPD_BIT	(1 << 3)
+#define SDHCI_QUIRK_BROKEN_VOLTAGE	(1 << 4)
+#define SDHCI_QUIRK_NO_CD		(1 << 5)
+#define SDHCI_QUIRK_WAIT_SEND_CMD	(1 << 6)
+#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1 << 7)
+#define SDHCI_QUIRK_USE_WIDE8		(1 << 8)
+
+/* to make gcc happy */
+struct sdhci_host;
+
+/*
+ * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
+ */
+#define SDHCI_DEFAULT_BOUNDARY_SIZE	(512 * 1024)
+#define SDHCI_DEFAULT_BOUNDARY_ARG	(7)
+struct sdhci_ops {
+#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
+	u32             (*read_l)(struct sdhci_host *host, int reg);
+	u16             (*read_w)(struct sdhci_host *host, int reg);
+	u8              (*read_b)(struct sdhci_host *host, int reg);
+	void            (*write_l)(struct sdhci_host *host, u32 val, int reg);
+	void            (*write_w)(struct sdhci_host *host, u16 val, int reg);
+	void            (*write_b)(struct sdhci_host *host, u8 val, int reg);
+#endif
+};
+
+struct sdhci_host {
+	char *name;
+	void *ioaddr;
+	unsigned int quirks;
+	unsigned int host_caps;
+	unsigned int version;
+	unsigned int clock;
+	struct mmc *mmc;
+	const struct sdhci_ops *ops;
+	int index;
+
+	int bus_width;
+	struct fdt_gpio_state pwr_gpio;	/* Power GPIO */
+	struct fdt_gpio_state cd_gpio;		/* Card Detect GPIO */
+
+	void (*set_control_reg)(struct sdhci_host *host);
+	void (*set_clock)(int dev_index, unsigned int div);
+	uint	voltages;
+
+	struct mmc_config cfg;
+};
+
+#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
+
+static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
+{
+	if (unlikely(host->ops->write_l))
+		host->ops->write_l(host, val, reg);
+	else
+		writel(val, host->ioaddr + reg);
+}
+
+static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
+{
+	if (unlikely(host->ops->write_w))
+		host->ops->write_w(host, val, reg);
+	else
+		writew(val, host->ioaddr + reg);
+}
+
+static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
+{
+	if (unlikely(host->ops->write_b))
+		host->ops->write_b(host, val, reg);
+	else
+		writeb(val, host->ioaddr + reg);
+}
+
+static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
+{
+	if (unlikely(host->ops->read_l))
+		return host->ops->read_l(host, reg);
+	else
+		return readl(host->ioaddr + reg);
+}
+
+static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
+{
+	if (unlikely(host->ops->read_w))
+		return host->ops->read_w(host, reg);
+	else
+		return readw(host->ioaddr + reg);
+}
+
+static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
+{
+	if (unlikely(host->ops->read_b))
+		return host->ops->read_b(host, reg);
+	else
+		return readb(host->ioaddr + reg);
+}
+
+#else
+
+static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
+{
+	writel(val, host->ioaddr + reg);
+}
+
+static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
+{
+	writew(val, host->ioaddr + reg);
+}
+
+static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
+{
+	writeb(val, host->ioaddr + reg);
+}
+static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
+{
+	return readl(host->ioaddr + reg);
+}
+
+static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
+{
+	return readw(host->ioaddr + reg);
+}
+
+static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
+{
+	return readb(host->ioaddr + reg);
+}
+#endif
+
+int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk);
+#endif /* __SDHCI_HW_H */
diff --git a/qemu/roms/u-boot/include/search.h b/qemu/roms/u-boot/include/search.h
new file mode 100644
index 000000000..ae3efc43c
--- /dev/null
+++ b/qemu/roms/u-boot/include/search.h
@@ -0,0 +1,123 @@
+/*
+ * Declarations for System V style searching functions.
+ * Copyright (C) 1995-1999, 2000 Free Software Foundation, Inc.
+ * This file is part of the GNU C Library.
+ *
+ * SPDX-License-Identifier:	LGPL-2.1+
+ */
+
+/*
+ * Based on code from uClibc-0.9.30.3
+ * Extensions for use within U-Boot
+ * Copyright (C) 2010-2013 Wolfgang Denk <wd@denx.de>
+ */
+
+#ifndef _SEARCH_H
+#define	_SEARCH_H 1
+
+#include <stddef.h>
+
+#define __set_errno(val) do { errno = val; } while (0)
+
+enum env_op {
+	env_op_create,
+	env_op_delete,
+	env_op_overwrite,
+};
+
+/* Action which shall be performed in the call the hsearch.  */
+typedef enum {
+	FIND,
+	ENTER
+} ACTION;
+
+typedef struct entry {
+	const char *key;
+	char *data;
+	int (*callback)(const char *name, const char *value, enum env_op op,
+		int flags);
+	int flags;
+} ENTRY;
+
+/* Opaque type for internal use.  */
+struct _ENTRY;
+
+/*
+ * Family of hash table handling functions.  The functions also
+ * have reentrant counterparts ending with _r.  The non-reentrant
+ * functions all work on a signle internal hashing table.
+ */
+
+/* Data type for reentrant functions.  */
+struct hsearch_data {
+	struct _ENTRY *table;
+	unsigned int size;
+	unsigned int filled;
+/*
+ * Callback function which will check whether the given change for variable
+ * "item" to "newval" may be applied or not, and possibly apply such change.
+ * When (flag & H_FORCE) is set, it shall not print out any error message and
+ * shall force overwriting of write-once variables.
+.* Must return 0 for approval, 1 for denial.
+ */
+	int (*change_ok)(const ENTRY *__item, const char *newval, enum env_op,
+		int flag);
+};
+
+/* Create a new hashing table which will at most contain NEL elements.  */
+extern int hcreate_r(size_t __nel, struct hsearch_data *__htab);
+
+/* Destroy current internal hashing table.  */
+extern void hdestroy_r(struct hsearch_data *__htab);
+
+/*
+ * Search for entry matching ITEM.key in internal hash table.  If
+ * ACTION is `FIND' return found entry or signal error by returning
+ * NULL.  If ACTION is `ENTER' replace existing data (if any) with
+ * ITEM.data.
+ * */
+extern int hsearch_r(ENTRY __item, ACTION __action, ENTRY ** __retval,
+		     struct hsearch_data *__htab, int __flag);
+
+/*
+ * Search for an entry matching `MATCH'.  Otherwise, Same semantics
+ * as hsearch_r().
+ */
+extern int hmatch_r(const char *__match, int __last_idx, ENTRY ** __retval,
+		    struct hsearch_data *__htab);
+
+/* Search and delete entry matching ITEM.key in internal hash table. */
+extern int hdelete_r(const char *__key, struct hsearch_data *__htab,
+		     int __flag);
+
+extern ssize_t hexport_r(struct hsearch_data *__htab,
+		     const char __sep, int __flag, char **__resp, size_t __size,
+		     int argc, char * const argv[]);
+
+/*
+ * nvars: length of vars array
+ * vars: array of strings (variable names) to import (nvars == 0 means all)
+ * do_apply: whether to call callback function to check the new argument,
+ * and possibly apply changes (false means accept everything)
+ */
+extern int himport_r(struct hsearch_data *__htab,
+		     const char *__env, size_t __size, const char __sep,
+		     int __flag, int nvars, char * const vars[]);
+
+/* Walk the whole table calling the callback on each element */
+extern int hwalk_r(struct hsearch_data *__htab, int (*callback)(ENTRY *));
+
+/* Flags for himport_r(), hexport_r(), hdelete_r(), and hsearch_r() */
+#define H_NOCLEAR	(1 << 0) /* do not clear hash table before importing */
+#define H_FORCE		(1 << 1) /* overwrite read-only/write-once variables */
+#define H_INTERACTIVE	(1 << 2) /* indicate that an import is user directed */
+#define H_HIDE_DOT	(1 << 3) /* don't print env vars that begin with '.' */
+#define H_MATCH_KEY	(1 << 4) /* search/grep key  = variable names	     */
+#define H_MATCH_DATA	(1 << 5) /* search/grep data = variable values	     */
+#define H_MATCH_BOTH	(H_MATCH_KEY | H_MATCH_DATA) /* search/grep both     */
+#define H_MATCH_IDENT	(1 << 6) /* search for indentical strings	     */
+#define H_MATCH_SUBSTR	(1 << 7) /* search for substring matches	     */
+#define H_MATCH_REGEX	(1 << 8) /* search for regular expression matches    */
+#define H_MATCH_METHOD	(H_MATCH_IDENT | H_MATCH_SUBSTR | H_MATCH_REGEX)
+
+#endif /* search.h */
diff --git a/qemu/roms/u-boot/include/sed13806.h b/qemu/roms/u-boot/include/sed13806.h
new file mode 100644
index 000000000..1cb0b860f
--- /dev/null
+++ b/qemu/roms/u-boot/include/sed13806.h
@@ -0,0 +1,81 @@
+/*
+ * (C) Copyright 2002
+ * Stäubli Faverges - <www.staubli.com>
+ * Pierre AUBERT  p.aubert@staubli.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/* Video support for Epson SED13806 chipset                                  */
+
+
+#ifndef _SED13806_H_
+#define _SED13806_H_
+
+
+/* General definitions                                                       */
+#define FRAME_BUFFER_OFFSET        0x200000     /* Frame buffer offset */
+#define TOTAL_SPACE_SIZE           0x400000
+
+#define DEFAULT_VIDEO_MEMORY_SIZE  0x140000     /* Video Memory Size */
+
+#define HWCURSORSIZE		   1024     /* Size of memory reserved
+						   for HW cursor*/
+
+/* Offset of chipset registers                                               */
+#define	BLT_CTRL0	(0x0100)
+#define	BLT_CTRL1	(0x0101)
+#define BLT_ROP		(0x0102)
+#define	BLT_OP		(0x0103)
+#define BLT_SRC_ADDR0	(0x0104)
+#define	BLT_SRC_ADDR1	(0x0105)
+#define	BLT_SRC_ADDR2	(0x0106)
+#define	BLT_DST_ADDR0	(0x0108)
+#define BLT_DST_ADDR1	(0x0109)
+#define	BLT_DST_ADDR2	(0x010A)
+#define BLT_MEM_OFF0	(0x010C)
+#define BLT_MEM_OFF1	(0x010D)
+#define BLT_WIDTH0	(0x0110)
+#define BLT_WIDTH1	(0x0111)
+#define BLT_HEIGHT0	(0x0112)
+#define BLT_HEIGHT1	(0x0113)
+#define	BLT_BGCOLOR0	(0x0114)
+#define	BLT_BGCOLOR1	(0x0115)
+#define	BLT_FGCOLOR0	(0x0118)
+#define BLT_FGCOLOR1	(0x0119)
+
+#define BLT_REG         (0x100000)
+
+/* Lookup table registers                                                    */
+#define REG_LUT_ADDR 0x1e2
+#define REG_LUT_DATA 0x1e4
+
+/* Cursor/Ink registers                                                      */
+#define LCD_CURSOR_CNTL         (0x0070)
+#define LCD_CURSOR_START        (0x0071)
+#define LCD_CURSOR_XL           (0x0072)
+#define LCD_CURSOR_XM           (0x0073)
+#define LCD_CURSOR_YL           (0x0074)
+#define LCD_CURSOR_YM           (0x0075)
+#define LCD_CURSOR_COL0_B       (0x0076)
+#define LCD_CURSOR_COL0_G       (0x0077)
+#define LCD_CURSOR_COL0_R       (0x0078)
+#define LCD_CURSOR_COL1_B       (0x007A)
+#define LCD_CURSOR_COL1_G       (0x007B)
+#define LCD_CURSOR_COL1_R       (0x007C)
+#define LCD_CURSOR_FIFO         (0x007E)
+
+typedef struct
+{
+    unsigned short      Index;
+    unsigned char       Value;
+} S1D_REGS;
+
+
+/* Board specific functions                                                  */
+unsigned int board_video_init (void);
+void board_validate_screen (unsigned int base);
+const S1D_REGS *board_get_regs (void);
+int board_get_width (void);
+int board_get_height (void);
+
+#endif /* _SED13806_H_ */
diff --git a/qemu/roms/u-boot/include/sed156x.h b/qemu/roms/u-boot/include/sed156x.h
new file mode 100644
index 000000000..4e24e01d4
--- /dev/null
+++ b/qemu/roms/u-boot/include/sed156x.h
@@ -0,0 +1,26 @@
+/*
+ * (C) Copyright 2004
+ *
+ * Pantelis Antoniou <panto@intracom.gr>
+ * Intracom S.A.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* Video support for Epson SED156x chipset(s) */
+
+#ifndef SED156X_H
+#define SED156X_H
+
+void sed156x_init(void);
+void sed156x_clear(void);
+void sed156x_output_at(int x, int y, const char *str, int size);
+void sed156x_reverse_at(int x, int y, int size);
+void sed156x_sync(void);
+void sed156x_scroll(int dx, int dy);
+
+/* export display */
+extern const int sed156x_text_width;
+extern const int sed156x_text_height;
+
+#endif	/* SED156X_H */
diff --git a/qemu/roms/u-boot/include/serial.h b/qemu/roms/u-boot/include/serial.h
new file mode 100644
index 000000000..d232d470a
--- /dev/null
+++ b/qemu/roms/u-boot/include/serial.h
@@ -0,0 +1,75 @@
+#ifndef __SERIAL_H__
+#define __SERIAL_H__
+
+#include <post.h>
+
+struct serial_device {
+	/* enough bytes to match alignment of following func pointer */
+	char	name[16];
+
+	int	(*start)(void);
+	int	(*stop)(void);
+	void	(*setbrg)(void);
+	int	(*getc)(void);
+	int	(*tstc)(void);
+	void	(*putc)(const char c);
+	void	(*puts)(const char *s);
+#if CONFIG_POST & CONFIG_SYS_POST_UART
+	void	(*loop)(int);
+#endif
+	struct serial_device	*next;
+};
+
+void default_serial_puts(const char *s);
+
+extern struct serial_device serial_smc_device;
+extern struct serial_device serial_scc_device;
+extern struct serial_device *default_serial_console(void);
+
+#if	defined(CONFIG_405GP) || \
+	defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
+	defined(CONFIG_405EX) || defined(CONFIG_440) || \
+	defined(CONFIG_MB86R0x) || defined(CONFIG_MPC5xxx) || \
+	defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \
+	defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) || \
+	defined(CONFIG_TEGRA) || defined(CONFIG_SYS_COREBOOT) || \
+	defined(CONFIG_MICROBLAZE)
+extern struct serial_device serial0_device;
+extern struct serial_device serial1_device;
+#endif
+
+extern struct serial_device eserial1_device;
+extern struct serial_device eserial2_device;
+
+extern void serial_register(struct serial_device *);
+extern void serial_initialize(void);
+extern void serial_stdio_init(void);
+extern int serial_assign(const char *name);
+extern void serial_reinit_all(void);
+
+/* For usbtty */
+#ifdef CONFIG_USB_TTY
+
+extern int usbtty_getc(void);
+extern void usbtty_putc(const char c);
+extern void usbtty_puts(const char *str);
+extern int usbtty_tstc(void);
+
+#else
+
+/* stubs */
+#define usbtty_getc() 0
+#define usbtty_putc(a)
+#define usbtty_puts(a)
+#define usbtty_tstc() 0
+
+#endif /* CONFIG_USB_TTY */
+
+#if defined(CONFIG_MPC512X)
+extern struct stdio_dev *open_port(int num, int baudrate);
+extern int close_port(int num);
+extern int write_port(struct stdio_dev *port, char *buf);
+extern int read_port(struct stdio_dev *port, char *buf, int size);
+#endif
+
+#endif
diff --git a/qemu/roms/u-boot/include/sh_pfc.h b/qemu/roms/u-boot/include/sh_pfc.h
new file mode 100644
index 000000000..7f6548f06
--- /dev/null
+++ b/qemu/roms/u-boot/include/sh_pfc.h
@@ -0,0 +1,192 @@
+/*
+ * SuperH Pin Function Controller Support
+ * Copy from Linux kernel. (include/linux/sh_pfc.h)
+ *
+ * Copyright (c) 2008 Magnus Damm
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __SH_PFC_H
+#define __SH_PFC_H
+
+typedef unsigned short pinmux_enum_t;
+typedef unsigned short pinmux_flag_t;
+
+#define PINMUX_TYPE_NONE            0
+#define PINMUX_TYPE_FUNCTION        1
+#define PINMUX_TYPE_GPIO            2
+#define PINMUX_TYPE_OUTPUT          3
+#define PINMUX_TYPE_INPUT           4
+#define PINMUX_TYPE_INPUT_PULLUP    5
+#define PINMUX_TYPE_INPUT_PULLDOWN  6
+
+#define PINMUX_FLAG_TYPE            (0x7)
+#define PINMUX_FLAG_WANT_PULLUP     (1 << 3)
+#define PINMUX_FLAG_WANT_PULLDOWN   (1 << 4)
+
+#define PINMUX_FLAG_DBIT_SHIFT      5
+#define PINMUX_FLAG_DBIT            (0x1f << PINMUX_FLAG_DBIT_SHIFT)
+#define PINMUX_FLAG_DREG_SHIFT      10
+#define PINMUX_FLAG_DREG            (0x3f << PINMUX_FLAG_DREG_SHIFT)
+
+struct pinmux_gpio {
+	pinmux_enum_t enum_id;
+	pinmux_flag_t flags;
+};
+
+#define PINMUX_GPIO(gpio, data_or_mark)[gpio] = { data_or_mark }
+#define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0
+
+struct pinmux_cfg_reg {
+	unsigned long reg, reg_width, field_width;
+	unsigned long *cnt;
+	pinmux_enum_t *enum_ids;
+	unsigned long *var_field_width;
+};
+
+#define PINMUX_CFG_REG(name, r, r_width, f_width) \
+	.reg = r, .reg_width = r_width, .field_width = f_width,		\
+	.cnt = (unsigned long [r_width / f_width]) {}, \
+	.enum_ids = (pinmux_enum_t [(r_width / f_width) * (1 << f_width)])
+
+#define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
+	.reg = r, .reg_width = r_width,	\
+	.cnt = (unsigned long [r_width]) {}, \
+	.var_field_width = (unsigned long [r_width]) { var_fw0, var_fwn, 0 }, \
+	.enum_ids = (pinmux_enum_t [])
+
+struct pinmux_data_reg {
+	unsigned long reg, reg_width, reg_shadow;
+	pinmux_enum_t *enum_ids;
+	void *mapped_reg;
+};
+
+#define PINMUX_DATA_REG(name, r, r_width) \
+	.reg = r, .reg_width = r_width,	\
+	.enum_ids = (pinmux_enum_t [r_width]) \
+
+struct pinmux_irq {
+	int irq;
+	pinmux_enum_t *enum_ids;
+};
+
+#define PINMUX_IRQ(irq_nr, ids...)			   \
+	{ .irq = irq_nr, .enum_ids = (pinmux_enum_t []) { ids, 0 } }	\
+
+struct pinmux_range {
+	pinmux_enum_t begin;
+	pinmux_enum_t end;
+	pinmux_enum_t force;
+};
+
+struct pinmux_info {
+	char *name;
+	pinmux_enum_t reserved_id;
+	struct pinmux_range data;
+	struct pinmux_range input;
+	struct pinmux_range input_pd;
+	struct pinmux_range input_pu;
+	struct pinmux_range output;
+	struct pinmux_range mark;
+	struct pinmux_range function;
+
+	unsigned first_gpio, last_gpio;
+
+	struct pinmux_gpio *gpios;
+	struct pinmux_cfg_reg *cfg_regs;
+	struct pinmux_data_reg *data_regs;
+
+	pinmux_enum_t *gpio_data;
+	unsigned int gpio_data_size;
+
+	struct pinmux_irq *gpio_irq;
+	unsigned int gpio_irq_size;
+
+	struct resource *resource;
+	unsigned int num_resources;
+	unsigned long unlock_reg;
+};
+
+int register_pinmux(struct pinmux_info *pip);
+int unregister_pinmux(struct pinmux_info *pip);
+
+/* helper macro for port */
+#define PORT_1(fn, pfx, sfx) fn(pfx, sfx)
+
+#define PORT_10(fn, pfx, sfx) \
+	PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx),	\
+	PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx),	\
+	PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx),	\
+	PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx),	\
+	PORT_1(fn, pfx##8, sfx), PORT_1(fn, pfx##9, sfx)
+
+#define PORT_90(fn, pfx, sfx) \
+	PORT_10(fn, pfx##1, sfx), PORT_10(fn, pfx##2, sfx),	\
+	PORT_10(fn, pfx##3, sfx), PORT_10(fn, pfx##4, sfx),	\
+	PORT_10(fn, pfx##5, sfx), PORT_10(fn, pfx##6, sfx),	\
+	PORT_10(fn, pfx##7, sfx), PORT_10(fn, pfx##8, sfx),	\
+	PORT_10(fn, pfx##9, sfx)
+
+#define _PORT_ALL(pfx, sfx) pfx##_##sfx
+#define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA)
+#define PORT_ALL(str)	CPU_ALL_PORT(_PORT_ALL, PORT, str)
+#define GPIO_PORT_ALL()	CPU_ALL_PORT(_GPIO_PORT, , unused)
+#define GPIO_FN(str) PINMUX_GPIO(GPIO_FN_##str, str##_MARK)
+
+/* helper macro for pinmux_enum_t */
+#define PORT_DATA_I(nr)	\
+	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_IN)
+
+#define PORT_DATA_I_PD(nr)	\
+	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0,	\
+		    PORT##nr##_IN, PORT##nr##_IN_PD)
+
+#define PORT_DATA_I_PU(nr)	\
+	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0,	\
+		    PORT##nr##_IN, PORT##nr##_IN_PU)
+
+#define PORT_DATA_I_PU_PD(nr)	\
+	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0,			\
+		    PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU)
+
+#define PORT_DATA_O(nr)		\
+	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT)
+
+#define PORT_DATA_IO(nr)	\
+	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT,	\
+		    PORT##nr##_IN)
+
+#define PORT_DATA_IO_PD(nr)	\
+	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT,	\
+		    PORT##nr##_IN, PORT##nr##_IN_PD)
+
+#define PORT_DATA_IO_PU(nr)	\
+	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT,	\
+		    PORT##nr##_IN, PORT##nr##_IN_PU)
+
+#define PORT_DATA_IO_PU_PD(nr)	\
+	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT,	\
+		    PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU)
+
+/* helper macro for top 4 bits in PORTnCR */
+#define _PCRH(in, in_pd, in_pu, out)	\
+	0, (out), (in), 0,		\
+	0, 0, 0, 0,			\
+	0, 0, (in_pd), 0,		\
+	0, 0, (in_pu), 0
+
+#define PORTCR(nr, reg)							\
+	{								\
+		PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) {		\
+			_PCRH(PORT##nr##_IN, PORT##nr##_IN_PD,		\
+			      PORT##nr##_IN_PU, PORT##nr##_OUT),	\
+				PORT##nr##_FN0, PORT##nr##_FN1,		\
+				PORT##nr##_FN2, PORT##nr##_FN3,		\
+				PORT##nr##_FN4, PORT##nr##_FN5,		\
+				PORT##nr##_FN6, PORT##nr##_FN7 }	\
+	}
+
+#endif /* __SH_PFC_H */
diff --git a/qemu/roms/u-boot/include/sh_tmu.h b/qemu/roms/u-boot/include/sh_tmu.h
new file mode 100644
index 000000000..61afc7136
--- /dev/null
+++ b/qemu/roms/u-boot/include/sh_tmu.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (C) 2012  Renesas Solutions Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __SH_TMU_H
+#define __SH_TMU_H
+
+#include <asm/types.h>
+
+#if defined(CONFIG_SH3)
+struct tmu_regs {
+	u8	tocr;
+	u8	reserved0;
+	u8	tstr;
+	u8	reserved1;
+	u32	tcor0;
+	u32	tcnt0;
+	u16	tcr0;
+	u16	reserved2;
+	u32	tcor1;
+	u32	tcnt1;
+	u16	tcr1;
+	u16	reserved3;
+	u32	tcor2;
+	u32	tcnt2;
+	u16	tcr2;
+	u16	reserved4;
+	u32	tcpr2;
+};
+#endif /* CONFIG_SH3 */
+
+#if defined(CONFIG_SH4) || defined(CONFIG_RMOBILE)
+struct tmu_regs {
+	u32 reserved;
+	u8  tstr;
+	u8  reserved2[3];
+	u32 tcor0;
+	u32 tcnt0;
+	u16 tcr0;
+	u16 reserved3;
+	u32 tcor1;
+	u32 tcnt1;
+	u16 tcr1;
+	u16 reserved4;
+	u32 tcor2;
+	u32 tcnt2;
+	u16 tcr2;
+	u16 reserved5;
+};
+#endif /* CONFIG_SH4 */
+
+static inline unsigned long get_tmu0_clk_rate(void)
+{
+	return CONFIG_SH_TMU_CLK_FREQ;
+}
+
+#endif	/* __SH_TMU_H */
diff --git a/qemu/roms/u-boot/include/sha1.h b/qemu/roms/u-boot/include/sha1.h
new file mode 100644
index 000000000..da09dab97
--- /dev/null
+++ b/qemu/roms/u-boot/include/sha1.h
@@ -0,0 +1,118 @@
+/**
+ * \file sha1.h
+ * based from http://xyssl.org/code/source/sha1/
+ *  FIPS-180-1 compliant SHA-1 implementation
+ *
+ *  Copyright (C) 2003-2006  Christophe Devine
+ *
+ *  This library is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU Lesser General Public
+ *  License, version 2.1 as published by the Free Software Foundation.
+ *
+ *  This library is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ *  Lesser General Public License for more details.
+ *
+ *  You should have received a copy of the GNU Lesser General Public
+ *  License along with this library; if not, write to the Free Software
+ *  Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ *  MA	02110-1301  USA
+ */
+/*
+ *  The SHA-1 standard was published by NIST in 1993.
+ *
+ *  http://www.itl.nist.gov/fipspubs/fip180-1.htm
+ */
+#ifndef _SHA1_H
+#define _SHA1_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define SHA1_SUM_POS	-0x20
+#define SHA1_SUM_LEN	20
+
+/**
+ * \brief	   SHA-1 context structure
+ */
+typedef struct
+{
+    unsigned long total[2];	/*!< number of bytes processed	*/
+    unsigned long state[5];	/*!< intermediate digest state	*/
+    unsigned char buffer[64];	/*!< data block being processed */
+}
+sha1_context;
+
+/**
+ * \brief	   SHA-1 context setup
+ *
+ * \param ctx	   SHA-1 context to be initialized
+ */
+void sha1_starts( sha1_context *ctx );
+
+/**
+ * \brief	   SHA-1 process buffer
+ *
+ * \param ctx	   SHA-1 context
+ * \param input    buffer holding the  data
+ * \param ilen	   length of the input data
+ */
+void sha1_update(sha1_context *ctx, const unsigned char *input,
+		 unsigned int ilen);
+
+/**
+ * \brief	   SHA-1 final digest
+ *
+ * \param ctx	   SHA-1 context
+ * \param output   SHA-1 checksum result
+ */
+void sha1_finish( sha1_context *ctx, unsigned char output[20] );
+
+/**
+ * \brief	   Output = SHA-1( input buffer )
+ *
+ * \param input    buffer holding the  data
+ * \param ilen	   length of the input data
+ * \param output   SHA-1 checksum result
+ */
+void sha1_csum(const unsigned char *input, unsigned int ilen,
+		unsigned char *output);
+
+/**
+ * \brief	   Output = SHA-1( input buffer ), with watchdog triggering
+ *
+ * \param input    buffer holding the  data
+ * \param ilen	   length of the input data
+ * \param output   SHA-1 checksum result
+ * \param chunk_sz watchdog triggering period (in bytes of input processed)
+ */
+void sha1_csum_wd(const unsigned char *input, unsigned int ilen,
+		unsigned char *output, unsigned int chunk_sz);
+
+/**
+ * \brief	   Output = HMAC-SHA-1( input buffer, hmac key )
+ *
+ * \param key	   HMAC secret key
+ * \param keylen   length of the HMAC key
+ * \param input    buffer holding the  data
+ * \param ilen	   length of the input data
+ * \param output   HMAC-SHA-1 result
+ */
+void sha1_hmac(const unsigned char *key, int keylen,
+		const unsigned char *input, unsigned int ilen,
+		unsigned char *output);
+
+/**
+ * \brief	   Checkup routine
+ *
+ * \return	   0 if successful, or 1 if the test failed
+ */
+int sha1_self_test( void );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* sha1.h */
diff --git a/qemu/roms/u-boot/include/sha256.h b/qemu/roms/u-boot/include/sha256.h
new file mode 100644
index 000000000..beadab35f
--- /dev/null
+++ b/qemu/roms/u-boot/include/sha256.h
@@ -0,0 +1,22 @@
+#ifndef _SHA256_H
+#define _SHA256_H
+
+#define SHA256_SUM_LEN	32
+
+/* Reset watchdog each time we process this many bytes */
+#define CHUNKSZ_SHA256	(64 * 1024)
+
+typedef struct {
+	uint32_t total[2];
+	uint32_t state[8];
+	uint8_t buffer[64];
+} sha256_context;
+
+void sha256_starts(sha256_context * ctx);
+void sha256_update(sha256_context *ctx, const uint8_t *input, uint32_t length);
+void sha256_finish(sha256_context * ctx, uint8_t digest[SHA256_SUM_LEN]);
+
+void sha256_csum_wd(const unsigned char *input, unsigned int ilen,
+		unsigned char *output, unsigned int chunk_sz);
+
+#endif /* _SHA256_H */
diff --git a/qemu/roms/u-boot/include/sja1000.h b/qemu/roms/u-boot/include/sja1000.h
new file mode 100644
index 000000000..07cd9e371
--- /dev/null
+++ b/qemu/roms/u-boot/include/sja1000.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright 2009, Matthias Fuchs <matthias.fuchs@esd.eu>
+ *
+ * SJA1000 register layout for basic CAN mode
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SJA1000_H_
+#define _SJA1000_H_
+
+/*
+ * SJA1000 register layout in basic can mode
+ */
+struct sja1000_basic_s {
+	u8 cr;
+	u8 cmr;
+	u8 sr;
+	u8 ir;
+	u8 ac;
+	u8 am;
+	u8 btr0;
+	u8 btr1;
+	u8 oc;
+	u8 txb[10];
+	u8 rxb[10];
+	u8 unused;
+	u8 cdr;
+};
+
+/* control register */
+#define CR_RR		0x01
+
+/* output control register */
+#define OC_MODE0	0x01
+#define OC_MODE1	0x02
+#define OC_POL0		0x04
+#define OC_TN0		0x08
+#define OC_TP0		0x10
+#define OC_POL1		0x20
+#define OC_TN1		0x40
+#define OC_TP1		0x80
+
+#endif
diff --git a/qemu/roms/u-boot/include/slre.h b/qemu/roms/u-boot/include/slre.h
new file mode 100644
index 000000000..4b41a4b27
--- /dev/null
+++ b/qemu/roms/u-boot/include/slre.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2004-2005 Sergey Lyubka <valenok@gmail.com>
+ * All rights reserved
+ *
+ * "THE BEER-WARE LICENSE" (Revision 42):
+ * Sergey Lyubka wrote this file.  As long as you retain this notice you
+ * can do whatever you want with this stuff. If we meet some day, and you think
+ * this stuff is worth it, you can buy me a beer in return.
+ */
+
+/*
+ * Downloaded Sat Nov  5 17:42:08 CET 2011 at
+ * http://slre.sourceforge.net/1.0/slre.h
+ */
+
+/*
+ * This is a regular expression library that implements a subset of Perl RE.
+ * Please refer to http://slre.sourceforge.net for detailed description.
+ *
+ * Usage example (parsing HTTP request):
+ *
+ * struct slre	slre;
+ * struct cap	captures[4 + 1];  // Number of braket pairs + 1
+ * ...
+ *
+ * slre_compile(&slre,"^(GET|POST) (\S+) HTTP/(\S+?)\r\n");
+ *
+ * if (slre_match(&slre, buf, len, captures)) {
+ *	printf("Request line length: %d\n", captures[0].len);
+ *	printf("Method: %.*s\n", captures[1].len, captures[1].ptr);
+ *	printf("URI: %.*s\n", captures[2].len, captures[2].ptr);
+ * }
+ *
+ * Supported syntax:
+ *	^		Match beginning of a buffer
+ *	$		Match end of a buffer
+ *	()		Grouping and substring capturing
+ *	[...]		Match any character from set
+ *	[^...]		Match any character but ones from set
+ *	\s		Match whitespace
+ *	\S		Match non-whitespace
+ *	\d		Match decimal digit
+ *	\r		Match carriage return
+ *	\n		Match newline
+ *	+		Match one or more times (greedy)
+ *	+?		Match one or more times (non-greedy)
+ *	*		Match zero or more times (greedy)
+ *	*?		Match zero or more times (non-greedy)
+ *	?		Match zero or once
+ *	\xDD		Match byte with hex value 0xDD
+ *	\meta		Match one of the meta character: ^$().[*+?\
+ */
+
+#ifndef SLRE_HEADER_DEFINED
+#define	SLRE_HEADER_DEFINED
+
+/*
+ * Compiled regular expression
+ */
+struct slre {
+	unsigned char	code[256];
+	unsigned char	data[256];
+	int		code_size;
+	int		data_size;
+	int		num_caps;	/* Number of bracket pairs	*/
+	int		anchored;	/* Must match from string start	*/
+	const char	*err_str;	/* Error string			*/
+};
+
+/*
+ * Captured substring
+ */
+struct cap {
+	const char	*ptr;		/* Pointer to the substring	*/
+	int		len;		/* Substring length		*/
+};
+
+/*
+ * Compile regular expression. If success, 1 is returned.
+ * If error, 0 is returned and slre.err_str points to the error message.
+ */
+int slre_compile(struct slre *, const char *re);
+
+/*
+ * Return 1 if match, 0 if no match.
+ * If `captured_substrings' array is not NULL, then it is filled with the
+ * values of captured substrings. captured_substrings[0] element is always
+ * a full matched substring. The round bracket captures start from
+ * captured_substrings[1].
+ * It is assumed that the size of captured_substrings array is enough to
+ * hold all captures. The caller function must make sure it is! So, the
+ * array_size = number_of_round_bracket_pairs + 1
+ */
+int slre_match(const struct slre *, const char *buf, int buf_len,
+	struct cap *captured_substrings);
+
+#ifdef SLRE_TEST
+void slre_dump(const struct slre *r, FILE *fp);
+#endif /* SLRE_TEST */
+#endif /* SLRE_HEADER_DEFINED */
diff --git a/qemu/roms/u-boot/include/sm501.h b/qemu/roms/u-boot/include/sm501.h
new file mode 100644
index 000000000..34ce350e6
--- /dev/null
+++ b/qemu/roms/u-boot/include/sm501.h
@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2002
+ * Stäubli Faverges - <www.staubli.com>
+ * Pierre AUBERT  p.aubert@staubli.com
+ *
+ * (C) Copyright 2005
+ * Martin Krause TQ-Systems GmbH martin.krause@tqs.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Basic video support for SMI SM501 "Voyager" graphic controller
+ */
+
+#ifndef _SM501_H_
+#define _SM501_H_
+
+#define PCI_VENDOR_SM		0x126f
+#define PCI_DEVICE_SM501	0x0501
+
+typedef struct {
+	unsigned int Index;
+	unsigned int Value;
+} SMI_REGS;
+
+/* Board specific functions                                                  */
+unsigned int board_video_init (void);
+void board_validate_screen (unsigned int base);
+const SMI_REGS *board_get_regs (void);
+int board_get_width (void);
+int board_get_height (void);
+unsigned int board_video_get_fb (void);
+
+#endif /* _SM501_H_ */
diff --git a/qemu/roms/u-boot/include/sound.h b/qemu/roms/u-boot/include/sound.h
new file mode 100644
index 000000000..155e1b40e
--- /dev/null
+++ b/qemu/roms/u-boot/include/sound.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * R. Chandrasekar < rcsekar@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __SOUND_H__
+#define __SOUND_H__
+
+/* sound codec enum */
+enum en_sound_codec {
+	CODEC_WM_8994,
+	CODEC_WM_8995,
+	CODEC_MAX_98095,
+	CODEC_MAX
+};
+
+/* sound codec enum */
+enum sound_compat {
+	AUDIO_COMPAT_SPI,
+	AUDIO_COMPAT_I2C,
+};
+
+/* Codec information structure to store the info from device tree */
+struct sound_codec_info {
+	int i2c_bus;
+	int i2c_dev_addr;
+	enum en_sound_codec codec_type;
+};
+
+/*
+ * Generates square wave sound data for 1 second
+ *
+ * @param data          data buffer pointer
+ * @param size          size of the buffer
+ * @param freq          frequency of the wave
+ */
+void sound_create_square_wave(unsigned short *data, int size, uint32_t freq);
+
+/*
+ * Initialises audio sub system
+ * @param blob	Pointer of device tree node or NULL if none.
+ * @return	int value 0 for success, -1 for error
+ */
+int sound_init(const void *blob);
+
+/*
+ * plays the pcm data buffer in pcm_data.h through i2s1 to make the
+ * sine wave sound
+ *
+ * @return	int 0 for success, -1 for error
+ */
+int sound_play(uint32_t msec, uint32_t frequency);
+
+#endif  /* __SOUND__H__ */
diff --git a/qemu/roms/u-boot/include/spartan2.h b/qemu/roms/u-boot/include/spartan2.h
new file mode 100644
index 000000000..2aca954e7
--- /dev/null
+++ b/qemu/roms/u-boot/include/spartan2.h
@@ -0,0 +1,96 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SPARTAN2_H_
+#define _SPARTAN2_H_
+
+#include <xilinx.h>
+
+/* Slave Parallel Implementation function table */
+typedef struct {
+	xilinx_pre_fn	pre;
+	xilinx_pgm_fn	pgm;
+	xilinx_init_fn	init;
+	xilinx_err_fn	err;
+	xilinx_done_fn	done;
+	xilinx_clk_fn	clk;
+	xilinx_cs_fn	cs;
+	xilinx_wr_fn	wr;
+	xilinx_rdata_fn	rdata;
+	xilinx_wdata_fn	wdata;
+	xilinx_busy_fn	busy;
+	xilinx_abort_fn	abort;
+	xilinx_post_fn	post;
+} xilinx_spartan2_slave_parallel_fns;
+
+/* Slave Serial Implementation function table */
+typedef struct {
+	xilinx_pre_fn	pre;
+	xilinx_pgm_fn	pgm;
+	xilinx_clk_fn	clk;
+	xilinx_init_fn	init;
+	xilinx_done_fn	done;
+	xilinx_wr_fn	wr;
+	xilinx_post_fn	post;
+} xilinx_spartan2_slave_serial_fns;
+
+extern struct xilinx_fpga_op spartan2_op;
+
+/* Device Image Sizes
+ *********************************************************************/
+/* Spartan-II (2.5V) */
+#define XILINX_XC2S15_SIZE	197728/8
+#define XILINX_XC2S30_SIZE	336800/8
+#define XILINX_XC2S50_SIZE	559232/8
+#define XILINX_XC2S100_SIZE	781248/8
+#define XILINX_XC2S150_SIZE	1040128/8
+#define XILINX_XC2S200_SIZE	1335872/8
+
+/* Spartan-IIE (1.8V) */
+#define XILINX_XC2S50E_SIZE     630048/8
+#define XILINX_XC2S100E_SIZE    863840/8
+#define XILINX_XC2S150E_SIZE    1134496/8
+#define XILINX_XC2S200E_SIZE    1442016/8
+#define XILINX_XC2S300E_SIZE    1875648/8
+
+/* Descriptor Macros
+ *********************************************************************/
+/* Spartan-II devices */
+#define XILINX_XC2S15_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan2, iface, XILINX_XC2S15_SIZE, fn_table, cookie, &spartan2_op }
+
+#define XILINX_XC2S30_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan2, iface, XILINX_XC2S30_SIZE, fn_table, cookie, &spartan2_op }
+
+#define XILINX_XC2S50_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan2, iface, XILINX_XC2S50_SIZE, fn_table, cookie, &spartan2_op }
+
+#define XILINX_XC2S100_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan2, iface, XILINX_XC2S100_SIZE, fn_table, cookie, &spartan2_op }
+
+#define XILINX_XC2S150_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie, &spartan2_op }
+
+#define XILINX_XC2S200_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie, &spartan2_op }
+
+#define XILINX_XC2S50E_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie, &spartan2_op }
+
+#define XILINX_XC2S100E_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie, &spartan2_op }
+
+#define XILINX_XC2S150E_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie, &spartan2_op }
+
+#define XILINX_XC2S200E_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie, &spartan2_op }
+
+#define XILINX_XC2S300E_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie, &spartan2_op }
+
+#endif /* _SPARTAN2_H_ */
diff --git a/qemu/roms/u-boot/include/spartan3.h b/qemu/roms/u-boot/include/spartan3.h
new file mode 100644
index 000000000..d6d67a6e5
--- /dev/null
+++ b/qemu/roms/u-boot/include/spartan3.h
@@ -0,0 +1,118 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SPARTAN3_H_
+#define _SPARTAN3_H_
+
+#include <xilinx.h>
+
+/* Slave Parallel Implementation function table */
+typedef struct {
+	xilinx_pre_fn	pre;
+	xilinx_pgm_fn	pgm;
+	xilinx_init_fn	init;
+	xilinx_err_fn	err;
+	xilinx_done_fn	done;
+	xilinx_clk_fn	clk;
+	xilinx_cs_fn	cs;
+	xilinx_wr_fn	wr;
+	xilinx_rdata_fn	rdata;
+	xilinx_wdata_fn	wdata;
+	xilinx_busy_fn	busy;
+	xilinx_abort_fn	abort;
+	xilinx_post_fn	post;
+} xilinx_spartan3_slave_parallel_fns;
+
+/* Slave Serial Implementation function table */
+typedef struct {
+	xilinx_pre_fn	pre;
+	xilinx_pgm_fn	pgm;
+	xilinx_clk_fn	clk;
+	xilinx_init_fn	init;
+	xilinx_done_fn	done;
+	xilinx_wr_fn	wr;
+	xilinx_post_fn	post;
+	xilinx_bwr_fn	bwr; /* block write function */
+	xilinx_abort_fn abort;
+} xilinx_spartan3_slave_serial_fns;
+
+extern struct xilinx_fpga_op spartan3_op;
+
+/* Device Image Sizes
+ *********************************************************************/
+/* Spartan-III (1.2V) */
+#define XILINX_XC3S50_SIZE	439264/8
+#define XILINX_XC3S200_SIZE	1047616/8
+#define XILINX_XC3S400_SIZE	1699136/8
+#define XILINX_XC3S1000_SIZE	3223488/8
+#define XILINX_XC3S1500_SIZE	5214784/8
+#define XILINX_XC3S2000_SIZE	7673024/8
+#define XILINX_XC3S4000_SIZE	11316864/8
+#define XILINX_XC3S5000_SIZE	13271936/8
+
+/* Spartan-3E (v3.4) */
+#define	XILINX_XC3S100E_SIZE	581344/8
+#define	XILINX_XC3S250E_SIZE	1353728/8
+#define	XILINX_XC3S500E_SIZE	2270208/8
+#define	XILINX_XC3S1200E_SIZE	3841184/8
+#define	XILINX_XC3S1600E_SIZE	5969696/8
+
+/*
+ * Spartan-6 : the Spartan-6 family can be programmed
+ * exactly as the Spartan-3
+ */
+#define XILINK_XC6SLX4_SIZE	(3713568/8)
+
+/* Descriptor Macros
+ *********************************************************************/
+/* Spartan-III devices */
+#define XILINX_XC3S50_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie, &spartan3_op }
+
+#define XILINX_XC3S200_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan3, iface, XILINX_XC3S200_SIZE, fn_table, cookie, &spartan3_op }
+
+#define XILINX_XC3S400_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan3, iface, XILINX_XC3S400_SIZE, fn_table, cookie, &spartan3_op }
+
+#define XILINX_XC3S1000_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan3, iface, XILINX_XC3S1000_SIZE, fn_table, cookie, &spartan3_op }
+
+#define XILINX_XC3S1500_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie, &spartan3_op }
+
+#define XILINX_XC3S2000_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan3, iface, XILINX_XC3S2000_SIZE, fn_table, cookie, &spartan3_op }
+
+#define XILINX_XC3S4000_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan3, iface, XILINX_XC3S4000_SIZE, fn_table, cookie, &spartan3_op }
+
+#define XILINX_XC3S5000_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan3, iface, XILINX_XC3S5000_SIZE, fn_table, cookie, &spartan3_op }
+
+/* Spartan-3E devices */
+#define XILINX_XC3S100E_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie, &spartan3_op }
+
+#define XILINX_XC3S250E_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie, &spartan3_op }
+
+#define XILINX_XC3S500E_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie, &spartan3_op }
+
+#define XILINX_XC3S1200E_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan3, iface, XILINX_XC3S1200E_SIZE, fn_table, cookie, \
+	&spartan3_op }
+
+#define XILINX_XC3S1600E_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan3, iface, XILINX_XC3S1600E_SIZE, fn_table, cookie, \
+	&spartan3_op }
+
+#define XILINX_XC6SLX4_DESC(iface, fn_table, cookie) \
+{ xilinx_spartan3, iface, XILINK_XC6SLX4_SIZE, fn_table, cookie, &spartan3_op }
+
+#endif /* _SPARTAN3_H_ */
diff --git a/qemu/roms/u-boot/include/spd.h b/qemu/roms/u-boot/include/spd.h
new file mode 100644
index 000000000..52e42314a
--- /dev/null
+++ b/qemu/roms/u-boot/include/spd.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (C) 2003 Arabella Software Ltd.
+ * Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * Serial Presence Detect (SPD) EEPROM format according to the
+ * Intel's PC SDRAM Serial Presence Detect (SPD) Specification,
+ * revision 1.2B, November 1999
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SPD_H_
+#define _SPD_H_
+
+typedef struct spd_eeprom_s {
+	unsigned char info_size;   /*  0 # bytes written into serial memory */
+	unsigned char chip_size;   /*  1 Total # bytes of SPD memory device */
+	unsigned char mem_type;    /*  2 Fundamental memory type */
+	unsigned char nrow_addr;   /*  3 # of Row Addresses on this assembly */
+	unsigned char ncol_addr;   /*  4 # of Column Addrs on this assembly */
+	unsigned char nrows;       /*  5 # of Module Rows on this assembly */
+	unsigned char dataw_lsb;   /*  6 Data Width of this assembly */
+	unsigned char dataw_msb;   /*  7 ... Data Width continuation */
+	unsigned char voltage;     /*  8 Voltage intf std of this assembly */
+	unsigned char clk_cycle;   /*  9 SDRAM Cycle time at CL=X */
+	unsigned char clk_access;  /* 10 SDRAM Access from Clock at CL=X */
+	unsigned char config;      /* 11 DIMM Configuration type */
+	unsigned char refresh;     /* 12 Refresh Rate/Type */
+	unsigned char primw;       /* 13 Primary SDRAM Width */
+	unsigned char ecw;         /* 14 Error Checking SDRAM width */
+	unsigned char min_delay;   /* 15 for Back to Back Random Address */
+	unsigned char burstl;      /* 16 Burst Lengths Supported */
+	unsigned char nbanks;      /* 17 # of Banks on Each SDRAM Device */
+	unsigned char cas_lat;     /* 18 CAS# Latencies Supported */
+	unsigned char cs_lat;      /* 19 CS# Latency */
+	unsigned char write_lat;   /* 20 Write Latency (aka Write Recovery) */
+	unsigned char mod_attr;    /* 21 SDRAM Module Attributes */
+	unsigned char dev_attr;    /* 22 SDRAM Device Attributes */
+	unsigned char clk_cycle2;  /* 23 Min SDRAM Cycle time at CL=X-1 */
+	unsigned char clk_access2; /* 24 SDRAM Access from Clock at CL=X-1 */
+	unsigned char clk_cycle3;  /* 25 Min SDRAM Cycle time at CL=X-2 */
+	unsigned char clk_access3; /* 26 Max Access from Clock at CL=X-2 */
+	unsigned char trp;         /* 27 Min Row Precharge Time (tRP)*/
+	unsigned char trrd;        /* 28 Min Row Active to Row Active (tRRD) */
+	unsigned char trcd;        /* 29 Min RAS to CAS Delay (tRCD) */
+	unsigned char tras;        /* 30 Minimum RAS Pulse Width (tRAS) */
+	unsigned char row_dens;    /* 31 Density of each row on module */
+	unsigned char ca_setup;    /* 32 Cmd + Addr signal input setup time */
+	unsigned char ca_hold;     /* 33 Cmd and Addr signal input hold time */
+	unsigned char data_setup;  /* 34 Data signal input setup time */
+	unsigned char data_hold;   /* 35 Data signal input hold time */
+	unsigned char twr;         /* 36 Write Recovery time tWR */
+	unsigned char twtr;        /* 37 Int write to read delay tWTR */
+	unsigned char trtp;        /* 38 Int read to precharge delay tRTP */
+	unsigned char mem_probe;   /* 39 Mem analysis probe characteristics */
+	unsigned char trctrfc_ext; /* 40 Extensions to trc and trfc */
+	unsigned char trc;         /* 41 Min Active to Auto refresh time tRC */
+	unsigned char trfc;        /* 42 Min Auto to Active period tRFC */
+	unsigned char tckmax;      /* 43 Max device cycle time tCKmax */
+	unsigned char tdqsq;       /* 44 Max DQS to DQ skew */
+	unsigned char tqhs;        /* 45 Max Read DataHold skew tQHS */
+	unsigned char pll_relock;  /* 46 PLL Relock time */
+	unsigned char res[15];     /* 47-xx IDD in SPD and Reserved space */
+	unsigned char spd_rev;     /* 62 SPD Data Revision Code */
+	unsigned char cksum;       /* 63 Checksum for bytes 0-62 */
+	unsigned char mid[8];      /* 64 Mfr's JEDEC ID code per JEP-108E */
+	unsigned char mloc;        /* 72 Manufacturing Location */
+	unsigned char mpart[18];   /* 73 Manufacturer's Part Number */
+	unsigned char rev[2];      /* 91 Revision Code */
+	unsigned char mdate[2];    /* 93 Manufacturing Date */
+	unsigned char sernum[4];   /* 95 Assembly Serial Number */
+	unsigned char mspec[27];   /* 99 Manufacturer Specific Data */
+
+	/*
+	 * Open for Customer Use starting with byte 128.
+	 */
+	unsigned char freq;        /* 128 Intel spec: frequency */
+	unsigned char intel_cas;   /* 129 Intel spec: CAS# Latency support */
+} spd_eeprom_t;
+
+
+/*
+ * Byte 2 Fundamental Memory Types.
+ */
+#define SPD_MEMTYPE_FPM		(0x01)
+#define SPD_MEMTYPE_EDO		(0x02)
+#define SPD_MEMTYPE_PIPE_NIBBLE	(0x03)
+#define SPD_MEMTYPE_SDRAM	(0x04)
+#define SPD_MEMTYPE_ROM		(0x05)
+#define SPD_MEMTYPE_SGRAM	(0x06)
+#define SPD_MEMTYPE_DDR		(0x07)
+#define SPD_MEMTYPE_DDR2	(0x08)
+
+#endif /* _SPD_H_ */
diff --git a/qemu/roms/u-boot/include/spd_sdram.h b/qemu/roms/u-boot/include/spd_sdram.h
new file mode 100644
index 000000000..a2be96c1a
--- /dev/null
+++ b/qemu/roms/u-boot/include/spd_sdram.h
@@ -0,0 +1,6 @@
+#ifndef _SPD_SDRAM_H_
+#define _SPD_SDRAM_H_
+
+long int spd_sdram(void);
+
+#endif
diff --git a/qemu/roms/u-boot/include/spi.h b/qemu/roms/u-boot/include/spi.h
new file mode 100644
index 000000000..ffd66478b
--- /dev/null
+++ b/qemu/roms/u-boot/include/spi.h
@@ -0,0 +1,308 @@
+/*
+ * Common SPI Interface: Controller-specific definitions
+ *
+ * (C) Copyright 2001
+ * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SPI_H_
+#define _SPI_H_
+
+/* SPI mode flags */
+#define	SPI_CPHA	0x01			/* clock phase */
+#define	SPI_CPOL	0x02			/* clock polarity */
+#define	SPI_MODE_0	(0|0)			/* (original MicroWire) */
+#define	SPI_MODE_1	(0|SPI_CPHA)
+#define	SPI_MODE_2	(SPI_CPOL|0)
+#define	SPI_MODE_3	(SPI_CPOL|SPI_CPHA)
+#define	SPI_CS_HIGH	0x04			/* CS active high */
+#define	SPI_LSB_FIRST	0x08			/* per-word bits-on-wire */
+#define	SPI_3WIRE	0x10			/* SI/SO signals shared */
+#define	SPI_LOOP	0x20			/* loopback mode */
+#define	SPI_SLAVE	0x40			/* slave mode */
+#define	SPI_PREAMBLE	0x80			/* Skip preamble bytes */
+
+/* SPI transfer flags */
+#define SPI_XFER_BEGIN		0x01	/* Assert CS before transfer */
+#define SPI_XFER_END		0x02	/* Deassert CS after transfer */
+#define SPI_XFER_MMAP		0x08	/* Memory Mapped start */
+#define SPI_XFER_MMAP_END	0x10	/* Memory Mapped End */
+#define SPI_XFER_ONCE		(SPI_XFER_BEGIN | SPI_XFER_END)
+#define SPI_XFER_U_PAGE		(1 << 5)
+
+/* SPI TX operation modes */
+#define SPI_OPM_TX_QPP		1 << 0
+
+/* SPI RX operation modes */
+#define SPI_OPM_RX_AS		1 << 0
+#define SPI_OPM_RX_DOUT		1 << 1
+#define SPI_OPM_RX_DIO		1 << 2
+#define SPI_OPM_RX_QOF		1 << 3
+#define SPI_OPM_RX_QIOF		1 << 4
+#define SPI_OPM_RX_EXTN		SPI_OPM_RX_AS | SPI_OPM_RX_DOUT | \
+				SPI_OPM_RX_DIO | SPI_OPM_RX_QOF | \
+				SPI_OPM_RX_QIOF
+
+/* SPI bus connection options */
+#define SPI_CONN_DUAL_SHARED	1 << 0
+#define SPI_CONN_DUAL_SEPARATED	1 << 1
+
+/* Header byte that marks the start of the message */
+#define SPI_PREAMBLE_END_BYTE	0xec
+
+#define SPI_DEFAULT_WORDLEN 8
+
+/**
+ * struct spi_slave - Representation of a SPI slave
+ *
+ * Drivers are expected to extend this with controller-specific data.
+ *
+ * @bus:		ID of the bus that the slave is attached to.
+ * @cs:			ID of the chip select connected to the slave.
+ * @op_mode_rx:		SPI RX operation mode.
+ * @op_mode_tx:		SPI TX operation mode.
+ * @wordlen:		Size of SPI word in number of bits
+ * @max_write_size:	If non-zero, the maximum number of bytes which can
+ *			be written at once, excluding command bytes.
+ * @memory_map:		Address of read-only SPI flash access.
+ * @option:		Varies SPI bus options - separate, shared bus.
+ * @flags:		Indication of SPI flags.
+ */
+struct spi_slave {
+	unsigned int bus;
+	unsigned int cs;
+	u8 op_mode_rx;
+	u8 op_mode_tx;
+	unsigned int wordlen;
+	unsigned int max_write_size;
+	void *memory_map;
+	u8 option;
+	u8 flags;
+};
+
+/**
+ * Initialization, must be called once on start up.
+ *
+ * TODO: I don't think we really need this.
+ */
+void spi_init(void);
+
+/**
+ * spi_do_alloc_slave - Allocate a new SPI slave (internal)
+ *
+ * Allocate and zero all fields in the spi slave, and set the bus/chip
+ * select. Use the helper macro spi_alloc_slave() to call this.
+ *
+ * @offset:	Offset of struct spi_slave within slave structure.
+ * @size:	Size of slave structure.
+ * @bus:	Bus ID of the slave chip.
+ * @cs:		Chip select ID of the slave chip on the specified bus.
+ */
+void *spi_do_alloc_slave(int offset, int size, unsigned int bus,
+			 unsigned int cs);
+
+/**
+ * spi_alloc_slave - Allocate a new SPI slave
+ *
+ * Allocate and zero all fields in the spi slave, and set the bus/chip
+ * select.
+ *
+ * @_struct:	Name of structure to allocate (e.g. struct tegra_spi).
+ *		This structure must contain a member 'struct spi_slave *slave'.
+ * @bus:	Bus ID of the slave chip.
+ * @cs:		Chip select ID of the slave chip on the specified bus.
+ */
+#define spi_alloc_slave(_struct, bus, cs) \
+	spi_do_alloc_slave(offsetof(_struct, slave), \
+			    sizeof(_struct), bus, cs)
+
+/**
+ * spi_alloc_slave_base - Allocate a new SPI slave with no private data
+ *
+ * Allocate and zero all fields in the spi slave, and set the bus/chip
+ * select.
+ *
+ * @bus:	Bus ID of the slave chip.
+ * @cs:		Chip select ID of the slave chip on the specified bus.
+ */
+#define spi_alloc_slave_base(bus, cs) \
+	spi_do_alloc_slave(0, sizeof(struct spi_slave), bus, cs)
+
+/**
+ * Set up communications parameters for a SPI slave.
+ *
+ * This must be called once for each slave. Note that this function
+ * usually doesn't touch any actual hardware, it only initializes the
+ * contents of spi_slave so that the hardware can be easily
+ * initialized later.
+ *
+ * @bus:	Bus ID of the slave chip.
+ * @cs:		Chip select ID of the slave chip on the specified bus.
+ * @max_hz:	Maximum SCK rate in Hz.
+ * @mode:	Clock polarity, clock phase and other parameters.
+ *
+ * Returns: A spi_slave reference that can be used in subsequent SPI
+ * calls, or NULL if one or more of the parameters are not supported.
+ */
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+		unsigned int max_hz, unsigned int mode);
+
+/**
+ * Free any memory associated with a SPI slave.
+ *
+ * @slave:	The SPI slave
+ */
+void spi_free_slave(struct spi_slave *slave);
+
+/**
+ * Claim the bus and prepare it for communication with a given slave.
+ *
+ * This must be called before doing any transfers with a SPI slave. It
+ * will enable and initialize any SPI hardware as necessary, and make
+ * sure that the SCK line is in the correct idle state. It is not
+ * allowed to claim the same bus for several slaves without releasing
+ * the bus in between.
+ *
+ * @slave:	The SPI slave
+ *
+ * Returns: 0 if the bus was claimed successfully, or a negative value
+ * if it wasn't.
+ */
+int spi_claim_bus(struct spi_slave *slave);
+
+/**
+ * Release the SPI bus
+ *
+ * This must be called once for every call to spi_claim_bus() after
+ * all transfers have finished. It may disable any SPI hardware as
+ * appropriate.
+ *
+ * @slave:	The SPI slave
+ */
+void spi_release_bus(struct spi_slave *slave);
+
+/**
+ * Set the word length for SPI transactions
+ *
+ * Set the word length (number of bits per word) for SPI transactions.
+ *
+ * @slave:	The SPI slave
+ * @wordlen:	The number of bits in a word
+ *
+ * Returns: 0 on success, -1 on failure.
+ */
+int spi_set_wordlen(struct spi_slave *slave, unsigned int wordlen);
+
+/**
+ * SPI transfer
+ *
+ * This writes "bitlen" bits out the SPI MOSI port and simultaneously clocks
+ * "bitlen" bits in the SPI MISO port.  That's just the way SPI works.
+ *
+ * The source of the outgoing bits is the "dout" parameter and the
+ * destination of the input bits is the "din" parameter.  Note that "dout"
+ * and "din" can point to the same memory location, in which case the
+ * input data overwrites the output data (since both are buffered by
+ * temporary variables, this is OK).
+ *
+ * spi_xfer() interface:
+ * @slave:	The SPI slave which will be sending/receiving the data.
+ * @bitlen:	How many bits to write and read.
+ * @dout:	Pointer to a string of bits to send out.  The bits are
+ *		held in a byte array and are sent MSB first.
+ * @din:	Pointer to a string of bits that will be filled in.
+ * @flags:	A bitwise combination of SPI_XFER_* flags.
+ *
+ * Returns: 0 on success, not 0 on failure
+ */
+int  spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
+		void *din, unsigned long flags);
+
+/**
+ * Determine if a SPI chipselect is valid.
+ * This function is provided by the board if the low-level SPI driver
+ * needs it to determine if a given chipselect is actually valid.
+ *
+ * Returns: 1 if bus:cs identifies a valid chip on this board, 0
+ * otherwise.
+ */
+int  spi_cs_is_valid(unsigned int bus, unsigned int cs);
+
+/**
+ * Activate a SPI chipselect.
+ * This function is provided by the board code when using a driver
+ * that can't control its chipselects automatically (e.g.
+ * common/soft_spi.c). When called, it should activate the chip select
+ * to the device identified by "slave".
+ */
+void spi_cs_activate(struct spi_slave *slave);
+
+/**
+ * Deactivate a SPI chipselect.
+ * This function is provided by the board code when using a driver
+ * that can't control its chipselects automatically (e.g.
+ * common/soft_spi.c). When called, it should deactivate the chip
+ * select to the device identified by "slave".
+ */
+void spi_cs_deactivate(struct spi_slave *slave);
+
+/**
+ * Set transfer speed.
+ * This sets a new speed to be applied for next spi_xfer().
+ * @slave:	The SPI slave
+ * @hz:		The transfer speed
+ */
+void spi_set_speed(struct spi_slave *slave, uint hz);
+
+/**
+ * Write 8 bits, then read 8 bits.
+ * @slave:	The SPI slave we're communicating with
+ * @byte:	Byte to be written
+ *
+ * Returns: The value that was read, or a negative value on error.
+ *
+ * TODO: This function probably shouldn't be inlined.
+ */
+static inline int spi_w8r8(struct spi_slave *slave, unsigned char byte)
+{
+	unsigned char dout[2];
+	unsigned char din[2];
+	int ret;
+
+	dout[0] = byte;
+	dout[1] = 0;
+
+	ret = spi_xfer(slave, 16, dout, din, SPI_XFER_BEGIN | SPI_XFER_END);
+	return ret < 0 ? ret : din[1];
+}
+
+/**
+ * Set up a SPI slave for a particular device tree node
+ *
+ * This calls spi_setup_slave() with the correct bus number. Call
+ * spi_free_slave() to free it later.
+ *
+ * @param blob:		Device tree blob
+ * @param slave_node:	Slave node to use
+ * @param spi_node:	SPI peripheral node to use
+ * @return pointer to new spi_slave structure
+ */
+struct spi_slave *spi_setup_slave_fdt(const void *blob, int slave_node,
+				      int spi_node);
+
+/**
+ * spi_base_setup_slave_fdt() - helper function to set up a SPI slace
+ *
+ * This decodes SPI properties from the slave node to determine the
+ * chip select and SPI parameters.
+ *
+ * @blob:	Device tree blob
+ * @busnum:	Bus number to use
+ * @node:	Device tree node for the SPI bus
+ */
+struct spi_slave *spi_base_setup_slave_fdt(const void *blob, int busnum,
+					   int node);
+
+#endif	/* _SPI_H_ */
diff --git a/qemu/roms/u-boot/include/spi_flash.h b/qemu/roms/u-boot/include/spi_flash.h
new file mode 100644
index 000000000..2db53c74c
--- /dev/null
+++ b/qemu/roms/u-boot/include/spi_flash.h
@@ -0,0 +1,163 @@
+/*
+ * Common SPI flash Interface
+ *
+ * Copyright (C) 2008 Atmel Corporation
+ * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ */
+
+#ifndef _SPI_FLASH_H_
+#define _SPI_FLASH_H_
+
+#include <spi.h>
+#include <linux/types.h>
+#include <linux/compiler.h>
+
+/* sf param flags */
+#define SECT_4K		1 << 1
+#define SECT_32K	1 << 2
+#define E_FSR		1 << 3
+#define WR_QPP		1 << 4
+
+/* Enum list - Full read commands */
+enum spi_read_cmds {
+	ARRAY_SLOW = 1 << 0,
+	DUAL_OUTPUT_FAST = 1 << 1,
+	DUAL_IO_FAST = 1 << 2,
+	QUAD_OUTPUT_FAST = 1 << 3,
+	QUAD_IO_FAST = 1 << 4,
+};
+#define RD_EXTN		ARRAY_SLOW | DUAL_OUTPUT_FAST | DUAL_IO_FAST
+#define RD_FULL		RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST
+
+/* Dual SPI flash memories */
+enum spi_dual_flash {
+	SF_SINGLE_FLASH = 0,
+	SF_DUAL_STACKED_FLASH = 1 << 0,
+	SF_DUAL_PARALLEL_FLASH = 1 << 1,
+};
+
+/**
+ * struct spi_flash_params - SPI/QSPI flash device params structure
+ *
+ * @name:		Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO])
+ * @jedec:		Device jedec ID (0x[1byte_manuf_id][2byte_dev_id])
+ * @ext_jedec:		Device ext_jedec ID
+ * @sector_size:	Sector size of this device
+ * @nr_sectors:		No.of sectors on this device
+ * @e_rd_cmd:		Enum list for read commands
+ * @flags:		Important param, for flash specific behaviour
+ */
+struct spi_flash_params {
+	const char *name;
+	u32 jedec;
+	u16 ext_jedec;
+	u32 sector_size;
+	u32 nr_sectors;
+	u8 e_rd_cmd;
+	u16 flags;
+};
+
+extern const struct spi_flash_params spi_flash_params_table[];
+
+/**
+ * struct spi_flash - SPI flash structure
+ *
+ * @spi:		SPI slave
+ * @name:		Name of SPI flash
+ * @dual_flash:		Indicates dual flash memories - dual stacked, parallel
+ * @shift:		Flash shift useful in dual parallel
+ * @size:		Total flash size
+ * @page_size:		Write (page) size
+ * @sector_size:	Sector size
+ * @erase_size:		Erase size
+ * @bank_read_cmd:	Bank read cmd
+ * @bank_write_cmd:	Bank write cmd
+ * @bank_curr:		Current flash bank
+ * @poll_cmd:		Poll cmd - for flash erase/program
+ * @erase_cmd:		Erase cmd 4K, 32K, 64K
+ * @read_cmd:		Read cmd - Array Fast, Extn read and quad read.
+ * @write_cmd:		Write cmd - page and quad program.
+ * @dummy_byte:		Dummy cycles for read operation.
+ * @memory_map:		Address of read-only SPI flash access
+ * @read:		Flash read ops: Read len bytes at offset into buf
+ *			Supported cmds: Fast Array Read
+ * @write:		Flash write ops: Write len bytes from buf into offset
+ *			Supported cmds: Page Program
+ * @erase:		Flash erase ops: Erase len bytes from offset
+ *			Supported cmds: Sector erase 4K, 32K, 64K
+ * return 0 - Success, 1 - Failure
+ */
+struct spi_flash {
+	struct spi_slave *spi;
+	const char *name;
+	u8 dual_flash;
+	u8 shift;
+
+	u32 size;
+	u32 page_size;
+	u32 sector_size;
+	u32 erase_size;
+#ifdef CONFIG_SPI_FLASH_BAR
+	u8 bank_read_cmd;
+	u8 bank_write_cmd;
+	u8 bank_curr;
+#endif
+	u8 poll_cmd;
+	u8 erase_cmd;
+	u8 read_cmd;
+	u8 write_cmd;
+	u8 dummy_byte;
+
+	void *memory_map;
+	int (*read)(struct spi_flash *flash, u32 offset, size_t len, void *buf);
+	int (*write)(struct spi_flash *flash, u32 offset, size_t len,
+			const void *buf);
+	int (*erase)(struct spi_flash *flash, u32 offset, size_t len);
+};
+
+struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
+		unsigned int max_hz, unsigned int spi_mode);
+
+/**
+ * Set up a new SPI flash from an fdt node
+ *
+ * @param blob		Device tree blob
+ * @param slave_node	Pointer to this SPI slave node in the device tree
+ * @param spi_node	Cached pointer to the SPI interface this node belongs
+ *			to
+ * @return 0 if ok, -1 on error
+ */
+struct spi_flash *spi_flash_probe_fdt(const void *blob, int slave_node,
+				      int spi_node);
+
+void spi_flash_free(struct spi_flash *flash);
+
+static inline int spi_flash_read(struct spi_flash *flash, u32 offset,
+		size_t len, void *buf)
+{
+	return flash->read(flash, offset, len, buf);
+}
+
+static inline int spi_flash_write(struct spi_flash *flash, u32 offset,
+		size_t len, const void *buf)
+{
+	return flash->write(flash, offset, len, buf);
+}
+
+static inline int spi_flash_erase(struct spi_flash *flash, u32 offset,
+		size_t len)
+{
+	return flash->erase(flash, offset, len);
+}
+
+void spi_boot(void) __noreturn;
+void spi_spl_load_image(uint32_t offs, unsigned int size, void *vdst);
+
+#endif /* _SPI_FLASH_H_ */
diff --git a/qemu/roms/u-boot/include/spl.h b/qemu/roms/u-boot/include/spl.h
new file mode 100644
index 000000000..a7e41da7f
--- /dev/null
+++ b/qemu/roms/u-boot/include/spl.h
@@ -0,0 +1,78 @@
+/*
+ * (C) Copyright 2012
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef	_SPL_H_
+#define	_SPL_H_
+
+/* Platform-specific defines */
+#include <linux/compiler.h>
+#include <asm/spl.h>
+
+
+/* Boot type */
+#define MMCSD_MODE_UNDEFINED	0
+#define MMCSD_MODE_RAW		1
+#define MMCSD_MODE_FAT		2
+#define MMCSD_MODE_EMMCBOOT	3
+
+struct spl_image_info {
+	const char *name;
+	u8 os;
+	u32 load_addr;
+	u32 entry_point;
+	u32 size;
+	u32 flags;
+};
+
+#define SPL_COPY_PAYLOAD_ONLY	1
+
+extern struct spl_image_info spl_image;
+
+/* SPL common functions */
+void preloader_console_init(void);
+u32 spl_boot_device(void);
+u32 spl_boot_mode(void);
+void spl_parse_image_header(const struct image_header *header);
+void spl_board_prepare_for_linux(void);
+void __noreturn jump_to_image_linux(void *arg);
+int spl_start_uboot(void);
+void spl_display_print(void);
+
+/* NAND SPL functions */
+void spl_nand_load_image(void);
+
+/* OneNAND SPL functions */
+void spl_onenand_load_image(void);
+
+/* NOR SPL functions */
+void spl_nor_load_image(void);
+
+/* MMC SPL functions */
+void spl_mmc_load_image(void);
+
+/* YMODEM SPL functions */
+void spl_ymodem_load_image(void);
+
+/* SPI SPL functions */
+void spl_spi_load_image(void);
+
+/* Ethernet SPL functions */
+void spl_net_load_image(const char *device);
+
+/* USB SPL functions */
+void spl_usb_load_image(void);
+
+/* SATA SPL functions */
+void spl_sata_load_image(void);
+
+/* SPL FAT image functions */
+int spl_load_image_fat(block_dev_desc_t *block_dev, int partition, const char *filename);
+int spl_load_image_fat_os(block_dev_desc_t *block_dev, int partition);
+
+#ifdef CONFIG_SPL_BOARD_INIT
+void spl_board_init(void);
+#endif
+#endif
diff --git a/qemu/roms/u-boot/include/splash.h b/qemu/roms/u-boot/include/splash.h
new file mode 100644
index 000000000..89ee7b22e
--- /dev/null
+++ b/qemu/roms/u-boot/include/splash.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., http://www.fsf.org/about/contact/
+ */
+
+#ifndef _SPLASH_H_
+#define _SPLASH_H_
+
+
+int splash_screen_prepare(void);
+
+#ifdef CONFIG_SPLASH_SCREEN_ALIGN
+void splash_get_pos(int *x, int *y);
+#else
+static inline void splash_get_pos(int *x, int *y) { }
+#endif
+
+#define BMP_ALIGN_CENTER	0x7FFF
+
+#endif
diff --git a/qemu/roms/u-boot/include/status_led.h b/qemu/roms/u-boot/include/status_led.h
new file mode 100644
index 000000000..ecff60d59
--- /dev/null
+++ b/qemu/roms/u-boot/include/status_led.h
@@ -0,0 +1,324 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * The purpose of this code is to signal the operational status of a
+ * target which usually boots over the network; while running in
+ * PCBoot, a status LED is blinking. As soon as a valid BOOTP reply
+ * message has been received, the LED is turned off. The Linux
+ * kernel, once it is running, will start blinking the LED again,
+ * with another frequency.
+ */
+
+#ifndef _STATUS_LED_H_
+#define	_STATUS_LED_H_
+
+#ifdef CONFIG_STATUS_LED
+
+#define STATUS_LED_OFF		0
+#define STATUS_LED_BLINKING	1
+#define STATUS_LED_ON		2
+
+void status_led_tick (unsigned long timestamp);
+void status_led_set  (int led, int state);
+
+/*****  TQM8xxL  ********************************************************/
+#if defined(CONFIG_TQM8xxL)
+# define STATUS_LED_PAR		im_cpm.cp_pbpar
+# define STATUS_LED_DIR		im_cpm.cp_pbdir
+# define STATUS_LED_ODR		im_cpm.cp_pbodr
+# define STATUS_LED_DAT		im_cpm.cp_pbdat
+
+# define STATUS_LED_BIT		0x00000001
+# define STATUS_LED_PERIOD	(CONFIG_SYS_HZ / 2)
+# define STATUS_LED_STATE	STATUS_LED_BLINKING
+
+# define STATUS_LED_ACTIVE	1		/* LED on for bit == 1	*/
+
+# define STATUS_LED_BOOT	0		/* LED 0 used for boot status */
+
+/*****  MVS v1  **********************************************************/
+#elif (defined(CONFIG_MVS) && CONFIG_MVS < 2)
+# define STATUS_LED_PAR		im_ioport.iop_pdpar
+# define STATUS_LED_DIR		im_ioport.iop_pddir
+# undef  STATUS_LED_ODR
+# define STATUS_LED_DAT		im_ioport.iop_pddat
+
+# define STATUS_LED_BIT		0x00000001
+# define STATUS_LED_PERIOD	(CONFIG_SYS_HZ / 2)
+# define STATUS_LED_STATE	STATUS_LED_BLINKING
+
+# define STATUS_LED_ACTIVE	1		/* LED on for bit == 1	*/
+
+# define STATUS_LED_BOOT	0		/* LED 0 used for boot status */
+
+/*****  GEN860T  *********************************************************/
+#elif defined(CONFIG_GEN860T)
+
+# define STATUS_LED_PAR			im_ioport.iop_papar
+# define STATUS_LED_DIR			im_ioport.iop_padir
+# define STATUS_LED_ODR			im_ioport.iop_paodr
+# define STATUS_LED_DAT			im_ioport.iop_padat
+
+# define STATUS_LED_BIT			0x0800	/* Red LED 0 is on PA.4	*/
+# define STATUS_LED_PERIOD		(CONFIG_SYS_HZ / 4)
+# define STATUS_LED_STATE		STATUS_LED_OFF
+# define STATUS_LED_BIT1		0x0400	/* Grn LED 1 is on PA.5	*/
+# define STATUS_LED_PERIOD1		(CONFIG_SYS_HZ / 8)
+# define STATUS_LED_STATE1		STATUS_LED_BLINKING
+# define STATUS_LED_BIT2		0x0080	/* Red LED 2 is on PA.8	*/
+# define STATUS_LED_PERIOD2		(CONFIG_SYS_HZ / 4)
+# define STATUS_LED_STATE2		STATUS_LED_OFF
+# define STATUS_LED_BIT3		0x0040	/* Grn LED 3 is on PA.9	*/
+# define STATUS_LED_PERIOD3		(CONFIG_SYS_HZ / 4)
+# define STATUS_LED_STATE3		STATUS_LED_OFF
+
+# define STATUS_LED_ACTIVE		1	/* LED on for bit == 1	*/
+# define STATUS_LED_BOOT		1	/* Boot status on LED 1	*/
+
+/*****  IVMS8  **********************************************************/
+#elif defined(CONFIG_IVMS8)
+
+# define STATUS_LED_PAR		im_cpm.cp_pbpar
+# define STATUS_LED_DIR		im_cpm.cp_pbdir
+# define STATUS_LED_ODR		im_cpm.cp_pbodr
+# define STATUS_LED_DAT		im_cpm.cp_pbdat
+
+# define STATUS_LED_BIT		0x00000010	/* LED 0 is on PB.27	*/
+# define STATUS_LED_PERIOD	(1 * CONFIG_SYS_HZ)
+# define STATUS_LED_STATE	STATUS_LED_OFF
+# define STATUS_LED_BIT1	0x00000020	/* LED 1 is on PB.26	*/
+# define STATUS_LED_PERIOD1	(1 * CONFIG_SYS_HZ)
+# define STATUS_LED_STATE1	STATUS_LED_OFF
+/* IDE LED usable for other purposes, too */
+# define STATUS_LED_BIT2	0x00000008	/* LED 2 is on PB.28	*/
+# define STATUS_LED_PERIOD2	(1 * CONFIG_SYS_HZ)
+# define STATUS_LED_STATE2	STATUS_LED_OFF
+
+# define STATUS_LED_ACTIVE	1		/* LED on for bit == 1	*/
+
+# define STATUS_ILOCK_SWITCH	0x00800000	/* ILOCK switch in IRQ4	*/
+
+# define STATUS_ILOCK_PERIOD	(CONFIG_SYS_HZ / 10)	/* about every 100 ms	*/
+
+# define STATUS_LED_YELLOW	0
+# define STATUS_LED_GREEN	1
+# define STATUS_LED_BOOT	2		/* IDE LED used for boot status */
+
+/*****  IVML24  *********************************************************/
+#elif defined(CONFIG_IVML24)
+
+# define STATUS_LED_PAR		im_cpm.cp_pbpar
+# define STATUS_LED_DIR		im_cpm.cp_pbdir
+# define STATUS_LED_ODR		im_cpm.cp_pbodr
+# define STATUS_LED_DAT		im_cpm.cp_pbdat
+
+# define STATUS_LED_BIT		0x00000010	/* LED 0 is on PB.27	*/
+# define STATUS_LED_PERIOD	(1 * CONFIG_SYS_HZ)
+# define STATUS_LED_STATE	STATUS_LED_OFF
+# define STATUS_LED_BIT1	0x00000020	/* LED 1 is on PB.26	*/
+# define STATUS_LED_PERIOD1	(1 * CONFIG_SYS_HZ)
+# define STATUS_LED_STATE1	STATUS_LED_OFF
+/* IDE LED usable for other purposes, too */
+# define STATUS_LED_BIT2	0x00000008	/* LED 2 is on PB.28	*/
+# define STATUS_LED_PERIOD2	(1 * CONFIG_SYS_HZ)
+# define STATUS_LED_STATE2	STATUS_LED_OFF
+
+# define STATUS_LED_ACTIVE	1		/* LED on for bit == 1	*/
+
+# define STATUS_ILOCK_SWITCH	0x00004000	/* ILOCK is on PB.17	*/
+
+# define STATUS_ILOCK_PERIOD	(CONFIG_SYS_HZ / 10)	/* about every 100 ms	*/
+
+# define STATUS_LED_YELLOW	0
+# define STATUS_LED_GREEN	1
+# define STATUS_LED_BOOT	2		/* IDE LED used for boot status */
+
+/*****  ICU862   ********************************************************/
+#elif defined(CONFIG_ICU862)
+
+# define STATUS_LED_PAR		im_ioport.iop_papar
+# define STATUS_LED_DIR		im_ioport.iop_padir
+# define STATUS_LED_ODR		im_ioport.iop_paodr
+# define STATUS_LED_DAT		im_ioport.iop_padat
+
+# define STATUS_LED_BIT		0x4000		/* LED 0 is on PA.1 */
+# define STATUS_LED_PERIOD	(CONFIG_SYS_HZ / 2)
+# define STATUS_LED_STATE	STATUS_LED_BLINKING
+# define STATUS_LED_BIT1	0x1000		/* LED 1 is on PA.3 */
+# define STATUS_LED_PERIOD1	(CONFIG_SYS_HZ)
+# define STATUS_LED_STATE1	STATUS_LED_OFF
+
+# define STATUS_LED_ACTIVE	1		/* LED on for bit == 1	*/
+
+# define STATUS_LED_BOOT	0		/* LED 0 used for boot status */
+
+/*****  Someone else defines these  *************************************/
+#elif defined(STATUS_LED_PAR)
+
+  /*
+   * ADVICE: Define in your board configuration file rather than
+   * filling this file up with lots of custom board stuff.
+   */
+
+/*****  NetVia   ********************************************************/
+#elif defined(CONFIG_NETVIA)
+
+#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
+
+#define STATUS_LED_PAR		im_ioport.iop_pdpar
+#define STATUS_LED_DIR		im_ioport.iop_pddir
+#undef  STATUS_LED_ODR
+#define STATUS_LED_DAT		im_ioport.iop_pddat
+
+# define STATUS_LED_BIT		0x0080			/* PD.8 */
+# define STATUS_LED_PERIOD	(CONFIG_SYS_HZ / 2)
+# define STATUS_LED_STATE	STATUS_LED_BLINKING
+
+# define STATUS_LED_BIT1	0x0040			/* PD.9 */
+# define STATUS_LED_PERIOD1	(CONFIG_SYS_HZ / 2)
+# define STATUS_LED_STATE1	STATUS_LED_OFF
+
+# define STATUS_LED_ACTIVE	0		/* LED on for bit == 0	*/
+# define STATUS_LED_BOOT	0		/* LED 0 used for boot status */
+
+#endif
+
+/*****  CMI   ********************************************************/
+#elif defined(CONFIG_CMI)
+# define STATUS_LED_DIR		im_mios.mios_mpiosm32ddr
+# define STATUS_LED_DAT		im_mios.mios_mpiosm32dr
+
+# define STATUS_LED_BIT		0x2000		/* Select one of the 16 possible*/
+						/* MIOS outputs */
+# define STATUS_LED_PERIOD	(CONFIG_SYS_HZ / 2)	/* Blinking periode is 500 ms */
+# define STATUS_LED_STATE	STATUS_LED_BLINKING
+
+# define STATUS_LED_ACTIVE	1		/* LED on for bit == 0	*/
+# define STATUS_LED_BOOT	0		/* LED 0 used for boot status */
+
+/*****  KUP4K, KUP4X  ****************************************************/
+#elif defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X)
+
+# define STATUS_LED_PAR		im_ioport.iop_papar
+# define STATUS_LED_DIR		im_ioport.iop_padir
+# define STATUS_LED_ODR		im_ioport.iop_paodr
+# define STATUS_LED_DAT		im_ioport.iop_padat
+
+# define STATUS_LED_BIT		0x00000300  /*  green + red    PA[8]=yellow,  PA[7]=red,  PA[6]=green */
+# define STATUS_LED_PERIOD	(CONFIG_SYS_HZ / 2)
+# define STATUS_LED_STATE	STATUS_LED_BLINKING
+
+# define STATUS_LED_ACTIVE	1		/* LED on for bit == 1	*/
+
+# define STATUS_LED_BOOT	0		/* LED 0 used for boot status */
+
+#elif defined(CONFIG_SVM_SC8xx)
+# define STATUS_LED_PAR         im_cpm.cp_pbpar
+# define STATUS_LED_DIR         im_cpm.cp_pbdir
+# define STATUS_LED_ODR         im_cpm.cp_pbodr
+# define STATUS_LED_DAT         im_cpm.cp_pbdat
+
+# define STATUS_LED_BIT         0x00000001
+# define STATUS_LED_PERIOD      (CONFIG_SYS_HZ / 2)
+# define STATUS_LED_STATE       STATUS_LED_BLINKING
+
+# define STATUS_LED_ACTIVE      1               /* LED on for bit == 1  */
+
+# define STATUS_LED_BOOT        0               /* LED 0 used for boot status */
+
+/*****  RBC823    ********************************************************/
+#elif defined(CONFIG_RBC823)
+
+# define STATUS_LED_PAR         im_ioport.iop_pcpar
+# define STATUS_LED_DIR         im_ioport.iop_pcdir
+#  undef STATUS_LED_ODR
+# define STATUS_LED_DAT         im_ioport.iop_pcdat
+
+# define STATUS_LED_BIT         0x0002          /* LED 0 is on PC.14 */
+# define STATUS_LED_PERIOD      (CONFIG_SYS_HZ / 2)
+# define STATUS_LED_STATE       STATUS_LED_BLINKING
+# define STATUS_LED_BIT1        0x0004          /* LED 1 is on PC.13 */
+# define STATUS_LED_PERIOD1     (CONFIG_SYS_HZ)
+# define STATUS_LED_STATE1      STATUS_LED_OFF
+
+# define STATUS_LED_ACTIVE      1               /* LED on for bit == 1  */
+
+# define STATUS_LED_BOOT        0               /* LED 0 used for boot status */
+
+/*****  NetPhone   ********************************************************/
+#elif defined(CONFIG_NETPHONE) || defined(CONFIG_NETTA2)
+/* XXX empty just to avoid the error */
+/*****  STx XTc    ********************************************************/
+#elif defined(CONFIG_STXXTC)
+/* XXX empty just to avoid the error */
+/************************************************************************/
+#elif defined(CONFIG_V38B)
+
+# define STATUS_LED_BIT		0x0010			/* Timer7 GPIO */
+# define STATUS_LED_PERIOD	(CONFIG_SYS_HZ / 2)
+# define STATUS_LED_STATE	STATUS_LED_BLINKING
+
+# define STATUS_LED_ACTIVE	0		/* LED on for bit == 0 */
+# define STATUS_LED_BOOT	0		/* LED 0 used for boot status */
+
+#elif defined(CONFIG_MOTIONPRO)
+
+#define STATUS_LED_BIT		((vu_long *) MPC5XXX_GPT6_ENABLE)
+#define STATUS_LED_PERIOD	(CONFIG_SYS_HZ / 10)
+#define STATUS_LED_STATE	STATUS_LED_BLINKING
+
+#define STATUS_LED_BIT1		((vu_long *) MPC5XXX_GPT7_ENABLE)
+#define STATUS_LED_PERIOD1	(CONFIG_SYS_HZ / 10)
+#define STATUS_LED_STATE1	STATUS_LED_OFF
+
+#define STATUS_LED_BOOT		0	/* LED 0 used for boot status */
+
+#elif defined(CONFIG_BOARD_SPECIFIC_LED)
+/* led_id_t is unsigned long mask */
+typedef unsigned long led_id_t;
+
+extern void __led_toggle (led_id_t mask);
+extern void __led_init (led_id_t mask, int state);
+extern void __led_set (led_id_t mask, int state);
+#else
+# error Status LED configuration missing
+#endif
+/************************************************************************/
+
+#ifndef CONFIG_BOARD_SPECIFIC_LED
+# include <asm/status_led.h>
+#endif
+
+/*
+ * Coloured LEDs API
+ */
+#ifndef	__ASSEMBLY__
+extern void	coloured_LED_init (void);
+extern void	red_led_on(void);
+extern void	red_led_off(void);
+extern void	green_led_on(void);
+extern void	green_led_off(void);
+extern void	yellow_led_on(void);
+extern void	yellow_led_off(void);
+extern void	blue_led_on(void);
+extern void	blue_led_off(void);
+#else
+	.extern LED_init
+	.extern red_led_on
+	.extern red_led_off
+	.extern yellow_led_on
+	.extern yellow_led_off
+	.extern green_led_on
+	.extern green_led_off
+	.extern blue_led_on
+	.extern blue_led_off
+#endif
+
+#endif	/* CONFIG_STATUS_LED	*/
+
+#endif	/* _STATUS_LED_H_	*/
diff --git a/qemu/roms/u-boot/include/stdio_dev.h b/qemu/roms/u-boot/include/stdio_dev.h
new file mode 100644
index 000000000..e6dc12ac3
--- /dev/null
+++ b/qemu/roms/u-boot/include/stdio_dev.h
@@ -0,0 +1,108 @@
+/*
+ * (C) Copyright 2000
+ * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _STDIO_DEV_H_
+#define _STDIO_DEV_H_
+
+#include <linux/list.h>
+
+/*
+ * STDIO DEVICES
+ */
+
+#define DEV_FLAGS_INPUT	 0x00000001	/* Device can be used as input	console */
+#define DEV_FLAGS_OUTPUT 0x00000002	/* Device can be used as output console */
+#define DEV_FLAGS_SYSTEM 0x80000000	/* Device is a system device		*/
+#define DEV_EXT_VIDEO	 0x00000001	/* Video extensions supported		*/
+
+/* Device information */
+struct stdio_dev {
+	int	flags;			/* Device flags: input/output/system	*/
+	int	ext;			/* Supported extensions			*/
+	char	name[16];		/* Device name				*/
+
+/* GENERAL functions */
+
+	int (*start) (void);		/* To start the device			*/
+	int (*stop) (void);		/* To stop the device			*/
+
+/* OUTPUT functions */
+
+	void (*putc) (const char c);	/* To put a char			*/
+	void (*puts) (const char *s);	/* To put a string (accelerator)	*/
+
+/* INPUT functions */
+
+	int (*tstc) (void);		/* To test if a char is ready...	*/
+	int (*getc) (void);		/* To get that char			*/
+
+/* Other functions */
+
+	void *priv;			/* Private extensions			*/
+	struct list_head list;
+};
+
+/*
+ * VIDEO EXTENSIONS
+ */
+#define VIDEO_FORMAT_RGB_INDEXED	0x0000
+#define VIDEO_FORMAT_RGB_DIRECTCOLOR	0x0001
+#define VIDEO_FORMAT_YUYV_4_4_4		0x0010
+#define VIDEO_FORMAT_YUYV_4_2_2		0x0011
+
+typedef struct {
+	void *address;			/* Address of framebuffer		*/
+	ushort	width;			/* Horizontal resolution		*/
+	ushort	height;			/* Vertical resolution			*/
+	uchar	format;			/* Format				*/
+	uchar	colors;			/* Colors number or color depth		*/
+	void (*setcolreg) (int, int, int, int);
+	void (*getcolreg) (int, void *);
+} video_ext_t;
+
+/*
+ * VARIABLES
+ */
+extern struct stdio_dev *stdio_devices[];
+extern char *stdio_names[MAX_FILES];
+
+/*
+ * PROTOTYPES
+ */
+int	stdio_register (struct stdio_dev * dev);
+int	stdio_init (void);
+void	stdio_print_current_devices(void);
+#ifdef CONFIG_SYS_STDIO_DEREGISTER
+int	stdio_deregister(const char *devname);
+#endif
+struct list_head* stdio_get_list(void);
+struct stdio_dev* stdio_get_by_name(const char* name);
+struct stdio_dev* stdio_clone(struct stdio_dev *dev);
+
+#ifdef CONFIG_LCD
+int	drv_lcd_init (void);
+#endif
+#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
+int	drv_video_init (void);
+#endif
+#ifdef CONFIG_KEYBOARD
+int	drv_keyboard_init (void);
+#endif
+#ifdef CONFIG_USB_TTY
+int	drv_usbtty_init (void);
+#endif
+#ifdef CONFIG_NETCONSOLE
+int	drv_nc_init (void);
+#endif
+#ifdef CONFIG_JTAG_CONSOLE
+int drv_jtag_console_init (void);
+#endif
+#ifdef CONFIG_CBMEM_CONSOLE
+int cbmemc_init(void);
+#endif
+
+#endif
diff --git a/qemu/roms/u-boot/include/stratixII.h b/qemu/roms/u-boot/include/stratixII.h
new file mode 100644
index 000000000..5873dd754
--- /dev/null
+++ b/qemu/roms/u-boot/include/stratixII.h
@@ -0,0 +1,14 @@
+/*
+ * (C) Copyright 2007
+ * Eran Liberty, Extricom, eran.liberty@gmail.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _STRATIXII_H_
+#define _STRATIXII_H_
+
+extern int StratixII_load (Altera_desc * desc, void *image, size_t size);
+extern int StratixII_dump (Altera_desc * desc, void *buf, size_t bsize);
+extern int StratixII_info (Altera_desc * desc);
+
+#endif				/* _STRATIXII_H_ */
diff --git a/qemu/roms/u-boot/include/sx151x.h b/qemu/roms/u-boot/include/sx151x.h
new file mode 100644
index 000000000..be42b0681
--- /dev/null
+++ b/qemu/roms/u-boot/include/sx151x.h
@@ -0,0 +1,17 @@
+/*
+ * (C) Copyright 2013
+ * Viktar Palstsiuk, Promwad, viktar.palstsiuk@promwad.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __SX151X_H_
+#define __SX151X_H_
+
+int sx151x_get_value(int chip, int gpio);
+int sx151x_set_value(int chip, int gpio, int val);
+int sx151x_direction_input(int chip, int gpio);
+int sx151x_direction_output(int chip, int gpio);
+int sx151x_reset(int chip);
+
+#endif /* __SX151X_H_ */
diff --git a/qemu/roms/u-boot/include/sym53c8xx.h b/qemu/roms/u-boot/include/sym53c8xx.h
new file mode 100644
index 000000000..f992a8552
--- /dev/null
+++ b/qemu/roms/u-boot/include/sym53c8xx.h
@@ -0,0 +1,553 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Most of these definitions are derived from
+ * linux/drivers/scsi/sym53c8xx_defs.h
+ */
+
+#ifndef _SYM53C8XX_DEFS_H
+#define _SYM53C8XX_DEFS_H
+
+
+#define SCNTL0		0x00    /* full arb., ena parity, par->ATN  */
+
+#define SCNTL1		0x01    /* no reset                         */
+  #define   ISCON   0x10  /* connected to scsi						*/
+  #define   CRST    0x08  /* force reset                      */
+  #define   IARB    0x02  /* immediate arbitration            */
+
+#define SCNTL2		0x02    /* no disconnect expected           */
+	#define   SDU     0x80  /* cmd: disconnect will raise error */
+	#define   CHM     0x40  /* sta: chained mode                */
+	#define   WSS     0x08  /* sta: wide scsi send           [W]*/
+	#define   WSR     0x01  /* sta: wide scsi received       [W]*/
+
+#define SCNTL3		0x03    /* cnf system clock dependent       */
+	#define   EWS     0x08  /* cmd: enable wide scsi         [W]*/
+	#define   ULTRA   0x80  /* cmd: ULTRA enable                */
+				/* bits 0-2, 7 rsvd for C1010       */
+
+#define SCID			0x04		/* cnf host adapter scsi address    */
+	#define   RRE     0x40  /* r/w:e enable response to resel.  */
+	#define   SRE     0x20  /* r/w:e enable response to select  */
+
+#define SXFER			0x05		/* ### Sync speed and count         */
+				/* bits 6-7 rsvd for C1010          */
+
+#define SDID			0x06	/* ### Destination-ID               */
+
+#define GPREG			0x07	/* ??? IO-Pins                      */
+
+#define SFBR			0x08	/* ### First byte in phase          */
+
+#define SOCL			0x09
+	#define   CREQ	  0x80	/* r/w: SCSI-REQ                    */
+	#define   CACK	  0x40	/* r/w: SCSI-ACK                    */
+	#define   CBSY	  0x20	/* r/w: SCSI-BSY                    */
+	#define   CSEL	  0x10	/* r/w: SCSI-SEL                    */
+	#define   CATN	  0x08	/* r/w: SCSI-ATN                    */
+	#define   CMSG	  0x04	/* r/w: SCSI-MSG                    */
+	#define   CC_D	  0x02	/* r/w: SCSI-C_D                    */
+	#define   CI_O	  0x01	/* r/w: SCSI-I_O                    */
+
+#define SSID			0x0a
+
+#define SBCL			0x0b
+
+#define DSTAT			0x0c
+  #define   DFE     0x80  /* sta: dma fifo empty              */
+  #define   MDPE    0x40  /* int: master data parity error    */
+  #define   BF      0x20  /* int: script: bus fault           */
+  #define   ABRT    0x10  /* int: script: command aborted     */
+  #define   SSI     0x08  /* int: script: single step         */
+  #define   SIR     0x04  /* int: script: interrupt instruct. */
+  #define   IID     0x01  /* int: script: illegal instruct.   */
+
+#define SSTAT0		0x0d
+  #define   ILF     0x80  /* sta: data in SIDL register lsb   */
+  #define   ORF     0x40  /* sta: data in SODR register lsb   */
+  #define   OLF     0x20  /* sta: data in SODL register lsb   */
+  #define   AIP     0x10  /* sta: arbitration in progress     */
+  #define   LOA     0x08  /* sta: arbitration lost            */
+  #define   WOA     0x04  /* sta: arbitration won             */
+  #define   IRST    0x02  /* sta: scsi reset signal           */
+  #define   SDP     0x01  /* sta: scsi parity signal          */
+
+#define SSTAT1		0x0e
+	#define   FF3210  0xf0	/* sta: bytes in the scsi fifo      */
+
+#define SSTAT2		0x0f
+  #define   ILF1    0x80  /* sta: data in SIDL register msb[W]*/
+  #define   ORF1    0x40  /* sta: data in SODR register msb[W]*/
+  #define   OLF1    0x20  /* sta: data in SODL register msb[W]*/
+  #define   DM      0x04  /* sta: DIFFSENS mismatch (895/6 only) */
+  #define   LDSC    0x02  /* sta: disconnect & reconnect      */
+
+#define DSA				0x10		/* --> Base page                    */
+#define DSA1			0x11
+#define DSA2			0x12
+#define DSA3			0x13
+
+#define ISTAT			0x14	/* --> Main Command and status      */
+  #define   CABRT   0x80  /* cmd: abort current operation     */
+  #define   SRST    0x40  /* mod: reset chip                  */
+  #define   SIGP    0x20  /* r/w: message from host to ncr    */
+  #define   SEM     0x10  /* r/w: message between host + ncr  */
+  #define   CON     0x08  /* sta: connected to scsi           */
+  #define   INTF    0x04  /* sta: int on the fly (reset by wr)*/
+  #define   SIP     0x02  /* sta: scsi-interrupt              */
+  #define   DIP     0x01  /* sta: host/script interrupt       */
+
+
+#define CTEST0		0x18
+#define CTEST1		0x19
+#define CTEST2		0x1a
+	#define   CSIGP   0x40
+				/* bits 0-2,7 rsvd for C1010        */
+
+#define CTEST3		0x1b
+	#define   FLF     0x08  /* cmd: flush dma fifo              */
+	#define   CLF		0x04	/* cmd: clear dma fifo		    */
+	#define   FM      0x02  /* mod: fetch pin mode              */
+	#define   WRIE    0x01  /* mod: write and invalidate enable */
+				/* bits 4-7 rsvd for C1010          */
+
+#define DFIFO			0x20
+#define CTEST4		0x21
+	#define   BDIS    0x80  /* mod: burst disable               */
+	#define   MPEE    0x08  /* mod: master parity error enable  */
+
+#define CTEST5		0x22
+	#define   DFS     0x20  /* mod: dma fifo size               */
+				/* bits 0-1, 3-7 rsvd for C1010          */
+#define CTEST6		0x23
+
+#define DBC				0x24	/* ### Byte count and command       */
+#define DNAD			0x28	/* ### Next command register        */
+#define DSP				0x2c	/* --> Script Pointer               */
+#define DSPS			0x30	/* --> Script pointer save/opcode#2 */
+
+#define SCRATCHA	0x34  /* Temporary register a            */
+#define SCRATCHA1	0x35
+#define SCRATCHA2	0x36
+#define SCRATCHA3	0x37
+
+#define DMODE			0x38
+	#define   BL_2    0x80  /* mod: burst length shift value +2 */
+	#define   BL_1    0x40  /* mod: burst length shift value +1 */
+	#define   ERL     0x08  /* mod: enable read line            */
+	#define   ERMP    0x04  /* mod: enable read multiple        */
+	#define   BOF     0x02  /* mod: burst op code fetch         */
+	#define   MAN     0x01  /* mod: manual start				         */
+
+#define DIEN		0x39
+#define SBR			0x3a
+
+#define DCNTL		0x3b			/* --> Script execution control     */
+	#define   CLSE    0x80  /* mod: cache line size enable      */
+	#define   PFF     0x40  /* cmd: pre-fetch flush             */
+	#define   PFEN    0x20  /* mod: pre-fetch enable            */
+	#define   SSM     0x10  /* mod: single step mode            */
+	#define   IRQM    0x08  /* mod: irq mode (1 = totem pole !) */
+	#define   STD     0x04  /* cmd: start dma mode              */
+	#define   IRQD    0x02  /* mod: irq disable                 */
+	#define	  NOCOM   0x01	/* cmd: protect sfbr while reselect */
+				/* bits 0-1 rsvd for C1010          */
+
+#define ADDER			0x3c
+
+#define SIEN			0x40	/* -->: interrupt enable            */
+#define SIST			0x42	/* <--: interrupt status            */
+  #define   SBMC    0x1000/* sta: SCSI Bus Mode Change (895/6 only) */
+  #define   STO     0x0400/* sta: timeout (select)            */
+  #define   GEN     0x0200/* sta: timeout (general)           */
+  #define   HTH     0x0100/* sta: timeout (handshake)         */
+  #define   MA      0x80  /* sta: phase mismatch              */
+  #define   CMP     0x40  /* sta: arbitration complete        */
+  #define   SEL     0x20  /* sta: selected by another device  */
+  #define   RSL     0x10  /* sta: reselected by another device*/
+  #define   SGE     0x08  /* sta: gross error (over/underflow)*/
+  #define   UDC     0x04  /* sta: unexpected disconnect       */
+  #define   RST     0x02  /* sta: scsi bus reset detected     */
+  #define   PAR     0x01  /* sta: scsi parity error           */
+
+#define SLPAR				0x44
+#define SWIDE				0x45
+#define MACNTL			0x46
+#define GPCNTL			0x47
+#define STIME0			0x48    /* cmd: timeout for select&handshake*/
+#define STIME1			0x49    /* cmd: timeout user defined        */
+#define RESPID			0x4a    /* sta: Reselect-IDs                */
+
+#define STEST0			0x4c
+
+#define STEST1			0x4d
+	#define   SCLK    0x80	/* Use the PCI clock as SCSI clock	*/
+	#define   DBLEN   0x08	/* clock doubler running		*/
+	#define   DBLSEL  0x04	/* clock doubler selected		*/
+
+
+#define STEST2			0x4e
+	#define   ROF     0x40	/* reset scsi offset (after gross error!) */
+	#define   EXT     0x02  /* extended filtering                     */
+
+#define STEST3			0x4f
+	#define   TE     0x80	/* c: tolerAnt enable */
+	#define   HSC    0x20	/* c: Halt SCSI Clock */
+	#define   CSF    0x02	/* c: clear scsi fifo */
+
+#define SIDL			0x50	/* Lowlevel: latched from scsi data */
+#define STEST4		0x52
+	#define SMODE	0xc0	/* SCSI bus mode      (895/6 only) */
+	#define SMODE_HVD 0x40	/* High Voltage Differential       */
+	#define SMODE_SE  0x80	/* Single Ended                    */
+	#define SMODE_LVD 0xc0	/* Low Voltage Differential        */
+	#define LCKFRQ 0x20	/* Frequency Lock (895/6 only)     */
+				/* bits 0-5 rsvd for C1010          */
+
+#define SODL			0x54	/* Lowlevel: data out to scsi data  */
+
+#define SBDL			0x58	/* Lowlevel: data from scsi data    */
+
+
+/*-----------------------------------------------------------
+**
+**	Utility macros for the script.
+**
+**-----------------------------------------------------------
+*/
+
+#define REG(r) (r)
+
+/*-----------------------------------------------------------
+**
+**	SCSI phases
+**
+**	DT phases illegal for ncr driver.
+**
+**-----------------------------------------------------------
+*/
+
+#define	SCR_DATA_OUT	0x00000000
+#define	SCR_DATA_IN	0x01000000
+#define	SCR_COMMAND	0x02000000
+#define	SCR_STATUS	0x03000000
+#define SCR_DT_DATA_OUT	0x04000000
+#define SCR_DT_DATA_IN	0x05000000
+#define SCR_MSG_OUT	0x06000000
+#define SCR_MSG_IN      0x07000000
+
+#define SCR_ILG_OUT	0x04000000
+#define SCR_ILG_IN	0x05000000
+
+/*-----------------------------------------------------------
+**
+**	Data transfer via SCSI.
+**
+**-----------------------------------------------------------
+**
+**	MOVE_ABS (LEN)
+**	<<start address>>
+**
+**	MOVE_IND (LEN)
+**	<<dnad_offset>>
+**
+**	MOVE_TBL
+**	<<dnad_offset>>
+**
+**-----------------------------------------------------------
+*/
+
+#define OPC_MOVE          0x08000000
+
+#define SCR_MOVE_ABS(l) ((0x00000000 | OPC_MOVE) | (l))
+#define SCR_MOVE_IND(l) ((0x20000000 | OPC_MOVE) | (l))
+#define SCR_MOVE_TBL     (0x10000000 | OPC_MOVE)
+
+#define SCR_CHMOV_ABS(l) ((0x00000000) | (l))
+#define SCR_CHMOV_IND(l) ((0x20000000) | (l))
+#define SCR_CHMOV_TBL     (0x10000000)
+
+
+/*-----------------------------------------------------------
+**
+**	Selection
+**
+**-----------------------------------------------------------
+**
+**	SEL_ABS | SCR_ID (0..15)    [ | REL_JMP]
+**	<<alternate_address>>
+**
+**	SEL_TBL | << dnad_offset>>  [ | REL_JMP]
+**	<<alternate_address>>
+**
+**-----------------------------------------------------------
+*/
+
+#define	SCR_SEL_ABS	0x40000000
+#define	SCR_SEL_ABS_ATN	0x41000000
+#define	SCR_SEL_TBL	0x42000000
+#define	SCR_SEL_TBL_ATN	0x43000000
+
+
+#define SCR_JMP_REL     0x04000000
+#define SCR_ID(id)	(((unsigned long)(id)) << 16)
+
+/*-----------------------------------------------------------
+**
+**	Waiting for Disconnect or Reselect
+**
+**-----------------------------------------------------------
+**
+**	WAIT_DISC
+**	dummy: <<alternate_address>>
+**
+**	WAIT_RESEL
+**	<<alternate_address>>
+**
+**-----------------------------------------------------------
+*/
+
+#define	SCR_WAIT_DISC	0x48000000
+#define SCR_WAIT_RESEL  0x50000000
+
+/*-----------------------------------------------------------
+**
+**	Bit Set / Reset
+**
+**-----------------------------------------------------------
+**
+**	SET (flags {|.. })
+**
+**	CLR (flags {|.. })
+**
+**-----------------------------------------------------------
+*/
+
+#define SCR_SET(f)     (0x58000000 | (f))
+#define SCR_CLR(f)     (0x60000000 | (f))
+
+#define	SCR_CARRY	0x00000400
+#define	SCR_TRG		0x00000200
+#define	SCR_ACK		0x00000040
+#define	SCR_ATN		0x00000008
+
+
+/*-----------------------------------------------------------
+**
+**	Memory to memory move
+**
+**-----------------------------------------------------------
+**
+**	COPY (bytecount)
+**	<< source_address >>
+**	<< destination_address >>
+**
+**	SCR_COPY   sets the NO FLUSH option by default.
+**	SCR_COPY_F does not set this option.
+**
+**	For chips which do not support this option,
+**	ncr_copy_and_bind() will remove this bit.
+**-----------------------------------------------------------
+*/
+
+#define SCR_NO_FLUSH 0x01000000
+
+#define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n))
+#define SCR_COPY_F(n) (0xc0000000 | (n))
+
+/*-----------------------------------------------------------
+**
+**	Register move and binary operations
+**
+**-----------------------------------------------------------
+**
+**	SFBR_REG (reg, op, data)        reg  = SFBR op data
+**	<< 0 >>
+**
+**	REG_SFBR (reg, op, data)        SFBR = reg op data
+**	<< 0 >>
+**
+**	REG_REG  (reg, op, data)        reg  = reg op data
+**	<< 0 >>
+**
+**-----------------------------------------------------------
+**	On 810A, 860, 825A, 875, 895 and 896 chips the content
+**	of SFBR register can be used as data (SCR_SFBR_DATA).
+**	The 896 has additionnal IO registers starting at
+**	offset 0x80. Bit 7 of register offset is stored in
+**	bit 7 of the SCRIPTS instruction first DWORD.
+**-----------------------------------------------------------
+*/
+
+#define SCR_REG_OFS(ofs) ((((ofs) & 0x7f) << 16ul)) /* + ((ofs) & 0x80)) */
+
+#define SCR_SFBR_REG(reg,op,data) \
+	(0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
+
+#define SCR_REG_SFBR(reg,op,data) \
+	(0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
+
+#define SCR_REG_REG(reg,op,data) \
+	(0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
+
+
+#define      SCR_LOAD   0x00000000
+#define      SCR_SHL    0x01000000
+#define      SCR_OR     0x02000000
+#define      SCR_XOR    0x03000000
+#define      SCR_AND    0x04000000
+#define      SCR_SHR    0x05000000
+#define      SCR_ADD    0x06000000
+#define      SCR_ADDC   0x07000000
+
+#define      SCR_SFBR_DATA   (0x00800000>>8ul)	/* Use SFBR as data */
+
+/*-----------------------------------------------------------
+**
+**	FROM_REG (reg)		  SFBR = reg
+**	<< 0 >>
+**
+**	TO_REG	 (reg)		  reg  = SFBR
+**	<< 0 >>
+**
+**	LOAD_REG (reg, data)	  reg  = <data>
+**	<< 0 >>
+**
+**	LOAD_SFBR(data)		  SFBR = <data>
+**	<< 0 >>
+**
+**-----------------------------------------------------------
+*/
+
+#define	SCR_FROM_REG(reg) \
+	SCR_REG_SFBR(reg,SCR_OR,0)
+
+#define	SCR_TO_REG(reg) \
+	SCR_SFBR_REG(reg,SCR_OR,0)
+
+#define	SCR_LOAD_REG(reg,data) \
+	SCR_REG_REG(reg,SCR_LOAD,data)
+
+#define SCR_LOAD_SFBR(data) \
+	(SCR_REG_SFBR (gpreg, SCR_LOAD, data))
+
+/*-----------------------------------------------------------
+**
+**	LOAD  from memory   to register.
+**	STORE from register to memory.
+**
+**	Only supported by 810A, 860, 825A, 875, 895 and 896.
+**
+**-----------------------------------------------------------
+**
+**	LOAD_ABS (LEN)
+**	<<start address>>
+**
+**	LOAD_REL (LEN)        (DSA relative)
+**	<<dsa_offset>>
+**
+**-----------------------------------------------------------
+*/
+
+#define SCR_REG_OFS2(ofs) (((ofs) & 0xff) << 16ul)
+#define SCR_NO_FLUSH2	0x02000000
+#define SCR_DSA_REL2	0x10000000
+
+#define SCR_LOAD_R(reg, how, n) \
+	(0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
+
+#define SCR_STORE_R(reg, how, n) \
+	(0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
+
+#define SCR_LOAD_ABS(reg, n)	SCR_LOAD_R(reg, SCR_NO_FLUSH2, n)
+#define SCR_LOAD_REL(reg, n)	SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n)
+#define SCR_LOAD_ABS_F(reg, n)	SCR_LOAD_R(reg, 0, n)
+#define SCR_LOAD_REL_F(reg, n)	SCR_LOAD_R(reg, SCR_DSA_REL2, n)
+
+#define SCR_STORE_ABS(reg, n)	SCR_STORE_R(reg, SCR_NO_FLUSH2, n)
+#define SCR_STORE_REL(reg, n)	SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n)
+#define SCR_STORE_ABS_F(reg, n)	SCR_STORE_R(reg, 0, n)
+#define SCR_STORE_REL_F(reg, n)	SCR_STORE_R(reg, SCR_DSA_REL2, n)
+
+
+/*-----------------------------------------------------------
+**
+**	Waiting for Disconnect or Reselect
+**
+**-----------------------------------------------------------
+**
+**	JUMP            [ | IFTRUE/IFFALSE ( ... ) ]
+**	<<address>>
+**
+**	JUMPR           [ | IFTRUE/IFFALSE ( ... ) ]
+**	<<distance>>
+**
+**	CALL            [ | IFTRUE/IFFALSE ( ... ) ]
+**	<<address>>
+**
+**	CALLR           [ | IFTRUE/IFFALSE ( ... ) ]
+**	<<distance>>
+**
+**	RETURN          [ | IFTRUE/IFFALSE ( ... ) ]
+**	<<dummy>>
+**
+**	INT             [ | IFTRUE/IFFALSE ( ... ) ]
+**	<<ident>>
+**
+**	INT_FLY         [ | IFTRUE/IFFALSE ( ... ) ]
+**	<<ident>>
+**
+**	Conditions:
+**	     WHEN (phase)
+**	     IF   (phase)
+**	     CARRYSET
+**	     DATA (data, mask)
+**
+**-----------------------------------------------------------
+*/
+
+#define SCR_NO_OP       0x80000000
+#define SCR_JUMP        0x80080000
+#define SCR_JUMP64      0x80480000
+#define SCR_JUMPR       0x80880000
+#define SCR_CALL        0x88080000
+#define SCR_CALLR       0x88880000
+#define SCR_RETURN      0x90080000
+#define SCR_INT         0x98080000
+#define SCR_INT_FLY     0x98180000
+
+#define IFFALSE(arg)   (0x00080000 | (arg))
+#define IFTRUE(arg)    (0x00000000 | (arg))
+
+#define WHEN(phase)    (0x00030000 | (phase))
+#define IF(phase)      (0x00020000 | (phase))
+
+#define DATA(D)        (0x00040000 | ((D) & 0xff))
+#define MASK(D,M)      (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff))
+
+#define CARRYSET       (0x00200000)
+
+
+#define SIR_COMPLETE					 0x10000000
+/* script errors */
+#define SIR_SEL_ATN_NO_MSG_OUT 0x00000001
+#define SIR_CMD_OUT_ILL_PH     0x00000002
+#define SIR_STATUS_ILL_PH			 0x00000003
+#define SIR_MSG_RECEIVED			 0x00000004
+#define SIR_DATA_IN_ERR        0x00000005
+#define SIR_DATA_OUT_ERR			 0x00000006
+#define SIR_SCRIPT_ERROR			 0x00000007
+#define SIR_MSG_OUT_NO_CMD		 0x00000008
+#define SIR_MSG_OVER7					 0x00000009
+/* Fly interrupt */
+#define INT_ON_FY							 0x00000080
+
+/* Hardware errors  are defined in scsi.h */
+
+#define SCSI_IDENTIFY					0xC0
+
+#endif
diff --git a/qemu/roms/u-boot/include/synopsys/dwcddr21mctl.h b/qemu/roms/u-boot/include/synopsys/dwcddr21mctl.h
new file mode 100644
index 000000000..5576dbf2a
--- /dev/null
+++ b/qemu/roms/u-boot/include/synopsys/dwcddr21mctl.h
@@ -0,0 +1,325 @@
+/*
+ * (C) Copyright 2011 Andes Technology Corp
+ * Macpaul Lin <macpaul@andestech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * DWCDDR21MCTL - Synopsys DWC DDR2/DDR1 Memory Controller
+ */
+#ifndef __DWCDDR21MCTL_H
+#define __DWCDDR21MCTL_H
+
+#ifndef __ASSEMBLY__
+struct dwcddr21mctl {
+	unsigned int	ccr;		/* Controller Configuration */
+	unsigned int	dcr;		/* DRAM Configuration */
+	unsigned int	iocr;		/* I/O Configuration */
+	unsigned int	csr;		/* Controller Status */
+	unsigned int	drr;		/* DRAM refresh */
+	unsigned int	tpr0;		/* SDRAM Timing Parameters 0 */
+	unsigned int	tpr1;		/* SDRAM Timing Parameters 1 */
+	unsigned int	tpr2;		/* SDRAM Timing Parameters 2 */
+	unsigned int	gdllcr;		/* Global DLL Control */
+	unsigned int	dllcr[10];	/* DLL Control */
+	unsigned int	rslr[4];	/* Rank System Lantency */
+	unsigned int	rdgr[4];	/* Rank DQS Gating */
+	unsigned int	dqtr[9];	/* DQ Timing */
+	unsigned int	dqstr;		/* DQS Timing */
+	unsigned int	dqsbtr;		/* DQS_b Timing */
+	unsigned int	odtcr;		/* ODT Configuration */
+	unsigned int	dtr[2];		/* Data Training */
+	unsigned int	dtar;		/* Data Training Address */
+	unsigned int	rsved[82];	/* Reserved */
+	unsigned int	mr;		/* Mode Register */
+	unsigned int	emr;		/* Extended Mode Register */
+	unsigned int	emr2;		/* Extended Mode Register 2 */
+	unsigned int	emr3;		/* Extended Mode Register 3 */
+	unsigned int	hpcr[32];	/* Host Port Configurarion */
+	unsigned int	pqcr[8];	/* Priority Queue Configuration */
+	unsigned int	mmgcr;		/* Memory Manager General Config */
+};
+#endif /* __ASSEMBLY__ */
+
+/*
+ * Control Configuration Register
+ */
+#define DWCDDR21MCTL_CCR_ECCEN(x)	((x) << 0)
+#define DWCDDR21MCTL_CCR_NOMRWR(x)	((x) << 1)
+#define DWCDDR21MCTL_CCR_HOSTEN(x)	((x) << 2)
+#define DWCDDR21MCTL_CCR_XBISC(x)	((x) << 3)
+#define DWCDDR21MCTL_CCR_NOAPD(x)	((x) << 4)
+#define DWCDDR21MCTL_CCR_RRB(x)		((x) << 13)
+#define DWCDDR21MCTL_CCR_DQSCFG(x)	((x) << 14)
+#define DWCDDR21MCTL_CCR_DFTLM(x)	(((x) & 0x3) << 15)
+#define DWCDDR21MCTL_CCR_DFTCMP(x)	((x) << 17)
+#define DWCDDR21MCTL_CCR_FLUSH(x)	((x) << 27)
+#define DWCDDR21MCTL_CCR_ITMRST(x)	((x) << 28)
+#define DWCDDR21MCTL_CCR_IB(x)		((x) << 29)
+#define DWCDDR21MCTL_CCR_DTT(x)		((x) << 30)
+#define DWCDDR21MCTL_CCR_IT(x)		((x) << 31)
+
+/*
+ * DRAM Configuration Register
+ */
+#define DWCDDR21MCTL_DCR_DDRMD(x)	((x) << 0)
+#define DWCDDR21MCTL_DCR_DIO(x)		(((x) & 0x3) << 1)
+#define DWCDDR21MCTL_DCR_DSIZE(x)	(((x) & 0x7) << 3)
+#define DWCDDR21MCTL_DCR_SIO(x)		(((x) & 0x7) << 6)
+#define DWCDDR21MCTL_DCR_PIO(x)		((x) << 9)
+#define DWCDDR21MCTL_DCR_RANKS(x)	(((x) & 0x3) << 10)
+#define DWCDDR21MCTL_DCR_RNKALL(x)	((x) << 12)
+#define DWCDDR21MCTL_DCR_AMAP(x)	(((x) & 0x3) << 13)
+#define DWCDDR21MCTL_DCR_RANK(x)	(((x) & 0x3) << 25)
+#define DWCDDR21MCTL_DCR_CMD(x)		(((x) & 0xf) << 27)
+#define DWCDDR21MCTL_DCR_EXE(x)		((x) << 31)
+
+/*
+ * I/O Configuration Register
+ */
+#define DWCDDR21MCTL_IOCR_RTT(x)	(((x) & 0xf) << 0)
+#define DWCDDR21MCTL_IOCR_DS(x)		(((x) & 0xf) << 4)
+#define DWCDDR21MCTL_IOCR_TESTEN(x)	((x) << 0x8)
+#define DWCDDR21MCTL_IOCR_RTTOH(x)	(((x) & 0x7) << 26)
+#define DWCDDR21MCTL_IOCR_RTTOE(x)	((x) << 29)
+#define DWCDDR21MCTL_IOCR_DQRTT(x)	((x) << 30)
+#define DWCDDR21MCTL_IOCR_DQSRTT(x)	((x) << 31)
+
+/*
+ * Controller Status Register
+ */
+#define DWCDDR21MCTL_CSR_DRIFT(x)	(((x) & 0x3ff) << 0)
+#define DWCDDR21MCTL_CSR_DFTERR(x)	((x) << 18)
+#define DWCDDR21MCTL_CSR_ECCERR(x)	((x) << 19)
+#define DWCDDR21MCTL_CSR_DTERR(x)	((x) << 20)
+#define DWCDDR21MCTL_CSR_DTIERR(x)	((x) << 21)
+#define DWCDDR21MCTL_CSR_ECCSEC(x)	((x) << 22)
+
+/*
+ * DRAM Refresh Register
+ */
+#define DWCDDR21MCTL_DRR_TRFC(x)	(((x) & 0xff) << 0)
+#define DWCDDR21MCTL_DRR_TRFPRD(x)	(((x) & 0xffff) << 8)
+#define DWCDDR21MCTL_DRR_RFBURST(x)	(((x) & 0xf) << 24)
+#define DWCDDR21MCTL_DRR_RD(x)		((x) << 31)
+
+/*
+ * SDRAM Timing Parameters Register 0
+ */
+#define DWCDDR21MCTL_TPR0_TMRD(x)	(((x) & 0x3) << 0)
+#define DWCDDR21MCTL_TPR0_TRTP(x)	(((x) & 0x7) << 2)
+#define DWCDDR21MCTL_TPR0_TWTR(x)	(((x) & 0x7) << 5)
+#define DWCDDR21MCTL_TPR0_TRP(x)	(((x) & 0xf) << 8)
+#define DWCDDR21MCTL_TPR0_TRCD(x)	(((x) & 0xf) << 12)
+#define DWCDDR21MCTL_TPR0_TRAS(x)	(((x) & 0x1f) << 16)
+#define DWCDDR21MCTL_TPR0_TRRD(x)	(((x) & 0xf) << 21)
+#define DWCDDR21MCTL_TPR0_TRC(x)	(((x) & 0x3f) << 25)
+#define DWCDDR21MCTL_TPR0_TCCD(x)	((x) << 31)
+
+/*
+ * SDRAM Timing Parameters Register 1
+ */
+#define DWCDDR21MCTL_TPR1_TAOND(x)	(((x) & 0x3) << 0)
+#define DWCDDR21MCTL_TPR1_TRTW(x)	((x) << 2)
+#define DWCDDR21MCTL_TPR1_TFAW(x)	(((x) & 0x3f) << 3)
+#define DWCDDR21MCTL_TPR1_TRNKRTR(x)	(((x) & 0x3) << 12)
+#define DWCDDR21MCTL_TPR1_TRNKWTW(x)	(((x) & 0x3) << 14)
+#define DWCDDR21MCTL_TPR1_XCL(x)	(((x) & 0xf) << 23)
+#define DWCDDR21MCTL_TPR1_XWR(x)	(((x) & 0xf) << 27)
+#define DWCDDR21MCTL_TPR1_XTP(x)	((x) << 31)
+
+/*
+ * SDRAM Timing Parameters Register 2
+ */
+#define DWCDDR21MCTL_TPR2_TXS(x)	(((x) & 0x3ff) << 0)
+#define DWCDDR21MCTL_TPR2_TXP(x)	(((x) & 0x1f) << 10)
+#define DWCDDR21MCTL_TPR2_TCKE(x)	(((x) & 0xf) << 15)
+
+/*
+ * Global DLL Control Register
+ */
+#define DWCDDR21MCTL_GDLLCR_DRES(x)	(((x) & 0x3) << 0)
+#define DWCDDR21MCTL_GDLLCR_IPUMP(x)	(((x) & 0x7) << 2)
+#define DWCDDR21MCTL_GDLLCR_TESTEN(x)	((x) << 5)
+#define DWCDDR21MCTL_GDLLCR_DTC(x)	(((x) & 0x7) << 6)
+#define DWCDDR21MCTL_GDLLCR_ATC(x)	(((x) & 0x3) << 9)
+#define DWCDDR21MCTL_GDLLCR_TESTSW(x)	((x) << 11)
+#define DWCDDR21MCTL_GDLLCR_MBIAS(x)	(((x) & 0xff) << 12)
+#define DWCDDR21MCTL_GDLLCR_SBIAS(x)	(((x) & 0xff) << 20)
+#define DWCDDR21MCTL_GDLLCR_LOCKDET(x)	((x) << 29)
+
+/*
+ * DLL Control Register 0-9
+ */
+#define DWCDDR21MCTL_DLLCR_SFBDLY(x)	(((x) & 0x7) << 0)
+#define DWCDDR21MCTL_DLLCR_SFWDLY(x)	(((x) & 0x7) << 3)
+#define DWCDDR21MCTL_DLLCR_MFBDLY(x)	(((x) & 0x7) << 6)
+#define DWCDDR21MCTL_DLLCR_MFWDLY(x)	(((x) & 0x7) << 9)
+#define DWCDDR21MCTL_DLLCR_SSTART(x)	(((x) & 0x3) << 12)
+#define DWCDDR21MCTL_DLLCR_PHASE(x)	(((x) & 0xf) << 14)
+#define DWCDDR21MCTL_DLLCR_ATESTEN(x)	((x) << 18)
+#define DWCDDR21MCTL_DLLCR_DRSVD(x)	((x) << 19)
+#define DWCDDR21MCTL_DLLCR_DD(x)	((x) << 31)
+
+/*
+ * Rank System Lantency Register
+ */
+#define DWCDDR21MCTL_RSLR_SL0(x)	(((x) & 0x7) << 0)
+#define DWCDDR21MCTL_RSLR_SL1(x)	(((x) & 0x7) << 3)
+#define DWCDDR21MCTL_RSLR_SL2(x)	(((x) & 0x7) << 6)
+#define DWCDDR21MCTL_RSLR_SL3(x)	(((x) & 0x7) << 9)
+#define DWCDDR21MCTL_RSLR_SL4(x)	(((x) & 0x7) << 12)
+#define DWCDDR21MCTL_RSLR_SL5(x)	(((x) & 0x7) << 15)
+#define DWCDDR21MCTL_RSLR_SL6(x)	(((x) & 0x7) << 18)
+#define DWCDDR21MCTL_RSLR_SL7(x)	(((x) & 0x7) << 21)
+#define DWCDDR21MCTL_RSLR_SL8(x)	(((x) & 0x7) << 24)
+
+/*
+ * Rank DQS Gating Register
+ */
+#define DWCDDR21MCTL_RDGR_DQSSEL0(x)	(((x) & 0x3) << 0)
+#define DWCDDR21MCTL_RDGR_DQSSEL1(x)	(((x) & 0x3) << 2)
+#define DWCDDR21MCTL_RDGR_DQSSEL2(x)	(((x) & 0x3) << 4)
+#define DWCDDR21MCTL_RDGR_DQSSEL3(x)	(((x) & 0x3) << 6)
+#define DWCDDR21MCTL_RDGR_DQSSEL4(x)	(((x) & 0x3) << 8)
+#define DWCDDR21MCTL_RDGR_DQSSEL5(x)	(((x) & 0x3) << 10)
+#define DWCDDR21MCTL_RDGR_DQSSEL6(x)	(((x) & 0x3) << 12)
+#define DWCDDR21MCTL_RDGR_DQSSEL7(x)	(((x) & 0x3) << 14)
+#define DWCDDR21MCTL_RDGR_DQSSEL8(x)	(((x) & 0x3) << 16)
+
+/*
+ * DQ Timing Register
+ */
+#define DWCDDR21MCTL_DQTR_DQDLY0(x)	(((x) & 0xf) << 0)
+#define DWCDDR21MCTL_DQTR_DQDLY1(x)	(((x) & 0xf) << 4)
+#define DWCDDR21MCTL_DQTR_DQDLY2(x)	(((x) & 0xf) << 8)
+#define DWCDDR21MCTL_DQTR_DQDLY3(x)	(((x) & 0xf) << 12)
+#define DWCDDR21MCTL_DQTR_DQDLY4(x)	(((x) & 0xf) << 16)
+#define DWCDDR21MCTL_DQTR_DQDLY5(x)	(((x) & 0xf) << 20)
+#define DWCDDR21MCTL_DQTR_DQDLY6(x)	(((x) & 0xf) << 24)
+#define DWCDDR21MCTL_DQTR_DQDLY7(x)	(((x) & 0xf) << 28)
+
+/*
+ * DQS Timing Register
+ */
+#define DWCDDR21MCTL_DQSTR_DQSDLY0(x)	(((x) & 0x7) << 0)
+#define DWCDDR21MCTL_DQSTR_DQSDLY1(x)	(((x) & 0x7) << 3)
+#define DWCDDR21MCTL_DQSTR_DQSDLY2(x)	(((x) & 0x7) << 6)
+#define DWCDDR21MCTL_DQSTR_DQSDLY3(x)	(((x) & 0x7) << 9)
+#define DWCDDR21MCTL_DQSTR_DQSDLY4(x)	(((x) & 0x7) << 12)
+#define DWCDDR21MCTL_DQSTR_DQSDLY5(x)	(((x) & 0x7) << 15)
+#define DWCDDR21MCTL_DQSTR_DQSDLY6(x)	(((x) & 0x7) << 18)
+#define DWCDDR21MCTL_DQSTR_DQSDLY7(x)	(((x) & 0x7) << 21)
+#define DWCDDR21MCTL_DQSTR_DQSDLY8(x)	(((x) & 0x7) << 24)
+
+/*
+ * DQS_b (DQSBTR) Timing Register
+ */
+#define DWCDDR21MCTL_DQSBTR_DQSDLY0(x)	(((x) & 0x7) << 0)
+#define DWCDDR21MCTL_DQSBTR_DQSDLY1(x)	(((x) & 0x7) << 3)
+#define DWCDDR21MCTL_DQSBTR_DQSDLY2(x)	(((x) & 0x7) << 6)
+#define DWCDDR21MCTL_DQSBTR_DQSDLY3(x)	(((x) & 0x7) << 9)
+#define DWCDDR21MCTL_DQSBTR_DQSDLY4(x)	(((x) & 0x7) << 12)
+#define DWCDDR21MCTL_DQSBTR_DQSDLY5(x)	(((x) & 0x7) << 15)
+#define DWCDDR21MCTL_DQSBTR_DQSDLY6(x)	(((x) & 0x7) << 18)
+#define DWCDDR21MCTL_DQSBTR_DQSDLY7(x)	(((x) & 0x7) << 21)
+#define DWCDDR21MCTL_DQSBTR_DQSDLY8(x)	(((x) & 0x7) << 24)
+
+/*
+ * ODT Configuration Register
+ */
+#define DWCDDR21MCTL_ODTCR_RDODT0(x)	(((x) & 0xf) << 0)
+#define DWCDDR21MCTL_ODTCR_RDODT1(x)	(((x) & 0xf) << 4)
+#define DWCDDR21MCTL_ODTCR_RDODT2(x)	(((x) & 0xf) << 8)
+#define DWCDDR21MCTL_ODTCR_RDODT3(x)	(((x) & 0xf) << 12)
+#define DWCDDR21MCTL_ODTCR_WDODT0(x)	(((x) & 0xf) << 16)
+#define DWCDDR21MCTL_ODTCR_WDODT1(x)	(((x) & 0xf) << 20)
+#define DWCDDR21MCTL_ODTCR_WDODT2(x)	(((x) & 0xf) << 24)
+#define DWCDDR21MCTL_ODTCR_WDODT3(x)	(((x) & 0xf) << 28)
+
+/*
+ * Data Training Register
+ */
+#define DWCDDR21MCTL_DTR0_DTBYTE0(x)	(((x) & 0xff) << 0)	/* def: 0x11 */
+#define DWCDDR21MCTL_DTR0_DTBYTE1(x)	(((x) & 0xff) << 8)	/* def: 0xee */
+#define DWCDDR21MCTL_DTR0_DTBYTE2(x)	(((x) & 0xff) << 16)	/* def: 0x22 */
+#define DWCDDR21MCTL_DTR0_DTBYTE3(x)	(((x) & 0xff) << 24)	/* def: 0xdd */
+
+#define DWCDDR21MCTL_DTR1_DTBYTE4(x)	(((x) & 0xff) << 0)	/* def: 0x44 */
+#define DWCDDR21MCTL_DTR1_DTBYTE5(x)	(((x) & 0xff) << 8)	/* def: 0xbb */
+#define DWCDDR21MCTL_DTR1_DTBYTE6(x)	(((x) & 0xff) << 16)	/* def: 0x88 */
+#define DWCDDR21MCTL_DTR1_DTBYTE7(x)	(((x) & 0xff) << 24)	/* def: 0x77 */
+
+/*
+ * Data Training Address Register
+ */
+#define DWCDDR21MCTL_DTAR_DTCOL(x)	(((x) & 0xfff) << 0)
+#define DWCDDR21MCTL_DTAR_DTROW(x)	(((x) & 0xffff) << 12)
+#define DWCDDR21MCTL_DTAR_DTBANK(x)	(((x) & 0x7) << 28)
+
+/*
+ * Mode Register
+ */
+#define DWCDDR21MCTL_MR_BL(x)		(((x) & 0x7) << 0)
+#define DWCDDR21MCTL_MR_BT(x)		((x) << 3)
+#define DWCDDR21MCTL_MR_CL(x)		(((x) & 0x7) << 4)
+#define DWCDDR21MCTL_MR_TM(x)		((x) << 7)
+#define DWCDDR21MCTL_MR_DR(x)		((x) << 8)
+#define DWCDDR21MCTL_MR_WR(x)		(((x) & 0x7) << 9)
+#define DWCDDR21MCTL_MR_PD(x)		((x) << 12)
+
+/*
+ * Extended Mode register
+ */
+#define DWCDDR21MCTL_EMR_DE(x)		((x) << 0)
+#define DWCDDR21MCTL_EMR_ODS(x)		((x) << 1)
+#define DWCDDR21MCTL_EMR_RTT2(x)	((x) << 2)
+#define DWCDDR21MCTL_EMR_AL(x)		(((x) & 0x7) << 3)
+#define DWCDDR21MCTL_EMR_RTT6(x)	((x) << 6)
+#define DWCDDR21MCTL_EMR_OCD(x)		(((x) & 0x7) << 7)
+#define DWCDDR21MCTL_EMR_DQS(x)		((x) << 10)
+#define DWCDDR21MCTL_EMR_RDQS(x)	((x) << 11)
+#define DWCDDR21MCTL_EMR_OE(x)		((x) << 12)
+
+#define EMR_RTT2(x)			DWCDDR21MCTL_EMR_RTT2(x)
+#define EMR_RTT6(x)			DWCDDR21MCTL_EMR_RTT6(x)
+
+#define DWCDDR21MCTL_EMR_RTT_DISABLED	(EMR_RTT6(0) | EMR_RTT2(0))
+#define DWCDDR21MCTL_EMR_RTT_75		(EMR_RTT6(0) | EMR_RTT2(1))
+#define DWCDDR21MCTL_EMR_RTT_150	(EMR_RTT6(1) | EMR_RTT2(0))
+#define DWCDDR21MCTL_EMR_RTT_50		(EMR_RTT6(1) | EMR_RTT2(1))
+
+/*
+ * Extended Mode register 2
+ */
+#define DWCDDR21MCTL_EMR2_PASR(x)	(((x) & 0x7) << 0)
+#define DWCDDR21MCTL_EMR2_DCC(x)	((x) << 3)
+#define DWCDDR21MCTL_EMR2_SRF(x)	((x) << 7)
+
+/*
+ * Extended Mode register 3: [15:0] reserved for JEDEC.
+ */
+
+/*
+ * Host port Configuration register 0-31
+ */
+#define DWCDDR21MCTL_HPCR_HPBL(x)	(((x) & 0xf) << 0)
+
+/*
+ * Priority Queue Configuration register 0-7
+ */
+#define DWCDDR21MCTL_HPCR_TOUT(x)	(((x) & 0xf) << 0)
+#define DWCDDR21MCTL_HPCR_TOUTX(x)	(((x) & 0x3) << 8)
+#define DWCDDR21MCTL_HPCR_LPQS(x)	(((x) & 0x3) << 10)
+#define DWCDDR21MCTL_HPCR_PQBL(x)	(((x) & 0xff) << 12)
+#define DWCDDR21MCTL_HPCR_SWAIT(x)	(((x) & 0x1f) << 20)
+#define DWCDDR21MCTL_HPCR_INTRPT(x)	(((x) & 0x7) << 25)
+#define DWCDDR21MCTL_HPCR_APQS(x)	((x) << 28)
+
+/*
+ * Memory Manager General Configuration register
+ */
+#define DWCDDR21MCTL_MMGCR_UHPP(x)	(((x) & 0x3) << 0)
+
+#endif	/* __DWCDDR21MCTL_H */
diff --git a/qemu/roms/u-boot/include/systemace.h b/qemu/roms/u-boot/include/systemace.h
new file mode 100644
index 000000000..73affc42b
--- /dev/null
+++ b/qemu/roms/u-boot/include/systemace.h
@@ -0,0 +1,18 @@
+#ifndef __SYSTEMACE_H
+#define __SYSTEMACE_H
+/*
+ * Copyright (c) 2004 Picture Elements, Inc.
+ *    Stephen Williams (steve@picturel.com)
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ident "$Id:$"
+
+#ifdef CONFIG_SYSTEMACE
+
+# include  <part.h>
+
+block_dev_desc_t *  systemace_get_dev(int dev);
+
+#endif	/* CONFIG_SYSTEMACE */
+#endif	/* __SYSTEMACE_H */
diff --git a/qemu/roms/u-boot/include/tca642x.h b/qemu/roms/u-boot/include/tca642x.h
new file mode 100644
index 000000000..bda86c1ed
--- /dev/null
+++ b/qemu/roms/u-boot/include/tca642x.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright 2013 Texas Instruments, Inc.
+ * Author: Dan Murphy <dmurphy@ti.com>
+ *
+ * Derived work from the pca953x.c driver
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __TCA642X_H_
+#define __TCA642X_H_
+
+#ifdef CONFIG_CMD_TCA642X
+enum {
+	TCA642X_CMD_INFO,
+	TCA642X_CMD_DEVICE,
+	TCA642X_CMD_OUTPUT,
+	TCA642X_CMD_INPUT,
+	TCA642X_CMD_INVERT,
+};
+#endif
+
+#define TCA642X_OUT_LOW		0
+#define TCA642X_OUT_HIGH	1
+#define TCA642X_POL_NORMAL	0
+#define TCA642X_POL_INVERT	1
+#define TCA642X_DIR_OUT		0
+#define TCA642X_DIR_IN		1
+
+/* Default to an address that hopefully won't corrupt other i2c devices */
+#ifndef CONFIG_SYS_I2C_TCA642X_ADDR
+#define CONFIG_SYS_I2C_TCA642X_ADDR	(~0)
+#endif
+
+/* Default to an address that hopefully won't corrupt other i2c devices */
+#ifndef CONFIG_SYS_I2C_TCA642X_BUS_NUM
+#define CONFIG_SYS_I2C_TCA642X_BUS_NUM	(0)
+#endif
+
+struct tca642x_bank_info {
+	uint8_t input_reg;
+	uint8_t output_reg;
+	uint8_t polarity_reg;
+	uint8_t configuration_reg;
+};
+
+int tca642x_set_val(uchar chip, uint8_t gpio_bank,
+			uint8_t reg_bit, uint8_t data);
+int tca642x_set_pol(uchar chip, uint8_t gpio_bank,
+			uint8_t reg_bit, uint8_t data);
+int tca642x_set_dir(uchar chip, uint8_t gpio_bank,
+			uint8_t reg_bit, uint8_t data);
+int tca642x_get_val(uchar chip, uint8_t gpio_bank);
+int tca642x_set_inital_state(uchar chip, struct tca642x_bank_info init_data[]);
+
+#endif /* __TCA642X_H_ */
diff --git a/qemu/roms/u-boot/include/tegra-kbc.h b/qemu/roms/u-boot/include/tegra-kbc.h
new file mode 100644
index 000000000..f331c79c9
--- /dev/null
+++ b/qemu/roms/u-boot/include/tegra-kbc.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __include_tegra_kbc_h__
+#define __include_tegra_kbc_h__
+
+#include <common.h>
+
+#define KEY_IS_MODIFIER(key) ((key) >= KEY_FIRST_MODIFIER)
+
+struct kbc_tegra {
+	u32 control;
+	u32 interrupt;
+	u32 row_cfg[4];
+	u32 col_cfg[3];
+	u32 timeout_dly;
+	u32 init_dly;
+	u32 rpt_dly;
+	u32 kp_ent[2];
+	u32 row_mask[16];
+};
+
+#ifdef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+extern int overwrite_console(void);
+#define OVERWRITE_CONSOLE overwrite_console()
+#else
+#define OVERWRITE_CONSOLE 0
+#endif /* CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE */
+
+#endif /* __include_tegra_kbc_h__ */
diff --git a/qemu/roms/u-boot/include/thor.h b/qemu/roms/u-boot/include/thor.h
new file mode 100644
index 000000000..5051be714
--- /dev/null
+++ b/qemu/roms/u-boot/include/thor.h
@@ -0,0 +1,19 @@
+/*
+ * thor.h -- USB THOR Downloader protocol
+ *
+ * Copyright (C) 2013 Samsung Electronics
+ * Lukasz Majewski  <l.majewski@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ */
+
+#ifndef __THOR_H_
+#define __THOR_H_
+
+#include <linux/usb/composite.h>
+
+int thor_handle(void);
+int thor_init(void);
+int thor_add(struct usb_configuration *c);
+#endif /* __THOR_H_ */
diff --git a/qemu/roms/u-boot/include/timestamp.h b/qemu/roms/u-boot/include/timestamp.h
new file mode 100644
index 000000000..e2c0f0696
--- /dev/null
+++ b/qemu/roms/u-boot/include/timestamp.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef	__TIMESTAMP_H__
+#define	__TIMESTAMP_H__
+
+#ifndef DO_DEPS_ONLY
+#include "generated/timestamp_autogenerated.h"
+#endif
+
+#endif	/* __TIMESTAMP_H__ */
diff --git a/qemu/roms/u-boot/include/tis.h b/qemu/roms/u-boot/include/tis.h
new file mode 100644
index 000000000..40a1f8676
--- /dev/null
+++ b/qemu/roms/u-boot/include/tis.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __TIS_H
+#define __TIS_H
+
+#include <common.h>
+
+/* Low-level interface to access TPM */
+
+/*
+ * tis_init()
+ *
+ * Initialize the TPM device. Returns 0 on success or -1 on
+ * failure (in case device probing did not succeed).
+ */
+int tis_init(void);
+
+/*
+ * tis_open()
+ *
+ * Requests access to locality 0 for the caller. After all commands have been
+ * completed the caller is supposed to call tis_close().
+ *
+ * Returns 0 on success, -1 on failure.
+ */
+int tis_open(void);
+
+/*
+ * tis_close()
+ *
+ * terminate the currect session with the TPM by releasing the locked
+ * locality. Returns 0 on success of -1 on failure (in case lock
+ * removal did not succeed).
+ */
+int tis_close(void);
+
+/*
+ * tis_sendrecv()
+ *
+ * Send the requested data to the TPM and then try to get its response
+ *
+ * @sendbuf - buffer of the data to send
+ * @send_size size of the data to send
+ * @recvbuf - memory to save the response to
+ * @recv_len - pointer to the size of the response buffer
+ *
+ * Returns 0 on success (and places the number of response bytes at recv_len)
+ * or -1 on failure.
+ */
+int tis_sendrecv(const uint8_t *sendbuf, size_t send_size, uint8_t *recvbuf,
+			size_t *recv_len);
+
+#endif /* __TIS_H */
diff --git a/qemu/roms/u-boot/include/tmu.h b/qemu/roms/u-boot/include/tmu.h
new file mode 100644
index 000000000..da07a2211
--- /dev/null
+++ b/qemu/roms/u-boot/include/tmu.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *      http://www.samsung.com
+ * Akshay Saraswat <akshay.s@samsung.com>
+ *
+ * Thermal Management Unit
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TMU_H
+#define _TMU_H
+
+enum tmu_status_t {
+	TMU_STATUS_INIT = -1,
+	TMU_STATUS_NORMAL = 0,
+	TMU_STATUS_WARNING,
+	TMU_STATUS_TRIPPED,
+};
+
+/*
+ * Monitors status of the TMU device and exynos temperature
+ *
+ * @param temp	pointer to the current temperature value
+ * @return	enum tmu_status_t value, code indicating event to execute
+ *		and -1 on error
+ */
+enum tmu_status_t tmu_monitor(int *temp);
+
+/*
+ * Initialize TMU device
+ *
+ * @param blob  FDT blob
+ * @return	int value, 0 for success
+ */
+int tmu_init(const void *blob);
+#endif	/* _THERMAL_H_ */
diff --git a/qemu/roms/u-boot/include/tpm.h b/qemu/roms/u-boot/include/tpm.h
new file mode 100644
index 000000000..88aeba28e
--- /dev/null
+++ b/qemu/roms/u-boot/include/tpm.h
@@ -0,0 +1,362 @@
+/*
+ * Copyright (c) 2013 The Chromium OS Authors.
+ * Coypright (c) 2013 Guntermann & Drunck GmbH
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __TPM_H
+#define __TPM_H
+
+#include <tis.h>
+
+/*
+ * Here is a partial implementation of TPM commands.  Please consult TCG Main
+ * Specification for definitions of TPM commands.
+ */
+
+enum tpm_startup_type {
+	TPM_ST_CLEAR		= 0x0001,
+	TPM_ST_STATE		= 0x0002,
+	TPM_ST_DEACTIVATED	= 0x0003,
+};
+
+enum tpm_physical_presence {
+	TPM_PHYSICAL_PRESENCE_HW_DISABLE	= 0x0200,
+	TPM_PHYSICAL_PRESENCE_CMD_DISABLE	= 0x0100,
+	TPM_PHYSICAL_PRESENCE_LIFETIME_LOCK	= 0x0080,
+	TPM_PHYSICAL_PRESENCE_HW_ENABLE		= 0x0040,
+	TPM_PHYSICAL_PRESENCE_CMD_ENABLE	= 0x0020,
+	TPM_PHYSICAL_PRESENCE_NOTPRESENT	= 0x0010,
+	TPM_PHYSICAL_PRESENCE_PRESENT		= 0x0008,
+	TPM_PHYSICAL_PRESENCE_LOCK		= 0x0004,
+};
+
+enum tpm_nv_index {
+	TPM_NV_INDEX_LOCK	= 0xffffffff,
+	TPM_NV_INDEX_0		= 0x00000000,
+	TPM_NV_INDEX_DIR	= 0x10000001,
+};
+
+/**
+ * TPM return codes as defined in the TCG Main specification
+ * (TPM Main Part 2 Structures; Specification version 1.2)
+ */
+enum tpm_return_code {
+	TPM_BASE	= 0x00000000,
+	TPM_NON_FATAL	= 0x00000800,
+	TPM_SUCCESS	= TPM_BASE,
+	/* TPM-defined fatal error codes */
+	TPM_AUTHFAIL			= TPM_BASE +  1,
+	TPM_BADINDEX			= TPM_BASE +  2,
+	TPM_BAD_PARAMETER		= TPM_BASE +  3,
+	TPM_AUDITFAILURE		= TPM_BASE +  4,
+	TPM_CLEAR_DISABLED		= TPM_BASE +  5,
+	TPM_DEACTIVATED			= TPM_BASE +  6,
+	TPM_DISABLED			= TPM_BASE +  7,
+	TPM_DISABLED_CMD		= TPM_BASE +  8,
+	TPM_FAIL			= TPM_BASE +  9,
+	TPM_BAD_ORDINAL			= TPM_BASE + 10,
+	TPM_INSTALL_DISABLED		= TPM_BASE + 11,
+	TPM_INVALID_KEYHANDLE		= TPM_BASE + 12,
+	TPM_KEYNOTFOUND			= TPM_BASE + 13,
+	TPM_INAPPROPRIATE_ENC		= TPM_BASE + 14,
+	TPM_MIGRATE_FAIL		= TPM_BASE + 15,
+	TPM_INVALID_PCR_INFO		= TPM_BASE + 16,
+	TPM_NOSPACE			= TPM_BASE + 17,
+	TPM_NOSRK			= TPM_BASE + 18,
+	TPM_NOTSEALED_BLOB		= TPM_BASE + 19,
+	TPM_OWNER_SET			= TPM_BASE + 20,
+	TPM_RESOURCES			= TPM_BASE + 21,
+	TPM_SHORTRANDOM			= TPM_BASE + 22,
+	TPM_SIZE			= TPM_BASE + 23,
+	TPM_WRONGPCRVAL			= TPM_BASE + 24,
+	TPM_BAD_PARAM_SIZE		= TPM_BASE + 25,
+	TPM_SHA_THREAD			= TPM_BASE + 26,
+	TPM_SHA_ERROR			= TPM_BASE + 27,
+	TPM_FAILEDSELFTEST		= TPM_BASE + 28,
+	TPM_AUTH2FAIL			= TPM_BASE + 29,
+	TPM_BADTAG			= TPM_BASE + 30,
+	TPM_IOERROR			= TPM_BASE + 31,
+	TPM_ENCRYPT_ERROR		= TPM_BASE + 32,
+	TPM_DECRYPT_ERROR		= TPM_BASE + 33,
+	TPM_INVALID_AUTHHANDLE		= TPM_BASE + 34,
+	TPM_NO_ENDORSEMENT		= TPM_BASE + 35,
+	TPM_INVALID_KEYUSAGE		= TPM_BASE + 36,
+	TPM_WRONG_ENTITYTYPE		= TPM_BASE + 37,
+	TPM_INVALID_POSTINIT		= TPM_BASE + 38,
+	TPM_INAPPROPRIATE_SIG		= TPM_BASE + 39,
+	TPM_BAD_KEY_PROPERTY		= TPM_BASE + 40,
+	TPM_BAD_MIGRATION		= TPM_BASE + 41,
+	TPM_BAD_SCHEME			= TPM_BASE + 42,
+	TPM_BAD_DATASIZE		= TPM_BASE + 43,
+	TPM_BAD_MODE			= TPM_BASE + 44,
+	TPM_BAD_PRESENCE		= TPM_BASE + 45,
+	TPM_BAD_VERSION			= TPM_BASE + 46,
+	TPM_NO_WRAP_TRANSPORT		= TPM_BASE + 47,
+	TPM_AUDITFAIL_UNSUCCESSFUL	= TPM_BASE + 48,
+	TPM_AUDITFAIL_SUCCESSFUL	= TPM_BASE + 49,
+	TPM_NOTRESETABLE		= TPM_BASE + 50,
+	TPM_NOTLOCAL			= TPM_BASE + 51,
+	TPM_BAD_TYPE			= TPM_BASE + 52,
+	TPM_INVALID_RESOURCE		= TPM_BASE + 53,
+	TPM_NOTFIPS			= TPM_BASE + 54,
+	TPM_INVALID_FAMILY		= TPM_BASE + 55,
+	TPM_NO_NV_PERMISSION		= TPM_BASE + 56,
+	TPM_REQUIRES_SIGN		= TPM_BASE + 57,
+	TPM_KEY_NOTSUPPORTED		= TPM_BASE + 58,
+	TPM_AUTH_CONFLICT		= TPM_BASE + 59,
+	TPM_AREA_LOCKED			= TPM_BASE + 60,
+	TPM_BAD_LOCALITY		= TPM_BASE + 61,
+	TPM_READ_ONLY			= TPM_BASE + 62,
+	TPM_PER_NOWRITE			= TPM_BASE + 63,
+	TPM_FAMILY_COUNT		= TPM_BASE + 64,
+	TPM_WRITE_LOCKED		= TPM_BASE + 65,
+	TPM_BAD_ATTRIBUTES		= TPM_BASE + 66,
+	TPM_INVALID_STRUCTURE		= TPM_BASE + 67,
+	TPM_KEY_OWNER_CONTROL		= TPM_BASE + 68,
+	TPM_BAD_COUNTER			= TPM_BASE + 69,
+	TPM_NOT_FULLWRITE		= TPM_BASE + 70,
+	TPM_CONTEXT_GAP			= TPM_BASE + 71,
+	TPM_MAXNVWRITES			= TPM_BASE + 72,
+	TPM_NOOPERATOR			= TPM_BASE + 73,
+	TPM_RESOURCEMISSING		= TPM_BASE + 74,
+	TPM_DELEGATE_LOCK		= TPM_BASE + 75,
+	TPM_DELEGATE_FAMILY		= TPM_BASE + 76,
+	TPM_DELEGATE_ADMIN		= TPM_BASE + 77,
+	TPM_TRANSPORT_NOTEXCLUSIVE	= TPM_BASE + 78,
+	TPM_OWNER_CONTROL		= TPM_BASE + 79,
+	TPM_DAA_RESOURCES		= TPM_BASE + 80,
+	TPM_DAA_INPUT_DATA0		= TPM_BASE + 81,
+	TPM_DAA_INPUT_DATA1		= TPM_BASE + 82,
+	TPM_DAA_ISSUER_SETTINGS		= TPM_BASE + 83,
+	TPM_DAA_TPM_SETTINGS		= TPM_BASE + 84,
+	TPM_DAA_STAGE			= TPM_BASE + 85,
+	TPM_DAA_ISSUER_VALIDITY		= TPM_BASE + 86,
+	TPM_DAA_WRONG_W			= TPM_BASE + 87,
+	TPM_BAD_HANDLE			= TPM_BASE + 88,
+	TPM_BAD_DELEGATE		= TPM_BASE + 89,
+	TPM_BADCONTEXT			= TPM_BASE + 90,
+	TPM_TOOMANYCONTEXTS		= TPM_BASE + 91,
+	TPM_MA_TICKET_SIGNATURE		= TPM_BASE + 92,
+	TPM_MA_DESTINATION		= TPM_BASE + 93,
+	TPM_MA_SOURCE			= TPM_BASE + 94,
+	TPM_MA_AUTHORITY		= TPM_BASE + 95,
+	TPM_PERMANENTEK			= TPM_BASE + 97,
+	TPM_BAD_SIGNATURE		= TPM_BASE + 98,
+	TPM_NOCONTEXTSPACE		= TPM_BASE + 99,
+	/* TPM-defined non-fatal errors */
+	TPM_RETRY		= TPM_BASE + TPM_NON_FATAL,
+	TPM_NEEDS_SELFTEST	= TPM_BASE + TPM_NON_FATAL + 1,
+	TPM_DOING_SELFTEST	= TPM_BASE + TPM_NON_FATAL + 2,
+	TPM_DEFEND_LOCK_RUNNING	= TPM_BASE + TPM_NON_FATAL + 3,
+};
+
+/**
+ * Initialize TPM device.  It must be called before any TPM commands.
+ *
+ * @return 0 on success, non-0 on error.
+ */
+uint32_t tpm_init(void);
+
+/**
+ * Issue a TPM_Startup command.
+ *
+ * @param mode		TPM startup mode
+ * @return return code of the operation
+ */
+uint32_t tpm_startup(enum tpm_startup_type mode);
+
+/**
+ * Issue a TPM_SelfTestFull command.
+ *
+ * @return return code of the operation
+ */
+uint32_t tpm_self_test_full(void);
+
+/**
+ * Issue a TPM_ContinueSelfTest command.
+ *
+ * @return return code of the operation
+ */
+uint32_t tpm_continue_self_test(void);
+
+/**
+ * Issue a TPM_NV_DefineSpace command.  The implementation is limited
+ * to specify TPM_NV_ATTRIBUTES and size of the area.  The area index
+ * could be one of the special value listed in enum tpm_nv_index.
+ *
+ * @param index		index of the area
+ * @param perm		TPM_NV_ATTRIBUTES of the area
+ * @param size		size of the area
+ * @return return code of the operation
+ */
+uint32_t tpm_nv_define_space(uint32_t index, uint32_t perm, uint32_t size);
+
+/**
+ * Issue a TPM_NV_ReadValue command.  This implementation is limited
+ * to read the area from offset 0.  The area index could be one of
+ * the special value listed in enum tpm_nv_index.
+ *
+ * @param index		index of the area
+ * @param data		output buffer of the area contents
+ * @param count		size of output buffer
+ * @return return code of the operation
+ */
+uint32_t tpm_nv_read_value(uint32_t index, void *data, uint32_t count);
+
+/**
+ * Issue a TPM_NV_WriteValue command.  This implementation is limited
+ * to write the area from offset 0.  The area index could be one of
+ * the special value listed in enum tpm_nv_index.
+ *
+ * @param index		index of the area
+ * @param data		input buffer to be wrote to the area
+ * @param length	length of data bytes of input buffer
+ * @return return code of the operation
+ */
+uint32_t tpm_nv_write_value(uint32_t index, const void *data, uint32_t length);
+
+/**
+ * Issue a TPM_Extend command.
+ *
+ * @param index		index of the PCR
+ * @param in_digest	160-bit value representing the event to be
+ *			recorded
+ * @param out_digest	160-bit PCR value after execution of the
+ *			command
+ * @return return code of the operation
+ */
+uint32_t tpm_extend(uint32_t index, const void *in_digest, void *out_digest);
+
+/**
+ * Issue a TPM_PCRRead command.
+ *
+ * @param index		index of the PCR
+ * @param data		output buffer for contents of the named PCR
+ * @param count		size of output buffer
+ * @return return code of the operation
+ */
+uint32_t tpm_pcr_read(uint32_t index, void *data, size_t count);
+
+/**
+ * Issue a TSC_PhysicalPresence command.  TPM physical presence flag
+ * is bit-wise OR'ed of flags listed in enum tpm_physical_presence.
+ *
+ * @param presence	TPM physical presence flag
+ * @return return code of the operation
+ */
+uint32_t tpm_tsc_physical_presence(uint16_t presence);
+
+/**
+ * Issue a TPM_ReadPubek command.
+ *
+ * @param data		output buffer for the public endorsement key
+ * @param count		size of ouput buffer
+ * @return return code of the operation
+ */
+uint32_t tpm_read_pubek(void *data, size_t count);
+
+/**
+ * Issue a TPM_ForceClear command.
+ *
+ * @return return code of the operation
+ */
+uint32_t tpm_force_clear(void);
+
+/**
+ * Issue a TPM_PhysicalEnable command.
+ *
+ * @return return code of the operation
+ */
+uint32_t tpm_physical_enable(void);
+
+/**
+ * Issue a TPM_PhysicalDisable command.
+ *
+ * @return return code of the operation
+ */
+uint32_t tpm_physical_disable(void);
+
+/**
+ * Issue a TPM_PhysicalSetDeactivated command.
+ *
+ * @param state		boolean state of the deactivated flag
+ * @return return code of the operation
+ */
+uint32_t tpm_physical_set_deactivated(uint8_t state);
+
+/**
+ * Issue a TPM_GetCapability command.  This implementation is limited
+ * to query sub_cap index that is 4-byte wide.
+ *
+ * @param cap_area	partition of capabilities
+ * @param sub_cap	further definition of capability, which is
+ *			limited to be 4-byte wide
+ * @param cap		output buffer for capability information
+ * @param count		size of ouput buffer
+ * @return return code of the operation
+ */
+uint32_t tpm_get_capability(uint32_t cap_area, uint32_t sub_cap,
+		void *cap, size_t count);
+
+/**
+ * Issue a TPM_FlushSpecific command for a AUTH ressource.
+ *
+ * @param auth_handle	handle of the auth session
+ * @return return code of the operation
+ */
+uint32_t tpm_terminate_auth_session(uint32_t auth_handle);
+
+/**
+ * Issue a TPM_OIAP command to setup an object independant authorization
+ * session.
+ * Information about the session is stored internally.
+ * If there was already an OIAP session active it is terminated and a new
+ * session is set up.
+ *
+ * @param auth_handle	pointer to the (new) auth handle or NULL.
+ * @return return code of the operation
+ */
+uint32_t tpm_oiap(uint32_t *auth_handle);
+
+/**
+ * Ends an active OIAP session.
+ *
+ * @return return code of the operation
+ */
+uint32_t tpm_end_oiap(void);
+
+/**
+ * Issue a TPM_LoadKey2 (Auth1) command using an OIAP session for authenticating
+ * the usage of the parent key.
+ *
+ * @param parent_handle	handle of the parent key.
+ * @param key		pointer to the key structure (TPM_KEY or TPM_KEY12).
+ * @param key_length	size of the key structure
+ * @param parent_key_usage_auth	usage auth for the parent key
+ * @param key_handle	pointer to the key handle
+ * @return return code of the operation
+ */
+uint32_t tpm_load_key2_oiap(uint32_t parent_handle,
+		const void *key, size_t key_length,
+		const void *parent_key_usage_auth,
+		uint32_t *key_handle);
+
+/**
+ * Issue a TPM_GetPubKey (Auth1) command using an OIAP session for
+ * authenticating the usage of the key.
+ *
+ * @param key_handle	handle of the key
+ * @param usage_auth	usage auth for the key
+ * @param pubkey	pointer to the pub key buffer; may be NULL if the pubkey
+ *			should not be stored.
+ * @param pubkey_len	pointer to the pub key buffer len. On entry: the size of
+ *			the provided pubkey buffer. On successful exit: the size
+ *			of the stored TPM_PUBKEY structure (iff pubkey != NULL).
+ * @return return code of the operation
+ */
+uint32_t tpm_get_pub_key_oiap(uint32_t key_handle, const void *usage_auth,
+		void *pubkey, size_t *pubkey_len);
+
+#endif /* __TPM_H */
diff --git a/qemu/roms/u-boot/include/tps6586x.h b/qemu/roms/u-boot/include/tps6586x.h
new file mode 100644
index 000000000..10ca10389
--- /dev/null
+++ b/qemu/roms/u-boot/include/tps6586x.h
@@ -0,0 +1,52 @@
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __H_
+#define _TPS6586X_H_
+
+enum {
+	/* SM0-2 PWM/PFM Mode Selection */
+	TPS6586X_PWM_SM0	= 1 << 0,
+	TPS6586X_PWM_SM1	= 1 << 1,
+	TPS6586X_PWM_SM2	= 1 << 2,
+};
+
+/**
+ * Enable PWM mode for selected SM0-2
+ *
+ * @param mask	Mask of synchronous converter to enable (TPS6586X_PWM_...)
+ * @return 0 if ok, -1 on error
+ */
+int tps6586x_set_pwm_mode(int mask);
+
+/**
+ * Adjust SM0 and SM1 voltages to the given targets in incremental steps.
+ *
+ * @param sm0_target	Target voltage for SM0 in 25mW units, 0=725mV, 31=1.5V
+ * @param sm1_target	Target voltage for SM1 in 25mW units, 0=725mV, 31=1.5V
+ * @param step		Amount to change voltage in each step, in 25mW units
+ * @param rate		Slew ratein mV/us: 0=instantly, 1=0.11, 2=0.22,
+ *			3=0.44, 4=0.88, 5=1.76, 6=3.52, 7=7.04
+ * @param min_sm0_over_sm1	Minimum amount by which sm0 must exceed sm1.
+ *			If this condition is not met, no adjustment will be
+ *			done and an error will be reported. Use -1 to skip
+ *			this check.
+ * @return 0 if ok, -1 on error
+ */
+int tps6586x_adjust_sm0_sm1(int sm0_target, int sm1_target, int step, int rate,
+			    int min_sm0_over_sm1);
+
+/**
+ * Set up the TPS6586X I2C bus number. This will be used for all operations
+ * on the device. This function must be called before using other functions.
+ *
+ * @param bus	I2C bus number containing the TPS6586X chip
+ * @return 0 (always succeeds)
+ */
+int tps6586x_init(int bus);
+
+#endif	/* _TPS6586X_H_ */
diff --git a/qemu/roms/u-boot/include/trace.h b/qemu/roms/u-boot/include/trace.h
new file mode 100644
index 000000000..871327fb3
--- /dev/null
+++ b/qemu/roms/u-boot/include/trace.h
@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __TRACE_H
+#define __TRACE_H
+
+enum {
+	/*
+	 * This affects the granularity of our trace. We can bin function
+	 * entry points into groups on the basis that functions typically
+	 * have a minimum size, so entry points can't appear any closer
+	 * than this to each other.
+	 *
+	 * The value here assumes a minimum instruction size of 4 bytes,
+	 * or that instructions are 2 bytes but there are at least 2 of
+	 * them in every function.
+	 *
+	 * Increasing this value reduces the number of functions we can
+	 * resolve, but reduces the size of the uintptr_t array used for
+	 * our function list, which is the length of the code divided by
+	 * this value.
+	 */
+	FUNC_SITE_SIZE	= 4,	/* distance between function sites */
+};
+
+enum trace_chunk_type {
+	TRACE_CHUNK_FUNCS,
+	TRACE_CHUNK_CALLS,
+};
+
+/* A trace record for a function, as written to the profile output file */
+struct trace_output_func {
+	uint32_t offset;		/* Function offset into code */
+	uint32_t call_count;		/* Number of times called */
+};
+
+/* A header at the start of the trace output buffer */
+struct trace_output_hdr {
+	enum trace_chunk_type type;	/* Record type */
+	uint32_t rec_count;		/* Number of records */
+};
+
+/* Print statistics about traced function calls */
+void trace_print_stats(void);
+
+/**
+ * Dump a list of functions and call counts into a buffer
+ *
+ * Each record in the buffer is a struct trace_func_stats. The 'needed'
+ * parameter returns the number of bytes needed to complete the operation,
+ * which may be more than buff_size if your buffer is too small.
+ *
+ * @param buff		Buffer in which to place data, or NULL to count size
+ * @param buff_size	Size of buffer
+ * @param needed	Returns number of bytes used / needed
+ * @return 0 if ok, -1 on error (buffer exhausted)
+ */
+int trace_list_functions(void *buff, int buff_size, unsigned *needed);
+
+/* Flags for ftrace_record */
+enum ftrace_flags {
+	FUNCF_EXIT		= 0UL << 30,
+	FUNCF_ENTRY		= 1UL << 30,
+	FUNCF_TEXTBASE		= 2UL << 30,
+
+	FUNCF_TIMESTAMP_MASK	= 0x3fffffff,
+};
+
+#define TRACE_CALL_TYPE(call)	((call)->flags & 0xc0000000UL)
+
+/* Information about a single function entry/exit */
+struct trace_call {
+	uint32_t func;		/* Function offset */
+	uint32_t caller;	/* Caller function offset */
+	uint32_t flags;		/* Flags and timestamp */
+};
+
+int trace_list_calls(void *buff, int buff_size, unsigned int *needed);
+
+/**
+ * Turn function tracing on and off
+ *
+ * Don't enable trace if it has not been initialised.
+ *
+ * @param enabled	1 to enable trace, 0 to disable
+ */
+void trace_set_enabled(int enabled);
+
+#ifdef CONFIG_TRACE_EARLY
+int trace_early_init(void);
+#else
+static inline int trace_early_init(void)
+{
+	return 0;
+}
+#endif
+
+/**
+ * Init the trace system
+ *
+ * This should be called after relocation with a suitably large buffer
+ * (typically as large as the U-Boot text area)
+ *
+ * @param buff		Pointer to trace buffer
+ * @param buff_size	Size of trace buffer
+ */
+int trace_init(void *buff, size_t buff_size);
+
+#endif
diff --git a/qemu/roms/u-boot/include/tsec.h b/qemu/roms/u-boot/include/tsec.h
new file mode 100644
index 000000000..1046426c5
--- /dev/null
+++ b/qemu/roms/u-boot/include/tsec.h
@@ -0,0 +1,416 @@
+/*
+ *  tsec.h
+ *
+ *  Driver for the Motorola Triple Speed Ethernet Controller
+ *
+ *  This software may be used and distributed according to the
+ *  terms of the GNU Public License, Version 2, incorporated
+ *  herein by reference.
+ *
+ * Copyright 2004, 2007, 2009, 2011, 2013 Freescale Semiconductor, Inc.
+ * (C) Copyright 2003, Motorola, Inc.
+ * maintained by Xianghua Xiao (x.xiao@motorola.com)
+ * author Andy Fleming
+ *
+ */
+
+#ifndef __TSEC_H
+#define __TSEC_H
+
+#include <net.h>
+#include <config.h>
+#include <phy.h>
+#include <asm/fsl_enet.h>
+
+#define TSEC_SIZE 		0x01000
+#define TSEC_MDIO_OFFSET	0x01000
+
+#define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + 0x520)
+
+#define TSEC_GET_REGS(num, offset) \
+	(struct tsec __iomem *)\
+	(TSEC_BASE_ADDR + (((num) - 1) * (offset)))
+
+#define TSEC_GET_REGS_BASE(num) \
+	TSEC_GET_REGS((num), TSEC_SIZE)
+
+#define TSEC_GET_MDIO_REGS(num, offset) \
+	(struct tsec_mii_mng __iomem *)\
+	(CONFIG_SYS_MDIO_BASE_ADDR  + ((num) - 1) * (offset))
+
+#define TSEC_GET_MDIO_REGS_BASE(num) \
+	TSEC_GET_MDIO_REGS((num), TSEC_MDIO_OFFSET)
+
+#define DEFAULT_MII_NAME "FSL_MDIO"
+
+#define STD_TSEC_INFO(num) \
+{			\
+	.regs = TSEC_GET_REGS_BASE(num), \
+	.miiregs_sgmii = TSEC_GET_MDIO_REGS_BASE(num), \
+	.devname = CONFIG_TSEC##num##_NAME, \
+	.phyaddr = TSEC##num##_PHY_ADDR, \
+	.flags = TSEC##num##_FLAGS, \
+	.mii_devname = DEFAULT_MII_NAME \
+}
+
+#define SET_STD_TSEC_INFO(x, num) \
+{			\
+	x.regs = TSEC_GET_REGS_BASE(num); \
+	x.miiregs_sgmii = TSEC_GET_MDIO_REGS_BASE(num); \
+	x.devname = CONFIG_TSEC##num##_NAME; \
+	x.phyaddr = TSEC##num##_PHY_ADDR; \
+	x.flags = TSEC##num##_FLAGS;\
+	x.mii_devname = DEFAULT_MII_NAME;\
+}
+
+#define MAC_ADDR_LEN 6
+
+/* #define TSEC_TIMEOUT	1000000 */
+#define TSEC_TIMEOUT 1000
+#define TOUT_LOOP	1000000
+
+/* TBI register addresses */
+#define TBI_CR			0x00
+#define TBI_SR			0x01
+#define TBI_ANA			0x04
+#define TBI_ANLPBPA		0x05
+#define TBI_ANEX		0x06
+#define TBI_TBICON		0x11
+
+/* TBI MDIO register bit fields*/
+#define TBICON_CLK_SELECT	0x0020
+#define TBIANA_ASYMMETRIC_PAUSE 0x0100
+#define TBIANA_SYMMETRIC_PAUSE  0x0080
+#define TBIANA_HALF_DUPLEX	0x0040
+#define TBIANA_FULL_DUPLEX	0x0020
+#define TBICR_PHY_RESET		0x8000
+#define TBICR_ANEG_ENABLE	0x1000
+#define TBICR_RESTART_ANEG	0x0200
+#define TBICR_FULL_DUPLEX	0x0100
+#define TBICR_SPEED1_SET	0x0040
+
+
+/* MAC register bits */
+#define MACCFG1_SOFT_RESET	0x80000000
+#define MACCFG1_RESET_RX_MC	0x00080000
+#define MACCFG1_RESET_TX_MC	0x00040000
+#define MACCFG1_RESET_RX_FUN	0x00020000
+#define	MACCFG1_RESET_TX_FUN	0x00010000
+#define MACCFG1_LOOPBACK	0x00000100
+#define MACCFG1_RX_FLOW		0x00000020
+#define MACCFG1_TX_FLOW		0x00000010
+#define MACCFG1_SYNCD_RX_EN	0x00000008
+#define MACCFG1_RX_EN		0x00000004
+#define MACCFG1_SYNCD_TX_EN	0x00000002
+#define MACCFG1_TX_EN		0x00000001
+
+#define MACCFG2_INIT_SETTINGS	0x00007205
+#define MACCFG2_FULL_DUPLEX	0x00000001
+#define MACCFG2_IF		0x00000300
+#define MACCFG2_GMII		0x00000200
+#define MACCFG2_MII		0x00000100
+
+#define ECNTRL_INIT_SETTINGS	0x00001000
+#define ECNTRL_TBI_MODE		0x00000020
+#define ECNTRL_REDUCED_MODE	0x00000010
+#define ECNTRL_R100		0x00000008
+#define ECNTRL_REDUCED_MII_MODE	0x00000004
+#define ECNTRL_SGMII_MODE	0x00000002
+
+#ifndef CONFIG_SYS_TBIPA_VALUE
+    #define CONFIG_SYS_TBIPA_VALUE	0x1f
+#endif
+
+#define MRBLR_INIT_SETTINGS	PKTSIZE_ALIGN
+
+#define MINFLR_INIT_SETTINGS	0x00000040
+
+#define DMACTRL_INIT_SETTINGS	0x000000c3
+#define DMACTRL_GRS		0x00000010
+#define DMACTRL_GTS		0x00000008
+
+#define TSTAT_CLEAR_THALT	0x80000000
+#define RSTAT_CLEAR_RHALT	0x00800000
+
+
+#define IEVENT_INIT_CLEAR	0xffffffff
+#define IEVENT_BABR		0x80000000
+#define IEVENT_RXC		0x40000000
+#define IEVENT_BSY		0x20000000
+#define IEVENT_EBERR		0x10000000
+#define IEVENT_MSRO		0x04000000
+#define IEVENT_GTSC		0x02000000
+#define IEVENT_BABT		0x01000000
+#define IEVENT_TXC		0x00800000
+#define IEVENT_TXE		0x00400000
+#define IEVENT_TXB		0x00200000
+#define IEVENT_TXF		0x00100000
+#define IEVENT_IE		0x00080000
+#define IEVENT_LC		0x00040000
+#define IEVENT_CRL		0x00020000
+#define IEVENT_XFUN		0x00010000
+#define IEVENT_RXB0		0x00008000
+#define IEVENT_GRSC		0x00000100
+#define IEVENT_RXF0		0x00000080
+
+#define IMASK_INIT_CLEAR	0x00000000
+#define IMASK_TXEEN		0x00400000
+#define IMASK_TXBEN		0x00200000
+#define IMASK_TXFEN		0x00100000
+#define IMASK_RXFEN0		0x00000080
+
+
+/* Default Attribute fields */
+#define ATTR_INIT_SETTINGS     0x000000c0
+#define ATTRELI_INIT_SETTINGS  0x00000000
+
+
+/* TxBD status field bits */
+#define TXBD_READY		0x8000
+#define TXBD_PADCRC		0x4000
+#define TXBD_WRAP		0x2000
+#define TXBD_INTERRUPT		0x1000
+#define TXBD_LAST		0x0800
+#define TXBD_CRC		0x0400
+#define TXBD_DEF		0x0200
+#define TXBD_HUGEFRAME		0x0080
+#define TXBD_LATECOLLISION	0x0080
+#define TXBD_RETRYLIMIT		0x0040
+#define	TXBD_RETRYCOUNTMASK	0x003c
+#define TXBD_UNDERRUN		0x0002
+#define TXBD_STATS		0x03ff
+
+/* RxBD status field bits */
+#define RXBD_EMPTY		0x8000
+#define RXBD_RO1		0x4000
+#define RXBD_WRAP		0x2000
+#define RXBD_INTERRUPT		0x1000
+#define RXBD_LAST		0x0800
+#define RXBD_FIRST		0x0400
+#define RXBD_MISS		0x0100
+#define RXBD_BROADCAST		0x0080
+#define RXBD_MULTICAST		0x0040
+#define RXBD_LARGE		0x0020
+#define RXBD_NONOCTET		0x0010
+#define RXBD_SHORT		0x0008
+#define RXBD_CRCERR		0x0004
+#define RXBD_OVERRUN		0x0002
+#define RXBD_TRUNCATED		0x0001
+#define RXBD_STATS		0x003f
+
+struct txbd8 {
+	uint16_t     status;	     /* Status Fields */
+	uint16_t     length;	     /* Buffer length */
+	uint32_t     bufptr;	     /* Buffer Pointer */
+};
+
+struct rxbd8 {
+	uint16_t     status;	     /* Status Fields */
+	uint16_t     length;	     /* Buffer Length */
+	uint32_t     bufptr;	     /* Buffer Pointer */
+};
+
+struct tsec_rmon_mib {
+	/* Transmit and Receive Counters */
+	u32	tr64;		/* Tx/Rx 64-byte Frame Counter */
+	u32	tr127;		/* Tx/Rx 65-127 byte Frame Counter */
+	u32	tr255;		/* Tx/Rx 128-255 byte Frame Counter */
+	u32	tr511;		/* Tx/Rx 256-511 byte Frame Counter */
+	u32	tr1k;		/* Tx/Rx 512-1023 byte Frame Counter */
+	u32	trmax;		/* Tx/Rx 1024-1518 byte Frame Counter */
+	u32	trmgv;		/* Tx/Rx 1519-1522 byte Good VLAN Frame */
+	/* Receive Counters */
+	u32	rbyt;		/* Receive Byte Counter */
+	u32	rpkt;		/* Receive Packet Counter */
+	u32	rfcs;		/* Receive FCS Error Counter */
+	u32	rmca;		/* Receive Multicast Packet (Counter) */
+	u32	rbca;		/* Receive Broadcast Packet */
+	u32	rxcf;		/* Receive Control Frame Packet */
+	u32	rxpf;		/* Receive Pause Frame Packet */
+	u32	rxuo;		/* Receive Unknown OP Code */
+	u32	raln;		/* Receive Alignment Error */
+	u32	rflr;		/* Receive Frame Length Error */
+	u32	rcde;		/* Receive Code Error */
+	u32	rcse;		/* Receive Carrier Sense Error */
+	u32	rund;		/* Receive Undersize Packet */
+	u32	rovr;		/* Receive Oversize Packet */
+	u32	rfrg;		/* Receive Fragments */
+	u32	rjbr;		/* Receive Jabber */
+	u32	rdrp;		/* Receive Drop */
+	/* Transmit Counters */
+	u32	tbyt;		/* Transmit Byte Counter */
+	u32	tpkt;		/* Transmit Packet */
+	u32	tmca;		/* Transmit Multicast Packet */
+	u32	tbca;		/* Transmit Broadcast Packet */
+	u32	txpf;		/* Transmit Pause Control Frame */
+	u32	tdfr;		/* Transmit Deferral Packet */
+	u32	tedf;		/* Transmit Excessive Deferral Packet */
+	u32	tscl;		/* Transmit Single Collision Packet */
+	/* (0x2_n700) */
+	u32	tmcl;		/* Transmit Multiple Collision Packet */
+	u32	tlcl;		/* Transmit Late Collision Packet */
+	u32	txcl;		/* Transmit Excessive Collision Packet */
+	u32	tncl;		/* Transmit Total Collision */
+
+	u32	res2;
+
+	u32	tdrp;		/* Transmit Drop Frame */
+	u32	tjbr;		/* Transmit Jabber Frame */
+	u32	tfcs;		/* Transmit FCS Error */
+	u32	txcf;		/* Transmit Control Frame */
+	u32	tovr;		/* Transmit Oversize Frame */
+	u32	tund;		/* Transmit Undersize Frame */
+	u32	tfrg;		/* Transmit Fragments Frame */
+	/* General Registers */
+	u32	car1;		/* Carry Register One */
+	u32	car2;		/* Carry Register Two */
+	u32	cam1;		/* Carry Register One Mask */
+	u32	cam2;		/* Carry Register Two Mask */
+};
+
+struct tsec_hash_regs {
+	u32	iaddr0;		/* Individual Address Register 0 */
+	u32	iaddr1;		/* Individual Address Register 1 */
+	u32	iaddr2;		/* Individual Address Register 2 */
+	u32	iaddr3;		/* Individual Address Register 3 */
+	u32	iaddr4;		/* Individual Address Register 4 */
+	u32	iaddr5;		/* Individual Address Register 5 */
+	u32	iaddr6;		/* Individual Address Register 6 */
+	u32	iaddr7;		/* Individual Address Register 7 */
+	u32	res1[24];
+	u32	gaddr0;		/* Group Address Register 0 */
+	u32	gaddr1;		/* Group Address Register 1 */
+	u32	gaddr2;		/* Group Address Register 2 */
+	u32	gaddr3;		/* Group Address Register 3 */
+	u32	gaddr4;		/* Group Address Register 4 */
+	u32	gaddr5;		/* Group Address Register 5 */
+	u32	gaddr6;		/* Group Address Register 6 */
+	u32	gaddr7;		/* Group Address Register 7 */
+	u32	res2[24];
+};
+
+struct tsec {
+	/* General Control and Status Registers (0x2_n000) */
+	u32	res000[4];
+
+	u32	ievent;		/* Interrupt Event */
+	u32	imask;		/* Interrupt Mask */
+	u32	edis;		/* Error Disabled */
+	u32	res01c;
+	u32	ecntrl;		/* Ethernet Control */
+	u32	minflr;		/* Minimum Frame Length */
+	u32	ptv;		/* Pause Time Value */
+	u32	dmactrl;	/* DMA Control */
+	u32	tbipa;		/* TBI PHY Address */
+
+	u32	res034[3];
+	u32	res040[48];
+
+	/* Transmit Control and Status Registers (0x2_n100) */
+	u32	tctrl;		/* Transmit Control */
+	u32	tstat;		/* Transmit Status */
+	u32	res108;
+	u32	tbdlen;		/* Tx BD Data Length */
+	u32	res110[5];
+	u32	ctbptr;		/* Current TxBD Pointer */
+	u32	res128[23];
+	u32	tbptr;		/* TxBD Pointer */
+	u32	res188[30];
+	/* (0x2_n200) */
+	u32	res200;
+	u32	tbase;		/* TxBD Base Address */
+	u32	res208[42];
+	u32	ostbd;		/* Out of Sequence TxBD */
+	u32	ostbdp;		/* Out of Sequence Tx Data Buffer Pointer */
+	u32	res2b8[18];
+
+	/* Receive Control and Status Registers (0x2_n300) */
+	u32	rctrl;		/* Receive Control */
+	u32	rstat;		/* Receive Status */
+	u32	res308;
+	u32	rbdlen;		/* RxBD Data Length */
+	u32	res310[4];
+	u32	res320;
+	u32	crbptr;	/* Current Receive Buffer Pointer */
+	u32	res328[6];
+	u32	mrblr;	/* Maximum Receive Buffer Length */
+	u32	res344[16];
+	u32	rbptr;	/* RxBD Pointer */
+	u32	res388[30];
+	/* (0x2_n400) */
+	u32	res400;
+	u32	rbase;	/* RxBD Base Address */
+	u32	res408[62];
+
+	/* MAC Registers (0x2_n500) */
+	u32	maccfg1;	/* MAC Configuration #1 */
+	u32	maccfg2;	/* MAC Configuration #2 */
+	u32	ipgifg;		/* Inter Packet Gap/Inter Frame Gap */
+	u32	hafdup;		/* Half-duplex */
+	u32	maxfrm;		/* Maximum Frame */
+	u32	res514;
+	u32	res518;
+
+	u32	res51c;
+
+	u32	resmdio[6];
+
+	u32	res538;
+
+	u32	ifstat;		/* Interface Status */
+	u32	macstnaddr1;	/* Station Address, part 1 */
+	u32	macstnaddr2;	/* Station Address, part 2 */
+	u32	res548[46];
+
+	/* (0x2_n600) */
+	u32	res600[32];
+
+	/* RMON MIB Registers (0x2_n680-0x2_n73c) */
+	struct tsec_rmon_mib	rmon;
+	u32	res740[48];
+
+	/* Hash Function Registers (0x2_n800) */
+	struct tsec_hash_regs	hash;
+
+	u32	res900[128];
+
+	/* Pattern Registers (0x2_nb00) */
+	u32	resb00[62];
+	u32	attr; /* Default Attribute Register */
+	u32	attreli; /* Default Attribute Extract Length and Index */
+
+	/* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */
+	u32	resc00[256];
+};
+
+#define TSEC_GIGABIT (1 << 0)
+
+/* These flags currently only have meaning if we're using the eTSEC */
+#define TSEC_REDUCED	(1 << 1)	/* MAC-PHY interface uses RGMII */
+#define TSEC_SGMII	(1 << 2)	/* MAC-PHY interface uses SGMII */
+
+struct tsec_private {
+	struct tsec __iomem *regs;
+	struct tsec_mii_mng __iomem *phyregs_sgmii;
+	struct phy_device *phydev;
+	phy_interface_t interface;
+	struct mii_dev *bus;
+	uint phyaddr;
+	char mii_devname[16];
+	u32 flags;
+};
+
+struct tsec_info_struct {
+	struct tsec __iomem *regs;
+	struct tsec_mii_mng __iomem *miiregs_sgmii;
+	char *devname;
+	char *mii_devname;
+	phy_interface_t interface;
+	unsigned int phyaddr;
+	u32 flags;
+};
+
+int tsec_standard_init(bd_t *bis);
+int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsec_info, int num);
+
+#endif /* __TSEC_H */
diff --git a/qemu/roms/u-boot/include/tsi108.h b/qemu/roms/u-boot/include/tsi108.h
new file mode 100644
index 000000000..34bd424f4
--- /dev/null
+++ b/qemu/roms/u-boot/include/tsi108.h
@@ -0,0 +1,208 @@
+/*****************************************************************************
+ * (C) Copyright 2003;  Tundra Semiconductor Corp.
+ * (C) Copyright 2006;  Freescale Semiconductor Corp.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *****************************************************************************/
+
+/*
+ * FILENAME: tsi108.h
+ *
+ * Originator: Alex Bounine
+ *
+ * DESCRIPTION:
+ * Common definitions for the Tundra Tsi108 bridge chip
+ *
+ */
+
+#ifndef _TSI108_H_
+#define _TSI108_H_
+
+#define TSI108_HLP_REG_OFFSET	(0x0000)
+#define TSI108_PCI_REG_OFFSET	(0x1000)
+#define TSI108_CLK_REG_OFFSET	(0x2000)
+#define TSI108_PB_REG_OFFSET	(0x3000)
+#define TSI108_SD_REG_OFFSET	(0x4000)
+#define TSI108_MPIC_REG_OFFSET	(0x7400)
+
+#define PB_ID			(0x000)
+#define PB_RSR			(0x004)
+#define PB_BUS_MS_SELECT	(0x008)
+#define PB_ISR			(0x00C)
+#define PB_ARB_CTRL		(0x018)
+#define PB_PVT_CTRL2		(0x034)
+#define PB_SCR			(0x400)
+#define PB_ERRCS		(0x404)
+#define PB_AERR			(0x408)
+#define PB_REG_BAR		(0x410)
+#define PB_OCN_BAR1		(0x414)
+#define PB_OCN_BAR2		(0x418)
+#define PB_SDRAM_BAR1		(0x41C)
+#define PB_SDRAM_BAR2		(0x420)
+#define PB_MCR			(0xC00)
+#define PB_MCMD			(0xC04)
+
+#define HLP_B0_ADDR		(0x000)
+#define HLP_B1_ADDR		(0x010)
+#define HLP_B2_ADDR		(0x020)
+#define HLP_B3_ADDR		(0x030)
+
+#define HLP_B0_MASK		(0x004)
+#define HLP_B1_MASK		(0x014)
+#define HLP_B2_MASK		(0x024)
+#define HLP_B3_MASK		(0x034)
+
+#define HLP_B0_CTRL0		(0x008)
+#define HLP_B1_CTRL0		(0x018)
+#define HLP_B2_CTRL0		(0x028)
+#define HLP_B3_CTRL0		(0x038)
+
+#define HLP_B0_CTRL1		(0x00C)
+#define HLP_B1_CTRL1		(0x01C)
+#define HLP_B2_CTRL1		(0x02C)
+#define HLP_B3_CTRL1		(0x03C)
+
+#define PCI_CSR			(0x004)
+#define PCI_P2O_BAR0		(0x010)
+#define PCI_P2O_BAR0_UPPER	(0x014)
+#define PCI_P2O_BAR2		(0x018)
+#define PCI_P2O_BAR2_UPPER	(0x01C)
+#define PCI_P2O_BAR3		(0x020)
+#define PCI_P2O_BAR3_UPPER	(0x024)
+
+#define PCI_MISC_CSR		(0x040)
+#define PCI_P2O_PAGE_SIZES	(0x04C)
+
+#define PCI_PCIX_STAT		(0x0F4)
+
+#define PCI_IRP_STAT		(0x184)
+
+#define PCI_PFAB_BAR0		(0x204)
+#define PCI_PFAB_BAR0_UPPER	(0x208)
+#define PCI_PFAB_IO		(0x20C)
+#define PCI_PFAB_IO_UPPER	(0x210)
+
+#define PCI_PFAB_MEM32		(0x214)
+#define PCI_PFAB_MEM32_REMAP	(0x218)
+#define PCI_PFAB_MEM32_MASK	(0x21C)
+
+#define CG_PLL0_CTRL0		(0x210)
+#define CG_PLL0_CTRL1		(0x214)
+#define CG_PLL1_CTRL0		(0x220)
+#define CG_PLL1_CTRL1		(0x224)
+#define CG_PWRUP_STATUS		(0x234)
+
+#define MPIC_CSR(n) (0x30C + (n * 0x40))
+
+#define SD_CTRL			(0x000)
+#define SD_STATUS		(0x004)
+#define SD_TIMING		(0x008)
+#define SD_REFRESH		(0x00C)
+#define SD_INT_STATUS		(0x010)
+#define SD_INT_ENABLE		(0x014)
+#define SD_INT_SET		(0x018)
+#define SD_D0_CTRL		(0x020)
+#define SD_D1_CTRL		(0x024)
+#define SD_D0_BAR		(0x028)
+#define SD_D1_BAR		(0x02C)
+#define SD_ECC_CTRL		(0x040)
+#define SD_DLL_STATUS		(0x250)
+
+#define TS_SD_CTRL_ENABLE	(1 << 31)
+
+#define PB_ERRCS_ES		(1 << 1)
+#define PB_ISR_PBS_RD_ERR	(1 << 8)
+#define PCI_IRP_STAT_P_CSR	(1 << 23)
+
+/*
+ * I2C : Register address offset definitions
+ */
+#define I2C_CNTRL1		(0x00000000)
+#define I2C_CNTRL2		(0x00000004)
+#define I2C_RD_DATA		(0x00000008)
+#define I2C_TX_DATA		(0x0000000c)
+
+/*
+ * I2C : Register Bit Masks and Reset Values
+ * definitions for every register
+ */
+
+/* I2C_CNTRL1 : Reset Value */
+#define I2C_CNTRL1_RESET_VALUE				(0x0000000a)
+
+/* I2C_CNTRL1 : Register Bits Masks Definitions */
+#define I2C_CNTRL1_DEVCODE				(0x0000000f)
+#define I2C_CNTRL1_PAGE					(0x00000700)
+#define I2C_CNTRL1_BYTADDR				(0x00ff0000)
+#define I2C_CNTRL1_I2CWRITE				(0x01000000)
+
+/* I2C_CNTRL1 : Read/Write Bit Mask Definition */
+#define I2C_CNTRL1_RWMASK				(0x01ff070f)
+
+/* I2C_CNTRL1 : Unused/Reserved bits Definition */
+#define I2C_CNTRL1_RESERVED				(0xfe00f8f0)
+
+/* I2C_CNTRL2 : Reset Value */
+#define I2C_CNTRL2_RESET_VALUE				(0x00000000)
+
+/* I2C_CNTRL2 : Register Bits Masks Definitions */
+#define I2C_CNTRL2_SIZE					(0x00000003)
+#define I2C_CNTRL2_LANE					(0x0000000c)
+#define I2C_CNTRL2_MULTIBYTE				(0x00000010)
+#define I2C_CNTRL2_START				(0x00000100)
+#define I2C_CNTRL2_WR_STATUS				(0x00010000)
+#define I2C_CNTRL2_RD_STATUS				(0x00020000)
+#define I2C_CNTRL2_I2C_TO_ERR				(0x04000000)
+#define I2C_CNTRL2_I2C_CFGERR				(0x08000000)
+#define I2C_CNTRL2_I2C_CMPLT				(0x10000000)
+
+/* I2C_CNTRL2 : Read/Write Bit Mask Definition */
+#define I2C_CNTRL2_RWMASK				(0x0000011f)
+
+/* I2C_CNTRL2 : Unused/Reserved bits Definition */
+#define I2C_CNTRL2_RESERVED				(0xe3fcfee0)
+
+/* I2C_RD_DATA : Reset Value */
+#define I2C_RD_DATA_RESET_VALUE				(0x00000000)
+
+/* I2C_RD_DATA : Register Bits Masks Definitions */
+#define I2C_RD_DATA_RBYTE0				(0x000000ff)
+#define I2C_RD_DATA_RBYTE1				(0x0000ff00)
+#define I2C_RD_DATA_RBYTE2				(0x00ff0000)
+#define I2C_RD_DATA_RBYTE3				(0xff000000)
+
+/* I2C_RD_DATA : Read/Write Bit Mask Definition */
+#define I2C_RD_DATA_RWMASK				(0x00000000)
+
+/* I2C_RD_DATA : Unused/Reserved bits Definition */
+#define I2C_RD_DATA_RESERVED				(0x00000000)
+
+/* I2C_TX_DATA : Reset Value */
+#define I2C_TX_DATA_RESET_VALUE				(0x00000000)
+
+/* I2C_TX_DATA : Register Bits Masks Definitions */
+#define I2C_TX_DATA_TBYTE0				(0x000000ff)
+#define I2C_TX_DATA_TBYTE1				(0x0000ff00)
+#define I2C_TX_DATA_TBYTE2				(0x00ff0000)
+#define I2C_TX_DATA_TBYTE3				(0xff000000)
+
+/* I2C_TX_DATA : Read/Write Bit Mask Definition */
+#define I2C_TX_DATA_RWMASK				(0xffffffff)
+
+/* I2C_TX_DATA : Unused/Reserved bits Definition */
+#define I2C_TX_DATA_RESERVED				(0x00000000)
+
+#define TSI108_I2C_OFFSET	0x7000	/* offset for general use I2C channel */
+#define TSI108_I2C_SDRAM_OFFSET	0x4400	/* offset for SPD I2C channel */
+
+#define I2C_EEPROM_DEVCODE	0xA	/* standard I2C EEPROM device code */
+
+/* I2C status codes */
+
+#define TSI108_I2C_SUCCESS	0
+#define TSI108_I2C_PARAM_ERR	1
+#define TSI108_I2C_TIMEOUT_ERR	2
+#define TSI108_I2C_IF_BUSY	3
+#define TSI108_I2C_IF_ERROR	4
+
+#endif		/* _TSI108_H_ */
diff --git a/qemu/roms/u-boot/include/tsi148.h b/qemu/roms/u-boot/include/tsi148.h
new file mode 100644
index 000000000..9b635e150
--- /dev/null
+++ b/qemu/roms/u-boot/include/tsi148.h
@@ -0,0 +1,202 @@
+/*
+ * (C) Copyright 2009 Reinhard Arlt, reinhard.arlt@esd-electronics.com
+ *
+ * base on universe.h by
+ *
+ * (C) Copyright 2003 Stefan Roese, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _tsi148_h
+#define _tsi148_h
+
+#ifndef PCI_DEVICE_ID_TUNDRA_TSI148
+#define PCI_DEVICE_ID_TUNDRA_TSI148 0x0148
+#endif
+
+typedef struct _TSI148 TSI148;
+typedef struct _OUTBOUND OUTBOUND;
+typedef struct _INBOUND  INBOUND;
+typedef struct _TDMA_CMD_PACKET TDMA_CMD_PACKET;
+
+struct _OUTBOUND {
+	unsigned int otsau;                   /* 0x000 Outbound start       upper */
+	unsigned int otsal;                   /* 0x004 Outbouud start       lower */
+	unsigned int oteau;                   /* 0x008 Outbound end         upper */
+	unsigned int oteal;                   /* 0x00c Outbound end         lower */
+	unsigned int otofu;                   /* 0x010 Outbound translation upper */
+	unsigned int otofl;                   /* 0x014 Outbound translation lower */
+	unsigned int otbs;                    /* 0x018 Outbound translation 2eSST */
+	unsigned int otat;                    /* 0x01c Outbound translation attr  */
+};
+
+struct _INBOUND {
+	unsigned int itsau;                   /* 0x000 inbound  start       upper */
+	unsigned int itsal;                   /* 0x004 inbouud  start       lower */
+	unsigned int iteau;                   /* 0x008 inbound  end         upper */
+	unsigned int iteal;                   /* 0x00c inbound  end         lower */
+	unsigned int itofu;                   /* 0x010 inbound  translation upper */
+	unsigned int itofl;                   /* 0x014 inbound  translation lower */
+	unsigned int itat;                    /* 0x018 inbound  translation attr  */
+	unsigned int spare;                   /* 0x01c not used                   */
+};
+
+struct _TSI148 {
+	unsigned int pci_id;                  /* 0x000         */
+	unsigned int pci_csr;                 /* 0x004         */
+	unsigned int pci_class;               /* 0x008         */
+	unsigned int pci_misc0;               /* 0x00c         */
+	unsigned int pci_mbarl;               /* 0x010         */
+	unsigned int pci_mbarh;               /* 0x014         */
+	unsigned int spare0[(0x03c-0x018)/4]; /* 0x018         */
+	unsigned int pci_misc1;               /* 0x03c         */
+	unsigned int pci_pcixcap;             /* 0x040         */
+	unsigned int pci_pcixstat;            /* 0x044         */
+	unsigned int spare1[(0x100-0x048)/4]; /* 0x048         */
+	OUTBOUND     outbound[8];             /* 0x100         */
+	unsigned int viack[8];                /* 0x204         */
+	unsigned int rmwau;                   /* 0x220         */
+	unsigned int rmwal;                   /* 0x224         */
+	unsigned int rmwen;                   /* 0x228         */
+	unsigned int rmwc;                    /* 0x22c         */
+	unsigned int rmws;                    /* 0x230         */
+	unsigned int vmctrl;                  /* 0x234         */
+	unsigned int vctrl;                   /* 0x238         */
+	unsigned int vstat;                   /* 0x23c         */
+	unsigned int pcsr;                    /* 0x240         */
+	unsigned int spare2[3];               /* 0x244 - 0x24c */
+	unsigned int vmefl;                   /* 0x250         */
+	unsigned int spare3[3];               /* 0x254 - 0x25c */
+	unsigned int veau;                    /* 0x260         */
+	unsigned int veal;                    /* 0x264         */
+	unsigned int veat;                    /* 0x268         */
+	unsigned int spare4[1];               /* 0x26c         */
+	unsigned int edpau;                   /* 0x270         */
+	unsigned int edpal;                   /* 0x274         */
+	unsigned int edpxa;                   /* 0x278         */
+	unsigned int edpxs;                   /* 0x27c         */
+	unsigned int edpat;                   /* 0x280         */
+	unsigned int spare5[31];              /* 0x284 - 0x2fc */
+	INBOUND      inbound[8];              /* 0x100         */
+	unsigned int gbau;                    /* 0x400         */
+	unsigned int gbal;                    /* 0x404         */
+	unsigned int gcsrat;                  /* 0x408         */
+	unsigned int cbau;                    /* 0x40c         */
+	unsigned int cbal;                    /* 0x410         */
+	unsigned int crgat;                   /* 0x414         */
+	unsigned int crou;                    /* 0x418         */
+	unsigned int crol;                    /* 0x41c         */
+	unsigned int crat;                    /* 0x420         */
+	unsigned int lmbau;                   /* 0x424         */
+	unsigned int lmbal;                   /* 0x428         */
+	unsigned int lmat;                    /* 0x42c         */
+	unsigned int r64bcu;                  /* 0x430         */
+	unsigned int r64bcl;                  /* 0x434         */
+	unsigned int bpgtr;                   /* 0x438         */
+	unsigned int bpctr;                   /* 0x43c         */
+	unsigned int vicr;                    /* 0x440         */
+	unsigned int spare6[1];               /* 0x444         */
+	unsigned int inten;                   /* 0x448         */
+	unsigned int inteo;                   /* 0x44c         */
+	unsigned int ints;                    /* 0x450         */
+	unsigned int intc;                    /* 0x454         */
+	unsigned int intm1;                   /* 0x458         */
+	unsigned int intm2;                   /* 0x45c         */
+	unsigned int spare7[40];              /* 0x460 - 0x4fc */
+	unsigned int dctl0;                   /* 0x500         */
+	unsigned int dsta0;                   /* 0x504         */
+	unsigned int dcsau0;                  /* 0x508         */
+	unsigned int dcsal0;                  /* 0x50c         */
+	unsigned int dcdau0;                  /* 0x510         */
+	unsigned int dcdal0;                  /* 0x514         */
+	unsigned int dclau0;                  /* 0x518         */
+	unsigned int dclal0;                  /* 0x51c         */
+	unsigned int dsau0;                   /* 0x520         */
+	unsigned int dsal0;                   /* 0x524         */
+	unsigned int ddau0;                   /* 0x528         */
+	unsigned int ddal0;                   /* 0x52c         */
+	unsigned int dsat0;                   /* 0x530         */
+	unsigned int ddat0;                   /* 0x534         */
+	unsigned int dnlau0;                  /* 0x538         */
+	unsigned int dnlal0;                  /* 0x53c         */
+	unsigned int dcnt0;                   /* 0x540         */
+	unsigned int ddbs0;                   /* 0x544         */
+	unsigned int r20[14];                 /* 0x548 - 0x57c */
+	unsigned int dctl1;                   /* 0x580         */
+	unsigned int dsta1;                   /* 0x584         */
+	unsigned int dcsau1;                  /* 0x588         */
+	unsigned int dcsal1;                  /* 0x58c         */
+	unsigned int dcdau1;                  /* 0x590         */
+	unsigned int dcdal1;                  /* 0x594         */
+	unsigned int dclau1;                  /* 0x598         */
+	unsigned int dclal1;                  /* 0x59c         */
+	unsigned int dsau1;                   /* 0x5a0         */
+	unsigned int dsal1;                   /* 0x5a4         */
+	unsigned int ddau1;                   /* 0x5a8         */
+	unsigned int ddal1;                   /* 0x5ac         */
+	unsigned int dsat1;                   /* 0x5b0         */
+	unsigned int ddat1;                   /* 0x5b4         */
+	unsigned int dnlau1;                  /* 0x5b8         */
+	unsigned int dnlal1;                  /* 0x5bc         */
+	unsigned int dcnt1;                   /* 0x5c0         */
+	unsigned int ddbs1;                   /* 0x5c4         */
+	unsigned int r21[14];                 /* 0x5c8 - 0x5fc */
+	unsigned int devi_veni_2;             /* 0x600         */
+	unsigned int gctrl_ga_revid;          /* 0x604         */
+	unsigned int semaphore0_1_2_3;        /* 0x608         */
+	unsigned int semaphore4_5_6_7;        /* 0x60c         */
+	unsigned int mbox0;                   /* 0x610         */
+	unsigned int mbox1;                   /* 0x614         */
+	unsigned int mbox2;                   /* 0x618         */
+	unsigned int mbox3;                   /* 0x61c         */
+	unsigned int r22[629];                /* 0x620 - 0xff0 */
+	unsigned int csrbcr;                  /* 0xff4         */
+	unsigned int csrbsr;                  /* 0xff8         */
+	unsigned int cbar;                    /* 0xffc         */
+};
+
+#define IRQ_VOWN	0x0001
+#define IRQ_VIRQ1	0x0002
+#define IRQ_VIRQ2	0x0004
+#define IRQ_VIRQ3	0x0008
+#define IRQ_VIRQ4	0x0010
+#define IRQ_VIRQ5	0x0020
+#define IRQ_VIRQ6	0x0040
+#define IRQ_VIRQ7	0x0080
+#define IRQ_DMA		0x0100
+#define IRQ_LERR	0x0200
+#define IRQ_VERR	0x0400
+#define IRQ_res		0x0800
+#define IRQ_IACK	0x1000
+#define IRQ_SWINT	0x2000
+#define IRQ_SYSFAIL	0x4000
+#define IRQ_ACFAIL	0x8000
+
+struct _TDMA_CMD_PACKET {
+	unsigned int dctl;   /* DMA Control         */
+	unsigned int dtbc;   /* Transfer Byte Count */
+	unsigned int dlv;    /* PCI Address         */
+	unsigned int res1;   /* Reserved            */
+	unsigned int dva;    /* Vme Address         */
+	unsigned int res2;   /* Reserved            */
+	unsigned int dcpp;   /* Pointer to Numed Cmd Packet with rPN */
+	unsigned int res3;   /* Reserved                             */
+};
+
+#define VME_AM_A16		0x01
+#define VME_AM_A24		0x02
+#define VME_AM_A32		0x03
+#define VME_AM_Axx		0x03
+#define VME_AM_USR		0x04
+#define VME_AM_SUP		0x08
+#define VME_AM_DATA		0x10
+#define VME_AM_PROG		0x20
+#define VME_AM_Mxx		(VME_AM_DATA | VME_AM_PROG)
+
+#define VME_FLAG_D8		0x01
+#define VME_FLAG_D16		0x02
+#define VME_FLAG_D32		0x03
+#define VME_FLAG_Dxx		0x03
+
+#endif
diff --git a/qemu/roms/u-boot/include/twl4030.h b/qemu/roms/u-boot/include/twl4030.h
new file mode 100644
index 000000000..093c61d6d
--- /dev/null
+++ b/qemu/roms/u-boot/include/twl4030.h
@@ -0,0 +1,662 @@
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <Tom.Rix at windriver.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Derived from code on omapzoom, git://git.omapzoom.com/repo/u-boot.git
+ *
+ * Copyright (C) 2007-2009 Texas Instruments, Inc.
+ */
+
+#ifndef TWL4030_H
+#define TWL4030_H
+
+#include <common.h>
+#include <i2c.h>
+
+/* I2C chip addresses */
+
+/* USB */
+#define TWL4030_CHIP_USB				0x48
+/* AUD */
+#define TWL4030_CHIP_AUDIO_VOICE			0x49
+#define TWL4030_CHIP_GPIO				0x49
+#define TWL4030_CHIP_INTBR				0x49
+#define TWL4030_CHIP_PIH				0x49
+#define TWL4030_CHIP_TEST				0x49
+/* AUX */
+#define TWL4030_CHIP_KEYPAD				0x4a
+#define TWL4030_CHIP_MADC				0x4a
+#define TWL4030_CHIP_INTERRUPTS				0x4a
+#define TWL4030_CHIP_LED				0x4a
+#define TWL4030_CHIP_MAIN_CHARGE			0x4a
+#define TWL4030_CHIP_PRECHARGE				0x4a
+#define TWL4030_CHIP_PWM0				0x4a
+#define TWL4030_CHIP_PWM1				0x4a
+#define TWL4030_CHIP_PWMA				0x4a
+#define TWL4030_CHIP_PWMB				0x4a
+/* POWER */
+#define TWL4030_CHIP_BACKUP				0x4b
+#define TWL4030_CHIP_INT				0x4b
+#define TWL4030_CHIP_PM_MASTER				0x4b
+#define TWL4030_CHIP_PM_RECEIVER			0x4b
+#define TWL4030_CHIP_RTC				0x4b
+#define TWL4030_CHIP_SECURED_REG			0x4b
+
+/* Register base addresses */
+
+/* USB */
+#define TWL4030_BASEADD_USB				0x0000
+/* AUD */
+#define TWL4030_BASEADD_AUDIO_VOICE			0x0000
+#define TWL4030_BASEADD_GPIO				0x0098
+#define TWL4030_BASEADD_INTBR				0x0085
+#define TWL4030_BASEADD_PIH				0x0080
+#define TWL4030_BASEADD_TEST				0x004C
+/* AUX */
+#define TWL4030_BASEADD_INTERRUPTS			0x00B9
+#define TWL4030_BASEADD_LED				0x00EE
+#define TWL4030_BASEADD_MADC				0x0000
+#define TWL4030_BASEADD_MAIN_CHARGE			0x0074
+#define TWL4030_BASEADD_PRECHARGE			0x00AA
+#define TWL4030_BASEADD_PWM0				0x00F8
+#define TWL4030_BASEADD_PWM1				0x00FB
+#define TWL4030_BASEADD_PWMA				0x00EF
+#define TWL4030_BASEADD_PWMB				0x00F1
+#define TWL4030_BASEADD_KEYPAD				0x00D2
+/* POWER */
+#define TWL4030_BASEADD_BACKUP				0x0014
+#define TWL4030_BASEADD_INT				0x002E
+#define TWL4030_BASEADD_PM_MASTER			0x0036
+#define TWL4030_BASEADD_PM_RECIEVER			0x005B
+#define TWL4030_BASEADD_RTC				0x001C
+#define TWL4030_BASEADD_SECURED_REG			0x0000
+
+/*
+ * Power Management Master
+ */
+#define TWL4030_PM_MASTER_CFG_P1_TRANSITION		0x36
+#define TWL4030_PM_MASTER_CFG_P2_TRANSITION		0x37
+#define TWL4030_PM_MASTER_CFG_P3_TRANSITION		0x38
+#define TWL4030_PM_MASTER_CFG_P123_TRANSITION		0x39
+#define TWL4030_PM_MASTER_STS_BOOT			0x3A
+#define TWL4030_PM_MASTER_CFG_BOOT			0x3B
+#define TWL4030_PM_MASTER_SHUNDAN			0x3C
+#define TWL4030_PM_MASTER_BOOT_BCI			0x3D
+#define TWL4030_PM_MASTER_CFG_PWRANA1			0x3E
+#define TWL4030_PM_MASTER_CFG_PWRANA2			0x3F
+#define TWL4030_PM_MASTER_BGAP_TRIM			0x40
+#define TWL4030_PM_MASTER_BACKUP_MISC_STS		0x41
+#define TWL4030_PM_MASTER_BACKUP_MISC_CFG		0x42
+#define TWL4030_PM_MASTER_BACKUP_MISC_TST		0x43
+#define TWL4030_PM_MASTER_PROTECT_KEY			0x44
+#define TWL4030_PM_MASTER_STS_HW_CONDITIONS		0x45
+#define TWL4030_PM_MASTER_P1_SW_EVENTS			0x46
+#define TWL4030_PM_MASTER_P2_SW_EVENTS			0x47
+#define TWL4030_PM_MASTER_P3_SW_EVENTS			0x48
+#define TWL4030_PM_MASTER_STS_P123_STATE		0x49
+#define TWL4030_PM_MASTER_PB_CFG			0x4A
+#define TWL4030_PM_MASTER_PB_WORD_MSB			0x4B
+#define TWL4030_PM_MASTER_PB_WORD_LSB			0x4C
+#define TWL4030_PM_MASTER_SEQ_ADD_W2P			0x52
+#define TWL4030_PM_MASTER_SEQ_ADD_P2A			0x53
+#define TWL4030_PM_MASTER_SEQ_ADD_A2W			0x54
+#define TWL4030_PM_MASTER_SEQ_ADD_A2S			0x55
+#define TWL4030_PM_MASTER_SEQ_ADD_S2A12			0x56
+#define TWL4030_PM_MASTER_SEQ_ADD_S2A3			0x57
+#define TWL4030_PM_MASTER_SEQ_ADD_WARM			0x58
+#define TWL4030_PM_MASTER_MEMORY_ADDRESS		0x59
+#define TWL4030_PM_MASTER_MEMORY_DATA			0x5A
+#define TWL4030_PM_MASTER_SC_CONFIG			0x5B
+#define TWL4030_PM_MASTER_SC_DETECT1			0x5C
+#define TWL4030_PM_MASTER_SC_DETECT2			0x5D
+#define TWL4030_PM_MASTER_WATCHDOG_CFG			0x5E
+#define TWL4030_PM_MASTER_IT_CHECK_CFG			0x5F
+#define TWL4030_PM_MASTER_VIBRATOR_CFG			0x60
+#define TWL4030_PM_MASTER_DCDC_GLOBAL_CFG		0x61
+#define TWL4030_PM_MASTER_VDD1_TRIM1			0x62
+#define TWL4030_PM_MASTER_VDD1_TRIM2			0x63
+#define TWL4030_PM_MASTER_VDD2_TRIM1			0x64
+#define TWL4030_PM_MASTER_VDD2_TRIM2			0x65
+#define TWL4030_PM_MASTER_VIO_TRIM1			0x66
+#define TWL4030_PM_MASTER_VIO_TRIM2			0x67
+#define TWL4030_PM_MASTER_MISC_CFG			0x68
+#define TWL4030_PM_MASTER_LS_TST_A			0x69
+#define TWL4030_PM_MASTER_LS_TST_B			0x6A
+#define TWL4030_PM_MASTER_LS_TST_C			0x6B
+#define TWL4030_PM_MASTER_LS_TST_D			0x6C
+#define TWL4030_PM_MASTER_BB_CFG			0x6D
+#define TWL4030_PM_MASTER_MISC_TST			0x6E
+#define TWL4030_PM_MASTER_TRIM1				0x6F
+/* P[1-3]_SW_EVENTS */
+#define TWL4030_PM_MASTER_SW_EVENTS_STOPON_PWRON	(1 << 6)
+#define TWL4030_PM_MASTER_SW_EVENTS_STOPON_SYSEN	(1 << 5)
+#define TWL4030_PM_MASTER_SW_EVENTS_ENABLE_WARMRESET	(1 << 4)
+#define TWL4030_PM_MASTER_SW_EVENTS_LVL_WAKEUP		(1 << 3)
+#define TWL4030_PM_MASTER_SW_EVENTS_DEVACT		(1 << 2)
+#define TWL4030_PM_MASTER_SW_EVENTS_DEVSLP		(1 << 1)
+#define TWL4030_PM_MASTER_SW_EVENTS_DEVOFF		(1 << 0)
+
+/* Power bus message definitions */
+
+/* The TWL4030/5030 splits its power-management resources (the various
+ * regulators, clock and reset lines) into 3 processor groups - P1, P2 and
+ * P3. These groups can then be configured to transition between sleep, wait-on
+ * and active states by sending messages to the power bus.  See Section 5.4.2
+ * Power Resources of TWL4030 TRM
+ */
+
+/* Processor groups */
+#define DEV_GRP_NULL		0x0
+#define DEV_GRP_P1		0x1	/* P1: all OMAP devices */
+#define DEV_GRP_P2		0x2	/* P2: all Modem devices */
+#define DEV_GRP_P3		0x4	/* P3: all peripheral devices */
+
+/* Resource groups */
+#define RES_GRP_RES		0x0	/* Reserved */
+#define RES_GRP_PP		0x1	/* Power providers */
+#define RES_GRP_RC		0x2	/* Reset and control */
+#define RES_GRP_PP_RC		0x3
+#define RES_GRP_PR		0x4	/* Power references */
+#define RES_GRP_PP_PR		0x5
+#define RES_GRP_RC_PR		0x6
+#define RES_GRP_ALL		0x7	/* All resource groups */
+
+#define RES_TYPE2_R0		0x0
+
+#define RES_TYPE_ALL		0x7
+
+/* Resource states */
+#define RES_STATE_WRST		0xF
+#define RES_STATE_ACTIVE	0xE
+#define RES_STATE_SLEEP		0x8
+#define RES_STATE_OFF		0x0
+
+/* Power resources */
+
+/* Power providers */
+#define RES_VAUX1               1
+#define RES_VAUX2               2
+#define RES_VAUX3               3
+#define RES_VAUX4               4
+#define RES_VMMC1               5
+#define RES_VMMC2               6
+#define RES_VPLL1               7
+#define RES_VPLL2               8
+#define RES_VSIM                9
+#define RES_VDAC                10
+#define RES_VINTANA1            11
+#define RES_VINTANA2            12
+#define RES_VINTDIG             13
+#define RES_VIO                 14
+#define RES_VDD1                15
+#define RES_VDD2                16
+#define RES_VUSB_1V5            17
+#define RES_VUSB_1V8            18
+#define RES_VUSB_3V1            19
+#define RES_VUSBCP              20
+#define RES_REGEN               21
+/* Reset and control */
+#define RES_NRES_PWRON          22
+#define RES_CLKEN               23
+#define RES_SYSEN               24
+#define RES_HFCLKOUT            25
+#define RES_32KCLKOUT           26
+#define RES_RESET               27
+/* Power Reference */
+#define RES_Main_Ref            28
+
+#define TOTAL_RESOURCES		28
+/*
+ * Power Bus Message Format ... these can be sent individually by Linux,
+ * but are usually part of downloaded scripts that are run when various
+ * power events are triggered.
+ *
+ *  Broadcast Message (16 Bits):
+ *    DEV_GRP[15:13] MT[12]  RES_GRP[11:9]  RES_TYPE2[8:7] RES_TYPE[6:4]
+ *    RES_STATE[3:0]
+ *
+ *  Singular Message (16 Bits):
+ *    DEV_GRP[15:13] MT[12]  RES_ID[11:4]  RES_STATE[3:0]
+ */
+
+#define MSG_BROADCAST(devgrp, grp, type, type2, state) \
+	((devgrp) << 13 | 1 << 12 | (grp) << 9 | (type2) << 7 \
+	| (type) << 4 | (state))
+
+#define MSG_SINGULAR(devgrp, id, state) \
+	((devgrp) << 13 | 0 << 12 | (id) << 4 | (state))
+
+#define MSG_BROADCAST_ALL(devgrp, state) \
+	((devgrp) << 5 | (state))
+
+#define MSG_BROADCAST_REF MSG_BROADCAST_ALL
+#define MSG_BROADCAST_PROV MSG_BROADCAST_ALL
+#define MSG_BROADCAST__CLK_RST MSG_BROADCAST_ALL
+
+/* Power Managment Receiver */
+#define TWL4030_PM_RECEIVER_SC_CONFIG			0x5B
+#define TWL4030_PM_RECEIVER_SC_DETECT1			0x5C
+#define TWL4030_PM_RECEIVER_SC_DETECT2			0x5D
+#define TWL4030_PM_RECEIVER_WATCHDOG_CFG		0x5E
+#define TWL4030_PM_RECEIVER_IT_CHECK_CFG		0x5F
+#define TWL4030_PM_RECEIVER_VIBRATOR_CFG		0x5F
+#define TWL4030_PM_RECEIVER_DC_TO_DC_CFG		0x61
+#define TWL4030_PM_RECEIVER_VDD1_TRIM1			0x62
+#define TWL4030_PM_RECEIVER_VDD1_TRIM2			0x63
+#define TWL4030_PM_RECEIVER_VDD2_TRIM1			0x64
+#define TWL4030_PM_RECEIVER_VDD2_TRIM2			0x65
+#define TWL4030_PM_RECEIVER_VIO_TRIM1			0x66
+#define TWL4030_PM_RECEIVER_VIO_TRIM2			0x67
+#define TWL4030_PM_RECEIVER_MISC_CFG			0x68
+#define TWL4030_PM_RECEIVER_LS_TST_A			0x69
+#define TWL4030_PM_RECEIVER_LS_TST_B			0x6A
+#define TWL4030_PM_RECEIVER_LS_TST_C			0x6B
+#define TWL4030_PM_RECEIVER_LS_TST_D			0x6C
+#define TWL4030_PM_RECEIVER_BB_CFG			0x6D
+#define TWL4030_PM_RECEIVER_MISC_TST			0x6E
+#define TWL4030_PM_RECEIVER_TRIM1			0x6F
+#define TWL4030_PM_RECEIVER_TRIM2			0x70
+#define TWL4030_PM_RECEIVER_DC_DC_TIMEOUT		0x71
+#define TWL4030_PM_RECEIVER_VAUX1_DEV_GRP		0x72
+#define TWL4030_PM_RECEIVER_VAUX1_TYPE			0x73
+#define TWL4030_PM_RECEIVER_VAUX1_REMAP			0x74
+#define TWL4030_PM_RECEIVER_VAUX1_DEDICATED		0x75
+#define TWL4030_PM_RECEIVER_VAUX2_DEV_GRP		0x76
+#define TWL4030_PM_RECEIVER_VAUX2_TYPE			0x77
+#define TWL4030_PM_RECEIVER_VAUX2_REMAP			0x78
+#define TWL4030_PM_RECEIVER_VAUX2_DEDICATED		0x79
+#define TWL4030_PM_RECEIVER_VAUX3_DEV_GRP		0x7A
+#define TWL4030_PM_RECEIVER_VAUX3_TYPE			0x7B
+#define TWL4030_PM_RECEIVER_VAUX3_REMAP			0x7C
+#define TWL4030_PM_RECEIVER_VAUX3_DEDICATED		0x7D
+#define TWL4030_PM_RECEIVER_VAUX4_DEV_GRP		0x7E
+#define TWL4030_PM_RECEIVER_VAUX4_TYPE			0x7F
+#define TWL4030_PM_RECEIVER_VAUX4_REMAP			0x80
+#define TWL4030_PM_RECEIVER_VAUX4_DEDICATED		0x81
+#define TWL4030_PM_RECEIVER_VMMC1_DEV_GRP		0x82
+#define TWL4030_PM_RECEIVER_VMMC1_TYPE			0x83
+#define TWL4030_PM_RECEIVER_VMMC1_REMAP			0x84
+#define TWL4030_PM_RECEIVER_VMMC1_DEDICATED		0x85
+#define TWL4030_PM_RECEIVER_VMMC2_DEV_GRP		0x86
+#define TWL4030_PM_RECEIVER_VMMC2_TYPE			0x87
+#define TWL4030_PM_RECEIVER_VMMC2_REMAP			0x88
+#define TWL4030_PM_RECEIVER_VMMC2_DEDICATED		0x89
+#define TWL4030_PM_RECEIVER_VPLL1_DEV_GRP		0x8A
+#define TWL4030_PM_RECEIVER_VPLL1_TYPE			0x8B
+#define TWL4030_PM_RECEIVER_VPLL1_REMAP			0x8C
+#define TWL4030_PM_RECEIVER_VPLL1_DEDICATED		0x8D
+#define TWL4030_PM_RECEIVER_VPLL2_DEV_GRP		0x8E
+#define TWL4030_PM_RECEIVER_VPLL2_TYPE			0x8F
+#define TWL4030_PM_RECEIVER_VPLL2_REMAP			0x90
+#define TWL4030_PM_RECEIVER_VPLL2_DEDICATED		0x91
+#define TWL4030_PM_RECEIVER_VSIM_DEV_GRP		0x92
+#define TWL4030_PM_RECEIVER_VSIM_TYPE			0x93
+#define TWL4030_PM_RECEIVER_VSIM_REMAP			0x94
+#define TWL4030_PM_RECEIVER_VSIM_DEDICATED		0x95
+#define TWL4030_PM_RECEIVER_VDAC_DEV_GRP		0x96
+#define TWL4030_PM_RECEIVER_VDAC_TYPE			0x97
+#define TWL4030_PM_RECEIVER_VDAC_REMAP			0x98
+#define TWL4030_PM_RECEIVER_VDAC_DEDICATED		0x99
+#define TWL4030_PM_RECEIVER_VINTANA1_DEV_GRP		0x9A
+#define TWL4030_PM_RECEIVER_VINTANA1_TYP		0x9B
+#define TWL4030_PM_RECEIVER_VINTANA1_REMAP		0x9C
+#define TWL4030_PM_RECEIVER_VINTANA1_DEDICATED		0x9D
+#define TWL4030_PM_RECEIVER_VINTANA2_DEV_GRP		0x9E
+#define TWL4030_PM_RECEIVER_VINTANA2_TYPE		0x9F
+#define TWL4030_PM_RECEIVER_VINTANA2_REMAP		0xA0
+#define TWL4030_PM_RECEIVER_VINTANA2_DEDICATED		0xA1
+#define TWL4030_PM_RECEIVER_VINTDIG_DEV_GRP		0xA2
+#define TWL4030_PM_RECEIVER_VINTDIG_TYPE		0xA3
+#define TWL4030_PM_RECEIVER_VINTDIG_REMAP		0xA4
+#define TWL4030_PM_RECEIVER_VINTDIG_DEDICATED		0xA5
+#define TWL4030_PM_RECEIVER_VIO_DEV_GRP			0xA6
+#define TWL4030_PM_RECEIVER_VIO_TYPE			0xA7
+#define TWL4030_PM_RECEIVER_VIO_REMAP			0xA8
+#define TWL4030_PM_RECEIVER_VIO_CFG			0xA9
+#define TWL4030_PM_RECEIVER_VIO_MISC_CFG		0xAA
+#define TWL4030_PM_RECEIVER_VIO_TEST1			0xAB
+#define TWL4030_PM_RECEIVER_VIO_TEST2			0xAC
+#define TWL4030_PM_RECEIVER_VIO_OSC			0xAD
+#define TWL4030_PM_RECEIVER_VIO_RESERVED		0xAE
+#define TWL4030_PM_RECEIVER_VIO_VSEL			0xAF
+#define TWL4030_PM_RECEIVER_VDD1_DEV_GRP		0xB0
+#define TWL4030_PM_RECEIVER_VDD1_TYPE			0xB1
+#define TWL4030_PM_RECEIVER_VDD1_REMAP			0xB2
+#define TWL4030_PM_RECEIVER_VDD1_CFG			0xB3
+#define TWL4030_PM_RECEIVER_VDD1_MISC_CFG		0xB4
+#define TWL4030_PM_RECEIVER_VDD1_TEST1			0xB5
+#define TWL4030_PM_RECEIVER_VDD1_TEST2			0xB6
+#define TWL4030_PM_RECEIVER_VDD1_OSC			0xB7
+#define TWL4030_PM_RECEIVER_VDD1_RESERVED		0xB8
+#define TWL4030_PM_RECEIVER_VDD1_VSEL			0xB9
+#define TWL4030_PM_RECEIVER_VDD1_VMODE_CFG		0xBA
+#define TWL4030_PM_RECEIVER_VDD1_VFLOOR			0xBB
+#define TWL4030_PM_RECEIVER_VDD1_VROOF			0xBC
+#define TWL4030_PM_RECEIVER_VDD1_STEP			0xBD
+#define TWL4030_PM_RECEIVER_VDD2_DEV_GRP		0xBE
+#define TWL4030_PM_RECEIVER_VDD2_TYPE			0xBF
+#define TWL4030_PM_RECEIVER_VDD2_REMAP			0xC0
+#define TWL4030_PM_RECEIVER_VDD2_CFG			0xC1
+#define TWL4030_PM_RECEIVER_VDD2_MISC_CFG		0xC2
+#define TWL4030_PM_RECEIVER_VDD2_TEST1			0xC3
+#define TWL4030_PM_RECEIVER_VDD2_TEST2			0xC4
+#define TWL4030_PM_RECEIVER_VDD2_OSC			0xC5
+#define TWL4030_PM_RECEIVER_VDD2_RESERVED		0xC6
+#define TWL4030_PM_RECEIVER_VDD2_VSEL			0xC7
+#define TWL4030_PM_RECEIVER_VDD2_VMODE_CFG		0xC8
+#define TWL4030_PM_RECEIVER_VDD2_VFLOOR			0xC9
+#define TWL4030_PM_RECEIVER_VDD2_VROOF			0xCA
+#define TWL4030_PM_RECEIVER_VDD2_STEP			0xCB
+#define TWL4030_PM_RECEIVER_VUSB1V5_DEV_GRP		0xCC
+#define TWL4030_PM_RECEIVER_VUSB1V5_TYPE		0xCD
+#define TWL4030_PM_RECEIVER_VUSB1V5_REMAP		0xCE
+#define TWL4030_PM_RECEIVER_VUSB1V8_DEV_GRP		0xCF
+#define TWL4030_PM_RECEIVER_VUSB1V8_TYPE		0xD0
+#define TWL4030_PM_RECEIVER_VUSB1V8_REMAP		0xD1
+#define TWL4030_PM_RECEIVER_VUSB3V1_DEV_GRP		0xD2
+#define TWL4030_PM_RECEIVER_VUSB3V1_TYPE		0xD3
+#define TWL4030_PM_RECEIVER_VUSB3V1_REMAP		0xD4
+#define TWL4030_PM_RECEIVER_VUSBCP_DEV_GRP		0xD5
+#define TWL4030_PM_RECEIVER_VUSBCP_TYPE			0xD6
+#define TWL4030_PM_RECEIVER_VUSBCP_REMAP		0xD7
+#define TWL4030_PM_RECEIVER_VUSB_DEDICATED1		0xD8
+#define TWL4030_PM_RECEIVER_VUSB_DEDICATED2		0xD9
+#define TWL4030_PM_RECEIVER_REGEN_DEV_GRP		0xDA
+#define TWL4030_PM_RECEIVER_REGEN_TYPE			0xDB
+#define TWL4030_PM_RECEIVER_REGEN_REMAP			0xDC
+#define TWL4030_PM_RECEIVER_NRESPWRON_DEV_GRP		0xDD
+#define TWL4030_PM_RECEIVER_NRESPWRON_TYPE		0xDE
+#define TWL4030_PM_RECEIVER_NRESPWRON_REMAP		0xDF
+#define TWL4030_PM_RECEIVER_CLKEN_DEV_GRP		0xE0
+#define TWL4030_PM_RECEIVER_CLKEN_TYPE			0xE1
+#define TWL4030_PM_RECEIVER_CLKEN_REMAP			0xE2
+#define TWL4030_PM_RECEIVER_SYSEN_DEV_GRP		0xE3
+#define TWL4030_PM_RECEIVER_SYSEN_TYPE			0xE4
+#define TWL4030_PM_RECEIVER_SYSEN_REMAP			0xE5
+#define TWL4030_PM_RECEIVER_HFCLKOUT_DEV_GRP		0xE6
+#define TWL4030_PM_RECEIVER_HFCLKOUT_TYPE		0xE7
+#define TWL4030_PM_RECEIVER_HFCLKOUT_REMAP		0xE8
+#define TWL4030_PM_RECEIVER_32KCLKOUT_DEV_GRP		0xE9
+#define TWL4030_PM_RECEIVER_32KCLKOUT_TYPE		0xEA
+#define TWL4030_PM_RECEIVER_32KCLKOUT_REMAP		0xEB
+#define TWL4030_PM_RECEIVER_TRITON_RESET_DEV_GRP	0xEC
+#define TWL4030_PM_RECEIVER_TRITON_RESET_TYPE		0xED
+#define TWL4030_PM_RECEIVER_TRITON_RESET_REMAP		0xEE
+#define TWL4030_PM_RECEIVER_MAINREF_DEV_GRP		0xEF
+#define TWL4030_PM_RECEIVER_MAINREF_TYPE		0xF0
+#define TWL4030_PM_RECEIVER_MAINREF_REMAP		0xF1
+
+/* Voltage Selection in PM Receiver Module */
+#define TWL4030_PM_RECEIVER_VAUX2_VSEL_18		0x05
+#define TWL4030_PM_RECEIVER_VAUX3_VSEL_28		0x03
+#define TWL4030_PM_RECEIVER_VPLL2_VSEL_18		0x05
+#define TWL4030_PM_RECEIVER_VDAC_VSEL_18		0x03
+#define TWL4030_PM_RECEIVER_VMMC1_VSEL_30		0x02
+#define TWL4030_PM_RECEIVER_VMMC1_VSEL_32		0x03
+#define TWL4030_PM_RECEIVER_VSIM_VSEL_18		0x03
+
+/* Device Selection in PM Receiver Module */
+#define TWL4030_PM_RECEIVER_DEV_GRP_P1			0x20
+#define TWL4030_PM_RECEIVER_DEV_GRP_ALL			0xE0
+
+/* LED */
+#define TWL4030_LED_LEDEN				0xEE
+#define TWL4030_LED_LEDEN_LEDAON			(1 << 0)
+#define TWL4030_LED_LEDEN_LEDBON			(1 << 1)
+#define TWL4030_LED_LEDEN_LEDAPWM			(1 << 4)
+#define TWL4030_LED_LEDEN_LEDBPWM			(1 << 5)
+
+/* Keypad */
+#define TWL4030_KEYPAD_KEYP_CTRL_REG			0xD2
+#define TWL4030_KEYPAD_KEY_DEB_REG			0xD3
+#define TWL4030_KEYPAD_LONG_KEY_REG1			0xD4
+#define TWL4030_KEYPAD_LK_PTV_REG			0xD5
+#define TWL4030_KEYPAD_TIME_OUT_REG1			0xD6
+#define TWL4030_KEYPAD_TIME_OUT_REG2			0xD7
+#define TWL4030_KEYPAD_KBC_REG				0xD8
+#define TWL4030_KEYPAD_KBR_REG				0xD9
+#define TWL4030_KEYPAD_KEYP_SMS				0xDA
+#define TWL4030_KEYPAD_FULL_CODE_7_0			0xDB
+#define TWL4030_KEYPAD_FULL_CODE_15_8			0xDC
+#define TWL4030_KEYPAD_FULL_CODE_23_16			0xDD
+#define TWL4030_KEYPAD_FULL_CODE_31_24			0xDE
+#define TWL4030_KEYPAD_FULL_CODE_39_32			0xDF
+#define TWL4030_KEYPAD_FULL_CODE_47_40			0xE0
+#define TWL4030_KEYPAD_FULL_CODE_55_48			0xE1
+#define TWL4030_KEYPAD_FULL_CODE_63_56			0xE2
+#define TWL4030_KEYPAD_KEYP_ISR1			0xE3
+#define TWL4030_KEYPAD_KEYP_IMR1			0xE4
+#define TWL4030_KEYPAD_KEYP_ISR2			0xE5
+#define TWL4030_KEYPAD_KEYP_IMR2			0xE6
+#define TWL4030_KEYPAD_KEYP_SIR				0xE7
+#define TWL4030_KEYPAD_KEYP_EDR				0xE8
+#define TWL4030_KEYPAD_KEYP_SIH_CTRL			0xE9
+
+#define TWL4030_KEYPAD_CTRL_KBD_ON			(1 << 6)
+#define TWL4030_KEYPAD_CTRL_RP_EN			(1 << 5)
+#define TWL4030_KEYPAD_CTRL_TOLE_EN			(1 << 4)
+#define TWL4030_KEYPAD_CTRL_TOE_EN			(1 << 3)
+#define TWL4030_KEYPAD_CTRL_LK_EN			(1 << 2)
+#define TWL4030_KEYPAD_CTRL_SOFTMODEN			(1 << 1)
+#define TWL4030_KEYPAD_CTRL_SOFT_NRST			(1 << 0)
+
+/* USB */
+#define TWL4030_USB_VENDOR_ID_LO			0x00
+#define TWL4030_USB_VENDOR_ID_HI			0x01
+#define TWL4030_USB_PRODUCT_ID_LO			0x02
+#define TWL4030_USB_PRODUCT_ID_HI			0x03
+#define TWL4030_USB_FUNC_CTRL				0x04
+#define TWL4030_USB_FUNC_CTRL_SET			0x05
+#define TWL4030_USB_FUNC_CTRL_CLR			0x06
+#define TWL4030_USB_IFC_CTRL				0x07
+#define TWL4030_USB_IFC_CTRL_SET			0x08
+#define TWL4030_USB_IFC_CTRL_CLR			0x09
+#define TWL4030_USB_OTG_CTRL				0x0A
+#define TWL4030_USB_OTG_CTRL_SET			0x0B
+#define TWL4030_USB_OTG_CTRL_CLR			0x0C
+#define TWL4030_USB_USB_INT_EN_RISE			0x0D
+#define TWL4030_USB_USB_INT_EN_RISE_SET			0x0E
+#define TWL4030_USB_USB_INT_EN_RISE_CLR			0x0F
+#define TWL4030_USB_USB_INT_EN_FALL			0x10
+#define TWL4030_USB_USB_INT_EN_FALL_SET			0x11
+#define TWL4030_USB_USB_INT_EN_FALL_CLR			0x12
+#define TWL4030_USB_USB_INT_STS				0x13
+#define TWL4030_USB_USB_INT_LATCH			0x14
+#define TWL4030_USB_DEBUG				0x15
+#define TWL4030_USB_SCRATCH_REG				0x16
+#define TWL4030_USB_SCRATCH_REG_SET			0x17
+#define TWL4030_USB_SCRATCH_REG_CLR			0x18
+#define TWL4030_USB_CARKIT_CTRL				0x19
+#define TWL4030_USB_CARKIT_CTRL_SET			0x1A
+#define TWL4030_USB_CARKIT_CTRL_CLR			0x1B
+#define TWL4030_USB_CARKIT_INT_DELAY			0x1C
+#define TWL4030_USB_CARKIT_INT_EN			0x1D
+#define TWL4030_USB_CARKIT_INT_EN_SET			0x1E
+#define TWL4030_USB_CARKIT_INT_EN_CLR			0x1F
+#define TWL4030_USB_CARKIT_INT_STS			0x20
+#define TWL4030_USB_CARKIT_INT_LATCH			0x21
+#define TWL4030_USB_CARKIT_PLS_CTRL			0x22
+#define TWL4030_USB_CARKIT_PLS_CTRL_SET			0x23
+#define TWL4030_USB_CARKIT_PLS_CTRL_CLR			0x24
+#define TWL4030_USB_TRANS_POS_WIDTH			0x25
+#define TWL4030_USB_TRANS_NEG_WIDTH			0x26
+#define TWL4030_USB_RCV_PLTY_RECOVERY			0x27
+#define TWL4030_USB_MCPC_CTRL				0x30
+#define TWL4030_USB_MCPC_CTRL_SET			0x31
+#define TWL4030_USB_MCPC_CTRL_CLR			0x32
+#define TWL4030_USB_MCPC_IO_CTRL			0x33
+#define TWL4030_USB_MCPC_IO_CTRL_SET			0x34
+#define TWL4030_USB_MCPC_IO_CTRL_CLR			0x35
+#define TWL4030_USB_MCPC_CTRL2				0x36
+#define TWL4030_USB_MCPC_CTRL2_SET			0x37
+#define TWL4030_USB_MCPC_CTRL2_CLR			0x38
+#define TWL4030_USB_OTHER_FUNC_CTRL			0x80
+#define TWL4030_USB_OTHER_FUNC_CTRL_SET			0x81
+#define TWL4030_USB_OTHER_FUNC_CTRL_CLR			0x82
+#define TWL4030_USB_OTHER_IFC_CTRL			0x83
+#define TWL4030_USB_OTHER_IFC_CTRL_SET			0x84
+#define TWL4030_USB_OTHER_IFC_CTRL_CLR			0x85
+#define TWL4030_USB_OTHER_INT_EN_RISE_SET		0x87
+#define TWL4030_USB_OTHER_INT_EN_RISE_CLR		0x88
+#define TWL4030_USB_OTHER_INT_EN_FALL			0x89
+#define TWL4030_USB_OTHER_INT_EN_FALL_SET		0x8A
+#define TWL4030_USB_OTHER_INT_EN_FALL_CLR		0x8B
+#define TWL4030_USB_OTHER_INT_STS			0x8C
+#define TWL4030_USB_OTHER_INT_LATCH			0x8D
+#define TWL4030_USB_ID_STATUS				0x96
+#define TWL4030_USB_CARKIT_SM_1_INT_EN			0x97
+#define TWL4030_USB_CARKIT_SM_1_INT_EN_SET		0x98
+#define TWL4030_USB_CARKIT_SM_1_INT_EN_CLR		0x99
+#define TWL4030_USB_CARKIT_SM_1_INT_STS			0x9A
+#define TWL4030_USB_CARKIT_SM_1_INT_LATCH		0x9B
+#define TWL4030_USB_CARKIT_SM_2_INT_EN			0x9C
+#define TWL4030_USB_CARKIT_SM_2_INT_EN_SET		0x9D
+#define TWL4030_USB_CARKIT_SM_2_INT_EN_CLR		0x9E
+#define TWL4030_USB_CARKIT_SM_2_INT_STS			0x9F
+#define TWL4030_USB_CARKIT_SM_2_INT_LATCH		0xA0
+#define TWL4030_USB_CARKIT_SM_CTRL			0xA1
+#define TWL4030_USB_CARKIT_SM_CTRL_SET			0xA2
+#define TWL4030_USB_CARKIT_SM_CTRL_CLR			0xA3
+#define TWL4030_USB_CARKIT_SM_CMD			0xA4
+#define TWL4030_USB_CARKIT_SM_CMD_SET			0xA5
+#define TWL4030_USB_CARKIT_SM_CMD_CLR			0xA6
+#define TWL4030_USB_CARKIT_SM_CMD_STS			0xA7
+#define TWL4030_USB_CARKIT_SM_STATUS			0xA8
+#define TWL4030_USB_CARKIT_SM_ERR_STATUS		0xAA
+#define TWL4030_USB_CARKIT_SM_CTRL_STATE		0xAB
+#define TWL4030_USB_POWER_CTRL				0xAC
+#define TWL4030_USB_POWER_CTRL_SET			0xAD
+#define TWL4030_USB_POWER_CTRL_CLR			0xAE
+#define TWL4030_USB_OTHER_IFC_CTRL2			0xAF
+#define TWL4030_USB_OTHER_IFC_CTRL2_SET			0xB0
+#define TWL4030_USB_OTHER_IFC_CTRL2_CLR			0xB1
+#define TWL4030_USB_REG_CTRL_EN				0xB2
+#define TWL4030_USB_REG_CTRL_EN_SET			0xB3
+#define TWL4030_USB_REG_CTRL_EN_CLR			0xB4
+#define TWL4030_USB_REG_CTRL_ERROR			0xB5
+#define TWL4030_USB_OTHER_FUNC_CTRL2			0xB8
+#define TWL4030_USB_OTHER_FUNC_CTRL2_SET		0xB9
+#define TWL4030_USB_OTHER_FUNC_CTRL2_CLR		0xBA
+#define TWL4030_USB_CARKIT_ANA_CTRL			0xBB
+#define TWL4030_USB_CARKIT_ANA_CTRL_SET			0xBC
+#define TWL4030_USB_CARKIT_ANA_CTRL_CLR			0xBD
+#define TWL4030_USB_VBUS_DEBOUNCE			0xC0
+#define TWL4030_USB_ID_DEBOUNCE				0xC1
+#define TWL4030_USB_TPH_DP_CON_MIN			0xC2
+#define TWL4030_USB_TPH_DP_CON_MAX			0xC3
+#define TWL4030_USB_TCR_DP_CON_MIN			0xC4
+#define TWL4030_USB_TCR_DP_CON_MAX			0xC5
+#define TWL4030_USB_TPH_DP_PD_SHORT			0xC6
+#define TWL4030_USB_TPH_CMD_DLY				0xC7
+#define TWL4030_USB_TPH_DET_RST				0xC8
+#define TWL4030_USB_TPH_AUD_BIAS			0xC9
+#define TWL4030_USB_TCR_UART_DET_MIN			0xCA
+#define TWL4030_USB_TCR_UART_DET_MAX			0xCB
+#define TWL4030_USB_TPH_ID_INT_PW			0xCD
+#define TWL4030_USB_TACC_ID_INT_WAIT			0xCE
+#define TWL4030_USB_TACC_ID_INT_PW			0xCF
+#define TWL4030_USB_TPH_CMD_WAIT			0xD0
+#define TWL4030_USB_TPH_ACK_WAIT			0xD1
+#define TWL4030_USB_TPH_DP_DISC_DET			0xD2
+#define TWL4030_USB_VBAT_TIMER				0xD3
+#define TWL4030_USB_CARKIT_4W_DEBUG			0xE0
+#define TWL4030_USB_CARKIT_5W_DEBUG			0xE1
+#define TWL4030_USB_PHY_PWR_CTRL			0xFD
+#define TWL4030_USB_PHY_CLK_CTRL			0xFE
+#define TWL4030_USB_PHY_CLK_CTRL_STS			0xFF
+
+/* GPIO */
+#define TWL4030_GPIO_GPIODATAIN1			0x00
+#define TWL4030_GPIO_GPIODATAIN2			0x01
+#define TWL4030_GPIO_GPIODATAIN3			0x02
+#define TWL4030_GPIO_GPIODATADIR1			0x03
+#define TWL4030_GPIO_GPIODATADIR2			0x04
+#define TWL4030_GPIO_GPIODATADIR3			0x05
+#define TWL4030_GPIO_GPIODATAOUT1			0x06
+#define TWL4030_GPIO_GPIODATAOUT2			0x07
+#define TWL4030_GPIO_GPIODATAOUT3			0x08
+#define TWL4030_GPIO_CLEARGPIODATAOUT1			0x09
+#define TWL4030_GPIO_CLEARGPIODATAOUT2			0x0A
+#define TWL4030_GPIO_CLEARGPIODATAOUT3			0x0B
+#define TWL4030_GPIO_SETGPIODATAOUT1			0x0C
+#define TWL4030_GPIO_SETGPIODATAOUT2			0x0D
+#define TWL4030_GPIO_SETGPIODATAOUT3			0x0E
+#define TWL4030_GPIO_GPIO_DEBEN1			0x0F
+#define TWL4030_GPIO_GPIO_DEBEN2			0x10
+#define TWL4030_GPIO_GPIO_DEBEN3			0x11
+#define TWL4030_GPIO_GPIO_CTRL				0x12
+#define TWL4030_GPIO_GPIOPUPDCTR1			0x13
+#define TWL4030_GPIO_GPIOPUPDCTR2			0x14
+#define TWL4030_GPIO_GPIOPUPDCTR3			0x15
+#define TWL4030_GPIO_GPIOPUPDCTR4			0x16
+#define TWL4030_GPIO_GPIOPUPDCTR5			0x17
+#define TWL4030_GPIO_GPIO_ISR1A				0x19
+#define TWL4030_GPIO_GPIO_ISR2A				0x1A
+#define TWL4030_GPIO_GPIO_ISR3A				0x1B
+#define TWL4030_GPIO_GPIO_IMR1A				0x1C
+#define TWL4030_GPIO_GPIO_IMR2A				0x1D
+#define TWL4030_GPIO_GPIO_IMR3A				0x1E
+#define TWL4030_GPIO_GPIO_ISR1B				0x1F
+#define TWL4030_GPIO_GPIO_ISR2B				0x20
+#define TWL4030_GPIO_GPIO_ISR3B				0x21
+#define TWL4030_GPIO_GPIO_IMR1B				0x22
+#define TWL4030_GPIO_GPIO_IMR2B				0x23
+#define TWL4030_GPIO_GPIO_IMR3B				0x24
+#define TWL4030_GPIO_GPIO_EDR1				0x28
+#define TWL4030_GPIO_GPIO_EDR2				0x29
+#define TWL4030_GPIO_GPIO_EDR3				0x2A
+#define TWL4030_GPIO_GPIO_EDR4				0x2B
+#define TWL4030_GPIO_GPIO_EDR5				0x2C
+#define TWL4030_GPIO_GPIO_SIH_CTRL			0x2D
+
+/*
+ * Convience functions to read and write from TWL4030
+ *
+ * chip_no is the i2c address, it must be one of the chip addresses
+ *   defined at the top of this file with the prefix TWL4030_CHIP_
+ *   examples are TWL4030_CHIP_PM_RECEIVER and TWL4030_CHIP_KEYPAD
+ *
+ * val is the data either written to or read from the twl4030
+ *
+ * reg is the register to act on, it must be one of the defines
+ *   above and with the format TWL4030_<chip suffix>_<register name>
+ *   examples are TWL4030_PM_RECEIVER_VMMC1_DEV_GRP and
+ *   TWL4030_LED_LEDEN.
+ */
+static inline int twl4030_i2c_write_u8(u8 chip_no, u8 reg, u8 val)
+{
+	return i2c_write(chip_no, reg, 1, &val, 1);
+}
+
+static inline int twl4030_i2c_read_u8(u8 chip_no, u8 reg, u8 *val)
+{
+	return i2c_read(chip_no, reg, 1, val, 1);
+}
+
+/*
+ * Power
+ */
+
+/* For hardware resetting */
+void twl4030_power_reset_init(void);
+/* For setting device group and voltage */
+void twl4030_pmrecv_vsel_cfg(u8 vsel_reg, u8 vsel_val,
+			     u8 dev_grp, u8 dev_grp_sel);
+/* For initializing power device */
+void twl4030_power_init(void);
+/* For initializing mmc power */
+void twl4030_power_mmc_init(void);
+
+/*
+ * LED
+ */
+void twl4030_led_init(unsigned char ledon_mask);
+
+/*
+ * USB
+ */
+int twl4030_usb_ulpi_init(void);
+
+#endif /* TWL4030_H */
diff --git a/qemu/roms/u-boot/include/twl6030.h b/qemu/roms/u-boot/include/twl6030.h
new file mode 100644
index 000000000..7898699ea
--- /dev/null
+++ b/qemu/roms/u-boot/include/twl6030.h
@@ -0,0 +1,173 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef TWL6030_H
+#define TWL6030_H
+
+#include <common.h>
+#include <i2c.h>
+
+/* I2C chip addresses */
+#define TWL6030_CHIP_PM		0x48
+
+#define TWL6030_CHIP_USB	0x49
+#define TWL6030_CHIP_ADC	0x49
+#define TWL6030_CHIP_CHARGER	0x49
+#define TWL6030_CHIP_PWM	0x49
+
+/* Slave Address 0x48 */
+#define VMMC_CFG_STATE		0x9A
+#define VMMC_CFG_VOLTATE	0x9B
+#define VUSB_CFG_STATE		0xA2
+
+#define MISC1			0xE4
+#define VAC_MEAS		(1 << 2)
+#define VBAT_MEAS		(1 << 1)
+#define BB_MEAS			(1 << 0)
+
+#define MISC2			0xE5
+
+/* Slave Address 0x49 */
+
+/* Battery CHARGER REGISTERS */
+#define CONTROLLER_INT_MASK	0xE0
+#define CONTROLLER_CTRL1	0xE1
+#define CONTROLLER_WDG		0xE2
+#define CONTROLLER_STAT1	0xE3
+#define CHARGERUSB_INT_STATUS	0xE4
+#define CHARGERUSB_INT_MASK	0xE5
+#define CHARGERUSB_STATUS_INT1	0xE6
+#define CHARGERUSB_STATUS_INT2	0xE7
+#define CHARGERUSB_CTRL1	0xE8
+#define CHARGERUSB_CTRL2	0xE9
+#define CHARGERUSB_CTRL3	0xEA
+#define CHARGERUSB_STAT1	0xEB
+#define CHARGERUSB_VOREG	0xEC
+#define CHARGERUSB_VICHRG	0xED
+#define CHARGERUSB_CINLIMIT	0xEE
+#define CHARGERUSB_CTRLLIMIT1	0xEF
+
+/* CHARGERUSB_VICHRG */
+#define CHARGERUSB_VICHRG_500		0x4
+#define CHARGERUSB_VICHRG_1500		0xE
+/* CHARGERUSB_CINLIMIT */
+#define CHARGERUSB_CIN_LIMIT_100	0x1
+#define CHARGERUSB_CIN_LIMIT_300	0x5
+#define CHARGERUSB_CIN_LIMIT_500	0x9
+#define CHARGERUSB_CIN_LIMIT_NONE	0xF
+/* CONTROLLER_INT_MASK */
+#define MVAC_FAULT		(1 << 6)
+#define MAC_EOC			(1 << 5)
+#define MBAT_REMOVED		(1 << 4)
+#define MFAULT_WDG		(1 << 3)
+#define MBAT_TEMP		(1 << 2)
+#define MVBUS_DET		(1 << 1)
+#define MVAC_DET		(1 << 0)
+/* CHARGERUSB_INT_MASK */
+#define MASK_MCURRENT_TERM		(1 << 3)
+#define MASK_MCHARGERUSB_STAT		(1 << 2)
+#define MASK_MCHARGERUSB_THMREG		(1 << 1)
+#define MASK_MCHARGERUSB_FAULT		(1 << 0)
+/* CHARGERUSB_VOREG */
+#define CHARGERUSB_VOREG_3P52		0x01
+#define CHARGERUSB_VOREG_4P0		0x19
+#define CHARGERUSB_VOREG_4P2		0x23
+#define CHARGERUSB_VOREG_4P76		0x3F
+/* CHARGERUSB_CTRL1 */
+#define SUSPEND_BOOT		(1 << 7)
+#define OPA_MODE		(1 << 6)
+#define HZ_MODE			(1 << 5)
+#define TERM			(1 << 4)
+/* CHARGERUSB_CTRL2 */
+#define CHARGERUSB_CTRL2_VITERM_50	(0 << 5)
+#define CHARGERUSB_CTRL2_VITERM_100	(1 << 5)
+#define CHARGERUSB_CTRL2_VITERM_150	(2 << 5)
+#define CHARGERUSB_CTRL2_VITERM_400	(7 << 5)
+/* CONTROLLER_CTRL1 */
+#define CONTROLLER_CTRL1_EN_CHARGER	(1 << 4)
+#define CONTROLLER_CTRL1_SEL_CHARGER	(1 << 3)
+/* CONTROLLER_STAT1 */
+#define CHRG_EXTCHRG_STATZ	(1 << 7)
+#define CHRG_DET_N		(1 << 5)
+#define VAC_DET			(1 << 3)
+#define VBUS_DET		(1 << 2)
+
+#define FG_REG_10	0xCA
+#define FG_REG_11	0xCB
+
+#define TOGGLE1		0x90
+#define FGS		(1 << 5)
+#define FGR		(1 << 4)
+#define GPADCS		(1 << 1)
+#define GPADCR		(1 << 0)
+
+#define CTRL_P2		0x34
+#define CTRL_P2_SP2	(1 << 2)
+#define CTRL_P2_EOCP2	(1 << 1)
+#define CTRL_P2_BUSY	(1 << 0)
+
+#define TWL6032_CTRL_P1	0x36
+#define CTRL_P1_SP1	(1 << 3)
+
+#define GPCH0_LSB	0x57
+#define GPCH0_MSB	0x58
+
+#define TWL6032_GPCH0_LSB	0x3b
+
+#define TWL6032_GPSELECT_ISB	0x35
+
+#define USB_PRODUCT_ID_LSB	0x02
+
+#define TWL6030_GPADC_VBAT_CHNL	0x07
+#define TWL6032_GPADC_VBAT_CHNL	0x12
+
+#define TWL6030_GPADC_CTRL	0x2e
+#define TWL6032_GPADC_CTRL2	0x2f
+#define GPADC_CTRL2_CH18_SCALER_EN	(1 << 2)
+#define GPADC_CTRL_SCALER_DIV4		(1 << 3)
+
+#define TWL6030_VBAT_MULT	40 * 1000
+#define TWL6032_VBAT_MULT	25 * 1000
+
+#define TWL6030_VBAT_SHIFT	(10 + 3)
+#define TWL6032_VBAT_SHIFT	(12 + 2)
+
+enum twl603x_chip_type{
+	chip_TWL6030,
+	chip_TWL6032,
+	chip_TWL603X_cnt
+};
+
+struct twl6030_data{
+	u8 chip_type;
+	u8 adc_rbase;
+	u8 adc_ctrl;
+	u8 adc_enable;
+	int vbat_mult;
+	int vbat_shift;
+};
+
+/* Functions to read and write from TWL6030 */
+static inline int twl6030_i2c_write_u8(u8 chip_no, u8 reg, u8 val)
+{
+	return i2c_write(chip_no, reg, 1, &val, 1);
+}
+
+static inline int twl6030_i2c_read_u8(u8 chip_no, u8 reg, u8 *val)
+{
+	return i2c_read(chip_no, reg, 1, val, 1);
+}
+
+void twl6030_init_battery_charging(void);
+void twl6030_usb_device_settings(void);
+void twl6030_start_usb_charging(void);
+void twl6030_stop_usb_charging(void);
+int twl6030_get_battery_voltage(void);
+int twl6030_get_battery_current(void);
+void twl6030_power_mmc_init(void);
+
+#endif /* TWL6030_H */
diff --git a/qemu/roms/u-boot/include/tws.h b/qemu/roms/u-boot/include/tws.h
new file mode 100644
index 000000000..7dd526812
--- /dev/null
+++ b/qemu/roms/u-boot/include/tws.h
@@ -0,0 +1,21 @@
+/*
+ * (C) Copyright 2009
+ * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _TWS_H_
+#define _TWS_H_
+
+/*
+ * Read/Write interface:
+ *   buffer:  Where to read/write the data
+ *   len:     How many bits to read/write
+ *
+ *   Returns: 0 on success, not 0 on failure
+ */
+int tws_read(uchar *buffer, int len);
+int tws_write(uchar *buffer, int len);
+
+#endif	/* _TWS_H_ */
diff --git a/qemu/roms/u-boot/include/u-boot/crc.h b/qemu/roms/u-boot/include/u-boot/crc.h
new file mode 100644
index 000000000..754ac729c
--- /dev/null
+++ b/qemu/roms/u-boot/include/u-boot/crc.h
@@ -0,0 +1,28 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _UBOOT_CRC_H
+#define _UBOOT_CRC_H
+
+/* lib/crc32.c */
+uint32_t crc32 (uint32_t, const unsigned char *, uint);
+uint32_t crc32_wd (uint32_t, const unsigned char *, uint, uint);
+uint32_t crc32_no_comp (uint32_t, const unsigned char *, uint);
+
+/**
+ * crc32_wd_buf - Perform CRC32 on a buffer and return result in buffer
+ *
+ * @input:	Input buffer
+ * @ilen:	Input buffer length
+ * @output:	Place to put checksum result (4 bytes)
+ * @chunk_sz:	Trigger watchdog after processing this many bytes
+ */
+void crc32_wd_buf(const unsigned char *input, uint ilen,
+		    unsigned char *output, uint chunk_sz);
+
+#endif /* _UBOOT_CRC_H */
diff --git a/qemu/roms/u-boot/include/u-boot/md5.h b/qemu/roms/u-boot/include/u-boot/md5.h
new file mode 100644
index 000000000..e09c16a6e
--- /dev/null
+++ b/qemu/roms/u-boot/include/u-boot/md5.h
@@ -0,0 +1,34 @@
+/*
+ * This file was transplanted with slight modifications from Linux sources
+ * (fs/cifs/md5.h) into U-Boot by Bartlomiej Sieka <tur@semihalf.com>.
+ */
+
+#ifndef _MD5_H
+#define _MD5_H
+
+#include "compiler.h"
+
+struct MD5Context {
+	__u32 buf[4];
+	__u32 bits[2];
+	union {
+		unsigned char in[64];
+		__u32 in32[16];
+	};
+};
+
+/*
+ * Calculate and store in 'output' the MD5 digest of 'len' bytes at
+ * 'input'. 'output' must have enough space to hold 16 bytes.
+ */
+void md5 (unsigned char *input, int len, unsigned char output[16]);
+
+/*
+ * Calculate and store in 'output' the MD5 digest of 'len' bytes at 'input'.
+ * 'output' must have enough space to hold 16 bytes. If 'chunk' Trigger the
+ * watchdog every 'chunk_sz' bytes of input processed.
+ */
+void md5_wd (unsigned char *input, int len, unsigned char output[16],
+		unsigned int chunk_sz);
+
+#endif /* _MD5_H */
diff --git a/qemu/roms/u-boot/include/u-boot/u-boot.lds.h b/qemu/roms/u-boot/include/u-boot/u-boot.lds.h
new file mode 100644
index 000000000..ead37d069
--- /dev/null
+++ b/qemu/roms/u-boot/include/u-boot/u-boot.lds.h
@@ -0,0 +1,25 @@
+/*
+ * Linker script helper macros
+ *
+ * Copyright (c) 2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __U_BOOT_LDS__
+#define __U_BOOT_LDS__
+
+/* See if the linker version is at least the specified version */
+#define LD_AT_LEAST(major, minor) \
+	((major > LD_MAJOR) || (major == LD_MAJOR && minor <= LD_MINOR))
+
+/*
+ * Linker versions prior to 2.16 don't understand the builtin
+ * functions SORT_BY_ALIGNMENT() and SORT_BY_NAME(), so disable these
+ */
+#if !LD_AT_LEAST(2, 16)
+# define SORT_BY_ALIGNMENT(x) x
+# define SORT_BY_NAME(x) x
+#endif
+
+#endif
diff --git a/qemu/roms/u-boot/include/u-boot/zlib.h b/qemu/roms/u-boot/include/u-boot/zlib.h
new file mode 100644
index 000000000..e23ceb50c
--- /dev/null
+++ b/qemu/roms/u-boot/include/u-boot/zlib.h
@@ -0,0 +1,731 @@
+/*
+ * This file is derived from zlib.h and zconf.h from the zlib-1.2.3
+ * distribution by Jean-loup Gailly and Mark Adler, with some additions
+ * by Paul Mackerras to aid in implementing Deflate compression and
+ * decompression for PPP packets.
+ */
+
+ /*
+  * ==FILEVERSION 960122==
+  *
+  * This marker is used by the Linux installation script to determine
+  * whether an up-to-date version of this file is already installed.
+  */
+
+/* zlib.h -- interface of the 'zlib' general purpose compression library
+  version 1.2.3, July 18th, 2005
+
+  Copyright (C) 1995-2005 Jean-loup Gailly and Mark Adler
+
+  This software is provided 'as-is', without any express or implied
+  warranty.  In no event will the authors be held liable for any damages
+  arising from the use of this software.
+
+  Permission is granted to anyone to use this software for any purpose,
+  including commercial applications, and to alter it and redistribute it
+  freely, subject to the following restrictions:
+
+  1. The origin of this software must not be misrepresented; you must not
+     claim that you wrote the original software. If you use this software
+     in a product, an acknowledgment in the product documentation would be
+     appreciated but is not required.
+  2. Altered source versions must be plainly marked as such, and must not be
+     misrepresented as being the original software.
+  3. This notice may not be removed or altered from any source distribution.
+
+  Jean-loup Gailly        Mark Adler
+  jloup@gzip.org          madler@alumni.caltech.edu
+
+
+  The data format used by the zlib library is described by RFCs (Request for
+  Comments) 1950 to 1952 in the files http://www.ietf.org/rfc/rfc1950.txt
+  (zlib format), rfc1951.txt (deflate format) and rfc1952.txt (gzip format).
+*/
+
+#ifndef ZLIB_H
+#define ZLIB_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define ZLIB_VERSION "1.2.3"
+#define ZLIB_VERNUM 0x1230
+
+/* #include "zconf.h" */        /* included directly here */
+/* zconf.h -- configuration of the zlib compression library
+ * Copyright (C) 1995-2005 Jean-loup Gailly.
+ * For conditions of distribution and use, see copyright notice in zlib.h
+ */
+
+/* Begin of new zconf.h */
+/*
+ * If you *really* need a unique prefix for all types and library functions,
+ * compile with -DZ_PREFIX. The "standard" zlib should be compiled without it.
+ */
+#ifdef Z_PREFIX
+#  define deflateInit_          z_deflateInit_
+#  define deflate               z_deflate
+#  define deflateEnd            z_deflateEnd
+#  define inflateInit_          z_inflateInit_
+#  define inflate               z_inflate
+#  define inflateEnd            z_inflateEnd
+#  define deflateInit2_         z_deflateInit2_
+#  define deflateSetDictionary  z_deflateSetDictionary
+#  define deflateCopy           z_deflateCopy
+#  define deflateReset          z_deflateReset
+#  define deflateParams         z_deflateParams
+#  define deflateBound          z_deflateBound
+#  define deflatePrime          z_deflatePrime
+#  define inflateInit2_         z_inflateInit2_
+#  define inflateSetDictionary  z_inflateSetDictionary
+#  define inflateSync           z_inflateSync
+#  define inflateSyncPoint      z_inflateSyncPoint
+#  define inflateCopy           z_inflateCopy
+#  define inflateReset          z_inflateReset
+#  define inflateBack           z_inflateBack
+#  define inflateBackEnd        z_inflateBackEnd
+#  define compress              z_compress
+#  define compress2             z_compress2
+#  define compressBound         z_compressBound
+#  define uncompress            z_uncompress
+#  define adler32               z_adler32
+#  define crc32                 z_crc32
+#  define get_crc_table         z_get_crc_table
+#  define zError                z_zError
+
+#  define alloc_func            z_alloc_func
+#  define free_func             z_free_func
+#  define in_func               z_in_func
+#  define out_func              z_out_func
+#  define Byte                  z_Byte
+#  define uInt                  z_uInt
+#  define uLong                 z_uLong
+#  define Bytef                 z_Bytef
+#  define charf                 z_charf
+#  define intf                  z_intf
+#  define uIntf                 z_uIntf
+#  define uLongf                z_uLongf
+#  define voidpf                z_voidpf
+#  define voidp                 z_voidp
+#endif
+
+#if defined(__MSDOS__) && !defined(MSDOS)
+#  define MSDOS
+#endif
+#if (defined(OS_2) || defined(__OS2__)) && !defined(OS2)
+#  define OS2
+#endif
+#if defined(_WINDOWS) && !defined(WINDOWS)
+#  define WINDOWS
+#endif
+#if defined(_WIN32) || defined(_WIN32_WCE) || defined(__WIN32__)
+#  ifndef WIN32
+#    define WIN32
+#  endif
+#endif
+#if (defined(MSDOS) || defined(OS2) || defined(WINDOWS)) && !defined(WIN32)
+#  if !defined(__GNUC__) && !defined(__FLAT__) && !defined(__386__)
+#    ifndef SYS16BIT
+#      define SYS16BIT
+#    endif
+#  endif
+#endif
+
+/*
+ * Compile with -DMAXSEG_64K if the alloc function cannot allocate more
+ * than 64k bytes at a time (needed on systems with 16-bit int).
+ */
+#ifdef SYS16BIT
+#  define MAXSEG_64K
+#endif
+#ifdef MSDOS
+#  define UNALIGNED_OK
+#endif
+
+#ifdef __STDC_VERSION__
+#  ifndef STDC
+#    define STDC
+#  endif
+#  if __STDC_VERSION__ >= 199901L
+#    ifndef STDC99
+#      define STDC99
+#    endif
+#  endif
+#endif
+#if !defined(STDC) && (defined(__STDC__) || defined(__cplusplus))
+#  define STDC
+#endif
+#if !defined(STDC) && (defined(__GNUC__) || defined(__BORLANDC__))
+#  define STDC
+#endif
+#if !defined(STDC) && (defined(MSDOS) || defined(WINDOWS) || defined(WIN32))
+#  define STDC
+#endif
+#if !defined(STDC) && (defined(OS2) || defined(__HOS_AIX__))
+#  define STDC
+#endif
+
+#if defined(__OS400__) && !defined(STDC)    /* iSeries (formerly AS/400). */
+#  define STDC
+#endif
+
+#ifndef STDC
+#  ifndef const /* cannot use !defined(STDC) && !defined(const) on Mac */
+#    define const       /* note: need a more gentle solution here */
+#  endif
+#endif
+
+/* Some Mac compilers merge all .h files incorrectly: */
+#if defined(__MWERKS__)||defined(applec)||defined(THINK_C)||defined(__SC__)
+#  define NO_DUMMY_DECL
+#endif
+
+/* Maximum value for memLevel in deflateInit2 */
+#ifndef MAX_MEM_LEVEL
+#  ifdef MAXSEG_64K
+#    define MAX_MEM_LEVEL 8
+#  else
+#    define MAX_MEM_LEVEL 9
+#  endif
+#endif
+
+/* Maximum value for windowBits in deflateInit2 and inflateInit2.
+ * WARNING: reducing MAX_WBITS makes minigzip unable to extract .gz files
+ * created by gzip. (Files created by minigzip can still be extracted by
+ * gzip.)
+ */
+#ifndef MAX_WBITS
+#  define MAX_WBITS   15 /* 32K LZ77 window */
+#endif
+
+/* The memory requirements for deflate are (in bytes):
+            (1 << (windowBits+2)) +  (1 << (memLevel+9))
+ that is: 128K for windowBits=15  +  128K for memLevel = 8  (default values)
+ plus a few kilobytes for small objects. For example, if you want to reduce
+ the default memory requirements from 256K to 128K, compile with
+     make CFLAGS="-O -DMAX_WBITS=14 -DMAX_MEM_LEVEL=7"
+ Of course this will generally degrade compression (there's no free lunch).
+
+   The memory requirements for inflate are (in bytes) 1 << windowBits
+ that is, 32K for windowBits=15 (default value) plus a few kilobytes
+ for small objects.
+*/
+
+                        /* Type declarations */
+
+#ifndef OF /* function prototypes */
+#  ifdef STDC
+#    define OF(args)  args
+#  else
+#    define OF(args)  ()
+#  endif
+#endif
+
+/* The following definitions for FAR are needed only for MSDOS mixed
+ * model programming (small or medium model with some far allocations).
+ * This was tested only with MSC; for other MSDOS compilers you may have
+ * to define NO_MEMCPY in zutil.h.  If you don't need the mixed model,
+ * just define FAR to be empty.
+ */
+#ifdef SYS16BIT
+#  if defined(M_I86SM) || defined(M_I86MM)
+     /* MSC small or medium model */
+#    define SMALL_MEDIUM
+#    ifdef _MSC_VER
+#      define FAR _far
+#    else
+#      define FAR far
+#    endif
+#  endif
+#  if (defined(__SMALL__) || defined(__MEDIUM__))
+     /* Turbo C small or medium model */
+#    define SMALL_MEDIUM
+#    ifdef __BORLANDC__
+#      define FAR _far
+#    else
+#      define FAR far
+#    endif
+#  endif
+#endif
+
+#if defined(WINDOWS) || defined(WIN32)
+   /* If building or using zlib as a DLL, define ZLIB_DLL.
+    * This is not mandatory, but it offers a little performance increase.
+    */
+#  ifdef ZLIB_DLL
+#    if defined(WIN32) && (!defined(__BORLANDC__) || (__BORLANDC__ >= 0x500))
+#      ifdef ZLIB_INTERNAL
+#        define ZEXTERN extern __declspec(dllexport)
+#      else
+#        define ZEXTERN extern __declspec(dllimport)
+#      endif
+#    endif
+#  endif  /* ZLIB_DLL */
+   /* If building or using zlib with the WINAPI/WINAPIV calling convention,
+    * define ZLIB_WINAPI.
+    * Caution: the standard ZLIB1.DLL is NOT compiled using ZLIB_WINAPI.
+    */
+#  ifdef ZLIB_WINAPI
+#    ifdef FAR
+#      undef FAR
+#    endif
+#    include <windows.h>
+     /* No need for _export, use ZLIB.DEF instead. */
+     /* For complete Windows compatibility, use WINAPI, not __stdcall. */
+#    define ZEXPORT WINAPI
+#    ifdef WIN32
+#      define ZEXPORTVA WINAPIV
+#    else
+#      define ZEXPORTVA FAR CDECL
+#    endif
+#  endif
+#endif
+
+#if defined (__BEOS__)
+#  ifdef ZLIB_DLL
+#    ifdef ZLIB_INTERNAL
+#      define ZEXPORT   __declspec(dllexport)
+#      define ZEXPORTVA __declspec(dllexport)
+#    else
+#      define ZEXPORT   __declspec(dllimport)
+#      define ZEXPORTVA __declspec(dllimport)
+#    endif
+#  endif
+#endif
+
+#ifndef ZEXTERN
+#  define ZEXTERN extern
+#endif
+#ifndef ZEXPORT
+#  define ZEXPORT
+#endif
+#ifndef ZEXPORTVA
+#  define ZEXPORTVA
+#endif
+
+#ifndef FAR
+#  define FAR
+#endif
+
+#if !defined(__MACTYPES__)
+typedef unsigned char  Byte;  /* 8 bits */
+#endif
+typedef unsigned int   uInt;  /* 16 bits or more */
+typedef unsigned long  uLong; /* 32 bits or more */
+
+#ifdef SMALL_MEDIUM
+   /* Borland C/C++ and some old MSC versions ignore FAR inside typedef */
+#  define Bytef Byte FAR
+#else
+   typedef Byte  FAR Bytef;
+#endif
+typedef char  FAR charf;
+typedef int   FAR intf;
+typedef uInt  FAR uIntf;
+typedef uLong FAR uLongf;
+
+#ifdef STDC
+   typedef void const *voidpc;
+   typedef void FAR   *voidpf;
+   typedef void       *voidp;
+#else
+   typedef Byte const *voidpc;
+   typedef Byte FAR   *voidpf;
+   typedef Byte       *voidp;
+#endif
+
+#  ifdef VMS
+#    include <unixio.h>   /* for off_t */
+#  endif
+#  define z_off_t off_t
+#ifndef SEEK_SET
+#  define SEEK_SET        0       /* Seek from beginning of file.  */
+#  define SEEK_CUR        1       /* Seek from current position.  */
+#  define SEEK_END        2       /* Set file pointer to EOF plus "offset" */
+#endif
+#ifndef z_off_t
+#  define z_off_t long
+#endif
+
+#if defined(__OS400__)
+#  define NO_vsnprintf
+#endif
+
+#if defined(__MVS__)
+#  define NO_vsnprintf
+#  ifdef FAR
+#    undef FAR
+#  endif
+#endif
+
+/* MVS linker does not support external names larger than 8 bytes */
+#if defined(__MVS__)
+#   pragma map(deflateInit_,"DEIN")
+#   pragma map(deflateInit2_,"DEIN2")
+#   pragma map(deflateEnd,"DEEND")
+#   pragma map(deflateBound,"DEBND")
+#   pragma map(inflateInit_,"ININ")
+#   pragma map(inflateInit2_,"ININ2")
+#   pragma map(inflateEnd,"INEND")
+#   pragma map(inflateSync,"INSY")
+#   pragma map(inflateSetDictionary,"INSEDI")
+#   pragma map(compressBound,"CMBND")
+#   pragma map(inflate_table,"INTABL")
+#   pragma map(inflate_fast,"INFA")
+#   pragma map(inflate_copyright,"INCOPY")
+#endif
+/* End of new zconf.h */
+
+/*
+     The 'zlib' compression library provides in-memory compression and
+  decompression functions, including integrity checks of the uncompressed
+  data.  This version of the library supports only one compression method
+  (deflation) but other algorithms will be added later and will have the same
+  stream interface.
+
+     Compression can be done in a single step if the buffers are large
+  enough (for example if an input file is mmap'ed), or can be done by
+  repeated calls of the compression function.  In the latter case, the
+  application must provide more input and/or consume the output
+  (providing more output space) before each call.
+
+     The compressed data format used by default by the in-memory functions is
+  the zlib format, which is a zlib wrapper documented in RFC 1950, wrapped
+  around a deflate stream, which is itself documented in RFC 1951.
+
+     The library also supports reading and writing files in gzip (.gz) format
+  with an interface similar to that of stdio using the functions that start
+  with "gz".  The gzip format is different from the zlib format.  gzip is a
+  gzip wrapper, documented in RFC 1952, wrapped around a deflate stream.
+
+     This library can optionally read and write gzip streams in memory as well.
+
+     The zlib format was designed to be compact and fast for use in memory
+  and on communications channels.  The gzip format was designed for single-
+  file compression on file systems, has a larger header than zlib to maintain
+  directory information, and uses a different, slower check method than zlib.
+
+     The library does not install any signal handler. The decoder checks
+  the consistency of the compressed data, so the library should never
+  crash even in case of corrupted input.
+*/
+
+typedef voidpf (*alloc_func) OF((voidpf opaque, uInt items, uInt size));
+typedef void   (*free_func)  OF((voidpf opaque, voidpf address, uInt size));
+typedef void   (*cb_func)    OF((Bytef *buf, uInt len));
+
+struct internal_state;
+
+typedef struct z_stream_s {
+	Bytef	*next_in; /* next input byte */
+	uInt	avail_in; /* number of bytes available at next_in */
+	uLong	total_in; /* total nb of input bytes read so far */
+	Bytef	*next_out; /* next output byte should be put there */
+	uInt	avail_out; /* remaining free space at next_out */
+	uLong	total_out; /* total nb of bytes output so far */
+	char	*msg;	/* last error message, NULL if no error */
+	struct	internal_state FAR *state; /* not visible by applications */
+	alloc_func	zalloc;	/* used to allocate the internal state */
+	free_func	zfree;	/* used to free the internal state */
+	voidpf	opaque;	/* private data object passed to zalloc and zfree */
+	int	data_type;	/* best guess about the data type:
+					binary or text */
+	cb_func	outcb;	/* called regularly just before blocks of output */
+	uLong	adler;	/* adler32 value of the uncompressed data */
+	uLong	reserved;	/* reserved for future use */
+} z_stream;
+
+typedef z_stream FAR *z_streamp;
+
+/*
+     gzip header information passed to and from zlib routines.  See RFC 1952
+  for more details on the meanings of these fields.
+*/
+typedef struct gz_header_s {
+	int	text;	/* true if compressed data believed to be text */
+	uLong	time;	/* modification time */
+	int	xflags;	/* extra flags (not used when writing a gzip file) */
+	int	os;	/* operating system */
+	Bytef	*extra;	/* pointer to extra field or Z_NULL if none */
+	uInt	extra_len; /* extra field length (valid if extra != Z_NULL) */
+	uInt	extra_max; /* space at extra (only when reading header) */
+	Bytef	*name; /* pointer to zero-terminated file name or Z_NULL */
+	uInt	name_max; /* space at name (only when reading header) */
+	Bytef	*comment; /* pointer to zero-terminated comment or Z_NULL */
+	uInt	comm_max; /* space at comment (only when reading header) */
+	int	hcrc; /* true if there was or will be a header crc */
+	int	done; /* true when done reading gzip header (not used
+			when writing a gzip file) */
+} gz_header;
+
+typedef gz_header FAR *gz_headerp;
+
+                        /* constants */
+#define Z_NO_FLUSH      0
+#define Z_PARTIAL_FLUSH 1 /* will be removed, use Z_SYNC_FLUSH instead */
+#define Z_SYNC_FLUSH    2
+#define Z_FULL_FLUSH    3
+#define Z_FINISH        4
+#define Z_BLOCK         5
+/* Allowed flush values; see deflate() and inflate() below for details */
+
+#define Z_OK            0
+#define Z_STREAM_END    1
+#define Z_NEED_DICT     2
+#define Z_ERRNO        (-1)
+#define Z_STREAM_ERROR (-2)
+#define Z_DATA_ERROR   (-3)
+#define Z_MEM_ERROR    (-4)
+#define Z_BUF_ERROR    (-5)
+#define Z_VERSION_ERROR (-6)
+/* Return codes for the compression/decompression functions. Negative
+ * values are errors, positive values are used for special but normal events.
+ */
+
+#define Z_NO_COMPRESSION         0
+#define Z_BEST_SPEED             1
+#define Z_BEST_COMPRESSION       9
+#define Z_DEFAULT_COMPRESSION  (-1)
+/* compression levels */
+
+#define Z_FILTERED            1
+#define Z_HUFFMAN_ONLY        2
+#define Z_RLE                 3
+#define Z_FIXED               4
+#define Z_DEFAULT_STRATEGY    0
+/* compression strategy; see deflateInit2() below for details */
+
+#define Z_BINARY   0
+#define Z_TEXT     1
+#define Z_ASCII    Z_TEXT   /* for compatibility with 1.2.2 and earlier */
+#define Z_UNKNOWN  2
+/* Possible values of the data_type field (though see inflate()) */
+
+#define Z_DEFLATED   8
+/* The deflate compression method (the only one supported in this version) */
+
+#define Z_NULL  (void *)0  /* for initializing zalloc, zfree, opaque */
+
+                        /* basic functions */
+
+/* The application can compare zlibVersion and ZLIB_VERSION for consistency.
+   If the first character differs, the library code actually used is
+   not compatible with the zlib.h header file used by the application.
+   This check is automatically made by deflateInit and inflateInit.
+   */
+
+ZEXTERN int ZEXPORT deflate OF((z_streamp strm, int flush));
+ZEXTERN int ZEXPORT deflateInit_ OF((z_streamp strm, int level,
+			const char *version, int stream_size));
+ZEXTERN int ZEXPORT deflateEnd OF((z_streamp strm));
+ZEXTERN int ZEXPORT deflateInit2_ OF((z_streamp strm, int  level, int  method,
+			int windowBits, int memLevel,
+			int strategy, const char *version,
+			int stream_size));
+ZEXTERN int ZEXPORT deflateReset OF((z_streamp strm));
+ZEXTERN int ZEXPORT deflateSetDictionary OF((z_streamp strm,
+			const Bytef *dictionary,
+			uInt  dictLength));
+ZEXTERN int ZEXPORT deflateSetHeader OF((z_streamp strm,
+			gz_headerp head));
+ZEXTERN int ZEXPORT deflatePrime OF((z_streamp strm,
+			int bits,
+			int value));
+ZEXTERN int ZEXPORT deflateParams OF((z_streamp strm,
+			int level,
+			int strategy));
+ZEXTERN int ZEXPORT deflateTune OF((z_streamp strm,
+			int good_length,
+			int max_lazy,
+			int nice_length,
+			int max_chain));
+ZEXTERN uLong ZEXPORT deflateBound OF((z_streamp strm,
+			uLong sourceLen));
+ZEXTERN int ZEXPORT deflateCopy OF((z_streamp dest,
+			z_streamp source));
+
+
+ZEXTERN int ZEXPORT inflateInit_ OF((z_streamp strm,
+			const char *version, int stream_size));
+ZEXTERN int ZEXPORT inflate OF((z_streamp strm, int flush));
+/*
+    inflate decompresses as much data as possible, and stops when the input
+  buffer becomes empty or the output buffer becomes full. It may introduce
+  some output latency (reading input without producing any output) except when
+  forced to flush.
+
+  The detailed semantics are as follows. inflate performs one or both of the
+  following actions:
+
+  - Decompress more input starting at next_in and update next_in and avail_in
+    accordingly. If not all input can be processed (because there is not
+    enough room in the output buffer), next_in is updated and processing
+    will resume at this point for the next call of inflate().
+
+  - Provide more output starting at next_out and update next_out and avail_out
+    accordingly.  inflate() provides as much output as possible, until there
+    is no more input data or no more space in the output buffer (see below
+    about the flush parameter).
+
+  Before the call of inflate(), the application should ensure that at least
+  one of the actions is possible, by providing more input and/or consuming
+  more output, and updating the next_* and avail_* values accordingly.
+  The application can consume the uncompressed output when it wants, for
+  example when the output buffer is full (avail_out == 0), or after each
+  call of inflate(). If inflate returns Z_OK and with zero avail_out, it
+  must be called again after making room in the output buffer because there
+  might be more output pending.
+
+    The flush parameter of inflate() can be Z_NO_FLUSH, Z_SYNC_FLUSH,
+  Z_FINISH, or Z_BLOCK. Z_SYNC_FLUSH requests that inflate() flush as much
+  output as possible to the output buffer. Z_BLOCK requests that inflate() stop
+  if and when it gets to the next deflate block boundary. When decoding the
+  zlib or gzip format, this will cause inflate() to return immediately after
+  the header and before the first block. When doing a raw inflate, inflate()
+  will go ahead and process the first block, and will return when it gets to
+  the end of that block, or when it runs out of data.
+
+    The Z_BLOCK option assists in appending to or combining deflate streams.
+  Also to assist in this, on return inflate() will set strm->data_type to the
+  number of unused bits in the last byte taken from strm->next_in, plus 64
+  if inflate() is currently decoding the last block in the deflate stream,
+  plus 128 if inflate() returned immediately after decoding an end-of-block
+  code or decoding the complete header up to just before the first byte of the
+  deflate stream. The end-of-block will not be indicated until all of the
+  uncompressed data from that block has been written to strm->next_out.  The
+  number of unused bits may in general be greater than seven, except when
+  bit 7 of data_type is set, in which case the number of unused bits will be
+  less than eight.
+
+    inflate() should normally be called until it returns Z_STREAM_END or an
+  error. However if all decompression is to be performed in a single step
+  (a single call of inflate), the parameter flush should be set to
+  Z_FINISH. In this case all pending input is processed and all pending
+  output is flushed; avail_out must be large enough to hold all the
+  uncompressed data. (The size of the uncompressed data may have been saved
+  by the compressor for this purpose.) The next operation on this stream must
+  be inflateEnd to deallocate the decompression state. The use of Z_FINISH
+  is never required, but can be used to inform inflate that a faster approach
+  may be used for the single inflate() call.
+
+     In this implementation, inflate() always flushes as much output as
+  possible to the output buffer, and always uses the faster approach on the
+  first call. So the only effect of the flush parameter in this implementation
+  is on the return value of inflate(), as noted below, or when it returns early
+  because Z_BLOCK is used.
+
+     If a preset dictionary is needed after this call (see inflateSetDictionary
+  below), inflate sets strm->adler to the adler32 checksum of the dictionary
+  chosen by the compressor and returns Z_NEED_DICT; otherwise it sets
+  strm->adler to the adler32 checksum of all output produced so far (that is,
+  total_out bytes) and returns Z_OK, Z_STREAM_END or an error code as described
+  below. At the end of the stream, inflate() checks that its computed adler32
+  checksum is equal to that saved by the compressor and returns Z_STREAM_END
+  only if the checksum is correct.
+
+    inflate() will decompress and check either zlib-wrapped or gzip-wrapped
+  deflate data.  The header type is detected automatically.  Any information
+  contained in the gzip header is not retained, so applications that need that
+  information should instead use raw inflate, see inflateInit2() below, or
+  inflateBack() and perform their own processing of the gzip header and
+  trailer.
+
+    inflate() returns Z_OK if some progress has been made (more input processed
+  or more output produced), Z_STREAM_END if the end of the compressed data has
+  been reached and all uncompressed output has been produced, Z_NEED_DICT if a
+  preset dictionary is needed at this point, Z_DATA_ERROR if the input data was
+  corrupted (input stream not conforming to the zlib format or incorrect check
+  value), Z_STREAM_ERROR if the stream structure was inconsistent (for example
+  if next_in or next_out was NULL), Z_MEM_ERROR if there was not enough memory,
+  Z_BUF_ERROR if no progress is possible or if there was not enough room in the
+  output buffer when Z_FINISH is used. Note that Z_BUF_ERROR is not fatal, and
+  inflate() can be called again with more input and more output space to
+  continue decompressing. If Z_DATA_ERROR is returned, the application may then
+  call inflateSync() to look for a good compression block if a partial recovery
+  of the data is desired.
+*/
+
+ZEXTERN int ZEXPORT inflateEnd OF((z_streamp strm));
+/*
+     All dynamically allocated data structures for this stream are freed.
+   This function discards any unprocessed input and does not flush any
+   pending output.
+
+     inflateEnd returns Z_OK if success, Z_STREAM_ERROR if the stream state
+   was inconsistent. In the error case, msg may be set but then points to a
+   static string (which must not be deallocated).
+*/
+
+                        /* Advanced functions */
+
+ZEXTERN int ZEXPORT inflateReset OF((z_streamp strm));
+
+                        /* utility functions */
+
+/*
+     The following utility functions are implemented on top of the
+   basic stream-oriented functions. To simplify the interface, some
+   default options are assumed (compression level and memory usage,
+   standard memory allocation functions). The source code of these
+   utility functions can easily be modified if you need special options.
+*/
+
+ZEXTERN uLong ZEXPORT adler32 OF((uLong adler, const Bytef *buf, uInt len));
+/*
+     Update a running Adler-32 checksum with the bytes buf[0..len-1] and
+   return the updated checksum. If buf is NULL, this function returns
+   the required initial value for the checksum.
+   An Adler-32 checksum is almost as reliable as a CRC32 but can be computed
+   much faster. Usage example:
+
+     uLong adler = adler32(0L, Z_NULL, 0);
+
+     while (read_buffer(buffer, length) != EOF) {
+       adler = adler32(adler, buffer, length);
+     }
+     if (adler != original_adler) error();
+*/
+
+/*
+     Combine two Adler-32 checksums into one.  For two sequences of bytes, seq1
+   and seq2 with lengths len1 and len2, Adler-32 checksums were calculated for
+   each, adler1 and adler2.  adler32_combine() returns the Adler-32 checksum of
+   seq1 and seq2 concatenated, requiring only adler1, adler2, and len2.
+*/
+
+ZEXTERN  uInt ZEXPORT crc32  OF((uInt crc, const Bytef *buf, uInt len));
+/*
+     Update a running CRC-32 with the bytes buf[0..len-1] and return the
+   updated CRC-32. If buf is NULL, this function returns the required initial
+   value for the for the crc. Pre- and post-conditioning (one's complement) is
+   performed within this function so it shouldn't be done by the application.
+   Usage example:
+
+     uLong crc = crc32(0L, Z_NULL, 0);
+
+     while (read_buffer(buffer, length) != EOF) {
+       crc = crc32(crc, buffer, length);
+     }
+     if (crc != original_crc) error();
+*/
+
+ZEXTERN int ZEXPORT inflateInit2_ OF((z_streamp strm, int  windowBits,
+                                      const char *version, int stream_size));
+#define inflateInit(strm) \
+	inflateInit_((strm), ZLIB_VERSION, sizeof(z_stream))
+#define inflateInit2(strm, windowBits) \
+	inflateInit2_((strm), (windowBits), ZLIB_VERSION, sizeof(z_stream))
+
+#if !defined(ZUTIL_H) && !defined(NO_DUMMY_DECL)
+	struct internal_state {int dummy;}; /* hack for buggy compilers */
+#endif
+
+extern void *gzalloc(void *, unsigned, unsigned);
+extern void gzfree(void *, void *, unsigned);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ZLIB_H */
diff --git a/qemu/roms/u-boot/include/ubi_uboot.h b/qemu/roms/u-boot/include/ubi_uboot.h
new file mode 100644
index 000000000..7f720229a
--- /dev/null
+++ b/qemu/roms/u-boot/include/ubi_uboot.h
@@ -0,0 +1,223 @@
+/*
+ * Header file for UBI support for U-Boot
+ *
+ * Adaptation from kernel to U-Boot
+ *
+ *  Copyright (C) 2005-2007 Samsung Electronics
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __UBOOT_UBI_H
+#define __UBOOT_UBI_H
+
+#include <common.h>
+#include <compiler.h>
+#include <malloc.h>
+#include <div64.h>
+#include <linux/crc32.h>
+#include <linux/types.h>
+#include <linux/list.h>
+#include <linux/rbtree.h>
+#include <linux/string.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/ubi.h>
+
+#ifdef CONFIG_CMD_ONENAND
+#include <onenand_uboot.h>
+#endif
+
+#include <asm/errno.h>
+
+#define DPRINTK(format, args...)					\
+do {									\
+	printf("%s[%d]: " format "\n", __func__, __LINE__, ##args);	\
+} while (0)
+
+/* configurable */
+#define CONFIG_MTD_UBI_WL_THRESHOLD	4096
+#define CONFIG_MTD_UBI_BEB_RESERVE	1
+#define UBI_IO_DEBUG			0
+
+/* debug options (Linux: drivers/mtd/ubi/Kconfig.debug) */
+#undef CONFIG_MTD_UBI_DEBUG
+#undef CONFIG_MTD_UBI_DEBUG_PARANOID
+#undef CONFIG_MTD_UBI_DEBUG_MSG
+#undef CONFIG_MTD_UBI_DEBUG_MSG_EBA
+#undef CONFIG_MTD_UBI_DEBUG_MSG_WL
+#undef CONFIG_MTD_UBI_DEBUG_MSG_IO
+#undef CONFIG_MTD_UBI_DEBUG_MSG_BLD
+#define CONFIG_MTD_UBI_DEBUG_DISABLE_BGT
+
+/* build.c */
+#define get_device(...)
+#define put_device(...)
+#define ubi_sysfs_init(...)		0
+#define ubi_sysfs_close(...)		do { } while (0)
+static inline int is_power_of_2(unsigned long n)
+{
+	return (n != 0 && ((n & (n - 1)) == 0));
+}
+
+/* FIXME */
+#define MKDEV(...)			0
+#define MAJOR(dev)			0
+#define MINOR(dev)			0
+
+#define alloc_chrdev_region(...)	0
+#define unregister_chrdev_region(...)
+
+#define class_create(...)		__builtin_return_address(0)
+#define class_create_file(...)		0
+#define class_remove_file(...)
+#define class_destroy(...)
+#define misc_register(...)		0
+#define misc_deregister(...)
+
+/* vmt.c */
+#define device_register(...)		0
+#define volume_sysfs_init(...)		0
+#define volume_sysfs_close(...)		do { } while (0)
+
+/* kapi.c */
+
+/* eba.c */
+
+/* io.c */
+#define init_waitqueue_head(...)	do { } while (0)
+#define wait_event_interruptible(...)	0
+#define wake_up_interruptible(...)	do { } while (0)
+#define print_hex_dump(...)		do { } while (0)
+#define dump_stack(...)			do { } while (0)
+
+/* wl.c */
+#define task_pid_nr(x)			0
+#define set_freezable(...)		do { } while (0)
+#define try_to_freeze(...)		0
+#define set_current_state(...)		do { } while (0)
+#define kthread_should_stop(...)	0
+#define schedule()			do { } while (0)
+
+/* upd.c */
+static inline unsigned long copy_from_user(void *dest, const void *src,
+					   unsigned long count)
+{
+	memcpy((void *)dest, (void *)src, count);
+	return 0;
+}
+
+/* common */
+typedef int	spinlock_t;
+typedef int	wait_queue_head_t;
+#define spin_lock_init(...)
+#define spin_lock(...)
+#define spin_unlock(...)
+
+#define mutex_init(...)
+#define mutex_lock(...)
+#define mutex_unlock(...)
+
+#define init_rwsem(...)			do { } while (0)
+#define down_read(...)			do { } while (0)
+#define down_write(...)			do { } while (0)
+#define down_write_trylock(...)		1
+#define up_read(...)			do { } while (0)
+#define up_write(...)			do { } while (0)
+
+struct kmem_cache { int i; };
+#define kmem_cache_create(...)		1
+#define kmem_cache_alloc(obj, gfp)	malloc(sizeof(struct ubi_wl_entry))
+#define kmem_cache_free(obj, size)	free(size)
+#define kmem_cache_destroy(...)
+
+#define cond_resched()			do { } while (0)
+#define yield()				do { } while (0)
+
+#define KERN_WARNING
+#define KERN_ERR
+#define KERN_NOTICE
+#define KERN_DEBUG
+
+#define GFP_KERNEL			0
+#define GFP_NOFS			1
+
+#define __user
+#define __init
+#define __exit
+
+#define kthread_create(...)	__builtin_return_address(0)
+#define kthread_stop(...)	do { } while (0)
+#define wake_up_process(...)	do { } while (0)
+
+#define BUS_ID_SIZE		20
+
+struct rw_semaphore { int i; };
+struct device {
+	struct device		*parent;
+	struct class		*class;
+	char	bus_id[BUS_ID_SIZE];	/* position on parent bus */
+	dev_t			devt;	/* dev_t, creates the sysfs "dev" */
+	void	(*release)(struct device *dev);
+};
+struct mutex { int i; };
+struct kernel_param { int i; };
+
+struct cdev {
+	int owner;
+	dev_t dev;
+};
+#define cdev_init(...)		do { } while (0)
+#define cdev_add(...)		0
+#define cdev_del(...)		do { } while (0)
+
+#define MAX_ERRNO		4095
+#define IS_ERR_VALUE(x)		((x) >= (unsigned long)-MAX_ERRNO)
+
+static inline void *ERR_PTR(long error)
+{
+	return (void *) error;
+}
+
+static inline long PTR_ERR(const void *ptr)
+{
+	return (long) ptr;
+}
+
+static inline long IS_ERR(const void *ptr)
+{
+	return IS_ERR_VALUE((unsigned long)ptr);
+}
+
+/* module */
+#define THIS_MODULE		0
+#define try_module_get(...)	1
+#define module_put(...)		do { } while (0)
+#define module_init(...)
+#define module_exit(...)
+#define EXPORT_SYMBOL(...)
+#define EXPORT_SYMBOL_GPL(...)
+#define module_param_call(...)
+#define MODULE_PARM_DESC(...)
+#define MODULE_VERSION(...)
+#define MODULE_DESCRIPTION(...)
+#define MODULE_AUTHOR(...)
+#define MODULE_LICENSE(...)
+
+#ifndef __UBIFS_H__
+#include "../drivers/mtd/ubi/ubi.h"
+#endif
+
+/* functions */
+extern int ubi_mtd_param_parse(const char *val, struct kernel_param *kp);
+extern int ubi_init(void);
+extern void ubi_exit(void);
+extern int ubi_part(char *part_name, const char *vid_header_offset);
+extern int ubi_volume_write(char *volume, void *buf, size_t size);
+extern int ubi_volume_read(char *volume, char *buf, size_t size);
+
+extern struct ubi_device *ubi_devices[];
+
+#endif
diff --git a/qemu/roms/u-boot/include/universe.h b/qemu/roms/u-boot/include/universe.h
new file mode 100644
index 000000000..eb81e073d
--- /dev/null
+++ b/qemu/roms/u-boot/include/universe.h
@@ -0,0 +1,132 @@
+/*
+ * (C) Copyright 2003 Stefan Roese, stefan.roese@esd-electronics.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _universe_h
+#define _universe_h
+
+typedef struct _UNIVERSE UNIVERSE;
+typedef struct _SLAVE_IMAGE SLAVE_IMAGE;
+typedef struct _TDMA_CMD_PACKET TDMA_CMD_PACKET;
+
+struct _SLAVE_IMAGE {
+	unsigned int ctl;      /* Control     */
+	unsigned int bs;       /* Base        */
+	unsigned int bd;       /* Bound       */
+	unsigned int to;       /* Translation */
+	unsigned int reserved;
+};
+
+struct _UNIVERSE {
+	unsigned int pci_id;
+	unsigned int pci_csr;
+	unsigned int pci_class;
+	unsigned int pci_misc0;
+	unsigned int pci_bs;
+	unsigned int spare0[10];
+	unsigned int pci_misc1;
+	unsigned int spare1[48];
+	SLAVE_IMAGE  lsi[4];
+	unsigned int spare2[8];
+	unsigned int scyc_ctl;
+	unsigned int scyc_addr;
+	unsigned int scyc_en;
+	unsigned int scyc_cmp;
+	unsigned int scyc_swp;
+	unsigned int lmisc;
+	unsigned int slsi;
+	unsigned int l_cmderr;
+	unsigned int laerr;
+	unsigned int spare3[27];
+	unsigned int dctl;
+	unsigned int dtbc;
+	unsigned int dla;
+	unsigned int spare4[1];
+	unsigned int dva;
+	unsigned int spare5[1];
+	unsigned int dcpp;
+	unsigned int spare6[1];
+	unsigned int dgcs;
+	unsigned int d_llue;
+	unsigned int spare7[54];
+	unsigned int lint_en;
+	unsigned int lint_stat;
+	unsigned int lint_map0;
+	unsigned int lint_map1;
+	unsigned int vint_en;
+	unsigned int vint_stat;
+	unsigned int vint_map0;
+	unsigned int vint_map1;
+	unsigned int statid;
+	unsigned int vx_statid[7];
+	unsigned int spare8[48];
+	unsigned int mast_ctl;
+	unsigned int misc_ctl;
+	unsigned int misc_stat;
+	unsigned int user_am;
+	unsigned int spare9[700];
+	SLAVE_IMAGE  vsi[4];
+	unsigned int spare10[8];
+	unsigned int vrai_ctl;
+	unsigned int vrai_bs;
+	unsigned int spare11[2];
+	unsigned int vcsr_ctl;
+	unsigned int vcsr_to;
+	unsigned int v_amerr;
+	unsigned int vaerr;
+	unsigned int spare12[25];
+	unsigned int vcsr_clr;
+	unsigned int vcsr_set;
+	unsigned int vcsr_bs;
+};
+
+#define IRQ_VOWN    0x0001
+#define IRQ_VIRQ1   0x0002
+#define IRQ_VIRQ2   0x0004
+#define IRQ_VIRQ3   0x0008
+#define IRQ_VIRQ4   0x0010
+#define IRQ_VIRQ5   0x0020
+#define IRQ_VIRQ6   0x0040
+#define IRQ_VIRQ7   0x0080
+#define IRQ_DMA     0x0100
+#define IRQ_LERR    0x0200
+#define IRQ_VERR    0x0400
+#define IRQ_res     0x0800
+#define IRQ_IACK    0x1000
+#define IRQ_SWINT   0x2000
+#define IRQ_SYSFAIL 0x4000
+#define IRQ_ACFAIL  0x8000
+
+struct _TDMA_CMD_PACKET {
+	unsigned int dctl;   /* DMA Control         */
+	unsigned int dtbc;   /* Transfer Byte Count */
+	unsigned int dlv;    /* PCI Address         */
+	unsigned int res1;   /* Reserved            */
+	unsigned int dva;    /* Vme Address         */
+	unsigned int res2;   /* Reserved            */
+	unsigned int dcpp;   /* Pointer to Numed Cmd Packet with rPN */
+	unsigned int res3;   /* Reserved                             */
+};
+
+#define VME_AM_A16		0x01
+#define VME_AM_A24		0x02
+#define VME_AM_A32		0x03
+#define VME_AM_Axx		0x03
+#define VME_AM_SUP		0x04
+#define VME_AM_DATA		0x10
+#define VME_AM_PROG		0x20
+#define VME_AM_Mxx		0x30
+
+#define VME_FLAG_D8             0x01
+#define VME_FLAG_D16            0x02
+#define VME_FLAG_D32            0x03
+#define VME_FLAG_Dxx		0x03
+
+#define PCI_MS_MEM		0x01
+#define PCI_MS_IO		0x02
+#define PCI_MS_CONFIG		0x03
+#define PCI_MS_Mxx		0x03
+
+#endif
diff --git a/qemu/roms/u-boot/include/usb.h b/qemu/roms/u-boot/include/usb.h
new file mode 100644
index 000000000..d9fedeeff
--- /dev/null
+++ b/qemu/roms/u-boot/include/usb.h
@@ -0,0 +1,419 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ * Note: Part of this code has been derived from linux
+ *
+ */
+#ifndef _USB_H_
+#define _USB_H_
+
+#include <usb_defs.h>
+#include <linux/usb/ch9.h>
+
+/*
+ * The EHCI spec says that we must align to at least 32 bytes.  However,
+ * some platforms require larger alignment.
+ */
+#if ARCH_DMA_MINALIGN > 32
+#define USB_DMA_MINALIGN	ARCH_DMA_MINALIGN
+#else
+#define USB_DMA_MINALIGN	32
+#endif
+
+/* Everything is aribtrary */
+#define USB_ALTSETTINGALLOC		4
+#define USB_MAXALTSETTING		128	/* Hard limit */
+
+#define USB_MAX_DEVICE			32
+#define USB_MAXCONFIG			8
+#define USB_MAXINTERFACES		8
+#define USB_MAXENDPOINTS		16
+#define USB_MAXCHILDREN			8	/* This is arbitrary */
+#define USB_MAX_HUB			16
+
+#define USB_CNTL_TIMEOUT 100 /* 100ms timeout */
+
+/*
+ * This is the timeout to allow for submitting an urb in ms. We allow more
+ * time for a BULK device to react - some are slow.
+ */
+#define USB_TIMEOUT_MS(pipe) (usb_pipebulk(pipe) ? 5000 : 1000)
+
+/* device request (setup) */
+struct devrequest {
+	unsigned char	requesttype;
+	unsigned char	request;
+	unsigned short	value;
+	unsigned short	index;
+	unsigned short	length;
+} __attribute__ ((packed));
+
+/* Interface */
+struct usb_interface {
+	struct usb_interface_descriptor desc;
+
+	unsigned char	no_of_ep;
+	unsigned char	num_altsetting;
+	unsigned char	act_altsetting;
+
+	struct usb_endpoint_descriptor ep_desc[USB_MAXENDPOINTS];
+	/*
+	 * Super Speed Device will have Super Speed Endpoint
+	 * Companion Descriptor  (section 9.6.7 of usb 3.0 spec)
+	 * Revision 1.0 June 6th 2011
+	 */
+	struct usb_ss_ep_comp_descriptor ss_ep_comp_desc[USB_MAXENDPOINTS];
+} __attribute__ ((packed));
+
+/* Configuration information.. */
+struct usb_config {
+	struct usb_config_descriptor desc;
+
+	unsigned char	no_of_if;	/* number of interfaces */
+	struct usb_interface if_desc[USB_MAXINTERFACES];
+} __attribute__ ((packed));
+
+enum {
+	/* Maximum packet size; encoded as 0,1,2,3 = 8,16,32,64 */
+	PACKET_SIZE_8   = 0,
+	PACKET_SIZE_16  = 1,
+	PACKET_SIZE_32  = 2,
+	PACKET_SIZE_64  = 3,
+};
+
+struct usb_device {
+	int	devnum;			/* Device number on USB bus */
+	int	speed;			/* full/low/high */
+	char	mf[32];			/* manufacturer */
+	char	prod[32];		/* product */
+	char	serial[32];		/* serial number */
+
+	/* Maximum packet size; one of: PACKET_SIZE_* */
+	int maxpacketsize;
+	/* one bit for each endpoint ([0] = IN, [1] = OUT) */
+	unsigned int toggle[2];
+	/* endpoint halts; one bit per endpoint # & direction;
+	 * [0] = IN, [1] = OUT
+	 */
+	unsigned int halted[2];
+	int epmaxpacketin[16];		/* INput endpoint specific maximums */
+	int epmaxpacketout[16];		/* OUTput endpoint specific maximums */
+
+	int configno;			/* selected config number */
+	/* Device Descriptor */
+	struct usb_device_descriptor descriptor
+		__attribute__((aligned(ARCH_DMA_MINALIGN)));
+	struct usb_config config; /* config descriptor */
+
+	int have_langid;		/* whether string_langid is valid yet */
+	int string_langid;		/* language ID for strings */
+	int (*irq_handle)(struct usb_device *dev);
+	unsigned long irq_status;
+	int irq_act_len;		/* transfered bytes */
+	void *privptr;
+	/*
+	 * Child devices -  if this is a hub device
+	 * Each instance needs its own set of data structures.
+	 */
+	unsigned long status;
+	int act_len;			/* transfered bytes */
+	int maxchild;			/* Number of ports if hub */
+	int portnr;
+	struct usb_device *parent;
+	struct usb_device *children[USB_MAXCHILDREN];
+
+	void *controller;		/* hardware controller private data */
+	/* slot_id - for xHCI enabled devices */
+	unsigned int slot_id;
+};
+
+/*
+ * You can initialize platform's USB host or device
+ * ports by passing this enum as an argument to
+ * board_usb_init().
+ */
+enum usb_init_type {
+	USB_INIT_HOST,
+	USB_INIT_DEVICE
+};
+
+/**********************************************************************
+ * this is how the lowlevel part communicate with the outer world
+ */
+
+#if defined(CONFIG_USB_UHCI) || defined(CONFIG_USB_OHCI) || \
+	defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_OHCI_NEW) || \
+	defined(CONFIG_USB_SL811HS) || defined(CONFIG_USB_ISP116X_HCD) || \
+	defined(CONFIG_USB_R8A66597_HCD) || defined(CONFIG_USB_DAVINCI) || \
+	defined(CONFIG_USB_OMAP3) || defined(CONFIG_USB_DA8XX) || \
+	defined(CONFIG_USB_BLACKFIN) || defined(CONFIG_USB_AM35X) || \
+	defined(CONFIG_USB_MUSB_DSPS) || defined(CONFIG_USB_MUSB_AM35X) || \
+	defined(CONFIG_USB_MUSB_OMAP2PLUS) || defined(CONFIG_USB_XHCI)
+
+int usb_lowlevel_init(int index, enum usb_init_type init, void **controller);
+int usb_lowlevel_stop(int index);
+
+int submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
+			void *buffer, int transfer_len);
+int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+			int transfer_len, struct devrequest *setup);
+int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+			int transfer_len, int interval);
+
+/* Defines */
+#define USB_UHCI_VEND_ID	0x8086
+#define USB_UHCI_DEV_ID		0x7112
+
+/*
+ * PXA25x can only act as USB device. There are drivers
+ * which works with USB CDC gadgets implementations.
+ * Some of them have common routines which can be used
+ * in boards init functions e.g. udc_disconnect() used for
+ * forced device disconnection from host.
+ */
+#elif defined(CONFIG_USB_GADGET_PXA2XX)
+
+extern void udc_disconnect(void);
+
+#endif
+
+/*
+ * board-specific hardware initialization, called by
+ * usb drivers and u-boot commands
+ *
+ * @param index USB controller number
+ * @param init initializes controller as USB host or device
+ */
+int board_usb_init(int index, enum usb_init_type init);
+
+/*
+ * can be used to clean up after failed USB initialization attempt
+ * vide: board_usb_init()
+ *
+ * @param index USB controller number for selective cleanup
+ * @param init usb_init_type passed to board_usb_init()
+ */
+int board_usb_cleanup(int index, enum usb_init_type init);
+
+#ifdef CONFIG_USB_STORAGE
+
+#define USB_MAX_STOR_DEV 5
+block_dev_desc_t *usb_stor_get_dev(int index);
+int usb_stor_scan(int mode);
+int usb_stor_info(void);
+
+#endif
+
+#ifdef CONFIG_USB_HOST_ETHER
+
+#define USB_MAX_ETH_DEV 5
+int usb_host_eth_scan(int mode);
+
+#endif
+
+#ifdef CONFIG_USB_KEYBOARD
+
+int drv_usb_kbd_init(void);
+int usb_kbd_deregister(void);
+
+#endif
+/* routines */
+int usb_init(void); /* initialize the USB Controller */
+int usb_stop(void); /* stop the USB Controller */
+
+
+int usb_set_protocol(struct usb_device *dev, int ifnum, int protocol);
+int usb_set_idle(struct usb_device *dev, int ifnum, int duration,
+			int report_id);
+struct usb_device *usb_get_dev_index(int index);
+int usb_control_msg(struct usb_device *dev, unsigned int pipe,
+			unsigned char request, unsigned char requesttype,
+			unsigned short value, unsigned short index,
+			void *data, unsigned short size, int timeout);
+int usb_bulk_msg(struct usb_device *dev, unsigned int pipe,
+			void *data, int len, int *actual_length, int timeout);
+int usb_submit_int_msg(struct usb_device *dev, unsigned long pipe,
+			void *buffer, int transfer_len, int interval);
+int usb_disable_asynch(int disable);
+int usb_maxpacket(struct usb_device *dev, unsigned long pipe);
+int usb_get_configuration_no(struct usb_device *dev, unsigned char *buffer,
+				int cfgno);
+int usb_get_report(struct usb_device *dev, int ifnum, unsigned char type,
+			unsigned char id, void *buf, int size);
+int usb_get_class_descriptor(struct usb_device *dev, int ifnum,
+			unsigned char type, unsigned char id, void *buf,
+			int size);
+int usb_clear_halt(struct usb_device *dev, int pipe);
+int usb_string(struct usb_device *dev, int index, char *buf, size_t size);
+int usb_set_interface(struct usb_device *dev, int interface, int alternate);
+
+/* big endian -> little endian conversion */
+/* some CPUs are already little endian e.g. the ARM920T */
+#define __swap_16(x) \
+	({ unsigned short x_ = (unsigned short)x; \
+	 (unsigned short)( \
+		((x_ & 0x00FFU) << 8) | ((x_ & 0xFF00U) >> 8)); \
+	})
+#define __swap_32(x) \
+	({ unsigned long x_ = (unsigned long)x; \
+	 (unsigned long)( \
+		((x_ & 0x000000FFUL) << 24) | \
+		((x_ & 0x0000FF00UL) <<	 8) | \
+		((x_ & 0x00FF0000UL) >>	 8) | \
+		((x_ & 0xFF000000UL) >> 24)); \
+	})
+
+#ifdef __LITTLE_ENDIAN
+# define swap_16(x) (x)
+# define swap_32(x) (x)
+#else
+# define swap_16(x) __swap_16(x)
+# define swap_32(x) __swap_32(x)
+#endif
+
+/*
+ * Calling this entity a "pipe" is glorifying it. A USB pipe
+ * is something embarrassingly simple: it basically consists
+ * of the following information:
+ *  - device number (7 bits)
+ *  - endpoint number (4 bits)
+ *  - current Data0/1 state (1 bit)
+ *  - direction (1 bit)
+ *  - speed (2 bits)
+ *  - max packet size (2 bits: 8, 16, 32 or 64)
+ *  - pipe type (2 bits: control, interrupt, bulk, isochronous)
+ *
+ * That's 18 bits. Really. Nothing more. And the USB people have
+ * documented these eighteen bits as some kind of glorious
+ * virtual data structure.
+ *
+ * Let's not fall in that trap. We'll just encode it as a simple
+ * unsigned int. The encoding is:
+ *
+ *  - max size:		bits 0-1	(00 = 8, 01 = 16, 10 = 32, 11 = 64)
+ *  - direction:	bit 7		(0 = Host-to-Device [Out],
+ *					(1 = Device-to-Host [In])
+ *  - device:		bits 8-14
+ *  - endpoint:		bits 15-18
+ *  - Data0/1:		bit 19
+ *  - pipe type:	bits 30-31	(00 = isochronous, 01 = interrupt,
+ *					 10 = control, 11 = bulk)
+ *
+ * Why? Because it's arbitrary, and whatever encoding we select is really
+ * up to us. This one happens to share a lot of bit positions with the UHCI
+ * specification, so that much of the uhci driver can just mask the bits
+ * appropriately.
+ */
+/* Create various pipes... */
+#define create_pipe(dev,endpoint) \
+		(((dev)->devnum << 8) | ((endpoint) << 15) | \
+		(dev)->maxpacketsize)
+#define default_pipe(dev) ((dev)->speed << 26)
+
+#define usb_sndctrlpipe(dev, endpoint)	((PIPE_CONTROL << 30) | \
+					 create_pipe(dev, endpoint))
+#define usb_rcvctrlpipe(dev, endpoint)	((PIPE_CONTROL << 30) | \
+					 create_pipe(dev, endpoint) | \
+					 USB_DIR_IN)
+#define usb_sndisocpipe(dev, endpoint)	((PIPE_ISOCHRONOUS << 30) | \
+					 create_pipe(dev, endpoint))
+#define usb_rcvisocpipe(dev, endpoint)	((PIPE_ISOCHRONOUS << 30) | \
+					 create_pipe(dev, endpoint) | \
+					 USB_DIR_IN)
+#define usb_sndbulkpipe(dev, endpoint)	((PIPE_BULK << 30) | \
+					 create_pipe(dev, endpoint))
+#define usb_rcvbulkpipe(dev, endpoint)	((PIPE_BULK << 30) | \
+					 create_pipe(dev, endpoint) | \
+					 USB_DIR_IN)
+#define usb_sndintpipe(dev, endpoint)	((PIPE_INTERRUPT << 30) | \
+					 create_pipe(dev, endpoint))
+#define usb_rcvintpipe(dev, endpoint)	((PIPE_INTERRUPT << 30) | \
+					 create_pipe(dev, endpoint) | \
+					 USB_DIR_IN)
+#define usb_snddefctrl(dev)		((PIPE_CONTROL << 30) | \
+					 default_pipe(dev))
+#define usb_rcvdefctrl(dev)		((PIPE_CONTROL << 30) | \
+					 default_pipe(dev) | \
+					 USB_DIR_IN)
+
+/* The D0/D1 toggle bits */
+#define usb_gettoggle(dev, ep, out) (((dev)->toggle[out] >> ep) & 1)
+#define usb_dotoggle(dev, ep, out)  ((dev)->toggle[out] ^= (1 << ep))
+#define usb_settoggle(dev, ep, out, bit) ((dev)->toggle[out] = \
+						((dev)->toggle[out] & \
+						 ~(1 << ep)) | ((bit) << ep))
+
+/* Endpoint halt control/status */
+#define usb_endpoint_out(ep_dir)	(((ep_dir >> 7) & 1) ^ 1)
+#define usb_endpoint_halt(dev, ep, out) ((dev)->halted[out] |= (1 << (ep)))
+#define usb_endpoint_running(dev, ep, out) ((dev)->halted[out] &= ~(1 << (ep)))
+#define usb_endpoint_halted(dev, ep, out) ((dev)->halted[out] & (1 << (ep)))
+
+#define usb_packetid(pipe)	(((pipe) & USB_DIR_IN) ? USB_PID_IN : \
+				 USB_PID_OUT)
+
+#define usb_pipeout(pipe)	((((pipe) >> 7) & 1) ^ 1)
+#define usb_pipein(pipe)	(((pipe) >> 7) & 1)
+#define usb_pipedevice(pipe)	(((pipe) >> 8) & 0x7f)
+#define usb_pipe_endpdev(pipe)	(((pipe) >> 8) & 0x7ff)
+#define usb_pipeendpoint(pipe)	(((pipe) >> 15) & 0xf)
+#define usb_pipedata(pipe)	(((pipe) >> 19) & 1)
+#define usb_pipetype(pipe)	(((pipe) >> 30) & 3)
+#define usb_pipeisoc(pipe)	(usb_pipetype((pipe)) == PIPE_ISOCHRONOUS)
+#define usb_pipeint(pipe)	(usb_pipetype((pipe)) == PIPE_INTERRUPT)
+#define usb_pipecontrol(pipe)	(usb_pipetype((pipe)) == PIPE_CONTROL)
+#define usb_pipebulk(pipe)	(usb_pipetype((pipe)) == PIPE_BULK)
+
+#define usb_pipe_ep_index(pipe)	\
+		usb_pipecontrol(pipe) ? (usb_pipeendpoint(pipe) * 2) : \
+				((usb_pipeendpoint(pipe) * 2) - \
+				 (usb_pipein(pipe) ? 0 : 1))
+
+/*************************************************************************
+ * Hub Stuff
+ */
+struct usb_port_status {
+	unsigned short wPortStatus;
+	unsigned short wPortChange;
+} __attribute__ ((packed));
+
+struct usb_hub_status {
+	unsigned short wHubStatus;
+	unsigned short wHubChange;
+} __attribute__ ((packed));
+
+
+/* Hub descriptor */
+struct usb_hub_descriptor {
+	unsigned char  bLength;
+	unsigned char  bDescriptorType;
+	unsigned char  bNbrPorts;
+	unsigned short wHubCharacteristics;
+	unsigned char  bPwrOn2PwrGood;
+	unsigned char  bHubContrCurrent;
+	unsigned char  DeviceRemovable[(USB_MAXCHILDREN+1+7)/8];
+	unsigned char  PortPowerCtrlMask[(USB_MAXCHILDREN+1+7)/8];
+	/* DeviceRemovable and PortPwrCtrlMask want to be variable-length
+	   bitmaps that hold max 255 entries. (bit0 is ignored) */
+} __attribute__ ((packed));
+
+
+struct usb_hub_device {
+	struct usb_device *pusb_dev;
+	struct usb_hub_descriptor desc;
+};
+
+int usb_hub_probe(struct usb_device *dev, int ifnum);
+void usb_hub_reset(void);
+int hub_port_reset(struct usb_device *dev, int port,
+			  unsigned short *portstat);
+
+struct usb_device *usb_alloc_new_device(void *controller);
+
+int usb_new_device(struct usb_device *dev);
+void usb_free_device(void);
+int usb_alloc_device(struct usb_device *dev);
+
+#endif /*_USB_H_ */
diff --git a/qemu/roms/u-boot/include/usb/ci_udc.h b/qemu/roms/u-boot/include/usb/ci_udc.h
new file mode 100644
index 000000000..0dee50461
--- /dev/null
+++ b/qemu/roms/u-boot/include/usb/ci_udc.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright 2011, Marvell Semiconductor Inc.
+ * Lei Wen <leiwen@marvell.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+
+#ifndef __CI_UDC_H__
+#define __CI_UDC_H__
+
+#define EP_MAX_PACKET_SIZE	0x200
+#define EP0_MAX_PACKET_SIZE	64
+#endif /* __CI_UDC_H__ */
diff --git a/qemu/roms/u-boot/include/usb/designware_udc.h b/qemu/roms/u-boot/include/usb/designware_udc.h
new file mode 100644
index 000000000..2e1cdf138
--- /dev/null
+++ b/qemu/roms/u-boot/include/usb/designware_udc.h
@@ -0,0 +1,184 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DW_UDC_H
+#define __DW_UDC_H
+
+/*
+ * Defines for  USBD
+ *
+ * The udc_ahb controller has three AHB slaves:
+ *
+ * 1.  THe UDC registers
+ * 2.  The plug detect
+ * 3.  The RX/TX FIFO
+ */
+
+#define MAX_ENDPOINTS		16
+
+struct udc_endp_regs {
+	u32 endp_cntl;
+	u32 endp_status;
+	u32 endp_bsorfn;
+	u32 endp_maxpacksize;
+	u32 reserved_1;
+	u32 endp_desc_point;
+	u32 reserved_2;
+	u32 write_done;
+};
+
+/* Endpoint Control Register definitions */
+
+#define  ENDP_CNTL_STALL		0x00000001
+#define  ENDP_CNTL_FLUSH		0x00000002
+#define  ENDP_CNTL_SNOOP		0x00000004
+#define  ENDP_CNTL_POLL			0x00000008
+#define  ENDP_CNTL_CONTROL		0x00000000
+#define  ENDP_CNTL_ISO			0x00000010
+#define  ENDP_CNTL_BULK			0x00000020
+#define  ENDP_CNTL_INT			0x00000030
+#define  ENDP_CNTL_NAK			0x00000040
+#define  ENDP_CNTL_SNAK			0x00000080
+#define  ENDP_CNTL_CNAK			0x00000100
+#define  ENDP_CNTL_RRDY			0x00000200
+
+/* Endpoint Satus Register definitions */
+
+#define  ENDP_STATUS_PIDMSK		0x0000000f
+#define  ENDP_STATUS_OUTMSK		0x00000030
+#define  ENDP_STATUS_OUT_NONE		0x00000000
+#define  ENDP_STATUS_OUT_DATA		0x00000010
+#define  ENDP_STATUS_OUT_SETUP		0x00000020
+#define  ENDP_STATUS_IN			0x00000040
+#define  ENDP_STATUS_BUFFNAV		0x00000080
+#define  ENDP_STATUS_FATERR		0x00000100
+#define  ENDP_STATUS_HOSTBUSERR		0x00000200
+#define  ENDP_STATUS_TDC		0x00000400
+#define  ENDP_STATUS_RXPKTMSK		0x003ff800
+
+struct udc_regs {
+	struct udc_endp_regs in_regs[MAX_ENDPOINTS];
+	struct udc_endp_regs out_regs[MAX_ENDPOINTS];
+	u32 dev_conf;
+	u32 dev_cntl;
+	u32 dev_stat;
+	u32 dev_int;
+	u32 dev_int_mask;
+	u32 endp_int;
+	u32 endp_int_mask;
+	u32 reserved_3[0x39];
+	u32 reserved_4;		/* offset 0x500 */
+	u32 udc_endp_reg[MAX_ENDPOINTS];
+};
+
+/* Device Configuration Register definitions */
+
+#define  DEV_CONF_HS_SPEED		0x00000000
+#define  DEV_CONF_LS_SPEED		0x00000002
+#define  DEV_CONF_FS_SPEED		0x00000003
+#define  DEV_CONF_REMWAKEUP		0x00000004
+#define  DEV_CONF_SELFPOW		0x00000008
+#define  DEV_CONF_SYNCFRAME		0x00000010
+#define  DEV_CONF_PHYINT_8		0x00000020
+#define  DEV_CONF_PHYINT_16		0x00000000
+#define  DEV_CONF_UTMI_BIDIR		0x00000040
+#define  DEV_CONF_STATUS_STALL		0x00000080
+
+/* Device Control Register definitions */
+
+#define  DEV_CNTL_RESUME		0x00000001
+#define  DEV_CNTL_TFFLUSH		0x00000002
+#define  DEV_CNTL_RXDMAEN		0x00000004
+#define  DEV_CNTL_TXDMAEN		0x00000008
+#define  DEV_CNTL_DESCRUPD		0x00000010
+#define  DEV_CNTL_BIGEND		0x00000020
+#define  DEV_CNTL_BUFFILL		0x00000040
+#define  DEV_CNTL_TSHLDEN		0x00000080
+#define  DEV_CNTL_BURSTEN		0x00000100
+#define  DEV_CNTL_DMAMODE		0x00000200
+#define  DEV_CNTL_SOFTDISCONNECT	0x00000400
+#define  DEV_CNTL_SCALEDOWN		0x00000800
+#define  DEV_CNTL_BURSTLENU		0x00010000
+#define  DEV_CNTL_BURSTLENMSK		0x00ff0000
+#define  DEV_CNTL_TSHLDLENU		0x01000000
+#define  DEV_CNTL_TSHLDLENMSK		0xff000000
+
+/* Device Status Register definitions */
+
+#define  DEV_STAT_CFG			0x0000000f
+#define  DEV_STAT_INTF			0x000000f0
+#define  DEV_STAT_ALT			0x00000f00
+#define  DEV_STAT_SUSP			0x00001000
+#define  DEV_STAT_ENUM			0x00006000
+#define  DEV_STAT_ENUM_SPEED_HS		0x00000000
+#define  DEV_STAT_ENUM_SPEED_FS		0x00002000
+#define  DEV_STAT_ENUM_SPEED_LS		0x00004000
+#define  DEV_STAT_RXFIFO_EMPTY		0x00008000
+#define  DEV_STAT_PHY_ERR		0x00010000
+#define  DEV_STAT_TS			0xf0000000
+
+/* Device Interrupt Register definitions */
+
+#define  DEV_INT_MSK			0x0000007f
+#define  DEV_INT_SETCFG			0x00000001
+#define  DEV_INT_SETINTF		0x00000002
+#define  DEV_INT_INACTIVE		0x00000004
+#define  DEV_INT_USBRESET		0x00000008
+#define  DEV_INT_SUSPUSB		0x00000010
+#define  DEV_INT_SOF			0x00000020
+#define  DEV_INT_ENUM			0x00000040
+
+/* Endpoint Interrupt Register definitions */
+
+#define  ENDP0_INT_CTRLIN		0x00000001
+#define  ENDP1_INT_BULKIN		0x00000002
+#define  ENDP_INT_NONISOIN_MSK		0x0000AAAA
+#define  ENDP2_INT_BULKIN		0x00000004
+#define  ENDP0_INT_CTRLOUT		0x00010000
+#define  ENDP1_INT_BULKOUT		0x00020000
+#define  ENDP2_INT_BULKOUT		0x00040000
+#define  ENDP_INT_NONISOOUT_MSK		0x55540000
+
+/* Endpoint Register definitions */
+#define  ENDP_EPDIR_OUT			0x00000000
+#define  ENDP_EPDIR_IN			0x00000010
+#define  ENDP_EPTYPE_CNTL		0x0
+#define  ENDP_EPTYPE_ISO		0x1
+#define  ENDP_EPTYPE_BULK		0x2
+#define  ENDP_EPTYPE_INT		0x3
+
+/*
+ * Defines for Plug Detect
+ */
+
+struct plug_regs {
+	u32 plug_state;
+	u32 plug_pending;
+};
+
+/* Plug State Register definitions */
+#define  PLUG_STATUS_EN			0x1
+#define  PLUG_STATUS_ATTACHED		0x2
+#define  PLUG_STATUS_PHY_RESET		0x4
+#define  PLUG_STATUS_PHY_MODE		0x8
+
+/*
+ * Defines for UDC FIFO (Slave Mode)
+ */
+struct udcfifo_regs {
+	u32 *fifo_p;
+};
+
+/*
+ * UDC endpoint definitions
+ */
+#define  UDC_EP0			0
+#define  UDC_EP1			1
+#define  UDC_EP2			2
+#define  UDC_EP3			3
+
+#endif /* __DW_UDC_H */
diff --git a/qemu/roms/u-boot/include/usb/ehci-fsl.h b/qemu/roms/u-boot/include/usb/ehci-fsl.h
new file mode 100644
index 000000000..c9ee1d5bf
--- /dev/null
+++ b/qemu/roms/u-boot/include/usb/ehci-fsl.h
@@ -0,0 +1,281 @@
+/*
+ * Copyright (c) 2005, 2009 Freescale Semiconductor, Inc
+ * Copyright (c) 2005 MontaVista Software
+ * Copyright (c) 2008 Excito Elektronik i Sk=E5ne AB
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _EHCI_FSL_H
+#define _EHCI_FSL_H
+
+#include <asm/processor.h>
+
+/* Global offsets */
+#define FSL_SKIP_PCI		0x100
+
+/* offsets for the non-ehci registers in the FSL SOC USB controller */
+#define FSL_SOC_USB_ULPIVP	0x170
+#define FSL_SOC_USB_PORTSC1	0x184
+#define PORT_PTS_MSK		(3 << 30)
+#define PORT_PTS_UTMI		(0 << 30)
+#define PORT_PTS_ULPI		(2 << 30)
+#define PORT_PTS_SERIAL		(3 << 30)
+#define PORT_PTS_PTW		(1 << 28)
+#define PORT_PFSC		(1 << 24) /* Defined on Page 39-44 of the mpc5151 ERM */
+#define PORT_PTS_PHCD		(1 << 23)
+#define PORT_PP			(1 << 12)
+#define PORT_PR			(1 << 8)
+
+/* USBMODE Register bits */
+#define CM_IDLE			(0 << 0)
+#define CM_RESERVED		(1 << 0)
+#define CM_DEVICE		(2 << 0)
+#define CM_HOST			(3 << 0)
+#define ES_BE			(1 << 2)	/* Big Endian Select, default is LE */
+#define USBMODE_RESERVED_2	(0 << 2)
+#define SLOM			(1 << 3)
+#define SDIS			(1 << 4)
+
+/* CONTROL Register bits */
+#define ULPI_INT_EN		(1 << 0)
+#define WU_INT_EN		(1 << 1)
+#define USB_EN			(1 << 2)
+#define LSF_EN			(1 << 3)
+#define KEEP_OTG_ON		(1 << 4)
+#define OTG_PORT		(1 << 5)
+#define REFSEL_12MHZ		(0 << 6)
+#define REFSEL_16MHZ		(1 << 6)
+#define REFSEL_48MHZ		(2 << 6)
+#define PLL_RESET		(1 << 8)
+#define UTMI_PHY_EN		(1 << 9)
+#define PHY_CLK_SEL_UTMI	(0 << 10)
+#define PHY_CLK_SEL_ULPI	(1 << 10)
+#define CLKIN_SEL_USB_CLK	(0 << 11)
+#define CLKIN_SEL_USB_CLK2	(1 << 11)
+#define CLKIN_SEL_SYS_CLK	(2 << 11)
+#define CLKIN_SEL_SYS_CLK2	(3 << 11)
+#define RESERVED_18		(0 << 13)
+#define RESERVED_17		(0 << 14)
+#define RESERVED_16		(0 << 15)
+#define WU_INT			(1 << 16)
+#define PHY_CLK_VALID		(1 << 17)
+
+#define FSL_SOC_USB_PORTSC2	0x188
+
+/* OTG Status Control Register bits */
+#define FSL_SOC_USB_OTGSC	0x1a4
+#define CTRL_VBUS_DISCHARGE	(0x1<<0)
+#define CTRL_VBUS_CHARGE	(0x1<<1)
+#define CTRL_OTG_TERMINATION	(0x1<<3)
+#define CTRL_DATA_PULSING	(0x1<<4)
+#define CTRL_ID_PULL_EN		(0x1<<5)
+#define HA_DATA_PULSE		(0x1<<6)
+#define HA_BA			(0x1<<7)
+#define STS_USB_ID		(0x1<<8)
+#define STS_A_VBUS_VALID	(0x1<<9)
+#define STS_A_SESSION_VALID	(0x1<<10)
+#define STS_B_SESSION_VALID	(0x1<<11)
+#define STS_B_SESSION_END	(0x1<<12)
+#define STS_1MS_TOGGLE		(0x1<<13)
+#define STS_DATA_PULSING	(0x1<<14)
+#define INTSTS_USB_ID		(0x1<<16)
+#define INTSTS_A_VBUS_VALID	(0x1<<17)
+#define INTSTS_A_SESSION_VALID	(0x1<<18)
+#define INTSTS_B_SESSION_VALID	(0x1<<19)
+#define INTSTS_B_SESSION_END	(0x1<<20)
+#define INTSTS_1MS		(0x1<<21)
+#define INTSTS_DATA_PULSING	(0x1<<22)
+#define INTR_USB_ID_EN		(0x1<<24)
+#define INTR_A_VBUS_VALID_EN	(0x1<<25)
+#define INTR_A_SESSION_VALID_EN (0x1<<26)
+#define INTR_B_SESSION_VALID_EN (0x1<<27)
+#define INTR_B_SESSION_END_EN	(0x1<<28)
+#define INTR_1MS_TIMER_EN	(0x1<<29)
+#define INTR_DATA_PULSING_EN	(0x1<<30)
+#define INTSTS_MASK		(0x00ff0000)
+
+/* USBCMD Bits of interest */
+#define EHCI_FSL_USBCMD_RST	(1 <<  1)
+#define EHCI_FSL_USBCMD_RS	(1 <<  0)
+
+#define  INTERRUPT_ENABLE_BITS_MASK  \
+		(INTR_USB_ID_EN		| \
+		INTR_1MS_TIMER_EN	| \
+		INTR_A_VBUS_VALID_EN	| \
+		INTR_A_SESSION_VALID_EN | \
+		INTR_B_SESSION_VALID_EN | \
+		INTR_B_SESSION_END_EN	| \
+		INTR_DATA_PULSING_EN)
+
+#define  INTERRUPT_STATUS_BITS_MASK  \
+		(INTSTS_USB_ID		| \
+		INTR_1MS_TIMER_EN	| \
+		INTSTS_A_VBUS_VALID	| \
+		INTSTS_A_SESSION_VALID  | \
+		INTSTS_B_SESSION_VALID  | \
+		INTSTS_B_SESSION_END	| \
+		INTSTS_DATA_PULSING)
+
+#define FSL_SOC_USB_USBMODE	0x1a8
+
+#define USBGENCTRL		0x200		/* NOTE: big endian */
+#define GC_WU_INT_CLR		(1 << 5)	/* Wakeup int clear */
+#define GC_ULPI_SEL		(1 << 4)	/* ULPI i/f select (usb0 only)*/
+#define GC_PPP			(1 << 3)	/* Port Power Polarity */
+#define GC_PFP			(1 << 2)	/* Power Fault Polarity */
+#define GC_WU_ULPI_EN		(1 << 1)	/* Wakeup on ULPI event */
+#define GC_WU_IE		(1 << 1)	/* Wakeup interrupt enable */
+
+#define ISIPHYCTRL		0x204		/* NOTE: big endian */
+#define PHYCTRL_PHYE		(1 << 4)	/* On-chip UTMI PHY enable */
+#define PHYCTRL_BSENH		(1 << 3)	/* Bit Stuff Enable High */
+#define PHYCTRL_BSEN		(1 << 2)	/* Bit Stuff Enable */
+#define PHYCTRL_LSFE		(1 << 1)	/* Line State Filter Enable */
+#define PHYCTRL_PXE		(1 << 0)	/* PHY oscillator enable */
+
+#define FSL_SOC_USB_SNOOP1	0x400	/* NOTE: big-endian */
+#define FSL_SOC_USB_SNOOP2	0x404	/* NOTE: big-endian */
+#define FSL_SOC_USB_AGECNTTHRSH	0x408	/* NOTE: big-endian */
+#define FSL_SOC_USB_PRICTRL	0x40c	/* NOTE: big-endian */
+#define FSL_SOC_USB_SICTRL	0x410	/* NOTE: big-endian */
+#define FSL_SOC_USB_CTRL	0x500	/* NOTE: big-endian */
+#define SNOOP_SIZE_2GB		0x1e
+
+/* System Clock Control Register */
+#define MPC83XX_SCCR_USB_MASK		0x00f00000
+#define MPC83XX_SCCR_USB_DRCM_11	0x00300000
+#define MPC83XX_SCCR_USB_DRCM_01	0x00100000
+#define MPC83XX_SCCR_USB_DRCM_10	0x00200000
+
+#if defined(CONFIG_MPC83xx)
+#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC83xx_USB1_ADDR
+#if defined(CONFIG_MPC834x)
+#define CONFIG_SYS_FSL_USB2_ADDR CONFIG_SYS_MPC83xx_USB2_ADDR
+#else
+#define CONFIG_SYS_FSL_USB2_ADDR	0
+#endif
+#elif defined(CONFIG_MPC85xx)
+#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC85xx_USB1_ADDR
+#define CONFIG_SYS_FSL_USB2_ADDR CONFIG_SYS_MPC85xx_USB2_ADDR
+#elif defined(CONFIG_MPC512X)
+#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC512x_USB1_ADDR
+#define CONFIG_SYS_FSL_USB2_ADDR	0
+#endif
+
+/*
+ * Increasing TX FIFO threshold value from 2 to 4 decreases
+ * data burst rate with which data packets are posted from the TX
+ * latency FIFO to compensate for latencies in DDR pipeline during DMA
+ */
+#define TXFIFOTHRESH		4
+
+/*
+ * USB Registers
+ */
+struct usb_ehci {
+	u32	id;		/* 0x000 - Identification register */
+	u32	hwgeneral;	/* 0x004 - General hardware parameters */
+	u32	hwhost;		/* 0x008 - Host hardware parameters */
+	u32	hwdevice;	/* 0x00C - Device hardware parameters  */
+	u32	hwtxbuf;	/* 0x010 - TX buffer hardware parameters */
+	u32	hwrxbuf;	/* 0x014 - RX buffer hardware parameters */
+	u8	res1[0x68];
+	u32	gptimer0_ld;	/* 0x080 - General Purpose Timer 0 load value */
+	u32	gptimer0_ctrl;	/* 0x084 - General Purpose Timer 0 control */
+	u32     gptimer1_ld;	/* 0x088 - General Purpose Timer 1 load value */
+	u32     gptimer1_ctrl;	/* 0x08C - General Purpose Timer 1 control */
+	u32	sbuscfg;	/* 0x090 - System Bus Interface Control */
+	u8	res2[0x6C];
+	u8	caplength;	/* 0x100 - Capability Register Length */
+	u8	res3[0x1];
+	u16	hciversion;	/* 0x102 - Host Interface Version */
+	u32	hcsparams;	/* 0x104 - Host Structural Parameters */
+	u32	hccparams;	/* 0x108 - Host Capability Parameters */
+	u8	res4[0x14];
+	u32	dciversion;	/* 0x120 - Device Interface Version */
+	u32	dciparams;	/* 0x124 - Device Controller Params */
+	u8	res5[0x18];
+	u32	usbcmd;		/* 0x140 - USB Command */
+	u32	usbsts;		/* 0x144 - USB Status */
+	u32	usbintr;	/* 0x148 - USB Interrupt Enable */
+	u32	frindex;	/* 0x14C - USB Frame Index */
+	u8	res6[0x4];
+	u32	perlistbase;	/* 0x154 - Periodic List Base
+					 - USB Device Address */
+	u32	ep_list_addr;	/* 0x158 - Next Asynchronous List
+					 - End Point Address */
+	u8	res7[0x4];
+	u32	burstsize;	/* 0x160 - Programmable Burst Size */
+#define FSL_EHCI_TXPBURST(X)	((X) << 8)
+#define FSL_EHCI_RXPBURST(X)	(X)
+	u32	txfilltuning;	/* 0x164 - Host TT Transmit
+					   pre-buffer packet tuning */
+	u8	res8[0x8];
+	u32	ulpi_viewpoint;	/* 0x170 - ULPI Reister Access */
+	u8	res9[0xc];
+	u32	config_flag;	/* 0x180 - Configured Flag Register */
+	u32	portsc;		/* 0x184 - Port status/control */
+	u8	res10[0x1C];
+	u32	otgsc;		/* 0x1a4 - Oo-The-Go status and control */
+	u32	usbmode;	/* 0x1a8 - USB Device Mode */
+	u32	epsetupstat;	/* 0x1ac - End Point Setup Status */
+	u32	epprime;	/* 0x1b0 - End Point Init Status */
+	u32	epflush;	/* 0x1b4 - End Point De-initlialize */
+	u32	epstatus;	/* 0x1b8 - End Point Status */
+	u32	epcomplete;	/* 0x1bc - End Point Complete */
+	u32	epctrl0;	/* 0x1c0 - End Point Control 0 */
+	u32	epctrl1;	/* 0x1c4 - End Point Control 1 */
+	u32	epctrl2;	/* 0x1c8 - End Point Control 2 */
+	u32	epctrl3;	/* 0x1cc - End Point Control 3 */
+	u32	epctrl4;	/* 0x1d0 - End Point Control 4 */
+	u32	epctrl5;	/* 0x1d4 - End Point Control 5 */
+	u8	res11[0x28];
+	u32	usbgenctrl;	/* 0x200 - USB General Control */
+	u32	isiphyctrl;	/* 0x204 - On-Chip PHY Control */
+	u8	res12[0x1F8];
+	u32	snoop1;		/* 0x400 - Snoop 1 */
+	u32	snoop2;		/* 0x404 - Snoop 2 */
+	u32	age_cnt_limit;	/* 0x408 - Age Count Threshold */
+	u32	prictrl;	/* 0x40c - Priority Control */
+	u32	sictrl;		/* 0x410 - System Interface Control */
+	u8	res13[0xEC];
+	u32	control;	/* 0x500 - Control */
+	u8	res14[0xafc];
+};
+
+/*
+ * For MXC SOCs
+ */
+
+/* values for portsc field */
+#define MXC_EHCI_PHY_LOW_POWER_SUSPEND	(1 << 23)
+#define MXC_EHCI_FORCE_FS		(1 << 24)
+#define MXC_EHCI_UTMI_8BIT		(0 << 28)
+#define MXC_EHCI_UTMI_16BIT		(1 << 28)
+#define MXC_EHCI_SERIAL			(1 << 29)
+#define MXC_EHCI_MODE_UTMI		(0 << 30)
+#define MXC_EHCI_MODE_PHILIPS		(1 << 30)
+#define MXC_EHCI_MODE_ULPI		(2 << 30)
+#define MXC_EHCI_MODE_SERIAL		(3 << 30)
+
+/* values for flags field */
+#define MXC_EHCI_INTERFACE_DIFF_UNI	(0 << 0)
+#define MXC_EHCI_INTERFACE_DIFF_BI	(1 << 0)
+#define MXC_EHCI_INTERFACE_SINGLE_UNI	(2 << 0)
+#define MXC_EHCI_INTERFACE_SINGLE_BI	(3 << 0)
+#define MXC_EHCI_INTERFACE_MASK		(0xf)
+
+#define MXC_EHCI_POWER_PINS_ENABLED	(1 << 5)
+#define MXC_EHCI_PWR_PIN_ACTIVE_HIGH	(1 << 6)
+#define MXC_EHCI_OC_PIN_ACTIVE_LOW	(1 << 7)
+#define MXC_EHCI_TTL_ENABLED		(1 << 8)
+
+#define MXC_EHCI_INTERNAL_PHY		(1 << 9)
+#define MXC_EHCI_IPPUE_DOWN		(1 << 10)
+#define MXC_EHCI_IPPUE_UP		(1 << 11)
+
+/* Board-specific initialization */
+int board_ehci_hcd_init(int port);
+
+#endif /* _EHCI_FSL_H */
diff --git a/qemu/roms/u-boot/include/usb/fotg210.h b/qemu/roms/u-boot/include/usb/fotg210.h
new file mode 100644
index 000000000..b83e8f593
--- /dev/null
+++ b/qemu/roms/u-boot/include/usb/fotg210.h
@@ -0,0 +1,363 @@
+/*
+ * Faraday USB 2.0 OTG Controller
+ *
+ * (C) Copyright 2010 Faraday Technology
+ * Dante Su <dantesu@faraday-tech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _FOTG210_H
+#define _FOTG210_H
+
+struct fotg210_regs {
+	/* USB Host Controller */
+	struct {
+		uint32_t data[4];
+	} hccr;			/* 0x00 - 0x0f: hccr */
+	struct {
+		uint32_t data[9];
+	} hcor;			/* 0x10 - 0x33: hcor */
+	uint32_t rsvd1[3];
+	uint32_t miscr;	/* 0x40: Miscellaneous Register */
+	uint32_t rsvd2[15];
+	/* USB OTG Controller */
+	uint32_t otgcsr;/* 0x80: OTG Control Status Register */
+	uint32_t otgisr;/* 0x84: OTG Interrupt Status Register */
+	uint32_t otgier;/* 0x88: OTG Interrupt Enable Register */
+	uint32_t rsvd3[13];
+	uint32_t isr;	/* 0xC0: Global Interrupt Status Register */
+	uint32_t imr;	/* 0xC4: Global Interrupt Mask Register */
+	uint32_t rsvd4[14];
+	/* USB Device Controller */
+	uint32_t dev_ctrl;/* 0x100: Device Control Register */
+	uint32_t dev_addr;/* 0x104: Device Address Register */
+	uint32_t dev_test;/* 0x108: Device Test Register */
+	uint32_t sof_fnr; /* 0x10c: SOF Frame Number Register */
+	uint32_t sof_mtr; /* 0x110: SOF Mask Timer Register */
+	uint32_t phy_tmsr;/* 0x114: PHY Test Mode Selector Register */
+	uint32_t rsvd5[2];
+	uint32_t cxfifo;/* 0x120: CX FIFO Register */
+	uint32_t idle;	/* 0x124: IDLE Counter Register */
+	uint32_t rsvd6[2];
+	uint32_t gimr;	/* 0x130: Group Interrupt Mask Register */
+	uint32_t gimr0; /* 0x134: Group Interrupt Mask Register 0 */
+	uint32_t gimr1; /* 0x138: Group Interrupt Mask Register 1 */
+	uint32_t gimr2; /* 0x13c: Group Interrupt Mask Register 2 */
+	uint32_t gisr;	/* 0x140: Group Interrupt Status Register */
+	uint32_t gisr0; /* 0x144: Group Interrupt Status Register 0 */
+	uint32_t gisr1; /* 0x148: Group Interrupt Status Register 1 */
+	uint32_t gisr2; /* 0x14c: Group Interrupt Status Register 2 */
+	uint32_t rxzlp; /* 0x150: Receive Zero-Length-Packet Register */
+	uint32_t txzlp; /* 0x154: Transfer Zero-Length-Packet Register */
+	uint32_t isoeasr;/* 0x158: ISOC Error/Abort Status Register */
+	uint32_t rsvd7[1];
+	uint32_t iep[8]; /* 0x160 - 0x17f: IN Endpoint Register */
+	uint32_t oep[8]; /* 0x180 - 0x19f: OUT Endpoint Register */
+	uint32_t epmap14;/* 0x1a0: Endpoint Map Register (EP1 ~ 4) */
+	uint32_t epmap58;/* 0x1a4: Endpoint Map Register (EP5 ~ 8) */
+	uint32_t fifomap;/* 0x1a8: FIFO Map Register */
+	uint32_t fifocfg; /* 0x1ac: FIFO Configuration Register */
+	uint32_t fifocsr[4];/* 0x1b0 - 0x1bf: FIFO Control Status Register */
+	uint32_t dma_fifo; /* 0x1c0: DMA Target FIFO Register */
+	uint32_t rsvd8[1];
+	uint32_t dma_ctrl; /* 0x1c8: DMA Control Register */
+	uint32_t dma_addr; /* 0x1cc: DMA Address Register */
+	uint32_t ep0_data; /* 0x1d0: EP0 Setup Packet PIO Register */
+};
+
+/* Miscellaneous Register */
+#define MISCR_SUSPEND  (1 << 6) /* Put transceiver in suspend mode */
+#define MISCR_EOF2(x)  (((x) & 0x3) << 4) /* EOF 2 Timing */
+#define MISCR_EOF1(x)  (((x) & 0x3) << 2) /* EOF 1 Timing */
+#define MISCR_ASST(x)  (((x) & 0x3) << 0) /* Async. Sched. Sleep Timer */
+
+/* OTG Control Status Register */
+#define OTGCSR_SPD_HIGH     (2 << 22) /* Speed of the attached device (host) */
+#define OTGCSR_SPD_LOW      (1 << 22)
+#define OTGCSR_SPD_FULL     (0 << 22)
+#define OTGCSR_SPD_MASK     (3 << 22)
+#define OTGCSR_SPD_SHIFT    22
+#define OTGCSR_SPD(x)       (((x) >> 22) & 0x03)
+#define OTGCSR_DEV_A        (0 << 21) /* Acts as A-device */
+#define OTGCSR_DEV_B        (1 << 21) /* Acts as B-device */
+#define OTGCSR_ROLE_H       (0 << 20) /* Acts as Host */
+#define OTGCSR_ROLE_D       (1 << 20) /* Acts as Device */
+#define OTGCSR_A_VBUS_VLD   (1 << 19) /* A-device VBUS Valid */
+#define OTGCSR_A_SESS_VLD   (1 << 18) /* A-device Session Valid */
+#define OTGCSR_B_SESS_VLD   (1 << 17) /* B-device Session Valid */
+#define OTGCSR_B_SESS_END   (1 << 16) /* B-device Session End */
+#define OTGCSR_HFT_LONG     (1 << 11) /* HDISCON noise filter = 270 us*/
+#define OTGCSR_HFT          (0 << 11) /* HDISCON noise filter = 135 us*/
+#define OTGCSR_VFT_LONG     (1 << 10) /* VBUS noise filter = 472 us*/
+#define OTGCSR_VFT          (0 << 10) /* VBUS noise filter = 135 us*/
+#define OTGCSR_IDFT_LONG    (1 << 9)  /* ID noise filter = 4 ms*/
+#define OTGCSR_IDFT         (0 << 9)  /* ID noise filter = 3 ms*/
+#define OTGCSR_A_SRPR_VBUS  (0 << 8)  /* A-device: SRP responds to VBUS */
+#define OTGCSR_A_SRPR_DATA  (1 << 8)  /* A-device: SRP responds to DATA-LINE */
+#define OTGCSR_A_SRP_EN     (1 << 7)  /* A-device SRP detection enabled */
+#define OTGCSR_A_HNP        (1 << 6)  /* Set role=A-device with HNP enabled */
+#define OTGCSR_A_BUSDROP    (1 << 5)  /* A-device drop bus (power-down) */
+#define OTGCSR_A_BUSREQ     (1 << 4)  /* A-device request bus */
+#define OTGCSR_B_VBUS_DISC  (1 << 2)  /* B-device discharges VBUS */
+#define OTGCSR_B_HNP        (1 << 1)  /* B-device enable HNP */
+#define OTGCSR_B_BUSREQ     (1 << 0)  /* B-device request bus */
+
+/* OTG Interrupt Status Register */
+#define OTGISR_APRM         (1 << 12) /* Mini-A plug removed */
+#define OTGISR_BPRM         (1 << 11) /* Mini-B plug removed */
+#define OTGISR_OVD          (1 << 10) /* over-current detected */
+#define OTGISR_IDCHG        (1 << 9)  /* ID(A/B) changed */
+#define OTGISR_RLCHG        (1 << 8)  /* Role(Host/Device) changed */
+#define OTGISR_BSESSEND     (1 << 6)  /* B-device Session End */
+#define OTGISR_AVBUSERR     (1 << 5)  /* A-device VBUS Error */
+#define OTGISR_ASRP         (1 << 4)  /* A-device SRP detected */
+#define OTGISR_BSRP         (1 << 0)  /* B-device SRP complete */
+
+/* OTG Interrupt Enable Register */
+#define OTGIER_APRM         (1 << 12) /* Mini-A plug removed */
+#define OTGIER_BPRM         (1 << 11) /* Mini-B plug removed */
+#define OTGIER_OVD          (1 << 10) /* over-current detected */
+#define OTGIER_IDCHG        (1 << 9)  /* ID(A/B) changed */
+#define OTGIER_RLCHG        (1 << 8)  /* Role(Host/Device) changed */
+#define OTGIER_BSESSEND     (1 << 6)  /* B-device Session End */
+#define OTGIER_AVBUSERR     (1 << 5)  /* A-device VBUS Error */
+#define OTGIER_ASRP         (1 << 4)  /* A-device SRP detected */
+#define OTGIER_BSRP         (1 << 0)  /* B-device SRP complete */
+
+/* Global Interrupt Status Register (W1C) */
+#define ISR_HOST            (1 << 2)  /* USB Host interrupt */
+#define ISR_OTG             (1 << 1)  /* USB OTG interrupt */
+#define ISR_DEV             (1 << 0)  /* USB Device interrupt */
+#define ISR_MASK            0x07
+
+/* Global Interrupt Mask Register */
+#define IMR_IRQLH           (1 << 3)  /* Interrupt triggered at level-high */
+#define IMR_IRQLL           (0 << 3)  /* Interrupt triggered at level-low */
+#define IMR_HOST            (1 << 2)  /* USB Host interrupt */
+#define IMR_OTG             (1 << 1)  /* USB OTG interrupt */
+#define IMR_DEV             (1 << 0)  /* USB Device interrupt */
+#define IMR_MASK            0x0f
+
+/* Device Control Register */
+#define DEVCTRL_FS_FORCED   (1 << 9)  /* Forced to be Full-Speed Mode */
+#define DEVCTRL_HS          (1 << 6)  /* High Speed Mode */
+#define DEVCTRL_FS          (0 << 6)  /* Full Speed Mode */
+#define DEVCTRL_EN          (1 << 5)  /* Chip Enable */
+#define DEVCTRL_RESET       (1 << 4)  /* Chip Software Reset */
+#define DEVCTRL_SUSPEND     (1 << 3)  /* Enter Suspend Mode */
+#define DEVCTRL_GIRQ_EN     (1 << 2)  /* Global Interrupt Enabled */
+#define DEVCTRL_HALFSPD     (1 << 1)  /* Half speed mode for FPGA test */
+#define DEVCTRL_RWAKEUP     (1 << 0)  /* Enable remote wake-up */
+
+/* Device Address Register */
+#define DEVADDR_CONF        (1 << 7)  /* SET_CONFIGURATION has been executed */
+#define DEVADDR_ADDR(x)     ((x) & 0x7f)
+#define DEVADDR_ADDR_MASK   0x7f
+
+/* Device Test Register */
+#define DEVTEST_NOSOF       (1 << 6)  /* Do not generate SOF */
+#define DEVTEST_TST_MODE    (1 << 5)  /* Enter Test Mode */
+#define DEVTEST_TST_NOTS    (1 << 4)  /* Do not toggle sequence */
+#define DEVTEST_TST_NOCRC   (1 << 3)  /* Do not append CRC */
+#define DEVTEST_TST_CLREA   (1 << 2)  /* Clear External Side Address */
+#define DEVTEST_TST_CXLP    (1 << 1)  /* EP0 loopback test */
+#define DEVTEST_TST_CLRFF   (1 << 0)  /* Clear FIFO */
+
+/* SOF Frame Number Register */
+#define SOFFNR_UFN(x)       (((x) >> 11) & 0x7) /* SOF Micro-Frame Number */
+#define SOFFNR_FNR(x)       ((x) & 0x7ff) /* SOF Frame Number */
+
+/* SOF Mask Timer Register */
+#define SOFMTR_TMR(x)       ((x) & 0xffff)
+
+/* PHY Test Mode Selector Register */
+#define PHYTMSR_TST_PKT     (1 << 4) /* Packet send test */
+#define PHYTMSR_TST_SE0NAK  (1 << 3) /* High-Speed quiescent state */
+#define PHYTMSR_TST_KSTA    (1 << 2) /* High-Speed K state */
+#define PHYTMSR_TST_JSTA    (1 << 1) /* High-Speed J state */
+#define PHYTMSR_UNPLUG      (1 << 0) /* Enable soft-detachment */
+
+/* CX FIFO Register */
+#define CXFIFO_BYTES(x)     (((x) >> 24) & 0x7f) /* CX/EP0 FIFO byte count */
+#define CXFIFO_FIFOE(x)     (1 << (((x) & 0x03) + 8)) /* EPx FIFO empty */
+#define CXFIFO_FIFOE_FIFO0  (1 << 8)
+#define CXFIFO_FIFOE_FIFO1  (1 << 9)
+#define CXFIFO_FIFOE_FIFO2  (1 << 10)
+#define CXFIFO_FIFOE_FIFO3  (1 << 11)
+#define CXFIFO_FIFOE_MASK   (0x0f << 8)
+#define CXFIFO_CXFIFOE      (1 << 5) /* CX FIFO empty */
+#define CXFIFO_CXFIFOF      (1 << 4) /* CX FIFO full */
+#define CXFIFO_CXFIFOCLR    (1 << 3) /* CX FIFO clear */
+#define CXFIFO_CXSTALL      (1 << 2) /* CX Stall */
+#define CXFIFO_TSTPKTFIN    (1 << 1) /* Test packet data transfer finished */
+#define CXFIFO_CXFIN        (1 << 0) /* CX data transfer finished */
+
+/* IDLE Counter Register */
+#define IDLE_MS(x)          ((x) & 0x07) /* PHY suspend delay = x ms */
+
+/* Group Interrupt Mask(Disable) Register */
+#define GIMR_GRP2           (1 << 2) /* Disable interrupt group 2 */
+#define GIMR_GRP1           (1 << 1) /* Disable interrupt group 1 */
+#define GIMR_GRP0           (1 << 0) /* Disable interrupt group 0 */
+#define GIMR_MASK           0x07
+
+/* Group Interrupt Mask(Disable) Register 0 (CX) */
+#define GIMR0_CXABORT       (1 << 5) /* CX command abort interrupt */
+#define GIMR0_CXERR         (1 << 4) /* CX command error interrupt */
+#define GIMR0_CXEND         (1 << 3) /* CX command end interrupt */
+#define GIMR0_CXOUT         (1 << 2) /* EP0-OUT packet interrupt */
+#define GIMR0_CXIN          (1 << 1) /* EP0-IN packet interrupt */
+#define GIMR0_CXSETUP       (1 << 0) /* EP0-SETUP packet interrupt */
+#define GIMR0_MASK          0x3f
+
+/* Group Interrupt Mask(Disable) Register 1 (FIFO) */
+#define GIMR1_FIFO_IN(x)    (1 << (((x) & 3) + 16))    /* FIFOx IN */
+#define GIMR1_FIFO_TX(x)    GIMR1_FIFO_IN(x)
+#define GIMR1_FIFO_OUT(x)   (1 << (((x) & 3) * 2))     /* FIFOx OUT */
+#define GIMR1_FIFO_SPK(x)   (1 << (((x) & 3) * 2 + 1)) /* FIFOx SHORT PACKET */
+#define GIMR1_FIFO_RX(x)    (GIMR1_FIFO_OUT(x) | GIMR1_FIFO_SPK(x))
+#define GIMR1_MASK          0xf00ff
+
+/* Group Interrupt Mask(Disable) Register 2 (Device) */
+#define GIMR2_WAKEUP        (1 << 10) /* Device waked up */
+#define GIMR2_IDLE          (1 << 9)  /* Device idle */
+#define GIMR2_DMAERR        (1 << 8)  /* DMA error */
+#define GIMR2_DMAFIN        (1 << 7)  /* DMA finished */
+#define GIMR2_ZLPRX         (1 << 6)  /* Zero-Length-Packet Rx Interrupt */
+#define GIMR2_ZLPTX         (1 << 5)  /* Zero-Length-Packet Tx Interrupt */
+#define GIMR2_ISOCABT       (1 << 4)  /* ISOC Abort Interrupt */
+#define GIMR2_ISOCERR       (1 << 3)  /* ISOC Error Interrupt */
+#define GIMR2_RESUME        (1 << 2)  /* Resume state change Interrupt */
+#define GIMR2_SUSPEND       (1 << 1)  /* Suspend state change Interrupt */
+#define GIMR2_RESET         (1 << 0)  /* Reset Interrupt */
+#define GIMR2_MASK          0x7ff
+
+/* Group Interrupt Status Register */
+#define GISR_GRP2           (1 << 2) /* Interrupt group 2 */
+#define GISR_GRP1           (1 << 1) /* Interrupt group 1 */
+#define GISR_GRP0           (1 << 0) /* Interrupt group 0 */
+
+/* Group Interrupt Status Register 0 (CX) */
+#define GISR0_CXABORT       (1 << 5) /* CX command abort interrupt */
+#define GISR0_CXERR         (1 << 4) /* CX command error interrupt */
+#define GISR0_CXEND         (1 << 3) /* CX command end interrupt */
+#define GISR0_CXOUT         (1 << 2) /* EP0-OUT packet interrupt */
+#define GISR0_CXIN          (1 << 1) /* EP0-IN packet interrupt */
+#define GISR0_CXSETUP       (1 << 0) /* EP0-SETUP packet interrupt */
+
+/* Group Interrupt Status Register 1 (FIFO) */
+#define GISR1_IN_FIFO(x)    (1 << (((x) & 0x03) + 16))    /* FIFOx IN */
+#define GISR1_OUT_FIFO(x)   (1 << (((x) & 0x03) * 2))     /* FIFOx OUT */
+#define GISR1_SPK_FIFO(x)   (1 << (((x) & 0x03) * 2 + 1)) /* FIFOx SPK */
+#define GISR1_RX_FIFO(x)    (3 << (((x) & 0x03) * 2))     /* FIFOx OUT/SPK */
+
+/* Group Interrupt Status Register 2 (Device) */
+#define GISR2_WAKEUP        (1 << 10) /* Device waked up */
+#define GISR2_IDLE          (1 << 9)  /* Device idle */
+#define GISR2_DMAERR        (1 << 8)  /* DMA error */
+#define GISR2_DMAFIN        (1 << 7)  /* DMA finished */
+#define GISR2_ZLPRX         (1 << 6)  /* Zero-Length-Packet Rx Interrupt */
+#define GISR2_ZLPTX         (1 << 5)  /* Zero-Length-Packet Tx Interrupt */
+#define GISR2_ISOCABT       (1 << 4)  /* ISOC Abort Interrupt */
+#define GISR2_ISOCERR       (1 << 3)  /* ISOC Error Interrupt */
+#define GISR2_RESUME        (1 << 2)  /* Resume state change Interrupt */
+#define GISR2_SUSPEND       (1 << 1)  /* Suspend state change Interrupt */
+#define GISR2_RESET         (1 << 0)  /* Reset Interrupt */
+
+/* Receive Zero-Length-Packet Register */
+#define RXZLP_EP(x)         (1 << ((x) - 1)) /* EPx ZLP rx interrupt */
+
+/* Transfer Zero-Length-Packet Register */
+#define TXZLP_EP(x)         (1 << ((x) - 1)) /* EPx ZLP tx interrupt */
+
+/* ISOC Error/Abort Status Register */
+#define ISOEASR_EP(x)       (0x10001 << ((x) - 1)) /* EPx ISOC Error/Abort */
+
+/* IN Endpoint Register */
+#define IEP_SENDZLP         (1 << 15)     /* Send Zero-Length-Packet */
+#define IEP_TNRHB(x)        (((x) & 0x03) << 13) \
+	/* Transaction Number for High-Bandwidth EP(ISOC) */
+#define IEP_RESET           (1 << 12)     /* Reset Toggle Sequence */
+#define IEP_STALL           (1 << 11)     /* Stall */
+#define IEP_MAXPS(x)        ((x) & 0x7ff) /* Max. packet size */
+
+/* OUT Endpoint Register */
+#define OEP_RESET           (1 << 12)     /* Reset Toggle Sequence */
+#define OEP_STALL           (1 << 11)     /* Stall */
+#define OEP_MAXPS(x)        ((x) & 0x7ff) /* Max. packet size */
+
+/* Endpoint Map Register (EP1 ~ EP4) */
+#define EPMAP14_SET_IN(ep, fifo) \
+	((fifo) & 3) << (((ep) - 1) << 3 + 0)
+#define EPMAP14_SET_OUT(ep, fifo) \
+	((fifo) & 3) << (((ep) - 1) << 3 + 4)
+#define EPMAP14_SET(ep, in, out) \
+	do { \
+		EPMAP14_SET_IN(ep, in); \
+		EPMAP14_SET_OUT(ep, out); \
+	} while (0)
+
+#define EPMAP14_DEFAULT     0x33221100 /* EP1->FIFO0, EP2->FIFO1... */
+
+/* Endpoint Map Register (EP5 ~ EP8) */
+#define EPMAP58_SET_IN(ep, fifo) \
+	((fifo) & 3) << (((ep) - 5) << 3 + 0)
+#define EPMAP58_SET_OUT(ep, fifo) \
+	((fifo) & 3) << (((ep) - 5) << 3 + 4)
+#define EPMAP58_SET(ep, in, out) \
+	do { \
+		EPMAP58_SET_IN(ep, in); \
+		EPMAP58_SET_OUT(ep, out); \
+	} while (0)
+
+#define EPMAP58_DEFAULT     0x00000000 /* All EPx->FIFO0 */
+
+/* FIFO Map Register */
+#define FIFOMAP_BIDIR       (2 << 4)
+#define FIFOMAP_IN          (1 << 4)
+#define FIFOMAP_OUT         (0 << 4)
+#define FIFOMAP_DIR_MASK    0x30
+#define FIFOMAP_EP(x)       ((x) & 0x0f)
+#define FIFOMAP_EP_MASK     0x0f
+#define FIFOMAP_CFG_MASK    0x3f
+#define FIFOMAP_DEFAULT     0x04030201 /* FIFO0->EP1, FIFO1->EP2... */
+#define FIFOMAP(fifo, cfg)  (((cfg) & 0x3f) << (((fifo) & 3) << 3))
+
+/* FIFO Configuration Register */
+#define FIFOCFG_EN          (1 << 5)
+#define FIFOCFG_BLKSZ_1024  (1 << 4)
+#define FIFOCFG_BLKSZ_512   (0 << 4)
+#define FIFOCFG_3BLK        (2 << 2)
+#define FIFOCFG_2BLK        (1 << 2)
+#define FIFOCFG_1BLK        (0 << 2)
+#define FIFOCFG_NBLK_MASK   3
+#define FIFOCFG_NBLK_SHIFT  2
+#define FIFOCFG_INTR        (3 << 0)
+#define FIFOCFG_BULK        (2 << 0)
+#define FIFOCFG_ISOC        (1 << 0)
+#define FIFOCFG_RSVD        (0 << 0)  /* Reserved */
+#define FIFOCFG_TYPE_MASK   3
+#define FIFOCFG_TYPE_SHIFT  0
+#define FIFOCFG_CFG_MASK    0x3f
+#define FIFOCFG(fifo, cfg)  (((cfg) & 0x3f) << (((fifo) & 3) << 3))
+
+/* FIFO Control Status Register */
+#define FIFOCSR_RESET       (1 << 12) /* FIFO Reset */
+#define FIFOCSR_BYTES(x)    ((x) & 0x7ff) /* Length(bytes) for OUT-EP/FIFO */
+
+/* DMA Target FIFO Register */
+#define DMAFIFO_CX          (1 << 4) /* DMA FIFO = CX FIFO */
+#define DMAFIFO_FIFO(x)     (1 << ((x) & 0x3)) /* DMA FIFO = FIFOx */
+
+/* DMA Control Register */
+#define DMACTRL_LEN(x)      (((x) & 0x1ffff) << 8) /* DMA length (Bytes) */
+#define DMACTRL_LEN_SHIFT   8
+#define DMACTRL_CLRFF       (1 << 4) /* Clear FIFO upon DMA abort */
+#define DMACTRL_ABORT       (1 << 3) /* DMA abort */
+#define DMACTRL_IO2IO       (1 << 2) /* IO to IO */
+#define DMACTRL_FIFO2MEM    (0 << 1) /* FIFO to Memory */
+#define DMACTRL_MEM2FIFO    (1 << 1) /* Memory to FIFO */
+#define DMACTRL_START       (1 << 0) /* DMA start */
+
+#endif
diff --git a/qemu/roms/u-boot/include/usb/fusbh200.h b/qemu/roms/u-boot/include/usb/fusbh200.h
new file mode 100644
index 000000000..e2d855365
--- /dev/null
+++ b/qemu/roms/u-boot/include/usb/fusbh200.h
@@ -0,0 +1,60 @@
+/*
+ * Faraday USB 2.0 EHCI Controller
+ *
+ * (C) Copyright 2010 Faraday Technology
+ * Dante Su <dantesu@faraday-tech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _FUSBH200_H
+#define _FUSBH200_H
+
+struct fusbh200_regs {
+	struct {
+		uint32_t data[4];
+	} hccr;			/* 0x00 - 0x0f: hccr */
+	struct {
+		uint32_t data[9];
+	} hcor;			/* 0x10 - 0x33: hcor */
+	uint32_t easstr;/* 0x34: EOF&Async. Sched. Sleep Timer Register */
+	uint32_t rsvd[2];
+	uint32_t bmcsr;	/* 0x40: Bus Monitor Control Status Register */
+	uint32_t bmisr;	/* 0x44: Bus Monitor Interrupt Status Register */
+	uint32_t bmier; /* 0x48: Bus Monitor Interrupt Enable Register */
+};
+
+/* EOF & Async. Schedule Sleep Timer Register */
+#define EASSTR_RUNNING  (1 << 6) /* Put transceiver in running/resume mode */
+#define EASSTR_SUSPEND  (0 << 6) /* Put transceiver in suspend mode */
+#define EASSTR_EOF2(x)  (((x) & 0x3) << 4) /* EOF 2 Timing */
+#define EASSTR_EOF1(x)  (((x) & 0x3) << 2) /* EOF 1 Timing */
+#define EASSTR_ASST(x)  (((x) & 0x3) << 0) /* Async. Sched. Sleep Timer */
+
+/* Bus Monitor Control Status Register */
+#define BMCSR_SPD_HIGH  (2 << 9) /* Speed of the attached device */
+#define BMCSR_SPD_LOW   (1 << 9)
+#define BMCSR_SPD_FULL  (0 << 9)
+#define BMCSR_SPD_MASK  (3 << 9)
+#define BMCSR_SPD_SHIFT 9
+#define BMCSR_SPD(x)    ((x >> 9) & 0x03)
+#define BMCSR_VBUS      (1 << 8) /* VBUS Valid */
+#define BMCSR_VBUS_OFF  (1 << 4) /* VBUS Off */
+#define BMCSR_VBUS_ON   (0 << 4) /* VBUS On */
+#define BMCSR_IRQLH     (1 << 3) /* IRQ triggered at level-high */
+#define BMCSR_IRQLL     (0 << 3) /* IRQ triggered at level-low */
+#define BMCSR_HALFSPD   (1 << 2) /* Half speed mode for FPGA test */
+#define BMCSR_HFT_LONG  (1 << 1) /* HDISCON noise filter = 270 us*/
+#define BMCSR_HFT       (0 << 1) /* HDISCON noise filter = 135 us*/
+#define BMCSR_VFT_LONG  (1 << 1) /* VBUS noise filter = 472 us*/
+#define BMCSR_VFT       (0 << 1) /* VBUS noise filter = 135 us*/
+
+/* Bus Monitor Interrupt Status Register */
+/* Bus Monitor Interrupt Enable Register */
+#define BMISR_DMAERR    (1 << 4) /* DMA error */
+#define BMISR_DMA       (1 << 3) /* DMA complete */
+#define BMISR_DEVRM     (1 << 2) /* device removed */
+#define BMISR_OVD       (1 << 1) /* over-current detected */
+#define BMISR_VBUSERR   (1 << 0) /* VBUS error */
+
+#endif
diff --git a/qemu/roms/u-boot/include/usb/lin_gadget_compat.h b/qemu/roms/u-boot/include/usb/lin_gadget_compat.h
new file mode 100644
index 000000000..a25e9d9ef
--- /dev/null
+++ b/qemu/roms/u-boot/include/usb/lin_gadget_compat.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2011 Samsung Electronics
+ * Lukasz Majewski <l.majewski@samsung.com>
+ *
+ * This is a Linux kernel compatibility layer for USB Gadget
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __LIN_COMPAT_H__
+#define __LIN_COMPAT_H__
+
+#include <linux/compat.h>
+
+/* common */
+#define spin_lock_init(...)
+#define spin_lock(...)
+#define spin_lock_irqsave(lock, flags) do { debug("%lu\n", flags); } while (0)
+#define spin_unlock(...)
+#define spin_unlock_irqrestore(lock, flags) do {flags = 0; } while (0)
+#define disable_irq(...)
+#define enable_irq(...)
+
+#define mutex_init(...)
+#define mutex_lock(...)
+#define mutex_unlock(...)
+
+#define GFP_KERNEL	0
+
+#define IRQ_HANDLED	1
+
+#define ENOTSUPP	524	/* Operation is not supported */
+
+#define BITS_PER_BYTE				8
+#define BITS_TO_LONGS(nr) \
+	DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long))
+#define DECLARE_BITMAP(name, bits) \
+	unsigned long name[BITS_TO_LONGS(bits)]
+
+#define small_const_nbits(nbits) \
+	(__builtin_constant_p(nbits) && (nbits) <= BITS_PER_LONG)
+
+static inline void bitmap_zero(unsigned long *dst, int nbits)
+{
+	if (small_const_nbits(nbits))
+		*dst = 0UL;
+	else {
+		int len = BITS_TO_LONGS(nbits) * sizeof(unsigned long);
+		memset(dst, 0, len);
+	}
+}
+
+#define dma_cache_maint(addr, size, mode) cache_flush()
+void cache_flush(void);
+
+#endif /* __LIN_COMPAT_H__ */
diff --git a/qemu/roms/u-boot/include/usb/mpc8xx_udc.h b/qemu/roms/u-boot/include/usb/mpc8xx_udc.h
new file mode 100644
index 000000000..9906c75f6
--- /dev/null
+++ b/qemu/roms/u-boot/include/usb/mpc8xx_udc.h
@@ -0,0 +1,178 @@
+/*
+ * Copyright (C) 2006 Bryan O'Donoghue, CodeHermit
+ * bodonoghue@codehermit.ie
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <commproc.h>
+
+/* Mode Register */
+#define USMOD_EN	0x01
+#define USMOD_HOST	0x02
+#define USMOD_TEST	0x04
+#define USMOD_SFTE	0x08
+#define USMOD_RESUME	0x40
+#define USMOD_LSS	0x80
+
+/* Endpoint Registers */
+#define USEP_RHS_NORM	0x00
+#define USEP_RHS_IGNORE	0x01
+#define USEP_RHS_NAK	0x02
+#define USEP_RHS_STALL	0x03
+
+#define USEP_THS_NORM	0x00
+#define USEP_THS_IGNORE	0x04
+#define USEP_THS_NAK	0x08
+#define USEP_THS_STALL	0x0C
+
+#define USEP_RTE	0x10
+#define USEP_MF		0x20
+
+#define USEP_TM_CONTROL	0x00
+#define USEP_TM_INT	0x100
+#define USEP_TM_BULK	0x200
+#define USEP_TM_ISO	0x300
+
+/* Command Register */
+#define USCOM_EP0	0x00
+#define USCOM_EP1	0x01
+#define USCOM_EP2	0x02
+#define USCOM_EP3	0x03
+
+#define USCOM_FLUSH	0x40
+#define USCOM_STR	0x80
+
+/* Event Register */
+#define USB_E_RXB	0x0001
+#define USB_E_TXB	0x0002
+#define USB_E_BSY	0x0004
+#define USB_E_SOF	0x0008
+#define USB_E_TXE1	0x0010
+#define USB_E_TXE2	0x0020
+#define USB_E_TXE3	0x0040
+#define USB_E_TXE4	0x0080
+#define USB_TX_ERRMASK (USB_E_TXE1|USB_E_TXE2|USB_E_TXE3|USB_E_TXE4)
+#define USB_E_IDLE	0x0100
+#define USB_E_RESET	0x0200
+
+/* Mask Register */
+#define USBS_IDLE	0x01
+
+/* RX Buffer Descriptor */
+#define RX_BD_OV	0x02
+#define RX_BD_CR	0x04
+#define RX_BD_AB	0x08
+#define RX_BD_NO	0x10
+#define RX_BD_PID_DATA0	0x00
+#define RX_BD_PID_DATA1	0x40
+#define RX_BD_PID_SETUP	0x80
+#define RX_BD_F		0x400
+#define RX_BD_L		0x800
+#define RX_BD_I		0x1000
+#define RX_BD_W		0x2000
+#define RX_BD_E		0x8000
+
+/* Useful masks */
+#define RX_BD_PID_BITMASK (RX_BD_PID_DATA1 | RX_BD_PID_SETUP)
+#define STALL_BITMASK (USEP_THS_STALL | USEP_RHS_STALL)
+#define NAK_BITMASK (USEP_THS_NAK | USEP_RHS_NAK)
+#define CBD_TX_BITMASK (TX_BD_R | TX_BD_L | TX_BD_TC | TX_BD_I | TX_BD_CNF)
+
+/* TX Buffer Descriptor */
+#define TX_BD_UN	0x02
+#define TX_BD_TO	0x04
+#define TX_BD_NO_PID	0x00
+#define TX_BD_PID_DATA0	0x80
+#define TX_BD_PID_DATA1	0xC0
+#define TX_BD_CNF	0x200
+#define TX_BD_TC	0x400
+#define TX_BD_L		0x800
+#define TX_BD_I		0x1000
+#define TX_BD_W		0x2000
+#define TX_BD_R		0x8000
+
+/* Implementation specific defines */
+
+#define EP_MIN_PACKET_SIZE 0x08
+#define MAX_ENDPOINTS	0x04
+#define FIFO_SIZE	0x10
+#define EP_MAX_PKT	FIFO_SIZE
+#define TX_RING_SIZE	0x04
+#define RX_RING_SIZE	0x06
+#define USB_MAX_PKT	0x40
+#define TOGGLE_TX_PID(x) x= ((~x)&0x40)|0x80
+#define TOGGLE_RX_PID(x) x^= 0x40
+#define EP_ATTACHED	0x01	/* Endpoint has a urb attached or not */
+#define EP_SEND_ZLP	0x02	/* Send ZLP y/n ? */
+
+#define PROFF_USB	0x00000000
+#define CPM_USB_BASE	0x00000A00
+
+/* UDC device defines */
+#define EP0_MAX_PACKET_SIZE	EP_MAX_PKT
+
+#define UDC_OUT_PACKET_SIZE	EP_MIN_PACKET_SIZE
+#define UDC_IN_PACKET_SIZE	EP_MIN_PACKET_SIZE
+#define UDC_INT_PACKET_SIZE	UDC_IN_PACKET_SIZE
+#define UDC_BULK_PACKET_SIZE	EP_MIN_PACKET_SIZE
+
+struct mpc8xx_ep {
+	struct urb * urb;
+	unsigned char pid;
+	unsigned char sc;
+	volatile cbd_t * prx;
+};
+
+typedef struct mpc8xx_usb{
+	char usmod;	/* Mode Register */
+	char usaddr;	/* Slave Address Register */
+	char uscom;	/* Command Register */
+	char res1;	/* Reserved */
+	ushort usep[4];
+	ulong res2;	/* Reserved */
+	ushort usber;	/* Event Register */
+	ushort res3;	/* Reserved */
+	ushort usbmr;	/* Mask Register */
+	char res4;	/* Reserved */
+	char usbs;	/* Status Register */
+	char res5[8];	/* Reserved */
+}usb_t;
+
+typedef struct mpc8xx_parameter_ram{
+	ushort ep0ptr;	/* Endpoint Pointer Register 0 */
+	ushort ep1ptr;	/* Endpoint Pointer Register 1 */
+	ushort ep2ptr;	/* Endpoint Pointer Register 2 */
+	ushort ep3ptr;	/* Endpoint Pointer Register 3 */
+	uint rstate;	/* Receive state */
+	uint rptr;	/* Receive internal data pointer */
+	ushort frame_n;	/* Frame number */
+	ushort rbcnt;	/* Receive byte count */
+	uint rtemp;	/* Receive temp cp use only */
+	uint rxusb;	/* Rx Data Temp */
+	ushort rxuptr;	/* Rx microcode return address temp */
+}usb_pram_t;
+
+typedef struct endpoint_parameter_block_pointer{
+	ushort rbase;	/* RxBD base address */
+	ushort tbase;	/* TxBD base address */
+	char rfcr;	/* Rx Function code */
+	char tfcr;	/* Tx Function code */
+	ushort mrblr;	/* Maximum Receive Buffer Length */
+	ushort rbptr;	/* RxBD pointer Next Buffer Descriptor */
+	ushort tbptr;	/* TxBD pointer Next Buffer Descriptor  */
+	ulong tstate;	/* Transmit internal state */
+	ulong tptr;	/* Transmit internal data pointer */
+	ushort tcrc;	/* Transmit temp CRC */
+	ushort tbcnt;	/* Transmit internal bye count */
+	ulong ttemp;	/* Tx temp */
+	ushort txuptr;	/* Tx microcode return address */
+	ushort res1;	/* Reserved */
+}usb_epb_t;
+
+typedef enum mpc8xx_udc_state{
+	STATE_NOT_READY,
+	STATE_ERROR,
+	STATE_READY,
+}mpc8xx_udc_state_t;
+
diff --git a/qemu/roms/u-boot/include/usb/omap1510_udc.h b/qemu/roms/u-boot/include/usb/omap1510_udc.h
new file mode 100644
index 000000000..adfbf5499
--- /dev/null
+++ b/qemu/roms/u-boot/include/usb/omap1510_udc.h
@@ -0,0 +1,174 @@
+/*
+ * (C) Copyright 2003
+ * Gerry Hamel, geh@ti.com, Texas Instruments
+ *
+ * Based on
+ * linux/drivers/usb/device/bi/omap.h
+ * Register definitions for TI OMAP1510 USB bus interface driver
+ *
+ * Author: MontaVista Software, Inc.
+ *	   source@mvista.com
+ *
+ * 2003 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#ifndef __USBDCORE_OMAP1510_H__
+#define __USBDCORE_OMAP1510_H__
+
+
+/*
+ * 13.2 MPU Register Map
+ */
+
+/* Table 13-1. USB Function Module Registers (endpoint) */
+#define UDC_BASE		     0xFFFB4000
+#define UDC_OFFSET(offset)	     (UDC_BASE + (offset))
+#define UDC_REV			     UDC_OFFSET(0x0)	/* Revision */
+#define UDC_EP_NUM		     UDC_OFFSET(0x4)	/* Endpoint selection */
+#define UDC_DATA		     UDC_OFFSET(0x08)	/* Data */
+#define UDC_CTRL		     UDC_OFFSET(0x0C)	/* Control */
+#define UDC_STAT_FLG		     UDC_OFFSET(0x10)	/* Status flag */
+#define UDC_RXFSTAT		     UDC_OFFSET(0x14)	/* Receive FIFO status */
+#define UDC_SYSCON1		     UDC_OFFSET(0x18)	/* System configuration 1 */
+#define UDC_SYSCON2		     UDC_OFFSET(0x1C)	/* System configuration 2 */
+#define UDC_DEVSTAT		     UDC_OFFSET(0x20)	/* Device status */
+#define UDC_SOF			     UDC_OFFSET(0x24)	/* Start of frame */
+#define UDC_IRQ_EN		     UDC_OFFSET(0x28)	/* Interrupt enable */
+#define UDC_DMA_IRQ_EN		     UDC_OFFSET(0x2C)	/* DMA interrupt enable */
+#define UDC_IRQ_SRC		     UDC_OFFSET(0x30)	/* Interrupt source */
+#define UDC_EPN_STAT		     UDC_OFFSET(0x34)	/* Endpoint interrupt status */
+#define UDC_DMAN_STAT		     UDC_OFFSET(0x3C)	/* DMA endpoint interrupt status */
+
+/* IRQ_EN register fields */
+#define UDC_Sof_IE		     (1 << 7)	/* Start-of-frame interrupt enabled */
+#define UDC_EPn_RX_IE		     (1 << 5)	/* Receive endpoint interrupt enabled */
+#define UDC_EPn_TX_IE		     (1 << 4)	/* Transmit endpoint interrupt enabled */
+#define UDC_DS_Chg_IE		     (1 << 3)	/* Device state changed interrupt enabled */
+#define UDC_EP0_IE		     (1 << 0)	/* EP0 transaction interrupt enabled */
+
+/* IRQ_SRC register fields */
+#define UDC_TXn_Done		     (1 << 10)	/* Transmit DMA channel n done */
+#define UDC_RXn_Cnt		     (1 << 9)	/* Receive DMA channel n transactions count */
+#define UDC_RXn_EOT		     (1 << 8)	/* Receive DMA channel n end of transfer */
+#define UDC_SOF_Flg		     (1 << 7)	/* Start-of-frame interrupt flag */
+#define UDC_EPn_RX		     (1 << 5)	/* Endpoint n OUT transaction */
+#define UDC_EPn_TX		     (1 << 4)	/* Endpoint n IN transaction */
+#define UDC_DS_Chg		     (1 << 3)	/* Device state changed */
+#define UDC_Setup		     (1 << 2)	/* Setup transaction */
+#define UDC_EP0_RX		     (1 << 1)	/* EP0 OUT transaction */
+#define UDC_EP0_TX		     (1 << 0)	/* EP0 IN transaction */
+
+/* DEVSTAT register fields, 14.2.9 */
+#define UDC_R_WK_OK		     (1 << 6)	/* Remote wakeup granted */
+#define UDC_USB_Reset		     (1 << 5)	/* USB reset signalling is active */
+#define UDC_SUS			     (1 << 4)	/* Suspended state */
+#define UDC_CFG			     (1 << 3)	/* Configured state */
+#define UDC_ADD			     (1 << 2)	/* Addressed state */
+#define UDC_DEF			     (1 << 1)	/* Default state */
+#define UDC_ATT			     (1 << 0)	/* Attached state */
+
+/* SYSCON1 register fields */
+#define UDC_Cfg_Lock		     (1 << 8)	/* Device configuration locked */
+#define UDC_Nak_En		     (1 << 4)	/* NAK enable */
+#define UDC_Self_Pwr		     (1 << 2)	/* Device is self-powered */
+#define UDC_Soff_Dis		     (1 << 1)	/* Shutoff disabled */
+#define UDC_Pullup_En		     (1 << 0)	/* External pullup enabled */
+
+/* SYSCON2 register fields */
+#define UDC_Rmt_Wkp		     (1 << 6)	/* Remote wakeup */
+#define UDC_Stall_Cmd		     (1 << 5)	/* Stall endpoint */
+#define UDC_Dev_Cfg		     (1 << 3)	/* Device configured */
+#define UDC_Clr_Cfg		     (1 << 2)	/* Clear configured */
+
+/*
+ * Select and enable endpoints
+ */
+
+/* Table 13-1. USB Function Module Registers (endpoint configuration) */
+#define UDC_EPBASE		     UDC_OFFSET(0x80)	/* Endpoints base address */
+#define UDC_EP0			     UDC_EPBASE /* Control endpoint configuration */
+#define UDC_EP_RX_BASE		     UDC_OFFSET(0x84)	/* Receive endpoints base address */
+#define UDC_EP_RX(endpoint)	     (UDC_EP_RX_BASE + ((endpoint) - 1) * 4)
+#define UDC_EP_TX_BASE		     UDC_OFFSET(0xC4)	/* Transmit endpoints base address */
+#define UDC_EP_TX(endpoint)	     (UDC_EP_TX_BASE + ((endpoint) - 1) * 4)
+
+/* EP_NUM register fields */
+#define UDC_Setup_Sel		     (1 << 6)	/* Setup FIFO select */
+#define UDC_EP_Sel		     (1 << 5)	/* TX/RX FIFO select */
+#define UDC_EP_Dir		     (1 << 4)	/* Endpoint direction */
+
+/* CTRL register fields */
+#define UDC_Clr_Halt		     (1 << 7)	/* Clear halt endpoint */
+#define UDC_Set_Halt		     (1 << 6)	/* Set halt endpoint */
+#define UDC_Set_FIFO_En		     (1 << 2)	/* Set FIFO enable */
+#define UDC_Clr_EP		     (1 << 1)	/* Clear endpoint */
+#define UDC_Reset_EP		     (1 << 0)	/* Reset endpoint */
+
+/* STAT_FLG register fields */
+#define UDC_Miss_In		     (1 << 14)
+#define UDC_Data_Flush		     (1 << 13)
+#define UDC_ISO_Err		     (1 << 12)
+#define UDC_ISO_FIFO_Empty	     (1 << 9)
+#define UDC_ISO_FIFO_Full	     (1 << 8)
+#define UDC_EP_Halted		     (1 << 6)
+#define UDC_STALL		     (1 << 5)
+#define UDC_NAK			     (1 << 4)
+#define UDC_ACK			     (1 << 3)
+#define UDC_FIFO_En		     (1 << 2)
+#define UDC_Non_ISO_FIFO_Empty	     (1 << 1)
+#define UDC_Non_ISO_FIFO_Full	     (1 << 0)
+
+/* EPn_RX register fields */
+#define UDC_EPn_RX_Valid	     (1 << 15)	/* valid */
+#define UDC_EPn_RX_Db		     (1 << 14)	/* double-buffer */
+#define UDC_EPn_RX_Iso		     (1 << 11)	/* isochronous */
+
+/* EPn_TX register fields */
+#define UDC_EPn_TX_Valid	     (1 << 15)	/* valid */
+#define UDC_EPn_TX_Db		     (1 << 14)	/* double-buffer */
+#define UDC_EPn_TX_Iso		     (1 << 11)	/* isochronous */
+
+#define EP0_PACKETSIZE		     0x40
+
+/* physical to logical endpoint mapping
+ * Physical endpoints are an index into device->bus->endpoint_array.
+ * Logical endpoints are endpoints 0 to 15 IN and OUT as defined in
+ * the USB specification.
+ *
+ *	physical ep	logical ep	direction	endpoint_address
+ *	0		0		IN and OUT	0x00
+ *	1 to 15		1 to 15		OUT		0x01 to 0x0f
+ *	16 to 30	1 to 15		IN		0x81 to 0x8f
+ */
+#define PHYS_EP_TO_EP_ADDR(ep) (((ep) < 16) ? (ep) : (((ep) - 15) | 0x80))
+#define EP_ADDR_TO_PHYS_EP(a) (((a) & 0x80) ? (((a) & ~0x80) + 15) : (a))
+
+/* MOD_CONF_CTRL_0 bits (FIXME: move to board hardware.h ?) */
+#define CONF_MOD_USB_W2FC_VBUS_MODE_R (1 << 17)
+
+/* Other registers (may be) related to USB */
+
+#define CLOCK_CTRL	    (0xFFFE0830)
+#define APLL_CTRL	    (0xFFFE084C)
+#define DPLL_CTRL	    (0xFFFE083C)
+#define SOFT_REQ	    (0xFFFE0834)
+#define STATUS_REQ	    (0xFFFE0840)
+
+/* FUNC_MUX_CTRL_0 bits related to USB */
+#define UDC_VBUS_CTRL	    (1 << 19)
+#define UDC_VBUS_MODE	    (1 << 18)
+
+/* OMAP Endpoint parameters */
+#define UDC_OUT_PACKET_SIZE	64
+#define UDC_IN_PACKET_SIZE	64
+#define UDC_INT_PACKET_SIZE	16
+#define UDC_BULK_PACKET_SIZE	16
+
+#define UDC_INT_ENDPOINT 5
+#define UDC_OUT_ENDPOINT 2
+#define UDC_IN_ENDPOINT	1
+
+#endif
diff --git a/qemu/roms/u-boot/include/usb/pxa27x_udc.h b/qemu/roms/u-boot/include/usb/pxa27x_udc.h
new file mode 100644
index 000000000..7eaa00030
--- /dev/null
+++ b/qemu/roms/u-boot/include/usb/pxa27x_udc.h
@@ -0,0 +1,32 @@
+/*
+ * PXA27x register declarations and HCD data structures
+ *
+ * Copyright (C) 2007 Rodolfo Giometti <giometti@linux.it>
+ * Copyright (C) 2007 Eurotech S.p.A. <info@eurotech.it>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+
+#ifndef __PXA270X_UDC_H__
+#define __PXA270X_UDC_H__
+
+#include <asm/byteorder.h>
+
+/* Endpoint 0 states */
+#define EP0_IDLE		0
+#define EP0_IN_DATA		1
+#define EP0_OUT_DATA		2
+#define EP0_XFER_COMPLETE	3
+
+
+/* Endpoint parameters */
+#define MAX_ENDPOINTS		4
+
+#define EP0_MAX_PACKET_SIZE     16
+
+#define UDC_OUT_ENDPOINT        0x02
+#define UDC_IN_ENDPOINT         0x01
+#define UDC_INT_ENDPOINT        0x05
+
+#endif
diff --git a/qemu/roms/u-boot/include/usb/s3c_udc.h b/qemu/roms/u-boot/include/usb/s3c_udc.h
new file mode 100644
index 000000000..70e48f88e
--- /dev/null
+++ b/qemu/roms/u-boot/include/usb/s3c_udc.h
@@ -0,0 +1,112 @@
+/*
+ * drivers/usb/gadget/s3c_udc.h
+ * Samsung S3C on-chip full/high speed USB device controllers
+ * Copyright (C) 2005 for Samsung Electronics
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __S3C_USB_GADGET
+#define __S3C_USB_GADGET
+
+#include <asm/errno.h>
+#include <linux/sizes.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <linux/list.h>
+#include <usb/lin_gadget_compat.h>
+
+#define PHY0_SLEEP              (1 << 5)
+
+/*-------------------------------------------------------------------------*/
+/* DMA bounce buffer size, 16K is enough even for mass storage */
+#define DMA_BUFFER_SIZE	(16*SZ_1K)
+
+#define EP0_FIFO_SIZE		64
+#define EP_FIFO_SIZE		512
+#define EP_FIFO_SIZE2		1024
+/* ep0-control, ep1in-bulk, ep2out-bulk, ep3in-int */
+#define S3C_MAX_ENDPOINTS	4
+#define S3C_MAX_HW_ENDPOINTS	16
+
+#define WAIT_FOR_SETUP          0
+#define DATA_STATE_XMIT         1
+#define DATA_STATE_NEED_ZLP     2
+#define WAIT_FOR_OUT_STATUS     3
+#define DATA_STATE_RECV         4
+#define WAIT_FOR_COMPLETE	5
+#define WAIT_FOR_OUT_COMPLETE	6
+#define WAIT_FOR_IN_COMPLETE	7
+#define WAIT_FOR_NULL_COMPLETE	8
+
+#define TEST_J_SEL		0x1
+#define TEST_K_SEL		0x2
+#define TEST_SE0_NAK_SEL	0x3
+#define TEST_PACKET_SEL		0x4
+#define TEST_FORCE_ENABLE_SEL	0x5
+
+/* ************************************************************************* */
+/* IO
+ */
+
+enum ep_type {
+	ep_control, ep_bulk_in, ep_bulk_out, ep_interrupt
+};
+
+struct s3c_ep {
+	struct usb_ep ep;
+	struct s3c_udc *dev;
+
+	const struct usb_endpoint_descriptor *desc;
+	struct list_head queue;
+	unsigned long pio_irqs;
+	int len;
+	void *dma_buf;
+
+	u8 stopped;
+	u8 bEndpointAddress;
+	u8 bmAttributes;
+
+	enum ep_type ep_type;
+	int fifo_num;
+};
+
+struct s3c_request {
+	struct usb_request req;
+	struct list_head queue;
+};
+
+struct s3c_udc {
+	struct usb_gadget gadget;
+	struct usb_gadget_driver *driver;
+
+	struct s3c_plat_otg_data *pdata;
+
+	int ep0state;
+	struct s3c_ep ep[S3C_MAX_ENDPOINTS];
+
+	unsigned char usb_address;
+
+	unsigned req_pending:1, req_std:1;
+};
+
+extern struct s3c_udc *the_controller;
+
+#define ep_is_in(EP) (((EP)->bEndpointAddress&USB_DIR_IN) == USB_DIR_IN)
+#define ep_index(EP) ((EP)->bEndpointAddress&0xF)
+#define ep_maxpacket(EP) ((EP)->ep.maxpacket)
+
+extern void otg_phy_init(struct s3c_udc *dev);
+extern void otg_phy_off(struct s3c_udc *dev);
+
+extern void s3c_udc_ep_set_stall(struct s3c_ep *ep);
+extern int s3c_udc_probe(struct s3c_plat_otg_data *pdata);
+
+struct s3c_plat_otg_data {
+	int		(*phy_control)(int on);
+	unsigned int	regs_phy;
+	unsigned int	regs_otg;
+	unsigned int    usb_phy_ctrl;
+	unsigned int    usb_flags;
+};
+#endif
diff --git a/qemu/roms/u-boot/include/usb/udc.h b/qemu/roms/u-boot/include/usb/udc.h
new file mode 100644
index 000000000..1f545ec1b
--- /dev/null
+++ b/qemu/roms/u-boot/include/usb/udc.h
@@ -0,0 +1,53 @@
+/*
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef USB_UDC_H
+#define USB_UDC_H
+
+#ifndef EP0_MAX_PACKET_SIZE
+#define EP0_MAX_PACKET_SIZE     64
+#endif
+
+#ifndef EP_MAX_PACKET_SIZE
+#define EP_MAX_PACKET_SIZE	64
+#endif
+
+#if !defined(CONFIG_PPC) && !defined(CONFIG_OMAP1510)
+/* omap1510_udc.h and mpc8xx_udc.h will set these values */
+#define UDC_OUT_PACKET_SIZE     EP_MAX_PACKET_SIZE
+#define UDC_IN_PACKET_SIZE      EP_MAX_PACKET_SIZE
+#define UDC_INT_PACKET_SIZE     EP_MAX_PACKET_SIZE
+#define UDC_BULK_PACKET_SIZE    EP_MAX_PACKET_SIZE
+#endif
+
+#define UDC_BULK_HS_PACKET_SIZE	512
+
+#ifndef UDC_INT_ENDPOINT
+#define UDC_INT_ENDPOINT	1
+#endif
+
+#ifndef UDC_OUT_ENDPOINT
+#define UDC_OUT_ENDPOINT	2
+#endif
+
+#ifndef UDC_IN_ENDPOINT
+#define UDC_IN_ENDPOINT		3
+#endif
+
+/* function declarations */
+int udc_init(void);
+void udc_irq(void);
+int udc_endpoint_write(struct usb_endpoint_instance *endpoint);
+void udc_setup_ep(struct usb_device_instance *device, unsigned int ep,
+		  struct usb_endpoint_instance *endpoint);
+void udc_connect(void);
+void udc_disconnect(void);
+void udc_enable(struct usb_device_instance *device);
+void udc_disable(void);
+void udc_startup_events(struct usb_device_instance *device);
+
+/* Flow control */
+void udc_set_nak(int epid);
+void udc_unset_nak(int epid);
+
+#endif
diff --git a/qemu/roms/u-boot/include/usb/ulpi.h b/qemu/roms/u-boot/include/usb/ulpi.h
new file mode 100644
index 000000000..99166c44a
--- /dev/null
+++ b/qemu/roms/u-boot/include/usb/ulpi.h
@@ -0,0 +1,319 @@
+/*
+ * Generic ULPI interface.
+ *
+ * Copyright (C) 2011 Jana Rapava <fermata7@gmail.com>
+ * Copyright (C) 2011 CompuLab, Ltd. <www.compulab.co.il>
+ *
+ * Authors: Jana Rapava <fermata7@gmail.com>
+ *	    Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * Register offsets taken from:
+ * linux/include/linux/usb/ulpi.h
+ *
+ * Original Copyrights follow:
+ * Copyright (C) 2010 Nokia Corporation
+ *
+ * This software is distributed under the terms of the GNU General
+ * Public License ("GPL") as published by the Free Software Foundation,
+ * version 2 of that License.
+ */
+
+#ifndef __USB_ULPI_H__
+#define __USB_ULPI_H__
+
+#define ULPI_ERROR	(1 << 8) /* overflow from any register value */
+
+#ifndef CONFIG_USB_ULPI_TIMEOUT
+#define CONFIG_USB_ULPI_TIMEOUT 1000	/* timeout in us */
+#endif
+
+/*
+ * ulpi view port address and
+ * Port_number that can be passed.
+ * Any additional data to be passed can
+ * be extended from this structure
+ */
+struct ulpi_viewport {
+	u32 viewport_addr;
+	u32 port_num;
+};
+
+/*
+ * Initialize the ULPI transciever and check the interface integrity.
+ * @ulpi_vp -  structure containing ULPI viewport data
+ *
+ * returns 0 on success, ULPI_ERROR on failure.
+ */
+int ulpi_init(struct ulpi_viewport *ulpi_vp);
+
+/*
+ * Select transceiver speed.
+ * @speed	- ULPI_FC_HIGH_SPEED, ULPI_FC_FULL_SPEED (default),
+ *                ULPI_FC_LOW_SPEED,  ULPI_FC_FS4LS
+ * returns 0 on success, ULPI_ERROR on failure.
+ */
+int ulpi_select_transceiver(struct ulpi_viewport *ulpi_vp, unsigned speed);
+
+/*
+ * Enable/disable VBUS.
+ * @ext_power		- external VBUS supply is used (default is false)
+ * @ext_indicator	- external VBUS over-current indicator is used
+ *
+ * returns 0 on success, ULPI_ERROR on failure.
+ */
+int ulpi_set_vbus(struct ulpi_viewport *ulpi_vp, int on, int ext_power);
+
+/*
+ * Configure VBUS indicator
+ * @external		- external VBUS over-current indicator is used
+ * @passthru		- disables ANDing of internal VBUS comparator
+ *                    with external VBUS input
+ * @complement		- inverts the external VBUS input
+ */
+int ulpi_set_vbus_indicator(struct ulpi_viewport *ulpi_vp, int external,
+			int passthru, int complement);
+
+/*
+ * Enable/disable pull-down resistors on D+ and D- USB lines.
+ *
+ * returns 0 on success, ULPI_ERROR on failure.
+ */
+int ulpi_set_pd(struct ulpi_viewport *ulpi_vp, int enable);
+
+/*
+ * Select OpMode.
+ * @opmode	- ULPI_FC_OPMODE_NORMAL (default), ULPI_FC_OPMODE_NONDRIVING,
+ *		  ULPI_FC_OPMODE_DISABLE_NRZI,	   ULPI_FC_OPMODE_NOSYNC_NOEOP
+ *
+ * returns 0 on success, ULPI_ERROR on failure.
+ */
+int ulpi_opmode_sel(struct ulpi_viewport *ulpi_vp, unsigned opmode);
+
+/*
+ * Switch to Serial Mode.
+ * @smode	- ULPI_IFACE_6_PIN_SERIAL_MODE or ULPI_IFACE_3_PIN_SERIAL_MODE
+ *
+ * returns 0 on success, ULPI_ERROR on failure.
+ *
+ * Notes:
+ * Switches immediately to Serial Mode.
+ * To return from Serial Mode, STP line needs to be asserted.
+ */
+int ulpi_serial_mode_enable(struct ulpi_viewport *ulpi_vp, unsigned smode);
+
+/*
+ * Put PHY into low power mode.
+ *
+ * returns 0 on success, ULPI_ERROR on failure.
+ *
+ * Notes:
+ * STP line must be driven low to keep the PHY in suspend.
+ * To resume the PHY, STP line needs to be asserted.
+ */
+int ulpi_suspend(struct ulpi_viewport *ulpi_vp);
+
+/*
+ * Reset the transceiver. ULPI interface and registers are not affected.
+ *
+ * returns 0 on success, ULPI_ERROR on failure.
+ */
+int ulpi_reset(struct ulpi_viewport *ulpi_vp);
+
+
+/* ULPI access methods below must be implemented for each ULPI viewport. */
+
+/*
+ * Write to the ULPI PHY register via the viewport.
+ * @reg		- the ULPI register (one of the fields in struct ulpi_regs).
+ * @value	- the value - only 8 lower bits are used, others ignored.
+ *
+ * returns 0 on success, ULPI_ERROR on failure.
+ */
+int ulpi_write(struct ulpi_viewport *ulpi_vp, u8 *reg, u32 value);
+
+/*
+ * Read the ULPI PHY register content via the viewport.
+ * @reg		- the ULPI register (one of the fields in struct ulpi_regs).
+ *
+ * returns register content on success, ULPI_ERROR on failure.
+ */
+u32 ulpi_read(struct ulpi_viewport *ulpi_vp, u8 *reg);
+
+/*
+ * Wait for the reset to complete.
+ * The Link must not attempt to access the PHY until the reset has
+ * completed and DIR line is de-asserted.
+ */
+int ulpi_reset_wait(struct ulpi_viewport *ulpi_vp);
+
+/* Access Extended Register Set (indicator) */
+#define ACCESS_EXT_REGS_OFFSET	0x2f	/* read-write */
+/* Vendor-specific */
+#define VENDOR_SPEC_OFFSET	0x30
+
+/*
+ * Extended Register Set
+ *
+ * Addresses 0x00-0x3F map directly to Immediate Register Set.
+ * Addresses 0x40-0x7F are reserved.
+ * Addresses 0x80-0xff are vendor-specific.
+ */
+#define EXT_VENDOR_SPEC_OFFSET	0x80
+
+/* ULPI registers, bits and offsets definitions */
+struct ulpi_regs {
+	/* Vendor ID and Product ID: 0x00 - 0x03 Read-only */
+	u8	vendor_id_low;
+	u8	vendor_id_high;
+	u8	product_id_low;
+	u8	product_id_high;
+	/* Function Control: 0x04 - 0x06 Read */
+	u8	function_ctrl;		/* 0x04 Write */
+	u8	function_ctrl_set;	/* 0x05 Set */
+	u8	function_ctrl_clear;	/* 0x06 Clear */
+	/* Interface Control: 0x07 - 0x09 Read */
+	u8	iface_ctrl;		/* 0x07 Write */
+	u8	iface_ctrl_set;		/* 0x08 Set */
+	u8	iface_ctrl_clear;	/* 0x09 Clear */
+	/* OTG Control: 0x0A - 0x0C Read */
+	u8	otg_ctrl;		/* 0x0A Write */
+	u8	otg_ctrl_set;		/* 0x0B Set */
+	u8	otg_ctrl_clear;		/* 0x0C Clear */
+	/* USB Interrupt Enable Rising: 0x0D - 0x0F Read */
+	u8	usb_ie_rising;		/* 0x0D Write */
+	u8	usb_ie_rising_set;	/* 0x0E Set */
+	u8	usb_ie_rising_clear;	/* 0x0F Clear */
+	/* USB Interrupt Enable Falling: 0x10 - 0x12 Read */
+	u8	usb_ie_falling;		/* 0x10 Write */
+	u8	usb_ie_falling_set;	/* 0x11 Set */
+	u8	usb_ie_falling_clear;	/* 0x12 Clear */
+	/* USB Interrupt Status: 0x13 Read-only */
+	u8	usb_int_status;
+	/* USB Interrupt Latch: 0x14 Read-only with auto-clear */
+	u8	usb_int_latch;
+	/* Debug: 0x15 Read-only */
+	u8	debug;
+	/* Scratch Register: 0x16 - 0x18 Read */
+	u8	scratch;		/* 0x16 Write */
+	u8	scratch_set;		/* 0x17 Set */
+	u8	scratch_clear;		/* 0x18 Clear */
+	/*
+	 * Optional Carkit registers:
+	 * Carkit Control: 0x19 - 0x1B Read
+	 */
+	u8	carkit_ctrl;		/* 0x19 Write */
+	u8	carkit_ctrl_set;	/* 0x1A Set */
+	u8	carkit_ctrl_clear;	/* 0x1B Clear */
+	/* Carkit Interrupt Delay: 0x1C Read, Write */
+	u8	carkit_int_delay;
+	/* Carkit Interrupt Enable: 0x1D - 0x1F Read */
+	u8	carkit_ie;		/* 0x1D Write */
+	u8	carkit_ie_set;		/* 0x1E Set */
+	u8	carkit_ie_clear;	/* 0x1F Clear */
+	/* Carkit Interrupt Status: 0x20 Read-only */
+	u8	carkit_int_status;
+	/* Carkit Interrupt Latch: 0x21 Read-only with auto-clear */
+	u8	carkit_int_latch;
+	/* Carkit Pulse Control: 0x22 - 0x24 Read */
+	u8	carkit_pulse_ctrl;		/* 0x22 Write */
+	u8	carkit_pulse_ctrl_set;		/* 0x23 Set */
+	u8	carkit_pulse_ctrl_clear;	/* 0x24 Clear */
+	/*
+	 * Other optional registers:
+	 * Transmit Positive Width: 0x25 Read, Write
+	 */
+	u8	transmit_pos_width;
+	/* Transmit Negative Width: 0x26 Read, Write */
+	u8	transmit_neg_width;
+	/* Receive Polarity Recovery: 0x27 Read, Write */
+	u8	recv_pol_recovery;
+	/*
+	 * Addresses 0x28 - 0x2E are reserved, so we use offsets
+	 * for immediate registers with higher addresses
+	 */
+};
+
+/*
+ * Register Bits
+ */
+
+/* Function Control */
+#define ULPI_FC_XCVRSEL_MASK		(3 << 0)
+#define ULPI_FC_HIGH_SPEED		(0 << 0)
+#define ULPI_FC_FULL_SPEED		(1 << 0)
+#define ULPI_FC_LOW_SPEED		(2 << 0)
+#define ULPI_FC_FS4LS			(3 << 0)
+#define ULPI_FC_TERMSELECT		(1 << 2)
+#define ULPI_FC_OPMODE_MASK		(3 << 3)
+#define ULPI_FC_OPMODE_NORMAL		(0 << 3)
+#define ULPI_FC_OPMODE_NONDRIVING	(1 << 3)
+#define ULPI_FC_OPMODE_DISABLE_NRZI	(2 << 3)
+#define ULPI_FC_OPMODE_NOSYNC_NOEOP	(3 << 3)
+#define ULPI_FC_RESET			(1 << 5)
+#define ULPI_FC_SUSPENDM		(1 << 6)
+
+/* Interface Control */
+#define ULPI_IFACE_6_PIN_SERIAL_MODE	(1 << 0)
+#define ULPI_IFACE_3_PIN_SERIAL_MODE	(1 << 1)
+#define ULPI_IFACE_CARKITMODE		(1 << 2)
+#define ULPI_IFACE_CLOCKSUSPENDM	(1 << 3)
+#define ULPI_IFACE_AUTORESUME		(1 << 4)
+#define ULPI_IFACE_EXTVBUS_COMPLEMENT	(1 << 5)
+#define ULPI_IFACE_PASSTHRU		(1 << 6)
+#define ULPI_IFACE_PROTECT_IFC_DISABLE	(1 << 7)
+
+/* OTG Control */
+#define ULPI_OTG_ID_PULLUP		(1 << 0)
+#define ULPI_OTG_DP_PULLDOWN		(1 << 1)
+#define ULPI_OTG_DM_PULLDOWN		(1 << 2)
+#define ULPI_OTG_DISCHRGVBUS		(1 << 3)
+#define ULPI_OTG_CHRGVBUS		(1 << 4)
+#define ULPI_OTG_DRVVBUS		(1 << 5)
+#define ULPI_OTG_DRVVBUS_EXT		(1 << 6)
+#define ULPI_OTG_EXTVBUSIND		(1 << 7)
+
+/*
+ * USB Interrupt Enable Rising,
+ * USB Interrupt Enable Falling,
+ * USB Interrupt Status and
+ * USB Interrupt Latch
+ */
+#define ULPI_INT_HOST_DISCONNECT	(1 << 0)
+#define ULPI_INT_VBUS_VALID		(1 << 1)
+#define ULPI_INT_SESS_VALID		(1 << 2)
+#define ULPI_INT_SESS_END		(1 << 3)
+#define ULPI_INT_IDGRD			(1 << 4)
+
+/* Debug */
+#define ULPI_DEBUG_LINESTATE0		(1 << 0)
+#define ULPI_DEBUG_LINESTATE1		(1 << 1)
+
+/* Carkit Control */
+#define ULPI_CARKIT_CTRL_CARKITPWR		(1 << 0)
+#define ULPI_CARKIT_CTRL_IDGNDDRV		(1 << 1)
+#define ULPI_CARKIT_CTRL_TXDEN			(1 << 2)
+#define ULPI_CARKIT_CTRL_RXDEN			(1 << 3)
+#define ULPI_CARKIT_CTRL_SPKLEFTEN		(1 << 4)
+#define ULPI_CARKIT_CTRL_SPKRIGHTEN		(1 << 5)
+#define ULPI_CARKIT_CTRL_MICEN			(1 << 6)
+
+/* Carkit Interrupt Enable */
+#define ULPI_CARKIT_INT_EN_IDFLOAT_RISE		(1 << 0)
+#define ULPI_CARKIT_INT_EN_IDFLOAT_FALL		(1 << 1)
+#define ULPI_CARKIT_INT_EN_CARINTDET		(1 << 2)
+#define ULPI_CARKIT_INT_EN_DP_RISE		(1 << 3)
+#define ULPI_CARKIT_INT_EN_DP_FALL		(1 << 4)
+
+/* Carkit Interrupt Status and Latch */
+#define ULPI_CARKIT_INT_IDFLOAT			(1 << 0)
+#define ULPI_CARKIT_INT_CARINTDET		(1 << 1)
+#define ULPI_CARKIT_INT_DP			(1 << 2)
+
+/* Carkit Pulse Control*/
+#define ULPI_CARKIT_PLS_CTRL_TXPLSEN		(1 << 0)
+#define ULPI_CARKIT_PLS_CTRL_RXPLSEN		(1 << 1)
+#define ULPI_CARKIT_PLS_CTRL_SPKRLEFT_BIASEN	(1 << 2)
+#define ULPI_CARKIT_PLS_CTRL_SPKRRIGHT_BIASEN	(1 << 3)
+
+
+#endif /* __USB_ULPI_H__ */
diff --git a/qemu/roms/u-boot/include/usb_cdc_acm.h b/qemu/roms/u-boot/include/usb_cdc_acm.h
new file mode 100644
index 000000000..5709ecac4
--- /dev/null
+++ b/qemu/roms/u-boot/include/usb_cdc_acm.h
@@ -0,0 +1,30 @@
+/*
+ * (C) Copyright 2006
+ * Bryan O'Donoghue, deckard@codehermit.ie, CodeHermit
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* ACM Control Requests */
+#define ACM_SEND_ENCAPSULATED_COMMAND	0x00
+#define ACM_GET_ENCAPSULATED_RESPONSE	0x01
+#define ACM_SET_COMM_FEATURE		0x02
+#define ACM_GET_COMM_FEATRUE		0x03
+#define ACM_CLEAR_COMM_FEATURE		0x04
+#define ACM_SET_LINE_ENCODING		0x20
+#define ACM_GET_LINE_ENCODING		0x21
+#define ACM_SET_CONTROL_LINE_STATE	0x22
+#define ACM_SEND_BREAK			0x23
+
+/* ACM Notification Codes */
+#define ACM_NETWORK_CONNECTION		0x00
+#define ACM_RESPONSE_AVAILABLE		0x01
+#define ACM_SERIAL_STATE		0x20
+
+/* Format of response expected by a ACM_GET_LINE_ENCODING request */
+struct rs232_emu{
+		unsigned long dter;
+		unsigned char stop_bits;
+		unsigned char parity;
+		unsigned char data_bits;
+}__attribute__((packed));
diff --git a/qemu/roms/u-boot/include/usb_defs.h b/qemu/roms/u-boot/include/usb_defs.h
new file mode 100644
index 000000000..236a5ecdf
--- /dev/null
+++ b/qemu/roms/u-boot/include/usb_defs.h
@@ -0,0 +1,289 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Note: Part of this code has been derived from linux
+ */
+#ifndef _USB_DEFS_H_
+#define _USB_DEFS_H_
+
+/* USB constants */
+
+/* Device and/or Interface Class codes */
+#define USB_CLASS_PER_INTERFACE  0	/* for DeviceClass */
+#define USB_CLASS_AUDIO          1
+#define USB_CLASS_COMM           2
+#define USB_CLASS_HID            3
+#define USB_CLASS_PRINTER	       7
+#define USB_CLASS_MASS_STORAGE   8
+#define USB_CLASS_HUB            9
+#define USB_CLASS_DATA           10
+#define USB_CLASS_VENDOR_SPEC    0xff
+
+/* some HID sub classes */
+#define USB_SUB_HID_NONE        0
+#define USB_SUB_HID_BOOT        1
+
+/* some UID Protocols */
+#define USB_PROT_HID_NONE       0
+#define USB_PROT_HID_KEYBOARD   1
+#define USB_PROT_HID_MOUSE      2
+
+
+/* Sub STORAGE Classes */
+#define US_SC_RBC              1		/* Typically, flash devices */
+#define US_SC_8020             2		/* CD-ROM */
+#define US_SC_QIC              3		/* QIC-157 Tapes */
+#define US_SC_UFI              4		/* Floppy */
+#define US_SC_8070             5		/* Removable media */
+#define US_SC_SCSI             6		/* Transparent */
+#define US_SC_MIN              US_SC_RBC
+#define US_SC_MAX              US_SC_SCSI
+
+/* STORAGE Protocols */
+#define US_PR_CB               1		/* Control/Bulk w/o interrupt */
+#define US_PR_CBI              0		/* Control/Bulk/Interrupt */
+#define US_PR_BULK             0x50		/* bulk only */
+
+/* USB types */
+#define USB_TYPE_STANDARD   (0x00 << 5)
+#define USB_TYPE_CLASS      (0x01 << 5)
+#define USB_TYPE_VENDOR     (0x02 << 5)
+#define USB_TYPE_RESERVED   (0x03 << 5)
+
+/* USB recipients */
+#define USB_RECIP_DEVICE      0x00
+#define USB_RECIP_INTERFACE   0x01
+#define USB_RECIP_ENDPOINT    0x02
+#define USB_RECIP_OTHER       0x03
+
+/* USB directions */
+#define USB_DIR_OUT           0
+#define USB_DIR_IN            0x80
+
+/*
+ * bmRequestType: USB Device Requests, table 9.2 USB 2.0 spec.
+ * (shifted) direction/type/recipient.
+ */
+#define DeviceRequest \
+	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
+
+#define DeviceOutRequest \
+	((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
+
+#define InterfaceRequest \
+	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
+
+#define EndpointRequest \
+	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
+
+#define EndpointOutRequest \
+	((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
+
+/* Descriptor types */
+#define USB_DT_DEVICE        0x01
+#define USB_DT_CONFIG        0x02
+#define USB_DT_STRING        0x03
+#define USB_DT_INTERFACE     0x04
+#define USB_DT_ENDPOINT      0x05
+
+#define USB_DT_HID          (USB_TYPE_CLASS | 0x01)
+#define USB_DT_REPORT       (USB_TYPE_CLASS | 0x02)
+#define USB_DT_PHYSICAL     (USB_TYPE_CLASS | 0x03)
+#define USB_DT_HUB          (USB_TYPE_CLASS | 0x09)
+
+/* Descriptor sizes per descriptor type */
+#define USB_DT_DEVICE_SIZE      18
+#define USB_DT_CONFIG_SIZE      9
+#define USB_DT_INTERFACE_SIZE   9
+#define USB_DT_ENDPOINT_SIZE    7
+#define USB_DT_ENDPOINT_AUDIO_SIZE  9	/* Audio extension */
+#define USB_DT_HUB_NONVAR_SIZE  7
+#define USB_DT_HID_SIZE         9
+
+/* Endpoints */
+#define USB_ENDPOINT_NUMBER_MASK  0x0f	/* in bEndpointAddress */
+#define USB_ENDPOINT_DIR_MASK     0x80
+
+#define USB_ENDPOINT_XFERTYPE_MASK 0x03	/* in bmAttributes */
+#define USB_ENDPOINT_XFER_CONTROL  0
+#define USB_ENDPOINT_XFER_ISOC     1
+#define USB_ENDPOINT_XFER_BULK     2
+#define USB_ENDPOINT_XFER_INT      3
+
+/* USB Packet IDs (PIDs) */
+#define USB_PID_UNDEF_0             0xf0
+#define USB_PID_OUT                 0xe1
+#define USB_PID_ACK                 0xd2
+#define USB_PID_DATA0               0xc3
+#define USB_PID_UNDEF_4             0xb4
+#define USB_PID_SOF                 0xa5
+#define USB_PID_UNDEF_6             0x96
+#define USB_PID_UNDEF_7             0x87
+#define USB_PID_UNDEF_8             0x78
+#define USB_PID_IN                  0x69
+#define USB_PID_NAK                 0x5a
+#define USB_PID_DATA1               0x4b
+#define USB_PID_PREAMBLE            0x3c
+#define USB_PID_SETUP               0x2d
+#define USB_PID_STALL               0x1e
+#define USB_PID_UNDEF_F             0x0f
+
+/* Standard requests */
+#define USB_REQ_GET_STATUS          0x00
+#define USB_REQ_CLEAR_FEATURE       0x01
+#define USB_REQ_SET_FEATURE         0x03
+#define USB_REQ_SET_ADDRESS         0x05
+#define USB_REQ_GET_DESCRIPTOR      0x06
+#define USB_REQ_SET_DESCRIPTOR      0x07
+#define USB_REQ_GET_CONFIGURATION   0x08
+#define USB_REQ_SET_CONFIGURATION   0x09
+#define USB_REQ_GET_INTERFACE       0x0A
+#define USB_REQ_SET_INTERFACE       0x0B
+#define USB_REQ_SYNCH_FRAME         0x0C
+
+/* HID requests */
+#define USB_REQ_GET_REPORT          0x01
+#define USB_REQ_GET_IDLE            0x02
+#define USB_REQ_GET_PROTOCOL        0x03
+#define USB_REQ_SET_REPORT          0x09
+#define USB_REQ_SET_IDLE            0x0A
+#define USB_REQ_SET_PROTOCOL        0x0B
+
+/* Device features */
+#define USB_FEAT_HALT               0x00
+#define USB_FEAT_WAKEUP             0x01
+#define USB_FEAT_TEST               0x02
+
+/* Test modes */
+#define USB_TEST_MODE_J             0x01
+#define USB_TEST_MODE_K             0x02
+#define USB_TEST_MODE_SE0_NAK       0x03
+#define USB_TEST_MODE_PACKET        0x04
+#define USB_TEST_MODE_FORCE_ENABLE  0x05
+
+
+/* "pipe" definitions */
+
+#define PIPE_ISOCHRONOUS    0
+#define PIPE_INTERRUPT      1
+#define PIPE_CONTROL        2
+#define PIPE_BULK           3
+#define PIPE_DEVEP_MASK     0x0007ff00
+
+#define USB_ISOCHRONOUS    0
+#define USB_INTERRUPT      1
+#define USB_CONTROL        2
+#define USB_BULK           3
+
+/* USB-status codes: */
+#define USB_ST_ACTIVE           0x1		/* TD is active */
+#define USB_ST_STALLED          0x2		/* TD is stalled */
+#define USB_ST_BUF_ERR          0x4		/* buffer error */
+#define USB_ST_BABBLE_DET       0x8		/* Babble detected */
+#define USB_ST_NAK_REC          0x10	/* NAK Received*/
+#define USB_ST_CRC_ERR          0x20	/* CRC/timeout Error */
+#define USB_ST_BIT_ERR          0x40	/* Bitstuff error */
+#define USB_ST_NOT_PROC         0x80000000L	/* Not yet processed */
+
+
+/*************************************************************************
+ * Hub defines
+ */
+
+/*
+ * Hub request types
+ */
+
+#define USB_RT_HUB	(USB_TYPE_CLASS | USB_RECIP_DEVICE)
+#define USB_RT_PORT	(USB_TYPE_CLASS | USB_RECIP_OTHER)
+
+/*
+ * Hub Class feature numbers
+ */
+#define C_HUB_LOCAL_POWER   0
+#define C_HUB_OVER_CURRENT  1
+
+/*
+ * Port feature numbers
+ */
+#define USB_PORT_FEAT_CONNECTION     0
+#define USB_PORT_FEAT_ENABLE         1
+#define USB_PORT_FEAT_SUSPEND        2
+#define USB_PORT_FEAT_OVER_CURRENT   3
+#define USB_PORT_FEAT_RESET          4
+#define USB_PORT_FEAT_POWER          8
+#define USB_PORT_FEAT_LOWSPEED       9
+#define USB_PORT_FEAT_HIGHSPEED      10
+#define USB_PORT_FEAT_C_CONNECTION   16
+#define USB_PORT_FEAT_C_ENABLE       17
+#define USB_PORT_FEAT_C_SUSPEND      18
+#define USB_PORT_FEAT_C_OVER_CURRENT 19
+#define USB_PORT_FEAT_C_RESET        20
+#define USB_PORT_FEAT_TEST           21
+
+/*
+ * Changes to Port feature numbers for Super speed,
+ * from USB 3.0 spec Table 10-8
+ */
+#define USB_SS_PORT_FEAT_U1_TIMEOUT	23
+#define USB_SS_PORT_FEAT_U2_TIMEOUT	24
+#define USB_SS_PORT_FEAT_C_LINK_STATE	25
+#define USB_SS_PORT_FEAT_C_CONFIG_ERROR	26
+#define USB_SS_PORT_FEAT_BH_RESET	28
+#define USB_SS_PORT_FEAT_C_BH_RESET	29
+
+/* wPortStatus bits */
+#define USB_PORT_STAT_CONNECTION    0x0001
+#define USB_PORT_STAT_ENABLE        0x0002
+#define USB_PORT_STAT_SUSPEND       0x0004
+#define USB_PORT_STAT_OVERCURRENT   0x0008
+#define USB_PORT_STAT_RESET         0x0010
+#define USB_PORT_STAT_POWER         0x0100
+#define USB_PORT_STAT_LOW_SPEED     0x0200
+#define USB_PORT_STAT_HIGH_SPEED    0x0400	/* support for EHCI */
+#define USB_PORT_STAT_SUPER_SPEED   0x0600	/* faking support to XHCI */
+#define USB_PORT_STAT_SPEED_MASK	\
+	(USB_PORT_STAT_LOW_SPEED | USB_PORT_STAT_HIGH_SPEED)
+
+/*
+ * Changes to wPortStatus bit field in USB 3.0
+ * See USB 3.0 spec Table 10-11
+ */
+#define USB_SS_PORT_STAT_LINK_STATE	0x01e0
+#define USB_SS_PORT_STAT_POWER		0x0200
+#define USB_SS_PORT_STAT_SPEED		0x1c00
+#define USB_SS_PORT_STAT_SPEED_5GBPS	0x0000
+
+/* wPortChange bits */
+#define USB_PORT_STAT_C_CONNECTION  0x0001
+#define USB_PORT_STAT_C_ENABLE      0x0002
+#define USB_PORT_STAT_C_SUSPEND     0x0004
+#define USB_PORT_STAT_C_OVERCURRENT 0x0008
+#define USB_PORT_STAT_C_RESET       0x0010
+
+/*
+ * Changes to wPortChange bit fields in USB 3.0
+ * See USB 3.0 spec Table 10-12
+ */
+#define USB_SS_PORT_STAT_C_BH_RESET	0x0020
+#define USB_SS_PORT_STAT_C_LINK_STATE	0x0040
+#define USB_SS_PORT_STAT_C_CONFIG_ERROR	0x0080
+
+/* wHubCharacteristics (masks) */
+#define HUB_CHAR_LPSM               0x0003
+#define HUB_CHAR_COMPOUND           0x0004
+#define HUB_CHAR_OCPM               0x0018
+
+/*
+ * Hub Status & Hub Change bit masks
+ */
+#define HUB_STATUS_LOCAL_POWER	0x0001
+#define HUB_STATUS_OVERCURRENT	0x0002
+
+#define HUB_CHANGE_LOCAL_POWER	0x0001
+#define HUB_CHANGE_OVERCURRENT	0x0002
+
+#endif /*_USB_DEFS_H_ */
diff --git a/qemu/roms/u-boot/include/usb_ether.h b/qemu/roms/u-boot/include/usb_ether.h
new file mode 100644
index 000000000..35700a21b
--- /dev/null
+++ b/qemu/roms/u-boot/include/usb_ether.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __USB_ETHER_H__
+#define __USB_ETHER_H__
+
+#include <net.h>
+
+/*
+ *	IEEE 802.3 Ethernet magic constants.  The frame sizes omit the preamble
+ *	and FCS/CRC (frame check sequence).
+ */
+#define ETH_ALEN	6		/* Octets in one ethernet addr	 */
+#define ETH_HLEN	14		/* Total octets in header.	 */
+#define ETH_ZLEN	60		/* Min. octets in frame sans FCS */
+#define ETH_DATA_LEN	1500		/* Max. octets in payload	 */
+#define ETH_FRAME_LEN	PKTSIZE_ALIGN	/* Max. octets in frame sans FCS */
+#define ETH_FCS_LEN	4		/* Octets in the FCS		 */
+
+struct ueth_data {
+	/* eth info */
+	struct eth_device eth_dev;		/* used with eth_register */
+	int phy_id;						/* mii phy id */
+
+	/* usb info */
+	struct usb_device *pusb_dev;	/* this usb_device */
+	unsigned char	ifnum;			/* interface number */
+	unsigned char	ep_in;			/* in endpoint */
+	unsigned char	ep_out;			/* out ....... */
+	unsigned char	ep_int;			/* interrupt . */
+	unsigned char	subclass;		/* as in overview */
+	unsigned char	protocol;		/* .............. */
+	unsigned char	irqinterval;	/* Intervall for IRQ Pipe */
+
+	/* driver private */
+	void *dev_priv;
+};
+
+/*
+ * Function definitions for each USB ethernet driver go here
+ * (declaration is unconditional, compilation is conditional)
+ */
+void asix_eth_before_probe(void);
+int asix_eth_probe(struct usb_device *dev, unsigned int ifnum,
+		      struct ueth_data *ss);
+int asix_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
+		      struct eth_device *eth);
+
+void mcs7830_eth_before_probe(void);
+int mcs7830_eth_probe(struct usb_device *dev, unsigned int ifnum,
+		      struct ueth_data *ss);
+int mcs7830_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
+			 struct eth_device *eth);
+
+void smsc95xx_eth_before_probe(void);
+int smsc95xx_eth_probe(struct usb_device *dev, unsigned int ifnum,
+			struct ueth_data *ss);
+int smsc95xx_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
+			struct eth_device *eth);
+
+#endif /* __USB_ETHER_H__ */
diff --git a/qemu/roms/u-boot/include/usb_mass_storage.h b/qemu/roms/u-boot/include/usb_mass_storage.h
new file mode 100644
index 000000000..ed460644c
--- /dev/null
+++ b/qemu/roms/u-boot/include/usb_mass_storage.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2011 Samsung Electrnoics
+ * Lukasz Majewski <l.majewski@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __USB_MASS_STORAGE_H__
+#define __USB_MASS_STORAGE_H__
+
+#define SECTOR_SIZE		0x200
+#include <mmc.h>
+#include <linux/usb/composite.h>
+
+#ifndef UMS_START_SECTOR
+#define UMS_START_SECTOR	0
+#endif
+
+#ifndef UMS_NUM_SECTORS
+#define UMS_NUM_SECTORS		0
+#endif
+
+/* Wait at maximum 60 seconds for cable connection */
+#define UMS_CABLE_READY_TIMEOUT	60
+
+struct ums {
+	int (*read_sector)(struct ums *ums_dev,
+			   ulong start, lbaint_t blkcnt, void *buf);
+	int (*write_sector)(struct ums *ums_dev,
+			    ulong start, lbaint_t blkcnt, const void *buf);
+	unsigned int start_sector;
+	unsigned int num_sectors;
+	const char *name;
+	struct mmc *mmc;
+};
+
+extern struct ums *ums;
+
+int fsg_init(struct ums *);
+void fsg_cleanup(void);
+struct ums *ums_init(unsigned int);
+int fsg_main_thread(void *);
+int fsg_add(struct usb_configuration *c);
+#endif /* __USB_MASS_STORAGE_H__ */
diff --git a/qemu/roms/u-boot/include/usbdescriptors.h b/qemu/roms/u-boot/include/usbdescriptors.h
new file mode 100644
index 000000000..227b91995
--- /dev/null
+++ b/qemu/roms/u-boot/include/usbdescriptors.h
@@ -0,0 +1,535 @@
+/*
+ * (C) Copyright 2003
+ * Gerry Hamel, geh@ti.com, Texas Instruments
+ *
+ * Based on
+ * linux/drivers/usbd/usb-function.h - USB Function
+ *
+ * Copyright (c) 2000, 2001, 2002 Lineo
+ * Copyright (c) 2001 Hewlett Packard
+ *
+ * By:
+ *	Stuart Lynne <sl@lineo.com>,
+ *	Tom Rushworth <tbr@lineo.com>,
+ *	Bruce Balden <balden@lineo.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* USB Descriptors - Create a complete description of all of the
+ * function driver capabilities. These map directly to the USB descriptors.
+ *
+ * This heirarchy is created by the functions drivers and is passed to the
+ * usb-device driver when the function driver is registered.
+ *
+ *  device
+ *	configuration
+ *	     interface
+ *		alternate
+ *		     class
+ *		     class
+ *		alternate
+ *		     endpoint
+ *		     endpoint
+ *	     interface
+ *		alternate
+ *		     endpoint
+ *		     endpoint
+ *	configuration
+ *	     interface
+ *		alternate
+ *		     endpoint
+ *		     endpoint
+ *
+ *
+ * The configuration structures refer to the USB Configurations that will be
+ * made available to a USB HOST during the enumeration process.
+ *
+ * The USB HOST will select a configuration and optionally an interface with
+ * the usb set configuration and set interface commands.
+ *
+ * The selected interface (or the default interface if not specifically
+ * selected) will define the list of endpoints that will be used.
+ *
+ * The configuration and interfaces are stored in an array that is indexed
+ * by the specified configuratin or interface number minus one.
+ *
+ * A configuration number of zero is used to specify a return to the unconfigured
+ * state.
+ *
+ */
+
+
+#ifndef __USBDESCRIPTORS_H__
+#define __USBDESCRIPTORS_H__
+
+#include <asm/types.h>
+
+/*
+ * communications class types
+ *
+ * c.f. CDC  USB Class Definitions for Communications Devices
+ * c.f. WMCD USB CDC Subclass Specification for Wireless Mobile Communications Devices
+ *
+ */
+
+#define CLASS_BCD_VERSION		0x0110
+
+/* c.f. CDC 4.1 Table 14 */
+#define COMMUNICATIONS_DEVICE_CLASS	0x02
+
+/* c.f. CDC 4.2 Table 15 */
+#define COMMUNICATIONS_INTERFACE_CLASS_CONTROL	0x02
+#define COMMUNICATIONS_INTERFACE_CLASS_DATA		0x0A
+#define COMMUNICATIONS_INTERFACE_CLASS_VENDOR	0x0FF
+
+/* c.f. CDC 4.3 Table 16 */
+#define COMMUNICATIONS_NO_SUBCLASS		0x00
+#define COMMUNICATIONS_DLCM_SUBCLASS	0x01
+#define COMMUNICATIONS_ACM_SUBCLASS		0x02
+#define COMMUNICATIONS_TCM_SUBCLASS		0x03
+#define COMMUNICATIONS_MCCM_SUBCLASS	0x04
+#define COMMUNICATIONS_CCM_SUBCLASS		0x05
+#define COMMUNICATIONS_ENCM_SUBCLASS	0x06
+#define COMMUNICATIONS_ANCM_SUBCLASS	0x07
+
+/* c.f. WMCD 5.1 */
+#define COMMUNICATIONS_WHCM_SUBCLASS	0x08
+#define COMMUNICATIONS_DMM_SUBCLASS		0x09
+#define COMMUNICATIONS_MDLM_SUBCLASS	0x0a
+#define COMMUNICATIONS_OBEX_SUBCLASS	0x0b
+
+/* c.f. CDC 4.4 Table 17 */
+#define COMMUNICATIONS_NO_PROTOCOL		0x00
+#define COMMUNICATIONS_V25TER_PROTOCOL	0x01	/*Common AT Hayes compatible*/
+
+/* c.f. CDC 4.5 Table 18 */
+#define DATA_INTERFACE_CLASS		0x0a
+
+/* c.f. CDC 4.6 No Table */
+#define DATA_INTERFACE_SUBCLASS_NONE	0x00	/* No subclass pertinent */
+
+/* c.f. CDC 4.7 Table 19 */
+#define DATA_INTERFACE_PROTOCOL_NONE	0x00	/* No class protcol required */
+
+
+/* c.f. CDC 5.2.3 Table 24 */
+#define CS_INTERFACE		0x24
+#define CS_ENDPOINT			0x25
+
+/*
+ * bDescriptorSubtypes
+ *
+ * c.f. CDC 5.2.3 Table 25
+ * c.f. WMCD 5.3 Table 5.3
+ */
+
+#define USB_ST_HEADER		0x00
+#define USB_ST_CMF			0x01
+#define USB_ST_ACMF			0x02
+#define USB_ST_DLMF			0x03
+#define USB_ST_TRF			0x04
+#define USB_ST_TCLF			0x05
+#define USB_ST_UF			0x06
+#define USB_ST_CSF			0x07
+#define USB_ST_TOMF			0x08
+#define USB_ST_USBTF		0x09
+#define USB_ST_NCT			0x0a
+#define USB_ST_PUF			0x0b
+#define USB_ST_EUF			0x0c
+#define USB_ST_MCMF			0x0d
+#define USB_ST_CCMF			0x0e
+#define USB_ST_ENF			0x0f
+#define USB_ST_ATMNF		0x10
+
+#define USB_ST_WHCM			0x11
+#define USB_ST_MDLM			0x12
+#define USB_ST_MDLMD		0x13
+#define USB_ST_DMM			0x14
+#define USB_ST_OBEX			0x15
+#define USB_ST_CS			0x16
+#define USB_ST_CSD			0x17
+#define USB_ST_TCM			0x18
+
+/* endpoint modifiers
+ * static struct usb_endpoint_description function_default_A_1[] = {
+ *
+ *     {this_endpoint: 0, attributes: CONTROL,	 max_size: 8,  polling_interval: 0 },
+ *     {this_endpoint: 1, attributes: BULK,	 max_size: 64, polling_interval: 0, direction: IN},
+ *     {this_endpoint: 2, attributes: BULK,	 max_size: 64, polling_interval: 0, direction: OUT},
+ *     {this_endpoint: 3, attributes: INTERRUPT, max_size: 8,  polling_interval: 0},
+ *
+ *
+ */
+#define OUT		0x00
+#define IN		0x80
+
+#define CONTROL		0x00
+#define ISOCHRONOUS	0x01
+#define BULK		0x02
+#define INTERRUPT	0x03
+
+
+/* configuration modifiers
+ */
+#define BMATTRIBUTE_RESERVED		0x80
+#define BMATTRIBUTE_SELF_POWERED	0x40
+
+/*
+ * standard usb descriptor structures
+ */
+
+struct usb_endpoint_descriptor {
+	u8 bLength;
+	u8 bDescriptorType;	/* 0x5 */
+	u8 bEndpointAddress;
+	u8 bmAttributes;
+	u16 wMaxPacketSize;
+	u8 bInterval;
+} __attribute__ ((packed));
+
+struct usb_interface_descriptor {
+	u8 bLength;
+	u8 bDescriptorType;	/* 0x04 */
+	u8 bInterfaceNumber;
+	u8 bAlternateSetting;
+	u8 bNumEndpoints;
+	u8 bInterfaceClass;
+	u8 bInterfaceSubClass;
+	u8 bInterfaceProtocol;
+	u8 iInterface;
+} __attribute__ ((packed));
+
+struct usb_configuration_descriptor {
+	u8 bLength;
+	u8 bDescriptorType;	/* 0x2 */
+	u16 wTotalLength;
+	u8 bNumInterfaces;
+	u8 bConfigurationValue;
+	u8 iConfiguration;
+	u8 bmAttributes;
+	u8 bMaxPower;
+} __attribute__ ((packed));
+
+struct usb_device_descriptor {
+	u8 bLength;
+	u8 bDescriptorType;	/* 0x01 */
+	u16 bcdUSB;
+	u8 bDeviceClass;
+	u8 bDeviceSubClass;
+	u8 bDeviceProtocol;
+	u8 bMaxPacketSize0;
+	u16 idVendor;
+	u16 idProduct;
+	u16 bcdDevice;
+	u8 iManufacturer;
+	u8 iProduct;
+	u8 iSerialNumber;
+	u8 bNumConfigurations;
+} __attribute__ ((packed));
+
+#if defined(CONFIG_USBD_HS)
+struct usb_qualifier_descriptor {
+	u8 bLength;
+	u8 bDescriptorType;
+
+	u16 bcdUSB;
+	u8 bDeviceClass;
+	u8 bDeviceSubClass;
+	u8 bDeviceProtocol;
+	u8 bMaxPacketSize0;
+	u8 bNumConfigurations;
+	u8 breserved;
+} __attribute__ ((packed));
+#endif
+
+struct usb_string_descriptor {
+	u8 bLength;
+	u8 bDescriptorType;	/* 0x03 */
+	u16 wData[0];
+} __attribute__ ((packed));
+
+struct usb_generic_descriptor {
+	u8 bLength;
+	u8 bDescriptorType;
+	u8 bDescriptorSubtype;
+} __attribute__ ((packed));
+
+
+/*
+ * communications class descriptor structures
+ *
+ * c.f. CDC 5.2 Table 25c
+ */
+
+struct usb_class_function_descriptor {
+	u8 bFunctionLength;
+	u8 bDescriptorType;
+	u8 bDescriptorSubtype;
+} __attribute__ ((packed));
+
+struct usb_class_function_descriptor_generic {
+	u8 bFunctionLength;
+	u8 bDescriptorType;
+	u8 bDescriptorSubtype;
+	u8 bmCapabilities;
+} __attribute__ ((packed));
+
+struct usb_class_header_function_descriptor {
+	u8 bFunctionLength;
+	u8 bDescriptorType;
+	u8 bDescriptorSubtype;	/* 0x00 */
+	u16 bcdCDC;
+} __attribute__ ((packed));
+
+struct usb_class_call_management_descriptor {
+	u8 bFunctionLength;
+	u8 bDescriptorType;
+	u8 bDescriptorSubtype;	/* 0x01 */
+	u8 bmCapabilities;
+	u8 bDataInterface;
+} __attribute__ ((packed));
+
+struct usb_class_abstract_control_descriptor {
+	u8 bFunctionLength;
+	u8 bDescriptorType;
+	u8 bDescriptorSubtype;	/* 0x02 */
+	u8 bmCapabilities;
+} __attribute__ ((packed));
+
+struct usb_class_direct_line_descriptor {
+	u8 bFunctionLength;
+	u8 bDescriptorType;
+	u8 bDescriptorSubtype;	/* 0x03 */
+} __attribute__ ((packed));
+
+struct usb_class_telephone_ringer_descriptor {
+	u8 bFunctionLength;
+	u8 bDescriptorType;
+	u8 bDescriptorSubtype;	/* 0x04 */
+	u8 bRingerVolSeps;
+	u8 bNumRingerPatterns;
+} __attribute__ ((packed));
+
+struct usb_class_telephone_call_descriptor {
+	u8 bFunctionLength;
+	u8 bDescriptorType;
+	u8 bDescriptorSubtype;	/* 0x05 */
+	u8 bmCapabilities;
+} __attribute__ ((packed));
+
+struct usb_class_union_function_descriptor {
+	u8 bFunctionLength;
+	u8 bDescriptorType;
+	u8 bDescriptorSubtype;	/* 0x06 */
+	u8 bMasterInterface;
+	/* u8 bSlaveInterface0[0]; */
+	u8 bSlaveInterface0;
+} __attribute__ ((packed));
+
+struct usb_class_country_selection_descriptor {
+	u8 bFunctionLength;
+	u8 bDescriptorType;
+	u8 bDescriptorSubtype;	/* 0x07 */
+	u8 iCountryCodeRelDate;
+	u16 wCountryCode0[0];
+} __attribute__ ((packed));
+
+
+struct usb_class_telephone_operational_descriptor {
+	u8 bFunctionLength;
+	u8 bDescriptorType;
+	u8 bDescriptorSubtype;	/* 0x08 */
+	u8 bmCapabilities;
+} __attribute__ ((packed));
+
+
+struct usb_class_usb_terminal_descriptor {
+	u8 bFunctionLength;
+	u8 bDescriptorType;
+	u8 bDescriptorSubtype;	/* 0x09 */
+	u8 bEntityId;
+	u8 bInterfaceNo;
+	u8 bOutInterfaceNo;
+	u8 bmOptions;
+	u8 bChild0[0];
+} __attribute__ ((packed));
+
+struct usb_class_network_channel_descriptor {
+	u8 bFunctionLength;
+	u8 bDescriptorType;
+	u8 bDescriptorSubtype;	/* 0x0a */
+	u8 bEntityId;
+	u8 iName;
+	u8 bChannelIndex;
+	u8 bPhysicalInterface;
+} __attribute__ ((packed));
+
+struct usb_class_protocol_unit_function_descriptor {
+	u8 bFunctionLength;
+	u8 bDescriptorType;
+	u8 bDescriptorSubtype;	/* 0x0b */
+	u8 bEntityId;
+	u8 bProtocol;
+	u8 bChild0[0];
+} __attribute__ ((packed));
+
+struct usb_class_extension_unit_descriptor {
+	u8 bFunctionLength;
+	u8 bDescriptorType;
+	u8 bDescriptorSubtype;	/* 0x0c */
+	u8 bEntityId;
+	u8 bExtensionCode;
+	u8 iName;
+	u8 bChild0[0];
+} __attribute__ ((packed));
+
+struct usb_class_multi_channel_descriptor {
+	u8 bFunctionLength;
+	u8 bDescriptorType;
+	u8 bDescriptorSubtype;	/* 0x0d */
+	u8 bmCapabilities;
+} __attribute__ ((packed));
+
+struct usb_class_capi_control_descriptor {
+	u8 bFunctionLength;
+	u8 bDescriptorType;
+	u8 bDescriptorSubtype;	/* 0x0e */
+	u8 bmCapabilities;
+} __attribute__ ((packed));
+
+struct usb_class_ethernet_networking_descriptor {
+	u8 bFunctionLength;
+	u8 bDescriptorType;
+	u8 bDescriptorSubtype;	/* 0x0f */
+	u8 iMACAddress;
+	u32 bmEthernetStatistics;
+	u16 wMaxSegmentSize;
+	u16 wNumberMCFilters;
+	u8 bNumberPowerFilters;
+} __attribute__ ((packed));
+
+struct usb_class_atm_networking_descriptor {
+	u8 bFunctionLength;
+	u8 bDescriptorType;
+	u8 bDescriptorSubtype;	/* 0x10 */
+	u8 iEndSystermIdentifier;
+	u8 bmDataCapabilities;
+	u8 bmATMDeviceStatistics;
+	u16 wType2MaxSegmentSize;
+	u16 wType3MaxSegmentSize;
+	u16 wMaxVC;
+} __attribute__ ((packed));
+
+
+struct usb_class_mdlm_descriptor {
+	u8 bFunctionLength;
+	u8 bDescriptorType;
+	u8 bDescriptorSubtype;	/* 0x12 */
+	u16 bcdVersion;
+	u8 bGUID[16];
+} __attribute__ ((packed));
+
+struct usb_class_mdlmd_descriptor {
+	u8 bFunctionLength;
+	u8 bDescriptorType;
+	u8 bDescriptorSubtype;	/* 0x13 */
+	u8 bGuidDescriptorType;
+	u8 bDetailData[0];
+
+} __attribute__ ((packed));
+
+/*
+ * HID class descriptor structures
+ *
+ * c.f. HID 6.2.1
+ */
+
+struct usb_class_hid_descriptor {
+    u8	      bLength;
+    u8	      bDescriptorType;
+    u16	      bcdCDC;
+    u8	      bCountryCode;
+    u8	      bNumDescriptors;	/* 0x01 */
+    u8	      bDescriptorType0;
+    u16	      wDescriptorLength0;
+    /* optional descriptors are not supported. */
+} __attribute__((packed));
+
+struct usb_class_report_descriptor {
+    u8	      bLength;	/* dummy */
+    u8	      bDescriptorType;
+    u16	      wLength;
+    u8		bData[0];
+} __attribute__((packed));
+
+/*
+ * descriptor union structures
+ */
+
+struct usb_descriptor {
+	union {
+		struct usb_generic_descriptor generic;
+		struct usb_endpoint_descriptor endpoint;
+		struct usb_interface_descriptor interface;
+		struct usb_configuration_descriptor configuration;
+		struct usb_device_descriptor device;
+		struct usb_string_descriptor string;
+	} descriptor;
+
+} __attribute__ ((packed));
+
+struct usb_class_descriptor {
+	union {
+		struct usb_class_function_descriptor function;
+		struct usb_class_function_descriptor_generic generic;
+		struct usb_class_header_function_descriptor header_function;
+		struct usb_class_call_management_descriptor call_management;
+		struct usb_class_abstract_control_descriptor abstract_control;
+		struct usb_class_direct_line_descriptor direct_line;
+		struct usb_class_telephone_ringer_descriptor telephone_ringer;
+		struct usb_class_telephone_operational_descriptor telephone_operational;
+		struct usb_class_telephone_call_descriptor telephone_call;
+		struct usb_class_union_function_descriptor union_function;
+		struct usb_class_country_selection_descriptor country_selection;
+		struct usb_class_usb_terminal_descriptor usb_terminal;
+		struct usb_class_network_channel_descriptor network_channel;
+		struct usb_class_extension_unit_descriptor extension_unit;
+		struct usb_class_multi_channel_descriptor multi_channel;
+		struct usb_class_capi_control_descriptor capi_control;
+		struct usb_class_ethernet_networking_descriptor ethernet_networking;
+		struct usb_class_atm_networking_descriptor atm_networking;
+		struct usb_class_mdlm_descriptor mobile_direct;
+		struct usb_class_mdlmd_descriptor mobile_direct_detail;
+		struct usb_class_hid_descriptor hid;
+	} descriptor;
+
+} __attribute__ ((packed));
+
+#ifdef DEBUG
+static inline void print_device_descriptor(struct usb_device_descriptor *d)
+{
+	serial_printf("usb device descriptor \n");
+	serial_printf("\tbLength %2.2x\n", d->bLength);
+	serial_printf("\tbDescriptorType %2.2x\n", d->bDescriptorType);
+	serial_printf("\tbcdUSB %4.4x\n", d->bcdUSB);
+	serial_printf("\tbDeviceClass %2.2x\n", d->bDeviceClass);
+	serial_printf("\tbDeviceSubClass %2.2x\n", d->bDeviceSubClass);
+	serial_printf("\tbDeviceProtocol %2.2x\n", d->bDeviceProtocol);
+	serial_printf("\tbMaxPacketSize0 %2.2x\n", d->bMaxPacketSize0);
+	serial_printf("\tidVendor %4.4x\n", d->idVendor);
+	serial_printf("\tidProduct %4.4x\n", d->idProduct);
+	serial_printf("\tbcdDevice %4.4x\n", d->bcdDevice);
+	serial_printf("\tiManufacturer %2.2x\n", d->iManufacturer);
+	serial_printf("\tiProduct %2.2x\n", d->iProduct);
+	serial_printf("\tiSerialNumber %2.2x\n", d->iSerialNumber);
+	serial_printf("\tbNumConfigurations %2.2x\n", d->bNumConfigurations);
+}
+
+#else
+
+/* stubs */
+#define print_device_descriptor(d)
+
+#endif /* DEBUG */
+#endif
diff --git a/qemu/roms/u-boot/include/usbdevice.h b/qemu/roms/u-boot/include/usbdevice.h
new file mode 100644
index 000000000..da5af6efe
--- /dev/null
+++ b/qemu/roms/u-boot/include/usbdevice.h
@@ -0,0 +1,778 @@
+/*
+ * (C) Copyright 2003
+ * Gerry Hamel, geh@ti.com, Texas Instruments
+ *
+ * Based on linux/drivers/usbd/usbd.h
+ *
+ * Copyright (c) 2000, 2001, 2002 Lineo
+ * Copyright (c) 2001 Hewlett Packard
+ *
+ * By:
+ *	Stuart Lynne <sl@lineo.com>,
+ *	Tom Rushworth <tbr@lineo.com>,
+ *	Bruce Balden <balden@lineo.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __USBDCORE_H__
+#define __USBDCORE_H__
+
+#include <common.h>
+#include "usbdescriptors.h"
+
+
+#define MAX_URBS_QUEUED 5
+
+
+#if 1
+#define usberr(fmt,args...) serial_printf("ERROR: %s(), %d: "fmt"\n",__FUNCTION__,__LINE__,##args)
+#else
+#define usberr(fmt,args...) do{}while(0)
+#endif
+
+#if 0
+#define usbdbg(fmt,args...) serial_printf("debug: %s(), %d: "fmt"\n",__FUNCTION__,__LINE__,##args)
+#else
+#define usbdbg(fmt,args...) do{}while(0)
+#endif
+
+#if 0
+#define usbinfo(fmt,args...) serial_printf("info: %s(), %d: "fmt"\n",__FUNCTION__,__LINE__,##args)
+#else
+#define usbinfo(fmt,args...) do{}while(0)
+#endif
+
+#ifndef le16_to_cpu
+#define le16_to_cpu(x)	(x)
+#endif
+
+#ifndef inb
+#define inb(p)	     (*(volatile u8*)(p))
+#endif
+
+#ifndef outb
+#define outb(val,p)  (*(volatile u8*)(p) = (val))
+#endif
+
+#ifndef inw
+#define inw(p)	     (*(volatile u16*)(p))
+#endif
+
+#ifndef outw
+#define outw(val,p)  (*(volatile u16*)(p) = (val))
+#endif
+
+#ifndef inl
+#define inl(p)	     (*(volatile u32*)(p))
+#endif
+
+#ifndef outl
+#define outl(val,p)  (*(volatile u32*)(p) = (val))
+#endif
+
+#ifndef insw
+#define insw(p,to,len)	   mmio_insw(p,to,len)
+#endif
+
+#ifndef outsw
+#define outsw(p,from,len)  mmio_outsw(p,from,len)
+#endif
+
+#ifndef insb
+#define insb(p,to,len)	   mmio_insb(p,to,len)
+#endif
+
+#ifndef mmio_insw
+#define mmio_insw(r,b,l)	({	int __i ;  \
+					u16 *__b2;  \
+					__b2 = (u16 *) b;  \
+					for (__i = 0; __i < l; __i++) {	 \
+					  *(__b2 + __i) = inw(r);  \
+					};  \
+				})
+#endif
+
+#ifndef mmio_outsw
+#define mmio_outsw(r,b,l)	({	int __i; \
+					u16 *__b2; \
+					__b2 = (u16 *) b; \
+					for (__i = 0; __i < l; __i++) { \
+					    outw( *(__b2 + __i), r); \
+					} \
+				})
+#endif
+
+#ifndef mmio_insb
+#define mmio_insb(r,b,l)	({	int __i ;  \
+					u8 *__b2;  \
+					__b2 = (u8 *) b;  \
+					for (__i = 0; __i < l; __i++) {	 \
+					  *(__b2 + __i) = inb(r);  \
+					};  \
+				})
+#endif
+
+/*
+ * Structure member address manipulation macros.
+ * These are used by client code (code using the urb_link routines), since
+ * the urb_link structure is embedded in the client data structures.
+ *
+ * Note: a macro offsetof equivalent to member_offset is defined in stddef.h
+ *	 but this is kept here for the sake of portability.
+ *
+ * p2surround returns a pointer to the surrounding structure given
+ * type of the surrounding structure, the name memb of the structure
+ * member pointed at by ptr.  For example, if you have:
+ *
+ *	struct foo {
+ *	    int x;
+ *	    float y;
+ *	    char z;
+ *	} thingy;
+ *
+ *	char *cp = &thingy.z;
+ *
+ * then
+ *
+ *	&thingy == p2surround(struct foo, z, cp)
+ *
+ * Clear?
+ */
+#define _cv_(ptr)		  ((char*)(void*)(ptr))
+#define member_offset(type,memb)  (_cv_(&(((type*)0)->memb))-(char*)0)
+#define p2surround(type,memb,ptr) ((type*)(void*)(_cv_(ptr)-member_offset(type,memb)))
+
+struct urb;
+
+struct usb_endpoint_instance;
+struct usb_interface_instance;
+struct usb_configuration_instance;
+struct usb_device_instance;
+struct usb_bus_instance;
+
+/*
+ * Device and/or Interface Class codes
+ */
+#define USB_CLASS_PER_INTERFACE		0	/* for DeviceClass */
+#define USB_CLASS_AUDIO			1
+#define USB_CLASS_COMM			2
+#define USB_CLASS_HID			3
+#define USB_CLASS_PHYSICAL		5
+#define USB_CLASS_PRINTER		7
+#define USB_CLASS_MASS_STORAGE		8
+#define USB_CLASS_HUB			9
+#define USB_CLASS_DATA			10
+#define USB_CLASS_APP_SPEC		0xfe
+#define USB_CLASS_VENDOR_SPEC		0xff
+
+/*
+ * USB types
+ */
+#define USB_TYPE_STANDARD		(0x00 << 5)
+#define USB_TYPE_CLASS			(0x01 << 5)
+#define USB_TYPE_VENDOR			(0x02 << 5)
+#define USB_TYPE_RESERVED		(0x03 << 5)
+
+/*
+ * USB recipients
+ */
+#define USB_RECIP_DEVICE		0x00
+#define USB_RECIP_INTERFACE		0x01
+#define USB_RECIP_ENDPOINT		0x02
+#define USB_RECIP_OTHER			0x03
+
+/*
+ * USB directions
+ */
+#define USB_DIR_OUT			0
+#define USB_DIR_IN			0x80
+
+/*
+ * Descriptor types
+ */
+#define USB_DT_DEVICE			0x01
+#define USB_DT_CONFIG			0x02
+#define USB_DT_STRING			0x03
+#define USB_DT_INTERFACE		0x04
+#define USB_DT_ENDPOINT			0x05
+
+#if defined(CONFIG_USBD_HS)
+#define USB_DT_QUAL			0x06
+#endif
+
+#define USB_DT_HID			(USB_TYPE_CLASS | 0x01)
+#define USB_DT_REPORT			(USB_TYPE_CLASS | 0x02)
+#define USB_DT_PHYSICAL			(USB_TYPE_CLASS | 0x03)
+#define USB_DT_HUB			(USB_TYPE_CLASS | 0x09)
+
+/*
+ * Descriptor sizes per descriptor type
+ */
+#define USB_DT_DEVICE_SIZE		18
+#define USB_DT_CONFIG_SIZE		9
+#define USB_DT_INTERFACE_SIZE		9
+#define USB_DT_ENDPOINT_SIZE		7
+#define USB_DT_ENDPOINT_AUDIO_SIZE	9	/* Audio extension */
+#define USB_DT_HUB_NONVAR_SIZE		7
+#define USB_DT_HID_SIZE			9
+
+/*
+ * Endpoints
+ */
+#define USB_ENDPOINT_NUMBER_MASK	0x0f	/* in bEndpointAddress */
+#define USB_ENDPOINT_DIR_MASK		0x80
+
+#define USB_ENDPOINT_XFERTYPE_MASK	0x03	/* in bmAttributes */
+#define USB_ENDPOINT_XFER_CONTROL	0
+#define USB_ENDPOINT_XFER_ISOC		1
+#define USB_ENDPOINT_XFER_BULK		2
+#define USB_ENDPOINT_XFER_INT		3
+
+/*
+ * USB Packet IDs (PIDs)
+ */
+#define USB_PID_UNDEF_0			       0xf0
+#define USB_PID_OUT			       0xe1
+#define USB_PID_ACK			       0xd2
+#define USB_PID_DATA0			       0xc3
+#define USB_PID_PING			       0xb4	/* USB 2.0 */
+#define USB_PID_SOF			       0xa5
+#define USB_PID_NYET			       0x96	/* USB 2.0 */
+#define USB_PID_DATA2			       0x87	/* USB 2.0 */
+#define USB_PID_SPLIT			       0x78	/* USB 2.0 */
+#define USB_PID_IN			       0x69
+#define USB_PID_NAK			       0x5a
+#define USB_PID_DATA1			       0x4b
+#define USB_PID_PREAMBLE		       0x3c	/* Token mode */
+#define USB_PID_ERR			       0x3c	/* USB 2.0: handshake mode */
+#define USB_PID_SETUP			       0x2d
+#define USB_PID_STALL			       0x1e
+#define USB_PID_MDATA			       0x0f	/* USB 2.0 */
+
+/*
+ * Standard requests
+ */
+#define USB_REQ_GET_STATUS		0x00
+#define USB_REQ_CLEAR_FEATURE		0x01
+#define USB_REQ_SET_FEATURE		0x03
+#define USB_REQ_SET_ADDRESS		0x05
+#define USB_REQ_GET_DESCRIPTOR		0x06
+#define USB_REQ_SET_DESCRIPTOR		0x07
+#define USB_REQ_GET_CONFIGURATION	0x08
+#define USB_REQ_SET_CONFIGURATION	0x09
+#define USB_REQ_GET_INTERFACE		0x0A
+#define USB_REQ_SET_INTERFACE		0x0B
+#define USB_REQ_SYNCH_FRAME		0x0C
+
+#define USBD_DEVICE_REQUESTS(x) (((unsigned int)x <= USB_REQ_SYNCH_FRAME) ? usbd_device_requests[x] : "UNKNOWN")
+
+/*
+ * HID requests
+ */
+#define USB_REQ_GET_REPORT		0x01
+#define USB_REQ_GET_IDLE		0x02
+#define USB_REQ_GET_PROTOCOL		0x03
+#define USB_REQ_SET_REPORT		0x09
+#define USB_REQ_SET_IDLE		0x0A
+#define USB_REQ_SET_PROTOCOL		0x0B
+
+
+/*
+ * USB Spec Release number
+ */
+
+#if defined(CONFIG_USBD_HS)
+#define USB_BCD_VERSION			0x0200
+#else
+#define USB_BCD_VERSION			0x0110
+#endif
+
+
+/*
+ * Device Requests	(c.f Table 9-2)
+ */
+
+#define USB_REQ_DIRECTION_MASK		0x80
+#define USB_REQ_TYPE_MASK		0x60
+#define USB_REQ_RECIPIENT_MASK		0x1f
+
+#define USB_REQ_DEVICE2HOST		0x80
+#define USB_REQ_HOST2DEVICE		0x00
+
+#define USB_REQ_TYPE_STANDARD		0x00
+#define USB_REQ_TYPE_CLASS		0x20
+#define USB_REQ_TYPE_VENDOR		0x40
+
+#define USB_REQ_RECIPIENT_DEVICE	0x00
+#define USB_REQ_RECIPIENT_INTERFACE	0x01
+#define USB_REQ_RECIPIENT_ENDPOINT	0x02
+#define USB_REQ_RECIPIENT_OTHER		0x03
+
+/*
+ * get status bits
+ */
+
+#define USB_STATUS_SELFPOWERED		0x01
+#define USB_STATUS_REMOTEWAKEUP		0x02
+
+#define USB_STATUS_HALT			0x01
+
+/*
+ * descriptor types
+ */
+
+#define USB_DESCRIPTOR_TYPE_DEVICE			0x01
+#define USB_DESCRIPTOR_TYPE_CONFIGURATION		0x02
+#define USB_DESCRIPTOR_TYPE_STRING			0x03
+#define USB_DESCRIPTOR_TYPE_INTERFACE			0x04
+#define USB_DESCRIPTOR_TYPE_ENDPOINT			0x05
+#define USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER		0x06
+#define USB_DESCRIPTOR_TYPE_OTHER_SPEED_CONFIGURATION	0x07
+#define USB_DESCRIPTOR_TYPE_INTERFACE_POWER		0x08
+#define USB_DESCRIPTOR_TYPE_HID				0x21
+#define USB_DESCRIPTOR_TYPE_REPORT			0x22
+
+#define USBD_DEVICE_DESCRIPTORS(x) (((unsigned int)x <= USB_DESCRIPTOR_TYPE_INTERFACE_POWER) ? \
+		usbd_device_descriptors[x] : "UNKNOWN")
+
+/*
+ * standard feature selectors
+ */
+#define USB_ENDPOINT_HALT		0x00
+#define USB_DEVICE_REMOTE_WAKEUP	0x01
+#define USB_TEST_MODE			0x02
+
+
+/* USB Requests
+ *
+ */
+
+struct usb_device_request {
+	u8 bmRequestType;
+	u8 bRequest;
+	u16 wValue;
+	u16 wIndex;
+	u16 wLength;
+} __attribute__ ((packed));
+
+
+/* USB Status
+ *
+ */
+typedef enum urb_send_status {
+	SEND_IN_PROGRESS,
+	SEND_FINISHED_OK,
+	SEND_FINISHED_ERROR,
+	RECV_READY,
+	RECV_OK,
+	RECV_ERROR
+} urb_send_status_t;
+
+/*
+ * Device State (c.f USB Spec 2.0 Figure 9-1)
+ *
+ * What state the usb device is in.
+ *
+ * Note the state does not change if the device is suspended, we simply set a
+ * flag to show that it is suspended.
+ *
+ */
+typedef enum usb_device_state {
+	STATE_INIT,		/* just initialized */
+	STATE_CREATED,		/* just created */
+	STATE_ATTACHED,		/* we are attached */
+	STATE_POWERED,		/* we have seen power indication (electrical bus signal) */
+	STATE_DEFAULT,		/* we been reset */
+	STATE_ADDRESSED,	/* we have been addressed (in default configuration) */
+	STATE_CONFIGURED,	/* we have seen a set configuration device command */
+	STATE_UNKNOWN,		/* destroyed */
+} usb_device_state_t;
+
+#define USBD_DEVICE_STATE(x) (((unsigned int)x <= STATE_UNKNOWN) ? usbd_device_states[x] : "UNKNOWN")
+
+/*
+ * Device status
+ *
+ * Overall state
+ */
+typedef enum usb_device_status {
+	USBD_OPENING,		/* we are currently opening */
+	USBD_OK,		/* ok to use */
+	USBD_SUSPENDED,		/* we are currently suspended */
+	USBD_CLOSING,		/* we are currently closing */
+} usb_device_status_t;
+
+#define USBD_DEVICE_STATUS(x) (((unsigned int)x <= USBD_CLOSING) ? usbd_device_status[x] : "UNKNOWN")
+
+/*
+ * Device Events
+ *
+ * These are defined in the USB Spec (c.f USB Spec 2.0 Figure 9-1).
+ *
+ * There are additional events defined to handle some extra actions we need
+ * to have handled.
+ *
+ */
+typedef enum usb_device_event {
+
+	DEVICE_UNKNOWN,		/* bi - unknown event */
+	DEVICE_INIT,		/* bi  - initialize */
+	DEVICE_CREATE,		/* bi  - */
+	DEVICE_HUB_CONFIGURED,	/* bi  - bus has been plugged int */
+	DEVICE_RESET,		/* bi  - hub has powered our port */
+
+	DEVICE_ADDRESS_ASSIGNED,	/* ep0 - set address setup received */
+	DEVICE_CONFIGURED,	/* ep0 - set configure setup received */
+	DEVICE_SET_INTERFACE,	/* ep0 - set interface setup received */
+
+	DEVICE_SET_FEATURE,	/* ep0 - set feature setup received */
+	DEVICE_CLEAR_FEATURE,	/* ep0 - clear feature setup received */
+
+	DEVICE_DE_CONFIGURED,	/* ep0 - set configure setup received for ?? */
+
+	DEVICE_BUS_INACTIVE,	/* bi  - bus in inactive (no SOF packets) */
+	DEVICE_BUS_ACTIVITY,	/* bi  - bus is active again */
+
+	DEVICE_POWER_INTERRUPTION,	/* bi  - hub has depowered our port */
+	DEVICE_HUB_RESET,	/* bi  - bus has been unplugged */
+	DEVICE_DESTROY,		/* bi  - device instance should be destroyed */
+
+	DEVICE_HOTPLUG,		/* bi  - a hotplug event has occured */
+
+	DEVICE_FUNCTION_PRIVATE,	/* function - private */
+
+} usb_device_event_t;
+
+
+typedef struct urb_link {
+	struct urb_link *next;
+	struct urb_link *prev;
+} urb_link;
+
+/* USB Data structure - for passing data around.
+ *
+ * This is used for both sending and receiving data.
+ *
+ * The callback function is used to let the function driver know when
+ * transmitted data has been sent.
+ *
+ * The callback function is set by the alloc_recv function when an urb is
+ * allocated for receiving data for an endpoint and used to call the
+ * function driver to inform it that data has arrived.
+ */
+
+/* in linux we'd malloc this, but in u-boot we prefer static data */
+#define URB_BUF_SIZE 512
+
+struct urb {
+
+	struct usb_endpoint_instance *endpoint;
+	struct usb_device_instance *device;
+
+	struct usb_device_request device_request;	/* contents of received SETUP packet */
+
+	struct urb_link link;	/* embedded struct for circular doubly linked list of urbs */
+
+	u8* buffer;
+	unsigned int buffer_length;
+	unsigned int actual_length;
+
+	urb_send_status_t status;
+	int data;
+
+	u16 buffer_data[URB_BUF_SIZE];	/* data received (OUT) or being sent (IN) */
+};
+
+/* Endpoint configuration
+ *
+ * Per endpoint configuration data. Used to track which function driver owns
+ * an endpoint.
+ *
+ */
+struct usb_endpoint_instance {
+	int endpoint_address;	/* logical endpoint address */
+
+	/* control */
+	int status;		/* halted */
+	int state;		/* available for use by bus interface driver */
+
+	/* receive side */
+	struct urb_link rcv;	/* received urbs */
+	struct urb_link rdy;	/* empty urbs ready to receive */
+	struct urb *rcv_urb;	/* active urb */
+	int rcv_attributes;	/* copy of bmAttributes from endpoint descriptor */
+	int rcv_packetSize;	/* maximum packet size from endpoint descriptor */
+	int rcv_transferSize;	/* maximum transfer size from function driver */
+	int rcv_queue;
+
+	/* transmit side */
+	struct urb_link tx;	/* urbs ready to transmit */
+	struct urb_link done;	/* transmitted urbs */
+	struct urb *tx_urb;	/* active urb */
+	int tx_attributes;	/* copy of bmAttributes from endpoint descriptor */
+	int tx_packetSize;	/* maximum packet size from endpoint descriptor */
+	int tx_transferSize;	/* maximum transfer size from function driver */
+	int tx_queue;
+
+	int sent;		/* data already sent */
+	int last;		/* data sent in last packet XXX do we need this */
+};
+
+struct usb_alternate_instance {
+	struct usb_interface_descriptor *interface_descriptor;
+
+	int endpoints;
+	int *endpoint_transfersize_array;
+	struct usb_endpoint_descriptor **endpoints_descriptor_array;
+};
+
+struct usb_interface_instance {
+	int alternates;
+	struct usb_alternate_instance *alternates_instance_array;
+};
+
+struct usb_configuration_instance {
+	int interfaces;
+	struct usb_configuration_descriptor *configuration_descriptor;
+	struct usb_interface_instance *interface_instance_array;
+};
+
+
+/* USB Device Instance
+ *
+ * For each physical bus interface we create a logical device structure. This
+ * tracks all of the required state to track the USB HOST's view of the device.
+ *
+ * Keep track of the device configuration for a real physical bus interface,
+ * this includes the bus interface, multiple function drivers, the current
+ * configuration and the current state.
+ *
+ * This will show:
+ *	the specific bus interface driver
+ *	the default endpoint 0 driver
+ *	the configured function driver
+ *	device state
+ *	device status
+ *	endpoint list
+ */
+
+struct usb_device_instance {
+
+	/* generic */
+	char *name;
+	struct usb_device_descriptor *device_descriptor;	/* per device descriptor */
+#if defined(CONFIG_USBD_HS)
+	struct usb_qualifier_descriptor *qualifier_descriptor;
+#endif
+
+	void (*event) (struct usb_device_instance *device, usb_device_event_t event, int data);
+
+	/* Do cdc device specific control requests */
+	int (*cdc_recv_setup)(struct usb_device_request *request, struct urb *urb);
+
+	/* bus interface */
+	struct usb_bus_instance *bus;	/* which bus interface driver */
+
+	/* configuration descriptors */
+	int configurations;
+	struct usb_configuration_instance *configuration_instance_array;
+
+	/* device state */
+	usb_device_state_t device_state;	/* current USB Device state */
+	usb_device_state_t device_previous_state;	/* current USB Device state */
+
+	u8 address;		/* current address (zero is default) */
+	u8 configuration;	/* current show configuration (zero is default) */
+	u8 interface;		/* current interface (zero is default) */
+	u8 alternate;		/* alternate flag */
+
+	usb_device_status_t status;	/* device status */
+
+	int urbs_queued;	/* number of submitted urbs */
+
+	/* Shouldn't need to make this atomic, all we need is a change indicator */
+	unsigned long usbd_rxtx_timestamp;
+	unsigned long usbd_last_rxtx_timestamp;
+
+};
+
+/* Bus Interface configuration structure
+ *
+ * This is allocated for each configured instance of a bus interface driver.
+ *
+ * The privdata pointer may be used by the bus interface driver to store private
+ * per instance state information.
+ */
+struct usb_bus_instance {
+
+	struct usb_device_instance *device;
+	struct usb_endpoint_instance *endpoint_array;	/* array of available configured endpoints */
+
+	int max_endpoints;	/* maximimum number of rx enpoints */
+	unsigned char			maxpacketsize;
+
+	unsigned int serial_number;
+	char *serial_number_str;
+	void *privdata;		/* private data for the bus interface */
+
+};
+
+extern char *usbd_device_events[];
+extern char *usbd_device_states[];
+extern char *usbd_device_status[];
+extern char *usbd_device_requests[];
+extern char *usbd_device_descriptors[];
+
+void urb_link_init (urb_link * ul);
+void urb_detach (struct urb *urb);
+urb_link *first_urb_link (urb_link * hd);
+struct urb *first_urb (urb_link * hd);
+struct urb *first_urb_detached (urb_link * hd);
+void urb_append (urb_link * hd, struct urb *urb);
+
+struct urb *usbd_alloc_urb (struct usb_device_instance *device, struct usb_endpoint_instance *endpoint);
+void	    usbd_dealloc_urb (struct urb *urb);
+
+/*
+ * usbd_device_event is used by bus interface drivers to tell the higher layers that
+ * certain events have taken place.
+ */
+void usbd_device_event_irq (struct usb_device_instance *conf, usb_device_event_t, int);
+void usbd_device_event (struct usb_device_instance *conf, usb_device_event_t, int);
+
+/* descriptors
+ *
+ * Various ways of finding descriptors based on the current device and any
+ * possible configuration / interface / endpoint for it.
+ */
+struct usb_configuration_descriptor *usbd_device_configuration_descriptor (struct usb_device_instance *, int, int);
+struct usb_function_instance *usbd_device_function_instance (struct usb_device_instance *, unsigned int);
+struct usb_interface_instance *usbd_device_interface_instance (struct usb_device_instance *, int, int, int);
+struct usb_alternate_instance *usbd_device_alternate_instance (struct usb_device_instance *, int, int, int, int);
+struct usb_interface_descriptor *usbd_device_interface_descriptor (struct usb_device_instance *, int, int, int, int);
+struct usb_endpoint_descriptor *usbd_device_endpoint_descriptor_index (struct usb_device_instance *, int, int, int, int, int);
+struct usb_class_descriptor *usbd_device_class_descriptor_index (struct usb_device_instance *, int, int, int, int, int);
+struct usb_class_report_descriptor *usbd_device_class_report_descriptor_index( struct usb_device_instance *, int , int , int , int , int );
+struct usb_endpoint_descriptor *usbd_device_endpoint_descriptor (struct usb_device_instance *, int, int, int, int, int);
+int				usbd_device_endpoint_transfersize (struct usb_device_instance *, int, int, int, int, int);
+struct usb_string_descriptor *usbd_get_string (u8);
+struct usb_device_descriptor *usbd_device_device_descriptor(struct
+		usb_device_instance *, int);
+
+#if defined(CONFIG_USBD_HS)
+/*
+ * is_usbd_high_speed routine needs to be defined by specific gadget driver
+ * It returns true if device enumerates at High speed
+ * Retuns false otherwise
+ */
+int is_usbd_high_speed(void);
+#endif
+int usbd_endpoint_halted (struct usb_device_instance *device, int endpoint);
+void usbd_rcv_complete(struct usb_endpoint_instance *endpoint, int len, int urb_bad);
+void usbd_tx_complete (struct usb_endpoint_instance *endpoint);
+
+/* These are macros used in debugging */
+#ifdef DEBUG
+static inline void print_urb(struct urb *u)
+{
+	serial_printf("urb %p\n", (u));
+	serial_printf("\tendpoint %p\n", u->endpoint);
+	serial_printf("\tdevice %p\n", u->device);
+	serial_printf("\tbuffer %p\n", u->buffer);
+	serial_printf("\tbuffer_length %d\n", u->buffer_length);
+	serial_printf("\tactual_length %d\n", u->actual_length);
+	serial_printf("\tstatus %d\n", u->status);
+	serial_printf("\tdata %d\n", u->data);
+}
+
+static inline void print_usb_device_request(struct usb_device_request *r)
+{
+	serial_printf("usb request\n");
+	serial_printf("\tbmRequestType 0x%2.2x\n", r->bmRequestType);
+	if ((r->bmRequestType & USB_REQ_DIRECTION_MASK) == 0)
+		serial_printf("\t\tDirection : To device\n");
+	else
+		serial_printf("\t\tDirection : To host\n");
+	if ((r->bmRequestType & USB_TYPE_STANDARD) == USB_TYPE_STANDARD)
+		serial_printf("\t\tType      : Standard\n");
+	if ((r->bmRequestType & USB_TYPE_CLASS) == USB_TYPE_CLASS)
+		serial_printf("\t\tType      : Standard\n");
+	if ((r->bmRequestType & USB_TYPE_VENDOR) == USB_TYPE_VENDOR)
+		serial_printf("\t\tType      : Standard\n");
+	if ((r->bmRequestType & USB_TYPE_RESERVED) == USB_TYPE_RESERVED)
+		serial_printf("\t\tType      : Standard\n");
+	if ((r->bmRequestType & USB_REQ_RECIPIENT_MASK) ==
+	    USB_REQ_RECIPIENT_DEVICE)
+		serial_printf("\t\tRecipient : Device\n");
+	if ((r->bmRequestType & USB_REQ_RECIPIENT_MASK) ==
+	    USB_REQ_RECIPIENT_INTERFACE)
+		serial_printf("\t\tRecipient : Interface\n");
+	if ((r->bmRequestType & USB_REQ_RECIPIENT_MASK) ==
+	    USB_REQ_RECIPIENT_ENDPOINT)
+		serial_printf("\t\tRecipient : Endpoint\n");
+	if ((r->bmRequestType & USB_REQ_RECIPIENT_MASK) ==
+	    USB_REQ_RECIPIENT_OTHER)
+		serial_printf("\t\tRecipient : Other\n");
+	serial_printf("\tbRequest      0x%2.2x\n", r->bRequest);
+	if (r->bRequest == USB_REQ_GET_STATUS)
+		serial_printf("\t\tGET_STATUS\n");
+	else if (r->bRequest == USB_REQ_SET_ADDRESS)
+		serial_printf("\t\tSET_ADDRESS\n");
+	else if (r->bRequest == USB_REQ_SET_FEATURE)
+		serial_printf("\t\tSET_FEATURE\n");
+	else if (r->bRequest == USB_REQ_GET_DESCRIPTOR)
+		serial_printf("\t\tGET_DESCRIPTOR\n");
+	else if (r->bRequest == USB_REQ_SET_CONFIGURATION)
+		serial_printf("\t\tSET_CONFIGURATION\n");
+	else if (r->bRequest == USB_REQ_SET_INTERFACE)
+		serial_printf("\t\tUSB_REQ_SET_INTERFACE\n");
+	else
+		serial_printf("\tUNKNOWN %d\n", r->bRequest);
+	serial_printf("\twValue        0x%4.4x\n", r->wValue);
+	if (r->bRequest == USB_REQ_GET_DESCRIPTOR) {
+		switch (r->wValue >> 8) {
+		case USB_DESCRIPTOR_TYPE_DEVICE:
+			serial_printf("\tDEVICE\n");
+			break;
+		case USB_DESCRIPTOR_TYPE_CONFIGURATION:
+			serial_printf("\tCONFIGURATION\n");
+			break;
+		case USB_DESCRIPTOR_TYPE_STRING:
+			serial_printf("\tSTRING\n");
+			break;
+		case USB_DESCRIPTOR_TYPE_INTERFACE:
+			serial_printf("\tINTERFACE\n");
+			break;
+		case USB_DESCRIPTOR_TYPE_ENDPOINT:
+			serial_printf("\tENDPOINT\n");
+			break;
+		case USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER:
+			serial_printf("\tDEVICE_QUALIFIER\n");
+			break;
+		case USB_DESCRIPTOR_TYPE_OTHER_SPEED_CONFIGURATION:
+			serial_printf("\tOTHER_SPEED_CONFIGURATION\n");
+			break;
+		case USB_DESCRIPTOR_TYPE_INTERFACE_POWER:
+			serial_printf("\tINTERFACE_POWER\n");
+			break;
+		case USB_DESCRIPTOR_TYPE_HID:
+			serial_printf("\tHID\n");
+			break;
+		case USB_DESCRIPTOR_TYPE_REPORT:
+			serial_printf("\tREPORT\n");
+			break;
+		default:
+			serial_printf("\tUNKNOWN TYPE\n");
+			break;
+		}
+	}
+	serial_printf("\twIndex        0x%4.4x\n", r->wIndex);
+	serial_printf("\twLength       0x%4.4x\n", r->wLength);
+}
+#else
+/* stubs */
+#define print_urb(u)
+#define print_usb_device_request(r)
+#endif /* DEBUG */
+#endif
diff --git a/qemu/roms/u-boot/include/usbroothubdes.h b/qemu/roms/u-boot/include/usbroothubdes.h
new file mode 100644
index 000000000..adb70cd6a
--- /dev/null
+++ b/qemu/roms/u-boot/include/usbroothubdes.h
@@ -0,0 +1,129 @@
+/*
+ * USB virtual root hub descriptors
+ *
+ * (C) Copyright 2014
+ * Stephen Warren swarren@wwwdotorg.org
+ *
+ * Based on ohci-hcd.c
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __USBROOTHUBDES_H__
+#define __USBROOTHUBDES_H__
+
+/* Device descriptor */
+static __u8 root_hub_dev_des[] = {
+	0x12,		/* __u8  bLength; */
+	0x01,		/* __u8  bDescriptorType; Device */
+	0x10,		/* __u16 bcdUSB; v1.1 */
+	0x01,
+	0x09,		/* __u8  bDeviceClass; HUB_CLASSCODE */
+	0x00,		/* __u8  bDeviceSubClass; */
+	0x00,		/* __u8  bDeviceProtocol; */
+	0x08,		/* __u8  bMaxPacketSize0; 8 Bytes */
+	0x00,		/* __u16 idVendor; */
+	0x00,
+	0x00,		/* __u16 idProduct; */
+	0x00,
+	0x00,		/* __u16 bcdDevice; */
+	0x00,
+	0x00,		/* __u8  iManufacturer; */
+	0x01,		/* __u8  iProduct; */
+	0x00,		/* __u8  iSerialNumber; */
+	0x01,		/* __u8  bNumConfigurations; */
+};
+
+/* Configuration descriptor */
+static __u8 root_hub_config_des[] = {
+	0x09,		/* __u8  bLength; */
+	0x02,		/* __u8  bDescriptorType; Configuration */
+	0x19,		/* __u16 wTotalLength; */
+	0x00,
+	0x01,		/* __u8  bNumInterfaces; */
+	0x01,		/* __u8  bConfigurationValue; */
+	0x00,		/* __u8  iConfiguration; */
+	0x40,		/* __u8  bmAttributes;
+			 *       Bit 7: Bus-powered
+			 *       6: Self-powered,
+			 *       5 Remote-wakwup,
+			 *       4..0: resvd
+			 */
+	0x00,		/* __u8  MaxPower; */
+	/* interface */
+	0x09,		/* __u8  if_bLength; */
+	0x04,		/* __u8  if_bDescriptorType; Interface */
+	0x00,		/* __u8  if_bInterfaceNumber; */
+	0x00,		/* __u8  if_bAlternateSetting; */
+	0x01,		/* __u8  if_bNumEndpoints; */
+	0x09,		/* __u8  if_bInterfaceClass; HUB_CLASSCODE */
+	0x00,		/* __u8  if_bInterfaceSubClass; */
+	0x00,		/* __u8  if_bInterfaceProtocol; */
+	0x00,		/* __u8  if_iInterface; */
+	/* endpoint */
+	0x07,		/* __u8  ep_bLength; */
+	0x05,		/* __u8  ep_bDescriptorType; Endpoint */
+	0x81,		/* __u8  ep_bEndpointAddress; IN Endpoint 1 */
+	0x03,		/* __u8  ep_bmAttributes; Interrupt */
+	0x02,		/* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
+	0x00,
+	0xff,		/* __u8  ep_bInterval; 255 ms */
+};
+
+#ifdef WANT_USB_ROOT_HUB_HUB_DES
+static unsigned char root_hub_hub_des[] = {
+	0x09,		/* __u8  bLength; */
+	0x29,		/* __u8  bDescriptorType; Hub-descriptor */
+	0x02,		/* __u8  bNbrPorts; */
+	0x00,		/* __u16 wHubCharacteristics; */
+	0x00,
+	0x01,		/* __u8  bPwrOn2pwrGood; 2ms */
+	0x00,		/* __u8  bHubContrCurrent; 0 mA */
+	0x00,		/* __u8  DeviceRemovable; *** 7 Ports max *** */
+	0xff,		/* __u8  PortPwrCtrlMask; *** 7 ports max *** */
+};
+#endif
+
+static unsigned char root_hub_str_index0[] = {
+	0x04,		/* __u8  bLength; */
+	0x03,		/* __u8  bDescriptorType; String-descriptor */
+	0x09,		/* __u8  lang ID */
+	0x04,		/* __u8  lang ID */
+};
+
+static unsigned char root_hub_str_index1[] = {
+	32,		/* __u8  bLength; */
+	0x03,		/* __u8  bDescriptorType; String-descriptor */
+	'U',		/* __u8  Unicode */
+	0,		/* __u8  Unicode */
+	'-',		/* __u8  Unicode */
+	0,		/* __u8  Unicode */
+	'B',		/* __u8  Unicode */
+	0,		/* __u8  Unicode */
+	'o',		/* __u8  Unicode */
+	0,		/* __u8  Unicode */
+	'o',		/* __u8  Unicode */
+	0,		/* __u8  Unicode */
+	't',		/* __u8  Unicode */
+	0,		/* __u8  Unicode */
+	' ',		/* __u8  Unicode */
+	0,		/* __u8  Unicode */
+	'R',		/* __u8  Unicode */
+	0,		/* __u8  Unicode */
+	'o',		/* __u8  Unicode */
+	0,		/* __u8  Unicode */
+	'o',		/* __u8  Unicode */
+	0,		/* __u8  Unicode */
+	't',		/* __u8  Unicode */
+	0,		/* __u8  Unicode */
+	' ',		/* __u8  Unicode */
+	0,		/* __u8  Unicode */
+	'H',		/* __u8  Unicode */
+	0,		/* __u8  Unicode */
+	'u',		/* __u8  Unicode */
+	0,		/* __u8  Unicode */
+	'b',		/* __u8  Unicode */
+	0,		/* __u8  Unicode */
+};
+
+#endif
diff --git a/qemu/roms/u-boot/include/uuid.h b/qemu/roms/u-boot/include/uuid.h
new file mode 100644
index 000000000..93027c1b2
--- /dev/null
+++ b/qemu/roms/u-boot/include/uuid.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2014 Samsung Electronics
+ * Przemyslaw Marczak <p.marczak@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __UUID_H__
+#define __UUID_H__
+
+/* This is structure is in big-endian */
+struct uuid {
+	unsigned int time_low;
+	unsigned short time_mid;
+	unsigned short time_hi_and_version;
+	unsigned char clock_seq_hi_and_reserved;
+	unsigned char clock_seq_low;
+	unsigned char node[6];
+} __packed;
+
+enum {
+	UUID_STR_FORMAT_STD,
+	UUID_STR_FORMAT_GUID
+};
+
+#define UUID_STR_LEN		36
+#define UUID_BIN_LEN		sizeof(struct uuid)
+
+#define UUID_VERSION_MASK	0xf000
+#define UUID_VERSION_SHIFT	12
+#define UUID_VERSION		0x4
+
+#define UUID_VARIANT_MASK	0xc0
+#define UUID_VARIANT_SHIFT	7
+#define UUID_VARIANT		0x1
+
+int uuid_str_valid(const char *uuid);
+int uuid_str_to_bin(char *uuid_str, unsigned char *uuid_bin, int str_format);
+void uuid_bin_to_str(unsigned char *uuid_bin, char *uuid_str, int str_format);
+void gen_rand_uuid(unsigned char *uuid_bin);
+void gen_rand_uuid_str(char *uuid_str, int str_format);
+#endif
diff --git a/qemu/roms/u-boot/include/version.h b/qemu/roms/u-boot/include/version.h
new file mode 100644
index 000000000..d6c7cf2ae
--- /dev/null
+++ b/qemu/roms/u-boot/include/version.h
@@ -0,0 +1,27 @@
+/*
+ * (C) Copyright 2000-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef	__VERSION_H__
+#define	__VERSION_H__
+
+#include <timestamp.h>
+
+#ifndef DO_DEPS_ONLY
+#include "generated/version_autogenerated.h"
+#endif
+
+#ifndef CONFIG_IDENT_STRING
+#define CONFIG_IDENT_STRING ""
+#endif
+
+#define U_BOOT_VERSION_STRING U_BOOT_VERSION " (" U_BOOT_DATE " - " \
+	U_BOOT_TIME ")" CONFIG_IDENT_STRING
+
+#ifndef __ASSEMBLY__
+extern const char version_string[];
+#endif	/* __ASSEMBLY__ */
+#endif	/* __VERSION_H__ */
diff --git a/qemu/roms/u-boot/include/video.h b/qemu/roms/u-boot/include/video.h
new file mode 100644
index 000000000..0ff857bc9
--- /dev/null
+++ b/qemu/roms/u-boot/include/video.h
@@ -0,0 +1,70 @@
+/*
+** MPC823 Video Controller
+** =======================
+** (C) 2000 by Paolo Scaffardi (arsenio@tin.it)
+** AIRVENT SAM s.p.a - RIMINI(ITALY)
+**
+*/
+
+#ifndef _VIDEO_H_
+#define _VIDEO_H_
+
+/* Video functions */
+
+int	video_init	(void *videobase);
+void	video_putc	(const char c);
+void	video_puts	(const char *s);
+
+/**
+ * Display a BMP format bitmap on the screen
+ *
+ * @param bmp_image	Address of BMP image
+ * @param x		X position to draw image
+ * @param y		Y position to draw image
+ */
+int video_display_bitmap(ulong bmp_image, int x, int y);
+
+/**
+ * Get the width of the screen in pixels
+ *
+ * @return width of screen in pixels
+ */
+int video_get_pixel_width(void);
+
+/**
+ * Get the height of the screen in pixels
+ *
+ * @return height of screen in pixels
+ */
+int video_get_pixel_height(void);
+
+/**
+ * Get the number of text lines/rows on the screen
+ *
+ * @return number of rows
+ */
+int video_get_screen_rows(void);
+
+/**
+ * Get the number of text columns on the screen
+ *
+ * @return number of columns
+ */
+int video_get_screen_columns(void);
+
+/**
+ * Set the position of the text cursor
+ *
+ * @param col	Column to place cursor (0 = left side)
+ * @param row	Row to place cursor (0 = top line)
+ */
+void video_position_cursor(unsigned col, unsigned row);
+
+/* Clear the display */
+void video_clear(void);
+
+#if defined(CONFIG_FORMIKE)
+int kwh043st20_f01_spi_startup(unsigned int bus, unsigned int cs,
+	unsigned int max_hz, unsigned int spi_mode);
+#endif
+#endif
diff --git a/qemu/roms/u-boot/include/video_ad7176.h b/qemu/roms/u-boot/include/video_ad7176.h
new file mode 100644
index 000000000..6a0230e5a
--- /dev/null
+++ b/qemu/roms/u-boot/include/video_ad7176.h
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2000
+ * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _VIDEO_AD7176_H_
+#define _VIDEO_AD7176_H_
+
+#define VIDEO_ENCODER_NAME	"Analog Devices AD7176"
+
+#define VIDEO_ENCODER_I2C_RATE	100000	/* Max rate is 100 kHz		*/
+#define VIDEO_ENCODER_CB_Y_CR_Y		/* Use CB Y CR Y format...	*/
+
+#define VIDEO_MODE_YUYV		/* The only mode supported by this encoder */
+#undef	VIDEO_MODE_RGB
+#define VIDEO_MODE_BPP		16
+
+#ifdef	VIDEO_MODE_PAL
+#define VIDEO_ACTIVE_COLS	720
+#define VIDEO_ACTIVE_ROWS	576
+#define VIDEO_VISIBLE_COLS	640
+#define VIDEO_VISIBLE_ROWS	480
+#endif
+
+#ifdef	VIDEO_MODE_NTSC
+#define VIDEO_ACTIVE_COLS	720
+#define VIDEO_ACTIVE_ROWS	525
+#define VIDEO_VISIBLE_COLS	640
+#define VIDEO_VISIBLE_ROWS	400
+#endif
+
+static unsigned char video_encoder_data[] = {
+#ifdef VIDEO_MODE_NTSC
+					0x04, /* Mode Register 0	*/
+#ifdef VIDEO_DEBUG_COLORBARS
+					0x82,
+#else
+					0x02, /* Mode Register 1	*/
+#endif	/* VIDEO_DEBUG_COLORBARS */
+					0x16, /* Subcarrier Freq 0	*/
+					0x7c, /* Subcarrier Freq 1	*/
+					0xf0, /* Subcarrier Freq 2	*/
+					0x21, /* Subcarrier Freq 3	*/
+					0x00, /* Subcarrier phase	*/
+					0x02, /* Timing Register 0	*/
+					0x00, /* Extended Captioning 0	*/
+					0x00, /* Extended Captioning 1	*/
+					0x00, /* Closed Captioning 0	*/
+					0x00, /* Closed Captioning 1	*/
+					0x00, /* Timing Register 1	*/
+					0x08, /* Mode Register 2	*/
+					0x00, /* Pedestal Register 0	*/
+					0x00, /* Pedestal Register 1	*/
+					0x00, /* Pedestal Register 2	*/
+					0x00, /* Pedestal Register 3	*/
+					0x00  /* Mode Register 3	*/
+
+#endif	/* VIDEO_MODE_NTSC */
+
+#ifdef VIDEO_MODE_PAL
+					0x05, /* Mode Register 0	*/
+#ifdef VIDEO_DEBUG_COLORBARS
+					0x82,
+#else
+					0x02, /* Mode Register 1 (2)	*/
+#endif	/* VIDEO_DEBUG_COLORBARS */
+					0xcb, /* Subcarrier Freq 0	*/
+					0x8a, /* Subcarrier Freq 1	*/
+					0x09, /* Subcarrier Freq 2	*/
+					0x2a, /* Subcarrier Freq 3	*/
+					0x00, /* Subcarrier phase	*/
+					0x0a, /* Timing Register 0 (a)	*/
+					0x00, /* Extended Captioning 0	*/
+					0x00, /* Extended Captioning 1	*/
+					0x00, /* Closed Captioning 0	*/
+					0x00, /* Closed Captioning 1	*/
+					0x00, /* Timing Register 1	*/
+					0x08, /* Mode Register 2 (8)	*/
+					0x00, /* Pedestal Register 0	*/
+					0x00, /* Pedestal Register 1	*/
+					0x00, /* Pedestal Register 2	*/
+					0x00, /* Pedestal Register 3	*/
+					0x00  /* Mode Register 3	*/
+#endif	/* VIDEO_MODE_PAL */
+} ;
+
+#endif	/* _VIDEO_AD7176_H_ */
diff --git a/qemu/roms/u-boot/include/video_ad7177.h b/qemu/roms/u-boot/include/video_ad7177.h
new file mode 100644
index 000000000..38436d641
--- /dev/null
+++ b/qemu/roms/u-boot/include/video_ad7177.h
@@ -0,0 +1,133 @@
+/*
+ * (C) Copyright 2000
+ * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _VIDEO_AD7177_H_
+#define _VIDEO_AD7177_H_
+
+/* #define VIDEO_DEBUG_DISABLE_COLORS	0 */
+
+#define VIDEO_ENCODER_NAME	"Analog Devices AD7177"
+
+#define VIDEO_ENCODER_I2C_RATE	100000	/* Max rate is 100 kHz		*/
+#define VIDEO_ENCODER_CB_Y_CR_Y		/* Use CB Y CR Y format...	*/
+
+#define VIDEO_MODE_YUYV		/* The only mode supported by this encoder */
+#undef	VIDEO_MODE_RGB
+#define VIDEO_MODE_BPP		16
+
+#ifdef	VIDEO_MODE_PAL
+#define VIDEO_ACTIVE_COLS	720
+#define VIDEO_ACTIVE_ROWS	576
+#define VIDEO_VISIBLE_COLS	640
+#define VIDEO_VISIBLE_ROWS	480
+#endif
+
+#ifdef	VIDEO_MODE_NTSC
+#define VIDEO_ACTIVE_COLS	720
+#define VIDEO_ACTIVE_ROWS	525
+#define VIDEO_VISIBLE_COLS	640
+#define VIDEO_VISIBLE_ROWS	400
+#endif
+
+static unsigned char
+    video_encoder_data[] = {
+#ifdef VIDEO_MODE_NTSC
+					0x04, /* Mode Register 0	*/
+#ifdef VIDEO_DEBUG_COLORBARS
+					0xc2,
+#else
+					0x42, /* Mode Register 1	*/
+#endif	/* VIDEO_DEBUG_COLORBARS */
+					0x16, /* Subcarrier Freq 0	*/
+					0x7c, /* Subcarrier Freq 1	*/
+					0xf0, /* Subcarrier Freq 2	*/
+					0x21, /* Subcarrier Freq 3	*/
+					0x00, /* Subcarrier phase	*/
+					0x02, /* Timing Register 0	*/
+					0x00, /* Extended Captioning 0	*/
+					0x00, /* Extended Captioning 1	*/
+					0x00, /* Closed Captioning 0	*/
+					0x00, /* Closed Captioning 1	*/
+					0x00, /* Timing Register 1	*/
+					0x08, /* Mode Register 2	*/
+					0x00, /* Pedestal Register 0	*/
+					0x00, /* Pedestal Register 1	*/
+					0x00, /* Pedestal Register 2	*/
+					0x00, /* Pedestal Register 3	*/
+					0x08, /* Mode Register 3	*/
+
+#endif	/* VIDEO_MODE_NTSC */
+
+#ifdef VIDEO_MODE_PAL
+#ifdef VIDEO_MODE_RGB_OUT
+
+					0x69, /* Mode Register 0	*/
+#ifdef VIDEO_DEBUG_COLORBARS
+					0xc0, /* Mode Register 1 (c0)	*/
+#else
+					0x40, /* Mode Register 1 (c0)	*/
+#endif	/* VIDEO_DEBUG_COLORBARS */
+					0xcb, /* Subcarrier Freq 0	*/
+					0x8a, /* Subcarrier Freq 1	*/
+					0x09, /* Subcarrier Freq 2	*/
+					0x2a, /* Subcarrier Freq 3	*/
+					0x00, /* Subcarrier phase	*/
+					0x02, /* Timing Register 0	*/
+					0x00, /* Extended Captioning 0	*/
+					0x00, /* Extended Captioning 1	*/
+					0x00, /* Closed Captioning 0	*/
+					0x00, /* Closed Captioning 1	*/
+					0x00, /* Timing Register 1	*/
+					0x28, /* Mode Register 2	*/
+					0x00, /* Pedestal Register 0	*/
+					0x00, /* Pedestal Register 1	*/
+					0x00, /* Pedestal Register 2	*/
+					0x00, /* Pedestal Register 3	*/
+					0x08, /* Mode Register 3	*/
+
+#else	/* ! VIDEO_MODE_RGB_OUT */
+
+					0x09, /* Mode Register 0 (was 01) */
+#ifdef VIDEO_DEBUG_COLORBARS
+					0xd8, /*			*/
+#else
+					0x59, /* Mode Register 1 (was 58) */
+#endif	/* VIDEO_DEBUG_COLORBARS */
+					0xcb, /* Subcarrier Freq 0	*/
+					0x8a, /* Subcarrier Freq 1	*/
+					0x09, /* Subcarrier Freq 2	*/
+					0x2a, /* Subcarrier Freq 3	*/
+					0x00, /* Subcarrier phase	*/
+					0x02, /* Timing Register 0 (was a) */
+					0x00, /* Extended Captioning 0	*/
+					0x00, /* Extended Captioning 1	*/
+					0x00, /* Closed Captioning 0	*/
+					0x00, /* Closed Captioning 1	*/
+					0x00, /* Timing Register 1	*/
+#ifdef VIDEO_DEBUG_LOWPOWER
+#ifdef VIDEO_DEBUG_DISABLE_COLORS
+					0x98, /* Mode Register 2	*/
+#else
+					0x88, /* Mode Register 2	*/
+#endif	/* VIDEO_DEBUG_DISABLE_COLORS */
+#else	/* ! VIDEO_DEBUG_LOWPOWER */
+#ifdef VIDEO_DEBUG_DISABLE_COLORS
+					0x18, /* Mode Register 2	*/
+#else
+					0x08, /* Mode Register 2	*/
+#endif	/* VIDEO_DEBUG_DISABLE_COLORS */
+#endif	/* VIDEO_DEBUG_LOWPOWER */
+					0x00, /* Pedestal Register 0	*/
+					0x00, /* Pedestal Register 1	*/
+					0x00, /* Pedestal Register 2	*/
+					0x00, /* Pedestal Register 3	*/
+					0x08  /* Mode Register 3	*/
+#endif	/* VIDEO_MODE_RGB_OUT */
+#endif	/* VIDEO_MODE_PAL */
+    } ;
+
+#endif	/* _VIDEO_AD7177_H_ */
diff --git a/qemu/roms/u-boot/include/video_ad7179.h b/qemu/roms/u-boot/include/video_ad7179.h
new file mode 100644
index 000000000..67c1ec0ce
--- /dev/null
+++ b/qemu/roms/u-boot/include/video_ad7179.h
@@ -0,0 +1,20 @@
+/*
+ * (C) Copyright 2003 Wolfgang Grandegger <wg@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _VIDEO_AD7179_H_
+#define _VIDEO_AD7179_H_
+
+/*
+ * The video encoder data are board specific now!
+ */
+
+#if defined(CONFIG_RRVISION)
+#include "../board/RRvision/video_ad7179.h"
+#else
+#error "Please provide a board-specific video_ad7179.h"
+#endif
+
+#endif /* _VIDEO_AD7179_H_ */
diff --git a/qemu/roms/u-boot/include/video_easylogo.h b/qemu/roms/u-boot/include/video_easylogo.h
new file mode 100644
index 000000000..ce93868da
--- /dev/null
+++ b/qemu/roms/u-boot/include/video_easylogo.h
@@ -0,0 +1,26 @@
+/*
+** video easylogo
+** ==============
+** (C) 2000 by Paolo Scaffardi (arsenio@tin.it)
+** AIRVENT SAM s.p.a - RIMINI(ITALY)
+**
+** This utility is still under construction!
+*/
+
+#ifndef _EASYLOGO_H_
+#define _EASYLOGO_H_
+
+#if 0
+#define ENABLE_ASCII_BANNERS
+#endif
+
+typedef struct {
+	unsigned char	*data;
+	int		width;
+	int		height;
+	int		bpp;
+	int		pixel_size;
+	int		size;
+} fastimage_t ;
+
+#endif	/* _EASYLOGO_H_ */
diff --git a/qemu/roms/u-boot/include/video_fb.h b/qemu/roms/u-boot/include/video_fb.h
new file mode 100644
index 000000000..6cd4e377c
--- /dev/null
+++ b/qemu/roms/u-boot/include/video_fb.h
@@ -0,0 +1,104 @@
+/*
+ * (C) Copyright 1997-2002 ELTEC Elektronik AG
+ * Frank Gottschling <fgottschling@eltec.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * smiLynxEM.h
+ * Silicon Motion graphic interface for sm810/sm710/sm712 accelerator
+ *
+ *
+ *  modification history
+ *  --------------------
+ *  04-18-2002 Rewritten for U-Boot <fgottschling@eltec.de>.
+ */
+
+#ifndef _VIDEO_FB_H_
+#define _VIDEO_FB_H_
+
+#if defined(CONFIG_SYS_CONSOLE_FG_COL) && defined(CONFIG_SYS_CONSOLE_BG_COL)
+#define CONSOLE_BG_COL            CONFIG_SYS_CONSOLE_BG_COL
+#define CONSOLE_FG_COL            CONFIG_SYS_CONSOLE_FG_COL
+#else
+#define CONSOLE_BG_COL            0x00
+#define CONSOLE_FG_COL            0xa0
+#endif
+
+/*
+ * Graphic Data Format (GDF) bits for VIDEO_DATA_FORMAT
+ */
+#define GDF__8BIT_INDEX         0
+#define GDF_15BIT_555RGB        1
+#define GDF_16BIT_565RGB        2
+#define GDF_32BIT_X888RGB       3
+#define GDF_24BIT_888RGB        4
+#define GDF__8BIT_332RGB        5
+
+/******************************************************************************/
+/* Export Graphic Driver Control                                              */
+/******************************************************************************/
+
+typedef struct {
+    unsigned int isaBase;
+    unsigned int pciBase;
+    unsigned int dprBase;
+    unsigned int vprBase;
+    unsigned int cprBase;
+    unsigned int frameAdrs;
+    unsigned int memSize;
+    unsigned int mode;
+    unsigned int gdfIndex;
+    unsigned int gdfBytesPP;
+    unsigned int fg;
+    unsigned int bg;
+    unsigned int plnSizeX;
+    unsigned int plnSizeY;
+    unsigned int winSizeX;
+    unsigned int winSizeY;
+    char modeIdent[80];
+} GraphicDevice;
+
+
+/******************************************************************************/
+/* Export Graphic Functions                                                   */
+/******************************************************************************/
+
+void *video_hw_init (void);       /* returns GraphicDevice struct or NULL */
+
+#ifdef VIDEO_HW_BITBLT
+void video_hw_bitblt (
+    unsigned int bpp,             /* bytes per pixel */
+    unsigned int src_x,           /* source pos x */
+    unsigned int src_y,           /* source pos y */
+    unsigned int dst_x,           /* dest pos x */
+    unsigned int dst_y,           /* dest pos y */
+    unsigned int dim_x,           /* frame width */
+    unsigned int dim_y            /* frame height */
+    );
+#endif
+
+#ifdef VIDEO_HW_RECTFILL
+void video_hw_rectfill (
+    unsigned int bpp,             /* bytes per pixel */
+    unsigned int dst_x,           /* dest pos x */
+    unsigned int dst_y,           /* dest pos y */
+    unsigned int dim_x,           /* frame width */
+    unsigned int dim_y,           /* frame height */
+    unsigned int color            /* fill color */
+     );
+#endif
+
+void video_set_lut (
+    unsigned int index,           /* color number */
+    unsigned char r,              /* red */
+    unsigned char g,              /* green */
+    unsigned char b               /* blue */
+    );
+#ifdef CONFIG_VIDEO_HW_CURSOR
+void video_set_hw_cursor(int x, int y); /* x y in pixel */
+void video_init_hw_cursor(int font_width, int font_height);
+#endif
+
+#endif /*_VIDEO_FB_H_ */
diff --git a/qemu/roms/u-boot/include/video_font.h b/qemu/roms/u-boot/include/video_font.h
new file mode 100644
index 000000000..96b9edb0d
--- /dev/null
+++ b/qemu/roms/u-boot/include/video_font.h
@@ -0,0 +1,17 @@
+/*
+ * (C) Copyright 2000
+ * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _VIDEO_FONT_
+#define _VIDEO_FONT_
+
+#ifdef CONFIG_VIDEO_FONT_4X6
+#include <video_font_4x6.h>
+#else
+#include <video_font_data.h>
+#endif
+
+#endif /* _VIDEO_FONT_ */
diff --git a/qemu/roms/u-boot/include/video_font_4x6.h b/qemu/roms/u-boot/include/video_font_4x6.h
new file mode 100644
index 000000000..6aeed092a
--- /dev/null
+++ b/qemu/roms/u-boot/include/video_font_4x6.h
@@ -0,0 +1,2153 @@
+/* Hand composed "Minuscule" 4x6 font, with binary data generated using
+ * Perl stub.
+ *
+ * Use 'perl -x mini_4x6.c < mini_4x6.c > new_version.c' to regenerate
+ * binary data.
+ *
+ * Created by Kenneth Albanowski.
+ * No rights reserved, released to the public domain.
+ *
+ * Version 1.0
+ */
+
+/*
+
+#!/usr/bin/perl -pn
+
+s{((0x)?[0-9a-fA-F]+)(.*\[([\*\ ]{4})\])}{
+
+	($num,$pat,$bits) = ($1,$3,$4);
+
+	$bits =~ s/([^\s0])|(.)/ defined($1) + 0 /ge;
+
+	$num = ord(pack("B8", $bits));
+	$num |= $num >> 4;
+	$num = sprintf("0x%.2x", $num);
+
+	#print "$num,$pat,$bits\n";
+
+	$num . $pat;
+}ge;
+
+__END__;
+*/
+
+/* Note: binary data consists of one byte for each row of each character top
+   to bottom, character 0 to character 255, six bytes per character. Each
+   byte contains the same four character bits in both nybbles.
+   MSBit to LSBit = left to right.
+ */
+
+#ifndef _VIDEO_FONT_DATA_
+#define _VIDEO_FONT_DATA_
+
+#define VIDEO_FONT_CHARS	256
+#define VIDEO_FONT_WIDTH	4
+#define VIDEO_FONT_HEIGHT	6
+#define VIDEO_FONT_SIZE		(VIDEO_FONT_CHARS * VIDEO_FONT_HEIGHT)
+
+static unsigned char video_fontdata[VIDEO_FONT_SIZE] = {
+
+	/*{*/
+	  	/*   Char 0: ' '  */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 1: ' '  */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 2: ' '  */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 3: ' '  */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 4: ' '  */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 5: ' '  */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 6: ' '  */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 7: ' '  */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 8: ' '  */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 9: ' '  */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 10: '' */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 11: ' ' */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 12: ' ' */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 13: ' ' */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 14: ' ' */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 15: ' ' */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 16: ' ' */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 17: ' ' */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 18: ' ' */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 19: ' ' */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 20: ' ' */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 21: ' ' */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 22: ' ' */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 23: ' ' */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 24: ' ' */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 25: ' ' */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 26: ' ' */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 27: ' ' */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 28: ' ' */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 29: ' ' */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 30: ' ' */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 31: ' ' */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 32: ' ' */
+	0x00,	/*=  [    ]       */
+	0x00,	/*=  [    ]       */
+	0x00,	/*=  [    ]       */
+	0x00,	/*=  [    ]       */
+	0x00,	/*=  [    ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 33: '!' */
+	0x44,	/*=  [ *  ]       */
+	0x44,	/*=  [ *  ]       */
+	0x44,	/*=  [ *  ]       */
+	0x00,	/*=  [    ]       */
+	0x44,	/*=  [ *  ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 34: '"' */
+	0xaa,	/*=  [* * ]       */
+	0xaa,	/*=  [* * ]       */
+	0x00,	/*=  [    ]       */
+	0x00,	/*=  [    ]       */
+	0x00,	/*=  [    ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 35: '#' */
+	0xaa,	/*=  [* * ]       */
+	0xff,	/*=  [****]       */
+	0xff,	/*=  [****]       */
+	0xaa,	/*=  [* * ]       */
+	0x00,	/*=  [    ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 36: '$' */
+	0x44,	/*=  [ *  ]       */
+	0x66,	/*=  [ ** ]       */
+	0xee,	/*=  [*** ]       */
+	0xcc,	/*=  [**  ]       */
+	0x44,	/*=  [ *  ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 37: '%' */
+	0xaa,	/*=  [* * ]       */
+	0x22,	/*=  [  * ]       */
+	0x44,	/*=  [ *  ]       */
+	0x88,	/*=  [*   ]       */
+	0xaa,	/*=  [* * ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 38: '&' */
+	0x66,	/*=  [ ** ]       */
+	0x99,	/*=  [*  *]       */
+	0x66,	/*=  [ ** ]       */
+	0xaa,	/*=  [* * ]       */
+	0xdd,	/*=  [** *]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 39: ''' */
+	0x22,	/*=  [  * ]       */
+	0x44,	/*=  [ *  ]       */
+	0x00,	/*=  [    ]       */
+	0x00,	/*=  [    ]       */
+	0x00,	/*=  [    ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 40: '(' */
+	0x22,	/*=  [  * ]       */
+	0x44,	/*=  [ *  ]       */
+	0x44,	/*=  [ *  ]       */
+	0x44,	/*=  [ *  ]       */
+	0x22,	/*=  [  * ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 41: ')' */
+	0x44,	/*=  [ *  ]       */
+	0x22,	/*=  [  * ]       */
+	0x22,	/*=  [  * ]       */
+	0x22,	/*=  [  * ]       */
+	0x44,	/*=  [ *  ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 42: '*' */
+	0x00,	/*=  [    ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 43: '+' */
+	0x00,	/*=  [    ]       */
+	0x44,	/*=  [ *  ]       */
+	0xee,	/*=  [*** ]       */
+	0x44,	/*=  [ *  ]       */
+	0x00,	/*=  [    ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 44: ',' */
+	0x00,	/*=  [    ]       */
+	0x00,	/*=  [    ]       */
+	0x00,	/*=  [    ]       */
+	0x44,	/*=  [ *  ]       */
+	0x88,	/*=  [*   ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 45: '-' */
+	0x00,	/*=  [    ]       */
+	0x00,	/*=  [    ]       */
+	0xee,	/*=  [*** ]       */
+	0x00,	/*=  [    ]       */
+	0x00,	/*=  [    ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 46: '.' */
+	0x00,	/*=  [    ]       */
+	0x00,	/*=  [    ]       */
+	0x00,	/*=  [    ]       */
+	0x00,	/*=  [    ]       */
+	0x44,	/*=  [ *  ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 47: '/' */
+	0x00,	/*=  [    ]       */
+	0x22,	/*=  [  * ]       */
+	0x44,	/*=  [ *  ]       */
+	0x88,	/*=  [*   ]       */
+	0x00,	/*=  [    ]       */
+	0x00,	/*=  [    ]       */
+	/*}*/
+	/*{*/
+	  	/*   Char 48: '0'   */
+	0x44,	/*=   [ *  ]        */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0x44,	/*=   [ *  ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/
+	  	/*   Char 49: '1'   */
+	0x44,	/*=   [ *  ]        */
+	0xcc,	/*=   [**  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/
+	  	/*   Char 50: '2'   */
+	0xcc,	/*=   [**  ]        */
+	0x22,	/*=   [  * ]        */
+	0x44,	/*=   [ *  ]        */
+	0x88,	/*=   [*   ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/
+	  	/*   Char 51: '3'   */
+	0xee,	/*=   [*** ]        */
+	0x22,	/*=   [  * ]        */
+	0x66,	/*=   [ ** ]        */
+	0x22,	/*=   [  * ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 52: '4'   */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0xee,	/*=   [*** ]        */
+	0x22,	/*=   [  * ]        */
+	0x22,	/*=   [  * ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 53: '5'   */
+	0xee,	/*=   [*** ]        */
+	0x88,	/*=   [*   ]        */
+	0xee,	/*=   [*** ]        */
+	0x22,	/*=   [  * ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 54: '6'   */
+	0xee,	/*=   [*** ]        */
+	0x88,	/*=   [*   ]        */
+	0xee,	/*=   [*** ]        */
+	0xaa,	/*=   [* * ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 55: '7'   */
+	0xee,	/*=   [*** ]        */
+	0x22,	/*=   [  * ]        */
+	0x22,	/*=   [  * ]        */
+	0x22,	/*=   [  * ]        */
+	0x22,	/*=   [  * ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 56: '8'   */
+	0xee,	/*=   [*** ]        */
+	0xaa,	/*=   [* * ]        */
+	0xee,	/*=   [*** ]        */
+	0xaa,	/*=   [* * ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 57: '9'   */
+	0xee,	/*=   [*** ]        */
+	0xaa,	/*=   [* * ]        */
+	0xee,	/*=   [*** ]        */
+	0x22,	/*=   [  * ]        */
+	0x22,	/*=   [  * ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 58: ':'   */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x44,	/*=   [ *  ]        */
+	0x00,	/*=   [    ]        */
+	0x44,	/*=   [ *  ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 59: ';'   */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x44,	/*=   [ *  ]        */
+	0x00,	/*=   [    ]        */
+	0x44,	/*=   [ *  ]        */
+	0x88,	/*=   [*   ]        */
+	/*}*/
+	/*{*/ 	/*   Char 60: '<'   */
+	0x22,	/*=   [  * ]        */
+	0x44,	/*=   [ *  ]        */
+	0x88,	/*=   [*   ]        */
+	0x44,	/*=   [ *  ]        */
+	0x22,	/*=   [  * ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 61: '='   */
+	0x00,	/*=   [    ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 62: '>'   */
+	0x88,	/*=   [*   ]        */
+	0x44,	/*=   [ *  ]        */
+	0x22,	/*=   [  * ]        */
+	0x44,	/*=   [ *  ]        */
+	0x88,	/*=   [*   ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 63: '?'   */
+	0xee,	/*=   [*** ]        */
+	0x22,	/*=   [  * ]        */
+	0x66,	/*=   [ ** ]        */
+	0x00,	/*=   [    ]        */
+	0x44,	/*=   [ *  ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 64: '@'   */
+	0x44,	/*=   [ *  ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x88,	/*=   [*   ]        */
+	0x44,	/*=   [ *  ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 65: 'A'   */
+	0x44,	/*=   [ *  ]        */
+	0xaa,	/*=   [* * ]        */
+	0xee,	/*=   [*** ]        */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 66: 'B'   */
+	0xcc,	/*=   [**  ]        */
+	0xaa,	/*=   [* * ]        */
+	0xcc,	/*=   [**  ]        */
+	0xaa,	/*=   [* * ]        */
+	0xcc,	/*=   [**  ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 67: 'C'   */
+	0x66,	/*=   [ ** ]        */
+	0x88,	/*=   [*   ]        */
+	0x88,	/*=   [*   ]        */
+	0x88,	/*=   [*   ]        */
+	0x66,	/*=   [ ** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 68: 'D'   */
+	0xcc,	/*=   [**  ]        */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0xcc,	/*=   [**  ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 69: 'E'   */
+	0xee,	/*=   [*** ]        */
+	0x88,	/*=   [*   ]        */
+	0xee,	/*=   [*** ]        */
+	0x88,	/*=   [*   ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 70: 'F'   */
+	0xee,	/*=   [*** ]        */
+	0x88,	/*=   [*   ]        */
+	0xee,	/*=   [*** ]        */
+	0x88,	/*=   [*   ]        */
+	0x88,	/*=   [*   ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 71: 'G'   */
+	0x66,	/*=   [ ** ]        */
+	0x88,	/*=   [*   ]        */
+	0xee,	/*=   [*** ]        */
+	0xaa,	/*=   [* * ]        */
+	0x66,	/*=   [ ** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 72: 'H'   */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0xee,	/*=   [*** ]        */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 73: 'I'   */
+	0xee,	/*=   [*** ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 74: 'J'   */
+	0x22,	/*=   [  * ]        */
+	0x22,	/*=   [  * ]        */
+	0x22,	/*=   [  * ]        */
+	0xaa,	/*=   [* * ]        */
+	0x44,	/*=   [ *  ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 75: 'K'   */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0xcc,	/*=   [**  ]        */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 76: 'L'   */
+	0x88,	/*=   [*   ]        */
+	0x88,	/*=   [*   ]        */
+	0x88,	/*=   [*   ]        */
+	0x88,	/*=   [*   ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 77: 'M'   */
+	0xaa,	/*=   [* * ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 78: 'N'   */
+	0xaa,	/*=   [* * ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xaa,	/*=   [* * ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 79: 'O'   */
+	0x44,	/*=   [ *  ]        */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0x44,	/*=   [ *  ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 80: 'P'   */
+	0xcc,	/*=   [**  ]        */
+	0xaa,	/*=   [* * ]        */
+	0xcc,	/*=   [**  ]        */
+	0x88,	/*=   [*   ]        */
+	0x88,	/*=   [*   ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 81: 'Q'   */
+	0x44,	/*=   [ *  ]        */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0xee,	/*=   [*** ]        */
+	0x66,	/*=   [ ** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 82: 'R'   */
+	0xcc,	/*=   [**  ]        */
+	0xaa,	/*=   [* * ]        */
+	0xee,	/*=   [*** ]        */
+	0xcc,	/*=   [**  ]        */
+	0xaa,	/*=   [* * ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 83: 'S'   */
+	0x66,	/*=   [ ** ]        */
+	0x88,	/*=   [*   ]        */
+	0x44,	/*=   [ *  ]        */
+	0x22,	/*=   [  * ]        */
+	0xcc,	/*=   [**  ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 84: 'T'   */
+	0xee,	/*=   [*** ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 85: 'U'   */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0x66,	/*=   [ ** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 86: 'V'   */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 87: 'W'   */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xaa,	/*=   [* * ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 88: 'X'   */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0x44,	/*=   [ *  ]        */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 89: 'Y'   */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 90: 'Z'   */
+	0xee,	/*=   [*** ]        */
+	0x22,	/*=   [  * ]        */
+	0x44,	/*=   [ *  ]        */
+	0x88,	/*=   [*   ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 91: '['   */
+	0x66,	/*=   [ ** ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x66,	/*=   [ ** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 92: '\'   */
+	0x00,	/*=   [    ]        */
+	0x88,	/*=   [*   ]        */
+	0x44,	/*=   [ *  ]        */
+	0x22,	/*=   [  * ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 93: ']'   */
+	0x66,	/*=   [ ** ]        */
+	0x22,	/*=   [  * ]        */
+	0x22,	/*=   [  * ]        */
+	0x22,	/*=   [  * ]        */
+	0x66,	/*=   [ ** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 94: '^'   */
+	0x44,	/*=   [ *  ]        */
+	0xaa,	/*=   [* * ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 95: '_'   */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0xff,	/*=   [****]        */
+	/*}*/
+	/*{*/ 	/*   Char 96: '`'   */
+	0x88,	/*=   [*   ]        */
+	0x44,	/*=   [ *  ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 97: 'a'   */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x66,	/*=   [ ** ]        */
+	0xaa,	/*=   [* * ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 98: 'b'   */
+	0x88,	/*=   [*   ]        */
+	0x88,	/*=   [*   ]        */
+	0xcc,	/*=   [**  ]        */
+	0xaa,	/*=   [* * ]        */
+	0xcc,	/*=   [**  ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 99: 'c'   */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x66,	/*=   [ ** ]        */
+	0x88,	/*=   [*   ]        */
+	0x66,	/*=   [ ** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 100: 'd'   */
+	0x22,	/*=   [  * ]        */
+	0x22,	/*=   [  * ]        */
+	0x66,	/*=   [ ** ]        */
+	0xaa,	/*=   [* * ]        */
+	0x66,	/*=   [ ** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 101: 'e'   */
+	0x00,	/*=   [    ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x88,	/*=   [*   ]        */
+	0x66,	/*=   [ ** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 102: 'f'   */
+	0x22,	/*=   [  * ]        */
+	0x44,	/*=   [ *  ]        */
+	0xee,	/*=   [*** ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 103: 'g'   */
+	0x00,	/*=   [    ]        */
+	0x66,	/*=   [ ** ]        */
+	0xaa,	/*=   [* * ]        */
+	0x66,	/*=   [ ** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 104: 'h'   */
+	0x88,	/*=   [*   ]        */
+	0x88,	/*=   [*   ]        */
+	0xcc,	/*=   [**  ]        */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 105: 'i'   */
+	0x44,	/*=   [ *  ]        */
+	0x00,	/*=   [    ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 106: 'j'   */
+	0x44,	/*=   [ *  ]        */
+	0x00,	/*=   [    ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x88,	/*=   [*   ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 107: 'k'   */
+	0x00,	/*=   [    ]        */
+	0x88,	/*=   [*   ]        */
+	0xaa,	/*=   [* * ]        */
+	0xcc,	/*=   [**  ]        */
+	0xaa,	/*=   [* * ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 108: 'l'   */
+	0x00,	/*=   [    ]        */
+	0xcc,	/*=   [**  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 109: 'm'   */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xaa,	/*=   [* * ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 110: 'n'   */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0xcc,	/*=   [**  ]        */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 111: 'o'   */
+	0x00,	/*=   [    ]        */
+	0x44,	/*=   [ *  ]        */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0x44,	/*=   [ *  ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 112: 'p'   */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0xcc,	/*=   [**  ]        */
+	0xaa,	/*=   [* * ]        */
+	0xcc,	/*=   [**  ]        */
+	0x88,	/*=   [*   ]        */
+	/*}*/
+	/*{*/ 	/*   Char 113: 'q'   */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x66,	/*=   [ ** ]        */
+	0xaa,	/*=   [* * ]        */
+	0x66,	/*=   [ ** ]        */
+	0x22,	/*=   [  * ]        */
+	/*}*/
+	/*{*/ 	/*   Char 114: 'r'   */
+	0x00,	/*=   [    ]        */
+	0xcc,	/*=   [**  ]        */
+	0xaa,	/*=   [* * ]        */
+	0x88,	/*=   [*   ]        */
+	0x88,	/*=   [*   ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 115: 's'   */
+	0x00,	/*=   [    ]        */
+	0x66,	/*=   [ ** ]        */
+	0xcc,	/*=   [**  ]        */
+	0x22,	/*=   [  * ]        */
+	0xcc,	/*=   [**  ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 116: 't'   */
+	0x00,	/*=   [    ]        */
+	0x44,	/*=   [ *  ]        */
+	0xee,	/*=   [*** ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 117: 'u'   */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0x66,	/*=   [ ** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 118: 'v'   */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0xaa,	/*=   [* * ]        */
+	0xee,	/*=   [*** ]        */
+	0x44,	/*=   [ *  ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 119: 'w'   */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0xaa,	/*=   [* * ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 120: 'x'   */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0xaa,	/*=   [* * ]        */
+	0x44,	/*=   [ *  ]        */
+	0xaa,	/*=   [* * ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 121: 'y'   */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0xaa,	/*=   [* * ]        */
+	0xee,	/*=   [*** ]        */
+	0x22,	/*=   [  * ]        */
+	0xcc,	/*=   [**  ]        */
+	/*}*/
+	/*{*/ 	/*   Char 122: 'z' */
+	0x00,	/*=   [    ]        */
+	0xee,	/*=   [*** ]        */
+	0x66,	/*=   [ ** ]        */
+	0xcc,	/*=   [**  ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 123: '{' */
+	0x22,	/*=   [  * ]        */
+	0x44,	/*=   [ *  ]        */
+	0xcc,	/*=   [**  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x22,	/*=   [  * ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 124: '|' */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 125: '}' */
+	0x88,	/*=   [*   ]        */
+	0x44,	/*=   [ *  ]        */
+	0x66,	/*=   [ ** ]        */
+	0x44,	/*=   [ *  ]        */
+	0x88,	/*=   [*   ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 126: '~' */
+	0x55,	/*=   [ * *]        */
+	0xaa,	/*=   [* * ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 127: '' */
+	0x44,	/*=   [ *  ]        */
+	0xaa,	/*=   [* * ]        */
+	0xaa,	/*=   [* * ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 128:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 129:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 130:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 131:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 132:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 133:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 134:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 135:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 136:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 137:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 138:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 139:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 140:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 141:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 142:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 143:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 144:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 145:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 146:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 147:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 148:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 149:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 150:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 151:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 152:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 153:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 154:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 155:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 156:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 157:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 158:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 159:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 160:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 161:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 162:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 163:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 164:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 165:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 166:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 167:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 168:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 169:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 170:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 171:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 172:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 173:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 174:  */
+	0x00,	/*=   [    ]        */
+	0x66,	/*=   [ ** ]        */
+	0xcc,	/*=   [**  ]        */
+	0x66,	/*=   [ ** ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 175:  */
+	0x00,	/*=   [    ]        */
+	0xcc,	/*=   [**  ]        */
+	0x66,	/*=   [ ** ]        */
+	0xcc,	/*=   [**  ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 176:  */
+	0x88,	/*=   [*   ]        */
+	0x22,	/*=   [  * ]        */
+	0x88,	/*=   [*   ]        */
+	0x22,	/*=   [  * ]        */
+	0x88,	/*=   [*   ]        */
+	0x22,	/*=   [  * ]        */
+	/*}*/
+	/*{*/ 	/*   Char 177:  */
+	0xaa,	/*=   [* * ]        */
+	0x55,	/*=   [ * *]        */
+	0xaa,	/*=   [* * ]        */
+	0x55,	/*=   [ * *]        */
+	0xaa,	/*=   [* * ]        */
+	0x55,	/*=   [ * *]        */
+	/*}*/
+	/*{*/ 	/*   Char 178:  */
+	0xdd,	/*=   [** *]        */
+	0xbb,	/*=   [* **]        */
+	0xdd,	/*=   [** *]        */
+	0xbb,	/*=   [* **]        */
+	0xdd,	/*=   [** *]        */
+	0xbb,	/*=   [* **]        */
+	/*}*/
+	/*{*/ 	/*   Char 179:  */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	/*}*/
+	/*{*/ 	/*   Char 180:  */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0xcc,	/*=   [**  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	/*}*/
+	/*{*/ 	/*   Char 181:  */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0xcc,	/*=   [**  ]        */
+	0xcc,	/*=   [**  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	/*}*/
+	/*{*/ 	/*   Char 182:  */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	0xee,	/*=   [*** ]        */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	/*}*/
+	/*{*/ 	/*   Char 183:  */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0xee,	/*=   [*** ]        */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	/*}*/
+	/*{*/ 	/*   Char 184:  */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0xcc,	/*=   [**  ]        */
+	0xcc,	/*=   [**  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	/*}*/
+	/*{*/ 	/*   Char 185:  */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	/*}*/
+	/*{*/ 	/*   Char 186:  */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	/*}*/
+	/*{*/ 	/*   Char 187:  */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	/*}*/
+	/*{*/ 	/*   Char 188:  */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 189:  */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 190:  */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0xcc,	/*=   [**  ]        */
+	0xcc,	/*=   [**  ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 191:  */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0xcc,	/*=   [**  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	/*}*/
+	/*{*/ 	/*   Char 192:  */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x77,	/*=   [ ***]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 193:  */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0xff,	/*=   [****]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 194:  */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0xff,	/*=   [****]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	/*}*/
+	/*{*/ 	/*   Char 195:  */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x77,	/*=   [ ***]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	/*}*/
+	/*{*/ 	/*   Char 196:  */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0xff,	/*=   [****]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 197:  */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0xff,	/*=   [****]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	/*}*/
+	/*{*/ 	/*   Char 198:  */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x77,	/*=   [ ***]        */
+	0x77,	/*=   [ ***]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	/*}*/
+	/*{*/ 	/*   Char 199:  */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	0x77,	/*=   [ ***]        */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	/*}*/
+	/*{*/ 	/*   Char 200:  */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	0x77,	/*=   [ ***]        */
+	0x77,	/*=   [ ***]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 201:  */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x77,	/*=   [ ***]        */
+	0x77,	/*=   [ ***]        */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	/*}*/
+	/*{*/ 	/*   Char 202:  */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	0xff,	/*=   [****]        */
+	0xff,	/*=   [****]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 203:  */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0xff,	/*=   [****]        */
+	0xff,	/*=   [****]        */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	/*}*/
+	/*{*/ 	/*   Char 204:  */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	0x77,	/*=   [ ***]        */
+	0x77,	/*=   [ ***]        */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	/*}*/
+	/*{*/ 	/*   Char 205:  */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0xff,	/*=   [****]        */
+	0xff,	/*=   [****]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 206:  */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	0xff,	/*=   [****]        */
+	0xff,	/*=   [****]        */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	/*}*/
+	/*{*/ 	/*   Char 207:  */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0xff,	/*=   [****]        */
+	0xff,	/*=   [****]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 208:  */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	0xff,	/*=   [****]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 209:  */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0xff,	/*=   [****]        */
+	0xff,	/*=   [****]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	/*}*/
+	/*{*/ 	/*   Char 210:  */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0xff,	/*=   [****]        */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	/*}*/
+	/*{*/ 	/*   Char 211:  */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	0x77,	/*=   [ ***]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 212:  */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x77,	/*=   [ ***]        */
+	0x77,	/*=   [ ***]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 213:  */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x77,	/*=   [ ***]        */
+	0x77,	/*=   [ ***]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	/*}*/
+	/*{*/ 	/*   Char 214:  */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x77,	/*=   [ ***]        */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	/*}*/
+	/*{*/ 	/*   Char 215:  */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	0xff,	/*=   [****]        */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	/*}*/
+	/*{*/ 	/*   Char 216:  */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0xff,	/*=   [****]        */
+	0xff,	/*=   [****]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	/*}*/
+	/*{*/ 	/*   Char 217:  */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0xcc,	/*=   [**  ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 218:  */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x77,	/*=   [ ***]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	0x44,	/*=   [ *  ]        */
+	/*}*/
+	/*{*/ 	/*   Char 219:  */
+	0xff,	/*=   [****]        */
+	0xff,	/*=   [****]        */
+	0xff,	/*=   [****]        */
+	0xff,	/*=   [****]        */
+	0xff,	/*=   [****]        */
+	0xff,	/*=   [****]        */
+	/*}*/
+	/*{*/ 	/*   Char 220:  */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0xff,	/*=   [****]        */
+	0xff,	/*=   [****]        */
+	0xff,	/*=   [****]        */
+	/*}*/
+	/*{*/ 	/*   Char 221:  */
+	0xcc,	/*=   [**  ]        */
+	0xcc,	/*=   [**  ]        */
+	0xcc,	/*=   [**  ]        */
+	0xcc,	/*=   [**  ]        */
+	0xcc,	/*=   [**  ]        */
+	0xcc,	/*=   [**  ]        */
+	/*}*/
+	/*{*/ 	/*   Char 222:  */
+	0x33,	/*=   [  **]        */
+	0x33,	/*=   [  **]        */
+	0x33,	/*=   [  **]        */
+	0x33,	/*=   [  **]        */
+	0x33,	/*=   [  **]        */
+	0x33,	/*=   [  **]        */
+	/*}*/
+	/*{*/ 	/*   Char 223:  */
+	0xff,	/*=   [****]        */
+	0xff,	/*=   [****]        */
+	0xff,	/*=   [****]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 224:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 225:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 226:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 227:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 228:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 229:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 230:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 231:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 232:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 233:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 234:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 235:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 236:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 237:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 238:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 239:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 240:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 241:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 242:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 243:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 244:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 245:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 246:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 247:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 248:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 249:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 250:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 251:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 252:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 253:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 254:  */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	0x66,	/*=   [ ** ]        */
+	0x66,	/*=   [ ** ]        */
+	0x00,	/*=   [    ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+	/*{*/ 	/*   Char 255:  */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0xee,	/*=   [*** ]        */
+	0x00,	/*=   [    ]        */
+	/*}*/
+};
+
+#endif
diff --git a/qemu/roms/u-boot/include/video_font_data.h b/qemu/roms/u-boot/include/video_font_data.h
new file mode 100644
index 000000000..346a162f5
--- /dev/null
+++ b/qemu/roms/u-boot/include/video_font_data.h
@@ -0,0 +1,4628 @@
+/*
+ * (C) Copyright 2000
+ * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _VIDEO_FONT_DATA_
+#define _VIDEO_FONT_DATA_
+
+#define VIDEO_FONT_CHARS	256
+#define VIDEO_FONT_WIDTH	8
+#define VIDEO_FONT_HEIGHT	16
+#define VIDEO_FONT_SIZE		(VIDEO_FONT_CHARS * VIDEO_FONT_HEIGHT)
+
+static unsigned char __maybe_unused video_fontdata[VIDEO_FONT_SIZE] = {
+
+	/* 0 0x00 '^@' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 1 0x01 '^A' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7e, /* 01111110 */
+	0x81, /* 10000001 */
+	0xa5, /* 10100101 */
+	0x81, /* 10000001 */
+	0x81, /* 10000001 */
+	0xbd, /* 10111101 */
+	0x99, /* 10011001 */
+	0x81, /* 10000001 */
+	0x81, /* 10000001 */
+	0x7e, /* 01111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 2 0x02 '^B' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7e, /* 01111110 */
+	0xff, /* 11111111 */
+	0xdb, /* 11011011 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xc3, /* 11000011 */
+	0xe7, /* 11100111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0x7e, /* 01111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 3 0x03 '^C' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x6c, /* 01101100 */
+	0xfe, /* 11111110 */
+	0xfe, /* 11111110 */
+	0xfe, /* 11111110 */
+	0xfe, /* 11111110 */
+	0x7c, /* 01111100 */
+	0x38, /* 00111000 */
+	0x10, /* 00010000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 4 0x04 '^D' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x10, /* 00010000 */
+	0x38, /* 00111000 */
+	0x7c, /* 01111100 */
+	0xfe, /* 11111110 */
+	0x7c, /* 01111100 */
+	0x38, /* 00111000 */
+	0x10, /* 00010000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 5 0x05 '^E' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x3c, /* 00111100 */
+	0xe7, /* 11100111 */
+	0xe7, /* 11100111 */
+	0xe7, /* 11100111 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 6 0x06 '^F' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x7e, /* 01111110 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0x7e, /* 01111110 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 7 0x07 '^G' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x3c, /* 00111100 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 8 0x08 '^H' */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xe7, /* 11100111 */
+	0xc3, /* 11000011 */
+	0xc3, /* 11000011 */
+	0xe7, /* 11100111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+
+	/* 9 0x09 '^I' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x3c, /* 00111100 */
+	0x66, /* 01100110 */
+	0x42, /* 01000010 */
+	0x42, /* 01000010 */
+	0x66, /* 01100110 */
+	0x3c, /* 00111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 10 0x0a '^J' */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xc3, /* 11000011 */
+	0x99, /* 10011001 */
+	0xbd, /* 10111101 */
+	0xbd, /* 10111101 */
+	0x99, /* 10011001 */
+	0xc3, /* 11000011 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+
+	/* 11 0x0b '^K' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x1e, /* 00011110 */
+	0x0e, /* 00001110 */
+	0x1a, /* 00011010 */
+	0x32, /* 00110010 */
+	0x78, /* 01111000 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0x78, /* 01111000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 12 0x0c '^L' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x3c, /* 00111100 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x3c, /* 00111100 */
+	0x18, /* 00011000 */
+	0x7e, /* 01111110 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 13 0x0d '^M' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x3f, /* 00111111 */
+	0x33, /* 00110011 */
+	0x3f, /* 00111111 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x70, /* 01110000 */
+	0xf0, /* 11110000 */
+	0xe0, /* 11100000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 14 0x0e '^N' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7f, /* 01111111 */
+	0x63, /* 01100011 */
+	0x7f, /* 01111111 */
+	0x63, /* 01100011 */
+	0x63, /* 01100011 */
+	0x63, /* 01100011 */
+	0x63, /* 01100011 */
+	0x67, /* 01100111 */
+	0xe7, /* 11100111 */
+	0xe6, /* 11100110 */
+	0xc0, /* 11000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 15 0x0f '^O' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0xdb, /* 11011011 */
+	0x3c, /* 00111100 */
+	0xe7, /* 11100111 */
+	0x3c, /* 00111100 */
+	0xdb, /* 11011011 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 16 0x10 '^P' */
+	0x00, /* 00000000 */
+	0x80, /* 10000000 */
+	0xc0, /* 11000000 */
+	0xe0, /* 11100000 */
+	0xf0, /* 11110000 */
+	0xf8, /* 11111000 */
+	0xfe, /* 11111110 */
+	0xf8, /* 11111000 */
+	0xf0, /* 11110000 */
+	0xe0, /* 11100000 */
+	0xc0, /* 11000000 */
+	0x80, /* 10000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 17 0x11 '^Q' */
+	0x00, /* 00000000 */
+	0x02, /* 00000010 */
+	0x06, /* 00000110 */
+	0x0e, /* 00001110 */
+	0x1e, /* 00011110 */
+	0x3e, /* 00111110 */
+	0xfe, /* 11111110 */
+	0x3e, /* 00111110 */
+	0x1e, /* 00011110 */
+	0x0e, /* 00001110 */
+	0x06, /* 00000110 */
+	0x02, /* 00000010 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 18 0x12 '^R' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x7e, /* 01111110 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x7e, /* 01111110 */
+	0x3c, /* 00111100 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 19 0x13 '^S' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x00, /* 00000000 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 20 0x14 '^T' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7f, /* 01111111 */
+	0xdb, /* 11011011 */
+	0xdb, /* 11011011 */
+	0xdb, /* 11011011 */
+	0x7b, /* 01111011 */
+	0x1b, /* 00011011 */
+	0x1b, /* 00011011 */
+	0x1b, /* 00011011 */
+	0x1b, /* 00011011 */
+	0x1b, /* 00011011 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 21 0x15 '^U' */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0x60, /* 01100000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x6c, /* 01101100 */
+	0x38, /* 00111000 */
+	0x0c, /* 00001100 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 22 0x16 '^V' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0xfe, /* 11111110 */
+	0xfe, /* 11111110 */
+	0xfe, /* 11111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 23 0x17 '^W' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x7e, /* 01111110 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x7e, /* 01111110 */
+	0x3c, /* 00111100 */
+	0x18, /* 00011000 */
+	0x7e, /* 01111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 24 0x18 '^X' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x7e, /* 01111110 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 25 0x19 '^Y' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x7e, /* 01111110 */
+	0x3c, /* 00111100 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 26 0x1a '^Z' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x0c, /* 00001100 */
+	0xfe, /* 11111110 */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 27 0x1b '^[' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x30, /* 00110000 */
+	0x60, /* 01100000 */
+	0xfe, /* 11111110 */
+	0x60, /* 01100000 */
+	0x30, /* 00110000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 28 0x1c '^\' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xfe, /* 11111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 29 0x1d '^]' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x28, /* 00101000 */
+	0x6c, /* 01101100 */
+	0xfe, /* 11111110 */
+	0x6c, /* 01101100 */
+	0x28, /* 00101000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 30 0x1e '^^' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x10, /* 00010000 */
+	0x38, /* 00111000 */
+	0x38, /* 00111000 */
+	0x7c, /* 01111100 */
+	0x7c, /* 01111100 */
+	0xfe, /* 11111110 */
+	0xfe, /* 11111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 31 0x1f '^_' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0xfe, /* 11111110 */
+	0x7c, /* 01111100 */
+	0x7c, /* 01111100 */
+	0x38, /* 00111000 */
+	0x38, /* 00111000 */
+	0x10, /* 00010000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 32 0x20 ' ' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 33 0x21 '!' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x3c, /* 00111100 */
+	0x3c, /* 00111100 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 34 0x22 '"' */
+	0x00, /* 00000000 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x24, /* 00100100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 35 0x23 '#' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x6c, /* 01101100 */
+	0x6c, /* 01101100 */
+	0xfe, /* 11111110 */
+	0x6c, /* 01101100 */
+	0x6c, /* 01101100 */
+	0x6c, /* 01101100 */
+	0xfe, /* 11111110 */
+	0x6c, /* 01101100 */
+	0x6c, /* 01101100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 36 0x24 '$' */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc2, /* 11000010 */
+	0xc0, /* 11000000 */
+	0x7c, /* 01111100 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0x86, /* 10000110 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 37 0x25 '%' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xc2, /* 11000010 */
+	0xc6, /* 11000110 */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x60, /* 01100000 */
+	0xc6, /* 11000110 */
+	0x86, /* 10000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 38 0x26 '&' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0x6c, /* 01101100 */
+	0x38, /* 00111000 */
+	0x76, /* 01110110 */
+	0xdc, /* 11011100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0x76, /* 01110110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 39 0x27 ''' */
+	0x00, /* 00000000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x60, /* 01100000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 40 0x28 '(' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x18, /* 00011000 */
+	0x0c, /* 00001100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 41 0x29 ')' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x30, /* 00110000 */
+	0x18, /* 00011000 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 42 0x2a '*' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x66, /* 01100110 */
+	0x3c, /* 00111100 */
+	0xff, /* 11111111 */
+	0x3c, /* 00111100 */
+	0x66, /* 01100110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 43 0x2b '+' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x7e, /* 01111110 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 44 0x2c ',' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 45 0x2d '-' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 46 0x2e '.' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 47 0x2f '/' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x02, /* 00000010 */
+	0x06, /* 00000110 */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x60, /* 01100000 */
+	0xc0, /* 11000000 */
+	0x80, /* 10000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 48 0x30 '0' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xd6, /* 11010110 */
+	0xd6, /* 11010110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x6c, /* 01101100 */
+	0x38, /* 00111000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 49 0x31 '1' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x38, /* 00111000 */
+	0x78, /* 01111000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x7e, /* 01111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 50 0x32 '2' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0x06, /* 00000110 */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x60, /* 01100000 */
+	0xc0, /* 11000000 */
+	0xc6, /* 11000110 */
+	0xfe, /* 11111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 51 0x33 '3' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0x3c, /* 00111100 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 52 0x34 '4' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x0c, /* 00001100 */
+	0x1c, /* 00011100 */
+	0x3c, /* 00111100 */
+	0x6c, /* 01101100 */
+	0xcc, /* 11001100 */
+	0xfe, /* 11111110 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x1e, /* 00011110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 53 0x35 '5' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xfc, /* 11111100 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 54 0x36 '6' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x38, /* 00111000 */
+	0x60, /* 01100000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xfc, /* 11111100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 55 0x37 '7' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0xc6, /* 11000110 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 56 0x38 '8' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 57 0x39 '9' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x7e, /* 01111110 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0x0c, /* 00001100 */
+	0x78, /* 01111000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 58 0x3a ':' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 59 0x3b ';' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 60 0x3c '<' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x06, /* 00000110 */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x60, /* 01100000 */
+	0x30, /* 00110000 */
+	0x18, /* 00011000 */
+	0x0c, /* 00001100 */
+	0x06, /* 00000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 61 0x3d '=' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7e, /* 01111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7e, /* 01111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 62 0x3e '>' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x60, /* 01100000 */
+	0x30, /* 00110000 */
+	0x18, /* 00011000 */
+	0x0c, /* 00001100 */
+	0x06, /* 00000110 */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x60, /* 01100000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 63 0x3f '?' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 64 0x40 '@' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xde, /* 11011110 */
+	0xde, /* 11011110 */
+	0xde, /* 11011110 */
+	0xdc, /* 11011100 */
+	0xc0, /* 11000000 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 65 0x41 'A' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x10, /* 00010000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xfe, /* 11111110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 66 0x42 'B' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfc, /* 11111100 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x7c, /* 01111100 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0xfc, /* 11111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 67 0x43 'C' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x3c, /* 00111100 */
+	0x66, /* 01100110 */
+	0xc2, /* 11000010 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc2, /* 11000010 */
+	0x66, /* 01100110 */
+	0x3c, /* 00111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 68 0x44 'D' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xf8, /* 11111000 */
+	0x6c, /* 01101100 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x6c, /* 01101100 */
+	0xf8, /* 11111000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 69 0x45 'E' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0x66, /* 01100110 */
+	0x62, /* 01100010 */
+	0x68, /* 01101000 */
+	0x78, /* 01111000 */
+	0x68, /* 01101000 */
+	0x60, /* 01100000 */
+	0x62, /* 01100010 */
+	0x66, /* 01100110 */
+	0xfe, /* 11111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 70 0x46 'F' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0x66, /* 01100110 */
+	0x62, /* 01100010 */
+	0x68, /* 01101000 */
+	0x78, /* 01111000 */
+	0x68, /* 01101000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0xf0, /* 11110000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 71 0x47 'G' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x3c, /* 00111100 */
+	0x66, /* 01100110 */
+	0xc2, /* 11000010 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xde, /* 11011110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x66, /* 01100110 */
+	0x3a, /* 00111010 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 72 0x48 'H' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xfe, /* 11111110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 73 0x49 'I' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x3c, /* 00111100 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 74 0x4a 'J' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x1e, /* 00011110 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0x78, /* 01111000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 75 0x4b 'K' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xe6, /* 11100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x6c, /* 01101100 */
+	0x78, /* 01111000 */
+	0x78, /* 01111000 */
+	0x6c, /* 01101100 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0xe6, /* 11100110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 76 0x4c 'L' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xf0, /* 11110000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0x62, /* 01100010 */
+	0x66, /* 01100110 */
+	0xfe, /* 11111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 77 0x4d 'M' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0xee, /* 11101110 */
+	0xfe, /* 11111110 */
+	0xfe, /* 11111110 */
+	0xd6, /* 11010110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 78 0x4e 'N' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0xe6, /* 11100110 */
+	0xf6, /* 11110110 */
+	0xfe, /* 11111110 */
+	0xde, /* 11011110 */
+	0xce, /* 11001110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 79 0x4f 'O' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 80 0x50 'P' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfc, /* 11111100 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x7c, /* 01111100 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0xf0, /* 11110000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 81 0x51 'Q' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xd6, /* 11010110 */
+	0xde, /* 11011110 */
+	0x7c, /* 01111100 */
+	0x0c, /* 00001100 */
+	0x0e, /* 00001110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 82 0x52 'R' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfc, /* 11111100 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x7c, /* 01111100 */
+	0x6c, /* 01101100 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0xe6, /* 11100110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 83 0x53 'S' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x60, /* 01100000 */
+	0x38, /* 00111000 */
+	0x0c, /* 00001100 */
+	0x06, /* 00000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 84 0x54 'T' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7e, /* 01111110 */
+	0x7e, /* 01111110 */
+	0x5a, /* 01011010 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 85 0x55 'U' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 86 0x56 'V' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x6c, /* 01101100 */
+	0x38, /* 00111000 */
+	0x10, /* 00010000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 87 0x57 'W' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xd6, /* 11010110 */
+	0xd6, /* 11010110 */
+	0xd6, /* 11010110 */
+	0xfe, /* 11111110 */
+	0xee, /* 11101110 */
+	0x6c, /* 01101100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 88 0x58 'X' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x6c, /* 01101100 */
+	0x7c, /* 01111100 */
+	0x38, /* 00111000 */
+	0x38, /* 00111000 */
+	0x7c, /* 01111100 */
+	0x6c, /* 01101100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 89 0x59 'Y' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x3c, /* 00111100 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 90 0x5a 'Z' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0xc6, /* 11000110 */
+	0x86, /* 10000110 */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x60, /* 01100000 */
+	0xc2, /* 11000010 */
+	0xc6, /* 11000110 */
+	0xfe, /* 11111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 91 0x5b '[' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x3c, /* 00111100 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x3c, /* 00111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 92 0x5c '\' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x80, /* 10000000 */
+	0xc0, /* 11000000 */
+	0xe0, /* 11100000 */
+	0x70, /* 01110000 */
+	0x38, /* 00111000 */
+	0x1c, /* 00011100 */
+	0x0e, /* 00001110 */
+	0x06, /* 00000110 */
+	0x02, /* 00000010 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 93 0x5d ']' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x3c, /* 00111100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x3c, /* 00111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 94 0x5e '^' */
+	0x10, /* 00010000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 95 0x5f '_' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xff, /* 11111111 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 96 0x60 '`' */
+	0x00, /* 00000000 */
+	0x30, /* 00110000 */
+	0x18, /* 00011000 */
+	0x0c, /* 00001100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 97 0x61 'a' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x78, /* 01111000 */
+	0x0c, /* 00001100 */
+	0x7c, /* 01111100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0x76, /* 01110110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 98 0x62 'b' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xe0, /* 11100000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0x78, /* 01111000 */
+	0x6c, /* 01101100 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 99 0x63 'c' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 100 0x64 'd' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x1c, /* 00011100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x3c, /* 00111100 */
+	0x6c, /* 01101100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0x76, /* 01110110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 101 0x65 'e' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xfe, /* 11111110 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 102 0x66 'f' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x1c, /* 00011100 */
+	0x36, /* 00110110 */
+	0x32, /* 00110010 */
+	0x30, /* 00110000 */
+	0x78, /* 01111000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x78, /* 01111000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 103 0x67 'g' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x76, /* 01110110 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0x7c, /* 01111100 */
+	0x0c, /* 00001100 */
+	0xcc, /* 11001100 */
+	0x78, /* 01111000 */
+	0x00, /* 00000000 */
+
+	/* 104 0x68 'h' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xe0, /* 11100000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0x6c, /* 01101100 */
+	0x76, /* 01110110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0xe6, /* 11100110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 105 0x69 'i' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x38, /* 00111000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 106 0x6a 'j' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0x00, /* 00000000 */
+	0x0e, /* 00001110 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x3c, /* 00111100 */
+	0x00, /* 00000000 */
+
+	/* 107 0x6b 'k' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xe0, /* 11100000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0x66, /* 01100110 */
+	0x6c, /* 01101100 */
+	0x78, /* 01111000 */
+	0x78, /* 01111000 */
+	0x6c, /* 01101100 */
+	0x66, /* 01100110 */
+	0xe6, /* 11100110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 108 0x6c 'l' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x38, /* 00111000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 109 0x6d 'm' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xec, /* 11101100 */
+	0xfe, /* 11111110 */
+	0xd6, /* 11010110 */
+	0xd6, /* 11010110 */
+	0xd6, /* 11010110 */
+	0xd6, /* 11010110 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 110 0x6e 'n' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xdc, /* 11011100 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 111 0x6f 'o' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 112 0x70 'p' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xdc, /* 11011100 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x7c, /* 01111100 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0xf0, /* 11110000 */
+	0x00, /* 00000000 */
+
+	/* 113 0x71 'q' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x76, /* 01110110 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0x7c, /* 01111100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x1e, /* 00011110 */
+	0x00, /* 00000000 */
+
+	/* 114 0x72 'r' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xdc, /* 11011100 */
+	0x76, /* 01110110 */
+	0x66, /* 01100110 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0xf0, /* 11110000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 115 0x73 's' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0x60, /* 01100000 */
+	0x38, /* 00111000 */
+	0x0c, /* 00001100 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 116 0x74 't' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x10, /* 00010000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0xfc, /* 11111100 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x36, /* 00110110 */
+	0x1c, /* 00011100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 117 0x75 'u' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0x76, /* 01110110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 118 0x76 'v' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x6c, /* 01101100 */
+	0x38, /* 00111000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 119 0x77 'w' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xd6, /* 11010110 */
+	0xd6, /* 11010110 */
+	0xd6, /* 11010110 */
+	0xfe, /* 11111110 */
+	0x6c, /* 01101100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 120 0x78 'x' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0x6c, /* 01101100 */
+	0x38, /* 00111000 */
+	0x38, /* 00111000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 121 0x79 'y' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x7e, /* 01111110 */
+	0x06, /* 00000110 */
+	0x0c, /* 00001100 */
+	0xf8, /* 11111000 */
+	0x00, /* 00000000 */
+
+	/* 122 0x7a 'z' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0xcc, /* 11001100 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x60, /* 01100000 */
+	0xc6, /* 11000110 */
+	0xfe, /* 11111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 123 0x7b '{' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x0e, /* 00001110 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x70, /* 01110000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x0e, /* 00001110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 124 0x7c '|' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 125 0x7d '}' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x70, /* 01110000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x0e, /* 00001110 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x70, /* 01110000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 126 0x7e '~' */
+	0x00, /* 00000000 */
+	0x76, /* 01110110 */
+	0xdc, /* 11011100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 127 0x7f '' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x10, /* 00010000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xfe, /* 11111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 128 0x80 '€' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x3c, /* 00111100 */
+	0x66, /* 01100110 */
+	0xc2, /* 11000010 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc2, /* 11000010 */
+	0x66, /* 01100110 */
+	0x3c, /* 00111100 */
+	0x18, /* 00011000 */
+	0x70, /* 01110000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 129 0x81 '�' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xcc, /* 11001100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0x76, /* 01110110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 130 0x82 '‚' */
+	0x00, /* 00000000 */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xfe, /* 11111110 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 131 0x83 'ƒ' */
+	0x00, /* 00000000 */
+	0x10, /* 00010000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0x00, /* 00000000 */
+	0x78, /* 01111000 */
+	0x0c, /* 00001100 */
+	0x7c, /* 01111100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0x76, /* 01110110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 132 0x84 '„' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xcc, /* 11001100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x78, /* 01111000 */
+	0x0c, /* 00001100 */
+	0x7c, /* 01111100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0x76, /* 01110110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 133 0x85 '…' */
+	0x00, /* 00000000 */
+	0x60, /* 01100000 */
+	0x30, /* 00110000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x78, /* 01111000 */
+	0x0c, /* 00001100 */
+	0x7c, /* 01111100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0x76, /* 01110110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 134 0x86 '†' */
+	0x00, /* 00000000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0x38, /* 00111000 */
+	0x00, /* 00000000 */
+	0x78, /* 01111000 */
+	0x0c, /* 00001100 */
+	0x7c, /* 01111100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0x76, /* 01110110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 135 0x87 '‡' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x18, /* 00011000 */
+	0x70, /* 01110000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 136 0x88 'ˆ' */
+	0x00, /* 00000000 */
+	0x10, /* 00010000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xfe, /* 11111110 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 137 0x89 '‰' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xfe, /* 11111110 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 138 0x8a 'Š' */
+	0x00, /* 00000000 */
+	0x60, /* 01100000 */
+	0x30, /* 00110000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xfe, /* 11111110 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 139 0x8b '‹' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x66, /* 01100110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x38, /* 00111000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 140 0x8c 'Œ' */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x66, /* 01100110 */
+	0x00, /* 00000000 */
+	0x38, /* 00111000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 141 0x8d '�' */
+	0x00, /* 00000000 */
+	0x60, /* 01100000 */
+	0x30, /* 00110000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x38, /* 00111000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 142 0x8e 'Ž' */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x10, /* 00010000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xfe, /* 11111110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 143 0x8f '�' */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0x38, /* 00111000 */
+	0x10, /* 00010000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0xc6, /* 11000110 */
+	0xfe, /* 11111110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 144 0x90 '�' */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0x66, /* 01100110 */
+	0x62, /* 01100010 */
+	0x68, /* 01101000 */
+	0x78, /* 01111000 */
+	0x68, /* 01101000 */
+	0x62, /* 01100010 */
+	0x66, /* 01100110 */
+	0xfe, /* 11111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 145 0x91 '‘' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xec, /* 11101100 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x7e, /* 01111110 */
+	0xd8, /* 11011000 */
+	0xd8, /* 11011000 */
+	0x6e, /* 01101110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 146 0x92 '’' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x3e, /* 00111110 */
+	0x6c, /* 01101100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xfe, /* 11111110 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xce, /* 11001110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 147 0x93 '“' */
+	0x00, /* 00000000 */
+	0x10, /* 00010000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 148 0x94 '”' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 149 0x95 '•' */
+	0x00, /* 00000000 */
+	0x60, /* 01100000 */
+	0x30, /* 00110000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 150 0x96 '–' */
+	0x00, /* 00000000 */
+	0x30, /* 00110000 */
+	0x78, /* 01111000 */
+	0xcc, /* 11001100 */
+	0x00, /* 00000000 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0x76, /* 01110110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 151 0x97 '—' */
+	0x00, /* 00000000 */
+	0x60, /* 01100000 */
+	0x30, /* 00110000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0x76, /* 01110110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 152 0x98 '˜' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x7e, /* 01111110 */
+	0x06, /* 00000110 */
+	0x0c, /* 00001100 */
+	0x78, /* 01111000 */
+	0x00, /* 00000000 */
+
+	/* 153 0x99 '™' */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 154 0x9a 'š' */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 155 0x9b '›' */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 156 0x9c 'œ' */
+	0x00, /* 00000000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0x64, /* 01100100 */
+	0x60, /* 01100000 */
+	0xf0, /* 11110000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0xe6, /* 11100110 */
+	0xfc, /* 11111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 157 0x9d '�' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x3c, /* 00111100 */
+	0x18, /* 00011000 */
+	0x7e, /* 01111110 */
+	0x18, /* 00011000 */
+	0x7e, /* 01111110 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 158 0x9e 'ž' */
+	0x00, /* 00000000 */
+	0xf8, /* 11111000 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xf8, /* 11111000 */
+	0xc4, /* 11000100 */
+	0xcc, /* 11001100 */
+	0xde, /* 11011110 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 159 0x9f 'Ÿ' */
+	0x00, /* 00000000 */
+	0x0e, /* 00001110 */
+	0x1b, /* 00011011 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x7e, /* 01111110 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0xd8, /* 11011000 */
+	0x70, /* 01110000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 160 0xa0 ' ' */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x60, /* 01100000 */
+	0x00, /* 00000000 */
+	0x78, /* 01111000 */
+	0x0c, /* 00001100 */
+	0x7c, /* 01111100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0x76, /* 01110110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 161 0xa1 '¡' */
+	0x00, /* 00000000 */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x00, /* 00000000 */
+	0x38, /* 00111000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 162 0xa2 '¢' */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x60, /* 01100000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 163 0xa3 '£' */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x60, /* 01100000 */
+	0x00, /* 00000000 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0x76, /* 01110110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 164 0xa4 '¤' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x76, /* 01110110 */
+	0xdc, /* 11011100 */
+	0x00, /* 00000000 */
+	0xdc, /* 11011100 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 165 0xa5 '¥' */
+	0x76, /* 01110110 */
+	0xdc, /* 11011100 */
+	0x00, /* 00000000 */
+	0xc6, /* 11000110 */
+	0xe6, /* 11100110 */
+	0xf6, /* 11110110 */
+	0xfe, /* 11111110 */
+	0xde, /* 11011110 */
+	0xce, /* 11001110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 166 0xa6 '¦' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x3c, /* 00111100 */
+	0x6c, /* 01101100 */
+	0x6c, /* 01101100 */
+	0x3e, /* 00111110 */
+	0x00, /* 00000000 */
+	0x7e, /* 01111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 167 0xa7 '§' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0x6c, /* 01101100 */
+	0x38, /* 00111000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 168 0xa8 '¨' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x00, /* 00000000 */
+	0x30, /* 00110000 */
+	0x30, /* 00110000 */
+	0x60, /* 01100000 */
+	0xc0, /* 11000000 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x7c, /* 01111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 169 0xa9 '©' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 170 0xaa 'ª' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 171 0xab '«' */
+	0x00, /* 00000000 */
+	0x60, /* 01100000 */
+	0xe0, /* 11100000 */
+	0x62, /* 01100010 */
+	0x66, /* 01100110 */
+	0x6c, /* 01101100 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x60, /* 01100000 */
+	0xdc, /* 11011100 */
+	0x86, /* 10000110 */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x3e, /* 00111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 172 0xac '¬' */
+	0x00, /* 00000000 */
+	0x60, /* 01100000 */
+	0xe0, /* 11100000 */
+	0x62, /* 01100010 */
+	0x66, /* 01100110 */
+	0x6c, /* 01101100 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x66, /* 01100110 */
+	0xce, /* 11001110 */
+	0x9a, /* 10011010 */
+	0x3f, /* 00111111 */
+	0x06, /* 00000110 */
+	0x06, /* 00000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 173 0xad '­' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x3c, /* 00111100 */
+	0x3c, /* 00111100 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 174 0xae '®' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x36, /* 00110110 */
+	0x6c, /* 01101100 */
+	0xd8, /* 11011000 */
+	0x6c, /* 01101100 */
+	0x36, /* 00110110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 175 0xaf '¯' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xd8, /* 11011000 */
+	0x6c, /* 01101100 */
+	0x36, /* 00110110 */
+	0x6c, /* 01101100 */
+	0xd8, /* 11011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 176 0xb0 '°' */
+	0x11, /* 00010001 */
+	0x44, /* 01000100 */
+	0x11, /* 00010001 */
+	0x44, /* 01000100 */
+	0x11, /* 00010001 */
+	0x44, /* 01000100 */
+	0x11, /* 00010001 */
+	0x44, /* 01000100 */
+	0x11, /* 00010001 */
+	0x44, /* 01000100 */
+	0x11, /* 00010001 */
+	0x44, /* 01000100 */
+	0x11, /* 00010001 */
+	0x44, /* 01000100 */
+	0x11, /* 00010001 */
+	0x44, /* 01000100 */
+
+	/* 177 0xb1 '±' */
+	0x55, /* 01010101 */
+	0xaa, /* 10101010 */
+	0x55, /* 01010101 */
+	0xaa, /* 10101010 */
+	0x55, /* 01010101 */
+	0xaa, /* 10101010 */
+	0x55, /* 01010101 */
+	0xaa, /* 10101010 */
+	0x55, /* 01010101 */
+	0xaa, /* 10101010 */
+	0x55, /* 01010101 */
+	0xaa, /* 10101010 */
+	0x55, /* 01010101 */
+	0xaa, /* 10101010 */
+	0x55, /* 01010101 */
+	0xaa, /* 10101010 */
+
+	/* 178 0xb2 '²' */
+	0xdd, /* 11011101 */
+	0x77, /* 01110111 */
+	0xdd, /* 11011101 */
+	0x77, /* 01110111 */
+	0xdd, /* 11011101 */
+	0x77, /* 01110111 */
+	0xdd, /* 11011101 */
+	0x77, /* 01110111 */
+	0xdd, /* 11011101 */
+	0x77, /* 01110111 */
+	0xdd, /* 11011101 */
+	0x77, /* 01110111 */
+	0xdd, /* 11011101 */
+	0x77, /* 01110111 */
+	0xdd, /* 11011101 */
+	0x77, /* 01110111 */
+
+	/* 179 0xb3 '³' */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+
+	/* 180 0xb4 '´' */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0xf8, /* 11111000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+
+	/* 181 0xb5 'µ' */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0xf8, /* 11111000 */
+	0x18, /* 00011000 */
+	0xf8, /* 11111000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+
+	/* 182 0xb6 '¶' */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0xf6, /* 11110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+
+	/* 183 0xb7 '·' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+
+	/* 184 0xb8 '¸' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xf8, /* 11111000 */
+	0x18, /* 00011000 */
+	0xf8, /* 11111000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+
+	/* 185 0xb9 '¹' */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0xf6, /* 11110110 */
+	0x06, /* 00000110 */
+	0xf6, /* 11110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+
+	/* 186 0xba 'º' */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+
+	/* 187 0xbb '»' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0x06, /* 00000110 */
+	0xf6, /* 11110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+
+	/* 188 0xbc '¼' */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0xf6, /* 11110110 */
+	0x06, /* 00000110 */
+	0xfe, /* 11111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 189 0xbd '½' */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0xfe, /* 11111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 190 0xbe '¾' */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0xf8, /* 11111000 */
+	0x18, /* 00011000 */
+	0xf8, /* 11111000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 191 0xbf '¿' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xf8, /* 11111000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+
+	/* 192 0xc0 'À' */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x1f, /* 00011111 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 193 0xc1 'Á' */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0xff, /* 11111111 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 194 0xc2 'Â' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xff, /* 11111111 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+
+	/* 195 0xc3 'Ã' */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x1f, /* 00011111 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+
+	/* 196 0xc4 'Ä' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xff, /* 11111111 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 197 0xc5 'Å' */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0xff, /* 11111111 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+
+	/* 198 0xc6 'Æ' */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x1f, /* 00011111 */
+	0x18, /* 00011000 */
+	0x1f, /* 00011111 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+
+	/* 199 0xc7 'Ç' */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x37, /* 00110111 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+
+	/* 200 0xc8 'È' */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x37, /* 00110111 */
+	0x30, /* 00110000 */
+	0x3f, /* 00111111 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 201 0xc9 'É' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x3f, /* 00111111 */
+	0x30, /* 00110000 */
+	0x37, /* 00110111 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+
+	/* 202 0xca 'Ê' */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0xf7, /* 11110111 */
+	0x00, /* 00000000 */
+	0xff, /* 11111111 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 203 0xcb 'Ë' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xff, /* 11111111 */
+	0x00, /* 00000000 */
+	0xf7, /* 11110111 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+
+	/* 204 0xcc 'Ì' */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x37, /* 00110111 */
+	0x30, /* 00110000 */
+	0x37, /* 00110111 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+
+	/* 205 0xcd 'Í' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xff, /* 11111111 */
+	0x00, /* 00000000 */
+	0xff, /* 11111111 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 206 0xce 'Î' */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0xf7, /* 11110111 */
+	0x00, /* 00000000 */
+	0xf7, /* 11110111 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+
+	/* 207 0xcf 'Ï' */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0xff, /* 11111111 */
+	0x00, /* 00000000 */
+	0xff, /* 11111111 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 208 0xd0 'Ð' */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0xff, /* 11111111 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 209 0xd1 'Ñ' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xff, /* 11111111 */
+	0x00, /* 00000000 */
+	0xff, /* 11111111 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+
+	/* 210 0xd2 'Ò' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xff, /* 11111111 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+
+	/* 211 0xd3 'Ó' */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x3f, /* 00111111 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 212 0xd4 'Ô' */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x1f, /* 00011111 */
+	0x18, /* 00011000 */
+	0x1f, /* 00011111 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 213 0xd5 'Õ' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x1f, /* 00011111 */
+	0x18, /* 00011000 */
+	0x1f, /* 00011111 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+
+	/* 214 0xd6 'Ö' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x3f, /* 00111111 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+
+	/* 215 0xd7 '×' */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0xff, /* 11111111 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+
+	/* 216 0xd8 'Ø' */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0xff, /* 11111111 */
+	0x18, /* 00011000 */
+	0xff, /* 11111111 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+
+	/* 217 0xd9 'Ù' */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0xf8, /* 11111000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 218 0xda 'Ú' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x1f, /* 00011111 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+
+	/* 219 0xdb 'Û' */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+
+	/* 220 0xdc 'Ü' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+
+	/* 221 0xdd 'Ý' */
+	0xf0, /* 11110000 */
+	0xf0, /* 11110000 */
+	0xf0, /* 11110000 */
+	0xf0, /* 11110000 */
+	0xf0, /* 11110000 */
+	0xf0, /* 11110000 */
+	0xf0, /* 11110000 */
+	0xf0, /* 11110000 */
+	0xf0, /* 11110000 */
+	0xf0, /* 11110000 */
+	0xf0, /* 11110000 */
+	0xf0, /* 11110000 */
+	0xf0, /* 11110000 */
+	0xf0, /* 11110000 */
+	0xf0, /* 11110000 */
+	0xf0, /* 11110000 */
+
+	/* 222 0xde 'Þ' */
+	0x0f, /* 00001111 */
+	0x0f, /* 00001111 */
+	0x0f, /* 00001111 */
+	0x0f, /* 00001111 */
+	0x0f, /* 00001111 */
+	0x0f, /* 00001111 */
+	0x0f, /* 00001111 */
+	0x0f, /* 00001111 */
+	0x0f, /* 00001111 */
+	0x0f, /* 00001111 */
+	0x0f, /* 00001111 */
+	0x0f, /* 00001111 */
+	0x0f, /* 00001111 */
+	0x0f, /* 00001111 */
+	0x0f, /* 00001111 */
+	0x0f, /* 00001111 */
+
+	/* 223 0xdf 'ß' */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0xff, /* 11111111 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 224 0xe0 'à' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x76, /* 01110110 */
+	0xdc, /* 11011100 */
+	0xd8, /* 11011000 */
+	0xd8, /* 11011000 */
+	0xd8, /* 11011000 */
+	0xdc, /* 11011100 */
+	0x76, /* 01110110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 225 0xe1 'á' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x78, /* 01111000 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xcc, /* 11001100 */
+	0xd8, /* 11011000 */
+	0xcc, /* 11001100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xcc, /* 11001100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 226 0xe2 'â' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0xc0, /* 11000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 227 0xe3 'ã' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0x6c, /* 01101100 */
+	0x6c, /* 01101100 */
+	0x6c, /* 01101100 */
+	0x6c, /* 01101100 */
+	0x6c, /* 01101100 */
+	0x6c, /* 01101100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 228 0xe4 'ä' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0xc6, /* 11000110 */
+	0x60, /* 01100000 */
+	0x30, /* 00110000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x60, /* 01100000 */
+	0xc6, /* 11000110 */
+	0xfe, /* 11111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 229 0xe5 'å' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7e, /* 01111110 */
+	0xd8, /* 11011000 */
+	0xd8, /* 11011000 */
+	0xd8, /* 11011000 */
+	0xd8, /* 11011000 */
+	0xd8, /* 11011000 */
+	0x70, /* 01110000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 230 0xe6 'æ' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x7c, /* 01111100 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0xc0, /* 11000000 */
+	0x00, /* 00000000 */
+
+	/* 231 0xe7 'ç' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x76, /* 01110110 */
+	0xdc, /* 11011100 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 232 0xe8 'è' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7e, /* 01111110 */
+	0x18, /* 00011000 */
+	0x3c, /* 00111100 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x3c, /* 00111100 */
+	0x18, /* 00011000 */
+	0x7e, /* 01111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 233 0xe9 'é' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xfe, /* 11111110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x6c, /* 01101100 */
+	0x38, /* 00111000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 234 0xea 'ê' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x6c, /* 01101100 */
+	0x6c, /* 01101100 */
+	0x6c, /* 01101100 */
+	0x6c, /* 01101100 */
+	0xee, /* 11101110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 235 0xeb 'ë' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x1e, /* 00011110 */
+	0x30, /* 00110000 */
+	0x18, /* 00011000 */
+	0x0c, /* 00001100 */
+	0x3e, /* 00111110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x66, /* 01100110 */
+	0x3c, /* 00111100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 236 0xec 'ì' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7e, /* 01111110 */
+	0xdb, /* 11011011 */
+	0xdb, /* 11011011 */
+	0xdb, /* 11011011 */
+	0x7e, /* 01111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 237 0xed 'í' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x03, /* 00000011 */
+	0x06, /* 00000110 */
+	0x7e, /* 01111110 */
+	0xdb, /* 11011011 */
+	0xdb, /* 11011011 */
+	0xf3, /* 11110011 */
+	0x7e, /* 01111110 */
+	0x60, /* 01100000 */
+	0xc0, /* 11000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 238 0xee 'î' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x1c, /* 00011100 */
+	0x30, /* 00110000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0x7c, /* 01111100 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0x60, /* 01100000 */
+	0x30, /* 00110000 */
+	0x1c, /* 00011100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 239 0xef 'ï' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7c, /* 01111100 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0xc6, /* 11000110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 240 0xf0 'ð' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0xfe, /* 11111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 241 0xf1 'ñ' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x7e, /* 01111110 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7e, /* 01111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 242 0xf2 'ò' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x30, /* 00110000 */
+	0x18, /* 00011000 */
+	0x0c, /* 00001100 */
+	0x06, /* 00000110 */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x00, /* 00000000 */
+	0x7e, /* 01111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 243 0xf3 'ó' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x30, /* 00110000 */
+	0x60, /* 01100000 */
+	0x30, /* 00110000 */
+	0x18, /* 00011000 */
+	0x0c, /* 00001100 */
+	0x00, /* 00000000 */
+	0x7e, /* 01111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 244 0xf4 'ô' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x0e, /* 00001110 */
+	0x1b, /* 00011011 */
+	0x1b, /* 00011011 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+
+	/* 245 0xf5 'õ' */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0xd8, /* 11011000 */
+	0xd8, /* 11011000 */
+	0xd8, /* 11011000 */
+	0x70, /* 01110000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 246 0xf6 'ö' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x7e, /* 01111110 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 247 0xf7 '÷' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x76, /* 01110110 */
+	0xdc, /* 11011100 */
+	0x00, /* 00000000 */
+	0x76, /* 01110110 */
+	0xdc, /* 11011100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 248 0xf8 'ø' */
+	0x00, /* 00000000 */
+	0x38, /* 00111000 */
+	0x6c, /* 01101100 */
+	0x6c, /* 01101100 */
+	0x38, /* 00111000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 249 0xf9 'ù' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 250 0xfa 'ú' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x18, /* 00011000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 251 0xfb 'û' */
+	0x00, /* 00000000 */
+	0x0f, /* 00001111 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0x0c, /* 00001100 */
+	0xec, /* 11101100 */
+	0x6c, /* 01101100 */
+	0x6c, /* 01101100 */
+	0x3c, /* 00111100 */
+	0x1c, /* 00011100 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 252 0xfc 'ü' */
+	0x00, /* 00000000 */
+	0x6c, /* 01101100 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x36, /* 00110110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 253 0xfd 'ý' */
+	0x00, /* 00000000 */
+	0x3c, /* 00111100 */
+	0x66, /* 01100110 */
+	0x0c, /* 00001100 */
+	0x18, /* 00011000 */
+	0x32, /* 00110010 */
+	0x7e, /* 01111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 254 0xfe 'þ' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x7e, /* 01111110 */
+	0x7e, /* 01111110 */
+	0x7e, /* 01111110 */
+	0x7e, /* 01111110 */
+	0x7e, /* 01111110 */
+	0x7e, /* 01111110 */
+	0x7e, /* 01111110 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+	/* 255 0xff 'ÿ' */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+	0x00, /* 00000000 */
+
+};
+
+#endif
diff --git a/qemu/roms/u-boot/include/video_logo.h b/qemu/roms/u-boot/include/video_logo.h
new file mode 100644
index 000000000..a0d2da430
--- /dev/null
+++ b/qemu/roms/u-boot/include/video_logo.h
@@ -0,0 +1,1951 @@
+/* */
+/* Generated by EasyLogo, (C) 2000 by Paolo Scaffardi */
+/* */
+/* To use this, include it and call: easylogo_plot(screen,&u_boot_logo, width,x,y) */
+/* */
+/* Where:	'screen'	is the pointer to the frame buffer */
+/*		'width'	is the screen width */
+/*		'x'		is the horizontal position */
+/*		'y'		is the vertical position */
+/* */
+
+#include <video_easylogo.h>
+
+#define	DEF_U_BOOT_LOGO_WIDTH		160
+#define	DEF_U_BOOT_LOGO_HEIGHT		96
+#define	DEF_U_BOOT_LOGO_PIXELS		15360
+#define	DEF_U_BOOT_LOGO_BPP		16
+#define	DEF_U_BOOT_LOGO_PIXEL_SIZE	2
+#define	DEF_U_BOOT_LOGO_SIZE		30720
+
+unsigned char DEF_U_BOOT_LOGO_DATA[DEF_U_BOOT_LOGO_SIZE] = {
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xb6,
+ 0x80, 0xb6, 0x80, 0xb6, 0x80, 0xb6, 0x80, 0xb6, 0x80, 0xb6, 0x80, 0xb6, 0x80, 0xb6, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f,
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+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7e, 0xaa, 0x7a, 0x3f, 0x7e, 0xa0, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7c, 0x4b, 0x7a, 0x3f, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7c, 0x4b, 0x7c, 0x69,
+ 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x7f, 0x8b, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1,
+ 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x80, 0xe1, 0x7d, 0x80, 0x7a, 0x3f, 0x7a, 0x3f,
+ 0x7a, 0x3f, 0x7c, 0x69, 0x7b, 0x60, 0x7a, 0x3f, 0x7a, 0x3f, 0x7a, 0x3f, 0x80, 0xe1, 0x80, 0xe1
+};
+
+fastimage_t u_boot_logo = {
+		DEF_U_BOOT_LOGO_DATA,
+		DEF_U_BOOT_LOGO_WIDTH,
+		DEF_U_BOOT_LOGO_HEIGHT,
+		DEF_U_BOOT_LOGO_BPP,
+		DEF_U_BOOT_LOGO_PIXEL_SIZE,
+		DEF_U_BOOT_LOGO_SIZE
+};
diff --git a/qemu/roms/u-boot/include/virtex2.h b/qemu/roms/u-boot/include/virtex2.h
new file mode 100644
index 000000000..7b7825f51
--- /dev/null
+++ b/qemu/roms/u-boot/include/virtex2.h
@@ -0,0 +1,96 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _VIRTEX2_H_
+#define _VIRTEX2_H_
+
+#include <xilinx.h>
+
+extern struct xilinx_fpga_op virtex2_op;
+
+/*
+ * Slave SelectMap Implementation function table.
+ */
+typedef struct {
+	xilinx_pre_fn	pre;
+	xilinx_pgm_fn	pgm;
+	xilinx_init_fn	init;
+	xilinx_err_fn	err;
+	xilinx_done_fn	done;
+	xilinx_clk_fn	clk;
+	xilinx_cs_fn	cs;
+	xilinx_wr_fn	wr;
+	xilinx_rdata_fn	rdata;
+	xilinx_wdata_fn	wdata;
+	xilinx_busy_fn	busy;
+	xilinx_abort_fn	abort;
+	xilinx_post_fn	post;
+} xilinx_virtex2_slave_selectmap_fns;
+
+/* Slave Serial Implementation function table */
+typedef struct {
+	xilinx_pgm_fn	pgm;
+	xilinx_clk_fn	clk;
+	xilinx_rdata_fn	rdata;
+	xilinx_wdata_fn	wdata;
+} xilinx_virtex2_slave_serial_fns;
+
+/* Device Image Sizes (in bytes)
+ *********************************************************************/
+#define XILINX_XC2V40_SIZE		(338208 / 8)
+#define XILINX_XC2V80_SIZE		(597408 / 8)
+#define XILINX_XC2V250_SIZE		(1591584 / 8)
+#define XILINX_XC2V500_SIZE		(2557857 / 8)
+#define XILINX_XC2V1000_SIZE	(3749408 / 8)
+#define XILINX_XC2V1500_SIZE	(5166240 / 8)
+#define XILINX_XC2V2000_SIZE	(6808352 / 8)
+#define XILINX_XC2V3000_SIZE	(9589408 / 8)
+#define XILINX_XC2V4000_SIZE	(14220192 / 8)
+#define XILINX_XC2V6000_SIZE	(19752096 / 8)
+#define XILINX_XC2V8000_SIZE	(26185120 / 8)
+#define XILINX_XC2V10000_SIZE	(33519264 / 8)
+
+/* Descriptor Macros
+ *********************************************************************/
+#define XILINX_XC2V40_DESC(iface, fn_table, cookie)	\
+{ xilinx_virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie, &virtex2_op }
+
+#define XILINX_XC2V80_DESC(iface, fn_table, cookie) \
+{ xilinx_virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie, &virtex2_op }
+
+#define XILINX_XC2V250_DESC(iface, fn_table, cookie) \
+{ xilinx_virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie, &virtex2_op }
+
+#define XILINX_XC2V500_DESC(iface, fn_table, cookie) \
+{ xilinx_virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie, &virtex2_op }
+
+#define XILINX_XC2V1000_DESC(iface, fn_table, cookie) \
+{ xilinx_virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie, &virtex2_op }
+
+#define XILINX_XC2V1500_DESC(iface, fn_table, cookie) \
+{ xilinx_virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie, &virtex2_op }
+
+#define XILINX_XC2V2000_DESC(iface, fn_table, cookie) \
+{ xilinx_virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie, &virtex2_op }
+
+#define XILINX_XC2V3000_DESC(iface, fn_table, cookie) \
+{ xilinx_virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie, &virtex2_op }
+
+#define XILINX_XC2V4000_DESC(iface, fn_table, cookie) \
+{ xilinx_virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie, &virtex2_op }
+
+#define XILINX_XC2V6000_DESC(iface, fn_table, cookie) \
+{ xilinx_virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie, &virtex2_op }
+
+#define XILINX_XC2V8000_DESC(iface, fn_table, cookie) \
+{ xilinx_virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie, &virtex2_op }
+
+#define XILINX_XC2V10000_DESC(iface, fn_table, cookie) \
+{ xilinx_virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie, &virtex2_op }
+
+#endif /* _VIRTEX2_H_ */
diff --git a/qemu/roms/u-boot/include/vsc7385.h b/qemu/roms/u-boot/include/vsc7385.h
new file mode 100644
index 000000000..fceb078fc
--- /dev/null
+++ b/qemu/roms/u-boot/include/vsc7385.h
@@ -0,0 +1,12 @@
+/*
+ * Header file for vsc7385.c
+ *
+ * Author: Timur Tabi <timur@freescale.com>
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc.  This file is licensed
+ * under the terms of the GNU General Public License version 2.  This
+ * program is licensed "as is" without any warranty of any kind, whether
+ * express or implied.
+ */
+
+int vsc7385_upload_firmware(void *firmware, unsigned int size);
diff --git a/qemu/roms/u-boot/include/vsprintf.h b/qemu/roms/u-boot/include/vsprintf.h
new file mode 100644
index 000000000..5624482d5
--- /dev/null
+++ b/qemu/roms/u-boot/include/vsprintf.h
@@ -0,0 +1,176 @@
+/*
+ * (C) Copyright 2000-2009
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __VSPRINTF_H
+#define __VSPRINTF_H
+
+ulong simple_strtoul(const char *cp, char **endp, unsigned int base);
+
+/**
+ * strict_strtoul - convert a string to an unsigned long strictly
+ * @param cp	The string to be converted
+ * @param base	The number base to use
+ * @param res	The converted result value
+ * @return 0 if conversion is successful and *res is set to the converted
+ * value, otherwise it returns -EINVAL and *res is set to 0.
+ *
+ * strict_strtoul converts a string to an unsigned long only if the
+ * string is really an unsigned long string, any string containing
+ * any invalid char at the tail will be rejected and -EINVAL is returned,
+ * only a newline char at the tail is acceptible because people generally
+ * change a module parameter in the following way:
+ *
+ *      echo 1024 > /sys/module/e1000/parameters/copybreak
+ *
+ * echo will append a newline to the tail.
+ *
+ * simple_strtoul just ignores the successive invalid characters and
+ * return the converted value of prefix part of the string.
+ *
+ * Copied this function from Linux 2.6.38 commit ID:
+ * 521cb40b0c44418a4fd36dc633f575813d59a43d
+ *
+ */
+int strict_strtoul(const char *cp, unsigned int base, unsigned long *res);
+unsigned long long simple_strtoull(const char *cp, char **endp,
+					unsigned int base);
+long simple_strtol(const char *cp, char **endp, unsigned int base);
+void panic(const char *fmt, ...)
+		__attribute__ ((format (__printf__, 1, 2), noreturn));
+
+/**
+ * Format a string and place it in a buffer
+ *
+ * @param buf	The buffer to place the result into
+ * @param fmt	The format string to use
+ * @param ...	Arguments for the format string
+ *
+ * The function returns the number of characters written
+ * into @buf.
+ *
+ * See the vsprintf() documentation for format string extensions over C99.
+ */
+int sprintf(char *buf, const char *fmt, ...)
+		__attribute__ ((format (__printf__, 2, 3)));
+
+/**
+ * Format a string and place it in a buffer (va_list version)
+ *
+ * @param buf	The buffer to place the result into
+ * @param size	The size of the buffer, including the trailing null space
+ * @param fmt	The format string to use
+ * @param args	Arguments for the format string
+ * @return the number of characters which have been written into
+ * the @buf not including the trailing '\0'. If @size is == 0 the function
+ * returns 0.
+ *
+ * If you're not already dealing with a va_list consider using scnprintf().
+ *
+ * See the vsprintf() documentation for format string extensions over C99.
+ */
+int vsprintf(char *buf, const char *fmt, va_list args);
+char *simple_itoa(ulong i);
+
+#ifdef CONFIG_SYS_VSNPRINTF
+/**
+ * Format a string and place it in a buffer
+ *
+ * @param buf	The buffer to place the result into
+ * @param size	The size of the buffer, including the trailing null space
+ * @param fmt	The format string to use
+ * @param ...	Arguments for the format string
+ * @return the number of characters which would be
+ * generated for the given input, excluding the trailing null,
+ * as per ISO C99.  If the return is greater than or equal to
+ * @size, the resulting string is truncated.
+ *
+ * See the vsprintf() documentation for format string extensions over C99.
+ */
+int snprintf(char *buf, size_t size, const char *fmt, ...)
+		__attribute__ ((format (__printf__, 3, 4)));
+
+/**
+ * Format a string and place it in a buffer
+ *
+ * @param buf	The buffer to place the result into
+ * @param size	The size of the buffer, including the trailing null space
+ * @param fmt	The format string to use
+ * @param ...	Arguments for the format string
+ *
+ * The return value is the number of characters written into @buf not including
+ * the trailing '\0'. If @size is == 0 the function returns 0.
+ *
+ * See the vsprintf() documentation for format string extensions over C99.
+ */
+int scnprintf(char *buf, size_t size, const char *fmt, ...)
+		__attribute__ ((format (__printf__, 3, 4)));
+
+/**
+ * Format a string and place it in a buffer (base function)
+ *
+ * @param buf	The buffer to place the result into
+ * @param size	The size of the buffer, including the trailing null space
+ * @param fmt	The format string to use
+ * @param args	Arguments for the format string
+ * @return The number characters which would be generated for the given
+ * input, excluding the trailing '\0', as per ISO C99. Note that fewer
+ * characters may be written if this number of characters is >= size.
+ *
+ * This function follows C99 vsnprintf, but has some extensions:
+ * %pS output the name of a text symbol
+ * %pF output the name of a function pointer
+ * %pR output the address range in a struct resource
+ *
+ * The function returns the number of characters which would be
+ * generated for the given input, excluding the trailing '\0',
+ * as per ISO C99.
+ *
+ * Call this function if you are already dealing with a va_list.
+ * You probably want snprintf() instead.
+ */
+int vsnprintf(char *buf, size_t size, const char *fmt, va_list args);
+
+/**
+ * Format a string and place it in a buffer (va_list version)
+ *
+ * @param buf	The buffer to place the result into
+ * @param size	The size of the buffer, including the trailing null space
+ * @param fmt	The format string to use
+ * @param args	Arguments for the format string
+ * @return the number of characters which have been written into
+ * the @buf not including the trailing '\0'. If @size is == 0 the function
+ * returns 0.
+ *
+ * If you're not already dealing with a va_list consider using scnprintf().
+ *
+ * See the vsprintf() documentation for format string extensions over C99.
+ */
+int vscnprintf(char *buf, size_t size, const char *fmt, va_list args);
+#else
+/*
+ * Use macros to silently drop the size parameter. Note that the 'cn'
+ * versions are the same as the 'n' versions since the functions assume
+ * there is always enough buffer space when !CONFIG_SYS_VSNPRINTF
+ */
+#define snprintf(buf, size, fmt, args...) sprintf(buf, fmt, ##args)
+#define scnprintf(buf, size, fmt, args...) sprintf(buf, fmt, ##args)
+#define vsnprintf(buf, size, fmt, args...) vsprintf(buf, fmt, ##args)
+#define vscnprintf(buf, size, fmt, args...) vsprintf(buf, fmt, ##args)
+#endif /* CONFIG_SYS_VSNPRINTF */
+
+/**
+ * print_grouped_ull() - print a value with digits grouped by ','
+ *
+ * This prints a value with grouped digits, like 12,345,678 to make it easier
+ * to read.
+ *
+ * @val:	Value to print
+ * @digits:	Number of digiits to print
+ */
+void print_grouped_ull(unsigned long long int_val, int digits);
+
+#endif
diff --git a/qemu/roms/u-boot/include/vxworks.h b/qemu/roms/u-boot/include/vxworks.h
new file mode 100644
index 000000000..122043c94
--- /dev/null
+++ b/qemu/roms/u-boot/include/vxworks.h
@@ -0,0 +1,38 @@
+/*
+ * (C) Copyright 2008
+ * Niklaus Giger, niklaus.giger@member.fsf.org
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _VXWORKS_H_
+#define _VXWORKS_H_
+
+int do_bootvx(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+void boot_prep_vxworks(bootm_headers_t *images);
+void boot_jump_vxworks(bootm_headers_t *images);
+void do_bootvx_fdt(bootm_headers_t *images);
+
+/*
+ * Use bootaddr to find the location in memory that VxWorks
+ * will look for the bootline string. The default value for
+ * PowerPC is LOCAL_MEM_LOCAL_ADRS + BOOT_LINE_OFFSET which
+ * defaults to 0x4200
+ */
+#ifndef CONFIG_SYS_VXWORKS_BOOT_ADDR
+#define CONFIG_SYS_VXWORKS_BOOT_ADDR 0x4200
+#endif
+
+#ifndef CONFIG_SYS_VXWORKS_BOOT_DEVICE
+#if defined(CONFIG_4xx)
+#define		CONFIG_SYS_VXWORKS_BOOT_DEVICE "emac(0,0)"
+#else
+#define		CONFIG_SYS_VXWORKS_BOOT_DEVICE "eth(0,0)"
+#endif
+#endif
+
+#ifndef CONFIG_SYS_VXWORKS_SERVERNAME
+#define CONFIG_SYS_VXWORKS_SERVERNAME	"srv"
+#endif
+
+#endif
diff --git a/qemu/roms/u-boot/include/w83c553f.h b/qemu/roms/u-boot/include/w83c553f.h
new file mode 100644
index 000000000..ec872ac24
--- /dev/null
+++ b/qemu/roms/u-boot/include/w83c553f.h
@@ -0,0 +1,162 @@
+/*
+ * (C) Copyright 2000
+ * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+ /* winbond access routines and defines*/
+
+/* from the winbond data sheet -
+ The W83C553F SIO controller with PCI arbiter is a multi-function PCI device.
+ Function 0 is the ISA bridge, and Function 1 is the bus master IDE controller.
+*/
+
+/*ISA bridge configuration space*/
+
+#define W83C553F_VID		0x10AD
+#define W83C553F_DID		0x0565
+
+#define WINBOND_PCICONTR	0x40  /*pci control reg*/
+#define WINBOND_SGBAR		0x41  /*scatter/gather base address reg*/
+#define WINBOND_LBCR		0x42  /*Line Buffer Control reg*/
+#define WINBOND_IDEIRCR		0x43  /*IDE Interrupt Routing Control  Reg*/
+#define WINBOND_PCIIRCR		0x44  /*PCI Interrupt Routing Control Reg*/
+#define WINBOND_BTBAR		0x46  /*BIOS Timer Base Address Register*/
+#define WINBOND_IPADCR		0x48  /*ISA to PCI Address Decoder Control Register*/
+#define WINBOND_IRADCR		0x49  /*ISA ROM Address Decoder Control Register*/
+#define WINBOND_IPMHSAR		0x4a  /*ISA to PCI Memory Hole STart Address Register*/
+#define WINBOND_IPMHSR		0x4b  /*ISA to PCI Memory Hols Size Register*/
+#define WINBOND_CDR			0x4c  /*Clock Divisor Register*/
+#define WINBOND_CSCR		0x4d  /*Chip Select Control Register*/
+#define WINBOND_ATSCR		0x4e  /*AT System Control register*/
+#define WINBOND_ATBCR		0x4f  /*AT Bus ControL Register*/
+#define WINBOND_IRQBEE0R	0x60  /*IRQ Break Event Enable 0 Register*/
+#define WINBOND_IRQBEE1R	0x61  /*IRQ Break Event Enable 1 Register*/
+#define WINBOND_ABEER		0x62  /*Additional Break Event Enable Register*/
+#define WINBOND_DMABEER		0x63  /*DMA Break Event Enable Register*/
+
+#define WINDOND_IDECSR		0x40  /*IDE Control/Status Register, Function 1*/
+
+#define IPADCR_MBE512		0x1
+#define IPADCR_MBE640		0x2
+#define IPADCR_IPATOM4		0x10
+#define IPADCR_IPATOM5		0x20
+#define IPADCR_IPATOM6		0x40
+#define IPADCR_IPATOM7		0x80
+
+#define CSCR_UBIOSCSE		0x10
+#define CSCR_BIOSWP			0x20
+
+#define IDECSR_P0EN			0x01
+#define IDECSR_P0F16		0x02
+#define IDECSR_P1EN			0x10
+#define IDECSR_P1F16		0x20
+#define IDECSR_LEGIRQ		0x800
+
+/*
+ * Interrupt controller
+ */
+#define W83C553F_PIC1_ICW1	CONFIG_SYS_ISA_IO + 0x20
+#define W83C553F_PIC1_ICW2	CONFIG_SYS_ISA_IO + 0x21
+#define W83C553F_PIC1_ICW3	CONFIG_SYS_ISA_IO + 0x21
+#define W83C553F_PIC1_ICW4	CONFIG_SYS_ISA_IO + 0x21
+#define W83C553F_PIC1_OCW1	CONFIG_SYS_ISA_IO + 0x21
+#define W83C553F_PIC1_OCW2	CONFIG_SYS_ISA_IO + 0x20
+#define W83C553F_PIC1_OCW3	CONFIG_SYS_ISA_IO + 0x20
+#define W83C553F_PIC1_ELC	CONFIG_SYS_ISA_IO + 0x4D0
+#define W83C553F_PIC2_ICW1	CONFIG_SYS_ISA_IO + 0xA0
+#define W83C553F_PIC2_ICW2	CONFIG_SYS_ISA_IO + 0xA1
+#define W83C553F_PIC2_ICW3	CONFIG_SYS_ISA_IO + 0xA1
+#define W83C553F_PIC2_ICW4	CONFIG_SYS_ISA_IO + 0xA1
+#define W83C553F_PIC2_OCW1	CONFIG_SYS_ISA_IO + 0xA1
+#define W83C553F_PIC2_OCW2	CONFIG_SYS_ISA_IO + 0xA0
+#define W83C553F_PIC2_OCW3	CONFIG_SYS_ISA_IO + 0xA0
+#define W83C553F_PIC2_ELC	CONFIG_SYS_ISA_IO + 0x4D1
+
+#define W83C553F_TMR1_CMOD	CONFIG_SYS_ISA_IO + 0x43
+
+/*
+ * DMA controller
+ */
+#define W83C553F_DMA1	CONFIG_SYS_ISA_IO + 0x000	/* channel 0 - 3 */
+#define W83C553F_DMA2	CONFIG_SYS_ISA_IO + 0x0C0	/* channel 4 - 7 */
+
+/* command/status register bit definitions */
+
+#define W83C553F_CS_COM_DACKAL	(1<<7)	/* DACK# assert level */
+#define W83C553F_CS_COM_DREQSAL	(1<<6)	/* DREQ sense assert level */
+#define W83C553F_CS_COM_GAP	(1<<4)	/* group arbitration priority */
+#define W83C553F_CS_COM_CGE	(1<<2)	/* channel group enable */
+
+#define W83C553F_CS_STAT_CH0REQ	(1<<4)	/* channel 0 (4) DREQ status */
+#define W83C553F_CS_STAT_CH1REQ	(1<<5)	/* channel 1 (5) DREQ status */
+#define W83C553F_CS_STAT_CH2REQ	(1<<6)	/* channel 2 (6) DREQ status */
+#define W83C553F_CS_STAT_CH3REQ	(1<<7)	/* channel 3 (7) DREQ status */
+
+#define W83C553F_CS_STAT_CH0TC	(1<<0)	/* channel 0 (4) TC status */
+#define W83C553F_CS_STAT_CH1TC	(1<<1)	/* channel 1 (5) TC status */
+#define W83C553F_CS_STAT_CH2TC	(1<<2)	/* channel 2 (6) TC status */
+#define W83C553F_CS_STAT_CH3TC	(1<<3)	/* channel 3 (7) TC status */
+
+/* mode register bit definitions */
+
+#define W83C553F_MODE_TM_DEMAND	(0<<6)	/* transfer mode - demand */
+#define W83C553F_MODE_TM_SINGLE	(1<<6)	/* transfer mode - single */
+#define W83C553F_MODE_TM_BLOCK	(2<<6)	/* transfer mode - block */
+#define W83C553F_MODE_TM_CASCADE	(3<<6)	/* transfer mode - cascade */
+#define W83C553F_MODE_ADDRDEC	(1<<5)	/* address increment/decrement select */
+#define W83C553F_MODE_AUTOINIT	(1<<4)	/* autoinitialize enable */
+#define W83C553F_MODE_TT_VERIFY	(0<<2)	/* transfer type - verify */
+#define W83C553F_MODE_TT_WRITE	(1<<2)	/* transfer type - write */
+#define W83C553F_MODE_TT_READ	(2<<2)	/* transfer type - read */
+#define W83C553F_MODE_TT_ILLEGAL	(3<<2)	/* transfer type - illegal */
+#define W83C553F_MODE_CH0SEL	(0<<0)	/* channel 0 (4) select */
+#define W83C553F_MODE_CH1SEL	(1<<0)	/* channel 1 (5) select */
+#define W83C553F_MODE_CH2SEL	(2<<0)	/* channel 2 (6) select */
+#define W83C553F_MODE_CH3SEL	(3<<0)	/* channel 3 (7) select */
+
+/* request register bit definitions */
+
+#define W83C553F_REQ_CHSERREQ	(1<<2)	/* channel service request */
+#define W83C553F_REQ_CH0SEL	(0<<0)	/* channel 0 (4) select */
+#define W83C553F_REQ_CH1SEL	(1<<0)	/* channel 1 (5) select */
+#define W83C553F_REQ_CH2SEL	(2<<0)	/* channel 2 (6) select */
+#define W83C553F_REQ_CH3SEL	(3<<0)	/* channel 3 (7) select */
+
+/* write single mask bit register bit definitions */
+
+#define W83C553F_WSMB_CHMASKSEL	(1<<2)	/* channel mask select */
+#define W83C553F_WSMB_CH0SEL	(0<<0)	/* channel 0 (4) select */
+#define W83C553F_WSMB_CH1SEL	(1<<0)	/* channel 1 (5) select */
+#define W83C553F_WSMB_CH2SEL	(2<<0)	/* channel 2 (6) select */
+#define W83C553F_WSMB_CH3SEL	(3<<0)	/* channel 3 (7) select */
+
+/* read/write all mask bits register bit definitions */
+
+#define W83C553F_RWAMB_CH0MASK	(1<<0)	/* channel 0 (4) mask */
+#define W83C553F_RWAMB_CH1MASK	(1<<1)	/* channel 1 (5) mask */
+#define W83C553F_RWAMB_CH2MASK	(1<<2)	/* channel 2 (6) mask */
+#define W83C553F_RWAMB_CH3MASK	(1<<3)	/* channel 3 (7) mask */
+
+/* typedefs */
+
+#define W83C553F_DMA1_CS		0x8
+#define W83C553F_DMA1_WR		0x9
+#define W83C553F_DMA1_WSMB		0xA
+#define W83C553F_DMA1_WM		0xB
+#define W83C553F_DMA1_CBP		0xC
+#define W83C553F_DMA1_MC		0xD
+#define W83C553F_DMA1_CM		0xE
+#define W83C553F_DMA1_RWAMB		0xF
+
+#define W83C553F_DMA2_CS		0x10
+#define W83C553F_DMA2_WR		0x12
+#define W83C553F_DMA2_WSMB		0x14
+#define W83C553F_DMA2_WM		0x16
+#define W83C553F_DMA2_CBP		0x18
+#define W83C553F_DMA2_MC		0x1A
+#define W83C553F_DMA2_CM		0x1C
+#define W83C553F_DMA2_RWAMB		0x1E
+
+void initialise_w83c553f(void);
diff --git a/qemu/roms/u-boot/include/watchdog.h b/qemu/roms/u-boot/include/watchdog.h
new file mode 100644
index 000000000..aacacb970
--- /dev/null
+++ b/qemu/roms/u-boot/include/watchdog.h
@@ -0,0 +1,98 @@
+/*
+ * (C) Copyright 2001
+ * Erik Theisen,  Wave 7 Optics, etheisen@mindspring.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Watchdog functions and macros.
+ */
+#ifndef _WATCHDOG_H_
+#define _WATCHDOG_H_
+
+#if !defined(__ASSEMBLY__)
+/*
+ * Reset the watchdog timer, always returns 0
+ *
+ * This function is here since it is shared between board_f() and board_r(),
+ * and the legacy arch/<arch>/board.c code.
+ */
+int init_func_watchdog_reset(void);
+#endif
+
+#ifdef CONFIG_WATCHDOG
+#define INIT_FUNC_WATCHDOG_INIT	init_func_watchdog_init,
+#define INIT_FUNC_WATCHDOG_RESET	init_func_watchdog_reset,
+#else
+#define INIT_FUNC_WATCHDOG_INIT
+#define INIT_FUNC_WATCHDOG_RESET
+#endif
+
+#if defined(CONFIG_HW_WATCHDOG) && defined(CONFIG_WATCHDOG)
+#  error "Configuration error: CONFIG_HW_WATCHDOG and CONFIG_WATCHDOG can't be used together."
+#endif
+
+/*
+ * Hardware watchdog
+ */
+#ifdef CONFIG_HW_WATCHDOG
+	#if defined(__ASSEMBLY__)
+		#define WATCHDOG_RESET bl hw_watchdog_reset
+	#else
+		extern void hw_watchdog_reset(void);
+
+		#define WATCHDOG_RESET hw_watchdog_reset
+	#endif /* __ASSEMBLY__ */
+#else
+	/*
+	 * Maybe a software watchdog?
+	 */
+	#if defined(CONFIG_WATCHDOG)
+		#if defined(__ASSEMBLY__)
+			#define WATCHDOG_RESET bl watchdog_reset
+		#else
+			extern void watchdog_reset(void);
+
+			#define WATCHDOG_RESET watchdog_reset
+		#endif
+	#else
+		/*
+		 * No hardware or software watchdog.
+		 */
+		#if defined(__ASSEMBLY__)
+			#define WATCHDOG_RESET /*XXX DO_NOT_DEL_THIS_COMMENT*/
+		#else
+			#define WATCHDOG_RESET() {}
+		#endif /* __ASSEMBLY__ */
+	#endif /* CONFIG_WATCHDOG && !__ASSEMBLY__ */
+#endif /* CONFIG_HW_WATCHDOG */
+
+/*
+ * Prototypes from $(CPU)/cpu.c.
+ */
+
+/* MPC 8xx */
+#if (defined(CONFIG_8xx) || defined(CONFIG_MPC860)) && !defined(__ASSEMBLY__)
+	void reset_8xx_watchdog(volatile immap_t *immr);
+#endif
+
+/* MPC 5xx */
+#if defined(CONFIG_5xx) && !defined(__ASSEMBLY__)
+	void reset_5xx_watchdog(volatile immap_t *immr);
+#endif
+
+/* MPC 5xxx */
+#if defined(CONFIG_MPC5xxx) && !defined(__ASSEMBLY__)
+	void reset_5xxx_watchdog(void);
+#endif
+
+/* AMCC 4xx */
+#if defined(CONFIG_4xx) && !defined(__ASSEMBLY__)
+	void reset_4xx_watchdog(void);
+#endif
+
+#if defined(CONFIG_HW_WATCHDOG) && !defined(__ASSEMBLY__)
+	void hw_watchdog_init(void);
+#endif
+#endif /* _WATCHDOG_H_ */
diff --git a/qemu/roms/u-boot/include/xilinx.h b/qemu/roms/u-boot/include/xilinx.h
new file mode 100644
index 000000000..9801267c5
--- /dev/null
+++ b/qemu/roms/u-boot/include/xilinx.h
@@ -0,0 +1,76 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <fpga.h>
+
+#ifndef _XILINX_H_
+#define _XILINX_H_
+
+/* Xilinx types
+ *********************************************************************/
+typedef enum {			/* typedef xilinx_iface */
+	min_xilinx_iface_type,	/* low range check value */
+	slave_serial,		/* serial data and external clock */
+	master_serial,		/* serial data w/ internal clock (not used) */
+	slave_parallel,		/* parallel data w/ external latch */
+	jtag_mode,		/* jtag/tap serial (not used ) */
+	master_selectmap,	/* master SelectMap (virtex2)           */
+	slave_selectmap,	/* slave SelectMap (virtex2)            */
+	devcfg,			/* devcfg interface (zynq) */
+	max_xilinx_iface_type	/* insert all new types before this */
+} xilinx_iface;			/* end, typedef xilinx_iface */
+
+typedef enum {			/* typedef xilinx_family */
+	min_xilinx_type,	/* low range check value */
+	xilinx_spartan2,	/* Spartan-II Family */
+	xilinx_virtexE,		/* Virtex-E Family */
+	xilinx_virtex2,		/* Virtex2 Family */
+	xilinx_spartan3,	/* Spartan-III Family */
+	xilinx_zynq,		/* Zynq Family */
+	max_xilinx_type		/* insert all new types before this */
+} xilinx_family;		/* end, typedef xilinx_family */
+
+typedef struct {		/* typedef xilinx_desc */
+	xilinx_family family;	/* part type */
+	xilinx_iface iface;	/* interface type */
+	size_t size;		/* bytes of data part can accept */
+	void *iface_fns;	/* interface function table */
+	int cookie;		/* implementation specific cookie */
+	struct xilinx_fpga_op *operations; /* operations */
+	char *name;		/* device name in bitstream */
+} xilinx_desc;			/* end, typedef xilinx_desc */
+
+struct xilinx_fpga_op {
+	int (*load)(xilinx_desc *, const void *, size_t);
+	int (*dump)(xilinx_desc *, const void *, size_t);
+	int (*info)(xilinx_desc *);
+};
+
+/* Generic Xilinx Functions
+ *********************************************************************/
+int xilinx_load(xilinx_desc *desc, const void *image, size_t size);
+int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize);
+int xilinx_info(xilinx_desc *desc);
+
+/* Board specific implementation specific function types
+ *********************************************************************/
+typedef int (*xilinx_pgm_fn)(int assert_pgm, int flush, int cookie);
+typedef int (*xilinx_init_fn)(int cookie);
+typedef int (*xilinx_err_fn)(int cookie);
+typedef int (*xilinx_done_fn)(int cookie);
+typedef int (*xilinx_clk_fn)(int assert_clk, int flush, int cookie);
+typedef int (*xilinx_cs_fn)(int assert_cs, int flush, int cookie);
+typedef int (*xilinx_wr_fn)(int assert_write, int flush, int cookie);
+typedef int (*xilinx_rdata_fn)(unsigned char *data, int cookie);
+typedef int (*xilinx_wdata_fn)(unsigned char data, int flush, int cookie);
+typedef int (*xilinx_busy_fn)(int cookie);
+typedef int (*xilinx_abort_fn)(int cookie);
+typedef int (*xilinx_pre_fn)(int cookie);
+typedef int (*xilinx_post_fn)(int cookie);
+typedef int (*xilinx_bwr_fn)(void *buf, size_t len, int flush, int cookie);
+
+#endif  /* _XILINX_H_ */
diff --git a/qemu/roms/u-boot/include/xyzModem.h b/qemu/roms/u-boot/include/xyzModem.h
new file mode 100644
index 000000000..0eddbbc78
--- /dev/null
+++ b/qemu/roms/u-boot/include/xyzModem.h
@@ -0,0 +1,77 @@
+/*
+ *==========================================================================
+ *
+ *      xyzModem.h
+ *
+ *      RedBoot stream handler for xyzModem protocol
+ *
+ *==========================================================================
+ * SPDX-License-Identifier:	eCos-2.0
+ *==========================================================================
+ *#####DESCRIPTIONBEGIN####
+ *
+ * Author(s):    gthomas
+ * Contributors: gthomas
+ * Date:         2000-07-14
+ * Purpose:
+ * Description:
+ *
+ * This code is part of RedBoot (tm).
+ *
+ *####DESCRIPTIONEND####
+ *
+ *==========================================================================
+ */
+
+#ifndef _XYZMODEM_H_
+#define _XYZMODEM_H_
+
+#define xyzModem_xmodem 1
+#define xyzModem_ymodem 2
+/* Don't define this until the protocol support is in place */
+/*#define xyzModem_zmodem 3 */
+
+#define xyzModem_access   -1
+#define xyzModem_noZmodem -2
+#define xyzModem_timeout  -3
+#define xyzModem_eof      -4
+#define xyzModem_cancel   -5
+#define xyzModem_frame    -6
+#define xyzModem_cksum    -7
+#define xyzModem_sequence -8
+
+#define xyzModem_close 1
+#define xyzModem_abort 2
+
+
+#ifdef REDBOOT
+extern getc_io_funcs_t xyzModem_io;
+#else
+#define CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT
+#define CYGACC_CALL_IF_SET_CONSOLE_COMM(x)
+
+#define diag_vprintf vprintf
+#define diag_printf printf
+#define diag_vsprintf vsprintf
+
+#define CYGACC_CALL_IF_DELAY_US(x) udelay(x)
+
+typedef struct {
+    char *filename;
+    int   mode;
+    int   chan;
+#ifdef CYGPKG_REDBOOT_NETWORKING
+    struct sockaddr_in *server;
+#endif
+} connection_info_t;
+
+#endif
+
+
+int   xyzModem_stream_open(connection_info_t *info, int *err);
+void  xyzModem_stream_close(int *err);
+void  xyzModem_stream_terminate(bool method, int (*getc)(void));
+int   xyzModem_stream_read(char *buf, int size, int *err);
+char *xyzModem_error(int err);
+
+#endif /* _XYZMODEM_H_ */
diff --git a/qemu/roms/u-boot/include/zfs/dmu.h b/qemu/roms/u-boot/include/zfs/dmu.h
new file mode 100644
index 000000000..f07a1e3a8
--- /dev/null
+++ b/qemu/roms/u-boot/include/zfs/dmu.h
@@ -0,0 +1,108 @@
+/*
+ *  GRUB  --  GRand Unified Bootloader
+ *  Copyright (C) 1999,2000,2001,2002,2003,2004  Free Software Foundation, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/*
+ * Copyright 2010 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SYS_DMU_H
+#define	_SYS_DMU_H
+
+/*
+ * This file describes the interface that the DMU provides for its
+ * consumers.
+ *
+ * The DMU also interacts with the SPA.  That interface is described in
+ * dmu_spa.h.
+ */
+typedef enum dmu_object_type {
+	DMU_OT_NONE,
+	/* general: */
+	DMU_OT_OBJECT_DIRECTORY,	/* ZAP */
+	DMU_OT_OBJECT_ARRAY,		/* UINT64 */
+	DMU_OT_PACKED_NVLIST,		/* UINT8 (XDR by nvlist_pack/unpack) */
+	DMU_OT_PACKED_NVLIST_SIZE,	/* UINT64 */
+	DMU_OT_BPLIST,			/* UINT64 */
+	DMU_OT_BPLIST_HDR,		/* UINT64 */
+	/* spa: */
+	DMU_OT_SPACE_MAP_HEADER,	/* UINT64 */
+	DMU_OT_SPACE_MAP,		/* UINT64 */
+	/* zil: */
+	DMU_OT_INTENT_LOG,		/* UINT64 */
+	/* dmu: */
+	DMU_OT_DNODE,			/* DNODE */
+	DMU_OT_OBJSET,			/* OBJSET */
+	/* dsl: */
+	DMU_OT_DSL_DIR,			/* UINT64 */
+	DMU_OT_DSL_DIR_CHILD_MAP,	/* ZAP */
+	DMU_OT_DSL_DS_SNAP_MAP,		/* ZAP */
+	DMU_OT_DSL_PROPS,		/* ZAP */
+	DMU_OT_DSL_DATASET,		/* UINT64 */
+	/* zpl: */
+	DMU_OT_ZNODE,			/* ZNODE */
+	DMU_OT_OLDACL,			/* OLD ACL */
+	DMU_OT_PLAIN_FILE_CONTENTS,	/* UINT8 */
+	DMU_OT_DIRECTORY_CONTENTS,	/* ZAP */
+	DMU_OT_MASTER_NODE,		/* ZAP */
+	DMU_OT_UNLINKED_SET,		/* ZAP */
+	/* zvol: */
+	DMU_OT_ZVOL,			/* UINT8 */
+	DMU_OT_ZVOL_PROP,		/* ZAP */
+	/* other; for testing only! */
+	DMU_OT_PLAIN_OTHER,		/* UINT8 */
+	DMU_OT_UINT64_OTHER,		/* UINT64 */
+	DMU_OT_ZAP_OTHER,		/* ZAP */
+	/* new object types: */
+	DMU_OT_ERROR_LOG,		/* ZAP */
+	DMU_OT_SPA_HISTORY,		/* UINT8 */
+	DMU_OT_SPA_HISTORY_OFFSETS,	/* spa_his_phys_t */
+	DMU_OT_POOL_PROPS,		/* ZAP */
+	DMU_OT_DSL_PERMS,		/* ZAP */
+	DMU_OT_ACL,			/* ACL */
+	DMU_OT_SYSACL,			/* SYSACL */
+	DMU_OT_FUID,			/* FUID table (Packed NVLIST UINT8) */
+	DMU_OT_FUID_SIZE,		/* FUID table size UINT64 */
+	DMU_OT_NEXT_CLONES,		/* ZAP */
+	DMU_OT_SCRUB_QUEUE,		/* ZAP */
+	DMU_OT_USERGROUP_USED,		/* ZAP */
+	DMU_OT_USERGROUP_QUOTA,		/* ZAP */
+	DMU_OT_USERREFS,		/* ZAP */
+	DMU_OT_DDT_ZAP,			/* ZAP */
+	DMU_OT_DDT_STATS,		/* ZAP */
+	DMU_OT_SA,			/* System attr */
+	DMU_OT_SA_MASTER_NODE,		/* ZAP */
+	DMU_OT_SA_ATTR_REGISTRATION,	/* ZAP */
+	DMU_OT_SA_ATTR_LAYOUTS,		/* ZAP */
+	DMU_OT_NUMTYPES
+} dmu_object_type_t;
+
+typedef enum dmu_objset_type {
+	DMU_OST_NONE,
+	DMU_OST_META,
+	DMU_OST_ZFS,
+	DMU_OST_ZVOL,
+	DMU_OST_OTHER,			/* For testing only! */
+	DMU_OST_ANY,			/* Be careful! */
+	DMU_OST_NUMTYPES
+} dmu_objset_type_t;
+
+/*
+ * The names of zap entries in the DIRECTORY_OBJECT of the MOS.
+ */
+#define	DMU_POOL_DIRECTORY_OBJECT	1
+#define	DMU_POOL_CONFIG			"config"
+#define	DMU_POOL_ROOT_DATASET		"root_dataset"
+#define	DMU_POOL_SYNC_BPLIST		"sync_bplist"
+#define	DMU_POOL_ERRLOG_SCRUB		"errlog_scrub"
+#define	DMU_POOL_ERRLOG_LAST		"errlog_last"
+#define	DMU_POOL_SPARES			"spares"
+#define	DMU_POOL_DEFLATE		"deflate"
+#define	DMU_POOL_HISTORY		"history"
+#define	DMU_POOL_PROPS			"pool_props"
+#define	DMU_POOL_L2CACHE		"l2cache"
+
+#endif	/* _SYS_DMU_H */
diff --git a/qemu/roms/u-boot/include/zfs/dmu_objset.h b/qemu/roms/u-boot/include/zfs/dmu_objset.h
new file mode 100644
index 000000000..2f51fc4e7
--- /dev/null
+++ b/qemu/roms/u-boot/include/zfs/dmu_objset.h
@@ -0,0 +1,31 @@
+/*
+ *  GRUB  --  GRand Unified Bootloader
+ *  Copyright (C) 1999,2000,2001,2002,2003,2004  Free Software Foundation, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/*
+ * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SYS_DMU_OBJSET_H
+#define	_SYS_DMU_OBJSET_H
+
+#include <zfs/zil.h>
+
+#define OBJSET_PHYS_SIZE	2048
+#define OBJSET_PHYS_SIZE_V14	1024
+
+typedef struct objset_phys {
+	dnode_phys_t os_meta_dnode;
+	zil_header_t os_zil_header;
+	uint64_t os_type;
+	uint64_t os_flags;
+	char os_pad[OBJSET_PHYS_SIZE - sizeof(dnode_phys_t)*3 -
+	    sizeof(zil_header_t) - sizeof(uint64_t)*2];
+	dnode_phys_t os_userused_dnode;
+	dnode_phys_t os_groupused_dnode;
+} objset_phys_t;
+
+#endif /* _SYS_DMU_OBJSET_H */
diff --git a/qemu/roms/u-boot/include/zfs/dnode.h b/qemu/roms/u-boot/include/zfs/dnode.h
new file mode 100644
index 000000000..182dd9b41
--- /dev/null
+++ b/qemu/roms/u-boot/include/zfs/dnode.h
@@ -0,0 +1,69 @@
+/*
+ *  GRUB  --  GRand Unified Bootloader
+ *  Copyright (C) 1999,2000,2001,2002,2003,2004  Free Software Foundation, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/*
+ * Copyright 2010 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SYS_DNODE_H
+#define	_SYS_DNODE_H
+
+#include <zfs/spa.h>
+
+/*
+ * Fixed constants.
+ */
+#define	DNODE_SHIFT		9	/* 512 bytes */
+#define	DN_MIN_INDBLKSHIFT	10	/* 1k */
+#define	DN_MAX_INDBLKSHIFT	14	/* 16k */
+#define	DNODE_BLOCK_SHIFT	14	/* 16k */
+#define	DNODE_CORE_SIZE		64	/* 64 bytes for dnode sans blkptrs */
+#define	DN_MAX_OBJECT_SHIFT	48	/* 256 trillion (zfs_fid_t limit) */
+#define	DN_MAX_OFFSET_SHIFT	64	/* 2^64 bytes in a dnode */
+
+/*
+ * Derived constants.
+ */
+#define	DNODE_SIZE	(1 << DNODE_SHIFT)
+#define	DN_MAX_NBLKPTR	((DNODE_SIZE - DNODE_CORE_SIZE) >> SPA_BLKPTRSHIFT)
+#define	DN_MAX_BONUSLEN	(DNODE_SIZE - DNODE_CORE_SIZE - (1 << SPA_BLKPTRSHIFT))
+#define	DN_MAX_OBJECT	(1ULL << DN_MAX_OBJECT_SHIFT)
+
+#define	DNODES_PER_BLOCK_SHIFT	(DNODE_BLOCK_SHIFT - DNODE_SHIFT)
+#define	DNODES_PER_BLOCK	(1ULL << DNODES_PER_BLOCK_SHIFT)
+#define	DNODES_PER_LEVEL_SHIFT	(DN_MAX_INDBLKSHIFT - SPA_BLKPTRSHIFT)
+
+#define	DNODE_FLAG_SPILL_BLKPTR (1<<2)
+
+#define	DN_BONUS(dnp)	((void *)((dnp)->dn_bonus + \
+	(((dnp)->dn_nblkptr - 1) * sizeof(blkptr_t))))
+
+typedef struct dnode_phys {
+	uint8_t dn_type;		/* dmu_object_type_t */
+	uint8_t dn_indblkshift;		/* ln2(indirect block size) */
+	uint8_t dn_nlevels;		/* 1=dn_blkptr->data blocks */
+	uint8_t dn_nblkptr;		/* length of dn_blkptr */
+	uint8_t dn_bonustype;		/* type of data in bonus buffer */
+	uint8_t	dn_checksum;		/* ZIO_CHECKSUM type */
+	uint8_t	dn_compress;		/* ZIO_COMPRESS type */
+	uint8_t dn_flags;		/* DNODE_FLAG_* */
+	uint16_t dn_datablkszsec;	/* data block size in 512b sectors */
+	uint16_t dn_bonuslen;		/* length of dn_bonus */
+	uint8_t dn_pad2[4];
+
+	/* accounting is protected by dn_dirty_mtx */
+	uint64_t dn_maxblkid;		/* largest allocated block ID */
+	uint64_t dn_used;		/* bytes (or sectors) of disk space */
+
+	uint64_t dn_pad3[4];
+
+	blkptr_t dn_blkptr[1];
+	uint8_t dn_bonus[DN_MAX_BONUSLEN - sizeof(blkptr_t)];
+	blkptr_t dn_spill;
+} dnode_phys_t;
+
+#endif	/* _SYS_DNODE_H */
diff --git a/qemu/roms/u-boot/include/zfs/dsl_dataset.h b/qemu/roms/u-boot/include/zfs/dsl_dataset.h
new file mode 100644
index 000000000..237c2d7cc
--- /dev/null
+++ b/qemu/roms/u-boot/include/zfs/dsl_dataset.h
@@ -0,0 +1,41 @@
+/*
+ *  GRUB  --  GRand Unified Bootloader
+ *  Copyright (C) 1999,2000,2001,2002,2003,2004  Free Software Foundation, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/*
+ * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SYS_DSL_DATASET_H
+#define	_SYS_DSL_DATASET_H
+
+typedef struct dsl_dataset_phys {
+	uint64_t ds_dir_obj;
+	uint64_t ds_prev_snap_obj;
+	uint64_t ds_prev_snap_txg;
+	uint64_t ds_next_snap_obj;
+	uint64_t ds_snapnames_zapobj;	/* zap obj of snaps; ==0 for snaps */
+	uint64_t ds_num_children;	/* clone/snap children; ==0 for head */
+	uint64_t ds_creation_time;	/* seconds since 1970 */
+	uint64_t ds_creation_txg;
+	uint64_t ds_deadlist_obj;
+	uint64_t ds_used_bytes;
+	uint64_t ds_compressed_bytes;
+	uint64_t ds_uncompressed_bytes;
+	uint64_t ds_unique_bytes;	/* only relevant to snapshots */
+	/*
+	 * The ds_fsid_guid is a 56-bit ID that can change to avoid
+	 * collisions.  The ds_guid is a 64-bit ID that will never
+	 * change, so there is a small probability that it will collide.
+	 */
+	uint64_t ds_fsid_guid;
+	uint64_t ds_guid;
+	uint64_t ds_flags;
+	blkptr_t ds_bp;
+	uint64_t ds_pad[8]; /* pad out to 320 bytes for good measure */
+} dsl_dataset_phys_t;
+
+#endif /* _SYS_DSL_DATASET_H */
diff --git a/qemu/roms/u-boot/include/zfs/dsl_dir.h b/qemu/roms/u-boot/include/zfs/dsl_dir.h
new file mode 100644
index 000000000..7b3ca8af1
--- /dev/null
+++ b/qemu/roms/u-boot/include/zfs/dsl_dir.h
@@ -0,0 +1,37 @@
+/*
+ *  GRUB  --  GRand Unified Bootloader
+ *  Copyright (C) 1999,2000,2001,2002,2003,2004  Free Software Foundation, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/*
+ * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SYS_DSL_DIR_H
+#define	_SYS_DSL_DIR_H
+
+typedef struct dsl_dir_phys {
+	uint64_t dd_creation_time; /* not actually used */
+	uint64_t dd_head_dataset_obj;
+	uint64_t dd_parent_obj;
+	uint64_t dd_clone_parent_obj;
+	uint64_t dd_child_dir_zapobj;
+	/*
+	 * how much space our children are accounting for; for leaf
+	 * datasets, == physical space used by fs + snaps
+	 */
+	uint64_t dd_used_bytes;
+	uint64_t dd_compressed_bytes;
+	uint64_t dd_uncompressed_bytes;
+	/* Administrative quota setting */
+	uint64_t dd_quota;
+	/* Administrative reservation setting */
+	uint64_t dd_reserved;
+	uint64_t dd_props_zapobj;
+	uint64_t dd_deleg_zapobj;	/* dataset permissions */
+	uint64_t dd_pad[20]; /* pad out to 256 bytes for good measure */
+} dsl_dir_phys_t;
+
+#endif /* _SYS_DSL_DIR_H */
diff --git a/qemu/roms/u-boot/include/zfs/sa_impl.h b/qemu/roms/u-boot/include/zfs/sa_impl.h
new file mode 100644
index 000000000..e729e59ed
--- /dev/null
+++ b/qemu/roms/u-boot/include/zfs/sa_impl.h
@@ -0,0 +1,23 @@
+/*
+ *  GRUB  --  GRand Unified Bootloader
+ *  Copyright (C) 1999,2000,2001,2002,2003,2004  Free Software Foundation, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/*
+ * Copyright 2010 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+#ifndef	_SYS_SA_IMPL_H
+#define	_SYS_SA_IMPL_H
+
+typedef struct sa_hdr_phys {
+	uint32_t sa_magic;
+	uint16_t sa_layout_info;
+	uint16_t sa_lengths[1];
+} sa_hdr_phys_t;
+
+#define	SA_HDR_SIZE(hdr)	BF32_GET_SB(hdr->sa_layout_info, 10, 16, 3, 0)
+#define	SA_SIZE_OFFSET	0x8
+
+#endif	/* _SYS_SA_IMPL_H */
diff --git a/qemu/roms/u-boot/include/zfs/spa.h b/qemu/roms/u-boot/include/zfs/spa.h
new file mode 100644
index 000000000..eb54d906b
--- /dev/null
+++ b/qemu/roms/u-boot/include/zfs/spa.h
@@ -0,0 +1,280 @@
+/*
+ *  GRUB  --  GRand Unified Bootloader
+ *  Copyright (C) 1999,2000,2001,2002,2003,2004  Free Software Foundation, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/*
+ * Copyright (c) 2008, 2011, Oracle and/or its affiliates. All rights reserved.
+ */
+
+#ifndef ZFS_SPA_HEADER
+#define	ZFS_SPA_HEADER 1
+
+
+/*
+ * General-purpose 32-bit and 64-bit bitfield encodings.
+ */
+#define	BF32_DECODE(x, low, len)	P2PHASE((x) >> (low), 1U << (len))
+#define	BF64_DECODE(x, low, len)	P2PHASE((x) >> (low), 1ULL << (len))
+#define	BF32_ENCODE(x, low, len)	(P2PHASE((x), 1U << (len)) << (low))
+#define	BF64_ENCODE(x, low, len)	(P2PHASE((x), 1ULL << (len)) << (low))
+
+#define	BF32_GET(x, low, len)		BF32_DECODE(x, low, len)
+#define	BF64_GET(x, low, len)		BF64_DECODE(x, low, len)
+
+#define	BF32_SET(x, low, len, val)						\
+	((x) ^= BF32_ENCODE((x >> low) ^ (val), low, len))
+#define	BF64_SET(x, low, len, val)						\
+	((x) ^= BF64_ENCODE((x >> low) ^ (val), low, len))
+
+#define	BF32_GET_SB(x, low, len, shift, bias)		\
+	((BF32_GET(x, low, len) + (bias)) << (shift))
+#define	BF64_GET_SB(x, low, len, shift, bias)		\
+	((BF64_GET(x, low, len) + (bias)) << (shift))
+
+#define	BF32_SET_SB(x, low, len, shift, bias, val)		\
+	BF32_SET(x, low, len, ((val) >> (shift)) - (bias))
+#define	BF64_SET_SB(x, low, len, shift, bias, val)		\
+	BF64_SET(x, low, len, ((val) >> (shift)) - (bias))
+
+/*
+ * We currently support nine block sizes, from 512 bytes to 128K.
+ * We could go higher, but the benefits are near-zero and the cost
+ * of COWing a giant block to modify one byte would become excessive.
+ */
+#define	SPA_MINBLOCKSHIFT	9
+#define	SPA_MAXBLOCKSHIFT	17
+#define	SPA_MINBLOCKSIZE	(1ULL << SPA_MINBLOCKSHIFT)
+#define	SPA_MAXBLOCKSIZE	(1ULL << SPA_MAXBLOCKSHIFT)
+
+#define	SPA_BLOCKSIZES		(SPA_MAXBLOCKSHIFT - SPA_MINBLOCKSHIFT + 1)
+
+/*
+ * Size of block to hold the configuration data (a packed nvlist)
+ */
+#define	SPA_CONFIG_BLOCKSIZE	(1 << 14)
+
+/*
+ * The DVA size encodings for LSIZE and PSIZE support blocks up to 32MB.
+ * The ASIZE encoding should be at least 64 times larger (6 more bits)
+ * to support up to 4-way RAID-Z mirror mode with worst-case gang block
+ * overhead, three DVAs per bp, plus one more bit in case we do anything
+ * else that expands the ASIZE.
+ */
+#define	SPA_LSIZEBITS		16	/* LSIZE up to 32M (2^16 * 512)	*/
+#define	SPA_PSIZEBITS		16	/* PSIZE up to 32M (2^16 * 512)	*/
+#define	SPA_ASIZEBITS		24	/* ASIZE up to 64 times larger	*/
+
+/*
+ * All SPA data is represented by 128-bit data virtual addresses (DVAs).
+ * The members of the dva_t should be considered opaque outside the SPA.
+ */
+typedef struct dva {
+	uint64_t	dva_word[2];
+} dva_t;
+
+/*
+ * Each block has a 256-bit checksum -- strong enough for cryptographic hashes.
+ */
+typedef struct zio_cksum {
+	uint64_t	zc_word[4];
+} zio_cksum_t;
+
+/*
+ * Each block is described by its DVAs, time of birth, checksum, etc.
+ * The word-by-word, bit-by-bit layout of the blkptr is as follows:
+ *
+ *	64	56	48	40	32	24	16	8	0
+ *	+-------+-------+-------+-------+-------+-------+-------+-------+
+ * 0	|		vdev1		| GRID	|	  ASIZE		|
+ *	+-------+-------+-------+-------+-------+-------+-------+-------+
+ * 1	|G|			 offset1				|
+ *	+-------+-------+-------+-------+-------+-------+-------+-------+
+ * 2	|		vdev2		| GRID	|	  ASIZE		|
+ *	+-------+-------+-------+-------+-------+-------+-------+-------+
+ * 3	|G|			 offset2				|
+ *	+-------+-------+-------+-------+-------+-------+-------+-------+
+ * 4	|		vdev3		| GRID	|	  ASIZE		|
+ *	+-------+-------+-------+-------+-------+-------+-------+-------+
+ * 5	|G|			 offset3				|
+ *	+-------+-------+-------+-------+-------+-------+-------+-------+
+ * 6	|BDX|lvl| type	| cksum | comp	|	  PSIZE	|	  LSIZE	|
+ *	+-------+-------+-------+-------+-------+-------+-------+-------+
+ * 7	|			padding					|
+ *	+-------+-------+-------+-------+-------+-------+-------+-------+
+ * 8	|			padding					|
+ *	+-------+-------+-------+-------+-------+-------+-------+-------+
+ * 9	|			physical birth txg			|
+ *	+-------+-------+-------+-------+-------+-------+-------+-------+
+ * a	|			logical birth txg			|
+ *	+-------+-------+-------+-------+-------+-------+-------+-------+
+ * b	|			fill count				|
+ *	+-------+-------+-------+-------+-------+-------+-------+-------+
+ * c	|			checksum[0]				|
+ *	+-------+-------+-------+-------+-------+-------+-------+-------+
+ * d	|			checksum[1]				|
+ *	+-------+-------+-------+-------+-------+-------+-------+-------+
+ * e	|			checksum[2]				|
+ *	+-------+-------+-------+-------+-------+-------+-------+-------+
+ * f	|			checksum[3]				|
+ *	+-------+-------+-------+-------+-------+-------+-------+-------+
+ *
+ * Legend:
+ *
+ * vdev		virtual device ID
+ * offset	offset into virtual device
+ * LSIZE	logical size
+ * PSIZE	physical size (after compression)
+ * ASIZE	allocated size (including RAID-Z parity and gang block headers)
+ * GRID		RAID-Z layout information (reserved for future use)
+ * cksum	checksum function
+ * comp		compression function
+ * G		gang block indicator
+ * B		byteorder (endianness)
+ * D		dedup
+ * X		unused
+ * lvl		level of indirection
+ * type		DMU object type
+ * phys birth	txg of block allocation; zero if same as logical birth txg
+ * log. birth	transaction group in which the block was logically born
+ * fill count	number of non-zero blocks under this bp
+ * checksum[4]	256-bit checksum of the data this bp describes
+ */
+#define	SPA_BLKPTRSHIFT	7		/* blkptr_t is 128 bytes	*/
+#define	SPA_DVAS_PER_BP	3		/* Number of DVAs in a bp	*/
+
+typedef struct blkptr {
+	dva_t		blk_dva[SPA_DVAS_PER_BP]; /* Data Virtual Addresses */
+	uint64_t	blk_prop;	/* size, compression, type, etc		*/
+	uint64_t	blk_pad[2];	/* Extra space for the future		*/
+	uint64_t	blk_phys_birth;	/* txg when block was allocated		*/
+	uint64_t	blk_birth;	/* transaction group at birth		*/
+	uint64_t	blk_fill;	/* fill count				*/
+	zio_cksum_t	blk_cksum;	/* 256-bit checksum			*/
+} blkptr_t;
+
+/*
+ * Macros to get and set fields in a bp or DVA.
+ */
+#define	DVA_GET_ASIZE(dva)											\
+	BF64_GET_SB((dva)->dva_word[0], 0, 24, SPA_MINBLOCKSHIFT, 0)
+#define	DVA_SET_ASIZE(dva, x)										\
+	BF64_SET_SB((dva)->dva_word[0], 0, 24, SPA_MINBLOCKSHIFT, 0, x)
+
+#define	DVA_GET_GRID(dva)	BF64_GET((dva)->dva_word[0], 24, 8)
+#define	DVA_SET_GRID(dva, x)	BF64_SET((dva)->dva_word[0], 24, 8, x)
+
+#define	DVA_GET_VDEV(dva)	BF64_GET((dva)->dva_word[0], 32, 32)
+#define	DVA_SET_VDEV(dva, x)	BF64_SET((dva)->dva_word[0], 32, 32, x)
+
+#define	DVA_GET_GANG(dva)	BF64_GET((dva)->dva_word[1], 63, 1)
+#define	DVA_SET_GANG(dva, x)	BF64_SET((dva)->dva_word[1], 63, 1, x)
+
+#define	BP_GET_LSIZE(bp)										\
+	BF64_GET_SB((bp)->blk_prop, 0, 16, SPA_MINBLOCKSHIFT, 1)
+#define	BP_SET_LSIZE(bp, x)										\
+	BF64_SET_SB((bp)->blk_prop, 0, 16, SPA_MINBLOCKSHIFT, 1, x)
+
+#define	BP_GET_COMPRESS(bp)		BF64_GET((bp)->blk_prop, 32, 8)
+#define	BP_SET_COMPRESS(bp, x)		BF64_SET((bp)->blk_prop, 32, 8, x)
+
+#define	BP_GET_CHECKSUM(bp)		BF64_GET((bp)->blk_prop, 40, 8)
+#define	BP_SET_CHECKSUM(bp, x)		BF64_SET((bp)->blk_prop, 40, 8, x)
+
+#define	BP_GET_TYPE(bp)			BF64_GET((bp)->blk_prop, 48, 8)
+#define	BP_SET_TYPE(bp, x)		BF64_SET((bp)->blk_prop, 48, 8, x)
+
+#define	BP_GET_LEVEL(bp)		BF64_GET((bp)->blk_prop, 56, 5)
+#define	BP_SET_LEVEL(bp, x)		BF64_SET((bp)->blk_prop, 56, 5, x)
+
+#define	BP_GET_PROP_BIT_61(bp)		BF64_GET((bp)->blk_prop, 61, 1)
+#define	BP_SET_PROP_BIT_61(bp, x)	BF64_SET((bp)->blk_prop, 61, 1, x)
+
+#define	BP_GET_DEDUP(bp)		BF64_GET((bp)->blk_prop, 62, 1)
+#define	BP_SET_DEDUP(bp, x)		BF64_SET((bp)->blk_prop, 62, 1, x)
+
+#define	BP_GET_BYTEORDER(bp)		(0 - BF64_GET((bp)->blk_prop, 63, 1))
+#define	BP_SET_BYTEORDER(bp, x)		BF64_SET((bp)->blk_prop, 63, 1, x)
+
+#define	BP_PHYSICAL_BIRTH(bp)										\
+	((bp)->blk_phys_birth ? (bp)->blk_phys_birth : (bp)->blk_birth)
+
+#define	BP_SET_BIRTH(bp, logical, physical)								\
+	{																	\
+		(bp)->blk_birth = (logical);									\
+		(bp)->blk_phys_birth = ((logical) == (physical) ? 0 : (physical)); \
+	}
+
+#define	BP_GET_ASIZE(bp)												\
+	(DVA_GET_ASIZE(&(bp)->blk_dva[0]) + DVA_GET_ASIZE(&(bp)->blk_dva[1]) + \
+	 DVA_GET_ASIZE(&(bp)->blk_dva[2]))
+
+#define	BP_GET_UCSIZE(bp)												\
+	((BP_GET_LEVEL(bp) > 0 || dmu_ot[BP_GET_TYPE(bp)].ot_metadata) ?	\
+	 BP_GET_PSIZE(bp) : BP_GET_LSIZE(bp));
+
+#define	BP_GET_NDVAS(bp)						\
+	(!!DVA_GET_ASIZE(&(bp)->blk_dva[0]) +		\
+	 !!DVA_GET_ASIZE(&(bp)->blk_dva[1]) +		\
+	 !!DVA_GET_ASIZE(&(bp)->blk_dva[2]))
+
+#define	BP_COUNT_GANG(bp)						\
+	(DVA_GET_GANG(&(bp)->blk_dva[0]) +			\
+	 DVA_GET_GANG(&(bp)->blk_dva[1]) +			\
+	 DVA_GET_GANG(&(bp)->blk_dva[2]))
+
+#define	DVA_EQUAL(dva1, dva2)						\
+	((dva1)->dva_word[1] == (dva2)->dva_word[1] &&	\
+	 (dva1)->dva_word[0] == (dva2)->dva_word[0])
+
+#define	BP_EQUAL(bp1, bp2)									\
+	(BP_PHYSICAL_BIRTH(bp1) == BP_PHYSICAL_BIRTH(bp2) &&	\
+	 DVA_EQUAL(&(bp1)->blk_dva[0], &(bp2)->blk_dva[0]) &&	\
+	 DVA_EQUAL(&(bp1)->blk_dva[1], &(bp2)->blk_dva[1]) &&	\
+	 DVA_EQUAL(&(bp1)->blk_dva[2], &(bp2)->blk_dva[2]))
+
+#define	ZIO_CHECKSUM_EQUAL(zc1, zc2)				\
+	(0 == (((zc1).zc_word[0] - (zc2).zc_word[0]) |	\
+		   ((zc1).zc_word[1] - (zc2).zc_word[1]) |	\
+		   ((zc1).zc_word[2] - (zc2).zc_word[2]) |	\
+		   ((zc1).zc_word[3] - (zc2).zc_word[3])))
+
+#define	DVA_IS_VALID(dva)	(DVA_GET_ASIZE(dva) != 0)
+
+#define	ZIO_SET_CHECKSUM(zcp, w0, w1, w2, w3)	\
+	{											\
+		(zcp)->zc_word[0] = w0;					\
+		(zcp)->zc_word[1] = w1;					\
+		(zcp)->zc_word[2] = w2;					\
+		(zcp)->zc_word[3] = w3;					\
+	}
+
+#define	BP_IDENTITY(bp)		(&(bp)->blk_dva[0])
+#define	BP_IS_GANG(bp)		DVA_GET_GANG(BP_IDENTITY(bp))
+#define	BP_IS_HOLE(bp)		((bp)->blk_birth == 0)
+
+/* BP_IS_RAIDZ(bp) assumes no block compression */
+#define	BP_IS_RAIDZ(bp)		(DVA_GET_ASIZE(&(bp)->blk_dva[0]) > \
+							 BP_GET_PSIZE(bp))
+
+#define	BP_ZERO(bp)										\
+	{													\
+		(bp)->blk_dva[0].dva_word[0] = 0;				\
+		(bp)->blk_dva[0].dva_word[1] = 0;				\
+		(bp)->blk_dva[1].dva_word[0] = 0;				\
+		(bp)->blk_dva[1].dva_word[1] = 0;				\
+		(bp)->blk_dva[2].dva_word[0] = 0;				\
+		(bp)->blk_dva[2].dva_word[1] = 0;				\
+		(bp)->blk_prop = 0;								\
+		(bp)->blk_pad[0] = 0;							\
+		(bp)->blk_pad[1] = 0;							\
+		(bp)->blk_phys_birth = 0;						\
+		(bp)->blk_birth = 0;							\
+		(bp)->blk_fill = 0;								\
+		ZIO_SET_CHECKSUM(&(bp)->blk_cksum, 0, 0, 0, 0);	\
+	}
+
+#define	BP_SPRINTF_LEN	320
+
+#endif	/* ! ZFS_SPA_HEADER */
diff --git a/qemu/roms/u-boot/include/zfs/uberblock_impl.h b/qemu/roms/u-boot/include/zfs/uberblock_impl.h
new file mode 100644
index 000000000..e19eee598
--- /dev/null
+++ b/qemu/roms/u-boot/include/zfs/uberblock_impl.h
@@ -0,0 +1,45 @@
+/*
+ *  GRUB  --  GRand Unified Bootloader
+ *  Copyright (C) 1999,2000,2001,2002,2003,2004  Free Software Foundation, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/*
+ * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _SYS_UBERBLOCK_IMPL_H
+#define	_SYS_UBERBLOCK_IMPL_H
+
+#define UBMAX(a, b) ((a) > (b) ? (a) : (b))
+
+/*
+ * The uberblock version is incremented whenever an incompatible on-disk
+ * format change is made to the SPA, DMU, or ZAP.
+ *
+ * Note: the first two fields should never be moved.  When a storage pool
+ * is opened, the uberblock must be read off the disk before the version
+ * can be checked.	If the ub_version field is moved, we may not detect
+ * version mismatch.  If the ub_magic field is moved, applications that
+ * expect the magic number in the first word won't work.
+ */
+#define	UBERBLOCK_MAGIC		0x00bab10c		/* oo-ba-bloc!	*/
+#define	UBERBLOCK_SHIFT		10			/* up to 1K	*/
+
+typedef struct uberblock {
+	uint64_t	ub_magic;	/* UBERBLOCK_MAGIC		*/
+	uint64_t	ub_version;	/* ZFS_VERSION			*/
+	uint64_t	ub_txg;		/* txg of last sync		*/
+	uint64_t	ub_guid_sum;	/* sum of all vdev guids	*/
+	uint64_t	ub_timestamp;	/* UTC time of last sync	*/
+	blkptr_t	ub_rootbp;	/* MOS objset_phys_t		*/
+} uberblock_t;
+
+#define	VDEV_UBERBLOCK_SHIFT(as)	UBMAX(as, UBERBLOCK_SHIFT)
+#define	UBERBLOCK_SIZE(as)		(1ULL << VDEV_UBERBLOCK_SHIFT(as))
+
+/* Number of uberblocks that can fit in the ring at a given ashift */
+#define UBERBLOCK_COUNT(as) (VDEV_UBERBLOCK_RING >> VDEV_UBERBLOCK_SHIFT(as))
+
+#endif	/* _SYS_UBERBLOCK_IMPL_H */
diff --git a/qemu/roms/u-boot/include/zfs/vdev_impl.h b/qemu/roms/u-boot/include/zfs/vdev_impl.h
new file mode 100644
index 000000000..9acc23834
--- /dev/null
+++ b/qemu/roms/u-boot/include/zfs/vdev_impl.h
@@ -0,0 +1,58 @@
+/*
+ *  GRUB  --  GRand Unified Bootloader
+ *  Copyright (C) 1999,2000,2001,2002,2003,2004  Free Software Foundation, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/*
+ * Copyright 2010 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _SYS_VDEV_IMPL_H
+#define	_SYS_VDEV_IMPL_H
+
+#define	VDEV_SKIP_SIZE		(8 << 10)
+#define	VDEV_BOOT_HEADER_SIZE	(8 << 10)
+#define	VDEV_PHYS_SIZE		(112 << 10)
+#define	VDEV_UBERBLOCK_RING	(128 << 10)
+
+/* ZFS boot block */
+#define	VDEV_BOOT_MAGIC		0x2f5b007b10cULL
+#define	VDEV_BOOT_VERSION	1		/* version number	*/
+
+typedef struct vdev_boot_header {
+	uint64_t	vb_magic;		/* VDEV_BOOT_MAGIC	*/
+	uint64_t	vb_version;		/* VDEV_BOOT_VERSION	*/
+	uint64_t	vb_offset;		/* start offset	(bytes) */
+	uint64_t	vb_size;		/* size (bytes)		*/
+	char		vb_pad[VDEV_BOOT_HEADER_SIZE - 4 * sizeof(uint64_t)];
+} vdev_boot_header_t;
+
+typedef struct vdev_phys {
+	char		vp_nvlist[VDEV_PHYS_SIZE - sizeof(zio_eck_t)];
+	zio_eck_t	vp_zbt;
+} vdev_phys_t;
+
+typedef struct vdev_label {
+	char		vl_pad[VDEV_SKIP_SIZE];			/*   8K	*/
+	vdev_boot_header_t vl_boot_header;			/*   8K	*/
+	vdev_phys_t	vl_vdev_phys;				/* 112K	*/
+	char		vl_uberblock[VDEV_UBERBLOCK_RING];	/* 128K	*/
+} vdev_label_t;							/* 256K total */
+
+/*
+ * Size and offset of embedded boot loader region on each label.
+ * The total size of the first two labels plus the boot area is 4MB.
+ */
+#define	VDEV_BOOT_OFFSET	(2 * sizeof(vdev_label_t))
+#define	VDEV_BOOT_SIZE		(7ULL << 19)			/* 3.5M	*/
+
+/*
+ * Size of label regions at the start and end of each leaf device.
+ */
+#define	VDEV_LABEL_START_SIZE	(2 * sizeof(vdev_label_t) + VDEV_BOOT_SIZE)
+#define	VDEV_LABEL_END_SIZE	(2 * sizeof(vdev_label_t))
+#define	VDEV_LABELS		4
+
+#endif	/* _SYS_VDEV_IMPL_H */
diff --git a/qemu/roms/u-boot/include/zfs/zap_impl.h b/qemu/roms/u-boot/include/zfs/zap_impl.h
new file mode 100644
index 000000000..431fd2dbf
--- /dev/null
+++ b/qemu/roms/u-boot/include/zfs/zap_impl.h
@@ -0,0 +1,99 @@
+/*
+ *  GRUB  --  GRand Unified Bootloader
+ *  Copyright (C) 1999,2000,2001,2002,2003,2004  Free Software Foundation, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/*
+ * Copyright (c) 2008, 2011, Oracle and/or its affiliates. All rights reserved.
+ */
+
+#ifndef	_SYS_ZAP_IMPL_H
+#define	_SYS_ZAP_IMPL_H
+
+#define	ZAP_MAGIC 0x2F52AB2ABULL
+
+#define	ZAP_HASHBITS		28
+#define	MZAP_ENT_LEN		64
+#define	MZAP_NAME_LEN		(MZAP_ENT_LEN - 8 - 4 - 2)
+#define	MZAP_MAX_BLKSHIFT	SPA_MAXBLOCKSHIFT
+#define	MZAP_MAX_BLKSZ		(1 << MZAP_MAX_BLKSHIFT)
+
+typedef struct mzap_ent_phys {
+	uint64_t mze_value;
+	uint32_t mze_cd;
+	uint16_t mze_pad;	/* in case we want to chain them someday */
+	char mze_name[MZAP_NAME_LEN];
+} mzap_ent_phys_t;
+
+typedef struct mzap_phys {
+	uint64_t mz_block_type;	/* ZBT_MICRO */
+	uint64_t mz_salt;
+	uint64_t mz_pad[6];
+	mzap_ent_phys_t mz_chunk[1];
+	/* actually variable size depending on block size */
+} mzap_phys_t;
+
+/*
+ * The (fat) zap is stored in one object. It is an array of
+ * 1<<FZAP_BLOCK_SHIFT byte blocks. The layout looks like one of:
+ *
+ * ptrtbl fits in first block:
+ *	[zap_phys_t zap_ptrtbl_shift < 6] [zap_leaf_t] ...
+ *
+ * ptrtbl too big for first block:
+ *	[zap_phys_t zap_ptrtbl_shift >= 6] [zap_leaf_t] [ptrtbl] ...
+ *
+ */
+
+#define	ZBT_LEAF		((1ULL << 63) + 0)
+#define	ZBT_HEADER		((1ULL << 63) + 1)
+#define	ZBT_MICRO		((1ULL << 63) + 3)
+/* any other values are ptrtbl blocks */
+
+/*
+ * the embedded pointer table takes up half a block:
+ * block size / entry size (2^3) / 2
+ */
+#define	ZAP_EMBEDDED_PTRTBL_SHIFT(zap) (FZAP_BLOCK_SHIFT(zap) - 3 - 1)
+
+/*
+ * The embedded pointer table starts half-way through the block.  Since
+ * the pointer table itself is half the block, it starts at (64-bit)
+ * word number (1<<ZAP_EMBEDDED_PTRTBL_SHIFT(zap)).
+ */
+#define	ZAP_EMBEDDED_PTRTBL_ENT(zap, idx) \
+	((uint64_t *)(zap)->zap_f.zap_phys) \
+	[(idx) + (1<<ZAP_EMBEDDED_PTRTBL_SHIFT(zap))]
+
+/*
+ * TAKE NOTE:
+ * If zap_phys_t is modified, zap_byteswap() must be modified.
+ */
+typedef struct zap_phys {
+	uint64_t zap_block_type;	/* ZBT_HEADER */
+	uint64_t zap_magic;		/* ZAP_MAGIC */
+
+	struct zap_table_phys {
+		uint64_t zt_blk;	/* starting block number */
+		uint64_t zt_numblks;	/* number of blocks */
+		uint64_t zt_shift;	/* bits to index it */
+		uint64_t zt_nextblk;	/* next (larger) copy start block */
+		uint64_t zt_blks_copied; /* number source blocks copied */
+	} zap_ptrtbl;
+
+	uint64_t zap_freeblk;		/* the next free block */
+	uint64_t zap_num_leafs;		/* number of leafs */
+	uint64_t zap_num_entries;	/* number of entries */
+	uint64_t zap_salt;		/* salt to stir into hash function */
+	uint64_t zap_normflags;		/* flags for u8_textprep_str() */
+	uint64_t zap_flags;		/* zap_flag_t */
+	/*
+	 * This structure is followed by padding, and then the embedded
+	 * pointer table.  The embedded pointer table takes up second
+	 * half of the block.  It is accessed using the
+	 * ZAP_EMBEDDED_PTRTBL_ENT() macro.
+	 */
+} zap_phys_t;
+
+#endif /* _SYS_ZAP_IMPL_H */
diff --git a/qemu/roms/u-boot/include/zfs/zap_leaf.h b/qemu/roms/u-boot/include/zfs/zap_leaf.h
new file mode 100644
index 000000000..5836f2272
--- /dev/null
+++ b/qemu/roms/u-boot/include/zfs/zap_leaf.h
@@ -0,0 +1,91 @@
+/*
+ *  GRUB  --  GRand Unified Bootloader
+ *  Copyright (C) 1999,2000,2001,2002,2003,2004  Free Software Foundation, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/*
+ * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SYS_ZAP_LEAF_H
+#define	_SYS_ZAP_LEAF_H
+
+#define	ZAP_LEAF_MAGIC 0x2AB1EAF
+
+/* chunk size = 24 bytes */
+#define	ZAP_LEAF_CHUNKSIZE 24
+
+/*
+ * The amount of space within the chunk available for the array is:
+ * chunk size - space for type (1) - space for next pointer (2)
+ */
+#define	ZAP_LEAF_ARRAY_BYTES (ZAP_LEAF_CHUNKSIZE - 3)
+
+typedef enum zap_chunk_type {
+	ZAP_CHUNK_FREE = 253,
+	ZAP_CHUNK_ENTRY = 252,
+	ZAP_CHUNK_ARRAY = 251,
+	ZAP_CHUNK_TYPE_MAX = 250
+} zap_chunk_type_t;
+
+/*
+ * TAKE NOTE:
+ * If zap_leaf_phys_t is modified, zap_leaf_byteswap() must be modified.
+ */
+typedef struct zap_leaf_phys {
+	struct zap_leaf_header {
+		uint64_t lh_block_type;		/* ZBT_LEAF */
+		uint64_t lh_pad1;
+		uint64_t lh_prefix;		/* hash prefix of this leaf */
+		uint32_t lh_magic;		/* ZAP_LEAF_MAGIC */
+		uint16_t lh_nfree;		/* number free chunks */
+		uint16_t lh_nentries;		/* number of entries */
+		uint16_t lh_prefix_len;		/* num bits used to id this */
+
+		/* above is accessable to zap, below is zap_leaf private */
+
+		uint16_t lh_freelist;		/* chunk head of free list */
+		uint8_t lh_pad2[12];
+	} l_hdr; /* 2 24-byte chunks */
+
+	/*
+	 * The header is followed by a hash table with
+	 * ZAP_LEAF_HASH_NUMENTRIES(zap) entries.  The hash table is
+	 * followed by an array of ZAP_LEAF_NUMCHUNKS(zap)
+	 * zap_leaf_chunk structures.  These structures are accessed
+	 * with the ZAP_LEAF_CHUNK() macro.
+	 */
+
+	uint16_t l_hash[1];
+} zap_leaf_phys_t;
+
+typedef union zap_leaf_chunk {
+	struct zap_leaf_entry {
+		uint8_t le_type;		/* always ZAP_CHUNK_ENTRY */
+		uint8_t le_int_size;		/* size of ints */
+		uint16_t le_next;		/* next entry in hash chain */
+		uint16_t le_name_chunk;		/* first chunk of the name */
+		uint16_t le_name_length;	/* bytes in name, incl null */
+		uint16_t le_value_chunk;	/* first chunk of the value */
+		uint16_t le_value_length;	/* value length in ints */
+		uint32_t le_cd;		/* collision differentiator */
+		uint64_t le_hash;		/* hash value of the name */
+	} l_entry;
+	struct zap_leaf_array {
+		uint8_t la_type;		/* always ZAP_CHUNK_ARRAY */
+		union {
+			uint8_t la_array[ZAP_LEAF_ARRAY_BYTES];
+			uint64_t la_array64;
+		} __attribute__ ((packed));
+		uint16_t la_next;		/* next blk or CHAIN_END */
+	} l_array;
+	struct zap_leaf_free {
+		uint8_t lf_type;		/* always ZAP_CHUNK_FREE */
+		uint8_t lf_pad[ZAP_LEAF_ARRAY_BYTES];
+		uint16_t lf_next;	/* next in free list, or CHAIN_END */
+	} l_free;
+} zap_leaf_chunk_t;
+
+#endif /* _SYS_ZAP_LEAF_H */
diff --git a/qemu/roms/u-boot/include/zfs/zfs.h b/qemu/roms/u-boot/include/zfs/zfs.h
new file mode 100644
index 000000000..8912732ab
--- /dev/null
+++ b/qemu/roms/u-boot/include/zfs/zfs.h
@@ -0,0 +1,110 @@
+/*
+ *  GRUB  --  GRand Unified Bootloader
+ *  Copyright (C) 1999,2000,2001,2002,2003,2004  Free Software Foundation, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/*
+ * Copyright (c) 2007, 2011, Oracle and/or its affiliates. All rights reserved.
+ */
+
+#ifndef	GRUB_ZFS_HEADER
+#define	GRUB_ZFS_HEADER 1
+
+
+/*
+ * On-disk version number.
+ */
+#define	SPA_VERSION			28ULL
+
+/*
+ * The following are configuration names used in the nvlist describing a pool's
+ * configuration.
+ */
+#define	ZPOOL_CONFIG_VERSION		"version"
+#define	ZPOOL_CONFIG_POOL_NAME		"name"
+#define	ZPOOL_CONFIG_POOL_STATE		"state"
+#define	ZPOOL_CONFIG_POOL_TXG		"txg"
+#define	ZPOOL_CONFIG_POOL_GUID		"pool_guid"
+#define	ZPOOL_CONFIG_CREATE_TXG		"create_txg"
+#define	ZPOOL_CONFIG_TOP_GUID		"top_guid"
+#define	ZPOOL_CONFIG_VDEV_TREE		"vdev_tree"
+#define	ZPOOL_CONFIG_TYPE		"type"
+#define	ZPOOL_CONFIG_CHILDREN		"children"
+#define	ZPOOL_CONFIG_ID			"id"
+#define	ZPOOL_CONFIG_GUID		"guid"
+#define	ZPOOL_CONFIG_PATH		"path"
+#define	ZPOOL_CONFIG_DEVID		"devid"
+#define	ZPOOL_CONFIG_METASLAB_ARRAY	"metaslab_array"
+#define	ZPOOL_CONFIG_METASLAB_SHIFT	"metaslab_shift"
+#define	ZPOOL_CONFIG_ASHIFT		"ashift"
+#define	ZPOOL_CONFIG_ASIZE		"asize"
+#define	ZPOOL_CONFIG_DTL		"DTL"
+#define	ZPOOL_CONFIG_STATS		"stats"
+#define	ZPOOL_CONFIG_WHOLE_DISK		"whole_disk"
+#define	ZPOOL_CONFIG_ERRCOUNT		"error_count"
+#define	ZPOOL_CONFIG_NOT_PRESENT	"not_present"
+#define	ZPOOL_CONFIG_SPARES		"spares"
+#define	ZPOOL_CONFIG_IS_SPARE		"is_spare"
+#define	ZPOOL_CONFIG_NPARITY		"nparity"
+#define	ZPOOL_CONFIG_PHYS_PATH		"phys_path"
+#define	ZPOOL_CONFIG_L2CACHE		"l2cache"
+#define	ZPOOL_CONFIG_HOLE_ARRAY		"hole_array"
+#define	ZPOOL_CONFIG_VDEV_CHILDREN	"vdev_children"
+#define	ZPOOL_CONFIG_IS_HOLE		"is_hole"
+#define	ZPOOL_CONFIG_DDT_HISTOGRAM	"ddt_histogram"
+#define	ZPOOL_CONFIG_DDT_OBJ_STATS	"ddt_object_stats"
+#define	ZPOOL_CONFIG_DDT_STATS		"ddt_stats"
+/*
+ * The persistent vdev state is stored as separate values rather than a single
+ * 'vdev_state' entry.  This is because a device can be in multiple states, such
+ * as offline and degraded.
+ */
+#define	ZPOOL_CONFIG_OFFLINE		"offline"
+#define	ZPOOL_CONFIG_FAULTED		"faulted"
+#define	ZPOOL_CONFIG_DEGRADED		"degraded"
+#define	ZPOOL_CONFIG_REMOVED		"removed"
+
+#define	VDEV_TYPE_ROOT			"root"
+#define	VDEV_TYPE_MIRROR		"mirror"
+#define	VDEV_TYPE_REPLACING		"replacing"
+#define	VDEV_TYPE_RAIDZ			"raidz"
+#define	VDEV_TYPE_DISK			"disk"
+#define	VDEV_TYPE_FILE			"file"
+#define	VDEV_TYPE_MISSING		"missing"
+#define	VDEV_TYPE_HOLE			"hole"
+#define	VDEV_TYPE_SPARE			"spare"
+#define	VDEV_TYPE_L2CACHE		"l2cache"
+
+/*
+ * pool state.  The following states are written to disk as part of the normal
+ * SPA lifecycle: ACTIVE, EXPORTED, DESTROYED, SPARE, L2CACHE.  The remaining
+ * states are software abstractions used at various levels to communicate pool
+ * state.
+ */
+typedef enum pool_state {
+	POOL_STATE_ACTIVE = 0,		/* In active use		*/
+	POOL_STATE_EXPORTED,		/* Explicitly exported		*/
+	POOL_STATE_DESTROYED,		/* Explicitly destroyed		*/
+	POOL_STATE_SPARE,		/* Reserved for hot spare use	*/
+	POOL_STATE_L2CACHE,		/* Level 2 ARC device		*/
+	POOL_STATE_UNINITIALIZED,	/* Internal spa_t state		*/
+	POOL_STATE_UNAVAIL,		/* Internal libzfs state	*/
+	POOL_STATE_POTENTIALLY_ACTIVE	/* Internal libzfs state	*/
+} pool_state_t;
+
+struct zfs_data;
+
+int zfs_fetch_nvlist(device_t dev, char **nvlist);
+int zfs_getmdnobj(device_t dev, const char *fsfilename,
+			       uint64_t *mdnobj);
+
+char *zfs_nvlist_lookup_string(char *nvlist, char *name);
+char *zfs_nvlist_lookup_nvlist(char *nvlist, char *name);
+int zfs_nvlist_lookup_uint64(char *nvlist, char *name,
+				   uint64_t *out);
+char *zfs_nvlist_lookup_nvlist_array(char *nvlist, char *name,
+					   size_t index);
+int zfs_nvlist_lookup_nvlist_array_get_nelm(char *nvlist, char *name);
+
+#endif	/* ! GRUB_ZFS_HEADER */
diff --git a/qemu/roms/u-boot/include/zfs/zfs_acl.h b/qemu/roms/u-boot/include/zfs/zfs_acl.h
new file mode 100644
index 000000000..265736d59
--- /dev/null
+++ b/qemu/roms/u-boot/include/zfs/zfs_acl.h
@@ -0,0 +1,43 @@
+/*
+ *  GRUB  --  GRand Unified Bootloader
+ *  Copyright (C) 1999,2000,2001,2002,2003,2004  Free Software Foundation, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/*
+ * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SYS_FS_ZFS_ACL_H
+#define	_SYS_FS_ZFS_ACL_H
+
+typedef struct zfs_oldace {
+	uint32_t	z_fuid;		/* "who" */
+	uint32_t	z_access_mask;	/* access mask */
+	uint16_t	z_flags;	/* flags, i.e inheritance */
+	uint16_t	z_type;		/* type of entry allow/deny */
+} zfs_oldace_t;
+
+#define	ACE_SLOT_CNT	6
+
+typedef struct zfs_znode_acl_v0 {
+	uint64_t	z_acl_extern_obj;	  /* ext acl pieces */
+	uint32_t	z_acl_count;		  /* Number of ACEs */
+	uint16_t	z_acl_version;		  /* acl version */
+	uint16_t	z_acl_pad;		  /* pad */
+	zfs_oldace_t	z_ace_data[ACE_SLOT_CNT]; /* 6 standard ACEs */
+} zfs_znode_acl_v0_t;
+
+#define	ZFS_ACE_SPACE	(sizeof(zfs_oldace_t) * ACE_SLOT_CNT)
+
+typedef struct zfs_znode_acl {
+	uint64_t	z_acl_extern_obj;	  /* ext acl pieces */
+	uint32_t	z_acl_size;		  /* Number of bytes in ACL */
+	uint16_t	z_acl_version;		  /* acl version */
+	uint16_t	z_acl_count;		  /* ace count */
+	uint8_t	z_ace_data[ZFS_ACE_SPACE]; /* space for embedded ACEs */
+} zfs_znode_acl_t;
+
+
+#endif	/* _SYS_FS_ZFS_ACL_H */
diff --git a/qemu/roms/u-boot/include/zfs/zfs_znode.h b/qemu/roms/u-boot/include/zfs/zfs_znode.h
new file mode 100644
index 000000000..4a5e0f8d7
--- /dev/null
+++ b/qemu/roms/u-boot/include/zfs/zfs_znode.h
@@ -0,0 +1,59 @@
+/*
+ *  GRUB  --  GRand Unified Bootloader
+ *  Copyright (C) 1999,2000,2001,2002,2003,2004  Free Software Foundation, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/*
+ * Copyright 2010 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SYS_FS_ZFS_ZNODE_H
+#define	_SYS_FS_ZFS_ZNODE_H
+
+#include <zfs/zfs_acl.h>
+
+#define	MASTER_NODE_OBJ	1
+#define	ZFS_ROOT_OBJ		"ROOT"
+#define	ZPL_VERSION_STR		"VERSION"
+#define	ZFS_SA_ATTRS		"SA_ATTRS"
+
+#define	ZPL_VERSION		5ULL
+
+#define	ZFS_DIRENT_OBJ(de) BF64_GET(de, 0, 48)
+
+/*
+ * This is the persistent portion of the znode.  It is stored
+ * in the "bonus buffer" of the file.  Short symbolic links
+ * are also stored in the bonus buffer.
+ */
+typedef struct znode_phys {
+	uint64_t zp_atime[2];      /*  0 - last file access time */
+	uint64_t zp_mtime[2];	/* 16 - last file modification time */
+	uint64_t zp_ctime[2];	/* 32 - last file change time */
+	uint64_t zp_crtime[2];	/* 48 - creation time */
+	uint64_t zp_gen;		/* 64 - generation (txg of creation) */
+	uint64_t zp_mode;		/* 72 - file mode bits */
+	uint64_t zp_size;		/* 80 - size of file */
+	uint64_t zp_parent;	/* 88 - directory parent (`..') */
+	uint64_t zp_links;		/* 96 - number of links to file */
+	uint64_t zp_xattr;		/* 104 - DMU object for xattrs */
+	uint64_t zp_rdev;		/* 112 - dev_t for VBLK & VCHR files */
+	uint64_t zp_flags;		/* 120 - persistent flags */
+	uint64_t zp_uid;		/* 128 - file owner */
+	uint64_t zp_gid;		/* 136 - owning group */
+	uint64_t zp_pad[4];	/* 144 - future */
+	zfs_znode_acl_t zp_acl;		/* 176 - 263 ACL */
+	/*
+	 * Data may pad out any remaining bytes in the znode buffer, eg:
+	 *
+	 * |<---------------------- dnode_phys (512) ------------------------>|
+	 * |<-- dnode (192) --->|<----------- "bonus" buffer (320) ---------->|
+	 *			|<---- znode (264) ---->|<---- data (56) ---->|
+	 *
+	 * At present, we only use this space to store symbolic links.
+	 */
+} znode_phys_t;
+
+#endif	/* _SYS_FS_ZFS_ZNODE_H */
diff --git a/qemu/roms/u-boot/include/zfs/zil.h b/qemu/roms/u-boot/include/zfs/zil.h
new file mode 100644
index 000000000..7391c4628
--- /dev/null
+++ b/qemu/roms/u-boot/include/zfs/zil.h
@@ -0,0 +1,45 @@
+/*
+ *  GRUB  --  GRand Unified Bootloader
+ *  Copyright (C) 1999,2000,2001,2002,2003,2004  Free Software Foundation, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/*
+ * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SYS_ZIL_H
+#define	_SYS_ZIL_H
+
+/*
+ * Intent log format:
+ *
+ * Each objset has its own intent log.  The log header (zil_header_t)
+ * for objset N's intent log is kept in the Nth object of the SPA's
+ * intent_log objset.  The log header points to a chain of log blocks,
+ * each of which contains log records (i.e., transactions) followed by
+ * a log block trailer (zil_trailer_t).  The format of a log record
+ * depends on the record (or transaction) type, but all records begin
+ * with a common structure that defines the type, length, and txg.
+ */
+
+/*
+ * Intent log header - this on disk structure holds fields to manage
+ * the log.  All fields are 64 bit to easily handle cross architectures.
+ */
+typedef struct zil_header {
+	uint64_t zh_claim_txg;   /* txg in which log blocks were claimed */
+	uint64_t zh_replay_seq;  /* highest replayed sequence number */
+	blkptr_t zh_log;	/* log chain */
+	uint64_t zh_claim_seq;	/* highest claimed sequence number */
+	uint64_t zh_flags;	/* header flags */
+	uint64_t zh_pad[4];
+} zil_header_t;
+
+/*
+ * zh_flags bit settings
+ */
+#define	ZIL_REPLAY_NEEDED 0x1	/* replay needed - internal only */
+
+#endif	/* _SYS_ZIL_H */
diff --git a/qemu/roms/u-boot/include/zfs/zio.h b/qemu/roms/u-boot/include/zfs/zio.h
new file mode 100644
index 000000000..888a4d382
--- /dev/null
+++ b/qemu/roms/u-boot/include/zfs/zio.h
@@ -0,0 +1,80 @@
+/*
+ *  GRUB  --  GRand Unified Bootloader
+ *  Copyright (C) 1999,2000,2001,2002,2003,2004  Free Software Foundation, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/*
+ * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
+ */
+
+#ifndef _ZIO_H
+#define	_ZIO_H
+
+#include <zfs/spa.h>
+
+#define	ZEC_MAGIC	0x210da7ab10c7a11ULL	/* zio data bloc tail */
+
+typedef struct zio_eck {
+	uint64_t	zec_magic;	/* for validation, endianness	*/
+	zio_cksum_t	zec_cksum;	/* 256-bit checksum		*/
+} zio_eck_t;
+
+/*
+ * Gang block headers are self-checksumming and contain an array
+ * of block pointers.
+ */
+#define	SPA_GANGBLOCKSIZE	SPA_MINBLOCKSIZE
+#define	SPA_GBH_NBLKPTRS	((SPA_GANGBLOCKSIZE - \
+	sizeof(zio_eck_t)) / sizeof(blkptr_t))
+#define	SPA_GBH_FILLER		((SPA_GANGBLOCKSIZE - \
+	sizeof(zio_eck_t) - \
+	(SPA_GBH_NBLKPTRS * sizeof(blkptr_t))) /\
+	sizeof(uint64_t))
+
+#define	ZIO_GET_IOSIZE(zio)	\
+	(BP_IS_GANG((zio)->io_bp) ? \
+	SPA_GANGBLOCKSIZE : BP_GET_PSIZE((zio)->io_bp))
+
+typedef struct zio_gbh {
+	blkptr_t		zg_blkptr[SPA_GBH_NBLKPTRS];
+	uint64_t		zg_filler[SPA_GBH_FILLER];
+	zio_eck_t		zg_tail;
+} zio_gbh_phys_t;
+
+enum zio_checksum {
+	ZIO_CHECKSUM_INHERIT = 0,
+	ZIO_CHECKSUM_ON,
+	ZIO_CHECKSUM_OFF,
+	ZIO_CHECKSUM_LABEL,
+	ZIO_CHECKSUM_GANG_HEADER,
+	ZIO_CHECKSUM_ZILOG,
+	ZIO_CHECKSUM_FLETCHER_2,
+	ZIO_CHECKSUM_FLETCHER_4,
+	ZIO_CHECKSUM_SHA256,
+	ZIO_CHECKSUM_ZILOG2,
+	ZIO_CHECKSUM_FUNCTIONS
+};
+
+#define	ZIO_CHECKSUM_ON_VALUE	ZIO_CHECKSUM_FLETCHER_2
+#define	ZIO_CHECKSUM_DEFAULT	ZIO_CHECKSUM_ON
+
+enum zio_compress {
+	ZIO_COMPRESS_INHERIT = 0,
+	ZIO_COMPRESS_ON,
+	ZIO_COMPRESS_OFF,
+	ZIO_COMPRESS_LZJB,
+	ZIO_COMPRESS_EMPTY,
+	ZIO_COMPRESS_GZIP1,
+	ZIO_COMPRESS_GZIP2,
+	ZIO_COMPRESS_GZIP3,
+	ZIO_COMPRESS_GZIP4,
+	ZIO_COMPRESS_GZIP5,
+	ZIO_COMPRESS_GZIP6,
+	ZIO_COMPRESS_GZIP7,
+	ZIO_COMPRESS_GZIP8,
+	ZIO_COMPRESS_GZIP9,
+	ZIO_COMPRESS_FUNCTIONS
+};
+
+#endif	/* _ZIO_H */
diff --git a/qemu/roms/u-boot/include/zfs/zio_checksum.h b/qemu/roms/u-boot/include/zfs/zio_checksum.h
new file mode 100644
index 000000000..0c9b17a97
--- /dev/null
+++ b/qemu/roms/u-boot/include/zfs/zio_checksum.h
@@ -0,0 +1,38 @@
+/*
+ *  GRUB  --  GRand Unified Bootloader
+ *  Copyright (C) 1999,2000,2001,2002,2003,2004  Free Software Foundation, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/*
+ * Copyright 2010 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _SYS_ZIO_CHECKSUM_H
+#define	_SYS_ZIO_CHECKSUM_H
+
+/*
+ * Signature for checksum functions.
+ */
+typedef void zio_checksum_t(const void *data, uint64_t size,
+			    zfs_endian_t endian, zio_cksum_t *zcp);
+
+/*
+ * Information about each checksum function.
+ */
+typedef struct zio_checksum_info {
+	zio_checksum_t	*ci_func; /* checksum function for each byteorder */
+	int		ci_correctable;	/* number of correctable bits	*/
+	int		ci_eck;		/* uses zio embedded checksum? */
+	char		*ci_name;	/* descriptive name */
+} zio_checksum_info_t;
+
+extern void zio_checksum_SHA256(const void *, uint64_t,
+				 zfs_endian_t endian, zio_cksum_t *);
+extern void fletcher_2_endian(const void *, uint64_t, zfs_endian_t endian,
+			zio_cksum_t *);
+extern void fletcher_4_endian(const void *, uint64_t, zfs_endian_t endian,
+			zio_cksum_t *);
+
+#endif	/* _SYS_ZIO_CHECKSUM_H */
diff --git a/qemu/roms/u-boot/include/zfs_common.h b/qemu/roms/u-boot/include/zfs_common.h
new file mode 100644
index 000000000..3bd575ef5
--- /dev/null
+++ b/qemu/roms/u-boot/include/zfs_common.h
@@ -0,0 +1,104 @@
+/*
+ * ZFS filesystem port for Uboot by
+ * Jorgen Lundman <lundman at lundman.net>
+ *
+ * zfsfs support
+ * made from existing GRUB Sources by Sun, GNU and others.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ZFS_COMMON__
+#define __ZFS_COMMON__
+
+#define SECTOR_SIZE			0x200
+#define SECTOR_BITS			9
+
+
+typedef enum zfs_endian {
+	UNKNOWN_ENDIAN = -2,
+	LITTLE_ENDIAN = -1,
+	BIG_ENDIAN = 0
+} zfs_endian_t;
+
+
+/* Endian macros. */
+#define zfs_to_cpu16(x, a) (((a) == BIG_ENDIAN) ? be16_to_cpu(x) \
+								: le16_to_cpu(x))
+#define cpu_to_zfs16(x, a) (((a) == BIG_ENDIAN) ? cpu_to_be16(x) \
+								: cpu_to_le16(x))
+
+#define zfs_to_cpu32(x, a) (((a) == BIG_ENDIAN) ? be32_to_cpu(x) \
+								: le32_to_cpu(x))
+#define cpu_to_zfs32(x, a) (((a) == BIG_ENDIAN) ? cpu_to_be32(x) \
+								: cpu_to_le32(x))
+
+#define zfs_to_cpu64(x, a) (((a) == BIG_ENDIAN) ? be64_to_cpu(x) \
+								: le64_to_cpu(x))
+#define cpu_to_zfs64(x, a) (((a) == BIG_ENDIAN) ? cpu_to_be64(x) \
+								: cpu_to_le64(x))
+
+
+enum zfs_errors {
+	ZFS_ERR_NONE = 0,
+	ZFS_ERR_NOT_IMPLEMENTED_YET = -1,
+	ZFS_ERR_BAD_FS = -2,
+	ZFS_ERR_OUT_OF_MEMORY = -3,
+	ZFS_ERR_FILE_NOT_FOUND = -4,
+	ZFS_ERR_BAD_FILE_TYPE = -5,
+	ZFS_ERR_OUT_OF_RANGE = -6,
+};
+
+struct zfs_filesystem {
+
+	/* Block Device Descriptor */
+	block_dev_desc_t *dev_desc;
+};
+
+struct device_s {
+	uint64_t part_length;
+};
+typedef struct device_s *device_t;
+
+struct zfs_file {
+	device_t device;
+	uint64_t size;
+	void *data;
+	uint64_t offset;
+};
+
+typedef struct zfs_file *zfs_file_t;
+
+struct zfs_dirhook_info {
+	int dir;
+	int mtimeset;
+	time_t mtime;
+	time_t mtime2;
+};
+
+
+
+
+struct zfs_filesystem *zfsget_fs(void);
+int zfs_open(zfs_file_t, const char *filename);
+uint64_t zfs_read(zfs_file_t, char *buf, uint64_t len);
+struct zfs_data *zfs_mount(device_t);
+int zfs_close(zfs_file_t);
+int zfs_ls(device_t dev, const char *path,
+		   int (*hook) (const char *, const struct zfs_dirhook_info *));
+int zfs_devread(int sector, int byte_offset, int byte_len, char *buf);
+void zfs_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info);
+void zfs_unmount(struct zfs_data *data);
+int lzjb_decompress(void *, void *, uint32_t, uint32_t);
+#endif
diff --git a/qemu/roms/u-boot/include/zynqpl.h b/qemu/roms/u-boot/include/zynqpl.h
new file mode 100644
index 000000000..8a9ec3297
--- /dev/null
+++ b/qemu/roms/u-boot/include/zynqpl.h
@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright 2012-2013, Xilinx, Michal Simek
+ *
+ * (C) Copyright 2012
+ * Joe Hershberger <joe.hershberger@ni.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ZYNQPL_H_
+#define _ZYNQPL_H_
+
+#include <xilinx.h>
+
+extern struct xilinx_fpga_op zynq_op;
+
+#define XILINX_ZYNQ_7010	0x2
+#define XILINX_ZYNQ_7015	0x1b
+#define XILINX_ZYNQ_7020	0x7
+#define XILINX_ZYNQ_7030	0xc
+#define XILINX_ZYNQ_7045	0x11
+#define XILINX_ZYNQ_7100	0x16
+
+/* Device Image Sizes */
+#define XILINX_XC7Z010_SIZE	16669920/8
+#define XILINX_XC7Z015_SIZE	28085344/8
+#define XILINX_XC7Z020_SIZE	32364512/8
+#define XILINX_XC7Z030_SIZE	47839328/8
+#define XILINX_XC7Z045_SIZE	106571232/8
+#define XILINX_XC7Z100_SIZE	139330784/8
+
+/* Descriptor Macros */
+#define XILINX_XC7Z010_DESC(cookie) \
+{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, &zynq_op, "7z010" }
+
+#define XILINX_XC7Z015_DESC(cookie) \
+{ xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, &zynq_op, "7z015" }
+
+#define XILINX_XC7Z020_DESC(cookie) \
+{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, &zynq_op, "7z020" }
+
+#define XILINX_XC7Z030_DESC(cookie) \
+{ xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, &zynq_op, "7z030" }
+
+#define XILINX_XC7Z045_DESC(cookie) \
+{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, &zynq_op, "7z045" }
+
+#define XILINX_XC7Z100_DESC(cookie) \
+{ xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, &zynq_op, "7z100" }
+
+#endif /* _ZYNQPL_H_ */