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authorYang Zhang <yang.z.zhang@intel.com>2015-08-28 09:58:54 +0800
committerYang Zhang <yang.z.zhang@intel.com>2015-09-01 12:44:00 +0800
commite44e3482bdb4d0ebde2d8b41830ac2cdb07948fb (patch)
tree66b09f592c55df2878107a468a91d21506104d3f /qemu/roms/u-boot/include/sja1000.h
parent9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (diff)
Add qemu 2.4.0
Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5 Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>
Diffstat (limited to 'qemu/roms/u-boot/include/sja1000.h')
-rw-r--r--qemu/roms/u-boot/include/sja1000.h44
1 files changed, 44 insertions, 0 deletions
diff --git a/qemu/roms/u-boot/include/sja1000.h b/qemu/roms/u-boot/include/sja1000.h
new file mode 100644
index 000000000..07cd9e371
--- /dev/null
+++ b/qemu/roms/u-boot/include/sja1000.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright 2009, Matthias Fuchs <matthias.fuchs@esd.eu>
+ *
+ * SJA1000 register layout for basic CAN mode
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SJA1000_H_
+#define _SJA1000_H_
+
+/*
+ * SJA1000 register layout in basic can mode
+ */
+struct sja1000_basic_s {
+ u8 cr;
+ u8 cmr;
+ u8 sr;
+ u8 ir;
+ u8 ac;
+ u8 am;
+ u8 btr0;
+ u8 btr1;
+ u8 oc;
+ u8 txb[10];
+ u8 rxb[10];
+ u8 unused;
+ u8 cdr;
+};
+
+/* control register */
+#define CR_RR 0x01
+
+/* output control register */
+#define OC_MODE0 0x01
+#define OC_MODE1 0x02
+#define OC_POL0 0x04
+#define OC_TN0 0x08
+#define OC_TP0 0x10
+#define OC_POL1 0x20
+#define OC_TN1 0x40
+#define OC_TP1 0x80
+
+#endif